[..]
- P
- P0
- P0SEG
- P0_ACT_LED_EN
- P0_AT_BYPASS
- P0_CONFIG
- P0_CON_BCLR
- P0_CON_IN_RES_FORCE_NRDY
- P0_CON_IN_RES_FORCE_STALL
- P0_CON_IN_RES_MASK
- P0_CON_IN_RES_NORMAL
- P0_CON_OT_RES_FORCE_NRDY
- P0_CON_OT_RES_FORCE_STALL
- P0_CON_OT_RES_MASK
- P0_CON_OT_RES_NORMAL
- P0_CON_RES_WEN
- P0_CON_ST_RES_FORCE_NRDY
- P0_CON_ST_RES_FORCE_STALL
- P0_CON_ST_RES_MASK
- P0_CON_ST_RES_NORMAL
- P0_CP_DET
- P0_CP_POD
- P0_CP_POD_EN
- P0_DISABLE
- P0_DSP_RESET_LBN
- P0_DSP_RESET_WIDTH
- P0_EN_1V0X_LBN
- P0_EN_1V0X_WIDTH
- P0_EN_1V2_LBN
- P0_EN_1V2_WIDTH
- P0_EN_2V5_LBN
- P0_EN_2V5_WIDTH
- P0_EN_3V3X_LBN
- P0_EN_3V3X_WIDTH
- P0_EN_5V_LBN
- P0_EN_5V_WIDTH
- P0_IN
- P0_INT_ALL_BITS
- P0_INT_BFRDY
- P0_INT_ERDY
- P0_INT_FLOW
- P0_INT_NRDY
- P0_INT_RCVNL
- P0_INT_SETUP
- P0_INT_STALL
- P0_INT_STSED
- P0_INT_STSST
- P0_INVERT
- P0_IPDIPDMSYNTH
- P0_IPDRXL
- P0_IPDTXL
- P0_IRQ_OFF
- P0_IRST_HARD_SYNTH
- P0_IRST_HARD_TXRX
- P0_IRST_POR
- P0_MOD_DIR
- P0_MP_SW
- P0_OUT
- P0_PATIAL
- P0_PHY_CALI
- P0_PHY_READY
- P0_PHY_SIG_DET
- P0_SHORTEN_JTAG_LBN
- P0_SHORTEN_JTAG_WIDTH
- P0_SIZE
- P0_SLUMBER
- P0_X_TRST_LBN
- P0_X_TRST_WIDTH
- P1
- P1024e
- P1024o
- P10_1610_GPIO22
- P1100_FIRMWARE
- P11_1610_CF_CD2
- P128e
- P128o
- P15_1610_SPIF_CS3
- P15_1610_UWIRE_CS3
- P16ST_HIGH_Z
- P16ST_PULL_DOWN
- P16ST_PULL_MASK
- P16ST_PULL_UP
- P16V_VOL
- P16_32x32_16x16
- P16_32x32_8x16
- P16_ADDR_SURF
- P16e
- P16e_s
- P16o
- P16o_s
- P17V_AC97_OUT_MASTER_VOL_H
- P17V_AC97_OUT_MASTER_VOL_L
- P17V_AUDIO_OUT_ENABLE
- P17V_CAPTURE_FIFO_BASE
- P17V_CAPTURE_FIFO_INDEX
- P17V_CAPTURE_FIFO_PTR
- P17V_CAPTURE_FIFO_SIZE
- P17V_CAPTURE_VOL_H
- P17V_CAPTURE_VOL_L
- P17V_I2C_0
- P17V_I2C_1
- P17V_I2C_ADDR
- P17V_I2S_CHANNEL_SWAP_PHASE_INVERSE
- P17V_I2S_OUT_MASTER_VOL_H
- P17V_I2S_OUT_MASTER_VOL_L
- P17V_I2S_SRC_SEL
- P17V_MIXER_AC97_10K1_VOL_H
- P17V_MIXER_AC97_10K1_VOL_L
- P17V_MIXER_AC97_ENABLE
- P17V_MIXER_AC97_P17V_VOL_H
- P17V_MIXER_AC97_P17V_VOL_L
- P17V_MIXER_AC97_SRP_REC_VOL_H
- P17V_MIXER_AC97_SRP_REC_VOL_L
- P17V_MIXER_ATT
- P17V_MIXER_I2S_10K1_VOL_H
- P17V_MIXER_I2S_10K1_VOL_L
- P17V_MIXER_I2S_ENABLE
- P17V_MIXER_I2S_P17V_VOL_H
- P17V_MIXER_I2S_P17V_VOL_L
- P17V_MIXER_I2S_SRP_REC_VOL_H
- P17V_MIXER_I2S_SRP_REC_VOL_L
- P17V_MIXER_SPDIF_ENABLE
- P17V_MIXER_Spdif_10K1_VOL_H
- P17V_MIXER_Spdif_10K1_VOL_L
- P17V_MIXER_Spdif_P17V_VOL_H
- P17V_MIXER_Spdif_P17V_VOL_L
- P17V_MIXER_Spdif_SRP_REC_VOL_H
- P17V_MIXER_Spdif_SRP_REC_VOL_L
- P17V_PB_CHN_SEL
- P17V_PLAYBACK_FIFO_PTR
- P17V_SE_SLOT_SEL_H
- P17V_SE_SLOT_SEL_L
- P17V_SOFT_RESET_SRP_MIXER
- P17V_SPDIF_CHANNEL_SWAP_PHASE_INVERSE
- P17V_SPDIF_OUT_MASTER_VOL_H
- P17V_SPDIF_OUT_MASTER_VOL_L
- P17V_SPI
- P17V_SRCSel
- P17V_SRP_BYPASS
- P17V_SRP_P17V_ESR
- P17V_SRP_RECORD_SRR
- P17V_SRP_REC_ESR
- P17V_START_AUDIO
- P17V_START_CAPTURE
- P18
- P18_1610_GPIO3
- P18_DESC
- P19
- P19_1710_MMC_CMDDIR
- P19_DESC
- P1A_B
- P1C
- P1CR_ADV_100BT_FDX
- P1CR_ADV_100BT_HDX
- P1CR_ADV_10BT_FDX
- P1CR_ADV_10BT_HDX
- P1CR_ADV_FLOW
- P1CR_AUTONEGEN
- P1CR_DISAUTOMDIX
- P1CR_FORCE100
- P1CR_FORCEFDX
- P1CR_FORCEMDIX
- P1CR_LEDOFF
- P1CR_RESTARTAN
- P1CR_TXIDS
- P1CTL
- P1CTL_NON_DRIVING
- P1CTL_SOFT_RESET
- P1D_E_F
- P1ELEN_MASK
- P1ELEN_SHIFT
- P1FLEN_MASK
- P1FLEN_SHIFT
- P1G
- P1G_21R2
- P1K_SIZE
- P1MODE
- P1MSEL0_0
- P1MSEL0_1
- P1MSEL10_0
- P1MSEL10_1
- P1MSEL11_0
- P1MSEL11_1
- P1MSEL12_0
- P1MSEL12_1
- P1MSEL13_0
- P1MSEL13_1
- P1MSEL14_0
- P1MSEL14_1
- P1MSEL15_0
- P1MSEL15_1
- P1MSEL1_0
- P1MSEL1_1
- P1MSEL2_0
- P1MSEL2_1
- P1MSEL3_0
- P1MSEL3_1
- P1MSEL4_0
- P1MSEL4_1
- P1MSEL5_0
- P1MSEL5_1
- P1MSEL6_0
- P1MSEL6_1
- P1MSEL7_0
- P1MSEL7_1
- P1MSEL8_0
- P1MSEL8_1
- P1MSEL9_0
- P1MSEL9_1
- P1SEG
- P1SEGADDR
- P1SR_AN_DONE
- P1SR_HP_MDIX
- P1SR_LINK_GOOD
- P1SR_OP_100M
- P1SR_OP_FDX
- P1SR_OP_MDI
- P1SR_PNTR_100BT_FDX
- P1SR_PNTR_100BT_HDX
- P1SR_PNTR_10BT_FDX
- P1SR_PNTR_10BT_HDX
- P1SR_PNTR_FLOW
- P1SR_REV_POL
- P1_A
- P1_ACT_LED_EN
- P1_AFE_PWD_LBN
- P1_AFE_PWD_WIDTH
- P1_AT_BYPASS
- P1_CONFIG
- P1_CP_DET
- P1_CP_POD
- P1_CP_POD_EN
- P1_DISABLE
- P1_DSP_PWD25_LBN
- P1_DSP_PWD25_WIDTH
- P1_GRP_4030
- P1_GRP_6030
- P1_IN
- P1_INVERT
- P1_IPDIPDMSYNTH
- P1_IPDRXL
- P1_IPDTXL
- P1_IRST_HARD_SYNTH
- P1_IRST_HARD_TXRX
- P1_IRST_POR
- P1_MADDR0
- P1_MADDR1
- P1_MADDR2
- P1_MDATA0
- P1_MDATA1
- P1_MDATA2
- P1_MDATA3
- P1_MP_SW
- P1_OUT
- P1_PATIAL
- P1_PHY_CALI
- P1_PHY_READY
- P1_PHY_SIG_DET
- P1_RADDR0
- P1_RADDR1
- P1_RDATA0
- P1_RDATA1
- P1_RDATA2
- P1_RDATA3
- P1_RESERVED_LBN
- P1_RESERVED_WIDTH
- P1_RRDWR
- P1_SIZE
- P1_SLUMBER
- P1_SPARE_LBN
- P1_SPARE_WIDTH
- P1_START
- P1e
- P1e_s
- P1o
- P1o_s
- P2
- P20
- P2048e
- P2048o
- P20_1610_GPIO4
- P20_1610_SPIF_DIN
- P20_1710_MMC_DATDIR0
- P20_DESC
- P21
- P21_DESC
- P22
- P22_DESC
- P23
- P24
- P24_CDSP_MIC20_SEL_MASK
- P24_CDSP_MIC38_SEL_MASK
- P24_CDSP_MICS_SEL_MASK
- P25
- P256e
- P256o
- P26
- P2A0_RG_INTR_EN
- P2A1_RG_INTR_CAL
- P2A1_RG_INTR_CAL_VAL
- P2A1_RG_TERM_SEL
- P2A1_RG_TERM_SEL_VAL
- P2A1_RG_VRT_SEL
- P2A1_RG_VRT_SEL_VAL
- P2A5_RG_HSTX_SRCAL_EN
- P2A5_RG_HSTX_SRCTRL
- P2A5_RG_HSTX_SRCTRL_VAL
- P2A6_RG_BC11_SW_EN
- P2A6_RG_OTG_VBUSCMP_EN
- P2A_HI_PRIORITY
- P2A_INT_ENABLE
- P2A_INT_ENA_ALL
- P2A_INT_STATUS
- P2A_INT_STS_ALL
- P2A_REGION_COUNT
- P2C_DTM0_PART_MASK
- P2C_FORCE_DATAIN
- P2C_FORCE_DM_PULLDOWN
- P2C_FORCE_DP_PULLDOWN
- P2C_FORCE_IDDIG
- P2C_FORCE_SUSPENDM
- P2C_FORCE_TERMSEL
- P2C_FORCE_UART_EN
- P2C_FORCE_XCVRSEL
- P2C_RG_AVALID
- P2C_RG_CHGDT_EN
- P2C_RG_DATAIN
- P2C_RG_DATAIN_VAL
- P2C_RG_DMPULLDOWN
- P2C_RG_DPPULLDOWN
- P2C_RG_IDDIG
- P2C_RG_SESSEND
- P2C_RG_SIF_U2PLL_FORCE_ON
- P2C_RG_SUSPENDM
- P2C_RG_TERMSEL
- P2C_RG_UART_EN
- P2C_RG_USB20_GPIO_CTL
- P2C_RG_VBUSVALID
- P2C_RG_XCVRSEL
- P2C_RG_XCVRSEL_VAL
- P2C_U2_GPIO_CTR_MSK
- P2C_USB20_GPIO_MODE
- P2D_FORCE_IDDIG
- P2D_RG_AVALID
- P2D_RG_IDDIG
- P2D_RG_SESSEND
- P2D_RG_VBUSVALID
- P2ELEN_MASK
- P2ELEN_SHIFT
- P2EN_MASK
- P2EN_SHIFT
- P2FLEN_MASK
- P2FLEN_SHIFT
- P2F_RG_CYCLECNT
- P2F_RG_CYCLECNT_VAL
- P2F_RG_FRCK_EN
- P2F_RG_FREQDET_EN
- P2F_RG_MONCLK_SEL
- P2F_RG_MONCLK_SEL_VAL
- P2F_USB_FM_VALID
- P2K
- P2MSEL0_0
- P2MSEL0_1
- P2MSEL10_0
- P2MSEL10_1
- P2MSEL11_0
- P2MSEL11_1
- P2MSEL12_0
- P2MSEL12_1
- P2MSEL13_0
- P2MSEL13_1
- P2MSEL14_0
- P2MSEL14_1
- P2MSEL15_0
- P2MSEL15_1
- P2MSEL1_0
- P2MSEL1_1
- P2MSEL2_0
- P2MSEL2_1
- P2MSEL3_0
- P2MSEL3_1
- P2MSEL4_0
- P2MSEL4_1
- P2MSEL5_0
- P2MSEL5_1
- P2MSEL6_0
- P2MSEL6_1
- P2MSEL7_0
- P2MSEL7_1
- P2MSEL8_0
- P2MSEL8_1
- P2MSEL9_0
- P2MSEL9_1
- P2M_LIMIT
- P2M_MID_PER_PAGE
- P2M_PER_PAGE
- P2M_TOP_PER_PAGE
- P2M_TYPE_IDENTITY
- P2M_TYPE_MISSING
- P2M_TYPE_PFN
- P2M_TYPE_UNKNOWN
- P2P
- P2PAPI_BSSCFG_CONNECTION
- P2PAPI_BSSCFG_DEVICE
- P2PAPI_BSSCFG_MAX
- P2PAPI_BSSCFG_PRIMARY
- P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS
- P2PAPI_SCAN_DWELL_TIME_MS
- P2PAPI_SCAN_HOME_TIME_MS
- P2PAPI_SCAN_NPROBES
- P2PAPI_SCAN_NPROBS_TIME_MS
- P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS
- P2PELEM_ATTR_ID
- P2PLL_CNTL
- P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN
- P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK
- P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC
- P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK
- P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET
- P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK
- P2PLL_CNTL__P2PLL_FBCLK_SEL
- P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK
- P2PLL_CNTL__P2PLL_PCP_MASK
- P2PLL_CNTL__P2PLL_PDC_MASK
- P2PLL_CNTL__P2PLL_PVG_MASK
- P2PLL_CNTL__P2PLL_REFCLK_SEL
- P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK
- P2PLL_CNTL__P2PLL_RESET
- P2PLL_CNTL__P2PLL_RESET_MASK
- P2PLL_CNTL__P2PLL_SLEEP
- P2PLL_CNTL__P2PLL_SLEEP_MASK
- P2PLL_CNTL__P2PLL_TCPOFF
- P2PLL_CNTL__P2PLL_TCPOFF_MASK
- P2PLL_CNTL__P2PLL_TST_EN
- P2PLL_CNTL__P2PLL_TST_EN_MASK
- P2PLL_CNTL__P2PLL_TVCOMAX
- P2PLL_CNTL__P2PLL_TVCOMAX_MASK
- P2PLL_DIV_0
- P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R
- P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK
- P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W
- P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK
- P2PLL_DIV_0__P2PLL_FB_DIV_MASK
- P2PLL_DIV_0__P2PLL_POST_DIV_MASK
- P2PLL_REF_DIV
- P2PLL_TURNOFF
- P2POUI
- P2PSD_ACTION_CATEGORY
- P2PSD_ACTION_ID_GAS_CREQ
- P2PSD_ACTION_ID_GAS_CRESP
- P2PSD_ACTION_ID_GAS_IREQ
- P2PSD_ACTION_ID_GAS_IRESP
- P2P_AF_CATEGORY
- P2P_AF_DWELL_TIME
- P2P_AF_FRM_SCAN_MAX_WAIT
- P2P_AF_GO_DISC_REQ
- P2P_AF_LONG_DWELL_TIME
- P2P_AF_MAX_WAIT_TIME
- P2P_AF_MED_DWELL_TIME
- P2P_AF_MIN_DWELL_TIME
- P2P_AF_NOTICE_OF_ABSENCE
- P2P_AF_PRESENCE_REQ
- P2P_AF_PRESENCE_RSP
- P2P_AF_TX_MAX_RETRY
- P2P_AP_P2P_CH_SWITCH_PROCESS_WK
- P2P_ATTR_CAPABILITY
- P2P_ATTR_CH_LIST
- P2P_ATTR_CONF_TIMEOUT
- P2P_ATTR_DEVICE_ID
- P2P_ATTR_DEVICE_INFO
- P2P_ATTR_EX_LISTEN_TIMING
- P2P_ATTR_GO_INTENT
- P2P_ATTR_GROUP_BSSID
- P2P_ATTR_GROUP_ID
- P2P_ATTR_GROUP_INFO
- P2P_ATTR_INTENTED_IF_ADDR
- P2P_ATTR_INTERFACE
- P2P_ATTR_INVITATION_FLAGS
- P2P_ATTR_LISTEN_CH
- P2P_ATTR_MANAGEABILITY
- P2P_ATTR_MINOR_REASON_CODE
- P2P_ATTR_NOA
- P2P_ATTR_OPERATING_CH
- P2P_ATTR_STATUS
- P2P_CHANNEL_SYNC_RETRY
- P2P_CONCURRENT_GO_NEGO_TIMEOUT
- P2P_CONCURRENT_INVITE_TIMEOUT
- P2P_CONCURRENT_PROVISION_TIMEOUT
- P2P_DEFAULT_BI
- P2P_DEFAULT_CTWIN
- P2P_DEFAULT_SLEEP_TIME_VSDB
- P2P_DEVCAP_CLIENT_DISCOVERABILITY
- P2P_DEVCAP_CONCURRENT_OPERATION
- P2P_DEVCAP_DEVICE_LIMIT
- P2P_DEVCAP_INFRA_MANAGED
- P2P_DEVCAP_INVITATION_PROC
- P2P_DEVCAP_SERVICE_DISCOVERY
- P2P_DEVDISC_REQ
- P2P_DEVDISC_RESP
- P2P_DMG_SOCIAL_CHANNEL
- P2P_FINDPHASE_EX_FULL
- P2P_FINDPHASE_EX_MAX
- P2P_FINDPHASE_EX_NONE
- P2P_FINDPHASE_EX_SOCIAL_FIRST
- P2P_FINDPHASE_EX_SOCIAL_LAST
- P2P_FIND_PHASE_WK
- P2P_FLAG_CAPABILITIES_REQ
- P2P_FLAG_HMODEL_REQ
- P2P_FLAG_MACADDR_REQ
- P2P_GOT_WPSINFO_PBC
- P2P_GOT_WPSINFO_PEER_DISPLAY_PIN
- P2P_GOT_WPSINFO_SELF_DISPLAY_PIN
- P2P_GO_DISC_REQUEST
- P2P_GO_NEGO_CONF
- P2P_GO_NEGO_REQ
- P2P_GO_NEGO_RESP
- P2P_GO_NEGO_TIMEOUT
- P2P_GO_NOA_DECOUPLE_INIT_SCAN
- P2P_GRPCAP_CROSS_CONN
- P2P_GRPCAP_GO
- P2P_GRPCAP_GROUP_FORMATION
- P2P_GRPCAP_GROUP_LIMIT
- P2P_GRPCAP_INTRABSS
- P2P_GRPCAP_PERSISTENT_GROUP
- P2P_GRPCAP_PERSISTENT_RECONN
- P2P_INVALID_CHANNEL
- P2P_INVITATION_FLAGS_PERSISTENT
- P2P_INVITE_TIMEOUT
- P2P_INVIT_REQ
- P2P_INVIT_RESP
- P2P_INV_REQ
- P2P_INV_RSP
- P2P_LOOP
- P2P_MAX_INTENT
- P2P_MAX_NOA_NUM
- P2P_MAX_PERSISTENT_GROUP_NUM
- P2P_MAX_REG_CLASSES
- P2P_MAX_REG_CLASS_CHANNELS
- P2P_MODES
- P2P_MODE_CLIENT
- P2P_MODE_DEVICE
- P2P_MODE_DISABLE
- P2P_MODE_GO
- P2P_NOTICE_OF_ABSENCE
- P2P_NO_WPSINFO
- P2P_OUI
- P2P_OUI_LEN
- P2P_PAF_DEVDIS_REQ
- P2P_PAF_DEVDIS_RSP
- P2P_PAF_GON_CONF
- P2P_PAF_GON_REQ
- P2P_PAF_GON_RSP
- P2P_PAF_INVITE_REQ
- P2P_PAF_INVITE_RSP
- P2P_PAF_PROVDIS_REQ
- P2P_PAF_PROVDIS_RSP
- P2P_PAF_SUBTYPE_INVALID
- P2P_PRESENCE_REQUEST
- P2P_PRESENCE_RESPONSE
- P2P_PRE_TX_INVITEREQ_PROCESS_WK
- P2P_PRE_TX_NEGOREQ_PROCESS_WK
- P2P_PRE_TX_PROVDISC_PROCESS_WK
- P2P_PRIVATE_IOCTL_SET_LEN
- P2P_PROTO_WK_CID
- P2P_PROTO_WK_ID
- P2P_PROVISIONING_SCAN_CNT
- P2P_PROVISION_DISC_REQ
- P2P_PROVISION_DISC_RESP
- P2P_PROVISION_TIMEOUT
- P2P_PS_ALLSTASLEEP
- P2P_PS_CTWINDOW
- P2P_PS_CTWPeriod_t
- P2P_PS_DISABLE
- P2P_PS_ENABLE
- P2P_PS_MIX
- P2P_PS_NOA
- P2P_PS_NONE
- P2P_PS_Offload_t
- P2P_PS_SCAN
- P2P_PS_SCAN_DONE
- P2P_PS_WK_CID
- P2P_PUB_ACTION_ACTION
- P2P_PUB_ACTION_SUBTYPE
- P2P_PUB_AF_ACTION
- P2P_PUB_AF_CATEGORY
- P2P_RESET_SCAN_CH
- P2P_RESTORE_STATE_WK
- P2P_ROLE
- P2P_ROLE_CLIENT
- P2P_ROLE_DEVICE
- P2P_ROLE_DISABLE
- P2P_ROLE_GO
- P2P_RO_CH_WK
- P2P_SEARCH_DURATION_MS
- P2P_STATE
- P2P_STATE_FIND_PHASE_LISTEN
- P2P_STATE_FIND_PHASE_SEARCH
- P2P_STATE_GONEGO_FAIL
- P2P_STATE_GONEGO_ING
- P2P_STATE_GONEGO_OK
- P2P_STATE_IDLE
- P2P_STATE_LISTEN
- P2P_STATE_NONE
- P2P_STATE_PROVISIONING_DONE
- P2P_STATE_PROVISIONING_ING
- P2P_STATE_RECV_INVITE_REQ_DISMATCH
- P2P_STATE_RECV_INVITE_REQ_GO
- P2P_STATE_RECV_INVITE_REQ_JOIN
- P2P_STATE_RECV_INVITE_REQ_MATCH
- P2P_STATE_RX_INFOR_NOREADY
- P2P_STATE_RX_INVITE_RESP_FAIL
- P2P_STATE_RX_INVITE_RESP_OK
- P2P_STATE_RX_PROVISION_DIS_REQ
- P2P_STATE_RX_PROVISION_DIS_RSP
- P2P_STATE_SCAN
- P2P_STATE_TX_INFOR_NOREADY
- P2P_STATE_TX_INVITE_REQ
- P2P_STATE_TX_PROVISION_DIS_REQ
- P2P_STATUS_FAIL_BOTH_GOINTENT_15
- P2P_STATUS_FAIL_INCOMPATIBLE_PARAM
- P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION
- P2P_STATUS_FAIL_INFO_UNAVAILABLE
- P2P_STATUS_FAIL_INVALID_PARAM
- P2P_STATUS_FAIL_LIMIT_REACHED
- P2P_STATUS_FAIL_NO_COMMON_CH
- P2P_STATUS_FAIL_PREVOUS_PROTO_ERR
- P2P_STATUS_FAIL_REQUEST_UNABLE
- P2P_STATUS_FAIL_UNKNOWN_P2PGROUP
- P2P_STATUS_FAIL_USER_REJECT
- P2P_STATUS_SUCCESS
- P2P_TX_PRESCAN_TIMEOUT
- P2P_VER
- P2P_WILDCARD_SSID
- P2P_WILDCARD_SSID_LEN
- P2P_WPSINFO
- P2SB_ADDR_OFF
- P2SB_BUSY
- P2SB_DATA_OFF
- P2SB_DEVFN
- P2SB_EADD_OFF
- P2SB_HIDE_OFF
- P2SB_READ
- P2SB_ROUT_OFF
- P2SB_STAT_OFF
- P2SB_WRITE
- P2SEG
- P2SEGADDR
- P2SM_MASK
- P2SM_SHIFT
- P2T_CTRL
- P2T_DC_PKT_EN
- P2U_PERIODIC_EQ_CTRL_GEN3
- P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN
- P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN
- P2U_PERIODIC_EQ_CTRL_GEN4
- P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN
- P2U_RX_DEBOUNCE_TIME
- P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK
- P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL
- P2WI_CCR
- P2WI_CCR_CLK_DIV
- P2WI_CCR_MAX_CLK_DIV
- P2WI_CCR_SDA_OUT_DELAY
- P2WI_CTRL
- P2WI_CTRL_ABORT_TRANS
- P2WI_CTRL_GLOBAL_INT_ENB
- P2WI_CTRL_SOFT_RST
- P2WI_CTRL_START_TRANS
- P2WI_DADDR0
- P2WI_DADDR1
- P2WI_DATA0
- P2WI_DATA1
- P2WI_DLEN
- P2WI_DLEN_DATA_LENGTH
- P2WI_DLEN_READ
- P2WI_INTE
- P2WI_INTS
- P2WI_INTS_LOAD_BSY
- P2WI_INTS_TRANS_ERR
- P2WI_INTS_TRANS_ERR_ID
- P2WI_INTS_TRANS_OVER
- P2WI_LCR
- P2WI_LCR_SCL_CTL
- P2WI_LCR_SCL_CTL_EN
- P2WI_LCR_SCL_STATE
- P2WI_LCR_SDA_CTL
- P2WI_LCR_SDA_CTL_EN
- P2WI_LCR_SDA_STATE
- P2WI_MAX_FREQ
- P2WI_PMCR
- P2WI_PMCR_PMU_DEV_ADDR
- P2WI_PMCR_PMU_INIT_DATA
- P2WI_PMCR_PMU_INIT_SEND
- P2WI_PMCR_PMU_MODE_REG
- P2_A
- P2_GRP_4030
- P2_GRP_6030
- P2_MAX_MTU
- P2_NAND_RB_GPIO_PIN
- P2_PHY_READY
- P2_START
- P2e
- P2e_s
- P2o
- P2o_s
- P3
- P32
- P320H_DEVICE_ID
- P320M_DEVICE_ID
- P320S_DEVICE_ID
- P325M_DEVICE_ID
- P32e
- P32o
- P35u
- P3A_RG_CLKDRV_AMP
- P3A_RG_CLKDRV_AMP_VAL
- P3A_RG_CLKDRV_OFF
- P3A_RG_CLKDRV_OFF_VAL
- P3A_RG_PLL_BC_PE2H
- P3A_RG_PLL_BC_PE2H_VAL
- P3A_RG_PLL_BP_PE2H
- P3A_RG_PLL_BP_PE2H_VAL
- P3A_RG_PLL_BR_PE2H
- P3A_RG_PLL_BR_PE2H_VAL
- P3A_RG_PLL_DELTA1_PE2H
- P3A_RG_PLL_DELTA1_PE2H_VAL
- P3A_RG_PLL_DELTA_PE2H
- P3A_RG_PLL_DELTA_PE2H_VAL
- P3A_RG_PLL_DIVEN_PE2H
- P3A_RG_PLL_IC_PE2H
- P3A_RG_PLL_IC_PE2H_VAL
- P3A_RG_PLL_IR_PE2H
- P3A_RG_PLL_IR_PE2H_VAL
- P3A_RG_RX_DAC_MUX
- P3A_RG_RX_DAC_MUX_VAL
- P3A_RG_TX_EIDLE_CM
- P3A_RG_TX_EIDLE_CM_VAL
- P3A_RG_XTAL_EXT_EN_U3
- P3A_RG_XTAL_EXT_EN_U3_VAL
- P3A_RG_XTAL_EXT_PE1H
- P3A_RG_XTAL_EXT_PE1H_VAL
- P3A_RG_XTAL_EXT_PE2H
- P3A_RG_XTAL_EXT_PE2H_VAL
- P3C_FORCE_IP_SW_RST
- P3C_MCU_BUS_CK_GATE_EN
- P3C_REG_IP_SW_RST
- P3C_RG_SWRST_U3_PHYD
- P3C_RG_SWRST_U3_PHYD_FORCE_EN
- P3D_RG_CDR_BIR_LTD0
- P3D_RG_CDR_BIR_LTD0_VAL
- P3D_RG_CDR_BIR_LTD1
- P3D_RG_CDR_BIR_LTD1_VAL
- P3D_RG_FWAKE_TH
- P3D_RG_FWAKE_TH_VAL
- P3D_RG_RXDET_STB2_SET
- P3D_RG_RXDET_STB2_SET_P3
- P3D_RG_RXDET_STB2_SET_P3_VAL
- P3D_RG_RXDET_STB2_SET_VAL
- P3P_LINK_SPEED_MASK
- P3P_LINK_SPEED_MHZ
- P3P_LINK_SPEED_REG
- P3P_LINK_SPEED_VAL
- P3P_MAX_MTU
- P3P_MIN_MTU
- P3SEG
- P3SEGADDR
- P3_ADDR_MAX
- P3_DESC
- P3_GRP_4030
- P3_GRP_6030
- P3_LINK_SPEED_MASK
- P3_LINK_SPEED_MHZ
- P3_LINK_SPEED_REG
- P3_LINK_SPEED_VAL
- P3_MAX_MTU
- P3_PHY_READY
- P4
- P420H_DEVICE_ID
- P420M_DEVICE_ID
- P425M_DEVICE_ID
- P44_MEMIRQ_MASTER_SLAVE_SEL_MASK
- P44_MEMIRQ_SYNCED_ALONE_SEL_MASK
- P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK
- P44_MEMIRQ_WCLK_UER_SEL_MASK
- P4D_BYT3S
- P4D_BYTES
- P4D_FLAGS
- P4D_LEVEL_MULT
- P4D_MASK
- P4D_SHIFT
- P4D_SIZE
- P4M890_FUNCTION3
- P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
- P4M890_IGA1_FIFO_HIGH_THRESHOLD
- P4M890_IGA1_FIFO_MAX_DEPTH
- P4M890_IGA1_FIFO_THRESHOLD
- P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
- P4M890_IGA2_FIFO_HIGH_THRESHOLD
- P4M890_IGA2_FIFO_MAX_DEPTH
- P4M890_IGA2_FIFO_THRESHOLD
- P4M900_FUNCTION3
- P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
- P4M900_IGA1_FIFO_HIGH_THRESHOLD
- P4M900_IGA1_FIFO_MAX_DEPTH
- P4M900_IGA1_FIFO_THRESHOLD
- P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
- P4M900_IGA2_FIFO_HIGH_THRESHOLD
- P4M900_IGA2_FIFO_MAX_DEPTH
- P4M900_IGA2_FIFO_THRESHOLD
- P4SEG
- P4SEGADDR
- P4SEG_IC_ADDR
- P4SEG_IC_DATA
- P4SEG_ITLB_ADDR
- P4SEG_ITLB_DATA
- P4SEG_OC_ADDR
- P4SEG_OC_DATA
- P4SEG_REG_BASE
- P4SEG_STORE_QUE
- P4SEG_TLB_ADDR
- P4SEG_TLB_DATA
- P4WE_HIGH_HYSTERESIS
- P4WE_HIGH_Z
- P4WE_PULL_DOWN
- P4WE_PULL_MASK
- P4WE_PULL_UP
- P4_16x16
- P4_16x32
- P4_32x32
- P4_8x16
- P4_CCCR_CASCADE
- P4_CCCR_COMPARE
- P4_CCCR_COMPLEMENT
- P4_CCCR_EDGE
- P4_CCCR_ENABLE
- P4_CCCR_ESCR_SELECT_MASK
- P4_CCCR_ESCR_SELECT_SHIFT
- P4_CCCR_ESEL
- P4_CCCR_FORCE_OVF
- P4_CCCR_OVF
- P4_CCCR_OVF_PMI_T0
- P4_CCCR_OVF_PMI_T1
- P4_CCCR_RESERVED
- P4_CCCR_THREAD_ANY
- P4_CCCR_THREAD_BOTH
- P4_CCCR_THREAD_SINGLE
- P4_CCCR_THRESHOLD
- P4_CCCR_THRESHOLD_MASK
- P4_CCCR_THRESHOLD_SHIFT
- P4_CNTR_LIMIT
- P4_CONFIG_ALIASABLE
- P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS
- P4_CONFIG_EVENT_ALIAS_MASK
- P4_CONFIG_HT
- P4_CONFIG_HT_SHIFT
- P4_CONFIG_MASK
- P4_CONFIG_MASK_CCCR
- P4_CONFIG_MASK_ESCR
- P4_DESC
- P4_ESCR_EMASK
- P4_ESCR_EMASKS
- P4_ESCR_EMASK_BIT
- P4_ESCR_EVENT
- P4_ESCR_EVENTMASK_MASK
- P4_ESCR_EVENTMASK_SHIFT
- P4_ESCR_EVENT_MASK
- P4_ESCR_EVENT_SHIFT
- P4_ESCR_MSR_BASE
- P4_ESCR_MSR_IDX
- P4_ESCR_MSR_MAX
- P4_ESCR_MSR_TABLE_ENTRY
- P4_ESCR_MSR_TABLE_SIZE
- P4_ESCR_T0_OS
- P4_ESCR_T0_USR
- P4_ESCR_T1_OS
- P4_ESCR_T1_USR
- P4_ESCR_TAG
- P4_ESCR_TAG_ENABLE
- P4_ESCR_TAG_MASK
- P4_ESCR_TAG_SHIFT
- P4_EVENTS
- P4_EVENT_128BIT_MMX_UOP
- P4_EVENT_64BIT_MMX_UOP
- P4_EVENT_B2B_CYCLES
- P4_EVENT_BNR
- P4_EVENT_BPU_FETCH_REQUEST
- P4_EVENT_BRANCH_RETIRED
- P4_EVENT_BSQ_ACTIVE_ENTRIES
- P4_EVENT_BSQ_ALLOCATION
- P4_EVENT_BSQ_CACHE_REFERENCE
- P4_EVENT_EXECUTION_EVENT
- P4_EVENT_FRONT_END_EVENT
- P4_EVENT_FSB_DATA_ACTIVITY
- P4_EVENT_GLOBAL_POWER_EVENTS
- P4_EVENT_INSTR_COMPLETED
- P4_EVENT_INSTR_RETIRED
- P4_EVENT_IOQ_ACTIVE_ENTRIES
- P4_EVENT_IOQ_ALLOCATION
- P4_EVENT_ITLB_REFERENCE
- P4_EVENT_LOAD_PORT_REPLAY
- P4_EVENT_MACHINE_CLEAR
- P4_EVENT_MEMORY_CANCEL
- P4_EVENT_MEMORY_COMPLETE
- P4_EVENT_MISPRED_BRANCH_RETIRED
- P4_EVENT_MOB_LOAD_REPLAY
- P4_EVENT_OPCODES
- P4_EVENT_PACKED_DP_UOP
- P4_EVENT_PACKED_SP_UOP
- P4_EVENT_PAGE_WALK_TYPE
- P4_EVENT_REPLAY_EVENT
- P4_EVENT_RESOURCE_STALL
- P4_EVENT_RESPONSE
- P4_EVENT_RETIRED_BRANCH_TYPE
- P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE
- P4_EVENT_SCALAR_DP_UOP
- P4_EVENT_SCALAR_SP_UOP
- P4_EVENT_SNOOP
- P4_EVENT_SSE_INPUT_ASSIST
- P4_EVENT_STORE_PORT_REPLAY
- P4_EVENT_TC_DELIVER_MODE
- P4_EVENT_TC_MISC
- P4_EVENT_TC_MS_XFER
- P4_EVENT_UOPS_RETIRED
- P4_EVENT_UOP_QUEUE_WRITES
- P4_EVENT_UOP_TYPE
- P4_EVENT_WC_BUFFER
- P4_EVENT_X87_ASSIST
- P4_EVENT_X87_FP_UOP
- P4_GEN_CACHE_EVENT
- P4_GEN_ESCR_EMASK
- P4_GEN_PEBS_BIND
- P4_OPCODE
- P4_OPCODE_ESEL
- P4_OPCODE_EVNT
- P4_OPCODE_PACK
- P4_PEBS_CONFIG_ENABLE
- P4_PEBS_CONFIG_MASK
- P4_PEBS_CONFIG_METRIC_MASK
- P4_PEBS_CONFIG_UOP_TAG
- P4_PEBS_ENABLE
- P4_PEBS_ENABLE_UOP_TAG
- P4_PEBS_METRIC
- P4_PEBS_METRIC__1stl_cache_load_miss_retired
- P4_PEBS_METRIC__2ndl_cache_load_miss_retired
- P4_PEBS_METRIC__dtlb_all_miss_retired
- P4_PEBS_METRIC__dtlb_load_miss_retired
- P4_PEBS_METRIC__dtlb_store_miss_retired
- P4_PEBS_METRIC__max
- P4_PEBS_METRIC__mob_load_replay_retired
- P4_PEBS_METRIC__none
- P4_PEBS_METRIC__split_load_retired
- P4_PEBS_METRIC__split_store_retired
- P4_PEBS_METRIC__tagged_mispred_branch
- P4e
- P4e_s
- P4o
- P4o_s
- P5
- P512e
- P512o
- P54PCI_H
- P54P_PM_OPS
- P54P_READ
- P54P_WRITE
- P54SPI_EEPROM_H
- P54SPI_H
- P54USB_H
- P54U_3887
- P54U_BRG_POWER_DOWN
- P54U_BRG_POWER_UP
- P54U_DEV_BASE
- P54U_FW_BLOCK
- P54U_INVALID_HW
- P54U_NET2280
- P54U_PIPE_3
- P54U_PIPE_4
- P54U_PIPE_BRG
- P54U_PIPE_DATA
- P54U_PIPE_DEV
- P54U_PIPE_INT
- P54U_PIPE_MGMT
- P54U_PIPE_NUMBER
- P54U_READ
- P54U_WRITE
- P54_CONTROL_TYPE_ARPTABLE
- P54_CONTROL_TYPE_BBP
- P54_CONTROL_TYPE_BT_BALANCER
- P54_CONTROL_TYPE_BT_OPTIONS
- P54_CONTROL_TYPE_BURST
- P54_CONTROL_TYPE_CCE_QUIET
- P54_CONTROL_TYPE_DCFINIT
- P54_CONTROL_TYPE_DETECTOR_VALUE
- P54_CONTROL_TYPE_EEPROM_READBACK
- P54_CONTROL_TYPE_GPIO
- P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE
- P54_CONTROL_TYPE_LED
- P54_CONTROL_TYPE_MODULATION
- P54_CONTROL_TYPE_PCS
- P54_CONTROL_TYPE_PSM
- P54_CONTROL_TYPE_PSM_STA_UNLOCK
- P54_CONTROL_TYPE_RX_KEYCACHE
- P54_CONTROL_TYPE_SCAN
- P54_CONTROL_TYPE_SETUP
- P54_CONTROL_TYPE_STAT_READBACK
- P54_CONTROL_TYPE_SYNTH_CONFIG
- P54_CONTROL_TYPE_TIM
- P54_CONTROL_TYPE_TIMER
- P54_CONTROL_TYPE_TRAP
- P54_CONTROL_TYPE_TXCANCEL
- P54_CONTROL_TYPE_TXDONE
- P54_CONTROL_TYPE_XBOW_SYNTH_CFG
- P54_CRYPTO_AESCCMP
- P54_CRYPTO_CCX_KP
- P54_CRYPTO_CCX_KPMIC
- P54_CRYPTO_CCX_WEPMIC
- P54_CRYPTO_NONE
- P54_CRYPTO_TKIP
- P54_CRYPTO_TKIPMICHAEL
- P54_CRYPTO_WEP
- P54_DECRYPT_FAIL_AESCCMP
- P54_DECRYPT_FAIL_CKIPKP
- P54_DECRYPT_FAIL_CKIPMIC
- P54_DECRYPT_FAIL_MICHAEL
- P54_DECRYPT_FAIL_TKIP
- P54_DECRYPT_FAIL_WEP
- P54_DECRYPT_NOCKIPMIC
- P54_DECRYPT_NOKEY
- P54_DECRYPT_NOMICHAEL
- P54_DECRYPT_NONE
- P54_DECRYPT_OK
- P54_FILTER_TYPE_AP
- P54_FILTER_TYPE_HIBERNATE
- P54_FILTER_TYPE_IBSS
- P54_FILTER_TYPE_NOACK
- P54_FILTER_TYPE_NONE
- P54_FILTER_TYPE_PROMISCUOUS
- P54_FILTER_TYPE_RX_DISABLED
- P54_FILTER_TYPE_STATION
- P54_FILTER_TYPE_TRANSPARENT
- P54_H
- P54_HDR_FLAG_CONTROL
- P54_HDR_FLAG_CONTROL_OPSET
- P54_HDR_FLAG_DATA_ALIGN
- P54_HDR_FLAG_DATA_IN_BCAST_BSS
- P54_HDR_FLAG_DATA_IN_BEACON
- P54_HDR_FLAG_DATA_IN_BIT8
- P54_HDR_FLAG_DATA_IN_DATA
- P54_HDR_FLAG_DATA_IN_FCS_GOOD
- P54_HDR_FLAG_DATA_IN_MATCH_BSS
- P54_HDR_FLAG_DATA_IN_MATCH_MAC
- P54_HDR_FLAG_DATA_IN_MCBC
- P54_HDR_FLAG_DATA_IN_TRANSPARENT
- P54_HDR_FLAG_DATA_IN_TRUNCATED
- P54_HDR_FLAG_DATA_OUT_BIT3
- P54_HDR_FLAG_DATA_OUT_BURST
- P54_HDR_FLAG_DATA_OUT_CLEARTIM
- P54_HDR_FLAG_DATA_OUT_COMPRESS
- P54_HDR_FLAG_DATA_OUT_CONCAT
- P54_HDR_FLAG_DATA_OUT_HITCHHIKE
- P54_HDR_FLAG_DATA_OUT_NOCANCEL
- P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT
- P54_HDR_FLAG_DATA_OUT_PROMISC
- P54_HDR_FLAG_DATA_OUT_SEQNR
- P54_HDR_FLAG_DATA_OUT_TIMESTAMP
- P54_HDR_FLAG_DATA_OUT_WAITEOSP
- P54_LED_MAX_NAME_LEN
- P54_MAX_CTRL_FRAME_LEN
- P54_PSM
- P54_PSM_AUTOSWITCH_SLEEP
- P54_PSM_BEACON_TIMEOUT
- P54_PSM_BF_MCAST_SKIP
- P54_PSM_BF_UCAST_SKIP
- P54_PSM_CAM
- P54_PSM_CHECKSUM
- P54_PSM_DTIM
- P54_PSM_HFOSLEEP
- P54_PSM_LPIT
- P54_PSM_MCBC
- P54_PSM_SKIP_MORE_DATA
- P54_QUEUE_AC_BE
- P54_QUEUE_AC_BK
- P54_QUEUE_AC_NUM
- P54_QUEUE_AC_VI
- P54_QUEUE_AC_VO
- P54_QUEUE_BEACON
- P54_QUEUE_CAB
- P54_QUEUE_DATA
- P54_QUEUE_FWSCAN
- P54_QUEUE_MGMT
- P54_QUEUE_NUM
- P54_SCAN_ACTIVE
- P54_SCAN_EXIT
- P54_SCAN_FILTER
- P54_SCAN_TRAP
- P54_SETUP_V1_LEN
- P54_SETUP_V2_LEN
- P54_SET_QUEUE
- P54_STATISTICS_UPDATE
- P54_TIM_CLEAR
- P54_TRAP_BEACON_TX
- P54_TRAP_FAA_RADIO_OFF
- P54_TRAP_FAA_RADIO_ON
- P54_TRAP_NO_BEACON
- P54_TRAP_RADAR
- P54_TRAP_SCAN
- P54_TRAP_SCO_ENTER
- P54_TRAP_SCO_EXIT
- P54_TRAP_TBTT
- P54_TRAP_TIMER
- P54_TX_FAILED
- P54_TX_FRAME_LIFETIME
- P54_TX_INFO_DATA_SIZE
- P54_TX_OK
- P54_TX_PSM
- P54_TX_PSM_CANCELLED
- P54_TX_TIMEOUT
- P5_CPU_WAKE_IRQ
- P5_DESC
- P5_DISABLED
- P5_INTF_SEL_GMAC5
- P5_INTF_SEL_PHY_P0
- P5_INTF_SEL_PHY_P4
- P5_IO_CLK_DRV
- P5_IO_DATA_DRV
- P6
- P64
- P64e
- P64o
- P6_INTF_MODE
- P6_INTF_MODE_MASK
- P6_NOP1
- P6_NOP2
- P6_NOP3
- P6_NOP4
- P6_NOP5
- P6_NOP5_ATOMIC
- P6_NOP6
- P6_NOP7
- P6_NOP8
- P6_NOP_EVENT
- P7
- P7500_FIRMWARE
- P7_CPU_WAKE_IRQ
- P7_IRQ_OFF
- P8
- P80211CAPTURE_VERSION
- P80211DID_ACCESS
- P80211DID_GET
- P80211DID_GROUP
- P80211DID_INDEX
- P80211DID_ISTABLE
- P80211DID_ITEM
- P80211DID_LSB_ACCESS
- P80211DID_LSB_GROUP
- P80211DID_LSB_INDEX
- P80211DID_LSB_ISTABLE
- P80211DID_LSB_ITEM
- P80211DID_LSB_SECTION
- P80211DID_MASK_ACCESS
- P80211DID_MASK_GROUP
- P80211DID_MASK_INDEX
- P80211DID_MASK_ISTABLE
- P80211DID_MASK_ITEM
- P80211DID_MASK_SECTION
- P80211DID_MK
- P80211DID_MKGROUP
- P80211DID_MKID
- P80211DID_MKINDEX
- P80211DID_MKISTABLE
- P80211DID_MKITEM
- P80211DID_MKSECTION
- P80211DID_SECTION
- P80211ENUM_authalg_opensystem
- P80211ENUM_authalg_sharedkey
- P80211ENUM_bsstype_any
- P80211ENUM_bsstype_independent
- P80211ENUM_bsstype_infrastructure
- P80211ENUM_ifstate_disable
- P80211ENUM_ifstate_enable
- P80211ENUM_ifstate_fwload
- P80211ENUM_msgitem_status_data_ok
- P80211ENUM_msgitem_status_no_value
- P80211ENUM_resultcode_cant_get_writeonly_mib
- P80211ENUM_resultcode_cant_set_readonly_mib
- P80211ENUM_resultcode_implementation_failure
- P80211ENUM_resultcode_invalid_parameters
- P80211ENUM_resultcode_not_supported
- P80211ENUM_resultcode_refused
- P80211ENUM_resultcode_success
- P80211ENUM_scantype_active
- P80211ENUM_status_ap_full
- P80211ENUM_status_successful
- P80211ENUM_status_unspec_failure
- P80211ENUM_truth_false
- P80211ENUM_truth_true
- P80211SEC_DOT11MAC
- P80211SEC_DOT11PHY
- P80211SEC_DOT11SMT
- P80211_DATA_VAL
- P80211_FRMMETA_MAGIC
- P80211_IFREQ
- P80211_IFTEST
- P80211_IOCTL_MAGIC
- P80211_MIB_CAT_DOT11MAC
- P80211_MIB_CAT_DOT11PHY
- P80211_MIB_CAT_DOT11SMT
- P80211_MSG_CAT_DOT11IND
- P80211_MSG_CAT_DOT11REQ
- P80211_NSDCAP_AUTOJOIN
- P80211_NSDCAP_HARDWAREWEP
- P80211_NSDCAP_HWFRAGMENT
- P80211_NSDCAP_NOSCAN
- P80211_NSDCAP_SHORT_PREAMBLE
- P80211_OUI_LEN
- P8023_DATA_VAL
- P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
- P880_IGA1_FIFO_HIGH_THRESHOLD
- P880_IGA1_FIFO_MAX_DEPTH
- P880_IGA1_FIFO_THRESHOLD
- P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
- P880_IGA2_FIFO_HIGH_THRESHOLD
- P880_IGA2_FIFO_MAX_DEPTH
- P880_IGA2_FIFO_THRESHOLD
- P880_POWER_SEQ_FORMULA
- P880_POWER_SEQ_UNIT
- P8_16x16_8x16
- P8_16x32_16x16
- P8_16x32_8x16
- P8_32x32_16x16
- P8_32x32_16x32
- P8_32x32_8x16
- P8_32x64_32x32
- P8_CAPP_UNIT0_ID
- P8_CAPP_UNIT1_ID
- P8_CPU_WAKE_IRQ
- P8e
- P8e_s
- P8o
- P8o_s
- P9
- P9100_CMD_OFF
- P9100_FB_OFF
- P9100_FLAG_BLANKED
- P9100_RAMDAC_OFF
- P9100_SYSCTL_OFF
- P9100_VIDEOCOPROC_OFF
- P9100_VIDEOCTL_OFF
- P9100_VRAMCTL_OFF
- P9_ATTR_ATIME
- P9_ATTR_ATIME_SET
- P9_ATTR_CTIME
- P9_ATTR_GID
- P9_ATTR_MODE
- P9_ATTR_MTIME
- P9_ATTR_MTIME_SET
- P9_ATTR_SIZE
- P9_ATTR_UID
- P9_CAPP_UNIT0_ID
- P9_CAPP_UNIT1_ID
- P9_DEBUG_9P
- P9_DEBUG_CONV
- P9_DEBUG_ERROR
- P9_DEBUG_FCALL
- P9_DEBUG_FID
- P9_DEBUG_FSC
- P9_DEBUG_MUX
- P9_DEBUG_PKT
- P9_DEBUG_SLABS
- P9_DEBUG_TRANS
- P9_DEBUG_VFS
- P9_DEBUG_VPKT
- P9_DEF_MAX_RESVPORT
- P9_DEF_MIN_RESVPORT
- P9_DMAPPEND
- P9_DMAUTH
- P9_DMDEVICE
- P9_DMDIR
- P9_DMEXCL
- P9_DMLINK
- P9_DMMOUNT
- P9_DMNAMEDPIPE
- P9_DMSETGID
- P9_DMSETUID
- P9_DMSETVTX
- P9_DMSOCKET
- P9_DMSYMLINK
- P9_DMTMP
- P9_DOTL_APPEND
- P9_DOTL_AT_REMOVEDIR
- P9_DOTL_CLOEXEC
- P9_DOTL_CREATE
- P9_DOTL_DIRECT
- P9_DOTL_DIRECTORY
- P9_DOTL_DSYNC
- P9_DOTL_EXCL
- P9_DOTL_FASYNC
- P9_DOTL_LARGEFILE
- P9_DOTL_NOACCESS
- P9_DOTL_NOATIME
- P9_DOTL_NOCTTY
- P9_DOTL_NOFOLLOW
- P9_DOTL_NONBLOCK
- P9_DOTL_RDONLY
- P9_DOTL_RDWR
- P9_DOTL_SYNC
- P9_DOTL_TRUNC
- P9_DOTL_WRONLY
- P9_HDRSZ
- P9_IOHDRSZ
- P9_LOCK_BLOCKED
- P9_LOCK_ERROR
- P9_LOCK_FLAGS_BLOCK
- P9_LOCK_FLAGS_RECLAIM
- P9_LOCK_GRACE
- P9_LOCK_SUCCESS
- P9_LOCK_TIMEOUT
- P9_LOCK_TYPE_RDLCK
- P9_LOCK_TYPE_UNLCK
- P9_LOCK_TYPE_WRLCK
- P9_MAXWELEM
- P9_MSG_T
- P9_NOFID
- P9_NOTAG
- P9_OAPPEND
- P9_OEXCL
- P9_OEXEC
- P9_ORCLOSE
- P9_ORDWR
- P9_OREAD
- P9_OREXEC
- P9_OTRUNC
- P9_OWRITE
- P9_PORT
- P9_PROTO_DUMP_SZ
- P9_QTAPPEND
- P9_QTAUTH
- P9_QTDIR
- P9_QTEXCL
- P9_QTFILE
- P9_QTLINK
- P9_QTMOUNT
- P9_QTSYMLINK
- P9_QTTMP
- P9_RATTACH
- P9_RAUTH
- P9_RCLUNK
- P9_RCREATE
- P9_RDMA_ADDR_RESOLVED
- P9_RDMA_CLOSED
- P9_RDMA_CLOSING
- P9_RDMA_CONNECTED
- P9_RDMA_FLUSHING
- P9_RDMA_INIT
- P9_RDMA_IRD
- P9_RDMA_MAXSIZE
- P9_RDMA_ORD
- P9_RDMA_RECV_SGE
- P9_RDMA_ROUTE_RESOLVED
- P9_RDMA_RQ_DEPTH
- P9_RDMA_SEND_SGE
- P9_RDMA_SQ_DEPTH
- P9_RDMA_TIMEOUT
- P9_READDIRHDRSZ
- P9_RERROR
- P9_RFLUSH
- P9_RFSYNC
- P9_RGETATTR
- P9_RGETLOCK
- P9_RLCREATE
- P9_RLERROR
- P9_RLINK
- P9_RLOCK
- P9_RLOPEN
- P9_RMKDIR
- P9_RMKNOD
- P9_ROPEN
- P9_ROW_MAXTAG
- P9_RREAD
- P9_RREADDIR
- P9_RREADLINK
- P9_RREMOVE
- P9_RRENAME
- P9_RRENAMEAT
- P9_RSETATTR
- P9_RSTAT
- P9_RSTATFS
- P9_RSYMLINK
- P9_RUNLINKAT
- P9_RVERSION
- P9_RWALK
- P9_RWRITE
- P9_RWSTAT
- P9_RXATTRCREATE
- P9_RXATTRWALK
- P9_STATS_ALL
- P9_STATS_ATIME
- P9_STATS_BASIC
- P9_STATS_BLOCKS
- P9_STATS_BTIME
- P9_STATS_CTIME
- P9_STATS_DATA_VERSION
- P9_STATS_GEN
- P9_STATS_GID
- P9_STATS_INO
- P9_STATS_MODE
- P9_STATS_MTIME
- P9_STATS_NLINK
- P9_STATS_RDEV
- P9_STATS_SIZE
- P9_STATS_UID
- P9_STOP_SPR_MSR
- P9_STOP_SPR_PSSCR
- P9_TATTACH
- P9_TAUTH
- P9_TCLUNK
- P9_TCREATE
- P9_TERROR
- P9_TFLUSH
- P9_TFSYNC
- P9_TGETATTR
- P9_TGETLOCK
- P9_TLCREATE
- P9_TLERROR
- P9_TLINK
- P9_TLOCK
- P9_TLOPEN
- P9_TMKDIR
- P9_TMKNOD
- P9_TOPEN
- P9_TREAD
- P9_TREADDIR
- P9_TREADLINK
- P9_TREMOVE
- P9_TRENAME
- P9_TRENAMEAT
- P9_TSETATTR
- P9_TSTAT
- P9_TSTATFS
- P9_TSYMLINK
- P9_TUNLINKAT
- P9_TVERSION
- P9_TWALK
- P9_TWRITE
- P9_TWSTAT
- P9_TXATTRCREATE
- P9_TXATTRWALK
- P9_ZC_HDR_SZ
- PA
- PA0HZP
- PA0_AIN_SLCDC1_DAT3
- PA0_DATA
- PA0_FN
- PA0_IN
- PA0_IOR_IN
- PA0_IOR_OUT
- PA0_OUT
- PA0_PF_USBH2_CLK
- PA0_RG_U2PLL_FORCE_ON
- PA0_RG_USB20_INTR_EN
- PA10_AF_BMI_D4
- PA10_PF_LD4
- PA11_AF_BMI_D5
- PA11_AIN_SLCDC1_DAT5
- PA11_PF_LD5
- PA12203001_AFSR_MASK
- PA12203001_AFSR_SHIFT
- PA12203001_ALS_EN_MASK
- PA12203001_CHIP_DISABLE
- PA12203001_CHIP_ENABLE
- PA12203001_DRIVER_NAME
- PA12203001_PSCAN
- PA12203001_PX_EN_MASK
- PA12203001_PX_NORMAL_MODE_MASK
- PA12203001_REG_ADL
- PA12203001_REG_CFG0
- PA12203001_REG_CFG0_DEFAULT
- PA12203001_REG_CFG1
- PA12203001_REG_CFG1_DEFAULT
- PA12203001_REG_CFG2
- PA12203001_REG_CFG2_DEFAULT
- PA12203001_REG_CFG3
- PA12203001_REG_CFG3_DEFAULT
- PA12203001_REG_PDH
- PA12203001_REG_POFS
- PA12203001_REG_PSET
- PA12203001_SLEEP_DELAY_MS
- PA12_AF_BMI_D6
- PA12_PF_LD6
- PA13_AF_BMI_D7
- PA13_AIN_SLCDC1_DAT7
- PA13_PF_LD7
- PA14_AF_BMI_D8
- PA14_CIN_SLCDC1_DAT0
- PA14_PF_LD8
- PA15_AF_BMI_D9
- PA15_AIN_SLCDC1_DAT9
- PA15_CIN_SLCDC1_DAT1
- PA15_PF_LD9
- PA16_AF_BMI_D10
- PA16_CIN_SLCDC1_DAT2
- PA16_PF_LD10
- PA17_AF_BMI_D11
- PA17_AIN_SLCDC1_DAT11
- PA17_CIN_SLCDC1_DAT3
- PA17_PF_LD11
- PA18_AF_BMI_D12
- PA18_CIN_SLCDC1_DAT4
- PA18_PF_LD12
- PA19_AF_BMI_D13
- PA19_AIN_SLCDC1_DAT13
- PA19_CIN_SLCDC1_DAT5
- PA19_PF_LD13
- PA1_COL
- PA1_CRS
- PA1_DATA
- PA1_DIRA0
- PA1_DIRA1
- PA1_FN
- PA1_IN
- PA1_IOR_IN
- PA1_IOR_OUT
- PA1_OUT
- PA1_PF_USBH2_DIR
- PA1_PSORA0
- PA1_PSORA1
- PA1_RG_TERM_SEL
- PA1_RG_TERM_SEL_VAL
- PA1_RG_VRT_SEL
- PA1_RG_VRT_SEL_VAL
- PA1_RXDAT
- PA1_RXDV
- PA1_RXER
- PA1_TXDAT
- PA1_TXEN
- PA1_TXER
- PA20_AF_BMI_D14
- PA20_CIN_SLCDC1_DAT6
- PA20_PF_LD14
- PA21_AF_BMI_D15
- PA21_AIN_SLCDC1_DAT15
- PA21_CIN_SLCDC1_DAT7
- PA21_PF_LD15
- PA22_AF_BMI_READ_REQ
- PA22_AIN_EXT_DMAGRANT
- PA22_PF_LD16
- PA23_AF_BMI_WRITE
- PA23_PF_LD17
- PA24_AIN_SLCDC1_D0
- PA24_PF_REV
- PA25_AIN_SLCDC1_RS
- PA25_PF_CLS
- PA26_AIN_SLCDC1_CS
- PA26_PF_PS
- PA27_AIN_SLCDC1_CLK
- PA27_PF_SPL_SPR
- PA28_PF_HSYNC
- PA29_AF_BMI_RX_FULL
- PA29_AOUT_BMI_WAIT
- PA29_PF_VSYNC
- PA2_0_FPU_FLAG
- PA2_DATA
- PA2_FN
- PA2_IN
- PA2_IOR_IN
- PA2_IOR_OUT
- PA2_OUT
- PA2_PF_USBH2_DATA7
- PA2_RG_SIF_U2PLL_FORCE_EN
- PA30_AF_BMI_READ
- PA30_PF_CONTRAST
- PA31_PF_OE_ACD
- PA3_DATA
- PA3_FN
- PA3_IN
- PA3_IOR_IN
- PA3_IOR_OUT
- PA3_OUT
- PA3_PF_USBH2_NXT
- PA4_DATA
- PA4_FN
- PA4_IN
- PA4_OUT
- PA4_PF_USBH2_STP
- PA5_AF_BMI_CLK_CS
- PA5_DATA
- PA5_FN
- PA5_IN
- PA5_OUT
- PA5_PF_LSCLK
- PA5_RG_U2_HSTX_SRCAL_EN
- PA5_RG_U2_HSTX_SRCTRL
- PA5_RG_U2_HSTX_SRCTRL_VAL
- PA5_RG_U2_HS_100U_U3_EN
- PA6T_MMCR0_DAMEN2
- PA6T_MMCR0_DAMEN3
- PA6T_MMCR0_DAMEN4
- PA6T_MMCR0_DAMEN5
- PA6T_MMCR0_DAMSEL2
- PA6T_MMCR0_DAMSEL3
- PA6T_MMCR0_DAMSEL4
- PA6T_MMCR0_DAMSEL5
- PA6T_MMCR0_DISCNT
- PA6T_MMCR0_EN0
- PA6T_MMCR0_EN1
- PA6T_MMCR0_EN2
- PA6T_MMCR0_EN3
- PA6T_MMCR0_EN4
- PA6T_MMCR0_EN5
- PA6T_MMCR0_FCM0
- PA6T_MMCR0_FCM1
- PA6T_MMCR0_HANDDIS
- PA6T_MMCR0_HYPEN
- PA6T_MMCR0_INTEN0
- PA6T_MMCR0_INTEN1
- PA6T_MMCR0_INTEN2
- PA6T_MMCR0_INTEN3
- PA6T_MMCR0_INTEN4
- PA6T_MMCR0_INTEN5
- PA6T_MMCR0_INTGEN
- PA6T_MMCR0_PCTEN
- PA6T_MMCR0_PREN
- PA6T_MMCR0_PROEN
- PA6T_MMCR0_PROLOG
- PA6T_MMCR0_SDARLOG
- PA6T_MMCR0_SIARLOG
- PA6T_MMCR0_SOCEN
- PA6T_MMCR0_SOCMOD
- PA6T_MMCR0_SUPEN
- PA6T_MMCR0_TRG
- PA6T_MMCR0_TRGEN
- PA6T_MMCR0_TRGREG
- PA6T_MMCR0_UOP
- PA6T_MMCR1_ES2
- PA6T_MMCR1_ES3
- PA6T_MMCR1_ES4
- PA6T_MMCR1_ES5
- PA6_AF_BMI_D0
- PA6_AIN_SLCDC1_DAT0
- PA6_DATA
- PA6_FN
- PA6_IN
- PA6_OUT
- PA6_PF_LD0
- PA6_RG_U2_BC11_SW_EN
- PA6_RG_U2_OTG_VBUSCMP_EN
- PA6_RG_U2_SQTH
- PA6_RG_U2_SQTH_VAL
- PA7_AF_BMI_D1
- PA7_AIN_SLCDC1_DAT1
- PA7_DATA
- PA7_FN
- PA7_IN
- PA7_OUT
- PA7_PF_LD1
- PA83_FPU_FLAG
- PA83_UNIMP_EXCP
- PA89_FPU_FLAG
- PA89_INSTRUCTION_SET
- PA8_AF_BMI_D2
- PA8_AIN_SLCDC1_DAT2
- PA8_PF_LD2
- PA90_INSTRUCTION_SET
- PA9_AF_BMI_D3
- PA9_PF_LD3
- PAACE_AF_AP
- PAACE_AF_AP_SHIFT
- PAACE_AF_DD
- PAACE_AF_DD_SHIFT
- PAACE_AF_PT
- PAACE_AF_PT_SHIFT
- PAACE_AF_V
- PAACE_AF_V_SHIFT
- PAACE_AP_PERMS_ALL
- PAACE_AP_PERMS_DENIED
- PAACE_AP_PERMS_QUERY
- PAACE_AP_PERMS_UPDATE
- PAACE_ATM_NO_XLATE
- PAACE_ATM_PAGE_XLATE
- PAACE_ATM_WINDOW_XLATE
- PAACE_ATM_WIN_PG_XLATE
- PAACE_DA_HOST_CR
- PAACE_DA_HOST_CR_SHIFT
- PAACE_DD_TO_HOST
- PAACE_DD_TO_IO
- PAACE_DID_BM_SW_PORTAL
- PAACE_DID_BROADCAST
- PAACE_DID_CAAM
- PAACE_DID_CORE0_DATA
- PAACE_DID_CORE0_INST
- PAACE_DID_CORE1_DATA
- PAACE_DID_CORE1_INST
- PAACE_DID_CORE2_DATA
- PAACE_DID_CORE2_INST
- PAACE_DID_CORE3_DATA
- PAACE_DID_CORE3_INST
- PAACE_DID_CORE4_DATA
- PAACE_DID_CORE4_INST
- PAACE_DID_CORE5_DATA
- PAACE_DID_CORE5_INST
- PAACE_DID_CORE6_DATA
- PAACE_DID_CORE6_INST
- PAACE_DID_CORE7_DATA
- PAACE_DID_CORE7_INST
- PAACE_DID_LOCAL_BUS
- PAACE_DID_MEM_1
- PAACE_DID_MEM_1_2
- PAACE_DID_MEM_1_4
- PAACE_DID_MEM_2
- PAACE_DID_MEM_3
- PAACE_DID_MEM_3_4
- PAACE_DID_MEM_4
- PAACE_DID_PAMU
- PAACE_DID_PCI_EXPRESS_1
- PAACE_DID_PCI_EXPRESS_2
- PAACE_DID_PCI_EXPRESS_3
- PAACE_DID_PCI_EXPRESS_4
- PAACE_DID_QM_SW_PORTAL
- PAACE_DID_SRIO
- PAACE_IA_ATM
- PAACE_IA_ATM_SHIFT
- PAACE_IA_CID
- PAACE_IA_CID_SHIFT
- PAACE_IA_OTM
- PAACE_IA_OTM_SHIFT
- PAACE_IA_WCE
- PAACE_IA_WCE_SHIFT
- PAACE_MW_SUBWINDOWS
- PAACE_M_COHERENCE_REQ
- PAACE_NUMBER_ENTRIES
- PAACE_OTM_IMMEDIATE
- PAACE_OTM_INDEXED
- PAACE_OTM_NO_XLATE
- PAACE_OTM_RESERVED
- PAACE_PID_0
- PAACE_PID_1
- PAACE_PID_2
- PAACE_PID_3
- PAACE_PID_4
- PAACE_PID_5
- PAACE_PID_6
- PAACE_PID_7
- PAACE_PT_PRIMARY
- PAACE_PT_SECONDARY
- PAACE_TCEF_FORMAT0_8B
- PAACE_TCEF_FORMAT1_RSVD
- PAACE_V_INVALID
- PAACE_V_VALID
- PAACE_WIN_SWSE
- PAACE_WIN_SWSE_SHIFT
- PAACE_WIN_TWBAL
- PAACE_WIN_TWBAL_SHIFT
- PAACE_WSE_128K
- PAACE_WSE_128M
- PAACE_WSE_16K
- PAACE_WSE_16M
- PAACE_WSE_1G
- PAACE_WSE_1M
- PAACE_WSE_256K
- PAACE_WSE_256M
- PAACE_WSE_2G
- PAACE_WSE_2M
- PAACE_WSE_32K
- PAACE_WSE_32M
- PAACE_WSE_4G
- PAACE_WSE_4K
- PAACE_WSE_4M
- PAACE_WSE_512K
- PAACE_WSE_512M
- PAACE_WSE_64K
- PAACE_WSE_64M
- PAACE_WSE_8K
- PAACE_WSE_8M
- PAACT_SIZE
- PABO
- PABR0
- PABR0H
- PABR0L
- PABR1
- PABR1H
- PABR1L
- PAB_AXI_AMAP_AXI_WIN
- PAB_AXI_AMAP_CTRL
- PAB_AXI_AMAP_PEX_WIN_H
- PAB_AXI_AMAP_PEX_WIN_L
- PAB_AXI_PIO_CTRL
- PAB_BUS_SHIFT
- PAB_CTRL
- PAB_DEVICE_SHIFT
- PAB_EXT_AXI_AMAP_AXI_WIN
- PAB_EXT_AXI_AMAP_SIZE
- PAB_EXT_PEX_AMAP_AXI_WIN
- PAB_EXT_PEX_AMAP_SIZEN
- PAB_EXT_REG_ADDR
- PAB_EXT_REG_BLOCK_SIZE
- PAB_FUNCTION_SHIFT
- PAB_INTP_AMBA_MISC_ENB
- PAB_INTP_AMBA_MISC_STAT
- PAB_INTP_AXI_PIO_CLASS
- PAB_INTP_INTX_MASK
- PAB_INTP_MSI_MASK
- PAB_INTX_START
- PAB_PEX_AMAP_AXI_WIN
- PAB_PEX_AMAP_CTRL
- PAB_PEX_AMAP_PEX_WIN_H
- PAB_PEX_AMAP_PEX_WIN_L
- PAB_PEX_PIO_CTRL
- PAB_REG_ADDR
- PAB_REG_BLOCK_SIZE
- PAC207_AUTOGAIN_DEADZONE
- PAC207_BRIGHTNESS_DEFAULT
- PAC207_BRIGHTNESS_MAX
- PAC207_BRIGHTNESS_MIN
- PAC207_BRIGHTNESS_REG
- PAC207_CTRL_TIMEOUT
- PAC207_EXPOSURE_DEFAULT
- PAC207_EXPOSURE_MAX
- PAC207_EXPOSURE_MIN
- PAC207_EXPOSURE_REG
- PAC207_GAIN_DEFAULT
- PAC207_GAIN_MAX
- PAC207_GAIN_MIN
- PAC207_GAIN_REG
- PAC7302_EXPOSURE_DEFAULT
- PAC7302_EXPOSURE_KNEE
- PAC7302_GAIN_DEFAULT
- PAC7302_GAIN_KNEE
- PAC7302_RGB_BALANCE_DEFAULT
- PAC7302_RGB_BALANCE_MAX
- PAC7302_RGB_BALANCE_MIN
- PAC7311_EXPOSURE_DEFAULT
- PAC7311_GAIN_DEFAULT
- PACATOC
- PACA_EXGDBELL
- PACA_IRQ_DBELL
- PACA_IRQ_DEC
- PACA_IRQ_EE
- PACA_IRQ_EE_EDGE
- PACA_IRQ_HARD_DIS
- PACA_IRQ_HMI
- PACA_IRQ_MUST_HARD_MASK
- PACA_IRQ_PMI
- PACE_OFFSET
- PACE_S
- PACE_V
- PACFGIB_DEFAULT_CURRENT
- PACK
- PACK32
- PACK64
- PACKAGE
- PACKAGE_16BITBUS_STREAM
- PACKAGE_24BITBUS_BACK
- PACKAGE_24BITBUS_FRONT
- PACKAGE_DEFAULT
- PACKAGE_DOMAIN_NAME_LENGTH
- PACKAGE_INFO
- PACKAGE_LEVEL
- PACKAGE_MAX_FW_INFO_ENTRIES
- PACKAGE_PLN_INT_SAVED
- PACKAGE_POWER__Pkg_power_MASK
- PACKAGE_POWER__Pkg_power__SHIFT
- PACKAGE_QFN68
- PACKAGE_TFBGA79
- PACKAGE_TFBGA80
- PACKAGE_TFBGA90
- PACKAGE_THERM_INT_HIGH_ENABLE
- PACKAGE_THERM_INT_LOW_ENABLE
- PACKAGE_THERM_INT_PLN_ENABLE
- PACKAGE_THERM_STATUS_POWER_LIMIT
- PACKAGE_THERM_STATUS_PROCHOT
- PACKAGE_TYPE_E
- PACKAGE_V2_MAX_FW_INFO_ENTRIES
- PACKB
- PACKED
- PACKED_444
- PACKED_444_FP16
- PACKED_FLAG_HAT
- PACKED_MODE_COMPLAIN
- PACKED_MODE_ENABLE
- PACKED_MODE_ENFORCE
- PACKED_MODE_KILL
- PACKED_MODE_UNCONFINED
- PACKED_PS_16BIT_RGB565
- PACKED_PS_18BIT_RGB666
- PACKED_PS_24BIT_RGB888
- PACKET
- PACKET0
- PACKET0_BASE_INDEX_MASK
- PACKET0_BASE_INDEX_SHIFT
- PACKET0_COUNT_MASK
- PACKET0_COUNT_SHIFT
- PACKET2
- PACKET2_PAD_MASK
- PACKET2_PAD_SHIFT
- PACKET3
- PACKET3_3D_CLEAR_CMASK
- PACKET3_3D_CLEAR_HIZ
- PACKET3_3D_CLEAR_ZMASK
- PACKET3_3D_DRAW_IMMD
- PACKET3_3D_DRAW_IMMD_2
- PACKET3_3D_DRAW_INDX
- PACKET3_3D_DRAW_INDX_2
- PACKET3_3D_DRAW_VBUF
- PACKET3_3D_DRAW_VBUF_2
- PACKET3_3D_LOAD_VBPNTR
- PACKET3_ACQUIRE_MEM
- PACKET3_ALLOC_GDS
- PACKET3_ALU_PS_CONST_BUFFER_COPY
- PACKET3_ALU_PS_CONST_UPDATE
- PACKET3_ALU_VS_CONST_BUFFER_COPY
- PACKET3_ALU_VS_CONST_UPDATE
- PACKET3_AQL_PACKET
- PACKET3_AQUIRE_MEM
- PACKET3_ATOMIC
- PACKET3_ATOMIC_GDS
- PACKET3_ATOMIC_MEM
- PACKET3_BASE_INDEX
- PACKET3_BITBLT_MULTI
- PACKET3_BLK_CNTX_UPDATE
- PACKET3_CB0_DEST_BASE_ENA
- PACKET3_CB10_DEST_BASE_ENA
- PACKET3_CB11_DEST_BASE_ENA
- PACKET3_CB1_DEST_BASE_ENA
- PACKET3_CB2_DEST_BASE_ENA
- PACKET3_CB3_DEST_BASE_ENA
- PACKET3_CB4_DEST_BASE_ENA
- PACKET3_CB5_DEST_BASE_ENA
- PACKET3_CB6_DEST_BASE_ENA
- PACKET3_CB7_DEST_BASE_ENA
- PACKET3_CB8_DEST_BASE_ENA
- PACKET3_CB9_DEST_BASE_ENA
- PACKET3_CB_ACTION_ENA
- PACKET3_CE_WRITE
- PACKET3_CLEAR_STATE
- PACKET3_COMPUTE
- PACKET3_COND_EXEC
- PACKET3_COND_INDIRECT_BUFFER
- PACKET3_COND_INDIRECT_BUFFER_CNST
- PACKET3_COND_PREEMPT
- PACKET3_COND_WRITE
- PACKET3_CONTEXT_CONTROL
- PACKET3_CONTEXT_REG_RMW
- PACKET3_COPY_DATA
- PACKET3_COPY_DATA_RB
- PACKET3_COPY_DW
- PACKET3_COUNT_MASK
- PACKET3_COUNT_SHIFT
- PACKET3_CP_DMA
- PACKET3_CP_DMA_CMD_DAIC
- PACKET3_CP_DMA_CMD_DAS
- PACKET3_CP_DMA_CMD_DST_SWAP
- PACKET3_CP_DMA_CMD_RAW_WAIT
- PACKET3_CP_DMA_CMD_SAIC
- PACKET3_CP_DMA_CMD_SAS
- PACKET3_CP_DMA_CMD_SRC_SWAP
- PACKET3_CP_DMA_CP_SYNC
- PACKET3_CP_DMA_DIS_WC
- PACKET3_CP_DMA_DST_SEL
- PACKET3_CP_DMA_ENGINE
- PACKET3_CP_DMA_SRC_SEL
- PACKET3_DB_ACTION_ENA
- PACKET3_DB_DEST_BASE_ENA
- PACKET3_DEALLOC_STATE
- PACKET3_DEST_BASE_0_ENA
- PACKET3_DEST_BASE_1_ENA
- PACKET3_DEST_BASE_2_ENA
- PACKET3_DEST_BASE_3_ENA
- PACKET3_DISPATCH_DIRECT
- PACKET3_DISPATCH_DRAW
- PACKET3_DISPATCH_DRAW_ACE
- PACKET3_DISPATCH_DRAW_PREAMBLE
- PACKET3_DISPATCH_DRAW_PREAMBLE_ACE
- PACKET3_DISPATCH_INDIRECT
- PACKET3_DMA_DATA
- PACKET3_DMA_DATA_CMD_DAIC
- PACKET3_DMA_DATA_CMD_DAS
- PACKET3_DMA_DATA_CMD_DST_SWAP
- PACKET3_DMA_DATA_CMD_RAW_WAIT
- PACKET3_DMA_DATA_CMD_SAIC
- PACKET3_DMA_DATA_CMD_SAS
- PACKET3_DMA_DATA_CMD_SRC_SWAP
- PACKET3_DMA_DATA_CP_SYNC
- PACKET3_DMA_DATA_DIS_WC
- PACKET3_DMA_DATA_DST_CACHE_POLICY
- PACKET3_DMA_DATA_DST_SEL
- PACKET3_DMA_DATA_DST_VOLATILE
- PACKET3_DMA_DATA_ENGINE
- PACKET3_DMA_DATA_FILL_MULTI
- PACKET3_DMA_DATA_SRC_CACHE_POLICY
- PACKET3_DMA_DATA_SRC_SEL
- PACKET3_DMA_DATA_SRC_VOLATILE
- PACKET3_DRAW_INDEX
- PACKET3_DRAW_INDEX_2
- PACKET3_DRAW_INDEX_AUTO
- PACKET3_DRAW_INDEX_IMMD
- PACKET3_DRAW_INDEX_IMMD_BE
- PACKET3_DRAW_INDEX_INDIRECT
- PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI
- PACKET3_DRAW_INDEX_INDIRECT_MULTI
- PACKET3_DRAW_INDEX_MULTI_AUTO
- PACKET3_DRAW_INDEX_MULTI_ELEMENT
- PACKET3_DRAW_INDEX_MULTI_INST
- PACKET3_DRAW_INDEX_OFFSET
- PACKET3_DRAW_INDEX_OFFSET_2
- PACKET3_DRAW_INDIRECT
- PACKET3_DRAW_INDIRECT_COUNT_MULTI
- PACKET3_DRAW_INDIRECT_MULTI
- PACKET3_DRAW_MULTI_PREAMBLE
- PACKET3_DRAW_PREAMBLE
- PACKET3_DUMP_CONST_RAM
- PACKET3_DUMP_CONST_RAM_OFFSET
- PACKET3_ENGINE_ME
- PACKET3_EVENT_WRITE
- PACKET3_EVENT_WRITE_EOP
- PACKET3_EVENT_WRITE_EOS
- PACKET3_FORWARD_HEADER
- PACKET3_FRAME_CONTROL
- PACKET3_FULL_CACHE_ENA
- PACKET3_GEN_PDEPTE
- PACKET3_GET_LOD_STATS
- PACKET3_GFX_CNTX_UPDATE
- PACKET3_GFX_PIPE_LOCK
- PACKET3_HDP_FLUSH
- PACKET3_INCREMENT_CE_COUNTER
- PACKET3_INCREMENT_DE_COUNTER
- PACKET3_INCR_UPDT_STATE
- PACKET3_INDEX_ATTRIBUTES_INDIRECT
- PACKET3_INDEX_BASE
- PACKET3_INDEX_BUFFER_SIZE
- PACKET3_INDEX_TYPE
- PACKET3_INDIRECT_BUFFER
- PACKET3_INDIRECT_BUFFER_CNST
- PACKET3_INDIRECT_BUFFER_CNST_END
- PACKET3_INDIRECT_BUFFER_CONST
- PACKET3_INDIRECT_BUFFER_END
- PACKET3_INDIRECT_BUFFER_MP
- PACKET3_INDIRECT_BUFFER_PASID
- PACKET3_INDIRECT_BUFFER_PRIV
- PACKET3_INDX_BUFFER
- PACKET3_INTERRUPT
- PACKET3_INVALIDATE_TLBS
- PACKET3_INVALIDATE_TLBS_ALL_HUB
- PACKET3_INVALIDATE_TLBS_DST_SEL
- PACKET3_INVALIDATE_TLBS_FLUSH_TYPE
- PACKET3_INVALIDATE_TLBS_PASID
- PACKET3_IT_OPCODE_MASK
- PACKET3_IT_OPCODE_SHIFT
- PACKET3_LOAD_COMPUTE_STATE
- PACKET3_LOAD_CONFIG_REG
- PACKET3_LOAD_CONST_RAM
- PACKET3_LOAD_CONTEXT_REG
- PACKET3_LOAD_CONTEXT_REG_INDEX
- PACKET3_LOAD_SH_REG
- PACKET3_LOAD_SH_REG_INDEX
- PACKET3_LOAD_UCONFIG_REG
- PACKET3_MAP_PROCESS
- PACKET3_MAP_PROCESS_VM
- PACKET3_MAP_QUEUES
- PACKET3_MAP_QUEUES_ALLOC_FORMAT
- PACKET3_MAP_QUEUES_CHECK_DISABLE
- PACKET3_MAP_QUEUES_DOORBELL_OFFSET
- PACKET3_MAP_QUEUES_ENGINE_SEL
- PACKET3_MAP_QUEUES_ME
- PACKET3_MAP_QUEUES_NUM_QUEUES
- PACKET3_MAP_QUEUES_PIPE
- PACKET3_MAP_QUEUES_QUEUE
- PACKET3_MAP_QUEUES_QUEUE_SEL
- PACKET3_MAP_QUEUES_QUEUE_TYPE
- PACKET3_MAP_QUEUES_VMID
- PACKET3_MEM_SEMAPHORE
- PACKET3_MEM_WRITE
- PACKET3_ME_INITIALIZE
- PACKET3_ME_INITIALIZE_DEVICE_ID
- PACKET3_ME_WRITE
- PACKET3_MODE_CONTROL
- PACKET3_MPEG_INDEX
- PACKET3_NOP
- PACKET3_NUM_INSTANCES
- PACKET3_OCCLUSION_QUERY
- PACKET3_ONE_REG_WRITE
- PACKET3_PFP_SYNC_ME
- PACKET3_PREAMBLE_BEGIN_CLEAR_STATE
- PACKET3_PREAMBLE_CNTL
- PACKET3_PREAMBLE_END_CLEAR_STATE
- PACKET3_PRED_EXEC
- PACKET3_PRIME_UTCL2
- PACKET3_QUERY_STATUS
- PACKET3_QUERY_STATUS_COMMAND
- PACKET3_QUERY_STATUS_CONTEXT_ID
- PACKET3_QUERY_STATUS_DOORBELL_OFFSET
- PACKET3_QUERY_STATUS_ENG_SEL
- PACKET3_QUERY_STATUS_INTERRUPT_SEL
- PACKET3_QUERY_STATUS_PASID
- PACKET3_RB_OFFSET
- PACKET3_REG_RMW
- PACKET3_RELEASE_MEM
- PACKET3_RELEASE_MEM_CACHE_POLICY
- PACKET3_RELEASE_MEM_DATA_SEL
- PACKET3_RELEASE_MEM_DST_SEL
- PACKET3_RELEASE_MEM_EVENT_INDEX
- PACKET3_RELEASE_MEM_EVENT_TYPE
- PACKET3_RELEASE_MEM_EXECUTE
- PACKET3_RELEASE_MEM_GCR_GL1_INV
- PACKET3_RELEASE_MEM_GCR_GL2_DISCARD
- PACKET3_RELEASE_MEM_GCR_GL2_INV
- PACKET3_RELEASE_MEM_GCR_GL2_RANGE
- PACKET3_RELEASE_MEM_GCR_GL2_US
- PACKET3_RELEASE_MEM_GCR_GL2_WB
- PACKET3_RELEASE_MEM_GCR_GLM_INV
- PACKET3_RELEASE_MEM_GCR_GLM_WB
- PACKET3_RELEASE_MEM_GCR_GLV_INV
- PACKET3_RELEASE_MEM_GCR_SEQ
- PACKET3_RELEASE_MEM_INT_SEL
- PACKET3_REWIND
- PACKET3_RUN_LIST
- PACKET3_SAC_SRC_SEL_DATA
- PACKET3_SAC_SRC_SEL_GDS
- PACKET3_SAC_SRC_SEL_MEM
- PACKET3_SAC_SRC_SEL_REG
- PACKET3_SCRATCH_RAM_READ
- PACKET3_SCRATCH_RAM_WRITE
- PACKET3_SEM_CLIENT_CODE
- PACKET3_SEM_SEL_SIGNAL
- PACKET3_SEM_SEL_SIGNAL_TYPE
- PACKET3_SEM_SEL_WAIT
- PACKET3_SEM_USE_MAILBOX
- PACKET3_SEM_WAIT_ON_SIGNAL
- PACKET3_SET_ALU_CONST
- PACKET3_SET_ALU_CONST_DI
- PACKET3_SET_ALU_CONST_END
- PACKET3_SET_ALU_CONST_OFFSET
- PACKET3_SET_ALU_CONST_VS
- PACKET3_SET_APPEND_CNT
- PACKET3_SET_APPEND_CNT_SRC_SELECT
- PACKET3_SET_BASE
- PACKET3_SET_BOOL_CONST
- PACKET3_SET_BOOL_CONST_END
- PACKET3_SET_BOOL_CONST_OFFSET
- PACKET3_SET_BOOL_CONST_START
- PACKET3_SET_CE_DE_COUNTERS
- PACKET3_SET_CONFIG_REG
- PACKET3_SET_CONFIG_REG_END
- PACKET3_SET_CONFIG_REG_OFFSET
- PACKET3_SET_CONFIG_REG_START
- PACKET3_SET_CONTEXT_REG
- PACKET3_SET_CONTEXT_REG_END
- PACKET3_SET_CONTEXT_REG_INDEX
- PACKET3_SET_CONTEXT_REG_INDIRECT
- PACKET3_SET_CONTEXT_REG_OFFSET
- PACKET3_SET_CONTEXT_REG_START
- PACKET3_SET_CTL_CONST
- PACKET3_SET_CTL_CONST_END
- PACKET3_SET_CTL_CONST_OFFSET
- PACKET3_SET_CTL_CONST_START
- PACKET3_SET_LOOP_CONST
- PACKET3_SET_LOOP_CONST_END
- PACKET3_SET_LOOP_CONST_OFFSET
- PACKET3_SET_LOOP_CONST_START
- PACKET3_SET_PREDICATION
- PACKET3_SET_QUEUE_REG
- PACKET3_SET_RESOURCE
- PACKET3_SET_RESOURCES
- PACKET3_SET_RESOURCES_QUEUE_TYPE
- PACKET3_SET_RESOURCES_UNMAP_LATENTY
- PACKET3_SET_RESOURCES_VMID_MASK
- PACKET3_SET_RESOURCE_END
- PACKET3_SET_RESOURCE_INDIRECT
- PACKET3_SET_RESOURCE_OFFSET
- PACKET3_SET_RESOURCE_START
- PACKET3_SET_SAMPLER
- PACKET3_SET_SAMPLER_END
- PACKET3_SET_SAMPLER_OFFSET
- PACKET3_SET_SAMPLER_START
- PACKET3_SET_SH_REG
- PACKET3_SET_SH_REG_DI
- PACKET3_SET_SH_REG_DI_MULTI
- PACKET3_SET_SH_REG_END
- PACKET3_SET_SH_REG_INDEX
- PACKET3_SET_SH_REG_OFFSET
- PACKET3_SET_SH_REG_START
- PACKET3_SET_UCONFIG_REG
- PACKET3_SET_UCONFIG_REG_END
- PACKET3_SET_UCONFIG_REG_INDEX
- PACKET3_SET_UCONFIG_REG_INDEX_TYPE
- PACKET3_SET_UCONFIG_REG_START
- PACKET3_SET_VGPR_REG_DI_MULTI
- PACKET3_SH_ACTION_ENA
- PACKET3_SH_ICACHE_ACTION_ENA
- PACKET3_SH_KCACHE_ACTION_ENA
- PACKET3_SH_KCACHE_VOL_ACTION_ENA
- PACKET3_SMX_ACTION_ENA
- PACKET3_START_3D_CMDBUF
- PACKET3_STRMOUT_BASE_UPDATE
- PACKET3_STRMOUT_BUFFER_UPDATE
- PACKET3_SURFACE_BASE_UPDATE
- PACKET3_SURFACE_SYNC
- PACKET3_SWITCH_BUFFER
- PACKET3_SX_ACTION_ENA
- PACKET3_TCL1_ACTION_ENA
- PACKET3_TCL1_VOL_ACTION_ENA
- PACKET3_TC_ACTION_ENA
- PACKET3_TC_VOL_ACTION_ENA
- PACKET3_TC_WB_ACTION_ENA
- PACKET3_UNMAP_QUEUES
- PACKET3_UNMAP_QUEUES_ACTION
- PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0
- PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1
- PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2
- PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3
- PACKET3_UNMAP_QUEUES_ENGINE_SEL
- PACKET3_UNMAP_QUEUES_NUM_QUEUES
- PACKET3_UNMAP_QUEUES_PASID
- PACKET3_UNMAP_QUEUES_QUEUE_SEL
- PACKET3_UNMAP_QUEUES_RB_WPTR
- PACKET3_VC_ACTION_ENA
- PACKET3_WAIT_ON_AVAIL_BUFFER
- PACKET3_WAIT_ON_CE_COUNTER
- PACKET3_WAIT_ON_DE_COUNTER
- PACKET3_WAIT_ON_DE_COUNTER_DIFF
- PACKET3_WAIT_REG_MEM
- PACKET3_WAIT_REG_MEM64
- PACKET3_WRITE_CONST_RAM
- PACKET3_WRITE_CONST_RAM_OFFSET
- PACKET3_WRITE_DATA
- PACKET3_WRITE_GDS_RAM
- PACKETCONFIG1_ADDRESSFILTERING_NODE
- PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST
- PACKETCONFIG1_ADDRESSFILTERING_OFF
- PACKETCONFIG1_DCFREE_MANCHESTER
- PACKETCONFIG1_DCFREE_OFF
- PACKETCONFIG1_DCFREE_WHITENING
- PACKETDEBUG
- PACKETJ
- PACKETJ_CONDITION_CHECK0
- PACKETJ_CONDITION_CHECK1
- PACKETJ_CONDITION_CHECK2
- PACKETJ_CONDITION_CHECK3
- PACKETJ_CONDITION_CHECK4
- PACKETJ_CONDITION_CHECK5
- PACKETJ_CONDITION_CHECK6
- PACKETJ_CONDITION_CHECK7
- PACKETJ_TYPE0
- PACKETJ_TYPE1
- PACKETJ_TYPE2
- PACKETJ_TYPE3
- PACKETJ_TYPE4
- PACKETJ_TYPE5
- PACKETJ_TYPE6
- PACKETJ_TYPE7
- PACKETLEN
- PACKETLEN_MAX
- PACKETLEN_MIN
- PACKETLEN_MIN_MAX
- PACKETPTR
- PACKETS_PER_PAGE
- PACKETS_TO_IGNORE
- PACKET_ACTIVE
- PACKET_ADD_MEMBERSHIP
- PACKET_ARP
- PACKET_AUXDATA
- PACKET_AVCPQ
- PACKET_BAD
- PACKET_BLOCK_MODE1
- PACKET_BLOCK_MODE2
- PACKET_BROADCAST
- PACKET_BUFF_BURST_ACCESS
- PACKET_BUFF_BYTE_ACCESS
- PACKET_CANCEL_ID
- PACKET_CDR
- PACKET_CDRW
- PACKET_COPY_THRESH
- PACKET_CP_DMA
- PACKET_CTRL_CMD
- PACKET_DCBCPQ
- PACKET_DEBOUNCE
- PACKET_DEBUG
- PACKET_DEV_INFO
- PACKET_DEV_KEYB
- PACKET_DEV_TPAD
- PACKET_DHCP
- PACKET_DIAG_FANOUT
- PACKET_DIAG_FILTER
- PACKET_DIAG_INFO
- PACKET_DIAG_MAX
- PACKET_DIAG_MCLIST
- PACKET_DIAG_MEMINFO
- PACKET_DIAG_RX_RING
- PACKET_DIAG_TX_RING
- PACKET_DIAG_UID
- PACKET_DISC_COMPLETE
- PACKET_DISC_EMPTY
- PACKET_DISC_INCOMPLETE
- PACKET_DISC_OTHER
- PACKET_DROP_MEMBERSHIP
- PACKET_DVDR
- PACKET_DVDRW
- PACKET_EAPOL
- PACKET_EGRESS_TIMEOUT
- PACKET_EMPTY
- PACKET_END
- PACKET_FANOUT
- PACKET_FANOUT_CBPF
- PACKET_FANOUT_CPU
- PACKET_FANOUT_DATA
- PACKET_FANOUT_EBPF
- PACKET_FANOUT_FLAG_DEFRAG
- PACKET_FANOUT_FLAG_ROLLOVER
- PACKET_FANOUT_FLAG_UNIQUEID
- PACKET_FANOUT_HASH
- PACKET_FANOUT_LB
- PACKET_FANOUT_MAX
- PACKET_FANOUT_QM
- PACKET_FANOUT_RND
- PACKET_FANOUT_ROLLOVER
- PACKET_FASTROUTE
- PACKET_FENCE
- PACKET_FIELD_DATA_LENGTH
- PACKET_FIELD_DETAIL
- PACKET_FIELD_TRANSACTION
- PACKET_FINISHED_STATE
- PACKET_FLAG_BCAST
- PACKET_FLAG_ERR
- PACKET_FLAG_ETH_TYPE
- PACKET_FLAG_IPV4
- PACKET_FLAG_MCAST
- PACKET_FLAG_PAUSE
- PACKET_FLAG_TCP
- PACKET_FLAG_UDP
- PACKET_FLAG_VLAN_INS
- PACKET_FORMAT_OFFSET
- PACKET_FULL
- PACKET_HDRLEN
- PACKET_HEADER0_CONT_ID_SHIFT
- PACKET_HEADER0_HEADER_SIZE_SHIFT
- PACKET_HEADER0_PACKET_ID_SHIFT
- PACKET_HEADER0_PROTOCOL_I2C
- PACKET_HEADER_PACKET_ID_MASK
- PACKET_HEADER_PACKET_ID_SHIFT
- PACKET_HOST
- PACKET_IDLE_STATE
- PACKET_IGNORE_OUTGOING
- PACKET_INTM
- PACKET_IOCTL_MAGIC
- PACKET_IO_FAST
- PACKET_IO_SLOW
- PACKET_IS_NET_INFO
- PACKET_KERNEL
- PACKET_LENGTH
- PACKET_LIN_DMA
- PACKET_LOOPBACK
- PACKET_LOSS
- PACKET_LRA_VALID
- PACKET_MAX_SECTORS
- PACKET_MAX_SIZE
- PACKET_MCBCQ
- PACKET_MCN
- PACKET_MERGE_SEGS
- PACKET_MODE1
- PACKET_MODE2
- PACKET_MP_DONE
- PACKET_MP_MORE
- PACKET_MR_ALLMULTI
- PACKET_MR_MULTICAST
- PACKET_MR_PROMISC
- PACKET_MR_UNICAST
- PACKET_MSG_LONG
- PACKET_MSG_PROT
- PACKET_MSG_SHORT
- PACKET_MULTICAST
- PACKET_NEXT
- PACKET_NOP
- PACKET_NORMAL
- PACKET_NUM_STATES
- PACKET_NWA_VALID
- PACKET_OFFSET_SZ
- PACKET_ORIGDEV
- PACKET_OTHER
- PACKET_OTHERHOST
- PACKET_OUTGOING
- PACKET_PAGE_OFFSET
- PACKET_PORT_MASK
- PACKET_PTPQ
- PACKET_QDISC_BYPASS
- PACKET_QUEUE_LEN
- PACKET_RCVD
- PACKET_READ_WAIT_STATE
- PACKET_RECOVERY_STATE
- PACKET_RECV_OUTPUT
- PACKET_REJECT
- PACKET_REQUEST
- PACKET_RESERVE
- PACKET_RESERVED
- PACKET_RESPONSE
- PACKET_ROLLOVER_STATS
- PACKET_RX_RING
- PACKET_SENT
- PACKET_SESSION_COMPLETE
- PACKET_SESSION_EMPTY
- PACKET_SESSION_INCOMPLETE
- PACKET_SESSION_RESERVED
- PACKET_SHOW_FANOUT
- PACKET_SHOW_FILTER
- PACKET_SHOW_INFO
- PACKET_SHOW_MCLIST
- PACKET_SHOW_MEMINFO
- PACKET_SHOW_RING_CFG
- PACKET_SIZE
- PACKET_SKB_CB
- PACKET_START
- PACKET_STATISTICS
- PACKET_STOP
- PACKET_TIMEOUT
- PACKET_TIMESTAMP
- PACKET_TRACE
- PACKET_TRACKPOINT
- PACKET_TX_HAS_OFF
- PACKET_TX_RING
- PACKET_TX_TIMESTAMP
- PACKET_TYPE
- PACKET_TYPE0
- PACKET_TYPE1
- PACKET_TYPE2
- PACKET_TYPE3
- PACKET_TYPE_ALL_MULTICAST
- PACKET_TYPE_BROADCAST
- PACKET_TYPE_DIRECTED
- PACKET_TYPE_FS1
- PACKET_TYPE_FS2
- PACKET_TYPE_ID
- PACKET_TYPE_MULTICAST
- PACKET_TYPE_PROMISCUOUS
- PACKET_TYPE_READ
- PACKET_TYPE_UNICAST
- PACKET_TYPE_VRR
- PACKET_TYPE_VTEM
- PACKET_TYPE_WRITE
- PACKET_UNDERRUN
- PACKET_UNKNOWN
- PACKET_UPQ
- PACKET_USER
- PACKET_USE_LS
- PACKET_V3_HEAD
- PACKET_V3_TAIL
- PACKET_V4_HEAD
- PACKET_V4_MOTION
- PACKET_V4_STATUS
- PACKET_VERSION
- PACKET_VNET_HDR
- PACKET_WAITING_STATE
- PACKET_WAIT_TIME
- PACKET_WREG_32
- PACKET_WREG_BULK
- PACKET_WRITABLE
- PACKET_WRITE_WAIT_STATE
- PACKING_BYTES_PW
- PACKING_DIR_SHIFT
- PACKING_LEN_SHIFT
- PACKING_START_SHIFT
- PACKING_STOP_BIT
- PACKING_VECTOR_SHIFT
- PACKPP
- PACK_0
- PACK_1
- PACK_2
- PACK_3
- PACK_3D_COL_INT
- PACK_3D_FRAME_INT
- PACK_3D_H_ROW_INT
- PACK_3D_V_ROW_INT
- PACK_D
- PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK_MASK
- PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_ACK__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED_MASK
- PACK_FIFO_ERROR__PACK_FIFO_C_OVERFLOW_OCCURED__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK_MASK
- PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_ACK__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED_MASK
- PACK_FIFO_ERROR__PACK_FIFO_C_UNDERFLOW_OCCURED__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK_MASK
- PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_ACK__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED_MASK
- PACK_FIFO_ERROR__PACK_FIFO_L_OVERFLOW_OCCURED__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK_MASK
- PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_ACK__SHIFT
- PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED_MASK
- PACK_FIFO_ERROR__PACK_FIFO_L_UNDERFLOW_OCCURED__SHIFT
- PACK_LEGACY_SCPI_CMD
- PACK_OP_DEVLIST_REPLY
- PACK_OP_DEVLIST_REQUEST
- PACK_OP_EXPORT_REPLY
- PACK_OP_EXPORT_REQUEST
- PACK_OP_IMPORT_REPLY
- PACK_OP_IMPORT_REQUEST
- PACK_OP_UNEXPORT_REPLY
- PACK_OP_UNEXPORT_REQUEST
- PACK_S
- PACK_SCPI_CMD
- PACR
- PACR_DS
- PACR_EXTMINTE
- PACR_EXTMPRI
- PACR_INTMINTE
- PACR_INTMPRI
- PACR_PKMD
- PACT_CATEGORY
- PAC_AUTOGAIN_IGNORE_FRAMES
- PAC_BASE_ADDRESS_SILICON
- PAC_REG_BASE
- PAC_RESET_KEYS
- PAC_SHARED_MEMORY_SILICON
- PAD
- PADATA
- PADATA_ADDR
- PADATA_ATTR_RO
- PADATA_ATTR_RW
- PADATA_CPU_PARALLEL
- PADATA_CPU_SERIAL
- PADATA_H
- PADATA_INIT
- PADATA_INVALID
- PADATA_RESET
- PADBAR
- PADBYTES
- PADC
- PADCFG0
- PADCFG0_GPIORXDIS
- PADCFG0_GPIORXSTATE
- PADCFG0_GPIOTXDIS
- PADCFG0_GPIOTXSTATE
- PADCFG0_GPIROUTIOXAPIC
- PADCFG0_GPIROUTNMI
- PADCFG0_GPIROUTSCI
- PADCFG0_GPIROUTSMI
- PADCFG0_PMODE_GPIO
- PADCFG0_PMODE_MASK
- PADCFG0_PMODE_SHIFT
- PADCFG0_PREGFRXSEL
- PADCFG0_RXEVCFG_DISABLED
- PADCFG0_RXEVCFG_EDGE
- PADCFG0_RXEVCFG_EDGE_BOTH
- PADCFG0_RXEVCFG_LEVEL
- PADCFG0_RXEVCFG_MASK
- PADCFG0_RXEVCFG_SHIFT
- PADCFG0_RXINV
- PADCFG1
- PADCFG1_TERM_1K
- PADCFG1_TERM_20K
- PADCFG1_TERM_2K
- PADCFG1_TERM_5K
- PADCFG1_TERM_MASK
- PADCFG1_TERM_SHIFT
- PADCFG1_TERM_UP
- PADCFG2
- PADCFG2_DEBEN
- PADCFG2_DEBOUNCE_MASK
- PADCFG2_DEBOUNCE_SHIFT
- PADCONF
- PADCONF_SAVE_DONE
- PADCTL_OFFSET
- PADCTL_PAD_OUT_EN_MASK
- PADDING
- PADDING_8ALIGNED
- PADDING_MASK
- PADDING_STREAM
- PADDR
- PADDRH
- PADDRR
- PADDRW
- PADDR_A
- PADDR_B
- PADEnable
- PADIR
- PADIR_ADDR
- PADI_CODE
- PADLOCK_ALIGNMENT
- PADLOCK_COMPOSITE_PRIORITY
- PADLOCK_CRA_PRIORITY
- PADOWN_BITS
- PADOWN_GPP
- PADOWN_MASK
- PADOWN_SHIFT
- PADO_CODE
- PADR
- PADRH
- PADRL
- PADRM
- PADR_CODE
- PADS_AS_GPIO_REG0_MASK
- PADS_AS_GPIO_REG7_MASK
- PADS_AS_GPIO_REGS_MASK
- PADS_CODE
- PADS_CTL
- PADS_CTL_IDDQ_1L
- PADS_CTL_RX_DATA_EN_1L
- PADS_CTL_SEL
- PADS_CTL_TX_DATA_EN_1L
- PADS_DRIVE_STRENGTH0
- PADS_DRIVE_STRENGTH_12MA
- PADS_DRIVE_STRENGTH_2MA
- PADS_DRIVE_STRENGTH_4MA
- PADS_DRIVE_STRENGTH_8MA
- PADS_DRIVE_STRENGTH_MASK
- PADS_DRIVE_STRENGTH_REG
- PADS_DRIVE_STRENGTH_SHIFT
- PADS_FUNCTION_SELECT0
- PADS_FUNCTION_SELECT1
- PADS_FUNCTION_SELECT2
- PADS_MASK
- PADS_MAXBIT
- PADS_PLL_CTL_LOCKDET
- PADS_PLL_CTL_REFCLK_EXTERNAL
- PADS_PLL_CTL_REFCLK_INTERNAL_CML
- PADS_PLL_CTL_REFCLK_INTERNAL_CMOS
- PADS_PLL_CTL_REFCLK_MASK
- PADS_PLL_CTL_RST_B4SM
- PADS_PLL_CTL_TEGRA20
- PADS_PLL_CTL_TEGRA30
- PADS_PLL_CTL_TXCLKREF_BUF_EN
- PADS_PLL_CTL_TXCLKREF_DIV10
- PADS_PLL_CTL_TXCLKREF_DIV5
- PADS_PLL_CTL_TXCLKREF_MASK
- PADS_PULL_CR
- PADS_PU_PD0
- PADS_PU_PD_BUS
- PADS_PU_PD_DOWN
- PADS_PU_PD_HIGHZ
- PADS_PU_PD_MASK
- PADS_PU_PD_REG
- PADS_PU_PD_SHIFT
- PADS_PU_PD_UP
- PADS_REFCLK_BIAS
- PADS_REFCLK_CFG0
- PADS_REFCLK_CFG1
- PADS_REFCLK_CFG_DRVI_SHIFT
- PADS_REFCLK_CFG_E_TERM_SHIFT
- PADS_REFCLK_CFG_PREDI_SHIFT
- PADS_REFCLK_CFG_TERM_SHIFT
- PADS_SCENARIO_SELECT
- PADS_SCHMITT_EN0
- PADS_SCHMITT_EN_BIT
- PADS_SCHMITT_EN_REG
- PADS_SLEW_RATE0
- PADS_SLEW_RATE_BIT
- PADS_SLEW_RATE_REG
- PADT_CODE
- PAD_ACCOUNTING
- PAD_AGPINPUT_DELAY
- PAD_BRIDGED
- PAD_BYTE
- PAD_BYTES
- PAD_CFG_DW0_GPP_D_0
- PAD_CIS
- PAD_CMD_RD_RXDLY2_SEL
- PAD_CMD_RD_RXDLY_SEL
- PAD_CMD_RXDLY
- PAD_CMD_RXDLY2
- PAD_CMD_TUNE
- PAD_CMD_TUNE_RX_DLY3
- PAD_CMD_TX_DLY
- PAD_CRC
- PAD_CTL
- PAD_CTLR_MISC
- PAD_CTLR_STRENGTH
- PAD_CTLR_UPDATE
- PAD_CTL_100K_PD
- PAD_CTL_100K_PU
- PAD_CTL_22K_PU
- PAD_CTL_47K_PU
- PAD_CTL_DRV_HIGH
- PAD_CTL_DRV_MAX
- PAD_CTL_DRV_NORMAL
- PAD_CTL_DSE_HIGH
- PAD_CTL_DSE_LOW
- PAD_CTL_DSE_MAX
- PAD_CTL_DSE_MED
- PAD_CTL_DVS
- PAD_CTL_HYS
- PAD_CTL_HYS_CMOS
- PAD_CTL_HYS_SCHMITZ
- PAD_CTL_LOOPBACK
- PAD_CTL_MASK
- PAD_CTL_NOLOOPBACK
- PAD_CTL_ODE
- PAD_CTL_ODE_CMOS
- PAD_CTL_ODE_OpenDrain
- PAD_CTL_PKE
- PAD_CTL_PKE_ENABLE
- PAD_CTL_PKE_NONE
- PAD_CTL_PUE
- PAD_CTL_PUE_KEEPER
- PAD_CTL_PUE_PUD
- PAD_CTL_PUS_100K_DOWN
- PAD_CTL_PUS_100K_UP
- PAD_CTL_PUS_22K_UP
- PAD_CTL_PUS_47K_UP
- PAD_CTL_SRE_FAST
- PAD_CTL_SRE_SLOW
- PAD_CTRL
- PAD_CTRL1_SW_DPDT_SEL_DATA
- PAD_DAT_RD_RXDLY
- PAD_DAT_RD_RXDLY2
- PAD_DAT_RD_RXDLY2_SEL
- PAD_DAT_RD_RXDLY_SEL
- PAD_DBG
- PAD_DELAY_MAX
- PAD_DEVICE_ID
- PAD_DIRECTION_SEL_0
- PAD_DIRECTION_SEL_1
- PAD_DIRECTION_SEL_2
- PAD_DRIVE_STRENGTH_10_MA
- PAD_DRIVE_STRENGTH_12_MA
- PAD_DRIVE_STRENGTH_14_MA
- PAD_DRIVE_STRENGTH_16_MA
- PAD_DRIVE_STRENGTH_2_MA
- PAD_DRIVE_STRENGTH_4_MA
- PAD_DRIVE_STRENGTH_6_MA
- PAD_DRIVE_STRENGTH_8_MA
- PAD_DRIVE_STRENGTH_MASK
- PAD_DRV0
- PAD_DRV1
- PAD_DRV2
- PAD_DS_TUNE
- PAD_DS_TUNE_DLY1
- PAD_DS_TUNE_DLY2
- PAD_DS_TUNE_DLY3
- PAD_ERR
- PAD_ERROR_BIT
- PAD_FUNCTION_EN_0
- PAD_FUNCTION_EN_1
- PAD_FUNCTION_EN_2
- PAD_FUNCTION_EN_3
- PAD_FUNCTION_EN_4
- PAD_FUNCTION_EN_5
- PAD_FUNCTION_EN_6
- PAD_FUNCTION_EN_7
- PAD_FUNCTION_EN_8
- PAD_HCI_SEL
- PAD_HWPD_IDN
- PAD_HYSTERESIS_ENA
- PAD_HYSTERESIS_ENA_MASK
- PAD_ID
- PAD_INFO
- PAD_INFO_PULLCTL
- PAD_INFO_PULLCTL_ST
- PAD_INFO_ST
- PAD_INPUT_PATH_DIS
- PAD_INPUT_PATH_DIS_MASK
- PAD_LOCKED
- PAD_LOCKED_FULL
- PAD_LOCKED_TX
- PAD_MANUAL_OVERRIDE
- PAD_MODE_GTX_CLK_DELAY
- PAD_MODE_GTX_CLK_INV
- PAD_MODE_MASK
- PAD_MODE_MII
- PAD_MODE_RGMII
- PAD_MSG
- PAD_MUX_GPIO_00_SYNC_BASEADDR
- PAD_MUX_UART_RX_C_PINMUX_BASEADDR
- PAD_NOACCOUNT
- PAD_OUT
- PAD_OUTPUT_ENABLE
- PAD_OUTPUT_ENABLE_MS
- PAD_OWN_GPP_D_0
- PAD_POW2
- PAD_PULLCTL0
- PAD_PULLCTL1
- PAD_PULLCTL2
- PAD_PULLCTL_CONF
- PAD_PULL_DOWN_ENA
- PAD_PULL_DOWN_ENA_MASK
- PAD_PULL_UP_ENA
- PAD_PULL_UP_ENA_MASK
- PAD_PU_PD
- PAD_PU_PD_OFF
- PAD_PU_PD_ON_MS_SOCK0
- PAD_PU_PD_ON_MS_SOCK1
- PAD_RXDLY_SEL
- PAD_SEL
- PAD_SHARED_IP_EN_1
- PAD_SHARED_IP_EN_2
- PAD_SHIFT
- PAD_SIGNAL_ANALOG
- PAD_SIGNAL_AUDIO
- PAD_SIGNAL_DEFAULT
- PAD_SIGNAL_DV
- PAD_SIZE
- PAD_SLEW_RATE_ENA
- PAD_SLEW_RATE_ENA_MASK
- PAD_SR0
- PAD_SR1
- PAD_SR2
- PAD_ST0
- PAD_ST1
- PAD_ST_CONF
- PAD_TRACE
- PAD_T_16ST
- PAD_T_4WE_PD
- PAD_T_4WE_PU
- PAD_T_AD
- PAD_T_M31_0204_PD
- PAD_T_M31_0204_PU
- PAD_T_M31_0610_PD
- PAD_T_M31_0610_PU
- PAD_UNLOCKED
- PAD_VAL
- PADbit
- PAES_MAX_KEYSIZE
- PAES_MIN_KEYSIZE
- PAG
- PAGE0
- PAGE0_ALWAYS_MAPPED
- PAGE0_BTEN
- PAGE0_BTEN_BIT
- PAGE0_SELECT
- PAGE1_SEL
- PAGE1_SELECT
- PAGE4
- PAGE5
- PAGE6
- PAGEBLOCK_FLAGS_H
- PAGECACHE_TAG_DIRTY
- PAGECACHE_TAG_TOWRITE
- PAGECACHE_TAG_WRITEBACK
- PAGED_ADDR_BNDRY
- PAGEFLAG
- PAGEFLAG_FALSE
- PAGEFMT_2K_4K
- PAGEFMT_4K_8K
- PAGEFMT_512_2K
- PAGEFMT_8K_16K
- PAGEFMT_FDM_ECC_SHIFT
- PAGEFMT_FDM_SHIFT
- PAGEFMT_SEC_SEL_512
- PAGELIST_ENTRIES_PER_PAGE
- PAGELIST_READ
- PAGELIST_READ_WITH_FRAGMENTS
- PAGELIST_WRITE
- PAGEMAP_ANONYMOUS
- PAGEMAP_BATCH
- PAGEMAP_BUFFERS
- PAGEMAP_FILE
- PAGEMAP_MAPPED
- PAGEMAP_MAPPEDDISK
- PAGEMAP_PFN
- PAGEMAP_PRESENT
- PAGEMAP_SWAPBACKED
- PAGEMAP_SWAPCACHE
- PAGEMAP_WALK_MASK
- PAGEMAP_WALK_SIZE
- PAGEMODE_REG
- PAGEOUT
- PAGEOUTRUN
- PAGEREF_ACTIVATE
- PAGEREF_KEEP
- PAGEREF_RECLAIM
- PAGEREF_RECLAIM_CLEAN
- PAGES
- PAGES2KB
- PAGESEL
- PAGESIZE
- PAGESIZE_MASK
- PAGESIZE_SHIFT
- PAGESZ_16K
- PAGESZ_16M
- PAGESZ_1K
- PAGESZ_1M
- PAGESZ_256K
- PAGESZ_4K
- PAGESZ_4M
- PAGESZ_64K
- PAGES_4K_SPANNED
- PAGES_FOR_IO
- PAGES_IN_2M
- PAGES_NR
- PAGES_PER_BLOCK
- PAGES_PER_BLOCK__VALUE
- PAGES_PER_CHUNK
- PAGES_PER_RANGE
- PAGES_PER_REGION
- PAGES_PER_SECTION
- PAGES_PER_SEGMENT
- PAGES_PER_SGE
- PAGES_PER_SGE_SHIFT
- PAGES_PER_SUBSECTION
- PAGES_REQUIRED
- PAGES_SHIFT_16
- PAGES_SHIFT_24
- PAGES_SHIFT_32
- PAGES_SHIFT_8
- PAGES_TO_KB
- PAGES_TO_MB
- PAGES_TO_MiB
- PAGETABLE_LEVELS
- PAGEVEC_SIZE
- PAGE_0_ATTR
- PAGE_2K
- PAGE_2_EXP_SIZE
- PAGE_A1_IN
- PAGE_A1_OUT
- PAGE_A2_IN
- PAGE_A2_OUT
- PAGE_ABSDATA
- PAGE_ACC
- PAGE_ACCESSED_BIT
- PAGE_ACCESS_ERR_MASK
- PAGE_ACTIVATE
- PAGE_ACTOR_H
- PAGE_ADDR_SHIFT
- PAGE_ADD_HUGE_SHIFT
- PAGE_ADD_SHIFT
- PAGE_AGP
- PAGE_ALIGN
- PAGE_ALIGNED
- PAGE_ALIGNED_DATA
- PAGE_ALLOC_COSTLY_ORDER
- PAGE_ALL_ERASED
- PAGE_ATTR
- PAGE_BITS
- PAGE_BIT_SHIFT
- PAGE_BUDDY_MAPCOUNT_VALUE
- PAGE_CACHE_BITS
- PAGE_CACHE_L1
- PAGE_CACHE_SECTORS
- PAGE_CACHE_SECTOR_SHIFT
- PAGE_CHUNK_SIZE
- PAGE_CLAIMED
- PAGE_CLEAN
- PAGE_CLEAR_DIRTY
- PAGE_CNT
- PAGE_COPY
- PAGE_COPY_C
- PAGE_COPY_EXEC
- PAGE_COPY_NOEXEC
- PAGE_COPY_READ_EXEC
- PAGE_COPY_X
- PAGE_CORRECTABLE
- PAGE_COUNT
- PAGE_COUNTER_MASK
- PAGE_COUNTER_MAX
- PAGE_COUNTER_RATIO
- PAGE_COUNTER_SHIFT
- PAGE_CPA_TEST
- PAGE_DATA_LEN
- PAGE_DEFAULT_ACC
- PAGE_DEFAULT_KEY
- PAGE_DEVICE
- PAGE_DIRTY
- PAGE_DIRTY_BIT
- PAGE_DIR_OFFSET
- PAGE_DIV
- PAGE_DOWN
- PAGE_END
- PAGE_END_NR
- PAGE_END_WRITEBACK
- PAGE_ERASE
- PAGE_ERASED
- PAGE_EVBITS
- PAGE_EXEC
- PAGE_EXECREAD
- PAGE_EXT_IDLE
- PAGE_EXT_OWNER
- PAGE_EXT_OWNER_ALLOCATED
- PAGE_EXT_YOUNG
- PAGE_FACTOR
- PAGE_FAULT_ERROR_CODE_MASK
- PAGE_FAULT_ERROR_CODE_MATCH
- PAGE_FLAGS_CHECK_AT_FREE
- PAGE_FLAGS_CHECK_AT_PREP
- PAGE_FLAGS_H
- PAGE_FLAGS_LAYOUT_H
- PAGE_FLAGS_PRIVATE
- PAGE_FRAG_CACHE_MAX_ORDER
- PAGE_FRAG_CACHE_MAX_SIZE
- PAGE_FREE_INTERVAL
- PAGE_GATE
- PAGE_GATEWAY
- PAGE_GLOBAL
- PAGE_HEADLESS
- PAGE_HYP
- PAGE_HYP_DEVICE
- PAGE_HYP_EXEC
- PAGE_HYP_RO
- PAGE_IF_HW
- PAGE_IF_SW
- PAGE_INIT
- PAGE_INUSE
- PAGE_INVALID
- PAGE_IN_4K
- PAGE_IO
- PAGE_IO_SIZE
- PAGE_IS_EMPTY
- PAGE_KEEP
- PAGE_KERNEL
- PAGE_KERNELRX
- PAGE_KERNEL_CI
- PAGE_KERNEL_EXEC
- PAGE_KERNEL_EXEC_CONT
- PAGE_KERNEL_EXEC_NOENC
- PAGE_KERNEL_IO
- PAGE_KERNEL_IO_NOCACHE
- PAGE_KERNEL_LARGE
- PAGE_KERNEL_LARGE_EXEC
- PAGE_KERNEL_NC
- PAGE_KERNEL_NCG
- PAGE_KERNEL_NOCACHE
- PAGE_KERNEL_NOENC
- PAGE_KERNEL_NO_CACHE
- PAGE_KERNEL_PCC
- PAGE_KERNEL_RO
- PAGE_KERNEL_ROX
- PAGE_KERNEL_RWX
- PAGE_KERNEL_RX
- PAGE_KERNEL_TEXT
- PAGE_KERNEL_UC
- PAGE_KERNEL_UNC
- PAGE_KERNEL_UNCACHED
- PAGE_KERNEL_VVAR
- PAGE_KERNEL_X
- PAGE_KEY_DATA_SIZE
- PAGE_LEN
- PAGE_LOCK
- PAGE_LO_MASK
- PAGE_MAPCOUNT_RESERVE
- PAGE_MAPPING_ANON
- PAGE_MAPPING_ENABLE
- PAGE_MAPPING_FLAGS
- PAGE_MAPPING_KSM
- PAGE_MAPPING_MOVABLE
- PAGE_MASK
- PAGE_MASK_2MB
- PAGE_MEMORY
- PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK
- PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT
- PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK
- PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT
- PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK
- PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT
- PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK
- PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT
- PAGE_MOD
- PAGE_MODE_1_LEVEL
- PAGE_MODE_2_LEVEL
- PAGE_MODE_3_LEVEL
- PAGE_MODE_4_LEVEL
- PAGE_MODE_5_LEVEL
- PAGE_MODE_6_LEVEL
- PAGE_MODE_7_LEVEL
- PAGE_MODE_NONE
- PAGE_MODE_VALUES_E2
- PAGE_MODE_VALUES_E3
- PAGE_MODIFIED_BIT
- PAGE_MODIFY
- PAGE_NAME
- PAGE_NOEXEC
- PAGE_NONE
- PAGE_NONE_C
- PAGE_NOTCORRECTABLE
- PAGE_OFFLINE_MAPCOUNT_VALUE
- PAGE_OFFSET
- PAGE_OFFSET_NR
- PAGE_OFFSET_RAW
- PAGE_OK
- PAGE_ORDER_TO_SIZE
- PAGE_OWNER_STACK_DEPTH
- PAGE_PER_GROUP_2_EXP_SIZE
- PAGE_POISON
- PAGE_POISON_PATTERN
- PAGE_PRESENT_MASK
- PAGE_PRG_1
- PAGE_PRG_2
- PAGE_PROGRAM
- PAGE_PROTECT
- PAGE_PTR
- PAGE_PTRS_PER_BVEC
- PAGE_RDWR
- PAGE_READ
- PAGE_READONLY
- PAGE_READONLY_C
- PAGE_READONLY_EXEC
- PAGE_READONLY_X
- PAGE_READ_EXEC
- PAGE_READ_REGS_E2
- PAGE_READ_REGS_E3
- PAGE_REG
- PAGE_RO
- PAGE_RW
- PAGE_RWX
- PAGE_RX
- PAGE_RX_INT
- PAGE_S2
- PAGE_S2_DEVICE
- PAGE_S2_MEMATTR
- PAGE_S2_XN
- PAGE_SCAN_TYPE_INTERLACED
- PAGE_SCAN_TYPE_STANDARD
- PAGE_SECTION_MASK
- PAGE_SECTORS
- PAGE_SECTORS_SHIFT
- PAGE_SEL_MASK
- PAGE_SEL_OFFSET_SHIFT
- PAGE_SEL_REG
- PAGE_SEL_SHIFT
- PAGE_SET_ERROR
- PAGE_SET_PRIVATE2
- PAGE_SET_WRITEBACK
- PAGE_SHARED
- PAGE_SHARED_C
- PAGE_SHARED_EXEC
- PAGE_SHARED_X
- PAGE_SHIFT
- PAGE_SHIFT_16M
- PAGE_SHIFT_2MB
- PAGE_SHIFT_4K
- PAGE_SHIFT_4KB
- PAGE_SHIFT_512K
- PAGE_SHIFT_64K
- PAGE_SHIFT_8M
- PAGE_SIZE
- PAGE_SIZE_0
- PAGE_SIZE_1
- PAGE_SIZE_128
- PAGE_SIZE_16MB_64KB
- PAGE_SIZE_256
- PAGE_SIZE_2MB
- PAGE_SIZE_4K
- PAGE_SIZE_4KB
- PAGE_SIZE_4K_ENABLE
- PAGE_SIZE_512
- PAGE_SIZE_ALIGN
- PAGE_SIZE_LEVEL
- PAGE_SIZE_MASK
- PAGE_SIZE_PTE
- PAGE_SIZE_PTE_COUNT
- PAGE_SIZE_REM
- PAGE_SIZE_RX_8723B
- PAGE_SIZE_TX_8723B
- PAGE_STALE
- PAGE_STATES_H
- PAGE_STATUS
- PAGE_SUBSECTION_MASK
- PAGE_SUCCESS
- PAGE_SZ
- PAGE_TABLE
- PAGE_TABLE_BLOCK_SIZE
- PAGE_TABLE_DEPTH
- PAGE_TABLE_SIZE
- PAGE_TBL_RID
- PAGE_TYPE_BASE
- PAGE_TYPE_OF_BIO
- PAGE_TYPE_OPS
- PAGE_UNALLOCATED
- PAGE_UNDEF
- PAGE_UNLOCK
- PAGE_UP
- PAGE_URXKRWX_V2
- PAGE_USERIO
- PAGE_USE_COUNT
- PAGE_UXKRWX_V1
- PAGE_UXKRWX_V2
- PAGE_U_NONE
- PAGE_U_R
- PAGE_U_W_R
- PAGE_U_X_R
- PAGE_U_X_W_R
- PAGE_VALID
- PAGE_VALID_BIT
- PAGE_WAIT_TABLE_BITS
- PAGE_WAIT_TABLE_SIZE
- PAGE_WRITE
- PAGE_WRITEONLY
- PAGE_WRITE_EXEC
- PAGE_WRITE_REGS_E2
- PAGE_WRITE_REGS_E3
- PAGGRE_SIZE_E
- PAGING_ADDR_SIG
- PAGING_BLOCK_SIZE
- PAGING_CMD_IS_ENABLED
- PAGING_CMD_IS_SECURED
- PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS
- PAGING_SEPARATOR_SECTION
- PAGING_TLV_SECURE_MASK
- PAIRWISE_KEY
- PAIRWISE_KEYIDX
- PAIRWISE_KEY_ENTRY
- PAIRWISE_KEY_TABLE_BASE
- PAIRWISE_TA_ENTRY
- PAIRWISE_TA_TABLE_BASE
- PAIRWISE_USAGE
- PAL60_SUPPORT
- PALCN_SUPPORT
- PALEN
- PALETCTL
- PALETTE
- PALETTE2_SNOOP_EN
- PALETTE_10_ENTRIES
- PALETTE_10_SIZE
- PALETTE_30_DATA
- PALETTE_8_BLUE_SHIFT
- PALETTE_8_ENTRIES
- PALETTE_8_GREEN_SHIFT
- PALETTE_8_MASK
- PALETTE_8_RED_SHIFT
- PALETTE_8_SIZE
- PALETTE_A
- PALETTE_ACCESS_CNTL
- PALETTE_AND_DATA
- PALETTE_B
- PALETTE_BUFF_CLEAR
- PALETTE_C
- PALETTE_DATA
- PALETTE_DATA_AUTO_FILL
- PALETTE_DATA_CONTROL_PARAMETERS_V3
- PALETTE_DATA_READ
- PALETTE_DATA_WRITE
- PALETTE_ENTRIES_NO
- PALETTE_INDEX
- PALETTE_NR
- PALETTE_ONLY
- PALETTE_SIZE
- PALFilterTableAddr
- PALHT
- PALIGN
- PALINFO_VERSION
- PALMAS_ADC_CH0_CURRENT_SRC_0
- PALMAS_ADC_CH0_CURRENT_SRC_15
- PALMAS_ADC_CH0_CURRENT_SRC_20
- PALMAS_ADC_CH0_CURRENT_SRC_5
- PALMAS_ADC_CH3_CURRENT_SRC_0
- PALMAS_ADC_CH3_CURRENT_SRC_10
- PALMAS_ADC_CH3_CURRENT_SRC_400
- PALMAS_ADC_CH3_CURRENT_SRC_800
- PALMAS_ADC_CHAN_IIO
- PALMAS_ADC_CH_IN0
- PALMAS_ADC_CH_IN1
- PALMAS_ADC_CH_IN10
- PALMAS_ADC_CH_IN11
- PALMAS_ADC_CH_IN12
- PALMAS_ADC_CH_IN13
- PALMAS_ADC_CH_IN14
- PALMAS_ADC_CH_IN15
- PALMAS_ADC_CH_IN2
- PALMAS_ADC_CH_IN3
- PALMAS_ADC_CH_IN4
- PALMAS_ADC_CH_IN5
- PALMAS_ADC_CH_IN6
- PALMAS_ADC_CH_IN7
- PALMAS_ADC_CH_IN8
- PALMAS_ADC_CH_IN9
- PALMAS_ADC_CH_MAX
- PALMAS_ADC_CONVERSION_TIMEOUT
- PALMAS_ADC_INFO
- PALMAS_ALARM_DAYS_REG
- PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK
- PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT
- PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK
- PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT
- PALMAS_ALARM_HOURS_REG
- PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK
- PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT
- PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK
- PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT
- PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM
- PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT
- PALMAS_ALARM_MINUTES_REG
- PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK
- PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT
- PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK
- PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT
- PALMAS_ALARM_MONTHS_REG
- PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK
- PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT
- PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1
- PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT
- PALMAS_ALARM_SECONDS_REG
- PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK
- PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT
- PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK
- PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT
- PALMAS_ALARM_YEARS_REG
- PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK
- PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT
- PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK
- PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT
- PALMAS_BACKUP0
- PALMAS_BACKUP0_BACKUP_MASK
- PALMAS_BACKUP0_BACKUP_SHIFT
- PALMAS_BACKUP1
- PALMAS_BACKUP1_BACKUP_MASK
- PALMAS_BACKUP1_BACKUP_SHIFT
- PALMAS_BACKUP2
- PALMAS_BACKUP2_BACKUP_MASK
- PALMAS_BACKUP2_BACKUP_SHIFT
- PALMAS_BACKUP3
- PALMAS_BACKUP3_BACKUP_MASK
- PALMAS_BACKUP3_BACKUP_SHIFT
- PALMAS_BACKUP4
- PALMAS_BACKUP4_BACKUP_MASK
- PALMAS_BACKUP4_BACKUP_SHIFT
- PALMAS_BACKUP5
- PALMAS_BACKUP5_BACKUP_MASK
- PALMAS_BACKUP5_BACKUP_SHIFT
- PALMAS_BACKUP6
- PALMAS_BACKUP6_BACKUP_MASK
- PALMAS_BACKUP6_BACKUP_SHIFT
- PALMAS_BACKUP7
- PALMAS_BACKUP7_BACKUP_MASK
- PALMAS_BACKUP7_BACKUP_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL
- PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG
- PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN
- PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK
- PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN
- PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT
- PALMAS_BASE_TO_REG
- PALMAS_BASE_TO_SLAVE
- PALMAS_BATDEBOUNCING
- PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS
- PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT
- PALMAS_BATDEBOUNCING_BEXT_DEB_MASK
- PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT
- PALMAS_BATDEBOUNCING_BINS_DEB_MASK
- PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT
- PALMAS_BATREMOVAL_IRQ
- PALMAS_BATTERY_BOUNCE
- PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK
- PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT
- PALMAS_BOOT_STATUS
- PALMAS_BOOT_STATUS_BOOT0
- PALMAS_BOOT_STATUS_BOOT0_SHIFT
- PALMAS_BOOT_STATUS_BOOT1
- PALMAS_BOOT_STATUS_BOOT1_SHIFT
- PALMAS_CHARG_DET_N_VBUS_OVV_IRQ
- PALMAS_CHIP_CHARGER_ID
- PALMAS_CHIP_ID
- PALMAS_CHIP_OLD_ID
- PALMAS_CLK32KGAUDIO_CTRL
- PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE
- PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP
- PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT
- PALMAS_CLK32KGAUDIO_CTRL_RESERVED3
- PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT
- PALMAS_CLK32KGAUDIO_CTRL_STATUS
- PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT
- PALMAS_CLK32KG_CTRL
- PALMAS_CLK32KG_CTRL_MODE_ACTIVE
- PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_CLK32KG_CTRL_MODE_SLEEP
- PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT
- PALMAS_CLK32KG_CTRL_STATUS
- PALMAS_CLK32KG_CTRL_STATUS_SHIFT
- PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1
- PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2
- PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP
- PALMAS_DATASHEET_NAME
- PALMAS_DAYS_REG
- PALMAS_DAYS_REG_DAY0_MASK
- PALMAS_DAYS_REG_DAY0_SHIFT
- PALMAS_DAYS_REG_DAY1_MASK
- PALMAS_DAYS_REG_DAY1_SHIFT
- PALMAS_DEV_CTRL
- PALMAS_DEV_CTRL_DEV_ON
- PALMAS_DEV_CTRL_DEV_ON_SHIFT
- PALMAS_DEV_CTRL_DEV_STATUS_MASK
- PALMAS_DEV_CTRL_DEV_STATUS_SHIFT
- PALMAS_DEV_CTRL_SW_RST
- PALMAS_DEV_CTRL_SW_RST_SHIFT
- PALMAS_DVFS_BASE
- PALMAS_ENABLE1_LDO_ASSIGN1
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO1
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO2
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO3
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO4
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO5
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO6
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO7
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO8
- PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN2
- PALMAS_ENABLE1_LDO_ASSIGN2_LDO9
- PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN
- PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT
- PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB
- PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN
- PALMAS_ENABLE1_RES_ASSIGN_CLK32KG
- PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO
- PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_REGEN1
- PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_REGEN2
- PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_REGEN3
- PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_SYSEN1
- PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT
- PALMAS_ENABLE1_RES_ASSIGN_SYSEN2
- PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9
- PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO1
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO2
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO3
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO4
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO5
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO6
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO7
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO8
- PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN2
- PALMAS_ENABLE2_LDO_ASSIGN2_LDO9
- PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN
- PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT
- PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB
- PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN
- PALMAS_ENABLE2_RES_ASSIGN_CLK32KG
- PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO
- PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_REGEN1
- PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_REGEN2
- PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_REGEN3
- PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_SYSEN1
- PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT
- PALMAS_ENABLE2_RES_ASSIGN_SYSEN2
- PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9
- PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT
- PALMAS_EXTERNAL_REQSTR_ID_CLK32KG
- PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO
- PALMAS_EXTERNAL_REQSTR_ID_LDO1
- PALMAS_EXTERNAL_REQSTR_ID_LDO2
- PALMAS_EXTERNAL_REQSTR_ID_LDO3
- PALMAS_EXTERNAL_REQSTR_ID_LDO4
- PALMAS_EXTERNAL_REQSTR_ID_LDO5
- PALMAS_EXTERNAL_REQSTR_ID_LDO6
- PALMAS_EXTERNAL_REQSTR_ID_LDO7
- PALMAS_EXTERNAL_REQSTR_ID_LDO8
- PALMAS_EXTERNAL_REQSTR_ID_LDO9
- PALMAS_EXTERNAL_REQSTR_ID_LDOLN
- PALMAS_EXTERNAL_REQSTR_ID_LDOUSB
- PALMAS_EXTERNAL_REQSTR_ID_MAX
- PALMAS_EXTERNAL_REQSTR_ID_REGEN1
- PALMAS_EXTERNAL_REQSTR_ID_REGEN2
- PALMAS_EXTERNAL_REQSTR_ID_REGEN3
- PALMAS_EXTERNAL_REQSTR_ID_SMPS10
- PALMAS_EXTERNAL_REQSTR_ID_SMPS12
- PALMAS_EXTERNAL_REQSTR_ID_SMPS3
- PALMAS_EXTERNAL_REQSTR_ID_SMPS45
- PALMAS_EXTERNAL_REQSTR_ID_SMPS6
- PALMAS_EXTERNAL_REQSTR_ID_SMPS7
- PALMAS_EXTERNAL_REQSTR_ID_SMPS8
- PALMAS_EXTERNAL_REQSTR_ID_SMPS9
- PALMAS_EXTERNAL_REQSTR_ID_SYSEN1
- PALMAS_EXTERNAL_REQSTR_ID_SYSEN2
- PALMAS_EXT_CHRG_CTRL
- PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN
- PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT
- PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN
- PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT
- PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS
- PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT
- PALMAS_EXT_CHRG_CTRL_CHRG_DET_N
- PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT
- PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS
- PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT
- PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY
- PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT
- PALMAS_EXT_CONTROL_ENABLE1
- PALMAS_EXT_CONTROL_ENABLE2
- PALMAS_EXT_CONTROL_NSLEEP
- PALMAS_EXT_CONTROL_PIN_ENABLE1
- PALMAS_EXT_CONTROL_PIN_ENABLE2
- PALMAS_EXT_CONTROL_PIN_NSLEEP
- PALMAS_EXT_REQ
- PALMAS_FBI_BB_IRQ
- PALMAS_GPADC_AUTO_0_IRQ
- PALMAS_GPADC_AUTO_1_IRQ
- PALMAS_GPADC_AUTO_CONV0_LSB
- PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK
- PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT
- PALMAS_GPADC_AUTO_CONV0_MSB
- PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK
- PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT
- PALMAS_GPADC_AUTO_CONV1_LSB
- PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK
- PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT
- PALMAS_GPADC_AUTO_CONV1_MSB
- PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK
- PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT
- PALMAS_GPADC_AUTO_CTRL
- PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN
- PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT
- PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN
- PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT
- PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK
- PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT
- PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0
- PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT
- PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1
- PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT
- PALMAS_GPADC_AUTO_SELECT
- PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK
- PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT
- PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK
- PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT
- PALMAS_GPADC_BASE
- PALMAS_GPADC_CTRL1
- PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET
- PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT
- PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK
- PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT
- PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK
- PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT
- PALMAS_GPADC_CTRL1_GPADC_FORCE
- PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT
- PALMAS_GPADC_CTRL1_RESERVED_MASK
- PALMAS_GPADC_CTRL1_RESERVED_SHIFT
- PALMAS_GPADC_CTRL2
- PALMAS_GPADC_CTRL2_RESERVED_MASK
- PALMAS_GPADC_CTRL2_RESERVED_SHIFT
- PALMAS_GPADC_EOC_RT_IRQ
- PALMAS_GPADC_EOC_SW_IRQ
- PALMAS_GPADC_RT_CONV0_LSB
- PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK
- PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT
- PALMAS_GPADC_RT_CONV0_MSB
- PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK
- PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT
- PALMAS_GPADC_RT_CTRL
- PALMAS_GPADC_RT_CTRL_EXTEND_DELAY
- PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT
- PALMAS_GPADC_RT_CTRL_START_POLARITY
- PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT
- PALMAS_GPADC_RT_SELECT
- PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK
- PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT
- PALMAS_GPADC_RT_SELECT_RT_CONV_EN
- PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT
- PALMAS_GPADC_SMPS_ILMONITOR_EN
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK
- PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT
- PALMAS_GPADC_SMPS_VSEL_MONITORING
- PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE
- PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT
- PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK
- PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT
- PALMAS_GPADC_STATUS
- PALMAS_GPADC_STATUS_GPADC_AVAILABLE
- PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT
- PALMAS_GPADC_SW_CONV0_LSB
- PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK
- PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT
- PALMAS_GPADC_SW_CONV0_MSB
- PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK
- PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT
- PALMAS_GPADC_SW_SELECT
- PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK
- PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT
- PALMAS_GPADC_SW_SELECT_SW_CONV_EN
- PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT
- PALMAS_GPADC_SW_SELECT_SW_START_CONV0
- PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT
- PALMAS_GPADC_THRES_CONV0_LSB
- PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK
- PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT
- PALMAS_GPADC_THRES_CONV0_MSB
- PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK
- PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT
- PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL
- PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT
- PALMAS_GPADC_THRES_CONV1_LSB
- PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK
- PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT
- PALMAS_GPADC_THRES_CONV1_MSB
- PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK
- PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT
- PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL
- PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT
- PALMAS_GPADC_TRIM1
- PALMAS_GPADC_TRIM10
- PALMAS_GPADC_TRIM11
- PALMAS_GPADC_TRIM12
- PALMAS_GPADC_TRIM13
- PALMAS_GPADC_TRIM14
- PALMAS_GPADC_TRIM15
- PALMAS_GPADC_TRIM16
- PALMAS_GPADC_TRIM2
- PALMAS_GPADC_TRIM3
- PALMAS_GPADC_TRIM4
- PALMAS_GPADC_TRIM5
- PALMAS_GPADC_TRIM6
- PALMAS_GPADC_TRIM7
- PALMAS_GPADC_TRIM8
- PALMAS_GPADC_TRIM9
- PALMAS_GPADC_TRIMINVALID
- PALMAS_GPIO_0_IRQ
- PALMAS_GPIO_0_MUXED
- PALMAS_GPIO_1_IRQ
- PALMAS_GPIO_1_MUXED
- PALMAS_GPIO_2_IRQ
- PALMAS_GPIO_2_MUXED
- PALMAS_GPIO_3_IRQ
- PALMAS_GPIO_3_MUXED
- PALMAS_GPIO_4_IRQ
- PALMAS_GPIO_4_MUXED
- PALMAS_GPIO_5_IRQ
- PALMAS_GPIO_5_MUXED
- PALMAS_GPIO_6_IRQ
- PALMAS_GPIO_6_MUXED
- PALMAS_GPIO_7_IRQ
- PALMAS_GPIO_7_MUXED
- PALMAS_GPIO_BASE
- PALMAS_GPIO_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT2
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT
- PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT
- PALMAS_GPIO_DATA_DIR
- PALMAS_GPIO_DATA_DIR2
- PALMAS_GPIO_DATA_DIR_GPIO_0_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_1_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_2_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_3_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_4_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_5_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_6_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT
- PALMAS_GPIO_DATA_DIR_GPIO_7_DIR
- PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT
- PALMAS_GPIO_DATA_IN
- PALMAS_GPIO_DATA_IN2
- PALMAS_GPIO_DATA_IN_GPIO_0_IN
- PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_1_IN
- PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_2_IN
- PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_3_IN
- PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_4_IN
- PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_5_IN
- PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_6_IN
- PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT
- PALMAS_GPIO_DATA_IN_GPIO_7_IN
- PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT
- PALMAS_GPIO_DATA_OUT
- PALMAS_GPIO_DATA_OUT2
- PALMAS_GPIO_DATA_OUT_GPIO_0_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_1_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_2_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_3_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_4_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_5_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_6_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT
- PALMAS_GPIO_DATA_OUT_GPIO_7_OUT
- PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN2
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN
- PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT
- PALMAS_GPIO_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT2
- PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT
- PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT
- PALMAS_HOTDIE_IRQ
- PALMAS_HOURS_REG
- PALMAS_HOURS_REG_HOUR0_MASK
- PALMAS_HOURS_REG_HOUR0_SHIFT
- PALMAS_HOURS_REG_HOUR1_MASK
- PALMAS_HOURS_REG_HOUR1_SHIFT
- PALMAS_HOURS_REG_PM_NAM
- PALMAS_HOURS_REG_PM_NAM_SHIFT
- PALMAS_I2C_SPI
- PALMAS_I2C_SPI_I2C2OTP_EN
- PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT
- PALMAS_I2C_SPI_I2C2OTP_PAGESEL
- PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT
- PALMAS_I2C_SPI_I2C_SPI
- PALMAS_I2C_SPI_I2C_SPI_SHIFT
- PALMAS_I2C_SPI_ID_I2C1_MASK
- PALMAS_I2C_SPI_ID_I2C1_SHIFT
- PALMAS_I2C_SPI_ID_I2C2
- PALMAS_I2C_SPI_ID_I2C2_SHIFT
- PALMAS_ID_IRQ
- PALMAS_ID_OTG_IRQ
- PALMAS_INT1_EDGE_DETECT1_RESERVED
- PALMAS_INT1_EDGE_DETECT2_RESERVED
- PALMAS_INT1_LINE_STATE
- PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV
- PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT
- PALMAS_INT1_LINE_STATE_HOTDIE
- PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT
- PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY
- PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT
- PALMAS_INT1_LINE_STATE_PWRDOWN
- PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT
- PALMAS_INT1_LINE_STATE_PWRON
- PALMAS_INT1_LINE_STATE_PWRON_SHIFT
- PALMAS_INT1_LINE_STATE_RPWRON
- PALMAS_INT1_LINE_STATE_RPWRON_SHIFT
- PALMAS_INT1_LINE_STATE_VBAT_MON
- PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT
- PALMAS_INT1_LINE_STATE_VSYS_MON
- PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT
- PALMAS_INT1_MASK
- PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV
- PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT
- PALMAS_INT1_MASK_HOTDIE
- PALMAS_INT1_MASK_HOTDIE_SHIFT
- PALMAS_INT1_MASK_LONG_PRESS_KEY
- PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT
- PALMAS_INT1_MASK_PWRDOWN
- PALMAS_INT1_MASK_PWRDOWN_SHIFT
- PALMAS_INT1_MASK_PWRON
- PALMAS_INT1_MASK_PWRON_SHIFT
- PALMAS_INT1_MASK_RPWRON
- PALMAS_INT1_MASK_RPWRON_SHIFT
- PALMAS_INT1_MASK_VBAT_MON
- PALMAS_INT1_MASK_VBAT_MON_SHIFT
- PALMAS_INT1_MASK_VSYS_MON
- PALMAS_INT1_MASK_VSYS_MON_SHIFT
- PALMAS_INT1_STATUS
- PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV
- PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT
- PALMAS_INT1_STATUS_HOTDIE
- PALMAS_INT1_STATUS_HOTDIE_SHIFT
- PALMAS_INT1_STATUS_LONG_PRESS_KEY
- PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT
- PALMAS_INT1_STATUS_PWRDOWN
- PALMAS_INT1_STATUS_PWRDOWN_SHIFT
- PALMAS_INT1_STATUS_PWRON
- PALMAS_INT1_STATUS_PWRON_SHIFT
- PALMAS_INT1_STATUS_RPWRON
- PALMAS_INT1_STATUS_RPWRON_SHIFT
- PALMAS_INT1_STATUS_VBAT_MON
- PALMAS_INT1_STATUS_VBAT_MON_SHIFT
- PALMAS_INT1_STATUS_VSYS_MON
- PALMAS_INT1_STATUS_VSYS_MON_SHIFT
- PALMAS_INT2_EDGE_DETECT1_RESERVED
- PALMAS_INT2_EDGE_DETECT2_RESERVED
- PALMAS_INT2_LINE_STATE
- PALMAS_INT2_LINE_STATE_BATREMOVAL
- PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT
- PALMAS_INT2_LINE_STATE_FBI_BB
- PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT
- PALMAS_INT2_LINE_STATE_RESET_IN
- PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT
- PALMAS_INT2_LINE_STATE_RTC_ALARM
- PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT
- PALMAS_INT2_LINE_STATE_RTC_TIMER
- PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT
- PALMAS_INT2_LINE_STATE_SHORT
- PALMAS_INT2_LINE_STATE_SHORT_SHIFT
- PALMAS_INT2_LINE_STATE_VAC_ACOK
- PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT
- PALMAS_INT2_LINE_STATE_WDT
- PALMAS_INT2_LINE_STATE_WDT_SHIFT
- PALMAS_INT2_MASK
- PALMAS_INT2_MASK_BATREMOVAL
- PALMAS_INT2_MASK_BATREMOVAL_SHIFT
- PALMAS_INT2_MASK_FBI_BB
- PALMAS_INT2_MASK_FBI_BB_SHIFT
- PALMAS_INT2_MASK_RESET_IN
- PALMAS_INT2_MASK_RESET_IN_SHIFT
- PALMAS_INT2_MASK_RTC_ALARM
- PALMAS_INT2_MASK_RTC_ALARM_SHIFT
- PALMAS_INT2_MASK_RTC_TIMER
- PALMAS_INT2_MASK_RTC_TIMER_SHIFT
- PALMAS_INT2_MASK_SHORT
- PALMAS_INT2_MASK_SHORT_SHIFT
- PALMAS_INT2_MASK_VAC_ACOK
- PALMAS_INT2_MASK_VAC_ACOK_SHIFT
- PALMAS_INT2_MASK_WDT
- PALMAS_INT2_MASK_WDT_SHIFT
- PALMAS_INT2_STATUS
- PALMAS_INT2_STATUS_BATREMOVAL
- PALMAS_INT2_STATUS_BATREMOVAL_SHIFT
- PALMAS_INT2_STATUS_FBI_BB
- PALMAS_INT2_STATUS_FBI_BB_SHIFT
- PALMAS_INT2_STATUS_RESET_IN
- PALMAS_INT2_STATUS_RESET_IN_SHIFT
- PALMAS_INT2_STATUS_RTC_ALARM
- PALMAS_INT2_STATUS_RTC_ALARM_SHIFT
- PALMAS_INT2_STATUS_RTC_TIMER
- PALMAS_INT2_STATUS_RTC_TIMER_SHIFT
- PALMAS_INT2_STATUS_SHORT
- PALMAS_INT2_STATUS_SHORT_SHIFT
- PALMAS_INT2_STATUS_VAC_ACOK
- PALMAS_INT2_STATUS_VAC_ACOK_SHIFT
- PALMAS_INT2_STATUS_WDT
- PALMAS_INT2_STATUS_WDT_SHIFT
- PALMAS_INT3_EDGE_DETECT1_RESERVED
- PALMAS_INT3_EDGE_DETECT2_RESERVED
- PALMAS_INT3_LINE_STATE
- PALMAS_INT3_LINE_STATE_GPADC_AUTO_0
- PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT
- PALMAS_INT3_LINE_STATE_GPADC_AUTO_1
- PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT
- PALMAS_INT3_LINE_STATE_GPADC_EOC_RT
- PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT
- PALMAS_INT3_LINE_STATE_GPADC_EOC_SW
- PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT
- PALMAS_INT3_LINE_STATE_ID
- PALMAS_INT3_LINE_STATE_ID_OTG
- PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT
- PALMAS_INT3_LINE_STATE_ID_SHIFT
- PALMAS_INT3_LINE_STATE_VBUS
- PALMAS_INT3_LINE_STATE_VBUS_OTG
- PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT
- PALMAS_INT3_LINE_STATE_VBUS_SHIFT
- PALMAS_INT3_MASK
- PALMAS_INT3_MASK_GPADC_AUTO_0
- PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT
- PALMAS_INT3_MASK_GPADC_AUTO_1
- PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT
- PALMAS_INT3_MASK_GPADC_EOC_RT
- PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT
- PALMAS_INT3_MASK_GPADC_EOC_SW
- PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT
- PALMAS_INT3_MASK_ID
- PALMAS_INT3_MASK_ID_OTG
- PALMAS_INT3_MASK_ID_OTG_SHIFT
- PALMAS_INT3_MASK_ID_SHIFT
- PALMAS_INT3_MASK_VBUS
- PALMAS_INT3_MASK_VBUS_OTG
- PALMAS_INT3_MASK_VBUS_OTG_SHIFT
- PALMAS_INT3_MASK_VBUS_SHIFT
- PALMAS_INT3_STATUS
- PALMAS_INT3_STATUS_GPADC_AUTO_0
- PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT
- PALMAS_INT3_STATUS_GPADC_AUTO_1
- PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT
- PALMAS_INT3_STATUS_GPADC_EOC_RT
- PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT
- PALMAS_INT3_STATUS_GPADC_EOC_SW
- PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT
- PALMAS_INT3_STATUS_ID
- PALMAS_INT3_STATUS_ID_OTG
- PALMAS_INT3_STATUS_ID_OTG_SHIFT
- PALMAS_INT3_STATUS_ID_SHIFT
- PALMAS_INT3_STATUS_VBUS
- PALMAS_INT3_STATUS_VBUS_OTG
- PALMAS_INT3_STATUS_VBUS_OTG_SHIFT
- PALMAS_INT3_STATUS_VBUS_SHIFT
- PALMAS_INT4_EDGE_DETECT1
- PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING
- PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING
- PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING
- PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING
- PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING
- PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING
- PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING
- PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING
- PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT2
- PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING
- PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING
- PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING
- PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING
- PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING
- PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING
- PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING
- PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT
- PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING
- PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT
- PALMAS_INT4_LINE_STATE
- PALMAS_INT4_LINE_STATE_GPIO_0
- PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_1
- PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_2
- PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_3
- PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_4
- PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_5
- PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_6
- PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT
- PALMAS_INT4_LINE_STATE_GPIO_7
- PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT
- PALMAS_INT4_MASK
- PALMAS_INT4_MASK_GPIO_0
- PALMAS_INT4_MASK_GPIO_0_SHIFT
- PALMAS_INT4_MASK_GPIO_1
- PALMAS_INT4_MASK_GPIO_1_SHIFT
- PALMAS_INT4_MASK_GPIO_2
- PALMAS_INT4_MASK_GPIO_2_SHIFT
- PALMAS_INT4_MASK_GPIO_3
- PALMAS_INT4_MASK_GPIO_3_SHIFT
- PALMAS_INT4_MASK_GPIO_4
- PALMAS_INT4_MASK_GPIO_4_SHIFT
- PALMAS_INT4_MASK_GPIO_5
- PALMAS_INT4_MASK_GPIO_5_SHIFT
- PALMAS_INT4_MASK_GPIO_6
- PALMAS_INT4_MASK_GPIO_6_SHIFT
- PALMAS_INT4_MASK_GPIO_7
- PALMAS_INT4_MASK_GPIO_7_SHIFT
- PALMAS_INT4_STATUS
- PALMAS_INT4_STATUS_GPIO_0
- PALMAS_INT4_STATUS_GPIO_0_SHIFT
- PALMAS_INT4_STATUS_GPIO_1
- PALMAS_INT4_STATUS_GPIO_1_SHIFT
- PALMAS_INT4_STATUS_GPIO_2
- PALMAS_INT4_STATUS_GPIO_2_SHIFT
- PALMAS_INT4_STATUS_GPIO_3
- PALMAS_INT4_STATUS_GPIO_3_SHIFT
- PALMAS_INT4_STATUS_GPIO_4
- PALMAS_INT4_STATUS_GPIO_4_SHIFT
- PALMAS_INT4_STATUS_GPIO_5
- PALMAS_INT4_STATUS_GPIO_5_SHIFT
- PALMAS_INT4_STATUS_GPIO_6
- PALMAS_INT4_STATUS_GPIO_6_SHIFT
- PALMAS_INT4_STATUS_GPIO_7
- PALMAS_INT4_STATUS_GPIO_7_SHIFT
- PALMAS_INTERRUPT_BASE
- PALMAS_INT_CTRL
- PALMAS_INT_CTRL_INT_CLEAR
- PALMAS_INT_CTRL_INT_CLEAR_SHIFT
- PALMAS_INT_CTRL_INT_PENDING
- PALMAS_INT_CTRL_INT_PENDING_SHIFT
- PALMAS_LDO1_CTRL
- PALMAS_LDO1_CTRL_MODE_ACTIVE
- PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO1_CTRL_MODE_SLEEP
- PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO1_CTRL_STATUS
- PALMAS_LDO1_CTRL_STATUS_SHIFT
- PALMAS_LDO1_CTRL_WR_S
- PALMAS_LDO1_CTRL_WR_S_SHIFT
- PALMAS_LDO1_VOLTAGE
- PALMAS_LDO1_VOLTAGE_VSEL_MASK
- PALMAS_LDO1_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO2_CTRL
- PALMAS_LDO2_CTRL_MODE_ACTIVE
- PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO2_CTRL_MODE_SLEEP
- PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO2_CTRL_STATUS
- PALMAS_LDO2_CTRL_STATUS_SHIFT
- PALMAS_LDO2_CTRL_WR_S
- PALMAS_LDO2_CTRL_WR_S_SHIFT
- PALMAS_LDO2_VOLTAGE
- PALMAS_LDO2_VOLTAGE_VSEL_MASK
- PALMAS_LDO2_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO3_CTRL
- PALMAS_LDO3_CTRL_MODE_ACTIVE
- PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO3_CTRL_MODE_SLEEP
- PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO3_CTRL_STATUS
- PALMAS_LDO3_CTRL_STATUS_SHIFT
- PALMAS_LDO3_CTRL_WR_S
- PALMAS_LDO3_CTRL_WR_S_SHIFT
- PALMAS_LDO3_VOLTAGE
- PALMAS_LDO3_VOLTAGE_VSEL_MASK
- PALMAS_LDO3_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO4_CTRL
- PALMAS_LDO4_CTRL_MODE_ACTIVE
- PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO4_CTRL_MODE_SLEEP
- PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO4_CTRL_STATUS
- PALMAS_LDO4_CTRL_STATUS_SHIFT
- PALMAS_LDO4_CTRL_WR_S
- PALMAS_LDO4_CTRL_WR_S_SHIFT
- PALMAS_LDO4_VOLTAGE
- PALMAS_LDO4_VOLTAGE_VSEL_MASK
- PALMAS_LDO4_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO5_CTRL
- PALMAS_LDO5_CTRL_MODE_ACTIVE
- PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO5_CTRL_MODE_SLEEP
- PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO5_CTRL_STATUS
- PALMAS_LDO5_CTRL_STATUS_SHIFT
- PALMAS_LDO5_CTRL_WR_S
- PALMAS_LDO5_CTRL_WR_S_SHIFT
- PALMAS_LDO5_VOLTAGE
- PALMAS_LDO5_VOLTAGE_VSEL_MASK
- PALMAS_LDO5_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO6_CTRL
- PALMAS_LDO6_CTRL_LDO_VIB_EN
- PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT
- PALMAS_LDO6_CTRL_MODE_ACTIVE
- PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO6_CTRL_MODE_SLEEP
- PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO6_CTRL_STATUS
- PALMAS_LDO6_CTRL_STATUS_SHIFT
- PALMAS_LDO6_CTRL_WR_S
- PALMAS_LDO6_CTRL_WR_S_SHIFT
- PALMAS_LDO6_VOLTAGE
- PALMAS_LDO6_VOLTAGE_VSEL_MASK
- PALMAS_LDO6_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO7_CTRL
- PALMAS_LDO7_CTRL_MODE_ACTIVE
- PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO7_CTRL_MODE_SLEEP
- PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO7_CTRL_STATUS
- PALMAS_LDO7_CTRL_STATUS_SHIFT
- PALMAS_LDO7_CTRL_WR_S
- PALMAS_LDO7_CTRL_WR_S_SHIFT
- PALMAS_LDO7_VOLTAGE
- PALMAS_LDO7_VOLTAGE_VSEL_MASK
- PALMAS_LDO7_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO8_CTRL
- PALMAS_LDO8_CTRL_LDO_TRACKING_EN
- PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT
- PALMAS_LDO8_CTRL_MODE_ACTIVE
- PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO8_CTRL_MODE_SLEEP
- PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO8_CTRL_STATUS
- PALMAS_LDO8_CTRL_STATUS_SHIFT
- PALMAS_LDO8_CTRL_WR_S
- PALMAS_LDO8_CTRL_WR_S_SHIFT
- PALMAS_LDO8_VOLTAGE
- PALMAS_LDO8_VOLTAGE_VSEL_MASK
- PALMAS_LDO8_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO9_CTRL
- PALMAS_LDO9_CTRL_LDO_BYPASS_EN
- PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT
- PALMAS_LDO9_CTRL_MODE_ACTIVE
- PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDO9_CTRL_MODE_SLEEP
- PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDO9_CTRL_STATUS
- PALMAS_LDO9_CTRL_STATUS_SHIFT
- PALMAS_LDO9_CTRL_WR_S
- PALMAS_LDO9_CTRL_WR_S_SHIFT
- PALMAS_LDO9_VOLTAGE
- PALMAS_LDO9_VOLTAGE_VSEL_MASK
- PALMAS_LDO9_VOLTAGE_VSEL_SHIFT
- PALMAS_LDOLN_CTRL
- PALMAS_LDOLN_CTRL_MODE_ACTIVE
- PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDOLN_CTRL_MODE_SLEEP
- PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDOLN_CTRL_STATUS
- PALMAS_LDOLN_CTRL_STATUS_SHIFT
- PALMAS_LDOLN_CTRL_WR_S
- PALMAS_LDOLN_CTRL_WR_S_SHIFT
- PALMAS_LDOLN_VOLTAGE
- PALMAS_LDOLN_VOLTAGE_VSEL_MASK
- PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT
- PALMAS_LDOUSB_CTRL
- PALMAS_LDOUSB_CTRL_MODE_ACTIVE
- PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_LDOUSB_CTRL_MODE_SLEEP
- PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT
- PALMAS_LDOUSB_CTRL_STATUS
- PALMAS_LDOUSB_CTRL_STATUS_SHIFT
- PALMAS_LDOUSB_CTRL_WR_S
- PALMAS_LDOUSB_CTRL_WR_S_SHIFT
- PALMAS_LDOUSB_VOLTAGE
- PALMAS_LDOUSB_VOLTAGE_VSEL_MASK
- PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT
- PALMAS_LDO_BASE
- PALMAS_LDO_CTRL
- PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS
- PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT
- PALMAS_LDO_NUM_VOLTAGES
- PALMAS_LDO_PD_CTRL1
- PALMAS_LDO_PD_CTRL1_LDO1
- PALMAS_LDO_PD_CTRL1_LDO1_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO2
- PALMAS_LDO_PD_CTRL1_LDO2_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO3
- PALMAS_LDO_PD_CTRL1_LDO3_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO4
- PALMAS_LDO_PD_CTRL1_LDO4_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO5
- PALMAS_LDO_PD_CTRL1_LDO5_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO6
- PALMAS_LDO_PD_CTRL1_LDO6_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO7
- PALMAS_LDO_PD_CTRL1_LDO7_SHIFT
- PALMAS_LDO_PD_CTRL1_LDO8
- PALMAS_LDO_PD_CTRL1_LDO8_SHIFT
- PALMAS_LDO_PD_CTRL2
- PALMAS_LDO_PD_CTRL2_LDO9
- PALMAS_LDO_PD_CTRL2_LDO9_SHIFT
- PALMAS_LDO_PD_CTRL2_LDOLN
- PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT
- PALMAS_LDO_PD_CTRL2_LDOUSB
- PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT
- PALMAS_LDO_SHORT_STATUS1
- PALMAS_LDO_SHORT_STATUS1_LDO1
- PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO2
- PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO3
- PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO4
- PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO5
- PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO6
- PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO7
- PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT
- PALMAS_LDO_SHORT_STATUS1_LDO8
- PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT
- PALMAS_LDO_SHORT_STATUS2
- PALMAS_LDO_SHORT_STATUS2_LDO9
- PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT
- PALMAS_LDO_SHORT_STATUS2_LDOLN
- PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT
- PALMAS_LDO_SHORT_STATUS2_LDOUSB
- PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT
- PALMAS_LDO_SHORT_STATUS2_LDOVANA
- PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT
- PALMAS_LED1_MUXED
- PALMAS_LED2_MUXED
- PALMAS_LED_BASE
- PALMAS_LED_CTRL
- PALMAS_LED_CTRL_LED_1_ON_TIME_MASK
- PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT
- PALMAS_LED_CTRL_LED_1_SEQ
- PALMAS_LED_CTRL_LED_1_SEQ_SHIFT
- PALMAS_LED_CTRL_LED_2_ON_TIME_MASK
- PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT
- PALMAS_LED_CTRL_LED_2_SEQ
- PALMAS_LED_CTRL_LED_2_SEQ_SHIFT
- PALMAS_LED_PERIOD_CTRL
- PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK
- PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT
- PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK
- PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT
- PALMAS_LONG_PRESS_KEY
- PALMAS_LONG_PRESS_KEY_IRQ
- PALMAS_LONG_PRESS_KEY_LPK_INT_CLR
- PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT
- PALMAS_LONG_PRESS_KEY_LPK_LOCK
- PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT
- PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK
- PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT
- PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK
- PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT
- PALMAS_LPK_TIME_MASK
- PALMAS_MAX_CHANNELS
- PALMAS_MINUTES_REG
- PALMAS_MINUTES_REG_MIN0_MASK
- PALMAS_MINUTES_REG_MIN0_SHIFT
- PALMAS_MINUTES_REG_MIN1_MASK
- PALMAS_MINUTES_REG_MIN1_SHIFT
- PALMAS_MONTHS_REG
- PALMAS_MONTHS_REG_MONTH0_MASK
- PALMAS_MONTHS_REG_MONTH0_SHIFT
- PALMAS_MONTHS_REG_MONTH1
- PALMAS_MONTHS_REG_MONTH1_SHIFT
- PALMAS_NONE_BASE
- PALMAS_NSLEEP_LDO_ASSIGN1
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO1
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO2
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO3
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO4
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO5
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO6
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO7
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO8
- PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN2
- PALMAS_NSLEEP_LDO_ASSIGN2_LDO9
- PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN
- PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT
- PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB
- PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN
- PALMAS_NSLEEP_RES_ASSIGN_CLK32KG
- PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO
- PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_REGEN1
- PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_REGEN2
- PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_REGEN3
- PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_SYSEN1
- PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT
- PALMAS_NSLEEP_RES_ASSIGN_SYSEN2
- PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9
- PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT
- PALMAS_NUM_CLIENTS
- PALMAS_NUM_IRQ
- PALMAS_NUM_REGS
- PALMAS_NUM_TIME_REGS
- PALMAS_OD_OUTPUT_CTRL
- PALMAS_OD_OUTPUT_CTRL2
- PALMAS_OD_OUTPUT_CTRL_INT_OD
- PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT
- PALMAS_OD_OUTPUT_CTRL_PWM_1_OD
- PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT
- PALMAS_OD_OUTPUT_CTRL_PWM_2_OD
- PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT
- PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD
- PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT
- PALMAS_OD_OUTPUT_GPIO_CTRL
- PALMAS_OD_OUTPUT_GPIO_CTRL2
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD
- PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT
- PALMAS_OSC_THERM_CTRL
- PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP
- PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT
- PALMAS_OSC_THERM_CTRL_OSC_BYPASS
- PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT
- PALMAS_OSC_THERM_CTRL_OSC_HPMODE
- PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT
- PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP
- PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT
- PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK
- PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT
- PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP
- PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT
- PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP
- PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT
- PALMAS_PINGROUP
- PALMAS_PINMUX_
- PALMAS_PINMUX_NA
- PALMAS_PIN_ENABLE1
- PALMAS_PIN_ENABLE2
- PALMAS_PIN_GPADC_START
- PALMAS_PIN_GPIO0_ID
- PALMAS_PIN_GPIO10_WIRELESS_CHRG1
- PALMAS_PIN_GPIO11_RCM
- PALMAS_PIN_GPIO12_SIM2RSTO
- PALMAS_PIN_GPIO13
- PALMAS_PIN_GPIO14
- PALMAS_PIN_GPIO15_SIM2RSTI
- PALMAS_PIN_GPIO1_VBUS_LED1_PWM1
- PALMAS_PIN_GPIO2_REGEN_LED2_PWM2
- PALMAS_PIN_GPIO3_CHRG_DET
- PALMAS_PIN_GPIO4_SYSEN1
- PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL
- PALMAS_PIN_GPIO6_SYSEN2
- PALMAS_PIN_GPIO7_MSECURE_PWRHOLD
- PALMAS_PIN_GPIO8_SIM1RSTI
- PALMAS_PIN_GPIO9_LOW_VBAT
- PALMAS_PIN_INT
- PALMAS_PIN_NRESWARM
- PALMAS_PIN_NSLEEP
- PALMAS_PIN_NUM
- PALMAS_PIN_POWERGOOD_USB_PSEL
- PALMAS_PIN_PWRDOWN
- PALMAS_PIN_RESET_IN
- PALMAS_PIN_VAC
- PALMAS_PMIC_FEATURE_SMPS10_BOOST
- PALMAS_PMIC_HAS
- PALMAS_PMU_CONFIG
- PALMAS_PMU_CONFIG_AUTODEVON
- PALMAS_PMU_CONFIG_AUTODEVON_SHIFT
- PALMAS_PMU_CONFIG_GATE_RESET_OUT
- PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT
- PALMAS_PMU_CONFIG_MULTI_CELL_EN
- PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT
- PALMAS_PMU_CONFIG_SPARE_MASK
- PALMAS_PMU_CONFIG_SPARE_SHIFT
- PALMAS_PMU_CONFIG_SWOFF_DLY_MASK
- PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT
- PALMAS_PMU_CONTROL_BASE
- PALMAS_PMU_SECONDARY_INT
- PALMAS_PMU_SECONDARY_INT2
- PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC
- PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK
- PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT
- PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC
- PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK
- PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT
- PALMAS_PMU_SECONDARY_INT_BB_INT_SRC
- PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT_BB_MASK
- PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT
- PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC
- PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK
- PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT
- PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC
- PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT_FBI_MASK
- PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT
- PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC
- PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT
- PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK
- PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT
- PALMAS_POLARITY_CTRL
- PALMAS_POLARITY_CTRL2
- PALMAS_POLARITY_CTRL_ENABLE1_POLARITY
- PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_ENABLE2_POLARITY
- PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY
- PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_INT_POLARITY
- PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_NSLEEP_POLARITY
- PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY
- PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY
- PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT
- PALMAS_POLARITY_CTRL_RESET_IN_POLARITY
- PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT
- PALMAS_POWER_CTRL
- PALMAS_POWER_CTRL_ENABLE1_MASK
- PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT
- PALMAS_POWER_CTRL_ENABLE2_MASK
- PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT
- PALMAS_POWER_CTRL_NSLEEP_MASK
- PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT
- PALMAS_PRIMARY_SECONDARY_INPUT3
- PALMAS_PRIMARY_SECONDARY_NONE
- PALMAS_PRIMARY_SECONDARY_PAD1
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3
- PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD
- PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD1_VAC
- PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD2
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK
- PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD3
- PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1
- PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2
- PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT
- PALMAS_PRIMARY_SECONDARY_PAD4
- PALMAS_PU_PD_GPIO_CTRL1
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD
- PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD
- PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT
- PALMAS_PU_PD_GPIO_CTRL3
- PALMAS_PU_PD_GPIO_CTRL4
- PALMAS_PU_PD_INPUT_CTRL1
- PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD
- PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU
- PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT
- PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU
- PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT
- PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD
- PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD
- PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU
- PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD
- PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU
- PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT
- PALMAS_PU_PD_INPUT_CTRL3
- PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD
- PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD
- PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD
- PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD
- PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL4
- PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD
- PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD
- PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD
- PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD
- PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT
- PALMAS_PU_PD_INPUT_CTRL5
- PALMAS_PU_PD_OD_BASE
- PALMAS_PWM1_MUXED
- PALMAS_PWM2_MUXED
- PALMAS_PWM_CTRL1
- PALMAS_PWM_CTRL1_PWM_FREQ_EN
- PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT
- PALMAS_PWM_CTRL1_PWM_FREQ_SEL
- PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT
- PALMAS_PWM_CTRL2
- PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK
- PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT
- PALMAS_PWRDOWN_IRQ
- PALMAS_PWRON_DEBOUNCE_MASK
- PALMAS_PWRON_IRQ
- PALMAS_PWR_KEY_Q_TIME_MS
- PALMAS_REGEN1_CTRL
- PALMAS_REGEN1_CTRL_MODE_ACTIVE
- PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_REGEN1_CTRL_MODE_SLEEP
- PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT
- PALMAS_REGEN1_CTRL_STATUS
- PALMAS_REGEN1_CTRL_STATUS_SHIFT
- PALMAS_REGEN2_CTRL
- PALMAS_REGEN2_CTRL_MODE_ACTIVE
- PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_REGEN2_CTRL_MODE_SLEEP
- PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT
- PALMAS_REGEN2_CTRL_STATUS
- PALMAS_REGEN2_CTRL_STATUS_SHIFT
- PALMAS_REGEN3_CTRL
- PALMAS_REGEN3_CTRL_MODE_ACTIVE
- PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_REGEN3_CTRL_MODE_SLEEP
- PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT
- PALMAS_REGEN3_CTRL_STATUS
- PALMAS_REGEN3_CTRL_STATUS_SHIFT
- PALMAS_REG_LDO1
- PALMAS_REG_LDO2
- PALMAS_REG_LDO3
- PALMAS_REG_LDO4
- PALMAS_REG_LDO5
- PALMAS_REG_LDO6
- PALMAS_REG_LDO7
- PALMAS_REG_LDO8
- PALMAS_REG_LDO9
- PALMAS_REG_LDOLN
- PALMAS_REG_LDOUSB
- PALMAS_REG_REGEN1
- PALMAS_REG_REGEN2
- PALMAS_REG_REGEN3
- PALMAS_REG_SMPS10_OUT1
- PALMAS_REG_SMPS10_OUT2
- PALMAS_REG_SMPS12
- PALMAS_REG_SMPS123
- PALMAS_REG_SMPS3
- PALMAS_REG_SMPS45
- PALMAS_REG_SMPS457
- PALMAS_REG_SMPS6
- PALMAS_REG_SMPS7
- PALMAS_REG_SMPS8
- PALMAS_REG_SMPS9
- PALMAS_REG_SYSEN1
- PALMAS_REG_SYSEN2
- PALMAS_RESET_IN_IRQ
- PALMAS_RESOURCE_BASE
- PALMAS_RPWRON_IRQ
- PALMAS_RTC_ALARM_IRQ
- PALMAS_RTC_BASE
- PALMAS_RTC_COMP_LSB_REG
- PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK
- PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT
- PALMAS_RTC_COMP_MSB_REG
- PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK
- PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT
- PALMAS_RTC_CTRL_REG
- PALMAS_RTC_CTRL_REG_AUTO_COMP
- PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT
- PALMAS_RTC_CTRL_REG_GET_TIME
- PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT
- PALMAS_RTC_CTRL_REG_MODE_12_24
- PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT
- PALMAS_RTC_CTRL_REG_ROUND_30S
- PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT
- PALMAS_RTC_CTRL_REG_RTC_V_OPT
- PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT
- PALMAS_RTC_CTRL_REG_SET_32_COUNTER
- PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT
- PALMAS_RTC_CTRL_REG_STOP_RTC
- PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT
- PALMAS_RTC_CTRL_REG_TEST_MODE
- PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT
- PALMAS_RTC_INTERRUPTS_REG
- PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK
- PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT
- PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN
- PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT
- PALMAS_RTC_INTERRUPTS_REG_IT_TIMER
- PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT
- PALMAS_RTC_RESET_STATUS_REG
- PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS
- PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT
- PALMAS_RTC_RES_PROG_REG
- PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK
- PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT
- PALMAS_RTC_STATUS_REG
- PALMAS_RTC_STATUS_REG_ALARM
- PALMAS_RTC_STATUS_REG_ALARM_SHIFT
- PALMAS_RTC_STATUS_REG_EVENT_1D
- PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT
- PALMAS_RTC_STATUS_REG_EVENT_1H
- PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT
- PALMAS_RTC_STATUS_REG_EVENT_1M
- PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT
- PALMAS_RTC_STATUS_REG_EVENT_1S
- PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT
- PALMAS_RTC_STATUS_REG_POWER_UP
- PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT
- PALMAS_RTC_STATUS_REG_RUN
- PALMAS_RTC_STATUS_REG_RUN_SHIFT
- PALMAS_RTC_TIMER_IRQ
- PALMAS_SECONDS_REG
- PALMAS_SECONDS_REG_SEC0_MASK
- PALMAS_SECONDS_REG_SEC0_SHIFT
- PALMAS_SECONDS_REG_SEC1_MASK
- PALMAS_SECONDS_REG_SEC1_SHIFT
- PALMAS_SHORT_IRQ
- PALMAS_SMPS10_CTRL
- PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS10_NUM_VOLTAGES
- PALMAS_SMPS10_STATUS
- PALMAS_SMPS10_STATUS_STATUS_MASK
- PALMAS_SMPS10_STATUS_STATUS_SHIFT
- PALMAS_SMPS12_CTRL
- PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN
- PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT
- PALMAS_SMPS12_CTRL_STATUS_MASK
- PALMAS_SMPS12_CTRL_STATUS_SHIFT
- PALMAS_SMPS12_CTRL_WR_S
- PALMAS_SMPS12_CTRL_WR_S_SHIFT
- PALMAS_SMPS12_FORCE
- PALMAS_SMPS12_FORCE_CMD
- PALMAS_SMPS12_FORCE_CMD_SHIFT
- PALMAS_SMPS12_FORCE_VSEL_MASK
- PALMAS_SMPS12_FORCE_VSEL_SHIFT
- PALMAS_SMPS12_TSTEP
- PALMAS_SMPS12_TSTEP_TSTEP_MASK
- PALMAS_SMPS12_TSTEP_TSTEP_SHIFT
- PALMAS_SMPS12_VOLTAGE
- PALMAS_SMPS12_VOLTAGE_RANGE
- PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS12_VOLTAGE_VSEL_MASK
- PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS3_CTRL
- PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS3_CTRL_STATUS_MASK
- PALMAS_SMPS3_CTRL_STATUS_SHIFT
- PALMAS_SMPS3_CTRL_WR_S
- PALMAS_SMPS3_CTRL_WR_S_SHIFT
- PALMAS_SMPS3_VOLTAGE
- PALMAS_SMPS3_VOLTAGE_RANGE
- PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS3_VOLTAGE_VSEL_MASK
- PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS45_CTRL
- PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN
- PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT
- PALMAS_SMPS45_CTRL_STATUS_MASK
- PALMAS_SMPS45_CTRL_STATUS_SHIFT
- PALMAS_SMPS45_CTRL_WR_S
- PALMAS_SMPS45_CTRL_WR_S_SHIFT
- PALMAS_SMPS45_FORCE
- PALMAS_SMPS45_FORCE_CMD
- PALMAS_SMPS45_FORCE_CMD_SHIFT
- PALMAS_SMPS45_FORCE_VSEL_MASK
- PALMAS_SMPS45_FORCE_VSEL_SHIFT
- PALMAS_SMPS45_TSTEP
- PALMAS_SMPS45_TSTEP_TSTEP_MASK
- PALMAS_SMPS45_TSTEP_TSTEP_SHIFT
- PALMAS_SMPS45_VOLTAGE
- PALMAS_SMPS45_VOLTAGE_RANGE
- PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS45_VOLTAGE_VSEL_MASK
- PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS6_CTRL
- PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN
- PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT
- PALMAS_SMPS6_CTRL_STATUS_MASK
- PALMAS_SMPS6_CTRL_STATUS_SHIFT
- PALMAS_SMPS6_CTRL_WR_S
- PALMAS_SMPS6_CTRL_WR_S_SHIFT
- PALMAS_SMPS6_FORCE
- PALMAS_SMPS6_FORCE_CMD
- PALMAS_SMPS6_FORCE_CMD_SHIFT
- PALMAS_SMPS6_FORCE_VSEL_MASK
- PALMAS_SMPS6_FORCE_VSEL_SHIFT
- PALMAS_SMPS6_TSTEP
- PALMAS_SMPS6_TSTEP_TSTEP_MASK
- PALMAS_SMPS6_TSTEP_TSTEP_SHIFT
- PALMAS_SMPS6_VOLTAGE
- PALMAS_SMPS6_VOLTAGE_RANGE
- PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS6_VOLTAGE_VSEL_MASK
- PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS7_CTRL
- PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS7_CTRL_STATUS_MASK
- PALMAS_SMPS7_CTRL_STATUS_SHIFT
- PALMAS_SMPS7_CTRL_WR_S
- PALMAS_SMPS7_CTRL_WR_S_SHIFT
- PALMAS_SMPS7_VOLTAGE
- PALMAS_SMPS7_VOLTAGE_RANGE
- PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS7_VOLTAGE_VSEL_MASK
- PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS8_CTRL
- PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN
- PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT
- PALMAS_SMPS8_CTRL_STATUS_MASK
- PALMAS_SMPS8_CTRL_STATUS_SHIFT
- PALMAS_SMPS8_CTRL_WR_S
- PALMAS_SMPS8_CTRL_WR_S_SHIFT
- PALMAS_SMPS8_FORCE
- PALMAS_SMPS8_FORCE_CMD
- PALMAS_SMPS8_FORCE_CMD_SHIFT
- PALMAS_SMPS8_FORCE_VSEL_MASK
- PALMAS_SMPS8_FORCE_VSEL_SHIFT
- PALMAS_SMPS8_TSTEP
- PALMAS_SMPS8_TSTEP_TSTEP_MASK
- PALMAS_SMPS8_TSTEP_TSTEP_SHIFT
- PALMAS_SMPS8_VOLTAGE
- PALMAS_SMPS8_VOLTAGE_RANGE
- PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS8_VOLTAGE_VSEL_MASK
- PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS9_CTRL
- PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK
- PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK
- PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SMPS9_CTRL_STATUS_MASK
- PALMAS_SMPS9_CTRL_STATUS_SHIFT
- PALMAS_SMPS9_CTRL_WR_S
- PALMAS_SMPS9_CTRL_WR_S_SHIFT
- PALMAS_SMPS9_VOLTAGE
- PALMAS_SMPS9_VOLTAGE_RANGE
- PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT
- PALMAS_SMPS9_VOLTAGE_VSEL_MASK
- PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT
- PALMAS_SMPS_BASE
- PALMAS_SMPS_CTRL
- PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK
- PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT
- PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN
- PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT
- PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK
- PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT
- PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN
- PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT
- PALMAS_SMPS_DITHER_EN
- PALMAS_SMPS_DVS_BASE
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9
- PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT
- PALMAS_SMPS_NUM_VOLTAGES
- PALMAS_SMPS_PD_CTRL
- PALMAS_SMPS_PD_CTRL_SMPS12
- PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS3
- PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS45
- PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS6
- PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS7
- PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS8
- PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT
- PALMAS_SMPS_PD_CTRL_SMPS9
- PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS10
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS12
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS3
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS45
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS6
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS7
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS8
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS9
- PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK2
- PALMAS_SMPS_POWERGOOD_MASK2_ACOK
- PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7
- PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT
- PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT
- PALMAS_SMPS_POWERGOOD_MASK2_VBUS
- PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT
- PALMAS_SMPS_SHORT_STATUS
- PALMAS_SMPS_SHORT_STATUS_SMPS10
- PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS12
- PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS3
- PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS45
- PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS6
- PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS7
- PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS8
- PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT
- PALMAS_SMPS_SHORT_STATUS_SMPS9
- PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT
- PALMAS_SMPS_THERMAL_EN
- PALMAS_SMPS_THERMAL_EN_SMPS123
- PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT
- PALMAS_SMPS_THERMAL_EN_SMPS457
- PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT
- PALMAS_SMPS_THERMAL_EN_SMPS6
- PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT
- PALMAS_SMPS_THERMAL_EN_SMPS8
- PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT
- PALMAS_SMPS_THERMAL_EN_SMPS9
- PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT
- PALMAS_SMPS_THERMAL_STATUS
- PALMAS_SMPS_THERMAL_STATUS_SMPS123
- PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT
- PALMAS_SMPS_THERMAL_STATUS_SMPS457
- PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT
- PALMAS_SMPS_THERMAL_STATUS_SMPS6
- PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT
- PALMAS_SMPS_THERMAL_STATUS_SMPS8
- PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT
- PALMAS_SMPS_THERMAL_STATUS_SMPS9
- PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT
- PALMAS_SPARE
- PALMAS_SPARE_REGEN1_OD
- PALMAS_SPARE_REGEN1_OD_SHIFT
- PALMAS_SPARE_REGEN2_OD
- PALMAS_SPARE_REGEN2_OD_SHIFT
- PALMAS_SPARE_REGEN3_OD
- PALMAS_SPARE_REGEN3_OD_SHIFT
- PALMAS_SPARE_SPARE_MASK
- PALMAS_SPARE_SPARE_SHIFT
- PALMAS_SWOFF_COLDRST
- PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN
- PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT
- PALMAS_SWOFF_COLDRST_PWRDOWN
- PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT
- PALMAS_SWOFF_COLDRST_PWRON_LPK
- PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT
- PALMAS_SWOFF_COLDRST_RESET_IN
- PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT
- PALMAS_SWOFF_COLDRST_SW_RST
- PALMAS_SWOFF_COLDRST_SW_RST_SHIFT
- PALMAS_SWOFF_COLDRST_TSHUT
- PALMAS_SWOFF_COLDRST_TSHUT_SHIFT
- PALMAS_SWOFF_COLDRST_VSYS_LO
- PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT
- PALMAS_SWOFF_COLDRST_WTD
- PALMAS_SWOFF_COLDRST_WTD_SHIFT
- PALMAS_SWOFF_HWRST
- PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN
- PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT
- PALMAS_SWOFF_HWRST_PWRDOWN
- PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT
- PALMAS_SWOFF_HWRST_PWRON_LPK
- PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT
- PALMAS_SWOFF_HWRST_RESET_IN
- PALMAS_SWOFF_HWRST_RESET_IN_SHIFT
- PALMAS_SWOFF_HWRST_SW_RST
- PALMAS_SWOFF_HWRST_SW_RST_SHIFT
- PALMAS_SWOFF_HWRST_TSHUT
- PALMAS_SWOFF_HWRST_TSHUT_SHIFT
- PALMAS_SWOFF_HWRST_VSYS_LO
- PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT
- PALMAS_SWOFF_HWRST_WTD
- PALMAS_SWOFF_HWRST_WTD_SHIFT
- PALMAS_SWOFF_STATUS
- PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN
- PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT
- PALMAS_SWOFF_STATUS_PWRDOWN
- PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT
- PALMAS_SWOFF_STATUS_PWRON_LPK
- PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT
- PALMAS_SWOFF_STATUS_RESET_IN
- PALMAS_SWOFF_STATUS_RESET_IN_SHIFT
- PALMAS_SWOFF_STATUS_SW_RST
- PALMAS_SWOFF_STATUS_SW_RST_SHIFT
- PALMAS_SWOFF_STATUS_TSHUT
- PALMAS_SWOFF_STATUS_TSHUT_SHIFT
- PALMAS_SWOFF_STATUS_VSYS_LO
- PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT
- PALMAS_SWOFF_STATUS_WTD
- PALMAS_SWOFF_STATUS_WTD_SHIFT
- PALMAS_SW_REVISION
- PALMAS_SW_REVISION_SW_REVISION_MASK
- PALMAS_SW_REVISION_SW_REVISION_SHIFT
- PALMAS_SYSEN1_CTRL
- PALMAS_SYSEN1_CTRL_MODE_ACTIVE
- PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SYSEN1_CTRL_MODE_SLEEP
- PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SYSEN1_CTRL_STATUS
- PALMAS_SYSEN1_CTRL_STATUS_SHIFT
- PALMAS_SYSEN2_CTRL
- PALMAS_SYSEN2_CTRL_MODE_ACTIVE
- PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT
- PALMAS_SYSEN2_CTRL_MODE_SLEEP
- PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT
- PALMAS_SYSEN2_CTRL_STATUS
- PALMAS_SYSEN2_CTRL_STATUS_SHIFT
- PALMAS_TO_BE_CALCULATED
- PALMAS_TRIM_GPADC_BASE
- PALMAS_USB_BASE
- PALMAS_USB_ID_A
- PALMAS_USB_ID_B
- PALMAS_USB_ID_C
- PALMAS_USB_ID_CTRL_CLEAR
- PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP
- PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT
- PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV
- PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT
- PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K
- PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT
- PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K
- PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT
- PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U
- PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT
- PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U
- PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT
- PALMAS_USB_ID_CTRL_SET
- PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP
- PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT
- PALMAS_USB_ID_CTRL_SET_ID_GND_DRV
- PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT
- PALMAS_USB_ID_CTRL_SET_ID_PU_100K
- PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT
- PALMAS_USB_ID_CTRL_SET_ID_PU_220K
- PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT
- PALMAS_USB_ID_CTRL_SET_ID_SRC_16U
- PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT
- PALMAS_USB_ID_CTRL_SET_ID_SRC_5U
- PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT
- PALMAS_USB_ID_FLOAT
- PALMAS_USB_ID_GND
- PALMAS_USB_ID_INT_EN_HI_CLR
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_A
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_B
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_C
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND
- PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT
- PALMAS_USB_ID_INT_EN_HI_SET
- PALMAS_USB_ID_INT_EN_HI_SET_ID_A
- PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT
- PALMAS_USB_ID_INT_EN_HI_SET_ID_B
- PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT
- PALMAS_USB_ID_INT_EN_HI_SET_ID_C
- PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT
- PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT
- PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_EN_HI_SET_ID_GND
- PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT
- PALMAS_USB_ID_INT_EN_LO_CLR
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_A
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_B
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_C
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND
- PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT
- PALMAS_USB_ID_INT_EN_LO_SET
- PALMAS_USB_ID_INT_EN_LO_SET_ID_A
- PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT
- PALMAS_USB_ID_INT_EN_LO_SET_ID_B
- PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT
- PALMAS_USB_ID_INT_EN_LO_SET_ID_C
- PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT
- PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT
- PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_EN_LO_SET_ID_GND
- PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT
- PALMAS_USB_ID_INT_LATCH_CLR
- PALMAS_USB_ID_INT_LATCH_CLR_ID_A
- PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT
- PALMAS_USB_ID_INT_LATCH_CLR_ID_B
- PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT
- PALMAS_USB_ID_INT_LATCH_CLR_ID_C
- PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT
- PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT
- PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_LATCH_CLR_ID_GND
- PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT
- PALMAS_USB_ID_INT_LATCH_SET
- PALMAS_USB_ID_INT_LATCH_SET_ID_A
- PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT
- PALMAS_USB_ID_INT_LATCH_SET_ID_B
- PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT
- PALMAS_USB_ID_INT_LATCH_SET_ID_C
- PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT
- PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT
- PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_LATCH_SET_ID_GND
- PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT
- PALMAS_USB_ID_INT_SRC
- PALMAS_USB_ID_INT_SRC_ID_A
- PALMAS_USB_ID_INT_SRC_ID_A_SHIFT
- PALMAS_USB_ID_INT_SRC_ID_B
- PALMAS_USB_ID_INT_SRC_ID_B_SHIFT
- PALMAS_USB_ID_INT_SRC_ID_C
- PALMAS_USB_ID_INT_SRC_ID_C_SHIFT
- PALMAS_USB_ID_INT_SRC_ID_FLOAT
- PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT
- PALMAS_USB_ID_INT_SRC_ID_GND
- PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT
- PALMAS_USB_ID_WAKEPUP
- PALMAS_USB_OTG_ADP_CTRL
- PALMAS_USB_OTG_ADP_CTRL_ADP_EN
- PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT
- PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK
- PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT
- PALMAS_USB_OTG_ADP_HIGH
- PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK
- PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT
- PALMAS_USB_OTG_ADP_LOW
- PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK
- PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT
- PALMAS_USB_OTG_ADP_RISE
- PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK
- PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT
- PALMAS_USB_OTG_BASE
- PALMAS_USB_OTG_REVISION
- PALMAS_USB_OTG_REVISION_OTG_REV
- PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT
- PALMAS_USB_STATE_DISCONNECT
- PALMAS_USB_STATE_ID
- PALMAS_USB_STATE_VBUS
- PALMAS_USB_VADP_PRB
- PALMAS_USB_VADP_SNS
- PALMAS_USB_VA_SESS_VLD
- PALMAS_USB_VA_VBUS_VLD
- PALMAS_USB_VBUS_CTRL_CLR
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC
- PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT
- PALMAS_USB_VBUS_CTRL_SET
- PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP
- PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT
- PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS
- PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT
- PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG
- PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT
- PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK
- PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT
- PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC
- PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR
- PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP
- PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET
- PALMAS_USB_VBUS_INT_EN_HI_SET_ADP
- PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB
- PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS
- PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END
- PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET
- PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB
- PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS
- PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END
- PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR
- PALMAS_USB_VBUS_INT_LATCH_CLR_ADP
- PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB
- PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS
- PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END
- PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET
- PALMAS_USB_VBUS_INT_LATCH_SET_ADP
- PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB
- PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS
- PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END
- PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_SRC
- PALMAS_USB_VBUS_INT_SRC_VADP_PRB
- PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VADP_SNS
- PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD
- PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD
- PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VB_SESS_END
- PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD
- PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD
- PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT
- PALMAS_USB_VBUS_WAKEUP
- PALMAS_USB_VB_SESS_END
- PALMAS_USB_VB_SESS_VLD
- PALMAS_USB_VOTG_SESS_VLD
- PALMAS_USB_WAKEUP
- PALMAS_USB_WAKEUP_ID_WK_UP_COMP
- PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT
- PALMAS_VAC_ACOK_IRQ
- PALMAS_VALIDITY_BASE
- PALMAS_VBAT_MON
- PALMAS_VBAT_MON_ENABLE
- PALMAS_VBAT_MON_ENABLE_SHIFT
- PALMAS_VBAT_MON_IRQ
- PALMAS_VBAT_MON_THRESHOLD_MASK
- PALMAS_VBAT_MON_THRESHOLD_SHIFT
- PALMAS_VBUS_IRQ
- PALMAS_VBUS_OTG_IRQ
- PALMAS_VIBRATOR_BASE
- PALMAS_VIBRA_CTRL
- PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK
- PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT
- PALMAS_VIBRA_CTRL_PWM_FREQ_SEL
- PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT
- PALMAS_VSYS_LO
- PALMAS_VSYS_LO_THRESHOLD_MASK
- PALMAS_VSYS_LO_THRESHOLD_SHIFT
- PALMAS_VSYS_MON
- PALMAS_VSYS_MON_ENABLE
- PALMAS_VSYS_MON_ENABLE_SHIFT
- PALMAS_VSYS_MON_IRQ
- PALMAS_VSYS_MON_THRESHOLD_MASK
- PALMAS_VSYS_MON_THRESHOLD_SHIFT
- PALMAS_WATCHDOG
- PALMAS_WATCHDOG_ENABLE
- PALMAS_WATCHDOG_ENABLE_SHIFT
- PALMAS_WATCHDOG_LOCK
- PALMAS_WATCHDOG_LOCK_SHIFT
- PALMAS_WATCHDOG_MODE
- PALMAS_WATCHDOG_MODE_SHIFT
- PALMAS_WATCHDOG_TIMER_MASK
- PALMAS_WATCHDOG_TIMER_SHIFT
- PALMAS_WDT_IRQ
- PALMAS_WEEKS_REG
- PALMAS_WEEKS_REG_WEEK_MASK
- PALMAS_WEEKS_REG_WEEK_SHIFT
- PALMAS_YEARS_REG
- PALMAS_YEARS_REG_YEAR0_MASK
- PALMAS_YEARS_REG_YEAR0_SHIFT
- PALMAS_YEARS_REG_YEAR1_MASK
- PALMAS_YEARS_REG_YEAR1_SHIFT
- PALMCONNECT_PID
- PALMCONNECT_VID
- PALMLD_BAT_MAX_CHARGE
- PALMLD_BAT_MAX_CURRENT
- PALMLD_BAT_MAX_VOLTAGE
- PALMLD_BAT_MEASURE_DELAY
- PALMLD_BAT_MIN_CHARGE
- PALMLD_BAT_MIN_CURRENT
- PALMLD_BAT_MIN_VOLTAGE
- PALMLD_DEFAULT_INTENSITY
- PALMLD_IDE_PHYS
- PALMLD_IDE_SIZE
- PALMLD_IDE_VIRT
- PALMLD_LIMIT_MASK
- PALMLD_MAX_INTENSITY
- PALMLD_MAX_LIFE_MINS
- PALMLD_PERIOD_NS
- PALMLD_PHYS_IO_START
- PALMLD_PRESCALER
- PALMLD_STR_BASE
- PALMLD_USB_PHYS
- PALMLD_USB_SIZE
- PALMLD_USB_VIRT
- PALMT5_BAT_MAX_CHARGE
- PALMT5_BAT_MAX_CURRENT
- PALMT5_BAT_MAX_VOLTAGE
- PALMT5_BAT_MEASURE_DELAY
- PALMT5_BAT_MIN_CHARGE
- PALMT5_BAT_MIN_CURRENT
- PALMT5_BAT_MIN_VOLTAGE
- PALMT5_DEFAULT_INTENSITY
- PALMT5_LIMIT_MASK
- PALMT5_MAX_INTENSITY
- PALMT5_MAX_LIFE_MINS
- PALMT5_PERIOD_NS
- PALMT5_PHYS_IO_START
- PALMT5_PHYS_RAM_START
- PALMT5_PRESCALER
- PALMT5_STR_BASE
- PALMTC_BAT_MAX_CHARGE
- PALMTC_BAT_MAX_CURRENT
- PALMTC_BAT_MAX_VOLTAGE
- PALMTC_BAT_MEASURE_DELAY
- PALMTC_BAT_MIN_CHARGE
- PALMTC_BAT_MIN_CURRENT
- PALMTC_BAT_MIN_VOLTAGE
- PALMTC_DEFAULT_INTENSITY
- PALMTC_LIMIT_MASK
- PALMTC_MAX_INTENSITY
- PALMTC_MAX_LIFE_MINS
- PALMTC_PERIOD_NS
- PALMTC_PRESCALER
- PALMTC_UCB1400_GPIO_OFFSET
- PALMTE2_BAT_MAX_CHARGE
- PALMTE2_BAT_MAX_CURRENT
- PALMTE2_BAT_MAX_VOLTAGE
- PALMTE2_BAT_MIN_CHARGE
- PALMTE2_BAT_MIN_CURRENT
- PALMTE2_BAT_MIN_VOLTAGE
- PALMTE2_DEFAULT_INTENSITY
- PALMTE2_LIMIT_MASK
- PALMTE2_MAX_INTENSITY
- PALMTE2_MAX_LIFE_MINS
- PALMTE2_PERIOD_NS
- PALMTE2_PRESCALER
- PALMTE_DC_GPIO
- PALMTE_HDQ_GPIO
- PALMTE_HEADPHONES_GPIO
- PALMTE_MMC1_GPIO
- PALMTE_MMC2_GPIO
- PALMTE_MMC3_GPIO
- PALMTE_MMC_POWER_GPIO
- PALMTE_MMC_SWITCH_GPIO
- PALMTE_MMC_WP_GPIO
- PALMTE_PINTDAV_GPIO
- PALMTE_SPEAKER_GPIO
- PALMTE_TSC_GPIO
- PALMTE_USBDETECT_GPIO
- PALMTE_USB_OR_DC_GPIO
- PALMTT_CABLE_GPIO
- PALMTT_HDQ_GPIO
- PALMTT_LED_GPIO
- PALMTT_MMC_WP_GPIO
- PALMTT_PENIRQ_GPIO
- PALMTT_USBDETECT_GPIO
- PALMTX_BAT_MAX_CHARGE
- PALMTX_BAT_MAX_CURRENT
- PALMTX_BAT_MAX_VOLTAGE
- PALMTX_BAT_MEASURE_DELAY
- PALMTX_BAT_MIN_CHARGE
- PALMTX_BAT_MIN_CURRENT
- PALMTX_BAT_MIN_VOLTAGE
- PALMTX_DEFAULT_INTENSITY
- PALMTX_LIMIT_MASK
- PALMTX_MAX_INTENSITY
- PALMTX_MAX_LIFE_MINS
- PALMTX_NAND_ALE_PHYS
- PALMTX_NAND_ALE_VIRT
- PALMTX_NAND_CLE_PHYS
- PALMTX_NAND_CLE_VIRT
- PALMTX_PCMCIA_PHYS
- PALMTX_PCMCIA_SIZE
- PALMTX_PCMCIA_VIRT
- PALMTX_PERIOD_NS
- PALMTX_PHYS_FLASH_START
- PALMTX_PHYS_IO_START
- PALMTX_PHYS_NAND_START
- PALMTX_PHYS_RAM_START
- PALMTX_PRESCALER
- PALMTX_STR_BASE
- PALMZ71_CABLE_GPIO
- PALMZ71_HDQ_GPIO
- PALMZ71_HOTSYNC_GPIO
- PALMZ71_MMC_IN_GPIO
- PALMZ71_MMC_WP_GPIO
- PALMZ71_PENIRQ_GPIO
- PALMZ71_SLIDER_GPIO
- PALMZ71_USBDETECT_GPIO
- PALMZ72_BAT_MAX_CHARGE
- PALMZ72_BAT_MAX_CURRENT
- PALMZ72_BAT_MAX_VOLTAGE
- PALMZ72_BAT_MIN_CHARGE
- PALMZ72_BAT_MIN_CURRENT
- PALMZ72_BAT_MIN_VOLTAGE
- PALMZ72_DEFAULT_INTENSITY
- PALMZ72_LIMIT_MASK
- PALMZ72_MAX_INTENSITY
- PALMZ72_MAX_LIFE_MINS
- PALMZ72_PERIOD_NS
- PALMZ72_PRESCALER
- PALMZ72_SAVE_DWORD
- PALM_GEOMETRY_DISABLE
- PALM_GEOMETRY_ENABLE
- PALM_GET_EXT_CONNECTION_INFORMATION
- PALM_I705_ID
- PALM_M100_ID
- PALM_M125_ID
- PALM_M130_ID
- PALM_M500_ID
- PALM_M505_ID
- PALM_M515_ID
- PALM_SUPPORT
- PALM_TREO_650
- PALM_TUNGSTEN_T_ID
- PALM_TUNGSTEN_Z_ID
- PALM_VENDOR_ID
- PALM_ZIRE_ID
- PALN_SUPPORT
- PALO_MAX_TLB_PURGES
- PALO_SIG
- PALVT
- PAL_8x_SUB_CARRIER
- PAL_ARGB1555
- PAL_ARGB4444
- PAL_ARGB8888
- PAL_BASE
- PAL_BRAND_INFO
- PAL_BUS_GET_FEATURES
- PAL_BUS_SET_FEATURES
- PAL_CACHE_ATTR_WB
- PAL_CACHE_ATTR_WT
- PAL_CACHE_ATTR_WT_OR_WB
- PAL_CACHE_FLUSH
- PAL_CACHE_FLUSH_CHK_INTRS
- PAL_CACHE_FLUSH_INVALIDATE
- PAL_CACHE_HINT_NTEMP_1
- PAL_CACHE_HINT_NTEMP_ALL
- PAL_CACHE_HINT_TEMP_1
- PAL_CACHE_INFO
- PAL_CACHE_INIT
- PAL_CACHE_LEVEL_L0
- PAL_CACHE_LEVEL_L1
- PAL_CACHE_LEVEL_L2
- PAL_CACHE_LINE_ID_PART_DATA
- PAL_CACHE_LINE_ID_PART_DATA_PROT
- PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT
- PAL_CACHE_LINE_ID_PART_TAG
- PAL_CACHE_LINE_ID_PART_TAG_PROT
- PAL_CACHE_LINE_INIT
- PAL_CACHE_LINE_STATE_EXCLUSIVE
- PAL_CACHE_LINE_STATE_INVALID
- PAL_CACHE_LINE_STATE_MODIFIED
- PAL_CACHE_LINE_STATE_SHARED
- PAL_CACHE_PROT_INFO
- PAL_CACHE_PROT_METHOD_ECC
- PAL_CACHE_PROT_METHOD_EVEN_PARITY
- PAL_CACHE_PROT_METHOD_NONE
- PAL_CACHE_PROT_METHOD_ODD_PARITY
- PAL_CACHE_PROT_PART_DATA
- PAL_CACHE_PROT_PART_DATA_TAG
- PAL_CACHE_PROT_PART_MAX
- PAL_CACHE_PROT_PART_TAG
- PAL_CACHE_PROT_PART_TAG_DATA
- PAL_CACHE_READ
- PAL_CACHE_SHARED_INFO
- PAL_CACHE_SUMMARY
- PAL_CACHE_TYPE_DATA
- PAL_CACHE_TYPE_INSTRUCTION
- PAL_CACHE_TYPE_INSTRUCTION_DATA
- PAL_CACHE_WRITE
- PAL_CALL
- PAL_CALL_PHYS
- PAL_CALL_PHYS_STK
- PAL_CALL_STK
- PAL_COPY_INFO
- PAL_COPY_PAL
- PAL_DEBUG_INFO
- PAL_DIWSTRT_H
- PAL_DIWSTRT_V
- PAL_ENTER_IA_32_ENV
- PAL_FIXED_ADDR
- PAL_FREQ_BASE
- PAL_FREQ_RATIOS
- PAL_GET_HW_POLICY
- PAL_GET_PSTATE
- PAL_GET_PSTATE_TYPE_AVGANDRESET
- PAL_GET_PSTATE_TYPE_AVGNORESET
- PAL_GET_PSTATE_TYPE_INSTANT
- PAL_GET_PSTATE_TYPE_LASTSET
- PAL_HALT
- PAL_HALT_INFO
- PAL_HALT_LIGHT
- PAL_HTOTAL
- PAL_LIKE
- PAL_LIKE_TIMINGS
- PAL_LOGICAL_TO_PHYSICAL
- PAL_MAX
- PAL_MAX_PURGES
- PAL_MC_CLEAR_LOG
- PAL_MC_DRAIN
- PAL_MC_DYNAMIC_STATE
- PAL_MC_ERROR_INFO
- PAL_MC_ERROR_INJECT
- PAL_MC_EXPECTED
- PAL_MC_HW_TRACKING
- PAL_MC_INFO_BUS_CHECK
- PAL_MC_INFO_CACHE_CHECK
- PAL_MC_INFO_IMPL_DEP
- PAL_MC_INFO_PROCESSOR
- PAL_MC_INFO_REQ_ADDR
- PAL_MC_INFO_RESP_ADDR
- PAL_MC_INFO_TARGET_ADDR
- PAL_MC_INFO_TLB_CHECK
- PAL_MC_PENDING_INIT
- PAL_MC_PENDING_MCA
- PAL_MC_REGISTER_MEM
- PAL_MC_RESUME
- PAL_MEM_ATTRIB
- PAL_MEM_FOR_TEST
- PAL_NONE
- PAL_NUM_ACTIVE_LINES
- PAL_NUM_ACTIVE_PIXELS
- PAL_OV1
- PAL_OV2
- PAL_PERF_MON_INFO
- PAL_PLATFORM_ADDR
- PAL_PMI_ENTRYPOINT
- PAL_PREC_10_12_BIT
- PAL_PREC_AUTO_INCREMENT
- PAL_PREC_INDEX_VALUE
- PAL_PREC_INDEX_VALUE_MASK
- PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT
- PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK
- PAL_PREC_SPLIT_MODE
- PAL_PREFETCH_VISIBILITY
- PAL_PROC_GET_FEATURES
- PAL_PROC_SET_FEATURES
- PAL_PSR_BITS_TO_CLEAR
- PAL_PSR_BITS_TO_SET
- PAL_PTCE_INFO
- PAL_REGISTER_INFO
- PAL_RGB565
- PAL_RSE_INFO
- PAL_SET_HW_POLICY
- PAL_SET_PSTATE
- PAL_SHUTDOWN
- PAL_STATUS_CACHE_INIT_FAIL
- PAL_STATUS_EINVAL
- PAL_STATUS_ERROR
- PAL_STATUS_REQUIRES_MEMORY
- PAL_STATUS_SUCCESS
- PAL_STATUS_UNIMPLEMENTED
- PAL_STIP_DISABLE
- PAL_SUPPORT
- PAL_TEST_PROC
- PAL_TLB_CHECK_OP_PURGE
- PAL_TV_CLOCK_T
- PAL_TV_H_SIZE_UNIT
- PAL_TV_LINES_PER_FRAME
- PAL_TV_PLL_M_14
- PAL_TV_PLL_M_27
- PAL_TV_PLL_N_14
- PAL_TV_PLL_N_27
- PAL_TV_PLL_P_14
- PAL_TV_PLL_P_27
- PAL_TV_VFTOTAL
- PAL_TV_ZERO_H_SIZE
- PAL_VBI_END_LINE
- PAL_VBI_LINES
- PAL_VBI_START_LINE
- PAL_VERSION
- PAL_VISIBILITY_ERROR
- PAL_VISIBILITY_INVAL_ARG
- PAL_VISIBILITY_OK
- PAL_VISIBILITY_OK_REMOTE_NEEDED
- PAL_VISIBILITY_PHYSICAL
- PAL_VISIBILITY_VIRTUAL
- PAL_VM_INFO
- PAL_VM_PAGE_SIZE
- PAL_VM_SUMMARY
- PAL_VM_TR_READ
- PAL_VP_INFO
- PAL_VTOTAL
- PAL_bpt
- PAL_bugchk
- PAL_callsys
- PAL_cflush
- PAL_chmk
- PAL_cserve
- PAL_draina
- PAL_gentrap
- PAL_halt
- PAL_imb
- PAL_jtopal
- PAL_mfpr_vptb
- PAL_nphalt
- PAL_rdmces
- PAL_rdps
- PAL_rduniq
- PAL_rdusp
- PAL_rdval
- PAL_retsys
- PAL_rti
- PAL_swpctx
- PAL_swpipl
- PAL_swppal
- PAL_tbi
- PAL_whami
- PAL_wrent
- PAL_wrfen
- PAL_wripir
- PAL_wrkgp
- PAL_wrmces
- PAL_wrperfmon
- PAL_wruniq
- PAL_wrusp
- PAL_wrval
- PAL_wrvptptr
- PAL_wtint
- PAM
- PAMAC0_DLY_CNTL
- PAMAC1_DLY_CNTL
- PAMAC2_DLY_CNTL
- PAMR
- PAMU_ACCESS_VIOLATION_ENABLE
- PAMU_ACCESS_VIOLATION_STAT
- PAMU_ATTR_CACHE_L1
- PAMU_ATTR_CACHE_L2
- PAMU_ATTR_CACHE_L3
- PAMU_AVAH
- PAMU_AVAL
- PAMU_AVS1
- PAMU_AVS1_APV
- PAMU_AVS1_AV
- PAMU_AVS1_GCV
- PAMU_AVS1_LAV
- PAMU_AVS1_LIODN_SHIFT
- PAMU_AVS1_OTV
- PAMU_AVS1_PDV
- PAMU_AVS1_WAV
- PAMU_AVS2
- PAMU_AV_MASK
- PAMU_CONTROL
- PAMU_EEAHI
- PAMU_EEALO
- PAMU_EEATTR
- PAMU_EECC
- PAMU_EECTL
- PAMU_EEDET
- PAMU_EEDHI
- PAMU_EEDIS
- PAMU_EEDLO
- PAMU_EEINTEN
- PAMU_LAV_LIODN_NOT_IN_PPAACT
- PAMU_MMAP_REGS_BASE
- PAMU_OFFSET
- PAMU_PAGE_SHIFT
- PAMU_PAGE_SIZE
- PAMU_PC
- PAMU_PC1
- PAMU_PC2
- PAMU_PC2_MLIODN
- PAMU_PC3
- PAMU_PC3_MWCE
- PAMU_PC4
- PAMU_PC_OCE
- PAMU_PC_PE
- PAMU_PC_PGC
- PAMU_PC_PPCC
- PAMU_PC_SPCC
- PAMU_PD1
- PAMU_PD2
- PAMU_PD3
- PAMU_PD4
- PAMU_PE
- PAMU_PFA1
- PAMU_PFA2
- PAMU_PGC
- PAMU_PICS
- PAMU_POEAH
- PAMU_POEAL
- PAMU_POES1
- PAMU_POES2
- PAMU_PR1
- PAMU_PR1_MASK
- PAMU_PR2
- PAMU_UDAD
- PAM_BIT
- PAM_CARD
- PANASONIC_FIRST_IF_BASE_IN_KHz
- PANDORABL_WAS_OFF
- PANEL
- PANELCTL_BICTLB_000
- PANELCTL_BICTLB_001
- PANELCTL_BICTLB_CON_MASK
- PANELCTL_BICTL_000
- PANELCTL_BICTL_001
- PANELCTL_BICTL_CON_MASK
- PANELCTL_CLK1_000
- PANELCTL_CLK1_001
- PANELCTL_CLK1_CON_MASK
- PANELCTL_CLK2_000
- PANELCTL_CLK2_001
- PANELCTL_CLK2_CON_MASK
- PANELCTL_EM_CLK1B_110
- PANELCTL_EM_CLK1B_111
- PANELCTL_EM_CLK1B_CON_MASK
- PANELCTL_EM_CLK1_110
- PANELCTL_EM_CLK1_111
- PANELCTL_EM_CLK1_CON_MASK
- PANELCTL_EM_CLK2B_110
- PANELCTL_EM_CLK2B_111
- PANELCTL_EM_CLK2B_CON_MASK
- PANELCTL_EM_CLK2_110
- PANELCTL_EM_CLK2_111
- PANELCTL_EM_CLK2_CON_MASK
- PANELCTL_EM_INT1_000
- PANELCTL_EM_INT1_001
- PANELCTL_EM_INT1_CON_MASK
- PANELCTL_EM_INT2_000
- PANELCTL_EM_INT2_001
- PANELCTL_EM_INT2_CON_MASK
- PANELCTL_GTCON_110
- PANELCTL_GTCON_111
- PANELCTL_GTCON_MASK
- PANELCTL_INT1_000
- PANELCTL_INT1_001
- PANELCTL_INT1_CON_MASK
- PANELCTL_INT2_000
- PANELCTL_INT2_001
- PANELCTL_INT2_CON_MASK
- PANELCTL_SS_1_800
- PANELCTL_SS_800_1
- PANELCTL_SS_MASK
- PANELTYPE
- PANELTYPE_ACTIVE
- PANELTYPE_DSI_CMD
- PANELTYPE_DSI_VIDEO
- PANELTYPE_SMART
- PANELTYPE_TV
- PANEL_10BIT_COLOR
- PANEL_10BIT_PER_COLOR
- PANEL_12BIT_COLOR
- PANEL_12BIT_PER_COLOR
- PANEL_16BIT_COLOR
- PANEL_16BIT_PER_COLOR
- PANEL_6BIT_COLOR
- PANEL_6BIT_PER_COLOR
- PANEL_8BIT_COLOR
- PANEL_8BIT_PER_COLOR
- PANEL_8TO6_DITHER_ENABLE
- PANEL_ALLOW_DISTORT
- PANEL_BPC_UNDEFINE
- PANEL_BYPASS_PWMI
- PANEL_CM_BRIGHTNESS
- PANEL_CM_CE_ENABLE
- PANEL_CM_ENABLE
- PANEL_CM_GAIN
- PANEL_CM_HUE
- PANEL_CM_HUETABLE_END
- PANEL_CM_HUETABLE_START
- PANEL_CM_INTENSITY
- PANEL_CM_PEAK_EN
- PANEL_CM_SATURATION
- PANEL_COLOR_BIT_DEPTH_MASK
- PANEL_COLOR_KEY
- PANEL_COLOR_KEY_MASK_MASK
- PANEL_COLOR_KEY_VALUE_MASK
- PANEL_CURRENT_LINE
- PANEL_CURRENT_LINE_LINE_MASK
- PANEL_DISPLAY_CTRL
- PANEL_DISPLAY_CTRL_CAPTURE_TIMING
- PANEL_DISPLAY_CTRL_COLOR_KEY
- PANEL_DISPLAY_CTRL_DATA
- PANEL_DISPLAY_CTRL_DOUBLE_PIXEL
- PANEL_DISPLAY_CTRL_DUAL_DISPLAY
- PANEL_DISPLAY_CTRL_FIFO
- PANEL_DISPLAY_CTRL_FIFO_1
- PANEL_DISPLAY_CTRL_FIFO_11
- PANEL_DISPLAY_CTRL_FIFO_3
- PANEL_DISPLAY_CTRL_FIFO_7
- PANEL_DISPLAY_CTRL_FORMAT
- PANEL_DISPLAY_CTRL_FORMAT_16
- PANEL_DISPLAY_CTRL_FORMAT_32
- PANEL_DISPLAY_CTRL_FORMAT_8
- PANEL_DISPLAY_CTRL_FPEN
- PANEL_DISPLAY_CTRL_FPVDDEN
- PANEL_DISPLAY_CTRL_HORIZONTAL_PAN
- PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR
- PANEL_DISPLAY_CTRL_RESERVED_MASK
- PANEL_DISPLAY_CTRL_SELECT_CRT
- PANEL_DISPLAY_CTRL_SELECT_MASK
- PANEL_DISPLAY_CTRL_SELECT_PANEL
- PANEL_DISPLAY_CTRL_SELECT_SHIFT
- PANEL_DISPLAY_CTRL_SELECT_VGA
- PANEL_DISPLAY_CTRL_VBIASEN
- PANEL_DISPLAY_CTRL_VERTICAL_PAN
- PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR
- PANEL_DISPLAY_CTRL_VSYNC
- PANEL_DUTY_CONTROL
- PANEL_ENCODER_25FRC_E
- PANEL_ENCODER_25FRC_F
- PANEL_ENCODER_25FRC_MASK
- PANEL_ENCODER_50FRC_A
- PANEL_ENCODER_50FRC_B
- PANEL_ENCODER_50FRC_C
- PANEL_ENCODER_50FRC_D
- PANEL_ENCODER_50FRC_MASK
- PANEL_ENCODER_75FRC_E
- PANEL_ENCODER_75FRC_F
- PANEL_ENCODER_75FRC_MASK
- PANEL_ENCODER_ACTION_COHERENTSEQ
- PANEL_ENCODER_ACTION_DISABLE
- PANEL_ENCODER_ACTION_ENABLE
- PANEL_ENCODER_MISC_COHERENT
- PANEL_ENCODER_MISC_DUAL
- PANEL_ENCODER_MISC_HDMI_TYPE
- PANEL_ENCODER_MISC_TMDS_LINKB
- PANEL_ENCODER_SPATIAL_DITHER_DEPTH
- PANEL_ENCODER_SPATIAL_DITHER_EN
- PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
- PANEL_ENCODER_TEMPORAL_DITHER_EN
- PANEL_ENCODER_TEMPORAL_LEVEL_4
- PANEL_ENCODER_TRUNCATE_DEPTH
- PANEL_ENCODER_TRUNCATE_EN
- PANEL_FB_ADDRESS
- PANEL_FB_ADDRESS_ADDRESS_MASK
- PANEL_FB_ADDRESS_EXT
- PANEL_FB_ADDRESS_STATUS
- PANEL_FB_WIDTH
- PANEL_FB_WIDTH_OFFSET_MASK
- PANEL_FB_WIDTH_WIDTH_MASK
- PANEL_FB_WIDTH_WIDTH_SHIFT
- PANEL_FRAMERATE_CONTROL
- PANEL_FREQ_DIVIDER_HI
- PANEL_FREQ_DIVIDER_LO
- PANEL_HORIZONTAL_SYNC
- PANEL_HORIZONTAL_SYNC_START_MASK
- PANEL_HORIZONTAL_SYNC_WIDTH_MASK
- PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT
- PANEL_HORIZONTAL_TOTAL
- PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK
- PANEL_HORIZONTAL_TOTAL_TOTAL_MASK
- PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT
- PANEL_HWC_ADDRESS
- PANEL_HWC_ADDRESS_ADDRESS_MASK
- PANEL_HWC_ADDRESS_ENABLE
- PANEL_HWC_ADDRESS_EXT
- PANEL_HWC_COLOR_01
- PANEL_HWC_COLOR_01_0_BLUE_MASK
- PANEL_HWC_COLOR_01_0_GREEN_MASK
- PANEL_HWC_COLOR_01_0_RED_MASK
- PANEL_HWC_COLOR_01_1_BLUE_MASK
- PANEL_HWC_COLOR_01_1_GREEN_MASK
- PANEL_HWC_COLOR_01_1_RED_MASK
- PANEL_HWC_COLOR_12
- PANEL_HWC_COLOR_12_1_RGB565_MASK
- PANEL_HWC_COLOR_12_2_RGB565_MASK
- PANEL_HWC_COLOR_2
- PANEL_HWC_COLOR_2_BLUE_MASK
- PANEL_HWC_COLOR_2_GREEN_MASK
- PANEL_HWC_COLOR_2_RED_MASK
- PANEL_HWC_COLOR_3
- PANEL_HWC_COLOR_3_RGB565_MASK
- PANEL_HWC_LOCATION
- PANEL_HWC_LOCATION_LEFT
- PANEL_HWC_LOCATION_TOP
- PANEL_HWC_LOCATION_X_MASK
- PANEL_HWC_LOCATION_Y_MASK
- PANEL_IFACE_CTRL_1
- PANEL_IFACE_CTRL_2
- PANEL_IFACE_CTRL_4
- PANEL_IFACE_CTRL_5
- PANEL_LIGHT_OFF_DELAY_MASK
- PANEL_LIGHT_OFF_DELAY_SHIFT
- PANEL_LIGHT_ON_DELAY_MASK
- PANEL_LIGHT_ON_DELAY_SHIFT
- PANEL_MODIFY_RGB
- PANEL_PALETTE_RAM
- PANEL_PAN_CTRL
- PANEL_PAN_CTRL_HORIZONTAL_PAN_MASK
- PANEL_PAN_CTRL_HORIZONTAL_VSYNC_MASK
- PANEL_PAN_CTRL_VERTICAL_PAN_MASK
- PANEL_PAN_CTRL_VERTICAL_VSYNC_MASK
- PANEL_PLANE_BR
- PANEL_PLANE_BR_BOTTOM_MASK
- PANEL_PLANE_BR_BOTTOM_SHIFT
- PANEL_PLANE_BR_RIGHT_MASK
- PANEL_PLANE_TL
- PANEL_PLANE_TL_LEFT_MASK
- PANEL_PLANE_TL_TOP_MASK
- PANEL_PLANE_TL_TOP_SHIFT
- PANEL_PLL_CTRL
- PANEL_PORT_SELECT_DPA
- PANEL_PORT_SELECT_DPC
- PANEL_PORT_SELECT_DPD
- PANEL_PORT_SELECT_EDP
- PANEL_PORT_SELECT_LVDS
- PANEL_PORT_SELECT_MASK
- PANEL_PORT_SELECT_VLV
- PANEL_POWER_CYCLE_DELAY_MASK
- PANEL_POWER_CYCLE_DELAY_SHIFT
- PANEL_POWER_DOWN_DELAY_MASK
- PANEL_POWER_DOWN_DELAY_SHIFT
- PANEL_POWER_DOWN_TIMEOUT
- PANEL_POWER_OFF
- PANEL_POWER_ON
- PANEL_POWER_RESET
- PANEL_POWER_UP_DELAY_MASK
- PANEL_POWER_UP_DELAY_SHIFT
- PANEL_POWER_UP_TIMEOUT
- PANEL_PROFILE_CUSTOM
- PANEL_PROFILE_HANTRONIX
- PANEL_PROFILE_LARGE
- PANEL_PROFILE_NEW
- PANEL_PROFILE_NEXCOM
- PANEL_PROFILE_OLD
- PANEL_PWM_CONTROL
- PANEL_PWM_MAX
- PANEL_PWM_MAX_VALUE
- PANEL_PWM_MIN
- PANEL_PWM_REF
- PANEL_RANDOM_DITHER
- PANEL_RANDOM_DITHER_MASK
- PANEL_SETUPTIME_CONF_REG
- PANEL_SIMPLE_BOUNDS_CHECK
- PANEL_UNDEFINE
- PANEL_UNLOCK_MASK
- PANEL_UNLOCK_REGS
- PANEL_VERTICAL_SYNC
- PANEL_VERTICAL_SYNC_HEIGHT_MASK
- PANEL_VERTICAL_SYNC_HEIGHT_SHIFT
- PANEL_VERTICAL_SYNC_START_MASK
- PANEL_VERTICAL_TOTAL
- PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK
- PANEL_VERTICAL_TOTAL_TOTAL_MASK
- PANEL_VERTICAL_TOTAL_TOTAL_SHIFT
- PANEL_WINDOW_HEIGHT
- PANEL_WINDOW_HEIGHT_HEIGHT_MASK
- PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT
- PANEL_WINDOW_HEIGHT_Y_MASK
- PANEL_WINDOW_WIDTH
- PANEL_WINDOW_WIDTH_WIDTH_MASK
- PANEL_WINDOW_WIDTH_WIDTH_SHIFT
- PANEL_WINDOW_WIDTH_X_MASK
- PANFROST_BO_HEAP
- PANFROST_BO_NOEXEC
- PANFROST_FEATURE
- PANFROST_FEATURE_ARRAY
- PANFROST_IOCTL
- PANFROST_JD_REQ_FS
- PANFROST_MADV_DONTNEED
- PANFROST_MADV_WILLNEED
- PANGD_HIGH_Z
- PANGD_PULL_DOWN
- PANGD_PULL_MASK
- PANGD_PULL_UP
- PANIC
- PANIC_BLINK_SPD
- PANIC_CPU_INVALID
- PANIC_FREQ
- PANIC_PRINT_ALL_PRINTK_MSG
- PANIC_PRINT_FTRACE_INFO
- PANIC_PRINT_LOCK_INFO
- PANIC_PRINT_MEM_INFO
- PANIC_PRINT_TASK_INFO
- PANIC_PRINT_TIMER_INFO
- PANIC_TIMEOUT
- PANIC_TIMER_STEP
- PANTHER_IMPL
- PANT_DETECTED_INFO
- PANT_DIV_TYPE_E
- PAPAT
- PAPC
- PAPC_ALTERNATE_0
- PAPC_ALTERNATE_B
- PAPC_FAIR
- PAPD2LUT
- PAPD_BLANKING_PROFILE
- PAPD_BLANKING_THRESHOLD
- PAPD_CORR_NORM
- PAPD_STOP_AFTER_LAST_UPDATE
- PAPOUCH_AD4USB_PID
- PAPOUCH_AP485_2_PID
- PAPOUCH_AP485_PID
- PAPOUCH_DRAK5_PID
- PAPOUCH_DRAK6_PID
- PAPOUCH_GMSR_PID
- PAPOUCH_GMUX_PID
- PAPOUCH_IRAMP_PID
- PAPOUCH_LEC_PID
- PAPOUCH_MU_PID
- PAPOUCH_QUIDO10x1_PID
- PAPOUCH_QUIDO2x16_PID
- PAPOUCH_QUIDO2x2_PID
- PAPOUCH_QUIDO30x3_PID
- PAPOUCH_QUIDO3x32_PID
- PAPOUCH_QUIDO4x4_PID
- PAPOUCH_QUIDO60x3_PID
- PAPOUCH_QUIDO8x8_PID
- PAPOUCH_SB232_PID
- PAPOUCH_SB422_2_PID
- PAPOUCH_SB422_PID
- PAPOUCH_SB485C_PID
- PAPOUCH_SB485S_PID
- PAPOUCH_SB485_2_PID
- PAPOUCH_SB485_PID
- PAPOUCH_SIMUKEY_PID
- PAPOUCH_TMU_PID
- PAPOUCH_UPSUSB_PID
- PAPOUCH_VID
- PAPRD_DONE
- PAPRD_GAIN_TABLE_ENTRIES
- PAPRD_IDEAL_AGC2_PWR_RANGE
- PAPRD_PACKET_SENT
- PAPRD_TABLE_SZ
- PAPR_SCM_DIMM_CMD_MASK
- PAPUEN
- PAPUEN_ADDR
- PAR
- PAR0
- PAR1
- PAR2
- PAR3
- PAR4
- PAR5
- PAR96_ACK
- PAR96_BURST
- PAR96_BURSTBITS
- PAR96_DCD
- PAR96_DESCRAM_TAP1
- PAR96_DESCRAM_TAP2
- PAR96_DESCRAM_TAP3
- PAR96_DESCRAM_TAPSH1
- PAR96_DESCRAM_TAPSH2
- PAR96_DESCRAM_TAPSH3
- PAR96_PTT
- PAR96_RXBIT
- PAR96_SCRAM_TAP1
- PAR96_SCRAM_TAPN
- PAR96_TXBIT
- PAR97_POWER
- PARA1_H2C69_DIS_5MS
- PARA1_H2C69_EN_5MS
- PARA1_H2C69_TDMA_2SLOT
- PARA1_H2C69_TDMA_4SLOT
- PARA78
- PARA78_default
- PARA7c
- PARA7c_default
- PARA7c_xxx
- PARAHOTPLUG_TIMEOUT_MS
- PARALLEL
- PARALLEL_0
- PARALLEL_4BIT_IF
- PARALLEL_8BIT_IF
- PARALLEL_ADD_SUB
- PARALLEL_DETECT_FAULT_INT
- PARALLEL_DET_IGNORE_ADVERTISED
- PARALLEL_MBUS_FLAGS
- PARALLEL_RATE_MODE0
- PARALLEL_SCSI
- PARALLEL_TS_MODE
- PARAM
- PARAM0
- PARAM1
- PARAM2
- PARAM3
- PARAM4
- PARAM5
- PARAM6
- PARAM7
- PARAMETER
- PARAMETER_ERROR
- PARAMETER_LIST_LENGTH_ERR
- PARAMETER_SAVE_AREA_OFFSET
- PARAMP_10
- PARAMP_100
- PARAMP_1000
- PARAMP_12
- PARAMP_125
- PARAMP_15
- PARAMP_20
- PARAMP_2000
- PARAMP_25
- PARAMP_250
- PARAMP_31
- PARAMP_3400
- PARAMP_40
- PARAMP_50
- PARAMP_500
- PARAMP_62
- PARAMS
- PARAMS_LEN
- PARAM_BASE
- PARAM_BCN_INTERVAL_CHANGED
- PARAM_BEACON_UPDATE_MASK
- PARAM_BOOT_FLAG_GAME_OS
- PARAM_BOOT_FLAG_OTHER_OS
- PARAM_BUFFER_CONTROL
- PARAM_BUFFER_OTF_INPUT
- PARAM_BUFFER_OTF_OUTPUT
- PARAM_CTRL_BUTTON_O_IS_YES
- PARAM_CTRL_BUTTON_X_IS_YES
- PARAM_DATA
- PARAM_DIS_CONTROL
- PARAM_DIS_OTF_INPUT
- PARAM_DIS_OTF_OUTPUT
- PARAM_DRC_CONTROL
- PARAM_DRC_DMA_INPUT
- PARAM_DRC_OTF_INPUT
- PARAM_DRC_OTF_OUTPUT
- PARAM_DTR
- PARAM_ENDDELAY
- PARAM_FD_CONFIG
- PARAM_FD_CONTROL
- PARAM_FD_DMA_INPUT
- PARAM_FD_OTF_INPUT
- PARAM_FULLDUP
- PARAM_GEN
- PARAM_GEN_ADDR
- PARAM_GLOBAL_SHOTMODE
- PARAM_GROUP
- PARAM_HARDWARE
- PARAM_HT20MHZCOEXIST_CHANGED
- PARAM_HWEVENT
- PARAM_IDLE
- PARAM_INTERRUPT_MASK
- PARAM_INTERRUPT_STATUS
- PARAM_ISP_AA
- PARAM_ISP_ADJUST
- PARAM_ISP_AFC
- PARAM_ISP_AWB
- PARAM_ISP_CONTROL
- PARAM_ISP_DMA1_INPUT
- PARAM_ISP_DMA1_OUTPUT
- PARAM_ISP_DMA2_INPUT
- PARAM_ISP_DMA2_OUTPUT
- PARAM_ISP_FLASH
- PARAM_ISP_IMAGE_EFFECT
- PARAM_ISP_ISO
- PARAM_ISP_METERING
- PARAM_ISP_OTF_INPUT
- PARAM_ISP_OTF_OUTPUT
- PARAM_LIST
- PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED
- PARAM_MAXDEFER
- PARAM_MAXKEY
- PARAM_MAX_STACK
- PARAM_MIN
- PARAM_MUTE
- PARAM_NON_GF_DEVICES_PRESENT_CHANGED
- PARAM_OBSS_MODE_CHANGED
- PARAM_ODC_CONTROL
- PARAM_ODC_OTF_INPUT
- PARAM_ODC_OTF_OUTPUT
- PARAM_PERSIST
- PARAM_RETURN
- PARAM_RIFS_MODE_CHANGED
- PARAM_RTS
- PARAM_RX_BUF_SIZE
- PARAM_RX_BYTES
- PARAM_RX_TRIGGER
- PARAM_SCALERC_CONTROL
- PARAM_SCALERC_DMA_OUTPUT
- PARAM_SCALERC_IMAGE_EFFECT
- PARAM_SCALERC_INPUT_CROP
- PARAM_SCALERC_OTF_INPUT
- PARAM_SCALERC_OTF_OUTPUT
- PARAM_SCALERC_OUTPUT_CROP
- PARAM_SCALERP_CONTROL
- PARAM_SCALERP_DMA_OUTPUT
- PARAM_SCALERP_FLIP
- PARAM_SCALERP_IMAGE_EFFECT
- PARAM_SCALERP_INPUT_CROP
- PARAM_SCALERP_OTF_INPUT
- PARAM_SCALERP_OTF_OUTPUT
- PARAM_SCALERP_OUTPUT_CROP
- PARAM_SCALERP_ROTATION
- PARAM_SENSOR_CONTROL
- PARAM_SENSOR_FRAME_RATE
- PARAM_SENSOR_OTF_OUTPUT
- PARAM_SHORT_PREAMBLE_CHANGED
- PARAM_SHORT_SLOT_TIME_CHANGED
- PARAM_SIZE
- PARAM_SLOTTIME
- PARAM_SOFTDCD
- PARAM_SPEED
- PARAM_TDNR_1ST_FRAME
- PARAM_TDNR_CONTROL
- PARAM_TDNR_DMA_OUTPUT
- PARAM_TDNR_OTF_INPUT
- PARAM_TDNR_OTF_OUTPUT
- PARAM_TX
- PARAM_TXDELAY
- PARAM_TXTAIL
- PARAM_TX_BUF_SIZE
- PARAM_TX_BYTES
- PARAM_TX_TRIGGER
- PARAM_WAIT
- PARAM_WC_LOWER_SHIFT
- PARAM_WC_MASK
- PARAM_WC_UPPER_SHIFT
- PARAM_llACOEXIST_CHANGED
- PARAM_llBCOEXIST_CHANGED
- PARAM_llGCOEXIST_CHANGED
- PARANOIA_ENTRY
- PARANOIA_LC_ELEMENT
- PARANOID_EXIT_TO_KERNEL_MODE
- PARANOID_PATH
- PARAVIRT_CALL
- PARAVIRT_LAZY_CPU
- PARAVIRT_LAZY_MMU
- PARAVIRT_LAZY_NONE
- PARAVIRT_PATCH
- PARA_DLL_BYPASS_MODE
- PARA_DLL_LOCK_NUM
- PARA_DLL_LOCK_NUM_MASK
- PARA_DLL_START
- PARA_DLL_START_MASK
- PARA_HALF_CLK_MODE
- PARA_INDIRECT
- PARA_LEN
- PARA_PATCH
- PARA_PHASE_DET_SEL
- PARA_PHASE_DET_SEL_MASK
- PARA_SITE
- PARCLR
- PARDEVICE_MAX
- PAREG
- PARENB
- PARENT
- PARENTFILENAME_COMMENT
- PARENTS
- PARENT_CLK_EXTERNAL
- PARENT_CLK_NODE1
- PARENT_CLK_NODE2
- PARENT_CLK_NODE3
- PARENT_CLK_NODE4
- PARENT_CLK_SELF
- PARENT_COUNT_MAX
- PARENT_DDB
- PARENT_FAIL_IF
- PARENT_FLGS_CLS_HWINIT
- PARENT_MAX
- PARENT_SKIP_IF_UNSUPPORTED
- PARENT_TOKEN
- PARIDE_H_VERSION
- PARISC_BUG_BREAK_ASM
- PARISC_BUG_BREAK_INSN
- PARISC_IRQ_CR16_COUNTS
- PARISC_ITLB_TRAP
- PARISC_KERNEL_DEATH
- PARISC_KGDB_BREAK_INSN
- PARISC_KGDB_COMPILED_BREAK_INSN
- PARISC_KPROBES_BREAK_INSN
- PARISC_QEMU_MACHINE_HEADER
- PARISC_RT_SIGFRAME_SIZE
- PARISC_RT_SIGFRAME_SIZE32
- PARISC_SC_FLAG_IN_SYSCALL
- PARISC_SC_FLAG_ONSTACK
- PARISC_UAC_MASK
- PARISC_UAC_NOPRINT
- PARISC_UAC_SHIFT
- PARISC_UAC_SIGBUS
- PARITY
- PARITYCHECK
- PARITYCTRL
- PARITYERROR
- PARITYERR_F
- PARITYERR_S
- PARITYERR_V
- PARITYSTATUS
- PARITY_0
- PARITY_1
- PARITY_CHECK_ENABLE
- PARITY_CONTROL
- PARITY_CONTROL_0__ParityCorrThreshold_MASK
- PARITY_CONTROL_0__ParityCorrThreshold__SHIFT
- PARITY_CONTROL_0__ParityUCPThreshold_MASK
- PARITY_CONTROL_0__ParityUCPThreshold__SHIFT
- PARITY_CONTROL_1__ParityErrGenCmd_MASK
- PARITY_CONTROL_1__ParityErrGenCmd__SHIFT
- PARITY_CONTROL_1__ParityErrGenGroupSel_MASK
- PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT
- PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK
- PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT
- PARITY_CONTROL_1__ParityErrGenIdSel_MASK
- PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT
- PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK
- PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT
- PARITY_CONTROL_1__ParityErrGenTrigger_MASK
- PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT
- PARITY_COUNTER_CORR_GRP0__ResetEn_MASK
- PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT
- PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK
- PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT
- PARITY_COUNTER_CORR_GRP1__ResetEn_MASK
- PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT
- PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK
- PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT
- PARITY_COUNTER_CORR_GRP2__ResetEn_MASK
- PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT
- PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK
- PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT
- PARITY_COUNTER_CORR_GRP3__ResetEn_MASK
- PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT
- PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK
- PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT
- PARITY_COUNTER_CORR_GRP4__ResetEn_MASK
- PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT
- PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK
- PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT
- PARITY_COUNTER_UCP_GRP0__ResetEn_MASK
- PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT
- PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK
- PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT
- PARITY_COUNTER_UCP_GRP1__ResetEn_MASK
- PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT
- PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK
- PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT
- PARITY_COUNTER_UCP_GRP2__ResetEn_MASK
- PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT
- PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK
- PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT
- PARITY_COUNTER_UCP_GRP3__ResetEn_MASK
- PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT
- PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK
- PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT
- PARITY_COUNTER_UCP_GRP4__ResetEn_MASK
- PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT
- PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK
- PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT
- PARITY_CRC16_PR0
- PARITY_CRC16_PR0_CCITT
- PARITY_CRC16_PR1
- PARITY_CRC16_PR1_CCITT
- PARITY_CRC32_PR0_CCITT
- PARITY_CRC32_PR1_CCITT
- PARITY_DEFAULT
- PARITY_DISABLE_RMW
- PARITY_EN
- PARITY_ENABLE_RMW
- PARITY_ERR
- PARITY_ERROR
- PARITY_ERROR_CLEAR
- PARITY_ERROR_LSB
- PARITY_ERROR_MSB
- PARITY_ERROR_NORMAL
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK
- PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT
- PARITY_MARK_1
- PARITY_MASK
- PARITY_NONE
- PARITY_PREFER_RMW
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK
- PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK
- PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK
- PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT
- PARITY_SPACE_0
- PARITY_STATUS
- PARKBD_CLOCK
- PARKBD_DATA
- PARM
- PARMAN_ALGO_TYPE_LSORT
- PARMAREA
- PARMBSIZE
- PARMEnable
- PARMRK
- PARMSK
- PARM_A_B_CNT
- PARM_BYTE
- PARM_BYTE_HI
- PARM_BYTE_LO
- PARM_CCNT
- PARM_DMA_CACHE_DEF
- PARM_DST
- PARM_EFFECT
- PARM_ERR
- PARM_GET
- PARM_INTERFACE
- PARM_IS_ALIGNED
- PARM_IS_ALIGN_HI
- PARM_IS_ALIGN_LO
- PARM_IS_BYTE
- PARM_IS_SIGNED
- PARM_IS_WORD
- PARM_LINK_BCNTRLD
- PARM_MIN_MAX
- PARM_MON_FPS
- PARM_MON_SIZE
- PARM_OFFSET
- PARM_OPT
- PARM_RX_MEM_END_DEF
- PARM_RX_NUM_BUFS_DEF
- PARM_RX_TIME_INT_DEF
- PARM_SET
- PARM_SIGN_HI
- PARM_SIGN_LO
- PARM_SIZE
- PARM_SRC
- PARM_SRC_DST_BIDX
- PARM_SRC_DST_CIDX
- PARM_TX_NUM_BUFS_DEF
- PARM_TX_TIME_INT_DEF
- PARM_WORD
- PARODD
- PARP
- PARPORT_CLASS_DIGCAM
- PARPORT_CLASS_FDC
- PARPORT_CLASS_HDC
- PARPORT_CLASS_LEGACY
- PARPORT_CLASS_MEDIA
- PARPORT_CLASS_MODEM
- PARPORT_CLASS_NET
- PARPORT_CLASS_OTHER
- PARPORT_CLASS_PCMCIA
- PARPORT_CLASS_PORTS
- PARPORT_CLASS_PRINTER
- PARPORT_CLASS_SCANNER
- PARPORT_CLASS_SCSIADAPTER
- PARPORT_CLASS_UNSPEC
- PARPORT_CONTROL_AUTOFD
- PARPORT_CONTROL_INIT
- PARPORT_CONTROL_SELECT
- PARPORT_CONTROL_STROBE
- PARPORT_CTRL_BIDIR_ENA
- PARPORT_CTRL_IRQ_ENA
- PARPORT_CTRL_REG
- PARPORT_DATA_REG
- PARPORT_DEBUG_SHARING
- PARPORT_DEFAULT_TIMESLICE
- PARPORT_DEVICES_ROOT_DIR
- PARPORT_DEVPROC_REGISTERED
- PARPORT_DEV_DIR
- PARPORT_DEV_EXCL
- PARPORT_DEV_LURK
- PARPORT_DEV_TRAN
- PARPORT_DISABLE
- PARPORT_DMA_AUTO
- PARPORT_DMA_NOFIFO
- PARPORT_DMA_NONE
- PARPORT_EPP_FAST
- PARPORT_FLAG_EXCL
- PARPORT_GSC_OFFSET
- PARPORT_INACTIVITY_O_NONBLOCK
- PARPORT_IOHI_AUTO
- PARPORT_IP32_ENABLE_DMA
- PARPORT_IP32_ENABLE_ECP
- PARPORT_IP32_ENABLE_EPP
- PARPORT_IP32_ENABLE_IRQ
- PARPORT_IP32_ENABLE_SPP
- PARPORT_IP32_IRQ_FWD
- PARPORT_IP32_IRQ_HERE
- PARPORT_IRQ_AUTO
- PARPORT_IRQ_NONE
- PARPORT_IRQ_PROBEONLY
- PARPORT_MAX
- PARPORT_MAX_SPINTIME_VALUE
- PARPORT_MAX_TIMESLICE_VALUE
- PARPORT_MIN_SPINTIME_VALUE
- PARPORT_MIN_TIMESLICE_VALUE
- PARPORT_MODE_COMPAT
- PARPORT_MODE_DMA
- PARPORT_MODE_ECP
- PARPORT_MODE_EPP
- PARPORT_MODE_PCSPP
- PARPORT_MODE_SAFEININT
- PARPORT_MODE_TRISTATE
- PARPORT_PARANOID
- PARPORT_PARPORT_DIR
- PARPORT_PC_MAX_PORTS
- PARPORT_PORT_DIR
- PARPORT_PRIMARY_BASE
- PARPORT_STATUS_ACK
- PARPORT_STATUS_BUSY
- PARPORT_STATUS_ERROR
- PARPORT_STATUS_PAPEROUT
- PARPORT_STATUS_REG
- PARPORT_STATUS_SELECT
- PARPORT_W91284PIC
- PARP_BASE
- PARP_DRQ
- PARP_INTERRUPT
- PARP_IRQ
- PARSER
- PARSER0
- PARSER1
- PARSER2
- PARSER_ALL
- PARSER_CONFIG
- PARSER_CONTROL
- PARSER_ES_CONTROL
- PARSER_ETH_CONN_CM_HDR
- PARSER_ETH_CONN_GFT_ACTION_CM_HDR
- PARSER_FETCH_ADDR
- PARSER_FETCH_CMD
- PARSER_INTSTAT_SC_FOUND
- PARSER_INT_ENABLE
- PARSER_INT_HOST_EN_BIT
- PARSER_INT_STATUS
- PARSER_MASK
- PARSER_SEARCH_MASK
- PARSER_SEARCH_PATTERN
- PARSER_VIDEO_END_PTR
- PARSER_VIDEO_HOLE
- PARSER_VIDEO_START_PTR
- PARSER_VIDEO_WP
- PARSE_BD_INDEX
- PARSE_CTX_H
- PARSE_EOF
- PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT
- PARSE_EVENTS__TERM_TYPE_BRANCH_SAMPLE_TYPE
- PARSE_EVENTS__TERM_TYPE_CALLGRAPH
- PARSE_EVENTS__TERM_TYPE_CONFIG
- PARSE_EVENTS__TERM_TYPE_CONFIG1
- PARSE_EVENTS__TERM_TYPE_CONFIG2
- PARSE_EVENTS__TERM_TYPE_DRV_CFG
- PARSE_EVENTS__TERM_TYPE_INHERIT
- PARSE_EVENTS__TERM_TYPE_MAX_EVENTS
- PARSE_EVENTS__TERM_TYPE_MAX_STACK
- PARSE_EVENTS__TERM_TYPE_NAME
- PARSE_EVENTS__TERM_TYPE_NOINHERIT
- PARSE_EVENTS__TERM_TYPE_NOOVERWRITE
- PARSE_EVENTS__TERM_TYPE_NUM
- PARSE_EVENTS__TERM_TYPE_OVERWRITE
- PARSE_EVENTS__TERM_TYPE_PERCORE
- PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ
- PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD
- PARSE_EVENTS__TERM_TYPE_STACKSIZE
- PARSE_EVENTS__TERM_TYPE_STR
- PARSE_EVENTS__TERM_TYPE_TIME
- PARSE_EVENTS__TERM_TYPE_USER
- PARSE_INVALID
- PARSE_IP
- PARSE_IPV6
- PARSE_IP_PROG_FD
- PARSE_IRDATA
- PARSE_LIST
- PARSE_MOUNT
- PARSE_MPLS
- PARSE_NOT_LONGNAME
- PARSE_OPT_CANSKIP
- PARSE_OPT_DISABLED
- PARSE_OPT_DONE
- PARSE_OPT_EXCLUSIVE
- PARSE_OPT_HELP
- PARSE_OPT_HIDDEN
- PARSE_OPT_KEEP_ARGV0
- PARSE_OPT_KEEP_DASHDASH
- PARSE_OPT_KEEP_UNKNOWN
- PARSE_OPT_LASTARG_DEFAULT
- PARSE_OPT_LIST_OPTS
- PARSE_OPT_LIST_SUBCMDS
- PARSE_OPT_NOARG
- PARSE_OPT_NOBUILD
- PARSE_OPT_NOEMPTY
- PARSE_OPT_NONEG
- PARSE_OPT_NO_INTERNAL_HELP
- PARSE_OPT_OPTARG
- PARSE_OPT_STOP_AT_NON_OPTION
- PARSE_OPT_UNKNOWN
- PARSE_REMOUNT
- PARSE_TIME
- PARSE_VLAN
- PARSE_ZOFS
- PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK
- PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT
- PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK
- PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT
- PARSING_AND_ERR_FLAGS_L3TYPE_MASK
- PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT
- PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK
- PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT
- PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK
- PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT
- PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK
- PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT
- PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK
- PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT
- PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK
- PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT
- PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK
- PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT
- PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK
- PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT
- PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK
- PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT
- PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK
- PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT
- PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK
- PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT
- PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK
- PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK
- PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK
- PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK
- PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK
- PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK
- PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT
- PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK
- PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT
- PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK
- PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT
- PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK
- PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT
- PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK
- PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT
- PARSING_ERR_FLAGS_MAC_ERROR_MASK
- PARSING_ERR_FLAGS_MAC_ERROR_SHIFT
- PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK
- PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT
- PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK
- PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT
- PARSING_ERR_FLAGS_TRUNC_ERROR_MASK
- PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT
- PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK
- PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT
- PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK
- PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT
- PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK
- PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT
- PARSING_FLAGS_CONNECTION_MATCH
- PARSING_FLAGS_CONNECTION_MATCH_SHIFT
- PARSING_FLAGS_ETHERNET_ADDRESS_TYPE
- PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT
- PARSING_FLAGS_EXTRA_VLAN
- PARSING_FLAGS_EXTRA_VLAN_SHIFT
- PARSING_FLAGS_FRAGMENTATION_STATUS
- PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT
- PARSING_FLAGS_IP_OPTIONS
- PARSING_FLAGS_IP_OPTIONS_SHIFT
- PARSING_FLAGS_LLC_SNAP
- PARSING_FLAGS_LLC_SNAP_SHIFT
- PARSING_FLAGS_OVER_ETHERNET_PROTOCOL
- PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT
- PARSING_FLAGS_OVER_IP_PROTOCOL
- PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT
- PARSING_FLAGS_PURE_ACK_INDICATION
- PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT
- PARSING_FLAGS_RESERVED0
- PARSING_FLAGS_RESERVED0_SHIFT
- PARSING_FLAGS_TCP_OPTIONS_EXIST
- PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT
- PARSING_FLAGS_TIME_STAMP_EXIST_FLAG
- PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT
- PARSING_FLAGS_VLAN
- PARSING_FLAGS_VLAN_SHIFT
- PART
- PART1OFFSET
- PART2OFFSET
- PART3OFFSET
- PART4OFFSET
- PART5OFFSET
- PARTIAL
- PARTIALSUCCESS
- PARTIAL_BLOCK
- PARTIAL_DATA
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
- PARTIAL_NODE
- PARTIAL_POWER_ON
- PARTIAL_VBM_MAX
- PARTITION_BASIC_DATA_GUID
- PARTITION_COUNT
- PARTITION_LINUX
- PARTITION_LINUX_LVM_GUID
- PARTITION_LINUX_RAID_GUID
- PARTITION_LINUX_SWAP_GUID
- PARTITION_META_INFO_UUIDLTH
- PARTITION_META_INFO_VOLNAMELTH
- PARTITION_MSFT_RESERVED_GUID
- PARTITION_NAMELEN
- PARTITION_RISCIX_MFM
- PARTITION_RISCIX_SCSI
- PARTITION_SHIFT
- PARTITION_SYSTEM_GUID
- PARTNER_DEREGISTER
- PARTNER_FAILED
- PARTNO_92D_NIC
- PARTNO_92D_NIC_REMARK
- PARTNO_CONCURRENT_BAND_VC
- PARTNO_CONCURRENT_BAND_VC_REMARK
- PARTNO_SINGLE_BAND_VS
- PARTNO_SINGLE_BAND_VS_REMARK
- PARTN_BITS
- PARTROUNDS
- PARTS_PER_DISK
- PARTS_PER_EXT_DISK
- PART_BITS
- PART_BLOB_LEN
- PART_BLOB_START
- PART_BOOT
- PART_BOOT_SIZE
- PART_BOOT_START
- PART_DESC_ALLOC_STEP
- PART_DOWN
- PART_DRPW
- PART_FPGA_SIZE
- PART_FPGA_START
- PART_FRAC_EVEN
- PART_FRAC_ODD
- PART_GDA_VERSION
- PART_IMAGE_SIZE
- PART_IMAGE_START
- PART_INITRD_LEN
- PART_INITRD_START
- PART_INTEGER
- PART_KERNEL_LEN
- PART_KERNEL_START
- PART_MASK
- PART_NO_SIG
- PART_PAGE
- PART_PAGE_FIXED_LENGTH
- PART_PHY_INIT
- PART_POW2
- PART_REV
- PART_SHIFT
- PART_SIZE
- PART_SLIM_VAR
- PART_TABLE_LEN
- PART_TOP_PRCM_ELP_SOC
- PART_TYPE_X4
- PART_TYPE_X8
- PART_WORK
- PAR_ABS_VLD
- PAR_CALC_EN
- PAR_CONTROL
- PAR_DATA
- PAR_EL1
- PAR_ENA
- PAR_ENAB
- PAR_ENABLE
- PAR_EQUAL
- PAR_ERR
- PAR_ERR_INT
- PAR_EVEN
- PAR_GRP_VLD
- PAR_ID_VLD
- PAR_IRQ
- PAR_MARK
- PAR_MODE_MSK
- PAR_MODE_SHFT
- PAR_MT_EN
- PAR_NOFAULT_MT
- PAR_NOFAULT_MT_MASK
- PAR_NOFAULT_MT_SHIFT
- PAR_NOFAULT_NOS
- PAR_NOFAULT_NOS_MASK
- PAR_NOFAULT_NOS_SHIFT
- PAR_NOFAULT_NS
- PAR_NOFAULT_NS_MASK
- PAR_NOFAULT_NS_SHIFT
- PAR_NOFAULT_SH
- PAR_NOFAULT_SH_MASK
- PAR_NOFAULT_SH_SHIFT
- PAR_NOFAULT_SS
- PAR_NOFAULT_SS_MASK
- PAR_NOFAULT_SS_SHIFT
- PAR_NPFAULT_PA
- PAR_NPFAULT_PA_MASK
- PAR_NPFAULT_PA_SHIFT
- PAR_ODD
- PAR_PCNT_VLD
- PAR_SPACE
- PAR_SPEC
- PAR_STATUS
- PAR_TO_HPFAR
- PAR_WGHT_VLD
- PAS106_REG0e
- PAS106_REG13
- PAS106_REG2
- PAS106_REG3
- PAS106_REG4
- PAS106_REG5
- PAS106_REG6
- PAS106_REG7
- PAS106_REG9
- PASCAL_A
- PASCAL_B
- PASCAL_CHANNEL_GPFIFO_A
- PASCAL_COMPUTE_A
- PASCAL_COMPUTE_B
- PASCAL_DMA_COPY_A
- PASCAL_DMA_COPY_B
- PASCR_SE
- PASEL
- PASEL_ADDR
- PASEMI_EDAC_ERROR_GRAIN
- PASEMI_EDAC_NR_CHANS
- PASEMI_EDAC_NR_CSROWS
- PASEMI_MAC_H
- PASEMI_MSI_ADDR
- PASIC3_BIT2_LED0
- PASIC3_BIT2_LED1
- PASIC3_BIT2_LED2
- PASIC3_MASK_LED0
- PASIC3_MASK_LED1
- PASIC3_MASK_LED2
- PASID_FLAG_SUPERVISOR_MODE
- PASID_MASK
- PASID_MAX
- PASID_MIN
- PASID_NUMBER_MASK
- PASID_NUMBER_SHIFT
- PASID_PDE_SHIFT
- PASID_PTE_MASK
- PASID_PTE_PRESENT
- PASID_RID2PASID
- PASID_TBL_ENTRIES
- PASORI_PRODUCT_ID
- PASR
- PASR_MASK
- PASR_SHIFT
- PASS
- PASS0_SUMS
- PASS1_SUMS
- PASS2_SUMS
- PASS3_SUMS
- PASSALL
- PASSED
- PASSIVE_BYPASS
- PASSIVE_DATA_LEN
- PASSIVE_SCAN
- PASSIVE_SCAN_LISTEN
- PASSIVE_SCAN_WAIT
- PASSTHRU_CMD
- PASSTHRU_DISABLE
- PASSTHRU_ENABLE
- PASSTHRU_FSCTL
- PASSTHRU_GET_ADAPTER
- PASSTHRU_GET_DRVVER
- PASSTHRU_IGNORE
- PASSTHRU_QUERY_INFO
- PASSTHRU_REQ_NO_WAKEUP
- PASSTHRU_REQ_TYPE
- PASSTHRU_SET_INFO
- PASSTHRU_SIGNATURE
- PASSTHRU_STATUS_COMPLETE
- PASS_ACCEPT_REQ
- PASS_BAD_FRAMES
- PASS_ERR_SK_SELECT_REUSEPORT
- PASS_ESTAB
- PASS_FROM_SPHY_TO_AFE
- PASS_INFO
- PASS_LIMIT
- PASS_NAME
- PASS_OPEN_TID_G
- PASS_OPEN_TID_M
- PASS_OPEN_TID_S
- PASS_OPEN_TID_V
- PASS_OPEN_TOS_G
- PASS_OPEN_TOS_M
- PASS_OPEN_TOS_S
- PASS_OPEN_TOS_V
- PASS_PRI_TAGGED
- PASS_REPLAY
- PASS_REVOKE
- PASS_SCAN
- PASS_THROUGH_STATE
- PASS_THRU_MASK
- PASTE
- PASTE1
- PASTE2
- PAS_DMA_CAP_IFI
- PAS_DMA_CAP_IFI_IOFF_M
- PAS_DMA_CAP_IFI_IOFF_S
- PAS_DMA_CAP_IFI_NIN_M
- PAS_DMA_CAP_IFI_NIN_S
- PAS_DMA_CAP_RXCH
- PAS_DMA_CAP_RXCH_RCHN_M
- PAS_DMA_CAP_RXCH_RCHN_S
- PAS_DMA_CAP_TXCH
- PAS_DMA_CAP_TXCH_TCHN_M
- PAS_DMA_CAP_TXCH_TCHN_S
- PAS_DMA_COM_CFG
- PAS_DMA_COM_RXCMD
- PAS_DMA_COM_RXCMD_EN
- PAS_DMA_COM_RXSTA
- PAS_DMA_COM_RXSTA_ACT
- PAS_DMA_COM_TXCMD
- PAS_DMA_COM_TXCMD_EN
- PAS_DMA_COM_TXSTA
- PAS_DMA_COM_TXSTA_ACT
- PAS_DMA_RXCHAN_BASEL
- PAS_DMA_RXCHAN_BASEL_BRBL
- PAS_DMA_RXCHAN_BASEL_BRBL_M
- PAS_DMA_RXCHAN_BASEL_BRBL_S
- PAS_DMA_RXCHAN_BASEU
- PAS_DMA_RXCHAN_BASEU_BRBH
- PAS_DMA_RXCHAN_BASEU_BRBH_M
- PAS_DMA_RXCHAN_BASEU_BRBH_S
- PAS_DMA_RXCHAN_BASEU_SIZ
- PAS_DMA_RXCHAN_BASEU_SIZ_M
- PAS_DMA_RXCHAN_BASEU_SIZ_S
- PAS_DMA_RXCHAN_CCMDSTA
- PAS_DMA_RXCHAN_CCMDSTA_ACT
- PAS_DMA_RXCHAN_CCMDSTA_DT
- PAS_DMA_RXCHAN_CCMDSTA_DU
- PAS_DMA_RXCHAN_CCMDSTA_EN
- PAS_DMA_RXCHAN_CCMDSTA_FD
- PAS_DMA_RXCHAN_CCMDSTA_OD
- PAS_DMA_RXCHAN_CCMDSTA_ST
- PAS_DMA_RXCHAN_CFG
- PAS_DMA_RXCHAN_CFG_CTR
- PAS_DMA_RXCHAN_CFG_HBU
- PAS_DMA_RXCHAN_CFG_HBU_M
- PAS_DMA_RXCHAN_CFG_HBU_S
- PAS_DMA_RXCHAN_INCR
- PAS_DMA_RXINT_BASEL
- PAS_DMA_RXINT_BASEL_BRBL
- PAS_DMA_RXINT_BASEU
- PAS_DMA_RXINT_BASEU_BRBH
- PAS_DMA_RXINT_BASEU_SIZ
- PAS_DMA_RXINT_BASEU_SIZ_M
- PAS_DMA_RXINT_BASEU_SIZ_S
- PAS_DMA_RXINT_CFG
- PAS_DMA_RXINT_CFG_DHL
- PAS_DMA_RXINT_CFG_DHL_M
- PAS_DMA_RXINT_CFG_DHL_S
- PAS_DMA_RXINT_CFG_HEN
- PAS_DMA_RXINT_CFG_ITR
- PAS_DMA_RXINT_CFG_ITRR
- PAS_DMA_RXINT_CFG_L2
- PAS_DMA_RXINT_CFG_LW
- PAS_DMA_RXINT_CFG_RBP
- PAS_DMA_RXINT_CFG_WIF
- PAS_DMA_RXINT_CFG_WIL
- PAS_DMA_RXINT_INCR
- PAS_DMA_RXINT_INCR_INCR
- PAS_DMA_RXINT_INCR_INCR_M
- PAS_DMA_RXINT_INCR_INCR_S
- PAS_DMA_RXINT_RCMDSTA
- PAS_DMA_RXINT_RCMDSTA_ACT
- PAS_DMA_RXINT_RCMDSTA_BP
- PAS_DMA_RXINT_RCMDSTA_BT
- PAS_DMA_RXINT_RCMDSTA_DR
- PAS_DMA_RXINT_RCMDSTA_DROPS_M
- PAS_DMA_RXINT_RCMDSTA_DROPS_S
- PAS_DMA_RXINT_RCMDSTA_EN
- PAS_DMA_RXINT_RCMDSTA_MBP
- PAS_DMA_RXINT_RCMDSTA_MBT
- PAS_DMA_RXINT_RCMDSTA_MDR
- PAS_DMA_RXINT_RCMDSTA_MOO
- PAS_DMA_RXINT_RCMDSTA_OO
- PAS_DMA_RXINT_RCMDSTA_ST
- PAS_DMA_RXINT_RCMDSTA_TB
- PAS_DMA_TXCHAN_BASEL
- PAS_DMA_TXCHAN_BASEL_BRBL
- PAS_DMA_TXCHAN_BASEL_BRBL_M
- PAS_DMA_TXCHAN_BASEL_BRBL_S
- PAS_DMA_TXCHAN_BASEU
- PAS_DMA_TXCHAN_BASEU_BRBH
- PAS_DMA_TXCHAN_BASEU_BRBH_M
- PAS_DMA_TXCHAN_BASEU_BRBH_S
- PAS_DMA_TXCHAN_BASEU_SIZ
- PAS_DMA_TXCHAN_BASEU_SIZ_M
- PAS_DMA_TXCHAN_BASEU_SIZ_S
- PAS_DMA_TXCHAN_CFG
- PAS_DMA_TXCHAN_CFG_CF
- PAS_DMA_TXCHAN_CFG_CL
- PAS_DMA_TXCHAN_CFG_LPDQ
- PAS_DMA_TXCHAN_CFG_LPSQ
- PAS_DMA_TXCHAN_CFG_TATTR
- PAS_DMA_TXCHAN_CFG_TATTR_M
- PAS_DMA_TXCHAN_CFG_TATTR_S
- PAS_DMA_TXCHAN_CFG_TRD
- PAS_DMA_TXCHAN_CFG_TRR
- PAS_DMA_TXCHAN_CFG_TY_COPY
- PAS_DMA_TXCHAN_CFG_TY_FUNC
- PAS_DMA_TXCHAN_CFG_TY_IFACE
- PAS_DMA_TXCHAN_CFG_TY_XOR
- PAS_DMA_TXCHAN_CFG_UP
- PAS_DMA_TXCHAN_CFG_WT
- PAS_DMA_TXCHAN_CFG_WT_M
- PAS_DMA_TXCHAN_CFG_WT_S
- PAS_DMA_TXCHAN_INCR
- PAS_DMA_TXCHAN_TCMDSTA
- PAS_DMA_TXCHAN_TCMDSTA_ACT
- PAS_DMA_TXCHAN_TCMDSTA_DA
- PAS_DMA_TXCHAN_TCMDSTA_DB
- PAS_DMA_TXCHAN_TCMDSTA_DE
- PAS_DMA_TXCHAN_TCMDSTA_EN
- PAS_DMA_TXCHAN_TCMDSTA_ST
- PAS_DMA_TXCHAN_TCMDSTA_SZ
- PAS_DMA_TXF_CFLG0
- PAS_DMA_TXF_CFLG1
- PAS_DMA_TXF_SFLG0
- PAS_DMA_TXF_SFLG1
- PAS_IOB_COM_PKTHDRCNT
- PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M
- PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S
- PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M
- PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S
- PAS_IOB_DMA_COM_TIMEOUTCFG
- PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT
- PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M
- PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S
- PAS_IOB_DMA_RXCH_CFG
- PAS_IOB_DMA_RXCH_CFG_CNTTH
- PAS_IOB_DMA_RXCH_CFG_CNTTH_M
- PAS_IOB_DMA_RXCH_CFG_CNTTH_S
- PAS_IOB_DMA_RXCH_RESET
- PAS_IOB_DMA_RXCH_RESET_DCNTRST
- PAS_IOB_DMA_RXCH_RESET_DINTC
- PAS_IOB_DMA_RXCH_RESET_PCNT
- PAS_IOB_DMA_RXCH_RESET_PCNTRST
- PAS_IOB_DMA_RXCH_RESET_PCNT_M
- PAS_IOB_DMA_RXCH_RESET_PCNT_S
- PAS_IOB_DMA_RXCH_RESET_PINTC
- PAS_IOB_DMA_RXCH_RESET_SINTC
- PAS_IOB_DMA_RXCH_RESET_TINTC
- PAS_IOB_DMA_RXCH_STAT
- PAS_IOB_DMA_RXCH_STAT_CNTDEL
- PAS_IOB_DMA_RXCH_STAT_CNTDEL_M
- PAS_IOB_DMA_RXCH_STAT_CNTDEL_S
- PAS_IOB_DMA_RXCH_STAT_INTGEN
- PAS_IOB_DMA_TXCH_CFG
- PAS_IOB_DMA_TXCH_CFG_CNTTH
- PAS_IOB_DMA_TXCH_CFG_CNTTH_M
- PAS_IOB_DMA_TXCH_CFG_CNTTH_S
- PAS_IOB_DMA_TXCH_RESET
- PAS_IOB_DMA_TXCH_RESET_DCNTRST
- PAS_IOB_DMA_TXCH_RESET_DINTC
- PAS_IOB_DMA_TXCH_RESET_PCNT
- PAS_IOB_DMA_TXCH_RESET_PCNTRST
- PAS_IOB_DMA_TXCH_RESET_PCNT_M
- PAS_IOB_DMA_TXCH_RESET_PCNT_S
- PAS_IOB_DMA_TXCH_RESET_PINTC
- PAS_IOB_DMA_TXCH_RESET_SINTC
- PAS_IOB_DMA_TXCH_RESET_TINTC
- PAS_IOB_DMA_TXCH_STAT
- PAS_IOB_DMA_TXCH_STAT_CNTDEL
- PAS_IOB_DMA_TXCH_STAT_CNTDEL_M
- PAS_IOB_DMA_TXCH_STAT_CNTDEL_S
- PAS_IOB_DMA_TXCH_STAT_INTGEN
- PAS_MAC_CFG_ADR0
- PAS_MAC_CFG_ADR1
- PAS_MAC_CFG_MACCFG
- PAS_MAC_CFG_MACCFG_MAXF
- PAS_MAC_CFG_MACCFG_MAXF_M
- PAS_MAC_CFG_MACCFG_MAXF_S
- PAS_MAC_CFG_MACCFG_MINF_M
- PAS_MAC_CFG_MACCFG_MINF_S
- PAS_MAC_CFG_MACCFG_PRES_M
- PAS_MAC_CFG_MACCFG_PRES_S
- PAS_MAC_CFG_MACCFG_TXT_M
- PAS_MAC_CFG_MACCFG_TXT_S
- PAS_MAC_CFG_PCFG
- PAS_MAC_CFG_PCFG_BU
- PAS_MAC_CFG_PCFG_CE
- PAS_MAC_CFG_PCFG_CRO_M
- PAS_MAC_CFG_PCFG_CRO_S
- PAS_MAC_CFG_PCFG_HD
- PAS_MAC_CFG_PCFG_IO_IND_ETH
- PAS_MAC_CFG_PCFG_IO_IND_IP
- PAS_MAC_CFG_PCFG_IO_M
- PAS_MAC_CFG_PCFG_IO_MAC
- PAS_MAC_CFG_PCFG_IO_OFF
- PAS_MAC_CFG_PCFG_IPO_M
- PAS_MAC_CFG_PCFG_IPO_S
- PAS_MAC_CFG_PCFG_LP
- PAS_MAC_CFG_PCFG_PE
- PAS_MAC_CFG_PCFG_PR
- PAS_MAC_CFG_PCFG_S1
- PAS_MAC_CFG_PCFG_SPD_100M
- PAS_MAC_CFG_PCFG_SPD_10G
- PAS_MAC_CFG_PCFG_SPD_10M
- PAS_MAC_CFG_PCFG_SPD_1G
- PAS_MAC_CFG_PCFG_SPD_M
- PAS_MAC_CFG_PCFG_T24
- PAS_MAC_CFG_PCFG_TS
- PAS_MAC_CFG_PCFG_TSR_100M
- PAS_MAC_CFG_PCFG_TSR_10G
- PAS_MAC_CFG_PCFG_TSR_10M
- PAS_MAC_CFG_PCFG_TSR_1G
- PAS_MAC_CFG_PCFG_TSR_M
- PAS_MAC_CFG_PCFG_TT
- PAS_MAC_CFG_RMON
- PAS_MAC_CFG_TXP
- PAS_MAC_CFG_TXP_BL
- PAS_MAC_CFG_TXP_COB
- PAS_MAC_CFG_TXP_COB_M
- PAS_MAC_CFG_TXP_COB_S
- PAS_MAC_CFG_TXP_FC
- PAS_MAC_CFG_TXP_FCE
- PAS_MAC_CFG_TXP_FCF
- PAS_MAC_CFG_TXP_FPC
- PAS_MAC_CFG_TXP_FPC_M
- PAS_MAC_CFG_TXP_FPC_S
- PAS_MAC_CFG_TXP_RT
- PAS_MAC_CFG_TXP_SL
- PAS_MAC_CFG_TXP_SL_M
- PAS_MAC_CFG_TXP_SL_S
- PAS_MAC_CFG_TXP_TIFG
- PAS_MAC_CFG_TXP_TIFG_M
- PAS_MAC_CFG_TXP_TIFG_S
- PAS_MAC_CFG_TXP_TIFT
- PAS_MAC_CFG_TXP_TIFT_M
- PAS_MAC_CFG_TXP_TIFT_S
- PAS_MAC_IPC_CHNL
- PAS_MAC_IPC_CHNL_BCH
- PAS_MAC_IPC_CHNL_BCH_M
- PAS_MAC_IPC_CHNL_BCH_S
- PAS_MAC_IPC_CHNL_DCHNO
- PAS_MAC_IPC_CHNL_DCHNO_M
- PAS_MAC_IPC_CHNL_DCHNO_S
- PAS_MAC_RMON
- PAS_STATUS_BPCNT_M
- PAS_STATUS_BPCNT_S
- PAS_STATUS_CAUSE_M
- PAS_STATUS_DCNT_M
- PAS_STATUS_DCNT_S
- PAS_STATUS_ERROR
- PAS_STATUS_INT
- PAS_STATUS_PCNT_M
- PAS_STATUS_PCNT_S
- PAS_STATUS_SOFT
- PAS_STATUS_TIMER
- PAT
- PATA_IMX_ATA_CONTROL
- PATA_IMX_ATA_CTRL_ATA_RST_B
- PATA_IMX_ATA_CTRL_FIFO_RST_B
- PATA_IMX_ATA_CTRL_IORDY_EN
- PATA_IMX_ATA_INTR_ATA_INTRQ2
- PATA_IMX_ATA_INT_EN
- PATA_IMX_ATA_TIME_1
- PATA_IMX_ATA_TIME_2R
- PATA_IMX_ATA_TIME_2W
- PATA_IMX_ATA_TIME_4
- PATA_IMX_ATA_TIME_9
- PATA_IMX_ATA_TIME_AX
- PATA_IMX_ATA_TIME_OFF
- PATA_IMX_ATA_TIME_ON
- PATA_IMX_ATA_TIME_PIO_RDX
- PATA_IMX_DRIVE_CONTROL
- PATA_IMX_DRIVE_DATA
- PATA_PIO_TIMING
- PATA_UDMA_TIMING
- PATB_GR
- PATB_HR
- PATB_SIZE_SHIFT
- PATCH
- PATCHES
- PATCH_CASE
- PATCH_FOPS
- PATCH_INSN
- PATCH_IS_DL
- PATCH_MAX_SIZE
- PATCH_NOT_DL_SEM_FAIL
- PATCH_NOT_DL_SEM_SUCCESS
- PATCH_RAM_CLK
- PATCH_READY
- PATCH_REL_SEM_SUCCESS
- PATCH_REQUEST
- PATCH_RESET
- PATCH_SEM_GET
- PATCH_SEM_RELEASE
- PATEN_F
- PATEN_S
- PATEN_V
- PATFG
- PATH0
- PATH1_CTL1
- PATH1_EQ_CTL
- PATH1_SC_CTL
- PATH1_VOL_CTL
- PATH2_CTL1
- PATH2_EQ_CTL
- PATH2_SC_CTL
- PATH2_VOL_CTL
- PATHDIV_REG
- PATHDIV_T
- PATHDIV_TRI
- PATHLENGTH
- PATHS_ATTR
- PATH_ARR_SIZE
- PATH_BLOCKED
- PATH_BYTES
- PATH_CHROOT_NSCONNECT
- PATH_CHROOT_REL
- PATH_CONNECT_PATH
- PATH_DELEGATE_DELETED
- PATH_H_B_ITEM_ORDER
- PATH_H_PATH_OFFSET
- PATH_H_PBUFFER
- PATH_H_POSITION
- PATH_H_PPARENT
- PATH_ISO
- PATH_IS_DIR
- PATH_LAST_POSITION
- PATH_LEN_V1
- PATH_LEN_V2
- PATH_LEN_V3
- PATH_MAX
- PATH_MEDIATE_DELETED
- PATH_NET_TUN
- PATH_NUM
- PATH_OFFSET_PBUFFER
- PATH_OFFSET_PELEMENT
- PATH_OFFSET_POSITION
- PATH_OUT_DSI
- PATH_OUT_HDMI
- PATH_OUT_PARALLEL
- PATH_P2
- PATH_PLAST_BUFFER
- PATH_PN
- PATH_PRIM
- PATH_READA
- PATH_READA_BACK
- PATH_REC_FIELD
- PATH_S0
- PATH_S1
- PATH_THRU
- PATH_TO_CPU
- PATH_TV
- PATMONO
- PATPATREG
- PATREGSIZE
- PATTERN_COLOR_0
- PATTERN_COLOR_1
- PATTERN_COPY
- PATTERN_COUNT_MASK
- PATTERN_DETECTION
- PATTERN_DST
- PATTERN_FORMAT
- PATTERN_FORMAT_DEPTH16
- PATTERN_FORMAT_DEPTH24
- PATTERN_FORMAT_DEPTH8
- PATTERN_MEMSET_IDX
- PATTERN_OVERWRITE
- PATTERN_PATTERN_0
- PATTERN_PATTERN_1
- PATTERN_REG
- PATTERN_SRC
- PATTERN_TEST
- PAT_AHPA
- PAT_BASE_ADDR_REG
- PAT_BGCOLOR
- PAT_CLR_4x2_ENABLE
- PAT_CLR_8x1_ENABLE
- PAT_CNTL
- PAT_COLOR_MODE_REG
- PAT_COPY_ROP
- PAT_DESCR
- PAT_ENTITY_CA
- PAT_ENTITY_LBA
- PAT_ENTITY_MEM
- PAT_ENTITY_PBC
- PAT_ENTITY_PROC
- PAT_ENTITY_RC
- PAT_ENTITY_SBA
- PAT_ENTITY_XBC
- PAT_FGCOLOR
- PAT_GET_CBA
- PAT_GET_DVI
- PAT_GET_ENTITY
- PAT_GET_IOC
- PAT_GET_MOD_PAGES
- PAT_GMMIO
- PAT_GNIP
- PAT_IS_IN_COLOR
- PAT_IS_MONO
- PAT_LMMIO
- PAT_MAX_RANGES
- PAT_MEMORY_DESCRIPTOR
- PAT_MEMTYPE_FIRMWARE
- PAT_MEMTYPE_MEMORY
- PAT_MEMUSE_GENERAL
- PAT_MEMUSE_GI
- PAT_MEMUSE_GNI
- PAT_MONO_8x8_ENABLE
- PAT_NPIOP
- PAT_OFFSET_REG
- PAT_PBNUM
- PAT_PIOP
- PAT_PIPE
- PAT_REG0
- PAT_REG1
- PAT_ROP_GXCOPY
- PAT_ROP_GXXOR
- PAT_SEQ
- PAT_SIZE_REG
- PAT_STATUS
- PAT_STRIDE_REG
- PAT_UC
- PAT_UC_MINUS
- PAT_UFO
- PAT_VERT_ALIGN
- PAT_WB
- PAT_WC
- PAT_WP
- PAT_WT
- PAT_ZERO
- PAUSE
- PAUSED
- PAUSEDIS
- PAUSESTS_TX_PAUSE_SHIFT
- PAUSE_AUTONEG
- PAUSE_DELAY
- PAUSE_DONE
- PAUSE_FLOW_CTRL
- PAUSE_FRAME
- PAUSE_FRM_DEST_HI
- PAUSE_FRM_DEST_LO
- PAUSE_LEN
- PAUSE_LEN_CHG
- PAUSE_OFF
- PAUSE_ON
- PAUSE_OPCODE
- PAUSE_RESOLUTION_RX_SIDE
- PAUSE_RESOLUTION_TX_SIDE
- PAUSE_RX
- PAUSE_SHIFT
- PAUSE_SRC_HI
- PAUSE_SRC_LO
- PAUSE_STATE
- PAUSE_STREAM_NOTIFIED
- PAUSE_TIME
- PAUSE_TIMER
- PAUSE_TIMER_VALUE
- PAUSE_TIME_MASK
- PAUSE_TRIES
- PAUSE_TX
- PAUSE_XON_EN
- PAUTHENTICATE_MESSAGE
- PAXC_RESET_MASK
- PAXIC_ADBW_BW64
- PAXIC_MARID
- PAXIC_MARIDD
- PAXIC_MAWID
- PAXIC_MAWIDD
- PAXIC_OTL
- PAYLOAD
- PAYLOAD_AREA_SIZE
- PAYLOAD_ARG_CNT
- PAYLOAD_BODY
- PAYLOAD_HEADER
- PAYLOAD_LENGTH
- PAYLOAD_MAX
- PAYLOAD_OFFSET
- PAYLOAD_PRESENT
- PAYLOAD_SIZE
- PAYLOAD_TYPE_LEN
- PAY_START
- PA_83902
- PA_83902_IF
- PA_83902_RST
- PA_A
- PA_A16
- PA_A17
- PA_A18
- PA_A19
- PA_A20
- PA_A21
- PA_A22
- PA_A23
- PA_ACTIVERXDATALANES
- PA_ACTIVETXDATALANES
- PA_AREA0
- PA_AREA1
- PA_AREA2
- PA_AREA3
- PA_AREA4
- PA_AREA5
- PA_AREA5_IO
- PA_AREA6
- PA_AREA6_IO
- PA_AREA7
- PA_ASM_LEVEL
- PA_ATARST
- PA_AUDIOSEL
- PA_AVAILRXDATALANES
- PA_AVAILTXDATALANES
- PA_AX88796L
- PA_BASE
- PA_BCR
- PA_BIAS_CTRL
- PA_BIAS_HIGH_POWER
- PA_BIAS_LOW_POWER
- PA_BRIDGE_DBIAS
- PA_BUSY
- PA_BVERREG
- PA_CFCDINTCLR
- PA_CFCTL
- PA_CFPCR
- PA_CFPOW
- PA_CFTCR
- PA_CHANNEL_ATTENTION
- PA_CLR_TO_RX1
- PA_CLR_TO_RX2
- PA_CLR_TO_TX1
- PA_CLR_TO_TX2
- PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK
- PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT
- PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK
- PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT
- PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK
- PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT
- PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK
- PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT
- PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK
- PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT
- PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK
- PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT
- PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK
- PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT
- PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK
- PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT
- PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK
- PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_0_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_1_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_2_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_3_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_4_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT
- PA_CL_CLIP_CNTL__UCP_ENA_5_MASK
- PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT
- PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK
- PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT
- PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK
- PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT
- PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK
- PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT
- PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK
- PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT
- PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK
- PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT
- PA_CL_CNTL_STATUS__CL_BUSY_MASK
- PA_CL_CNTL_STATUS__CL_BUSY__SHIFT
- PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK
- PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT
- PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK
- PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT
- PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK
- PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT
- PA_CL_ENHANCE
- PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK
- PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT
- PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK
- PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT
- PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK
- PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT
- PA_CL_ENHANCE__ECO_SPARE0_MASK
- PA_CL_ENHANCE__ECO_SPARE0__SHIFT
- PA_CL_ENHANCE__ECO_SPARE1_MASK
- PA_CL_ENHANCE__ECO_SPARE1__SHIFT
- PA_CL_ENHANCE__ECO_SPARE2_MASK
- PA_CL_ENHANCE__ECO_SPARE2__SHIFT
- PA_CL_ENHANCE__ECO_SPARE3_MASK
- PA_CL_ENHANCE__ECO_SPARE3__SHIFT
- PA_CL_ENHANCE__EN_32BIT_OBJPRIMID_MASK
- PA_CL_ENHANCE__EN_32BIT_OBJPRIMID__SHIFT
- PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK
- PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT
- PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK
- PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT
- PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK
- PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT
- PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK
- PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT
- PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK
- PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT
- PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK
- PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT
- PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK
- PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT
- PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK
- PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT
- PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK
- PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT
- PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK
- PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT
- PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK
- PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT
- PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK
- PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT
- PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK
- PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT
- PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK
- PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT
- PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK
- PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT
- PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK
- PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT
- PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK
- PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT
- PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK
- PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT
- PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK
- PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT
- PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK
- PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT
- PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK
- PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT
- PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK
- PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT
- PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK
- PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT
- PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK
- PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT
- PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK
- PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT
- PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK
- PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT
- PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK
- PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT
- PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK
- PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT
- PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK
- PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT
- PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK
- PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT
- PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK
- PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT
- PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK
- PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT
- PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK
- PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT
- PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK
- PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT
- PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK
- PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT
- PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK
- PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT
- PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK
- PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT
- PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK
- PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT
- PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK
- PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT
- PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK
- PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT
- PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK
- PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT
- PA_CL_POINT_SIZE__DATA_REGISTER_MASK
- PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT
- PA_CL_POINT_X_RAD__DATA_REGISTER_MASK
- PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT
- PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK
- PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT
- PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK
- PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT
- PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK
- PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT
- PA_CL_UCP_0_W__DATA_REGISTER_MASK
- PA_CL_UCP_0_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_0_X__DATA_REGISTER_MASK
- PA_CL_UCP_0_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_0_Y__DATA_REGISTER_MASK
- PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_0_Z__DATA_REGISTER_MASK
- PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT
- PA_CL_UCP_1_W__DATA_REGISTER_MASK
- PA_CL_UCP_1_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_1_X__DATA_REGISTER_MASK
- PA_CL_UCP_1_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_1_Y__DATA_REGISTER_MASK
- PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_1_Z__DATA_REGISTER_MASK
- PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT
- PA_CL_UCP_2_W__DATA_REGISTER_MASK
- PA_CL_UCP_2_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_2_X__DATA_REGISTER_MASK
- PA_CL_UCP_2_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_2_Y__DATA_REGISTER_MASK
- PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_2_Z__DATA_REGISTER_MASK
- PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT
- PA_CL_UCP_3_W__DATA_REGISTER_MASK
- PA_CL_UCP_3_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_3_X__DATA_REGISTER_MASK
- PA_CL_UCP_3_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_3_Y__DATA_REGISTER_MASK
- PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_3_Z__DATA_REGISTER_MASK
- PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT
- PA_CL_UCP_4_W__DATA_REGISTER_MASK
- PA_CL_UCP_4_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_4_X__DATA_REGISTER_MASK
- PA_CL_UCP_4_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_4_Y__DATA_REGISTER_MASK
- PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_4_Z__DATA_REGISTER_MASK
- PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT
- PA_CL_UCP_5_W__DATA_REGISTER_MASK
- PA_CL_UCP_5_W__DATA_REGISTER__SHIFT
- PA_CL_UCP_5_X__DATA_REGISTER_MASK
- PA_CL_UCP_5_X__DATA_REGISTER__SHIFT
- PA_CL_UCP_5_Y__DATA_REGISTER_MASK
- PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT
- PA_CL_UCP_5_Z__DATA_REGISTER_MASK
- PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT
- PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK
- PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT
- PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK
- PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT
- PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK
- PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT
- PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK
- PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT
- PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK
- PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT
- PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT
- PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK
- PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK
- PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK
- PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT
- PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK
- PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT
- PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK
- PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT
- PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK
- PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT
- PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK
- PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT
- PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK
- PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT
- PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK
- PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT
- PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT
- PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT
- PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT
- PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT
- PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT
- PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK
- PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT
- PA_CL_VTE_CNTL__VTX_W0_FMT_MASK
- PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT
- PA_CL_VTE_CNTL__VTX_XY_FMT_MASK
- PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT
- PA_CL_VTE_CNTL__VTX_Z_FMT_MASK
- PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT
- PA_CONNECTEDRXDATALANES
- PA_CONNECTEDTXDATALANES
- PA_CONTROL_PAGE
- PA_CPLD_BASE_ADDR
- PA_CPLD_IMSK_REG
- PA_CPLD_ST_REG
- PA_CPU_PORT_L_ACCESS
- PA_CS2
- PA_CS3
- PA_CS4
- PA_CS5
- PA_CTRL
- PA_CTRL_APAGAIN
- PA_CTRL_APALP
- PA_CTRL_APAON
- PA_CTRL_APAPRECH
- PA_CU3MDR
- PA_CU5MDR
- PA_DBDET
- PA_DBDISPCTL
- PA_DBIAS_HIGH_POWER
- PA_DBIAS_LOW_POWER
- PA_DBSW
- PA_DIPSW
- PA_DIPSW0
- PA_DIPSW1
- PA_DISPCTL
- PA_DIS_TO_RX1
- PA_DIS_TO_RX2
- PA_DIS_TO_TX1
- PA_DIS_TO_TX2
- PA_ENA_TO_ALL
- PA_ENA_TO_RX1
- PA_ENA_TO_RX2
- PA_ENA_TO_TX1
- PA_ENA_TO_TX2
- PA_EXIRLCR
- PA_EXT1
- PA_EXT1_SIZE
- PA_EXT2
- PA_EXT2_SIZE
- PA_EXT4
- PA_EXT4_SIZE
- PA_EXT5
- PA_EXT5_SIZE
- PA_EXTGIO
- PA_EXTPLR
- PA_EXT_FLASH
- PA_EXT_USER
- PA_FPGA
- PA_FROM
- PA_FROM_SIZE
- PA_GPIODR
- PA_GPIOPFR
- PA_GRANULARITY
- PA_GRANULARITY_MAX_VAL
- PA_GRANULARITY_MIN_VAL
- PA_HASH_ORDER
- PA_HIBERN8TIME
- PA_HIBERN8_TIME_UNIT_US
- PA_HSSERIES
- PA_HS_MODE_A
- PA_HS_MODE_B
- PA_HVERSION_ANY_ID
- PA_HVERSION_REV_ANY_ID
- PA_HWTYPE_ANY_ID
- PA_I82596_RESET
- PA_IDE_OFFSET
- PA_IMASK
- PA_INPORT
- PA_IRLMCR1
- PA_IRLMCR2
- PA_IRLMON
- PA_IRLMSK
- PA_IRLPRA
- PA_IRLPRB
- PA_IRLPRC
- PA_IRLPRD
- PA_IRLPRE
- PA_IRLPRF
- PA_IRLPRI1
- PA_IRLPRI2
- PA_IRLPRI3
- PA_IRLPRI4
- PA_IRLSSR1
- PA_IRLSSR2
- PA_IVDRCTL
- PA_IVDRMON
- PA_IVDRSR
- PA_LAN
- PA_LCD1
- PA_LCD2
- PA_LCDCR
- PA_LED
- PA_LED_DISP
- PA_LEGACYDPHYESCDL
- PA_LOCALVERINFO
- PA_LOCAL_TX_LCC_ENABLE
- PA_LOGICALLANEMAP
- PA_LOWER_BITS
- PA_LOWER_BITS_SHIFT
- PA_MAXDATALANES
- PA_MAXRXHSGEAR
- PA_MAXRXPWMGEAR
- PA_MAXRXSPEEDFAST
- PA_MAXRXSPEEDSLOW
- PA_MAXTXSPEEDFAST
- PA_MAXTXSPEEDSLOW
- PA_MINRXTRAILINGCLOCKS
- PA_MMSR
- PA_MRSHPC
- PA_MRSHPC_IO
- PA_MRSHPC_MW1
- PA_MRSHPC_MW2
- PA_NORFLASH_ADDR
- PA_NORFLASH_SIZE
- PA_OBLED
- PA_OBSW
- PA_OUTPORT
- PA_PACPERRORCOUNT
- PA_PACPFRAMECOUNT
- PA_PACPREQEOBTIMEOUT
- PA_PACPREQTIMEOUT
- PA_PCIBD
- PA_PCIC
- PA_PCICD
- PA_PCICR
- PA_PCIPME
- PA_PCISCR
- PA_PCI_IO
- PA_PCI_MEM
- PA_PDRSTCR
- PA_PERF_DEV
- PA_PERF_MINOR
- PA_PERF_OFF
- PA_PERF_ON
- PA_PERF_VERSION
- PA_PERIPHERAL
- PA_PGD
- PA_PHYTESTCONTROL
- PA_PHY_TYPE
- PA_PH_ENHANCE__DISABLE_FOPKT_MASK
- PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK
- PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT
- PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT
- PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK
- PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT
- PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK
- PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT
- PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK
- PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT
- PA_PH_ENHANCE__ECO_SPARE0_MASK
- PA_PH_ENHANCE__ECO_SPARE0__SHIFT
- PA_PH_ENHANCE__ECO_SPARE1_MASK
- PA_PH_ENHANCE__ECO_SPARE1__SHIFT
- PA_PH_ENHANCE__ECO_SPARE2_MASK
- PA_PH_ENHANCE__ECO_SPARE2__SHIFT
- PA_PH_ENHANCE__ECO_SPARE3_MASK
- PA_PH_ENHANCE__ECO_SPARE3__SHIFT
- PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK
- PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT
- PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK
- PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT
- PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK
- PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT
- PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
- PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
- PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
- PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
- PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
- PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
- PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
- PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
- PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK
- PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT
- PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK
- PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT
- PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK
- PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT
- PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK
- PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT
- PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK
- PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT
- PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK
- PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT
- PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT
- PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK
- PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT
- PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK
- PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT
- PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK
- PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT
- PA_PIDE_OFFSET
- PA_PLABEL_FDESC
- PA_PMR
- PA_POFF
- PA_POWOFF
- PA_PWR
- PA_PWRINT_CLR
- PA_PWRMODE
- PA_PWRMODEUSERDATA0
- PA_PWRMODEUSERDATA1
- PA_PWRMODEUSERDATA10
- PA_PWRMODEUSERDATA11
- PA_PWRMODEUSERDATA2
- PA_PWRMODEUSERDATA3
- PA_PWRMODEUSERDATA4
- PA_PWRMODEUSERDATA5
- PA_PWRMODEUSERDATA6
- PA_PWRMODEUSERDATA7
- PA_PWRMODEUSERDATA8
- PA_PWRMODEUSERDATA9
- PA_PXP_CFA
- PA_R2D1_ADMRTS
- PA_R2D1_AXRST
- PA_R2D1_CFCDINTCLR
- PA_R2D1_CFRST
- PA_R2D1_EXTRST
- PA_R2DPLUS_ADMRTS
- PA_R2DPLUS_CFCDINTCLR
- PA_R2DPLUS_CFRST
- PA_R2DPLUS_EXTRST
- PA_R2DPLUS_KEYCTLCLR
- PA_REMOTEVERINFO
- PA_RESERVED
- PA_ROM
- PA_ROM_SIZE
- PA_RSTCTL
- PA_RST_CLR
- PA_RST_SET
- PA_RTCCE
- PA_RXGEAR
- PA_RXHSUNTERMCAP
- PA_RXLSTERMCAP
- PA_RXPWRSTATUS
- PA_RXTERMINATION
- PA_SAVECONFIGTIME
- PA_SC1602BSLB
- PA_SCBRR
- PA_SCBRR0
- PA_SCBRR1
- PA_SCFCR
- PA_SCFCR0
- PA_SCFCR1
- PA_SCFDR
- PA_SCFDTR
- PA_SCFRDR
- PA_SCFRDR0
- PA_SCFRDR1
- PA_SCFSR
- PA_SCFSR0
- PA_SCFSR1
- PA_SCFTDR0
- PA_SCFTDR1
- PA_SCLSR
- PA_SCLSR0
- PA_SCLSR1
- PA_SCRER0
- PA_SCRER1
- PA_SCRFDR0
- PA_SCRFDR1
- PA_SCSCR
- PA_SCSCR0
- PA_SCSCR1
- PA_SCSMR
- PA_SCSMR0
- PA_SCSMR1
- PA_SCSPTR0
- PA_SCSPTR1
- PA_SCTFDR0
- PA_SCTFDR1
- PA_SC_AA_CONFIG
- PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK
- PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT
- PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK
- PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT
- PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK
- PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT
- PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK
- PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT
- PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK
- PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT
- PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK
- PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT
- PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK
- PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT
- PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK
- PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT
- PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK
- PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT
- PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK
- PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT
- PA_SC_AA_SAMPLE_LOCS_2S
- PA_SC_AA_SAMPLE_LOCS_4S
- PA_SC_AA_SAMPLE_LOCS_8S_WD0
- PA_SC_AA_SAMPLE_LOCS_8S_WD1
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK
- PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT
- PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK
- PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT
- PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK
- PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT
- PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK
- PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT
- PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK
- PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT
- PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK
- PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT
- PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK
- PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT
- PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK
- PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT
- PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK
- PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT
- PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK
- PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT
- PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK
- PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT
- PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK
- PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT
- PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK
- PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT
- PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK
- PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT
- PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK
- PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT
- PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK
- PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT
- PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK
- PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT
- PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK
- PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK
- PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK
- PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK
- PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK
- PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK
- PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK
- PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK
- PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK
- PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK
- PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK
- PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT
- PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK
- PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK
- PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK
- PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK
- PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK
- PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK
- PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK
- PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK
- PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK
- PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK
- PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK
- PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK
- PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT
- PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK
- PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK
- PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK
- PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK
- PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK
- PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK
- PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK
- PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK
- PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK
- PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK
- PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK
- PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT
- PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT
- PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK
- PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT
- PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK
- PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK
- PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK
- PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT
- PA_SC_CLIPRECT_0_BR__BR_X_MASK
- PA_SC_CLIPRECT_0_BR__BR_X__SHIFT
- PA_SC_CLIPRECT_0_BR__BR_Y_MASK
- PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT
- PA_SC_CLIPRECT_0_TL__TL_X_MASK
- PA_SC_CLIPRECT_0_TL__TL_X__SHIFT
- PA_SC_CLIPRECT_0_TL__TL_Y_MASK
- PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT
- PA_SC_CLIPRECT_1_BR__BR_X_MASK
- PA_SC_CLIPRECT_1_BR__BR_X__SHIFT
- PA_SC_CLIPRECT_1_BR__BR_Y_MASK
- PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT
- PA_SC_CLIPRECT_1_TL__TL_X_MASK
- PA_SC_CLIPRECT_1_TL__TL_X__SHIFT
- PA_SC_CLIPRECT_1_TL__TL_Y_MASK
- PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT
- PA_SC_CLIPRECT_2_BR__BR_X_MASK
- PA_SC_CLIPRECT_2_BR__BR_X__SHIFT
- PA_SC_CLIPRECT_2_BR__BR_Y_MASK
- PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT
- PA_SC_CLIPRECT_2_TL__TL_X_MASK
- PA_SC_CLIPRECT_2_TL__TL_X__SHIFT
- PA_SC_CLIPRECT_2_TL__TL_Y_MASK
- PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT
- PA_SC_CLIPRECT_3_BR__BR_X_MASK
- PA_SC_CLIPRECT_3_BR__BR_X__SHIFT
- PA_SC_CLIPRECT_3_BR__BR_Y_MASK
- PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT
- PA_SC_CLIPRECT_3_TL__TL_X_MASK
- PA_SC_CLIPRECT_3_TL__TL_X__SHIFT
- PA_SC_CLIPRECT_3_TL__TL_Y_MASK
- PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT
- PA_SC_CLIPRECT_RULE
- PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK
- PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK
- PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT
- PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK
- PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT
- PA_SC_DEBUG_DATA__DATA_MASK
- PA_SC_DEBUG_DATA__DATA__SHIFT
- PA_SC_DEBUG_REG0__REG0_FIELD0_MASK
- PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT
- PA_SC_DEBUG_REG0__REG0_FIELD1_MASK
- PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT
- PA_SC_DEBUG_REG1__REG1_FIELD0_MASK
- PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT
- PA_SC_DEBUG_REG1__REG1_FIELD1_MASK
- PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT
- PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK
- PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT
- PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK
- PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT
- PA_SC_EDGERULE
- PA_SC_EDGERULE__ER_LINE_BT_MASK
- PA_SC_EDGERULE__ER_LINE_BT__SHIFT
- PA_SC_EDGERULE__ER_LINE_LR_MASK
- PA_SC_EDGERULE__ER_LINE_LR__SHIFT
- PA_SC_EDGERULE__ER_LINE_RL_MASK
- PA_SC_EDGERULE__ER_LINE_RL__SHIFT
- PA_SC_EDGERULE__ER_LINE_TB_MASK
- PA_SC_EDGERULE__ER_LINE_TB__SHIFT
- PA_SC_EDGERULE__ER_POINT_MASK
- PA_SC_EDGERULE__ER_POINT__SHIFT
- PA_SC_EDGERULE__ER_RECT_MASK
- PA_SC_EDGERULE__ER_RECT__SHIFT
- PA_SC_EDGERULE__ER_TRI_MASK
- PA_SC_EDGERULE__ER_TRI__SHIFT
- PA_SC_ENHANCE
- PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK
- PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT
- PA_SC_ENHANCE_1__BYPASS_PBB_MASK
- PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT
- PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK
- PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT
- PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK
- PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT
- PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK
- PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK
- PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK
- PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK
- PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK
- PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK
- PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT
- PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK
- PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT
- PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK
- PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK
- PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT
- PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK
- PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT
- PA_SC_ENHANCE_1__ECO_SPARE0_MASK
- PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT
- PA_SC_ENHANCE_1__ECO_SPARE1_MASK
- PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT
- PA_SC_ENHANCE_1__ECO_SPARE2_MASK
- PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT
- PA_SC_ENHANCE_1__ECO_SPARE3_MASK
- PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT
- PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK
- PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT
- PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK
- PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT
- PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK
- PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT
- PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK
- PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT
- PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK
- PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT
- PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK
- PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT
- PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK
- PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT
- PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK
- PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT
- PA_SC_ENHANCE_1__RSVD_MASK
- PA_SC_ENHANCE_1__RSVD__SHIFT
- PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK
- PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT
- PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK
- PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT
- PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK
- PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT
- PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK
- PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT
- PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK
- PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT
- PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK
- PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT
- PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK
- PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT
- PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK
- PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT
- PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK
- PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT
- PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK
- PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT
- PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK
- PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT
- PA_SC_ENHANCE_2__ECO_SPARE0_MASK
- PA_SC_ENHANCE_2__ECO_SPARE0__SHIFT
- PA_SC_ENHANCE_2__ECO_SPARE1_MASK
- PA_SC_ENHANCE_2__ECO_SPARE1__SHIFT
- PA_SC_ENHANCE_2__ECO_SPARE2_MASK
- PA_SC_ENHANCE_2__ECO_SPARE2__SHIFT
- PA_SC_ENHANCE_2__ECO_SPARE3_MASK
- PA_SC_ENHANCE_2__ECO_SPARE3__SHIFT
- PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK
- PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT
- PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK
- PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT
- PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK
- PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT
- PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK
- PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID_MASK
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID__SHIFT
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK
- PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT
- PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK
- PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT
- PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK
- PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT
- PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK
- PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT
- PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK
- PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT
- PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK
- PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT
- PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK
- PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT
- PA_SC_ENHANCE_2__RESERVED_0_MASK
- PA_SC_ENHANCE_2__RESERVED_0__SHIFT
- PA_SC_ENHANCE_2__RESERVED_1_MASK
- PA_SC_ENHANCE_2__RESERVED_1__SHIFT
- PA_SC_ENHANCE_2__RESERVED_2_MASK
- PA_SC_ENHANCE_2__RESERVED_2__SHIFT
- PA_SC_ENHANCE_2__RESERVED_3_MASK
- PA_SC_ENHANCE_2__RESERVED_3__SHIFT
- PA_SC_ENHANCE_2__RESERVED_4_MASK
- PA_SC_ENHANCE_2__RESERVED_4__SHIFT
- PA_SC_ENHANCE_2__RESERVED_5_MASK
- PA_SC_ENHANCE_2__RESERVED_5__SHIFT
- PA_SC_ENHANCE_2__RSVD_MASK
- PA_SC_ENHANCE_2__RSVD__SHIFT
- PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK
- PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT
- PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK
- PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT
- PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK
- PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT
- PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK
- PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT
- PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK
- PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT
- PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK
- PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK
- PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT
- PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK
- PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT
- PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK
- PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT
- PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK
- PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT
- PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK
- PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK
- PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT
- PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK
- PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT
- PA_SC_ENHANCE__ECO_SPARE0_MASK
- PA_SC_ENHANCE__ECO_SPARE0__SHIFT
- PA_SC_ENHANCE__ECO_SPARE1_MASK
- PA_SC_ENHANCE__ECO_SPARE1__SHIFT
- PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK
- PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT
- PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK
- PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT
- PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK
- PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK
- PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT
- PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK
- PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT
- PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK
- PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT
- PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK
- PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT
- PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK
- PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT
- PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK
- PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT
- PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK
- PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT
- PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK
- PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT
- PA_SC_FIFO_SIZE
- PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK
- PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT
- PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK
- PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT
- PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK
- PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT
- PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK
- PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT
- PA_SC_FORCE_EOV_MAX_CNTS
- PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK
- PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT
- PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK
- PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT
- PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK
- PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT
- PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK
- PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT
- PA_SC_GENERIC_SCISSOR_TL
- PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK
- PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT
- PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK
- PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT
- PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_HORIZ_GRID__BOT_HALF_MASK
- PA_SC_HORIZ_GRID__BOT_HALF__SHIFT
- PA_SC_HORIZ_GRID__BOT_QTR_MASK
- PA_SC_HORIZ_GRID__BOT_QTR__SHIFT
- PA_SC_HORIZ_GRID__TOP_HALF_MASK
- PA_SC_HORIZ_GRID__TOP_HALF__SHIFT
- PA_SC_HORIZ_GRID__TOP_QTR_MASK
- PA_SC_HORIZ_GRID__TOP_QTR__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK
- PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK
- PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK
- PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK
- PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK
- PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK
- PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT
- PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK
- PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT
- PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK
- PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT
- PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK
- PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT
- PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK
- PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT
- PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK
- PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT
- PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK
- PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT
- PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK
- PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT
- PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK
- PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT
- PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK
- PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT
- PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK
- PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT
- PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK
- PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT
- PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK
- PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT
- PA_SC_LINE_CNTL__LAST_PIXEL_MASK
- PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT
- PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK
- PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT
- PA_SC_LINE_STIPPLE
- PA_SC_LINE_STIPPLE_STATE
- PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK
- PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT
- PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK
- PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT
- PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK
- PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT
- PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK
- PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT
- PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK
- PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT
- PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK
- PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT
- PA_SC_MODE_CNTL
- PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK
- PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT
- PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK
- PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT
- PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK
- PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT
- PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK
- PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT
- PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK
- PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT
- PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK
- PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT
- PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK
- PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK
- PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK
- PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK
- PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK
- PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT
- PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK
- PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT
- PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK
- PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT
- PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK
- PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK
- PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK
- PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK
- PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK
- PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT
- PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK
- PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT
- PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK
- PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK
- PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT
- PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK
- PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT
- PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK
- PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK
- PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT
- PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK
- PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT
- PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK
- PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT
- PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK
- PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT
- PA_SC_MODE_CNTL_1__WALK_SIZE_MASK
- PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT
- PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK
- PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT
- PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK
- PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT
- PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK
- PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT
- PA_SC_MULTI_CHIP_CNTL
- PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK
- PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT
- PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK
- PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT
- PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK
- PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT
- PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK
- PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT
- PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK
- PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT
- PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK
- PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT
- PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK
- PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT
- PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK
- PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT
- PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK
- PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT
- PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK
- PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT
- PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK
- PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT
- PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT
- PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK
- PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT
- PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK
- PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT
- PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK
- PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT
- PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK
- PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT
- PA_SC_RASTER_CONFIG
- PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK
- PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT
- PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK
- PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT
- PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK
- PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT
- PA_SC_RASTER_CONFIG__PKR_MAP_MASK
- PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT
- PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK
- PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT
- PA_SC_RASTER_CONFIG__PKR_XSEL_MASK
- PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT
- PA_SC_RASTER_CONFIG__PKR_YSEL_MASK
- PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT
- PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK
- PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT
- PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK
- PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT
- PA_SC_RASTER_CONFIG__RB_XSEL2_MASK
- PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT
- PA_SC_RASTER_CONFIG__RB_XSEL_MASK
- PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT
- PA_SC_RASTER_CONFIG__RB_YSEL_MASK
- PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT
- PA_SC_RASTER_CONFIG__SC_MAP_MASK
- PA_SC_RASTER_CONFIG__SC_MAP__SHIFT
- PA_SC_RASTER_CONFIG__SC_XSEL_MASK
- PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT
- PA_SC_RASTER_CONFIG__SC_YSEL_MASK
- PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT
- PA_SC_RASTER_CONFIG__SE_MAP_MASK
- PA_SC_RASTER_CONFIG__SE_MAP__SHIFT
- PA_SC_RASTER_CONFIG__SE_XSEL_MASK
- PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT
- PA_SC_RASTER_CONFIG__SE_YSEL_MASK
- PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT
- PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK
- PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT
- PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK
- PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT
- PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK
- PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT
- PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK
- PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT
- PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK
- PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT
- PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK
- PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT
- PA_SC_SCREEN_EXTENT_MAX_0__X_MASK
- PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT
- PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK
- PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT
- PA_SC_SCREEN_EXTENT_MAX_1__X_MASK
- PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT
- PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK
- PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT
- PA_SC_SCREEN_EXTENT_MIN_0__X_MASK
- PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT
- PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK
- PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT
- PA_SC_SCREEN_EXTENT_MIN_1__X_MASK
- PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT
- PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK
- PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT
- PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK
- PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT
- PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK
- PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT
- PA_SC_SCREEN_SCISSOR_TL
- PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK
- PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT
- PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK
- PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT
- PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK
- PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT
- PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK
- PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT
- PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK
- PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT
- PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK
- PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT
- PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK
- PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT
- PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK
- PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT
- PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK
- PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT
- PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK
- PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT
- PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK
- PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK
- PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK
- PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK
- PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK
- PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK
- PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK
- PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT
- PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK
- PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT
- PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK
- PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT
- PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK
- PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT
- PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK
- PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT
- PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK
- PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT
- PA_SC_TRAP_SCREEN_H__X_COORD_MASK
- PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT
- PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK
- PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT
- PA_SC_TRAP_SCREEN_V__Y_COORD_MASK
- PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT
- PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK
- PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT
- PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK
- PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT
- PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK
- PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT
- PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK
- PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT
- PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK
- PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT
- PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT
- PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK
- PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT
- PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK
- PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT
- PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK
- PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT
- PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK
- PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT
- PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK
- PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT
- PA_SC_WINDOW_SCISSOR_TL
- PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK
- PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT
- PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK
- PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT
- PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK
- PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT
- PA_SDMPOW
- PA_SDPOW
- PA_SDRAM
- PA_SDRAM_SIZE
- PA_SECTION_SHIFT
- PA_SHUTDOWN
- PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK
- PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT
- PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK
- PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT
- PA_SIDE_OFFSET
- PA_SLEEPNOCONFIGTIME
- PA_SM501
- PA_SM501_SIZE
- PA_SMCR
- PA_SMMR
- PA_SMSADR1
- PA_SMSADR32
- PA_SMSC
- PA_SMSMADR
- PA_SMTRDR1
- PA_SMTRDR16
- PA_SRAM
- PA_STALLNOCONFIGTIME
- PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK
- PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT
- PA_STATUS
- PA_STEREO_CNTL__EN_STEREO_MASK
- PA_STEREO_CNTL__EN_STEREO__SHIFT
- PA_STEREO_CNTL__RT_SLICE_MODE_MASK
- PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT
- PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK
- PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT
- PA_STEREO_CNTL__STEREO_MODE_MASK
- PA_STEREO_CNTL__STEREO_MODE__SHIFT
- PA_STEREO_CNTL__VP_ID_MODE_MASK
- PA_STEREO_CNTL__VP_ID_MODE__SHIFT
- PA_STEREO_CNTL__VP_ID_OFFSET_MASK
- PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT
- PA_SUPERIO
- PA_SU_CNTL_STATUS__SU_BUSY_MASK
- PA_SU_CNTL_STATUS__SU_BUSY__SHIFT
- PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK
- PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT
- PA_SU_DEBUG_DATA__DATA_MASK
- PA_SU_DEBUG_DATA__DATA__SHIFT
- PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK
- PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT
- PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK
- PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT
- PA_SU_LINE_CNTL__WIDTH_MASK
- PA_SU_LINE_CNTL__WIDTH__SHIFT
- PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK
- PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT
- PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK
- PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT
- PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK
- PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT
- PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK
- PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT
- PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK
- PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT
- PA_SU_LINE_STIPPLE_VALUE
- PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK
- PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK
- PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT
- PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK
- PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT
- PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
- PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
- PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
- PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
- PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
- PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
- PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
- PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
- PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK
- PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT
- PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK
- PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT
- PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK
- PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT
- PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK
- PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT
- PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK
- PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT
- PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK
- PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT
- PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- PA_SU_POINT_MINMAX__MAX_SIZE_MASK
- PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT
- PA_SU_POINT_MINMAX__MIN_SIZE_MASK
- PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT
- PA_SU_POINT_SIZE__HEIGHT_MASK
- PA_SU_POINT_SIZE__HEIGHT__SHIFT
- PA_SU_POINT_SIZE__WIDTH_MASK
- PA_SU_POINT_SIZE__WIDTH__SHIFT
- PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK
- PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT
- PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK
- PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT
- PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK
- PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT
- PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK
- PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT
- PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK
- PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT
- PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK
- PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT
- PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK
- PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT
- PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK
- PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT
- PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK
- PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT
- PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK
- PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT
- PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK
- PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT
- PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK
- PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT
- PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK
- PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT
- PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK
- PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT
- PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK
- PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT
- PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK
- PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT
- PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK
- PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT
- PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK
- PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT
- PA_SU_SC_MODE_CNTL__CULL_BACK_MASK
- PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT
- PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK
- PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT
- PA_SU_SC_MODE_CNTL__FACE_MASK
- PA_SU_SC_MODE_CNTL__FACE__SHIFT
- PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK
- PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT
- PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK
- PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT
- PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK
- PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT
- PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK
- PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT
- PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK
- PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT
- PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK
- PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT
- PA_SU_SC_MODE_CNTL__POLY_MODE_MASK
- PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK
- PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT
- PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK
- PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT
- PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK
- PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT
- PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK
- PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT
- PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK
- PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT
- PA_SU_VTX_CNTL__PIX_CENTER_MASK
- PA_SU_VTX_CNTL__PIX_CENTER__SHIFT
- PA_SU_VTX_CNTL__QUANT_MODE_MASK
- PA_SU_VTX_CNTL__QUANT_MODE__SHIFT
- PA_SU_VTX_CNTL__ROUND_MODE_MASK
- PA_SU_VTX_CNTL__ROUND_MODE__SHIFT
- PA_SVERSION_ANY_ID
- PA_SWAP_PAGE
- PA_SWSR
- PA_TABLE_PAGE
- PA_TACTIVATE
- PA_TACTIVATE_TIME_UNIT_US
- PA_TPCKCR
- PA_TPCR
- PA_TPCTL
- PA_TPCTLCLR
- PA_TPDCKCTL
- PA_TPRSTR
- PA_TPXPDR
- PA_TPXPOS
- PA_TPYPDR
- PA_TPYPOS
- PA_TXFORCECLOCK
- PA_TXGEAR
- PA_TXLINKSTARTUPHS
- PA_TXPWRMODE
- PA_TXPWRSTATUS
- PA_TXSPEEDFAST
- PA_TXSPEEDSLOW
- PA_TXTERMINATION
- PA_TXTRAILINGCLOCKS
- PA_UPPER_BITS
- PA_UPPER_BITS_SHIFT
- PA_USB
- PA_UTCL1_CNTL1__CLIENTID_MASK
- PA_UTCL1_CNTL1__CLIENTID__SHIFT
- PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK
- PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT
- PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK
- PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT
- PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK
- PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT
- PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK
- PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT
- PA_UTCL1_CNTL1__FORCE_MISS_MASK
- PA_UTCL1_CNTL1__FORCE_MISS__SHIFT
- PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK
- PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT
- PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK
- PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT
- PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK
- PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT
- PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK
- PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT
- PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK
- PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT
- PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK
- PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT
- PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK
- PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT
- PA_UTCL1_CNTL1__REG_INV_VMID_MASK
- PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT
- PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK
- PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT
- PA_UTCL1_CNTL1__RESP_MODE_MASK
- PA_UTCL1_CNTL1__RESP_MODE__SHIFT
- PA_UTCL1_CNTL1__SPARE_MASK
- PA_UTCL1_CNTL1__SPARE__SHIFT
- PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK
- PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT
- PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK
- PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT
- PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK
- PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT
- PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK
- PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT
- PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK
- PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT
- PA_UTCL1_CNTL2__FORCE_SNOOP_MASK
- PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT
- PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK
- PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT
- PA_UTCL1_CNTL2__LINE_VALID_MASK
- PA_UTCL1_CNTL2__LINE_VALID__SHIFT
- PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK
- PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT
- PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK
- PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT
- PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK
- PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT
- PA_UTCL1_CNTL2__RESERVED_MASK
- PA_UTCL1_CNTL2__RESERVED__SHIFT
- PA_UTCL1_CNTL2__SPARE1_MASK
- PA_UTCL1_CNTL2__SPARE1__SHIFT
- PA_UTCL1_CNTL2__SPARE2_MASK
- PA_UTCL1_CNTL2__SPARE2__SHIFT
- PA_UTCL1_CNTL2__SPARE3_MASK
- PA_UTCL1_CNTL2__SPARE3__SHIFT
- PA_UTCL1_CNTL2__SPARE4_MASK
- PA_UTCL1_CNTL2__SPARE4__SHIFT
- PA_UTCL1_CNTL2__SPARE5_MASK
- PA_UTCL1_CNTL2__SPARE5__SHIFT
- PA_VERREG
- PA_VIEW
- PA_VOYAGER
- PA_VOYAGERRTS
- PA_VS_CONFIG_REG1
- PA_XHFC_A0
- PA_ZIGIO1
- PA_ZIGIO2
- PA_ZIGIO3
- PA_ZIGIO4
- PB
- PB0
- PB0100_CROP_TO_VGA
- PB0100_SUBSAMPLE
- PB0MD_00
- PB0MD_01
- PB0MD_10
- PB0MD_11
- PB0_DATA
- PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK
- PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT
- PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK
- PB0_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT
- PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK
- PB0_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT
- PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK
- PB0_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT
- PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK
- PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT
- PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK
- PB0_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT
- PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK
- PB0_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT
- PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK
- PB0_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT
- PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK
- PB0_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK
- PB0_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT
- PB0_FN
- PB0_GLB_CTRL_REG0__BACKUP_MASK
- PB0_GLB_CTRL_REG0__BACKUP__SHIFT
- PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK
- PB0_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT
- PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK
- PB0_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT
- PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK
- PB0_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT
- PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK
- PB0_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT
- PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK
- PB0_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT
- PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK
- PB0_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT
- PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK
- PB0_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT
- PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK
- PB0_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK
- PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK
- PB0_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK
- PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK
- PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK
- PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK
- PB0_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK
- PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK
- PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK
- PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK
- PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK
- PB0_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK
- PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT
- PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK
- PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT
- PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK
- PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT
- PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK
- PB0_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT
- PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK
- PB0_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT
- PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK
- PB0_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT
- PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK
- PB0_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT
- PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK
- PB0_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT
- PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK
- PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK
- PB0_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK
- PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK
- PB0_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK
- PB0_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT
- PB0_GLB_CTRL_REG3__RXDBG_SEL_MASK
- PB0_GLB_CTRL_REG3__RXDBG_SEL__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK
- PB0_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK
- PB0_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK
- PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK
- PB0_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK
- PB0_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT
- PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK
- PB0_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT
- PB0_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK
- PB0_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT
- PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK
- PB0_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT
- PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK
- PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK
- PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK
- PB0_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK
- PB0_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK
- PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK
- PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT
- PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK
- PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT
- PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK
- PB0_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK
- PB0_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK
- PB0_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK
- PB0_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK
- PB0_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK
- PB0_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT
- PB0_HW_DEBUG__HW_00_DEBUG_MASK
- PB0_HW_DEBUG__HW_00_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_01_DEBUG_MASK
- PB0_HW_DEBUG__HW_01_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_02_DEBUG_MASK
- PB0_HW_DEBUG__HW_02_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_03_DEBUG_MASK
- PB0_HW_DEBUG__HW_03_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_04_DEBUG_MASK
- PB0_HW_DEBUG__HW_04_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_05_DEBUG_MASK
- PB0_HW_DEBUG__HW_05_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_06_DEBUG_MASK
- PB0_HW_DEBUG__HW_06_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_07_DEBUG_MASK
- PB0_HW_DEBUG__HW_07_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_08_DEBUG_MASK
- PB0_HW_DEBUG__HW_08_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_09_DEBUG_MASK
- PB0_HW_DEBUG__HW_09_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_10_DEBUG_MASK
- PB0_HW_DEBUG__HW_10_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_11_DEBUG_MASK
- PB0_HW_DEBUG__HW_11_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_12_DEBUG_MASK
- PB0_HW_DEBUG__HW_12_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_13_DEBUG_MASK
- PB0_HW_DEBUG__HW_13_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_14_DEBUG_MASK
- PB0_HW_DEBUG__HW_14_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_15_DEBUG_MASK
- PB0_HW_DEBUG__HW_15_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_16_DEBUG_MASK
- PB0_HW_DEBUG__HW_16_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_17_DEBUG_MASK
- PB0_HW_DEBUG__HW_17_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_18_DEBUG_MASK
- PB0_HW_DEBUG__HW_18_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_19_DEBUG_MASK
- PB0_HW_DEBUG__HW_19_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_20_DEBUG_MASK
- PB0_HW_DEBUG__HW_20_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_21_DEBUG_MASK
- PB0_HW_DEBUG__HW_21_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_22_DEBUG_MASK
- PB0_HW_DEBUG__HW_22_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_23_DEBUG_MASK
- PB0_HW_DEBUG__HW_23_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_24_DEBUG_MASK
- PB0_HW_DEBUG__HW_24_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_25_DEBUG_MASK
- PB0_HW_DEBUG__HW_25_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_26_DEBUG_MASK
- PB0_HW_DEBUG__HW_26_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_27_DEBUG_MASK
- PB0_HW_DEBUG__HW_27_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_28_DEBUG_MASK
- PB0_HW_DEBUG__HW_28_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_29_DEBUG_MASK
- PB0_HW_DEBUG__HW_29_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_30_DEBUG_MASK
- PB0_HW_DEBUG__HW_30_DEBUG__SHIFT
- PB0_HW_DEBUG__HW_31_DEBUG_MASK
- PB0_HW_DEBUG__HW_31_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_00_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_00_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_01_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_01_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_02_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_02_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_03_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_03_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_04_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_04_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_05_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_05_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_06_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_06_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_07_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_07_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_08_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_08_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_09_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_09_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_10_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_10_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_11_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_11_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_12_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_12_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_13_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_13_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_14_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_14_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_15_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_15_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_16_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_16_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_17_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_17_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_18_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_18_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_19_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_19_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_20_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_20_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_21_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_21_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_22_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_22_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_23_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_23_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_24_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_24_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_25_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_25_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_26_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_26_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_27_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_27_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_28_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_28_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_29_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_29_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_30_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_30_DEBUG__SHIFT
- PB0_HW_DEBUG__PB0_HW_31_DEBUG_MASK
- PB0_HW_DEBUG__PB0_HW_31_DEBUG__SHIFT
- PB0_IN
- PB0_IOR_IN
- PB0_IOR_OUT
- PB0_OUT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK
- PB0_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK
- PB0_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK
- PB0_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK
- PB0_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT
- PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK
- PB0_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK
- PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT
- PB0_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT
- PB0_PIF_CNTL
- PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK
- PB0_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT
- PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK
- PB0_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT
- PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK
- PB0_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK
- PB0_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_CNTL2__RXDETECT_PRG_EN_MASK
- PB0_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT
- PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK
- PB0_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT
- PB0_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK
- PB0_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT
- PB0_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK
- PB0_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT
- PB0_PIF_CNTL2__RX_STAGGERING_MODE_MASK
- PB0_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT
- PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK
- PB0_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT
- PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK
- PB0_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT
- PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK
- PB0_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT
- PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK
- PB0_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT
- PB0_PIF_CNTL__DA_FIFO_RESET_0_MASK
- PB0_PIF_CNTL__DA_FIFO_RESET_0__SHIFT
- PB0_PIF_CNTL__DA_FIFO_RESET_1_MASK
- PB0_PIF_CNTL__DA_FIFO_RESET_1__SHIFT
- PB0_PIF_CNTL__DA_FIFO_RESET_2_MASK
- PB0_PIF_CNTL__DA_FIFO_RESET_2__SHIFT
- PB0_PIF_CNTL__DA_FIFO_RESET_3_MASK
- PB0_PIF_CNTL__DA_FIFO_RESET_3__SHIFT
- PB0_PIF_CNTL__DIVINIT_ENABLE_MASK
- PB0_PIF_CNTL__DIVINIT_ENABLE__SHIFT
- PB0_PIF_CNTL__DIVINIT_MODE_MASK
- PB0_PIF_CNTL__DIVINIT_MODE__SHIFT
- PB0_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK
- PB0_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT
- PB0_PIF_CNTL__EI_DET_CYCLE_MODE_MASK
- PB0_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT
- PB0_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK
- PB0_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT
- PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK
- PB0_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT
- PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK
- PB0_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT
- PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK
- PB0_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT
- PB0_PIF_CNTL__LS2_EXIT_TIME_MASK
- PB0_PIF_CNTL__LS2_EXIT_TIME__SHIFT
- PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK
- PB0_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT
- PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK
- PB0_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT
- PB0_PIF_CNTL__PHY_CR_EN_MODE_MASK
- PB0_PIF_CNTL__PHY_CR_EN_MODE__SHIFT
- PB0_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK
- PB0_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT
- PB0_PIF_CNTL__PLL_BINDING_ENABLE_MASK
- PB0_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT
- PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK
- PB0_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT
- PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK
- PB0_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT
- PB0_PIF_CNTL__RXEN_GATER_MASK
- PB0_PIF_CNTL__RXEN_GATER__SHIFT
- PB0_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK
- PB0_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT
- PB0_PIF_CNTL__SERIAL_CFG_ENABLE_MASK
- PB0_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT
- PB0_PIF_CNTL__TXGND_TIME_MASK
- PB0_PIF_CNTL__TXGND_TIME__SHIFT
- PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK
- PB0_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT
- PB0_PIF_CTRL__PHY_RST_PWROK_VDD_MASK
- PB0_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT
- PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK
- PB0_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT
- PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK
- PB0_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT
- PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK
- PB0_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT
- PB0_PIF_CTRL__PIF_PG_EXIT_MODE_MASK
- PB0_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT
- PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK
- PB0_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT
- PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK
- PB0_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT
- PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK
- PB0_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT
- PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK
- PB0_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT
- PB0_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK
- PB0_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT
- PB0_PIF_CTRL__PIF_PLL_STATUS_MASK
- PB0_PIF_CTRL__PIF_PLL_STATUS__SHIFT
- PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK
- PB0_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT
- PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT
- PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK
- PB0_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK
- PB0_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_HW_DEBUG__HW_00_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_01_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_02_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_03_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_04_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_05_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_06_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_07_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_08_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_09_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_10_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_11_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_12_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_13_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_14_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__HW_15_DEBUG_MASK
- PB0_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_00_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_01_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_02_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_03_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_04_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_05_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_06_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_07_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_08_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_09_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_10_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_11_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_12_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_13_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_14_DEBUG__SHIFT
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG_MASK
- PB0_PIF_HW_DEBUG__PB0_PIF_HW_15_DEBUG__SHIFT
- PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK
- PB0_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT
- PB0_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK
- PB0_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT
- PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK
- PB0_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT
- PB0_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK
- PB0_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT
- PB0_PIF_LANE0_OVRD2__FREQDIV_0_MASK
- PB0_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT
- PB0_PIF_LANE0_OVRD2__GANGMODE_0_MASK
- PB0_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT
- PB0_PIF_LANE0_OVRD2__LINKSPEED_0_MASK
- PB0_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT
- PB0_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK
- PB0_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT
- PB0_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK
- PB0_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT
- PB0_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK
- PB0_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT
- PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK
- PB0_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT
- PB0_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK
- PB0_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT
- PB0_PIF_LANE0_OVRD2__RXPWR_0_MASK
- PB0_PIF_LANE0_OVRD2__RXPWR_0__SHIFT
- PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK
- PB0_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT
- PB0_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK
- PB0_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT
- PB0_PIF_LANE0_OVRD2__TXPWR_0_MASK
- PB0_PIF_LANE0_OVRD2__TXPWR_0__SHIFT
- PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK
- PB0_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT
- PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT
- PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK
- PB0_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT
- PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK
- PB0_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT
- PB0_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK
- PB0_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT
- PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK
- PB0_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT
- PB0_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK
- PB0_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT
- PB0_PIF_LANE1_OVRD2__FREQDIV_1_MASK
- PB0_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT
- PB0_PIF_LANE1_OVRD2__GANGMODE_1_MASK
- PB0_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT
- PB0_PIF_LANE1_OVRD2__LINKSPEED_1_MASK
- PB0_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT
- PB0_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK
- PB0_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT
- PB0_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK
- PB0_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT
- PB0_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK
- PB0_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT
- PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK
- PB0_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT
- PB0_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK
- PB0_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT
- PB0_PIF_LANE1_OVRD2__RXPWR_1_MASK
- PB0_PIF_LANE1_OVRD2__RXPWR_1__SHIFT
- PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK
- PB0_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT
- PB0_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK
- PB0_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT
- PB0_PIF_LANE1_OVRD2__TXPWR_1_MASK
- PB0_PIF_LANE1_OVRD2__TXPWR_1__SHIFT
- PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK
- PB0_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT
- PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT
- PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK
- PB0_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT
- PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK
- PB0_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT
- PB0_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK
- PB0_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT
- PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK
- PB0_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT
- PB0_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK
- PB0_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT
- PB0_PIF_LANE2_OVRD2__FREQDIV_2_MASK
- PB0_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT
- PB0_PIF_LANE2_OVRD2__GANGMODE_2_MASK
- PB0_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT
- PB0_PIF_LANE2_OVRD2__LINKSPEED_2_MASK
- PB0_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT
- PB0_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK
- PB0_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT
- PB0_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK
- PB0_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT
- PB0_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK
- PB0_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT
- PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK
- PB0_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT
- PB0_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK
- PB0_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT
- PB0_PIF_LANE2_OVRD2__RXPWR_2_MASK
- PB0_PIF_LANE2_OVRD2__RXPWR_2__SHIFT
- PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK
- PB0_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT
- PB0_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK
- PB0_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT
- PB0_PIF_LANE2_OVRD2__TXPWR_2_MASK
- PB0_PIF_LANE2_OVRD2__TXPWR_2__SHIFT
- PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK
- PB0_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT
- PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT
- PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK
- PB0_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT
- PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK
- PB0_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT
- PB0_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK
- PB0_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT
- PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK
- PB0_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT
- PB0_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK
- PB0_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT
- PB0_PIF_LANE3_OVRD2__FREQDIV_3_MASK
- PB0_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT
- PB0_PIF_LANE3_OVRD2__GANGMODE_3_MASK
- PB0_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT
- PB0_PIF_LANE3_OVRD2__LINKSPEED_3_MASK
- PB0_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT
- PB0_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK
- PB0_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT
- PB0_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK
- PB0_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT
- PB0_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK
- PB0_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT
- PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK
- PB0_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT
- PB0_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK
- PB0_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT
- PB0_PIF_LANE3_OVRD2__RXPWR_3_MASK
- PB0_PIF_LANE3_OVRD2__RXPWR_3__SHIFT
- PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK
- PB0_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT
- PB0_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK
- PB0_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT
- PB0_PIF_LANE3_OVRD2__TXPWR_3_MASK
- PB0_PIF_LANE3_OVRD2__TXPWR_3__SHIFT
- PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK
- PB0_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT
- PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT
- PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK
- PB0_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT
- PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK
- PB0_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT
- PB0_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK
- PB0_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT
- PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK
- PB0_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT
- PB0_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK
- PB0_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT
- PB0_PIF_LANE4_OVRD2__FREQDIV_4_MASK
- PB0_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT
- PB0_PIF_LANE4_OVRD2__GANGMODE_4_MASK
- PB0_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT
- PB0_PIF_LANE4_OVRD2__LINKSPEED_4_MASK
- PB0_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT
- PB0_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK
- PB0_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT
- PB0_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK
- PB0_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT
- PB0_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK
- PB0_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT
- PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK
- PB0_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT
- PB0_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK
- PB0_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT
- PB0_PIF_LANE4_OVRD2__RXPWR_4_MASK
- PB0_PIF_LANE4_OVRD2__RXPWR_4__SHIFT
- PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK
- PB0_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT
- PB0_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK
- PB0_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT
- PB0_PIF_LANE4_OVRD2__TXPWR_4_MASK
- PB0_PIF_LANE4_OVRD2__TXPWR_4__SHIFT
- PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK
- PB0_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT
- PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT
- PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK
- PB0_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT
- PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK
- PB0_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT
- PB0_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK
- PB0_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT
- PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK
- PB0_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT
- PB0_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK
- PB0_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT
- PB0_PIF_LANE5_OVRD2__FREQDIV_5_MASK
- PB0_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT
- PB0_PIF_LANE5_OVRD2__GANGMODE_5_MASK
- PB0_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT
- PB0_PIF_LANE5_OVRD2__LINKSPEED_5_MASK
- PB0_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT
- PB0_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK
- PB0_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT
- PB0_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK
- PB0_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT
- PB0_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK
- PB0_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT
- PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK
- PB0_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT
- PB0_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK
- PB0_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT
- PB0_PIF_LANE5_OVRD2__RXPWR_5_MASK
- PB0_PIF_LANE5_OVRD2__RXPWR_5__SHIFT
- PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK
- PB0_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT
- PB0_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK
- PB0_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT
- PB0_PIF_LANE5_OVRD2__TXPWR_5_MASK
- PB0_PIF_LANE5_OVRD2__TXPWR_5__SHIFT
- PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK
- PB0_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT
- PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT
- PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK
- PB0_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT
- PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK
- PB0_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT
- PB0_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK
- PB0_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT
- PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK
- PB0_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT
- PB0_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK
- PB0_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT
- PB0_PIF_LANE6_OVRD2__FREQDIV_6_MASK
- PB0_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT
- PB0_PIF_LANE6_OVRD2__GANGMODE_6_MASK
- PB0_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT
- PB0_PIF_LANE6_OVRD2__LINKSPEED_6_MASK
- PB0_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT
- PB0_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK
- PB0_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT
- PB0_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK
- PB0_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT
- PB0_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK
- PB0_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT
- PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK
- PB0_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT
- PB0_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK
- PB0_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT
- PB0_PIF_LANE6_OVRD2__RXPWR_6_MASK
- PB0_PIF_LANE6_OVRD2__RXPWR_6__SHIFT
- PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK
- PB0_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT
- PB0_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK
- PB0_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT
- PB0_PIF_LANE6_OVRD2__TXPWR_6_MASK
- PB0_PIF_LANE6_OVRD2__TXPWR_6__SHIFT
- PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK
- PB0_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT
- PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT
- PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK
- PB0_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT
- PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK
- PB0_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT
- PB0_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK
- PB0_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT
- PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK
- PB0_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT
- PB0_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK
- PB0_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT
- PB0_PIF_LANE7_OVRD2__FREQDIV_7_MASK
- PB0_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT
- PB0_PIF_LANE7_OVRD2__GANGMODE_7_MASK
- PB0_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT
- PB0_PIF_LANE7_OVRD2__LINKSPEED_7_MASK
- PB0_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT
- PB0_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK
- PB0_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT
- PB0_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK
- PB0_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT
- PB0_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK
- PB0_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT
- PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK
- PB0_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT
- PB0_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK
- PB0_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT
- PB0_PIF_LANE7_OVRD2__RXPWR_7_MASK
- PB0_PIF_LANE7_OVRD2__RXPWR_7__SHIFT
- PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK
- PB0_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT
- PB0_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK
- PB0_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT
- PB0_PIF_LANE7_OVRD2__TXPWR_7_MASK
- PB0_PIF_LANE7_OVRD2__TXPWR_7__SHIFT
- PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK
- PB0_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT
- PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT
- PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK
- PB0_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT
- PB0_PIF_PAIRING
- PB0_PIF_PAIRING__MULTI_PIF_MASK
- PB0_PIF_PAIRING__MULTI_PIF__SHIFT
- PB0_PIF_PAIRING__X16_LANE_15_0_MASK
- PB0_PIF_PAIRING__X16_LANE_15_0__SHIFT
- PB0_PIF_PAIRING__X2_LANE_11_10_MASK
- PB0_PIF_PAIRING__X2_LANE_11_10__SHIFT
- PB0_PIF_PAIRING__X2_LANE_13_12_MASK
- PB0_PIF_PAIRING__X2_LANE_13_12__SHIFT
- PB0_PIF_PAIRING__X2_LANE_15_14_MASK
- PB0_PIF_PAIRING__X2_LANE_15_14__SHIFT
- PB0_PIF_PAIRING__X2_LANE_1_0_MASK
- PB0_PIF_PAIRING__X2_LANE_1_0__SHIFT
- PB0_PIF_PAIRING__X2_LANE_3_2_MASK
- PB0_PIF_PAIRING__X2_LANE_3_2__SHIFT
- PB0_PIF_PAIRING__X2_LANE_5_4_MASK
- PB0_PIF_PAIRING__X2_LANE_5_4__SHIFT
- PB0_PIF_PAIRING__X2_LANE_7_6_MASK
- PB0_PIF_PAIRING__X2_LANE_7_6__SHIFT
- PB0_PIF_PAIRING__X2_LANE_9_8_MASK
- PB0_PIF_PAIRING__X2_LANE_9_8__SHIFT
- PB0_PIF_PAIRING__X4_LANE_11_8_MASK
- PB0_PIF_PAIRING__X4_LANE_11_8__SHIFT
- PB0_PIF_PAIRING__X4_LANE_15_12_MASK
- PB0_PIF_PAIRING__X4_LANE_15_12__SHIFT
- PB0_PIF_PAIRING__X4_LANE_3_0_MASK
- PB0_PIF_PAIRING__X4_LANE_3_0__SHIFT
- PB0_PIF_PAIRING__X4_LANE_7_4_MASK
- PB0_PIF_PAIRING__X4_LANE_7_4__SHIFT
- PB0_PIF_PAIRING__X8_LANE_15_8_MASK
- PB0_PIF_PAIRING__X8_LANE_15_8__SHIFT
- PB0_PIF_PAIRING__X8_LANE_7_0_MASK
- PB0_PIF_PAIRING__X8_LANE_7_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK
- PB0_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK
- PB0_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK
- PB0_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK
- PB0_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK
- PB0_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK
- PB0_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK
- PB0_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK
- PB0_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK
- PB0_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK
- PB0_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK
- PB0_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK
- PB0_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK
- PB0_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK
- PB0_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK
- PB0_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT
- PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK
- PB0_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT
- PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK
- PB0_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT
- PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK
- PB0_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT
- PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK
- PB0_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT
- PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK
- PB0_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT
- PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK
- PB0_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT
- PB0_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK
- PB0_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT
- PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK
- PB0_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT
- PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK
- PB0_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT
- PB0_PIF_PWRDOWN_0
- PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK
- PB0_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT
- PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK
- PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT
- PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK
- PB0_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT
- PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
- PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
- PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
- PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
- PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK
- PB0_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT
- PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK
- PB0_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT
- PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK
- PB0_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT
- PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK
- PB0_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT
- PB0_PIF_PWRDOWN_1
- PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK
- PB0_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT
- PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK
- PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT
- PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK
- PB0_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT
- PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
- PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
- PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
- PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
- PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK
- PB0_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT
- PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK
- PB0_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT
- PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK
- PB0_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT
- PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK
- PB0_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT
- PB0_PIF_PWRDOWN_2
- PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK
- PB0_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT
- PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK
- PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT
- PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK
- PB0_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT
- PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK
- PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT
- PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK
- PB0_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT
- PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK
- PB0_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT
- PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK
- PB0_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT
- PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK
- PB0_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT
- PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK
- PB0_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT
- PB0_PIF_PWRDOWN_3
- PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK
- PB0_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT
- PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK
- PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT
- PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK
- PB0_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT
- PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK
- PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT
- PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK
- PB0_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT
- PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK
- PB0_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT
- PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK
- PB0_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT
- PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK
- PB0_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT
- PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK
- PB0_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT
- PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK
- PB0_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT
- PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK
- PB0_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT
- PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK
- PB0_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT
- PB0_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK
- PB0_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT
- PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK
- PB0_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT
- PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK
- PB0_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT
- PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK
- PB0_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT
- PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK
- PB0_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT
- PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK
- PB0_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT
- PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK
- PB0_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK
- PB0_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT
- PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK
- PB0_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK
- PB0_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK
- PB0_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_INIT_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_OFF_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_S2_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK
- PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT
- PB0_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT
- PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK
- PB0_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT
- PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK
- PB0_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT
- PB0_PIF_SCRATCH__PIF_SCRATCH_MASK
- PB0_PIF_SCRATCH__PIF_SCRATCH__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK
- PB0_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT
- PB0_PIF_SC_CTL__SC_CALIBRATION_MASK
- PB0_PIF_SC_CTL__SC_CALIBRATION__SHIFT
- PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK
- PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT
- PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK
- PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT
- PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK
- PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT
- PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK
- PB0_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_0_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_10_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_11_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_12_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_13_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_14_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_15_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_1_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_2_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_3_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_4_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_5_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_6_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_7_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_8_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_LANE_9_RESUME_MASK
- PB0_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_1_MASK
- PB0_PIF_SC_CTL__SC_PHASE_1__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_2_MASK
- PB0_PIF_SC_CTL__SC_PHASE_2__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_3_MASK
- PB0_PIF_SC_CTL__SC_PHASE_3__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_4_MASK
- PB0_PIF_SC_CTL__SC_PHASE_4__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_5_MASK
- PB0_PIF_SC_CTL__SC_PHASE_5__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_6_MASK
- PB0_PIF_SC_CTL__SC_PHASE_6__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_7_MASK
- PB0_PIF_SC_CTL__SC_PHASE_7__SHIFT
- PB0_PIF_SC_CTL__SC_PHASE_8_MASK
- PB0_PIF_SC_CTL__SC_PHASE_8__SHIFT
- PB0_PIF_SC_CTL__SC_RXDETECT_MASK
- PB0_PIF_SC_CTL__SC_RXDETECT__SHIFT
- PB0_PIF_SC_CTL__SC_SPEED_CHANGE_MASK
- PB0_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT
- PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK
- PB0_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT
- PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK
- PB0_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT
- PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK
- PB0_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT
- PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK
- PB0_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT
- PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK
- PB0_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT
- PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK
- PB0_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT
- PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK
- PB0_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT
- PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK
- PB0_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT
- PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK
- PB0_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT
- PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK
- PB0_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT
- PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK
- PB0_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT
- PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK
- PB0_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT
- PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK
- PB0_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT
- PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK
- PB0_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT
- PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK
- PB0_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT
- PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK
- PB0_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT
- PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK
- PB0_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT
- PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK
- PB0_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT
- PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK
- PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT
- PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK
- PB0_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT
- PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK
- PB0_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT
- PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK
- PB0_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT
- PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK
- PB0_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT
- PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK
- PB0_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT
- PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK
- PB0_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK
- PB0_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT
- PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK
- PB0_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT
- PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK
- PB0_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT
- PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK
- PB0_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT
- PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK
- PB0_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT
- PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK
- PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT
- PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK
- PB0_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT
- PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK
- PB0_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT
- PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK
- PB0_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT
- PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK
- PB0_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT
- PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK
- PB0_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT
- PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK
- PB0_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK
- PB0_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT
- PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK
- PB0_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK
- PB0_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK
- PB0_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_INIT_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_OFF_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_S2_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK
- PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT
- PB0_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK
- PB0_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT
- PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK
- PB0_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK
- PB0_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK
- PB0_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK
- PB0_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK
- PB0_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK
- PB0_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK
- PB0_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT
- PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK
- PB0_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK
- PB0_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK
- PB0_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK
- PB0_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK
- PB0_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK
- PB0_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK
- PB0_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK
- PB0_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK
- PB0_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK
- PB0_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK
- PB0_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK
- PB0_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK
- PB0_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK
- PB0_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK
- PB0_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK
- PB0_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK
- PB0_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK
- PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK
- PB0_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK
- PB0_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK
- PB0_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK
- PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT
- PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK
- PB0_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK
- PB0_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK
- PB0_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT
- PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK
- PB0_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT
- PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK
- PB0_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT
- PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK
- PB0_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT
- PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK
- PB0_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT
- PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK
- PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT
- PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK
- PB0_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK
- PB0_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT
- PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK
- PB0_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT
- PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK
- PB0_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT
- PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK
- PB0_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT
- PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK
- PB0_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT
- PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK
- PB0_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK
- PB0_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT
- PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK
- PB0_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT
- PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK
- PB0_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT
- PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK
- PB0_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT
- PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK
- PB0_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT
- PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK
- PB0_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK
- PB0_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT
- PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK
- PB0_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT
- PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK
- PB0_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT
- PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK
- PB0_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT
- PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK
- PB0_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT
- PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK
- PB0_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK
- PB0_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT
- PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK
- PB0_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT
- PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK
- PB0_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT
- PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK
- PB0_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT
- PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK
- PB0_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT
- PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK
- PB0_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK
- PB0_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT
- PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK
- PB0_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT
- PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK
- PB0_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT
- PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK
- PB0_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT
- PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK
- PB0_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT
- PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK
- PB0_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK
- PB0_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT
- PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK
- PB0_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT
- PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK
- PB0_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT
- PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK
- PB0_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT
- PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK
- PB0_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT
- PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK
- PB0_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK
- PB0_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT
- PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK
- PB0_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT
- PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK
- PB0_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT
- PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK
- PB0_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT
- PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK
- PB0_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT
- PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK
- PB0_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK
- PB0_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT
- PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK
- PB0_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT
- PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK
- PB0_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT
- PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK
- PB0_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT
- PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK
- PB0_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT
- PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK
- PB0_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK
- PB0_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT
- PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK
- PB0_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT
- PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK
- PB0_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT
- PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK
- PB0_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT
- PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK
- PB0_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT
- PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK
- PB0_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK
- PB0_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT
- PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK
- PB0_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT
- PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK
- PB0_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT
- PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK
- PB0_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT
- PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK
- PB0_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT
- PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK
- PB0_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK
- PB0_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT
- PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK
- PB0_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT
- PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK
- PB0_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT
- PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK
- PB0_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT
- PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK
- PB0_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT
- PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK
- PB0_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK
- PB0_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT
- PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK
- PB0_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT
- PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK
- PB0_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT
- PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK
- PB0_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT
- PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK
- PB0_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT
- PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK
- PB0_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK
- PB0_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT
- PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK
- PB0_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT
- PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK
- PB0_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT
- PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK
- PB0_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT
- PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK
- PB0_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT
- PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK
- PB0_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK
- PB0_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT
- PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK
- PB0_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT
- PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK
- PB0_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT
- PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK
- PB0_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT
- PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK
- PB0_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT
- PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK
- PB0_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK
- PB0_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT
- PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK
- PB0_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT
- PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK
- PB0_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT
- PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK
- PB0_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT
- PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK
- PB0_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT
- PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK
- PB0_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK
- PB0_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT
- PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK
- PB0_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT
- PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK
- PB0_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT
- PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK
- PB0_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT
- PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK
- PB0_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT
- PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK
- PB0_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK
- PB0_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK
- PB0_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK
- PB0_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK
- PB0_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK
- PB0_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK
- PB0_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK
- PB0_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK
- PB0_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK
- PB0_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK
- PB0_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK
- PB0_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT
- PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK
- PB0_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT
- PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK
- PB0_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK
- PB0_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK
- PB0_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK
- PB0_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK
- PB0_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK
- PB0_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT
- PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK
- PB0_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT
- PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK
- PB0_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT
- PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK
- PB0_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK
- PB0_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK
- PB0_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT
- PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK
- PB0_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT
- PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK
- PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT
- PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK
- PB0_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT
- PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK
- PB0_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK
- PB0_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT
- PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK
- PB0_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT
- PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK
- PB0_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK
- PB0_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT
- PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK
- PB0_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT
- PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK
- PB0_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK
- PB0_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK
- PB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK
- PB0_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK
- PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK
- PB0_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK
- PB0_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK
- PB0_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK
- PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK
- PB0_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK
- PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK
- PB0_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK
- PB0_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT
- PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK
- PB0_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK
- PB0_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK
- PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT
- PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB0_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK
- PB0_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK
- PB0_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT
- PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK
- PB0_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT
- PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK
- PB0_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK
- PB0_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK
- PB0_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT
- PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK
- PB0_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT
- PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK
- PB0_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK
- PB0_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK
- PB0_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT
- PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK
- PB0_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT
- PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK
- PB0_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK
- PB0_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK
- PB0_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT
- PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK
- PB0_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT
- PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK
- PB0_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK
- PB0_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK
- PB0_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT
- PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK
- PB0_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT
- PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK
- PB0_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK
- PB0_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK
- PB0_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT
- PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK
- PB0_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT
- PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK
- PB0_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK
- PB0_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK
- PB0_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT
- PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK
- PB0_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT
- PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK
- PB0_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK
- PB0_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK
- PB0_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT
- PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK
- PB0_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT
- PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK
- PB0_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK
- PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK
- PB0_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT
- PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK
- PB0_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT
- PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK
- PB0_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK
- PB0_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK
- PB0_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT
- PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK
- PB0_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT
- PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK
- PB0_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK
- PB0_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK
- PB0_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT
- PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK
- PB0_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT
- PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK
- PB0_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK
- PB0_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK
- PB0_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT
- PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK
- PB0_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT
- PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK
- PB0_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK
- PB0_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK
- PB0_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT
- PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK
- PB0_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT
- PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK
- PB0_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK
- PB0_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK
- PB0_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT
- PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK
- PB0_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT
- PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK
- PB0_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK
- PB0_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK
- PB0_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT
- PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK
- PB0_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT
- PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK
- PB0_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK
- PB0_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK
- PB0_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT
- PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK
- PB0_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT
- PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK
- PB0_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK
- PB0_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT
- PB1
- PB10MD_0
- PB10MD_00
- PB10MD_01
- PB10MD_1
- PB10MD_10
- PB10MD_11
- PB10_AF_UART6_TXD
- PB10_DATA
- PB10_IN
- PB10_IOR_IN
- PB10_IOR_OUT
- PB10_OUT
- PB10_PF_CSI_D0
- PB11MD_0
- PB11MD_00
- PB11MD_01
- PB11MD_1
- PB11MD_10
- PB11MD_11
- PB11_AF_UART6_RXD
- PB11_DATA
- PB11_IN
- PB11_IOR_IN
- PB11_IOR_OUT
- PB11_OUT
- PB11_PF_CSI_D1
- PB1200_BCSR_HEXLED_OFS
- PB1200_BCSR_PHYS_ADDR
- PB1200_ETH_PHYS_ADDR
- PB1200_IDE_PHYS_ADDR
- PB1200_NAND_PHYS_ADDR
- PB1200_SD1_EJECT_INT
- PB1200_SD1_INSERT_INT
- PB12IRQ_00
- PB12IRQ_01
- PB12IRQ_10
- PB12MD_00
- PB12MD_01
- PB12MD_10
- PB12MD_11
- PB12_AF_UART6_CTS
- PB12_DATA
- PB12_IN
- PB12_IOR_IN
- PB12_IOR_OUT
- PB12_OUT
- PB12_PF_CSI_D2
- PB13MD_00
- PB13MD_000
- PB13MD_001
- PB13MD_01
- PB13MD_010
- PB13MD_011
- PB13MD_10
- PB13MD_100
- PB13MD_101
- PB13MD_11
- PB13MD_110
- PB13MD_111
- PB13_AF_UART6_RTS
- PB13_DATA
- PB13_IN
- PB13_IOR_IN
- PB13_IOR_OUT
- PB13_OUT
- PB13_PF_CSI_D3
- PB14MD_00
- PB14MD_000
- PB14MD_001
- PB14MD_01
- PB14MD_010
- PB14MD_011
- PB14MD_10
- PB14MD_100
- PB14MD_101
- PB14MD_11
- PB14MD_110
- PB14MD_111
- PB14_DATA
- PB14_IN
- PB14_IOR_IN
- PB14_IOR_OUT
- PB14_OUT
- PB14_PF_CSI_D4
- PB1550_BCSR_HEXLED_OFS
- PB1550_BCSR_PHYS_ADDR
- PB15MD_00
- PB15MD_000
- PB15MD_001
- PB15MD_01
- PB15MD_010
- PB15MD_011
- PB15MD_10
- PB15MD_100
- PB15MD_101
- PB15MD_11
- PB15MD_110
- PB15MD_111
- PB15_DATA
- PB15_IN
- PB15_IOR_IN
- PB15_IOR_OUT
- PB15_OUT
- PB15_PF_CSI_MCLK
- PB16MD_00
- PB16MD_000
- PB16MD_001
- PB16MD_01
- PB16MD_010
- PB16MD_011
- PB16MD_10
- PB16MD_100
- PB16MD_101
- PB16MD_11
- PB16MD_110
- PB16MD_111
- PB16_DATA
- PB16_IN
- PB16_IOR_IN
- PB16_IOR_OUT
- PB16_OUT
- PB16_PF_CSI_PIXCLK
- PB17MD_00
- PB17MD_000
- PB17MD_001
- PB17MD_01
- PB17MD_010
- PB17MD_011
- PB17MD_10
- PB17MD_100
- PB17MD_101
- PB17MD_11
- PB17MD_110
- PB17MD_111
- PB17_DATA
- PB17_IN
- PB17_IOR_IN
- PB17_IOR_OUT
- PB17_OUT
- PB17_PF_CSI_D5
- PB18MD_00
- PB18MD_000
- PB18MD_001
- PB18MD_01
- PB18MD_010
- PB18MD_011
- PB18MD_10
- PB18MD_100
- PB18MD_101
- PB18MD_11
- PB18MD_110
- PB18MD_111
- PB18_AF_UART5_TXD
- PB18_DATA
- PB18_IN
- PB18_IOR_IN
- PB18_IOR_OUT
- PB18_OUT
- PB18_PF_CSI_D6
- PB19MD_00
- PB19MD_000
- PB19MD_001
- PB19MD_01
- PB19MD_010
- PB19MD_011
- PB19MD_10
- PB19MD_100
- PB19MD_101
- PB19MD_11
- PB19MD_110
- PB19MD_111
- PB19_AF_UART5_RXD
- PB19_DATA
- PB19_IN
- PB19_IOR_IN
- PB19_IOR_OUT
- PB19_OUT
- PB19_PF_CSI_D7
- PB1CLK
- PB1DIV
- PB1MD_0
- PB1MD_00
- PB1MD_01
- PB1MD_1
- PB1MD_10
- PB1MD_11
- PB1_DATA
- PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN_MASK
- PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_EN__SHIFT
- PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE_MASK
- PB1_DFT_DEBUG_CTRL_REG0__DFT_PHY_DEBUG_MODE__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_CLK_PER_STEP__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_DECR_SWP_EN__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_DISABLE_ERR__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_EN_RECOVERY__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_INCR_SWP_EN__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_MODE_CDR_EN__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_NUM_STEPS__SHIFT
- PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME_MASK
- PB1_DFT_JIT_INJ_REG0__DFT_RECOVERY_TIME__SHIFT
- PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN_MASK
- PB1_DFT_JIT_INJ_REG1__DFT_BLOCK_EN__SHIFT
- PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN_MASK
- PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_EN__SHIFT
- PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE_MASK
- PB1_DFT_JIT_INJ_REG1__DFT_BYPASS_VALUE__SHIFT
- PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME_MASK
- PB1_DFT_JIT_INJ_REG1__DFT_CHECK_TIME__SHIFT
- PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS_MASK
- PB1_DFT_JIT_INJ_REG1__DFT_NUM_OF_TESTS__SHIFT
- PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN_MASK
- PB1_DFT_JIT_INJ_REG2__DFT_LANE_EN__SHIFT
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR_MASK
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_DECR__SHIFT
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED_MASK
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_FINISHED__SHIFT
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR_MASK
- PB1_DFT_JIT_INJ_STAT_REG0__DFT_STAT_INCR__SHIFT
- PB1_FN
- PB1_GLB_CTRL_REG0__BACKUP_MASK
- PB1_GLB_CTRL_REG0__BACKUP__SHIFT
- PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH_MASK
- PB1_GLB_CTRL_REG0__CFG_IDLEDET_TH__SHIFT
- PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL_MASK
- PB1_GLB_CTRL_REG0__DBG_RX2TXBYP_SEL__SHIFT
- PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN_MASK
- PB1_GLB_CTRL_REG0__DBG_RXFEBYP_EN__SHIFT
- PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR_MASK
- PB1_GLB_CTRL_REG0__DBG_RXPRBS_CLR__SHIFT
- PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN_MASK
- PB1_GLB_CTRL_REG0__DBG_RXTOGGLE_EN__SHIFT
- PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN_MASK
- PB1_GLB_CTRL_REG0__DBG_TX2RXLBACK_EN__SHIFT
- PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE_MASK
- PB1_GLB_CTRL_REG0__TXCFG_CMGOOD_RANGE__SHIFT
- PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV_MASK
- PB1_GLB_CTRL_REG1__PLL_CFG_DISPCLK_DIV__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN_MASK
- PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL_MASK
- PB1_GLB_CTRL_REG1__RXDBG_CDR_FR_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN_MASK
- PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG1__RXDBG_CDR_PH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN_MASK
- PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG1__RXDBG_D0TH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN_MASK
- PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG1__RXDBG_D1TH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN_MASK
- PB1_GLB_CTRL_REG1__TST_LOSPDTST_EN__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN_MASK
- PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG2__RXDBG_D2TH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN_MASK
- PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG2__RXDBG_D3TH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN_MASK
- PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG2__RXDBG_DXTH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN_MASK
- PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL_MASK
- PB1_GLB_CTRL_REG2__RXDBG_ETH_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL_MASK
- PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF0_SEL__SHIFT
- PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK
- PB1_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL__SHIFT
- PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK
- PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL__SHIFT
- PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL_MASK
- PB1_GLB_CTRL_REG3__BG_DBG_ANALOG_SEL__SHIFT
- PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN_MASK
- PB1_GLB_CTRL_REG3__BG_DBG_IREFBYP_EN__SHIFT
- PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN_MASK
- PB1_GLB_CTRL_REG3__BG_DBG_VREFBYP_EN__SHIFT
- PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL_MASK
- PB1_GLB_CTRL_REG3__DBG_DLL_CLK_SEL__SHIFT
- PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE_MASK
- PB1_GLB_CTRL_REG3__DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE__SHIFT
- PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN_MASK
- PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL_MASK
- PB1_GLB_CTRL_REG3__DBG_RXPI_OFFSET_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN_MASK
- PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL_MASK
- PB1_GLB_CTRL_REG3__DBG_RXSWAPDX_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL_MASK
- PB1_GLB_CTRL_REG3__PLL_DISPCLK_CMOS_SEL__SHIFT
- PB1_GLB_CTRL_REG3__RXDBG_SEL_MASK
- PB1_GLB_CTRL_REG3__RXDBG_SEL__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC_MASK
- PB1_GLB_CTRL_REG4__DBG_RXAPU_EXEC__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXAPU_INST_MASK
- PB1_GLB_CTRL_REG4__DBG_RXAPU_INST__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN_MASK
- PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_EN__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL_MASK
- PB1_GLB_CTRL_REG4__DBG_RXDFEMUX_BYP_VAL__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL_MASK
- PB1_GLB_CTRL_REG4__DBG_RXDLL_VREG_REF_SEL__SHIFT
- PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE_MASK
- PB1_GLB_CTRL_REG4__DBG_RXRDATA_GATING_DISABLE__SHIFT
- PB1_GLB_CTRL_REG4__PWRGOOD_OVRD_MASK
- PB1_GLB_CTRL_REG4__PWRGOOD_OVRD__SHIFT
- PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE_MASK
- PB1_GLB_CTRL_REG5__DBG_RXAPU_MODE__SHIFT
- PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG0__TXPDTERM_VAL_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG0__TXPUTERM_VAL_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN_MASK
- PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG1__RXTERM_VAL_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN_MASK
- PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG1__TST_LOSPDTST_RST_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN_MASK
- PB1_GLB_OVRD_REG1__TXPDTERM_VAL_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN_MASK
- PB1_GLB_OVRD_REG1__TXPUTERM_VAL_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN_MASK
- PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG2__BG_PWRON_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN_MASK
- PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG2__PLL_DBG_LC_EXT_RESET_OVRD_VAL__SHIFT
- PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN_MASK
- PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_EN__SHIFT
- PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL_MASK
- PB1_GLB_OVRD_REG2__PLL_DBG_RO_EXT_RESET_OVRD_VAL__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_CBI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_ALL_SCI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_CBI_UPDT__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IGNR_IMPCAL_ACTIVE_SCI_UPDT__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__IMPCAL_ACTIVE__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__RXIMP__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__TXNIMP__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP_MASK
- PB1_GLB_SCI_STAT_OVRD_REG0__TXPIMP__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_0__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_1__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_2__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__DLL_LOCK_3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_0__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_1__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_2__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__FREQDIV_3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_CBI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_DLL_LOCK_SCI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_CBI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_FREQDIV_SCI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_LINKSPEED_CBI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__IGNR_MODE_SCI_UPDT_L0T3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_0__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_1__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_2__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__LINKSPEED_3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_1__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_2__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3_MASK
- PB1_GLB_SCI_STAT_OVRD_REG1__MODE_3__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_4__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_5__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_6__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__DLL_LOCK_7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_4__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_5__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_6__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__FREQDIV_7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_CBI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_DLL_LOCK_SCI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_CBI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_FREQDIV_SCI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_LINKSPEED_CBI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__IGNR_MODE_SCI_UPDT_L4T7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_4__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_5__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_6__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__LINKSPEED_7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_4__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_6__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7_MASK
- PB1_GLB_SCI_STAT_OVRD_REG2__MODE_7__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_10__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_8__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__DLL_LOCK_9__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_10__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_8__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__FREQDIV_9__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_CBI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_DLL_LOCK_SCI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_CBI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_FREQDIV_SCI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_LINKSPEED_CBI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__IGNR_MODE_SCI_UPDT_L8T11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_10__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_8__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__LINKSPEED_9__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_11__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_8__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9_MASK
- PB1_GLB_SCI_STAT_OVRD_REG3__MODE_9__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_12__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_13__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_14__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__DLL_LOCK_15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_12__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_13__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_14__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__FREQDIV_15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_CBI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_DLL_LOCK_SCI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_CBI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_FREQDIV_SCI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_LINKSPEED_CBI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__IGNR_MODE_SCI_UPDT_L12T15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_12__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_13__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_14__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__LINKSPEED_15__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_12__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_13__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_14__SHIFT
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15_MASK
- PB1_GLB_SCI_STAT_OVRD_REG4__MODE_15__SHIFT
- PB1_HW_DEBUG__HW_00_DEBUG_MASK
- PB1_HW_DEBUG__HW_00_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_01_DEBUG_MASK
- PB1_HW_DEBUG__HW_01_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_02_DEBUG_MASK
- PB1_HW_DEBUG__HW_02_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_03_DEBUG_MASK
- PB1_HW_DEBUG__HW_03_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_04_DEBUG_MASK
- PB1_HW_DEBUG__HW_04_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_05_DEBUG_MASK
- PB1_HW_DEBUG__HW_05_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_06_DEBUG_MASK
- PB1_HW_DEBUG__HW_06_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_07_DEBUG_MASK
- PB1_HW_DEBUG__HW_07_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_08_DEBUG_MASK
- PB1_HW_DEBUG__HW_08_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_09_DEBUG_MASK
- PB1_HW_DEBUG__HW_09_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_10_DEBUG_MASK
- PB1_HW_DEBUG__HW_10_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_11_DEBUG_MASK
- PB1_HW_DEBUG__HW_11_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_12_DEBUG_MASK
- PB1_HW_DEBUG__HW_12_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_13_DEBUG_MASK
- PB1_HW_DEBUG__HW_13_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_14_DEBUG_MASK
- PB1_HW_DEBUG__HW_14_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_15_DEBUG_MASK
- PB1_HW_DEBUG__HW_15_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_16_DEBUG_MASK
- PB1_HW_DEBUG__HW_16_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_17_DEBUG_MASK
- PB1_HW_DEBUG__HW_17_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_18_DEBUG_MASK
- PB1_HW_DEBUG__HW_18_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_19_DEBUG_MASK
- PB1_HW_DEBUG__HW_19_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_20_DEBUG_MASK
- PB1_HW_DEBUG__HW_20_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_21_DEBUG_MASK
- PB1_HW_DEBUG__HW_21_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_22_DEBUG_MASK
- PB1_HW_DEBUG__HW_22_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_23_DEBUG_MASK
- PB1_HW_DEBUG__HW_23_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_24_DEBUG_MASK
- PB1_HW_DEBUG__HW_24_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_25_DEBUG_MASK
- PB1_HW_DEBUG__HW_25_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_26_DEBUG_MASK
- PB1_HW_DEBUG__HW_26_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_27_DEBUG_MASK
- PB1_HW_DEBUG__HW_27_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_28_DEBUG_MASK
- PB1_HW_DEBUG__HW_28_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_29_DEBUG_MASK
- PB1_HW_DEBUG__HW_29_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_30_DEBUG_MASK
- PB1_HW_DEBUG__HW_30_DEBUG__SHIFT
- PB1_HW_DEBUG__HW_31_DEBUG_MASK
- PB1_HW_DEBUG__HW_31_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_00_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_00_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_01_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_01_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_02_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_02_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_03_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_03_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_04_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_04_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_05_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_05_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_06_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_06_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_07_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_07_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_08_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_08_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_09_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_09_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_10_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_10_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_11_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_11_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_12_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_12_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_13_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_13_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_14_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_14_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_15_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_15_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_16_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_16_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_17_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_17_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_18_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_18_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_19_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_19_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_20_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_20_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_21_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_21_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_22_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_22_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_23_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_23_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_24_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_24_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_25_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_25_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_26_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_26_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_27_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_27_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_28_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_28_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_29_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_29_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_30_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_30_DEBUG__SHIFT
- PB1_HW_DEBUG__PB1_HW_31_DEBUG_MASK
- PB1_HW_DEBUG__PB1_HW_31_DEBUG__SHIFT
- PB1_IN
- PB1_IOR_IN
- PB1_IOR_OUT
- PB1_OUT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK
- PB1_PIF_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK
- PB1_PIF_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK
- PB1_PIF_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK
- PB1_PIF_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT
- PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK
- PB1_PIF_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK
- PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT
- PB1_PIF_CMD_BUS_GLB_OVRD__TXMARG__SHIFT
- PB1_PIF_CNTL
- PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN_MASK
- PB1_PIF_CNTL2__LS2_EXIT_TIME_PRG_EN__SHIFT
- PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN_MASK
- PB1_PIF_CNTL2__PLL1_ALWAYS_ON_EN__SHIFT
- PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN_MASK
- PB1_PIF_CNTL2__PLL_RAMP_UP_TIME_PRG_EN__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_EN__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9_MASK
- PB1_PIF_CNTL2__RXDETECT_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_CNTL2__RXDETECT_PRG_EN_MASK
- PB1_PIF_CNTL2__RXDETECT_PRG_EN__SHIFT
- PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME_MASK
- PB1_PIF_CNTL2__RXDETECT_SAMPL_TIME__SHIFT
- PB1_PIF_CNTL2__RXPHYSTATUS_DELAY_MASK
- PB1_PIF_CNTL2__RXPHYSTATUS_DELAY__SHIFT
- PB1_PIF_CNTL2__RX_STAGGERING_DISABLE_MASK
- PB1_PIF_CNTL2__RX_STAGGERING_DISABLE__SHIFT
- PB1_PIF_CNTL2__RX_STAGGERING_MODE_MASK
- PB1_PIF_CNTL2__RX_STAGGERING_MODE__SHIFT
- PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN_MASK
- PB1_PIF_CNTL2__SERVICE2_STEP4_DELAY_PRG_EN__SHIFT
- PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN_MASK
- PB1_PIF_CNTL2__SERVICE3_STEP4_DELAY_PRG_EN__SHIFT
- PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN_MASK
- PB1_PIF_CNTL2__SPEEDCHANGE_STEP2_DELAY_PRG_EN__SHIFT
- PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN_MASK
- PB1_PIF_CNTL2__SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN__SHIFT
- PB1_PIF_CNTL__DA_FIFO_RESET_0_MASK
- PB1_PIF_CNTL__DA_FIFO_RESET_0__SHIFT
- PB1_PIF_CNTL__DA_FIFO_RESET_1_MASK
- PB1_PIF_CNTL__DA_FIFO_RESET_1__SHIFT
- PB1_PIF_CNTL__DA_FIFO_RESET_2_MASK
- PB1_PIF_CNTL__DA_FIFO_RESET_2__SHIFT
- PB1_PIF_CNTL__DA_FIFO_RESET_3_MASK
- PB1_PIF_CNTL__DA_FIFO_RESET_3__SHIFT
- PB1_PIF_CNTL__DIVINIT_ENABLE_MASK
- PB1_PIF_CNTL__DIVINIT_ENABLE__SHIFT
- PB1_PIF_CNTL__DIVINIT_MODE_MASK
- PB1_PIF_CNTL__DIVINIT_MODE__SHIFT
- PB1_PIF_CNTL__EI_CYCLE_OFF_TIME_MASK
- PB1_PIF_CNTL__EI_CYCLE_OFF_TIME__SHIFT
- PB1_PIF_CNTL__EI_DET_CYCLE_MODE_MASK
- PB1_PIF_CNTL__EI_DET_CYCLE_MODE__SHIFT
- PB1_PIF_CNTL__EXIT_L0S_INIT_DIS_MASK
- PB1_PIF_CNTL__EXIT_L0S_INIT_DIS__SHIFT
- PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP_MASK
- PB1_PIF_CNTL__EXTEND_WAIT_FOR_RAMPUP__SHIFT
- PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN_MASK
- PB1_PIF_CNTL__FORCE_TxFreqEquZeroinDTM_EN__SHIFT
- PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS_MASK
- PB1_PIF_CNTL__IGNORE_TxDataValid_EP_DIS__SHIFT
- PB1_PIF_CNTL__LS2_EXIT_TIME_MASK
- PB1_PIF_CNTL__LS2_EXIT_TIME__SHIFT
- PB1_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK
- PB1_PIF_CNTL__PHYCMD_CR_EN_MODE__SHIFT
- PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN_MASK
- PB1_PIF_CNTL__PHYRESPONSEMODE_ON_RXDET_EN__SHIFT
- PB1_PIF_CNTL__PHY_CR_EN_MODE_MASK
- PB1_PIF_CNTL__PHY_CR_EN_MODE__SHIFT
- PB1_PIF_CNTL__PLL0_IN_GEN3_MODE_MASK
- PB1_PIF_CNTL__PLL0_IN_GEN3_MODE__SHIFT
- PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK
- PB1_PIF_CNTL__PLL_BINDING_ENABLE__SHIFT
- PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE_MASK
- PB1_PIF_CNTL__RXDETECT_FIFO_RESET_MODE__SHIFT
- PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE_MASK
- PB1_PIF_CNTL__RXDETECT_TX_PWR_MODE__SHIFT
- PB1_PIF_CNTL__RXEN_GATER_MASK
- PB1_PIF_CNTL__RXEN_GATER__SHIFT
- PB1_PIF_CNTL__SC_CALIB_DONE_CNTL_MASK
- PB1_PIF_CNTL__SC_CALIB_DONE_CNTL__SHIFT
- PB1_PIF_CNTL__SERIAL_CFG_ENABLE_MASK
- PB1_PIF_CNTL__SERIAL_CFG_ENABLE__SHIFT
- PB1_PIF_CNTL__TXGND_TIME_MASK
- PB1_PIF_CNTL__TXGND_TIME__SHIFT
- PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1_MASK
- PB1_PIF_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT
- PB1_PIF_CTRL__PHY_RST_PWROK_VDD_MASK
- PB1_PIF_CTRL__PHY_RST_PWROK_VDD__SHIFT
- PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK
- PB1_PIF_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT
- PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK
- PB1_PIF_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT
- PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE_MASK
- PB1_PIF_CTRL__PIF_PG_ABORT_DISABLE__SHIFT
- PB1_PIF_CTRL__PIF_PG_EXIT_MODE_MASK
- PB1_PIF_CTRL__PIF_PG_EXIT_MODE__SHIFT
- PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK
- PB1_PIF_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT
- PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK
- PB1_PIF_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT
- PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK
- PB1_PIF_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT
- PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK
- PB1_PIF_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT
- PB1_PIF_CTRL__PIF_PLL_PWRDN_EN_MASK
- PB1_PIF_CTRL__PIF_PLL_PWRDN_EN__SHIFT
- PB1_PIF_CTRL__PIF_PLL_STATUS_MASK
- PB1_PIF_CTRL__PIF_PLL_STATUS__SHIFT
- PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK
- PB1_PIF_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT
- PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT
- PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK
- PB1_PIF_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK
- PB1_PIF_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_HW_DEBUG__HW_00_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_00_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_01_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_01_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_02_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_02_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_03_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_03_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_04_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_04_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_05_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_05_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_06_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_06_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_07_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_07_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_08_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_08_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_09_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_09_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_10_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_10_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_11_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_11_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_12_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_12_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_13_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_13_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_14_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_14_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__HW_15_DEBUG_MASK
- PB1_PIF_HW_DEBUG__HW_15_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_00_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_01_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_02_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_03_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_04_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_05_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_06_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_07_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_08_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_09_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_10_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_11_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_12_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_13_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_14_DEBUG__SHIFT
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG_MASK
- PB1_PIF_HW_DEBUG__PB1_PIF_HW_15_DEBUG__SHIFT
- PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0_MASK
- PB1_PIF_LANE0_OVRD2__COEFFICIENTID_0__SHIFT
- PB1_PIF_LANE0_OVRD2__COEFFICIENT_0_MASK
- PB1_PIF_LANE0_OVRD2__COEFFICIENT_0__SHIFT
- PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0_MASK
- PB1_PIF_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT
- PB1_PIF_LANE0_OVRD2__ENABLEFOM_0_MASK
- PB1_PIF_LANE0_OVRD2__ENABLEFOM_0__SHIFT
- PB1_PIF_LANE0_OVRD2__FREQDIV_0_MASK
- PB1_PIF_LANE0_OVRD2__FREQDIV_0__SHIFT
- PB1_PIF_LANE0_OVRD2__GANGMODE_0_MASK
- PB1_PIF_LANE0_OVRD2__GANGMODE_0__SHIFT
- PB1_PIF_LANE0_OVRD2__LINKSPEED_0_MASK
- PB1_PIF_LANE0_OVRD2__LINKSPEED_0__SHIFT
- PB1_PIF_LANE0_OVRD2__REQUESTFOM_0_MASK
- PB1_PIF_LANE0_OVRD2__REQUESTFOM_0__SHIFT
- PB1_PIF_LANE0_OVRD2__REQUESTTRK_0_MASK
- PB1_PIF_LANE0_OVRD2__REQUESTTRK_0__SHIFT
- PB1_PIF_LANE0_OVRD2__REQUESTTRN_0_MASK
- PB1_PIF_LANE0_OVRD2__REQUESTTRN_0__SHIFT
- PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0_MASK
- PB1_PIF_LANE0_OVRD2__RESPONSEMODE_0__SHIFT
- PB1_PIF_LANE0_OVRD2__RXPGENABLE_0_MASK
- PB1_PIF_LANE0_OVRD2__RXPGENABLE_0__SHIFT
- PB1_PIF_LANE0_OVRD2__RXPWR_0_MASK
- PB1_PIF_LANE0_OVRD2__RXPWR_0__SHIFT
- PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0_MASK
- PB1_PIF_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT
- PB1_PIF_LANE0_OVRD2__TXPGENABLE_0_MASK
- PB1_PIF_LANE0_OVRD2__TXPGENABLE_0__SHIFT
- PB1_PIF_LANE0_OVRD2__TXPWR_0_MASK
- PB1_PIF_LANE0_OVRD2__TXPWR_0__SHIFT
- PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK
- PB1_PIF_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT
- PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT
- PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK
- PB1_PIF_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT
- PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1_MASK
- PB1_PIF_LANE1_OVRD2__COEFFICIENTID_1__SHIFT
- PB1_PIF_LANE1_OVRD2__COEFFICIENT_1_MASK
- PB1_PIF_LANE1_OVRD2__COEFFICIENT_1__SHIFT
- PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1_MASK
- PB1_PIF_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT
- PB1_PIF_LANE1_OVRD2__ENABLEFOM_1_MASK
- PB1_PIF_LANE1_OVRD2__ENABLEFOM_1__SHIFT
- PB1_PIF_LANE1_OVRD2__FREQDIV_1_MASK
- PB1_PIF_LANE1_OVRD2__FREQDIV_1__SHIFT
- PB1_PIF_LANE1_OVRD2__GANGMODE_1_MASK
- PB1_PIF_LANE1_OVRD2__GANGMODE_1__SHIFT
- PB1_PIF_LANE1_OVRD2__LINKSPEED_1_MASK
- PB1_PIF_LANE1_OVRD2__LINKSPEED_1__SHIFT
- PB1_PIF_LANE1_OVRD2__REQUESTFOM_1_MASK
- PB1_PIF_LANE1_OVRD2__REQUESTFOM_1__SHIFT
- PB1_PIF_LANE1_OVRD2__REQUESTTRK_1_MASK
- PB1_PIF_LANE1_OVRD2__REQUESTTRK_1__SHIFT
- PB1_PIF_LANE1_OVRD2__REQUESTTRN_1_MASK
- PB1_PIF_LANE1_OVRD2__REQUESTTRN_1__SHIFT
- PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1_MASK
- PB1_PIF_LANE1_OVRD2__RESPONSEMODE_1__SHIFT
- PB1_PIF_LANE1_OVRD2__RXPGENABLE_1_MASK
- PB1_PIF_LANE1_OVRD2__RXPGENABLE_1__SHIFT
- PB1_PIF_LANE1_OVRD2__RXPWR_1_MASK
- PB1_PIF_LANE1_OVRD2__RXPWR_1__SHIFT
- PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1_MASK
- PB1_PIF_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT
- PB1_PIF_LANE1_OVRD2__TXPGENABLE_1_MASK
- PB1_PIF_LANE1_OVRD2__TXPGENABLE_1__SHIFT
- PB1_PIF_LANE1_OVRD2__TXPWR_1_MASK
- PB1_PIF_LANE1_OVRD2__TXPWR_1__SHIFT
- PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK
- PB1_PIF_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT
- PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT
- PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK
- PB1_PIF_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT
- PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2_MASK
- PB1_PIF_LANE2_OVRD2__COEFFICIENTID_2__SHIFT
- PB1_PIF_LANE2_OVRD2__COEFFICIENT_2_MASK
- PB1_PIF_LANE2_OVRD2__COEFFICIENT_2__SHIFT
- PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2_MASK
- PB1_PIF_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT
- PB1_PIF_LANE2_OVRD2__ENABLEFOM_2_MASK
- PB1_PIF_LANE2_OVRD2__ENABLEFOM_2__SHIFT
- PB1_PIF_LANE2_OVRD2__FREQDIV_2_MASK
- PB1_PIF_LANE2_OVRD2__FREQDIV_2__SHIFT
- PB1_PIF_LANE2_OVRD2__GANGMODE_2_MASK
- PB1_PIF_LANE2_OVRD2__GANGMODE_2__SHIFT
- PB1_PIF_LANE2_OVRD2__LINKSPEED_2_MASK
- PB1_PIF_LANE2_OVRD2__LINKSPEED_2__SHIFT
- PB1_PIF_LANE2_OVRD2__REQUESTFOM_2_MASK
- PB1_PIF_LANE2_OVRD2__REQUESTFOM_2__SHIFT
- PB1_PIF_LANE2_OVRD2__REQUESTTRK_2_MASK
- PB1_PIF_LANE2_OVRD2__REQUESTTRK_2__SHIFT
- PB1_PIF_LANE2_OVRD2__REQUESTTRN_2_MASK
- PB1_PIF_LANE2_OVRD2__REQUESTTRN_2__SHIFT
- PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2_MASK
- PB1_PIF_LANE2_OVRD2__RESPONSEMODE_2__SHIFT
- PB1_PIF_LANE2_OVRD2__RXPGENABLE_2_MASK
- PB1_PIF_LANE2_OVRD2__RXPGENABLE_2__SHIFT
- PB1_PIF_LANE2_OVRD2__RXPWR_2_MASK
- PB1_PIF_LANE2_OVRD2__RXPWR_2__SHIFT
- PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2_MASK
- PB1_PIF_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT
- PB1_PIF_LANE2_OVRD2__TXPGENABLE_2_MASK
- PB1_PIF_LANE2_OVRD2__TXPGENABLE_2__SHIFT
- PB1_PIF_LANE2_OVRD2__TXPWR_2_MASK
- PB1_PIF_LANE2_OVRD2__TXPWR_2__SHIFT
- PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK
- PB1_PIF_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT
- PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT
- PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK
- PB1_PIF_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT
- PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3_MASK
- PB1_PIF_LANE3_OVRD2__COEFFICIENTID_3__SHIFT
- PB1_PIF_LANE3_OVRD2__COEFFICIENT_3_MASK
- PB1_PIF_LANE3_OVRD2__COEFFICIENT_3__SHIFT
- PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3_MASK
- PB1_PIF_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT
- PB1_PIF_LANE3_OVRD2__ENABLEFOM_3_MASK
- PB1_PIF_LANE3_OVRD2__ENABLEFOM_3__SHIFT
- PB1_PIF_LANE3_OVRD2__FREQDIV_3_MASK
- PB1_PIF_LANE3_OVRD2__FREQDIV_3__SHIFT
- PB1_PIF_LANE3_OVRD2__GANGMODE_3_MASK
- PB1_PIF_LANE3_OVRD2__GANGMODE_3__SHIFT
- PB1_PIF_LANE3_OVRD2__LINKSPEED_3_MASK
- PB1_PIF_LANE3_OVRD2__LINKSPEED_3__SHIFT
- PB1_PIF_LANE3_OVRD2__REQUESTFOM_3_MASK
- PB1_PIF_LANE3_OVRD2__REQUESTFOM_3__SHIFT
- PB1_PIF_LANE3_OVRD2__REQUESTTRK_3_MASK
- PB1_PIF_LANE3_OVRD2__REQUESTTRK_3__SHIFT
- PB1_PIF_LANE3_OVRD2__REQUESTTRN_3_MASK
- PB1_PIF_LANE3_OVRD2__REQUESTTRN_3__SHIFT
- PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3_MASK
- PB1_PIF_LANE3_OVRD2__RESPONSEMODE_3__SHIFT
- PB1_PIF_LANE3_OVRD2__RXPGENABLE_3_MASK
- PB1_PIF_LANE3_OVRD2__RXPGENABLE_3__SHIFT
- PB1_PIF_LANE3_OVRD2__RXPWR_3_MASK
- PB1_PIF_LANE3_OVRD2__RXPWR_3__SHIFT
- PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3_MASK
- PB1_PIF_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT
- PB1_PIF_LANE3_OVRD2__TXPGENABLE_3_MASK
- PB1_PIF_LANE3_OVRD2__TXPGENABLE_3__SHIFT
- PB1_PIF_LANE3_OVRD2__TXPWR_3_MASK
- PB1_PIF_LANE3_OVRD2__TXPWR_3__SHIFT
- PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK
- PB1_PIF_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT
- PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT
- PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK
- PB1_PIF_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT
- PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4_MASK
- PB1_PIF_LANE4_OVRD2__COEFFICIENTID_4__SHIFT
- PB1_PIF_LANE4_OVRD2__COEFFICIENT_4_MASK
- PB1_PIF_LANE4_OVRD2__COEFFICIENT_4__SHIFT
- PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4_MASK
- PB1_PIF_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT
- PB1_PIF_LANE4_OVRD2__ENABLEFOM_4_MASK
- PB1_PIF_LANE4_OVRD2__ENABLEFOM_4__SHIFT
- PB1_PIF_LANE4_OVRD2__FREQDIV_4_MASK
- PB1_PIF_LANE4_OVRD2__FREQDIV_4__SHIFT
- PB1_PIF_LANE4_OVRD2__GANGMODE_4_MASK
- PB1_PIF_LANE4_OVRD2__GANGMODE_4__SHIFT
- PB1_PIF_LANE4_OVRD2__LINKSPEED_4_MASK
- PB1_PIF_LANE4_OVRD2__LINKSPEED_4__SHIFT
- PB1_PIF_LANE4_OVRD2__REQUESTFOM_4_MASK
- PB1_PIF_LANE4_OVRD2__REQUESTFOM_4__SHIFT
- PB1_PIF_LANE4_OVRD2__REQUESTTRK_4_MASK
- PB1_PIF_LANE4_OVRD2__REQUESTTRK_4__SHIFT
- PB1_PIF_LANE4_OVRD2__REQUESTTRN_4_MASK
- PB1_PIF_LANE4_OVRD2__REQUESTTRN_4__SHIFT
- PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4_MASK
- PB1_PIF_LANE4_OVRD2__RESPONSEMODE_4__SHIFT
- PB1_PIF_LANE4_OVRD2__RXPGENABLE_4_MASK
- PB1_PIF_LANE4_OVRD2__RXPGENABLE_4__SHIFT
- PB1_PIF_LANE4_OVRD2__RXPWR_4_MASK
- PB1_PIF_LANE4_OVRD2__RXPWR_4__SHIFT
- PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4_MASK
- PB1_PIF_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT
- PB1_PIF_LANE4_OVRD2__TXPGENABLE_4_MASK
- PB1_PIF_LANE4_OVRD2__TXPGENABLE_4__SHIFT
- PB1_PIF_LANE4_OVRD2__TXPWR_4_MASK
- PB1_PIF_LANE4_OVRD2__TXPWR_4__SHIFT
- PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK
- PB1_PIF_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT
- PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT
- PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK
- PB1_PIF_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT
- PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5_MASK
- PB1_PIF_LANE5_OVRD2__COEFFICIENTID_5__SHIFT
- PB1_PIF_LANE5_OVRD2__COEFFICIENT_5_MASK
- PB1_PIF_LANE5_OVRD2__COEFFICIENT_5__SHIFT
- PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5_MASK
- PB1_PIF_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT
- PB1_PIF_LANE5_OVRD2__ENABLEFOM_5_MASK
- PB1_PIF_LANE5_OVRD2__ENABLEFOM_5__SHIFT
- PB1_PIF_LANE5_OVRD2__FREQDIV_5_MASK
- PB1_PIF_LANE5_OVRD2__FREQDIV_5__SHIFT
- PB1_PIF_LANE5_OVRD2__GANGMODE_5_MASK
- PB1_PIF_LANE5_OVRD2__GANGMODE_5__SHIFT
- PB1_PIF_LANE5_OVRD2__LINKSPEED_5_MASK
- PB1_PIF_LANE5_OVRD2__LINKSPEED_5__SHIFT
- PB1_PIF_LANE5_OVRD2__REQUESTFOM_5_MASK
- PB1_PIF_LANE5_OVRD2__REQUESTFOM_5__SHIFT
- PB1_PIF_LANE5_OVRD2__REQUESTTRK_5_MASK
- PB1_PIF_LANE5_OVRD2__REQUESTTRK_5__SHIFT
- PB1_PIF_LANE5_OVRD2__REQUESTTRN_5_MASK
- PB1_PIF_LANE5_OVRD2__REQUESTTRN_5__SHIFT
- PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5_MASK
- PB1_PIF_LANE5_OVRD2__RESPONSEMODE_5__SHIFT
- PB1_PIF_LANE5_OVRD2__RXPGENABLE_5_MASK
- PB1_PIF_LANE5_OVRD2__RXPGENABLE_5__SHIFT
- PB1_PIF_LANE5_OVRD2__RXPWR_5_MASK
- PB1_PIF_LANE5_OVRD2__RXPWR_5__SHIFT
- PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5_MASK
- PB1_PIF_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT
- PB1_PIF_LANE5_OVRD2__TXPGENABLE_5_MASK
- PB1_PIF_LANE5_OVRD2__TXPGENABLE_5__SHIFT
- PB1_PIF_LANE5_OVRD2__TXPWR_5_MASK
- PB1_PIF_LANE5_OVRD2__TXPWR_5__SHIFT
- PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK
- PB1_PIF_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT
- PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT
- PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK
- PB1_PIF_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT
- PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6_MASK
- PB1_PIF_LANE6_OVRD2__COEFFICIENTID_6__SHIFT
- PB1_PIF_LANE6_OVRD2__COEFFICIENT_6_MASK
- PB1_PIF_LANE6_OVRD2__COEFFICIENT_6__SHIFT
- PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6_MASK
- PB1_PIF_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT
- PB1_PIF_LANE6_OVRD2__ENABLEFOM_6_MASK
- PB1_PIF_LANE6_OVRD2__ENABLEFOM_6__SHIFT
- PB1_PIF_LANE6_OVRD2__FREQDIV_6_MASK
- PB1_PIF_LANE6_OVRD2__FREQDIV_6__SHIFT
- PB1_PIF_LANE6_OVRD2__GANGMODE_6_MASK
- PB1_PIF_LANE6_OVRD2__GANGMODE_6__SHIFT
- PB1_PIF_LANE6_OVRD2__LINKSPEED_6_MASK
- PB1_PIF_LANE6_OVRD2__LINKSPEED_6__SHIFT
- PB1_PIF_LANE6_OVRD2__REQUESTFOM_6_MASK
- PB1_PIF_LANE6_OVRD2__REQUESTFOM_6__SHIFT
- PB1_PIF_LANE6_OVRD2__REQUESTTRK_6_MASK
- PB1_PIF_LANE6_OVRD2__REQUESTTRK_6__SHIFT
- PB1_PIF_LANE6_OVRD2__REQUESTTRN_6_MASK
- PB1_PIF_LANE6_OVRD2__REQUESTTRN_6__SHIFT
- PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6_MASK
- PB1_PIF_LANE6_OVRD2__RESPONSEMODE_6__SHIFT
- PB1_PIF_LANE6_OVRD2__RXPGENABLE_6_MASK
- PB1_PIF_LANE6_OVRD2__RXPGENABLE_6__SHIFT
- PB1_PIF_LANE6_OVRD2__RXPWR_6_MASK
- PB1_PIF_LANE6_OVRD2__RXPWR_6__SHIFT
- PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6_MASK
- PB1_PIF_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT
- PB1_PIF_LANE6_OVRD2__TXPGENABLE_6_MASK
- PB1_PIF_LANE6_OVRD2__TXPGENABLE_6__SHIFT
- PB1_PIF_LANE6_OVRD2__TXPWR_6_MASK
- PB1_PIF_LANE6_OVRD2__TXPWR_6__SHIFT
- PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK
- PB1_PIF_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT
- PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT
- PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK
- PB1_PIF_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT
- PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7_MASK
- PB1_PIF_LANE7_OVRD2__COEFFICIENTID_7__SHIFT
- PB1_PIF_LANE7_OVRD2__COEFFICIENT_7_MASK
- PB1_PIF_LANE7_OVRD2__COEFFICIENT_7__SHIFT
- PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7_MASK
- PB1_PIF_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT
- PB1_PIF_LANE7_OVRD2__ENABLEFOM_7_MASK
- PB1_PIF_LANE7_OVRD2__ENABLEFOM_7__SHIFT
- PB1_PIF_LANE7_OVRD2__FREQDIV_7_MASK
- PB1_PIF_LANE7_OVRD2__FREQDIV_7__SHIFT
- PB1_PIF_LANE7_OVRD2__GANGMODE_7_MASK
- PB1_PIF_LANE7_OVRD2__GANGMODE_7__SHIFT
- PB1_PIF_LANE7_OVRD2__LINKSPEED_7_MASK
- PB1_PIF_LANE7_OVRD2__LINKSPEED_7__SHIFT
- PB1_PIF_LANE7_OVRD2__REQUESTFOM_7_MASK
- PB1_PIF_LANE7_OVRD2__REQUESTFOM_7__SHIFT
- PB1_PIF_LANE7_OVRD2__REQUESTTRK_7_MASK
- PB1_PIF_LANE7_OVRD2__REQUESTTRK_7__SHIFT
- PB1_PIF_LANE7_OVRD2__REQUESTTRN_7_MASK
- PB1_PIF_LANE7_OVRD2__REQUESTTRN_7__SHIFT
- PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7_MASK
- PB1_PIF_LANE7_OVRD2__RESPONSEMODE_7__SHIFT
- PB1_PIF_LANE7_OVRD2__RXPGENABLE_7_MASK
- PB1_PIF_LANE7_OVRD2__RXPGENABLE_7__SHIFT
- PB1_PIF_LANE7_OVRD2__RXPWR_7_MASK
- PB1_PIF_LANE7_OVRD2__RXPWR_7__SHIFT
- PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7_MASK
- PB1_PIF_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT
- PB1_PIF_LANE7_OVRD2__TXPGENABLE_7_MASK
- PB1_PIF_LANE7_OVRD2__TXPGENABLE_7__SHIFT
- PB1_PIF_LANE7_OVRD2__TXPWR_7_MASK
- PB1_PIF_LANE7_OVRD2__TXPWR_7__SHIFT
- PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK
- PB1_PIF_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT
- PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT
- PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK
- PB1_PIF_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT
- PB1_PIF_PAIRING
- PB1_PIF_PAIRING__MULTI_PIF_MASK
- PB1_PIF_PAIRING__MULTI_PIF__SHIFT
- PB1_PIF_PAIRING__X16_LANE_15_0_MASK
- PB1_PIF_PAIRING__X16_LANE_15_0__SHIFT
- PB1_PIF_PAIRING__X2_LANE_11_10_MASK
- PB1_PIF_PAIRING__X2_LANE_11_10__SHIFT
- PB1_PIF_PAIRING__X2_LANE_13_12_MASK
- PB1_PIF_PAIRING__X2_LANE_13_12__SHIFT
- PB1_PIF_PAIRING__X2_LANE_15_14_MASK
- PB1_PIF_PAIRING__X2_LANE_15_14__SHIFT
- PB1_PIF_PAIRING__X2_LANE_1_0_MASK
- PB1_PIF_PAIRING__X2_LANE_1_0__SHIFT
- PB1_PIF_PAIRING__X2_LANE_3_2_MASK
- PB1_PIF_PAIRING__X2_LANE_3_2__SHIFT
- PB1_PIF_PAIRING__X2_LANE_5_4_MASK
- PB1_PIF_PAIRING__X2_LANE_5_4__SHIFT
- PB1_PIF_PAIRING__X2_LANE_7_6_MASK
- PB1_PIF_PAIRING__X2_LANE_7_6__SHIFT
- PB1_PIF_PAIRING__X2_LANE_9_8_MASK
- PB1_PIF_PAIRING__X2_LANE_9_8__SHIFT
- PB1_PIF_PAIRING__X4_LANE_11_8_MASK
- PB1_PIF_PAIRING__X4_LANE_11_8__SHIFT
- PB1_PIF_PAIRING__X4_LANE_15_12_MASK
- PB1_PIF_PAIRING__X4_LANE_15_12__SHIFT
- PB1_PIF_PAIRING__X4_LANE_3_0_MASK
- PB1_PIF_PAIRING__X4_LANE_3_0__SHIFT
- PB1_PIF_PAIRING__X4_LANE_7_4_MASK
- PB1_PIF_PAIRING__X4_LANE_7_4__SHIFT
- PB1_PIF_PAIRING__X8_LANE_15_8_MASK
- PB1_PIF_PAIRING__X8_LANE_15_8__SHIFT
- PB1_PIF_PAIRING__X8_LANE_7_0_MASK
- PB1_PIF_PAIRING__X8_LANE_7_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RXEN_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RXPWR_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__RX_PDNB_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__TXPWR_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0_MASK
- PB1_PIF_PDNB_OVERRIDE_0__TX_PDNB_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_EN_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RXEN_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_EN_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RXPWR_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_EN_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__RX_PDNB_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_EN_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__TXPWR_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_EN_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10_MASK
- PB1_PIF_PDNB_OVERRIDE_10__TX_PDNB_OVERRIDE_VAL_10__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_EN_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RXEN_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_EN_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RXPWR_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_EN_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__RX_PDNB_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_EN_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__TXPWR_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_EN_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11_MASK
- PB1_PIF_PDNB_OVERRIDE_11__TX_PDNB_OVERRIDE_VAL_11__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_EN_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RXEN_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_EN_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RXPWR_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_EN_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__RX_PDNB_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_EN_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__TXPWR_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_EN_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12_MASK
- PB1_PIF_PDNB_OVERRIDE_12__TX_PDNB_OVERRIDE_VAL_12__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_EN_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RXEN_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_EN_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RXPWR_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_EN_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__RX_PDNB_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_EN_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__TXPWR_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_EN_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13_MASK
- PB1_PIF_PDNB_OVERRIDE_13__TX_PDNB_OVERRIDE_VAL_13__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_EN_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RXEN_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_EN_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RXPWR_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_EN_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__RX_PDNB_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_EN_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__TXPWR_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_EN_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14_MASK
- PB1_PIF_PDNB_OVERRIDE_14__TX_PDNB_OVERRIDE_VAL_14__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_EN_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RXEN_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_EN_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RXPWR_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_EN_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__RX_PDNB_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_EN_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__TXPWR_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_EN_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15_MASK
- PB1_PIF_PDNB_OVERRIDE_15__TX_PDNB_OVERRIDE_VAL_15__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RXEN_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RXPWR_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__RX_PDNB_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__TXPWR_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1_MASK
- PB1_PIF_PDNB_OVERRIDE_1__TX_PDNB_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RXEN_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RXPWR_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__RX_PDNB_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__TXPWR_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2_MASK
- PB1_PIF_PDNB_OVERRIDE_2__TX_PDNB_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RXEN_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RXPWR_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__RX_PDNB_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__TXPWR_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3_MASK
- PB1_PIF_PDNB_OVERRIDE_3__TX_PDNB_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_EN_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RXEN_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_EN_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RXPWR_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_EN_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__RX_PDNB_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_EN_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__TXPWR_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_EN_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4_MASK
- PB1_PIF_PDNB_OVERRIDE_4__TX_PDNB_OVERRIDE_VAL_4__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_EN_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RXEN_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_EN_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RXPWR_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_EN_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__RX_PDNB_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_EN_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__TXPWR_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_EN_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5_MASK
- PB1_PIF_PDNB_OVERRIDE_5__TX_PDNB_OVERRIDE_VAL_5__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_EN_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RXEN_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_EN_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RXPWR_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_EN_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__RX_PDNB_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_EN_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__TXPWR_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_EN_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6_MASK
- PB1_PIF_PDNB_OVERRIDE_6__TX_PDNB_OVERRIDE_VAL_6__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_EN_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RXEN_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_EN_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RXPWR_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_EN_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__RX_PDNB_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_EN_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__TXPWR_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_EN_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7_MASK
- PB1_PIF_PDNB_OVERRIDE_7__TX_PDNB_OVERRIDE_VAL_7__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_EN_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RXEN_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_EN_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RXPWR_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_EN_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__RX_PDNB_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_EN_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__TXPWR_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_EN_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8_MASK
- PB1_PIF_PDNB_OVERRIDE_8__TX_PDNB_OVERRIDE_VAL_8__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_EN_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RXEN_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_EN_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RXPWR_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_EN_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__RX_PDNB_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_EN_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__TXPWR_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_EN_9__SHIFT
- PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9_MASK
- PB1_PIF_PDNB_OVERRIDE_9__TX_PDNB_OVERRIDE_VAL_9__SHIFT
- PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME_MASK
- PB1_PIF_PRG0__PRG_RXDETECT_SAMPL_TIME__SHIFT
- PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME_MASK
- PB1_PIF_PRG1__PRG_PLL_RAMP_UP_TIME__SHIFT
- PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY_MASK
- PB1_PIF_PRG2__PRG_SERVICE2_STEP4_DELAY__SHIFT
- PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY_MASK
- PB1_PIF_PRG3__PRG_SERVICE3_STEP4_DELAY__SHIFT
- PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY_MASK
- PB1_PIF_PRG4__PRG_SPEEDCHANGE_STEP2_DELAY__SHIFT
- PB1_PIF_PRG5__PRG_LS2_EXIT_TIME_MASK
- PB1_PIF_PRG5__PRG_LS2_EXIT_TIME__SHIFT
- PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY_MASK
- PB1_PIF_PRG6__PRG_SPEEDCHANGE_STEP4_DELAY__SHIFT
- PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY_MASK
- PB1_PIF_PRG7__PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY__SHIFT
- PB1_PIF_PWRDOWN_0
- PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0_MASK
- PB1_PIF_PWRDOWN_0__FORCE_RXEN_IN_L0s_0__SHIFT
- PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0_MASK
- PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_EN_0__SHIFT
- PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0_MASK
- PB1_PIF_PWRDOWN_0__PLLPWR_OVERRIDE_VAL_0__SHIFT
- PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK
- PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT
- PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK
- PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT
- PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0_MASK
- PB1_PIF_PWRDOWN_0__PLL_RAMP_UP_TIME_0__SHIFT
- PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0_MASK
- PB1_PIF_PWRDOWN_0__RX_POWER_STATE_IN_RXS2_0__SHIFT
- PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0_MASK
- PB1_PIF_PWRDOWN_0__TX2P5CLK_CLOCK_GATING_EN_0__SHIFT
- PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0_MASK
- PB1_PIF_PWRDOWN_0__TX_POWER_STATE_IN_TXS2_0__SHIFT
- PB1_PIF_PWRDOWN_1
- PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1_MASK
- PB1_PIF_PWRDOWN_1__FORCE_RXEN_IN_L0s_1__SHIFT
- PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1_MASK
- PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_EN_1__SHIFT
- PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1_MASK
- PB1_PIF_PWRDOWN_1__PLLPWR_OVERRIDE_VAL_1__SHIFT
- PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK
- PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT
- PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK
- PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT
- PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1_MASK
- PB1_PIF_PWRDOWN_1__PLL_RAMP_UP_TIME_1__SHIFT
- PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1_MASK
- PB1_PIF_PWRDOWN_1__RX_POWER_STATE_IN_RXS2_1__SHIFT
- PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1_MASK
- PB1_PIF_PWRDOWN_1__TX2P5CLK_CLOCK_GATING_EN_1__SHIFT
- PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1_MASK
- PB1_PIF_PWRDOWN_1__TX_POWER_STATE_IN_TXS2_1__SHIFT
- PB1_PIF_PWRDOWN_2
- PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2_MASK
- PB1_PIF_PWRDOWN_2__FORCE_RXEN_IN_L0s_2__SHIFT
- PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2_MASK
- PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_EN_2__SHIFT
- PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2_MASK
- PB1_PIF_PWRDOWN_2__PLLPWR_OVERRIDE_VAL_2__SHIFT
- PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2_MASK
- PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_OFF_2__SHIFT
- PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2_MASK
- PB1_PIF_PWRDOWN_2__PLL_POWER_STATE_IN_TXS2_2__SHIFT
- PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2_MASK
- PB1_PIF_PWRDOWN_2__PLL_RAMP_UP_TIME_2__SHIFT
- PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2_MASK
- PB1_PIF_PWRDOWN_2__RX_POWER_STATE_IN_RXS2_2__SHIFT
- PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2_MASK
- PB1_PIF_PWRDOWN_2__TX2P5CLK_CLOCK_GATING_EN_2__SHIFT
- PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2_MASK
- PB1_PIF_PWRDOWN_2__TX_POWER_STATE_IN_TXS2_2__SHIFT
- PB1_PIF_PWRDOWN_3
- PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3_MASK
- PB1_PIF_PWRDOWN_3__FORCE_RXEN_IN_L0s_3__SHIFT
- PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3_MASK
- PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_EN_3__SHIFT
- PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3_MASK
- PB1_PIF_PWRDOWN_3__PLLPWR_OVERRIDE_VAL_3__SHIFT
- PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3_MASK
- PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_OFF_3__SHIFT
- PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3_MASK
- PB1_PIF_PWRDOWN_3__PLL_POWER_STATE_IN_TXS2_3__SHIFT
- PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3_MASK
- PB1_PIF_PWRDOWN_3__PLL_RAMP_UP_TIME_3__SHIFT
- PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3_MASK
- PB1_PIF_PWRDOWN_3__RX_POWER_STATE_IN_RXS2_3__SHIFT
- PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3_MASK
- PB1_PIF_PWRDOWN_3__TX2P5CLK_CLOCK_GATING_EN_3__SHIFT
- PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3_MASK
- PB1_PIF_PWRDOWN_3__TX_POWER_STATE_IN_TXS2_3__SHIFT
- PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK
- PB1_PIF_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT
- PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE_MASK
- PB1_PIF_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT
- PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME_MASK
- PB1_PIF_RX_CTRL2__EI_DET_OFF_TIME__SHIFT
- PB1_PIF_RX_CTRL2__EI_DET_ON_TIME_MASK
- PB1_PIF_RX_CTRL2__EI_DET_ON_TIME__SHIFT
- PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK
- PB1_PIF_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT
- PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY_MASK
- PB1_PIF_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT
- PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE_MASK
- PB1_PIF_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT
- PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK
- PB1_PIF_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT
- PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK
- PB1_PIF_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT
- PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK
- PB1_PIF_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK
- PB1_PIF_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT
- PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK
- PB1_PIF_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1_MASK
- PB1_PIF_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK
- PB1_PIF_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_INIT_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_INIT__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_OFF_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_OFF__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_S2_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_S2__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK
- PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT
- PB1_PIF_RX_CTRL__RXPWR_IN_UNUSED__SHIFT
- PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK
- PB1_PIF_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT
- PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT_MASK
- PB1_PIF_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT
- PB1_PIF_SCRATCH__PIF_SCRATCH_MASK
- PB1_PIF_SCRATCH__PIF_SCRATCH__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_0__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_10__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_11__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_12__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_13__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_14__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_15__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_1__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_2__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_3__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_4__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_5__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_6__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_7__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_8__SHIFT
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9_MASK
- PB1_PIF_SC_CTL2__SERIAL_CFG_PERLANE_DISABLE_9__SHIFT
- PB1_PIF_SC_CTL__SC_CALIBRATION_MASK
- PB1_PIF_SC_CTL__SC_CALIBRATION__SHIFT
- PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK
- PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S__SHIFT
- PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK
- PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0__SHIFT
- PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S_MASK
- PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0S__SHIFT
- PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0_MASK
- PB1_PIF_SC_CTL__SC_EXIT_L1_TO_L0__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_0_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_10_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_10_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_11_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_11_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_12_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_12_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_13_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_13_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_14_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_14_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_15_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_15_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_1_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_1_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_2_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_2_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_3_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_3_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_4_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_4_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_5_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_6_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_6_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_7_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_7_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_8_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_8_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_LANE_9_RESUME_MASK
- PB1_PIF_SC_CTL__SC_LANE_9_RESUME__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_1_MASK
- PB1_PIF_SC_CTL__SC_PHASE_1__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_2_MASK
- PB1_PIF_SC_CTL__SC_PHASE_2__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_3_MASK
- PB1_PIF_SC_CTL__SC_PHASE_3__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_4_MASK
- PB1_PIF_SC_CTL__SC_PHASE_4__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_5_MASK
- PB1_PIF_SC_CTL__SC_PHASE_5__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_6_MASK
- PB1_PIF_SC_CTL__SC_PHASE_6__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_7_MASK
- PB1_PIF_SC_CTL__SC_PHASE_7__SHIFT
- PB1_PIF_SC_CTL__SC_PHASE_8_MASK
- PB1_PIF_SC_CTL__SC_PHASE_8__SHIFT
- PB1_PIF_SC_CTL__SC_RXDETECT_MASK
- PB1_PIF_SC_CTL__SC_RXDETECT__SHIFT
- PB1_PIF_SC_CTL__SC_SPEED_CHANGE_MASK
- PB1_PIF_SC_CTL__SC_SPEED_CHANGE__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_CALIBRATION_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0S_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_ENTER_L1_FROM_L0_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0S_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_EXIT_L1_TO_L0_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_PHASE_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_RXDETECT_0__SHIFT
- PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0_MASK
- PB1_PIF_SEQ_STATUS_0__SEQ_SPEED_CHANGE_0__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_CALIBRATION_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0S_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_ENTER_L1_FROM_L0_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0S_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_EXIT_L1_TO_L0_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_PHASE_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_RXDETECT_10__SHIFT
- PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10_MASK
- PB1_PIF_SEQ_STATUS_10__SEQ_SPEED_CHANGE_10__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_CALIBRATION_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0S_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_ENTER_L1_FROM_L0_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0S_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_EXIT_L1_TO_L0_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_PHASE_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_RXDETECT_11__SHIFT
- PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11_MASK
- PB1_PIF_SEQ_STATUS_11__SEQ_SPEED_CHANGE_11__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_CALIBRATION_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0S_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_ENTER_L1_FROM_L0_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0S_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_EXIT_L1_TO_L0_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_PHASE_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_RXDETECT_12__SHIFT
- PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12_MASK
- PB1_PIF_SEQ_STATUS_12__SEQ_SPEED_CHANGE_12__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_CALIBRATION_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0S_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_ENTER_L1_FROM_L0_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0S_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_EXIT_L1_TO_L0_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_PHASE_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_RXDETECT_13__SHIFT
- PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13_MASK
- PB1_PIF_SEQ_STATUS_13__SEQ_SPEED_CHANGE_13__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_CALIBRATION_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0S_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_ENTER_L1_FROM_L0_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0S_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_EXIT_L1_TO_L0_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_PHASE_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_RXDETECT_14__SHIFT
- PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14_MASK
- PB1_PIF_SEQ_STATUS_14__SEQ_SPEED_CHANGE_14__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_CALIBRATION_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0S_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_ENTER_L1_FROM_L0_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0S_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_EXIT_L1_TO_L0_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_PHASE_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_RXDETECT_15__SHIFT
- PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15_MASK
- PB1_PIF_SEQ_STATUS_15__SEQ_SPEED_CHANGE_15__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_CALIBRATION_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0S_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_ENTER_L1_FROM_L0_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0S_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_EXIT_L1_TO_L0_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_PHASE_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_RXDETECT_1__SHIFT
- PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1_MASK
- PB1_PIF_SEQ_STATUS_1__SEQ_SPEED_CHANGE_1__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_CALIBRATION_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0S_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_ENTER_L1_FROM_L0_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0S_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_EXIT_L1_TO_L0_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_PHASE_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_RXDETECT_2__SHIFT
- PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2_MASK
- PB1_PIF_SEQ_STATUS_2__SEQ_SPEED_CHANGE_2__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_CALIBRATION_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0S_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_ENTER_L1_FROM_L0_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0S_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_EXIT_L1_TO_L0_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_PHASE_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_RXDETECT_3__SHIFT
- PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3_MASK
- PB1_PIF_SEQ_STATUS_3__SEQ_SPEED_CHANGE_3__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_CALIBRATION_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0S_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_ENTER_L1_FROM_L0_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0S_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_EXIT_L1_TO_L0_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_PHASE_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_RXDETECT_4__SHIFT
- PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4_MASK
- PB1_PIF_SEQ_STATUS_4__SEQ_SPEED_CHANGE_4__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_CALIBRATION_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0S_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_ENTER_L1_FROM_L0_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0S_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_EXIT_L1_TO_L0_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_PHASE_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_RXDETECT_5__SHIFT
- PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5_MASK
- PB1_PIF_SEQ_STATUS_5__SEQ_SPEED_CHANGE_5__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_CALIBRATION_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0S_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_ENTER_L1_FROM_L0_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0S_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_EXIT_L1_TO_L0_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_PHASE_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_RXDETECT_6__SHIFT
- PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6_MASK
- PB1_PIF_SEQ_STATUS_6__SEQ_SPEED_CHANGE_6__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_CALIBRATION_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0S_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_ENTER_L1_FROM_L0_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0S_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_EXIT_L1_TO_L0_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_PHASE_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_RXDETECT_7__SHIFT
- PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7_MASK
- PB1_PIF_SEQ_STATUS_7__SEQ_SPEED_CHANGE_7__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_CALIBRATION_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0S_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_ENTER_L1_FROM_L0_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0S_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_EXIT_L1_TO_L0_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_PHASE_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_RXDETECT_8__SHIFT
- PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8_MASK
- PB1_PIF_SEQ_STATUS_8__SEQ_SPEED_CHANGE_8__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_CALIBRATION_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0S_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_ENTER_L1_FROM_L0_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0S_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_EXIT_L1_TO_L0_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_PHASE_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_RXDETECT_9__SHIFT
- PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9_MASK
- PB1_PIF_SEQ_STATUS_9__SEQ_SPEED_CHANGE_9__SHIFT
- PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK
- PB1_PIF_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_12_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_12__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_13_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_13__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_14_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_14__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_15_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_15__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_16_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_BIT_16__SHIFT
- PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK
- PB1_PIF_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT
- PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK
- PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT
- PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK
- PB1_PIF_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT
- PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER_MASK
- PB1_PIF_STRAP_0__STRAP_RX_EI_FILTER__SHIFT
- PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK
- PB1_PIF_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT
- PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK
- PB1_PIF_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT
- PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK
- PB1_PIF_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT
- PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK
- PB1_PIF_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_0__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_10__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_11__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_12__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_13__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_14__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_15__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_1__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_2__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_3__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_4__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_5__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_6__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_7__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_8__SHIFT
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9_MASK
- PB1_PIF_TXPHYSTATUS__TXPHYSTATUS_9__SHIFT
- PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY_MASK
- PB1_PIF_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT
- PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK
- PB1_PIF_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT
- PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK
- PB1_PIF_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT
- PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID_MASK
- PB1_PIF_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT
- PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK
- PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT
- PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK
- PB1_PIF_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT
- PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK
- PB1_PIF_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT
- PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK
- PB1_PIF_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT
- PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK
- PB1_PIF_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT
- PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK
- PB1_PIF_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT
- PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK
- PB1_PIF_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK
- PB1_PIF_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT
- PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK
- PB1_PIF_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1_MASK
- PB1_PIF_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK
- PB1_PIF_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_INIT_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_INIT__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_OFF_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_OFF__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_S2_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_S2__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK
- PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT
- PB1_PIF_TX_CTRL__TXPWR_IN_UNUSED__SHIFT
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0_MASK
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_ANALOG_SEL_0__SHIFT
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0_MASK
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_EXT_RESET_EN_0__SHIFT
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0_MASK
- PB1_PLL_LC0_CTRL_REG0__PLL_DBG_LC_VCTL_ADC_EN_0__SHIFT
- PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0_MASK
- PB1_PLL_LC0_CTRL_REG0__PLL_TST_LC_USAMPLE_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_FBDIV_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG0__PLL_CFG_LC_REFDIV_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_EN_0__SHIFT
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0_MASK
- PB1_PLL_LC0_OVRD_REG1__PLL_LC_PWRON_OVRD_VAL_0__SHIFT
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE_MASK
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_FREQMODE__SHIFT
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR_MASK
- PB1_PLL_LC0_SCI_STAT_OVRD_REG0__PLL_LC0_PLLPWR__SHIFT
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE__SHIFT
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR_MASK
- PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_PLLPWR__SHIFT
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE_MASK
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_FREQMODE__SHIFT
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR_MASK
- PB1_PLL_LC2_SCI_STAT_OVRD_REG0__PLL_LC2_PLLPWR__SHIFT
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE_MASK
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_FREQMODE__SHIFT
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR_MASK
- PB1_PLL_LC3_SCI_STAT_OVRD_REG0__PLL_LC3_PLLPWR__SHIFT
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0_MASK
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_ANALOG_SEL_0__SHIFT
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0_MASK
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_EXT_RESET_EN_0__SHIFT
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0_MASK
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_LF_CNTRL_0__SHIFT
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0_MASK
- PB1_PLL_RO0_CTRL_REG0__PLL_DBG_RO_VCTL_ADC_EN_0__SHIFT
- PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0_MASK
- PB1_PLL_RO0_CTRL_REG0__PLL_TST_RO_USAMPLE_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_FBDIV_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG0__PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_REFDIV_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_CFG_RO_VCO_MODE_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_EN_0__SHIFT
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0_MASK
- PB1_PLL_RO0_OVRD_REG1__PLL_RO_PWRON_OVRD_VAL_0__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_FREQMODE__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLFREQ__SHIFT
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR_MASK
- PB1_PLL_RO0_SCI_STAT_OVRD_REG0__PLL_RO0_PLLPWR__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_FREQMODE__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLFREQ__SHIFT
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR_MASK
- PB1_PLL_RO1_SCI_STAT_OVRD_REG0__PLL_RO1_PLLPWR__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_FREQMODE__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLFREQ__SHIFT
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR_MASK
- PB1_PLL_RO2_SCI_STAT_OVRD_REG0__PLL_RO2_PLLPWR__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_FREQMODE__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_FREQMODE_SCI_UPDT__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLFREQ_CBI_UPDT__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_CBI_UPDT__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_IGNR_PLLPWR_SCI_UPDT__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLFREQ__SHIFT
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR_MASK
- PB1_PLL_RO3_SCI_STAT_OVRD_REG0__PLL_RO3_PLLPWR__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_LC_PWRON_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_RO_PWRON_LUT_ENTRY_LS2__SHIFT
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC_MASK
- PB1_PLL_RO_GLB_CTRL_REG0__PLL_TST_LOSPDTST_SRC__SHIFT
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1_MASK
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2_MASK
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3_MASK
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_MODE_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE_MASK
- PB1_RX_GLB_CTRL_REG0__RX_CFG_ADAPT_RST_MODE__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN_MASK
- PB1_RX_GLB_CTRL_REG1__RX_ADAPT_HLD_ASRT_TO_DCLK_EN__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_FR_GAIN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PH_GAIN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_CDR_PI_STPSZ_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG1__RX_CFG_LEQ_DCATTN_BYP_EN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_CDR_TIME_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG2__RX_CFG_LEQ_LOOP_GAIN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD_MASK
- PB1_RX_GLB_CTRL_REG2__RX_DCLK_EN_ASRT_TO_ADAPT_HLD__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1_MASK
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2_MASK
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3_MASK
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_MODE_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE_MASK
- PB1_RX_GLB_CTRL_REG3__RX_ADAPT_RST_SUB_MODE__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_CDR_FR_EN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3_MASK
- PB1_RX_GLB_CTRL_REG3__RX_CFG_DFE_TIME_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1_MASK
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2_MASK
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3_MASK
- PB1_RX_GLB_CTRL_REG3__RX_L0_ENTRY_MODE_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_BER_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_FOM_TIME_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3_MASK
- PB1_RX_GLB_CTRL_REG4__RX_CFG_LEQ_POLE_BYP_VAL_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE_MASK
- PB1_RX_GLB_CTRL_REG5__RX_ADAPT_AUX_PWRON_MODE__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_POLE_BYP_EN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_LEQ_SHUNT_EN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK
- PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0_MASK
- PB1_RX_GLB_CTRL_REG5__RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS_MASK
- PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF_MASK
- PB1_RX_GLB_CTRL_REG6__RX_ADAPT_HLD_L1_DLL_OFF__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2_MASK
- PB1_RX_GLB_CTRL_REG6__RX_AUX_PWRON_LUT_ENTRY_LS2__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_LEQ_TIME_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3_MASK
- PB1_RX_GLB_CTRL_REG6__RX_CFG_OC_TIME_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0_MASK
- PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0__SHIFT
- PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2_MASK
- PB1_RX_GLB_CTRL_REG6__RX_FRONTEND_PWRON_LUT_ENTRY_LS2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_CPI_SEL_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_DLL_FLOCK_DISABLE_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN1__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3_MASK
- PB1_RX_GLB_CTRL_REG7__RX_CFG_TH_LOOP_GAIN_GEN3__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_AFTER_DLL_LOCK__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DCLK_EN_LUT_ENTRY_LS2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_LS2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS2__SHIFT
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3_MASK
- PB1_RX_GLB_CTRL_REG7__RX_DLL_PWRON_LUT_ENTRY_PS3__SHIFT
- PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME_MASK
- PB1_RX_GLB_CTRL_REG8__RX_DLL_LOCK_TIME__SHIFT
- PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN_MASK
- PB1_RX_GLB_CTRL_REG8__RX_DLL_PWRON_IN_RAMPDOWN__SHIFT
- PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME_MASK
- PB1_RX_GLB_CTRL_REG8__RX_DLL_SPEEDCHANGE_RESET_TIME__SHIFT
- PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY_MASK
- PB1_RX_GLB_CTRL_REG8__RX_FSM_L0S_IF_RX_RDY__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_FOM_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_HLD_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_ADAPT_RST_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_AUX_PWRON_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DCLK_DIV_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_DLL_FREQ_MODE_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_CFG_RCLK_DIV_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_DCLK_EN_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_DLL_PWRON_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_FRONTEND_PWRON_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_IDLEDET_PWRON_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG0__RX_TERM_EN_OVRD_VAL__SHIFT
- PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN_MASK
- PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_EN__SHIFT
- PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL_MASK
- PB1_RX_GLB_OVRD_REG1__RX_ADAPT_TRK_OVRD_VAL__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_ENABLEFOM_SCI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTFOM_SCI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_REQUESTTRK_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RESPONSEMODE_SCI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPRESETHINT_SCI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_CBI_UPDT_L8T11__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L0T3__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L12T15__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L4T7__SHIFT
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11_MASK
- PB1_RX_GLB_SCI_STAT_OVRD_REG0__IGNR_RXPWR_SCI_UPDT_L8T11__SHIFT
- PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0_MASK
- PB1_RX_LANE0_CTRL_REG0__RX_BACKUP_0__SHIFT
- PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0_MASK
- PB1_RX_LANE0_CTRL_REG0__RX_CFG_OVR_PWRSF_0__SHIFT
- PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0_MASK
- PB1_RX_LANE0_CTRL_REG0__RX_DBG_ANALOG_SEL_0__SHIFT
- PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0_MASK
- PB1_RX_LANE0_CTRL_REG0__RX_TERM_EN_0__SHIFT
- PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0_MASK
- PB1_RX_LANE0_CTRL_REG0__RX_TST_BSCAN_EN_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__ENABLEFOM_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTFOM_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__REQUESTTRK_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RESPONSEMODE_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXEYEFOM_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPRESETHINT_0__SHIFT
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0_MASK
- PB1_RX_LANE0_SCI_STAT_OVRD_REG0__RXPWR_0__SHIFT
- PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10_MASK
- PB1_RX_LANE10_CTRL_REG0__RX_BACKUP_10__SHIFT
- PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10_MASK
- PB1_RX_LANE10_CTRL_REG0__RX_CFG_OVR_PWRSF_10__SHIFT
- PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10_MASK
- PB1_RX_LANE10_CTRL_REG0__RX_DBG_ANALOG_SEL_10__SHIFT
- PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10_MASK
- PB1_RX_LANE10_CTRL_REG0__RX_TERM_EN_10__SHIFT
- PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10_MASK
- PB1_RX_LANE10_CTRL_REG0__RX_TST_BSCAN_EN_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__ENABLEFOM_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTFOM_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__REQUESTTRK_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RESPONSEMODE_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXEYEFOM_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPRESETHINT_10__SHIFT
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10_MASK
- PB1_RX_LANE10_SCI_STAT_OVRD_REG0__RXPWR_10__SHIFT
- PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11_MASK
- PB1_RX_LANE11_CTRL_REG0__RX_BACKUP_11__SHIFT
- PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11_MASK
- PB1_RX_LANE11_CTRL_REG0__RX_CFG_OVR_PWRSF_11__SHIFT
- PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11_MASK
- PB1_RX_LANE11_CTRL_REG0__RX_DBG_ANALOG_SEL_11__SHIFT
- PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11_MASK
- PB1_RX_LANE11_CTRL_REG0__RX_TERM_EN_11__SHIFT
- PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11_MASK
- PB1_RX_LANE11_CTRL_REG0__RX_TST_BSCAN_EN_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__ENABLEFOM_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTFOM_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__REQUESTTRK_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RESPONSEMODE_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXEYEFOM_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPRESETHINT_11__SHIFT
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11_MASK
- PB1_RX_LANE11_SCI_STAT_OVRD_REG0__RXPWR_11__SHIFT
- PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12_MASK
- PB1_RX_LANE12_CTRL_REG0__RX_BACKUP_12__SHIFT
- PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12_MASK
- PB1_RX_LANE12_CTRL_REG0__RX_CFG_OVR_PWRSF_12__SHIFT
- PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12_MASK
- PB1_RX_LANE12_CTRL_REG0__RX_DBG_ANALOG_SEL_12__SHIFT
- PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12_MASK
- PB1_RX_LANE12_CTRL_REG0__RX_TERM_EN_12__SHIFT
- PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12_MASK
- PB1_RX_LANE12_CTRL_REG0__RX_TST_BSCAN_EN_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__ENABLEFOM_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTFOM_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__REQUESTTRK_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RESPONSEMODE_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXEYEFOM_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPRESETHINT_12__SHIFT
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12_MASK
- PB1_RX_LANE12_SCI_STAT_OVRD_REG0__RXPWR_12__SHIFT
- PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13_MASK
- PB1_RX_LANE13_CTRL_REG0__RX_BACKUP_13__SHIFT
- PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13_MASK
- PB1_RX_LANE13_CTRL_REG0__RX_CFG_OVR_PWRSF_13__SHIFT
- PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13_MASK
- PB1_RX_LANE13_CTRL_REG0__RX_DBG_ANALOG_SEL_13__SHIFT
- PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13_MASK
- PB1_RX_LANE13_CTRL_REG0__RX_TERM_EN_13__SHIFT
- PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13_MASK
- PB1_RX_LANE13_CTRL_REG0__RX_TST_BSCAN_EN_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__ENABLEFOM_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTFOM_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__REQUESTTRK_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RESPONSEMODE_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXEYEFOM_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPRESETHINT_13__SHIFT
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13_MASK
- PB1_RX_LANE13_SCI_STAT_OVRD_REG0__RXPWR_13__SHIFT
- PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14_MASK
- PB1_RX_LANE14_CTRL_REG0__RX_BACKUP_14__SHIFT
- PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14_MASK
- PB1_RX_LANE14_CTRL_REG0__RX_CFG_OVR_PWRSF_14__SHIFT
- PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14_MASK
- PB1_RX_LANE14_CTRL_REG0__RX_DBG_ANALOG_SEL_14__SHIFT
- PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14_MASK
- PB1_RX_LANE14_CTRL_REG0__RX_TERM_EN_14__SHIFT
- PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14_MASK
- PB1_RX_LANE14_CTRL_REG0__RX_TST_BSCAN_EN_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__ENABLEFOM_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTFOM_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__REQUESTTRK_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RESPONSEMODE_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXEYEFOM_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPRESETHINT_14__SHIFT
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14_MASK
- PB1_RX_LANE14_SCI_STAT_OVRD_REG0__RXPWR_14__SHIFT
- PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15_MASK
- PB1_RX_LANE15_CTRL_REG0__RX_BACKUP_15__SHIFT
- PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15_MASK
- PB1_RX_LANE15_CTRL_REG0__RX_CFG_OVR_PWRSF_15__SHIFT
- PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15_MASK
- PB1_RX_LANE15_CTRL_REG0__RX_DBG_ANALOG_SEL_15__SHIFT
- PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15_MASK
- PB1_RX_LANE15_CTRL_REG0__RX_TERM_EN_15__SHIFT
- PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15_MASK
- PB1_RX_LANE15_CTRL_REG0__RX_TST_BSCAN_EN_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__ENABLEFOM_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTFOM_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__REQUESTTRK_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RESPONSEMODE_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXEYEFOM_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPRESETHINT_15__SHIFT
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15_MASK
- PB1_RX_LANE15_SCI_STAT_OVRD_REG0__RXPWR_15__SHIFT
- PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1_MASK
- PB1_RX_LANE1_CTRL_REG0__RX_BACKUP_1__SHIFT
- PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1_MASK
- PB1_RX_LANE1_CTRL_REG0__RX_CFG_OVR_PWRSF_1__SHIFT
- PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1_MASK
- PB1_RX_LANE1_CTRL_REG0__RX_DBG_ANALOG_SEL_1__SHIFT
- PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1_MASK
- PB1_RX_LANE1_CTRL_REG0__RX_TERM_EN_1__SHIFT
- PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1_MASK
- PB1_RX_LANE1_CTRL_REG0__RX_TST_BSCAN_EN_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__ENABLEFOM_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTFOM_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__REQUESTTRK_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RESPONSEMODE_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXEYEFOM_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPRESETHINT_1__SHIFT
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1_MASK
- PB1_RX_LANE1_SCI_STAT_OVRD_REG0__RXPWR_1__SHIFT
- PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2_MASK
- PB1_RX_LANE2_CTRL_REG0__RX_BACKUP_2__SHIFT
- PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2_MASK
- PB1_RX_LANE2_CTRL_REG0__RX_CFG_OVR_PWRSF_2__SHIFT
- PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2_MASK
- PB1_RX_LANE2_CTRL_REG0__RX_DBG_ANALOG_SEL_2__SHIFT
- PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2_MASK
- PB1_RX_LANE2_CTRL_REG0__RX_TERM_EN_2__SHIFT
- PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2_MASK
- PB1_RX_LANE2_CTRL_REG0__RX_TST_BSCAN_EN_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__ENABLEFOM_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTFOM_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__REQUESTTRK_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RESPONSEMODE_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXEYEFOM_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPRESETHINT_2__SHIFT
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2_MASK
- PB1_RX_LANE2_SCI_STAT_OVRD_REG0__RXPWR_2__SHIFT
- PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3_MASK
- PB1_RX_LANE3_CTRL_REG0__RX_BACKUP_3__SHIFT
- PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3_MASK
- PB1_RX_LANE3_CTRL_REG0__RX_CFG_OVR_PWRSF_3__SHIFT
- PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3_MASK
- PB1_RX_LANE3_CTRL_REG0__RX_DBG_ANALOG_SEL_3__SHIFT
- PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3_MASK
- PB1_RX_LANE3_CTRL_REG0__RX_TERM_EN_3__SHIFT
- PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3_MASK
- PB1_RX_LANE3_CTRL_REG0__RX_TST_BSCAN_EN_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__ENABLEFOM_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTFOM_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__REQUESTTRK_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RESPONSEMODE_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXEYEFOM_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPRESETHINT_3__SHIFT
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3_MASK
- PB1_RX_LANE3_SCI_STAT_OVRD_REG0__RXPWR_3__SHIFT
- PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4_MASK
- PB1_RX_LANE4_CTRL_REG0__RX_BACKUP_4__SHIFT
- PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4_MASK
- PB1_RX_LANE4_CTRL_REG0__RX_CFG_OVR_PWRSF_4__SHIFT
- PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4_MASK
- PB1_RX_LANE4_CTRL_REG0__RX_DBG_ANALOG_SEL_4__SHIFT
- PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4_MASK
- PB1_RX_LANE4_CTRL_REG0__RX_TERM_EN_4__SHIFT
- PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4_MASK
- PB1_RX_LANE4_CTRL_REG0__RX_TST_BSCAN_EN_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__ENABLEFOM_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTFOM_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__REQUESTTRK_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RESPONSEMODE_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXEYEFOM_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPRESETHINT_4__SHIFT
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4_MASK
- PB1_RX_LANE4_SCI_STAT_OVRD_REG0__RXPWR_4__SHIFT
- PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5_MASK
- PB1_RX_LANE5_CTRL_REG0__RX_BACKUP_5__SHIFT
- PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5_MASK
- PB1_RX_LANE5_CTRL_REG0__RX_CFG_OVR_PWRSF_5__SHIFT
- PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5_MASK
- PB1_RX_LANE5_CTRL_REG0__RX_DBG_ANALOG_SEL_5__SHIFT
- PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5_MASK
- PB1_RX_LANE5_CTRL_REG0__RX_TERM_EN_5__SHIFT
- PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5_MASK
- PB1_RX_LANE5_CTRL_REG0__RX_TST_BSCAN_EN_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__ENABLEFOM_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTFOM_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__REQUESTTRK_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RESPONSEMODE_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXEYEFOM_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPRESETHINT_5__SHIFT
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5_MASK
- PB1_RX_LANE5_SCI_STAT_OVRD_REG0__RXPWR_5__SHIFT
- PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6_MASK
- PB1_RX_LANE6_CTRL_REG0__RX_BACKUP_6__SHIFT
- PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6_MASK
- PB1_RX_LANE6_CTRL_REG0__RX_CFG_OVR_PWRSF_6__SHIFT
- PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6_MASK
- PB1_RX_LANE6_CTRL_REG0__RX_DBG_ANALOG_SEL_6__SHIFT
- PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6_MASK
- PB1_RX_LANE6_CTRL_REG0__RX_TERM_EN_6__SHIFT
- PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6_MASK
- PB1_RX_LANE6_CTRL_REG0__RX_TST_BSCAN_EN_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__ENABLEFOM_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTFOM_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__REQUESTTRK_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RESPONSEMODE_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXEYEFOM_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPRESETHINT_6__SHIFT
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6_MASK
- PB1_RX_LANE6_SCI_STAT_OVRD_REG0__RXPWR_6__SHIFT
- PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7_MASK
- PB1_RX_LANE7_CTRL_REG0__RX_BACKUP_7__SHIFT
- PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7_MASK
- PB1_RX_LANE7_CTRL_REG0__RX_CFG_OVR_PWRSF_7__SHIFT
- PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7_MASK
- PB1_RX_LANE7_CTRL_REG0__RX_DBG_ANALOG_SEL_7__SHIFT
- PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7_MASK
- PB1_RX_LANE7_CTRL_REG0__RX_TERM_EN_7__SHIFT
- PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7_MASK
- PB1_RX_LANE7_CTRL_REG0__RX_TST_BSCAN_EN_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__ENABLEFOM_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTFOM_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__REQUESTTRK_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RESPONSEMODE_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXEYEFOM_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPRESETHINT_7__SHIFT
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7_MASK
- PB1_RX_LANE7_SCI_STAT_OVRD_REG0__RXPWR_7__SHIFT
- PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8_MASK
- PB1_RX_LANE8_CTRL_REG0__RX_BACKUP_8__SHIFT
- PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8_MASK
- PB1_RX_LANE8_CTRL_REG0__RX_CFG_OVR_PWRSF_8__SHIFT
- PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8_MASK
- PB1_RX_LANE8_CTRL_REG0__RX_DBG_ANALOG_SEL_8__SHIFT
- PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8_MASK
- PB1_RX_LANE8_CTRL_REG0__RX_TERM_EN_8__SHIFT
- PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8_MASK
- PB1_RX_LANE8_CTRL_REG0__RX_TST_BSCAN_EN_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__ENABLEFOM_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTFOM_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__REQUESTTRK_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RESPONSEMODE_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXEYEFOM_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPRESETHINT_8__SHIFT
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8_MASK
- PB1_RX_LANE8_SCI_STAT_OVRD_REG0__RXPWR_8__SHIFT
- PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9_MASK
- PB1_RX_LANE9_CTRL_REG0__RX_BACKUP_9__SHIFT
- PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9_MASK
- PB1_RX_LANE9_CTRL_REG0__RX_CFG_OVR_PWRSF_9__SHIFT
- PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9_MASK
- PB1_RX_LANE9_CTRL_REG0__RX_DBG_ANALOG_SEL_9__SHIFT
- PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9_MASK
- PB1_RX_LANE9_CTRL_REG0__RX_TERM_EN_9__SHIFT
- PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9_MASK
- PB1_RX_LANE9_CTRL_REG0__RX_TST_BSCAN_EN_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ELECIDLEDETEN_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__ENABLEFOM_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTFOM_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__REQUESTTRK_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RESPONSEMODE_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXEYEFOM_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPRESETHINT_9__SHIFT
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9_MASK
- PB1_RX_LANE9_SCI_STAT_OVRD_REG0__RXPWR_9__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH_MASK
- PB1_STRAP_GLB_REG0__STRAP_CFG_IDLEDET_TH__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL_MASK
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXDLL_VREG_REF_SEL__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL_MASK
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXPI_OFFSET_BYP_VAL__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE_MASK
- PB1_STRAP_GLB_REG0__STRAP_DBG_RXRDATA_GATING_DISABLE__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS_MASK
- PB1_STRAP_GLB_REG0__STRAP_DFT_CALIB_BYPASS__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL_MASK
- PB1_STRAP_GLB_REG0__STRAP_DFT_RXBSCAN_EN_VAL__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON_MASK
- PB1_STRAP_GLB_REG0__STRAP_FORCE_LC_PLL_ON__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE_MASK
- PB1_STRAP_GLB_REG0__STRAP_PLL_CFG_LC_VCO_TUNE__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD_MASK
- PB1_STRAP_GLB_REG0__STRAP_PWRGOOD_OVRD__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START_MASK
- PB1_STRAP_GLB_REG0__STRAP_QUICK_SIM_START__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL_MASK
- PB1_STRAP_GLB_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF_MASK
- PB1_STRAP_GLB_REG0__STRAP_RX_CFG_OVR_PWRSF__SHIFT
- PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0__MASK
- PB1_STRAP_GLB_REG0__STRAP_RX_TRK_MODE_0___SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_MODE__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_RST_SUB_ENTRY__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_ADAPT_TIME_OUT__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_DLL_RESET_IN_SPDCHG__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_EI_FILTER__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_L0_ENTRY_MODE__SHIFT
- PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE_MASK
- PB1_STRAP_GLB_REG1__STRAP_RX_PS0_RDY_GEN_MODE__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME_MASK
- PB1_STRAP_GLB_REG2__STRAP_BG_SETTLE_TIME__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME_MASK
- PB1_STRAP_GLB_REG2__STRAP_BPHYC_PLL_RAMP_UP_TIME__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0_MASK
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS0__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1_MASK
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DIS1__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR_MASK
- PB1_STRAP_GLB_REG2__STRAP_B_PCB_DRV_STR__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME_MASK
- PB1_STRAP_GLB_REG2__STRAP_IMPCAL_SETTLE_TIME__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME_MASK
- PB1_STRAP_GLB_REG2__STRAP_TX_CMDET_TIME__SHIFT
- PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME_MASK
- PB1_STRAP_GLB_REG2__STRAP_TX_STARTUP_TIME__SHIFT
- PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN_MASK
- PB1_STRAP_PIN_REG0__STRAP_TX_DEEMPH_EN__SHIFT
- PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING_MASK
- PB1_STRAP_PIN_REG0__STRAP_TX_FULL_SWING__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL_MASK
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_BW_CNTRL__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL_MASK
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_LC_LF_CNTRL__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL_MASK
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_BW_CNTRL__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS_MASK
- PB1_STRAP_PLL_REG0__STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL_MASK
- PB1_STRAP_PLL_REG0__STRAP_PLL_STRAP_SEL__SHIFT
- PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF_MASK
- PB1_STRAP_PLL_REG0__STRAP_TX_RXDET_X1_SSF__SHIFT
- PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL_MASK
- PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF0_SEL__SHIFT
- PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL_MASK
- PB1_STRAP_RX_REG0__STRAP_BG_CFG_LC_REG_VREF1_SEL__SHIFT
- PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN_MASK
- PB1_STRAP_RX_REG0__STRAP_DBG_RXPI_OFFSET_BYP_EN__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_CDR_TIME__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_DLL_FLOCK_DISABLE__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_FOM_TIME__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_LEQ_TIME__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_OC_TIME__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_TERM_MODE__SHIFT
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN_MASK
- PB1_STRAP_RX_REG0__STRAP_RX_CFG_TH_LOOP_GAIN__SHIFT
- PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL_MASK
- PB1_STRAP_RX_REG0__STRAP_TX_CFG_RPTR_RST_VAL__SHIFT
- PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL_MASK
- PB1_STRAP_RX_REG1__STRAP_BG_CFG_RO_REG_VREF_SEL__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_ADAPT_MODE__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PH_GAIN__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_CDR_PI_STPSZ__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_DFE_TIME__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_LOOP_GAIN__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_DIS__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_POLE_BYP_VAL__SHIFT
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS_MASK
- PB1_STRAP_RX_REG1__STRAP_RX_CFG_LEQ_SHUNT_DIS__SHIFT
- PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG_MASK
- PB1_STRAP_RX_REG1__STRAP_TX_DEEMPH_PRSHT_STNG__SHIFT
- PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1__MASK
- PB1_STRAP_TX_REG0__STRAP_RX_TRK_MODE_1___SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_EN__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV0_TAP_SEL__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_EN__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV1_TAP_SEL__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_EN__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRV2_TAP_SEL__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_EN__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_DRVX_TAP_SEL__SHIFT
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN_MASK
- PB1_STRAP_TX_REG0__STRAP_TX_CFG_SWING_BOOST_EN__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_0__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_10__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_11__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_12__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_13__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_14__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_15__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_16__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_17__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_18__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_19__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_1__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_20__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_21__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_22__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_23__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_24__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_25__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_26__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_27__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_28__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_29__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_2__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_30__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_31__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_3__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_4__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_5__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_6__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_7__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_8__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0__ACCEPT_ENTRY_9__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_32__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_33__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_34__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_35__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_36__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_37__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_38__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_39__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_40__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_41__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_42__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_43__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_44__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_45__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_46__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_47__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_48__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_49__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_50__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_51__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_52__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_53__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_54__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_55__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_56__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_57__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_58__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_59__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_60__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_61__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_62__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1__ACCEPT_ENTRY_63__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_64__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_65__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_66__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_67__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_68__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_69__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_70__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_71__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_72__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_73__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_74__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_75__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_76__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_77__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_78__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_79__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_80__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_81__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_82__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_83__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_84__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_85__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_86__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_87__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_88__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_89__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_90__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_91__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_92__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_93__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_94__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2__ACCEPT_ENTRY_95__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_100__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_101__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_102__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_103__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_104__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_105__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_106__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_107__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_108__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_109__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_96__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_97__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_98__SHIFT
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99_MASK
- PB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3__ACCEPT_ENTRY_99__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1_MASK
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN1__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2_MASK
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN2__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3_MASK
- PB1_TX_GLB_CTRL_REG0__TX_CFG_RPTR_RST_VAL_GEN3__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER_MASK
- PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_DIR_VER__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN_MASK
- PB1_TX_GLB_CTRL_REG0__TX_COEFF_ROUND_EN__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING_MASK
- PB1_TX_GLB_CTRL_REG0__TX_DATA_CLK_GATING__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON_MASK
- PB1_TX_GLB_CTRL_REG0__TX_DCLK_EN_LSX_ALWAYS_ON__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL_MASK
- PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_ASRT_DLY_VAL__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL_MASK
- PB1_TX_GLB_CTRL_REG0__TX_DRV_DATA_DSRT_DLY_VAL__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF_MASK
- PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_OFF__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4_MASK
- PB1_TX_GLB_CTRL_REG0__TX_FRONTEND_PWRON_IN_PS4__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS_MASK
- PB1_TX_GLB_CTRL_REG0__TX_PRESET_TABLE_BYPASS__SHIFT
- PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL_MASK
- PB1_TX_GLB_CTRL_REG0__TX_STAGGER_CTRL__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX16_EN_L0T15__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_0__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_10__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_11__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_12__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_13__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_14__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_15__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_1__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_2__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_3__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_4__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_5__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_6__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_7__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_8__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX1_EN_9__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L0T1__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L10T11__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L12T13__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L14T15__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L2T3__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L4T5__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L6T7__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX2_EN_L8T9__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L0T3__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L12T15__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L4T7__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX4_EN_L8T11__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L0T7__SHIFT
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15_MASK
- PB1_TX_GLB_LANE_SKEW_CTRL__TX_CFG_GROUPX8_EN_L8T15__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DCLK_DIV_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV0_TAP_SEL_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV1_TAP_SEL_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG0__TX_CFG_DRV2_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRV2_TAP_SEL_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_DRVX_TAP_SEL_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_PLLCLK_SEL_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_CMDET_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_DATA_IN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_RPTR_RSTN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_RXDET_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG1__TX_WPTR_RSTN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_EN_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_EN_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX16_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX1_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX2_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX4_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_CFG_GROUPX8_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN_MASK
- PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_EN__SHIFT
- PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG2__TX_WRITE_EN_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_EN_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_EN_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_EN_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_EN_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG3__TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_EN_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL_MASK
- PB1_TX_GLB_OVRD_REG4__TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_CBI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENTID_SCI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_CBI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_COEFFICIENT_SCI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_INCOHERENTCK_SCI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_CBI_UPDT_L8T11__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L0T3__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L12T15__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L4T7__SHIFT
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11_MASK
- PB1_TX_GLB_SCI_STAT_OVRD_REG0__IGNR_TXPWR_SCI_UPDT_L8T11__SHIFT
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0_MASK
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_DISPCLK_MODE_0__SHIFT
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0_MASK
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_INV_DATA_0__SHIFT
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0_MASK
- PB1_TX_LANE0_CTRL_REG0__TX_CFG_SWING_BOOST_EN_0__SHIFT
- PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0_MASK
- PB1_TX_LANE0_CTRL_REG0__TX_DBG_PRBS_EN_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_EN_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_0__SHIFT
- PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0_MASK
- PB1_TX_LANE0_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENTID_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__COEFFICIENT_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__DEEMPH_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__INCOHERENTCK_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXMARG_0__SHIFT
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0_MASK
- PB1_TX_LANE0_SCI_STAT_OVRD_REG0__TXPWR_0__SHIFT
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10_MASK
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_DISPCLK_MODE_10__SHIFT
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10_MASK
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_INV_DATA_10__SHIFT
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10_MASK
- PB1_TX_LANE10_CTRL_REG0__TX_CFG_SWING_BOOST_EN_10__SHIFT
- PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10_MASK
- PB1_TX_LANE10_CTRL_REG0__TX_DBG_PRBS_EN_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_EN_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_10__SHIFT
- PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10_MASK
- PB1_TX_LANE10_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENTID_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__COEFFICIENT_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__DEEMPH_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__INCOHERENTCK_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXMARG_10__SHIFT
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10_MASK
- PB1_TX_LANE10_SCI_STAT_OVRD_REG0__TXPWR_10__SHIFT
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11_MASK
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_DISPCLK_MODE_11__SHIFT
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11_MASK
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_INV_DATA_11__SHIFT
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11_MASK
- PB1_TX_LANE11_CTRL_REG0__TX_CFG_SWING_BOOST_EN_11__SHIFT
- PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11_MASK
- PB1_TX_LANE11_CTRL_REG0__TX_DBG_PRBS_EN_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_EN_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_11__SHIFT
- PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11_MASK
- PB1_TX_LANE11_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENTID_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__COEFFICIENT_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__DEEMPH_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__INCOHERENTCK_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXMARG_11__SHIFT
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11_MASK
- PB1_TX_LANE11_SCI_STAT_OVRD_REG0__TXPWR_11__SHIFT
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12_MASK
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_DISPCLK_MODE_12__SHIFT
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12_MASK
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_INV_DATA_12__SHIFT
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12_MASK
- PB1_TX_LANE12_CTRL_REG0__TX_CFG_SWING_BOOST_EN_12__SHIFT
- PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12_MASK
- PB1_TX_LANE12_CTRL_REG0__TX_DBG_PRBS_EN_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_EN_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_12__SHIFT
- PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12_MASK
- PB1_TX_LANE12_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENTID_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__COEFFICIENT_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__DEEMPH_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__INCOHERENTCK_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXMARG_12__SHIFT
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12_MASK
- PB1_TX_LANE12_SCI_STAT_OVRD_REG0__TXPWR_12__SHIFT
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13_MASK
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_DISPCLK_MODE_13__SHIFT
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13_MASK
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_INV_DATA_13__SHIFT
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13_MASK
- PB1_TX_LANE13_CTRL_REG0__TX_CFG_SWING_BOOST_EN_13__SHIFT
- PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13_MASK
- PB1_TX_LANE13_CTRL_REG0__TX_DBG_PRBS_EN_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_EN_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_13__SHIFT
- PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13_MASK
- PB1_TX_LANE13_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENTID_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__COEFFICIENT_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__DEEMPH_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__INCOHERENTCK_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXMARG_13__SHIFT
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13_MASK
- PB1_TX_LANE13_SCI_STAT_OVRD_REG0__TXPWR_13__SHIFT
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14_MASK
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_DISPCLK_MODE_14__SHIFT
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14_MASK
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_INV_DATA_14__SHIFT
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14_MASK
- PB1_TX_LANE14_CTRL_REG0__TX_CFG_SWING_BOOST_EN_14__SHIFT
- PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14_MASK
- PB1_TX_LANE14_CTRL_REG0__TX_DBG_PRBS_EN_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_EN_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_14__SHIFT
- PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14_MASK
- PB1_TX_LANE14_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENTID_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__COEFFICIENT_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__DEEMPH_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__INCOHERENTCK_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXMARG_14__SHIFT
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14_MASK
- PB1_TX_LANE14_SCI_STAT_OVRD_REG0__TXPWR_14__SHIFT
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15_MASK
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_DISPCLK_MODE_15__SHIFT
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15_MASK
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_INV_DATA_15__SHIFT
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15_MASK
- PB1_TX_LANE15_CTRL_REG0__TX_CFG_SWING_BOOST_EN_15__SHIFT
- PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15_MASK
- PB1_TX_LANE15_CTRL_REG0__TX_DBG_PRBS_EN_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_EN_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_15__SHIFT
- PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15_MASK
- PB1_TX_LANE15_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENTID_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__COEFFICIENT_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__DEEMPH_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__INCOHERENTCK_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXMARG_15__SHIFT
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15_MASK
- PB1_TX_LANE15_SCI_STAT_OVRD_REG0__TXPWR_15__SHIFT
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1_MASK
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_DISPCLK_MODE_1__SHIFT
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1_MASK
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_INV_DATA_1__SHIFT
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1_MASK
- PB1_TX_LANE1_CTRL_REG0__TX_CFG_SWING_BOOST_EN_1__SHIFT
- PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1_MASK
- PB1_TX_LANE1_CTRL_REG0__TX_DBG_PRBS_EN_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_EN_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_1__SHIFT
- PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1_MASK
- PB1_TX_LANE1_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENTID_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__COEFFICIENT_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__DEEMPH_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__INCOHERENTCK_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXMARG_1__SHIFT
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1_MASK
- PB1_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2_MASK
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_DISPCLK_MODE_2__SHIFT
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2_MASK
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_INV_DATA_2__SHIFT
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2_MASK
- PB1_TX_LANE2_CTRL_REG0__TX_CFG_SWING_BOOST_EN_2__SHIFT
- PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2_MASK
- PB1_TX_LANE2_CTRL_REG0__TX_DBG_PRBS_EN_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_EN_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_2__SHIFT
- PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2_MASK
- PB1_TX_LANE2_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENTID_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__COEFFICIENT_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__DEEMPH_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__INCOHERENTCK_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXMARG_2__SHIFT
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2_MASK
- PB1_TX_LANE2_SCI_STAT_OVRD_REG0__TXPWR_2__SHIFT
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3_MASK
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_DISPCLK_MODE_3__SHIFT
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3_MASK
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_INV_DATA_3__SHIFT
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3_MASK
- PB1_TX_LANE3_CTRL_REG0__TX_CFG_SWING_BOOST_EN_3__SHIFT
- PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3_MASK
- PB1_TX_LANE3_CTRL_REG0__TX_DBG_PRBS_EN_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_EN_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_3__SHIFT
- PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3_MASK
- PB1_TX_LANE3_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENTID_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__COEFFICIENT_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__DEEMPH_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__INCOHERENTCK_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXMARG_3__SHIFT
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3_MASK
- PB1_TX_LANE3_SCI_STAT_OVRD_REG0__TXPWR_3__SHIFT
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4_MASK
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_DISPCLK_MODE_4__SHIFT
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4_MASK
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_INV_DATA_4__SHIFT
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4_MASK
- PB1_TX_LANE4_CTRL_REG0__TX_CFG_SWING_BOOST_EN_4__SHIFT
- PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4_MASK
- PB1_TX_LANE4_CTRL_REG0__TX_DBG_PRBS_EN_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_EN_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_4__SHIFT
- PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4_MASK
- PB1_TX_LANE4_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENTID_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__COEFFICIENT_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__DEEMPH_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__INCOHERENTCK_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXMARG_4__SHIFT
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4_MASK
- PB1_TX_LANE4_SCI_STAT_OVRD_REG0__TXPWR_4__SHIFT
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5_MASK
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_DISPCLK_MODE_5__SHIFT
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5_MASK
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_INV_DATA_5__SHIFT
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5_MASK
- PB1_TX_LANE5_CTRL_REG0__TX_CFG_SWING_BOOST_EN_5__SHIFT
- PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5_MASK
- PB1_TX_LANE5_CTRL_REG0__TX_DBG_PRBS_EN_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_EN_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_5__SHIFT
- PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5_MASK
- PB1_TX_LANE5_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENTID_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__COEFFICIENT_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__DEEMPH_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__INCOHERENTCK_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5_MASK
- PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXPWR_5__SHIFT
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6_MASK
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_DISPCLK_MODE_6__SHIFT
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6_MASK
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_INV_DATA_6__SHIFT
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6_MASK
- PB1_TX_LANE6_CTRL_REG0__TX_CFG_SWING_BOOST_EN_6__SHIFT
- PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6_MASK
- PB1_TX_LANE6_CTRL_REG0__TX_DBG_PRBS_EN_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_EN_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_6__SHIFT
- PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6_MASK
- PB1_TX_LANE6_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENTID_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__COEFFICIENT_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__DEEMPH_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__INCOHERENTCK_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXMARG_6__SHIFT
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6_MASK
- PB1_TX_LANE6_SCI_STAT_OVRD_REG0__TXPWR_6__SHIFT
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7_MASK
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_DISPCLK_MODE_7__SHIFT
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7_MASK
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_INV_DATA_7__SHIFT
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7_MASK
- PB1_TX_LANE7_CTRL_REG0__TX_CFG_SWING_BOOST_EN_7__SHIFT
- PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7_MASK
- PB1_TX_LANE7_CTRL_REG0__TX_DBG_PRBS_EN_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_EN_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_7__SHIFT
- PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7_MASK
- PB1_TX_LANE7_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENTID_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__COEFFICIENT_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__DEEMPH_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__INCOHERENTCK_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXMARG_7__SHIFT
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7_MASK
- PB1_TX_LANE7_SCI_STAT_OVRD_REG0__TXPWR_7__SHIFT
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8_MASK
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_DISPCLK_MODE_8__SHIFT
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8_MASK
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_INV_DATA_8__SHIFT
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8_MASK
- PB1_TX_LANE8_CTRL_REG0__TX_CFG_SWING_BOOST_EN_8__SHIFT
- PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8_MASK
- PB1_TX_LANE8_CTRL_REG0__TX_DBG_PRBS_EN_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_EN_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_8__SHIFT
- PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8_MASK
- PB1_TX_LANE8_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENTID_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__COEFFICIENT_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__DEEMPH_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__INCOHERENTCK_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXMARG_8__SHIFT
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8_MASK
- PB1_TX_LANE8_SCI_STAT_OVRD_REG0__TXPWR_8__SHIFT
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9_MASK
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_DISPCLK_MODE_9__SHIFT
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9_MASK
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_INV_DATA_9__SHIFT
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9_MASK
- PB1_TX_LANE9_CTRL_REG0__TX_CFG_SWING_BOOST_EN_9__SHIFT
- PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9_MASK
- PB1_TX_LANE9_CTRL_REG0__TX_DBG_PRBS_EN_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_EN_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DCLK_EN_OVRD_VAL_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_EN_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_DATA_EN_OVRD_VAL_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_EN_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_DRV_PWRON_OVRD_VAL_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_EN_9__SHIFT
- PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9_MASK
- PB1_TX_LANE9_OVRD_REG0__TX_FRONTEND_PWRON_OVRD_VAL_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENTID_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__COEFFICIENT_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__DEEMPH_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__INCOHERENTCK_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXMARG_9__SHIFT
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9_MASK
- PB1_TX_LANE9_SCI_STAT_OVRD_REG0__TXPWR_9__SHIFT
- PB2
- PB20MD_0
- PB20MD_000
- PB20MD_001
- PB20MD_010
- PB20MD_011
- PB20MD_1
- PB20MD_100
- PB20MD_101
- PB20MD_110
- PB20MD_111
- PB20_AF_UART5_CTS
- PB20_DATA
- PB20_IN
- PB20_IOR_IN
- PB20_IOR_OUT
- PB20_OUT
- PB20_PF_CSI_VSYNC
- PB21MD_0
- PB21MD_00
- PB21MD_01
- PB21MD_1
- PB21MD_10
- PB21MD_11
- PB21_AF_UART5_RTS
- PB21_DATA
- PB21_IN
- PB21_IOR_IN
- PB21_IOR_OUT
- PB21_OUT
- PB21_PF_CSI_HSYNC
- PB22MD_00
- PB22MD_000
- PB22MD_001
- PB22MD_01
- PB22MD_010
- PB22MD_011
- PB22MD_10
- PB22MD_100
- PB22MD_101
- PB22MD_110
- PB22MD_111
- PB22_DATA
- PB22_IN
- PB22_IOR_IN
- PB22_IOR_OUT
- PB22_OUT
- PB22_PF_USBH1_BYP
- PB22_PF_USBH1_SUSP
- PB23_PF_USB_PWR
- PB24_PF_USB_OC
- PB25_AIN_SLCDC1_DAT0
- PB25_PF_USBH1_ON
- PB25_PF_USBH1_RCV
- PB26_AF_UART4_RTS
- PB26_AIN_SLCDC1_DAT1
- PB26_CIN_USBH1_RXDAT
- PB26_PF_USBH1_FS
- PB27_AIN_SLCDC1_DAT2
- PB27_PF_USBH1_OE
- PB28_AF_UART4_TXD
- PB28_AIN_SLCDC1_DAT3
- PB28_PF_USBH1_TXDM
- PB29_AF_UART4_CTS
- PB29_AIN_SLCDC1_DAT4
- PB29_AOUT_UART4_RXD
- PB29_PF_USBH1_TXDP
- PB2CLK
- PB2MD_0
- PB2MD_00
- PB2MD_01
- PB2MD_1
- PB2MD_10
- PB2MD_11
- PB2_COL
- PB2_CRS
- PB2_DATA
- PB2_DIRB0
- PB2_DIRB1
- PB2_FN
- PB2_IN
- PB2_IOR_IN
- PB2_IOR_OUT
- PB2_OUT
- PB2_PSORB0
- PB2_PSORB1
- PB2_RXDAT
- PB2_RXDV
- PB2_RXER
- PB2_TXDAT
- PB2_TXEN
- PB2_TXER
- PB3
- PB30_AIN_SLCDC1_DAT5
- PB30_CIN_UART4_CTS
- PB30_PF_USBH1_RXDM
- PB31_AF_UART4_RXD
- PB31_AIN_SLCDC1_DAT6
- PB31_AOUT_UART4_RTS
- PB31_PF_USBH1_RXDP
- PB3400_MEM_CTRL
- PB3400_MEM_CTRL_SLEEP
- PB3CLK
- PB3MD_0
- PB3MD_00
- PB3MD_01
- PB3MD_1
- PB3MD_10
- PB3MD_11
- PB3_COL
- PB3_CRS
- PB3_DATA
- PB3_DIRB0
- PB3_DIRB1
- PB3_FN
- PB3_IN
- PB3_IOR_IN
- PB3_IOR_OUT
- PB3_OUT
- PB3_PSORB0
- PB3_PSORB1
- PB3_RXDAT
- PB3_RXDV
- PB3_RXER
- PB3_TXDAT
- PB3_TXEN
- PB3_TXER
- PB4
- PB4CLK
- PB4MD_00
- PB4MD_01
- PB4MD_10
- PB4MD_11
- PB4_AF_MSHC_DATA0
- PB4_DATA
- PB4_FN
- PB4_IN
- PB4_IOR_IN
- PB4_IOR_OUT
- PB4_OUT
- PB4_PF_SD2_D0
- PB5
- PB5CLK
- PB5MD_00
- PB5MD_01
- PB5MD_10
- PB5MD_11
- PB5_AF_MSHC_DATA1
- PB5_DATA
- PB5_FN
- PB5_IN
- PB5_IOR_IN
- PB5_IOR_OUT
- PB5_OUT
- PB5_PF_SD2_D1
- PB6
- PB6CLK
- PB6MD_00
- PB6MD_01
- PB6MD_10
- PB6MD_11
- PB6_AF_MSHC_DATA2
- PB6_AIN_SLCDC1_D0
- PB6_DATA
- PB6_FN
- PB6_IN
- PB6_IOR_IN
- PB6_IOR_OUT
- PB6_OUT
- PB6_PF_SD2_D2
- PB7
- PB7CLK
- PB7MD_00
- PB7MD_01
- PB7MD_10
- PB7MD_11
- PB7_AF_MSHC_DATA4
- PB7_AIN_SLCDC1_RS
- PB7_DATA
- PB7_FN
- PB7_IN
- PB7_IOR_IN
- PB7_IOR_OUT
- PB7_OUT
- PB7_PF_SD2_D3
- PB8MD_00
- PB8MD_01
- PB8MD_10
- PB8MD_11
- PB8_AF_MSHC_BS
- PB8_AIN_SLCDC1_CS
- PB8_DATA
- PB8_IN
- PB8_IOR_IN
- PB8_IOR_OUT
- PB8_OUT
- PB8_PF_SD2_CMD
- PB9MD_00
- PB9MD_01
- PB9MD_10
- PB9MD_11
- PB9_AF_MSHC_SCLK
- PB9_AIN_SLCDC1_CLK
- PB9_DATA
- PB9_IN
- PB9_IOR_IN
- PB9_IOR_OUT
- PB9_OUT
- PB9_PF_SD2_CLK
- PBA_ACTION
- PBA_HI
- PBA_LO
- PBA_SIZE
- PBA_STRATEGY_EQUAL
- PBA_STRATEGY_WEIGHTED
- PBA_ZONE
- PBB_REGISTER_DEFINITION_T
- PBC2LRH
- PBCC_LONG
- PBCC_RATE_BIT
- PBCC_SHORT
- PBCR
- PBC_6120_VL15_SEND_CTRL
- PBC_7220_VL15_SEND
- PBC_7220_VL15_SEND_CTRL
- PBC_7322_VL15_SEND
- PBC_7322_VL15_SEND_CTRL
- PBC_ADDR_SH
- PBC_BASE_ADDRESS
- PBC_BCTRL1_CLEAR_REG
- PBC_BCTRL1_LCDON
- PBC_BCTRL1_SET_REG
- PBC_CREDIT_RETURN
- PBC_DC_INFO
- PBC_DC_INFO_SHIFT
- PBC_FECN
- PBC_IHCRC_GKDETH
- PBC_IHCRC_LKDETH
- PBC_IHCRC_NONE
- PBC_INSERT_BYPASS_ICRC
- PBC_INSERT_HCRC_MASK
- PBC_INSERT_HCRC_SHIFT
- PBC_INSERT_HCRC_SMASK
- PBC_INT
- PBC_INTCURR_STATUS
- PBC_INTMASK_CLEAR
- PBC_INTMASK_CLEAR_REG
- PBC_INTMASK_SET
- PBC_INTMASK_SET_REG
- PBC_INTR
- PBC_INTSTATUS
- PBC_INTSTATUS_REG
- PBC_LENGTH_DWS_MASK
- PBC_LENGTH_DWS_SHIFT
- PBC_LENGTH_DWS_SMASK
- PBC_PACKET_BYPASS
- PBC_POLLING_WK_CID
- PBC_PORT_SEL_LSB
- PBC_PORT_SEL_RMASK
- PBC_REG_ADDR
- PBC_SC16C652_UARTA
- PBC_SC16C652_UARTB
- PBC_STATIC_RATE_CONTROL_COUNT_MASK
- PBC_STATIC_RATE_CONTROL_COUNT_SHIFT
- PBC_STATIC_RATE_CONTROL_COUNT_SMASK
- PBC_TEST_BAD_ICRC
- PBC_TEST_EBP
- PBC_VERSION_REG
- PBC_VL_MASK
- PBC_VL_NUM_LSB
- PBC_VL_NUM_RMASK
- PBC_VL_SHIFT
- PBC_VL_SMASK
- PBDATA
- PBDATA_ADDR
- PBDIR
- PBDIR_ADDR
- PBDR
- PBE
- PBES_PER_LINKED_PAGE
- PBF_BTB_GUARANTEED_RT_OFFSET
- PBF_CFG
- PBF_CMDQ_LINES_E5_RSVD_RATIO
- PBF_CMDQ_LINES_RT_OFFSET
- PBF_CMDQ_PURE_LB_LINES
- PBF_CTRL
- PBF_DBG
- PBF_INT_ENA
- PBF_INT_STA
- PBF_LIFE_TIMER
- PBF_MAX_CMD_LINES
- PBF_MAX_PCNT
- PBF_PB1_REG_DBG_DWORD_ENABLE
- PBF_PB1_REG_DBG_FORCE_FRAME
- PBF_PB1_REG_DBG_FORCE_VALID
- PBF_PB1_REG_DBG_SELECT
- PBF_PB1_REG_DBG_SHIFT
- PBF_PB2_REG_DBG_DWORD_ENABLE
- PBF_PB2_REG_DBG_FORCE_FRAME
- PBF_PB2_REG_DBG_FORCE_VALID
- PBF_PB2_REG_DBG_SELECT
- PBF_PB2_REG_DBG_SHIFT
- PBF_QUEUE_CSR
- PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET
- PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET
- PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET
- PBF_REG_COS0_UPPER_BOUND
- PBF_REG_COS0_UPPER_BOUND_P0
- PBF_REG_COS0_UPPER_BOUND_P1
- PBF_REG_COS0_WEIGHT
- PBF_REG_COS0_WEIGHT_P0
- PBF_REG_COS0_WEIGHT_P1
- PBF_REG_COS1_UPPER_BOUND
- PBF_REG_COS1_WEIGHT
- PBF_REG_COS1_WEIGHT_P0
- PBF_REG_COS1_WEIGHT_P1
- PBF_REG_COS2_WEIGHT_P0
- PBF_REG_COS2_WEIGHT_P1
- PBF_REG_COS3_WEIGHT_P0
- PBF_REG_COS4_WEIGHT_P0
- PBF_REG_COS5_WEIGHT_P0
- PBF_REG_CREDIT_LB_Q
- PBF_REG_CREDIT_Q0
- PBF_REG_CREDIT_Q1
- PBF_REG_DBG_DWORD_ENABLE
- PBF_REG_DBG_FORCE_FRAME
- PBF_REG_DBG_FORCE_VALID
- PBF_REG_DBG_SELECT
- PBF_REG_DBG_SHIFT
- PBF_REG_DISABLE_NEW_TASK_PROC_P0
- PBF_REG_DISABLE_NEW_TASK_PROC_P1
- PBF_REG_DISABLE_NEW_TASK_PROC_P4
- PBF_REG_DISABLE_PF
- PBF_REG_DISABLE_VF
- PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0
- PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1
- PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0
- PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1
- PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0
- PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1
- PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0
- PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1
- PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0
- PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1
- PBF_REG_ETS_ENABLED
- PBF_REG_HDRS_AFTER_BASIC
- PBF_REG_HDRS_AFTER_TAG_0
- PBF_REG_HIGH_PRIORITY_COS_NUM
- PBF_REG_IF_ENABLE_REG
- PBF_REG_INIT
- PBF_REG_INIT_CRD_LB_Q
- PBF_REG_INIT_CRD_Q0
- PBF_REG_INIT_CRD_Q1
- PBF_REG_INIT_P0
- PBF_REG_INIT_P1
- PBF_REG_INIT_P4
- PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
- PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
- PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
- PBF_REG_MAC_IF0_ENABLE
- PBF_REG_MAC_IF1_ENABLE
- PBF_REG_MAC_LB_ENABLE
- PBF_REG_MUST_HAVE_HDRS
- PBF_REG_NGE_COMP_VER
- PBF_REG_NGE_PORT
- PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0
- PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0
- PBF_REG_NUM_STRICT_ARB_SLOTS
- PBF_REG_P0_ARB_THRSH
- PBF_REG_P0_CREDIT
- PBF_REG_P0_INIT_CRD
- PBF_REG_P0_INTERNAL_CRD_FREED_CNT
- PBF_REG_P0_PAUSE_ENABLE
- PBF_REG_P0_TASK_CNT
- PBF_REG_P0_TQ_LINES_FREED_CNT
- PBF_REG_P0_TQ_OCCUPANCY
- PBF_REG_P1_CREDIT
- PBF_REG_P1_INIT_CRD
- PBF_REG_P1_INTERNAL_CRD_FREED_CNT
- PBF_REG_P1_TASK_CNT
- PBF_REG_P1_TQ_LINES_FREED_CNT
- PBF_REG_P1_TQ_OCCUPANCY
- PBF_REG_P4_CREDIT
- PBF_REG_P4_INIT_CRD
- PBF_REG_P4_INTERNAL_CRD_FREED_CNT
- PBF_REG_P4_TASK_CNT
- PBF_REG_P4_TQ_LINES_FREED_CNT
- PBF_REG_P4_TQ_OCCUPANCY
- PBF_REG_PBF_INT_MASK
- PBF_REG_PBF_INT_STS
- PBF_REG_PBF_PRTY_MASK
- PBF_REG_PBF_PRTY_STS
- PBF_REG_PBF_PRTY_STS_CLR
- PBF_REG_TAG_ETHERTYPE_0
- PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET
- PBF_REG_TAG_LEN_0
- PBF_REG_TQ_LINES_FREED_CNT_LB_Q
- PBF_REG_TQ_LINES_FREED_CNT_Q0
- PBF_REG_TQ_LINES_FREED_CNT_Q1
- PBF_REG_TQ_OCCUPANCY_LB_Q
- PBF_REG_TQ_OCCUPANCY_Q0
- PBF_REG_TQ_OCCUPANCY_Q1
- PBF_REG_VLAN_TYPE_0
- PBF_REG_VXLAN_PORT
- PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET
- PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET
- PBF_SYS_CTRL
- PBF_SYS_CTRL_HOST_RAM_WRITE
- PBF_SYS_CTRL_READY
- PBIA
- PBIAS_NUM_REGS
- PBIB
- PBIC
- PBINMXCTR
- PBINMXCTR_ENDIAN_0123
- PBINMXCTR_ENDIAN_1032
- PBINMXCTR_ENDIAN_2301
- PBINMXCTR_ENDIAN_3210
- PBINMXCTR_ENDIAN_MASK
- PBINMXCTR_INOUTSEL_IN
- PBINMXCTR_INOUTSEL_MASK
- PBINMXCTR_INOUTSEL_OUT
- PBINMXCTR_MEMFMT_16LR
- PBINMXCTR_MEMFMT_1CH
- PBINMXCTR_MEMFMT_4CH
- PBINMXCTR_MEMFMT_5_1CH_DMIX
- PBINMXCTR_MEMFMT_6CH
- PBINMXCTR_MEMFMT_7_1CH
- PBINMXCTR_MEMFMT_7_1CH_DMIX
- PBINMXCTR_MEMFMT_D0
- PBINMXCTR_MEMFMT_DMIX
- PBINMXCTR_MEMFMT_MASK
- PBINMXCTR_MEMFMT_STREAM
- PBINMXCTR_NCONNECT_CONNECT
- PBINMXCTR_NCONNECT_DISCONNECT
- PBINMXCTR_NCONNECT_MASK
- PBINMXCTR_PBINSEL_SHIFT
- PBINMXPAUSECTR0
- PBINMXPAUSECTR1
- PBLE_512_SHIFT
- PBLE_CHUNK_MEM
- PBLE_PER_PAGE
- PBLK2LBLK
- PBLK_BLK_ST_CLOSED
- PBLK_BLK_ST_OPEN
- PBLK_CACHE_NAME_LEN
- PBLK_CHUNK_RESET_DONE
- PBLK_CHUNK_RESET_FAILED
- PBLK_CHUNK_RESET_START
- PBLK_DATA_LINES
- PBLK_DEFAULT_OP
- PBLK_EMETA_TYPE_HEADER
- PBLK_EMETA_TYPE_LLBA
- PBLK_EMETA_TYPE_VSC
- PBLK_ERASE
- PBLK_EXPOSED_PAGE_SIZE
- PBLK_FLUSH_ENTRY
- PBLK_GC_L_QD
- PBLK_GC_MAX_READERS
- PBLK_GC_NR_LISTS
- PBLK_GC_RQ_QD
- PBLK_GEN_WS_POOL_SIZE
- PBLK_H_
- PBLK_IOTYPE_GC
- PBLK_IOTYPE_USER
- PBLK_LINEGC_EMPTY
- PBLK_LINEGC_FULL
- PBLK_LINEGC_HIGH
- PBLK_LINEGC_LOW
- PBLK_LINEGC_MID
- PBLK_LINEGC_NONE
- PBLK_LINEGC_WERR
- PBLK_LINESTATE_BAD
- PBLK_LINESTATE_CLOSED
- PBLK_LINESTATE_CORRUPT
- PBLK_LINESTATE_FREE
- PBLK_LINESTATE_GC
- PBLK_LINESTATE_NEW
- PBLK_LINESTATE_OPEN
- PBLK_LINETYPE_DATA
- PBLK_LINETYPE_FREE
- PBLK_LINETYPE_LOG
- PBLK_LINE_EMPTY
- PBLK_MAGIC
- PBLK_MAX_LUNS_BITMAP
- PBLK_NR_CLOSE_JOBS
- PBLK_READ
- PBLK_READ_RECOV
- PBLK_RECOVERY_SECTORS
- PBLK_RL_HIGH
- PBLK_RL_LOW
- PBLK_RL_MID
- PBLK_RL_OFF
- PBLK_RL_WERR
- PBLK_SECTOR
- PBLK_STATE_RECOVERING
- PBLK_STATE_RUNNING
- PBLK_STATE_STOPPED
- PBLK_STATE_STOPPING
- PBLK_SUBMITTED_ENTRY
- PBLK_USER_HIGH_THRS
- PBLK_USER_LOW_THRS
- PBLK_WRITABLE_ENTRY
- PBLK_WRITE
- PBLK_WRITE_INT
- PBLK_WRITTEN_DATA
- PBLOCK
- PBL_0
- PBL_1
- PBL_16
- PBL_2
- PBL_32
- PBL_4
- PBL_8
- PBL_BOUND_ERR_CH0_F
- PBL_BOUND_ERR_CH0_S
- PBL_BOUND_ERR_CH0_V
- PBL_BOUND_ERR_CH1_F
- PBL_BOUND_ERR_CH1_S
- PBL_BOUND_ERR_CH1_V
- PBL_BOUND_ERR_CH2_F
- PBL_BOUND_ERR_CH2_S
- PBL_BOUND_ERR_CH2_V
- PBL_BOUND_ERR_CH3_F
- PBL_BOUND_ERR_CH3_S
- PBL_BOUND_ERR_CH3_V
- PBL_LVL_0
- PBL_LVL_1
- PBL_LVL_2
- PBL_LVL_MAX
- PBL_OFF
- PBMR
- PBM_CHIP_TYPE_PSYCHO
- PBM_CHIP_TYPE_SABRE
- PBM_CHIP_TYPE_SCHIZO
- PBM_CHIP_TYPE_SCHIZO_PLUS
- PBM_CHIP_TYPE_TOMATILLO
- PBM_PCIX_M1_100MHZ
- PBM_PCIX_M1_133MHZ
- PBM_PCIX_M1_66MHZ
- PBM_PCIX_M2_100MHZ
- PBM_PCIX_M2_133MHZ
- PBM_PCIX_M2_66MHZ
- PBM_PCI_33MHZ
- PBM_PCI_66MHZ
- PBOOK_FEATURES
- PBOUTMXCTR0
- PBOUTMXCTR0_ENDIAN_0123
- PBOUTMXCTR0_ENDIAN_1032
- PBOUTMXCTR0_ENDIAN_2301
- PBOUTMXCTR0_ENDIAN_3210
- PBOUTMXCTR0_ENDIAN_MASK
- PBOUTMXCTR0_MEMFMT_10CH
- PBOUTMXCTR0_MEMFMT_1CH
- PBOUTMXCTR0_MEMFMT_2CH
- PBOUTMXCTR0_MEMFMT_4CH
- PBOUTMXCTR0_MEMFMT_6CH
- PBOUTMXCTR0_MEMFMT_8CH
- PBOUTMXCTR0_MEMFMT_MASK
- PBOUTMXCTR0_MEMFMT_STREAM
- PBOUTMXCTR1
- PBOUTMXINTCTR
- PBP
- PBPUEN
- PBPUEN_ADDR
- PBP_1024
- PBP_128
- PBP_256
- PBP_512
- PBP_64
- PBP_8723B
- PBP_PAGE_SIZE_1024
- PBP_PAGE_SIZE_128
- PBP_PAGE_SIZE_256
- PBP_PAGE_SIZE_512
- PBP_PAGE_SIZE_64
- PBP_PAGE_SIZE_RX_SHIFT
- PBP_PAGE_SIZE_TX_SHIFT
- PBR
- PBR_SIGNATURE
- PBSEL
- PBSEL_ADDR
- PBSIZE
- PBSR
- PBSSIDInfo
- PBSS_HT
- PBTCDBGINFO
- PBTC_ANTENNA_POS
- PBTC_BOARD_INFO
- PBTC_BT_INFO
- PBTC_BT_LINK_INFO
- PBTC_BT_REG_TYPE
- PBTC_CHIP_INTERFACE
- PBTC_CHIP_TYPE
- PBTC_COEXIST
- PBTC_DBG_DISP_TYPE
- PBTC_DBG_OPCODE
- PBTC_GET_TYPE
- PBTC_NOTIFY_TYPE_ASSOCIATE
- PBTC_NOTIFY_TYPE_IPS
- PBTC_NOTIFY_TYPE_LPS
- PBTC_NOTIFY_TYPE_MEDIA_STATUS
- PBTC_NOTIFY_TYPE_SCAN
- PBTC_NOTIFY_TYPE_SPECIAL_PACKET
- PBTC_NOTIFY_TYPE_STACK_OPERATION
- PBTC_POWERSAVE_TYPE
- PBTC_RSSI_STATE
- PBTC_SET_TYPE
- PBTC_STACK_INFO
- PBTC_STATISTICS
- PBTC_WIFI_BW_MODE
- PBTC_WIFI_PNP
- PBTC_WIFI_ROLE
- PBTC_WIFI_TRAFFIC_DIR
- PBT_8723B_1ANT_BT_STATUS
- PBT_8723B_1ANT_COEX_ALGO
- PBT_8723B_1ANT_WIFI_STATUS
- PBT_8723B_2ANT_BT_STATUS
- PBT_8723B_2ANT_COEX_ALGO
- PBT_COEXIST
- PBT_INFO_SRC_8723B_1ANT
- PBT_INFO_SRC_8723B_2ANT
- PBT_WIFI_COEX_STATE
- PBUFSIZE_16K
- PBUFSIZE_1K
- PBUFSIZE_1P
- PBUFSIZE_2K
- PBUFSIZE_2P
- PBUFSIZE_32K
- PBUFSIZE_4K
- PBUFSIZE_8K
- PBUFSIZE_NONE
- PBUSY
- PBUS_ADDR
- PBUS_CMD
- PBUS_CS_CTRL
- PBUS_DATA
- PBUS_Def
- PBUS_IORDY
- PBUS_Mask
- PBUS_PAD_MODE
- PBUS_Print
- PBUS_REGS_ADDR
- PBUS_REGS_CNT
- PBUS_Read
- PBUS_SEG_NUM
- PBUS_Val
- PBUS_Write
- PBUTTON
- PBUTTON_HOLDDOWN_COUNT
- PB_24K_MODE
- PB_ABORTFRAME
- PB_ADCGAINH
- PB_ADCGAINL
- PB_ADCGLOBALGAIN
- PB_ADCMAXGAIN
- PB_ADCMINGAIN
- PB_BASE
- PB_BGAIN
- PB_CAPABILITY_ERROR_CHECK
- PB_CAPABILITY_SMBALERT
- PB_CFILLIN
- PB_CML_FAULT_INVALID_COMMAND
- PB_CML_FAULT_INVALID_DATA
- PB_CML_FAULT_MEMORY
- PB_CML_FAULT_OTHER_COMM
- PB_CML_FAULT_OTHER_MEM_LOGIC
- PB_CML_FAULT_PACKET_ERROR
- PB_CML_FAULT_PROCESSOR
- PB_CONTROL
- PB_CSB0
- PB_CSB1
- PB_CSC0_RAS0
- PB_CSC1_RAS1
- PB_CSD0_CAS0
- PB_CSD1_CAS1
- PB_CSTART
- PB_CURRENT_SHARE_FAULT
- PB_CWSIZE
- PB_D
- PB_D0
- PB_D1
- PB_D2
- PB_D3
- PB_D4
- PB_D5
- PB_D6
- PB_D7
- PB_DIV_ENABLE
- PB_DIV_MASK
- PB_DIV_MAX
- PB_DIV_MIN
- PB_DIV_READY
- PB_DIV_SHIFT
- PB_EXPGAIN
- PB_FAN_1_INSTALLED
- PB_FAN_1_PULSE_MASK
- PB_FAN_1_RPM
- PB_FAN_2_INSTALLED
- PB_FAN_2_PULSE_MASK
- PB_FAN_2_RPM
- PB_FAN_AIRFLOW_FAULT
- PB_FAN_AIRFLOW_WARNING
- PB_FAN_FAN1_FAULT
- PB_FAN_FAN1_SPEED_OVERRIDE
- PB_FAN_FAN1_WARNING
- PB_FAN_FAN2_FAULT
- PB_FAN_FAN2_SPEED_OVERRIDE
- PB_FAN_FAN2_WARNING
- PB_FINTTIME
- PB_G1GAIN
- PB_G2GAIN
- PB_I2C_BUSY
- PB_I2C_BWEN
- PB_IDENT
- PB_IIN_OC_FAULT
- PB_IIN_OC_WARNING
- PB_IOUT_OC_FAULT
- PB_IOUT_OC_LV_FAULT
- PB_IOUT_OC_WARNING
- PB_IOUT_UC_FAULT
- PB_MASK
- PB_NUM_STATUS_REG
- PB_OPERATION_CONTROL_ON
- PB_PIN_OP_WARNING
- PB_POUT_OP_FAULT
- PB_POUT_OP_WARNING
- PB_POWER_LIMITING
- PB_PREADCTRL
- PB_PWMO
- PB_R12
- PB_R15
- PB_R16
- PB_R17
- PB_R18
- PB_R19
- PB_R20
- PB_R21
- PB_R22
- PB_R24
- PB_R240
- PB_R241
- PB_R242
- PB_R25
- PB_R26
- PB_R27
- PB_R28
- PB_R29
- PB_R30
- PB_R31
- PB_R33
- PB_R34
- PB_R35
- PB_R36
- PB_R37
- PB_R38
- PB_R39
- PB_R40
- PB_R41
- PB_R42
- PB_R47
- PB_R48
- PB_R49
- PB_R50
- PB_R54
- PB_R55
- PB_R56
- PB_R58
- PB_R61
- PB_R62
- PB_R63
- PB_R64
- PB_R65
- PB_R66
- PB_R67
- PB_REG_PB_INT_MASK
- PB_REG_PB_INT_STS
- PB_REG_PB_PRTY_MASK
- PB_REG_PB_PRTY_STS
- PB_REG_PB_PRTY_STS_CLR
- PB_RESET
- PB_RGAIN
- PB_RINTTIME
- PB_ROWSPEED
- PB_RSTART
- PB_RWSIZE
- PB_STATUS
- PB_STATUS_BASE
- PB_STATUS_BUSY
- PB_STATUS_CML
- PB_STATUS_FAN34_BASE
- PB_STATUS_FANS
- PB_STATUS_FAN_BASE
- PB_STATUS_INPUT
- PB_STATUS_INPUT_BASE
- PB_STATUS_IOUT_BASE
- PB_STATUS_IOUT_OC
- PB_STATUS_IOUT_POUT
- PB_STATUS_NONE_ABOVE
- PB_STATUS_OFF
- PB_STATUS_OTHER
- PB_STATUS_POWER_GOOD_N
- PB_STATUS_TEMPERATURE
- PB_STATUS_TEMP_BASE
- PB_STATUS_UNKNOWN
- PB_STATUS_VIN_UV
- PB_STATUS_VMON_BASE
- PB_STATUS_VOUT
- PB_STATUS_VOUT_BASE
- PB_STATUS_VOUT_OV
- PB_STATUS_WORD_MFR
- PB_TEMP_OT_FAULT
- PB_TEMP_OT_WARNING
- PB_TEMP_UT_FAULT
- PB_TEMP_UT_WARNING
- PB_TIN_TOUT
- PB_UNDERRUN
- PB_UNDERRUN_IRQ
- PB_UPDATEINT
- PB_VBL
- PB_VOFFSET
- PB_VOLTAGE_OV_FAULT
- PB_VOLTAGE_OV_WARNING
- PB_VOLTAGE_UV_FAULT
- PB_VOLTAGE_UV_WARNING
- PB_VOUT_MODE_DIRECT
- PB_VOUT_MODE_LINEAR
- PB_VOUT_MODE_MODE_MASK
- PB_VOUT_MODE_PARAM_MASK
- PB_VOUT_MODE_VID
- PB_XHFC_IRQ1
- PB_XHFC_IRQ2
- PB_XHFC_IRQ3
- PB_XHFC_IRQ4
- PB_migrate
- PB_migrate_end
- PB_migrate_skip
- PB_migratetype_bits
- PBlockEncKey
- PBlockLen
- PC
- PC0MD_0
- PC0MD_00
- PC0MD_01
- PC0MD_1
- PC0MD_10
- PC0_DATA
- PC0_FN
- PC0_IN
- PC0_IOR_IN
- PC0_IOR_OUT
- PC0_OFF
- PC0_OUT
- PC1
- PC10
- PC100
- PC104PLUS_INTA_IRQ
- PC104PLUS_INTA_PIN
- PC104PLUS_INTB_IRQ
- PC104PLUS_INTB_PIN
- PC104PLUS_INTC_IRQ
- PC104PLUS_INTC_PIN
- PC104PLUS_INTD_IRQ
- PC104PLUS_INTD_PIN
- PC104_IO_BASE
- PC104_MEM_BASE
- PC10MD_0
- PC10MD_00
- PC10MD_01
- PC10MD_1
- PC10MD_10
- PC10_AIN_SLCDC1_DAT12
- PC10_DATA
- PC10_IN
- PC10_IOR_IN
- PC10_IOR_OUT
- PC10_OUT
- PC10_PF_USBOTG_DATA2
- PC10_PF_USBOTG_TXDM
- PC110PAD_MINOR
- PC110PAD_OFF
- PC110PAD_ON
- PC11MD_00
- PC11MD_01
- PC11MD_10
- PC11_AIN_SLCDC1_DAT13
- PC11_DATA
- PC11_IN
- PC11_IOR_IN
- PC11_IOR_OUT
- PC11_OUT
- PC11_PF_USBOTG_DATA1
- PC11_PF_USBOTG_TXDP
- PC12MD_0
- PC12MD_1
- PC12_AIN_SLCDC1_DAT14
- PC12_DATA
- PC12_IN
- PC12_IOR_IN
- PC12_IOR_OUT
- PC12_OUT
- PC12_PF_USBOTG_DATA4
- PC12_PF_USBOTG_RXDM
- PC13MD_0
- PC13MD_1
- PC13_AIN_SLCDC1_DAT15
- PC13_DATA
- PC13_IN
- PC13_IOR_IN
- PC13_IOR_OUT
- PC13_OUT
- PC13_PF_USBOTG_DATA3
- PC13_PF_USBOTG_RXDP
- PC14MD_0
- PC14MD_1
- PC14_AIN_SSI1_MCLK
- PC14_AIN_SYS_CLK
- PC14_AOUT_GPT6_TIN
- PC14_BIN_SSI2_MCLK
- PC14_BIN_SYS_CLK
- PC14_DATA
- PC14_IN
- PC14_IOR_IN
- PC14_IOR_OUT
- PC14_OUT
- PC14_PF_TOUT
- PC15_AIN_GPT6_TOUT
- PC15_AOUT_WKGD
- PC15_PF_TIN
- PC16_PF_SAP_FS
- PC16_PF_SSI4_FS
- PC17_BOUT_PC_IOIS16
- PC17_PF_SAP_RXD
- PC17_PF_SSI4_RXD
- PC18_BOUT_PC_BVD2
- PC18_PF_SAP_TXD
- PC18_PF_SSI4_TXD
- PC19_BOUT_PC_BVD1
- PC19_PF_SAP_CLK
- PC19_PF_SSI4_CLK
- PC1MD_0
- PC1MD_1
- PC1_BREAK
- PC1_DATA
- PC1_FN
- PC1_IN
- PC1_IOR_IN
- PC1_IOR_OUT
- PC1_OFF
- PC1_ON
- PC1_OUT
- PC2
- PC20_PF_SSI1_FS
- PC21_PF_SSI1_RXD
- PC22_PF_SSI1_TXD
- PC23_PF_SSI1_CLK
- PC24_AF_GPT5_TOUT
- PC24_PF_SSI2_FS
- PC25_AF_GPT5_TIN
- PC25_PF_SSI2_RXD
- PC263_DO_0_7_REG
- PC263_DO_8_15_REG
- PC26_AF_GPT4_TOUT
- PC26_PF_SSI2_TXD
- PC27_AF_GPT4_TIN
- PC27_PF_SSI2_CLK
- PC28_AF_SLCDC2_D0
- PC28_BOUT_PC_BVD2
- PC28_PF_SSI3_FS
- PC29_AF_SLCDC2_RS
- PC29_BOUT_PC_VS1
- PC29_PF_SSI3_RXD
- PC2CAL
- PC2H_EVT_HDR
- PC2MD_0
- PC2MD_00
- PC2MD_01
- PC2MD_1
- PC2MD_10
- PC2MD_11
- PC2MLSE
- PC2PM
- PC2_DATA
- PC2_FN
- PC2_IN
- PC2_IOR_IN
- PC2_IOR_OUT
- PC2_OUT
- PC2_TRACE
- PC3
- PC300_CHMEDIA_MASK
- PC300_CLKSEL_MASK
- PC300_CTYPE_MASK
- PC300_PLX_SIZE
- PC300_RSV
- PC300_SCA_SIZE
- PC300_TE
- PC300_X21
- PC30_AF_SLCDC2_CS
- PC30_BOUT_PC_READY
- PC30_PF_SSI3_TXD
- PC31_AF_SLCDC2_CLK
- PC31_BOUT_PC_WAIT
- PC31_PF_SSI3_CLK
- PC3MD_0
- PC3MD_00
- PC3MD_01
- PC3MD_1
- PC3MD_10
- PC3MD_11
- PC3_CONNECT
- PC3_DATA
- PC3_DIRC1
- PC3_FN
- PC3_IN
- PC3_IOR_IN
- PC3_IOR_OUT
- PC3_OUT
- PC3_TXDAT
- PC4500_accessrid
- PC4500_readrid
- PC4500_writerid
- PC4MD_0
- PC4MD_00
- PC4MD_01
- PC4MD_1
- PC4MD_10
- PC4MD_11
- PC4_DATA
- PC4_FN
- PC4_IN
- PC4_IOR_IN
- PC4_IOR_OUT
- PC4_NEXT
- PC4_OUT
- PC5MD_0
- PC5MD_00
- PC5MD_000
- PC5MD_001
- PC5MD_01
- PC5MD_010
- PC5MD_011
- PC5MD_1
- PC5MD_10
- PC5MD_100
- PC5MD_101
- PC5MD_11
- PC5MD_110
- PC5MD_111
- PC5_AIN_SLCDC1_DAT7
- PC5_DATA
- PC5_FN
- PC5_IN
- PC5_IOR_IN
- PC5_IOR_OUT
- PC5_OUT
- PC5_PF_I2C2_SDA
- PC5_PF_USBOTG_SDA
- PC5_SIGNAL
- PC6
- PC6MD_0
- PC6MD_00
- PC6MD_000
- PC6MD_001
- PC6MD_01
- PC6MD_010
- PC6MD_011
- PC6MD_1
- PC6MD_10
- PC6MD_100
- PC6MD_101
- PC6MD_11
- PC6MD_110
- PC6MD_111
- PC6_AIN_SLCDC1_DAT8
- PC6_DATA
- PC6_FN
- PC6_IN
- PC6_IOR_IN
- PC6_IOR_OUT
- PC6_JOIN
- PC6_OUT
- PC6_PF_I2C2_SCL
- PC6_PF_USBOTG_SCL
- PC7
- PC7MD_0
- PC7MD_00
- PC7MD_000
- PC7MD_001
- PC7MD_01
- PC7MD_010
- PC7MD_011
- PC7MD_1
- PC7MD_10
- PC7MD_100
- PC7MD_101
- PC7MD_11
- PC7MD_110
- PC7MD_111
- PC7_AIN_SLCDC1_DAT9
- PC7_DATA
- PC7_FN
- PC7_IN
- PC7_IOR_IN
- PC7_IOR_OUT
- PC7_OUT
- PC7_PF_USBOTG_DATA5
- PC7_PF_USBOTG_ON
- PC7_VERIFY
- PC8
- PC87303
- PC87306
- PC87312
- PC87332
- PC87334
- PC87360_EXTENT
- PC87360_REG_FAN
- PC87360_REG_FAN_MIN
- PC87360_REG_FAN_STATUS
- PC87360_REG_PRESCALE
- PC87360_REG_PWM
- PC87365_REG_BANK
- PC87365_REG_IN
- PC87365_REG_IN_ALARMS1
- PC87365_REG_IN_ALARMS2
- PC87365_REG_IN_CONFIG
- PC87365_REG_IN_CONVRATE
- PC87365_REG_IN_MAX
- PC87365_REG_IN_MIN
- PC87365_REG_IN_STATUS
- PC87365_REG_TEMP
- PC87365_REG_TEMP_ALARMS
- PC87365_REG_TEMP_CONFIG
- PC87365_REG_TEMP_CRIT
- PC87365_REG_TEMP_MAX
- PC87365_REG_TEMP_MIN
- PC87365_REG_TEMP_STATUS
- PC87365_REG_VID
- PC8736X_GPIO_CT
- PC8736X_GPIO_RANGE
- PC87427_REG_BANK
- PC87427_REG_FAN
- PC87427_REG_FAN_MIN
- PC87427_REG_FAN_STATUS
- PC87427_REG_PWM_DUTY
- PC87427_REG_PWM_ENABLE
- PC87427_REG_TEMP
- PC87427_REG_TEMP_CRIT
- PC87427_REG_TEMP_MAX
- PC87427_REG_TEMP_MIN
- PC87427_REG_TEMP_STATUS
- PC87427_REG_TEMP_TYPE
- PC8MD_0
- PC8MD_00
- PC8MD_000
- PC8MD_001
- PC8MD_01
- PC8MD_010
- PC8MD_011
- PC8MD_1
- PC8MD_10
- PC8MD_100
- PC8MD_101
- PC8MD_11
- PC8MD_110
- PC8MD_111
- PC8_ACTIVE
- PC8_AF_FEC_MDIO
- PC8_AIN_SLCDC1_DAT10
- PC8_AOUT_USBOTG_TXR_INT
- PC8_DATA
- PC8_IN
- PC8_IOR_IN
- PC8_IOR_OUT
- PC8_OUT
- PC8_PF_USBOTG_DATA6
- PC8_PF_USBOTG_FS
- PC9
- PC9MD_0
- PC9MD_1
- PC9_AIN_SLCDC1_DAT11
- PC9_DATA
- PC9_IN
- PC9_IOR_IN
- PC9_IOR_OUT
- PC9_MAINT
- PC9_OUT
- PC9_PF_USBOTG_DATA0
- PC9_PF_USBOTG_OE
- PCA
- PCA200E_CTRL_2_CACHE_WRT_INVAL
- PCA200E_CTRL_CONVERT_ENDIAN
- PCA200E_CTRL_DIS_CACHE_RD
- PCA200E_CTRL_DIS_WRT_INVAL
- PCA200E_CTRL_ENA_CONT_REQ_MODE
- PCA200E_CTRL_IGN_LAT_TIMER
- PCA200E_CTRL_LARGE_PCI_BURSTS
- PCA200E_HCR_CLRINTR
- PCA200E_HCR_ESPHOLD
- PCA200E_HCR_HOLD_ACK
- PCA200E_HCR_HOLD_LOCK
- PCA200E_HCR_I960FAIL
- PCA200E_HCR_INFULL
- PCA200E_HCR_INTRA
- PCA200E_HCR_INTRB
- PCA200E_HCR_OFFSET
- PCA200E_HCR_OUTFULL
- PCA200E_HCR_RESET
- PCA200E_HCR_TESTMODE
- PCA200E_IMR_OFFSET
- PCA200E_IOSPACE_LENGTH
- PCA200E_PCI_LATENCY
- PCA200E_PCI_MASTER_CTRL
- PCA200E_PCI_THRESHOLD
- PCA200E_PSR_OFFSET
- PCA56_CPU
- PCA57_CPU
- PCA935X_GPIO_BASE
- PCA9532_KEEP
- PCA9532_LED_TIMER2
- PCA9532_OFF
- PCA9532_ON
- PCA9532_PWM0
- PCA9532_PWM1
- PCA9532_REG_INPUT
- PCA9532_REG_OFFSET
- PCA9532_REG_PSC
- PCA9532_REG_PWM
- PCA9532_TYPE_GPIO
- PCA9532_TYPE_LED
- PCA9532_TYPE_N2100_BEEP
- PCA9532_TYPE_NONE
- PCA9534_I2C_ADDR
- PCA9539
- PCA9539A_MCI1_CD
- PCA9539A_MCI1_WP
- PCA9539A_MCI3_CD
- PCA9539A_MCI3_WP
- PCA9539A_MCI_CD
- PCA9539A_MCI_WP
- PCA9539_74_GPIO_BASE
- PCA9539_75_GPIO_BASE
- PCA9539_76_GPIO_BASE
- PCA9539_77_GPIO_BASE
- PCA953X_DIRECTION
- PCA953X_INPUT
- PCA953X_INVERT
- PCA953X_OUTPUT
- PCA953X_TYPE
- PCA953x_BANK_CONFIG
- PCA953x_BANK_INPUT
- PCA953x_BANK_OUTPUT
- PCA953x_BANK_POLARITY
- PCA9541_CONTROL
- PCA9541_CTL_BUSINIT
- PCA9541_CTL_BUSON
- PCA9541_CTL_MYBUS
- PCA9541_CTL_NBUSON
- PCA9541_CTL_NMYBUS
- PCA9541_CTL_NTESTON
- PCA9541_CTL_TESTON
- PCA9541_ISTAT
- PCA9541_ISTAT_BUSINIT
- PCA9541_ISTAT_BUSLOST
- PCA9541_ISTAT_BUSOK
- PCA9541_ISTAT_INTIN
- PCA9541_ISTAT_MYTEST
- PCA9541_ISTAT_NMYTEST
- PCA954X_IRQ_OFFSET
- PCA954X_MAX_NCHANS
- PCA9553_1_SLAVEADDR
- PCA9553_FAST
- PCA9553_HIGHZ
- PCA9553_LED
- PCA9553_LED_FAST
- PCA9553_LED_MASK
- PCA9553_LED_OFF
- PCA9553_LED_OFF_ALL
- PCA9553_LED_ON
- PCA9553_LED_SLOW
- PCA9553_LED_STATE
- PCA9553_LOW
- PCA9553_LS0_INIT
- PCA9553_OFF
- PCA9553_ON
- PCA9553_PWM0
- PCA9553_PWM1
- PCA9553_SLOW
- PCA9554_DEV
- PCA9554_DIR
- PCA9554_IN
- PCA9554_INVERT
- PCA9554_OUT
- PCA955X_GPIO_HIGH
- PCA955X_GPIO_INPUT
- PCA955X_GPIO_LOW
- PCA955X_LS_BLINK0
- PCA955X_LS_BLINK1
- PCA955X_LS_LED_OFF
- PCA955X_LS_LED_ON
- PCA955X_TYPE_GPIO
- PCA955X_TYPE_LED
- PCA955X_TYPE_NONE
- PCA9564_ADDR
- PCA9564_PROTO_32BIT_ADDR
- PCA9564_SIZE
- PCA957X_BKEN
- PCA957X_CFG
- PCA957X_IN
- PCA957X_INTS
- PCA957X_INVRT
- PCA957X_MSK
- PCA957X_OUT
- PCA957X_PUPD
- PCA957X_TYPE
- PCA957x_BANK_BUSHOLD
- PCA957x_BANK_CONFIG
- PCA957x_BANK_INPUT
- PCA957x_BANK_OUTPUT
- PCA957x_BANK_POLARITY
- PCA963X_BLINK_PERIOD_MAX
- PCA963X_BLINK_PERIOD_MIN
- PCA963X_HW_BLINK
- PCA963X_INVERTED
- PCA963X_LED_GRP_PWM
- PCA963X_LED_OFF
- PCA963X_LED_ON
- PCA963X_LED_PWM
- PCA963X_MODE1
- PCA963X_MODE2
- PCA963X_MODE2_DMBLNK
- PCA963X_MODE2_INVRT
- PCA963X_MODE2_OUTDRV
- PCA963X_NORMAL
- PCA963X_OPEN_DRAIN
- PCA963X_PWM_BASE
- PCA963X_SW_BLINK
- PCA963X_TOTEM_POLE
- PCA9685_ALLCALLADDR
- PCA9685_ALL_LED_OFF_H
- PCA9685_ALL_LED_OFF_L
- PCA9685_ALL_LED_ON_H
- PCA9685_ALL_LED_ON_L
- PCA9685_COUNTER_RANGE
- PCA9685_DEFAULT_PERIOD
- PCA9685_LEDX_OFF_H
- PCA9685_LEDX_OFF_L
- PCA9685_LEDX_ON_H
- PCA9685_LEDX_ON_L
- PCA9685_MAXCHAN
- PCA9685_MODE1
- PCA9685_MODE2
- PCA9685_NUMREGS
- PCA9685_OSC_CLOCK_MHZ
- PCA9685_PRESCALE
- PCA9685_PRESCALE_MAX
- PCA9685_PRESCALE_MIN
- PCA9685_SUBADDR1
- PCA9685_SUBADDR2
- PCA9685_SUBADDR3
- PCAL6524_DEBOUNCE
- PCAL6524_INT_CLR
- PCAL6524_INT_EDGE
- PCAL6524_IN_STATUS
- PCAL6524_OUT_INDCONF
- PCAL953X_INT_MASK
- PCAL953X_INT_STAT
- PCAL953X_IN_LATCH
- PCAL953X_OUT_CONF
- PCAL953X_OUT_STRENGTH
- PCAL953X_PULL_EN
- PCAL953X_PULL_SEL
- PCAL9555A_NUM
- PCAL9xxx_BANK_IN_LATCH
- PCAL9xxx_BANK_IRQ_MASK
- PCAL9xxx_BANK_IRQ_STAT
- PCAL9xxx_BANK_PULL_EN
- PCAL9xxx_BANK_PULL_SEL
- PCAL_GPIO_MASK
- PCAL_PINCTRL_MASK
- PCANFD_ECHO_SKB_DEF
- PCANFD_ECHO_SKB_MAX
- PCAN_CPCIEFD_ID
- PCAN_M2_ID
- PCAN_MINIPCIEFD_ID
- PCAN_PCIE104FD_ID
- PCAN_PCIEFD_OEM_ID
- PCAN_UFD_CLK_20MHZ
- PCAN_UFD_CLK_24MHZ
- PCAN_UFD_CLK_30MHZ
- PCAN_UFD_CLK_40MHZ
- PCAN_UFD_CLK_60MHZ
- PCAN_UFD_CLK_80MHZ
- PCAN_UFD_CLK_DEF
- PCAN_UFD_CMD_BUFFER_SIZE
- PCAN_UFD_CMD_CLK_SET
- PCAN_UFD_CMD_LED_SET
- PCAN_UFD_CMD_TIMEOUT_MS
- PCAN_UFD_CRYSTAL_HZ
- PCAN_UFD_FLTEXT_CALIBRATION
- PCAN_UFD_LED_DEF
- PCAN_UFD_LED_DEV
- PCAN_UFD_LED_FAST
- PCAN_UFD_LED_OFF
- PCAN_UFD_LED_ON
- PCAN_UFD_LED_SLOW
- PCAN_UFD_LOSPD_PKT_SIZE
- PCAN_UFD_MSG_CALIBRATION
- PCAN_UFD_MSG_OVERRUN
- PCAN_UFD_OVMSG_CHANNEL
- PCAN_UFD_RX_BUFFER_SIZE
- PCAN_UFD_TX_BUFFER_SIZE
- PCAN_USBCHIP_PRODUCT_ID
- PCAN_USBFD_CHANNEL_COUNT
- PCAN_USBFD_PRODUCT_ID
- PCAN_USBPROFD_CHANNEL_COUNT
- PCAN_USBPROFD_PRODUCT_ID
- PCAN_USBPRO_CHANNEL_COUNT
- PCAN_USBPRO_CMD_BUFFER_SIZE
- PCAN_USBPRO_COMMAND_TIMEOUT
- PCAN_USBPRO_CRYSTAL_HZ
- PCAN_USBPRO_EP_CMDIN
- PCAN_USBPRO_EP_CMDOUT
- PCAN_USBPRO_EP_MSGIN
- PCAN_USBPRO_EP_MSGOUT_0
- PCAN_USBPRO_EP_MSGOUT_1
- PCAN_USBPRO_EP_UNUSED
- PCAN_USBPRO_EXT
- PCAN_USBPRO_FCT_DRVLD
- PCAN_USBPRO_FCT_DRVLD_REQ_LEN
- PCAN_USBPRO_GETDEVID
- PCAN_USBPRO_INFO_BL
- PCAN_USBPRO_INFO_FW
- PCAN_USBPRO_MSG_HEADER_LEN
- PCAN_USBPRO_PRODUCT_ID
- PCAN_USBPRO_REQ_FCT
- PCAN_USBPRO_REQ_INFO
- PCAN_USBPRO_RSP_SUBMIT_MAX
- PCAN_USBPRO_RTR
- PCAN_USBPRO_RXMSG0
- PCAN_USBPRO_RXMSG4
- PCAN_USBPRO_RXMSG8
- PCAN_USBPRO_RXRTR
- PCAN_USBPRO_RXSTATUS
- PCAN_USBPRO_RXTS
- PCAN_USBPRO_RX_BUFFER_SIZE
- PCAN_USBPRO_SETBTR
- PCAN_USBPRO_SETBUSACT
- PCAN_USBPRO_SETFILTR
- PCAN_USBPRO_SETLED
- PCAN_USBPRO_SETSILENT
- PCAN_USBPRO_SETTS
- PCAN_USBPRO_STATUS_BUS
- PCAN_USBPRO_STATUS_ERROR
- PCAN_USBPRO_STATUS_OVERRUN
- PCAN_USBPRO_STATUS_QOVERRUN
- PCAN_USBPRO_TXMSG0
- PCAN_USBPRO_TXMSG4
- PCAN_USBPRO_TXMSG8
- PCAN_USBPRO_TX_BUFFER_SIZE
- PCAN_USBX6_PRODUCT_ID
- PCAN_USB_CMD_ARGS
- PCAN_USB_CMD_ARGS_LEN
- PCAN_USB_CMD_FUNC
- PCAN_USB_CMD_LEN
- PCAN_USB_CMD_NUM
- PCAN_USB_COMMAND_TIMEOUT
- PCAN_USB_CORE_H
- PCAN_USB_CRYSTAL_HZ
- PCAN_USB_DRIVER_NAME
- PCAN_USB_EP_CMDIN
- PCAN_USB_EP_CMDOUT
- PCAN_USB_EP_MSGIN
- PCAN_USB_EP_MSGOUT
- PCAN_USB_ERROR_BUS_HEAVY
- PCAN_USB_ERROR_BUS_LIGHT
- PCAN_USB_ERROR_BUS_OFF
- PCAN_USB_ERROR_QOVR
- PCAN_USB_ERROR_RXQEMPTY
- PCAN_USB_ERROR_RXQOVR
- PCAN_USB_ERROR_TXFULL
- PCAN_USB_ERROR_TXQFULL
- PCAN_USB_MAX_CHANNEL
- PCAN_USB_MAX_CMD_LEN
- PCAN_USB_MAX_RX_URBS
- PCAN_USB_MAX_TX_URBS
- PCAN_USB_MSG_HEADER_LEN
- PCAN_USB_PRODUCT_ID
- PCAN_USB_PRO_H
- PCAN_USB_REC_ANALOG
- PCAN_USB_REC_BUSEVT
- PCAN_USB_REC_BUSLOAD
- PCAN_USB_REC_ERROR
- PCAN_USB_REC_TS
- PCAN_USB_RX_BUFFER_SIZE
- PCAN_USB_STARTUP_TIMEOUT
- PCAN_USB_STATE_CONNECTED
- PCAN_USB_STATE_STARTED
- PCAN_USB_STATUSLEN_DLC
- PCAN_USB_STATUSLEN_EXT_ID
- PCAN_USB_STATUSLEN_INTERNAL
- PCAN_USB_STATUSLEN_RTR
- PCAN_USB_STATUSLEN_TIMESTAMP
- PCAN_USB_TS_DIV_SHIFTER
- PCAN_USB_TS_US_PER_TICK
- PCAN_USB_TX_BUFFER_SIZE
- PCAN_USB_VENDOR_ID
- PCAP
- PCAP5_CC_MASK
- PCAP5_CC_SHIFT
- PCAP5_PC_MASK
- PCAP5_PC_SHIFT
- PCAP5_VC_MASK
- PCAP5_VC_SHIFT
- PCAPEXT_SR_SUPPORTED_MASK
- PCAP_ADC_ADA1_MASK
- PCAP_ADC_ADA1_SHIFT
- PCAP_ADC_ADA2_MASK
- PCAP_ADC_ADA2_SHIFT
- PCAP_ADC_ADEN
- PCAP_ADC_AD_SEL1
- PCAP_ADC_AD_SEL2
- PCAP_ADC_ATOX
- PCAP_ADC_ATO_IN_BURST
- PCAP_ADC_ATO_MASK
- PCAP_ADC_ATO_OUT_BURST
- PCAP_ADC_ATO_SHIFT
- PCAP_ADC_BANK_0
- PCAP_ADC_BANK_1
- PCAP_ADC_BATT_I_ADC
- PCAP_ADC_BATT_I_POLARITY
- PCAP_ADC_CH_AD6
- PCAP_ADC_CH_AD7
- PCAP_ADC_CH_AD8
- PCAP_ADC_CH_AD9
- PCAP_ADC_CH_BATT
- PCAP_ADC_CH_BPLUS
- PCAP_ADC_CH_CHARGER_ID
- PCAP_ADC_CH_COIN
- PCAP_ADC_CH_MOBPORTB
- PCAP_ADC_CH_TEMPERATURE
- PCAP_ADC_CH_TS_X1
- PCAP_ADC_CH_TS_X2
- PCAP_ADC_CH_TS_Y1
- PCAP_ADC_CH_TS_Y2
- PCAP_ADC_MAXQ
- PCAP_ADC_MTR1
- PCAP_ADC_MTR2
- PCAP_ADC_RAND
- PCAP_ADC_TS_M_MASK
- PCAP_ADC_TS_M_NONTS
- PCAP_ADC_TS_M_PLATE_X
- PCAP_ADC_TS_M_PLATE_Y
- PCAP_ADC_TS_M_PRESSURE
- PCAP_ADC_TS_M_SHIFT
- PCAP_ADC_TS_M_STANDBY
- PCAP_ADC_TS_M_XY
- PCAP_ADC_TS_REFENB
- PCAP_ADC_TS_REF_LOWPWR
- PCAP_ADC_T_IN_BURST
- PCAP_ADC_T_NOW
- PCAP_ADC_T_OUT_BURST
- PCAP_ADR_ADD1_MASK
- PCAP_ADR_ADD1_SHIFT
- PCAP_ADR_ADD2_MASK
- PCAP_ADR_ADD2_SHIFT
- PCAP_ADR_ADINC1
- PCAP_ADR_ADINC2
- PCAP_ADR_ASC
- PCAP_ADR_ONESHOT
- PCAP_BATT_BATT_DET_EN
- PCAP_BATT_B_FDBK
- PCAP_BATT_COIN_CH_EN
- PCAP_BATT_DAC_MASK
- PCAP_BATT_DAC_SHIFT
- PCAP_BATT_EOL_CMP_EN
- PCAP_BATT_EOL_SEL_MASK
- PCAP_BATT_EOL_SEL_SHIFT
- PCAP_BATT_EXT_ISENSE
- PCAP_BATT_I_COIN
- PCAP_BATT_THERMBIAS_CTRL
- PCAP_BATT_V_COIN_MASK
- PCAP_BATT_V_COIN_SHIFT
- PCAP_BL0
- PCAP_BL0_SHIFT
- PCAP_BL1
- PCAP_BL1_SHIFT
- PCAP_BL_MASK
- PCAP_BUSCTRL_BUS_PRI_ADJ
- PCAP_BUSCTRL_CURRLIM
- PCAP_BUSCTRL_FSENB
- PCAP_BUSCTRL_RS232ENB
- PCAP_BUSCTRL_RS232_DIR
- PCAP_BUSCTRL_SE0_CONN
- PCAP_BUSCTRL_USB_PD
- PCAP_BUSCTRL_USB_PDM
- PCAP_BUSCTRL_USB_PS
- PCAP_BUSCTRL_USB_PU
- PCAP_BUSCTRL_USB_SUSPEND
- PCAP_BUSCTRL_VBUS_PD_ENB
- PCAP_BUSCTRL_VUSB_EN
- PCAP_BUSCTRL_VUSB_MSTR_EN
- PCAP_CC_MASK
- PCAP_CC_SHIFT
- PCAP_CLEAR_INTERRUPT_REGISTER
- PCAP_CS_AH
- PCAP_FD
- PCAP_IRQ_1HZ
- PCAP_IRQ_ADCDONE
- PCAP_IRQ_ADCDONE2
- PCAP_IRQ_CLK
- PCAP_IRQ_DUMMY
- PCAP_IRQ_EOL
- PCAP_IRQ_HS
- PCAP_IRQ_MIC
- PCAP_IRQ_MNEXB
- PCAP_IRQ_MOBPORT
- PCAP_IRQ_ONOFF
- PCAP_IRQ_ONOFF2
- PCAP_IRQ_PC
- PCAP_IRQ_SOFTRESET
- PCAP_IRQ_ST
- PCAP_IRQ_SYSRST
- PCAP_IRQ_TODA
- PCAP_IRQ_TS
- PCAP_IRQ_USB1V
- PCAP_IRQ_USB4V
- PCAP_IRQ_WARM
- PCAP_IRQ_WH
- PCAP_IRQ_WL
- PCAP_LED0
- PCAP_LED0_C_SHIFT
- PCAP_LED0_EN
- PCAP_LED0_T_SHIFT
- PCAP_LED1
- PCAP_LED1_C_SHIFT
- PCAP_LED1_EN
- PCAP_LED1_T_SHIFT
- PCAP_LED_3MA
- PCAP_LED_4MA
- PCAP_LED_5MA
- PCAP_LED_9MA
- PCAP_LED_C_MASK
- PCAP_LED_T_MASK
- PCAP_MASK_ALL_INTERRUPT
- PCAP_NIRQS
- PCAP_PC_MASK
- PCAP_PC_SHIFT
- PCAP_RC_MASK
- PCAP_RC_SHIFT
- PCAP_REGISTER_ADDRESS_MASK
- PCAP_REGISTER_ADDRESS_SHIFT
- PCAP_REGISTER_NUMBER
- PCAP_REGISTER_READ_OP_BIT
- PCAP_REGISTER_VALUE_MASK
- PCAP_REGISTER_WRITE_OP_BIT
- PCAP_REG_ADC
- PCAP_REG_ADR
- PCAP_REG_AUXVREG
- PCAP_REG_AUXVREG_MASK
- PCAP_REG_BATT
- PCAP_REG_BUSCTRL
- PCAP_REG_CODEC
- PCAP_REG_GP
- PCAP_REG_INT_SEL
- PCAP_REG_ISR
- PCAP_REG_LOWPWR
- PCAP_REG_MSR
- PCAP_REG_MTRTMR
- PCAP_REG_PERIPH
- PCAP_REG_PERIPH_MASK
- PCAP_REG_PSTAT
- PCAP_REG_PWR
- PCAP_REG_RTC_DAY
- PCAP_REG_RTC_DAYA
- PCAP_REG_RTC_TOD
- PCAP_REG_RTC_TODA
- PCAP_REG_RX_AMPS
- PCAP_REG_ST_DAC
- PCAP_REG_SWCTRL
- PCAP_REG_TEST1
- PCAP_REG_TEST2
- PCAP_REG_TX_AMPS
- PCAP_REG_VENDOR_REV
- PCAP_REG_VENDOR_TEST1
- PCAP_REG_VENDOR_TEST2
- PCAP_REG_VREG1
- PCAP_REG_VREG2
- PCAP_REV_MASK
- PCAP_RTC_DAY_MASK
- PCAP_RTC_PC_MASK
- PCAP_RTC_TOD_MASK
- PCAP_SECOND_PORT
- PCAP_TC_MASK
- PCAP_TC_SHIFT
- PCAP_TS_PM_OPS
- PCAP_VC_MASK
- PCAP_VC_SHIFT
- PCARD_TO_DEV
- PCAT_APM_CONTROL_PORT
- PCAT_APM_STATUS_PORT
- PCA_BAD_QACCESS_PF
- PCA_BAD_QACCESS_VF
- PCA_CHIP_TYPE
- PCA_GPIO_MASK
- PCA_INT
- PCA_LATCH_INT
- PCA_MALICIOUS_REQ
- PCA_NO_FAULT
- PCA_PCAL
- PCA_POISONED_TLP
- PCA_TLP_ABORT
- PCA_TYPE_MASK
- PCA_UNMAPPED_ADDR
- PCAvDelayByIO
- PCB
- PCBPWR_GPIO_PIN
- PCBRR
- PCB_DATAFRAME_RETRANSMIT_MASK
- PCB_DATAFRAME_RETRANSMIT_NO
- PCB_DATAFRAME_RETRANSMIT_YES
- PCB_FRAME_CRC_INFO_MASK
- PCB_FRAME_CRC_INFO_NOTPRESENT
- PCB_FRAME_CRC_INFO_PRESENT
- PCB_SUPERVISOR_RETRANSMIT_MASK
- PCB_SUPERVISOR_RETRANSMIT_NO
- PCB_SUPERVISOR_RETRANSMIT_YES
- PCB_SYNC_ACK
- PCB_SYNC_MASK
- PCB_SYNC_NACK
- PCB_SYNC_NOINFO
- PCB_SYNC_WAIT
- PCB_TYPE_DATAFRAME
- PCB_TYPE_MASK
- PCB_TYPE_SUPERVISOR
- PCB_t
- PCC
- PCC0
- PCC0_ENABLE
- PCC0_PWR0
- PCC0_PWR1
- PCC0_PWR2
- PCC0_PWR3
- PCC0_RESET
- PCC1
- PCC1_ENABLE
- PCC1_PWR0
- PCC1_PWR1
- PCC1_PWR2
- PCC1_PWR3
- PCC1_RESET
- PCC2CHIP
- PCCARD_32
- PCCC_GENERATE_DB_INT
- PCCFG_LCPA
- PCCR
- PCCRXTO_MASK
- PCCRXTO_SHIFT
- PCCRX_MASK
- PCCRX_SHIFT
- PCCR_S0_FLT
- PCCR_S0_PSE
- PCCR_S0_PWAITEN
- PCCR_S0_RST
- PCCR_S1_FLT
- PCCR_S1_PSE
- PCCR_S1_PWAITEN
- PCCR_S1_RST
- PCCSCCMICR
- PCCSCCRICR
- PCCSCCTICR
- PCCS_CMD_COMPLETE
- PCCS_PLATFORM_NOTIFICATION
- PCCS_SCI_DOORBEL
- PCCTCMP1
- PCCTCNT1
- PCCTIC1
- PCCTIC1_INT_CLR
- PCCTIC1_INT_EN
- PCCTOVR1
- PCCTOVR1_COC_EN
- PCCTOVR1_OVR_CLR
- PCCTOVR1_TIC_EN
- PCCTPIACKR
- PCCTXQ0_EN
- PCCTXQ1_EN
- PCCTXQ2_EN
- PCCTXQ3_EN
- PCCTXQ4_EN
- PCCTXQ5_EN
- PCCTXQ6_EN
- PCCTXQ7_EN
- PCCTXTO_MASK
- PCCTXTO_SHIFT
- PCCTX_MASK
- PCCTX_QS_MASK
- PCCTX_SHIFT
- PCC_6_COF_OV_ERR
- PCC_6_LSO_OV_ERR
- PCC_7_COF_OV_ERR
- PCC_7_LSO_OV_ERR
- PCC_BVD1
- PCC_BVD1_MARK
- PCC_BVD2
- PCC_BVD2_MARK
- PCC_CAN_CLOCK
- PCC_CARD_ID
- PCC_CCR
- PCC_CCR_CLK_10
- PCC_CCR_CLK_16
- PCC_CCR_CLK_21
- PCC_CCR_CLK_8
- PCC_CCR_CLK_MASK
- PCC_CCR_INIT
- PCC_CCR_LED_CHAN
- PCC_CCR_LED_FAST_CHAN
- PCC_CCR_LED_MASK
- PCC_CCR_LED_MASK_CHAN
- PCC_CCR_LED_OFF_ALL
- PCC_CCR_LED_OFF_CHAN
- PCC_CCR_LED_ON_CHAN
- PCC_CCR_LED_SLOW_CHAN
- PCC_CCR_RST_ALL
- PCC_CCR_RST_CHAN
- PCC_CCR_RST_MASK
- PCC_CD1_MARK
- PCC_CD2_MARK
- PCC_CDR
- PCC_CHAN_MAX
- PCC_CHAN_OFF
- PCC_CHAN_SIZE
- PCC_CMD_COMPLETE_MASK
- PCC_CMD_GENERATE_DB_INT
- PCC_COMN_OFF
- PCC_COMN_SIZE
- PCC_CPR
- PCC_CSR
- PCC_CSR_SPI_BUSY
- PCC_DRV_MARK
- PCC_EEP_RDSR
- PCC_EEP_READ
- PCC_EEP_SR_WEN
- PCC_EEP_SR_WIP
- PCC_EEP_WRDI
- PCC_EEP_WREN
- PCC_EEP_WRITE
- PCC_ENABLE_FOUR
- PCC_ERROR_MASK
- PCC_FB_ECC_DB_ERR
- PCC_FB_ECC_ERR
- PCC_FB_ECC_SG_ERR
- PCC_FW_MAJOR
- PCC_FW_MINOR
- PCC_INTERVAL
- PCC_INTERVAL_US
- PCC_INTR_THRESHOLD
- PCC_INT_ENAB
- PCC_IRQ_ABORT
- PCC_IRQ_AC_FAIL
- PCC_IRQ_BERR
- PCC_IRQ_PRINTER
- PCC_IRQ_SOFTWARE1
- PCC_IRQ_SOFTWARE2
- PCC_IRQ_TIMER1
- PCC_IRQ_TIMER2
- PCC_ISR_MAX_LOOP
- PCC_LED
- PCC_LED_ALL
- PCC_LED_FAST
- PCC_LED_OFF
- PCC_LED_ON
- PCC_LED_SLOW
- PCC_LEVEL_ABORT
- PCC_LEVEL_ETH
- PCC_LEVEL_SCSI_DMA
- PCC_LEVEL_SCSI_PORT
- PCC_LEVEL_SERIAL
- PCC_LEVEL_TIMER1
- PCC_MANF_ID
- PCC_MASTER_SUBSPACE
- PCC_NAME
- PCC_NUM_RETRIES
- PCC_N_SERR
- PCC_OCR
- PCC_OFF
- PCC_OFF_CNT
- PCC_OFF_TO
- PCC_P1
- PCC_P1_CNT
- PCC_P1_TO
- PCC_P2
- PCC_P2_CNT
- PCC_P2_THRESHOLD
- PCC_P2_TO
- PCC_P3
- PCC_P3_CNT
- PCC_P3_THRESHOLD
- PCC_P3_TO
- PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK
- PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT
- PCC_RDY_MARK
- PCC_REG_MARK
- PCC_RESET_MARK
- PCC_SIGNATURE
- PCC_SIGNATURE_MASK
- PCC_SM_ERR_ALARM
- PCC_SPI_ADR
- PCC_SPI_DIR
- PCC_SPI_DOR
- PCC_SPI_IR
- PCC_SPI_MAX_BUSY_WAIT_MS
- PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK
- PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT
- PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK
- PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT
- PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK
- PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT
- PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK
- PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT
- PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK
- PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT
- PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK
- PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT
- PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK
- PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK
- PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK
- PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK
- PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK
- PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK
- PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK
- PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT
- PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK
- PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT
- PCC_STS_CMD_COMPLETE
- PCC_STS_ERR
- PCC_STS_PLAT_NOTIFY
- PCC_STS_SCI_DOORBELL
- PCC_THROTTLING_BIT
- PCC_THROTTLING_MASK
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1_MASK
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_1__SHIFT
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2_MASK
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_2__SHIFT
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3_MASK
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_3__SHIFT
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4_MASK
- PCC_THROT_DECR_FIRST_PATN_1_4__FIRST_PATTERN_4__SHIFT
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5_MASK
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_5__SHIFT
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6_MASK
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_6__SHIFT
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7_MASK
- PCC_THROT_DECR_FIRST_PATN_5_7__FIRST_PATTERN_7__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17_MASK
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_17__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18_MASK
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_18__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19_MASK
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_19__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20_MASK
- PCC_THROT_REINCR_FIRST_PATN_17_20__FIRST_PATTERN_20__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_1__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_2__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_3__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_4__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_5__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_6__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_7__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8_MASK
- PCC_THROT_REINCR_FIRST_PATN_1_8__FIRST_PATTERN_8__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_10__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_11__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_12__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_13__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_14__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_15__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_16__SHIFT
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9_MASK
- PCC_THROT_REINCR_FIRST_PATN_9_16__FIRST_PATTERN_9__SHIFT
- PCC_TIMER_CLOCK_FREQ
- PCC_TIMER_CLR_OVF
- PCC_TIMER_CYCLES
- PCC_TIMER_INT_CLR
- PCC_TIMER_PRELOAD
- PCC_TXB_ECC_DB_ERR
- PCC_TXB_ECC_SG_ERR
- PCC_TX_CNT
- PCC_TX_TO
- PCC_VERSION
- PCC_VS1
- PCC_VS1_MARK
- PCC_VS2
- PCC_VS2_MARK
- PCC_WRITE_MAX_LOOP
- PCC_WR_ERR_ALARM
- PCD
- PCDATA
- PCDATA_ADDR
- PCDIR
- PCDIR_ADDR
- PCDP_CONSOLE
- PCDP_CONSOLE_INPUT
- PCDP_CONSOLE_OUTPUT
- PCDP_CONSOLE_UART
- PCDP_CONSOLE_USB
- PCDP_CONSOLE_VGA
- PCDP_DEBUG
- PCDP_DEBUG_UART
- PCDP_IF_PCI
- PCDP_PCI_TRANS_IOPORT
- PCDP_PCI_TRANS_MMIO
- PCDP_PRIMARY_CONSOLE
- PCDP_UART
- PCDP_UART_ACTIVE_LOW
- PCDP_UART_EDGE_SENSITIVE
- PCDP_UART_IRQ
- PCDP_UART_PCI
- PCDP_UART_PRIMARY_CONSOLE
- PCDP_USB
- PCDP_VGA
- PCDR
- PCD_DELAY
- PCD_MAJOR
- PCD_NAME
- PCD_READY_TMO
- PCD_RESET_TMO
- PCD_RETRIES
- PCD_SPIN
- PCD_TMO
- PCD_UNITS
- PCD_VERSION
- PCE_GET
- PCE_STATUS_ACQUIRED
- PCE_STATUS_ENABLED
- PCE_STATUS_ERROR
- PCE_STATUS_NONE
- PCF2123_READ
- PCF2123_REG_ALRM_DM
- PCF2123_REG_ALRM_DW
- PCF2123_REG_ALRM_HR
- PCF2123_REG_ALRM_MN
- PCF2123_REG_CTDWN_TMR
- PCF2123_REG_CTRL1
- PCF2123_REG_CTRL2
- PCF2123_REG_DM
- PCF2123_REG_DW
- PCF2123_REG_HR
- PCF2123_REG_MN
- PCF2123_REG_MO
- PCF2123_REG_OFFSET
- PCF2123_REG_SC
- PCF2123_REG_TMR_CLKOUT
- PCF2123_REG_YR
- PCF2123_WRITE
- PCF2127_BIT_CTRL1_TSF1
- PCF2127_BIT_CTRL2_TSF2
- PCF2127_BIT_CTRL2_TSIE
- PCF2127_BIT_CTRL3_BF
- PCF2127_BIT_CTRL3_BIE
- PCF2127_BIT_CTRL3_BLF
- PCF2127_BIT_CTRL3_BLIE
- PCF2127_BIT_CTRL3_BTSE
- PCF2127_BIT_SC_OSF
- PCF2127_BIT_TS_CTRL_TSM
- PCF2127_BIT_TS_CTRL_TSOFF
- PCF2127_BIT_WD_CTL_CD0
- PCF2127_BIT_WD_CTL_CD1
- PCF2127_BIT_WD_CTL_TF0
- PCF2127_BIT_WD_CTL_TF1
- PCF2127_REG_CTRL1
- PCF2127_REG_CTRL2
- PCF2127_REG_CTRL3
- PCF2127_REG_DM
- PCF2127_REG_DW
- PCF2127_REG_HR
- PCF2127_REG_MN
- PCF2127_REG_MO
- PCF2127_REG_RAM_ADDR_MSB
- PCF2127_REG_RAM_RD_CMD
- PCF2127_REG_RAM_WRT_CMD
- PCF2127_REG_SC
- PCF2127_REG_TS_CTRL
- PCF2127_REG_TS_DM
- PCF2127_REG_TS_HR
- PCF2127_REG_TS_MN
- PCF2127_REG_TS_MO
- PCF2127_REG_TS_SC
- PCF2127_REG_TS_YR
- PCF2127_REG_WD_CTL
- PCF2127_REG_WD_VAL
- PCF2127_REG_YR
- PCF2127_WD_VAL_DEFAULT
- PCF2127_WD_VAL_MAX
- PCF2127_WD_VAL_MIN
- PCF2127_WD_VAL_STOP
- PCF50633_ADCC1_ADCMUX_MASK
- PCF50633_ADCC1_ADCSTART
- PCF50633_ADCC1_AVERAGE_16
- PCF50633_ADCC1_AVERAGE_4
- PCF50633_ADCC1_AVERAGE_8
- PCF50633_ADCC1_AVERAGE_MASK
- PCF50633_ADCC1_AVERAGE_NO
- PCF50633_ADCC1_MUX_ADCIN1
- PCF50633_ADCC1_MUX_ADCIN2_RES
- PCF50633_ADCC1_MUX_ADCIN2_SUBTR
- PCF50633_ADCC1_MUX_BATSNS_RES
- PCF50633_ADCC1_MUX_BATSNS_SUBTR
- PCF50633_ADCC1_MUX_BATTEMP
- PCF50633_ADCC1_RES_10BIT
- PCF50633_ADCC1_RES_8BIT
- PCF50633_ADCC2_RATIOSETTL_100US
- PCF50633_ADCC2_RATIO_ADCIN1
- PCF50633_ADCC2_RATIO_BATTEMP
- PCF50633_ADCC2_RATIO_BOTH
- PCF50633_ADCC2_RATIO_NONE
- PCF50633_ADCC3_ACCSW_EN
- PCF50633_ADCC3_NTCSW_EN
- PCF50633_ADCC3_RES_DIV_THREE
- PCF50633_ADCC3_RES_DIV_TWO
- PCF50633_ADCS3_ADCDAT1L_MASK
- PCF50633_ADCS3_ADCDAT2L_MASK
- PCF50633_ADCS3_ADCDAT2L_SHIFT
- PCF50633_ADCS3_ADCRDY
- PCF50633_ADCS3_REF_2V0
- PCF50633_ADCS3_REF_2V0_2
- PCF50633_ADCS3_REF_ACCSW
- PCF50633_ADCS3_REF_NTCSW
- PCF50633_ADCS3_REF_VISA
- PCF50633_ASCS3_REF_MASK
- PCF50633_GPIO1
- PCF50633_GPIO2
- PCF50633_GPIO3
- PCF50633_GPO
- PCF50633_GPOCFG_GPOSEL_0
- PCF50633_GPOCFG_GPOSEL_1
- PCF50633_GPOCFG_GPOSEL_ACTPH4
- PCF50633_GPOCFG_GPOSEL_ADAPUSB
- PCF50633_GPOCFG_GPOSEL_CLK32K
- PCF50633_GPOCFG_GPOSEL_INVERSE
- PCF50633_GPOCFG_GPOSEL_LED_NFET
- PCF50633_GPOCFG_GPOSEL_MASK
- PCF50633_GPOCFG_GPOSEL_SYSxOK
- PCF50633_GPOCFG_GPOSEL_USBxOK
- PCF50633_INT1_ADPINS
- PCF50633_INT1_ADPREM
- PCF50633_INT1_ALARM
- PCF50633_INT1_SECOND
- PCF50633_INT1_USBINS
- PCF50633_INT1_USBREM
- PCF50633_INT2_EXTON1F
- PCF50633_INT2_EXTON1R
- PCF50633_INT2_EXTON2F
- PCF50633_INT2_EXTON2R
- PCF50633_INT2_EXTON3F
- PCF50633_INT2_EXTON3R
- PCF50633_INT2_ONKEYF
- PCF50633_INT2_ONKEYR
- PCF50633_INT3_ADCRDY
- PCF50633_INT3_BATFULL
- PCF50633_INT3_CHGHALT
- PCF50633_INT3_ONKEY1S
- PCF50633_INT3_THLIMOFF
- PCF50633_INT3_THLIMON
- PCF50633_INT3_USBLIMOFF
- PCF50633_INT3_USBLIMON
- PCF50633_INT4_AUTOPWRFAIL
- PCF50633_INT4_DWN1PWRFAIL
- PCF50633_INT4_DWN2PWRFAIL
- PCF50633_INT4_HIGHTMP
- PCF50633_INT4_LEDOVP
- PCF50633_INT4_LEDPWRFAIL
- PCF50633_INT4_LOWBAT
- PCF50633_INT4_LOWSYS
- PCF50633_INT5_HCLDOOVL
- PCF50633_INT5_HCLDOPWRFAIL
- PCF50633_INT5_LDO1PWRFAIL
- PCF50633_INT5_LDO2PWRFAIL
- PCF50633_INT5_LDO3PWRFAIL
- PCF50633_INT5_LDO4PWRFAIL
- PCF50633_INT5_LDO5PWRFAIL
- PCF50633_INT5_LDO6PWRFAIL
- PCF50633_IRQ_ADCRDY
- PCF50633_IRQ_ADPINS
- PCF50633_IRQ_ADPREM
- PCF50633_IRQ_ALARM
- PCF50633_IRQ_AUTOPWRFAIL
- PCF50633_IRQ_BATFULL
- PCF50633_IRQ_CHGHALT
- PCF50633_IRQ_DWN1PWRFAIL
- PCF50633_IRQ_DWN2PWRFAIL
- PCF50633_IRQ_EXTON1F
- PCF50633_IRQ_EXTON1R
- PCF50633_IRQ_EXTON2F
- PCF50633_IRQ_EXTON2R
- PCF50633_IRQ_EXTON3F
- PCF50633_IRQ_EXTON3R
- PCF50633_IRQ_HCLDOOVL
- PCF50633_IRQ_HCLDOPWRFAIL
- PCF50633_IRQ_HIGHTMP
- PCF50633_IRQ_LDO1PWRFAIL
- PCF50633_IRQ_LDO2PWRFAIL
- PCF50633_IRQ_LDO3PWRFAIL
- PCF50633_IRQ_LDO4PWRFAIL
- PCF50633_IRQ_LDO5PWRFAIL
- PCF50633_IRQ_LDO6PWRFAIL
- PCF50633_IRQ_LEDOVP
- PCF50633_IRQ_LEDPWRFAIL
- PCF50633_IRQ_LOWBAT
- PCF50633_IRQ_LOWSYS
- PCF50633_IRQ_ONKEY1S
- PCF50633_IRQ_ONKEYF
- PCF50633_IRQ_ONKEYR
- PCF50633_IRQ_RESERVED1
- PCF50633_IRQ_RESERVED2
- PCF50633_IRQ_SECOND
- PCF50633_IRQ_THLIMOFF
- PCF50633_IRQ_THLIMON
- PCF50633_IRQ_USBINS
- PCF50633_IRQ_USBLIMOFF
- PCF50633_IRQ_USBLIMON
- PCF50633_IRQ_USBREM
- PCF50633_MAX_ADC_FIFO_DEPTH
- PCF50633_MBCC1_AUTORES
- PCF50633_MBCC1_AUTOSTOP
- PCF50633_MBCC1_CHGENA
- PCF50633_MBCC1_PREWDTIME_60M
- PCF50633_MBCC1_RESTART
- PCF50633_MBCC1_RESUME
- PCF50633_MBCC1_WDTIME_1H
- PCF50633_MBCC1_WDTIME_2H
- PCF50633_MBCC1_WDTIME_4H
- PCF50633_MBCC1_WDTIME_6H
- PCF50633_MBCC1_WDTIME_MASK
- PCF50633_MBCC2_VBATCOND_2V7
- PCF50633_MBCC2_VBATCOND_2V85
- PCF50633_MBCC2_VBATCOND_3V0
- PCF50633_MBCC2_VBATCOND_3V15
- PCF50633_MBCC2_VBATCOND_MASK
- PCF50633_MBCC2_VMAX_4V
- PCF50633_MBCC2_VMAX_4V20
- PCF50633_MBCC2_VMAX_MASK
- PCF50633_MBCC2_VRESDEBTIME_64S
- PCF50633_MBCC7_BATSYSIMAX_1A6
- PCF50633_MBCC7_BATSYSIMAX_1A8
- PCF50633_MBCC7_BATSYSIMAX_2A0
- PCF50633_MBCC7_BATSYSIMAX_2A2
- PCF50633_MBCC7_BATTEMP_EN
- PCF50633_MBCC7_USB_1000mA
- PCF50633_MBCC7_USB_100mA
- PCF50633_MBCC7_USB_500mA
- PCF50633_MBCC7_USB_MASK
- PCF50633_MBCC7_USB_SUSPEND
- PCF50633_MBCC8_USBENASUS
- PCF50633_MBCS1_ADAPTOK
- PCF50633_MBCS1_ADAPTPRES
- PCF50633_MBCS1_PREWDTEXP
- PCF50633_MBCS1_TBAT_ABOVE
- PCF50633_MBCS1_TBAT_BELOW
- PCF50633_MBCS1_TBAT_OK
- PCF50633_MBCS1_TBAT_UNDEF
- PCF50633_MBCS1_USBOK
- PCF50633_MBCS1_USBPRES
- PCF50633_MBCS1_WDTEXP
- PCF50633_MBCS2_CHGS_ADAPTER
- PCF50633_MBCS2_CHGS_BOTH
- PCF50633_MBCS2_CHGS_NONE
- PCF50633_MBCS2_CHGS_USB
- PCF50633_MBCS2_MBC_ADP_FAST
- PCF50633_MBCS2_MBC_ADP_FAST_WAIT
- PCF50633_MBCS2_MBC_ADP_PRE
- PCF50633_MBCS2_MBC_ADP_PRE_WAIT
- PCF50633_MBCS2_MBC_BAT_FULL
- PCF50633_MBCS2_MBC_HALT
- PCF50633_MBCS2_MBC_MASK
- PCF50633_MBCS2_MBC_PLAY
- PCF50633_MBCS2_MBC_USB_FAST
- PCF50633_MBCS2_MBC_USB_FAST_WAIT
- PCF50633_MBCS2_MBC_USB_PRE
- PCF50633_MBCS2_MBC_USB_PRE_WAIT
- PCF50633_MBCS2_MBC_USB_SUSPEND
- PCF50633_MBCS2_RESSTAT_AUTO
- PCF50633_MBCS3_ILIM
- PCF50633_MBCS3_TLIM_CHG
- PCF50633_MBCS3_TLIM_PLAY
- PCF50633_MBCS3_USBLIM_CGH
- PCF50633_MBCS3_USBLIM_PLAY
- PCF50633_MBCS3_VBATSTAT
- PCF50633_MBCS3_VLIM
- PCF50633_MBCS3_VRES
- PCF50633_MBC_ADAPTER_ACTIVE
- PCF50633_MBC_ADAPTER_ONLINE
- PCF50633_MBC_USB_ACTIVE
- PCF50633_MBC_USB_ONLINE
- PCF50633_NUM_IRQ
- PCF50633_NUM_REGULATORS
- PCF50633_ONKEY1S_TIMEOUT
- PCF50633_OOCSTAT_ONKEY
- PCF50633_REGULATOR
- PCF50633_REGULATOR_ACTPH1
- PCF50633_REGULATOR_ACTPH2
- PCF50633_REGULATOR_ACTPH3
- PCF50633_REGULATOR_ACTPH4
- PCF50633_REGULATOR_ACTPH_MASK
- PCF50633_REGULATOR_AUTO
- PCF50633_REGULATOR_DOWN1
- PCF50633_REGULATOR_DOWN2
- PCF50633_REGULATOR_HCLDO
- PCF50633_REGULATOR_LDO1
- PCF50633_REGULATOR_LDO2
- PCF50633_REGULATOR_LDO3
- PCF50633_REGULATOR_LDO4
- PCF50633_REGULATOR_LDO5
- PCF50633_REGULATOR_LDO6
- PCF50633_REGULATOR_MEMLDO
- PCF50633_REGULATOR_ON
- PCF50633_REGULATOR_ON_GPIO1
- PCF50633_REGULATOR_ON_GPIO2
- PCF50633_REGULATOR_ON_GPIO3
- PCF50633_REGULATOR_ON_MASK
- PCF50633_REG_ADCC1
- PCF50633_REG_ADCC2
- PCF50633_REG_ADCC3
- PCF50633_REG_ADCS1
- PCF50633_REG_ADCS2
- PCF50633_REG_ADCS3
- PCF50633_REG_AUTOCTL
- PCF50633_REG_AUTOENA
- PCF50633_REG_AUTOMXC
- PCF50633_REG_AUTOOUT
- PCF50633_REG_DOWN1CTL
- PCF50633_REG_DOWN1ENA
- PCF50633_REG_DOWN1MXC
- PCF50633_REG_DOWN1OUT
- PCF50633_REG_DOWN2CTL
- PCF50633_REG_DOWN2ENA
- PCF50633_REG_DOWN2MXC
- PCF50633_REG_DOWN2OUT
- PCF50633_REG_GPIO1CFG
- PCF50633_REG_GPIO2CFG
- PCF50633_REG_GPIO3CFG
- PCF50633_REG_GPOCFG
- PCF50633_REG_HCLDOENA
- PCF50633_REG_HCLDOOUT
- PCF50633_REG_HCLDOOVL
- PCF50633_REG_INT1
- PCF50633_REG_INT1M
- PCF50633_REG_INT2
- PCF50633_REG_INT2M
- PCF50633_REG_INT3
- PCF50633_REG_INT3M
- PCF50633_REG_INT4
- PCF50633_REG_INT4M
- PCF50633_REG_INT5
- PCF50633_REG_INT5M
- PCF50633_REG_LDO1ENA
- PCF50633_REG_LDO1OUT
- PCF50633_REG_LDO2ENA
- PCF50633_REG_LDO2OUT
- PCF50633_REG_LDO3ENA
- PCF50633_REG_LDO3OUT
- PCF50633_REG_LDO4ENA
- PCF50633_REG_LDO4OUT
- PCF50633_REG_LDO5ENA
- PCF50633_REG_LDO5OUT
- PCF50633_REG_LDO6ENA
- PCF50633_REG_LDO6OUT
- PCF50633_REG_LEDCTL
- PCF50633_REG_LEDDIM
- PCF50633_REG_LEDENA
- PCF50633_REG_LEDOUT
- PCF50633_REG_MBCC1
- PCF50633_REG_MBCC2
- PCF50633_REG_MBCC3
- PCF50633_REG_MBCC4
- PCF50633_REG_MBCC5
- PCF50633_REG_MBCC6
- PCF50633_REG_MBCC7
- PCF50633_REG_MBCC8
- PCF50633_REG_MBCS1
- PCF50633_REG_MBCS2
- PCF50633_REG_MBCS3
- PCF50633_REG_MEMLDOENA
- PCF50633_REG_MEMLDOOUT
- PCF50633_REG_OOCMODE
- PCF50633_REG_OOCSHDWN
- PCF50633_REG_OOCSTAT
- PCF50633_REG_RTCDT
- PCF50633_REG_RTCDTA
- PCF50633_REG_RTCHR
- PCF50633_REG_RTCHRA
- PCF50633_REG_RTCMN
- PCF50633_REG_RTCMNA
- PCF50633_REG_RTCMT
- PCF50633_REG_RTCMTA
- PCF50633_REG_RTCSC
- PCF50633_REG_RTCSCA
- PCF50633_REG_RTCWD
- PCF50633_REG_RTCWDA
- PCF50633_REG_RTCYR
- PCF50633_REG_RTCYRA
- PCF50633_TI_DAY
- PCF50633_TI_EXTENT
- PCF50633_TI_HOUR
- PCF50633_TI_MIN
- PCF50633_TI_MONTH
- PCF50633_TI_SEC
- PCF50633_TI_WKDAY
- PCF50633_TI_YEAR
- PCF85063_AEN
- PCF85063_CTRL2_AF
- PCF85063_CTRL2_AIE
- PCF85063_OFFSET_MODE
- PCF85063_OFFSET_SIGN_BIT
- PCF85063_OFFSET_STEP0
- PCF85063_OFFSET_STEP1
- PCF85063_REG_ALM_S
- PCF85063_REG_CTRL1
- PCF85063_REG_CTRL1_CAP_SEL
- PCF85063_REG_CTRL1_STOP
- PCF85063_REG_CTRL2
- PCF85063_REG_OFFSET
- PCF85063_REG_RAM
- PCF85063_REG_SC
- PCF85063_REG_SC_OS
- PCF8563_BITS_ST2_N
- PCF8563_BIT_AF
- PCF8563_BIT_AIE
- PCF8563_MO_C
- PCF8563_REG_AMN
- PCF8563_REG_CLKO
- PCF8563_REG_CLKO_FE
- PCF8563_REG_CLKO_F_1024HZ
- PCF8563_REG_CLKO_F_1HZ
- PCF8563_REG_CLKO_F_32768HZ
- PCF8563_REG_CLKO_F_32HZ
- PCF8563_REG_CLKO_F_MASK
- PCF8563_REG_DM
- PCF8563_REG_DW
- PCF8563_REG_HR
- PCF8563_REG_MN
- PCF8563_REG_MO
- PCF8563_REG_SC
- PCF8563_REG_ST1
- PCF8563_REG_ST2
- PCF8563_REG_TMR
- PCF8563_REG_TMRC
- PCF8563_REG_YR
- PCF8563_SC_LV
- PCF8563_TMRC_1
- PCF8563_TMRC_1_60
- PCF8563_TMRC_4096
- PCF8563_TMRC_64
- PCF8563_TMRC_ENABLE
- PCF8563_TMRC_MASK
- PCF8584_ADDRESS
- PCF8584_CSR
- PCF8584_DATA
- PCF8584_FANSTAT_TYPE
- PCF8584_GLOBALADDR_TYPE
- PCF8584_MAX_CHANNELS
- PCF8584_TEMP_TYPE
- PCF8584_VOLTAGE_TYPE
- PCF8591_CONTROL_AICH_MASK
- PCF8591_CONTROL_AINC
- PCF8591_CONTROL_AIP_MASK
- PCF8591_CONTROL_AOEF
- PCF8591_INIT_AOUT
- PCF8591_INIT_CONTROL
- PCF9554_REG_CONFIG
- PCF9554_REG_INPUT
- PCF9554_REG_OUTPUT
- PCF9554_REG_POLARITY
- PCFG_PAD_VAL
- PCFG_PORT_BITWIDTH
- PCFG_PORT_MASK
- PCFG_TPRS_VAL
- PCFG_TPSS_VAL
- PCFO_TRACKING
- PCFR
- PCFR_ClkRun
- PCFR_ClkStp
- PCFR_DC_EN
- PCFR_DS
- PCFR_FO
- PCFR_FP
- PCFR_FS
- PCFR_FVC
- PCFR_GPROD
- PCFR_GPR_EN
- PCFR_L1_EN
- PCFR_OPDE
- PCFR_PCMCIAFlt
- PCFR_PCMCIANeg
- PCFR_PI2CEN
- PCFR_PI2C_EN
- PCFR_PO
- PCFR_RO
- PCFR_StMemFlt
- PCFR_StMemNeg
- PCFULIE
- PCFULIF
- PCF_Uxx_BASE
- PCGCCTL1
- PCGCCTL1_GATEEN
- PCGCCTL1_TIMER
- PCGCTL
- PCGCTL_DEEP_SLEEP
- PCGCTL_ENBL_EXTND_HIBER
- PCGCTL_ENBL_SLEEP_GATING
- PCGCTL_ESS_REG_RESTORED
- PCGCTL_EXTND_HIBER_PWRCLMP
- PCGCTL_EXTND_HIBER_SWITCH
- PCGCTL_GATEHCLK
- PCGCTL_IF_DEV_MODE
- PCGCTL_MAC_DEV_ADDR_MASK
- PCGCTL_MAC_DEV_ADDR_SHIFT
- PCGCTL_MAX_TERMSEL
- PCGCTL_MAX_XCVRSELECT_MASK
- PCGCTL_MAX_XCVRSELECT_SHIFT
- PCGCTL_P2HD_DEV_ENUM_SPD_MASK
- PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT
- PCGCTL_P2HD_PRT_SPD_MASK
- PCGCTL_P2HD_PRT_SPD_SHIFT
- PCGCTL_PHY_IN_SLEEP
- PCGCTL_PORT_POWER
- PCGCTL_PRT_CLK_SEL_MASK
- PCGCTL_PRT_CLK_SEL_SHIFT
- PCGCTL_PWRCLMP
- PCGCTL_RESETAFTSUSP
- PCGCTL_RESTOREMODE
- PCGCTL_RSTPDWNMODULE
- PCGCTL_STOPPCLK
- PCG_CGC_SHIFT
- PCG_DIV_MAX
- PCG_DIV_SHIFT
- PCG_DIV_WIDTH
- PCG_FRAC_MASK
- PCG_FRAC_SHIFT
- PCG_FRAC_WIDTH
- PCG_PCD_MASK
- PCG_PCD_SHIFT
- PCG_PCD_WIDTH
- PCG_PCS_MASK
- PCG_PCS_SHIFT
- PCG_PREDIV_MAX
- PCG_PREDIV_SHIFT
- PCG_PREDIV_WIDTH
- PCH0_ID
- PCH0_SR
- PCH1_ID
- PCH1_SR
- PCH2_ID
- PCH2_SR
- PCHALLENGE_MESSAGE
- PCHANNEL_ACCESS_SETTING
- PCHAR
- PCHD_ID
- PCHD_SR
- PCHG_ID
- PCH_3DCGDIS0
- PCH_3DCGDIS1
- PCH_ACK
- PCH_ACK_ERR
- PCH_ADDRESS_SIZE
- PCH_ADPA
- PCH_ALL
- PCH_AUTONEG_ADVERTISE_DEFAULT
- PCH_BIT0_ERR
- PCH_BIT1_ERR
- PCH_BIT_BRPE_BRPE_SHIFT
- PCH_BIT_BRP_SHIFT
- PCH_BIT_SJW_SHIFT
- PCH_BIT_TSEG1_SHIFT
- PCH_BIT_TSEG2_SHIFT
- PCH_BUFFER_MODE
- PCH_BUFFER_MODE_ENABLE
- PCH_BUFF_START
- PCH_BUF_RD
- PCH_BUF_SIZE
- PCH_BUF_TX
- PCH_BUS_OFF
- PCH_CAN_ALL
- PCH_CAN_CLK
- PCH_CAN_DISABLE
- PCH_CAN_ENABLE
- PCH_CAN_NONE
- PCH_CAN_RUN
- PCH_CAN_STOP
- PCH_CC_MM
- PCH_CC_MODE_MASK
- PCH_CC_MODE_SHIFT
- PCH_CC_TA
- PCH_CC_VERSION
- PCH_CE_OVR
- PCH_CE_RXS
- PCH_CE_TXS
- PCH_CE_VAL
- PCH_CLOCK_HZ
- PCH_CMASK_ALL
- PCH_CMASK_ARB
- PCH_CMASK_CLRINTPND
- PCH_CMASK_CTRL
- PCH_CMASK_MASK
- PCH_CMASK_NEWDAT
- PCH_CMASK_RDWR
- PCH_CMASK_RX_TX_GET
- PCH_CMASK_RX_TX_SET
- PCH_CNP
- PCH_CONSOLE
- PCH_COUNTER_LIMIT
- PCH_CPT
- PCH_CPUNIT_CLOCK_GATE_DISABLE
- PCH_CRC_ERR
- PCH_CTRL_CCE
- PCH_CTRL_IE
- PCH_CTRL_IE_SIE_EIE
- PCH_CTRL_INIT
- PCH_CTRL_OPT
- PCH_DISPLAY_BASE
- PCH_DMA_CTL0
- PCH_DMA_CTL1
- PCH_DMA_CTL2
- PCH_DMA_CTL3
- PCH_DMA_H
- PCH_DMA_STS0
- PCH_DMA_STS1
- PCH_DMA_STS2
- PCH_DMA_TRANS_SIZE
- PCH_DMA_WIDTH_1_BYTE
- PCH_DMA_WIDTH_2_BYTES
- PCH_DMA_WIDTH_4_BYTES
- PCH_DPLL
- PCH_DPLL_SEL
- PCH_DPLL_TEST
- PCH_DPLL_TMR_CFG
- PCH_DPLSUNIT_CLOCK_GATE_DISABLE
- PCH_DPLUNIT_CLOCK_GATE_DISABLE
- PCH_DP_AUX_CH_CTL
- PCH_DP_AUX_CH_DATA
- PCH_DP_B
- PCH_DP_C
- PCH_DP_D
- PCH_DREF_CONTROL
- PCH_ECS_CAN
- PCH_ECS_ETH
- PCH_EDGE_BOTH
- PCH_EDGE_FALLING
- PCH_EDGE_RISING
- PCH_EEPROM_SW_RST_MODE_ENABLE
- PCH_EPASSIV
- PCH_ESR_START
- PCH_EVENT_NONE
- PCH_EVENT_SET
- PCH_EWARN
- PCH_FAILED
- PCH_FIFO_THRESH
- PCH_FORM_ERR
- PCH_FP0
- PCH_FP1
- PCH_GBE_ADD_FIL_EN
- PCH_GBE_ALL_RST
- PCH_GBE_BUSY
- PCH_GBE_CHIP_TYPE_EXTERNAL
- PCH_GBE_CHIP_TYPE_INTERNAL
- PCH_GBE_CRS_SEL
- PCH_GBE_DEFAULT_RXD
- PCH_GBE_DEFAULT_RX_CSUM
- PCH_GBE_DEFAULT_TXD
- PCH_GBE_DEFAULT_TX_CSUM
- PCH_GBE_DESC_UNUSED
- PCH_GBE_DMA_ALIGN
- PCH_GBE_DMA_PADDING
- PCH_GBE_DUPLEX_FULL
- PCH_GBE_EX_LIST_EN
- PCH_GBE_FC_DEFAULT
- PCH_GBE_FC_FULL
- PCH_GBE_FC_NONE
- PCH_GBE_FC_RX_PAUSE
- PCH_GBE_FC_TX_PAUSE
- PCH_GBE_FL_CTRL_EN
- PCH_GBE_FRAME_SIZE_2048
- PCH_GBE_FRAME_SIZE_4096
- PCH_GBE_FRAME_SIZE_8192
- PCH_GBE_GET_DESC
- PCH_GBE_GLOBAL_STATS_LEN
- PCH_GBE_HAL_MIIM_READ
- PCH_GBE_HAL_MIIM_WRITE
- PCH_GBE_IDLE_CHECK
- PCH_GBE_INT_DISABLE_ALL
- PCH_GBE_INT_ENABLE_MASK
- PCH_GBE_INT_MIIM_CMPLT
- PCH_GBE_INT_PAUSE_CMPLT
- PCH_GBE_INT_PHY_INT
- PCH_GBE_INT_RX_DMA_CMPLT
- PCH_GBE_INT_RX_DMA_ERR
- PCH_GBE_INT_RX_DSC_EMP
- PCH_GBE_INT_RX_FIFO_ERR
- PCH_GBE_INT_RX_FRAME_ERR
- PCH_GBE_INT_RX_VALID
- PCH_GBE_INT_TCPIP_ERR
- PCH_GBE_INT_TX_CMPLT
- PCH_GBE_INT_TX_DMA_CMPLT
- PCH_GBE_INT_TX_DMA_ERR
- PCH_GBE_INT_TX_FIFO_ERR
- PCH_GBE_INT_WOL_DET
- PCH_GBE_LINK_UP
- PCH_GBE_MAC_REGS_LEN
- PCH_GBE_MAC_RGMII_CTRL_SETTING
- PCH_GBE_MAR_ENTRIES
- PCH_GBE_MAX_JUMBO_FRAME_SIZE
- PCH_GBE_MAX_RXD
- PCH_GBE_MAX_RX_BUFFER_SIZE
- PCH_GBE_MAX_TXD
- PCH_GBE_MIIM_OPER_READ
- PCH_GBE_MIIM_OPER_READY
- PCH_GBE_MIIM_OPER_WRITE
- PCH_GBE_MIIM_PHY_ADDR_SHIFT
- PCH_GBE_MIIM_REG_ADDR_SHIFT
- PCH_GBE_MIN_RXD
- PCH_GBE_MIN_TXD
- PCH_GBE_MLT_FIL_EN
- PCH_GBE_MODE_FR_BST
- PCH_GBE_MODE_FULL_DUPLEX
- PCH_GBE_MODE_GMII_ETHER
- PCH_GBE_MODE_HALF_DUPLEX
- PCH_GBE_MODE_MII_ETHER
- PCH_GBE_MRE_MAC_RX_EN
- PCH_GBE_PAUSE_PKT1_VALUE
- PCH_GBE_PAUSE_PKT2_VALUE
- PCH_GBE_PAUSE_PKT4_VALUE
- PCH_GBE_PAUSE_PKT5_VALUE
- PCH_GBE_PCI_BAR
- PCH_GBE_PHY_REGS_LEN
- PCH_GBE_PHY_RESET_DELAY_US
- PCH_GBE_PS_PKT_RQ
- PCH_GBE_QUEUE_STATS_LEN
- PCH_GBE_REGS_LEN
- PCH_GBE_RESERVE_MEMORY
- PCH_GBE_RF_ALM_EMP
- PCH_GBE_RF_ALM_FULL
- PCH_GBE_RF_RCVING
- PCH_GBE_RF_RD_TRG
- PCH_GBE_RF_STRWD
- PCH_GBE_RGMII_MODE_GMII
- PCH_GBE_RGMII_MODE_RGMII
- PCH_GBE_RGMII_RATE_125M
- PCH_GBE_RGMII_RATE_25M
- PCH_GBE_RGMII_RATE_2_5M
- PCH_GBE_RH_ALM_EMP_16
- PCH_GBE_RH_ALM_EMP_32
- PCH_GBE_RH_ALM_EMP_4
- PCH_GBE_RH_ALM_EMP_8
- PCH_GBE_RH_ALM_FULL_16
- PCH_GBE_RH_ALM_FULL_32
- PCH_GBE_RH_ALM_FULL_4
- PCH_GBE_RH_ALM_FULL_8
- PCH_GBE_RH_RD_TRG_128
- PCH_GBE_RH_RD_TRG_16
- PCH_GBE_RH_RD_TRG_256
- PCH_GBE_RH_RD_TRG_32
- PCH_GBE_RH_RD_TRG_4
- PCH_GBE_RH_RD_TRG_512
- PCH_GBE_RH_RD_TRG_64
- PCH_GBE_RH_RD_TRG_8
- PCH_GBE_RXC_SPEED_125M
- PCH_GBE_RXC_SPEED_25M
- PCH_GBE_RXC_SPEED_2_5M
- PCH_GBE_RXC_SPEED_MSK
- PCH_GBE_RXD_ACC_STAT_BCAST
- PCH_GBE_RXD_ACC_STAT_IP6ERR
- PCH_GBE_RXD_ACC_STAT_IPOK
- PCH_GBE_RXD_ACC_STAT_MACL
- PCH_GBE_RXD_ACC_STAT_MCAST
- PCH_GBE_RXD_ACC_STAT_OFLIST
- PCH_GBE_RXD_ACC_STAT_PPPOE
- PCH_GBE_RXD_ACC_STAT_TCPIPOK
- PCH_GBE_RXD_ACC_STAT_TCPOK
- PCH_GBE_RXD_ACC_STAT_TYPEIP
- PCH_GBE_RXD_ACC_STAT_UCAST
- PCH_GBE_RXD_ACC_STAT_VTAGT
- PCH_GBE_RXD_GMAC_STAT_CRCERR
- PCH_GBE_RXD_GMAC_STAT_MARBR
- PCH_GBE_RXD_GMAC_STAT_MARIND
- PCH_GBE_RXD_GMAC_STAT_MARMLT
- PCH_GBE_RXD_GMAC_STAT_MARNOTMT
- PCH_GBE_RXD_GMAC_STAT_NBLERR
- PCH_GBE_RXD_GMAC_STAT_NOTOCTAL
- PCH_GBE_RXD_GMAC_STAT_PAUSE
- PCH_GBE_RXD_GMAC_STAT_TLONG
- PCH_GBE_RXD_GMAC_STAT_TSHRT
- PCH_GBE_RX_BUFFER_WRITE
- PCH_GBE_RX_DESC
- PCH_GBE_RX_DESC_MULTIPLE
- PCH_GBE_RX_DMA_EN
- PCH_GBE_RX_RST
- PCH_GBE_RX_TCPIPACC_EN
- PCH_GBE_RX_TCPIPACC_OFF
- PCH_GBE_RX_WEIGHT
- PCH_GBE_SHORT_PKT
- PCH_GBE_STAT
- PCH_GBE_STATS_LEN
- PCH_GBE_TM_LONG_PKT
- PCH_GBE_TM_LTCOL_RETX
- PCH_GBE_TM_NO_RTRY
- PCH_GBE_TM_SHORT_PKT
- PCH_GBE_TM_ST_AND_FD
- PCH_GBE_TM_TH_ALM_EMP_128
- PCH_GBE_TM_TH_ALM_EMP_16
- PCH_GBE_TM_TH_ALM_EMP_256
- PCH_GBE_TM_TH_ALM_EMP_32
- PCH_GBE_TM_TH_ALM_EMP_4
- PCH_GBE_TM_TH_ALM_EMP_512
- PCH_GBE_TM_TH_ALM_EMP_64
- PCH_GBE_TM_TH_ALM_EMP_8
- PCH_GBE_TM_TH_ALM_FULL_16
- PCH_GBE_TM_TH_ALM_FULL_32
- PCH_GBE_TM_TH_ALM_FULL_4
- PCH_GBE_TM_TH_ALM_FULL_8
- PCH_GBE_TM_TH_TX_STRT_16
- PCH_GBE_TM_TH_TX_STRT_32
- PCH_GBE_TM_TH_TX_STRT_4
- PCH_GBE_TM_TH_TX_STRT_8
- PCH_GBE_TXD_CTRL_APAD
- PCH_GBE_TXD_CTRL_ICRC
- PCH_GBE_TXD_CTRL_ITAG
- PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF
- PCH_GBE_TXD_GMAC_STAT_ABT
- PCH_GBE_TXD_GMAC_STAT_CMPLT
- PCH_GBE_TXD_GMAC_STAT_CRSER
- PCH_GBE_TXD_GMAC_STAT_EXCOL
- PCH_GBE_TXD_GMAC_STAT_LTCOL
- PCH_GBE_TXD_GMAC_STAT_MLTCOL
- PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK
- PCH_GBE_TXD_GMAC_STAT_SNGCOL
- PCH_GBE_TXD_GMAC_STAT_TFUNDFLW
- PCH_GBE_TXD_GMAC_STAT_TLNG
- PCH_GBE_TXD_GMAC_STAT_TSHRT
- PCH_GBE_TXD_WORDS_SHIFT
- PCH_GBE_TX_DESC
- PCH_GBE_TX_DESC_MULTIPLE
- PCH_GBE_TX_DMA_EN
- PCH_GBE_TX_RST
- PCH_GBE_TX_TCPIPACC_EN
- PCH_GBE_TX_WEIGHT
- PCH_GBE_WATCHDOG_PERIOD
- PCH_GBE_WLA_BUSY
- PCH_GBE_WLC_BR
- PCH_GBE_WLC_IGN_CRCER
- PCH_GBE_WLC_IGN_NBLER
- PCH_GBE_WLC_IGN_OCTER
- PCH_GBE_WLC_IGN_TLONG
- PCH_GBE_WLC_IGN_TSHRT
- PCH_GBE_WLC_IND
- PCH_GBE_WLC_MLT
- PCH_GBE_WLC_MP
- PCH_GBE_WLC_WOL_MODE
- PCH_GBE_WLS_BR
- PCH_GBE_WLS_IND
- PCH_GBE_WLS_MLT
- PCH_GBE_WLS_MP
- PCH_GBE_WL_INIT_SETTING
- PCH_GETACK
- PCH_GMBUS0
- PCH_GMBUS1
- PCH_GMBUS2
- PCH_GMBUS3
- PCH_GMBUS4
- PCH_GMBUS5
- PCH_GMBUSUNIT_CLOCK_GATE_DISABLE
- PCH_GPIO_BASE
- PCH_GTC_CTL
- PCH_GTC_ENABLE
- PCH_HBLANK_B
- PCH_HDMIB
- PCH_HDMIC
- PCH_HDMID
- PCH_HSYNC_B
- PCH_HTOTAL_B
- PCH_I2CBC
- PCH_I2CBUFCTL
- PCH_I2CBUFFOR
- PCH_I2CBUFLEV
- PCH_I2CBUFMSK
- PCH_I2CBUFSLV
- PCH_I2CBUFSTA
- PCH_I2CBUFSUB
- PCH_I2CCTL
- PCH_I2CCTL_I2CMEN
- PCH_I2CDR
- PCH_I2CESRCTL
- PCH_I2CESRFOR
- PCH_I2CESRMSK
- PCH_I2CESRSTA
- PCH_I2CMOD
- PCH_I2CMON
- PCH_I2CNF
- PCH_I2CSADR
- PCH_I2CSR
- PCH_I2CSRST
- PCH_I2CTMR
- PCH_I2C_MAX_DEV
- PCH_IBX
- PCH_ICP
- PCH_ID2_DIR
- PCH_ID2_XTD
- PCH_ID_MSGVAL
- PCH_IEEE1588_CAN
- PCH_IEEE1588_ETH
- PCH_IF_CREQ_BUSY
- PCH_IF_MCONT_DLC
- PCH_IF_MCONT_EOB
- PCH_IF_MCONT_INTPND
- PCH_IF_MCONT_MSGLOST
- PCH_IF_MCONT_NEWDAT
- PCH_IF_MCONT_RMTEN
- PCH_IF_MCONT_RXIE
- PCH_IF_MCONT_TXIE
- PCH_IF_MCONT_TXRQXT
- PCH_IF_MCONT_UMASK
- PCH_IM_MASK
- PCH_INTERRUPTMODEINUSE
- PCH_INVALIDPARAM
- PCH_IRQ_BASE
- PCH_LEC_ALL
- PCH_LEVEL_H
- PCH_LEVEL_L
- PCH_LPT
- PCH_LP_PARTITION_LEVEL_DISABLE
- PCH_LVDS
- PCH_MASK2_MDIR_MXTD
- PCH_MAX_BAUDRATE
- PCH_MAX_CLK
- PCH_MAX_CS
- PCH_MAX_FIFO_DEPTH
- PCH_MAX_SPBR
- PCH_MCC
- PCH_MINOR_NOS
- PCH_MSK_BITT_BRP
- PCH_MSK_BRPE_BRPE
- PCH_MSK_CTRL_IE_SIE_EIE
- PCH_NONE
- PCH_NOP
- PCH_NOTIMESTAMP
- PCH_OPT_LBACK
- PCH_OPT_SILENT
- PCH_PCI_SOFT_RESET
- PCH_PCR_GPIO_1_BASE
- PCH_PCR_GPIO_ADDRESS
- PCH_PHUB_BRI_QUEUE_MAXSIZE_REG
- PCH_PHUB_BUS_SLAVE_CONTROL_REG
- PCH_PHUB_COMP_RESP_TIMEOUT_REG
- PCH_PHUB_DEADLOCK_AVOID_TYPE_REG
- PCH_PHUB_ID_REG
- PCH_PHUB_INTPIN_REG_WPERMIT_REG0
- PCH_PHUB_INTPIN_REG_WPERMIT_REG1
- PCH_PHUB_INTPIN_REG_WPERMIT_REG2
- PCH_PHUB_INTPIN_REG_WPERMIT_REG3
- PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE
- PCH_PHUB_MAC_START_ADDR_EG20T
- PCH_PHUB_MAC_START_ADDR_ML7223
- PCH_PHUB_OROM_SIZE
- PCH_PHUB_QUEUE_PRI_VAL_REG
- PCH_PHUB_RC_QUEUE_MAXSIZE_REG
- PCH_PHUB_ROM_START_ADDR_EG20T
- PCH_PHUB_ROM_START_ADDR_ML7213
- PCH_PHUB_ROM_START_ADDR_ML7223
- PCH_PHUB_ROM_WRITE_DISABLE
- PCH_PHUB_ROM_WRITE_ENABLE
- PCH_PIPEBCONF
- PCH_PIPEBSRC
- PCH_PIPEBSTAT
- PCH_PIPEB_DSL
- PCH_PIPEB_SLC
- PCH_PORT_HOTPLUG
- PCH_PORT_HOTPLUG2
- PCH_PPS_BASE
- PCH_PP_CONTROL
- PCH_PP_DIVISOR
- PCH_PP_OFF_DELAYS
- PCH_PP_ON_DELAYS
- PCH_PP_STATUS
- PCH_RAWCLK_FREQ
- PCH_READABLE
- PCH_REC
- PCH_REGS_BUFSIZE
- PCH_REPSTART
- PCH_RESTART
- PCH_RP
- PCH_RX_IFREG
- PCH_RX_OBJ_END
- PCH_RX_OBJ_NUM
- PCH_RX_OBJ_START
- PCH_RX_OK
- PCH_RX_THOLD
- PCH_RX_THOLD_MAX
- PCH_SDVOB
- PCH_SLEEP_TIME
- PCH_SPBRR
- PCH_SPCR
- PCH_SPDRR
- PCH_SPDWR
- PCH_SPI_MAX_DEV
- PCH_SPSR
- PCH_SPSR_RFD
- PCH_SPSR_TFD
- PCH_SPT
- PCH_SRST
- PCH_SSC4_AUX_PARMS
- PCH_SSC4_PARMS
- PCH_SSNXCR
- PCH_START
- PCH_STATION_BYTES
- PCH_STATUS_INT
- PCH_STUF_ERR
- PCH_SUCCESS
- PCH_TEC
- PCH_TGP
- PCH_THERMAL_DID_CNL
- PCH_THERMAL_DID_CNL_H
- PCH_THERMAL_DID_HSW_1
- PCH_THERMAL_DID_HSW_2
- PCH_THERMAL_DID_SKL
- PCH_THERMAL_DID_SKL_H
- PCH_THERMAL_DID_WPT
- PCH_TRANSCONF
- PCH_TRANS_DATA_M1
- PCH_TRANS_DATA_M2
- PCH_TRANS_DATA_N1
- PCH_TRANS_DATA_N2
- PCH_TRANS_HBLANK
- PCH_TRANS_HSYNC
- PCH_TRANS_HTOTAL
- PCH_TRANS_LINK_M1
- PCH_TRANS_LINK_M2
- PCH_TRANS_LINK_N1
- PCH_TRANS_LINK_N2
- PCH_TRANS_VBLANK
- PCH_TRANS_VSYNC
- PCH_TRANS_VSYNCSHIFT
- PCH_TRANS_VTOTAL
- PCH_TREQ2_TX_MASK
- PCH_TSC_AMMS_MASK
- PCH_TSC_ASMS_MASK
- PCH_TSC_PPSM_MASK
- PCH_TSC_RESET
- PCH_TSC_TTM_MASK
- PCH_TSE_PPS
- PCH_TSE_SNM
- PCH_TSE_SNS
- PCH_TSE_TTIPEND
- PCH_TX_IFREG
- PCH_TX_OBJ_END
- PCH_TX_OBJ_NUM
- PCH_TX_OBJ_START
- PCH_TX_OK
- PCH_TX_THOLD
- PCH_UART_BRCSR
- PCH_UART_DLL
- PCH_UART_DLM
- PCH_UART_DRIVER_DEVICE
- PCH_UART_FCR_DMS
- PCH_UART_FCR_FIFO256
- PCH_UART_FCR_FIFOE
- PCH_UART_FCR_RFR
- PCH_UART_FCR_RFTL
- PCH_UART_FCR_RFTL1
- PCH_UART_FCR_RFTL128
- PCH_UART_FCR_RFTL14
- PCH_UART_FCR_RFTL16
- PCH_UART_FCR_RFTL224
- PCH_UART_FCR_RFTL32
- PCH_UART_FCR_RFTL4
- PCH_UART_FCR_RFTL56
- PCH_UART_FCR_RFTL64
- PCH_UART_FCR_RFTL8
- PCH_UART_FCR_RFTL_SHIFT
- PCH_UART_FCR_TFR
- PCH_UART_HAL_5BIT
- PCH_UART_HAL_6BIT
- PCH_UART_HAL_7BIT
- PCH_UART_HAL_8BIT
- PCH_UART_HAL_AFE
- PCH_UART_HAL_ALL_INT
- PCH_UART_HAL_CLR_ALL_FIFO
- PCH_UART_HAL_CLR_RX_FIFO
- PCH_UART_HAL_CLR_TX_FIFO
- PCH_UART_HAL_DMA_MODE0
- PCH_UART_HAL_DTR
- PCH_UART_HAL_FIFO16
- PCH_UART_HAL_FIFO256
- PCH_UART_HAL_FIFO64
- PCH_UART_HAL_FIFO_DIS
- PCH_UART_HAL_LOOP
- PCH_UART_HAL_MS_INT
- PCH_UART_HAL_OUT
- PCH_UART_HAL_PARITY_EVEN
- PCH_UART_HAL_PARITY_FIX0
- PCH_UART_HAL_PARITY_FIX1
- PCH_UART_HAL_PARITY_NONE
- PCH_UART_HAL_PARITY_ODD
- PCH_UART_HAL_RTS
- PCH_UART_HAL_RX_ERR_INT
- PCH_UART_HAL_RX_INT
- PCH_UART_HAL_STB1
- PCH_UART_HAL_STB2
- PCH_UART_HAL_TRIGGER1
- PCH_UART_HAL_TRIGGER128
- PCH_UART_HAL_TRIGGER14
- PCH_UART_HAL_TRIGGER16
- PCH_UART_HAL_TRIGGER224
- PCH_UART_HAL_TRIGGER32
- PCH_UART_HAL_TRIGGER4
- PCH_UART_HAL_TRIGGER56
- PCH_UART_HAL_TRIGGER64
- PCH_UART_HAL_TRIGGER8
- PCH_UART_HAL_TRIGGER_H
- PCH_UART_HAL_TRIGGER_L
- PCH_UART_HAL_TRIGGER_M
- PCH_UART_HAL_TX_INT
- PCH_UART_HANDLED_LS_INT
- PCH_UART_HANDLED_LS_INT_SHIFT
- PCH_UART_HANDLED_MS_INT
- PCH_UART_HANDLED_MS_INT_SHIFT
- PCH_UART_HANDLED_RX_ERR_INT
- PCH_UART_HANDLED_RX_ERR_INT_SHIFT
- PCH_UART_HANDLED_RX_INT
- PCH_UART_HANDLED_RX_INT_SHIFT
- PCH_UART_HANDLED_RX_TRG_INT
- PCH_UART_HANDLED_RX_TRG_INT_SHIFT
- PCH_UART_HANDLED_TX_INT
- PCH_UART_HANDLED_TX_INT_SHIFT
- PCH_UART_IER_EDSSI
- PCH_UART_IER_ELSI
- PCH_UART_IER_ERBFI
- PCH_UART_IER_ETBEI
- PCH_UART_IER_MASK
- PCH_UART_IID_MS
- PCH_UART_IID_RDR
- PCH_UART_IID_RDR_TO
- PCH_UART_IID_RLS
- PCH_UART_IID_THRE
- PCH_UART_IIR_FE
- PCH_UART_IIR_FIFO256
- PCH_UART_IIR_FIFO64
- PCH_UART_IIR_IID
- PCH_UART_IIR_IP
- PCH_UART_IIR_MSI
- PCH_UART_IIR_REI
- PCH_UART_IIR_RRI
- PCH_UART_IIR_TOI
- PCH_UART_IIR_TRI
- PCH_UART_LCR_0P
- PCH_UART_LCR_1P
- PCH_UART_LCR_5BIT
- PCH_UART_LCR_6BIT
- PCH_UART_LCR_7BIT
- PCH_UART_LCR_8BIT
- PCH_UART_LCR_DLAB
- PCH_UART_LCR_EP
- PCH_UART_LCR_EPS
- PCH_UART_LCR_NP
- PCH_UART_LCR_OP
- PCH_UART_LCR_PEN
- PCH_UART_LCR_SB
- PCH_UART_LCR_SP
- PCH_UART_LCR_STB
- PCH_UART_LCR_WLS
- PCH_UART_LSR_DR
- PCH_UART_LSR_ERR
- PCH_UART_MCR_AFE
- PCH_UART_MCR_DTR
- PCH_UART_MCR_LOOP
- PCH_UART_MCR_OUT
- PCH_UART_MCR_RTS
- PCH_UART_MSR_CTS
- PCH_UART_MSR_DCD
- PCH_UART_MSR_DCTS
- PCH_UART_MSR_DDCD
- PCH_UART_MSR_DDSR
- PCH_UART_MSR_DELTA
- PCH_UART_MSR_DSR
- PCH_UART_MSR_RI
- PCH_UART_MSR_TERI
- PCH_UART_NR
- PCH_UART_RBR
- PCH_UART_THR
- PCH_UDC_BRLEN
- PCH_UDC_BS_DMA_BSY
- PCH_UDC_BS_DMA_DONE
- PCH_UDC_BS_HST_BSY
- PCH_UDC_BS_HST_RDY
- PCH_UDC_BUFF_STS
- PCH_UDC_CSR
- PCH_UDC_DMA_LAST
- PCH_UDC_EP0
- PCH_UDC_EP1
- PCH_UDC_EP2
- PCH_UDC_EP3
- PCH_UDC_EPINT
- PCH_UDC_EP_NUM
- PCH_UDC_PCI_BAR
- PCH_UDC_PCI_BAR_QUARK_X1000
- PCH_UDC_PM_OPS
- PCH_UDC_RTS_BUFERR
- PCH_UDC_RTS_DESERR
- PCH_UDC_RTS_SUCC
- PCH_UDC_RXTX_BYTES
- PCH_UDC_RXTX_STS
- PCH_UDC_THLEN
- PCH_UDC_USED_EP_NUM
- PCH_UNSUPPORTED
- PCH_VBLANK_B
- PCH_VBUS_INTERVAL
- PCH_VBUS_PERIOD
- PCH_VSYNC_B
- PCH_VTOTAL_B
- PCH_WORD_ADDR_MASK
- PCH_WRITABLE
- PCI
- PCI0_ADDR
- PCI0_BASE_ADDR
- PCI171X_AD_DATA_REG
- PCI171X_CLRFIFO_REG
- PCI171X_CLRINT_REG
- PCI171X_CTRL_CNT0
- PCI171X_CTRL_EXT
- PCI171X_CTRL_GATE
- PCI171X_CTRL_IRQEN
- PCI171X_CTRL_ONEFH
- PCI171X_CTRL_PACER
- PCI171X_CTRL_REG
- PCI171X_CTRL_SW
- PCI171X_DAREF
- PCI171X_DAREF_MASK
- PCI171X_DAREF_REG
- PCI171X_DA_REG
- PCI171X_DI_REG
- PCI171X_DO_REG
- PCI171X_MUX_CHAN
- PCI171X_MUX_CHANH
- PCI171X_MUX_CHANL
- PCI171X_MUX_REG
- PCI171X_RANGE_DIFF
- PCI171X_RANGE_GAIN
- PCI171X_RANGE_REG
- PCI171X_RANGE_UNI
- PCI171X_SOFTTRG_REG
- PCI171X_STATUS_FE
- PCI171X_STATUS_FF
- PCI171X_STATUS_FH
- PCI171X_STATUS_IRQ
- PCI171X_STATUS_REG
- PCI171X_TIMER_BASE
- PCI1720_AO_LSB_REG
- PCI1720_AO_MSB_REG
- PCI1720_AO_RANGE
- PCI1720_AO_RANGE_MASK
- PCI1720_AO_RANGE_REG
- PCI1720_BOARDID_REG
- PCI1720_SYNC_CTRL_REG
- PCI1720_SYNC_CTRL_SC0
- PCI1720_SYNC_REG
- PCI1723_AO_REG
- PCI1723_BOARD_ID_MASK
- PCI1723_BOARD_ID_REG
- PCI1723_CALIB_CTRL_CLK
- PCI1723_CALIB_CTRL_CS
- PCI1723_CALIB_CTRL_DAT
- PCI1723_CALIB_CTRL_REG
- PCI1723_CALIB_DATA_REG
- PCI1723_CALIB_STROBE_REG
- PCI1723_CTRL_BUSY
- PCI1723_CTRL_CHAN
- PCI1723_CTRL_GAIN
- PCI1723_CTRL_IDX
- PCI1723_CTRL_INIT
- PCI1723_CTRL_OFFSET
- PCI1723_CTRL_RANGE
- PCI1723_CTRL_REG
- PCI1723_CTRL_SEL
- PCI1723_CTRL_SELF
- PCI1723_DIO_CTRL_HDIO
- PCI1723_DIO_CTRL_LDIO
- PCI1723_DIO_CTRL_REG
- PCI1723_DIO_DATA_REG
- PCI1723_RANGE_STROBE_REG
- PCI1723_RESET_AO_STROBE_REG
- PCI1723_RESET_CALIB_STROBE_REG
- PCI1723_SYNC_CTRL
- PCI1723_SYNC_CTRL_ASYNC
- PCI1723_SYNC_CTRL_REG
- PCI1723_SYNC_CTRL_SYNC
- PCI1723_SYNC_STROBE_REG
- PCI1723_VREF
- PCI1723_VREF_0V
- PCI1723_VREF_NEG10V
- PCI1723_VREF_POS10V
- PCI1723_VREF_REG
- PCI1724_BOARD_ID_MASK
- PCI1724_BOARD_ID_REG
- PCI1724_DAC_CTRL_CX
- PCI1724_DAC_CTRL_DATA
- PCI1724_DAC_CTRL_GX
- PCI1724_DAC_CTRL_MODE
- PCI1724_DAC_CTRL_MODE_GAIN
- PCI1724_DAC_CTRL_MODE_MASK
- PCI1724_DAC_CTRL_MODE_NORMAL
- PCI1724_DAC_CTRL_MODE_OFFSET
- PCI1724_DAC_CTRL_REG
- PCI1724_EEPROM_CTRL_REG
- PCI1724_SYNC_CTRL_DACSTAT
- PCI1724_SYNC_CTRL_REG
- PCI1724_SYNC_CTRL_SYN
- PCI1724_SYNC_TRIG_REG
- PCI173X_INT_CLR_REG
- PCI173X_INT_EN_REG
- PCI173X_INT_RF_REG
- PCI1750_INT_REG
- PCI1752_CFC_REG
- PCI1753E_INT_REG
- PCI1753_INT_REG
- PCI1754_INT_REG
- PCI1760_CMD_CLR_IMB2
- PCI1760_CMD_ENA_CNT
- PCI1760_CMD_ENA_CNT_MATCH
- PCI1760_CMD_ENA_CNT_OFLOW
- PCI1760_CMD_ENA_FALL_EDGE
- PCI1760_CMD_ENA_FILT
- PCI1760_CMD_ENA_PAT_MATCH
- PCI1760_CMD_ENA_PWM
- PCI1760_CMD_ENA_RISE_EDGE
- PCI1760_CMD_GET_CNT
- PCI1760_CMD_GET_CNT_STATUS
- PCI1760_CMD_GET_DO
- PCI1760_CMD_GET_FW_VER
- PCI1760_CMD_GET_HW_VER
- PCI1760_CMD_GET_INT_FLAGS
- PCI1760_CMD_GET_INT_FLAGS_COS
- PCI1760_CMD_GET_INT_FLAGS_MATCH
- PCI1760_CMD_GET_INT_FLAGS_OFLOW
- PCI1760_CMD_GET_OS
- PCI1760_CMD_GET_STATUS
- PCI1760_CMD_RETRIES
- PCI1760_CMD_RST_CNT
- PCI1760_CMD_SET_CNT
- PCI1760_CMD_SET_CNT_EDGE
- PCI1760_CMD_SET_CNT_MATCH
- PCI1760_CMD_SET_DO
- PCI1760_CMD_SET_HI_SAMP
- PCI1760_CMD_SET_LO_SAMP
- PCI1760_CMD_SET_PAT_MATCH
- PCI1760_CMD_SET_PWM_CNT
- PCI1760_CMD_SET_PWM_HI
- PCI1760_CMD_SET_PWM_LO
- PCI1760_CMD_TIMEOUT
- PCI1760_IMB_REG
- PCI1760_INTCSR1_IRQ_ENA
- PCI1760_INTCSR2_IMB_IRQ
- PCI1760_INTCSR2_IRQ_ASSERTED
- PCI1760_INTCSR2_IRQ_STATUS
- PCI1760_INTCSR2_OMB_IRQ
- PCI1760_INTCSR_REG
- PCI1760_OMB_REG
- PCI1760_PWM_TIMEBASE
- PCI1761_INT_CLR_REG
- PCI1761_INT_EN_REG
- PCI1761_INT_RF_REG
- PCI1762_INT_REG
- PCI200SYN_PLX_SIZE
- PCI200SYN_SCA_SIZE
- PCI224_DACCEN
- PCI224_DACCON
- PCI224_DACCON_BUSY
- PCI224_DACCON_FIFOENAB
- PCI224_DACCON_FIFOFL
- PCI224_DACCON_FIFOFL_EMPTY
- PCI224_DACCON_FIFOFL_FULL
- PCI224_DACCON_FIFOFL_HALFTOFULL
- PCI224_DACCON_FIFOFL_MASK
- PCI224_DACCON_FIFOFL_ONETOHALF
- PCI224_DACCON_FIFOINTR
- PCI224_DACCON_FIFOINTR_EMPTY
- PCI224_DACCON_FIFOINTR_FULL
- PCI224_DACCON_FIFOINTR_HALF
- PCI224_DACCON_FIFOINTR_MASK
- PCI224_DACCON_FIFOINTR_NEMPTY
- PCI224_DACCON_FIFOINTR_NFULL
- PCI224_DACCON_FIFOINTR_NHALF
- PCI224_DACCON_FIFORESET
- PCI224_DACCON_FIFOWRAP
- PCI224_DACCON_GLOBALRESET
- PCI224_DACCON_POLAR
- PCI224_DACCON_POLAR_BI
- PCI224_DACCON_POLAR_MASK
- PCI224_DACCON_POLAR_UNI
- PCI224_DACCON_TRIG
- PCI224_DACCON_TRIG_EXTN
- PCI224_DACCON_TRIG_EXTP
- PCI224_DACCON_TRIG_MASK
- PCI224_DACCON_TRIG_NONE
- PCI224_DACCON_TRIG_SW
- PCI224_DACCON_TRIG_Z2CT0
- PCI224_DACCON_TRIG_Z2CT1
- PCI224_DACCON_TRIG_Z2CT2
- PCI224_DACCON_VREF
- PCI224_DACCON_VREF_10
- PCI224_DACCON_VREF_1_25
- PCI224_DACCON_VREF_2_5
- PCI224_DACCON_VREF_5
- PCI224_DACCON_VREF_MASK
- PCI224_DACDATA
- PCI224_FIFOSIZ
- PCI224_FIFO_ROOM_EMPTY
- PCI224_FIFO_ROOM_FULL
- PCI224_FIFO_ROOM_HALFTOFULL
- PCI224_FIFO_ROOM_ONETOHALF
- PCI224_FIFO_SIZE
- PCI224_INTR_DAC
- PCI224_INTR_EDGE_BITS
- PCI224_INTR_EXT
- PCI224_INTR_LEVEL_BITS
- PCI224_INTR_Z2CT1
- PCI224_INT_SCE
- PCI224_SOFTTRIG
- PCI224_Z2_BASE
- PCI224_ZCLK_SCE
- PCI224_ZGAT_SCE
- PCI230P2_DACDATA
- PCI230P2_DACEN
- PCI230P2_DACSWTRIG
- PCI230P2_DAC_FIFOLEVEL_FULL
- PCI230P2_DAC_FIFOLEVEL_HALF
- PCI230P2_DAC_FIFOROOM_EMPTY
- PCI230P2_DAC_FIFOROOM_FULL
- PCI230P2_DAC_FIFOROOM_HALFTOFULL
- PCI230P2_DAC_FIFOROOM_ONETOHALF
- PCI230P2_DAC_FIFO_EMPTY
- PCI230P2_DAC_FIFO_EN
- PCI230P2_DAC_FIFO_FULL
- PCI230P2_DAC_FIFO_HALF
- PCI230P2_DAC_FIFO_RESET
- PCI230P2_DAC_FIFO_UNDERRUN_CLEAR
- PCI230P2_DAC_FIFO_UNDERRUN_LATCHED
- PCI230P2_DAC_FIFO_WRAP
- PCI230P2_DAC_INT_FIFO
- PCI230P2_DAC_INT_FIFO_EMPTY
- PCI230P2_DAC_INT_FIFO_FULL
- PCI230P2_DAC_INT_FIFO_HALF
- PCI230P2_DAC_INT_FIFO_MASK
- PCI230P2_DAC_INT_FIFO_NEMPTY
- PCI230P2_DAC_INT_FIFO_NFULL
- PCI230P2_DAC_INT_FIFO_NHALF
- PCI230P2_DAC_TRIG
- PCI230P2_DAC_TRIG_EXTN
- PCI230P2_DAC_TRIG_EXTP
- PCI230P2_DAC_TRIG_MASK
- PCI230P2_DAC_TRIG_NONE
- PCI230P2_DAC_TRIG_SW
- PCI230P2_DAC_TRIG_Z2CT0
- PCI230P2_DAC_TRIG_Z2CT1
- PCI230P2_DAC_TRIG_Z2CT2
- PCI230P2_EXTFUNC_DACFIFO
- PCI230P2_INT_DAC
- PCI230P_ADCFFLEV
- PCI230P_ADCFFTH
- PCI230P_ADCHYST
- PCI230P_ADCPTSC
- PCI230P_ADCTH
- PCI230P_ADCTRIG
- PCI230P_ADC_INT_FIFO_THRESH
- PCI230P_EXTFUNC
- PCI230P_EXTFUNC_GAT_EXTTRIG
- PCI230P_HWVER
- PCI230_ADCCON
- PCI230_ADCDATA
- PCI230_ADCEN
- PCI230_ADCG
- PCI230_ADCSWTRIG
- PCI230_ADC_BUSY
- PCI230_ADC_FIFOLEVEL_FULL
- PCI230_ADC_FIFOLEVEL_HALFFULL
- PCI230_ADC_FIFO_EMPTY
- PCI230_ADC_FIFO_EN
- PCI230_ADC_FIFO_FULL
- PCI230_ADC_FIFO_FULL_LATCHED
- PCI230_ADC_FIFO_HALF
- PCI230_ADC_FIFO_RESET
- PCI230_ADC_GLOB_RESET
- PCI230_ADC_IM
- PCI230_ADC_IM_DIF
- PCI230_ADC_IM_MASK
- PCI230_ADC_IM_SE
- PCI230_ADC_INT_FIFO
- PCI230_ADC_INT_FIFO_EMPTY
- PCI230_ADC_INT_FIFO_FULL
- PCI230_ADC_INT_FIFO_HALF
- PCI230_ADC_INT_FIFO_MASK
- PCI230_ADC_INT_FIFO_NEMPTY
- PCI230_ADC_INT_FIFO_NFULL
- PCI230_ADC_INT_FIFO_NHALF
- PCI230_ADC_IR
- PCI230_ADC_IR_BIP
- PCI230_ADC_IR_MASK
- PCI230_ADC_IR_UNI
- PCI230_ADC_TRIG
- PCI230_ADC_TRIG_EXTN
- PCI230_ADC_TRIG_EXTP
- PCI230_ADC_TRIG_MASK
- PCI230_ADC_TRIG_NONE
- PCI230_ADC_TRIG_SW
- PCI230_ADC_TRIG_Z2CT0
- PCI230_ADC_TRIG_Z2CT1
- PCI230_ADC_TRIG_Z2CT2
- PCI230_DACCON
- PCI230_DACOUT1
- PCI230_DACOUT2
- PCI230_DAC_BUSY
- PCI230_DAC_OR
- PCI230_DAC_OR_BIP
- PCI230_DAC_OR_MASK
- PCI230_DAC_OR_UNI
- PCI230_INT_ADC
- PCI230_INT_DISABLE
- PCI230_INT_PPI_C0
- PCI230_INT_PPI_C3
- PCI230_INT_SCE
- PCI230_INT_STAT
- PCI230_INT_ZCLK_CT1
- PCI230_PPI_X_A
- PCI230_PPI_X_B
- PCI230_PPI_X_BASE
- PCI230_PPI_X_C
- PCI230_PPI_X_CMD
- PCI230_Z2_CT_BASE
- PCI230_ZCLK_SCE
- PCI230_ZGAT_SCE
- PCI236_INTR_DISABLE
- PCI236_INTR_ENABLE
- PCI263_DO_0_7_REG
- PCI263_DO_8_15_REG
- PCI2_IRQ
- PCI32ADDR_HIGH
- PCI32ADDR_HIGH_SHIFT
- PCI32_DIRECT_BASE
- PCI32_LOCAL_BASE
- PCI32_MAPPED_BASE
- PCI6208_AO_CONTROL
- PCI6208_AO_STATUS
- PCI6208_AO_STATUS_DATA_SEND
- PCI6208_DIO
- PCI6208_DIO_DI_MASK
- PCI6208_DIO_DI_SHIFT
- PCI6208_DIO_DO_MASK
- PCI6208_DIO_DO_SHIFT
- PCI64ADDR_HIGH
- PCI64ADDR_HIGH_SHIFT
- PCI64BIT
- PCI64_ADDR_BASE
- PCI64_ATTR_BAR
- PCI64_ATTR_PREC
- PCI64_ATTR_PREF
- PCI64_ATTR_RMF_MASK
- PCI64_ATTR_RMF_SHFT
- PCI64_ATTR_TARG_MASK
- PCI64_ATTR_TARG_SHFT
- PCI64_ATTR_VIRTUAL
- PCI64_REQUIRED_MASK
- PCI66
- PCI743X_DIO_REG
- PCI7X3X_DIO_REG
- PCI8164_AXIS
- PCI8164_BUF0_REG
- PCI8164_BUF1_REG
- PCI8164_CMD_MSTS_REG
- PCI8164_OTP_SSTS_REG
- PCI9050_E1_RESET
- PCI9050_E1_RUN
- PCI9050_INTR_REG
- PCI9050_INTR_REG_EN1
- PCI9050_INTR_REG_ENPCI
- PCI9050_INTR_REG_POL1
- PCI9050_INTR_REG_STAT1
- PCI9050_USER_IO
- PCI9050_USER_IO_DAT3
- PCI9050_USER_IO_DIR3
- PCI9050_USER_IO_EN3
- PCI9111_8254_BASE_REG
- PCI9111_AI_ACQUISITION_PERIOD_MIN_NS
- PCI9111_AI_CHANNEL_REG
- PCI9111_AI_FIFO_REG
- PCI9111_AI_INSTANT_READ_UDELAY_US
- PCI9111_AI_RANGE
- PCI9111_AI_RANGE_MASK
- PCI9111_AI_RANGE_STAT_REG
- PCI9111_AI_STAT_AD_BUSY
- PCI9111_AI_STAT_FF_EF
- PCI9111_AI_STAT_FF_FF
- PCI9111_AI_STAT_FF_HF
- PCI9111_AI_TRIG_CTRL_ASCAN
- PCI9111_AI_TRIG_CTRL_ETIS
- PCI9111_AI_TRIG_CTRL_POTRG
- PCI9111_AI_TRIG_CTRL_PTRG
- PCI9111_AI_TRIG_CTRL_REG
- PCI9111_AI_TRIG_CTRL_TPST
- PCI9111_AI_TRIG_CTRL_TRGEVENT
- PCI9111_AO_REG
- PCI9111_DIO_REG
- PCI9111_EDIO_REG
- PCI9111_FIFO_HALF_SIZE
- PCI9111_INT_CLR_REG
- PCI9111_INT_CTRL_FFEN
- PCI9111_INT_CTRL_ISC0
- PCI9111_INT_CTRL_ISC1
- PCI9111_INT_CTRL_ISC2
- PCI9111_INT_CTRL_REG
- PCI9111_LI1_ACTIVE
- PCI9111_LI2_ACTIVE
- PCI9111_RANGE_SETTING_DELAY
- PCI9111_SOFT_TRIG_REG
- PCI9118_AI_AUTOSCAN_MODE_REG
- PCI9118_AI_BURST_NUM_REG
- PCI9118_AI_CFG_AM
- PCI9118_AI_CFG_BM
- PCI9118_AI_CFG_BS
- PCI9118_AI_CFG_BSSH
- PCI9118_AI_CFG_PDTRG
- PCI9118_AI_CFG_PETRG
- PCI9118_AI_CFG_PM
- PCI9118_AI_CFG_REG
- PCI9118_AI_CFG_START
- PCI9118_AI_CHANLIST_CHAN
- PCI9118_AI_CHANLIST_RANGE
- PCI9118_AI_CHANLIST_REG
- PCI9118_AI_CTRL_DIFF
- PCI9118_AI_CTRL_DMA
- PCI9118_AI_CTRL_EXTG
- PCI9118_AI_CTRL_EXTM
- PCI9118_AI_CTRL_INT
- PCI9118_AI_CTRL_REG
- PCI9118_AI_CTRL_SOFTG
- PCI9118_AI_CTRL_TMRTR
- PCI9118_AI_CTRL_UNIP
- PCI9118_AI_FIFO_REG
- PCI9118_AI_STATUS_ACMP
- PCI9118_AI_STATUS_ADOR
- PCI9118_AI_STATUS_ADOS
- PCI9118_AI_STATUS_ADRDY
- PCI9118_AI_STATUS_BOVER
- PCI9118_AI_STATUS_DTH
- PCI9118_AI_STATUS_NEPTY
- PCI9118_AI_STATUS_NFULL
- PCI9118_AI_STATUS_NHFULL
- PCI9118_AI_STATUS_REG
- PCI9118_AO_REG
- PCI9118_DIO_REG
- PCI9118_FIFO_RESET_REG
- PCI9118_INT_CTRL_ABOUT
- PCI9118_INT_CTRL_DTRG
- PCI9118_INT_CTRL_HFULL
- PCI9118_INT_CTRL_REG
- PCI9118_INT_CTRL_TIMER
- PCI9118_SOFTTRG_REG
- PCI9118_TIMER_BASE
- PCIA
- PCIAGP_FAIL
- PCIAPCNTREG
- PCIAdapter
- PCIB
- PCIBAR0
- PCIBAR1
- PCIBIOS_BAD_REGISTER_NUMBER
- PCIBIOS_BAD_VENDOR_ID
- PCIBIOS_BUFFER_TOO_SMALL
- PCIBIOS_DEVICE_NOT_FOUND
- PCIBIOS_FIND_PCI_CLASS_CODE
- PCIBIOS_FIND_PCI_DEVICE
- PCIBIOS_FUNC_NOT_SUPPORTED
- PCIBIOS_GENERATE_SPECIAL_CYCLE
- PCIBIOS_GET_ROUTING_OPTIONS
- PCIBIOS_HW_TYPE1
- PCIBIOS_HW_TYPE1_SPEC
- PCIBIOS_HW_TYPE2
- PCIBIOS_HW_TYPE2_SPEC
- PCIBIOS_MAX_MEM
- PCIBIOS_MIN_CARDBUS_IO
- PCIBIOS_MIN_IO
- PCIBIOS_MIN_MEM
- PCIBIOS_PCI_BIOS_PRESENT
- PCIBIOS_PCI_FUNCTION_ID
- PCIBIOS_READ_CONFIG_BYTE
- PCIBIOS_READ_CONFIG_DWORD
- PCIBIOS_READ_CONFIG_WORD
- PCIBIOS_SET_FAILED
- PCIBIOS_SET_PCI_HW_INT
- PCIBIOS_SUCCESSFUL
- PCIBIOS_WRITE_CONFIG_BYTE
- PCIBIOS_WRITE_CONFIG_DWORD
- PCIBIOS_WRITE_CONFIG_WORD
- PCIBRI_AHBAMR0
- PCIBRI_AHBAMR1
- PCIBRI_AHBAMR2
- PCIBRI_AHBAMR3
- PCIBRI_AHBAMR4
- PCIBRI_AHBAMR5
- PCIBRI_AHBBAR0
- PCIBRI_AHBBAR1
- PCIBRI_AHBBAR2
- PCIBRI_AHBBAR3
- PCIBRI_AHBBAR4
- PCIBRI_AHBBAR5
- PCIBRI_AHBCTL0
- PCIBRI_AHBCTL1
- PCIBRI_AHBCTL2
- PCIBRI_AHBCTL3
- PCIBRI_AHBCTL4
- PCIBRI_AHBCTL5
- PCIBRI_AHBTAR0
- PCIBRI_AHBTAR1
- PCIBRI_AHBTAR2
- PCIBRI_AHBTAR3
- PCIBRI_AHBTAR4
- PCIBRI_AHBTAR5
- PCIBRI_BAR0
- PCIBRI_BAR1
- PCIBRI_BAR2
- PCIBRI_BAR3
- PCIBRI_BAR4
- PCIBRI_BAR5
- PCIBRI_BARx_ADDR
- PCIBRI_BARx_IO
- PCIBRI_BARx_MEM
- PCIBRI_CLASS
- PCIBRI_CMD
- PCIBRI_CMD_IO
- PCIBRI_CMD_MEM
- PCIBRI_CTLx_AT
- PCIBRI_CTLx_MRL
- PCIBRI_CTLx_PREF
- PCIBRI_ID
- PCIBRI_LTR
- PCIBRI_PCIAMR0
- PCIBRI_PCIAMR1
- PCIBRI_PCIAMR2
- PCIBRI_PCIAMR3
- PCIBRI_PCIAMR4
- PCIBRI_PCIAMR5
- PCIBRI_PCIBAR0
- PCIBRI_PCIBAR1
- PCIBRI_PCIBAR2
- PCIBRI_PCIBAR3
- PCIBRI_PCIBAR4
- PCIBRI_PCIBAR5
- PCIBRI_PCICTL0
- PCIBRI_PCICTL1
- PCIBRI_PCICTL2
- PCIBRI_PCICTL3
- PCIBRI_PCICTL4
- PCIBRI_PCICTL5
- PCIBRI_PCITAR0
- PCIBRI_PCITAR1
- PCIBRI_PCITAR2
- PCIBRI_PCITAR3
- PCIBRI_PCITAR4
- PCIBRI_PCITAR5
- PCIB_op_pending
- PCIBurstCnt
- PCIBusCfg
- PCIBusCfg_bits
- PCIBusConfig
- PCIBusConfig1
- PCIBusErr170
- PCIBusErr175
- PCIC
- PCIC0_PCISERR
- PCIC1
- PCIC1_PCIDMA0
- PCIC1_PCIDMA1
- PCIC1_PCIDMA2
- PCIC1_PCIDMA3
- PCIC1_PCIERR
- PCIC1_PCIPWDWN
- PCIC1_PCIPWON
- PCIC5
- PCICAR
- PCICAR_BUSN
- PCICAR_DEVFNN
- PCICAR_DWORDN
- PCICAR_E
- PCICCPR
- PCICCRIR
- PCICFG0_BASE
- PCICFG0_SIZE
- PCICFG1_BASE
- PCICFG1_SIZE
- PCICFG_ADDR
- PCICFG_BAR_1_HIGH
- PCICFG_BAR_1_LOW
- PCICFG_BAR_2_HIGH
- PCICFG_BAR_2_LOW
- PCICFG_BRIBASE
- PCICFG_CACHE_LINE_SIZE
- PCICFG_COMMAND_BUS_MASTER
- PCICFG_COMMAND_FAST_B2B
- PCICFG_COMMAND_INT_DISABLE
- PCICFG_COMMAND_IO_SPACE
- PCICFG_COMMAND_MEM_SPACE
- PCICFG_COMMAND_MWI_CYCLES
- PCICFG_COMMAND_OFFSET
- PCICFG_COMMAND_PERR_ENA
- PCICFG_COMMAND_RESERVED
- PCICFG_COMMAND_SERR_ENA
- PCICFG_COMMAND_SPECIAL_CYCLES
- PCICFG_COMMAND_STEPPING
- PCICFG_COMMAND_VGA_SNOOP
- PCICFG_DATA
- PCICFG_DESC_RING_STATUS
- PCICFG_DEVICE_CONTROL
- PCICFG_DEVICE_ID_OFFSET
- PCICFG_DEVICE_STATUS
- PCICFG_DEVICE_STATUS_AUX_PWR_DET
- PCICFG_DEVICE_STATUS_CORR_ERR_DET
- PCICFG_DEVICE_STATUS_FATAL_ERR_DET
- PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET
- PCICFG_DEVICE_STATUS_NO_PEND
- PCICFG_DEVICE_STATUS_UNSUP_REQ_DET
- PCICFG_GRC_ADDRESS
- PCICFG_GRC_DATA
- PCICFG_INT_LINE
- PCICFG_INT_PIN
- PCICFG_LATENCY_TIMER
- PCICFG_LINK_CONTROL
- PCICFG_LINK_SPEED
- PCICFG_LINK_SPEED_SHIFT
- PCICFG_LINK_WIDTH
- PCICFG_LINK_WIDTH_SHIFT
- PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET
- PCICFG_ME_REGISTER
- PCICFG_MSIX_CAP_ID_OFFSET
- PCICFG_MSIX_CONTROL_FUNC_MASK
- PCICFG_MSIX_CONTROL_MSIX_ENABLE
- PCICFG_MSIX_CONTROL_RESERVED
- PCICFG_MSIX_CONTROL_TABLE_SIZE
- PCICFG_MSI_CAP_ID_OFFSET
- PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP
- PCICFG_MSI_CONTROL_ENABLE
- PCICFG_MSI_CONTROL_MCAP
- PCICFG_MSI_CONTROL_MENA
- PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE
- PCICFG_OFFSET
- PCICFG_ONLINE0
- PCICFG_ONLINE1
- PCICFG_PM_CAPABILITY
- PCICFG_PM_CAPABILITY_AUX_CURRENT
- PCICFG_PM_CAPABILITY_CLOCK
- PCICFG_PM_CAPABILITY_D1_SUPPORT
- PCICFG_PM_CAPABILITY_D2_SUPPORT
- PCICFG_PM_CAPABILITY_DSI
- PCICFG_PM_CAPABILITY_PME_IN_D0
- PCICFG_PM_CAPABILITY_PME_IN_D1
- PCICFG_PM_CAPABILITY_PME_IN_D2
- PCICFG_PM_CAPABILITY_PME_IN_D3_COLD
- PCICFG_PM_CAPABILITY_PME_IN_D3_HOT
- PCICFG_PM_CAPABILITY_RESERVED
- PCICFG_PM_CAPABILITY_VERSION
- PCICFG_PM_CONTROL_MASK
- PCICFG_PM_CONTROL_OFFSET
- PCICFG_PM_CSR_OFFSET
- PCICFG_PM_CSR_PME_ENABLE
- PCICFG_PM_CSR_PME_STATUS
- PCICFG_PM_CSR_STATE
- PCICFG_REVESION_ID_ERROR_VAL
- PCICFG_REVESION_ID_MASK
- PCICFG_REVISION_ID_OFFSET
- PCICFG_STATUS_OFFSET
- PCICFG_SUBSYSTEM_ID_OFFSET
- PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET
- PCICFG_UE_STATUS_HIGH
- PCICFG_UE_STATUS_HI_MASK
- PCICFG_UE_STATUS_LOW
- PCICFG_UE_STATUS_LOW_MASK
- PCICFG_UE_STATUS_MASK_HI
- PCICFG_UE_STATUS_MASK_LOW
- PCICFG_VENDOR_ID_OFFSET
- PCICLK
- PCICLKRUNREG
- PCICLKSELREG
- PCICMD_ABORT
- PCICMD_ERROR_BITS
- PCICONF
- PCICONFAREG
- PCICONFDREG
- PCICPR
- PCICR1
- PCICR1_CL
- PCICR1_LT
- PCICR2
- PCICR_ENDIANNESS
- PCICSR
- PCICSR_BIG_ENDIAN
- PCICSR_BURST_LENTH
- PCICSR_ENABLE_CLK
- PCICSR_READ_MULTIPLE
- PCICSR_RX_TRESHOLD
- PCICSR_TX_TRESHOLD
- PCICSR_WRITE_INVALID
- PCIC_BASE1
- PCIC_BASEA
- PCIC_BASEB
- PCIC_BASEC
- PCIC_CACHELINE_SIZE
- PCIC_CLASS_CODE
- PCIC_COMMAND
- PCIC_COUNT
- PCIC_DEVICE_ID
- PCIC_DEVREV_ID
- PCIC_FLASH_MBAR
- PCIC_HSTPCIX_CNTRL
- PCIC_INTRPT_STAT
- PCIC_IOBAR
- PCIC_IOBAR_OFFSET
- PCIC_MBAR0
- PCIC_MBAR0_MASK
- PCIC_MBAR0_OFFSET
- PCIC_MBAR0_SIZE
- PCIC_MBAR0_SIZE_MASK
- PCIC_MBAR0_SIZE_SHIFT
- PCIC_MBAR1
- PCIC_MBAR1_OFFSET
- PCIC_MBAR_KEY
- PCIC_PM_CSR
- PCIC_READ
- PCIC_STATUS
- PCIC_SUBSYTEM_ID
- PCIC_SUBVENDOR_ID
- PCIC_TP_CTRL
- PCIC_VENDOR_ID
- PCIC_WRITE
- PCIClkMeas
- PCID
- PCIDAC
- PCIDAS_8255_BASE
- PCIDAS_AI_8254_BASE
- PCIDAS_AI_CHAN
- PCIDAS_AI_DATA_REG
- PCIDAS_AI_EOC
- PCIDAS_AI_FIFO_CLR_REG
- PCIDAS_AI_FIRST
- PCIDAS_AI_GAIN
- PCIDAS_AI_LAST
- PCIDAS_AI_PACER
- PCIDAS_AI_PACER_EXTN
- PCIDAS_AI_PACER_EXTP
- PCIDAS_AI_PACER_INT
- PCIDAS_AI_PACER_MASK
- PCIDAS_AI_PACER_SW
- PCIDAS_AI_REG
- PCIDAS_AI_SE
- PCIDAS_AI_UNIP
- PCIDAS_AO_8254_BASE
- PCIDAS_AO_CHAN_EN
- PCIDAS_AO_CHAN_MASK
- PCIDAS_AO_DACEN
- PCIDAS_AO_DATA_REG
- PCIDAS_AO_EMPTY
- PCIDAS_AO_FIFO_CLR_REG
- PCIDAS_AO_FIFO_REG
- PCIDAS_AO_PACER
- PCIDAS_AO_PACER_EXTN
- PCIDAS_AO_PACER_EXTP
- PCIDAS_AO_PACER_INT
- PCIDAS_AO_PACER_MASK
- PCIDAS_AO_PACER_SW
- PCIDAS_AO_RANGE
- PCIDAS_AO_RANGE_MASK
- PCIDAS_AO_REG
- PCIDAS_AO_START
- PCIDAS_AO_UPDATE_BOTH
- PCIDAS_CALIB_8800_SEL
- PCIDAS_CALIB_DAC08_SEL
- PCIDAS_CALIB_DATA
- PCIDAS_CALIB_EN
- PCIDAS_CALIB_REG
- PCIDAS_CALIB_SRC
- PCIDAS_CALIB_TRIM_SEL
- PCIDAS_CTRL_ADHFI
- PCIDAS_CTRL_ADNE
- PCIDAS_CTRL_ADNEI
- PCIDAS_CTRL_AI_INT
- PCIDAS_CTRL_AO_INT
- PCIDAS_CTRL_DAEMI
- PCIDAS_CTRL_DAEMIE
- PCIDAS_CTRL_DAHFI
- PCIDAS_CTRL_DAHFIE
- PCIDAS_CTRL_EOAI
- PCIDAS_CTRL_EOAIE
- PCIDAS_CTRL_EOBI
- PCIDAS_CTRL_INT
- PCIDAS_CTRL_INTE
- PCIDAS_CTRL_INT_CLR
- PCIDAS_CTRL_INT_EOS
- PCIDAS_CTRL_INT_FHF
- PCIDAS_CTRL_INT_FNE
- PCIDAS_CTRL_INT_MASK
- PCIDAS_CTRL_INT_NONE
- PCIDAS_CTRL_LADFUL
- PCIDAS_CTRL_REG
- PCIDAS_TRIG_BURSTE
- PCIDAS_TRIG_CLR
- PCIDAS_TRIG_EN
- PCIDAS_TRIG_MODE
- PCIDAS_TRIG_POL
- PCIDAS_TRIG_REG
- PCIDAS_TRIG_SEL
- PCIDAS_TRIG_SEL_ANALOG
- PCIDAS_TRIG_SEL_EXT
- PCIDAS_TRIG_SEL_MASK
- PCIDAS_TRIG_SEL_NONE
- PCIDAS_TRIG_SEL_SW
- PCIDEF
- PCIDEVICE_LATENCY_TIMER_MIN
- PCIDEVICE_LATENCY_TIMER_VAL
- PCIDEVMASK
- PCIDE_BASE1
- PCIDE_BASE2
- PCIDE_BASE3
- PCIDE_BASE4
- PCIDE_BASE5
- PCIDE_BASE6
- PCIDMA
- PCIDMA_WIN0_BASE
- PCIDMA_WIN0_MASK
- PCIDMA_WIN0_MMAP
- PCIDMA_WIN1_BASE
- PCIDMA_WIN1_MASK
- PCIDMA_WIN1_MMAP
- PCIDMA_WIN2_BASE
- PCIDMA_WIN2_MASK
- PCIDMA_WIN2_MMAP
- PCIDMA_WIN3_BASE
- PCIDMA_WIN3_MASK
- PCIDMA_WIN3_MMAP
- PCIDeviceConfig
- PCIE
- PCIE00_VIRT_BASE
- PCIE01_VIRT_BASE
- PCIE02_VIRT_BASE
- PCIE03_VIRT_BASE
- PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK
- PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK
- PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT
- PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK
- PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT
- PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK
- PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- PCIE0_AUX_CLK_SRC
- PCIE0_AXI_CLK_SRC
- PCIE0_BASE__INST0_SEG0
- PCIE0_BASE__INST0_SEG1
- PCIE0_BASE__INST0_SEG2
- PCIE0_BASE__INST0_SEG3
- PCIE0_BASE__INST0_SEG4
- PCIE0_BASE__INST0_SEG5
- PCIE0_BASE__INST1_SEG0
- PCIE0_BASE__INST1_SEG1
- PCIE0_BASE__INST1_SEG2
- PCIE0_BASE__INST1_SEG3
- PCIE0_BASE__INST1_SEG4
- PCIE0_BASE__INST1_SEG5
- PCIE0_BASE__INST2_SEG0
- PCIE0_BASE__INST2_SEG1
- PCIE0_BASE__INST2_SEG2
- PCIE0_BASE__INST2_SEG3
- PCIE0_BASE__INST2_SEG4
- PCIE0_BASE__INST2_SEG5
- PCIE0_BASE__INST3_SEG0
- PCIE0_BASE__INST3_SEG1
- PCIE0_BASE__INST3_SEG2
- PCIE0_BASE__INST3_SEG3
- PCIE0_BASE__INST3_SEG4
- PCIE0_BASE__INST3_SEG5
- PCIE0_BASE__INST4_SEG0
- PCIE0_BASE__INST4_SEG1
- PCIE0_BASE__INST4_SEG2
- PCIE0_BASE__INST4_SEG3
- PCIE0_BASE__INST4_SEG4
- PCIE0_BASE__INST4_SEG5
- PCIE0_BASE__INST5_SEG0
- PCIE0_BASE__INST5_SEG1
- PCIE0_BASE__INST5_SEG2
- PCIE0_BASE__INST5_SEG3
- PCIE0_BASE__INST5_SEG4
- PCIE0_BASE__INST5_SEG5
- PCIE0_BASE__INST6_SEG0
- PCIE0_BASE__INST6_SEG1
- PCIE0_BASE__INST6_SEG2
- PCIE0_BASE__INST6_SEG3
- PCIE0_BASE__INST6_SEG4
- PCIE0_BASE__INST6_SEG5
- PCIE0_BASE__INST7_SEG0
- PCIE0_BASE__INST7_SEG1
- PCIE0_BASE__INST7_SEG2
- PCIE0_BASE__INST7_SEG3
- PCIE0_BASE__INST7_SEG4
- PCIE0_BASE__INST7_SEG5
- PCIE0_CFG_AUX_CLK_EN
- PCIE0_CFG_CORE_CLK_EN
- PCIE0_CFG_DEVICE_PRESENT
- PCIE0_CFG_POWERUP_RESET
- PCIE0_ERROR
- PCIE0_ERROR_MASK
- PCIE0_GDSC
- PCIE0_PHY_IDDQ_SHIFT
- PCIE0_PIPE_CLK_SRC
- PCIE10_VIRT_BASE
- PCIE11_VIRT_BASE
- PCIE12_VIRT_BASE
- PCIE13_VIRT_BASE
- PCIE1_AUX_CLK_SRC
- PCIE1_AXI_CLK_SRC
- PCIE1_CFG_AUX_CLK_EN
- PCIE1_CFG_CORE_CLK_EN
- PCIE1_CFG_DEVICE_PRESENT
- PCIE1_CFG_POWERUP_RESET
- PCIE1_ERROR
- PCIE1_ERROR_MASK
- PCIE1_GDSC
- PCIE1_PHY_IDDQ_SHIFT
- PCIE1_PIPE_CLK_SRC
- PCIE20_AXI_MSTR_RESP_COMP_CTRL0
- PCIE20_AXI_MSTR_RESP_COMP_CTRL1
- PCIE20_CAP
- PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT
- PCIE20_CAP_LINK_1
- PCIE20_CAP_LINK_CAPABILITIES
- PCIE20_COMMAND_STATUS
- PCIE20_DEVICE_CONTROL2_STATUS2
- PCIE20_ELBI_SYS_CTRL
- PCIE20_ELBI_SYS_CTRL_LT_ENABLE
- PCIE20_MISC_CONTROL_1_REG
- PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT
- PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2
- PCIE20_PARF_BDF_TRANSLATE_CFG
- PCIE20_PARF_CONFIGBITS
- PCIE20_PARF_DBI_BASE_ADDR
- PCIE20_PARF_LTSSM
- PCIE20_PARF_MHI_CLOCK_RESET_CTRL
- PCIE20_PARF_PCS_CTRL
- PCIE20_PARF_PCS_DEEMPH1
- PCIE20_PARF_PCS_DEEMPH2
- PCIE20_PARF_PCS_DEEMPH3
- PCIE20_PARF_PCS_SWING_CTRL1
- PCIE20_PARF_PCS_SWING_CTRL2
- PCIE20_PARF_PHY_CTRL
- PCIE20_PARF_PHY_CTRL3
- PCIE20_PARF_PHY_REFCLK
- PCIE20_PARF_PHY_REFCLK_CTRL2
- PCIE20_PARF_PHY_REFCLK_CTRL3
- PCIE20_PARF_PHY_STTS
- PCIE20_PARF_Q2A_FLUSH
- PCIE20_PARF_SID_OFFSET
- PCIE20_PARF_SLV_ADDR_SPACE_SIZE
- PCIE20_PARF_SYS_CTRL
- PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE
- PCIE2AHB_SIZE
- PCIE2CIO_CMD
- PCIE2CIO_CMD_CS_MASK
- PCIE2CIO_CMD_CS_SHIFT
- PCIE2CIO_CMD_PORT_MASK
- PCIE2CIO_CMD_PORT_SHIFT
- PCIE2CIO_CMD_START
- PCIE2CIO_CMD_TIMEOUT
- PCIE2CIO_CMD_WRITE
- PCIE2CIO_RDDATA
- PCIE2CIO_WRDATA
- PCIE2_CAP_DEVSTSCTRL2_LTRENAB
- PCIE2_CAP_DEVSTSCTRL2_OFFSET
- PCIE2_CFG_AUX_CLK_EN
- PCIE2_CFG_CORE_CLK_EN
- PCIE2_CFG_DEVICE_PRESENT
- PCIE2_CFG_POWERUP_RESET
- PCIE2_CLKC_DISABLE_L1CLK_GATING
- PCIE2_CLKC_DISSPROMLD
- PCIE2_CLKC_DLYPERST
- PCIE2_CLKC_RST
- PCIE2_CLKC_RST_OE
- PCIE2_CLKC_SPERST
- PCIE2_CLKC_WAKE_MODE_L2
- PCIE2_GDSC
- PCIE2_INTMASK
- PCIE2_INTSTATUS
- PCIE2_LTR_ACTIVE
- PCIE2_LTR_ACTIVE_IDLE
- PCIE2_LTR_FINAL_MASK
- PCIE2_LTR_FINAL_SHIFT
- PCIE2_LTR_SLEEP
- PCIE2_PHY_RESET_CTRL
- PCIE2_PMCR_REFUP
- PCIE2_PVT_REG_PM_CLK_PERIOD
- PCIE2_SBMBX
- PCIE8766_DEFAULT_FW_NAME
- PCIE8897_A0
- PCIE8897_A0_FW_NAME
- PCIE8897_B0
- PCIE8897_B0_FW_NAME
- PCIE8897_DEFAULT_FW_NAME
- PCIE8997_A0
- PCIE8997_A1
- PCIEBRIDGE_UNITID
- PCIECAR
- PCIECCTLR
- PCIECDR
- PCIECFG
- PCIECFG_CISRREN
- PCIECFG_CLKREQ_B
- PCIECFG_CORE_RESET_REQ
- PCIECFG_DBG_OEN
- PCIECFG_DEVICE_TYPE_MASK
- PCIECFG_LTSSM_ENABLE
- PCIECFG_MACRO_ENABLE
- PCIECFG_MODE_TX_DRV_EN
- PCIECFG_NOC_RESET
- PCIECFG_PCLK_ENABLE
- PCIECFG_PLL_ENABLE
- PCIECFG_REFCLKSEL
- PCIECFG_REFCLK_ENABLE
- PCIECFG_RISRCREN
- PCIECORE_CTLANDSTATUS
- PCIECR
- PCIECR_CLKEN
- PCIECR_ENBL
- PCIECR_PCIEMUX0
- PCIECR_PCIEMUX1
- PCIECR_PRST1
- PCIECR_PRST2
- PCIECR_PRST3
- PCIECR_PRST4
- PCIECTRL_DRA7XX_CONF_DEVICE_CMD
- PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN
- PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI
- PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
- PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI
- PCIECTRL_DRA7XX_CONF_PHY_CS
- PCIECTRL_TI_CONF_DEVICE_TYPE
- PCIECTRL_TI_CONF_INTX_ASSERT
- PCIECTRL_TI_CONF_INTX_DEASSERT
- PCIECTRL_TI_CONF_MSI_XMT
- PCIEDLINTENR_DLL_ACT_ENABLE
- PCIEERRFR
- PCIEFD_BAR0_SIZE
- PCIEFD_CANX_OFF
- PCIEFD_DRV_NAME
- PCIEFD_ECHO_SKB_MAX
- PCIEFD_FW_VERSION
- PCIEFD_REG_CAN_CLK_SEL
- PCIEFD_REG_CAN_CMD_PORT_H
- PCIEFD_REG_CAN_CMD_PORT_L
- PCIEFD_REG_CAN_MISC
- PCIEFD_REG_CAN_RX_CTL_ACK
- PCIEFD_REG_CAN_RX_CTL_CLR
- PCIEFD_REG_CAN_RX_CTL_SET
- PCIEFD_REG_CAN_RX_CTL_WRT
- PCIEFD_REG_CAN_RX_DMA_ADDR_H
- PCIEFD_REG_CAN_RX_DMA_ADDR_L
- PCIEFD_REG_CAN_TX_CTL_CLR
- PCIEFD_REG_CAN_TX_CTL_SET
- PCIEFD_REG_CAN_TX_DMA_ADDR_H
- PCIEFD_REG_CAN_TX_DMA_ADDR_L
- PCIEFD_REG_CAN_TX_REQ_ACC
- PCIEFD_REG_SYS_CTL_CLR
- PCIEFD_REG_SYS_CTL_SET
- PCIEFD_REG_SYS_VER1
- PCIEFD_REG_SYS_VER2
- PCIEFD_RX_DMA_SIZE
- PCIEFD_SYS_CTL_CLK_EN
- PCIEFD_SYS_CTL_TS_RST
- PCIEFD_TX_DMA_SIZE
- PCIEFD_TX_PAGE_COUNT
- PCIEFD_TX_PAGE_SIZE
- PCIEINTXR
- PCIELAMR
- PCIELAR
- PCIEMACCTLR_SCR_DIS
- PCIEMSIALR
- PCIEMSIAUR
- PCIEMSIFR
- PCIEMSIIER
- PCIEMSITXR
- PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_GBE0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_GBE1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_MP2_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PBA_0__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_0__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_1__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_1__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_2__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_2__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_3__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_3__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_4__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_4__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_5__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_5__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_6__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_6__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA_7__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA_7__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK
- PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_PSP_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT100_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT100_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT100_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT100_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT100_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT100_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT101_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT101_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT101_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT101_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT101_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT101_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT102_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT102_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT102_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT102_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT102_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT102_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT103_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT103_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT103_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT103_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT103_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT103_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT104_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT104_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT104_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT104_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT104_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT104_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT105_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT105_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT105_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT105_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT105_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT105_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT106_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT106_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT106_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT106_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT106_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT106_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT107_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT107_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT107_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT107_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT107_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT107_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT108_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT108_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT108_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT108_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT108_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT108_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT109_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT109_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT109_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT109_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT109_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT109_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT110_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT110_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT110_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT110_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT110_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT110_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT111_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT111_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT111_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT111_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT111_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT111_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT112_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT112_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT112_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT112_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT112_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT112_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT113_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT113_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT113_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT113_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT113_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT113_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT114_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT114_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT114_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT114_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT114_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT114_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT115_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT115_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT115_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT115_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT115_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT115_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT116_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT116_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT116_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT116_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT116_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT116_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT117_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT117_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT117_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT117_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT117_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT117_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT118_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT118_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT118_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT118_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT118_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT118_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT119_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT119_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT119_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT119_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT119_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT119_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT120_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT120_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT120_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT120_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT120_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT120_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT121_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT121_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT121_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT121_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT121_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT121_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT122_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT122_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT122_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT122_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT122_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT122_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT123_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT123_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT123_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT123_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT123_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT123_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT124_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT124_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT124_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT124_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT124_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT124_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT125_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT125_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT125_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT125_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT125_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT125_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT126_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT126_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT126_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT126_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT126_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT126_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT127_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT127_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT127_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT127_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT127_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT127_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT128_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT128_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT128_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT128_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT128_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT128_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT129_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT129_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT129_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT129_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT129_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT129_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT130_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT130_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT130_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT130_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT130_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT130_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT131_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT131_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT131_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT131_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT131_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT131_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT132_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT132_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT132_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT132_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT132_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT132_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT133_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT133_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT133_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT133_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT133_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT133_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT134_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT134_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT134_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT134_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT134_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT134_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT135_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT135_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT135_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT135_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT135_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT135_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT136_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT136_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT136_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT136_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT136_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT136_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT137_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT137_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT137_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT137_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT137_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT137_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT138_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT138_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT138_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT138_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT138_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT138_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT139_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT139_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT139_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT139_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT139_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT139_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT140_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT140_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT140_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT140_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT140_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT140_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT141_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT141_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT141_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT141_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT141_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT141_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT142_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT142_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT142_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT142_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT142_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT142_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT143_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT143_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT143_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT143_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT143_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT143_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT144_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT144_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT144_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT144_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT144_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT144_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT145_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT145_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT145_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT145_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT145_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT145_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT146_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT146_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT146_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT146_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT146_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT146_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT147_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT147_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT147_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT147_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT147_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT147_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT148_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT148_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT148_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT148_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT148_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT148_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT149_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT149_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT149_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT149_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT149_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT149_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT150_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT150_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT150_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT150_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT150_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT150_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT151_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT151_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT151_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT151_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT151_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT151_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT152_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT152_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT152_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT152_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT152_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT152_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT153_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT153_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT153_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT153_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT153_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT153_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT154_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT154_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT154_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT154_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT154_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT154_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT155_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT155_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT155_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT155_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT155_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT155_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT156_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT156_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT156_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT156_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT156_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT156_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT157_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT157_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT157_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT157_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT157_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT157_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT158_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT158_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT158_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT158_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT158_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT158_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT159_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT159_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT159_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT159_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT159_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT159_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT160_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT160_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT160_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT160_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT160_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT160_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT161_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT161_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT161_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT161_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT161_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT161_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT162_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT162_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT162_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT162_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT162_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT162_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT163_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT163_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT163_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT163_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT163_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT163_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT164_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT164_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT164_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT164_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT164_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT164_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT165_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT165_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT165_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT165_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT165_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT165_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT166_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT166_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT166_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT166_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT166_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT166_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT167_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT167_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT167_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT167_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT167_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT167_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT168_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT168_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT168_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT168_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT168_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT168_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT169_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT169_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT169_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT169_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT169_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT169_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT170_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT170_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT170_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT170_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT170_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT170_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT171_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT171_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT171_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT171_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT171_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT171_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT172_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT172_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT172_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT172_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT172_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT172_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT173_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT173_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT173_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT173_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT173_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT173_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT174_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT174_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT174_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT174_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT174_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT174_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT175_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT175_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT175_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT175_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT175_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT175_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT176_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT176_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT176_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT176_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT176_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT176_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT177_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT177_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT177_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT177_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT177_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT177_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT178_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT178_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT178_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT178_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT178_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT178_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT179_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT179_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT179_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT179_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT179_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT179_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT180_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT180_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT180_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT180_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT180_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT180_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT181_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT181_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT181_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT181_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT181_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT181_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT182_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT182_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT182_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT182_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT182_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT182_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT183_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT183_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT183_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT183_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT183_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT183_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT184_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT184_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT184_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT184_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT184_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT184_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT185_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT185_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT185_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT185_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT185_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT185_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT186_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT186_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT186_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT186_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT186_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT186_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT187_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT187_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT187_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT187_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT187_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT187_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT188_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT188_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT188_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT188_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT188_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT188_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT189_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT189_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT189_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT189_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT189_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT189_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT190_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT190_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT190_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT190_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT190_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT190_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT191_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT191_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT191_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT191_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT191_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT191_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT192_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT192_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT192_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT192_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT192_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT192_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT193_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT193_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT193_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT193_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT193_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT193_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT194_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT194_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT194_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT194_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT194_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT194_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT195_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT195_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT195_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT195_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT195_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT195_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT196_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT196_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT196_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT196_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT196_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT196_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT197_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT197_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT197_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT197_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT197_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT197_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT198_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT198_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT198_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT198_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT198_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT198_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT199_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT199_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT199_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT199_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT199_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT199_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT200_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT200_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT200_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT200_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT200_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT200_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT201_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT201_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT201_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT201_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT201_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT201_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT202_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT202_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT202_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT202_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT202_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT202_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT203_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT203_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT203_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT203_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT203_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT203_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT204_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT204_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT204_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT204_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT204_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT204_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT205_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT205_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT205_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT205_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT205_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT205_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT206_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT206_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT206_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT206_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT206_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT206_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT207_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT207_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT207_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT207_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT207_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT207_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT208_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT208_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT208_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT208_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT208_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT208_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT209_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT209_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT209_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT209_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT209_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT209_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT210_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT210_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT210_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT210_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT210_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT210_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT211_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT211_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT211_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT211_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT211_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT211_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT212_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT212_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT212_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT212_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT212_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT212_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT213_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT213_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT213_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT213_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT213_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT213_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT214_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT214_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT214_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT214_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT214_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT214_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT215_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT215_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT215_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT215_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT215_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT215_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT216_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT216_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT216_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT216_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT216_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT216_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT217_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT217_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT217_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT217_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT217_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT217_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT218_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT218_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT218_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT218_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT218_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT218_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT219_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT219_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT219_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT219_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT219_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT219_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT220_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT220_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT220_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT220_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT220_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT220_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT221_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT221_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT221_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT221_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT221_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT221_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT222_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT222_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT222_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT222_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT222_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT222_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT223_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT223_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT223_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT223_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT223_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT223_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT224_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT224_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT224_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT224_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT224_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT224_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT225_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT225_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT225_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT225_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT225_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT225_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT226_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT226_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT226_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT226_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT226_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT226_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT227_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT227_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT227_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT227_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT227_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT227_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT228_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT228_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT228_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT228_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT228_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT228_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT229_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT229_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT229_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT229_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT229_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT229_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT230_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT230_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT230_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT230_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT230_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT230_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT231_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT231_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT231_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT231_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT231_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT231_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT232_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT232_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT232_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT232_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT232_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT232_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT233_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT233_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT233_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT233_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT233_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT233_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT234_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT234_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT234_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT234_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT234_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT234_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT235_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT235_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT235_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT235_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT235_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT235_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT236_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT236_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT236_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT236_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT236_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT236_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT237_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT237_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT237_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT237_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT237_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT237_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT238_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT238_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT238_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT238_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT238_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT238_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT239_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT239_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT239_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT239_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT239_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT239_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT240_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT240_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT240_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT240_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT240_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT240_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT241_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT241_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT241_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT241_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT241_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT241_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT242_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT242_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT242_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT242_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT242_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT242_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT243_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT243_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT243_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT243_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT243_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT243_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT244_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT244_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT244_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT244_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT244_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT244_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT245_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT245_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT245_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT245_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT245_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT245_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT246_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT246_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT246_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT246_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT246_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT246_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT247_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT247_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT247_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT247_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT247_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT247_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT248_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT248_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT248_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT248_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT248_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT248_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT249_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT249_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT249_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT249_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT249_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT249_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT250_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT250_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT250_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT250_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT250_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT250_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT251_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT251_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT251_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT251_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT251_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT251_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT252_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT252_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT252_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT252_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT252_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT252_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT253_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT253_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT253_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT253_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT253_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT253_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT254_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT254_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT254_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT254_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT254_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT254_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT255_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT255_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT255_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT255_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT255_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT255_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT32_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT32_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT32_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT32_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT32_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT32_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT33_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT33_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT33_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT33_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT33_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT33_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT34_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT34_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT34_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT34_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT34_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT34_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT35_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT35_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT35_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT35_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT35_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT35_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT36_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT36_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT36_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT36_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT36_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT36_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT37_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT37_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT37_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT37_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT37_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT37_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT38_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT38_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT38_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT38_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT38_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT38_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT39_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT39_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT39_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT39_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT39_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT39_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT40_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT40_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT40_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT40_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT40_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT40_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT41_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT41_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT41_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT41_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT41_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT41_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT42_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT42_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT42_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT42_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT42_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT42_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT43_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT43_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT43_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT43_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT43_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT43_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT44_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT44_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT44_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT44_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT44_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT44_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT45_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT45_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT45_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT45_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT45_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT45_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT46_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT46_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT46_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT46_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT46_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT46_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT47_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT47_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT47_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT47_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT47_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT47_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT48_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT48_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT48_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT48_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT48_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT48_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT49_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT49_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT49_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT49_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT49_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT49_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT50_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT50_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT50_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT50_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT50_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT50_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT51_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT51_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT51_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT51_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT51_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT51_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT52_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT52_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT52_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT52_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT52_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT52_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT53_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT53_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT53_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT53_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT53_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT53_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT54_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT54_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT54_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT54_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT54_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT54_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT55_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT55_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT55_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT55_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT55_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT55_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT56_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT56_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT56_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT56_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT56_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT56_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT57_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT57_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT57_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT57_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT57_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT57_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT58_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT58_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT58_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT58_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT58_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT58_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT59_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT59_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT59_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT59_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT59_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT59_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT60_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT60_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT60_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT60_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT60_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT60_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT61_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT61_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT61_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT61_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT61_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT61_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT62_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT62_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT62_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT62_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT62_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT62_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT63_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT63_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT63_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT63_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT63_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT63_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT64_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT64_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT64_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT64_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT64_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT64_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT65_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT65_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT65_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT65_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT65_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT65_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT66_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT66_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT66_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT66_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT66_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT66_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT67_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT67_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT67_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT67_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT67_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT67_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT68_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT68_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT68_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT68_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT68_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT68_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT69_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT69_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT69_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT69_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT69_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT69_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT70_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT70_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT70_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT70_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT70_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT70_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT71_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT71_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT71_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT71_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT71_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT71_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT72_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT72_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT72_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT72_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT72_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT72_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT73_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT73_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT73_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT73_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT73_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT73_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT74_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT74_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT74_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT74_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT74_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT74_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT75_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT75_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT75_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT75_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT75_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT75_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT76_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT76_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT76_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT76_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT76_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT76_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT77_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT77_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT77_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT77_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT77_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT77_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT78_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT78_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT78_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT78_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT78_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT78_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT79_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT79_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT79_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT79_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT79_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT79_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT80_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT80_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT80_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT80_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT80_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT80_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT81_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT81_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT81_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT81_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT81_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT81_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT82_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT82_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT82_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT82_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT82_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT82_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT83_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT83_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT83_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT83_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT83_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT83_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT84_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT84_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT84_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT84_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT84_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT84_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT85_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT85_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT85_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT85_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT85_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT85_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT86_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT86_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT86_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT86_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT86_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT86_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT87_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT87_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT87_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT87_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT87_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT87_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT88_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT88_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT88_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT88_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT88_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT88_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT89_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT89_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT89_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT89_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT89_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT89_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT90_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT90_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT90_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT90_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT90_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT90_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT91_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT91_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT91_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT91_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT91_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT91_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT92_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT92_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT92_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT92_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT92_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT92_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT93_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT93_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT93_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT93_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT93_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT93_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT94_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT94_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT94_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT94_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT94_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT94_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT95_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT95_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT95_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT95_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT95_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT95_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT96_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT96_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT96_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT96_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT96_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT96_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT97_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT97_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT97_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT97_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT97_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT97_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT98_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT98_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT98_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT98_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT98_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT98_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT99_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT99_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT99_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT99_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT99_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT99_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK
- PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK
- PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT
- PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK
- PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK
- PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT
- PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK
- PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK
- PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT
- PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK
- PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK
- PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT
- PCIEMSR
- PCIENREG
- PCIEOFST_G
- PCIEOFST_M
- PCIEOFST_S
- PCIEOFST_SHIFT_X
- PCIEPALR
- PCIEPAMR
- PCIEPAUR
- PCIEPHY0_CFG
- PCIEPHYSR
- PCIEPINT_F
- PCIEPINT_S
- PCIEPINT_V
- PCIEPRAR
- PCIEPTCTLR
- PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK
- PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT
- PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK
- PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT
- PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK
- PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK
- PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK
- PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT
- PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK
- PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT
- PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK
- PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT
- PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK
- PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT
- PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK
- PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT
- PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK
- PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT
- PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK
- PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT
- PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK
- PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT
- PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK
- PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT
- PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK
- PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT
- PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK
- PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT
- PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK
- PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT
- PCIEP_HPGI__REG_HPGI_HOOK_MASK
- PCIEP_HPGI__REG_HPGI_HOOK__SHIFT
- PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK
- PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT
- PCIEP_HW_DEBUG__HW_00_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_00_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_01_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_01_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_02_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_02_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_03_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_03_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_04_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_04_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_05_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_05_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_06_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_06_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_07_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_07_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_08_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_08_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_09_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_09_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_10_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_10_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_11_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_11_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_12_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_12_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_13_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_13_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_14_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_14_DEBUG__SHIFT
- PCIEP_HW_DEBUG__HW_15_DEBUG_MASK
- PCIEP_HW_DEBUG__HW_15_DEBUG__SHIFT
- PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK
- PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT
- PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK
- PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT
- PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK
- PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT
- PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK
- PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT
- PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK
- PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT
- PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK
- PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT
- PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK
- PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT
- PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK
- PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT
- PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK
- PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT
- PCIEP_PORT_CNTL__PMI_BM_DIS_MASK
- PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT
- PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK
- PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT
- PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE_MASK
- PCIEP_PORT_CNTL__SEQNUM_DEBUG_MODE__SHIFT
- PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK
- PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT
- PCIEP_RESERVED__PCIEP_RESERVED_MASK
- PCIEP_RESERVED__PCIEP_RESERVED__MASK
- PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
- PCIEP_RESERVED__RESERVED_MASK
- PCIEP_RESERVED__RESERVED__SHIFT
- PCIEP_SCRATCH__PCIEP_SCRATCH_MASK
- PCIEP_SCRATCH__PCIEP_SCRATCH__MASK
- PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT
- PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK
- PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT
- PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK
- PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT
- PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK
- PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT
- PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK
- PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT
- PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK
- PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT
- PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK
- PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT
- PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK
- PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT
- PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK
- PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT
- PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK
- PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT
- PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK
- PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT
- PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK
- PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT
- PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK
- PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT
- PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK
- PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT
- PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK
- PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT
- PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK
- PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT
- PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK
- PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT
- PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK
- PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT
- PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK
- PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT
- PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK
- PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT
- PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK
- PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT
- PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
- PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
- PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
- PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
- PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
- PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
- PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK
- PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK
- PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT
- PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
- PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
- PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
- PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
- PCIERBAR
- PCIERRGENDIS
- PCIESINT_F
- PCIESINT_S
- PCIESINT_V
- PCIESLOTSR_OFS
- PCIESTAT
- PCIESTAT_EXTREFCLK
- PCIETCTLR
- PCIETSTR
- PCIEUART8997_FW_NAME_V4
- PCIEUSB8997_FW_NAME_V4
- PCIEXACCREG
- PCIE_0_AUX_CLK_SRC
- PCIE_0_GDSC
- PCIE_0_PIPE_CLK_SRC
- PCIE_1LANE_2LANE_SELECTION
- PCIE_1_ACLK_RESET
- PCIE_1_ALT_REF_CLK
- PCIE_1_ALT_REF_SRC
- PCIE_1_AUX_CLK
- PCIE_1_AUX_CLK_SRC
- PCIE_1_A_CLK
- PCIE_1_EXT_RESET
- PCIE_1_GDSC
- PCIE_1_HCLK_RESET
- PCIE_1_H_CLK
- PCIE_1_M_RESET
- PCIE_1_PCI_RESET
- PCIE_1_PHY_CLK
- PCIE_1_PHY_RESET
- PCIE_1_PIPE_CLK_SRC
- PCIE_1_POR_RESET
- PCIE_1_S_RESET
- PCIE_2_ACLK_RESET
- PCIE_2_ALT_REF_CLK
- PCIE_2_ALT_REF_SRC
- PCIE_2_AUX_CLK
- PCIE_2_A_CLK
- PCIE_2_EXT_RESET
- PCIE_2_HCLK_RESET
- PCIE_2_H_CLK
- PCIE_2_M_RESET
- PCIE_2_PCI_RESET
- PCIE_2_PHY_CLK
- PCIE_2_PHY_RESET
- PCIE_2_POR_RESET
- PCIE_2_S_RESET
- PCIE_9XX_BRIDGE_MSIX_ADDR_BASE
- PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT
- PCIE_9XX_BYTE_SWAP_IO_BASE
- PCIE_9XX_BYTE_SWAP_IO_LIM
- PCIE_9XX_BYTE_SWAP_MEM_BASE
- PCIE_9XX_BYTE_SWAP_MEM_LIM
- PCIE_9XX_INT_EN0
- PCIE_9XX_INT_EN1
- PCIE_9XX_INT_STATUS0
- PCIE_9XX_INT_STATUS1
- PCIE_9XX_MSIX_STATUS0
- PCIE_9XX_MSIX_STATUSX
- PCIE_9XX_MSIX_VEC
- PCIE_9XX_MSIX_VECX
- PCIE_9XX_MSI_EN
- PCIE_9XX_MSI_STATUS
- PCIE_ABSERR
- PCIE_ABSERR_SETTING
- PCIE_ACLK_RESET
- PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
- PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK
- PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
- PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
- PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK
- PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
- PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
- PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK
- PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
- PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
- PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK
- PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
- PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
- PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK
- PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
- PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
- PCIE_ACS_CAP__SOURCE_VALIDATION__MASK
- PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
- PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
- PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK
- PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
- PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
- PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK
- PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
- PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
- PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK
- PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
- PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
- PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK
- PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
- PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
- PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK
- PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
- PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
- PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK
- PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
- PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
- PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK
- PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
- PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
- PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK
- PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
- PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
- PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK
- PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
- PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK
- PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
- PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK
- PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK
- PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
- PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
- PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK
- PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_AHB_ARES
- PCIE_AHB_TRANS_BASE0_H
- PCIE_AHB_TRANS_BASE0_L
- PCIE_ALT_REF_CLK
- PCIE_ALT_REF_SRC
- PCIE_ANY_PORT
- PCIE_APB_PHY_CTRL0
- PCIE_APB_PHY_CTRL1
- PCIE_APB_PHY_STATUS0
- PCIE_APP0_CLK_REQ
- PCIE_APP_INIT_RESET
- PCIE_APP_LTSSM_EN
- PCIE_APP_LTSSM_ENABLE
- PCIE_APP_TLP_REQ
- PCIE_ARCACHE_TRC_REG
- PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
- PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK
- PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
- PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
- PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK
- PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
- PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
- PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK
- PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
- PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
- PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK
- PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
- PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
- PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK
- PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
- PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
- PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK
- PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
- PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_ARUSER_REG
- PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK
- PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK
- PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT
- PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK
- PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK
- PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT
- PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK
- PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK
- PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT
- PCIE_ATS_CNTL__ATC_ENABLE_MASK
- PCIE_ATS_CNTL__ATC_ENABLE__MASK
- PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
- PCIE_ATS_CNTL__STU_MASK
- PCIE_ATS_CNTL__STU__MASK
- PCIE_ATS_CNTL__STU__SHIFT
- PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_ATTR_ENTRY
- PCIE_ATU_BAR_MODE_ENABLE
- PCIE_ATU_BUS
- PCIE_ATU_CR1
- PCIE_ATU_CR2
- PCIE_ATU_DEV
- PCIE_ATU_ENABLE
- PCIE_ATU_FUNC
- PCIE_ATU_LIMIT
- PCIE_ATU_LOWER_BASE
- PCIE_ATU_LOWER_TARGET
- PCIE_ATU_REGION_INBOUND
- PCIE_ATU_REGION_INDEX0
- PCIE_ATU_REGION_INDEX1
- PCIE_ATU_REGION_INDEX2
- PCIE_ATU_REGION_OUTBOUND
- PCIE_ATU_TYPE_CFG0
- PCIE_ATU_TYPE_CFG1
- PCIE_ATU_TYPE_IO
- PCIE_ATU_TYPE_MEM
- PCIE_ATU_UNR_LIMIT
- PCIE_ATU_UNR_LOWER_BASE
- PCIE_ATU_UNR_LOWER_TARGET
- PCIE_ATU_UNR_REGION_CTRL1
- PCIE_ATU_UNR_REGION_CTRL2
- PCIE_ATU_UNR_UPPER_BASE
- PCIE_ATU_UNR_UPPER_TARGET
- PCIE_ATU_UPPER_BASE
- PCIE_ATU_UPPER_TARGET
- PCIE_ATU_VIEWPORT
- PCIE_AUX_CLK
- PCIE_AUX_CLK_SRC
- PCIE_AUX_MAX_OFFSET
- PCIE_AUX_RESET
- PCIE_AUX_SECTION
- PCIE_AWCACHE_TRC_REG
- PCIE_AWUSER_REG
- PCIE_AXI_M_ARES
- PCIE_AXI_M_STICKY_ARES
- PCIE_AXI_M_VMIDMT_ARES
- PCIE_AXI_S_ARES
- PCIE_AXI_S_XPU_ARES
- PCIE_AXI_WINDOW0
- PCIE_A_CLK
- PCIE_A_RESET
- PCIE_B0_B1_TSYNCEN
- PCIE_B1C0_MODE_SEL
- PCIE_BAR0_SETUP
- PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR1_CNTL__BAR_INDEX_MASK
- PCIE_BAR1_CNTL__BAR_INDEX__MASK
- PCIE_BAR1_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR1_CNTL__BAR_SIZE_MASK
- PCIE_BAR1_CNTL__BAR_SIZE__MASK
- PCIE_BAR1_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR2_CNTL__BAR_INDEX_MASK
- PCIE_BAR2_CNTL__BAR_INDEX__MASK
- PCIE_BAR2_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR2_CNTL__BAR_SIZE_MASK
- PCIE_BAR2_CNTL__BAR_SIZE__MASK
- PCIE_BAR2_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR3_CNTL__BAR_INDEX_MASK
- PCIE_BAR3_CNTL__BAR_INDEX__MASK
- PCIE_BAR3_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR3_CNTL__BAR_SIZE_MASK
- PCIE_BAR3_CNTL__BAR_SIZE__MASK
- PCIE_BAR3_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR4_CNTL__BAR_INDEX_MASK
- PCIE_BAR4_CNTL__BAR_INDEX__MASK
- PCIE_BAR4_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR4_CNTL__BAR_SIZE_MASK
- PCIE_BAR4_CNTL__BAR_SIZE__MASK
- PCIE_BAR4_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR5_CNTL__BAR_INDEX_MASK
- PCIE_BAR5_CNTL__BAR_INDEX__MASK
- PCIE_BAR5_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR5_CNTL__BAR_SIZE_MASK
- PCIE_BAR5_CNTL__BAR_SIZE__MASK
- PCIE_BAR5_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK
- PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK
- PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT
- PCIE_BAR6_CNTL__BAR_INDEX_MASK
- PCIE_BAR6_CNTL__BAR_INDEX__MASK
- PCIE_BAR6_CNTL__BAR_INDEX__SHIFT
- PCIE_BAR6_CNTL__BAR_SIZE_MASK
- PCIE_BAR6_CNTL__BAR_SIZE__MASK
- PCIE_BAR6_CNTL__BAR_SIZE__SHIFT
- PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK
- PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK
- PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT
- PCIE_BAR_CTRL_OFF
- PCIE_BAR_ENABLE
- PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_BAR_HI_OFF
- PCIE_BAR_LO_OFF
- PCIE_BAR_MAP_MAX
- PCIE_BAR_REG_ADDRESS
- PCIE_BASE
- PCIE_BASE_ADDR0
- PCIE_BASE_ADDR1
- PCIE_BDA_NAMELEN
- PCIE_BMON_MSTR_RD_MAX_OFFSET
- PCIE_BMON_MSTR_RD_SECTION
- PCIE_BMON_MSTR_WR_MAX_OFFSET
- PCIE_BMON_MSTR_WR_SECTION
- PCIE_BMON_SLV_RD_MAX_OFFSET
- PCIE_BMON_SLV_RD_SECTION
- PCIE_BMON_SLV_WR_MAX_OFFSET
- PCIE_BMON_SLV_WR_SECTION
- PCIE_BRIDGE
- PCIE_BRIDGE_BAR0_BASEMASK_REG
- PCIE_BRIDGE_BAR0_REBASE_ADDR_REG
- PCIE_BRIDGE_BAR1_BASEMASK_REG
- PCIE_BRIDGE_BAR1_REBASE_ADDR_REG
- PCIE_BRIDGE_CMD
- PCIE_BRIDGE_MSIX_ADDR_BASE
- PCIE_BRIDGE_MSIX_ADDR_LIMIT
- PCIE_BRIDGE_MSI_ADDRH
- PCIE_BRIDGE_MSI_ADDRL
- PCIE_BRIDGE_MSI_CAP
- PCIE_BRIDGE_MSI_DATA
- PCIE_BRIDGE_OPT1_REG
- PCIE_BRIDGE_OPT2_REG
- PCIE_BRIDGE_RC_INT_MASK_REG
- PCIE_BUS_BRIDGE
- PCIE_BUS_CLK
- PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- PCIE_BUS_CNTL__PMI_INT_DIS_MASK
- PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT
- PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK
- PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT
- PCIE_BUS_DEFAULT
- PCIE_BUS_DEVICE
- PCIE_BUS_PEER2PEER
- PCIE_BUS_PERFORMANCE
- PCIE_BUS_SAFE
- PCIE_BUS_TUNE_OFF
- PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK
- PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT
- PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK
- PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT
- PCIE_BYTE_SWAP_IO_BASE
- PCIE_BYTE_SWAP_IO_LIM
- PCIE_BYTE_SWAP_MEM_BASE
- PCIE_BYTE_SWAP_MEM_LIM
- PCIE_CAP_CPL_TIMEOUT_DISABLE
- PCIE_CAP_LINK1_VAL
- PCIE_CAP_LIST__CAP_ID_MASK
- PCIE_CAP_LIST__CAP_ID__MASK
- PCIE_CAP_LIST__CAP_ID__SHIFT
- PCIE_CAP_LIST__NEXT_PTR_MASK
- PCIE_CAP_LIST__NEXT_PTR__MASK
- PCIE_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_CAP_MAX_PAYLOAD_MASK
- PCIE_CAP_MAX_PAYLOAD_SIZE
- PCIE_CAP_MAX_READ_REQ_MASK
- PCIE_CAP_MAX_READ_REQ_SIZE
- PCIE_CAP_OFFSET
- PCIE_CAP_PCIEXP
- PCIE_CAP__DEVICE_TYPE_MASK
- PCIE_CAP__DEVICE_TYPE__MASK
- PCIE_CAP__DEVICE_TYPE__SHIFT
- PCIE_CAP__INT_MESSAGE_NUM_MASK
- PCIE_CAP__INT_MESSAGE_NUM__MASK
- PCIE_CAP__INT_MESSAGE_NUM__SHIFT
- PCIE_CAP__SLOT_IMPLEMENTED_MASK
- PCIE_CAP__SLOT_IMPLEMENTED__MASK
- PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
- PCIE_CAP__VERSION_MASK
- PCIE_CAP__VERSION__MASK
- PCIE_CAP__VERSION__SHIFT
- PCIE_CC_REV_ID_0_EP1_REG
- PCIE_CC_REV_ID_0_EP2_REG
- PCIE_CC_REV_ID_0_EP3_REG
- PCIE_CC_REV_ID_0_EP4_REG
- PCIE_CC_REV_ID_1_EP1_REG
- PCIE_CC_REV_ID_1_EP2_REG
- PCIE_CC_REV_ID_1_EP3_REG
- PCIE_CC_REV_ID_1_EP4_REG
- PCIE_CC_REV_ID_2_EP1_REG
- PCIE_CC_REV_ID_2_EP2_REG
- PCIE_CC_REV_ID_2_EP3_REG
- PCIE_CC_REV_ID_2_EP4_REG
- PCIE_CC_REV_ID_3_EP1_REG
- PCIE_CC_REV_ID_3_EP2_REG
- PCIE_CC_REV_ID_3_EP3_REG
- PCIE_CC_REV_ID_3_EP4_REG
- PCIE_CC_REV_ID_4_EP1_REG
- PCIE_CC_REV_ID_4_EP2_REG
- PCIE_CC_REV_ID_4_EP3_REG
- PCIE_CC_REV_ID_4_EP4_REG
- PCIE_CC_REV_ID_5_EP1_REG
- PCIE_CC_REV_ID_5_EP2_REG
- PCIE_CC_REV_ID_5_EP3_REG
- PCIE_CC_REV_ID_5_EP4_REG
- PCIE_CC_REV_ID_6_EP1_REG
- PCIE_CC_REV_ID_6_EP2_REG
- PCIE_CC_REV_ID_6_EP3_REG
- PCIE_CC_REV_ID_6_EP4_REG
- PCIE_CC_REV_ID_7_EP1_REG
- PCIE_CC_REV_ID_7_EP2_REG
- PCIE_CC_REV_ID_7_EP3_REG
- PCIE_CC_REV_ID_7_EP4_REG
- PCIE_CFG0
- PCIE_CFG1_EVENT_CLK_D3_SET
- PCIE_CFG_ADDR
- PCIE_CFG_AUX_CLK_EN
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- PCIE_CFG_CORE_CLK_EN
- PCIE_CFG_DATA
- PCIE_CFG_DEVICE_PRESENT
- PCIE_CFG_HEADER0
- PCIE_CFG_HEADER1
- PCIE_CFG_HEADER2
- PCIE_CFG_OFFSET
- PCIE_CFG_POWERUP_RESET
- PCIE_CFG_RDATA
- PCIE_CFG_REG_PL100
- PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK
- PCIE_CFG_REG_PL101
- PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT
- PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT
- PCIE_CFG_REG_PL102
- PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT
- PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT
- PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT
- PCIE_CFG_REG_PL103
- PCIE_CFG_REG_PL105
- PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK
- PCIE_CFG_REG_PL106
- PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK
- PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK
- PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT
- PCIE_CFG_REG_PL2
- PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT
- PCIE_CFG_REG_PL3
- PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT
- PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK
- PCIE_CFG_SPACE_DATA_A
- PCIE_CFG_SPACE_REQ_A
- PCIE_CFG_SPCIE1
- PCIE_CFG_SPCIE2
- PCIE_CFG_STATUS12
- PCIE_CFG_STATUS17
- PCIE_CFG_TPH2
- PCIE_CFG_VAL
- PCIE_CFG_WDATA
- PCIE_CHANNEL
- PCIE_CHICKEN3
- PCIE_CI_CNTL__CI_MSTSPLIT_DIS_MASK
- PCIE_CI_CNTL__CI_MSTSPLIT_DIS__SHIFT
- PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS_MASK
- PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS__SHIFT
- PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH_MASK
- PCIE_CI_CNTL__CI_MST_ATOMIC_ADDR_HASH__SHIFT
- PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK
- PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT
- PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST_MASK
- PCIE_CI_CNTL__CI_MST_IGNORE_PAGE_ALIGNED_REQUEST__SHIFT
- PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS_MASK
- PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS__SHIFT
- PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK
- PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT
- PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK
- PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT
- PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK
- PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK
- PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT
- PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK
- PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT
- PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK
- PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT
- PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK
- PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT
- PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK
- PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT
- PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK
- PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT
- PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK
- PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT
- PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK
- PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT
- PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK
- PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT
- PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK
- PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT
- PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK
- PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT
- PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK
- PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT
- PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE_MASK
- PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE__SHIFT
- PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK
- PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT
- PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK
- PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT
- PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK
- PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT
- PCIE_CLASS
- PCIE_CLASS_CODE
- PCIE_CLIENT_ARI_ENABLE
- PCIE_CLIENT_BASE
- PCIE_CLIENT_BASIC_STATUS1
- PCIE_CLIENT_CONFIG
- PCIE_CLIENT_CONF_DISABLE
- PCIE_CLIENT_CONF_ENABLE
- PCIE_CLIENT_CONF_LANE_NUM
- PCIE_CLIENT_DEBUG_LTSSM_L1
- PCIE_CLIENT_DEBUG_LTSSM_L2
- PCIE_CLIENT_DEBUG_LTSSM_MASK
- PCIE_CLIENT_DEBUG_OUT_0
- PCIE_CLIENT_GEN_SEL_1
- PCIE_CLIENT_GEN_SEL_2
- PCIE_CLIENT_INTR_MASK
- PCIE_CLIENT_INTR_SHIFT
- PCIE_CLIENT_INT_CLI
- PCIE_CLIENT_INT_CORR_ERR
- PCIE_CLIENT_INT_DPA
- PCIE_CLIENT_INT_FATAL_ERR
- PCIE_CLIENT_INT_HOT_PLUG
- PCIE_CLIENT_INT_HOT_RST
- PCIE_CLIENT_INT_INTA
- PCIE_CLIENT_INT_INTB
- PCIE_CLIENT_INT_INTC
- PCIE_CLIENT_INT_INTD
- PCIE_CLIENT_INT_LEGACY
- PCIE_CLIENT_INT_LEGACY_DONE
- PCIE_CLIENT_INT_LOCAL
- PCIE_CLIENT_INT_MASK
- PCIE_CLIENT_INT_MSG
- PCIE_CLIENT_INT_NFATAL_ERR
- PCIE_CLIENT_INT_PHY
- PCIE_CLIENT_INT_PWR_STCG
- PCIE_CLIENT_INT_STATUS
- PCIE_CLIENT_INT_UDMA
- PCIE_CLIENT_LINK_STATUS_MASK
- PCIE_CLIENT_LINK_STATUS_UP
- PCIE_CLIENT_LINK_TRAIN_ENABLE
- PCIE_CLIENT_MODE_EP
- PCIE_CLIENT_MODE_RC
- PCIE_CLK_GEN1_DIS
- PCIE_CLK_GEN1_EN
- PCIE_CLK_GEN_DIS
- PCIE_CLK_GEN_EN
- PCIE_CMD_OFF
- PCIE_CNTL2
- PCIE_CNTL2__MST_MEM_DS_EN_MASK
- PCIE_CNTL2__MST_MEM_DS_EN__SHIFT
- PCIE_CNTL2__MST_MEM_LS_EN_MASK
- PCIE_CNTL2__MST_MEM_LS_EN__SHIFT
- PCIE_CNTL2__MST_MEM_SD_EN_MASK
- PCIE_CNTL2__MST_MEM_SD_EN__SHIFT
- PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK
- PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT
- PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
- PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT
- PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK
- PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT
- PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK
- PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT
- PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK
- PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT
- PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK
- PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT
- PCIE_CNTL2__SLV_MEM_DS_EN_MASK
- PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT
- PCIE_CNTL2__SLV_MEM_LS_EN_MASK
- PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT
- PCIE_CNTL2__SLV_MEM_SD_EN_MASK
- PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT
- PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK
- PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT
- PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK
- PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT
- PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK
- PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT
- PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK
- PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT
- PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK
- PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT
- PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK
- PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT
- PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK
- PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT
- PCIE_CNTL__HWINIT_WR_LOCK_MASK
- PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK
- PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT
- PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK
- PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT
- PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK
- PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT
- PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK
- PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT
- PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK
- PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT
- PCIE_CNTL__RX_RCB_CHANNEL_ORDERING_MASK
- PCIE_CNTL__RX_RCB_CHANNEL_ORDERING__SHIFT
- PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK
- PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT
- PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK
- PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT
- PCIE_CNTL__RX_RCB_REORDER_EN_MASK
- PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT
- PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK
- PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT
- PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK
- PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT
- PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK
- PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT
- PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK
- PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT
- PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK
- PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT
- PCIE_CNTL__TX_CPL_DEBUG_MASK
- PCIE_CNTL__TX_CPL_DEBUG__SHIFT
- PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- PCIE_COMMON_CLOCK_CONFIG_0_4_0
- PCIE_CONFIG2_REG
- PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE_MASK
- PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE__SHIFT
- PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK
- PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT
- PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK
- PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT
- PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK
- PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT
- PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK
- PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT
- PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK
- PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT
- PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK
- PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT
- PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK
- PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT
- PCIE_CONFIG_EXT_DEVICE_CONTROL_OFFSET
- PCIE_CONFIG_FLAG_ENABLE_L1
- PCIE_CONFIG_RD_TYPE0
- PCIE_CONFIG_RD_TYPE1
- PCIE_CONFIG_WR_TYPE0
- PCIE_CONFIG_WR_TYPE1
- PCIE_CONF_ADDR
- PCIE_CONF_ADDR_EN
- PCIE_CONF_ADDR_OFF
- PCIE_CONF_BUS
- PCIE_CONF_CLASS_ID
- PCIE_CONF_DATA_OFF
- PCIE_CONF_DEV
- PCIE_CONF_DEVICE_ID
- PCIE_CONF_FUN
- PCIE_CONF_FUNC
- PCIE_CONF_REG
- PCIE_CONF_VEND_ID
- PCIE_CORE_AXI_CONF_BASE
- PCIE_CORE_AXI_INBOUND_BASE
- PCIE_CORE_CMD_IO_ACCESS_EN
- PCIE_CORE_CMD_MEM_ACCESS_EN
- PCIE_CORE_CMD_MEM_IO_REQ_EN
- PCIE_CORE_CMD_STATUS_REG
- PCIE_CORE_CONFIG_VENDOR
- PCIE_CORE_CTRL
- PCIE_CORE_CTRL0_REG
- PCIE_CORE_CTRL1_REG
- PCIE_CORE_CTRL2_MSI_ENABLE
- PCIE_CORE_CTRL2_OB_WIN_ENABLE
- PCIE_CORE_CTRL2_REG
- PCIE_CORE_CTRL2_RESERVED
- PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE
- PCIE_CORE_CTRL2_TD_ENABLE
- PCIE_CORE_CTRL_MGMT_BASE
- PCIE_CORE_CTRL_PLC1
- PCIE_CORE_CTRL_PLC1_FTS_CNT
- PCIE_CORE_CTRL_PLC1_FTS_MASK
- PCIE_CORE_CTRL_PLC1_FTS_SHIFT
- PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ
- PCIE_CORE_DEV_CTRL_STATS_REG
- PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE
- PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE
- PCIE_CORE_DEV_ID_REG
- PCIE_CORE_DEV_REV_REG
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV
- PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX
- PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN
- PCIE_CORE_ERR_CAPCTL_REG
- PCIE_CORE_IB_REGION_ADDR0_LO_ADDR
- PCIE_CORE_IB_REGION_ADDR0_NUM_BITS
- PCIE_CORE_INT
- PCIE_CORE_INT_A_ASSERT_ENABLE
- PCIE_CORE_INT_B_ASSERT_ENABLE
- PCIE_CORE_INT_CRFO
- PCIE_CORE_INT_CRFPE
- PCIE_CORE_INT_CT
- PCIE_CORE_INT_C_ASSERT_ENABLE
- PCIE_CORE_INT_D_ASSERT_ENABLE
- PCIE_CORE_INT_FCE
- PCIE_CORE_INT_MASK
- PCIE_CORE_INT_MMVC
- PCIE_CORE_INT_MTR
- PCIE_CORE_INT_PE
- PCIE_CORE_INT_PRFO
- PCIE_CORE_INT_PRFPE
- PCIE_CORE_INT_RRPE
- PCIE_CORE_INT_RT
- PCIE_CORE_INT_RTR
- PCIE_CORE_INT_STATUS
- PCIE_CORE_INT_UCR
- PCIE_CORE_INT_UTC
- PCIE_CORE_LANE_MAP
- PCIE_CORE_LANE_MAP_MASK
- PCIE_CORE_LANE_MAP_REVERSE
- PCIE_CORE_LINK_CTRL_STAT_REG
- PCIE_CORE_LINK_L0S_ENTRY
- PCIE_CORE_LINK_TRAINING
- PCIE_CORE_LINK_WIDTH_SHIFT
- PCIE_CORE_MAX_OFFSET
- PCIE_CORE_MODE_COMMAND
- PCIE_CORE_MODE_DIRECT
- PCIE_CORE_OB_REGION_ADDR0
- PCIE_CORE_OB_REGION_ADDR0_LO_ADDR
- PCIE_CORE_OB_REGION_ADDR0_NUM_BITS
- PCIE_CORE_OB_REGION_ADDR1
- PCIE_CORE_OB_REGION_DESC0
- PCIE_CORE_OB_REGION_DESC1
- PCIE_CORE_PCIEXP_CAP
- PCIE_CORE_PHY_FUNC_CFG
- PCIE_CORE_PL_CONF_LANE_MASK
- PCIE_CORE_PL_CONF_LANE_SHIFT
- PCIE_CORE_PL_CONF_SPEED_5G
- PCIE_CORE_PL_CONF_SPEED_MASK
- PCIE_CORE_RESET
- PCIE_CORE_RESET_ENABLE
- PCIE_CORE_SECTION
- PCIE_CORE_TXCREDIT_CFG1
- PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE
- PCIE_CORE_TXCREDIT_CFG1_MUI_MASK
- PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT
- PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
- PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
- PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
- PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK
- PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
- PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
- PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK
- PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
- PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
- PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK
- PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
- PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
- PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK
- PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
- PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
- PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK
- PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
- PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
- PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK
- PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
- PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
- PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK
- PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
- PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
- PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK
- PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
- PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
- PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK
- PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
- PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK
- PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
- PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK
- PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
- PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK
- PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
- PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK
- PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
- PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK
- PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
- PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK
- PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
- PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
- PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK
- PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
- PCIE_CPU_INT_EVENT
- PCIE_CPU_INT_STATUS
- PCIE_CRB_WINDOW_REG
- PCIE_CRSTB
- PCIE_CSR_ASPM_L1_EN
- PCIE_CSR_LTSSM_EN
- PCIE_CTI_0_MAX_OFFSET
- PCIE_CTI_0_SECTION
- PCIE_CTI_1_MAX_OFFSET
- PCIE_CTI_1_SECTION
- PCIE_CTRL_MASK
- PCIE_CTRL_OFF
- PCIE_CTRL_X1_MODE
- PCIE_DATA
- PCIE_DATA2__PCIE_DATA2_MASK
- PCIE_DATA2__PCIE_DATA2__MASK
- PCIE_DATA2__PCIE_DATA2__SHIFT
- PCIE_DATA_2__PCIE_DATA_MASK
- PCIE_DATA_2__PCIE_DATA__SHIFT
- PCIE_DATA__PCIE_DATA_MASK
- PCIE_DATA__PCIE_DATA__MASK
- PCIE_DATA__PCIE_DATA__SHIFT
- PCIE_DBI2_OFFSET
- PCIE_DBI_MAX_OFFSET
- PCIE_DBI_RO_WR_EN
- PCIE_DBI_SECTION
- PCIE_DB_CFG_MAX_OFFSET
- PCIE_DB_CFG_SECTION
- PCIE_DB_CMD_MAX_OFFSET
- PCIE_DB_CMD_SECTION
- PCIE_DB_RSV_MAX_OFFSET
- PCIE_DB_RSV_SECTION
- PCIE_DCR
- PCIE_DEBOUNCE_PARAM
- PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK
- PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT
- PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK
- PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT
- PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK
- PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT
- PCIE_DEBUG_CTRL
- PCIE_DEBUG_SOFT_RESET
- PCIE_DESC_RX_CSUM_ALL
- PCIE_DESC_RX_CSUM_OK_SHIFT
- PCIE_DESC_RX_DD
- PCIE_DESC_RX_DECRYPTED
- PCIE_DESC_RX_EOP
- PCIE_DESC_RX_IP4_CSUM
- PCIE_DESC_RX_IP4_CSUM_OK
- PCIE_DESC_RX_I_IP4_CSUM
- PCIE_DESC_RX_I_IP4_CSUM_OK
- PCIE_DESC_RX_I_TCP_CSUM
- PCIE_DESC_RX_I_TCP_CSUM_OK
- PCIE_DESC_RX_I_UDP_CSUM
- PCIE_DESC_RX_I_UDP_CSUM_OK
- PCIE_DESC_RX_META_LEN_MASK
- PCIE_DESC_RX_RSS
- PCIE_DESC_RX_TCP_CSUM
- PCIE_DESC_RX_TCP_CSUM_OK
- PCIE_DESC_RX_UDP_CSUM
- PCIE_DESC_RX_UDP_CSUM_OK
- PCIE_DESC_RX_VLAN
- PCIE_DESC_TX_CSUM
- PCIE_DESC_TX_ENCAP
- PCIE_DESC_TX_EOP
- PCIE_DESC_TX_IP4_CSUM
- PCIE_DESC_TX_LSO
- PCIE_DESC_TX_MSS_MASK
- PCIE_DESC_TX_OFFSET_MASK
- PCIE_DESC_TX_O_IP4_CSUM
- PCIE_DESC_TX_TCP_CSUM
- PCIE_DESC_TX_UDP_CSUM
- PCIE_DESC_TX_VLAN
- PCIE_DEVICEID_SHIFT
- PCIE_DEVICE_CONTROL2
- PCIE_DEVICE_CONTROL2_16ms
- PCIE_DEVICE_ID_MARVELL_88W8766P
- PCIE_DEVICE_ID_MARVELL_88W8897
- PCIE_DEVICE_ID_MARVELL_88W8997
- PCIE_DEVICE_ID_NEO_2_OX_IBM
- PCIE_DEVICE_ID_NEO_4
- PCIE_DEVICE_ID_NEO_4RJ45
- PCIE_DEVICE_ID_NEO_4_IBM
- PCIE_DEVICE_ID_NEO_8
- PCIE_DEVICE_ID_NEO_8RJ45
- PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1
- PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1
- PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2
- PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1
- PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT
- PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280
- PCIE_DEVICE_ID_PF_DSC_1_X
- PCIE_DEVICE_ID_PF_INT_5_X
- PCIE_DEVICE_ID_PF_INT_6_X
- PCIE_DEVICE_ID_QSR
- PCIE_DEVICE_ID_VF_DSC_1_X
- PCIE_DEVICE_ID_VF_INT_5_X
- PCIE_DEVICE_ID_VF_INT_6_X
- PCIE_DEVICE_ID_WCH_CH382_2S
- PCIE_DEVICE_ID_WCH_CH382_2S1P
- PCIE_DEVICE_ID_WCH_CH384_4S
- PCIE_DEVICE_NEO_IBM_PCI_NAME
- PCIE_DEVICE_OFFSET
- PCIE_DEVICE_TYPE_MASK
- PCIE_DEVICE_TYPE_RC
- PCIE_DEVICE_TYPE_SHIFT
- PCIE_DEV_CTRL_DEV_STUS
- PCIE_DEV_ID_0_EP1_REG
- PCIE_DEV_ID_0_EP2_REG
- PCIE_DEV_ID_0_EP3_REG
- PCIE_DEV_ID_0_EP4_REG
- PCIE_DEV_ID_1_EP1_REG
- PCIE_DEV_ID_1_EP2_REG
- PCIE_DEV_ID_1_EP3_REG
- PCIE_DEV_ID_1_EP4_REG
- PCIE_DEV_ID_2_EP1_REG
- PCIE_DEV_ID_2_EP2_REG
- PCIE_DEV_ID_2_EP3_REG
- PCIE_DEV_ID_2_EP4_REG
- PCIE_DEV_ID_3_EP1_REG
- PCIE_DEV_ID_3_EP2_REG
- PCIE_DEV_ID_3_EP3_REG
- PCIE_DEV_ID_3_EP4_REG
- PCIE_DEV_ID_4_EP1_REG
- PCIE_DEV_ID_4_EP2_REG
- PCIE_DEV_ID_4_EP3_REG
- PCIE_DEV_ID_4_EP4_REG
- PCIE_DEV_ID_5_EP1_REG
- PCIE_DEV_ID_5_EP2_REG
- PCIE_DEV_ID_5_EP3_REG
- PCIE_DEV_ID_5_EP4_REG
- PCIE_DEV_ID_6_EP1_REG
- PCIE_DEV_ID_6_EP2_REG
- PCIE_DEV_ID_6_EP3_REG
- PCIE_DEV_ID_6_EP4_REG
- PCIE_DEV_ID_7_EP1_REG
- PCIE_DEV_ID_7_EP2_REG
- PCIE_DEV_ID_7_EP3_REG
- PCIE_DEV_ID_7_EP4_REG
- PCIE_DEV_ID_OFF
- PCIE_DEV_MISC_CTRL_EXT_PIPE
- PCIE_DEV_MISC_CTRL_RETRY_BUFDIS
- PCIE_DEV_MISC_CTRL_SERDES_ENDIAN
- PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN
- PCIE_DEV_MISC_CTRL_SPIROM_EXIST
- PCIE_DEV_MISC_EXT_PIPE
- PCIE_DEV_MISC_RETRY_BUFDIS
- PCIE_DEV_MISC_SERDES_ENDIAN
- PCIE_DEV_MISC_SERDES_SEL_DIN
- PCIE_DEV_MISC_SPIROM_EXIST
- PCIE_DEV_REV_OFF
- PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
- PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK
- PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
- PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
- PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK
- PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_DLL_TX_CTRL1_DEF
- PCIE_DLL_TX_CTRL1_SEL_NOR_CLK
- PCIE_DLSTATUS_REG
- PCIE_DL_ACTIVE
- PCIE_DL_ACTIVE_SHIFT
- PCIE_DMA_OFFSET_ERROR
- PCIE_DMA_OFFSET_ERROR_MASK
- PCIE_DMA_RD_DONE_IMWR_ADDR_HIGH
- PCIE_DMA_RD_DONE_IMWR_ADDR_LOW
- PCIE_DMA_RD_ERR_STATUS_HIGH
- PCIE_DMA_RD_ERR_STATUS_LOW
- PCIE_DMA_RD_INTR_CLR
- PCIE_DMA_RD_INTR_MASK
- PCIE_DMA_RD_INTR_STATUS
- PCIE_DMA_WR_DONE_IMWR_ADDR_HIGH
- PCIE_DMA_WR_DONE_IMWR_ADDR_LOW
- PCIE_DMA_WR_ERR_STATUS
- PCIE_DMA_WR_INTR_CLR
- PCIE_DMA_WR_INTR_MASK
- PCIE_DMA_WR_INTR_STATUS
- PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK
- PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK
- PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- PCIE_DPA_CAP__SUBSTATE_MAX_MASK
- PCIE_DPA_CAP__SUBSTATE_MAX__MASK
- PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT
- PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK
- PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK
- PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK
- PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK
- PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK
- PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK
- PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK
- PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK
- PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT
- PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK
- PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK
- PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK
- PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT
- PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK
- PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK
- PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK
- PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_ECAM_ADDR
- PCIE_ECAM_BUS
- PCIE_ECAM_DEV
- PCIE_ECAM_DEVFN
- PCIE_ECAM_FUNC
- PCIE_ECAM_REG
- PCIE_EFUSE2__SPARE_31_1_EFUSE2_MASK
- PCIE_EFUSE2__SPARE_31_1_EFUSE2__SHIFT
- PCIE_EFUSE3__SPARE_14_PCIEFUSE3_MASK
- PCIE_EFUSE3__SPARE_14_PCIEFUSE3__SHIFT
- PCIE_EFUSE3__STRAP_BIF_KILL_GEN3_MASK
- PCIE_EFUSE3__STRAP_BIF_KILL_GEN3__SHIFT
- PCIE_EFUSE3__STRAP_CEC_ID_MASK
- PCIE_EFUSE3__STRAP_CEC_ID__SHIFT
- PCIE_EFUSE4__CC_WRITE_DISABLE_MASK
- PCIE_EFUSE4__CC_WRITE_DISABLE__SHIFT
- PCIE_EFUSE4__SPARE_3_PCIEFUSE4_MASK
- PCIE_EFUSE4__SPARE_3_PCIEFUSE4__SHIFT
- PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK
- PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT
- PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID_MASK
- PCIE_EFUSE4__STRAP_BIF_F0_DEVICE_ID__SHIFT
- PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID_MASK
- PCIE_EFUSE4__STRAP_BIF_F0_MAJOR_REV_ID__SHIFT
- PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID_MASK
- PCIE_EFUSE4__STRAP_BIF_F0_MINOR_REV_ID__SHIFT
- PCIE_EFUSE5__SPARE_16_PCIEFUSE5_MASK
- PCIE_EFUSE5__SPARE_16_PCIEFUSE5__SHIFT
- PCIE_EFUSE5__STRAP_AZALIA_DID_MASK
- PCIE_EFUSE5__STRAP_AZALIA_DID__SHIFT
- PCIE_EFUSE6__SPARE_15_PCIEFUSE6_MASK
- PCIE_EFUSE6__SPARE_15_PCIEFUSE6__SHIFT
- PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES_MASK
- PCIE_EFUSE6__STRAP_BIF_F0_SUPPORTED_PAGE_SIZES__SHIFT
- PCIE_EFUSE7__SPARE_15_PCIEFUSE7_MASK
- PCIE_EFUSE7__SPARE_15_PCIEFUSE7__SHIFT
- PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID_MASK
- PCIE_EFUSE7__STRAP_BIF_F0_SRIOV_VF_DEVICE_ID__SHIFT
- PCIE_EFUSE__CHIP_BIF_MODE_MASK
- PCIE_EFUSE__CHIP_BIF_MODE__SHIFT
- PCIE_EFUSE__ISTRAP_ARBEN0_MASK
- PCIE_EFUSE__ISTRAP_ARBEN0__SHIFT
- PCIE_EFUSE__PCIE_EFUSE_VALID_MASK
- PCIE_EFUSE__PCIE_EFUSE_VALID__SHIFT
- PCIE_EFUSE__PPHY_EFUSE_VALID_MASK
- PCIE_EFUSE__PPHY_EFUSE_VALID__SHIFT
- PCIE_EFUSE__SPARE_26_7_EFUSE0_MASK
- PCIE_EFUSE__SPARE_26_7_EFUSE0__SHIFT
- PCIE_EFUSE__SPARE_31_28_EFUSE0_MASK
- PCIE_EFUSE__SPARE_31_28_EFUSE0__SHIFT
- PCIE_EFUSE__SPARE_5_3_EFUSE0_MASK
- PCIE_EFUSE__SPARE_5_3_EFUSE0__SHIFT
- PCIE_ELBI_LTSSM_ENABLE
- PCIE_ELBI_RDLH_LINKUP
- PCIE_ELBI_SLV_ARMISC
- PCIE_ELBI_SLV_AWMISC
- PCIE_ELBI_SLV_DBI_ENABLE
- PCIE_EP1_FUNC3_0_INTR_REG
- PCIE_EP1_FUNC7_4_INTR_REG
- PCIE_EP1_FUNC_F_REG
- PCIE_EP1_FUNC_TC_REG
- PCIE_EP2_FUNC3_0_INTR_REG
- PCIE_EP2_FUNC7_4_INTR_REG
- PCIE_EP2_FUNC_F_REG
- PCIE_EP2_FUNC_TC_REG
- PCIE_EP3_FUNC3_0_INTR_REG
- PCIE_EP3_FUNC7_4_INTR_REG
- PCIE_EP3_FUNC_F_REG
- PCIE_EP3_FUNC_TC_REG
- PCIE_EP4_FUNC3_0_INTR_REG
- PCIE_EP4_FUNC7_4_INTR_REG
- PCIE_EP4_FUNC_F_REG
- PCIE_EP4_FUNC_TC_REG
- PCIE_EP_DEBUG_REG_BASE
- PCIE_EP_IRQ_CLR
- PCIE_EP_IRQ_SET
- PCIE_ERROR_INTERRUPT
- PCIE_ERROR_INTERRUPT_ENABLE
- PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK
- PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
- PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
- PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
- PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
- PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
- PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
- PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK
- PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
- PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
- PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
- PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
- PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
- PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
- PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK
- PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
- PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
- PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
- PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
- PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
- PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
- PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK
- PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT
- PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK
- PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT
- PCIE_ESM_CAP_1__ESM_10P0G_MASK
- PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P1G_MASK
- PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P2G_MASK
- PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P3G_MASK
- PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P4G_MASK
- PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P5G_MASK
- PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P6G_MASK
- PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P7G_MASK
- PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P8G_MASK
- PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
- PCIE_ESM_CAP_1__ESM_10P9G_MASK
- PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P0G_MASK
- PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P1G_MASK
- PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P2G_MASK
- PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P3G_MASK
- PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P4G_MASK
- PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P5G_MASK
- PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P6G_MASK
- PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P7G_MASK
- PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P8G_MASK
- PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
- PCIE_ESM_CAP_1__ESM_8P9G_MASK
- PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P0G_MASK
- PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P1G_MASK
- PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P2G_MASK
- PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P3G_MASK
- PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P4G_MASK
- PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P5G_MASK
- PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P6G_MASK
- PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P7G_MASK
- PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P8G_MASK
- PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
- PCIE_ESM_CAP_1__ESM_9P9G_MASK
- PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P0G_MASK
- PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P1G_MASK
- PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P2G_MASK
- PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P3G_MASK
- PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P4G_MASK
- PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P5G_MASK
- PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P6G_MASK
- PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P7G_MASK
- PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P8G_MASK
- PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
- PCIE_ESM_CAP_2__ESM_11P9G_MASK
- PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P0G_MASK
- PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P1G_MASK
- PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P2G_MASK
- PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P3G_MASK
- PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P4G_MASK
- PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P5G_MASK
- PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P6G_MASK
- PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P7G_MASK
- PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P8G_MASK
- PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
- PCIE_ESM_CAP_2__ESM_12P9G_MASK
- PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P0G_MASK
- PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P1G_MASK
- PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P2G_MASK
- PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P3G_MASK
- PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P4G_MASK
- PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P5G_MASK
- PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P6G_MASK
- PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P7G_MASK
- PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P8G_MASK
- PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
- PCIE_ESM_CAP_2__ESM_13P9G_MASK
- PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P0G_MASK
- PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P1G_MASK
- PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P2G_MASK
- PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P3G_MASK
- PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P4G_MASK
- PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P5G_MASK
- PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P6G_MASK
- PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P7G_MASK
- PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P8G_MASK
- PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
- PCIE_ESM_CAP_3__ESM_14P9G_MASK
- PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P0G_MASK
- PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P1G_MASK
- PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P2G_MASK
- PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P3G_MASK
- PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P4G_MASK
- PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P5G_MASK
- PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P6G_MASK
- PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P7G_MASK
- PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P8G_MASK
- PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
- PCIE_ESM_CAP_3__ESM_15P9G_MASK
- PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P0G_MASK
- PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P1G_MASK
- PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P2G_MASK
- PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P3G_MASK
- PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P4G_MASK
- PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P5G_MASK
- PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P6G_MASK
- PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P7G_MASK
- PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P8G_MASK
- PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
- PCIE_ESM_CAP_4__ESM_16P9G_MASK
- PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P0G_MASK
- PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P1G_MASK
- PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P2G_MASK
- PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P3G_MASK
- PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P4G_MASK
- PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P5G_MASK
- PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P6G_MASK
- PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P7G_MASK
- PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P8G_MASK
- PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
- PCIE_ESM_CAP_4__ESM_17P9G_MASK
- PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P0G_MASK
- PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P1G_MASK
- PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P2G_MASK
- PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P3G_MASK
- PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P4G_MASK
- PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P5G_MASK
- PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P6G_MASK
- PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P7G_MASK
- PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P8G_MASK
- PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
- PCIE_ESM_CAP_4__ESM_18P9G_MASK
- PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P0G_MASK
- PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P1G_MASK
- PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P2G_MASK
- PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P3G_MASK
- PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P4G_MASK
- PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P5G_MASK
- PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P6G_MASK
- PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P7G_MASK
- PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P8G_MASK
- PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
- PCIE_ESM_CAP_5__ESM_19P9G_MASK
- PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P0G_MASK
- PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P1G_MASK
- PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P2G_MASK
- PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P3G_MASK
- PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P4G_MASK
- PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P5G_MASK
- PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P6G_MASK
- PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P7G_MASK
- PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P8G_MASK
- PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
- PCIE_ESM_CAP_5__ESM_20P9G_MASK
- PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P0G_MASK
- PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P1G_MASK
- PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P2G_MASK
- PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P3G_MASK
- PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P4G_MASK
- PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P5G_MASK
- PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P6G_MASK
- PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P7G_MASK
- PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P8G_MASK
- PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
- PCIE_ESM_CAP_5__ESM_21P9G_MASK
- PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P0G_MASK
- PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P1G_MASK
- PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P2G_MASK
- PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P3G_MASK
- PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P4G_MASK
- PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P5G_MASK
- PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P6G_MASK
- PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P7G_MASK
- PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P8G_MASK
- PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
- PCIE_ESM_CAP_6__ESM_22P9G_MASK
- PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P0G_MASK
- PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P1G_MASK
- PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P2G_MASK
- PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P3G_MASK
- PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P4G_MASK
- PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P5G_MASK
- PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P6G_MASK
- PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P7G_MASK
- PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P8G_MASK
- PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
- PCIE_ESM_CAP_6__ESM_23P9G_MASK
- PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P0G_MASK
- PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P1G_MASK
- PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P2G_MASK
- PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P3G_MASK
- PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P4G_MASK
- PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P5G_MASK
- PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P6G_MASK
- PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P7G_MASK
- PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P8G_MASK
- PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
- PCIE_ESM_CAP_6__ESM_24P9G_MASK
- PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P0G_MASK
- PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P1G_MASK
- PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P2G_MASK
- PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P3G_MASK
- PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P4G_MASK
- PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P5G_MASK
- PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P6G_MASK
- PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P7G_MASK
- PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P8G_MASK
- PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
- PCIE_ESM_CAP_7__ESM_25P9G_MASK
- PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P0G_MASK
- PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P1G_MASK
- PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P2G_MASK
- PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P3G_MASK
- PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P4G_MASK
- PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P5G_MASK
- PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P6G_MASK
- PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P7G_MASK
- PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P8G_MASK
- PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
- PCIE_ESM_CAP_7__ESM_26P9G_MASK
- PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P0G_MASK
- PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P1G_MASK
- PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P2G_MASK
- PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P3G_MASK
- PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P4G_MASK
- PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P5G_MASK
- PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P6G_MASK
- PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P7G_MASK
- PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P8G_MASK
- PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
- PCIE_ESM_CAP_7__ESM_27P9G_MASK
- PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
- PCIE_ESM_CAP_7__ESM_28P0G_MASK
- PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
- PCIE_ESM_CAP_LIST__CAP_ID_MASK
- PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
- PCIE_ESM_CAP_LIST__CAP_VER_MASK
- PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
- PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
- PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_ESM_CTRL__ESM_ENABLED_MASK
- PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
- PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
- PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
- PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
- PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
- PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
- PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
- PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
- PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
- PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
- PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
- PCIE_ESM_HEADER_2__CAP_ID_MASK
- PCIE_ESM_HEADER_2__CAP_ID__SHIFT
- PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
- PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
- PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
- PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
- PCIE_ETF_MAX_OFFSET
- PCIE_ETF_SECTION
- PCIE_EVENT_INTERRUPT
- PCIE_EVENT_INTERRUPT_ENABLE
- PCIE_EXT_CFG_RDY_REG
- PCIE_EXT_PCI_RESET
- PCIE_EXT_RESET
- PCIE_F
- PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK
- PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK
- PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK
- PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK
- PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK
- PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT
- PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK
- PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT
- PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK
- PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK
- PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT
- PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK
- PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT
- PCIE_FC_CPL__CPLD_CREDITS_MASK
- PCIE_FC_CPL__CPLD_CREDITS__SHIFT
- PCIE_FC_CPL__CPLH_CREDITS_MASK
- PCIE_FC_CPL__CPLH_CREDITS__SHIFT
- PCIE_FC_CREDIT
- PCIE_FC_CREDIT_MASK
- PCIE_FC_CREDIT_VAL
- PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK
- PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT
- PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK
- PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT
- PCIE_FC_NP__NPD_CREDITS_MASK
- PCIE_FC_NP__NPD_CREDITS__SHIFT
- PCIE_FC_NP__NPH_CREDITS_MASK
- PCIE_FC_NP__NPH_CREDITS__SHIFT
- PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK
- PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT
- PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK
- PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT
- PCIE_FC_P__PD_CREDITS_MASK
- PCIE_FC_P__PD_CREDITS__SHIFT
- PCIE_FC_P__PH_CREDITS_MASK
- PCIE_FC_P__PH_CREDITS__SHIFT
- PCIE_FTS_NUM
- PCIE_FTS_NUM_L0
- PCIE_FTS_NUM_MASK
- PCIE_FUNNEL_MAX_OFFSET
- PCIE_FUNNEL_SECTION
- PCIE_FW_A
- PCIE_FW_ERR_F
- PCIE_FW_ERR_S
- PCIE_FW_ERR_V
- PCIE_FW_EVAL_CRASH
- PCIE_FW_EVAL_G
- PCIE_FW_EVAL_M
- PCIE_FW_EVAL_S
- PCIE_FW_HALT_F
- PCIE_FW_HALT_S
- PCIE_FW_HALT_V
- PCIE_FW_INIT_F
- PCIE_FW_INIT_S
- PCIE_FW_INIT_V
- PCIE_FW_MASTER_G
- PCIE_FW_MASTER_M
- PCIE_FW_MASTER_S
- PCIE_FW_MASTER_V
- PCIE_FW_MASTER_VLD_F
- PCIE_FW_MASTER_VLD_S
- PCIE_FW_MASTER_VLD_V
- PCIE_FW_PF_A
- PCIE_FW_PF_DEVLOG
- PCIE_FW_PF_DEVLOG_ADDR16_G
- PCIE_FW_PF_DEVLOG_ADDR16_M
- PCIE_FW_PF_DEVLOG_ADDR16_S
- PCIE_FW_PF_DEVLOG_ADDR16_V
- PCIE_FW_PF_DEVLOG_MEMTYPE_G
- PCIE_FW_PF_DEVLOG_MEMTYPE_M
- PCIE_FW_PF_DEVLOG_MEMTYPE_S
- PCIE_FW_PF_DEVLOG_MEMTYPE_V
- PCIE_FW_PF_DEVLOG_NENTRIES128_G
- PCIE_FW_PF_DEVLOG_NENTRIES128_M
- PCIE_FW_PF_DEVLOG_NENTRIES128_S
- PCIE_FW_PF_DEVLOG_NENTRIES128_V
- PCIE_FW_REG
- PCIE_GEN1
- PCIE_GEN2
- PCIE_GEN2_CTRL_OFF
- PCIE_GEN3
- PCIE_GEN4
- PCIE_GEN_SEL_MSK
- PCIE_GEN_SEL_SHIFT
- PCIE_GET_ATU_INB_UNR_REG_OFFSET
- PCIE_GET_ATU_OUTB_UNR_REG_OFFSET
- PCIE_GLB_STS_PHY_LINK_UP
- PCIE_GLB_STS_RDLH_LINK_UP
- PCIE_GLOBAL_CONTROL_REG
- PCIE_GLOBAL_INT_CAUSE1_REG
- PCIE_GLOBAL_INT_MASK1_REG
- PCIE_GLOBAL_STATUS_REG
- PCIE_HCLK_RESET
- PCIE_HDP_AXI_CTRL
- PCIE_HDP_CFG0
- PCIE_HDP_CFG1
- PCIE_HDP_CFG10
- PCIE_HDP_CFG11
- PCIE_HDP_CFG2
- PCIE_HDP_CFG3
- PCIE_HDP_CFG4
- PCIE_HDP_CFG5
- PCIE_HDP_CFG6
- PCIE_HDP_CFG7
- PCIE_HDP_CFG8
- PCIE_HDP_CFG9
- PCIE_HDP_CTAG_CTRL
- PCIE_HDP_CTRL
- PCIE_HDP_HHBM_BUF_FIFO_NOE
- PCIE_HDP_HHBM_BUF_PTR
- PCIE_HDP_HHBM_BUF_PTR_H
- PCIE_HDP_HOST_WR_DESC0
- PCIE_HDP_HOST_WR_DESC0_H
- PCIE_HDP_HOST_WR_DESC1
- PCIE_HDP_HOST_WR_DESC1_H
- PCIE_HDP_HOST_WR_DESC2
- PCIE_HDP_HOST_WR_DESC2_H
- PCIE_HDP_HOST_WR_DESC3
- PCIE_HDP_HOST_WR_DESC4_H
- PCIE_HDP_INT_EN
- PCIE_HDP_INT_EP_RXDMA
- PCIE_HDP_INT_EP_TXDMA
- PCIE_HDP_INT_EP_TXEMPTY
- PCIE_HDP_INT_HBM_UF
- PCIE_HDP_INT_HHBM_UF
- PCIE_HDP_INT_IPC
- PCIE_HDP_INT_RX_BITS
- PCIE_HDP_INT_RX_HDR_LEN_ERR
- PCIE_HDP_INT_RX_LEN_ERR
- PCIE_HDP_INT_STATUS
- PCIE_HDP_INT_TX_BITS
- PCIE_HDP_RX0DMA_CNT
- PCIE_HDP_RX1DMA_CNT
- PCIE_HDP_RX2DMA_CNT
- PCIE_HDP_RX3DMA_CNT
- PCIE_HDP_RXDMA_CTRL
- PCIE_HDP_RX_DESC0_NOE
- PCIE_HDP_RX_DESC0_PTR
- PCIE_HDP_RX_DESC1_NOE
- PCIE_HDP_RX_DESC1_PTR
- PCIE_HDP_RX_DESC2_NOE
- PCIE_HDP_RX_DESC2_PTR
- PCIE_HDP_RX_DESC3_NOE
- PCIE_HDP_RX_DESC3_PTR
- PCIE_HDP_RX_INT_CTRL
- PCIE_HDP_TX0DMA_CNT
- PCIE_HDP_TX0_BASE_ADDR
- PCIE_HDP_TX0_Q_CTRL
- PCIE_HDP_TX1DMA_CNT
- PCIE_HDP_TX1_BASE_ADDR
- PCIE_HDP_TX1_Q_CTRL
- PCIE_HDP_TX_HOST_Q_BASE_H
- PCIE_HDP_TX_HOST_Q_BASE_L
- PCIE_HDP_TX_HOST_Q_RD_PTR
- PCIE_HDP_TX_HOST_Q_STS
- PCIE_HDP_TX_HOST_Q_SZ_CTRL
- PCIE_HDP_TX_HOST_Q_WR_PTR
- PCIE_HDP_TX_INT_CTRL
- PCIE_HDR_LOG0__TLP_HDR_MASK
- PCIE_HDR_LOG0__TLP_HDR__MASK
- PCIE_HDR_LOG0__TLP_HDR__SHIFT
- PCIE_HDR_LOG1__TLP_HDR_MASK
- PCIE_HDR_LOG1__TLP_HDR__MASK
- PCIE_HDR_LOG1__TLP_HDR__SHIFT
- PCIE_HDR_LOG2__TLP_HDR_MASK
- PCIE_HDR_LOG2__TLP_HDR__MASK
- PCIE_HDR_LOG2__TLP_HDR__SHIFT
- PCIE_HDR_LOG3__TLP_HDR_MASK
- PCIE_HDR_LOG3__TLP_HDR__MASK
- PCIE_HDR_LOG3__TLP_HDR__SHIFT
- PCIE_HEADER_LOG_4_OFF
- PCIE_HHBM_CONFIG
- PCIE_HHBM_CSR_REG
- PCIE_HHBM_MAX_SIZE
- PCIE_HHBM_POOL_CNFIG
- PCIE_HHBM_POOL_DATA_0
- PCIE_HHBM_POOL_DATA_0_H
- PCIE_HHBM_POOL_OVERFLOW_CNT
- PCIE_HHBM_POOL_REQ_0
- PCIE_HHBM_POOL_UNDERFLOW_CNT
- PCIE_HHBM_POOL_WATERMARK
- PCIE_HHBM_Q_BASE_REG
- PCIE_HHBM_Q_LIMIT_REG
- PCIE_HHBM_Q_RD_REG
- PCIE_HHBM_Q_WR_REG
- PCIE_HHBM_WATERMARK_INT
- PCIE_HHBM_WATERMARK_MASKED_INT
- PCIE_HIP06_CTRL_OFF
- PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI_MASK
- PCIE_HIP_REG0__CI_HIP_APT0_BASE_HI__SHIFT
- PCIE_HIP_REG0__CI_HIP_APT0_ENABLE_MASK
- PCIE_HIP_REG0__CI_HIP_APT0_ENABLE__SHIFT
- PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE_MASK
- PCIE_HIP_REG0__CI_HIP_APT0_PASID_MODE__SHIFT
- PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE_MASK
- PCIE_HIP_REG0__CI_HIP_APT0_REQAT_MODE__SHIFT
- PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE_MASK
- PCIE_HIP_REG0__CI_HIP_APT0_REQIO_MODE__SHIFT
- PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO_MASK
- PCIE_HIP_REG1__CI_HIP_APT0_BASE_LO__SHIFT
- PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI_MASK
- PCIE_HIP_REG2__CI_HIP_APT0_LIMIT_HI__SHIFT
- PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO_MASK
- PCIE_HIP_REG3__CI_HIP_APT0_LIMIT_LO__SHIFT
- PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI_MASK
- PCIE_HIP_REG4__CI_HIP_APT1_BASE_HI__SHIFT
- PCIE_HIP_REG4__CI_HIP_APT1_ENABLE_MASK
- PCIE_HIP_REG4__CI_HIP_APT1_ENABLE__SHIFT
- PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE_MASK
- PCIE_HIP_REG4__CI_HIP_APT1_PASID_MODE__SHIFT
- PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE_MASK
- PCIE_HIP_REG4__CI_HIP_APT1_REQAT_MODE__SHIFT
- PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE_MASK
- PCIE_HIP_REG4__CI_HIP_APT1_REQIO_MODE__SHIFT
- PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO_MASK
- PCIE_HIP_REG5__CI_HIP_APT1_BASE_LO__SHIFT
- PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI_MASK
- PCIE_HIP_REG6__CI_HIP_APT1_LIMIT_HI__SHIFT
- PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO_MASK
- PCIE_HIP_REG7__CI_HIP_APT1_LIMIT_LO__SHIFT
- PCIE_HIP_REG8__CI_HIP_MASK_MASK
- PCIE_HIP_REG8__CI_HIP_MASK__SHIFT
- PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A_MASK
- PCIE_HOLD_TRAINING_A__HOLD_TRAINING_A__SHIFT
- PCIE_HOST_INT_MASK
- PCIE_HOST_INT_STATUS
- PCIE_HOST_INT_STATUS_MASK
- PCIE_HWID
- PCIE_HW_DEBUG__HW_00_DEBUG_MASK
- PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_01_DEBUG_MASK
- PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_02_DEBUG_MASK
- PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_03_DEBUG_MASK
- PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_04_DEBUG_MASK
- PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_05_DEBUG_MASK
- PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_06_DEBUG_MASK
- PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_07_DEBUG_MASK
- PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_08_DEBUG_MASK
- PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_09_DEBUG_MASK
- PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_10_DEBUG_MASK
- PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_11_DEBUG_MASK
- PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_12_DEBUG_MASK
- PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_13_DEBUG_MASK
- PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_14_DEBUG_MASK
- PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT
- PCIE_HW_DEBUG__HW_15_DEBUG_MASK
- PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT
- PCIE_H_CLK
- PCIE_H_RESET
- PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK
- PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT
- PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK
- PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT
- PCIE_IATU_NUM
- PCIE_ICH8_SNOOP_ALL
- PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS_MASK
- PCIE_IDLE_STATUS__PCIE_ALL_IDLE_STATUS__SHIFT
- PCIE_IDLE_STATUS__TX_CPLBUF_IDLE_MASK
- PCIE_IDLE_STATUS__TX_CPLBUF_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_MSGBUF_IDLE_MASK
- PCIE_IDLE_STATUS__TX_MSGBUF_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_NPBUF_IDLE_MASK
- PCIE_IDLE_STATUS__TX_NPBUF_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_PBUF_IDLE_MASK
- PCIE_IDLE_STATUS__TX_PBUF_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS_MASK
- PCIE_IDLE_STATUS__TX_RBUF_IDLE_STATUS__SHIFT
- PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE_MASK
- PCIE_IDLE_STATUS__TX_RCVD_FC_CREDITS_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE_MASK
- PCIE_IDLE_STATUS__TX_RPL_CREDITS_IDLE__SHIFT
- PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS_MASK
- PCIE_IDLE_STATUS__TX_TXDL_IDLE_STATUS__SHIFT
- PCIE_IDVAL3_REG
- PCIE_IMSI_ADDR
- PCIE_IMSI_STATUS
- PCIE_INDEX
- PCIE_INDEX2__PCIE_INDEX2_MASK
- PCIE_INDEX2__PCIE_INDEX2__MASK
- PCIE_INDEX2__PCIE_INDEX2__SHIFT
- PCIE_INDEX_2__PCIE_INDEX_MASK
- PCIE_INDEX_2__PCIE_INDEX__SHIFT
- PCIE_INDEX__PCIE_INDEX_MASK
- PCIE_INDEX__PCIE_INDEX__MASK
- PCIE_INDEX__PCIE_INDEX__SHIFT
- PCIE_INT
- PCIE_INTERRUPT_MASK
- PCIE_INTERRUPT_MASK_OFF
- PCIE_INTR_CAUSE_ADDRESS
- PCIE_INTR_CE_MASK_ALL
- PCIE_INTR_CLR_ADDRESS
- PCIE_INTR_ENABLE0_REG
- PCIE_INTR_ENABLE1_REG
- PCIE_INTR_ENABLE_ADDRESS
- PCIE_INTR_FIRMWARE_MASK
- PCIE_INTR_MASK
- PCIE_INT_A_ASSERT_MASK
- PCIE_INT_B_ASSERT_MASK
- PCIE_INT_CAUSE_A
- PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK
- PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT
- PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK
- PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT
- PCIE_INT_CNTL__LINK_BW_INT_EN_MASK
- PCIE_INT_CNTL__LINK_BW_INT_EN__SHIFT
- PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK
- PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT
- PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK
- PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT
- PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK
- PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT
- PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN_MASK
- PCIE_INT_CNTL__QUIESCE_RCVD_INT_EN__SHIFT
- PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK
- PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT
- PCIE_INT_C_ASSERT_MASK
- PCIE_INT_D_ASSERT_MASK
- PCIE_INT_EN0
- PCIE_INT_EN1
- PCIE_INT_ENABLE
- PCIE_INT_INTX
- PCIE_INT_MASK
- PCIE_INT_MSI
- PCIE_INT_STATUS
- PCIE_INT_STATUS0
- PCIE_INT_STATUS1
- PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK
- PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT
- PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK
- PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT
- PCIE_INT_STATUS__LINK_BW_INT_STATUS_MASK
- PCIE_INT_STATUS__LINK_BW_INT_STATUS__SHIFT
- PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK
- PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT
- PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK
- PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT
- PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK
- PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT
- PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS_MASK
- PCIE_INT_STATUS__QUIESCE_RCVD_INT_STATUS__SHIFT
- PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK
- PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT
- PCIE_IO_BASE
- PCIE_IO_LIMIT
- PCIE_IP_REG_ACS
- PCIE_IP_REG_ACS_ADDR
- PCIE_IP_REG_ACS_DATA
- PCIE_IP_REV_2_2
- PCIE_IP_REV_3_0
- PCIE_IRQ_ALL_MASK
- PCIE_IRQ_CAUSE
- PCIE_IRQ_CMDQ_INT
- PCIE_IRQ_CMD_SENT_DONE
- PCIE_IRQ_COMPQ_INT
- PCIE_IRQ_CORE_INT
- PCIE_IRQ_CORE_INT_PIO
- PCIE_IRQ_DIR_RD_DDR_DET
- PCIE_IRQ_DIR_WR_DDR_DET
- PCIE_IRQ_DMA_INT
- PCIE_IRQ_DPMU_INT
- PCIE_IRQ_ENABLE_INTS_MASK
- PCIE_IRQ_EN_LEVEL
- PCIE_IRQ_EN_PULSE
- PCIE_IRQ_EN_SPECIAL
- PCIE_IRQ_EP_STATUS
- PCIE_IRQ_IB_DXFERDONE
- PCIE_IRQ_LEVEL
- PCIE_IRQ_MASK
- PCIE_IRQ_MSI_INT1_DET
- PCIE_IRQ_MSI_INT2_DET
- PCIE_IRQ_MSI_STATUS_INT
- PCIE_IRQ_OB_DXFERDONE
- PCIE_IRQ_OB_RXFERDONE
- PCIE_IRQ_PCIE_MIS_INT
- PCIE_IRQ_PULSE
- PCIE_IRQ_RC_DBELL_DET
- PCIE_IRQ_SPECIAL
- PCIE_ISR0_ALL_MASK
- PCIE_ISR0_INTX_ASSERT
- PCIE_ISR0_INTX_DEASSERT
- PCIE_ISR0_MASK_REG
- PCIE_ISR0_MSI_INT_PENDING
- PCIE_ISR0_REG
- PCIE_ISR1_ALL_MASK
- PCIE_ISR1_FLUSH
- PCIE_ISR1_INTX_ASSERT
- PCIE_ISR1_MASK_REG
- PCIE_ISR1_POWER_STATE_CHANGE
- PCIE_ISR1_REG
- PCIE_L1_0_EN
- PCIE_L1_0_PD_FE_EN
- PCIE_L1_1_EN
- PCIE_L1_1_PD_FE_EN
- PCIE_L1_2_EN
- PCIE_L1_2_PD_FE_EN
- PCIE_L1_ASPM_READY_REG
- PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
- PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
- PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
- PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
- PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
- PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
- PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
- PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
- PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
- PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
- PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
- PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
- PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
- PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
- PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
- PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
- PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
- PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
- PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
- PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
- PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
- PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
- PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
- PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
- PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
- PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
- PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
- PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
- PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
- PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
- PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
- PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
- PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
- PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
- PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
- PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
- PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
- PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
- PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK
- PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
- PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK
- PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
- PCIE_LANE_ERROR_STATUS__RESERVED_MASK
- PCIE_LANE_ERROR_STATUS__RESERVED__MASK
- PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK
- PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT
- PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK
- PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT
- PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK
- PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT
- PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK
- PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT
- PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK
- PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT
- PCIE_LC_CNTL
- PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK
- PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT
- PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK
- PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT
- PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK
- PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT
- PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK
- PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT
- PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK
- PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT
- PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK
- PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT
- PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK
- PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT
- PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK
- PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT
- PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK
- PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT
- PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK
- PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT
- PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK
- PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK
- PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT
- PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK
- PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK
- PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT
- PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK
- PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT
- PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK
- PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT
- PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK
- PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK
- PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_DONE_MASK
- PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_EN_MASK
- PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_MODE_MASK
- PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK
- PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT
- PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK
- PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT
- PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK
- PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT
- PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK
- PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT
- PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK
- PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT
- PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK
- PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT
- PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK
- PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT
- PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK
- PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT
- PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK
- PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT
- PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK
- PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT
- PCIE_LC_CNTL2
- PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
- PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
- PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
- PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
- PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
- PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
- PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
- PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
- PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
- PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
- PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
- PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
- PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
- PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
- PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
- PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
- PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
- PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
- PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
- PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
- PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
- PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
- PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK
- PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
- PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
- PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
- PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
- PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
- PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
- PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
- PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
- PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
- PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
- PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
- PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
- PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
- PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
- PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
- PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
- PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
- PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
- PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
- PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
- PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
- PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
- PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
- PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
- PCIE_LC_CNTL3
- PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
- PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
- PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK
- PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT
- PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
- PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
- PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK
- PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
- PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK
- PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT
- PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK
- PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT
- PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK
- PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT
- PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK
- PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT
- PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK
- PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT
- PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK
- PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT
- PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK
- PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT
- PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK
- PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT
- PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK
- PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK
- PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT
- PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK
- PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT
- PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK
- PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT
- PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK
- PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT
- PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK
- PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT
- PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK
- PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT
- PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK
- PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT
- PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK
- PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT
- PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK
- PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT
- PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK
- PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT
- PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK
- PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT
- PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK
- PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT
- PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK
- PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT
- PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK
- PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT
- PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK
- PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT
- PCIE_LC_CNTL4
- PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK
- PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT
- PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK
- PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT
- PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK
- PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK
- PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT
- PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK
- PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT
- PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK
- PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT
- PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK
- PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT
- PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK
- PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT
- PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK
- PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT
- PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK
- PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT
- PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK
- PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT
- PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK
- PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT
- PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK
- PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT
- PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK
- PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT
- PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK
- PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT
- PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK
- PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT
- PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK
- PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT
- PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING_MASK
- PCIE_LC_CNTL4__LC_PCIE_TX_FULL_SWING__SHIFT
- PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK
- PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT
- PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK
- PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT
- PCIE_LC_CNTL4__LC_REDO_EQ_MASK
- PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT
- PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK
- PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT
- PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK
- PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT
- PCIE_LC_CNTL4__LC_TX_SWING_MASK
- PCIE_LC_CNTL4__LC_TX_SWING__SHIFT
- PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK
- PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT
- PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK
- PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT
- PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK
- PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT
- PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK
- PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT
- PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK
- PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT
- PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK
- PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT
- PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK
- PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT
- PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK
- PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT
- PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK
- PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK
- PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT
- PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT
- PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK
- PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT
- PCIE_LC_CNTL5__LC_EQ_FS_0_MASK
- PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT
- PCIE_LC_CNTL5__LC_EQ_FS_8_MASK
- PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT
- PCIE_LC_CNTL5__LC_EQ_LF_0_MASK
- PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT
- PCIE_LC_CNTL5__LC_EQ_LF_8_MASK
- PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT
- PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK
- PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT
- PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK
- PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT
- PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK
- PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT
- PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK
- PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT
- PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK
- PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT
- PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK
- PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT
- PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK
- PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT
- PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK
- PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT
- PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK
- PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT
- PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK
- PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT
- PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK
- PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT
- PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
- PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
- PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK
- PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT
- PCIE_LC_CNTL6__LC_P2_ENTRY_MASK
- PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT
- PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK
- PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT
- PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK
- PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT
- PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK
- PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT
- PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK
- PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT
- PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK
- PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT
- PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK
- PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT
- PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK
- PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT
- PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK
- PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK
- PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT
- PCIE_LC_CNTL6__LC_SRIS_EN_MASK
- PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT
- PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK
- PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT
- PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
- PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
- PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK
- PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT
- PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK
- PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT
- PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
- PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
- PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK
- PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT
- PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK
- PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT
- PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK
- PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT
- PCIE_LC_CNTL7__LC_ESM_RATES_MASK
- PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT
- PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK
- PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT
- PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK
- PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT
- PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK
- PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT
- PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK
- PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT
- PCIE_LC_CNTL7__LC_FOM_TIME_MASK
- PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT
- PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK
- PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT
- PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK
- PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT
- PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK
- PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT
- PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK
- PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT
- PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK
- PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT
- PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK
- PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT
- PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK
- PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT
- PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK
- PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT
- PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK
- PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT
- PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK
- PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT
- PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK
- PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK
- PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT
- PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK
- PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT
- PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK
- PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT
- PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK
- PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT
- PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK
- PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT
- PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK
- PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT
- PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK
- PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
- PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
- PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
- PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK
- PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT
- PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK
- PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT
- PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK
- PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT
- PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK
- PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT
- PCIE_LC_CNTL8__LC_FOM_TIME_MASK
- PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT
- PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK
- PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT
- PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK
- PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT
- PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK
- PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT
- PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK
- PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT
- PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK
- PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT
- PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK
- PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT
- PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK
- PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT
- PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK
- PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT
- PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK
- PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT
- PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK
- PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT
- PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK
- PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT
- PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK
- PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT
- PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK
- PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT
- PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK
- PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT
- PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK
- PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT
- PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK
- PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT
- PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK
- PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT
- PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK
- PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT
- PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK
- PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT
- PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK
- PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT
- PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK
- PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT
- PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK
- PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT
- PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK
- PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT
- PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK
- PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT
- PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK
- PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT
- PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK
- PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT
- PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK
- PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT
- PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK
- PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT
- PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK
- PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT
- PCIE_LC_CNTL__LC_DELAY_COUNT_MASK
- PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT
- PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK
- PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT
- PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK
- PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT
- PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK
- PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT
- PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK
- PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT
- PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK
- PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT
- PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK
- PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT
- PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK
- PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT
- PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK
- PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT
- PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK
- PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT
- PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK
- PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT
- PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK
- PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT
- PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK
- PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT
- PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK
- PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT
- PCIE_LC_CNTL__LC_RESET_LINK_MASK
- PCIE_LC_CNTL__LC_RESET_LINK__SHIFT
- PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK
- PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT
- PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK
- PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT
- PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK
- PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT
- PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN_MASK
- PCIE_LC_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT
- PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK
- PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT
- PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK
- PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT
- PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK
- PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT
- PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK
- PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT
- PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK
- PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT
- PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK
- PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT
- PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK
- PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK
- PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK
- PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT
- PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK
- PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT
- PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK
- PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK
- PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT
- PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK
- PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT
- PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK
- PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK
- PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT
- PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK
- PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT
- PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK
- PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT
- PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK
- PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL
- PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT
- PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK
- PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT
- PCIE_LC_N_FTS_CNTL
- PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK
- PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK
- PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT
- PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT
- PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK
- PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT
- PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK
- PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT
- PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK
- PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT
- PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK
- PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK
- PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT
- PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK
- PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT
- PCIE_LC_SPEED_CNTL
- PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
- PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
- PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
- PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
- PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
- PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
- PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
- PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
- PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
- PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
- PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
- PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
- PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
- PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
- PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
- PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
- PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
- PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
- PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
- PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
- PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK
- PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK
- PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
- PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
- PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
- PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
- PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
- PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
- PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
- PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
- PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
- PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
- PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
- PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
- PCIE_LC_STATE0__LC_CURRENT_STATE_MASK
- PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT
- PCIE_LC_STATE0__LC_PREV_STATE1_MASK
- PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT
- PCIE_LC_STATE0__LC_PREV_STATE2_MASK
- PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT
- PCIE_LC_STATE0__LC_PREV_STATE3_MASK
- PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT
- PCIE_LC_STATE10__LC_PREV_STATE40_MASK
- PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT
- PCIE_LC_STATE10__LC_PREV_STATE41_MASK
- PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT
- PCIE_LC_STATE10__LC_PREV_STATE42_MASK
- PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT
- PCIE_LC_STATE10__LC_PREV_STATE43_MASK
- PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT
- PCIE_LC_STATE11__LC_PREV_STATE44_MASK
- PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT
- PCIE_LC_STATE11__LC_PREV_STATE45_MASK
- PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT
- PCIE_LC_STATE11__LC_PREV_STATE46_MASK
- PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT
- PCIE_LC_STATE11__LC_PREV_STATE47_MASK
- PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT
- PCIE_LC_STATE1__LC_PREV_STATE4_MASK
- PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT
- PCIE_LC_STATE1__LC_PREV_STATE5_MASK
- PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT
- PCIE_LC_STATE1__LC_PREV_STATE6_MASK
- PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT
- PCIE_LC_STATE1__LC_PREV_STATE7_MASK
- PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT
- PCIE_LC_STATE2__LC_PREV_STATE10_MASK
- PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT
- PCIE_LC_STATE2__LC_PREV_STATE11_MASK
- PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT
- PCIE_LC_STATE2__LC_PREV_STATE8_MASK
- PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT
- PCIE_LC_STATE2__LC_PREV_STATE9_MASK
- PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT
- PCIE_LC_STATE3__LC_PREV_STATE12_MASK
- PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT
- PCIE_LC_STATE3__LC_PREV_STATE13_MASK
- PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT
- PCIE_LC_STATE3__LC_PREV_STATE14_MASK
- PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT
- PCIE_LC_STATE3__LC_PREV_STATE15_MASK
- PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT
- PCIE_LC_STATE4__LC_PREV_STATE16_MASK
- PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT
- PCIE_LC_STATE4__LC_PREV_STATE17_MASK
- PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT
- PCIE_LC_STATE4__LC_PREV_STATE18_MASK
- PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT
- PCIE_LC_STATE4__LC_PREV_STATE19_MASK
- PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT
- PCIE_LC_STATE5__LC_PREV_STATE20_MASK
- PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT
- PCIE_LC_STATE5__LC_PREV_STATE21_MASK
- PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT
- PCIE_LC_STATE5__LC_PREV_STATE22_MASK
- PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT
- PCIE_LC_STATE5__LC_PREV_STATE23_MASK
- PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT
- PCIE_LC_STATE6__LC_PREV_STATE24_MASK
- PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT
- PCIE_LC_STATE6__LC_PREV_STATE25_MASK
- PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT
- PCIE_LC_STATE6__LC_PREV_STATE26_MASK
- PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT
- PCIE_LC_STATE6__LC_PREV_STATE27_MASK
- PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT
- PCIE_LC_STATE7__LC_PREV_STATE28_MASK
- PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT
- PCIE_LC_STATE7__LC_PREV_STATE29_MASK
- PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT
- PCIE_LC_STATE7__LC_PREV_STATE30_MASK
- PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT
- PCIE_LC_STATE7__LC_PREV_STATE31_MASK
- PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT
- PCIE_LC_STATE8__LC_PREV_STATE32_MASK
- PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT
- PCIE_LC_STATE8__LC_PREV_STATE33_MASK
- PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT
- PCIE_LC_STATE8__LC_PREV_STATE34_MASK
- PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT
- PCIE_LC_STATE8__LC_PREV_STATE35_MASK
- PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT
- PCIE_LC_STATE9__LC_PREV_STATE36_MASK
- PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT
- PCIE_LC_STATE9__LC_PREV_STATE37_MASK
- PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT
- PCIE_LC_STATE9__LC_PREV_STATE38_MASK
- PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT
- PCIE_LC_STATE9__LC_PREV_STATE39_MASK
- PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT
- PCIE_LC_STATUS1
- PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK
- PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT
- PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK
- PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT
- PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK
- PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT
- PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK
- PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT
- PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK
- PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT
- PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK
- PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT
- PCIE_LC_TRAINING_CNTL
- PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK
- PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK
- PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK
- PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK
- PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK
- PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK
- PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK
- PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK
- PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK
- PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK
- PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK
- PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK
- PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK
- PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK
- PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK
- PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK
- PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK
- PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK
- PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK
- PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT
- PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK
- PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT
- PCIE_LEGACY_IRQ_ENABLE_CLR
- PCIE_LEGACY_IRQ_ENABLE_SET
- PCIE_LINKDOWN_RST_EN
- PCIE_LINKUP_ENABLE
- PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
- PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK
- PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
- PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
- PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK
- PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
- PCIE_LINK_CNTL3__RESERVED_MASK
- PCIE_LINK_CNTL3__RESERVED__MASK
- PCIE_LINK_CNTL3__RESERVED__SHIFT
- PCIE_LINK_IS_GEN2
- PCIE_LINK_IS_L2
- PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK
- PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK
- PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK
- PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK
- PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK
- PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK
- PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK
- PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK
- PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT
- PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK
- PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK
- PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK
- PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK
- PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK
- PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT
- PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK
- PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT
- PCIE_LINK_STATE_CLKPM
- PCIE_LINK_STATE_L0S
- PCIE_LINK_STATE_L1
- PCIE_LINK_STATUS
- PCIE_LINK_STATUS_V2
- PCIE_LINK_UP
- PCIE_LINK_UP_ST
- PCIE_LINK_WIDTH_MASK
- PCIE_LINK_WIDTH_SHIFT
- PCIE_LINK_WIDTH_SPEED_CONTROL
- PCIE_LNK_WIDTH_RESRV
- PCIE_LNK_WIDTH_UNKNOWN
- PCIE_LNK_X1
- PCIE_LNK_X12
- PCIE_LNK_X16
- PCIE_LNK_X2
- PCIE_LNK_X32
- PCIE_LNK_X4
- PCIE_LNK_X8
- PCIE_LOCAL_BASE_ADDRESS
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK
- PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK
- PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
- PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_LTSSM
- PCIE_LTSSM_ENABLE_BIT
- PCIE_LTSSM_L0
- PCIE_LTSSM_LINKUP_STATE
- PCIE_LTSSM_STATE_ACTIVE
- PCIE_LTSSM_STATE_MASK
- PCIE_MAC_SRSTB
- PCIE_MAILBOX_REG
- PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_MASK_ENABLE_INTS
- PCIE_MASK_OFF
- PCIE_MAX_DMA_XFER_SIZE
- PCIE_MAX_MASTER_SPLIT
- PCIE_MA_SYNC_A
- PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
- PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK
- PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
- PCIE_MC_ADDR0__MC_INDEX_POS_MASK
- PCIE_MC_ADDR0__MC_INDEX_POS__MASK
- PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
- PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
- PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK
- PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
- PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
- PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK
- PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
- PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
- PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK
- PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
- PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
- PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK
- PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
- PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
- PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK
- PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
- PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
- PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK
- PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
- PCIE_MC_CAP__MC_MAX_GROUP_MASK
- PCIE_MC_CAP__MC_MAX_GROUP__MASK
- PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
- PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
- PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK
- PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
- PCIE_MC_CNTL__MC_ENABLE_MASK
- PCIE_MC_CNTL__MC_ENABLE__MASK
- PCIE_MC_CNTL__MC_ENABLE__SHIFT
- PCIE_MC_CNTL__MC_NUM_GROUP_MASK
- PCIE_MC_CNTL__MC_NUM_GROUP__MASK
- PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
- PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
- PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
- PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
- PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
- PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
- PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
- PCIE_MC_RCV0__MC_RECEIVE_0_MASK
- PCIE_MC_RCV0__MC_RECEIVE_0__MASK
- PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
- PCIE_MC_RCV1__MC_RECEIVE_1_MASK
- PCIE_MC_RCV1__MC_RECEIVE_1__MASK
- PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
- PCIE_MEMWIN_MAX_NPPODS
- PCIE_MEM_ACCESS_BASE_WIN_A
- PCIE_MEM_ACCESS_OFFSET_A
- PCIE_MEM_ACCESS_REG
- PCIE_MEM_BASE
- PCIE_MEM_LIMIT
- PCIE_MIPHYP_ADDR_REG
- PCIE_MIPHYP_SSC_EN_REG
- PCIE_MISCCFG_RC
- PCIE_MISC_CONTROL_1_OFF
- PCIE_MN_WINDOW_REG
- PCIE_MPS_128B
- PCIE_MPS_256B
- PCIE_MPS_DEFAULT
- PCIE_MRRS_1024B
- PCIE_MRRS_128B
- PCIE_MRRS_2048B
- PCIE_MRRS_256B
- PCIE_MRRS_4096B
- PCIE_MRRS_512B
- PCIE_MRRS_DEFAULT
- PCIE_MSG_LOG_REG
- PCIE_MSG_PM_PME_MASK
- PCIE_MSIX_STATUS
- PCIE_MSI_ADDR_HI
- PCIE_MSI_ADDR_HIGH_REG
- PCIE_MSI_ADDR_LO
- PCIE_MSI_ADDR_LOW_REG
- PCIE_MSI_EN
- PCIE_MSI_INTR0_ENABLE
- PCIE_MSI_INTR0_MASK
- PCIE_MSI_INTR0_STATUS
- PCIE_MSI_MASK
- PCIE_MSI_MASK_REG
- PCIE_MSI_PAYLOAD_REG
- PCIE_MSI_PNDG
- PCIE_MSI_STATUS
- PCIE_MSI_STATUS_REG
- PCIE_MSI_VECTOR
- PCIE_NLINKS
- PCIE_NONFAT_ERR_A
- PCIE_NONSTICKY_RESET
- PCIE_NORMAL_RESET
- PCIE_NO_SNOOP_ALL
- PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0_MASK
- PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE_MASK
- PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH_MASK
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_MASK
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD_MASK
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN_MASK
- PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT
- PCIE_OE_BYPASS
- PCIE_OUR3_WOL_D3_COLD_SET
- PCIE_OUR5_EVENT_CLK_D3_SET
- PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK
- PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK
- PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT
- PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK
- PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK
- PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT
- PCIE_PAB_AMBA_SW_RST_REG
- PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK
- PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK
- PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT
- PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK
- PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK
- PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK
- PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK
- PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT
- PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK
- PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK
- PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT
- PCIE_PAGE_REQ_STATUS__STOPPED_MASK
- PCIE_PAGE_REQ_STATUS__STOPPED__MASK
- PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT
- PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK
- PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK
- PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT
- PCIE_PARF_XPU_ARES
- PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK
- PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK
- PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT
- PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK
- PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK
- PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT
- PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK
- PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK
- PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT
- PCIE_PASID_CNTL__PASID_ENABLE_MASK
- PCIE_PASID_CNTL__PASID_ENABLE__MASK
- PCIE_PASID_CNTL__PASID_ENABLE__SHIFT
- PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK
- PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK
- PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT
- PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK
- PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK
- PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT
- PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_PCI_RESET
- PCIE_PCS_DELAY_COUNT_SHIFT
- PCIE_PCS_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK
- PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK
- PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK
- PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK
- PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT
- PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_SCLK1__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_SCLK1__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_SCLK1__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_SCLK1__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_SCLK2__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_SCLK2__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_SCLK2__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_SCLK2__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK
- PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT
- PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK
- PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT
- PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK
- PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT
- PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_SCLK1__COUNTER0_MASK
- PCIE_PERF_COUNT0_SCLK1__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_SCLK2__COUNTER0_MASK
- PCIE_PERF_COUNT0_SCLK2__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK
- PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK
- PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK
- PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK
- PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT
- PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK
- PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT
- PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_SCLK1__COUNTER1_MASK
- PCIE_PERF_COUNT1_SCLK1__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_SCLK2__COUNTER1_MASK
- PCIE_PERF_COUNT1_SCLK2__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK
- PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK
- PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK
- PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK
- PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT
- PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK
- PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT
- PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK
- PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT
- PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK
- PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT
- PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK
- PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT
- PCIE_PERF_GET
- PCIE_PERF_GET64
- PCIE_PERF_OFF
- PCIE_PERF_OFF64
- PCIE_PERF_REQ_FORCE_LOWPOWER
- PCIE_PERF_REQ_GEN1
- PCIE_PERF_REQ_GEN2
- PCIE_PERF_REQ_GEN3
- PCIE_PERF_REQ_PECI_GEN1
- PCIE_PERF_REQ_PECI_GEN2
- PCIE_PERF_REQ_PECI_GEN3
- PCIE_PERF_REQ_REMOVE_REGISTRY
- PCIE_PERSTB
- PCIE_PF_CFG_A
- PCIE_PF_CLI_A
- PCIE_PGFSM2_CONFIG__FSM_ADDR_MASK
- PCIE_PGFSM2_CONFIG__FSM_ADDR__SHIFT
- PCIE_PGFSM2_CONFIG__P1_Select_MASK
- PCIE_PGFSM2_CONFIG__P1_Select__SHIFT
- PCIE_PGFSM2_CONFIG__P2_Select_MASK
- PCIE_PGFSM2_CONFIG__P2_Select__SHIFT
- PCIE_PGFSM2_CONFIG__Power_Down_MASK
- PCIE_PGFSM2_CONFIG__Power_Down__SHIFT
- PCIE_PGFSM2_CONFIG__Power_Up_MASK
- PCIE_PGFSM2_CONFIG__Power_Up__SHIFT
- PCIE_PGFSM2_CONFIG__REG_ADDR_MASK
- PCIE_PGFSM2_CONFIG__REG_ADDR__SHIFT
- PCIE_PGFSM2_CONFIG__Read_Op_MASK
- PCIE_PGFSM2_CONFIG__Read_Op__SHIFT
- PCIE_PGFSM2_CONFIG__Reserved_MASK
- PCIE_PGFSM2_CONFIG__Reserved__SHIFT
- PCIE_PGFSM2_CONFIG__Write_Op_MASK
- PCIE_PGFSM2_CONFIG__Write_Op__SHIFT
- PCIE_PGFSM2_WRITE__Write_value_MASK
- PCIE_PGFSM2_WRITE__Write_value__SHIFT
- PCIE_PGFSM_0_READ__Read_valid_MASK
- PCIE_PGFSM_0_READ__Read_valid__SHIFT
- PCIE_PGFSM_0_READ__Read_value_MASK
- PCIE_PGFSM_0_READ__Read_value__SHIFT
- PCIE_PGFSM_1_READ__Read_valid_MASK
- PCIE_PGFSM_1_READ__Read_valid__SHIFT
- PCIE_PGFSM_1_READ__Read_value_MASK
- PCIE_PGFSM_1_READ__Read_value__SHIFT
- PCIE_PGFSM_CONFIG__FSM_ADDR_MASK
- PCIE_PGFSM_CONFIG__FSM_ADDR__SHIFT
- PCIE_PGFSM_CONFIG__P1_Select_MASK
- PCIE_PGFSM_CONFIG__P1_Select__SHIFT
- PCIE_PGFSM_CONFIG__P2_Select_MASK
- PCIE_PGFSM_CONFIG__P2_Select__SHIFT
- PCIE_PGFSM_CONFIG__Power_Down_MASK
- PCIE_PGFSM_CONFIG__Power_Down__SHIFT
- PCIE_PGFSM_CONFIG__Power_Up_MASK
- PCIE_PGFSM_CONFIG__Power_Up__SHIFT
- PCIE_PGFSM_CONFIG__REG_ADDR_MASK
- PCIE_PGFSM_CONFIG__REG_ADDR__SHIFT
- PCIE_PGFSM_CONFIG__Read_Op_MASK
- PCIE_PGFSM_CONFIG__Read_Op__SHIFT
- PCIE_PGFSM_CONFIG__Reserved_MASK
- PCIE_PGFSM_CONFIG__Reserved__SHIFT
- PCIE_PGFSM_CONFIG__Write_Op_MASK
- PCIE_PGFSM_CONFIG__Write_Op__SHIFT
- PCIE_PGFSM_WRITE__Write_value_MASK
- PCIE_PGFSM_WRITE__Write_value__SHIFT
- PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK
- PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT
- PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK
- PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT
- PCIE_PGMST_CNTL__CFG_PG_EN_MASK
- PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT
- PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK
- PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT
- PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK
- PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT
- PCIE_PHYLINKUP
- PCIE_PHYLINKUP_SHIFT
- PCIE_PHYMISC2_CDR_BW_MASK
- PCIE_PHYMISC2_CDR_BW_SHIFT
- PCIE_PHYMISC2_L0S_TH_MASK
- PCIE_PHYMISC2_L0S_TH_SHIFT
- PCIE_PHYMISC_FORCE_RCV_DET
- PCIE_PHYMISC_NFTS_MASK
- PCIE_PHYMISC_NFTS_SHIFT
- PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_PHY_AHB_ARES
- PCIE_PHY_ARES
- PCIE_PHY_ATEOVRD
- PCIE_PHY_ATEOVRD_EN
- PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK
- PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT
- PCIE_PHY_CLK
- PCIE_PHY_CMN_REG
- PCIE_PHY_CMN_REG15
- PCIE_PHY_CMN_REG15_DLY_4
- PCIE_PHY_CMN_REG15_OVRD_PLL_PD
- PCIE_PHY_CMN_REG15_PLL_PD
- PCIE_PHY_CMN_REG24
- PCIE_PHY_CMN_REG24_RX_EQ
- PCIE_PHY_CMN_REG24_RX_EQ_SEL
- PCIE_PHY_CMN_REG26
- PCIE_PHY_CMN_REG26_ATT_MODE
- PCIE_PHY_CMN_REG4
- PCIE_PHY_CMN_REG4_DCC_FB_EN
- PCIE_PHY_COMMON_PD_CMN
- PCIE_PHY_COMMON_POWER
- PCIE_PHY_COMMON_RESET
- PCIE_PHY_CR
- PCIE_PHY_CTRL
- PCIE_PHY_CTRL_CAP_ADR
- PCIE_PHY_CTRL_CAP_DAT
- PCIE_PHY_CTRL_DATA
- PCIE_PHY_CTRL_RD
- PCIE_PHY_CTRL_WR
- PCIE_PHY_DCC_FEEDBACK
- PCIE_PHY_GLOBAL_RESET
- PCIE_PHY_IMPEDANCE
- PCIE_PHY_LINKUP_BIT
- PCIE_PHY_MAC_RESET
- PCIE_PHY_MAX_OFFSET
- PCIE_PHY_MPLL_MULTIPLIER_MASK
- PCIE_PHY_MPLL_MULTIPLIER_OVRD
- PCIE_PHY_MPLL_MULTIPLIER_SHIFT
- PCIE_PHY_MPLL_OVRD_IN_LO
- PCIE_PHY_PLL_A_CTRL1
- PCIE_PHY_PLL_A_CTRL2
- PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN
- PCIE_PHY_PLL_A_CTRL3
- PCIE_PHY_PLL_A_CTRL3_MMD_MASK
- PCIE_PHY_PLL_BIAS
- PCIE_PHY_PLL_CTRL1
- PCIE_PHY_PLL_CTRL2
- PCIE_PHY_PLL_CTRL2_CONST_SDM_EN
- PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK
- PCIE_PHY_PLL_CTRL2_PLL_SDM_EN
- PCIE_PHY_PLL_CTRL3
- PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN
- PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK
- PCIE_PHY_PLL_CTRL4
- PCIE_PHY_PLL_CTRL5
- PCIE_PHY_PLL_CTRL6
- PCIE_PHY_PLL_CTRL7
- PCIE_PHY_PLL_DIV_0
- PCIE_PHY_PLL_DIV_1
- PCIE_PHY_PLL_LOCKED
- PCIE_PHY_PLL_STATUS
- PCIE_PHY_REF_CLK
- PCIE_PHY_RESET
- PCIE_PHY_RSTB
- PCIE_PHY_RX1_A_CTRL
- PCIE_PHY_RX1_CDR
- PCIE_PHY_RX1_CTRL1
- PCIE_PHY_RX1_CTRL1_LOAD_EN
- PCIE_PHY_RX1_CTRL2
- PCIE_PHY_RX1_EI
- PCIE_PHY_RX_ASIC_OUT
- PCIE_PHY_RX_ASIC_OUT_VALID
- PCIE_PHY_SECTION
- PCIE_PHY_STAT
- PCIE_PHY_STAT_ACK
- PCIE_PHY_TRSV0_DRV_LVL
- PCIE_PHY_TRSV0_EMP_LVL
- PCIE_PHY_TRSV0_LVCC
- PCIE_PHY_TRSV0_PD_TSV
- PCIE_PHY_TRSV0_POWER
- PCIE_PHY_TRSV0_RXCDR
- PCIE_PHY_TRSV1_EMP_LVL
- PCIE_PHY_TRSV1_LVCC
- PCIE_PHY_TRSV1_PD_TSV
- PCIE_PHY_TRSV1_POWER
- PCIE_PHY_TRSV1_RXCDR
- PCIE_PHY_TRSV2_EMP_LVL
- PCIE_PHY_TRSV2_LVCC
- PCIE_PHY_TRSV2_PD_TSV
- PCIE_PHY_TRSV2_POWER
- PCIE_PHY_TRSV2_RXCDR
- PCIE_PHY_TRSV3_EMP_LVL
- PCIE_PHY_TRSV3_LVCC
- PCIE_PHY_TRSV3_PD_TSV
- PCIE_PHY_TRSV3_POWER
- PCIE_PHY_TRSV3_RXCDR
- PCIE_PHY_TRSVREG_RESET
- PCIE_PHY_TRSV_RESET
- PCIE_PHY_TX1_A_CTRL1
- PCIE_PHY_TX1_A_CTRL2
- PCIE_PHY_TX1_CTRL1
- PCIE_PHY_TX1_CTRL1_FORCE_EN
- PCIE_PHY_TX1_CTRL1_LOAD_EN
- PCIE_PHY_TX1_CTRL2
- PCIE_PHY_TX1_CTRL3
- PCIE_PHY_TX1_MOD1
- PCIE_PHY_TX1_MOD2
- PCIE_PHY_TX1_MOD3
- PCIE_PHY_TX2_A_CTRL1
- PCIE_PHY_TX2_A_CTRL2
- PCIE_PHY_TX2_CTRL1
- PCIE_PHY_TX2_CTRL1_LOAD_EN
- PCIE_PHY_TX2_CTRL2
- PCIE_PHY_TX2_MOD1
- PCIE_PHY_TX2_MOD2
- PCIE_PHY_TX2_MOD3
- PCIE_PIPEMUX_CFG_OFFSET
- PCIE_PIPEMUX_MASK
- PCIE_PIPEMUX_SELECT_STRAP
- PCIE_PIPEMUX_SHIFT
- PCIE_PIPE_ARES
- PCIE_PIPE_SRSTB
- PCIE_PIPE_STICKY_ARES
- PCIE_PLL_RECONF__RECONF_WAIT_MASK
- PCIE_PLL_RECONF__RECONF_WAIT__SHIFT
- PCIE_PLL_RECONF__RECONF_WRAPPER_MASK
- PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT
- PCIE_PLL_RECONF__SB_NEW_PORT_MASK
- PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT
- PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK
- PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT
- PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR
- PCIE_PL_CHK_REG_CHK_REG_COMPLETE
- PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS
- PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR
- PCIE_PL_CHK_REG_CHK_REG_START
- PCIE_PL_CHK_REG_CONTROL_STATUS
- PCIE_PL_CHK_REG_ERR_ADDR
- PCIE_PM_STATUS_0_PORT_0_4
- PCIE_PM_STATUS_7_0_EP1
- PCIE_PM_STATUS_7_0_EP2
- PCIE_PM_STATUS_7_0_EP3
- PCIE_PM_STATUS_7_0_EP4
- PCIE_PORTDRV_PM_OPS
- PCIE_PORT_CLK_EN
- PCIE_PORT_DATA
- PCIE_PORT_DATA__PCIE_DATA_MASK
- PCIE_PORT_DATA__PCIE_DATA__SHIFT
- PCIE_PORT_DEBUG0
- PCIE_PORT_DEBUG1
- PCIE_PORT_DEBUG1_LINK_IN_TRAINING
- PCIE_PORT_DEBUG1_LINK_UP
- PCIE_PORT_DEVICE_MAXSERVICES
- PCIE_PORT_INDEX
- PCIE_PORT_INDEX__PCIE_INDEX_MASK
- PCIE_PORT_INDEX__PCIE_INDEX__SHIFT
- PCIE_PORT_INT_EN
- PCIE_PORT_LINKUP
- PCIE_PORT_LINKUP_V2
- PCIE_PORT_LINK_CONTROL
- PCIE_PORT_LINK_CTRL_OFF
- PCIE_PORT_MAX_MSI_ENTRIES
- PCIE_PORT_PERST
- PCIE_PORT_SERVICE_AER
- PCIE_PORT_SERVICE_AER_SHIFT
- PCIE_PORT_SERVICE_BWNOTIF
- PCIE_PORT_SERVICE_BWNOTIF_SHIFT
- PCIE_PORT_SERVICE_DPC
- PCIE_PORT_SERVICE_DPC_SHIFT
- PCIE_PORT_SERVICE_HP
- PCIE_PORT_SERVICE_HP_SHIFT
- PCIE_PORT_SERVICE_PME
- PCIE_PORT_SERVICE_PME_SHIFT
- PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
- PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK
- PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
- PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
- PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK
- PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
- PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
- PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK
- PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
- PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
- PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK
- PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
- PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
- PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK
- PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
- PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
- PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK
- PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
- PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
- PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK
- PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
- PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
- PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK
- PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
- PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
- PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK
- PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
- PCIE_POR_RESET
- PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK
- PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT
- PCIE_PRBS_CLR__PRBS_CLR_MASK
- PCIE_PRBS_CLR__PRBS_CLR__SHIFT
- PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK
- PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT
- PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK
- PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT
- PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK
- PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT
- PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK
- PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT
- PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK
- PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT
- PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK
- PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT
- PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK
- PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT
- PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK
- PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT
- PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK
- PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT
- PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK
- PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT
- PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK
- PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT
- PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK
- PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT
- PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK
- PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT
- PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK
- PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT
- PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK
- PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT
- PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK
- PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT
- PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK
- PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT
- PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK
- PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT
- PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK
- PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT
- PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK
- PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT
- PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK
- PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT
- PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK
- PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT
- PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK
- PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT
- PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK
- PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT
- PCIE_PRBS_MISC__PRBS_EN_MASK
- PCIE_PRBS_MISC__PRBS_EN__SHIFT
- PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK
- PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT
- PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK
- PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT
- PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK
- PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT
- PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK
- PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT
- PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK
- PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT
- PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK
- PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT
- PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK
- PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT
- PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT_MASK
- PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT__SHIFT
- PCIE_PRI_CFG
- PCIE_PWR_ARES
- PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK
- PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK
- PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT
- PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK
- PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK
- PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT
- PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK
- PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK
- PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT
- PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK
- PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK
- PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT
- PCIE_PWR_BUDGET_DATA__PM_STATE_MASK
- PCIE_PWR_BUDGET_DATA__PM_STATE__MASK
- PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT
- PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK
- PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK
- PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT
- PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK
- PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK
- PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT
- PCIE_PWR_BUDGET_DATA__TYPE_MASK
- PCIE_PWR_BUDGET_DATA__TYPE__MASK
- PCIE_PWR_BUDGET_DATA__TYPE__SHIFT
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_PWR_GATER_BUSY
- PCIE_PWR_GATER_STATE
- PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
- PCIE_PWR_MGMT_L1_THRESH_4MS
- PCIE_PWR_MGMT_L1_THRESH_MSK
- PCIE_PWR_MGMT_THRESH
- PCIE_PWR_RESET
- PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK
- PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT
- PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK
- PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT
- PCIE_P_CNTL
- PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK
- PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT
- PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK
- PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT
- PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK
- PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT
- PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK
- PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT
- PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK
- PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT
- PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK
- PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT
- PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK
- PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT
- PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK
- PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT
- PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK
- PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT
- PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK
- PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT
- PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK
- PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT
- PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK
- PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT
- PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK
- PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT
- PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK
- PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT
- PCIE_P_CNTL__P_PWRDN_EN_MASK
- PCIE_P_CNTL__P_PWRDN_EN__SHIFT
- PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK
- PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT
- PCIE_P_CNTL__P_SYMALIGN_MODE_MASK
- PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT
- PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK
- PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT
- PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK
- PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT
- PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK
- PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT
- PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK
- PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT
- PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK
- PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT
- PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK
- PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT
- PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK
- PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT
- PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK
- PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT
- PCIE_RC_BAR_CONF
- PCIE_RC_CONFIG_BASE
- PCIE_RC_CONFIG_DCR
- PCIE_RC_CONFIG_DCR_CPLS_SHIFT
- PCIE_RC_CONFIG_DCR_CSPL_LIMIT
- PCIE_RC_CONFIG_DCR_CSPL_SHIFT
- PCIE_RC_CONFIG_DCSR
- PCIE_RC_CONFIG_DCSR_MPS_256
- PCIE_RC_CONFIG_DCSR_MPS_MASK
- PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2
- PCIE_RC_CONFIG_LCS
- PCIE_RC_CONFIG_LINK_CAP
- PCIE_RC_CONFIG_LINK_CAP_L0S
- PCIE_RC_CONFIG_NORMAL_BASE
- PCIE_RC_CONFIG_RID_CCR
- PCIE_RC_CONFIG_SCC_SHIFT
- PCIE_RC_CONFIG_THP_CAP
- PCIE_RC_CONFIG_THP_CAP_NEXT_MASK
- PCIE_RC_IMX6_MSI_CAP
- PCIE_RC_INT_A
- PCIE_RC_INT_B
- PCIE_RC_INT_C
- PCIE_RC_INT_D
- PCIE_RC_K2E
- PCIE_RC_K2G
- PCIE_RC_K2HK
- PCIE_RC_K2L
- PCIE_RC_LCR
- PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1
- PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2
- PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
- PCIE_RC_LCSR
- PCIE_RC_RP_ATS_BASE
- PCIE_RC_RTSTA
- PCIE_RC_SEND_PME_OFF
- PCIE_RDLH_LINK_UP
- PCIE_RD_DATA_PTR_Q0_Q1
- PCIE_REF
- PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5
- PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5
- PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5
- PCIE_REG_DBG_COMMON_SELECT_K2_E5
- PCIE_REG_DBG_COMMON_SHIFT_K2_E5
- PCIE_REG_DBG_DWORD_ENABLE
- PCIE_REG_DBG_FORCE_FRAME
- PCIE_REG_DBG_FORCE_VALID
- PCIE_REG_DBG_SELECT
- PCIE_REG_DBG_SHIFT
- PCIE_REG_PCIER_TL_HDR_FC_ST
- PCIE_RESERVED__PCIE_RESERVED_MASK
- PCIE_RESERVED__PCIE_RESERVED__SHIFT
- PCIE_RESERVED__RESERVED_MASK
- PCIE_RESERVED__RESERVED__SHIFT
- PCIE_RESET_DELAY
- PCIE_RESET_READY_POLL_MS
- PCIE_RESOURCE_DESC_TYPE_V0
- PCIE_RESOURCE_DESC_TYPE_V1
- PCIE_REVISION_ID
- PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK
- PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT
- PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK
- PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT
- PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK
- PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT
- PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK
- PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT
- PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT
- PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT
- PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT
- PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK
- PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT
- PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT
- PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT
- PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK
- PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT
- PCIE_RP_IB_ADDR0
- PCIE_RP_IB_ADDR1
- PCIE_RST_CTRL
- PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK
- PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT
- PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK
- PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT
- PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK
- PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT
- PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK
- PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT
- PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK
- PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT
- PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK
- PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT
- PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK
- PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT
- PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK
- PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK
- PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK
- PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT
- PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK
- PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT
- PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK
- PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT
- PCIE_RX_AD__RX_RC_DROP_VDM0_MASK
- PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT
- PCIE_RX_AD__RX_RC_DROP_VDM1_MASK
- PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT
- PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK
- PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT
- PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK
- PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT
- PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK
- PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT
- PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK
- PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT
- PCIE_RX_AD__RX_RC_UR_VDM0_MASK
- PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT
- PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK
- PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT
- PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK
- PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT
- PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK
- PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT
- PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK
- PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT
- PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK
- PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT
- PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK
- PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT
- PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK
- PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT
- PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT
- PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK
- PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT
- PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK
- PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT
- PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK
- PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT
- PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK
- PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT
- PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK
- PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT
- PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK
- PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT
- PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK
- PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT
- PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK
- PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT
- PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK
- PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT
- PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK
- PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT
- PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK
- PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT
- PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK
- PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT
- PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
- PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
- PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
- PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
- PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
- PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK
- PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK
- PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK
- PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK
- PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT
- PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
- PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
- PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK
- PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
- PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
- PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
- PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
- PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK
- PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- PCIE_RX_CNTL__RX_TPH_DIS_MASK
- PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK
- PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK
- PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK
- PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK
- PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK
- PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT
- PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK
- PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT
- PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK
- PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT
- PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK
- PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT
- PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK
- PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT
- PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK
- PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT
- PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK
- PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT
- PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK
- PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT
- PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK
- PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT
- PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK
- PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT
- PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK
- PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT
- PCIE_S
- PCIE_SATA0_SEL_PCIE
- PCIE_SATA0_SEL_SATA
- PCIE_SATA1_SEL_PCIE
- PCIE_SATA1_SEL_SATA
- PCIE_SATA2_SEL_PCIE
- PCIE_SATA2_SEL_SATA
- PCIE_SATA_CFG
- PCIE_SATA_SEL_PCIE
- PCIE_SATA_SEL_SATA
- PCIE_SCRATCH_0_REG
- PCIE_SCRATCH_10_REG
- PCIE_SCRATCH_11_REG
- PCIE_SCRATCH_12_REG
- PCIE_SCRATCH_13_REG
- PCIE_SCRATCH_14_REG
- PCIE_SCRATCH_15_REG
- PCIE_SCRATCH_1_REG
- PCIE_SCRATCH_2_REG
- PCIE_SCRATCH_3_REG
- PCIE_SCRATCH_4_REG
- PCIE_SCRATCH_5_REG
- PCIE_SCRATCH_6_REG
- PCIE_SCRATCH_7_REG
- PCIE_SCRATCH_8_REG
- PCIE_SCRATCH_9_REG
- PCIE_SCRATCH__PCIE_SCRATCH_MASK
- PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK
- PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT
- PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK
- PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT
- PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK
- PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT
- PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK
- PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT
- PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK
- PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT
- PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK
- PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT
- PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK
- PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT
- PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK
- PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT
- PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK
- PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT
- PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK
- PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT
- PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK
- PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT
- PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK
- PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT
- PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK
- PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT
- PCIE_SDP_CTRL__SDP_UNIT_ID_MASK
- PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT
- PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK
- PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT
- PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK
- PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT
- PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS_MASK
- PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS__SHIFT
- PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN_MASK
- PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN__SHIFT
- PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS_MASK
- PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS__SHIFT
- PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS_MASK
- PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS__SHIFT
- PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS_MASK
- PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS__SHIFT
- PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS_MASK
- PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS__SHIFT
- PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK
- PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT
- PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK
- PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK
- PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK
- PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_SEM0_LOCK
- PCIE_SEM0_UNLOCK
- PCIE_SEM1_LOCK
- PCIE_SEM1_UNLOCK
- PCIE_SEM2_LOCK
- PCIE_SEM2_UNLOCK
- PCIE_SEM3_LOCK
- PCIE_SEM3_UNLOCK
- PCIE_SEM4_LOCK
- PCIE_SEM4_UNLOCK
- PCIE_SEM5_LOCK
- PCIE_SEM5_UNLOCK
- PCIE_SEM6_LOCK
- PCIE_SEM6_UNLOCK
- PCIE_SEM7_LOCK
- PCIE_SEM7_UNLOCK
- PCIE_SEM_LOCK
- PCIE_SEM_UNLOCK
- PCIE_SERDES0
- PCIE_SERDES1
- PCIE_SETUP_FUNCTION
- PCIE_SETUP_FUNCTION2
- PCIE_SHARED_RESET
- PCIE_SN_WINDOW_REG
- PCIE_SOC_WAKE_ADDRESS
- PCIE_SOC_WAKE_RESET
- PCIE_SOC_WAKE_V_MASK
- PCIE_SPEED2MBS_ENC
- PCIE_SPEED2STR
- PCIE_SPEED_16_0GT
- PCIE_SPEED_2_5GT
- PCIE_SPEED_32_0GT
- PCIE_SPEED_5_0GT
- PCIE_SPEED_8_0GT
- PCIE_SPMU_MAX_OFFSET
- PCIE_SPMU_SECTION
- PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK
- PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK
- PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK
- PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT
- PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK
- PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK
- PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT
- PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT
- PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK
- PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT
- PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK
- PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK
- PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT
- PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK
- PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK
- PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT
- PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK
- PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK
- PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT
- PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK
- PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK
- PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT
- PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK
- PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK
- PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT
- PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK
- PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK
- PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT
- PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK
- PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK
- PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT
- PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK
- PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK
- PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK
- PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK
- PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT
- PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK
- PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK
- PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK
- PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT
- PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK
- PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK
- PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT
- PCIE_STATUS_COMMAND
- PCIE_STAT_BUS
- PCIE_STAT_BUS_MASK
- PCIE_STAT_BUS_OFFS
- PCIE_STAT_DEV
- PCIE_STAT_DEV_MASK
- PCIE_STAT_DEV_OFFS
- PCIE_STAT_LINK_DOWN
- PCIE_STAT_OFF
- PCIE_STICKY_RESET
- PCIE_STM_MAX_OFFSET
- PCIE_STM_SECTION
- PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
- PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
- PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK
- PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT
- PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK
- PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT
- PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK
- PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT
- PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK
- PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT
- PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK
- PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT
- PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK
- PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ACS_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ACS_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_AER_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_AER_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_64BIT_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ATOMIC_ROUTING_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ATS_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ATS_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_BAR_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_BAR_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_CPL_ABORT_ERR_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_DPA_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_DPA_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_DSN_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_DSN_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ECRC_CHECK_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_ECRC_GEN_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_LEGACY_DEVICE_TYPE_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_MSI_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_MSI_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP_MASK
- PCIE_STRAP_F1__STRAP_F1_MSI_MULTI_CAP__SHIFT
- PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP_MASK
- PCIE_STRAP_F1__STRAP_F1_MSI_PERVECTOR_MASK_CAP__SHIFT
- PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_PAGE_REQ_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_PASID_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_PASID_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL_MASK
- PCIE_STRAP_F1__STRAP_F1_POISONED_ADVISORY_NONFATAL__SHIFT
- PCIE_STRAP_F1__STRAP_F1_PWR_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_PWR_EN__SHIFT
- PCIE_STRAP_F1__STRAP_F1_VC_EN_MASK
- PCIE_STRAP_F1__STRAP_F1_VC_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ACS_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ACS_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_AER_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_AER_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_64BIT_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ATOMIC_ROUTING_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ATS_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ATS_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_BAR_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_BAR_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_CPL_ABORT_ERR_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_DPA_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_DPA_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_DSN_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_DSN_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ECRC_CHECK_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_ECRC_GEN_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_LEGACY_DEVICE_TYPE_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_MSI_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_MSI_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP_MASK
- PCIE_STRAP_F2__STRAP_F2_MSI_MULTI_CAP__SHIFT
- PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP_MASK
- PCIE_STRAP_F2__STRAP_F2_MSI_PERVECTOR_MASK_CAP__SHIFT
- PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_PAGE_REQ_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_PASID_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_PASID_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL_MASK
- PCIE_STRAP_F2__STRAP_F2_POISONED_ADVISORY_NONFATAL__SHIFT
- PCIE_STRAP_F2__STRAP_F2_PWR_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_PWR_EN__SHIFT
- PCIE_STRAP_F2__STRAP_F2_VC_EN_MASK
- PCIE_STRAP_F2__STRAP_F2_VC_EN__SHIFT
- PCIE_STRAP_F3__RESERVED_MASK
- PCIE_STRAP_F3__RESERVED__SHIFT
- PCIE_STRAP_F4__RESERVED_MASK
- PCIE_STRAP_F4__RESERVED__SHIFT
- PCIE_STRAP_F5__RESERVED_MASK
- PCIE_STRAP_F5__RESERVED__SHIFT
- PCIE_STRAP_F6__RESERVED_MASK
- PCIE_STRAP_F6__RESERVED__SHIFT
- PCIE_STRAP_F7__RESERVED_MASK
- PCIE_STRAP_F7__RESERVED__SHIFT
- PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK
- PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT
- PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK
- PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT
- PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK
- PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT
- PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK
- PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT
- PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK
- PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT
- PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK
- PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT
- PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
- PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
- PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK
- PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT
- PCIE_STRAP_MISC__STRAP_16GT_EN_MASK
- PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK
- PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT
- PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
- PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_DLF_EN_MASK
- PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK
- PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK
- PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT
- PCIE_STRAP_MISC__STRAP_FLR_EN_MASK
- PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK
- PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_LINK_CONFIG_MASK
- PCIE_STRAP_MISC__STRAP_LINK_CONFIG__SHIFT
- PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK
- PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH_MASK
- PCIE_STRAP_MISC__STRAP_MAX_PASID_WIDTH__SHIFT
- PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED_MASK
- PCIE_STRAP_MISC__STRAP_PASID_EXE_PERMISSION_SUPPORTED__SHIFT
- PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_MASK
- PCIE_STRAP_MISC__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED__SHIFT
- PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED_MASK
- PCIE_STRAP_MISC__STRAP_PASID_PRIV_MODE_SUPPORTED__SHIFT
- PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK
- PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT
- PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK
- PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN_MASK
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_EN__SHIFT
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR_MASK
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_BIR__SHIFT
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET_MASK
- PCIE_STRAP_MSIX__STRAP_F0_MSIX_TABLE_OFFSET__SHIFT
- PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK
- PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT
- PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK
- PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT
- PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK
- PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT
- PCIE_STRFMR1
- PCIE_SUBCTRL_SYS_STATE4_REG
- PCIE_SUBSYS_VEN_ID_REG
- PCIE_SYS_CFG
- PCIE_SYS_CFG_V2
- PCIE_SYS_CTRL0
- PCIE_SYS_CTRL1
- PCIE_SYS_CTRL13
- PCIE_SYS_CTRL15
- PCIE_SYS_CTRL16
- PCIE_SYS_CTRL17
- PCIE_SYS_CTRL7
- PCIE_SYS_STAT0
- PCIE_SYS_STAT4
- PCIE_SYS_STATE4
- PCIE_SoC_INT_ROUTER_STATUS0_REG
- PCIE_SoC_INT_ROUTER_STATUS1_REG
- PCIE_SoC_INT_ROUTER_STATUS2_REG
- PCIE_SoC_INT_ROUTER_STATUS3_REG
- PCIE_TGT_SPLIT_CHICKEN
- PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
- PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK
- PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
- PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
- PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK
- PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
- PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
- PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK
- PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
- PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
- PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK
- PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK
- PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT
- PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK
- PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK
- PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT
- PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK
- PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK
- PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_TRANSACTION_CFG
- PCIE_TRANS_CFG_1SHOT_MSI
- PCIE_TRANS_CFG_LOM
- PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK
- PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK
- PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT
- PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT
- PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK
- PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT
- PCIE_TX_CNTL3__MCA_CLKGATE_DIS_MASK
- PCIE_TX_CNTL3__MCA_CLKGATE_DIS__SHIFT
- PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN_MASK
- PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN__SHIFT
- PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE_MASK
- PCIE_TX_CNTL3__TX_ATOMIC_ORD_HASH_MODE__SHIFT
- PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN_MASK
- PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN__SHIFT
- PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN_MASK
- PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN__SHIFT
- PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS_MASK
- PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS__SHIFT
- PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN_MASK
- PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN__SHIFT
- PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE_MASK
- PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE__SHIFT
- PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS_MASK
- PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS__SHIFT
- PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS_MASK
- PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS__SHIFT
- PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT_MASK
- PCIE_TX_CNTL_2__TX_SKID_CREDIT_LIMIT__SHIFT
- PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN_MASK
- PCIE_TX_CNTL_2__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT
- PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK
- PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT
- PCIE_TX_CNTL__TX_CPL_PASS_P_MASK
- PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT
- PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK
- PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT
- PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK
- PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT
- PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK
- PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT
- PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK
- PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT
- PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK
- PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT
- PCIE_TX_CNTL__TX_NP_PASS_P_MASK
- PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT
- PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK
- PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT
- PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
- PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
- PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
- PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
- PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK
- PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT
- PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK
- PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT
- PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK
- PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT
- PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK
- PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT
- PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK
- PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT
- PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK
- PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT
- PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK
- PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK
- PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT
- PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK
- PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT
- PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK
- PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT
- PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK
- PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT
- PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK
- PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT
- PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK
- PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT
- PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK
- PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK
- PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT
- PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK
- PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_CPL__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_IDO_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_RO_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F1_SNR_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_CPL__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_IDO_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_RO_OVERRIDE_P__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_NP__SHIFT
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P_MASK
- PCIE_TX_F1_F2_ATTR_CNTL__TX_F2_SNR_OVERRIDE_P__SHIFT
- PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK
- PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT
- PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK
- PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT
- PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK
- PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT
- PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK
- PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK
- PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT
- PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK
- PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT
- PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK
- PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT
- PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK
- PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT
- PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK
- PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT
- PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK
- PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK
- PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT
- PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
- PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT
- PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT
- PCIE_TX_SEQ__TX_ACKD_SEQ_MASK
- PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT
- PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK
- PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT
- PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK
- PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT
- PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK
- PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT
- PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK
- PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT
- PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK
- PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT
- PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK
- PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT
- PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK
- PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT
- PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK
- PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT
- PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK
- PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT
- PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK
- PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT
- PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK
- PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT
- PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK
- PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT
- PCIE_TX_STATUS__TX_MST_MEM_READY_MASK
- PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT
- PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK
- PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT
- PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK
- PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT
- PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK
- PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT
- PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK
- PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK
- PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT
- PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK
- PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT
- PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK
- PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK
- PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT
- PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK
- PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT
- PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK
- PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT
- PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
- PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK
- PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
- PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK
- PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
- PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK
- PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
- PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK
- PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
- PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK
- PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
- PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK
- PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
- PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK
- PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
- PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
- PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK
- PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
- PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK
- PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
- PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
- PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
- PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK
- PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
- PCIE_UNMASK_ALL_IRQS
- PCIE_V
- PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK
- PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK
- PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK
- PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK
- PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK
- PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK
- PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
- PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK
- PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
- PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK
- PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
- PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK
- PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK
- PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK
- PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK
- PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK
- PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK
- PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK
- PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK
- PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
- PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK
- PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
- PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK
- PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
- PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK
- PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK
- PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_VDDC_CONTROL_GPIO_PINID
- PCIE_VDM_CNTL2__AMDVDM2SMUEn_MASK
- PCIE_VDM_CNTL2__AMDVDM2SMUEn__SHIFT
- PCIE_VDM_CNTL2__MCTPMasterID_MASK
- PCIE_VDM_CNTL2__MCTPMasterID__SHIFT
- PCIE_VDM_CNTL2__MCTPMasterValid_MASK
- PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT
- PCIE_VDM_CNTL2__MCTPT2SMUEn_MASK
- PCIE_VDM_CNTL2__MCTPT2SMUEn__SHIFT
- PCIE_VDM_CNTL2__OtherVDM2SMUEn_MASK
- PCIE_VDM_CNTL2__OtherVDM2SMUEn__SHIFT
- PCIE_VDM_CNTL2__VdmP2pMode_MASK
- PCIE_VDM_CNTL2__VdmP2pMode__SHIFT
- PCIE_VDM_CNTL3__APMTPMasterID_MASK
- PCIE_VDM_CNTL3__APMTPMasterID__SHIFT
- PCIE_VDM_CNTL3__APMTPMasterValid_MASK
- PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT
- PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK
- PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT
- PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK
- PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT
- PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK
- PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT
- PCIE_VENDORID_MASK
- PCIE_VENDOR_ID_MARVELL
- PCIE_VENDOR_ID_QUANTENNA
- PCIE_VENDOR_ID_V2_MARVELL
- PCIE_VENDOR_ID_WCH
- PCIE_VENDOR_REGS_OFFSET
- PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
- PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK
- PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
- PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
- PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK
- PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK
- PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__CMD_CONTROL__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__FCN_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC__NXT_FCN_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS__CMD_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CNTXT_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT__GPU_IDLE_LATENCY__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__LOWER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5__UPPER__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__AUTO_SCH_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__DISP_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GPU_INFO_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0__DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1__DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2__DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3__DATA__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS__VM_INIT_STATUS__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK
- PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK
- PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
- PCIE_VERSION
- PCIE_VNDR_CAP_ID_FIXED_BAR
- PCIE_WAKE_LATE_US
- PCIE_WAKE_TIMEOUT
- PCIE_WIN04_BASE_OFF
- PCIE_WIN04_CTRL_OFF
- PCIE_WIN04_REMAP_OFF
- PCIE_WIN5_BASE_OFF
- PCIE_WIN5_CTRL_OFF
- PCIE_WIN5_REMAP_OFF
- PCIE_WM_EP
- PCIE_WM_LEGACY
- PCIE_WM_RC
- PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT
- PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK
- PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT
- PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK
- PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT
- PCIE_WRAP_MAX_OFFSET
- PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY_MASK
- PCIE_WRAP_MISC__STRAP_BIF_HOLD_TRAINING_STICKY__SHIFT
- PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK
- PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT
- PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK
- PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT
- PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK
- PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT
- PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK
- PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT
- PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK
- PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT
- PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK
- PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT
- PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK
- PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT
- PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK
- PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT
- PCIE_WRAP_SECTION
- PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK
- PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT
- PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK
- PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT
- PCIE_WR_DATA_PTR_Q0_Q1
- PCIE_XMLH_LINK_UP
- PCIErr
- PCIF
- PCIFRAME_VSYNC_MARK
- PCIGSCR
- PCIGSCR_PE
- PCIGSCR_PEE
- PCIGSCR_RESET
- PCIGSCR_SE
- PCIGSCR_SEE
- PCIGSCR_XCLKBIN
- PCII0
- PCII1
- PCII2
- PCII3
- PCII4
- PCII5
- PCII56789
- PCII6
- PCII7
- PCII8
- PCII9
- PCIIA
- PCIIACK_BASE
- PCIIACK_SIZE
- PCIICR
- PCIIDR
- PCIINIT0
- PCIINT0
- PCIINT2
- PCIINTA
- PCIINTB
- PCIINTC
- PCIINTD
- PCIINTE
- PCIINTF
- PCIINTREG
- PCIIOC_BASE
- PCIIOC_CONTROLLER
- PCIIOC_MMAP_IS_IO
- PCIIOC_MMAP_IS_MEM
- PCIIOC_WRITE_COMBINE
- PCIIRQ
- PCIISR
- PCIIW0BTAR
- PCIIW1BTAR
- PCIIW2BTAR
- PCIIWCR
- PCIIWCR_W0_E
- PCIIWCR_W0_IO
- PCIIWCR_W0_MEM
- PCIIWCR_W0_MRD
- PCIIWCR_W0_MRDL
- PCIIWCR_W0_MRDM
- PCIIWCR_W1_E
- PCIIWCR_W1_IO
- PCIIWCR_W1_MEM
- PCIIWCR_W1_MRD
- PCIIWCR_W1_MRDL
- PCIIWCR_W1_MRDM
- PCIL0_PMM0LA
- PCIL0_PMM0MA
- PCIL0_PMM0PCIHA
- PCIL0_PMM0PCILA
- PCIL0_PMM1LA
- PCIL0_PMM1MA
- PCIL0_PMM1PCIHA
- PCIL0_PMM1PCILA
- PCIL0_PMM2LA
- PCIL0_PMM2MA
- PCIL0_PMM2PCIHA
- PCIL0_PMM2PCILA
- PCIL0_PTM1LA
- PCIL0_PTM1MS
- PCIL0_PTM2LA
- PCIL0_PTM2MS
- PCILBA_SIZE_MASK
- PCILBA_SIZE_SHFT
- PCILYNX_MAX_MEMORY
- PCILYNX_MAX_REGISTER
- PCIMAILREG
- PCIMAXFREQ
- PCIMBA1REG
- PCIMBA2REG
- PCIMCR_MRSET_OFF
- PCIMCR_RFSH_OFF
- PCIMDAS_8254_BASE
- PCIMDAS_8255_BASE
- PCIMDAS_AI_REG
- PCIMDAS_AI_SOFTTRIG_REG
- PCIMDAS_AO_REG
- PCIMDAS_BURST_BME
- PCIMDAS_BURST_CONV_EN
- PCIMDAS_BURST_REG
- PCIMDAS_CONV_STATUS_EOA
- PCIMDAS_CONV_STATUS_EOB
- PCIMDAS_CONV_STATUS_EOC
- PCIMDAS_CONV_STATUS_FHF
- PCIMDAS_CONV_STATUS_FNE
- PCIMDAS_CONV_STATUS_OVERRUN
- PCIMDAS_CONV_STATUS_REG
- PCIMDAS_DI_DO_REG
- PCIMDAS_GAIN_REG
- PCIMDAS_IRQ_EOA
- PCIMDAS_IRQ_EOA_INT_SEL
- PCIMDAS_IRQ_INT
- PCIMDAS_IRQ_INTE
- PCIMDAS_IRQ_INTSEL
- PCIMDAS_IRQ_INTSEL_EOB
- PCIMDAS_IRQ_INTSEL_EOC
- PCIMDAS_IRQ_INTSEL_FHF_EOA
- PCIMDAS_IRQ_INTSEL_FNE
- PCIMDAS_IRQ_OVERRUN
- PCIMDAS_IRQ_REG
- PCIMDAS_MUX
- PCIMDAS_MUX_REG
- PCIMDAS_PACER_EXT_PACER_POL
- PCIMDAS_PACER_GATE_EN
- PCIMDAS_PACER_GATE_LATCH
- PCIMDAS_PACER_GATE_POL
- PCIMDAS_PACER_GATE_STATUS
- PCIMDAS_PACER_REG
- PCIMDAS_PACER_SRC
- PCIMDAS_PACER_SRC_EXT
- PCIMDAS_PACER_SRC_INT
- PCIMDAS_PACER_SRC_MASK
- PCIMDAS_PACER_SRC_POLLED
- PCIMDAS_RESIDUE_LSB_REG
- PCIMDAS_RESIDUE_MSB_REG
- PCIMDAS_STATUS_CLK
- PCIMDAS_STATUS_EOC
- PCIMDAS_STATUS_MUX
- PCIMDAS_STATUS_REG
- PCIMDAS_STATUS_TO_CURR_MUX
- PCIMDAS_STATUS_UB
- PCIMDAS_USER_CNTR_CTR1_CLK_SEL
- PCIMDAS_USER_CNTR_REG
- PCIMDDA_8255_BASE_REG
- PCIMDDA_DA_CHAN
- PCIMEM_ARBITRATION
- PCIMEM_ARBITRATION_CRT_MASK
- PCIMEM_ARBITRATION_CRT_OFF
- PCIMEM_ARBITRATION_CRT_PRIORITY_1
- PCIMEM_ARBITRATION_CRT_PRIORITY_2
- PCIMEM_ARBITRATION_CRT_PRIORITY_3
- PCIMEM_ARBITRATION_CRT_PRIORITY_4
- PCIMEM_ARBITRATION_CRT_PRIORITY_5
- PCIMEM_ARBITRATION_CRT_PRIORITY_6
- PCIMEM_ARBITRATION_CRT_PRIORITY_7
- PCIMEM_ARBITRATION_DMA_MASK
- PCIMEM_ARBITRATION_DMA_OFF
- PCIMEM_ARBITRATION_DMA_PRIORITY_1
- PCIMEM_ARBITRATION_DMA_PRIORITY_2
- PCIMEM_ARBITRATION_DMA_PRIORITY_3
- PCIMEM_ARBITRATION_DMA_PRIORITY_4
- PCIMEM_ARBITRATION_DMA_PRIORITY_5
- PCIMEM_ARBITRATION_DMA_PRIORITY_6
- PCIMEM_ARBITRATION_DMA_PRIORITY_7
- PCIMEM_ARBITRATION_PANEL_MASK
- PCIMEM_ARBITRATION_PANEL_OFF
- PCIMEM_ARBITRATION_PANEL_PRIORITY_1
- PCIMEM_ARBITRATION_PANEL_PRIORITY_2
- PCIMEM_ARBITRATION_PANEL_PRIORITY_3
- PCIMEM_ARBITRATION_PANEL_PRIORITY_4
- PCIMEM_ARBITRATION_PANEL_PRIORITY_5
- PCIMEM_ARBITRATION_PANEL_PRIORITY_6
- PCIMEM_ARBITRATION_PANEL_PRIORITY_7
- PCIMEM_ARBITRATION_ROTATE
- PCIMEM_ARBITRATION_VGA_MASK
- PCIMEM_ARBITRATION_VGA_OFF
- PCIMEM_ARBITRATION_VGA_PRIORITY_1
- PCIMEM_ARBITRATION_VGA_PRIORITY_2
- PCIMEM_ARBITRATION_VGA_PRIORITY_3
- PCIMEM_ARBITRATION_VGA_PRIORITY_4
- PCIMEM_ARBITRATION_VGA_PRIORITY_5
- PCIMEM_ARBITRATION_VGA_PRIORITY_6
- PCIMEM_ARBITRATION_VGA_PRIORITY_7
- PCIMEM_ARBITRATION_VIDEO_MASK
- PCIMEM_ARBITRATION_VIDEO_OFF
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_1
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_2
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_3
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_4
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_5
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_6
- PCIMEM_ARBITRATION_VIDEO_PRIORITY_7
- PCIMEM_ARBITRATION_ZVPORT0_MASK
- PCIMEM_ARBITRATION_ZVPORT0_OFF
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6
- PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7
- PCIMEM_ARBITRATION_ZVPORT1_MASK
- PCIMEM_ARBITRATION_ZVPORT1_OFF
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6
- PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7
- PCIMEM_BASE
- PCIMEM_SIZE
- PCIMINFREQ
- PCIMIOAWREG
- PCIMMAW1REG
- PCIMMAW2REG
- PCIMT_ASIC_ID
- PCIMT_AUTO_PO_DIS
- PCIMT_AUTO_PO_EN
- PCIMT_CACHECONF
- PCIMT_CLRPOFF
- PCIMT_CLR_TEMP
- PCIMT_CONFIG_ADDRESS
- PCIMT_CONFIG_DATA
- PCIMT_CSITPEND
- PCIMT_CSLED
- PCIMT_CSMAPISA
- PCIMT_CSMSR
- PCIMT_CSRSTBP
- PCIMT_CSSWITCH
- PCIMT_CSTIMER
- PCIMT_CSWCSM
- PCIMT_DMAACCESS
- PCIMT_DMAHIT
- PCIMT_ECCREG
- PCIMT_EISA_BASE
- PCIMT_ERRADDR
- PCIMT_ERRSTATUS
- PCIMT_EXMSR
- PCIMT_INT_ACKNOWLEDGE
- PCIMT_INVSPACE
- PCIMT_IOADTIMEOUT1
- PCIMT_IOADTIMEOUT2
- PCIMT_IOMEMCONF
- PCIMT_IOMMU
- PCIMT_IRQSEL
- PCIMT_IRQ_BUTTON
- PCIMT_IRQ_EISA
- PCIMT_IRQ_EISA_NMI
- PCIMT_IRQ_ETHERNET
- PCIMT_IRQ_INT2
- PCIMT_IRQ_INTA
- PCIMT_IRQ_INTB
- PCIMT_IRQ_INTC
- PCIMT_IRQ_INTD
- PCIMT_IRQ_POWER_OFF
- PCIMT_IRQ_SCSI
- PCIMT_IRQ_TEMPERATURE
- PCIMT_ITPEND
- PCIMT_KEYBOARD_IRQ
- PCIMT_PCI_CONF
- PCIMT_PIA_DATAIN
- PCIMT_PIA_DATAOUT
- PCIMT_PIA_OE
- PCIMT_PWDN
- PCIMT_SOFT_RESET
- PCIMT_SYNDROME
- PCIMT_TESTMEM
- PCIMT_UCONF
- PCIMT_UNUSED1
- PCIMT_UNUSED2
- PCIMUX_FULL
- PCIMUX_KEY
- PCIMUX_SINGLE
- PCIM_BIT_LEN
- PCIM_CMD_BUSMASTEREN
- PCIM_CMD_MEMEN
- PCIM_CMD_MWRICEN
- PCIM_CMD_PERRESPEN
- PCIM_CMD_PORTEN
- PCIM_CMD_SERRESPEN
- PCIM_H_EA
- PCIM_H_IA_FIX
- PCIM_H_IA_RR
- PCIM_IOMAP_MAX
- PCIM_MFDEV
- PCIM_SHFT
- PCIMaster
- PCIMulRW
- PCINAME
- PCIO_BASE
- PCIO_BASE_b
- PCIO_BASE_l
- PCIO_BASE_w
- PCIPAR
- PCIPCI_ALIMAGIK
- PCIPCI_FAIL
- PCIPCI_NATOMA
- PCIPCI_TRITON
- PCIPCI_VIAETBF
- PCIPCI_VSFX
- PCIPDR
- PCIPM
- PCIRDCR
- PCIRECONTREG
- PCIRER
- PCIRFAR
- PCIRFCR
- PCIRFDR
- PCIRFRPR
- PCIRFSR
- PCIRFWPR
- PCIRNAR
- PCIRPSR
- PCIRSAR
- PCIRSR
- PCIRST
- PCIRSTB
- PCIRTCR
- PCIR_BIST
- PCIR_CACHELNSZ
- PCIR_CAP_PTR
- PCIR_CLASS
- PCIR_COMMAND
- PCIR_DEVICE
- PCIR_DEVVENDOR
- PCIR_DSXG_CTRL
- PCIR_DSXG_ELEGACY
- PCIR_DSXG_FMBASE
- PCIR_DSXG_JOYBASE
- PCIR_DSXG_LEGACY
- PCIR_DSXG_MPU401BASE
- PCIR_DSXG_PWRCTRL1
- PCIR_DSXG_PWRCTRL2
- PCIR_DSXG_SBBASE
- PCIR_HEADERTYPE
- PCIR_LATTIMER
- PCIR_MAPS
- PCIR_PROGIF
- PCIR_REVID
- PCIR_STATUS
- PCIR_SUBCLASS
- PCIR_SUBDEV_0
- PCIR_SUBVEND_0
- PCIR_VENDOR
- PCIReg
- PCIRetry
- PCISCR
- PCISERR
- PCISH5_ICR_AINT
- PCISH5_ICR_AINTM
- PCISH5_ICR_AIR
- PCISH5_ICR_BMIR
- PCISH5_ICR_CIR
- PCISH5_ICR_CR
- PCISH5_ICR_CSCR0
- PCISH5_ICR_CSCR1
- PCISH5_ICR_CSR_CMD
- PCISH5_ICR_CSR_DID
- PCISH5_ICR_CSR_IBAR0
- PCISH5_ICR_CSR_MBAR0
- PCISH5_ICR_CSR_MBAR1
- PCISH5_ICR_CSR_STATUS
- PCISH5_ICR_CSR_VID
- PCISH5_ICR_INT
- PCISH5_ICR_INTM
- PCISH5_ICR_IOBMR
- PCISH5_ICR_IOBR
- PCISH5_ICR_LAR0
- PCISH5_ICR_LAR1
- PCISH5_ICR_LSR0
- PCISH5_ICR_LSR1
- PCISH5_ICR_MBMR
- PCISH5_ICR_MBR
- PCISH5_ICR_PAR
- PCISH5_ICR_PDR
- PCISH5_ICR_PINT
- PCISH5_ICR_PINTM
- PCISH5_ICR_REG
- PCISH5_IO_SIZCONV
- PCISH5_MEM_SIZCONV
- PCISH5_PID
- PCISH5_VCR_STATUS
- PCISH5_VCR_VERSION
- PCISH5_VID
- PCISID
- PCISLOT_64_BIT_OPERATION
- PCISLOT_64_BIT_SUPPORTED
- PCISLOT_66_MHZ_OPERATION
- PCISLOT_66_MHZ_SUPPORTED
- PCISLOT_ADAPTER_PRESENT
- PCISLOT_ADD_SUPPORTED
- PCISLOT_INTERLOCK_CLOSED
- PCISLOT_INTERLOCK_SUPPORTED
- PCISLOT_IRQ
- PCISLOT_POWERED
- PCISLOT_REPLACE_SUPPORTED
- PCISTATE_ALLOW_APE_CTLSPC_WR
- PCISTATE_ALLOW_APE_PSPACE_WR
- PCISTATE_ALLOW_APE_SHMEM_WR
- PCISTATE_BUS_32BIT
- PCISTATE_BUS_SPEED_HIGH
- PCISTATE_CONV_PCI_MODE
- PCISTATE_FLAT_VIEW
- PCISTATE_FORCE_RESET
- PCISTATE_INT_NOT_ACTIVE
- PCISTATE_RETRY_SAME_DMA
- PCISTATE_ROM_ENABLE
- PCISTATE_ROM_RETRY_ENABLE
- PCISTIKY
- PCISTUB_DRIVER_NAME
- PCITAW1REG
- PCITAW2REG
- PCITBATR0
- PCITBATR0_E
- PCITBATR1
- PCITBATR1_E
- PCITCR
- PCITC_DTIMER_VAL
- PCITC_RTIMER_VAL
- PCITDCR
- PCITER
- PCITEST_BAR
- PCITEST_COPY
- PCITEST_GET_IRQTYPE
- PCITEST_LEGACY_IRQ
- PCITEST_MSI
- PCITEST_MSIX
- PCITEST_READ
- PCITEST_SET_IRQTYPE
- PCITEST_WRITE
- PCITFAR
- PCITFCR
- PCITFDR
- PCITFRPR
- PCITFSR
- PCITFWPR
- PCITLWR
- PCITNAR
- PCITPSR
- PCITRDYVREG
- PCITSAR
- PCITSR
- PCITTCR
- PCIT_IRQ_ETHERNET
- PCIT_IRQ_INTA
- PCIT_IRQ_INTB
- PCIT_IRQ_INTC
- PCIT_IRQ_INTD
- PCIT_IRQ_SCSI0
- PCIT_IRQ_SCSI1
- PCIU_BASE
- PCIU_CLOCK
- PCIU_CONFIG_DONE
- PCIU_SIZE
- PCIW5
- PCIX0_BAR0H
- PCIX0_BAR0L
- PCIX0_BAR1
- PCIX0_BAR2H
- PCIX0_BAR2L
- PCIX0_BAR3
- PCIX0_BIST
- PCIX0_BRDGOPT1
- PCIX0_BRDGOPT2
- PCIX0_CACHELS
- PCIX0_CAP
- PCIX0_CAPID
- PCIX0_CID
- PCIX0_CISPTR
- PCIX0_CLS
- PCIX0_CMD
- PCIX0_COMMAND
- PCIX0_DEVID
- PCIX0_EROMBA
- PCIX0_ERREN
- PCIX0_ERRSTS
- PCIX0_HDTYPE
- PCIX0_IDR
- PCIX0_IM
- PCIX0_INTLN
- PCIX0_INTPN
- PCIX0_LATTIM
- PCIX0_MAXLTNCY
- PCIX0_MINGNT
- PCIX0_MSGIH
- PCIX0_MSGIL
- PCIX0_MSGOH
- PCIX0_MSGOL
- PCIX0_NIPTR
- PCIX0_OMCAPID
- PCIX0_OMMA
- PCIX0_OMMC
- PCIX0_OMMDATA
- PCIX0_OMMEOI
- PCIX0_OMMUA
- PCIX0_OMNIPTR
- PCIX0_PIM0LAH
- PCIX0_PIM0LAL
- PCIX0_PIM0SA
- PCIX0_PIM0SAH
- PCIX0_PIM0SAL
- PCIX0_PIM1LAH
- PCIX0_PIM1LAL
- PCIX0_PIM1SA
- PCIX0_PIM2LAH
- PCIX0_PIM2LAL
- PCIX0_PIM2SA
- PCIX0_PIM2SAH
- PCIX0_PIM2SAL
- PCIX0_PLBBEARH
- PCIX0_PLBBEARL
- PCIX0_PLBBESR
- PCIX0_PMC
- PCIX0_PMCAPID
- PCIX0_PMCSR
- PCIX0_PMCSRBSE
- PCIX0_PMDATA
- PCIX0_PMNIPTR
- PCIX0_PMSCRR
- PCIX0_POM0LAH
- PCIX0_POM0LAL
- PCIX0_POM0PCIAH
- PCIX0_POM0PCIAL
- PCIX0_POM0SA
- PCIX0_POM1LAH
- PCIX0_POM1LAL
- PCIX0_POM1PCIAH
- PCIX0_POM1PCIAL
- PCIX0_POM1SA
- PCIX0_POM2SA
- PCIX0_RES0
- PCIX0_RES1
- PCIX0_RES2
- PCIX0_REVID
- PCIX0_RID
- PCIX0_SBSYSID
- PCIX0_SBSYSVID
- PCIX0_STATUS
- PCIX0_STS
- PCIX0_VENDID
- PCIX133
- PCIX66
- PCIXINITPAT
- PCIXINIT_PCI33_66
- PCIXINIT_PCIX100_133
- PCIXINIT_PCIX50_66
- PCIXINIT_PCIX66_100
- PCIXM_DEVADDR_BNUM
- PCIXM_DEVADDR_DNUM
- PCIXM_DEVADDR_FNUM
- PCIXM_STATUS_133CAP
- PCIXM_STATUS_64BIT
- PCIXM_STATUS_CMPLEXDEV
- PCIXM_STATUS_MAXCRDS
- PCIXM_STATUS_MAXMRDBC
- PCIXM_STATUS_MAXSPLITS
- PCIXM_STATUS_RCVDSCEM
- PCIXM_STATUS_SCDISC
- PCIXM_STATUS_UNEXPSC
- PCIXR_COMMAND
- PCIXR_DEVADDR
- PCIXR_STATUS
- PCIX_CAP_MASK_PI1
- PCIX_CAP_MASK_PI2
- PCIX_CAP_SHIFT
- PCIX_CFG_SPACE
- PCIX_COMMAND_MMRBC_MASK
- PCIX_COMMAND_MMRBC_SHIFT
- PCIX_COMMAND_REGISTER
- PCIX_CRB_WINDOW
- PCIX_CRB_WINDOW_F0
- PCIX_CRB_WINDOW_F1
- PCIX_CRB_WINDOW_F2
- PCIX_CRB_WINDOW_F3
- PCIX_CRB_WINDOW_F4
- PCIX_CRB_WINDOW_F5
- PCIX_CRB_WINDOW_F6
- PCIX_CRB_WINDOW_F7
- PCIX_FLAG
- PCIX_INTR_MASK
- PCIX_INT_MASK
- PCIX_INT_REG_ECC_DB_ERR
- PCIX_INT_REG_ECC_SG_ERR
- PCIX_INT_REG_FLASHR_R_FSM_ERR
- PCIX_INT_REG_FLASHR_W_FSM_ERR
- PCIX_INT_REG_INI_RX_FSM_SERR
- PCIX_INT_REG_INI_TXO_FSM_ERR
- PCIX_INT_REG_INI_TX_FSM_SERR
- PCIX_INT_REG_PIFR_FSM_SERR
- PCIX_INT_REG_RA_RX_FSM_SERR
- PCIX_INT_REG_RRC_TX_REQ_FSM_SERR
- PCIX_INT_REG_SRT_FSM_SERR
- PCIX_INT_REG_TRT_FSM_SERR
- PCIX_INT_REG_WRC_TX_SEND_FSM_SERR
- PCIX_INT_VECTOR
- PCIX_INT_VECTOR_BIT_F0
- PCIX_INT_VECTOR_BIT_F1
- PCIX_INT_VECTOR_BIT_F2
- PCIX_INT_VECTOR_BIT_F3
- PCIX_INT_VECTOR_BIT_F4
- PCIX_INT_VECTOR_BIT_F5
- PCIX_INT_VECTOR_BIT_F6
- PCIX_INT_VECTOR_BIT_F7
- PCIX_IO_SPACE
- PCIX_MEMORY_SPACE
- PCIX_MEM_BASE_LIMIT_OFFSET
- PCIX_MISCII_OFFSET
- PCIX_MISC_BRIDGE_ERRORS_OFFSET
- PCIX_MN_WINDOW
- PCIX_MN_WINDOW_F0
- PCIX_MN_WINDOW_F1
- PCIX_MN_WINDOW_F2
- PCIX_MN_WINDOW_F3
- PCIX_MN_WINDOW_F4
- PCIX_MN_WINDOW_F5
- PCIX_MN_WINDOW_F6
- PCIX_MN_WINDOW_F7
- PCIX_MSI_F
- PCIX_MSI_F0
- PCIX_MSI_F1
- PCIX_MSI_F2
- PCIX_MSI_F3
- PCIX_MSI_F4
- PCIX_MSI_F5
- PCIX_MSI_F6
- PCIX_MSI_F7
- PCIX_OCM_WINDOW
- PCIX_OCM_WINDOW_REG
- PCIX_PS_MEM_SPACE
- PCIX_PS_OP_ADDR_HI
- PCIX_PS_OP_ADDR_LO
- PCIX_REG_BASE_ADR
- PCIX_SN_WINDOW
- PCIX_SN_WINDOW_F0
- PCIX_SN_WINDOW_F1
- PCIX_SN_WINDOW_F2
- PCIX_SN_WINDOW_F3
- PCIX_SN_WINDOW_F4
- PCIX_SN_WINDOW_F5
- PCIX_SN_WINDOW_F6
- PCIX_SN_WINDOW_F7
- PCIX_STAT
- PCIX_STATUS
- PCIX_STATUS_HI_MMRBC_2K
- PCIX_STATUS_HI_MMRBC_4K
- PCIX_STATUS_HI_MMRBC_MASK
- PCIX_STATUS_HI_MMRBC_SHIFT
- PCIX_STATUS_REGISTER_HI
- PCIX_STATUS_REGISTER_LO
- PCIX_STAT_BUS_MASK
- PCIX_STAT_BUS_OFFS
- PCIX_TARGET_MASK
- PCIX_TARGET_MASK_F1
- PCIX_TARGET_MASK_F2
- PCIX_TARGET_MASK_F3
- PCIX_TARGET_MASK_F4
- PCIX_TARGET_MASK_F5
- PCIX_TARGET_MASK_F6
- PCIX_TARGET_MASK_F7
- PCIX_TARGET_STATUS
- PCIX_TARGET_STATUS_F1
- PCIX_TARGET_STATUS_F2
- PCIX_TARGET_STATUS_F3
- PCIX_TARGET_STATUS_F4
- PCIX_TARGET_STATUS_F5
- PCIX_TARGET_STATUS_F6
- PCIX_TARGET_STATUS_F7
- PCI_32BIT
- PCI_32BIT_FLAG
- PCI_64BIT
- PCI_64BIT_BAR0
- PCI_64BIT_BAR2
- PCI_64BIT_BAR4
- PCI_64BIT_BAR_COUNT
- PCI_64BIT_SLOT
- PCI_66MHZ
- PCI_A
- PCI_ACCESS_READ
- PCI_ACCESS_WRITE
- PCI_ACC_INT_REG
- PCI_ACPI_CONTROL
- PCI_ACPI_D0
- PCI_ACPI_D1
- PCI_ACPI_D2
- PCI_ACS_CAP
- PCI_ACS_CR
- PCI_ACS_CTRL
- PCI_ACS_DT
- PCI_ACS_EC
- PCI_ACS_EGRESS_BITS
- PCI_ACS_EGRESS_CTL_V
- PCI_ACS_RR
- PCI_ACS_SV
- PCI_ACS_TB
- PCI_ACS_UF
- PCI_ADAPTER_SOFTWARE_RESET
- PCI_ADDR_DECODE_CTRL
- PCI_ADDR_START
- PCI_ADP1
- PCI_ADP2
- PCI_ADP3
- PCI_ADP4
- PCI_AF_CAP
- PCI_AF_CAP_FLR
- PCI_AF_CAP_TP
- PCI_AF_CTRL
- PCI_AF_CTRL_FLR
- PCI_AF_LENGTH
- PCI_AF_REG_BAR_NUM
- PCI_AF_STATUS
- PCI_AF_STATUS_TP
- PCI_AGP_COMMAND
- PCI_AGP_COMMAND_64BIT
- PCI_AGP_COMMAND_AGP
- PCI_AGP_COMMAND_FW
- PCI_AGP_COMMAND_RATE1
- PCI_AGP_COMMAND_RATE2
- PCI_AGP_COMMAND_RATE4
- PCI_AGP_COMMAND_RQ_MASK
- PCI_AGP_COMMAND_SBA
- PCI_AGP_RFU
- PCI_AGP_SIZEOF
- PCI_AGP_STATUS
- PCI_AGP_STATUS_64BIT
- PCI_AGP_STATUS_FW
- PCI_AGP_STATUS_RATE1
- PCI_AGP_STATUS_RATE2
- PCI_AGP_STATUS_RATE4
- PCI_AGP_STATUS_RQ_MASK
- PCI_AGP_STATUS_SBA
- PCI_AGP_VERSION
- PCI_AHBDOORBELL
- PCI_AHBDOORBELL_OFFSET
- PCI_AHBIOBASE
- PCI_AHBIOBASE_OFFSET
- PCI_AHBMEMBASE
- PCI_AHBMEMBASE_OFFSET
- PCI_ALLEGRO_CONFIG
- PCI_ANY_ID
- PCI_ARBITER_CLEAR
- PCI_ARBITER_PARK_SELECT
- PCI_ARBITER_TIMEOUT_INTERRUPT
- PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE
- PCI_ARBITRATION_MODE_ALTERNATE_0
- PCI_ARBITRATION_MODE_ALTERNATE_B
- PCI_ARBITRATION_MODE_FAIR
- PCI_ARBITRATION_SELECT
- PCI_ARI_CAP
- PCI_ARI_CAP_ACS
- PCI_ARI_CAP_MFVC
- PCI_ARI_CAP_NFN
- PCI_ARI_CTRL
- PCI_ARI_CTRL_ACS
- PCI_ARI_CTRL_FG
- PCI_ARI_CTRL_MFVC
- PCI_ASLE
- PCI_ASLS
- PCI_ASSIGN_ALL_BUSSES
- PCI_ASSIGN_ROMS
- PCI_ATI_VENDOR_ID
- PCI_ATPDMA0_AHBADDR
- PCI_ATPDMA0_AHBADDR_OFFSET
- PCI_ATPDMA0_LENADDR
- PCI_ATPDMA0_LENADDR_OFFSET
- PCI_ATPDMA0_PCIADDR
- PCI_ATPDMA0_PCIADDR_OFFSET
- PCI_ATPDMA1_AHBADDR
- PCI_ATPDMA1_AHBADDR_OFFSET
- PCI_ATPDMA1_LENADDR
- PCI_ATPDMA1_LENADDR_OFFSET
- PCI_ATPDMA1_PCIADDR
- PCI_ATPDMA1_PCIADDR_OFFSET
- PCI_ATS_CAP
- PCI_ATS_CAP_PAGE_ALIGNED
- PCI_ATS_CAP_QDEP
- PCI_ATS_CTRL
- PCI_ATS_CTRL_ENABLE
- PCI_ATS_CTRL_STU
- PCI_ATS_MAX_QDEP
- PCI_ATS_MIN_STU
- PCI_B
- PCI_B2BBASE0_VID_B0
- PCI_B2BBASE0_VID_SV
- PCI_B2BBASE1_SID_B1
- PCI_B2BBASE1_SID_SI
- PCI_B2BMASK_B2BMASK
- PCI_B2BMASK_CCH
- PCI_BAR
- PCI_BAR0_REG
- PCI_BAR1_ENABLE_CA
- PCI_BAR1_ENDIAN_MODE
- PCI_BAR1_ENTRY_VALID
- PCI_BAR1_MASK
- PCI_BAR1_REG
- PCI_BAR2_REG
- PCI_BAR3_REG
- PCI_BAR4_REG
- PCI_BAR5_REG
- PCI_BAR_2
- PCI_BAR_COUNT
- PCI_BAR_DEV
- PCI_BAR_ENABLE
- PCI_BAR_HOST
- PCI_BAR_NO
- PCI_BAR_OTG
- PCI_BAR_RANGE_MASK
- PCI_BAR_REMAP_DDR_CS
- PCI_BAR_SIZE_DDR_CS
- PCI_BASE2_RANGE
- PCI_BASE2_SELECT
- PCI_BASE_ADDRESS_0
- PCI_BASE_ADDRESS_1
- PCI_BASE_ADDRESS_2
- PCI_BASE_ADDRESS_3
- PCI_BASE_ADDRESS_4
- PCI_BASE_ADDRESS_5
- PCI_BASE_ADDRESS_IO_MASK
- PCI_BASE_ADDRESS_MEM_MASK
- PCI_BASE_ADDRESS_MEM_PREFETCH
- PCI_BASE_ADDRESS_MEM_TYPE_1M
- PCI_BASE_ADDRESS_MEM_TYPE_32
- PCI_BASE_ADDRESS_MEM_TYPE_64
- PCI_BASE_ADDRESS_MEM_TYPE_MASK
- PCI_BASE_ADDRESS_SPACE
- PCI_BASE_ADDRESS_SPACE_IO
- PCI_BASE_ADDRESS_SPACE_MEMORY
- PCI_BASE_CLASS_BRIDGE
- PCI_BASE_CLASS_COMMUNICATION
- PCI_BASE_CLASS_CRYPT
- PCI_BASE_CLASS_DISPLAY
- PCI_BASE_CLASS_DOCKING
- PCI_BASE_CLASS_INPUT
- PCI_BASE_CLASS_INTELLIGENT
- PCI_BASE_CLASS_MEMORY
- PCI_BASE_CLASS_MULTIMEDIA
- PCI_BASE_CLASS_NETWORK
- PCI_BASE_CLASS_PROCESSOR
- PCI_BASE_CLASS_SATELLITE
- PCI_BASE_CLASS_SERIAL
- PCI_BASE_CLASS_SIGNAL_PROCESSING
- PCI_BASE_CLASS_STORAGE
- PCI_BASE_CLASS_SYSTEM
- PCI_BASE_CLASS_WIRELESS
- PCI_BASE_REG
- PCI_BCM63XX_H_
- PCI_BIG_ROOT_WINDOW
- PCI_BIOS_IRQ_SCAN
- PCI_BIST
- PCI_BIST_CAPABLE
- PCI_BIST_CODE_MASK
- PCI_BIST_START
- PCI_BM_CTL
- PCI_BM_CTL_BACK2BACK
- PCI_BM_CTL_BURST
- PCI_BM_CTL_DUMMY
- PCI_BM_CTL_ENABLE
- PCI_BRIDGE
- PCI_BRIDGE_CONF_END
- PCI_BRIDGE_CONTROL
- PCI_BRIDGE_CTL_BUS_RESET
- PCI_BRIDGE_CTL_FAST_BACK
- PCI_BRIDGE_CTL_ISA
- PCI_BRIDGE_CTL_MASTER_ABORT
- PCI_BRIDGE_CTL_PARITY
- PCI_BRIDGE_CTL_SERR
- PCI_BRIDGE_CTL_VGA
- PCI_BRIDGE_CTRL_REG_OFFSET
- PCI_BRIDGE_DEVICE
- PCI_BRIDGE_EMUL_HANDLED
- PCI_BRIDGE_EMUL_NOT_HANDLED
- PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR
- PCI_BRIDGE_FUNCS
- PCI_BRIDGE_HEADER_TYPE
- PCI_BRIDGE_RESOURCES
- PCI_BRIDGE_RESOURCE_END
- PCI_BRIDGE_RESOURCE_NUM
- PCI_BRIDGE_VENDOR_AMD
- PCI_BRIDGE_VENDOR_ATI
- PCI_BRIDGE_VENDOR_INTEL
- PCI_BRIDGE_VENDOR_MAX
- PCI_BRIDGE_VENDOR_SIS
- PCI_BRIDGE_VENDOR_UNKNOWN
- PCI_BT_A
- PCI_BT_DEBI
- PCI_BT_V1
- PCI_BT_V2
- PCI_BT_V3
- PCI_BUF_SIZE
- PCI_BUS
- PCI_BUSNO
- PCI_BUS_CS5536
- PCI_BUS_D0ENTRY
- PCI_BUS_D0EXIT
- PCI_BUS_ENABLED
- PCI_BUS_FLAGS_NO_AERSID
- PCI_BUS_FLAGS_NO_EXTCFG
- PCI_BUS_FLAGS_NO_MMRBC
- PCI_BUS_FLAGS_NO_MSI
- PCI_BUS_FUNCTION
- PCI_BUS_FUNCTION_MDS
- PCI_BUS_MASTER_EN
- PCI_BUS_MODES_INDEX
- PCI_BUS_NUM
- PCI_BUS_RELATIONS
- PCI_BUS_RESET_WAIT_MSEC
- PCI_BUS_SIZE64
- PCI_C
- PCI_CACHE_LINE_SIZE
- PCI_CAN_SKIP_ISA_ALIGN
- PCI_CAPABILITY_ID_PCI_EXPRESS
- PCI_CAPABILITY_LIST
- PCI_CAPLIST_POINTER
- PCI_CAPLIST_USB_POINTER
- PCI_CAP_AF_SIZEOF
- PCI_CAP_EXP_ENDPOINT_SIZEOF_V1
- PCI_CAP_EXP_ENDPOINT_SIZEOF_V2
- PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1
- PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2
- PCI_CAP_FLAGS
- PCI_CAP_ID_AF
- PCI_CAP_ID_AGP
- PCI_CAP_ID_AGP3
- PCI_CAP_ID_BASIC
- PCI_CAP_ID_CCRC
- PCI_CAP_ID_CHSWP
- PCI_CAP_ID_DBG
- PCI_CAP_ID_EA
- PCI_CAP_ID_EHCI_DEBUG
- PCI_CAP_ID_EXP
- PCI_CAP_ID_GEN
- PCI_CAP_ID_HT
- PCI_CAP_ID_INVALID
- PCI_CAP_ID_INVALID_VIRT
- PCI_CAP_ID_MAX
- PCI_CAP_ID_MSI
- PCI_CAP_ID_MSIX
- PCI_CAP_ID_PCIX
- PCI_CAP_ID_PM
- PCI_CAP_ID_SATA
- PCI_CAP_ID_SECDEV
- PCI_CAP_ID_SHPC
- PCI_CAP_ID_SLOTID
- PCI_CAP_ID_SSVID
- PCI_CAP_ID_VNDR
- PCI_CAP_ID_VPD
- PCI_CAP_LIST_ID
- PCI_CAP_LIST_NEXT
- PCI_CAP_MSIX_SIZEOF
- PCI_CAP_PCIE_END
- PCI_CAP_PCIE_START
- PCI_CAP_PCIX_SIZEOF_V0
- PCI_CAP_PCIX_SIZEOF_V1
- PCI_CAP_PCIX_SIZEOF_V2
- PCI_CAP_SIZEOF
- PCI_CAP_VC_BASE_SIZEOF
- PCI_CAP_VC_PER_VC_SIZEOF
- PCI_CAP_VPD_SIZEOF
- PCI_CARDBUS_CIS
- PCI_CARDBUS_CIS_POINTER
- PCI_CBER
- PCI_CBIO
- PCI_CBMA
- PCI_CB_BRIDGE_CONTROL
- PCI_CB_BRIDGE_CTL_16BIT_INT
- PCI_CB_BRIDGE_CTL_CB_RESET
- PCI_CB_BRIDGE_CTL_ISA
- PCI_CB_BRIDGE_CTL_MASTER_ABORT
- PCI_CB_BRIDGE_CTL_PARITY
- PCI_CB_BRIDGE_CTL_POST_WRITES
- PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
- PCI_CB_BRIDGE_CTL_PREFETCH_MEM1
- PCI_CB_BRIDGE_CTL_SERR
- PCI_CB_BRIDGE_CTL_VGA
- PCI_CB_CAPABILITY_LIST
- PCI_CB_CARD_BUS
- PCI_CB_IO_BASE_0
- PCI_CB_IO_BASE_0_HI
- PCI_CB_IO_BASE_1
- PCI_CB_IO_BASE_1_HI
- PCI_CB_IO_LIMIT_0
- PCI_CB_IO_LIMIT_0_HI
- PCI_CB_IO_LIMIT_1
- PCI_CB_IO_LIMIT_1_HI
- PCI_CB_IO_RANGE_MASK
- PCI_CB_LATENCY_TIMER
- PCI_CB_LEGACY_MODE_BASE
- PCI_CB_MEMORY_BASE_0
- PCI_CB_MEMORY_BASE_1
- PCI_CB_MEMORY_LIMIT_0
- PCI_CB_MEMORY_LIMIT_1
- PCI_CB_PRIMARY_BUS
- PCI_CB_SEC_STATUS
- PCI_CB_SUBORDINATE_BUS
- PCI_CB_SUBSYSTEM_ID
- PCI_CB_SUBSYSTEM_VENDOR_ID
- PCI_CFCS
- PCI_CFDA
- PCI_CFDA_DSU
- PCI_CFDA_PSM
- PCI_CFDD
- PCI_CFG04_CMD_BM_ENA
- PCI_CFG04_CMD_FAST_ENA
- PCI_CFG04_CMD_IO_ENA
- PCI_CFG04_CMD_MEM_ENA
- PCI_CFG04_CMD_MW_INV
- PCI_CFG04_CMD_PAR_ENA
- PCI_CFG04_CMD_SER_ENA
- PCI_CFG04_STAT
- PCI_CFG04_STAT_66_MHZ
- PCI_CFG04_STAT_BIT
- PCI_CFG04_STAT_DST
- PCI_CFG04_STAT_FBB
- PCI_CFG04_STAT_MDPE
- PCI_CFG04_STAT_PE
- PCI_CFG04_STAT_RMA
- PCI_CFG04_STAT_RTA
- PCI_CFG04_STAT_SSE
- PCI_CFG04_STAT_STA
- PCI_CFG40_RET_LIM
- PCI_CFG40_TRDY_TIM
- PCI_CFGA_BUS_BIT
- PCI_CFGA_BUS_TYPE0
- PCI_CFGA_DEV
- PCI_CFGA_DEV_BIT
- PCI_CFGA_DEV_INTERN
- PCI_CFGA_EN
- PCI_CFGA_FUNC
- PCI_CFGA_FUNC_BIT
- PCI_CFGA_REG
- PCI_CFGA_REG_04
- PCI_CFGA_REG_08
- PCI_CFGA_REG_0C
- PCI_CFGA_REG_3C
- PCI_CFGA_REG_BIT
- PCI_CFGA_REG_ID
- PCI_CFGA_REG_PBA0
- PCI_CFGA_REG_PBA0M
- PCI_CFGA_REG_PBA1
- PCI_CFGA_REG_PBA1C
- PCI_CFGA_REG_PBA1M
- PCI_CFGA_REG_PBA2
- PCI_CFGA_REG_PBA2C
- PCI_CFGA_REG_PBA2M
- PCI_CFGA_REG_PBA3
- PCI_CFGA_REG_PBA3C
- PCI_CFGA_REG_PBA3M
- PCI_CFGA_REG_PBBA0C
- PCI_CFGA_REG_PMGT
- PCI_CFGA_REG_SUBSYS
- PCI_CFG_CSR
- PCI_CFG_GPIO_PLL
- PCI_CFG_GPIO_SCS
- PCI_CFG_GPIO_XTAL
- PCI_CFG_HEADER_TYPE_REG
- PCI_CFG_HFS_1
- PCI_CFG_HFS_1_D0I3_MSK
- PCI_CFG_HFS_2
- PCI_CFG_HFS_3
- PCI_CFG_HFS_4
- PCI_CFG_HFS_5
- PCI_CFG_HFS_6
- PCI_CFG_MSIX0
- PCI_CFG_PRIMARY_BUS_NUMBER_REG
- PCI_CFG_REG1
- PCI_CFG_REG11
- PCI_CFG_REG_0
- PCI_CFG_REG_1
- PCI_CFG_REG_BAR_NUM
- PCI_CFG_RETRY_TIMEOUT
- PCI_CFG_REV_ID_BIT_BASIC_SKU
- PCI_CFG_REV_ID_BIT_RTP
- PCI_CFG_SECONDARY_BUS_NUMBER_REG
- PCI_CFG_SET
- PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
- PCI_CFG_TXE_FW_STS0
- PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK
- PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT
- PCI_CFG_TXE_FW_STS0_OP_MODE_MSK
- PCI_CFG_TXE_FW_STS0_OP_ST_MSK
- PCI_CFG_TXE_FW_STS0_RST_CNT_MSK
- PCI_CFG_TXE_FW_STS0_WRK_ST_MSK
- PCI_CFG_TXE_FW_STS1
- PCI_CFG_TYPE0_FUNC_SHF
- PCI_CFG_TYPE0_REG_SHF
- PCI_CFG_TYPE1_BUS_SHF
- PCI_CFG_TYPE1_DEV_SHF
- PCI_CFG_TYPE1_FUNC_SHF
- PCI_CFG_TYPE1_REG_SHF
- PCI_CFG_ZIP_PF_BAR0
- PCI_CFID
- PCI_CFIT
- PCI_CFLT
- PCI_CFPM
- PCI_CFRV
- PCI_CGCTL
- PCI_CGCTL_ADSPDCGE
- PCI_CGCTL_MISCBDCGE_MASK
- PCI_CHECK_ENABLE_AMD_MMCONF
- PCI_CHIP_AST1180
- PCI_CHIP_AST2000
- PCI_CHIP_AST2100
- PCI_CHIP_MACH32
- PCI_CHIP_MACH64CT
- PCI_CHIP_MACH64CX
- PCI_CHIP_MACH64ET
- PCI_CHIP_MACH64GB
- PCI_CHIP_MACH64GD
- PCI_CHIP_MACH64GI
- PCI_CHIP_MACH64GL
- PCI_CHIP_MACH64GM
- PCI_CHIP_MACH64GN
- PCI_CHIP_MACH64GO
- PCI_CHIP_MACH64GP
- PCI_CHIP_MACH64GQ
- PCI_CHIP_MACH64GR
- PCI_CHIP_MACH64GS
- PCI_CHIP_MACH64GT
- PCI_CHIP_MACH64GU
- PCI_CHIP_MACH64GV
- PCI_CHIP_MACH64GW
- PCI_CHIP_MACH64GX
- PCI_CHIP_MACH64GY
- PCI_CHIP_MACH64GZ
- PCI_CHIP_MACH64LB
- PCI_CHIP_MACH64LD
- PCI_CHIP_MACH64LG
- PCI_CHIP_MACH64LI
- PCI_CHIP_MACH64LM
- PCI_CHIP_MACH64LN
- PCI_CHIP_MACH64LP
- PCI_CHIP_MACH64LQ
- PCI_CHIP_MACH64LR
- PCI_CHIP_MACH64LS
- PCI_CHIP_MACH64LT
- PCI_CHIP_MACH64VT
- PCI_CHIP_MACH64VU
- PCI_CHIP_MACH64VV
- PCI_CHIP_NM2070
- PCI_CHIP_NM2090
- PCI_CHIP_NM2093
- PCI_CHIP_NM2097
- PCI_CHIP_NM2160
- PCI_CHIP_NM2200
- PCI_CHIP_NM2230
- PCI_CHIP_NM2360
- PCI_CHIP_NM2380
- PCI_CHIP_PROSAVAGE_DDR
- PCI_CHIP_PROSAVAGE_DDRK
- PCI_CHIP_PROSAVAGE_KM
- PCI_CHIP_PROSAVAGE_PM
- PCI_CHIP_R200_BB
- PCI_CHIP_R200_BC
- PCI_CHIP_R200_QH
- PCI_CHIP_R200_QI
- PCI_CHIP_R200_QJ
- PCI_CHIP_R200_QK
- PCI_CHIP_R200_QL
- PCI_CHIP_R200_QM
- PCI_CHIP_R200_QN
- PCI_CHIP_R200_QO
- PCI_CHIP_R300_AD
- PCI_CHIP_R300_AE
- PCI_CHIP_R300_AF
- PCI_CHIP_R300_AG
- PCI_CHIP_R300_ND
- PCI_CHIP_R300_NE
- PCI_CHIP_R300_NF
- PCI_CHIP_R300_NG
- PCI_CHIP_R350_AH
- PCI_CHIP_R350_AI
- PCI_CHIP_R350_AJ
- PCI_CHIP_R350_AK
- PCI_CHIP_R350_NH
- PCI_CHIP_R350_NI
- PCI_CHIP_R350_NK
- PCI_CHIP_R360_NJ
- PCI_CHIP_R420_JH
- PCI_CHIP_R420_JI
- PCI_CHIP_R420_JJ
- PCI_CHIP_R420_JK
- PCI_CHIP_R420_JL
- PCI_CHIP_R420_JM
- PCI_CHIP_R420_JN
- PCI_CHIP_R420_JP
- PCI_CHIP_R423_5D57
- PCI_CHIP_R423_UH
- PCI_CHIP_R423_UI
- PCI_CHIP_R423_UJ
- PCI_CHIP_R423_UK
- PCI_CHIP_R423_UQ
- PCI_CHIP_R423_UR
- PCI_CHIP_R423_UT
- PCI_CHIP_RADEON_LW
- PCI_CHIP_RADEON_LX
- PCI_CHIP_RADEON_LY
- PCI_CHIP_RADEON_LZ
- PCI_CHIP_RADEON_QD
- PCI_CHIP_RADEON_QE
- PCI_CHIP_RADEON_QF
- PCI_CHIP_RADEON_QG
- PCI_CHIP_RAGE128LE
- PCI_CHIP_RAGE128LF
- PCI_CHIP_RAGE128MF
- PCI_CHIP_RAGE128ML
- PCI_CHIP_RAGE128PA
- PCI_CHIP_RAGE128PB
- PCI_CHIP_RAGE128PC
- PCI_CHIP_RAGE128PD
- PCI_CHIP_RAGE128PE
- PCI_CHIP_RAGE128PF
- PCI_CHIP_RAGE128PG
- PCI_CHIP_RAGE128PH
- PCI_CHIP_RAGE128PI
- PCI_CHIP_RAGE128PJ
- PCI_CHIP_RAGE128PK
- PCI_CHIP_RAGE128PL
- PCI_CHIP_RAGE128PM
- PCI_CHIP_RAGE128PN
- PCI_CHIP_RAGE128PO
- PCI_CHIP_RAGE128PP
- PCI_CHIP_RAGE128PQ
- PCI_CHIP_RAGE128PR
- PCI_CHIP_RAGE128PS
- PCI_CHIP_RAGE128PT
- PCI_CHIP_RAGE128PU
- PCI_CHIP_RAGE128PV
- PCI_CHIP_RAGE128PW
- PCI_CHIP_RAGE128PX
- PCI_CHIP_RAGE128RE
- PCI_CHIP_RAGE128RF
- PCI_CHIP_RAGE128RG
- PCI_CHIP_RAGE128RK
- PCI_CHIP_RAGE128RL
- PCI_CHIP_RAGE128SE
- PCI_CHIP_RAGE128SF
- PCI_CHIP_RAGE128SG
- PCI_CHIP_RAGE128SH
- PCI_CHIP_RAGE128SK
- PCI_CHIP_RAGE128SL
- PCI_CHIP_RAGE128SM
- PCI_CHIP_RAGE128SN
- PCI_CHIP_RAGE128TF
- PCI_CHIP_RAGE128TL
- PCI_CHIP_RAGE128TR
- PCI_CHIP_RAGE128TS
- PCI_CHIP_RAGE128TT
- PCI_CHIP_RAGE128TU
- PCI_CHIP_RC410_5A62
- PCI_CHIP_RN50
- PCI_CHIP_RS100_4136
- PCI_CHIP_RS100_4336
- PCI_CHIP_RS200_4137
- PCI_CHIP_RS200_4337
- PCI_CHIP_RS250_4237
- PCI_CHIP_RS250_4437
- PCI_CHIP_RS300_5834
- PCI_CHIP_RS300_5835
- PCI_CHIP_RS300_5836
- PCI_CHIP_RS300_5837
- PCI_CHIP_RS350_7834
- PCI_CHIP_RS350_7835
- PCI_CHIP_RS480_5955
- PCI_CHIP_RS482_5975
- PCI_CHIP_RV100_QY
- PCI_CHIP_RV100_QZ
- PCI_CHIP_RV200_QW
- PCI_CHIP_RV200_QX
- PCI_CHIP_RV250_Id
- PCI_CHIP_RV250_Ie
- PCI_CHIP_RV250_If
- PCI_CHIP_RV250_Ig
- PCI_CHIP_RV250_Ld
- PCI_CHIP_RV250_Le
- PCI_CHIP_RV250_Lf
- PCI_CHIP_RV250_Lg
- PCI_CHIP_RV250_Ln
- PCI_CHIP_RV280_5960
- PCI_CHIP_RV280_5961
- PCI_CHIP_RV280_5962
- PCI_CHIP_RV280_5964
- PCI_CHIP_RV280_5C61
- PCI_CHIP_RV280_5C63
- PCI_CHIP_RV350_AP
- PCI_CHIP_RV350_AQ
- PCI_CHIP_RV350_AS
- PCI_CHIP_RV350_AT
- PCI_CHIP_RV350_AV
- PCI_CHIP_RV350_NP
- PCI_CHIP_RV350_NQ
- PCI_CHIP_RV350_NR
- PCI_CHIP_RV350_NS
- PCI_CHIP_RV350_NT
- PCI_CHIP_RV350_NV
- PCI_CHIP_RV360_AR
- PCI_CHIP_RV370_5460
- PCI_CHIP_RV370_5461
- PCI_CHIP_RV370_5462
- PCI_CHIP_RV370_5463
- PCI_CHIP_RV370_5464
- PCI_CHIP_RV370_5465
- PCI_CHIP_RV370_5466
- PCI_CHIP_RV370_5467
- PCI_CHIP_RV370_5B60
- PCI_CHIP_RV370_5B61
- PCI_CHIP_RV370_5B62
- PCI_CHIP_RV370_5B63
- PCI_CHIP_RV370_5B64
- PCI_CHIP_RV370_5B65
- PCI_CHIP_RV370_5B66
- PCI_CHIP_RV370_5B67
- PCI_CHIP_RV380_3150
- PCI_CHIP_RV380_3151
- PCI_CHIP_RV380_3152
- PCI_CHIP_RV380_3153
- PCI_CHIP_RV380_3154
- PCI_CHIP_RV380_3156
- PCI_CHIP_RV380_3E50
- PCI_CHIP_RV380_3E51
- PCI_CHIP_RV380_3E52
- PCI_CHIP_RV380_3E53
- PCI_CHIP_RV380_3E54
- PCI_CHIP_RV380_3E56
- PCI_CHIP_S3TWISTER_K
- PCI_CHIP_S3TWISTER_P
- PCI_CHIP_SAVAGE2000
- PCI_CHIP_SAVAGE3D
- PCI_CHIP_SAVAGE3D_MV
- PCI_CHIP_SAVAGE4
- PCI_CHIP_SAVAGE_IX
- PCI_CHIP_SAVAGE_IX_MV
- PCI_CHIP_SAVAGE_MX
- PCI_CHIP_SAVAGE_MX_MV
- PCI_CHIP_SUPSAV_IX128DDR
- PCI_CHIP_SUPSAV_IX128SDR
- PCI_CHIP_SUPSAV_IX64DDR
- PCI_CHIP_SUPSAV_IX64SDR
- PCI_CHIP_SUPSAV_IXCDDR
- PCI_CHIP_SUPSAV_IXCSDR
- PCI_CHIP_SUPSAV_MX128
- PCI_CHIP_SUPSAV_MX64
- PCI_CHIP_SUPSAV_MX64C
- PCI_CHSWP_CSR
- PCI_CHSWP_DHA
- PCI_CHSWP_EIM
- PCI_CHSWP_EXT
- PCI_CHSWP_INS
- PCI_CHSWP_LOO
- PCI_CHSWP_PI
- PCI_CHSWP_PIE
- PCI_CLASSCODE_GENWQE5
- PCI_CLASSCODE_GENWQE5_SRIOV
- PCI_CLASSREV_CLASS
- PCI_CLASSREV_REV
- PCI_CLASS_BRIDGE_CARDBUS
- PCI_CLASS_BRIDGE_DEV
- PCI_CLASS_BRIDGE_EISA
- PCI_CLASS_BRIDGE_HOST
- PCI_CLASS_BRIDGE_ISA
- PCI_CLASS_BRIDGE_MASK
- PCI_CLASS_BRIDGE_MC
- PCI_CLASS_BRIDGE_NUBUS
- PCI_CLASS_BRIDGE_OTHER
- PCI_CLASS_BRIDGE_PCI
- PCI_CLASS_BRIDGE_PCMCIA
- PCI_CLASS_BRIDGE_RACEWAY
- PCI_CLASS_BRIDGE_SHIFT
- PCI_CLASS_COMMUNICATION_MODEM
- PCI_CLASS_COMMUNICATION_MULTISERIAL
- PCI_CLASS_COMMUNICATION_OTHER
- PCI_CLASS_COMMUNICATION_PARALLEL
- PCI_CLASS_COMMUNICATION_SERIAL
- PCI_CLASS_CRYPT_ENTERTAINMENT
- PCI_CLASS_CRYPT_NETWORK
- PCI_CLASS_CRYPT_OTHER
- PCI_CLASS_DEVICE
- PCI_CLASS_DISPLAY_3D
- PCI_CLASS_DISPLAY_OTHER
- PCI_CLASS_DISPLAY_VGA
- PCI_CLASS_DISPLAY_XGA
- PCI_CLASS_DOCKING_GENERIC
- PCI_CLASS_DOCKING_OTHER
- PCI_CLASS_INPUT_GAMEPORT
- PCI_CLASS_INPUT_KEYBOARD
- PCI_CLASS_INPUT_MOUSE
- PCI_CLASS_INPUT_OTHER
- PCI_CLASS_INPUT_PEN
- PCI_CLASS_INPUT_SCANNER
- PCI_CLASS_INTELLIGENT_I2O
- PCI_CLASS_MASK
- PCI_CLASS_MEMORY_FLASH
- PCI_CLASS_MEMORY_OTHER
- PCI_CLASS_MEMORY_RAM
- PCI_CLASS_MULTIMEDIA_AUDIO
- PCI_CLASS_MULTIMEDIA_HD_AUDIO
- PCI_CLASS_MULTIMEDIA_OTHER
- PCI_CLASS_MULTIMEDIA_PHONE
- PCI_CLASS_MULTIMEDIA_VIDEO
- PCI_CLASS_NETWORK_ATM
- PCI_CLASS_NETWORK_ETHERNET
- PCI_CLASS_NETWORK_FDDI
- PCI_CLASS_NETWORK_OTHER
- PCI_CLASS_NETWORK_TOKEN_RING
- PCI_CLASS_NOT_DEFINED
- PCI_CLASS_NOT_DEFINED_VGA
- PCI_CLASS_OTHERS
- PCI_CLASS_PROCESSOR_386
- PCI_CLASS_PROCESSOR_486
- PCI_CLASS_PROCESSOR_ALPHA
- PCI_CLASS_PROCESSOR_CO
- PCI_CLASS_PROCESSOR_MIPS
- PCI_CLASS_PROCESSOR_PENTIUM
- PCI_CLASS_PROCESSOR_POWERPC
- PCI_CLASS_PROG
- PCI_CLASS_REVISION
- PCI_CLASS_SATELLITE_AUDIO
- PCI_CLASS_SATELLITE_DATA
- PCI_CLASS_SATELLITE_TV
- PCI_CLASS_SATELLITE_VOICE
- PCI_CLASS_SERIAL_ACCESS
- PCI_CLASS_SERIAL_FIBER
- PCI_CLASS_SERIAL_FIREWIRE
- PCI_CLASS_SERIAL_FIREWIRE_OHCI
- PCI_CLASS_SERIAL_IPMI
- PCI_CLASS_SERIAL_IPMI_BT
- PCI_CLASS_SERIAL_IPMI_KCS
- PCI_CLASS_SERIAL_IPMI_SMIC
- PCI_CLASS_SERIAL_SMBUS
- PCI_CLASS_SERIAL_SSA
- PCI_CLASS_SERIAL_UNKNOWN
- PCI_CLASS_SERIAL_USB
- PCI_CLASS_SERIAL_USB_DEVICE
- PCI_CLASS_SERIAL_USB_EHCI
- PCI_CLASS_SERIAL_USB_OHCI
- PCI_CLASS_SERIAL_USB_UHCI
- PCI_CLASS_SERIAL_USB_XHCI
- PCI_CLASS_SP_DPIO
- PCI_CLASS_SP_OTHER
- PCI_CLASS_STORAGE_EXPRESS
- PCI_CLASS_STORAGE_FLOPPY
- PCI_CLASS_STORAGE_IDE
- PCI_CLASS_STORAGE_IPI
- PCI_CLASS_STORAGE_OTHER
- PCI_CLASS_STORAGE_RAID
- PCI_CLASS_STORAGE_SAS
- PCI_CLASS_STORAGE_SATA
- PCI_CLASS_STORAGE_SATA_AHCI
- PCI_CLASS_STORAGE_SCSI
- PCI_CLASS_SYSTEM_DMA
- PCI_CLASS_SYSTEM_OTHER
- PCI_CLASS_SYSTEM_PCI_HOTPLUG
- PCI_CLASS_SYSTEM_PIC
- PCI_CLASS_SYSTEM_PIC_IOAPIC
- PCI_CLASS_SYSTEM_PIC_IOXAPIC
- PCI_CLASS_SYSTEM_RTC
- PCI_CLASS_SYSTEM_SDHCI
- PCI_CLASS_SYSTEM_TIMER
- PCI_CLASS_WIRELESS_RF_CONTROLLER
- PCI_CLASS_WIRELESS_WHCI
- PCI_CLKRUN_EN
- PCI_CLK_12M
- PCI_CLK_16M
- PCI_CLK_24M
- PCI_CLK_33
- PCI_CLK_33A
- PCI_CLK_33M
- PCI_CLK_375K
- PCI_CLK_48
- PCI_CLK_48M
- PCI_CLK_66
- PCI_CLK_66MHZ
- PCI_CLK_8M
- PCI_CLK_PAD_ENABLE
- PCI_CLK_RIN
- PCI_CLOCK
- PCI_CLOCK_CTL
- PCI_CLOCK_MAX
- PCI_CMD
- PCI_CMD_BUS_MASTER_ENABLE_BIT
- PCI_CMD_HOST_REORDER
- PCI_CMD_IO_SPACE_ENABLE_BIT
- PCI_CMD_MEM_SPACE_ENABLE_BIT
- PCI_CMEM_CMBASE
- PCI_CMEM_CMMASK
- PCI_CMEM_E
- PCI_COMMAND
- PCI_COMMAND_DECODE_ENABLE
- PCI_COMMAND_FAST_BACK
- PCI_COMMAND_GUEST
- PCI_COMMAND_INTX_DISABLE
- PCI_COMMAND_INVALIDATE
- PCI_COMMAND_IO
- PCI_COMMAND_MASTER
- PCI_COMMAND_MEMORY
- PCI_COMMAND_PARITY
- PCI_COMMAND_REGISTER
- PCI_COMMAND_SERR
- PCI_COMMAND_SPECIAL
- PCI_COMMAND_TIMEOUT
- PCI_COMMAND_VGA_PALETTE
- PCI_COMMAND_WAIT
- PCI_COMPAT_DOMAIN_0
- PCI_CONF1_ADDRESS
- PCI_CONF2_ADDRESS
- PCI_CONFIG
- PCI_CONFIG_2_BAR1_64ENA
- PCI_CONFIG_2_BAR1_SIZE
- PCI_CONFIG_2_BAR1_SIZE_128K
- PCI_CONFIG_2_BAR1_SIZE_128M
- PCI_CONFIG_2_BAR1_SIZE_16M
- PCI_CONFIG_2_BAR1_SIZE_1G
- PCI_CONFIG_2_BAR1_SIZE_1M
- PCI_CONFIG_2_BAR1_SIZE_256K
- PCI_CONFIG_2_BAR1_SIZE_256M
- PCI_CONFIG_2_BAR1_SIZE_2M
- PCI_CONFIG_2_BAR1_SIZE_32M
- PCI_CONFIG_2_BAR1_SIZE_4M
- PCI_CONFIG_2_BAR1_SIZE_512K
- PCI_CONFIG_2_BAR1_SIZE_512M
- PCI_CONFIG_2_BAR1_SIZE_64K
- PCI_CONFIG_2_BAR1_SIZE_64M
- PCI_CONFIG_2_BAR1_SIZE_8M
- PCI_CONFIG_2_BAR1_SIZE_DISABLED
- PCI_CONFIG_2_BAR2_64ENA
- PCI_CONFIG_2_BAR2_SIZE
- PCI_CONFIG_2_BAR2_SIZE_128K
- PCI_CONFIG_2_BAR2_SIZE_128M
- PCI_CONFIG_2_BAR2_SIZE_16M
- PCI_CONFIG_2_BAR2_SIZE_1G
- PCI_CONFIG_2_BAR2_SIZE_1M
- PCI_CONFIG_2_BAR2_SIZE_256K
- PCI_CONFIG_2_BAR2_SIZE_256M
- PCI_CONFIG_2_BAR2_SIZE_2M
- PCI_CONFIG_2_BAR2_SIZE_32M
- PCI_CONFIG_2_BAR2_SIZE_4M
- PCI_CONFIG_2_BAR2_SIZE_512K
- PCI_CONFIG_2_BAR2_SIZE_512M
- PCI_CONFIG_2_BAR2_SIZE_64K
- PCI_CONFIG_2_BAR2_SIZE_64M
- PCI_CONFIG_2_BAR2_SIZE_8M
- PCI_CONFIG_2_BAR2_SIZE_DISABLED
- PCI_CONFIG_2_BAR_PREFETCH
- PCI_CONFIG_2_CFG_CYCLE_RETRY
- PCI_CONFIG_2_EXP_ROM_RETRY
- PCI_CONFIG_2_EXP_ROM_SIZE
- PCI_CONFIG_2_EXP_ROM_SIZE_128K
- PCI_CONFIG_2_EXP_ROM_SIZE_16K
- PCI_CONFIG_2_EXP_ROM_SIZE_16M
- PCI_CONFIG_2_EXP_ROM_SIZE_1M
- PCI_CONFIG_2_EXP_ROM_SIZE_256K
- PCI_CONFIG_2_EXP_ROM_SIZE_2K
- PCI_CONFIG_2_EXP_ROM_SIZE_2M
- PCI_CONFIG_2_EXP_ROM_SIZE_32K
- PCI_CONFIG_2_EXP_ROM_SIZE_32M
- PCI_CONFIG_2_EXP_ROM_SIZE_4K
- PCI_CONFIG_2_EXP_ROM_SIZE_4M
- PCI_CONFIG_2_EXP_ROM_SIZE_512K
- PCI_CONFIG_2_EXP_ROM_SIZE_64K
- PCI_CONFIG_2_EXP_ROM_SIZE_8K
- PCI_CONFIG_2_EXP_ROM_SIZE_8M
- PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED
- PCI_CONFIG_2_FIRST_CFG_DONE
- PCI_CONFIG_2_RESERVED0
- PCI_CONFIG_3_FORCE_PME
- PCI_CONFIG_3_PCI_POWER
- PCI_CONFIG_3_PME_ENABLE
- PCI_CONFIG_3_PME_STATUS
- PCI_CONFIG_3_PM_STATE
- PCI_CONFIG_3_STICKY_BYTE
- PCI_CONFIG_3_VAUX_PRESET
- PCI_CONFIG_ADDRESS
- PCI_CONFIG_AEN
- PCI_CONFIG_BM
- PCI_CONFIG_BME
- PCI_CONFIG_CH
- PCI_CONFIG_DATA
- PCI_CONFIG_EF
- PCI_CONFIG_ELBI_CTRL_WRITE
- PCI_CONFIG_ELBI_STS_DONE
- PCI_CONFIG_ELBI_STS_ERR
- PCI_CONFIG_ELBI_STS_MASK
- PCI_CONFIG_EM
- PCI_CONFIG_EP
- PCI_CONFIG_ERD
- PCI_CONFIG_ET
- PCI_CONFIG_IA
- PCI_CONFIG_IMM
- PCI_CONFIG_IP
- PCI_CONFIG_IPB
- PCI_CONFIG_IS
- PCI_CONFIG_ITM
- PCI_CONFIG_ITT
- PCI_CONFIG_LENGTH
- PCI_CONFIG_MMIO_LENGTH
- PCI_CONFIG_NC
- PCI_CONFIG_PD
- PCI_CONFIG_PORT_SIZE
- PCI_CONFIG_R1H
- PCI_CONFIG_R2H
- PCI_CONFIG_SIC_ALL
- PCI_CONFIG_SIC_BA_ADR
- PCI_CONFIG_SIC_HWA_DAT
- PCI_CONFIG_SIC_NO
- PCI_CONFIG_SM
- PCI_CONFIG_SPACE_REG
- PCI_CONFIG_SPACE_SIZE
- PCI_CONFIG_ST
- PCI_CONFIG_SUBSYS_ID
- PCI_CONF_ADDR
- PCI_CONF_ADDRESS
- PCI_CONF_ADDR_EN
- PCI_CONF_AMISIG
- PCI_CONF_AMISIG64
- PCI_CONF_BUS
- PCI_CONF_DATA
- PCI_CONF_DEV
- PCI_CONF_DEVICE
- PCI_CONF_ENABLE
- PCI_CONF_FLSH_BAR
- PCI_CONF_FUNC
- PCI_CONF_FUNCTION
- PCI_CONF_FUNC_BAR_CS
- PCI_CONF_FUNC_STAT_CMD
- PCI_CONF_MBAR0_SWA
- PCI_CONF_MBAR0_SWB
- PCI_CONF_MBAR0_SWC
- PCI_CONF_MBAR1
- PCI_CONF_MBAR_KEY
- PCI_CONF_REG
- PCI_CONF_REG_BAR_HI_CS
- PCI_CONF_REG_BAR_LO_CS
- PCI_CONF_REG_STAT_CMD
- PCI_CONF_WHERE
- PCI_CONTROLLER
- PCI_CONTROL_OFFSET
- PCI_COUNTERS
- PCI_COUNTER_IRQ
- PCI_COUNTER_IRQ_CPU
- PCI_COUNTER_IRQ_SET
- PCI_COUNTER_IRQ_SYS
- PCI_CPU_COUNTER_LIMIT
- PCI_CPU_COUNTER_LIMIT_HI
- PCI_CPU_COUNTER_LIMIT_LO
- PCI_CPU_INTERRUPT_PENDING
- PCI_CPWM
- PCI_CREATE_INTERRUPT_MESSAGE
- PCI_CREATE_INTERRUPT_MESSAGE2
- PCI_CRP_AD_CBE
- PCI_CRP_AD_CBE_OFFSET
- PCI_CRP_RDATA
- PCI_CRP_RDATA_OFFSET
- PCI_CRP_WDATA
- PCI_CRP_WDATA_OFFSET
- PCI_CR_BAR11MASK
- PCI_CR_BAR12MASK
- PCI_CR_BAR13MASK
- PCI_CR_CLK_CTRL
- PCI_CR_FCI_ADDR_MAP0
- PCI_CR_FCI_ADDR_MAP1
- PCI_CR_FCI_ADDR_MAP11hg
- PCI_CR_FCI_ADDR_MAP2
- PCI_CR_FCI_ADDR_MAP3
- PCI_CR_FCI_ADDR_MAP4
- PCI_CR_FCI_ADDR_MAP5
- PCI_CR_FCI_ADDR_MAP6
- PCI_CR_FCI_ADDR_MAP7
- PCI_CR_FCI_BURST_LENGTH
- PCI_CR_PCI_ADDR_MAP11
- PCI_CR_PCI_EOI
- PCI_CR_PCI_MOD
- PCI_CR_PC_ARB
- PCI_CSI_CONTROL
- PCI_CSI_CONTROL_PORTS_OFF_MASK
- PCI_CSR
- PCI_CSR_ABE
- PCI_CSR_ADS
- PCI_CSR_ARBEN
- PCI_CSR_ASE
- PCI_CSR_DBT
- PCI_CSR_HOST
- PCI_CSR_IC
- PCI_CSR_OFFSET
- PCI_CSR_PDS
- PCI_CS_BASE_ADDR1
- PCI_CS_STS_CMD
- PCI_CTL
- PCI_CTL_AAA
- PCI_CTL_CLOCK_DLY_ADDR
- PCI_CTL_EAP
- PCI_CTL_EN
- PCI_CTL_IEN
- PCI_CTL_IGM
- PCI_CTL_PCIM
- PCI_CTL_PCIM_BIT
- PCI_CTL_PCIM_DIS
- PCI_CTL_PCIM_EXT
- PCI_CTL_PCIM_RR
- PCI_CTL_PCIM_RSVD6
- PCI_CTL_PCIM_RSVD7
- PCI_CTL_PCIM_SUS
- PCI_CTL_PCIM_TNR
- PCI_CTL_SCE
- PCI_CTL_TNR
- PCI_CTRL
- PCI_CTRL2_INTMASK_CMDERR
- PCI_CTRL2_INTMASK_MABRT_RX
- PCI_CTRL2_INTMASK_PARERR
- PCI_CTRL2_INTMASK_PERR_RX
- PCI_CTRL2_INTMASK_RETRY4
- PCI_CTRL2_INTMASK_SERR_RX
- PCI_CTRL2_INTMASK_SHIFT
- PCI_CTRL2_INTMASK_TABRT_RX
- PCI_CTRL2_INTMASK_TABRT_TX
- PCI_CTRL2_INTSTS_SHIFT
- PCI_CTRL2_MSTPRI_REQ0
- PCI_CTRL2_MSTPRI_REQ1
- PCI_CTRL2_MSTPRI_REQ2
- PCI_CTRL2_MSTPRI_REQ3
- PCI_CTRL2_MSTPRI_REQ4
- PCI_CTRL2_MSTPRI_REQ5
- PCI_CTRL2_MSTPRI_REQ6
- PCI_Clock_33MHz
- PCI_Clock_66MHz
- PCI_D
- PCI_D0
- PCI_D1
- PCI_D2
- PCI_D3cold
- PCI_D3hot
- PCI_DAC_DEN
- PCI_DAS_B
- PCI_DAS_D
- PCI_DAS_E
- PCI_DAS_IFE
- PCI_DAS_IFF
- PCI_DAS_OFE
- PCI_DAS_OFF
- PCI_DATA
- PCI_DCSR_MRRS
- PCI_DCSR_MRRS_MASK
- PCI_DDMA_CTRL
- PCI_DEBUG
- PCI_DEBUG0
- PCI_DEBUG1
- PCI_DEBUG2
- PCI_DEBUG3
- PCI_DEBUG4
- PCI_DEBUG5
- PCI_DEBUG6
- PCI_DEBUG7
- PCI_DEFAULT_PIN
- PCI_DELETE_INTERRUPT_MESSAGE
- PCI_DELETE_INTERRUPT_MESSAGE2
- PCI_DESCR
- PCI_DEVFN
- PCI_DEVICE
- PCI_DEVICE_CLASS
- PCI_DEVICE_DATA
- PCI_DEVICE_ENABLED
- PCI_DEVICE_GENWQE
- PCI_DEVICE_ID
- PCI_DEVICE_ID_38C0800_REV1
- PCI_DEVICE_ID_38C1600_REV1
- PCI_DEVICE_ID_3COM_2_3CRPAG175
- PCI_DEVICE_ID_3COM_3C339
- PCI_DEVICE_ID_3COM_3C359
- PCI_DEVICE_ID_3COM_3C940
- PCI_DEVICE_ID_3COM_3C940B
- PCI_DEVICE_ID_3COM_3C985
- PCI_DEVICE_ID_3COM_3CR990
- PCI_DEVICE_ID_3COM_3CR990B
- PCI_DEVICE_ID_3COM_3CR990SVR
- PCI_DEVICE_ID_3COM_3CR990SVR95
- PCI_DEVICE_ID_3COM_3CR990SVR97
- PCI_DEVICE_ID_3COM_3CR990_FX
- PCI_DEVICE_ID_3COM_3CR990_TX_95
- PCI_DEVICE_ID_3COM_3CR990_TX_97
- PCI_DEVICE_ID_3COM_3CRDAG675
- PCI_DEVICE_ID_3DFX_BANSHEE
- PCI_DEVICE_ID_3DFX_VOODOO
- PCI_DEVICE_ID_3DFX_VOODOO2
- PCI_DEVICE_ID_3DFX_VOODOO3
- PCI_DEVICE_ID_3DFX_VOODOO5
- PCI_DEVICE_ID_3DLABS_PERMEDIA2
- PCI_DEVICE_ID_3DLABS_PERMEDIA2V
- PCI_DEVICE_ID_3WARE_1000
- PCI_DEVICE_ID_3WARE_7000
- PCI_DEVICE_ID_3WARE_9000
- PCI_DEVICE_ID_3WARE_9550SX
- PCI_DEVICE_ID_3WARE_9650SE
- PCI_DEVICE_ID_3WARE_9690SA
- PCI_DEVICE_ID_3WARE_9750
- PCI_DEVICE_ID_57980S_10
- PCI_DEVICE_ID_57980S_100
- PCI_DEVICE_ID_57980S_25
- PCI_DEVICE_ID_57980S_40
- PCI_DEVICE_ID_57980S_50
- PCI_DEVICE_ID_57980S_IOV
- PCI_DEVICE_ID_57980S_MF
- PCI_DEVICE_ID_9420
- PCI_DEVICE_ID_ABOCOM_2BD1
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S
- PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2
- PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4
- PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4
- PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8
- PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4
- PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8
- PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4
- PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB
- PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S
- PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM
- PCI_DEVICE_ID_ACCESSIO_WDG_CSM
- PCI_DEVICE_ID_ACCES_COM232_8
- PCI_DEVICE_ID_ACCES_COM_2S
- PCI_DEVICE_ID_ACCES_COM_2SM
- PCI_DEVICE_ID_ACCES_COM_4S
- PCI_DEVICE_ID_ACCES_COM_4SM
- PCI_DEVICE_ID_ACCES_COM_8S
- PCI_DEVICE_ID_ACCES_COM_8SM
- PCI_DEVICE_ID_AD1889JS
- PCI_DEVICE_ID_ADAPTEC2_2930U2
- PCI_DEVICE_ID_ADAPTEC2_2940U2
- PCI_DEVICE_ID_ADAPTEC2_3940U2
- PCI_DEVICE_ID_ADAPTEC2_3950U2D
- PCI_DEVICE_ID_ADAPTEC2_7890
- PCI_DEVICE_ID_ADAPTEC2_7890B
- PCI_DEVICE_ID_ADAPTEC2_7892A
- PCI_DEVICE_ID_ADAPTEC2_7892B
- PCI_DEVICE_ID_ADAPTEC2_7892D
- PCI_DEVICE_ID_ADAPTEC2_7892P
- PCI_DEVICE_ID_ADAPTEC2_7896
- PCI_DEVICE_ID_ADAPTEC2_7899A
- PCI_DEVICE_ID_ADAPTEC2_7899B
- PCI_DEVICE_ID_ADAPTEC2_7899D
- PCI_DEVICE_ID_ADAPTEC2_7899P
- PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN
- PCI_DEVICE_ID_ADAPTEC2_SCAMP
- PCI_DEVICE_ID_ADAPTEC_1480A
- PCI_DEVICE_ID_ADAPTEC_3860
- PCI_DEVICE_ID_ADAPTEC_38602
- PCI_DEVICE_ID_ADAPTEC_7810
- PCI_DEVICE_ID_ADAPTEC_7821
- PCI_DEVICE_ID_ADAPTEC_7850
- PCI_DEVICE_ID_ADAPTEC_7855
- PCI_DEVICE_ID_ADAPTEC_7860
- PCI_DEVICE_ID_ADAPTEC_7861
- PCI_DEVICE_ID_ADAPTEC_7870
- PCI_DEVICE_ID_ADAPTEC_7871
- PCI_DEVICE_ID_ADAPTEC_7872
- PCI_DEVICE_ID_ADAPTEC_7873
- PCI_DEVICE_ID_ADAPTEC_7874
- PCI_DEVICE_ID_ADAPTEC_7880
- PCI_DEVICE_ID_ADAPTEC_7881
- PCI_DEVICE_ID_ADAPTEC_7882
- PCI_DEVICE_ID_ADAPTEC_7883
- PCI_DEVICE_ID_ADAPTEC_7884
- PCI_DEVICE_ID_ADAPTEC_7885
- PCI_DEVICE_ID_ADAPTEC_7886
- PCI_DEVICE_ID_ADAPTEC_7887
- PCI_DEVICE_ID_ADAPTEC_7888
- PCI_DEVICE_ID_ADAPTEC_7895
- PCI_DEVICE_ID_ADDIDATA_APCI7300
- PCI_DEVICE_ID_ADDIDATA_APCI7300_2
- PCI_DEVICE_ID_ADDIDATA_APCI7300_3
- PCI_DEVICE_ID_ADDIDATA_APCI7420
- PCI_DEVICE_ID_ADDIDATA_APCI7420_2
- PCI_DEVICE_ID_ADDIDATA_APCI7420_3
- PCI_DEVICE_ID_ADDIDATA_APCI7500
- PCI_DEVICE_ID_ADDIDATA_APCI7500_2
- PCI_DEVICE_ID_ADDIDATA_APCI7500_3
- PCI_DEVICE_ID_ADDIDATA_APCI7800_3
- PCI_DEVICE_ID_ADDIDATA_APCIe7300
- PCI_DEVICE_ID_ADDIDATA_APCIe7420
- PCI_DEVICE_ID_ADDIDATA_APCIe7500
- PCI_DEVICE_ID_ADDIDATA_APCIe7800
- PCI_DEVICE_ID_ADL_2301
- PCI_DEVICE_ID_ADVANTECH_PCI3618
- PCI_DEVICE_ID_ADVANTECH_PCI3620
- PCI_DEVICE_ID_ADVANTECH_PCIf618
- PCI_DEVICE_ID_AEC_VITCLTC
- PCI_DEVICE_ID_AFAVLAB_P028
- PCI_DEVICE_ID_AFAVLAB_P030
- PCI_DEVICE_ID_AGERE_FW643
- PCI_DEVICE_ID_AGESTAR_9375
- PCI_DEVICE_ID_AH
- PCI_DEVICE_ID_AH_IOV
- PCI_DEVICE_ID_AI_M1435
- PCI_DEVICE_ID_AKS_ALADDINCARD
- PCI_DEVICE_ID_ALACRITECH_MOJAVE
- PCI_DEVICE_ID_ALACRITECH_OASIS
- PCI_DEVICE_ID_ALTEON_ACENIC_COPPER
- PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
- PCI_DEVICE_ID_ALTIMA_AC1000
- PCI_DEVICE_ID_ALTIMA_AC1001
- PCI_DEVICE_ID_ALTIMA_AC1003
- PCI_DEVICE_ID_ALTIMA_AC9100
- PCI_DEVICE_ID_AL_M1533
- PCI_DEVICE_ID_AL_M1535
- PCI_DEVICE_ID_AL_M1541
- PCI_DEVICE_ID_AL_M1563
- PCI_DEVICE_ID_AL_M1621
- PCI_DEVICE_ID_AL_M1631
- PCI_DEVICE_ID_AL_M1632
- PCI_DEVICE_ID_AL_M1641
- PCI_DEVICE_ID_AL_M1644
- PCI_DEVICE_ID_AL_M1647
- PCI_DEVICE_ID_AL_M1651
- PCI_DEVICE_ID_AL_M1671
- PCI_DEVICE_ID_AL_M1681
- PCI_DEVICE_ID_AL_M1683
- PCI_DEVICE_ID_AL_M1689
- PCI_DEVICE_ID_AL_M5219
- PCI_DEVICE_ID_AL_M5228
- PCI_DEVICE_ID_AL_M5229
- PCI_DEVICE_ID_AL_M5451
- PCI_DEVICE_ID_AL_M7101
- PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800
- PCI_DEVICE_ID_AMD8111E_7462
- PCI_DEVICE_ID_AMD_10H_NB_DRAM
- PCI_DEVICE_ID_AMD_10H_NB_HT
- PCI_DEVICE_ID_AMD_10H_NB_LINK
- PCI_DEVICE_ID_AMD_10H_NB_MAP
- PCI_DEVICE_ID_AMD_10H_NB_MISC
- PCI_DEVICE_ID_AMD_11H_NB_DRAM
- PCI_DEVICE_ID_AMD_11H_NB_HT
- PCI_DEVICE_ID_AMD_11H_NB_LINK
- PCI_DEVICE_ID_AMD_11H_NB_MAP
- PCI_DEVICE_ID_AMD_11H_NB_MISC
- PCI_DEVICE_ID_AMD_15H_M10H_F3
- PCI_DEVICE_ID_AMD_15H_M30H_NB_F1
- PCI_DEVICE_ID_AMD_15H_M30H_NB_F2
- PCI_DEVICE_ID_AMD_15H_M30H_NB_F3
- PCI_DEVICE_ID_AMD_15H_M30H_NB_F4
- PCI_DEVICE_ID_AMD_15H_M60H_NB_F1
- PCI_DEVICE_ID_AMD_15H_M60H_NB_F2
- PCI_DEVICE_ID_AMD_15H_M60H_NB_F3
- PCI_DEVICE_ID_AMD_15H_M60H_NB_F4
- PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
- PCI_DEVICE_ID_AMD_15H_M70H_NB_F4
- PCI_DEVICE_ID_AMD_15H_NB_F0
- PCI_DEVICE_ID_AMD_15H_NB_F1
- PCI_DEVICE_ID_AMD_15H_NB_F2
- PCI_DEVICE_ID_AMD_15H_NB_F3
- PCI_DEVICE_ID_AMD_15H_NB_F4
- PCI_DEVICE_ID_AMD_15H_NB_F5
- PCI_DEVICE_ID_AMD_16H_M30H_NB_F1
- PCI_DEVICE_ID_AMD_16H_M30H_NB_F2
- PCI_DEVICE_ID_AMD_16H_M30H_NB_F3
- PCI_DEVICE_ID_AMD_16H_M30H_NB_F4
- PCI_DEVICE_ID_AMD_16H_NB_F1
- PCI_DEVICE_ID_AMD_16H_NB_F2
- PCI_DEVICE_ID_AMD_16H_NB_F3
- PCI_DEVICE_ID_AMD_16H_NB_F4
- PCI_DEVICE_ID_AMD_17H_DF_F0
- PCI_DEVICE_ID_AMD_17H_DF_F3
- PCI_DEVICE_ID_AMD_17H_DF_F4
- PCI_DEVICE_ID_AMD_17H_DF_F6
- PCI_DEVICE_ID_AMD_17H_M10H_DF_F0
- PCI_DEVICE_ID_AMD_17H_M10H_DF_F3
- PCI_DEVICE_ID_AMD_17H_M10H_DF_F4
- PCI_DEVICE_ID_AMD_17H_M10H_DF_F6
- PCI_DEVICE_ID_AMD_17H_M10H_ROOT
- PCI_DEVICE_ID_AMD_17H_M30H_DF_F0
- PCI_DEVICE_ID_AMD_17H_M30H_DF_F3
- PCI_DEVICE_ID_AMD_17H_M30H_DF_F4
- PCI_DEVICE_ID_AMD_17H_M30H_DF_F6
- PCI_DEVICE_ID_AMD_17H_M30H_ROOT
- PCI_DEVICE_ID_AMD_17H_M70H_DF_F0
- PCI_DEVICE_ID_AMD_17H_M70H_DF_F3
- PCI_DEVICE_ID_AMD_17H_M70H_DF_F4
- PCI_DEVICE_ID_AMD_17H_M70H_DF_F6
- PCI_DEVICE_ID_AMD_17H_ROOT
- PCI_DEVICE_ID_AMD_8111_AUDIO
- PCI_DEVICE_ID_AMD_8111_IDE
- PCI_DEVICE_ID_AMD_8111_LPC
- PCI_DEVICE_ID_AMD_8111_PCI
- PCI_DEVICE_ID_AMD_8111_SMBUS
- PCI_DEVICE_ID_AMD_8111_SMBUS2
- PCI_DEVICE_ID_AMD_8131_APIC
- PCI_DEVICE_ID_AMD_8131_BRIDGE
- PCI_DEVICE_ID_AMD_8132_BRIDGE
- PCI_DEVICE_ID_AMD_8151_0
- PCI_DEVICE_ID_AMD_CNB17H_F3
- PCI_DEVICE_ID_AMD_CNB17H_F4
- PCI_DEVICE_ID_AMD_COBRA_7401
- PCI_DEVICE_ID_AMD_CS5535_IDE
- PCI_DEVICE_ID_AMD_CS5536_AUDIO
- PCI_DEVICE_ID_AMD_CS5536_DEV_IDE
- PCI_DEVICE_ID_AMD_CS5536_EHC
- PCI_DEVICE_ID_AMD_CS5536_FLASH
- PCI_DEVICE_ID_AMD_CS5536_IDE
- PCI_DEVICE_ID_AMD_CS5536_ISA
- PCI_DEVICE_ID_AMD_CS5536_OHC
- PCI_DEVICE_ID_AMD_CS5536_UDC
- PCI_DEVICE_ID_AMD_CS5536_UOC
- PCI_DEVICE_ID_AMD_FE_GATE_7006
- PCI_DEVICE_ID_AMD_FE_GATE_7007
- PCI_DEVICE_ID_AMD_FE_GATE_700C
- PCI_DEVICE_ID_AMD_FE_GATE_700E
- PCI_DEVICE_ID_AMD_GOLAM_7450
- PCI_DEVICE_ID_AMD_HUDSON2_IDE
- PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE
- PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
- PCI_DEVICE_ID_AMD_K8_NB
- PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP
- PCI_DEVICE_ID_AMD_K8_NB_MEMCTL
- PCI_DEVICE_ID_AMD_K8_NB_MISC
- PCI_DEVICE_ID_AMD_KERNCZ_SMBUS
- PCI_DEVICE_ID_AMD_LANCE
- PCI_DEVICE_ID_AMD_LANCE_HOME
- PCI_DEVICE_ID_AMD_LX_AES
- PCI_DEVICE_ID_AMD_LX_VIDEO
- PCI_DEVICE_ID_AMD_MP2
- PCI_DEVICE_ID_AMD_NL_USB
- PCI_DEVICE_ID_AMD_OPUS_7441
- PCI_DEVICE_ID_AMD_OPUS_7443
- PCI_DEVICE_ID_AMD_OPUS_7445
- PCI_DEVICE_ID_AMD_POGO_7458
- PCI_DEVICE_ID_AMD_PROMONTORYA_1
- PCI_DEVICE_ID_AMD_PROMONTORYA_2
- PCI_DEVICE_ID_AMD_PROMONTORYA_3
- PCI_DEVICE_ID_AMD_PROMONTORYA_4
- PCI_DEVICE_ID_AMD_SCSI
- PCI_DEVICE_ID_AMD_SERENADE
- PCI_DEVICE_ID_AMD_VIPER_7409
- PCI_DEVICE_ID_AMD_VIPER_740B
- PCI_DEVICE_ID_AMD_VIPER_7410
- PCI_DEVICE_ID_AMD_VIPER_7411
- PCI_DEVICE_ID_AMD_VIPER_7413
- PCI_DEVICE_ID_AMD_VIPER_7440
- PCI_DEVICE_ID_AMD_VIPER_7443
- PCI_DEVICE_ID_AMI_MEGARAID
- PCI_DEVICE_ID_AMI_MEGARAID2
- PCI_DEVICE_ID_AMI_MEGARAID3
- PCI_DEVICE_ID_ANIGMA_MC145575
- PCI_DEVICE_ID_APPLE_BANDIT
- PCI_DEVICE_ID_APPLE_HYDRA
- PCI_DEVICE_ID_APPLE_IPID2_AGP
- PCI_DEVICE_ID_APPLE_IPID2_ATA
- PCI_DEVICE_ID_APPLE_IPID2_FW
- PCI_DEVICE_ID_APPLE_IPID2_GMAC
- PCI_DEVICE_ID_APPLE_IPID_ATA100
- PCI_DEVICE_ID_APPLE_K2_ATA100
- PCI_DEVICE_ID_APPLE_K2_GMAC
- PCI_DEVICE_ID_APPLE_SH_ATA
- PCI_DEVICE_ID_APPLE_SH_SUNGEM
- PCI_DEVICE_ID_APPLE_TIGON3
- PCI_DEVICE_ID_APPLE_U3H_AGP
- PCI_DEVICE_ID_APPLE_U3L_AGP
- PCI_DEVICE_ID_APPLE_U3_AGP
- PCI_DEVICE_ID_APPLE_U4_PCIE
- PCI_DEVICE_ID_APPLE_UNI_N_AGP
- PCI_DEVICE_ID_APPLE_UNI_N_AGP15
- PCI_DEVICE_ID_APPLE_UNI_N_AGP2
- PCI_DEVICE_ID_APPLE_UNI_N_AGP_P
- PCI_DEVICE_ID_APPLE_UNI_N_ATA
- PCI_DEVICE_ID_APPLE_UNI_N_FW
- PCI_DEVICE_ID_APPLE_UNI_N_GMAC
- PCI_DEVICE_ID_APPLE_UNI_N_GMAC2
- PCI_DEVICE_ID_APPLE_UNI_N_GMACP
- PCI_DEVICE_ID_APPLE_UNI_N_PCI15
- PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN
- PCI_DEVICE_ID_APPLICOM_PCI2000PFB
- PCI_DEVICE_ID_APPLICOM_PCIGENERIC
- PCI_DEVICE_ID_ARASAN_PHY_EMMC
- PCI_DEVICE_ID_ARECA_1110
- PCI_DEVICE_ID_ARECA_1120
- PCI_DEVICE_ID_ARECA_1130
- PCI_DEVICE_ID_ARECA_1160
- PCI_DEVICE_ID_ARECA_1170
- PCI_DEVICE_ID_ARECA_1200
- PCI_DEVICE_ID_ARECA_1201
- PCI_DEVICE_ID_ARECA_1202
- PCI_DEVICE_ID_ARECA_1203
- PCI_DEVICE_ID_ARECA_1210
- PCI_DEVICE_ID_ARECA_1214
- PCI_DEVICE_ID_ARECA_1220
- PCI_DEVICE_ID_ARECA_1230
- PCI_DEVICE_ID_ARECA_1260
- PCI_DEVICE_ID_ARECA_1270
- PCI_DEVICE_ID_ARECA_1280
- PCI_DEVICE_ID_ARECA_1300
- PCI_DEVICE_ID_ARECA_1320
- PCI_DEVICE_ID_ARECA_1380
- PCI_DEVICE_ID_ARECA_1381
- PCI_DEVICE_ID_ARECA_1680
- PCI_DEVICE_ID_ARECA_1681
- PCI_DEVICE_ID_ARECA_1880
- PCI_DEVICE_ID_ARECA_1884
- PCI_DEVICE_ID_ARTOP_8060
- PCI_DEVICE_ID_ARTOP_AEC7610
- PCI_DEVICE_ID_ARTOP_AEC7612D
- PCI_DEVICE_ID_ARTOP_AEC7612S
- PCI_DEVICE_ID_ARTOP_AEC7612SUW
- PCI_DEVICE_ID_ARTOP_AEC7612U
- PCI_DEVICE_ID_ARTOP_AEC7612UW
- PCI_DEVICE_ID_ARTOP_ATP850UF
- PCI_DEVICE_ID_ARTOP_ATP860
- PCI_DEVICE_ID_ARTOP_ATP860R
- PCI_DEVICE_ID_ARTOP_ATP865
- PCI_DEVICE_ID_ARTOP_ATP865R
- PCI_DEVICE_ID_ARTOP_ATP867A
- PCI_DEVICE_ID_ARTOP_ATP867B
- PCI_DEVICE_ID_ASMEDIA_1042A_XHCI
- PCI_DEVICE_ID_ASP_1200A
- PCI_DEVICE_ID_ASP_ABP940
- PCI_DEVICE_ID_ASP_ABP940U
- PCI_DEVICE_ID_ASP_ABP940UW
- PCI_DEVICE_ID_ASUSTEK_0675
- PCI_DEVICE_ID_ATHEROS_AR2413
- PCI_DEVICE_ID_ATHEROS_AR5210
- PCI_DEVICE_ID_ATHEROS_AR5210_AP
- PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT
- PCI_DEVICE_ID_ATHEROS_AR5211
- PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT
- PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B
- PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY
- PCI_DEVICE_ID_ATHEROS_AR5212
- PCI_DEVICE_ID_ATHEROS_AR5212_0014
- PCI_DEVICE_ID_ATHEROS_AR5212_0015
- PCI_DEVICE_ID_ATHEROS_AR5212_0016
- PCI_DEVICE_ID_ATHEROS_AR5212_0017
- PCI_DEVICE_ID_ATHEROS_AR5212_0018
- PCI_DEVICE_ID_ATHEROS_AR5212_0019
- PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT
- PCI_DEVICE_ID_ATHEROS_AR5212_FPGA
- PCI_DEVICE_ID_ATHEROS_AR5212_IBM
- PCI_DEVICE_ID_ATHEROS_AR5311
- PCI_DEVICE_ID_ATHEROS_AR5312_REV2
- PCI_DEVICE_ID_ATHEROS_AR5312_REV7
- PCI_DEVICE_ID_ATHEROS_AR5312_REV8
- PCI_DEVICE_ID_ATHEROS_AR5413
- PCI_DEVICE_ID_ATHEROS_AR5416
- PCI_DEVICE_ID_ATHEROS_AR5418
- PCI_DEVICE_ID_ATHEROS_AR5424
- PCI_DEVICE_ID_ATHEROS_L1D
- PCI_DEVICE_ID_ATHEROS_L1D_2_0
- PCI_DEVICE_ID_ATHEROS_L2C_B
- PCI_DEVICE_ID_ATHEROS_L2C_B2
- PCI_DEVICE_ID_ATI_210888CX
- PCI_DEVICE_ID_ATI_210888GX
- PCI_DEVICE_ID_ATI_215CT222
- PCI_DEVICE_ID_ATI_215ET222
- PCI_DEVICE_ID_ATI_215GB
- PCI_DEVICE_ID_ATI_215GD
- PCI_DEVICE_ID_ATI_215GI
- PCI_DEVICE_ID_ATI_215GP
- PCI_DEVICE_ID_ATI_215GQ
- PCI_DEVICE_ID_ATI_215GT
- PCI_DEVICE_ID_ATI_215GTB
- PCI_DEVICE_ID_ATI_215XL
- PCI_DEVICE_ID_ATI_215_IV
- PCI_DEVICE_ID_ATI_215_IW
- PCI_DEVICE_ID_ATI_215_IZ
- PCI_DEVICE_ID_ATI_215_LB
- PCI_DEVICE_ID_ATI_215_LD
- PCI_DEVICE_ID_ATI_215_LG
- PCI_DEVICE_ID_ATI_215_LI
- PCI_DEVICE_ID_ATI_215_LM
- PCI_DEVICE_ID_ATI_215_LN
- PCI_DEVICE_ID_ATI_215_LR
- PCI_DEVICE_ID_ATI_215_LS
- PCI_DEVICE_ID_ATI_264VT
- PCI_DEVICE_ID_ATI_264VU
- PCI_DEVICE_ID_ATI_264VV
- PCI_DEVICE_ID_ATI_264_LT
- PCI_DEVICE_ID_ATI_68800
- PCI_DEVICE_ID_ATI_IXP200_IDE
- PCI_DEVICE_ID_ATI_IXP200_SMBUS
- PCI_DEVICE_ID_ATI_IXP300_IDE
- PCI_DEVICE_ID_ATI_IXP300_SATA
- PCI_DEVICE_ID_ATI_IXP300_SMBUS
- PCI_DEVICE_ID_ATI_IXP400_IDE
- PCI_DEVICE_ID_ATI_IXP400_SATA
- PCI_DEVICE_ID_ATI_IXP400_SATA2
- PCI_DEVICE_ID_ATI_IXP400_SMBUS
- PCI_DEVICE_ID_ATI_IXP600_IDE
- PCI_DEVICE_ID_ATI_IXP600_SATA
- PCI_DEVICE_ID_ATI_IXP700_IDE
- PCI_DEVICE_ID_ATI_IXP700_SATA
- PCI_DEVICE_ID_ATI_RADEON_BB
- PCI_DEVICE_ID_ATI_RADEON_Id
- PCI_DEVICE_ID_ATI_RADEON_Ie
- PCI_DEVICE_ID_ATI_RADEON_If
- PCI_DEVICE_ID_ATI_RADEON_Ig
- PCI_DEVICE_ID_ATI_RADEON_LW
- PCI_DEVICE_ID_ATI_RADEON_LX
- PCI_DEVICE_ID_ATI_RADEON_LY
- PCI_DEVICE_ID_ATI_RADEON_LZ
- PCI_DEVICE_ID_ATI_RADEON_Ld
- PCI_DEVICE_ID_ATI_RADEON_Le
- PCI_DEVICE_ID_ATI_RADEON_Lf
- PCI_DEVICE_ID_ATI_RADEON_Lg
- PCI_DEVICE_ID_ATI_RADEON_ND
- PCI_DEVICE_ID_ATI_RADEON_NE
- PCI_DEVICE_ID_ATI_RADEON_NF
- PCI_DEVICE_ID_ATI_RADEON_NG
- PCI_DEVICE_ID_ATI_RADEON_QD
- PCI_DEVICE_ID_ATI_RADEON_QE
- PCI_DEVICE_ID_ATI_RADEON_QF
- PCI_DEVICE_ID_ATI_RADEON_QG
- PCI_DEVICE_ID_ATI_RADEON_QL
- PCI_DEVICE_ID_ATI_RADEON_QM
- PCI_DEVICE_ID_ATI_RADEON_QN
- PCI_DEVICE_ID_ATI_RADEON_QO
- PCI_DEVICE_ID_ATI_RADEON_QW
- PCI_DEVICE_ID_ATI_RADEON_QX
- PCI_DEVICE_ID_ATI_RADEON_QY
- PCI_DEVICE_ID_ATI_RADEON_QZ
- PCI_DEVICE_ID_ATI_RADEON_Ql
- PCI_DEVICE_ID_ATI_RADEON_Ya
- PCI_DEVICE_ID_ATI_RADEON_Yd
- PCI_DEVICE_ID_ATI_RAGE128_LE
- PCI_DEVICE_ID_ATI_RAGE128_LF
- PCI_DEVICE_ID_ATI_RAGE128_MF
- PCI_DEVICE_ID_ATI_RAGE128_ML
- PCI_DEVICE_ID_ATI_RAGE128_PA
- PCI_DEVICE_ID_ATI_RAGE128_PB
- PCI_DEVICE_ID_ATI_RAGE128_PC
- PCI_DEVICE_ID_ATI_RAGE128_PD
- PCI_DEVICE_ID_ATI_RAGE128_PE
- PCI_DEVICE_ID_ATI_RAGE128_PF
- PCI_DEVICE_ID_ATI_RAGE128_PG
- PCI_DEVICE_ID_ATI_RAGE128_PH
- PCI_DEVICE_ID_ATI_RAGE128_PI
- PCI_DEVICE_ID_ATI_RAGE128_PJ
- PCI_DEVICE_ID_ATI_RAGE128_PK
- PCI_DEVICE_ID_ATI_RAGE128_PL
- PCI_DEVICE_ID_ATI_RAGE128_PM
- PCI_DEVICE_ID_ATI_RAGE128_PN
- PCI_DEVICE_ID_ATI_RAGE128_PO
- PCI_DEVICE_ID_ATI_RAGE128_PP
- PCI_DEVICE_ID_ATI_RAGE128_PQ
- PCI_DEVICE_ID_ATI_RAGE128_PR
- PCI_DEVICE_ID_ATI_RAGE128_PS
- PCI_DEVICE_ID_ATI_RAGE128_PT
- PCI_DEVICE_ID_ATI_RAGE128_PU
- PCI_DEVICE_ID_ATI_RAGE128_PV
- PCI_DEVICE_ID_ATI_RAGE128_PW
- PCI_DEVICE_ID_ATI_RAGE128_PX
- PCI_DEVICE_ID_ATI_RAGE128_RE
- PCI_DEVICE_ID_ATI_RAGE128_RF
- PCI_DEVICE_ID_ATI_RAGE128_RG
- PCI_DEVICE_ID_ATI_RAGE128_RK
- PCI_DEVICE_ID_ATI_RAGE128_RL
- PCI_DEVICE_ID_ATI_RAGE128_SE
- PCI_DEVICE_ID_ATI_RAGE128_SF
- PCI_DEVICE_ID_ATI_RAGE128_SG
- PCI_DEVICE_ID_ATI_RAGE128_SH
- PCI_DEVICE_ID_ATI_RAGE128_SK
- PCI_DEVICE_ID_ATI_RAGE128_SL
- PCI_DEVICE_ID_ATI_RAGE128_SM
- PCI_DEVICE_ID_ATI_RAGE128_SN
- PCI_DEVICE_ID_ATI_RAGE128_TF
- PCI_DEVICE_ID_ATI_RAGE128_TL
- PCI_DEVICE_ID_ATI_RAGE128_TR
- PCI_DEVICE_ID_ATI_RAGE128_TS
- PCI_DEVICE_ID_ATI_RAGE128_TT
- PCI_DEVICE_ID_ATI_RAGE128_TU
- PCI_DEVICE_ID_ATI_RS100
- PCI_DEVICE_ID_ATI_RS200
- PCI_DEVICE_ID_ATI_RS200_B
- PCI_DEVICE_ID_ATI_RS250
- PCI_DEVICE_ID_ATI_RS300_100
- PCI_DEVICE_ID_ATI_RS300_133
- PCI_DEVICE_ID_ATI_RS300_166
- PCI_DEVICE_ID_ATI_RS300_200
- PCI_DEVICE_ID_ATI_RS350_100
- PCI_DEVICE_ID_ATI_RS350_133
- PCI_DEVICE_ID_ATI_RS350_166
- PCI_DEVICE_ID_ATI_RS350_200
- PCI_DEVICE_ID_ATI_RS400_100
- PCI_DEVICE_ID_ATI_RS400_133
- PCI_DEVICE_ID_ATI_RS400_166
- PCI_DEVICE_ID_ATI_RS400_200
- PCI_DEVICE_ID_ATI_RS480
- PCI_DEVICE_ID_ATI_SBX00_SMBUS
- PCI_DEVICE_ID_ATTANSIC_L1
- PCI_DEVICE_ID_ATTANSIC_L1C
- PCI_DEVICE_ID_ATTANSIC_L1E
- PCI_DEVICE_ID_ATTANSIC_L2
- PCI_DEVICE_ID_ATTANSIC_L2C
- PCI_DEVICE_ID_ATT_VENUS_MODEM
- PCI_DEVICE_ID_AUREAL_ADVANTAGE
- PCI_DEVICE_ID_AUREAL_VORTEX_1
- PCI_DEVICE_ID_AUREAL_VORTEX_2
- PCI_DEVICE_ID_AVM_A1
- PCI_DEVICE_ID_AVM_A1_V2
- PCI_DEVICE_ID_AVM_B1
- PCI_DEVICE_ID_AVM_C2
- PCI_DEVICE_ID_AVM_C4
- PCI_DEVICE_ID_AVM_T1
- PCI_DEVICE_ID_BALIUS
- PCI_DEVICE_ID_BCM1250_HT
- PCI_DEVICE_ID_BCM1250_PCI
- PCI_DEVICE_ID_BCM4401
- PCI_DEVICE_ID_BCM4401B0
- PCI_DEVICE_ID_BCM4401B1
- PCI_DEVICE_ID_BC_6110_16
- PCI_DEVICE_ID_BC_6110_4
- PCI_DEVICE_ID_BC_6110_8
- PCI_DEVICE_ID_BC_SOLO_16
- PCI_DEVICE_ID_BC_SOLO_4
- PCI_DEVICE_ID_BC_SOLO_9
- PCI_DEVICE_ID_BELKIN_F5D7010V7
- PCI_DEVICE_ID_BERKOM_A1T
- PCI_DEVICE_ID_BERKOM_A4T
- PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO
- PCI_DEVICE_ID_BERKOM_T_CONCEPT
- PCI_DEVICE_ID_BMID
- PCI_DEVICE_ID_BROADCOM_TRUMANAGE
- PCI_DEVICE_ID_BROCADE_CT
- PCI_DEVICE_ID_BROCADE_CT_FC
- PCI_DEVICE_ID_BROCADE_FC_8G1P
- PCI_DEVICE_ID_BROOKTREE_878
- PCI_DEVICE_ID_BROOKTREE_879
- PCI_DEVICE_ID_BSMB
- PCI_DEVICE_ID_BT848
- PCI_DEVICE_ID_BT849
- PCI_DEVICE_ID_BT878
- PCI_DEVICE_ID_BT879
- PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT
- PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER
- PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC
- PCI_DEVICE_ID_CAVIUM_PTP
- PCI_DEVICE_ID_CAVIUM_RST
- PCI_DEVICE_ID_CB108
- PCI_DEVICE_ID_CB114
- PCI_DEVICE_ID_CB134I
- PCI_DEVICE_ID_CCD_2BD0
- PCI_DEVICE_ID_CCD_B000
- PCI_DEVICE_ID_CCD_B006
- PCI_DEVICE_ID_CCD_B007
- PCI_DEVICE_ID_CCD_B008
- PCI_DEVICE_ID_CCD_B009
- PCI_DEVICE_ID_CCD_B00A
- PCI_DEVICE_ID_CCD_B00B
- PCI_DEVICE_ID_CCD_B00C
- PCI_DEVICE_ID_CCD_B100
- PCI_DEVICE_ID_CCD_B700
- PCI_DEVICE_ID_CCD_B701
- PCI_DEVICE_ID_CCD_HFC4S
- PCI_DEVICE_ID_CCD_HFC8S
- PCI_DEVICE_ID_CCD_HFCE1
- PCI_DEVICE_ID_CENATEK_IDE
- PCI_DEVICE_ID_CENTAUR
- PCI_DEVICE_ID_CHT_PMC
- PCI_DEVICE_ID_CIRRUS_4610
- PCI_DEVICE_ID_CIRRUS_4612
- PCI_DEVICE_ID_CIRRUS_4615
- PCI_DEVICE_ID_CIRRUS_5430
- PCI_DEVICE_ID_CIRRUS_5434_4
- PCI_DEVICE_ID_CIRRUS_5434_8
- PCI_DEVICE_ID_CIRRUS_5436
- PCI_DEVICE_ID_CIRRUS_5446
- PCI_DEVICE_ID_CIRRUS_5462
- PCI_DEVICE_ID_CIRRUS_5464
- PCI_DEVICE_ID_CIRRUS_5465
- PCI_DEVICE_ID_CIRRUS_5480
- PCI_DEVICE_ID_CIRRUS_6729
- PCI_DEVICE_ID_CIRRUS_6832
- PCI_DEVICE_ID_CIRRUS_7543
- PCI_DEVICE_ID_CIRRUS_7548
- PCI_DEVICE_ID_CISCO_FNIC
- PCI_DEVICE_ID_CISCO_SNIC
- PCI_DEVICE_ID_CISCO_VIC_ENET
- PCI_DEVICE_ID_CISCO_VIC_ENET_DYN
- PCI_DEVICE_ID_CISCO_VIC_ENET_VF
- PCI_DEVICE_ID_CISCO_VIC_USPACE_NIC
- PCI_DEVICE_ID_CLASSIC_4
- PCI_DEVICE_ID_CLASSIC_4_422
- PCI_DEVICE_ID_CLASSIC_8
- PCI_DEVICE_ID_CLASSIC_8_422
- PCI_DEVICE_ID_CLOVERVIEW
- PCI_DEVICE_ID_CMD_643
- PCI_DEVICE_ID_CMD_646
- PCI_DEVICE_ID_CMD_648
- PCI_DEVICE_ID_CMD_649
- PCI_DEVICE_ID_CMEDIA_CM8338A
- PCI_DEVICE_ID_CMEDIA_CM8338B
- PCI_DEVICE_ID_CMEDIA_CM8738
- PCI_DEVICE_ID_CMEDIA_CM8738B
- PCI_DEVICE_ID_CNET_GIGACARD
- PCI_DEVICE_ID_COBALT
- PCI_DEVICE_ID_COMMTECH_2324PCI335
- PCI_DEVICE_ID_COMMTECH_2328PCI335
- PCI_DEVICE_ID_COMMTECH_4222PCI335
- PCI_DEVICE_ID_COMMTECH_4222PCIE
- PCI_DEVICE_ID_COMMTECH_4224PCI335
- PCI_DEVICE_ID_COMMTECH_4224PCIE
- PCI_DEVICE_ID_COMMTECH_4228PCIE
- PCI_DEVICE_ID_COMPAQ_42XX
- PCI_DEVICE_ID_COMPAQ_CISS
- PCI_DEVICE_ID_COMPAQ_CISSB
- PCI_DEVICE_ID_COMPAQ_CISSC
- PCI_DEVICE_ID_COMPAQ_NETEL10
- PCI_DEVICE_ID_COMPAQ_NETEL100
- PCI_DEVICE_ID_COMPAQ_NETEL100D
- PCI_DEVICE_ID_COMPAQ_NETEL100I
- PCI_DEVICE_ID_COMPAQ_NETEL100PI
- PCI_DEVICE_ID_COMPAQ_NETFLEX3B
- PCI_DEVICE_ID_COMPAQ_NETFLEX3I
- PCI_DEVICE_ID_COMPAQ_SMART2P
- PCI_DEVICE_ID_COMPAQ_TACHYON
- PCI_DEVICE_ID_COMPAQ_THUNDER
- PCI_DEVICE_ID_COMPAQ_TOKENRING
- PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE
- PCI_DEVICE_ID_COMPEX2_100VG
- PCI_DEVICE_ID_COMPEX_ENET100VG4
- PCI_DEVICE_ID_COMPUTONE_PG
- PCI_DEVICE_ID_CONTAQ_82C693
- PCI_DEVICE_ID_CP102UF
- PCI_DEVICE_ID_CP112UL
- PCI_DEVICE_ID_CP114UL
- PCI_DEVICE_ID_CP138U
- PCI_DEVICE_ID_CREATIVE_20K1
- PCI_DEVICE_ID_CREATIVE_20K2
- PCI_DEVICE_ID_CREATIVE_EMU10K1
- PCI_DEVICE_ID_CREATIVE_SB1394
- PCI_DEVICE_ID_CRP16INTF
- PCI_DEVICE_ID_CT_65545
- PCI_DEVICE_ID_CT_65548
- PCI_DEVICE_ID_CT_65550
- PCI_DEVICE_ID_CT_65554
- PCI_DEVICE_ID_CT_65555
- PCI_DEVICE_ID_CT_69000
- PCI_DEVICE_ID_CX2300_VID
- PCI_DEVICE_ID_CX23418
- PCI_DEVICE_ID_CYCLOM_4Y_Hi
- PCI_DEVICE_ID_CYCLOM_4Y_Lo
- PCI_DEVICE_ID_CYCLOM_8Y_Hi
- PCI_DEVICE_ID_CYCLOM_8Y_Lo
- PCI_DEVICE_ID_CYCLOM_Y_Hi
- PCI_DEVICE_ID_CYCLOM_Y_Lo
- PCI_DEVICE_ID_CYCLOM_Z_Hi
- PCI_DEVICE_ID_CYCLOM_Z_Lo
- PCI_DEVICE_ID_CYRIX_5510
- PCI_DEVICE_ID_CYRIX_5520
- PCI_DEVICE_ID_CYRIX_5530_AUDIO
- PCI_DEVICE_ID_CYRIX_5530_IDE
- PCI_DEVICE_ID_CYRIX_5530_LEGACY
- PCI_DEVICE_ID_CYRIX_5530_VIDEO
- PCI_DEVICE_ID_CYRIX_PCI_MASTER
- PCI_DEVICE_ID_DAKTRONICS
- PCI_DEVICE_ID_DAKTRONICS_KADOKA_P2KR0
- PCI_DEVICE_ID_DCI_PCCOM2
- PCI_DEVICE_ID_DCI_PCCOM4
- PCI_DEVICE_ID_DCI_PCCOM8
- PCI_DEVICE_ID_DEC_21052
- PCI_DEVICE_ID_DEC_21142
- PCI_DEVICE_ID_DEC_21150
- PCI_DEVICE_ID_DEC_21152
- PCI_DEVICE_ID_DEC_21153
- PCI_DEVICE_ID_DEC_21154
- PCI_DEVICE_ID_DEC_21285
- PCI_DEVICE_ID_DEC_BRD
- PCI_DEVICE_ID_DEC_FDDI
- PCI_DEVICE_ID_DEC_TGA
- PCI_DEVICE_ID_DEC_TGA2
- PCI_DEVICE_ID_DEC_TULIP
- PCI_DEVICE_ID_DEC_TULIP_FAST
- PCI_DEVICE_ID_DEC_TULIP_PLUS
- PCI_DEVICE_ID_DELL_PERC5
- PCI_DEVICE_ID_DELL_RAC4
- PCI_DEVICE_ID_DELL_RACIII
- PCI_DEVICE_ID_DIGIUM_HFC4S
- PCI_DEVICE_ID_DIGI_DF_M_A
- PCI_DEVICE_ID_DIGI_DF_M_E
- PCI_DEVICE_ID_DIGI_DF_M_IOM2_A
- PCI_DEVICE_ID_DIGI_DF_M_IOM2_E
- PCI_DEVICE_ID_DIGI_NEO_8
- PCI_DEVICE_ID_DISCOVERY
- PCI_DEVICE_ID_DLINK_DGE510T
- PCI_DEVICE_ID_DM05
- PCI_DEVICE_ID_DM1105
- PCI_DEVICE_ID_DOBSON
- PCI_DEVICE_ID_DOMEX_DMX3191D
- PCI_DEVICE_ID_DPT
- PCI_DEVICE_ID_DRAGONFLY
- PCI_DEVICE_ID_DUNORD_I3000
- PCI_DEVICE_ID_DW2002
- PCI_DEVICE_ID_DW2004
- PCI_DEVICE_ID_DYNALINK_IS64PH
- PCI_DEVICE_ID_ECTIVA_EV1938
- PCI_DEVICE_ID_EFAR_SLC90E66_0
- PCI_DEVICE_ID_EFAR_SLC90E66_1
- PCI_DEVICE_ID_EFAR_SLC90E66_3
- PCI_DEVICE_ID_EFFICEON
- PCI_DEVICE_ID_EF_ATM_ASIC
- PCI_DEVICE_ID_EF_ATM_FPGA
- PCI_DEVICE_ID_EF_ATM_LANAI2
- PCI_DEVICE_ID_EF_ATM_LANAIHB
- PCI_DEVICE_ID_EG20T_PCH_DMA_4CH
- PCI_DEVICE_ID_EG20T_PCH_DMA_8CH
- PCI_DEVICE_ID_EICON_DIVA20
- PCI_DEVICE_ID_EICON_DIVA201
- PCI_DEVICE_ID_EICON_DIVA202
- PCI_DEVICE_ID_EICON_DIVA20_U
- PCI_DEVICE_ID_EICON_MAESTRA
- PCI_DEVICE_ID_EICON_MAESTRAP
- PCI_DEVICE_ID_EICON_MAESTRAQ
- PCI_DEVICE_ID_EICON_MAESTRAQ_U
- PCI_DEVICE_ID_EJ168
- PCI_DEVICE_ID_ELSA_MICROLINK
- PCI_DEVICE_ID_ELSA_QS3000
- PCI_DEVICE_ID_ENDRUN_1588
- PCI_DEVICE_ID_ENE_1211
- PCI_DEVICE_ID_ENE_1225
- PCI_DEVICE_ID_ENE_1410
- PCI_DEVICE_ID_ENE_1420
- PCI_DEVICE_ID_ENE_710
- PCI_DEVICE_ID_ENE_712
- PCI_DEVICE_ID_ENE_720
- PCI_DEVICE_ID_ENE_722
- PCI_DEVICE_ID_ENE_CB710_FLASH
- PCI_DEVICE_ID_ENE_CB712_SD
- PCI_DEVICE_ID_ENE_CB712_SD_2
- PCI_DEVICE_ID_ENE_CB714_SD
- PCI_DEVICE_ID_ENE_CB714_SD_2
- PCI_DEVICE_ID_ENSONIQ_CT5880
- PCI_DEVICE_ID_ENSONIQ_ES1370
- PCI_DEVICE_ID_ENSONIQ_ES1371
- PCI_DEVICE_ID_ESDGMBH_CPCIASIO4
- PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER
- PCI_DEVICE_ID_ESS_ALLEGRO
- PCI_DEVICE_ID_ESS_ALLEGRO_1
- PCI_DEVICE_ID_ESS_CANYON3D_2
- PCI_DEVICE_ID_ESS_CANYON3D_2LE
- PCI_DEVICE_ID_ESS_ESS0100
- PCI_DEVICE_ID_ESS_ESS1968
- PCI_DEVICE_ID_ESS_ESS1978
- PCI_DEVICE_ID_ESS_MAESTRO3
- PCI_DEVICE_ID_ESS_MAESTRO3_1
- PCI_DEVICE_ID_ESS_MAESTRO3_2
- PCI_DEVICE_ID_ESS_MAESTRO3_HW
- PCI_DEVICE_ID_EXAR_XR17C152
- PCI_DEVICE_ID_EXAR_XR17C154
- PCI_DEVICE_ID_EXAR_XR17C158
- PCI_DEVICE_ID_EXAR_XR17V352
- PCI_DEVICE_ID_EXAR_XR17V354
- PCI_DEVICE_ID_EXAR_XR17V358
- PCI_DEVICE_ID_EXAR_XR17V4358
- PCI_DEVICE_ID_EXAR_XR17V8358
- PCI_DEVICE_ID_FALCON
- PCI_DEVICE_ID_FARALLON_PN9000SX
- PCI_DEVICE_ID_FARALLON_PN9100T
- PCI_DEVICE_ID_FARSITE_T1U
- PCI_DEVICE_ID_FARSITE_T2P
- PCI_DEVICE_ID_FARSITE_T2U
- PCI_DEVICE_ID_FARSITE_T4P
- PCI_DEVICE_ID_FARSITE_T4U
- PCI_DEVICE_ID_FARSITE_TE1
- PCI_DEVICE_ID_FARSITE_TE1C
- PCI_DEVICE_ID_FD_36C70
- PCI_DEVICE_ID_FIREFLY
- PCI_DEVICE_ID_FM801_GP
- PCI_DEVICE_ID_FORE_HE
- PCI_DEVICE_ID_FORE_PCA200E
- PCI_DEVICE_ID_FRESCO_LOGIC_FL1009
- PCI_DEVICE_ID_FRESCO_LOGIC_FL1400
- PCI_DEVICE_ID_FRESCO_LOGIC_PDK
- PCI_DEVICE_ID_FS70_FLASH
- PCI_DEVICE_ID_FS80_FLASH
- PCI_DEVICE_ID_FUJITSU_CARMINE
- PCI_DEVICE_ID_FUJITSU_CORALP
- PCI_DEVICE_ID_FUJITSU_CORALPA
- PCI_DEVICE_ID_FUJITSU_FS155
- PCI_DEVICE_ID_FUJITSU_FS50
- PCI_DEVICE_ID_FUSION879
- PCI_DEVICE_ID_GEFORCE_6800A
- PCI_DEVICE_ID_GEFORCE_6800A_LE
- PCI_DEVICE_ID_GEFORCE_GO_6800
- PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA
- PCI_DEVICE_ID_GE_SPI
- PCI_DEVICE_ID_GL880S_UHCI
- PCI_DEVICE_ID_GLI_9750
- PCI_DEVICE_ID_GLI_9755
- PCI_DEVICE_ID_GUILLEMOT_MAXIRADIO
- PCI_DEVICE_ID_HELIOS
- PCI_DEVICE_ID_HELIOS_DCSP
- PCI_DEVICE_ID_HELIOS_SCSP
- PCI_DEVICE_ID_HERC_UNI
- PCI_DEVICE_ID_HERC_WIN
- PCI_DEVICE_ID_HIFN_7955
- PCI_DEVICE_ID_HIFN_7956
- PCI_DEVICE_ID_HILSCHER_NETPLC
- PCI_DEVICE_ID_HILSCHER_NETX
- PCI_DEVICE_ID_HINT_VXPROII_IDE
- PCI_DEVICE_ID_HOLTEK_6565
- PCI_DEVICE_ID_HORNET
- PCI_DEVICE_ID_HP_CISSA
- PCI_DEVICE_ID_HP_CISSC
- PCI_DEVICE_ID_HP_CISSD
- PCI_DEVICE_ID_HP_CISSE
- PCI_DEVICE_ID_HP_CISSF
- PCI_DEVICE_ID_HP_CISSH
- PCI_DEVICE_ID_HP_CISSI
- PCI_DEVICE_ID_HP_DIVA
- PCI_DEVICE_ID_HP_DIVA_AUX
- PCI_DEVICE_ID_HP_DIVA_EVEREST
- PCI_DEVICE_ID_HP_DIVA_HALFDOME
- PCI_DEVICE_ID_HP_DIVA_HURRICANE
- PCI_DEVICE_ID_HP_DIVA_KEYSTONE
- PCI_DEVICE_ID_HP_DIVA_MAESTRO
- PCI_DEVICE_ID_HP_DIVA_POWERBAR
- PCI_DEVICE_ID_HP_DIVA_RMP3
- PCI_DEVICE_ID_HP_DIVA_TOSCA1
- PCI_DEVICE_ID_HP_DIVA_TOSCA2
- PCI_DEVICE_ID_HP_J2585A
- PCI_DEVICE_ID_HP_J2585B
- PCI_DEVICE_ID_HP_J2970A
- PCI_DEVICE_ID_HP_J2973A
- PCI_DEVICE_ID_HP_MMC
- PCI_DEVICE_ID_HP_PCIX_LBA
- PCI_DEVICE_ID_HP_REO_IOC
- PCI_DEVICE_ID_HP_SX1000_IOC
- PCI_DEVICE_ID_HP_SX2000_IOC
- PCI_DEVICE_ID_HP_TACHLITE
- PCI_DEVICE_ID_HP_TACHYON
- PCI_DEVICE_ID_HP_VISUALIZE_EG
- PCI_DEVICE_ID_HP_VISUALIZE_FX2
- PCI_DEVICE_ID_HP_VISUALIZE_FX4
- PCI_DEVICE_ID_HP_VISUALIZE_FX6
- PCI_DEVICE_ID_HP_VISUALIZE_FXE
- PCI_DEVICE_ID_HP_ZX1_IOC
- PCI_DEVICE_ID_HP_ZX2_IOC
- PCI_DEVICE_ID_HYPERCOPE_PLX
- PCI_DEVICE_ID_HYPERV_VIDEO
- PCI_DEVICE_ID_I5000_BRANCH_0
- PCI_DEVICE_ID_I5000_BRANCH_1
- PCI_DEVICE_ID_IBM_BRIARD
- PCI_DEVICE_ID_IBM_CALGARY
- PCI_DEVICE_ID_IBM_CALIOC2
- PCI_DEVICE_ID_IBM_CITRINE
- PCI_DEVICE_ID_IBM_CORSA
- PCI_DEVICE_ID_IBM_CPC710_PCI64
- PCI_DEVICE_ID_IBM_CROCODILE
- PCI_DEVICE_ID_IBM_CROC_FPGA_E2
- PCI_DEVICE_ID_IBM_FLASH_GT
- PCI_DEVICE_ID_IBM_GEMSTONE
- PCI_DEVICE_ID_IBM_GXT4000P
- PCI_DEVICE_ID_IBM_GXT4500P
- PCI_DEVICE_ID_IBM_GXT6000P
- PCI_DEVICE_ID_IBM_GXT6500P
- PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1
- PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2
- PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL
- PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM
- PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE
- PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX
- PCI_DEVICE_ID_IBM_ISM
- PCI_DEVICE_ID_IBM_OBSIDIAN
- PCI_DEVICE_ID_IBM_OBSIDIAN_E
- PCI_DEVICE_ID_IBM_RATTLESNAKE
- PCI_DEVICE_ID_IBM_SNIPE
- PCI_DEVICE_ID_IBM_TR
- PCI_DEVICE_ID_IBM_TR_WAKE
- PCI_DEVICE_ID_ICE_1712
- PCI_DEVICE_ID_IDT_89HPES12NT12G2
- PCI_DEVICE_ID_IDT_89HPES16NT16G2
- PCI_DEVICE_ID_IDT_89HPES24NT24G2
- PCI_DEVICE_ID_IDT_89HPES24NT6AG2
- PCI_DEVICE_ID_IDT_89HPES32NT24AG2
- PCI_DEVICE_ID_IDT_89HPES32NT24BG2
- PCI_DEVICE_ID_IDT_89HPES32NT8AG2
- PCI_DEVICE_ID_IDT_89HPES32NT8BG2
- PCI_DEVICE_ID_IDT_IDT77201
- PCI_DEVICE_ID_IDT_IDT77252
- PCI_DEVICE_ID_IDT_TSI310
- PCI_DEVICE_ID_IMS_TT128
- PCI_DEVICE_ID_IMS_TT3D
- PCI_DEVICE_ID_INTASHIELD_IS200
- PCI_DEVICE_ID_INTASHIELD_IS400
- PCI_DEVICE_ID_INTEL0
- PCI_DEVICE_ID_INTEL1
- PCI_DEVICE_ID_INTEL_3000_HB
- PCI_DEVICE_ID_INTEL_3100_0
- PCI_DEVICE_ID_INTEL_3100_1_ERR
- PCI_DEVICE_ID_INTEL_3200_HB
- PCI_DEVICE_ID_INTEL_440MX
- PCI_DEVICE_ID_INTEL_440MX_6
- PCI_DEVICE_ID_INTEL_5000_ERR
- PCI_DEVICE_ID_INTEL_5000_FBD0
- PCI_DEVICE_ID_INTEL_5000_FBD1
- PCI_DEVICE_ID_INTEL_5100_16
- PCI_DEVICE_ID_INTEL_5100_19
- PCI_DEVICE_ID_INTEL_5100_21
- PCI_DEVICE_ID_INTEL_5100_22
- PCI_DEVICE_ID_INTEL_5400_ERR
- PCI_DEVICE_ID_INTEL_5400_FBD0
- PCI_DEVICE_ID_INTEL_5400_FBD1
- PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX
- PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN
- PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS
- PCI_DEVICE_ID_INTEL_7205_0
- PCI_DEVICE_ID_INTEL_7205_1_ERR
- PCI_DEVICE_ID_INTEL_7320_0
- PCI_DEVICE_ID_INTEL_7320_1_ERR
- PCI_DEVICE_ID_INTEL_7500_0
- PCI_DEVICE_ID_INTEL_7500_1_ERR
- PCI_DEVICE_ID_INTEL_7501_0
- PCI_DEVICE_ID_INTEL_7501_1_ERR
- PCI_DEVICE_ID_INTEL_7505_0
- PCI_DEVICE_ID_INTEL_7505_1_ERR
- PCI_DEVICE_ID_INTEL_7520_0
- PCI_DEVICE_ID_INTEL_7520_1_ERR
- PCI_DEVICE_ID_INTEL_7525_0
- PCI_DEVICE_ID_INTEL_7525_1_ERR
- PCI_DEVICE_ID_INTEL_80332_0
- PCI_DEVICE_ID_INTEL_80332_1
- PCI_DEVICE_ID_INTEL_80333_0
- PCI_DEVICE_ID_INTEL_80333_1
- PCI_DEVICE_ID_INTEL_80960_RP
- PCI_DEVICE_ID_INTEL_82092AA_0
- PCI_DEVICE_ID_INTEL_82371AB
- PCI_DEVICE_ID_INTEL_82371AB_0
- PCI_DEVICE_ID_INTEL_82371AB_2
- PCI_DEVICE_ID_INTEL_82371AB_3
- PCI_DEVICE_ID_INTEL_82371FB_0
- PCI_DEVICE_ID_INTEL_82371FB_1
- PCI_DEVICE_ID_INTEL_82371MX
- PCI_DEVICE_ID_INTEL_82371SB_0
- PCI_DEVICE_ID_INTEL_82371SB_1
- PCI_DEVICE_ID_INTEL_82371SB_2
- PCI_DEVICE_ID_INTEL_82372FB_1
- PCI_DEVICE_ID_INTEL_82375
- PCI_DEVICE_ID_INTEL_82378
- PCI_DEVICE_ID_INTEL_82380FB
- PCI_DEVICE_ID_INTEL_82424
- PCI_DEVICE_ID_INTEL_82437
- PCI_DEVICE_ID_INTEL_82437VX
- PCI_DEVICE_ID_INTEL_82439
- PCI_DEVICE_ID_INTEL_82439TX
- PCI_DEVICE_ID_INTEL_82441
- PCI_DEVICE_ID_INTEL_82443BX_0
- PCI_DEVICE_ID_INTEL_82443BX_1
- PCI_DEVICE_ID_INTEL_82443BX_2
- PCI_DEVICE_ID_INTEL_82443GX_0
- PCI_DEVICE_ID_INTEL_82443GX_2
- PCI_DEVICE_ID_INTEL_82443LX_0
- PCI_DEVICE_ID_INTEL_82443LX_1
- PCI_DEVICE_ID_INTEL_82443MX_0
- PCI_DEVICE_ID_INTEL_82443MX_1
- PCI_DEVICE_ID_INTEL_82443MX_3
- PCI_DEVICE_ID_INTEL_82450GX
- PCI_DEVICE_ID_INTEL_82451NX
- PCI_DEVICE_ID_INTEL_82454GX
- PCI_DEVICE_ID_INTEL_82454NX
- PCI_DEVICE_ID_INTEL_82573E_SOL
- PCI_DEVICE_ID_INTEL_82573L_SOL
- PCI_DEVICE_ID_INTEL_8257X_SOL
- PCI_DEVICE_ID_INTEL_82599_SFP_VF
- PCI_DEVICE_ID_INTEL_82801AA_0
- PCI_DEVICE_ID_INTEL_82801AA_1
- PCI_DEVICE_ID_INTEL_82801AA_3
- PCI_DEVICE_ID_INTEL_82801AA_5
- PCI_DEVICE_ID_INTEL_82801AA_6
- PCI_DEVICE_ID_INTEL_82801AA_8
- PCI_DEVICE_ID_INTEL_82801AB_0
- PCI_DEVICE_ID_INTEL_82801AB_1
- PCI_DEVICE_ID_INTEL_82801AB_3
- PCI_DEVICE_ID_INTEL_82801AB_5
- PCI_DEVICE_ID_INTEL_82801AB_6
- PCI_DEVICE_ID_INTEL_82801AB_8
- PCI_DEVICE_ID_INTEL_82801BA_0
- PCI_DEVICE_ID_INTEL_82801BA_10
- PCI_DEVICE_ID_INTEL_82801BA_11
- PCI_DEVICE_ID_INTEL_82801BA_2
- PCI_DEVICE_ID_INTEL_82801BA_4
- PCI_DEVICE_ID_INTEL_82801BA_6
- PCI_DEVICE_ID_INTEL_82801BA_8
- PCI_DEVICE_ID_INTEL_82801BA_9
- PCI_DEVICE_ID_INTEL_82801CA_0
- PCI_DEVICE_ID_INTEL_82801CA_10
- PCI_DEVICE_ID_INTEL_82801CA_11
- PCI_DEVICE_ID_INTEL_82801CA_12
- PCI_DEVICE_ID_INTEL_82801CA_3
- PCI_DEVICE_ID_INTEL_82801CA_5
- PCI_DEVICE_ID_INTEL_82801CA_6
- PCI_DEVICE_ID_INTEL_82801DB_0
- PCI_DEVICE_ID_INTEL_82801DB_1
- PCI_DEVICE_ID_INTEL_82801DB_10
- PCI_DEVICE_ID_INTEL_82801DB_11
- PCI_DEVICE_ID_INTEL_82801DB_12
- PCI_DEVICE_ID_INTEL_82801DB_2
- PCI_DEVICE_ID_INTEL_82801DB_3
- PCI_DEVICE_ID_INTEL_82801DB_5
- PCI_DEVICE_ID_INTEL_82801DB_6
- PCI_DEVICE_ID_INTEL_82801DB_9
- PCI_DEVICE_ID_INTEL_82801EB_0
- PCI_DEVICE_ID_INTEL_82801EB_1
- PCI_DEVICE_ID_INTEL_82801EB_11
- PCI_DEVICE_ID_INTEL_82801EB_12
- PCI_DEVICE_ID_INTEL_82801EB_13
- PCI_DEVICE_ID_INTEL_82801EB_3
- PCI_DEVICE_ID_INTEL_82801EB_5
- PCI_DEVICE_ID_INTEL_82801EB_6
- PCI_DEVICE_ID_INTEL_82801E_0
- PCI_DEVICE_ID_INTEL_82801E_11
- PCI_DEVICE_ID_INTEL_82810E_IG
- PCI_DEVICE_ID_INTEL_82810E_MC
- PCI_DEVICE_ID_INTEL_82810_IG1
- PCI_DEVICE_ID_INTEL_82810_IG3
- PCI_DEVICE_ID_INTEL_82810_MC1
- PCI_DEVICE_ID_INTEL_82810_MC3
- PCI_DEVICE_ID_INTEL_82815_100
- PCI_DEVICE_ID_INTEL_82815_CGC
- PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
- PCI_DEVICE_ID_INTEL_82815_MC
- PCI_DEVICE_ID_INTEL_82815_NOAGP
- PCI_DEVICE_ID_INTEL_82820_HB
- PCI_DEVICE_ID_INTEL_82820_UP_HB
- PCI_DEVICE_ID_INTEL_82830_CGC
- PCI_DEVICE_ID_INTEL_82830_HB
- PCI_DEVICE_ID_INTEL_82840_HB
- PCI_DEVICE_ID_INTEL_82845G_HB
- PCI_DEVICE_ID_INTEL_82845G_IG
- PCI_DEVICE_ID_INTEL_82845_HB
- PCI_DEVICE_ID_INTEL_82850_HB
- PCI_DEVICE_ID_INTEL_82854_HB
- PCI_DEVICE_ID_INTEL_82854_IG
- PCI_DEVICE_ID_INTEL_82855GM_HB
- PCI_DEVICE_ID_INTEL_82855GM_IG
- PCI_DEVICE_ID_INTEL_82855PM_HB
- PCI_DEVICE_ID_INTEL_82860_0
- PCI_DEVICE_ID_INTEL_82860_HB
- PCI_DEVICE_ID_INTEL_82865_HB
- PCI_DEVICE_ID_INTEL_82865_IG
- PCI_DEVICE_ID_INTEL_82875_0
- PCI_DEVICE_ID_INTEL_82875_6
- PCI_DEVICE_ID_INTEL_82875_HB
- PCI_DEVICE_ID_INTEL_82915GM_HB
- PCI_DEVICE_ID_INTEL_82915GM_IG
- PCI_DEVICE_ID_INTEL_82915G_HB
- PCI_DEVICE_ID_INTEL_82915G_IG
- PCI_DEVICE_ID_INTEL_82945GME_HB
- PCI_DEVICE_ID_INTEL_82945GME_IG
- PCI_DEVICE_ID_INTEL_82945GM_HB
- PCI_DEVICE_ID_INTEL_82945GM_IG
- PCI_DEVICE_ID_INTEL_82945G_HB
- PCI_DEVICE_ID_INTEL_82945G_IG
- PCI_DEVICE_ID_INTEL_82946GZ_HB
- PCI_DEVICE_ID_INTEL_82946GZ_IG
- PCI_DEVICE_ID_INTEL_82965GME_HB
- PCI_DEVICE_ID_INTEL_82965GME_IG
- PCI_DEVICE_ID_INTEL_82965GM_HB
- PCI_DEVICE_ID_INTEL_82965GM_IG
- PCI_DEVICE_ID_INTEL_82965G_HB
- PCI_DEVICE_ID_INTEL_82965G_IG
- PCI_DEVICE_ID_INTEL_82965Q_HB
- PCI_DEVICE_ID_INTEL_82965Q_IG
- PCI_DEVICE_ID_INTEL_82975_0
- PCI_DEVICE_ID_INTEL_82G35_HB
- PCI_DEVICE_ID_INTEL_82G35_IG
- PCI_DEVICE_ID_INTEL_830M
- PCI_DEVICE_ID_INTEL_84460GX
- PCI_DEVICE_ID_INTEL_845G
- PCI_DEVICE_ID_INTEL_854
- PCI_DEVICE_ID_INTEL_85XGM
- PCI_DEVICE_ID_INTEL_865G
- PCI_DEVICE_ID_INTEL_915G
- PCI_DEVICE_ID_INTEL_915GM
- PCI_DEVICE_ID_INTEL_945G
- PCI_DEVICE_ID_INTEL_945GM
- PCI_DEVICE_ID_INTEL_945GME
- PCI_DEVICE_ID_INTEL_965G
- PCI_DEVICE_ID_INTEL_965GM
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI
- PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI
- PCI_DEVICE_ID_INTEL_AML_YD_IMC
- PCI_DEVICE_ID_INTEL_AML_YQ_IMC
- PCI_DEVICE_ID_INTEL_APL
- PCI_DEVICE_ID_INTEL_APL_EMMC
- PCI_DEVICE_ID_INTEL_APL_SD
- PCI_DEVICE_ID_INTEL_APL_SDIO
- PCI_DEVICE_ID_INTEL_APL_XHCI
- PCI_DEVICE_ID_INTEL_AVOTON_SMBUS
- PCI_DEVICE_ID_INTEL_AVOTON_SMT
- PCI_DEVICE_ID_INTEL_B43_1_HB
- PCI_DEVICE_ID_INTEL_B43_1_IG
- PCI_DEVICE_ID_INTEL_B43_HB
- PCI_DEVICE_ID_INTEL_B43_IG
- PCI_DEVICE_ID_INTEL_BAYTRAIL
- PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS
- PCI_DEVICE_ID_INTEL_BDW_IMC
- PCI_DEVICE_ID_INTEL_BDW_UART1
- PCI_DEVICE_ID_INTEL_BDW_UART2
- PCI_DEVICE_ID_INTEL_BRASWELL
- PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TM
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TM
- PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC
- PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI
- PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI
- PCI_DEVICE_ID_INTEL_BROXTON_SMBUS
- PCI_DEVICE_ID_INTEL_BSW
- PCI_DEVICE_ID_INTEL_BSW_EMMC
- PCI_DEVICE_ID_INTEL_BSW_SD
- PCI_DEVICE_ID_INTEL_BSW_SDIO
- PCI_DEVICE_ID_INTEL_BSW_UART1
- PCI_DEVICE_ID_INTEL_BSW_UART2
- PCI_DEVICE_ID_INTEL_BXT
- PCI_DEVICE_ID_INTEL_BXTM_EMMC
- PCI_DEVICE_ID_INTEL_BXTM_SD
- PCI_DEVICE_ID_INTEL_BXTM_SDIO
- PCI_DEVICE_ID_INTEL_BXT_EMMC
- PCI_DEVICE_ID_INTEL_BXT_M
- PCI_DEVICE_ID_INTEL_BXT_SD
- PCI_DEVICE_ID_INTEL_BXT_SDIO
- PCI_DEVICE_ID_INTEL_BYT
- PCI_DEVICE_ID_INTEL_BYT_EMMC
- PCI_DEVICE_ID_INTEL_BYT_EMMC2
- PCI_DEVICE_ID_INTEL_BYT_SD
- PCI_DEVICE_ID_INTEL_BYT_SDIO
- PCI_DEVICE_ID_INTEL_BYT_UART1
- PCI_DEVICE_ID_INTEL_BYT_UART2
- PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C
- PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C
- PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS
- PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS
- PCI_DEVICE_ID_INTEL_CDF_EMMC
- PCI_DEVICE_ID_INTEL_CDF_SMBUS
- PCI_DEVICE_ID_INTEL_CDF_SMT
- PCI_DEVICE_ID_INTEL_CDF_UART
- PCI_DEVICE_ID_INTEL_CE4100
- PCI_DEVICE_ID_INTEL_CE4100_UART
- PCI_DEVICE_ID_INTEL_CE4100_USB
- PCI_DEVICE_ID_INTEL_CENTERTON_ILB
- PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC
- PCI_DEVICE_ID_INTEL_CFL_2U_IMC
- PCI_DEVICE_ID_INTEL_CFL_4H_IMC
- PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC
- PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC
- PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC
- PCI_DEVICE_ID_INTEL_CFL_4U_IMC
- PCI_DEVICE_ID_INTEL_CFL_6H_IMC
- PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC
- PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC
- PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC
- PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC
- PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC
- PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC
- PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI
- PCI_DEVICE_ID_INTEL_CLV_EMMC0
- PCI_DEVICE_ID_INTEL_CLV_EMMC1
- PCI_DEVICE_ID_INTEL_CLV_SDIO0
- PCI_DEVICE_ID_INTEL_CLV_SDIO1
- PCI_DEVICE_ID_INTEL_CLV_SDIO2
- PCI_DEVICE_ID_INTEL_CMLH
- PCI_DEVICE_ID_INTEL_CMLH_SD
- PCI_DEVICE_ID_INTEL_CMLLP
- PCI_DEVICE_ID_INTEL_CML_EMMC
- PCI_DEVICE_ID_INTEL_CML_SD
- PCI_DEVICE_ID_INTEL_CML_XHCI
- PCI_DEVICE_ID_INTEL_CNPH
- PCI_DEVICE_ID_INTEL_CNPH_SD
- PCI_DEVICE_ID_INTEL_CNPLP
- PCI_DEVICE_ID_INTEL_CNPV
- PCI_DEVICE_ID_INTEL_CNP_EMMC
- PCI_DEVICE_ID_INTEL_CNP_SD
- PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS
- PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS
- PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX
- PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN
- PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS
- PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX
- PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN
- PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS
- PCI_DEVICE_ID_INTEL_DNV_EMMC
- PCI_DEVICE_ID_INTEL_DNV_SMBUS
- PCI_DEVICE_ID_INTEL_DNV_SMT
- PCI_DEVICE_ID_INTEL_DNV_UART
- PCI_DEVICE_ID_INTEL_DNV_XHCI
- PCI_DEVICE_ID_INTEL_E6XX_CU
- PCI_DEVICE_ID_INTEL_E7221_HB
- PCI_DEVICE_ID_INTEL_E7221_IG
- PCI_DEVICE_ID_INTEL_E7320_MCH
- PCI_DEVICE_ID_INTEL_E7501_MCH
- PCI_DEVICE_ID_INTEL_E7520_MCH
- PCI_DEVICE_ID_INTEL_E7525_MCH
- PCI_DEVICE_ID_INTEL_EAGLELAKE_HB
- PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
- PCI_DEVICE_ID_INTEL_EAGLE_RIDGE
- PCI_DEVICE_ID_INTEL_EESSC
- PCI_DEVICE_ID_INTEL_EG20T_UDC
- PCI_DEVICE_ID_INTEL_EHLLP
- PCI_DEVICE_ID_INTEL_EHL_EMMC
- PCI_DEVICE_ID_INTEL_EHL_SD
- PCI_DEVICE_ID_INTEL_EHL_UART0
- PCI_DEVICE_ID_INTEL_EHL_UART1
- PCI_DEVICE_ID_INTEL_EHL_UART2
- PCI_DEVICE_ID_INTEL_EHL_UART3
- PCI_DEVICE_ID_INTEL_EHL_UART4
- PCI_DEVICE_ID_INTEL_EHL_UART5
- PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS
- PCI_DEVICE_ID_INTEL_EP80579_0
- PCI_DEVICE_ID_INTEL_EP80579_1
- PCI_DEVICE_ID_INTEL_ESB2_0
- PCI_DEVICE_ID_INTEL_ESB2_14
- PCI_DEVICE_ID_INTEL_ESB2_17
- PCI_DEVICE_ID_INTEL_ESB2_18
- PCI_DEVICE_ID_INTEL_ESB_1
- PCI_DEVICE_ID_INTEL_ESB_10
- PCI_DEVICE_ID_INTEL_ESB_2
- PCI_DEVICE_ID_INTEL_ESB_4
- PCI_DEVICE_ID_INTEL_ESB_5
- PCI_DEVICE_ID_INTEL_ESB_9
- PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI
- PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE
- PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI
- PCI_DEVICE_ID_INTEL_FBD_0
- PCI_DEVICE_ID_INTEL_FBD_1
- PCI_DEVICE_ID_INTEL_FBD_CNB
- PCI_DEVICE_ID_INTEL_G33_HB
- PCI_DEVICE_ID_INTEL_G33_IG
- PCI_DEVICE_ID_INTEL_G41_HB
- PCI_DEVICE_ID_INTEL_G41_IG
- PCI_DEVICE_ID_INTEL_G45_HB
- PCI_DEVICE_ID_INTEL_G45_IG
- PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS
- PCI_DEVICE_ID_INTEL_GLK
- PCI_DEVICE_ID_INTEL_GLK_EMMC
- PCI_DEVICE_ID_INTEL_GLK_SD
- PCI_DEVICE_ID_INTEL_GLK_SDIO
- PCI_DEVICE_ID_INTEL_GM45_HB
- PCI_DEVICE_ID_INTEL_GM45_IG
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TM
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TM
- PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC
- PCI_DEVICE_ID_INTEL_HSW_IMC
- PCI_DEVICE_ID_INTEL_HSW_U_IMC
- PCI_DEVICE_ID_INTEL_I5000_DEV16
- PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
- PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
- PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
- PCI_DEVICE_ID_INTEL_I7_MCR
- PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR
- PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL
- PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK
- PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC
- PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR
- PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL
- PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK
- PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC
- PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR
- PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL
- PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK
- PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC
- PCI_DEVICE_ID_INTEL_I7_MC_RAS
- PCI_DEVICE_ID_INTEL_I7_MC_TAD
- PCI_DEVICE_ID_INTEL_I7_MC_TEST
- PCI_DEVICE_ID_INTEL_I7_NONCORE
- PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT
- PCI_DEVICE_ID_INTEL_I960
- PCI_DEVICE_ID_INTEL_I960RM
- PCI_DEVICE_ID_INTEL_IBRIDGE_BR0
- PCI_DEVICE_ID_INTEL_IBRIDGE_BR1
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2
- PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3
- PCI_DEVICE_ID_INTEL_IBRIDGE_SAD
- PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS
- PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI
- PCI_DEVICE_ID_INTEL_ICH10_0
- PCI_DEVICE_ID_INTEL_ICH10_1
- PCI_DEVICE_ID_INTEL_ICH10_2
- PCI_DEVICE_ID_INTEL_ICH10_3
- PCI_DEVICE_ID_INTEL_ICH10_4
- PCI_DEVICE_ID_INTEL_ICH10_5
- PCI_DEVICE_ID_INTEL_ICH6_0
- PCI_DEVICE_ID_INTEL_ICH6_1
- PCI_DEVICE_ID_INTEL_ICH6_16
- PCI_DEVICE_ID_INTEL_ICH6_17
- PCI_DEVICE_ID_INTEL_ICH6_18
- PCI_DEVICE_ID_INTEL_ICH6_19
- PCI_DEVICE_ID_INTEL_ICH6_2
- PCI_DEVICE_ID_INTEL_ICH7_0
- PCI_DEVICE_ID_INTEL_ICH7_1
- PCI_DEVICE_ID_INTEL_ICH7_17
- PCI_DEVICE_ID_INTEL_ICH7_19
- PCI_DEVICE_ID_INTEL_ICH7_20
- PCI_DEVICE_ID_INTEL_ICH7_21
- PCI_DEVICE_ID_INTEL_ICH7_30
- PCI_DEVICE_ID_INTEL_ICH7_31
- PCI_DEVICE_ID_INTEL_ICH8_0
- PCI_DEVICE_ID_INTEL_ICH8_1
- PCI_DEVICE_ID_INTEL_ICH8_2
- PCI_DEVICE_ID_INTEL_ICH8_3
- PCI_DEVICE_ID_INTEL_ICH8_4
- PCI_DEVICE_ID_INTEL_ICH8_5
- PCI_DEVICE_ID_INTEL_ICH8_6
- PCI_DEVICE_ID_INTEL_ICH9_0
- PCI_DEVICE_ID_INTEL_ICH9_1
- PCI_DEVICE_ID_INTEL_ICH9_2
- PCI_DEVICE_ID_INTEL_ICH9_3
- PCI_DEVICE_ID_INTEL_ICH9_4
- PCI_DEVICE_ID_INTEL_ICH9_5
- PCI_DEVICE_ID_INTEL_ICH9_6
- PCI_DEVICE_ID_INTEL_ICH9_7
- PCI_DEVICE_ID_INTEL_ICH9_8
- PCI_DEVICE_ID_INTEL_ICLLP
- PCI_DEVICE_ID_INTEL_ICL_NHI0
- PCI_DEVICE_ID_INTEL_ICL_NHI1
- PCI_DEVICE_ID_INTEL_ICL_U2_IMC
- PCI_DEVICE_ID_INTEL_ICL_U_IMC
- PCI_DEVICE_ID_INTEL_ICP_EMMC
- PCI_DEVICE_ID_INTEL_ICP_SD
- PCI_DEVICE_ID_INTEL_IE31200_HB_1
- PCI_DEVICE_ID_INTEL_IE31200_HB_2
- PCI_DEVICE_ID_INTEL_IE31200_HB_3
- PCI_DEVICE_ID_INTEL_IE31200_HB_4
- PCI_DEVICE_ID_INTEL_IE31200_HB_5
- PCI_DEVICE_ID_INTEL_IE31200_HB_6
- PCI_DEVICE_ID_INTEL_IE31200_HB_7
- PCI_DEVICE_ID_INTEL_IE31200_HB_8
- PCI_DEVICE_ID_INTEL_IE31200_HB_9
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9
- PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK
- PCI_DEVICE_ID_INTEL_IOAT
- PCI_DEVICE_ID_INTEL_IOAT_BDX0
- PCI_DEVICE_ID_INTEL_IOAT_BDX1
- PCI_DEVICE_ID_INTEL_IOAT_BDX2
- PCI_DEVICE_ID_INTEL_IOAT_BDX3
- PCI_DEVICE_ID_INTEL_IOAT_BDX4
- PCI_DEVICE_ID_INTEL_IOAT_BDX5
- PCI_DEVICE_ID_INTEL_IOAT_BDX6
- PCI_DEVICE_ID_INTEL_IOAT_BDX7
- PCI_DEVICE_ID_INTEL_IOAT_BDX8
- PCI_DEVICE_ID_INTEL_IOAT_BDX9
- PCI_DEVICE_ID_INTEL_IOAT_BDXDE0
- PCI_DEVICE_ID_INTEL_IOAT_BDXDE1
- PCI_DEVICE_ID_INTEL_IOAT_BDXDE2
- PCI_DEVICE_ID_INTEL_IOAT_BDXDE3
- PCI_DEVICE_ID_INTEL_IOAT_BWD0
- PCI_DEVICE_ID_INTEL_IOAT_BWD1
- PCI_DEVICE_ID_INTEL_IOAT_BWD2
- PCI_DEVICE_ID_INTEL_IOAT_BWD3
- PCI_DEVICE_ID_INTEL_IOAT_CNB
- PCI_DEVICE_ID_INTEL_IOAT_HSW0
- PCI_DEVICE_ID_INTEL_IOAT_HSW1
- PCI_DEVICE_ID_INTEL_IOAT_HSW2
- PCI_DEVICE_ID_INTEL_IOAT_HSW3
- PCI_DEVICE_ID_INTEL_IOAT_HSW4
- PCI_DEVICE_ID_INTEL_IOAT_HSW5
- PCI_DEVICE_ID_INTEL_IOAT_HSW6
- PCI_DEVICE_ID_INTEL_IOAT_HSW7
- PCI_DEVICE_ID_INTEL_IOAT_HSW8
- PCI_DEVICE_ID_INTEL_IOAT_HSW9
- PCI_DEVICE_ID_INTEL_IOAT_ICX
- PCI_DEVICE_ID_INTEL_IOAT_IVB0
- PCI_DEVICE_ID_INTEL_IOAT_IVB1
- PCI_DEVICE_ID_INTEL_IOAT_IVB2
- PCI_DEVICE_ID_INTEL_IOAT_IVB3
- PCI_DEVICE_ID_INTEL_IOAT_IVB4
- PCI_DEVICE_ID_INTEL_IOAT_IVB5
- PCI_DEVICE_ID_INTEL_IOAT_IVB6
- PCI_DEVICE_ID_INTEL_IOAT_IVB7
- PCI_DEVICE_ID_INTEL_IOAT_IVB8
- PCI_DEVICE_ID_INTEL_IOAT_IVB9
- PCI_DEVICE_ID_INTEL_IOAT_JSF0
- PCI_DEVICE_ID_INTEL_IOAT_JSF1
- PCI_DEVICE_ID_INTEL_IOAT_JSF2
- PCI_DEVICE_ID_INTEL_IOAT_JSF3
- PCI_DEVICE_ID_INTEL_IOAT_JSF4
- PCI_DEVICE_ID_INTEL_IOAT_JSF5
- PCI_DEVICE_ID_INTEL_IOAT_JSF6
- PCI_DEVICE_ID_INTEL_IOAT_JSF7
- PCI_DEVICE_ID_INTEL_IOAT_JSF8
- PCI_DEVICE_ID_INTEL_IOAT_JSF9
- PCI_DEVICE_ID_INTEL_IOAT_SCNB
- PCI_DEVICE_ID_INTEL_IOAT_SKX
- PCI_DEVICE_ID_INTEL_IOAT_SNB
- PCI_DEVICE_ID_INTEL_IOAT_SNB0
- PCI_DEVICE_ID_INTEL_IOAT_SNB1
- PCI_DEVICE_ID_INTEL_IOAT_SNB2
- PCI_DEVICE_ID_INTEL_IOAT_SNB3
- PCI_DEVICE_ID_INTEL_IOAT_SNB4
- PCI_DEVICE_ID_INTEL_IOAT_SNB5
- PCI_DEVICE_ID_INTEL_IOAT_SNB6
- PCI_DEVICE_ID_INTEL_IOAT_SNB7
- PCI_DEVICE_ID_INTEL_IOAT_SNB8
- PCI_DEVICE_ID_INTEL_IOAT_SNB9
- PCI_DEVICE_ID_INTEL_IOAT_TBG0
- PCI_DEVICE_ID_INTEL_IOAT_TBG1
- PCI_DEVICE_ID_INTEL_IOAT_TBG2
- PCI_DEVICE_ID_INTEL_IOAT_TBG3
- PCI_DEVICE_ID_INTEL_IOAT_TBG4
- PCI_DEVICE_ID_INTEL_IOAT_TBG5
- PCI_DEVICE_ID_INTEL_IOAT_TBG6
- PCI_DEVICE_ID_INTEL_IOAT_TBG7
- PCI_DEVICE_ID_INTEL_IOH1_GBE
- PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB
- PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB
- PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
- PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB
- PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB
- PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
- PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
- PCI_DEVICE_ID_INTEL_ITC_LPC
- PCI_DEVICE_ID_INTEL_IVB_E3_IMC
- PCI_DEVICE_ID_INTEL_IVB_IMC
- PCI_DEVICE_ID_INTEL_IVB_M2_VGA
- PCI_DEVICE_ID_INTEL_IVB_M_VGA
- PCI_DEVICE_ID_INTEL_IXP2800
- PCI_DEVICE_ID_INTEL_IXP4XX
- PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX
- PCI_DEVICE_ID_INTEL_JSL_EMMC
- PCI_DEVICE_ID_INTEL_JSL_SD
- PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS
- PCI_DEVICE_ID_INTEL_KBL_HQ_IMC
- PCI_DEVICE_ID_INTEL_KBL_SD_IMC
- PCI_DEVICE_ID_INTEL_KBL_SQ_IMC
- PCI_DEVICE_ID_INTEL_KBL_UQ_IMC
- PCI_DEVICE_ID_INTEL_KBL_U_IMC
- PCI_DEVICE_ID_INTEL_KBL_WQ_IMC
- PCI_DEVICE_ID_INTEL_KBL_Y_IMC
- PCI_DEVICE_ID_INTEL_KBP
- PCI_DEVICE_ID_INTEL_KNL_IMC_CHA
- PCI_DEVICE_ID_INTEL_KNL_IMC_CHAN
- PCI_DEVICE_ID_INTEL_KNL_IMC_MC
- PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0
- PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1
- PCI_DEVICE_ID_INTEL_KNL_IMC_TA
- PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM
- PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS
- PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS
- PCI_DEVICE_ID_INTEL_LIGHT_PEAK
- PCI_DEVICE_ID_INTEL_LIGHT_RIDGE
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST
- PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE
- PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT
- PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2
- PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0
- PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0
- PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD
- PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS
- PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI
- PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS
- PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI
- PCI_DEVICE_ID_INTEL_MCH_PA
- PCI_DEVICE_ID_INTEL_MCH_PA1
- PCI_DEVICE_ID_INTEL_MCH_PB
- PCI_DEVICE_ID_INTEL_MCH_PB1
- PCI_DEVICE_ID_INTEL_MCH_PC
- PCI_DEVICE_ID_INTEL_MCH_PC1
- PCI_DEVICE_ID_INTEL_MFD_EMMC0
- PCI_DEVICE_ID_INTEL_MFD_EMMC1
- PCI_DEVICE_ID_INTEL_MFD_SD
- PCI_DEVICE_ID_INTEL_MFD_SDIO1
- PCI_DEVICE_ID_INTEL_MFD_SDIO2
- PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA
- PCI_DEVICE_ID_INTEL_MRFLD
- PCI_DEVICE_ID_INTEL_MRFLD_HSU
- PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA
- PCI_DEVICE_ID_INTEL_MRFLD_MMC
- PCI_DEVICE_ID_INTEL_MRST_SD0
- PCI_DEVICE_ID_INTEL_MRST_SD1
- PCI_DEVICE_ID_INTEL_MRST_SD2
- PCI_DEVICE_ID_INTEL_NTB_B2B_BDX
- PCI_DEVICE_ID_INTEL_NTB_B2B_HSX
- PCI_DEVICE_ID_INTEL_NTB_B2B_IVT
- PCI_DEVICE_ID_INTEL_NTB_B2B_JSF
- PCI_DEVICE_ID_INTEL_NTB_B2B_SKX
- PCI_DEVICE_ID_INTEL_NTB_B2B_SNB
- PCI_DEVICE_ID_INTEL_NTB_PS_BDX
- PCI_DEVICE_ID_INTEL_NTB_PS_HSX
- PCI_DEVICE_ID_INTEL_NTB_PS_IVT
- PCI_DEVICE_ID_INTEL_NTB_PS_JSF
- PCI_DEVICE_ID_INTEL_NTB_PS_SNB
- PCI_DEVICE_ID_INTEL_NTB_SS_BDX
- PCI_DEVICE_ID_INTEL_NTB_SS_HSX
- PCI_DEVICE_ID_INTEL_NTB_SS_IVT
- PCI_DEVICE_ID_INTEL_NTB_SS_JSF
- PCI_DEVICE_ID_INTEL_NTB_SS_SNB
- PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX
- PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN
- PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS
- PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI
- PCI_DEVICE_ID_INTEL_PATSBURG_KT
- PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0
- PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1
- PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS
- PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0
- PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1
- PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2
- PCI_DEVICE_ID_INTEL_PCH_SDIO0
- PCI_DEVICE_ID_INTEL_PCH_SDIO1
- PCI_DEVICE_ID_INTEL_PINEVIEW_HB
- PCI_DEVICE_ID_INTEL_PINEVIEW_IG
- PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB
- PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
- PCI_DEVICE_ID_INTEL_PNW_UART1
- PCI_DEVICE_ID_INTEL_PNW_UART2
- PCI_DEVICE_ID_INTEL_PNW_UART3
- PCI_DEVICE_ID_INTEL_PORT_RIDGE
- PCI_DEVICE_ID_INTEL_PXHD_0
- PCI_DEVICE_ID_INTEL_PXHD_1
- PCI_DEVICE_ID_INTEL_PXHV
- PCI_DEVICE_ID_INTEL_PXH_0
- PCI_DEVICE_ID_INTEL_PXH_1
- PCI_DEVICE_ID_INTEL_Q33_HB
- PCI_DEVICE_ID_INTEL_Q33_IG
- PCI_DEVICE_ID_INTEL_Q35_HB
- PCI_DEVICE_ID_INTEL_Q35_IG
- PCI_DEVICE_ID_INTEL_Q45_HB
- PCI_DEVICE_ID_INTEL_Q45_IG
- PCI_DEVICE_ID_INTEL_QRK_SD
- PCI_DEVICE_ID_INTEL_QRK_UARTx
- PCI_DEVICE_ID_INTEL_QUARK_X1000
- PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB
- PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC
- PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC
- PCI_DEVICE_ID_INTEL_RAID_SRCS16
- PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK
- PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_NHI
- PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE
- PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_NHI
- PCI_DEVICE_ID_INTEL_S1200_SMT0
- PCI_DEVICE_ID_INTEL_S1200_SMT1
- PCI_DEVICE_ID_INTEL_S21152BB
- PCI_DEVICE_ID_INTEL_SBRIDGE_BR
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2
- PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3
- PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0
- PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1
- PCI_DEVICE_ID_INTEL_SCH_IDE
- PCI_DEVICE_ID_INTEL_SCH_LPC
- PCI_DEVICE_ID_INTEL_SKL_E3_IMC
- PCI_DEVICE_ID_INTEL_SKL_HD_IMC
- PCI_DEVICE_ID_INTEL_SKL_HQ_IMC
- PCI_DEVICE_ID_INTEL_SKL_SD_IMC
- PCI_DEVICE_ID_INTEL_SKL_SQ_IMC
- PCI_DEVICE_ID_INTEL_SKL_U_IMC
- PCI_DEVICE_ID_INTEL_SKL_Y_IMC
- PCI_DEVICE_ID_INTEL_SNB_IMC
- PCI_DEVICE_ID_INTEL_SPTH
- PCI_DEVICE_ID_INTEL_SPTLP
- PCI_DEVICE_ID_INTEL_SPT_EMMC
- PCI_DEVICE_ID_INTEL_SPT_SD
- PCI_DEVICE_ID_INTEL_SPT_SDIO
- PCI_DEVICE_ID_INTEL_SRC
- PCI_DEVICE_ID_INTEL_SRC_XSCALE
- PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS
- PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI
- PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS
- PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI
- PCI_DEVICE_ID_INTEL_TANGIER
- PCI_DEVICE_ID_INTEL_TGPLP
- PCI_DEVICE_ID_INTEL_TGP_LPC
- PCI_DEVICE_ID_INTEL_THERMAL_SENSOR
- PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE
- PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI
- PCI_DEVICE_ID_INTEL_TNG_UART
- PCI_DEVICE_ID_INTEL_UNC_HA
- PCI_DEVICE_ID_INTEL_UNC_IMC0
- PCI_DEVICE_ID_INTEL_UNC_IMC1
- PCI_DEVICE_ID_INTEL_UNC_IMC2
- PCI_DEVICE_ID_INTEL_UNC_IMC3
- PCI_DEVICE_ID_INTEL_UNC_QPI0
- PCI_DEVICE_ID_INTEL_UNC_QPI1
- PCI_DEVICE_ID_INTEL_UNC_R2PCIE
- PCI_DEVICE_ID_INTEL_UNC_R3QPI0
- PCI_DEVICE_ID_INTEL_UNC_R3QPI1
- PCI_DEVICE_ID_INTEL_VMD_201D
- PCI_DEVICE_ID_INTEL_VMD_28C0
- PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS
- PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0
- PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1
- PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2
- PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC
- PCI_DEVICE_ID_INTEL_WHL_UD_IMC
- PCI_DEVICE_ID_INTEL_WHL_UQ_IMC
- PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS
- PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI
- PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS
- PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE
- PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI
- PCI_DEVICE_ID_INTEL_X38_HB
- PCI_DEVICE_ID_INTEL_X58_HUB_MGMT
- PCI_DEVICE_ID_INTERG_1682
- PCI_DEVICE_ID_INTERG_2000
- PCI_DEVICE_ID_INTERG_2010
- PCI_DEVICE_ID_INTERG_5000
- PCI_DEVICE_ID_INTERG_5050
- PCI_DEVICE_ID_IOMEGA_BUZ
- PCI_DEVICE_ID_IPHASE_5575
- PCI_DEVICE_ID_ITE_8152
- PCI_DEVICE_ID_ITE_8172
- PCI_DEVICE_ID_ITE_8211
- PCI_DEVICE_ID_ITE_8212
- PCI_DEVICE_ID_ITE_8213
- PCI_DEVICE_ID_ITE_8872
- PCI_DEVICE_ID_ITE_IT8330G_0
- PCI_DEVICE_ID_IVTV15
- PCI_DEVICE_ID_IVTV16
- PCI_DEVICE_ID_JMICRON_JMB360
- PCI_DEVICE_ID_JMICRON_JMB361
- PCI_DEVICE_ID_JMICRON_JMB362
- PCI_DEVICE_ID_JMICRON_JMB363
- PCI_DEVICE_ID_JMICRON_JMB364
- PCI_DEVICE_ID_JMICRON_JMB365
- PCI_DEVICE_ID_JMICRON_JMB366
- PCI_DEVICE_ID_JMICRON_JMB368
- PCI_DEVICE_ID_JMICRON_JMB369
- PCI_DEVICE_ID_JMICRON_JMB385_MS
- PCI_DEVICE_ID_JMICRON_JMB388_ESD
- PCI_DEVICE_ID_JMICRON_JMB388_SD
- PCI_DEVICE_ID_JMICRON_JMB38X_FW
- PCI_DEVICE_ID_JMICRON_JMB38X_MMC
- PCI_DEVICE_ID_JMICRON_JMB38X_MS
- PCI_DEVICE_ID_JMICRON_JMB38X_SD
- PCI_DEVICE_ID_JMICRON_JMB390_MS
- PCI_DEVICE_ID_JMICRON_JMC250
- PCI_DEVICE_ID_JMICRON_JMC260
- PCI_DEVICE_ID_KORENIX_JETCARDF0
- PCI_DEVICE_ID_KORENIX_JETCARDF1
- PCI_DEVICE_ID_KORENIX_JETCARDF2
- PCI_DEVICE_ID_KORENIX_JETCARDF3
- PCI_DEVICE_ID_LANCER_FC
- PCI_DEVICE_ID_LANCER_FCOE
- PCI_DEVICE_ID_LANCER_FCOE_VF
- PCI_DEVICE_ID_LANCER_FC_VF
- PCI_DEVICE_ID_LANCER_G6_FC
- PCI_DEVICE_ID_LANCER_G7_FC
- PCI_DEVICE_ID_LAVA_BOCA_IOPPAR
- PCI_DEVICE_ID_LAVA_DSERIAL
- PCI_DEVICE_ID_LAVA_DUAL_PAR_A
- PCI_DEVICE_ID_LAVA_DUAL_PAR_B
- PCI_DEVICE_ID_LAVA_OCTO_A
- PCI_DEVICE_ID_LAVA_OCTO_B
- PCI_DEVICE_ID_LAVA_PARALLEL
- PCI_DEVICE_ID_LAVA_PORT_650
- PCI_DEVICE_ID_LAVA_PORT_PLUS
- PCI_DEVICE_ID_LAVA_QUAD_A
- PCI_DEVICE_ID_LAVA_QUAD_B
- PCI_DEVICE_ID_LAVA_QUATRO_A
- PCI_DEVICE_ID_LAVA_QUATRO_B
- PCI_DEVICE_ID_LAVA_QUATTRO_A
- PCI_DEVICE_ID_LAVA_QUATTRO_B
- PCI_DEVICE_ID_LAVA_SSERIAL
- PCI_DEVICE_ID_LINCROFT
- PCI_DEVICE_ID_LINDSAY
- PCI_DEVICE_ID_LINKSYS_EG1064
- PCI_DEVICE_ID_LMC_DS3
- PCI_DEVICE_ID_LMC_HSSI
- PCI_DEVICE_ID_LMC_SSI
- PCI_DEVICE_ID_LMC_T1
- PCI_DEVICE_ID_LML_33R10
- PCI_DEVICE_ID_LP10000S
- PCI_DEVICE_ID_LP101
- PCI_DEVICE_ID_LP11000S
- PCI_DEVICE_ID_LPE11000S
- PCI_DEVICE_ID_LSI_1030_53C1035
- PCI_DEVICE_ID_LSI_53C1010_33
- PCI_DEVICE_ID_LSI_53C1010_66
- PCI_DEVICE_ID_LSI_53C1030
- PCI_DEVICE_ID_LSI_53C1035
- PCI_DEVICE_ID_LSI_53C1510
- PCI_DEVICE_ID_LSI_53C810AP
- PCI_DEVICE_ID_LSI_53C875A
- PCI_DEVICE_ID_LSI_53C895A
- PCI_DEVICE_ID_LSI_61C102
- PCI_DEVICE_ID_LSI_63C815
- PCI_DEVICE_ID_LSI_AERO_10E0
- PCI_DEVICE_ID_LSI_AERO_10E1
- PCI_DEVICE_ID_LSI_AERO_10E2
- PCI_DEVICE_ID_LSI_AERO_10E3
- PCI_DEVICE_ID_LSI_AERO_10E4
- PCI_DEVICE_ID_LSI_AERO_10E5
- PCI_DEVICE_ID_LSI_AERO_10E6
- PCI_DEVICE_ID_LSI_AERO_10E7
- PCI_DEVICE_ID_LSI_CRUSADER
- PCI_DEVICE_ID_LSI_CRUSADER_4PORT
- PCI_DEVICE_ID_LSI_CUTLASS_52
- PCI_DEVICE_ID_LSI_CUTLASS_53
- PCI_DEVICE_ID_LSI_FC909
- PCI_DEVICE_ID_LSI_FC919
- PCI_DEVICE_ID_LSI_FC919X
- PCI_DEVICE_ID_LSI_FC919_LAN
- PCI_DEVICE_ID_LSI_FC929
- PCI_DEVICE_ID_LSI_FC929X
- PCI_DEVICE_ID_LSI_FC929_LAN
- PCI_DEVICE_ID_LSI_FC939X
- PCI_DEVICE_ID_LSI_FC949ES
- PCI_DEVICE_ID_LSI_FC949X
- PCI_DEVICE_ID_LSI_FURY
- PCI_DEVICE_ID_LSI_FUSION
- PCI_DEVICE_ID_LSI_HARPOON
- PCI_DEVICE_ID_LSI_INTRUDER
- PCI_DEVICE_ID_LSI_INTRUDER_24
- PCI_DEVICE_ID_LSI_INVADER
- PCI_DEVICE_ID_LSI_PLASMA
- PCI_DEVICE_ID_LSI_SAS0071SKINNY
- PCI_DEVICE_ID_LSI_SAS0073SKINNY
- PCI_DEVICE_ID_LSI_SAS0079GEN2
- PCI_DEVICE_ID_LSI_SAS1064
- PCI_DEVICE_ID_LSI_SAS1064A
- PCI_DEVICE_ID_LSI_SAS1064E
- PCI_DEVICE_ID_LSI_SAS1064R
- PCI_DEVICE_ID_LSI_SAS1066
- PCI_DEVICE_ID_LSI_SAS1066E
- PCI_DEVICE_ID_LSI_SAS1068
- PCI_DEVICE_ID_LSI_SAS1068E
- PCI_DEVICE_ID_LSI_SAS1078
- PCI_DEVICE_ID_LSI_SAS1078DE
- PCI_DEVICE_ID_LSI_SAS1078GEN2
- PCI_DEVICE_ID_LSI_SAS1078R
- PCI_DEVICE_ID_LSI_TOMCAT
- PCI_DEVICE_ID_LSI_VENTURA
- PCI_DEVICE_ID_LSI_VENTURA_4PORT
- PCI_DEVICE_ID_LSI_VERDE_ZCR
- PCI_DEVICE_ID_MADGE_AMBASSADOR
- PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD
- PCI_DEVICE_ID_MADGE_HORIZON
- PCI_DEVICE_ID_MADGE_MK2
- PCI_DEVICE_ID_MAINPINE_PBRIDGE
- PCI_DEVICE_ID_MARVELL_88ALP01_CCIC
- PCI_DEVICE_ID_MARVELL_88ALP01_NAND
- PCI_DEVICE_ID_MARVELL_88ALP01_SD
- PCI_DEVICE_ID_MARVELL_GT64111
- PCI_DEVICE_ID_MARVELL_GT64260
- PCI_DEVICE_ID_MARVELL_MV64360
- PCI_DEVICE_ID_MARVELL_MV64460
- PCI_DEVICE_ID_MARVELL_MV9143
- PCI_DEVICE_ID_MARVELL_MV9580
- PCI_DEVICE_ID_MASK
- PCI_DEVICE_ID_MATROX_G100_AGP
- PCI_DEVICE_ID_MATROX_G100_MM
- PCI_DEVICE_ID_MATROX_G200EV_PCI
- PCI_DEVICE_ID_MATROX_G200_AGP
- PCI_DEVICE_ID_MATROX_G200_PCI
- PCI_DEVICE_ID_MATROX_G400
- PCI_DEVICE_ID_MATROX_G550
- PCI_DEVICE_ID_MATROX_MGA_2
- PCI_DEVICE_ID_MATROX_MGA_IMP
- PCI_DEVICE_ID_MATROX_MIL
- PCI_DEVICE_ID_MATROX_MIL_2
- PCI_DEVICE_ID_MATROX_MIL_2_AGP
- PCI_DEVICE_ID_MATROX_MYS
- PCI_DEVICE_ID_MATROX_MYS_AGP
- PCI_DEVICE_ID_MATROX_VIA
- PCI_DEVICE_ID_MCHIP_KL5A72002
- PCI_DEVICE_ID_MEDIATEK_7629
- PCI_DEVICE_ID_MEGARAID_I4_133_RAID
- PCI_DEVICE_ID_MEGARAID_SATA_150_4
- PCI_DEVICE_ID_MEGARAID_SATA_150_6
- PCI_DEVICE_ID_MEGARAID_SCSI_320_0
- PCI_DEVICE_ID_MEGARAID_SCSI_320_1
- PCI_DEVICE_ID_MEGARAID_SCSI_320_2
- PCI_DEVICE_ID_MELLANOX_ARBEL
- PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT
- PCI_DEVICE_ID_MELLANOX_CONNECTIB
- PCI_DEVICE_ID_MELLANOX_CONNECTX2
- PCI_DEVICE_ID_MELLANOX_CONNECTX3
- PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO
- PCI_DEVICE_ID_MELLANOX_CONNECTX4
- PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX
- PCI_DEVICE_ID_MELLANOX_CONNECTX_EN
- PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2
- PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2
- PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2
- PCI_DEVICE_ID_MELLANOX_HERMON_DDR
- PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2
- PCI_DEVICE_ID_MELLANOX_HERMON_EN
- PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2
- PCI_DEVICE_ID_MELLANOX_HERMON_QDR
- PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2
- PCI_DEVICE_ID_MELLANOX_HERMON_SDR
- PCI_DEVICE_ID_MELLANOX_SINAI
- PCI_DEVICE_ID_MELLANOX_SINAI_OLD
- PCI_DEVICE_ID_MELLANOX_SPECTRUM
- PCI_DEVICE_ID_MELLANOX_SPECTRUM2
- PCI_DEVICE_ID_MELLANOX_SPECTRUM3
- PCI_DEVICE_ID_MELLANOX_SWITCHIB
- PCI_DEVICE_ID_MELLANOX_SWITCHIB2
- PCI_DEVICE_ID_MELLANOX_SWITCHX2
- PCI_DEVICE_ID_MELLANOX_TAVOR
- PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
- PCI_DEVICE_ID_MEN_CHAMELEON
- PCI_DEVICE_ID_MF624
- PCI_DEVICE_ID_MICROGATE_SCA
- PCI_DEVICE_ID_MICROGATE_USC
- PCI_DEVICE_ID_MICRO_MEMORY_5415CN
- PCI_DEVICE_ID_MICRO_MEMORY_5425CN
- PCI_DEVICE_ID_MICRO_MEMORY_6155
- PCI_DEVICE_ID_MIRO_36050
- PCI_DEVICE_ID_MIRO_DC10PLUS
- PCI_DEVICE_ID_MIRO_DC30PLUS
- PCI_DEVICE_ID_ML7213_DMA1_8CH
- PCI_DEVICE_ID_ML7213_DMA2_8CH
- PCI_DEVICE_ID_ML7213_DMA3_4CH
- PCI_DEVICE_ID_ML7213_DMA4_12CH
- PCI_DEVICE_ID_ML7213_I2C
- PCI_DEVICE_ID_ML7213_IOH_UDC
- PCI_DEVICE_ID_ML7213_SPI
- PCI_DEVICE_ID_ML7223_DMA1_4CH
- PCI_DEVICE_ID_ML7223_DMA2_4CH
- PCI_DEVICE_ID_ML7223_DMA3_4CH
- PCI_DEVICE_ID_ML7223_DMA4_4CH
- PCI_DEVICE_ID_ML7223_I2C
- PCI_DEVICE_ID_ML7223_SPI
- PCI_DEVICE_ID_ML7831_DMA1_8CH
- PCI_DEVICE_ID_ML7831_DMA2_4CH
- PCI_DEVICE_ID_ML7831_I2C
- PCI_DEVICE_ID_ML7831_IOH_UDC
- PCI_DEVICE_ID_ML7831_SPI
- PCI_DEVICE_ID_MOTOROLA_FALCON
- PCI_DEVICE_ID_MOTOROLA_HARRIER
- PCI_DEVICE_ID_MOTOROLA_HAWK
- PCI_DEVICE_ID_MOTOROLA_MPC105
- PCI_DEVICE_ID_MOTOROLA_MPC106
- PCI_DEVICE_ID_MOTOROLA_MPC107
- PCI_DEVICE_ID_MOTOROLA_MPC5200
- PCI_DEVICE_ID_MOTOROLA_MPC5200B
- PCI_DEVICE_ID_MOTOROLA_RAVEN
- PCI_DEVICE_ID_MOXA_C104
- PCI_DEVICE_ID_MOXA_C168
- PCI_DEVICE_ID_MOXA_C218
- PCI_DEVICE_ID_MOXA_C320
- PCI_DEVICE_ID_MOXA_CP102
- PCI_DEVICE_ID_MOXA_CP102E
- PCI_DEVICE_ID_MOXA_CP102EL
- PCI_DEVICE_ID_MOXA_CP102U
- PCI_DEVICE_ID_MOXA_CP102UL
- PCI_DEVICE_ID_MOXA_CP104EL
- PCI_DEVICE_ID_MOXA_CP104EL_A
- PCI_DEVICE_ID_MOXA_CP104JU
- PCI_DEVICE_ID_MOXA_CP104U
- PCI_DEVICE_ID_MOXA_CP114
- PCI_DEVICE_ID_MOXA_CP114EL
- PCI_DEVICE_ID_MOXA_CP116E_A_A
- PCI_DEVICE_ID_MOXA_CP116E_A_B
- PCI_DEVICE_ID_MOXA_CP118EL
- PCI_DEVICE_ID_MOXA_CP118EL_A
- PCI_DEVICE_ID_MOXA_CP118E_A_I
- PCI_DEVICE_ID_MOXA_CP118U
- PCI_DEVICE_ID_MOXA_CP132
- PCI_DEVICE_ID_MOXA_CP132EL
- PCI_DEVICE_ID_MOXA_CP132U
- PCI_DEVICE_ID_MOXA_CP134EL_A
- PCI_DEVICE_ID_MOXA_CP134U
- PCI_DEVICE_ID_MOXA_CP138E_A
- PCI_DEVICE_ID_MOXA_CP168EL
- PCI_DEVICE_ID_MOXA_CP168EL_A
- PCI_DEVICE_ID_MOXA_CP168U
- PCI_DEVICE_ID_MOXA_CP204J
- PCI_DEVICE_ID_MOXA_CT114
- PCI_DEVICE_ID_MOXA_RC7000
- PCI_DEVICE_ID_MPC8308
- PCI_DEVICE_ID_MPC8314
- PCI_DEVICE_ID_MPC8314E
- PCI_DEVICE_ID_MPC8315
- PCI_DEVICE_ID_MPC8315E
- PCI_DEVICE_ID_MPC8377
- PCI_DEVICE_ID_MPC8377E
- PCI_DEVICE_ID_MPC8378
- PCI_DEVICE_ID_MPC8378E
- PCI_DEVICE_ID_MPC8533
- PCI_DEVICE_ID_MPC8533E
- PCI_DEVICE_ID_MPC8536
- PCI_DEVICE_ID_MPC8536E
- PCI_DEVICE_ID_MPC8543
- PCI_DEVICE_ID_MPC8543E
- PCI_DEVICE_ID_MPC8544
- PCI_DEVICE_ID_MPC8544E
- PCI_DEVICE_ID_MPC8545
- PCI_DEVICE_ID_MPC8545E
- PCI_DEVICE_ID_MPC8547E
- PCI_DEVICE_ID_MPC8548
- PCI_DEVICE_ID_MPC8548E
- PCI_DEVICE_ID_MPC8567
- PCI_DEVICE_ID_MPC8567E
- PCI_DEVICE_ID_MPC8568
- PCI_DEVICE_ID_MPC8568E
- PCI_DEVICE_ID_MPC8569
- PCI_DEVICE_ID_MPC8569E
- PCI_DEVICE_ID_MPC8572
- PCI_DEVICE_ID_MPC8572E
- PCI_DEVICE_ID_MPC8610
- PCI_DEVICE_ID_MPC8641
- PCI_DEVICE_ID_MPC8641D
- PCI_DEVICE_ID_MYLEX_DAC960_BA
- PCI_DEVICE_ID_MYLEX_DAC960_GEM
- PCI_DEVICE_ID_MYLEX_DAC960_LA
- PCI_DEVICE_ID_MYLEX_DAC960_LP
- PCI_DEVICE_ID_MYLEX_DAC960_P
- PCI_DEVICE_ID_MYLEX_DAC960_PD
- PCI_DEVICE_ID_MYLEX_DAC960_PG
- PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E
- PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9
- PCI_DEVICE_ID_NCR_53C1510
- PCI_DEVICE_ID_NCR_53C810
- PCI_DEVICE_ID_NCR_53C815
- PCI_DEVICE_ID_NCR_53C820
- PCI_DEVICE_ID_NCR_53C825
- PCI_DEVICE_ID_NCR_53C860
- PCI_DEVICE_ID_NCR_53C875
- PCI_DEVICE_ID_NCR_53C875J
- PCI_DEVICE_ID_NCR_53C885
- PCI_DEVICE_ID_NCR_53C895
- PCI_DEVICE_ID_NCR_53C896
- PCI_DEVICE_ID_NCR_YELLOWFIN
- PCI_DEVICE_ID_NEC_486
- PCI_DEVICE_ID_NEC_ACCEL_1
- PCI_DEVICE_ID_NEC_ACCEL_2
- PCI_DEVICE_ID_NEC_ATM
- PCI_DEVICE_ID_NEC_CBUS_1
- PCI_DEVICE_ID_NEC_CBUS_2
- PCI_DEVICE_ID_NEC_CBUS_3
- PCI_DEVICE_ID_NEC_EMMA2RH
- PCI_DEVICE_ID_NEC_GRAPH
- PCI_DEVICE_ID_NEC_LOCAL
- PCI_DEVICE_ID_NEC_NAPCCARD
- PCI_DEVICE_ID_NEC_NEON250
- PCI_DEVICE_ID_NEC_PC9821CS01
- PCI_DEVICE_ID_NEC_PC9821NRB06
- PCI_DEVICE_ID_NEC_PCX2
- PCI_DEVICE_ID_NEC_R4000
- PCI_DEVICE_ID_NEC_STARALPHA2
- PCI_DEVICE_ID_NEC_USB
- PCI_DEVICE_ID_NEC_UXBUS
- PCI_DEVICE_ID_NEC_VL
- PCI_DEVICE_ID_NEC_VRC4173
- PCI_DEVICE_ID_NEC_VRC5476
- PCI_DEVICE_ID_NEC_VRC5477_AC97
- PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO
- PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO
- PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO
- PCI_DEVICE_ID_NEO_1_422
- PCI_DEVICE_ID_NEO_1_422_485
- PCI_DEVICE_ID_NEO_2DB9
- PCI_DEVICE_ID_NEO_2DB9PRI
- PCI_DEVICE_ID_NEO_2RJ45
- PCI_DEVICE_ID_NEO_2RJ45PRI
- PCI_DEVICE_ID_NEO_2_422_485
- PCI_DEVICE_ID_NEO_4
- PCI_DEVICE_ID_NEPTUNE
- PCI_DEVICE_ID_NEPTUNE_DCSP
- PCI_DEVICE_ID_NEPTUNE_SCSP
- PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100
- PCI_DEVICE_ID_NETELLIGENT_10_T2
- PCI_DEVICE_ID_NETGEAR_GA620
- PCI_DEVICE_ID_NETGEAR_GA620T
- PCI_DEVICE_ID_NETMOS_9705
- PCI_DEVICE_ID_NETMOS_9715
- PCI_DEVICE_ID_NETMOS_9735
- PCI_DEVICE_ID_NETMOS_9745
- PCI_DEVICE_ID_NETMOS_9755
- PCI_DEVICE_ID_NETMOS_9805
- PCI_DEVICE_ID_NETMOS_9815
- PCI_DEVICE_ID_NETMOS_9835
- PCI_DEVICE_ID_NETMOS_9845
- PCI_DEVICE_ID_NETMOS_9855
- PCI_DEVICE_ID_NETMOS_9865
- PCI_DEVICE_ID_NETMOS_9900
- PCI_DEVICE_ID_NETMOS_9901
- PCI_DEVICE_ID_NETMOS_9904
- PCI_DEVICE_ID_NETMOS_9912
- PCI_DEVICE_ID_NETMOS_9922
- PCI_DEVICE_ID_NETRONOME_NFP3800
- PCI_DEVICE_ID_NETRONOME_NFP4000
- PCI_DEVICE_ID_NETRONOME_NFP5000
- PCI_DEVICE_ID_NETRONOME_NFP6000
- PCI_DEVICE_ID_NETRONOME_NFP6000_VF
- PCI_DEVICE_ID_NEUSOLO_16
- PCI_DEVICE_ID_NEUSOLO_4
- PCI_DEVICE_ID_NEUSOLO_9
- PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC
- PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II
- PCI_DEVICE_ID_NINJASCSI_32BI_KME
- PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC
- PCI_DEVICE_ID_NINJASCSI_32BI_WBT
- PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO
- PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II
- PCI_DEVICE_ID_NI_PCI23216
- PCI_DEVICE_ID_NI_PCI2322
- PCI_DEVICE_ID_NI_PCI2322I
- PCI_DEVICE_ID_NI_PCI2324
- PCI_DEVICE_ID_NI_PCI2324I
- PCI_DEVICE_ID_NI_PCI2328
- PCI_DEVICE_ID_NI_PCI8430_23216
- PCI_DEVICE_ID_NI_PCI8430_2322
- PCI_DEVICE_ID_NI_PCI8430_2324
- PCI_DEVICE_ID_NI_PCI8430_2328
- PCI_DEVICE_ID_NI_PCI8432_2322
- PCI_DEVICE_ID_NI_PCI8432_2324
- PCI_DEVICE_ID_NI_PXI8420_23216
- PCI_DEVICE_ID_NI_PXI8420_2322
- PCI_DEVICE_ID_NI_PXI8420_2324
- PCI_DEVICE_ID_NI_PXI8420_2328
- PCI_DEVICE_ID_NI_PXI8422_2322
- PCI_DEVICE_ID_NI_PXI8422_2324
- PCI_DEVICE_ID_NI_PXI8430_23216
- PCI_DEVICE_ID_NI_PXI8430_2322
- PCI_DEVICE_ID_NI_PXI8430_2324
- PCI_DEVICE_ID_NI_PXI8430_2328
- PCI_DEVICE_ID_NI_PXI8432_2322
- PCI_DEVICE_ID_NI_PXI8432_2324
- PCI_DEVICE_ID_NLM_CMP
- PCI_DEVICE_ID_NLM_EHCI
- PCI_DEVICE_ID_NLM_FMN
- PCI_DEVICE_ID_NLM_I2C
- PCI_DEVICE_ID_NLM_ICI
- PCI_DEVICE_ID_NLM_MMC
- PCI_DEVICE_ID_NLM_NAE
- PCI_DEVICE_ID_NLM_NAND
- PCI_DEVICE_ID_NLM_NOR
- PCI_DEVICE_ID_NLM_OHCI
- PCI_DEVICE_ID_NLM_PCIE
- PCI_DEVICE_ID_NLM_PIC
- PCI_DEVICE_ID_NLM_POE
- PCI_DEVICE_ID_NLM_RAID
- PCI_DEVICE_ID_NLM_ROOT
- PCI_DEVICE_ID_NLM_RSA
- PCI_DEVICE_ID_NLM_SAE
- PCI_DEVICE_ID_NLM_SATA
- PCI_DEVICE_ID_NLM_UART
- PCI_DEVICE_ID_NLM_XHCI
- PCI_DEVICE_ID_NS_83815
- PCI_DEVICE_ID_NS_83820
- PCI_DEVICE_ID_NS_87410
- PCI_DEVICE_ID_NS_87415
- PCI_DEVICE_ID_NS_87560_LIO
- PCI_DEVICE_ID_NS_87560_USB
- PCI_DEVICE_ID_NS_CS5535_AUDIO
- PCI_DEVICE_ID_NS_CS5535_IDE
- PCI_DEVICE_ID_NS_CS5535_ISA
- PCI_DEVICE_ID_NS_CS5535_USB
- PCI_DEVICE_ID_NS_GX_HOST_BRIDGE
- PCI_DEVICE_ID_NS_GX_VIDEO
- PCI_DEVICE_ID_NS_SATURN
- PCI_DEVICE_ID_NS_SC1100_BRIDGE
- PCI_DEVICE_ID_NS_SC1100_SMI
- PCI_DEVICE_ID_NS_SC1100_XBUS
- PCI_DEVICE_ID_NS_SCx200_AUDIO
- PCI_DEVICE_ID_NS_SCx200_BRIDGE
- PCI_DEVICE_ID_NS_SCx200_IDE
- PCI_DEVICE_ID_NS_SCx200_SMI
- PCI_DEVICE_ID_NS_SCx200_VIDEO
- PCI_DEVICE_ID_NS_SCx200_XBUS
- PCI_DEVICE_ID_NVIDIA_CK804_AUDIO
- PCI_DEVICE_ID_NVIDIA_CK804_PCIE
- PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO
- PCI_DEVICE_ID_NVIDIA_CK8_AUDIO
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2
- PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE3
- PCI_DEVICE_ID_NVIDIA_GEFORCE3_1
- PCI_DEVICE_ID_NVIDIA_GEFORCE3_2
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE
- PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X
- PCI_DEVICE_ID_NVIDIA_GEFORCE_320M
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6200
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6600
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX
- PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2
- PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800
- PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX
- PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR
- PCI_DEVICE_ID_NVIDIA_IGEFORCE2
- PCI_DEVICE_ID_NVIDIA_ITNT2
- PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO
- PCI_DEVICE_ID_NVIDIA_MCP1_MODEM
- PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
- PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO
- PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
- PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO
- PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
- PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0
- PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4
- PCI_DEVICE_ID_NVIDIA_NFORCE
- PCI_DEVICE_ID_NVIDIA_NFORCE2
- PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE3
- PCI_DEVICE_ID_NVIDIA_NFORCE3S
- PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS
- PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA
- PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS
- PCI_DEVICE_ID_NVIDIA_NVENET_15
- PCI_DEVICE_ID_NVIDIA_QUADRO
- PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR
- PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO
- PCI_DEVICE_ID_NVIDIA_QUADRO4_200
- PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS
- PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL
- PCI_DEVICE_ID_NVIDIA_QUADRO_DDC
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000
- PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700
- PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI
- PCI_DEVICE_ID_NVIDIA_SGS_RIVA128
- PCI_DEVICE_ID_NVIDIA_TNT
- PCI_DEVICE_ID_NVIDIA_TNT2
- PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN
- PCI_DEVICE_ID_NVIDIA_UTNT2
- PCI_DEVICE_ID_NVIDIA_UVTNT2
- PCI_DEVICE_ID_NVIDIA_VTNT2
- PCI_DEVICE_ID_NX2031_10GCX4
- PCI_DEVICE_ID_NX2031_10GXSR
- PCI_DEVICE_ID_NX2031_4GCU
- PCI_DEVICE_ID_NX2031_HMEZ
- PCI_DEVICE_ID_NX2031_IMEZ
- PCI_DEVICE_ID_NX2031_XG_MGMT
- PCI_DEVICE_ID_NX2031_XG_MGMT2
- PCI_DEVICE_ID_NX2_5706
- PCI_DEVICE_ID_NX2_5706S
- PCI_DEVICE_ID_NX2_5708
- PCI_DEVICE_ID_NX2_5708S
- PCI_DEVICE_ID_NX2_5709
- PCI_DEVICE_ID_NX2_5709S
- PCI_DEVICE_ID_NX2_57710
- PCI_DEVICE_ID_NX2_57711
- PCI_DEVICE_ID_NX2_57711E
- PCI_DEVICE_ID_NX2_57712
- PCI_DEVICE_ID_NX2_57712E
- PCI_DEVICE_ID_NX2_57712_MF
- PCI_DEVICE_ID_NX2_57712_VF
- PCI_DEVICE_ID_NX2_57800
- PCI_DEVICE_ID_NX2_57800_MF
- PCI_DEVICE_ID_NX2_57800_VF
- PCI_DEVICE_ID_NX2_57810
- PCI_DEVICE_ID_NX2_57810_MF
- PCI_DEVICE_ID_NX2_57810_VF
- PCI_DEVICE_ID_NX2_57811
- PCI_DEVICE_ID_NX2_57811_MF
- PCI_DEVICE_ID_NX2_57811_VF
- PCI_DEVICE_ID_NX2_57840
- PCI_DEVICE_ID_NX2_57840_2_20
- PCI_DEVICE_ID_NX2_57840_4_10
- PCI_DEVICE_ID_NX2_57840_MF
- PCI_DEVICE_ID_NX2_57840_MFO
- PCI_DEVICE_ID_NX2_57840_O
- PCI_DEVICE_ID_NX2_57840_VF
- PCI_DEVICE_ID_NX3031
- PCI_DEVICE_ID_O2_6729
- PCI_DEVICE_ID_O2_6730
- PCI_DEVICE_ID_O2_6812
- PCI_DEVICE_ID_O2_6832
- PCI_DEVICE_ID_O2_6836
- PCI_DEVICE_ID_O2_6933
- PCI_DEVICE_ID_O2_8120
- PCI_DEVICE_ID_O2_8220
- PCI_DEVICE_ID_O2_8221
- PCI_DEVICE_ID_O2_8320
- PCI_DEVICE_ID_O2_8321
- PCI_DEVICE_ID_O2_FUJIN2
- PCI_DEVICE_ID_O2_SDS0
- PCI_DEVICE_ID_O2_SDS1
- PCI_DEVICE_ID_O2_SEABIRD0
- PCI_DEVICE_ID_O2_SEABIRD1
- PCI_DEVICE_ID_OCTPRO
- PCI_DEVICE_ID_OLICOM_OC2183
- PCI_DEVICE_ID_OLICOM_OC2325
- PCI_DEVICE_ID_OLICOM_OC2326
- PCI_DEVICE_ID_OPTI_82C558
- PCI_DEVICE_ID_OPTI_82C621
- PCI_DEVICE_ID_OPTI_82C700
- PCI_DEVICE_ID_OPTI_82C825
- PCI_DEVICE_ID_OXSEMI_12PCI840
- PCI_DEVICE_ID_OXSEMI_16PCI952
- PCI_DEVICE_ID_OXSEMI_16PCI952PP
- PCI_DEVICE_ID_OXSEMI_16PCI954
- PCI_DEVICE_ID_OXSEMI_16PCI954PP
- PCI_DEVICE_ID_OXSEMI_16PCI958
- PCI_DEVICE_ID_OXSEMI_16PCI95N
- PCI_DEVICE_ID_OXSEMI_C950
- PCI_DEVICE_ID_OXSEMI_PCIe840
- PCI_DEVICE_ID_OXSEMI_PCIe840_G
- PCI_DEVICE_ID_OXSEMI_PCIe952_0
- PCI_DEVICE_ID_OXSEMI_PCIe952_0_G
- PCI_DEVICE_ID_OXSEMI_PCIe952_1
- PCI_DEVICE_ID_OXSEMI_PCIe952_1_G
- PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU
- PCI_DEVICE_ID_OXSEMI_PCIe952_1_U
- PCI_DEVICE_ID_P1011
- PCI_DEVICE_ID_P1011E
- PCI_DEVICE_ID_P1013
- PCI_DEVICE_ID_P1013E
- PCI_DEVICE_ID_P1020
- PCI_DEVICE_ID_P1020E
- PCI_DEVICE_ID_P1021
- PCI_DEVICE_ID_P1021E
- PCI_DEVICE_ID_P1022
- PCI_DEVICE_ID_P1022E
- PCI_DEVICE_ID_P2010
- PCI_DEVICE_ID_P2010E
- PCI_DEVICE_ID_P2020
- PCI_DEVICE_ID_P2020E
- PCI_DEVICE_ID_P2040
- PCI_DEVICE_ID_P2040E
- PCI_DEVICE_ID_P3041
- PCI_DEVICE_ID_P3041E
- PCI_DEVICE_ID_P4040
- PCI_DEVICE_ID_P4040E
- PCI_DEVICE_ID_P4080
- PCI_DEVICE_ID_P4080E
- PCI_DEVICE_ID_P5010
- PCI_DEVICE_ID_P5010E
- PCI_DEVICE_ID_P5020
- PCI_DEVICE_ID_P5020E
- PCI_DEVICE_ID_PANACOM_DUALMODEM
- PCI_DEVICE_ID_PANACOM_QUADMODEM
- PCI_DEVICE_ID_PC300_RX_1
- PCI_DEVICE_ID_PC300_RX_2
- PCI_DEVICE_ID_PC300_TE_1
- PCI_DEVICE_ID_PC300_TE_2
- PCI_DEVICE_ID_PC300_TE_M_1
- PCI_DEVICE_ID_PC300_TE_M_2
- PCI_DEVICE_ID_PCH1_PHUB
- PCI_DEVICE_ID_PCH_1588
- PCI_DEVICE_ID_PCH_CAN
- PCI_DEVICE_ID_PCH_I2C
- PCI_DEVICE_ID_PCI230
- PCI_DEVICE_ID_PCI260
- PCI_DEVICE_ID_PCTECH_RZ1000
- PCI_DEVICE_ID_PCTECH_RZ1001
- PCI_DEVICE_ID_PCTECH_SAMURAI_IDE
- PCI_DEVICE_ID_PEGASUS
- PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF
- PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF
- PCI_DEVICE_ID_PENWELL
- PCI_DEVICE_ID_PERC4E_DI_CORVETTE
- PCI_DEVICE_ID_PERC4E_DI_EXPEDITION
- PCI_DEVICE_ID_PERC4E_DI_GUADALUPE
- PCI_DEVICE_ID_PERC4E_DI_KOBUK
- PCI_DEVICE_ID_PERC4E_SI_BIGBEND
- PCI_DEVICE_ID_PERC4_DC
- PCI_DEVICE_ID_PERC4_DI
- PCI_DEVICE_ID_PERC4_DI_DISCOVERY
- PCI_DEVICE_ID_PERC4_DI_EVERGLADES
- PCI_DEVICE_ID_PERC4_QC_VERDE
- PCI_DEVICE_ID_PERC4_SC
- PCI_DEVICE_ID_PERICOM_PI7C9X7951
- PCI_DEVICE_ID_PERICOM_PI7C9X7952
- PCI_DEVICE_ID_PERICOM_PI7C9X7954
- PCI_DEVICE_ID_PERICOM_PI7C9X7958
- PCI_DEVICE_ID_PFLY
- PCI_DEVICE_ID_PHILIPS_SAA7130
- PCI_DEVICE_ID_PHILIPS_SAA7133
- PCI_DEVICE_ID_PHILIPS_SAA7134
- PCI_DEVICE_ID_PHILIPS_SAA7135
- PCI_DEVICE_ID_PHILIPS_SAA7146
- PCI_DEVICE_ID_PHILIPS_SAA9730
- PCI_DEVICE_ID_PICOPOWER_PT86C523
- PCI_DEVICE_ID_PICOPOWER_PT86C523BBP
- PCI_DEVICE_ID_PLUTO2
- PCI_DEVICE_ID_PLX_1077
- PCI_DEVICE_ID_PLX_9030
- PCI_DEVICE_ID_PLX_9050
- PCI_DEVICE_ID_PLX_9056
- PCI_DEVICE_ID_PLX_9080
- PCI_DEVICE_ID_PLX_CRONYX_OMEGA
- PCI_DEVICE_ID_PLX_DJINN_ITOO
- PCI_DEVICE_ID_PLX_GTEK_SERIAL2
- PCI_DEVICE_ID_PLX_LX6464ES
- PCI_DEVICE_ID_PLX_OLITEC
- PCI_DEVICE_ID_PLX_PCI200SYN
- PCI_DEVICE_ID_PLX_R685
- PCI_DEVICE_ID_PLX_R753
- PCI_DEVICE_ID_PLX_ROMULUS
- PCI_DEVICE_ID_PLX_SPCOM200
- PCI_DEVICE_ID_PLX_SPCOM800
- PCI_DEVICE_ID_PMC_MAXRAID
- PCI_DEVICE_ID_POS104UL
- PCI_DEVICE_ID_PROC_BDW_THERMAL
- PCI_DEVICE_ID_PROC_BSW_THERMAL
- PCI_DEVICE_ID_PROC_BXT0_THERMAL
- PCI_DEVICE_ID_PROC_BXT1_THERMAL
- PCI_DEVICE_ID_PROC_BXTP_THERMAL
- PCI_DEVICE_ID_PROC_BXTX_THERMAL
- PCI_DEVICE_ID_PROC_CFL_THERMAL
- PCI_DEVICE_ID_PROC_CNL_THERMAL
- PCI_DEVICE_ID_PROC_GLK_THERMAL
- PCI_DEVICE_ID_PROC_HSB_THERMAL
- PCI_DEVICE_ID_PROC_ICL_THERMAL
- PCI_DEVICE_ID_PROC_SKL_THERMAL
- PCI_DEVICE_ID_PROMISE_20246
- PCI_DEVICE_ID_PROMISE_20262
- PCI_DEVICE_ID_PROMISE_20263
- PCI_DEVICE_ID_PROMISE_20265
- PCI_DEVICE_ID_PROMISE_20267
- PCI_DEVICE_ID_PROMISE_20268
- PCI_DEVICE_ID_PROMISE_20269
- PCI_DEVICE_ID_PROMISE_20270
- PCI_DEVICE_ID_PROMISE_20271
- PCI_DEVICE_ID_PROMISE_20275
- PCI_DEVICE_ID_PROMISE_20276
- PCI_DEVICE_ID_PROMISE_20277
- PCI_DEVICE_ID_PROTEUS_PF
- PCI_DEVICE_ID_PROTEUS_S
- PCI_DEVICE_ID_PROTEUS_VF
- PCI_DEVICE_ID_QLOGIC_IB_6120
- PCI_DEVICE_ID_QLOGIC_IB_7220
- PCI_DEVICE_ID_QLOGIC_IB_7322
- PCI_DEVICE_ID_QLOGIC_ISP10160
- PCI_DEVICE_ID_QLOGIC_ISP1020
- PCI_DEVICE_ID_QLOGIC_ISP1080
- PCI_DEVICE_ID_QLOGIC_ISP12160
- PCI_DEVICE_ID_QLOGIC_ISP1240
- PCI_DEVICE_ID_QLOGIC_ISP1280
- PCI_DEVICE_ID_QLOGIC_ISP2031
- PCI_DEVICE_ID_QLOGIC_ISP2061
- PCI_DEVICE_ID_QLOGIC_ISP2071
- PCI_DEVICE_ID_QLOGIC_ISP2081
- PCI_DEVICE_ID_QLOGIC_ISP2089
- PCI_DEVICE_ID_QLOGIC_ISP2100
- PCI_DEVICE_ID_QLOGIC_ISP2200
- PCI_DEVICE_ID_QLOGIC_ISP2261
- PCI_DEVICE_ID_QLOGIC_ISP2271
- PCI_DEVICE_ID_QLOGIC_ISP2281
- PCI_DEVICE_ID_QLOGIC_ISP2289
- PCI_DEVICE_ID_QLOGIC_ISP2300
- PCI_DEVICE_ID_QLOGIC_ISP2312
- PCI_DEVICE_ID_QLOGIC_ISP2322
- PCI_DEVICE_ID_QLOGIC_ISP2422
- PCI_DEVICE_ID_QLOGIC_ISP2432
- PCI_DEVICE_ID_QLOGIC_ISP2512
- PCI_DEVICE_ID_QLOGIC_ISP2522
- PCI_DEVICE_ID_QLOGIC_ISP2532
- PCI_DEVICE_ID_QLOGIC_ISP4010
- PCI_DEVICE_ID_QLOGIC_ISP4022
- PCI_DEVICE_ID_QLOGIC_ISP4032
- PCI_DEVICE_ID_QLOGIC_ISP5422
- PCI_DEVICE_ID_QLOGIC_ISP5432
- PCI_DEVICE_ID_QLOGIC_ISP6312
- PCI_DEVICE_ID_QLOGIC_ISP6322
- PCI_DEVICE_ID_QLOGIC_ISP8001
- PCI_DEVICE_ID_QLOGIC_ISP8021
- PCI_DEVICE_ID_QLOGIC_ISP8022
- PCI_DEVICE_ID_QLOGIC_ISP8031
- PCI_DEVICE_ID_QLOGIC_ISP8042
- PCI_DEVICE_ID_QLOGIC_ISP8044
- PCI_DEVICE_ID_QLOGIC_ISP8324
- PCI_DEVICE_ID_QLOGIC_ISP8432
- PCI_DEVICE_ID_QLOGIC_ISPF001
- PCI_DEVICE_ID_QLOGIC_QLE824X
- PCI_DEVICE_ID_QLOGIC_QLE834X
- PCI_DEVICE_ID_QLOGIC_QLE844X
- PCI_DEVICE_ID_QLOGIC_QLE8830
- PCI_DEVICE_ID_QLOGIC_VF_QLE834X
- PCI_DEVICE_ID_QLOGIC_VF_QLE844X
- PCI_DEVICE_ID_QLOGIC_VF_QLE8C30
- PCI_DEVICE_ID_QUADRO_FX_1400
- PCI_DEVICE_ID_QUADRO_FX_GO1400
- PCI_DEVICE_ID_QUATECH_DSC100
- PCI_DEVICE_ID_QUATECH_DSC100E
- PCI_DEVICE_ID_QUATECH_DSC200
- PCI_DEVICE_ID_QUATECH_DSC200E
- PCI_DEVICE_ID_QUATECH_DSCLP100
- PCI_DEVICE_ID_QUATECH_DSCLP200
- PCI_DEVICE_ID_QUATECH_DSCP100
- PCI_DEVICE_ID_QUATECH_DSCP200
- PCI_DEVICE_ID_QUATECH_ESC100D
- PCI_DEVICE_ID_QUATECH_ESC100M
- PCI_DEVICE_ID_QUATECH_ESCLP100
- PCI_DEVICE_ID_QUATECH_QSC100
- PCI_DEVICE_ID_QUATECH_QSC200
- PCI_DEVICE_ID_QUATECH_QSCLP100
- PCI_DEVICE_ID_QUATECH_QSCLP200
- PCI_DEVICE_ID_QUATECH_QSCP100
- PCI_DEVICE_ID_QUATECH_QSCP200
- PCI_DEVICE_ID_QUATECH_SPPXP_100
- PCI_DEVICE_ID_QUATECH_SSCLP100
- PCI_DEVICE_ID_QUATECH_SSCLP200
- PCI_DEVICE_ID_QUICKNET_XJ
- PCI_DEVICE_ID_RASTEL_2PORT
- PCI_DEVICE_ID_RD890_IOMMU
- PCI_DEVICE_ID_RDC_D1010
- PCI_DEVICE_ID_RDC_R6020
- PCI_DEVICE_ID_RDC_R6030
- PCI_DEVICE_ID_RDC_R6040
- PCI_DEVICE_ID_RDC_R6060
- PCI_DEVICE_ID_RDC_R6061
- PCI_DEVICE_ID_RDK1
- PCI_DEVICE_ID_RDK2
- PCI_DEVICE_ID_REALTEK_5250
- PCI_DEVICE_ID_REALTEK_8139
- PCI_DEVICE_ID_REDHAT_ROCKER
- PCI_DEVICE_ID_RENESAS_SH7763
- PCI_DEVICE_ID_RENESAS_SH7780
- PCI_DEVICE_ID_RENESAS_SH7781
- PCI_DEVICE_ID_RENESAS_SH7785
- PCI_DEVICE_ID_RENESAS_SH7786
- PCI_DEVICE_ID_REVOLUTION
- PCI_DEVICE_ID_RFLY
- PCI_DEVICE_ID_RICOH_R5C822
- PCI_DEVICE_ID_RICOH_R5C832
- PCI_DEVICE_ID_RICOH_R5C843
- PCI_DEVICE_ID_RICOH_R5CE822
- PCI_DEVICE_ID_RICOH_R5CE823
- PCI_DEVICE_ID_RICOH_RL5C465
- PCI_DEVICE_ID_RICOH_RL5C466
- PCI_DEVICE_ID_RICOH_RL5C475
- PCI_DEVICE_ID_RICOH_RL5C476
- PCI_DEVICE_ID_RICOH_RL5C478
- PCI_DEVICE_ID_RME_DIGI32
- PCI_DEVICE_ID_RME_DIGI32_8
- PCI_DEVICE_ID_RME_DIGI32_PRO
- PCI_DEVICE_ID_RME_DIGI96
- PCI_DEVICE_ID_RME_DIGI96_8
- PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
- PCI_DEVICE_ID_RME_DIGI96_8_PRO
- PCI_DEVICE_ID_ROHM_ML7213_PHUB
- PCI_DEVICE_ID_ROHM_ML7223_GBE
- PCI_DEVICE_ID_ROHM_ML7223_mPHUB
- PCI_DEVICE_ID_ROHM_ML7223_nPHUB
- PCI_DEVICE_ID_ROHM_ML7831_GBE
- PCI_DEVICE_ID_ROHM_ML7831_PHUB
- PCI_DEVICE_ID_RP16INTF
- PCI_DEVICE_ID_RP16SNI
- PCI_DEVICE_ID_RP2_232
- PCI_DEVICE_ID_RP2_422
- PCI_DEVICE_ID_RP32INTF
- PCI_DEVICE_ID_RP4J
- PCI_DEVICE_ID_RP4M
- PCI_DEVICE_ID_RP4QUAD
- PCI_DEVICE_ID_RP6M
- PCI_DEVICE_ID_RP8INTF
- PCI_DEVICE_ID_RP8J
- PCI_DEVICE_ID_RP8OCTA
- PCI_DEVICE_ID_RP8SNI
- PCI_DEVICE_ID_RPP4
- PCI_DEVICE_ID_RPP8
- PCI_DEVICE_ID_S1120
- PCI_DEVICE_ID_S2IO_UNI
- PCI_DEVICE_ID_S2IO_WIN
- PCI_DEVICE_ID_S3_868
- PCI_DEVICE_ID_S3_968
- PCI_DEVICE_ID_S3_PROSAVAGE8
- PCI_DEVICE_ID_S3_SAVAGE4
- PCI_DEVICE_ID_S3_SONICVIBES
- PCI_DEVICE_ID_S3_TRIO
- PCI_DEVICE_ID_SAT
- PCI_DEVICE_ID_SATSAGEM_NICCY
- PCI_DEVICE_ID_SAT_DCSP
- PCI_DEVICE_ID_SAT_MID
- PCI_DEVICE_ID_SAT_S
- PCI_DEVICE_ID_SAT_SCSP
- PCI_DEVICE_ID_SAT_SMB
- PCI_DEVICE_ID_SBE_WANXL100
- PCI_DEVICE_ID_SBE_WANXL200
- PCI_DEVICE_ID_SBE_WANXL400
- PCI_DEVICE_ID_SCALEMP_VSMP_CTL
- PCI_DEVICE_ID_SDV_GPIO
- PCI_DEVICE_ID_SEALEVEL_7803
- PCI_DEVICE_ID_SEALEVEL_COMM4
- PCI_DEVICE_ID_SEALEVEL_COMM8
- PCI_DEVICE_ID_SEALEVEL_U530
- PCI_DEVICE_ID_SEALEVEL_UCOMM2
- PCI_DEVICE_ID_SEALEVEL_UCOMM232
- PCI_DEVICE_ID_SEALEVEL_UCOMM422
- PCI_DEVICE_ID_SEALEVEL_UCOMM8
- PCI_DEVICE_ID_SEGA_BBA
- PCI_DEVICE_ID_SERVERWORKS_CSB5
- PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
- PCI_DEVICE_ID_SERVERWORKS_CSB6
- PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
- PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
- PCI_DEVICE_ID_SERVERWORKS_CSB6LPC
- PCI_DEVICE_ID_SERVERWORKS_EPB
- PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
- PCI_DEVICE_ID_SERVERWORKS_HE
- PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
- PCI_DEVICE_ID_SERVERWORKS_HT1000SB
- PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB
- PCI_DEVICE_ID_SERVERWORKS_HT1100LD
- PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE
- PCI_DEVICE_ID_SERVERWORKS_LE
- PCI_DEVICE_ID_SERVERWORKS_OSB4
- PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
- PCI_DEVICE_ID_SGI_ACENIC
- PCI_DEVICE_ID_SGI_IOC3
- PCI_DEVICE_ID_SGI_LITHIUM
- PCI_DEVICE_ID_SIEMENS_DSCC4
- PCI_DEVICE_ID_SIIG_1P_10x
- PCI_DEVICE_ID_SIIG_1P_20x
- PCI_DEVICE_ID_SIIG_1S1P_10x_550
- PCI_DEVICE_ID_SIIG_1S1P_10x_650
- PCI_DEVICE_ID_SIIG_1S1P_10x_850
- PCI_DEVICE_ID_SIIG_1S1P_20x_550
- PCI_DEVICE_ID_SIIG_1S1P_20x_650
- PCI_DEVICE_ID_SIIG_1S1P_20x_850
- PCI_DEVICE_ID_SIIG_1S_10x
- PCI_DEVICE_ID_SIIG_1S_10x_550
- PCI_DEVICE_ID_SIIG_1S_10x_650
- PCI_DEVICE_ID_SIIG_1S_10x_850
- PCI_DEVICE_ID_SIIG_1S_20x_550
- PCI_DEVICE_ID_SIIG_1S_20x_650
- PCI_DEVICE_ID_SIIG_1S_20x_850
- PCI_DEVICE_ID_SIIG_2P1S_20x_550
- PCI_DEVICE_ID_SIIG_2P1S_20x_650
- PCI_DEVICE_ID_SIIG_2P1S_20x_850
- PCI_DEVICE_ID_SIIG_2P_10x
- PCI_DEVICE_ID_SIIG_2P_20x
- PCI_DEVICE_ID_SIIG_2S1P_10x_550
- PCI_DEVICE_ID_SIIG_2S1P_10x_650
- PCI_DEVICE_ID_SIIG_2S1P_10x_850
- PCI_DEVICE_ID_SIIG_2S1P_20x
- PCI_DEVICE_ID_SIIG_2S1P_20x_550
- PCI_DEVICE_ID_SIIG_2S1P_20x_650
- PCI_DEVICE_ID_SIIG_2S1P_20x_850
- PCI_DEVICE_ID_SIIG_2S_10x
- PCI_DEVICE_ID_SIIG_2S_10x_550
- PCI_DEVICE_ID_SIIG_2S_10x_650
- PCI_DEVICE_ID_SIIG_2S_10x_850
- PCI_DEVICE_ID_SIIG_2S_20x
- PCI_DEVICE_ID_SIIG_2S_20x_550
- PCI_DEVICE_ID_SIIG_2S_20x_650
- PCI_DEVICE_ID_SIIG_2S_20x_850
- PCI_DEVICE_ID_SIIG_4S_10x_550
- PCI_DEVICE_ID_SIIG_4S_10x_650
- PCI_DEVICE_ID_SIIG_4S_10x_850
- PCI_DEVICE_ID_SIIG_4S_20x_550
- PCI_DEVICE_ID_SIIG_4S_20x_650
- PCI_DEVICE_ID_SIIG_4S_20x_850
- PCI_DEVICE_ID_SIIG_8S_20x_550
- PCI_DEVICE_ID_SIIG_8S_20x_650
- PCI_DEVICE_ID_SIIG_8S_20x_850
- PCI_DEVICE_ID_SII_1210SA
- PCI_DEVICE_ID_SII_3112
- PCI_DEVICE_ID_SII_680
- PCI_DEVICE_ID_SITECOM_DC105V2
- PCI_DEVICE_ID_SI_1180
- PCI_DEVICE_ID_SI_300
- PCI_DEVICE_ID_SI_315
- PCI_DEVICE_ID_SI_315H
- PCI_DEVICE_ID_SI_315PRO
- PCI_DEVICE_ID_SI_330
- PCI_DEVICE_ID_SI_496
- PCI_DEVICE_ID_SI_501
- PCI_DEVICE_ID_SI_503
- PCI_DEVICE_ID_SI_530
- PCI_DEVICE_ID_SI_540
- PCI_DEVICE_ID_SI_540_VGA
- PCI_DEVICE_ID_SI_550
- PCI_DEVICE_ID_SI_550_VGA
- PCI_DEVICE_ID_SI_5511
- PCI_DEVICE_ID_SI_5513
- PCI_DEVICE_ID_SI_5517
- PCI_DEVICE_ID_SI_5518
- PCI_DEVICE_ID_SI_5571
- PCI_DEVICE_ID_SI_5581
- PCI_DEVICE_ID_SI_5582
- PCI_DEVICE_ID_SI_5591
- PCI_DEVICE_ID_SI_5591_AGP
- PCI_DEVICE_ID_SI_5596
- PCI_DEVICE_ID_SI_5597
- PCI_DEVICE_ID_SI_5597_VGA
- PCI_DEVICE_ID_SI_5598
- PCI_DEVICE_ID_SI_5600
- PCI_DEVICE_ID_SI_620
- PCI_DEVICE_ID_SI_6202
- PCI_DEVICE_ID_SI_6205
- PCI_DEVICE_ID_SI_630
- PCI_DEVICE_ID_SI_630_VGA
- PCI_DEVICE_ID_SI_633
- PCI_DEVICE_ID_SI_635
- PCI_DEVICE_ID_SI_640
- PCI_DEVICE_ID_SI_645
- PCI_DEVICE_ID_SI_646
- PCI_DEVICE_ID_SI_648
- PCI_DEVICE_ID_SI_650
- PCI_DEVICE_ID_SI_650_VGA
- PCI_DEVICE_ID_SI_651
- PCI_DEVICE_ID_SI_655
- PCI_DEVICE_ID_SI_660
- PCI_DEVICE_ID_SI_660_VGA
- PCI_DEVICE_ID_SI_661
- PCI_DEVICE_ID_SI_662
- PCI_DEVICE_ID_SI_671
- PCI_DEVICE_ID_SI_7012
- PCI_DEVICE_ID_SI_7013
- PCI_DEVICE_ID_SI_7016
- PCI_DEVICE_ID_SI_7018
- PCI_DEVICE_ID_SI_730
- PCI_DEVICE_ID_SI_733
- PCI_DEVICE_ID_SI_735
- PCI_DEVICE_ID_SI_740
- PCI_DEVICE_ID_SI_741
- PCI_DEVICE_ID_SI_745
- PCI_DEVICE_ID_SI_746
- PCI_DEVICE_ID_SI_755
- PCI_DEVICE_ID_SI_760
- PCI_DEVICE_ID_SI_761
- PCI_DEVICE_ID_SI_900
- PCI_DEVICE_ID_SI_961
- PCI_DEVICE_ID_SI_962
- PCI_DEVICE_ID_SI_963
- PCI_DEVICE_ID_SI_964
- PCI_DEVICE_ID_SI_965
- PCI_DEVICE_ID_SI_966
- PCI_DEVICE_ID_SI_968
- PCI_DEVICE_ID_SI_ACPI
- PCI_DEVICE_ID_SI_LPC
- PCI_DEVICE_ID_SI_SMBUS
- PCI_DEVICE_ID_SKYHAWK
- PCI_DEVICE_ID_SKYHAWK_VF
- PCI_DEVICE_ID_SK_FP
- PCI_DEVICE_ID_SMSC_LAN7430
- PCI_DEVICE_ID_SMSC_LAN7431
- PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0
- PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1
- PCI_DEVICE_ID_SOLARFLARE_SFC4000B
- PCI_DEVICE_ID_SOLO6010
- PCI_DEVICE_ID_SOLO6110
- PCI_DEVICE_ID_SP1011
- PCI_DEVICE_ID_STG4000
- PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA
- PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS
- PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS
- PCI_DEVICE_ID_STMICRO_CAN
- PCI_DEVICE_ID_STMICRO_DBP
- PCI_DEVICE_ID_STMICRO_ESRAM
- PCI_DEVICE_ID_STMICRO_GPIO
- PCI_DEVICE_ID_STMICRO_I2C
- PCI_DEVICE_ID_STMICRO_MAC
- PCI_DEVICE_ID_STMICRO_MLB
- PCI_DEVICE_ID_STMICRO_SATA
- PCI_DEVICE_ID_STMICRO_SATA_PHY
- PCI_DEVICE_ID_STMICRO_SDIO
- PCI_DEVICE_ID_STMICRO_SDIO_EMMC
- PCI_DEVICE_ID_STMICRO_SOC_DMA
- PCI_DEVICE_ID_STMICRO_SPI_HS
- PCI_DEVICE_ID_STMICRO_UART_HWFC
- PCI_DEVICE_ID_STMICRO_UART_NO_HWFC
- PCI_DEVICE_ID_STMICRO_USB_HOST
- PCI_DEVICE_ID_STMICRO_USB_OHCI
- PCI_DEVICE_ID_STMICRO_USB_OTG
- PCI_DEVICE_ID_STMICRO_VIC
- PCI_DEVICE_ID_STMICRO_VIP
- PCI_DEVICE_ID_SUNIX_1999
- PCI_DEVICE_ID_SUN_CASSINI
- PCI_DEVICE_ID_SUN_EBUS
- PCI_DEVICE_ID_SUN_GEM
- PCI_DEVICE_ID_SUN_HAPPYMEAL
- PCI_DEVICE_ID_SUN_HUMMINGBIRD
- PCI_DEVICE_ID_SUN_PBM
- PCI_DEVICE_ID_SUN_RIO_1394
- PCI_DEVICE_ID_SUN_RIO_EBUS
- PCI_DEVICE_ID_SUN_RIO_GEM
- PCI_DEVICE_ID_SUN_RIO_USB
- PCI_DEVICE_ID_SUN_SABRE
- PCI_DEVICE_ID_SUN_SCHIZO
- PCI_DEVICE_ID_SUN_SIMBA
- PCI_DEVICE_ID_SUN_TOMATILLO
- PCI_DEVICE_ID_SUPERFLY
- PCI_DEVICE_ID_SYBA_1P_ECP
- PCI_DEVICE_ID_SYBA_2P_EPP
- PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC
- PCI_DEVICE_ID_SYNOPSYS_EDDA
- PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3
- PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31
- PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI
- PCI_DEVICE_ID_SYSKONNECT_8000
- PCI_DEVICE_ID_SYSKONNECT_9DXX
- PCI_DEVICE_ID_SYSKONNECT_9MXX
- PCI_DEVICE_ID_SYSKONNECT_GE
- PCI_DEVICE_ID_SYSKONNECT_TR
- PCI_DEVICE_ID_SYSKONNECT_YU
- PCI_DEVICE_ID_TANGIER
- PCI_DEVICE_ID_TCONRAD_TOKENRING
- PCI_DEVICE_ID_TDI_EHCI
- PCI_DEVICE_ID_TECHWELL_5864
- PCI_DEVICE_ID_TECHWELL_6800
- PCI_DEVICE_ID_TECHWELL_6801
- PCI_DEVICE_ID_TECHWELL_6804
- PCI_DEVICE_ID_TECHWELL_6816_1
- PCI_DEVICE_ID_TECHWELL_6816_2
- PCI_DEVICE_ID_TECHWELL_6816_3
- PCI_DEVICE_ID_TECHWELL_6816_4
- PCI_DEVICE_ID_TEHUTI_3009
- PCI_DEVICE_ID_TEHUTI_3010
- PCI_DEVICE_ID_TEHUTI_3014
- PCI_DEVICE_ID_TEKRAM_DC290
- PCI_DEVICE_ID_TEKRAM_TRMS1040
- PCI_DEVICE_ID_TFLY
- PCI_DEVICE_ID_THOR
- PCI_DEVICE_ID_THUNDERX_ZIP
- PCI_DEVICE_ID_THUNDER_BGX
- PCI_DEVICE_ID_THUNDER_L2C_CBC
- PCI_DEVICE_ID_THUNDER_L2C_MCI
- PCI_DEVICE_ID_THUNDER_L2C_TAD
- PCI_DEVICE_ID_THUNDER_LMC
- PCI_DEVICE_ID_THUNDER_NIC_PF
- PCI_DEVICE_ID_THUNDER_NIC_VF
- PCI_DEVICE_ID_THUNDER_OCX
- PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF
- PCI_DEVICE_ID_THUNDER_RGX
- PCI_DEVICE_ID_THUNDER_TWSI
- PCI_DEVICE_ID_TIGERJET_100
- PCI_DEVICE_ID_TIGERJET_300
- PCI_DEVICE_ID_TIGERSHARK
- PCI_DEVICE_ID_TIGON3_5700
- PCI_DEVICE_ID_TIGON3_5701
- PCI_DEVICE_ID_TIGON3_5702
- PCI_DEVICE_ID_TIGON3_5702A3
- PCI_DEVICE_ID_TIGON3_5702FE
- PCI_DEVICE_ID_TIGON3_5702X
- PCI_DEVICE_ID_TIGON3_5703
- PCI_DEVICE_ID_TIGON3_5703A3
- PCI_DEVICE_ID_TIGON3_5703X
- PCI_DEVICE_ID_TIGON3_5704
- PCI_DEVICE_ID_TIGON3_5704S
- PCI_DEVICE_ID_TIGON3_5704S_2
- PCI_DEVICE_ID_TIGON3_5705
- PCI_DEVICE_ID_TIGON3_5705F
- PCI_DEVICE_ID_TIGON3_5705M
- PCI_DEVICE_ID_TIGON3_5705M_2
- PCI_DEVICE_ID_TIGON3_5705_2
- PCI_DEVICE_ID_TIGON3_5714
- PCI_DEVICE_ID_TIGON3_5714S
- PCI_DEVICE_ID_TIGON3_5715
- PCI_DEVICE_ID_TIGON3_5715S
- PCI_DEVICE_ID_TIGON3_5719
- PCI_DEVICE_ID_TIGON3_5721
- PCI_DEVICE_ID_TIGON3_5722
- PCI_DEVICE_ID_TIGON3_5723
- PCI_DEVICE_ID_TIGON3_5750
- PCI_DEVICE_ID_TIGON3_5751
- PCI_DEVICE_ID_TIGON3_5751F
- PCI_DEVICE_ID_TIGON3_5751M
- PCI_DEVICE_ID_TIGON3_5752
- PCI_DEVICE_ID_TIGON3_5752M
- PCI_DEVICE_ID_TIGON3_5753
- PCI_DEVICE_ID_TIGON3_5753F
- PCI_DEVICE_ID_TIGON3_5753M
- PCI_DEVICE_ID_TIGON3_5754
- PCI_DEVICE_ID_TIGON3_5754M
- PCI_DEVICE_ID_TIGON3_5755
- PCI_DEVICE_ID_TIGON3_5755M
- PCI_DEVICE_ID_TIGON3_5756
- PCI_DEVICE_ID_TIGON3_5761
- PCI_DEVICE_ID_TIGON3_5761E
- PCI_DEVICE_ID_TIGON3_5764
- PCI_DEVICE_ID_TIGON3_5780
- PCI_DEVICE_ID_TIGON3_5780S
- PCI_DEVICE_ID_TIGON3_5781
- PCI_DEVICE_ID_TIGON3_5782
- PCI_DEVICE_ID_TIGON3_5784
- PCI_DEVICE_ID_TIGON3_5786
- PCI_DEVICE_ID_TIGON3_5787
- PCI_DEVICE_ID_TIGON3_5787F
- PCI_DEVICE_ID_TIGON3_5787M
- PCI_DEVICE_ID_TIGON3_5788
- PCI_DEVICE_ID_TIGON3_5789
- PCI_DEVICE_ID_TIGON3_5901
- PCI_DEVICE_ID_TIGON3_5901_2
- PCI_DEVICE_ID_TIGON3_5906
- PCI_DEVICE_ID_TIGON3_5906M
- PCI_DEVICE_ID_TIMB
- PCI_DEVICE_ID_TIMEDIA_1889
- PCI_DEVICE_ID_TITAN_010L
- PCI_DEVICE_ID_TITAN_100
- PCI_DEVICE_ID_TITAN_100E
- PCI_DEVICE_ID_TITAN_100L
- PCI_DEVICE_ID_TITAN_110L
- PCI_DEVICE_ID_TITAN_200
- PCI_DEVICE_ID_TITAN_200E
- PCI_DEVICE_ID_TITAN_200EI
- PCI_DEVICE_ID_TITAN_200EISI
- PCI_DEVICE_ID_TITAN_200I
- PCI_DEVICE_ID_TITAN_200L
- PCI_DEVICE_ID_TITAN_200V3
- PCI_DEVICE_ID_TITAN_210L
- PCI_DEVICE_ID_TITAN_400
- PCI_DEVICE_ID_TITAN_400E
- PCI_DEVICE_ID_TITAN_400EH
- PCI_DEVICE_ID_TITAN_400I
- PCI_DEVICE_ID_TITAN_400L
- PCI_DEVICE_ID_TITAN_400V3
- PCI_DEVICE_ID_TITAN_410V3
- PCI_DEVICE_ID_TITAN_800B
- PCI_DEVICE_ID_TITAN_800E
- PCI_DEVICE_ID_TITAN_800EH
- PCI_DEVICE_ID_TITAN_800EHB
- PCI_DEVICE_ID_TITAN_800I
- PCI_DEVICE_ID_TITAN_800L
- PCI_DEVICE_ID_TITAN_800V3
- PCI_DEVICE_ID_TITAN_800V3B
- PCI_DEVICE_ID_TITAN_UNI
- PCI_DEVICE_ID_TITAN_WIN
- PCI_DEVICE_ID_TI_1031
- PCI_DEVICE_ID_TI_1130
- PCI_DEVICE_ID_TI_1131
- PCI_DEVICE_ID_TI_1210
- PCI_DEVICE_ID_TI_1211
- PCI_DEVICE_ID_TI_1220
- PCI_DEVICE_ID_TI_1221
- PCI_DEVICE_ID_TI_1225
- PCI_DEVICE_ID_TI_1250
- PCI_DEVICE_ID_TI_1251A
- PCI_DEVICE_ID_TI_1251B
- PCI_DEVICE_ID_TI_1410
- PCI_DEVICE_ID_TI_1420
- PCI_DEVICE_ID_TI_1450
- PCI_DEVICE_ID_TI_1451A
- PCI_DEVICE_ID_TI_1510
- PCI_DEVICE_ID_TI_1520
- PCI_DEVICE_ID_TI_1620
- PCI_DEVICE_ID_TI_4410
- PCI_DEVICE_ID_TI_4450
- PCI_DEVICE_ID_TI_4451
- PCI_DEVICE_ID_TI_4510
- PCI_DEVICE_ID_TI_4520
- PCI_DEVICE_ID_TI_7410
- PCI_DEVICE_ID_TI_7510
- PCI_DEVICE_ID_TI_7610
- PCI_DEVICE_ID_TI_AM654
- PCI_DEVICE_ID_TI_DRA72x
- PCI_DEVICE_ID_TI_DRA74x
- PCI_DEVICE_ID_TI_PCILYNX
- PCI_DEVICE_ID_TI_TSB12LV22
- PCI_DEVICE_ID_TI_TSB12LV26
- PCI_DEVICE_ID_TI_TSB82AA2
- PCI_DEVICE_ID_TI_TVP4020
- PCI_DEVICE_ID_TI_X420
- PCI_DEVICE_ID_TI_X515
- PCI_DEVICE_ID_TI_X620
- PCI_DEVICE_ID_TI_XIO2000A
- PCI_DEVICE_ID_TI_XX12
- PCI_DEVICE_ID_TI_XX12_FM
- PCI_DEVICE_ID_TI_XX20_FM
- PCI_DEVICE_ID_TI_XX21_XX11
- PCI_DEVICE_ID_TI_XX21_XX11_FM
- PCI_DEVICE_ID_TI_XX21_XX11_SD
- PCI_DEVICE_ID_TOMCAT
- PCI_DEVICE_ID_TOPIC_TP560
- PCI_DEVICE_ID_TOSHIBA_PICCOLO_1
- PCI_DEVICE_ID_TOSHIBA_PICCOLO_2
- PCI_DEVICE_ID_TOSHIBA_PICCOLO_3
- PCI_DEVICE_ID_TOSHIBA_PICCOLO_5
- PCI_DEVICE_ID_TOSHIBA_SPIDER_NET
- PCI_DEVICE_ID_TOSHIBA_TC35815CF
- PCI_DEVICE_ID_TOSHIBA_TC35815_NWU
- PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939
- PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE
- PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC
- PCI_DEVICE_ID_TOSHIBA_TOPIC100
- PCI_DEVICE_ID_TOSHIBA_TOPIC95
- PCI_DEVICE_ID_TOSHIBA_TOPIC97
- PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
- PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
- PCI_DEVICE_ID_TRIDENT_8400
- PCI_DEVICE_ID_TRIDENT_8420
- PCI_DEVICE_ID_TRIDENT_8500
- PCI_DEVICE_ID_TRIDENT_9320
- PCI_DEVICE_ID_TRIDENT_9388
- PCI_DEVICE_ID_TRIDENT_9397
- PCI_DEVICE_ID_TRIDENT_939A
- PCI_DEVICE_ID_TRIDENT_9420
- PCI_DEVICE_ID_TRIDENT_9440
- PCI_DEVICE_ID_TRIDENT_9520
- PCI_DEVICE_ID_TRIDENT_9525
- PCI_DEVICE_ID_TRIDENT_9660
- PCI_DEVICE_ID_TRIDENT_9750
- PCI_DEVICE_ID_TRIDENT_9850
- PCI_DEVICE_ID_TRIDENT_9880
- PCI_DEVICE_ID_TSENG_ET6000
- PCI_DEVICE_ID_TSENG_W32P_2
- PCI_DEVICE_ID_TSENG_W32P_b
- PCI_DEVICE_ID_TSENG_W32P_c
- PCI_DEVICE_ID_TSENG_W32P_d
- PCI_DEVICE_ID_TSI721
- PCI_DEVICE_ID_TTI_HPT302
- PCI_DEVICE_ID_TTI_HPT343
- PCI_DEVICE_ID_TTI_HPT366
- PCI_DEVICE_ID_TTI_HPT371
- PCI_DEVICE_ID_TTI_HPT372
- PCI_DEVICE_ID_TTI_HPT372N
- PCI_DEVICE_ID_TTI_HPT374
- PCI_DEVICE_ID_TTTECH_MC322
- PCI_DEVICE_ID_TUNDRA_CA91C142
- PCI_DEVICE_ID_TUNDRA_TSI148
- PCI_DEVICE_ID_UMC_UM8673F
- PCI_DEVICE_ID_UMC_UM8886A
- PCI_DEVICE_ID_UMC_UM8886BF
- PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR
- PCI_DEVICE_ID_UPCI_RM3_4PORT
- PCI_DEVICE_ID_UPCI_RM3_8PORT
- PCI_DEVICE_ID_URP16INTF
- PCI_DEVICE_ID_URP32INTF
- PCI_DEVICE_ID_URP8INTF
- PCI_DEVICE_ID_URP8OCTA
- PCI_DEVICE_ID_USR_6692
- PCI_DEVICE_ID_V3_SEMI_V370PDC
- PCI_DEVICE_ID_V3_V351
- PCI_DEVICE_ID_V3_V960
- PCI_DEVICE_ID_VERDE
- PCI_DEVICE_ID_VIA_3238_0
- PCI_DEVICE_ID_VIA_3269_0
- PCI_DEVICE_ID_VIA_3296_0
- PCI_DEVICE_ID_VIA_612X
- PCI_DEVICE_ID_VIA_6410
- PCI_DEVICE_ID_VIA_6415
- PCI_DEVICE_ID_VIA_8231
- PCI_DEVICE_ID_VIA_8231_4
- PCI_DEVICE_ID_VIA_8233A
- PCI_DEVICE_ID_VIA_8233C_0
- PCI_DEVICE_ID_VIA_8233_0
- PCI_DEVICE_ID_VIA_8233_5
- PCI_DEVICE_ID_VIA_8235
- PCI_DEVICE_ID_VIA_8235_USB_2
- PCI_DEVICE_ID_VIA_8237
- PCI_DEVICE_ID_VIA_8237A
- PCI_DEVICE_ID_VIA_8237S
- PCI_DEVICE_ID_VIA_8237_SATA
- PCI_DEVICE_ID_VIA_8251
- PCI_DEVICE_ID_VIA_8261
- PCI_DEVICE_ID_VIA_82C561
- PCI_DEVICE_ID_VIA_82C576
- PCI_DEVICE_ID_VIA_82C576_1
- PCI_DEVICE_ID_VIA_82C586_0
- PCI_DEVICE_ID_VIA_82C586_1
- PCI_DEVICE_ID_VIA_82C586_2
- PCI_DEVICE_ID_VIA_82C586_3
- PCI_DEVICE_ID_VIA_82C596
- PCI_DEVICE_ID_VIA_82C596B_3
- PCI_DEVICE_ID_VIA_82C596_3
- PCI_DEVICE_ID_VIA_82C597_0
- PCI_DEVICE_ID_VIA_82C598_0
- PCI_DEVICE_ID_VIA_82C598_1
- PCI_DEVICE_ID_VIA_82C686
- PCI_DEVICE_ID_VIA_82C686_4
- PCI_DEVICE_ID_VIA_82C686_5
- PCI_DEVICE_ID_VIA_82C691_0
- PCI_DEVICE_ID_VIA_8361
- PCI_DEVICE_ID_VIA_8363_0
- PCI_DEVICE_ID_VIA_8365_1
- PCI_DEVICE_ID_VIA_8367_0
- PCI_DEVICE_ID_VIA_8371_0
- PCI_DEVICE_ID_VIA_8371_1
- PCI_DEVICE_ID_VIA_8377_0
- PCI_DEVICE_ID_VIA_8378_0
- PCI_DEVICE_ID_VIA_8380_0
- PCI_DEVICE_ID_VIA_8385_0
- PCI_DEVICE_ID_VIA_838X_1
- PCI_DEVICE_ID_VIA_83_87XX_1
- PCI_DEVICE_ID_VIA_8501_0
- PCI_DEVICE_ID_VIA_8601_0
- PCI_DEVICE_ID_VIA_8605_0
- PCI_DEVICE_ID_VIA_8622
- PCI_DEVICE_ID_VIA_862X_0
- PCI_DEVICE_ID_VIA_8633_0
- PCI_DEVICE_ID_VIA_8653_0
- PCI_DEVICE_ID_VIA_8703_51_0
- PCI_DEVICE_ID_VIA_8753_0
- PCI_DEVICE_ID_VIA_8754C_0
- PCI_DEVICE_ID_VIA_8763_0
- PCI_DEVICE_ID_VIA_8783_0
- PCI_DEVICE_ID_VIA_9530
- PCI_DEVICE_ID_VIA_95D0
- PCI_DEVICE_ID_VIA_ANON
- PCI_DEVICE_ID_VIA_CX700
- PCI_DEVICE_ID_VIA_CX700_IDE
- PCI_DEVICE_ID_VIA_K8T800PRO_0
- PCI_DEVICE_ID_VIA_P4M800CE
- PCI_DEVICE_ID_VIA_P4M890
- PCI_DEVICE_ID_VIA_PT880
- PCI_DEVICE_ID_VIA_PT880ULTRA
- PCI_DEVICE_ID_VIA_PX8X0_0
- PCI_DEVICE_ID_VIA_SATA_EIDE
- PCI_DEVICE_ID_VIA_VT3324
- PCI_DEVICE_ID_VIA_VT3336
- PCI_DEVICE_ID_VIA_VT3351
- PCI_DEVICE_ID_VIA_VT3364
- PCI_DEVICE_ID_VIA_VT630X
- PCI_DEVICE_ID_VIA_VT6315
- PCI_DEVICE_ID_VIA_VX800
- PCI_DEVICE_ID_VIA_VX855
- PCI_DEVICE_ID_VIA_VX855_IDE
- PCI_DEVICE_ID_VIA_VX900
- PCI_DEVICE_ID_VIA_XM266
- PCI_DEVICE_ID_VIA_XN266
- PCI_DEVICE_ID_VIPER
- PCI_DEVICE_ID_VITESSE_VSC7174
- PCI_DEVICE_ID_VLSI_82C147
- PCI_DEVICE_ID_VLSI_82C532
- PCI_DEVICE_ID_VLSI_82C534
- PCI_DEVICE_ID_VLSI_82C535
- PCI_DEVICE_ID_VLSI_82C541
- PCI_DEVICE_ID_VLSI_82C543
- PCI_DEVICE_ID_VLSI_82C592
- PCI_DEVICE_ID_VLSI_82C593
- PCI_DEVICE_ID_VLSI_82C594
- PCI_DEVICE_ID_VLSI_82C597
- PCI_DEVICE_ID_VLSI_VAS96011
- PCI_DEVICE_ID_VLV_PMC
- PCI_DEVICE_ID_VMWARE_PVRDMA
- PCI_DEVICE_ID_VMWARE_PVSCSI
- PCI_DEVICE_ID_VMWARE_VMCI
- PCI_DEVICE_ID_VMWARE_VMXNET3
- PCI_DEVICE_ID_VORTEX_GDT6000B
- PCI_DEVICE_ID_VORTEX_GDT60x0
- PCI_DEVICE_ID_VORTEX_GDT6530
- PCI_DEVICE_ID_VORTEX_GDT6535
- PCI_DEVICE_ID_VORTEX_GDT6537
- PCI_DEVICE_ID_VORTEX_GDT6537RD
- PCI_DEVICE_ID_VORTEX_GDT6537RP
- PCI_DEVICE_ID_VORTEX_GDT6550
- PCI_DEVICE_ID_VORTEX_GDT6555
- PCI_DEVICE_ID_VORTEX_GDT6557
- PCI_DEVICE_ID_VORTEX_GDT6557RD
- PCI_DEVICE_ID_VORTEX_GDT6557RP
- PCI_DEVICE_ID_VORTEX_GDT6x10
- PCI_DEVICE_ID_VORTEX_GDT6x11RD
- PCI_DEVICE_ID_VORTEX_GDT6x11RP
- PCI_DEVICE_ID_VORTEX_GDT6x15
- PCI_DEVICE_ID_VORTEX_GDT6x17
- PCI_DEVICE_ID_VORTEX_GDT6x17RD
- PCI_DEVICE_ID_VORTEX_GDT6x17RP
- PCI_DEVICE_ID_VORTEX_GDT6x18RD
- PCI_DEVICE_ID_VORTEX_GDT6x19RD
- PCI_DEVICE_ID_VORTEX_GDT6x20
- PCI_DEVICE_ID_VORTEX_GDT6x21RD
- PCI_DEVICE_ID_VORTEX_GDT6x21RP
- PCI_DEVICE_ID_VORTEX_GDT6x25
- PCI_DEVICE_ID_VORTEX_GDT6x27
- PCI_DEVICE_ID_VORTEX_GDT6x27RD
- PCI_DEVICE_ID_VORTEX_GDT6x27RP
- PCI_DEVICE_ID_VORTEX_GDT6x28RD
- PCI_DEVICE_ID_VORTEX_GDT6x29RD
- PCI_DEVICE_ID_VORTEX_GDT6x38RD
- PCI_DEVICE_ID_VORTEX_GDT6x58RD
- PCI_DEVICE_ID_VORTEX_GDT7x18RN
- PCI_DEVICE_ID_VORTEX_GDT7x19RN
- PCI_DEVICE_ID_VORTEX_GDT7x28RN
- PCI_DEVICE_ID_VORTEX_GDT7x29RN
- PCI_DEVICE_ID_VORTEX_GDT7x38RN
- PCI_DEVICE_ID_VORTEX_GDT7x58RN
- PCI_DEVICE_ID_VORTEX_GDTMAXRP
- PCI_DEVICE_ID_VORTEX_GDTNEWRX
- PCI_DEVICE_ID_VORTEX_GDTNEWRX2
- PCI_DEVICE_ID_VT1724
- PCI_DEVICE_ID_VTIMR
- PCI_DEVICE_ID_WATCHDOG_PCIPCWD
- PCI_DEVICE_ID_WCH_CH352_2S
- PCI_DEVICE_ID_WCH_CH353_1S1P
- PCI_DEVICE_ID_WCH_CH353_2S1P
- PCI_DEVICE_ID_WCH_CH353_2S1PF
- PCI_DEVICE_ID_WCH_CH353_4S
- PCI_DEVICE_ID_WCH_CH355_4S
- PCI_DEVICE_ID_WD_90C
- PCI_DEVICE_ID_WEITEK_P9000
- PCI_DEVICE_ID_WEITEK_P9100
- PCI_DEVICE_ID_WINBOND2_6692
- PCI_DEVICE_ID_WINBOND2_89C940F
- PCI_DEVICE_ID_WINBOND_82C105
- PCI_DEVICE_ID_WINBOND_83C553
- PCI_DEVICE_ID_WORKBIT_DUALEDGE
- PCI_DEVICE_ID_WORKBIT_STANDARD
- PCI_DEVICE_ID_XEN_PLATFORM
- PCI_DEVICE_ID_XGI_20
- PCI_DEVICE_ID_XGI_40
- PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
- PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI
- PCI_DEVICE_ID_XILLYBUS
- PCI_DEVICE_ID_XIRCOM_RBM56G
- PCI_DEVICE_ID_XIRCOM_X3201_MDM
- PCI_DEVICE_ID_XLP9XX_MMC
- PCI_DEVICE_ID_XLP9XX_SATA
- PCI_DEVICE_ID_XLP9XX_XHCI
- PCI_DEVICE_ID_YAMAHA_724
- PCI_DEVICE_ID_YAMAHA_724F
- PCI_DEVICE_ID_YAMAHA_740
- PCI_DEVICE_ID_YAMAHA_740C
- PCI_DEVICE_ID_YAMAHA_744
- PCI_DEVICE_ID_YAMAHA_754
- PCI_DEVICE_ID_ZEITNET_1221
- PCI_DEVICE_ID_ZEITNET_1225
- PCI_DEVICE_ID_ZEPHYR
- PCI_DEVICE_ID_ZEPHYR_DCSP
- PCI_DEVICE_ID_ZEPHYR_SCSP
- PCI_DEVICE_ID_ZIATECH_5550_HC
- PCI_DEVICE_ID_ZIP_PF
- PCI_DEVICE_ID_ZIP_VF
- PCI_DEVICE_ID_ZMID
- PCI_DEVICE_ID_ZOLTRIX_2BD0
- PCI_DEVICE_ID_ZORAN_36057
- PCI_DEVICE_ID_ZORAN_36120
- PCI_DEVICE_ID_ZSMB
- PCI_DEVICE_MODE
- PCI_DEVICE_NEO_2DB9PRI_PCI_NAME
- PCI_DEVICE_NEO_2DB9_PCI_NAME
- PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME
- PCI_DEVICE_NEO_2RJ45_PCI_NAME
- PCI_DEVICE_NFP6000VF
- PCI_DEVICE_SUB
- PCI_DEVID
- PCI_DEVID_OCTEONTX2_CGX
- PCI_DEVID_OCTEONTX2_LBK
- PCI_DEVID_OCTEONTX2_RVU_AF
- PCI_DEV_ADDED
- PCI_DEV_CTRL_REG
- PCI_DEV_FLAGS_ACS_ENABLED_QUIRK
- PCI_DEV_FLAGS_ASSIGNED
- PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT
- PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
- PCI_DEV_FLAGS_NO_BUS_RESET
- PCI_DEV_FLAGS_NO_D3
- PCI_DEV_FLAGS_NO_FLR_RESET
- PCI_DEV_FLAGS_NO_PM_RESET
- PCI_DEV_FLAGS_NO_RELAXED_ORDERING
- PCI_DEV_FLAGS_VPD_REF_F0
- PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS
- PCI_DEV_FN_HOST_DEVICE
- PCI_DEV_FN_OTG
- PCI_DEV_ID_EFA_VF
- PCI_DEV_ID_ENA_LLQ_PF
- PCI_DEV_ID_ENA_LLQ_VF
- PCI_DEV_ID_ENA_PF
- PCI_DEV_ID_ENA_VF
- PCI_DEV_ID_GVNIC
- PCI_DEV_REG1
- PCI_DEV_REG2
- PCI_DEV_REG3
- PCI_DEV_REG4
- PCI_DEV_REG5
- PCI_DEV_SEL
- PCI_DEV_STATUS
- PCI_DEV_TMOUT
- PCI_DIAGNOSTIC_0
- PCI_DIAGNOSTIC_1
- PCI_DIO_MAX_DIO_SUBDEVG
- PCI_DIO_MAX_DI_SUBDEVS
- PCI_DIO_MAX_DO_SUBDEVS
- PCI_DISABLE_MWI
- PCI_DLF_CAP
- PCI_DLF_EXCHANGE_ENABLE
- PCI_DLL_BYPASS
- PCI_DLL_TAP_SEL_MASK
- PCI_DM9009_ID
- PCI_DM9100_ID
- PCI_DM9102_ID
- PCI_DM9132_ID
- PCI_DMA8C_MBS
- PCI_DMA8C_MBS_BIT
- PCI_DMA8C_OUR
- PCI_DMA9C_MBS
- PCI_DMA9C_MBS_BIT
- PCI_DMACTRL
- PCI_DMACTRL_OFFSET
- PCI_DMAD_DEVCMD_IOR
- PCI_DMAD_DEVCMD_IOW
- PCI_DMAD_DEVCMD_MR
- PCI_DMAD_DEVCMD_MRL
- PCI_DMAD_DEVCMD_MRM
- PCI_DMAD_DEVCMD_MW
- PCI_DMAD_DEVCMD_MWI
- PCI_DMAD_PT
- PCI_DMAD_PT_BIT
- PCI_DMAD_SB
- PCI_DMA_BIDIRECTIONAL
- PCI_DMA_DDP
- PCI_DMA_FROMDEVICE
- PCI_DMA_NONE
- PCI_DMA_THRESHOLD
- PCI_DMA_TODEVICE
- PCI_DN
- PCI_DN_FLAG_DEAD
- PCI_DN_FLAG_IOV_VF
- PCI_DOORBELL_INT_ENABLE_BIT
- PCI_DPA_BASE_SIZEOF
- PCI_DPA_CAP
- PCI_DPA_CAP_SUBSTATE_MASK
- PCI_DPT_DEVICE_ID
- PCI_DPT_RAPTOR_DEVICE_ID
- PCI_DPT_VENDOR_ID
- PCI_DRAM_OFFSET
- PCI_DRIVER
- PCI_DRIVER_NAME
- PCI_DUMP_SIZE
- PCI_DVMA_CONTROL
- PCI_DVMA_CONTROL_INACTIVITY_ACK
- PCI_DVMA_CONTROL_INACTIVITY_REQ
- PCI_DVMA_CONTROL_IOTLB_DISABLE
- PCI_DVMA_CONTROL_IOTLB_ENABLE
- PCI_EA_BASE
- PCI_EA_BEI
- PCI_EA_BEI_BAR0
- PCI_EA_BEI_BAR5
- PCI_EA_BEI_BRIDGE
- PCI_EA_BEI_ENI
- PCI_EA_BEI_RESERVED
- PCI_EA_BEI_ROM
- PCI_EA_BEI_VF_BAR0
- PCI_EA_BEI_VF_BAR5
- PCI_EA_ENABLE
- PCI_EA_ES
- PCI_EA_FIELD_MASK
- PCI_EA_FIRST_ENT
- PCI_EA_FIRST_ENT_BRIDGE
- PCI_EA_IS_64
- PCI_EA_MAX_OFFSET
- PCI_EA_NUM_ENT
- PCI_EA_NUM_ENT_MASK
- PCI_EA_PP
- PCI_EA_P_BRIDGE_IO
- PCI_EA_P_BRIDGE_MEM
- PCI_EA_P_BRIDGE_MEM_PREFETCH
- PCI_EA_P_IO
- PCI_EA_P_IO_RESERVED
- PCI_EA_P_MEM
- PCI_EA_P_MEM_PREFETCH
- PCI_EA_P_MEM_RESERVED
- PCI_EA_P_UNAVAILABLE
- PCI_EA_P_VF_MEM
- PCI_EA_P_VF_MEM_PREFETCH
- PCI_EA_SEC_BUS_MASK
- PCI_EA_SP
- PCI_EA_SUB_BUS_MASK
- PCI_EA_SUB_BUS_SHIFT
- PCI_EA_WRITABLE
- PCI_EDE_ADDR_PERR
- PCI_EDE_IRMSV
- PCI_EDE_MST_ABRT
- PCI_EDE_MST_PERR
- PCI_EDE_MULTI_ERR
- PCI_EDE_ORMSV
- PCI_EDE_OWMSV
- PCI_EDE_PERR_MASK
- PCI_EDE_RCVD_SERR
- PCI_EDE_SCM
- PCI_EDE_TGT_ABRT
- PCI_EDE_TGT_PERR
- PCI_EDE_TOE
- PCI_EEPROM_ERASE_OPCODE
- PCI_EEPROM_EWDS_OPCODE
- PCI_EEPROM_EWEN_OPCODE
- PCI_EEPROM_READ_OPCODE
- PCI_EEPROM_WIDTH_93C46
- PCI_EEPROM_WIDTH_93C56
- PCI_EEPROM_WIDTH_93C66
- PCI_EEPROM_WIDTH_93C86
- PCI_EEPROM_WIDTH_OPCODE
- PCI_EEPROM_WRITE_OPCODE
- PCI_EHCI_FLADJ_REG
- PCI_EHCI_LEGSMIEN_REG
- PCI_EHCI_LEGSMISTS_REG
- PCI_EJECT
- PCI_EJECTION_COMPLETE
- PCI_ENABLE
- PCI_ENABLE_PROC_DOMAINS
- PCI_ENA_GPHY_LNK
- PCI_ENA_L1_EVENT
- PCI_ENA_MASTER
- PCI_ENA_MEMIO
- PCI_ENA_REGIO
- PCI_ENDIAN_FLAG
- PCI_ENDPOINT_TEST_CHECKSUM
- PCI_ENDPOINT_TEST_COMMAND
- PCI_ENDPOINT_TEST_IRQ_NUMBER
- PCI_ENDPOINT_TEST_IRQ_TYPE
- PCI_ENDPOINT_TEST_LOWER_DST_ADDR
- PCI_ENDPOINT_TEST_LOWER_SRC_ADDR
- PCI_ENDPOINT_TEST_MAGIC
- PCI_ENDPOINT_TEST_SIZE
- PCI_ENDPOINT_TEST_STATUS
- PCI_ENDPOINT_TEST_UPPER_DST_ADDR
- PCI_ENDPOINT_TEST_UPPER_SRC_ADDR
- PCI_EN_DUMMY_RD
- PCI_EN_FIFO_WR
- PCI_EN_INIT_WR
- PCI_EPC_IRQ_LEGACY
- PCI_EPC_IRQ_MSI
- PCI_EPC_IRQ_MSIX
- PCI_EPC_IRQ_UNKNOWN
- PCI_EPF_HEADER_R
- PCI_EPF_HEADER_W_u16
- PCI_EPF_HEADER_W_u32
- PCI_EPF_HEADER_W_u8
- PCI_EPF_MODULE_PREFIX
- PCI_EPF_NAME_SIZE
- PCI_ERR
- PCI_ERRBITS
- PCI_ERROR_INTERRUPTS
- PCI_ERR_ANON_BUF_RD
- PCI_ERR_BADACK
- PCI_ERR_BIM_DMA_READ
- PCI_ERR_BIM_DMA_TIMEOUT
- PCI_ERR_BIM_DMA_WRITE
- PCI_ERR_CAP
- PCI_ERR_CAP_ECRC_CHKC
- PCI_ERR_CAP_ECRC_CHKE
- PCI_ERR_CAP_ECRC_GENC
- PCI_ERR_CAP_ECRC_GENE
- PCI_ERR_CAP_FEP
- PCI_ERR_COR_ADV_NFAT
- PCI_ERR_COR_BAD_DLLP
- PCI_ERR_COR_BAD_TLP
- PCI_ERR_COR_INTERNAL
- PCI_ERR_COR_LOG_OVER
- PCI_ERR_COR_MASK
- PCI_ERR_COR_RCVR
- PCI_ERR_COR_REP_ROLL
- PCI_ERR_COR_REP_TIMER
- PCI_ERR_COR_STATUS
- PCI_ERR_DTRTO
- PCI_ERR_HEADER_LOG
- PCI_ERR_OTHER
- PCI_ERR_ROOT_AER_IRQ
- PCI_ERR_ROOT_CMD_COR_EN
- PCI_ERR_ROOT_CMD_FATAL_EN
- PCI_ERR_ROOT_CMD_NONFATAL_EN
- PCI_ERR_ROOT_COMMAND
- PCI_ERR_ROOT_COR_RCV
- PCI_ERR_ROOT_ERR_SRC
- PCI_ERR_ROOT_FATAL_RCV
- PCI_ERR_ROOT_FIRST_FATAL
- PCI_ERR_ROOT_MULTI_COR_RCV
- PCI_ERR_ROOT_MULTI_UNCOR_RCV
- PCI_ERR_ROOT_NONFATAL_RCV
- PCI_ERR_ROOT_STATUS
- PCI_ERR_ROOT_UNCOR_RCV
- PCI_ERR_UNCOR_MASK
- PCI_ERR_UNCOR_SEVER
- PCI_ERR_UNCOR_STATUS
- PCI_ERR_UNC_ACSV
- PCI_ERR_UNC_ATOMEG
- PCI_ERR_UNC_COMP_ABORT
- PCI_ERR_UNC_COMP_TIME
- PCI_ERR_UNC_DLP
- PCI_ERR_UNC_ECRC
- PCI_ERR_UNC_FCP
- PCI_ERR_UNC_INTN
- PCI_ERR_UNC_MALF_TLP
- PCI_ERR_UNC_MCBTLP
- PCI_ERR_UNC_POISON_TLP
- PCI_ERR_UNC_RX_OVER
- PCI_ERR_UNC_SURPDN
- PCI_ERR_UNC_TLPPRE
- PCI_ERR_UNC_UND
- PCI_ERR_UNC_UNSUP
- PCI_ERR_UNC_UNX_COMP
- PCI_ERS_RESULT_CAN_RECOVER
- PCI_ERS_RESULT_DISCONNECT
- PCI_ERS_RESULT_NEED_RESET
- PCI_ERS_RESULT_NONE
- PCI_ERS_RESULT_NO_AER_DRIVER
- PCI_ERS_RESULT_RECOVERED
- PCI_EXPANSION_ROM_BAR
- PCI_EXPRESS_ROOT_HID_STRING
- PCI_EXP_AER_FLAGS
- PCI_EXP_COMP_TIMEOUT_65_TO_210_MS
- PCI_EXP_DEVCAP
- PCI_EXP_DEVCAP2
- PCI_EXP_DEVCAP2_ARI
- PCI_EXP_DEVCAP2_ATOMIC_COMP128
- PCI_EXP_DEVCAP2_ATOMIC_COMP32
- PCI_EXP_DEVCAP2_ATOMIC_COMP64
- PCI_EXP_DEVCAP2_ATOMIC_ROUTE
- PCI_EXP_DEVCAP2_COMP_TMOUT_DIS
- PCI_EXP_DEVCAP2_EE_PREFIX
- PCI_EXP_DEVCAP2_LTR
- PCI_EXP_DEVCAP2_OBFF_MASK
- PCI_EXP_DEVCAP2_OBFF_MSG
- PCI_EXP_DEVCAP2_OBFF_WAKE
- PCI_EXP_DEVCAP_ATN_BUT
- PCI_EXP_DEVCAP_ATN_IND
- PCI_EXP_DEVCAP_EXT_TAG
- PCI_EXP_DEVCAP_FLR
- PCI_EXP_DEVCAP_L0S
- PCI_EXP_DEVCAP_L1
- PCI_EXP_DEVCAP_PAYLOAD
- PCI_EXP_DEVCAP_PHANTOM
- PCI_EXP_DEVCAP_PWR_IND
- PCI_EXP_DEVCAP_PWR_SCL
- PCI_EXP_DEVCAP_PWR_VAL
- PCI_EXP_DEVCAP_RBER
- PCI_EXP_DEVCTL
- PCI_EXP_DEVCTL2
- PCI_EXP_DEVCTL2_ARI
- PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
- PCI_EXP_DEVCTL2_ATOMIC_REQ
- PCI_EXP_DEVCTL2_COMP_TIMEOUT
- PCI_EXP_DEVCTL2_COMP_TMOUT_DIS
- PCI_EXP_DEVCTL2_IDO_CMP_EN
- PCI_EXP_DEVCTL2_IDO_REQ_EN
- PCI_EXP_DEVCTL2_LTR_EN
- PCI_EXP_DEVCTL2_OBFF_MSGA_EN
- PCI_EXP_DEVCTL2_OBFF_MSGB_EN
- PCI_EXP_DEVCTL2_OBFF_WAKE_EN
- PCI_EXP_DEVCTL_AUX_PME
- PCI_EXP_DEVCTL_BCR_FLR
- PCI_EXP_DEVCTL_CERE
- PCI_EXP_DEVCTL_EXT_TAG
- PCI_EXP_DEVCTL_FERE
- PCI_EXP_DEVCTL_NFERE
- PCI_EXP_DEVCTL_NOSNOOP_EN
- PCI_EXP_DEVCTL_PAYLOAD
- PCI_EXP_DEVCTL_PHANTOM
- PCI_EXP_DEVCTL_READRQ
- PCI_EXP_DEVCTL_READRQ_1024B
- PCI_EXP_DEVCTL_READRQ_128B
- PCI_EXP_DEVCTL_READRQ_2048B
- PCI_EXP_DEVCTL_READRQ_256B
- PCI_EXP_DEVCTL_READRQ_4096B
- PCI_EXP_DEVCTL_READRQ_512B
- PCI_EXP_DEVCTL_RELAX_EN
- PCI_EXP_DEVCTL_URRE
- PCI_EXP_DEVSTA
- PCI_EXP_DEVSTA2
- PCI_EXP_DEVSTA_AUXPD
- PCI_EXP_DEVSTA_CED
- PCI_EXP_DEVSTA_FED
- PCI_EXP_DEVSTA_NFED
- PCI_EXP_DEVSTA_TRPND
- PCI_EXP_DEVSTA_URD
- PCI_EXP_DPC_CAP
- PCI_EXP_DPC_CAP_DL_ACTIVE
- PCI_EXP_DPC_CAP_POISONED_TLP
- PCI_EXP_DPC_CAP_RP_EXT
- PCI_EXP_DPC_CAP_SW_TRIGGER
- PCI_EXP_DPC_CTL
- PCI_EXP_DPC_CTL_EN_FATAL
- PCI_EXP_DPC_CTL_EN_NONFATAL
- PCI_EXP_DPC_CTL_INT_EN
- PCI_EXP_DPC_IRQ
- PCI_EXP_DPC_RP_BUSY
- PCI_EXP_DPC_RP_PIO_EXCEPTION
- PCI_EXP_DPC_RP_PIO_HEADER_LOG
- PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG
- PCI_EXP_DPC_RP_PIO_LOG_SIZE
- PCI_EXP_DPC_RP_PIO_MASK
- PCI_EXP_DPC_RP_PIO_SEVERITY
- PCI_EXP_DPC_RP_PIO_STATUS
- PCI_EXP_DPC_RP_PIO_SYSERROR
- PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG
- PCI_EXP_DPC_SOURCE_ID
- PCI_EXP_DPC_STATUS
- PCI_EXP_DPC_STATUS_INTERRUPT
- PCI_EXP_DPC_STATUS_TRIGGER
- PCI_EXP_DPC_STATUS_TRIGGER_RSN
- PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT
- PCI_EXP_FLAGS
- PCI_EXP_FLAGS_IRQ
- PCI_EXP_FLAGS_SLOT
- PCI_EXP_FLAGS_TYPE
- PCI_EXP_FLAGS_VERS
- PCI_EXP_LNKCAP
- PCI_EXP_LNKCAP2
- PCI_EXP_LNKCAP2_CROSSLINK
- PCI_EXP_LNKCAP2_SLS_16_0GB
- PCI_EXP_LNKCAP2_SLS_2_5GB
- PCI_EXP_LNKCAP2_SLS_32_0GB
- PCI_EXP_LNKCAP2_SLS_5_0GB
- PCI_EXP_LNKCAP2_SLS_8_0GB
- PCI_EXP_LNKCAP_ASPMS
- PCI_EXP_LNKCAP_CLKPM
- PCI_EXP_LNKCAP_DLLLARC
- PCI_EXP_LNKCAP_L0SEL
- PCI_EXP_LNKCAP_L1EL
- PCI_EXP_LNKCAP_LBNC
- PCI_EXP_LNKCAP_MLW
- PCI_EXP_LNKCAP_PN
- PCI_EXP_LNKCAP_SDERC
- PCI_EXP_LNKCAP_SLS
- PCI_EXP_LNKCAP_SLS_16_0GB
- PCI_EXP_LNKCAP_SLS_2_5GB
- PCI_EXP_LNKCAP_SLS_32_0GB
- PCI_EXP_LNKCAP_SLS_5_0GB
- PCI_EXP_LNKCAP_SLS_8_0GB
- PCI_EXP_LNKCTL
- PCI_EXP_LNKCTL2
- PCI_EXP_LNKCTL2_TLS
- PCI_EXP_LNKCTL2_TLS_16_0GT
- PCI_EXP_LNKCTL2_TLS_2_5GT
- PCI_EXP_LNKCTL2_TLS_32_0GT
- PCI_EXP_LNKCTL2_TLS_5_0GT
- PCI_EXP_LNKCTL2_TLS_8_0GT
- PCI_EXP_LNKCTL_ASPMC
- PCI_EXP_LNKCTL_ASPM_L0S
- PCI_EXP_LNKCTL_ASPM_L1
- PCI_EXP_LNKCTL_CCC
- PCI_EXP_LNKCTL_CLKREQ_EN
- PCI_EXP_LNKCTL_ES
- PCI_EXP_LNKCTL_HAWD
- PCI_EXP_LNKCTL_LABIE
- PCI_EXP_LNKCTL_LBMIE
- PCI_EXP_LNKCTL_LD
- PCI_EXP_LNKCTL_RCB
- PCI_EXP_LNKCTL_RL
- PCI_EXP_LNKSTA
- PCI_EXP_LNKSTA2
- PCI_EXP_LNKSTA_CLS
- PCI_EXP_LNKSTA_CLS_16_0GB
- PCI_EXP_LNKSTA_CLS_2_5GB
- PCI_EXP_LNKSTA_CLS_32_0GB
- PCI_EXP_LNKSTA_CLS_5_0GB
- PCI_EXP_LNKSTA_CLS_8_0GB
- PCI_EXP_LNKSTA_DLLLA
- PCI_EXP_LNKSTA_LABS
- PCI_EXP_LNKSTA_LBMS
- PCI_EXP_LNKSTA_LT
- PCI_EXP_LNKSTA_NLW
- PCI_EXP_LNKSTA_NLW_SHIFT
- PCI_EXP_LNKSTA_NLW_X1
- PCI_EXP_LNKSTA_NLW_X2
- PCI_EXP_LNKSTA_NLW_X4
- PCI_EXP_LNKSTA_NLW_X8
- PCI_EXP_LNKSTA_SLC
- PCI_EXP_RTCAP
- PCI_EXP_RTCAP_CRSVIS
- PCI_EXP_RTCTL
- PCI_EXP_RTCTL_CRSSVE
- PCI_EXP_RTCTL_PMEIE
- PCI_EXP_RTCTL_SECEE
- PCI_EXP_RTCTL_SEFEE
- PCI_EXP_RTCTL_SENFEE
- PCI_EXP_RTSTA
- PCI_EXP_RTSTA_PENDING
- PCI_EXP_RTSTA_PME
- PCI_EXP_SAVE_REGS
- PCI_EXP_SLTCAP
- PCI_EXP_SLTCAP2
- PCI_EXP_SLTCAP_ABP
- PCI_EXP_SLTCAP_AIP
- PCI_EXP_SLTCAP_EIP
- PCI_EXP_SLTCAP_HPC
- PCI_EXP_SLTCAP_HPS
- PCI_EXP_SLTCAP_MRLSP
- PCI_EXP_SLTCAP_NCCS
- PCI_EXP_SLTCAP_PCP
- PCI_EXP_SLTCAP_PIP
- PCI_EXP_SLTCAP_PSN
- PCI_EXP_SLTCAP_SPLS
- PCI_EXP_SLTCAP_SPLV
- PCI_EXP_SLTCTL
- PCI_EXP_SLTCTL2
- PCI_EXP_SLTCTL_ABPE
- PCI_EXP_SLTCTL_AIC
- PCI_EXP_SLTCTL_ATTN_IND_BLINK
- PCI_EXP_SLTCTL_ATTN_IND_OFF
- PCI_EXP_SLTCTL_ATTN_IND_ON
- PCI_EXP_SLTCTL_ATTN_IND_SHIFT
- PCI_EXP_SLTCTL_CCIE
- PCI_EXP_SLTCTL_DLLSCE
- PCI_EXP_SLTCTL_EIC
- PCI_EXP_SLTCTL_HPIE
- PCI_EXP_SLTCTL_MRLSCE
- PCI_EXP_SLTCTL_PCC
- PCI_EXP_SLTCTL_PDCE
- PCI_EXP_SLTCTL_PFDE
- PCI_EXP_SLTCTL_PIC
- PCI_EXP_SLTCTL_PWR_IND_BLINK
- PCI_EXP_SLTCTL_PWR_IND_OFF
- PCI_EXP_SLTCTL_PWR_IND_ON
- PCI_EXP_SLTCTL_PWR_OFF
- PCI_EXP_SLTCTL_PWR_ON
- PCI_EXP_SLTSTA
- PCI_EXP_SLTSTA2
- PCI_EXP_SLTSTA_ABP
- PCI_EXP_SLTSTA_CC
- PCI_EXP_SLTSTA_DLLSC
- PCI_EXP_SLTSTA_EIS
- PCI_EXP_SLTSTA_MRLSC
- PCI_EXP_SLTSTA_MRLSS
- PCI_EXP_SLTSTA_PDC
- PCI_EXP_SLTSTA_PDS
- PCI_EXP_SLTSTA_PFD
- PCI_EXP_TYPE_DOWNSTREAM
- PCI_EXP_TYPE_ENDPOINT
- PCI_EXP_TYPE_LEG_END
- PCI_EXP_TYPE_PCIE_BRIDGE
- PCI_EXP_TYPE_PCI_BRIDGE
- PCI_EXP_TYPE_RC_EC
- PCI_EXP_TYPE_RC_END
- PCI_EXP_TYPE_ROOT_PORT
- PCI_EXP_TYPE_UPSTREAM
- PCI_EXTERNAL_ARBITER
- PCI_EXT_AsicRev
- PCI_EXT_CAP_ARI_SIZEOF
- PCI_EXT_CAP_ATS_SIZEOF
- PCI_EXT_CAP_DSN_SIZEOF
- PCI_EXT_CAP_ID
- PCI_EXT_CAP_ID_ACS
- PCI_EXT_CAP_ID_AMD_XXX
- PCI_EXT_CAP_ID_ARI
- PCI_EXT_CAP_ID_ATS
- PCI_EXT_CAP_ID_CAC
- PCI_EXT_CAP_ID_DLF
- PCI_EXT_CAP_ID_DPA
- PCI_EXT_CAP_ID_DPC
- PCI_EXT_CAP_ID_DSN
- PCI_EXT_CAP_ID_ERR
- PCI_EXT_CAP_ID_L1SS
- PCI_EXT_CAP_ID_LTR
- PCI_EXT_CAP_ID_MAX
- PCI_EXT_CAP_ID_MCAST
- PCI_EXT_CAP_ID_MFVC
- PCI_EXT_CAP_ID_MRIOV
- PCI_EXT_CAP_ID_PASID
- PCI_EXT_CAP_ID_PL_16GT
- PCI_EXT_CAP_ID_PMUX
- PCI_EXT_CAP_ID_PRI
- PCI_EXT_CAP_ID_PTM
- PCI_EXT_CAP_ID_PWR
- PCI_EXT_CAP_ID_RCEC
- PCI_EXT_CAP_ID_RCILC
- PCI_EXT_CAP_ID_RCLD
- PCI_EXT_CAP_ID_RCRB
- PCI_EXT_CAP_ID_REBAR
- PCI_EXT_CAP_ID_SECPCI
- PCI_EXT_CAP_ID_SRIOV
- PCI_EXT_CAP_ID_TPH
- PCI_EXT_CAP_ID_VC
- PCI_EXT_CAP_ID_VC9
- PCI_EXT_CAP_ID_VNDR
- PCI_EXT_CAP_LTR_SIZEOF
- PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF
- PCI_EXT_CAP_NEXT
- PCI_EXT_CAP_PASID_SIZEOF
- PCI_EXT_CAP_PRI_SIZEOF
- PCI_EXT_CAP_PWR_SIZEOF
- PCI_EXT_CAP_SRIOV_SIZEOF
- PCI_EXT_CAP_VER
- PCI_EXT_CapId
- PCI_EXT_Data00
- PCI_EXT_FM_Base
- PCI_EXT_Game_Base
- PCI_EXT_Legacy_Mask
- PCI_EXT_MPU_Base
- PCI_EXT_NextCapPrt
- PCI_EXT_PATCHS
- PCI_EXT_PMSCR_BSE
- PCI_EXT_PWMC
- PCI_EXT_PWSCR
- PCI_EXT_Reserved3
- PCI_EXT_SB_Base
- PCI_EX_82566_SNOOP_ALL
- PCI_EX_LINK_STATUS
- PCI_EX_LINK_WIDTH_MASK
- PCI_EX_LINK_WIDTH_SHIFT
- PCI_EX_NO_SNOOP_ALL
- PCI_FDC_SWAP_DRIVES
- PCI_FIND_CAP_TTL
- PCI_FIXED_BAR_0_SIZE
- PCI_FIXED_BAR_1_SIZE
- PCI_FIXED_BAR_2_SIZE
- PCI_FIXED_BAR_3_SIZE
- PCI_FIXED_BAR_4_SIZE
- PCI_FIXED_BAR_5_SIZE
- PCI_FIX_ADDR
- PCI_FLUSH_REG
- PCI_FORCE_PEX_L1
- PCI_FSL_BRR1
- PCI_FSL_BRR1_VER
- PCI_FUNC
- PCI_F_EXTEND
- PCI_GART_PAGE
- PCI_GET_ADDR_TOKEN
- PCI_GPIO_CTRL_8PORT
- PCI_GetBusDevHelper
- PCI_HAS_IO_ECS
- PCI_HBA_MAX
- PCI_HC_MAIN_IRQ_CAUSE
- PCI_HC_MAIN_IRQ_MASK
- PCI_HEADER_TYPE
- PCI_HEADER_TYPE_BRIDGE
- PCI_HEADER_TYPE_CARDBUS
- PCI_HEADER_TYPE_MASK
- PCI_HEADER_TYPE_MULTIBRIDGE
- PCI_HEADER_TYPE_MULTIDEVICE
- PCI_HEADER_TYPE_MULTIFUNC
- PCI_HEADER_TYPE_NORMAL
- PCI_HEADER_TYPE_REGISTER
- PCI_HOST
- PCI_HOST_CLK_CONTROL
- PCI_HOST_ENABLE_CMD
- PCI_HOST_MODE
- PCI_HPC_ID
- PCI_HT_CAP_SLAVE_CTRL0
- PCI_HT_CAP_SLAVE_CTRL1
- PCI_HW_INT_OUTPUT
- PCI_I810_MISCC
- PCI_ID
- PCI_IDE_CAST_REG
- PCI_IDE_CFG
- PCI_IDE_CFG_REG
- PCI_IDE_DTC_REG
- PCI_IDE_ETC_REG
- PCI_IDE_INT_REG
- PCI_IDE_PM_REG
- PCI_IDSEL_CS5536
- PCI_IDS_GOYA
- PCI_ID_ALCOR_MICRO
- PCI_ID_AU6601
- PCI_ID_AU6621
- PCI_ID_DID
- PCI_ID_LAST
- PCI_ID_PCIM_DDA06_16
- PCI_ID_PCX1221E
- PCI_ID_PCX1221HR
- PCI_ID_PCX1222E
- PCI_ID_PCX1222HR
- PCI_ID_PCX22E
- PCI_ID_PCX22HR
- PCI_ID_PCX442E
- PCI_ID_PCX442HR
- PCI_ID_PCX822E
- PCI_ID_PCX822HR
- PCI_ID_PCX881E
- PCI_ID_PCX881HR
- PCI_ID_PCX882E
- PCI_ID_PCX882HR
- PCI_ID_PCX924E
- PCI_ID_PCX924E_MIC
- PCI_ID_PCX924HR
- PCI_ID_PCX924HRMIC
- PCI_ID_TABLE_ENTRY
- PCI_ID_VAL1
- PCI_ID_VAL2
- PCI_ID_VAL3
- PCI_ID_VID
- PCI_ID_VX1221E
- PCI_ID_VX1221HR
- PCI_ID_VX1222E
- PCI_ID_VX1222HR
- PCI_ID_VX222E
- PCI_ID_VX222E_MIC
- PCI_ID_VX222HR
- PCI_ID_VX222HRMIC
- PCI_ID_VX442E
- PCI_ID_VX442HR
- PCI_ID_VX822E
- PCI_ID_VX822HR
- PCI_ID_VX881E
- PCI_ID_VX881HR
- PCI_ID_VX882E
- PCI_ID_VX882HR
- PCI_IGNORE
- PCI_IMAP
- PCI_IMPL_H
- PCI_INIT_ENABLE
- PCI_INT
- PCI_INTA
- PCI_INTA_INTERRUPT
- PCI_INTA_INTERRUPT_ENABLE
- PCI_INTA_SLOT
- PCI_INTB
- PCI_INTBRG_CTRL_CLEAR_MASK
- PCI_INTBRG_CTRL_DTSERREN
- PCI_INTBRG_CTRL_DTSTAT
- PCI_INTBRG_CTRL_MARSP
- PCI_INTBRG_CTRL_PEREN
- PCI_INTBRG_CTRL_POLL_MASK
- PCI_INTBRG_CTRL_SERREN
- PCI_INTB_RTL8139
- PCI_INTB_SLOT
- PCI_INTC
- PCI_INTC_PCI1520
- PCI_INTD
- PCI_INTD_RTL8139
- PCI_INTEL_BXT_DSM_GUID
- PCI_INTEL_BXT_FUNC_PMU_PWR
- PCI_INTEL_BXT_STATE_D0
- PCI_INTEL_BXT_STATE_D3
- PCI_INTEN
- PCI_INTEN_ADB
- PCI_INTEN_AHBE
- PCI_INTEN_APDC
- PCI_INTEN_OFFSET
- PCI_INTEN_PADC
- PCI_INTEN_PDB
- PCI_INTEN_PFE
- PCI_INTEN_PPE
- PCI_INTEN_PSE
- PCI_INTERRUPT_CONTROL
- PCI_INTERRUPT_CTRL
- PCI_INTERRUPT_ENABLE
- PCI_INTERRUPT_INTA
- PCI_INTERRUPT_INTB
- PCI_INTERRUPT_INTC
- PCI_INTERRUPT_INTD
- PCI_INTERRUPT_LINE
- PCI_INTERRUPT_PIN
- PCI_INTERRUPT_UNKNOWN
- PCI_INTX_PIN
- PCI_INT_AUDINT
- PCI_INT_AUX_INT
- PCI_INT_AUX_TO
- PCI_INT_BRDG_BERRINT
- PCI_INT_CTRL_AIOP
- PCI_INT_DMA0_HLT
- PCI_INT_DMA0_PCL
- PCI_INT_DMA1_HLT
- PCI_INT_DMA1_PCL
- PCI_INT_DMA2_HLT
- PCI_INT_DMA2_PCL
- PCI_INT_DMA3_HLT
- PCI_INT_DMA3_PCL
- PCI_INT_DMA4_HLT
- PCI_INT_DMA4_PCL
- PCI_INT_DMA_ALL
- PCI_INT_DMA_HLT
- PCI_INT_DMA_PCL
- PCI_INT_DSTDMAINT
- PCI_INT_DST_DMA_BERRINT
- PCI_INT_ENABLE
- PCI_INT_ENABLE_BIT
- PCI_INT_FRC_INT
- PCI_INT_GPIO_INT0
- PCI_INT_GPIO_INT1
- PCI_INT_HSTINT
- PCI_INT_I2CDONE
- PCI_INT_I2CRACK
- PCI_INT_INT_PEND
- PCI_INT_INT_SLV_TO
- PCI_INT_IPB_DMA_BERRINT
- PCI_INT_IR_SMPINT
- PCI_INT_MODE
- PCI_INT_MSK
- PCI_INT_MSTAT
- PCI_INT_MST_DAT_PERR
- PCI_INT_MST_DEV_TO
- PCI_INT_P1394_INT
- PCI_INT_RISC_RD_BERRINT
- PCI_INT_RISC_WR_BERRINT
- PCI_INT_SELECT_HI
- PCI_INT_SELECT_LO
- PCI_INT_SLV_ADR_PERR
- PCI_INT_SLV_DAT_PERR
- PCI_INT_SRCDMAINT
- PCI_INT_SRC_DMA_BERRINT
- PCI_INT_STAT
- PCI_INT_STATUS
- PCI_INT_TM1INT
- PCI_INT_TSINT
- PCI_INT_VIDINT
- PCI_INT_VIPINT
- PCI_INVALIDATE_BLOCK
- PCI_INVALID_CARD
- PCI_IO
- PCI_IO1_END
- PCI_IO1_START
- PCI_IO2_END
- PCI_IO2_START
- PCI_IOBAR_OFFSET
- PCI_IOBASE
- PCI_IOSIZE
- PCI_IOTLB_CAM_INPUT
- PCI_IOTLB_CAM_OUTPUT
- PCI_IOTLB_CONTROL
- PCI_IOTLB_ERROR_ADDRESS
- PCI_IOTLB_RAM_INPUT
- PCI_IOTLB_RAM_OUTPUT
- PCI_IOV_RESOURCES
- PCI_IOV_RESOURCE_END
- PCI_IO_1K_RANGE_MASK
- PCI_IO_ADDR
- PCI_IO_BA
- PCI_IO_BASE
- PCI_IO_BASE_UPPER16
- PCI_IO_EN
- PCI_IO_END
- PCI_IO_IND_TOKEN_MASK
- PCI_IO_IND_TOKEN_SHIFT
- PCI_IO_LIMIT
- PCI_IO_LIMIT_UPPER16
- PCI_IO_MASK
- PCI_IO_PA
- PCI_IO_RANGE_MASK
- PCI_IO_RANGE_TYPE_16
- PCI_IO_RANGE_TYPE_32
- PCI_IO_RANGE_TYPE_MASK
- PCI_IO_RESOURCE_END
- PCI_IO_RESOURCE_START
- PCI_IO_SIZE
- PCI_IO_START
- PCI_IO_VIRT_BASE
- PCI_IRQ
- PCI_IRQTC
- PCI_IRQ_AFFINITY
- PCI_IRQ_ALL_TYPES
- PCI_IRQ_CAUSE
- PCI_IRQ_LEGACY
- PCI_IRQ_MASK
- PCI_IRQ_MSI
- PCI_IRQ_MSIX
- PCI_IRQ_NONE
- PCI_IRQ_VIRTUAL
- PCI_ISA_FIXUP_REG
- PCI_ISC
- PCI_ISIZE
- PCI_ISIZE_128M
- PCI_ISIZE_16M
- PCI_ISIZE_256M
- PCI_ISIZE_32M
- PCI_ISIZE_64M
- PCI_ISR
- PCI_ISR_ADB
- PCI_ISR_AHBE
- PCI_ISR_APDC
- PCI_ISR_OFFSET
- PCI_ISR_PADC
- PCI_ISR_PDB
- PCI_ISR_PFE
- PCI_ISR_PPE
- PCI_ISR_PSE
- PCI_JTAG_DEVID_REG
- PCI_KEY
- PCI_L1SS_CAP
- PCI_L1SS_CAP_ASPM_L1_1
- PCI_L1SS_CAP_ASPM_L1_2
- PCI_L1SS_CAP_CM_RESTORE_TIME
- PCI_L1SS_CAP_L1_PM_SS
- PCI_L1SS_CAP_PCIPM_L1_1
- PCI_L1SS_CAP_PCIPM_L1_2
- PCI_L1SS_CAP_P_PWR_ON_SCALE
- PCI_L1SS_CAP_P_PWR_ON_VALUE
- PCI_L1SS_CTL1
- PCI_L1SS_CTL1_ASPM_L1_1
- PCI_L1SS_CTL1_ASPM_L1_2
- PCI_L1SS_CTL1_CM_RESTORE_TIME
- PCI_L1SS_CTL1_L1SS_MASK
- PCI_L1SS_CTL1_LTR_L12_TH_SCALE
- PCI_L1SS_CTL1_LTR_L12_TH_VALUE
- PCI_L1SS_CTL1_PCIPM_L1_1
- PCI_L1SS_CTL1_PCIPM_L1_2
- PCI_L1SS_CTL2
- PCI_LAT
- PCI_LATENCY_CACHELINE
- PCI_LATENCY_TIMER
- PCI_LBAC_MSI
- PCI_LBAC_MSI_IO
- PCI_LBAC_MSI_MEM
- PCI_LBAC_RT
- PCI_LBAC_RT_NO_PREF
- PCI_LBAC_RT_PREF
- PCI_LBAC_SB
- PCI_LBAC_SIZE
- PCI_LBAC_SIZE_BIT
- PCI_LBAM_MADDR
- PCI_LBAM_MADDR_BIT
- PCI_LBA_BADDR
- PCI_LBA_BADDR_BIT
- PCI_LBA_COUNT
- PCI_LDO_CTRL
- PCI_LEGACY_AUDIO_CTRL
- PCI_LINK_STATUS_REG
- PCI_LOAD_INTERVAL
- PCI_LOST_IRQ_DISABLE_ACPI
- PCI_LOST_IRQ_DISABLE_MSI
- PCI_LOST_IRQ_DISABLE_MSIX
- PCI_LOST_IRQ_NO_INFORMATION
- PCI_LTR_MAX_NOSNOOP_LAT
- PCI_LTR_MAX_SNOOP_LAT
- PCI_LTR_SCALE_MASK
- PCI_LTR_SCALE_SHIFT
- PCI_LTR_VALUE_MASK
- PCI_MAILBOX_BASE_ADDRESS
- PCI_MAIN_CMD_STS
- PCI_MAJOR_VERSION
- PCI_MAKE_VERSION
- PCI_MASTER0_REQ_MASK_2BITS
- PCI_MASTER1_REQ_MASK_2BITS
- PCI_MASTER2_REQ_MASK_2BITS
- PCI_MASTER_ABORT_RECEIVED_INTERRUPT
- PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE
- PCI_MASTER_ADDRESS_MASK
- PCI_MASTER_BASE
- PCI_MASTER_BASE_ADDRESS_MASK
- PCI_MASTER_BYTE_WRITE_ENABLES
- PCI_MASTER_COMMAND_SELECT
- PCI_MASTER_CYCLE_DONE_INTERRUPT
- PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE
- PCI_MASTER_EMPTY
- PCI_MASTER_IO_ADDRESS_MASK
- PCI_MASTER_IO_BUS_BASE_ADDRESS
- PCI_MASTER_IO_PCI_BASE_ADDRESS
- PCI_MASTER_MEM1_ADDRESS_MASK
- PCI_MASTER_MEM1_BUS_BASE_ADDRESS
- PCI_MASTER_MEM1_PCI_BASE_ADDRESS
- PCI_MASTER_READ
- PCI_MASTER_READ_WRITE
- PCI_MASTER_START
- PCI_MASTER_SUPPORT
- PCI_MASTER_WRITE
- PCI_MAX_BRIDGE_NUMBER
- PCI_MAX_BUSSES
- PCI_MAX_BUS_NUM
- PCI_MAX_DEVICES
- PCI_MAX_FUNCTION
- PCI_MAX_LAT
- PCI_MAX_LATENCY
- PCI_MBOX_BAR_NUM
- PCI_MEM
- PCI_MEM1_END
- PCI_MEM1_START
- PCI_MEM2_END
- PCI_MEM2_START
- PCI_MEMMISC_REG
- PCI_MEMORY_BASE
- PCI_MEMORY_LIMIT
- PCI_MEMORY_RANGE_MASK
- PCI_MEMORY_RANGE_TYPE_MASK
- PCI_MEM_BA
- PCI_MEM_DUMP_SIZE
- PCI_MEM_MASK
- PCI_MEM_PA
- PCI_MEM_RESOURCE_END
- PCI_MEM_RESOURCE_START
- PCI_MEM_SIZE
- PCI_MEM_SPACE_EN
- PCI_MESSAGE_BASE
- PCI_MESSAGE_MAXIMUM
- PCI_MGA_DATA
- PCI_MGA_INDEX
- PCI_MGA_OPTION
- PCI_MGA_OPTION2
- PCI_MGA_OPTION3
- PCI_MINOR_VERSION
- PCI_MIN_GNT
- PCI_MIN_GRANT
- PCI_MMAP_PROCFS
- PCI_MMAP_SYSFS
- PCI_MMCFG_BUS_OFFSET
- PCI_MMCFG_RESOURCE_NAME_LEN
- PCI_MODE
- PCI_MODE_32_BITS
- PCI_MODE_64BIT
- PCI_MODE_PCIX
- PCI_MODE_PCIX_M1_100
- PCI_MODE_PCIX_M1_133
- PCI_MODE_PCIX_M1_66
- PCI_MODE_PCIX_M2_100
- PCI_MODE_PCIX_M2_133
- PCI_MODE_PCIX_M2_66
- PCI_MODE_PCI_33
- PCI_MODE_PCI_66
- PCI_MODE_UNKNOWN_MODE
- PCI_MODE_UNSUPPORTED
- PCI_MODOFF
- PCI_MODON
- PCI_MONITOR_ENABLE_REG
- PCI_MSG_ADDR
- PCI_MSIX
- PCI_MSIX_ENTRY_CTRL_MASKBIT
- PCI_MSIX_ENTRY_DATA
- PCI_MSIX_ENTRY_LOWER_ADDR
- PCI_MSIX_ENTRY_SIZE
- PCI_MSIX_ENTRY_UPPER_ADDR
- PCI_MSIX_ENTRY_VECTOR_CTRL
- PCI_MSIX_FLAGS
- PCI_MSIX_FLAGS_BIRMASK
- PCI_MSIX_FLAGS_ENABLE
- PCI_MSIX_FLAGS_MASKALL
- PCI_MSIX_FLAGS_QSIZE
- PCI_MSIX_PBA
- PCI_MSIX_PBA_BIR
- PCI_MSIX_PBA_OFFSET
- PCI_MSIX_REG_BAR_NUM
- PCI_MSIX_TABLE
- PCI_MSIX_TABLE_BIR
- PCI_MSIX_TABLE_OFFSET
- PCI_MSIZE0
- PCI_MSIZE1
- PCI_MSI_ADDRESS_HI
- PCI_MSI_ADDRESS_LO
- PCI_MSI_DATA_32
- PCI_MSI_DATA_64
- PCI_MSI_DOORBELL_END
- PCI_MSI_DOORBELL_MASK
- PCI_MSI_DOORBELL_NR
- PCI_MSI_DOORBELL_START
- PCI_MSI_FLAGS
- PCI_MSI_FLAGS_64BIT
- PCI_MSI_FLAGS_ENABLE
- PCI_MSI_FLAGS_MASKBIT
- PCI_MSI_FLAGS_QMASK
- PCI_MSI_FLAGS_QSIZE
- PCI_MSI_MASK_32
- PCI_MSI_MASK_64
- PCI_MSI_PENDING_32
- PCI_MSI_PENDING_64
- PCI_MSI_RFU
- PCI_MSK_AL_RD
- PCI_MSK_AL_WR
- PCI_MSK_APB_DMA
- PCI_MSK_AUD_EXT
- PCI_MSK_AUD_INT
- PCI_MSK_AV_CORE
- PCI_MSK_GPIO0
- PCI_MSK_GPIO1
- PCI_MSK_IR
- PCI_MSK_RISC_RD
- PCI_MSK_RISC_WR
- PCI_MSK_VID_A
- PCI_MSK_VID_B
- PCI_MSK_VID_C
- PCI_MSR_ADDR
- PCI_MSR_CTRL
- PCI_MSR_DATA_HI
- PCI_MSR_DATA_LO
- PCI_MSU_COUNT
- PCI_MSU_DB
- PCI_MSU_M0
- PCI_MSU_M1
- PCI_MULTI
- PCI_MWBASEREVCCL_BASE
- PCI_MWBASEREVCCL_CCL
- PCI_MWBASEREVCCL_REV
- PCI_MWMASKDEV_DEVID
- PCI_MWMASKDEV_MWMASK
- PCI_NBP1_ACTIVE_BIT
- PCI_NBP1_CAPABLE_BIT
- PCI_NBP1_CAP_OFFSET
- PCI_NBP1_ENTERED_BIT
- PCI_NBP1_STAT_OFFSET
- PCI_NOASSIGN_BARS
- PCI_NOASSIGN_ROMS
- PCI_NODENAME_MAX
- PCI_NONE_BIST
- PCI_NON_PC0_ENABLE_BIT
- PCI_NON_PC0_OFFSET
- PCI_NORMAL_CACHE_LINE_SIZE
- PCI_NORMAL_HEADER_TYPE
- PCI_NORMAL_LATENCY_TIMER
- PCI_NO_CHECKS
- PCI_NP_AD
- PCI_NP_AD_OFFSET
- PCI_NP_CBE
- PCI_NP_CBE_OFFSET
- PCI_NP_RDATA
- PCI_NP_RDATA_OFFSET
- PCI_NP_WDATA
- PCI_NP_WDATA_OFFSET
- PCI_NRTR_DBG_E_ARB_L_MASK
- PCI_NRTR_DBG_E_ARB_L_SHIFT
- PCI_NRTR_DBG_E_ARB_MAX_CREDIT_MASK
- PCI_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT
- PCI_NRTR_DBG_E_ARB_N_MASK
- PCI_NRTR_DBG_E_ARB_N_SHIFT
- PCI_NRTR_DBG_E_ARB_S_MASK
- PCI_NRTR_DBG_E_ARB_S_SHIFT
- PCI_NRTR_DBG_E_ARB_W_MASK
- PCI_NRTR_DBG_E_ARB_W_SHIFT
- PCI_NRTR_DBG_L_ARB_E_MASK
- PCI_NRTR_DBG_L_ARB_E_SHIFT
- PCI_NRTR_DBG_L_ARB_MAX_CREDIT_MASK
- PCI_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT
- PCI_NRTR_DBG_L_ARB_N_MASK
- PCI_NRTR_DBG_L_ARB_N_SHIFT
- PCI_NRTR_DBG_L_ARB_S_MASK
- PCI_NRTR_DBG_L_ARB_S_SHIFT
- PCI_NRTR_DBG_L_ARB_W_MASK
- PCI_NRTR_DBG_L_ARB_W_SHIFT
- PCI_NRTR_DBG_N_ARB_E_MASK
- PCI_NRTR_DBG_N_ARB_E_SHIFT
- PCI_NRTR_DBG_N_ARB_L_MASK
- PCI_NRTR_DBG_N_ARB_L_SHIFT
- PCI_NRTR_DBG_N_ARB_MAX_CREDIT_MASK
- PCI_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT
- PCI_NRTR_DBG_N_ARB_S_MASK
- PCI_NRTR_DBG_N_ARB_S_SHIFT
- PCI_NRTR_DBG_N_ARB_W_MASK
- PCI_NRTR_DBG_N_ARB_W_SHIFT
- PCI_NRTR_DBG_S_ARB_E_MASK
- PCI_NRTR_DBG_S_ARB_E_SHIFT
- PCI_NRTR_DBG_S_ARB_L_MASK
- PCI_NRTR_DBG_S_ARB_L_SHIFT
- PCI_NRTR_DBG_S_ARB_MAX_CREDIT_MASK
- PCI_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT
- PCI_NRTR_DBG_S_ARB_N_MASK
- PCI_NRTR_DBG_S_ARB_N_SHIFT
- PCI_NRTR_DBG_S_ARB_W_MASK
- PCI_NRTR_DBG_S_ARB_W_SHIFT
- PCI_NRTR_DBG_W_ARB_E_MASK
- PCI_NRTR_DBG_W_ARB_E_SHIFT
- PCI_NRTR_DBG_W_ARB_L_MASK
- PCI_NRTR_DBG_W_ARB_L_SHIFT
- PCI_NRTR_DBG_W_ARB_MAX_CREDIT_MASK
- PCI_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT
- PCI_NRTR_DBG_W_ARB_N_MASK
- PCI_NRTR_DBG_W_ARB_N_SHIFT
- PCI_NRTR_DBG_W_ARB_S_MASK
- PCI_NRTR_DBG_W_ARB_S_SHIFT
- PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK
- PCI_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT
- PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK
- PCI_NRTR_HBW_MAX_CRED_RD_RS_SHIFT
- PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK
- PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT
- PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK
- PCI_NRTR_HBW_MAX_CRED_WR_RS_SHIFT
- PCI_NRTR_HBW_RANGE_BASE_H_VAL_MASK
- PCI_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT
- PCI_NRTR_HBW_RANGE_BASE_L_VAL_MASK
- PCI_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT
- PCI_NRTR_HBW_RANGE_HIT_IND_MASK
- PCI_NRTR_HBW_RANGE_HIT_IND_SHIFT
- PCI_NRTR_HBW_RANGE_MASK_H_VAL_MASK
- PCI_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT
- PCI_NRTR_HBW_RANGE_MASK_L_VAL_MASK
- PCI_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT
- PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK
- PCI_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT
- PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK
- PCI_NRTR_LBW_MAX_CRED_RD_RS_SHIFT
- PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK
- PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT
- PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK
- PCI_NRTR_LBW_MAX_CRED_WR_RS_SHIFT
- PCI_NRTR_LBW_RANGE_BASE_VAL_MASK
- PCI_NRTR_LBW_RANGE_BASE_VAL_SHIFT
- PCI_NRTR_LBW_RANGE_HIT_IND_MASK
- PCI_NRTR_LBW_RANGE_HIT_IND_SHIFT
- PCI_NRTR_LBW_RANGE_MASK_VAL_MASK
- PCI_NRTR_LBW_RANGE_MASK_VAL_SHIFT
- PCI_NRTR_MAX_OFFSET
- PCI_NRTR_NON_LIN_SCRAMB_EN_MASK
- PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT
- PCI_NRTR_RGLTR_RD_EN_MASK
- PCI_NRTR_RGLTR_RD_EN_SHIFT
- PCI_NRTR_RGLTR_RD_RESULT_VAL_MASK
- PCI_NRTR_RGLTR_RD_RESULT_VAL_SHIFT
- PCI_NRTR_RGLTR_WR_EN_MASK
- PCI_NRTR_RGLTR_WR_EN_SHIFT
- PCI_NRTR_RGLTR_WR_RESULT_VAL_MASK
- PCI_NRTR_RGLTR_WR_RESULT_VAL_SHIFT
- PCI_NRTR_SCRAMB_EN_VAL_MASK
- PCI_NRTR_SCRAMB_EN_VAL_SHIFT
- PCI_NRTR_SECTION
- PCI_NRTR_SPLIT_CFG_B2B_OPT_MASK
- PCI_NRTR_SPLIT_CFG_B2B_OPT_SHIFT
- PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK
- PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT
- PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK
- PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT
- PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK
- PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT
- PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK
- PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT
- PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK
- PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT
- PCI_NRTR_SPLIT_COEF_VAL_MASK
- PCI_NRTR_SPLIT_COEF_VAL_SHIFT
- PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK
- PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT
- PCI_NRTR_SPLIT_RD_SAT_VAL_MASK
- PCI_NRTR_SPLIT_RD_SAT_VAL_SHIFT
- PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK
- PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT
- PCI_NRTR_SPLIT_WR_SAT_VAL_MASK
- PCI_NRTR_SPLIT_WR_SAT_VAL_SHIFT
- PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK
- PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT
- PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK
- PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT
- PCI_NUM_BAR_RESOURCES
- PCI_NUM_INTX
- PCI_NUM_MSI
- PCI_NUM_RESOURCES
- PCI_OFFSET_FIRST_RANGE
- PCI_OFFSET_SECOND_RANGE
- PCI_OFFSET_THIRD_RANGE
- PCI_OHCI_INT_REG
- PCI_OHCI_PM_REG
- PCI_OPTION2_REG
- PCI_OPTION3_REG
- PCI_OPTION_ENABLE_ROM
- PCI_OPTION_REG
- PCI_OP_READ
- PCI_OP_WRITE
- PCI_OUT_INT_MASK
- PCI_OUT_INT_STATUS
- PCI_P2PDMA_MAP_BUS_ADDR
- PCI_P2PDMA_MAP_NOT_SUPPORTED
- PCI_P2PDMA_MAP_THRU_HOST_BRIDGE
- PCI_P2PDMA_MAP_UNKNOWN
- PCI_P2P_BUS_MASK
- PCI_P2P_BUS_OFFS
- PCI_P2P_CONF
- PCI_P2P_DEFAULT_IO_ALIGN
- PCI_P2P_DEFAULT_IO_ALIGN_1K
- PCI_P2P_DEFAULT_MEM_ALIGN
- PCI_P2P_DEV_MASK
- PCI_P2P_DEV_OFFS
- PCI_PADS_ENABLE
- PCI_PARAM_BIST
- PCI_PARAM_CLS
- PCI_PARAM_HT
- PCI_PARAM_LT
- PCI_PARENT_DUMP_SIZE
- PCI_PARITY_ERROR_INTERRUPT
- PCI_PARITY_ERROR_INTERRUPT_ENABLE
- PCI_PASID_CAP
- PCI_PASID_CAP_EXEC
- PCI_PASID_CAP_PRIV
- PCI_PASID_CTRL
- PCI_PASID_CTRL_ENABLE
- PCI_PASID_CTRL_EXEC
- PCI_PASID_CTRL_PRIV
- PCI_PATCH_DIR
- PCI_PBAC_MR
- PCI_PBAC_MRL
- PCI_PBAC_MRM
- PCI_PBAC_MR_BIT
- PCI_PBAC_MR_RD
- PCI_PBAC_MR_RD_LINE
- PCI_PBAC_MR_RD_MULT
- PCI_PBAC_MSI
- PCI_PBAC_P
- PCI_PBAC_PP
- PCI_PBAC_SB
- PCI_PBAC_SIZE
- PCI_PBAC_SIZE_BIT
- PCI_PBAC_TRP
- PCI_PBA_MSI
- PCI_PBA_P
- PCI_PBAxC_R
- PCI_PBAxC_RL
- PCI_PBAxC_RM
- PCI_PC1_ENABLE_BIT
- PCI_PC1_OFFSET
- PCI_PC6_ENABLE_BIT
- PCI_PC6_OFFSET
- PCI_PCIDOORBELL
- PCI_PCIDOORBELL_OFFSET
- PCI_PCIMEMBASE
- PCI_PCIMEMBASE_OFFSET
- PCI_PERIPHERAL
- PCI_PERR_INTERRUPT
- PCI_PERR_INTERRUPT_ENABLE
- PCI_PER_BRI
- PCI_PF_REG_BAR_NUM
- PCI_PGCTL
- PCI_PGCTL_ADSPPGD
- PCI_PGCTL_LSRMD_MASK
- PCI_PHY_COMA
- PCI_PHY_LNK_TIM_MSK
- PCI_PIBAR
- PCI_PID
- PCI_PIO_CONTROL
- PCI_PIO_ERROR_ADDRESS
- PCI_PIO_ERROR_COMMAND
- PCI_PLL
- PCI_PLL_INIT
- PCI_PL_16GT_LE_CTRL
- PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK
- PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK
- PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT
- PCI_PMBAR0
- PCI_PMBAR1
- PCI_PMCS
- PCI_PMCS_PS_MASK
- PCI_PMER1
- PCI_PMER2
- PCI_PMER3
- PCI_PME_INTERRUPT
- PCI_PME_INTERRUPT_ENABLE
- PCI_PMOS0_CONTROL
- PCI_PMOS1_CONTROL
- PCI_PM_BPCC_ENABLE
- PCI_PM_BUS_WAIT
- PCI_PM_CAP_AUX_POWER
- PCI_PM_CAP_D1
- PCI_PM_CAP_D2
- PCI_PM_CAP_DSI
- PCI_PM_CAP_PME
- PCI_PM_CAP_PME_CLOCK
- PCI_PM_CAP_PME_D0
- PCI_PM_CAP_PME_D1
- PCI_PM_CAP_PME_D2
- PCI_PM_CAP_PME_D3
- PCI_PM_CAP_PME_D3cold
- PCI_PM_CAP_PME_MASK
- PCI_PM_CAP_PME_SHIFT
- PCI_PM_CAP_RESERVED
- PCI_PM_CAP_VER_MASK
- PCI_PM_CTRL
- PCI_PM_CTRL_DATA_SCALE_MASK
- PCI_PM_CTRL_DATA_SEL_MASK
- PCI_PM_CTRL_NO_SOFT_RESET
- PCI_PM_CTRL_PME_ENABLE
- PCI_PM_CTRL_PME_STATUS
- PCI_PM_CTRL_STATE_MASK
- PCI_PM_D2_DELAY
- PCI_PM_D3COLD_WAIT
- PCI_PM_D3_WAIT
- PCI_PM_DATA_A
- PCI_PM_DATA_B
- PCI_PM_DATA_REGISTER
- PCI_PM_OPS_PTR
- PCI_PM_PMC
- PCI_PM_PPB_B2_B3
- PCI_PM_PPB_EXTENSIONS
- PCI_PM_SIZEOF
- PCI_PORT_ADDR
- PCI_PORT_HBA
- PCI_PORT_IN
- PCI_PORT_OUT
- PCI_PORT_SIZE
- PCI_PORT_XILINX_SIZE
- PCI_POWERMGMT
- PCI_POWER_ERROR
- PCI_POWER_STATE_CHANGE
- PCI_POWER_THROTTLE
- PCI_PREF_BASE_UPPER32
- PCI_PREF_LIMIT_UPPER32
- PCI_PREF_MEMORY_BASE
- PCI_PREF_MEMORY_LIMIT
- PCI_PREF_RANGE_MASK
- PCI_PREF_RANGE_TYPE_32
- PCI_PREF_RANGE_TYPE_64
- PCI_PREF_RANGE_TYPE_MASK
- PCI_PRIMARY_BUS
- PCI_PRIV_PE1
- PCI_PRIV_SHARE_NICCTRL
- PCI_PRI_ALLOC_REQ
- PCI_PRI_CTRL
- PCI_PRI_CTRL_ENABLE
- PCI_PRI_CTRL_RESET
- PCI_PRI_MAX_REQ
- PCI_PRI_STATUS
- PCI_PRI_STATUS_PASID
- PCI_PRI_STATUS_RF
- PCI_PRI_STATUS_STOPPED
- PCI_PRI_STATUS_UPRGI
- PCI_PROBE_BIOS
- PCI_PROBE_CONF1
- PCI_PROBE_CONF2
- PCI_PROBE_DEVTREE
- PCI_PROBE_MASK
- PCI_PROBE_MMCONF
- PCI_PROBE_NOEARLY
- PCI_PROBE_NONE
- PCI_PROBE_NORMAL
- PCI_PROBE_ONLY
- PCI_PRODUCT_ID_HAPS_HSOTG
- PCI_PROT
- PCI_PROTOCOL_VERSION_1_1
- PCI_PROTOCOL_VERSION_1_2
- PCI_PTM_CAP
- PCI_PTM_CAP_REQ
- PCI_PTM_CAP_ROOT
- PCI_PTM_CTRL
- PCI_PTM_CTRL_ENABLE
- PCI_PTM_CTRL_ROOT
- PCI_PTM_GRANULARITY_MASK
- PCI_PTP_BAR_NO
- PCI_PWR_CAP
- PCI_PWR_CAP_BUDGET
- PCI_PWR_DATA
- PCI_PWR_DATA_BASE
- PCI_PWR_DATA_PM_STATE
- PCI_PWR_DATA_PM_SUB
- PCI_PWR_DATA_RAIL
- PCI_PWR_DATA_SCALE
- PCI_PWR_DATA_TYPE
- PCI_PWR_DSR
- PCI_QUERY_BUS_RELATIONS
- PCI_QUERY_PROTOCOL_VERSION
- PCI_QUERY_RESOURCE_REQUIREMENTS
- PCI_QUERY_RESOURCE_RESOURCES
- PCI_QUERY_STOP
- PCI_QUERY_STOP_FAILED
- PCI_RD_REGULATOR_MAX_OFFSET
- PCI_RD_REGULATOR_SECTION
- PCI_READ_BLOCK
- PCI_REASSIGN_ALL_BUS
- PCI_REASSIGN_ALL_RSRC
- PCI_REBAR_CAP
- PCI_REBAR_CAP_SIZES
- PCI_REBAR_CTRL
- PCI_REBAR_CTRL_BAR_IDX
- PCI_REBAR_CTRL_BAR_SHIFT
- PCI_REBAR_CTRL_BAR_SIZE
- PCI_REBAR_CTRL_NBAR_MASK
- PCI_REBAR_CTRL_NBAR_SHIFT
- PCI_RECONFIG
- PCI_REENABLE
- PCI_REG
- PCI_REGION_FLAG_MASK
- PCI_REG_B2BBASE0_VID
- PCI_REG_B2BBASE1_SID
- PCI_REG_B2BMASK_CCH
- PCI_REG_CLASSREV
- PCI_REG_CMEM
- PCI_REG_COMMAND
- PCI_REG_CONFIG
- PCI_REG_ERR_ADDR
- PCI_REG_ID
- PCI_REG_MBAR
- PCI_REG_MEMORY_BASE
- PCI_REG_MWBASE_REV_CCL
- PCI_REG_MWMASK_DEV
- PCI_REG_NPKDSC
- PCI_REG_PARAM
- PCI_REG_PLX_IO_BASE
- PCI_REG_PLX_MEM_BASE
- PCI_REG_SPEC_INTACK
- PCI_REG_STATCMD
- PCI_REG_TIMEOUT
- PCI_REG_VMCAP
- PCI_REG_VMCONFIG
- PCI_REG_VMLOCK
- PCI_REMAP_DAC
- PCI_RESET_NIC
- PCI_RESOURCES_ASSIGNED
- PCI_RESOURCES_ASSIGNED2
- PCI_RESOURCES_RELEASED
- PCI_RES_TYPE_MASK
- PCI_RETRY_ABORT_ENABLE
- PCI_RETRY_ABORT_INTERRUPT
- PCI_RETRY_ABORT_INTERRUPT_ENABLE
- PCI_REVISION_ID
- PCI_REVISION_ID_ERROR_VAL
- PCI_REVISION_ID_HIP08_A
- PCI_REVISION_ID_HIP08_B
- PCI_REV_DESC
- PCI_REV_ID_VIA_VT6306
- PCI_ROM_ADDRESS
- PCI_ROM_ADDRESS1
- PCI_ROM_ADDRESS_ENABLE
- PCI_ROM_ADDRESS_MASK
- PCI_ROM_RESOURCE
- PCI_ROM_TABLE_MAX_OFFSET
- PCI_ROM_TABLE_SECTION
- PCI_ROOT_HID_STRING
- PCI_ROOT_NO_CRS
- PCI_RPWM
- PCI_RST_BAR_NO
- PCI_RefinedAccessConfig
- PCI_SAL_ADDRESS
- PCI_SAL_EXT_ADDRESS
- PCI_SATA_REGS
- PCI_SATA_REGS_INLINE
- PCI_SATA_REGS_MASK
- PCI_SATA_SIZEOF_LONG
- PCI_SATA_SIZEOF_SHORT
- PCI_SCAN_ALL_PCIE_DEVS
- PCI_SCR_DROP_MODE
- PCI_SCR_DROP_MODE_EN
- PCI_SCR_PAR_ERR
- PCI_SCR_PAR_RESP_EN
- PCI_SCR_RX_SERR
- PCI_SCR_RX_TAR_ABRT
- PCI_SCR_SERR_EN
- PCI_SCR_SIG_MST_ABRT
- PCI_SCR_SIG_PAR_ERR
- PCI_SCR_SIG_SERR
- PCI_SCR_SIG_TAR_ABRT
- PCI_SDHCI_IFDMA
- PCI_SDHCI_IFPIO
- PCI_SDHCI_IFVENDOR
- PCI_SECONDARY_BUS
- PCI_SEC_LATENCY_TIMER
- PCI_SEC_STATUS
- PCI_SELFID
- PCI_SERR_INTERRUPT
- PCI_SERR_INTERRUPT_ENABLE
- PCI_SERVICE
- PCI_SET_ADDR_TOKEN
- PCI_SHARED_LEN
- PCI_SHDW
- PCI_SIBAR
- PCI_SIBAR_ADDRESS_MASK
- PCI_SID_CHASSIS_NR
- PCI_SID_ESR
- PCI_SID_ESR_FIC
- PCI_SID_ESR_NSLOTS
- PCI_SIGNATURE
- PCI_SIZE_0
- PCI_SIZE_1
- PCI_SIZE_2
- PCI_SIZE_3
- PCI_SIZE_4
- PCI_SIZE_5
- PCI_SLOT
- PCI_SLOT_ID
- PCI_SLOT_ID_PREFIX
- PCI_SLOT_INFO
- PCI_SLOT_INFO_FIRST_BAR_MASK
- PCI_SLOT_INFO_SLOTS
- PCI_SLOT_MAX
- PCI_SLP_REG
- PCI_SMAP
- PCI_SMBAR0
- PCI_SMBAR1
- PCI_SOFTRST
- PCI_SOFTWARE_INT_CLEAR
- PCI_SOFTWARE_INT_SET
- PCI_SOFT_RESET
- PCI_SPACE_LIMIT
- PCI_SPACE_SIZE
- PCI_SPEED_100MHz_PCIX
- PCI_SPEED_100MHz_PCIX_266
- PCI_SPEED_100MHz_PCIX_533
- PCI_SPEED_100MHz_PCIX_ECC
- PCI_SPEED_133MHz_PCIX
- PCI_SPEED_133MHz_PCIX_266
- PCI_SPEED_133MHz_PCIX_533
- PCI_SPEED_133MHz_PCIX_ECC
- PCI_SPEED_33MHz
- PCI_SPEED_66MHz
- PCI_SPEED_66MHz_PCIX
- PCI_SPEED_66MHz_PCIX_266
- PCI_SPEED_66MHz_PCIX_533
- PCI_SPEED_66MHz_PCIX_ECC
- PCI_SPEED_SIZE
- PCI_SPEED_UNKNOWN
- PCI_SPI
- PCI_SRIOV_BAR
- PCI_SRIOV_CAP
- PCI_SRIOV_CAP_INTR
- PCI_SRIOV_CAP_VFM
- PCI_SRIOV_CTRL
- PCI_SRIOV_CTRL_ARI
- PCI_SRIOV_CTRL_INTR
- PCI_SRIOV_CTRL_MSE
- PCI_SRIOV_CTRL_VFE
- PCI_SRIOV_CTRL_VFM
- PCI_SRIOV_FUNC_LINK
- PCI_SRIOV_INITIAL_VF
- PCI_SRIOV_NUM_BARS
- PCI_SRIOV_NUM_VF
- PCI_SRIOV_STATUS
- PCI_SRIOV_STATUS_VFM
- PCI_SRIOV_SUP_PGSIZE
- PCI_SRIOV_SYS_PGSIZE
- PCI_SRIOV_TOTAL_VF
- PCI_SRIOV_VFM
- PCI_SRIOV_VFM_AV
- PCI_SRIOV_VFM_BIR
- PCI_SRIOV_VFM_MI
- PCI_SRIOV_VFM_MO
- PCI_SRIOV_VFM_OFFSET
- PCI_SRIOV_VFM_UA
- PCI_SRIOV_VF_DID
- PCI_SRIOV_VF_OFFSET
- PCI_SRIOV_VF_STRIDE
- PCI_SSVID_DEVICE_ID
- PCI_SSVID_VENDOR_ID
- PCI_SS_ID_MATROX_GENERIC
- PCI_SS_ID_MATROX_MARVEL_G200_AGP
- PCI_SS_ID_MATROX_MGA_G100_AGP
- PCI_SS_ID_MATROX_MGA_G100_PCI
- PCI_SS_ID_MATROX_MILLENIUM_G200_AGP
- PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP
- PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP
- PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
- PCI_SS_ID_SIEMENS_MGA_G100_AGP
- PCI_SS_ID_SIEMENS_MGA_G200_AGP
- PCI_SS_VENDOR_ID_MATROX
- PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
- PCI_STATCMD_CMD
- PCI_STATCMD_STATUS
- PCI_STATM_BME
- PCI_STATM_CRE
- PCI_STATM_CWE
- PCI_STATM_EED
- PCI_STATM_II
- PCI_STATM_MDPE
- PCI_STATM_NMI
- PCI_STATM_OSE
- PCI_STATM_PE
- PCI_STATM_PRD
- PCI_STATM_RIP
- PCI_STATM_RLE
- PCI_STATM_RMA
- PCI_STATM_RTA
- PCI_STATM_SSE
- PCI_STATM_STA
- PCI_STATM_TAE
- PCI_STATM_WR
- PCI_STATUS
- PCI_STATUS_66MHZ
- PCI_STATUS_66MHZ_CAPABLE
- PCI_STATUS_CAP_LIST
- PCI_STATUS_DETECTED_PARITY
- PCI_STATUS_DEVSEL_FAST
- PCI_STATUS_DEVSEL_MASK
- PCI_STATUS_DEVSEL_MEDIUM
- PCI_STATUS_DEVSEL_SLOW
- PCI_STATUS_ERROR_BITS
- PCI_STATUS_FAST_BACK
- PCI_STATUS_IMM_READY
- PCI_STATUS_INTERRUPT
- PCI_STATUS_NEW_CAP
- PCI_STATUS_PARITY
- PCI_STATUS_REC_MASTER_ABORT
- PCI_STATUS_REC_TARGET_ABORT
- PCI_STATUS_SIG_SYSTEM_ERROR
- PCI_STATUS_SIG_TARGET_ABORT
- PCI_STATUS_UDF
- PCI_STAT_BME
- PCI_STAT_CRE
- PCI_STAT_CWE
- PCI_STAT_EED
- PCI_STAT_II
- PCI_STAT_IRQ
- PCI_STAT_MASTER_ABORT_RCVD_BIT
- PCI_STAT_MDPE
- PCI_STAT_NMI
- PCI_STAT_OSE
- PCI_STAT_PARITY_ERROR_BIT
- PCI_STAT_PE
- PCI_STAT_PRD
- PCI_STAT_RIP
- PCI_STAT_RLE
- PCI_STAT_RMA
- PCI_STAT_RTA
- PCI_STAT_SSE
- PCI_STAT_STA
- PCI_STAT_SYSTEM_ERROR_BIT
- PCI_STAT_TAE
- PCI_STAT_TARGET_ABORT_RCVD_BIT
- PCI_STAT_TARGET_ABORT_SENT_BIT
- PCI_STAT_WR
- PCI_STC_FLUSHFLAG_INIT
- PCI_STC_FLUSHFLAG_SET
- PCI_STD_HEADER_SIZEOF
- PCI_STD_RESOURCES
- PCI_STD_RESOURCE_END
- PCI_STROB
- PCI_STSCMD_CLEAR_MASK
- PCI_STSCMD_RMA
- PCI_STSCMD_RTA
- PCI_STSCMD_SERREN
- PCI_STSCMD_SSE
- PCI_SUBCLASS_BR_PCI_TO_PCI
- PCI_SUBDEVICE_DEVICE
- PCI_SUBDEVICE_ID_AFAVLAB_P061
- PCI_SUBDEVICE_ID_ALACRITECH_1000X1
- PCI_SUBDEVICE_ID_ALACRITECH_1000X1F
- PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2
- PCI_SUBDEVICE_ID_ALACRITECH_CICADA
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF
- PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET
- PCI_SUBDEVICE_ID_ALACRITECH_SES1001F
- PCI_SUBDEVICE_ID_ALACRITECH_SES1001T
- PCI_SUBDEVICE_ID_AT_2700FX
- PCI_SUBDEVICE_ID_AT_2701FX
- PCI_SUBDEVICE_ID_CCD_BN1SM
- PCI_SUBDEVICE_ID_CCD_BN2S
- PCI_SUBDEVICE_ID_CCD_BN2SM
- PCI_SUBDEVICE_ID_CCD_BN4S
- PCI_SUBDEVICE_ID_CCD_BN4SM
- PCI_SUBDEVICE_ID_CCD_BN8S
- PCI_SUBDEVICE_ID_CCD_BN8SP
- PCI_SUBDEVICE_ID_CCD_BNE1
- PCI_SUBDEVICE_ID_CCD_BNE1D
- PCI_SUBDEVICE_ID_CCD_BNE1DP
- PCI_SUBDEVICE_ID_CCD_BNE1M
- PCI_SUBDEVICE_ID_CCD_HFC4S
- PCI_SUBDEVICE_ID_CCD_HFC8S
- PCI_SUBDEVICE_ID_CCD_HFCE1
- PCI_SUBDEVICE_ID_CCD_IOB1E1
- PCI_SUBDEVICE_ID_CCD_IOB4ST
- PCI_SUBDEVICE_ID_CCD_IOB8ST
- PCI_SUBDEVICE_ID_CCD_IOB8STR
- PCI_SUBDEVICE_ID_CCD_IOB8ST_1
- PCI_SUBDEVICE_ID_CCD_JH4S20
- PCI_SUBDEVICE_ID_CCD_JH8S
- PCI_SUBDEVICE_ID_CCD_JHSE1
- PCI_SUBDEVICE_ID_CCD_OV2S
- PCI_SUBDEVICE_ID_CCD_OV4S
- PCI_SUBDEVICE_ID_CCD_OV8S
- PCI_SUBDEVICE_ID_CCD_PMX2S
- PCI_SUBDEVICE_ID_CCD_SPD4S
- PCI_SUBDEVICE_ID_CCD_SPDE1
- PCI_SUBDEVICE_ID_CCD_SWYX4S
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC
- PCI_SUBDEVICE_ID_CHASE_PCIFAST4
- PCI_SUBDEVICE_ID_CHASE_PCIFAST8
- PCI_SUBDEVICE_ID_CHASE_PCIRAS4
- PCI_SUBDEVICE_ID_CHASE_PCIRAS8
- PCI_SUBDEVICE_ID_COMPUTONE_PG4
- PCI_SUBDEVICE_ID_COMPUTONE_PG6
- PCI_SUBDEVICE_ID_COMPUTONE_PG8
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6
- PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4
- PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232
- PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485
- PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2
- PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4
- PCI_SUBDEVICE_ID_CREATIVE_HENDRIX
- PCI_SUBDEVICE_ID_CREATIVE_SB0760
- PCI_SUBDEVICE_ID_CREATIVE_SB08801
- PCI_SUBDEVICE_ID_CREATIVE_SB08802
- PCI_SUBDEVICE_ID_CREATIVE_SB08803
- PCI_SUBDEVICE_ID_CREATIVE_SB1270
- PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_CAE_SERIAL_SUBSYSTEM
- PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ESE_SERIAL_SUBSYSTEM
- PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM
- PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM
- PCI_SUBDEVICE_ID_EXSYS_4014
- PCI_SUBDEVICE_ID_EXSYS_4055
- PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2
- PCI_SUBDEVICE_ID_HYPERCOPE_ERGO
- PCI_SUBDEVICE_ID_HYPERCOPE_METRO
- PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO
- PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT
- PCI_SUBDEVICE_ID_KEYSPAN_SX2
- PCI_SUBDEVICE_ID_NETPLC_FLASH
- PCI_SUBDEVICE_ID_NETPLC_RAM
- PCI_SUBDEVICE_ID_NI_7884
- PCI_SUBDEVICE_ID_NI_78E3
- PCI_SUBDEVICE_ID_NXPCA
- PCI_SUBDEVICE_ID_NXSB_PCA
- PCI_SUBDEVICE_ID_OCTPRO232
- PCI_SUBDEVICE_ID_OCTPRO422
- PCI_SUBDEVICE_ID_OXSEMI_C950
- PCI_SUBDEVICE_ID_PCI_RAS4
- PCI_SUBDEVICE_ID_PCI_RAS8
- PCI_SUBDEVICE_ID_POCTAL232
- PCI_SUBDEVICE_ID_POCTAL422
- PCI_SUBDEVICE_ID_QEMU
- PCI_SUBDEVICE_ID_SBE_2T3E3_P0
- PCI_SUBDEVICE_ID_SBE_2T3E3_P1
- PCI_SUBDEVICE_ID_SBE_T3E3
- PCI_SUBDEVICE_ID_SIIG_DUAL_00
- PCI_SUBDEVICE_ID_SIIG_DUAL_30
- PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL
- PCI_SUBDEVICE_ID_SPECIALIX_SPEED4
- PCI_SUBDEVICE_ID_UNKNOWN_0x1584
- PCI_SUBDEVICE_ID_UNKNOWN_0x1588
- PCI_SUBORDINATE_BUS
- PCI_SUBSYSTEM_DEVICEID
- PCI_SUBSYSTEM_ID
- PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD
- PCI_SUBSYSTEM_ID_GENWQE5
- PCI_SUBSYSTEM_ID_GENWQE5_NEW
- PCI_SUBSYSTEM_ID_GENWQE5_SRIOV
- PCI_SUBSYSTEM_VENDOR_ID
- PCI_SUBSYS_DEVID_81XX_BGX
- PCI_SUBSYS_DEVID_81XX_NIC_PF
- PCI_SUBSYS_DEVID_81XX_NIC_VF
- PCI_SUBSYS_DEVID_81XX_RGX
- PCI_SUBSYS_DEVID_83XX_BGX
- PCI_SUBSYS_DEVID_83XX_NIC_PF
- PCI_SUBSYS_DEVID_83XX_NIC_VF
- PCI_SUBSYS_DEVID_88XX_BGX
- PCI_SUBSYS_DEVID_88XX_NIC_PF
- PCI_SUBSYS_DEVID_88XX_NIC_VF
- PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF
- PCI_SUBSYS_DEVID_96XX
- PCI_SUBSYS_ID_CERC_ATA100_4CH
- PCI_SUBSYS_ID_INTEL_RAID_SRCS16
- PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK
- PCI_SUBSYS_ID_MEGARAID_I4_133_RAID
- PCI_SUBSYS_ID_MEGARAID_SATA_150_4
- PCI_SUBSYS_ID_MEGARAID_SATA_150_6
- PCI_SUBSYS_ID_MEGARAID_SCSI_320_0
- PCI_SUBSYS_ID_MEGARAID_SCSI_320_1
- PCI_SUBSYS_ID_MEGARAID_SCSI_320_2
- PCI_SUBSYS_ID_PERC3_DC
- PCI_SUBSYS_ID_PERC3_QC
- PCI_SUBSYS_ID_PERC3_SC
- PCI_SUBSYS_ID_PERC4E_DI_CORVETTE
- PCI_SUBSYS_ID_PERC4E_DI_EXPEDITION
- PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE
- PCI_SUBSYS_ID_PERC4E_DI_KOBUK
- PCI_SUBSYS_ID_PERC4E_SI_BIGBEND
- PCI_SUBSYS_ID_PERC4_DC
- PCI_SUBSYS_ID_PERC4_DI_DISCOVERY
- PCI_SUBSYS_ID_PERC4_DI_EVERGLADES
- PCI_SUBSYS_ID_PERC4_SC
- PCI_SUBTRACTIVE_DECODE
- PCI_SUBVENDOR_HST_SAPHIR3
- PCI_SUBVENDOR_ID_CHASE_PCIFAST
- PCI_SUBVENDOR_ID_CHASE_PCIRAS
- PCI_SUBVENDOR_ID_COMPUTONE
- PCI_SUBVENDOR_ID_CONNECT_TECH
- PCI_SUBVENDOR_ID_EXSYS
- PCI_SUBVENDOR_ID_HUMUSOFT
- PCI_SUBVENDOR_ID_IBM
- PCI_SUBVENDOR_ID_IBM_SRIOV
- PCI_SUBVENDOR_ID_KEYSPAN
- PCI_SUBVENDOR_ID_PEP
- PCI_SUBVENDOR_ID_PERLE
- PCI_SUBVENDOR_ID_REDHAT_QUMRANET
- PCI_SUBVENDOR_ID_SBSMODULARIO
- PCI_SUBVENDOR_ID_SIIG
- PCI_SUBVENDOR_SEDLBAUER_PCI
- PCI_SUBVENDOR_SPEEDFAX_PCI
- PCI_SUBVENDOR_SPEEDFAX_PYRAMID
- PCI_SUB_HPC_ID
- PCI_SUB_HPC_ID2
- PCI_SUB_HPC_ID3
- PCI_SUB_HPC_ID4
- PCI_SUB_HPC_ID_INTC
- PCI_SUB_ID_SEDLBAUER
- PCI_SUSCFG
- PCI_SUSEN
- PCI_SW_PWR_ON_RST
- PCI_SYS_COUNTER
- PCI_SYS_COUNTER_OVERFLOW
- PCI_SYS_INT_PENDING
- PCI_SYS_INT_PENDING_APSR
- PCI_SYS_INT_PENDING_CLEAR
- PCI_SYS_INT_PENDING_CLEAR_ALL
- PCI_SYS_INT_PENDING_CLEAR_DMA
- PCI_SYS_INT_PENDING_CLEAR_PCI
- PCI_SYS_INT_PENDING_CLEAR_PIO
- PCI_SYS_INT_PENDING_DMA
- PCI_SYS_INT_PENDING_PCI
- PCI_SYS_INT_PENDING_PIO
- PCI_SYS_INT_TARGET_MASK
- PCI_SYS_INT_TARGET_MASK_CLEAR
- PCI_SYS_INT_TARGET_MASK_SET
- PCI_SYS_LIMIT
- PCI_SYS_LIMIT_PSEUDO
- PCI_SYS_STATUS
- PCI_SYS_STATUS_PCI_RESET
- PCI_SYS_STATUS_PCI_RESET_ENABLE
- PCI_SYS_STATUS_PCI_SATTELITE_MODE
- PCI_SYS_STATUS_RESET
- PCI_SYS_STATUS_RESET_ENABLE
- PCI_SYS_STATUS_WATCHDOG_RESET
- PCI_ScanBusForNonBridge
- PCI_TAKE_AWAY_GNT_DISABLE
- PCI_TAKE_AWAY_GNT_ENABLE
- PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE
- PCI_TARGET_ABORT_RECEIVED_INTERRUPT
- PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE
- PCI_TARGET_LINK_SPEED_GEN1
- PCI_TARGET_LINK_SPEED_GEN2
- PCI_TARGET_LINK_SPEED_MASK
- PCI_TARGET_MEM1_ADDRESS_MASK
- PCI_TARGET_MEM1_BUS_BASE_ADDRESS
- PCI_TARGET_WINDOW1_BASE_ADDRESS
- PCI_TCSEL
- PCI_TC_DDT
- PCI_TC_DTIMER
- PCI_TC_DTIMER_BIT
- PCI_TC_RDR
- PCI_TC_RTIMER
- PCI_TC_RTIMER_BIT
- PCI_TGT_ABORT
- PCI_TIMEOUT
- PCI_TIMEOUT_RETRIES
- PCI_TIMEOUT_TO
- PCI_TIMING
- PCI_TONGA_CTRL
- PCI_TO_PCI_BRIDGE_CLASS
- PCI_TPH_BASE_SIZEOF
- PCI_TPH_CAP
- PCI_TPH_CAP_LOC_MASK
- PCI_TPH_CAP_ST_MASK
- PCI_TPH_CAP_ST_SHIFT
- PCI_TPH_LOC_CAP
- PCI_TPH_LOC_MSIX
- PCI_TPH_LOC_NONE
- PCI_TYPE_BRIDGE
- PCI_TYPE_CARDBUS_BRIDGE
- PCI_UART1_INT_REG
- PCI_UART2_INT_REG
- PCI_ULI5261_ID
- PCI_ULI5263_ID
- PCI_UNKNOWN
- PCI_UNMASK_ALL_IRQS
- PCI_USEC_CSR
- PCI_USEDATA64
- PCI_USER_CONFIG
- PCI_USER_CONFIG_C
- PCI_USER_READ_CONFIG
- PCI_USER_TIMER_CONFIG
- PCI_USER_TIMER_CONTROL
- PCI_USER_WRITE_CONFIG
- PCI_USES_MASTER
- PCI_USE_PIRQ_MASK
- PCI_USE__CRS
- PCI_VARIANT_PCI
- PCI_VARIANT_PCIE
- PCI_VARIANT_PCIX_266_MODE2
- PCI_VARIANT_PCIX_MODE1_ECC
- PCI_VARIANT_PCIX_MODE1_PARITY
- PCI_VCLK_DISABLE
- PCI_VCLK_ENABLE
- PCI_VC_CAP1_ARB_SIZE
- PCI_VC_CAP1_EVCC
- PCI_VC_CAP1_LPEVCC
- PCI_VC_CAP2_128_PHASE
- PCI_VC_CAP2_32_PHASE
- PCI_VC_CAP2_64_PHASE
- PCI_VC_CAP2_ARB_OFF
- PCI_VC_PORT_CAP1
- PCI_VC_PORT_CAP2
- PCI_VC_PORT_CTRL
- PCI_VC_PORT_CTRL_LOAD_TABLE
- PCI_VC_PORT_STATUS
- PCI_VC_PORT_STATUS_TABLE
- PCI_VC_RES_CAP
- PCI_VC_RES_CAP_128_PHASE
- PCI_VC_RES_CAP_128_PHASE_TB
- PCI_VC_RES_CAP_256_PHASE
- PCI_VC_RES_CAP_32_PHASE
- PCI_VC_RES_CAP_64_PHASE
- PCI_VC_RES_CAP_ARB_OFF
- PCI_VC_RES_CTRL
- PCI_VC_RES_CTRL_ARB_SELECT
- PCI_VC_RES_CTRL_ENABLE
- PCI_VC_RES_CTRL_ID
- PCI_VC_RES_CTRL_LOAD_TABLE
- PCI_VC_RES_STATUS
- PCI_VC_RES_STATUS_NEGO
- PCI_VC_RES_STATUS_TABLE
- PCI_VDEVICE
- PCI_VDP1
- PCI_VDP2
- PCI_VDP3
- PCI_VDRTCL0_D3PGD
- PCI_VDRTCL0_D3SRAMPGD
- PCI_VDRTCL0_DSRAMPGE_MASK
- PCI_VDRTCL0_DSRAMPGE_SHIFT
- PCI_VDRTCL0_ISRAMPGE_MASK
- PCI_VDRTCL0_ISRAMPGE_SHIFT
- PCI_VDRTCL2_APLLSE_MASK
- PCI_VDRTCL2_DCLCGE
- PCI_VDRTCL2_DTCGE
- PCI_VDRTCTL0
- PCI_VDRTCTL1
- PCI_VDRTCTL2
- PCI_VDRTCTL3
- PCI_VENDOR_ASPEED
- PCI_VENDOR_ID
- PCI_VENDOR_ID_3COM
- PCI_VENDOR_ID_3COM_2
- PCI_VENDOR_ID_3DFX
- PCI_VENDOR_ID_3DLABS
- PCI_VENDOR_ID_3WARE
- PCI_VENDOR_ID_9420
- PCI_VENDOR_ID_ABOCOM
- PCI_VENDOR_ID_ACCESIO
- PCI_VENDOR_ID_ACCESSIO
- PCI_VENDOR_ID_ACTEL
- PCI_VENDOR_ID_ADAPTEC
- PCI_VENDOR_ID_ADAPTEC2
- PCI_VENDOR_ID_ADDIDATA
- PCI_VENDOR_ID_ADL
- PCI_VENDOR_ID_ADLINK
- PCI_VENDOR_ID_ADVANTECH
- PCI_VENDOR_ID_AEC
- PCI_VENDOR_ID_AFAVLAB
- PCI_VENDOR_ID_AGESTAR
- PCI_VENDOR_ID_AI
- PCI_VENDOR_ID_AKS
- PCI_VENDOR_ID_AL
- PCI_VENDOR_ID_ALACRITECH
- PCI_VENDOR_ID_ALTEON
- PCI_VENDOR_ID_ALTERA
- PCI_VENDOR_ID_ALTIMA
- PCI_VENDOR_ID_AMAZON
- PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS
- PCI_VENDOR_ID_AMBIT
- PCI_VENDOR_ID_AMCC
- PCI_VENDOR_ID_AMD
- PCI_VENDOR_ID_AMI
- PCI_VENDOR_ID_AMPERE
- PCI_VENDOR_ID_AMPLICON
- PCI_VENDOR_ID_ANALOG_DEVICES
- PCI_VENDOR_ID_ANIGMA
- PCI_VENDOR_ID_APPLE
- PCI_VENDOR_ID_APPLICOM
- PCI_VENDOR_ID_AQUANTIA
- PCI_VENDOR_ID_ARASAN
- PCI_VENDOR_ID_ARECA
- PCI_VENDOR_ID_ARIMA
- PCI_VENDOR_ID_ARTOP
- PCI_VENDOR_ID_ASIX
- PCI_VENDOR_ID_ASMEDIA
- PCI_VENDOR_ID_ASP
- PCI_VENDOR_ID_ASUSTEK
- PCI_VENDOR_ID_AT
- PCI_VENDOR_ID_ATHEROS
- PCI_VENDOR_ID_ATI
- PCI_VENDOR_ID_ATT
- PCI_VENDOR_ID_ATTANSIC
- PCI_VENDOR_ID_ATTO
- PCI_VENDOR_ID_AUREAL
- PCI_VENDOR_ID_AVM
- PCI_VENDOR_ID_AXESS
- PCI_VENDOR_ID_AZWAVE
- PCI_VENDOR_ID_BCM_GVC
- PCI_VENDOR_ID_BELKIN
- PCI_VENDOR_ID_BERKOM
- PCI_VENDOR_ID_BLUECHERRY
- PCI_VENDOR_ID_BROADCOM
- PCI_VENDOR_ID_BROCADE
- PCI_VENDOR_ID_BROOKTREE
- PCI_VENDOR_ID_BUSLOGIC
- PCI_VENDOR_ID_CAVIUM
- PCI_VENDOR_ID_CB
- PCI_VENDOR_ID_CCD
- PCI_VENDOR_ID_CDNS
- PCI_VENDOR_ID_CENATEK
- PCI_VENDOR_ID_CHELSIO
- PCI_VENDOR_ID_CIRCUITCO
- PCI_VENDOR_ID_CIRRUS
- PCI_VENDOR_ID_CISCO
- PCI_VENDOR_ID_CMD
- PCI_VENDOR_ID_CMEDIA
- PCI_VENDOR_ID_CNET
- PCI_VENDOR_ID_COMMTECH
- PCI_VENDOR_ID_COMPAQ
- PCI_VENDOR_ID_COMPEX
- PCI_VENDOR_ID_COMPEX2
- PCI_VENDOR_ID_COMPUTONE
- PCI_VENDOR_ID_CONEXANT
- PCI_VENDOR_ID_CONTAQ
- PCI_VENDOR_ID_CONTEC
- PCI_VENDOR_ID_CREATIVE
- PCI_VENDOR_ID_CT
- PCI_VENDOR_ID_CX
- PCI_VENDOR_ID_CYCLADES
- PCI_VENDOR_ID_CYRIX
- PCI_VENDOR_ID_DAKTRONICS
- PCI_VENDOR_ID_DCI
- PCI_VENDOR_ID_DEC
- PCI_VENDOR_ID_DELL
- PCI_VENDOR_ID_DFI
- PCI_VENDOR_ID_DIGI
- PCI_VENDOR_ID_DIGIGRAM
- PCI_VENDOR_ID_DIGIUM
- PCI_VENDOR_ID_DLINK
- PCI_VENDOR_ID_DOMEX
- PCI_VENDOR_ID_DPT
- PCI_VENDOR_ID_DT
- PCI_VENDOR_ID_DUNORD
- PCI_VENDOR_ID_DYNALINK
- PCI_VENDOR_ID_ECTIVA
- PCI_VENDOR_ID_EF
- PCI_VENDOR_ID_EFAR
- PCI_VENDOR_ID_EICON
- PCI_VENDOR_ID_ELECTRONICDESIGNGMBH
- PCI_VENDOR_ID_ELSA
- PCI_VENDOR_ID_EMULEX
- PCI_VENDOR_ID_ENDRUN
- PCI_VENDOR_ID_ENE
- PCI_VENDOR_ID_ENSONIQ
- PCI_VENDOR_ID_ESDGMBH
- PCI_VENDOR_ID_ESS
- PCI_VENDOR_ID_ESSENTIAL
- PCI_VENDOR_ID_ETRON
- PCI_VENDOR_ID_EXAR
- PCI_VENDOR_ID_FARSITE
- PCI_VENDOR_ID_FD
- PCI_VENDOR_ID_FORE
- PCI_VENDOR_ID_FORTEMEDIA
- PCI_VENDOR_ID_FOXCONN
- PCI_VENDOR_ID_FREESCALE
- PCI_VENDOR_ID_FRESCO_LOGIC
- PCI_VENDOR_ID_FUJITSU_LIMITED
- PCI_VENDOR_ID_FUJITSU_ME
- PCI_VENDOR_ID_FUJITU_LIMITED
- PCI_VENDOR_ID_GENESYS
- PCI_VENDOR_ID_GIGABYTE
- PCI_VENDOR_ID_GLI
- PCI_VENDOR_ID_GOOGLE
- PCI_VENDOR_ID_GUILLEMOT
- PCI_VENDOR_ID_HABANALABS
- PCI_VENDOR_ID_HIFN
- PCI_VENDOR_ID_HILSCHER
- PCI_VENDOR_ID_HINT
- PCI_VENDOR_ID_HOLTEK
- PCI_VENDOR_ID_HP
- PCI_VENDOR_ID_HP_3PAR
- PCI_VENDOR_ID_HUAWEI
- PCI_VENDOR_ID_HUMUSOFT
- PCI_VENDOR_ID_HXT
- PCI_VENDOR_ID_HYGON
- PCI_VENDOR_ID_HYPERCOPE
- PCI_VENDOR_ID_IBM
- PCI_VENDOR_ID_ICE
- PCI_VENDOR_ID_ICOMP
- PCI_VENDOR_ID_ICP
- PCI_VENDOR_ID_IDT
- PCI_VENDOR_ID_IMS
- PCI_VENDOR_ID_INIT
- PCI_VENDOR_ID_INTASHIELD
- PCI_VENDOR_ID_INTEL
- PCI_VENDOR_ID_INTERG
- PCI_VENDOR_ID_IODATA
- PCI_VENDOR_ID_IOMEGA
- PCI_VENDOR_ID_IOTECH
- PCI_VENDOR_ID_IPHASE
- PCI_VENDOR_ID_ITE
- PCI_VENDOR_ID_JANZ
- PCI_VENDOR_ID_JMICRON
- PCI_VENDOR_ID_JR3
- PCI_VENDOR_ID_KAWASAKI
- PCI_VENDOR_ID_KOLTER
- PCI_VENDOR_ID_KORENIX
- PCI_VENDOR_ID_KTI
- PCI_VENDOR_ID_LATTICE
- PCI_VENDOR_ID_LAVA
- PCI_VENDOR_ID_LENOVO
- PCI_VENDOR_ID_LINKSYS
- PCI_VENDOR_ID_LMC
- PCI_VENDOR_ID_LSI_LOGIC
- PCI_VENDOR_ID_MADGE
- PCI_VENDOR_ID_MAINPINE
- PCI_VENDOR_ID_MARVELL
- PCI_VENDOR_ID_MARVELL_EXT
- PCI_VENDOR_ID_MATROX
- PCI_VENDOR_ID_MEDIATEK
- PCI_VENDOR_ID_MEILHAUS
- PCI_VENDOR_ID_MELLANOX
- PCI_VENDOR_ID_MEN
- PCI_VENDOR_ID_MICREL_KS
- PCI_VENDOR_ID_MICROGATE
- PCI_VENDOR_ID_MICRON
- PCI_VENDOR_ID_MICROSEMI
- PCI_VENDOR_ID_MICROSOFT
- PCI_VENDOR_ID_MICRO_MEMORY
- PCI_VENDOR_ID_MIRO
- PCI_VENDOR_ID_MOBILITY_ELECTRONICS
- PCI_VENDOR_ID_MORETON
- PCI_VENDOR_ID_MOTOROLA
- PCI_VENDOR_ID_MOXA
- PCI_VENDOR_ID_MYLEX
- PCI_VENDOR_ID_MYRICOM
- PCI_VENDOR_ID_NCR
- PCI_VENDOR_ID_NCUBE
- PCI_VENDOR_ID_NEC
- PCI_VENDOR_ID_NEOMAGIC
- PCI_VENDOR_ID_NETCELL
- PCI_VENDOR_ID_NETGEAR
- PCI_VENDOR_ID_NETMOS
- PCI_VENDOR_ID_NETRONOME
- PCI_VENDOR_ID_NETXEN
- PCI_VENDOR_ID_NI
- PCI_VENDOR_ID_NOTVALID
- PCI_VENDOR_ID_NS
- PCI_VENDOR_ID_NVIDIA
- PCI_VENDOR_ID_NVIDIA_SGS
- PCI_VENDOR_ID_O2
- PCI_VENDOR_ID_OCZ
- PCI_VENDOR_ID_OLICOM
- PCI_VENDOR_ID_OPTI
- PCI_VENDOR_ID_OXSEMI
- PCI_VENDOR_ID_PANACOM
- PCI_VENDOR_ID_PASEMI
- PCI_VENDOR_ID_PATHSCALE
- PCI_VENDOR_ID_PCTECH
- PCI_VENDOR_ID_PDC
- PCI_VENDOR_ID_PENSANDO
- PCI_VENDOR_ID_PERICOM
- PCI_VENDOR_ID_PHILIPS
- PCI_VENDOR_ID_PICOPOWER
- PCI_VENDOR_ID_PINNACLE_SYSTEMS
- PCI_VENDOR_ID_PLX
- PCI_VENDOR_ID_PLX_LEGACY
- PCI_VENDOR_ID_PMC
- PCI_VENDOR_ID_PMC_Sierra
- PCI_VENDOR_ID_PROMISE
- PCI_VENDOR_ID_QCOM
- PCI_VENDOR_ID_QLOGIC
- PCI_VENDOR_ID_QMI
- PCI_VENDOR_ID_QUATECH
- PCI_VENDOR_ID_QUICKLOGIC
- PCI_VENDOR_ID_QUICKNET
- PCI_VENDOR_ID_RADISYS
- PCI_VENDOR_ID_RDC
- PCI_VENDOR_ID_REALTEK
- PCI_VENDOR_ID_REDHAT
- PCI_VENDOR_ID_REDHAT_QUMRANET
- PCI_VENDOR_ID_RENESAS
- PCI_VENDOR_ID_RICOH
- PCI_VENDOR_ID_ROCKWELL
- PCI_VENDOR_ID_ROHM
- PCI_VENDOR_ID_RP
- PCI_VENDOR_ID_RTD
- PCI_VENDOR_ID_S2IO
- PCI_VENDOR_ID_S3
- PCI_VENDOR_ID_SAMSUNG
- PCI_VENDOR_ID_SATSAGEM
- PCI_VENDOR_ID_SBE
- PCI_VENDOR_ID_SBSMODULARIO
- PCI_VENDOR_ID_SCALEMP
- PCI_VENDOR_ID_SCM
- PCI_VENDOR_ID_SEALEVEL
- PCI_VENDOR_ID_SERVERENGINE
- PCI_VENDOR_ID_SERVERWORKS
- PCI_VENDOR_ID_SGI
- PCI_VENDOR_ID_SI
- PCI_VENDOR_ID_SIBYTE
- PCI_VENDOR_ID_SIEMENS
- PCI_VENDOR_ID_SIGMA
- PCI_VENDOR_ID_SIIG
- PCI_VENDOR_ID_SILAN
- PCI_VENDOR_ID_SIPACKETS
- PCI_VENDOR_ID_SITECOM
- PCI_VENDOR_ID_SK
- PCI_VENDOR_ID_SMSC
- PCI_VENDOR_ID_SOFTLOGIC
- PCI_VENDOR_ID_SOLARFLARE
- PCI_VENDOR_ID_SONY
- PCI_VENDOR_ID_SPECIALIX
- PCI_VENDOR_ID_ST
- PCI_VENDOR_ID_STALLION
- PCI_VENDOR_ID_STEC
- PCI_VENDOR_ID_STMICRO
- PCI_VENDOR_ID_STMMAC
- PCI_VENDOR_ID_SUN
- PCI_VENDOR_ID_SUNDANCE
- PCI_VENDOR_ID_SUNIX
- PCI_VENDOR_ID_SYBA
- PCI_VENDOR_ID_SYNOPSYS
- PCI_VENDOR_ID_SYSKONNECT
- PCI_VENDOR_ID_TCONRAD
- PCI_VENDOR_ID_TDI
- PCI_VENDOR_ID_TECHWELL
- PCI_VENDOR_ID_TEHUTI
- PCI_VENDOR_ID_TEKRAM
- PCI_VENDOR_ID_TI
- PCI_VENDOR_ID_TIGERJET
- PCI_VENDOR_ID_TIMB
- PCI_VENDOR_ID_TIMEDIA
- PCI_VENDOR_ID_TITAN
- PCI_VENDOR_ID_TOPIC
- PCI_VENDOR_ID_TOPSPIN
- PCI_VENDOR_ID_TOSHIBA
- PCI_VENDOR_ID_TOSHIBA_2
- PCI_VENDOR_ID_TRANSMETA
- PCI_VENDOR_ID_TRIDENT
- PCI_VENDOR_ID_TRIGEM
- PCI_VENDOR_ID_TSENG
- PCI_VENDOR_ID_TTI
- PCI_VENDOR_ID_TTTECH
- PCI_VENDOR_ID_TUNDRA
- PCI_VENDOR_ID_UBIQUITI
- PCI_VENDOR_ID_UMC
- PCI_VENDOR_ID_UNISYS
- PCI_VENDOR_ID_USR
- PCI_VENDOR_ID_V3
- PCI_VENDOR_ID_V3_SEMI
- PCI_VENDOR_ID_VIA
- PCI_VENDOR_ID_VITESSE
- PCI_VENDOR_ID_VLSI
- PCI_VENDOR_ID_VMIC
- PCI_VENDOR_ID_VMWARE
- PCI_VENDOR_ID_VORTEX
- PCI_VENDOR_ID_WCH
- PCI_VENDOR_ID_WD
- PCI_VENDOR_ID_WEITEK
- PCI_VENDOR_ID_WINBOND
- PCI_VENDOR_ID_WINBOND2
- PCI_VENDOR_ID_WORKBIT
- PCI_VENDOR_ID_XEN
- PCI_VENDOR_ID_XGI
- PCI_VENDOR_ID_XILINX
- PCI_VENDOR_ID_XILINX_RME
- PCI_VENDOR_ID_XIRCOM
- PCI_VENDOR_ID_YAMAHA
- PCI_VENDOR_ID_ZEITNET
- PCI_VENDOR_ID_ZHAOXIN
- PCI_VENDOR_ID_ZIATECH
- PCI_VENDOR_ID_ZOLTRIX
- PCI_VENDOR_ID_ZORAN
- PCI_VENDOR_NETLOGIC
- PCI_VEND_DEV
- PCI_VGA_STATE_CHANGE_BRIDGE
- PCI_VGA_STATE_CHANGE_DECODES
- PCI_VIA_VENDOR_ID
- PCI_VID
- PCI_VIDTC
- PCI_VIO
- PCI_VNDR_HEADER
- PCI_VNDR_HEADER_ID
- PCI_VNDR_HEADER_LEN
- PCI_VNDR_HEADER_REV
- PCI_VPD_ADDR
- PCI_VPD_ADDR_F
- PCI_VPD_ADDR_MASK
- PCI_VPD_DATA
- PCI_VPD_INFO_FLD_HDR_SIZE
- PCI_VPD_LRDT
- PCI_VPD_LRDT_ID
- PCI_VPD_LRDT_ID_STRING
- PCI_VPD_LRDT_RO_DATA
- PCI_VPD_LRDT_RW_DATA
- PCI_VPD_LRDT_TAG_SIZE
- PCI_VPD_LRDT_TIN_MASK
- PCI_VPD_LTIN_ID_STRING
- PCI_VPD_LTIN_RO_DATA
- PCI_VPD_LTIN_RW_DATA
- PCI_VPD_MAX_SIZE
- PCI_VPD_ROM_SZ
- PCI_VPD_RO_KEYWORD_CHKSUM
- PCI_VPD_RO_KEYWORD_MFR_ID
- PCI_VPD_RO_KEYWORD_PARTNO
- PCI_VPD_RO_KEYWORD_VENDOR0
- PCI_VPD_SRDT_END
- PCI_VPD_SRDT_LEN_MASK
- PCI_VPD_SRDT_TAG_SIZE
- PCI_VPD_SRDT_TIN_MASK
- PCI_VPD_STIN_END
- PCI_VPD_WR_THR
- PCI_VSEC_HDR
- PCI_VSEC_HDR_LEN_SHIFT
- PCI_VSEC_ID_INTEL_TBT
- PCI_WIDTH_SIZE
- PCI_WINDOW1
- PCI_WRITE_BLOCK
- PCI_WR_REGULATOR_MAX_OFFSET
- PCI_WR_REGULATOR_SECTION
- PCI_X_BRIDGE_SSTATUS
- PCI_X_BRIDGE_STATUS
- PCI_X_CMD
- PCI_X_CMD_DPERR_E
- PCI_X_CMD_ERO
- PCI_X_CMD_MAX_READ
- PCI_X_CMD_MAX_SPLIT
- PCI_X_CMD_READ_1K
- PCI_X_CMD_READ_2K
- PCI_X_CMD_READ_4K
- PCI_X_CMD_READ_512
- PCI_X_CMD_SPLIT_1
- PCI_X_CMD_SPLIT_12
- PCI_X_CMD_SPLIT_16
- PCI_X_CMD_SPLIT_2
- PCI_X_CMD_SPLIT_3
- PCI_X_CMD_SPLIT_32
- PCI_X_CMD_SPLIT_4
- PCI_X_CMD_SPLIT_8
- PCI_X_CMD_VERSION
- PCI_X_ECC_CSR
- PCI_X_SSTATUS_133MHZ
- PCI_X_SSTATUS_266MHZ
- PCI_X_SSTATUS_533MHZ
- PCI_X_SSTATUS_64BIT
- PCI_X_SSTATUS_FREQ
- PCI_X_SSTATUS_V1
- PCI_X_SSTATUS_V2
- PCI_X_SSTATUS_VERS
- PCI_X_STATUS
- PCI_X_STATUS_133MHZ
- PCI_X_STATUS_266MHZ
- PCI_X_STATUS_533MHZ
- PCI_X_STATUS_64BIT
- PCI_X_STATUS_BUS
- PCI_X_STATUS_COMPLEX
- PCI_X_STATUS_DEVFN
- PCI_X_STATUS_MAX_CUM
- PCI_X_STATUS_MAX_READ
- PCI_X_STATUS_MAX_SPLIT
- PCI_X_STATUS_SPL_DISC
- PCI_X_STATUS_SPL_ERR
- PCI_X_STATUS_UNX_SPL
- PCI_X_TCOUNT
- PCI_Y2_DLL_DIS
- PCI_Y2_PHY1_COMA
- PCI_Y2_PHY1_POWD
- PCI_Y2_PHY2_COMA
- PCI_Y2_PHY2_POWD
- PCI_Y2_PIG_ENA
- PCI_Y2_PME_LEGACY
- PCI_byte_BAD
- PCI_dword_BAD
- PCI_signature
- PCI_word_BAD
- PCIeC0_0
- PCIeC0_1
- PCIeC0_2
- PCIeC1_0
- PCIeC1_1
- PCIeC1_2
- PCIeC2_0
- PCIeC2_1
- PCIeC2_2
- PCKT_FRAGMENTED
- PCK_STUFF_STATUS_0
- PCK_STUFF_STATUS_1
- PCK_TH_MULT
- PCL711_AI_GAIN
- PCL711_AI_GAIN_REG
- PCL711_AI_LSB_REG
- PCL711_AI_MSB_DRDY
- PCL711_AI_MSB_REG
- PCL711_AO_LSB_REG
- PCL711_AO_MSB_REG
- PCL711_DI_LSB_REG
- PCL711_DI_MSB_REG
- PCL711_DO_LSB_REG
- PCL711_DO_MSB_REG
- PCL711_INT_STAT_CLR
- PCL711_INT_STAT_REG
- PCL711_MODE
- PCL711_MODE_DEFAULT
- PCL711_MODE_EXT
- PCL711_MODE_EXT_IRQ
- PCL711_MODE_IRQ
- PCL711_MODE_PACER
- PCL711_MODE_PACER_IRQ
- PCL711_MODE_REG
- PCL711_MODE_SOFTTRIG
- PCL711_MUX_CHAN
- PCL711_MUX_CS0
- PCL711_MUX_CS1
- PCL711_MUX_DIFF
- PCL711_MUX_REG
- PCL711_SOFTTRIG
- PCL711_SOFTTRIG_REG
- PCL711_TIMER_BASE
- PCL726_AO_LSB_REG
- PCL726_AO_MSB_REG
- PCL726_DI_LSB_REG
- PCL726_DI_MSB_REG
- PCL726_DO_LSB_REG
- PCL726_DO_MSB_REG
- PCL727_DI_LSB_REG
- PCL727_DI_MSB_REG
- PCL727_DO_LSB_REG
- PCL727_DO_MSB_REG
- PCL812_AI_LSB_REG
- PCL812_AI_MSB_DRDY
- PCL812_AI_MSB_REG
- PCL812_AO_LSB_REG
- PCL812_AO_MSB_REG
- PCL812_CTRL_DISABLE_TRIG
- PCL812_CTRL_PACER_DMA_TRIG
- PCL812_CTRL_PACER_EOC_TRIG
- PCL812_CTRL_REG
- PCL812_CTRL_SOFT_TRIG
- PCL812_CTRL_TRIG
- PCL812_DI_LSB_REG
- PCL812_DI_MSB_REG
- PCL812_DO_LSB_REG
- PCL812_DO_MSB_REG
- PCL812_MUX_CHAN
- PCL812_MUX_CS0
- PCL812_MUX_CS1
- PCL812_MUX_REG
- PCL812_RANGE_REG
- PCL812_SOFTTRIG_REG
- PCL812_STATUS_DRDY
- PCL812_STATUS_REG
- PCL812_TIMER_BASE
- PCL816_AI_LSB_REG
- PCL816_AI_MSB_REG
- PCL816_CLRINT_REG
- PCL816_CTRL_DMAEN
- PCL816_CTRL_DMASRC_SLOT
- PCL816_CTRL_EXT_TRIG
- PCL816_CTRL_INTEN
- PCL816_CTRL_PACER_TRIG
- PCL816_CTRL_POE
- PCL816_CTRL_REG
- PCL816_CTRL_SOFT_TRIG
- PCL816_DO_DI_LSB_REG
- PCL816_DO_DI_MSB_REG
- PCL816_MUX_REG
- PCL816_MUX_SCAN
- PCL816_RANGE_REG
- PCL816_STATUS_DRDY
- PCL816_STATUS_INTACT
- PCL816_STATUS_INTSRC_DMA
- PCL816_STATUS_INTSRC_MASK
- PCL816_STATUS_INTSRC_SLOT
- PCL816_STATUS_NEXT_CHAN_MASK
- PCL816_STATUS_REG
- PCL816_TIMER_BASE
- PCL818_AI_LSB_REG
- PCL818_AI_MSB_REG
- PCL818_AO_LSB_REG
- PCL818_AO_MSB_REG
- PCL818_CNTENABLE_CNT0_INT_CLK
- PCL818_CNTENABLE_PACER_TRIG0
- PCL818_CNTENABLE_REG
- PCL818_CTRL_DISABLE_TRIG
- PCL818_CTRL_DMAE
- PCL818_CTRL_EXT_TRIG
- PCL818_CTRL_INTE
- PCL818_CTRL_IRQ
- PCL818_CTRL_PACER_TRIG
- PCL818_CTRL_REG
- PCL818_CTRL_SOFT_TRIG
- PCL818_CTRL_TRIG
- PCL818_DO_DI_LSB_REG
- PCL818_DO_DI_MSB_REG
- PCL818_FI_DATAHI
- PCL818_FI_DATALO
- PCL818_FI_ENABLE
- PCL818_FI_FLUSH
- PCL818_FI_INTCLR
- PCL818_FI_STATUS
- PCL818_MUX_REG
- PCL818_MUX_SCAN
- PCL818_RANGE_REG
- PCL818_STATUS_EOC
- PCL818_STATUS_INT
- PCL818_STATUS_MUX
- PCL818_STATUS_NEXT_CHAN_MASK
- PCL818_STATUS_REG
- PCL818_STATUS_UNI
- PCL818_TIMER_BASE
- PCLAMP
- PCLK
- PCLK0_CLK_SRC
- PCLK1
- PCLK1_CLK_SRC
- PCLK2
- PCLK3
- PCLK4
- PCLKCON
- PCLK_AC97
- PCLK_ACODEC
- PCLK_ACODECPHY
- PCLK_ADC
- PCLK_ADCIF
- PCLK_ALIVE
- PCLK_AUDIO
- PCLK_AXI2ACEL_BRIDGE
- PCLK_BUS
- PCLK_BUS_PRE
- PCLK_CAN
- PCLK_CENTER_MAIN_NOC
- PCLK_CHIPID
- PCLK_CIC
- PCLK_CIF
- PCLK_COREDBG_B
- PCLK_COREDBG_L
- PCLK_CPU
- PCLK_CPU_BOOST
- PCLK_CRU
- PCLK_CTL
- PCLK_DBG_CXCS_PD_CORE_B
- PCLK_DCF
- PCLK_DDR
- PCLK_DDRPHY
- PCLK_DDRUPCTL
- PCLK_DDRUPCTL0
- PCLK_DDRUPCTL1
- PCLK_DDR_MON
- PCLK_DDR_SGRF
- PCLK_DDR_STDBY
- PCLK_DDR_UPCTL
- PCLK_DELAY_MASK
- PCLK_DELAY_SHIFT
- PCLK_DP_CTRL
- PCLK_DSP_CFG
- PCLK_EDP
- PCLK_EDP_CTRL
- PCLK_EDP_NOC
- PCLK_EFUSE
- PCLK_EFUSE0
- PCLK_EFUSE1
- PCLK_EFUSE1024
- PCLK_EFUSE1024NS
- PCLK_EFUSE1024S
- PCLK_EFUSE256
- PCLK_EFUSE_1024
- PCLK_EFUSE_256
- PCLK_FREQ_MAX
- PCLK_FREQ_MIN
- PCLK_G2D
- PCLK_GASKET
- PCLK_GATE
- PCLK_GMAC
- PCLK_GMAC_NOC
- PCLK_GPIO
- PCLK_GPIO0
- PCLK_GPIO0_PMU
- PCLK_GPIO1
- PCLK_GPIO1_PMU
- PCLK_GPIO2
- PCLK_GPIO3
- PCLK_GPIO4
- PCLK_GPIO5
- PCLK_GPIO6
- PCLK_GPIO7
- PCLK_GPIO8
- PCLK_GPIO_FSYS1
- PCLK_GRF
- PCLK_H265
- PCLK_HDCP
- PCLK_HDCP22
- PCLK_HDCP_NOC
- PCLK_HDMI
- PCLK_HDMIPHY
- PCLK_HDMI_CTRL
- PCLK_HDMI_PHY
- PCLK_HSI2C0
- PCLK_HSI2C1
- PCLK_HSI2C10
- PCLK_HSI2C11
- PCLK_HSI2C2
- PCLK_HSI2C3
- PCLK_HSI2C4
- PCLK_HSI2C5
- PCLK_HSI2C6
- PCLK_HSI2C7
- PCLK_HSI2C8
- PCLK_HSI2C9
- PCLK_HSICPHY
- PCLK_HSIRX
- PCLK_HSITX
- PCLK_I2C
- PCLK_I2C0
- PCLK_I2C0_PMU
- PCLK_I2C1
- PCLK_I2C2
- PCLK_I2C3
- PCLK_I2C4
- PCLK_I2C4_PMU
- PCLK_I2C5
- PCLK_I2C6
- PCLK_I2C7
- PCLK_I2C8_PMU
- PCLK_I2S
- PCLK_I2S0
- PCLK_I2S1
- PCLK_IIC0
- PCLK_IIC1
- PCLK_IIS0
- PCLK_IIS1
- PCLK_IIS2
- PCLK_INTMEM1_PMU
- PCLK_INTR_ARB
- PCLK_INTR_ARB_PMU
- PCLK_INV_SHIFT
- PCLK_IRDA
- PCLK_ISP
- PCLK_ISP1_WRAPPER
- PCLK_ISP_IN
- PCLK_JPEG
- PCLK_KEYPAD
- PCLK_LVDS_PHY
- PCLK_MAC
- PCLK_MAC2IO
- PCLK_MAC2PHY
- PCLK_MAILBOX
- PCLK_MAILBOX0
- PCLK_MAILBOX_PMU
- PCLK_MAX_FREQ
- PCLK_MFC
- PCLK_MIN_FREQ
- PCLK_MIPI
- PCLK_MIPICSIPHY
- PCLK_MIPIDSIPHY
- PCLK_MIPI_CSI
- PCLK_MIPI_DSI
- PCLK_MIPI_DSI0
- PCLK_MIPI_DSI1
- PCLK_MODE_SEL
- PCLK_MSCL_0
- PCLK_MSCL_1
- PCLK_NOC_PMU
- PCLK_OTP_NS
- PCLK_OTP_PHY
- PCLK_OWIRE
- PCLK_PCIE
- PCLK_PCM
- PCLK_PCM0
- PCLK_PCM1
- PCLK_PERI
- PCLK_PERIHP
- PCLK_PERIHP_GRF
- PCLK_PERIHP_NOC
- PCLK_PERILP0
- PCLK_PERILP1
- PCLK_PERILP1_NOC
- PCLK_PERILP_SGRF
- PCLK_PERI_PRE
- PCLK_PMU
- PCLK_PMUGRF
- PCLK_PMUGRF_PMU
- PCLK_PMU_INTR_ARB
- PCLK_PMU_MSCL
- PCLK_PMU_PRE
- PCLK_PPMU_MSCL_0
- PCLK_PPMU_MSCL_1
- PCLK_PS2C
- PCLK_PUBL
- PCLK_PUBL0
- PCLK_PUBL1
- PCLK_PWM
- PCLK_PWM0
- PCLK_PWM01
- PCLK_PWM0_PMU
- PCLK_PWM1
- PCLK_PWM2
- PCLK_PWM23
- PCLK_QE_G2D
- PCLK_QE_JPEG
- PCLK_QE_MSCL_0
- PCLK_QE_MSCL_1
- PCLK_RATIO_MASK
- PCLK_RATIO_SHIFT
- PCLK_RKPWM
- PCLK_RKPWM_PMU
- PCLK_RTC
- PCLK_SARADC
- PCLK_SDI
- PCLK_SEL_DIV2
- PCLK_SEL_DIV4
- PCLK_SEL_MASK
- PCLK_SEL_SHIFT
- PCLK_SEL_X1
- PCLK_SEL_X2
- PCLK_SFC
- PCLK_SGRF
- PCLK_SGRF_PMU
- PCLK_SIM
- PCLK_SIM_CARD
- PCLK_SKEY
- PCLK_SPDIF
- PCLK_SPI
- PCLK_SPI0
- PCLK_SPI1
- PCLK_SPI2
- PCLK_SPI3
- PCLK_SPI3_PMU
- PCLK_SPI4
- PCLK_SPI5
- PCLK_SRC_PMU
- PCLK_TIMER
- PCLK_TIMER0
- PCLK_TIMER1
- PCLK_TIMER2
- PCLK_TIMER3
- PCLK_TIMER_PMU
- PCLK_TMU
- PCLK_TSADC
- PCLK_TZPC
- PCLK_UART0
- PCLK_UART0_PMU
- PCLK_UART1
- PCLK_UART2
- PCLK_UART3
- PCLK_UART4
- PCLK_UART4_PMU
- PCLK_UART5
- PCLK_UPHY0_TCPD_G
- PCLK_UPHY0_TCPHY_G
- PCLK_UPHY1_TCPD_G
- PCLK_UPHY1_TCPHY_G
- PCLK_USB2_GRF
- PCLK_USB3PHY_OTG
- PCLK_USB3PHY_PIPE
- PCLK_USB3_GRF
- PCLK_USBD
- PCLK_USBPHY_MUX_G
- PCLK_USBSD_DET
- PCLK_USB_GRF
- PCLK_VIO
- PCLK_VIO2_H2P
- PCLK_VIO_GRF
- PCLK_VIO_H2P
- PCLK_VIO_NOC
- PCLK_VIP
- PCLK_VLD
- PCLK_VO_PRE
- PCLK_WDT
- PCLK_WDT_M0_PMU
- PCLK_WDT_NS
- PCLMUL_MIN_LEN
- PCLR
- PCLRSV
- PCLUKN
- PCLUNL
- PCL_10
- PCL_6N
- PCL_6R
- PCL_7S
- PCL_APP_LTSSM_ENABLE
- PCL_APP_PM0
- PCL_APP_READY_CTRL
- PCL_BIGENDIAN
- PCL_CFG_AER_RC_ERR_MSI_STATUS
- PCL_CFG_BW_MGT_STATUS
- PCL_CFG_LINK_AUTO_BW_STATUS
- PCL_CFG_PME_MSI_STATUS
- PCL_CMD_ADD
- PCL_CMD_BRANCH
- PCL_CMD_COMPARE
- PCL_CMD_LBUS_TO_PCI
- PCL_CMD_LOAD
- PCL_CMD_NOP
- PCL_CMD_PCI_TO_LBUS
- PCL_CMD_RCV
- PCL_CMD_RCV_AND_UPDATE
- PCL_CMD_STORE0
- PCL_CMD_STORE1
- PCL_CMD_STORED
- PCL_CMD_STOREQ
- PCL_CMD_SWAP_COMPARE
- PCL_CMD_UNFXMT
- PCL_CMD_XMT
- PCL_COND_DMARDY_CLEAR
- PCL_COND_DMARDY_SET
- PCL_GEN_INTR
- PCL_ISOMODE
- PCL_LAST_BUFF
- PCL_LAST_CMD
- PCL_NEXT_INVALID
- PCL_PCLK_ALIVE
- PCL_PERST_NOE_REGEN
- PCL_PERST_NOE_REGVAL
- PCL_PERST_OUT_REGEN
- PCL_PERST_OUT_REGVAL
- PCL_PERST_PLDN_REGEN
- PCL_PERST_PLDN_REGVAL
- PCL_PHY_R00
- PCL_PHY_R06
- PCL_PHY_R26
- PCL_PHY_RESET
- PCL_PHY_RESET_N
- PCL_PHY_RESET_N_MNMODE
- PCL_PHY_TEST_I
- PCL_PHY_TEST_O
- PCL_PINCTRL0
- PCL_PIPEMON
- PCL_RCV_INT
- PCL_RCV_INTX
- PCL_RCV_INTX_ALL_ENABLE
- PCL_RCV_INTX_ALL_MASK
- PCL_RCV_INTX_ALL_STATUS
- PCL_RCV_INTX_MASK_SHIFT
- PCL_RCV_INTX_STATUS_SHIFT
- PCL_RCV_INT_ALL_ENABLE
- PCL_RDLH_LINK_UP
- PCL_STATUS_LINK
- PCL_SYS_AUX_PWR_DET
- PCL_WAITSTAT
- PCL_XMLH_LINK_UP
- PCL__0
- PCL__1
- PCL__2
- PCL__3
- PCL__4
- PCL__6
- PCL__7
- PCL__8
- PCL__9
- PCM027_BTDET_IRQ
- PCM027_CAN_IRQ
- PCM027_CAN_IRQ_EDGE
- PCM027_CAN_IRQ_GPIO
- PCM027_CAN_PHYS
- PCM027_CAN_SIZE
- PCM027_EGPIO_CS
- PCM027_EGPIO_CS_MODE
- PCM027_EGPIO_IRQ
- PCM027_EGPIO_IRQ_EDGE
- PCM027_EGPIO_IRQ_GPIO
- PCM027_ETH_IRQ
- PCM027_ETH_IRQ_EDGE
- PCM027_ETH_IRQ_GPIO
- PCM027_ETH_PHYS
- PCM027_ETH_SIZE
- PCM027_FF_RI_IRQ
- PCM027_FLASH_PHYS
- PCM027_FLASH_SIZE
- PCM027_IRQ
- PCM027_LED_CPU
- PCM027_LED_HEARD_BEAT
- PCM027_MMCDET_IRQ
- PCM027_NR_IRQS
- PCM027_PM_5V_IRQ
- PCM027_RTC_IRQ
- PCM027_RTC_IRQ_EDGE
- PCM027_RTC_IRQ_GPIO
- PCM037_EET
- PCM037_PCM970
- PCM1681_ATT_CONTROL
- PCM1681_DAC_CONTROL
- PCM1681_DEEMPH_CONTROL
- PCM1681_DEEMPH_MASK
- PCM1681_DEEMPH_RATE_MASK
- PCM1681_FMT_CONTROL
- PCM1681_PCM_FORMATS
- PCM1681_PCM_RATES
- PCM1681_SOFT_MUTE
- PCM1681_SOFT_MUTE_ALL
- PCM1681_ZERO_DETECT_STATUS
- PCM1789_DAC_VOL_LEFT
- PCM1789_DAC_VOL_RIGHT
- PCM1789_FMT_CONTROL
- PCM1789_FMT_MASK
- PCM1789_FORMATS
- PCM1789_MUTE_CONTROL
- PCM1789_MUTE_MASK
- PCM1789_MUTE_SRET
- PCM1789_SOFT_MUTE
- PCM1792A_FORMATS
- PCM1796_ATLD
- PCM1796_ATL_MASK
- PCM1796_ATR_MASK
- PCM1796_ATS_1
- PCM1796_ATS_2
- PCM1796_ATS_4
- PCM1796_ATS_8
- PCM1796_ATS_MASK
- PCM1796_CHSL_LEFT
- PCM1796_CHSL_MASK
- PCM1796_CHSL_RIGHT
- PCM1796_DFMS
- PCM1796_DFTH
- PCM1796_DME
- PCM1796_DMF_32
- PCM1796_DMF_441
- PCM1796_DMF_48
- PCM1796_DMF_MASK
- PCM1796_DSD
- PCM1796_DZ_MASK
- PCM1796_FLT_MASK
- PCM1796_FLT_SHARP
- PCM1796_FLT_SLOW
- PCM1796_FMT_16_I2S
- PCM1796_FMT_16_RJUST
- PCM1796_FMT_20_RJUST
- PCM1796_FMT_24_I2S
- PCM1796_FMT_24_LJUST
- PCM1796_FMT_24_RJUST
- PCM1796_FMT_MASK
- PCM1796_H_INCLUDED
- PCM1796_ID_MASK
- PCM1796_INZD
- PCM1796_MONO
- PCM1796_MUTE
- PCM1796_OPE
- PCM1796_OS_128
- PCM1796_OS_32
- PCM1796_OS_64
- PCM1796_OS_MASK
- PCM1796_PCMZ
- PCM1796_REG_BASE
- PCM1796_REV
- PCM1796_SRST
- PCM1796_ZFGL
- PCM1796_ZFGR
- PCM179X_ATLD_ENABLE
- PCM179X_DAC_VOL_LEFT
- PCM179X_DAC_VOL_RIGHT
- PCM179X_FMT_CONTROL
- PCM179X_FMT_MASK
- PCM179X_FMT_SHIFT
- PCM179X_MODE_CONTROL
- PCM179X_MUTE_MASK
- PCM179X_MUTE_SHIFT
- PCM179X_SOFT_MUTE
- PCM1862
- PCM1863
- PCM1864
- PCM1865
- PCM186X_ADC1_INPUT_SEL_L
- PCM186X_ADC1_INPUT_SEL_R
- PCM186X_ADC2_INPUT_SEL_L
- PCM186X_ADC2_INPUT_SEL_R
- PCM186X_ADC_CLK_DIV
- PCM186X_ADC_INPUT_SEL_MASK
- PCM186X_ADC_INPUT_SEL_POL
- PCM186X_AUXADC_DATA_CTRL
- PCM186X_AUXADC_DATA_LSB
- PCM186X_AUXADC_DATA_MSB
- PCM186X_AUXADC_INPUT_SEL
- PCM186X_BCK_DIV
- PCM186X_CLK_CTRL
- PCM186X_CLK_CTRL_ADC_SRC_PLL
- PCM186X_CLK_CTRL_CLKDET_EN
- PCM186X_CLK_CTRL_DSP1_SRC_PLL
- PCM186X_CLK_CTRL_DSP2_SRC_PLL
- PCM186X_CLK_CTRL_MST_MODE
- PCM186X_CLK_CTRL_SCK_SRC_PLL
- PCM186X_CLK_CTRL_SCK_XI_SEL0
- PCM186X_CLK_CTRL_SCK_XI_SEL1
- PCM186X_CLK_STATUS
- PCM186X_CLK_STATUS_BCKERR
- PCM186X_CLK_STATUS_BCKHLT
- PCM186X_CLK_STATUS_LRCKERR
- PCM186X_CLK_STATUS_LRCKHLT
- PCM186X_CLK_STATUS_SCKERR
- PCM186X_CLK_STATUS_SCKHLT
- PCM186X_CURR_TRIM_CTRL
- PCM186X_DEVICE_STATUS
- PCM186X_DIN_RESAMP_CTRL
- PCM186X_DIV_STATUS
- PCM186X_DPGA_GAIN_CTRL
- PCM186X_DPGA_MIC_CTRL
- PCM186X_DPGA_VAL_CH1_L
- PCM186X_DPGA_VAL_CH1_R
- PCM186X_DPGA_VAL_CH2_L
- PCM186X_DPGA_VAL_CH2_R
- PCM186X_DSP1_CLK_DIV
- PCM186X_DSP2_CLK_DIV
- PCM186X_FILTER_MUTE_CTRL
- PCM186X_FORMATS
- PCM186X_FSAMPLE_STATUS
- PCM186X_GPIO1_0_CTRL
- PCM186X_GPIO1_0_DIR_CTRL
- PCM186X_GPIO3_2_CTRL
- PCM186X_GPIO3_2_DIR_CTRL
- PCM186X_GPIO_IN_OUT
- PCM186X_GPIO_PULL_CTRL
- PCM186X_INT_ENABLE
- PCM186X_INT_FLAG
- PCM186X_INT_POL_WIDTH
- PCM186X_LRK_DIV
- PCM186X_MAX_REGISTER
- PCM186X_MEM_RDATA0
- PCM186X_MEM_RDATA1
- PCM186X_MEM_RDATA2
- PCM186X_MEM_RDATA3
- PCM186X_MEM_WDATA0
- PCM186X_MEM_WDATA1
- PCM186X_MEM_WDATA2
- PCM186X_MEM_WDATA3
- PCM186X_MIC_BIAS_CTRL
- PCM186X_MMAP_ADDRESS
- PCM186X_MMAP_STAT_BUSY
- PCM186X_MMAP_STAT_CTRL
- PCM186X_MMAP_STAT_DONE
- PCM186X_MMAP_STAT_R_REQ
- PCM186X_MMAP_STAT_W_REQ
- PCM186X_OSC_PWR_DOWN_CTRL
- PCM186X_PAGE
- PCM186X_PAGE_BASE
- PCM186X_PAGE_LEN
- PCM186X_PCM_CFG
- PCM186X_PCM_CFG_FMT_I2S
- PCM186X_PCM_CFG_FMT_LEFTJ
- PCM186X_PCM_CFG_FMT_MASK
- PCM186X_PCM_CFG_FMT_RIGHTJ
- PCM186X_PCM_CFG_FMT_SHIFT
- PCM186X_PCM_CFG_FMT_TDM
- PCM186X_PCM_CFG_RX_WLEN_16
- PCM186X_PCM_CFG_RX_WLEN_20
- PCM186X_PCM_CFG_RX_WLEN_24
- PCM186X_PCM_CFG_RX_WLEN_32
- PCM186X_PCM_CFG_RX_WLEN_MASK
- PCM186X_PCM_CFG_RX_WLEN_SHIFT
- PCM186X_PCM_CFG_TDM_LRCK_MODE
- PCM186X_PCM_CFG_TX_WLEN_16
- PCM186X_PCM_CFG_TX_WLEN_20
- PCM186X_PCM_CFG_TX_WLEN_24
- PCM186X_PCM_CFG_TX_WLEN_32
- PCM186X_PCM_CFG_TX_WLEN_MASK
- PCM186X_PCM_CFG_TX_WLEN_SHIFT
- PCM186X_PGA_CTRL
- PCM186X_PGA_VAL_CH1_L
- PCM186X_PGA_VAL_CH1_R
- PCM186X_PGA_VAL_CH2_L
- PCM186X_PGA_VAL_CH2_R
- PCM186X_PLL_CTRL
- PCM186X_PLL_CTRL_EN
- PCM186X_PLL_CTRL_LOCK
- PCM186X_PLL_CTRL_REF_SEL
- PCM186X_PLL_D_DIV_LSB
- PCM186X_PLL_D_DIV_MSB
- PCM186X_PLL_J_DIV
- PCM186X_PLL_P_DIV
- PCM186X_PLL_R_DIV
- PCM186X_PLL_SCK_DIV
- PCM186X_POWER_CTRL
- PCM186X_PWR_CTRL_PWRDN
- PCM186X_PWR_CTRL_SLEEP
- PCM186X_PWR_CTRL_STBY
- PCM186X_RATES
- PCM186X_RESET
- PCM186X_SIGDET_DC_DIFF_CH1_L
- PCM186X_SIGDET_DC_DIFF_CH1_R
- PCM186X_SIGDET_DC_DIFF_CH2_L
- PCM186X_SIGDET_DC_DIFF_CH2_R
- PCM186X_SIGDET_DC_DIFF_CH3_L
- PCM186X_SIGDET_DC_DIFF_CH3_R
- PCM186X_SIGDET_DC_DIFF_CH4_L
- PCM186X_SIGDET_DC_DIFF_CH4_R
- PCM186X_SIGDET_DC_LEV_CH1_L
- PCM186X_SIGDET_DC_LEV_CH1_R
- PCM186X_SIGDET_DC_LEV_CH2_L
- PCM186X_SIGDET_DC_LEV_CH2_R
- PCM186X_SIGDET_DC_LEV_CH3_L
- PCM186X_SIGDET_DC_LEV_CH3_R
- PCM186X_SIGDET_DC_LEV_CH4_L
- PCM186X_SIGDET_DC_LEV_CH4_R
- PCM186X_SIGDET_DC_REF_CH1_L
- PCM186X_SIGDET_DC_REF_CH1_R
- PCM186X_SIGDET_DC_REF_CH2_L
- PCM186X_SIGDET_DC_REF_CH2_R
- PCM186X_SIGDET_DC_REF_CH3_L
- PCM186X_SIGDET_DC_REF_CH3_R
- PCM186X_SIGDET_DC_REF_CH4_L
- PCM186X_SIGDET_DC_REF_CH4_R
- PCM186X_SIGDET_INT_INTVL
- PCM186X_SIGDET_LOSS_TIME
- PCM186X_SIGDET_MASK
- PCM186X_SIGDET_MODE
- PCM186X_SIGDET_SCAN_TIME
- PCM186X_SIGDET_STAT
- PCM186X_SUPPLY_STATUS
- PCM186X_SUPPLY_STATUS_AVDD
- PCM186X_SUPPLY_STATUS_DVDD
- PCM186X_SUPPLY_STATUS_LDO
- PCM186X_TDM_RX_OFFSET
- PCM186X_TDM_TX_OFFSET
- PCM186X_TDM_TX_SEL
- PCM186X_TDM_TX_SEL_2CH
- PCM186X_TDM_TX_SEL_4CH
- PCM186X_TDM_TX_SEL_6CH
- PCM186X_TDM_TX_SEL_MASK
- PCM186x_NUM_SUPPLIES
- PCM1_CLK
- PCM1_IN
- PCM1_OUT
- PCM1_PCM2_LOOPBACK_MASK
- PCM1_PCM2_LOOPBACK_MASK_SFT
- PCM1_PCM2_LOOPBACK_SFT
- PCM1_RX_FIFO_OV_MASK
- PCM1_RX_FIFO_OV_MASK_SFT
- PCM1_RX_FIFO_OV_SFT
- PCM1_SYNC
- PCM1_SYNC_GLITCH_MASK
- PCM1_SYNC_GLITCH_MASK_SFT
- PCM1_SYNC_GLITCH_SFT
- PCM1_TX_FIFO_OV_MASK
- PCM1_TX_FIFO_OV_MASK_SFT
- PCM1_TX_FIFO_OV_SFT
- PCM2_AFIFO_MASK
- PCM2_AFIFO_MASK_SFT
- PCM2_AFIFO_SFT
- PCM2_BCLK_IN_INV_MASK
- PCM2_BCLK_IN_INV_MASK_SFT
- PCM2_BCLK_IN_INV_SFT
- PCM2_BT_MODE_MASK
- PCM2_BT_MODE_MASK_SFT
- PCM2_BT_MODE_SFT
- PCM2_BUFFER_LOOPBACK_MASK
- PCM2_BUFFER_LOOPBACK_MASK_SFT
- PCM2_BUFFER_LOOPBACK_SFT
- PCM2_DAI_PCM_LOOPBACK_MASK
- PCM2_DAI_PCM_LOOPBACK_MASK_SFT
- PCM2_DAI_PCM_LOOPBACK_SFT
- PCM2_EN_MASK
- PCM2_EN_MASK_SFT
- PCM2_EN_SFT
- PCM2_FIX_VALUE_SEL_MASK
- PCM2_FIX_VALUE_SEL_MASK_SFT
- PCM2_FIX_VALUE_SEL_SFT
- PCM2_FMT_MASK
- PCM2_FMT_MASK_SFT
- PCM2_FMT_SFT
- PCM2_I2S_PCM_LOOPBACK_MASK
- PCM2_I2S_PCM_LOOPBACK_MASK_SFT
- PCM2_I2S_PCM_LOOPBACK_SFT
- PCM2_INTF_CON
- PCM2_LOOPBACK_CH_SEL_MASK
- PCM2_LOOPBACK_CH_SEL_MASK_SFT
- PCM2_LOOPBACK_CH_SEL_SFT
- PCM2_MODE_MASK
- PCM2_MODE_MASK_SFT
- PCM2_MODE_SFT
- PCM2_PARALLEL_LOOPBACK_MASK
- PCM2_PARALLEL_LOOPBACK_MASK_SFT
- PCM2_PARALLEL_LOOPBACK_SFT
- PCM2_RX_FIFO_OV_MASK
- PCM2_RX_FIFO_OV_MASK_SFT
- PCM2_RX_FIFO_OV_SFT
- PCM2_SERIAL_LOOPBACK_MASK
- PCM2_SERIAL_LOOPBACK_MASK_SFT
- PCM2_SERIAL_LOOPBACK_SFT
- PCM2_SYNC_DELSEL_MASK
- PCM2_SYNC_DELSEL_MASK_SFT
- PCM2_SYNC_DELSEL_SFT
- PCM2_SYNC_GLITCH_MASK
- PCM2_SYNC_GLITCH_MASK_SFT
- PCM2_SYNC_GLITCH_SFT
- PCM2_SYNC_IN_INV_MASK
- PCM2_SYNC_IN_INV_MASK_SFT
- PCM2_SYNC_IN_INV_SFT
- PCM2_TX2_BT_MODE_MASK
- PCM2_TX2_BT_MODE_MASK_SFT
- PCM2_TX2_BT_MODE_SFT
- PCM2_TX_FIFO_OV_MASK
- PCM2_TX_FIFO_OV_MASK_SFT
- PCM2_TX_FIFO_OV_SFT
- PCM2_TX_FIX_VALUE_MASK
- PCM2_TX_FIX_VALUE_MASK_SFT
- PCM2_TX_FIX_VALUE_SFT
- PCM2_TX_LCH_RPT_MASK
- PCM2_TX_LCH_RPT_MASK_SFT
- PCM2_TX_LCH_RPT_SFT
- PCM2_TX_LR_SWAP_MASK
- PCM2_TX_LR_SWAP_MASK_SFT
- PCM2_TX_LR_SWAP_SFT
- PCM2_VBT_16K_MODE_MASK
- PCM2_VBT_16K_MODE_MASK_SFT
- PCM2_VBT_16K_MODE_SFT
- PCM2_WLEN_MASK
- PCM2_WLEN_MASK_SFT
- PCM2_WLEN_SFT
- PCM3008_RATES
- PCM3060_CLK1
- PCM3060_CLK2
- PCM3060_CLK_DEF
- PCM3060_DAI_IDS_NUM
- PCM3060_DAI_ID_ADC
- PCM3060_DAI_ID_DAC
- PCM3060_DAI_RATES_ADC
- PCM3060_DAI_RATES_DAC
- PCM3060_REG64
- PCM3060_REG65
- PCM3060_REG66
- PCM3060_REG67
- PCM3060_REG68
- PCM3060_REG69
- PCM3060_REG70
- PCM3060_REG71
- PCM3060_REG72
- PCM3060_REG73
- PCM3060_REG_ADPSV
- PCM3060_REG_AT1_MAX
- PCM3060_REG_AT1_MIN
- PCM3060_REG_AT2_MAX
- PCM3060_REG_AT2_MIN
- PCM3060_REG_AZRO
- PCM3060_REG_BYP
- PCM3060_REG_CSEL
- PCM3060_REG_DAPSV
- PCM3060_REG_DMC
- PCM3060_REG_DREV1
- PCM3060_REG_DREV2
- PCM3060_REG_FLT
- PCM3060_REG_FMT_I2S
- PCM3060_REG_FMT_LJ
- PCM3060_REG_FMT_RJ
- PCM3060_REG_MASK_DMF
- PCM3060_REG_MASK_FMT
- PCM3060_REG_MASK_MS
- PCM3060_REG_MRST
- PCM3060_REG_MS_M128
- PCM3060_REG_MS_M192
- PCM3060_REG_MS_M256
- PCM3060_REG_MS_M384
- PCM3060_REG_MS_M512
- PCM3060_REG_MS_M768
- PCM3060_REG_MS_S
- PCM3060_REG_OVER
- PCM3060_REG_SE
- PCM3060_REG_SHIFT_ADPSV
- PCM3060_REG_SHIFT_DAPSV
- PCM3060_REG_SHIFT_MUT11
- PCM3060_REG_SHIFT_MUT12
- PCM3060_REG_SHIFT_MUT21
- PCM3060_REG_SHIFT_MUT22
- PCM3060_REG_SRST
- PCM3060_REG_ZCDD
- PCM3060_REG_ZREV
- PCM3168A_ADC_ATMDAD_MASK
- PCM3168A_ADC_ATMDAD_SHIFT
- PCM3168A_ADC_ATSPAD_MASK
- PCM3168A_ADC_ATSPAD_SHIFT
- PCM3168A_ADC_ATT_OVF
- PCM3168A_ADC_BYP_MASK
- PCM3168A_ADC_BYP_SHIFT
- PCM3168A_ADC_FMTAD_MASK
- PCM3168A_ADC_FMTAD_SHIFT
- PCM3168A_ADC_INV
- PCM3168A_ADC_MSAD_MASK
- PCM3168A_ADC_MSAD_SHIFT
- PCM3168A_ADC_MST_FMT
- PCM3168A_ADC_MUTE
- PCM3168A_ADC_OV
- PCM3168A_ADC_OVFP_MASK
- PCM3168A_ADC_OVFP_SHIFT
- PCM3168A_ADC_PSVAD_MASK
- PCM3168A_ADC_PSVAD_SHIFT
- PCM3168A_ADC_PWR_HPFB
- PCM3168A_ADC_SEAD
- PCM3168A_ADC_SMODE
- PCM3168A_ADC_SRAD_MASK
- PCM3168A_ADC_SRAD_SHIFT
- PCM3168A_ADC_VOL_CHAN_START
- PCM3168A_ADC_VOL_MASTER
- PCM3168A_DAC_ATMDDA_MASK
- PCM3168A_DAC_ATMDDA_SHIFT
- PCM3168A_DAC_ATSPDA_MASK
- PCM3168A_DAC_ATSPDA_SHIFT
- PCM3168A_DAC_ATT_DEMP_ZF
- PCM3168A_DAC_AZRO_MASK
- PCM3168A_DAC_AZRO_SHIFT
- PCM3168A_DAC_DEMP_MASK
- PCM3168A_DAC_DEMP_SHIFT
- PCM3168A_DAC_FLT_MASK
- PCM3168A_DAC_FLT_SHIFT
- PCM3168A_DAC_FMT_MASK
- PCM3168A_DAC_FMT_SHIFT
- PCM3168A_DAC_INV
- PCM3168A_DAC_MSDA_MASK
- PCM3168A_DAC_MSDA_SHIFT
- PCM3168A_DAC_MUTE
- PCM3168A_DAC_OPEDA_MASK
- PCM3168A_DAC_OPEDA_SHIFT
- PCM3168A_DAC_OP_FLT
- PCM3168A_DAC_PSMDA_MASK
- PCM3168A_DAC_PSMDA_SHIFT
- PCM3168A_DAC_PWR_MST_FMT
- PCM3168A_DAC_SRDA_MASK
- PCM3168A_DAC_SRDA_SHIFT
- PCM3168A_DAC_VOL_CHAN_START
- PCM3168A_DAC_VOL_MASTER
- PCM3168A_DAC_ZERO
- PCM3168A_DAC_ZREV_MASK
- PCM3168A_DAC_ZREV_SHIFT
- PCM3168A_DAI_ADC
- PCM3168A_DAI_DAC
- PCM3168A_FMT_DSP_A
- PCM3168A_FMT_DSP_B
- PCM3168A_FMT_DSP_MASK
- PCM3168A_FMT_I2S
- PCM3168A_FMT_I2S_TDM
- PCM3168A_FMT_LEFT_J
- PCM3168A_FMT_LEFT_J_TDM
- PCM3168A_FMT_RIGHT_J
- PCM3168A_FMT_RIGHT_J_16
- PCM3168A_FORMATS
- PCM3168A_MAX_SYSCLK
- PCM3168A_MRST_MASK
- PCM3168A_NUM_SCKI_RATIOS_ADC
- PCM3168A_NUM_SCKI_RATIOS_DAC
- PCM3168A_NUM_SUPPLIES
- PCM3168A_RST_SMODE
- PCM3168A_SRST_MASK
- PCM3724_8255_0_BASE
- PCM3724_8255_1_BASE
- PCM3724_DIO_DIR_A0_OUT
- PCM3724_DIO_DIR_A1_OUT
- PCM3724_DIO_DIR_B0_OUT
- PCM3724_DIO_DIR_B1_OUT
- PCM3724_DIO_DIR_C0_OUT
- PCM3724_DIO_DIR_C1_OUT
- PCM3724_DIO_DIR_REG
- PCM3724_GATE_CTRL_A0_ENA
- PCM3724_GATE_CTRL_A1_ENA
- PCM3724_GATE_CTRL_B0_ENA
- PCM3724_GATE_CTRL_B1_ENA
- PCM3724_GATE_CTRL_C0_ENA
- PCM3724_GATE_CTRL_C1_ENA
- PCM3724_GATE_CTRL_REG
- PCM512x_ACTL_SHIFT
- PCM512x_AFMT
- PCM512x_AFMT_DSP
- PCM512x_AFMT_I2S
- PCM512x_AFMT_LTJ
- PCM512x_AFMT_RTJ
- PCM512x_AFMT_SHIFT
- PCM512x_AGBL_SHIFT
- PCM512x_AGBR_SHIFT
- PCM512x_ALEN
- PCM512x_ALEN_16
- PCM512x_ALEN_20
- PCM512x_ALEN_24
- PCM512x_ALEN_32
- PCM512x_ALEN_SHIFT
- PCM512x_AMLE_SHIFT
- PCM512x_AMRE_SHIFT
- PCM512x_ANALOG_GAIN_BOOST
- PCM512x_ANALOG_GAIN_CTRL
- PCM512x_ANALOG_MUTE_CTRL
- PCM512x_ANALOG_MUTE_DET
- PCM512x_ATML_SHIFT
- PCM512x_ATMR_SHIFT
- PCM512x_AUPL_SHIFT
- PCM512x_AUPR_SHIFT
- PCM512x_AUTO_MUTE
- PCM512x_BCKO
- PCM512x_BCKO_SHIFT
- PCM512x_BCKP
- PCM512x_BCKP_SHIFT
- PCM512x_BCLK_LRCLK_CFG
- PCM512x_CLKDET
- PCM512x_CLOCK_STATUS
- PCM512x_CRAM_CTRL
- PCM512x_DAC_CLKDIV
- PCM512x_DAC_REF
- PCM512x_DAC_ROUTING
- PCM512x_DCAS
- PCM512x_DEMP
- PCM512x_DEMP_SHIFT
- PCM512x_DIGITAL_MUTE_1
- PCM512x_DIGITAL_MUTE_2
- PCM512x_DIGITAL_MUTE_3
- PCM512x_DIGITAL_MUTE_DET
- PCM512x_DIGITAL_VOLUME_1
- PCM512x_DIGITAL_VOLUME_2
- PCM512x_DIGITAL_VOLUME_3
- PCM512x_DSP
- PCM512x_DSP_CLKDIV
- PCM512x_DSP_GPIO_INPUT
- PCM512x_DSP_PROGRAM
- PCM512x_ERROR_DETECT
- PCM512x_FLEX_A
- PCM512x_FLEX_B
- PCM512x_FSSP
- PCM512x_FSSP_192KHZ
- PCM512x_FSSP_384KHZ
- PCM512x_FSSP_48KHZ
- PCM512x_FSSP_96KHZ
- PCM512x_FSSP_SHIFT
- PCM512x_FS_SPEED_MODE
- PCM512x_G1OE
- PCM512x_G2OE
- PCM512x_G3OE
- PCM512x_G4OE
- PCM512x_G5OE
- PCM512x_G6OE
- PCM512x_GPIN
- PCM512x_GPIO_CONTROL_1
- PCM512x_GPIO_CONTROL_2
- PCM512x_GPIO_DACIN
- PCM512x_GPIO_EN
- PCM512x_GPIO_OUTPUT_1
- PCM512x_GPIO_OUTPUT_2
- PCM512x_GPIO_OUTPUT_3
- PCM512x_GPIO_OUTPUT_4
- PCM512x_GPIO_OUTPUT_5
- PCM512x_GPIO_OUTPUT_6
- PCM512x_GPIO_PLLIN
- PCM512x_GREF
- PCM512x_GREF_GPIO1
- PCM512x_GREF_GPIO2
- PCM512x_GREF_GPIO3
- PCM512x_GREF_GPIO4
- PCM512x_GREF_GPIO5
- PCM512x_GREF_GPIO6
- PCM512x_GREF_SHIFT
- PCM512x_GxSL
- PCM512x_GxSL_AMUTB
- PCM512x_GxSL_AMUTL
- PCM512x_GxSL_AMUTR
- PCM512x_GxSL_ANMUL
- PCM512x_GxSL_ANMUR
- PCM512x_GxSL_CLKI
- PCM512x_GxSL_CPCLK
- PCM512x_GxSL_DSP
- PCM512x_GxSL_OFF
- PCM512x_GxSL_PLLCK
- PCM512x_GxSL_PLLLK
- PCM512x_GxSL_REG
- PCM512x_GxSL_SDOUT
- PCM512x_GxSL_SHIFT
- PCM512x_GxSL_UV0_3
- PCM512x_GxSL_UV0_7
- PCM512x_I2S_1
- PCM512x_I2S_2
- PCM512x_IDAC_1
- PCM512x_IDAC_2
- PCM512x_IDBK
- PCM512x_IDCH
- PCM512x_IDCM
- PCM512x_IDFS
- PCM512x_IDSK
- PCM512x_IPLK
- PCM512x_LAGN_SHIFT
- PCM512x_LRKO
- PCM512x_LRKO_SHIFT
- PCM512x_MASTER_CLKDIV_1
- PCM512x_MASTER_CLKDIV_2
- PCM512x_MASTER_MODE
- PCM512x_MAX_REGISTER
- PCM512x_MUTE
- PCM512x_NCP_CLKDIV
- PCM512x_NUM_SUPPLIES
- PCM512x_OSR_CLKDIV
- PCM512x_OUTPUT_AMPLITUDE
- PCM512x_OVERFLOW
- PCM512x_PAGE
- PCM512x_PAGE_BASE
- PCM512x_PAGE_LEN
- PCM512x_PLCK
- PCM512x_PLCK_SHIFT
- PCM512x_PLLE
- PCM512x_PLLE_SHIFT
- PCM512x_PLL_COEFF_0
- PCM512x_PLL_COEFF_1
- PCM512x_PLL_COEFF_2
- PCM512x_PLL_COEFF_3
- PCM512x_PLL_COEFF_4
- PCM512x_PLL_EN
- PCM512x_PLL_REF
- PCM512x_POWER
- PCM512x_RAGN_SHIFT
- PCM512x_RATE_DET_1
- PCM512x_RATE_DET_2
- PCM512x_RATE_DET_3
- PCM512x_RATE_DET_4
- PCM512x_RBCK
- PCM512x_RBCK_SHIFT
- PCM512x_REGULATOR_EVENT
- PCM512x_RESET
- PCM512x_RLRK
- PCM512x_RLRK_SHIFT
- PCM512x_RQML
- PCM512x_RQML_SHIFT
- PCM512x_RQMR
- PCM512x_RQMR_SHIFT
- PCM512x_RQPD
- PCM512x_RQPD_SHIFT
- PCM512x_RQST
- PCM512x_RQST_SHIFT
- PCM512x_RQSY
- PCM512x_RQSY_HALT
- PCM512x_RQSY_RESUME
- PCM512x_RSTM
- PCM512x_RSTR
- PCM512x_SDAC
- PCM512x_SDAC_BCK
- PCM512x_SDAC_GPIO
- PCM512x_SDAC_MCK
- PCM512x_SDAC_PLL
- PCM512x_SDAC_SCK
- PCM512x_SDAC_SHIFT
- PCM512x_SDSL
- PCM512x_SDSL_SHIFT
- PCM512x_SPI_MISO_FUNCTION
- PCM512x_SREF
- PCM512x_SREF_BCK
- PCM512x_SREF_GPIO
- PCM512x_SREF_SCK
- PCM512x_SREF_SHIFT
- PCM512x_SYNCHRONIZE
- PCM512x_UNDERVOLTAGE_PROT
- PCM512x_VCOM_CTRL_1
- PCM512x_VCOM_CTRL_2
- PCM512x_VEDF_SHIFT
- PCM512x_VEDS_SHIFT
- PCM512x_VIRT_BASE
- PCM512x_VNDF_SHIFT
- PCM512x_VNDS_SHIFT
- PCM512x_VNUF_SHIFT
- PCM512x_VNUS_SHIFT
- PCM990_AC97_IRQ
- PCM990_AC97_IRQ_EDGE
- PCM990_AC97_IRQ_GPIO
- PCM990_CF_CD
- PCM990_CF_CD_EDGE
- PCM990_CF_CD_GPIO
- PCM990_CF_IRQ
- PCM990_CF_IRQ_EDGE
- PCM990_CF_IRQ_GPIO
- PCM990_CF_PLD_PHYS
- PCM990_CF_PLD_REG0
- PCM990_CF_PLD_REG1
- PCM990_CF_PLD_REG2
- PCM990_CF_PLD_REG3
- PCM990_CF_PLD_REG4
- PCM990_CF_PLD_REG5
- PCM990_CF_PLD_REG6
- PCM990_CF_REG0_BLK
- PCM990_CF_REG0_LED
- PCM990_CF_REG0_PM5V
- PCM990_CF_REG0_STBY
- PCM990_CF_REG1_CF0
- PCM990_CF_REG1_IDEMODE
- PCM990_CF_REG2_RDY
- PCM990_CF_REG2_RDYENA
- PCM990_CF_REG2_RES
- PCM990_CF_REG3_CFCD
- PCM990_CF_REG3_CFIN
- PCM990_CF_REG3_CFOE
- PCM990_CF_REG3_CFON
- PCM990_CF_REG4_3B
- PCM990_CF_REG4_5_3V
- PCM990_CF_REG4_PWG
- PCM990_CF_REG4_PWRENA
- PCM990_CF_REG5_BVD1
- PCM990_CF_REG5_BVD2
- PCM990_CF_REG5_VS1
- PCM990_CF_REG5_VS2
- PCM990_CF_REG6_CD1
- PCM990_CF_REG6_CD2
- PCM990_CTRL_5VOFF
- PCM990_CTRL_AC97ENA
- PCM990_CTRL_ACALARM
- PCM990_CTRL_ACENA
- PCM990_CTRL_ACPRES
- PCM990_CTRL_ACSEL
- PCM990_CTRL_BTRX
- PCM990_CTRL_BTSD
- PCM990_CTRL_CANPWR
- PCM990_CTRL_ENAINT0
- PCM990_CTRL_ENAINT1
- PCM990_CTRL_ENAINT2
- PCM990_CTRL_ENAINT3
- PCM990_CTRL_FFRI
- PCM990_CTRL_FFSD
- PCM990_CTRL_FLDIS
- PCM990_CTRL_FLWP
- PCM990_CTRL_GPSENA
- PCM990_CTRL_GPSPWR
- PCM990_CTRL_INTC0
- PCM990_CTRL_INTC1
- PCM990_CTRL_INTC2
- PCM990_CTRL_INTC3
- PCM990_CTRL_INTMSKENA
- PCM990_CTRL_INTSETCLR
- PCM990_CTRL_INT_IRQ
- PCM990_CTRL_INT_IRQ_EDGE
- PCM990_CTRL_INT_IRQ_GPIO
- PCM990_CTRL_LCDON
- PCM990_CTRL_LCDPOS1
- PCM990_CTRL_LCDPOS2
- PCM990_CTRL_LCDPWR
- PCM990_CTRL_LEDBAS
- PCM990_CTRL_LEDPWR
- PCM990_CTRL_LEDUSR
- PCM990_CTRL_MMC1PWR
- PCM990_CTRL_MMC2DE
- PCM990_CTRL_MMC2LED
- PCM990_CTRL_MMC2PWR
- PCM990_CTRL_MMC2WP
- PCM990_CTRL_PHYS
- PCM990_CTRL_PM_5V
- PCM990_CTRL_PWR_IRQ
- PCM990_CTRL_PWR_IRQ_EDGE
- PCM990_CTRL_PWR_IRQ_GPIO
- PCM990_CTRL_REG0
- PCM990_CTRL_REG1
- PCM990_CTRL_REG10
- PCM990_CTRL_REG11
- PCM990_CTRL_REG2
- PCM990_CTRL_REG3
- PCM990_CTRL_REG4
- PCM990_CTRL_REG5
- PCM990_CTRL_REG8
- PCM990_CTRL_REG9
- PCM990_CTRL_RESGPIO
- PCM990_CTRL_RESOUT
- PCM990_CTRL_SIZE
- PCM990_CTRL_SYSRES
- PCM990_IDE_5V
- PCM990_IDE_DMA1_0
- PCM990_IDE_DMAENA
- PCM990_IDE_IDEIN
- PCM990_IDE_IDEMODE
- PCM990_IDE_IDEOE
- PCM990_IDE_IDEON
- PCM990_IDE_IRQ
- PCM990_IDE_IRQ_EDGE
- PCM990_IDE_IRQ_GPIO
- PCM990_IDE_PLD_BASE
- PCM990_IDE_PLD_P2V
- PCM990_IDE_PLD_PHYS
- PCM990_IDE_PLD_REG0
- PCM990_IDE_PLD_REG1
- PCM990_IDE_PLD_REG2
- PCM990_IDE_PLD_REG3
- PCM990_IDE_PLD_REG4
- PCM990_IDE_PLD_SIZE
- PCM990_IDE_PLD_V2P
- PCM990_IDE_PM5V
- PCM990_IDE_PWG
- PCM990_IDE_PWRENA
- PCM990_IDE_RDY
- PCM990_IDE_RES
- PCM990_IDE_RESENA
- PCM990_IDE_STBY
- PCM990_MMC0_IRQ
- PCM990_MMC0_IRQ_EDGE
- PCM990_MMC0_IRQ_GPIO
- PCM990_USB_OVERCURRENT
- PCM990_USB_PWR_EN
- PCMAD_CONVERT
- PCMAD_LSB
- PCMAD_MSB
- PCMAD_STATUS
- PCMCIA0AttrSp
- PCMCIA0IOSp
- PCMCIA0MemSp
- PCMCIA0Sp
- PCMCIA1AttrSp
- PCMCIA1IOSp
- PCMCIA1MemSp
- PCMCIA1Sp
- PCMCIAAttrSp
- PCMCIAIOSp
- PCMCIAMemSp
- PCMCIAPrtSp
- PCMCIASp
- PCMCIA_0V
- PCMCIA_12V
- PCMCIA_5V
- PCMCIA_ATA
- PCMCIA_ATTR16
- PCMCIA_ATTR8
- PCMCIA_BUFF_DIS
- PCMCIA_BUS
- PCMCIA_BVD1
- PCMCIA_BVD2
- PCMCIA_C1_CBIDSEL_MASK
- PCMCIA_C1_CBIDSEL_SHIFT
- PCMCIA_C1_CD1_MASK
- PCMCIA_C1_CD2_MASK
- PCMCIA_C1_EN_CARDBUS_MASK
- PCMCIA_C1_EN_PCMCIA_GPIO_MASK
- PCMCIA_C1_EN_PCMCIA_MASK
- PCMCIA_C1_REG
- PCMCIA_C1_RESET_MASK
- PCMCIA_C1_VS1OE_MASK
- PCMCIA_C1_VS1_MASK
- PCMCIA_C1_VS2OE_MASK
- PCMCIA_C1_VS2_MASK
- PCMCIA_C2_BYTESWAP_MASK
- PCMCIA_C2_DATA16_MASK
- PCMCIA_C2_HOLD_MASK
- PCMCIA_C2_HOLD_SHIFT
- PCMCIA_C2_INACTIVE_MASK
- PCMCIA_C2_INACTIVE_SHIFT
- PCMCIA_C2_REG
- PCMCIA_C2_RWCOUNT_MASK
- PCMCIA_C2_RWCOUNT_SHIFT
- PCMCIA_C2_SETUP_MASK
- PCMCIA_C2_SETUP_SHIFT
- PCMCIA_COMM16
- PCMCIA_COMM8
- PCMCIA_CS
- PCMCIA_DEVICE_CIS_MANF_CARD
- PCMCIA_DEVICE_CIS_PROD_ID12
- PCMCIA_DEVICE_CIS_PROD_ID123
- PCMCIA_DEVICE_CIS_PROD_ID2
- PCMCIA_DEVICE_FUNC_ID
- PCMCIA_DEVICE_MANF_CARD
- PCMCIA_DEVICE_MANF_CARD_INFO
- PCMCIA_DEVICE_MANF_CARD_PROD_ID1
- PCMCIA_DEVICE_MANF_CARD_PROD_ID3
- PCMCIA_DEVICE_NULL
- PCMCIA_DEVICE_PROD_ID1
- PCMCIA_DEVICE_PROD_ID12
- PCMCIA_DEVICE_PROD_ID123
- PCMCIA_DEVICE_PROD_ID1234
- PCMCIA_DEVICE_PROD_ID124
- PCMCIA_DEVICE_PROD_ID12_INFO
- PCMCIA_DEVICE_PROD_ID13
- PCMCIA_DEVICE_PROD_ID134
- PCMCIA_DEVICE_PROD_ID14
- PCMCIA_DEVICE_PROD_ID2
- PCMCIA_DEVICE_PROD_ID3
- PCMCIA_DEV_ID_MATCH_ANONYMOUS
- PCMCIA_DEV_ID_MATCH_CARD_ID
- PCMCIA_DEV_ID_MATCH_DEVICE_NO
- PCMCIA_DEV_ID_MATCH_FAKE_CIS
- PCMCIA_DEV_ID_MATCH_FUNCTION
- PCMCIA_DEV_ID_MATCH_FUNC_ID
- PCMCIA_DEV_ID_MATCH_MANF_ID
- PCMCIA_DEV_ID_MATCH_PROD_ID1
- PCMCIA_DEV_ID_MATCH_PROD_ID2
- PCMCIA_DEV_ID_MATCH_PROD_ID3
- PCMCIA_DEV_ID_MATCH_PROD_ID4
- PCMCIA_INSERTED
- PCMCIA_IO16
- PCMCIA_IO8
- PCMCIA_IODYN
- PCMCIA_IOMEM_0
- PCMCIA_IOMEM_1
- PCMCIA_IOMEM_2
- PCMCIA_IOMEM_3
- PCMCIA_IOPORT_0
- PCMCIA_IOPORT_1
- PCMCIA_MFC_DEVICE_CIS_MANF_CARD
- PCMCIA_MFC_DEVICE_CIS_PROD_ID12
- PCMCIA_MFC_DEVICE_CIS_PROD_ID4
- PCMCIA_MFC_DEVICE_MANF_CARD
- PCMCIA_MFC_DEVICE_PROD_ID1
- PCMCIA_MFC_DEVICE_PROD_ID12
- PCMCIA_MFC_DEVICE_PROD_ID123
- PCMCIA_MFC_DEVICE_PROD_ID13
- PCMCIA_MFC_DEVICE_PROD_ID2
- PCMCIA_NUM_RESOURCES
- PCMCIA_PFC_DEVICE_CIS_PROD_ID12
- PCMCIA_PFC_DEVICE_MANF_CARD
- PCMCIA_PFC_DEVICE_PROD_ID1
- PCMCIA_PFC_DEVICE_PROD_ID12
- PCMCIA_PFC_DEVICE_PROD_ID123
- PCMCIA_PFC_DEVICE_PROD_ID13
- PCMCIA_PFC_DEVICE_PROD_ID2
- PCMCIA_PHYS
- PCMCIA_RESET
- PCMCIA_S0_CD_VALID
- PCMCIA_S0_CD_VALID_EDGE
- PCMCIA_S0_RDYINT
- PCMCIA_S1_CD_VALID
- PCMCIA_S1_CD_VALID_EDGE
- PCMCIA_S1_RDYINT
- PCMCIA_SHORT
- PCMCIA_SOCKET_CLASS_PM_OPS
- PCMCIA_SPEED_100NS
- PCMCIA_SPEED_150NS
- PCMCIA_SPEED_250NS
- PCMCIA_SPEED_720NS
- PCMCIA_UEVENT_EJECT
- PCMCIA_UEVENT_INSERT
- PCMCIA_UEVENT_REQUERY
- PCMCIA_UEVENT_RESUME
- PCMCIA_UEVENT_SUSPEND
- PCMCIA_VS1
- PCMCIA_VS2
- PCMD
- PCMD0
- PCMD1
- PCMD10
- PCMD11
- PCMD12
- PCMD13
- PCMD14
- PCMD15
- PCMD16
- PCMD17
- PCMD18
- PCMD19
- PCMD2
- PCMD20
- PCMD21
- PCMD22
- PCMD23
- PCMD24
- PCMD25
- PCMD26
- PCMD27
- PCMD28
- PCMD29
- PCMD3
- PCMD30
- PCMD31
- PCMD4
- PCMD5
- PCMD6
- PCMD7
- PCMD8
- PCMD9
- PCMD_DCE
- PCMD_ENA
- PCMD_LC
- PCMD_LEN_OVFL0_F
- PCMD_LEN_OVFL0_S
- PCMD_LEN_OVFL0_V
- PCMD_LEN_OVFL1_F
- PCMD_LEN_OVFL1_S
- PCMD_LEN_OVFL1_V
- PCMD_LEN_OVFL2_F
- PCMD_LEN_OVFL2_S
- PCMD_LEN_OVFL2_V
- PCMD_MBC
- PCMD_SQC
- PCMIDI_CHANNEL_MAX
- PCMIDI_CHANNEL_MIN
- PCMIDI_MIDDLE_C
- PCMIDI_OCTAVE_MAX
- PCMIDI_OCTAVE_MIN
- PCMIDI_SUSTAINED_MAX
- PCMIDI_SUSTAIN_MAX
- PCMIDI_SUSTAIN_MIN
- PCMIN
- PCMIN_B_MIX
- PCMMIO_AI_2ND_ADC_OFFSET
- PCMMIO_AI_CMD_CHAN_SEL
- PCMMIO_AI_CMD_ODD_CHAN
- PCMMIO_AI_CMD_RANGE
- PCMMIO_AI_CMD_REG
- PCMMIO_AI_CMD_SE
- PCMMIO_AI_LSB_REG
- PCMMIO_AI_MSB_REG
- PCMMIO_AI_RES_ENA_AI_RES_ACCESS
- PCMMIO_AI_RES_ENA_CMD_REG_ACCESS
- PCMMIO_AI_RES_ENA_DIO_RES_ACCESS
- PCMMIO_AI_RES_ENA_REG
- PCMMIO_AI_STATUS_CMD_DMA_PEND
- PCMMIO_AI_STATUS_CMD_DRQ_ENA
- PCMMIO_AI_STATUS_DATA_DMA_PEND
- PCMMIO_AI_STATUS_DATA_DRQ_ENA
- PCMMIO_AI_STATUS_DATA_READY
- PCMMIO_AI_STATUS_IRQ_ENA
- PCMMIO_AI_STATUS_IRQ_PEND
- PCMMIO_AI_STATUS_REG
- PCMMIO_AI_STATUS_REG_SEL
- PCMMIO_AO_2ND_DAC_OFFSET
- PCMMIO_AO_CMD_CHAN_SEL
- PCMMIO_AO_CMD_CHAN_SEL_ALL
- PCMMIO_AO_CMD_NOP
- PCMMIO_AO_CMD_RD_B1_CODE
- PCMMIO_AO_CMD_RD_B1_SPAN
- PCMMIO_AO_CMD_RD_B2_CODE
- PCMMIO_AO_CMD_RD_B2_SPAN
- PCMMIO_AO_CMD_REG
- PCMMIO_AO_CMD_UPDATE
- PCMMIO_AO_CMD_UPDATE_ALL
- PCMMIO_AO_CMD_WR_CODE
- PCMMIO_AO_CMD_WR_CODE_UPDATE
- PCMMIO_AO_CMD_WR_CODE_UPDATE_ALL
- PCMMIO_AO_CMD_WR_SPAN
- PCMMIO_AO_CMD_WR_SPAN_UPDATE
- PCMMIO_AO_CMD_WR_SPAN_UPDATE_ALL
- PCMMIO_AO_LSB_REG
- PCMMIO_AO_LSB_SPAN
- PCMMIO_AO_MSB_REG
- PCMMIO_AO_RESOURCE_ENA_REG
- PCMMIO_AO_STATUS_CMD_DMA_PEND
- PCMMIO_AO_STATUS_CMD_DRQ_ENA
- PCMMIO_AO_STATUS_DATA_DMA_PEND
- PCMMIO_AO_STATUS_DATA_DRQ_ENA
- PCMMIO_AO_STATUS_DATA_READY
- PCMMIO_AO_STATUS_IRQ_ENA
- PCMMIO_AO_STATUS_IRQ_PEND
- PCMMIO_AO_STATUS_REG
- PCMMIO_AO_STATUS_REG_SEL
- PCMMIO_INT_PENDING_REG
- PCMMIO_LOCK_PORT
- PCMMIO_PAGE
- PCMMIO_PAGE_ENAB
- PCMMIO_PAGE_INT_ID
- PCMMIO_PAGE_LOCK_REG
- PCMMIO_PAGE_MASK
- PCMMIO_PAGE_POL
- PCMMIO_PAGE_REG
- PCMMIO_PORT_REG
- PCMMIO_RESOURCE_IRQ
- PCMMIO_RESOURCE_REG
- PCMOE_MARK
- PCMOE_N_MARK
- PCMOUT
- PCMR
- PCMREADER_SCB_ADDR
- PCMSERIALINII_SCB_ADDR
- PCMSERIALIN_PCM_SCB_ADDR
- PCMSERIALIN_SCB_ADDR
- PCMUIO_ASIC_IOSIZE
- PCMUIO_INT_PENDING_REG
- PCMUIO_LOCK_PORT
- PCMUIO_MAX_ASICS
- PCMUIO_PAGE
- PCMUIO_PAGE_ENAB
- PCMUIO_PAGE_INT_ID
- PCMUIO_PAGE_LOCK_REG
- PCMUIO_PAGE_MASK
- PCMUIO_PAGE_POL
- PCMUIO_PAGE_REG
- PCMUIO_PORT_REG
- PCMWE_MARK
- PCMWE_N_MARK
- PCM_0dB
- PCM_12_CAPTURE_VOLUME
- PCM_12_PLAYBACK_VOLUME
- PCM_24BIT_MASK
- PCM_24BIT_MASK_SFT
- PCM_24BIT_SFT
- PCM_34_CAPTURE_VOLUME
- PCM_34_PLAYBACK_VOLUME
- PCM_A
- PCM_AC97
- PCM_ACTIVE
- PCM_B
- PCM_BCLK_IN_INV_MASK
- PCM_BCLK_IN_INV_MASK_SFT
- PCM_BCLK_IN_INV_SFT
- PCM_BCLK_OUT_INV_MASK
- PCM_BCLK_OUT_INV_MASK_SFT
- PCM_BCLK_OUT_INV_SFT
- PCM_BT_MODE_MASK
- PCM_BT_MODE_MASK_SFT
- PCM_BT_MODE_SFT
- PCM_BUFFER_LOOPBACK_MASK
- PCM_BUFFER_LOOPBACK_MASK_SFT
- PCM_BUFFER_LOOPBACK_SFT
- PCM_BUFFER_SIZE
- PCM_BYP_ASRC_MASK
- PCM_BYP_ASRC_MASK_SFT
- PCM_BYP_ASRC_SFT
- PCM_C
- PCM_CENTER_LFE_CHANNEL
- PCM_CHANNELS
- PCM_CHANNEL_CS
- PCM_CHANNEL_FC
- PCM_CHANNEL_FL
- PCM_CHANNEL_FR
- PCM_CHANNEL_LB
- PCM_CHANNEL_LFE
- PCM_CHANNEL_LS
- PCM_CHANNEL_NULL
- PCM_CHANNEL_RB
- PCM_CHANNEL_RS
- PCM_CLK
- PCM_CLK_OUT
- PCM_CLS_OUT_BOTH
- PCM_CLS_OUT_LOCAL
- PCM_CLS_OUT_MUTE
- PCM_CLS_OUT_REMOTE
- PCM_CONNECTING
- PCM_COUNT
- PCM_DAI_PCM_LOOPBACK_MASK
- PCM_DAI_PCM_LOOPBACK_MASK_SFT
- PCM_DAI_PCM_LOOPBACK_SFT
- PCM_DATA_INVALID_DW_VAL
- PCM_DISABLED
- PCM_EDMA
- PCM_ENABLE_INPUT
- PCM_ENABLE_OUTPUT
- PCM_EN_MASK
- PCM_EN_MASK_SFT
- PCM_EN_SFT
- PCM_EXACT_I2S
- PCM_EXT_MODEM_MASK
- PCM_EXT_MODEM_MASK_SFT
- PCM_EXT_MODEM_SFT
- PCM_FIX_VALUE_SEL_MASK
- PCM_FIX_VALUE_SEL_MASK_SFT
- PCM_FIX_VALUE_SEL_SFT
- PCM_FMT_MASK
- PCM_FMT_MASK_SFT
- PCM_FMT_SFT
- PCM_FRONT_CHANNEL
- PCM_GENERAL_I2S
- PCM_H
- PCM_I2S_PCM_LOOPBACK_MASK
- PCM_I2S_PCM_LOOPBACK_MASK_SFT
- PCM_I2S_PCM_LOOPBACK_SFT
- PCM_INF2_18WL
- PCM_INF2_BCLK
- PCM_INF2_FS
- PCM_INF2_MASTER
- PCM_INTF_CON1
- PCM_INTF_CON2
- PCM_LEFT_I2S
- PCM_LONG_FS
- PCM_LR_IN_BOTH
- PCM_LR_IN_LOCAL
- PCM_LR_IN_REMOTE
- PCM_LR_OUT_BOTH
- PCM_LR_OUT_LOCAL
- PCM_LR_OUT_MUTE
- PCM_LR_OUT_REMOTE
- PCM_LR_RESERVED
- PCM_MAX_NUM_CHANNEL
- PCM_MAX_PACKET_SIZE
- PCM_MIN
- PCM_MODE_MASK
- PCM_MODE_MASK_SFT
- PCM_MODE_SET
- PCM_MODE_SFT
- PCM_MULTICH
- PCM_N_PACKETS_PER_URB
- PCM_N_URBS
- PCM_PACKET_SIZE
- PCM_PARALLEL_LOOPBACK_MASK
- PCM_PARALLEL_LOOPBACK_MASK_SFT
- PCM_PARALLEL_LOOPBACK_SFT
- PCM_PLAYBACK_DEVICE
- PCM_PLAYBACK_MUTE
- PCM_PLAYBACK_VOLUME
- PCM_READER_BUF1
- PCM_REAR_CHANNEL
- PCM_REG_CTX_RBC_ACCS
- PCM_REG_DBG_DWORD_ENABLE
- PCM_REG_DBG_FORCE_FRAME
- PCM_REG_DBG_FORCE_VALID
- PCM_REG_DBG_SELECT
- PCM_REG_DBG_SHIFT
- PCM_REG_INIT
- PCM_REG_SM_CON_CTX
- PCM_RES
- PCM_RIGHT_I2S
- PCM_RLF_OUT_BOTH
- PCM_RLF_OUT_LOCAL
- PCM_RLF_OUT_MUTE
- PCM_RLF_OUT_REMOTE
- PCM_RUNTIME_CHECK
- PCM_SDMA
- PCM_SEC_AC97
- PCM_SERIAL_LOOPBACK_MASK
- PCM_SERIAL_LOOPBACK_MASK_SFT
- PCM_SERIAL_LOOPBACK_SFT
- PCM_SHORT_FS
- PCM_SIDE_CHANNEL
- PCM_SLAVE_MASK
- PCM_SLAVE_MASK_SFT
- PCM_SLAVE_SFT
- PCM_SPDIF
- PCM_SRC
- PCM_STANDBY
- PCM_SYNC_DELSEL_MASK
- PCM_SYNC_DELSEL_MASK_SFT
- PCM_SYNC_DELSEL_SFT
- PCM_SYNC_IN_INV_MASK
- PCM_SYNC_IN_INV_MASK_SFT
- PCM_SYNC_IN_INV_SFT
- PCM_SYNC_LENGTH_MASK
- PCM_SYNC_LENGTH_MASK_SFT
- PCM_SYNC_LENGTH_SFT
- PCM_SYNC_OUT_INV_MASK
- PCM_SYNC_OUT_INV_MASK_SFT
- PCM_SYNC_OUT_INV_SFT
- PCM_SYNC_TYPE_MASK
- PCM_SYNC_TYPE_MASK_SFT
- PCM_SYNC_TYPE_SFT
- PCM_TO_AES
- PCM_TO_PCM
- PCM_TX_LCH_RPT_MASK
- PCM_TX_LCH_RPT_MASK_SFT
- PCM_TX_LCH_RPT_SFT
- PCM_TX_LR_SWAP_MASK
- PCM_TX_LR_SWAP_MASK_SFT
- PCM_TX_LR_SWAP_SFT
- PCM_UNKNOWN_CHANNEL
- PCM_USE_MD3_MASK
- PCM_USE_MD3_MASK_SFT
- PCM_USE_MD3_SFT
- PCM_VBT_16K_MODE_MASK
- PCM_VBT_16K_MODE_MASK_SFT
- PCM_VBT_16K_MODE_SFT
- PCM_VOLUME
- PCM_WLEN_MASK
- PCM_WLEN_MASK_SFT
- PCM_WLEN_SFT
- PCNET32_79C970A
- PCNET32_BLINK_TIMEOUT
- PCNET32_DMA_MASK
- PCNET32_DWIO_BDP
- PCNET32_DWIO_RAP
- PCNET32_DWIO_RDP
- PCNET32_DWIO_RESET
- PCNET32_INIT_HIGH
- PCNET32_INIT_LOW
- PCNET32_LOG_MAX_RX_BUFFERS
- PCNET32_LOG_MAX_TX_BUFFERS
- PCNET32_LOG_RX_BUFFERS
- PCNET32_LOG_TX_BUFFERS
- PCNET32_MAX_PHYS
- PCNET32_MC_FILTER
- PCNET32_MSG_DEFAULT
- PCNET32_NUM_REGS
- PCNET32_PORT_100
- PCNET32_PORT_10BT
- PCNET32_PORT_ASEL
- PCNET32_PORT_AUI
- PCNET32_PORT_FD
- PCNET32_PORT_GPSI
- PCNET32_PORT_MII
- PCNET32_PORT_PORTSEL
- PCNET32_REGS_PER_PHY
- PCNET32_TEST_LEN
- PCNET32_TOTAL_SIZE
- PCNET32_WATCHDOG_TIMEOUT
- PCNET32_WIO_BDP
- PCNET32_WIO_RAP
- PCNET32_WIO_RDP
- PCNET32_WIO_RESET
- PCNET_CMD
- PCNET_DATAPORT
- PCNET_ISA
- PCNET_ISAP
- PCNET_MISC
- PCNET_PCI
- PCNET_PCI_II
- PCNET_RDC_TIMEOUT
- PCNET_RESET
- PCNET_START_PG
- PCNET_STOP_PG
- PCNET_VLB
- PCNOC_BFDCD_CLK_SRC
- PCNOC_INT_0
- PCNOC_INT_2
- PCNOC_INT_3
- PCNOC_S_0
- PCNOC_S_1
- PCNOC_S_10
- PCNOC_S_11
- PCNOC_S_2
- PCNOC_S_3
- PCNOC_S_4
- PCNOC_S_6
- PCNOC_S_7
- PCNOC_S_8
- PCNOC_S_9
- PCODE
- PCOEX_DM_8723B_1ANT
- PCOEX_DM_8723B_2ANT
- PCOEX_STA_8723B_1ANT
- PCOEX_STA_8723B_2ANT
- PCONFDUMP
- PCONFIG
- PCONFIG_CPUID
- PCONFIG_CPUID_SUBLEAF_INVALID
- PCONFIG_CPUID_SUBLEAF_MASK
- PCONFIG_CPUID_SUBLEAF_TARGETID
- PCONFIG_LEAF_INVALID
- PCONFIG_TARGET_NR
- PCONV
- PCP
- PCPCIEN_EN
- PCPCIG_GDC_MASK
- PCPCIG_GDC_SHIFT
- PCPCIG_VL
- PCPCIR_C_MASK
- PCPCIR_C_SHIFT
- PCPCIR_RDC_MASK
- PCPCIR_RDC_SHIFT
- PCPCIR_REQ
- PCPCI_EN
- PCPDEN
- PCPDEN_ADDR
- PCPHPERRINTMSK
- PCPHPERRINTSTS
- PCPLPERRINTMSK
- PCPLPERRINTSTS
- PCPPMU_INTCLRMASK
- PCPPMU_INTENMASK
- PCPPMU_INTMASK
- PCPPMU_INTMASK_REG
- PCPPMU_INTSTATUS_REG
- PCPPMU_INT_IOB
- PCPPMU_INT_L3C
- PCPPMU_INT_MCB
- PCPPMU_INT_MCU
- PCPPMU_V3_INTCLRMASK
- PCPPMU_V3_INTENMASK
- PCPPMU_V3_INTMASK
- PCPPMU_V3_INT_IOB
- PCPPMU_V3_INT_L3C
- PCPPMU_V3_INT_MCB
- PCPPMU_V3_INT_MCU
- PCPU_BITMAP_BLOCK_BITS
- PCPU_BITMAP_BLOCK_SIZE
- PCPU_DYN_SIZE
- PCPU_EMPTY_POP_PAGES_HIGH
- PCPU_EMPTY_POP_PAGES_LOW
- PCPU_FC_AUTO
- PCPU_FC_EMBED
- PCPU_FC_NR
- PCPU_FC_PAGE
- PCPU_MIN_ALLOC_SHIFT
- PCPU_MIN_ALLOC_SIZE
- PCPU_MIN_UNIT_SIZE
- PCPU_SETUP_BUG_ON
- PCPU_SLOT_BASE_SHIFT
- PCPU_SLOT_FAIL_THRESHOLD
- PCP_DEI_MASK
- PCP_MASK
- PCP_PMU_V1
- PCP_PMU_V2
- PCP_PMU_V3
- PCP_SHIFT
- PCQ_ED_ADR
- PCQ_EMPTY
- PCQ_RD_PTR
- PCQ_ST_ADR
- PCQ_WR_PTR
- PCR
- PCRCE
- PCRELIMM_8BY2
- PCRELIMM_8BY4
- PCRIT
- PCRTC_Def
- PCRTC_Mask
- PCRTC_Read
- PCRTC_Val
- PCRTC_Write
- PCR_ACD
- PCR_ACD_SEL
- PCR_ARCH_205
- PCR_ARCH_206
- PCR_ARCH_207
- PCR_ARCH_300
- PCR_ASPM_SETTING_5260
- PCR_ASPM_SETTING_REG1
- PCR_ASPM_SETTING_REG2
- PCR_BCAST_CONN
- PCR_BPIX_1
- PCR_BPIX_12
- PCR_BPIX_16
- PCR_BPIX_18
- PCR_BPIX_2
- PCR_BPIX_4
- PCR_BPIX_8
- PCR_BRC
- PCR_BURST
- PCR_BUS16
- PCR_CCC
- PCR_CHANNEL_MASK
- PCR_CHANNEL_SHIFT
- PCR_CHNG
- PCR_CLKPOL
- PCR_COLOR
- PCR_COTE
- PCR_DATA_POLARITY_INVERT
- PCR_DCLK_EDGE_RISING
- PCR_DEV_CTRL
- PCR_DUPLEX_FULL
- PCR_ECP_CLK_ENA
- PCR_ECP_ENABLE
- PCR_EN
- PCR_END_BYTE_SWAP
- PCR_END_SEL
- PCR_ENWIN
- PCR_EPP_ENABLE
- PCR_EPP_IEEE
- PCR_FCLK_EDGE_RISING
- PCR_FFHI_8K
- PCR_FFLO_4K
- PCR_FIBER_SELECT
- PCR_FLAG
- PCR_FLMPOL
- PCR_FREQ_REQ_VALID
- PCR_FRM_PULSE_DISABLED
- PCR_FRM_SYNC_ACTIVE_HIGH
- PCR_FRM_SYNC_FALLINGEDGE
- PCR_FRM_SYNC_OUTPUT_FALLING
- PCR_FRM_SYNC_OUTPUT_RISING
- PCR_FRM_SYNC_RISINGEDGE
- PCR_HALF_CLK_RATE
- PCR_HIGH_BITS
- PCR_HILO_SELECT
- PCR_HS
- PCR_IRQ_ODRAIN
- PCR_IRQ_POLAR
- PCR_LINK_STAT
- PCR_LOW_BITS
- PCR_LPPOL
- PCR_MASK
- PCR_MATRIX
- PCR_MATRIX_CLR
- PCR_MATRIX_MASK
- PCR_MSB_ENDIAN
- PCR_MS_PMOS
- PCR_N2_HTRACE
- PCR_N2_MASK0
- PCR_N2_MASK0_SHIFT
- PCR_N2_MASK1
- PCR_N2_MASK1_SHIFT
- PCR_N2_OV0
- PCR_N2_OV1
- PCR_N2_SL0
- PCR_N2_SL0_SHIFT
- PCR_N2_SL1
- PCR_N2_SL1_SHIFT
- PCR_N2_TOE_OV0
- PCR_N2_TOE_OV1
- PCR_N4_HTRACE
- PCR_N4_MASK
- PCR_N4_MASK_SHIFT
- PCR_N4_NTC
- PCR_N4_OV
- PCR_N4_PICNHT
- PCR_N4_PICNPT
- PCR_N4_SL
- PCR_N4_SL_SHIFT
- PCR_N4_STRACE
- PCR_N4_TOE
- PCR_N4_UTRACE
- PCR_OEPOL
- PCR_ONLINE
- PCR_OSB
- PCR_P2P_CONN_MASK
- PCR_P2P_CONN_SHIFT
- PCR_PAUSE_CNT
- PCR_PBSIZ_1
- PCR_PBSIZ_2
- PCR_PBSIZ_4
- PCR_PBSIZ_8
- PCR_PCD
- PCR_PHY_CTL
- PCR_PHY_CTL2
- PCR_PIC_PRIV
- PCR_PIXPOL
- PCR_PM
- PCR_PORT_VLAN_MASK
- PCR_PR0
- PCR_PR1
- PCR_PR2
- PCR_PSEN
- PCR_PS_DA
- PCR_PS_MCAST
- PCR_RESERVED
- PCR_REVERSE_SOCKET
- PCR_REV_VS
- PCR_RUNSCA
- PCR_SCLKIDLE
- PCR_SCLK_SEL
- PCR_SETTING_REG1
- PCR_SETTING_REG2
- PCR_SETTING_REG3
- PCR_SHARP
- PCR_SNOOPACC_MASK
- PCR_SNOOPLAT_MASK
- PCR_SOF_NO_FBIT
- PCR_SPEED_FULL
- PCR_SPEED_HALF
- PCR_SPEED_MASK
- PCR_SPEED_QUARTER
- PCR_SPEED_SHIFT
- PCR_STATLAT_MASK
- PCR_STHI_8
- PCR_STLO_4
- PCR_STRACE
- PCR_SYNC_CLK_DIR_OUTPUT
- PCR_TARGET_TIME_MASK
- PCR_TFT
- PCR_TIMER_ACCESS
- PCR_TM_DIS
- PCR_TOLERANCE
- PCR_TX_56KE_BIT_0_UNUSED
- PCR_TX_56KS_56K_DATA
- PCR_TX_DATA_ENABLE
- PCR_TX_FB_HIGH_IMP
- PCR_TX_PINS_OPEN_DRAIN
- PCR_TX_UNASS_HIGH
- PCR_TX_UNASS_HIGH_IMP
- PCR_TX_V56K_HIGH
- PCR_TX_V56K_HIGH_IMP
- PCR_UTRACE
- PCR_VEC_DIS
- PCR_VOLT_REQ_VALID
- PCR_VPM
- PCR_VSX_DIS
- PCS1G_ANEG_CFG
- PCS1G_ANEG_CFG_ADV_ABILITY
- PCS1G_ANEG_CFG_ADV_ABILITY_M
- PCS1G_ANEG_CFG_ADV_ABILITY_X
- PCS1G_ANEG_CFG_ANEG_ENA
- PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT
- PCS1G_ANEG_CFG_SW_RESOLVE_ENA
- PCS1G_ANEG_NP_CFG
- PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT
- PCS1G_ANEG_NP_CFG_NP_TX
- PCS1G_ANEG_NP_CFG_NP_TX_M
- PCS1G_ANEG_NP_CFG_NP_TX_X
- PCS1G_ANEG_NP_STATUS
- PCS1G_ANEG_STATUS
- PCS1G_ANEG_STATUS_ANEG_COMPLETE
- PCS1G_ANEG_STATUS_LP_ADV_ABILITY
- PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M
- PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X
- PCS1G_ANEG_STATUS_PAGE_RX_STICKY
- PCS1G_ANEG_STATUS_PR
- PCS1G_CDET_CFG
- PCS1G_CDET_CFG_CDET_ENA
- PCS1G_CFG
- PCS1G_CFG_AN_LINK_CTRL_ENA
- PCS1G_CFG_LINK_STATUS_TYPE
- PCS1G_CFG_PCS_ENA
- PCS1G_DBG_CFG
- PCS1G_DBG_CFG_UDLT
- PCS1G_DEBUG_STATUS
- PCS1G_LB_CFG
- PCS1G_LB_CFG_GMII_PHY_LB_ENA
- PCS1G_LB_CFG_RA_ENA
- PCS1G_LB_CFG_TBI_HOST_LB_ENA
- PCS1G_LINK_DOWN_CNT
- PCS1G_LINK_STATUS
- PCS1G_LINK_STATUS_DELAY_VAR
- PCS1G_LINK_STATUS_DELAY_VAR_M
- PCS1G_LINK_STATUS_DELAY_VAR_X
- PCS1G_LINK_STATUS_LINK_STATUS
- PCS1G_LINK_STATUS_SIGNAL_DETECT
- PCS1G_LINK_STATUS_SYNC_STATUS
- PCS1G_LPI_CFG
- PCS1G_LPI_CFG_LPI_RX_WTIM
- PCS1G_LPI_CFG_LPI_RX_WTIM_M
- PCS1G_LPI_CFG_LPI_RX_WTIM_X
- PCS1G_LPI_CFG_LPI_TESTMODE
- PCS1G_LPI_CFG_QSGMII_MS_SEL
- PCS1G_LPI_CFG_RX_LPI_OUT_DIS
- PCS1G_LPI_CFG_TX_ASSERT_LPIDLE
- PCS1G_LPI_STATUS
- PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY
- PCS1G_LPI_STATUS_RX_LPI_FAIL
- PCS1G_LPI_STATUS_RX_LPI_MODE
- PCS1G_LPI_STATUS_RX_QUIET
- PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY
- PCS1G_LPI_STATUS_TX_LPI_MODE
- PCS1G_LPI_STATUS_TX_QUIET
- PCS1G_LPI_WAKE_ERROR_CNT
- PCS1G_MODE_CFG
- PCS1G_MODE_CFG_SGMII_MODE_ENA
- PCS1G_MODE_CFG_UNIDIR_MODE_ENA
- PCS1G_SD_CFG
- PCS1G_SD_CFG_SD_ENA
- PCS1G_SD_CFG_SD_POL
- PCS1G_SD_CFG_SD_SEL
- PCS1G_STICKY
- PCS1G_STICKY_LINK_DOWN_STICKY
- PCS1G_STICKY_OUT_OF_SYNC_STICKY
- PCS1G_TSTPAT_MODE_CFG
- PCS1G_TSTPAT_STATUS
- PCS1G_TSTPAT_STATUS_JTP_ERR
- PCS1G_TSTPAT_STATUS_JTP_ERR_CNT
- PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M
- PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X
- PCS1G_TSTPAT_STATUS_JTP_LOCK
- PCSCSI
- PCSDIS
- PCSEL
- PCSEL_ADDR
- PCSINT
- PCSP_BUFFER_SIZE
- PCSP_CALC_NS
- PCSP_CALC_RATE
- PCSP_DEBUG
- PCSP_DEFAULT_SDIV
- PCSP_DEFAULT_SRATE
- PCSP_DEFAULT_TREBLE
- PCSP_INDEX_INC
- PCSP_MAX_PERIODS
- PCSP_MAX_PERIOD_NS
- PCSP_MAX_PERIOD_SIZE
- PCSP_MAX_RATE__1
- PCSP_MAX_TREBLE
- PCSP_MIN_LPJ
- PCSP_MIN_PERIOD_NS
- PCSP_MIN_RATE__1
- PCSP_MIXER_CONTROL
- PCSP_PERIOD_NS
- PCSP_PM_OPS
- PCSP_RATE
- PCSP_SOUND_VERSION
- PCSR
- PCSR_CPU_CTRL_OFFSET
- PCSR_S0_BVD1
- PCSR_S0_BVD2
- PCSR_S0_DETECT
- PCSR_S0_READY
- PCSR_S0_VS1
- PCSR_S0_VS2
- PCSR_S0_WP
- PCSR_S1_BVD1
- PCSR_S1_BVD2
- PCSR_S1_DETECT
- PCSR_S1_READY
- PCSR_S1_VS1
- PCSR_S1_VS2
- PCSR_S1_WP
- PCSSR
- PCSSR_S0_SLEEP
- PCSSR_S1_SLEEP
- PCSTimeout
- PCS_10G_R_STATUS_BLK_LOCK
- PCS_10G_R_STATUS_HI_BER
- PCS_10G_R_STATUS_LINKSTAT
- PCS_10G_R_STATUS_PRBS31_ABLE
- PCS_6
- PCS_7
- PCS_ADDR_REG_OFFSET
- PCS_ANAR
- PCS_ANAR_ASYMMETRIC
- PCS_ANAR_FULL_DUPLEX
- PCS_ANAR_HALF_DUPLEX
- PCS_ANAR_NEXT_PAGE
- PCS_ANAR_PAUSE
- PCS_ANAR_REMOTE_FAULT
- PCS_ANER
- PCS_ANE_IRQ
- PCS_ANLPAR
- PCS_ANLPAR_ASYMMETRIC
- PCS_ANLPAR_FULL_DUPLEX
- PCS_ANLPAR_HALF_DUPLEX
- PCS_ANLPAR_NEXT_PAGE
- PCS_ANLPAR_PAUSE
- PCS_ANLPAR_REMOTE_FAULT
- PCS_ANLPRNP
- PCS_ANNPT
- PCS_APERTURE0_IDX__PCS_Index_MASK
- PCS_APERTURE0_IDX__PCS_Index__SHIFT
- PCS_APERTURE0_LOC__Aperture_Offset_MASK
- PCS_APERTURE0_LOC__Aperture_Offset__SHIFT
- PCS_APERTURE0_LOC__Overlay_MASK
- PCS_APERTURE0_LOC__Overlay__SHIFT
- PCS_APERTURE0_LOC__PCS_Aperture_Size_MASK
- PCS_APERTURE0_LOC__PCS_Aperture_Size__SHIFT
- PCS_APERTURE0_LOC__PCS_Indirect_MASK
- PCS_APERTURE0_LOC__PCS_Indirect__SHIFT
- PCS_APERTURE1_IDX__PCS_Index_MASK
- PCS_APERTURE1_IDX__PCS_Index__SHIFT
- PCS_APERTURE1_LOC__Aperture_Offset_MASK
- PCS_APERTURE1_LOC__Aperture_Offset__SHIFT
- PCS_APERTURE1_LOC__Overlay_MASK
- PCS_APERTURE1_LOC__Overlay__SHIFT
- PCS_APERTURE1_LOC__PCS_Aperture_Size_MASK
- PCS_APERTURE1_LOC__PCS_Aperture_Size__SHIFT
- PCS_APERTURE1_LOC__PCS_Indirect_MASK
- PCS_APERTURE1_LOC__PCS_Indirect__SHIFT
- PCS_APERTURE2_IDX__PCS_Index_MASK
- PCS_APERTURE2_IDX__PCS_Index__SHIFT
- PCS_APERTURE2_LOC__Aperture_Offset_MASK
- PCS_APERTURE2_LOC__Aperture_Offset__SHIFT
- PCS_APERTURE2_LOC__Overlay_MASK
- PCS_APERTURE2_LOC__Overlay__SHIFT
- PCS_APERTURE2_LOC__PCS_Aperture_Size_MASK
- PCS_APERTURE2_LOC__PCS_Aperture_Size__SHIFT
- PCS_APERTURE2_LOC__PCS_Indirect_MASK
- PCS_APERTURE2_LOC__PCS_Indirect__SHIFT
- PCS_APERTURE3_IDX__PCS_Index_MASK
- PCS_APERTURE3_IDX__PCS_Index__SHIFT
- PCS_APERTURE3_LOC__Aperture_Offset_MASK
- PCS_APERTURE3_LOC__Aperture_Offset__SHIFT
- PCS_APERTURE3_LOC__Overlay_MASK
- PCS_APERTURE3_LOC__Overlay__SHIFT
- PCS_APERTURE3_LOC__PCS_Aperture_Size_MASK
- PCS_APERTURE3_LOC__PCS_Aperture_Size__SHIFT
- PCS_APERTURE3_LOC__PCS_Indirect_MASK
- PCS_APERTURE3_LOC__PCS_Indirect__SHIFT
- PCS_BMCR
- PCS_BMSR
- PCS_BOOT_CODE_STARTED_LBN
- PCS_BOOT_DOWNLOAD_WAIT_LBN
- PCS_BOOT_FATAL_ERROR_LBN
- PCS_BOOT_PROGRESS_CHECKSUM
- PCS_BOOT_PROGRESS_INIT
- PCS_BOOT_PROGRESS_JUMP
- PCS_BOOT_PROGRESS_LBN
- PCS_BOOT_PROGRESS_WAIT_MDIO
- PCS_BOOT_PROGRESS_WIDTH
- PCS_BOOT_STATUS_REG
- PCS_CAPABILITIES__Number_of_Lanes_MASK
- PCS_CAPABILITIES__Number_of_Lanes__SHIFT
- PCS_CFG
- PCS_CFG_10MS_TIMER_OVERRIDE
- PCS_CFG_EN
- PCS_CFG_ENABLE
- PCS_CFG_JITTER_STUDY_MASK
- PCS_CFG_JS
- PCS_CFG_SDL
- PCS_CFG_SDO
- PCS_CFG_SD_ACTIVE_LOW
- PCS_CFG_SD_OVERRIDE
- PCS_CFG_TO
- PCS_CLK
- PCS_CLOCK_CTRL_REG
- PCS_CMD_EN
- PCS_CMD_RST
- PCS_CMD_STOP_ERR
- PCS_COMMAND_DONE_REG_OFFSET
- PCS_COMMAND_REG_OFFSET
- PCS_CONF
- PCS_CONF_10MS_TMR_OVERRIDE
- PCS_CONF_ENABLE
- PCS_CONF_JITTER_STUDY
- PCS_CONF_MASK
- PCS_CONF_SIGDET_ACTIVE_LOW
- PCS_CONF_SIGDET_OVERRIDE
- PCS_CONTEXT_LOSS_OFF
- PCS_CONTROL_1
- PCS_CTRL_PCS_RST
- PCS_DATAPATH_MODE_MII
- PCS_DATAPATH_MODE_SERDES
- PCS_DMODE
- PCS_DMODE_ESM
- PCS_DMODE_GMOE
- PCS_DMODE_MGM
- PCS_DMODE_SM
- PCS_DPATH_MODE
- PCS_DPATH_MODE_LINKUP_F_ENAB
- PCS_DPATH_MODE_MII
- PCS_DPATH_MODE_PCS
- PCS_EN_PORT_XMT_SHIFT
- PCS_EN_PORT_XMT_SHIFT2
- PCS_EN_SATA_REG_SHIFT
- PCS_ESR
- PCS_EXTENDED_CAP__Next_Capability_Pointer_MASK
- PCS_EXTENDED_CAP__Next_Capability_Pointer__SHIFT
- PCS_FEAT_IRQ
- PCS_FEAT_PINCONF
- PCS_FIS_RX_EN
- PCS_FW_BUILD_1
- PCS_FW_HEARTBEAT_REG
- PCS_FW_HEARTB_LBN
- PCS_FW_HEARTB_WIDTH
- PCS_FW_PRODUCT_CODE_1
- PCS_FW_VERSION_1
- PCS_GLOBAL_CONTROL17__refclk_div2_en1_MASK
- PCS_GLOBAL_CONTROL17__refclk_div2_en1__SHIFT
- PCS_GLOBAL_CONTROL17__refclk_range1_MASK
- PCS_GLOBAL_CONTROL17__refclk_range1__SHIFT
- PCS_GLOBAL_CONTROL18__refclk_div2_en2_MASK
- PCS_GLOBAL_CONTROL18__refclk_div2_en2__SHIFT
- PCS_GLOBAL_CONTROL18__refclk_range2_MASK
- PCS_GLOBAL_CONTROL18__refclk_range2__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_bandwidth1_MASK
- PCS_GLOBAL_CONTROL19__mplla_bandwidth1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1_MASK
- PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1_MASK
- PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_force_en1_MASK
- PCS_GLOBAL_CONTROL19__mplla_force_en1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1_MASK
- PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_multiplier1_MASK
- PCS_GLOBAL_CONTROL19__mplla_multiplier1__SHIFT
- PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1_MASK
- PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_bandwidth2_MASK
- PCS_GLOBAL_CONTROL20__mplla_bandwidth2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2_MASK
- PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2_MASK
- PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_force_en2_MASK
- PCS_GLOBAL_CONTROL20__mplla_force_en2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2_MASK
- PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_multiplier2_MASK
- PCS_GLOBAL_CONTROL20__mplla_multiplier2__SHIFT
- PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2_MASK
- PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_bandwidth1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_bandwidth1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_force_en1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_force_en1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_multiplier1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_multiplier1__SHIFT
- PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1_MASK
- PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_bandwidth2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_bandwidth2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_force_en2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_force_en2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_multiplier2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_multiplier2__SHIFT
- PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2_MASK
- PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2__SHIFT
- PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en_MASK
- PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en__SHIFT
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1_MASK
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1__SHIFT
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2_MASK
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2__SHIFT
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3_MASK
- PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3__SHIFT
- PCS_GLOBAL_CONTROL23__rxX_term_acdc_MASK
- PCS_GLOBAL_CONTROL23__rxX_term_acdc__SHIFT
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl1_MASK
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl1__SHIFT
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl2_MASK
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl2__SHIFT
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl3_MASK
- PCS_GLOBAL_CONTROL23__txX_iboost_lvl3__SHIFT
- PCS_GLOBAL_CONTROL23__txX_vboost_en1_MASK
- PCS_GLOBAL_CONTROL23__txX_vboost_en1__SHIFT
- PCS_GLOBAL_CONTROL23__txX_vboost_en2_MASK
- PCS_GLOBAL_CONTROL23__txX_vboost_en2__SHIFT
- PCS_GLOBAL_CONTROL23__txX_vboost_en3_MASK
- PCS_GLOBAL_CONTROL23__txX_vboost_en3__SHIFT
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl1_MASK
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl1__SHIFT
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl2_MASK
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl2__SHIFT
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl3_MASK
- PCS_GLOBAL_CONTROL23__tx_vboost_lvl3__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1__SHIFT
- PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1_MASK
- PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2__SHIFT
- PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2_MASK
- PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3__SHIFT
- PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3_MASK
- PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3__SHIFT
- PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1_MASK
- PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1__SHIFT
- PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1_MASK
- PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1__SHIFT
- PCS_GLOBAL_CONTROL27__rx_vref_ctrl1_MASK
- PCS_GLOBAL_CONTROL27__rx_vref_ctrl1__SHIFT
- PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2_MASK
- PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2__SHIFT
- PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2_MASK
- PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2__SHIFT
- PCS_GLOBAL_CONTROL28__rx_vref_ctrl2_MASK
- PCS_GLOBAL_CONTROL28__rx_vref_ctrl2__SHIFT
- PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3_MASK
- PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3__SHIFT
- PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3_MASK
- PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3__SHIFT
- PCS_GLOBAL_CONTROL29__rx_vref_ctrl3_MASK
- PCS_GLOBAL_CONTROL29__rx_vref_ctrl3__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue_MASK
- PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLAControlOverride_MASK
- PCS_GLOBAL_CONTROL30__MPLLAControlOverride__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate_MASK
- PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue_MASK
- PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLBControlOverride_MASK
- PCS_GLOBAL_CONTROL30__MPLLBControlOverride__SHIFT
- PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate_MASK
- PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate__SHIFT
- PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm_MASK
- PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm__SHIFT
- PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority_MASK
- PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority__SHIFT
- PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate_MASK
- PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate__SHIFT
- PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue_MASK
- PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue__SHIFT
- PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride_MASK
- PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride__SHIFT
- PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate_MASK
- PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate__SHIFT
- PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate_MASK
- PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate__SHIFT
- PCS_HAS_IRQ
- PCS_HAS_PINCONF
- PCS_HWID
- PCS_INTERRUPT
- PCS_INTERRUPT_LSTATUS
- PCS_INTR_STATUS_LINK_CHANGE
- PCS_ISTAT
- PCS_ISTAT_LSC
- PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0_MASK
- PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0__SHIFT
- PCS_LANE0_CNTRL1__rxX_los_threshold_lane0_MASK
- PCS_LANE0_CNTRL1__rxX_los_threshold_lane0__SHIFT
- PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1_MASK
- PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1__SHIFT
- PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1_MASK
- PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1__SHIFT
- PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1_MASK
- PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1__SHIFT
- PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1_MASK
- PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1__SHIFT
- PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1_MASK
- PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1__SHIFT
- PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2_MASK
- PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2__SHIFT
- PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2_MASK
- PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2__SHIFT
- PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2_MASK
- PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2__SHIFT
- PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2_MASK
- PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2__SHIFT
- PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2_MASK
- PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2__SHIFT
- PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3_MASK
- PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3__SHIFT
- PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3_MASK
- PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3__SHIFT
- PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3_MASK
- PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3__SHIFT
- PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3_MASK
- PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3__SHIFT
- PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3_MASK
- PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3__SHIFT
- PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10_MASK
- PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10__SHIFT
- PCS_LANE10_CNTRL1__rxX_los_threshold_lane10_MASK
- PCS_LANE10_CNTRL1__rxX_los_threshold_lane10__SHIFT
- PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1_MASK
- PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1__SHIFT
- PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1_MASK
- PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1__SHIFT
- PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1_MASK
- PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1__SHIFT
- PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1_MASK
- PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1__SHIFT
- PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1_MASK
- PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1__SHIFT
- PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2_MASK
- PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2__SHIFT
- PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2_MASK
- PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2__SHIFT
- PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2_MASK
- PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2__SHIFT
- PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2_MASK
- PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2__SHIFT
- PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2_MASK
- PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2__SHIFT
- PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3_MASK
- PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3__SHIFT
- PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3_MASK
- PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3__SHIFT
- PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3_MASK
- PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3__SHIFT
- PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3_MASK
- PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3__SHIFT
- PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3_MASK
- PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3__SHIFT
- PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11_MASK
- PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11__SHIFT
- PCS_LANE11_CNTRL1__rxX_los_threshold_lane11_MASK
- PCS_LANE11_CNTRL1__rxX_los_threshold_lane11__SHIFT
- PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1_MASK
- PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1__SHIFT
- PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1_MASK
- PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1__SHIFT
- PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1_MASK
- PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1__SHIFT
- PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1_MASK
- PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1__SHIFT
- PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1_MASK
- PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1__SHIFT
- PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2_MASK
- PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2__SHIFT
- PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2_MASK
- PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2__SHIFT
- PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2_MASK
- PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2__SHIFT
- PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2_MASK
- PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2__SHIFT
- PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2_MASK
- PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2__SHIFT
- PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3_MASK
- PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3__SHIFT
- PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3_MASK
- PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3__SHIFT
- PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3_MASK
- PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3__SHIFT
- PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3_MASK
- PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3__SHIFT
- PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3_MASK
- PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3__SHIFT
- PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12_MASK
- PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12__SHIFT
- PCS_LANE12_CNTRL1__rxX_los_threshold_lane12_MASK
- PCS_LANE12_CNTRL1__rxX_los_threshold_lane12__SHIFT
- PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1_MASK
- PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1__SHIFT
- PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1_MASK
- PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1__SHIFT
- PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1_MASK
- PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1__SHIFT
- PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1_MASK
- PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1__SHIFT
- PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1_MASK
- PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1__SHIFT
- PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2_MASK
- PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2__SHIFT
- PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2_MASK
- PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2__SHIFT
- PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2_MASK
- PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2__SHIFT
- PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2_MASK
- PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2__SHIFT
- PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2_MASK
- PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2__SHIFT
- PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3_MASK
- PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3__SHIFT
- PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3_MASK
- PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3__SHIFT
- PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3_MASK
- PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3__SHIFT
- PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3_MASK
- PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3__SHIFT
- PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3_MASK
- PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3__SHIFT
- PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13_MASK
- PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13__SHIFT
- PCS_LANE13_CNTRL1__rxX_los_threshold_lane13_MASK
- PCS_LANE13_CNTRL1__rxX_los_threshold_lane13__SHIFT
- PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1_MASK
- PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1__SHIFT
- PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1_MASK
- PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1__SHIFT
- PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1_MASK
- PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1__SHIFT
- PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1_MASK
- PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1__SHIFT
- PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1_MASK
- PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1__SHIFT
- PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2_MASK
- PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2__SHIFT
- PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2_MASK
- PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2__SHIFT
- PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2_MASK
- PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2__SHIFT
- PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2_MASK
- PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2__SHIFT
- PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2_MASK
- PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2__SHIFT
- PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3_MASK
- PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3__SHIFT
- PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3_MASK
- PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3__SHIFT
- PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3_MASK
- PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3__SHIFT
- PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3_MASK
- PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3__SHIFT
- PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3_MASK
- PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3__SHIFT
- PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14_MASK
- PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14__SHIFT
- PCS_LANE14_CNTRL1__rxX_los_threshold_lane14_MASK
- PCS_LANE14_CNTRL1__rxX_los_threshold_lane14__SHIFT
- PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1_MASK
- PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1__SHIFT
- PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1_MASK
- PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1__SHIFT
- PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1_MASK
- PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1__SHIFT
- PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1_MASK
- PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1__SHIFT
- PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1_MASK
- PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1__SHIFT
- PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2_MASK
- PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2__SHIFT
- PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2_MASK
- PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2__SHIFT
- PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2_MASK
- PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2__SHIFT
- PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2_MASK
- PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2__SHIFT
- PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2_MASK
- PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2__SHIFT
- PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3_MASK
- PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3__SHIFT
- PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3_MASK
- PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3__SHIFT
- PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3_MASK
- PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3__SHIFT
- PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3_MASK
- PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3__SHIFT
- PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3_MASK
- PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3__SHIFT
- PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15_MASK
- PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15__SHIFT
- PCS_LANE15_CNTRL1__rxX_los_threshold_lane15_MASK
- PCS_LANE15_CNTRL1__rxX_los_threshold_lane15__SHIFT
- PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1_MASK
- PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1__SHIFT
- PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1_MASK
- PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1__SHIFT
- PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1_MASK
- PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1__SHIFT
- PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1_MASK
- PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1__SHIFT
- PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1_MASK
- PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1__SHIFT
- PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2_MASK
- PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2__SHIFT
- PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2_MASK
- PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2__SHIFT
- PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2_MASK
- PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2__SHIFT
- PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2_MASK
- PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2__SHIFT
- PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2_MASK
- PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2__SHIFT
- PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3_MASK
- PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3__SHIFT
- PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3_MASK
- PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3__SHIFT
- PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3_MASK
- PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3__SHIFT
- PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3_MASK
- PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3__SHIFT
- PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3_MASK
- PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3__SHIFT
- PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1_MASK
- PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1__SHIFT
- PCS_LANE1_CNTRL1__rxX_los_threshold_lane1_MASK
- PCS_LANE1_CNTRL1__rxX_los_threshold_lane1__SHIFT
- PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1_MASK
- PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1__SHIFT
- PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1_MASK
- PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1__SHIFT
- PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1_MASK
- PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1__SHIFT
- PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1_MASK
- PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1__SHIFT
- PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1_MASK
- PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1__SHIFT
- PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2_MASK
- PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2__SHIFT
- PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2_MASK
- PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2__SHIFT
- PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2_MASK
- PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2__SHIFT
- PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2_MASK
- PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2__SHIFT
- PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2_MASK
- PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2__SHIFT
- PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3_MASK
- PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3__SHIFT
- PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3_MASK
- PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3__SHIFT
- PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3_MASK
- PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3__SHIFT
- PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3_MASK
- PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3__SHIFT
- PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3_MASK
- PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3__SHIFT
- PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2_MASK
- PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2__SHIFT
- PCS_LANE2_CNTRL1__rxX_los_threshold_lane2_MASK
- PCS_LANE2_CNTRL1__rxX_los_threshold_lane2__SHIFT
- PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1_MASK
- PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1__SHIFT
- PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1_MASK
- PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1__SHIFT
- PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1_MASK
- PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1__SHIFT
- PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1_MASK
- PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1__SHIFT
- PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1_MASK
- PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1__SHIFT
- PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2_MASK
- PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2__SHIFT
- PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2_MASK
- PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2__SHIFT
- PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2_MASK
- PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2__SHIFT
- PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2_MASK
- PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2__SHIFT
- PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2_MASK
- PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2__SHIFT
- PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3_MASK
- PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3__SHIFT
- PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3_MASK
- PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3__SHIFT
- PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3_MASK
- PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3__SHIFT
- PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3_MASK
- PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3__SHIFT
- PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3_MASK
- PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3__SHIFT
- PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3_MASK
- PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3__SHIFT
- PCS_LANE3_CNTRL1__rxX_los_threshold_lane3_MASK
- PCS_LANE3_CNTRL1__rxX_los_threshold_lane3__SHIFT
- PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1_MASK
- PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1__SHIFT
- PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1_MASK
- PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1__SHIFT
- PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1_MASK
- PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1__SHIFT
- PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1_MASK
- PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1__SHIFT
- PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1_MASK
- PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1__SHIFT
- PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2_MASK
- PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2__SHIFT
- PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2_MASK
- PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2__SHIFT
- PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2_MASK
- PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2__SHIFT
- PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2_MASK
- PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2__SHIFT
- PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2_MASK
- PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2__SHIFT
- PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3_MASK
- PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3__SHIFT
- PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3_MASK
- PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3__SHIFT
- PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3_MASK
- PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3__SHIFT
- PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3_MASK
- PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3__SHIFT
- PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3_MASK
- PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3__SHIFT
- PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4_MASK
- PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4__SHIFT
- PCS_LANE4_CNTRL1__rxX_los_threshold_lane4_MASK
- PCS_LANE4_CNTRL1__rxX_los_threshold_lane4__SHIFT
- PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1_MASK
- PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1__SHIFT
- PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1_MASK
- PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1__SHIFT
- PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1_MASK
- PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1__SHIFT
- PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1_MASK
- PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1__SHIFT
- PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1_MASK
- PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1__SHIFT
- PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2_MASK
- PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2__SHIFT
- PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2_MASK
- PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2__SHIFT
- PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2_MASK
- PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2__SHIFT
- PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2_MASK
- PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2__SHIFT
- PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2_MASK
- PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2__SHIFT
- PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3_MASK
- PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3__SHIFT
- PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3_MASK
- PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3__SHIFT
- PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3_MASK
- PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3__SHIFT
- PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3_MASK
- PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3__SHIFT
- PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3_MASK
- PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3__SHIFT
- PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5_MASK
- PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5__SHIFT
- PCS_LANE5_CNTRL1__rxX_los_threshold_lane5_MASK
- PCS_LANE5_CNTRL1__rxX_los_threshold_lane5__SHIFT
- PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1_MASK
- PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1__SHIFT
- PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1_MASK
- PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1__SHIFT
- PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1_MASK
- PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1__SHIFT
- PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1_MASK
- PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1__SHIFT
- PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1_MASK
- PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1__SHIFT
- PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2_MASK
- PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2__SHIFT
- PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2_MASK
- PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2__SHIFT
- PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2_MASK
- PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2__SHIFT
- PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2_MASK
- PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2__SHIFT
- PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2_MASK
- PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2__SHIFT
- PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3_MASK
- PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3__SHIFT
- PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3_MASK
- PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3__SHIFT
- PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3_MASK
- PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3__SHIFT
- PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3_MASK
- PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3__SHIFT
- PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3_MASK
- PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3__SHIFT
- PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6_MASK
- PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6__SHIFT
- PCS_LANE6_CNTRL1__rxX_los_threshold_lane6_MASK
- PCS_LANE6_CNTRL1__rxX_los_threshold_lane6__SHIFT
- PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1_MASK
- PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1__SHIFT
- PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1_MASK
- PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1__SHIFT
- PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1_MASK
- PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1__SHIFT
- PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1_MASK
- PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1__SHIFT
- PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1_MASK
- PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1__SHIFT
- PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2_MASK
- PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2__SHIFT
- PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2_MASK
- PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2__SHIFT
- PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2_MASK
- PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2__SHIFT
- PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2_MASK
- PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2__SHIFT
- PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2_MASK
- PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2__SHIFT
- PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3_MASK
- PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3__SHIFT
- PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3_MASK
- PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3__SHIFT
- PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3_MASK
- PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3__SHIFT
- PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3_MASK
- PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3__SHIFT
- PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3_MASK
- PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3__SHIFT
- PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7_MASK
- PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7__SHIFT
- PCS_LANE7_CNTRL1__rxX_los_threshold_lane7_MASK
- PCS_LANE7_CNTRL1__rxX_los_threshold_lane7__SHIFT
- PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1_MASK
- PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1__SHIFT
- PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1_MASK
- PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1__SHIFT
- PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1_MASK
- PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1__SHIFT
- PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1_MASK
- PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1__SHIFT
- PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1_MASK
- PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1__SHIFT
- PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2_MASK
- PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2__SHIFT
- PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2_MASK
- PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2__SHIFT
- PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2_MASK
- PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2__SHIFT
- PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2_MASK
- PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2__SHIFT
- PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2_MASK
- PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2__SHIFT
- PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3_MASK
- PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3__SHIFT
- PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3_MASK
- PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3__SHIFT
- PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3_MASK
- PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3__SHIFT
- PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3_MASK
- PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3__SHIFT
- PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3_MASK
- PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3__SHIFT
- PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8_MASK
- PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8__SHIFT
- PCS_LANE8_CNTRL1__rxX_los_threshold_lane8_MASK
- PCS_LANE8_CNTRL1__rxX_los_threshold_lane8__SHIFT
- PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1_MASK
- PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1__SHIFT
- PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1_MASK
- PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1__SHIFT
- PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1_MASK
- PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1__SHIFT
- PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1_MASK
- PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1__SHIFT
- PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1_MASK
- PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1__SHIFT
- PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2_MASK
- PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2__SHIFT
- PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2_MASK
- PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2__SHIFT
- PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2_MASK
- PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2__SHIFT
- PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2_MASK
- PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2__SHIFT
- PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2_MASK
- PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2__SHIFT
- PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3_MASK
- PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3__SHIFT
- PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3_MASK
- PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3__SHIFT
- PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3_MASK
- PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3__SHIFT
- PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3_MASK
- PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3__SHIFT
- PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3_MASK
- PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3__SHIFT
- PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9_MASK
- PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9__SHIFT
- PCS_LANE9_CNTRL1__rxX_los_threshold_lane9_MASK
- PCS_LANE9_CNTRL1__rxX_los_threshold_lane9__SHIFT
- PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1_MASK
- PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1__SHIFT
- PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1_MASK
- PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1__SHIFT
- PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1_MASK
- PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1__SHIFT
- PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1_MASK
- PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1__SHIFT
- PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1_MASK
- PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1__SHIFT
- PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2_MASK
- PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2__SHIFT
- PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2_MASK
- PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2__SHIFT
- PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2_MASK
- PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2__SHIFT
- PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2_MASK
- PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2__SHIFT
- PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2_MASK
- PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2__SHIFT
- PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3_MASK
- PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3__SHIFT
- PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3_MASK
- PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3__SHIFT
- PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3_MASK
- PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3__SHIFT
- PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3_MASK
- PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3__SHIFT
- PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3_MASK
- PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3__SHIFT
- PCS_LANEGRP0_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP0_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP0_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP0_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP0_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP0_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP1_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP1_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP1_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP1_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP1_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP1_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP2_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP2_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP2_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP2_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP2_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP2_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP3_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP3_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP3_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP3_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP3_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP3_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP4_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP4_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP4_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP4_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP4_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP4_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP5_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP5_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP5_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP5_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP5_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP5_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP6_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP6_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP6_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP6_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP6_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP6_MAPPING__Target_Mux_Position__SHIFT
- PCS_LANEGRP7_MAPPING__Lane_Connections_MASK
- PCS_LANEGRP7_MAPPING__Lane_Connections__SHIFT
- PCS_LANEGRP7_MAPPING__Lane_Shift_MASK
- PCS_LANEGRP7_MAPPING__Lane_Shift__SHIFT
- PCS_LANEGRP7_MAPPING__Target_Mux_Position_MASK
- PCS_LANEGRP7_MAPPING__Target_Mux_Position__SHIFT
- PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN_MASK
- PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN__SHIFT
- PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER_MASK
- PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER__SHIFT
- PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN_MASK
- PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN__SHIFT
- PCS_LCU_CNTL__PCS_LCU_POWER_GATING_MASK
- PCS_LCU_CNTL__PCS_LCU_POWER_GATING__SHIFT
- PCS_LCU_CNTL__SMU_INITIATOR_ID_MASK
- PCS_LCU_CNTL__SMU_INITIATOR_ID__SHIFT
- PCS_LCU_CNTL__SMU_UNIT_ID_MASK
- PCS_LCU_CNTL__SMU_UNIT_ID__SHIFT
- PCS_LINKX_TIMER_COUNT
- PCS_LINK_IRQ
- PCS_MIIADV
- PCS_MIIADV_ACK
- PCS_MIIADV_AP
- PCS_MIIADV_FD
- PCS_MIIADV_HD
- PCS_MIIADV_NP
- PCS_MIIADV_RF
- PCS_MIIADV_SP
- PCS_MIICTRL
- PCS_MIICTRL_ANE
- PCS_MIICTRL_CT
- PCS_MIICTRL_DM
- PCS_MIICTRL_ISO
- PCS_MIICTRL_PD
- PCS_MIICTRL_RAN
- PCS_MIICTRL_RST
- PCS_MIICTRL_SPD
- PCS_MIICTRL_SS
- PCS_MIICTRL_WB
- PCS_MIILP
- PCS_MIISTAT
- PCS_MIISTAT_ANA
- PCS_MIISTAT_ANC
- PCS_MIISTAT_EC
- PCS_MIISTAT_ES
- PCS_MIISTAT_JD
- PCS_MIISTAT_LS
- PCS_MIISTAT_RF
- PCS_MII_1000MB_SPEED
- PCS_MII_10_100_SEL
- PCS_MII_ADV
- PCS_MII_ADVERT_ACK
- PCS_MII_ADVERT_ASYM_PAUSE
- PCS_MII_ADVERT_FD
- PCS_MII_ADVERT_HD
- PCS_MII_ADVERT_NEXT_PAGE
- PCS_MII_ADVERT_RF_MASK
- PCS_MII_ADVERT_SYM_PAUSE
- PCS_MII_ADV_ACK
- PCS_MII_ADV_ASM_DIR
- PCS_MII_ADV_FULL_DUPLEX
- PCS_MII_ADV_HALF_DUPLEX
- PCS_MII_ADV_NEXT_PAGE
- PCS_MII_ADV_PAUSE
- PCS_MII_ADV_REMOTE_FAULT
- PCS_MII_AUTONEG_EN
- PCS_MII_AUTONEG_RESTART
- PCS_MII_COLL_TEST
- PCS_MII_CTL
- PCS_MII_CTL_10_100_SPEED
- PCS_MII_CTL_RST
- PCS_MII_CTRL_1000_SEL
- PCS_MII_CTRL_COLLISION_TEST
- PCS_MII_CTRL_DUPLEX
- PCS_MII_DUPLEX
- PCS_MII_ISOLATE
- PCS_MII_LPA_ACK
- PCS_MII_LPA_ASYM_PAUSE
- PCS_MII_LPA_FD
- PCS_MII_LPA_HD
- PCS_MII_LPA_NEXT_PAGE
- PCS_MII_LPA_RF_MASK
- PCS_MII_LPA_SYM_PAUSE
- PCS_MII_PARTNER
- PCS_MII_PARTNER_ACK
- PCS_MII_PARTNER_FULL_DUPLEX
- PCS_MII_PARTNER_HALF_DUPLEX
- PCS_MII_PARTNER_NEXT_PAGE
- PCS_MII_PARTNER_PAUSE
- PCS_MII_PARTNER_REMOTE_FAULT
- PCS_MII_POWER_DOWN
- PCS_MII_PWR_DOWN
- PCS_MII_RESET
- PCS_MII_RESTART_AUTONEG
- PCS_MII_STAT
- PCS_MII_STATUS_AUTONEG_ABLE
- PCS_MII_STATUS_AUTONEG_COMP
- PCS_MII_STATUS_EXTEND_CAP
- PCS_MII_STATUS_EXTEND_STATUS
- PCS_MII_STATUS_JABBER_DETECT
- PCS_MII_STATUS_LINK_STATUS
- PCS_MII_STATUS_REMOTE_FAULT
- PCS_MII_STAT_AUTONEG_ABLE
- PCS_MII_STAT_AUTONEG_DONE
- PCS_MII_STAT_EXT_CAP
- PCS_MII_STAT_EXT_STATUS
- PCS_MII_STAT_JABBER_DET
- PCS_MII_STAT_LINK_STATUS
- PCS_MII_STAT_REMOTE_FAULT
- PCS_MISC_CTL_DISP_EN
- PCS_MISC_CTL_GMX_ENO
- PCS_MISC_CTL_MODE
- PCS_MISC_CTL_SAMP_PT_MASK
- PCS_MMD_SELECT
- PCS_MRX_CTL_AN_EN
- PCS_MRX_CTL_LOOPBACK1
- PCS_MRX_CTL_PWR_DN
- PCS_MRX_CTL_RESET
- PCS_MRX_CTL_RST_AN
- PCS_MRX_STATUS_AN_CPT
- PCS_MRX_STATUS_LINK
- PCS_OFF_DISABLED
- PCS_PACKET_COUNT_RX
- PCS_PACKET_COUNT_TX
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval_MASK
- PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols_MASK
- PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance_MASK
- PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn_MASK
- PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout_MASK
- PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b_MASK
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout_MASK
- PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros_MASK
- PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings_MASK
- PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE_MASK
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK_MASK
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED_MASK
- PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5_MASK
- PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency_MASK
- PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime_MASK
- PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE_MASK
- PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE_MASK
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK_MASK
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED_MASK
- PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN_MASK
- PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT_MASK
- PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing_MASK
- PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing__SHIFT
- PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency_MASK
- PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency__SHIFT
- PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY_MASK
- PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY__SHIFT
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask__SHIFT
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating_MASK
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating__SHIFT
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity_MASK
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity__SHIFT
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber_MASK
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber__SHIFT
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask_MASK
- PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset__SHIFT
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset_MASK
- PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset__SHIFT
- PCS_PKT_CNT
- PCS_PKT_CNT_RX
- PCS_PKT_CNT_TX
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6__SHIFT
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7_MASK
- PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7__SHIFT
- PCS_QUIRK_HAS_SHARED_IRQ
- PCS_QUIRK_SHARED_IRQ
- PCS_READY
- PCS_READ_REG_OFFSET
- PCS_RGSMIIIS_IRQ
- PCS_RSP_RX_EN
- PCS_RST
- PCS_SATA_RETRY
- PCS_SATA_RETRY_2
- PCS_SCTRL
- PCS_SCTRL_EMP
- PCS_SCTRL_ESCD
- PCS_SCTRL_LOCK
- PCS_SCTRL_LOOP
- PCS_SCTRL_PDWN
- PCS_SCTRL_RXP
- PCS_SCTRL_RXZ
- PCS_SCTRL_STEST
- PCS_SCTRL_TXP
- PCS_SCTRL_TXZ
- PCS_SELF_CLEAR
- PCS_SERDES_CTRL_LOCKREF
- PCS_SERDES_CTRL_LOOPBACK
- PCS_SERDES_CTRL_SYNCD_EN
- PCS_SERDES_STATE_MASK
- PCS_SMACHINE
- PCS_SM_LINK_STATE_MASK
- PCS_SM_LOSS_LINK_C
- PCS_SM_LOSS_LINK_SYNC
- PCS_SM_LOSS_SIGNAL_DETECT
- PCS_SM_NO_LINK_BREAKLINK
- PCS_SM_NO_LINK_C
- PCS_SM_NO_LINK_NO_IDLE
- PCS_SM_NO_LINK_SERDES
- PCS_SM_NO_LINK_SYNC
- PCS_SM_NO_LINK_WAIT_C
- PCS_SM_RX_STATE_MASK
- PCS_SM_SEQ_DETECT_STATE_MASK
- PCS_SM_TX_STATE_MASK
- PCS_SM_WORD_SYNC_STATE_MASK
- PCS_SOFT_RESET__PCS_Soft_Reset_MASK
- PCS_SOFT_RESET__PCS_Soft_Reset__SHIFT
- PCS_SOFT_RST2_REG
- PCS_SOS
- PCS_SOS_PADDR
- PCS_SOS_PROM_ADDR_MASK
- PCS_SSTATE
- PCS_START
- PCS_STATE
- PCS_STATE_D_BREAKLINK_C_CODES
- PCS_STATE_D_NO_GOOD_C_CODES
- PCS_STATE_D_PARTNER_FAIL
- PCS_STATE_D_SERDES
- PCS_STATE_D_SYNC_LOSS
- PCS_STATE_D_WAIT_C_CODES_ACK
- PCS_STATE_LINK_CFG_STATE
- PCS_STATE_L_C_CODES
- PCS_STATE_L_SIGDET
- PCS_STATE_L_SYNC_LOSS
- PCS_STATE_NO_IDLE
- PCS_STATE_SEQ_DET_STATE
- PCS_STATE_WORD_SYNC_STATE
- PCS_STATUS1__HighPriorityInterrupt1Done_MASK
- PCS_STATUS1__HighPriorityInterrupt1Done__SHIFT
- PCS_STATUS1__LowPriorityInterrupt0Done_MASK
- PCS_STATUS1__LowPriorityInterrupt0Done__SHIFT
- PCS_STATUS1__LowPriorityInterrupt2Done_MASK
- PCS_STATUS1__LowPriorityInterrupt2Done__SHIFT
- PCS_TEST_ENABLE
- PCS_TEST_PATTERN_MASK
- PCS_TEST_PATTERN_SHIFT
- PCS_TEST_SELECT_REG
- PCS_UC8051_STATUS_REG
- PCS_UC_STATUS_FW_SAVE
- PCS_UC_STATUS_LBN
- PCS_UC_STATUS_WIDTH
- PCS_V1_WINDOW_SELECT
- PCS_V2_RV_WINDOW_DEF
- PCS_V2_RV_WINDOW_SELECT
- PCS_V2_WINDOW_DEF
- PCS_V2_WINDOW_DEF_OFFSET_INDEX
- PCS_V2_WINDOW_DEF_OFFSET_WIDTH
- PCS_V2_WINDOW_DEF_SIZE_INDEX
- PCS_V2_WINDOW_DEF_SIZE_WIDTH
- PCS_V2_WINDOW_SELECT
- PCS_VEND1_LBTXD_LBN
- PCS_VEND1_REG
- PCS_WRITE_REG_OFFSET
- PCT
- PCT2075_REG_IDLE
- PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK
- PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT
- PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK
- PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT
- PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK
- PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT
- PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK
- PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT
- PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK
- PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT
- PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK
- PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT
- PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK
- PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT
- PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK
- PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT
- PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK
- PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT
- PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK
- PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT
- PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK
- PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT
- PCTL0_CTRL__PGFSM_CMD_STATUS_MASK
- PCTL0_CTRL__PGFSM_CMD_STATUS__SHIFT
- PCTL0_CTRL__PG_ENABLE_MASK
- PCTL0_CTRL__PG_ENABLE__SHIFT
- PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK
- PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT
- PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK
- PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT
- PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK
- PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT
- PCTL0_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK
- PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK
- PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT
- PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK
- PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT
- PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK
- PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT
- PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT
- PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK
- PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT
- PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT
- PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK
- PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT
- PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT
- PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK
- PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT
- PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT
- PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK
- PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT
- PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK
- PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK
- PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT
- PCTL1_CTRL__OVR_EA0_SDP_FULLACK_MASK
- PCTL1_CTRL__OVR_EA0_SDP_FULLACK__SHIFT
- PCTL1_CTRL__OVR_EA0_SDP_PARTACK_MASK
- PCTL1_CTRL__OVR_EA0_SDP_PARTACK__SHIFT
- PCTL1_CTRL__OVR_EA1_SDP_FULLACK_MASK
- PCTL1_CTRL__OVR_EA1_SDP_FULLACK__SHIFT
- PCTL1_CTRL__OVR_EA1_SDP_PARTACK_MASK
- PCTL1_CTRL__OVR_EA1_SDP_PARTACK__SHIFT
- PCTL1_CTRL__OVR_EA2_SDP_FULLACK_MASK
- PCTL1_CTRL__OVR_EA2_SDP_FULLACK__SHIFT
- PCTL1_CTRL__OVR_EA2_SDP_PARTACK_MASK
- PCTL1_CTRL__OVR_EA2_SDP_PARTACK__SHIFT
- PCTL1_CTRL__OVR_EA3_SDP_FULLACK_MASK
- PCTL1_CTRL__OVR_EA3_SDP_FULLACK__SHIFT
- PCTL1_CTRL__OVR_EA3_SDP_PARTACK_MASK
- PCTL1_CTRL__OVR_EA3_SDP_PARTACK__SHIFT
- PCTL1_CTRL__OVR_EA4_SDP_FULLACK_MASK
- PCTL1_CTRL__OVR_EA4_SDP_FULLACK__SHIFT
- PCTL1_CTRL__OVR_EA4_SDP_PARTACK_MASK
- PCTL1_CTRL__OVR_EA4_SDP_PARTACK__SHIFT
- PCTL1_CTRL__PGFSM_CMD_STATUS_MASK
- PCTL1_CTRL__PGFSM_CMD_STATUS__SHIFT
- PCTL1_CTRL__PG_ENABLE_MASK
- PCTL1_CTRL__PG_ENABLE__SHIFT
- PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK
- PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT
- PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK
- PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT
- PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK
- PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT
- PCTL1_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS0_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS0__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS10_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS10__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS11_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS11__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS12_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS12__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS13_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS13__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS14_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS14__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS15_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS15__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS16_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS16__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS1_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS1__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS2_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS2__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS3_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS3__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS4_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS4__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS5_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS5__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS6_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS6__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS7_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS7__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS8_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS8__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__DS9_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__DS9__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK
- PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK
- PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS0_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS0__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS10_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS10__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS11_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS11__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS12_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS12__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS13_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS13__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS14_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS14__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS15_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS15__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS16_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS16__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS1_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS1__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS2_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS2__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS3_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS3__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS4_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS4__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS5_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS5__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS6_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS6__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS7_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS7__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS8_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS8__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS9_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS9__SHIFT
- PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK
- PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS0_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS0__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS10_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS10__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS11_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS11__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS12_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS12__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS13_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS13__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS14_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS14__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS15_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS15__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS16_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS16__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS1_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS1__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS2_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS2__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS3_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS3__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS4_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS4__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS5_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS5__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS6_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS6__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS7_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS7__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS8_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS8__SHIFT
- PCTL1_SLICE0_CFG_DS_ALLOW__DS9_MASK
- PCTL1_SLICE0_CFG_DS_ALLOW__DS9__SHIFT
- PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_SLICE0_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS0_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS0__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS10_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS10__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS11_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS11__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS12_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS12__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS13_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS13__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS14_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS14__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS15_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS15__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS16_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS16__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS1_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS1__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS2_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS2__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS3_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS3__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS4_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS4__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS5_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS5__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS6_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS6__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS7_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS7__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS8_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS8__SHIFT
- PCTL1_SLICE1_CFG_DS_ALLOW__DS9_MASK
- PCTL1_SLICE1_CFG_DS_ALLOW__DS9__SHIFT
- PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_SLICE1_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS0_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS0__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS10_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS10__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS11_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS11__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS12_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS12__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS13_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS13__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS14_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS14__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS15_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS15__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS16_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS16__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS1_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS1__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS2_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS2__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS3_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS3__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS4_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS4__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS5_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS5__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS6_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS6__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS7_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS7__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS8_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS8__SHIFT
- PCTL1_SLICE2_CFG_DS_ALLOW__DS9_MASK
- PCTL1_SLICE2_CFG_DS_ALLOW__DS9__SHIFT
- PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_SLICE2_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS0_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS0__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS10_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS10__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS11_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS11__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS12_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS12__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS13_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS13__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS14_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS14__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS15_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS15__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS16_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS16__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS1_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS1__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS2_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS2__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS3_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS3__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS4_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS4__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS5_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS5__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS6_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS6__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS7_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS7__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS8_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS8__SHIFT
- PCTL1_SLICE3_CFG_DS_ALLOW__DS9_MASK
- PCTL1_SLICE3_CFG_DS_ALLOW__DS9__SHIFT
- PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_SLICE3_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK
- PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS0_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS0__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS10_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS10__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS11_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS11__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS12_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS12__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS13_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS13__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS14_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS14__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS15_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS15__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS16_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS16__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS1_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS1__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS2_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS2__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS3_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS3__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS4_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS4__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS5_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS5__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS6_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS6__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS7_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS7__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS8_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS8__SHIFT
- PCTL1_SLICE4_CFG_DS_ALLOW__DS9_MASK
- PCTL1_SLICE4_CFG_DS_ALLOW__DS9__SHIFT
- PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL1_SLICE4_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL1_UTCL2_MISC__RD_TIMER_ENABLE_MASK
- PCTL1_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL2_MISC__CRITICAL_REGS_LOCK_MASK
- PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT
- PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK
- PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT
- PCTL2_MISC__RD_TIMER_ENABLE_MASK
- PCTL2_MISC__RD_TIMER_ENABLE__SHIFT
- PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK
- PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT
- PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK
- PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK
- PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK
- PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT
- PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK
- PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT
- PCTL_ALP_REQ_EN
- PCTL_AUTO_SLEEP
- PCTL_COM_ON
- PCTL_HT_REQ_EN
- PCTL_ILP_DIV_EN
- PCTL_ILP_DIV_MASK
- PCTL_ILP_DIV_SHIFT
- PCTL_LINK
- PCTL_LINK_OFFS
- PCTL_LINK_RST
- PCTL_LPO_SEL
- PCTL_MEASURE
- PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK
- PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT
- PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK
- PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT
- PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK
- PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT
- PCTL_MISC__OVR_EA0_SDP_FULLACK_MASK
- PCTL_MISC__OVR_EA0_SDP_FULLACK__SHIFT
- PCTL_MISC__OVR_EA0_SDP_PARTACK_MASK
- PCTL_MISC__OVR_EA0_SDP_PARTACK__SHIFT
- PCTL_MISC__OVR_EA1_SDP_FULLACK_MASK
- PCTL_MISC__OVR_EA1_SDP_FULLACK__SHIFT
- PCTL_MISC__OVR_EA1_SDP_PARTACK_MASK
- PCTL_MISC__OVR_EA1_SDP_PARTACK__SHIFT
- PCTL_MISC__PGFSM_CMD_STATUS_MASK
- PCTL_MISC__PGFSM_CMD_STATUS__SHIFT
- PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK
- PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT
- PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK
- PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT
- PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK
- PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK
- PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS0_MASK
- PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS10_MASK
- PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS11_MASK
- PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS12_MASK
- PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS13_MASK
- PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS14_MASK
- PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS15_MASK
- PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS16_MASK
- PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS1_MASK
- PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS2_MASK
- PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS3_MASK
- PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS4_MASK
- PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS5_MASK
- PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS6_MASK
- PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS7_MASK
- PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS8_MASK
- PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT
- PCTL_MMHUB_DEEPSLEEP__DS9_MASK
- PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT
- PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK
- PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT
- PCTL_NOILP_ON_WAIT
- PCTL_PERFCOUNTER0_CFG__CLEAR_MASK
- PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT
- PCTL_PERFCOUNTER0_CFG__ENABLE_MASK
- PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT
- PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK
- PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK
- PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- PCTL_PERFCOUNTER1_CFG__CLEAR_MASK
- PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT
- PCTL_PERFCOUNTER1_CFG__ENABLE_MASK
- PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT
- PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK
- PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK
- PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK
- PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK
- PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- PCTL_PG_DAGB__DS0_MASK
- PCTL_PG_DAGB__DS0__SHIFT
- PCTL_PG_DAGB__DS10_MASK
- PCTL_PG_DAGB__DS10__SHIFT
- PCTL_PG_DAGB__DS11_MASK
- PCTL_PG_DAGB__DS11__SHIFT
- PCTL_PG_DAGB__DS12_MASK
- PCTL_PG_DAGB__DS12__SHIFT
- PCTL_PG_DAGB__DS13_MASK
- PCTL_PG_DAGB__DS13__SHIFT
- PCTL_PG_DAGB__DS14_MASK
- PCTL_PG_DAGB__DS14__SHIFT
- PCTL_PG_DAGB__DS15_MASK
- PCTL_PG_DAGB__DS15__SHIFT
- PCTL_PG_DAGB__DS16_MASK
- PCTL_PG_DAGB__DS16__SHIFT
- PCTL_PG_DAGB__DS1_MASK
- PCTL_PG_DAGB__DS1__SHIFT
- PCTL_PG_DAGB__DS2_MASK
- PCTL_PG_DAGB__DS2__SHIFT
- PCTL_PG_DAGB__DS3_MASK
- PCTL_PG_DAGB__DS3__SHIFT
- PCTL_PG_DAGB__DS4_MASK
- PCTL_PG_DAGB__DS4__SHIFT
- PCTL_PG_DAGB__DS5_MASK
- PCTL_PG_DAGB__DS5__SHIFT
- PCTL_PG_DAGB__DS6_MASK
- PCTL_PG_DAGB__DS6__SHIFT
- PCTL_PG_DAGB__DS7_MASK
- PCTL_PG_DAGB__DS7__SHIFT
- PCTL_PG_DAGB__DS8_MASK
- PCTL_PG_DAGB__DS8__SHIFT
- PCTL_PG_DAGB__DS9_MASK
- PCTL_PG_DAGB__DS9__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT
- PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK
- PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT
- PCTL_PHY_DSBL
- PCTL_PHY_DSBL_OFFS
- PCTL_PLL_PLLCTL_UPD
- PCTL_PWR_OFF
- PCTL_SLEEP
- PCTL_WAKEUP
- PCTL_XTALFREQ_MASK
- PCTL_XTALFREQ_SHIFT
- PCTODSP_BASED
- PCTODSP_OFFSET
- PCTRA
- PCTRL
- PCTRL_ADDR
- PCTRL_CMD_CONT
- PCTRL_CMD_ESC
- PCTRL_CMD_FRH
- PCTRL_CMD_FRM
- PCTRL_CMD_FTH
- PCTRL_CMD_FTM
- PCTRL_CMD_HALT
- PCTRL_CMD_SILOFF
- PCTRL_CMD_SILON
- PCTRL_CMD_TDTMF
- PCTRL_LOC_REN
- PCTRL_LOC_RET
- PCTRL_ORIG
- PCTRL_PCEN
- PCTRL_PERI_CTRL24
- PCTRL_PERI_CTRL3
- PCTRL_PERI_CTRL3_MSK_START
- PCTRL_STOP
- PCTRL_WIDTH_MASK
- PCTRL_WIDTH_SHIFT
- PCTV_74E_USB_PID
- PCTV_74E_USB_VID
- PCTV_ANSWER_LEN
- PCTV_CMD_I2C
- PCTV_CMD_IR
- PCTV_CMD_RESET
- PCTV_LED_GPIO
- PCTV_LED_GREEN
- PCTV_LED_ORANGE
- PCTV_TIMEOUT
- PCURRMS2SEG_END
- PCURRMS2SEG_START
- PCURRMS4SEG_END
- PCURRMS4SEG_START
- PCURR_END
- PCURR_START
- PCUT_STATUS
- PCU_CPU0_CTRL
- PCU_CPU1_CTRL
- PCU_CPU1_ST
- PCU_DM_ACK_SYNC
- PCU_DM_CLKEN
- PCU_DM_DECPPU
- PCU_DM_GMAC
- PCU_DM_GPU
- PCU_DM_HDE
- PCU_DM_HSIC
- PCU_DM_ISOEN
- PCU_DM_NEON0
- PCU_DM_NEON1
- PCU_DM_PWRDN
- PCU_DM_PWREN
- PCU_DM_R2D
- PCU_DM_RSTEN
- PCU_DM_SAPPU
- PCU_DM_TOP
- PCU_DM_TS
- PCU_DM_USB20
- PCU_DM_USB21
- PCU_DM_USB30
- PCU_DM_VCE
- PCU_DM_VDE
- PCU_DM_VIU
- PCU_DM_VOU
- PCU_EXPEND_CONTROL
- PCU_GLOBAL_CTRL
- PCU_PCODE2DRIVER_MAILBOX
- PCU_THERMAL
- PCV
- PCV_MASK
- PCV_SHIFT
- PCWA5
- PCWB5
- PCWD_ISA_NR_CARDS
- PCWD_REVISION_A
- PCWD_REVISION_C
- PCW_CHG_MASK
- PCXHR_BOARD_AESIN_NO_192K
- PCXHR_BOARD_HAS_AES1
- PCXHR_CFG_CLOCKIN_SEL_MASK
- PCXHR_CFG_CLOCK_UER1_SEL_MASK
- PCXHR_CFG_DATAIN_SEL_MASK
- PCXHR_CFG_DATA_UER1_SEL_MASK
- PCXHR_CFG_DEPENDENCY_MASK
- PCXHR_CFG_INDEPENDANT_SEL
- PCXHR_CFG_MASTER_SEL
- PCXHR_CFG_SLAVE_SEL
- PCXHR_CFG_SRC_MASK
- PCXHR_CFG_SYNCDSP_MASK
- PCXHR_CHIPSC_DATA_CLK
- PCXHR_CHIPSC_DATA_IN
- PCXHR_CHIPSC_GPI_USERI
- PCXHR_CHIPSC_INIT_VALUE
- PCXHR_CHIPSC_RESET_XILINX
- PCXHR_CLOCK_TYPE_AES_1
- PCXHR_CLOCK_TYPE_AES_2
- PCXHR_CLOCK_TYPE_AES_3
- PCXHR_CLOCK_TYPE_AES_4
- PCXHR_CLOCK_TYPE_AES_SYNC
- PCXHR_CLOCK_TYPE_INTERNAL
- PCXHR_CLOCK_TYPE_MAX
- PCXHR_CLOCK_TYPE_WORD_CLOCK
- PCXHR_CVR_HI08_HC
- PCXHR_DATA_CODEC
- PCXHR_DIGITAL_LEVEL_MAX
- PCXHR_DIGITAL_LEVEL_MIN
- PCXHR_DIGITAL_ZERO_LEVEL
- PCXHR_DRIVER_VERSION
- PCXHR_DRIVER_VERSION_STRING
- PCXHR_DSP
- PCXHR_DSP_CVR
- PCXHR_DSP_ICR
- PCXHR_DSP_ISR
- PCXHR_DSP_IVR
- PCXHR_DSP_OFFSET_MAX
- PCXHR_DSP_RESET
- PCXHR_DSP_RESET_CODEC
- PCXHR_DSP_RESET_DSP
- PCXHR_DSP_RESET_GPO_MASK
- PCXHR_DSP_RESET_GPO_OFFSET
- PCXHR_DSP_RESET_MUTE
- PCXHR_DSP_RESET_SMPTE
- PCXHR_DSP_RXH
- PCXHR_DSP_RXL
- PCXHR_DSP_RXM
- PCXHR_DSP_TIME_INVALID
- PCXHR_DSP_TIME_MASK
- PCXHR_DSP_TXH
- PCXHR_DSP_TXL
- PCXHR_DSP_TXM
- PCXHR_ERR_AUDIO
- PCXHR_ERR_PIPE
- PCXHR_ERR_STREAM
- PCXHR_FATAL_DSP_ERR
- PCXHR_FIRMWARE_DSP_BOOT_INDEX
- PCXHR_FIRMWARE_DSP_EPRM_INDEX
- PCXHR_FIRMWARE_DSP_MAIN_INDEX
- PCXHR_FIRMWARE_FILES_MAX_INDEX
- PCXHR_FIRMWARE_XLX_COM_INDEX
- PCXHR_FIRMWARE_XLX_INT_INDEX
- PCXHR_FREQ_AES_1
- PCXHR_FREQ_AES_2
- PCXHR_FREQ_AES_3
- PCXHR_FREQ_AES_4
- PCXHR_FREQ_PLL
- PCXHR_FREQ_QUARTZ_11025
- PCXHR_FREQ_QUARTZ_12000
- PCXHR_FREQ_QUARTZ_128000
- PCXHR_FREQ_QUARTZ_16000
- PCXHR_FREQ_QUARTZ_176400
- PCXHR_FREQ_QUARTZ_192000
- PCXHR_FREQ_QUARTZ_22050
- PCXHR_FREQ_QUARTZ_24000
- PCXHR_FREQ_QUARTZ_32000
- PCXHR_FREQ_QUARTZ_44100
- PCXHR_FREQ_QUARTZ_48000
- PCXHR_FREQ_QUARTZ_64000
- PCXHR_FREQ_QUARTZ_8000
- PCXHR_FREQ_QUARTZ_88200
- PCXHR_FREQ_QUARTZ_96000
- PCXHR_FREQ_REG_MASK
- PCXHR_FREQ_SYNC_AES
- PCXHR_FREQ_WORD_CLOCK
- PCXHR_GRANULARITY
- PCXHR_GRANULARITY_HR22
- PCXHR_GRANULARITY_MIN
- PCXHR_ICR_HI08_HDRQ
- PCXHR_ICR_HI08_HF0
- PCXHR_ICR_HI08_HF1
- PCXHR_ICR_HI08_HLEND
- PCXHR_ICR_HI08_INIT
- PCXHR_ICR_HI08_RREQ
- PCXHR_ICR_HI08_TREQ
- PCXHR_INPB
- PCXHR_INPL
- PCXHR_IRQCS_ACTIVE_PCIDB
- PCXHR_IRQCS_ENABLE_PCIDB
- PCXHR_IRQCS_ENABLE_PCIIRQ
- PCXHR_IRQ_ASYNC
- PCXHR_IRQ_FREQ_CHANGE
- PCXHR_IRQ_MASK
- PCXHR_IRQ_NOTIFY
- PCXHR_IRQ_TIMER
- PCXHR_IRQ_TIMER_FREQ
- PCXHR_IRQ_TIMER_PERIOD
- PCXHR_IRQ_TIME_CODE
- PCXHR_ISR_HI08_CHK
- PCXHR_ISR_HI08_ERR
- PCXHR_ISR_HI08_HREQ
- PCXHR_ISR_HI08_RXDF
- PCXHR_ISR_HI08_TRDY
- PCXHR_ISR_HI08_TXDE
- PCXHR_IT_DEBUG
- PCXHR_IT_DOWNLOAD_BOOT
- PCXHR_IT_DOWNLOAD_DSP
- PCXHR_IT_MESSAGE
- PCXHR_IT_RESET_BOARD_FUNC
- PCXHR_IT_RESET_CHK
- PCXHR_IT_RESET_SEMAPHORE
- PCXHR_IT_SEND_BYTE_XILINX
- PCXHR_IT_TEST_XILINX
- PCXHR_IT_UPDATE_RBUFFER
- PCXHR_LINE_CAPTURE_LEVEL_MAX
- PCXHR_LINE_CAPTURE_LEVEL_MIN
- PCXHR_LINE_CAPTURE_ZERO_LEVEL
- PCXHR_LINE_PLAYBACK_LEVEL_MAX
- PCXHR_LINE_PLAYBACK_LEVEL_MIN
- PCXHR_LINE_PLAYBACK_ZERO_LEVEL
- PCXHR_MASK_EXTRA_INFO
- PCXHR_MASK_IT_HF0
- PCXHR_MASK_IT_HF1
- PCXHR_MASK_IT_MANAGE_HF5
- PCXHR_MASK_IT_NO_HF0_HF1
- PCXHR_MASK_IT_WAIT
- PCXHR_MASK_IT_WAIT_EXTRA
- PCXHR_MAX_CARDS
- PCXHR_MBOX0_BOOT_HERE
- PCXHR_MBOX0_HF4
- PCXHR_MBOX0_HF5
- PCXHR_MODIFY_CLOCK_S_BIT
- PCXHR_OUTPB
- PCXHR_OUTPL
- PCXHR_PIPE_DEFINED
- PCXHR_PIPE_STATE_CAPTURE_OFFSET
- PCXHR_PIPE_UNDEFINED
- PCXHR_PLAYBACK_STREAMS
- PCXHR_PLX
- PCXHR_PLX_CHIPSC
- PCXHR_PLX_IRQCS
- PCXHR_PLX_L2PCIDB
- PCXHR_PLX_MBOX0
- PCXHR_PLX_MBOX1
- PCXHR_PLX_MBOX2
- PCXHR_PLX_MBOX3
- PCXHR_PLX_MBOX4
- PCXHR_PLX_MBOX5
- PCXHR_PLX_MBOX6
- PCXHR_PLX_MBOX7
- PCXHR_PLX_OFFSET_MIN
- PCXHR_REG_TO_PORT
- PCXHR_SELMIC_PHANTOM_ALIM
- PCXHR_SELMIC_PREAMPLI_MASK
- PCXHR_SELMIC_PREAMPLI_OFFSET
- PCXHR_SIZE_MAX_CMD
- PCXHR_SIZE_MAX_LONG_STATUS
- PCXHR_SIZE_MAX_STATUS
- PCXHR_SOURCE_AUDIO01_SYNC
- PCXHR_SOURCE_AUDIO01_UER
- PCXHR_SOURCE_AUDIO23_UER
- PCXHR_SOURCE_AUDIO45_UER
- PCXHR_SOURCE_AUDIO67_UER
- PCXHR_STAT_FREQ_SAVE_MASK
- PCXHR_STAT_FREQ_SYNC_MASK
- PCXHR_STAT_FREQ_UER1_MASK
- PCXHR_STAT_GPI_MASK
- PCXHR_STAT_GPI_OFFSET
- PCXHR_STAT_LEVEL_IN
- PCXHR_STAT_MIC_CAPS
- PCXHR_STAT_SRC_LOCK
- PCXHR_STREAM_STATUS_FREE
- PCXHR_STREAM_STATUS_OPEN
- PCXHR_STREAM_STATUS_PAUSED
- PCXHR_STREAM_STATUS_RUNNING
- PCXHR_STREAM_STATUS_SCHEDULE_RUN
- PCXHR_STREAM_STATUS_SCHEDULE_STOP
- PCXHR_STREAM_STATUS_STARTED
- PCXHR_STREAM_STATUS_STOPPED
- PCXHR_SUER1_BIT_C_READ_MASK
- PCXHR_SUER1_BIT_U_READ_MASK
- PCXHR_SUER1_CLOCK_PRESENT_MASK
- PCXHR_SUER1_DATA_PRESENT_MASK
- PCXHR_SUER_BIT_C_READ_MASK
- PCXHR_SUER_BIT_C_WRITE_MASK
- PCXHR_SUER_BIT_U_READ_MASK
- PCXHR_SUER_BIT_U_WRITE_MASK
- PCXHR_SUER_CLOCK_PRESENT_MASK
- PCXHR_SUER_DATA_PRESENT_MASK
- PCXHR_TIMEOUT_DSP
- PCXHR_WAIT_DEFAULT
- PCXHR_WAIT_IT
- PCXHR_WAIT_IT_EXTRA
- PCXHR_XLX_CFG
- PCXHR_XLX_CSUER
- PCXHR_XLX_DATA
- PCXHR_XLX_HIFREQ
- PCXHR_XLX_LOFREQ
- PCXHR_XLX_RUER
- PCXHR_XLX_SELMIC
- PCXHR_XLX_STATUS
- PCXL_DMA_MAP_SIZE
- PCXL_FIND_FREE_MAPPING
- PCXL_FREE_MAPPINGS
- PCXL_SEARCH_LOOP
- PCXR_2BSM
- PCXR_AN_DUPLEX_DIS
- PCXR_AN_FLOWCTL_DIS
- PCXR_AN_SPEED_DIS
- PCXR_DSCP_EN
- PCXR_FLOWCTL_DIS
- PCXR_FLP
- PCXR_MFL_1518
- PCXR_MFL_1536
- PCXR_MFL_2048
- PCXR_MFL_64K
- PCXR_PRIO_TX_OFF
- PCXR_RMII_EN
- PCXR_SPEED_100
- PCXR_TX_HIGH_PRI
- PCXU_IMAGE_SIZE
- PCXW_IMAGE_SIZE
- PCX_IRQ_NONE
- PCX_TIME_HI_MASK
- PC_ACCEPT
- PC_BASE
- PC_BE_CLOCK_GATE_DISABLE
- PC_BUSY
- PC_BUSY_CYCLES
- PC_BUSY_GUI
- PC_BUSY_INIT
- PC_BUSY_NGUI
- PC_CCU_INVALIDATE_COLOR
- PC_CCU_INVALIDATE_DEPTH
- PC_CID
- PC_CIDMODE
- PC_CKS_LOC
- PC_CKS_RANGE_END
- PC_CKS_RANGE_START
- PC_CLK
- PC_DEAD_DRAWCALLS
- PC_DEAD_PRIM
- PC_DEBUG_MODE
- PC_DIAL
- PC_DISABLE
- PC_DLE0
- PC_DLE1
- PC_DRAW_LINES
- PC_DRAW_POINTS
- PC_DRAW_TRIANGLES
- PC_DS_INVOCATIONS
- PC_DS_PRIMITIVES
- PC_DTACK
- PC_ENABLE
- PC_F1RXCLK
- PC_F1TXCLK
- PC_F2RXCLK
- PC_F2TXCLK
- PC_F3RXCLK
- PC_F3TXCLK
- PC_FE_CLOCK_GATE_DISABLE
- PC_FLAG_ABORT
- PC_FLAG_DMA_ERROR
- PC_FLAG_DMA_IN_PROGRESS
- PC_FLAG_DMA_OK
- PC_FLAG_SUPPRESS_ERROR
- PC_FLAG_WAIT_FOR_DSC
- PC_FLAG_WRITING
- PC_GS_PRIMITIVES
- PC_GUI_CTLSTAT
- PC_GUI_MODE
- PC_HLS
- PC_HS_INVOCATIONS
- PC_HUP
- PC_IA_VERTICES
- PC_ILS
- PC_INIT
- PC_IRQ7
- PC_JOIN
- PC_KOBJ_ID
- PC_LACD
- PC_LCLK
- PC_LD0
- PC_LD1
- PC_LD2
- PC_LD3
- PC_LDS
- PC_LEM
- PC_LFLM
- PC_LIVE_DRAWCALLS
- PC_LIVE_PRIM
- PC_LLP
- PC_LOOP
- PC_LS_NONE
- PC_LS_PDR
- PC_MAINT
- PC_MAX_SPEC_BNKS
- PC_MAX_SPEC_CNTRS
- PC_MLS
- PC_MOCLK
- PC_MODE0_DRAWCALL
- PC_MODE1_DRAWCALL
- PC_MODE2_DRAWCALL
- PC_MODE3_DRAWCALL
- PC_MODE4_DRAWCALL
- PC_NGUI_CTLSTAT
- PC_NGUI_MODE
- PC_NOCID
- PC_NSE
- PC_PCPERF_CYCLES_IS_WORKING
- PC_PCPERF_CYCLES_STALLED_BY_TSE
- PC_PCPERF_CYCLES_STALLED_BY_VBIF
- PC_PCPERF_CYCLES_STALLED_BY_VFD
- PC_PCPERF_DRAWCALLS_KILLED_BY_VS
- PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS
- PC_PCPERF_PRIMITIVES_KILLED_BY_VS
- PC_PCPERF_PRIMITIVES_PC_VPC
- PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS
- PC_PCPERF_REUSED_VERTICES
- PC_PCPERF_TOTAL_INSTANCES
- PC_PCPERF_VERTICES_TO_VFD
- PC_PCPERF_VISIBILITY_STREAMS
- PC_PDR
- PC_PREDICATED_DEAD_DRAWCALL
- PC_QLS
- PC_REJECT
- PC_REQ_SIZE
- PC_RESP_SIZE
- PC_SHUTDOWN
- PC_SIGNAL
- PC_STALL_CYCLES_BY_TSE_ONLY
- PC_STALL_CYCLES_BY_VPC_ONLY
- PC_STALL_CYCLES_TESS
- PC_STALL_CYCLES_TSE
- PC_STALL_CYCLES_UCHE
- PC_STALL_CYCLES_VFD
- PC_STALL_CYCLES_VPC
- PC_START
- PC_STARVE_CYCLES_DI
- PC_STARVE_CYCLES_FOR_INDEX
- PC_STARVE_CYCLES_FOR_POSITION
- PC_STARVE_CYCLES_FOR_TESS_FACTOR
- PC_STARVE_CYCLES_FOR_VIZ_STREAM
- PC_STOP
- PC_TEST_MODE
- PC_TIMEOUT_C_MIN
- PC_TIMEOUT_LCT
- PC_TIMEOUT_TB_MAX
- PC_TIMEOUT_TB_MIN
- PC_TIMEOUT_TL_MIN
- PC_TIMEOUT_T_NEXT
- PC_TIMEOUT_T_OUT
- PC_TRACE
- PC_UDS
- PC_UMMODE
- PC_VAUX_DIS
- PC_VAUX_ENA
- PC_VAUX_OFF
- PC_VAUX_ON
- PC_VCC_DIS
- PC_VCC_ENA
- PC_VCC_OFF
- PC_VCC_ON
- PC_VERTEX_MISSES
- PC_VIS_STREAMS_LOADED
- PC_VPC_POS_DATA_TRANSACTION
- PC_VPC_PRIMITIVES
- PC_WE
- PC_WH_M_M
- PC_WH_NONE
- PC_WH_OTHER
- PC_WH_PATH
- PC_WORKING_CYCLES
- PD
- PD0
- PD0MD_00
- PD0MD_000
- PD0MD_001
- PD0MD_01
- PD0MD_010
- PD0MD_011
- PD0MD_10
- PD0MD_100
- PD0MD_101
- PD0MD_11
- PD0_AIN_FEC_TXD0
- PD0_DATA
- PD0_FN
- PD0_IN
- PD0_IOR_IN
- PD0_IOR_OUT
- PD0_MASK
- PD0_OUT
- PD0_PF_SD3_CMD
- PD0_SHIFT
- PD1
- PD1011_RDESC_ORIG_SIZE
- PD10MD_00
- PD10MD_000
- PD10MD_001
- PD10MD_01
- PD10MD_010
- PD10MD_10
- PD10MD_100
- PD10MD_101
- PD10MD_11
- PD10_AF_ETMTRACE_PKT11
- PD10_AOUT_FEC_CRS
- PD10_CIN_SLCDC1_DAT8
- PD10_DATA
- PD10_IN
- PD10_IOR_IN
- PD10_IOR_OUT
- PD10_OUT
- PD10_PF_ATA_DATA8
- PD11MD_00
- PD11MD_000
- PD11MD_001
- PD11MD_01
- PD11MD_010
- PD11MD_10
- PD11MD_100
- PD11MD_101
- PD11MD_11
- PD11_AF_ETMTRACE_PKT10
- PD11_AOUT_FEC_TX_CLK
- PD11_CIN_SLCDC1_DAT9
- PD11_DATA
- PD11_IN
- PD11_IOR_IN
- PD11_IOR_OUT
- PD11_OUT
- PD11_PF_ATA_DATA9
- PD12MD_00
- PD12MD_000
- PD12MD_001
- PD12MD_01
- PD12MD_010
- PD12MD_10
- PD12MD_100
- PD12MD_101
- PD12MD_11
- PD12_AF_ETMTRACE_PKT9
- PD12_AOUT_FEC_RXD0
- PD12_CIN_SLCDC1_DAT10
- PD12_DATA
- PD12_IN
- PD12_IOR_IN
- PD12_IOR_OUT
- PD12_OUT
- PD12_PF_ATA_DATA10
- PD13MD_00
- PD13MD_000
- PD13MD_001
- PD13MD_01
- PD13MD_010
- PD13MD_10
- PD13MD_100
- PD13MD_101
- PD13MD_11
- PD13_AF_ETMTRACE_PKT8
- PD13_AOUT_FEC_RX_DV
- PD13_CIN_SLCDC1_DAT11
- PD13_DATA
- PD13_IN
- PD13_IOR_IN
- PD13_IOR_OUT
- PD13_OUT
- PD13_PF_ATA_DATA11
- PD14MD_00
- PD14MD_000
- PD14MD_001
- PD14MD_01
- PD14MD_010
- PD14MD_10
- PD14MD_101
- PD14MD_11
- PD14_AF_ETMTRACE_PKT7
- PD14_AOUT_FEC_RX_CLK
- PD14_CIN_SLCDC1_DAT12
- PD14_DATA
- PD14_IN
- PD14_IOR_IN
- PD14_IOR_OUT
- PD14_OUT
- PD14_PF_ATA_DATA12
- PD15MD_00
- PD15MD_000
- PD15MD_001
- PD15MD_01
- PD15MD_010
- PD15MD_10
- PD15MD_100
- PD15MD_101
- PD15MD_11
- PD15_AF_ETMTRACE_PKT6
- PD15_AOUT_FEC_COL
- PD15_CIN_SLCDC1_DAT13
- PD15_DATA
- PD15_IN
- PD15_IOR_IN
- PD15_IOR_OUT
- PD15_OUT
- PD15_PF_ATA_DATA13
- PD16_AF_ETMTRACE_PKT5
- PD16_AIN_FEC_TX_ER
- PD16_CIN_SLCDC1_DAT14
- PD16_PF_ATA_DATA14
- PD17_PF_I2C_DATA
- PD18_PF_I2C_CLK
- PD19_AF_USBH2_DATA4
- PD19_AOUT_USBH2_RXDM
- PD19_PF_CSPI2_SS2
- PD1MD_00
- PD1MD_000
- PD1MD_001
- PD1MD_01
- PD1MD_010
- PD1MD_011
- PD1MD_10
- PD1MD_100
- PD1MD_101
- PD1MD_11
- PD1_AF_ETMTRACE_PKT15
- PD1_AIN_FEC_TXD1
- PD1_DATA
- PD1_DISPLAY_POS
- PD1_FN
- PD1_IN
- PD1_IOR_IN
- PD1_IOR_OUT
- PD1_MASK
- PD1_OUT
- PD1_PF_SD3_CLK
- PD1_RAM_END
- PD1_RAM_START
- PD1_SHIFT
- PD20_AF_USBH2_DATA3
- PD20_AOUT_USBH2_RXDP
- PD20_PF_CSPI2_SS1
- PD21_AF_USBH2_DATA6
- PD21_AIN_USBH2_FS
- PD21_PF_CSPI2_SS0
- PD22_AF_USBH2_DATA0
- PD22_AIN_USBH2_OE
- PD22_PF_CSPI2_SCLK
- PD23_AF_USBH2_DATA2
- PD23_AIN_USBH2_TXDM
- PD23_CIN_SLCDC1_DAT15
- PD23_PF_CSPI2_MISO
- PD24_AF_USBH2_DATA1
- PD24_AIN_USBH2_TXDP
- PD24_PF_CSPI2_MOSI
- PD25_AOUT_EXT_DMAREQ
- PD25_PF_CSPI1_RDY
- PD26_AF_USBH2_DATA5
- PD26_AOUT_USBOTG_RXDAT
- PD26_PF_CSPI1_SS2
- PD27_AIN_EXT_DMA_GRANT
- PD27_BIN_EXT_DMA_GRANT
- PD27_PF_CSPI1_SS1
- PD28_PF_CSPI1_SS0
- PD29_PF_CSPI1_SCLK
- PD2MD_00
- PD2MD_000
- PD2MD_001
- PD2MD_01
- PD2MD_010
- PD2MD_011
- PD2MD_10
- PD2MD_100
- PD2MD_101
- PD2MD_11
- PD2_AF_SD3_D0
- PD2_AIN_FEC_TXD2
- PD2_CIN_SLCDC1_DAT0
- PD2_DATA
- PD2_DISPLAY_POS
- PD2_FN
- PD2_IN
- PD2_IOR_IN
- PD2_IOR_OUT
- PD2_OUT
- PD2_PF_ATA_DATA0
- PD2_RAM_END
- PD2_RAM_START
- PD2_ZERO_LENGTH
- PD30_PF_CSPI1_MISO
- PD31_PF_CSPI1_MOSI
- PD3MD_00
- PD3MD_000
- PD3MD_001
- PD3MD_01
- PD3MD_010
- PD3MD_011
- PD3MD_10
- PD3MD_100
- PD3MD_101
- PD3MD_11
- PD3_AF_SD3_D1
- PD3_AIN_FEC_TXD3
- PD3_CIN_SLCDC1_DAT1
- PD3_DATA
- PD3_FN
- PD3_IN
- PD3_IOR_IN
- PD3_IOR_OUT
- PD3_OUT
- PD3_PF_ATA_DATA1
- PD4MD_00
- PD4MD_000
- PD4MD_001
- PD4MD_01
- PD4MD_010
- PD4MD_011
- PD4MD_10
- PD4MD_100
- PD4MD_101
- PD4MD_11
- PD4_AF_SD3_D2
- PD4_AOUT_FEC_RX_ER
- PD4_CIN_SLCDC1_DAT2
- PD4_DATA
- PD4_FN
- PD4_IN
- PD4_IOR_IN
- PD4_IOR_OUT
- PD4_OUT
- PD4_PF_ATA_DATA2
- PD5MD_00
- PD5MD_000
- PD5MD_001
- PD5MD_01
- PD5MD_010
- PD5MD_011
- PD5MD_10
- PD5MD_100
- PD5MD_101
- PD5MD_11
- PD5_AF_SD3_D3
- PD5_AOUT_FEC_RXD1
- PD5_CIN_SLCDC1_DAT3
- PD5_DATA
- PD5_FN
- PD5_IN
- PD5_IOR_IN
- PD5_IOR_OUT
- PD5_OUT
- PD5_PF_ATA_DATA3
- PD67_ATA_CTL
- PD67_CHIP_INFO
- PD67_DATA_MASK0
- PD67_DATA_MASK1
- PD67_DMA_CTL
- PD67_DMA_DREQ_BVD2
- PD67_DMA_DREQ_INPACK
- PD67_DMA_DREQ_WP
- PD67_DMA_MODE
- PD67_DMA_OFF
- PD67_DMA_PULLUP
- PD67_EC1_AUTO_PWR_CLEAR
- PD67_EC1_INV_CARD_IRQ
- PD67_EC1_INV_MGMT_IRQ
- PD67_EC1_LED_ENA
- PD67_EC1_PULLUP_CTL
- PD67_EC1_VCC_PWR_LOCK
- PD67_EXD_VS1
- PD67_EXD_VS2
- PD67_EXTERN_DATA
- PD67_EXT_CTL_1
- PD67_EXT_DATA
- PD67_EXT_INDEX
- PD67_FIFO_CTL
- PD67_FIFO_EMPTY
- PD67_INFO_CHIP_ID
- PD67_INFO_REV
- PD67_INFO_SLOTS
- PD67_IO_OFF
- PD67_MASK
- PD67_MC1_5V_DET
- PD67_MC1_INPACK_ENA
- PD67_MC1_MEDIA_ENA
- PD67_MC1_PULSE_IRQ
- PD67_MC1_PULSE_MGMT
- PD67_MC1_SPKR_ENA
- PD67_MC1_VCC_3V
- PD67_MC2_3STATE_BIT7
- PD67_MC2_5V_CORE
- PD67_MC2_DMA_MODE
- PD67_MC2_DYNAMIC_MODE
- PD67_MC2_FAST_PCI
- PD67_MC2_FREQ_BYPASS
- PD67_MC2_IRQ15_RI
- PD67_MC2_LED_ENA
- PD67_MC2_SUSPEND
- PD67_MC3_IRQ_EXTERN
- PD67_MC3_IRQ_MASK
- PD67_MC3_IRQ_PCI
- PD67_MC3_IRQ_PCIWAY
- PD67_MC3_IRQ_PCPCI
- PD67_MC3_PWR_MASK
- PD67_MC3_PWR_SERIAL
- PD67_MC3_PWR_SMB
- PD67_MC3_PWR_TI2202
- PD67_MEM_PAGE
- PD67_MISC_CTL_1
- PD67_MISC_CTL_2
- PD67_MISC_CTL_3
- PD67_SMB_PWR_CTL
- PD67_TIME_CMD
- PD67_TIME_MULT
- PD67_TIME_RECOV
- PD67_TIME_SCALE
- PD67_TIME_SCALE_1
- PD67_TIME_SCALE_16
- PD67_TIME_SCALE_256
- PD67_TIME_SCALE_4096
- PD67_TIME_SETUP
- PD6832_BCR_MGMT_IRQ_ENA
- PD6832_SOCKET_NUMBER
- PD68_EXT_CSC
- PD68_EXT_CTL_2
- PD68_MC3_HW_SUSP
- PD68_MC3_MM_ARM
- PD68_MC3_MM_EXPAND
- PD68_MISC_CTL_4
- PD68_MISC_CTL_5
- PD68_MISC_CTL_6
- PD68_PCCARD_SPACE
- PD68_PCI_SPACE
- PD68_WINDOW_TYPE
- PD6MD_00
- PD6MD_000
- PD6MD_001
- PD6MD_01
- PD6MD_010
- PD6MD_011
- PD6MD_10
- PD6MD_100
- PD6MD_101
- PD6MD_11
- PD6_AF_ETMTRACE_PKT14
- PD6_AOUT_FEC_RXD2
- PD6_CIN_SLCDC1_DAT4
- PD6_DATA
- PD6_FN
- PD6_IN
- PD6_IOR_IN
- PD6_IOR_OUT
- PD6_OUT
- PD6_PF_ATA_DATA4
- PD7MD_00
- PD7MD_000
- PD7MD_001
- PD7MD_01
- PD7MD_010
- PD7MD_011
- PD7MD_10
- PD7MD_100
- PD7MD_101
- PD7MD_11
- PD7_AF_ETMTRACE_PKT13
- PD7_AOUT_FEC_RXD3
- PD7_CIN_SLCDC1_DAT5
- PD7_DATA
- PD7_FN
- PD7_IN
- PD7_IOR_IN
- PD7_IOR_OUT
- PD7_OUT
- PD7_PF_ATA_DATA5
- PD8MD_00
- PD8MD_000
- PD8MD_001
- PD8MD_01
- PD8MD_010
- PD8MD_10
- PD8MD_100
- PD8MD_101
- PD8MD_11
- PD8_AF_FEC_MDIO
- PD8_CIN_SLCDC1_DAT6
- PD8_DATA
- PD8_IN
- PD8_IOR_IN
- PD8_IOR_OUT
- PD8_OUT
- PD8_PF_ATA_DATA6
- PD9MD_00
- PD9MD_000
- PD9MD_001
- PD9MD_01
- PD9MD_010
- PD9MD_10
- PD9MD_100
- PD9MD_101
- PD9MD_11
- PD9_AF_ETMTRACE_PKT12
- PD9_AIN_FEC_MDC
- PD9_CIN_SLCDC1_DAT7
- PD9_DATA
- PD9_IN
- PD9_IOR_IN
- PD9_IOR_OUT
- PD9_OUT
- PD9_PF_ATA_DATA7
- PDAC
- PDAC2ACLNK
- PDAC_Def
- PDAC_Mask
- PDAC_Print
- PDAC_Read
- PDAC_ReadExt
- PDAC_Val
- PDAC_Write
- PDAC_WriteExt
- PDATA
- PDATA_LEN_MSK
- PDAUDIOCF_AK_SBP
- PDAUDIOCF_AK_SDD
- PDAUDIOCF_BLUEDUTY0
- PDAUDIOCF_BLUEDUTY1
- PDAUDIOCF_BLUEMODULATE
- PDAUDIOCF_BLUESDD
- PDAUDIOCF_BLUE_LED_OFF
- PDAUDIOCF_CLKDIV0
- PDAUDIOCF_CLKDIV1
- PDAUDIOCF_DATAFMT0
- PDAUDIOCF_DATAFMT1
- PDAUDIOCF_ELIMAKMBIT
- PDAUDIOCF_FPGAREV
- PDAUDIOCF_HALFRATE
- PDAUDIOCF_IRQAKM
- PDAUDIOCF_IRQAKMEN
- PDAUDIOCF_IRQLVL
- PDAUDIOCF_IRQLVLEN0
- PDAUDIOCF_IRQLVLEN1
- PDAUDIOCF_IRQOVR
- PDAUDIOCF_IRQOVREN
- PDAUDIOCF_PDN
- PDAUDIOCF_RECORD
- PDAUDIOCF_REDDUTY0
- PDAUDIOCF_REDDUTY1
- PDAUDIOCF_REDMODULATE
- PDAUDIOCF_RED_LED_OFF
- PDAUDIOCF_REG_AK_IFR
- PDAUDIOCF_REG_IER
- PDAUDIOCF_REG_ISR
- PDAUDIOCF_REG_MD
- PDAUDIOCF_REG_RDP
- PDAUDIOCF_REG_SCR
- PDAUDIOCF_REG_TCR
- PDAUDIOCF_REG_WDP
- PDAUDIOCF_RST
- PDAUDIOCF_STAT_IS_CONFIGURED
- PDAUDIOCF_STAT_IS_STALE
- PDAUDIOCF_STAT_IS_SUSPENDED
- PDAUDIOCF_TESTDATASEL
- PDA_COMP
- PDA_HIGH_BIT
- PDA_LOW_BIT
- PDA_POWER_CHARGE_AC
- PDA_POWER_CHARGE_USB
- PDA_PSY_OFFLINE
- PDA_PSY_ONLINE
- PDA_PSY_TO_CHANGE
- PDBG_CRS
- PDBG_RFD
- PDBG_RXF
- PDBG_RXFRG
- PDBG_RXS
- PDBG_RXV
- PDBG_TXA
- PDBG_TXE
- PDBG_TXF
- PDBHDRLEN_ESP_DECAP_SHIFT
- PDBHDRLEN_MASK
- PDBHMO_ESP_DECAP_DEC_TTL
- PDBHMO_ESP_DECAP_SHIFT
- PDBHMO_ESP_DFBIT
- PDBHMO_ESP_DIFFSERV
- PDBHMO_ESP_ENCAP_DEC_TTL
- PDBHMO_ESP_ENCAP_SHIFT
- PDBNH_ESP_ENCAP_MASK
- PDBNH_ESP_ENCAP_SHIFT
- PDBOPTS_ESP_AOFL
- PDBOPTS_ESP_ARS128
- PDBOPTS_ESP_ARS32
- PDBOPTS_ESP_ARS64
- PDBOPTS_ESP_ARSNONE
- PDBOPTS_ESP_ARS_MASK
- PDBOPTS_ESP_DIFFSERV
- PDBOPTS_ESP_ESN
- PDBOPTS_ESP_INCIPHDR
- PDBOPTS_ESP_IPHDRSRC
- PDBOPTS_ESP_IPV6
- PDBOPTS_ESP_IPVSN
- PDBOPTS_ESP_IVSRC
- PDBOPTS_ESP_OUTFMT
- PDBOPTS_ESP_TUNNEL
- PDBOPTS_ESP_UPDATE_CSUM
- PDBOPTS_ESP_VERIFY_CSUM
- PDB_CLOCK
- PDB_CMND
- PDB_DATA
- PDB_ENBL
- PDB_MASK
- PDB_NH_OFFSET_MASK
- PDB_NH_OFFSET_SHIFT
- PDB_SHIFT
- PDB_STRB
- PDC1_ERR_MASK
- PDC1_PCI_PARITY_ERR
- PDC20230
- PDC2_ATA_DMA_CNT_ERR
- PDC2_ATA_HBA_ERR
- PDC2_ERR_MASK
- PDC2_HTO_ERR
- PDC2_SATA_PLUG_CSR
- PDCR
- PDCSPATH_ENTRY
- PDCS_ADDR_DIAG
- PDCS_ADDR_FSIZ
- PDCS_ADDR_OSD1
- PDCS_ADDR_OSD2
- PDCS_ADDR_OSID
- PDCS_ADDR_PALT
- PDCS_ADDR_PCON
- PDCS_ADDR_PKBD
- PDCS_ADDR_PPRI
- PDCS_ATTR
- PDCS_DEBUG
- PDCS_PREFIX
- PDCS_VERSION
- PDCTL
- PDCTL_EPCGOOD
- PDCTL_NEXT
- PDC_100_MHZ
- PDC_133_MHZ
- PDC_20621_DIMM_BASE
- PDC_20621_DIMM_DATA
- PDC_20621_DIMM_WINDOW
- PDC_20621_ERR_MASK
- PDC_20621_GENERAL_CTL
- PDC_20621_PAGE_SIZE
- PDC_20621_SEQCTL
- PDC_20621_SEQMASK
- PDC_ADD_VALID
- PDC_ADD_VALID_VERIFY
- PDC_ALLOC
- PDC_ALTSTATUS
- PDC_AOP_SYNC_RESET
- PDC_APPS_SYNC_RESET
- PDC_ATA_CTL
- PDC_AUDIO_SYNC_RESET
- PDC_BAD_OPTION
- PDC_BAD_PROC
- PDC_BLOCK_TLB
- PDC_BROADCAST_RESET
- PDC_BR_RECONFIGURATION
- PDC_BTLB_INFO
- PDC_BTLB_INSERT
- PDC_BTLB_PURGE
- PDC_BTLB_PURGE_ALL
- PDC_BUFFER_SIZE
- PDC_BUS_POW_WARN
- PDC_BYTE_COUNT
- PDC_CACHE
- PDC_CACHE_INFO
- PDC_CACHE_RET_SPID
- PDC_CACHE_SET_COH
- PDC_CHASSIS
- PDC_CHASSIS_ACT_STATUS_UNSPEC
- PDC_CHASSIS_ALERT_BLOCKED
- PDC_CHASSIS_ALERT_CONF_CHG
- PDC_CHASSIS_ALERT_ENV_FATAL
- PDC_CHASSIS_ALERT_ENV_PB
- PDC_CHASSIS_ALERT_FORWARD
- PDC_CHASSIS_ALERT_FUNC_IMP
- PDC_CHASSIS_ALERT_HANG
- PDC_CHASSIS_ALERT_HW_FATAL
- PDC_CHASSIS_ALERT_NURGENT
- PDC_CHASSIS_ALERT_PENDING
- PDC_CHASSIS_ALERT_PERF_IMP
- PDC_CHASSIS_ALERT_SERPROC
- PDC_CHASSIS_ALERT_SOFT_FAIL
- PDC_CHASSIS_CALL_ACT_HPUX_BL
- PDC_CHASSIS_CALL_ACT_HPUX_DU
- PDC_CHASSIS_CALL_ACT_HPUX_EVENT
- PDC_CHASSIS_CALL_ACT_HPUX_INIT
- PDC_CHASSIS_CALL_ACT_HPUX_IO
- PDC_CHASSIS_CALL_ACT_HPUX_PANIC
- PDC_CHASSIS_CALL_ACT_HPUX_PD
- PDC_CHASSIS_CALL_ACT_HPUX_SHUT
- PDC_CHASSIS_CALL_ACT_HPUX_WARN
- PDC_CHASSIS_CALL_SACT_UNSPEC
- PDC_CHASSIS_DEBUG
- PDC_CHASSIS_DIRECT_BCOMPLETE
- PDC_CHASSIS_DIRECT_BSTART
- PDC_CHASSIS_DIRECT_DUMP
- PDC_CHASSIS_DIRECT_HPMC
- PDC_CHASSIS_DIRECT_LPMC
- PDC_CHASSIS_DIRECT_OOPS
- PDC_CHASSIS_DIRECT_PANIC
- PDC_CHASSIS_DIRECT_SHUTDOWN
- PDC_CHASSIS_DISP
- PDC_CHASSIS_DISPWARN
- PDC_CHASSIS_DISP_DATA
- PDC_CHASSIS_DT_ACTUAL
- PDC_CHASSIS_DT_ACT_LEV
- PDC_CHASSIS_DT_ASCII_MSG
- PDC_CHASSIS_DT_CODE_ADDR
- PDC_CHASSIS_DT_DATA_EXPECT
- PDC_CHASSIS_DT_DEV_STAT
- PDC_CHASSIS_DT_DEV_TYPE
- PDC_CHASSIS_DT_INTERRUPT
- PDC_CHASSIS_DT_NONE
- PDC_CHASSIS_DT_PA_LEGACY
- PDC_CHASSIS_DT_PB_DET
- PDC_CHASSIS_DT_PHYS_ADDR
- PDC_CHASSIS_DT_PHYS_LOC
- PDC_CHASSIS_DT_PHYS_LOC_EXT
- PDC_CHASSIS_DT_POST
- PDC_CHASSIS_DT_PROC_DEALLOC
- PDC_CHASSIS_DT_RESET
- PDC_CHASSIS_DT_REV_NUM
- PDC_CHASSIS_DT_SER_NUM
- PDC_CHASSIS_DT_STATE_CHG
- PDC_CHASSIS_DT_SYNDROME
- PDC_CHASSIS_DT_TAG
- PDC_CHASSIS_DT_TEST_NUM
- PDC_CHASSIS_DT_TIMESTAMP
- PDC_CHASSIS_EOM_CLEAR
- PDC_CHASSIS_EOM_SET
- PDC_CHASSIS_LED_ATTN_FLASH
- PDC_CHASSIS_LED_ATTN_NC
- PDC_CHASSIS_LED_ATTN_OFF
- PDC_CHASSIS_LED_FAULT_FLASH
- PDC_CHASSIS_LED_FAULT_NC
- PDC_CHASSIS_LED_FAULT_OFF
- PDC_CHASSIS_LED_FAULT_ON
- PDC_CHASSIS_LED_RUN_FLASH
- PDC_CHASSIS_LED_RUN_NC
- PDC_CHASSIS_LED_RUN_OFF
- PDC_CHASSIS_LED_RUN_ON
- PDC_CHASSIS_LED_VALID
- PDC_CHASSIS_LSTATE_BFAIL_NCRIT
- PDC_CHASSIS_LSTATE_CANNOT_PDC
- PDC_CHASSIS_LSTATE_FATAL_BFAIL
- PDC_CHASSIS_LSTATE_FATAL_NCRIT
- PDC_CHASSIS_LSTATE_NOCODE_NCRIT
- PDC_CHASSIS_LSTATE_NONOS
- PDC_CHASSIS_LSTATE_NONOS_BFAIL
- PDC_CHASSIS_LSTATE_NONOS_NCRIT
- PDC_CHASSIS_LSTATE_NONOS_UNEXP
- PDC_CHASSIS_LSTATE_RUN_CRASHREC
- PDC_CHASSIS_LSTATE_RUN_NCRIT
- PDC_CHASSIS_LSTATE_RUN_NORMAL
- PDC_CHASSIS_LSTATE_RUN_SYSINT
- PDC_CHASSIS_LSTATE_UNEXP_NCRIT
- PDC_CHASSIS_MSG_ID
- PDC_CHASSIS_PB_D_PROC_NONE
- PDC_CHASSIS_PB_D_PROC_TIMEOUT
- PDC_CHASSIS_PMSG_BCOMPLETE
- PDC_CHASSIS_PMSG_BSTART
- PDC_CHASSIS_PMSG_HPMC
- PDC_CHASSIS_PMSG_LPMC
- PDC_CHASSIS_PMSG_PANIC
- PDC_CHASSIS_PMSG_SHUTDOWN
- PDC_CHASSIS_REID_UNSPEC
- PDC_CHASSIS_RET_DIAG
- PDC_CHASSIS_RET_GENERICOS
- PDC_CHASSIS_RET_HPUX
- PDC_CHASSIS_RET_IA64_NT
- PDC_CHASSIS_SRC_CELL
- PDC_CHASSIS_SRC_D_PROC
- PDC_CHASSIS_SRC_FAB
- PDC_CHASSIS_SRC_ID_UNSPEC
- PDC_CHASSIS_SRC_IO
- PDC_CHASSIS_SRC_MEM
- PDC_CHASSIS_SRC_NONE
- PDC_CHASSIS_SRC_PD
- PDC_CHASSIS_SRC_PDH
- PDC_CHASSIS_SRC_PLATi
- PDC_CHASSIS_SRC_PROC
- PDC_CHASSIS_SRC_PROC_CACHE
- PDC_CHASSIS_SRC_PWR
- PDC_CHASSIS_SYSTATE_BCOMP
- PDC_CHASSIS_SYSTATE_BSTART
- PDC_CHASSIS_SYSTATE_CHANGE
- PDC_CHASSIS_SYSTATE_DUMP
- PDC_CHASSIS_SYSTATE_HALT
- PDC_CHASSIS_SYSTATE_HPMC
- PDC_CHASSIS_SYSTATE_LED
- PDC_CHASSIS_SYSTATE_PANIC
- PDC_CHASSIS_VER
- PDC_CHASSIS_WARN
- PDC_CHECK_RANGES
- PDC_CHIP0_OFS
- PDC_CKSUM_CTRL
- PDC_CKSUM_CTRL_OFFSET
- PDC_COMMAND
- PDC_COMMON_FLAGS
- PDC_COMPUTE_SYNC_RESET
- PDC_CONFIG
- PDC_CONFIG_DECONFIG
- PDC_CONFIG_DRECONFIG
- PDC_CONFIG_DRETURN_CONFIG
- PDC_CONSOLE_IO_IODC_SIZE
- PDC_CONS_POLL_DELAY
- PDC_COPROC
- PDC_COPROC_CFG
- PDC_CRASH_DUMP
- PDC_CRASH_LOG_CEC_ERROR
- PDC_CRASH_PREP
- PDC_CTCR0
- PDC_CTCR1
- PDC_CTLSTAT
- PDC_CTL_STATUS
- PDC_CYLINDER_HIGH
- PDC_CYLINDER_LOW
- PDC_DEBUG
- PDC_DEBUG_SYNC_RESET
- PDC_DELETE_INITIATOR
- PDC_DEVICE
- PDC_DEVICE_SATA
- PDC_DEV_ADDR
- PDC_DH_ERR
- PDC_DIMM0_CONTROL
- PDC_DIMM0_SPD_DEV_ADDRESS
- PDC_DIMM1_CONTROL
- PDC_DIMM1_SPD_DEV_ADDRESS
- PDC_DIMM_APKT_PRD
- PDC_DIMM_ATA_PKT
- PDC_DIMM_BAR
- PDC_DIMM_DATA_STEP
- PDC_DIMM_HEADER_SZ
- PDC_DIMM_HOST_PKT
- PDC_DIMM_HOST_PRD
- PDC_DIMM_HPKT_PRD
- PDC_DIMM_SPD_ACTIVE_PRECHARGE
- PDC_DIMM_SPD_ATTRIBUTE
- PDC_DIMM_SPD_BANK_NUM
- PDC_DIMM_SPD_CAS_LATENCY
- PDC_DIMM_SPD_COLUMN_NUM
- PDC_DIMM_SPD_FRESH_RATE
- PDC_DIMM_SPD_MODULE_ROW
- PDC_DIMM_SPD_RAS_CAS_DELAY
- PDC_DIMM_SPD_ROW_ACTIVE_DELAY
- PDC_DIMM_SPD_ROW_NUM
- PDC_DIMM_SPD_ROW_PRE_CHARGE
- PDC_DIMM_SPD_SUBADDRESS_END
- PDC_DIMM_SPD_SUBADDRESS_START
- PDC_DIMM_SPD_SYSTEM_FREQ
- PDC_DIMM_SPD_TYPE
- PDC_DIMM_WINDOW_CTLR
- PDC_DIMM_WINDOW_STEP
- PDC_DISPLAY_SYNC_RESET
- PDC_DMA_BUF_MAX
- PDC_DMA_ENABLE
- PDC_DO_FIRM_TEST_RESET
- PDC_DO_RESET
- PDC_DRIVE_ERR
- PDC_EDGE_DUAL
- PDC_EDGE_FALLING
- PDC_EDGE_RISING
- PDC_EEPROM
- PDC_EEPROM_EEPROM_PASSWORD
- PDC_EEPROM_READ_BYTE
- PDC_EEPROM_READ_WORD
- PDC_EEPROM_WRITE_BYTE
- PDC_EEPROM_WRITE_WORD
- PDC_ERROR
- PDC_ERR_MASK
- PDC_FEATURE
- PDC_FEATURE_ATAPI_DMA
- PDC_FEATURE_ATAPI_PIO
- PDC_FIND_ADDRESS
- PDC_FIND_MODULE
- PDC_FIRM_TEST_MAGIC
- PDC_FIRST_BUF
- PDC_FLAG_4_PORTS
- PDC_FLAG_GEN_II
- PDC_FLAG_SATA_PATA
- PDC_FLASH_CTL
- PDC_FPDMA_CTLSTAT
- PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG
- PDC_FPDMA_CTLSTAT_RESET
- PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG
- PDC_GENERAL_CTLR
- PDC_GET_INITIATOR
- PDC_GLOBAL_CTL
- PDC_GPU_SYNC_RESET
- PDC_HAS_PATA
- PDC_HDMA_CTLSTAT
- PDC_HDMA_PKT_SUBMIT
- PDC_HDMA_Q_MASK
- PDC_HPA
- PDC_HPA_MODULES
- PDC_HPA_PROCESSOR
- PDC_HW
- PDC_I2C_ADDR_DATA
- PDC_I2C_COMPLETE
- PDC_I2C_CONTROL
- PDC_I2C_MASK_INT
- PDC_I2C_NO_ACK
- PDC_I2C_READ
- PDC_I2C_START
- PDC_I2C_WRITE
- PDC_INITIATOR
- PDC_INSTR
- PDC_INTERNAL_DEBUG_1
- PDC_INTERNAL_DEBUG_2
- PDC_INTMASK
- PDC_INTMASK_OFFSET
- PDC_INTRIGUE
- PDC_INTRIGUE_GET_SCRATCH_BUFSIZE
- PDC_INTRIGUE_START_CPU_COUNTERS
- PDC_INTRIGUE_STOP_CPU_COUNTERS
- PDC_INTRIGUE_WRITE_BUFFER
- PDC_INTSTATUS_OFFSET
- PDC_INT_SEQMASK
- PDC_INVALID_ARG
- PDC_IO
- PDC_IODC
- PDC_IODC_BUS_ERROR
- PDC_IODC_COUNT
- PDC_IODC_DINIT
- PDC_IODC_INDEX_DATA
- PDC_IODC_INVALID_INDEX
- PDC_IODC_MEMERR
- PDC_IODC_NINIT
- PDC_IODC_READ
- PDC_IODC_RI_CONFIG
- PDC_IODC_RI_DATA_BYTES
- PDC_IODC_RI_INIT
- PDC_IODC_RI_IO
- PDC_IODC_RI_SPA
- PDC_IODC_RI_TEST
- PDC_IODC_RI_TLB
- PDC_IO_EEPROM_IO_ERR_TABLE_FULL
- PDC_IO_NO_SUSPEND
- PDC_IO_READ_AND_CLEAR_ERRORS
- PDC_IO_RESET
- PDC_IO_RESET_DEVICES
- PDC_IO_USB_SUSPEND
- PDC_IRQ_CLEAR
- PDC_IRQ_DISABLE
- PDC_IRQ_ENABLE
- PDC_IRQ_ROUTE
- PDC_IRQ_ROUTE_EXT_EN_IR
- PDC_IRQ_ROUTE_EXT_EN_RTC
- PDC_IRQ_ROUTE_EXT_EN_SYS0
- PDC_IRQ_ROUTE_EXT_EN_SYS1
- PDC_IRQ_ROUTE_EXT_EN_SYS2
- PDC_IRQ_ROUTE_EXT_EN_SYS3
- PDC_IRQ_ROUTE_EXT_EN_WD
- PDC_IRQ_ROUTE_WU_EN_IR
- PDC_IRQ_ROUTE_WU_EN_RTC
- PDC_IRQ_ROUTE_WU_EN_SYS0
- PDC_IRQ_ROUTE_WU_EN_SYS1
- PDC_IRQ_ROUTE_WU_EN_SYS2
- PDC_IRQ_ROUTE_WU_EN_SYS3
- PDC_IRQ_ROUTE_WU_EN_WD
- PDC_IRQ_STATUS
- PDC_IRQ_SYS0
- PDC_IRQ_SYS1
- PDC_IRQ_SYS2
- PDC_IRQ_SYS3
- PDC_LAN_STATION_ID
- PDC_LAN_STATION_ID_READ
- PDC_LAN_STATION_ID_SIZE
- PDC_LAST_REG
- PDC_LAZY_FRAMECOUNT
- PDC_LAZY_INT
- PDC_LAZY_TIMEOUT
- PDC_LEVEL_HIGH
- PDC_LEVEL_LOW
- PDC_LINK
- PDC_LINK_LAYER_ERRORS
- PDC_LINK_PCI_ENTRY_POINTS
- PDC_LINK_USB_ENTRY_POINTS
- PDC_MASK_INT
- PDC_MAX_HDMA
- PDC_MAX_IRQS
- PDC_MAX_PORTS
- PDC_MAX_PRD
- PDC_MEM
- PDC_MEM_ADDR
- PDC_MEM_ADD_PAGE
- PDC_MEM_CLEAR_PDT
- PDC_MEM_GET_MEMORY_SYSTEM_TABLES
- PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE
- PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS
- PDC_MEM_GOODMEM
- PDC_MEM_MAP
- PDC_MEM_MAP_HPA
- PDC_MEM_MEMINFO
- PDC_MEM_READ_PDT
- PDC_MEM_RESET_CLEAR
- PDC_MEM_RETURN_ADDRESS_TABLE
- PDC_MEM_RET_BUF_SIZE_SMALL
- PDC_MEM_RET_DUPLICATE_ENTRY
- PDC_MEM_RET_INVALID_PHYSICAL_LOCATION
- PDC_MEM_RET_PDT_FULL
- PDC_MEM_RET_SBE_REPLACED
- PDC_MEM_TABLE
- PDC_MMIO_BAR
- PDC_MODEL
- PDC_MODEL_BOOTID
- PDC_MODEL_CAPABILITIES
- PDC_MODEL_CPU_ID
- PDC_MODEL_DISPEC
- PDC_MODEL_ENSPEC
- PDC_MODEL_GET_BOOT__OP
- PDC_MODEL_GET_INSTALL_KERNEL
- PDC_MODEL_GET_PLATFORM_INFO
- PDC_MODEL_INFO
- PDC_MODEL_IOPDIR_FDC
- PDC_MODEL_NVA_MASK
- PDC_MODEL_NVA_SLOW
- PDC_MODEL_NVA_SUPPORTED
- PDC_MODEL_NVA_UNSUPPORTED
- PDC_MODEL_OS32
- PDC_MODEL_OS64
- PDC_MODEL_SET_BOOT__OP
- PDC_MODEL_SYSMODEL
- PDC_MODEL_VERSIONS
- PDC_MODEM_SYNC_RESET
- PDC_NEXT
- PDC_NE_BOOTDEV
- PDC_NE_CELL_MOD
- PDC_NE_MOD
- PDC_NOT_NARROW
- PDC_NUM_DMA_RINGS
- PDC_NVM
- PDC_NVM_READ_BYTE
- PDC_NVM_READ_WORD
- PDC_NVM_WRITE_BYTE
- PDC_NVM_WRITE_WORD
- PDC_NVOLATILE
- PDC_NVOLATILE_INITIALIZE
- PDC_NVOLATILE_READ
- PDC_NVOLATILE_RETURN_SIZE
- PDC_NVOLATILE_VERIFY_CONTENTS
- PDC_NVOLATILE_WRITE
- PDC_NV_SECTIONS
- PDC_OK
- PDC_OS_BOOT_RENDEZVOUS
- PDC_OS_BOOT_RENDEZVOUS_HI
- PDC_OVERRUN_ERR
- PDC_PAGE_ADJ_SHIFT
- PDC_PAGE_DATA
- PDC_PAGE_SET
- PDC_PAGE_WINDOW
- PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ
- PDC_PAT_CAPABILITY_BIT_PDC_IODC_32
- PDC_PAT_CAPABILITY_BIT_PDC_IODC_64
- PDC_PAT_CAPABILITY_BIT_PDC_NBC
- PDC_PAT_CAPABILITY_BIT_PDC_POLLING
- PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE
- PDC_PAT_CAPABILITY_BIT_PDC_UFO
- PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB
- PDC_PAT_CELL
- PDC_PAT_CELL_CHANGE_ALIAS
- PDC_PAT_CELL_GET_DBG_INFO
- PDC_PAT_CELL_GET_INFO
- PDC_PAT_CELL_GET_LOCAL_PDH_SZ
- PDC_PAT_CELL_GET_NUMBER
- PDC_PAT_CELL_GET_RDT
- PDC_PAT_CELL_GET_RDT_SIZE
- PDC_PAT_CELL_GET_REMOTE_PDH
- PDC_PAT_CELL_GET_REMOTE_PDH_SZ
- PDC_PAT_CELL_MODULE
- PDC_PAT_CELL_NUMBER_TO_LOC
- PDC_PAT_CELL_SET_ATTENTION
- PDC_PAT_CELL_SET_LOCAL_PDH
- PDC_PAT_CELL_WALK_FABRIC
- PDC_PAT_CHASSIS_LOG
- PDC_PAT_CHASSIS_READ_LOG
- PDC_PAT_CHASSIS_WRITE_LOG
- PDC_PAT_COMPLEX
- PDC_PAT_CPU
- PDC_PAT_CPU_ADD
- PDC_PAT_CPU_DELETE
- PDC_PAT_CPU_GET_CLOCK_INFO
- PDC_PAT_CPU_GET_HPA
- PDC_PAT_CPU_GET_NUMBER
- PDC_PAT_CPU_GET_RENDEZVOUS_STATE
- PDC_PAT_CPU_INFO
- PDC_PAT_CPU_PLUNGE_FABRIC
- PDC_PAT_CPU_RENDEZVOUS
- PDC_PAT_CPU_STOP
- PDC_PAT_CPU_UPDATE_CACHE_CLEANSING
- PDC_PAT_EVENT
- PDC_PAT_EVENT_GET_CAPS
- PDC_PAT_EVENT_GET_NB_CALL
- PDC_PAT_EVENT_HANDLE
- PDC_PAT_EVENT_SCAN
- PDC_PAT_EVENT_SET_MODE
- PDC_PAT_HPMC
- PDC_PAT_HPMC_RENDEZ_CPU
- PDC_PAT_HPMC_SET_PARAMS
- PDC_PAT_IO
- PDC_PAT_IO_BAY_STATUS_INFO
- PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO
- PDC_PAT_IO_GET_HARDWARE_FROM_LOC
- PDC_PAT_IO_GET_HINT_TABLE
- PDC_PAT_IO_GET_HINT_TABLE_SIZE
- PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG
- PDC_PAT_IO_GET_LOC_FROM_HARDWARE
- PDC_PAT_IO_GET_LOC_IO_SLOTS
- PDC_PAT_IO_GET_NUM_IO_SLOTS
- PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW
- PDC_PAT_IO_GET_PCI_ROUTING_TABLE
- PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE
- PDC_PAT_IO_GET_PROC_VIEW
- PDC_PAT_IO_GET_SLOT_STATUS
- PDC_PAT_IO_PCI_CONFIG_READ
- PDC_PAT_IO_PCI_CONFIG_WRITE
- PDC_PAT_IO_PROG_SBA_DIR_RANGE
- PDC_PAT_IO_READ_HOST_BRIDGE_INFO
- PDC_PAT_MEM
- PDC_PAT_MEM_ADDRESS
- PDC_PAT_MEM_ADD_PAGE
- PDC_PAT_MEM_CELL_CLEAR
- PDC_PAT_MEM_CELL_INFO
- PDC_PAT_MEM_CELL_READ
- PDC_PAT_MEM_CELL_RESET
- PDC_PAT_MEM_CLEAN_RANGE
- PDC_PAT_MEM_CLR_STATE_INFO
- PDC_PAT_MEM_GET_CELL_TXT
- PDC_PAT_MEM_GET_PD_TXT
- PDC_PAT_MEM_GET_TBL
- PDC_PAT_MEM_GET_TBL_SIZE
- PDC_PAT_MEM_GET_TXT_SIZE
- PDC_PAT_MEM_PD_CLEAR
- PDC_PAT_MEM_PD_INFO
- PDC_PAT_MEM_PD_READ
- PDC_PAT_MEM_PD_RESET
- PDC_PAT_MEM_RD_STATE_INFO
- PDC_PAT_MEM_SETGM
- PDC_PAT_NVOLATILE
- PDC_PAT_NVOLATILE_GET_SIZE
- PDC_PAT_NVOLATILE_INIT
- PDC_PAT_NVOLATILE_READ
- PDC_PAT_NVOLATILE_VERIFY
- PDC_PAT_NVOLATILE_WRITE
- PDC_PAT_PD
- PDC_PAT_PD_GET_ADDR_MAP
- PDC_PAT_PD_GET_PDC_INTERF_REV
- PDC_PAT_REGISTER_TOC
- PDC_PAT_SYSTEM_INFO
- PDC_PAT_TOC_READ_VECTOR
- PDC_PAT_TOC_REGISTER_VECTOR
- PDC_PCI_CTL
- PDC_PCI_GET_INT_TBL
- PDC_PCI_GET_INT_TBL_SIZE
- PDC_PCI_INDEX
- PDC_PCI_INFLIGHT_BYTES
- PDC_PCI_INTERFACE_INFO
- PDC_PCI_PCI_HPA_TO_PCI_PATH
- PDC_PCI_PCI_INT_ROUTE
- PDC_PCI_PCI_INT_ROUTE_SIZE
- PDC_PCI_PCI_PATH_TO_PCI_BUS
- PDC_PCI_PCI_PATH_TO_PCI_HPA
- PDC_PCI_PCI_RESERVED
- PDC_PCI_READ_CONFIG
- PDC_PCI_READ_CONFIG_DELAY
- PDC_PCI_READ_MON_TYPE
- PDC_PCI_READ_PCI_IO
- PDC_PCI_SLOT_INFO
- PDC_PCI_SYS_ERR
- PDC_PCI_UPDATE_CONFIG_DELAY
- PDC_PCI_WRITE_CONFIG
- PDC_PCI_WRITE_MON_TYPE
- PDC_PCI_WRITE_PCI_IO
- PDC_PERFORMANCE
- PDC_PHYMODE4
- PDC_PH_ERR
- PDC_PIM
- PDC_PIM_HPMC
- PDC_PIM_LPMC
- PDC_PIM_RETURN_SIZE
- PDC_PIM_SOFT_BOOT
- PDC_PIM_TOC
- PDC_PKT_CLEAR_BSY
- PDC_PKT_NODATA
- PDC_PKT_READ
- PDC_PKT_SIZEMASK
- PDC_PKT_SUBMIT
- PDC_PKT_WAIT_DRDY
- PDC_PLL_CTL
- PDC_POW_FAIL
- PDC_POW_FAIL_PREPARE
- PDC_PRD_TBL
- PDC_PROC
- PDC_PSW
- PDC_PSW_ENDIAN_BIT
- PDC_PSW_GET_DEFAULTS
- PDC_PSW_MASK
- PDC_PSW_SET_DEFAULTS
- PDC_PSW_WIDE_BIT
- PDC_RCVINTEN_0
- PDC_RCVINT_0
- PDC_RCVLAZY0_OFFSET
- PDC_RDR
- PDC_RDR_READ_BUFFER
- PDC_RDR_READ_SINGLE
- PDC_RDR_WRITE_SINGLE
- PDC_REG_DEVCTL
- PDC_RELOCATE
- PDC_RELOCATE_CHECKSUM
- PDC_RELOCATE_GET_RELOCINFO
- PDC_RELOCATE_RELOCATE
- PDC_REQ_ERR_0
- PDC_REQ_ERR_1
- PDC_RESET
- PDC_RETURN_CHASSIS_INFO
- PDC_RETURN_TABLE
- PDC_RETURN_TABLE_SIZE
- PDC_RINGSET
- PDC_RING_ENTRIES
- PDC_RING_SIZE
- PDC_RING_SPACE_MIN
- PDC_RXREGS_OFFSET
- PDC_RX_CTL
- PDC_RX_ENABLE
- PDC_RX_TIMEOUT
- PDC_SATA_ERROR
- PDC_SATA_PLUG_CSR
- PDC_SCSI_GET_PARMS
- PDC_SCSI_PARMS
- PDC_SCSI_SET_PARMS
- PDC_SDRAM_CONTROL
- PDC_SECOND_BUF
- PDC_SECTOR_COUNT
- PDC_SECTOR_NUMBER
- PDC_SEED_ERROR
- PDC_SENSORS_SYNC_RESET
- PDC_SEQCNTRL_INT_MASK
- PDC_SET_INITIATOR
- PDC_SHM_SIZE
- PDC_SH_ERR
- PDC_SIZE
- PDC_SLEW_CTL
- PDC_SOFT_POWER
- PDC_SOFT_POWER_ENABLE
- PDC_SOFT_POWER_INFO
- PDC_SPU2_RESP_HDR_LEN
- PDC_SPUM_RESP_HDR_LEN
- PDC_SP_SYNC_RESET
- PDC_STABLE
- PDC_STABLE_INITIALIZE
- PDC_STABLE_READ
- PDC_STABLE_RETURN_SIZE
- PDC_STABLE_VERIFY_CONTENTS
- PDC_STABLE_WRITE
- PDC_STI
- PDC_SUCCESS
- PDC_SYSINFO_RETURN_INFO_SIZE
- PDC_SYSINFO_RETURN_REVISIONS
- PDC_SYSINFO_RRETURN_DIAGNOSE
- PDC_SYSINFO_RRETURN_ERRORS
- PDC_SYSINFO_RRETURN_HV_DIAGNOSE
- PDC_SYSINFO_RRETURN_SYS_INFO
- PDC_SYSINFO_RRETURN_WARNINGS
- PDC_SYSTEM_INFO
- PDC_SYSTEM_MAP
- PDC_SYS_CTL
- PDC_SYS_WAKE_BASE
- PDC_SYS_WAKE_CONFIG_BASE
- PDC_SYS_WAKE_CONFIG_STRIDE
- PDC_SYS_WAKE_INT_CHANGE
- PDC_SYS_WAKE_INT_DOWN
- PDC_SYS_WAKE_INT_HIGH
- PDC_SYS_WAKE_INT_LOW
- PDC_SYS_WAKE_INT_MODE
- PDC_SYS_WAKE_INT_MODE_SHIFT
- PDC_SYS_WAKE_INT_NONE
- PDC_SYS_WAKE_INT_UP
- PDC_SYS_WAKE_PIN_VAL
- PDC_SYS_WAKE_RESET
- PDC_SYS_WAKE_STRIDE
- PDC_TBG_MODE
- PDC_TIMER_BUZZER
- PDC_TIMER_DEFAULT
- PDC_TIMER_ENABLE
- PDC_TIMER_MASK_INT
- PDC_TIMER_MODE_ONCE
- PDC_TIMER_MODE_PERIODIC
- PDC_TIMER_SEQ_MASK
- PDC_TIME_CONTROL
- PDC_TIME_COUNTER
- PDC_TIME_PERIOD
- PDC_TLB
- PDC_TLB_INFO
- PDC_TLB_SETUP
- PDC_TOD
- PDC_TOD_CALIBRATE
- PDC_TOD_READ
- PDC_TOD_WRITE
- PDC_TRANSLATE_PATH
- PDC_TXREGS_OFFSET
- PDC_TX_CTL
- PDC_TX_ENABLE
- PDC_TYPE_ILLEGAL
- PDC_TYPE_PAT
- PDC_TYPE_SNAKE
- PDC_TYPE_SYSTEM_MAP
- PDC_UDMA_100
- PDC_UDMA_133
- PDC_UNDERRUN_ERR
- PDC_WARN
- PDC_WDT_CONFIG
- PDC_WDT_CONFIG_DELAY_MASK
- PDC_WDT_CONFIG_ENABLE
- PDC_WDT_DEF_TIMEOUT
- PDC_WDT_MIN_TIMEOUT
- PDC_WDT_SOFT_RESET
- PDC_WDT_TICKLE1
- PDC_WDT_TICKLE1_MAGIC
- PDC_WDT_TICKLE2
- PDC_WDT_TICKLE2_MAGIC
- PDC_WDT_TICKLE_STATUS_HRESET
- PDC_WDT_TICKLE_STATUS_MASK
- PDC_WDT_TICKLE_STATUS_SHIFT
- PDC_WDT_TICKLE_STATUS_SRESET
- PDC_WDT_TICKLE_STATUS_TICKLE
- PDC_WDT_TICKLE_STATUS_TIMEOUT
- PDC_WDT_TICKLE_STATUS_USER
- PDDATA
- PDDATA_ADDR
- PDDIR
- PDDIR_ADDR
- PDDR
- PDD_BOUND
- PDD_BOUND_SUSPENDED
- PDD_UNBOUND
- PDE
- PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
- PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT
- PDEBUG
- PDEBUG2
- PDEBUGV
- PDEBUG_FACILITIES
- PDEBUG_MODE
- PDECODE
- PDELCTRL1
- PDELCTRL2
- PDELCTRL3
- PDET_LINK_WAIT
- PDEVB_op_active
- PDEVF_op_active
- PDEV_DEFAULT_STATS_UPDATE_PERIOD
- PDEV_OVERLAY
- PDEV_STAT
- PDEV_STAT_IDLE
- PDEV_STAT_RUN
- PDE_BIT
- PDE_DATA
- PDE_IDENT_ATTR
- PDE_NET
- PDE_PFN_MASK
- PDFLT
- PDF_ACK0_CAPABLE
- PDF_CLASS_2
- PDF_FCP2_CONF
- PDF_FC_TAPE
- PDF_HARD_ADDR
- PDF_HAS_CHANNEL_ID
- PDF_HAS_LUN_ID
- PDF_HAS_TARGET_ID
- PDF_HAS_VIRT_HOST_ID
- PDF_HAS_VPD_DEV_IDENT
- PDF_HAS_VPD_UNIT_SERIAL
- PDF_TASK_RETRY_ID
- PDINFO
- PDIQEG
- PDIQEG_ADDR
- PDIRQEN
- PDIRQEN_ADDR
- PDIR_ENTRY_SIZE
- PDIR_INDEX
- PDIR_SEARCH_TIMING
- PDIST_OPF
- PDIV_MASK
- PDIV_SHIFT
- PDI_AUXDATA
- PDI_END
- PDI_LOSS
- PDI_ORIGDEV
- PDI_RUNNING
- PDI_VNETHDR
- PDKBEN
- PDKBEN_ADDR
- PDM0_DATA
- PDM0_OUTCLK_236
- PDM0_OUTCLK_6
- PDM0_OUTDATA_239
- PDM0_OUTDATA_7
- PDM1_DATA
- PDM1_OUTCLK_133
- PDM1_OUTCLK_8
- PDM1_OUTDATA_128
- PDM1_OUTDATA_9
- PDM2_CLK_0
- PDM2_CLK_282
- PDM2_CLK_SRC
- PDM2_DATA_1
- PDM2_DATA_281
- PDM3_CLK_2
- PDM3_CLK_234
- PDM3_DATA_235
- PDM3_DATA_3
- PDM4_CLK_125
- PDM4_CLK_4
- PDM4_DATA_130
- PDM4_DATA_5
- PDMACHCR
- PDMACHCR_DE
- PDMADAR
- PDMASAR
- PDMA_ALIGNMENT
- PDMA_DESCR_COUNT
- PDMA_Def
- PDMA_FILTER_PARAM
- PDMA_IH_SRC_ID_END
- PDMA_IH_SRC_ID_START
- PDMA_IN_BUF_CFG_DATA_BUF_SIZE
- PDMA_IN_BUF_CFG_DESCR_BUF_SIZE
- PDMA_IN_BUF_CFG_STAT_BUF_SIZE
- PDMA_IN_CFG_EN
- PDMA_IN_CMD_START
- PDMA_IN_DESCRQ_PUSH_ADDR
- PDMA_IN_DESCRQ_PUSH_LEN
- PDMA_IN_DESCRQ_STAT_LEVEL
- PDMA_IN_DESCRQ_STAT_SIZE
- PDMA_IN_STATQ_PUSH_ADDR
- PDMA_IN_STATQ_PUSH_LEN
- PDMA_MAX_DESC_BYTES
- PDMA_Mask
- PDMA_OUT_BUF_CFG
- PDMA_OUT_BUF_CFG_DATA_BUF_SIZE
- PDMA_OUT_BUF_CFG_DESCR_BUF_SIZE
- PDMA_OUT_CFG
- PDMA_OUT_CFG_EN
- PDMA_OUT_CMD
- PDMA_OUT_CMD_START
- PDMA_OUT_DESCRQ_PUSH
- PDMA_OUT_DESCRQ_PUSH_ADDR
- PDMA_OUT_DESCRQ_PUSH_LEN
- PDMA_OUT_DESCRQ_STAT
- PDMA_OUT_DESCRQ_STAT_LEVEL
- PDMA_OUT_DESCRQ_STAT_SIZE
- PDMA_Print
- PDMA_READ
- PDMA_Read
- PDMA_Val
- PDMA_WRITE
- PDMA_Write
- PDMIC_CDR
- PDMIC_CR
- PDMIC_CR_ENPDM_DIS
- PDMIC_CR_ENPDM_EN
- PDMIC_CR_ENPDM_MASK
- PDMIC_CR_ENPDM_SHIFT
- PDMIC_CR_SWRST
- PDMIC_CR_SWRST_MASK
- PDMIC_CR_SWRST_SHIFT
- PDMIC_DSPR0
- PDMIC_DSPR0_HPFBYP_DIS
- PDMIC_DSPR0_HPFBYP_EN
- PDMIC_DSPR0_HPFBYP_MASK
- PDMIC_DSPR0_HPFBYP_SHIFT
- PDMIC_DSPR0_OSR_128
- PDMIC_DSPR0_OSR_64
- PDMIC_DSPR0_OSR_MASK
- PDMIC_DSPR0_OSR_SHIFT
- PDMIC_DSPR0_SCALE_MASK
- PDMIC_DSPR0_SCALE_SHIFT
- PDMIC_DSPR0_SHIFT_MASK
- PDMIC_DSPR0_SHIFT_SHIFT
- PDMIC_DSPR0_SINBYP_DIS
- PDMIC_DSPR0_SINBYP_EN
- PDMIC_DSPR0_SINBYP_MASK
- PDMIC_DSPR0_SINBYP_SHIFT
- PDMIC_DSPR0_SIZE_16_BITS
- PDMIC_DSPR0_SIZE_32_BITS
- PDMIC_DSPR0_SIZE_MASK
- PDMIC_DSPR0_SIZE_SHIFT
- PDMIC_DSPR1
- PDMIC_DSPR1_DGAIN_MASK
- PDMIC_DSPR1_DGAIN_SHIFT
- PDMIC_DSPR1_OFFSET_MASK
- PDMIC_DSPR1_OFFSET_SHIFT
- PDMIC_IDR
- PDMIC_IDR_OVRE
- PDMIC_IER
- PDMIC_IER_OVRE
- PDMIC_IMR
- PDMIC_ISR
- PDMIC_ISR_OVRE
- PDMIC_MR
- PDMIC_MR_CLKS_GCK
- PDMIC_MR_CLKS_MASK
- PDMIC_MR_CLKS_PCK
- PDMIC_MR_CLKS_SHIFT
- PDMIC_MR_PRESCAL_MASK
- PDMIC_MR_PRESCAL_MAX_VAL
- PDMIC_MR_PRESCAL_SHIFT
- PDMIC_OFFSET_MAX_VAL
- PDMIC_OFFSET_MIN_VAL
- PDMIC_WPMR
- PDMIC_WPSR
- PDM_CHAN_CTRL
- PDM_CHAN_CTRL1
- PDM_CHAN_CTRL_NUM
- PDM_CHAN_CTRL_POINTER_MAX
- PDM_CHAN_CTRL_POINTER_WIDTH
- PDM_CKP_INVERTED
- PDM_CKP_MSK
- PDM_CKP_NORMAL
- PDM_CLK
- PDM_CLKG_CTRL
- PDM_CLK_1280FS
- PDM_CLK_2560FS
- PDM_CLK_320FS
- PDM_CLK_5120FS
- PDM_CLK_640FS
- PDM_CLK_CTRL
- PDM_CLK_DIS
- PDM_CLK_EN
- PDM_CLK_FD_RATIO_35
- PDM_CLK_FD_RATIO_40
- PDM_CLK_FD_RATIO_MSK
- PDM_CLK_MSK
- PDM_CNTL_1__BaseCoreTdpLimit0_MASK
- PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT
- PDM_CNTL_1__BaseCoreTdpLimit1_MASK
- PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT
- PDM_CNTL_1__BaseCoreTdpLimit2_MASK
- PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT
- PDM_CNTL_1__GpuPdmMult_MASK
- PDM_CNTL_1__GpuPdmMult__SHIFT
- PDM_CNTL_2__CoolPdmTc_MASK
- PDM_CNTL_2__CoolPdmTc__SHIFT
- PDM_CNTL_2__GpuActThr_MASK
- PDM_CNTL_2__GpuActThr__SHIFT
- PDM_CNTL_2__GpuPdmTc_MASK
- PDM_CNTL_2__GpuPdmTc__SHIFT
- PDM_CNTL_2__HeatPdmTc_MASK
- PDM_CNTL_2__HeatPdmTc__SHIFT
- PDM_CNTL_3__CoolPdmThr1_MASK
- PDM_CNTL_3__CoolPdmThr1__SHIFT
- PDM_CNTL_3__CoolPdmThr2_MASK
- PDM_CNTL_3__CoolPdmThr2__SHIFT
- PDM_CNTL_3__HeatPdmThr1_MASK
- PDM_CNTL_3__HeatPdmThr1__SHIFT
- PDM_CNTL_3__HeatPdmThr2_MASK
- PDM_CNTL_3__HeatPdmThr2__SHIFT
- PDM_COEFF_ADDR
- PDM_COEFF_DATA
- PDM_CTRL
- PDM_CTRL0
- PDM_CTRL1
- PDM_CTRL_BYPASS_MODE
- PDM_CTRL_CHAN_EN
- PDM_CTRL_CHAN_EN_MASK
- PDM_CTRL_CHAN_RSTN
- PDM_CTRL_CHAN_RSTN_MASK
- PDM_CTRL_EN
- PDM_CTRL_OUT_MODE
- PDM_CTRL_RST_FIFO
- PDM_DATA_VALID
- PDM_DMA_BURST_SIZE
- PDM_DMA_CTRL
- PDM_DMA_RDL
- PDM_DMA_RDL_MSK
- PDM_DMA_RD_DIS
- PDM_DMA_RD_EN
- PDM_DMA_RD_MSK
- PDM_DS_RATIO_MSK
- PDM_F1_CTRL
- PDM_F2_CTRL
- PDM_F3_CTRL
- PDM_FD_DENOMINATOR_MSK
- PDM_FD_DENOMINATOR_SFT
- PDM_FD_NUMERATOR_MSK
- PDM_FD_NUMERATOR_SFT
- PDM_FIFO_CTRL
- PDM_FILTER_EN
- PDM_HCIC_CTRL1
- PDM_HCIC_CTRL1_DSR
- PDM_HCIC_CTRL1_DSR_MASK
- PDM_HCIC_CTRL1_GAIN_MULT
- PDM_HCIC_CTRL1_GAIN_MULT_MASK
- PDM_HCIC_CTRL1_GAIN_SFT
- PDM_HCIC_CTRL1_GAIN_SFT_MASK
- PDM_HCIC_CTRL1_STAGE_NUM
- PDM_HCIC_CTRL1_STAGE_NUM_MASK
- PDM_HCIC_CTRL2
- PDM_HPF_243HZ
- PDM_HPF_3P79HZ
- PDM_HPF_493HZ
- PDM_HPF_60HZ
- PDM_HPF_CF_MSK
- PDM_HPF_CTRL
- PDM_HPF_LE
- PDM_HPF_OUT_FACTOR
- PDM_HPF_OUT_FACTOR_MASK
- PDM_HPF_RE
- PDM_HPF_SFT_STEPS
- PDM_HPF_SFT_STEPS_MASK
- PDM_HWT_EN
- PDM_INT_CLR
- PDM_INT_EN
- PDM_INT_ST
- PDM_LPF_DSR
- PDM_LPF_DSR_MASK
- PDM_LPF_MAX_STAGE
- PDM_LPF_NUM
- PDM_LPF_ROUND_MODE
- PDM_LPF_ROUND_MODE_MASK
- PDM_LPF_STAGE_NUM
- PDM_LPF_STAGE_NUM_MASK
- PDM_MODE_LJ
- PDM_MODE_MSK
- PDM_MODE_RJ
- PDM_ODM_T
- PDM_OFFSET
- PDM_PATH0_EN
- PDM_PATH1_EN
- PDM_PATH2_EN
- PDM_PATH3_EN
- PDM_PATH_MSK
- PDM_RESET
- PDM_RXFIFO_DATA
- PDM_RX_CLR_DONE
- PDM_RX_CLR_MASK
- PDM_RX_CLR_WR
- PDM_RX_MASK
- PDM_RX_START
- PDM_RX_STOP
- PDM_SIGNOFF_CLK_RATE
- PDM_SRC
- PDM_STATUS__NewCpcTdpLimit_MASK
- PDM_STATUS__NewCpcTdpLimit__SHIFT
- PDM_STATUS__NoofConnectedCores_MASK
- PDM_STATUS__NoofConnectedCores__SHIFT
- PDM_STATUS__PDM_ENABLED_MASK
- PDM_STATUS__PDM_ENABLED__SHIFT
- PDM_STATUS__Reserved_MASK
- PDM_STATUS__Reserved__SHIFT
- PDM_STS
- PDM_SYSCONFIG
- PDM_VDW
- PDM_VDW_MSK
- PDM_VERSION
- PDN
- PDNB
- PDN_22M_MASK
- PDN_22M_MASK_SFT
- PDN_22M_SFT
- PDN_24M_MASK
- PDN_24M_MASK_SFT
- PDN_24M_SFT
- PDN_ADC_CTL_MASK
- PDN_ADC_CTL_MASK_SFT
- PDN_ADC_CTL_SFT
- PDN_ADC_HIRES_MASK
- PDN_ADC_HIRES_MASK_SFT
- PDN_ADC_HIRES_SFT
- PDN_ADC_HIRES_TML_MASK
- PDN_ADC_HIRES_TML_MASK_SFT
- PDN_ADC_HIRES_TML_SFT
- PDN_ADC_MASK
- PDN_ADC_MASK_SFT
- PDN_ADC_SFT
- PDN_ADDA4_ADC_MASK
- PDN_ADDA4_ADC_MASK_SFT
- PDN_ADDA4_ADC_SFT
- PDN_AFE_CTL_MASK
- PDN_AFE_CTL_MASK_SFT
- PDN_AFE_CTL_SFT
- PDN_AFE_MASK
- PDN_AFE_MASK_SFT
- PDN_AFE_SFT
- PDN_AFE_TESTMODEL_CTL_MASK
- PDN_AFE_TESTMODEL_CTL_MASK_SFT
- PDN_AFE_TESTMODEL_CTL_SFT
- PDN_APLL2_TUNER_MASK
- PDN_APLL2_TUNER_MASK_SFT
- PDN_APLL2_TUNER_SFT
- PDN_APLL_TUNER_MASK
- PDN_APLL_TUNER_MASK_SFT
- PDN_APLL_TUNER_SFT
- PDN_BT_N
- PDN_DAC_CTL_MASK
- PDN_DAC_CTL_MASK_SFT
- PDN_DAC_CTL_SFT
- PDN_DAC_MASK
- PDN_DAC_MASK_SFT
- PDN_DAC_PREDIS_MASK
- PDN_DAC_PREDIS_MASK_SFT
- PDN_DAC_PREDIS_SFT
- PDN_DAC_SFT
- PDN_DONE_ATTEMPTS
- PDN_GPS_N
- PDN_I2S_DL_CTL_MASK
- PDN_I2S_DL_CTL_MASK_SFT
- PDN_I2S_DL_CTL_SFT
- PDN_I2S_MASK
- PDN_I2S_MASK_SFT
- PDN_I2S_SFT
- PDN_PL
- PDN_POLL_MAX
- PDN_RESERVED_MASK
- PDN_RESERVED_MASK_SFT
- PDN_RESERVED_SFT
- PDN_TDM_CK_MASK
- PDN_TDM_CK_MASK_SFT
- PDN_TDM_CK_SFT
- PDN_TML_MASK
- PDN_TML_MASK_SFT
- PDN_TML_SFT
- PDN_VOW_F32K_CK_MASK
- PDN_VOW_F32K_CK_MASK_SFT
- PDN_VOW_F32K_CK_SFT
- PDN_VOW_MASK
- PDN_VOW_MASK_SFT
- PDN_VOW_SFT
- PDO_APDO_TYPE
- PDO_APDO_TYPE_MASK
- PDO_APDO_TYPE_SHIFT
- PDO_BATT
- PDO_BATT_MAX_POWER
- PDO_BATT_MAX_PWR_SHIFT
- PDO_BATT_MAX_VOLT
- PDO_BATT_MAX_VOLT_SHIFT
- PDO_BATT_MIN_VOLT
- PDO_BATT_MIN_VOLT_SHIFT
- PDO_CURR_MASK
- PDO_ERR_DUPE_PDO
- PDO_ERR_DUPE_PPS_APDO
- PDO_ERR_FIXED_NOT_SORTED
- PDO_ERR_NO_VSAFE5V
- PDO_ERR_PDO_TYPE_NOT_IN_ORDER
- PDO_ERR_PPS_APDO_NOT_SORTED
- PDO_ERR_VARIABLE_BATT_NOT_SORTED
- PDO_ERR_VSAFE5V_NOT_FIRST
- PDO_FIXED
- PDO_FIXED_CURR
- PDO_FIXED_CURR_SHIFT
- PDO_FIXED_DATA_SWAP
- PDO_FIXED_DUAL_ROLE
- PDO_FIXED_EXTPOWER
- PDO_FIXED_FLAGS
- PDO_FIXED_HIGHER_CAP
- PDO_FIXED_MAX_CURR
- PDO_FIXED_OP_CURR
- PDO_FIXED_SUSPEND
- PDO_FIXED_USB_COMM
- PDO_FIXED_VOLT
- PDO_FIXED_VOLT_SHIFT
- PDO_FORCE_ADISC
- PDO_FORCE_PLOGI
- PDO_MAX_OBJECTS
- PDO_NO_ERR
- PDO_PPS_APDO
- PDO_PPS_APDO_CURR_MASK
- PDO_PPS_APDO_MAX_CURR
- PDO_PPS_APDO_MAX_CURR_SHIFT
- PDO_PPS_APDO_MAX_VOLT
- PDO_PPS_APDO_MAX_VOLT_SHIFT
- PDO_PPS_APDO_MIN_VOLT
- PDO_PPS_APDO_MIN_VOLT_SHIFT
- PDO_PPS_APDO_VOLT_MASK
- PDO_PROG_OP_CURR
- PDO_PROG_OUT_VOLT
- PDO_PWR_MASK
- PDO_TYPE
- PDO_TYPE_APDO
- PDO_TYPE_BATT
- PDO_TYPE_FIXED
- PDO_TYPE_MASK
- PDO_TYPE_SHIFT
- PDO_TYPE_VAR
- PDO_VAR
- PDO_VAR_MAX_CURR
- PDO_VAR_MAX_CURR_SHIFT
- PDO_VAR_MAX_VOLT
- PDO_VAR_MAX_VOLT_SHIFT
- PDO_VAR_MIN_VOLT
- PDO_VAR_MIN_VOLT_SHIFT
- PDO_VOLT_MASK
- PDPOL
- PDPOL_ADDR
- PDPORT_1
- PDPORT_2
- PDPRINTK
- PDPUEN
- PDPUEN_ADDR
- PDP_swab
- PDR
- PDRV_FAILED
- PDRV_HOTSPARE
- PDRV_ONLINE
- PDRV_RBLD
- PDRV_SW_SET
- PDRV_UNCNF
- PDR_3842_PRISM_II_NIC_CONFIG
- PDR_3861_BASELINE_REG_SETTINGS
- PDR_3861_CHAN_CALIB_INTEGRATOR
- PDR_3861_CHAN_CALIB_SET_POINTS
- PDR_3861_IFRF_REG_SETTINGS
- PDR_3861_MF_TEST_CHAN_INTEGRATORS
- PDR_3861_MF_TEST_CHAN_SET_POINTS
- PDR_3861_SHADOW_REG_SETTINGS
- PDR_ALLOWED_CHAN_SET
- PDR_ANTENNA_GAIN
- PDR_BASEBAND_REGISTERS
- PDR_COUNTRY_CERT_BAND
- PDR_COUNTRY_CERT_BAND_2GHZ
- PDR_COUNTRY_CERT_BAND_5GHZ
- PDR_COUNTRY_CERT_CODE
- PDR_COUNTRY_CERT_CODE_PSEUDO
- PDR_COUNTRY_CERT_CODE_REAL
- PDR_COUNTRY_CERT_INDEX
- PDR_COUNTRY_CERT_IODOOR
- PDR_COUNTRY_CERT_IODOOR_BOTH
- PDR_COUNTRY_CERT_IODOOR_INDOOR
- PDR_COUNTRY_CERT_IODOOR_OUTDOOR
- PDR_COUNTRY_INFORMATION
- PDR_COUNTRY_LIST
- PDR_DEFAULT_CHAN
- PDR_DEFAULT_COUNTRY
- PDR_END
- PDR_HARDWARE_PLATFORM_COMPONENT_ID
- PDR_IFR_SETTING
- PDR_INTERFACE_LIST
- PDR_INTERFACE_ROLE_CLIENT
- PDR_INTERFACE_ROLE_SERVER
- PDR_MAC_ADDRESS
- PDR_MANUFACTURING_PART_NUMBER
- PDR_NIC_ID
- PDR_NIC_RAM_SIZE
- PDR_NIC_SERIAL_NUMBER
- PDR_OEM_NAME
- PDR_PDA_VERSION
- PDR_PER_CHANNEL_BASEBAND_REGISTERS
- PDR_PRISM_INDIGO_PA_CALIBRATION_DATA
- PDR_PRISM_MAC_SUP_RANGE
- PDR_PRISM_PA_CAL_CURVE_DATA
- PDR_PRISM_PA_CAL_CURVE_DATA_CUSTOM
- PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS
- PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS_CUSTOM
- PDR_PRISM_PCI_ID
- PDR_PRISM_PCI_IF_CONFIG
- PDR_PRISM_PCI_PM_CONFIG
- PDR_PRISM_TX_IQ_CALIBRATION
- PDR_PRISM_USB_ID
- PDR_PRISM_ZIF_TX_IQ_CALIBRATION
- PDR_PRODUCT_NAME
- PDR_RADIATED_TRANSMISSION_CORRECTION
- PDR_REGULATORY_DOMAIN_LIST
- PDR_REGULATORY_POWER_LIMITS
- PDR_RFMODEM_SUP_RANGE
- PDR_RFR_SETTING
- PDR_RSSI_LINEAR_APPROXIMATION
- PDR_RSSI_LINEAR_APPROXIMATION_CUSTOM
- PDR_RSSI_LINEAR_APPROXIMATION_CUSTOMV2
- PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND
- PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED
- PDR_SYNTH_24_GHZ_DISABLED
- PDR_SYNTH_24_GHZ_MASK
- PDR_SYNTH_5_GHZ_DISABLED
- PDR_SYNTH_5_GHZ_MASK
- PDR_SYNTH_ASM_MASK
- PDR_SYNTH_ASM_XSWON
- PDR_SYNTH_FAA_SWITCH_ENABLED
- PDR_SYNTH_FAA_SWITCH_MASK
- PDR_SYNTH_FRONTEND_DUETTE2
- PDR_SYNTH_FRONTEND_DUETTE3
- PDR_SYNTH_FRONTEND_FRISBEE
- PDR_SYNTH_FRONTEND_LONGBOW
- PDR_SYNTH_FRONTEND_MASK
- PDR_SYNTH_FRONTEND_XBOW
- PDR_SYNTH_IQ_CAL_DISABLED
- PDR_SYNTH_IQ_CAL_MASK
- PDR_SYNTH_IQ_CAL_PA_DETECTOR
- PDR_SYNTH_IQ_CAL_ZIF
- PDR_SYNTH_RX_DIV_MASK
- PDR_SYNTH_RX_DIV_SUPPORTED
- PDR_SYNTH_TX_DIV_MASK
- PDR_SYNTH_TX_DIV_SUPPORTED
- PDR_TEMPERATURE_TYPE
- PDR_UTF8_OEM_NAME
- PDR_UTF8_PRODUCT_NAME
- PDSEL
- PDSEL_ADDR
- PDSP_CTRL_ENABLE
- PDSP_CTRL_PC_MASK
- PDSP_CTRL_RUNNING
- PDSP_CTRL_SOFT_RESET
- PDSTAT
- PDSTATUS
- PDSTATUS_MARK
- PDSTAT_STATE_MASK
- PDS_BITS
- PDS_DIV
- PDS_DIV_MASK
- PDS_DIV_SHIFT
- PDS_LOGO_PENDING
- PDS_PLOGI_COMPLETE
- PDS_PLOGI_PENDING
- PDS_PORT_UNAVAILABLE
- PDS_PRLI2_PENDING
- PDS_PRLI_COMPLETE
- PDS_PRLI_PENDING
- PDS_PRLO_PENDING
- PDTA
- PDTRA
- PDT_ADDR_PERM_ERR
- PDT_ADDR_PHYS_MASK
- PDT_ADDR_SINGLE_ERR
- PDT_END_SCAN_LOCATION
- PDT_NONE
- PDT_PAT_CELL
- PDT_PAT_NEW
- PDT_PDC
- PDT_POLL_INTERVAL_DEFAULT
- PDT_POLL_INTERVAL_SHORT
- PDT_PROPERTIES_LOCATION
- PDT_START_SCAN_LOCATION
- PDUBASE_DATALENHI_MASK
- PDUBASE_DATALENLO_MASK
- PDUBASE_OPCODE_MASK
- PDUCBF_RX_DATA
- PDUCBF_RX_DATA_DDPD
- PDUCBF_RX_DCRC_ERR
- PDUCBF_RX_DDP_CMP
- PDUCBF_RX_HCRC_ERR
- PDUCBF_RX_HDR
- PDUCBF_RX_STATUS
- PDULIST_IMMEDIATE
- PDULIST_IMMEDIATE_AND_UNSOLICITED
- PDULIST_NORMAL
- PDULIST_UNSOLICITED
- PDUMODE_AAL0
- PDUMODE_AAL5
- PDUMODE_AAL5STREAM
- PDUTYPE_IMMEDIATE
- PDUTYPE_NORMAL
- PDUTYPE_UNSOLICITED
- PDU_CNTL
- PDU_ENCAPSULATION
- PDU_FIRST
- PDU_GET_NEXT_Vr
- PDU_HEADER_LENGTH
- PDU_LAST
- PDU_SUPV_GET_Nr
- PD_ACCESS_TYPE_NONE
- PD_ACCESS_TYPE_OVERWRITABLE
- PD_ACCESS_TYPE_READ_ONLY
- PD_ACCESS_TYPE_REWRITABLE
- PD_ACCESS_TYPE_WRITE_ONCE
- PD_ADMA
- PD_ALWAYS_ON
- PD_API_OP_ALLOC_COM_BUF
- PD_API_OP_CLOSE_PROVIDER
- PD_API_OP_CONFIG
- PD_API_OP_CREATE_QUEUE
- PD_API_OP_FLUSH_QUEUE
- PD_API_OP_FREE_COM_BUF
- PD_API_OP_FREE_QUEUE
- PD_API_OP_MAX
- PD_API_OP_OPEN_PROVIDER
- PD_API_OP_SW_DATAPATH
- PD_BASE
- PD_BITS
- PD_CAN_0
- PD_CAN_1
- PD_CHARGE_5V
- PD_CHARGE_MAX
- PD_CHARGE_NONE
- PD_CHARGE_NO_CHANGE
- PD_CHIP_ON
- PD_CMD_FAIL
- PD_CONSOLE
- PD_CONTROL_DISABLE
- PD_CPU
- PD_CPU_CR
- PD_CPU_NOCR
- PD_CSTAT_XID
- PD_CTL_HASH_FINAL
- PD_CTL_HOST_READY
- PD_CTL_PE_DONE
- PD_CTRL_ACCEPT
- PD_CTRL_DR_SWAP
- PD_CTRL_FR_SWAP
- PD_CTRL_GET_COUNTRY_CODES
- PD_CTRL_GET_PPS_STATUS
- PD_CTRL_GET_SINK_CAP
- PD_CTRL_GET_SOURCE_CAP
- PD_CTRL_GET_SOURCE_CAP_EXT
- PD_CTRL_GET_STATUS
- PD_CTRL_GOOD_CRC
- PD_CTRL_GOTO_MIN
- PD_CTRL_NOT_SUPP
- PD_CTRL_PING
- PD_CTRL_PR_SWAP
- PD_CTRL_PS_RDY
- PD_CTRL_REJECT
- PD_CTRL_RESP_ENABLED_COMMS
- PD_CTRL_RESP_ENABLED_CONNECTED
- PD_CTRL_RESP_ENABLED_PD_CAPABLE
- PD_CTRL_RESP_ROLE_DATA
- PD_CTRL_RESP_ROLE_DR_DATA
- PD_CTRL_RESP_ROLE_DR_POWER
- PD_CTRL_RESP_ROLE_EXT_POWERED
- PD_CTRL_RESP_ROLE_POWER
- PD_CTRL_RESP_ROLE_USB_COMM
- PD_CTRL_RESP_ROLE_VCONN
- PD_CTRL_SOFT_RESET
- PD_CTRL_VCONN_SWAP
- PD_CTRL_WAIT
- PD_DATA_ALERT
- PD_DATA_BATT_STATUS
- PD_DATA_BIST
- PD_DATA_GET_COUNTRY_INFO
- PD_DATA_REQUEST
- PD_DATA_SINK_CAP
- PD_DATA_SOURCE_CAP
- PD_DATA_VENDOR_DEF
- PD_DEBUG
- PD_DEFAULT_MASK
- PD_DMA_OPS_MASK
- PD_DP
- PD_ENTER_MODE
- PD_ENTRY_BUSY
- PD_ENTRY_FREE
- PD_ENTRY_INUSE
- PD_ETH_0
- PD_ETH_1
- PD_ETH_2
- PD_ETH_3
- PD_EVENT_ACC_BASE
- PD_EVENT_ACC_RW_ERASE
- PD_EVENT_ACC_RW_FAIL
- PD_EVENT_DATA_SWAP
- PD_EVENT_IDENTITY_RECEIVED
- PD_EVENT_MCU_BASE
- PD_EVENT_MCU_BOARD_CUSTOM
- PD_EVENT_MCU_CHARGE
- PD_EVENT_MCU_CONNECT
- PD_EVENT_NO_ENTRY
- PD_EVENT_POWER_CHANGE
- PD_EVENT_PS_BASE
- PD_EVENT_PS_FAULT
- PD_EVENT_UPDATE_DEVICE
- PD_EVENT_VIDEO_BASE
- PD_EVENT_VIDEO_CODEC
- PD_EVENT_VIDEO_DP_MODE
- PD_EXIT_MODE
- PD_EXT_BATT_CAP
- PD_EXT_COUNTRY_CODES
- PD_EXT_COUNTRY_INFO
- PD_EXT_FW_UPDATE_REQUEST
- PD_EXT_FW_UPDATE_RESPONSE
- PD_EXT_GET_BATT_CAP
- PD_EXT_GET_BATT_STATUS
- PD_EXT_GET_MANUFACTURER_INFO
- PD_EXT_HDR
- PD_EXT_HDR_CHUNKED
- PD_EXT_HDR_CHUNK_NUM_MASK
- PD_EXT_HDR_CHUNK_NUM_SHIFT
- PD_EXT_HDR_DATA_SIZE_MASK
- PD_EXT_HDR_DATA_SIZE_SHIFT
- PD_EXT_HDR_LE
- PD_EXT_HDR_REQ_CHUNK
- PD_EXT_MANUFACTURER_INFO
- PD_EXT_MAX_CHUNK_DATA
- PD_EXT_PPS_STATUS
- PD_EXT_SECURITY_REQUEST
- PD_EXT_SECURITY_RESPONSE
- PD_EXT_SOURCE_CAP_EXT
- PD_EXT_STATUS
- PD_GDMA
- PD_GPIO
- PD_GPU
- PD_HEADER
- PD_HEADER_CNT_MASK
- PD_HEADER_CNT_SHIFT
- PD_HEADER_DATA_ROLE
- PD_HEADER_EXT_HDR
- PD_HEADER_ID_MASK
- PD_HEADER_ID_SHIFT
- PD_HEADER_LE
- PD_HEADER_PWR_ROLE
- PD_HEADER_REV_MASK
- PD_HEADER_REV_SHIFT
- PD_HEADER_TYPE_MASK
- PD_HEADER_TYPE_SHIFT
- PD_HUGE
- PD_I2C_0
- PD_I2C_1
- PD_IDH_MODAL_SUPP
- PD_IDH_PTYPE
- PD_IDH_VID
- PD_ID_LEN
- PD_ID_OFF
- PD_INT0
- PD_INT1
- PD_INT2
- PD_INT3
- PD_IOMMUV2_MASK
- PD_IRQ1
- PD_IRQ2
- PD_IRQ3
- PD_IRQ6
- PD_KB
- PD_KB0
- PD_KB1
- PD_KB2
- PD_KB3
- PD_KB4
- PD_KB5
- PD_KB6
- PD_KB7
- PD_LOG_HEADS
- PD_LOG_PORT
- PD_LOG_PORT_MASK
- PD_LOG_PORT_SHIFT
- PD_LOG_PORT_SIZE
- PD_LOG_SECTS
- PD_LOG_SIZE
- PD_LOG_SIZE_MASK
- PD_LOG_TIMESTAMP_SHIFT
- PD_MAJOR
- PD_MARKBITS
- PD_MAX_PAYLOAD
- PD_MAX_RETRIES
- PD_MAX_REV
- PD_MEMCTL
- PD_MODE_CMD_COUNT
- PD_MSG_CTRL_NOT_SUPP
- PD_MSG_CTRL_REJECT
- PD_MSG_CTRL_WAIT
- PD_MSG_DATA_SINK_CAP
- PD_MSG_DATA_SOURCE_CAP
- PD_MSG_NONE
- PD_NAME
- PD_NAMELEN
- PD_NAND
- PD_NORMAL
- PD_NO_CR
- PD_N_CAPS_COUNT
- PD_N_HARD_RESET_COUNT
- PD_PAD_CTL_128
- PD_PAD_CTL_256
- PD_PAD_CTL_32
- PD_PAD_CTL_64
- PD_PAGE
- PD_PARTITION_CONTENTS_CD001
- PD_PARTITION_CONTENTS_CDW02
- PD_PARTITION_CONTENTS_FDC01
- PD_PARTITION_CONTENTS_NSR02
- PD_PARTITION_CONTENTS_NSR03
- PD_PARTITION_FLAGS_ALLOC
- PD_PASSTHROUGH_MASK
- PD_PCIE
- PD_POWER_CHARGING_PORT
- PD_PPS_CTRL_TIMEOUT
- PD_PRODUCT_PID
- PD_PTABLE
- PD_QSPI
- PD_RESET
- PD_RESUME
- PD_RETRY_COUNT
- PD_REV10
- PD_REV20
- PD_REV30
- PD_RING_OSC
- PD_ROLE_SWAP_TIMEOUT
- PD_RW_HASH_SIZE
- PD_SATA
- PD_SCLK_DIVIDER
- PD_SCLK_DIVIDER_MASK
- PD_SCLK_DIVIDER_SHIFT
- PD_SCU
- PD_SD_0
- PD_SD_1
- PD_SPIN
- PD_SPIN_DEL
- PD_SPI_0
- PD_SPI_1
- PD_STATE_DISCOVERY
- PD_STATE_PORT_LOGGED_IN
- PD_STATE_PORT_LOGIN
- PD_STATE_PORT_LOGOUT
- PD_STATE_PORT_UNAVAILABLE
- PD_STATE_PROCESS_LOGIN
- PD_STATE_PROCESS_LOGOUT
- PD_STATE_WAIT_DISCOVERY_ACK
- PD_STATE_WAIT_PORT_LOGIN_ACK
- PD_STATE_WAIT_PORT_LOGOUT_ACK
- PD_STATE_WAIT_PROCESS_LOGIN_ACK
- PD_STATE_WAIT_PROCESS_LOGOUT_ACK
- PD_STATUS_EC_INT_ACTIVE
- PD_STATUS_HOST_EVENT
- PD_STATUS_IN_RW
- PD_STATUS_JUMPED_TO_IMAGE
- PD_STATUS_TCPC_ALERT_0
- PD_STATUS_TCPC_ALERT_1
- PD_STATUS_TCPC_ALERT_2
- PD_STATUS_TCPC_ALERT_3
- PD_SUSPEND
- PD_TIM_MASK
- PD_TIM_SHIFT
- PD_TMO
- PD_TTC_0
- PD_TTC_1
- PD_TTC_2
- PD_TTC_3
- PD_T_CC_DEBOUNCE
- PD_T_DB_DETECT
- PD_T_DRP_SNK
- PD_T_DRP_SRC
- PD_T_DRP_TRY
- PD_T_DRP_TRYWAIT
- PD_T_ERROR_RECOVERY
- PD_T_NEWSRC
- PD_T_NO_RESPONSE
- PD_T_PD_DEBOUNCE
- PD_T_PS_HARD_RESET
- PD_T_PS_SOURCE_OFF
- PD_T_PS_SOURCE_ON
- PD_T_PS_TRANSITION
- PD_T_SAFE_0V
- PD_T_SENDER_RESPONSE
- PD_T_SEND_SOURCE_CAP
- PD_T_SINK_ACTIVITY
- PD_T_SINK_REQUEST
- PD_T_SINK_WAIT_CAP
- PD_T_SOURCE_ACTIVITY
- PD_T_SRCSWAPSTDBY
- PD_T_SRC_RECOVER
- PD_T_SRC_RECOVER_MAX
- PD_T_SRC_TRANSITION
- PD_T_SRC_TURN_ON
- PD_T_TCPC_TX_TIMEOUT
- PD_T_VCONN_SOURCE_ON
- PD_T_VDM_BUSY
- PD_T_VDM_E_MODE
- PD_T_VDM_RCVR_RSP
- PD_T_VDM_SNDR_RSP
- PD_T_VDM_UNSTRUCTURED
- PD_T_VDM_WAIT_MODE_E
- PD_UART_0
- PD_UART_1
- PD_UNITS
- PD_USB_0
- PD_USB_1
- PD_VDO_AMA_VBUS_REQ
- PD_VDO_AMA_VCONN_REQ
- PD_VDO_CMD
- PD_VDO_CMDT
- PD_VDO_OPOS
- PD_VDO_SVDM
- PD_VDO_SVID_SVID0
- PD_VDO_SVID_SVID1
- PD_VDO_VID
- PD_VERSION
- PE
- PE0MD_00
- PE0MD_000
- PE0MD_001
- PE0MD_01
- PE0MD_011
- PE0MD_10
- PE0MD_100
- PE0MD_11
- PE0_AF_KP_COL6
- PE0_DATA
- PE0_FN
- PE0_IN
- PE0_IOR_IN
- PE0_IOR_OUT
- PE0_OUT
- PE0_PF_TEST_WB2
- PE0_PF_USBOTG_NXT
- PE10MD_000
- PE10MD_001
- PE10MD_010
- PE10MD_100
- PE10_DATA
- PE10_IN
- PE10_OUT
- PE10_PF_UART3_CTS
- PE11MD_000
- PE11MD_001
- PE11MD_010
- PE11MD_100
- PE11_DATA
- PE11_IN
- PE11_OUT
- PE11_PF_UART3_RTS
- PE12MD_00
- PE12MD_11
- PE12_DATA
- PE12_IN
- PE12_OUT
- PE12_PF_UART1_TXD
- PE1300_CMOS_CMD_STRUCT_PTR
- PE13MD_00
- PE13MD_11
- PE13_DATA
- PE13_IN
- PE13_OUT
- PE13_PF_UART1_RXD
- PE1400_APM_CONTROL_PORT
- PE1400_CMOS_CMD_STRUCT_PTR
- PE14MD_00
- PE14MD_01
- PE14MD_11
- PE14_DATA
- PE14_IN
- PE14_OUT
- PE14_PF_UART1_CTS
- PE15MD_00
- PE15MD_01
- PE15MD_11
- PE15_DATA
- PE15_IN
- PE15_OUT
- PE15_PF_UART1_RTS
- PE16_AF_OWIRE
- PE16_PF_RTCK
- PE17_PF_RESET_OUT
- PE18_AF_CSPI3_MISO
- PE18_PF_SD1_D0
- PE19_PF_SD1_D1
- PE1MD_00
- PE1MD_000
- PE1MD_001
- PE1MD_01
- PE1MD_010
- PE1MD_011
- PE1MD_10
- PE1MD_100
- PE1MD_101
- PE1MD_11
- PE1MD_110
- PE1MD_111
- PE1_AF_KP_ROW6
- PE1_ASPMOPTH
- PE1_ASPMOPTL
- PE1_ASPMSUPRT
- PE1_DATA
- PE1_FN
- PE1_GPREG0
- PE1_GPREG0_ENBG
- PE1_GPREG0_PBG
- PE1_GPREG0_PDD3COLD
- PE1_GPREG0_PDPCIEIDDQ
- PE1_GPREG0_PDPCIESD
- PE1_GPREG1
- PE1_IN
- PE1_IOR_IN
- PE1_IOR_OUT
- PE1_MULTIFUN
- PE1_OUT
- PE1_PF_TEST_WB1
- PE1_PF_USBOTG_STP
- PE1_RDYDMA
- PE1_REVID
- PE20_PF_SD1_D2
- PE21_AF_CSPI3_SS
- PE21_PF_SD1_D3
- PE22_AF_CSPI3_MOSI
- PE22_PF_SD1_CMD
- PE23_AF_CSPI3_SCLK
- PE23_PF_SD1_CLK
- PE24_PF_USBOTG_CLK
- PE25_PF_USBOTG_DATA7
- PE2MD_00
- PE2MD_000
- PE2MD_001
- PE2MD_01
- PE2MD_010
- PE2MD_011
- PE2MD_10
- PE2MD_100
- PE2MD_101
- PE2MD_11
- PE2MD_110
- PE2MD_111
- PE2_AF_KP_ROW7
- PE2_DATA
- PE2_FN
- PE2_IN
- PE2_IOR_IN
- PE2_IOR_OUT
- PE2_OUT
- PE2_PF_TEST_WB0
- PE2_PF_USBOTG_DIR
- PE3MD_00
- PE3MD_000
- PE3MD_001
- PE3MD_01
- PE3MD_010
- PE3MD_011
- PE3MD_10
- PE3MD_100
- PE3MD_101
- PE3MD_11
- PE3MD_110
- PE3MD_111
- PE3_AF_KP_COL7
- PE3_DATA
- PE3_FN
- PE3_IN
- PE3_IOR_IN
- PE3_IOR_OUT
- PE3_OUT
- PE3_PF_UART2_CTS
- PE4MD_00
- PE4MD_000
- PE4MD_001
- PE4MD_01
- PE4MD_010
- PE4MD_011
- PE4MD_10
- PE4MD_100
- PE4MD_11
- PE4_AF_KP_ROW7
- PE4_DATA
- PE4_FN
- PE4_IN
- PE4_IOR_IN
- PE4_IOR_OUT
- PE4_OUT
- PE4_PF_UART2_RTS
- PE5MD_00
- PE5MD_000
- PE5MD_001
- PE5MD_01
- PE5MD_010
- PE5MD_011
- PE5MD_10
- PE5MD_100
- PE5MD_11
- PE5_AIN_PC_SPKOUT
- PE5_BIN_TOUT2
- PE5_CIN_TOUT3
- PE5_DATA
- PE5_FN
- PE5_IN
- PE5_IOR_IN
- PE5_IOR_OUT
- PE5_OUT
- PE5_PF_PWMO
- PE6MD_00
- PE6MD_000
- PE6MD_001
- PE6MD_01
- PE6MD_010
- PE6MD_011
- PE6MD_10
- PE6MD_100
- PE6MD_11
- PE6_AF_KP_COL6
- PE6_DATA
- PE6_FN
- PE6_IN
- PE6_IOR_IN
- PE6_IOR_OUT
- PE6_OUT
- PE6_PF_UART2_TXD
- PE7MD_00
- PE7MD_000
- PE7MD_001
- PE7MD_01
- PE7MD_010
- PE7MD_011
- PE7MD_10
- PE7MD_100
- PE7MD_11
- PE7_AF_KP_ROW6
- PE7_DATA
- PE7_FN
- PE7_IN
- PE7_IOR_IN
- PE7_IOR_OUT
- PE7_OUT
- PE7_PF_UART2_RXD
- PE8MD_00
- PE8MD_01
- PE8MD_10
- PE8MD_11
- PE8_AIN_IR_TXD
- PE8_DATA
- PE8_IN
- PE8_OUT
- PE8_PF_UART3_TXD
- PE9MD_00
- PE9MD_01
- PE9MD_10
- PE9MD_11
- PE9_AOUT_IR_RXD
- PE9_DATA
- PE9_IN
- PE9_OUT
- PE9_PF_UART3_RXD
- PEAKWT
- PEAK_CANFD_USER_H
- PEAK_CPCI_DEVICE_ID
- PEAK_CURRENT_0_000_mA
- PEAK_CURRENT_0_200_mA
- PEAK_CURRENT_0_400_mA
- PEAK_CURRENT_0_600_mA
- PEAK_CURRENT_0_800_mA
- PEAK_CURRENT_1_000_mA
- PEAK_CURRENT_1_200_mA
- PEAK_CURRENT_1_400_mA
- PEAK_CURRENT_1_600_mA
- PEAK_CURRENT_1_800_mA
- PEAK_CURRENT_2_000_mA
- PEAK_CURRENT_2_200_mA
- PEAK_CURRENT_2_400_mA
- PEAK_CURRENT_2_600_mA
- PEAK_CURRENT_2_800_mA
- PEAK_CURRENT_3_000_mA
- PEAK_CURRENT_3_200_mA
- PEAK_CURRENT_3_400_mA
- PEAK_CURRENT_3_600_mA
- PEAK_CURRENT_3_800_mA
- PEAK_CURRENT_4_000_mA
- PEAK_CURRENT_4_200_mA
- PEAK_CURRENT_4_400_mA
- PEAK_CURRENT_4_600_mA
- PEAK_CURRENT_4_800_mA
- PEAK_CURRENT_5_000_mA
- PEAK_CURRENT_5_200_mA
- PEAK_CURRENT_5_400_mA
- PEAK_CURRENT_5_600_mA
- PEAK_CURRENT_5_800_mA
- PEAK_CURRENT_6_000_mA
- PEAK_CURRENT_6_200_mA
- PEAK_CURRENT_6_400_mA
- PEAK_CURRENT_6_600_mA
- PEAK_CURRENT_6_800_mA
- PEAK_CURRENT_7_000_mA
- PEAK_CURRENT_7_200_mA
- PEAK_CURRENT_7_400_mA
- PEAK_CURRENT_7_600_mA
- PEAK_CURRENT_7_800_mA
- PEAK_CURRENT_8_000_mA
- PEAK_CURRENT_8_200_mA
- PEAK_CURRENT_8_400_mA
- PEAK_CURRENT_8_600_mA
- PEAK_CURRENT_8_800_mA
- PEAK_CURRENT_9_000_mA
- PEAK_CURRENT_9_200_mA
- PEAK_CURRENT_9_400_mA
- PEAK_CURRENT_LANE0
- PEAK_CURRENT_LANE1
- PEAK_CURRENT_LANE2
- PEAK_CURRENT_LANE3
- PEAK_FACTOR_X1000
- PEAK_MPCIE_DEVICE_ID
- PEAK_MPCI_DEVICE_ID
- PEAK_PCIEC34_DEVICE_ID
- PEAK_PCIEC_DEVICE_ID
- PEAK_PCIEFD_ID
- PEAK_PCIE_DEVICE_ID
- PEAK_PCIE_OEM_ID
- PEAK_PCI_104E_DEVICE_ID
- PEAK_PCI_CAN_CLOCK
- PEAK_PCI_CDR
- PEAK_PCI_CFG_SIZE
- PEAK_PCI_CHAN_MAX
- PEAK_PCI_CHAN_SIZE
- PEAK_PCI_DEVICE_ID
- PEAK_PCI_OCR
- PEAK_PCI_VENDOR_ID
- PEAK_PC_104P_DEVICE_ID
- PEAQ_DOLBY_BUTTON_GUID
- PEAQ_DOLBY_BUTTON_METHOD_ID
- PEAQ_POLL_IGNORE_MS
- PEAQ_POLL_INTERVAL_MS
- PEAQ_POLL_MAX_MS
- PEARL8x8_IDX
- PEARL_ASR_DISABLE_MASK
- PEARL_ASR_TOGGLE_MASK
- PEARL_ASSERT_INTX
- PEARL_BASE
- PEARL_PCIE_CFG0_OFFSET
- PEARL_READ
- PEARL_TX_BD_SIZE_DEFAULT
- PEARL_WRITE
- PEBS_BUFFER_SIZE
- PEBS_COUNTER_MASK
- PEBS_DATACFG_GP
- PEBS_DATACFG_LBRS
- PEBS_DATACFG_LBR_SHIFT
- PEBS_DATACFG_MEMINFO
- PEBS_DATACFG_XMMS
- PEBS_FIXUP_SIZE
- PEBS_GP_REGS
- PEBS_HSW_TSX_FLAGS
- PEBS_OUTPUT_MASK
- PEBS_OUTPUT_OFFSET
- PEBS_OUTPUT_PT
- PEBS_PMI_AFTER_EACH_RECORD
- PEBS_VIA_PT_MASK
- PECFG_460SX_DLLSTA
- PECFG_460SX_DLLSTA_LINKUP
- PECFG_BAR0HMPA
- PECFG_BAR0LMPA
- PECFG_BAR1MPA
- PECFG_BAR2HMPA
- PECFG_BAR2LMPA
- PECFG_ECRTCTL
- PECFG_PIM01SAH
- PECFG_PIM01SAL
- PECFG_PIM0LAH
- PECFG_PIM0LAL
- PECFG_PIM1LAH
- PECFG_PIM1LAL
- PECFG_PIMEN
- PECFG_POM0LAH
- PECFG_POM0LAL
- PECFG_POM1LAH
- PECFG_POM1LAL
- PECFG_POM2LAH
- PECFG_POM2LAL
- PECFG_TLDLP
- PECFG_TLDLP_LNKUP
- PECFG_TLDLP_PRESENT
- PECI0
- PECI1
- PECI2
- PECI3
- PECI4
- PECI5
- PECOFF_EDATA_PADDING
- PECOFF_RELOC_RESERVE
- PECR
- PECR_IE
- PECR_IS
- PECULIAR_486
- PEDATA
- PEDATA_ADDR
- PEDIR
- PEDIR_ADDR
- PEDIT_ETH_DMAC_31_0
- PEDIT_ETH_DMAC_47_32_SMAC_15_0
- PEDIT_ETH_DMAC_MASK
- PEDIT_ETH_SMAC_47_16
- PEDIT_FIELDS
- PEDIT_IP4_DST
- PEDIT_IP4_SRC
- PEDIT_IP6_DST_127_96
- PEDIT_IP6_DST_31_0
- PEDIT_IP6_DST_63_32
- PEDIT_IP6_DST_95_64
- PEDIT_IP6_SRC_127_96
- PEDIT_IP6_SRC_31_0
- PEDIT_IP6_SRC_63_32
- PEDIT_IP6_SRC_95_64
- PEDIT_TCP_SPORT_DPORT
- PEDIT_TCP_UDP_SPORT_MASK
- PEDIT_UDP_SPORT_DPORT
- PEDR
- PEEK_POKE_TIMEOUT
- PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI_MASK
- PEER0_FB_OFFSET_HI_IND__PEER0_FB_OFFSET_HI__SHIFT
- PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK
- PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT
- PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN_MASK
- PEER0_FB_OFFSET_LO_IND__PEER0_FB_EN__SHIFT
- PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO_MASK
- PEER0_FB_OFFSET_LO_IND__PEER0_FB_OFFSET_LO__SHIFT
- PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK
- PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT
- PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK
- PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT
- PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI_MASK
- PEER1_FB_OFFSET_HI_IND__PEER1_FB_OFFSET_HI__SHIFT
- PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK
- PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT
- PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN_MASK
- PEER1_FB_OFFSET_LO_IND__PEER1_FB_EN__SHIFT
- PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO_MASK
- PEER1_FB_OFFSET_LO_IND__PEER1_FB_OFFSET_LO__SHIFT
- PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK
- PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT
- PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK
- PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT
- PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI_MASK
- PEER2_FB_OFFSET_HI_IND__PEER2_FB_OFFSET_HI__SHIFT
- PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK
- PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT
- PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN_MASK
- PEER2_FB_OFFSET_LO_IND__PEER2_FB_EN__SHIFT
- PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO_MASK
- PEER2_FB_OFFSET_LO_IND__PEER2_FB_OFFSET_LO__SHIFT
- PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK
- PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT
- PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK
- PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT
- PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI_MASK
- PEER3_FB_OFFSET_HI_IND__PEER3_FB_OFFSET_HI__SHIFT
- PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK
- PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT
- PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN_MASK
- PEER3_FB_OFFSET_LO_IND__PEER3_FB_EN__SHIFT
- PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO_MASK
- PEER3_FB_OFFSET_LO_IND__PEER3_FB_OFFSET_LO__SHIFT
- PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK
- PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT
- PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK
- PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT
- PEER_ABORT
- PEER_ABORT_IN_PROGRESS
- PEER_AIRGO
- PEER_ATH
- PEER_BROAD
- PEER_BW_RXNSS_OVERRIDE_OFFSET
- PEER_CISCO
- PEER_CLOSE
- PEER_DEFAULT_STATS_UPDATE_PERIOD
- PEER_ESTABL_CONTACT_EVT
- PEER_FIRST_NODE_JOIN_EVENT
- PEER_LAST_NODE_LEAVE_EVENT
- PEER_LOST_CONTACT_EVT
- PEER_MARV
- PEER_MAX
- PEER_MAX_GC
- PEER_NODE_JOIN_EVENT
- PEER_NODE_LEAVE_EVENT
- PEER_NOTIFY
- PEER_RAL
- PEER_REG_RANGE0_IND__END_ADDR_MASK
- PEER_REG_RANGE0_IND__END_ADDR__SHIFT
- PEER_REG_RANGE0_IND__START_ADDR_MASK
- PEER_REG_RANGE0_IND__START_ADDR__SHIFT
- PEER_REG_RANGE0__END_ADDR_MASK
- PEER_REG_RANGE0__END_ADDR__SHIFT
- PEER_REG_RANGE0__START_ADDR_MASK
- PEER_REG_RANGE0__START_ADDR__SHIFT
- PEER_REG_RANGE1_IND__END_ADDR_MASK
- PEER_REG_RANGE1_IND__END_ADDR__SHIFT
- PEER_REG_RANGE1_IND__START_ADDR_MASK
- PEER_REG_RANGE1_IND__START_ADDR__SHIFT
- PEER_REG_RANGE1__END_ADDR_MASK
- PEER_REG_RANGE1__END_ADDR__SHIFT
- PEER_REG_RANGE1__START_ADDR_MASK
- PEER_REG_RANGE1__START_ADDR__SHIFT
- PEER_REMOVE_COMPLETE_EVENT_ID
- PEER_RTL
- PEER_RTL_92SE
- PEER_STATS_FOR_NO_OF_PPDUS
- PEER_TYPE_AP
- PEER_TYPE_STA
- PEER_UNKNOWN
- PEFE
- PEFE_FILTERAMOUNT
- PEFE_FILTERAMOUNT_MASK
- PEFE_PITCHAMOUNT
- PEFE_PITCHAMOUNT_MASK
- PEFUSE_HAL
- PEG0EC
- PEG1EC
- PEGASOS2_MARVELL_REGBASE
- PEGASOS2_MARVELL_REGSIZE
- PEGASOS2_SRAM_BASE
- PEGASOS2_SRAM_BASE_ETH_PORT0
- PEGASOS2_SRAM_BASE_ETH_PORT1
- PEGASOS2_SRAM_RXRING_SIZE
- PEGASOS2_SRAM_SIZE
- PEGASOS2_SRAM_TXRING_SIZE
- PEGASUS_DEV
- PEGASUS_DEV_CLASS
- PEGASUS_II
- PEGASUS_JEDEC_ID
- PEGASUS_MTU
- PEGASUS_ORION_JEDEC_ID
- PEGASUS_PRESENT
- PEGASUS_REQT_READ
- PEGASUS_REQT_WRITE
- PEGASUS_REQ_GET_REGS
- PEGASUS_REQ_SET_REG
- PEGASUS_REQ_SET_REGS
- PEGASUS_RX_BUSY
- PEGASUS_RX_URB_FAIL
- PEGASUS_TX_BUSY
- PEGASUS_TX_TIMEOUT
- PEGASUS_UNPLUG
- PEGASUS_WRITE_EEPROM
- PEGA_ACCEL_DESC
- PEGA_ACCEL_NAME
- PEGA_ACC_CLAMP
- PEGA_ACC_RETRIES
- PEGA_ALS
- PEGA_ALS_POWER
- PEGA_BLUETOOTH
- PEGA_READ_ALS_H
- PEGA_READ_ALS_L
- PEGA_WLAN
- PEGA_WWAN
- PEGNET_REQUEST
- PEG_BAND_GAP_DATA
- PEG_NETWORK_BASE
- PEH_AXUSER_CFG
- PEH_AXUSER_CFG_ENABLE
- PEIH_CNTRST
- PEIH_FLUSH0
- PEIH_FLUSH1
- PEIH_MSIASS
- PEIH_MSIED
- PEIH_MSIMK
- PEIH_TERMADH
- PEIH_TERMADL
- PELMASKOFFSET
- PEM0_INT
- PEM_BIST_STATUSX
- PEM_CFG_RD
- PEM_CFG_WR
- PEM_CLEAR_INFO_FLAGS
- PEM_DATA_ALARM_1
- PEM_DATA_ALARM_2
- PEM_DATA_CURRENT
- PEM_DATA_STATUS_1
- PEM_DATA_STATUS_2
- PEM_DATA_TEMP
- PEM_DATA_TEMP_CRIT
- PEM_DATA_TEMP_MAX
- PEM_DATA_VOUT_LSB
- PEM_DATA_VOUT_MSB
- PEM_FAN_ADJUSTMENT
- PEM_FAN_FAN1
- PEM_FAN_FAN2
- PEM_FAN_FAN3
- PEM_FAN_HI_SPEED
- PEM_FAN_NORMAL_SPEED
- PEM_INDX_MASK
- PEM_INPUT_POWER_LSB
- PEM_INPUT_POWER_MSB
- PEM_INPUT_VOLTAGE
- PEM_MAX_DOM_IN_NODE
- PEM_MIN_DOM_IN_NODE
- PEM_NODE_MASK
- PEM_OPERATION
- PEM_READ_DATA_STRING
- PEM_READ_FAN_SPEED
- PEM_READ_FIRMWARE_REV
- PEM_READ_INPUT_STRING
- PEM_READ_RUN_TIMER
- PEM_RES_BASE
- PEM_VOUT_COMMAND
- PEM_VOUT_OV_FAULT_LIMIT
- PENALTY_FOR_NODE_WITH_CPUS
- PENC0_MARK
- PENC1_MARK
- PEND
- PENDBASER_RES0_MASK
- PENDIN
- PENDING
- PENDING_CURSOR
- PENDING_ERROR
- PENDING_FLIP
- PENDING_IO_MAX
- PENDING_IO_ONE_FLUSH
- PENDING_LIST_LOCK
- PENDING_SIG
- PENDING_THOLD
- PENDOWN_MASK
- PEND_WR_DATE
- PEND_WR_TIME
- PENPARTNER
- PENSKETCH_M912_RDESC_ORIG_SIZE
- PENUP_TIMEOUT
- PEN_BUTTON_PRESSED
- PEN_DOWN_STATUS
- PEN_IRQ_BIT
- PEN_IRQ_NUM
- PEN_MODE_XY
- PEN_TIP
- PEN_UP_STATUS
- PEN_UP_TIMEOUT_MS
- PEPUEN
- PEPUEN_ADDR
- PEP_IND_BUSY
- PEP_IND_EMPTY
- PEP_IND_READY
- PER
- PERACOM_PID
- PERACOM_VID
- PERCENT
- PERCENTUSED
- PERCENT_FN
- PERCENT_HITS_GLOBAL
- PERCENT_HITS_LOCAL
- PERCENT_MAX
- PERCENT_PERIOD_GLOBAL
- PERCENT_PERIOD_LOCAL
- PERCPU_ADDR
- PERCPU_COUNT_BIAS
- PERCPU_DECRYPTED_SECTION
- PERCPU_DYNAMIC_EARLY_SIZE
- PERCPU_DYNAMIC_EARLY_SLOTS
- PERCPU_DYNAMIC_RESERVE
- PERCPU_FIRST_CHUNK_RESERVE
- PERCPU_FREE_TARGET
- PERCPU_H
- PERCPU_HASH_KMALLOC
- PERCPU_HASH_PREALLOC
- PERCPU_INPUT
- PERCPU_IRQ_MASK
- PERCPU_MODULE_RESERVE
- PERCPU_NR_SCANS
- PERCPU_OFFSET
- PERCPU_OP
- PERCPU_PAGE_SHIFT
- PERCPU_PAGE_SIZE
- PERCPU_REF_ALLOW_REINIT
- PERCPU_REF_INIT_ATOMIC
- PERCPU_REF_INIT_DEAD
- PERCPU_RET_OP
- PERCPU_RW_OPS
- PERCPU_SECTION
- PERCPU_VADDR
- PERC_STR
- PERD0_PWMDV_MASK
- PERD0_SPIDV_MASK
- PERD0_U0DV_MASK
- PERD0_U1DV_MASK
- PERENTRY
- PERFCOUNTER_ACTIVE
- PERFCOUNTER_CNT0_STATE
- PERFCOUNTER_CNT0_STATE_FREEZE
- PERFCOUNTER_CNT0_STATE_HW
- PERFCOUNTER_CNT0_STATE_RESET
- PERFCOUNTER_CNT0_STATE_START
- PERFCOUNTER_CNT1_STATE
- PERFCOUNTER_CNT1_STATE_FREEZE
- PERFCOUNTER_CNT1_STATE_HW
- PERFCOUNTER_CNT1_STATE_RESET
- PERFCOUNTER_CNT1_STATE_START
- PERFCOUNTER_CNT2_STATE
- PERFCOUNTER_CNT2_STATE_FREEZE
- PERFCOUNTER_CNT2_STATE_HW
- PERFCOUNTER_CNT2_STATE_RESET
- PERFCOUNTER_CNT2_STATE_START
- PERFCOUNTER_CNT3_STATE
- PERFCOUNTER_CNT3_STATE_FREEZE
- PERFCOUNTER_CNT3_STATE_HW
- PERFCOUNTER_CNT3_STATE_RESET
- PERFCOUNTER_CNT3_STATE_START
- PERFCOUNTER_CNT4_STATE
- PERFCOUNTER_CNT4_STATE_FREEZE
- PERFCOUNTER_CNT4_STATE_HW
- PERFCOUNTER_CNT4_STATE_RESET
- PERFCOUNTER_CNT4_STATE_START
- PERFCOUNTER_CNT5_STATE
- PERFCOUNTER_CNT5_STATE_FREEZE
- PERFCOUNTER_CNT5_STATE_HW
- PERFCOUNTER_CNT5_STATE_RESET
- PERFCOUNTER_CNT5_STATE_START
- PERFCOUNTER_CNT6_STATE
- PERFCOUNTER_CNT6_STATE_FREEZE
- PERFCOUNTER_CNT6_STATE_HW
- PERFCOUNTER_CNT6_STATE_RESET
- PERFCOUNTER_CNT6_STATE_START
- PERFCOUNTER_CNT7_STATE
- PERFCOUNTER_CNT7_STATE_FREEZE
- PERFCOUNTER_CNT7_STATE_HW
- PERFCOUNTER_CNT7_STATE_RESET
- PERFCOUNTER_CNT7_STATE_START
- PERFCOUNTER_CNTL_SEL
- PERFCOUNTER_CNTL_SEL_0
- PERFCOUNTER_CNTL_SEL_1
- PERFCOUNTER_CNTL_SEL_2
- PERFCOUNTER_CNTL_SEL_3
- PERFCOUNTER_CNTL_SEL_4
- PERFCOUNTER_CNTL_SEL_5
- PERFCOUNTER_CNTL_SEL_6
- PERFCOUNTER_CNTL_SEL_7
- PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_INT_TYPE__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT
- PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK
- PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT
- PERFCOUNTER_CNTOFF_START_DIS
- PERFCOUNTER_CNTOFF_START_DISABLE
- PERFCOUNTER_CNTOFF_START_ENABLE
- PERFCOUNTER_COUNTED_VALUE_TYPE
- PERFCOUNTER_COUNTED_VALUE_TYPE_ACC
- PERFCOUNTER_COUNTED_VALUE_TYPE_MAX
- PERFCOUNTER_COUNTED_VALUE_TYPE_MIN
- PERFCOUNTER_CVALUE_SEL
- PERFCOUNTER_CVALUE_SEL_11_0
- PERFCOUNTER_CVALUE_SEL_15_0
- PERFCOUNTER_CVALUE_SEL_23_12
- PERFCOUNTER_CVALUE_SEL_31_16
- PERFCOUNTER_CVALUE_SEL_35_24
- PERFCOUNTER_CVALUE_SEL_47_0
- PERFCOUNTER_CVALUE_SEL_47_32
- PERFCOUNTER_CVALUE_SEL_47_36
- PERFCOUNTER_HW_CNTL_SEL
- PERFCOUNTER_HW_CNTL_SEL_CNTOFF
- PERFCOUNTER_HW_CNTL_SEL_RUNEN
- PERFCOUNTER_HW_STOP1_0
- PERFCOUNTER_HW_STOP1_1
- PERFCOUNTER_HW_STOP1_SEL
- PERFCOUNTER_HW_STOP2_0
- PERFCOUNTER_HW_STOP2_1
- PERFCOUNTER_HW_STOP2_SEL
- PERFCOUNTER_INC_MODE
- PERFCOUNTER_INC_MODE_BOTH_EDGE
- PERFCOUNTER_INC_MODE_LSB
- PERFCOUNTER_INC_MODE_MULTI_BIT
- PERFCOUNTER_INC_MODE_NEG_EDGE
- PERFCOUNTER_INC_MODE_POS_EDGE
- PERFCOUNTER_INT_DISABLE
- PERFCOUNTER_INT_EN
- PERFCOUNTER_INT_ENABLE
- PERFCOUNTER_INT_TYPE
- PERFCOUNTER_INT_TYPE_LEVEL
- PERFCOUNTER_INT_TYPE_PULSE
- PERFCOUNTER_IS_ACTIVE
- PERFCOUNTER_IS_IDLE
- PERFCOUNTER_OFF_MASK
- PERFCOUNTER_OFF_MASK_DISABLE
- PERFCOUNTER_OFF_MASK_ENABLE
- PERFCOUNTER_RESTART_DISABLE
- PERFCOUNTER_RESTART_EN
- PERFCOUNTER_RESTART_ENABLE
- PERFCOUNTER_RUNEN_MODE
- PERFCOUNTER_RUNEN_MODE_EDGE
- PERFCOUNTER_RUNEN_MODE_LEVEL
- PERFCOUNTER_SAMPLE
- PERFCOUNTER_START
- PERFCOUNTER_STATE_SEL0
- PERFCOUNTER_STATE_SEL0_GLOBAL
- PERFCOUNTER_STATE_SEL0_LOCAL
- PERFCOUNTER_STATE_SEL1
- PERFCOUNTER_STATE_SEL1_GLOBAL
- PERFCOUNTER_STATE_SEL1_LOCAL
- PERFCOUNTER_STATE_SEL2
- PERFCOUNTER_STATE_SEL2_GLOBAL
- PERFCOUNTER_STATE_SEL2_LOCAL
- PERFCOUNTER_STATE_SEL3
- PERFCOUNTER_STATE_SEL3_GLOBAL
- PERFCOUNTER_STATE_SEL3_LOCAL
- PERFCOUNTER_STATE_SEL4
- PERFCOUNTER_STATE_SEL4_GLOBAL
- PERFCOUNTER_STATE_SEL4_LOCAL
- PERFCOUNTER_STATE_SEL5
- PERFCOUNTER_STATE_SEL5_GLOBAL
- PERFCOUNTER_STATE_SEL5_LOCAL
- PERFCOUNTER_STATE_SEL6
- PERFCOUNTER_STATE_SEL6_GLOBAL
- PERFCOUNTER_STATE_SEL6_LOCAL
- PERFCOUNTER_STATE_SEL7
- PERFCOUNTER_STATE_SEL7_GLOBAL
- PERFCOUNTER_STATE_SEL7_LOCAL
- PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK
- PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT
- PERFCOUNTER_STOP
- PERFCTR_CLRPIC
- PERFCTR_GETPCR
- PERFCTR_OFF
- PERFCTR_ON
- PERFCTR_READ
- PERFCTR_SETPCR
- PERFECT
- PERFECT_F
- PERFECT_HASH_THRESHOLD
- PERFECT_REJ
- PERFMON_CMD_DESIRED_EVENTS
- PERFMON_CMD_DISABLE
- PERFMON_CMD_ENABLE
- PERFMON_CMD_ENABLE_CLEAR
- PERFMON_CMD_ENABLE_WRITE
- PERFMON_CMD_INT_FREQ
- PERFMON_CMD_I_STAT
- PERFMON_CMD_LOGGING_OPTIONS
- PERFMON_CMD_PMPC
- PERFMON_CMD_READ
- PERFMON_CMD_WRITE
- PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK
- PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT
- PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK
- PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT
- PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK
- PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT
- PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK
- PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT
- PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK
- PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT
- PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK
- PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT
- PERFMON_CNTL__PERFMON_RPT_COUNT_MASK
- PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT
- PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK
- PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT
- PERFMON_CNTL__PERFMON_STATE_MASK
- PERFMON_CNTL__PERFMON_STATE__SHIFT
- PERFMON_CNTOFF_AND
- PERFMON_CNTOFF_AND_OR
- PERFMON_CNTOFF_INT_DISABLE
- PERFMON_CNTOFF_INT_EN
- PERFMON_CNTOFF_INT_ENABLE
- PERFMON_CNTOFF_INT_TYPE
- PERFMON_CNTOFF_INT_TYPE_LEVEL
- PERFMON_CNTOFF_INT_TYPE_PULSE
- PERFMON_CNTOFF_OR
- PERFMON_COUNTER_MODE
- PERFMON_COUNTER_MODE_ACCUM
- PERFMON_COUNTER_MODE_ACTIVE_CYCLES
- PERFMON_COUNTER_MODE_CYCLES_EQ_HI
- PERFMON_COUNTER_MODE_CYCLES_GE_HI
- PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT
- PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT
- PERFMON_COUNTER_MODE_DIRTY
- PERFMON_COUNTER_MODE_INACTIVE_CYCLES
- PERFMON_COUNTER_MODE_MAX
- PERFMON_COUNTER_MODE_RESERVED
- PERFMON_COUNTER_MODE_SAMPLE
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK
- PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT
- PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK
- PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT
- PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK
- PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT
- PERFMON_HI__PERFMON_HI_MASK
- PERFMON_HI__PERFMON_HI__SHIFT
- PERFMON_HI__PERFMON_READ_SEL_MASK
- PERFMON_HI__PERFMON_READ_SEL__SHIFT
- PERFMON_IS_SYSWIDE
- PERFMON_LOW__PERFMON_LOW_MASK
- PERFMON_LOW__PERFMON_LOW__SHIFT
- PERFMON_SPM_MODE
- PERFMON_SPM_MODE_16BIT_CLAMP
- PERFMON_SPM_MODE_16BIT_NO_CLAMP
- PERFMON_SPM_MODE_32BIT_CLAMP
- PERFMON_SPM_MODE_32BIT_NO_CLAMP
- PERFMON_SPM_MODE_OFF
- PERFMON_SPM_MODE_RESERVED_5
- PERFMON_SPM_MODE_RESERVED_6
- PERFMON_SPM_MODE_RESERVED_7
- PERFMON_SPM_MODE_TEST_MODE_0
- PERFMON_SPM_MODE_TEST_MODE_1
- PERFMON_SPM_MODE_TEST_MODE_2
- PERFMON_STATE
- PERFMON_STATE_FREEZE
- PERFMON_STATE_HW
- PERFMON_STATE_RESET
- PERFMON_STATE_START
- PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK
- PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT
- PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK
- PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT
- PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK
- PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT
- PERFORMANCE_TRACE_END
- PERFORMANCE_TRACE_START
- PERFORMANT_MODE
- PERFORM_EMU_COMMANDS
- PERFORM_SOFTWARE_RESET
- PERFORM_SS_FUNC
- PERFOUT_STRING
- PERFPROBE_GROUP
- PERF_8xx_ID_CPU_CYCLES
- PERF_8xx_ID_DTLB_LOAD_MISS
- PERF_8xx_ID_HW_INSTRUCTIONS
- PERF_8xx_ID_ITLB_LOAD_MISS
- PERF_ADDR_FILTER_ACTION_FILTER
- PERF_ADDR_FILTER_ACTION_START
- PERF_ADDR_FILTER_ACTION_STOP
- PERF_ADSLPLLCTL_REG
- PERF_AFFINITY_CPU
- PERF_AFFINITY_MAX
- PERF_AFFINITY_NODE
- PERF_AFFINITY_SYS
- PERF_ALIGN
- PERF_ATTACH_CONTEXT
- PERF_ATTACH_GROUP
- PERF_ATTACH_ITRACE
- PERF_ATTACH_TASK
- PERF_ATTACH_TASK_DATA
- PERF_ATTR_CFG1_KVM_PMU_CHAINED
- PERF_ATTR_SIZE_VER0
- PERF_ATTR_SIZE_VER1
- PERF_ATTR_SIZE_VER2
- PERF_ATTR_SIZE_VER3
- PERF_ATTR_SIZE_VER4
- PERF_ATTR_SIZE_VER5
- PERF_AUXTRACE_ARM_SPE
- PERF_AUXTRACE_CS_ETM
- PERF_AUXTRACE_ERROR_ITRACE
- PERF_AUXTRACE_ERROR_MAX
- PERF_AUXTRACE_INDEX_ENTRY_COUNT
- PERF_AUXTRACE_INTEL_BTS
- PERF_AUXTRACE_INTEL_PT
- PERF_AUXTRACE_RECORD_ALIGNMENT
- PERF_AUXTRACE_S390_CPUMSF
- PERF_AUXTRACE_UNKNOWN
- PERF_AUX_FLAG_COLLISION
- PERF_AUX_FLAG_OVERWRITE
- PERF_AUX_FLAG_PARTIAL
- PERF_AUX_FLAG_TRUNCATED
- PERF_AUX_GFP
- PERF_BPF_EVENT_MAX
- PERF_BPF_EVENT_PROG_LOAD
- PERF_BPF_EVENT_PROG_UNLOAD
- PERF_BPF_EVENT_UNKNOWN
- PERF_BPF_PROBE_GROUP
- PERF_BRANCH_MASK
- PERF_BR_CALL
- PERF_BR_COND
- PERF_BR_COND_CALL
- PERF_BR_COND_RET
- PERF_BR_IND
- PERF_BR_IND_CALL
- PERF_BR_MAX
- PERF_BR_RET
- PERF_BR_SYSCALL
- PERF_BR_SYSRET
- PERF_BR_UNCOND
- PERF_BR_UNKNOWN
- PERF_BUF_LEN
- PERF_BUILD_ID_H_
- PERF_CACHELINE_H
- PERF_CACHE_MAP_ALL_UNSUPPORTED
- PERF_CCU_2D_BUSY_CYCLES
- PERF_CCU_2D_PIXELS
- PERF_CCU_2D_RD_REQ
- PERF_CCU_2D_REORDER_STARVE_CYCLES
- PERF_CCU_2D_WR_REQ
- PERF_CCU_BUSY_CYCLES
- PERF_CCU_COLOR_BLOCKS
- PERF_CCU_COLOR_BLOCK_HIT
- PERF_CCU_COLOR_READ_FLAG0_COUNT
- PERF_CCU_COLOR_READ_FLAG1_COUNT
- PERF_CCU_COLOR_READ_FLAG2_COUNT
- PERF_CCU_COLOR_READ_FLAG3_COUNT
- PERF_CCU_COLOR_READ_FLAG4_COUNT
- PERF_CCU_COLOR_READ_FLAG5_COUNT
- PERF_CCU_COLOR_READ_FLAG6_COUNT
- PERF_CCU_COLOR_READ_FLAG8_COUNT
- PERF_CCU_DEPTH_BLOCKS
- PERF_CCU_DEPTH_BLOCK_HIT
- PERF_CCU_DEPTH_READ_FLAG0_COUNT
- PERF_CCU_DEPTH_READ_FLAG1_COUNT
- PERF_CCU_DEPTH_READ_FLAG2_COUNT
- PERF_CCU_DEPTH_READ_FLAG3_COUNT
- PERF_CCU_DEPTH_READ_FLAG4_COUNT
- PERF_CCU_DEPTH_READ_FLAG5_COUNT
- PERF_CCU_DEPTH_READ_FLAG6_COUNT
- PERF_CCU_DEPTH_READ_FLAG8_COUNT
- PERF_CCU_GMEM_READ
- PERF_CCU_GMEM_WRITE
- PERF_CCU_PARTIAL_BLOCK_READ
- PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN
- PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN
- PERF_CCU_STARVE_CYCLES_FLAG_RETURN
- PERF_CGROUP_SWIN
- PERF_CGROUP_SWOUT
- PERF_CKCTL_REG
- PERF_CLIENT_UTCL1_INFLIGHT
- PERF_CMD_CLEAR
- PERF_CMD_INVAL
- PERF_CMD_RSIZE
- PERF_CMD_RXLAT
- PERF_CMD_SSIZE
- PERF_CMD_SXLAT
- PERF_CMPDECMP_2D_BUSY_CYCLES
- PERF_CMPDECMP_2D_OUTPUT_TRANS
- PERF_CMPDECMP_2D_PIXELS
- PERF_CMPDECMP_2D_RD_DATA
- PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR
- PERF_CMPDECMP_2D_WR_DATA
- PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT
- PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT
- PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT
- PERF_CMPDECMP_FLAG_FETCH_CYCLES
- PERF_CMPDECMP_FLAG_FETCH_SAMPLES
- PERF_CMPDECMP_STALL_CYCLES_ARB
- PERF_CMPDECMP_STALL_CYCLES_VBIF
- PERF_CMPDECMP_VBIF_LATENCY_CYCLES
- PERF_CMPDECMP_VBIF_LATENCY_SAMPLES
- PERF_CMPDECMP_VBIF_READ_DATA
- PERF_CMPDECMP_VBIF_READ_DATA_CCU
- PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0
- PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1
- PERF_CMPDECMP_VBIF_READ_REQUEST
- PERF_CMPDECMP_VBIF_WRITE_DATA
- PERF_CMPDECMP_VBIF_WRITE_DATA_CCU
- PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE
- PERF_CMPDECMP_VBIF_WRITE_REQUEST
- PERF_COLOR_BG_RED
- PERF_COLOR_BLUE
- PERF_COLOR_BOLD
- PERF_COLOR_CYAN
- PERF_COLOR_GREEN
- PERF_COLOR_MAGENTA
- PERF_COLOR_NORMAL
- PERF_COLOR_RED
- PERF_COLOR_RESET
- PERF_COLOR_YELLOW
- PERF_COMPRESS_H
- PERF_COMP_MAX
- PERF_COMP_NONE
- PERF_COMP_ZSTD
- PERF_CONST
- PERF_CONTEXT_GUEST
- PERF_CONTEXT_GUEST_KERNEL
- PERF_CONTEXT_GUEST_USER
- PERF_CONTEXT_HV
- PERF_CONTEXT_KERNEL
- PERF_CONTEXT_MAX
- PERF_CONTEXT_USER
- PERF_COPYFILE_H_
- PERF_COUNTER
- PERF_COUNTER2_INTERRUPT_EN
- PERF_COUNTER2_INTERRUPT_STATUS
- PERF_COUNTER_API
- PERF_COUNTER_INTERRUPT_EN
- PERF_COUNTER_INTERRUPT_STATUS
- PERF_COUNT_ARC_BPOK
- PERF_COUNT_ARC_DCLM
- PERF_COUNT_ARC_DCSM
- PERF_COUNT_ARC_EDTLB
- PERF_COUNT_ARC_EITLB
- PERF_COUNT_ARC_HW_MAX
- PERF_COUNT_ARC_ICM
- PERF_COUNT_ARC_LDC
- PERF_COUNT_ARC_STC
- PERF_COUNT_BUF_SIZE
- PERF_COUNT_HW_BRANCH_INSTRUCTIONS
- PERF_COUNT_HW_BRANCH_MISSES
- PERF_COUNT_HW_BUS_CYCLES
- PERF_COUNT_HW_CACHE_BPU
- PERF_COUNT_HW_CACHE_DTLB
- PERF_COUNT_HW_CACHE_ITLB
- PERF_COUNT_HW_CACHE_L1D
- PERF_COUNT_HW_CACHE_L1I
- PERF_COUNT_HW_CACHE_LL
- PERF_COUNT_HW_CACHE_MAX
- PERF_COUNT_HW_CACHE_MISSES
- PERF_COUNT_HW_CACHE_NODE
- PERF_COUNT_HW_CACHE_OP_MAX
- PERF_COUNT_HW_CACHE_OP_PREFETCH
- PERF_COUNT_HW_CACHE_OP_READ
- PERF_COUNT_HW_CACHE_OP_WRITE
- PERF_COUNT_HW_CACHE_REFERENCES
- PERF_COUNT_HW_CACHE_RESULT_ACCESS
- PERF_COUNT_HW_CACHE_RESULT_MAX
- PERF_COUNT_HW_CACHE_RESULT_MISS
- PERF_COUNT_HW_CPU_CYCLES
- PERF_COUNT_HW_INSTRUCTIONS
- PERF_COUNT_HW_MAX
- PERF_COUNT_HW_REF_CPU_CYCLES
- PERF_COUNT_HW_STALLED_CYCLES_BACKEND
- PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
- PERF_COUNT_SW_ALIGNMENT_FAULTS
- PERF_COUNT_SW_BPF_OUTPUT
- PERF_COUNT_SW_CONTEXT_SWITCHES
- PERF_COUNT_SW_CPU_CLOCK
- PERF_COUNT_SW_CPU_MIGRATIONS
- PERF_COUNT_SW_DUMMY
- PERF_COUNT_SW_EMULATION_FAULTS
- PERF_COUNT_SW_MAX
- PERF_COUNT_SW_PAGE_FAULTS
- PERF_COUNT_SW_PAGE_FAULTS_MAJ
- PERF_COUNT_SW_PAGE_FAULTS_MIN
- PERF_COUNT_SW_TASK_CLOCK
- PERF_CPUFEATURE_H
- PERF_CPUM_CF_MAX_CTR
- PERF_CPUM_SF_BASIC_MODE
- PERF_CPUM_SF_DIAG_MODE
- PERF_CPUM_SF_FREQ_MODE
- PERF_CPUM_SF_FULL_BLOCKS
- PERF_CPUM_SF_MAX_CTR
- PERF_CPUM_SF_MODE_MASK
- PERF_CPU_HRTIMER
- PERF_CPU_MAP__CPUS
- PERF_CPU_MAP__MASK
- PERF_CP_AHB_STALL_SQE_GMU
- PERF_CP_AHB_STALL_SQE_RD_OTHER
- PERF_CP_AHB_STALL_SQE_WR_OTHER
- PERF_CP_AHB_WR_STALL_PRE_DRAWS
- PERF_CP_ALWAYS_COUNT
- PERF_CP_BUSY_CYCLES
- PERF_CP_BUSY_GFX_CORE_IDLE
- PERF_CP_CACHE_FLUSH
- PERF_CP_CLUSTER0_EMPTY
- PERF_CP_CLUSTER1_EMPTY
- PERF_CP_CLUSTER2_EMPTY
- PERF_CP_CLUSTER3_EMPTY
- PERF_CP_CLUSTER4_EMPTY
- PERF_CP_CLUSTER5_EMPTY
- PERF_CP_CONTEXT_DONE
- PERF_CP_DEAD_DRAWS_IN_BIN_RENDER
- PERF_CP_LONG_PREEMPTIONS
- PERF_CP_MEMORY_POOL_ABOVE_THRESH
- PERF_CP_MEMORY_POOL_EMPTY
- PERF_CP_MEMORY_POOL_SYNC_STALL
- PERF_CP_ME_BUSY_WORKING
- PERF_CP_ME_FIFO_EMPTY_PFP_BUSY
- PERF_CP_ME_FIFO_EMPTY_PFP_IDLE
- PERF_CP_ME_FIFO_FULL_ME_BUSY
- PERF_CP_ME_FIFO_FULL_ME_NON_WORKING
- PERF_CP_ME_ICACHE_HIT
- PERF_CP_ME_ICACHE_MISS
- PERF_CP_ME_IDLE
- PERF_CP_ME_STALL_CYCLES_ANY
- PERF_CP_ME_STARVE_CYCLES_ANY
- PERF_CP_MODE_SWITCH
- PERF_CP_NUM_PREEMPTIONS
- PERF_CP_PFP_BUSY_WORKING
- PERF_CP_PFP_ICACHE_HIT
- PERF_CP_PFP_ICACHE_MISS
- PERF_CP_PFP_IDLE
- PERF_CP_PFP_MATCH_PM4_PKT_PROFILE
- PERF_CP_PFP_STALL_CYCLES_ANY
- PERF_CP_PFP_STARVE_CYCLES_ANY
- PERF_CP_PM4_DATA
- PERF_CP_PM4_HEADERS
- PERF_CP_PREDICATED_DRAWS_KILLED
- PERF_CP_PREEMPTION_REACTION_DELAY
- PERF_CP_PREEMPTION_SWITCH_IN_TIME
- PERF_CP_PREEMPTION_SWITCH_OUT_TIME
- PERF_CP_SQE_CTXT_REG_BUNCH_EXEC
- PERF_CP_SQE_DRAW_EXEC
- PERF_CP_SQE_EXEC_PROFILED
- PERF_CP_SQE_IDLE
- PERF_CP_SQE_INSTR_COUNTER
- PERF_CP_SQE_I_CACHE_STARVE
- PERF_CP_SQE_LOAD_STATE_EXEC
- PERF_CP_SQE_MRB_STARVE
- PERF_CP_SQE_PIPE_OUT_STALL
- PERF_CP_SQE_PM4_STARVE_RB_IB
- PERF_CP_SQE_PM4_STARVE_SDS
- PERF_CP_SQE_PM4_WFI_STALL
- PERF_CP_SQE_RRB_STARVE
- PERF_CP_SQE_SAVE_SDS_STATE
- PERF_CP_SQE_SYNC_STALL
- PERF_CP_SQE_SYS_WFI_STALL
- PERF_CP_SQE_T4_EXEC
- PERF_CP_SQE_VSD_STARVE
- PERF_CP_VBIF_READ_BEATS
- PERF_CP_VBIF_WRITE_BEATS
- PERF_CP_VSD_DECODE_STARVE
- PERF_CP_ZPASS_DONE
- PERF_CSTATE_CORE_C1_RES
- PERF_CSTATE_CORE_C3_RES
- PERF_CSTATE_CORE_C6_RES
- PERF_CSTATE_CORE_C7_RES
- PERF_CSTATE_CORE_EVENT_MAX
- PERF_CSTATE_PKG_C10_RES
- PERF_CSTATE_PKG_C2_RES
- PERF_CSTATE_PKG_C3_RES
- PERF_CSTATE_PKG_C6_RES
- PERF_CSTATE_PKG_C7_RES
- PERF_CSTATE_PKG_C8_RES
- PERF_CSTATE_PKG_C9_RES
- PERF_CSTATE_PKG_EVENT_MAX
- PERF_CTRL
- PERF_CURRENT_PID
- PERF_DATA_MODE_READ
- PERF_DATA_MODE_WRITE
- PERF_DEBUGFS_ENVIRONMENT
- PERF_DESCRIBE_FASTCHANNEL
- PERF_DESCRIBE_LEVELS
- PERF_DIR_VERSION
- PERF_DOMAIN_ATTRIBUTES
- PERF_DWARF2_H
- PERF_EFLAGS_EXACT
- PERF_EFLAGS_VM
- PERF_EF_RELOAD
- PERF_EF_START
- PERF_EF_UPDATE
- PERF_ELF_C_READ_MMAP
- PERF_EVENT_CONFIG
- PERF_EVENT_CONFIG_EBB_SHIFT
- PERF_EVENT_CPUM_CF_DIAG
- PERF_EVENT_CPUM_SF
- PERF_EVENT_CPUM_SF_DIAG
- PERF_EVENT_ID
- PERF_EVENT_IOC_DISABLE
- PERF_EVENT_IOC_ENABLE
- PERF_EVENT_IOC_ID
- PERF_EVENT_IOC_MODIFY_ATTRIBUTES
- PERF_EVENT_IOC_PAUSE_OUTPUT
- PERF_EVENT_IOC_PERIOD
- PERF_EVENT_IOC_QUERY_BPF
- PERF_EVENT_IOC_REFRESH
- PERF_EVENT_IOC_RESET
- PERF_EVENT_IOC_SET_BPF
- PERF_EVENT_IOC_SET_FILTER
- PERF_EVENT_IOC_SET_OUTPUT
- PERF_EVENT_P4_H
- PERF_EVENT_RAW
- PERF_EVENT_STATE_ACTIVE
- PERF_EVENT_STATE_DEAD
- PERF_EVENT_STATE_ERROR
- PERF_EVENT_STATE_EXIT
- PERF_EVENT_STATE_INACTIVE
- PERF_EVENT_STATE_OFF
- PERF_EVENT_TYPE
- PERF_EVENT_UPDATE__CPUS
- PERF_EVENT_UPDATE__NAME
- PERF_EVENT_UPDATE__SCALE
- PERF_EVENT_UPDATE__UNIT
- PERF_EVLIST__HLIST_BITS
- PERF_EVLIST__HLIST_SIZE
- PERF_EVSEL__CONFIG_TERM_AUX_OUTPUT
- PERF_EVSEL__CONFIG_TERM_BRANCH
- PERF_EVSEL__CONFIG_TERM_CALLGRAPH
- PERF_EVSEL__CONFIG_TERM_DRV_CFG
- PERF_EVSEL__CONFIG_TERM_FREQ
- PERF_EVSEL__CONFIG_TERM_INHERIT
- PERF_EVSEL__CONFIG_TERM_MAX_EVENTS
- PERF_EVSEL__CONFIG_TERM_MAX_STACK
- PERF_EVSEL__CONFIG_TERM_OVERWRITE
- PERF_EVSEL__CONFIG_TERM_PERCORE
- PERF_EVSEL__CONFIG_TERM_PERIOD
- PERF_EVSEL__CONFIG_TERM_STACK_USER
- PERF_EVSEL__CONFIG_TERM_TIME
- PERF_EVSEL__MAX_ALIASES
- PERF_EV_CAP_READ_ACTIVE_PKG
- PERF_EV_CAP_SOFTWARE
- PERF_EXTIRQ_CFG_REG2_6368
- PERF_EXTIRQ_CFG_REG_3368
- PERF_EXTIRQ_CFG_REG_6328
- PERF_EXTIRQ_CFG_REG_6338
- PERF_EXTIRQ_CFG_REG_6345
- PERF_EXTIRQ_CFG_REG_6348
- PERF_EXTIRQ_CFG_REG_6358
- PERF_EXTIRQ_CFG_REG_6362
- PERF_EXTIRQ_CFG_REG_6368
- PERF_FLAG
- PERF_FLAG_ALL
- PERF_FLAG_FD_CLOEXEC
- PERF_FLAG_FD_NO_GROUP
- PERF_FLAG_FD_OUTPUT
- PERF_FLAG_PID_CGROUP
- PERF_FORMAT_GROUP
- PERF_FORMAT_ID
- PERF_FORMAT_MAX
- PERF_FORMAT_TOTAL_TIMES
- PERF_FORMAT_TOTAL_TIME_ENABLED
- PERF_FORMAT_TOTAL_TIME_RUNNING
- PERF_GTK_DSO
- PERF_HEADER_VERSION_1
- PERF_HEADER_VERSION_2
- PERF_HES_ARCH
- PERF_HES_STOPPED
- PERF_HES_UPTODATE
- PERF_HLSQ_BUSY_CYCLES
- PERF_HLSQ_COMPUTE_DRAWCALLS
- PERF_HLSQ_CS_INVOCATIONS
- PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC
- PERF_HLSQ_DUAL_FS_PROG_ACTIVE
- PERF_HLSQ_DUAL_VS_PROG_ACTIVE
- PERF_HLSQ_FS_BATCH_COUNT_ZERO
- PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING
- PERF_HLSQ_FS_STAGE_1X_WAVES
- PERF_HLSQ_FS_STAGE_2X_WAVES
- PERF_HLSQ_FS_STAGE_32_WAVES
- PERF_HLSQ_FS_STAGE_64_WAVES
- PERF_HLSQ_PIXELS
- PERF_HLSQ_QUADS
- PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE
- PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE
- PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE
- PERF_HLSQ_STALL_CYCLES_SP_STATE
- PERF_HLSQ_STALL_CYCLES_UCHE
- PERF_HLSQ_STALL_CYCLES_VPC
- PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE
- PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE
- PERF_HLSQ_UCHE_LATENCY_COUNT
- PERF_HLSQ_UCHE_LATENCY_CYCLES
- PERF_HLSQ_VS_BATCH_COUNT_ZERO
- PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE
- PERF_HLSQ_WAVE_PENDING_NO_QUAD
- PERF_HOOK
- PERF_HPP_DIFF__BASELINE
- PERF_HPP_DIFF__CYCLES
- PERF_HPP_DIFF__DELTA
- PERF_HPP_DIFF__DELTA_ABS
- PERF_HPP_DIFF__FORMULA
- PERF_HPP_DIFF__MAX_INDEX
- PERF_HPP_DIFF__PERIOD
- PERF_HPP_DIFF__PERIOD_BASELINE
- PERF_HPP_DIFF__RATIO
- PERF_HPP_DIFF__WEIGHTED_DIFF
- PERF_HPP__MAX_INDEX
- PERF_HPP__OVERHEAD
- PERF_HPP__OVERHEAD_ACC
- PERF_HPP__OVERHEAD_GUEST_SYS
- PERF_HPP__OVERHEAD_GUEST_US
- PERF_HPP__OVERHEAD_SYS
- PERF_HPP__OVERHEAD_US
- PERF_HPP__PERIOD
- PERF_HPP__SAMPLES
- PERF_IDX2OFF
- PERF_IMAGES_H
- PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE
- PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE
- PERF_INDEX_RECEIVE_QUALIFIED_BUSY
- PERF_INDEX_RECEIVE_QUALIFIED_STARVED
- PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO
- PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE
- PERF_INDEX_REQUEST_QUALIFIED_BUSY
- PERF_INDEX_REQUEST_QUALIFIED_STARVED
- PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO
- PERF_INDEX_REQUEST_WAITING_ON_TOKENS
- PERF_IOC_FLAG_GROUP
- PERF_IP_FLAG_ASYNC
- PERF_IP_FLAG_BRANCH
- PERF_IP_FLAG_CALL
- PERF_IP_FLAG_CHARS
- PERF_IP_FLAG_CONDITIONAL
- PERF_IP_FLAG_INTERRUPT
- PERF_IP_FLAG_IN_TX
- PERF_IP_FLAG_RETURN
- PERF_IP_FLAG_SYSCALLRET
- PERF_IP_FLAG_TRACE_BEGIN
- PERF_IP_FLAG_TRACE_END
- PERF_IP_FLAG_TX_ABORT
- PERF_IRQMASK_3368_REG
- PERF_IRQMASK_6328_REG
- PERF_IRQMASK_6338_REG
- PERF_IRQMASK_6345_REG
- PERF_IRQMASK_6348_REG
- PERF_IRQMASK_6358_REG
- PERF_IRQMASK_6362_REG
- PERF_IRQMASK_6368_REG
- PERF_IRQSTAT_3368_REG
- PERF_IRQSTAT_6328_REG
- PERF_IRQSTAT_6338_REG
- PERF_IRQSTAT_6345_REG
- PERF_IRQSTAT_6348_REG
- PERF_IRQSTAT_6358_REG
- PERF_IRQSTAT_6362_REG
- PERF_IRQSTAT_6368_REG
- PERF_ITRACE_DEFAULT_CALLCHAIN_SZ
- PERF_ITRACE_DEFAULT_LAST_BRANCH_SZ
- PERF_ITRACE_DEFAULT_PERIOD
- PERF_ITRACE_DEFAULT_PERIOD_TYPE
- PERF_ITRACE_MAX_CALLCHAIN_SZ
- PERF_ITRACE_MAX_LAST_BRANCH_SZ
- PERF_ITRACE_PERIOD_INSTRUCTIONS
- PERF_ITRACE_PERIOD_NANOSECS
- PERF_ITRACE_PERIOD_TICKS
- PERF_KCORE_EXTRACT
- PERF_KVM__MAX_EVENTS_PER_MMAP
- PERF_LEVEL_ACTIVITY
- PERF_LEVEL_GET
- PERF_LEVEL_POWER_CONTAINMENT
- PERF_LEVEL_SET
- PERF_LIMITED
- PERF_LIMITS_GET
- PERF_LIMITS_SET
- PERF_LINUX_LINKAGE_H_
- PERF_LRZ_BUSY_CYCLES
- PERF_LRZ_FEEDBACK_ACCEPT
- PERF_LRZ_FEEDBACK_DISCARD
- PERF_LRZ_FEEDBACK_STALL
- PERF_LRZ_FULLY_COVERED_TILES
- PERF_LRZ_FULL_8X8_TILES
- PERF_LRZ_LRZ_READ
- PERF_LRZ_LRZ_WRITE
- PERF_LRZ_MERGE_CACHE_UPDATING
- PERF_LRZ_PARTIAL_8X8_TILES
- PERF_LRZ_PARTIAL_COVERED_TILES
- PERF_LRZ_PRIM_KILLED_BY_LRZ
- PERF_LRZ_PRIM_KILLED_BY_MASKGEN
- PERF_LRZ_RAS_MASK_TRANS
- PERF_LRZ_READ_LATENCY
- PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH
- PERF_LRZ_STALL_CYCLES_RB
- PERF_LRZ_STALL_CYCLES_RB_BPLANE
- PERF_LRZ_STALL_CYCLES_RB_ZPLANE
- PERF_LRZ_STALL_CYCLES_UCHE
- PERF_LRZ_STALL_CYCLES_VC
- PERF_LRZ_STALL_CYCLES_VPC
- PERF_LRZ_STALL_CYCLES_VSC
- PERF_LRZ_STARVE_CYCLES_RAS
- PERF_LRZ_TILE_KILLED
- PERF_LRZ_TOTAL_PIXEL
- PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ
- PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ
- PERF_LVL_A15
- PERF_LVL_A7
- PERF_MAGIC
- PERF_MAP_ALL_UNSUPPORTED
- PERF_MAX_BRANCH_DEPTH
- PERF_MAX_CONTEXTS_PER_STACK
- PERF_MAX_STACK_DEPTH
- PERF_MAX_TRACE_SIZE
- PERF_MEMSWAP_H_
- PERF_MEM_DATA_SRC_NONE
- PERF_MEM_EVENTS__LOAD
- PERF_MEM_EVENTS__MAX
- PERF_MEM_EVENTS__STORE
- PERF_MEM_LOCK_LOCKED
- PERF_MEM_LOCK_NA
- PERF_MEM_LOCK_SHIFT
- PERF_MEM_LVLNUM_ANY_CACHE
- PERF_MEM_LVLNUM_L1
- PERF_MEM_LVLNUM_L2
- PERF_MEM_LVLNUM_L3
- PERF_MEM_LVLNUM_L4
- PERF_MEM_LVLNUM_LFB
- PERF_MEM_LVLNUM_NA
- PERF_MEM_LVLNUM_PMEM
- PERF_MEM_LVLNUM_RAM
- PERF_MEM_LVLNUM_SHIFT
- PERF_MEM_LVL_HIT
- PERF_MEM_LVL_IO
- PERF_MEM_LVL_L1
- PERF_MEM_LVL_L2
- PERF_MEM_LVL_L3
- PERF_MEM_LVL_LFB
- PERF_MEM_LVL_LOC_RAM
- PERF_MEM_LVL_MISS
- PERF_MEM_LVL_NA
- PERF_MEM_LVL_REM_CCE1
- PERF_MEM_LVL_REM_CCE2
- PERF_MEM_LVL_REM_RAM1
- PERF_MEM_LVL_REM_RAM2
- PERF_MEM_LVL_SHIFT
- PERF_MEM_LVL_UNC
- PERF_MEM_NA
- PERF_MEM_OP_EXEC
- PERF_MEM_OP_LOAD
- PERF_MEM_OP_NA
- PERF_MEM_OP_PFETCH
- PERF_MEM_OP_SHIFT
- PERF_MEM_OP_STORE
- PERF_MEM_REMOTE_REMOTE
- PERF_MEM_REMOTE_SHIFT
- PERF_MEM_S
- PERF_MEM_SNOOPX_FWD
- PERF_MEM_SNOOPX_SHIFT
- PERF_MEM_SNOOP_HIT
- PERF_MEM_SNOOP_HITM
- PERF_MEM_SNOOP_MISS
- PERF_MEM_SNOOP_NA
- PERF_MEM_SNOOP_NONE
- PERF_MEM_SNOOP_SHIFT
- PERF_MEM_TLB_HIT
- PERF_MEM_TLB_L1
- PERF_MEM_TLB_L2
- PERF_MEM_TLB_MISS
- PERF_MEM_TLB_NA
- PERF_MEM_TLB_OS
- PERF_MEM_TLB_SHIFT
- PERF_MEM_TLB_WK
- PERF_MIPSPLLCTL_REG
- PERF_MODE_INT
- PERF_MON_CLR_REG
- PERF_MON_CNTH_REG
- PERF_MON_CNTL_REG
- PERF_MON_CTRL_REG
- PERF_MSG_CMD
- PERF_MSG_CNT
- PERF_MSG_HDATA
- PERF_MSG_LDATA
- PERF_MSR_APERF
- PERF_MSR_EVENT_MAX
- PERF_MSR_IRPERF
- PERF_MSR_MPERF
- PERF_MSR_PPERF
- PERF_MSR_PTSC
- PERF_MSR_SMI
- PERF_MSR_THERM
- PERF_MSR_TSC
- PERF_NOTIFY_LEVEL
- PERF_NOTIFY_LIMITS
- PERF_NO_CPU
- PERF_NO_GROUP
- PERF_NO_PID
- PERF_NR_CONTEXTS
- PERF_OUTPUT_ADDR
- PERF_OUTPUT_BPF_OUTPUT
- PERF_OUTPUT_BRSTACK
- PERF_OUTPUT_BRSTACKINSN
- PERF_OUTPUT_BRSTACKOFF
- PERF_OUTPUT_BRSTACKSYM
- PERF_OUTPUT_CALLINDENT
- PERF_OUTPUT_COMM
- PERF_OUTPUT_CPU
- PERF_OUTPUT_DATA_SRC
- PERF_OUTPUT_DSO
- PERF_OUTPUT_EVNAME
- PERF_OUTPUT_INSN
- PERF_OUTPUT_INSNLEN
- PERF_OUTPUT_IP
- PERF_OUTPUT_IPC
- PERF_OUTPUT_IREGS
- PERF_OUTPUT_METRIC
- PERF_OUTPUT_MISC
- PERF_OUTPUT_PERIOD
- PERF_OUTPUT_PHYS_ADDR
- PERF_OUTPUT_PID
- PERF_OUTPUT_SRCCODE
- PERF_OUTPUT_SRCLINE
- PERF_OUTPUT_SYM
- PERF_OUTPUT_SYMOFFSET
- PERF_OUTPUT_SYNTH
- PERF_OUTPUT_TID
- PERF_OUTPUT_TIME
- PERF_OUTPUT_TRACE
- PERF_OUTPUT_UREGS
- PERF_OUTPUT_WEIGHT
- PERF_PAGER_ENVIRONMENT
- PERF_PAPC_CCGSM_BUSY
- PERF_PAPC_CCGSM_IDLE
- PERF_PAPC_CCGSM_STALLED
- PERF_PAPC_CLIPGA_BUSY
- PERF_PAPC_CLIPGA_IDLE
- PERF_PAPC_CLIPGA_STALLED
- PERF_PAPC_CLIPGA_STARVED_VTE_CLIP
- PERF_PAPC_CLIPGA_VTE_KILL_PRIM
- PERF_PAPC_CLIPSM_BUSY
- PERF_PAPC_CLIPSM_IDLE
- PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP
- PERF_PAPC_CLIPSM_WAIT_CLIPGA
- PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM
- PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH
- PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ
- PERF_PAPC_CLIP_BUSY
- PERF_PAPC_CLIP_IDLE
- PERF_PAPC_CLPRIM_BUSY
- PERF_PAPC_CLPRIM_IDLE
- PERF_PAPC_CLPRIM_STALLED
- PERF_PAPC_CLPRIM_STARVED_CCGSM
- PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_1
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_2
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_3
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_4
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12
- PERF_PAPC_CLPR_CLIP_PLANE_FAR
- PERF_PAPC_CLPR_CLIP_PLANE_LEFT
- PERF_PAPC_CLPR_CLIP_PLANE_NEAR
- PERF_PAPC_CLPR_CLIP_PLANE_RIGHT
- PERF_PAPC_CLPR_CLIP_PLANE_TOP
- PERF_PAPC_CLPR_CULL_PRIM
- PERF_PAPC_CLPR_CULL_TO_NULL_PRIM
- PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM
- PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE
- PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM
- PERF_PAPC_CLPR_UCP_CLIP_PRIM
- PERF_PAPC_CLPR_UCP_CULL_PRIM
- PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM
- PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM
- PERF_PAPC_CLPR_VVUCP_CLIP_PRIM
- PERF_PAPC_CLPR_VVUCP_CULL_PRIM
- PERF_PAPC_CLPR_VV_CLIP_PRIM
- PERF_PAPC_CLPR_VV_CULL_PRIM
- PERF_PAPC_CLSM_CLIPPING_PRIM
- PERF_PAPC_CLSM_CULL_TO_NULL_PRIM
- PERF_PAPC_CLSM_NULL_PRIM
- PERF_PAPC_CLSM_OUT_PRIM_CNT_1
- PERF_PAPC_CLSM_OUT_PRIM_CNT_2
- PERF_PAPC_CLSM_OUT_PRIM_CNT_3
- PERF_PAPC_CLSM_OUT_PRIM_CNT_4
- PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8
- PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13
- PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM
- PERF_PAPC_CL_DYN_SCLK_VLD
- PERF_PAPC_PASX_DISABLE_PIPE
- PERF_PAPC_PASX_FIRST_DEAD
- PERF_PAPC_PASX_FIRST_VECTOR
- PERF_PAPC_PASX_REC_BUSY
- PERF_PAPC_PASX_REC_IDLE
- PERF_PAPC_PASX_REC_STALLED
- PERF_PAPC_PASX_REC_STALLED_CCGSM_IN
- PERF_PAPC_PASX_REC_STALLED_POS_MEM
- PERF_PAPC_PASX_REC_STARVED_SX
- PERF_PAPC_PASX_REQ
- PERF_PAPC_PASX_REQ_BUSY
- PERF_PAPC_PASX_REQ_IDLE
- PERF_PAPC_PASX_REQ_STALLED
- PERF_PAPC_PASX_SE0_FIRST_VECTOR
- PERF_PAPC_PASX_SE0_REQ
- PERF_PAPC_PASX_SE0_SECOND_VECTOR
- PERF_PAPC_PASX_SE1_FIRST_VECTOR
- PERF_PAPC_PASX_SE1_REQ
- PERF_PAPC_PASX_SE1_SECOND_VECTOR
- PERF_PAPC_PASX_SECOND_DEAD
- PERF_PAPC_PASX_SECOND_VECTOR
- PERF_PAPC_PASX_VTX_KILL_DISCARD
- PERF_PAPC_PASX_VTX_NAN_DISCARD
- PERF_PAPC_PA_INPUT_END_OF_PACKET
- PERF_PAPC_PA_INPUT_EVENT_FLAG
- PERF_PAPC_PA_INPUT_EXTENDED_EVENT
- PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT
- PERF_PAPC_PA_INPUT_NULL_PRIM
- PERF_PAPC_PA_INPUT_PRIM
- PERF_PAPC_PA_REG_SCLK_VLD
- PERF_PAPC_SU_BACK_FACE_CULL_PRIM
- PERF_PAPC_SU_BUSY
- PERF_PAPC_SU_CULLED_PRIM
- PERF_PAPC_SU_DYN_SCLK_VLD
- PERF_PAPC_SU_FRONT_FACE_CULL_PRIM
- PERF_PAPC_SU_IDLE
- PERF_PAPC_SU_INPUT_CLIP_PRIM
- PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL
- PERF_PAPC_SU_INPUT_NULL_PRIM
- PERF_PAPC_SU_INPUT_PRIM
- PERF_PAPC_SU_INPUT_PRIM_DUAL
- PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL
- PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL
- PERF_PAPC_SU_OUTPUT_CLIP_PRIM
- PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL
- PERF_PAPC_SU_OUTPUT_END_OF_PACKET
- PERF_PAPC_SU_OUTPUT_EOPG
- PERF_PAPC_SU_OUTPUT_EVENT_FLAG
- PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT
- PERF_PAPC_SU_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_OUTPUT_POLYMODE_BACK
- PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL
- PERF_PAPC_SU_OUTPUT_POLYMODE_FACE
- PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT
- PERF_PAPC_SU_OUTPUT_PRIM
- PERF_PAPC_SU_OUTPUT_PRIM_DUAL
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT
- PERF_PAPC_SU_POLYMODE_BACK_CULL
- PERF_PAPC_SU_POLYMODE_FACE_CULL
- PERF_PAPC_SU_POLYMODE_FRONT_CULL
- PERF_PAPC_SU_POLYMODE_INVALID_FILL
- PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_SE01_OUTPUT_PRIM
- PERF_PAPC_SU_SE01_PRIM_FILTER_CULL
- PERF_PAPC_SU_SE01_STALLED_SC
- PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET
- PERF_PAPC_SU_SE0_OUTPUT_EOPG
- PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT
- PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_SE0_OUTPUT_PRIM
- PERF_PAPC_SU_SE0_PRIM_FILTER_CULL
- PERF_PAPC_SU_SE0_STALLED_SC
- PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET
- PERF_PAPC_SU_SE1_OUTPUT_EOPG
- PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT
- PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_SE1_OUTPUT_PRIM
- PERF_PAPC_SU_SE1_PRIM_FILTER_CULL
- PERF_PAPC_SU_SE1_STALLED_SC
- PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET
- PERF_PAPC_SU_SE2_OUTPUT_EOPG
- PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_SE2_OUTPUT_PRIM
- PERF_PAPC_SU_SE2_PRIM_FILTER_CULL
- PERF_PAPC_SU_SE2_STALLED_SC
- PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET
- PERF_PAPC_SU_SE3_OUTPUT_EOPG
- PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM
- PERF_PAPC_SU_SE3_OUTPUT_PRIM
- PERF_PAPC_SU_SE3_PRIM_FILTER_CULL
- PERF_PAPC_SU_SE3_STALLED_SC
- PERF_PAPC_SU_STALLED_SC
- PERF_PAPC_SU_STARVED_CLIP
- PERF_PAPC_SU_ZERO_AREA_CULL_PRIM
- PERF_PAWD_DEALLOC_FIFO_IS_FULL
- PERF_PAWD_DEALLOC_WAITING_TO_BE_READ
- PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL
- PERF_PA_FETCH_TO_SXIF_FIFO_FULL
- PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL
- PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND
- PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND
- PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED
- PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND
- PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND
- PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED
- PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND
- PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND
- PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED
- PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND
- PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND
- PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED
- PERF_PA_VERTEX_FIFO_FULL
- PERF_PC_2D_DRAWCALLS
- PERF_PC_3D_DRAWCALLS
- PERF_PC_BUSY_CYCLES
- PERF_PC_DEAD_PRIM
- PERF_PC_DS_INVOCATIONS
- PERF_PC_DS_PRIMITIVES
- PERF_PC_GS_INVOCATIONS
- PERF_PC_GS_PRIMITIVES
- PERF_PC_HS_INVOCATIONS
- PERF_PC_IA_PRIMITIVES
- PERF_PC_IA_VERTICES
- PERF_PC_INSTANCES
- PERF_PC_LIVE_PRIM
- PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS
- PERF_PC_PASS1_TF_STALL_CYCLES
- PERF_PC_STALL_CYCLES_TESS
- PERF_PC_STALL_CYCLES_TSE
- PERF_PC_STALL_CYCLES_TSE_ONLY
- PERF_PC_STALL_CYCLES_UCHE
- PERF_PC_STALL_CYCLES_VFD
- PERF_PC_STALL_CYCLES_VPC
- PERF_PC_STALL_CYCLES_VPC_ONLY
- PERF_PC_STARVE_CYCLES_DI
- PERF_PC_STARVE_CYCLES_FOR_INDEX
- PERF_PC_STARVE_CYCLES_FOR_POSITION
- PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR
- PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM
- PERF_PC_TESS_FACTOR_TRANS
- PERF_PC_TESS_PC_UV_PATCHES
- PERF_PC_TESS_PC_UV_TRANS
- PERF_PC_TSE_TRANSACTION
- PERF_PC_TSE_VERTEX
- PERF_PC_VERTEX_HITS
- PERF_PC_VIS_STREAMS_LOADED
- PERF_PC_VPC_POS_DATA_TRANSACTION
- PERF_PC_VPC_PRIMITIVES
- PERF_PC_VS_INVOCATIONS
- PERF_PC_WORKING_CYCLES
- PERF_PEBS_MEMINFO_TYPE
- PERF_PIPE_HDR_VER0
- PERF_PMU_CAP_AUX_NO_SG
- PERF_PMU_CAP_AUX_OUTPUT
- PERF_PMU_CAP_EXCLUSIVE
- PERF_PMU_CAP_EXTENDED_REGS
- PERF_PMU_CAP_HETEROGENEOUS_CPUS
- PERF_PMU_CAP_ITRACE
- PERF_PMU_CAP_NO_EXCLUDE
- PERF_PMU_CAP_NO_INTERRUPT
- PERF_PMU_CAP_NO_NMI
- PERF_PMU_FORMAT_BITS
- PERF_PMU_FORMAT_VALUE_CONFIG
- PERF_PMU_FORMAT_VALUE_CONFIG1
- PERF_PMU_FORMAT_VALUE_CONFIG2
- PERF_PMU_TXN_ADD
- PERF_PMU_TXN_READ
- PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE
- PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE
- PERF_POS_REQ_QUALIFIED_BUSY
- PERF_POS_REQ_QUALIFIED_STARVED
- PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM
- PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM
- PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM
- PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM
- PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO
- PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO
- PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO
- PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO
- PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO
- PERF_POS_REQ_STALLED_BY_NO_TOKENS
- PERF_POS_REQ_STALLED_BY_UTCL1
- PERF_POS_REQ_STARVED_BY_NO_PRIM
- PERF_POS_RET_1_CACHELINE_POSITION_USED
- PERF_POS_RET_2_CACHELINE_POSITION_USED
- PERF_POS_RET_3_CACHELINE_POSITION_USED
- PERF_POS_RET_4_CACHELINE_POSITION_USED
- PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE
- PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO
- PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO
- PERF_POS_RET_QUALIFIED_BUSY
- PERF_POS_RET_QUALIFIED_STARVED
- PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE
- PERF_PRINT_BINARY_H
- PERF_PROBE_CONFIG_IS_RETPROBE
- PERF_RAPL_MAX
- PERF_RAPL_PKG
- PERF_RAPL_PP0
- PERF_RAPL_PP1
- PERF_RAPL_PSYS
- PERF_RAPL_RAM
- PERF_RAS_8X4_TILES
- PERF_RAS_BLOCKS
- PERF_RAS_BUSY_CYCLES
- PERF_RAS_FULLY_COVERED_8X4_TILES
- PERF_RAS_FULLY_COVERED_SUPER_TILES
- PERF_RAS_LRZ_INTF_WORKING_CYCLES
- PERF_RAS_MASKGEN_ACTIVE
- PERF_RAS_PRIM_KILLED_INVISILBE
- PERF_RAS_STALL_CYCLES_LRZ
- PERF_RAS_STARVE_CYCLES_TSE
- PERF_RAS_SUPERTILE_ACTIVE_CYCLES
- PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES
- PERF_RAS_SUPER_TILES
- PERF_RBBM_ALWAYS_COUNT
- PERF_RBBM_ALWAYS_ON
- PERF_RBBM_COM_BUSY
- PERF_RBBM_DCOM_BUSY
- PERF_RBBM_HLSQ_BUSY
- PERF_RBBM_PC_DCALL_BUSY
- PERF_RBBM_PC_VSD_BUSY
- PERF_RBBM_RAS_BUSY
- PERF_RBBM_STATUS_MASKED
- PERF_RBBM_TESS_BUSY
- PERF_RBBM_TSE_BUSY
- PERF_RBBM_UCHE_BUSY
- PERF_RBBM_VBIF_BUSY
- PERF_RBBM_VSC_BUSY
- PERF_RB_2D_ALIVE_CYCLES
- PERF_RB_2D_INPUT_TRANS
- PERF_RB_2D_OUTPUT_RB_DST_TRANS
- PERF_RB_2D_OUTPUT_RB_SRC_TRANS
- PERF_RB_2D_STALL_CYCLES_A2D
- PERF_RB_2D_STARVE_CYCLES_DST
- PERF_RB_2D_STARVE_CYCLES_SP
- PERF_RB_2D_STARVE_CYCLES_SRC
- PERF_RB_2D_VALID_PIXELS
- PERF_RB_3D_PIXELS
- PERF_RB_BLENDED_FP16_COMPONENTS
- PERF_RB_BLENDED_FP32_COMPONENTS
- PERF_RB_BLENDED_FXP_COMPONENTS
- PERF_RB_BLENDER_WORKING_CYCLES
- PERF_RB_BUSY_CYCLES
- PERF_RB_COLOR_PIX_TILES
- PERF_RB_CPROC_WORKING_CYCLES
- PERF_RB_C_READ
- PERF_RB_C_WRITE
- PERF_RB_EARLY_Z_ARB3_GRANT
- PERF_RB_EARLY_Z_SKIP_GRANT
- PERF_RB_HLSQ_ACTIVE
- PERF_RB_LATE_Z_ARB3_GRANT
- PERF_RB_PS_INVOCATIONS
- PERF_RB_SAMPLER_WORKING_CYCLES
- PERF_RB_STALL_CYCLES_CCU
- PERF_RB_STALL_CYCLES_CCU_COLOR_READ
- PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE
- PERF_RB_STALL_CYCLES_CCU_DEPTH_READ
- PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE
- PERF_RB_STALL_CYCLES_FIFO0_FULL
- PERF_RB_STALL_CYCLES_FIFO1_FULL
- PERF_RB_STALL_CYCLES_FIFO2_FULL
- PERF_RB_STALL_CYCLES_HLSQ
- PERF_RB_STALL_CYCLES_VPC
- PERF_RB_STARVE_CYCLES_BARY_PLANE
- PERF_RB_STARVE_CYCLES_CCU
- PERF_RB_STARVE_CYCLES_LRZ_TILE
- PERF_RB_STARVE_CYCLES_SP
- PERF_RB_STARVE_CYCLES_Z_PLANE
- PERF_RB_S_FAIL
- PERF_RB_TOTAL_PASS
- PERF_RB_ZPROC_WORKING_CYCLES
- PERF_RB_Z_FAIL
- PERF_RB_Z_PASS
- PERF_RB_Z_READ
- PERF_RB_Z_WORKLOAD
- PERF_RB_Z_WRITE
- PERF_RD512_HI
- PERF_RD512_LO
- PERF_RECORD_AUX
- PERF_RECORD_AUXTRACE
- PERF_RECORD_AUXTRACE_ERROR
- PERF_RECORD_AUXTRACE_INFO
- PERF_RECORD_BPF_EVENT
- PERF_RECORD_COMM
- PERF_RECORD_COMPRESSED
- PERF_RECORD_CPU_MAP
- PERF_RECORD_EVENT_UPDATE
- PERF_RECORD_EXIT
- PERF_RECORD_FINISHED_ROUND
- PERF_RECORD_FORK
- PERF_RECORD_HEADER_ATTR
- PERF_RECORD_HEADER_BUILD_ID
- PERF_RECORD_HEADER_EVENT_TYPE
- PERF_RECORD_HEADER_FEATURE
- PERF_RECORD_HEADER_MAX
- PERF_RECORD_HEADER_TRACING_DATA
- PERF_RECORD_ID_INDEX
- PERF_RECORD_ITRACE_START
- PERF_RECORD_KSYMBOL
- PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER
- PERF_RECORD_KSYMBOL_TYPE_BPF
- PERF_RECORD_KSYMBOL_TYPE_MAX
- PERF_RECORD_KSYMBOL_TYPE_UNKNOWN
- PERF_RECORD_LOST
- PERF_RECORD_LOST_SAMPLES
- PERF_RECORD_MAX
- PERF_RECORD_MISC_COMM_EXEC
- PERF_RECORD_MISC_CPUMODE_MASK
- PERF_RECORD_MISC_CPUMODE_UNKNOWN
- PERF_RECORD_MISC_EXACT_IP
- PERF_RECORD_MISC_EXT_RESERVED
- PERF_RECORD_MISC_FORK_EXEC
- PERF_RECORD_MISC_GUEST_KERNEL
- PERF_RECORD_MISC_GUEST_USER
- PERF_RECORD_MISC_HYPERVISOR
- PERF_RECORD_MISC_KERNEL
- PERF_RECORD_MISC_MMAP_DATA
- PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT
- PERF_RECORD_MISC_SWITCH_OUT
- PERF_RECORD_MISC_SWITCH_OUT_PREEMPT
- PERF_RECORD_MISC_USER
- PERF_RECORD_MMAP
- PERF_RECORD_MMAP2
- PERF_RECORD_NAMESPACES
- PERF_RECORD_READ
- PERF_RECORD_SAMPLE
- PERF_RECORD_STAT
- PERF_RECORD_STAT_CONFIG
- PERF_RECORD_STAT_ROUND
- PERF_RECORD_SWITCH
- PERF_RECORD_SWITCH_CPU_WIDE
- PERF_RECORD_THREAD_MAP
- PERF_RECORD_THROTTLE
- PERF_RECORD_TIME_CONV
- PERF_RECORD_UNTHROTTLE
- PERF_RECORD_USER_TYPE_START
- PERF_REDUC_TOLERANCE
- PERF_REGS_MASK
- PERF_REGS_MAX
- PERF_REG_ARM64_LR
- PERF_REG_ARM64_MAX
- PERF_REG_ARM64_PC
- PERF_REG_ARM64_SP
- PERF_REG_ARM64_X0
- PERF_REG_ARM64_X1
- PERF_REG_ARM64_X10
- PERF_REG_ARM64_X11
- PERF_REG_ARM64_X12
- PERF_REG_ARM64_X13
- PERF_REG_ARM64_X14
- PERF_REG_ARM64_X15
- PERF_REG_ARM64_X16
- PERF_REG_ARM64_X17
- PERF_REG_ARM64_X18
- PERF_REG_ARM64_X19
- PERF_REG_ARM64_X2
- PERF_REG_ARM64_X20
- PERF_REG_ARM64_X21
- PERF_REG_ARM64_X22
- PERF_REG_ARM64_X23
- PERF_REG_ARM64_X24
- PERF_REG_ARM64_X25
- PERF_REG_ARM64_X26
- PERF_REG_ARM64_X27
- PERF_REG_ARM64_X28
- PERF_REG_ARM64_X29
- PERF_REG_ARM64_X3
- PERF_REG_ARM64_X4
- PERF_REG_ARM64_X5
- PERF_REG_ARM64_X6
- PERF_REG_ARM64_X7
- PERF_REG_ARM64_X8
- PERF_REG_ARM64_X9
- PERF_REG_ARM_FP
- PERF_REG_ARM_IP
- PERF_REG_ARM_LR
- PERF_REG_ARM_MAX
- PERF_REG_ARM_PC
- PERF_REG_ARM_R0
- PERF_REG_ARM_R1
- PERF_REG_ARM_R10
- PERF_REG_ARM_R2
- PERF_REG_ARM_R3
- PERF_REG_ARM_R4
- PERF_REG_ARM_R5
- PERF_REG_ARM_R6
- PERF_REG_ARM_R7
- PERF_REG_ARM_R8
- PERF_REG_ARM_R9
- PERF_REG_ARM_SP
- PERF_REG_CSKY_A0
- PERF_REG_CSKY_A1
- PERF_REG_CSKY_A2
- PERF_REG_CSKY_A3
- PERF_REG_CSKY_DCSR
- PERF_REG_CSKY_EXREGS0
- PERF_REG_CSKY_EXREGS1
- PERF_REG_CSKY_EXREGS10
- PERF_REG_CSKY_EXREGS11
- PERF_REG_CSKY_EXREGS12
- PERF_REG_CSKY_EXREGS13
- PERF_REG_CSKY_EXREGS14
- PERF_REG_CSKY_EXREGS2
- PERF_REG_CSKY_EXREGS3
- PERF_REG_CSKY_EXREGS4
- PERF_REG_CSKY_EXREGS5
- PERF_REG_CSKY_EXREGS6
- PERF_REG_CSKY_EXREGS7
- PERF_REG_CSKY_EXREGS8
- PERF_REG_CSKY_EXREGS9
- PERF_REG_CSKY_HI
- PERF_REG_CSKY_LO
- PERF_REG_CSKY_LR
- PERF_REG_CSKY_MAX
- PERF_REG_CSKY_ORIG_A0
- PERF_REG_CSKY_PC
- PERF_REG_CSKY_REGS0
- PERF_REG_CSKY_REGS1
- PERF_REG_CSKY_REGS2
- PERF_REG_CSKY_REGS3
- PERF_REG_CSKY_REGS4
- PERF_REG_CSKY_REGS5
- PERF_REG_CSKY_REGS6
- PERF_REG_CSKY_REGS7
- PERF_REG_CSKY_REGS8
- PERF_REG_CSKY_REGS9
- PERF_REG_CSKY_SP
- PERF_REG_CSKY_SR
- PERF_REG_CSKY_TLS
- PERF_REG_EXTENDED_MASK
- PERF_REG_IP
- PERF_REG_POWERPC_CCR
- PERF_REG_POWERPC_CTR
- PERF_REG_POWERPC_DAR
- PERF_REG_POWERPC_DSISR
- PERF_REG_POWERPC_LINK
- PERF_REG_POWERPC_MAX
- PERF_REG_POWERPC_MMCRA
- PERF_REG_POWERPC_MSR
- PERF_REG_POWERPC_NIP
- PERF_REG_POWERPC_ORIG_R3
- PERF_REG_POWERPC_R0
- PERF_REG_POWERPC_R1
- PERF_REG_POWERPC_R10
- PERF_REG_POWERPC_R11
- PERF_REG_POWERPC_R12
- PERF_REG_POWERPC_R13
- PERF_REG_POWERPC_R14
- PERF_REG_POWERPC_R15
- PERF_REG_POWERPC_R16
- PERF_REG_POWERPC_R17
- PERF_REG_POWERPC_R18
- PERF_REG_POWERPC_R19
- PERF_REG_POWERPC_R2
- PERF_REG_POWERPC_R20
- PERF_REG_POWERPC_R21
- PERF_REG_POWERPC_R22
- PERF_REG_POWERPC_R23
- PERF_REG_POWERPC_R24
- PERF_REG_POWERPC_R25
- PERF_REG_POWERPC_R26
- PERF_REG_POWERPC_R27
- PERF_REG_POWERPC_R28
- PERF_REG_POWERPC_R29
- PERF_REG_POWERPC_R3
- PERF_REG_POWERPC_R30
- PERF_REG_POWERPC_R31
- PERF_REG_POWERPC_R4
- PERF_REG_POWERPC_R5
- PERF_REG_POWERPC_R6
- PERF_REG_POWERPC_R7
- PERF_REG_POWERPC_R8
- PERF_REG_POWERPC_R9
- PERF_REG_POWERPC_SIER
- PERF_REG_POWERPC_SOFTE
- PERF_REG_POWERPC_TRAP
- PERF_REG_POWERPC_XER
- PERF_REG_RISCV_A0
- PERF_REG_RISCV_A1
- PERF_REG_RISCV_A2
- PERF_REG_RISCV_A3
- PERF_REG_RISCV_A4
- PERF_REG_RISCV_A5
- PERF_REG_RISCV_A6
- PERF_REG_RISCV_A7
- PERF_REG_RISCV_GP
- PERF_REG_RISCV_MAX
- PERF_REG_RISCV_PC
- PERF_REG_RISCV_RA
- PERF_REG_RISCV_S0
- PERF_REG_RISCV_S1
- PERF_REG_RISCV_S10
- PERF_REG_RISCV_S11
- PERF_REG_RISCV_S2
- PERF_REG_RISCV_S3
- PERF_REG_RISCV_S4
- PERF_REG_RISCV_S5
- PERF_REG_RISCV_S6
- PERF_REG_RISCV_S7
- PERF_REG_RISCV_S8
- PERF_REG_RISCV_S9
- PERF_REG_RISCV_SP
- PERF_REG_RISCV_T0
- PERF_REG_RISCV_T1
- PERF_REG_RISCV_T2
- PERF_REG_RISCV_T3
- PERF_REG_RISCV_T4
- PERF_REG_RISCV_T5
- PERF_REG_RISCV_T6
- PERF_REG_RISCV_TP
- PERF_REG_S390_FP0
- PERF_REG_S390_FP1
- PERF_REG_S390_FP10
- PERF_REG_S390_FP11
- PERF_REG_S390_FP12
- PERF_REG_S390_FP13
- PERF_REG_S390_FP14
- PERF_REG_S390_FP15
- PERF_REG_S390_FP2
- PERF_REG_S390_FP3
- PERF_REG_S390_FP4
- PERF_REG_S390_FP5
- PERF_REG_S390_FP6
- PERF_REG_S390_FP7
- PERF_REG_S390_FP8
- PERF_REG_S390_FP9
- PERF_REG_S390_MASK
- PERF_REG_S390_MAX
- PERF_REG_S390_PC
- PERF_REG_S390_R0
- PERF_REG_S390_R1
- PERF_REG_S390_R10
- PERF_REG_S390_R11
- PERF_REG_S390_R12
- PERF_REG_S390_R13
- PERF_REG_S390_R14
- PERF_REG_S390_R15
- PERF_REG_S390_R2
- PERF_REG_S390_R3
- PERF_REG_S390_R4
- PERF_REG_S390_R5
- PERF_REG_S390_R6
- PERF_REG_S390_R7
- PERF_REG_S390_R8
- PERF_REG_S390_R9
- PERF_REG_SP
- PERF_REG_X86_32_MAX
- PERF_REG_X86_64_MAX
- PERF_REG_X86_AX
- PERF_REG_X86_BP
- PERF_REG_X86_BX
- PERF_REG_X86_CS
- PERF_REG_X86_CX
- PERF_REG_X86_DI
- PERF_REG_X86_DS
- PERF_REG_X86_DX
- PERF_REG_X86_ES
- PERF_REG_X86_FLAGS
- PERF_REG_X86_FS
- PERF_REG_X86_GS
- PERF_REG_X86_IP
- PERF_REG_X86_MAX
- PERF_REG_X86_R10
- PERF_REG_X86_R11
- PERF_REG_X86_R12
- PERF_REG_X86_R13
- PERF_REG_X86_R14
- PERF_REG_X86_R15
- PERF_REG_X86_R8
- PERF_REG_X86_R9
- PERF_REG_X86_RESERVED
- PERF_REG_X86_SI
- PERF_REG_X86_SP
- PERF_REG_X86_SS
- PERF_REG_X86_XMM0
- PERF_REG_X86_XMM1
- PERF_REG_X86_XMM10
- PERF_REG_X86_XMM11
- PERF_REG_X86_XMM12
- PERF_REG_X86_XMM13
- PERF_REG_X86_XMM14
- PERF_REG_X86_XMM15
- PERF_REG_X86_XMM2
- PERF_REG_X86_XMM3
- PERF_REG_X86_XMM4
- PERF_REG_X86_XMM5
- PERF_REG_X86_XMM6
- PERF_REG_X86_XMM7
- PERF_REG_X86_XMM8
- PERF_REG_X86_XMM9
- PERF_REG_X86_XMM_MAX
- PERF_REQ_A15
- PERF_REQ_A7
- PERF_REV_REG
- PERF_SAMPLE_ADDR
- PERF_SAMPLE_BRANCH_ABORT_TX
- PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT
- PERF_SAMPLE_BRANCH_ANY
- PERF_SAMPLE_BRANCH_ANY_CALL
- PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
- PERF_SAMPLE_BRANCH_ANY_RETURN
- PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
- PERF_SAMPLE_BRANCH_ANY_SHIFT
- PERF_SAMPLE_BRANCH_CALL
- PERF_SAMPLE_BRANCH_CALL_SHIFT
- PERF_SAMPLE_BRANCH_CALL_STACK
- PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
- PERF_SAMPLE_BRANCH_COND
- PERF_SAMPLE_BRANCH_COND_SHIFT
- PERF_SAMPLE_BRANCH_HV
- PERF_SAMPLE_BRANCH_HV_SHIFT
- PERF_SAMPLE_BRANCH_IND_CALL
- PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
- PERF_SAMPLE_BRANCH_IND_JUMP
- PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
- PERF_SAMPLE_BRANCH_IN_TX
- PERF_SAMPLE_BRANCH_IN_TX_SHIFT
- PERF_SAMPLE_BRANCH_KERNEL
- PERF_SAMPLE_BRANCH_KERNEL_SHIFT
- PERF_SAMPLE_BRANCH_MAX
- PERF_SAMPLE_BRANCH_MAX_SHIFT
- PERF_SAMPLE_BRANCH_NO_CYCLES
- PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT
- PERF_SAMPLE_BRANCH_NO_FLAGS
- PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT
- PERF_SAMPLE_BRANCH_NO_TX
- PERF_SAMPLE_BRANCH_NO_TX_SHIFT
- PERF_SAMPLE_BRANCH_PERM_PLM
- PERF_SAMPLE_BRANCH_PLM_ALL
- PERF_SAMPLE_BRANCH_STACK
- PERF_SAMPLE_BRANCH_TYPE_SAVE
- PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT
- PERF_SAMPLE_BRANCH_USER
- PERF_SAMPLE_BRANCH_USER_SHIFT
- PERF_SAMPLE_CALLCHAIN
- PERF_SAMPLE_CPU
- PERF_SAMPLE_DATA_SRC
- PERF_SAMPLE_ID
- PERF_SAMPLE_IDENTIFIER
- PERF_SAMPLE_IP
- PERF_SAMPLE_MASK
- PERF_SAMPLE_MAX
- PERF_SAMPLE_MAX_SIZE
- PERF_SAMPLE_PERIOD
- PERF_SAMPLE_PHYS_ADDR
- PERF_SAMPLE_RAW
- PERF_SAMPLE_READ
- PERF_SAMPLE_REGS_ABI
- PERF_SAMPLE_REGS_ABI_32
- PERF_SAMPLE_REGS_ABI_64
- PERF_SAMPLE_REGS_ABI_NONE
- PERF_SAMPLE_REGS_INTR
- PERF_SAMPLE_REGS_USER
- PERF_SAMPLE_STACK_USER
- PERF_SAMPLE_STREAM_ID
- PERF_SAMPLE_TID
- PERF_SAMPLE_TIME
- PERF_SAMPLE_TRANSACTION
- PERF_SAMPLE_WEIGHT
- PERF_SC0_QUALIFIED_SEND_BUSY_EVENT
- PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT
- PERF_SC1_QUALIFIED_SEND_BUSY_EVENT
- PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT
- PERF_SC2_QUALIFIED_SEND_BUSY_EVENT
- PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT
- PERF_SC3_QUALIFIED_SEND_BUSY_EVENT
- PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT
- PERF_SHOOTDOWN_WAIT_ALL_CLEAN
- PERF_SHOOTDOWN_WAIT_DEASSERT
- PERF_SHOOTDOWN_WAIT_ON_UTCL1
- PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX
- PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION
- PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND
- PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_
- PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_
- PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_
- PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_
- PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD
- PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD
- PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD
- PERF_SIDEBAND_FIFO_VMID_FIFO_FULL
- PERF_SIDEBAND_INVALID_REFETCH
- PERF_SIDEBAND_POP_BIT_FIFO_FULL
- PERF_SIDEBAND_QUALIFIED_BUSY
- PERF_SIDEBAND_QUALIFIED_STARVED
- PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY
- PERF_SIDEBAND_WAITING_ON_RETURNED_DATA
- PERF_SIDEBAND_WAITING_ON_UTCL1
- PERF_SLP_REG
- PERF_SMALL_PRIM_CULL_PRIM_1X1
- PERF_SMALL_PRIM_CULL_PRIM_1X2
- PERF_SMALL_PRIM_CULL_PRIM_1X3
- PERF_SMALL_PRIM_CULL_PRIM_1XN
- PERF_SMALL_PRIM_CULL_PRIM_2X1
- PERF_SMALL_PRIM_CULL_PRIM_2X2
- PERF_SMALL_PRIM_CULL_PRIM_2X3
- PERF_SMALL_PRIM_CULL_PRIM_2XN
- PERF_SMALL_PRIM_CULL_PRIM_3X1
- PERF_SMALL_PRIM_CULL_PRIM_3X2
- PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT
- PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT
- PERF_SMALL_PRIM_CULL_PRIM_NX1
- PERF_SMALL_PRIM_CULL_PRIM_NX2
- PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT
- PERF_SOFTRESET_6328_REG
- PERF_SOFTRESET_6358_REG
- PERF_SOFTRESET_6362_REG
- PERF_SOFTRESET_6368_REG
- PERF_SOFTRESET_REG
- PERF_SPAD_CMD
- PERF_SPAD_CNT
- PERF_SPAD_HDATA
- PERF_SPAD_LDATA
- PERF_SPAD_NOTIFY
- PERF_SP_ADDR_LOCK_COUNT
- PERF_SP_ALU_WORKING_CYCLES
- PERF_SP_ANY_EU_WORKING
- PERF_SP_ANY_EU_WORKING_CS_STAGE
- PERF_SP_ANY_EU_WORKING_FS_STAGE
- PERF_SP_ANY_EU_WORKING_VS_STAGE
- PERF_SP_BUSY_CYCLES
- PERF_SP_CS_INSTRUCTIONS
- PERF_SP_DISPATCHER_WORKING_CYCLES
- PERF_SP_DS_INSTRUCTIONS
- PERF_SP_EFU_WORKING_CYCLES
- PERF_SP_EXECUTABLE_WAVES
- PERF_SP_EXPORT_RB_TRANS
- PERF_SP_EXPORT_VPC_TRANS
- PERF_SP_FLOW_CONTROL_WORKING_CYCLES
- PERF_SP_FS_INSTRUCTIONS
- PERF_SP_FS_STAGE_BARY_INSTRUCTIONS
- PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS
- PERF_SP_FS_STAGE_DURATION_CYCLES
- PERF_SP_FS_STAGE_EFU_INSTRUCTIONS
- PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS
- PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS
- PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS
- PERF_SP_FS_STAGE_TEX_INSTRUCTIONS
- PERF_SP_FS_STAGE_WAVE_CYCLES
- PERF_SP_FS_STAGE_WAVE_SAMPLES
- PERF_SP_GM_ATOMICS
- PERF_SP_GM_LOAD_INSTRUCTIONS
- PERF_SP_GM_LOAD_LATENCY_CYCLES
- PERF_SP_GM_LOAD_LATENCY_SAMPLES
- PERF_SP_GM_STORE_INSTRUCTIONS
- PERF_SP_GPR_READ
- PERF_SP_GPR_READ_CONFLICT
- PERF_SP_GPR_READ_PREFETCH
- PERF_SP_GPR_WRITE
- PERF_SP_GPR_WRITE_CONFLICT
- PERF_SP_GS_INSTRUCTIONS
- PERF_SP_HS_INSTRUCTIONS
- PERF_SP_ICL0_MISSES
- PERF_SP_ICL0_REQUESTS
- PERF_SP_ICL1_MISSES
- PERF_SP_ICL1_REQUESTS
- PERF_SP_LM_ATOMICS
- PERF_SP_LM_BANK_CONFLICTS
- PERF_SP_LM_CH0_REQUESTS
- PERF_SP_LM_CH1_REQUESTS
- PERF_SP_LM_LOAD_INSTRUCTIONS
- PERF_SP_LM_STORE_INSTRUCTIONS
- PERF_SP_LM_WORKING_CYCLES
- PERF_SP_LOAD_CONTROL_WORKING_CYCLES
- PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP
- PERF_SP_NON_EXECUTION_CYCLES
- PERF_SP_NON_EXECUTION_LS_CYCLES
- PERF_SP_PIXELS_KILLED
- PERF_SP_SCHEDULER_NON_WORKING
- PERF_SP_SEQUENCER_WORKING_CYCLES
- PERF_SP_STALL_CYCLES_RB
- PERF_SP_STALL_CYCLES_TP
- PERF_SP_STALL_CYCLES_UCHE
- PERF_SP_STALL_CYCLES_VPC
- PERF_SP_STARVE_CYCLES_HLSQ
- PERF_SP_TEX_CONTROL_WORKING_CYCLES
- PERF_SP_UCHE_READ_TRANS
- PERF_SP_UCHE_WRITE_TRANS
- PERF_SP_VS_INSTRUCTIONS
- PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS
- PERF_SP_VS_STAGE_DURATION_CYCLES
- PERF_SP_VS_STAGE_EFU_INSTRUCTIONS
- PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS
- PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS
- PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS
- PERF_SP_VS_STAGE_TEX_INSTRUCTIONS
- PERF_SP_VS_STAGE_WAVE_CYCLES
- PERF_SP_VS_STAGE_WAVE_SAMPLES
- PERF_SP_WAVE_CONTEXTS
- PERF_SP_WAVE_CONTEXT_CYCLES
- PERF_SP_WAVE_CTRL_CYCLES
- PERF_SP_WAVE_EMIT_CYCLES
- PERF_SP_WAVE_END_CYCLES
- PERF_SP_WAVE_FETCH_CYCLES
- PERF_SP_WAVE_IDLE_CYCLES
- PERF_SP_WAVE_JOIN_CYCLES
- PERF_SP_WAVE_LOAD_CYCLES
- PERF_SP_WAVE_LONG_SYNC_CYCLES
- PERF_SP_WAVE_NOP_CYCLES
- PERF_SP_WAVE_SHORT_SYNC_CYCLES
- PERF_SP_WAVE_WAIT_CYCLES
- PERF_SP_WORKING_EU
- PERF_SP_WORKING_EU_CS_STAGE
- PERF_SP_WORKING_EU_FS_STAGE
- PERF_SP_WORKING_EU_VS_STAGE
- PERF_SRCLINE_H
- PERF_STATUS_THROTTLE_TIME_MASK
- PERF_STAT_CONFIG_TERM__AGGR_MODE
- PERF_STAT_CONFIG_TERM__INTERVAL
- PERF_STAT_CONFIG_TERM__MAX
- PERF_STAT_CONFIG_TERM__SCALE
- PERF_STAT_EVSEL_ID__APERF
- PERF_STAT_EVSEL_ID__CYCLES_IN_TX
- PERF_STAT_EVSEL_ID__CYCLES_IN_TX_CP
- PERF_STAT_EVSEL_ID__ELISION_START
- PERF_STAT_EVSEL_ID__MAX
- PERF_STAT_EVSEL_ID__NONE
- PERF_STAT_EVSEL_ID__SMI_NUM
- PERF_STAT_EVSEL_ID__TOPDOWN_FETCH_BUBBLES
- PERF_STAT_EVSEL_ID__TOPDOWN_RECOVERY_BUBBLES
- PERF_STAT_EVSEL_ID__TOPDOWN_SLOTS_ISSUED
- PERF_STAT_EVSEL_ID__TOPDOWN_SLOTS_RETIRED
- PERF_STAT_EVSEL_ID__TOPDOWN_TOTAL_SLOTS
- PERF_STAT_EVSEL_ID__TRANSACTION_START
- PERF_STAT_ROUND_TYPE__FINAL
- PERF_STAT_ROUND_TYPE__INTERVAL
- PERF_STRING_H
- PERF_STS_DONE
- PERF_STS_LNKUP
- PERF_SUBSYS_FUNC
- PERF_SU_SMALL_PRIM_FILTER_CULL_CNT
- PERF_SYNTH_INTEL_CBR
- PERF_SYNTH_INTEL_EXSTOP
- PERF_SYNTH_INTEL_MWAIT
- PERF_SYNTH_INTEL_PTWRITE
- PERF_SYNTH_INTEL_PWRE
- PERF_SYNTH_INTEL_PWRX
- PERF_SYS_PLL_CTL_REG
- PERF_TCIF_BUSY
- PERF_TCIF_INDEX_RDREQ
- PERF_TCIF_POSITION_RDREQ
- PERF_TCIF_SIDEBAND_RDREQ
- PERF_TCIF_STALLING_CLIENT_NO_CREDITS
- PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE
- PERF_TC_INDEX_LATENCY_BIN0
- PERF_TC_INDEX_LATENCY_BIN1
- PERF_TC_INDEX_LATENCY_BIN10
- PERF_TC_INDEX_LATENCY_BIN11
- PERF_TC_INDEX_LATENCY_BIN12
- PERF_TC_INDEX_LATENCY_BIN13
- PERF_TC_INDEX_LATENCY_BIN14
- PERF_TC_INDEX_LATENCY_BIN15
- PERF_TC_INDEX_LATENCY_BIN2
- PERF_TC_INDEX_LATENCY_BIN3
- PERF_TC_INDEX_LATENCY_BIN4
- PERF_TC_INDEX_LATENCY_BIN5
- PERF_TC_INDEX_LATENCY_BIN6
- PERF_TC_INDEX_LATENCY_BIN7
- PERF_TC_INDEX_LATENCY_BIN8
- PERF_TC_INDEX_LATENCY_BIN9
- PERF_TC_POSITION_LATENCY_BIN0
- PERF_TC_POSITION_LATENCY_BIN1
- PERF_TC_POSITION_LATENCY_BIN10
- PERF_TC_POSITION_LATENCY_BIN11
- PERF_TC_POSITION_LATENCY_BIN12
- PERF_TC_POSITION_LATENCY_BIN13
- PERF_TC_POSITION_LATENCY_BIN14
- PERF_TC_POSITION_LATENCY_BIN15
- PERF_TC_POSITION_LATENCY_BIN2
- PERF_TC_POSITION_LATENCY_BIN3
- PERF_TC_POSITION_LATENCY_BIN4
- PERF_TC_POSITION_LATENCY_BIN5
- PERF_TC_POSITION_LATENCY_BIN6
- PERF_TC_POSITION_LATENCY_BIN7
- PERF_TC_POSITION_LATENCY_BIN8
- PERF_TC_POSITION_LATENCY_BIN9
- PERF_TC_STREAM0_DATA_AVAILABLE
- PERF_TC_STREAM1_DATA_AVAILABLE
- PERF_TC_STREAM2_DATA_AVAILABLE
- PERF_TESS_BUSY_CYCLES
- PERF_TESS_STALL_CYCLES_PC
- PERF_TESS_STARVE_CYCLES_PC
- PERF_TESS_WORKING_CYCLES
- PERF_TEST_BPF_PATH
- PERF_TEST_LLVM_H
- PERF_TIMER_HI
- PERF_TIMER_LO
- PERF_TOOL_DURATION_TIME
- PERF_TOOL_NONE
- PERF_TP_2D_FILTER_WORKLOAD_16BIT
- PERF_TP_2D_FILTER_WORKLOAD_32BIT
- PERF_TP_2D_OUTPUT_PIXELS
- PERF_TP_2D_OUTPUT_PIXELS_BILINEAR
- PERF_TP_2D_OUTPUT_PIXELS_POINT
- PERF_TP_BACKEND_WORKING_CYCLES
- PERF_TP_BINDLESS_STATE_CACHE_MISSES
- PERF_TP_BINDLESS_STATE_CACHE_REQUESTS
- PERF_TP_BUSY_CYCLES
- PERF_TP_DIVERGENT_QUADS_RECEIVED
- PERF_TP_FILTER_WORKLOAD_16BIT
- PERF_TP_FILTER_WORKLOAD_32BIT
- PERF_TP_FLAG_CACHE_MISSES
- PERF_TP_FLAG_CACHE_REQUESTS
- PERF_TP_FLAG_CACHE_REQUEST_LATENCY
- PERF_TP_FLAG_CACHE_REQUEST_SAMPLES
- PERF_TP_FLAG_CACHE_WORKING_CYCLES
- PERF_TP_FRONTEND_WORKING_CYCLES
- PERF_TP_L1_5_CACHE_WORKING_CYCLES
- PERF_TP_L1_5_L2_COMPRESS_MISS
- PERF_TP_L1_5_L2_COMPRESS_REQS
- PERF_TP_L1_5_L2_REQUESTS
- PERF_TP_L1_5_MISS_LATENCY_CYCLES
- PERF_TP_L1_5_MISS_LATENCY_TRANS
- PERF_TP_L1_BANK_CONFLICT
- PERF_TP_L1_CACHELINE_MISSES
- PERF_TP_L1_CACHELINE_REQUESTS
- PERF_TP_L1_DATA_WRITE_WORKING_CYCLES
- PERF_TP_L1_MISSES_ASTC_1TILE
- PERF_TP_L1_MISSES_ASTC_2TILE
- PERF_TP_L1_MISSES_ASTC_4TILE
- PERF_TP_L1_TAG_WORKING_CYCLES
- PERF_TP_LATENCY_CYCLES
- PERF_TP_LATENCY_TRANS
- PERF_TP_OUTPUT_PIXELS
- PERF_TP_OUTPUT_PIXELS_ANISO
- PERF_TP_OUTPUT_PIXELS_BILINEAR
- PERF_TP_OUTPUT_PIXELS_MIP
- PERF_TP_OUTPUT_PIXELS_POINT
- PERF_TP_OUTPUT_PIXELS_ZERO_LOD
- PERF_TP_PRE_L1_DECOM_WORKING_CYCLES
- PERF_TP_PRT_NON_RESIDENT_EVENTS
- PERF_TP_QUADS_1D
- PERF_TP_QUADS_2D
- PERF_TP_QUADS_3D
- PERF_TP_QUADS_ARRAY
- PERF_TP_QUADS_BUFFER
- PERF_TP_QUADS_CONSTANT_MULTIPLIED
- PERF_TP_QUADS_CUBE
- PERF_TP_QUADS_GRADIENT
- PERF_TP_QUADS_OFFSET
- PERF_TP_QUADS_RECEIVED
- PERF_TP_QUADS_SHADOW
- PERF_TP_SAMPLE_TYPE
- PERF_TP_SP_TP_TRANS
- PERF_TP_STALL_CYCLES_UCHE
- PERF_TP_STARVE_CYCLES_SP
- PERF_TP_STARVE_CYCLES_UCHE
- PERF_TP_STATE_CACHE_MISSES
- PERF_TP_STATE_CACHE_REQUESTS
- PERF_TP_TPA2TPC_TRANS
- PERF_TP_TP_SP_TRANS
- PERF_TRACE
- PERF_TRACEFS_ENVIRONMENT
- PERF_TRACE_CTX
- PERF_TSE_2D_ALIVE_CLCLES
- PERF_TSE_2D_ALIVE_CYCLES
- PERF_TSE_2D_INPUT_PRIM
- PERF_TSE_BUSY_CYCLES
- PERF_TSE_CINVOCATION
- PERF_TSE_CLIPPED_PRIM
- PERF_TSE_CLIPPING_CYCLES
- PERF_TSE_CLIP_PLANES
- PERF_TSE_CPRIMITIVES
- PERF_TSE_FACENESS_CULLED_PRIM
- PERF_TSE_INPUT_NULL_PRIM
- PERF_TSE_INPUT_PRIM
- PERF_TSE_OUTPUT_NULL_PRIM
- PERF_TSE_OUTPUT_VISIBLE_PRIM
- PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE
- PERF_TSE_STALL_CYCLES_LRZ_ZPLANE
- PERF_TSE_STALL_CYCLES_RAS
- PERF_TSE_STARVE_CYCLES_PC
- PERF_TSE_TRIVAL_REJ_PRIM
- PERF_TSE_ZERO_AREA_PRIM
- PERF_TSE_ZERO_PIXEL_PRIM
- PERF_TXN_ABORT_MASK
- PERF_TXN_ABORT_SHIFT
- PERF_TXN_ASYNC
- PERF_TXN_CAPACITY_READ
- PERF_TXN_CAPACITY_WRITE
- PERF_TXN_CONFLICT
- PERF_TXN_ELISION
- PERF_TXN_MAX
- PERF_TXN_RETRY
- PERF_TXN_SYNC
- PERF_TXN_TRANSACTION
- PERF_TYPE_AMDGPU_DF
- PERF_TYPE_AMDGPU_MAX
- PERF_TYPE_BREAKPOINT
- PERF_TYPE_HARDWARE
- PERF_TYPE_HW_CACHE
- PERF_TYPE_MAX
- PERF_TYPE_RAW
- PERF_TYPE_SOFTWARE
- PERF_TYPE_SYNTH
- PERF_TYPE_TRACEPOINT
- PERF_UCHE_BANK_REQ0
- PERF_UCHE_BANK_REQ1
- PERF_UCHE_BANK_REQ2
- PERF_UCHE_BANK_REQ3
- PERF_UCHE_BANK_REQ4
- PERF_UCHE_BANK_REQ5
- PERF_UCHE_BANK_REQ6
- PERF_UCHE_BANK_REQ7
- PERF_UCHE_BUSY_CYCLES
- PERF_UCHE_DCMP_LATENCY_CYCLES
- PERF_UCHE_DCMP_LATENCY_SAMPLES
- PERF_UCHE_EVICTS
- PERF_UCHE_FLAG_COUNT
- PERF_UCHE_GMEM_READ_BEATS
- PERF_UCHE_RAM_READ_REQ
- PERF_UCHE_RAM_WRITE_REQ
- PERF_UCHE_READ_REQUESTS_HLSQ
- PERF_UCHE_READ_REQUESTS_LRZ
- PERF_UCHE_READ_REQUESTS_PC
- PERF_UCHE_READ_REQUESTS_SP
- PERF_UCHE_READ_REQUESTS_TP
- PERF_UCHE_READ_REQUESTS_VFD
- PERF_UCHE_STALL_CYCLES_ARBITER
- PERF_UCHE_STALL_CYCLES_VBIF
- PERF_UCHE_TPH_EXT_FULL
- PERF_UCHE_TPH_REF_FULL
- PERF_UCHE_TPH_VICTIM_FULL
- PERF_UCHE_VBIF_LATENCY_CYCLES
- PERF_UCHE_VBIF_LATENCY_SAMPLES
- PERF_UCHE_VBIF_READ_BEATS_CH0
- PERF_UCHE_VBIF_READ_BEATS_CH1
- PERF_UCHE_VBIF_READ_BEATS_HLSQ
- PERF_UCHE_VBIF_READ_BEATS_LRZ
- PERF_UCHE_VBIF_READ_BEATS_PC
- PERF_UCHE_VBIF_READ_BEATS_SP
- PERF_UCHE_VBIF_READ_BEATS_TP
- PERF_UCHE_VBIF_READ_BEATS_VFD
- PERF_UCHE_VBIF_STALL_WRITE_DATA
- PERF_UCHE_WRITE_REQUESTS_LRZ
- PERF_UCHE_WRITE_REQUESTS_SP
- PERF_UCHE_WRITE_REQUESTS_VPC
- PERF_UCHE_WRITE_REQUESTS_VSC
- PERF_UNIT_H
- PERF_UPROBE_REF_CTR_OFFSET_BITS
- PERF_UPROBE_REF_CTR_OFFSET_SHIFT
- PERF_UTCL1_LFIFO_FULL
- PERF_UTCL1_PERMISSION_MISS_CLIENT0
- PERF_UTCL1_PERMISSION_MISS_CLIENT1
- PERF_UTCL1_PERMISSION_MISS_CLIENT2
- PERF_UTCL1_REQUEST_CLIENT0
- PERF_UTCL1_REQUEST_CLIENT1
- PERF_UTCL1_REQUEST_CLIENT2
- PERF_UTCL1_STALL_INFLIGHT_MAX
- PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0
- PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1
- PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2
- PERF_UTCL1_STALL_LRU_INFLIGHT
- PERF_UTCL1_STALL_MISSFIFO_FULL
- PERF_UTCL1_STALL_MULTI_MISS
- PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS
- PERF_UTCL1_TRANSLATION_HIT_CLIENT0
- PERF_UTCL1_TRANSLATION_HIT_CLIENT1
- PERF_UTCL1_TRANSLATION_HIT_CLIENT2
- PERF_UTCL1_TRANSLATION_MISS_CLIENT0
- PERF_UTCL1_TRANSLATION_MISS_CLIENT1
- PERF_UTCL1_TRANSLATION_MISS_CLIENT2
- PERF_UTCL1_UTCL2_INFLIGHT
- PERF_UTCL1_UTCL2_REQ
- PERF_UTCL1_UTCL2_RET
- PERF_UTC_INDEX_DRIVER_BUSY
- PERF_UTC_INDEX_DRIVER_STALLING_CLIENT
- PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1
- PERF_UTC_INDEX_RECEIVER_BUSY
- PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER
- PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1
- PERF_UTC_POSITION_DRIVER_BUSY
- PERF_UTC_POSITION_DRIVER_STALLING_CLIENT
- PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1
- PERF_UTC_POSITION_RECEIVER_BUSY
- PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER
- PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1
- PERF_UTC_SIDEBAND_DRIVER_BUSY
- PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT
- PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1
- PERF_UTC_SIDEBAND_RECEIVER_BUSY
- PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER
- PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1
- PERF_UTIL_CLANG_C_H
- PERF_UTIL_CLANG_H
- PERF_UTIL_PERF_HOOKS_H
- PERF_VERSION
- PERF_VFDP_STALL_CYCLES_VFD
- PERF_VFDP_STALL_CYCLES_VFD_INDEX
- PERF_VFDP_STALL_CYCLES_VFD_PROG
- PERF_VFDP_STARVE_CYCLES_PC
- PERF_VFDP_VS_STAGE_32_WAVES
- PERF_VFDP_VS_STAGE_WAVES
- PERF_VFD_1_BURST_REQ
- PERF_VFD_ATTR_INFO_FIFO_FULL
- PERF_VFD_BUSY_CYCLES
- PERF_VFD_DECODED_ATTRIBUTE_BYTES
- PERF_VFD_DECODER_PACKER_STALL
- PERF_VFD_INSTRUCTIONS
- PERF_VFD_LOWER_SHADER_FIBERS
- PERF_VFD_MODE_0_FIBERS
- PERF_VFD_MODE_1_FIBERS
- PERF_VFD_MODE_2_FIBERS
- PERF_VFD_MODE_3_FIBERS
- PERF_VFD_MODE_4_FIBERS
- PERF_VFD_NUM_ATTRIBUTES
- PERF_VFD_NUM_ATTR_MISS
- PERF_VFD_RBUFFER_FULL
- PERF_VFD_STALL_CYCLES_MISS_Q
- PERF_VFD_STALL_CYCLES_MISS_VB
- PERF_VFD_STALL_CYCLES_SP_ATTR
- PERF_VFD_STALL_CYCLES_SP_INFO
- PERF_VFD_STALL_CYCLES_UCHE
- PERF_VFD_STALL_CYCLES_VFDP_Q
- PERF_VFD_STALL_CYCLES_VFDP_VB
- PERF_VFD_STALL_CYCLES_VPC_ALLOC
- PERF_VFD_STARVE_CYCLES_UCHE
- PERF_VFD_TOTAL_VERTICES
- PERF_VFD_UPPER_SHADER_FIBERS
- PERF_VPC_BUSY_CYCLES
- PERF_VPC_GRANT_PHASES
- PERF_VPC_LM_FULL_WAIT_FOR_INTP_END
- PERF_VPC_LM_TRANSACTION
- PERF_VPC_LRZ_ASSIGN_PRIMITIVES
- PERF_VPC_NUM_ATTR_REQ_LM
- PERF_VPC_NUM_VPCRAM_READ_POS
- PERF_VPC_NUM_VPCRAM_READ_SO
- PERF_VPC_NUM_VPCRAM_WRITE
- PERF_VPC_PC_PRIMITIVES
- PERF_VPC_POS_EXPORT_STALL_CYCLES
- PERF_VPC_PS_BUSY_CYCLES
- PERF_VPC_PS_WORKING_CYCLES
- PERF_VPC_RB_VISIBLE_PRIMITIVES
- PERF_VPC_SP_COMPONENTS
- PERF_VPC_SP_LM_COMPONENTS
- PERF_VPC_SP_LM_DWORDS
- PERF_VPC_SP_LM_PRIMITIVES
- PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC
- PERF_VPC_STALL_CYCLES_PC
- PERF_VPC_STALL_CYCLES_SP_LM
- PERF_VPC_STALL_CYCLES_UCHE
- PERF_VPC_STALL_CYCLES_VFD_WACK
- PERF_VPC_STALL_CYCLES_VPCRAM_POS
- PERF_VPC_STARVE_CYCLES_LRZ
- PERF_VPC_STARVE_CYCLES_RB
- PERF_VPC_STARVE_CYCLES_SP
- PERF_VPC_STREAMOUT_COMPONENTS
- PERF_VPC_STREAMOUT_TRANSACTION
- PERF_VPC_VPCRAM_FULL_CYCLES
- PERF_VPC_VS_BUSY_CYCLES
- PERF_VPC_VS_WORKING_CYCLES
- PERF_VPC_WIT_FULL_CYCLES
- PERF_VPC_WORKING_CYCLES
- PERF_VSC_BUSY_CYCLES
- PERF_VSC_EOT_NUM
- PERF_VSC_INPUT_TILES
- PERF_VSC_STALL_CYCLES_UCHE
- PERF_VSC_WORKING_CYCLES
- PERF_WR512_HI
- PERF_WR512_LO
- PERF_WRITING_TO_SIDEBAND_MEMORY
- PERF_X86_EVENT_AUTO_RELOAD
- PERF_X86_EVENT_DYNAMIC
- PERF_X86_EVENT_EXCL
- PERF_X86_EVENT_EXCL_ACCT
- PERF_X86_EVENT_LARGE_PEBS
- PERF_X86_EVENT_PAIR
- PERF_X86_EVENT_PEBS_HSW_PREC
- PERF_X86_EVENT_PEBS_LDLAT
- PERF_X86_EVENT_PEBS_LD_HSW
- PERF_X86_EVENT_PEBS_NA_HSW
- PERF_X86_EVENT_PEBS_ST
- PERF_X86_EVENT_PEBS_ST_HSW
- PERF_X86_EVENT_PEBS_VIA_PT
- PERF_X86_EVENT_RDPMC_ALLOWED
- PERI9_CPU1_RESET
- PERIC0_NR_CLK
- PERIC1_NR_CLK
- PERIC_NR_CLK
- PERIF_BANK
- PERIOD
- PERIODIC_FLAGS_LINK_EVENT
- PERIODIC_ONLY
- PERIODIC_SCAN_COMPLETE_EVENT_ID
- PERIODIC_SCAN_REPORT_EVENT_ID
- PERIODIC_SIZE
- PERIODS
- PERIODS_MAX
- PERIODS_MIN
- PERIOD_ACTIVE_HIGH
- PERIOD_BYTES_MAX
- PERIOD_BYTES_MIN
- PERIOD_CDIV
- PERIOD_CDIV_MAX
- PERIOD_CFG_PERIODS_SHIFT
- PERIOD_COUNT_MAX
- PERIOD_COUNT_MIN
- PERIOD_COUNT_OFFSET
- PERIOD_INACTIVE_LOW
- PERIOD_MASK
- PERIOD_MAX
- PERIOD_MIN
- PERIOD_OFFSET
- PERIOD_PERIOD
- PERIOD_PERIOD_MAX
- PERIOD_SHIFT
- PERIP1_CLK_ENB
- PERIPHERAL
- PERIPHERALS0
- PERIPHERALS1
- PERIPHERAL_AT91RM9200
- PERIPHERAL_AT91SAM9X5
- PERIPHERAL_CTRL
- PERIPHERAL_ENABLE
- PERIPHERAL_ID_MAX
- PERIPHERAL_ID_MIN
- PERIPHERAL_MASK
- PERIPHERAL_MAX
- PERIPHERAL_MAX_SHIFT
- PERIPH_AFBC_DMA_EN
- PERIPH_ASSERT_OFFSET
- PERIPH_CLK_COUNTER_FAST
- PERIPH_CLK_COUNTER_FAST_DIV
- PERIPH_CLK_COUNTER_SLOW
- PERIPH_CLK_COUNTER_SLOW_DIV
- PERIPH_CLK_COUNTER_SLOW_PRE_DIV
- PERIPH_CLK_DDR
- PERIPH_CLK_FULL
- PERIPH_CLK_FULL_DD
- PERIPH_CLK_GATE_DIV
- PERIPH_CLK_I2C0
- PERIPH_CLK_I2C0_DIV
- PERIPH_CLK_I2C0_PRE_DIV
- PERIPH_CLK_I2C1
- PERIPH_CLK_I2C1_DIV
- PERIPH_CLK_I2C1_PRE_DIV
- PERIPH_CLK_I2C2
- PERIPH_CLK_I2C2_DIV
- PERIPH_CLK_I2C2_PRE_DIV
- PERIPH_CLK_I2C3
- PERIPH_CLK_I2C3_DIV
- PERIPH_CLK_I2C3_PRE_DIV
- PERIPH_CLK_IR
- PERIPH_CLK_IR_DIV
- PERIPH_CLK_IR_PRE_DIV
- PERIPH_CLK_MUX_DD
- PERIPH_CLK_NR_CLKS
- PERIPH_CLK_PDM
- PERIPH_CLK_PDM_DIV
- PERIPH_CLK_PDM_PRE_DIV
- PERIPH_CLK_PWM
- PERIPH_CLK_PWM_DIV
- PERIPH_CLK_PWM_PRE_DIV
- PERIPH_CLK_ROM
- PERIPH_CLK_ROM_DIV
- PERIPH_CLK_SYS
- PERIPH_CLK_SYS_BUS
- PERIPH_CLK_UART_DIV_ENB
- PERIPH_CLK_WD
- PERIPH_CLK_WD_DIV
- PERIPH_CLK_WD_PRE_DIV
- PERIPH_CONFIGURATION_ID
- PERIPH_DEASSERT_OFFSET
- PERIPH_DIV
- PERIPH_DOUBLEDIV
- PERIPH_GATE
- PERIPH_ID
- PERIPH_ID_VAL
- PERIPH_MAX_INDEX
- PERIPH_MAX_LINE_SIZE
- PERIPH_MUX
- PERIPH_NOC_CLK_SRC
- PERIPH_NON_PIPE_GRP_SHIFT
- PERIPH_NON_PIP_GRP_MASK
- PERIPH_NUM_RICH_LAYERS
- PERIPH_PHYS
- PERIPH_PM_CPU
- PERIPH_REV_MASK
- PERIPH_REV_R0P0
- PERIPH_REV_R1P0
- PERIPH_REV_R1P1
- PERIPH_REV_SHIFT
- PERIPH_RSDIST9_CARM_ATB
- PERIPH_RSDIST9_CARM_CORE
- PERIPH_RSDIST9_CARM_DAP
- PERIPH_RSDIST9_CARM_DBG
- PERIPH_RSDIST9_CARM_ETM
- PERIPH_RSDIST9_CARM_L2
- PERIPH_RSDIST9_CARM_LBUS
- PERIPH_RSDIST9_CARM_POR
- PERIPH_RSDIST9_CARM_SOCDBG
- PERIPH_RSTDIS0_MMC0
- PERIPH_RSTDIS0_MMC1
- PERIPH_RSTDIS0_MMC2
- PERIPH_RSTDIS0_NANDC
- PERIPH_RSTDIS0_POR_PICOPHY
- PERIPH_RSTDIS0_USBOTG
- PERIPH_RSTDIS0_USBOTG_32K
- PERIPH_RSTDIS0_USBOTG_BUS
- PERIPH_RSTDIS1_DIGACODEC
- PERIPH_RSTDIS1_HIFI
- PERIPH_RSTEN2_ABB
- PERIPH_RSTEN2_DMAC
- PERIPH_RSTEN2_HPM0
- PERIPH_RSTEN2_HPM1
- PERIPH_RSTEN2_HPM2
- PERIPH_RSTEN2_HPM3
- PERIPH_RSTEN2_IPF
- PERIPH_RSTEN2_SECENG
- PERIPH_RSTEN2_SOCP
- PERIPH_RSTEN3_BLPWM
- PERIPH_RSTEN3_CODEC_SSI
- PERIPH_RSTEN3_CSSYS
- PERIPH_RSTEN3_DAPB
- PERIPH_RSTEN3_HKADC
- PERIPH_RSTEN3_I2C0
- PERIPH_RSTEN3_I2C1
- PERIPH_RSTEN3_I2C2
- PERIPH_RSTEN3_I2C3
- PERIPH_RSTEN3_PMUSSI1
- PERIPH_RSTEN3_PWM
- PERIPH_RSTEN3_SSP
- PERIPH_RSTEN3_TSENSOR
- PERIPH_RSTEN3_UART1
- PERIPH_RSTEN3_UART2
- PERIPH_RSTEN3_UART3
- PERIPH_RSTEN3_UART4
- PERIPH_RSTEN8_DDRC
- PERIPH_RSTEN8_DDRC_APB
- PERIPH_RSTEN8_DDRPACK_APB
- PERIPH_RSTEN8_DDRT
- PERIPH_RSTEN8_HARQ
- PERIPH_RSTEN8_MS0
- PERIPH_RSTEN8_MS2
- PERIPH_RSTEN8_RS0
- PERIPH_RSTEN8_RS2
- PERIPH_RSTEN8_RS3
- PERIPH_RSTEN8_SRAM
- PERIPH_RSTEN8_X2SRAM_TZMA
- PERIPH_RSTEN8_XG2RAM0
- PERIPH_SIZE
- PERIPH_SPLIT_EN
- PERIPH_TBU_EN
- PERIPH_VIRT
- PERIP_CFG
- PERIP_CLK_CFG
- PERIP_GRP1_BASE
- PERIP_GRP2_BASE
- PERIP_PWM_PDM_CONTROL
- PERIP_PWM_PDM_CONTROL_CH_MASK
- PERIP_PWM_PDM_CONTROL_CH_SHIFT
- PERIP_TIMER_CONTROL
- PERIS_NR_CLK
- PERI_CLK_ABB
- PERI_CLK_ADC
- PERI_CLK_CHIPID
- PERI_CLK_EFUSE_WRITER
- PERI_CLK_HDMICEC
- PERI_CLK_HSIC0
- PERI_CLK_HSIC1
- PERI_CLK_HSIC2
- PERI_CLK_HSIC3
- PERI_CLK_I2C10
- PERI_CLK_I2C11
- PERI_CLK_I2C4
- PERI_CLK_I2C5
- PERI_CLK_I2C6
- PERI_CLK_I2C7
- PERI_CLK_I2C8
- PERI_CLK_I2C9
- PERI_CLK_I2CHDMI
- PERI_CLK_I2S
- PERI_CLK_MCT
- PERI_CLK_PCM
- PERI_CLK_PROVKEY0
- PERI_CLK_PROVKEY1
- PERI_CLK_PWM
- PERI_CLK_SECKEY
- PERI_CLK_SPDIF
- PERI_CLK_SPI0
- PERI_CLK_SPI1
- PERI_CLK_SPI2
- PERI_CLK_TMU0
- PERI_CLK_TMU1
- PERI_CLK_TMU2
- PERI_CLK_TMU3
- PERI_CLK_TMU4
- PERI_CLK_TOP_RTC
- PERI_CLK_TZPC0
- PERI_CLK_TZPC1
- PERI_CLK_TZPC10
- PERI_CLK_TZPC2
- PERI_CLK_TZPC3
- PERI_CLK_TZPC4
- PERI_CLK_TZPC5
- PERI_CLK_TZPC6
- PERI_CLK_TZPC7
- PERI_CLK_TZPC8
- PERI_CLK_TZPC9
- PERI_CLK_UART0
- PERI_CLK_UART1
- PERI_CLK_UART2
- PERI_CLK_UART4
- PERI_CLK_WDT_EGL
- PERI_CLK_WDT_KFC
- PERI_CRG_CLK_DIS4
- PERI_CRG_CLK_EN4
- PERI_CRG_ISODIS
- PERI_CRG_RSTDIS4
- PERI_CRG_RSTEN4
- PERI_DOUT_I2S
- PERI_DOUT_PCM
- PERI_ETH_DLY
- PERI_ETH_DLY_FINE
- PERI_ETH_PHY_INTF_SEL
- PERI_MOUT_SCLK_I2SCOD
- PERI_MOUT_SCLK_PCM
- PERI_MOUT_SCLK_SPDIF
- PERI_NR_CLK
- PERI_SCLK_I2S
- PERI_SCLK_PCM1
- PERI_SCLK_SPDIF
- PERI_SCLK_SPI0
- PERI_SCLK_SPI1
- PERI_SCLK_SPI2
- PERI_SCLK_UART0
- PERI_SCLK_UART1
- PERI_SCLK_UART2
- PERI_SSUSB_SPM_CTRL
- PERI_WK_CTRL1
- PERLINE
- PERL_UNUSED_VAR
- PERMANENT_CONFIG_CONTAINER
- PERMCODEFILE
- PERMISSION
- PERMS_CHRS_MASK
- PERMS_NAMES_MASK
- PERM_ADDR
- PERM_CON
- PERM_RD
- PERM_READ
- PERM_SYMTAB_SIZE
- PERM_WR
- PERM_WRITE
- PEROUT_GPIO
- PERPLL_BYPASS
- PERPLL_SRC_BYPASS
- PERRFATALENABLE_MASK
- PERRFLOODENABLE_MASK
- PERRNONFATALENABLE_MASK
- PERROR
- PERRORDIS
- PERRVFID_F
- PERRVFID_S
- PERRVFID_V
- PERR_DET
- PERR_EN
- PERR_IE_TARGET_ADDR
- PERR_IE_TARGET_FLAGS
- PERR_IE_TARGET_RCODE
- PERR_IE_TARGET_SN
- PERR_IE_TTL
- PERR_INT_CAUSE_F
- PERR_INT_CAUSE_S
- PERR_INT_CAUSE_V
- PERR_INT_ENB
- PERR_MARK
- PERR_OBSERVED_MASK
- PERR_PAR_CAUSE_F
- PERR_PAR_CAUSE_S
- PERR_PAR_CAUSE_V
- PERSHIFTBACKOFFMAX_G
- PERSHIFTBACKOFFMAX_M
- PERSHIFTBACKOFFMAX_S
- PERSHIFTBACKOFFMAX_V
- PERSHIFTMAX_G
- PERSHIFTMAX_M
- PERSHIFTMAX_S
- PERSHIFTMAX_V
- PERSISTENCE_BIT
- PERSISTENT_KEY
- PERSISTENT_RAM_SIG
- PERSISTENT_RESERVE_IN
- PERSISTENT_RESERVE_OUT
- PERSISTENT_SPACE_END
- PERSISTENT_SPACE_START
- PERSMAX_G
- PERSMAX_M
- PERSMAX_S
- PERSMAX_V
- PERSONALITY_CORE
- PERSONALITY_ETH
- PERSONALITY_FCOE
- PERSONALITY_ISCSI
- PERSONALITY_RDMA
- PERSONALITY_RDMA_AND_ETH
- PERSONALITY_RESERVED
- PERSP_GRADIENT_ENA
- PERST_2_ACCESS_MAX
- PERST_2_ACCESS_MIN
- PERST_DELAY_US
- PERST_GLITCH_WIDTH
- PERST_MODE_GPIO
- PERST_MODE_MASK
- PERVASIVE_H
- PER_BSD
- PER_CK
- PER_CLEAR_ON_SETID
- PER_CLK
- PER_CLKF
- PER_CMD_PKT
- PER_CODE_BRANCH
- PER_CODE_IFETCH
- PER_CODE_MASK
- PER_CODE_STORE
- PER_CODE_STORE_REAL
- PER_CONTROL_ALTERATION
- PER_CONTROL_BRANCH_ADDRESS
- PER_CONTROL_MASK
- PER_CONTROL_SUSPENSION
- PER_CPU
- PER_CPU_ALIGNED_SECTION
- PER_CPU_ATTRIBUTES
- PER_CPU_BASE_SECTION
- PER_CPU_FIRST_SECTION
- PER_CPU_IRQ_REGION
- PER_CPU_SHARED_ALIGNED_SECTION
- PER_CPU_VAR
- PER_CTRL_REG
- PER_CTX_ADDR_MASK
- PER_EM_MASK
- PER_EN
- PER_ERR_MSK_REG
- PER_ERR_STS_REG
- PER_EVENT_BRANCH
- PER_EVENT_IFETCH
- PER_EVENT_MASK
- PER_EVENT_NULLIFICATION
- PER_EVENT_STORE
- PER_EVENT_STORE_REAL
- PER_EVENT_TRANSACTION_END
- PER_FLAG_NO_TE
- PER_FLAG_TE_ABORT_RAND
- PER_FLAG_TE_ABORT_RAND_TEND
- PER_HDR1_REG
- PER_HDR2_REG
- PER_HPUX
- PER_INFO_BYTE
- PER_INT_MSK_REG
- PER_INT_STS_REG
- PER_IRIX32
- PER_IRIX64
- PER_IRIXN32
- PER_ISCR4
- PER_LINUX
- PER_LINUX32
- PER_LINUX32_3GB
- PER_LINUX_32BIT
- PER_LINUX_FDPIC
- PER_MASK
- PER_MAX_LOG_COUNT
- PER_MIN_LOG_COUNT
- PER_OSF4
- PER_OSR5
- PER_PIXEL_ALPHA
- PER_PIXEL_ALPHA_BYPASS_EN
- PER_PKT_STATS_SUPPORTED
- PER_PLATFORM_ANT_GAIN_CMD
- PER_RCU_NODE_PERIOD
- PER_RISCOS
- PER_SCOSVR3
- PER_SEC
- PER_SIZE_REG_SEQ
- PER_SOLARIS
- PER_STAGE_REG_NUM
- PER_STS_REG
- PER_SUNOS
- PER_SVR3
- PER_SVR4
- PER_UW7
- PER_VL_SEND_CONTEXTS
- PER_WYSEV386
- PER_XENIX
- PESDR0_405EX_BIST
- PESDR0_405EX_DLPSET
- PESDR0_405EX_LOOP
- PESDR0_405EX_LPB
- PESDR0_405EX_PHYSET1
- PESDR0_405EX_PHYSET2
- PESDR0_405EX_PHYSTA
- PESDR0_405EX_RCSSET
- PESDR0_405EX_RCSSTS
- PESDR0_405EX_UTLSET1
- PESDR0_405EX_UTLSET2
- PESDR0_440SPE_DLPSET
- PESDR0_440SPE_HSSCTLSET
- PESDR0_440SPE_HSSL0SET1
- PESDR0_440SPE_HSSL0SET2
- PESDR0_440SPE_HSSL0STS
- PESDR0_440SPE_HSSL1SET1
- PESDR0_440SPE_HSSL1SET2
- PESDR0_440SPE_HSSL1STS
- PESDR0_440SPE_HSSL2SET1
- PESDR0_440SPE_HSSL2SET2
- PESDR0_440SPE_HSSL2STS
- PESDR0_440SPE_HSSL3SET1
- PESDR0_440SPE_HSSL3SET2
- PESDR0_440SPE_HSSL3STS
- PESDR0_440SPE_HSSL4SET1
- PESDR0_440SPE_HSSL4SET2
- PESDR0_440SPE_HSSL4STS
- PESDR0_440SPE_HSSL5SET1
- PESDR0_440SPE_HSSL5SET2
- PESDR0_440SPE_HSSL5STS
- PESDR0_440SPE_HSSL6SET1
- PESDR0_440SPE_HSSL6SET2
- PESDR0_440SPE_HSSL6STS
- PESDR0_440SPE_HSSL7SET1
- PESDR0_440SPE_HSSL7SET2
- PESDR0_440SPE_HSSL7STS
- PESDR0_440SPE_LANE_ABCD
- PESDR0_440SPE_LANE_EFGH
- PESDR0_440SPE_LOOP
- PESDR0_440SPE_RCSSET
- PESDR0_440SPE_RCSSTS
- PESDR0_440SPE_UTLSET1
- PESDR0_440SPE_UTLSET2
- PESDR0_460EX_IHS1
- PESDR0_460EX_IHS2
- PESDR0_460EX_L0BIST
- PESDR0_460EX_L0BISTSTS
- PESDR0_460EX_L0CDRCTL
- PESDR0_460EX_L0CLK
- PESDR0_460EX_L0DRV
- PESDR0_460EX_L0ERRC
- PESDR0_460EX_L0LPB
- PESDR0_460EX_L0REC
- PESDR0_460EX_OBS
- PESDR0_460EX_PHY_CTL_RST
- PESDR0_460EX_RSTSTA
- PESDR0_460SX_HSSCTLSET
- PESDR0_460SX_HSSL0COEFA
- PESDR0_460SX_HSSL0DAMP
- PESDR0_460SX_HSSL1CALDRV
- PESDR0_460SX_HSSL1COEFA
- PESDR0_460SX_HSSL1DAMP
- PESDR0_460SX_HSSL2COEFA
- PESDR0_460SX_HSSL2DAMP
- PESDR0_460SX_HSSL3COEFA
- PESDR0_460SX_HSSL3DAMP
- PESDR0_460SX_HSSL4COEFA
- PESDR0_460SX_HSSL4DAMP
- PESDR0_460SX_HSSL5COEFA
- PESDR0_460SX_HSSL5DAMP
- PESDR0_460SX_HSSL6COEFA
- PESDR0_460SX_HSSL6DAMP
- PESDR0_460SX_HSSL7COEFA
- PESDR0_460SX_HSSL7DAMP
- PESDR0_460SX_HSSSLEW
- PESDR0_460SX_RCSSET
- PESDR0_PLLLCT1
- PESDR0_PLLLCT2
- PESDR0_PLLLCT3
- PESDR1_405EX_BIST
- PESDR1_405EX_DLPSET
- PESDR1_405EX_LOOP
- PESDR1_405EX_LPB
- PESDR1_405EX_PHYSET1
- PESDR1_405EX_PHYSET2
- PESDR1_405EX_PHYSTA
- PESDR1_405EX_RCSSET
- PESDR1_405EX_RCSSTS
- PESDR1_405EX_UTLSET1
- PESDR1_405EX_UTLSET2
- PESDR1_440SPE_DLPSET
- PESDR1_440SPE_HSSCTLSET
- PESDR1_440SPE_HSSL0SET1
- PESDR1_440SPE_HSSL0SET2
- PESDR1_440SPE_HSSL0STS
- PESDR1_440SPE_HSSL1SET1
- PESDR1_440SPE_HSSL1SET2
- PESDR1_440SPE_HSSL1STS
- PESDR1_440SPE_HSSL2SET1
- PESDR1_440SPE_HSSL2SET2
- PESDR1_440SPE_HSSL2STS
- PESDR1_440SPE_HSSL3SET1
- PESDR1_440SPE_HSSL3SET2
- PESDR1_440SPE_HSSL3STS
- PESDR1_440SPE_LANE_ABCD
- PESDR1_440SPE_LOOP
- PESDR1_440SPE_RCSSET
- PESDR1_440SPE_RCSSTS
- PESDR1_440SPE_UTLSET1
- PESDR1_440SPE_UTLSET2
- PESDR1_460EX_L0BIST
- PESDR1_460EX_L0BISTSTS
- PESDR1_460EX_L0CDRCTL
- PESDR1_460EX_L0CLK
- PESDR1_460EX_L0DRV
- PESDR1_460EX_L0ERRC
- PESDR1_460EX_L0LPB
- PESDR1_460EX_L0REC
- PESDR1_460EX_L1BIST
- PESDR1_460EX_L1BISTSTS
- PESDR1_460EX_L1CDRCTL
- PESDR1_460EX_L1CLK
- PESDR1_460EX_L1DRV
- PESDR1_460EX_L1ERRC
- PESDR1_460EX_L1LPB
- PESDR1_460EX_L1REC
- PESDR1_460EX_L2BIST
- PESDR1_460EX_L2BISTSTS
- PESDR1_460EX_L2CDRCTL
- PESDR1_460EX_L2CLK
- PESDR1_460EX_L2DRV
- PESDR1_460EX_L2ERRC
- PESDR1_460EX_L2LPB
- PESDR1_460EX_L2REC
- PESDR1_460EX_L3BIST
- PESDR1_460EX_L3BISTSTS
- PESDR1_460EX_L3CDRCTL
- PESDR1_460EX_L3CLK
- PESDR1_460EX_L3DRV
- PESDR1_460EX_L3ERRC
- PESDR1_460EX_L3LPB
- PESDR1_460EX_L3REC
- PESDR1_460EX_OBS
- PESDR1_460EX_PHY_CTL_RST
- PESDR1_460EX_RSTSTA
- PESDR1_460SX_HSSCTLSET
- PESDR1_460SX_HSSL0COEFA
- PESDR1_460SX_HSSL0DAMP
- PESDR1_460SX_HSSL1CALDRV
- PESDR1_460SX_HSSL1COEFA
- PESDR1_460SX_HSSL1DAMP
- PESDR1_460SX_HSSL2COEFA
- PESDR1_460SX_HSSL2DAMP
- PESDR1_460SX_HSSL3COEFA
- PESDR1_460SX_HSSL3DAMP
- PESDR1_460SX_HSSSLEW
- PESDR1_460SX_RCSSET
- PESDR2_440SPE_DLPSET
- PESDR2_440SPE_HSSCTLSET
- PESDR2_440SPE_HSSL0SET1
- PESDR2_440SPE_HSSL0SET2
- PESDR2_440SPE_HSSL0STS
- PESDR2_440SPE_HSSL1SET1
- PESDR2_440SPE_HSSL1SET2
- PESDR2_440SPE_HSSL1STS
- PESDR2_440SPE_HSSL2SET1
- PESDR2_440SPE_HSSL2SET2
- PESDR2_440SPE_HSSL2STS
- PESDR2_440SPE_HSSL3SET1
- PESDR2_440SPE_HSSL3SET2
- PESDR2_440SPE_HSSL3STS
- PESDR2_440SPE_LANE_ABCD
- PESDR2_440SPE_LOOP
- PESDR2_440SPE_RCSSET
- PESDR2_440SPE_RCSSTS
- PESDR2_440SPE_UTLSET1
- PESDR2_440SPE_UTLSET2
- PESDR2_460SX_HSSCTLSET
- PESDR2_460SX_HSSL0COEFA
- PESDR2_460SX_HSSL0DAMP
- PESDR2_460SX_HSSL1CALDRV
- PESDR2_460SX_HSSL1COEFA
- PESDR2_460SX_HSSL1DAMP
- PESDR2_460SX_HSSL2COEFA
- PESDR2_460SX_HSSL2DAMP
- PESDR2_460SX_HSSL3COEFA
- PESDR2_460SX_HSSL3DAMP
- PESDR2_460SX_HSSSLEW
- PESDR2_460SX_RCSSET
- PESDRn_405EX_PHYSET1
- PESDRn_405EX_PHYSET2
- PESDRn_405EX_PHYSTA
- PESDRn_440SPE_HSSL0SET1
- PESDRn_440SPE_HSSL0SET2
- PESDRn_440SPE_HSSL0STS
- PESDRn_440SPE_HSSL1SET1
- PESDRn_440SPE_HSSL1SET2
- PESDRn_440SPE_HSSL1STS
- PESDRn_440SPE_HSSL2SET1
- PESDRn_440SPE_HSSL2SET2
- PESDRn_440SPE_HSSL2STS
- PESDRn_440SPE_HSSL3SET1
- PESDRn_440SPE_HSSL3SET2
- PESDRn_440SPE_HSSL3STS
- PESDRn_440SPE_HSSL4SET1
- PESDRn_440SPE_HSSL4SET2
- PESDRn_440SPE_HSSL4STS
- PESDRn_440SPE_HSSL5SET1
- PESDRn_440SPE_HSSL5SET2
- PESDRn_440SPE_HSSL5STS
- PESDRn_440SPE_HSSL6SET1
- PESDRn_440SPE_HSSL6SET2
- PESDRn_440SPE_HSSL6STS
- PESDRn_440SPE_HSSL7SET1
- PESDRn_440SPE_HSSL7SET2
- PESDRn_440SPE_HSSL7STS
- PESDRn_460SX_RCEI
- PESDRn_DLPSET
- PESDRn_LOOP
- PESDRn_RCSSET
- PESDRn_RCSSTS
- PESDRn_UTLSET1
- PESDRn_UTLSET2
- PESDRx_RCSSET_HLDPLB
- PESDRx_RCSSET_RDY
- PESDRx_RCSSET_RSTDL
- PESDRx_RCSSET_RSTGU
- PESDRx_RCSSET_RSTPYN
- PESEL
- PESEL_ADDR
- PESQI_BDDONE
- PESQI_BDP_START
- PESQI_BD_BASE_ADDR_REG
- PESQI_BD_BUF_LEN_MAX
- PESQI_BD_COUNT
- PESQI_BD_CTRL_REG
- PESQI_BD_CUR_ADDR_REG
- PESQI_BD_POLL_CTRL_REG
- PESQI_BD_RX_DMA_STAT_REG
- PESQI_BD_STAT_REG
- PESQI_BD_TX_DMA_STAT_REG
- PESQI_BURST_EN
- PESQI_CLKDIV
- PESQI_CLKDIV_SHIFT
- PESQI_CLK_CTRL_REG
- PESQI_CLK_EN
- PESQI_CLK_STABLE
- PESQI_CMD_THRES_REG
- PESQI_CONF_REG
- PESQI_CPHA
- PESQI_CPOL
- PESQI_CSEN_SHIFT
- PESQI_CS_CTRL_HW
- PESQI_CTRL_REG
- PESQI_DMAERR
- PESQI_DMA_EN
- PESQI_DUAL_LANE
- PESQI_EN
- PESQI_HOLD_EN
- PESQI_INT_ENABLE_REG
- PESQI_INT_SIGEN_REG
- PESQI_INT_STAT_REG
- PESQI_INT_THRES_REG
- PESQI_LANES_SHIFT
- PESQI_LSBF
- PESQI_MODE
- PESQI_MODE_BOOT
- PESQI_MODE_DMA
- PESQI_MODE_PIO
- PESQI_MODE_SHIFT
- PESQI_MODE_XIP
- PESQI_PKTCOMP
- PESQI_POLL_EN
- PESQI_QUAD_LANE
- PESQI_RXEMPTY
- PESQI_RXFULL
- PESQI_RXLATCH
- PESQI_RXTHR
- PESQI_RXTHR_MASK
- PESQI_RXTHR_SHIFT
- PESQI_RX_DATA_REG
- PESQI_SERMODE
- PESQI_SINGLE_LANE
- PESQI_SOFT_RESET
- PESQI_STAT1_REG
- PESQI_STAT2_REG
- PESQI_THRES_REG
- PESQI_TXEMPTY
- PESQI_TXFULL
- PESQI_TXTHR
- PESQI_TXTHR_MASK
- PESQI_TXTHR_SHIFT
- PESQI_TX_DATA_REG
- PESQI_WP_EN
- PESQI_XIP_CONF1_REG
- PESQI_XIP_CONF2_REG
- PES_CRC_FLAG
- PES_EXT_FLAG
- PES_STREAM
- PETATEL_PRODUCT_NP10T_600A
- PETATEL_PRODUCT_NP10T_600E
- PETATEL_VENDOR_ID
- PETBI_CONTROL_REG
- PETBI_CTRL_ALL_PARAMS
- PETBI_CTRL_AUTO_NEG
- PETBI_CTRL_FULL_DUPLEX
- PETBI_CTRL_RESTART_NEG
- PETBI_CTRL_SOFT_RESET
- PETBI_CTRL_SPEED_1000
- PETBI_EXPANSION_REG
- PETBI_EXP_PAGE_RX
- PETBI_NEG_ADVER
- PETBI_NEG_DUPLEX
- PETBI_NEG_DUPLEX_MASK
- PETBI_NEG_ERROR_MASK
- PETBI_NEG_PARTNER
- PETBI_NEG_PAUSE
- PETBI_NEG_PAUSE_MASK
- PETBI_STATUS_REG
- PETBI_STAT_LINK_UP
- PETBI_STAT_NEG_DONE
- PETBI_TBI_AUTO_SENSE
- PETBI_TBI_CTRL
- PETBI_TBI_RESET
- PETBI_TBI_SERDES_MODE
- PETBI_TBI_SERDES_WRAP
- PETXCFG
- PET_ADDR
- PEUTL_INTR
- PEUTL_IPDBSZ
- PEUTL_IPHBSZ
- PEUTL_OPDBSZ
- PEUTL_OUTTR
- PEUTL_PBBSZ
- PEUTL_PBCTL
- PEUTL_PCTL
- PEUTL_RCIRQEN
- PEUTL_RCSTA
- PEW
- PEX811X
- PEXECUTE
- PEXPEVT
- PEXTDEV_Def
- PEXTDEV_Mask
- PEXTDEV_Print
- PEXTDEV_Read
- PEXTDEV_Val
- PEXTDEV_Write
- PEX_COMMAND
- PEX_CSR0_LTSSM_L0
- PEX_CSR0_LTSSM_MASK
- PEX_CSR0_LTSSM_SHIFT
- PEX_DB_ACCESS
- PEX_ERR_ICCAD_DISR_BIT
- PEX_ERR_ICCAIE_EN_BIT
- PEX_GET_SENSOR_COUNT
- PEX_GET_SENSOR_DATA
- PEX_GET_SENSOR_NAME
- PEX_GET_VERSION
- PEX_MULT_LEN
- PEX_NET_FUNCTION
- PEX_NUM_SENSOR_FUNCS
- PEX_OUTWIN0_BAR
- PEX_OUTWIN0_TAH
- PEX_OUTWIN0_TAL
- PEX_PIO_ENABLE_SHIFT
- PEX_PMCR_EXL2S
- PEX_PMCR_PTOMR
- PEX_RCIWARn_EN
- PEX_RC_INWIN_BASE
- PEX_RD_ACCESS
- PEX_RESET_HIGH_LOW
- PEX_SENSOR_TYPE_LEN
- PE_AIC_ENABLED_STAT
- PE_AIC_ENABLE_CLR
- PE_AIC_ENABLE_CTRL
- PE_AIC_ENABLE_SET
- PE_AIC_OPTIONS
- PE_AIC_POL_CTRL
- PE_AIC_RAW_STAT
- PE_AIC_TYPE_CTRL
- PE_AIC_VERSION
- PE_BASE
- PE_CONTEXT_CTRL
- PE_CONTEXT_STAT
- PE_CSA1
- PE_CSA2
- PE_CSA3
- PE_CSB0
- PE_CSB1
- PE_CSB2
- PE_CSB3
- PE_CTS
- PE_CURRENT0
- PE_CURRENT1
- PE_CURRENT2
- PE_CURRENT3
- PE_CURRENT_0_0_mA
- PE_CURRENT_0_5_mA
- PE_CURRENT_0_mA_T114
- PE_CURRENT_10_mA_T114
- PE_CURRENT_11_mA_T114
- PE_CURRENT_12_mA_T114
- PE_CURRENT_13_mA_T114
- PE_CURRENT_14_mA_T114
- PE_CURRENT_15_mA_T114
- PE_CURRENT_1_0_mA
- PE_CURRENT_1_5_mA
- PE_CURRENT_1_mA_T114
- PE_CURRENT_2_0_mA
- PE_CURRENT_2_5_mA
- PE_CURRENT_2_mA_T114
- PE_CURRENT_3_0_mA
- PE_CURRENT_3_5_mA
- PE_CURRENT_3_mA_T114
- PE_CURRENT_4_0_mA
- PE_CURRENT_4_5_mA
- PE_CURRENT_4_mA_T114
- PE_CURRENT_5_0_mA
- PE_CURRENT_5_5_mA
- PE_CURRENT_5_mA_T114
- PE_CURRENT_6_0_mA
- PE_CURRENT_6_5_mA
- PE_CURRENT_6_mA_T114
- PE_CURRENT_7_0_mA
- PE_CURRENT_7_5_mA
- PE_CURRENT_7_mA_T114
- PE_CURRENT_8_mA_T114
- PE_CURRENT_9_mA_T114
- PE_DEF_MTU
- PE_DWE
- PE_EIP96_AIC_ACK
- PE_EIP96_AIC_ENABLED_STAT
- PE_EIP96_AIC_ENABLE_CLR
- PE_EIP96_AIC_ENABLE_CTRL
- PE_EIP96_AIC_ENABLE_SET
- PE_EIP96_AIC_OPTIONS
- PE_EIP96_AIC_POL_CTRL
- PE_EIP96_AIC_RAW_STAT
- PE_EIP96_AIC_TYPE_CTRL
- PE_EIP96_AIC_VERSION
- PE_EIP96_OPTIONS
- PE_EIP96_VERSION
- PE_FUNCTION_EN
- PE_GLOBAL_CLASS_A_STATS_INFO
- PE_GLOBAL_CLASS_B_STATS_INFO
- PE_GLOBAL_CLASS_C_STATS_INFO
- PE_GLOBAL_CLASS_D_STATS_INFO
- PE_INTERRUPT_CTRL_STAT
- PE_IN_DBUF_THRESH
- PE_IN_FLIGHT
- PE_IN_TBUF_THRESH
- PE_MAGIC
- PE_MAX_MTU
- PE_MIN_MTU
- PE_NONE
- PE_OPTIONS
- PE_OPT_MAGIC_PE32
- PE_OPT_MAGIC_PE32PLUS
- PE_OPT_MAGIC_PE32_ROM
- PE_OUT_BUF_CTRL
- PE_OUT_DBUF_THRESH
- PE_OUT_TBUF_THRESH
- PE_OUT_TRANS_CTRL_STAT
- PE_PATHGROUP_ESTABLISHED
- PE_PATH_AVAILABLE
- PE_PATH_GONE
- PE_PER_STA_STATS_INFO
- PE_PRNG_CTRL
- PE_PRNG_KEY_0_H
- PE_PRNG_KEY_0_L
- PE_PRNG_KEY_1_H
- PE_PRNG_KEY_1_L
- PE_PRNG_LFSR_H
- PE_PRNG_LFSR_L
- PE_PRNG_RES_0
- PE_PRNG_RES_1
- PE_PRNG_RES_2
- PE_PRNG_RES_3
- PE_PRNG_SEED_H
- PE_PRNG_SEED_L
- PE_PRNG_STAT
- PE_RTS
- PE_RXD
- PE_SIZE_PMD
- PE_SIZE_PTE
- PE_SIZE_PUD
- PE_SPMCLK
- PE_SPMRXD
- PE_SPMTXD
- PE_STATS_TYPE_MAX
- PE_SUMMARY_STATS_INFO
- PE_TOKEN_CTRL_STAT
- PE_TXD
- PE_VERSION
- PF
- PF0
- PF0INT_ITR_0
- PF0INT_ITR_1
- PF0INT_ITR_2
- PF0LKPIDX_M
- PF0MD_00
- PF0MD_000
- PF0MD_001
- PF0MD_01
- PF0MD_010
- PF0MD_011
- PF0MD_10
- PF0MD_100
- PF0MD_101
- PF0MD_11
- PF0MD_110
- PF0MD_111
- PF0_AIN_PC_RST
- PF0_BASE
- PF0_DATA
- PF0_FN
- PF0_IN
- PF0_IOR_IN
- PF0_IOR_OUT
- PF0_OUT
- PF0_PF_NRFB
- PF0_REG
- PF1
- PF10MD_00
- PF10MD_000
- PF10MD_001
- PF10MD_01
- PF10MD_010
- PF10MD_011
- PF10MD_10
- PF10MD_100
- PF10MD_101
- PF10MD_110
- PF10MD_111
- PF10_AF_ATA_RESET
- PF10_AOUT_PC_WP
- PF10_DATA
- PF10_IN
- PF10_IOR_IN
- PF10_IOR_OUT
- PF10_OUT
- PF10_PF_NFIO3
- PF10_PF_PC_RST
- PF11MD_00
- PF11MD_000
- PF11MD_001
- PF11MD_01
- PF11MD_010
- PF11MD_011
- PF11MD_10
- PF11MD_100
- PF11MD_101
- PF11MD_110
- PF11MD_111
- PF11_AF_ATA_DMACK
- PF11_AOUT_PC_READY
- PF11_DATA
- PF11_IN
- PF11_IOR_IN
- PF11_IOR_OUT
- PF11_OUT
- PF11_PF_NFIO4
- PF11_PF_PC_BVD2
- PF12MD_00
- PF12MD_000
- PF12MD_001
- PF12MD_01
- PF12MD_010
- PF12MD_011
- PF12MD_10
- PF12MD_100
- PF12MD_101
- PF12MD_110
- PF12MD_111
- PF12_AF_ATA_DMAREQ
- PF12_AOUT_PC_WAIT
- PF12_DATA
- PF12_IN
- PF12_IOR_IN
- PF12_IOR_OUT
- PF12_OUT
- PF12_PF_NFIO5
- PF12_PF_PC_BVD1
- PF13MD_00
- PF13MD_000
- PF13MD_001
- PF13MD_01
- PF13MD_010
- PF13MD_011
- PF13MD_10
- PF13MD_100
- PF13MD_101
- PF13MD_110
- PF13MD_111
- PF13_AF_ATA_DA0
- PF13_AOUT_PC_CD2
- PF13_DATA
- PF13_IN
- PF13_IOR_IN
- PF13_IOR_OUT
- PF13_OUT
- PF13_PF_NFIO6
- PF13_PF_PC_VS2
- PF14MD_00
- PF14MD_000
- PF14MD_001
- PF14MD_01
- PF14MD_010
- PF14MD_011
- PF14MD_10
- PF14MD_100
- PF14MD_101
- PF14MD_110
- PF14MD_111
- PF14_AF_ATA_DA1
- PF14_AOUT_PC_CD1
- PF14_DATA
- PF14_IN
- PF14_IOR_IN
- PF14_IOR_OUT
- PF14_OUT
- PF14_PF_NFIO7
- PF14_PF_PC_VS1
- PF15MD_00
- PF15MD_000
- PF15MD_001
- PF15MD_01
- PF15MD_010
- PF15MD_011
- PF15MD_10
- PF15MD_100
- PF15MD_101
- PF15MD_110
- PF15MD_111
- PF15_AF_ETMTRACE_SYNC
- PF15_DATA
- PF15_IN
- PF15_IOR_IN
- PF15_IOR_OUT
- PF15_OUT
- PF15_PF_CLKO
- PF16MD_00
- PF16MD_000
- PF16MD_001
- PF16MD_01
- PF16MD_010
- PF16MD_011
- PF16MD_10
- PF16MD_100
- PF16MD_101
- PF16MD_110
- PF16MD_111
- PF16_AF_ATA_DA2
- PF16_DATA
- PF16_IN
- PF16_IOR_IN
- PF16_IOR_OUT
- PF16_OUT
- PF16_PF_PC_PWRON
- PF16_PF_RES
- PF17MD_00
- PF17MD_000
- PF17MD_001
- PF17MD_01
- PF17MD_010
- PF17MD_011
- PF17MD_10
- PF17MD_100
- PF17MD_101
- PF17MD_110
- PF17MD_111
- PF17_AF_ATA_CS0
- PF17_DATA
- PF17_IN
- PF17_IOR_IN
- PF17_IOR_OUT
- PF17_OUT
- PF17_PF_PC_READY
- PF18MD_00
- PF18MD_000
- PF18MD_001
- PF18MD_01
- PF18MD_010
- PF18MD_011
- PF18MD_10
- PF18MD_100
- PF18MD_101
- PF18MD_110
- PF18MD_111
- PF18_AF_ATA_CS1
- PF18_DATA
- PF18_IN
- PF18_IOR_IN
- PF18_IOR_OUT
- PF18_OUT
- PF18_PF_PC_WAIT
- PF19MD_00
- PF19MD_000
- PF19MD_001
- PF19MD_01
- PF19MD_010
- PF19MD_011
- PF19MD_10
- PF19MD_100
- PF19MD_101
- PF19MD_110
- PF19MD_111
- PF19_AF_ATA_DIOW
- PF19_DATA
- PF19_IN
- PF19_IOR_IN
- PF19_IOR_OUT
- PF19_OUT
- PF19_PF_PC_CD2
- PF1LKPIDX_S
- PF1MD_00
- PF1MD_000
- PF1MD_001
- PF1MD_01
- PF1MD_010
- PF1MD_011
- PF1MD_10
- PF1MD_100
- PF1MD_101
- PF1MD_11
- PF1MD_110
- PF1MD_111
- PF1MSKSIZE_M
- PF1MSKSIZE_S
- PF1_AF_ETMTRACE_PKT0
- PF1_AIN_PC_CE1
- PF1_DATA
- PF1_FN
- PF1_IN
- PF1_IOR_IN
- PF1_IOR_OUT
- PF1_OUT
- PF1_PF_NFCE
- PF1_PF_NFCLE
- PF2
- PF20MD_00
- PF20MD_000
- PF20MD_001
- PF20MD_01
- PF20MD_010
- PF20MD_011
- PF20MD_10
- PF20MD_100
- PF20MD_101
- PF20MD_110
- PF20MD_111
- PF20_AF_ATA_DIOR
- PF20_DATA
- PF20_IN
- PF20_IOR_IN
- PF20_IOR_OUT
- PF20_OUT
- PF20_PF_PC_CD1
- PF21MD_00
- PF21MD_000
- PF21MD_001
- PF21MD_01
- PF21MD_010
- PF21MD_011
- PF21MD_10
- PF21MD_100
- PF21MD_101
- PF21MD_110
- PF21MD_111
- PF21_AOUT_DTACK
- PF21_DATA
- PF21_IN
- PF21_IOR_IN
- PF21_IOR_OUT
- PF21_OUT
- PF21_PF_CS4
- PF22MD_00
- PF22MD_000
- PF22MD_001
- PF22MD_01
- PF22MD_010
- PF22MD_011
- PF22MD_10
- PF22MD_100
- PF22MD_101
- PF22MD_110
- PF22MD_111
- PF22_AF_ETMTRACE_CLK
- PF22_DATA
- PF22_IN
- PF22_IOR_IN
- PF22_IOR_OUT
- PF22_OUT
- PF22_PF_CS5
- PF23MD_00
- PF23MD_000
- PF23MD_001
- PF23MD_01
- PF23MD_010
- PF23MD_011
- PF23MD_10
- PF23MD_100
- PF23MD_101
- PF23MD_110
- PF23MD_111
- PF23_AF_ETMTRACE_PKT4
- PF23_AIN_FEC_TX_EN
- PF23_DATA
- PF23_IN
- PF23_IOR_IN
- PF23_IOR_OUT
- PF23_OUT
- PF23_PF_ATA_DATA15
- PF24MD_0
- PF24MD_1
- PF24_DATA
- PF24_IN
- PF24_OUT
- PF25MD_0
- PF25MD_1
- PF25_DATA
- PF25_IN
- PF25_OUT
- PF26MD_0
- PF26MD_1
- PF26_DATA
- PF26_IN
- PF26_OUT
- PF27MD_0
- PF27MD_1
- PF27_CIN_EXT_DMA_GRANT
- PF27_DATA
- PF27_IN
- PF27_OUT
- PF28MD_0
- PF28MD_1
- PF28_DATA
- PF28_IN
- PF28_OUT
- PF29MD_0
- PF29MD_1
- PF29_DATA
- PF29_IN
- PF29_OUT
- PF2MD_00
- PF2MD_000
- PF2MD_001
- PF2MD_01
- PF2MD_010
- PF2MD_011
- PF2MD_10
- PF2MD_100
- PF2MD_101
- PF2MD_11
- PF2MD_110
- PF2MD_111
- PF2_AIN_PC_CE2
- PF2_DATA
- PF2_FN
- PF2_IN
- PF2_IOR_IN
- PF2_IOR_OUT
- PF2_OUT
- PF2_PF_NFWP
- PF3
- PF30MD_0
- PF30MD_1
- PF30_DATA
- PF30_IN
- PF30_OUT
- PF38F4476
- PF3MD_00
- PF3MD_000
- PF3MD_001
- PF3MD_01
- PF3MD_010
- PF3MD_011
- PF3MD_10
- PF3MD_100
- PF3MD_101
- PF3MD_11
- PF3MD_110
- PF3MD_111
- PF3_AF_ETMTRACE_PKT2
- PF3_AIN_PC_POE
- PF3_DATA
- PF3_FN
- PF3_IN
- PF3_IOR_IN
- PF3_IOR_OUT
- PF3_OUT
- PF3_PF_NFCE
- PF3_PF_NFCLE
- PF4
- PF4MD_00
- PF4MD_000
- PF4MD_001
- PF4MD_01
- PF4MD_010
- PF4MD_011
- PF4MD_10
- PF4MD_100
- PF4MD_101
- PF4MD_11
- PF4MD_110
- PF4MD_111
- PF4_AIN_PC_OE
- PF4_DATA
- PF4_FN
- PF4_IN
- PF4_IOR_IN
- PF4_IOR_OUT
- PF4_OUT
- PF4_PF_NFALE
- PF5MD_00
- PF5MD_000
- PF5MD_001
- PF5MD_01
- PF5MD_010
- PF5MD_011
- PF5MD_10
- PF5MD_100
- PF5MD_101
- PF5MD_11
- PF5MD_110
- PF5MD_111
- PF5_AF_ETMPIPESTAT11
- PF5_AIN_PC_RW
- PF5_DATA
- PF5_FN
- PF5_IN
- PF5_IOR_IN
- PF5_IOR_OUT
- PF5_OUT
- PF5_PF_NFRE
- PF6MD_00
- PF6MD_000
- PF6MD_001
- PF6MD_01
- PF6MD_010
- PF6MD_011
- PF6MD_10
- PF6MD_100
- PF6MD_101
- PF6MD_11
- PF6MD_110
- PF6MD_111
- PF6_AOUT_PC_BVD2
- PF6_DATA
- PF6_FN
- PF6_IN
- PF6_IOR_IN
- PF6_IOR_OUT
- PF6_OUT
- PF6_PF_NFWE
- PF7MD_00
- PF7MD_000
- PF7MD_001
- PF7MD_01
- PF7MD_010
- PF7MD_011
- PF7MD_10
- PF7MD_100
- PF7MD_101
- PF7MD_11
- PF7MD_110
- PF7MD_111
- PF7_AF_ATA_BUFFER_EN
- PF7_AOUT_PC_BVD1
- PF7_DATA
- PF7_FN
- PF7_IN
- PF7_IOR_IN
- PF7_IOR_OUT
- PF7_OUT
- PF7_PF_NFIO0
- PF7_PF_PC_POE
- PF8MD_00
- PF8MD_000
- PF8MD_001
- PF8MD_01
- PF8MD_010
- PF8MD_011
- PF8MD_10
- PF8MD_100
- PF8MD_101
- PF8MD_11
- PF8MD_110
- PF8MD_111
- PF8_AF_ATA_IORDY
- PF8_AOUT_PC_VS2
- PF8_DATA
- PF8_IN
- PF8_IOR_IN
- PF8_IOR_OUT
- PF8_OUT
- PF8_PF_NFIO1
- PF8_PF_PC_RW
- PF9MD_00
- PF9MD_000
- PF9MD_001
- PF9MD_01
- PF9MD_010
- PF9MD_011
- PF9MD_10
- PF9MD_100
- PF9MD_101
- PF9MD_110
- PF9MD_111
- PF9_AF_ATA_INTRQ
- PF9_AOUT_PC_VS1
- PF9_DATA
- PF9_IN
- PF9_IOR_IN
- PF9_IOR_OUT
- PF9_OUT
- PF9_PF_NFIO2
- PF9_PF_PC_IOIS16
- PFAT_STATE_E
- PFAULT_DONE
- PFAULT_INIT
- PFAXP2_ATN
- PFAXP2_CTN
- PFA_NO_NEW_PRIVS
- PFA_SPEC_IB_DISABLE
- PFA_SPEC_IB_FORCE_DISABLE
- PFA_SPEC_SSB_DISABLE
- PFA_SPEC_SSB_FORCE_DISABLE
- PFA_SPEC_SSB_NOEXEC
- PFA_SPREAD_PAGE
- PFA_SPREAD_SLAB
- PFBASE
- PFB_Def
- PFB_Mask
- PFB_Print
- PFB_Read
- PFB_Val
- PFB_Write
- PFCEIL
- PFCIM_F
- PFCIM_S
- PFCIM_V
- PFCR
- PFCV1_PC1V_MASK
- PFCV1_PC1V_SHIFT
- PFCV2_PC2V_MASK
- PFCV2_PC2V_SHIFT
- PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD
- PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD
- PFC_BRB_FULL_LB_XOFF_THRESHOLD
- PFC_BRB_FULL_LB_XON_THRESHOLD
- PFC_ECC_DB_ERR
- PFC_ECC_SG_ERR
- PFC_MISC_0_ERR
- PFC_MISC_1_ERR
- PFC_MISC_ERR_1
- PFC_PCIX_ERR
- PFC_PHCR
- PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA
- PFC_SM_ERR_ALARM
- PFC_STORM_PREVENTION_AUTO
- PFC_STORM_PREVENTION_DISABLE
- PFC_VALUE_FRAME_SIZE
- PFD0_CLKGATE
- PFD1_CLKGATE
- PFD2_CLKGATE
- PFD3_CLKGATE
- PFDATA
- PFDATA_ADDR
- PFDIR
- PFDIR_ADDR
- PFDR
- PFDR_AR_EN
- PFD_PLL1_BASE
- PFD_PLL2_BASE
- PFD_PLL3_BASE
- PFEN
- PFER
- PFERR_FETCH_BIT
- PFERR_FETCH_MASK
- PFERR_GUEST_FINAL_BIT
- PFERR_GUEST_FINAL_MASK
- PFERR_GUEST_PAGE_BIT
- PFERR_GUEST_PAGE_MASK
- PFERR_NESTED_GUEST_PAGE
- PFERR_PK_BIT
- PFERR_PK_MASK
- PFERR_PRESENT_BIT
- PFERR_PRESENT_MASK
- PFERR_RSVD_BIT
- PFERR_RSVD_MASK
- PFERR_USER_BIT
- PFERR_USER_MASK
- PFERR_WRITE_BIT
- PFERR_WRITE_MASK
- PFE_REG
- PFF
- PFGEN_CTRL
- PFGEN_CTRL_PFSWR_M
- PFGEN_STATE
- PFHMC_ERRORDATA
- PFHMC_ERRORINFO
- PFIFO_Def
- PFIFO_FAST_BANDS
- PFIFO_Mask
- PFIFO_Print
- PFIFO_RD_PTR
- PFIFO_Read
- PFIFO_Val
- PFIFO_WR_PTR
- PFIFO_Write
- PFILTER_OPCODES_ARM_H
- PFINT_FW_CTL
- PFINT_FW_CTL_CAUSE_ENA_M
- PFINT_FW_CTL_ITR_INDX_M
- PFINT_FW_CTL_ITR_INDX_S
- PFINT_FW_CTL_MSIX_INDX_M
- PFINT_MBX_CTL
- PFINT_MBX_CTL_CAUSE_ENA_M
- PFINT_MBX_CTL_ITR_INDX_M
- PFINT_MBX_CTL_ITR_INDX_S
- PFINT_MBX_CTL_MSIX_INDX_M
- PFINT_OICR
- PFINT_OICR_CTL
- PFINT_OICR_CTL_CAUSE_ENA_M
- PFINT_OICR_CTL_ITR_INDX_M
- PFINT_OICR_CTL_ITR_INDX_S
- PFINT_OICR_CTL_MSIX_INDX_M
- PFINT_OICR_ECC_ERR_M
- PFINT_OICR_ENA
- PFINT_OICR_GRST_M
- PFINT_OICR_HMC_ERR_M
- PFINT_OICR_MAL_DETECT_M
- PFINT_OICR_PCI_EXCEPTION_M
- PFINT_OICR_PE_CRITERR_M
- PFINT_OICR_SWINT_M
- PFINT_OICR_VFLR_M
- PFIT_AUTO_RATIOS
- PFIT_CONTROL
- PFIT_ENABLE
- PFIT_FILTER_FUZZY
- PFIT_HORIZ_SCALE_MASK
- PFIT_HORIZ_SCALE_MASK_965
- PFIT_HORIZ_SCALE_SHIFT
- PFIT_HORIZ_SCALE_SHIFT_965
- PFIT_PGM_RATIOS
- PFIT_PIPE_MASK
- PFIT_PIPE_SELECT
- PFIT_PIPE_SELECT_SHIFT
- PFIT_PIPE_SHIFT
- PFIT_SCALING_AUTO
- PFIT_SCALING_LETTER
- PFIT_SCALING_MODE_LETTERBOX
- PFIT_SCALING_MODE_PILLARBOX
- PFIT_SCALING_PILLAR
- PFIT_SCALING_PROGRAMMED
- PFIT_VERT_SCALE_MASK
- PFIT_VERT_SCALE_MASK_965
- PFIT_VERT_SCALE_SHIFT
- PFIT_VERT_SCALE_SHIFT_965
- PFI_CREDIT
- PFI_CREDIT_31
- PFI_CREDIT_63
- PFI_CREDIT_RESEND
- PFI_K_CSR_IO_LEN
- PFI_K_CSR_MEM_LEN
- PFI_K_LAT_TIMER_DEF
- PFI_K_LAT_TIMER_MIN
- PFI_K_PKT_MEM_LEN
- PFI_K_REG_FIFO_READ
- PFI_K_REG_FIFO_WRITE
- PFI_K_REG_MODE_CTRL
- PFI_K_REG_RESERVED_0
- PFI_K_REG_RESERVED_1
- PFI_K_REG_STATUS
- PFI_MODE_K_ALL_DISABLE
- PFI_MODE_M_DMA_ENB
- PFI_MODE_M_PDQ_INT_ENB
- PFI_MODE_M_PFI_INT_ENB
- PFI_MODE_M_RESERVED
- PFI_MODE_M_TGT_ABORT_ENB
- PFI_MODE_V_DMA_ENB
- PFI_MODE_V_PDQ_INT_ENB
- PFI_MODE_V_PFI_INT_ENB
- PFI_MODE_V_RESERVED
- PFI_MODE_V_TGT_ABORT_ENB
- PFI_STATUS_M_DMA_IN_PROGRESS
- PFI_STATUS_M_FIFO_EMPTY
- PFI_STATUS_M_FIFO_FULL
- PFI_STATUS_M_PDQ_DMA_ABORT
- PFI_STATUS_M_PDQ_INT
- PFI_STATUS_M_PFI_ERROR
- PFI_STATUS_M_RESERVED
- PFI_STATUS_V_DMA_IN_PROGRESS
- PFI_STATUS_V_FIFO_EMPTY
- PFI_STATUS_V_FIFO_FULL
- PFI_STATUS_V_PDQ_DMA_ABORT
- PFI_STATUS_V_PDQ_INT
- PFI_STATUS_V_PFI_ERROR
- PFI_STATUS_V_RESERVED
- PFKEYV2_REVISION
- PFKEY_ALIGN8
- PFLAG
- PFLAG_RANGE
- PFLAG_RANGE_DEFAULT
- PFLASH_PADS_DISABLE
- PFMASK
- PFMC0
- PFMC1
- PFMC2
- PFMC_BUS_GRANT
- PFMC_BUS_OWNERSHIP
- PFMC_C1EV
- PFMC_C1RS
- PFMC_C1SS_MASK
- PFMC_C1SS_SHIFT
- PFMC_C2EV
- PFMC_C2RS
- PFMC_C2SS_MASK
- PFMC_C2SS_SHIFT
- PFMC_DISCONNECT_RETRY
- PFMC_DWORD_TRANSFER
- PFMC_GRANT_AFTER_REQ
- PFMC_INTERRUPT
- PFMC_PCI_CLOCK
- PFMC_PREEMPTION
- PFMC_SERIAL_CLOCK
- PFMC_SLAVE_READ
- PFMC_SLAVE_WRITE
- PFMC_SP_CLOCK
- PFMC_TRANSACTION
- PFMC_TRANSACTION_LAG
- PFMEM
- PFMFS_MAGIC
- PFMF_CF
- PFMF_FSC
- PFMF_KEY
- PFMF_MC
- PFMF_MR
- PFMF_NQ
- PFMF_RESERVED
- PFMF_SK
- PFMF_UI
- PFM_ALDN
- PFM_CHECK_PMC_PM
- PFM_CMD
- PFM_CMD_ARG_MANY
- PFM_CMD_ARG_READ
- PFM_CMD_ARG_RW
- PFM_CMD_COUNT
- PFM_CMD_FD
- PFM_CMD_NAME
- PFM_CMD_NONE
- PFM_CMD_PCLRW
- PFM_CMD_PCLRWS
- PFM_CMD_READ_ARG
- PFM_CMD_RW_ARG
- PFM_CMD_S
- PFM_CMD_STOP
- PFM_CMD_STOPPED
- PFM_CMD_USE_FD
- PFM_CODE_RR
- PFM_CPUINFO_CLEAR
- PFM_CPUINFO_DCR_PP
- PFM_CPUINFO_EXCL_IDLE
- PFM_CPUINFO_GET
- PFM_CPUINFO_SET
- PFM_CPUINFO_SYST_WIDE
- PFM_CREATE_CONTEXT
- PFM_CTL_mskEN0
- PFM_CTL_mskEN1
- PFM_CTL_mskEN2
- PFM_CTL_mskIE0
- PFM_CTL_mskIE1
- PFM_CTL_mskIE2
- PFM_CTL_mskKS0
- PFM_CTL_mskKS1
- PFM_CTL_mskKS2
- PFM_CTL_mskKU0
- PFM_CTL_mskKU1
- PFM_CTL_mskKU2
- PFM_CTL_mskOVF0
- PFM_CTL_mskOVF1
- PFM_CTL_mskOVF2
- PFM_CTL_mskSEL0
- PFM_CTL_mskSEL1
- PFM_CTL_mskSEL2
- PFM_CTL_offEN0
- PFM_CTL_offEN1
- PFM_CTL_offEN2
- PFM_CTL_offIE0
- PFM_CTL_offIE1
- PFM_CTL_offIE2
- PFM_CTL_offKS0
- PFM_CTL_offKS1
- PFM_CTL_offKS2
- PFM_CTL_offKU0
- PFM_CTL_offKU1
- PFM_CTL_offKU2
- PFM_CTL_offOVF0
- PFM_CTL_offOVF1
- PFM_CTL_offOVF2
- PFM_CTL_offSEL0
- PFM_CTL_offSEL1
- PFM_CTL_offSEL2
- PFM_CTXARG_BUF_ARG
- PFM_CTXQ_EMPTY
- PFM_CTX_LOADED
- PFM_CTX_MASKED
- PFM_CTX_TASK
- PFM_CTX_UNLOADED
- PFM_CTX_ZOMBIE
- PFM_D3COLD_EN
- PFM_DATA_RR
- PFM_DEBUG
- PFM_DEBUGGING
- PFM_DEFAULT_MAX_ENTRY_SIZE
- PFM_DEFAULT_MAX_PMDS
- PFM_DEFAULT_SMPL_MIN_BUF_SIZE
- PFM_DEFAULT_SMPL_UUID
- PFM_DEFAULT_SMPL_VERSION
- PFM_DEFAULT_SMPL_VERSION_MAJ
- PFM_DEFAULT_SMPL_VERSION_MIN
- PFM_DESTROY_CONTEXT
- PFM_DISABLE
- PFM_EN
- PFM_ENABLE
- PFM_FL_NOTIFY_BLOCK
- PFM_FL_OVFL_NO_MSG
- PFM_FL_SYSTEM_WIDE
- PFM_GET_CTX
- PFM_GET_FEATURES
- PFM_GET_PMC_RESET_VAL
- PFM_GET_WORK_PENDING
- PFM_INVALID_ACTIVATION
- PFM_IS_FILE
- PFM_LDALL
- PFM_LDKP
- PFM_LOAD_CONTEXT
- PFM_MASK
- PFM_MAX_ARGSIZE
- PFM_MAX_MSGS
- PFM_MSG_END
- PFM_MSG_OVFL
- PFM_NUM_DBRS
- PFM_NUM_IBRS
- PFM_NUM_PMC_REGS
- PFM_NUM_PMD_REGS
- PFM_OFFSET_MAGIC_0
- PFM_OFFSET_MAGIC_1
- PFM_OFFSET_MAGIC_2
- PFM_PMD_LONG_RESET
- PFM_PMD_SHORT_RESET
- PFM_PMU_IRQ_RESEND
- PFM_PROC_SHOW_HEADER
- PFM_PROTECT_CONTEXT
- PFM_PWM_SWITCH
- PFM_READ_PMDS
- PFM_REGFL_OVFL_NOTIFY
- PFM_REGFL_RANDOM
- PFM_REG_BUFFER
- PFM_REG_CONFIG
- PFM_REG_CONTROL
- PFM_REG_COUNTING
- PFM_REG_END
- PFM_REG_HAS_ERROR
- PFM_REG_IMPL
- PFM_REG_MONITOR
- PFM_REG_NOTIMPL
- PFM_REG_RETFLAG_SET
- PFM_REG_RETFL_EINVAL
- PFM_REG_RETFL_MASK
- PFM_REG_RETFL_NOTAVAIL
- PFM_RESTART
- PFM_SETFL_EXCL_IDLE
- PFM_SET_WORK_PENDING
- PFM_START
- PFM_STOP
- PFM_TRAP_REASON_BLOCK
- PFM_TRAP_REASON_NONE
- PFM_TRAP_REASON_RESET
- PFM_UNLOAD_CONTEXT
- PFM_UNPROTECT_CONTEXT
- PFM_VERSION
- PFM_VERSION_MAJ
- PFM_VERSION_MAJOR
- PFM_VERSION_MIN
- PFM_VERSION_MINOR
- PFM_WOWL
- PFM_WRITE_DBRS
- PFM_WRITE_IBRS
- PFM_WRITE_PMCS
- PFM_WRITE_PMDS
- PFN
- PFNUM_S
- PFNUM_V
- PFN_16M
- PFN_4G
- PFN_4G_MASK
- PFN_ALIGN
- PFN_BIAS
- PFN_DEV
- PFN_DOWN
- PFN_FLAGS_MASK
- PFN_FLAGS_TRACE
- PFN_MAP
- PFN_MASK
- PFN_MAX
- PFN_MODE_NONE
- PFN_MODE_PMEM
- PFN_MODE_RAM
- PFN_NASIDSHFT
- PFN_PHYS
- PFN_PTE_SHIFT
- PFN_SECTION_SHIFT
- PFN_SG_CHAIN
- PFN_SG_LAST
- PFN_SHIFT_OFFSET
- PFN_SIG
- PFN_SIG_LEN
- PFN_SPECIAL
- PFN_START
- PFN_SUBSECTION_SHIFT
- PFN_UP
- PFO
- PFOW_CLEAR_PROGRAM_BUFFER
- PFOW_COMMAND_ADDRESS_H
- PFOW_COMMAND_ADDRESS_L
- PFOW_COMMAND_CODE
- PFOW_COMMAND_DATA
- PFOW_COMMAND_EXECUTE
- PFOW_DATA_COUNT_H
- PFOW_DATA_COUNT_L
- PFOW_DEVICE_ID
- PFOW_DSR
- PFOW_MANUFACTURER_ID
- PFOW_PROGRAM_BUFFER_OFFSET
- PFOW_PROGRAM_BUFFER_SIZE
- PFOW_PROGRAM_ERASE_SUSPEND
- PFOW_QUERY_STRING_F
- PFOW_QUERY_STRING_O
- PFOW_QUERY_STRING_P
- PFOW_QUERY_STRING_W
- PFPUEN
- PFPUEN_ADDR
- PFR
- PFRAME
- PFRAME_BIT
- PFRCR
- PFSEL
- PFSEL_ADDR
- PFSR2SEG_END
- PFSR2SEG_START
- PFSR4SEG_END
- PFSR4SEG_START
- PFSTAT2SEG_END
- PFSTAT2SEG_START
- PFSTAT4SEG_END
- PFSTAT4SEG_START
- PFSW_F
- PFSW_S
- PFSW_V
- PFS_ISEL
- PFTARG2SEG_END
- PFTARG2SEG_START
- PFTARG4SEG_END
- PFTARG4SEG_START
- PFTCR
- PFT_ARCH_V1_0
- PFT_ARCH_V1_1
- PFULDPX
- PFUZE100
- PFUZE100_COIN
- PFUZE100_COINVOL
- PFUZE100_COIN_REG
- PFUZE100_CONF_OFFSET
- PFUZE100_DEVICEID
- PFUZE100_FABID
- PFUZE100_FIXED_REG
- PFUZE100_MAX_REGULATOR
- PFUZE100_MODE_OFFSET
- PFUZE100_REVID
- PFUZE100_STANDBY_OFFSET
- PFUZE100_SW1AB
- PFUZE100_SW1ABMODE
- PFUZE100_SW1ABVOL
- PFUZE100_SW1C
- PFUZE100_SW1CMODE
- PFUZE100_SW1CVOL
- PFUZE100_SW2
- PFUZE100_SW2MODE
- PFUZE100_SW2VOL
- PFUZE100_SW3A
- PFUZE100_SW3AMODE
- PFUZE100_SW3AVOL
- PFUZE100_SW3B
- PFUZE100_SW3BMODE
- PFUZE100_SW3BVOL
- PFUZE100_SW4
- PFUZE100_SW4MODE
- PFUZE100_SW4VOL
- PFUZE100_SWBST
- PFUZE100_SWBSTCON1
- PFUZE100_SWB_REG
- PFUZE100_SW_REG
- PFUZE100_SWxMODE_APS_APS
- PFUZE100_SWxMODE_APS_OFF
- PFUZE100_SWxMODE_MASK
- PFUZE100_VGEN1
- PFUZE100_VGEN1VOL
- PFUZE100_VGEN2
- PFUZE100_VGEN2VOL
- PFUZE100_VGEN3
- PFUZE100_VGEN3VOL
- PFUZE100_VGEN4
- PFUZE100_VGEN4VOL
- PFUZE100_VGEN5
- PFUZE100_VGEN5VOL
- PFUZE100_VGEN6
- PFUZE100_VGEN6VOL
- PFUZE100_VGEN_REG
- PFUZE100_VGENxLPWR
- PFUZE100_VGENxSTBY
- PFUZE100_VOL_OFFSET
- PFUZE100_VREFDDR
- PFUZE100_VREFDDRCON
- PFUZE100_VSNVS
- PFUZE100_VSNVSVOL
- PFUZE200
- PFUZE200_COIN
- PFUZE200_SW1AB
- PFUZE200_SW2
- PFUZE200_SW3A
- PFUZE200_SW3B
- PFUZE200_SWBST
- PFUZE200_VGEN1
- PFUZE200_VGEN2
- PFUZE200_VGEN3
- PFUZE200_VGEN4
- PFUZE200_VGEN5
- PFUZE200_VGEN6
- PFUZE200_VREFDDR
- PFUZE200_VSNVS
- PFUZE3000
- PFUZE3000_SW1A
- PFUZE3000_SW1B
- PFUZE3000_SW2
- PFUZE3000_SW2_REG
- PFUZE3000_SW3
- PFUZE3000_SW3_REG
- PFUZE3000_SWBST
- PFUZE3000_V33
- PFUZE3000_VCCSD
- PFUZE3000_VCC_REG
- PFUZE3000_VLDO1
- PFUZE3000_VLDO2
- PFUZE3000_VLDO3
- PFUZE3000_VLDO4
- PFUZE3000_VREFDDR
- PFUZE3000_VSNVS
- PFUZE3001
- PFUZE3001_SW1
- PFUZE3001_SW2
- PFUZE3001_SW3
- PFUZE3001_V33
- PFUZE3001_VCCSD
- PFUZE3001_VLDO1
- PFUZE3001_VLDO2
- PFUZE3001_VLDO3
- PFUZE3001_VLDO4
- PFUZE3001_VSNVS
- PFUZE_FLAG_DISABLE_SW
- PFUZE_NUMREGS
- PFVF_ACQUIRE_CAP_100G
- PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED
- PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE
- PFVF_ACQUIRE_CAP_QUEUE_QIDS
- PFVF_BULLETIN_CRC_ERR
- PFVF_BULLETIN_UNCHANGED
- PFVF_BULLETIN_UPDATED
- PFVF_CAP_DHC
- PFVF_CAP_RSS
- PFVF_CAP_TPA
- PFVF_CAP_TPA_UPDATE
- PFVF_CAP_VLAN_FILTER
- PFVF_MAX_FILTERS
- PFVF_MAX_MAC_FILTERS
- PFVF_MAX_MULTICAST_PER_VF
- PFVF_MAX_QUEUES_PER_VF
- PFVF_MAX_SBS_PER_VF
- PFVF_MAX_VLAN_FILTERS
- PFVF_STATUS_FAILURE
- PFVF_STATUS_FORCED
- PFVF_STATUS_MALICIOUS
- PFVF_STATUS_NOT_SUPPORTED
- PFVF_STATUS_NO_RESOURCE
- PFVF_STATUS_SUCCESS
- PFVF_STATUS_WAITING
- PFX
- PFX_eckd_data
- PF_A
- PF_A20
- PF_A21
- PF_A22
- PF_A23
- PF_A24
- PF_A25
- PF_A26
- PF_A27
- PF_A28
- PF_A29
- PF_A30
- PF_A31
- PF_AL44
- PF_AL88
- PF_ALG
- PF_ALPHA_C_MASK
- PF_ALPHA_C_SHIFT
- PF_ANY
- PF_APPLETALK
- PF_ARGB1555
- PF_ARGB4444
- PF_ARGB8888
- PF_ASH
- PF_ATMPVC
- PF_ATMSVC
- PF_AUTOBOOT
- PF_AUTOSEARCH
- PF_AX25
- PF_BASE
- PF_BITS_MASK
- PF_BITWIDTH
- PF_BLUETOOTH
- PF_BLUE_C_MASK
- PF_BLUE_C_SHIFT
- PF_BRIDGE
- PF_BYTE_F
- PF_CAIF
- PF_CAN
- PF_CGXMAP_BASE
- PF_CLKO
- PF_COMPLETE
- PF_COMP_0_MASK
- PF_COMP_0_SHIFT
- PF_COMP_1_MASK
- PF_COMP_1_SHIFT
- PF_COMP_2_MASK
- PF_COMP_2_SHIFT
- PF_COMP_3_MASK
- PF_COMP_3_SHIFT
- PF_CONF
- PF_CONTEXT_BEHAVIOUR_MASK
- PF_COUNT
- PF_CSA1
- PF_CTL
- PF_DECnet
- PF_DUMPCORE
- PF_ECONET
- PF_ENABLE
- PF_EVENT_SEVERITY_CERTAIN_DOOM
- PF_EVENT_SEVERITY_INFO
- PF_EXITING
- PF_FD_HDS
- PF_FD_MAX
- PF_FD_SPT
- PF_FILTER_EDGE_ENHANCE
- PF_FILTER_EDGE_SOFTEN
- PF_FILTER_MASK
- PF_FILTER_MED_3x3
- PF_FILTER_PROGRAMMED
- PF_FL_RW
- PF_FL_UPROBE
- PF_FORKNOEXEC
- PF_FREEZER_SKIP
- PF_FROZEN
- PF_FUNC_RID
- PF_FUNC_RID_FUNC_NUM_M
- PF_FUNC_RID_FUNC_NUM_S
- PF_FW_ARQBAH
- PF_FW_ARQBAL
- PF_FW_ARQH
- PF_FW_ARQH_ARQH_M
- PF_FW_ARQLEN
- PF_FW_ARQLEN_ARQCRIT_M
- PF_FW_ARQLEN_ARQENABLE_M
- PF_FW_ARQLEN_ARQLEN_M
- PF_FW_ARQLEN_ARQOVFL_M
- PF_FW_ARQLEN_ARQVFE_M
- PF_FW_ARQT
- PF_FW_ATQBAH
- PF_FW_ATQBAL
- PF_FW_ATQH
- PF_FW_ATQH_ATQH_M
- PF_FW_ATQLEN
- PF_FW_ATQLEN_ATQCRIT_M
- PF_FW_ATQLEN_ATQENABLE_M
- PF_FW_ATQLEN_ATQLEN_M
- PF_FW_ATQLEN_ATQOVFL_M
- PF_FW_ATQLEN_ATQVFE_M
- PF_FW_ATQT
- PF_G
- PF_GREEN_C_MASK
- PF_GREEN_C_SHIFT
- PF_HD_HDS
- PF_HD_SPT
- PF_HEAD
- PF_HP
- PF_HP_CODE
- PF_HP_FAR_SHARED
- PF_HP_LAZYSWAP
- PF_HP_MODIFY
- PF_HP_NEAR_SHARED
- PF_HP_PAGE_SIZE
- PF_HP_SBP
- PF_HSCALE
- PF_IB
- PF_IDLE
- PF_IEEE802154
- PF_INET
- PF_INET6
- PF_INTR_MASK
- PF_IPX
- PF_IRDA
- PF_IRQ5
- PF_ISDN
- PF_IS_V11
- PF_IUCV
- PF_KCM
- PF_KEY
- PF_KEY_V2
- PF_KHTREAD
- PF_KOU
- PF_KSWAPD
- PF_KTHREAD
- PF_L8
- PF_LCONTRAST
- PF_LESS_THROTTLE
- PF_LLC
- PF_LOCAL
- PF_M
- PF_MAC_CREDIT_E2
- PF_MAJOR
- PF_MASK
- PF_MAX
- PF_MAX_RETRIES
- PF_MBX_ARQBAH
- PF_MBX_ARQBAL
- PF_MBX_ARQH
- PF_MBX_ARQH_ARQH_M
- PF_MBX_ARQLEN
- PF_MBX_ARQLEN_ARQENABLE_M
- PF_MBX_ARQLEN_ARQLEN_M
- PF_MBX_ARQT
- PF_MBX_ATQBAH
- PF_MBX_ATQBAL
- PF_MBX_ATQH
- PF_MBX_ATQH_ATQH_M
- PF_MBX_ATQLEN
- PF_MBX_ATQLEN_ATQENABLE_M
- PF_MBX_ATQLEN_ATQLEN_M
- PF_MBX_ATQT
- PF_MCE_EARLY
- PF_MCE_PROCESS
- PF_MDET_RX
- PF_MDET_RX_VALID_M
- PF_MDET_TX_PQM
- PF_MDET_TX_PQM_VALID_M
- PF_MDET_TX_TCLAN
- PF_MDET_TX_TCLAN_VALID_M
- PF_MEMALLOC
- PF_MEMALLOC_NOCMA
- PF_MEMALLOC_NOFS
- PF_MEMALLOC_NOIO
- PF_MEMSTALL
- PF_MPLS
- PF_NAME
- PF_NAMELEN
- PF_NETBEUI
- PF_NETLINK
- PF_NETROM
- PF_NFC
- PF_NM
- PF_NOFREEZE
- PF_NONE
- PF_NOTIFY
- PF_NO_COMPOUND
- PF_NO_SETAFFINITY
- PF_NO_TAIL
- PF_NPROC_EXCEEDED
- PF_NUM_IGNORE
- PF_OFFS
- PF_ONLY_HEAD
- PF_OXS
- PF_PACKET
- PF_PALETTE
- PF_PARISC_SBP
- PF_PCI_CIAA
- PF_PCI_CIAA_VF_NUM_S
- PF_PCI_CIAD
- PF_PHONET
- PF_PIPE_SEL_IVB
- PF_PIPE_SEL_MASK_IVB
- PF_PIXEL_S_MASK
- PF_PIXEL_S_SHIFT
- PF_POISONED_CHECK
- PF_POWERUP_LOCK
- PF_PPPOX
- PF_QIPCRTR
- PF_R
- PF_RANDOMIZE
- PF_RDONLY
- PF_RDS
- PF_RED_C_MASK
- PF_RED_C_SHIFT
- PF_REG
- PF_RESET_TMO
- PF_RESUME
- PF_RES_DATA_1_PF_QPC_BT_IDX_M
- PF_RES_DATA_1_PF_QPC_BT_IDX_S
- PF_RES_DATA_1_PF_QPC_BT_NUM_M
- PF_RES_DATA_1_PF_QPC_BT_NUM_S
- PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_M
- PF_RES_DATA_1_PF_QPC_TIMER_BT_IDX_S
- PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M
- PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S
- PF_RES_DATA_1_PF_SMAC_IDX_M
- PF_RES_DATA_1_PF_SMAC_IDX_S
- PF_RES_DATA_1_PF_SMAC_NUM_M
- PF_RES_DATA_1_PF_SMAC_NUM_S
- PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_M
- PF_RES_DATA_2_PF_CQC_TIMER_BT_IDX_S
- PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M
- PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S
- PF_RES_DATA_2_PF_SGID_IDX_M
- PF_RES_DATA_2_PF_SGID_IDX_S
- PF_RES_DATA_2_PF_SGID_NUM_M
- PF_RES_DATA_2_PF_SGID_NUM_S
- PF_RES_DATA_2_PF_SRQC_BT_IDX_M
- PF_RES_DATA_2_PF_SRQC_BT_IDX_S
- PF_RES_DATA_2_PF_SRQC_BT_NUM_M
- PF_RES_DATA_2_PF_SRQC_BT_NUM_S
- PF_RES_DATA_3_PF_CQC_BT_IDX_M
- PF_RES_DATA_3_PF_CQC_BT_IDX_S
- PF_RES_DATA_3_PF_CQC_BT_NUM_M
- PF_RES_DATA_3_PF_CQC_BT_NUM_S
- PF_RES_DATA_3_PF_QID_IDX_M
- PF_RES_DATA_3_PF_QID_IDX_S
- PF_RES_DATA_3_PF_SL_NUM_M
- PF_RES_DATA_3_PF_SL_NUM_S
- PF_RES_DATA_4_PF_MPT_BT_IDX_M
- PF_RES_DATA_4_PF_MPT_BT_IDX_S
- PF_RES_DATA_4_PF_MPT_BT_NUM_M
- PF_RES_DATA_4_PF_MPT_BT_NUM_S
- PF_RES_DATA_4_PF_SCCC_BT_IDX_M
- PF_RES_DATA_4_PF_SCCC_BT_IDX_S
- PF_RES_DATA_4_PF_SCCC_BT_NUM_M
- PF_RES_DATA_4_PF_SCCC_BT_NUM_S
- PF_RES_DATA_5_PF_EQC_BT_IDX_M
- PF_RES_DATA_5_PF_EQC_BT_IDX_S
- PF_RES_DATA_5_PF_EQC_BT_NUM_M
- PF_RES_DATA_5_PF_EQC_BT_NUM_S
- PF_RGB565
- PF_RGB888
- PF_RGBA8888
- PF_RO
- PF_ROSE
- PF_ROUTE
- PF_RQ_PENDING
- PF_RW
- PF_RXRPC
- PF_S
- PF_SECURITY
- PF_SIGNALED
- PF_SMC
- PF_SNA
- PF_SPIN
- PF_SPIN_DEL
- PF_STRIDE
- PF_SUPERPRIV
- PF_SUSPEND_TASK
- PF_SWAPWRITE
- PF_TESTED
- PF_TIMER
- PF_TIPC
- PF_TMO
- PF_TO_CHANNEL
- PF_TO_PPP
- PF_TO_X
- PF_UMH
- PF_UNITS
- PF_UNIX
- PF_UNSPEC
- PF_USED_ASYNC
- PF_USED_MATH
- PF_VCPU
- PF_VECTOR
- PF_VERSION
- PF_VF_BULLETIN_SIZE
- PF_VLAN_CREDIT_E2
- PF_VPORT_ID
- PF_VSCALE
- PF_VSOCK
- PF_VT_PFALLOC_HIF
- PF_W
- PF_WANPIPE
- PF_WIN_POS
- PF_WIN_SZ
- PF_WQ_WORKER
- PF_X
- PF_X25
- PF_XDP
- PG
- PG0MD_000
- PG0MD_001
- PG0MD_010
- PG0MD_011
- PG0MD_100
- PG0MD_101
- PG0MD_110
- PG0MD_111
- PG0_DATA
- PG0_FN
- PG0_IN
- PG0_IOR_IN
- PG0_IOR_OUT
- PG0_OUT
- PG0_RBCR0
- PG0_RBCR1
- PG0_RSAR0
- PG0_RSAR1
- PG10MD_000
- PG10MD_001
- PG10MD_010
- PG10MD_011
- PG10MD_100
- PG10MD_101
- PG10MD_110
- PG10MD_111
- PG10_DATA
- PG10_IN
- PG10_IOR_IN
- PG10_IOR_OUT
- PG10_OUT
- PG11MD_000
- PG11MD_001
- PG11MD_010
- PG11MD_011
- PG11MD_100
- PG11MD_101
- PG11MD_110
- PG11MD_111
- PG11_DATA
- PG11_IN
- PG11_IOR_IN
- PG11_IOR_OUT
- PG11_OUT
- PG12MD_00
- PG12MD_000
- PG12MD_001
- PG12MD_01
- PG12MD_010
- PG12MD_011
- PG12MD_10
- PG12MD_100
- PG12MD_101
- PG12MD_11
- PG12MD_110
- PG12MD_111
- PG12_DATA
- PG12_IN
- PG12_IOR_IN
- PG12_IOR_OUT
- PG12_OUT
- PG13MD_00
- PG13MD_000
- PG13MD_001
- PG13MD_01
- PG13MD_010
- PG13MD_011
- PG13MD_10
- PG13MD_100
- PG13MD_101
- PG13MD_11
- PG13MD_110
- PG13MD_111
- PG13_DATA
- PG13_IN
- PG13_IOR_IN
- PG13_IOR_OUT
- PG13_OUT
- PG14MD_00
- PG14MD_000
- PG14MD_001
- PG14MD_01
- PG14MD_010
- PG14MD_011
- PG14MD_10
- PG14MD_100
- PG14MD_101
- PG14MD_11
- PG14MD_110
- PG14MD_111
- PG14_DATA
- PG14_IN
- PG14_IOR_IN
- PG14_IOR_OUT
- PG14_OUT
- PG15MD_00
- PG15MD_000
- PG15MD_001
- PG15MD_01
- PG15MD_010
- PG15MD_011
- PG15MD_10
- PG15MD_100
- PG15MD_101
- PG15MD_11
- PG15MD_110
- PG15MD_111
- PG15_DATA
- PG15_IN
- PG15_IOR_IN
- PG15_IOR_OUT
- PG15_OUT
- PG16MD_00
- PG16MD_000
- PG16MD_001
- PG16MD_01
- PG16MD_010
- PG16MD_011
- PG16MD_10
- PG16MD_100
- PG16MD_101
- PG16MD_11
- PG16MD_110
- PG16MD_111
- PG16_DATA
- PG16_IN
- PG16_IOR_IN
- PG16_IOR_OUT
- PG16_OUT
- PG17MD_00
- PG17MD_000
- PG17MD_001
- PG17MD_01
- PG17MD_010
- PG17MD_011
- PG17MD_10
- PG17MD_100
- PG17MD_101
- PG17MD_11
- PG17MD_110
- PG17MD_111
- PG17_DATA
- PG17_IN
- PG17_IOR_IN
- PG17_IOR_OUT
- PG17_OUT
- PG18MD_000
- PG18MD_001
- PG18MD_010
- PG18MD_011
- PG18MD_100
- PG18MD_101
- PG18MD_110
- PG18MD_111
- PG18_DATA
- PG18_IN
- PG18_IOR_IN
- PG18_IOR_OUT
- PG18_OUT
- PG19MD_000
- PG19MD_001
- PG19MD_010
- PG19MD_011
- PG19MD_100
- PG19MD_101
- PG19MD_110
- PG19MD_111
- PG19_DATA
- PG19_IN
- PG19_IOR_IN
- PG19_IOR_OUT
- PG19_OUT
- PG1MD_00
- PG1MD_000
- PG1MD_001
- PG1MD_01
- PG1MD_010
- PG1MD_011
- PG1MD_10
- PG1MD_100
- PG1MD_101
- PG1MD_11
- PG1MD_110
- PG1MD_111
- PG1_DATA
- PG1_FN
- PG1_IN
- PG1_IOR_IN
- PG1_IOR_OUT
- PG1_OUT
- PG20MD_000
- PG20MD_001
- PG20MD_010
- PG20MD_011
- PG20MD_100
- PG20MD_101
- PG20MD_110
- PG20MD_111
- PG20_DATA
- PG20_IN
- PG20_IOR_IN
- PG20_IOR_OUT
- PG20_OUT
- PG21MD_00
- PG21MD_000
- PG21MD_001
- PG21MD_01
- PG21MD_010
- PG21MD_011
- PG21MD_10
- PG21MD_100
- PG21MD_101
- PG21MD_11
- PG21MD_110
- PG21MD_111
- PG21_DATA
- PG21_IN
- PG21_IOR_IN
- PG21_IOR_OUT
- PG21_OUT
- PG22MD_00
- PG22MD_000
- PG22MD_001
- PG22MD_01
- PG22MD_010
- PG22MD_011
- PG22MD_10
- PG22MD_100
- PG22MD_101
- PG22MD_11
- PG22MD_110
- PG22MD_111
- PG22_DATA
- PG22_IN
- PG22_IOR_IN
- PG22_IOR_OUT
- PG22_OUT
- PG23MD_00
- PG23MD_000
- PG23MD_001
- PG23MD_01
- PG23MD_010
- PG23MD_011
- PG23MD_10
- PG23MD_100
- PG23MD_101
- PG23MD_11
- PG23MD_110
- PG23MD_111
- PG23_DATA
- PG23_IN
- PG23_IOR_IN
- PG23_IOR_OUT
- PG23_OUT
- PG24MD_00
- PG24MD_01
- PG24MD_10
- PG24MD_11
- PG24_DATA
- PG24_IN
- PG24_IOR_IN
- PG24_IOR_OUT
- PG24_OUT
- PG25MD_00
- PG25MD_01
- PG25MD_10
- PG25MD_11
- PG25_DATA
- PG25_IN
- PG25_IOR_IN
- PG25_IOR_OUT
- PG25_OUT
- PG26MD_00
- PG26MD_01
- PG26MD_10
- PG26MD_11
- PG26_DATA
- PG26_IN
- PG26_IOR_IN
- PG26_IOR_OUT
- PG26_OUT
- PG27MD_00
- PG27MD_01
- PG27MD_10
- PG27MD_11
- PG27_DATA
- PG27_IN
- PG27_IOR_IN
- PG27_IOR_OUT
- PG27_OUT
- PG2MD_00
- PG2MD_000
- PG2MD_001
- PG2MD_01
- PG2MD_010
- PG2MD_011
- PG2MD_10
- PG2MD_100
- PG2MD_101
- PG2MD_11
- PG2MD_110
- PG2MD_111
- PG2_DATA
- PG2_FN
- PG2_IN
- PG2_IOR_IN
- PG2_IOR_OUT
- PG2_OUT
- PG3MD_00
- PG3MD_000
- PG3MD_001
- PG3MD_01
- PG3MD_010
- PG3MD_011
- PG3MD_10
- PG3MD_100
- PG3MD_101
- PG3MD_11
- PG3MD_110
- PG3MD_111
- PG3_DATA
- PG3_FN
- PG3_IN
- PG3_IOR_IN
- PG3_IOR_OUT
- PG3_OUT
- PG4MD_00
- PG4MD_000
- PG4MD_001
- PG4MD_01
- PG4MD_010
- PG4MD_011
- PG4MD_10
- PG4MD_100
- PG4MD_101
- PG4MD_11
- PG4MD_110
- PG4MD_111
- PG4_DATA
- PG4_FN
- PG4_IN
- PG4_IOR_IN
- PG4_IOR_OUT
- PG4_OUT
- PG5MD_00
- PG5MD_000
- PG5MD_001
- PG5MD_01
- PG5MD_010
- PG5MD_011
- PG5MD_10
- PG5MD_100
- PG5MD_101
- PG5MD_11
- PG5MD_110
- PG5MD_111
- PG5_DATA
- PG5_FN
- PG5_IN
- PG5_IOR_IN
- PG5_IOR_OUT
- PG5_OUT
- PG6MD_00
- PG6MD_000
- PG6MD_001
- PG6MD_01
- PG6MD_010
- PG6MD_011
- PG6MD_10
- PG6MD_100
- PG6MD_101
- PG6MD_11
- PG6MD_110
- PG6MD_111
- PG6_DATA
- PG6_FN
- PG6_IN
- PG6_IOR_IN
- PG6_IOR_OUT
- PG6_OUT
- PG7MD_00
- PG7MD_000
- PG7MD_001
- PG7MD_01
- PG7MD_010
- PG7MD_011
- PG7MD_10
- PG7MD_100
- PG7MD_101
- PG7MD_11
- PG7MD_110
- PG7MD_111
- PG7_DATA
- PG7_FN
- PG7_IN
- PG7_IOR_IN
- PG7_IOR_OUT
- PG7_OUT
- PG8MD_000
- PG8MD_001
- PG8MD_010
- PG8MD_011
- PG8MD_100
- PG8MD_101
- PG8MD_110
- PG8MD_111
- PG8_DATA
- PG8_IN
- PG8_IOR_IN
- PG8_IOR_OUT
- PG8_OUT
- PG9MD_000
- PG9MD_001
- PG9MD_010
- PG9MD_011
- PG9MD_100
- PG9MD_101
- PG9MD_110
- PG9MD_111
- PG9_DATA
- PG9_IN
- PG9_IOR_IN
- PG9_IOR_OUT
- PG9_OUT
- PGACTIVATE
- PGACT_DETERM
- PGACT_NETRAND
- PGACT_NONE
- PGALLOC
- PGALLOC_GFP
- PGAL_2_HPLCOM_VOL
- PGAL_2_HPLOUT_VOL
- PGAL_2_HPRCOM_VOL
- PGAL_2_HPROUT_VOL
- PGAL_2_LLOPM_VOL
- PGAL_2_MONOLOPM_VOL
- PGAL_2_RLOPM_VOL
- PGAR_2_HPLCOM_VOL
- PGAR_2_HPLOUT_VOL
- PGAR_2_HPRCOM_VOL
- PGAR_2_HPROUT_VOL
- PGAR_2_LLOPM_VOL
- PGAR_2_MONOLOPM_VOL
- PGAR_2_RLOPM_VOL
- PGA_MUX_AIN0
- PGA_MUX_AIN1
- PGA_MUX_AIN2
- PGA_MUX_MASK
- PGA_MUX_NONE
- PGA_RETURN_EN
- PGCTRL
- PGC_DOMAIN_FLAG_NO_PD
- PGD
- PGDATA
- PGDATA_ADDR
- PGDAT_CONGESTED
- PGDAT_DIRTY
- PGDAT_RECLAIM_LOCKED
- PGDAT_WRITEBACK
- PGDEACTIVATE
- PGDIR
- PGDIR_ADDR
- PGDIR_BITS
- PGDIR_MASK
- PGDIR_SHIFT
- PGDIR_SIZE
- PGDR
- PGDR_MAIN_BATTERY_OUT
- PGDR_OPENED
- PGDR_PLAY_BUTTON
- PGDR_RECORD_BUTTON
- PGDR_REWIND_BUTTON
- PGD_ALIGN
- PGD_ALLOCATION_ORDER
- PGD_ALLOC_ORDER
- PGD_ALLOWED_BITS
- PGD_BOUND
- PGD_ENTRY_SIZE
- PGD_FLAGS
- PGD_IDENT_ATTR
- PGD_INDEX
- PGD_INDEX_SIZE
- PGD_KERNEL_START
- PGD_LEVEL_MULT
- PGD_MASKED_BITS
- PGD_ORDER
- PGD_PAE_PAGE_MASK
- PGD_PAE_PHYS_MASK
- PGD_SIZE
- PGD_TABLE_SIZE
- PGD_T_LOG2
- PGD_VAL_BITS
- PGE_EMPTY
- PGFAULT
- PGFREE
- PGID_AGGR
- PGID_CPU
- PGID_MC
- PGID_MCIPV4
- PGID_MCIPV6
- PGID_RETRIES
- PGID_SRC
- PGID_TIMEOUT
- PGID_UC
- PGINODESTEAL
- PGLAZYFREE
- PGLAZYFREED
- PGLCS_REG_DBG_DWORD_ENABLE_K2_E5
- PGLCS_REG_DBG_FORCE_FRAME_K2_E5
- PGLCS_REG_DBG_FORCE_VALID_K2_E5
- PGLCS_REG_DBG_SELECT_K2_E5
- PGLCS_REG_DBG_SHIFT_K2_E5
- PGLIST_NENTS
- PGLUE_ATTENTION_DETAILS2_BME_MASK
- PGLUE_ATTENTION_DETAILS2_BME_SHIFT
- PGLUE_ATTENTION_DETAILS2_FID_EN_MASK
- PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT
- PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK
- PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT
- PGLUE_ATTENTION_DETAILS_PFID_MASK
- PGLUE_ATTENTION_DETAILS_PFID_SHIFT
- PGLUE_ATTENTION_DETAILS_VFID_MASK
- PGLUE_ATTENTION_DETAILS_VFID_SHIFT
- PGLUE_ATTENTION_DETAILS_VF_VALID_MASK
- PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT
- PGLUE_ATTENTION_ICPL_VALID
- PGLUE_ATTENTION_ILT_VALID
- PGLUE_ATTENTION_RD_VALID
- PGLUE_ATTENTION_VALID
- PGLUE_ATTENTION_ZLR_VALID
- PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
- PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
- PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
- PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
- PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
- PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
- PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
- PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
- PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
- PGLUE_B_REG_ADMIN_PER_PF_REGION
- PGLUE_B_REG_CFG_SPACE_A_REQUEST
- PGLUE_B_REG_CFG_SPACE_B_REQUEST
- PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE
- PGLUE_B_REG_CSDM_INB_INT_B_VF
- PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE
- PGLUE_B_REG_CSDM_START_OFFSET_A
- PGLUE_B_REG_CSDM_START_OFFSET_B
- PGLUE_B_REG_CSDM_VF_SHIFT_B
- PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF
- PGLUE_B_REG_DBG_DWORD_ENABLE
- PGLUE_B_REG_DBG_FORCE_FRAME
- PGLUE_B_REG_DBG_FORCE_VALID
- PGLUE_B_REG_DBG_SELECT
- PGLUE_B_REG_DBG_SHIFT
- PGLUE_B_REG_FLR_REQUEST_PF_7_0
- PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
- PGLUE_B_REG_FLR_REQUEST_VF_127_96
- PGLUE_B_REG_FLR_REQUEST_VF_31_0
- PGLUE_B_REG_FLR_REQUEST_VF_63_32
- PGLUE_B_REG_FLR_REQUEST_VF_95_64
- PGLUE_B_REG_INCORRECT_RCV_DETAILS
- PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
- PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
- PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE
- PGLUE_B_REG_INTERNAL_VFID_ENABLE
- PGLUE_B_REG_LATCHED_ERRORS_CLR
- PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE
- PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0
- PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32
- PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS
- PGLUE_B_REG_PF_BAR0_SIZE
- PGLUE_B_REG_PF_BAR1_SIZE
- PGLUE_B_REG_PGLUE_B_INT_STS
- PGLUE_B_REG_PGLUE_B_INT_STS_CLR
- PGLUE_B_REG_PGLUE_B_PRTY_MASK
- PGLUE_B_REG_PGLUE_B_PRTY_STS
- PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR
- PGLUE_B_REG_PGL_ADDR_88_F0_BB
- PGLUE_B_REG_PGL_ADDR_8C_F0_BB
- PGLUE_B_REG_PGL_ADDR_90_F0_BB
- PGLUE_B_REG_PGL_ADDR_94_F0_BB
- PGLUE_B_REG_PGL_ADDR_E8_F0_K2
- PGLUE_B_REG_PGL_ADDR_EC_F0_K2
- PGLUE_B_REG_PGL_ADDR_F0_F0_K2
- PGLUE_B_REG_PGL_ADDR_F4_F0_K2
- PGLUE_B_REG_RX_ERR_DETAILS
- PGLUE_B_REG_RX_TCPL_ERR_DETAILS
- PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
- PGLUE_B_REG_SR_IOV_DISABLED_REQUEST
- PGLUE_B_REG_TAGS_63_32
- PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE
- PGLUE_B_REG_TSDM_START_OFFSET_A
- PGLUE_B_REG_TSDM_START_OFFSET_B
- PGLUE_B_REG_TSDM_VF_SHIFT_B
- PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF
- PGLUE_B_REG_TX_ERR_RD_ADD_31_0
- PGLUE_B_REG_TX_ERR_RD_ADD_63_32
- PGLUE_B_REG_TX_ERR_RD_DETAILS
- PGLUE_B_REG_TX_ERR_RD_DETAILS2
- PGLUE_B_REG_TX_ERR_WR_ADD_31_0
- PGLUE_B_REG_TX_ERR_WR_ADD_63_32
- PGLUE_B_REG_TX_ERR_WR_DETAILS
- PGLUE_B_REG_TX_ERR_WR_DETAILS2
- PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL
- PGLUE_B_REG_USDM_INB_INT_A_0
- PGLUE_B_REG_USDM_INB_INT_A_1
- PGLUE_B_REG_USDM_INB_INT_A_2
- PGLUE_B_REG_USDM_INB_INT_A_3
- PGLUE_B_REG_USDM_INB_INT_A_4
- PGLUE_B_REG_USDM_INB_INT_A_5
- PGLUE_B_REG_USDM_INB_INT_A_6
- PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE
- PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE
- PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE
- PGLUE_B_REG_USDM_START_OFFSET_A
- PGLUE_B_REG_USDM_START_OFFSET_B
- PGLUE_B_REG_USDM_VF_SHIFT_B
- PGLUE_B_REG_USDM_ZONE_A_SIZE_PF
- PGLUE_B_REG_USE_CLIENTID_IN_TAG
- PGLUE_B_REG_VF_BAR1_SIZE
- PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS
- PGLUE_B_REG_VF_ILT_ERR_ADD_31_0
- PGLUE_B_REG_VF_ILT_ERR_ADD_63_32
- PGLUE_B_REG_VF_ILT_ERR_DETAILS
- PGLUE_B_REG_VF_ILT_ERR_DETAILS2
- PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS
- PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR
- PGLUE_B_REG_WAS_ERROR_PF_7_0
- PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
- PGLUE_B_REG_WAS_ERROR_VF_127_96
- PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR
- PGLUE_B_REG_WAS_ERROR_VF_31_0
- PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR
- PGLUE_B_REG_WAS_ERROR_VF_63_32
- PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR
- PGLUE_B_REG_WAS_ERROR_VF_95_64
- PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR
- PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE
- PGLUE_B_REG_XSDM_START_OFFSET_A
- PGLUE_B_REG_XSDM_START_OFFSET_B
- PGLUE_B_REG_XSDM_VF_SHIFT_B
- PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF
- PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET
- PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET
- PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET
- PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET
- PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET
- PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET
- PGLUE_REG_B_VF_BASE_RT_OFFSET
- PGMAJFAULT
- PGMAP_ALTMAP_VALID
- PGMIGRATE_FAIL
- PGMIGRATE_SUCCESS
- PGMK
- PGM_ADDRESSING
- PGM_AFX_TRANSLATION
- PGM_ALEN_TRANSLATION
- PGM_ALET_SPECIFICATION
- PGM_ALE_SEQUENCE
- PGM_ASCE_TYPE
- PGM_ASTE_INSTANCE
- PGM_ASTE_SEQUENCE
- PGM_ASTE_VALIDITY
- PGM_ASX_TRANSLATION
- PGM_CHECK
- PGM_CHECK_DEFAULT
- PGM_CMP
- PGM_CRYPTO_OPERATION
- PGM_DATA
- PGM_DECIMAL_DIVIDE
- PGM_DECIMAL_OVERFLOW
- PGM_EXECUTE
- PGM_EXTENDED_AUTHORITY
- PGM_EX_TRANSLATION
- PGM_FAIL
- PGM_FIXED_POINT_DIVIDE
- PGM_FIXED_POINT_OVERFLOW
- PGM_HFP_DIVIDE
- PGM_HFP_EXPONENT_OVERFLOW
- PGM_HFP_EXPONENT_UNDERFLOW
- PGM_HFP_SIGNIFICANCE
- PGM_HFP_SQUARE_ROOT
- PGM_LFX_TRANSLATION
- PGM_LSTE_SEQUENCE
- PGM_LSX_TRANSLATION
- PGM_LX_TRANSLATION
- PGM_MONITOR
- PGM_OPERAND
- PGM_OPERATION
- PGM_PAGE_TRANSLATION
- PGM_PC_TRANSLATION_SPEC
- PGM_PER
- PGM_PRIMARY_AUTHORITY
- PGM_PRIVILEGED_OP
- PGM_PROTECTION
- PGM_REGION_FIRST_TRANS
- PGM_REGION_SECOND_TRANS
- PGM_REGION_THIRD_TRANS
- PGM_SECONDARY_AUTHORITY
- PGM_SEGMENT_TRANSLATION
- PGM_SETUP
- PGM_SPACE_SWITCH
- PGM_SPECIAL_OPERATION
- PGM_SPECIFICATION
- PGM_STACK_EMPTY
- PGM_STACK_FULL
- PGM_STACK_OPERATION
- PGM_STACK_SPECIFICATION
- PGM_STACK_TYPE
- PGM_TRACE_TABEL
- PGM_TRANSLATION_SPEC
- PGM_VECTOR_PROCESSING
- PGOFFSET_4K
- PGOFFSET_64K
- PGOFF_LOFFT_MAX
- PGP
- PGPGIN
- PGPGOUT
- PGPKG_MAX_WORDS
- PGPKT_DATA_SIZE
- PGPKT_STRUCT
- PGPUEN
- PGPUEN_ADDR
- PGP_DIGEST_ALGO_SHA512
- PGP_MASK
- PGP_SHIFT
- PGRAPH_Def
- PGRAPH_Mask
- PGRAPH_Print
- PGRAPH_Read
- PGRAPH_Val
- PGRAPH_Write
- PGRDCMPL_EVT_STAT_LP_2K
- PGRDCMPL_EVT_STAT_LP_4K
- PGRDCMPL_EVT_STAT_MASK
- PGRDCMPL_EVT_STAT_SECTION_SP
- PGREFILL
- PGROTATED
- PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK_MASK
- PGRUNFEEDBACK_CPU_0__PG_RUNFEEDBACK__SHIFT
- PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK_MASK
- PGRUNFEEDBACK_CPU_1__PG_RUNFEEDBACK__SHIFT
- PGS
- PGSCAN_DIRECT
- PGSCAN_DIRECT_THROTTLE
- PGSCAN_KSWAPD
- PGSCAN_SKIP
- PGSCAN_ZONE_RECLAIM_FAILED
- PGSEL
- PGSEL_ADDR
- PGSPERIEXT
- PGSR
- PGSR0
- PGSR1
- PGSR2
- PGSR3
- PGSTEAL_DIRECT
- PGSTEAL_KSWAPD
- PGSTE_ACC_BITS
- PGSTE_FP_BIT
- PGSTE_GC_BIT
- PGSTE_GR_BIT
- PGSTE_HC_BIT
- PGSTE_HR_BIT
- PGSTE_IN_BIT
- PGSTE_PCL_BIT
- PGSTE_UC_BIT
- PGSTE_VSIE_BIT
- PGS_IN_2MB_PAGE
- PGS_MASK
- PGS_SHIFT
- PGT
- PGTABLE_EADDR_SIZE
- PGTABLE_HIGHMEM
- PGTABLE_PROT
- PGTABLE_RANGE
- PGTBL_ADDRESS_HI_MASK
- PGTBL_ADDRESS_LO_MASK
- PGTBL_CTL
- PGTBL_ER
- PGT_CACHE
- PGU
- PGU_MASK
- PGU_SHIFT
- PG_A0
- PG_AFTER_GRBM_REG_ST
- PG_AFTER_GRBM_REG_ST_MASK
- PG_ANY
- PG_BASE
- PG_BUSW_DTACK
- PG_BUSY
- PG_CLEAN
- PG_CNTL_ENABLE
- PG_COMMAND
- PG_COMMIT_TO_DS
- PG_CONTENDED1
- PG_CONTENDED2
- PG_DIRECT_MAP_1M
- PG_DIRECT_MAP_2G
- PG_DIRECT_MAP_4K
- PG_DIRECT_MAP_MAX
- PG_DIR_SIZE
- PG_DYNAMIC_MODE
- PG_ELPA
- PG_EMUBRK
- PG_EMUCS
- PG_EMUIRQ
- PG_ENABLE_MASK
- PG_ESP
- PG_HEADLOCK
- PG_HIZ_P_D
- PG_IEC
- PG_INODE_REF
- PG_LEVEL_1G
- PG_LEVEL_2M
- PG_LEVEL_4K
- PG_LEVEL_512G
- PG_LEVEL_NONE
- PG_LEVEL_NUM
- PG_MAGIC
- PG_MAJOR
- PG_MAPPED
- PG_MASK
- PG_MAX_DATA
- PG_MIG_INTR
- PG_NAME
- PG_NAMELEN
- PG_PKT_STRUCT_A
- PG_PMD_COLOUR
- PG_PMD_NR
- PG_POWER_DOWN
- PG_POWER_UP
- PG_PROC_DIR
- PG_PWMOUT
- PG_REMOVE
- PG_RESET
- PG_RESET_TMO
- PG_RIE
- PG_RTCOUT
- PG_SAFE
- PG_SEQ_DELAY_OVERRIDE_ENABLE
- PG_SEQ_DELAY_OVERRIDE_MASK
- PG_SEQ_DELAY_OVERRIDE_SHIFT
- PG_SHIFT_BIT
- PG_SHIFT_OFFSET
- PG_SIZE
- PG_SIZE_4K
- PG_SIZE_64K
- PG_SPIN
- PG_SPIN_DEL
- PG_STATE_DATA
- PG_STATE_HEADER
- PG_STATE_OFF
- PG_STATE_ON
- PG_STATE_RUNNING
- PG_STATE_WORD_0
- PG_STATE_WORD_1
- PG_STATE_WORD_2
- PG_STATE_WORD_3
- PG_STATIC_MODE
- PG_SWBYTE_H
- PG_SWBYTE_L
- PG_TEARDOWN
- PG_TIN1
- PG_TIN2
- PG_TMO
- PG_TOUT1
- PG_TOUT2
- PG_UART_RXD
- PG_UART_TXD
- PG_UNITS
- PG_UNLOCKPAGE
- PG_UNSAFE_CLEAR
- PG_UNSAFE_KEEP
- PG_UPTODATE
- PG_VERSION
- PG_VER_MASK
- PG_VER_OFFSET
- PG_WB_END
- PG_XIE
- PG_active
- PG_arch_1
- PG_buddy
- PG_checked
- PG_dc_clean
- PG_dcache_clean
- PG_dcache_cpu_mask
- PG_dcache_cpu_shift
- PG_dcache_dirty
- PG_dirty
- PG_double_map
- PG_error
- PG_foreign
- PG_fscache
- PG_guard
- PG_head
- PG_head_mask
- PG_hwpoison
- PG_idle
- PG_isolated
- PG_kmemcg
- PG_locked
- PG_lru
- PG_mappedtodisk
- PG_mlocked
- PG_offline
- PG_owner_priv_1
- PG_pinned
- PG_private
- PG_private_2
- PG_reclaim
- PG_referenced
- PG_reserved
- PG_savepinned
- PG_slab
- PG_slob_free
- PG_swapbacked
- PG_swapcache
- PG_table
- PG_uncached
- PG_unevictable
- PG_uptodate
- PG_waiters
- PG_workingset
- PG_writeback
- PG_xen_remapped
- PG_young
- PH
- PH0MD_0
- PH0MD_00
- PH0MD_01
- PH0MD_1
- PH0MD_10
- PH0MD_11
- PH0_DATA
- PH0_FN
- PH0_IN
- PH0_OUT
- PH1MD_0
- PH1MD_00
- PH1MD_01
- PH1MD_1
- PH1MD_10
- PH1MD_11
- PH1_DATA
- PH1_FN
- PH1_IN
- PH1_OUT
- PH2MD_0
- PH2MD_00
- PH2MD_01
- PH2MD_1
- PH2MD_10
- PH2MD_11
- PH2_DATA
- PH2_FN
- PH2_IN
- PH2_OUT
- PH3MD_0
- PH3MD_00
- PH3MD_01
- PH3MD_1
- PH3MD_10
- PH3MD_11
- PH3_DATA
- PH3_FN
- PH3_IN
- PH3_OUT
- PH4MD_0
- PH4MD_00
- PH4MD_01
- PH4MD_1
- PH4MD_10
- PH4MD_11
- PH4_DATA
- PH4_FN
- PH4_IN
- PH4_OUT
- PH5MD_0
- PH5MD_00
- PH5MD_01
- PH5MD_1
- PH5MD_10
- PH5MD_11
- PH5_DATA
- PH5_FN
- PH5_IN
- PH5_OUT
- PH6MD_0
- PH6MD_00
- PH6MD_01
- PH6MD_1
- PH6MD_10
- PH6MD_11
- PH6_DATA
- PH6_FN
- PH6_IN
- PH6_OUT
- PH7MD_0
- PH7MD_00
- PH7MD_01
- PH7MD_1
- PH7MD_10
- PH7MD_11
- PH7_DATA
- PH7_FN
- PH7_IN
- PH7_OUT
- PHACTRL_ADRS
- PHACTRL_PHASE_MANUAL
- PHAD_MAGIC
- PHAL_STATUS
- PHAL_VERSION
- PHAN0_MARK
- PHAN1_MARK
- PHAN2_MARK
- PHAN3_MARK
- PHAN4_MARK
- PHAN5_MARK
- PHAN6_MARK
- PHAN7_MARK
- PHANA
- PHANA_DEFAULT
- PHANDLE_BOTH
- PHANDLE_EPAPR
- PHANDLE_LEGACY
- PHANDLE_VALID
- PHANE
- PHANLPA
- PHANTOM_MAX_MINORS
- PHANTOM_VERSION
- PHAN_INITIALIZE_ACK
- PHAN_INITIALIZE_COMPLETE
- PHAN_INITIALIZE_FAILED
- PHAN_INITIALIZE_START
- PHAN_PEG_RCV_INITIALIZED
- PHAN_PEG_RCV_START_INITIALIZE
- PHASE
- PHASE1_LOOP_CNT
- PHASE1_LOOP_COUNT
- PHASE28_AC97_ADDR
- PHASE28_AC97_COMMIT
- PHASE28_AC97_DATA_HIGH
- PHASE28_AC97_DATA_LOW
- PHASE28_AC97_DATA_MASK
- PHASE28_AC97_RESET
- PHASE28_DIGITAL_SEL1
- PHASE28_HP_SEL
- PHASE28_SPI_CLK
- PHASE28_SPI_MISO
- PHASE28_SPI_MOSI
- PHASE28_WM_CS
- PHASE28_WM_RESET
- PHASE28_WM_RW
- PHASE2_EN
- PHASECHG
- PHASELATCH
- PHASEMASK
- PHASEMIS
- PHASEMISMATCH
- PHASES_MASK
- PHASES_SHIFT
- PHASE_ABORTED
- PHASE_CHANGE
- PHASE_CHANGE_IRQ
- PHASE_CMDOUT
- PHASE_COMMAND
- PHASE_COMMANDPAUSED
- PHASE_COMMON
- PHASE_CONNECTED
- PHASE_CONNECTING
- PHASE_DATAIN
- PHASE_DATAOUT
- PHASE_DECLARATIVE
- PHASE_DEVICE_DESC
- PHASE_DISCONNECT
- PHASE_DONE
- PHASE_ENGINE
- PHASE_FFP0
- PHASE_FIFO_CTL_INIT_MASK
- PHASE_FIFO_CTL_INIT_SHIFT
- PHASE_FIFO_CTL_RST_MASK
- PHASE_FIFO_CTL_RST_SHIFT
- PHASE_FREEZE_DLY_2_CL
- PHASE_FREEZE_DLY_4_CL
- PHASE_IDLE
- PHASE_INC_28MHZ
- PHASE_INC_49MHZ
- PHASE_INC_56MHZ
- PHASE_MASK
- PHASE_MESSAGESENT
- PHASE_MISMATCH
- PHASE_MM_INT
- PHASE_MSGIN
- PHASE_MSGIN_DISCONNECT
- PHASE_MSGOUT
- PHASE_MSGOUT_EXPECT
- PHASE_NOT_RESET
- PHASE_OFF_TOL_125
- PHASE_OFF_TOL_250
- PHASE_OPERATIONAL
- PHASE_OUT_OF_GUEST
- PHASE_PF
- PHASE_PF0
- PHASE_PF1
- PHASE_PF2
- PHASE_PF3
- PHASE_PF4
- PHASE_PF5
- PHASE_PF6
- PHASE_PF7
- PHASE_PORT
- PHASE_PORT0
- PHASE_PORT1
- PHASE_QM_PF
- PHASE_REALMODE
- PHASE_RECONNECTED
- PHASE_REF
- PHASE_RESET_LPCR
- PHASE_RESIDUAL
- PHASE_SECURITY
- PHASE_SELECTION
- PHASE_SELECT_MASK
- PHASE_SELSTEPS
- PHASE_SET_LPCR
- PHASE_SR_TO_TCR
- PHASE_STATIN
- PHASE_STATUS
- PHASE_STATUSIN
- PHASE_STEP_SHIFT
- PHASE_STEP_UNIT_SCALE
- PHASE_UNKNOWN
- PHASE_VF
- PHB3_TCE_KILL_INVAL_ALL
- PHB3_TCE_KILL_INVAL_ONE
- PHB3_TCE_KILL_INVAL_PE
- PHBS_PER_CALGARY
- PHB_AER_OFFSET
- PHB_CONFIG_0_END
- PHB_CONFIG_0_HIGH
- PHB_CONFIG_0_LOW
- PHB_CONFIG_RW_OFFSET
- PHB_CSR_OFFSET
- PHB_DAC_DISABLE
- PHB_DEBUG_STUFF_OFFSET
- PHB_DOSHOLE_OFFSET
- PHB_IOBASE_BAR_HIGH
- PHB_IOBASE_BAR_LOW
- PHB_IO_ADDR_SIZE
- PHB_IO_BASE
- PHB_IO_END
- PHB_MCSR_ENABLE
- PHB_MEM2_ENABLE
- PHB_MEM_1_HIGH
- PHB_MEM_1_LOW
- PHB_MEM_1_SIZE
- PHB_MEM_2_HIGH
- PHB_MEM_2_LOW
- PHB_MEM_2_SIZE_HIGH
- PHB_MEM_2_SIZE_LOW
- PHB_MEM_ST_OFFSET
- PHB_NOT_OH
- PHB_PAGE_MIG_CTRL
- PHB_PAGE_MIG_DEBUG
- PHB_PLSSR_OFFSET
- PHB_ROOT_COMPLEX_STATUS
- PHB_RUNNING
- PHB_SAVIOR_L2
- PHB_SET_NODE
- PHB_SLOT_DISABLE
- PHB_TCE_ENABLE
- PHC
- PHCLM_REG
- PHCLM_STOPSTATECKL
- PHCON1
- PHCON1_PDPXMD
- PHCON1_PLOOPBK
- PHCON1_PPWRSV
- PHCON1_PRST
- PHCON2
- PHCON2_FRCLINK
- PHCON2_HDLDIS
- PHCON2_JABBER
- PHCON2_TXDIS
- PHCTRLM_HIGH_SPEED
- PHCTRLM_REF_RATE
- PHC_MASK
- PHC_SHIFT
- PHDLM_REG
- PHDR
- PHDREN
- PHDR_TS_PEN_DOWN
- PHEERM_REG
- PHHID1
- PHHID2
- PHI
- PHIE
- PHIE_PGEIE
- PHIE_PLNKIE
- PHILIPS_MF_SET_STD_BG
- PHILIPS_MF_SET_STD_L
- PHILIPS_MF_SET_STD_LC
- PHILIPS_RF
- PHILIPS_SET_PAL_BGDK
- PHILIPS_SET_PAL_I
- PHILIPS_SET_PAL_L
- PHILIPS_SET_PAL_L2
- PHIMR_ATIMEND_E
- PHIMR_ATIM_CTW_END
- PHIMR_BCNDMAINT0
- PHIMR_BCNDMAINT1
- PHIMR_BCNDMAINT2
- PHIMR_BCNDMAINT3
- PHIMR_BCNDMAINT4
- PHIMR_BCNDMAINT5
- PHIMR_BCNDMAINT6
- PHIMR_BCNDMAINT7
- PHIMR_BCNDMAINT_E
- PHIMR_BCNDOK0
- PHIMR_BCNDOK1
- PHIMR_BCNDOK2
- PHIMR_BCNDOK3
- PHIMR_BCNDOK4
- PHIMR_BCNDOK5
- PHIMR_BCNDOK6
- PHIMR_BCNDOK7
- PHIMR_BEDOK
- PHIMR_BKDOK
- PHIMR_C2HCMD
- PHIMR_CPWM
- PHIMR_CPWM2
- PHIMR_GTINT3
- PHIMR_GTINT4
- PHIMR_HIGHDOK
- PHIMR_HISRE_IND
- PHIMR_HSISR_IND_ON
- PHIMR_MGNTDOK
- PHIMR_OCPINT
- PHIMR_PSTIMEOUT
- PHIMR_RDU
- PHIMR_ROK
- PHIMR_RXERR
- PHIMR_RXFOVW
- PHIMR_TIMEOUT1
- PHIMR_TIMEOUT2
- PHIMR_TSF_BIT32_TOGGLE
- PHIMR_TXBCNERR
- PHIMR_TXBCNOK
- PHIMR_TXERR
- PHIMR_TXFOVW
- PHIMR_VIDOK
- PHIMR_VODOK
- PHIR
- PHIR_PGEIF
- PHIR_PLNKIF
- PHLCON
- PHM_AutoThrottleSource
- PHM_AutoThrottleSource_External
- PHM_AutoThrottleSource_Thermal
- PHM_BackEnd_Magic
- PHM_CIslands_Magic
- PHM_Cz_Magic
- PHM_DispClock
- PHM_Dummy_Magic
- PHM_ENTIRE_REGISTER_MASK
- PHM_FIELD_MASK
- PHM_FIELD_SHIFT
- PHM_FUNC_CHECK
- PHM_GET_FIELD
- PHM_Kong_Magic
- PHM_Kv_Magic
- PHM_MAX_NUM_CAPS_BITS_PER_FIELD
- PHM_MAX_NUM_CAPS_ULONG_ENTRIES
- PHM_MemClock
- PHM_NIslands_Magic
- PHM_PerformanceLevel
- PHM_PerformanceLevelDesignation
- PHM_PerformanceLevelDesignation_Activity
- PHM_PerformanceLevelDesignation_PowerContainment
- PHM_PlatformCaps_ABM
- PHM_PlatformCaps_ACOverdriveSupport
- PHM_PlatformCaps_ACP
- PHM_PlatformCaps_AVFS
- PHM_PlatformCaps_AVFSSupport
- PHM_PlatformCaps_AcpDPM
- PHM_PlatformCaps_ActivityReporting
- PHM_PlatformCaps_AdjustUVDPriorityForSP
- PHM_PlatformCaps_AtomBiosPpV1
- PHM_PlatformCaps_AutoWattmanEnable_CCCState
- PHM_PlatformCaps_AutoWattmanSupport
- PHM_PlatformCaps_AutomaticDCTransition
- PHM_PlatformCaps_BACO
- PHM_PlatformCaps_BAMACO
- PHM_PlatformCaps_BBBSupported
- PHM_PlatformCaps_BLControlledByGPU
- PHM_PlatformCaps_BacklightSupport
- PHM_PlatformCaps_BiosPowerSourceControl
- PHM_PlatformCaps_BoostState
- PHM_PlatformCaps_BootStateOnAlert
- PHM_PlatformCaps_CAC
- PHM_PlatformCaps_ClockStretcher
- PHM_PlatformCaps_CombinePCCWithThermalSignal
- PHM_PlatformCaps_ConnectedStandby
- PHM_PlatformCaps_ContinuousHardwarePerformanceRange
- PHM_PlatformCaps_ControlVDDCI
- PHM_PlatformCaps_ControlVDDGFX
- PHM_PlatformCaps_CustomFanControlSupport
- PHM_PlatformCaps_CustomThermalPolicy
- PHM_PlatformCaps_DBRRamping
- PHM_PlatformCaps_DBRamping
- PHM_PlatformCaps_DTE
- PHM_PlatformCaps_DiDtEDCEnable
- PHM_PlatformCaps_DiDtSupport
- PHM_PlatformCaps_DisableDCODT
- PHM_PlatformCaps_DisableDPM
- PHM_PlatformCaps_DisableEngineTransition
- PHM_PlatformCaps_DisableLSClockGating
- PHM_PlatformCaps_DisableLightSleep
- PHM_PlatformCaps_DisableMCLS
- PHM_PlatformCaps_DisableMGCGTSSM
- PHM_PlatformCaps_DisableMGClockGating
- PHM_PlatformCaps_DisableMclkSwitchForVR
- PHM_PlatformCaps_DisableMclkSwitchingForFrameLock
- PHM_PlatformCaps_DisableMemoryTransition
- PHM_PlatformCaps_DisablePowerGating
- PHM_PlatformCaps_DisableSMUUVDHandshake
- PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc
- PHM_PlatformCaps_DisableVoltageIsland
- PHM_PlatformCaps_DisableVoltageTransition
- PHM_PlatformCaps_DontWaitForVBlankOnAlert
- PHM_PlatformCaps_DynamicACTiming
- PHM_PlatformCaps_DynamicM3Arbiter
- PHM_PlatformCaps_DynamicPCIEGen2Support
- PHM_PlatformCaps_DynamicPatchPowerState
- PHM_PlatformCaps_DynamicPowerManagement
- PHM_PlatformCaps_DynamicUVDState
- PHM_PlatformCaps_EVV
- PHM_PlatformCaps_EnableASPML0s
- PHM_PlatformCaps_EnableASPML1
- PHM_PlatformCaps_EnableBackbias
- PHM_PlatformCaps_EnableBoostState
- PHM_PlatformCaps_EnableDFSBypass
- PHM_PlatformCaps_EnableDriverEVV
- PHM_PlatformCaps_EnableHTLinkControl
- PHM_PlatformCaps_EnableLongIdleBACOSupport
- PHM_PlatformCaps_EnableMCUHTLinkControl
- PHM_PlatformCaps_EnableMVDDControl
- PHM_PlatformCaps_EnablePlatformPowerManagement
- PHM_PlatformCaps_EnableSCLKDeepSleepForUVD
- PHM_PlatformCaps_EnableSMU7ThermalManagement
- PHM_PlatformCaps_EnableShadowPstate
- PHM_PlatformCaps_EnableSideportControl
- PHM_PlatformCaps_EnableThermalIntByGPIO
- PHM_PlatformCaps_EnableVoltageControl
- PHM_PlatformCaps_EngineSpreadSpectrumSupport
- PHM_PlatformCaps_EvergreenChipsets
- PHM_PlatformCaps_ExclusiveModeAlwaysHigh
- PHM_PlatformCaps_FPS
- PHM_PlatformCaps_FPSEnhancement
- PHM_PlatformCaps_Falcon_QuickTransition
- PHM_PlatformCaps_FanSpeedInTableIsRPM
- PHM_PlatformCaps_FaultyInternalThermalReading
- PHM_PlatformCaps_Force3DClockSupport
- PHM_PlatformCaps_ForceMclkHigh
- PHM_PlatformCaps_FreeSyncActive
- PHM_PlatformCaps_GCEDC
- PHM_PlatformCaps_GFXClockGatingManagedInCAIL
- PHM_PlatformCaps_GFXClockGatingSupport
- PHM_PlatformCaps_GFXDynamicMGPowerGating
- PHM_PlatformCaps_GeminiAsymmetricPower
- PHM_PlatformCaps_GeminiPrimary
- PHM_PlatformCaps_GeminiRegulatorFanControlSupport
- PHM_PlatformCaps_IOIC3
- PHM_PlatformCaps_IPS_UlpsExclusive
- PHM_PlatformCaps_IcelandULPSSWWorkAround
- PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs
- PHM_PlatformCaps_KongThermalPolicy
- PHM_PlatformCaps_LoadPostProductionFirmware
- PHM_PlatformCaps_LowestUclkReservedForUlv
- PHM_PlatformCaps_MMClockGatingSupport
- PHM_PlatformCaps_Max
- PHM_PlatformCaps_MaxPCIEBandWidth
- PHM_PlatformCaps_MemorySpreadSpectrumSupport
- PHM_PlatformCaps_MicrocodeFanControl
- PHM_PlatformCaps_MultiUVDStateSupport
- PHM_PlatformCaps_NIChipsets
- PHM_PlatformCaps_NativeULPS
- PHM_PlatformCaps_NewCACVoltage
- PHM_PlatformCaps_NoOD5Support
- PHM_PlatformCaps_NonABMSupportInPPLib
- PHM_PlatformCaps_OCLPowerOptimization
- PHM_PlatformCaps_OD5inACSupport
- PHM_PlatformCaps_OD5inDCSupport
- PHM_PlatformCaps_OD6PlusinACSupport
- PHM_PlatformCaps_OD6PlusinDCSupport
- PHM_PlatformCaps_OD6inACSupport
- PHM_PlatformCaps_OD6inDCSupport
- PHM_PlatformCaps_OD8inACSupport
- PHM_PlatformCaps_OD8inDCSupport
- PHM_PlatformCaps_ODFuzzyFanControlSupport
- PHM_PlatformCaps_ODNinACSupport
- PHM_PlatformCaps_ODNinDCSupport
- PHM_PlatformCaps_ODThermalLimitUnlock
- PHM_PlatformCaps_OverdriveDisabledByPowerBudget
- PHM_PlatformCaps_PCIEPerformanceRequest
- PHM_PlatformCaps_PSM
- PHM_PlatformCaps_PauseMMSessions
- PHM_PlatformCaps_PerfPerWattOptimizationSupport
- PHM_PlatformCaps_PerformanceStateOnly
- PHM_PlatformCaps_PowerBudgetWaiverAvailable
- PHM_PlatformCaps_PowerContainment
- PHM_PlatformCaps_PowerControl
- PHM_PlatformCaps_PowerPlaySupport
- PHM_PlatformCaps_ReducePowerLimit
- PHM_PlatformCaps_RegWriteDelay
- PHM_PlatformCaps_RegulatorHot
- PHM_PlatformCaps_RevertGPIO5Polarity
- PHM_PlatformCaps_SMC
- PHM_PlatformCaps_SMCAllowSeparateSWThermalState
- PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme
- PHM_PlatformCaps_SMU7
- PHM_PlatformCaps_SMU8
- PHM_PlatformCaps_SPLLShutdownSupport
- PHM_PlatformCaps_SQRamping
- PHM_PlatformCaps_SamuDPM
- PHM_PlatformCaps_SamuPowerGating
- PHM_PlatformCaps_SclkDeepSleep
- PHM_PlatformCaps_SclkDeepSleepAboveLow
- PHM_PlatformCaps_SclkThrottleLowNotification
- PHM_PlatformCaps_ShowPowerBudgetWarning
- PHM_PlatformCaps_SoftStateOD5
- PHM_PlatformCaps_StablePState
- PHM_PlatformCaps_StayInBootState
- PHM_PlatformCaps_StepVddc
- PHM_PlatformCaps_SumoThermalPolicy
- PHM_PlatformCaps_SurpriseRemoval
- PHM_PlatformCaps_SwitchVDDNB
- PHM_PlatformCaps_TCPRamping
- PHM_PlatformCaps_TDRamping
- PHM_PlatformCaps_TablelessHardwareInterface
- PHM_PlatformCaps_TempInversion
- PHM_PlatformCaps_Thermal2GPIO17
- PHM_PlatformCaps_ThermalAutoThrottling
- PHM_PlatformCaps_ThermalController
- PHM_PlatformCaps_ThermalOutGPIO
- PHM_PlatformCaps_ThermalPolicyDelay
- PHM_PlatformCaps_TrinityChipsets
- PHM_PlatformCaps_TurnOffPll_ASPML1
- PHM_PlatformCaps_ULPS
- PHM_PlatformCaps_UMDPState
- PHM_PlatformCaps_UVDAlwaysHigh
- PHM_PlatformCaps_UVDClientMCTuning
- PHM_PlatformCaps_UVDDPM
- PHM_PlatformCaps_UVDDynamicPowerGating
- PHM_PlatformCaps_UVDPowerGating
- PHM_PlatformCaps_UnTabledHardwareInterface
- PHM_PlatformCaps_UseDummyBackEnd
- PHM_PlatformCaps_UserMaxClockForMultiDisplays
- PHM_PlatformCaps_VCEDPM
- PHM_PlatformCaps_VCEPowerGating
- PHM_PlatformCaps_VRHotGPIOConfigurable
- PHM_PlatformCaps_VRHotPolarityHigh
- PHM_PlatformCaps_VddNBDirectRequest
- PHM_PlatformCaps_VideoPlaybackEEUNotification
- PHM_PlatformCaps_VirtualBatteryState
- PHM_PlatformCaps_Virtual_System
- PHM_PlatformCaps_VpuRecoveryInProgress
- PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE
- PHM_PlatformCaps_WantACPClkWithDummyBackEnd
- PHM_PlatformCaps_WantSAMClkWithDummyBackEnd
- PHM_PlatformCaps_WantUVDClkWithDummyBackEnd
- PHM_PlatformCaps_WantVCEClkWithDummyBackEnd
- PHM_PlatformCaps_XDMAEnabled
- PHM_PlatformCaps_customThermalManagement
- PHM_PlatformCaps_staticFanControl
- PHM_READ_FIELD
- PHM_READ_INDIRECT_FIELD
- PHM_READ_VFPF_INDIRECT_FIELD
- PHM_RV770_Magic
- PHM_Rv_Magic
- PHM_SClock
- PHM_SET_FIELD
- PHM_SIslands_Magic
- PHM_Sumo_Magic
- PHM_Trinity_Magic
- PHM_VIslands_Magic
- PHM_WAIT_FIELD_UNEQUAL
- PHM_WAIT_INDIRECT_FIELD
- PHM_WAIT_INDIRECT_FIELD_UNEQUAL
- PHM_WAIT_INDIRECT_REGISTER
- PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL
- PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX
- PHM_WAIT_REGISTER_UNEQUAL
- PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX
- PHM_WAIT_VFPF_INDIRECT_FIELD
- PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL
- PHM_WAIT_VFPF_INDIRECT_REGISTER
- PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL
- PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX
- PHM_WRITE_FIELD
- PHM_WRITE_INDIRECT_FIELD
- PHM_WRITE_VFPF_INDIRECT_FIELD
- PHN_CONTROL
- PHN_CTL_AMP
- PHN_CTL_BUT
- PHN_CTL_IRQ
- PHN_FUSERX_MISC_FUSES__CoreDis_MASK
- PHN_FUSERX_MISC_FUSES__CoreDis__SHIFT
- PHN_FUSERX_MISC_FUSES__MemPstate_MASK
- PHN_FUSERX_MISC_FUSES__MemPstate__SHIFT
- PHN_FUSERX_MISC_FUSES__NbPstateHi_MASK
- PHN_FUSERX_MISC_FUSES__NbPstateHi__SHIFT
- PHN_FUSERX_MISC_FUSES__NbPstateLo_MASK
- PHN_FUSERX_MISC_FUSES__NbPstateLo__SHIFT
- PHN_FUSERX_MISC_FUSES__OverClockRefClkDis_MASK
- PHN_FUSERX_MISC_FUSES__OverClockRefClkDis__SHIFT
- PHN_FUSERX_MISC_FUSES__PHN_FusesValid_MASK
- PHN_FUSERX_MISC_FUSES__PHN_FusesValid__SHIFT
- PHN_FUSERX_MISC_FUSES__ScanCLK400MHz_MASK
- PHN_FUSERX_MISC_FUSES__ScanCLK400MHz__SHIFT
- PHN_FUSERX_MISC_FUSES__Spare_MASK
- PHN_FUSERX_MISC_FUSES__Spare__SHIFT
- PHN_GETREG
- PHN_GETREGS
- PHN_GET_REG
- PHN_GET_REGS
- PHN_IRQCTL
- PHN_NOT_OH
- PHN_SETREG
- PHN_SETREGS
- PHN_SET_REG
- PHN_SET_REGS
- PHN_ZERO_FORCE
- PHONET_DEV_MTU
- PHONET_MAX_MTU
- PHONET_MIN_MTU
- PHONET_NPROTO
- PHONE_MAJOR
- PHOTO_FRAME_MODE
- PHREG_MASK
- PHSTAT1
- PHSTAT1_JBSTAT
- PHSTAT1_LLSTAT
- PHSTAT1_PFDPX
- PHSTAT1_PHDPX
- PHSTAT2
- PHSTAT2_COLSTAT
- PHSTAT2_DPXSTAT
- PHSTAT2_LSTAT
- PHSTAT2_PLRITY
- PHSTAT2_RXSTAT
- PHSTAT2_TXSTAT
- PHSTAT3
- PHSTATM_PLL_LOCKED
- PHS_COMMAND
- PHS_DATA_IN
- PHS_DATA_OUT
- PHS_MESS_IN
- PHS_MESS_OUT
- PHS_STATUS
- PHSync
- PHTC_REG
- PHTC_TESTCLR
- PHTIOT_PEER_E
- PHTW_CWEN
- PHTW_DWEN
- PHTW_REG
- PHTW_TESTDIN_CODE
- PHTW_TESTDIN_DATA
- PHT_AGGRE_MODE_E
- PHT_AGGRE_SIZE_E
- PHT_INFORMATION_ELE
- PHT_IOT_ACTION_E
- PHT_SPEC_VER
- PHUB_CONTROL
- PHUB_STATUS
- PHUB_TIMEOUT
- PHV_LLD_SCSI_HOST_NO
- PHV_REFERENCE_TSC_PAGE
- PHV_VIRTUAL_HOST_ID
- PHY
- PHY0_BIST_LOOP
- PHY0_CNTRL
- PHY0_RESET_N
- PHY0_RX_ALIGN
- PHY0_RX_EQ_HI
- PHY0_RX_EQ_LO
- PHY0_STAT
- PHY1000AbilityMask
- PHY1_BIST_LOOP
- PHY1_CNTRL
- PHY1_RESET_N
- PHY1_RX_ALIGN
- PHY1_RX_EQ_HI
- PHY1_RX_EQ_LO
- PHY1_STAT
- PHY2_RESET_N
- PHY3DPX
- PHY3SPD100
- PHY3_RESET_N
- PHY84833_CONSTANT_LATENCY
- PHY84833_MB_PROCESS1
- PHY84833_MB_PROCESS2
- PHY84833_MB_PROCESS3
- PHY84833_STATUS_CMD_CLEAR_COMPLETE
- PHY84833_STATUS_CMD_COMPLETE_ERROR
- PHY84833_STATUS_CMD_COMPLETE_PASS
- PHY84833_STATUS_CMD_IN_PROGRESS
- PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS
- PHY84833_STATUS_CMD_OPEN_FOR_CMDS
- PHY84833_STATUS_CMD_OPEN_OVERRIDE
- PHY84833_STATUS_CMD_RECEIVED
- PHY84833_STATUS_CMD_SYSTEM_BOOT
- PHY84858_STATUS_CMD_COMPLETE_ERROR
- PHY84858_STATUS_CMD_COMPLETE_PASS
- PHY84858_STATUS_CMD_IN_PROGRESS
- PHY84858_STATUS_CMD_RECEIVED
- PHY84858_STATUS_CMD_SYSTEM_BUSY
- PHY848xx_CMDHDLR_MAX_ARGS
- PHY848xx_CMDHDLR_WAIT
- PHY848xx_CMD_GET_EEE_MODE
- PHY848xx_CMD_SET_EEE_MODE
- PHY848xx_CMD_SET_PAIR_SWAP
- PHYACC_ATTR_BANK_AFE
- PHYACC_ATTR_BANK_MAX
- PHYACC_ATTR_BANK_MISC
- PHYACC_ATTR_BANK_PCS
- PHYACC_ATTR_BANK_SMI
- PHYACC_ATTR_MODE_MODIFY
- PHYACC_ATTR_MODE_READ
- PHYACC_ATTR_MODE_WRITE
- PHYADD
- PHYADDR
- PHYAD_MASK
- PHYAD_SHIFT
- PHYAR
- PHYAR_FLAG
- PHYAbletoPerform1000FullDuplex
- PHYAbletoPerform1000HalfDuplex
- PHYCFG_OFS
- PHYCLKRST_COMMONONN
- PHYCLKRST_EN_UTMISUSPEND
- PHYCLKRST_FSEL
- PHYCLKRST_FSEL_PAD_100MHZ
- PHYCLKRST_FSEL_PAD_19_2MHZ
- PHYCLKRST_FSEL_PAD_20MHZ
- PHYCLKRST_FSEL_PAD_24MHZ
- PHYCLKRST_FSEL_PIPE_MASK
- PHYCLKRST_FSEL_UTMI_MASK
- PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF
- PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF
- PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF
- PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF
- PHYCLKRST_MPLL_MULTIPLIER_50M_REF
- PHYCLKRST_MPLL_MULTIPLIER_MASK
- PHYCLKRST_PORTRESET
- PHYCLKRST_REFCLKSEL_EXT_REFCLK
- PHYCLKRST_REFCLKSEL_MASK
- PHYCLKRST_REFCLKSEL_PAD_REFCLK
- PHYCLKRST_REF_CLKDIV2
- PHYCLKRST_REF_SSP_EN
- PHYCLKRST_RETENABLEN
- PHYCLKRST_SSC_EN
- PHYCLKRST_SSC_RANGE
- PHYCLKRST_SSC_RANGE_MASK
- PHYCLKRST_SSC_REFCLKSEL
- PHYCLKRST_SSC_REFCLKSEL_MASK
- PHYCLK_DPTX_PHY_CH0_TXD_CLK
- PHYCLK_DPTX_PHY_CH1_TXD_CLK
- PHYCLK_DPTX_PHY_CH2_TXD_CLK
- PHYCLK_DPTX_PHY_CH3_TXD_CLK
- PHYCLK_DPTX_PHY_CLK_DIV2
- PHYCLK_DPTX_PHY_O_REF_CLK_24M
- PHYCLK_HDMI_LINK_O_TMDS_CLKHI
- PHYCLK_HDMI_PHY_PIXEL_CLKO
- PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0
- PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS
- PHYCLK_UFS20_RX0_SYMBOL
- PHYCLK_UFS20_RX0_SYMBOL_USER
- PHYCLK_UFS20_RX1_SYMBOL
- PHYCLK_UFS20_RX1_SYMBOL_USER
- PHYCLK_UFS20_TX0_SYMBOL
- PHYCLK_UFS20_TX0_SYMBOL_USER
- PHYCLK_USBDRD300_UDRD30_PHYCLK_USER
- PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER
- PHYCLK_USBDRD30_UDRD30_PHYCLOCK
- PHYCLK_USBDRD30_UDRD30_PIPE_PCLK
- PHYCLK_USBHOST20_PHY_CLK48MOHCI
- PHYCLK_USBHOST20_PHY_FREECLK
- PHYCLK_USBHOST20_PHY_PHYCLOCK
- PHYCNT
- PHYCNT_ENABLECLK
- PHYCNT_ENABLE_0
- PHYCNT_ENABLE_1
- PHYCNT_ENABLE_2
- PHYCNT_ENABLE_3
- PHYCNT_REG
- PHYCNT_RSTZ
- PHYCNT_SHUTDOWNZ
- PHYCONF_HAS
- PHYCONF_IS
- PHYCR2
- PHYCTL_DATA
- PHYCTRLCFG
- PHYCTRL_BSEN
- PHYCTRL_BSENH
- PHYCTRL_CALDONE_DONE
- PHYCTRL_CALDONE_GOING
- PHYCTRL_CALDONE_MASK
- PHYCTRL_CALDONE_SHIFT
- PHYCTRL_DLLRDY_DONE
- PHYCTRL_DLLRDY_GOING
- PHYCTRL_DLLRDY_MASK
- PHYCTRL_DLLRDY_SHIFT
- PHYCTRL_DR_100OHM
- PHYCTRL_DR_33OHM
- PHYCTRL_DR_40OHM
- PHYCTRL_DR_50OHM
- PHYCTRL_DR_66OHM
- PHYCTRL_DR_MASK
- PHYCTRL_DR_SHIFT
- PHYCTRL_DWS_RESET_MSK
- PHYCTRL_ENDLL_DISABLE
- PHYCTRL_ENDLL_ENABLE
- PHYCTRL_ENDLL_MASK
- PHYCTRL_ENDLL_SHIFT
- PHYCTRL_FREQSEL_100M
- PHYCTRL_FREQSEL_150M
- PHYCTRL_FREQSEL_200M
- PHYCTRL_FREQSEL_50M
- PHYCTRL_FREQSEL_MASK
- PHYCTRL_FREQSEL_SHIFT
- PHYCTRL_IS_CALDONE
- PHYCTRL_IS_DLLRDY
- PHYCTRL_LSFE
- PHYCTRL_NOT_RDY_MSK
- PHYCTRL_OOB_RESTART_MSK
- PHYCTRL_OTAPDLYENA
- PHYCTRL_OTAPDLYENA_MASK
- PHYCTRL_OTAPDLYENA_SHIFT
- PHYCTRL_OTAPDLYSEL_MASK
- PHYCTRL_OTAPDLYSEL_SHIFT
- PHYCTRL_PDB_MASK
- PHYCTRL_PDB_PWR_OFF
- PHYCTRL_PDB_PWR_ON
- PHYCTRL_PDB_SHIFT
- PHYCTRL_PHYE
- PHYCTRL_PHY_ENA_MSK
- PHYCTRL_PXE
- PHYCTRL_REG
- PHYCTRL_SLEW_UP
- PHYCTRL_ULPS_EXIT
- PHYCTRL_VREG_LP
- PHYDAT
- PHYDATA0
- PHYDATA1
- PHYDATAR
- PHYDM_INFO_SET_CUT_VER
- PHYDM_INFO_SET_REF_TYPE
- PHYDM_INFO_SET_RF_TYPE
- PHYDM_INFO_SET_RX_ANT_STATUS
- PHYDM_INFO_SET_TX_ANT_STATUS
- PHYDPX
- PHYD_CTRL_SIGNAL_MODE4
- PHYD_DESIGN_OPTION2
- PHYD_DESIGN_OPTION9
- PHYERR_TLV_SIG
- PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY
- PHYERR_TLV_TAG_SEARCH_FFT_REPORT
- PHYERR_TLV_TAG_SPECTRAL_SUMMARY_REPORT
- PHYEV_AN
- PHYEV_BIST_ACT
- PHYEV_BROAD_CH
- PHYEV_COMWAKE
- PHYEV_CRC_ERR
- PHYEV_DCDR_ERR
- PHYEV_DEC_ERR
- PHYEV_HARD_RST
- PHYEV_HARD_RST_DONE
- PHYEV_ID_DONE
- PHYEV_ID_FAIL
- PHYEV_ID_TMOUT
- PHYEV_IU_BIG
- PHYEV_IU_SMALL
- PHYEV_POOF
- PHYEV_PORT_SEL
- PHYEV_RDY_CH
- PHYEV_SIG_FIS
- PHYEV_UNASSOC_FIS
- PHYEV_UNK_TAG
- PHYE_LOSS_OF_SIGNAL
- PHYE_OOB_DONE
- PHYE_OOB_ERROR
- PHYE_RESUME_TIMEOUT
- PHYE_SHUTDOWN
- PHYE_SPINUP_HOLD
- PHYID1_OUI_MASK
- PHYID1_OUI_SHFT
- PHYID2_MODEL_MASK
- PHYID2_OUI_MASK
- PHYID2_OUI_SHFT
- PHYIDENTIFIER
- PHYID_AM79C874
- PHYID_CICADA_CS8201
- PHYID_GET_PHY_ID
- PHYID_ICPLUS_IP101A
- PHYID_MARVELL_1000
- PHYID_MARVELL_1000S
- PHYID_REV_ID_MASK
- PHYID_VT3216_32BIT
- PHYID_VT3216_64BIT
- PHYLD_0
- PHYLD_1
- PHYLD_2
- PHYLD_3
- PHYLD_4
- PHYLD_5
- PHYLD_6
- PHYLD_7
- PHYLD_8
- PHYLD_9
- PHYLD_COUNT
- PHYLD_UNKNOWN
- PHYLINK_DEV
- PHYLINK_DISABLE_LINK
- PHYLINK_DISABLE_STOPPED
- PHYLINK_NETDEV
- PHYLNK
- PHYPARAM0_REF_LOSLEVEL
- PHYPARAM0_REF_LOSLEVEL_MASK
- PHYPARAM0_REF_USE_PAD
- PHYPARAM1_PCS_TXDEEMPH
- PHYPARAM1_PCS_TXDEEMPH_MASK
- PHYPARAM_REG
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLL_HSFREQRANGE
- PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK_MASK
- PHYPLL_PIXCLK_CNTL__DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK__SHIFT
- PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE_MASK
- PHYPLL_PIXCLK_CNTL__PHYPLL_PIXCLK_RESYNC_ENABLE__SHIFT
- PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL_MASK
- PHYPLL_PIXCLK_CNTL__PIXEL_RATE_PHYPLL_SEL__SHIFT
- PHYPLL_REG
- PHYPLL_WAIT_US
- PHYRDY
- PHYRDY_CYCLES
- PHYREG0_CR_CAP_ADDR
- PHYREG0_CR_CAP_DATA
- PHYREG0_CR_DATA_IN
- PHYREG0_CR_READ
- PHYREG0_CR_WRITE
- PHYREG0_SSC_RANGE
- PHYREG0_SSC_REF_CLK_SEL
- PHYREG1_CR_ACK
- PHYREG1_CR_DATA_OUT
- PHYREGS
- PHYRWCTL
- PHYR_ADDR_HI
- PHYR_ADDR_LO
- PHYR_ATT_ADDR_HI
- PHYR_ATT_ADDR_LO
- PHYR_ATT_DEV_INFO
- PHYR_CRC_ERR_COUNT
- PHYR_CURRENT0
- PHYR_CURRENT1
- PHYR_CURRENT2
- PHYR_IDENTIFY
- PHYR_PHY_STAT
- PHYR_R_ERR_COUNT
- PHYR_SATA_CTL
- PHYR_SATA_SIG0
- PHYR_SATA_SIG1
- PHYR_SATA_SIG2
- PHYR_SATA_SIG3
- PHYR_WIDE_PORT
- PHYS
- PHYSDEVOP_APIC_READ
- PHYSDEVOP_APIC_WRITE
- PHYSDEVOP_ASSIGN_VECTOR
- PHYSDEVOP_DBGP_BUS_PCI
- PHYSDEVOP_DBGP_BUS_UNKNOWN
- PHYSDEVOP_DBGP_RESET_DONE
- PHYSDEVOP_DBGP_RESET_PREPARE
- PHYSDEVOP_FREE_VECTOR
- PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY
- PHYSDEVOP_IRQ_SHARED
- PHYSDEVOP_IRQ_STATUS_QUERY
- PHYSDEVOP_IRQ_UNMASK_NOTIFY
- PHYSDEVOP_SET_IOBITMAP
- PHYSDEVOP_SET_IOPL
- PHYSDEVOP_alloc_irq_vector
- PHYSDEVOP_apic_read
- PHYSDEVOP_apic_write
- PHYSDEVOP_dbgp_op
- PHYSDEVOP_eoi
- PHYSDEVOP_free_irq_vector
- PHYSDEVOP_get_free_pirq
- PHYSDEVOP_get_nr_pirqs
- PHYSDEVOP_irq_status_query
- PHYSDEVOP_manage_pci_add
- PHYSDEVOP_manage_pci_add_ext
- PHYSDEVOP_manage_pci_remove
- PHYSDEVOP_map_pirq
- PHYSDEVOP_pci_device_add
- PHYSDEVOP_pci_device_remove
- PHYSDEVOP_pci_mmcfg_reserved
- PHYSDEVOP_pirq_eoi_gmfn_v1
- PHYSDEVOP_pirq_eoi_gmfn_v2
- PHYSDEVOP_prepare_msix
- PHYSDEVOP_release_msix
- PHYSDEVOP_restore_msi
- PHYSDEVOP_restore_msi_ext
- PHYSDEVOP_set_iobitmap
- PHYSDEVOP_set_iopl
- PHYSDEVOP_setup_gsi
- PHYSDEVOP_unmap_pirq
- PHYSDEV_CONTROL_DD_MASK
- PHYSDEV_CONTROL_FW_RESET_MASK
- PHYSDEV_CONTROL_INP_MASK
- PHYSDEV_CONTROL_OFFSET
- PHYSDSGL_MAX_LEN_SIZE
- PHYSEL
- PHYSEL_LINKINT
- PHYSEL_LINKSEL
- PHYSICAL
- PHYSICAL_ADDRESS_LOC
- PHYSICAL_DRIVE
- PHYSICAL_ID
- PHYSICAL_LINK_STATUS
- PHYSICAL_MODE_ENTER
- PHYSICAL_NODE_NAME_SIZE
- PHYSICAL_NODE_STRING
- PHYSICAL_OFFSET
- PHYSICAL_PAGE_MASK
- PHYSICAL_PMD_PAGE_MASK
- PHYSICAL_PUD_PAGE_MASK
- PHYSICAL_START
- PHYSID_ARRAY_SIZE
- PHYSID_MASK_ALL
- PHYSID_MASK_NONE
- PHYSLINK_UPDATE_NONE
- PHYSLINK_UPDATE_STATE
- PHYSLINK_UPDATE_STATE_ACK
- PHYSLINK_UPDATE_STATE_NACK
- PHYSP_CTRL_ASSERT_CRS_TX
- PHYSR0_FDPX
- PHYSR0_LINKGD
- PHYSR0_PHYRST
- PHYSR0_RXFLC
- PHYSR0_SPD10
- PHYSR0_SPDG
- PHYSR0_TXFLC
- PHYSR1_PHYTBI
- PHYSTATUS
- PHYSTS_CHG
- PHYSTS_CHG_M
- PHYS_ADDR_MASK
- PHYS_ADDR_MASK29
- PHYS_ADDR_MASK32
- PHYS_ADDR_MAX
- PHYS_ADDR_ONLY
- PHYS_BAT_ADDR
- PHYS_CPUID_INVALID
- PHYS_DMAC_BLOCK
- PHYS_EMI_BLOCK
- PHYS_EMI_CBLOCK
- PHYS_EMI_DBLOCK
- PHYS_EPBR_BLOCK
- PHYS_ETH_SELF_CTL
- PHYS_FEMI_CBLOCK
- PHYS_FEMI_DBLOCK
- PHYS_IMMR_BASE
- PHYS_INT_VER_REG
- PHYS_L2CACHE_NUM_WAYS
- PHYS_MASK
- PHYS_MASK_SHIFT
- PHYS_OFFSET
- PHYS_OFFSET_OFFSET
- PHYS_PBR_BLOCK
- PHYS_PCI_BLOCK
- PHYS_PERIPHERAL_BLOCK
- PHYS_PER_CHANNEL
- PHYS_PFN
- PHYS_PFN_OFFSET
- PHYS_RAMBASE
- PHYS_RELATIVE
- PHYS_TO_COMPATK1
- PHYS_TO_IO
- PHYS_TO_K0
- PHYS_TO_XKPHYS
- PHYS_TO_XKSEG_CACHED
- PHYS_TO_XKSEG_UNCACHED
- PHYS_TWIDDLE
- PHYS_UART_DATA
- PHYS_UART_FLAG
- PHYS_UDCDN
- PHYS_WATCHPOINT
- PHYTEST_POWERDOWN_HSP
- PHYTEST_POWERDOWN_SSP
- PHYTIMING_CLK_POST
- PHYTIMING_CLK_PREPARE
- PHYTIMING_CLK_TRAIL
- PHYTIMING_CLK_ZERO
- PHYTIMING_HS_EXIT
- PHYTIMING_HS_PREPARE
- PHYTIMING_HS_TRAIL
- PHYTIMING_HS_ZERO
- PHYTIMING_LPX
- PHYTMSR_TST_JSTA
- PHYTMSR_TST_KSTA
- PHYTMSR_TST_PKT
- PHYTMSR_TST_SE0NAK
- PHYTMSR_UNPLUG
- PHYTYPE
- PHYTYPE_11N_CAP
- PHYTYPE_IS
- PHYUTMICLKSEL_UTMI_CLKSEL
- PHYUTMI_FORCESLEEP
- PHYUTMI_FORCESUSPEND
- PHYUTMI_OTGDISABLE
- PHYXS_RESET_LBN
- PHYXS_RESET_WIDTH
- PHYXS_TEST1
- PHYXS_XCONTROL_REG
- PHYXS_XGXS_LANE_STAT_ALINGED
- PHYXS_XGXS_LANE_STAT_LANE0
- PHYXS_XGXS_LANE_STAT_LANE1
- PHYXS_XGXS_LANE_STAT_LANE2
- PHYXS_XGXS_LANE_STAT_LANE3
- PHYXS_XGXS_LANE_STAT_MAGIC
- PHYXS_XGXS_LANE_STAT_PATTEST
- PHY_100
- PHY_1000
- PHY_1000BT_FEATURES
- PHY_1000T_CTRL
- PHY_1000T_CTRL_DEFAULT
- PHY_1000T_STATUS
- PHY_100BT4_CAPABLE
- PHY_100BTX_CAPABLE
- PHY_100BTX_FD_CAPABLE
- PHY_100BT_FEATURES
- PHY_10BT_CAPABLE
- PHY_10BT_FD_CAPABLE
- PHY_10BT_FEATURES
- PHY_10GBIT_FEATURES
- PHY_10GBIT_FEC_FEATURES
- PHY_10GBIT_FULL_FEATURES
- PHY_14NM_CKLN_IDX
- PHY_16_JAB_ENB
- PHY_16_PORT_ENB
- PHY_28NM_CAL_REG
- PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28
- PHY_28NM_CHGDTC_CDP_EN_SHIFT_28
- PHY_28NM_CHGDTC_DCP_EN_SHIFT_28
- PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28
- PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28
- PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28
- PHY_28NM_CHGDTC_PD_EN_SHIFT_28
- PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28
- PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28
- PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28
- PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28
- PHY_28NM_CHRG_DET
- PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28
- PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28
- PHY_28NM_CTRL3_AVALID
- PHY_28NM_CTRL3_BVALID
- PHY_28NM_CTRL3_OVERWRITE
- PHY_28NM_CTRL3_VBUS_VALID
- PHY_28NM_CTRL_REG0
- PHY_28NM_CTRL_REG1
- PHY_28NM_CTRL_REG2
- PHY_28NM_CTRL_REG3
- PHY_28NM_DIG_BITSTAFFING_ERR
- PHY_28NM_DIG_REG0
- PHY_28NM_DIG_REG1
- PHY_28NM_DIG_SQ_BLK_MASK
- PHY_28NM_DIG_SQ_BLK_SHIFT
- PHY_28NM_DIG_SQ_FILT_MASK
- PHY_28NM_DIG_SQ_FILT_SHIFT
- PHY_28NM_DIG_SYNC_ERR
- PHY_28NM_DIG_SYNC_NUM_MASK
- PHY_28NM_DIG_SYNC_NUM_SHIFT
- PHY_28NM_HSIC_CONNECT_INT
- PHY_28NM_HSIC_CTRL
- PHY_28NM_HSIC_H2S_IMPCAL_DONE
- PHY_28NM_HSIC_H2S_PLL_LOCK
- PHY_28NM_HSIC_HS_READY_INT
- PHY_28NM_HSIC_IMPCAL_CAL
- PHY_28NM_HSIC_INT
- PHY_28NM_HSIC_PLL_CTRL01
- PHY_28NM_HSIC_PLL_CTRL2
- PHY_28NM_HSIC_PLL_FBDIV_SHIFT
- PHY_28NM_HSIC_PLL_REFDIV_SHIFT
- PHY_28NM_HSIC_PLL_SELLPFR_SHIFT
- PHY_28NM_HSIC_S2H_HSIC_EN
- PHY_28NM_HSIC_S2H_PU_PLL
- PHY_28NM_IMPCAL_START_SHIFT
- PHY_28NM_IMPCAL_VTH_MASK
- PHY_28NM_IMPCAL_VTH_SHIFT
- PHY_28NM_MOC_REG
- PHY_28NM_OTG_CONTROL_BY_PIN
- PHY_28NM_OTG_PU_OTG
- PHY_28NM_OTG_REG
- PHY_28NM_PHY_RESERVE
- PHY_28NM_PLLCAL_START_SHIFT
- PHY_28NM_PLL_CAL12_MASK
- PHY_28NM_PLL_CAL12_SHIFT
- PHY_28NM_PLL_FBDIV_MASK
- PHY_28NM_PLL_FBDIV_SHIFT
- PHY_28NM_PLL_ICP_MASK
- PHY_28NM_PLL_ICP_SHIFT
- PHY_28NM_PLL_IMPCAL_DONE
- PHY_28NM_PLL_KVCO_MASK
- PHY_28NM_PLL_KVCO_SHIFT
- PHY_28NM_PLL_LOCK_BYPASS
- PHY_28NM_PLL_PLLCAL_DONE
- PHY_28NM_PLL_PU_BY_REG
- PHY_28NM_PLL_PU_PLL
- PHY_28NM_PLL_READY
- PHY_28NM_PLL_REFDIV_MASK
- PHY_28NM_PLL_REFDIV_SHIFT
- PHY_28NM_PLL_REG0
- PHY_28NM_PLL_REG1
- PHY_28NM_PLL_SELLPFR_MASK
- PHY_28NM_PLL_SELLPFR_SHIFT
- PHY_28NM_RX_REG0
- PHY_28NM_RX_REG1
- PHY_28NM_RX_SQCAL_DONE
- PHY_28NM_RX_SQ_THRESH_MASK
- PHY_28NM_RX_SQ_THRESH_SHIFT
- PHY_28NM_TEST_REG0
- PHY_28NM_TEST_REG1
- PHY_28NM_TX_AMP_MASK
- PHY_28NM_TX_AMP_SHIFT
- PHY_28NM_TX_PU_ANA
- PHY_28NM_TX_PU_BY_REG
- PHY_28NM_TX_REG0
- PHY_28NM_TX_REG1
- PHY_2LANE
- PHY_A
- PHY_A0_EN
- PHY_ACCESS
- PHY_ACCESS_BITS
- PHY_ACK
- PHY_ADDR
- PHY_ADDRESS
- PHY_ADDR_BCOM
- PHY_ADDR_BMSK
- PHY_ADDR_INTERNAL
- PHY_ADDR_LEN
- PHY_ADDR_MARV
- PHY_ADDR_NONE
- PHY_ADDR_POS
- PHY_ADDR_REG
- PHY_ADDR_REVERSED
- PHY_ADDR_SET
- PHY_ADDR_SHFT
- PHY_ADDR_XMAC
- PHY_ADVERTISE_1000_FULL
- PHY_ADVERTISE_1000_HALF
- PHY_ADVERTISE_100_FULL
- PHY_ADVERTISE_100_HALF
- PHY_ADVERTISE_10_FULL
- PHY_ADVERTISE_10_HALF
- PHY_AGC_CLR
- PHY_AGERE_ET1011C
- PHY_ALLR
- PHY_ALLW
- PHY_ALL_1000_SPEED
- PHY_ALL_10_100_SPEED
- PHY_ANA08
- PHY_ANA08_RX_EQ_DCGAIN
- PHY_ANA08_RX_EQ_VAL
- PHY_ANA08_SCP
- PHY_ANA08_SEL_IPI
- PHY_ANA08_SEL_RX_EN
- PHY_ANA1A
- PHY_ANA1A_REV
- PHY_ANA1A_RXT_BIST
- PHY_ANA1A_TXR_BIST
- PHY_ANA1A_TXR_LOOPBACK
- PHY_ANA1D
- PHY_ANA1D_DEBUG_ADDR
- PHY_ANALOG_SETTING_INFO
- PHY_ANALOG_SETTING_INFO_V2
- PHY_ANY_ID
- PHY_ANY_UID
- PHY_AN_100BASE4
- PHY_AN_100FULL
- PHY_AN_100HALF
- PHY_AN_10FULL
- PHY_AN_10HALF
- PHY_AN_ACK
- PHY_AN_ALL
- PHY_AN_CSMA
- PHY_AN_FULL
- PHY_AN_NXT_PG
- PHY_AN_PAUSE_ASYM
- PHY_AN_PAUSE_CAP
- PHY_AN_RF
- PHY_AN_SEL
- PHY_AQ1202_DEVICEID
- PHY_AQ1202_FIRMWARE
- PHY_AR8031_DBG_DAT
- PHY_AR8031_DBG_OFF
- PHY_AR8031_HIBERNATE
- PHY_AR8031_PS_HIB_EN
- PHY_AR8031_SERDES
- PHY_AR8031_SERDES_TX_CLK_DLY
- PHY_AR803X_ID
- PHY_ARDENNES_MMD_DEV_3_PHY_CFG
- PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_
- PHY_AUTONEG_ADV
- PHY_AUTONEG_ADV_DEFAULT
- PHY_AUTONEG_EN
- PHY_AUTONEG_EXP
- PHY_AUTONEG_RDY
- PHY_AUTO_MDIX_DISABLE
- PHY_AUTO_NEG_100BT4
- PHY_AUTO_NEG_100BTX
- PHY_AUTO_NEG_100BTX_FD
- PHY_AUTO_NEG_10BT
- PHY_AUTO_NEG_10BT_FD
- PHY_AUTO_NEG_802_3
- PHY_AUTO_NEG_ACKNOWLEDGE
- PHY_AUTO_NEG_ASYM_PAUSE
- PHY_AUTO_NEG_CAPABLE
- PHY_AUTO_NEG_ENABLE
- PHY_AUTO_NEG_LIMIT
- PHY_AUTO_NEG_NEXT_PAGE
- PHY_AUTO_NEG_NEXT_PAGE_NOT
- PHY_AUTO_NEG_PAUSE
- PHY_AUTO_NEG_REMOTE_FAULT
- PHY_AUTO_NEG_REMOTE_FAULT_NOT
- PHY_AUTO_NEG_RESTART
- PHY_AUTO_NEG_SELECTOR
- PHY_AUTO_NEG_SYM_PAUSE
- PHY_AUTO_NEG_TIME
- PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK
- PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT
- PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK
- PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT
- PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK
- PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT
- PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK
- PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT
- PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK
- PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT
- PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK
- PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT
- PHY_AUX_CNTL__AUX_CAL_SPARE_MASK
- PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT
- PHY_AUX_CNTL__AUX_PAD_COMPSEL_MASK
- PHY_AUX_CNTL__AUX_PAD_COMPSEL__SHIFT
- PHY_AUX_CNTL__AUX_PAD_RESBIASEN_MASK
- PHY_AUX_CNTL__AUX_PAD_RESBIASEN__SHIFT
- PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK
- PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT
- PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK
- PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT
- PHY_AUX_CNTL__AUX_PAD_WAKE_MASK
- PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT
- PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK
- PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT
- PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK
- PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT
- PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK
- PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT
- PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK
- PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT
- PHY_AUX_CONFIG
- PHY_AUX_CTRL
- PHY_AUX_DUPLEX_STAT
- PHY_AUX_NEG_DONE
- PHY_AUX_NO_HW_STRAP
- PHY_AUX_RESET_STICK
- PHY_AUX_SPEED_STAT
- PHY_AWS_ANTDIV
- PHY_B
- PHY_BACR
- PHY_BACR_BASIC_MASK
- PHY_BAND_24
- PHY_BAND_2G
- PHY_BAND_5
- PHY_BAND_5G
- PHY_BASE
- PHY_BASIC_FEATURES
- PHY_BASIC_T1_FEATURES
- PHY_BBC_ANT_MASK
- PHY_BBC_ANT_SHIFT
- PHY_BBConfig8723B
- PHY_BBR
- PHY_BBW
- PHY_BCAST_CHG
- PHY_BCM5706_PHY_ID
- PHY_BCM84834_DEVICEID
- PHY_BCM84834_FIRMWARE
- PHY_BCM_FLAGS_INTF_SGMII
- PHY_BCM_FLAGS_INTF_XAUI
- PHY_BCM_FLAGS_MODE_1000BX
- PHY_BCM_FLAGS_MODE_COPPER
- PHY_BCM_FLAGS_VALID
- PHY_BCM_OUI_1
- PHY_BCM_OUI_2
- PHY_BCM_OUI_3
- PHY_BCM_OUI_4
- PHY_BCM_OUI_5
- PHY_BCM_OUI_6
- PHY_BCM_OUI_MASK
- PHY_BCOM_1000T_CTRL
- PHY_BCOM_1000T_STAT
- PHY_BCOM_AUNE_ADV
- PHY_BCOM_AUNE_EXP
- PHY_BCOM_AUNE_LP
- PHY_BCOM_AUX_CTRL
- PHY_BCOM_AUX_STAT
- PHY_BCOM_CTRL
- PHY_BCOM_EXT_STAT
- PHY_BCOM_FC_CTR
- PHY_BCOM_ID0
- PHY_BCOM_ID1
- PHY_BCOM_ID1_A1
- PHY_BCOM_ID1_B2
- PHY_BCOM_ID1_C0
- PHY_BCOM_ID1_C5
- PHY_BCOM_INT_MASK
- PHY_BCOM_INT_STAT
- PHY_BCOM_NEPG
- PHY_BCOM_NEPG_LP
- PHY_BCOM_P_EXT_CTRL
- PHY_BCOM_P_EXT_STAT
- PHY_BCOM_RE_CTR
- PHY_BCOM_RNO_CTR
- PHY_BCOM_STAT
- PHY_BCSR
- PHY_BEACON_RSSI_SLID_WIN_MAX
- PHY_BENR
- PHY_BERLIN_MODE_SATA
- PHY_BIAS
- PHY_BIST
- PHY_BIST_ENABLE
- PHY_BJMPN
- PHY_BPCR
- PHY_BPCR_CMIRROR_EN
- PHY_BPCR_IBRXSEL
- PHY_BPCR_IBTXSEL
- PHY_BPCR_IB_FILTER
- PHY_BPNR
- PHY_BPNR2
- PHY_BPR
- PHY_BRCM_7XXX_PATCH
- PHY_BRCM_7XXX_REV
- PHY_BRCM_AUTO_PWRDWN_ENABLE
- PHY_BRCM_CLEAR_RGMII_MODE
- PHY_BRCM_DIS_TXCRXC_NOENRGY
- PHY_BRCM_EN_MASTER_MODE
- PHY_BRCM_EXT_IBND_RX_ENABLE
- PHY_BRCM_EXT_IBND_TX_ENABLE
- PHY_BRCM_RX_REFCLK_UNUSED
- PHY_BRCM_STD_IBND_DISABLE
- PHY_BRCM_WIRESPEED_ENABLE
- PHY_BRNR2
- PHY_BROADCOM_5411
- PHY_BROADCOM_B0
- PHY_BUSY
- PHY_BUSY_LOOPS
- PHY_BUS_RESET
- PHY_BUS_SHORT_RESET
- PHY_B_1000C_AFD
- PHY_B_1000C_AHD
- PHY_B_1000C_MSC
- PHY_B_1000C_MSE
- PHY_B_1000C_RD
- PHY_B_1000C_TEST
- PHY_B_1000S_IEC
- PHY_B_1000S_LP_FD
- PHY_B_1000S_LP_HD
- PHY_B_1000S_LRS
- PHY_B_1000S_MSF
- PHY_B_1000S_MSR
- PHY_B_1000S_RRS
- PHY_B_AC_DIAG
- PHY_B_AC_DIS_PM
- PHY_B_AC_DIS_PRF
- PHY_B_AC_ER_CTRL
- PHY_B_AC_LONG_PACK
- PHY_B_AC_L_SQE
- PHY_B_AC_TX_TST
- PHY_B_AN_ASP
- PHY_B_AN_PC
- PHY_B_AN_RF
- PHY_B_AS_ANAB_D
- PHY_B_AS_ANACK_D
- PHY_B_AS_ANP_R
- PHY_B_AS_AN_C
- PHY_B_AS_AN_CA
- PHY_B_AS_AN_RES_MSK
- PHY_B_AS_LP_ANAB
- PHY_B_AS_LP_NPAB
- PHY_B_AS_LS
- PHY_B_AS_NPW
- PHY_B_AS_PAUSE_MSK
- PHY_B_AS_PDF
- PHY_B_AS_PRR
- PHY_B_AS_PRT
- PHY_B_AS_RF
- PHY_B_DEF_MSK
- PHY_B_ES_T_FD_CAP
- PHY_B_ES_T_HD_CAP
- PHY_B_ES_X_FD_CAP
- PHY_B_ES_X_HD_CAP
- PHY_B_FC_CTR
- PHY_B_IS_AN_PR
- PHY_B_IS_CRC_ER
- PHY_B_IS_DUP_CHANGE
- PHY_B_IS_HCT
- PHY_B_IS_LCT
- PHY_B_IS_LRS_CHANGE
- PHY_B_IS_LSP_CHANGE
- PHY_B_IS_LST_CHANGE
- PHY_B_IS_MDXI_SC
- PHY_B_IS_NEG_USHDC
- PHY_B_IS_NO_HDC
- PHY_B_IS_NO_HDCL
- PHY_B_IS_PSE
- PHY_B_IS_RRS_CHANGE
- PHY_B_IS_SCR_S_ER
- PHY_B_PEC_3_LED
- PHY_B_PEC_BY_45
- PHY_B_PEC_BY_MLT3
- PHY_B_PEC_BY_RXA
- PHY_B_PEC_BY_SCR
- PHY_B_PEC_DIS_CROSS
- PHY_B_PEC_EN_LTR
- PHY_B_PEC_EX_IPG
- PHY_B_PEC_F_INT
- PHY_B_PEC_HIGH_LA
- PHY_B_PEC_INT_DIS
- PHY_B_PEC_LED_OFF
- PHY_B_PEC_LED_ON
- PHY_B_PEC_MAC_PHY
- PHY_B_PEC_RES_SCR
- PHY_B_PEC_TX_DIS
- PHY_B_PES_BAD_ESD
- PHY_B_PES_BAD_SSD
- PHY_B_PES_CE_ER
- PHY_B_PES_CROSS_STAT
- PHY_B_PES_INT_STAT
- PHY_B_PES_LOCKED
- PHY_B_PES_LOCK_ER
- PHY_B_PES_LRS
- PHY_B_PES_LS
- PHY_B_PES_MLT3_ER
- PHY_B_PES_RF
- PHY_B_PES_RRS
- PHY_B_PES_RX_ER
- PHY_B_PES_TX_ER
- PHY_B_P_ASYM_MD
- PHY_B_P_BOTH_MD
- PHY_B_P_NO_PAUSE
- PHY_B_P_SYM_MD
- PHY_B_RC_LOC_MSK
- PHY_B_RC_REM_MSK
- PHY_B_RES_1000FD
- PHY_B_RES_1000HD
- PHY_Beacon_RSSI_SLID_WIN_MAX
- PHY_C
- PHY_CABLE_10M_SHORT
- PHY_CABLE_DIAG_RESULT
- PHY_CABLE_FAULT_COUNTER
- PHY_CABLE_STAT_FAILED
- PHY_CABLE_STAT_NORMAL
- PHY_CABLE_STAT_OPEN
- PHY_CABLE_STAT_SHORT
- PHY_CALIBRATION_DELAY
- PHY_CC
- PHY_CCA
- PHY_CCA_MODE
- PHY_CDP_DM_AUTO
- PHY_CDP_EN
- PHY_CFG
- PHY_CFG1_BYPSCR
- PHY_CFG1_CABLE
- PHY_CFG1_EQLZR
- PHY_CFG1_LNKDIS
- PHY_CFG1_REG
- PHY_CFG1_RLVL0
- PHY_CFG1_TLVL_MASK
- PHY_CFG1_TLVL_SHIFT
- PHY_CFG1_TRF_MASK
- PHY_CFG1_UNSCDS
- PHY_CFG1_XMTDIS
- PHY_CFG1_XMTPDN
- PHY_CFG2_APOLDIS
- PHY_CFG2_INTMDIO
- PHY_CFG2_JABDIS
- PHY_CFG2_MREG
- PHY_CFG2_REG
- PHY_CFG_ADDR_MASK
- PHY_CFG_ADDR_SHIFT
- PHY_CFG_CLK_SCC
- PHY_CFG_CLK_TEST
- PHY_CFG_DATA_MASK
- PHY_CFG_DATA_SHIFT
- PHY_CFG_DC_OPT_MSK
- PHY_CFG_DC_OPT_OFF
- PHY_CFG_ENA_MSK
- PHY_CFG_ENA_OFF
- PHY_CFG_I
- PHY_CFG_PHY_COMMON_RESET
- PHY_CFG_PHY_ENA
- PHY_CFG_PHY_RESET
- PHY_CFG_PHY_RST_MSK
- PHY_CFG_PHY_RST_OFF
- PHY_CFG_PLL_100M
- PHY_CFG_PLL_I
- PHY_CFG_PLL_II
- PHY_CFG_PLL_III
- PHY_CFG_PLL_IV
- PHY_CFG_PLL_LOCK
- PHY_CFG_PLL_V
- PHY_CFG_RD_MASK
- PHY_CFG_SEPE_RATE
- PHY_CFG_TIMEOUT
- PHY_CFG_WR_DISABLE
- PHY_CFG_WR_ENABLE
- PHY_CFG_WR_MASK
- PHY_CFG_WR_SHIFT
- PHY_CHAIN_TX_DISABLE_TEMP
- PHY_CHANGETO_1T1RARRAYLENGTH
- PHY_CHANGETO_1T2RARRAYLENGTH
- PHY_CHANGE_TIME
- PHY_CHANNEL_BONDING_STATE_MAX
- PHY_CH_DEEP_PSR
- PHY_CH_POWER_DOWN_OVRD
- PHY_CH_POWER_DOWN_OVRD_EN
- PHY_CH_POWER_MODE
- PHY_CH_SU_PSR
- PHY_CICADA_INIT1
- PHY_CICADA_INIT2
- PHY_CICADA_INIT3
- PHY_CICADA_INIT4
- PHY_CICADA_INIT5
- PHY_CICADA_INIT6
- PHY_CLEARALL
- PHY_CLEAR_READCOUNT
- PHY_CLKHS2LP_TIME
- PHY_CLKLP2HS_TIME
- PHY_CLK_CTRL
- PHY_CLK_CTRL_CLK32K_EN
- PHY_CLK_CTRL_CLOCKGATING_EN
- PHY_CLK_CTRL_STS
- PHY_CLK_ENABLE
- PHY_CLK_SCHEME_SEL
- PHY_CLK_STABLE_TIME
- PHY_CLK_TOO_SLOW_HZ
- PHY_CLK_VALID
- PHY_CMD_ACTIVE
- PHY_CMU
- PHY_CNT
- PHY_CNTL1_CLKFREQ
- PHY_CNTL1_CLK_EN
- PHY_CNTL1_MII_MODE
- PHY_CNTL1_PHY_ENB
- PHY_CNTL1_ST_MODE
- PHY_CNTL1_ST_PHYADD
- PHY_CNTL2_RX_CLK_EPHY
- PHY_CNTL2_SMI_SRC_MAC
- PHY_CNTL2_USE_INTERNAL
- PHY_CNTL_4_ADDR_POS
- PHY_COLLISION_TEST
- PHY_COLLISION_TEST_NOT
- PHY_COMP_EQ_SKIPN
- PHY_COMP_NEQ_SKIPN
- PHY_COM_LANE_RESET_DEASSERT
- PHY_CONDITION_REG_INFO
- PHY_CONDITION_REG_INFO_V2
- PHY_CONDITION_REG_VAL
- PHY_CONDITION_REG_VAL_V2
- PHY_CONFIG
- PHY_CONFIG2
- PHY_CONFIG2_FORCE_TXDEEMPH_MSK
- PHY_CONFIG2_FORCE_TXDEEMPH_OFF
- PHY_CONFIG2_TX_TRAIN_COMP_MSK
- PHY_CONFIG2_TX_TRAIN_COMP_OFF
- PHY_CONFIGURATION_CMD
- PHY_CONFIG_ENABLE_FW_MANAGEMENT_MASK
- PHY_CONFIG_GAP_COUNT
- PHY_CONFIG_PHY_ADDR_MASK
- PHY_CONFIG_ROOT_ID
- PHY_CONFIG_SHIFT
- PHY_CONN_RATE
- PHY_CONTENDER
- PHY_CONTEXT
- PHY_CONTEXT_CMD
- PHY_CONTROL
- PHY_CONTROL_0
- PHY_CONTROL_1
- PHY_CONTROL_2
- PHY_CONTROL_3
- PHY_CONTROL_4
- PHY_CONTROL_DEFAULT
- PHY_CONTROL_SET
- PHY_CORE_0
- PHY_CORE_1
- PHY_CORE_2
- PHY_CORE_3
- PHY_CORE_MAX
- PHY_CORE_NUM_1
- PHY_CORE_NUM_2
- PHY_CORE_NUM_3
- PHY_CORE_NUM_4
- PHY_COSPLLLOCK
- PHY_COUNT
- PHY_CSQ
- PHY_CSR0
- PHY_CSR0_PA_PE_A
- PHY_CSR0_PA_PE_BG
- PHY_CSR1
- PHY_CSR10
- PHY_CSR10_RF_BUSY
- PHY_CSR10_RF_IF_SELECT
- PHY_CSR10_RF_NUMBER_OF_BITS
- PHY_CSR10_RF_PLL_LD
- PHY_CSR10_RF_VALUE
- PHY_CSR1_RF_RPI
- PHY_CSR2
- PHY_CSR2_LNA
- PHY_CSR2_LNA_MODE
- PHY_CSR3
- PHY_CSR3_BUSY
- PHY_CSR3_READ_CONTROL
- PHY_CSR3_REGNUM
- PHY_CSR3_VALUE
- PHY_CSR4
- PHY_CSR4_BUSY
- PHY_CSR4_IF_SELECT
- PHY_CSR4_LOW_RF_LE
- PHY_CSR4_NUMBER_OF_BITS
- PHY_CSR4_PLL_LD
- PHY_CSR4_VALUE
- PHY_CSR5
- PHY_CSR5_CCK
- PHY_CSR5_CCK_FLIP
- PHY_CSR5_IQ_FLIP
- PHY_CSR6
- PHY_CSR6_IQ_FLIP
- PHY_CSR6_OFDM
- PHY_CSR6_OFDM_FLIP
- PHY_CSR7
- PHY_CSR7_DATA
- PHY_CSR7_READ_CONTROL
- PHY_CSR7_REG_ID
- PHY_CSR8
- PHY_CSR8_BUSY
- PHY_CSR9
- PHY_CSR9_RF_VALUE
- PHY_CTL0
- PHY_CTL1
- PHY_CTL2
- PHY_CTL_SIDDQ
- PHY_CTL_VBUSVLDEXT
- PHY_CTRL
- PHY_CTRL0
- PHY_CTRL0_REF_SSP_EN
- PHY_CTRL1
- PHY_CTRL1_ATERESET
- PHY_CTRL1_COMMONONN
- PHY_CTRL1_RESET
- PHY_CTRL1_VDATDETENB0
- PHY_CTRL1_VDATSRCENB0
- PHY_CTRL2
- PHY_CTRL2_TXENABLEN0
- PHY_CTRL3
- PHY_CTRL4
- PHY_CTRL5
- PHY_CTRL6
- PHY_CTRL_1
- PHY_CTRL_1_RESET
- PHY_CTRL_AUTO_NEG
- PHY_CTRL_INTERVAL
- PHY_CTRL_LOOPBACK
- PHY_CTRL_PHY_PWDN
- PHY_CTRL_R0
- PHY_CTRL_R1
- PHY_CTRL_R10
- PHY_CTRL_R11
- PHY_CTRL_R12
- PHY_CTRL_R13
- PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN
- PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL
- PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT
- PHY_CTRL_R13_CUSTOM_PATTERN_19
- PHY_CTRL_R13_I_C2L_FSLS_RX_EN
- PHY_CTRL_R13_I_C2L_FS_EN
- PHY_CTRL_R13_I_C2L_FS_OE
- PHY_CTRL_R13_I_C2L_HS_EN
- PHY_CTRL_R13_I_C2L_HS_OE
- PHY_CTRL_R13_I_C2L_HS_RX_EN
- PHY_CTRL_R13_I_C2L_LS_EN
- PHY_CTRL_R13_LOAD_STAT
- PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS
- PHY_CTRL_R14
- PHY_CTRL_R14_BYPASS_CTRL_15_8
- PHY_CTRL_R14_BYPASS_CTRL_7_0
- PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO
- PHY_CTRL_R14_I_C2L_DATA_16_8
- PHY_CTRL_R14_I_RDP_EN
- PHY_CTRL_R14_I_RPU_SW1_EN
- PHY_CTRL_R14_I_RPU_SW2_EN
- PHY_CTRL_R14_PG_RSTN
- PHY_CTRL_R15
- PHY_CTRL_R16
- PHY_CTRL_R16_MPLL_DCO_SDM_EN
- PHY_CTRL_R16_MPLL_EN
- PHY_CTRL_R16_MPLL_FAST_LOCK
- PHY_CTRL_R16_MPLL_LOAD
- PHY_CTRL_R16_MPLL_LOCK
- PHY_CTRL_R16_MPLL_LOCK_DIG
- PHY_CTRL_R16_MPLL_LOCK_F
- PHY_CTRL_R16_MPLL_LOCK_LONG
- PHY_CTRL_R16_MPLL_M
- PHY_CTRL_R16_MPLL_N
- PHY_CTRL_R16_MPLL_RESET
- PHY_CTRL_R16_MPLL_SDM_EN
- PHY_CTRL_R16_MPLL_TDC_MODE
- PHY_CTRL_R17
- PHY_CTRL_R17_MPLL_FILTER_MODE
- PHY_CTRL_R17_MPLL_FILTER_PVT1
- PHY_CTRL_R17_MPLL_FILTER_PVT2
- PHY_CTRL_R17_MPLL_FIX_EN
- PHY_CTRL_R17_MPLL_FRAC_IN
- PHY_CTRL_R17_MPLL_LAMBDA0
- PHY_CTRL_R17_MPLL_LAMBDA1
- PHY_CTRL_R18
- PHY_CTRL_R18_MPLL_ACG_RANGE
- PHY_CTRL_R18_MPLL_ADJ_LDO
- PHY_CTRL_R18_MPLL_ALPHA
- PHY_CTRL_R18_MPLL_BB_MODE
- PHY_CTRL_R18_MPLL_BIAS_ADJ
- PHY_CTRL_R18_MPLL_DATA_SEL
- PHY_CTRL_R18_MPLL_DCO_CLK_SEL
- PHY_CTRL_R18_MPLL_DCO_M_EN
- PHY_CTRL_R18_MPLL_LKW_SEL
- PHY_CTRL_R18_MPLL_LK_S
- PHY_CTRL_R18_MPLL_LK_W
- PHY_CTRL_R18_MPLL_PFD_GAIN
- PHY_CTRL_R18_MPLL_ROU
- PHY_CTRL_R19
- PHY_CTRL_R2
- PHY_CTRL_R20
- PHY_CTRL_R20_BYPASS_CAL_DONE_R5
- PHY_CTRL_R20_BYPASS_OTG_DET
- PHY_CTRL_R20_USB2_AMON_EN
- PHY_CTRL_R20_USB2_BGR_ADJ_4_0
- PHY_CTRL_R20_USB2_BGR_DBG_1_0
- PHY_CTRL_R20_USB2_BGR_START
- PHY_CTRL_R20_USB2_BGR_VREF_4_0
- PHY_CTRL_R20_USB2_CAL_CODE_R5
- PHY_CTRL_R20_USB2_DMON_EN
- PHY_CTRL_R20_USB2_DMON_SEL_3_0
- PHY_CTRL_R20_USB2_EDGE_DRV_EN
- PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0
- PHY_CTRL_R20_USB2_IDDET_EN
- PHY_CTRL_R20_USB2_OTG_VBUSDET_EN
- PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0
- PHY_CTRL_R21
- PHY_CTRL_R21_BYPASS_UTMI_CNTR
- PHY_CTRL_R21_BYPASS_UTMI_REG
- PHY_CTRL_R21_USB2_BGR_FORCE
- PHY_CTRL_R21_USB2_CAL_ACK_EN
- PHY_CTRL_R21_USB2_OTG_ACA_EN
- PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0
- PHY_CTRL_R21_USB2_TX_STRG_PD
- PHY_CTRL_R22
- PHY_CTRL_R23
- PHY_CTRL_R3
- PHY_CTRL_R3_DISC_THRESH
- PHY_CTRL_R3_HSDIC_REF
- PHY_CTRL_R3_SQUELCH_REF
- PHY_CTRL_R4
- PHY_CTRL_R4_CALIB_CODE_15_8
- PHY_CTRL_R4_CALIB_CODE_23_16
- PHY_CTRL_R4_CALIB_CODE_7_0
- PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0
- PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2
- PHY_CTRL_R4_I_C2L_CAL_DONE
- PHY_CTRL_R4_I_C2L_CAL_EN
- PHY_CTRL_R4_I_C2L_CAL_RESET_N
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN
- PHY_CTRL_R5
- PHY_CTRL_R6
- PHY_CTRL_R7
- PHY_CTRL_R8
- PHY_CTRL_R9
- PHY_CTRL_RDY_MSK
- PHY_CTRL_RESET_MSK
- PHY_CTRL_RESET_OFF
- PHY_CTRL_RESTART_NEG
- PHY_CTRL_SOFT_RESET
- PHY_CTX_MASK
- PHY_CTX_SHIFT
- PHY_CTX_SIZE
- PHY_CT_ANE
- PHY_CT_COL_TST
- PHY_CT_DUP_MD
- PHY_CT_ISOL
- PHY_CT_LOOP
- PHY_CT_PDOWN
- PHY_CT_RESET
- PHY_CT_RE_CFG
- PHY_CT_SP10
- PHY_CT_SP100
- PHY_CT_SP1000
- PHY_CT_SPS_LSB
- PHY_CT_SPS_MSB
- PHY_CURRENT_CHANNEL
- PHY_CWMAX
- PHY_ConfigRFWithParaFile
- PHY_ConfigRFWithPowerLimitTableParaFile
- PHY_ConfigRFWithTxPwrTrackParaFile
- PHY_ConvertTxPowerLimitToPowerIndex
- PHY_D
- PHY_DATA
- PHY_DATA_0
- PHY_DATA_1
- PHY_DATA_AND
- PHY_DATA_OR
- PHY_DATA_REG
- PHY_DAT_REG
- PHY_DB_CMD
- PHY_DCP_EN
- PHY_DEBUG_MODE
- PHY_DEFAULT_FEATURES
- PHY_DELAY_MS
- PHY_DEVICE_DISCOVERED
- PHY_DEVICE_INFO
- PHY_DEVICE_TYPE
- PHY_DEV_ID
- PHY_DEV_ID_MODEL_MASK_
- PHY_DEV_ID_MODEL_SHIFT_
- PHY_DEV_ID_OUI_MASK_
- PHY_DEV_ID_REV_MASK_
- PHY_DEV_ID_REV_SHIFT_
- PHY_DIG1E
- PHY_DIG1E_D0_X_D1
- PHY_DIG1E_RCLK_REF_HOST
- PHY_DIG1E_RCLK_RX_EIDLE_ON
- PHY_DIG1E_RCLK_TX_EN_KEEP
- PHY_DIG1E_RCLK_TX_TERM_KEEP
- PHY_DIG1E_REV
- PHY_DIG1E_RX_EN_KEEP
- PHY_DIG1E_RX_ON_HOST
- PHY_DIG1E_RX_TERM_KEEP
- PHY_DIG1E_TX_EN_KEEP
- PHY_DIG1E_TX_TERM_KEEP
- PHY_DISABLECLK
- PHY_DISCON_TH_SEL
- PHY_DISFORCEPLL
- PHY_DLL_READY_MASK
- PHY_DLL_READY_SHIFT
- PHY_DMR
- PHY_DONE
- PHY_DONE_CAL_RX
- PHY_DONE_CAL_TX
- PHY_DOUBLE_CHANNEL_CENTERED
- PHY_DOUBLE_CHANNEL_HIGH_PRIMARY
- PHY_DOUBLE_CHANNEL_LOW_PRIMARY
- PHY_DOWN
- PHY_DP83840
- PHY_DPLL_CLK
- PHY_DP_TX_CTL
- PHY_DUMP_SIZE_DWORDS
- PHY_DUM_REG
- PHY_DWORD_LENGTH
- PHY_DW_SYNC
- PHY_E
- PHY_EDPD_CONFIG
- PHY_EDPD_CONFIG_DEFAULT
- PHY_EDPD_CONFIG_EXT_CROSSOVER_
- PHY_EDPD_CONFIG_RX_1_NLP_
- PHY_EDPD_CONFIG_RX_NLP_1000_
- PHY_EDPD_CONFIG_RX_NLP_256_
- PHY_EDPD_CONFIG_RX_NLP_512_
- PHY_EDPD_CONFIG_RX_NLP_64_
- PHY_EDPD_CONFIG_TX_NLP_1000_
- PHY_EDPD_CONFIG_TX_NLP_256_
- PHY_EDPD_CONFIG_TX_NLP_512_
- PHY_EDPD_CONFIG_TX_NLP_768_
- PHY_EDPD_CONFIG_TX_NLP_EN_
- PHY_EMPTY
- PHY_EN
- PHY_ENABLECLK
- PHY_ENABLED
- PHY_ENABLE_ACCEL
- PHY_ENABLE_MULTI
- PHY_ENABLE_RESET_EN
- PHY_ENB
- PHY_ENFORCEPLL
- PHY_ENSWITCH_DM
- PHY_ENSWITCH_DP
- PHY_EOF
- PHY_ERR
- PHY_ERROR
- PHY_ERROR_10_4_RADAR_MASK
- PHY_ERROR_10_4_SPECTRAL_SCAN_MASK
- PHY_ERROR_FALSE_RADAR_EXT
- PHY_ERROR_GEN_FALSE_RADAR_EXT
- PHY_ERROR_GEN_RADAR
- PHY_ERROR_GEN_SPECTRAL_SCAN
- PHY_ERROR_RADAR
- PHY_ERROR_SPECTRAL_SCAN
- PHY_ERROR_UNKNOWN
- PHY_EVENT
- PHY_EVENTS_STATUS
- PHY_EXTENDED_CAPABILITY
- PHY_EXTENDED_REGISTERS
- PHY_EXT_PHYSP_CONTROL
- PHY_EXT_PHYSP_STATUS
- PHY_EXT_STATUS
- PHY_F
- PHY_FLAG_ATTACHED
- PHY_FLAG_OPENED
- PHY_FLD0
- PHY_FLD0_INIT_27S
- PHY_FLD1
- PHY_FLD2
- PHY_FLD3
- PHY_FLD3_INIT_27S
- PHY_FLD3_RXDELINK
- PHY_FLD3_TIMER_4
- PHY_FLD3_TIMER_6
- PHY_FLD4
- PHY_FLD4_BER_CHK_EN
- PHY_FLD4_BER_COUNT
- PHY_FLD4_BER_TIMER
- PHY_FLD4_FLDEN_SEL
- PHY_FLD4_INIT_27S
- PHY_FLD4_REQ_ADDA
- PHY_FLD4_REQ_REF
- PHY_FLD4_RXAMP_OFF
- PHY_FLOW_CTRL
- PHY_FORCE_LIMIT
- PHY_FORCE_LINK
- PHY_FORCE_MDIX
- PHY_FORCE_TIME
- PHY_FORCE_TIMEOUT
- PHY_FULLCAL
- PHY_FULL_DUPLEX
- PHY_FUNC_CLEAR_AFFIL
- PHY_FUNC_CLEAR_ERROR_LOG
- PHY_FUNC_DISABLE
- PHY_FUNC_GET_EVENTS
- PHY_FUNC_HARD_RESET
- PHY_FUNC_LINK_RESET
- PHY_FUNC_NOP
- PHY_FUNC_RELEASE_SPINUP_HOLD
- PHY_FUNC_SET_LINK_RATE
- PHY_FUNC_TX_SATA_PS_SIGNAL
- PHY_FW_VER_LEN
- PHY_G
- PHY_G3_WITHOUT_SSC_BIT_SHIFT
- PHY_G3_WITH_SSC_BIT_SHIFT
- PHY_GAD_TEST_MODE_1
- PHY_GAD_TEST_MODE_MSK
- PHY_GBIT_ALL_PORTS_FEATURES
- PHY_GBIT_FEATURES
- PHY_GBIT_FIBRE_FEATURES
- PHY_GEN_MAX_1_5
- PHY_GEN_MAX_3_0
- PHY_GEN_MAX_6_0
- PHY_GET_PADMIX
- PHY_GET_RFATTN
- PHY_GET_RFGAINID
- PHY_GIGABIT
- PHY_GIG_ADV_1000F
- PHY_GIG_ADV_1000H
- PHY_GIG_ALL_PARAMS
- PHY_GIG_CONTROL
- PHY_GIG_ENABLE_MAN
- PHY_GIG_SET_MASTER
- PHY_GMII_SEL_LAST
- PHY_GMII_SEL_PORT_MODE
- PHY_GMII_SEL_RGMII_ID_MODE
- PHY_GMII_SEL_RMII_IO_CLK_EN
- PHY_GO
- PHY_GetRateIndexOfTxPowerByRate
- PHY_GetRateSectionIndexOfTxPowerByRate
- PHY_GetRateValuesOfTxPowerByRate
- PHY_GetTxPowerByRate
- PHY_GetTxPowerByRateBase
- PHY_GetTxPowerIndex
- PHY_GetTxPowerIndexBase
- PHY_GetTxPowerLevel8723B
- PHY_GetTxPowerTrackingOffset
- PHY_H
- PHY_HALF
- PHY_HALF_OPEN_CONN_FLAG
- PHY_HALTED
- PHY_HARD_RESET
- PHY_HOLD_FOR_ASSOC
- PHY_HOLD_FOR_MUTE
- PHY_HOLD_FOR_NOT_ASSOC
- PHY_HOLD_FOR_PLT
- PHY_HOLD_FOR_RM
- PHY_HOLD_FOR_SCAN
- PHY_HOST_CLK_CTRL
- PHY_HP_MDIX
- PHY_HS2LP_TIME
- PHY_HS2LP_TIME_V131
- PHY_HW_ROUND
- PHY_HYSTERESIS_DELTATEMP
- PHY_HandleSwChnlAndSetBW8723B
- PHY_I
- PHY_I1_MOD_NUM
- PHY_I1_OUI_MSK
- PHY_I1_REV_MSK
- PHY_IAC_ACCESS
- PHY_IAC_ADDR_SHIFT
- PHY_IAC_READ
- PHY_IAC_REG_SHIFT
- PHY_IAC_START
- PHY_IAC_TIMEOUT
- PHY_IAC_WRITE
- PHY_ICS1889
- PHY_ICS1890
- PHY_ID
- PHY_ID1
- PHY_ID2
- PHY_IDENTIFIER
- PHY_IDLE_ERROR_COUNT_MASK
- PHY_ID_0_REG
- PHY_ID_1_REG
- PHY_ID_ADIN1200
- PHY_ID_ADIN1300
- PHY_ID_AM79C874
- PHY_ID_ANY
- PHY_ID_AQ1202
- PHY_ID_AQ2104
- PHY_ID_AQCS109
- PHY_ID_AQR105
- PHY_ID_AQR106
- PHY_ID_AQR107
- PHY_ID_AQR405
- PHY_ID_AR8031
- PHY_ID_AR8035
- PHY_ID_ASIX_AX88796B
- PHY_ID_BCM50610
- PHY_ID_BCM50610M
- PHY_ID_BCM5241
- PHY_ID_BCM5395
- PHY_ID_BCM5411
- PHY_ID_BCM5421
- PHY_ID_BCM54210E
- PHY_ID_BCM54220
- PHY_ID_BCM5461
- PHY_ID_BCM54612E
- PHY_ID_BCM54616S
- PHY_ID_BCM5464
- PHY_ID_BCM5481
- PHY_ID_BCM54810
- PHY_ID_BCM5482
- PHY_ID_BCM57780
- PHY_ID_BCM7250
- PHY_ID_BCM7255
- PHY_ID_BCM7260
- PHY_ID_BCM7268
- PHY_ID_BCM7271
- PHY_ID_BCM7278
- PHY_ID_BCM7346
- PHY_ID_BCM7362
- PHY_ID_BCM7364
- PHY_ID_BCM7366
- PHY_ID_BCM7425
- PHY_ID_BCM7429
- PHY_ID_BCM7435
- PHY_ID_BCM74371
- PHY_ID_BCM7439
- PHY_ID_BCM7439_2
- PHY_ID_BCM7445
- PHY_ID_BCM8706
- PHY_ID_BCM8727
- PHY_ID_BCM89610
- PHY_ID_BCMAC131
- PHY_ID_BCM_CYGNUS
- PHY_ID_BCM_OMEGA
- PHY_ID_CS4340
- PHY_ID_FMT
- PHY_ID_KS8737
- PHY_ID_KSZ8001
- PHY_ID_KSZ8021
- PHY_ID_KSZ8031
- PHY_ID_KSZ8041
- PHY_ID_KSZ8041RNLI
- PHY_ID_KSZ8051
- PHY_ID_KSZ8061
- PHY_ID_KSZ8081
- PHY_ID_KSZ87XX
- PHY_ID_KSZ8863
- PHY_ID_KSZ886X
- PHY_ID_KSZ8873MLL
- PHY_ID_KSZ9021
- PHY_ID_KSZ9021RLRN
- PHY_ID_KSZ9031
- PHY_ID_KSZ9131
- PHY_ID_KSZ9477
- PHY_ID_MASK
- PHY_ID_MATCH_EXACT
- PHY_ID_MATCH_MODEL
- PHY_ID_MATCH_VENDOR
- PHY_ID_PHY11G_1_3
- PHY_ID_PHY11G_1_4
- PHY_ID_PHY11G_1_5
- PHY_ID_PHY11G_VR9_1_1
- PHY_ID_PHY11G_VR9_1_2
- PHY_ID_PHY22F_1_3
- PHY_ID_PHY22F_1_4
- PHY_ID_PHY22F_1_5
- PHY_ID_PHY22F_VR9_1_1
- PHY_ID_PHY22F_VR9_1_2
- PHY_ID_QCA8337
- PHY_ID_RTL8201E
- PHY_ID_RTL8211C
- PHY_ID_TJA1100
- PHY_ID_TJA1101
- PHY_ID_TN2020
- PHY_ID_VSC7385
- PHY_ID_VSC7388
- PHY_ID_VSC7395
- PHY_ID_VSC7398
- PHY_ID_VSC8211
- PHY_ID_VSC8221
- PHY_ID_VSC8234
- PHY_ID_VSC8244
- PHY_ID_VSC8514
- PHY_ID_VSC8530
- PHY_ID_VSC8531
- PHY_ID_VSC8540
- PHY_ID_VSC8541
- PHY_ID_VSC8572
- PHY_ID_VSC8574
- PHY_ID_VSC8584
- PHY_ID_VSC8601
- PHY_ID_VSC8662
- PHY_IER
- PHY_IF_CFG
- PHY_IGNORE_INTERRUPT
- PHY_IMPCAL_DONE
- PHY_IMR
- PHY_INDEX_BOTH_HC
- PHY_INDEX_EHCI
- PHY_INDEX_HSUSB
- PHY_INDEX_OHCI
- PHY_INDEX_REG
- PHY_INEXISTENT
- PHY_INIT
- PHY_INITIALIZED
- PHY_INIT_BITS
- PHY_INIT_COMPLETE_TIMEOUT
- PHY_INIT_TIMEOUT
- PHY_INTERFACE_MODE_1000BASEX
- PHY_INTERFACE_MODE_10GKR
- PHY_INTERFACE_MODE_2500BASEX
- PHY_INTERFACE_MODE_GMII
- PHY_INTERFACE_MODE_INTERNAL
- PHY_INTERFACE_MODE_MAX
- PHY_INTERFACE_MODE_MII
- PHY_INTERFACE_MODE_MOCA
- PHY_INTERFACE_MODE_NA
- PHY_INTERFACE_MODE_QSGMII
- PHY_INTERFACE_MODE_REVMII
- PHY_INTERFACE_MODE_RGMII
- PHY_INTERFACE_MODE_RGMII_ID
- PHY_INTERFACE_MODE_RGMII_RXID
- PHY_INTERFACE_MODE_RGMII_TXID
- PHY_INTERFACE_MODE_RMII
- PHY_INTERFACE_MODE_RTBI
- PHY_INTERFACE_MODE_RXAUI
- PHY_INTERFACE_MODE_SGMII
- PHY_INTERFACE_MODE_SMII
- PHY_INTERFACE_MODE_TBI
- PHY_INTERFACE_MODE_TRGMII
- PHY_INTERFACE_MODE_USXGMII
- PHY_INTERFACE_MODE_XAUI
- PHY_INTERFACE_MODE_XGMII
- PHY_INTERRUPT_DISABLED
- PHY_INTERRUPT_ENABLED
- PHY_INTERRUPT_MASK
- PHY_INTERRUPT_STATUS
- PHY_INTF_MII
- PHY_INTF_RGMII
- PHY_INTF_RMII
- PHY_INTF_SELI
- PHY_INTF_SELI_SHIFT
- PHY_INTMSK_AN_ACK_
- PHY_INTMSK_AN_COMP_
- PHY_INTMSK_AN_RCV_
- PHY_INTMSK_DEFAULT_
- PHY_INTMSK_ENERGYON_
- PHY_INTMSK_LNKDOWN_
- PHY_INTMSK_PDFAULT_
- PHY_INTMSK_RFAULT_
- PHY_INT_CWRD
- PHY_INT_DPLXDET
- PHY_INT_ENB
- PHY_INT_ESD
- PHY_INT_INT
- PHY_INT_JAB
- PHY_INT_LNKFAIL
- PHY_INT_LOSSSYNC
- PHY_INT_MASK
- PHY_INT_MASK_ANEG_COMP
- PHY_INT_MASK_ANEG_COMP_
- PHY_INT_MASK_ANEG_LP_ACK_
- PHY_INT_MASK_ANEG_PGRX_
- PHY_INT_MASK_DEFAULT
- PHY_INT_MASK_DEFAULT_
- PHY_INT_MASK_ENERGY_ON
- PHY_INT_MASK_ENERGY_ON_
- PHY_INT_MASK_LINK_DOWN
- PHY_INT_MASK_LINK_DOWN_
- PHY_INT_MASK_PAR_DET_FAULT_
- PHY_INT_MASK_REMOTE_FAULT
- PHY_INT_MASK_REMOTE_FAULT_
- PHY_INT_REG
- PHY_INT_RPOL
- PHY_INT_SPDDET
- PHY_INT_SRC
- PHY_INT_SRC_ANEG_COMP
- PHY_INT_SRC_ANEG_COMP_
- PHY_INT_SRC_ANEG_LP_ACK_
- PHY_INT_SRC_ANEG_PGRX_
- PHY_INT_SRC_CLEAR_ALL
- PHY_INT_SRC_ENERGY_ON
- PHY_INT_SRC_ENERGY_ON_
- PHY_INT_SRC_LINK_DOWN
- PHY_INT_SRC_LINK_DOWN_
- PHY_INT_SRC_PAR_DET_FAULT_
- PHY_INT_SRC_REMOTE_FAULT
- PHY_INT_SRC_REMOTE_FAULT_
- PHY_INT_SSD
- PHY_INT_STATUS_BITS
- PHY_IPA
- PHY_IQCalibrate_8723B
- PHY_ISO
- PHY_ISOLATION_CTRL
- PHY_ISO_CMN_CTRL
- PHY_ISO_EN
- PHY_IS_INTERNAL
- PHY_InitTxPowerByRate
- PHY_InitTxPowerLimit
- PHY_JABBER_DETECT
- PHY_JABBER_DETECT_NOT
- PHY_KSZ9031RNX
- PHY_LAN83C180
- PHY_LAN83C183
- PHY_LAN8835
- PHY_LANE_A_STATUS
- PHY_LANE_B_STATUS
- PHY_LANE_C_STATUS
- PHY_LANE_D_STATUS
- PHY_LANE_IDLE_A_SHIFT
- PHY_LANE_IDLE_B_SHIFT
- PHY_LANE_IDLE_C_SHIFT
- PHY_LANE_IDLE_D_SHIFT
- PHY_LANE_IDLE_MASK
- PHY_LANE_IDLE_OFF
- PHY_LANE_RX_DET_SHIFT
- PHY_LANE_RX_DET_TH
- PHY_LCCalibrate_8723B
- PHY_LDO_DELAY_0NS
- PHY_LDO_DELAY_200NS
- PHY_LDO_DELAY_600NS
- PHY_LDO_SEQ_DELAY
- PHY_LED_1
- PHY_LED_2
- PHY_LED_CONTROL
- PHY_LED_DISABLE
- PHY_LED_TRIGGER_SPEED_SUFFIX_SIZE
- PHY_LINKQUALITY_SLID_WIN_MAX
- PHY_LINK_ACTIVE
- PHY_LINK_AUTONEG_COMPLETE
- PHY_LINK_DISABLE
- PHY_LINK_DOWN
- PHY_LINK_DUPLEX
- PHY_LINK_DUPLEX_FULL
- PHY_LINK_DUPLEX_HALF
- PHY_LINK_DUPLEX_NONE
- PHY_LINK_LED_TRIGGER_NAME_SIZE
- PHY_LINK_MDI_STAT
- PHY_LINK_RESET
- PHY_LINK_SPEEDDPU_RESOLVED
- PHY_LINK_SPEED_1000M
- PHY_LINK_SPEED_100M
- PHY_LINK_SPEED_100MBPS
- PHY_LINK_SPEED_10GBPS
- PHY_LINK_SPEED_10M
- PHY_LINK_SPEED_10MBPS
- PHY_LINK_SPEED_1GBPS
- PHY_LINK_SPEED_20GBPS
- PHY_LINK_SPEED_25GBPS
- PHY_LINK_SPEED_40GBPS
- PHY_LINK_SPEED_MASK
- PHY_LINK_SPEED_ZERO
- PHY_LINK_STATUS
- PHY_LINK_SUPPORT
- PHY_LINK_UP
- PHY_LOCK
- PHY_LOCK_DRIVER
- PHY_LOOPBACK
- PHY_LOOPBACK_CONTROL
- PHY_LOOPBACK_RX
- PHY_LOOPBACK_TX
- PHY_LOWPWREN_RX
- PHY_LOWPWREN_TX
- PHY_LP2HS_TIME
- PHY_LP2HS_TIME_V131
- PHY_LP_ABILITY
- PHY_LP_NEXT_PAGE
- PHY_LUCENT_B0
- PHY_M0_EN
- PHY_M0_RST
- PHY_M1_RST
- PHY_MACConfig8723B
- PHY_MACR
- PHY_MACW
- PHY_MARVELL_E3016_INITMASK
- PHY_MARV_1000T_CTRL
- PHY_MARV_1000T_STAT
- PHY_MARV_AUNE_ADV
- PHY_MARV_AUNE_EXP
- PHY_MARV_AUNE_LP
- PHY_MARV_CABLE_DIAG
- PHY_MARV_CTRL
- PHY_MARV_EXT_ADR
- PHY_MARV_EXT_CTRL
- PHY_MARV_EXT_CTRL_2
- PHY_MARV_EXT_P_STAT
- PHY_MARV_EXT_STAT
- PHY_MARV_FE_LED_PAR
- PHY_MARV_FE_LED_SER
- PHY_MARV_FE_SPEC_2
- PHY_MARV_FE_VCT_RX
- PHY_MARV_FE_VCT_TX
- PHY_MARV_ID0
- PHY_MARV_ID0_VAL
- PHY_MARV_ID1
- PHY_MARV_ID1_B0
- PHY_MARV_ID1_B2
- PHY_MARV_ID1_C2
- PHY_MARV_ID1_ECU
- PHY_MARV_ID1_FE
- PHY_MARV_ID1_Y2
- PHY_MARV_INT_MASK
- PHY_MARV_INT_STAT
- PHY_MARV_LED_CTRL
- PHY_MARV_LED_OVER
- PHY_MARV_NEPG
- PHY_MARV_NEPG_LP
- PHY_MARV_PAGE_ADDR
- PHY_MARV_PAGE_DATA
- PHY_MARV_PHY_CTRL
- PHY_MARV_PHY_STAT
- PHY_MARV_PORT_IRQ
- PHY_MARV_RXE_CNT
- PHY_MARV_STAT
- PHY_MASK_REG
- PHY_MAX_ADDR
- PHY_MAX_LANE_NUM
- PHY_MAX_REG_ADDRESS
- PHY_MAX_SPP_PHYS_LINK_RATE_MASK
- PHY_MCB_S6G_CFG
- PHY_MCB_S6G_READ
- PHY_MCB_S6G_WRITE
- PHY_MCB_TARGET
- PHY_MDIO_CHG
- PHY_MDIX_CTRL_M
- PHY_MDIX_CTRL_S
- PHY_MDIX_STATUS_B
- PHY_MDM6600_CMD0
- PHY_MDM6600_CMD1
- PHY_MDM6600_CMD2
- PHY_MDM6600_CMD_BP_PANIC_ACK
- PHY_MDM6600_CMD_BP_SHUTDOWN_REQ
- PHY_MDM6600_CMD_BP_UNKNOWN_5
- PHY_MDM6600_CMD_BP_UNKNOWN_6
- PHY_MDM6600_CMD_DATA_ONLY_BYPASS
- PHY_MDM6600_CMD_FULL_BYPASS
- PHY_MDM6600_CMD_NO_BYPASS
- PHY_MDM6600_CMD_UNDEFINED
- PHY_MDM6600_ENABLE
- PHY_MDM6600_ENABLED_DELAY_MS
- PHY_MDM6600_MODE0
- PHY_MDM6600_MODE1
- PHY_MDM6600_NR_CMD_LINES
- PHY_MDM6600_NR_CTRL_LINES
- PHY_MDM6600_NR_MODE_LINES
- PHY_MDM6600_NR_STATUS_LINES
- PHY_MDM6600_PHY_DELAY_MS
- PHY_MDM6600_POWER
- PHY_MDM6600_RESET
- PHY_MDM6600_STATUS0
- PHY_MDM6600_STATUS1
- PHY_MDM6600_STATUS2
- PHY_MDM6600_STATUS_PANIC
- PHY_MDM6600_STATUS_PANIC_BUSY_WAIT
- PHY_MDM6600_STATUS_PHONE_CODE_ASLEEP
- PHY_MDM6600_STATUS_PHONE_CODE_AWAKE
- PHY_MDM6600_STATUS_QC_DLOAD
- PHY_MDM6600_STATUS_RAM_DOWNLOADER
- PHY_MDM6600_STATUS_SHUTDOWN_ACK
- PHY_MDM6600_STATUS_UNDEFINED
- PHY_MDM6600_WAKE_KICK_MS
- PHY_MEM_ACCESS
- PHY_MIB_CHANNEL_POS
- PHY_MIB_RATE_SET_POS
- PHY_MIB_REG_DOMAIN_POS
- PHY_MII_DISABLE
- PHY_MII_SUPPRESS_CAPABLE
- PHY_MII_SUPPRESS_CAPABLE_NOT
- PHY_MIN_SPP_PHYS_LINK_RATE_MASK
- PHY_MODE2
- PHY_MODE3
- PHY_MODE4
- PHY_MODE4_CFG_MASK
- PHY_MODE4_CFG_VALUE
- PHY_MODE4_RSVD_ONES
- PHY_MODE4_RSVD_ZEROS
- PHY_MODE6_DTL_SPEED
- PHY_MODE6_FC_ORDER
- PHY_MODE6_FRC_RXFOFFS
- PHY_MODE6_FREEZE_LOOP
- PHY_MODE6_INT_RXFOFFS
- PHY_MODE6_LATECLK
- PHY_MODE6_MUCNT_EN
- PHY_MODE6_RXSAT_DIS
- PHY_MODE6_SELMUFF
- PHY_MODE6_SELMUFI
- PHY_MODE6_SELMUPF
- PHY_MODE6_SELMUPI
- PHY_MODE6_SEL_MUCNT_LEN
- PHY_MODE6_STAU_0D8
- PHY_MODE9_GEN1
- PHY_MODE9_GEN2
- PHY_MODEL_MARVELL_E3016
- PHY_MODEL_MASK
- PHY_MODEL_REALTEK_8201
- PHY_MODEL_REALTEK_8211
- PHY_MODE_100BT_FULL
- PHY_MODE_100BT_HALF
- PHY_MODE_10BT_FULL
- PHY_MODE_10BT_HALF
- PHY_MODE_CAL
- PHY_MODE_CTRL_STS
- PHY_MODE_ETHERNET
- PHY_MODE_INVALID
- PHY_MODE_IN_AUTO_NEG
- PHY_MODE_ISOLDATE
- PHY_MODE_LOW_POWER
- PHY_MODE_M
- PHY_MODE_MARVELL
- PHY_MODE_MIPI_DPHY
- PHY_MODE_NOISEM
- PHY_MODE_NORMAL
- PHY_MODE_OFF
- PHY_MODE_PCIE
- PHY_MODE_RTL8211CL
- PHY_MODE_S
- PHY_MODE_SATA
- PHY_MODE_SET_TIMEOUT
- PHY_MODE_SPECIAL
- PHY_MODE_TX_DISABLED
- PHY_MODE_UFS_HS_A
- PHY_MODE_UFS_HS_B
- PHY_MODE_USB_DEVICE
- PHY_MODE_USB_DEVICE_FS
- PHY_MODE_USB_DEVICE_HS
- PHY_MODE_USB_DEVICE_LS
- PHY_MODE_USB_DEVICE_SS
- PHY_MODE_USB_HOST
- PHY_MODE_USB_HOST_FS
- PHY_MODE_USB_HOST_HS
- PHY_MODE_USB_HOST_LS
- PHY_MODE_USB_HOST_SS
- PHY_MODE_USB_OTG
- PHY_MPHY_CONTROL_REG
- PHY_MUTED
- PHY_MUTE_ALL
- PHY_MUTE_FOR_PREISM
- PHY_M_1000C_AFD
- PHY_M_1000C_AHD
- PHY_M_1000C_MPD
- PHY_M_1000C_MSC
- PHY_M_1000C_MSE
- PHY_M_1000C_TEST
- PHY_M_10B_TE_ENABLE
- PHY_M_AN_1000X_AFD
- PHY_M_AN_1000X_AHD
- PHY_M_AN_100_FD
- PHY_M_AN_100_HD
- PHY_M_AN_100_T4
- PHY_M_AN_10_FD
- PHY_M_AN_10_HD
- PHY_M_AN_ACK
- PHY_M_AN_ASP
- PHY_M_AN_ASP_X
- PHY_M_AN_MSK
- PHY_M_AN_NXT_PG
- PHY_M_AN_PC
- PHY_M_AN_PC_X
- PHY_M_AN_RF
- PHY_M_AN_SEL_MSK
- PHY_M_CABD_AMPL_MSK
- PHY_M_CABD_DIST_MSK
- PHY_M_CABD_DIS_WAIT
- PHY_M_CABD_ENA_TEST
- PHY_M_CABD_STAT_MSK
- PHY_M_DEF_MSK
- PHY_M_DIS_AUT_MED
- PHY_M_DTE_POW_STAT
- PHY_M_EC2_FI_IMPED
- PHY_M_EC2_FO_AM_MSK
- PHY_M_EC2_FO_BOOST
- PHY_M_EC2_FO_IMPED
- PHY_M_EC2_FO_M_CLK
- PHY_M_EC_DIS_LINK_P
- PHY_M_EC_DOWN_S_ENA
- PHY_M_EC_DSC_2
- PHY_M_EC_DTE_D_ENA
- PHY_M_EC_ENA_BC_EXT
- PHY_M_EC_ENA_LIN_LB
- PHY_M_EC_FIB_AN_ENA
- PHY_M_EC_MAC_S
- PHY_M_EC_MAC_S_MSK
- PHY_M_EC_M_DSC
- PHY_M_EC_M_DSC_2
- PHY_M_EC_M_DSC_MSK
- PHY_M_EC_M_DSC_MSK2
- PHY_M_EC_RX_TIM_CT
- PHY_M_EC_S_DSC
- PHY_M_EC_S_DSC_MSK
- PHY_M_EC_TRANS_DIS
- PHY_M_EC_TX_TIM_CT
- PHY_M_FC_AN_REG_ACC
- PHY_M_FC_AUTO_SEL
- PHY_M_FC_RESOLUTION
- PHY_M_FELP_LED0_CTRL
- PHY_M_FELP_LED0_MSK
- PHY_M_FELP_LED1_CTRL
- PHY_M_FELP_LED1_MSK
- PHY_M_FELP_LED2_CTRL
- PHY_M_FELP_LED2_MSK
- PHY_M_FESC_DIS_WAIT
- PHY_M_FESC_ENA_MCLK
- PHY_M_FESC_SEL_CL_A
- PHY_M_FIB_FORCE_LNK
- PHY_M_FIB_SIGD_POL
- PHY_M_FIB_TX_DIS
- PHY_M_IRQ_POLARITY
- PHY_M_IS_AN_COMPL
- PHY_M_IS_AN_ERROR
- PHY_M_IS_AN_MSK
- PHY_M_IS_AN_PR
- PHY_M_IS_DEF_MSK
- PHY_M_IS_DOWNSH_DET
- PHY_M_IS_DTE_CHANGE
- PHY_M_IS_DUP_CHANGE
- PHY_M_IS_END_CHANGE
- PHY_M_IS_FALSE_CARR
- PHY_M_IS_FIFO_ERROR
- PHY_M_IS_JABBER
- PHY_M_IS_LSP_CHANGE
- PHY_M_IS_LST_CHANGE
- PHY_M_IS_MDI_CHANGE
- PHY_M_IS_POL_CHANGE
- PHY_M_IS_SYMB_ERROR
- PHY_M_LEDC_BL_R_MSK
- PHY_M_LEDC_DIS_LED
- PHY_M_LEDC_DP_CTRL
- PHY_M_LEDC_DP_C_LSB
- PHY_M_LEDC_DP_C_MSB
- PHY_M_LEDC_F_INT
- PHY_M_LEDC_INIT_CTRL
- PHY_M_LEDC_INIT_MSK
- PHY_M_LEDC_LINK_MSK
- PHY_M_LEDC_LK_C_MSK
- PHY_M_LEDC_LOS_CTRL
- PHY_M_LEDC_LOS_MSK
- PHY_M_LEDC_PULS_MSK
- PHY_M_LEDC_RX_CTRL
- PHY_M_LEDC_STA0_CTRL
- PHY_M_LEDC_STA0_MSK
- PHY_M_LEDC_STA1_CTRL
- PHY_M_LEDC_STA1_MSK
- PHY_M_LEDC_TX_CTRL
- PHY_M_LEDC_TX_C_LSB
- PHY_M_LEDC_TX_C_MSB
- PHY_M_LED_BLINK_RT
- PHY_M_LED_MO_10
- PHY_M_LED_MO_100
- PHY_M_LED_MO_1000
- PHY_M_LED_MO_DUP
- PHY_M_LED_MO_RX
- PHY_M_LED_MO_SGMII
- PHY_M_LED_MO_TX
- PHY_M_LED_PULS_DUR
- PHY_M_MAC_GMIF_PUP
- PHY_M_MAC_MD_1000BX
- PHY_M_MAC_MD_AUTO
- PHY_M_MAC_MD_COPPER
- PHY_M_MAC_MD_MSK
- PHY_M_MAC_MODE_SEL
- PHY_M_MODE_MASK
- PHY_M_PC_ASS_CRS_TX
- PHY_M_PC_COP_TX_DIS
- PHY_M_PC_DIS_125CLK
- PHY_M_PC_DIS_FEFI
- PHY_M_PC_DIS_JABBER
- PHY_M_PC_DIS_LINK_Pa
- PHY_M_PC_DIS_NLP_CK
- PHY_M_PC_DIS_NLP_GN
- PHY_M_PC_DIS_SCRAMB
- PHY_M_PC_DOWN_S_ENA
- PHY_M_PC_DSC
- PHY_M_PC_DSC_MSK
- PHY_M_PC_ENA_AUTO
- PHY_M_PC_ENA_DTE_DT
- PHY_M_PC_ENA_ENE_DT
- PHY_M_PC_ENA_EXT_D
- PHY_M_PC_ENA_LIP_NP
- PHY_M_PC_EN_DET
- PHY_M_PC_EN_DET_MSK
- PHY_M_PC_EN_DET_PLUS
- PHY_M_PC_FL_GOOD
- PHY_M_PC_MAC_POW_UP
- PHY_M_PC_MAN_MDI
- PHY_M_PC_MAN_MDIX
- PHY_M_PC_MDIX_MSK
- PHY_M_PC_MDI_XMODE
- PHY_M_PC_POL_R_DIS
- PHY_M_PC_POW_D_ENA
- PHY_M_PC_RX_FD_MSK
- PHY_M_PC_RX_FFD_MSK
- PHY_M_PC_SH_TP_SEL
- PHY_M_PC_SQE_T_ENA
- PHY_M_PC_TX_FFD_MSK
- PHY_M_POLC_INIT_CTRL
- PHY_M_POLC_INIT_MSK
- PHY_M_POLC_IS0M_MSK
- PHY_M_POLC_IS0_P_MIX
- PHY_M_POLC_LOS_CTRL
- PHY_M_POLC_LOS_MSK
- PHY_M_POLC_LS1M_MSK
- PHY_M_POLC_LS1_P_MIX
- PHY_M_POLC_STA0_CTRL
- PHY_M_POLC_STA0_MSK
- PHY_M_POLC_STA1_CTRL
- PHY_M_POLC_STA1_MSK
- PHY_M_PS_CABLE_MSK
- PHY_M_PS_DOWNS_STAT
- PHY_M_PS_DTE_DETECT
- PHY_M_PS_ENDET_STAT
- PHY_M_PS_FULL_DUP
- PHY_M_PS_JABBER
- PHY_M_PS_LINK_UP
- PHY_M_PS_MDI_X_STAT
- PHY_M_PS_PAGE_REC
- PHY_M_PS_PAUSE_MSK
- PHY_M_PS_POL_REV
- PHY_M_PS_RES_SPEED
- PHY_M_PS_RX_P_EN
- PHY_M_PS_SPDUP_RES
- PHY_M_PS_SPEED_10
- PHY_M_PS_SPEED_100
- PHY_M_PS_SPEED_1000
- PHY_M_PS_SPEED_MSK
- PHY_M_PS_TX_P_EN
- PHY_M_P_ASYM_MD_X
- PHY_M_P_BOTH_MD_X
- PHY_M_P_NO_PAUSE_X
- PHY_M_P_SYM_MD_X
- PHY_M_SER_IF_AN_BP
- PHY_M_SER_IF_BP_ST
- PHY_M_UNDOC1
- PHY_NAME
- PHY_NEG_ADVER
- PHY_NEG_ADV_100F
- PHY_NEG_ADV_100H
- PHY_NEG_ADV_10F
- PHY_NEG_ADV_10H
- PHY_NEG_ADV_SPEED
- PHY_NEG_ALL_PARAMS
- PHY_NEG_ASY_PAUSE
- PHY_NEG_PARTNER
- PHY_NEG_PAUSE
- PHY_NEG_SPP_PHYS_LINK_RATE_MASK
- PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET
- PHY_NEG_SYM_PAUSE
- PHY_NEXT_PAGE_TX
- PHY_NEXT_PAGE_TX_DEFAULT
- PHY_NOISEVAR_BUFSIZE
- PHY_NOISE_FIXED_VAL
- PHY_NOISE_FIXED_VAL_LCNPHY
- PHY_NOISE_FIXED_VAL_NPHY
- PHY_NOISE_GLITCH_INIT_MA
- PHY_NOISE_GLITCH_INIT_MA_BADPlCP
- PHY_NOISE_MASK
- PHY_NOISE_MA_WINDOW_SZ
- PHY_NOISE_OFFSETFACT_4322
- PHY_NOISE_SAMPLE_EXTERNAL
- PHY_NOISE_SAMPLE_LOG_NUM_NPHY
- PHY_NOISE_SAMPLE_LOG_NUM_UCODE
- PHY_NOISE_SAMPLE_MON
- PHY_NOISE_STATE_EXTERNAL
- PHY_NOISE_STATE_MON
- PHY_NOISE_WINDOW_SZ
- PHY_NOLINK
- PHY_NONE
- PHY_NOTIFY_ENABLE_SPINUP
- PHY_NOT_PRESENT
- PHY_NO_FLOW_CTRL
- PHY_NO_OP
- PHY_NS_DP83065
- PHY_NUMBER
- PHY_NUM_EVENTS
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5
- PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5
- PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5
- PHY_OFF
- PHY_OOB_DTCTD
- PHY_OPS_GROUP
- PHY_OP_READ
- PHY_OP_WRITE
- PHY_OTG_FUNC_EN
- PHY_OUI_1_MASK
- PHY_OUI_CICADA
- PHY_OUI_MARVELL
- PHY_OUI_REALTEK
- PHY_OUI_REALTEK2
- PHY_OUI_VITESSE
- PHY_OVER_CURRENT_FLAG
- PHY_PACKET_CONFIG
- PHY_PACKET_CONFIGURATION
- PHY_PACKET_LINK_ON
- PHY_PACKET_SELF_ID
- PHY_PACKET_SIZE
- PHY_PAGE_SELECT
- PHY_PAGE_SHIFT
- PHY_PAPD_EPS_TBL_SIZE_LCNPHY
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5
- PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5
- PHY_PCIE_REG_PHY0_K2_E5
- PHY_PCIE_REG_PHY1_K2_E5
- PHY_PCN
- PHY_PCR
- PHY_PCR_FORCE_CODE
- PHY_PCR_OOBS_CALI_50
- PHY_PCR_OOBS_SEN_90
- PHY_PCR_OOBS_VCM_08
- PHY_PCR_RSSI_EN
- PHY_PCR_RX10K
- PHY_PCTL
- PHY_PCTL_MASK
- PHY_PD
- PHY_PD_EN
- PHY_PERICAL_ASSOC_DELAY
- PHY_PERICAL_AUTO
- PHY_PERICAL_CHAN
- PHY_PERICAL_DISABLE
- PHY_PERICAL_DRIVERUP
- PHY_PERICAL_FULL
- PHY_PERICAL_INIT_DELAY
- PHY_PERICAL_JOIN_BSS
- PHY_PERICAL_MANUAL
- PHY_PERICAL_MPHASE
- PHY_PERICAL_MPHASE_PENDING
- PHY_PERICAL_NODELAY
- PHY_PERICAL_PARTIAL
- PHY_PERICAL_PHYINIT
- PHY_PERICAL_SPHASE
- PHY_PERICAL_START_IBSS
- PHY_PERICAL_UP_BSS
- PHY_PERICAL_WATCHDOG
- PHY_PERICAL_WDOG_DELAY
- PHY_PHYAD_MASK
- PHY_PHYAD_SHIFT
- PHY_PHYSCR
- PHY_PHYSCR_100MB
- PHY_PHYSCR_10MB
- PHY_PHYSCR_DUPLEX
- PHY_PHYSICAL_LINK_FLAG
- PHY_PHYSP_CONTROL
- PHY_PHYSP_CONTROL_DEFAULT
- PHY_PHY_CONTROL
- PHY_PHY_STATUS
- PHY_PLLCAL_DONE
- PHY_PLL_BW
- PHY_PLL_CFG
- PHY_PLL_CTRL
- PHY_PLL_LOCK
- PHY_PLL_LOCKED
- PHY_PLL_LOCK_WAIT_TIMEOUT
- PHY_PLL_LOCK_WAIT_USLEEP_MAX
- PHY_PLL_OUTPUT
- PHY_PLL_RESETB
- PHY_PLL_TIMEOUT
- PHY_PLUG_EVENT
- PHY_PLUG_IN
- PHY_PLUG_OUT
- PHY_PMA_CMN_READY
- PHY_PMA_ISO_CMN_CTRL
- PHY_PMA_ISO_LINK_MODE
- PHY_PMA_ISO_PWRST_CTRL
- PHY_PMA_ISO_RX_DATA_HI
- PHY_PMA_ISO_RX_DATA_LO
- PHY_PMA_ISO_TX_DATA_HI
- PHY_PMA_ISO_TX_DATA_LO
- PHY_PMA_ISO_XCVR_CTRL
- PHY_PMA_XCVR_PLLCLK_EN
- PHY_PMA_XCVR_PLLCLK_EN_ACK
- PHY_PMA_XCVR_POWER_STATE_ACK
- PHY_PMA_XCVR_POWER_STATE_REQ
- PHY_PMA_XCVR_TX_DEEMPH
- PHY_PMA_XCVR_TX_VMARGIN
- PHY_POLL
- PHY_POLL_LINK_OFF
- PHY_POLL_LINK_ON
- PHY_PORTS
- PHY_PORT_CS1
- PHY_PORT_CS1_LINK_DISABLE
- PHY_PORT_CS1_LINK_STATE_MASK
- PHY_PORT_CS1_LINK_STATE_SHIFT
- PHY_PORT_NUM_MA
- PHY_PORT_OFFSET
- PHY_PORT_SELECT_0
- PHY_PORT_SELECT_1
- PHY_POWERGOOD
- PHY_POWER_DOWN
- PHY_POWER_GOOD
- PHY_POWER_SAVING_DISABLE
- PHY_POWER_SAVING_ENABLE
- PHY_POWER_STATE_LN_0
- PHY_POWER_STATE_LN_1
- PHY_POWER_STATE_LN_2
- PHY_POWER_STATE_LN_3
- PHY_PREAMBLE
- PHY_PREAMBLE_SIZE
- PHY_PRE_SUP
- PHY_PULLUP_RES_SEL
- PHY_PU_CHRG_DTC
- PHY_PU_OTG
- PHY_PWRDIFF
- PHY_PWR_CLKSEL
- PHY_PWR_CTRL
- PHY_PWR_DOWN_BIT
- PHY_PWR_DWN1SEL
- PHY_PWR_DWN1SW
- PHY_PWR_DWN2
- PHY_PWR_PHYPWD
- PHY_QS6612X
- PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED
- PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED
- PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH
- PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW
- PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED
- PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH
- PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW
- PHY_QueryBBReg
- PHY_QueryBBReg_8723B
- PHY_QueryMacReg
- PHY_QueryRFReg
- PHY_QueryRFReg_8723B
- PHY_R0
- PHY_R0_PCIE_POWER_STATE
- PHY_R0_PCIE_USB3_SWITCH
- PHY_R1
- PHY_R1_PHY_LOS_BIAS
- PHY_R1_PHY_LOS_LEVEL
- PHY_R1_PHY_MPLL_MULTIPLIER
- PHY_R1_PHY_REF_CLKDIV2
- PHY_R1_PHY_RX0_EQ
- PHY_R1_PHY_RX1_EQ
- PHY_R1_PHY_TX0_TERM_OFFSET
- PHY_R1_PHY_TX1_TERM_OFFSET
- PHY_R2
- PHY_R2_PCS_TX_DEEMPH_GEN1
- PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB
- PHY_R2_PCS_TX_DEEMPH_GEN2_6DB
- PHY_R2_PHY_TX_VBOOST_LVL
- PHY_R4
- PHY_R4_PHY_CR_CAP_ADDR
- PHY_R4_PHY_CR_CAP_DATA
- PHY_R4_PHY_CR_DATA_IN
- PHY_R4_PHY_CR_READ
- PHY_R4_PHY_CR_WRITE
- PHY_R5
- PHY_R5_PHY_BS_OUT
- PHY_R5_PHY_CR_ACK
- PHY_R5_PHY_CR_DATA_OUT
- PHY_RATE_NEGO
- PHY_RAW_DATA
- PHY_RAW_H
- PHY_RAW_L
- PHY_RCR0
- PHY_RCR1
- PHY_RCR1_ADP_TIME_4
- PHY_RCR1_INIT_27S
- PHY_RCR1_VCO_COARSE
- PHY_RCR2
- PHY_RCR2_CALIB_LATE
- PHY_RCR2_CDR_SC_12P
- PHY_RCR2_CDR_SR_2
- PHY_RCR2_EMPHASE_EN
- PHY_RCR2_FREQSEL_12
- PHY_RCR2_INIT_27S
- PHY_RCR2_NADJR
- PHY_RDR
- PHY_RDR_RXDSEL_1_9
- PHY_RDY
- PHY_RDY_LINKUP_BIT
- PHY_RD_CMD
- PHY_RD_ERR
- PHY_READ
- PHY_READCOUNT_EQ_SKIP
- PHY_READY
- PHY_READY_MASK
- PHY_REALTEK_INIT1
- PHY_REALTEK_INIT10
- PHY_REALTEK_INIT11
- PHY_REALTEK_INIT2
- PHY_REALTEK_INIT3
- PHY_REALTEK_INIT4
- PHY_REALTEK_INIT5
- PHY_REALTEK_INIT6
- PHY_REALTEK_INIT7
- PHY_REALTEK_INIT8
- PHY_REALTEK_INIT9
- PHY_REALTEK_INIT_MSK1
- PHY_REALTEK_INIT_REG1
- PHY_REALTEK_INIT_REG2
- PHY_REALTEK_INIT_REG3
- PHY_REALTEK_INIT_REG4
- PHY_REALTEK_INIT_REG5
- PHY_REALTEK_INIT_REG6
- PHY_REALTEK_INIT_REG7
- PHY_REF_CLK_PERIOD_PS
- PHY_REF_CLK_RATE
- PHY_REF_PAD_BIT
- PHY_REF_SSP_EN
- PHY_REG
- PHY_REGArrayLength
- PHY_REGArrayLengthPciE
- PHY_REGISTER_MGMT_CONTROL
- PHY_REG_1T
- PHY_REG_1T2RArrayLength
- PHY_REG_1T2RArrayLengthPciE
- PHY_REG_1TARRAY_LENGTH
- PHY_REG_2T
- PHY_REG_2T2RARRAYLENGTH
- PHY_REG_2TARRAY_LENGTH
- PHY_REG_2T_ARRAYLENGTH
- PHY_REG_ADDR
- PHY_REG_ADDR_MASK
- PHY_REG_ARRAY_PGLENGTH
- PHY_REG_ARRAY_PG_LENGTH
- PHY_REG_AUTO_NEGOTIATION
- PHY_REG_CTRL
- PHY_REG_DATA
- PHY_REG_ID_1
- PHY_REG_ID_2
- PHY_REG_LINK_MD
- PHY_REG_MASK
- PHY_REG_PG
- PHY_REG_PG_EXACT_VALUE
- PHY_REG_PG_RELATIVE_VALUE
- PHY_REG_PG_TYPE
- PHY_REG_PHY_CTRL
- PHY_REG_REMOTE_CAPABILITY
- PHY_REG_RPT
- PHY_REG_SIZE
- PHY_REG_STATUS
- PHY_REMOTE_100BTX
- PHY_REMOTE_100BTX_FD
- PHY_REMOTE_10BT
- PHY_REMOTE_10BT_FD
- PHY_REMOTE_ACKNOWLEDGE
- PHY_REMOTE_ACKNOWLEDGE_NOT
- PHY_REMOTE_FAULT
- PHY_REMOTE_FAULT_DISABLE
- PHY_REMOTE_LOOPBACK
- PHY_REMOTE_NEXT_PAGE
- PHY_REMOTE_NEXT_PAGE_NOT
- PHY_REMOTE_REMOTE_FAULT
- PHY_REMOTE_REMOTE_FAULT_NOT
- PHY_REMOTE_SYM_PAUSE
- PHY_RES45_CAL_EN
- PHY_RESERVED
- PHY_RESET
- PHY_RESETB
- PHY_RESET_DELAYS_PROPERTY
- PHY_RESET_MAX_WAIT
- PHY_RESET_TIMEOUT
- PHY_RETRIES
- PHY_REV
- PHY_REVISION_MASK
- PHY_REV_CLKREQ_DT_1_0
- PHY_REV_CLKREQ_RX_EN
- PHY_REV_CLKREQ_TX_EN
- PHY_REV_ID
- PHY_REV_MASK
- PHY_REV_P1_EN
- PHY_REV_REALTEK_8211B
- PHY_REV_REALTEK_8211C
- PHY_REV_RESV
- PHY_REV_RXIDLE_EN
- PHY_REV_RXIDLE_LATCHED
- PHY_REV_RX_PWST
- PHY_REV_STOP_CLKRD
- PHY_REV_STOP_CLKWR
- PHY_RF6052SetBandwidth8723B
- PHY_RF6052_Config8723B
- PHY_RFConfig8723B
- PHY_RFR
- PHY_RFW
- PHY_RGMII
- PHY_ROLE_INITIATOR
- PHY_ROLE_NONE
- PHY_ROLE_TARGET
- PHY_RSSI_SLID_WIN_MAX
- PHY_RSSI_TABLE_SIZE
- PHY_RST
- PHY_RSTZ
- PHY_RST_ACK_BIT
- PHY_RST_AFTER_CLK_EN
- PHY_RST_HARD
- PHY_RST_POL
- PHY_RTCR
- PHY_RUNNING
- PHY_RX0_EQ_GEN1_VAL
- PHY_RX0_EQ_GEN2_VAL
- PHY_RXCLKACTIVEHS
- PHY_RXCOMCENTER_60V
- PHY_RXCOMCENTER_70V
- PHY_RXCOMCENTER_80V
- PHY_RXCOMCENTER_90V
- PHY_RXCOMCENTER_MASK
- PHY_RXULPSCLKNOT
- PHY_RX_AGC_INFO_T
- PHY_RX_ASIC_OUT
- PHY_RX_ASIC_OUT_ACK
- PHY_RX_CHAIN_CNT_MSK
- PHY_RX_CHAIN_CNT_POS
- PHY_RX_CHAIN_DRIVER_FORCE_MSK
- PHY_RX_CHAIN_DRIVER_FORCE_POS
- PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK
- PHY_RX_CHAIN_FORCE_MIMO_SEL_POS
- PHY_RX_CHAIN_FORCE_SEL_MSK
- PHY_RX_CHAIN_FORCE_SEL_POS
- PHY_RX_CHAIN_MIMO_CNT_MSK
- PHY_RX_CHAIN_MIMO_CNT_POS
- PHY_RX_CHAIN_MIMO_FORCE_MSK
- PHY_RX_CHAIN_MIMO_FORCE_POS
- PHY_RX_CHAIN_VALID_MSK
- PHY_RX_CHAIN_VALID_POS
- PHY_RX_ONLY
- PHY_RX_OVRD_IN_LO
- PHY_RX_OVRD_IN_LO_RX_DATA_EN
- PHY_RX_OVRD_IN_LO_RX_PLL_EN
- PHY_S6G_COMMON_CFG
- PHY_S6G_DFT_CFG2
- PHY_S6G_ENA_LANE_POS
- PHY_S6G_ENA_LOOP_POS
- PHY_S6G_GPC_CFG
- PHY_S6G_IB_STATUS0
- PHY_S6G_IF_MODE_POS
- PHY_S6G_LCPLL_CFG
- PHY_S6G_MISC_CFG
- PHY_S6G_PLL5G_CFG0
- PHY_S6G_PLL_CFG
- PHY_S6G_PLL_ENA_OFFS_POS
- PHY_S6G_PLL_FSM_CTRL_DATA_POS
- PHY_S6G_PLL_FSM_ENA_POS
- PHY_S6G_PLL_STATUS
- PHY_S6G_QRATE_POS
- PHY_S6G_SYS_RST_POS
- PHY_SAT
- PHY_SCR_t
- PHY_SETTING
- PHY_SFP_TX_FAULT_FLAG
- PHY_SGMII_FLAG
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5
- PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5
- PHY_SHIFT_ROUND
- PHY_SHUTDOWNZ
- PHY_SIGDET_FLTR_EN
- PHY_SINGLE_CHANNEL_CENTERED
- PHY_SKIPN
- PHY_SOF
- PHY_SPECIAL
- PHY_SPECIAL_ANEG_DONE_
- PHY_SPECIAL_INTERVAL
- PHY_SPECIAL_RES_
- PHY_SPECIAL_RES_MASK_
- PHY_SPECIAL_SPD
- PHY_SPECIAL_SPD_
- PHY_SPECIAL_SPD_100FULL
- PHY_SPECIAL_SPD_100FULL_
- PHY_SPECIAL_SPD_100HALF
- PHY_SPECIAL_SPD_100HALF_
- PHY_SPECIAL_SPD_10FULL
- PHY_SPECIAL_SPD_10FULL_
- PHY_SPECIAL_SPD_10HALF
- PHY_SPECIAL_SPD_10HALF_
- PHY_SPEED_10
- PHY_SPEED_100
- PHY_SPEED_1000
- PHY_SPEED_100MBIT
- PHY_SPEED_120
- PHY_SPEED_15
- PHY_SPEED_30
- PHY_SPEED_60
- PHY_SPEED_DUP_RESOLVE_B
- PHY_SPM
- PHY_SQUELCH_DETECT
- PHY_SSCCR2
- PHY_SSCCR2_PLL_NCODE
- PHY_SSCCR2_TIME0
- PHY_SSCCR2_TIME2_WIDTH
- PHY_SSCCR3
- PHY_SSCCR3_CHECK_DELAY
- PHY_SSCCR3_STEP_IN
- PHY_SSC_AUTO_PWD
- PHY_SSC_RSTB
- PHY_SSP_RST
- PHY_ST
- PHY_START_CABLE_DIAG
- PHY_START_CAL
- PHY_STAT1
- PHY_STAT2
- PHY_STATE
- PHY_STATES
- PHY_STATE_CONNECT
- PHY_STATE_DISCONNECT
- PHY_STATE_FS_LS_ONLINE
- PHY_STATE_HS_ONLINE
- PHY_STATE_INFO_VALID
- PHY_STATE_LINK_UP_SPC
- PHY_STATE_LINK_UP_SPCV
- PHY_STATE_MSG_SEVERITY
- PHY_STATE_OPER
- PHY_STATE_OPER_MSG_NONE
- PHY_STATE_STR
- PHY_STATE_TIME
- PHY_STATUS
- PHY_STATUS_100M
- PHY_STATUS_BIT
- PHY_STATUS_CMN_LDO
- PHY_STATUS_EMI_CA
- PHY_STATUS_RPT_8192CD_T
- PHY_STATUS_RPT_8812_T
- PHY_STATUS_SIZE
- PHY_STATUS_SPLINE_LDO
- PHY_STATUS_TIMEOUT_US
- PHY_STAT_CCK_AGC_RPT_SHT
- PHY_STAT_CFOSHO_SHT
- PHY_STAT_CFOTAIL_SHT
- PHY_STAT_CSI_CURRENT_SHT
- PHY_STAT_CSI_TARGET_SHT
- PHY_STAT_EXT_INIT
- PHY_STAT_GAIN_TRSW_SHT
- PHY_STAT_LAN_ON
- PHY_STAT_LINK_UP
- PHY_STAT_MASK
- PHY_STAT_MAX_EX_PWR_SHT
- PHY_STAT_MDIX
- PHY_STAT_PDSNR_SHT
- PHY_STAT_PWDB_ALL_SHT
- PHY_STAT_PWRDN
- PHY_STAT_REVERSED_POLARITY
- PHY_STAT_RXEVM_SHT
- PHY_STAT_RXSNR_SHT
- PHY_STAT_SIGEVM_SHT
- PHY_STOPSTATECLK
- PHY_STOPSTATEDATA
- PHY_STOPSTATEDATA_BIT
- PHY_STOP_ERR_DEVICE_ATTACHED
- PHY_STOP_STATE_CLK_LANE
- PHY_STOP_SUCCESS
- PHY_STOP_WAIT_TIME
- PHY_ST_AN_CAP
- PHY_ST_AN_OVER
- PHY_ST_EXT_REG
- PHY_ST_EXT_ST
- PHY_ST_JAB_DET
- PHY_ST_LINK
- PHY_ST_LSYNC
- PHY_ST_PRE_SUP
- PHY_ST_REM_FLT
- PHY_SUN4I_USB_H_
- PHY_SW_TIMER_FAST
- PHY_SW_TIMER_GLACIAL
- PHY_SW_TIMER_SLOW
- PHY_SetBBReg
- PHY_SetBBReg_8723B
- PHY_SetBWMode8723B
- PHY_SetMacReg
- PHY_SetRFPowerState
- PHY_SetRFReg
- PHY_SetRFReg_8723B
- PHY_SetSwChnlBWMode8723B
- PHY_SetTxPowerByRate
- PHY_SetTxPowerIndex
- PHY_SetTxPowerIndexByRateArray
- PHY_SetTxPowerIndexByRateSection
- PHY_SetTxPowerLevel8723B
- PHY_SetTxPowerLevelByPath
- PHY_SetTxPowerLimit
- PHY_Setup
- PHY_StoreTxPowerByRate
- PHY_StoreTxPowerByRateNew
- PHY_StoreTxPowerByRateOld
- PHY_SwChnl8723B
- PHY_TCR0
- PHY_TCR1
- PHY_TEGRA_XUSB_H
- PHY_TESTCLK
- PHY_TESTCLR
- PHY_TESTDIN
- PHY_TESTDOUT
- PHY_TESTEN
- PHY_TEST_ADDR
- PHY_TEST_CLK
- PHY_TEST_DATA
- PHY_TEST_PATTERN_80BIT_CUSTOM
- PHY_TEST_PATTERN_CP2520_1
- PHY_TEST_PATTERN_CP2520_2
- PHY_TEST_PATTERN_CP2520_3
- PHY_TEST_PATTERN_D10_2
- PHY_TEST_PATTERN_NONE
- PHY_TEST_PATTERN_PRBS7
- PHY_TEST_PATTERN_SYMBOL_ERROR
- PHY_TEST_PORT
- PHY_TEST_RST
- PHY_TEST_WREN
- PHY_TIMEOUT
- PHY_TMR_CFG
- PHY_TMR_LPCLK_CFG
- PHY_TO_OFF_PM_MASTER
- PHY_TO_OFF_PM_RECEIVER
- PHY_TPC_HW_OFF
- PHY_TPC_HW_ON
- PHY_TRANSMIT_DISABLE
- PHY_TRANSMIT_POWER
- PHY_TSSI_TABLE_SIZE
- PHY_TST
- PHY_TSTCLK
- PHY_TST_CTRL0
- PHY_TST_CTRL1
- PHY_TUNE
- PHY_TUNE_D18_1V7
- PHY_TUNE_D18_1V8
- PHY_TUNE_SDBUS_33
- PHY_TUNE_TUNEA12
- PHY_TUNE_TUNED12
- PHY_TUNE_TUNED18
- PHY_TUNE_TUNEREF_1_0
- PHY_TUNE_VBGSEL_1252
- PHY_TUNE_VOLTAGE_3V3
- PHY_TUNE_VOLTAGE_MASK
- PHY_TURNAROUND
- PHY_TX0_TERM_OFFST_VAL
- PHY_TXC1_BW_10MHZ
- PHY_TXC1_BW_10MHZ_UP
- PHY_TXC1_BW_20MHZ
- PHY_TXC1_BW_20MHZ_UP
- PHY_TXC1_BW_40MHZ
- PHY_TXC1_BW_40MHZ_DUP
- PHY_TXC1_BW_MASK
- PHY_TXC1_MODE_CDD
- PHY_TXC1_MODE_MASK
- PHY_TXC1_MODE_SDM
- PHY_TXC1_MODE_SHIFT
- PHY_TXC1_MODE_SISO
- PHY_TXC1_MODE_STBC
- PHY_TXC_ANT_0
- PHY_TXC_ANT_0_1
- PHY_TXC_ANT_1
- PHY_TXC_ANT_2
- PHY_TXC_ANT_3
- PHY_TXC_ANT_MASK
- PHY_TXC_ANT_SHIFT
- PHY_TXC_HTANT_MASK
- PHY_TXC_LCNPHY_ANT_LAST
- PHY_TXC_OLD_ANT_0
- PHY_TXC_OLD_ANT_1
- PHY_TXC_OLD_ANT_LAST
- PHY_TXC_PWR_MASK
- PHY_TXC_PWR_SHIFT
- PHY_TXC_SHORT_HDR
- PHY_TXPWR
- PHY_TXPWR_MIN
- PHY_TXPWR_MIN_NPHY
- PHY_TXREQUESTCLKHS
- PHY_TX_AMPLITUDE_TUNE
- PHY_TX_ASIC_OUT
- PHY_TX_ASIC_OUT_TX_ACK
- PHY_TX_NORMAL_POLARITY
- PHY_TX_ONLY
- PHY_TX_POLARITY_MASK
- PHY_TX_SLEWRATE_TUNE
- PHY_TYPE
- PHY_TYPE_88E1111
- PHY_TYPE_A
- PHY_TYPE_BASET_10GB
- PHY_TYPE_BASET_1GB
- PHY_TYPE_BASEX_1GB
- PHY_TYPE_CX4_10GB
- PHY_TYPE_DISABLED
- PHY_TYPE_G
- PHY_TYPE_HT
- PHY_TYPE_KR2_20GB
- PHY_TYPE_KR4_40GB
- PHY_TYPE_KR_10GB
- PHY_TYPE_KX4_10GB
- PHY_TYPE_LCN
- PHY_TYPE_LCNXN
- PHY_TYPE_LP
- PHY_TYPE_MAX
- PHY_TYPE_MII
- PHY_TYPE_N
- PHY_TYPE_NONE
- PHY_TYPE_NULL
- PHY_TYPE_PCIE
- PHY_TYPE_PCIE_PHY
- PHY_TYPE_PCS
- PHY_TYPE_PHYSICAL
- PHY_TYPE_PM8358
- PHY_TYPE_PMA_PMD
- PHY_TYPE_QSFP
- PHY_TYPE_QT2022C2
- PHY_TYPE_QT2025C
- PHY_TYPE_SATA
- PHY_TYPE_SFP_1GB
- PHY_TYPE_SFP_PLUS_10GB
- PHY_TYPE_SFT9001A
- PHY_TYPE_SFT9001B
- PHY_TYPE_SFX7101
- PHY_TYPE_SGMII
- PHY_TYPE_SSN
- PHY_TYPE_TN_8022
- PHY_TYPE_TXC43128
- PHY_TYPE_UFS
- PHY_TYPE_UNIPHY
- PHY_TYPE_UNKNOWN
- PHY_TYPE_USB2
- PHY_TYPE_USB3
- PHY_TYPE_VIRTUAL
- PHY_TYPE_XFP_10GB
- PHY_TxPowerByRateConfiguration
- PHY_UNRSTZ
- PHY_UNSHUTDOWNZ
- PHY_UNTESTCLK
- PHY_UNTESTCLR
- PHY_UNTESTEN
- PHY_UP
- PHY_UPPER_SHIFT
- PHY_VACANT
- PHY_VBUSVALID_TH_SEL
- PHY_VBUS_DET_EN
- PHY_VEND_AQUANTIA
- PHY_VERSION
- PHY_VER_LEN
- PHY_VER_STR_LEN
- PHY_VHT_CHANNEL_MODE160
- PHY_VHT_CHANNEL_MODE20
- PHY_VHT_CHANNEL_MODE40
- PHY_VHT_CHANNEL_MODE80
- PHY_VHT_CTRL_POS_1_ABOVE
- PHY_VHT_CTRL_POS_1_BELOW
- PHY_VHT_CTRL_POS_2_ABOVE
- PHY_VHT_CTRL_POS_2_BELOW
- PHY_VHT_CTRL_POS_3_ABOVE
- PHY_VHT_CTRL_POS_3_BELOW
- PHY_VHT_CTRL_POS_4_ABOVE
- PHY_VHT_CTRL_POS_4_BELOW
- PHY_VITESSE_INIT1
- PHY_VITESSE_INIT10
- PHY_VITESSE_INIT2
- PHY_VITESSE_INIT3
- PHY_VITESSE_INIT4
- PHY_VITESSE_INIT5
- PHY_VITESSE_INIT6
- PHY_VITESSE_INIT7
- PHY_VITESSE_INIT8
- PHY_VITESSE_INIT9
- PHY_VITESSE_INIT_MSK1
- PHY_VITESSE_INIT_MSK2
- PHY_VITESSE_INIT_REG1
- PHY_VITESSE_INIT_REG2
- PHY_VITESSE_INIT_REG3
- PHY_VITESSE_INIT_REG4
- PHY_VITESSE_VSC8211
- PHY_WAIT_ITERATIONS
- PHY_WREG_LIMIT
- PHY_WRITE
- PHY_WRITE_PREVIOUS
- PHY_WR_CMD
- PHY_XGXS_FLAG
- PHY_XMAC_AUNE_ADV
- PHY_XMAC_AUNE_EXP
- PHY_XMAC_AUNE_LP
- PHY_XMAC_CTRL
- PHY_XMAC_EXT_STAT
- PHY_XMAC_ID0
- PHY_XMAC_ID1
- PHY_XMAC_NEPG
- PHY_XMAC_NEPG_LP
- PHY_XMAC_RES_ABI
- PHY_XMAC_STAT
- PHY_X_AN_ACK
- PHY_X_AN_FD
- PHY_X_AN_HD
- PHY_X_AN_NXT_PG
- PHY_X_AN_PAUSE
- PHY_X_AN_RFB
- PHY_X_EX_FD
- PHY_X_EX_HD
- PHY_X_P_ASYM_MD
- PHY_X_P_BOTH_MD
- PHY_X_P_NO_PAUSE
- PHY_X_P_SYM_MD
- PHY_X_RS_ABLMIS
- PHY_X_RS_FD
- PHY_X_RS_HD
- PHY_X_RS_PAUMIS
- PHY_X_RS_PAUSE
- PHYstatus
- PH_ABORT
- PH_ACTIVATE_CNF
- PH_ACTIVATE_IND
- PH_ACTIVATE_REQ
- PH_ADDR_PR_1_FMT
- PH_ADDR_PR_3_FMT
- PH_ADDR_PR_4_FMT
- PH_ADDR_SCAN_FMT
- PH_ARBSTART
- PH_BASE
- PH_BUS_FREE
- PH_COMMAND
- PH_CONTROL_CNF
- PH_CONTROL_IND
- PH_CONTROL_REQ
- PH_DATA
- PH_DATA_CNF
- PH_DATA_E_IND
- PH_DATA_IN
- PH_DATA_IND
- PH_DATA_OUT
- PH_DATA_REQ
- PH_DEACTIVATE_CNF
- PH_DEACTIVATE_IND
- PH_DEACTIVATE_REQ
- PH_DISCONNECT
- PH_FILESZ
- PH_HEAD
- PH_HSIZE
- PH_IOC_MAGIC
- PH_MSG_IN
- PH_MSG_OUT
- PH_OFFSET
- PH_PERFCNT_SEL
- PH_RESELECT
- PH_RESET
- PH_SC0_ARB_BUSY
- PH_SC0_ARB_EOP_POP_SYNC_POP
- PH_SC0_ARB_EVENT_SYNC_POP
- PH_SC0_ARB_PA_BUSY_SOP
- PH_SC0_ARB_STALLED_FROM_BELOW
- PH_SC0_ARB_STARVED_FROM_ABOVE
- PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC0_BUSY_CNT_NOT_ZERO
- PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC0_CREDIT_AT_MAX
- PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC0_EOP_SYNC_WINDOW
- PH_SC0_GFX_PIPE0_TO_1_TRANSITION
- PH_SC0_GFX_PIPE1_TO_0_TRANSITION
- PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION
- PH_SC0_PA0_DATA_FIFO_EOP_RD
- PH_SC0_PA0_DATA_FIFO_RD
- PH_SC0_PA0_DATA_FIFO_WE
- PH_SC0_PA0_DEALLOC_4_0_RD
- PH_SC0_PA0_EOPG_WE
- PH_SC0_PA0_EOP_WE
- PH_SC0_PA0_EVENT_WE
- PH_SC0_PA0_FIFO_EMPTY
- PH_SC0_PA0_FIFO_FULL
- PH_SC0_PA0_FPOV_WE
- PH_SC0_PA0_LPOV_WE
- PH_SC0_PA0_NULL_WE
- PH_SC0_PA1_DATA_FIFO_EOP_RD
- PH_SC0_PA1_DATA_FIFO_RD
- PH_SC0_PA1_DATA_FIFO_WE
- PH_SC0_PA1_DEALLOC_4_0_RD
- PH_SC0_PA1_EOPG_WE
- PH_SC0_PA1_EOP_WE
- PH_SC0_PA1_EVENT_WE
- PH_SC0_PA1_FIFO_EMPTY
- PH_SC0_PA1_FIFO_FULL
- PH_SC0_PA1_FPOV_WE
- PH_SC0_PA1_LPOV_WE
- PH_SC0_PA1_NULL_WE
- PH_SC0_PA2_DATA_FIFO_EOP_RD
- PH_SC0_PA2_DATA_FIFO_RD
- PH_SC0_PA2_DATA_FIFO_WE
- PH_SC0_PA2_DEALLOC_4_0_RD
- PH_SC0_PA2_EOPG_WE
- PH_SC0_PA2_EOP_WE
- PH_SC0_PA2_EVENT_WE
- PH_SC0_PA2_FIFO_EMPTY
- PH_SC0_PA2_FIFO_FULL
- PH_SC0_PA2_FPOV_WE
- PH_SC0_PA2_LPOV_WE
- PH_SC0_PA2_NULL_WE
- PH_SC0_PA3_DATA_FIFO_EOP_RD
- PH_SC0_PA3_DATA_FIFO_RD
- PH_SC0_PA3_DATA_FIFO_WE
- PH_SC0_PA3_DEALLOC_4_0_RD
- PH_SC0_PA3_EOPG_WE
- PH_SC0_PA3_EOP_WE
- PH_SC0_PA3_EVENT_WE
- PH_SC0_PA3_FIFO_EMPTY
- PH_SC0_PA3_FIFO_FULL
- PH_SC0_PA3_FPOV_WE
- PH_SC0_PA3_LPOV_WE
- PH_SC0_PA3_NULL_WE
- PH_SC0_PA4_DATA_FIFO_EOP_RD
- PH_SC0_PA4_DATA_FIFO_RD
- PH_SC0_PA4_DATA_FIFO_WE
- PH_SC0_PA4_DEALLOC_4_0_RD
- PH_SC0_PA4_EOPG_WE
- PH_SC0_PA4_EOP_WE
- PH_SC0_PA4_EVENT_WE
- PH_SC0_PA4_FIFO_EMPTY
- PH_SC0_PA4_FIFO_FULL
- PH_SC0_PA4_FPOV_WE
- PH_SC0_PA4_LPOV_WE
- PH_SC0_PA4_NULL_WE
- PH_SC0_PA5_DATA_FIFO_EOP_RD
- PH_SC0_PA5_DATA_FIFO_RD
- PH_SC0_PA5_DATA_FIFO_WE
- PH_SC0_PA5_DEALLOC_4_0_RD
- PH_SC0_PA5_EOPG_WE
- PH_SC0_PA5_EOP_WE
- PH_SC0_PA5_EVENT_WE
- PH_SC0_PA5_FIFO_EMPTY
- PH_SC0_PA5_FIFO_FULL
- PH_SC0_PA5_FPOV_WE
- PH_SC0_PA5_LPOV_WE
- PH_SC0_PA5_NULL_WE
- PH_SC0_PA6_DATA_FIFO_EOP_RD
- PH_SC0_PA6_DATA_FIFO_RD
- PH_SC0_PA6_DATA_FIFO_WE
- PH_SC0_PA6_DEALLOC_4_0_RD
- PH_SC0_PA6_EOPG_WE
- PH_SC0_PA6_EOP_WE
- PH_SC0_PA6_EVENT_WE
- PH_SC0_PA6_FIFO_EMPTY
- PH_SC0_PA6_FIFO_FULL
- PH_SC0_PA6_FPOV_WE
- PH_SC0_PA6_LPOV_WE
- PH_SC0_PA6_NULL_WE
- PH_SC0_PA7_DATA_FIFO_EOP_RD
- PH_SC0_PA7_DATA_FIFO_RD
- PH_SC0_PA7_DATA_FIFO_WE
- PH_SC0_PA7_DEALLOC_4_0_RD
- PH_SC0_PA7_EOPG_WE
- PH_SC0_PA7_EOP_WE
- PH_SC0_PA7_EVENT_WE
- PH_SC0_PA7_FIFO_EMPTY
- PH_SC0_PA7_FIFO_FULL
- PH_SC0_PA7_FPOV_WE
- PH_SC0_PA7_LPOV_WE
- PH_SC0_PA7_NULL_WE
- PH_SC0_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC0_SEND
- PH_SC0_SRPS_WINDOW_VALID
- PH_SC1_ARB_BUSY
- PH_SC1_ARB_EOP_POP_SYNC_POP
- PH_SC1_ARB_EVENT_SYNC_POP
- PH_SC1_ARB_PA_BUSY_SOP
- PH_SC1_ARB_STALLED_FROM_BELOW
- PH_SC1_ARB_STARVED_FROM_ABOVE
- PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC1_BUSY_CNT_NOT_ZERO
- PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC1_CREDIT_AT_MAX
- PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC1_EOP_SYNC_WINDOW
- PH_SC1_GFX_PIPE0_TO_1_TRANSITION
- PH_SC1_GFX_PIPE1_TO_0_TRANSITION
- PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC1_PA0_DATA_FIFO_EOP_RD
- PH_SC1_PA0_DATA_FIFO_RD
- PH_SC1_PA0_DATA_FIFO_WE
- PH_SC1_PA0_DEALLOC_4_0_RD
- PH_SC1_PA0_EOPG_WE
- PH_SC1_PA0_EOP_WE
- PH_SC1_PA0_EVENT_WE
- PH_SC1_PA0_FIFO_EMPTY
- PH_SC1_PA0_FIFO_FULL
- PH_SC1_PA0_FPOV_WE
- PH_SC1_PA0_LPOV_WE
- PH_SC1_PA0_NULL_WE
- PH_SC1_PA1_DATA_FIFO_EOP_RD
- PH_SC1_PA1_DATA_FIFO_RD
- PH_SC1_PA1_DATA_FIFO_WE
- PH_SC1_PA1_DEALLOC_4_0_RD
- PH_SC1_PA1_EOPG_WE
- PH_SC1_PA1_EOP_WE
- PH_SC1_PA1_EVENT_WE
- PH_SC1_PA1_FIFO_EMPTY
- PH_SC1_PA1_FIFO_FULL
- PH_SC1_PA1_FPOV_WE
- PH_SC1_PA1_LPOV_WE
- PH_SC1_PA1_NULL_WE
- PH_SC1_PA2_DATA_FIFO_EOP_RD
- PH_SC1_PA2_DATA_FIFO_RD
- PH_SC1_PA2_DATA_FIFO_WE
- PH_SC1_PA2_DEALLOC_4_0_RD
- PH_SC1_PA2_EOPG_WE
- PH_SC1_PA2_EOP_WE
- PH_SC1_PA2_EVENT_WE
- PH_SC1_PA2_FIFO_EMPTY
- PH_SC1_PA2_FIFO_FULL
- PH_SC1_PA2_FPOV_WE
- PH_SC1_PA2_LPOV_WE
- PH_SC1_PA2_NULL_WE
- PH_SC1_PA3_DATA_FIFO_EOP_RD
- PH_SC1_PA3_DATA_FIFO_RD
- PH_SC1_PA3_DATA_FIFO_WE
- PH_SC1_PA3_DEALLOC_4_0_RD
- PH_SC1_PA3_EOPG_WE
- PH_SC1_PA3_EOP_WE
- PH_SC1_PA3_EVENT_WE
- PH_SC1_PA3_FIFO_EMPTY
- PH_SC1_PA3_FIFO_FULL
- PH_SC1_PA3_FPOV_WE
- PH_SC1_PA3_LPOV_WE
- PH_SC1_PA3_NULL_WE
- PH_SC1_PA4_DATA_FIFO_EOP_RD
- PH_SC1_PA4_DATA_FIFO_RD
- PH_SC1_PA4_DATA_FIFO_WE
- PH_SC1_PA4_DEALLOC_4_0_RD
- PH_SC1_PA4_EOPG_WE
- PH_SC1_PA4_EOP_WE
- PH_SC1_PA4_EVENT_WE
- PH_SC1_PA4_FIFO_EMPTY
- PH_SC1_PA4_FIFO_FULL
- PH_SC1_PA4_FPOV_WE
- PH_SC1_PA4_LPOV_WE
- PH_SC1_PA4_NULL_WE
- PH_SC1_PA5_DATA_FIFO_EOP_RD
- PH_SC1_PA5_DATA_FIFO_RD
- PH_SC1_PA5_DATA_FIFO_WE
- PH_SC1_PA5_DEALLOC_4_0_RD
- PH_SC1_PA5_EOPG_WE
- PH_SC1_PA5_EOP_WE
- PH_SC1_PA5_EVENT_WE
- PH_SC1_PA5_FIFO_EMPTY
- PH_SC1_PA5_FIFO_FULL
- PH_SC1_PA5_FPOV_WE
- PH_SC1_PA5_LPOV_WE
- PH_SC1_PA5_NULL_WE
- PH_SC1_PA6_DATA_FIFO_EOP_RD
- PH_SC1_PA6_DATA_FIFO_RD
- PH_SC1_PA6_DATA_FIFO_WE
- PH_SC1_PA6_DEALLOC_4_0_RD
- PH_SC1_PA6_EOPG_WE
- PH_SC1_PA6_EOP_WE
- PH_SC1_PA6_EVENT_WE
- PH_SC1_PA6_FIFO_EMPTY
- PH_SC1_PA6_FIFO_FULL
- PH_SC1_PA6_FPOV_WE
- PH_SC1_PA6_LPOV_WE
- PH_SC1_PA6_NULL_WE
- PH_SC1_PA7_DATA_FIFO_EOP_RD
- PH_SC1_PA7_DATA_FIFO_RD
- PH_SC1_PA7_DATA_FIFO_WE
- PH_SC1_PA7_DEALLOC_4_0_RD
- PH_SC1_PA7_EOPG_WE
- PH_SC1_PA7_EOP_WE
- PH_SC1_PA7_EVENT_WE
- PH_SC1_PA7_FIFO_EMPTY
- PH_SC1_PA7_FIFO_FULL
- PH_SC1_PA7_FPOV_WE
- PH_SC1_PA7_LPOV_WE
- PH_SC1_PA7_NULL_WE
- PH_SC1_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC1_SEND
- PH_SC1_SRPS_WINDOW_VALID
- PH_SC2_ARB_BUSY
- PH_SC2_ARB_EOP_POP_SYNC_POP
- PH_SC2_ARB_EVENT_SYNC_POP
- PH_SC2_ARB_PA_BUSY_SOP
- PH_SC2_ARB_STALLED_FROM_BELOW
- PH_SC2_ARB_STARVED_FROM_ABOVE
- PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC2_BUSY_CNT_NOT_ZERO
- PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC2_CREDIT_AT_MAX
- PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC2_EOP_SYNC_WINDOW
- PH_SC2_GFX_PIPE0_TO_1_TRANSITION
- PH_SC2_GFX_PIPE1_TO_0_TRANSITION
- PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC2_PA0_DATA_FIFO_EOP_RD
- PH_SC2_PA0_DATA_FIFO_RD
- PH_SC2_PA0_DATA_FIFO_WE
- PH_SC2_PA0_DEALLOC_4_0_RD
- PH_SC2_PA0_EOPG_WE
- PH_SC2_PA0_EOP_WE
- PH_SC2_PA0_EVENT_WE
- PH_SC2_PA0_FIFO_EMPTY
- PH_SC2_PA0_FIFO_FULL
- PH_SC2_PA0_FPOV_WE
- PH_SC2_PA0_LPOV_WE
- PH_SC2_PA0_NULL_WE
- PH_SC2_PA1_DATA_FIFO_EOP_RD
- PH_SC2_PA1_DATA_FIFO_RD
- PH_SC2_PA1_DATA_FIFO_WE
- PH_SC2_PA1_DEALLOC_4_0_RD
- PH_SC2_PA1_EOPG_WE
- PH_SC2_PA1_EOP_WE
- PH_SC2_PA1_EVENT_WE
- PH_SC2_PA1_FIFO_EMPTY
- PH_SC2_PA1_FIFO_FULL
- PH_SC2_PA1_FPOV_WE
- PH_SC2_PA1_LPOV_WE
- PH_SC2_PA1_NULL_WE
- PH_SC2_PA2_DATA_FIFO_EOP_RD
- PH_SC2_PA2_DATA_FIFO_RD
- PH_SC2_PA2_DATA_FIFO_WE
- PH_SC2_PA2_DEALLOC_4_0_RD
- PH_SC2_PA2_EOPG_WE
- PH_SC2_PA2_EOP_WE
- PH_SC2_PA2_EVENT_WE
- PH_SC2_PA2_FIFO_EMPTY
- PH_SC2_PA2_FIFO_FULL
- PH_SC2_PA2_FPOV_WE
- PH_SC2_PA2_LPOV_WE
- PH_SC2_PA2_NULL_WE
- PH_SC2_PA3_DATA_FIFO_EOP_RD
- PH_SC2_PA3_DATA_FIFO_RD
- PH_SC2_PA3_DATA_FIFO_WE
- PH_SC2_PA3_DEALLOC_4_0_RD
- PH_SC2_PA3_EOPG_WE
- PH_SC2_PA3_EOP_WE
- PH_SC2_PA3_EVENT_WE
- PH_SC2_PA3_FIFO_EMPTY
- PH_SC2_PA3_FIFO_FULL
- PH_SC2_PA3_FPOV_WE
- PH_SC2_PA3_LPOV_WE
- PH_SC2_PA3_NULL_WE
- PH_SC2_PA4_DATA_FIFO_EOP_RD
- PH_SC2_PA4_DATA_FIFO_RD
- PH_SC2_PA4_DATA_FIFO_WE
- PH_SC2_PA4_DEALLOC_4_0_RD
- PH_SC2_PA4_EOPG_WE
- PH_SC2_PA4_EOP_WE
- PH_SC2_PA4_EVENT_WE
- PH_SC2_PA4_FIFO_EMPTY
- PH_SC2_PA4_FIFO_FULL
- PH_SC2_PA4_FPOV_WE
- PH_SC2_PA4_LPOV_WE
- PH_SC2_PA4_NULL_WE
- PH_SC2_PA5_DATA_FIFO_EOP_RD
- PH_SC2_PA5_DATA_FIFO_RD
- PH_SC2_PA5_DATA_FIFO_WE
- PH_SC2_PA5_DEALLOC_4_0_RD
- PH_SC2_PA5_EOPG_WE
- PH_SC2_PA5_EOP_WE
- PH_SC2_PA5_EVENT_WE
- PH_SC2_PA5_FIFO_EMPTY
- PH_SC2_PA5_FIFO_FULL
- PH_SC2_PA5_FPOV_WE
- PH_SC2_PA5_LPOV_WE
- PH_SC2_PA5_NULL_WE
- PH_SC2_PA6_DATA_FIFO_EOP_RD
- PH_SC2_PA6_DATA_FIFO_RD
- PH_SC2_PA6_DATA_FIFO_WE
- PH_SC2_PA6_DEALLOC_4_0_RD
- PH_SC2_PA6_EOPG_WE
- PH_SC2_PA6_EOP_WE
- PH_SC2_PA6_EVENT_WE
- PH_SC2_PA6_FIFO_EMPTY
- PH_SC2_PA6_FIFO_FULL
- PH_SC2_PA6_FPOV_WE
- PH_SC2_PA6_LPOV_WE
- PH_SC2_PA6_NULL_WE
- PH_SC2_PA7_DATA_FIFO_EOP_RD
- PH_SC2_PA7_DATA_FIFO_RD
- PH_SC2_PA7_DATA_FIFO_WE
- PH_SC2_PA7_DEALLOC_4_0_RD
- PH_SC2_PA7_EOPG_WE
- PH_SC2_PA7_EOP_WE
- PH_SC2_PA7_EVENT_WE
- PH_SC2_PA7_FIFO_EMPTY
- PH_SC2_PA7_FIFO_FULL
- PH_SC2_PA7_FPOV_WE
- PH_SC2_PA7_LPOV_WE
- PH_SC2_PA7_NULL_WE
- PH_SC2_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC2_SEND
- PH_SC2_SRPS_WINDOW_VALID
- PH_SC3_ARB_BUSY
- PH_SC3_ARB_EOP_POP_SYNC_POP
- PH_SC3_ARB_EVENT_SYNC_POP
- PH_SC3_ARB_PA_BUSY_SOP
- PH_SC3_ARB_STALLED_FROM_BELOW
- PH_SC3_ARB_STARVED_FROM_ABOVE
- PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC3_BUSY_CNT_NOT_ZERO
- PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC3_CREDIT_AT_MAX
- PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC3_EOP_SYNC_WINDOW
- PH_SC3_GFX_PIPE0_TO_1_TRANSITION
- PH_SC3_GFX_PIPE1_TO_0_TRANSITION
- PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC3_PA0_DATA_FIFO_EOP_RD
- PH_SC3_PA0_DATA_FIFO_RD
- PH_SC3_PA0_DATA_FIFO_WE
- PH_SC3_PA0_DEALLOC_4_0_RD
- PH_SC3_PA0_EOPG_WE
- PH_SC3_PA0_EOP_WE
- PH_SC3_PA0_EVENT_WE
- PH_SC3_PA0_FIFO_EMPTY
- PH_SC3_PA0_FIFO_FULL
- PH_SC3_PA0_FPOV_WE
- PH_SC3_PA0_LPOV_WE
- PH_SC3_PA0_NULL_WE
- PH_SC3_PA1_DATA_FIFO_EOP_RD
- PH_SC3_PA1_DATA_FIFO_RD
- PH_SC3_PA1_DATA_FIFO_WE
- PH_SC3_PA1_DEALLOC_4_0_RD
- PH_SC3_PA1_EOPG_WE
- PH_SC3_PA1_EOP_WE
- PH_SC3_PA1_EVENT_WE
- PH_SC3_PA1_FIFO_EMPTY
- PH_SC3_PA1_FIFO_FULL
- PH_SC3_PA1_FPOV_WE
- PH_SC3_PA1_LPOV_WE
- PH_SC3_PA1_NULL_WE
- PH_SC3_PA2_DATA_FIFO_EOP_RD
- PH_SC3_PA2_DATA_FIFO_RD
- PH_SC3_PA2_DATA_FIFO_WE
- PH_SC3_PA2_DEALLOC_4_0_RD
- PH_SC3_PA2_EOPG_WE
- PH_SC3_PA2_EOP_WE
- PH_SC3_PA2_EVENT_WE
- PH_SC3_PA2_FIFO_EMPTY
- PH_SC3_PA2_FIFO_FULL
- PH_SC3_PA2_FPOV_WE
- PH_SC3_PA2_LPOV_WE
- PH_SC3_PA2_NULL_WE
- PH_SC3_PA3_DATA_FIFO_EOP_RD
- PH_SC3_PA3_DATA_FIFO_RD
- PH_SC3_PA3_DATA_FIFO_WE
- PH_SC3_PA3_DEALLOC_4_0_RD
- PH_SC3_PA3_EOPG_WE
- PH_SC3_PA3_EOP_WE
- PH_SC3_PA3_EVENT_WE
- PH_SC3_PA3_FIFO_EMPTY
- PH_SC3_PA3_FIFO_FULL
- PH_SC3_PA3_FPOV_WE
- PH_SC3_PA3_LPOV_WE
- PH_SC3_PA3_NULL_WE
- PH_SC3_PA4_DATA_FIFO_EOP_RD
- PH_SC3_PA4_DATA_FIFO_RD
- PH_SC3_PA4_DATA_FIFO_WE
- PH_SC3_PA4_DEALLOC_4_0_RD
- PH_SC3_PA4_EOPG_WE
- PH_SC3_PA4_EOP_WE
- PH_SC3_PA4_EVENT_WE
- PH_SC3_PA4_FIFO_EMPTY
- PH_SC3_PA4_FIFO_FULL
- PH_SC3_PA4_FPOV_WE
- PH_SC3_PA4_LPOV_WE
- PH_SC3_PA4_NULL_WE
- PH_SC3_PA5_DATA_FIFO_EOP_RD
- PH_SC3_PA5_DATA_FIFO_RD
- PH_SC3_PA5_DATA_FIFO_WE
- PH_SC3_PA5_DEALLOC_4_0_RD
- PH_SC3_PA5_EOPG_WE
- PH_SC3_PA5_EOP_WE
- PH_SC3_PA5_EVENT_WE
- PH_SC3_PA5_FIFO_EMPTY
- PH_SC3_PA5_FIFO_FULL
- PH_SC3_PA5_FPOV_WE
- PH_SC3_PA5_LPOV_WE
- PH_SC3_PA5_NULL_WE
- PH_SC3_PA6_DATA_FIFO_EOP_RD
- PH_SC3_PA6_DATA_FIFO_RD
- PH_SC3_PA6_DATA_FIFO_WE
- PH_SC3_PA6_DEALLOC_4_0_RD
- PH_SC3_PA6_EOPG_WE
- PH_SC3_PA6_EOP_WE
- PH_SC3_PA6_EVENT_WE
- PH_SC3_PA6_FIFO_EMPTY
- PH_SC3_PA6_FIFO_FULL
- PH_SC3_PA6_FPOV_WE
- PH_SC3_PA6_LPOV_WE
- PH_SC3_PA6_NULL_WE
- PH_SC3_PA7_DATA_FIFO_EOP_RD
- PH_SC3_PA7_DATA_FIFO_RD
- PH_SC3_PA7_DATA_FIFO_WE
- PH_SC3_PA7_DEALLOC_4_0_RD
- PH_SC3_PA7_EOPG_WE
- PH_SC3_PA7_EOP_WE
- PH_SC3_PA7_EVENT_WE
- PH_SC3_PA7_FIFO_EMPTY
- PH_SC3_PA7_FIFO_FULL
- PH_SC3_PA7_FPOV_WE
- PH_SC3_PA7_LPOV_WE
- PH_SC3_PA7_NULL_WE
- PH_SC3_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC3_SEND
- PH_SC3_SRPS_WINDOW_VALID
- PH_SC4_ARB_BUSY
- PH_SC4_ARB_EOP_POP_SYNC_POP
- PH_SC4_ARB_EVENT_SYNC_POP
- PH_SC4_ARB_PA_BUSY_SOP
- PH_SC4_ARB_STALLED_FROM_BELOW
- PH_SC4_ARB_STARVED_FROM_ABOVE
- PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC4_BUSY_CNT_NOT_ZERO
- PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC4_CREDIT_AT_MAX
- PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC4_EOP_SYNC_WINDOW
- PH_SC4_GFX_PIPE0_TO_1_TRANSITION
- PH_SC4_GFX_PIPE1_TO_0_TRANSITION
- PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC4_PA0_DATA_FIFO_EOP_RD
- PH_SC4_PA0_DATA_FIFO_RD
- PH_SC4_PA0_DATA_FIFO_WE
- PH_SC4_PA0_DEALLOC_4_0_RD
- PH_SC4_PA0_EOPG_WE
- PH_SC4_PA0_EOP_WE
- PH_SC4_PA0_EVENT_WE
- PH_SC4_PA0_FIFO_EMPTY
- PH_SC4_PA0_FIFO_FULL
- PH_SC4_PA0_FPOV_WE
- PH_SC4_PA0_LPOV_WE
- PH_SC4_PA0_NULL_WE
- PH_SC4_PA1_DATA_FIFO_EOP_RD
- PH_SC4_PA1_DATA_FIFO_RD
- PH_SC4_PA1_DATA_FIFO_WE
- PH_SC4_PA1_DEALLOC_4_0_RD
- PH_SC4_PA1_EOPG_WE
- PH_SC4_PA1_EOP_WE
- PH_SC4_PA1_EVENT_WE
- PH_SC4_PA1_FIFO_EMPTY
- PH_SC4_PA1_FIFO_FULL
- PH_SC4_PA1_FPOV_WE
- PH_SC4_PA1_LPOV_WE
- PH_SC4_PA1_NULL_WE
- PH_SC4_PA2_DATA_FIFO_EOP_RD
- PH_SC4_PA2_DATA_FIFO_RD
- PH_SC4_PA2_DATA_FIFO_WE
- PH_SC4_PA2_DEALLOC_4_0_RD
- PH_SC4_PA2_EOPG_WE
- PH_SC4_PA2_EOP_WE
- PH_SC4_PA2_EVENT_WE
- PH_SC4_PA2_FIFO_EMPTY
- PH_SC4_PA2_FIFO_FULL
- PH_SC4_PA2_FPOV_WE
- PH_SC4_PA2_LPOV_WE
- PH_SC4_PA2_NULL_WE
- PH_SC4_PA3_DATA_FIFO_EOP_RD
- PH_SC4_PA3_DATA_FIFO_RD
- PH_SC4_PA3_DATA_FIFO_WE
- PH_SC4_PA3_DEALLOC_4_0_RD
- PH_SC4_PA3_EOPG_WE
- PH_SC4_PA3_EOP_WE
- PH_SC4_PA3_EVENT_WE
- PH_SC4_PA3_FIFO_EMPTY
- PH_SC4_PA3_FIFO_FULL
- PH_SC4_PA3_FPOV_WE
- PH_SC4_PA3_LPOV_WE
- PH_SC4_PA3_NULL_WE
- PH_SC4_PA4_DATA_FIFO_EOP_RD
- PH_SC4_PA4_DATA_FIFO_RD
- PH_SC4_PA4_DATA_FIFO_WE
- PH_SC4_PA4_DEALLOC_4_0_RD
- PH_SC4_PA4_EOPG_WE
- PH_SC4_PA4_EOP_WE
- PH_SC4_PA4_EVENT_WE
- PH_SC4_PA4_FIFO_EMPTY
- PH_SC4_PA4_FIFO_FULL
- PH_SC4_PA4_FPOV_WE
- PH_SC4_PA4_LPOV_WE
- PH_SC4_PA4_NULL_WE
- PH_SC4_PA5_DATA_FIFO_EOP_RD
- PH_SC4_PA5_DATA_FIFO_RD
- PH_SC4_PA5_DATA_FIFO_WE
- PH_SC4_PA5_DEALLOC_4_0_RD
- PH_SC4_PA5_EOPG_WE
- PH_SC4_PA5_EOP_WE
- PH_SC4_PA5_EVENT_WE
- PH_SC4_PA5_FIFO_EMPTY
- PH_SC4_PA5_FIFO_FULL
- PH_SC4_PA5_FPOV_WE
- PH_SC4_PA5_LPOV_WE
- PH_SC4_PA5_NULL_WE
- PH_SC4_PA6_DATA_FIFO_EOP_RD
- PH_SC4_PA6_DATA_FIFO_RD
- PH_SC4_PA6_DATA_FIFO_WE
- PH_SC4_PA6_DEALLOC_4_0_RD
- PH_SC4_PA6_EOPG_WE
- PH_SC4_PA6_EOP_WE
- PH_SC4_PA6_EVENT_WE
- PH_SC4_PA6_FIFO_EMPTY
- PH_SC4_PA6_FIFO_FULL
- PH_SC4_PA6_FPOV_WE
- PH_SC4_PA6_LPOV_WE
- PH_SC4_PA6_NULL_WE
- PH_SC4_PA7_DATA_FIFO_EOP_RD
- PH_SC4_PA7_DATA_FIFO_RD
- PH_SC4_PA7_DATA_FIFO_WE
- PH_SC4_PA7_DEALLOC_4_0_RD
- PH_SC4_PA7_EOPG_WE
- PH_SC4_PA7_EOP_WE
- PH_SC4_PA7_EVENT_WE
- PH_SC4_PA7_FIFO_EMPTY
- PH_SC4_PA7_FIFO_FULL
- PH_SC4_PA7_FPOV_WE
- PH_SC4_PA7_LPOV_WE
- PH_SC4_PA7_NULL_WE
- PH_SC4_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC4_SEND
- PH_SC4_SRPS_WINDOW_VALID
- PH_SC5_ARB_BUSY
- PH_SC5_ARB_EOP_POP_SYNC_POP
- PH_SC5_ARB_EVENT_SYNC_POP
- PH_SC5_ARB_PA_BUSY_SOP
- PH_SC5_ARB_STALLED_FROM_BELOW
- PH_SC5_ARB_STARVED_FROM_ABOVE
- PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC5_BUSY_CNT_NOT_ZERO
- PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC5_CREDIT_AT_MAX
- PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC5_EOP_SYNC_WINDOW
- PH_SC5_GFX_PIPE0_TO_1_TRANSITION
- PH_SC5_GFX_PIPE1_TO_0_TRANSITION
- PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC5_PA0_DATA_FIFO_EOP_RD
- PH_SC5_PA0_DATA_FIFO_RD
- PH_SC5_PA0_DATA_FIFO_WE
- PH_SC5_PA0_DEALLOC_4_0_RD
- PH_SC5_PA0_EOPG_WE
- PH_SC5_PA0_EOP_WE
- PH_SC5_PA0_EVENT_WE
- PH_SC5_PA0_FIFO_EMPTY
- PH_SC5_PA0_FIFO_FULL
- PH_SC5_PA0_FPOV_WE
- PH_SC5_PA0_LPOV_WE
- PH_SC5_PA0_NULL_WE
- PH_SC5_PA1_DATA_FIFO_EOP_RD
- PH_SC5_PA1_DATA_FIFO_RD
- PH_SC5_PA1_DATA_FIFO_WE
- PH_SC5_PA1_DEALLOC_4_0_RD
- PH_SC5_PA1_EOPG_WE
- PH_SC5_PA1_EOP_WE
- PH_SC5_PA1_EVENT_WE
- PH_SC5_PA1_FIFO_EMPTY
- PH_SC5_PA1_FIFO_FULL
- PH_SC5_PA1_FPOV_WE
- PH_SC5_PA1_LPOV_WE
- PH_SC5_PA1_NULL_WE
- PH_SC5_PA2_DATA_FIFO_EOP_RD
- PH_SC5_PA2_DATA_FIFO_RD
- PH_SC5_PA2_DATA_FIFO_WE
- PH_SC5_PA2_DEALLOC_4_0_RD
- PH_SC5_PA2_EOPG_WE
- PH_SC5_PA2_EOP_WE
- PH_SC5_PA2_EVENT_WE
- PH_SC5_PA2_FIFO_EMPTY
- PH_SC5_PA2_FIFO_FULL
- PH_SC5_PA2_FPOV_WE
- PH_SC5_PA2_LPOV_WE
- PH_SC5_PA2_NULL_WE
- PH_SC5_PA3_DATA_FIFO_EOP_RD
- PH_SC5_PA3_DATA_FIFO_RD
- PH_SC5_PA3_DATA_FIFO_WE
- PH_SC5_PA3_DEALLOC_4_0_RD
- PH_SC5_PA3_EOPG_WE
- PH_SC5_PA3_EOP_WE
- PH_SC5_PA3_EVENT_WE
- PH_SC5_PA3_FIFO_EMPTY
- PH_SC5_PA3_FIFO_FULL
- PH_SC5_PA3_FPOV_WE
- PH_SC5_PA3_LPOV_WE
- PH_SC5_PA3_NULL_WE
- PH_SC5_PA4_DATA_FIFO_EOP_RD
- PH_SC5_PA4_DATA_FIFO_RD
- PH_SC5_PA4_DATA_FIFO_WE
- PH_SC5_PA4_DEALLOC_4_0_RD
- PH_SC5_PA4_EOPG_WE
- PH_SC5_PA4_EOP_WE
- PH_SC5_PA4_EVENT_WE
- PH_SC5_PA4_FIFO_EMPTY
- PH_SC5_PA4_FIFO_FULL
- PH_SC5_PA4_FPOV_WE
- PH_SC5_PA4_LPOV_WE
- PH_SC5_PA4_NULL_WE
- PH_SC5_PA5_DATA_FIFO_EOP_RD
- PH_SC5_PA5_DATA_FIFO_RD
- PH_SC5_PA5_DATA_FIFO_WE
- PH_SC5_PA5_DEALLOC_4_0_RD
- PH_SC5_PA5_EOPG_WE
- PH_SC5_PA5_EOP_WE
- PH_SC5_PA5_EVENT_WE
- PH_SC5_PA5_FIFO_EMPTY
- PH_SC5_PA5_FIFO_FULL
- PH_SC5_PA5_FPOV_WE
- PH_SC5_PA5_LPOV_WE
- PH_SC5_PA5_NULL_WE
- PH_SC5_PA6_DATA_FIFO_EOP_RD
- PH_SC5_PA6_DATA_FIFO_RD
- PH_SC5_PA6_DATA_FIFO_WE
- PH_SC5_PA6_DEALLOC_4_0_RD
- PH_SC5_PA6_EOPG_WE
- PH_SC5_PA6_EOP_WE
- PH_SC5_PA6_EVENT_WE
- PH_SC5_PA6_FIFO_EMPTY
- PH_SC5_PA6_FIFO_FULL
- PH_SC5_PA6_FPOV_WE
- PH_SC5_PA6_LPOV_WE
- PH_SC5_PA6_NULL_WE
- PH_SC5_PA7_DATA_FIFO_EOP_RD
- PH_SC5_PA7_DATA_FIFO_RD
- PH_SC5_PA7_DATA_FIFO_WE
- PH_SC5_PA7_DEALLOC_4_0_RD
- PH_SC5_PA7_EOPG_WE
- PH_SC5_PA7_EOP_WE
- PH_SC5_PA7_EVENT_WE
- PH_SC5_PA7_FIFO_EMPTY
- PH_SC5_PA7_FIFO_FULL
- PH_SC5_PA7_FPOV_WE
- PH_SC5_PA7_LPOV_WE
- PH_SC5_PA7_NULL_WE
- PH_SC5_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC5_SEND
- PH_SC5_SRPS_WINDOW_VALID
- PH_SC6_ARB_BUSY
- PH_SC6_ARB_EOP_POP_SYNC_POP
- PH_SC6_ARB_EVENT_SYNC_POP
- PH_SC6_ARB_PA_BUSY_SOP
- PH_SC6_ARB_STALLED_FROM_BELOW
- PH_SC6_ARB_STARVED_FROM_ABOVE
- PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC6_BUSY_CNT_NOT_ZERO
- PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC6_CREDIT_AT_MAX
- PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC6_EOP_SYNC_WINDOW
- PH_SC6_GFX_PIPE0_TO_1_TRANSITION
- PH_SC6_GFX_PIPE1_TO_0_TRANSITION
- PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC6_PA0_DATA_FIFO_EOP_RD
- PH_SC6_PA0_DATA_FIFO_RD
- PH_SC6_PA0_DATA_FIFO_WE
- PH_SC6_PA0_DEALLOC_4_0_RD
- PH_SC6_PA0_EOPG_WE
- PH_SC6_PA0_EOP_WE
- PH_SC6_PA0_EVENT_WE
- PH_SC6_PA0_FIFO_EMPTY
- PH_SC6_PA0_FIFO_FULL
- PH_SC6_PA0_FPOV_WE
- PH_SC6_PA0_LPOV_WE
- PH_SC6_PA0_NULL_WE
- PH_SC6_PA1_DATA_FIFO_EOP_RD
- PH_SC6_PA1_DATA_FIFO_RD
- PH_SC6_PA1_DATA_FIFO_WE
- PH_SC6_PA1_DEALLOC_4_0_RD
- PH_SC6_PA1_EOPG_WE
- PH_SC6_PA1_EOP_WE
- PH_SC6_PA1_EVENT_WE
- PH_SC6_PA1_FIFO_EMPTY
- PH_SC6_PA1_FIFO_FULL
- PH_SC6_PA1_FPOV_WE
- PH_SC6_PA1_LPOV_WE
- PH_SC6_PA1_NULL_WE
- PH_SC6_PA2_DATA_FIFO_EOP_RD
- PH_SC6_PA2_DATA_FIFO_RD
- PH_SC6_PA2_DATA_FIFO_WE
- PH_SC6_PA2_DEALLOC_4_0_RD
- PH_SC6_PA2_EOPG_WE
- PH_SC6_PA2_EOP_WE
- PH_SC6_PA2_EVENT_WE
- PH_SC6_PA2_FIFO_EMPTY
- PH_SC6_PA2_FIFO_FULL
- PH_SC6_PA2_FPOV_WE
- PH_SC6_PA2_LPOV_WE
- PH_SC6_PA2_NULL_WE
- PH_SC6_PA3_DATA_FIFO_EOP_RD
- PH_SC6_PA3_DATA_FIFO_RD
- PH_SC6_PA3_DATA_FIFO_WE
- PH_SC6_PA3_DEALLOC_4_0_RD
- PH_SC6_PA3_EOPG_WE
- PH_SC6_PA3_EOP_WE
- PH_SC6_PA3_EVENT_WE
- PH_SC6_PA3_FIFO_EMPTY
- PH_SC6_PA3_FIFO_FULL
- PH_SC6_PA3_FPOV_WE
- PH_SC6_PA3_LPOV_WE
- PH_SC6_PA3_NULL_WE
- PH_SC6_PA4_DATA_FIFO_EOP_RD
- PH_SC6_PA4_DATA_FIFO_RD
- PH_SC6_PA4_DATA_FIFO_WE
- PH_SC6_PA4_DEALLOC_4_0_RD
- PH_SC6_PA4_EOPG_WE
- PH_SC6_PA4_EOP_WE
- PH_SC6_PA4_EVENT_WE
- PH_SC6_PA4_FIFO_EMPTY
- PH_SC6_PA4_FIFO_FULL
- PH_SC6_PA4_FPOV_WE
- PH_SC6_PA4_LPOV_WE
- PH_SC6_PA4_NULL_WE
- PH_SC6_PA5_DATA_FIFO_EOP_RD
- PH_SC6_PA5_DATA_FIFO_RD
- PH_SC6_PA5_DATA_FIFO_WE
- PH_SC6_PA5_DEALLOC_4_0_RD
- PH_SC6_PA5_EOPG_WE
- PH_SC6_PA5_EOP_WE
- PH_SC6_PA5_EVENT_WE
- PH_SC6_PA5_FIFO_EMPTY
- PH_SC6_PA5_FIFO_FULL
- PH_SC6_PA5_FPOV_WE
- PH_SC6_PA5_LPOV_WE
- PH_SC6_PA5_NULL_WE
- PH_SC6_PA6_DATA_FIFO_EOP_RD
- PH_SC6_PA6_DATA_FIFO_RD
- PH_SC6_PA6_DATA_FIFO_WE
- PH_SC6_PA6_DEALLOC_4_0_RD
- PH_SC6_PA6_EOPG_WE
- PH_SC6_PA6_EOP_WE
- PH_SC6_PA6_EVENT_WE
- PH_SC6_PA6_FIFO_EMPTY
- PH_SC6_PA6_FIFO_FULL
- PH_SC6_PA6_FPOV_WE
- PH_SC6_PA6_LPOV_WE
- PH_SC6_PA6_NULL_WE
- PH_SC6_PA7_DATA_FIFO_EOP_RD
- PH_SC6_PA7_DATA_FIFO_RD
- PH_SC6_PA7_DATA_FIFO_WE
- PH_SC6_PA7_DEALLOC_4_0_RD
- PH_SC6_PA7_EOPG_WE
- PH_SC6_PA7_EOP_WE
- PH_SC6_PA7_EVENT_WE
- PH_SC6_PA7_FIFO_EMPTY
- PH_SC6_PA7_FIFO_FULL
- PH_SC6_PA7_FPOV_WE
- PH_SC6_PA7_LPOV_WE
- PH_SC6_PA7_NULL_WE
- PH_SC6_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC6_SEND
- PH_SC6_SRPS_WINDOW_VALID
- PH_SC7_ARB_BUSY
- PH_SC7_ARB_EOP_POP_SYNC_POP
- PH_SC7_ARB_EVENT_SYNC_POP
- PH_SC7_ARB_PA_BUSY_SOP
- PH_SC7_ARB_STALLED_FROM_BELOW
- PH_SC7_ARB_STARVED_FROM_ABOVE
- PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL
- PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY
- PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES
- PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM
- PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES
- PH_SC7_BUSY_CNT_NOT_ZERO
- PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM
- PH_SC7_CREDIT_AT_MAX
- PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND
- PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND
- PH_SC7_EOP_SYNC_WINDOW
- PH_SC7_GFX_PIPE0_TO_1_TRANSITION
- PH_SC7_GFX_PIPE1_TO_0_TRANSITION
- PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION
- PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION
- PH_SC7_PA0_DATA_FIFO_EOP_RD
- PH_SC7_PA0_DATA_FIFO_RD
- PH_SC7_PA0_DATA_FIFO_WE
- PH_SC7_PA0_DEALLOC_4_0_RD
- PH_SC7_PA0_EOPG_WE
- PH_SC7_PA0_EOP_WE
- PH_SC7_PA0_EVENT_WE
- PH_SC7_PA0_FIFO_EMPTY
- PH_SC7_PA0_FIFO_FULL
- PH_SC7_PA0_FPOV_WE
- PH_SC7_PA0_LPOV_WE
- PH_SC7_PA0_NULL_WE
- PH_SC7_PA1_DATA_FIFO_EOP_RD
- PH_SC7_PA1_DATA_FIFO_RD
- PH_SC7_PA1_DATA_FIFO_WE
- PH_SC7_PA1_DEALLOC_4_0_RD
- PH_SC7_PA1_EOPG_WE
- PH_SC7_PA1_EOP_WE
- PH_SC7_PA1_EVENT_WE
- PH_SC7_PA1_FIFO_EMPTY
- PH_SC7_PA1_FIFO_FULL
- PH_SC7_PA1_FPOV_WE
- PH_SC7_PA1_LPOV_WE
- PH_SC7_PA1_NULL_WE
- PH_SC7_PA2_DATA_FIFO_EOP_RD
- PH_SC7_PA2_DATA_FIFO_RD
- PH_SC7_PA2_DATA_FIFO_WE
- PH_SC7_PA2_DEALLOC_4_0_RD
- PH_SC7_PA2_EOPG_WE
- PH_SC7_PA2_EOP_WE
- PH_SC7_PA2_EVENT_WE
- PH_SC7_PA2_FIFO_EMPTY
- PH_SC7_PA2_FIFO_FULL
- PH_SC7_PA2_FPOV_WE
- PH_SC7_PA2_LPOV_WE
- PH_SC7_PA2_NULL_WE
- PH_SC7_PA3_DATA_FIFO_EOP_RD
- PH_SC7_PA3_DATA_FIFO_RD
- PH_SC7_PA3_DATA_FIFO_WE
- PH_SC7_PA3_DEALLOC_4_0_RD
- PH_SC7_PA3_EOPG_WE
- PH_SC7_PA3_EOP_WE
- PH_SC7_PA3_EVENT_WE
- PH_SC7_PA3_FIFO_EMPTY
- PH_SC7_PA3_FIFO_FULL
- PH_SC7_PA3_FPOV_WE
- PH_SC7_PA3_LPOV_WE
- PH_SC7_PA3_NULL_WE
- PH_SC7_PA4_DATA_FIFO_EOP_RD
- PH_SC7_PA4_DATA_FIFO_RD
- PH_SC7_PA4_DATA_FIFO_WE
- PH_SC7_PA4_DEALLOC_4_0_RD
- PH_SC7_PA4_EOPG_WE
- PH_SC7_PA4_EOP_WE
- PH_SC7_PA4_EVENT_WE
- PH_SC7_PA4_FIFO_EMPTY
- PH_SC7_PA4_FIFO_FULL
- PH_SC7_PA4_FPOV_WE
- PH_SC7_PA4_LPOV_WE
- PH_SC7_PA4_NULL_WE
- PH_SC7_PA5_DATA_FIFO_EOP_RD
- PH_SC7_PA5_DATA_FIFO_RD
- PH_SC7_PA5_DATA_FIFO_WE
- PH_SC7_PA5_DEALLOC_4_0_RD
- PH_SC7_PA5_EOPG_WE
- PH_SC7_PA5_EOP_WE
- PH_SC7_PA5_EVENT_WE
- PH_SC7_PA5_FIFO_EMPTY
- PH_SC7_PA5_FIFO_FULL
- PH_SC7_PA5_FPOV_WE
- PH_SC7_PA5_LPOV_WE
- PH_SC7_PA5_NULL_WE
- PH_SC7_PA6_DATA_FIFO_EOP_RD
- PH_SC7_PA6_DATA_FIFO_RD
- PH_SC7_PA6_DATA_FIFO_WE
- PH_SC7_PA6_DEALLOC_4_0_RD
- PH_SC7_PA6_EOPG_WE
- PH_SC7_PA6_EOP_WE
- PH_SC7_PA6_EVENT_WE
- PH_SC7_PA6_FIFO_EMPTY
- PH_SC7_PA6_FIFO_FULL
- PH_SC7_PA6_FPOV_WE
- PH_SC7_PA6_LPOV_WE
- PH_SC7_PA6_NULL_WE
- PH_SC7_PA7_DATA_FIFO_EOP_RD
- PH_SC7_PA7_DATA_FIFO_RD
- PH_SC7_PA7_DATA_FIFO_WE
- PH_SC7_PA7_DEALLOC_4_0_RD
- PH_SC7_PA7_EOPG_WE
- PH_SC7_PA7_EOP_WE
- PH_SC7_PA7_EVENT_WE
- PH_SC7_PA7_FIFO_EMPTY
- PH_SC7_PA7_FIFO_FULL
- PH_SC7_PA7_FPOV_WE
- PH_SC7_PA7_LPOV_WE
- PH_SC7_PA7_NULL_WE
- PH_SC7_PS_ENG_MULTICYCLE_BUBBLE
- PH_SC7_SEND
- PH_SC7_SRPS_WINDOW_VALID
- PH_SELECTED
- PH_SELSTART
- PH_SIZE
- PH_STATUS
- PH_TYPE
- PH_UNDETERMINED
- PI
- PI1_CTRL_AFD_N
- PI1_CTRL_DIR
- PI1_CTRL_INIT_N
- PI1_CTRL_IRQ_ENA
- PI1_CTRL_SEL
- PI1_CTRL_SLIN_N
- PI1_CTRL_STROBE_N
- PI1_DMACTRL_ABORT
- PI1_DMACTRL_BLKMODE
- PI1_DMACTRL_FIFO_CLEAR
- PI1_DMACTRL_FIFO_EMPTY
- PI1_DMACTRL_HPMODE
- PI1_DMACTRL_READ
- PI1_DMACTRL_RICOHMODE
- PI1_DMACTRL_RUN
- PI1_DMACTRL_SGIMODE
- PI1_DMACTRL_STDMODE
- PI1_INTMASK_ACK
- PI1_INTMASK_ERR
- PI1_INTMASK_FIFO_EMPTY
- PI1_INTMASK_NOINK
- PI1_INTMASK_ONLINE
- PI1_INTMASK_PE
- PI1_INTSTAT_ACK
- PI1_INTSTAT_ERR
- PI1_INTSTAT_FEMPTY
- PI1_INTSTAT_NOINK
- PI1_INTSTAT_ONLINE
- PI1_INTSTAT_PE
- PI1_STAT_ACK
- PI1_STAT_BUSY
- PI1_STAT_DEVID
- PI1_STAT_ERROR
- PI1_STAT_NOINK
- PI1_STAT_ONLINE
- PI1_STAT_PE
- PI1_TIME1
- PI1_TIME2
- PI1_TIME3
- PI1_TIME4
- PI2C_PORT
- PI3USB30532_CONF
- PI3USB30532_CONF_4LANE_DP
- PI3USB30532_CONF_OPEN
- PI3USB30532_CONF_SWAP
- PI3USB30532_CONF_USB3
- PI3USB30532_CONF_USB3_AND_2LANE_DP
- PI433_H
- PI433_IOC_MAGIC
- PI433_IOC_RD_RX_CFG
- PI433_IOC_RD_TX_CFG
- PI433_IOC_WR_RX_CFG
- PI433_IOC_WR_TX_CFG
- PI433_RX_CFG_IOCTL_NR
- PI433_TX_CFG_IOCTL_NR
- PI7C9X110
- PIA
- PIABASE
- PIAR
- PIA_C1_ENABLE_IRQ
- PIA_C1_LOW_TO_HIGH
- PIA_CMDBUF
- PIA_DDR
- PIA_IRQ1
- PIA_IRQ2
- PIA_REG_PADWIDTH
- PIBC0
- PIBS_MAC0
- PIBS_MAC1
- PIC
- PIC16C54_MISC_MTS_BOTH
- PIC16C54_MISC_MTS_MAIN
- PIC16C54_MISC_MTS_SAP
- PIC16C54_MISC_RESET_REMOTE_CTL
- PIC16C54_MISC_SND_MUTE
- PIC16C54_MISC_SND_NOTMUTE
- PIC16C54_MISC_SWITCH_LINE
- PIC16C54_MISC_SWITCH_TUNER
- PIC16C54_REG_KEY_CODE
- PIC16C54_REG_MISC
- PIC32F_DMA_PREP
- PIC32MZDA_COMMON_H
- PIC32_ALRMDATE
- PIC32_ALRMDAY
- PIC32_ALRMHOUR
- PIC32_ALRMMIN
- PIC32_ALRMMON
- PIC32_ALRMSEC
- PIC32_ALRMTIME
- PIC32_ALRMYEAR
- PIC32_BASE_CONFIG
- PIC32_BASE_DEVCFG2
- PIC32_BASE_OSC
- PIC32_BASE_PORT
- PIC32_BASE_PPS
- PIC32_BASE_RESET
- PIC32_BASE_UART
- PIC32_BPW_16
- PIC32_BPW_32
- PIC32_BPW_8
- PIC32_CFGCON
- PIC32_CFGCON2
- PIC32_CFGEBIA
- PIC32_CFGEBIC
- PIC32_CLR
- PIC32_CNCON_EDGE
- PIC32_CNCON_ON
- PIC32_DEVID
- PIC32_DEV_NAME
- PIC32_DMA_LEN_MIN
- PIC32_INT_PRI
- PIC32_INV
- PIC32_MAX_UARTS
- PIC32_PINCTRL_FUNCTION
- PIC32_PINCTRL_GROUP
- PIC32_POSC_FREQ
- PIC32_RCON
- PIC32_RSWRST
- PIC32_RTCALRM
- PIC32_RTCALRM_ALARMSYNC
- PIC32_RTCALRM_ALRMEN
- PIC32_RTCALRM_AMASK
- PIC32_RTCALRM_ARPT
- PIC32_RTCALRM_CHIME
- PIC32_RTCALRM_PIV
- PIC32_RTCCON
- PIC32_RTCCON_HALFSEC
- PIC32_RTCCON_ON
- PIC32_RTCCON_RTCCLKON
- PIC32_RTCCON_RTCCLKSEL
- PIC32_RTCCON_RTCOE
- PIC32_RTCCON_RTCSYNC
- PIC32_RTCCON_RTCWREN
- PIC32_RTCCON_SIDL
- PIC32_RTCDAY
- PIC32_RTCHOUR
- PIC32_RTCMIN
- PIC32_RTCMON
- PIC32_RTCSEC
- PIC32_RTCYEAR
- PIC32_SCONSOLE
- PIC32_SDEV_NAME
- PIC32_SET
- PIC32_SYSKEY
- PIC32_UART_BRG
- PIC32_UART_DFLT_BRATE
- PIC32_UART_MODE
- PIC32_UART_MODE_ABAUD
- PIC32_UART_MODE_BRGH
- PIC32_UART_MODE_FRZ
- PIC32_UART_MODE_IREN
- PIC32_UART_MODE_LPBK
- PIC32_UART_MODE_ON
- PIC32_UART_MODE_PDSEL0
- PIC32_UART_MODE_PDSEL1
- PIC32_UART_MODE_RESV1
- PIC32_UART_MODE_RTSMD
- PIC32_UART_MODE_RXINV
- PIC32_UART_MODE_SIDL
- PIC32_UART_MODE_STSEL
- PIC32_UART_MODE_UEN0
- PIC32_UART_MODE_UEN1
- PIC32_UART_MODE_WAKE
- PIC32_UART_RX
- PIC32_UART_RX_FIFO_DEPTH
- PIC32_UART_STA
- PIC32_UART_STA_ADDEN
- PIC32_UART_STA_FERR
- PIC32_UART_STA_OERR
- PIC32_UART_STA_PERR
- PIC32_UART_STA_RIDLE
- PIC32_UART_STA_TRMT
- PIC32_UART_STA_URXDA
- PIC32_UART_STA_URXEN
- PIC32_UART_STA_URXISEL0
- PIC32_UART_STA_URXISEL1
- PIC32_UART_STA_UTXBF
- PIC32_UART_STA_UTXBRK
- PIC32_UART_STA_UTXEN
- PIC32_UART_STA_UTXINV
- PIC32_UART_STA_UTXISEL0
- PIC32_UART_STA_UTXISEL1
- PIC32_UART_TX
- PIC32_UART_TX_FIFO_DEPTH
- PICASSO_15D8_REV_E3
- PICASSO_15D8_REV_E4
- PICASSO_A0
- PICA_ASIC_REVISION
- PICA_DRAM_CONFIG
- PICA_LED
- PICINFO_PROG
- PICINFO_TOP_FIRST
- PICK_RATE
- PICOLCDFB_HEIGHT
- PICOLCDFB_NAME
- PICOLCDFB_SIZE
- PICOLCDFB_UPDATE_RATE_DEFAULT
- PICOLCDFB_UPDATE_RATE_LIMIT
- PICOLCDFB_WIDTH
- PICOLCD_BOOTLOADER
- PICOLCD_CIR_SHUN
- PICOLCD_FAILED
- PICOLCD_KEYS
- PICOLCD_NAME
- PICOS2KHZ
- PICOXCELL_PERIPH_BASE
- PICOXCELL_PERIPH_LENGTH
- PICR
- PICR_FEIE
- PICR_FSRIE
- PICTRL_ADRS
- PICTRL_COM_SIGNAL_OFF
- PICTRL_DAC_SIGNAL_OFF
- PICTRL_INIOFF
- PICTRL_INIT_STATE
- PICTRL_POWER_DOWN
- PICTURE_CODING_EXTENSION
- PICTURE_CODING_TYPE_B
- PICTURE_CODING_TYPE_I
- PICTURE_CODING_TYPE_P
- PICTURE_DISPLAY_EXTENSION
- PICTURE_PARAMETER_SET
- PICTURE_SCALING_BOTH
- PICTURE_SCALING_HORIZONTAL
- PICTURE_SCALING_UNIFORM
- PICTURE_SCALING_VERTICAL
- PICT_BOTTOM_FIELD
- PICT_FRAME
- PICT_TOP_FIELD
- PIC_2XX_XHCI_0_IRQ
- PIC_2XX_XHCI_1_IRQ
- PIC_2XX_XHCI_2_IRQ
- PIC_9XX_IRT
- PIC_9XX_IRT0
- PIC_9XX_IRT_PCIE_LINK_0_INDEX
- PIC_9XX_IRT_PCIE_LINK_INDEX
- PIC_9XX_NUM_IRTS
- PIC_9XX_PENDING_0
- PIC_9XX_PENDING_1
- PIC_9XX_PENDING_2
- PIC_9XX_PENDING_3
- PIC_9XX_XHCI_0_IRQ
- PIC_9XX_XHCI_1_IRQ
- PIC_9XX_XHCI_2_IRQ
- PIC_AUX_DIV_SHIFT
- PIC_BRIDGE_AERR_IRQ
- PIC_BRIDGE_AERR_NMI_IRQ
- PIC_BRIDGE_BERR_IRQ
- PIC_BRIDGE_ERR_IRQ
- PIC_BRIDGE_TB_XLR_IRQ
- PIC_BRIDGE_TB_XLS_IRQ
- PIC_BYTESWAP
- PIC_CASCADE_IR
- PIC_CAUSE
- PIC_CDE_IRQ
- PIC_CLK_HZ
- PIC_CLOCK_IRQ
- PIC_CLOCK_TIMER
- PIC_CMD
- PIC_CNTL_RX_ALARM_MAP_1
- PIC_CNTL_SHARED_SPLITS
- PIC_CTRL
- PIC_CTRL_ICI
- PIC_CTRL_ITE
- PIC_CTRL_ITV
- PIC_CTRL_STE
- PIC_CTRL_WTE
- PIC_CTRL_WWN0
- PIC_CTRL_WWN1
- PIC_CTRL_WWR0
- PIC_CTRL_WWR1
- PIC_EHCI_0_IRQ
- PIC_EHCI_1_IRQ
- PIC_ENABLES
- PIC_FLSH_INT_REG_CYCLE_FSM_ERR
- PIC_FLSH_INT_REG_ERR
- PIC_GLOBAL_SCHEDULING
- PIC_GMAC_0_IRQ
- PIC_GMAC_1_IRQ
- PIC_GMAC_2_IRQ
- PIC_GMAC_3_IRQ
- PIC_GMAC_4_IRQ
- PIC_GMAC_5_IRQ
- PIC_GMAC_6_IRQ
- PIC_GMAC_7_IRQ
- PIC_GPIO_B_IRQ
- PIC_GPIO_IRQ
- PIC_HEAD_INFO
- PIC_HI
- PIC_HYPER_FATAL_IRQ
- PIC_HYPER_IRQ
- PIC_I2C_0_IRQ
- PIC_I2C_1_IRQ
- PIC_I2C_2_IRQ
- PIC_I2C_3_IRQ
- PIC_ICI0_INTR_TIMEOUT
- PIC_ICI1_INTR_TIMEOUT
- PIC_ICI2_INTR_TIMEOUT
- PIC_ICI_STATUS
- PIC_ICW4_AEOI
- PIC_IMR
- PIC_INTR_TIMEOUT
- PIC_INTR_TO_IRQ
- PIC_INT_ACK
- PIC_INT_FLSH
- PIC_INT_GPIO
- PIC_INT_IIC
- PIC_INT_MDIO
- PIC_INT_PENDING0
- PIC_INT_PENDING1
- PIC_INT_PENDING2
- PIC_INT_RX
- PIC_INT_TX
- PIC_IPI
- PIC_IPICTRL_DTE
- PIC_IPICTRL_IDB
- PIC_IPICTRL_NMI
- PIC_IPICTRL_RIV
- PIC_IPI_CTL
- PIC_IRQM_LPC
- PIC_IRQM_PRIM
- PIC_IRQS
- PIC_IRQ_BASE
- PIC_IRQ_IS_EDGE_TRIGGERED
- PIC_IRQ_IS_IRT
- PIC_IRQ_TO_INTR
- PIC_IRT
- PIC_IRT0
- PIC_IRT_0
- PIC_IRT_0_BASE
- PIC_IRT_1
- PIC_IRT_1_BASE
- PIC_IRT_BRIDGE_AERR_INDEX
- PIC_IRT_BRIDGE_AERR_NMI_INDEX
- PIC_IRT_BRIDGE_BERR_INDEX
- PIC_IRT_BRIDGE_ERR_INDEX
- PIC_IRT_BRIDGE_TB_XLR_INDEX
- PIC_IRT_BRIDGE_TB_XLS_INDEX
- PIC_IRT_CDE_INDEX
- PIC_IRT_CLOCK_INDEX
- PIC_IRT_DB
- PIC_IRT_DT
- PIC_IRT_DTE
- PIC_IRT_ENABLE
- PIC_IRT_FIRST_IRQ
- PIC_IRT_GMAC0_INDEX
- PIC_IRT_GMAC1_INDEX
- PIC_IRT_GMAC2_INDEX
- PIC_IRT_GMAC3_INDEX
- PIC_IRT_GMAC4_INDEX
- PIC_IRT_GMAC5_INDEX
- PIC_IRT_GMAC6_INDEX
- PIC_IRT_GMAC7_INDEX
- PIC_IRT_GPIO_B_INDEX
- PIC_IRT_GPIO_INDEX
- PIC_IRT_HYPER_FATAL_INDEX
- PIC_IRT_HYPER_INDEX
- PIC_IRT_I2C_0_INDEX
- PIC_IRT_I2C_1_INDEX
- PIC_IRT_LAST_IRQ
- PIC_IRT_MSG_0_INDEX
- PIC_IRT_MSG_1_INDEX
- PIC_IRT_MSG_Q0_INDEX
- PIC_IRT_MSG_Q_INDEX
- PIC_IRT_NMI
- PIC_IRT_PCIE_FATAL_INDEX
- PIC_IRT_PCIE_INT_INDEX
- PIC_IRT_PCIE_LINK0_INDEX
- PIC_IRT_PCIE_LINK1_INDEX
- PIC_IRT_PCIE_LINK2_INDEX
- PIC_IRT_PCIE_LINK3_INDEX
- PIC_IRT_PCIE_LINK_0_INDEX
- PIC_IRT_PCIE_LINK_1_INDEX
- PIC_IRT_PCIE_LINK_2_INDEX
- PIC_IRT_PCIE_LINK_3_INDEX
- PIC_IRT_PCIE_LINK_INDEX
- PIC_IRT_PCIE_MSIX_0_INDEX
- PIC_IRT_PCIE_MSIX_INDEX
- PIC_IRT_PCIE_XLSB0_LINK2_INDEX
- PIC_IRT_PCIE_XLSB0_LINK3_INDEX
- PIC_IRT_PCIX_FATAL_INDEX
- PIC_IRT_PCIX_INDEX
- PIC_IRT_PCMCIA_INDEX
- PIC_IRT_RVEC
- PIC_IRT_SCH
- PIC_IRT_SRIO_LINK0_INDEX
- PIC_IRT_SRIO_LINK1_INDEX
- PIC_IRT_SRIO_LINK2_INDEX
- PIC_IRT_SRIO_LINK3_INDEX
- PIC_IRT_TIMER_0_INDEX
- PIC_IRT_TIMER_1_INDEX
- PIC_IRT_TIMER_2_INDEX
- PIC_IRT_TIMER_3_INDEX
- PIC_IRT_TIMER_4_INDEX
- PIC_IRT_TIMER_5_INDEX
- PIC_IRT_TIMER_6_INDEX
- PIC_IRT_TIMER_7_INDEX
- PIC_IRT_TIMER_INDEX
- PIC_IRT_UART_0_INDEX
- PIC_IRT_UART_1_INDEX
- PIC_IRT_USB_INDEX
- PIC_IRT_VALID
- PIC_IRT_WD_0_INDEX
- PIC_IRT_WD_1_INDEX
- PIC_IRT_WD_INDEX
- PIC_IRT_WD_NMI_0_INDEX
- PIC_IRT_WD_NMI_1_INDEX
- PIC_IRT_XGS0_INDEX
- PIC_IRT_XGS1_INDEX
- PIC_ISR
- PIC_ITE0_N0_N1
- PIC_ITE0_N2_N3
- PIC_ITE1_N0_N1
- PIC_ITE1_N2_N3
- PIC_ITE2_N0_N1
- PIC_ITE2_N2_N3
- PIC_ITE3_N0_N1
- PIC_ITE3_N2_N3
- PIC_ITE4_N0_N1
- PIC_ITE4_N2_N3
- PIC_ITE5_N0_N1
- PIC_ITE5_N2_N3
- PIC_ITE6_N0_N1
- PIC_ITE6_N2_N3
- PIC_ITE7_N0_N1
- PIC_ITE7_N2_N3
- PIC_ITE_N0_N1
- PIC_ITE_N2_N3
- PIC_ITE_STATUS
- PIC_LO
- PIC_LOCAL_SCHEDULING
- PIC_LOWER
- PIC_LOWER_INDEX
- PIC_MAIN_DIV_SHIFT
- PIC_MASK
- PIC_MASK_HI
- PIC_MASK_LO
- PIC_MASTER_CMD
- PIC_MASTER_IMR
- PIC_MASTER_ISR
- PIC_MASTER_OCW3
- PIC_MASTER_POLL
- PIC_MAX_IRQS
- PIC_MAX_IRQ_MASK
- PIC_MMC_IRQ
- PIC_NAND_IRQ
- PIC_NONE
- PIC_NO_INDEX
- PIC_NUM_IRTS
- PIC_NUM_MSG_Q_IRTS
- PIC_NUM_PCIE_LINK_IRTS
- PIC_NUM_PCIE_MSIX_IRTS
- PIC_NUM_PINS
- PIC_OCW3
- PIC_OHCI_0_IRQ
- PIC_OHCI_1_IRQ
- PIC_OHCI_2_IRQ
- PIC_OHCI_3_IRQ
- PIC_PCIE_FATAL_IRQ
- PIC_PCIE_INT_IRQ
- PIC_PCIE_LINK0_IRQ
- PIC_PCIE_LINK1_IRQ
- PIC_PCIE_LINK2_IRQ
- PIC_PCIE_LINK3_IRQ
- PIC_PCIE_LINK_LEGACY_IRQ
- PIC_PCIE_LINK_LEGACY_IRQ_BASE
- PIC_PCIE_LINK_MSI_IRQ
- PIC_PCIE_LINK_MSI_IRQ_BASE
- PIC_PCIE_MSIX_IRQ
- PIC_PCIE_MSIX_IRQ_BASE
- PIC_PCIE_XLSB0_LINK2_IRQ
- PIC_PCIE_XLSB0_LINK3_IRQ
- PIC_PCIX_FATAL_IRQ
- PIC_PCIX_IRQ
- PIC_PCMCIA_IRQ
- PIC_POLL
- PIC_ROUTING_ENTRY
- PIC_RX_INT_M
- PIC_SATA_IRQ
- PIC_SLAVE_CMD
- PIC_SLAVE_IMR
- PIC_SNOOP1
- PIC_SNOOP2
- PIC_SNOOP_MODE_0
- PIC_SNOOP_MODE_1
- PIC_SPI_IRQ
- PIC_SRIO_LINK0_IRQ
- PIC_SRIO_LINK1_IRQ
- PIC_SRIO_LINK2_IRQ
- PIC_SRIO_LINK3_IRQ
- PIC_STATUS
- PIC_STS_STATUS
- PIC_TIMER0_COUNT
- PIC_TIMER0_MAXVAL
- PIC_TIMER1_COUNT
- PIC_TIMER1_MAXVAL
- PIC_TIMER2_COUNT
- PIC_TIMER2_MAXVAL
- PIC_TIMER3_COUNT
- PIC_TIMER3_MAXVAL
- PIC_TIMER4_COUNT
- PIC_TIMER4_MAXVAL
- PIC_TIMER5_COUNT
- PIC_TIMER5_MAXVAL
- PIC_TIMER6_COUNT
- PIC_TIMER6_MAXVAL
- PIC_TIMER7_COUNT
- PIC_TIMER7_MAXVAL
- PIC_TIMER_0_IRQ
- PIC_TIMER_1_IRQ
- PIC_TIMER_2_IRQ
- PIC_TIMER_3_IRQ
- PIC_TIMER_4_IRQ
- PIC_TIMER_5_IRQ
- PIC_TIMER_6_IRQ
- PIC_TIMER_7_IRQ
- PIC_TIMER_COUNT
- PIC_TIMER_COUNT_0
- PIC_TIMER_COUNT_0_BASE
- PIC_TIMER_COUNT_1
- PIC_TIMER_COUNT_1_BASE
- PIC_TIMER_MAXVAL
- PIC_TIMER_MAXVAL_0
- PIC_TIMER_MAXVAL_0_BASE
- PIC_TIMER_MAXVAL_1
- PIC_TIMER_MAXVAL_1_BASE
- PIC_TIME_BOT
- PIC_TIME_TOP
- PIC_UART_0_IRQ
- PIC_UART_1_IRQ
- PIC_UPPER
- PIC_UPPER_INDEX
- PIC_USB_IRQ
- PIC_VEC_SPURRIOUS
- PIC_WDOG0_BEAT0
- PIC_WDOG0_BEAT1
- PIC_WDOG0_BEATCMD
- PIC_WDOG0_COUNT
- PIC_WDOG0_ENABLE0
- PIC_WDOG0_ENABLE1
- PIC_WDOG0_MAXVAL
- PIC_WDOG1_BEAT0
- PIC_WDOG1_BEAT1
- PIC_WDOG1_BEATCMD
- PIC_WDOG1_COUNT
- PIC_WDOG1_ENABLE0
- PIC_WDOG1_ENABLE1
- PIC_WDOG1_MAXVAL
- PIC_WDOG_BEAT0
- PIC_WDOG_BEAT1
- PIC_WDOG_BEATCMD
- PIC_WDOG_COUNT
- PIC_WDOG_ENABLE0
- PIC_WDOG_ENABLE1
- PIC_WDOG_MAXVAL
- PIC_WD_IRQ
- PIC_WIS_STATUS
- PIC_WNS_STATUS
- PIC_XGS_0_IRQ
- PIC_XGS_1_IRQ
- PIC_XIRR_STS_HIGH
- PIC_XIRR_STS_LOW
- PIC_YSEL_HIGH
- PIC_YSEL_LOW
- PIC_YSEL_LOW_ACC_SHIFT
- PIC_YSEL_LOW_FLASH_SHIFT
- PIC_YSEL_LOW_USB_SHIFT
- PIC_ZSEL_HIGH
- PIC_ZSEL_LOW
- PID
- PID0
- PID0011_RDESC_ORIG_SIZE
- PID0902_RDESC_ORIG_SIZE
- PID0_AFIL
- PID0_END
- PID0_NOFIL
- PID1
- PID12
- PIDE_FLAG
- PIDFD_ERROR
- PIDFD_FAIL
- PIDFD_MAX_DEFAULT
- PIDFD_PASS
- PIDFD_SKIP
- PIDFD_XFAIL
- PIDFF_FIND_FIELDS
- PIDFF_FIND_SPECIAL_KEYS
- PIDF_BASE
- PIDF_LEAK_COUNTER
- PIDF_LEAK_COUNT_RESET
- PIDF_LEAK_ENABLE
- PIDF_LEAK_STATUS
- PIDF_OFFSET
- PIDNS_ADDING
- PIDS_MAX
- PIDS_MAX_STR
- PIDS_PER_CPU_DEFAULT
- PIDS_PER_CPU_MIN
- PIDTYPE_MAX
- PIDTYPE_PGID
- PIDTYPE_PID
- PIDTYPE_SID
- PIDTYPE_TGID
- PIDVEC_SIZE
- PIDX
- PIDXCTL
- PIDXDATA
- PIDXHI
- PIDXLO
- PIDX_S
- PIDX_T5_G
- PIDX_T5_M
- PIDX_T5_S
- PIDX_T5_V
- PIDX_V
- PID_0038_RDESC_ORIG_SIZE
- PID_1000
- PID_1001
- PID_1002
- PID_400
- PID_401
- PID_5249
- PID_524A
- PID_5250
- PID_525A
- PID_5260
- PID_ATTACK_LEVEL
- PID_ATTACK_TIME
- PID_BANK_SEL_SLICE0_REG
- PID_BANK_SEL_SLICE1_REG
- PID_BITS
- PID_BLOCK_FREE
- PID_BLOCK_LOAD
- PID_BLOCK_LOAD_FULL
- PID_BLOCK_LOAD_SUCCESS
- PID_BUF
- PID_BUF_SIZE
- PID_BURST_S
- PID_CHARGE_LOWER_LIMIT
- PID_CHARGE_MODE
- PID_CHARGE_UPPER_LIMIT
- PID_CODE_IN
- PID_CODE_SETUP
- PID_CONSTANT
- PID_CP_OFFSET
- PID_CREATE_NEW_EFFECT
- PID_DAMPER
- PID_DATA0
- PID_DATA1
- PID_DEAD_BAND
- PID_DEVICE_CONTROL
- PID_DEVICE_GAIN
- PID_DEVICE_GAIN_FIELD
- PID_DEVICE_MANAGED_POOL
- PID_DIRECTION_ENABLE
- PID_DURATION
- PID_EFFECTS_MAX
- PID_EFFECT_BLOCK_INDEX
- PID_EFFECT_OPERATION
- PID_EFFECT_START
- PID_EFFECT_STOP
- PID_ENABLE_ACTUATORS
- PID_ETHERNET
- PID_FADE_LEVEL
- PID_FADE_TIME
- PID_FRICTION
- PID_GAIN
- PID_GDM7240
- PID_GDM7243
- PID_INERTIA
- PID_IP
- PID_IPCP
- PID_IPV6
- PID_IPV6CP
- PID_KEY_LEN
- PID_LCP
- PID_LOOP_COUNT
- PID_LSB_ADDR
- PID_MAGNITUDE
- PID_MAJOR_REV
- PID_MASK
- PID_MASK_HI
- PID_MAX_DEFAULT
- PID_MAX_LIMIT
- PID_MINOR_REV
- PID_MSB_ADDR
- PID_NAK
- PID_NEG_COEFFICIENT
- PID_NEG_SATURATION
- PID_NS_INDEX
- PID_OFFSET
- PID_OV2640
- PID_PARAM_BLOCK_OFFSET
- PID_PERIOD
- PID_PHASE
- PID_POOL
- PID_POS_COEFFICIENT
- PID_POS_SATURATION
- PID_RAMP
- PID_RAMP_END
- PID_RAMP_START
- PID_RAM_POOL_AVAILABLE
- PID_RAM_POOL_SIZE
- PID_RECYCLE
- PID_REQUIRED_REPORTS
- PID_RESET
- PID_SAW_DOWN
- PID_SAW_UP
- PID_SETUP
- PID_SET_CONDITION
- PID_SET_CONSTANT
- PID_SET_EFFECT
- PID_SET_ENVELOPE
- PID_SET_PERIODIC
- PID_SET_RAMP
- PID_SHIFT
- PID_SIMULTANEOUS_MAX
- PID_SINE
- PID_SPRING
- PID_SQUARE
- PID_STALL
- PID_STALL10
- PID_STALL11
- PID_START_DELAY
- PID_TABLE_SIZE
- PID_TRIANGLE
- PID_TRIGGER_BUTTON
- PID_TRIGGER_REPEAT_INT
- PIDn_ENP
- PIDn_PID
- PIECE_RATE
- PIE_SCALE
- PIFS
- PIFS_TIME
- PIF_GUEST_FAULT
- PIF_INT_MASK_BIT
- PIF_PER_TRAP
- PIF_SYSCALL
- PIF_SYSCALL_RESTART
- PIGGYBACK_CTRL_REG
- PIGGYBACK_REGISTER_ACCESSES
- PIHR_BASE
- PIIX4_BLOCK_DATA
- PIIX4_BYTE
- PIIX4_BYTE_DATA
- PIIX4_FUNC0_DLC
- PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN
- PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN
- PIIX4_FUNC0_DLC_USBPR_EN
- PIIX4_FUNC0_GENCFG
- PIIX4_FUNC0_GENCFG_SERIRQ
- PIIX4_FUNC0_PIRQRC
- PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE
- PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK
- PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX
- PIIX4_FUNC0_SERIRQC
- PIIX4_FUNC0_SERIRQC_CONT
- PIIX4_FUNC0_SERIRQC_EN
- PIIX4_FUNC0_TOM
- PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK
- PIIX4_FUNC1_IDETIM_PRIMARY_HI
- PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN
- PIIX4_FUNC1_IDETIM_PRIMARY_LO
- PIIX4_FUNC1_IDETIM_SECONDARY_HI
- PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN
- PIIX4_FUNC1_IDETIM_SECONDARY_LO
- PIIX4_FUNC3IO_PMCNTRL
- PIIX4_FUNC3IO_PMCNTRL_SUS_EN
- PIIX4_FUNC3IO_PMCNTRL_SUS_TYP
- PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF
- PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR
- PIIX4_FUNC3IO_PMSTS
- PIIX4_FUNC3IO_PMSTS_PWRBTN_STS
- PIIX4_FUNC3_PMBA
- PIIX4_FUNC3_PMREGMISC
- PIIX4_FUNC3_PMREGMISC_EN
- PIIX4_MAX_ADAPTERS
- PIIX4_QUICK
- PIIX4_SUSPEND_MAGIC
- PIIX4_WORD_DATA
- PIIXE_IOBASE_RESOURCE
- PIIX_80C_PRI
- PIIX_80C_SEC
- PIIX_AHCI_DEVICE
- PIIX_FLAG_CHECKINTR
- PIIX_FLAG_PIO16
- PIIX_FLAG_SIDPR
- PIIX_HOST_BROKEN_SUSPEND
- PIIX_IOCFG
- PIIX_PATA_FLAGS
- PIIX_SATA_FLAGS
- PIIX_SIDPR_BAR
- PIIX_SIDPR_DATA
- PIIX_SIDPR_IDX
- PIIX_SIDPR_LEN
- PILADBGRDPTR_M
- PILADBGRDPTR_S
- PILADBGRDPTR_V
- PILADBGWRPTR_G
- PILADBGWRPTR_M
- PILADBGWRPTR_S
- PILOT_AUTO
- PILOT_DEV_SET
- PILOT_OFF
- PILOT_ON
- PIL_DEFERRED_PCR_WORK
- PIL_DEVICE_IRQ
- PIL_KGDB_CAPTURE
- PIL_NMI
- PIL_NORMAL_MAX
- PIL_SMP_CALL_FUNC
- PIL_SMP_CALL_FUNC_SNGL
- PIL_SMP_CAPTURE
- PIL_SMP_RECEIVE_SIGNAL
- PIM
- PIM1_1L
- PIM2_1L
- PIM3_1L
- PIMFOR_DEV_ID_MHLI_MIB
- PIMFOR_ETHERTYPE
- PIMFOR_FLAG_APPLIC_ORIGIN
- PIMFOR_FLAG_LITTLE_ENDIAN
- PIMFOR_HEADER_SIZE
- PIMFOR_OP_ERROR
- PIMFOR_OP_GET
- PIMFOR_OP_RESERVED
- PIMFOR_OP_RESPONSE
- PIMFOR_OP_SET
- PIMFOR_OP_TRAP
- PIMFOR_VERSION
- PIM_NULL_REGISTER
- PIM_TYPE_ASSERT
- PIM_TYPE_BOOTSTRAP
- PIM_TYPE_CANDIDATE_RP_ADV
- PIM_TYPE_GRAFT
- PIM_TYPE_GRAFT_ACK
- PIM_TYPE_HELLO
- PIM_TYPE_JOIN_PRUNE
- PIM_TYPE_REGISTER
- PIM_TYPE_REGISTER_STOP
- PIM_V1_REGISTER
- PIM_V1_VERSION
- PIM_VERSION
- PIN0
- PIN0_AUDIO_ENABLED
- PIN0_JACK_DETECTION_ENABLE
- PIN0_UNSOLICITED_RESPONSE_ENABLE
- PIN1
- PIN1_AUDIO_ENABLED
- PIN1_JACK_DETECTION_ENABLE
- PIN1_UNSOLICITED_RESPONSE_ENABLE
- PIN2
- PIN2_AUDIO_ENABLED
- PIN2_JACK_DETECTION_ENABLE
- PIN2_UNSOLICITED_RESPONSE_ENABLE
- PIN3
- PIN3_AUDIO_ENABLED
- PIN3_JACK_DETECTION_ENABLE
- PIN3_UNSOLICITED_RESPONSE_ENABLE
- PINCFG
- PINCFG_PACK
- PINCFG_TYPE_CON_PDN
- PINCFG_TYPE_DAT
- PINCFG_TYPE_DRV
- PINCFG_TYPE_FUNC
- PINCFG_TYPE_MASK
- PINCFG_TYPE_NUM
- PINCFG_TYPE_PUD
- PINCFG_TYPE_PUD_PDN
- PINCFG_UNPACK_TYPE
- PINCFG_UNPACK_VALUE
- PINCFG_VALUE_MASK
- PINCFG_VALUE_SHIFT
- PINCTRL_AB8500
- PINCTRL_AB8505
- PINCTRL_ARMADA_37XX_DEV_PM_OPS
- PINCTRL_ASPEED
- PINCTRL_BIT_MASK
- PINCTRL_DEVINFO_H
- PINCTRL_DIN
- PINCTRL_DOE
- PINCTRL_DOUT
- PINCTRL_FEATURE_1K_PD
- PINCTRL_FEATURE_DEBOUNCE
- PINCTRL_INTEL_H
- PINCTRL_IRQEN
- PINCTRL_IRQLEV
- PINCTRL_IRQPOL
- PINCTRL_IRQSTAT
- PINCTRL_MADERA_H
- PINCTRL_MTK_MT2712_H
- PINCTRL_NMK_DB8500
- PINCTRL_NMK_DB8540
- PINCTRL_NMK_STN8815
- PINCTRL_PIN
- PINCTRL_PIN2IRQ
- PINCTRL_PINCTRL_ABx500_H
- PINCTRL_PINCTRL_DEV
- PINCTRL_PINCTRL_NOMADIK_H
- PINCTRL_PINCTRL_PIC32_H
- PINCTRL_PIN_ANON
- PINCTRL_PIN_GROUP
- PINCTRL_PIN_REG_DI
- PINCTRL_PIN_REG_DIR
- PINCTRL_PIN_REG_DO
- PINCTRL_PIN_REG_DRV
- PINCTRL_PIN_REG_DRV_E0
- PINCTRL_PIN_REG_DRV_E1
- PINCTRL_PIN_REG_DRV_EN
- PINCTRL_PIN_REG_E4
- PINCTRL_PIN_REG_E8
- PINCTRL_PIN_REG_IES
- PINCTRL_PIN_REG_MAX
- PINCTRL_PIN_REG_MODE
- PINCTRL_PIN_REG_PD
- PINCTRL_PIN_REG_PU
- PINCTRL_PIN_REG_PULLEN
- PINCTRL_PIN_REG_PULLSEL
- PINCTRL_PIN_REG_PUPD
- PINCTRL_PIN_REG_R0
- PINCTRL_PIN_REG_R1
- PINCTRL_PIN_REG_RDSEL
- PINCTRL_PIN_REG_SMT
- PINCTRL_PIN_REG_SR
- PINCTRL_PIN_REG_TDSEL
- PINCTRL_PIN_STATE
- PINCTRL_REG_LEN
- PINCTRL_REG_MISC_OFFSET
- PINCTRL_REG_OFFSET
- PINCTRL_STATE_DEFAULT
- PINCTRL_STATE_IDLE
- PINCTRL_STATE_INIT
- PINCTRL_STATE_SLEEP
- PINCTRL_SUN4I_A10
- PINCTRL_SUN5I_A10S
- PINCTRL_SUN5I_A13
- PINCTRL_SUN5I_GR8
- PINCTRL_SUN6I_A31
- PINCTRL_SUN6I_A31S
- PINCTRL_SUN7I_A20
- PINCTRL_SUN8I_R40
- PINCTRL_SUN8I_V3
- PINCTRL_SUN8I_V3S
- PINEVIEW_CURSOR_DFT_WM
- PINEVIEW_CURSOR_FIFO
- PINEVIEW_CURSOR_GUARD_WM
- PINEVIEW_CURSOR_MAX_WM
- PINEVIEW_DFT_HPLLOFF_WM
- PINEVIEW_DFT_WM
- PINEVIEW_DISPLAY_FIFO
- PINEVIEW_FIFO_LINE_SIZE
- PINEVIEW_GUARD_WM
- PINEVIEW_MAX_WM
- PINEVIEW_SELF_REFRESH_EN
- PINFO
- PING
- PINGE
- PINGPONG_0
- PINGPONG_1
- PINGPONG_2
- PINGPONG_3
- PINGPONG_4
- PINGPONG_BUFFER
- PINGPONG_CMD_COMMAND_MASK
- PINGPONG_CMD_PROFILE_SHIFT
- PINGPONG_CMD_SS_SHIFT
- PINGPONG_COMMAND_FLUSH
- PINGPONG_COMMAND_HALT
- PINGPONG_COMMAND_NOOP
- PINGPONG_COMMAND_START_NOW
- PINGPONG_COMMAND_START_TRIGGER
- PINGPONG_MAX
- PINGPONG_S0
- PINGPONG_SDM845_MASK
- PINGPONG_SDM845_SPLIT_MASK
- PINGROUP
- PINGROUP_BIT_N
- PINGROUP_BIT_Y
- PINGROUP_REG
- PINGROUP_REG_A
- PING_AVAIL
- PING_BUFFER_ADDRESS
- PING_CMD
- PING_HTABLE_MASK
- PING_HTABLE_SIZE
- PING_IPV6_ADDR0
- PING_IPV6_ADDR1
- PING_IPV6_LINKLOCAL_ADDR
- PING_IPV6_PROTOCOL_ENABLE
- PING_OPT1_TLV_TYPE
- PING_OPT2_TLV_TYPE
- PING_PERIOD
- PING_PONG
- PING_REQ1_TLV_TYPE
- PING_RESP1_TLV_TYPE
- PING_RESPONSE
- PING_VALID
- PING_WRITE
- PINID
- PINID_TO_BANK
- PINID_TO_PIN
- PINMUX
- PINMUX_810_PRIMARY_SEL0
- PINMUX_810_PRIMARY_SEL1
- PINMUX_810_PULLUP_CTRL0
- PINMUX_810_PULLUP_CTRL1
- PINMUX_810_SECONDARY_SEL0
- PINMUX_810_SECONDARY_SEL1
- PINMUX_810_TERTIARY_SEL0
- PINMUX_810_TERTIARY_SEL1
- PINMUX_820_ALTERNATIVE_SEL
- PINMUX_820_BANK_OFFSET
- PINMUX_820_DEBUG_SEL
- PINMUX_820_PULLUP_CTRL
- PINMUX_820_QUATERNARY_SEL
- PINMUX_820_SECONDARY_SEL
- PINMUX_820_TERTIARY_SEL
- PINMUX_BIAS_REG
- PINMUX_CFG_REG
- PINMUX_CFG_REG_VAR
- PINMUX_DATA
- PINMUX_DATA_BEGIN
- PINMUX_DATA_END
- PINMUX_DATA_GP_ALL
- PINMUX_DATA_REG
- PINMUX_DRIVE_REG
- PINMUX_EMEV_DATA_ALL
- PINMUX_EMEV_GPIO_ALL
- PINMUX_FN_BASE
- PINMUX_FUNCTION_BEGIN
- PINMUX_FUNCTION_END
- PINMUX_GPIO0__FUNC_GPIO0
- PINMUX_GPIO0__FUNC_I2S3_MCK
- PINMUX_GPIO0__FUNC_MRG_SYNC
- PINMUX_GPIO0__FUNC_PCM0_SYNC
- PINMUX_GPIO0__FUNC_SCP_SPI2_CS
- PINMUX_GPIO0__FUNC_SPI2_CSB
- PINMUX_GPIO0__FUNC_SRCLKENAI0
- PINMUX_GPIO0__FUNC_TP_GPIO0_AO
- PINMUX_GPIO100__FUNC_CMMCLK1
- PINMUX_GPIO100__FUNC_CONN_MCU_AICE_TCKC
- PINMUX_GPIO100__FUNC_DBG_MON_B29
- PINMUX_GPIO100__FUNC_GPIO100
- PINMUX_GPIO100__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG
- PINMUX_GPIO100__FUNC_PWM_C
- PINMUX_GPIO101__FUNC_CLKM2
- PINMUX_GPIO101__FUNC_CMVREF1
- PINMUX_GPIO101__FUNC_CONN_MCU_TCK
- PINMUX_GPIO101__FUNC_GPIO101
- PINMUX_GPIO101__FUNC_I2S2_LRCK
- PINMUX_GPIO101__FUNC_IO_JTAG_TCK
- PINMUX_GPIO101__FUNC_SSPM_JTAG_TCK
- PINMUX_GPIO102__FUNC_CLKM1
- PINMUX_GPIO102__FUNC_CONN_MCU_TDI
- PINMUX_GPIO102__FUNC_DBG_MON_B8
- PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO102__FUNC_GPIO102
- PINMUX_GPIO102__FUNC_I2S2_DI
- PINMUX_GPIO102__FUNC_IO_JTAG_TDI
- PINMUX_GPIO102__FUNC_SSPM_JTAG_TDI
- PINMUX_GPIO103__FUNC_GPIO103
- PINMUX_GPIO103__FUNC_SCL2
- PINMUX_GPIO104__FUNC_GPIO104
- PINMUX_GPIO104__FUNC_SDA2
- PINMUX_GPIO105__FUNC_GPIO105
- PINMUX_GPIO105__FUNC_SCL4
- PINMUX_GPIO106__FUNC_GPIO106
- PINMUX_GPIO106__FUNC_SDA4
- PINMUX_GPIO107__FUNC_ANT_SEL0
- PINMUX_GPIO107__FUNC_CLKM0
- PINMUX_GPIO107__FUNC_DBG_MON_B12
- PINMUX_GPIO107__FUNC_DMIC_CLK
- PINMUX_GPIO107__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO107__FUNC_GPIO107
- PINMUX_GPIO107__FUNC_PWM_A
- PINMUX_GPIO107__FUNC_SDA7
- PINMUX_GPIO108__FUNC_ANT_SEL1
- PINMUX_GPIO108__FUNC_CLKM1
- PINMUX_GPIO108__FUNC_CMMCLK2
- PINMUX_GPIO108__FUNC_DAP_MD32_SWD
- PINMUX_GPIO108__FUNC_DBG_MON_B13
- PINMUX_GPIO108__FUNC_GPIO108
- PINMUX_GPIO108__FUNC_PWM_B
- PINMUX_GPIO108__FUNC_SCL8
- PINMUX_GPIO109__FUNC_ANT_SEL2
- PINMUX_GPIO109__FUNC_CLKM2
- PINMUX_GPIO109__FUNC_DAP_MD32_SWCK
- PINMUX_GPIO109__FUNC_DBG_MON_B14
- PINMUX_GPIO109__FUNC_DMIC_DAT
- PINMUX_GPIO109__FUNC_GPIO109
- PINMUX_GPIO109__FUNC_PWM_C
- PINMUX_GPIO109__FUNC_SDA8
- PINMUX_GPIO10__FUNC_ANT_SEL5
- PINMUX_GPIO10__FUNC_CMMCLK3
- PINMUX_GPIO10__FUNC_CONN_MCU_DBGI_N
- PINMUX_GPIO10__FUNC_DBG_MON_B11
- PINMUX_GPIO10__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO10__FUNC_GPIO10
- PINMUX_GPIO10__FUNC_SPI1_B_CLK
- PINMUX_GPIO10__FUNC_TDM_DATA3
- PINMUX_GPIO110__FUNC_ANT_SEL0
- PINMUX_GPIO110__FUNC_GPIO110
- PINMUX_GPIO110__FUNC_KPCOL2
- PINMUX_GPIO110__FUNC_SCL7
- PINMUX_GPIO110__FUNC_SRCLKENAI1
- PINMUX_GPIO110__FUNC_TP_URXD1_AO
- PINMUX_GPIO110__FUNC_URXD1
- PINMUX_GPIO110__FUNC_USB_DRVVBUS
- PINMUX_GPIO111__FUNC_ANT_SEL1
- PINMUX_GPIO111__FUNC_CMMCLK3
- PINMUX_GPIO111__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO111__FUNC_GPIO111
- PINMUX_GPIO111__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG
- PINMUX_GPIO111__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO111__FUNC_SRCLKENAI0
- PINMUX_GPIO112__FUNC_AGPS_SYNC
- PINMUX_GPIO112__FUNC_ANT_SEL2
- PINMUX_GPIO112__FUNC_GPIO112
- PINMUX_GPIO112__FUNC_IDDIG
- PINMUX_GPIO112__FUNC_KPROW2
- PINMUX_GPIO112__FUNC_SDA7
- PINMUX_GPIO112__FUNC_TP_UTXD1_AO
- PINMUX_GPIO112__FUNC_UTXD1
- PINMUX_GPIO113__FUNC_AUXIF_CLK0
- PINMUX_GPIO113__FUNC_CONN_TOP_CLK
- PINMUX_GPIO113__FUNC_GPIO113
- PINMUX_GPIO113__FUNC_SCL6
- PINMUX_GPIO113__FUNC_TP_UCTS1_AO
- PINMUX_GPIO114__FUNC_AUXIF_ST0
- PINMUX_GPIO114__FUNC_CONN_TOP_DATA
- PINMUX_GPIO114__FUNC_GPIO114
- PINMUX_GPIO114__FUNC_SDA6
- PINMUX_GPIO114__FUNC_TP_URTS1_AO
- PINMUX_GPIO115__FUNC_AUXIF_CLK1
- PINMUX_GPIO115__FUNC_CONN_BT_CLK
- PINMUX_GPIO115__FUNC_DAP_MD32_SWD
- PINMUX_GPIO115__FUNC_GPIO115
- PINMUX_GPIO115__FUNC_PTA_TXD
- PINMUX_GPIO115__FUNC_TP_UTXD1_AO
- PINMUX_GPIO115__FUNC_UTXD1
- PINMUX_GPIO116__FUNC_AUXIF_ST1
- PINMUX_GPIO116__FUNC_CONN_BT_DATA
- PINMUX_GPIO116__FUNC_DAP_MD32_SWCK
- PINMUX_GPIO116__FUNC_DBG_MON_A0
- PINMUX_GPIO116__FUNC_GPIO116
- PINMUX_GPIO116__FUNC_IPU_JTAG_TRST
- PINMUX_GPIO116__FUNC_TP_URXD2_AO
- PINMUX_GPIO117__FUNC_CONN_WF_HB0
- PINMUX_GPIO117__FUNC_DBG_MON_A4
- PINMUX_GPIO117__FUNC_GPIO117
- PINMUX_GPIO117__FUNC_IPU_JTAG_TDO
- PINMUX_GPIO117__FUNC_TP_UTXD2_AO
- PINMUX_GPIO118__FUNC_CONN_WF_HB1
- PINMUX_GPIO118__FUNC_DBG_MON_A5
- PINMUX_GPIO118__FUNC_GPIO118
- PINMUX_GPIO118__FUNC_IPU_JTAG_TDI
- PINMUX_GPIO118__FUNC_SSPM_URXD_AO
- PINMUX_GPIO118__FUNC_TP_UCTS2_AO
- PINMUX_GPIO119__FUNC_CONN_WF_HB2
- PINMUX_GPIO119__FUNC_GPIO119
- PINMUX_GPIO119__FUNC_IPU_JTAG_TCK
- PINMUX_GPIO119__FUNC_SSPM_UTXD_AO
- PINMUX_GPIO119__FUNC_TP_URTS2_AO
- PINMUX_GPIO11__FUNC_GPIO11
- PINMUX_GPIO11__FUNC_I2S5_MCK
- PINMUX_GPIO11__FUNC_IDDIG
- PINMUX_GPIO11__FUNC_SCL6
- PINMUX_GPIO11__FUNC_SRCLKENAI1
- PINMUX_GPIO11__FUNC_TP_URXD1_AO
- PINMUX_GPIO11__FUNC_UCTS0
- PINMUX_GPIO11__FUNC_UCTS1
- PINMUX_GPIO120__FUNC_CCU_URXD_AO
- PINMUX_GPIO120__FUNC_CONN_WB_PTA
- PINMUX_GPIO120__FUNC_GPIO120
- PINMUX_GPIO120__FUNC_IPU_JTAG_TMS
- PINMUX_GPIO121__FUNC_CCU_UTXD_AO
- PINMUX_GPIO121__FUNC_CONN_HRST_B
- PINMUX_GPIO121__FUNC_GPIO121
- PINMUX_GPIO121__FUNC_PTA_RXD
- PINMUX_GPIO121__FUNC_TP_URXD1_AO
- PINMUX_GPIO121__FUNC_URXD1
- PINMUX_GPIO122__FUNC_ANT_SEL1
- PINMUX_GPIO122__FUNC_DBG_MON_A12
- PINMUX_GPIO122__FUNC_GPIO122
- PINMUX_GPIO122__FUNC_MSDC0_CMD
- PINMUX_GPIO122__FUNC_SSPM_URXD2_AO
- PINMUX_GPIO123__FUNC_ANT_SEL0
- PINMUX_GPIO123__FUNC_DBG_MON_A13
- PINMUX_GPIO123__FUNC_GPIO123
- PINMUX_GPIO123__FUNC_MSDC0_DAT0
- PINMUX_GPIO124__FUNC_DBG_MON_A14
- PINMUX_GPIO124__FUNC_GPIO124
- PINMUX_GPIO124__FUNC_MSDC0_CLK
- PINMUX_GPIO125__FUNC_DBG_MON_A15
- PINMUX_GPIO125__FUNC_GPIO125
- PINMUX_GPIO125__FUNC_MRG_CLK
- PINMUX_GPIO125__FUNC_MSDC0_DAT2
- PINMUX_GPIO126__FUNC_ANT_SEL5
- PINMUX_GPIO126__FUNC_DBG_MON_A16
- PINMUX_GPIO126__FUNC_GPIO126
- PINMUX_GPIO126__FUNC_MSDC0_DAT4
- PINMUX_GPIO126__FUNC_UFS_MPHY_SCL
- PINMUX_GPIO127__FUNC_ANT_SEL4
- PINMUX_GPIO127__FUNC_DBG_MON_A17
- PINMUX_GPIO127__FUNC_GPIO127
- PINMUX_GPIO127__FUNC_MSDC0_DAT6
- PINMUX_GPIO127__FUNC_UFS_MPHY_SDA
- PINMUX_GPIO128__FUNC_ANT_SEL2
- PINMUX_GPIO128__FUNC_DBG_MON_A18
- PINMUX_GPIO128__FUNC_GPIO128
- PINMUX_GPIO128__FUNC_MSDC0_DAT1
- PINMUX_GPIO128__FUNC_UFS_UNIPRO_SDA
- PINMUX_GPIO129__FUNC_ANT_SEL3
- PINMUX_GPIO129__FUNC_DBG_MON_A23
- PINMUX_GPIO129__FUNC_GPIO129
- PINMUX_GPIO129__FUNC_MSDC0_DAT5
- PINMUX_GPIO129__FUNC_UFS_UNIPRO_SCL
- PINMUX_GPIO12__FUNC_GPIO12
- PINMUX_GPIO12__FUNC_I2S2_DI2
- PINMUX_GPIO12__FUNC_I2S5_BCK
- PINMUX_GPIO12__FUNC_SDA6
- PINMUX_GPIO12__FUNC_TP_UTXD1_AO
- PINMUX_GPIO12__FUNC_URTS0
- PINMUX_GPIO12__FUNC_URTS1
- PINMUX_GPIO12__FUNC_USB_DRVVBUS
- PINMUX_GPIO130__FUNC_DBG_MON_A24
- PINMUX_GPIO130__FUNC_GPIO130
- PINMUX_GPIO130__FUNC_MRG_DO
- PINMUX_GPIO130__FUNC_MSDC0_DAT7
- PINMUX_GPIO131__FUNC_DBG_MON_A25
- PINMUX_GPIO131__FUNC_GPIO131
- PINMUX_GPIO131__FUNC_MRG_SYNC
- PINMUX_GPIO131__FUNC_MSDC0_DSL
- PINMUX_GPIO132__FUNC_DBG_MON_A26
- PINMUX_GPIO132__FUNC_GPIO132
- PINMUX_GPIO132__FUNC_MRG_DI
- PINMUX_GPIO132__FUNC_MSDC0_DAT3
- PINMUX_GPIO133__FUNC_AGPS_SYNC
- PINMUX_GPIO133__FUNC_DBG_MON_A27
- PINMUX_GPIO133__FUNC_GPIO133
- PINMUX_GPIO133__FUNC_MSDC0_RSTB
- PINMUX_GPIO134__FUNC_GPIO134
- PINMUX_GPIO134__FUNC_RTC32K_CK
- PINMUX_GPIO135__FUNC_GPIO135
- PINMUX_GPIO135__FUNC_WATCHDOG
- PINMUX_GPIO136__FUNC_AUD_CLK_MISO
- PINMUX_GPIO136__FUNC_AUD_CLK_MOSI
- PINMUX_GPIO136__FUNC_GPIO136
- PINMUX_GPIO136__FUNC_I2S1_MCK
- PINMUX_GPIO136__FUNC_UFS_UNIPRO_SCL
- PINMUX_GPIO137__FUNC_AUD_SYNC_MISO
- PINMUX_GPIO137__FUNC_AUD_SYNC_MOSI
- PINMUX_GPIO137__FUNC_GPIO137
- PINMUX_GPIO137__FUNC_I2S1_BCK
- PINMUX_GPIO138__FUNC_AUD_DAT_MISO0
- PINMUX_GPIO138__FUNC_AUD_DAT_MOSI0
- PINMUX_GPIO138__FUNC_DBG_MON_B24
- PINMUX_GPIO138__FUNC_GPIO138
- PINMUX_GPIO138__FUNC_I2S1_LRCK
- PINMUX_GPIO139__FUNC_AUD_DAT_MISO1
- PINMUX_GPIO139__FUNC_AUD_DAT_MOSI1
- PINMUX_GPIO139__FUNC_GPIO139
- PINMUX_GPIO139__FUNC_I2S1_DO
- PINMUX_GPIO139__FUNC_UFS_MPHY_SDA
- PINMUX_GPIO13__FUNC_ANT_SEL3
- PINMUX_GPIO13__FUNC_DBG_MON_B15
- PINMUX_GPIO13__FUNC_DBPI_D0
- PINMUX_GPIO13__FUNC_GPIO13
- PINMUX_GPIO13__FUNC_I2S0_MCK
- PINMUX_GPIO13__FUNC_MD_URXD0
- PINMUX_GPIO13__FUNC_PCM0_SYNC
- PINMUX_GPIO13__FUNC_SPI5_MI
- PINMUX_GPIO140__FUNC_AUD_CLK_MISO
- PINMUX_GPIO140__FUNC_AUD_CLK_MOSI
- PINMUX_GPIO140__FUNC_GPIO140
- PINMUX_GPIO140__FUNC_I2S0_MCK
- PINMUX_GPIO140__FUNC_UFS_UNIPRO_SDA
- PINMUX_GPIO141__FUNC_AUD_SYNC_MISO
- PINMUX_GPIO141__FUNC_AUD_SYNC_MOSI
- PINMUX_GPIO141__FUNC_GPIO141
- PINMUX_GPIO141__FUNC_I2S0_BCK
- PINMUX_GPIO142__FUNC_AUD_DAT_MISO0
- PINMUX_GPIO142__FUNC_AUD_DAT_MOSI0
- PINMUX_GPIO142__FUNC_DBG_MON_B25
- PINMUX_GPIO142__FUNC_GPIO142
- PINMUX_GPIO142__FUNC_I2S0_LRCK
- PINMUX_GPIO142__FUNC_VOW_DAT_MISO
- PINMUX_GPIO143__FUNC_AUD_DAT_MISO1
- PINMUX_GPIO143__FUNC_AUD_DAT_MOSI1
- PINMUX_GPIO143__FUNC_DBG_MON_B26
- PINMUX_GPIO143__FUNC_GPIO143
- PINMUX_GPIO143__FUNC_I2S0_DI
- PINMUX_GPIO143__FUNC_UFS_MPHY_SCL
- PINMUX_GPIO143__FUNC_VOW_CLK_MISO
- PINMUX_GPIO144__FUNC_GPIO144
- PINMUX_GPIO144__FUNC_PWRAP_SPI0_MI
- PINMUX_GPIO144__FUNC_PWRAP_SPI0_MO
- PINMUX_GPIO145__FUNC_GPIO145
- PINMUX_GPIO145__FUNC_PWRAP_SPI0_CSN
- PINMUX_GPIO146__FUNC_GPIO146
- PINMUX_GPIO146__FUNC_PWRAP_SPI0_MI
- PINMUX_GPIO146__FUNC_PWRAP_SPI0_MO
- PINMUX_GPIO147__FUNC_GPIO147
- PINMUX_GPIO147__FUNC_PWRAP_SPI0_CK
- PINMUX_GPIO148__FUNC_GPIO148
- PINMUX_GPIO148__FUNC_SRCLKENA0
- PINMUX_GPIO149__FUNC_GPIO149
- PINMUX_GPIO149__FUNC_SRCLKENA1
- PINMUX_GPIO14__FUNC_ANT_SEL4
- PINMUX_GPIO14__FUNC_DBG_MON_B16
- PINMUX_GPIO14__FUNC_DBPI_D1
- PINMUX_GPIO14__FUNC_GPIO14
- PINMUX_GPIO14__FUNC_I2S0_BCK
- PINMUX_GPIO14__FUNC_MD_UTXD0
- PINMUX_GPIO14__FUNC_PCM0_CLK
- PINMUX_GPIO14__FUNC_SPI5_CSB
- PINMUX_GPIO150__FUNC_CLKM0
- PINMUX_GPIO150__FUNC_CMFLASH
- PINMUX_GPIO150__FUNC_DBG_MON_B30
- PINMUX_GPIO150__FUNC_GPIO150
- PINMUX_GPIO150__FUNC_PWM_A
- PINMUX_GPIO151__FUNC_CLKM1
- PINMUX_GPIO151__FUNC_CMVREF0
- PINMUX_GPIO151__FUNC_DBG_MON_B20
- PINMUX_GPIO151__FUNC_GPIO151
- PINMUX_GPIO151__FUNC_PWM_B
- PINMUX_GPIO152__FUNC_CLKM2
- PINMUX_GPIO152__FUNC_CMFLASH
- PINMUX_GPIO152__FUNC_DBG_MON_B21
- PINMUX_GPIO152__FUNC_GPIO152
- PINMUX_GPIO152__FUNC_PWM_C
- PINMUX_GPIO153__FUNC_CLKM3
- PINMUX_GPIO153__FUNC_CMVREF0
- PINMUX_GPIO153__FUNC_DBG_MON_B22
- PINMUX_GPIO153__FUNC_GPIO153
- PINMUX_GPIO153__FUNC_PWM_A
- PINMUX_GPIO154__FUNC_DBG_MON_B18
- PINMUX_GPIO154__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO154__FUNC_GPIO154
- PINMUX_GPIO154__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO155__FUNC_ANT_SEL0
- PINMUX_GPIO155__FUNC_CMVREF1
- PINMUX_GPIO155__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO155__FUNC_GPIO155
- PINMUX_GPIO155__FUNC_SCP_JTAG_TDI
- PINMUX_GPIO156__FUNC_ANT_SEL1
- PINMUX_GPIO156__FUNC_GPIO156
- PINMUX_GPIO156__FUNC_IDDIG
- PINMUX_GPIO156__FUNC_KPCOL2
- PINMUX_GPIO156__FUNC_SCL6
- PINMUX_GPIO156__FUNC_SCP_JTAG_TCK
- PINMUX_GPIO156__FUNC_SRCLKENAI0
- PINMUX_GPIO157__FUNC_ANT_SEL2
- PINMUX_GPIO157__FUNC_GPIO157
- PINMUX_GPIO157__FUNC_KPROW2
- PINMUX_GPIO157__FUNC_SCP_JTAG_TRSTN
- PINMUX_GPIO157__FUNC_SDA6
- PINMUX_GPIO157__FUNC_SRCLKENAI1
- PINMUX_GPIO157__FUNC_USB_DRVVBUS
- PINMUX_GPIO158__FUNC_ANT_SEL3
- PINMUX_GPIO158__FUNC_GPIO158
- PINMUX_GPIO159__FUNC_ANT_SEL4
- PINMUX_GPIO159__FUNC_GPIO159
- PINMUX_GPIO15__FUNC_ANT_SEL5
- PINMUX_GPIO15__FUNC_DBG_MON_B17
- PINMUX_GPIO15__FUNC_DBPI_D2
- PINMUX_GPIO15__FUNC_GPIO15
- PINMUX_GPIO15__FUNC_I2S0_LRCK
- PINMUX_GPIO15__FUNC_MD_URXD1
- PINMUX_GPIO15__FUNC_PCM0_DO
- PINMUX_GPIO15__FUNC_SPI5_MO
- PINMUX_GPIO160__FUNC_ANT_SEL5
- PINMUX_GPIO160__FUNC_GPIO160
- PINMUX_GPIO161__FUNC_ANT_SEL6
- PINMUX_GPIO161__FUNC_DBG_MON_B19
- PINMUX_GPIO161__FUNC_GPIO161
- PINMUX_GPIO161__FUNC_IDDIG
- PINMUX_GPIO161__FUNC_KPCOL2
- PINMUX_GPIO161__FUNC_PTA_RXD
- PINMUX_GPIO161__FUNC_SCP_SPI1_MI
- PINMUX_GPIO161__FUNC_SPI1_A_MI
- PINMUX_GPIO162__FUNC_ANT_SEL5
- PINMUX_GPIO162__FUNC_GPIO162
- PINMUX_GPIO162__FUNC_KPROW2
- PINMUX_GPIO162__FUNC_PTA_TXD
- PINMUX_GPIO162__FUNC_SCP_SPI1_CS
- PINMUX_GPIO162__FUNC_SPI1_A_CSB
- PINMUX_GPIO162__FUNC_USB_DRVVBUS
- PINMUX_GPIO163__FUNC_ANT_SEL4
- PINMUX_GPIO163__FUNC_CMMCLK2
- PINMUX_GPIO163__FUNC_DMIC_CLK
- PINMUX_GPIO163__FUNC_GPIO163
- PINMUX_GPIO163__FUNC_SCP_SPI1_MO
- PINMUX_GPIO163__FUNC_SDA1
- PINMUX_GPIO163__FUNC_SPI1_A_MO
- PINMUX_GPIO164__FUNC_ANT_SEL3
- PINMUX_GPIO164__FUNC_CMMCLK3
- PINMUX_GPIO164__FUNC_DMIC_DAT
- PINMUX_GPIO164__FUNC_GPIO164
- PINMUX_GPIO164__FUNC_SCL1
- PINMUX_GPIO164__FUNC_SCP_SPI1_CK
- PINMUX_GPIO164__FUNC_SPI1_A_CLK
- PINMUX_GPIO165__FUNC_CMMCLK2
- PINMUX_GPIO165__FUNC_GPIO165
- PINMUX_GPIO165__FUNC_PWM_B
- PINMUX_GPIO165__FUNC_SCP_JTAG_TDO
- PINMUX_GPIO165__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO165__FUNC_TDM_MCK_2ND
- PINMUX_GPIO166__FUNC_ANT_SEL6
- PINMUX_GPIO166__FUNC_GPIO166
- PINMUX_GPIO167__FUNC_GPIO167
- PINMUX_GPIO167__FUNC_RFIC0_BSI_EN
- PINMUX_GPIO167__FUNC_SPM_BSI_EN
- PINMUX_GPIO168__FUNC_GPIO168
- PINMUX_GPIO168__FUNC_RFIC0_BSI_CK
- PINMUX_GPIO168__FUNC_SPM_BSI_CK
- PINMUX_GPIO169__FUNC_AGPS_SYNC
- PINMUX_GPIO169__FUNC_ANT_SEL7
- PINMUX_GPIO169__FUNC_CMMCLK3
- PINMUX_GPIO169__FUNC_CMVREF1
- PINMUX_GPIO169__FUNC_GPIO169
- PINMUX_GPIO169__FUNC_PWM_C
- PINMUX_GPIO169__FUNC_SCP_JTAG_TMS
- PINMUX_GPIO169__FUNC_TDM_BCK_2ND
- PINMUX_GPIO16__FUNC_ANT_SEL6
- PINMUX_GPIO16__FUNC_DBG_MON_B23
- PINMUX_GPIO16__FUNC_DBPI_D3
- PINMUX_GPIO16__FUNC_GPIO16
- PINMUX_GPIO16__FUNC_I2S0_DI
- PINMUX_GPIO16__FUNC_MD_UTXD1
- PINMUX_GPIO16__FUNC_PCM0_DI
- PINMUX_GPIO16__FUNC_SPI5_CLK
- PINMUX_GPIO170__FUNC_ANT_SEL3
- PINMUX_GPIO170__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO170__FUNC_GPIO170
- PINMUX_GPIO170__FUNC_I2S1_BCK
- PINMUX_GPIO170__FUNC_I2S3_BCK
- PINMUX_GPIO170__FUNC_I2S5_BCK
- PINMUX_GPIO170__FUNC_SCL7
- PINMUX_GPIO170__FUNC_TDM_LRCK_2ND
- PINMUX_GPIO171__FUNC_ANT_SEL4
- PINMUX_GPIO171__FUNC_GPIO171
- PINMUX_GPIO171__FUNC_I2S1_LRCK
- PINMUX_GPIO171__FUNC_I2S3_LRCK
- PINMUX_GPIO171__FUNC_I2S5_LRCK
- PINMUX_GPIO171__FUNC_SDA7
- PINMUX_GPIO171__FUNC_TDM_DATA0_2ND
- PINMUX_GPIO171__FUNC_URXD1
- PINMUX_GPIO172__FUNC_ANT_SEL5
- PINMUX_GPIO172__FUNC_GPIO172
- PINMUX_GPIO172__FUNC_I2S1_DO
- PINMUX_GPIO172__FUNC_I2S3_DO
- PINMUX_GPIO172__FUNC_I2S5_DO
- PINMUX_GPIO172__FUNC_SCL8
- PINMUX_GPIO172__FUNC_TDM_DATA1_2ND
- PINMUX_GPIO172__FUNC_UTXD1
- PINMUX_GPIO173__FUNC_ANT_SEL6
- PINMUX_GPIO173__FUNC_GPIO173
- PINMUX_GPIO173__FUNC_I2S1_MCK
- PINMUX_GPIO173__FUNC_I2S3_MCK
- PINMUX_GPIO173__FUNC_I2S5_MCK
- PINMUX_GPIO173__FUNC_SDA8
- PINMUX_GPIO173__FUNC_TDM_DATA2_2ND
- PINMUX_GPIO173__FUNC_UCTS0
- PINMUX_GPIO174__FUNC_ANT_SEL7
- PINMUX_GPIO174__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO174__FUNC_GPIO174
- PINMUX_GPIO174__FUNC_I2S0_DI
- PINMUX_GPIO174__FUNC_I2S2_DI
- PINMUX_GPIO174__FUNC_I2S2_DI2
- PINMUX_GPIO174__FUNC_TDM_DATA3_2ND
- PINMUX_GPIO174__FUNC_URTS0
- PINMUX_GPIO175__FUNC_ANT_SEL7
- PINMUX_GPIO175__FUNC_GPIO175
- PINMUX_GPIO176__FUNC_GPIO176
- PINMUX_GPIO177__FUNC_GPIO177
- PINMUX_GPIO178__FUNC_GPIO178
- PINMUX_GPIO179__FUNC_GPIO179
- PINMUX_GPIO17__FUNC_ANT_SEL7
- PINMUX_GPIO17__FUNC_CONN_MCU_TRST_B
- PINMUX_GPIO17__FUNC_DBG_MON_A1
- PINMUX_GPIO17__FUNC_DBPI_D4
- PINMUX_GPIO17__FUNC_GPIO17
- PINMUX_GPIO17__FUNC_I2S3_MCK
- PINMUX_GPIO17__FUNC_MD_INT0
- PINMUX_GPIO17__FUNC_SPI4_MI
- PINMUX_GPIO18__FUNC_CONN_MCU_DBGI_N
- PINMUX_GPIO18__FUNC_DBG_MON_A2
- PINMUX_GPIO18__FUNC_DBPI_D5
- PINMUX_GPIO18__FUNC_GPIO18
- PINMUX_GPIO18__FUNC_I2S3_BCK
- PINMUX_GPIO18__FUNC_MD_INT0
- PINMUX_GPIO18__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO18__FUNC_SPI4_CSB
- PINMUX_GPIO19__FUNC_CONN_MCU_TDO
- PINMUX_GPIO19__FUNC_DBG_MON_A3
- PINMUX_GPIO19__FUNC_DBPI_D6
- PINMUX_GPIO19__FUNC_GPIO19
- PINMUX_GPIO19__FUNC_I2S3_LRCK
- PINMUX_GPIO19__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG
- PINMUX_GPIO19__FUNC_SPI4_MO
- PINMUX_GPIO19__FUNC_URXD1
- PINMUX_GPIO1__FUNC_CLKM3
- PINMUX_GPIO1__FUNC_GPIO1
- PINMUX_GPIO1__FUNC_I2S3_BCK
- PINMUX_GPIO1__FUNC_MRG_CLK
- PINMUX_GPIO1__FUNC_PCM0_CLK
- PINMUX_GPIO1__FUNC_SCP_SPI2_MO
- PINMUX_GPIO1__FUNC_SPI2_MO
- PINMUX_GPIO1__FUNC_TP_GPIO1_AO
- PINMUX_GPIO20__FUNC_CONN_MCU_DBGACK_N
- PINMUX_GPIO20__FUNC_DBG_MON_A19
- PINMUX_GPIO20__FUNC_DBPI_D7
- PINMUX_GPIO20__FUNC_GPIO20
- PINMUX_GPIO20__FUNC_I2S3_DO
- PINMUX_GPIO20__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG
- PINMUX_GPIO20__FUNC_SPI4_CLK
- PINMUX_GPIO20__FUNC_UTXD1
- PINMUX_GPIO21__FUNC_CONN_MCU_AICE_TMSC
- PINMUX_GPIO21__FUNC_CONN_MCU_TMS
- PINMUX_GPIO21__FUNC_DAP_MD32_SWD
- PINMUX_GPIO21__FUNC_DBG_MON_B5
- PINMUX_GPIO21__FUNC_DBPI_D8
- PINMUX_GPIO21__FUNC_GPIO21
- PINMUX_GPIO21__FUNC_I2S2_MCK
- PINMUX_GPIO21__FUNC_SPI3_MI
- PINMUX_GPIO22__FUNC_CONN_MCU_AICE_TCKC
- PINMUX_GPIO22__FUNC_CONN_MCU_TCK
- PINMUX_GPIO22__FUNC_DAP_MD32_SWCK
- PINMUX_GPIO22__FUNC_DBG_MON_B6
- PINMUX_GPIO22__FUNC_DBPI_D9
- PINMUX_GPIO22__FUNC_GPIO22
- PINMUX_GPIO22__FUNC_I2S2_BCK
- PINMUX_GPIO22__FUNC_SPI3_CSB
- PINMUX_GPIO23__FUNC_CONN_MCU_TDI
- PINMUX_GPIO23__FUNC_DBG_MON_B7
- PINMUX_GPIO23__FUNC_DBPI_D10
- PINMUX_GPIO23__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO23__FUNC_GPIO23
- PINMUX_GPIO23__FUNC_I2S2_LRCK
- PINMUX_GPIO23__FUNC_SPI3_MO
- PINMUX_GPIO23__FUNC_UCTS1
- PINMUX_GPIO24__FUNC_DBG_MON_B31
- PINMUX_GPIO24__FUNC_DBPI_D11
- PINMUX_GPIO24__FUNC_GPIO24
- PINMUX_GPIO24__FUNC_I2S2_DI
- PINMUX_GPIO24__FUNC_IO_JTAG_TCK
- PINMUX_GPIO24__FUNC_SPI3_CLK
- PINMUX_GPIO24__FUNC_SRCLKENAI0
- PINMUX_GPIO24__FUNC_URTS1
- PINMUX_GPIO25__FUNC_ANT_SEL0
- PINMUX_GPIO25__FUNC_DBG_MON_B0
- PINMUX_GPIO25__FUNC_DBPI_HSYNC
- PINMUX_GPIO25__FUNC_GPIO25
- PINMUX_GPIO25__FUNC_I2S1_MCK
- PINMUX_GPIO25__FUNC_IO_JTAG_TMS
- PINMUX_GPIO25__FUNC_KPCOL2
- PINMUX_GPIO25__FUNC_SCL6
- PINMUX_GPIO26__FUNC_ANT_SEL1
- PINMUX_GPIO26__FUNC_DBG_MON_B1
- PINMUX_GPIO26__FUNC_DBPI_VSYNC
- PINMUX_GPIO26__FUNC_GPIO26
- PINMUX_GPIO26__FUNC_I2S1_BCK
- PINMUX_GPIO26__FUNC_IO_JTAG_TDI
- PINMUX_GPIO26__FUNC_KPROW2
- PINMUX_GPIO26__FUNC_SDA6
- PINMUX_GPIO27__FUNC_ANT_SEL2
- PINMUX_GPIO27__FUNC_DBG_MON_B9
- PINMUX_GPIO27__FUNC_DBPI_DE
- PINMUX_GPIO27__FUNC_DMIC_CLK
- PINMUX_GPIO27__FUNC_GPIO27
- PINMUX_GPIO27__FUNC_I2S1_LRCK
- PINMUX_GPIO27__FUNC_IO_JTAG_TDO
- PINMUX_GPIO27__FUNC_SCL7
- PINMUX_GPIO28__FUNC_DBG_MON_B32
- PINMUX_GPIO28__FUNC_DBPI_CK
- PINMUX_GPIO28__FUNC_DMIC_DAT
- PINMUX_GPIO28__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO28__FUNC_GPIO28
- PINMUX_GPIO28__FUNC_I2S1_DO
- PINMUX_GPIO28__FUNC_IO_JTAG_TRSTN
- PINMUX_GPIO28__FUNC_SDA7
- PINMUX_GPIO29__FUNC_CONN_DSP_JCK
- PINMUX_GPIO29__FUNC_DBG_MON_A6
- PINMUX_GPIO29__FUNC_GPIO29
- PINMUX_GPIO29__FUNC_IO_JTAG_TCK
- PINMUX_GPIO29__FUNC_MSDC1_CLK
- PINMUX_GPIO29__FUNC_PCM1_CLK
- PINMUX_GPIO29__FUNC_SSPM_JTAG_TCK
- PINMUX_GPIO29__FUNC_UDI_TCK
- PINMUX_GPIO2__FUNC_GPIO2
- PINMUX_GPIO2__FUNC_I2S3_LRCK
- PINMUX_GPIO2__FUNC_MRG_DO
- PINMUX_GPIO2__FUNC_PCM0_DO
- PINMUX_GPIO2__FUNC_SCL6
- PINMUX_GPIO2__FUNC_SCP_SPI2_CK
- PINMUX_GPIO2__FUNC_SPI2_CLK
- PINMUX_GPIO2__FUNC_TP_GPIO2_AO
- PINMUX_GPIO30__FUNC_CONN_DSP_JINTP
- PINMUX_GPIO30__FUNC_CONN_MCU_AICE_TMSC
- PINMUX_GPIO30__FUNC_DAP_MD32_SWD
- PINMUX_GPIO30__FUNC_DBG_MON_A7
- PINMUX_GPIO30__FUNC_GPIO30
- PINMUX_GPIO30__FUNC_MSDC1_DAT3
- PINMUX_GPIO30__FUNC_PCM1_DI
- PINMUX_GPIO30__FUNC_SSPM_JTAG_TRSTN
- PINMUX_GPIO31__FUNC_CONN_DSP_JMS
- PINMUX_GPIO31__FUNC_DBG_MON_A8
- PINMUX_GPIO31__FUNC_GPIO31
- PINMUX_GPIO31__FUNC_IO_JTAG_TMS
- PINMUX_GPIO31__FUNC_MSDC1_CMD
- PINMUX_GPIO31__FUNC_PCM1_SYNC
- PINMUX_GPIO31__FUNC_SSPM_JTAG_TMS
- PINMUX_GPIO31__FUNC_UDI_TMS
- PINMUX_GPIO32__FUNC_CONN_DSP_JDI
- PINMUX_GPIO32__FUNC_DBG_MON_A9
- PINMUX_GPIO32__FUNC_GPIO32
- PINMUX_GPIO32__FUNC_IO_JTAG_TDI
- PINMUX_GPIO32__FUNC_MSDC1_DAT0
- PINMUX_GPIO32__FUNC_PCM1_DO0
- PINMUX_GPIO32__FUNC_SSPM_JTAG_TDI
- PINMUX_GPIO32__FUNC_UDI_TDI
- PINMUX_GPIO33__FUNC_CONN_MCU_AICE_TCKC
- PINMUX_GPIO33__FUNC_DAP_MD32_SWCK
- PINMUX_GPIO33__FUNC_DBG_MON_A10
- PINMUX_GPIO33__FUNC_GPIO33
- PINMUX_GPIO33__FUNC_IO_JTAG_TRSTN
- PINMUX_GPIO33__FUNC_MSDC1_DAT2
- PINMUX_GPIO33__FUNC_PCM1_DO2
- PINMUX_GPIO33__FUNC_UDI_NTRST
- PINMUX_GPIO34__FUNC_CONN_DSP_JDO
- PINMUX_GPIO34__FUNC_DBG_MON_A11
- PINMUX_GPIO34__FUNC_GPIO34
- PINMUX_GPIO34__FUNC_IO_JTAG_TDO
- PINMUX_GPIO34__FUNC_MSDC1_DAT1
- PINMUX_GPIO34__FUNC_PCM1_DO1
- PINMUX_GPIO34__FUNC_SSPM_JTAG_TDO
- PINMUX_GPIO34__FUNC_UDI_TDO
- PINMUX_GPIO35__FUNC_CCU_JTAG_TDO
- PINMUX_GPIO35__FUNC_CONN_DSP_JMS
- PINMUX_GPIO35__FUNC_DBG_MON_A28
- PINMUX_GPIO35__FUNC_GPIO35
- PINMUX_GPIO35__FUNC_MD1_SIM1_SIO
- PINMUX_GPIO35__FUNC_MD1_SIM2_SIO
- PINMUX_GPIO35__FUNC_SCP_JTAG_TDO
- PINMUX_GPIO36__FUNC_CCU_JTAG_TMS
- PINMUX_GPIO36__FUNC_CONN_DSP_JINTP
- PINMUX_GPIO36__FUNC_CONN_MCU_AICE_TMSC
- PINMUX_GPIO36__FUNC_DBG_MON_A29
- PINMUX_GPIO36__FUNC_GPIO36
- PINMUX_GPIO36__FUNC_MD1_SIM1_SRST
- PINMUX_GPIO36__FUNC_MD1_SIM2_SRST
- PINMUX_GPIO36__FUNC_SCP_JTAG_TMS
- PINMUX_GPIO37__FUNC_CCU_JTAG_TDI
- PINMUX_GPIO37__FUNC_CONN_DSP_JDO
- PINMUX_GPIO37__FUNC_DBG_MON_A30
- PINMUX_GPIO37__FUNC_GPIO37
- PINMUX_GPIO37__FUNC_MD1_SIM1_SCLK
- PINMUX_GPIO37__FUNC_MD1_SIM2_SCLK
- PINMUX_GPIO37__FUNC_SCP_JTAG_TDI
- PINMUX_GPIO38__FUNC_CONN_MCU_AICE_TCKC
- PINMUX_GPIO38__FUNC_DBG_MON_A20
- PINMUX_GPIO38__FUNC_GPIO38
- PINMUX_GPIO38__FUNC_MD1_SIM1_SCLK
- PINMUX_GPIO38__FUNC_MD1_SIM2_SCLK
- PINMUX_GPIO39__FUNC_CCU_JTAG_TCK
- PINMUX_GPIO39__FUNC_CONN_DSP_JCK
- PINMUX_GPIO39__FUNC_DBG_MON_A31
- PINMUX_GPIO39__FUNC_GPIO39
- PINMUX_GPIO39__FUNC_MD1_SIM1_SRST
- PINMUX_GPIO39__FUNC_MD1_SIM2_SRST
- PINMUX_GPIO39__FUNC_SCP_JTAG_TCK
- PINMUX_GPIO3__FUNC_GPIO3
- PINMUX_GPIO3__FUNC_I2S3_DO
- PINMUX_GPIO3__FUNC_MRG_DI
- PINMUX_GPIO3__FUNC_PCM0_DI
- PINMUX_GPIO3__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO3__FUNC_SDA6
- PINMUX_GPIO3__FUNC_TDM_MCK
- PINMUX_GPIO3__FUNC_TP_GPIO3_AO
- PINMUX_GPIO40__FUNC_CCU_JTAG_TRST
- PINMUX_GPIO40__FUNC_CONN_DSP_JDI
- PINMUX_GPIO40__FUNC_DBG_MON_A32
- PINMUX_GPIO40__FUNC_GPIO40
- PINMUX_GPIO40__FUNC_MD1_SIM1_SIO
- PINMUX_GPIO40__FUNC_MD1_SIM2_SIO
- PINMUX_GPIO40__FUNC_SCP_JTAG_TRSTN
- PINMUX_GPIO41__FUNC_DMIC_CLK
- PINMUX_GPIO41__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO41__FUNC_GPIO41
- PINMUX_GPIO41__FUNC_IDDIG
- PINMUX_GPIO41__FUNC_SSPM_UTXD_AO
- PINMUX_GPIO41__FUNC_UCTS0
- PINMUX_GPIO41__FUNC_URXD1
- PINMUX_GPIO42__FUNC_DMIC_DAT
- PINMUX_GPIO42__FUNC_EXT_FRAME_SYNC
- PINMUX_GPIO42__FUNC_GPIO42
- PINMUX_GPIO42__FUNC_SSPM_URXD_AO
- PINMUX_GPIO42__FUNC_URTS0
- PINMUX_GPIO42__FUNC_USB_DRVVBUS
- PINMUX_GPIO42__FUNC_UTXD1
- PINMUX_GPIO43__FUNC_DISP_PWM
- PINMUX_GPIO43__FUNC_GPIO43
- PINMUX_GPIO44__FUNC_DSI_TE
- PINMUX_GPIO44__FUNC_GPIO44
- PINMUX_GPIO45__FUNC_GPIO45
- PINMUX_GPIO45__FUNC_LCM_RST
- PINMUX_GPIO46__FUNC_CCU_UTXD_AO
- PINMUX_GPIO46__FUNC_GPIO46
- PINMUX_GPIO46__FUNC_I2S5_LRCK
- PINMUX_GPIO46__FUNC_IDDIG
- PINMUX_GPIO46__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG
- PINMUX_GPIO46__FUNC_TP_UCTS1_AO
- PINMUX_GPIO46__FUNC_UCTS1
- PINMUX_GPIO46__FUNC_URXD1
- PINMUX_GPIO47__FUNC_CCU_URXD_AO
- PINMUX_GPIO47__FUNC_GPIO47
- PINMUX_GPIO47__FUNC_I2S5_DO
- PINMUX_GPIO47__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG
- PINMUX_GPIO47__FUNC_TP_URTS1_AO
- PINMUX_GPIO47__FUNC_URTS1
- PINMUX_GPIO47__FUNC_USB_DRVVBUS
- PINMUX_GPIO47__FUNC_UTXD1
- PINMUX_GPIO48__FUNC_GPIO48
- PINMUX_GPIO48__FUNC_SCL5
- PINMUX_GPIO49__FUNC_GPIO49
- PINMUX_GPIO49__FUNC_SDA5
- PINMUX_GPIO4__FUNC_DAP_MD32_SWD
- PINMUX_GPIO4__FUNC_GPIO4
- PINMUX_GPIO4__FUNC_I2S0_MCK
- PINMUX_GPIO4__FUNC_MD_URXD1
- PINMUX_GPIO4__FUNC_PWM_B
- PINMUX_GPIO4__FUNC_SSPM_UTXD_AO
- PINMUX_GPIO4__FUNC_TDM_BCK
- PINMUX_GPIO4__FUNC_TP_GPIO4_AO
- PINMUX_GPIO50__FUNC_GPIO50
- PINMUX_GPIO50__FUNC_SCL3
- PINMUX_GPIO51__FUNC_GPIO51
- PINMUX_GPIO51__FUNC_SDA3
- PINMUX_GPIO52__FUNC_BPI_ANT2
- PINMUX_GPIO52__FUNC_GPIO52
- PINMUX_GPIO53__FUNC_BPI_ANT0
- PINMUX_GPIO53__FUNC_GPIO53
- PINMUX_GPIO54__FUNC_BPI_OLAT1
- PINMUX_GPIO54__FUNC_GPIO54
- PINMUX_GPIO55__FUNC_BPI_BUS8
- PINMUX_GPIO55__FUNC_GPIO55
- PINMUX_GPIO56__FUNC_BPI_BUS9
- PINMUX_GPIO56__FUNC_GPIO56
- PINMUX_GPIO56__FUNC_SCL_6306
- PINMUX_GPIO57__FUNC_BPI_BUS10
- PINMUX_GPIO57__FUNC_GPIO57
- PINMUX_GPIO57__FUNC_SDA_6306
- PINMUX_GPIO58__FUNC_GPIO58
- PINMUX_GPIO58__FUNC_PWM_B
- PINMUX_GPIO58__FUNC_RFIC0_BSI_D2
- PINMUX_GPIO58__FUNC_SPM_BSI_D2
- PINMUX_GPIO59__FUNC_GPIO59
- PINMUX_GPIO59__FUNC_RFIC0_BSI_D1
- PINMUX_GPIO59__FUNC_SPM_BSI_D1
- PINMUX_GPIO5__FUNC_DAP_MD32_SWCK
- PINMUX_GPIO5__FUNC_GPIO5
- PINMUX_GPIO5__FUNC_I2S0_BCK
- PINMUX_GPIO5__FUNC_MD_UTXD1
- PINMUX_GPIO5__FUNC_PWM_C
- PINMUX_GPIO5__FUNC_SSPM_URXD_AO
- PINMUX_GPIO5__FUNC_TDM_LRCK
- PINMUX_GPIO5__FUNC_TP_GPIO5_AO
- PINMUX_GPIO60__FUNC_GPIO60
- PINMUX_GPIO60__FUNC_RFIC0_BSI_D0
- PINMUX_GPIO60__FUNC_SPM_BSI_D0
- PINMUX_GPIO61__FUNC_GPIO61
- PINMUX_GPIO61__FUNC_MIPI1_SDATA
- PINMUX_GPIO62__FUNC_GPIO62
- PINMUX_GPIO62__FUNC_MIPI1_SCLK
- PINMUX_GPIO63__FUNC_GPIO63
- PINMUX_GPIO63__FUNC_MIPI0_SDATA
- PINMUX_GPIO64__FUNC_GPIO64
- PINMUX_GPIO64__FUNC_MIPI0_SCLK
- PINMUX_GPIO65__FUNC_BPI_OLAT2
- PINMUX_GPIO65__FUNC_GPIO65
- PINMUX_GPIO65__FUNC_MIPI3_SDATA
- PINMUX_GPIO66__FUNC_BPI_OLAT3
- PINMUX_GPIO66__FUNC_GPIO66
- PINMUX_GPIO66__FUNC_MIPI3_SCLK
- PINMUX_GPIO67__FUNC_GPIO67
- PINMUX_GPIO67__FUNC_MIPI2_SDATA
- PINMUX_GPIO68__FUNC_GPIO68
- PINMUX_GPIO68__FUNC_MIPI2_SCLK
- PINMUX_GPIO69__FUNC_BPI_BUS7
- PINMUX_GPIO69__FUNC_GPIO69
- PINMUX_GPIO6__FUNC_CMFLASH
- PINMUX_GPIO6__FUNC_GPIO6
- PINMUX_GPIO6__FUNC_I2S0_LRCK
- PINMUX_GPIO6__FUNC_IDDIG
- PINMUX_GPIO6__FUNC_MD_URXD0
- PINMUX_GPIO6__FUNC_PWM_A
- PINMUX_GPIO6__FUNC_TDM_DATA0
- PINMUX_GPIO6__FUNC_TP_GPIO6_AO
- PINMUX_GPIO70__FUNC_BPI_BUS6
- PINMUX_GPIO70__FUNC_GPIO70
- PINMUX_GPIO71__FUNC_BPI_BUS5
- PINMUX_GPIO71__FUNC_GPIO71
- PINMUX_GPIO72__FUNC_BPI_BUS4
- PINMUX_GPIO72__FUNC_GPIO72
- PINMUX_GPIO73__FUNC_BPI_BUS3
- PINMUX_GPIO73__FUNC_GPIO73
- PINMUX_GPIO74__FUNC_BPI_BUS2
- PINMUX_GPIO74__FUNC_GPIO74
- PINMUX_GPIO75__FUNC_BPI_BUS1
- PINMUX_GPIO75__FUNC_GPIO75
- PINMUX_GPIO76__FUNC_BPI_BUS0
- PINMUX_GPIO76__FUNC_GPIO76
- PINMUX_GPIO77__FUNC_BPI_ANT1
- PINMUX_GPIO77__FUNC_GPIO77
- PINMUX_GPIO78__FUNC_BPI_OLAT0
- PINMUX_GPIO78__FUNC_GPIO78
- PINMUX_GPIO79__FUNC_BPI_PA_VM1
- PINMUX_GPIO79__FUNC_GPIO79
- PINMUX_GPIO79__FUNC_MIPI4_SDATA
- PINMUX_GPIO7__FUNC_DVFSRC_EXT_REQ
- PINMUX_GPIO7__FUNC_GPIO7
- PINMUX_GPIO7__FUNC_I2S0_DI
- PINMUX_GPIO7__FUNC_MD_UTXD0
- PINMUX_GPIO7__FUNC_SPI1_B_MI
- PINMUX_GPIO7__FUNC_TDM_DATA1
- PINMUX_GPIO7__FUNC_TP_GPIO7_AO
- PINMUX_GPIO7__FUNC_USB_DRVVBUS
- PINMUX_GPIO80__FUNC_BPI_PA_VM0
- PINMUX_GPIO80__FUNC_GPIO80
- PINMUX_GPIO80__FUNC_MIPI4_SCLK
- PINMUX_GPIO81__FUNC_GPIO81
- PINMUX_GPIO81__FUNC_SDA1
- PINMUX_GPIO82__FUNC_GPIO82
- PINMUX_GPIO82__FUNC_SDA0
- PINMUX_GPIO83__FUNC_GPIO83
- PINMUX_GPIO83__FUNC_SCL0
- PINMUX_GPIO84__FUNC_GPIO84
- PINMUX_GPIO84__FUNC_SCL1
- PINMUX_GPIO85__FUNC_CLKM3
- PINMUX_GPIO85__FUNC_DFD_TDO
- PINMUX_GPIO85__FUNC_GPIO85
- PINMUX_GPIO85__FUNC_I2S1_BCK
- PINMUX_GPIO85__FUNC_JTDO_SEL1
- PINMUX_GPIO85__FUNC_MFG_DFD_JTAG_TDO
- PINMUX_GPIO85__FUNC_SCP_SPI0_MI
- PINMUX_GPIO85__FUNC_SPI0_MI
- PINMUX_GPIO86__FUNC_CLKM0
- PINMUX_GPIO86__FUNC_DFD_TMS
- PINMUX_GPIO86__FUNC_GPIO86
- PINMUX_GPIO86__FUNC_I2S1_LRCK
- PINMUX_GPIO86__FUNC_JTMS_SEL1
- PINMUX_GPIO86__FUNC_MFG_DFD_JTAG_TMS
- PINMUX_GPIO86__FUNC_SCP_SPI0_CS
- PINMUX_GPIO86__FUNC_SPI0_CSB
- PINMUX_GPIO87__FUNC_DFD_TDI
- PINMUX_GPIO87__FUNC_GPIO87
- PINMUX_GPIO87__FUNC_I2S1_DO
- PINMUX_GPIO87__FUNC_JTDI_SEL1
- PINMUX_GPIO87__FUNC_MFG_DFD_JTAG_TDI
- PINMUX_GPIO87__FUNC_SCP_SPI0_MO
- PINMUX_GPIO87__FUNC_SDA1
- PINMUX_GPIO87__FUNC_SPI0_MO
- PINMUX_GPIO88__FUNC_DFD_TCK_XI
- PINMUX_GPIO88__FUNC_GPIO88
- PINMUX_GPIO88__FUNC_I2S1_MCK
- PINMUX_GPIO88__FUNC_JTCK_SEL1
- PINMUX_GPIO88__FUNC_MFG_DFD_JTAG_TCK
- PINMUX_GPIO88__FUNC_SCL1
- PINMUX_GPIO88__FUNC_SCP_SPI0_CK
- PINMUX_GPIO88__FUNC_SPI0_CLK
- PINMUX_GPIO89__FUNC_ANT_SEL6
- PINMUX_GPIO89__FUNC_CMVREF0
- PINMUX_GPIO89__FUNC_DBG_MON_A21
- PINMUX_GPIO89__FUNC_GPIO89
- PINMUX_GPIO89__FUNC_I2S5_BCK
- PINMUX_GPIO89__FUNC_PWM_C
- PINMUX_GPIO89__FUNC_SDA8
- PINMUX_GPIO89__FUNC_SRCLKENAI0
- PINMUX_GPIO8__FUNC_ANT_SEL3
- PINMUX_GPIO8__FUNC_CONN_MCU_TRST_B
- PINMUX_GPIO8__FUNC_GPIO8
- PINMUX_GPIO8__FUNC_JTRSTN_SEL1
- PINMUX_GPIO8__FUNC_MD_INT0
- PINMUX_GPIO8__FUNC_SCL7
- PINMUX_GPIO8__FUNC_SPI1_B_CSB
- PINMUX_GPIO8__FUNC_TDM_DATA2
- PINMUX_GPIO90__FUNC_CMMCLK2
- PINMUX_GPIO90__FUNC_DBG_MON_A22
- PINMUX_GPIO90__FUNC_GPIO90
- PINMUX_GPIO90__FUNC_I2S5_LRCK
- PINMUX_GPIO90__FUNC_PTA_RXD
- PINMUX_GPIO90__FUNC_PWM_A
- PINMUX_GPIO90__FUNC_SCL8
- PINMUX_GPIO90__FUNC_SCP_VREQ_VAO
- PINMUX_GPIO91__FUNC_ANT_SEL7
- PINMUX_GPIO91__FUNC_CMMCLK3
- PINMUX_GPIO91__FUNC_GPIO91
- PINMUX_GPIO91__FUNC_I2S5_DO
- PINMUX_GPIO91__FUNC_KPROW1
- PINMUX_GPIO91__FUNC_PTA_TXD
- PINMUX_GPIO91__FUNC_PWM_B
- PINMUX_GPIO92__FUNC_GPIO92
- PINMUX_GPIO92__FUNC_KPROW0
- PINMUX_GPIO93__FUNC_DBG_MON_B27
- PINMUX_GPIO93__FUNC_GPIO93
- PINMUX_GPIO93__FUNC_KPCOL0
- PINMUX_GPIO94__FUNC_CMMCLK2
- PINMUX_GPIO94__FUNC_GPIO94
- PINMUX_GPIO94__FUNC_I2S2_DI2
- PINMUX_GPIO94__FUNC_I2S5_MCK
- PINMUX_GPIO94__FUNC_KPCOL1
- PINMUX_GPIO94__FUNC_SCP_SPI2_MI
- PINMUX_GPIO94__FUNC_SPI2_MI
- PINMUX_GPIO94__FUNC_SRCLKENAI1
- PINMUX_GPIO95__FUNC_CCU_URXD_AO
- PINMUX_GPIO95__FUNC_GPIO95
- PINMUX_GPIO95__FUNC_MD_URXD0
- PINMUX_GPIO95__FUNC_MD_URXD1
- PINMUX_GPIO95__FUNC_SSPM_URXD_AO
- PINMUX_GPIO95__FUNC_URXD0
- PINMUX_GPIO95__FUNC_UTXD0
- PINMUX_GPIO96__FUNC_CCU_UTXD_AO
- PINMUX_GPIO96__FUNC_DBG_MON_B2
- PINMUX_GPIO96__FUNC_GPIO96
- PINMUX_GPIO96__FUNC_MD_UTXD0
- PINMUX_GPIO96__FUNC_MD_UTXD1
- PINMUX_GPIO96__FUNC_SSPM_UTXD_AO
- PINMUX_GPIO96__FUNC_URXD0
- PINMUX_GPIO96__FUNC_UTXD0
- PINMUX_GPIO97__FUNC_CONN_MCU_TDO
- PINMUX_GPIO97__FUNC_DBG_MON_B3
- PINMUX_GPIO97__FUNC_GPIO97
- PINMUX_GPIO97__FUNC_I2S2_MCK
- PINMUX_GPIO97__FUNC_IDDIG
- PINMUX_GPIO97__FUNC_IO_JTAG_TDO
- PINMUX_GPIO97__FUNC_SSPM_JTAG_TDO
- PINMUX_GPIO97__FUNC_UCTS0
- PINMUX_GPIO98__FUNC_CONN_MCU_TMS
- PINMUX_GPIO98__FUNC_DBG_MON_B4
- PINMUX_GPIO98__FUNC_GPIO98
- PINMUX_GPIO98__FUNC_I2S2_BCK
- PINMUX_GPIO98__FUNC_IO_JTAG_TMS
- PINMUX_GPIO98__FUNC_SSPM_JTAG_TMS
- PINMUX_GPIO98__FUNC_URTS0
- PINMUX_GPIO98__FUNC_USB_DRVVBUS
- PINMUX_GPIO99__FUNC_CMMCLK0
- PINMUX_GPIO99__FUNC_CONN_MCU_AICE_TMSC
- PINMUX_GPIO99__FUNC_DBG_MON_B28
- PINMUX_GPIO99__FUNC_GPIO99
- PINMUX_GPIO9__FUNC_ANT_SEL4
- PINMUX_GPIO9__FUNC_CMMCLK2
- PINMUX_GPIO9__FUNC_CONN_MCU_DBGACK_N
- PINMUX_GPIO9__FUNC_DBG_MON_B10
- PINMUX_GPIO9__FUNC_GPIO9
- PINMUX_GPIO9__FUNC_IO_JTAG_TRSTN
- PINMUX_GPIO9__FUNC_SPI1_B_MO
- PINMUX_GPIO9__FUNC_SSPM_JTAG_TRSTN
- PINMUX_GPIO_GP_ALL
- PINMUX_GPSR
- PINMUX_INPUT_BEGIN
- PINMUX_INPUT_END
- PINMUX_IPSR
- PINMUX_IPSR_GPSR
- PINMUX_IPSR_MSEL
- PINMUX_IPSR_NOFN
- PINMUX_IPSR_NOGM
- PINMUX_IPSR_NOGP
- PINMUX_IPSR_PHYS
- PINMUX_IPSR_PHYS_MSEL
- PINMUX_IRQ
- PINMUX_MARK_BEGIN
- PINMUX_MARK_END
- PINMUX_MOD_SELS
- PINMUX_OUTPUT_BEGIN
- PINMUX_OUTPUT_END
- PINMUX_PHYS
- PINMUX_PIN
- PINMUX_RESERVED
- PINMUX_SINGLE
- PINMUX_STATIC
- PINMUX_TYPE_FUNCTION
- PINMUX_TYPE_GPIO
- PINMUX_TYPE_INPUT
- PINMUX_TYPE_INPUT_PULLDOWN
- PINMUX_TYPE_INPUT_PULLUP
- PINMUX_TYPE_NONE
- PINMUX_TYPE_OUTPUT
- PINMUX_TYPE_OUTPUT_HIGH
- PINMUX_TYPE_OUTPUT_LOW
- PINNA_LINX_VD_IN_CAB_NTSC
- PINNA_LINX_VD_IN_CAB_PAL
- PINNA_PCTV_BUNGEE_PAL_FM
- PINNA_PCTV_USB_NTSC_FM
- PINNA_PCTV_USB_NTSC_FM_V2
- PINNA_PCTV_USB_NTSC_FM_V3
- PINNA_PCTV_USB_PAL
- PINNA_PCTV_USB_PAL_FM
- PINNA_PCTV_USB_PAL_FM_V2
- PINNA_PCTV_USB_PAL_FM_V3
- PINNA_PCTV_USB_SECAM
- PINS
- PINSTR
- PINS_COUNT
- PINS_FIELD
- PINS_FIELD16
- PINS_FIELD_BASE
- PINS_PER_BANK
- PINS_PER_COLLECTION
- PINS_PER_GPIO_CHIP
- PINT
- PINT0
- PINT07
- PINT0_PB_MARK
- PINT0_PD_MARK
- PINT0_PG_MARK
- PINT0_PH_MARK
- PINT0_PJ_MARK
- PINT1
- PINT1_PB_MARK
- PINT1_PD_MARK
- PINT1_PG_MARK
- PINT1_PH_MARK
- PINT1_PJ_MARK
- PINT2
- PINT2_PB_MARK
- PINT2_PD_MARK
- PINT2_PG_MARK
- PINT2_PH_MARK
- PINT2_PJ_MARK
- PINT3
- PINT3_PB_MARK
- PINT3_PD_MARK
- PINT3_PG_MARK
- PINT3_PH_MARK
- PINT3_PJ_MARK
- PINT4
- PINT4_PB_MARK
- PINT4_PD_MARK
- PINT4_PG_MARK
- PINT4_PH_MARK
- PINT4_PJ_MARK
- PINT5
- PINT5_PB_MARK
- PINT5_PD_MARK
- PINT5_PG_MARK
- PINT5_PH_MARK
- PINT5_PJ_MARK
- PINT6
- PINT6_PB_MARK
- PINT6_PD_MARK
- PINT6_PG_MARK
- PINT6_PH_MARK
- PINT6_PJ_MARK
- PINT7
- PINT7_PB_MARK
- PINT7_PD_MARK
- PINT7_PG_MARK
- PINT7_PH_MARK
- PINT7_PJ_MARK
- PINT815
- PINTC_HIDISR
- PINTC_HIER
- PINTC_HIPIR
- PINTFIFO
- PIN_ALT
- PIN_ALT_A
- PIN_ALT_B
- PIN_ALT_C
- PIN_ALT_MASK
- PIN_ALT_SHIFT
- PIN_ASSIGN_C_E
- PIN_ASSIGN_D_F
- PIN_AUTOLF
- PIN_BANK
- PIN_BANK_2BIT
- PIN_BANK_2BIT_EINTG
- PIN_BANK_2BIT_EINTW
- PIN_BANK_4BIT
- PIN_BANK_4BIT2_ALIVE
- PIN_BANK_4BIT2_EINTG
- PIN_BANK_4BIT2_EINTW
- PIN_BANK_4BIT_EINTG
- PIN_BANK_4BIT_EINTW
- PIN_BANK_A
- PIN_BANK_DRV_FLAGS
- PIN_BANK_DRV_FLAGS_PULL_FLAGS
- PIN_BANK_IOMUX_DRV_FLAGS_OFFSET
- PIN_BANK_IOMUX_FLAGS
- PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS
- PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
- PIN_BASED_EXT_INTR_MASK
- PIN_BASED_NMI_EXITING
- PIN_BASED_POSTED_INTR
- PIN_BASED_VIRTUAL_NMIS
- PIN_BASED_VMX_PREEMPTION_TIMER
- PIN_BASED_VM_EXEC_CONTROL
- PIN_BIT_ACLKR
- PIN_BIT_ACLKX
- PIN_BIT_AFSR
- PIN_BIT_AFSX
- PIN_BIT_AHCLKR
- PIN_BIT_AHCLKX
- PIN_BIT_AMUTE
- PIN_BIT_AXR
- PIN_BOND_REG0
- PIN_BOND_REG1
- PIN_BOND_REG2
- PIN_CFG
- PIN_CFG_BYTE
- PIN_CFG_COL
- PIN_CFG_DEFAULT
- PIN_CFG_EPIO0
- PIN_CFG_EPIO1
- PIN_CFG_EPIO10
- PIN_CFG_EPIO11
- PIN_CFG_EPIO12
- PIN_CFG_EPIO13
- PIN_CFG_EPIO14
- PIN_CFG_EPIO15
- PIN_CFG_EPIO16
- PIN_CFG_EPIO17
- PIN_CFG_EPIO18
- PIN_CFG_EPIO19
- PIN_CFG_EPIO2
- PIN_CFG_EPIO20
- PIN_CFG_EPIO21
- PIN_CFG_EPIO22
- PIN_CFG_EPIO23
- PIN_CFG_EPIO24
- PIN_CFG_EPIO25
- PIN_CFG_EPIO26
- PIN_CFG_EPIO27
- PIN_CFG_EPIO28
- PIN_CFG_EPIO29
- PIN_CFG_EPIO3
- PIN_CFG_EPIO30
- PIN_CFG_EPIO31
- PIN_CFG_EPIO4
- PIN_CFG_EPIO5
- PIN_CFG_EPIO6
- PIN_CFG_EPIO7
- PIN_CFG_EPIO8
- PIN_CFG_EPIO9
- PIN_CFG_GPIO0_P0
- PIN_CFG_GPIO0_P1
- PIN_CFG_GPIO1_P0
- PIN_CFG_GPIO1_P1
- PIN_CFG_GPIO2_P0
- PIN_CFG_GPIO2_P1
- PIN_CFG_GPIO3_P0
- PIN_CFG_GPIO3_P1
- PIN_CFG_IGNORE
- PIN_CFG_INPUT
- PIN_CFG_NA
- PIN_CFG_OUTPUT
- PIN_CFG_ROW
- PIN_CLK0
- PIN_CLK1
- PIN_CLK2
- PIN_CLK3
- PIN_COLLECTIONS
- PIN_CONFIG_ACTIVE_HIGH
- PIN_CONFIG_BIAS_BUS_HOLD
- PIN_CONFIG_BIAS_DISABLE
- PIN_CONFIG_BIAS_HIGH_IMPEDANCE
- PIN_CONFIG_BIAS_PULL_DOWN
- PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
- PIN_CONFIG_BIAS_PULL_UP
- PIN_CONFIG_DRIVE_OPEN_DRAIN
- PIN_CONFIG_DRIVE_OPEN_SOURCE
- PIN_CONFIG_DRIVE_PUSH_PULL
- PIN_CONFIG_DRIVE_STRENGTH
- PIN_CONFIG_DRIVE_STRENGTH_UA
- PIN_CONFIG_END
- PIN_CONFIG_GPIO_PIN_INT
- PIN_CONFIG_INPUT_DEBOUNCE
- PIN_CONFIG_INPUT_ENABLE
- PIN_CONFIG_INPUT_SCHMITT
- PIN_CONFIG_INPUT_SCHMITT_ENABLE
- PIN_CONFIG_IN_PULLUP
- PIN_CONFIG_IN_WO_PULLUP
- PIN_CONFIG_IOSTANDARD
- PIN_CONFIG_LOW_POWER_MODE
- PIN_CONFIG_MASK
- PIN_CONFIG_MAX
- PIN_CONFIG_MICROCHIP_ANALOG
- PIN_CONFIG_MICROCHIP_DIGITAL
- PIN_CONFIG_OUT
- PIN_CONFIG_OUTPUT
- PIN_CONFIG_OUTPUT_ENABLE
- PIN_CONFIG_PERSIST_STATE
- PIN_CONFIG_POWER_SOURCE
- PIN_CONFIG_SKEW_DELAY
- PIN_CONFIG_SLEEP_HARDWARE_STATE
- PIN_CONFIG_SLEW_RATE
- PIN_CONF_PACKED
- PIN_CTRL
- PIN_CTRL_BL
- PIN_CTRL_E
- PIN_CTRL_REG_1
- PIN_CTRL_REG_2
- PIN_CTRL_RS
- PIN_CTRL_RW
- PIN_CTS
- PIN_D0
- PIN_D1
- PIN_D2
- PIN_D3
- PIN_D4
- PIN_D5
- PIN_D6
- PIN_D7
- PIN_DATA0
- PIN_DATA1
- PIN_DATA2
- PIN_DATA3
- PIN_DATA4
- PIN_DATA5
- PIN_DATA6
- PIN_DATA7
- PIN_DCD
- PIN_DECL_
- PIN_DECL_1
- PIN_DECL_2
- PIN_DECL_3
- PIN_DIR
- PIN_DIRECTION_IN
- PIN_DIRECTION_MASK
- PIN_DIRECTION_OUT
- PIN_DIR_INPUT
- PIN_DIR_MASK
- PIN_DIR_OUTPUT
- PIN_DIR_SHIFT
- PIN_DSR
- PIN_DTR
- PIN_EXPRS_PTR
- PIN_EXPRS_SYM
- PIN_FIELD
- PIN_FIELD15
- PIN_FIELD16
- PIN_FIELD_BASE
- PIN_FIELD_CALC
- PIN_FUNC_1
- PIN_FUNC_2
- PIN_FUNC_3
- PIN_FUNC_4
- PIN_FUNC_MASK
- PIN_FUNC_MAX
- PIN_FUNC_SEL_1
- PIN_FUNC_SEL_2
- PIN_FUNC_SEL_3
- PIN_FUNC_SEL_4
- PIN_GLOBAL
- PIN_GLOBAL_NS
- PIN_GPIO
- PIN_GPIOMODE
- PIN_GPIOMODE_DISABLED
- PIN_GPIOMODE_ENABLED
- PIN_GPIOMODE_MASK
- PIN_GPIOMODE_SHIFT
- PIN_GROUP
- PIN_GROUP_WITH_ALT
- PIN_GROUP_WITH_OVERRIDE
- PIN_GRP
- PIN_GRP_EXTRA
- PIN_GRP_GPIO
- PIN_GRP_GPIO_2
- PIN_GRP_GPIO_3
- PIN_HIGH
- PIN_HOLDN
- PIN_HP
- PIN_HP_AMP
- PIN_HSIC_0
- PIN_HSIC_1
- PIN_I2C0_SCL
- PIN_I2C0_SDA
- PIN_IN
- PIN_INFO
- PIN_INIT
- PIN_INITP
- PIN_INPUT
- PIN_INPUT_NOPULL
- PIN_INPUT_PULLDOWN
- PIN_INPUT_PULLUP
- PIN_INPUT_SLEW
- PIN_IO_INTAPM
- PIN_IO_INTA_BAT
- PIN_IO_INTA_CLK
- PIN_IO_INTA_HIZ
- PIN_IO_INTA_OUT
- PIN_IRQ_PENDING
- PIN_LOW
- PIN_LOWEMI
- PIN_LOWEMI_DISABLED
- PIN_LOWEMI_ENABLED
- PIN_LOWEMI_MASK
- PIN_LOWEMI_SHIFT
- PIN_MAPPABLE
- PIN_MAP_CONFIGS_GROUP
- PIN_MAP_CONFIGS_GROUP_DEFAULT
- PIN_MAP_CONFIGS_GROUP_HOG
- PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT
- PIN_MAP_CONFIGS_PIN
- PIN_MAP_CONFIGS_PIN_DEFAULT
- PIN_MAP_CONFIGS_PIN_HOG
- PIN_MAP_CONFIGS_PIN_HOG_DEFAULT
- PIN_MAP_DUMMY_STATE
- PIN_MAP_MUX_GROUP
- PIN_MAP_MUX_GROUP_DEFAULT
- PIN_MAP_MUX_GROUP_HOG
- PIN_MAP_MUX_GROUP_HOG_DEFAULT
- PIN_MAP_TYPE_CONFIGS_GROUP
- PIN_MAP_TYPE_CONFIGS_PIN
- PIN_MAP_TYPE_DUMMY_STATE
- PIN_MAP_TYPE_INVALID
- PIN_MAP_TYPE_MUX_GROUP
- PIN_MASK
- PIN_MAX
- PIN_MBZ
- PIN_MODE_DUMB_12_SPI_GPIO
- PIN_MODE_DUMB_16_GPIO
- PIN_MODE_DUMB_16_SPI
- PIN_MODE_DUMB_18_GPIO
- PIN_MODE_DUMB_18_SPI
- PIN_MODE_DUMB_24
- PIN_MODE_SMART_16_SPI
- PIN_MODE_SMART_18_SPI
- PIN_MODE_SMART_8_SPI_GPIO
- PIN_MSR_MASK
- PIN_MUXING_SIZE
- PIN_MUX_BT656_ENABLE_MASK
- PIN_MUX_BT656_I2S_MODE
- PIN_MUX_CTL_REG_A
- PIN_MUX_DEFAULT
- PIN_MUX_GPIO_MODE
- PIN_MUX_I2S_ENABLE_MASK
- PIN_MUX_MCLK_EN_CTRL_MASK
- PIN_MUX_MDAT_EN_0_MASK
- PIN_MUX_MDAT_EN_1_MASK
- PIN_MUX_MDAT_EN_2_MASK
- PIN_MUX_MDAT_EN_3_MASK
- PIN_MUX_MDAT_EN_4_MASK
- PIN_MUX_MDAT_EN_5_MASK
- PIN_MUX_MDAT_EN_6_MASK
- PIN_MUX_MDAT_EN_7_MASK
- PIN_MUX_MDVAL_EN_CTRL_MASK
- PIN_MUX_MPEG_MODE_MASK
- PIN_MUX_MPEG_PAR_EN_MASK
- PIN_MUX_MPEG_SER_EN_MASK
- PIN_MUX_MPERR_EN_CTRL_MASK
- PIN_MUX_MPG_IN_MUX_MASK
- PIN_MUX_MPSYN_EN_CTRL_MASK
- PIN_MUX_SPI_MODE_MASK
- PIN_MUX_TS_OUT_PARALLEL
- PIN_MUX_TS_OUT_SERIAL
- PIN_MUX_TS_PARALLEL_IN
- PIN_MUX_TS_SERIAL_IN_MODE_0
- PIN_MUX_TS_SERIAL_IN_MODE_1
- PIN_MUX_TS_SPI_IN_MODE_0
- PIN_MUX_TS_SPI_IN_MODE_1
- PIN_NAME_LENGTH
- PIN_NO
- PIN_NOEVICT
- PIN_NONBLOCK
- PIN_NONE
- PIN_NOSEARCH
- PIN_NOT_SET
- PIN_NUM
- PIN_NUMBER
- PIN_NUM_MASK
- PIN_OE_CTRL
- PIN_OFFSET
- PIN_OFFSET_BIAS
- PIN_OFFSET_FIXED
- PIN_OFFSET_MASK
- PIN_OFF_INPUT_PULLDOWN
- PIN_OFF_INPUT_PULLUP
- PIN_OFF_NONE
- PIN_OFF_OUTPUT_HIGH
- PIN_OFF_OUTPUT_LOW
- PIN_OFF_WAKEUPENABLE
- PIN_OPT_IDE
- PIN_OTG_0
- PIN_OTG_1
- PIN_OTG_2
- PIN_OUT
- PIN_OUTPUT
- PIN_OUTPUT_HIGH
- PIN_OUTPUT_LOW
- PIN_OUTPUT_PULLDOWN
- PIN_OUTPUT_PULLUP
- PIN_PA0
- PIN_PA0__D0
- PIN_PA0__GPIO
- PIN_PA0__QSPI0_SCK
- PIN_PA0__SDMMC0_CK
- PIN_PA1
- PIN_PA10
- PIN_PA10__A21_NANDALE
- PIN_PA10__FLEXCOM2_IO4
- PIN_PA10__GPIO
- PIN_PA10__QSPI1_IO3
- PIN_PA10__SDMMC0_RSTN
- PIN_PA10__TIOB4
- PIN_PA11
- PIN_PA11__A22_NANDCLE
- PIN_PA11__GPIO
- PIN_PA11__QSPI1_CS
- PIN_PA11__SDMMC0_VDDSEL
- PIN_PA11__TCLK4
- PIN_PA12
- PIN_PA12__GPIO
- PIN_PA12__IRQ
- PIN_PA12__NRD_NANDOE
- PIN_PA12__SDMMC0_WP
- PIN_PA13
- PIN_PA13__D8
- PIN_PA13__FLEXCOM3_IO1
- PIN_PA13__GPIO
- PIN_PA13__SDMMC0_CD
- PIN_PA14
- PIN_PA14__D9
- PIN_PA14__FLEXCOM3_IO2
- PIN_PA14__GPIO
- PIN_PA14__I2SC1_MCK
- PIN_PA14__QSPI0_SCK
- PIN_PA14__SPI0_SPCK
- PIN_PA14__TK1
- PIN_PA15
- PIN_PA15__D10
- PIN_PA15__FLEXCOM3_IO0
- PIN_PA15__GPIO
- PIN_PA15__I2SC1_CK
- PIN_PA15__QSPI0_CS
- PIN_PA15__SPI0_MOSI
- PIN_PA15__TF1
- PIN_PA16
- PIN_PA16__D11
- PIN_PA16__FLEXCOM3_IO3
- PIN_PA16__GPIO
- PIN_PA16__I2SC1_WS
- PIN_PA16__QSPI0_IO0
- PIN_PA16__SPI0_MISO
- PIN_PA16__TD1
- PIN_PA17
- PIN_PA17__D12
- PIN_PA17__FLEXCOM3_IO4
- PIN_PA17__GPIO
- PIN_PA17__I2SC1_DI0
- PIN_PA17__QSPI0_IO1
- PIN_PA17__RD1
- PIN_PA17__SPI0_NPCS0
- PIN_PA18
- PIN_PA18__D13
- PIN_PA18__GPIO
- PIN_PA18__I2SC1_DO0
- PIN_PA18__QSPI0_IO2
- PIN_PA18__RK1
- PIN_PA18__SDMMC1_DAT0
- PIN_PA18__SPI0_NPCS1
- PIN_PA19
- PIN_PA19__D14
- PIN_PA19__GPIO
- PIN_PA19__QSPI0_IO3
- PIN_PA19__RF1
- PIN_PA19__SDMMC1_DAT1
- PIN_PA19__SPI0_NPCS2
- PIN_PA19__TIOA0
- PIN_PA1__D1
- PIN_PA1__GPIO
- PIN_PA1__QSPI0_CS
- PIN_PA1__SDMMC0_CMD
- PIN_PA2
- PIN_PA20
- PIN_PA20__D15
- PIN_PA20__GPIO
- PIN_PA20__SDMMC1_DAT2
- PIN_PA20__SPI0_NPCS3
- PIN_PA20__TIOB0
- PIN_PA21
- PIN_PA21__GPIO
- PIN_PA21__IRQ
- PIN_PA21__NANDRDY
- PIN_PA21__PCK2
- PIN_PA21__SDMMC1_DAT3
- PIN_PA21__TCLK0
- PIN_PA22
- PIN_PA22__D0
- PIN_PA22__FLEXCOM1_IO2
- PIN_PA22__GPIO
- PIN_PA22__QSPI0_SCK
- PIN_PA22__SDMMC1_CK
- PIN_PA22__SPI1_SPCK
- PIN_PA22__TCK
- PIN_PA23
- PIN_PA23__D1
- PIN_PA23__FLEXCOM1_IO1
- PIN_PA23__GPIO
- PIN_PA23__QSPI0_CS
- PIN_PA23__SPI1_MOSI
- PIN_PA23__TDI
- PIN_PA24
- PIN_PA24__D2
- PIN_PA24__FLEXCOM1_IO0
- PIN_PA24__GPIO
- PIN_PA24__QSPI0_IO0
- PIN_PA24__SPI1_MISO
- PIN_PA24__TDO
- PIN_PA25
- PIN_PA25__D3
- PIN_PA25__FLEXCOM1_IO3
- PIN_PA25__GPIO
- PIN_PA25__QSPI0_IO1
- PIN_PA25__SPI1_NPCS0
- PIN_PA25__TMS
- PIN_PA26
- PIN_PA26__D4
- PIN_PA26__FLEXCOM1_IO4
- PIN_PA26__GPIO
- PIN_PA26__NTRST
- PIN_PA26__QSPI0_IO2
- PIN_PA26__SPI1_NPCS1
- PIN_PA27
- PIN_PA27__D5
- PIN_PA27__GPIO
- PIN_PA27__QSPI0_IO3
- PIN_PA27__SDMMC1_RSTN
- PIN_PA27__SPI0_NPCS2
- PIN_PA27__SPI1_NPCS2
- PIN_PA27__TIOA1
- PIN_PA28
- PIN_PA28__CLASSD_L0
- PIN_PA28__D6
- PIN_PA28__GPIO
- PIN_PA28__SDMMC1_CMD
- PIN_PA28__SPI0_NPCS3
- PIN_PA28__SPI1_NPCS3
- PIN_PA28__TIOB1
- PIN_PA29
- PIN_PA29__CLASSD_L1
- PIN_PA29__D7
- PIN_PA29__GPIO
- PIN_PA29__SDMMC1_WP
- PIN_PA29__SPI0_NPCS1
- PIN_PA29__TCLK1
- PIN_PA2__D2
- PIN_PA2__GPIO
- PIN_PA2__QSPI0_IO0
- PIN_PA2__SDMMC0_DAT0
- PIN_PA3
- PIN_PA30
- PIN_PA30__CLASSD_L2
- PIN_PA30__GPIO
- PIN_PA30__NWE_NANDWE
- PIN_PA30__PWMH0
- PIN_PA30__SDMMC1_CD
- PIN_PA30__SPI0_NPCS0
- PIN_PA31
- PIN_PA31__CLASSD_L3
- PIN_PA31__GPIO
- PIN_PA31__NCS3
- PIN_PA31__PWML0
- PIN_PA31__SPI0_MISO
- PIN_PA3__D3
- PIN_PA3__GPIO
- PIN_PA3__QSPI0_IO1
- PIN_PA3__SDMMC0_DAT1
- PIN_PA4
- PIN_PA4__D4
- PIN_PA4__GPIO
- PIN_PA4__QSPI0_IO2
- PIN_PA4__SDMMC0_DAT2
- PIN_PA5
- PIN_PA5__D5
- PIN_PA5__GPIO
- PIN_PA5__QSPI0_IO3
- PIN_PA5__SDMMC0_DAT3
- PIN_PA6
- PIN_PA6__D6
- PIN_PA6__FLEXCOM2_IO0
- PIN_PA6__GPIO
- PIN_PA6__QSPI1_SCK
- PIN_PA6__SDMMC0_DAT4
- PIN_PA6__TIOA5
- PIN_PA7
- PIN_PA7__D7
- PIN_PA7__FLEXCOM2_IO1
- PIN_PA7__GPIO
- PIN_PA7__QSPI1_IO0
- PIN_PA7__SDMMC0_DAT5
- PIN_PA7__TIOB5
- PIN_PA8
- PIN_PA8__FLEXCOM2_IO2
- PIN_PA8__GPIO
- PIN_PA8__NWE_NANDWE
- PIN_PA8__QSPI1_IO1
- PIN_PA8__SDMMC0_DAT6
- PIN_PA8__TCLK5
- PIN_PA9
- PIN_PA9__FLEXCOM2_IO3
- PIN_PA9__GPIO
- PIN_PA9__NCS3
- PIN_PA9__QSPI1_IO2
- PIN_PA9__SDMMC0_DAT7
- PIN_PA9__TIOA4
- PIN_PB0
- PIN_PB0__A21_NANDALE
- PIN_PB0__GPIO
- PIN_PB0__PWMH1
- PIN_PB0__SPI0_MOSI
- PIN_PB1
- PIN_PB10
- PIN_PB10__D15
- PIN_PB10__GPIO
- PIN_PB10__GRX2
- PIN_PB10__PWMEXTRG1
- PIN_PB10__QSPI1_IO3
- PIN_PB10__TIOB3
- PIN_PB11
- PIN_PB11__A0_NBS0
- PIN_PB11__GPIO
- PIN_PB11__GRX3
- PIN_PB11__LCDDAT0
- PIN_PB11__PDMIC_DAT
- PIN_PB11__URXD3
- PIN_PB12
- PIN_PB12__A1
- PIN_PB12__GPIO
- PIN_PB12__GTX2
- PIN_PB12__LCDDAT1
- PIN_PB12__PDMIC_CLK
- PIN_PB12__UTXD3
- PIN_PB13
- PIN_PB13__A2
- PIN_PB13__GPIO
- PIN_PB13__GTX3
- PIN_PB13__LCDDAT2
- PIN_PB13__PCK1
- PIN_PB14
- PIN_PB14__A3
- PIN_PB14__GPIO
- PIN_PB14__GTXCK
- PIN_PB14__I2SC1_MCK
- PIN_PB14__LCDDAT3
- PIN_PB14__QSPI1_SCK
- PIN_PB14__TK1
- PIN_PB15
- PIN_PB15__A4
- PIN_PB15__GPIO
- PIN_PB15__GTXEN
- PIN_PB15__I2SC1_CK
- PIN_PB15__LCDDAT4
- PIN_PB15__QSPI1_CS
- PIN_PB15__TF1
- PIN_PB16
- PIN_PB16__A5
- PIN_PB16__GPIO
- PIN_PB16__GRXDV
- PIN_PB16__I2SC1_WS
- PIN_PB16__LCDDAT5
- PIN_PB16__QSPI1_IO0
- PIN_PB16__TD1
- PIN_PB17
- PIN_PB17__A6
- PIN_PB17__GPIO
- PIN_PB17__GRXER
- PIN_PB17__I2SC1_DI0
- PIN_PB17__LCDDAT6
- PIN_PB17__QSPI1_IO1
- PIN_PB17__RD1
- PIN_PB18
- PIN_PB18__A7
- PIN_PB18__GPIO
- PIN_PB18__GRX0
- PIN_PB18__I2SC1_DO0
- PIN_PB18__LCDDAT7
- PIN_PB18__QSPI1_IO2
- PIN_PB18__RK1
- PIN_PB19
- PIN_PB19__A8
- PIN_PB19__GPIO
- PIN_PB19__GRX1
- PIN_PB19__LCDDAT8
- PIN_PB19__QSPI1_IO3
- PIN_PB19__RF1
- PIN_PB19__TIOA3
- PIN_PB1__A22_NANDCLE
- PIN_PB1__CLASSD_R0
- PIN_PB1__GPIO
- PIN_PB1__PWML1
- PIN_PB1__SPI0_SPCK
- PIN_PB2
- PIN_PB20
- PIN_PB20__A9
- PIN_PB20__GPIO
- PIN_PB20__GTX0
- PIN_PB20__LCDDAT9
- PIN_PB20__PCK1
- PIN_PB20__TIOB3
- PIN_PB20__TK0
- PIN_PB21
- PIN_PB21__A10
- PIN_PB21__FLEXCOM3_IO2
- PIN_PB21__GPIO
- PIN_PB21__GTX1
- PIN_PB21__LCDDAT10
- PIN_PB21__TCLK3
- PIN_PB21__TF0
- PIN_PB22
- PIN_PB22__A11
- PIN_PB22__FLEXCOM3_IO1
- PIN_PB22__GMDC
- PIN_PB22__GPIO
- PIN_PB22__LCDDAT11
- PIN_PB22__TD0
- PIN_PB22__TIOA2
- PIN_PB23
- PIN_PB23__A12
- PIN_PB23__FLEXCOM3_IO0
- PIN_PB23__GMDIO
- PIN_PB23__GPIO
- PIN_PB23__LCDDAT12
- PIN_PB23__RD0
- PIN_PB23__TIOB2
- PIN_PB24
- PIN_PB24__A13
- PIN_PB24__FLEXCOM3_IO3
- PIN_PB24__GPIO
- PIN_PB24__ISC_D10
- PIN_PB24__LCDDAT13
- PIN_PB24__RK0
- PIN_PB24__TCLK2
- PIN_PB25
- PIN_PB25__A14
- PIN_PB25__FLEXCOM3_IO4
- PIN_PB25__GPIO
- PIN_PB25__ISC_D11
- PIN_PB25__LCDDAT14
- PIN_PB25__RF0
- PIN_PB26
- PIN_PB26__A15
- PIN_PB26__GPIO
- PIN_PB26__ISC_D0
- PIN_PB26__LCDDAT15
- PIN_PB26__PDMIC_DAT
- PIN_PB26__URXD0
- PIN_PB27
- PIN_PB27__A16
- PIN_PB27__GPIO
- PIN_PB27__ISC_D1
- PIN_PB27__LCDDAT16
- PIN_PB27__PDMIC_CLK
- PIN_PB27__UTXD0
- PIN_PB28
- PIN_PB28__A17
- PIN_PB28__FLEXCOM0_IO0
- PIN_PB28__GPIO
- PIN_PB28__ISC_D2
- PIN_PB28__LCDDAT17
- PIN_PB28__TIOA5
- PIN_PB29
- PIN_PB29__A18
- PIN_PB29__FLEXCOM0_IO1
- PIN_PB29__GPIO
- PIN_PB29__ISC_D3
- PIN_PB29__LCDDAT18
- PIN_PB29__TIOB5
- PIN_PB2__CLASSD_R1
- PIN_PB2__GPIO
- PIN_PB2__NRD_NANDOE
- PIN_PB2__PWMFI0
- PIN_PB3
- PIN_PB30
- PIN_PB30__A19
- PIN_PB30__FLEXCOM0_IO2
- PIN_PB30__GPIO
- PIN_PB30__ISC_D4
- PIN_PB30__LCDDAT19
- PIN_PB30__TCLK5
- PIN_PB31
- PIN_PB31__A20
- PIN_PB31__FLEXCOM0_IO3
- PIN_PB31__GPIO
- PIN_PB31__ISC_D5
- PIN_PB31__LCDDAT20
- PIN_PB31__TWD0
- PIN_PB3__CLASSD_R2
- PIN_PB3__D8
- PIN_PB3__GPIO
- PIN_PB3__IRQ
- PIN_PB3__PWMEXTRG0
- PIN_PB3__URXD4
- PIN_PB4
- PIN_PB4__CLASSD_R3
- PIN_PB4__D9
- PIN_PB4__FIQ
- PIN_PB4__GPIO
- PIN_PB4__UTXD4
- PIN_PB5
- PIN_PB5__D10
- PIN_PB5__GPIO
- PIN_PB5__GTSUCOMP
- PIN_PB5__PWMH2
- PIN_PB5__QSPI1_SCK
- PIN_PB5__TCLK2
- PIN_PB6
- PIN_PB6__D11
- PIN_PB6__GPIO
- PIN_PB6__GTXER
- PIN_PB6__PWML2
- PIN_PB6__QSPI1_CS
- PIN_PB6__TIOA2
- PIN_PB7
- PIN_PB7__D12
- PIN_PB7__GPIO
- PIN_PB7__GRXCK
- PIN_PB7__PWMH3
- PIN_PB7__QSPI1_IO0
- PIN_PB7__TIOB2
- PIN_PB8
- PIN_PB8__D13
- PIN_PB8__GCRS
- PIN_PB8__GPIO
- PIN_PB8__PWML3
- PIN_PB8__QSPI1_IO1
- PIN_PB8__TCLK3
- PIN_PB9
- PIN_PB9__D14
- PIN_PB9__GCOL
- PIN_PB9__GPIO
- PIN_PB9__PWMFI1
- PIN_PB9__QSPI1_IO2
- PIN_PB9__TIOA3
- PIN_PC0
- PIN_PC0__A23
- PIN_PC0__FLEXCOM0_IO4
- PIN_PC0__GPIO
- PIN_PC0__ISC_D6
- PIN_PC0__LCDDAT21
- PIN_PC0__TWCK0
- PIN_PC1
- PIN_PC10
- PIN_PC10__CANTX0
- PIN_PC10__GPIO
- PIN_PC10__GTXCK
- PIN_PC10__ISC_D1
- PIN_PC10__LCDDAT2
- PIN_PC10__TIOB4
- PIN_PC11
- PIN_PC11__A0_NBS0
- PIN_PC11__CANRX0
- PIN_PC11__GPIO
- PIN_PC11__GTXEN
- PIN_PC11__ISC_D2
- PIN_PC11__LCDDAT3
- PIN_PC11__TCLK4
- PIN_PC12
- PIN_PC12__A1
- PIN_PC12__GPIO
- PIN_PC12__GRXDV
- PIN_PC12__ISC_D3
- PIN_PC12__LCDDAT4
- PIN_PC12__TK0
- PIN_PC12__URXD3
- PIN_PC13
- PIN_PC13__A2
- PIN_PC13__GPIO
- PIN_PC13__GRXER
- PIN_PC13__ISC_D4
- PIN_PC13__LCDDAT5
- PIN_PC13__TF0
- PIN_PC13__UTXD3
- PIN_PC14
- PIN_PC14__A3
- PIN_PC14__GPIO
- PIN_PC14__GRX0
- PIN_PC14__ISC_D5
- PIN_PC14__LCDDAT6
- PIN_PC14__TD0
- PIN_PC15
- PIN_PC15__A4
- PIN_PC15__GPIO
- PIN_PC15__GRX1
- PIN_PC15__ISC_D6
- PIN_PC15__LCDDAT7
- PIN_PC15__RD0
- PIN_PC16
- PIN_PC16__A5
- PIN_PC16__GPIO
- PIN_PC16__GTX0
- PIN_PC16__ISC_D7
- PIN_PC16__LCDDAT10
- PIN_PC16__RK0
- PIN_PC17
- PIN_PC17__A6
- PIN_PC17__GPIO
- PIN_PC17__GTX1
- PIN_PC17__ISC_D8
- PIN_PC17__LCDDAT11
- PIN_PC17__RF0
- PIN_PC18
- PIN_PC18__A7
- PIN_PC18__FLEXCOM3_IO2
- PIN_PC18__GMDC
- PIN_PC18__GPIO
- PIN_PC18__ISC_D9
- PIN_PC18__LCDDAT12
- PIN_PC19
- PIN_PC19__A8
- PIN_PC19__FLEXCOM3_IO1
- PIN_PC19__GMDIO
- PIN_PC19__GPIO
- PIN_PC19__ISC_D10
- PIN_PC19__LCDDAT13
- PIN_PC1__A24
- PIN_PC1__CANTX0
- PIN_PC1__GPIO
- PIN_PC1__I2SC0_CK
- PIN_PC1__ISC_D7
- PIN_PC1__LCDDAT22
- PIN_PC1__SPI1_SPCK
- PIN_PC2
- PIN_PC20
- PIN_PC20__A9
- PIN_PC20__FLEXCOM3_IO0
- PIN_PC20__GPIO
- PIN_PC20__GRXCK
- PIN_PC20__ISC_D11
- PIN_PC20__LCDDAT14
- PIN_PC21
- PIN_PC21__A10
- PIN_PC21__FLEXCOM3_IO3
- PIN_PC21__GPIO
- PIN_PC21__GTXER
- PIN_PC21__ISC_PCK
- PIN_PC21__LCDDAT15
- PIN_PC22
- PIN_PC22__A11
- PIN_PC22__FLEXCOM3_IO4
- PIN_PC22__GCRS
- PIN_PC22__GPIO
- PIN_PC22__ISC_VSYNC
- PIN_PC22__LCDDAT18
- PIN_PC23
- PIN_PC23__A12
- PIN_PC23__GCOL
- PIN_PC23__GPIO
- PIN_PC23__ISC_HSYNC
- PIN_PC23__LCDDAT19
- PIN_PC24
- PIN_PC24__A13
- PIN_PC24__GPIO
- PIN_PC24__GRX2
- PIN_PC24__ISC_MCK
- PIN_PC24__LCDDAT20
- PIN_PC25
- PIN_PC25__A14
- PIN_PC25__GPIO
- PIN_PC25__GRX3
- PIN_PC25__ISC_FIELD
- PIN_PC25__LCDDAT21
- PIN_PC26
- PIN_PC26__A15
- PIN_PC26__CANTX1
- PIN_PC26__GPIO
- PIN_PC26__GTX2
- PIN_PC26__LCDDAT22
- PIN_PC27
- PIN_PC27__A16
- PIN_PC27__CANRX1
- PIN_PC27__GPIO
- PIN_PC27__GTX3
- PIN_PC27__LCDDAT23
- PIN_PC27__PCK1
- PIN_PC27__TWD0
- PIN_PC28
- PIN_PC28__A17
- PIN_PC28__FLEXCOM4_IO0
- PIN_PC28__GPIO
- PIN_PC28__LCDPWM
- PIN_PC28__PCK2
- PIN_PC28__TWCK0
- PIN_PC29
- PIN_PC29__A18
- PIN_PC29__FLEXCOM4_IO1
- PIN_PC29__GPIO
- PIN_PC29__LCDDISP
- PIN_PC2__A25
- PIN_PC2__CANRX0
- PIN_PC2__GPIO
- PIN_PC2__I2SC0_MCK
- PIN_PC2__ISC_D8
- PIN_PC2__LCDDAT23
- PIN_PC2__SPI1_MOSI
- PIN_PC3
- PIN_PC30
- PIN_PC30__A19
- PIN_PC30__FLEXCOM4_IO2
- PIN_PC30__GPIO
- PIN_PC30__LCDVSYNC
- PIN_PC31
- PIN_PC31__A20
- PIN_PC31__FLEXCOM4_IO3
- PIN_PC31__GPIO
- PIN_PC31__LCDHSYNC
- PIN_PC31__URXD3
- PIN_PC3__GPIO
- PIN_PC3__I2SC0_WS
- PIN_PC3__ISC_D9
- PIN_PC3__LCDPWM
- PIN_PC3__NWAIT
- PIN_PC3__SPI1_MISO
- PIN_PC3__TIOA1
- PIN_PC4
- PIN_PC4__GPIO
- PIN_PC4__I2SC0_DI0
- PIN_PC4__ISC_PCK
- PIN_PC4__LCDDISP
- PIN_PC4__NWR1_NBS1
- PIN_PC4__SPI1_NPCS0
- PIN_PC4__TIOB1
- PIN_PC5
- PIN_PC5__GPIO
- PIN_PC5__I2SC0_DO0
- PIN_PC5__ISC_VSYNC
- PIN_PC5__LCDVSYNC
- PIN_PC5__NCS0
- PIN_PC5__SPI1_NPCS1
- PIN_PC5__TCLK1
- PIN_PC6
- PIN_PC6__GPIO
- PIN_PC6__ISC_HSYNC
- PIN_PC6__LCDHSYNC
- PIN_PC6__NCS1
- PIN_PC6__SPI1_NPCS2
- PIN_PC6__TWD1
- PIN_PC7
- PIN_PC7__GPIO
- PIN_PC7__ISC_MCK
- PIN_PC7__LCDPCK
- PIN_PC7__NCS2
- PIN_PC7__SPI1_NPCS3
- PIN_PC7__TWCK1
- PIN_PC7__URXD1
- PIN_PC8
- PIN_PC8__FIQ
- PIN_PC8__GPIO
- PIN_PC8__ISC_FIELD
- PIN_PC8__LCDDEN
- PIN_PC8__NANDRDY
- PIN_PC8__PCK0
- PIN_PC8__UTXD1
- PIN_PC9
- PIN_PC9__FIQ
- PIN_PC9__GPIO
- PIN_PC9__GTSUCOMP
- PIN_PC9__ISC_D0
- PIN_PC9__TIOA4
- PIN_PCIE_0
- PIN_PCIE_1
- PIN_PCIE_2
- PIN_PCIE_3
- PIN_PCIE_4
- PIN_PD0
- PIN_PD0__A23
- PIN_PD0__FLEXCOM4_IO4
- PIN_PD0__GPIO
- PIN_PD0__GTSUCOMP
- PIN_PD0__LCDPCK
- PIN_PD0__UTXD3
- PIN_PD1
- PIN_PD10
- PIN_PD10__GPIO
- PIN_PD10__GTXEN
- PIN_PD10__ISC_D3
- PIN_PD10__NTRST
- PIN_PD10__UTMI_HDIS
- PIN_PD11
- PIN_PD11__GPIO
- PIN_PD11__GRXDV
- PIN_PD11__ISC_D4
- PIN_PD11__ISC_MCK
- PIN_PD11__PCK2
- PIN_PD11__TIOA1
- PIN_PD11__UTMI_LS0
- PIN_PD12
- PIN_PD12__FLEXCOM4_IO0
- PIN_PD12__GPIO
- PIN_PD12__GRXER
- PIN_PD12__ISC_D4
- PIN_PD12__ISC_D5
- PIN_PD12__TIOB1
- PIN_PD12__UTMI_LS1
- PIN_PD13
- PIN_PD13__FLEXCOM4_IO1
- PIN_PD13__GPIO
- PIN_PD13__GRX0
- PIN_PD13__ISC_D5
- PIN_PD13__ISC_D6
- PIN_PD13__TCLK1
- PIN_PD13__UTMI_CDRPCSEL0
- PIN_PD14
- PIN_PD14__FLEXCOM4_IO2
- PIN_PD14__GPIO
- PIN_PD14__GRX1
- PIN_PD14__ISC_D6
- PIN_PD14__ISC_D7
- PIN_PD14__TCK
- PIN_PD14__UTMI_CDRPCSEL1
- PIN_PD15
- PIN_PD15__FLEXCOM4_IO3
- PIN_PD15__GPIO
- PIN_PD15__GTX0
- PIN_PD15__ISC_D7
- PIN_PD15__ISC_PCK
- PIN_PD15__TDI
- PIN_PD15__UTMI_CDRCPDIVEN
- PIN_PD16
- PIN_PD16__FLEXCOM4_IO4
- PIN_PD16__GPIO
- PIN_PD16__GTX1
- PIN_PD16__ISC_D8
- PIN_PD16__ISC_VSYNC
- PIN_PD16__TDO
- PIN_PD16__UTMI_CDRBISTEN
- PIN_PD17
- PIN_PD17__GMDC
- PIN_PD17__GPIO
- PIN_PD17__ISC_D9
- PIN_PD17__ISC_HSYNC
- PIN_PD17__TMS
- PIN_PD17__UTMI_CDRCPSELDIV
- PIN_PD18
- PIN_PD18__GMDIO
- PIN_PD18__GPIO
- PIN_PD18__ISC_D10
- PIN_PD18__ISC_FIELD
- PIN_PD18__NTRST
- PIN_PD19
- PIN_PD19__GPIO
- PIN_PD19__I2SC0_CK
- PIN_PD19__ISC_D11
- PIN_PD19__PCK0
- PIN_PD19__TWD1
- PIN_PD19__URXD2
- PIN_PD1__A24
- PIN_PD1__GPIO
- PIN_PD1__GRXCK
- PIN_PD1__LCDDEN
- PIN_PD2
- PIN_PD20
- PIN_PD20__GPIO
- PIN_PD20__I2SC0_MCK
- PIN_PD20__ISC_PCK
- PIN_PD20__TIOA2
- PIN_PD20__TWCK1
- PIN_PD20__UTXD2
- PIN_PD21
- PIN_PD21__FLEXCOM4_IO0
- PIN_PD21__GPIO
- PIN_PD21__I2SC0_WS
- PIN_PD21__ISC_VSYNC
- PIN_PD21__TIOB2
- PIN_PD21__TWD0
- PIN_PD22
- PIN_PD22__FLEXCOM4_IO1
- PIN_PD22__GPIO
- PIN_PD22__I2SC0_DI0
- PIN_PD22__ISC_HSYNC
- PIN_PD22__TCLK2
- PIN_PD22__TWCK0
- PIN_PD23
- PIN_PD23__FLEXCOM4_IO2
- PIN_PD23__GPIO
- PIN_PD23__I2SC0_DO0
- PIN_PD23__ISC_FIELD
- PIN_PD23__URXD2
- PIN_PD24
- PIN_PD24__FLEXCOM4_IO3
- PIN_PD24__GPIO
- PIN_PD24__UTXD2
- PIN_PD25
- PIN_PD25__FLEXCOM4_IO4
- PIN_PD25__GPIO
- PIN_PD25__SPI1_SPCK
- PIN_PD26
- PIN_PD26__FLEXCOM2_IO0
- PIN_PD26__GPIO
- PIN_PD26__SPI1_MOSI
- PIN_PD27
- PIN_PD27__FLEXCOM2_IO1
- PIN_PD27__GPIO
- PIN_PD27__SPI1_MISO
- PIN_PD27__TCK
- PIN_PD28
- PIN_PD28__FLEXCOM2_IO2
- PIN_PD28__GPIO
- PIN_PD28__SPI1_NPCS0
- PIN_PD28__TCI
- PIN_PD29
- PIN_PD29__FLEXCOM2_IO3
- PIN_PD29__GPIO
- PIN_PD29__SPI1_NPCS1
- PIN_PD29__TDO
- PIN_PD29__TIOA3
- PIN_PD29__TWD0
- PIN_PD2__A25
- PIN_PD2__GPIO
- PIN_PD2__GTXER
- PIN_PD2__ISC_MCK
- PIN_PD2__URXD1
- PIN_PD3
- PIN_PD30
- PIN_PD30__FLEXCOM2_IO4
- PIN_PD30__GPIO
- PIN_PD30__SPI1_NPCS2
- PIN_PD30__TIOB3
- PIN_PD30__TMS
- PIN_PD30__TWCK0
- PIN_PD31
- PIN_PD31__ADTRG
- PIN_PD31__GPIO
- PIN_PD31__IRQ
- PIN_PD31__NTRST
- PIN_PD31__PCK0
- PIN_PD31__TCLK3
- PIN_PD3__FIQ
- PIN_PD3__GCRS
- PIN_PD3__GPIO
- PIN_PD3__ISC_D11
- PIN_PD3__NWAIT
- PIN_PD3__UTXD1
- PIN_PD4
- PIN_PD4__GCOL
- PIN_PD4__GPIO
- PIN_PD4__ISC_D10
- PIN_PD4__NCS0
- PIN_PD4__TWD1
- PIN_PD4__URXD2
- PIN_PD5
- PIN_PD5__GPIO
- PIN_PD5__GRX2
- PIN_PD5__ISC_D9
- PIN_PD5__NCS1
- PIN_PD5__TWCK1
- PIN_PD5__UTXD2
- PIN_PD6
- PIN_PD6__GPIO
- PIN_PD6__GRX3
- PIN_PD6__ISC_D8
- PIN_PD6__NCS2
- PIN_PD6__PCK1
- PIN_PD6__TCK
- PIN_PD7
- PIN_PD7__GPIO
- PIN_PD7__GTX2
- PIN_PD7__ISC_D0
- PIN_PD7__NWR1_NBS1
- PIN_PD7__TDI
- PIN_PD7__UTMI_RXVAL
- PIN_PD8
- PIN_PD8__GPIO
- PIN_PD8__GTX3
- PIN_PD8__ISC_D1
- PIN_PD8__NANDRDY
- PIN_PD8__TDO
- PIN_PD8__UTMI_RXERR
- PIN_PD9
- PIN_PD9__GPIO
- PIN_PD9__GTXCK
- PIN_PD9__ISC_D2
- PIN_PD9__TMS
- PIN_PD9__UTMI_RXACT
- PIN_PINGROUP_ENTRY_Y
- PIN_PULL
- PIN_PULLDOWN
- PIN_PULLUP
- PIN_PULL_DOWN
- PIN_PULL_MASK
- PIN_PULL_NONE
- PIN_PULL_SHIFT
- PIN_PULL_UP
- PIN_RI
- PIN_RTS
- PIN_RXD
- PIN_SATA_0
- PIN_SCK
- PIN_SELECP
- PIN_SELECT1
- PIN_SLEEPMODE
- PIN_SLEEPMODE_DISABLED
- PIN_SLEEPMODE_ENABLED
- PIN_SLEEPMODE_MASK
- PIN_SLEEPMODE_SHIFT
- PIN_SLPM
- PIN_SLPM_ALTFUNC
- PIN_SLPM_DIR
- PIN_SLPM_DIR_INPUT
- PIN_SLPM_DIR_MASK
- PIN_SLPM_DIR_OUTPUT
- PIN_SLPM_DIR_SHIFT
- PIN_SLPM_GPIO
- PIN_SLPM_INPUT_NOPULL
- PIN_SLPM_INPUT_PULLDOWN
- PIN_SLPM_INPUT_PULLUP
- PIN_SLPM_MAKE_INPUT
- PIN_SLPM_MASK
- PIN_SLPM_NOCHANGE
- PIN_SLPM_OUTPUT_HIGH
- PIN_SLPM_OUTPUT_LOW
- PIN_SLPM_PDIS
- PIN_SLPM_PDIS_DISABLED
- PIN_SLPM_PDIS_ENABLED
- PIN_SLPM_PDIS_MASK
- PIN_SLPM_PDIS_NO_CHANGE
- PIN_SLPM_PDIS_SHIFT
- PIN_SLPM_PULL
- PIN_SLPM_PULL_DOWN
- PIN_SLPM_PULL_MASK
- PIN_SLPM_PULL_NONE
- PIN_SLPM_PULL_SHIFT
- PIN_SLPM_PULL_UP
- PIN_SLPM_SHIFT
- PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP
- PIN_SLPM_VAL
- PIN_SLPM_VAL_HIGH
- PIN_SLPM_VAL_LOW
- PIN_SLPM_VAL_MASK
- PIN_SLPM_VAL_SHIFT
- PIN_SLPM_WAKEUP_DISABLE
- PIN_SLPM_WAKEUP_ENABLE
- PIN_SPD_CTRL
- PIN_SPD_CTRL2
- PIN_STATE_DEFAULT
- PIN_STATE_MAX
- PIN_STROBE
- PIN_STS_OFF
- PIN_SYM
- PIN_TDM_OUT_OFF
- PIN_TDM_OUT_ON
- PIN_TXD
- PIN_ULPI_0
- PIN_UPDATE
- PIN_USB1_DM
- PIN_USB1_DP
- PIN_USBOE
- PIN_USBTN
- PIN_USBTP
- PIN_USER
- PIN_VAL
- PIN_VAL_HIGH
- PIN_VAL_LOW
- PIN_VAL_MASK
- PIN_VAL_SHIFT
- PIN_VREF100
- PIN_VREF50
- PIN_VREF80
- PIN_VREFGRD
- PIN_VREFHIZ
- PIN_WPN
- PIN_ZONE_4G
- PIO
- PIO1616L_DI_REG
- PIO1616L_DO_REG
- PIOBU_BASE
- PIOBU_BMPR
- PIOBU_DET_OFFSET
- PIOBU_DIRECTION
- PIOBU_HIGH
- PIOBU_IN
- PIOBU_LOW
- PIOBU_NMPR
- PIOBU_NUM
- PIOBU_OUT
- PIOBU_PDS
- PIOBU_REG_SIZE
- PIOBU_SOD
- PIOBU_WKPR
- PIOCMODE
- PIOCPARM_MASK
- PIOCPLGRPPERR_F
- PIOCPLGRPPERR_S
- PIOCPLGRPPERR_V
- PIOCPLPERR_F
- PIOCPLPERR_S
- PIOCPLPERR_V
- PIODATA_ENDIAN_SHIFT
- PIOEN0
- PIOEN1
- PIOError
- PIOP_TO_GMMIO
- PIOParityError
- PIOR
- PIOREQGRPPERR_F
- PIOREQGRPPERR_S
- PIOREQGRPPERR_V
- PIOREQPERR_F
- PIOREQPERR_S
- PIOREQPERR_V
- PIORSTMODE_F
- PIORSTMODE_S
- PIORSTMODE_V
- PIORST_F
- PIORST_S
- PIORST_V
- PIOTAGPERR_F
- PIOTAGPERR_S
- PIOTAGPERR_V
- PIOTYPE_ADDR_ERR
- PIOTYPE_CMD_ERR
- PIOTYPE_EXCHANGE
- PIOTYPE_PROT_ERR
- PIOTYPE_READ
- PIOTYPE_UNDEFINED
- PIOTYPE_UNKNOWN
- PIOTYPE_WRITE
- PIO_ABCDSR1
- PIO_ABCDSR2
- PIO_ABSR
- PIO_ADDR_CONTEXT_MASK
- PIO_ADDR_CONTEXT_SHIFT
- PIO_ADDR_LS
- PIO_ADDR_MS
- PIO_AIMDR
- PIO_AIMER
- PIO_AIMMR
- PIO_ARB_CTL
- PIO_ARB_CTL_CTL
- PIO_ARB_DBG_VEC
- PIO_ARB_DBG_VEC_VEC
- PIO_ASR
- PIO_BASE_ADDR
- PIO_BLOCK_MASK
- PIO_BLOCK_QWS
- PIO_BLOCK_SIZE
- PIO_BSR
- PIO_BUFS
- PIO_BUFS_SOP
- PIO_CMAP
- PIO_CMASK
- PIO_CODR
- PIO_COMPLETION_STATUS_CA
- PIO_COMPLETION_STATUS_CRS
- PIO_COMPLETION_STATUS_MASK
- PIO_COMPLETION_STATUS_OK
- PIO_COMPLETION_STATUS_SHIFT
- PIO_COMPLETION_STATUS_UR
- PIO_CRED
- PIO_CTRL
- PIO_CTRL_ADDR_WIN_DISABLE
- PIO_CTRL_TYPE_MASK
- PIO_DATAOUT_1B
- PIO_DATAOUT_4B
- PIO_DATA_IN_PROTO
- PIO_DATA_OUT_PROTO
- PIO_DBG_SEL
- PIO_DBG_SEL_SEL
- PIO_DI_RDY
- PIO_ELSR
- PIO_ENABLE_SHIFT
- PIO_ERR_INT
- PIO_ESR
- PIO_FELLSR
- PIO_FIFO
- PIO_FLAG
- PIO_FONT
- PIO_FONTRESET
- PIO_FONTX
- PIO_FRLHSR
- PIO_IDR
- PIO_IER
- PIO_IFDR
- PIO_IFER
- PIO_IFSCDR
- PIO_IFSCER
- PIO_IFSCSR
- PIO_IFSR
- PIO_IMASK0
- PIO_IMASK1
- PIO_IMR
- PIO_INDIRECT_SIZE
- PIO_ISR
- PIO_ISRM
- PIO_LDSV
- PIO_LSR
- PIO_MASK
- PIO_MAX_BLOCKS
- PIO_MDDR
- PIO_MDER
- PIO_MDSR
- PIO_NON_POSTED_REQ
- PIO_ODR
- PIO_ODSR
- PIO_OER
- PIO_OFFSET
- PIO_OSR
- PIO_OUT_TIMEOUT
- PIO_OVERRUN
- PIO_OWDR
- PIO_OWER
- PIO_OWSR
- PIO_PDR
- PIO_PDSR
- PIO_PER
- PIO_PIO_LDGIM
- PIO_POW_MOD_SEL_REG
- PIO_PPDDR
- PIO_PPDER
- PIO_PPDSR
- PIO_PSR
- PIO_PUDR
- PIO_PUER
- PIO_PUSR
- PIO_RD_DATA
- PIO_REG
- PIO_REHLSR
- PIO_RESERVED
- PIO_SCDR
- PIO_SCDR_DIV
- PIO_SCHMITT
- PIO_SCRNMAP
- PIO_SODR
- PIO_START
- PIO_STAT
- PIO_STATUS
- PIO_THRESHOLD
- PIO_THRESHOLD_CEILING
- PIO_TIMEOUT_MS
- PIO_TRAIN_VEC
- PIO_TRAIN_VEC_VEC
- PIO_UNIMAP
- PIO_UNIMAPCLR
- PIO_UNISCRNMAP
- PIO_VADDR
- PIO_WAIT_BATCH_SIZE
- PIO_WR_DATA
- PIO_WR_DATA_STRB
- PIO_XFER_CFG
- PIO_XFER_CTRL
- PIO_XFER_ERR_IRQ
- PIO_XFER_STATUS
- PIP
- PIPE
- PIPE0BUF
- PIPE0_ARBITRATION_CONTROL3
- PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE0_DMIF_BUFFER_CONTROL
- PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE0_LATENCY_CONTROL
- PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK
- PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT
- PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK
- PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT
- PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK
- PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT
- PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK
- PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT
- PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK
- PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT
- PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK
- PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT
- PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK
- PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT
- PIPE1CTR
- PIPE1TRE
- PIPE1TRN
- PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK
- PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT
- PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK
- PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT
- PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK
- PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT
- PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK
- PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT
- PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK
- PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT
- PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK
- PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT
- PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK
- PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT
- PIPE1_READ_REG
- PIPE2CTR
- PIPE2TRE
- PIPE2TRN
- PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK
- PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT
- PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK
- PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT
- PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK
- PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT
- PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK
- PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT
- PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK
- PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT
- PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK
- PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT
- PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK
- PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT
- PIPE3CTR
- PIPE3TRE
- PIPE3TRN
- PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE3_MODE_PCIE
- PIPE3_MODE_SATA
- PIPE3_MODE_USBSS
- PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK
- PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT
- PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK
- PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT
- PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK
- PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT
- PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK
- PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT
- PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK
- PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT
- PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK
- PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT
- PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK
- PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT
- PIPE3_PHYSTATUS_SW
- PIPE3_PHY_PWRCTL_CLK_CMD_MASK
- PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT
- PIPE3_PHY_PWRCTL_CLK_FREQ_MASK
- PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT
- PIPE3_PHY_RX_ANA_PROGRAMMABILITY
- PIPE3_PHY_RX_DIGITAL_MODES
- PIPE3_PHY_RX_DLL
- PIPE3_PHY_RX_EQUALIZER
- PIPE3_PHY_RX_POWERON
- PIPE3_PHY_RX_TRIM
- PIPE3_PHY_TX_POWERON
- PIPE4CTR
- PIPE4TRE
- PIPE4TRN
- PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK
- PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT
- PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK
- PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT
- PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK
- PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT
- PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK
- PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT
- PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK
- PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT
- PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK
- PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT
- PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK
- PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT
- PIPE5CTR
- PIPE5TRE
- PIPE5TRN
- PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK
- PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
- PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
- PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT
- PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK
- PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT
- PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK
- PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT
- PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK
- PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT
- PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK
- PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT
- PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK
- PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT
- PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK
- PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT
- PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK
- PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT
- PIPE6CTR
- PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE6_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE6_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE6_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE7CTR
- PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK
- PIPE7_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT
- PIPE7_MAX_REQUESTS__MAX_REQUESTS_MASK
- PIPE7_MAX_REQUESTS__MAX_REQUESTS__SHIFT
- PIPE8CTR
- PIPE9CTR
- PIPE9TRE
- PIPE9TRN
- PIPEACONF
- PIPEACONF_DISABLE
- PIPEACONF_DOUBLE_WIDE
- PIPEACONF_DSR
- PIPEACONF_ENABLE
- PIPEACONF_GAMMA
- PIPEACONF_PALETTE
- PIPEACONF_PIPE_LOCKED
- PIPEACONF_PIPE_STATE
- PIPEACONF_PIPE_UNLOCKED
- PIPEACONF_SINGLE_WIDE
- PIPEAFRAMEHIGH
- PIPEAFRAMEPIXEL
- PIPEASRC
- PIPEASTAT
- PIPEATRE
- PIPEATRN
- PIPEA_DP_LINK_M_MASK
- PIPEA_DP_LINK_N_MASK
- PIPEA_DSL
- PIPEA_HBLANK_INT_EN_VLV
- PIPEA_HLINE_INT_EN
- PIPEA_LINE_COMPARE_INT_EN
- PIPEA_VBLANK_INT_EN
- PIPEBCONF
- PIPEBCONF_DISABLE
- PIPEBCONF_DOUBLE_WIDE
- PIPEBCONF_ENABLE
- PIPEBCONF_GAMMA
- PIPEBCONF_PALETTE
- PIPEBFRAMEHIGH
- PIPEBFRAMEPIXEL
- PIPEBGCMAXBLUE
- PIPEBGCMAXGREEN
- PIPEBGCMAXRED
- PIPEBSRC
- PIPEBSTAT
- PIPEBTRE
- PIPEBTRN
- PIPEBUF
- PIPEB_DSL
- PIPEB_HLINE_INT_EN
- PIPEB_LINE_COMPARE_INT_EN
- PIPEB_VBLANK_INT_EN
- PIPECCONF
- PIPECFG
- PIPECFRAMEHIGH
- PIPECFRAMEPIXEL
- PIPECONF
- PIPECONF_10BPC
- PIPECONF_12BPC
- PIPECONF_6BPC
- PIPECONF_8BPC
- PIPECONF_ACTIVE
- PIPECONF_BPC_MASK
- PIPECONF_COLOR_RANGE_SELECT
- PIPECONF_CURSOR_OFF
- PIPECONF_CXSR_DOWNCLOCK
- PIPECONF_DISABLE
- PIPECONF_DITHER_EN
- PIPECONF_DITHER_TYPE_MASK
- PIPECONF_DITHER_TYPE_SP
- PIPECONF_DITHER_TYPE_ST1
- PIPECONF_DITHER_TYPE_ST2
- PIPECONF_DITHER_TYPE_TEMP
- PIPECONF_DOUBLE_WIDE
- PIPECONF_DSIPLL_LOCK
- PIPECONF_DSI_PLL_LOCKED
- PIPECONF_EDP_RR_MODE_SWITCH
- PIPECONF_EDP_RR_MODE_SWITCH_VLV
- PIPECONF_ENABLE
- PIPECONF_FORCE_BORDER
- PIPECONF_FRAME_START_DELAY_MASK
- PIPECONF_GAMMA
- PIPECONF_GAMMA_MODE
- PIPECONF_GAMMA_MODE_10BIT
- PIPECONF_GAMMA_MODE_12BIT
- PIPECONF_GAMMA_MODE_8BIT
- PIPECONF_GAMMA_MODE_MASK_I9XX
- PIPECONF_GAMMA_MODE_MASK_ILK
- PIPECONF_GAMMA_MODE_SHIFT
- PIPECONF_GAMMA_MODE_SPLIT
- PIPECONF_INTERLACED_DBL_ILK
- PIPECONF_INTERLACED_ILK
- PIPECONF_INTERLACE_FIELD_0_ONLY
- PIPECONF_INTERLACE_MASK
- PIPECONF_INTERLACE_MASK_HSW
- PIPECONF_INTERLACE_MODE_MASK
- PIPECONF_INTERLACE_W_FIELD_INDICATION
- PIPECONF_INTERLACE_W_SYNC_SHIFT
- PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL
- PIPECONF_LOCKED
- PIPECONF_PALETTE
- PIPECONF_PFIT_PF_INTERLACED_DBL_ILK
- PIPECONF_PFIT_PF_INTERLACED_ILK
- PIPECONF_PIPE_LOCKED
- PIPECONF_PIPE_UNLOCKED
- PIPECONF_PLANE_OFF
- PIPECONF_PROGRESSIVE
- PIPECONF_SINGLE_WIDE
- PIPECONF_UNLOCKED
- PIPECSRC
- PIPECSTAT
- PIPECTRE
- PIPECTRN
- PIPEC_HLINE_INT_EN
- PIPEC_LINE_COMPARE_INT_EN
- PIPEC_VBLANK_INT_EN
- PIPEDIR
- PIPEDIR_IN
- PIPEDIR_INOUT
- PIPEDIR_NONE
- PIPEDIR_OUT
- PIPEDSL
- PIPEDTRE
- PIPEDTRN
- PIPEETRE
- PIPEETRN
- PIPEFRAME
- PIPEFRAMEPIXEL
- PIPEFS_MAGIC
- PIPEFTRE
- PIPEFTRN
- PIPEGCMAX
- PIPEID
- PIPELINESTAT_START
- PIPELINESTAT_STOP
- PIPELINE_INFO_N_OUTPUTS
- PIPELINE_INFO_N_VALID_INPUTS
- PIPELINE_SELECT
- PIPEMAXP
- PIPEMISC
- PIPEMISC_DITHER_10_BPC
- PIPEMISC_DITHER_12_BPC
- PIPEMISC_DITHER_6_BPC
- PIPEMISC_DITHER_8_BPC
- PIPEMISC_DITHER_BPC_MASK
- PIPEMISC_DITHER_ENABLE
- PIPEMISC_DITHER_TYPE_MASK
- PIPEMISC_DITHER_TYPE_SP
- PIPEMISC_HDR_MODE_PRECISION
- PIPEMISC_OUTPUT_COLORSPACE_YUV
- PIPEMISC_YUV420_ENABLE
- PIPEMISC_YUV420_MODE_FULL_BLEND
- PIPENM
- PIPEPERI
- PIPESEL
- PIPESRC
- PIPESTAT
- PIPESTAT_CRC_DONE
- PIPESTAT_CRC_DONE_EN
- PIPESTAT_CRC_ERROR
- PIPESTAT_CRC_ERROR_EN
- PIPESTAT_DISPLINE_COMP
- PIPESTAT_DISPLINE_COMP_EN
- PIPESTAT_FIFO_UNDERRUN
- PIPESTAT_FLD_EVT_EVEN
- PIPESTAT_FLD_EVT_EVEN_EN
- PIPESTAT_FLD_EVT_ODD
- PIPESTAT_FLD_EVT_ODD_EN
- PIPESTAT_HOTPLUG
- PIPESTAT_HOTPLUG_EN
- PIPESTAT_HOTPLUG_STATE
- PIPESTAT_INT_ENABLE_MASK
- PIPESTAT_INT_STATUS_MASK
- PIPESTAT_OVL_UPDATE
- PIPESTAT_OVL_UPDATE_EN
- PIPESTAT_TV_HOTPLUG
- PIPESTAT_TV_HOTPLUG_EN
- PIPESTAT_VBLANK
- PIPESTAT_VBLANK_EN
- PIPESTAT_VERTICAL_SYNC_EN
- PIPESTAT_VSYNC
- PIPES_PER_STAGE
- PIPETYPE
- PIPE_10BPC
- PIPE_6BPC
- PIPE_8BPC
- PIPE_A
- PIPE_ACTIVE_ERR_SHIFT
- PIPE_ALIGNED
- PIPE_ALIGNED_SURF
- PIPE_A_CRC_DONE
- PIPE_A_CRC_ERR
- PIPE_A_EVENT_INTERRUPT
- PIPE_A_EVEN_FIELD
- PIPE_A_FIFO_UNDERRUN
- PIPE_A_LINE_COMPARE
- PIPE_A_ODD_FIELD
- PIPE_A_OFFSET
- PIPE_A_PSR_STATUS_VLV
- PIPE_A_SCRAMBLE_RESET
- PIPE_A_VBLANK
- PIPE_A_VSYNC
- PIPE_B
- PIPE_BPC_MASK
- PIPE_BUF
- PIPE_BUF_FLAG_ATOMIC
- PIPE_BUF_FLAG_GIFT
- PIPE_BUF_FLAG_LRU
- PIPE_BUF_FLAG_PACKET
- PIPE_BULK
- PIPE_B_CRC_DONE
- PIPE_B_CRC_ERR
- PIPE_B_EVENT_INTERRUPT
- PIPE_B_EVEN_FIELD
- PIPE_B_FIFO_UNDERRUN
- PIPE_B_LINE_COMPARE
- PIPE_B_ODD_FIELD
- PIPE_B_OFFSET
- PIPE_B_PSR_INTERRUPT_ENABLE_VLV
- PIPE_B_PSR_STATUS_VLV
- PIPE_B_SCRAMBLE_RESET
- PIPE_B_VBLANK
- PIPE_B_VSYNC
- PIPE_C
- PIPE_CHICKEN
- PIPE_CLK_STABLE
- PIPE_CLK_WAIT_MAX
- PIPE_CLK_WAIT_MIN
- PIPE_CLOCK_SET
- PIPE_CLOSE_ERROR
- PIPE_CLOSE_GRACEFUL
- PIPE_CLOSE_LOAD_SNAPSHOT
- PIPE_CLOSE_REBOOT
- PIPE_CMD_CLOSE
- PIPE_CMD_OPEN
- PIPE_CMD_POLL
- PIPE_CMD_READ
- PIPE_CMD_WAKE_ON_DONE_IO
- PIPE_CMD_WAKE_ON_READ
- PIPE_CMD_WAKE_ON_WRITE
- PIPE_CMD_WRITE
- PIPE_CMN_CTRL1
- PIPE_CMN_CTRL2
- PIPE_CODEC_IN0
- PIPE_CODEC_IN1
- PIPE_CODEC_OUT0
- PIPE_CODEC_OUT1
- PIPE_COM_LOCK_CFG1
- PIPE_COM_LOCK_CFG2
- PIPE_CONFIG
- PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
- PIPE_CONF_CHECK_BOOL
- PIPE_CONF_CHECK_BOOL_INCOMPLETE
- PIPE_CONF_CHECK_CLOCK_FUZZY
- PIPE_CONF_CHECK_FLAGS
- PIPE_CONF_CHECK_I
- PIPE_CONF_CHECK_INFOFRAME
- PIPE_CONF_CHECK_M_N
- PIPE_CONF_CHECK_M_N_ALT
- PIPE_CONF_CHECK_P
- PIPE_CONF_CHECK_X
- PIPE_CONF_QUIRK
- PIPE_CONTROL
- PIPE_CONTROL_COMMAND_CACHE_INVALIDATE
- PIPE_CONTROL_CONST_CACHE_INVALIDATE
- PIPE_CONTROL_CS_STALL
- PIPE_CONTROL_DC_FLUSH_ENABLE
- PIPE_CONTROL_DEPTH_CACHE_FLUSH
- PIPE_CONTROL_DEPTH_STALL
- PIPE_CONTROL_FLUSH_ENABLE
- PIPE_CONTROL_FLUSH_L3
- PIPE_CONTROL_GLOBAL_GTT
- PIPE_CONTROL_GLOBAL_GTT_IVB
- PIPE_CONTROL_INDIRECT_STATE_DISABLE
- PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
- PIPE_CONTROL_MEDIA_STATE_CLEAR
- PIPE_CONTROL_MMIO_WRITE
- PIPE_CONTROL_NOTIFY
- PIPE_CONTROL_POST_SYNC_OP_MASK
- PIPE_CONTROL_QW_WRITE
- PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
- PIPE_CONTROL_STALL_AT_SCOREBOARD
- PIPE_CONTROL_STATE_CACHE_INVALIDATE
- PIPE_CONTROL_STORE_DATA_INDEX
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
- PIPE_CONTROL_TILE_CACHE_FLUSH
- PIPE_CONTROL_TLB_INVALIDATE
- PIPE_CONTROL_VF_CACHE_INVALIDATE
- PIPE_CONTROL_WRITE_FLUSH
- PIPE_COUNT_MASK
- PIPE_COUNT_SHIFT
- PIPE_CRC_CTL
- PIPE_CRC_DONE_ENABLE
- PIPE_CRC_DONE_INTERRUPT_STATUS
- PIPE_CRC_ENABLE
- PIPE_CRC_ERROR_ENABLE
- PIPE_CRC_ERROR_INTERRUPT_STATUS
- PIPE_CRC_INCLUDE_BORDER_I8XX
- PIPE_CRC_RES_1_IVB
- PIPE_CRC_RES_2_IVB
- PIPE_CRC_RES_3_IVB
- PIPE_CRC_RES_4_IVB
- PIPE_CRC_RES_5_IVB
- PIPE_CRC_RES_BLUE
- PIPE_CRC_RES_GREEN
- PIPE_CRC_RES_RED
- PIPE_CRC_RES_RES1_I915
- PIPE_CRC_RES_RES2_G4X
- PIPE_CRC_SOURCE_DMUX_SKL
- PIPE_CRC_SOURCE_DP_B_G4X
- PIPE_CRC_SOURCE_DP_B_VLV
- PIPE_CRC_SOURCE_DP_C_G4X
- PIPE_CRC_SOURCE_DP_C_VLV
- PIPE_CRC_SOURCE_DP_D_G4X
- PIPE_CRC_SOURCE_DP_D_VLV
- PIPE_CRC_SOURCE_FDI_ILK
- PIPE_CRC_SOURCE_HDMIB_VLV
- PIPE_CRC_SOURCE_HDMIC_VLV
- PIPE_CRC_SOURCE_PF_IVB
- PIPE_CRC_SOURCE_PIPE_I9XX
- PIPE_CRC_SOURCE_PIPE_ILK
- PIPE_CRC_SOURCE_PIPE_VLV
- PIPE_CRC_SOURCE_PLANE_1_SKL
- PIPE_CRC_SOURCE_PLANE_2_SKL
- PIPE_CRC_SOURCE_PLANE_3_SKL
- PIPE_CRC_SOURCE_PLANE_4_SKL
- PIPE_CRC_SOURCE_PLANE_5_SKL
- PIPE_CRC_SOURCE_PLANE_6_SKL
- PIPE_CRC_SOURCE_PLANE_7_SKL
- PIPE_CRC_SOURCE_PORT_A_ILK
- PIPE_CRC_SOURCE_PRIMARY_ILK
- PIPE_CRC_SOURCE_PRIMARY_IVB
- PIPE_CRC_SOURCE_SDVOB_I9XX
- PIPE_CRC_SOURCE_SDVOC_I9XX
- PIPE_CRC_SOURCE_SPRITE_ILK
- PIPE_CRC_SOURCE_SPRITE_IVB
- PIPE_CRC_SOURCE_TV_POST
- PIPE_CRC_SOURCE_TV_PRE
- PIPE_CSC_COEFF_BU
- PIPE_CSC_COEFF_BV
- PIPE_CSC_COEFF_BY
- PIPE_CSC_COEFF_RU_GU
- PIPE_CSC_COEFF_RV_GV
- PIPE_CSC_COEFF_RY_GY
- PIPE_CSC_MODE
- PIPE_CSC_OUTPUT_COEFF_BU
- PIPE_CSC_OUTPUT_COEFF_BV
- PIPE_CSC_OUTPUT_COEFF_BY
- PIPE_CSC_OUTPUT_COEFF_RU_GU
- PIPE_CSC_OUTPUT_COEFF_RV_GV
- PIPE_CSC_OUTPUT_COEFF_RY_GY
- PIPE_CSC_OUTPUT_POSTOFF_HI
- PIPE_CSC_OUTPUT_POSTOFF_LO
- PIPE_CSC_OUTPUT_POSTOFF_ME
- PIPE_CSC_OUTPUT_PREOFF_HI
- PIPE_CSC_OUTPUT_PREOFF_LO
- PIPE_CSC_OUTPUT_PREOFF_ME
- PIPE_CSC_POSTOFF_HI
- PIPE_CSC_POSTOFF_LO
- PIPE_CSC_POSTOFF_ME
- PIPE_CSC_PREOFF_HI
- PIPE_CSC_PREOFF_LO
- PIPE_CSC_PREOFF_ME
- PIPE_CTL
- PIPE_CTL_ELASTICITYBUFFERMODE_
- PIPE_CTL_TXDEEMPHASIS_MASK_
- PIPE_CTL_TXMARGIN_MASK_
- PIPE_CTL_TXSWING_
- PIPE_CURRENT_DEVICE_VERSION
- PIPE_C_LINE_COMPARE
- PIPE_C_OFFSET
- PIPE_C_SCRAMBLE_RESET
- PIPE_C_VBLANK
- PIPE_C_VSYNC
- PIPE_D
- PIPE_DATA_M1
- PIPE_DATA_M1_OFFSET
- PIPE_DATA_M2
- PIPE_DATA_M2_OFFSET
- PIPE_DATA_M_G4X
- PIPE_DATA_N1
- PIPE_DATA_N1_OFFSET
- PIPE_DATA_N2
- PIPE_DATA_N2_OFFSET
- PIPE_DATA_N_G4X
- PIPE_DEF_BUFFERS
- PIPE_DEF_BUFS
- PIPE_DEPTH
- PIPE_DEVEP_MASK
- PIPE_DISPLAY_LINE_COMPARE_ENABLE
- PIPE_DISPLAY_LINE_COMPARE_STATUS
- PIPE_DPST_EVENT_ENABLE
- PIPE_DPST_EVENT_STATUS
- PIPE_DP_LINK_M
- PIPE_DP_LINK_N
- PIPE_DRIVER_VERSION
- PIPE_DSI0_OFFSET
- PIPE_DSI1_OFFSET
- PIPE_D_OFFSET
- PIPE_EDP_OFFSET
- PIPE_END_POINT
- PIPE_ERROR_AGAIN
- PIPE_ERROR_INVAL
- PIPE_ERROR_IO
- PIPE_ERROR_NOMEM
- PIPE_EVENT_MASK
- PIPE_EVEN_FIELD_INTERRUPT_ENABLE
- PIPE_EVEN_FIELD_INTERRUPT_STATUS
- PIPE_FIFO_UNDERRUN
- PIPE_FIFO_UNDERRUN_STATUS
- PIPE_FLIPCOUNT_G4X
- PIPE_FRAMESTART_INTERRUPT_ENABLE
- PIPE_FRAMESTART_INTERRUPT_STATUS
- PIPE_FRAME_HIGH_MASK
- PIPE_FRAME_HIGH_SHIFT
- PIPE_FRAME_LOW_MASK
- PIPE_FRAME_LOW_SHIFT
- PIPE_FRMCOUNT_G4X
- PIPE_FRMTMSTMP
- PIPE_GATING_CONTROL_DISABLE
- PIPE_GATING_CONTROL_ENABLE
- PIPE_GATING_CONTROL_INIT
- PIPE_GMBUS_EVENT_ENABLE
- PIPE_GMBUS_INTERRUPT_STATUS
- PIPE_GMCH_DATA_M
- PIPE_GMCH_DATA_M_MASK
- PIPE_GMCH_DATA_M_TU_SIZE_MASK
- PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
- PIPE_GMCH_DATA_N
- PIPE_GMCH_DATA_N_MASK
- PIPE_HBLANK_INT_STATUS
- PIPE_HDMI_AUDIO_BUFFER_DONE
- PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS
- PIPE_HDMI_AUDIO_INT_MASK
- PIPE_HDMI_AUDIO_UNDERRUN
- PIPE_HDMI_AUDIO_UNDERRUN_STATUS
- PIPE_HOTPLUG_INTERRUPT_ENABLE
- PIPE_HOTPLUG_INTERRUPT_STATUS
- PIPE_HOTPLUG_TV_INTERRUPT_ENABLE
- PIPE_HOTPLUG_TV_INTERRUPT_STATUS
- PIPE_ID0
- PIPE_ID1
- PIPE_ID2
- PIPE_ID3
- PIPE_ID_IN_START
- PIPE_ID_OUT_START
- PIPE_ID_PIPE_2D
- PIPE_ID_PIPE_3D
- PIPE_INFO_TO_CMD
- PIPE_INIT
- PIPE_INIT_END
- PIPE_INTERLEAVE
- PIPE_INTERLEAVE_1KB
- PIPE_INTERLEAVE_256B
- PIPE_INTERLEAVE_512B
- PIPE_INTERLEAVE_SIZE
- PIPE_INTERLEAVE_SIZE_MASK
- PIPE_INTERLEAVE_SIZE_SHIFT
- PIPE_INTERRUPT
- PIPE_ISOCHRONOUS
- PIPE_LEFT
- PIPE_LEGACY_BLC_EVENT_ENABLE
- PIPE_LEGACY_BLC_EVENT_STATUS
- PIPE_LINK_M1
- PIPE_LINK_M1_OFFSET
- PIPE_LINK_M2
- PIPE_LINK_M2_OFFSET
- PIPE_LINK_M_G4X
- PIPE_LINK_N1
- PIPE_LINK_N1_OFFSET
- PIPE_LINK_N2
- PIPE_LINK_N2_OFFSET
- PIPE_LINK_N_G4X
- PIPE_MASK
- PIPE_MAXP_MASK
- PIPE_MAX_SIZE
- PIPE_MBUS_DBOX_CTL
- PIPE_MEDIA0_IN
- PIPE_MEDIA0_OUT
- PIPE_MEDIA1_IN
- PIPE_MEDIA1_OUT
- PIPE_MEDIA2_IN
- PIPE_MEDIA3_IN
- PIPE_MEDIA_LOOP1_IN
- PIPE_MEDIA_LOOP1_OUT
- PIPE_MEDIA_LOOP2_IN
- PIPE_MEDIA_LOOP2_OUT
- PIPE_MESSAGE_DATA
- PIPE_MESSAGE_INVALID
- PIPE_MESSAGE_MAXIMUM
- PIPE_METER_FRAC
- PIPE_METER_INT
- PIPE_MIN_SIZE
- PIPE_MSG_DATA
- PIPE_MSG_INVALID
- PIPE_MSG_MAX
- PIPE_MULT
- PIPE_ODD_FIELD_INTERRUPT_ENABLE
- PIPE_ODD_FIELD_INTERRUPT_STATUS
- PIPE_OVERLAY_UPDATED_ENABLE
- PIPE_OVERLAY_UPDATED_STATUS
- PIPE_PARANOIA
- PIPE_PCM0_IN
- PIPE_PCM0_OUT
- PIPE_PCM1_IN
- PIPE_PCM1_OUT
- PIPE_PCM2_OUT
- PIPE_PHYPLL_PIXEL_RATE_SOURCE
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF
- PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG
- PIPE_PHY_RATE_RD
- PIPE_PIXEL_MASK
- PIPE_PIXEL_RATE_PLL_SOURCE
- PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL
- PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL
- PIPE_PIXEL_RATE_SOURCE
- PIPE_PIXEL_RATE_SOURCE_P0PLL
- PIPE_PIXEL_RATE_SOURCE_P1PLL
- PIPE_PIXEL_RATE_SOURCE_P2PLL
- PIPE_PIXEL_SHIFT
- PIPE_POLL_HUP
- PIPE_POLL_IN
- PIPE_POLL_OUT
- PIPE_PSR_INT_EN
- PIPE_RCV_DET_INH
- PIPE_READ_MODE
- PIPE_REG_CMD
- PIPE_REG_GET_SIGNALLED
- PIPE_REG_OPEN_BUFFER
- PIPE_REG_OPEN_BUFFER_HIGH
- PIPE_REG_SIGNAL_BUFFER
- PIPE_REG_SIGNAL_BUFFER_COUNT
- PIPE_REG_SIGNAL_BUFFER_HIGH
- PIPE_REG_VERSION
- PIPE_RESTORE
- PIPE_RIGHT
- PIPE_RSVD
- PIPE_RUNNING
- PIPE_SAVE
- PIPE_SCRAMBLE_RESET_MASK
- PIPE_SET_SELECT_MASK
- PIPE_SET_SELECT_SHIFT
- PIPE_SIZE
- PIPE_SPROT_LOOP_IN
- PIPE_SPROT_LOOP_OUT
- PIPE_START_VBLANK_INTERRUPT_ENABLE
- PIPE_START_VBLANK_INTERRUPT_STATUS
- PIPE_STATE_PAUSED
- PIPE_STATE_PENDING
- PIPE_STATE_STARTED
- PIPE_STATE_STOPPED
- PIPE_STATS_HW_FIFO
- PIPE_STOPPED
- PIPE_TE_ENABLE
- PIPE_TE_STATUS
- PIPE_TILING
- PIPE_TILING__MASK
- PIPE_TILING__SHIFT
- PIPE_TIME_NOTIFIED
- PIPE_UNALIGNED_SURF
- PIPE_UNDEFINED
- PIPE_UTMI_CLK_DIS
- PIPE_UTMI_CLK_SEL
- PIPE_VBLANK_CLEAR
- PIPE_VBLANK_INTERRUPT_ENABLE
- PIPE_VBLANK_INTERRUPT_STATUS
- PIPE_VBLANK_MASK
- PIPE_VBLANK_STATUS
- PIPE_VOIP_IN
- PIPE_VOIP_OUT
- PIPE_VSYNC_CLEAR
- PIPE_VSYNC_ENABL
- PIPE_VSYNC_INTERRUPT_ENABLE
- PIPE_VSYNC_INTERRUPT_STATUS
- PIPE_VSYNC_STATUS
- PIPE_WAKE_CLOSED
- PIPE_WAKE_READ
- PIPE_WAKE_UNLOCK_DMA
- PIPE_WAKE_UNLOCK_DMA_SHARED
- PIPE_WAKE_WRITE
- PIPE_WM_LINETIME
- PIPE_WM_LINETIME_IPS_LINETIME
- PIPE_WM_LINETIME_IPS_LINETIME_MASK
- PIPE_WM_LINETIME_MASK
- PIPE_WM_LINETIME_TIME
- PIPEinput
- PIPEnCTR
- PIPEoutput
- PIPExBUF
- PIPR
- PIPR_BIT
- PIPR_PHYIP
- PIPS_ADAPTER
- PIPS_CHUNK
- PIPS_CONF
- PIPS_CS_CMD
- PIPS_DCDB_CMD
- PIPS_DCDB_TABLE
- PIPS_DCDB_TABLE_TAPE
- PIPS_DEVSTATE
- PIPS_DRIVE_INFO
- PIPS_ENQ
- PIPS_FC_CMD
- PIPS_FFDC_CMD
- PIPS_FLASHBIOS_CMD
- PIPS_FLASHFW_CMD
- PIPS_HARDWARE
- PIPS_HOST_COMMAND
- PIPS_IOCTL_CMD
- PIPS_IO_CMD
- PIPS_LD
- PIPS_LD_CMD
- PIPS_LD_INFO
- PIPS_NVRAM_CMD
- PIPS_NVRAM_P5
- PIPS_RESET_CMD
- PIPS_SCSI_INQ_DATA
- PIPS_STATUS
- PIPS_STATUS_CMD
- PIPS_SUBSYS
- PIPS_US_CMD
- PIPS_VERSION_INFO
- PIP_APP_CMD_REPORT_ID
- PIP_APP_DEEP_SLEEP_REPORT_ID
- PIP_APP_RESP_REPORT_ID
- PIP_BL_APP_INFO_RESP_LENGTH
- PIP_BL_BLOCK_WRITE_RESP_LEN
- PIP_BL_CMD_GET_BL_INFO
- PIP_BL_CMD_INITIATE_BL
- PIP_BL_CMD_LAUNCH_APP
- PIP_BL_CMD_PROGRAM_VERIFY_ROW
- PIP_BL_CMD_REPORT_ID
- PIP_BL_CMD_VERIFY_APP_INTEGRITY
- PIP_BL_FAIL_EXIT_RESP_LEN
- PIP_BL_FAIL_EXIT_STATUS_CODE
- PIP_BL_GET_INFO_RESP_LENGTH
- PIP_BL_INITIATE_RESP_LEN
- PIP_BL_INTEGRITY_CHEKC_PASS
- PIP_BL_PLATFORM_VER_MASK
- PIP_BL_PLATFORM_VER_SHIFT
- PIP_BL_READ_APP_INFO_CMD_LENGTH
- PIP_BL_RESP_REPORT_ID
- PIP_BL_VERIFY_INTEGRITY_RESP_LEN
- PIP_BTN_REPORT_HEAD_SIZE
- PIP_BTN_REPORT_ID
- PIP_BTN_REPORT_MAX_SIZE
- PIP_BUTTONS_MASK
- PIP_BUTTONS_OFFSET
- PIP_CMD_CALIBRATE
- PIP_CMD_COMPLETE_SUCCESS
- PIP_CMD_DATA_ADDR
- PIP_DEEP_SLEEP_OPCODE
- PIP_DEEP_SLEEP_OPCODE_MASK
- PIP_DEEP_SLEEP_RESP_LENGTH
- PIP_DEEP_SLEEP_STATE_MASK
- PIP_DEEP_SLEEP_STATE_OFF
- PIP_DEEP_SLEEP_STATE_ON
- PIP_DEV_GET_PWR_STATE
- PIP_DEV_GET_SLEEP_TIME
- PIP_DEV_SET_PWR_STATE
- PIP_DEV_SET_SLEEP_TIME
- PIP_DEV_UNINIT_SLEEP_TIME
- PIP_EOP_KEY
- PIP_GET_EVENT_ID
- PIP_GET_TOUCH_ID
- PIP_GET_TOUCH_TYPE
- PIP_HID_APP_REPORT_ID
- PIP_HID_BL_REPORT_ID
- PIP_HID_DESCRIPTOR_ADDR
- PIP_HID_DESCRIPTOR_SIZE
- PIP_INPUT_REPORT_ADDR
- PIP_INVALID_CMD
- PIP_MIN_APP_CMD_LENGTH
- PIP_MIN_APP_RESP_LENGTH
- PIP_MIN_BL_CMD_LENGTH
- PIP_MIN_BL_RESP_LENGTH
- PIP_NUMBER_OF_TOUCH_MASK
- PIP_NUMBER_OF_TOUCH_OFFSET
- PIP_OUTPUT_REPORT_ADDR
- PIP_PRODUCT_FAMILY_MASK
- PIP_PRODUCT_FAMILY_TRACKPAD
- PIP_PROXIMITY_DISTANCE_MASK
- PIP_PROXIMITY_DISTANCE_OFFSET
- PIP_PROXIMITY_REPORT_ID
- PIP_PROXIMITY_REPORT_SIZE
- PIP_PUSH_BTN_REPORT_ID
- PIP_READ_SYS_INFO_CMD_LENGTH
- PIP_READ_SYS_INFO_RESP_LENGTH
- PIP_REPORT_DESCRIPTOR_ADDR
- PIP_RESP_APP_CMD_OFFSET
- PIP_RESP_BL_SOP_OFFSET
- PIP_RESP_LENGTH_OFFSET
- PIP_RESP_LENGTH_SIZE
- PIP_RESP_REPORT_ID_OFFSET
- PIP_RESP_RSVD_KEY
- PIP_RESP_RSVD_OFFSET
- PIP_RESP_STATUS_OFFSET
- PIP_RETRIEVE_DATA_STRUCTURE
- PIP_SENSING_MODE_MUTUAL_CAP_FINE
- PIP_SENSING_MODE_SELF_CAP
- PIP_SET_PROXIMITY
- PIP_SOP_KEY
- PIP_TOUCH_REPORT_HEAD_SIZE
- PIP_TOUCH_REPORT_ID
- PIP_TOUCH_REPORT_MAX_SIZE
- PIP_TOUCH_TYPE_FINGER
- PIP_TOUCH_TYPE_HOVER
- PIP_TOUCH_TYPE_PROXIMITY
- PIP_UNSUPPORTED_CMD_RESP_LENGTH
- PIP_WAKEUP_EVENT_REPORT_ID
- PIP_WAKEUP_EVENT_SIZE
- PIQK_MATRIX_REGS_SETTING
- PIR
- PIRANHA_ADDR_MASK
- PIRANHA_ADDR_VAL
- PIRELLI_BOARDS
- PIRELLI_PRODUCT_1004
- PIRELLI_PRODUCT_1005
- PIRELLI_PRODUCT_1006
- PIRELLI_PRODUCT_1007
- PIRELLI_PRODUCT_1008
- PIRELLI_PRODUCT_1009
- PIRELLI_PRODUCT_100A
- PIRELLI_PRODUCT_100B
- PIRELLI_PRODUCT_100C
- PIRELLI_PRODUCT_100D
- PIRELLI_PRODUCT_100E
- PIRELLI_PRODUCT_100F
- PIRELLI_PRODUCT_1011
- PIRELLI_PRODUCT_1012
- PIRELLI_PRODUCT_C100_1
- PIRELLI_PRODUCT_C100_2
- PIRELLI_VENDOR_ID
- PIRQ_ATA
- PIRQ_COMPLETE
- PIRQ_ERR
- PIRQ_FATAL
- PIRQ_MASK_DEFAULT
- PIRQ_MASK_FREEZE
- PIRQ_MSI_GROUP
- PIRQ_NEEDS_EOI
- PIRQ_OFFLINE
- PIRQ_ONLINE
- PIRQ_PENALTY_ISA_ALWAYS
- PIRQ_PENALTY_ISA_TYPICAL
- PIRQ_PENALTY_ISA_USED
- PIRQ_PENALTY_PCI_POSSIBLE
- PIRQ_PENALTY_PCI_USING
- PIRQ_PENDING
- PIRQ_REPLY
- PIRQ_SHAREABLE
- PIRQ_SIGNATURE
- PIRQ_SIS_IRQ_DISABLE
- PIRQ_SIS_IRQ_MASK
- PIRQ_SIS_USB_ENABLE
- PIRQ_VERSION
- PIR_BIT
- PIR_MDC
- PIR_MDI
- PIR_MDO
- PIR_MMD
- PIR_OFFSET
- PIS
- PISCR_PIE
- PISCR_PIRQ_MASK
- PISCR_PS
- PISCR_PTE
- PISCR_PTF
- PISMO_NUM_CS
- PISR
- PISR_EOC
- PISR_FIFOE
- PISR_FSR
- PISTACHIO_CORE_REV_A1
- PISTACHIO_CORE_REV_B0
- PISTACHIO_CORE_REV_REG
- PISTACHIO_CR_PERIPH_DMA_ROUTE
- PISTACHIO_CR_PERIPH_DMA_ROUTE_MASK
- PISTACHIO_CR_PERIPH_DMA_ROUTE_SHIFT
- PISTACHIO_FUNCTION_AUDIO_CLK_IN
- PISTACHIO_FUNCTION_AUDIO_PLL_LOCK
- PISTACHIO_FUNCTION_AUDIO_SYNC
- PISTACHIO_FUNCTION_AUDIO_TRIGGER
- PISTACHIO_FUNCTION_BT_PLL_LOCK
- PISTACHIO_FUNCTION_DDR_DEBUG
- PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0
- PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1
- PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND
- PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND
- PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND
- PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND
- PISTACHIO_FUNCTION_DEBUG_S2L_DONE
- PISTACHIO_FUNCTION_DREQ0
- PISTACHIO_FUNCTION_DREQ1
- PISTACHIO_FUNCTION_DREQ2
- PISTACHIO_FUNCTION_DREQ3
- PISTACHIO_FUNCTION_DREQ4
- PISTACHIO_FUNCTION_DREQ5
- PISTACHIO_FUNCTION_ETH
- PISTACHIO_FUNCTION_ETH_DEBUG
- PISTACHIO_FUNCTION_I2C0
- PISTACHIO_FUNCTION_I2C1
- PISTACHIO_FUNCTION_I2C2
- PISTACHIO_FUNCTION_I2C3
- PISTACHIO_FUNCTION_I2S_DAC_CLK
- PISTACHIO_FUNCTION_I2S_IN
- PISTACHIO_FUNCTION_I2S_OUT
- PISTACHIO_FUNCTION_IR
- PISTACHIO_FUNCTION_MDC_DEBUG
- PISTACHIO_FUNCTION_MIPS_DEBUG
- PISTACHIO_FUNCTION_MIPS_PLL_LOCK
- PISTACHIO_FUNCTION_MIPS_TRACE_CLK
- PISTACHIO_FUNCTION_MIPS_TRACE_DATA
- PISTACHIO_FUNCTION_MIPS_TRACE_DINT
- PISTACHIO_FUNCTION_MIPS_TRACE_DM
- PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N
- PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN
- PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT
- PISTACHIO_FUNCTION_NONE
- PISTACHIO_FUNCTION_PWMPDM
- PISTACHIO_FUNCTION_ROM_DEBUG
- PISTACHIO_FUNCTION_RPU_DEBUG
- PISTACHIO_FUNCTION_RPU_L_PLL_LOCK
- PISTACHIO_FUNCTION_RPU_V_PLL_LOCK
- PISTACHIO_FUNCTION_SDHOST
- PISTACHIO_FUNCTION_SDHOST_DEBUG
- PISTACHIO_FUNCTION_SOCIF_DEBUG
- PISTACHIO_FUNCTION_SPDIF_IN
- PISTACHIO_FUNCTION_SPDIF_OUT
- PISTACHIO_FUNCTION_SPIM0
- PISTACHIO_FUNCTION_SPIM1
- PISTACHIO_FUNCTION_SPIS
- PISTACHIO_FUNCTION_SRAM_DEBUG
- PISTACHIO_FUNCTION_SYS_PLL_LOCK
- PISTACHIO_FUNCTION_UART0
- PISTACHIO_FUNCTION_UART1
- PISTACHIO_FUNCTION_USB_DEBUG
- PISTACHIO_FUNCTION_WIFI_PLL_LOCK
- PISTACHIO_INTERNAL_DAC_CTRL
- PISTACHIO_INTERNAL_DAC_CTRL_PWRDN_MASK
- PISTACHIO_INTERNAL_DAC_CTRL_PWR_SEL_MASK
- PISTACHIO_INTERNAL_DAC_FORMATS
- PISTACHIO_INTERNAL_DAC_GTI_CTRL
- PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_MASK
- PISTACHIO_INTERNAL_DAC_GTI_CTRL_ADDR_SHIFT
- PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_MASK
- PISTACHIO_INTERNAL_DAC_GTI_CTRL_WDATA_SHIFT
- PISTACHIO_INTERNAL_DAC_GTI_CTRL_WE_MASK
- PISTACHIO_INTERNAL_DAC_PWR
- PISTACHIO_INTERNAL_DAC_PWR_MASK
- PISTACHIO_INTERNAL_DAC_SRST
- PISTACHIO_INTERNAL_DAC_SRST_MASK
- PISTACHIO_PIN_JTAG_COMPLY
- PISTACHIO_PIN_MFIO
- PISTACHIO_PIN_POR_DISABLE
- PISTACHIO_PIN_RESETN
- PISTACHIO_PIN_SAFE_MODE
- PISTACHIO_PIN_TCK
- PISTACHIO_PIN_TDI
- PISTACHIO_PIN_TDO
- PISTACHIO_PIN_TMS
- PISTACHIO_PIN_TRSTN
- PISTACHIO_RESET_ETHERNET
- PISTACHIO_RESET_EVT
- PISTACHIO_RESET_HASH
- PISTACHIO_RESET_I2C0
- PISTACHIO_RESET_I2C1
- PISTACHIO_RESET_I2C2
- PISTACHIO_RESET_I2C3
- PISTACHIO_RESET_I2S_IN
- PISTACHIO_RESET_I2S_OUT
- PISTACHIO_RESET_IR
- PISTACHIO_RESET_MAX
- PISTACHIO_RESET_MDC
- PISTACHIO_RESET_PRL_OUT
- PISTACHIO_RESET_PWM_PDM
- PISTACHIO_RESET_QSPI
- PISTACHIO_RESET_SDHOST
- PISTACHIO_RESET_SPDIF_IN
- PISTACHIO_RESET_SPDIF_OUT
- PISTACHIO_RESET_SPI
- PISTACHIO_RESET_TIMER
- PISTACHIO_RESET_UART0
- PISTACHIO_RESET_UART1
- PISTACHIO_RESET_USB_H
- PISTACHIO_RESET_USB_PHY_PON
- PISTACHIO_RESET_USB_PHY_PR
- PISTACHIO_RESET_USB_PR
- PISTACHIO_SOFT_RESET
- PIS_PER_SB_E4
- PIT0_OFFSET
- PITA2_ICR
- PITA2_ICR_INT0
- PITA2_ICR_INT0_EN
- PITA2_MISC
- PITA2_MISC_CONFIG
- PITA_GPIN
- PITA_GPIN_SCL
- PITA_GPIN_SDA
- PITA_GPIOICR
- PITA_GPOEN
- PITA_GPOUT
- PITA_ICR
- PITA_ICR_REG
- PITA_INT0_ENABLE
- PITA_INT0_STATUS
- PITA_MISC
- PITA_MISC_REG
- PITA_PARA_MPX_MODE
- PITA_PARA_SOFTRESET
- PITA_SER_SOFTRESET
- PITBASE
- PITCAIRN_MC_UCODE_SIZE
- PITCAIRN_SMC_UCODE_SIZE
- PITCAIRN_SMC_UCODE_START
- PITCH
- PITCH1
- PITCH2
- PITCH3
- PITCH_48000
- PITCH_57081
- PITCH_67882
- PITCH_80726
- PITCH_85000
- PITCH_96000
- PITCH_DEC
- PITCH_INC
- PITCH_SHIFT
- PITCTRL_CHN
- PITCVAL
- PITLDVAL
- PITMCR
- PITMCR_MDIS
- PITTCTRL
- PITTCTRL_TEN
- PITTCTRL_TIE
- PITTFLG
- PITTFLG_TIF
- PIT_ALL_ON
- PIT_BASE
- PIT_CH0
- PIT_CH2
- PIT_CPIV
- PIT_CTRL
- PIT_CYCLES_PER_JIFFY
- PIT_DEFAULT
- PIT_ENABLE_SHIFT
- PIT_IRQ_SHIFT
- PIT_LATCH
- PIT_MODE
- PIT_PARALLEL
- PIT_PICNT
- PIT_PRIO_MASK
- PIT_PRIO_SHIFT
- PIT_SIOA
- PIT_SIOB
- PIT_T0
- PIT_T1
- PIT_T2
- PIT_TICK_RATE
- PITn_OFFSET
- PIUINTREG
- PIUINT_COMMAND
- PIUINT_DATA
- PIUINT_DATALOST
- PIUINT_PAGE0
- PIUINT_PAGE1
- PIUINT_STATUSCHANGE
- PIU_CLOCK
- PIU_IRQ
- PIWAR_EN
- PIWAR_PF
- PIWAR_READ_SNOOP
- PIWAR_SZ_MASK
- PIWAR_TGI_LOCAL
- PIWAR_WRITE_SNOOP
- PIX
- PIX0
- PIX1
- PIX2CLK_ALWAYS_ONb
- PIX2CLK_DAC_ALWAYS_ONb
- PIX2CLK_SRC_SEL_BYTECLK
- PIX2CLK_SRC_SEL_CPUCLK
- PIX2CLK_SRC_SEL_MASK
- PIX2CLK_SRC_SEL_P2PLLCLK
- PIX2CLK_SRC_SEL_PSCANCLK
- PIXADDR
- PIXC0
- PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1
- PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF
- PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE
- PIXCENTER_D3D
- PIXCENTER_OGL
- PIXCIR_INT_DIFF_COORD
- PIXCIR_INT_ENABLE
- PIXCIR_INT_LEVEL_TOUCH
- PIXCIR_INT_MODE_MASK
- PIXCIR_INT_PERIODICAL
- PIXCIR_INT_POL_HIGH
- PIXCIR_INT_PULSE_TOUCH
- PIXCIR_MAX_SLOTS
- PIXCIR_POWER_ACTIVE
- PIXCIR_POWER_ALLOW_IDLE
- PIXCIR_POWER_HALT
- PIXCIR_POWER_IDLE
- PIXCIR_POWER_MODE_MASK
- PIXCIR_REG_INT_MODE
- PIXCIR_REG_POWER_MODE
- PIXCLK
- PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK
- PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT
- PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK
- PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT
- PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK
- PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT
- PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK
- PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT
- PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK
- PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT
- PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK
- PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT
- PIXCLKCR_PXCKDLY
- PIXCLKCR_PXCKEN
- PIXCLKCR_PXCKINV
- PIXCLKCR_PXCLK_MASK
- PIXCLKDIV
- PIXCLKDIV_PD
- PIXCLKSRC
- PIXCLKSRC_PLL_1
- PIXCLKSRC_PLL_2
- PIXCLKSRC_REF
- PIXCLKSRC_SEL
- PIXCLKS_CNTL
- PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
- PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb
- PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb
- PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIX2CLK_INVERT
- PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT
- PIXCLKS_CNTL__PIX2CLK_SRC_INVERT
- PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT
- PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK
- PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT
- PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb
- PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb
- PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb
- PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb
- PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb
- PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT
- PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL
- PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT
- PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF
- PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb
- PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb
- PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb
- PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb
- PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb
- PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb
- PIXCLK_ALWAYS_ONb
- PIXCLK_DAC_ALWAYS_ONb
- PIXCLK_EN
- PIXCLK_GATE
- PIXCLK_GATE_GATE
- PIXCLK_GATE_UNGATE
- PIXCLK_LVDS_ALWAYS_ONb
- PIXCLK_TMDS_ALWAYS_ONb
- PIXCLK_TV_SRC_SEL
- PIXCONF
- PIXCONF1
- PIXCONF15
- PIXCONF16
- PIXCONF24
- PIXCONF32
- PIXCONF8
- PIXCONF_0
- PIXCONF_1
- PIXCONF_2
- PIXCTL1
- PIXCTL2
- PIXELS_ACROSS_DEFAULT
- PIXELS_DOWN_DEFAULT
- PIXEL_BGR_RESERVED_8BIT_PER_COLOR
- PIXEL_BIT_MASK
- PIXEL_BLT
- PIXEL_BLT_ONLY
- PIXEL_BUF_OVERFLOW
- PIXEL_CLK_DIVIDER_PCD1
- PIXEL_CLK_DIVIDER_PCD12
- PIXEL_CLK_DIVIDER_PCD13
- PIXEL_CLK_DIVIDER_PCD16
- PIXEL_CLK_DIVIDER_PCD18
- PIXEL_CLK_DIVIDER_PCD1H
- PIXEL_CLK_DIVIDER_PCD2
- PIXEL_CLK_DIVIDER_PCD24
- PIXEL_CLK_DIVIDER_PCD3
- PIXEL_CLK_DIVIDER_PCD4
- PIXEL_CLK_DIVIDER_PCD6
- PIXEL_CLK_DIVIDER_PCD8
- PIXEL_CLK_DIVIDER_PCD9
- PIXEL_CLOCK
- PIXEL_CLOCK_HI
- PIXEL_CLOCK_LO
- PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1
- PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2
- PIXEL_CLOCK_MISC_CRTC_SEL_MASK
- PIXEL_CLOCK_MISC_FORCE_PROG_PPLL
- PIXEL_CLOCK_MISC_REF_DIV_SRC
- PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK
- PIXEL_CLOCK_MISC_VGA_MODE
- PIXEL_CLOCK_PARAMETERS
- PIXEL_CLOCK_PARAMETERS_LAST
- PIXEL_CLOCK_PARAMETERS_V2
- PIXEL_CLOCK_PARAMETERS_V3
- PIXEL_CLOCK_PARAMETERS_V5
- PIXEL_CLOCK_PARAMETERS_V6
- PIXEL_CLOCK_PARAMETERS_V7
- PIXEL_CLOCK_V4_MISC_COHERENT_MODE
- PIXEL_CLOCK_V4_MISC_SS_ENABLE
- PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL
- PIXEL_CLOCK_V5_MISC_HDMI_24BPP
- PIXEL_CLOCK_V5_MISC_HDMI_30BPP
- PIXEL_CLOCK_V5_MISC_HDMI_32BPP
- PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK
- PIXEL_CLOCK_V5_MISC_REF_DIV_SRC
- PIXEL_CLOCK_V5_MISC_VGA_MODE
- PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS
- PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL
- PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK
- PIXEL_CLOCK_V6_MISC_HDMI_24BPP
- PIXEL_CLOCK_V6_MISC_HDMI_30BPP
- PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6
- PIXEL_CLOCK_V6_MISC_HDMI_36BPP
- PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6
- PIXEL_CLOCK_V6_MISC_HDMI_48BPP
- PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK
- PIXEL_CLOCK_V6_MISC_REF_DIV_SRC
- PIXEL_CLOCK_V6_MISC_VGA_MODE
- PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1
- PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2
- PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4
- PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS
- PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE
- PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN
- PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL
- PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS
- PIXEL_CLOCK_V7_MISC_PROG_PHYPLL
- PIXEL_CLOCK_V7_MISC_REF_DIV_SRC
- PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK
- PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE
- PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD
- PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN
- PIXEL_CLOCK_V7_MISC_YUV420_MODE
- PIXEL_CMD
- PIXEL_DEPTH_10BPC
- PIXEL_DEPTH_18BPP
- PIXEL_DEPTH_24BPP
- PIXEL_DEPTH_30BPP
- PIXEL_DEPTH_38BPP
- PIXEL_DEPTH_8BPC
- PIXEL_ENCODING_COUNT
- PIXEL_ENCODING_RGB
- PIXEL_ENCODING_UNDEFINED
- PIXEL_ENCODING_YCBCR420
- PIXEL_ENCODING_YCBCR422
- PIXEL_ENCODING_YCBCR444
- PIXEL_ENGINE_VIP1
- PIXEL_ENGINE_VIP2
- PIXEL_EXPAN_MODE_DYN_EXP
- PIXEL_EXPAN_MODE_ZERO_EXP
- PIXEL_FORMAT
- PIXEL_FORMAT_420BPP10
- PIXEL_FORMAT_420BPP8
- PIXEL_FORMAT_ARGB2101010
- PIXEL_FORMAT_ARGB2101010_XRBIAS
- PIXEL_FORMAT_ARGB8888
- PIXEL_FORMAT_FIXED
- PIXEL_FORMAT_FIXED16
- PIXEL_FORMAT_FLOAT
- PIXEL_FORMAT_FP16
- PIXEL_FORMAT_GRPH_BEGIN
- PIXEL_FORMAT_GRPH_END
- PIXEL_FORMAT_INDEX8
- PIXEL_FORMAT_INVALID
- PIXEL_FORMAT_MAX
- PIXEL_FORMAT_RGB565
- PIXEL_FORMAT_RGB666
- PIXEL_FORMAT_RGB666_LOOSELY_PACKED
- PIXEL_FORMAT_RGB888
- PIXEL_FORMAT_RGB_444
- PIXEL_FORMAT_UNINITIALIZED
- PIXEL_FORMAT_UNKNOWN
- PIXEL_FORMAT_VIDEO_BEGIN
- PIXEL_FORMAT_VIDEO_END
- PIXEL_FORMAT_YCBCR_422
- PIXEL_FORMAT_YCBCR_444
- PIXEL_FORMAT_Y_ONLY
- PIXEL_FRMT_411
- PIXEL_FRMT_422
- PIXEL_FRMT_Y8
- PIXEL_MASK_CAMMING_DISABLE
- PIXEL_OVERLAP_CNT_MASK
- PIXEL_OVERLAP_CNT_SHIFT
- PIXEL_PIPE_OCCLUSION_COUNT_0
- PIXEL_PIPE_OCCLUSION_COUNT_1
- PIXEL_PIPE_OCCLUSION_COUNT_2
- PIXEL_PIPE_OCCLUSION_COUNT_3
- PIXEL_PIPE_SCREEN_MAX_EXTENTS_0
- PIXEL_PIPE_SCREEN_MAX_EXTENTS_1
- PIXEL_PIPE_SCREEN_MIN_EXTENTS_0
- PIXEL_PIPE_SCREEN_MIN_EXTENTS_1
- PIXEL_PIPE_STAT_CONTROL
- PIXEL_PIPE_STAT_DUMP
- PIXEL_PIPE_STAT_RESET
- PIXEL_PIPE_STRIDE_128_BITS
- PIXEL_PIPE_STRIDE_256_BITS
- PIXEL_PIPE_STRIDE_32_BITS
- PIXEL_PIPE_STRIDE_64_BITS
- PIXEL_REDUCE_MODE_ROUNDING
- PIXEL_REDUCE_MODE_TRUNCATION
- PIXEL_RGB_RESERVED_8BIT_PER_COLOR
- PIXEL_ROUNDING_TRUNC_FB_PASSTHRU
- PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
- PIXEL_TO_MM
- PIXFMT
- PIXFMT_1BPP
- PIXFMT_2BPP
- PIXFMT_4BPP
- PIXFMT_8BPP
- PIXFMT_BGR1555
- PIXFMT_BGR565
- PIXFMT_BGR888PACK
- PIXFMT_BGR888UNPACK
- PIXFMT_BGRA888
- PIXFMT_NV12
- PIXFMT_OSD_ATTR
- PIXFMT_PSEUDOCOLOR
- PIXFMT_RGB1555
- PIXFMT_RGB565
- PIXFMT_RGB666
- PIXFMT_RGB888
- PIXFMT_RGB888PACK
- PIXFMT_RGB888UNPACK
- PIXFMT_RGBA888
- PIXFMT_UYVY
- PIXFMT_VYUY
- PIXFMT_YCBCRI
- PIXFMT_YCRCBI
- PIXFMT_YUV420P
- PIXFMT_YUV422P
- PIXFMT_YUYV
- PIXFMT_YVU420P
- PIXFMT_YVU422P
- PIXM0
- PIXN0
- PIXP0
- PIXPIPE_CONFIG_0
- PIXPIPE_CONFIG_1
- PIXPIPE_CONFIG_2
- PIXSTEP
- PIX_BLT
- PIX_BUF_THRESHOLD_1_2
- PIX_BUF_THRESHOLD_1_4
- PIX_BUF_THRESHOLD_3_4
- PIX_BUF_THRESHOLD_FULL
- PIX_BUF_THRESHOLD_MASK
- PIX_BUF_THRESHOLD_SHIFT
- PIX_DYNAMIC_EXPANSION
- PIX_EXPAND_MODE
- PIX_FMT_BGR1555
- PIX_FMT_BGR565
- PIX_FMT_BGR888PACK
- PIX_FMT_BGR888UNPACK
- PIX_FMT_BGRA888
- PIX_FMT_COMPRESSED
- PIX_FMT_MASK
- PIX_FMT_PSEUDOCOLOR
- PIX_FMT_RGB101010
- PIX_FMT_RGB121212
- PIX_FMT_RGB1555
- PIX_FMT_RGB565
- PIX_FMT_RGB666_LOOSE
- PIX_FMT_RGB666_PACKED
- PIX_FMT_RGB888
- PIX_FMT_RGB888PACK
- PIX_FMT_RGB888UNPACK
- PIX_FMT_RGBA888
- PIX_FMT_SHIFT
- PIX_FMT_UYVY422PACK
- PIX_FMT_YUV420PLANAR
- PIX_FMT_YUV422PACK
- PIX_FMT_YUV422PLANAR
- PIX_FMT_YVU420PLANAR
- PIX_FMT_YVU422PACK
- PIX_FMT_YVU422PLANAR
- PIX_PIPE_DEL
- PIX_PIPE_DEL2
- PIX_REPEAT_CHROMA
- PIX_REPEAT_MASK_REP
- PIX_REPEAT_MASK_UP_SEL
- PIX_REPEAT_SHIFT
- PIX_VIRT_CHAN
- PIX_VIRT_CHAN_MASK
- PIX_VIRT_CHAN_SHIFT
- PIX_ZERO_EXPANSION
- PI_100F_PID
- PI_1011_PID
- PI_1012_PID
- PI_1013_PID
- PI_1014_PID
- PI_1015_PID
- PI_1016_PID
- PI_ALIGN_K_CMD_REQ_BUFF
- PI_ALIGN_K_CMD_RSP_BUFF
- PI_ALIGN_K_CONS_BLK
- PI_ALIGN_K_DESC_BLK
- PI_ALIGN_K_RCV_DATA_BUFF
- PI_ALIGN_K_UNSOL_BUFF
- PI_ALIGN_K_XMT_DATA_BUFF
- PI_BAD_CHECK_BIT_A
- PI_BAD_CHECK_BIT_B
- PI_BASE
- PI_BIST_COUNT_TARG
- PI_BIST_ENTER_RUN
- PI_BIST_READY
- PI_BIST_READ_DATA
- PI_BIST_SHIFT_LOAD
- PI_BIST_SHIFT_UNLOAD
- PI_BIST_WRITE_DATA
- PI_BURST_HOLDOFF_M_HOLDOFF
- PI_BURST_HOLDOFF_M_MEM_MAP
- PI_BURST_HOLDOFF_M_RESERVED
- PI_BURST_HOLDOFF_V_HOLDOFF
- PI_BURST_HOLDOFF_V_MEM_MAP
- PI_BURST_HOLDOFF_V_RESERVED
- PI_C663_PID
- PI_C725_PID
- PI_C857_PID
- PI_C863_PID
- PI_C865_PID
- PI_C866_PID
- PI_C867_PID
- PI_CALIAS_SIZE
- PI_CALIAS_SIZE_0
- PI_CALIAS_SIZE_128K
- PI_CALIAS_SIZE_16K
- PI_CALIAS_SIZE_16M
- PI_CALIAS_SIZE_1M
- PI_CALIAS_SIZE_256K
- PI_CALIAS_SIZE_2M
- PI_CALIAS_SIZE_32K
- PI_CALIAS_SIZE_32M
- PI_CALIAS_SIZE_4K
- PI_CALIAS_SIZE_4M
- PI_CALIAS_SIZE_512K
- PI_CALIAS_SIZE_64K
- PI_CALIAS_SIZE_64M
- PI_CALIAS_SIZE_8K
- PI_CALIAS_SIZE_8M
- PI_CC_MASK
- PI_CC_PEND_CLR_A
- PI_CC_PEND_CLR_B
- PI_CC_PEND_SET_A
- PI_CC_PEND_SET_B
- PI_CMD_ADDR_FILTER_GET_REQ
- PI_CMD_ADDR_FILTER_GET_RSP
- PI_CMD_ADDR_FILTER_K_SIZE
- PI_CMD_ADDR_FILTER_SET_REQ
- PI_CMD_ADDR_FILTER_SET_RSP
- PI_CMD_CHARS_SET_K_ITEMS_MAX
- PI_CMD_CHARS_SET_REQ
- PI_CMD_CHARS_SET_RSP
- PI_CMD_CNTRS_GET_REQ
- PI_CMD_CNTRS_GET_RSP
- PI_CMD_CNTRS_SET_REQ
- PI_CMD_CNTRS_SET_RSP
- PI_CMD_DEC_EXT_MIB_GET_REQ
- PI_CMD_DEC_EXT_MIB_GET_RSP
- PI_CMD_ERROR_LOG_CLEAR_REQ
- PI_CMD_ERROR_LOG_CLEAR_RSP
- PI_CMD_ERROR_LOG_GET_REQ
- PI_CMD_ERROR_LOG_GET_RSP
- PI_CMD_FDDI_MIB_GET_REQ
- PI_CMD_FDDI_MIB_GET_RSP
- PI_CMD_FILTERS_GET_REQ
- PI_CMD_FILTERS_GET_RSP
- PI_CMD_FILTERS_SET_K_ITEMS_MAX
- PI_CMD_FILTERS_SET_REQ
- PI_CMD_FILTERS_SET_RSP
- PI_CMD_K_ADDR_FILTER_GET
- PI_CMD_K_ADDR_FILTER_SET
- PI_CMD_K_CHARS_SET
- PI_CMD_K_CNTRS_GET
- PI_CMD_K_CNTRS_SET
- PI_CMD_K_DEC_EXT_MIB_GET
- PI_CMD_K_DEVICE_SPECIFIC_GET
- PI_CMD_K_ERROR_LOG_CLEAR
- PI_CMD_K_ERROR_LOG_GET
- PI_CMD_K_FDDI_MIB_GET
- PI_CMD_K_FILTERS_GET
- PI_CMD_K_FILTERS_SET
- PI_CMD_K_MAX
- PI_CMD_K_SMT_MIB_GET
- PI_CMD_K_SMT_MIB_SET
- PI_CMD_K_SNMP_SET
- PI_CMD_K_START
- PI_CMD_K_STATUS_CHARS_GET
- PI_CMD_K_UNSOL_TEST
- PI_CMD_REQ_K_NUM_ENTRIES
- PI_CMD_REQ_K_SIZE_MAX
- PI_CMD_RSP_K_NUM_ENTRIES
- PI_CMD_RSP_K_SIZE_MAX
- PI_CMD_SMT_MIB_GET_REQ
- PI_CMD_SMT_MIB_GET_RSP
- PI_CMD_SMT_MIB_SET_K_ITEMS_MAX
- PI_CMD_SMT_MIB_SET_REQ
- PI_CMD_SMT_MIB_SET_RSP
- PI_CMD_SNMP_SET_K_ITEMS_MAX
- PI_CMD_SNMP_SET_REQ
- PI_CMD_SNMP_SET_RSP
- PI_CMD_START_REQ
- PI_CMD_START_RSP
- PI_CMD_STATUS_CHARS_GET_REQ
- PI_CMD_STATUS_CHARS_GET_RSP
- PI_CNTR
- PI_CNTR_BLK
- PI_CONFIG_STAT_0_IRQ_K_10
- PI_CONFIG_STAT_0_IRQ_K_11
- PI_CONFIG_STAT_0_IRQ_K_15
- PI_CONFIG_STAT_0_IRQ_K_9
- PI_CONFIG_STAT_0_M_INT_ENB
- PI_CONFIG_STAT_0_M_IREQ_IN
- PI_CONFIG_STAT_0_M_IREQ_OUT
- PI_CONFIG_STAT_0_M_IRQ
- PI_CONFIG_STAT_0_M_PEND
- PI_CONFIG_STAT_0_M_RES_0
- PI_CONFIG_STAT_0_M_RES_1
- PI_CONFIG_STAT_0_V_INT_ENB
- PI_CONFIG_STAT_0_V_IREQ_IN
- PI_CONFIG_STAT_0_V_IREQ_OUT
- PI_CONFIG_STAT_0_V_IRQ
- PI_CONFIG_STAT_0_V_PEND
- PI_CONFIG_STAT_0_V_RES_0
- PI_CONFIG_STAT_0_V_RES_1
- PI_CONSUMER_BLOCK
- PI_CONS_BLK_K_CMD_REQ
- PI_CONS_BLK_K_CMD_RSP
- PI_CONS_BLK_K_SMT_HOST
- PI_CONS_BLK_K_UNSOL
- PI_CONS_BLK_K_XMT_RCV
- PI_CONS_M_RCV_INDEX
- PI_CONS_M_XMT_INDEX
- PI_CONS_V_RCV_INDEX
- PI_CONS_V_XMT_INDEX
- PI_COUNT_OFFSET
- PI_CPU_ENABLE_A
- PI_CPU_ENABLE_B
- PI_CPU_NUM
- PI_CPU_PRESENT_A
- PI_CPU_PRESENT_B
- PI_CPU_PROTECT
- PI_CRB_SFACTOR
- PI_CRB_TIMEOUT_A
- PI_CRB_TIMEOUT_B
- PI_DATA_REG
- PI_DEFEA_K_BURST_HOLDOFF
- PI_DEFEA_K_CSR_IO
- PI_DESCR_BLK_K_CMD_REQ
- PI_DESCR_BLK_K_CMD_RSP
- PI_DESCR_BLK_K_RCV_DATA
- PI_DESCR_BLK_K_SMT_HOST
- PI_DESCR_BLK_K_UNSOL
- PI_DESCR_BLK_K_XMT_DATA
- PI_DESCR_BLOCK
- PI_DMA_CMD_BUFFER
- PI_DMA_CMD_REQ
- PI_DMA_CMD_RSP
- PI_DREQ_MASK
- PI_E517_PID
- PI_E609_PID
- PI_E709_PID
- PI_E861_PID
- PI_ERRSTAT_OFFSET
- PI_ERR_ANY_CRB
- PI_ERR_BAD_SPOOL_A
- PI_ERR_BAD_SPOOL_B
- PI_ERR_CLEAR_ALL_A
- PI_ERR_CLEAR_ALL_B
- PI_ERR_GENERIC
- PI_ERR_INT_MASK_A
- PI_ERR_INT_MASK_B
- PI_ERR_INT_PEND
- PI_ERR_MD_UNCORR
- PI_ERR_RD_DERR
- PI_ERR_RD_PRERR
- PI_ERR_RD_TERR
- PI_ERR_RRB
- PI_ERR_SPOOL_CMP_A
- PI_ERR_SPOOL_CMP_B
- PI_ERR_SPUR_MSG_A
- PI_ERR_SPUR_MSG_B
- PI_ERR_ST0_ADDR_MASK
- PI_ERR_ST0_ADDR_SHFT
- PI_ERR_ST0_CMD_MASK
- PI_ERR_ST0_CMD_SHFT
- PI_ERR_ST0_OVERRUN_MASK
- PI_ERR_ST0_OVERRUN_SHFT
- PI_ERR_ST0_REQNUM_MASK
- PI_ERR_ST0_REQNUM_SHFT
- PI_ERR_ST0_SUPPL_MASK
- PI_ERR_ST0_SUPPL_SHFT
- PI_ERR_ST0_TYPE_MASK
- PI_ERR_ST0_TYPE_SHFT
- PI_ERR_ST0_VALID_MASK
- PI_ERR_ST0_VALID_SHFT
- PI_ERR_ST1_CRBNUM_MASK
- PI_ERR_ST1_CRBNUM_SHFT
- PI_ERR_ST1_CRBSTAT_MASK
- PI_ERR_ST1_CRBSTAT_SHFT
- PI_ERR_ST1_INVCNT_MASK
- PI_ERR_ST1_INVCNT_SHFT
- PI_ERR_ST1_MSGSRC_MASK
- PI_ERR_ST1_MSGSRC_SHFT
- PI_ERR_ST1_SPOOL_MASK
- PI_ERR_ST1_SPOOL_SHFT
- PI_ERR_ST1_TOUTCNT_MASK
- PI_ERR_ST1_TOUTCNT_SHFT
- PI_ERR_ST1_WRBRRB_MASK
- PI_ERR_ST1_WRBRRB_SHFT
- PI_ERR_STACK_ADDR_A
- PI_ERR_STACK_ADDR_B
- PI_ERR_STACK_SIZE
- PI_ERR_STATUS0_A
- PI_ERR_STATUS0_A_RCLR
- PI_ERR_STATUS0_B
- PI_ERR_STATUS0_B_RCLR
- PI_ERR_STATUS1_A
- PI_ERR_STATUS1_A_RCLR
- PI_ERR_STATUS1_B
- PI_ERR_STATUS1_B_RCLR
- PI_ERR_STK_ADDR_MASK
- PI_ERR_STK_ADDR_SHFT
- PI_ERR_STK_CMD_MASK
- PI_ERR_STK_CMD_SHFT
- PI_ERR_STK_CRBNUM_MASK
- PI_ERR_STK_CRBNUM_SHFT
- PI_ERR_STK_CRBSTAT_MASK
- PI_ERR_STK_CRBSTAT_SHFT
- PI_ERR_STK_REQNUM_MASK
- PI_ERR_STK_REQNUM_SHFT
- PI_ERR_STK_SUPPL_MASK
- PI_ERR_STK_SUPPL_SHFT
- PI_ERR_STK_TYPE_MASK
- PI_ERR_STK_TYPE_SHFT
- PI_ERR_STK_WRBRRB_MASK
- PI_ERR_STK_WRBRRB_SHFT
- PI_ERR_SYSAD_ADDR_A
- PI_ERR_SYSAD_ADDR_B
- PI_ERR_SYSAD_DATA_A
- PI_ERR_SYSAD_DATA_B
- PI_ERR_SYSCMD_ADDR_A
- PI_ERR_SYSCMD_ADDR_B
- PI_ERR_SYSCMD_DATA_A
- PI_ERR_SYSCMD_DATA_B
- PI_ERR_SYSSTATE_A
- PI_ERR_SYSSTATE_B
- PI_ERR_SYSSTATE_TAG_A
- PI_ERR_SYSSTATE_TAG_B
- PI_ERR_UNCAC_UNCORR_A
- PI_ERR_UNCAC_UNCORR_B
- PI_ERR_WRB
- PI_ERR_WRB_TERR_A
- PI_ERR_WRB_TERR_B
- PI_ERR_WRB_WERR_A
- PI_ERR_WRB_WERR_B
- PI_ERR_WR_PWERR
- PI_ERR_WR_TERR
- PI_ERR_WR_WERR
- PI_ESIC_K_BURST_HOLDOFF_LEN
- PI_ESIC_K_CSR_IO_LEN
- PI_ESIC_K_DIP_SWITCH
- PI_ESIC_K_DMA_CONFIG
- PI_ESIC_K_ESIC_CSR
- PI_ESIC_K_ESIC_CSR_LEN
- PI_ESIC_K_FUNCTION_CNTRL
- PI_ESIC_K_INPUT_PORT
- PI_ESIC_K_IO_ADD_CMP_0_0
- PI_ESIC_K_IO_ADD_CMP_0_1
- PI_ESIC_K_IO_ADD_CMP_1_0
- PI_ESIC_K_IO_ADD_CMP_1_1
- PI_ESIC_K_IO_ADD_CMP_2_0
- PI_ESIC_K_IO_ADD_CMP_2_1
- PI_ESIC_K_IO_ADD_CMP_3_0
- PI_ESIC_K_IO_ADD_CMP_3_1
- PI_ESIC_K_IO_ADD_MASK_0_0
- PI_ESIC_K_IO_ADD_MASK_0_1
- PI_ESIC_K_IO_ADD_MASK_1_0
- PI_ESIC_K_IO_ADD_MASK_1_1
- PI_ESIC_K_IO_ADD_MASK_2_0
- PI_ESIC_K_IO_ADD_MASK_2_1
- PI_ESIC_K_IO_ADD_MASK_3_0
- PI_ESIC_K_IO_ADD_MASK_3_1
- PI_ESIC_K_IO_CONFIG_STAT_0
- PI_ESIC_K_IO_CONFIG_STAT_1
- PI_ESIC_K_MEM_ADD_CMP_0
- PI_ESIC_K_MEM_ADD_CMP_1
- PI_ESIC_K_MEM_ADD_CMP_2
- PI_ESIC_K_MEM_ADD_HI_CMP_0
- PI_ESIC_K_MEM_ADD_HI_CMP_1
- PI_ESIC_K_MEM_ADD_HI_CMP_2
- PI_ESIC_K_MEM_ADD_LO_CMP_0
- PI_ESIC_K_MEM_ADD_LO_CMP_1
- PI_ESIC_K_MEM_ADD_LO_CMP_2
- PI_ESIC_K_MEM_ADD_MASK_0
- PI_ESIC_K_MEM_ADD_MASK_1
- PI_ESIC_K_MEM_ADD_MASK_2
- PI_ESIC_K_MOD_CONFIG_1
- PI_ESIC_K_MOD_CONFIG_2
- PI_ESIC_K_MOD_CONFIG_3
- PI_ESIC_K_MOD_CONFIG_4
- PI_ESIC_K_MOD_CONFIG_5
- PI_ESIC_K_MOD_CONFIG_6
- PI_ESIC_K_MOD_CONFIG_7
- PI_ESIC_K_OUTPUT_PORT
- PI_ESIC_K_SLOT_CNTRL
- PI_ESIC_K_SLOT_ID
- PI_FATAL_ERR_CPU_A
- PI_FATAL_ERR_CPU_B
- PI_FMC_DESCR_K_DD_CAM_MATCH
- PI_FMC_DESCR_K_DD_LOCAL_MATCH
- PI_FMC_DESCR_K_DD_NO_MATCH
- PI_FMC_DESCR_K_DD_PROMISCUOUS
- PI_FMC_DESCR_K_RCC_FMC_INT_ERR
- PI_FMC_DESCR_K_RRR_DA_MATCH
- PI_FMC_DESCR_K_RRR_FMC_ABORT
- PI_FMC_DESCR_K_RRR_FORMAT_ERR
- PI_FMC_DESCR_K_RRR_FRAGMENT
- PI_FMC_DESCR_K_RRR_LENGTH_BAD
- PI_FMC_DESCR_K_RRR_MAC_RESET
- PI_FMC_DESCR_K_RRR_SA_MATCH
- PI_FMC_DESCR_K_RRR_SUCCESS
- PI_FMC_DESCR_K_SS_BRIDGE_MATCH
- PI_FMC_DESCR_K_SS_LOCAL_MATCH
- PI_FMC_DESCR_K_SS_NOT_POSSIBLE
- PI_FMC_DESCR_K_SS_NO_MATCH
- PI_FMC_DESCR_M_EOP
- PI_FMC_DESCR_M_FSB
- PI_FMC_DESCR_M_FSB_ADDR_COPIED
- PI_FMC_DESCR_M_FSB_ADDR_RECOG
- PI_FMC_DESCR_M_FSB_ERROR
- PI_FMC_DESCR_M_FSC
- PI_FMC_DESCR_M_LEN
- PI_FMC_DESCR_M_RCC
- PI_FMC_DESCR_M_RCC_CRC
- PI_FMC_DESCR_M_RCC_DD
- PI_FMC_DESCR_M_RCC_FLUSH
- PI_FMC_DESCR_M_RCC_RRR
- PI_FMC_DESCR_M_RCC_SS
- PI_FMC_DESCR_M_SOP
- PI_FMC_DESCR_V_EOP
- PI_FMC_DESCR_V_FSB
- PI_FMC_DESCR_V_FSB_ADDR_COPIED
- PI_FMC_DESCR_V_FSB_ADDR_RECOG
- PI_FMC_DESCR_V_FSB_ERROR
- PI_FMC_DESCR_V_FSC
- PI_FMC_DESCR_V_LEN
- PI_FMC_DESCR_V_RCC
- PI_FMC_DESCR_V_RCC_CRC
- PI_FMC_DESCR_V_RCC_DD
- PI_FMC_DESCR_V_RCC_FLUSH
- PI_FMC_DESCR_V_RCC_RRR
- PI_FMC_DESCR_V_RCC_SS
- PI_FMC_DESCR_V_SOP
- PI_FSTATE_K_BLOCK
- PI_FSTATE_K_PASS
- PI_FUNCTION_CNTRL_M_DMA
- PI_FUNCTION_CNTRL_M_IOCS0
- PI_FUNCTION_CNTRL_M_IOCS1
- PI_FUNCTION_CNTRL_M_IOCS2
- PI_FUNCTION_CNTRL_M_IOCS3
- PI_FUNCTION_CNTRL_M_MEMCS0
- PI_FUNCTION_CNTRL_M_MEMCS1
- PI_GFX_BIAS_A
- PI_GFX_BIAS_B
- PI_GFX_CREDIT_CNTR_A
- PI_GFX_CREDIT_CNTR_B
- PI_GFX_INT_CMP_A
- PI_GFX_INT_CMP_B
- PI_GFX_INT_CNTR_A
- PI_GFX_INT_CNTR_B
- PI_GFX_OFFSET
- PI_GFX_PAGE_A
- PI_GFX_PAGE_B
- PI_GFX_PAGE_ENABLE
- PI_GRP_K_MAC_ADDRESS
- PI_GRP_K_MAC_CAPABILITIES
- PI_GRP_K_MAC_CONFIG
- PI_GRP_K_MAC_COUNTERS
- PI_GRP_K_MAC_FRM_ERR_COND
- PI_GRP_K_MAC_OPERATION
- PI_GRP_K_MAC_STATUS
- PI_GRP_K_PATH_CONFIG
- PI_GRP_K_PORT_CONFIG
- PI_GRP_K_PORT_ERR_CNTRS
- PI_GRP_K_PORT_LER
- PI_GRP_K_PORT_OPERATION
- PI_GRP_K_PORT_STATUS
- PI_GRP_K_SMT_MIB_OPERATION
- PI_GRP_K_SMT_STATION_CONFIG
- PI_GRP_K_SMT_STATION_ID
- PI_GRP_K_SMT_STATUS
- PI_HALT_ID_K_BUS_EXCEPTION
- PI_HALT_ID_K_DMA_ERROR
- PI_HALT_ID_K_HOST_DIR_HALT
- PI_HALT_ID_K_HW_FAULT
- PI_HALT_ID_K_IMAGE_CRC_ERROR
- PI_HALT_ID_K_PARITY_ERROR
- PI_HALT_ID_K_PC_TRACE
- PI_HALT_ID_K_SELFTEST_TIMEOUT
- PI_HALT_ID_K_SW_FAULT
- PI_HARDRESET_BIT
- PI_HOST_INT_K_ACK_ALL_TYPE_0
- PI_HOST_INT_K_DISABLE_ALL_INTS
- PI_HOST_INT_K_ENABLE_ALL_INTS
- PI_HOST_INT_K_ENABLE_DEF_INTS
- PI_HOST_INT_M_1MS
- PI_HOST_INT_M_20MS
- PI_HOST_INT_M_BUS_PAR_ERR
- PI_HOST_INT_M_CMD_REQ_ENB
- PI_HOST_INT_M_CMD_RSP_ENB
- PI_HOST_INT_M_CSR_CMD_DONE
- PI_HOST_INT_M_NXM
- PI_HOST_INT_M_PM_PAR_ERR
- PI_HOST_INT_M_RCV_DATA_ENB
- PI_HOST_INT_M_SMT_HOST_ENB
- PI_HOST_INT_M_STATE_CHANGE
- PI_HOST_INT_M_TYPE_0_RESERVED
- PI_HOST_INT_M_TYPE_1_RESERVED
- PI_HOST_INT_M_UNSOL_ENB
- PI_HOST_INT_M_XMT_DATA_ENB
- PI_HOST_INT_M_XMT_FLUSH
- PI_HOST_INT_V_1MS_ENB
- PI_HOST_INT_V_20MS_ENB
- PI_HOST_INT_V_BUS_PAR_ERR_ENB
- PI_HOST_INT_V_CMD_REQ_ENB
- PI_HOST_INT_V_CMD_RSP_ENB
- PI_HOST_INT_V_CSR_CMD_DONE_ENB
- PI_HOST_INT_V_NXM_ENB
- PI_HOST_INT_V_PM_PAR_ERR_ENB
- PI_HOST_INT_V_RCV_DATA_ENB
- PI_HOST_INT_V_SMT_HOST_ENB
- PI_HOST_INT_V_STATE_CHANGE_ENB
- PI_HOST_INT_V_TYPE_0_RESERVED
- PI_HOST_INT_V_TYPE_1_RESERVED
- PI_HOST_INT_V_UNSOL_ENB
- PI_HOST_INT_V_XMT_DATA_ENB
- PI_HOST_INT_V_XMT_FLUSH_ENB
- PI_INT_MASK0_A
- PI_INT_MASK0_B
- PI_INT_MASK1_A
- PI_INT_MASK1_B
- PI_INT_MASK_OFFSET
- PI_INT_PEND0
- PI_INT_PEND1
- PI_INT_PEND_MOD
- PI_INT_SET_OFFSET
- PI_IO_CMP_M_SLOT
- PI_IO_CMP_V_SLOT
- PI_IO_PROTECT
- PI_ITEM_K_BROADCAST
- PI_ITEM_K_CNTR_INTERVAL
- PI_ITEM_K_CONFIG_POLICY
- PI_ITEM_K_CON_POLICIES
- PI_ITEM_K_CON_POLICY
- PI_ITEM_K_EMAC_RING_PURGER
- PI_ITEM_K_EMAC_RTOKEN_TIMEOUT
- PI_ITEM_K_EOL
- PI_ITEM_K_FDX_ENB_DIS
- PI_ITEM_K_FLUSH_TIME
- PI_ITEM_K_GROUP_PROM
- PI_ITEM_K_IMPLEMENTOR
- PI_ITEM_K_IND_GROUP_PROM
- PI_ITEM_K_LEM_THRESHOLD
- PI_ITEM_K_LER_ALARM
- PI_ITEM_K_LER_CUTOFF
- PI_ITEM_K_LOOPBACK_MODE
- PI_ITEM_K_MAC_ACTION
- PI_ITEM_K_MAC_AVAIL_PATHS
- PI_ITEM_K_MAC_COPIED_CT
- PI_ITEM_K_MAC_CURRENT_PATH
- PI_ITEM_K_MAC_DA_FLAG
- PI_ITEM_K_MAC_DOWN_NBR
- PI_ITEM_K_MAC_DOWN_PORT_TYPE
- PI_ITEM_K_MAC_DUP_ADDR_TEST
- PI_ITEM_K_MAC_ERROR_CT
- PI_ITEM_K_MAC_FRAME_CT
- PI_ITEM_K_MAC_FRM_ERR_FLAG
- PI_ITEM_K_MAC_FRM_ERR_RAT
- PI_ITEM_K_MAC_FRM_ERR_THR
- PI_ITEM_K_MAC_FRM_STAT_FUNC
- PI_ITEM_K_MAC_HW_PRESENT
- PI_ITEM_K_MAC_INDEX
- PI_ITEM_K_MAC_LOOP_TIME
- PI_ITEM_K_MAC_LOST_CT
- PI_ITEM_K_MAC_MA_UNIT_AVAIL
- PI_ITEM_K_MAC_MA_UNIT_ENAB
- PI_ITEM_K_MAC_OLD_DOWN_NBR
- PI_ITEM_K_MAC_OLD_UP_NBR
- PI_ITEM_K_MAC_PATHS_REQ
- PI_ITEM_K_MAC_REQ_PATHS
- PI_ITEM_K_MAC_RMT_STATE
- PI_ITEM_K_MAC_SMT_ADDRESS
- PI_ITEM_K_MAC_TMAX
- PI_ITEM_K_MAC_TNEG
- PI_ITEM_K_MAC_TRANSMIT_CT
- PI_ITEM_K_MAC_TREQ
- PI_ITEM_K_MAC_TVX_CAP
- PI_ITEM_K_MAC_TVX_VALUE
- PI_ITEM_K_MAC_T_MAX_CAP
- PI_ITEM_K_MAC_T_REQ
- PI_ITEM_K_MAC_UNDA_FLAG
- PI_ITEM_K_MAC_UP_NBR
- PI_ITEM_K_MAX
- PI_ITEM_K_PATH_CONFIGURATION
- PI_ITEM_K_PATH_INDEX
- PI_ITEM_K_PATH_MAX_T_REQ
- PI_ITEM_K_PATH_TVX_LB
- PI_ITEM_K_PATH_T_MAX_LB
- PI_ITEM_K_PORT_ACT
- PI_ITEM_K_PORT_ACTION
- PI_ITEM_K_PORT_AVAIL_PATHS
- PI_ITEM_K_PORT_BS_FLAG
- PI_ITEM_K_PORT_CONNECT_STATE
- PI_ITEM_K_PORT_CONN_CAPS
- PI_ITEM_K_PORT_CONN_POLS
- PI_ITEM_K_PORT_CURRENT_PATH
- PI_ITEM_K_PORT_HW_PRESENT
- PI_ITEM_K_PORT_INDEX
- PI_ITEM_K_PORT_LCT_FAIL_CT
- PI_ITEM_K_PORT_LEM_CT
- PI_ITEM_K_PORT_LEM_REJ_CT
- PI_ITEM_K_PORT_LER_ALARM
- PI_ITEM_K_PORT_LER_CUTOFF
- PI_ITEM_K_PORT_LER_ESTIMATE
- PI_ITEM_K_PORT_LER_FLAG
- PI_ITEM_K_PORT_MAC_INDICATED
- PI_ITEM_K_PORT_MAC_PLACEMENT
- PI_ITEM_K_PORT_MY_TYPE
- PI_ITEM_K_PORT_NBR_TYPE
- PI_ITEM_K_PORT_PATHS_REQ
- PI_ITEM_K_PORT_PCM_STATE
- PI_ITEM_K_PORT_PC_WITHHOLD
- PI_ITEM_K_PORT_PMD_CLASS
- PI_ITEM_K_PORT_REQ_PATHS
- PI_ITEM_K_RESERVED
- PI_ITEM_K_RESTRICTED_TOKEN
- PI_ITEM_K_RING_PURGER
- PI_ITEM_K_SMT_AVAIL_PATHS
- PI_ITEM_K_SMT_BYPASS_PRESENT
- PI_ITEM_K_SMT_CF_STATE
- PI_ITEM_K_SMT_CONFIG_CAPS
- PI_ITEM_K_SMT_CONFIG_POL
- PI_ITEM_K_SMT_CONN_POL
- PI_ITEM_K_SMT_ECM_STATE
- PI_ITEM_K_SMT_HI_VERS_ID
- PI_ITEM_K_SMT_LO_VERS_ID
- PI_ITEM_K_SMT_MAC_CT
- PI_ITEM_K_SMT_MAC_INDEXES
- PI_ITEM_K_SMT_MASTER_CT
- PI_ITEM_K_SMT_MIB_VERS_ID
- PI_ITEM_K_SMT_MSG_TIME_STAMP
- PI_ITEM_K_SMT_NON_MASTER_CT
- PI_ITEM_K_SMT_OP_VERS_ID
- PI_ITEM_K_SMT_PEER_WRAP_FLAG
- PI_ITEM_K_SMT_PORT_INDEXES
- PI_ITEM_K_SMT_PROM
- PI_ITEM_K_SMT_REM_DISC_FLAG
- PI_ITEM_K_SMT_STATION_ACT
- PI_ITEM_K_SMT_STATION_ID
- PI_ITEM_K_SMT_STATION_STATUS
- PI_ITEM_K_SMT_STAT_POL
- PI_ITEM_K_SMT_TRN_TIME_STAMP
- PI_ITEM_K_SMT_TR_MAX_EXP
- PI_ITEM_K_SMT_T_NOTIFY
- PI_ITEM_K_SMT_USER
- PI_ITEM_K_SMT_USER_DATA
- PI_ITEM_K_STATION_ACTION
- PI_ITEM_K_TB_MAX
- PI_ITEM_K_TVX
- PI_ITEM_K_T_NOTIFY
- PI_ITEM_K_T_REQ
- PI_ITEM_LIST
- PI_K_FALSE
- PI_K_LOG_DIAG_SIZE
- PI_K_LOG_FW_SIZE
- PI_K_TRUE
- PI_LAN_ADDR
- PI_LOG_CALLER_ID_K_CNS_FW
- PI_LOG_CALLER_ID_K_CNS_HW
- PI_LOG_CALLER_ID_K_CONSOLE
- PI_LOG_CALLER_ID_K_FW
- PI_LOG_CALLER_ID_K_HW
- PI_LOG_CALLER_ID_K_MFG
- PI_LOG_CALLER_ID_K_NONE
- PI_LOG_CALLER_ID_K_ONLINE
- PI_LOG_CALLER_ID_K_SELFTEST
- PI_LOG_ENTRY
- PI_LOG_ENTRY_K_INDEX_MIN
- PI_LOG_EVENT_STATUS_K_INVALID
- PI_LOG_EVENT_STATUS_K_VALID
- PI_MAX_CRB_TIMEOUT
- PI_MEM_ADD_MASK_M
- PI_MIN_STACK_SIZE
- PI_MISC_ERR_CPU_A
- PI_MISC_ERR_CPU_B
- PI_NACK_CMP
- PI_NACK_CNT_A
- PI_NACK_CNT_B
- PI_NACK_CNT_EN_MASK
- PI_NACK_CNT_EN_SHFT
- PI_NACK_CNT_MASK
- PI_NACK_CNT_MAX
- PI_NMI_A
- PI_NMI_B
- PI_NMI_OFFSET
- PI_PAGE_MASK
- PI_PAGE_SIZE
- PI_PCD
- PI_PCTRL_M_BLAST_FLASH
- PI_PCTRL_M_CMD_ERROR
- PI_PCTRL_M_CONS_BLOCK
- PI_PCTRL_M_COPY_DATA
- PI_PCTRL_M_DEV_SPECIFIC
- PI_PCTRL_M_ERROR_LOG_READ
- PI_PCTRL_M_ERROR_LOG_START
- PI_PCTRL_M_FW_REV_READ
- PI_PCTRL_M_HALT
- PI_PCTRL_M_INIT
- PI_PCTRL_M_INIT_START
- PI_PCTRL_M_MLA
- PI_PCTRL_M_RING_MEMBER
- PI_PCTRL_M_SUB_CMD
- PI_PCTRL_M_UNINIT
- PI_PCTRL_M_XMT_DATA_FLUSH_DONE
- PI_PD
- PI_PDATA_A_INIT_M_BSWAP_DATA
- PI_PDATA_A_INIT_M_BSWAP_INIT
- PI_PDATA_A_INIT_M_BSWAP_LITERAL
- PI_PDATA_A_INIT_M_DESC_BLK_ADDR
- PI_PDATA_A_INIT_M_RESERVED
- PI_PDATA_A_INIT_V_BSWAP_DATA
- PI_PDATA_A_INIT_V_BSWAP_LITERAL
- PI_PDATA_A_INIT_V_DESC_BLK_ADDR
- PI_PDATA_A_INIT_V_RESERVED
- PI_PDATA_A_MLA_K_HI
- PI_PDATA_A_MLA_K_LO
- PI_PDATA_A_RESET_M_SKIP_ST
- PI_PDATA_A_RESET_M_SOFT_RESET
- PI_PDATA_A_RESET_M_UPGRADE
- PI_PDATA_B_DMA_BURST_SIZE_16
- PI_PDATA_B_DMA_BURST_SIZE_32
- PI_PDATA_B_DMA_BURST_SIZE_4
- PI_PDATA_B_DMA_BURST_SIZE_8
- PI_PDATA_B_DMA_BURST_SIZE_DEF
- PI_PDQ_K_REG_CMD_REQ_PROD
- PI_PDQ_K_REG_CMD_RSP_PROD
- PI_PDQ_K_REG_HOST_DATA
- PI_PDQ_K_REG_HOST_INT_ENB
- PI_PDQ_K_REG_PORT_CTRL
- PI_PDQ_K_REG_PORT_DATA_A
- PI_PDQ_K_REG_PORT_DATA_B
- PI_PDQ_K_REG_PORT_RESET
- PI_PDQ_K_REG_PORT_STATUS
- PI_PDQ_K_REG_SMT_HOST_PROD
- PI_PDQ_K_REG_TYPE_0_STATUS
- PI_PDQ_K_REG_TYPE_2_PROD
- PI_PDQ_K_REG_TYPE_2_PROD_NOINT
- PI_PDQ_K_REG_UNSOL_PROD
- PI_PF
- PI_PG
- PI_PHY_K_A
- PI_PHY_K_B
- PI_PHY_K_MAX
- PI_PHY_K_S
- PI_PROFILE_COMPARE
- PI_PROF_EN_A
- PI_PROF_EN_B
- PI_PROF_PEND_A
- PI_PROF_PEND_B
- PI_PROT_OVERRD
- PI_PSTATUS_M_CMD_REQ_PENDING
- PI_PSTATUS_M_CMD_RSP_PENDING
- PI_PSTATUS_M_HALT_ID
- PI_PSTATUS_M_RCV_DATA_PENDING
- PI_PSTATUS_M_RESERVED_1
- PI_PSTATUS_M_RESERVED_2
- PI_PSTATUS_M_SMT_HOST_PENDING
- PI_PSTATUS_M_STATE
- PI_PSTATUS_M_TYPE_0_PENDING
- PI_PSTATUS_M_UNSOL_PENDING
- PI_PSTATUS_M_XMT_DATA_PENDING
- PI_PSTATUS_V_CMD_REQ_PENDING
- PI_PSTATUS_V_CMD_RSP_PENDING
- PI_PSTATUS_V_HALT_ID
- PI_PSTATUS_V_RCV_DATA_PENDING
- PI_PSTATUS_V_RESERVED_1
- PI_PSTATUS_V_RESERVED_2
- PI_PSTATUS_V_SMT_HOST_PENDING
- PI_PSTATUS_V_STATE
- PI_PSTATUS_V_TYPE_0_PENDING
- PI_PSTATUS_V_UNSOL_PENDING
- PI_PSTATUS_V_XMT_DATA_PENDING
- PI_PT
- PI_RCV_DATA_K_NUM_ENTRIES
- PI_RCV_DATA_K_SIZE_MAX
- PI_RCV_DESCR
- PI_RCV_DESCR_M_BUFF_HI
- PI_RCV_DESCR_M_MBZ
- PI_RCV_DESCR_M_SEG_CNT
- PI_RCV_DESCR_M_SEG_LEN
- PI_RCV_DESCR_M_SEG_LEN_HI
- PI_RCV_DESCR_M_SEG_LEN_LO
- PI_RCV_DESCR_M_SOP
- PI_RCV_DESCR_V_BUFF_HI
- PI_RCV_DESCR_V_MBZ
- PI_RCV_DESCR_V_SEG_CNT
- PI_RCV_DESCR_V_SEG_LEN
- PI_RCV_DESCR_V_SEG_LEN_HI
- PI_RCV_DESCR_V_SEG_LEN_LO
- PI_RCV_DESCR_V_SOP
- PI_RDCLR_OFFSET
- PI_REGION_PRESENT
- PI_REPLY_LEVEL
- PI_RESET_M_ASSERT_RESET
- PI_RSP_HEADER
- PI_RSP_K_ADAPTER_STATE_BAD
- PI_RSP_K_CMD_TYPE_BAD
- PI_RSP_K_CONFIG_POLICY_BAD
- PI_RSP_K_CON_POLICIES_BAD
- PI_RSP_K_EMAC_RING_PURGER_BAD
- PI_RSP_K_EMAC_RTOKEN_TIME_BAD
- PI_RSP_K_FAILURE
- PI_RSP_K_FDX_ENB_DIS_BAD
- PI_RSP_K_FILTER_STATE_BAD
- PI_RSP_K_FLUSH_TIME_BAD
- PI_RSP_K_ITEM_CODE_BAD
- PI_RSP_K_ITEM_INDEX_BAD
- PI_RSP_K_LEM_THRESHOLD_BAD
- PI_RSP_K_LER_ALARM_BAD
- PI_RSP_K_LER_CUTOFF_BAD
- PI_RSP_K_LOOP_MODE_BAD
- PI_RSP_K_LOOP_NOT_SUPPORTED
- PI_RSP_K_MAC_ACTION_BAD
- PI_RSP_K_MAC_FRM_ERR_THR_BAD
- PI_RSP_K_MAC_LOOP_TIME_BAD
- PI_RSP_K_MAC_PATHS_REQ_BAD
- PI_RSP_K_MAC_T_REQ_BAD
- PI_RSP_K_MAX_T_REQ_BAD
- PI_RSP_K_NOT_IMPLEMENTED
- PI_RSP_K_NO_EOL
- PI_RSP_K_NO_SUCH_ENTRY
- PI_RSP_K_PORT_ACTION_BAD
- PI_RSP_K_RING_PURGER_BAD
- PI_RSP_K_STATION_ACTION_BAD
- PI_RSP_K_SUCCESS
- PI_RSP_K_TB_MAX_BAD
- PI_RSP_K_TOKEN_BAD
- PI_RSP_K_TREQ_BAD
- PI_RSP_K_TR_MAX_EXP_BAD
- PI_RSP_K_TVX_BAD
- PI_RSP_K_T_NOTIFY_BAD
- PI_RSP_K_WARNING
- PI_RT_COMPARE_A
- PI_RT_COMPARE_B
- PI_RT_COUNT
- PI_RT_EN_A
- PI_RT_EN_B
- PI_RT_FILTER_CTRL
- PI_RT_LOCAL_CTRL
- PI_RT_PEND_A
- PI_RT_PEND_B
- PI_SET
- PI_SLOT_CNTRL_M_ENB
- PI_SLOT_CNTRL_M_ERROR
- PI_SLOT_CNTRL_M_RESET
- PI_SMT_HOST_K_NUM_ENTRIES
- PI_SMT_HOST_K_SIZE_MAX
- PI_SNMP_K_FALSE
- PI_SNMP_K_TRUE
- PI_SOFTRESET
- PI_SPOOL_CMP_A
- PI_SPOOL_CMP_B
- PI_STACKADDR_OFFSET
- PI_STACK_SIZE_SHFT
- PI_STATE_K_DMA_AVAIL
- PI_STATE_K_DMA_UNAVAIL
- PI_STATE_K_HALTED
- PI_STATE_K_LINK_AVAIL
- PI_STATE_K_LINK_UNAVAIL
- PI_STATE_K_NUMBER
- PI_STATE_K_RESET
- PI_STATE_K_RING_MEMBER
- PI_STATE_K_UPGRADE
- PI_STATION_ID
- PI_SUB_CMD_K_BURST_SIZE_SET
- PI_SUB_CMD_K_HW_REV_GET
- PI_SUB_CMD_K_LINK_UNINIT
- PI_SUB_CMD_K_PDQ_REV_GET
- PI_SYSAD_CHECK_ALL
- PI_SYSAD_ERRCHK_CMDP
- PI_SYSAD_ERRCHK_ECCGEN
- PI_SYSAD_ERRCHK_EN
- PI_SYSAD_ERRCHK_QUAL
- PI_SYSAD_ERRCHK_QUALGEN
- PI_SYSAD_ERRCHK_SADP
- PI_SYSAD_ERRCHK_STATE
- PI_TC_K_CSR_LEN
- PI_TC_K_CSR_OFFSET
- PI_TYPE_0_STAT_M_1MS
- PI_TYPE_0_STAT_M_20MS
- PI_TYPE_0_STAT_M_BUS_PAR_ERR
- PI_TYPE_0_STAT_M_CSR_CMD_DONE
- PI_TYPE_0_STAT_M_NXM
- PI_TYPE_0_STAT_M_PM_PAR_ERR
- PI_TYPE_0_STAT_M_STATE_CHANGE
- PI_TYPE_0_STAT_M_XMT_FLUSH
- PI_TYPE_0_STAT_V_1MS
- PI_TYPE_0_STAT_V_20MS
- PI_TYPE_0_STAT_V_BUS_PAR_ERR
- PI_TYPE_0_STAT_V_CSR_CMD_DONE
- PI_TYPE_0_STAT_V_NXM
- PI_TYPE_0_STAT_V_PM_PAR_ERR
- PI_TYPE_0_STAT_V_STATE_CHANGE
- PI_TYPE_0_STAT_V_XMT_FLUSH
- PI_TYPE_1_CONSUMER
- PI_TYPE_1_PROD_REG
- PI_TYPE_2_CONSUMER
- PI_TYPE_2_PROD_REG
- PI_UINT16
- PI_UINT32
- PI_UINT8
- PI_UNSOL_K_NUM_ENTRIES
- PI_UNSOL_K_SIZE_MAX
- PI_VERSION
- PI_VID
- PI_XMT_DATA_K_NUM_ENTRIES
- PI_XMT_DATA_K_SIZE_MAX
- PI_XMT_DESCR
- PI_XMT_DESCR_M_BUFF_HI
- PI_XMT_DESCR_M_EOP
- PI_XMT_DESCR_M_MBZ
- PI_XMT_DESCR_M_SEG_LEN
- PI_XMT_DESCR_M_SOP
- PI_XMT_DESCR_V_BUFF_HI
- PI_XMT_DESCR_V_EOP
- PI_XMT_DESCR_V_MBZ
- PI_XMT_DESCR_V_SEG_LEN
- PI_XMT_DESCR_V_SOP
- PJ
- PJ0MD_000
- PJ0MD_001
- PJ0MD_010
- PJ0MD_011
- PJ0MD_100
- PJ0MD_101
- PJ0MD_110
- PJ0MD_111
- PJ0_DATA
- PJ0_FN
- PJ0_IN
- PJ0_IOR_IN
- PJ0_IOR_OUT
- PJ0_OUT
- PJ10MD_00
- PJ10MD_000
- PJ10MD_001
- PJ10MD_01
- PJ10MD_010
- PJ10MD_011
- PJ10MD_10
- PJ10MD_100
- PJ10MD_101
- PJ10MD_11
- PJ10MD_110
- PJ10MD_111
- PJ10_DATA
- PJ10_IN
- PJ10_IOR_IN
- PJ10_IOR_OUT
- PJ10_OUT
- PJ11MD_00
- PJ11MD_000
- PJ11MD_001
- PJ11MD_01
- PJ11MD_010
- PJ11MD_011
- PJ11MD_10
- PJ11MD_100
- PJ11MD_101
- PJ11MD_11
- PJ11MD_110
- PJ11MD_111
- PJ11_DATA
- PJ11_IN
- PJ11_IOR_IN
- PJ11_IOR_OUT
- PJ11_OUT
- PJ12MD_000
- PJ12MD_001
- PJ12MD_010
- PJ12MD_011
- PJ12MD_100
- PJ12MD_101
- PJ12MD_110
- PJ12MD_111
- PJ12_DATA
- PJ12_IN
- PJ12_IOR_IN
- PJ12_IOR_OUT
- PJ12_OUT
- PJ13MD_000
- PJ13MD_001
- PJ13MD_010
- PJ13MD_011
- PJ13MD_100
- PJ13MD_101
- PJ13MD_110
- PJ13MD_111
- PJ13_DATA
- PJ13_IN
- PJ13_IOR_IN
- PJ13_IOR_OUT
- PJ13_OUT
- PJ14MD_000
- PJ14MD_001
- PJ14MD_010
- PJ14MD_011
- PJ14MD_100
- PJ14MD_101
- PJ14MD_110
- PJ14MD_111
- PJ14_DATA
- PJ14_IN
- PJ14_IOR_IN
- PJ14_IOR_OUT
- PJ14_OUT
- PJ15MD_000
- PJ15MD_001
- PJ15MD_010
- PJ15MD_011
- PJ15MD_100
- PJ15MD_101
- PJ15MD_110
- PJ15MD_111
- PJ15_DATA
- PJ15_IN
- PJ15_IOR_IN
- PJ15_IOR_OUT
- PJ15_OUT
- PJ16MD_000
- PJ16MD_001
- PJ16MD_010
- PJ16MD_011
- PJ16MD_100
- PJ16MD_101
- PJ16MD_110
- PJ16MD_111
- PJ16_DATA
- PJ16_IN
- PJ16_IOR_IN
- PJ16_IOR_OUT
- PJ16_OUT
- PJ17MD_000
- PJ17MD_001
- PJ17MD_010
- PJ17MD_011
- PJ17MD_100
- PJ17MD_101
- PJ17MD_110
- PJ17MD_111
- PJ17_DATA
- PJ17_IN
- PJ17_IOR_IN
- PJ17_IOR_OUT
- PJ17_OUT
- PJ18MD_000
- PJ18MD_001
- PJ18MD_010
- PJ18MD_011
- PJ18MD_100
- PJ18MD_101
- PJ18MD_110
- PJ18MD_111
- PJ18_DATA
- PJ18_IN
- PJ18_IOR_IN
- PJ18_IOR_OUT
- PJ18_OUT
- PJ19MD_000
- PJ19MD_001
- PJ19MD_010
- PJ19MD_011
- PJ19MD_100
- PJ19MD_101
- PJ19MD_110
- PJ19MD_111
- PJ19_DATA
- PJ19_IN
- PJ19_IOR_IN
- PJ19_IOR_OUT
- PJ19_OUT
- PJ1MD_000
- PJ1MD_001
- PJ1MD_010
- PJ1MD_011
- PJ1MD_100
- PJ1MD_101
- PJ1MD_110
- PJ1MD_111
- PJ1_DATA
- PJ1_FN
- PJ1_IN
- PJ1_INT_SEL
- PJ1_IOR_IN
- PJ1_IOR_OUT
- PJ1_OUT
- PJ20MD_000
- PJ20MD_001
- PJ20MD_010
- PJ20MD_011
- PJ20MD_100
- PJ20MD_101
- PJ20MD_110
- PJ20MD_111
- PJ20_DATA
- PJ20_IN
- PJ20_IOR_IN
- PJ20_IOR_OUT
- PJ20_OUT
- PJ21MD_000
- PJ21MD_001
- PJ21MD_010
- PJ21MD_011
- PJ21MD_100
- PJ21MD_101
- PJ21MD_110
- PJ21MD_111
- PJ21_DATA
- PJ21_IN
- PJ21_IOR_IN
- PJ21_IOR_OUT
- PJ21_OUT
- PJ22MD_000
- PJ22MD_001
- PJ22MD_010
- PJ22MD_011
- PJ22MD_100
- PJ22MD_101
- PJ22MD_110
- PJ22MD_111
- PJ22_DATA
- PJ22_IN
- PJ22_IOR_IN
- PJ22_IOR_OUT
- PJ22_OUT
- PJ23MD_000
- PJ23MD_001
- PJ23MD_010
- PJ23MD_011
- PJ23MD_100
- PJ23MD_101
- PJ23MD_110
- PJ23MD_111
- PJ23_DATA
- PJ23_IN
- PJ23_IOR_IN
- PJ23_IOR_OUT
- PJ23_OUT
- PJ24MD_000
- PJ24MD_001
- PJ24MD_010
- PJ24MD_011
- PJ24MD_100
- PJ24MD_101
- PJ24MD_110
- PJ24MD_111
- PJ24_DATA
- PJ24_IN
- PJ24_IOR_IN
- PJ24_IOR_OUT
- PJ24_OUT
- PJ25MD_000
- PJ25MD_001
- PJ25MD_010
- PJ25MD_011
- PJ25MD_100
- PJ25MD_101
- PJ25MD_110
- PJ25MD_111
- PJ25_DATA
- PJ25_IN
- PJ25_IOR_IN
- PJ25_IOR_OUT
- PJ25_OUT
- PJ26MD_000
- PJ26MD_001
- PJ26MD_010
- PJ26MD_011
- PJ26MD_100
- PJ26MD_101
- PJ26MD_110
- PJ26MD_111
- PJ26_DATA
- PJ26_IN
- PJ26_IOR_IN
- PJ26_IOR_OUT
- PJ26_OUT
- PJ27MD_000
- PJ27MD_001
- PJ27MD_010
- PJ27MD_011
- PJ27MD_100
- PJ27MD_101
- PJ27MD_110
- PJ27MD_111
- PJ27_DATA
- PJ27_IN
- PJ27_IOR_IN
- PJ27_IOR_OUT
- PJ27_OUT
- PJ28MD_000
- PJ28MD_001
- PJ28MD_010
- PJ28MD_011
- PJ28MD_100
- PJ28MD_101
- PJ28MD_110
- PJ28MD_111
- PJ28_DATA
- PJ28_IN
- PJ28_IOR_IN
- PJ28_IOR_OUT
- PJ28_OUT
- PJ29MD_000
- PJ29MD_001
- PJ29MD_010
- PJ29MD_011
- PJ29MD_100
- PJ29MD_101
- PJ29MD_110
- PJ29MD_111
- PJ29_DATA
- PJ29_IN
- PJ29_IOR_IN
- PJ29_IOR_OUT
- PJ29_OUT
- PJ2MD_000
- PJ2MD_001
- PJ2MD_010
- PJ2MD_011
- PJ2MD_100
- PJ2MD_101
- PJ2MD_110
- PJ2MD_111
- PJ2_DATA
- PJ2_FN
- PJ2_IN
- PJ2_IOR_IN
- PJ2_IOR_OUT
- PJ2_OUT
- PJ30MD_000
- PJ30MD_001
- PJ30MD_010
- PJ30MD_011
- PJ30MD_100
- PJ30MD_101
- PJ30MD_110
- PJ30MD_111
- PJ30_DATA
- PJ30_IN
- PJ30_IOR_IN
- PJ30_IOR_OUT
- PJ30_OUT
- PJ31MD_0
- PJ31MD_1
- PJ31_DATA
- PJ31_IN
- PJ31_IOR_IN
- PJ31_IOR_OUT
- PJ31_OUT
- PJ3MD_00
- PJ3MD_000
- PJ3MD_001
- PJ3MD_01
- PJ3MD_010
- PJ3MD_011
- PJ3MD_10
- PJ3MD_100
- PJ3MD_101
- PJ3MD_11
- PJ3MD_110
- PJ3MD_111
- PJ3_DATA
- PJ3_FN
- PJ3_IN
- PJ3_IOR_IN
- PJ3_IOR_OUT
- PJ3_OUT
- PJ4
- PJ4B_AUX_DBG_CTRL2
- PJ4B_BROADCAST_CACHE
- PJ4B_CLEAN_LINE
- PJ4B_CWF
- PJ4B_FAST_LDR
- PJ4B_INTER_PARITY
- PJ4B_L1_PAR_CHK
- PJ4B_L1_REP_RR
- PJ4B_OUTSDNG_NC
- PJ4B_SMP_CFB
- PJ4B_SNOOP_DATA
- PJ4B_STATIC_BP
- PJ4B_WFI_WFE
- PJ4MD_00
- PJ4MD_000
- PJ4MD_001
- PJ4MD_01
- PJ4MD_010
- PJ4MD_011
- PJ4MD_10
- PJ4MD_100
- PJ4MD_101
- PJ4MD_11
- PJ4MD_110
- PJ4MD_111
- PJ4_DATA
- PJ4_FN
- PJ4_IN
- PJ4_INT_SEL
- PJ4_IOR_IN
- PJ4_IOR_OUT
- PJ4_OUT
- PJ5MD_00
- PJ5MD_000
- PJ5MD_001
- PJ5MD_01
- PJ5MD_010
- PJ5MD_011
- PJ5MD_10
- PJ5MD_100
- PJ5MD_101
- PJ5MD_11
- PJ5MD_110
- PJ5MD_111
- PJ5_DATA
- PJ5_FN
- PJ5_IN
- PJ5_IOR_IN
- PJ5_IOR_OUT
- PJ5_OUT
- PJ6MD_00
- PJ6MD_000
- PJ6MD_001
- PJ6MD_01
- PJ6MD_010
- PJ6MD_011
- PJ6MD_10
- PJ6MD_100
- PJ6MD_101
- PJ6MD_11
- PJ6MD_110
- PJ6MD_111
- PJ6_DATA
- PJ6_FN
- PJ6_IN
- PJ6_IOR_IN
- PJ6_IOR_OUT
- PJ6_OUT
- PJ7MD_00
- PJ7MD_000
- PJ7MD_001
- PJ7MD_01
- PJ7MD_010
- PJ7MD_011
- PJ7MD_10
- PJ7MD_100
- PJ7MD_101
- PJ7MD_11
- PJ7MD_110
- PJ7MD_111
- PJ7_DATA
- PJ7_FN
- PJ7_IN
- PJ7_IOR_IN
- PJ7_IOR_OUT
- PJ7_OUT
- PJ8MD_00
- PJ8MD_000
- PJ8MD_001
- PJ8MD_01
- PJ8MD_010
- PJ8MD_011
- PJ8MD_10
- PJ8MD_100
- PJ8MD_101
- PJ8MD_11
- PJ8MD_110
- PJ8MD_111
- PJ8_DATA
- PJ8_IN
- PJ8_IOR_IN
- PJ8_IOR_OUT
- PJ8_OUT
- PJ9MD_00
- PJ9MD_000
- PJ9MD_001
- PJ9MD_01
- PJ9MD_010
- PJ9MD_011
- PJ9MD_10
- PJ9MD_100
- PJ9MD_101
- PJ9MD_11
- PJ9MD_110
- PJ9MD_111
- PJ9_DATA
- PJ9_IN
- PJ9_IOR_IN
- PJ9_IOR_OUT
- PJ9_OUT
- PJDATA
- PJDATA_ADDR
- PJDIR
- PJDIR_ADDR
- PJDR
- PJDR_LED_BLINK
- PJPUEN
- PJPUEN_ADDR
- PJSEL
- PJSEL_ADDR
- PJ_CSD3
- PJ_CTS2
- PJ_INTERRUPT_MASK
- PJ_MISO
- PJ_MOSI
- PJ_RST_INTERRUPT
- PJ_RTS2
- PJ_RXD2
- PJ_SPICLK1
- PJ_SS
- PJ_TXD2
- PK
- PK0MD_00
- PK0MD_01
- PK0MD_10
- PK0MD_11
- PK0_DATA
- PK0_FN
- PK0_IN
- PK0_IOR_IN
- PK0_IOR_OUT
- PK0_OUT
- PK10MD_00
- PK10MD_01
- PK10MD_10
- PK10MD_11
- PK10_DATA
- PK10_IN
- PK10_IOR_IN
- PK10_IOR_OUT
- PK10_OUT
- PK11MD_00
- PK11MD_01
- PK11MD_10
- PK11MD_11
- PK11_DATA
- PK11_IN
- PK11_IOR_IN
- PK11_IOR_OUT
- PK11_OUT
- PK12_DATA
- PK12_IN
- PK12_OUT
- PK1MD_00
- PK1MD_01
- PK1MD_10
- PK1MD_11
- PK1_DATA
- PK1_FN
- PK1_IN
- PK1_IOR_IN
- PK1_IOR_OUT
- PK1_OUT
- PK2MD_00
- PK2MD_01
- PK2MD_10
- PK2MD_11
- PK2_DATA
- PK2_FN
- PK2_IN
- PK2_IOR_IN
- PK2_IOR_OUT
- PK2_OUT
- PK3MD_00
- PK3MD_01
- PK3MD_10
- PK3MD_11
- PK3_DATA
- PK3_FN
- PK3_IN
- PK3_IOR_IN
- PK3_IOR_OUT
- PK3_OUT
- PK4MD_00
- PK4MD_01
- PK4MD_10
- PK4MD_11
- PK4_DATA
- PK4_FN
- PK4_IN
- PK4_IOR_IN
- PK4_IOR_OUT
- PK4_OUT
- PK5MD_00
- PK5MD_01
- PK5MD_10
- PK5MD_11
- PK5_DATA
- PK5_FN
- PK5_IN
- PK5_IOR_IN
- PK5_IOR_OUT
- PK5_OUT
- PK6MD_00
- PK6MD_01
- PK6MD_10
- PK6MD_11
- PK6_DATA
- PK6_FN
- PK6_IN
- PK6_IOR_IN
- PK6_IOR_OUT
- PK6_OUT
- PK7MD_00
- PK7MD_01
- PK7MD_10
- PK7MD_11
- PK7_DATA
- PK7_FN
- PK7_IN
- PK7_IOR_IN
- PK7_IOR_OUT
- PK7_OUT
- PK8MD_00
- PK8MD_01
- PK8MD_10
- PK8MD_11
- PK8_DATA
- PK8_IN
- PK8_IOR_IN
- PK8_IOR_OUT
- PK8_OUT
- PK9MD_00
- PK9MD_01
- PK9MD_10
- PK9MD_11
- PK9_DATA
- PK9_IN
- PK9_IOR_IN
- PK9_IOR_OUT
- PK9_OUT
- PKDATA
- PKDATA_ADDR
- PKDIR
- PKDIR_ADDR
- PKDR
- PKDR_LED_GREEN
- PKDR_SPEAKER
- PKEY_ACCESS_MASK
- PKEY_APQNS4K
- PKEY_APQNS4KT
- PKEY_CHECK_INVALID
- PKEY_CLR2PROTK
- PKEY_CLR2SECK
- PKEY_CLR2SECK2
- PKEY_DEDICATED_EXECUTE_ONLY
- PKEY_DISABLE_ACCESS
- PKEY_DISABLE_EXECUTE
- PKEY_DISABLE_WRITE
- PKEY_FINDCARD
- PKEY_FLAGS_MATCH_ALT_MKVP
- PKEY_FLAGS_MATCH_CUR_MKVP
- PKEY_GENPROTK
- PKEY_GENSECK
- PKEY_GENSECK2
- PKEY_ID
- PKEY_ID_PGP
- PKEY_ID_PKCS7
- PKEY_ID_X509
- PKEY_IOCTL_MAGIC
- PKEY_KBLOB2PROTK
- PKEY_KBLOB2PROTK2
- PKEY_KEYGEN_XPRT_AASY
- PKEY_KEYGEN_XPRT_AES
- PKEY_KEYGEN_XPRT_CPAC
- PKEY_KEYGEN_XPRT_DES
- PKEY_KEYGEN_XPRT_RAW
- PKEY_KEYGEN_XPRT_RSA
- PKEY_KEYGEN_XPRT_SYM
- PKEY_KEYGEN_XPRT_UASY
- PKEY_KEYTYPE_AES_128
- PKEY_KEYTYPE_AES_192
- PKEY_KEYTYPE_AES_256
- PKEY_LOW_15_MASK
- PKEY_MEMBER_MASK
- PKEY_REG_BITS
- PKEY_SEC2PROTK
- PKEY_SIZE_AES_128
- PKEY_SIZE_AES_192
- PKEY_SIZE_AES_256
- PKEY_SIZE_UNKNOWN
- PKEY_SKEY2PKEY
- PKEY_TURNOFF_CR
- PKEY_TYPE_CCA_CIPHER
- PKEY_TYPE_CCA_DATA
- PKEY_VERIFYKEY
- PKEY_VERIFYKEY2
- PKEY_VERIFYPROTK
- PKEY_VERIFY_ATTR_AES
- PKEY_VERIFY_ATTR_OLD_MKVP
- PKE_DH_1536
- PKE_DH_2048
- PKE_DH_3072
- PKE_DH_4096
- PKE_DH_G2_1536
- PKE_DH_G2_2048
- PKE_DH_G2_3072
- PKE_DH_G2_4096
- PKE_RSA_DP1_1024
- PKE_RSA_DP1_1536
- PKE_RSA_DP1_2048
- PKE_RSA_DP1_3072
- PKE_RSA_DP1_4096
- PKE_RSA_DP1_512
- PKE_RSA_DP2_1024
- PKE_RSA_DP2_1536
- PKE_RSA_DP2_2048
- PKE_RSA_DP2_3072
- PKE_RSA_DP2_4096
- PKE_RSA_DP2_512
- PKE_RSA_EP_1024
- PKE_RSA_EP_1536
- PKE_RSA_EP_2048
- PKE_RSA_EP_3072
- PKE_RSA_EP_4096
- PKE_RSA_EP_512
- PKG0
- PKG1
- PKG2
- PKG3
- PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK
- PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT
- PKG_CSTATE_INIT
- PKG_PWR_CNTL__CpcGpuPerfPri_MASK
- PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT
- PKG_PWR_CNTL__FchPwrCreditScale_MASK
- PKG_PWR_CNTL__FchPwrCreditScale__SHIFT
- PKG_PWR_CNTL__PkgHystCoeff_MASK
- PKG_PWR_CNTL__PkgHystCoeff__SHIFT
- PKG_PWR_CNTL__PkgPwrLimit_MASK
- PKG_PWR_CNTL__PkgPwrLimit__SHIFT
- PKG_PWR_CNTL__RESERVED_MASK
- PKG_PWR_CNTL__RESERVED__SHIFT
- PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK
- PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT
- PKG_PWR_STATUS__PkgPwrLimit_base_MASK
- PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT
- PKG_PWR_STATUS__PkgPwr_MAWt_MASK
- PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT
- PKG_PWR_STATUS__PstateLimitSetFlag_MASK
- PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT
- PKG_PWR_STATUS__RESERVED_MASK
- PKG_PWR_STATUS__RESERVED__SHIFT
- PKG_SEL_HCI
- PKG_SYSFS_ATTR_NO
- PKG_TEMP_THERMAL_NOTIFY_DELAY
- PKMAP_ADDR
- PKMAP_BASE
- PKMAP_BASE_NR
- PKMAP_END
- PKMAP_NR
- PKMAP_ORDER
- PKMAP_SIZE
- PKP
- PKPUEN
- PKPUEN_ADDR
- PKRU_AD_BIT
- PKRU_AD_KEY
- PKRU_BITS_PER_PKEY
- PKRU_VALID_MASK
- PKRU_WD_BIT
- PKR_MAP
- PKR_MAP_MASK
- PKR_XSEL
- PKR_XSEL_MASK
- PKR_YSEL
- PKR_YSEL_MASK
- PKSEL
- PKSEL_ADDR
- PKSR
- PKT4
- PKTBUFSZ
- PKTBUF_ADDR
- PKTCTRL_PCRCEN
- PKTCTRL_PHUGEEN
- PKTCTRL_POVERRIDE
- PKTCTRL_PPADEN
- PKTDEC
- PKTDELIN_LOCK
- PKTFIFO_M
- PKTFIFO_S
- PKTFIFO_V
- PKTGEN_MAGIC
- PKTHDR_RADIOTAP_VERSION
- PKTIE
- PKTIF
- PKTINFO_SKB_CB
- PKTIN_Q_ALIGN_BYTES
- PKTLEN_MASK
- PKTLEN_SHIFT
- PKTM
- PKTQ_LEN_DEFAULT
- PKTQ_MAX_PREC
- PKTSHIFT_G
- PKTSHIFT_M
- PKTSHIFT_S
- PKTSHIFT_V
- PKTSIZE
- PKTSMask
- PKTSShift
- PKT_ADDRH_LEN
- PKT_ADDRH_POS
- PKT_ADDRL_LEN
- PKT_ADDRL_POS
- PKT_ALIGN
- PKT_AVAIL_SPDWN_EN
- PKT_BAUD_RATE_115200
- PKT_BAUD_RATE_230400
- PKT_BAUD_RATE_460800
- PKT_BAUD_RATE_57600
- PKT_BUFF_AVAILABLE
- PKT_BUFF_FULL
- PKT_BUFF_SEMI_FULL
- PKT_BUFF_SIZE
- PKT_BUFF_SZ
- PKT_BUF_SIZE
- PKT_BUF_SKB
- PKT_BUF_SZ
- PKT_CFG
- PKT_COMMAND
- PKT_COMPLETE
- PKT_COMP_Q
- PKT_COPY_THRESHOLD
- PKT_CTRL_CMD_SETUP
- PKT_CTRL_CMD_STATUS
- PKT_CTRL_CMD_TEARDOWN
- PKT_CTR_OFFSET
- PKT_CTR_SIZE
- PKT_DATA
- PKT_DISPOSED
- PKT_DUMMY_PACKET
- PKT_DV
- PKT_ERROR
- PKT_EVENT_LIFETIME_MS
- PKT_EXTRA_FLAGS
- PKT_FIELD
- PKT_FIRST_IN_FRAME
- PKT_FLAGS
- PKT_FRAGMENTED
- PKT_HASH_TYPE_L2
- PKT_HASH_TYPE_L3
- PKT_HASH_TYPE_L4
- PKT_HASH_TYPE_NONE
- PKT_HDLC_CRC_32
- PKT_HDLC_IDLE_ONES
- PKT_HDLC_MSB_ENDIAN
- PKT_HDR_LEN
- PKT_HOST_COMMAND
- PKT_HOST_DATA
- PKT_ID0
- PKT_ID1
- PKT_ID2
- PKT_IN_TOKEN_FRAME
- PKT_LB_TC
- PKT_LEN0
- PKT_LEN1
- PKT_LEN2
- PKT_LEN_OFFSET
- PKT_LEN_WHEN_EXTENDING
- PKT_LNGTH_MASK
- PKT_LOW_SPEED_PACKET
- PKT_LP
- PKT_MAXBLR_SIZE
- PKT_MAXBUF_SIZE
- PKT_MGMT_BUFF_FULL
- PKT_MINBUF_SIZE
- PKT_NACK_FRAME
- PKT_NO_CRC
- PKT_NO_PID
- PKT_NUM_PIPES
- PKT_NUM_PIPES_WRITE
- PKT_OFFSET_SHT
- PKT_OFFSET_SZ
- PKT_OUT_TOKEN_FRAME
- PKT_PAYLOAD_SIZE
- PKT_PCLOSE
- PKT_PID_DATA0
- PKT_PID_DATA1
- PKT_PID_SETUP
- PKT_PIPE_FIFO_SIZEW
- PKT_PIPE_FIFO_SIZEW_WRITE
- PKT_PIPE_FLOW_DISABLE
- PKT_PIPE_FLOW_ENABLE
- PKT_PIPE_HDLC_CFG_WRITE
- PKT_PIPE_IDLE_PATTERN_WRITE
- PKT_PIPE_MODE_WRITE
- PKT_PIPE_RX_SIZE_WRITE
- PKT_POPEN
- PKT_POSTFIX
- PKT_PREFIX
- PKT_PROT_NODE
- PKT_RAM
- PKT_RB_POOL_SIZE
- PKT_RDY
- PKT_RDY_Q
- PKT_READY
- PKT_READ_SIZE
- PKT_RING_MSIX_BASE
- PKT_SETADDR_STATUS
- PKT_SETUP_STATUS
- PKT_SETUP_TOKEN_FRAME
- PKT_SET_HOST_LAST
- PKT_SIZE
- PKT_SIZE_LEN
- PKT_SIZE_POS
- PKT_STALL_FRAME
- PKT_START
- PKT_START_HI
- PKT_START_LO
- PKT_STATE_SETUP
- PKT_STATE_TERMINATE
- PKT_STATE_TRANSFER
- PKT_STATUS
- PKT_SZ
- PKT_SZ_API0
- PKT_SZ_API1
- PKT_TM_CNT
- PKT_TOKEN_FRAME
- PKT_TO_SKB
- PKT_TYPE_ALL_MULTICAST
- PKT_TYPE_AMSDU
- PKT_TYPE_BAR
- PKT_TYPE_BROADCAST
- PKT_TYPE_BSSID
- PKT_TYPE_DIRECTED
- PKT_TYPE_ERROR
- PKT_TYPE_ERROR_CRC
- PKT_TYPE_ERROR_WPA
- PKT_TYPE_LACPDU
- PKT_TYPE_LONG
- PKT_TYPE_MAX
- PKT_TYPE_MGMT
- PKT_TYPE_MULTICAST
- PKT_TYPE_NODE
- PKT_TYPE_NONE
- PKT_TYPE_NORMAL
- PKT_TYPE_OFFSET
- PKT_TYPE_PROMISCUOUS
- PKT_TYPE_RETRIEVE
- PKT_TYPE_RUNT
- PKT_TYPE_RX_DUP_RFB
- PKT_TYPE_RX_EVENT
- PKT_TYPE_RX_TMR
- PKT_TYPE_SIZE
- PKT_TYPE_TXRXV
- PKT_TYPE_TXRX_NOTIFY
- PKT_TYPE_TXS
- PKT_VEC_PKT_LEN
- PKT_VEC_PKT_PTR
- PKT_VEC_QSEL_SET
- PKT_VEC_QSEL_VAL
- PKT_VEL_QSEL_SET_BIT
- PKT_VLAN_PRESENT_BIT
- PKT_VLAN_PRESENT_OFFSET
- PKT_WRITE_CONGESTION_OFF
- PKT_WRITE_CONGESTION_ON
- PKT_WRITE_SIZE
- PKT_ZLP
- PKUNITY_AC97_BASE
- PKUNITY_AC97_CONR
- PKUNITY_AC97_CRAC
- PKUNITY_AC97_ENABLE
- PKUNITY_AC97_ICR
- PKUNITY_AC97_INTR
- PKUNITY_AC97_INTRCLEAR
- PKUNITY_AC97_INTRSTAT
- PKUNITY_AC97_IN_FIFO
- PKUNITY_AC97_OCR
- PKUNITY_AC97_OUT_FIFO
- PKUNITY_AHB_BASE
- PKUNITY_APB_BASE
- PKUNITY_ARBITER_BASE
- PKUNITY_DDR2CTRL_BASE
- PKUNITY_DMAC_BASE
- PKUNITY_GPIO_BASE
- PKUNITY_H264D_BASE
- PKUNITY_H264E_BASE
- PKUNITY_I2C_BASE
- PKUNITY_INTC_BASE
- PKUNITY_MME_BASE
- PKUNITY_MMIO_BASE
- PKUNITY_NAND_BASE
- PKUNITY_OST_BASE
- PKUNITY_PCIAHB_BASE
- PKUNITY_PCIBRI_BASE
- PKUNITY_PCICFG_BASE
- PKUNITY_PCILIO_BASE
- PKUNITY_PCIMEM_BASE
- PKUNITY_PCI_BASE
- PKUNITY_PM_BASE
- PKUNITY_PS2_BASE
- PKUNITY_RESETC_BASE
- PKUNITY_RTC_BASE
- PKUNITY_SATA_BASE
- PKUNITY_SDC_BASE
- PKUNITY_SDRAM_BASE
- PKUNITY_SMC_BASE
- PKUNITY_SPI_BASE
- PKUNITY_UART0_BASE
- PKUNITY_UART1_BASE
- PKUNITY_UMAL_BASE
- PKUNITY_UNIGFX_BASE
- PKUNITY_USB_BASE
- PKWR
- PK_AVI_0BYTE
- PK_AVI_0HEAD
- PK_AVI_10BYTE
- PK_AVI_11BYTE
- PK_AVI_12BYTE
- PK_AVI_13BYTE
- PK_AVI_14BYTE
- PK_AVI_15BYTE
- PK_AVI_16BYTE
- PK_AVI_1BYTE
- PK_AVI_1HEAD
- PK_AVI_2BYTE
- PK_AVI_2HEAD
- PK_AVI_3BYTE
- PK_AVI_4BYTE
- PK_AVI_5BYTE
- PK_AVI_6BYTE
- PK_AVI_7BYTE
- PK_AVI_8BYTE
- PK_AVI_9BYTE
- PK_DATAREADY
- PK_INT_MODE
- PK_LD4
- PK_LD5
- PK_LD6
- PK_LD7
- PK_LDS
- PK_PWM2
- PK_QUIRK_NOGET
- PK_R_W
- PK_TYPE_11A
- PK_TYPE_11B
- PK_TYPE_11GA
- PK_TYPE_11GB
- PK_UDS
- PL
- PL011_DMA_BUFFER_SIZE
- PL061_GPIO_NR
- PL080N_CONFIG_ITPROT
- PL080N_CONFIG_SECPROT
- PL080S_CH_CONFIG
- PL080S_CH_CONTROL2
- PL080S_CONTROL_TRANSFER_SIZE_MASK
- PL080S_LLI_CCTL2
- PL080S_LLI_WORDS
- PL080_BSIZE_1
- PL080_BSIZE_128
- PL080_BSIZE_16
- PL080_BSIZE_256
- PL080_BSIZE_32
- PL080_BSIZE_4
- PL080_BSIZE_64
- PL080_BSIZE_8
- PL080_CH_CONFIG
- PL080_CH_CONTROL
- PL080_CH_DST_ADDR
- PL080_CH_LLI
- PL080_CH_SRC_ADDR
- PL080_CONFIG
- PL080_CONFIG_ACTIVE
- PL080_CONFIG_DST_SEL_MASK
- PL080_CONFIG_DST_SEL_SHIFT
- PL080_CONFIG_ENABLE
- PL080_CONFIG_ERR_IRQ_MASK
- PL080_CONFIG_FLOW_CONTROL_MASK
- PL080_CONFIG_FLOW_CONTROL_SHIFT
- PL080_CONFIG_HALT
- PL080_CONFIG_LOCK
- PL080_CONFIG_M1_BE
- PL080_CONFIG_M2_BE
- PL080_CONFIG_SRC_SEL_MASK
- PL080_CONFIG_SRC_SEL_SHIFT
- PL080_CONFIG_TC_IRQ_MASK
- PL080_CONTROL_DB_SIZE_MASK
- PL080_CONTROL_DB_SIZE_SHIFT
- PL080_CONTROL_DST_AHB2
- PL080_CONTROL_DST_INCR
- PL080_CONTROL_DWIDTH_MASK
- PL080_CONTROL_DWIDTH_SHIFT
- PL080_CONTROL_PROT_BUFF
- PL080_CONTROL_PROT_CACHE
- PL080_CONTROL_PROT_MASK
- PL080_CONTROL_PROT_SHIFT
- PL080_CONTROL_PROT_SYS
- PL080_CONTROL_SB_SIZE_MASK
- PL080_CONTROL_SB_SIZE_SHIFT
- PL080_CONTROL_SRC_AHB2
- PL080_CONTROL_SRC_INCR
- PL080_CONTROL_SWIDTH_MASK
- PL080_CONTROL_SWIDTH_SHIFT
- PL080_CONTROL_TC_IRQ_EN
- PL080_CONTROL_TRANSFER_SIZE_MASK
- PL080_CONTROL_TRANSFER_SIZE_SHIFT
- PL080_Cx_BASE
- PL080_EN_CHAN
- PL080_ERR_CLEAR
- PL080_ERR_STATUS
- PL080_FLOW_MEM2MEM
- PL080_FLOW_MEM2PER
- PL080_FLOW_MEM2PER_PER
- PL080_FLOW_PER2MEM
- PL080_FLOW_PER2MEM_PER
- PL080_FLOW_SRC2DST
- PL080_FLOW_SRC2DST_DST
- PL080_FLOW_SRC2DST_SRC
- PL080_INT_STATUS
- PL080_LLI_ADDR_MASK
- PL080_LLI_ADDR_SHIFT
- PL080_LLI_CCTL
- PL080_LLI_DST
- PL080_LLI_LLI
- PL080_LLI_LM_AHB2
- PL080_LLI_SRC
- PL080_LLI_WORDS
- PL080_RAW_ERR_STATUS
- PL080_RAW_TC_STATUS
- PL080_SOFT_BREQ
- PL080_SOFT_LBREQ
- PL080_SOFT_LSREQ
- PL080_SOFT_SREQ
- PL080_SYNC
- PL080_TC_CLEAR
- PL080_TC_STATUS
- PL080_WIDTH_16BIT
- PL080_WIDTH_32BIT
- PL080_WIDTH_8BIT
- PL08X_AHB1
- PL08X_AHB2
- PL08X_ALIGN
- PL08X_BURST_SZ_1
- PL08X_BURST_SZ_128
- PL08X_BURST_SZ_16
- PL08X_BURST_SZ_256
- PL08X_BURST_SZ_32
- PL08X_BURST_SZ_4
- PL08X_BURST_SZ_64
- PL08X_BURST_SZ_8
- PL08X_BUS_WIDTH_16_BITS
- PL08X_BUS_WIDTH_32_BITS
- PL08X_BUS_WIDTH_8_BITS
- PL08X_CHAN_IDLE
- PL08X_CHAN_PAUSED
- PL08X_CHAN_RUNNING
- PL08X_CHAN_WAITING
- PL0_DATA
- PL0_FN
- PL0_IN
- PL0_OUT
- PL0_REF
- PL111_NOMADIK_H
- PL111_VERSATILE_H
- PL172_MAX_CS
- PL1_CLAMP
- PL1_DATA
- PL1_ENABLE
- PL1_FN
- PL1_IN
- PL1_OUT
- PL1_REF
- PL2303_FLOWCTRL_MASK
- PL2303_PRODUCT_ID
- PL2303_PRODUCT_ID_ALDIGA
- PL2303_PRODUCT_ID_CHILITAG
- PL2303_PRODUCT_ID_DCU11
- PL2303_PRODUCT_ID_GPRS
- PL2303_PRODUCT_ID_HCR331
- PL2303_PRODUCT_ID_MMX
- PL2303_PRODUCT_ID_MOTOROLA
- PL2303_PRODUCT_ID_PHAROS
- PL2303_PRODUCT_ID_RSAQ2
- PL2303_PRODUCT_ID_RSAQ3
- PL2303_PRODUCT_ID_TB
- PL2303_PRODUCT_ID_ZTEK
- PL2303_QUIRK_ENDPOINT_HACK
- PL2303_QUIRK_LEGACY
- PL2303_QUIRK_UART_STATE_IDX0
- PL2303_VENDOR_ID
- PL2_CLAMP
- PL2_DATA
- PL2_ENABLE
- PL2_FN
- PL2_IN
- PL2_OUT
- PL2_REF
- PL310_EVENT_ATTR
- PL330_AUTOSUSPEND_DELAY
- PL330_DBGCMD_DUMP
- PL330_DBGMC_START
- PL330_DMA_BUSWIDTHS
- PL330_ERR_ABORT
- PL330_ERR_FAIL
- PL330_ERR_NONE
- PL330_MAX_BURST
- PL330_MAX_CHAN
- PL330_MAX_IRQS
- PL330_MAX_PERI
- PL330_QUIRK_BROKEN_NO_FLUSHP
- PL330_STABLE_STATES
- PL330_STATE_ATBARRIER
- PL330_STATE_CACHEMISS
- PL330_STATE_COMPLETING
- PL330_STATE_EXECUTING
- PL330_STATE_FAULTING
- PL330_STATE_FAULT_COMPLETING
- PL330_STATE_INVALID
- PL330_STATE_KILLING
- PL330_STATE_QUEUEBUSY
- PL330_STATE_STOPPED
- PL330_STATE_UPDTPC
- PL330_STATE_WFE
- PL330_STATE_WFP
- PL353_NAND_ECC_BUSY_TIMEOUT
- PL353_NAND_ECC_CMD1
- PL353_NAND_ECC_CMD2
- PL353_SMC_CFG_CLR_DEFAULT_MASK
- PL353_SMC_CFG_CLR_ECC_INT_DIS_1
- PL353_SMC_CFG_CLR_INT_CLR_1
- PL353_SMC_CFG_CLR_INT_DIS_1
- PL353_SMC_CFG_CLR_OFFS
- PL353_SMC_DC_UPT_NAND_REGS
- PL353_SMC_DIRECT_CMD_OFFS
- PL353_SMC_ECCMODE_APB
- PL353_SMC_ECCMODE_BYPASS
- PL353_SMC_ECCMODE_MEM
- PL353_SMC_ECC_MEMCFG_MODE_MASK
- PL353_SMC_ECC_MEMCFG_MODE_SHIFT
- PL353_SMC_ECC_MEMCFG_OFFS
- PL353_SMC_ECC_MEMCFG_PGSIZE_MASK
- PL353_SMC_ECC_MEMCMD1_OFFS
- PL353_SMC_ECC_MEMCMD2_OFFS
- PL353_SMC_ECC_REG_SIZE_OFFS
- PL353_SMC_ECC_STATUS_BUSY
- PL353_SMC_ECC_STATUS_OFFS
- PL353_SMC_ECC_VALUE0_OFFS
- PL353_SMC_MEMC_STATUS_OFFS
- PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT
- PL353_SMC_MEM_WIDTH_16
- PL353_SMC_MEM_WIDTH_8
- PL353_SMC_SET_CYCLES_OFFS
- PL353_SMC_SET_CYCLES_T0_MASK
- PL353_SMC_SET_CYCLES_T0_SHIFT
- PL353_SMC_SET_CYCLES_T1_MASK
- PL353_SMC_SET_CYCLES_T1_SHIFT
- PL353_SMC_SET_CYCLES_T2_MASK
- PL353_SMC_SET_CYCLES_T2_SHIFT
- PL353_SMC_SET_CYCLES_T3_MASK
- PL353_SMC_SET_CYCLES_T3_SHIFT
- PL353_SMC_SET_CYCLES_T4_MASK
- PL353_SMC_SET_CYCLES_T4_SHIFT
- PL353_SMC_SET_CYCLES_T5_MASK
- PL353_SMC_SET_CYCLES_T5_SHIFT
- PL353_SMC_SET_CYCLES_T6_MASK
- PL353_SMC_SET_CYCLES_T6_SHIFT
- PL353_SMC_SET_OPMODE_OFFS
- PL3_DATA
- PL3_FN
- PL3_IN
- PL3_OUT
- PL3_REF
- PL4_DATA
- PL4_FN
- PL4_IN
- PL4_OUT
- PL5_DATA
- PL5_FN
- PL5_IN
- PL5_OUT
- PL6_DATA
- PL6_FN
- PL6_IN
- PL6_OUT
- PL7_DATA
- PL7_FN
- PL7_IN
- PL7_OUT
- PL80X_DMA_BUSWIDTHS
- PLAIN_BUF_SIZE
- PLAIN_ROCE
- PLANAR_420_10BPC
- PLANAR_420_8BPC
- PLANAR_YUV_FMT
- PLANE0
- PLANE0_DATA_OFFSET
- PLANE1_AOI0
- PLANE1_AOI1
- PLANE2_AOI0
- PLANE2_AOI1
- PLANEA_FLIPDONE_INT_EN
- PLANEA_INVALID_GTT_INT_EN
- PLANEA_INVALID_GTT_STATUS
- PLANEB_FLIP_DONE_INT_EN
- PLANEB_INVALID_GTT_INT_EN
- PLANEB_INVALID_GTT_STATUS
- PLANEC_FLIPDONE_INT_EN
- PLANEC_INVALID_GTT_INT_EN
- PLANEC_INVALID_GTT_STATUS
- PLANETCORE_KEY_BOARD_REV
- PLANETCORE_KEY_BOARD_TYPE
- PLANETCORE_KEY_CRYSTAL_HZ
- PLANETCORE_KEY_FLASH_SPEED
- PLANETCORE_KEY_IP_ADDR
- PLANETCORE_KEY_KB_NVRAM
- PLANETCORE_KEY_MAC_ADDR
- PLANETCORE_KEY_MB_RAM
- PLANETCORE_KEY_PROCESSOR
- PLANETCORE_KEY_PROC_VARIANT
- PLANETCORE_KEY_SERIAL_BAUD
- PLANETCORE_KEY_SERIAL_PORT
- PLANETCORE_KEY_SWITCH
- PLANETCORE_KEY_TARGET_IP
- PLANETCORE_KEY_TEMP_OFFSET
- PLANE_A
- PLANE_AUX_DIST
- PLANE_AUX_OFFSET
- PLANE_B
- PLANE_BUF_CFG
- PLANE_C
- PLANE_COLOR_ALPHA_DISABLE
- PLANE_COLOR_ALPHA_HW_PREMULTIPLY
- PLANE_COLOR_ALPHA_MASK
- PLANE_COLOR_ALPHA_SW_PREMULTIPLY
- PLANE_COLOR_CSC_MODE_BYPASS
- PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020
- PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020
- PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709
- PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709
- PLANE_COLOR_CTL
- PLANE_COLOR_INPUT_CSC_ENABLE
- PLANE_COLOR_PIPE_CSC_ENABLE
- PLANE_COLOR_PIPE_GAMMA_ENABLE
- PLANE_COLOR_PLANE_GAMMA_DISABLE
- PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE
- PLANE_CTL
- PLANE_CTL_ALPHA_DISABLE
- PLANE_CTL_ALPHA_HW_PREMULTIPLY
- PLANE_CTL_ALPHA_MASK
- PLANE_CTL_ALPHA_SW_PREMULTIPLY
- PLANE_CTL_ASYNC_FLIP
- PLANE_CTL_ENABLE
- PLANE_CTL_FLIP_HORIZONTAL
- PLANE_CTL_FORMAT_AYUV
- PLANE_CTL_FORMAT_INDEXED
- PLANE_CTL_FORMAT_MASK
- PLANE_CTL_FORMAT_NV12
- PLANE_CTL_FORMAT_P010
- PLANE_CTL_FORMAT_P012
- PLANE_CTL_FORMAT_P016
- PLANE_CTL_FORMAT_RGB_565
- PLANE_CTL_FORMAT_XRGB_16161616F
- PLANE_CTL_FORMAT_XRGB_2101010
- PLANE_CTL_FORMAT_XRGB_8888
- PLANE_CTL_FORMAT_Y210
- PLANE_CTL_FORMAT_Y212
- PLANE_CTL_FORMAT_Y216
- PLANE_CTL_FORMAT_Y410
- PLANE_CTL_FORMAT_Y412
- PLANE_CTL_FORMAT_Y416
- PLANE_CTL_FORMAT_YUV422
- PLANE_CTL_KEY_ENABLE_DESTINATION
- PLANE_CTL_KEY_ENABLE_MASK
- PLANE_CTL_KEY_ENABLE_SOURCE
- PLANE_CTL_ORDER_BGRX
- PLANE_CTL_ORDER_RGBX
- PLANE_CTL_PIPE_CSC_ENABLE
- PLANE_CTL_PIPE_GAMMA_ENABLE
- PLANE_CTL_PLANE_GAMMA_DISABLE
- PLANE_CTL_RENDER_DECOMPRESSION_ENABLE
- PLANE_CTL_ROTATE_0
- PLANE_CTL_ROTATE_180
- PLANE_CTL_ROTATE_270
- PLANE_CTL_ROTATE_90
- PLANE_CTL_ROTATE_MASK
- PLANE_CTL_TILED_LINEAR
- PLANE_CTL_TILED_MASK
- PLANE_CTL_TILED_X
- PLANE_CTL_TILED_Y
- PLANE_CTL_TILED_YF
- PLANE_CTL_TRICKLE_FEED_DISABLE
- PLANE_CTL_YUV420_Y_PLANE
- PLANE_CTL_YUV422_ORDER_MASK
- PLANE_CTL_YUV422_UYVY
- PLANE_CTL_YUV422_VYUY
- PLANE_CTL_YUV422_YUYV
- PLANE_CTL_YUV422_YVYU
- PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE
- PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709
- PLANE_CURSOR
- PLANE_CUS_CTL
- PLANE_CUS_ENABLE
- PLANE_CUS_HPHASE_0
- PLANE_CUS_HPHASE_0_25
- PLANE_CUS_HPHASE_0_5
- PLANE_CUS_HPHASE_SIGN_NEGATIVE
- PLANE_CUS_PLANE_6
- PLANE_CUS_PLANE_7
- PLANE_CUS_VPHASE_0
- PLANE_CUS_VPHASE_0_25
- PLANE_CUS_VPHASE_0_5
- PLANE_CUS_VPHASE_SIGN_NEGATIVE
- PLANE_FLIP_DONE_INT_EN_VLV
- PLANE_FLIP_DONE_INT_STATUS_VLV
- PLANE_HAS_FENCE
- PLANE_INPUT_CSC_COEFF
- PLANE_INPUT_CSC_POSTOFF
- PLANE_INPUT_CSC_PREOFF
- PLANE_KEYMAX
- PLANE_KEYMAX_ALPHA
- PLANE_KEYMSK
- PLANE_KEYMSK_ALPHA_ENABLE
- PLANE_KEYVAL
- PLANE_NV12_BUF_CFG
- PLANE_OFF
- PLANE_OFFSET
- PLANE_POS
- PLANE_PRIMARY
- PLANE_PROP_ALPHA
- PLANE_PROP_MAX_NUM
- PLANE_PROP_PREMULTIPLIED
- PLANE_PROP_ZPOS
- PLANE_SIZE
- PLANE_SPRITE0
- PLANE_SPRITE1
- PLANE_SPRITE2
- PLANE_SPRITE3
- PLANE_SPRITE4
- PLANE_SPRITE5
- PLANE_STEREO_FORMAT_CHECKER_BOARD
- PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED
- PLANE_STEREO_FORMAT_FRAME_ALTERNATE
- PLANE_STEREO_FORMAT_NONE
- PLANE_STEREO_FORMAT_ROW_INTERLEAVED
- PLANE_STEREO_FORMAT_SIDE_BY_SIDE
- PLANE_STEREO_FORMAT_TOP_AND_BOTTOM
- PLANE_STRIDE
- PLANE_SURF
- PLANE_WM
- PLANE_WM_BLOCKS_MASK
- PLANE_WM_EN
- PLANE_WM_IGNORE_LINES
- PLANE_WM_LINES_MASK
- PLANE_WM_LINES_SHIFT
- PLANE_WM_TRANS
- PLANT_INSTR
- PLARGE_INTEGER
- PLAT8250_DEV_ACCENT
- PLAT8250_DEV_AU1X00
- PLAT8250_DEV_BOCA
- PLAT8250_DEV_EXAR_ST16C554
- PLAT8250_DEV_FOURPORT
- PLAT8250_DEV_HUB6
- PLAT8250_DEV_LEGACY
- PLAT8250_DEV_PLATFORM
- PLAT8250_DEV_PLATFORM1
- PLAT8250_DEV_PLATFORM2
- PLAT8250_DEV_SM501
- PLATFORM
- PLATFORM_ASIC
- PLATFORM_CODA_H
- PLATFORM_CONFIG_FLAGS
- PLATFORM_CONFIG_FORMAT_4_FILE_SIZE
- PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS
- PLATFORM_CONFIG_HEADER_RECORD_IDX_SHIFT
- PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS
- PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT
- PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS
- PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT
- PLATFORM_CONFIG_MAGIC_NUM
- PLATFORM_CONFIG_MAGIC_NUMBER_LEN
- PLATFORM_CONFIG_PORT_TABLE
- PLATFORM_CONFIG_QSFP_ATTEN_TABLE
- PLATFORM_CONFIG_RX_PRESET_TABLE
- PLATFORM_CONFIG_SYSTEM_TABLE
- PLATFORM_CONFIG_TABLE_MAX
- PLATFORM_CONFIG_TABLE_RESERVED
- PLATFORM_CONFIG_TX_PRESET_TABLE
- PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE
- PLATFORM_DATA_SGI_W1_H
- PLATFORM_DATA_SYSCON_H
- PLATFORM_DATA_WIZNET_H
- PLATFORM_DATA_X86_APPLE_H
- PLATFORM_DATA_XTALK_BRIDGE_H
- PLATFORM_DETECTION
- PLATFORM_DEVID_AUTO
- PLATFORM_DEVID_NONE
- PLATFORM_DRIVER
- PLATFORM_GENERIC
- PLATFORM_INFO
- PLATFORM_KEY
- PLATFORM_LPAR
- PLATFORM_MODULE_PREFIX
- PLATFORM_NAME
- PLATFORM_NAME_SIZE
- PLATFORM_NR_IRQS
- PLATFORM_PLL
- PLATFORM_POWERMAC
- PLATFORM_PSERIES
- PLATFORM_PSERIES_LPAR
- PLATFORM_RATIO
- PLATFORM_RESERVED
- PLATFORM_RESERVED2
- PLATFORM_RESERVED3
- PLATFORM_SETUP
- PLATFORM_TDP
- PLATRAM_RO
- PLATRAM_RW
- PLAT_COH901318_H
- PLAT_DRIVER_NAME
- PLAT_FPGA_IRQ_H
- PLAT_NAND_ALE
- PLAT_NAND_CLE
- PLAT_NODE_DATA_LOCALNR
- PLAT_PHYS_OFFSET
- PLAT_PM_LPM20
- PLAT_PM_SLEEP
- PLAT_RESOURCE_ACPI_IO_INDEX
- PLAT_RESOURCE_BIOS_DATA_INDEX
- PLAT_RESOURCE_BIOS_IFACE_INDEX
- PLAT_RESOURCE_GCR_OFFSET
- PLAT_RESOURCE_GCR_SIZE
- PLAT_RESOURCE_GTD_DATA_INDEX
- PLAT_RESOURCE_GTD_IFACE_INDEX
- PLAT_RESOURCE_IPC_INDEX
- PLAT_RESOURCE_IPC_SIZE
- PLAT_RESOURCE_ISP_DATA_INDEX
- PLAT_RESOURCE_ISP_IFACE_INDEX
- PLAT_RESOURCE_TELEM_SSRAM_INDEX
- PLAT_TYPE_ATCA_CP3220
- PLAT_TYPE_ATLAS
- PLAT_TYPE_INVALID
- PLAT_TYPE_NIU
- PLAT_TYPE_VF_P0
- PLAT_TYPE_VF_P1
- PLAY
- PLAYBACK_0_TO_I2S
- PLAYBACK_1_TO_SPDIF
- PLAYBACK_2_TO_AC97_1
- PLAYBACK_BLOCK_COUNTER
- PLAYBACK_BUFS
- PLAYBACK_CONFIGURED
- PLAYBACK_CONTROL
- PLAYBACK_DMA_ADDR
- PLAYBACK_DST_HP
- PLAYBACK_DST_HP_FP
- PLAYBACK_DST_MULTICH
- PLAYBACK_EFX
- PLAYBACK_EMUVOICE
- PLAYBACK_ENABLED
- PLAYBACK_END
- PLAYBACK_END_DMA_DESCR_CH12
- PLAYBACK_END_DMA_DESCR_CH13
- PLAYBACK_END_DMA_DESCR_CH8
- PLAYBACK_END_DMA_DESCR_CH9
- PLAYBACK_FIFO_ADDR_OFFSET
- PLAYBACK_FIFO_END_ADDRESS
- PLAYBACK_FIFO_OFFSET_ADDRESS
- PLAYBACK_FIFO_POINTER
- PLAYBACK_H
- PLAYBACK_LAST_SAMPLE
- PLAYBACK_LIST_ADDR
- PLAYBACK_LIST_PTR
- PLAYBACK_LIST_SIZE
- PLAYBACK_MAX_NUM_PERIODS
- PLAYBACK_MAX_PERIOD_SIZE
- PLAYBACK_MIN_NUM_PERIODS
- PLAYBACK_MIN_PERIOD_SIZE
- PLAYBACK_MUTE
- PLAYBACK_ON_SB
- PLAYBACK_PERIOD_END_ADDR
- PLAYBACK_PERIOD_SIZE
- PLAYBACK_POINTER
- PLAYBACK_ROUTING1
- PLAYBACK_ROUTING2
- PLAYBACK_SPDIF_SELECT
- PLAYBACK_SPDIF_SRC_SELECT
- PLAYBACK_SPDIF_USER_DATA0
- PLAYBACK_SPDIF_USER_DATA1
- PLAYBACK_START
- PLAYBACK_START_DMA_DESCR_CH12
- PLAYBACK_START_DMA_DESCR_CH13
- PLAYBACK_START_DMA_DESCR_CH8
- PLAYBACK_START_DMA_DESCR_CH9
- PLAYBACK_STREAM_MASK
- PLAYBACK_SUBSTREAMS
- PLAYBACK_UNKNOWN1
- PLAYBACK_UNKNOWN2
- PLAYBACK_UNKNOWN3
- PLAYBACK_UNKNOWN9
- PLAYBACK_URB_COMPLETED
- PLAYBACK_VOICE
- PLAYBACK_VOLUME1
- PLAYBACK_VOLUME2
- PLAYBACK_VOLUME_MIXER1
- PLAYBACK_VOLUME_MIXER10
- PLAYBACK_VOLUME_MIXER11
- PLAYBACK_VOLUME_MIXER12
- PLAYBACK_VOLUME_MIXER2
- PLAYBACK_VOLUME_MIXER3
- PLAYBACK_VOLUME_MIXER4
- PLAYBACK_VOLUME_MIXER5
- PLAYBACK_VOLUME_MIXER6
- PLAYBACK_VOLUME_MIXER7
- PLAYBACK_VOLUME_MIXER8
- PLAYBACK_VOLUME_MIXER9
- PLAYING
- PLAY_ENHANCEMENT
- PLAY_FREQ_RANGE_MSK
- PLA_BACKUP
- PLA_BDC_CR
- PLA_BOOT_CTRL
- PLA_BP_0
- PLA_BP_1
- PLA_BP_2
- PLA_BP_3
- PLA_BP_4
- PLA_BP_5
- PLA_BP_6
- PLA_BP_7
- PLA_BP_BA
- PLA_BP_EN
- PLA_CFG_WOL
- PLA_CONFIG12
- PLA_CONFIG34
- PLA_CONFIG5
- PLA_CONFIG6
- PLA_CPCR
- PLA_CR
- PLA_CRWECR
- PLA_DMY_REG0
- PLA_EEEP_CR
- PLA_EEE_CR
- PLA_EFUSE_CMD
- PLA_EFUSE_DATA
- PLA_EXTRA_STATUS
- PLA_FMC
- PLA_GPHY_INTR_IMR
- PLA_IDR
- PLA_INDICATE_FALG
- PLA_LEDSEL
- PLA_LED_FEATURE
- PLA_LWAKE_CTRL_REG
- PLA_MAC_PWR_CTRL
- PLA_MAC_PWR_CTRL2
- PLA_MAC_PWR_CTRL3
- PLA_MAC_PWR_CTRL4
- PLA_MAR
- PLA_MCU_SPDWN_EN
- PLA_MISC_0
- PLA_MISC_1
- PLA_MTPS
- PLA_OCP_GPHY_BASE
- PLA_OOB_CTRL
- PLA_PHYAR
- PLA_PHYSTATUS
- PLA_PHY_PWR
- PLA_RCR
- PLA_REALWOW_TIMER
- PLA_RMS
- PLA_RSTTALLY
- PLA_RXFIFO_CTRL0
- PLA_RXFIFO_CTRL1
- PLA_RXFIFO_CTRL2
- PLA_SFF_STS_7
- PLA_SUSPEND_FLAG
- PLA_TALLYCNT
- PLA_TCR0
- PLA_TCR1
- PLA_TEREDO_CFG
- PLA_TEREDO_TIMER
- PLA_TEREDO_WAKE_BASE
- PLA_TXFIFO_CTRL
- PLA_WDT6_CTRL
- PLB4OPB_GEAR
- PLB4OPB_GEARU
- PLB4OPB_GESR0
- PLB4OPB_GESR1
- PLB4OPB_GESR2
- PLB_EN
- PLC
- PLCP
- PLCP_HEADER_LENGTH
- PLCP_SIGNAL_11M
- PLCP_SIGNAL_1M
- PLCP_SIGNAL_2M
- PLCP_SIGNAL_5M5
- PLCS_BIST
- PLCS_CONTROL_C_S
- PLCS_CONTROL_C_U
- PLCS_FASSERT_S
- PLCS_FASSERT_U
- PLCS_FDEASSERT_S
- PLCS_FDEASSERT_U
- PLC_BIST
- PLC_CAM_A_BIST
- PLC_CAM_B_BIST
- PLC_ELM_B_BIST
- PLC_ELM_D_BIST
- PLC_IFD_A_BIST
- PLC_IFD_B_BIST
- PLC_INT_C
- PLC_INT_CAMEL
- PLC_INT_MASK
- PLC_INT_QE
- PLC_MS
- PLC_QELM_A_BIST
- PLC_REVISION_A
- PLC_REVISION_B
- PLC_REVISION_QA
- PLC_REVISION_S
- PLC_REV_MASK
- PLC_REV_SN3
- PLD
- PLDN_F
- PLDN_S
- PLDN_V
- PLDR
- PLDWSET
- PLDWSET_NORMAL
- PLDWSET_PULLDOWN
- PLD_ACC_TIME
- PLD_BASE_ADDR
- PLD_BASE_ADDRESS
- PLD_IMASK
- PLD_INLK0
- PLD_INLK1
- PLD_INLK2
- PLD_INLK3
- PLD_INTMODE_FIQ_ENABLE
- PLD_INTMODE_LEGACY
- PLD_INTMODE_MASK
- PLD_INTMODE_NEW_DCC
- PLD_INTMODE_NEW_NO_DCC
- PLD_LCD_BK_CONTR
- PLD_LEDCR
- PLD_LOCALCR
- PLD_MMSR
- PLD_OFF
- PLD_OUTLK0
- PLD_OUTLK1
- PLD_OUTLK2
- PLD_OUTLK3
- PLD_PCICR
- PLD_POFCR
- PLD_SHIFT
- PLD_SIZE
- PLD_SPAN_INFO
- PLD_SPAN_SET
- PLD_STATUS
- PLD_SWSR
- PLD_VERSR
- PLE
- PLEB_ETH0_P
- PLEB_ETH0_V
- PLED_LALBE
- PLED_STRATEGY_8190
- PLE_FLAG_ALL
- PLE_FLAG_MASK
- PLE_GAP
- PLE_PROPAGATE_ON_COPY
- PLE_WINDOW
- PLHMODCOD
- PLINK_CNF_AID
- PLINK_ENABLE
- PLINK_GET_LLID
- PLINK_GET_PLID
- PLINK_TRACK
- PLINK_UNDEFINED
- PLIP_CN_CLOSING
- PLIP_CN_ERROR
- PLIP_CN_NONE
- PLIP_CN_RECEIVE
- PLIP_CN_SEND
- PLIP_DELAY_UNIT
- PLIP_GET_TIMEOUT
- PLIP_MAX
- PLIP_NB_1
- PLIP_NB_2
- PLIP_NB_BEGIN
- PLIP_NIBBLE_WAIT
- PLIP_PK_CHECKSUM
- PLIP_PK_DATA
- PLIP_PK_DONE
- PLIP_PK_LENGTH_LSB
- PLIP_PK_LENGTH_MSB
- PLIP_PK_TRIGGER
- PLIP_SET_TIMEOUT
- PLIP_TRIGGER_WAIT
- PLIST_HEAD
- PLIST_HEAD_INIT
- PLIST_NODE_INIT
- PLL
- PLL0
- PLL01
- PLL02
- PLL0CTRL0
- PLL0_ADJ_REG
- PLL0_SLP_REG
- PLL0_VOTE
- PLL1
- PLL10
- PLL11
- PLL12
- PLL13
- PLL14
- PLL1460X_MDIV_MASK
- PLL14_VOTE
- PLL15
- PLL16
- PLL17
- PLL18
- PLL1CTRL0
- PLL1_ACTRL2
- PLL1_ACTRL3
- PLL1_ACTRL4
- PLL1_ACTRL5
- PLL1_ACTRL6
- PLL1_ACTRL7
- PLL1_ADJ_REG
- PLL1_CTR
- PLL1_CTRL
- PLL1_FRQ
- PLL1_P
- PLL1_Q
- PLL1_R
- PLL1_REG_BANK
- PLL1_SLP_REG
- PLL1_SW
- PLL1_SYS
- PLL2
- PLL2126_MDIV_MASK
- PLL2126_MDIV_SHIFT
- PLL2126_PDIV_MASK
- PLL2126_PDIV_SHIFT
- PLL2126_SDIV_MASK
- PLL2126_SDIV_SHIFT
- PLL2550XX_LOCK_FACTOR
- PLL2550XX_LOCK_STAT_MASK
- PLL2550XX_LOCK_STAT_SHIFT
- PLL2550XX_M_MASK
- PLL2550XX_M_SHIFT
- PLL2550XX_P_MASK
- PLL2550XX_P_SHIFT
- PLL2550XX_S_MASK
- PLL2550XX_S_SHIFT
- PLL2550X_M_MASK
- PLL2550X_M_SHIFT
- PLL2550X_P_MASK
- PLL2550X_P_SHIFT
- PLL2550X_R_MASK
- PLL2550X_R_SHIFT
- PLL2550X_S_MASK
- PLL2550X_S_SHIFT
- PLL2650XX_KDIV_MASK
- PLL2650XX_KDIV_SHIFT
- PLL2650XX_LOCK_FACTOR
- PLL2650XX_MDIV_MASK
- PLL2650XX_MDIV_SHIFT
- PLL2650XX_PDIV_MASK
- PLL2650XX_PDIV_SHIFT
- PLL2650XX_PLL_ENABLE_SHIFT
- PLL2650XX_PLL_FOUTMASK_SHIFT
- PLL2650XX_PLL_LOCKTIME_SHIFT
- PLL2650XX_SDIV_MASK
- PLL2650XX_SDIV_SHIFT
- PLL2650X_K_MASK
- PLL2650X_K_SHIFT
- PLL2650X_LOCK_FACTOR
- PLL2650X_LOCK_STAT_MASK
- PLL2650X_LOCK_STAT_SHIFT
- PLL2650X_M_MASK
- PLL2650X_M_SHIFT
- PLL2650X_PLL_ENABLE_SHIFT
- PLL2650X_P_MASK
- PLL2650X_P_SHIFT
- PLL2650X_S_MASK
- PLL2650X_S_SHIFT
- PLL2CTRL0
- PLL2_BUS
- PLL2_CTR
- PLL2_CTRL
- PLL2_FRQ
- PLL2_P
- PLL2_PFD2_396M
- PLL2_Q
- PLL2_R
- PLL3
- PLL3000_MDIV_MASK
- PLL3000_MDIV_SHIFT
- PLL3000_PDIV_MASK
- PLL3000_PDIV_SHIFT
- PLL3000_SDIV_MASK
- PLL3000_SDIV_SHIFT
- PLL312_RST_N_LBN
- PLL32KLOCKP_ER
- PLL35XX_ENABLE_SHIFT
- PLL35XX_LOCK_FACTOR
- PLL35XX_LOCK_STAT_SHIFT
- PLL35XX_MDIV_MASK
- PLL35XX_MDIV_SHIFT
- PLL35XX_PDIV_MASK
- PLL35XX_PDIV_SHIFT
- PLL35XX_SDIV_MASK
- PLL35XX_SDIV_SHIFT
- PLL36XX_ENABLE_SHIFT
- PLL36XX_KDIV_MASK
- PLL36XX_KDIV_SHIFT
- PLL36XX_LOCK_FACTOR
- PLL36XX_LOCK_STAT_SHIFT
- PLL36XX_MDIV_MASK
- PLL36XX_MDIV_SHIFT
- PLL36XX_PDIV_MASK
- PLL36XX_PDIV_SHIFT
- PLL36XX_SDIV_MASK
- PLL36XX_SDIV_SHIFT
- PLL3_CTRL
- PLL3_DO_MEAS_MASK
- PLL3_P
- PLL3_Q
- PLL3_R
- PLL3_VOTE
- PLL4
- PLL4502_LOCK_FACTOR
- PLL4508_LOCK_FACTOR
- PLL45XX_AFC_MASK
- PLL45XX_AFC_SHIFT
- PLL45XX_ENABLE
- PLL45XX_LOCKED
- PLL45XX_MDIV_MASK
- PLL45XX_MDIV_SHIFT
- PLL45XX_PDIV_MASK
- PLL45XX_PDIV_SHIFT
- PLL45XX_SDIV_MASK
- PLL45XX_SDIV_SHIFT
- PLL4650C_KDIV_MASK
- PLL46XX_ENABLE
- PLL46XX_KDIV_MASK
- PLL46XX_KDIV_SHIFT
- PLL46XX_LOCKED
- PLL46XX_LOCK_FACTOR
- PLL46XX_MDIV_MASK
- PLL46XX_MDIV_SHIFT
- PLL46XX_MFR_MASK
- PLL46XX_MFR_SHIFT
- PLL46XX_MRR_MASK
- PLL46XX_MRR_SHIFT
- PLL46XX_PDIV_MASK
- PLL46XX_PDIV_SHIFT
- PLL46XX_SDIV_MASK
- PLL46XX_SDIV_SHIFT
- PLL46XX_VSEL
- PLL46XX_VSEL_MASK
- PLL46XX_VSEL_SHIFT
- PLL4_CTRL
- PLL4_MEAS_DONE
- PLL4_P
- PLL4_Q
- PLL4_R
- PLL4_VOTE
- PLL5
- PLL5_CTRL
- PLL5_VOTE
- PLL6
- PLL6552_MDIV_MASK
- PLL6552_MDIV_SHIFT
- PLL6552_MDIV_SHIFT_2416
- PLL6552_PDIV_MASK
- PLL6552_PDIV_SHIFT
- PLL6552_PDIV_SHIFT_2416
- PLL6552_SDIV_MASK
- PLL6552_SDIV_SHIFT
- PLL6553_KDIV_MASK
- PLL6553_KDIV_SHIFT
- PLL6553_MDIV_MASK
- PLL6553_MDIV_SHIFT
- PLL6553_PDIV_MASK
- PLL6553_PDIV_SHIFT
- PLL6553_SDIV_MASK
- PLL6553_SDIV_SHIFT
- PLL6_CTRL
- PLL6_VOTE
- PLL7_CTRL
- PLL7_VOTE
- PLL8
- PLL8_VOTE
- PLL9
- PLL960_M_VAL_20
- PLL960_M_VAL_40
- PLL960_N_VAL_20
- PLL960_N_VAL_40
- PLL960_P_VAL_20
- PLL960_P_VAL_40
- PLLA1_BASE
- PLLA1_MISC0
- PLLA1_MISC1
- PLLA1_MISC2
- PLLA1_MISC3
- PLLALNCTL
- PLLARMLOCKP_ER
- PLLARMLOCKP_ERR
- PLLASET1
- PLLASET2
- PLLA_BASE
- PLLA_BASE_IDDQ
- PLLA_BASE_LOCK
- PLLA_IDDQ_BIT
- PLLA_MISC
- PLLA_MISC0
- PLLA_MISC0_DEFAULT_VALUE
- PLLA_MISC0_LOCK_ENABLE
- PLLA_MISC0_LOCK_OVERRIDE
- PLLA_MISC0_WRITE_MASK
- PLLA_MISC1
- PLLA_MISC2
- PLLA_MISC2_DEFAULT_VALUE
- PLLA_MISC2_EN_DYNRAMP
- PLLA_MISC2_EN_SDM
- PLLA_MISC2_WRITE_MASK
- PLLA_MISC_LOCK_ENABLE
- PLLA_OUT
- PLLA_SDM_DIN_MASK
- PLLA_SDM_EN_MASK
- PLLBCLK_ADDR
- PLLBSET1
- PLLBSET2
- PLLBYP
- PLLB_REF_INPUT_SPREADSPECTRUMIN
- PLLC
- PLLC2_BASE
- PLLC2_MISC
- PLLC2_MISC0
- PLLC2_MISC1
- PLLC2_MISC2
- PLLC2_MISC3
- PLLC3_BASE
- PLLC3_MISC
- PLLC3_MISC0
- PLLC3_MISC1
- PLLC3_MISC2
- PLLC3_MISC3
- PLLC4_BASE
- PLLC4_MISC
- PLLC4_MISC0
- PLLC4_MISC0_DEFAULT_VALUE
- PLLC4_OUT
- PLLCC_CDR_107_154_MHZ
- PLLCC_CDR_111_160_MHZ
- PLLCC_CDR_144_205_MHZ
- PLLCC_CDR_150_215_MHZ
- PLLCC_CDR_167_239_MHZ
- PLLCC_CDR_184_265_MHZ
- PLLCC_CDR_227_330_MHZ
- PLLCC_CDR_240_350_MHZ
- PLLCC_CDR_271_398_MHZ
- PLLCC_CDR_45_58_MHZ
- PLLCC_CDR_52_74_MHZ
- PLLCC_CDR_63_90_MHZ
- PLLCC_CDR_67_96_MHZ
- PLLCC_CDR_73_104_MHZ
- PLLCC_CDR_87_123_MHZ
- PLLCC_CDR_98_140_MHZ
- PLLCC_CDR_MASK
- PLLCC_LPF_1050_2780_KHZ
- PLLCC_LPF_14360_37270_KHZ
- PLLCC_LPF_1740_4580_KHZ
- PLLCC_LPF_23850_60000_KHZ
- PLLCC_LPF_2540_6690_KHZ
- PLLCC_LPF_25580_64530_KHZ
- PLLCC_LPF_317_798_KHZ
- PLLCC_LPF_4160_10980_KHZ
- PLLCC_LPF_450_1160_KHZ
- PLLCC_LPF_6100_16020_KHZ
- PLLCC_LPF_724_1910_KHZ
- PLLCC_LPF_7960_26290_KHZ
- PLLCC_LPF_MASK
- PLLCKEN
- PLLCKSTAT
- PLLCLK
- PLLCLK_IN_MASK
- PLLCLK_IN_SHIFT
- PLLCMD
- PLLCMD_GOSET
- PLLCMD_GOSTAT
- PLLCON1
- PLLCONTROL_0_FREQ_DET_RESTART
- PLLCONTROL_0_FREQ_MONITOR
- PLLCONTROL_0_SEQ_START
- PLLCON_FBDV
- PLLCON_INDV
- PLLCON_LOKI
- PLLCON_LOKS
- PLLCON_OTDV1
- PLLCON_OTDV2
- PLLCON_PWDEN
- PLLCR
- PLLCR_ADDR
- PLLCR_CLKEN
- PLLCR_DISPLL
- PLLCR_LCDCLK_SEL_MASK
- PLLCR_LCDCLK_SEL_SHIFT
- PLLCR_PIXCLK_SEL_MASK
- PLLCR_PIXCLK_SEL_SHIFT
- PLLCR_PRESC
- PLLCR_SYSCLK_SEL_MASK
- PLLCR_SYSCLK_SEL_SHIFT
- PLLCTL
- PLLCTL0
- PLLCTL1
- PLLCTL_AD
- PLLCTL_AS
- PLLCTL_B
- PLLCTL_BYPASS
- PLLCTL_CLKMODE
- PLLCTL_ENABLE
- PLLCTL_FD
- PLLCTL_LF
- PLLCTL_M_MASK
- PLLCTL_M_SHIFT
- PLLCTL_N_MASK
- PLLCTL_N_SHIFT
- PLLCTL_OD
- PLLCTL_OD_MASK
- PLLCTL_OD_SHIFT
- PLLCTL_PLLCLKEN_DISABLE
- PLLCTL_PLLCLKEN_ENABLE
- PLLCTL_PLLDIS
- PLLCTL_PLLEN
- PLLCTL_PLLENSRC
- PLLCTL_PLLPWRDN
- PLLCTL_PLLRST
- PLLCTL_PU_PLL_PWR_DWN
- PLLCTL_PU_PLL_PWR_UP
- PLLCTL_RD
- PLLCTL_SPE
- PLLCTL_SPS
- PLLCTL_SRC
- PLLCTL_STABLE
- PLLCTRL0
- PLLCTRL1
- PLLCTRL2
- PLLCTRL_BPQUAL_MASK
- PLLCTRL_CFG1
- PLLCTRL_CFG2
- PLLCTRL_CFG3
- PLLCTRL_CFG4
- PLLCTRL_FBDIV_MASK
- PLLCTRL_FBDIV_SHIFT
- PLLCTRL_PLL_CONTROL
- PLLCTRL_PLL_GO
- PLLCTRL_PLL_STATUS
- PLLCTRL_PWRDWN_MASK
- PLLCTRL_PWRDWN_SHIFT
- PLLCTRL_RESET_MASK
- PLLCTRL_RESET_SHIFT
- PLLCTRL_SSC_CFG1
- PLLCTRL_SSC_CFG2
- PLLCX_BASE_LOCK
- PLLCX_IDDQ_BIT
- PLLCX_MISC0_DEFAULT_VALUE
- PLLCX_MISC0_RESET
- PLLCX_MISC0_WRITE_MASK
- PLLCX_MISC1_DEFAULT
- PLLCX_MISC1_DEFAULT_VALUE
- PLLCX_MISC1_IDDQ
- PLLCX_MISC1_WRITE_MASK
- PLLCX_MISC2_DEFAULT
- PLLCX_MISC2_DEFAULT_VALUE
- PLLCX_MISC2_WRITE_MASK
- PLLCX_MISC3_DEFAULT
- PLLCX_MISC3_DEFAULT_VALUE
- PLLCX_MISC3_WRITE_MASK
- PLLCX_MISC_ALPHA_SHIFT
- PLLCX_MISC_COEF_LOW_RANGE
- PLLCX_MISC_DEFAULT
- PLLCX_MISC_DIV_HIGH_RANGE
- PLLCX_MISC_DIV_LOW_RANGE
- PLLCX_MISC_FILT_DIV_MASK
- PLLCX_MISC_FILT_DIV_SHIFT
- PLLCX_MISC_KA_SHIFT
- PLLCX_MISC_KB_SHIFT
- PLLCX_MISC_RESET
- PLLCX_MISC_SDM_DIV_MASK
- PLLCX_MISC_SDM_DIV_SHIFT
- PLLCX_MISC_STROBE
- PLLCX_RESET_BIT
- PLLC_BASE
- PLLC_IDDQ_BIT
- PLLC_MISC
- PLLC_MISC0
- PLLC_MISC1
- PLLC_MISC2
- PLLC_MISC3
- PLLC_MISC_LOCK_ENABLE
- PLLC_OUT
- PLLC_SRC_MASK
- PLLD2_BASE
- PLLD2_MISC
- PLLD2_MISC0
- PLLD2_MISC0_DEFAULT_VALUE
- PLLD2_MISC1
- PLLD2_MISC1_CFG_DEFAULT_VALUE
- PLLD2_MISC2
- PLLD2_MISC2_CTRL1_DEFAULT_VALUE
- PLLD2_MISC3
- PLLD2_MISC3_CTRL2_DEFAULT_VALUE
- PLLD2_SDM_EN_MASK
- PLLD2_SSC_EN_MASK
- PLLDCD
- PLLDCHANGE
- PLLDDRLOCKP_ER
- PLLDDRLOCKP_ERR
- PLLDITHEN0
- PLLDITHEN1
- PLLDIV1
- PLLDIV10
- PLLDIV11
- PLLDIV12
- PLLDIV13
- PLLDIV14
- PLLDIV15
- PLLDIV16
- PLLDIV2
- PLLDIV3
- PLLDIV4
- PLLDIV5
- PLLDIV6
- PLLDIV7
- PLLDIV8
- PLLDIV9
- PLLDIV_EN
- PLLDIV_MASK
- PLLDIV_RATIO
- PLLDIV_RATIO_MASK
- PLLDP_BASE
- PLLDP_MISC
- PLLDP_MISC0_DEFAULT_VALUE
- PLLDP_MISC1_CFG_DEFAULT_VALUE
- PLLDP_MISC2_CTRL1_DEFAULT_VALUE
- PLLDP_MISC3_CTRL2_DEFAULT_VALUE
- PLLDP_SDM_EN_MASK
- PLLDP_SSC_EN_MASK
- PLLDP_SS_CFG
- PLLDP_SS_CTRL1
- PLLDP_SS_CTRL2
- PLLDSS_BASE_IDDQ
- PLLDSS_BASE_LOCK
- PLLDSS_BASE_LOCK_OVERRIDE
- PLLDSS_BASE_REF_SEL_MASK
- PLLDSS_BASE_REF_SEL_SHIFT
- PLLDSS_MISC0_LOCK_ENABLE
- PLLDSS_MISC0_WRITE_MASK
- PLLDSS_MISC1_CFG_EN_SDM
- PLLDSS_MISC1_CFG_EN_SSC
- PLLDSS_MISC1_CFG_WRITE_MASK
- PLLDSS_MISC2_CTRL1_WRITE_MASK
- PLLDSS_MISC3_CTRL2_WRITE_MASK
- PLLDU_LFCON_SET_DIVN
- PLLDU_MISC_LOCK_ENABLE
- PLLD_BASE
- PLLD_BASE_CSI_CLKSOURCE
- PLLD_FBDV_MASK
- PLLD_FWDVA_MASK
- PLLD_FWDVB_MASK
- PLLD_IDDQ_BIT
- PLLD_LSB_SHIFT
- PLLD_MASK
- PLLD_MISC
- PLLD_MISC0
- PLLD_MISC0_DEFAULT_VALUE
- PLLD_MISC0_DSI_CLKENABLE
- PLLD_MISC0_EN_SDM
- PLLD_MISC0_IDDQ
- PLLD_MISC0_LOCK_ENABLE
- PLLD_MISC0_LOCK_OVERRIDE
- PLLD_MISC0_WRITE_MASK
- PLLD_MISC1
- PLLD_MISC1_DEFAULT_VALUE
- PLLD_MISC1_WRITE_MASK
- PLLD_MISC_LOCK_ENABLE
- PLLD_MSB_SHIFT
- PLLD_SDM_EN_MASK
- PLLEN
- PLLE_AUX
- PLLE_AUX_ENABLE_SWCTL
- PLLE_AUX_PLLP_SEL
- PLLE_AUX_PLLRE_SEL
- PLLE_AUX_SEQ_ENABLE
- PLLE_AUX_SEQ_START_STATE
- PLLE_AUX_SS_SEQ_INCLUDE
- PLLE_AUX_SS_SWCTL
- PLLE_AUX_USE_LOCKDET
- PLLE_BASE
- PLLE_BASE_DIVCML_MASK
- PLLE_BASE_DIVCML_SHIFT
- PLLE_BASE_DIVM_SHIFT
- PLLE_BASE_DIVM_WIDTH
- PLLE_BASE_DIVN_SHIFT
- PLLE_BASE_DIVN_WIDTH
- PLLE_BASE_DIVP_SHIFT
- PLLE_BASE_DIVP_WIDTH
- PLLE_BASE_ENABLE
- PLLE_MISC
- PLLE_MISC0
- PLLE_MISC_IDDQ_SW_CTRL
- PLLE_MISC_IDDQ_SW_VALUE
- PLLE_MISC_LOCK
- PLLE_MISC_LOCK_ENABLE
- PLLE_MISC_PLLE_PTS
- PLLE_MISC_READY
- PLLE_MISC_SETUP_BASE_MASK
- PLLE_MISC_SETUP_BASE_SHIFT
- PLLE_MISC_SETUP_EX_MASK
- PLLE_MISC_SETUP_EX_SHIFT
- PLLE_MISC_SETUP_MASK
- PLLE_MISC_SETUP_VALUE
- PLLE_MISC_VREG_BG_CTRL_MASK
- PLLE_MISC_VREG_BG_CTRL_SHIFT
- PLLE_MISC_VREG_CTRL_MASK
- PLLE_MISC_VREG_CTRL_SHIFT
- PLLE_SS_CNTL_BYPASS_SS
- PLLE_SS_CNTL_CENTER
- PLLE_SS_CNTL_INTERP_RESET
- PLLE_SS_CNTL_INVERT
- PLLE_SS_CNTL_SSC_BYP
- PLLE_SS_COEFFICIENTS_MASK
- PLLE_SS_COEFFICIENTS_VAL_TEGRA114
- PLLE_SS_COEFFICIENTS_VAL_TEGRA210
- PLLE_SS_CTRL
- PLLE_SS_DISABLE
- PLLE_SS_INCINTRV_MASK
- PLLE_SS_INCINTRV_VAL_TEGRA114
- PLLE_SS_INCINTRV_VAL_TEGRA210
- PLLE_SS_INC_MASK
- PLLE_SS_INC_VAL
- PLLE_SS_MAX_MASK
- PLLE_SS_MAX_VAL_TEGRA114
- PLLE_SS_MAX_VAL_TEGRA210
- PLLFCFG_FRAC_EN
- PLLFCLK_ADDR
- PLLFH
- PLLFL
- PLLFM
- PLLFRACCTL
- PLLFRACIN
- PLLFSR
- PLLFSR_ADDR
- PLLFSR_CLK32
- PLLFSR_PC_MASK
- PLLFSR_PC_SHIFT
- PLLFSR_PROT
- PLLFSR_QC_MASK
- PLLFSR_QC_SHIFT
- PLLJ_SHIFT
- PLLLOCK
- PLLLOCK_CMP
- PLLLOCK_CMP_EN
- PLLM
- PLLMB_BASE
- PLLMB_BASE_LOCK
- PLLMB_IDDQ_BIT
- PLLMB_MISC1
- PLLMB_MISC1_DEFAULT_VALUE
- PLLMB_MISC1_IDDQ
- PLLMB_MISC1_LOCK_ENABLE
- PLLMB_MISC1_LOCK_OVERRIDE
- PLLMB_MISC1_WRITE_MASK
- PLLMB_MISC_LOCK_ENABLE
- PLLMUL_MASK
- PLLM_BASE
- PLLM_HIGH_MASK
- PLLM_HIGH_SHIFT
- PLLM_IDDQ_BIT
- PLLM_LOW_MASK
- PLLM_MASK
- PLLM_MISC
- PLLM_MISC1
- PLLM_MISC2
- PLLM_MISC_LOCK_ENABLE
- PLLM_OUT
- PLLM_PLLM_MASK
- PLLM_SHIFT
- PLLM_VAL
- PLLNDIV
- PLLNH
- PLLNL
- PLLPOST
- PLLPRE
- PLLPREDIV_EN
- PLLPREDIV_VAL
- PLLP_BASE
- PLLP_BASE_LOCK
- PLLP_BASE_OVERRIDE
- PLLP_MASK
- PLLP_MISC
- PLLP_MISC0
- PLLP_MISC0_DEFAULT_VALUE
- PLLP_MISC0_IDDQ
- PLLP_MISC0_LOCK_ENABLE
- PLLP_MISC0_LOCK_OVERRIDE
- PLLP_MISC0_WRITE_MASK
- PLLP_MISC1
- PLLP_MISC1_DEFAULT_VALUE
- PLLP_MISC1_HSIO_EN
- PLLP_MISC1_HSIO_EN_SHIFT
- PLLP_MISC1_WRITE_MASK
- PLLP_MISC1_XUSB_EN
- PLLP_MISC1_XUSB_EN_SHIFT
- PLLP_MISC_LOCK_ENABLE
- PLLP_OUTA
- PLLP_OUTB
- PLLP_OUTC
- PLLP_SHIFT
- PLLQ_SHIFT
- PLLR1_FIXED_CLOCK
- PLLR1_REG
- PLLRE_BASE
- PLLRE_BASE_DEFAULT_MASK
- PLLRE_BASE_DEFAULT_VALUE
- PLLRE_IDDQ_BIT
- PLLRE_MISC
- PLLRE_MISC0
- PLLRE_MISC0_DEFAULT_VALUE
- PLLRE_MISC0_IDDQ
- PLLRE_MISC0_LOCK
- PLLRE_MISC0_LOCK_ENABLE
- PLLRE_MISC0_LOCK_OVERRIDE
- PLLRE_MISC0_WRITE_MASK
- PLLRE_MISC_LOCK
- PLLRE_MISC_LOCK_ENABLE
- PLLRE_OUT1
- PLLR_SHIFT
- PLLS3C2410_ENABLE_REG_OFFSET
- PLLS3C2410_MDIV_MASK
- PLLS3C2410_MDIV_SHIFT
- PLLS3C2410_PDIV_MASK
- PLLS3C2410_PDIV_SHIFT
- PLLS3C2410_SDIV_MASK
- PLLS3C2410_SDIV_SHIFT
- PLLSECCTL
- PLLSEL_TV_CRTC1_MASK
- PLLSEL_TV_CRTC2_MASK
- PLLSEL_TV_MASK
- PLLSEL_VPLL1_MASK
- PLLSEL_VPLL2_MASK
- PLLSET
- PLLSH_COEX_PLL_M
- PLLSH_COEX_PLL_N
- PLLSH_COEX_PLL_SWALLOW_EN
- PLLSH_COEX_PLL_SWALLOW_EN_VAL1
- PLLSH_COEX_PLL_SWALLOW_EN_VAL2
- PLLSH_WCS_PLL_M
- PLLSH_WCS_PLL_N
- PLLSH_WCS_PLL_P_FACTOR_CFG_1
- PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK
- PLLSH_WCS_PLL_P_FACTOR_CFG_2
- PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK
- PLLSH_WCS_PLL_Q_FACTOR_CFG_1
- PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK
- PLLSH_WCS_PLL_Q_FACTOR_CFG_2
- PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK
- PLLSH_WCS_PLL_SWALLOW_EN
- PLLSH_WCS_PLL_SWALLOW_EN_VAL1
- PLLSH_WCS_PLL_SWALLOW_EN_VAL2
- PLLSH_WL_PLL_EN
- PLLSH_WL_PLL_EN_VAL1
- PLLSH_WL_PLL_EN_VAL2
- PLLSH_WL_PLL_SEL
- PLLSH_WL_PLL_SEL_COEX_PLL
- PLLSH_WL_PLL_SEL_WCS_PLL
- PLLSOC0LOCKP_ERR
- PLLSOC1LOCKP_ERR
- PLLSOCK1LOCKP_ER
- PLLSOCLOCKP_ER
- PLLSRC
- PLLSS_CFG_DEFAULT
- PLLSS_CLAMP
- PLLSS_CTRL1_DEFAULT
- PLLSS_CTRL2_DEFAULT
- PLLSS_EN_DITHER
- PLLSS_EN_DITHER2
- PLLSS_EN_SDM
- PLLSS_EN_SSC
- PLLSS_IDDQ_BIT
- PLLSS_LOCK_OVERRIDE
- PLLSS_MISC_DEFAULT
- PLLSS_MISC_KCP
- PLLSS_MISC_KVCO
- PLLSS_MISC_LOCK_ENABLE
- PLLSS_MISC_SETUP
- PLLSS_REF_SRC_SEL_MASK
- PLLSS_REF_SRC_SEL_SHIFT
- PLLSS_SDM_DIN
- PLLSS_SDM_RESET
- PLLSS_SDM_SSC_MAX
- PLLSS_SDM_SSC_MIN
- PLLSS_SDM_SSC_STEP
- PLLSTAT
- PLLSTAT_B
- PLLSTAT_CCS
- PLLSTAT_CFD
- PLLSTAT_CORE_PLL_LOST_L
- PLLSTAT_CORE_PLL_LSTS
- PLLSTAT_CRD
- PLLSTAT_DISP_PLL_LOST_L
- PLLSTAT_DISP_PLL_LSTS
- PLLSTAT_FAS
- PLLSTAT_GOSTAT
- PLLSTAT_NCA
- PLLSTAT_OCA
- PLLSTAT_PD
- PLLSTAT_PLLLK_LOCKED
- PLLSTAT_PLLLK_UNLOCKED
- PLLSTAT_SL
- PLLSTAT_SPL
- PLLSTRB
- PLLSTRBYP
- PLLSYSTAT
- PLLS_BASE
- PLLS_I8xx
- PLLS_I9xx
- PLLS_MAX
- PLLS_MISC
- PLLUPDATE
- PLLU_BASE
- PLLU_BASE_CLKENABLE_48M
- PLLU_BASE_CLKENABLE_ALL
- PLLU_BASE_CLKENABLE_HSIC
- PLLU_BASE_CLKENABLE_ICUSB
- PLLU_BASE_CLKENABLE_USB
- PLLU_BASE_LOCK
- PLLU_BASE_OVERRIDE
- PLLU_HW_PWRDN_CFG0
- PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL
- PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL
- PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE
- PLLU_HW_PWRDN_CFG0_SEQ_ENABLE
- PLLU_HW_PWRDN_CFG0_USE_LOCKDET
- PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT
- PLLU_IDDQ_BIT
- PLLU_MISC
- PLLU_MISC0
- PLLU_MISC0_DEFAULT_VALUE
- PLLU_MISC0_IDDQ
- PLLU_MISC0_LOCK_ENABLE
- PLLU_MISC0_WRITE_MASK
- PLLU_MISC1
- PLLU_MISC1_DEFAULT_VALUE
- PLLU_MISC1_LOCK_OVERRIDE
- PLLU_MISC1_WRITE_MASK
- PLLU_MISC_LOCK_ENABLE
- PLLU_OUTA
- PLLU_POST_DIVP_MASK
- PLLVAL
- PLLXC_SW_MAX_P
- PLLXP_IDDQ_BIT
- PLLX_BASE
- PLLX_BASE_LOCK
- PLLX_HW_CTRL_CFG
- PLLX_HW_CTRL_CFG_SWCTRL
- PLLX_IDDQ_BIT
- PLLX_MISC
- PLLX_MISC0
- PLLX_MISC0_DEFAULT_VALUE
- PLLX_MISC0_FO_G_DISABLE
- PLLX_MISC0_LOCK_ENABLE
- PLLX_MISC0_WRITE_MASK
- PLLX_MISC1
- PLLX_MISC1_DEFAULT_VALUE
- PLLX_MISC1_WRITE_MASK
- PLLX_MISC2
- PLLX_MISC2_DEFAULT_VALUE
- PLLX_MISC2_DYNRAMP_DONE
- PLLX_MISC2_DYNRAMP_STEPA_MASK
- PLLX_MISC2_DYNRAMP_STEPA_SHIFT
- PLLX_MISC2_DYNRAMP_STEPB_MASK
- PLLX_MISC2_DYNRAMP_STEPB_SHIFT
- PLLX_MISC2_EN_DYNRAMP
- PLLX_MISC2_LOCK_OVERRIDE
- PLLX_MISC2_NDIV_NEW_MASK
- PLLX_MISC2_NDIV_NEW_SHIFT
- PLLX_MISC2_WRITE_MASK
- PLLX_MISC3
- PLLX_MISC3_DEFAULT_VALUE
- PLLX_MISC3_IDDQ
- PLLX_MISC3_WRITE_MASK
- PLLX_MISC4
- PLLX_MISC4_DEFAULT_VALUE
- PLLX_MISC4_WRITE_MASK
- PLLX_MISC5
- PLLX_MISC5_DEFAULT_VALUE
- PLLX_MISC5_WRITE_MASK
- PLLX_USE_DYN_RAMP
- PLL_0
- PLL_1
- PLL_14
- PLL_1416X
- PLL_1416X_RATE
- PLL_1443X
- PLL_1443X_RATE
- PLL_2064_CAL_REF_TO
- PLL_2064_D30
- PLL_2064_D30_DOUBLER
- PLL_2064_HIGH_END_KVCO
- PLL_2064_HIGH_END_VCO
- PLL_2064_LOOP_BW
- PLL_2064_LOOP_BW_DOUBLER
- PLL_2064_LOW_END_KVCO
- PLL_2064_LOW_END_VCO
- PLL_2064_MHZ
- PLL_2064_NDIV
- PLL_2064_OPEN_LOOP_DELAY
- PLL_28
- PLL_35
- PLL_35XX_RATE
- PLL_36XX_RATE
- PLL_4508_RATE
- PLL_4600_RATE
- PLL_4650_RATE
- PLL_4x
- PLL_6x
- PLL_8x
- PLL_AB_DIAG_CTRL
- PLL_ACTIVE_FLAG
- PLL_ACTRL2
- PLL_ACTRL2_SELDIV_MASK
- PLL_ACTRL2_SELDIV_SHIFT
- PLL_ACTRL6
- PLL_ADDR
- PLL_AFE1_100MHZ_BLK
- PLL_ALPHA_EN
- PLL_ALPHA_MODE
- PLL_ALPHA_VAL
- PLL_ALPHA_VAL_U
- PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK
- PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT
- PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK
- PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT
- PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK
- PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT
- PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL_MASK
- PLL_ANALOG_CNTL__PLL_CALIB_FASTCAL__SHIFT
- PLL_ANALOG_CNTL__PLL_CALIB_FBDIV_MASK
- PLL_ANALOG_CNTL__PLL_CALIB_FBDIV__SHIFT
- PLL_ANALOG_CNTL__PLL_REGREF_TRIM_MASK
- PLL_ANALOG_CNTL__PLL_REGREF_TRIM__SHIFT
- PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN_MASK
- PLL_ANALOG_CNTL__PLL_TEST_SSAMP_EN__SHIFT
- PLL_ANALOG__PLL_CAL_MODE_MASK
- PLL_ANALOG__PLL_CAL_MODE__SHIFT
- PLL_ANALOG__PLL_CP_MASK
- PLL_ANALOG__PLL_CP__SHIFT
- PLL_ANALOG__PLL_IBIAS_MASK
- PLL_ANALOG__PLL_IBIAS__SHIFT
- PLL_ANALOG__PLL_LF_MODE_MASK
- PLL_ANALOG__PLL_LF_MODE__SHIFT
- PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK
- PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT
- PLL_ANALOG__PLL_VREG_FB_TRIM_MASK
- PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT
- PLL_AO
- PLL_APLL
- PLL_APLLB
- PLL_APLLL
- PLL_ARM
- PLL_ARM_DIV_792M
- PLL_ARST_REG
- PLL_A_INT_FRAC
- PLL_A_POST_STAT_BIST
- PLL_B
- PLL_BASE_BYPASS
- PLL_BASE_DIVM_SHIFT
- PLL_BASE_DIVM_WIDTH
- PLL_BASE_DIVN_SHIFT
- PLL_BASE_DIVN_WIDTH
- PLL_BASE_DIVP_SHIFT
- PLL_BASE_DIVP_WIDTH
- PLL_BASE_ENABLE
- PLL_BASE_LOCK
- PLL_BASE_OVERRIDE
- PLL_BASE_REF_ENABLE
- PLL_BC_SHIFT
- PLL_BIAS_COUNT_MASK
- PLL_BIAS_COUNT_SHIFT
- PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL
- PLL_BLOCK
- PLL_BLOCK_MACH64
- PLL_BP_SHIFT
- PLL_BR_SHIFT
- PLL_BW_BADREF
- PLL_BW_GOODREF
- PLL_BW_VBADREF
- PLL_BW_VGOODREF
- PLL_BYPASS
- PLL_BYPASS1
- PLL_BYPASS2
- PLL_BYPASSNL
- PLL_BYPASS_CYCLES
- PLL_BYPASS_MASK
- PLL_BYPASS_NONE
- PLL_BYPASS_TIME
- PLL_B_INT_FRAC
- PLL_B_POST_STAT_BIST
- PLL_C
- PLL_CAL_L_VAL
- PLL_CAL_TIME
- PLL_CAL_VAL
- PLL_CAP_CHARGE_TIME
- PLL_CAP_CONTROL
- PLL_CCTRL
- PLL_CD_DIAG_CTRL
- PLL_CFG0
- PLL_CFG1
- PLL_CFG2
- PLL_CFG_EN
- PLL_CFG_ENPLL
- PLL_CFG_IDF_SHIFT
- PLL_CFG_IF_SOFT_RESET
- PLL_CFG_IF_SOFT_RESET_FORCE
- PLL_CFG_IF_SOFT_RESET_NOOP
- PLL_CFG_LD
- PLL_CFG_LD_SHIFT
- PLL_CFG_MPY
- PLL_CFG_MPY_10X
- PLL_CFG_MPY_12P5X
- PLL_CFG_MPY_12X
- PLL_CFG_MPY_4X
- PLL_CFG_MPY_5X
- PLL_CFG_MPY_6X
- PLL_CFG_MPY_8X
- PLL_CFG_MPY_SHIFT
- PLL_CFG_NDIV_SHIFT
- PLL_CFG_ODF_SHIFT
- PLL_CFG_OFFSET
- PLL_CFG_STD
- PLL_CFG_STD_SHIFT
- PLL_CLAMP
- PLL_CLAMP_ON
- PLL_CLKDIV_SHIFT
- PLL_CLKIN_SHIFT
- PLL_CLK_AMP_2P05V
- PLL_CLK_AMP_OFFSET
- PLL_CLK_CFG
- PLL_CLK_COUNT
- PLL_CLK_COUNT_COUNTER_MASK
- PLL_CNTL
- PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK
- PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT
- PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK
- PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT
- PLL_CNTL__PLL_BYPASS_CAL_MASK
- PLL_CNTL__PLL_BYPASS_CAL__SHIFT
- PLL_CNTL__PLL_CALIB_DONE_MASK
- PLL_CNTL__PLL_CALIB_DONE__SHIFT
- PLL_CNTL__PLL_CALREF_MASK
- PLL_CNTL__PLL_CALREF__SHIFT
- PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK
- PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT
- PLL_CNTL__PLL_DIG_SPARE_MASK
- PLL_CNTL__PLL_DIG_SPARE__SHIFT
- PLL_CNTL__PLL_LOCKED_MASK
- PLL_CNTL__PLL_LOCKED__SHIFT
- PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK
- PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT
- PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK
- PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT
- PLL_CNTL__PLL_POST_DIV_SRC_MASK
- PLL_CNTL__PLL_POST_DIV_SRC__SHIFT
- PLL_CNTL__PLL_POWER_DOWN_MASK
- PLL_CNTL__PLL_POWER_DOWN__SHIFT
- PLL_CNTL__PLL_REFCLK_RECV_EN_MASK
- PLL_CNTL__PLL_REFCLK_RECV_EN__SHIFT
- PLL_CNTL__PLL_REFCLK_RECV_SEL_MASK
- PLL_CNTL__PLL_REFCLK_RECV_SEL__SHIFT
- PLL_CNTL__PLL_REFCLK_SEL_MASK
- PLL_CNTL__PLL_REFCLK_SEL__SHIFT
- PLL_CNTL__PLL_REF_DIV_SRC_MASK
- PLL_CNTL__PLL_REF_DIV_SRC__SHIFT
- PLL_CNTL__PLL_RESET_MASK
- PLL_CNTL__PLL_RESET__SHIFT
- PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK
- PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT
- PLL_CNTL__PLL_VCOREF_MASK
- PLL_CNTL__PLL_VCOREF__SHIFT
- PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK
- PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT
- PLL_CONFIGURATION1
- PLL_CONFIGURATION2
- PLL_CONFIGURATION3
- PLL_CONFIGURATION4
- PLL_CONFIG_CTL
- PLL_CONFIG_CTL_U
- PLL_CONFIG_CTL_U1
- PLL_CONTROL
- PLL_CORE
- PLL_COUNT_SHIFT
- PLL_CPLL
- PLL_CPSETI
- PLL_CPSETP
- PLL_CPU_REG
- PLL_CP_CONTROL_PLL_LOCK_BYPASS
- PLL_CP_CURRENT_CTRL
- PLL_CSR_OFFSET
- PLL_CTL
- PLL_CTL0_EN
- PLL_CTL0_LOCK_DIG
- PLL_CTL0_M
- PLL_CTL0_N
- PLL_CTL0_RST
- PLL_CTL0_SEL
- PLL_CTRL
- PLL_CTRL1
- PLL_CTRL1_FBDIV_MASK
- PLL_CTRL1_FBDIV_SHIFT
- PLL_CTRL1_REFDIV_MASK
- PLL_CTRL1_REFDIV_SHIFT
- PLL_CTRL2
- PLL_CTRL3
- PLL_CTRL4
- PLL_CTRL_BYPASS
- PLL_CTRL_DIRECT
- PLL_CTRL_ENABLE
- PLL_CTRL_FAST
- PLL_CTRL_FEEDBACK
- PLL_CTRL_FEEDDIV
- PLL_CTRL_INPUT
- PLL_CTRL_LOCK
- PLL_CTRL_M_MASK
- PLL_CTRL_M_SHIFT
- PLL_CTRL_N_MASK
- PLL_CTRL_N_SHIFT
- PLL_CTRL_OD_MASK
- PLL_CTRL_OD_SHIFT
- PLL_CTRL_PIN
- PLL_CTRL_POD_MASK
- PLL_CTRL_POD_SHIFT
- PLL_CTRL_POSTDIV
- PLL_CTRL_POWER
- PLL_CTRL_PREDIV
- PLL_CTRL_REG
- PLL_C_INT_FRAC
- PLL_C_POST_STAT_BIST
- PLL_DATA
- PLL_DBG
- PLL_DDR_REG
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT
- PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT
- PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT
- PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK
- PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT
- PLL_DELAY
- PLL_DENOM_OFFSET
- PLL_DIAG_CTRL
- PLL_DIRECT
- PLL_DIRECT_BYPASS
- PLL_DISABLE_STATE
- PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK
- PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK
- PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT
- PLL_DITH_FDBK_M_MASK
- PLL_DITH_FDBK_M_SHIFT
- PLL_DIV
- PLL_DIV1
- PLL_DIV2
- PLL_DIV2_SEL
- PLL_DIV3
- PLL_DIV4
- PLL_DIVEN_SHIFT
- PLL_DIVF1_MASK
- PLL_DIVF1_MAX
- PLL_DIVF2_MASK
- PLL_DIVF2_MAX
- PLL_DIVISOR_REG
- PLL_DIVQ_MASK
- PLL_DIVQ_MAX
- PLL_DIVR1_MASK
- PLL_DIVR1_MAX
- PLL_DIVR2_MASK
- PLL_DIVR2_MAX
- PLL_DIV_FFEN
- PLL_DIV_MASK
- PLL_DIV_MAX
- PLL_DIV_N_MASK
- PLL_DIV_N_SHIFT
- PLL_DIV_ORD
- PLL_DIV_P_MASK
- PLL_DIV_P_SHIFT
- PLL_DIV_S
- PLL_DPLL
- PLL_DS_CNTL__PLL_DS_FRAC_MASK
- PLL_DS_CNTL__PLL_DS_FRAC__SHIFT
- PLL_DS_CNTL__PLL_DS_MODE_MASK
- PLL_DS_CNTL__PLL_DS_MODE__SHIFT
- PLL_DS_CNTL__PLL_DS_ORDER_MASK
- PLL_DS_CNTL__PLL_DS_ORDER__SHIFT
- PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK
- PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT
- PLL_DUTY_CYC
- PLL_D_INT_FRAC
- PLL_D_POST_STAT_BIST
- PLL_EF_DIAG_CTRL
- PLL_EN
- PLL_ENABLE
- PLL_ENABLE_STATE
- PLL_ENB
- PLL_ERRATA
- PLL_ERROR
- PLL_EXPO_PDIV_MAX
- PLL_EXT_CNTL
- PLL_FACTOR
- PLL_FACT_MAX
- PLL_FBDIV_MAX
- PLL_FBDIV_MIN
- PLL_FBDIV_REG
- PLL_FBKDIV_SHIFT
- PLL_FBKSEL_SHIFT
- PLL_FB_DIV_96
- PLL_FB_DIV_MASK
- PLL_FB_DIV_OFF
- PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK
- PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT
- PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK
- PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT
- PLL_FB_DIV__PLL_FB_DIV_MASK
- PLL_FB_DIV__PLL_FB_DIV__SHIFT
- PLL_FIX
- PLL_FIXED
- PLL_FRAC
- PLL_FRAC_ACK_TIMEOUT
- PLL_FRAC_CTRL2_FRAC_MASK
- PLL_FRAC_CTRL2_FRAC_SHIFT
- PLL_FRAC_CTRL2_POSTDIV1_MASK
- PLL_FRAC_CTRL2_POSTDIV1_SHIFT
- PLL_FRAC_CTRL2_POSTDIV2_MASK
- PLL_FRAC_CTRL2_POSTDIV2_SHIFT
- PLL_FRAC_CTRL3_DACPD
- PLL_FRAC_CTRL3_DSMPD
- PLL_FRAC_CTRL3_FOUT4PHASEPD
- PLL_FRAC_CTRL3_FOUTPOSTDIVPD
- PLL_FRAC_CTRL3_FOUTVCOPD
- PLL_FRAC_CTRL3_PD
- PLL_FRAC_CTRL4_BYPASS
- PLL_FRAC_DENOM
- PLL_FRAC_DIV_MASK
- PLL_FRAC_LOCK_TIMEOUT
- PLL_FREQ_DET_TIME
- PLL_FSM_ENA
- PLL_FVCO_MHZ
- PLL_GEN_CNTL
- PLL_GF40LP_FRAC
- PLL_GF40LP_LAINT
- PLL_GH_DIAG_CTRL
- PLL_GO
- PLL_GPLL
- PLL_GPLL_DIV2
- PLL_GPLL_DIV3
- PLL_HAS_CLKMODE
- PLL_HAS_EXTCLKSRC
- PLL_HAS_MUL
- PLL_HAS_POST
- PLL_HAS_POSTDIV
- PLL_HAS_PRE
- PLL_HAS_PREDIV
- PLL_HIGH
- PLL_HIGH_DEFAULT
- PLL_HOLDOVER
- PLL_HUAYRA_ALPHA_WIDTH
- PLL_HUAYRA_M_MASK
- PLL_HUAYRA_M_SHIFT
- PLL_HUAYRA_M_WIDTH
- PLL_HUAYRA_N_MASK
- PLL_HUAYRA_N_SHIFT
- PLL_I2S
- PLL_IBIAS
- PLL_ICLK_MASK
- PLL_ICLK_SHIFT
- PLL_ICPR_MASK
- PLL_ICPR_SHIFT
- PLL_IC_SHIFT
- PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR_MASK
- PLL_IDCLK_CNTL__PLL_CML_A_DRVSTR__SHIFT
- PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR_MASK
- PLL_IDCLK_CNTL__PLL_CML_B_DRVSTR__SHIFT
- PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK
- PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT
- PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK
- PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT
- PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK
- PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT
- PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT
- PLL_IDCLK_CNTL__PLL_IDCLK_EN_MASK
- PLL_IDCLK_CNTL__PLL_IDCLK_EN__SHIFT
- PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK
- PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT
- PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK
- PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT
- PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK
- PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT
- PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK
- PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT
- PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK
- PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT
- PLL_IDIV_MASK
- PLL_IDIV_REG
- PLL_IDIV_SHIFT
- PLL_IDLE
- PLL_IDLE_TIME
- PLL_IMX7_DENOM_OFFSET
- PLL_IMX7_NUM_OFFSET
- PLL_INDEX
- PLL_INFF_MAX_RATE_HZ
- PLL_INFF_MIN_RATE_HZ
- PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL
- PLL_INPUT_BCLK
- PLL_INPUT_DIVIDER_RATIO
- PLL_INPUT_DIV_EN
- PLL_INPUT_MCLK1
- PLL_INPUT_MCLK2
- PLL_INPUT_XTAL
- PLL_INT
- PLL_INTEGER
- PLL_INT_CTRL1_DSMPD
- PLL_INT_CTRL1_FOUTPOSTDIVPD
- PLL_INT_CTRL1_FOUTVCOPD
- PLL_INT_CTRL1_PD
- PLL_INT_CTRL1_POSTDIV1_MASK
- PLL_INT_CTRL1_POSTDIV1_SHIFT
- PLL_INT_CTRL1_POSTDIV2_MASK
- PLL_INT_CTRL1_POSTDIV2_SHIFT
- PLL_INT_CTRL2_BYPASS
- PLL_INT_DIV_MASK
- PLL_IPSETI
- PLL_IPSETP
- PLL_IR_SHIFT
- PLL_ISO_EN
- PLL_KILL
- PLL_KINT
- PLL_L
- PLL_LAST
- PLL_LD
- PLL_LDOPWDN
- PLL_LDO_PWR_ON
- PLL_LOAD_PULSE_PHASE_MASK
- PLL_LOAD_PULSE_PHASE_SHIFT
- PLL_LOCK
- PLL_LOCKDET_DELAY
- PLL_LOCKED
- PLL_LOCK_CHG
- PLL_LOCK_CONVERSION
- PLL_LOCK_COUNTERS_COEX
- PLL_LOCK_COUNTERS_MCS
- PLL_LOCK_COUNTERS_REG
- PLL_LOCK_COUNT_MASK
- PLL_LOCK_COUNT_SHIFT
- PLL_LOCK_CTRL
- PLL_LOCK_CYCLES
- PLL_LOCK_DELAY_US
- PLL_LOCK_DET
- PLL_LOCK_DONE
- PLL_LOCK_MASK
- PLL_LOCK_N
- PLL_LOCK_REG
- PLL_LOCK_RETRY
- PLL_LOCK_RETRY_COUNT
- PLL_LOCK_SHIFT
- PLL_LOCK_SLEEP
- PLL_LOCK_STATUS
- PLL_LOCK_TIME
- PLL_LOCK_TIMEOUT
- PLL_LOCK_TIMEOUT_US
- PLL_LOCK_TIME_US
- PLL_LOOP_DIVIDER_RATIO
- PLL_LOOP_DIV_EN
- PLL_LOW
- PLL_LPF_AND_CP_CONTROL
- PLL_LPF_C1_CTRL
- PLL_LPF_C2_CTRL
- PLL_LPF_R1
- PLL_L_MASK
- PLL_L_SHIFT
- PLL_L_VAL
- PLL_M
- PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK
- PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT
- PLL_MASK
- PLL_MAX
- PLL_MAX_COUNT
- PLL_MAX_ID
- PLL_MAX_LOCK_TIME
- PLL_MCLK_RST
- PLL_MEMCLK_100000KHZ
- PLL_MEMCLK_SEL
- PLL_MEMCLK__66667KHZ
- PLL_MEMCLK__75000KHZ
- PLL_MEMCLK__88889KHZ
- PLL_MEMORY
- PLL_MFB_TIMES_4_2B
- PLL_MISC_CPCON_MASK
- PLL_MISC_CPCON_SHIFT
- PLL_MISC_CPCON_WIDTH
- PLL_MISC_DCCON_SHIFT
- PLL_MISC_LFCON_MASK
- PLL_MISC_LFCON_SHIFT
- PLL_MISC_LFCON_WIDTH
- PLL_MISC_LOCK_ENABLE
- PLL_MISC_VCOCON_MASK
- PLL_MISC_VCOCON_SHIFT
- PLL_MISC_VCOCON_WIDTH
- PLL_MOD
- PLL_MODE
- PLL_MODE_DEEP
- PLL_MODE_DITH_DSM
- PLL_MODE_DITH_SSM
- PLL_MODE_FRAC
- PLL_MODE_FRACTION
- PLL_MODE_INT
- PLL_MODE_MASK
- PLL_MODE_NORM
- PLL_MODE_NORMAL
- PLL_MODE_SHIFT
- PLL_MODE_SLOW
- PLL_MOD_EN
- PLL_MUL
- PLL_MULTIPLIER
- PLL_MULT_MASK
- PLL_MULT_MAX
- PLL_MULT_SHIFT
- PLL_MUL_MASK
- PLL_MUL_MAX
- PLL_MUL_MIN
- PLL_MUX_NUM_PARENT
- PLL_N
- PLL_NDIV
- PLL_NDIV_FRAC
- PLL_NDIV_INT
- PLL_NEWDIV_ACK
- PLL_NEWDIV_VAL
- PLL_NINT
- PLL_NONE
- PLL_NON_INTEGER
- PLL_NORM_FDBK_M_MASK
- PLL_NORM_FDBK_M_SHIFT
- PLL_NPLL
- PLL_NUM_OFFSET
- PLL_ODIV0_REG
- PLL_ODIV1_REG
- PLL_ODIV_MASK
- PLL_ODIV_MAX
- PLL_ODIV_MIN
- PLL_ODIV_SHIFT
- PLL_OFFLINE_ACK
- PLL_OFFLINE_REQ
- PLL_OFF_ALPHA_VAL
- PLL_OFF_ALPHA_VAL_U
- PLL_OFF_CAL_L_VAL
- PLL_OFF_CAL_VAL
- PLL_OFF_CONFIG_CTL
- PLL_OFF_CONFIG_CTL_U
- PLL_OFF_CONFIG_CTL_U1
- PLL_OFF_FRAC
- PLL_OFF_L_VAL
- PLL_OFF_MAX_REGS
- PLL_OFF_OPMODE
- PLL_OFF_STATUS
- PLL_OFF_TEST_CTL
- PLL_OFF_TEST_CTL_U
- PLL_OFF_USER_CTL
- PLL_OFF_USER_CTL_U
- PLL_OFF_USER_CTL_U1
- PLL_ON
- PLL_OPMODE
- PLL_OSC_SEL
- PLL_OUT
- PLL_OUTCTRL
- PLL_OUTPUT_DIV_MASK
- PLL_OUT_HZ_48
- PLL_OUT_MAX_FREQ
- PLL_OUT_MIN_FREQ
- PLL_OUT_SHIFT
- PLL_OVERRIDE
- PLL_P1_DIVIDE_BY_TWO
- PLL_P2_DIVIDE_BY_4
- PLL_PARAMS
- PLL_PC_GAIN
- PLL_PDIV
- PLL_PDN
- PLL_PD_MASK
- PLL_PFD_DELAY_CTRL
- PLL_PLLCTRL_1
- PLL_PLLCTRL_2
- PLL_PLLCTRL_4
- PLL_PLLM_2X
- PLL_POSTDIV
- PLL_POSTDIV_ALWAYS_ENABLED
- PLL_POSTDIV_FIXED_DIV
- PLL_POST_DIV_MASK
- PLL_POST_DIV_SHIFT
- PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK
- PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT
- PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK
- PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT
- PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK
- PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT
- PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK
- PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT
- PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK
- PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT
- PLL_POST_LOCK_DELAY
- PLL_POWER_ENABLE
- PLL_POWER_STATE
- PLL_POWER_STATE_IN_OFF_0
- PLL_POWER_STATE_IN_OFF_0_MASK
- PLL_POWER_STATE_IN_OFF_0_SHIFT
- PLL_POWER_STATE_IN_OFF_1
- PLL_POWER_STATE_IN_OFF_1_MASK
- PLL_POWER_STATE_IN_OFF_1_SHIFT
- PLL_POWER_STATE_IN_OFF_2
- PLL_POWER_STATE_IN_OFF_2_MASK
- PLL_POWER_STATE_IN_OFF_2_SHIFT
- PLL_POWER_STATE_IN_OFF_3
- PLL_POWER_STATE_IN_OFF_3_MASK
- PLL_POWER_STATE_IN_OFF_3_SHIFT
- PLL_POWER_STATE_IN_TXS2_0
- PLL_POWER_STATE_IN_TXS2_0_MASK
- PLL_POWER_STATE_IN_TXS2_0_SHIFT
- PLL_POWER_STATE_IN_TXS2_1
- PLL_POWER_STATE_IN_TXS2_1_MASK
- PLL_POWER_STATE_IN_TXS2_1_SHIFT
- PLL_POWER_STATE_IN_TXS2_2
- PLL_POWER_STATE_IN_TXS2_2_MASK
- PLL_POWER_STATE_IN_TXS2_2_SHIFT
- PLL_POWER_STATE_IN_TXS2_3
- PLL_POWER_STATE_IN_TXS2_3_MASK
- PLL_POWER_STATE_IN_TXS2_3_SHIFT
- PLL_PPLL
- PLL_PREDIV
- PLL_PREDIV_ALWAYS_ENABLED
- PLL_PREDIV_FIXED8
- PLL_PREDIV_FIXED_DIV
- PLL_PRESCALE_BY_2
- PLL_PRESCALE_BY_3
- PLL_PRESCALE_BY_4
- PLL_PRESCALE_BY_5
- PLL_PWRMGT_CNTL
- PLL_PWRMGT_CNTL_MOBILE_SU
- PLL_PWRMGT_CNTL_P2PLL_TURNOFF
- PLL_PWRMGT_CNTL_PPLL_TURNOFF
- PLL_PWRMGT_CNTL_SPLL_TURNOFF
- PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK
- PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK
- PLL_PWRMGT_CNTL_TVPLL_TURNOFF
- PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK
- PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK
- PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK
- PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK
- PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND
- PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK
- PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND
- PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK
- PLL_PWRMGT_CNTL__MOBILE_SU
- PLL_PWRMGT_CNTL__MOBILE_SU_MASK
- PLL_PWRMGT_CNTL__MPLL_TURNOFF
- PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK
- PLL_PWRMGT_CNTL__P2PLL_TURNOFF
- PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK
- PLL_PWRMGT_CNTL__PM_MODE_SEL
- PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK
- PLL_PWRMGT_CNTL__PPLL_TURNOFF
- PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK
- PLL_PWRMGT_CNTL__SPLL_TURNOFF
- PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK
- PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK
- PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK
- PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK
- PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK
- PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE
- PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK
- PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE
- PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK
- PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD
- PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK
- PLL_PWRMGT_CNTL__TVPLL_TURNOFF
- PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK
- PLL_PWR_DOWN_TIME_US
- PLL_PWR_ON
- PLL_QLIN_PDIV_MAX
- PLL_RAMP_UP_TIME_0
- PLL_RAMP_UP_TIME_0_MASK
- PLL_RAMP_UP_TIME_0_SHIFT
- PLL_RAMP_UP_TIME_1
- PLL_RAMP_UP_TIME_1_MASK
- PLL_RAMP_UP_TIME_1_SHIFT
- PLL_RAMP_UP_TIME_2
- PLL_RAMP_UP_TIME_2_MASK
- PLL_RAMP_UP_TIME_2_SHIFT
- PLL_RAMP_UP_TIME_3
- PLL_RAMP_UP_TIME_3_MASK
- PLL_RAMP_UP_TIME_3_SHIFT
- PLL_RANGE_MASK
- PLL_RANGE_SHIFT
- PLL_RATE
- PLL_RAW
- PLL_RCTRL
- PLL_RDY
- PLL_READY
- PLL_READY_GATE_EN
- PLL_REFCLK
- PLL_REFIN
- PLL_REF_CLK
- PLL_REF_DIV
- PLL_REF_DIV_5
- PLL_REF_DIV_MASK
- PLL_REF_DIV_OFF
- PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK
- PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT
- PLL_REF_DIV__PLL_REF_DIV_MASK
- PLL_REF_DIV__PLL_REF_DIV__SHIFT
- PLL_REF_INPUT_DREFCLK
- PLL_REF_INPUT_MASK
- PLL_REF_INPUT_TVCLKINA
- PLL_REF_INPUT_TVCLKINBC
- PLL_REF_MASK
- PLL_REF_MAX_FREQ
- PLL_REF_MIN_FREQ
- PLL_REF_SDVO_HDMI_MULTIPLIER
- PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
- PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
- PLL_REG
- PLL_REGM_F_MASK
- PLL_REGM_F_SHIFT
- PLL_REGM_MASK
- PLL_REGM_SHIFT
- PLL_REGN_MASK
- PLL_REGN_SHIFT
- PLL_REG_BANK_0
- PLL_REG_BANK_0_PLLCONTROL_0
- PLL_REG_FBDIV
- PLL_REG_GET_BYPASS
- PLL_REG_GET_EDGE
- PLL_REG_GET_HIGH
- PLL_REG_GET_LOW
- PLL_REG_GET_NOUPD
- PLL_REG_GET_PAD
- PLL_REG_IDIV
- PLL_REG_ODIV
- PLL_REG_SETTINGS_COUNT
- PLL_REG_SET_BYPASS
- PLL_REG_SET_EDGE
- PLL_REG_SET_HIGH
- PLL_REG_SET_LOW
- PLL_REG_SET_NOUPD
- PLL_REG_SET_PAD
- PLL_RESERVED_INPUT1
- PLL_RESERVED_INPUT2
- PLL_RESET
- PLL_RESETB
- PLL_RESET_COMPLETE_TIME
- PLL_RESET_CYCLES
- PLL_RESET_N
- PLL_RESET_TIME
- PLL_RESUME
- PLL_RK3328_MODE_MASK
- PLL_RXCLK_EN
- PLL_RX_CFG_ALIGN_DIS
- PLL_RX_CFG_ALIGN_ENA
- PLL_RX_CFG_ALIGN_JOG
- PLL_RX_CFG_BSINRXN
- PLL_RX_CFG_BSINRXP
- PLL_RX_CFG_BUSWIDTH
- PLL_RX_CFG_BUSWIDTH_SHIFT
- PLL_RX_CFG_CDR
- PLL_RX_CFG_CDR_SHIFT
- PLL_RX_CFG_ENRX
- PLL_RX_CFG_ENTEST
- PLL_RX_CFG_EQ_LP_1084MHZ
- PLL_RX_CFG_EQ_LP_135MHZ
- PLL_RX_CFG_EQ_LP_156MHZ
- PLL_RX_CFG_EQ_LP_216MHZ
- PLL_RX_CFG_EQ_LP_304MHZ
- PLL_RX_CFG_EQ_LP_402MHZ
- PLL_RX_CFG_EQ_LP_573MHZ
- PLL_RX_CFG_EQ_LP_805MHZ
- PLL_RX_CFG_EQ_LP_ADAPTIVE
- PLL_RX_CFG_EQ_MAX_LF
- PLL_RX_CFG_EQ_SHIFT
- PLL_RX_CFG_INVPAIR
- PLL_RX_CFG_LOS_DIS
- PLL_RX_CFG_LOS_HTHRESH
- PLL_RX_CFG_LOS_LTHRESH
- PLL_RX_CFG_RATE
- PLL_RX_CFG_RATE_FULL
- PLL_RX_CFG_RATE_HALF
- PLL_RX_CFG_RATE_QUAD
- PLL_RX_CFG_RATE_SHIFT
- PLL_RX_CFG_TERM_0P8VDDT
- PLL_RX_CFG_TERM_FLOAT
- PLL_RX_CFG_TERM_VDDT
- PLL_RX_STS_BSRXN
- PLL_RX_STS_BSRXP
- PLL_RX_STS_CRCIDTCT
- PLL_RX_STS_CWDTCT
- PLL_RX_STS_LOSDTCT
- PLL_RX_STS_ODDCG
- PLL_RX_STS_SYNC
- PLL_RX_STS_TESTFAIL
- PLL_S3C2410_MPLL_RATE
- PLL_S3C2440_MPLL_RATE
- PLL_SAI
- PLL_SCCG_LOCK_TIMEOUT
- PLL_SDM_COEFF
- PLL_SDM_EN
- PLL_SD_MASK
- PLL_SD_SHIFT
- PLL_SELECT_MASK
- PLL_SELFREQDCO_MASK
- PLL_SELFREQDCO_SHIFT
- PLL_SEL_LPFR_MASK
- PLL_SEL_LPFR_OFF
- PLL_SEQ_START
- PLL_SERIAL_1_SRL_FDN
- PLL_SERIAL_1_SRL_IZ
- PLL_SERIAL_1_SRL_MAN_IZ
- PLL_SERIAL_2_SRL_NOSC
- PLL_SERIAL_2_SRL_PR
- PLL_SERIAL_3_SRL_CCIR
- PLL_SERIAL_3_SRL_DE
- PLL_SERIAL_3_SRL_PXIN_SEL
- PLL_SHADER
- PLL_SLEEP_STATE
- PLL_SNOOZE_STATE
- PLL_SOC0_OFF
- PLL_SOC0_ON
- PLL_SOC1_OFF
- PLL_SOC1_ON
- PLL_SSC_CONFIGURATION1
- PLL_SSC_CONFIGURATION2
- PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK
- PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT
- PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK
- PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT
- PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK
- PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT
- PLL_SS_CNTL__PLL_SS_EN_MASK
- PLL_SS_CNTL__PLL_SS_EN__SHIFT
- PLL_SS_CNTL__PLL_SS_MODE_MASK
- PLL_SS_CNTL__PLL_SS_MODE__SHIFT
- PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK
- PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT
- PLL_STAGE1_MAX_FREQ
- PLL_STAGE1_MIN_FREQ
- PLL_STAGE1_REF_MAX_FREQ
- PLL_STAGE1_REF_MIN_FREQ
- PLL_STAGE2_MAX_FREQ
- PLL_STAGE2_MIN_FREQ
- PLL_STAGE2_REF_MAX_FREQ
- PLL_STAGE2_REF_MIN_FREQ
- PLL_START
- PLL_STAT
- PLL_STATUS
- PLL_STATUS_LOCK
- PLL_STATUS_MASK
- PLL_STS_LOCK
- PLL_TEST_CFG_CLKBYP
- PLL_TEST_CFG_CLKBYP_SHIFT
- PLL_TEST_CFG_ENBSAC
- PLL_TEST_CFG_ENBSRX
- PLL_TEST_CFG_ENBSTX
- PLL_TEST_CFG_EN_RXPATT
- PLL_TEST_CFG_EN_TXPATT
- PLL_TEST_CFG_LOOPBACK_CML_DIS
- PLL_TEST_CFG_LOOPBACK_CML_EN
- PLL_TEST_CFG_LOOPBACK_PAD
- PLL_TEST_CFG_TPATT
- PLL_TEST_CFG_TPATT_SHIFT
- PLL_TEST_CNTL
- PLL_TEST_CNTL__REF_TEST_COUNT_MASK
- PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT
- PLL_TEST_CNTL__TEST_COUNT_MASK
- PLL_TEST_CNTL__TEST_COUNT__SHIFT
- PLL_TEST_CNTL__TST_REF_SEL_MASK
- PLL_TEST_CNTL__TST_REF_SEL__SHIFT
- PLL_TEST_CNTL__TST_RESET_MASK
- PLL_TEST_CNTL__TST_RESET__SHIFT
- PLL_TEST_CNTL__TST_SRC_SEL_MASK
- PLL_TEST_CNTL__TST_SRC_SEL__SHIFT
- PLL_TEST_COUNT
- PLL_TEST_CTL
- PLL_TEST_CTL_U
- PLL_TEST_INVPATT
- PLL_TEST_RATE
- PLL_TEST_RATE_SHIFT
- PLL_TICOPWDN
- PLL_TIMEOUT
- PLL_TIMEOUT_MS
- PLL_TIMER
- PLL_TXCLK_EN
- PLL_TXDIV_SHIFT
- PLL_TX_CFG_BSTX
- PLL_TX_CFG_BUSWIDTH
- PLL_TX_CFG_BUSWIDTH_SHIFT
- PLL_TX_CFG_CM
- PLL_TX_CFG_DE
- PLL_TX_CFG_DE_SHIFT
- PLL_TX_CFG_ENFTP
- PLL_TX_CFG_ENIDL
- PLL_TX_CFG_ENTEST
- PLL_TX_CFG_ENTX
- PLL_TX_CFG_INVPAIR
- PLL_TX_CFG_RATE
- PLL_TX_CFG_RATE_FULL
- PLL_TX_CFG_RATE_HALF
- PLL_TX_CFG_RATE_QUAD
- PLL_TX_CFG_RATE_SHIFT
- PLL_TX_CFG_RDTCT
- PLL_TX_CFG_RDTCT_SHIFT
- PLL_TX_CFG_SWING_1000MV
- PLL_TX_CFG_SWING_1250MV
- PLL_TX_CFG_SWING_125MV
- PLL_TX_CFG_SWING_1375MV
- PLL_TX_CFG_SWING_250MV
- PLL_TX_CFG_SWING_500MV
- PLL_TX_CFG_SWING_625MV
- PLL_TX_CFG_SWING_750MV
- PLL_TX_STS_RDTCTIP
- PLL_TX_STS_TESTFAIL
- PLL_TYPE_PCP
- PLL_TYPE_SOC
- PLL_TYPE_VT8500
- PLL_TYPE_WM8650
- PLL_TYPE_WM8750
- PLL_TYPE_WM8850
- PLL_UNK03
- PLL_UNK40
- PLL_UNK41
- PLL_UNK42
- PLL_UNKNOWN
- PLL_UNLOCK
- PLL_UNLOCKED
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK
- PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT
- PLL_UPDATE
- PLL_UPDATE_BYPASS
- PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK
- PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT
- PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK
- PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT
- PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK
- PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT
- PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK
- PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT
- PLL_USER_CTL
- PLL_USER_CTL_U
- PLL_USER_CTL_U1
- PLL_USER_MODE
- PLL_V2CLK_CNTL
- PLL_VALID
- PLL_VALID_RATE
- PLL_VBGBK_EN
- PLL_VCLK0_XDIV
- PLL_VCLK1_XDIV
- PLL_VCLK2_XDIV
- PLL_VCLK3_XDIV
- PLL_VCLK_CNTL
- PLL_VCLK_INVERT
- PLL_VCLK_RST
- PLL_VCLK_SRC_SEL
- PLL_VCO_CAL_THRESH
- PLL_VCO_HIGH_SHIFT
- PLL_VCO_I2S
- PLL_VCO_LOW_SHIFT
- PLL_VCO_MASK
- PLL_VCO_SAI
- PLL_VCO_SHIFT
- PLL_VC_GAIN
- PLL_VDEC
- PLL_VF610_DENOM_OFFSET
- PLL_VF610_NUM_OFFSET
- PLL_VGA_REG
- PLL_VLD
- PLL_VOTE_FSM_ENA
- PLL_VOTE_FSM_RESET
- PLL_VPLL
- PLL_VPLL0
- PLL_VPLL1
- PLL_VPLL2
- PLL_VPLL3
- PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK
- PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT
- PLL_VREG_CNTL__PLL_VREF_SEL_MASK
- PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT
- PLL_VREG_CNTL__PLL_VREG_BIAS_MASK
- PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT
- PLL_VREG_CNTL__PLL_VREG_CNTL_MASK
- PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT
- PLL_WRAP_CNTRL1__wrap_cfg_sel_clk_MASK
- PLL_WRAP_CNTRL1__wrap_cfg_sel_clk__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy_MASK
- PLL_WRAP_CNTRL__wrap_cfg_clk_gate_w_rdy__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel_MASK
- PLL_WRAP_CNTRL__wrap_cfg_cml_cmos_sel__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_dsm_sel__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_freq_programming_ovveride__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_pwr_state_ovrride__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_rdy_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_rdy__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_pll_update_MASK
- PLL_WRAP_CNTRL__wrap_cfg_pll_update__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg_MASK
- PLL_WRAP_CNTRL__wrap_cfg_ref_values_chg__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val_MASK
- PLL_WRAP_CNTRL__wrap_cfg_tx_pdiv_val__SHIFT
- PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val_MASK
- PLL_WRAP_CNTRL__wrap_cfg_tx_pixdiv_val__SHIFT
- PLL_WR_EN
- PLL_XCLK_MCLK_RATIO
- PLL_XCLK_SRC_SEL
- PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN_MASK
- PLL_XOR_LOCK__PLL_FAST_LOCK_MODE_EN__SHIFT
- PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL_MASK
- PLL_XOR_LOCK__PLL_LOCK_COUNT_SEL__SHIFT
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS_MASK
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_OPAMP_BIAS__SHIFT
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB_MASK
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FFB__SHIFT
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF_MASK
- PLL_XOR_LOCK__PLL_LOCK_DETECTOR_RESOLUTION_FREF__SHIFT
- PLL_XOR_LOCK__PLL_SPARE_MASK
- PLL_XOR_LOCK__PLL_SPARE__SHIFT
- PLL_XOR_LOCK__PLL_XOR_LOCK_MASK
- PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK
- PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT
- PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT
- PLL_YCLK_CNTL
- PLL_calcclock
- PLL_xtal
- PLN_ADDR_TYPE_GRAPHICS
- PLN_ADDR_TYPE_GRPH_STEREO
- PLN_ADDR_TYPE_VIDEO_PROGRESSIVE
- PLOGI_ACC_RCVD
- PLOGI_RCVD
- PLOGI_RJT_RCVD
- PLOGO_RCVD
- PLONG
- PLOOPBK
- PLPAR_HCALL9_BUFSIZE
- PLPAR_HCALL_BUFSIZE
- PLRITY
- PLROOT0
- PLROOT1
- PLROOT2
- PLR_OFFSET
- PLSB_MAP_SIZE
- PLST
- PLSTATIM
- PLS_CONFIGLT
- PLS_CONFIGLT_CONFIGURE
- PLS_CONFIGLT_LINK_TRANSFER_ACTIVE
- PLS_CONFIGPHY
- PLS_CONFIGPHY_DEBOUCE
- PLS_CONFIGPHY_ESTCOMM
- PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE
- PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT
- PLS_CONFIGPHY_OPTEQ
- PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE
- PLS_CONFIGPHY_OPTEQ_OPTIMIZING
- PLS_CONFIGPHY_VERIFYCAP
- PLS_CONFIGPHY_VERIFYCAP_EXCHANGE
- PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE
- PLS_DISABLED
- PLS_INTERNAL_SERDES_LOOPBACK
- PLS_LINKUP
- PLS_LINK_SPD
- PLS_LINK_SPD_OFFS
- PLS_NEG_LINK_WD
- PLS_NEG_LINK_WD_OFFS
- PLS_OFFLINE
- PLS_OFFLINE_PLANNED_DOWN_INFORM
- PLS_OFFLINE_QUIET
- PLS_OFFLINE_QUIET_DURATION
- PLS_OFFLINE_READY_TO_QUIET_BCC
- PLS_OFFLINE_READY_TO_QUIET_LT
- PLS_OFFLINE_REPORT_FAILURE
- PLS_PHYTEST
- PLS_POLLING
- PLS_POLLING_ACTIVE
- PLS_POLLING_QUIET
- PLS_QUICK_LINKUP
- PLT1_VOL_DOWN
- PLT1_VOL_UP
- PLT2_VOL_DOWN
- PLT2_VOL_UP
- PLT_ALLOW_CONSUMER
- PLT_ASYM_RX
- PLT_ASYM_TX
- PLT_BASIC_EXCEPTION
- PLT_BASIC_TELEPHONY
- PLT_BT300_MAX
- PLT_BT300_MIN
- PLT_CHIP_AWAKE
- PLT_CLK_NAME_BASE
- PLT_DA60
- PLT_ENTRY_SIZE
- PLT_ENT_COUNT
- PLT_ENT_LDR
- PLT_ENT_SIZE
- PLT_ENT_STRIDE
- PLT_FEM_DETECT
- PLT_HID_1_0_PAGE
- PLT_HID_2_0_PAGE
- PLT_INPROG_PHY
- PLT_MASK
- PLT_OFF
- PLT_ON
- PLT_RX_CALIBRATION_COMPLETE_EVENT_ID
- PLT_SYM
- PLT_VOL_DOWN
- PLT_VOL_UP
- PLUG
- PLUGGED_DELAY
- PLUGIN_DEBUG
- PLUGSB4RESET
- PLUG_CONTROL_ENABLE
- PLUG_MAX_CHK_2X
- PLUG_MAX_MSG_1X
- PLUG_MAX_OPC_64
- PLUG_MIN_OPC_8
- PLUG_MIN_SPACE_1
- PLUG_PAGE_SIZE_256
- PLUP_F
- PLUP_S
- PLUP_V
- PLURAL
- PLUS
- PLUTO_GART_SIZE
- PLUTO_IOC_OFFSET
- PLUTO_IOVA_BASE
- PLUTO_IOVA_SIZE
- PLUTO_MCKINLEY_PORT
- PLX9030_INTCSR
- PLX9052_CNTRL
- PLX9052_CNTRL_CS2
- PLX9052_CNTRL_CS3
- PLX9052_CNTRL_EEPROM_CLK
- PLX9052_CNTRL_EEPROM_CS
- PLX9052_CNTRL_EEPROM_DIN
- PLX9052_CNTRL_EEPROM_DOUT
- PLX9052_CNTRL_EEPROM_MASK
- PLX9052_CNTRL_EEPROM_PRESENT
- PLX9052_CNTRL_LLOCKO
- PLX9052_CNTRL_LOCK_ENAB
- PLX9052_CNTRL_MASK_REV
- PLX9052_CNTRL_PCI2_1_FEATURES
- PLX9052_CNTRL_PCIBAR
- PLX9052_CNTRL_PCIBAR0
- PLX9052_CNTRL_PCIBAR01
- PLX9052_CNTRL_PCIBAR1
- PLX9052_CNTRL_PCI_RESET
- PLX9052_CNTRL_PCI_R_NO_FLUSH
- PLX9052_CNTRL_PCI_R_NO_WRITE
- PLX9052_CNTRL_PCI_R_W_FLUSH
- PLX9052_CNTRL_PCI_W_RELEASE
- PLX9052_CNTRL_RELOAD_CFG
- PLX9052_CNTRL_RETRY_CLKS
- PLX9052_CNTRL_UIO0_DATA
- PLX9052_CNTRL_UIO0_DIR
- PLX9052_CNTRL_UIO1_DATA
- PLX9052_CNTRL_UIO1_DIR
- PLX9052_CNTRL_UIO2_DATA
- PLX9052_CNTRL_UIO2_DIR
- PLX9052_CNTRL_UIO3_DATA
- PLX9052_CNTRL_UIO3_DIR
- PLX9052_CNTRL_WAITO
- PLX9052_INTCSR
- PLX9052_INTCSR_ISAMODE
- PLX9052_INTCSR_LI1CLRINT
- PLX9052_INTCSR_LI1ENAB
- PLX9052_INTCSR_LI1POL
- PLX9052_INTCSR_LI1SEL
- PLX9052_INTCSR_LI1STAT
- PLX9052_INTCSR_LI2CLRINT
- PLX9052_INTCSR_LI2ENAB
- PLX9052_INTCSR_LI2POL
- PLX9052_INTCSR_LI2SEL
- PLX9052_INTCSR_LI2STAT
- PLX9052_INTCSR_PCIENAB
- PLX9052_INTCSR_SOFTINT
- PLX9056_CNTRL
- PLX9056_INTCSR
- PLX9056_LINTI
- PLX9056_PCI_INT_EN
- PLX9056_PCI_RCR
- PLXDEV
- PLX_2280
- PLX_9050
- PLX_9060
- PLX_9080
- PLX_BASE
- PLX_BIGEND_BEBLM
- PLX_BIGEND_CONFIG
- PLX_BIGEND_DM
- PLX_BIGEND_DMA
- PLX_BIGEND_DMA0
- PLX_BIGEND_DMA1
- PLX_BIGEND_DSAS0
- PLX_BIGEND_DSAS1
- PLX_BIGEND_EROM
- PLX_CNTRL
- PLX_CNTRL_CCRDM
- PLX_CNTRL_CCRDMA
- PLX_CNTRL_CCRDMA_MASK
- PLX_CNTRL_CCRDMA_NORMAL
- PLX_CNTRL_CCRDM_MASK
- PLX_CNTRL_CCRDM_NORMAL
- PLX_CNTRL_CCWDM
- PLX_CNTRL_CCWDMA
- PLX_CNTRL_CCWDMA_MASK
- PLX_CNTRL_CCWDMA_NORMAL
- PLX_CNTRL_CCWDM_MASK
- PLX_CNTRL_CCWDM_NORMAL
- PLX_CNTRL_CC_MASK
- PLX_CNTRL_CC_NORMAL
- PLX_CNTRL_EECS
- PLX_CNTRL_EEPRESENT
- PLX_CNTRL_EERB
- PLX_CNTRL_EERELOAD
- PLX_CNTRL_EESK
- PLX_CNTRL_EEWB
- PLX_CNTRL_INITDONE
- PLX_CNTRL_RESET
- PLX_CNTRL_SERIAL_EEPROM_PRESENT
- PLX_CNTRL_TO_CCRDM
- PLX_CNTRL_TO_CCRDMA
- PLX_CNTRL_TO_CCWDM
- PLX_CNTRL_TO_CCWDMA
- PLX_CNTRL_USERI
- PLX_CNTRL_USERO
- PLX_CONTROL
- PLX_CTL_RESET
- PLX_DBPBAM_PFLIMIT
- PLX_DMACSR_ABORT
- PLX_DMACSR_CLEARINTR
- PLX_DMACSR_DONE
- PLX_DMACSR_ENABLE
- PLX_DMACSR_START
- PLX_DMADPR_CHAINEND
- PLX_DMADPR_DESCPCI
- PLX_DMADPR_NEXT_MASK
- PLX_DMADPR_TCINTR
- PLX_DMADPR_XFERL2P
- PLX_DMAMODE_BTERMIEN
- PLX_DMAMODE_BURSTEN
- PLX_DMAMODE_CHAINEN
- PLX_DMAMODE_CLRCOUNT
- PLX_DMAMODE_DEMAND
- PLX_DMAMODE_DONEIEN
- PLX_DMAMODE_EOTEN
- PLX_DMAMODE_INTRPCI
- PLX_DMAMODE_IWS
- PLX_DMAMODE_IWS_MASK
- PLX_DMAMODE_LACONST
- PLX_DMAMODE_READYIEN
- PLX_DMAMODE_STOP
- PLX_DMAMODE_TO_IWS
- PLX_DMAMODE_WIDTH_16
- PLX_DMAMODE_WIDTH_32
- PLX_DMAMODE_WIDTH_32A
- PLX_DMAMODE_WIDTH_8
- PLX_DMAMODE_WIDTH_MASK
- PLX_DMAMODE_WINVALIDATE
- PLX_DMATHR_C0LPAE
- PLX_DMATHR_C0LPAE_MASK
- PLX_DMATHR_C0LPAF
- PLX_DMATHR_C0LPAF_MASK
- PLX_DMATHR_C0PLAE
- PLX_DMATHR_C0PLAE_MASK
- PLX_DMATHR_C0PLAF
- PLX_DMATHR_C0PLAF_MASK
- PLX_DMATHR_C1LPAE
- PLX_DMATHR_C1LPAE_MASK
- PLX_DMATHR_C1LPAF
- PLX_DMATHR_C1LPAF_MASK
- PLX_DMATHR_C1PLAE
- PLX_DMATHR_C1PLAE_MASK
- PLX_DMATHR_C1PLAF
- PLX_DMATHR_C1PLAF_MASK
- PLX_DMATHR_TO_C0LPAE
- PLX_DMATHR_TO_C0LPAF
- PLX_DMATHR_TO_C0PLAE
- PLX_DMATHR_TO_C0PLAF
- PLX_DMATHR_TO_C1LPAE
- PLX_DMATHR_TO_C1LPAF
- PLX_DMATHR_TO_C1PLAE
- PLX_DMATHR_TO_C1PLAF
- PLX_DMA_0_DESC
- PLX_DMA_0_LENGTH
- PLX_DMA_0_LOCAL
- PLX_DMA_0_MODE
- PLX_DMA_0_PCI
- PLX_DMA_1_DESC
- PLX_DMA_1_LENGTH
- PLX_DMA_1_LOCAL
- PLX_DMA_1_MODE
- PLX_DMA_1_PCI
- PLX_DMA_ARBITR_0
- PLX_DMA_ARBITR_1
- PLX_DMA_CH1_SUPPORTED_BIT
- PLX_DMA_CMD_STS
- PLX_DMCFGA_BUSNUM
- PLX_DMCFGA_BUSNUM_MASK
- PLX_DMCFGA_CONFIGEN
- PLX_DMCFGA_DEVNUM
- PLX_DMCFGA_DEVNUM_MASK
- PLX_DMCFGA_FUNCNUM
- PLX_DMCFGA_FUNCNUM_MASK
- PLX_DMCFGA_REGNUM
- PLX_DMCFGA_REGNUM_MASK
- PLX_DMCFGA_TO_BUSNUM
- PLX_DMCFGA_TO_DEVNUM
- PLX_DMCFGA_TO_FUNCNUM
- PLX_DMCFGA_TO_REGNUM
- PLX_DMCFGA_TYPE0
- PLX_DMCFGA_TYPE1
- PLX_DMCFGA_TYPE_MASK
- PLX_DMPBAM_IOACCEN
- PLX_DMPBAM_IOREMAPSEL
- PLX_DMPBAM_LLOCKIEN
- PLX_DMPBAM_MEMACCEN
- PLX_DMPBAM_PAFL
- PLX_DMPBAM_PAFL_MASK
- PLX_DMPBAM_REMAP_MASK
- PLX_DMPBAM_RMIRDY
- PLX_DMPBAM_RPSIZE_16
- PLX_DMPBAM_RPSIZE_4
- PLX_DMPBAM_RPSIZE_8
- PLX_DMPBAM_RPSIZE_CONT
- PLX_DMPBAM_RPSIZE_MASK
- PLX_DMPBAM_TO_PAFL
- PLX_DMPBAM_WDELAY_16
- PLX_DMPBAM_WDELAY_4
- PLX_DMPBAM_WDELAY_8
- PLX_DMPBAM_WDELAY_MASK
- PLX_DMPBAM_WDELAY_NONE
- PLX_DMPBAM_WIM
- PLX_DOORBELL_FROM_CARD
- PLX_DOORBELL_TO_CARD
- PLX_DSP_RES_N
- PLX_GPIO4
- PLX_GPIO4_BIT
- PLX_GPIO4_DIR
- PLX_GPIO4_DIR_BIT
- PLX_GPIO5
- PLX_GPIO5_BIT
- PLX_GPIO5_DIR
- PLX_GPIO5_DIR_BIT
- PLX_GPIO6
- PLX_GPIO6_BIT
- PLX_GPIO6_DIR
- PLX_GPIO6_DIR_BIT
- PLX_GPIO7
- PLX_GPIO7_BIT
- PLX_GPIO7_DIR
- PLX_GPIO7_DIR_BIT
- PLX_GPIO8
- PLX_GPIO8_BIT
- PLX_GPIO8_DIR
- PLX_GPIO8_DIR_BIT
- PLX_GPIOC
- PLX_GPIOC_INIT
- PLX_ICSR
- PLX_ICSR_ENA_CLR
- PLX_ICSR_LINTI1_CLR
- PLX_ICSR_LINTI1_ENA
- PLX_ICSR_PCIINT_ENA
- PLX_INTCSR
- PLX_INTCSR_ABNOTDM
- PLX_INTCSR_ABNOTDMA
- PLX_INTCSR_ABNOTDMA0
- PLX_INTCSR_ABNOTDMA1
- PLX_INTCSR_ABNOTRETRY
- PLX_INTCSR_BISTIA
- PLX_INTCSR_DMA0IA
- PLX_INTCSR_DMA0IEN
- PLX_INTCSR_DMA1IA
- PLX_INTCSR_DMA1IEN
- PLX_INTCSR_DMAIA
- PLX_INTCSR_DMAIEN
- PLX_INTCSR_GENSERR
- PLX_INTCSR_INTEN
- PLX_INTCSR_LDBIA
- PLX_INTCSR_LDBIEN
- PLX_INTCSR_LINTI1_ENABLE
- PLX_INTCSR_LINTI1_STATUS
- PLX_INTCSR_LINTI2_ENABLE
- PLX_INTCSR_LINTI2_STATUS
- PLX_INTCSR_LIOEN
- PLX_INTCSR_LSEABORTEN
- PLX_INTCSR_LSEPARITYEN
- PLX_INTCSR_MB0IA
- PLX_INTCSR_MB1IA
- PLX_INTCSR_MB2IA
- PLX_INTCSR_MB3IA
- PLX_INTCSR_MBIA
- PLX_INTCSR_MBIEN
- PLX_INTCSR_PABORTIA
- PLX_INTCSR_PABORTIEN
- PLX_INTCSR_PCIINT_ENABLE
- PLX_INTCSR_PCI_INTEN
- PLX_INTCSR_PDBIA
- PLX_INTCSR_PDBIEN
- PLX_INTCSR_PIEN
- PLX_INTCSR_PLIA
- PLX_INTCSR_PLIEN
- PLX_INTCSR_RAEN
- PLX_INTERRUPT_CS
- PLX_INT_CSR_REG
- PLX_LASBA_EN
- PLX_LASBA_IO_MASK
- PLX_LASBA_MEM_MASK
- PLX_LASRR_IO
- PLX_LASRR_IO_MASK
- PLX_LASRR_MEM_MASK
- PLX_LASRR_MLOC_ANY32
- PLX_LASRR_MLOC_ANY64
- PLX_LASRR_MLOC_LT1MB
- PLX_LASRR_MLOC_MASK
- PLX_LASRR_PREFETCH
- PLX_LBRD0_DSWMTRDY
- PLX_LBRD0_EELONGLOAD
- PLX_LBRD0_EROMBTERMIEN
- PLX_LBRD0_EROMBURSTEN
- PLX_LBRD0_EROMIWS
- PLX_LBRD0_EROMIWS_MASK
- PLX_LBRD0_EROMPREDIS
- PLX_LBRD0_EROMREADYIEN
- PLX_LBRD0_EROMWIDTH_16
- PLX_LBRD0_EROMWIDTH_32
- PLX_LBRD0_EROMWIDTH_32A
- PLX_LBRD0_EROMWIDTH_8
- PLX_LBRD0_EROMWIDTH_MASK
- PLX_LBRD0_MSBURSTEN
- PLX_LBRD0_MSPREDIS
- PLX_LBRD0_TO_EROMIWS
- PLX_LBRD0_TO_TRDELAY
- PLX_LBRD0_TRDELAY
- PLX_LBRD0_TRDELAY_MASK
- PLX_LBRD1_MSBURSTEN
- PLX_LBRD1_MSPREDIS
- PLX_LBRD_MSBTERMIEN
- PLX_LBRD_MSIWS
- PLX_LBRD_MSIWS_MASK
- PLX_LBRD_MSREADYIEN
- PLX_LBRD_MSWIDTH_16
- PLX_LBRD_MSWIDTH_32
- PLX_LBRD_MSWIDTH_32A
- PLX_LBRD_MSWIDTH_8
- PLX_LBRD_MSWIDTH_MASK
- PLX_LBRD_PFCOUNT
- PLX_LBRD_PFCOUNT_MASK
- PLX_LBRD_RPFCOUNTEN
- PLX_LBRD_TO_MSIWS
- PLX_LBRD_TO_PFCOUNT
- PLX_LEGACY
- PLX_LINT1_EN
- PLX_LINT1_POL
- PLX_LINT2_EN
- PLX_LINT2_POL
- PLX_MAILBOX_0
- PLX_MAILBOX_1
- PLX_MAILBOX_2
- PLX_MAILBOX_3
- PLX_MAILBOX_4
- PLX_MAILBOX_5
- PLX_MAILBOX_6
- PLX_MAILBOX_7
- PLX_MARBR_BREQEN
- PLX_MARBR_DSGUBM
- PLX_MARBR_DSLLOCKOEN
- PLX_MARBR_GLTBREQ
- PLX_MARBR_LT
- PLX_MARBR_LTEN
- PLX_MARBR_LT_MASK
- PLX_MARBR_PCIREQM
- PLX_MARBR_PCIRNFM
- PLX_MARBR_PCIRNWM
- PLX_MARBR_PCIRWFM
- PLX_MARBR_PCIV21M
- PLX_MARBR_PRIO_DMA0
- PLX_MARBR_PRIO_DMA1
- PLX_MARBR_PRIO_MASK
- PLX_MARBR_PRIO_ROT
- PLX_MARBR_PT
- PLX_MARBR_PTEN
- PLX_MARBR_PT_MASK
- PLX_MARBR_SUBSYSIDS
- PLX_MARBR_TO_LT
- PLX_MARBR_TO_PT
- PLX_MASTER_EN
- PLX_MIN_ATTR_LEN
- PLX_OFFSET
- PLX_PCIE
- PLX_PCIHIDR_9080
- PLX_PCIIPR
- PLX_PCI_CAN_CLOCK
- PLX_PCI_CDR
- PLX_PCI_INT_EN
- PLX_PCI_MAX_CARDS
- PLX_PCI_MAX_CHAN
- PLX_PCI_OCR
- PLX_PCI_RESET
- PLX_PREFETCH
- PLX_QSR_VALUE_AFTER_RESET
- PLX_REG_ALT_MBOX
- PLX_REG_ALT_MBOX0
- PLX_REG_ALT_MBOX1
- PLX_REG_BIGEND
- PLX_REG_CNTRL
- PLX_REG_DMAARB
- PLX_REG_DMACSR
- PLX_REG_DMACSR0
- PLX_REG_DMACSR1
- PLX_REG_DMADPR
- PLX_REG_DMADPR0
- PLX_REG_DMADPR1
- PLX_REG_DMALADR
- PLX_REG_DMALADR0
- PLX_REG_DMALADR1
- PLX_REG_DMAMODE
- PLX_REG_DMAMODE0
- PLX_REG_DMAMODE1
- PLX_REG_DMAPADR
- PLX_REG_DMAPADR0
- PLX_REG_DMAPADR1
- PLX_REG_DMASIZ
- PLX_REG_DMASIZ0
- PLX_REG_DMASIZ1
- PLX_REG_DMATHR
- PLX_REG_DMCFGA
- PLX_REG_DMLBAI
- PLX_REG_DMLBAM
- PLX_REG_DMPBAM
- PLX_REG_DMRR
- PLX_REG_EROMBA
- PLX_REG_EROMRR
- PLX_REG_INTCSR
- PLX_REG_L2PDBELL
- PLX_REG_LAS0BA
- PLX_REG_LAS0RR
- PLX_REG_LAS1BA
- PLX_REG_LAS1RR
- PLX_REG_LBRD0
- PLX_REG_LBRD1
- PLX_REG_MARBR
- PLX_REG_MBOX
- PLX_REG_MBOX0
- PLX_REG_MBOX1
- PLX_REG_MBOX2
- PLX_REG_MBOX3
- PLX_REG_MBOX4
- PLX_REG_MBOX5
- PLX_REG_MBOX6
- PLX_REG_MBOX7
- PLX_REG_P2LDBELL
- PLX_REG_PCIHIDR
- PLX_REG_PCIHREV
- PLX_REG_QSR
- PLX_RESET_TIME
- PLX_SLAVE_EN_N
- PLX_SUPERSPEED
- PLX_SYNC_O_EN
- PLX_TERM_ON
- PL_16K
- PL_16M
- PL_1M
- PL_256K
- PL_256M
- PL_4K
- PL_4M
- PL_64K
- PL_64M
- PL_BASE
- PL_BIST_SIGNAT
- PL_BREAK_REASON
- PL_B_HLS
- PL_B_ILS
- PL_B_NOT
- PL_B_PCS
- PL_B_QLS
- PL_B_TNE
- PL_B_TPC
- PL_CI_INS
- PL_CI_ISCR
- PL_CI_REMV
- PL_CI_RSCR
- PL_CLASS_S
- PL_CLK_DIV
- PL_CNTRL_A
- PL_CNTRL_B
- PL_CNTRL_C
- PL_CONFIG_CNTRL
- PL_C_CIPHER_ENABLE
- PL_C_CIPHER_LPBCK
- PL_C_FOTOFF_0
- PL_C_FOTOFF_30
- PL_C_FOTOFF_50
- PL_C_FOTOFF_ACT
- PL_C_FOTOFF_CTRL
- PL_C_FOTOFF_INA
- PL_C_FOTOFF_NEVER
- PL_C_FOTOFF_SRCE
- PL_C_FOTOFF_TIM
- PL_C_MIN
- PL_C_RXDATA_EN
- PL_C_SDNRZEN
- PL_C_SDOFF_ENABLE
- PL_C_SDON_084
- PL_C_SDON_132
- PL_C_SDON_252
- PL_C_SDON_512
- PL_C_SDON_ENABLE
- PL_C_SDON_TIMER
- PL_C_SOFF_076
- PL_C_SOFF_132
- PL_C_SOFF_252
- PL_C_SOFF_512
- PL_C_SOFF_TIMER
- PL_C_TSEL
- PL_DEL
- PL_EBUF_ERR
- PL_EB_LOC_LOOP
- PL_ENA_PAR_CHK
- PL_EP_CFG_4
- PL_EP_CTRL
- PL_EP_STATUS_1
- PL_EP_STATUS_3
- PL_EP_STATUS_4
- PL_F
- PL_FDEL
- PL_FGET
- PL_FOT_OFF
- PL_FSET
- PL_GET
- PL_INTR_EVENT
- PL_INTR_MASK
- PL_INT_CAUSE_A
- PL_INT_ENABLE_A
- PL_INT_MAP0_A
- PL_I_ANY
- PL_I_HALT
- PL_I_IDLE
- PL_I_MASTR
- PL_I_QUIET
- PL_LC_LENGTH
- PL_LE_CTR
- PL_LE_THRESHOLD
- PL_LINE_ST
- PL_LINK_ERR_CTR
- PL_LM_LOC_LOOP
- PL_LOGINFO_CODE_ABORT
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_FORM
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_NOT_IMP
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_NO_DEV
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_NO_OWNER
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_NUM_PHYS
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_PHY
- PL_LOGINFO_CODE_CONFIG_INVALID_PAGE_PT
- PL_LOGINFO_CODE_CONFIG_PL_NOT_INITIALIZED
- PL_LOGINFO_CODE_DISCOVERY_SATA_INIT_W_IOS
- PL_LOGINFO_CODE_DSCVRY_SATA_INIT_TIMEOUT
- PL_LOGINFO_CODE_ENCL_MGMT_ADDR_MODE_NOT_SUPPORTED
- PL_LOGINFO_CODE_ENCL_MGMT_BAD_SLOT_NUM
- PL_LOGINFO_CODE_ENCL_MGMT_GPIO_CONFIG_PAGE_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_GPIO_FRAME_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_GPIO_NOT_CONFIGURED
- PL_LOGINFO_CODE_ENCL_MGMT_NOT_SUPPORTED_ON_ENCL
- PL_LOGINFO_CODE_ENCL_MGMT_SES_FRAME_ALLOC_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_SES_IO_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_SES_RETRIES_EXHAUSTED
- PL_LOGINFO_CODE_ENCL_MGMT_SGPIO_NOT_PRESENT
- PL_LOGINFO_CODE_ENCL_MGMT_SMP_FRAME_ALLOC_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_SMP_FRAME_FAILURE
- PL_LOGINFO_CODE_ENCL_MGMT_SMP_READ_ERROR
- PL_LOGINFO_CODE_ENCL_MGMT_SMP_WRITE_ERROR
- PL_LOGINFO_CODE_FRAME_XFER_ERROR
- PL_LOGINFO_CODE_INVALID_SGL
- PL_LOGINFO_CODE_IO_CANCELLED_DUE_TO_R_ERR
- PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
- PL_LOGINFO_CODE_IO_EXECUTED
- PL_LOGINFO_CODE_IO_NOT_YET_EXECUTED
- PL_LOGINFO_CODE_OPEN_FAILURE
- PL_LOGINFO_CODE_OPEN_TXDMA_ABORT
- PL_LOGINFO_CODE_PERS_RESV_OUT_NOT_AFFIL_OWNER
- PL_LOGINFO_CODE_RESET
- PL_LOGINFO_CODE_RX_CTX_MESSAGE_VALID_ERROR
- PL_LOGINFO_CODE_RX_FM_CURRENT_FRAME_ERROR
- PL_LOGINFO_CODE_RX_FM_INVALID_MESSAGE
- PL_LOGINFO_CODE_SATA_ERR_IN_RCV_SET_DEV_BIT_FIS
- PL_LOGINFO_CODE_SATA_LINK_DOWN
- PL_LOGINFO_CODE_SATA_NCQ_FAIL_ALL_CMDS_AFTR_ERR
- PL_LOGINFO_CODE_SATA_NON_NCQ_RW_ERR_BIT_SET
- PL_LOGINFO_CODE_SATA_READ_LOG_RECEIVE_DATA_ERR
- PL_LOGINFO_CODE_TX_FM_CONNECTED_LOW
- PL_LOGINFO_CODE_WRONG_REL_OFF_OR_FRAME_LENGTH
- PL_LOGINFO_DA_SEP_BAD_STATUS_HDR_CHKSUM
- PL_LOGINFO_DA_SEP_CHKSUM_ERROR_AFTER_STOP
- PL_LOGINFO_DA_SEP_CHKSUM_ERROR_AFTER_STOP_GETDATA
- PL_LOGINFO_DA_SEP_DID_NOT_RECEIVE_ACK
- PL_LOGINFO_DA_SEP_ISTWI_INTR_IN_IDLE_STATE
- PL_LOGINFO_DA_SEP_NOT_PRESENT
- PL_LOGINFO_DA_SEP_RECEIVED_NACK_FROM_SLAVE
- PL_LOGINFO_DA_SEP_SINGLE_THREAD_ERROR
- PL_LOGINFO_DA_SEP_STOP_ON_DATA
- PL_LOGINFO_DA_SEP_STOP_ON_SENSE_DATA
- PL_LOGINFO_DA_SEP_UNSUPPORTED_COMMAND
- PL_LOGINFO_DA_SEP_UNSUPPORTED_COMMAND_2
- PL_LOGINFO_DA_SEP_UNSUPPORTED_COMMAND_3
- PL_LOGINFO_DA_SEP_UNSUPPORTED_SCSI_STATUS_1
- PL_LOGINFO_DA_SEP_UNSUPPORTED_SCSI_STATUS_2
- PL_LOGINFO_SUB_CODE_BREAK_ON_INCOMPLETE_BREAK_RCVD
- PL_LOGINFO_SUB_CODE_BREAK_ON_SATA_CONNECTION
- PL_LOGINFO_SUB_CODE_BREAK_ON_STUCK_LINK
- PL_LOGINFO_SUB_CODE_BREAK_ON_STUCK_LINK_AIP
- PL_LOGINFO_SUB_CODE_DISCOVERY_REMOTE_SEP_RESET
- PL_LOGINFO_SUB_CODE_DISCOVERY_SATA_INIT_W_IOS
- PL_LOGINFO_SUB_CODE_DSCVRY_SATA_INIT_TIMEOUT
- PL_LOGINFO_SUB_CODE_FRAME_XFER_ERROR
- PL_LOGINFO_SUB_CODE_INVALID_SGL
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ABANDON0
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ABANDON1
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ABANDON2
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ABANDON3
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_AWT_MAXED
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_BREAK
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_NO_DEST_TIMEOUT
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ORR_TIMEOUT
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_PATH_BLOCKED
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_RATE_NOT_SUPPORTED
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_SATA_NEG_RATE_2HI
- PL_LOGINFO_SUB_CODE_OPEN_FAILURE_ZONE_VIOLATION
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_AWT_MAXED
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_BAD_DEST
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_BREAK
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_DVTBLE_ACCSS_FAIL
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_NO_DEST_TIME_OUT
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_OPEN_TIMEOUT_EXP
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_PATHWAY_BLOCKED
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_PATH_BLOCKED
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_PROT_NOT_SUPP
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RATE_NOT_SUPP
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RESERVED_ABANDON0
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RESERVED_ABANDON1
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RESERVED_ABANDON2
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RESERVED_ABANDON3
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_CONTINUE0
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_CONTINUE1
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_INITIALIZE0
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_INITIALIZE1
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_STOP0
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RES_STOP1
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_RETRY
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_STP_RESOURCES_BSY
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_UNUSED_0B
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_UNUSED_0D
- PL_LOGINFO_SUB_CODE_OPEN_FAIL_WRONG_DESTINATION
- PL_LOGINFO_SUB_CODE_PORT_LAYER
- PL_LOGINFO_SUB_CODE_RX_CTX_MESSAGE_VALID_ERROR
- PL_LOGINFO_SUB_CODE_RX_FM_CURRENT_FRAME_ERROR
- PL_LOGINFO_SUB_CODE_RX_FM_INVALID_MESSAGE
- PL_LOGINFO_SUB_CODE_SATA_ERR_IN_RCV_SET_DEV_BIT_FIS
- PL_LOGINFO_SUB_CODE_SATA_LINK_DOWN
- PL_LOGINFO_SUB_CODE_SATA_NCQ_FAIL_ALL_CMDS_AFTR_ERR
- PL_LOGINFO_SUB_CODE_SATA_NON_NCQ_RW_ERR_BIT_SET
- PL_LOGINFO_SUB_CODE_SATA_READ_LOG_RECEIVE_DATA_ERR
- PL_LOGINFO_SUB_CODE_SECOND_OPEN
- PL_LOGINFO_SUB_CODE_TARGET_BUS_RESET
- PL_LOGINFO_SUB_CODE_TRANSPORT_LAYER
- PL_LOGINFO_SUB_CODE_TX_FM_CONNECTED_LOW
- PL_LOGINFO_SUB_CODE_WRONG_REL_OFF_OR_FRAME_LENGTH
- PL_LONG
- PL_LOOPBACK
- PL_LSDO
- PL_LSF
- PL_LSM_STATE
- PL_LS_MATCH
- PL_L_ALS
- PL_L_HLS
- PL_L_ILS16
- PL_L_ILS4
- PL_L_MLS
- PL_L_NLS
- PL_L_QLS
- PL_L_UND
- PL_MAINT
- PL_MAINT_LS
- PL_MATCH_LS
- PL_MINI_CTR
- PL_MINI_CTR_INT
- PL_MIN_IDLE_CTR
- PL_M_HALT
- PL_M_IDLE
- PL_M_MASTR
- PL_M_QUI0
- PL_M_QUI1
- PL_M_QUI2
- PL_M_QUI3
- PL_M_TPDR
- PL_NOISE_TIMER
- PL_NOLCT
- PL_NP_ERR
- PL_NS_MAX
- PL_OFFSET
- PL_PARITY_ERR
- PL_PC0
- PL_PC1
- PL_PC2
- PL_PC3
- PL_PC4
- PL_PC5
- PL_PC6
- PL_PC7
- PL_PC8
- PL_PC9
- PL_PCI_SCRUB
- PL_PCI_STATE
- PL_PCM_BREAK
- PL_PCM_CNTRL
- PL_PCM_CODE
- PL_PCM_ENABLED
- PL_PCM_NAF
- PL_PCM_SIGNAL
- PL_PCM_START
- PL_PCM_STATE
- PL_PCM_STOP
- PL_PCM_TRACE
- PL_PC_JOIN
- PL_PC_LOOP
- PL_PEER_E
- PL_PF_CTL_A
- PL_PF_INT_CAUSE_A
- PL_PF_INT_ENABLE_A
- PL_PHYINV
- PL_PL_INT_CAUSE_A
- PL_PREV_LINE_ST
- PL_P_HLS
- PL_P_ILS16
- PL_P_MLS
- PL_P_QLS
- PL_RCF
- PL_RCV_VECTOR
- PL_REQ_SCRUB
- PL_RESET_IN
- PL_RESET_OUT
- PL_REV_A
- PL_RF_DISABLE
- PL_RF_HALT1
- PL_RF_HALT2
- PL_RF_IDLE
- PL_RF_REPT
- PL_RF_STATE
- PL_RLBP
- PL_RST_A
- PL_RUN_BIST
- PL_S
- PL_SC_BYPASS
- PL_SC_REM_LOOP
- PL_SELF_TEST
- PL_SET
- PL_SIGNAL_DET
- PL_STATUS_A
- PL_STATUS_B
- PL_SYM_PR_CTR
- PL_S_EN
- PL_TB_MIN
- PL_TCF
- PL_TIDLE
- PL_TL_MIN
- PL_TNE
- PL_TNE_16BIT
- PL_TNE_EXPIRED
- PL_TNE_LOAD_V
- PL_TPC
- PL_TPC_16BIT
- PL_TPC_EXPIRED
- PL_TPC_LOAD_V
- PL_TPDR
- PL_TRACE_PROP
- PL_TX_C
- PL_TX_READY
- PL_TX_REQ
- PL_T_FOT_ASS
- PL_T_FOT_DEASS
- PL_T_OUT
- PL_T_SCRUB
- PL_UNKN_LINE_ST
- PL_V
- PL_VECTOR_LEN
- PL_VF_REVISION_A
- PL_VF_REV_A
- PL_VF_WHOAMI
- PL_VF_WHOAMI_A
- PL_VIOL_SYM_CTR
- PL_VSYM_CTR
- PL_VSYM_CTR_INT
- PL_WHOAMI_A
- PL_XMIT_VECTOR
- PM
- PM07_CTR_COUNT_CYCLES
- PM07_CTR_ENABLE
- PM07_CTR_INPUT_CONTROL
- PM07_CTR_INPUT_MUX
- PM07_CTR_POLARITY
- PM0_DATA
- PM0_ENABLE
- PM0_FN
- PM0_IN
- PM0_OUT
- PM1
- PM10
- PM121_CPU_INTERVAL
- PM121_NUM_CONFIGS
- PM121_SYS_GD
- PM121_SYS_GR
- PM121_SYS_HISTORY_SIZE
- PM121_SYS_INTERVAL
- PM16
- PM1_CNT
- PM1_DATA
- PM1_ENABLE
- PM1_FN
- PM1_IN
- PM1_OUT
- PM2301_CHARGER_H
- PM2FB_H
- PM2FB_MASTER_DEBUG
- PM2F_APERTURE_BYTESWAP
- PM2F_APERTURE_HALFWORDSWAP
- PM2F_APERTURE_STANDARD
- PM2F_BEING_RESET
- PM2F_BLANK_LOW
- PM2F_COLOR_KEY_TEST_OFF
- PM2F_CONFIG_FB_PACKED_DATA
- PM2F_CONFIG_FB_READ_DEST_ENABLE
- PM2F_CONFIG_FB_READ_SOURCE_ENABLE
- PM2F_CONFIG_FB_WRITE_ENABLE
- PM2F_CURSORMODE_CURSOR_ENABLE
- PM2F_CURSORMODE_TYPE_X
- PM2F_DATATYPE_COLOR
- PM2F_DATA_64_ENABLE
- PM2F_DELTA_ORDER_RGB
- PM2F_FB_READ_SOURCE_ENABLE
- PM2F_FB_WRITE_ENABLE
- PM2F_HSYNC_ACT_HIGH
- PM2F_HSYNC_ACT_LOW
- PM2F_HSYNC_FORCED_LOW
- PM2F_HSYNC_MASK
- PM2F_INCREASE_X
- PM2F_INCREASE_Y
- PM2F_LINE_DOUBLE
- PM2F_MEM_BANKS_1
- PM2F_MEM_BANKS_2
- PM2F_MEM_BANKS_3
- PM2F_MEM_BANKS_4
- PM2F_MEM_CONFIG_RAM_MASK
- PM2F_NO_ALPHA_BUFFER
- PM2F_PART_PROD_MASK
- PM2F_PLL_LOCKED
- PM2F_RD_COLOR_MODE_RGB
- PM2F_RD_GUI_ACTIVE
- PM2F_RD_PALETTE_WIDTH_8
- PM2F_RD_PIXELFORMAT_RGB232OFFSET
- PM2F_RD_PIXELFORMAT_RGB565
- PM2F_RD_PIXELFORMAT_RGB888
- PM2F_RD_PIXELFORMAT_RGBA2321
- PM2F_RD_PIXELFORMAT_RGBA4444
- PM2F_RD_PIXELFORMAT_RGBA5551
- PM2F_RD_PIXELFORMAT_RGBA8888
- PM2F_RD_PIXELFORMAT_SVGA
- PM2F_RD_TRUECOLOR
- PM2F_RENDER_AREASTIPPLE
- PM2F_RENDER_FASTFILL
- PM2F_RENDER_LINE
- PM2F_RENDER_POINT
- PM2F_RENDER_PRIMITIVE_MASK
- PM2F_RENDER_RECTANGLE
- PM2F_RENDER_SYNC_ON_BIT_MASK
- PM2F_RENDER_TEXTURE_ENABLE
- PM2F_RENDER_TRAPEZOID
- PM2F_SCREEN_SCISSOR_ENABLE
- PM2F_SYNCHRONIZATION
- PM2F_TEXTEL_SIZE_16
- PM2F_TEXTEL_SIZE_24
- PM2F_TEXTEL_SIZE_32
- PM2F_TEXTEL_SIZE_4
- PM2F_VGA_ENABLE
- PM2F_VGA_FIXED
- PM2F_VIDEO_ENABLE
- PM2F_VSYNC_ACT_HIGH
- PM2F_VSYNC_ACT_LOW
- PM2F_VSYNC_FORCED_LOW
- PM2F_VSYNC_MASK
- PM2I_RD_BLUE_KEY
- PM2I_RD_COLOR_KEY_CONTROL
- PM2I_RD_COLOR_MODE
- PM2I_RD_CURSOR_CONTROL
- PM2I_RD_GREEN_KEY
- PM2I_RD_MEMORY_CLOCK_1
- PM2I_RD_MEMORY_CLOCK_2
- PM2I_RD_MEMORY_CLOCK_3
- PM2I_RD_MEMORY_CLOCK_STATUS
- PM2I_RD_MISC_CONTROL
- PM2I_RD_MODE_CONTROL
- PM2I_RD_OVERLAY_KEY
- PM2I_RD_PIXEL_CLOCK_A1
- PM2I_RD_PIXEL_CLOCK_A2
- PM2I_RD_PIXEL_CLOCK_A3
- PM2I_RD_PIXEL_CLOCK_STATUS
- PM2I_RD_RED_KEY
- PM2P5
- PM2R_ALPHA_BLEND_MODE
- PM2R_APERTURE_ONE
- PM2R_APERTURE_TWO
- PM2R_AREA_STIPPLE_MODE
- PM2R_BIT_MASK_PATTERN
- PM2R_BOOT_ADDRESS
- PM2R_BYPASS_WRITE_MASK
- PM2R_CHIP_CONFIG
- PM2R_COLOR_DDA_MODE
- PM2R_CONFIG
- PM2R_CONSTANT_COLOR
- PM2R_COUNT
- PM2R_DELTA_MODE
- PM2R_DEPTH_MODE
- PM2R_DITHER_MODE
- PM2R_D_X_DOM
- PM2R_D_X_SUB
- PM2R_D_Y
- PM2R_FB_BLOCK_COLOR
- PM2R_FB_HARD_WRITE_MASK
- PM2R_FB_PIXEL_OFFSET
- PM2R_FB_READ_MODE
- PM2R_FB_READ_PIXEL
- PM2R_FB_SOFT_WRITE_MASK
- PM2R_FB_SOURCE_DELTA
- PM2R_FB_SOURCE_OFFSET
- PM2R_FB_WINDOW_BASE
- PM2R_FB_WRITE_MODE
- PM2R_FIFO_CONTROL
- PM2R_FIFO_DISCON
- PM2R_FILTER_MODE
- PM2R_FOG_MODE
- PM2R_FRAMEBUFFER_WRITE_MASK
- PM2R_HB_END
- PM2R_HG_END
- PM2R_HS_END
- PM2R_HS_START
- PM2R_H_TOTAL
- PM2R_IN_FIFO_SPACE
- PM2R_LB_READ_FORMAT
- PM2R_LB_READ_MODE
- PM2R_LB_SOURCE_OFFSET
- PM2R_LB_WINDOW_BASE
- PM2R_LB_WRITE_FORMAT
- PM2R_LINE_COUNT
- PM2R_LOGICAL_OP_MODE
- PM2R_MEM_CONFIG
- PM2R_MEM_CONTROL
- PM2R_OUT_FIFO
- PM2R_OUT_FIFO_WORDS
- PM2R_PACKED_DATA_LIMITS
- PM2R_RASTERIZER_MODE
- PM2R_RD_CURSOR_COLOR_ADDRESS
- PM2R_RD_CURSOR_COLOR_DATA
- PM2R_RD_CURSOR_DATA
- PM2R_RD_CURSOR_X_LSB
- PM2R_RD_CURSOR_X_MSB
- PM2R_RD_CURSOR_Y_LSB
- PM2R_RD_CURSOR_Y_MSB
- PM2R_RD_INDEXED_DATA
- PM2R_RD_PALETTE_DATA
- PM2R_RD_PALETTE_READ_ADDRESS
- PM2R_RD_PALETTE_WRITE_ADDRESS
- PM2R_RD_PIXEL_MASK
- PM2R_REBOOT
- PM2R_RECTANGLE_ORIGIN
- PM2R_RECTANGLE_SIZE
- PM2R_RENDER
- PM2R_RESET_STATUS
- PM2R_SCISSOR_MAX_XY
- PM2R_SCISSOR_MIN_XY
- PM2R_SCISSOR_MODE
- PM2R_SCREEN_BASE
- PM2R_SCREEN_SIZE
- PM2R_SCREEN_STRIDE
- PM2R_START_X_DOM
- PM2R_START_X_SUB
- PM2R_START_Y
- PM2R_STATISTICS_MODE
- PM2R_STENCIL_MODE
- PM2R_SYNC
- PM2R_TEXEL0
- PM2R_TEXEL_LUT_MODE
- PM2R_TEXTURE_ADDRESS_MODE
- PM2R_TEXTURE_COLOR_MODE
- PM2R_TEXTURE_DATA_FORMAT
- PM2R_TEXTURE_MAP_FORMAT
- PM2R_TEXTURE_READ_MODE
- PM2R_VB_END
- PM2R_VIDEO_CONTROL
- PM2R_VS_END
- PM2R_VS_START
- PM2R_V_TOTAL
- PM2R_WINDOW_ORIGIN
- PM2R_YUV_MODE
- PM2TAG
- PM2VI_RD_CLK0_FEEDBACK
- PM2VI_RD_CLK0_POSTSCALE
- PM2VI_RD_CLK0_PRESCALE
- PM2VI_RD_CLK1_FEEDBACK
- PM2VI_RD_CLK1_POSTSCALE
- PM2VI_RD_CLK1_PRESCALE
- PM2VI_RD_COLOR_FORMAT
- PM2VI_RD_CURSOR_MODE
- PM2VI_RD_CURSOR_PALETTE
- PM2VI_RD_CURSOR_PATTERN
- PM2VI_RD_CURSOR_X_HIGH
- PM2VI_RD_CURSOR_X_HOT
- PM2VI_RD_CURSOR_X_LOW
- PM2VI_RD_CURSOR_Y_HIGH
- PM2VI_RD_CURSOR_Y_HOT
- PM2VI_RD_CURSOR_Y_LOW
- PM2VI_RD_DAC_CONTROL
- PM2VI_RD_MCLK_CONTROL
- PM2VI_RD_MCLK_FEEDBACK
- PM2VI_RD_MCLK_POSTSCALE
- PM2VI_RD_MCLK_PRESCALE
- PM2VI_RD_MISC_CONTROL
- PM2VI_RD_OVERLAY_KEY
- PM2VI_RD_PIXEL_SIZE
- PM2VI_RD_SYNC_CONTROL
- PM2VR_RD_INDEXED_DATA
- PM2VR_RD_INDEX_HIGH
- PM2VR_RD_INDEX_LOW
- PM2XXX_ANTI_OVERSHOOT_DIS
- PM2XXX_ANTI_OVERSHOOT_EN
- PM2XXX_ANTI_OVERSHOOT_MASK
- PM2XXX_AUTOSUSPEND_DELAY
- PM2XXX_BATT_CTRL_REG1
- PM2XXX_BATT_CTRL_REG2
- PM2XXX_BATT_CTRL_REG3
- PM2XXX_BATT_CTRL_REG4
- PM2XXX_BATT_CTRL_REG5
- PM2XXX_BATT_CTRL_REG6
- PM2XXX_BATT_CTRL_REG7
- PM2XXX_BATT_CTRL_REG8
- PM2XXX_BATT_CTRL_REG9
- PM2XXX_BATT_DISC_REG
- PM2XXX_BATT_LOW_LEV_COMP_REG
- PM2XXX_BATT_LOW_LEV_VAL_REG
- PM2XXX_BATT_STAT_REG1
- PM2XXX_BATT_WD_KICK
- PM2XXX_BTEMP_HIGH_TH_45
- PM2XXX_BTEMP_HIGH_TH_50
- PM2XXX_BTEMP_HIGH_TH_55
- PM2XXX_BTEMP_HIGH_TH_60
- PM2XXX_BTEMP_HIGH_TH_65
- PM2XXX_BTEMP_LOW_TH_0
- PM2XXX_BTEMP_LOW_TH_10
- PM2XXX_BTEMP_LOW_TH_5
- PM2XXX_BTEMP_LOW_TH_N5
- PM2XXX_CHARCHING_INFO_DIS
- PM2XXX_CHARCHING_INFO_EN
- PM2XXX_CHARGER_DIS
- PM2XXX_CHARGER_ENA
- PM2XXX_CHG_STATUS_ERR
- PM2XXX_CHG_STATUS_FULL
- PM2XXX_CHG_STATUS_NOBAT
- PM2XXX_CHG_STATUS_OFF
- PM2XXX_CHG_STATUS_ON
- PM2XXX_CHG_STATUS_WAIT
- PM2XXX_CH_150MV_DROP_150MV
- PM2XXX_CH_150MV_DROP_300MV
- PM2XXX_CH_AUTO_RESUME_DIS
- PM2XXX_CH_AUTO_RESUME_EN
- PM2XXX_CH_CC_MODEDROP_DIS
- PM2XXX_CH_CC_MODEDROP_EN
- PM2XXX_CH_CC_REDUCED_CURRENT_100MA
- PM2XXX_CH_CC_REDUCED_CURRENT_200MA
- PM2XXX_CH_CC_REDUCED_CURRENT_400MA
- PM2XXX_CH_CC_REDUCED_CURRENT_IDENT
- PM2XXX_CH_EOC_CURRENT_100MA
- PM2XXX_CH_EOC_CURRENT_150MA
- PM2XXX_CH_EOC_CURRENT_300MA
- PM2XXX_CH_EOC_CURRENT_400MA
- PM2XXX_CH_EOC_CURRENT_MASK
- PM2XXX_CH_PRECH_CURRENT_100MA
- PM2XXX_CH_PRECH_CURRENT_25MA
- PM2XXX_CH_PRECH_CURRENT_50MA
- PM2XXX_CH_PRECH_CURRENT_75MA
- PM2XXX_CH_PRECH_CURRENT_MASK
- PM2XXX_CH_PRECH_VOL_2_5
- PM2XXX_CH_PRECH_VOL_2_7
- PM2XXX_CH_PRECH_VOL_2_9
- PM2XXX_CH_PRECH_VOL_3_1
- PM2XXX_CH_RESUME_DIS
- PM2XXX_CH_RESUME_EN
- PM2XXX_CH_VOLT_3_5
- PM2XXX_CH_VOLT_3_5225
- PM2XXX_CH_VOLT_3_6
- PM2XXX_CH_VOLT_3_7
- PM2XXX_CH_VOLT_4_0
- PM2XXX_CH_VOLT_4_175
- PM2XXX_CH_VOLT_4_2
- PM2XXX_CH_VOLT_4_275
- PM2XXX_CH_VOLT_4_3
- PM2XXX_CH_VOLT_MASK
- PM2XXX_CH_VRESUME_VOL_3_2
- PM2XXX_CH_VRESUME_VOL_3_4
- PM2XXX_CH_VRESUME_VOL_3_6
- PM2XXX_CH_VRESUME_VOL_3_8
- PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN
- PM2XXX_CH_WD_AUTO_TIMEOUT_NONE
- PM2XXX_CH_WD_CC_PHASE_10MIN
- PM2XXX_CH_WD_CC_PHASE_120MIN
- PM2XXX_CH_WD_CC_PHASE_240MIN
- PM2XXX_CH_WD_CC_PHASE_30MIN
- PM2XXX_CH_WD_CC_PHASE_360MIN
- PM2XXX_CH_WD_CC_PHASE_5MIN
- PM2XXX_CH_WD_CC_PHASE_60MIN
- PM2XXX_CH_WD_CC_PHASE_OFF
- PM2XXX_CH_WD_CV_PHASE_10MIN
- PM2XXX_CH_WD_CV_PHASE_120MIN
- PM2XXX_CH_WD_CV_PHASE_240MIN
- PM2XXX_CH_WD_CV_PHASE_30MIN
- PM2XXX_CH_WD_CV_PHASE_360MIN
- PM2XXX_CH_WD_CV_PHASE_5MIN
- PM2XXX_CH_WD_CV_PHASE_60MIN
- PM2XXX_CH_WD_CV_PHASE_OFF
- PM2XXX_CH_WD_PRECH_PHASE_10MIN
- PM2XXX_CH_WD_PRECH_PHASE_120MIN
- PM2XXX_CH_WD_PRECH_PHASE_1MIN
- PM2XXX_CH_WD_PRECH_PHASE_240MIN
- PM2XXX_CH_WD_PRECH_PHASE_30MIN
- PM2XXX_CH_WD_PRECH_PHASE_5MIN
- PM2XXX_CH_WD_PRECH_PHASE_60MIN
- PM2XXX_CH_WD_PRECH_PHASE_OFF
- PM2XXX_CONST_CURR
- PM2XXX_CONST_VOLT
- PM2XXX_DEV_VER_STAT
- PM2XXX_DIR_CH_CC_CURRENT_1000MA
- PM2XXX_DIR_CH_CC_CURRENT_1200MA
- PM2XXX_DIR_CH_CC_CURRENT_1400MA
- PM2XXX_DIR_CH_CC_CURRENT_1600MA
- PM2XXX_DIR_CH_CC_CURRENT_1800MA
- PM2XXX_DIR_CH_CC_CURRENT_2000MA
- PM2XXX_DIR_CH_CC_CURRENT_200MA
- PM2XXX_DIR_CH_CC_CURRENT_2200MA
- PM2XXX_DIR_CH_CC_CURRENT_2400MA
- PM2XXX_DIR_CH_CC_CURRENT_2600MA
- PM2XXX_DIR_CH_CC_CURRENT_2800MA
- PM2XXX_DIR_CH_CC_CURRENT_3000MA
- PM2XXX_DIR_CH_CC_CURRENT_400MA
- PM2XXX_DIR_CH_CC_CURRENT_600MA
- PM2XXX_DIR_CH_CC_CURRENT_800MA
- PM2XXX_DIR_CH_CC_CURRENT_MASK
- PM2XXX_I2C_PAD_CTRL_REG
- PM2XXX_INP_DROP_VPWR1
- PM2XXX_INP_DROP_VPWR2
- PM2XXX_INP_MODE_VPWR
- PM2XXX_INP_VOLT_VPWR1
- PM2XXX_INP_VOLT_VPWR2
- PM2XXX_INT1_ITVBATDISCONNECT
- PM2XXX_INT1_ITVBATLOWF
- PM2XXX_INT1_ITVBATLOWR
- PM2XXX_INT1_M_ITVBATDISCONNECT
- PM2XXX_INT1_M_ITVBATLOWF
- PM2XXX_INT1_M_ITVBATLOWR
- PM2XXX_INT1_S_ITVBATDISCONNECT
- PM2XXX_INT1_S_ITVBATLOWF
- PM2XXX_INT1_S_ITVBATLOWR
- PM2XXX_INT2_ITVPWR1PLUG
- PM2XXX_INT2_ITVPWR1UNPLUG
- PM2XXX_INT2_ITVPWR2PLUG
- PM2XXX_INT2_ITVPWR2UNPLUG
- PM2XXX_INT2_M_ITVPWR1PLUG
- PM2XXX_INT2_M_ITVPWR1UNPLUG
- PM2XXX_INT2_M_ITVPWR2PLUG
- PM2XXX_INT2_M_ITVPWR2UNPLUG
- PM2XXX_INT2_S_ITVPWR1PLUG
- PM2XXX_INT2_S_ITVPWR2PLUG
- PM2XXX_INT3_ITAUTOTIMEOUTWD
- PM2XXX_INT3_ITCHCCWD
- PM2XXX_INT3_ITCHCVWD
- PM2XXX_INT3_ITCHPRECHARGEWD
- PM2XXX_INT3_M_ITAUTOTIMEOUTWD
- PM2XXX_INT3_M_ITCHCCWD
- PM2XXX_INT3_M_ITCHCVWD
- PM2XXX_INT3_M_ITCHPRECHARGEWD
- PM2XXX_INT3_S_ITAUTOTIMEOUTWD
- PM2XXX_INT3_S_ITCHCCWD
- PM2XXX_INT3_S_ITCHCVWD
- PM2XXX_INT3_S_ITCHPRECHARGEWD
- PM2XXX_INT4_ITBATTEMPCOLD
- PM2XXX_INT4_ITBATTEMPHOT
- PM2XXX_INT4_ITBATTFULL
- PM2XXX_INT4_ITCHARGINGON
- PM2XXX_INT4_ITCVPHASE
- PM2XXX_INT4_ITVPWR1OVV
- PM2XXX_INT4_ITVPWR2OVV
- PM2XXX_INT4_ITVRESUME
- PM2XXX_INT4_M_ITBATTEMPCOLD
- PM2XXX_INT4_M_ITBATTEMPHOT
- PM2XXX_INT4_M_ITBATTFULL
- PM2XXX_INT4_M_ITCHARGINGON
- PM2XXX_INT4_M_ITCVPHASE
- PM2XXX_INT4_M_ITVPWR1OVV
- PM2XXX_INT4_M_ITVPWR2OVV
- PM2XXX_INT4_M_ITVRESUME
- PM2XXX_INT4_S_ITBATTEMPCOLD
- PM2XXX_INT4_S_ITBATTEMPHOT
- PM2XXX_INT4_S_ITBATTFULL
- PM2XXX_INT4_S_ITCHARGINGON
- PM2XXX_INT4_S_ITCVPHASE
- PM2XXX_INT4_S_ITVPWR1OVV
- PM2XXX_INT4_S_ITVPWR2OVV
- PM2XXX_INT4_S_ITVRESUME
- PM2XXX_INT5_ITTHERMALSHUTDOWNFALL
- PM2XXX_INT5_ITTHERMALSHUTDOWNRISE
- PM2XXX_INT5_ITTHERMALWARNINGFALL
- PM2XXX_INT5_ITTHERMALWARNINGRISE
- PM2XXX_INT5_ITVSYSTEMOVV
- PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL
- PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE
- PM2XXX_INT5_M_ITTHERMALWARNINGFALL
- PM2XXX_INT5_M_ITTHERMALWARNINGRISE
- PM2XXX_INT5_M_ITVSYSTEMOVV
- PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL
- PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE
- PM2XXX_INT5_S_ITTHERMALWARNINGFALL
- PM2XXX_INT5_S_ITTHERMALWARNINGRISE
- PM2XXX_INT5_S_ITVSYSTEMOVV
- PM2XXX_INT6_ITVPWR1DROP
- PM2XXX_INT6_ITVPWR1VALIDFALL
- PM2XXX_INT6_ITVPWR1VALIDRISE
- PM2XXX_INT6_ITVPWR2DROP
- PM2XXX_INT6_ITVPWR2VALIDFALL
- PM2XXX_INT6_ITVPWR2VALIDRISE
- PM2XXX_INT6_M_ITVPWR1DROP
- PM2XXX_INT6_M_ITVPWR1VALIDFALL
- PM2XXX_INT6_M_ITVPWR1VALIDRISE
- PM2XXX_INT6_M_ITVPWR2DROP
- PM2XXX_INT6_M_ITVPWR2VALIDFALL
- PM2XXX_INT6_M_ITVPWR2VALIDRISE
- PM2XXX_INT6_S_ITVPWR1DROP
- PM2XXX_INT6_S_ITVPWR1VALIDFALL
- PM2XXX_INT6_S_ITVPWR1VALIDRISE
- PM2XXX_INT6_S_ITVPWR2DROP
- PM2XXX_INT6_S_ITVPWR2VALIDFALL
- PM2XXX_INT6_S_ITVPWR2VALIDRISE
- PM2XXX_LED_CTRL_REG
- PM2XXX_LED_CURRENT_10MA
- PM2XXX_LED_CURRENT_1MA
- PM2XXX_LED_CURRENT_2_5MA
- PM2XXX_LED_CURRENT_5MA
- PM2XXX_LED_CURRENT_MASK
- PM2XXX_LED_SELECT_DIS
- PM2XXX_LED_SELECT_EN
- PM2XXX_LED_SELECT_MASK
- PM2XXX_MASK_REG_INT1
- PM2XXX_MASK_REG_INT2
- PM2XXX_MASK_REG_INT3
- PM2XXX_MASK_REG_INT4
- PM2XXX_MASK_REG_INT5
- PM2XXX_MASK_REG_INT6
- PM2XXX_NTC_BETA_COEFF_3477
- PM2XXX_NTC_BETA_COEFF_3964
- PM2XXX_NTC_CTRL_REG1
- PM2XXX_NTC_CTRL_REG2
- PM2XXX_NTC_RES_100K
- PM2XXX_NTC_RES_10K
- PM2XXX_NTC_RES_47K
- PM2XXX_NTC_RES_NO_NTC
- PM2XXX_NUM_INT_REG
- PM2XXX_REG_INT1
- PM2XXX_REG_INT2
- PM2XXX_REG_INT3
- PM2XXX_REG_INT4
- PM2XXX_REG_INT5
- PM2XXX_REG_INT6
- PM2XXX_SRCE_REG_INT1
- PM2XXX_SRCE_REG_INT2
- PM2XXX_SRCE_REG_INT3
- PM2XXX_SRCE_REG_INT4
- PM2XXX_SRCE_REG_INT5
- PM2XXX_SRCE_REG_INT6
- PM2XXX_SWCTRL_HW
- PM2XXX_SWCTRL_SW
- PM2XXX_SW_CTRL_REG
- PM2XXX_THERM_WARN_CTRL_REG
- PM2XXX_VBAT_LOW_LEVEL_2_3
- PM2XXX_VBAT_LOW_LEVEL_2_4
- PM2XXX_VBAT_LOW_LEVEL_2_5
- PM2XXX_VBAT_LOW_LEVEL_2_6
- PM2XXX_VBAT_LOW_LEVEL_2_7
- PM2XXX_VBAT_LOW_LEVEL_2_8
- PM2XXX_VBAT_LOW_LEVEL_2_9
- PM2XXX_VBAT_LOW_LEVEL_3_0
- PM2XXX_VBAT_LOW_LEVEL_3_1
- PM2XXX_VBAT_LOW_LEVEL_3_2
- PM2XXX_VBAT_LOW_LEVEL_3_3
- PM2XXX_VBAT_LOW_LEVEL_3_4
- PM2XXX_VBAT_LOW_LEVEL_3_5
- PM2XXX_VBAT_LOW_LEVEL_3_6
- PM2XXX_VBAT_LOW_LEVEL_3_7
- PM2XXX_VBAT_LOW_LEVEL_3_8
- PM2XXX_VBAT_LOW_LEVEL_3_9
- PM2XXX_VBAT_LOW_LEVEL_4_0
- PM2XXX_VBAT_LOW_LEVEL_4_1
- PM2XXX_VBAT_LOW_LEVEL_4_2
- PM2XXX_VBAT_LOW_MONITORING_DIS
- PM2XXX_VBAT_LOW_MONITORING_ENA
- PM2XXX_VPWR1_DROP_DIS
- PM2XXX_VPWR1_DROP_EN
- PM2XXX_VPWR1_HW_OPT_DIS
- PM2XXX_VPWR1_HW_OPT_EN
- PM2XXX_VPWR1_OVV_10
- PM2XXX_VPWR1_OVV_6_0
- PM2XXX_VPWR1_OVV_6_3
- PM2XXX_VPWR1_OVV_NONE
- PM2XXX_VPWR1_VALID_DIS
- PM2XXX_VPWR1_VALID_EN
- PM2XXX_VPWR2_DROP_DIS
- PM2XXX_VPWR2_DROP_EN
- PM2XXX_VPWR2_HW_OPT_DIS
- PM2XXX_VPWR2_HW_OPT_EN
- PM2XXX_VPWR2_OVV_10
- PM2XXX_VPWR2_OVV_6_0
- PM2XXX_VPWR2_OVV_6_3
- PM2XXX_VPWR2_OVV_NONE
- PM2XXX_VPWR2_VALID_DIS
- PM2XXX_VPWR2_VALID_EN
- PM2_DATA
- PM2_INDEX
- PM2_MAX_PIXCLOCK
- PM2_PIXMAP_SIZE
- PM2_REFERENCE_CLOCK
- PM2_REGS_SIZE
- PM2_TYPE_PERMEDIA2
- PM2_TYPE_PERMEDIA2V
- PM31_PULL_DISABLED
- PM31_PULL_ENABLED
- PM31_PULL_MASK
- PM3393_MAX_FRAME_SIZE
- PM3AALineWidth
- PM3AAPointsize
- PM3AGPControl
- PM3AlphaBlendAlphaMode
- PM3AlphaBlendAlphaModeAnd
- PM3AlphaBlendAlphaModeOr
- PM3AlphaBlendColorMode
- PM3AlphaBlendColorModeAnd
- PM3AlphaBlendColorModeOr
- PM3AlphaDestColor
- PM3AlphaSourceColor
- PM3AlphaTestMode
- PM3AlphaTestModeAnd
- PM3AlphaTestModeOr
- PM3AntialiasMode
- PM3AntialiasModeAnd
- PM3AntialiasModeOr
- PM3Aperture0
- PM3Aperture1
- PM3AreaStippleMode
- PM3BackgroundColor
- PM3BitMaskPattern
- PM3ByAperture1Mode
- PM3ByAperture2Mode
- PM3ByApertureMode_BYTESWAP_ABCD
- PM3ByApertureMode_BYTESWAP_BADC
- PM3ByApertureMode_BYTESWAP_CDAB
- PM3ByApertureMode_BYTESWAP_DCBA
- PM3ByApertureMode_DOUBLE_WRITE_16MB
- PM3ByApertureMode_DOUBLE_WRITE_1MB
- PM3ByApertureMode_DOUBLE_WRITE_2MB
- PM3ByApertureMode_DOUBLE_WRITE_32MB
- PM3ByApertureMode_DOUBLE_WRITE_4MB
- PM3ByApertureMode_DOUBLE_WRITE_8MB
- PM3ByApertureMode_DOUBLE_WRITE_OFF
- PM3ByApertureMode_EFFECTIVE_STRIDE_1024
- PM3ByApertureMode_EFFECTIVE_STRIDE_2048
- PM3ByApertureMode_EFFECTIVE_STRIDE_4096
- PM3ByApertureMode_EFFECTIVE_STRIDE_8192
- PM3ByApertureMode_FORMAT_RAW
- PM3ByApertureMode_FORMAT_UYVY
- PM3ByApertureMode_FORMAT_YUYV
- PM3ByApertureMode_FRAMEBUFFER
- PM3ByApertureMode_LOCALBUFFER
- PM3ByApertureMode_PATCH_ENABLE
- PM3ByApertureMode_PATCH_OFFSET_X
- PM3ByApertureMode_PATCH_OFFSET_Y
- PM3ByApertureMode_PIXELSIZE_16BIT
- PM3ByApertureMode_PIXELSIZE_32BIT
- PM3ByApertureMode_PIXELSIZE_8BIT
- PM3ByApertureMode_PIXELSIZE_MASK
- PM3ChipConfig
- PM3ChromaTestMode
- PM3ColorDDAMode
- PM3ColorDDAModeAnd
- PM3ColorDDAModeOr
- PM3CommandInterrupt
- PM3Config2D
- PM3Config2D_AlphaBlendEnable
- PM3Config2D_BackgroundROP
- PM3Config2D_BackgroundROPEnable
- PM3Config2D_Blocking
- PM3Config2D_DitherEnable
- PM3Config2D_ExternalSourceData
- PM3Config2D_FBDestReadEnable
- PM3Config2D_FBWriteEnable
- PM3Config2D_ForegroundROP
- PM3Config2D_ForegroundROPEnable
- PM3Config2D_LUTModeEnable
- PM3Config2D_MultiRXBlit
- PM3Config2D_OpaqueSpan
- PM3Config2D_UseConstantSource
- PM3Config2D_UserScissorEnable
- PM3ConstantColorDDA
- PM3ConstantColorDDA_A
- PM3ConstantColorDDA_B
- PM3ConstantColorDDA_G
- PM3ConstantColorDDA_R
- PM3ContextData
- PM3ContextDump
- PM3ContextRestore
- PM3Continue
- PM3ContinueNewDom
- PM3ContinueNewLine
- PM3ContinueNewSub
- PM3Count
- PM3DMAAddress
- PM3DMAControl
- PM3DMACount
- PM3DeltaControl
- PM3DeltaControlAnd
- PM3DeltaControlOr
- PM3DeltaMode
- PM3DeltaModeAnd
- PM3DeltaModeOr
- PM3DepthMode
- PM3DisplayData
- PM3DitherMode
- PM3DitherModeAnd
- PM3DitherModeOr
- PM3DownloadGlyphwidth
- PM3DownloadGlyphwidth_GlyphWidth
- PM3DownloadTarget
- PM3DownloadTarget_TagName
- PM3ErrorFlags
- PM3FBBlockColor
- PM3FBBlockColor0
- PM3FBBlockColor1
- PM3FBBlockColor2
- PM3FBBlockColor3
- PM3FBBlockColorBack
- PM3FBBlockColorBack0
- PM3FBBlockColorBack1
- PM3FBBlockColorBack2
- PM3FBBlockColorBack3
- PM3FBColor
- PM3FBData
- PM3FBDestReadBufferAddr0
- PM3FBDestReadBufferAddr1
- PM3FBDestReadBufferAddr2
- PM3FBDestReadBufferAddr3
- PM3FBDestReadBufferOffset0
- PM3FBDestReadBufferOffset1
- PM3FBDestReadBufferOffset2
- PM3FBDestReadBufferOffset3
- PM3FBDestReadBufferOffset_XOffset
- PM3FBDestReadBufferOffset_YOffset
- PM3FBDestReadBufferWidth0
- PM3FBDestReadBufferWidth1
- PM3FBDestReadBufferWidth2
- PM3FBDestReadBufferWidth3
- PM3FBDestReadBufferWidth_Width
- PM3FBDestReadEnables
- PM3FBDestReadEnablesAnd
- PM3FBDestReadEnablesOr
- PM3FBDestReadEnables_E
- PM3FBDestReadEnables_E0
- PM3FBDestReadEnables_E1
- PM3FBDestReadEnables_E2
- PM3FBDestReadEnables_E3
- PM3FBDestReadEnables_E4
- PM3FBDestReadEnables_E5
- PM3FBDestReadEnables_E6
- PM3FBDestReadEnables_E7
- PM3FBDestReadEnables_R
- PM3FBDestReadEnables_R0
- PM3FBDestReadEnables_R1
- PM3FBDestReadEnables_R2
- PM3FBDestReadEnables_R3
- PM3FBDestReadEnables_R4
- PM3FBDestReadEnables_R5
- PM3FBDestReadEnables_R6
- PM3FBDestReadEnables_R7
- PM3FBDestReadEnables_ReferenceAlpha
- PM3FBDestReadMode
- PM3FBDestReadModeAnd
- PM3FBDestReadModeOr
- PM3FBDestReadMode_AlphaFiltering
- PM3FBDestReadMode_Blocking
- PM3FBDestReadMode_Enable0
- PM3FBDestReadMode_Enable1
- PM3FBDestReadMode_Enable2
- PM3FBDestReadMode_Enable3
- PM3FBDestReadMode_Layout0
- PM3FBDestReadMode_Layout1
- PM3FBDestReadMode_Layout2
- PM3FBDestReadMode_Layout3
- PM3FBDestReadMode_Origin0
- PM3FBDestReadMode_Origin1
- PM3FBDestReadMode_Origin2
- PM3FBDestReadMode_Origin3
- PM3FBDestReadMode_ReadDisable
- PM3FBDestReadMode_ReadEnable
- PM3FBDestReadMode_StripeHeight
- PM3FBDestReadMode_StripePitch
- PM3FBDestReadMode_UseReadEnabled
- PM3FBHardwareWriteMask
- PM3FBIO_RESETCHIP
- PM3FBSoftwareWriteMask
- PM3FBSourceData
- PM3FBSourceReadBufferAddr
- PM3FBSourceReadBufferOffset
- PM3FBSourceReadBufferOffset_XOffset
- PM3FBSourceReadBufferOffset_YOffset
- PM3FBSourceReadBufferWidth
- PM3FBSourceReadBufferWidth_Width
- PM3FBSourceReadMode
- PM3FBSourceReadModeAnd
- PM3FBSourceReadModeOr
- PM3FBSourceReadMode_Blocking
- PM3FBSourceReadMode_ExternalSourceData
- PM3FBSourceReadMode_Layout
- PM3FBSourceReadMode_Origin
- PM3FBSourceReadMode_ReadDisable
- PM3FBSourceReadMode_ReadEnable
- PM3FBSourceReadMode_StripeHeight
- PM3FBSourceReadMode_StripePitch
- PM3FBSourceReadMode_UserTexelCoord
- PM3FBSourceReadMode_WrapX
- PM3FBSourceReadMode_WrapXEnable
- PM3FBSourceReadMode_WrapY
- PM3FBSourceReadMode_WrapYEnable
- PM3FBWriteBufferAddr0
- PM3FBWriteBufferAddr1
- PM3FBWriteBufferAddr2
- PM3FBWriteBufferAddr3
- PM3FBWriteBufferOffset0
- PM3FBWriteBufferOffset1
- PM3FBWriteBufferOffset2
- PM3FBWriteBufferOffset3
- PM3FBWriteBufferOffset_XOffset
- PM3FBWriteBufferOffset_YOffset
- PM3FBWriteBufferWidth0
- PM3FBWriteBufferWidth1
- PM3FBWriteBufferWidth2
- PM3FBWriteBufferWidth3
- PM3FBWriteBufferWidth_Width
- PM3FBWriteMode
- PM3FBWriteModeAnd
- PM3FBWriteModeOr
- PM3FBWriteMode_Enable0
- PM3FBWriteMode_Enable1
- PM3FBWriteMode_Enable2
- PM3FBWriteMode_Enable3
- PM3FBWriteMode_Layout0
- PM3FBWriteMode_Layout1
- PM3FBWriteMode_Layout2
- PM3FBWriteMode_Layout3
- PM3FBWriteMode_OpaqueSpan
- PM3FBWriteMode_Origin0
- PM3FBWriteMode_Origin1
- PM3FBWriteMode_Origin2
- PM3FBWriteMode_Origin3
- PM3FBWriteMode_Replicate
- PM3FBWriteMode_StripeHeight
- PM3FBWriteMode_StripePitch
- PM3FBWriteMode_WriteDisable
- PM3FBWriteMode_WriteEnable
- PM3FB_H
- PM3FB_MASTER_DEBUG
- PM3FIFODis
- PM3FifoControl
- PM3FillBackgroundColor
- PM3FillConfig2D0
- PM3FillConfig2D1
- PM3FillConfig2D_AlphaBlendEnable
- PM3FillConfig2D_BackgroundROP
- PM3FillConfig2D_BackgroundROPEnable
- PM3FillConfig2D_Blocking
- PM3FillConfig2D_DitherEnable
- PM3FillConfig2D_ExternalSourceData
- PM3FillConfig2D_FBDestReadEnable
- PM3FillConfig2D_FBWriteEnable
- PM3FillConfig2D_ForegroundROP
- PM3FillConfig2D_ForegroundROPEnable
- PM3FillConfig2D_LUTModeEnable
- PM3FillConfig2D_MultiRXBlit
- PM3FillConfig2D_OpaqueSpan
- PM3FillConfig2D_UseConstantSource
- PM3FillConfig2D_UserScissorEnable
- PM3FillFBDestReadBufferAddr
- PM3FillFBSourceReadBufferAddr
- PM3FillFBSourceReadBufferOffset
- PM3FillFBSourceReadBufferOffset_XOffset
- PM3FillFBSourceReadBufferOffset_YOffset
- PM3FillFBWriteBufferAddr
- PM3FillForegroundColor0
- PM3FillForegroundColor1
- PM3FillGlyphPosition
- PM3FillGlyphPosition_XOffset
- PM3FillGlyphPosition_YOffset
- PM3FillRectanglePosition
- PM3FillRectanglePosition_XOffset
- PM3FillRectanglePosition_YOffset
- PM3FilterMode
- PM3FilterModeSync
- PM3FogMode
- PM3ForegroundColor
- PM3GIDMode
- PM3GIDModeAnd
- PM3GIDModeOr
- PM3GPOutDMAAddress
- PM3GlyphData
- PM3GlyphPosition
- PM3GlyphPosition_XOffset
- PM3GlyphPosition_YOffset
- PM3HTotal
- PM3HbEnd
- PM3HgEnd
- PM3HostTextureAddress
- PM3HsEnd
- PM3HsStart
- PM3InFIFOSpace
- PM3IntEnable
- PM3IntFlags
- PM3InterruptLine
- PM3LBDestReadBufferAddr
- PM3LBDestReadBufferOffset
- PM3LBDestReadEnables
- PM3LBDestReadEnablesAnd
- PM3LBDestReadEnablesOr
- PM3LBDestReadMode
- PM3LBDestReadModeAnd
- PM3LBDestReadModeOr
- PM3LBDestReadMode_Disable
- PM3LBDestReadMode_Enable
- PM3LBDestReadMode_Layout
- PM3LBDestReadMode_Origin
- PM3LBDestReadMode_Packed16
- PM3LBDestReadMode_StripeHeight
- PM3LBDestReadMode_StripePitch
- PM3LBDestReadMode_UserReadEnables
- PM3LBDestReadMode_Width
- PM3LBReadFormat
- PM3LBReadFormat_DepthWidth
- PM3LBReadFormat_FCPPosition
- PM3LBReadFormat_FCPWidth
- PM3LBReadFormat_GIDPosition
- PM3LBReadFormat_GIDWidth
- PM3LBReadFormat_StencilPosition
- PM3LBReadFormat_StencilWidth
- PM3LBSourceReadBufferAddr
- PM3LBSourceReadBufferOffset
- PM3LBSourceReadMode
- PM3LBSourceReadModeAnd
- PM3LBSourceReadModeOr
- PM3LBSourceReadMode_Enable
- PM3LBSourceReadMode_Layout
- PM3LBSourceReadMode_Origin
- PM3LBSourceReadMode_Packed16
- PM3LBSourceReadMode_StripeHeight
- PM3LBSourceReadMode_StripePitch
- PM3LBSourceReadMode_Width
- PM3LBStencil
- PM3LBWriteBufferAddr
- PM3LBWriteBufferOffset
- PM3LBWriteFormat
- PM3LBWriteFormat_DepthWidth
- PM3LBWriteFormat_GIDPosition
- PM3LBWriteFormat_GIDWidth
- PM3LBWriteFormat_StencilPosition
- PM3LBWriteFormat_StencilWidth
- PM3LBWriteMode
- PM3LBWriteModeAnd
- PM3LBWriteModeOr
- PM3LBWriteMode_Layout
- PM3LBWriteMode_Origin
- PM3LBWriteMode_Packed16
- PM3LBWriteMode_StripeHeight
- PM3LBWriteMode_StripePitch
- PM3LBWriteMode_Width
- PM3LBWriteMode_WriteDisable
- PM3LBWriteMode_WriteEnable
- PM3LUT
- PM3LUTAddress
- PM3LUTData
- PM3LUTIndex
- PM3LUTMode
- PM3LUTModeAnd
- PM3LUTModeOr
- PM3LUTTransfer
- PM3LineStippleMode
- PM3LineStippleModeAnd
- PM3LineStippleModeOr
- PM3LoadLineStippleCounters
- PM3LocalMemCaps
- PM3LocalMemCaps_NoWriteMask
- PM3LocalMemControl
- PM3LocalMemPowerDown
- PM3LocalMemRefresh
- PM3LocalMemTimings
- PM3LogicalOpMode
- PM3LogicalOpModeAnd
- PM3LogicalOpModeOr
- PM3LogicalOpMode_Background_Disable
- PM3LogicalOpMode_Background_Enable
- PM3LogicalOpMode_Background_LogicOp
- PM3LogicalOpMode_Disable
- PM3LogicalOpMode_Enable
- PM3LogicalOpMode_LogicOp
- PM3LogicalOpMode_UseConstantSource_Disable
- PM3LogicalOpMode_UseConstantSource_Enable
- PM3LogicalOpMode_UseConstantWriteData_Disable
- PM3LogicalOpMode_UseConstantWriteData_Enable
- PM3LogicalTexturePage
- PM3MemBypassWriteMask
- PM3MemCounter
- PM3MemScratch
- PM3MiscControl
- PM3OutFIFOWords
- PM3OutputFifo
- PM3PCIAbortAddress
- PM3PCIAbortStatus
- PM3PCIFeedbackCount
- PM3PCIPLLStatus
- PM3Packed16Pixels
- PM3Packed4Pixels
- PM3Packed8Pixels
- PM3PixelSize
- PM3PixelSize_FRAMEBUFFER_16BIT
- PM3PixelSize_FRAMEBUFFER_32BIT
- PM3PixelSize_FRAMEBUFFER_8BIT
- PM3PixelSize_GLOBAL
- PM3PixelSize_GLOBAL_16BIT
- PM3PixelSize_GLOBAL_32BIT
- PM3PixelSize_GLOBAL_8BIT
- PM3PixelSize_INDIVIDUAL
- PM3PixelSize_LOCALBUFFER_16BIT
- PM3PixelSize_LOCALBUFFER_32BIT
- PM3PixelSize_LOCALBUFFER_8BIT
- PM3PixelSize_LOGICAL_OP_16BIT
- PM3PixelSize_LOGICAL_OP_32BIT
- PM3PixelSize_LOGICAL_OP_8BIT
- PM3PixelSize_LUT_16BIT
- PM3PixelSize_LUT_32BIT
- PM3PixelSize_LUT_8BIT
- PM3PixelSize_RASTERIZER_16BIT
- PM3PixelSize_RASTERIZER_32BIT
- PM3PixelSize_RASTERIZER_8BIT
- PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT
- PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT
- PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT
- PM3PixelSize_SETUP_16BIT
- PM3PixelSize_SETUP_32BIT
- PM3PixelSize_SETUP_8BIT
- PM3PixelSize_TEXTURE_16BIT
- PM3PixelSize_TEXTURE_32BIT
- PM3PixelSize_TEXTURE_8BIT
- PM3RD_CheckControl
- PM3RD_CheckControl_LUT_ENABLED
- PM3RD_CheckControl_PIXEL_ENABLED
- PM3RD_CheckLUTBlue
- PM3RD_CheckLUTGreen
- PM3RD_CheckLUTRed
- PM3RD_CheckPixelBlue
- PM3RD_CheckPixelGreen
- PM3RD_CheckPixelRed
- PM3RD_ColorFormat
- PM3RD_ColorFormat_2321_BACK_COLOR
- PM3RD_ColorFormat_2321_FRONT_COLOR
- PM3RD_ColorFormat_232_BACKOFF_COLOR
- PM3RD_ColorFormat_232_FRONTOFF_COLOR
- PM3RD_ColorFormat_332_BACK_COLOR
- PM3RD_ColorFormat_332_FRONT_COLOR
- PM3RD_ColorFormat_4444_COLOR
- PM3RD_ColorFormat_5551_BACK_COLOR
- PM3RD_ColorFormat_5551_FRONT_COLOR
- PM3RD_ColorFormat_565_BACK_COLOR
- PM3RD_ColorFormat_565_FRONT_COLOR
- PM3RD_ColorFormat_8888_COLOR
- PM3RD_ColorFormat_CI8_COLOR
- PM3RD_ColorFormat_COLOR_FORMAT_MASK
- PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW
- PM3RD_ColorFormat_COLOR_ORDER_RED_LOW
- PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE
- PM3RD_CursorControl
- PM3RD_CursorControl_DOUBLE_X_ENABLED
- PM3RD_CursorControl_DOUBLE_Y_ENABLED
- PM3RD_CursorControl_READBACK_POS_ENABLED
- PM3RD_CursorHotSpotX
- PM3RD_CursorHotSpotY
- PM3RD_CursorMode
- PM3RD_CursorMode_CURSOR_ENABLE
- PM3RD_CursorMode_FORMAT_32x32_2BPE_P0
- PM3RD_CursorMode_FORMAT_32x32_2BPE_P1
- PM3RD_CursorMode_FORMAT_32x32_2BPE_P2
- PM3RD_CursorMode_FORMAT_32x32_2BPE_P3
- PM3RD_CursorMode_FORMAT_32x32_4BPE_P01
- PM3RD_CursorMode_FORMAT_32x32_4BPE_P23
- PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123
- PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR
- PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR
- PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE
- PM3RD_CursorMode_TYPE_MS
- PM3RD_CursorMode_TYPE_X
- PM3RD_CursorPalette
- PM3RD_CursorPattern
- PM3RD_CursorXHigh
- PM3RD_CursorXLow
- PM3RD_CursorYHigh
- PM3RD_CursorYLow
- PM3RD_DACControl
- PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE
- PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE
- PM3RD_DACControl_BLANK_PEDESTAL_ENABLE
- PM3RD_DACControl_BLANK_RED_DAC_ENABLE
- PM3RD_DACControl_DAC_POWER_OFF
- PM3RD_DACControl_DAC_POWER_ON
- PM3RD_DACControl_SYNC_ON_GREEN_ENABLE
- PM3RD_DClk0FeedbackScale
- PM3RD_DClk0PostScale
- PM3RD_DClk0PreScale
- PM3RD_DClk1FeedbackScale
- PM3RD_DClk1PostScale
- PM3RD_DClk1PreScale
- PM3RD_DClk2FeedbackScale
- PM3RD_DClk2PostScale
- PM3RD_DClk2PreScale
- PM3RD_DClk3FeedbackScale
- PM3RD_DClk3PostScale
- PM3RD_DClk3PreScale
- PM3RD_DClkControl
- PM3RD_DClkControl_ENABLE
- PM3RD_DClkControl_LOCKED
- PM3RD_DClkControl_NOT_LOCKED
- PM3RD_DClkControl_SOURCE_EXT
- PM3RD_DClkControl_SOURCE_PLL
- PM3RD_DClkControl_SOURCE_VSA
- PM3RD_DClkControl_SOURCE_VSB
- PM3RD_DClkControl_STATE_HIGH
- PM3RD_DClkControl_STATE_LOW
- PM3RD_DClkControl_STATE_RUN
- PM3RD_DClkSetup1
- PM3RD_DClkSetup2
- PM3RD_IndexControl
- PM3RD_IndexControl_AUTOINCREMENT_ENABLE
- PM3RD_IndexHigh
- PM3RD_IndexLow
- PM3RD_IndexedData
- PM3RD_KClkControl
- PM3RD_KClkControl_ENABLE
- PM3RD_KClkControl_LOCKED
- PM3RD_KClkControl_NOT_LOCKED
- PM3RD_KClkControl_SOURCE_HALF_PCLK
- PM3RD_KClkControl_SOURCE_PCLK
- PM3RD_KClkControl_SOURCE_PLL
- PM3RD_KClkControl_STATE_HIGH
- PM3RD_KClkControl_STATE_LOW
- PM3RD_KClkControl_STATE_LOW_POWER
- PM3RD_KClkControl_STATE_RUN
- PM3RD_KClkFeedbackScale
- PM3RD_KClkPostScale
- PM3RD_KClkPreScale
- PM3RD_KClkSetup1
- PM3RD_KClkSetup2
- PM3RD_MClkControl
- PM3RD_MClkControl_ENABLE
- PM3RD_MClkControl_LOCKED
- PM3RD_MClkControl_NOT_LOCKED
- PM3RD_MClkControl_SOURCE_EXT
- PM3RD_MClkControl_SOURCE_HALF_EXT
- PM3RD_MClkControl_SOURCE_HALF_KCLK
- PM3RD_MClkControl_SOURCE_HALF_PCLK
- PM3RD_MClkControl_SOURCE_KCLK
- PM3RD_MClkControl_SOURCE_PCLK
- PM3RD_MClkControl_STATE_HIGH
- PM3RD_MClkControl_STATE_LOW
- PM3RD_MClkControl_STATE_LOW_POWER
- PM3RD_MClkControl_STATE_RUN
- PM3RD_MClkFeedbackScale
- PM3RD_MClkPostScale
- PM3RD_MClkPreScale
- PM3RD_MiscControl
- PM3RD_MiscControl_DIRECTCOLOR_ENABLE
- PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE
- PM3RD_MiscControl_LASTREAD_ADDR_ENABLE
- PM3RD_MiscControl_OVERLAY_ENABLE
- PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE
- PM3RD_MiscControl_PIXELDOUBLE_ENABLE
- PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE
- PM3RD_MiscControl_VSB_OUTPUT_ENABLE
- PM3RD_OverlayKey
- PM3RD_PaletteData
- PM3RD_PaletteReadAddress
- PM3RD_PaletteWriteAddress
- PM3RD_Pan
- PM3RD_Pan_ENABLE
- PM3RD_Pan_GATE_ENABLE
- PM3RD_PixelMask
- PM3RD_PixelSize
- PM3RD_PixelSize_16_BIT_PIXELS
- PM3RD_PixelSize_24_BIT_PIXELS
- PM3RD_PixelSize_32_BIT_PIXELS
- PM3RD_PixelSize_8_BIT_PIXELS
- PM3RD_SClkControl
- PM3RD_SClkControl_ENABLE
- PM3RD_SClkControl_LOCKED
- PM3RD_SClkControl_NOT_LOCKED
- PM3RD_SClkControl_SOURCE_EXT
- PM3RD_SClkControl_SOURCE_HALF_EXT
- PM3RD_SClkControl_SOURCE_HALF_KCLK
- PM3RD_SClkControl_SOURCE_HALF_PCLK
- PM3RD_SClkControl_SOURCE_KCLK
- PM3RD_SClkControl_SOURCE_PCLK
- PM3RD_SClkControl_STATE_HIGH
- PM3RD_SClkControl_STATE_LOW
- PM3RD_SClkControl_STATE_LOW_POWER
- PM3RD_SClkControl_STATE_RUN
- PM3RD_SClkFeedbackScale
- PM3RD_SClkPostScale
- PM3RD_SClkPreScale
- PM3RD_Scratch
- PM3RD_Sense
- PM3RD_SyncControl
- PM3RD_SyncControl_HSYNC_ACTIVE_HIGH
- PM3RD_SyncControl_HSYNC_ACTIVE_LOW
- PM3RD_SyncControl_HSYNC_FORCE_ACTIVE
- PM3RD_SyncControl_HSYNC_FORCE_INACTIVE
- PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH
- PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC
- PM3RD_SyncControl_HSYNC_TRI_STATE
- PM3RD_SyncControl_VSYNC_ACTIVE_HIGH
- PM3RD_SyncControl_VSYNC_ACTIVE_LOW
- PM3RD_SyncControl_VSYNC_FORCE_ACTIVE
- PM3RD_SyncControl_VSYNC_FORCE_INACTIVE
- PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH
- PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC
- PM3RD_SyncControl_VSYNC_TRI_STATE
- PM3RD_VideoOverlayBlend
- PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT
- PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT
- PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT
- PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT
- PM3RD_VideoOverlayControl
- PM3RD_VideoOverlayControl_BLENDSRC_MAIN
- PM3RD_VideoOverlayControl_BLENDSRC_REGISTER
- PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED
- PM3RD_VideoOverlayControl_ENABLE
- PM3RD_VideoOverlayControl_KEY_ALPHA
- PM3RD_VideoOverlayControl_KEY_COLOR
- PM3RD_VideoOverlayControl_MODE_ALWAYS
- PM3RD_VideoOverlayControl_MODE_BLEND
- PM3RD_VideoOverlayControl_MODE_MAINKEY
- PM3RD_VideoOverlayControl_MODE_MASK
- PM3RD_VideoOverlayControl_MODE_OVERLAYKEY
- PM3RD_VideoOverlayKeyB
- PM3RD_VideoOverlayKeyG
- PM3RD_VideoOverlayKeyR
- PM3RD_VideoOverlayXEndHigh
- PM3RD_VideoOverlayXEndLow
- PM3RD_VideoOverlayXStartHigh
- PM3RD_VideoOverlayXStartLow
- PM3RD_VideoOverlayYEndHigh
- PM3RD_VideoOverlayYEndLow
- PM3RD_VideoOverlayYStartHigh
- PM3RD_VideoOverlayYStartLow
- PM3RLCount
- PM3RLCount_Count
- PM3RLData
- PM3RLEMask
- PM3RStart
- PM3RasterizerMode
- PM3RasterizerModeAnd
- PM3RasterizerModeOr
- PM3RectangleHeight
- PM3RectanglePosition
- PM3RectanglePosition_XOffset
- PM3RectanglePosition_YOffset
- PM3RemoteMemControl
- PM3Render
- PM3Render2D
- PM3Render2DGlyph
- PM3Render2DGlyph_Height
- PM3Render2DGlyph_Width
- PM3Render2DGlyph_XOffset
- PM3Render2DGlyph_YOffset
- PM3Render2D_AreaStippleEnable
- PM3Render2D_FBSourceReadEnable
- PM3Render2D_Height
- PM3Render2D_Operation_Normal
- PM3Render2D_Operation_PatchOrderRendering
- PM3Render2D_Operation_SyncOnBitMask
- PM3Render2D_Operation_SyncOnHostData
- PM3Render2D_SpanOperation
- PM3Render2D_TextureEnable
- PM3Render2D_Width
- PM3Render2D_XPositive
- PM3Render2D_YPositive
- PM3RenderPatchOffset
- PM3RenderPatchOffset_XOffset
- PM3RenderPatchOffset_YOffset
- PM3Render_Antialias_Disable
- PM3Render_Antialias_Enable
- PM3Render_Antialias_SubPixelRes_4x4
- PM3Render_Antialias_SubPixelRes_8x8
- PM3Render_AreaStipple_Disable
- PM3Render_AreaStipple_Enable
- PM3Render_Coverage_Disable
- PM3Render_Coverage_Enable
- PM3Render_FBSourceRead_Disable
- PM3Render_FBSourceRead_Enable
- PM3Render_FastFill_Disable
- PM3Render_FastFill_Enable
- PM3Render_Fog_Disable
- PM3Render_Fog_Enable
- PM3Render_LineStipple_Disable
- PM3Render_LineStipple_Enable
- PM3Render_Primitive_Line
- PM3Render_Primitive_Point
- PM3Render_Primitive_Trapezoid
- PM3Render_ResetLine_Disable
- PM3Render_ResetLine_Enable
- PM3Render_SpanOperation_Disable
- PM3Render_SpanOperation_Enable
- PM3Render_SubPixelCorrection_Disable
- PM3Render_SubPixelCorrection_Enable
- PM3Render_SyncOnBitMask_Enable
- PM3Render_SyncOnHostData_Disable
- PM3Render_SyncOnHostData_Enable
- PM3Render_SyncOnbitMask_Disable
- PM3Render_Texture_Disable
- PM3Render_Texture_Enable
- PM3Render_UsePointTable_Disable
- PM3Render_UsePointTable_Enable
- PM3RepeatLine
- PM3ResetPickResult
- PM3ResetStatus
- PM3RouterMode
- PM3S1Start
- PM3SStart
- PM3ScissorMaxXY
- PM3ScissorMinXY
- PM3ScissorMode
- PM3ScissorModeAnd
- PM3ScissorModeOr
- PM3ScreenBase
- PM3ScreenBaseRight
- PM3ScreenSize
- PM3ScreenStride
- PM3Security
- PM3SetLogicalTexturePage
- PM3SizeOfFramebuffer
- PM3SpanColorMask
- PM3StartXDom
- PM3StartXSub
- PM3StartY
- PM3StatisticMode
- PM3StencilData
- PM3StencilMode
- PM3Sync
- PM3Sync_Tag
- PM3TestRegister
- PM3TexDMAAddress
- PM3TexFIFOSpace
- PM3TextureApplicationMode
- PM3TextureApplicationModeAnd
- PM3TextureApplicationModeOr
- PM3TextureBaseAddr
- PM3TextureCacheControl
- PM3TextureChromaLower0
- PM3TextureChromaLower1
- PM3TextureChromaUpper0
- PM3TextureChromaUpper1
- PM3TextureCompositeAlphaMode0
- PM3TextureCompositeAlphaMode0And
- PM3TextureCompositeAlphaMode0Or
- PM3TextureCompositeAlphaMode1
- PM3TextureCompositeAlphaMode1And
- PM3TextureCompositeAlphaMode1Or
- PM3TextureCompositeColorMode0
- PM3TextureCompositeColorMode0And
- PM3TextureCompositeColorMode0Or
- PM3TextureCompositeColorMode1
- PM3TextureCompositeColorMode1And
- PM3TextureCompositeColorMode1Or
- PM3TextureCompositeFactor0
- PM3TextureCompositeFactor1
- PM3TextureCompositeMode
- PM3TextureCoordMode
- PM3TextureCoordModeAnd
- PM3TextureCoordModeOr
- PM3TextureData
- PM3TextureDownloadControl
- PM3TextureDownloadOffset
- PM3TextureEnvColor
- PM3TextureFilterMode
- PM3TextureFilterModeAnd
- PM3TextureFilterModeOr
- PM3TextureIndexMode0
- PM3TextureIndexMode0And
- PM3TextureIndexMode0Or
- PM3TextureIndexMode1
- PM3TextureIndexMode1And
- PM3TextureIndexMode1Or
- PM3TextureMapSize
- PM3TextureMapWidth0
- PM3TextureMapWidth1
- PM3TextureMapWidth_BorderLayout
- PM3TextureMapWidth_HostTexture
- PM3TextureMapWidth_Layout_Linear
- PM3TextureMapWidth_Layout_Patch2
- PM3TextureMapWidth_Layout_Patch32_2
- PM3TextureMapWidth_Layout_Patch64
- PM3TextureMapWidth_Width
- PM3TextureOperation
- PM3TextureReadMode
- PM3TextureReadMode0
- PM3TextureReadMode0And
- PM3TextureReadMode0Or
- PM3TextureReadMode1
- PM3TextureReadMode1And
- PM3TextureReadMode1Or
- PM3UVMode
- PM3VClkCtl
- PM3VSConfiguration
- PM3VTotal
- PM3VbEnd
- PM3VerticalLineCount
- PM3VideoControl
- PM3VideoControl_BLANK_ACTIVE_HIGH
- PM3VideoControl_BLANK_ACTIVE_LOW
- PM3VideoControl_BUFFER_SWAP_FREE_RUNNING
- PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE
- PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK
- PM3VideoControl_BYTE_DOUBLE_OFF
- PM3VideoControl_BYTE_DOUBLE_ON
- PM3VideoControl_DISPLAY_ENABLE
- PM3VideoControl_ENABLE
- PM3VideoControl_HSYNC_ACTIVE_HIGH
- PM3VideoControl_HSYNC_ACTIVE_LOW
- PM3VideoControl_HSYNC_FORCE_HIGH
- PM3VideoControl_HSYNC_FORCE_LOW
- PM3VideoControl_HSYNC_MASK
- PM3VideoControl_LINE_DOUBLE_OFF
- PM3VideoControl_LINE_DOUBLE_ON
- PM3VideoControl_PATCH_ENABLE
- PM3VideoControl_PATCH_OFFSET_X
- PM3VideoControl_PATCH_OFFSET_Y
- PM3VideoControl_PIXELSIZE_16BIT
- PM3VideoControl_PIXELSIZE_32BIT
- PM3VideoControl_PIXELSIZE_8BIT
- PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH
- PM3VideoControl_RIGHT_EYE_ACTIVE_LOW
- PM3VideoControl_STEREO_ENABLE
- PM3VideoControl_SYNC_MODE_INDEPENDENT
- PM3VideoControl_SYNC_MODE_SYNCTO_VSA
- PM3VideoControl_SYNC_MODE_SYNCTO_VSB
- PM3VideoControl_VIDEO_EXT_HIGH
- PM3VideoControl_VIDEO_EXT_LOW
- PM3VideoControl_VSYNC_ACTIVE_HIGH
- PM3VideoControl_VSYNC_ACTIVE_LOW
- PM3VideoControl_VSYNC_FORCE_HIGH
- PM3VideoControl_VSYNC_FORCE_LOW
- PM3VideoControl_VSYNC_MASK
- PM3VideoOverlayBase0
- PM3VideoOverlayBase1
- PM3VideoOverlayBase2
- PM3VideoOverlayFieldOffset
- PM3VideoOverlayFifoControl
- PM3VideoOverlayHeight
- PM3VideoOverlayHeight_HEIGHT
- PM3VideoOverlayIndex
- PM3VideoOverlayMode
- PM3VideoOverlayMode_BUFFERSYNC_MANUAL
- PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA
- PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB
- PM3VideoOverlayMode_COLORFORMAT_BGR332
- PM3VideoOverlayMode_COLORFORMAT_BGR4444
- PM3VideoOverlayMode_COLORFORMAT_BGR5551
- PM3VideoOverlayMode_COLORFORMAT_BGR565
- PM3VideoOverlayMode_COLORFORMAT_BGR8888
- PM3VideoOverlayMode_COLORFORMAT_CI8
- PM3VideoOverlayMode_COLORFORMAT_RGB332
- PM3VideoOverlayMode_COLORFORMAT_RGB4444
- PM3VideoOverlayMode_COLORFORMAT_RGB5551
- PM3VideoOverlayMode_COLORFORMAT_RGB565
- PM3VideoOverlayMode_COLORFORMAT_RGB8888
- PM3VideoOverlayMode_COLORFORMAT_VUY422
- PM3VideoOverlayMode_COLORFORMAT_VUY444
- PM3VideoOverlayMode_COLORFORMAT_YUV422
- PM3VideoOverlayMode_COLORFORMAT_YUV444
- PM3VideoOverlayMode_COLORORDER_BGR
- PM3VideoOverlayMode_COLORORDER_RGB
- PM3VideoOverlayMode_DEINTERLACE_BOB
- PM3VideoOverlayMode_DEINTERLACE_OFF
- PM3VideoOverlayMode_ENABLE
- PM3VideoOverlayMode_FIELDPOLARITY_INVERT
- PM3VideoOverlayMode_FIELDPOLARITY_NORMAL
- PM3VideoOverlayMode_FILTER_FULL
- PM3VideoOverlayMode_FILTER_MASK
- PM3VideoOverlayMode_FILTER_OFF
- PM3VideoOverlayMode_FILTER_PARTIAL
- PM3VideoOverlayMode_FLIP_VIDEO
- PM3VideoOverlayMode_FLIP_VIDEOSTREAMA
- PM3VideoOverlayMode_FLIP_VIDEOSTREAMB
- PM3VideoOverlayMode_LINEARCOLOREXT_OFF
- PM3VideoOverlayMode_LINEARCOLOREXT_ON
- PM3VideoOverlayMode_MIRRORX_OFF
- PM3VideoOverlayMode_MIRRORX_ON
- PM3VideoOverlayMode_MIRRORY_OFF
- PM3VideoOverlayMode_MIRRORY_ON
- PM3VideoOverlayMode_MIRROR_MASK
- PM3VideoOverlayMode_PATCHMODE_OFF
- PM3VideoOverlayMode_PATCHMODE_ON
- PM3VideoOverlayMode_PIXELSIZE_16BIT
- PM3VideoOverlayMode_PIXELSIZE_32BIT
- PM3VideoOverlayMode_PIXELSIZE_8BIT
- PM3VideoOverlayOrigin
- PM3VideoOverlayOrigin_XORIGIN
- PM3VideoOverlayOrigin_YORIGIN
- PM3VideoOverlayShrinkXDelta
- PM3VideoOverlayShrinkXDelta_DELTA
- PM3VideoOverlayShrinkXDelta_NONE
- PM3VideoOverlayStatus
- PM3VideoOverlayStride
- PM3VideoOverlayStride_STRIDE
- PM3VideoOverlayUpdate
- PM3VideoOverlayUpdate_ENABLE
- PM3VideoOverlayWidth
- PM3VideoOverlayWidth_WIDTH
- PM3VideoOverlayYDelta
- PM3VideoOverlayYDelta_DELTA
- PM3VideoOverlayYDelta_NONE
- PM3VideoOverlayZoomXDelta
- PM3VideoOverlayZoomXDelta_DELTA
- PM3VideoOverlayZoomXDelta_NONE
- PM3VsEnd
- PM3VsStart
- PM3WaitForCompletion
- PM3Window
- PM3WindowAnd
- PM3WindowOr
- PM3WindowOrigin
- PM3Window_DepthFCP
- PM3Window_ForceLBUpdate
- PM3Window_FrameCount
- PM3Window_LBUpdateSource
- PM3Window_OverrideWriteFiltering
- PM3Window_StencilFCP
- PM3XBias
- PM3YBias
- PM3YLimits
- PM3YUVMode
- PM3ZFogBias
- PM3ZStart
- PM3ZStartL
- PM3ZStartU
- PM3_FIFO_SIZE
- PM3_MAX_PIXCLOCK
- PM3_PIXMAP_SIZE
- PM3_READ_REG
- PM3_REF_CLOCK
- PM3_REGS_SIZE
- PM3_WAIT
- PM3_WRITE_DAC_REG
- PM3_WRITE_REG
- PM3aveLineStippleCounters
- PM3dXDom
- PM3dXSub
- PM3dY
- PM4
- PM49FL002
- PM49FL004
- PM49FL008
- PM4_BUFFER_ADDR
- PM4_BUFFER_CNTL
- PM4_BUFFER_CNTL_NONPM4
- PM4_BUFFER_DATAH
- PM4_BUFFER_DATAL
- PM4_BUFFER_DL_RPTR
- PM4_BUFFER_DL_RPTR_ADDR
- PM4_BUFFER_DL_WPTR
- PM4_BUFFER_OFFSET
- PM4_BUFFER_WM_CNTL
- PM4_CMDFIFO_ADDR
- PM4_CMDFIFO_DATAH
- PM4_CMDFIFO_DATAL
- PM4_COUNT_ZERO
- PM4_FIFO_DATA_EVEN
- PM4_FIFO_DATA_ODD
- PM4_FPU_CNTL
- PM4_FPU_DMAJOR01
- PM4_FPU_DMAJOR02
- PM4_FPU_DMAJOR12
- PM4_FPU_FPA
- PM4_FPU_FPB
- PM4_FPU_FPG
- PM4_FPU_FPR
- PM4_FPU_FPTWICEAREA
- PM4_FPU_FPX0
- PM4_FPU_FPX1
- PM4_FPU_FPX2
- PM4_FPU_FPY0
- PM4_FPU_FPY1
- PM4_FPU_FPY2
- PM4_FPU_FPY3
- PM4_FPU_FPY4
- PM4_FPU_FPY5
- PM4_FPU_FPY6
- PM4_FPU_INTARGB
- PM4_FPU_INTXY0
- PM4_FPU_INTXY1
- PM4_FPU_INTXY2
- PM4_FPU_STAT
- PM4_IW_INDOFF
- PM4_IW_INDSIZE
- PM4_MEC_RELEASE_MEM_DEFINED
- PM4_MES_HEADER_DEFINED
- PM4_MES_MAP_PROCESS_DEFINED
- PM4_MES_MAP_PROCESS_DEFINED_KV_SCRATCH
- PM4_MES_MAP_PROCESS_VM
- PM4_MES_MAP_PROCESS_VM_DEFINED
- PM4_MES_MAP_QUEUES_VI_DEFINED
- PM4_MES_QUERY_STATUS_DEFINED
- PM4_MES_RUN_LIST_DEFINED
- PM4_MES_SET_RESOURCES_DEFINED
- PM4_MES_TYPE_3_HEADER
- PM4_MES_UNMAP_QUEUES_DEFINED
- PM4_MICROCODE_ADDR
- PM4_MICROCODE_DATAH
- PM4_MICROCODE_DATAL
- PM4_MICROCODE_RADDR
- PM4_MICRO_CNTL
- PM4_PARITY
- PM4_STAT
- PM4_TEST_CNTL
- PM4_TYPE_0
- PM4_TYPE_2
- PM4_TYPE_3
- PM4_VC_CNTL
- PM4_VC_FORMAT
- PM4_VC_FPU_SETUP
- PM4_VC_I01
- PM4_VC_VLOFF
- PM4_VC_VLSIZE
- PM8001F_INIT_TIME
- PM8001F_RUN_TIME
- PM8001_CAN_QUEUE
- PM8001_CHECK_LOGGING
- PM8001_CHIP_DISP
- PM8001_CTL_H_INCLUDED
- PM8001_DISC_DBG
- PM8001_DISC_LOGGING
- PM8001_EH_DBG
- PM8001_EH_LOGGING
- PM8001_EVENT_LOG_SIZE
- PM8001_FAIL_DBG
- PM8001_FAIL_LOGGING
- PM8001_IB_OB_QUEUE_SIZE
- PM8001_INIT_DBG
- PM8001_INIT_LOGGING
- PM8001_IOCTL_DBG
- PM8001_IOCTL_LOGGING
- PM8001_IO_DBG
- PM8001_IO_LOGGING
- PM8001_MAX_CCB
- PM8001_MAX_DEVICES
- PM8001_MAX_DMA_SG
- PM8001_MAX_INB_NUM
- PM8001_MAX_MSIX_VEC
- PM8001_MAX_OUTB_NUM
- PM8001_MAX_PHYS
- PM8001_MAX_PORTS
- PM8001_MAX_SPCV_INB_NUM
- PM8001_MAX_SPCV_OUTB_NUM
- PM8001_MPI_QUEUE
- PM8001_MSG_DBG
- PM8001_MSG_LOGGING
- PM8001_NAME_LENGTH
- PM8001_READ_VPD
- PM8001_TASK_TIMEOUT
- PM8001_USE_MSIX
- PM8001_USE_TASKLET
- PM8004_SUBTYPE
- PM8005_SUBTYPE
- PM800_ALARM
- PM800_ALARM1_EN
- PM800_ALARM_WAKEUP
- PM800_BAT_INT_ENA1
- PM800_BAT_INT_STS1
- PM800_BAT_STS1
- PM800_BIAS_OUT_GP0
- PM800_BIAS_OUT_GP1
- PM800_BIAS_OUT_GP2
- PM800_BIAS_OUT_GP3
- PM800_BUCK
- PM800_BUCK1
- PM800_BUCK1_1
- PM800_BUCK1_2
- PM800_BUCK1_3
- PM800_BUCK1_MISC1
- PM800_BUCK1_SLP1_MASK
- PM800_BUCK1_SLP1_SHIFT
- PM800_BUCK2
- PM800_BUCK3
- PM800_BUCK3_MISC1
- PM800_BUCK4
- PM800_BUCK4_1
- PM800_BUCK4_2
- PM800_BUCK4_3
- PM800_BUCK4_MISC1
- PM800_BUCK5
- PM800_BUCK5_MISC1
- PM800_BUCK_ENA
- PM800_BUCK_PGOOD_STS1
- PM800_BUCK_SLP1
- PM800_CHG_INT_ENA1
- PM800_CHG_INT_STS1
- PM800_CHG_STS1
- PM800_CHIP_GEN_ID_NUM
- PM800_CLASSD_OC_INT_ENA1
- PM800_CLASSD_OC_INT_STS1
- PM800_EXTON_INT_ENA1
- PM800_EXTON_INT_STS1
- PM800_EXTON_STS1
- PM800_GPADC0_GP_PREBIAS_TIME
- PM800_GPADC0_INT_ENA3
- PM800_GPADC0_INT_STS2
- PM800_GPADC0_LOW_TH
- PM800_GPADC0_MEAS1
- PM800_GPADC0_MEAS2
- PM800_GPADC0_UPP_TH
- PM800_GPADC1_INT_ENA3
- PM800_GPADC1_LOW_TH
- PM800_GPADC1_MEAS1
- PM800_GPADC1_MEAS2
- PM800_GPADC1_UPP_TH
- PM800_GPADC2_INT_ENA3
- PM800_GPADC2_INT_STS2
- PM800_GPADC2_LOW_TH
- PM800_GPADC2_MEAS1
- PM800_GPADC2_MEAS2
- PM800_GPADC2_UPP_TH
- PM800_GPADC3_INT_ENA3
- PM800_GPADC3_INT_STS2
- PM800_GPADC3_LOW_TH
- PM800_GPADC3_MEAS1
- PM800_GPADC3_MEAS2
- PM800_GPADC3_UPP_TH
- PM800_GPADC4_AVG1
- PM800_GPADC4_AVG2
- PM800_GPADC4_INT_ENA3
- PM800_GPADC4_LOW_TH
- PM800_GPADC4_MEAS1
- PM800_GPADC4_MEAS2
- PM800_GPADC4_UPP_TH
- PM800_GPADC_GP_BIAS_EN0
- PM800_GPADC_GP_BIAS_EN1
- PM800_GPADC_GP_BIAS_EN2
- PM800_GPADC_GP_BIAS_EN3
- PM800_GPADC_MEAS_EN1
- PM800_GPADC_MEAS_EN2
- PM800_GPADC_MISC_CONFIG1
- PM800_GPADC_MISC_CONFIG2
- PM800_GPADC_MISC_CONFIG3
- PM800_GPADC_MISC_CONFIG4
- PM800_GPADC_MISC_GPFSM_EN
- PM800_GPADC_PREBIAS1
- PM800_GPADC_PREBIAS2
- PM800_GPADC_SLOW_MODE
- PM800_GPIO0_GPIO_MODE
- PM800_GPIO0_INT_ENA4
- PM800_GPIO0_INT_STS4
- PM800_GPIO0_VAL
- PM800_GPIO1_GPIO_MODE
- PM800_GPIO1_INT_ENA4
- PM800_GPIO1_INT_STS4
- PM800_GPIO1_VAL
- PM800_GPIO2_GPIO_MODE
- PM800_GPIO2_INT_ENA4
- PM800_GPIO2_INT_STS4
- PM800_GPIO2_VAL
- PM800_GPIO3_GPIO_MODE
- PM800_GPIO3_HEADSET_MODE
- PM800_GPIO3_INT_ENA4
- PM800_GPIO3_INT_STS4
- PM800_GPIO3_MODE_MASK
- PM800_GPIO3_VAL
- PM800_GPIO4_GPIO_MODE
- PM800_GPIO4_INT_ENA4
- PM800_GPIO4_INT_STS4
- PM800_GPIO4_VAL
- PM800_GPIO_0_1_CNTRL
- PM800_GPIO_2_3_CNTRL
- PM800_GPIO_4_CNTRL
- PM800_GP_BIAS_ENA1
- PM800_GP_BIAS_OUT1
- PM800_HEADSET_CNTRL
- PM800_HEADSET_DET_EN
- PM800_HSDET_SLP
- PM800_ID_BUCK1
- PM800_ID_BUCK2
- PM800_ID_BUCK3
- PM800_ID_BUCK4
- PM800_ID_BUCK5
- PM800_ID_LDO1
- PM800_ID_LDO10
- PM800_ID_LDO11
- PM800_ID_LDO12
- PM800_ID_LDO13
- PM800_ID_LDO14
- PM800_ID_LDO15
- PM800_ID_LDO16
- PM800_ID_LDO17
- PM800_ID_LDO18
- PM800_ID_LDO19
- PM800_ID_LDO2
- PM800_ID_LDO3
- PM800_ID_LDO4
- PM800_ID_LDO5
- PM800_ID_LDO6
- PM800_ID_LDO7
- PM800_ID_LDO8
- PM800_ID_LDO9
- PM800_ID_RG_MAX
- PM800_INT_ENA_1
- PM800_INT_ENA_2
- PM800_INT_ENA_3
- PM800_INT_ENA_4
- PM800_INT_REG_NUM
- PM800_INT_STATUS1
- PM800_INT_STATUS2
- PM800_INT_STATUS3
- PM800_INT_STATUS4
- PM800_IRQ_BAT
- PM800_IRQ_CHG
- PM800_IRQ_CLASSD
- PM800_IRQ_EXTON
- PM800_IRQ_GPADC0
- PM800_IRQ_GPADC1
- PM800_IRQ_GPADC2
- PM800_IRQ_GPADC3
- PM800_IRQ_GPADC4
- PM800_IRQ_GPIO0
- PM800_IRQ_GPIO1
- PM800_IRQ_GPIO2
- PM800_IRQ_GPIO3
- PM800_IRQ_GPIO4
- PM800_IRQ_ONKEY
- PM800_IRQ_RTC
- PM800_IRQ_TINT
- PM800_IRQ_VBAT
- PM800_IRQ_VCHG
- PM800_IRQ_VSYS
- PM800_LDO
- PM800_LDO10_VOUT
- PM800_LDO11_VOUT
- PM800_LDO12_VOUT
- PM800_LDO13_VOUT
- PM800_LDO14_VOUT
- PM800_LDO15_VOUT
- PM800_LDO16_VOUT
- PM800_LDO17_VOUT
- PM800_LDO18_VOUT
- PM800_LDO19_VOUT
- PM800_LDO1_VOUT
- PM800_LDO1_VOUT_2
- PM800_LDO1_VOUT_3
- PM800_LDO2_VOUT
- PM800_LDO3_VOUT
- PM800_LDO4_VOUT
- PM800_LDO5_VOUT
- PM800_LDO6_VOUT
- PM800_LDO7_VOUT
- PM800_LDO8_VOUT
- PM800_LDO9_VOUT
- PM800_LDO_ENA1_1
- PM800_LDO_ENA1_2
- PM800_LDO_ENA1_3
- PM800_LDO_ENA2_1
- PM800_LDO_ENA2_2
- PM800_LDO_ENA2_3
- PM800_LDO_PGOOD_STS1
- PM800_LONG_KEY_DELAY
- PM800_LONG_ONKEY_EN
- PM800_LONKEY_PRESS_TIME
- PM800_LONKEY_PRESS_TIME_MASK
- PM800_LOW_POWER1
- PM800_LOW_POWER2
- PM800_LOW_POWER_CONFIG3
- PM800_LOW_POWER_CONFIG4
- PM800_MAX_IRQ
- PM800_MAX_REGULATOR
- PM800_MEAS_EN1_VBAT
- PM800_MEAS_EN2_RFTMP
- PM800_MEAS_GP0_EN
- PM800_MEAS_GP1_EN
- PM800_MEAS_GP2_EN
- PM800_MEAS_GP3_EN
- PM800_MEAS_GP4_EN
- PM800_NUM_BUCK
- PM800_NUM_LDO
- PM800_ONKEY_INT_ENA1
- PM800_ONKEY_INT_STS1
- PM800_ONKEY_STS1
- PM800_PMOD_MEAS1
- PM800_PMOD_MEAS2
- PM800_POWER_DOWN_LOG1
- PM800_POWER_DOWN_LOG2
- PM800_POWER_UP_LOG
- PM800_PWM1
- PM800_PWM2
- PM800_PWM3
- PM800_PWM4
- PM800_RTC1_USE_XO
- PM800_RTC_ALARM_STS2
- PM800_RTC_CONTROL
- PM800_RTC_COUNTER1
- PM800_RTC_COUNTER2
- PM800_RTC_COUNTER3
- PM800_RTC_COUNTER4
- PM800_RTC_EXPIRE1_1
- PM800_RTC_EXPIRE1_2
- PM800_RTC_EXPIRE1_3
- PM800_RTC_EXPIRE1_4
- PM800_RTC_EXPIRE2_1
- PM800_RTC_EXPIRE2_2
- PM800_RTC_EXPIRE2_3
- PM800_RTC_EXPIRE2_4
- PM800_RTC_INT_ENA1
- PM800_RTC_INT_STS1
- PM800_RTC_MISC1
- PM800_RTC_MISC2
- PM800_RTC_MISC3
- PM800_RTC_MISC4
- PM800_RTC_MISC5
- PM800_RTC_TRIM1
- PM800_RTC_TRIM2
- PM800_RTC_TRIM3
- PM800_RTC_TRIM4
- PM800_SLEEP_BUCK1
- PM800_STATUS0_INT_MASK
- PM800_STATUS_1
- PM800_STATUS_2
- PM800_SW_PDOWN
- PM800_TBAT_INT_STS2
- PM800_TINT_INT_ENA2
- PM800_TINT_INT_STS2
- PM800_TINT_MEAS1
- PM800_TINT_MEAS2
- PM800_VBAT_INT_ENA2
- PM800_VBAT_INT_STS2
- PM800_VBAT_MEAS1
- PM800_VBAT_MEAS2
- PM800_VBBAT_MEAS1
- PM800_VBBAT_MEAS2
- PM800_VBUS_STS1
- PM800_VCHG_INT_ENA2
- PM800_VCHG_INT_STS2
- PM800_VCHG_MEAS1
- PM800_VCHG_MEAS2
- PM800_VSYS_INT_ENA2
- PM800_VSYS_INT_STS2
- PM800_VSYS_MEAS1
- PM800_VSYS_MEAS2
- PM800_WAKEUP1
- PM800_WAKEUP2
- PM800_WAKEUP2_INT_CLEAR
- PM800_WAKEUP2_INT_MASK
- PM800_WAKEUP2_INV_INT
- PM8018_GPIO_L14
- PM8018_GPIO_L2
- PM8018_GPIO_L4
- PM8018_GPIO_L5
- PM8018_GPIO_L6
- PM8018_GPIO_S3
- PM8018_GPIO_VDD
- PM8018_MPP_L14
- PM8018_MPP_L2
- PM8018_MPP_L4
- PM8018_MPP_L5
- PM8018_MPP_L6
- PM8018_MPP_S3
- PM8018_MPP_VPH
- PM8019_SUBTYPE
- PM8038_GPIO10_11_EXT_REG_EN
- PM8038_GPIO1_2_LPG_DRV
- PM8038_GPIO3_5V_BOOST_EN
- PM8038_GPIO4_SSBI_ALT_CLK
- PM8038_GPIO5_6_EXT_REG_EN
- PM8038_GPIO6_12_KYPD_DRV
- PM8038_GPIO6_7_CLK
- PM8038_GPIO9_BAT_ALRM_OUT
- PM8038_GPIO_BB
- PM8038_GPIO_L11
- PM8038_GPIO_L15
- PM8038_GPIO_L17
- PM8038_GPIO_L3
- PM8038_GPIO_L4
- PM8038_GPIO_VPH
- PM8038_MPP_L11
- PM8038_MPP_L15
- PM8038_MPP_L17
- PM8038_MPP_L20
- PM8038_MPP_L5
- PM8038_MPP_VPH
- PM8058_AMUX_PRESCALE_0
- PM8058_AMUX_PRESCALE_1
- PM8058_AMUX_PRESCALE_1_DIV3
- PM8058_GPIO21_23_UART_TX
- PM8058_GPIO24_26_LPG_DRV
- PM8058_GPIO33_BCLK_19P2MHZ
- PM8058_GPIO34_35_MP3_CLK
- PM8058_GPIO36_BCLK_19P2MHZ
- PM8058_GPIO37_UART_M_RX
- PM8058_GPIO37_UPL_OUT
- PM8058_GPIO38_39_CLK_32KHZ
- PM8058_GPIO38_XO_SLEEP_CLK
- PM8058_GPIO39_MP3_CLK
- PM8058_GPIO40_EXT_BB_EN
- PM8058_GPIO7_8_BCLK_19P2MHZ
- PM8058_GPIO7_8_MP3_CLK
- PM8058_GPIO9_26_KYPD_DRV
- PM8058_GPIO_BB
- PM8058_GPIO_L2
- PM8058_GPIO_L3
- PM8058_GPIO_L5
- PM8058_GPIO_L6
- PM8058_GPIO_L7
- PM8058_GPIO_S3
- PM8058_GPIO_VPH
- PM8058_L21_CTRL
- PM8058_L22_CTRL
- PM8058_LED_TYPE_COMMON
- PM8058_LED_TYPE_COMMON_MASK
- PM8058_LED_TYPE_COMMON_SHIFT
- PM8058_LED_TYPE_FLASH
- PM8058_LED_TYPE_KEYPAD
- PM8058_LED_TYPE_KEYPAD_MASK
- PM8058_LED_TYPE_KEYPAD_SHIFT
- PM8058_MPP_L2
- PM8058_MPP_L3
- PM8058_MPP_S3
- PM8058_MPP_VPH
- PM8058_REGULATOR_BANK_MASK
- PM8058_REGULATOR_BANK_SEL
- PM8058_REGULATOR_BANK_SHIFT
- PM8058_REGULATOR_BANK_WRITE
- PM8058_REGULATOR_DISABLE
- PM8058_REGULATOR_ENABLE
- PM8058_REGULATOR_ENABLE_MASK
- PM8058_REGULATOR_PULL_DOWN_EN
- PM8058_REGULATOR_PULL_DOWN_MASK
- PM8058_S0_CTRL
- PM8058_S0_TEST2
- PM8058_S1_CTRL
- PM8058_S1_TEST2
- PM8058_S3_CTRL
- PM8058_S3_TEST2
- PM8058_SLEEP_CTRL
- PM8058_SMPS_ADVANCED_BAND_MASK
- PM8058_SMPS_ADVANCED_BAND_SHIFT
- PM8058_SMPS_ADVANCED_MODE
- PM8058_SMPS_ADVANCED_MODE_MASK
- PM8058_SMPS_ADVANCED_VPROG_MASK
- PM8058_SMPS_LEGACY_MODE
- PM8058_SMPS_LEGACY_VLOW_SEL
- PM8058_SMPS_LEGACY_VPROG_MASK
- PM8058_SMPS_LEGACY_VREF_SEL
- PM805_ADC_GAIN1
- PM805_ADC_GAIN2
- PM805_ADC_SETTING1
- PM805_ADC_SETTING2
- PM805_ADC_SETTING3
- PM805_AUTO_SEQ_SETTING
- PM805_AUTO_SEQ_STATUS1
- PM805_AUTO_SEQ_STATUS2
- PM805_DMIC_SETTING
- PM805_DWS_SETTING
- PM805_EARPHONE_SETTING
- PM805_HEADPHONE_GAIN_A2A
- PM805_HEADPHONE_SETTING
- PM805_HEADPHONE_SHORT_STATE
- PM805_INT1_CLIP_FAULT
- PM805_INT1_HP1_SHRT
- PM805_INT1_HP2_SHRT
- PM805_INT1_LDO_OFF
- PM805_INT1_MIC_CONFLICT
- PM805_INT1_SRC_DPLL_LOCK
- PM805_INT2_FINE_PLL_FAULT
- PM805_INT2_MIC_DET
- PM805_INT2_RAW_PLL_FAULT
- PM805_INT2_SHRT_BTN_DET
- PM805_INT2_VOLM_BTN_DET
- PM805_INT2_VOLP_BTN_DET
- PM805_INT_MASK1
- PM805_INT_MASK2
- PM805_INT_REG_NUM
- PM805_INT_STATUS0
- PM805_INT_STATUS1
- PM805_INT_STATUS2
- PM805_IRQ_CLIP_FAULT
- PM805_IRQ_FINE_PLL_FAULT
- PM805_IRQ_HP1_SHRT
- PM805_IRQ_HP2_SHRT
- PM805_IRQ_LDO_OFF
- PM805_IRQ_MIC_CONFLICT
- PM805_IRQ_MIC_DET
- PM805_IRQ_RAW_PLL_FAULT
- PM805_IRQ_SHRT_BTN_DET
- PM805_IRQ_SRC_DPLL_LOCK
- PM805_IRQ_VOLM_BTN_DET
- PM805_IRQ_VOLP_BTN_DET
- PM805_MAIN_POWERUP
- PM805_MAX_IRQ
- PM805_MIC_CONFLICT_STS
- PM805_MIC_DET1
- PM805_MIC_DET2
- PM805_MIC_DET_EN_MIC_DET
- PM805_MIC_DET_STATUS1
- PM805_MIC_DET_STATUS3
- PM805_PDM_CONTROL1
- PM805_PDM_CONTROL2
- PM805_PDM_CONTROL3
- PM805_PDM_SETTING1
- PM805_PDM_SETTING2
- PM805_PDM_SETTING3
- PM805_SHRT_BTN_DET
- PM805_STATUS0_INT_CLEAR
- PM805_STATUS0_INV_INT
- PM80XX_IB_OB_QUEUE_SIZE
- PM80X_CHIP_ID
- PM80X_CHIP_ID_NUM
- PM80X_CHIP_ID_REVISION
- PM8110_SUBTYPE
- PM8226_SUBTYPE
- PM8606_CHIP_ID
- PM8606_DCM_1000MA
- PM8606_DCM_1250MA
- PM8606_DCM_250MV
- PM8606_DCM_300MV
- PM8606_DCM_350MV
- PM8606_DCM_400MV
- PM8606_DCM_500MA
- PM8606_DCM_750MA
- PM8606_DCM_BOOST
- PM8606_FLAGS
- PM8606_ID_BACKLIGHT
- PM8606_ID_CHARGER
- PM8606_ID_INVALID
- PM8606_ID_LED
- PM8606_ID_MAX
- PM8606_ID_PREG
- PM8606_ID_SOUND
- PM8606_ID_TOUCH
- PM8606_ID_VIBRATOR
- PM8606_LED_CURRENT
- PM8606_MISC
- PM8606_MISC_OSC_EN
- PM8606_PREG
- PM8606_PREREGULATORA
- PM8606_PREREGULATORB
- PM8606_PROTECTA
- PM8606_PROTECTB
- PM8606_PROTECTC
- PM8606_PWM
- PM8606_PWM_15600HZ
- PM8606_PWM_1950HZ
- PM8606_PWM_244HZ
- PM8606_PWM_31200HZ
- PM8606_PWM_3900HZ
- PM8606_PWM_488HZ
- PM8606_PWM_7800HZ
- PM8606_PWM_976HZ
- PM8606_PWM_FREQ_MASK
- PM8606_REF_GP_OSC_OFF
- PM8606_REF_GP_OSC_ON
- PM8606_REF_GP_OSC_UNKNOWN
- PM8606_RGB1A
- PM8606_RGB1B
- PM8606_RGB1C
- PM8606_RGB1D
- PM8606_RGB2A
- PM8606_RGB2B
- PM8606_RGB2C
- PM8606_RGB2D
- PM8606_STATUS
- PM8606_VCHG
- PM8606_VIBRATORA
- PM8606_VIBRATORB
- PM8606_VSYS
- PM8606_VSYS_EN
- PM8606_WLED1A
- PM8606_WLED1B
- PM8606_WLED2A
- PM8606_WLED2B
- PM8606_WLED3A
- PM8606_WLED3B
- PM8606_WLED_CURRENT
- PM8606_WLED_ON
- PM8607_A1_MISC1
- PM8607_A1_MISC1_PI2C
- PM8607_B0_MISC1
- PM8607_B0_MISC1_INT_CLEAR
- PM8607_B0_MISC1_INT_MASK
- PM8607_B0_MISC1_INV_INT
- PM8607_B0_MISC1_PI2C
- PM8607_B0_MISC1_RESET
- PM8607_BUCK1
- PM8607_BUCK2
- PM8607_BUCK3
- PM8607_BUCK3_DOUBLE
- PM8607_BUCK_CONTROLS
- PM8607_CCNT
- PM8607_CCNT_MEAS1
- PM8607_CCNT_MEAS2
- PM8607_CHG_CTRL1
- PM8607_CHG_CTRL2
- PM8607_CHG_CTRL3
- PM8607_CHG_CTRL4
- PM8607_CHG_CTRL5
- PM8607_CHG_CTRL6
- PM8607_CHG_CTRL7
- PM8607_CHIP_A0
- PM8607_CHIP_A1
- PM8607_CHIP_B0
- PM8607_CHIP_ID
- PM8607_DVC
- PM8607_DVC3
- PM8607_GO
- PM8607_GPADC0_GP_BIAS_A0
- PM8607_GPADC0_HIGHTH
- PM8607_GPADC0_LOWTH
- PM8607_GPADC0_MEAS1
- PM8607_GPADC0_MEAS2
- PM8607_GPADC1_GP_BIAS_A1
- PM8607_GPADC1_HIGHTH
- PM8607_GPADC1_LOWTH
- PM8607_GPADC1_MEAS1
- PM8607_GPADC1_MEAS2
- PM8607_GPADC2_GP_BIAS_A2
- PM8607_GPADC2_GP_BIAS_OUT2
- PM8607_GPADC2_HIGHTH
- PM8607_GPADC2_LOWTH
- PM8607_GPADC2_MEAS1
- PM8607_GPADC2_MEAS2
- PM8607_GPADC3_GP_BIAS_A3
- PM8607_GPADC3_HIGHTH
- PM8607_GPADC3_LOWTH
- PM8607_GPADC3_MEAS1
- PM8607_GPADC3_MEAS2
- PM8607_GPADC_EN
- PM8607_GPADC_MISC1
- PM8607_GPADC_MISC2
- PM8607_GPADC_OFF_SCALE_MASK
- PM8607_GPADC_PREBIAS_MASK
- PM8607_GPADC_SLOT_CYCLE_MASK
- PM8607_GPADC_SW_CAL_MASK
- PM8607_GP_BIAS1
- PM8607_GP_BIAS2
- PM8607_GROUP1
- PM8607_GROUP2
- PM8607_GROUP3
- PM8607_GROUP4
- PM8607_GROUP5
- PM8607_GROUP6
- PM8607_IBAT_MEAS1
- PM8607_IBAT_MEAS2
- PM8607_ID_BUCK1
- PM8607_ID_BUCK2
- PM8607_ID_BUCK3
- PM8607_ID_LDO1
- PM8607_ID_LDO10
- PM8607_ID_LDO11
- PM8607_ID_LDO12
- PM8607_ID_LDO13
- PM8607_ID_LDO14
- PM8607_ID_LDO15
- PM8607_ID_LDO2
- PM8607_ID_LDO3
- PM8607_ID_LDO4
- PM8607_ID_LDO5
- PM8607_ID_LDO6
- PM8607_ID_LDO7
- PM8607_ID_LDO8
- PM8607_ID_LDO9
- PM8607_ID_RG_MAX
- PM8607_INT_MASK_1
- PM8607_INT_MASK_2
- PM8607_INT_MASK_3
- PM8607_INT_STATUS1
- PM8607_INT_STATUS2
- PM8607_INT_STATUS3
- PM8607_IRQ_AUDIO_SHORT
- PM8607_IRQ_BAT
- PM8607_IRQ_CC
- PM8607_IRQ_CHG
- PM8607_IRQ_CHG_DONE
- PM8607_IRQ_CHG_FAIL
- PM8607_IRQ_CHG_FAULT
- PM8607_IRQ_EXTON
- PM8607_IRQ_GPADC0
- PM8607_IRQ_GPADC1
- PM8607_IRQ_GPADC2
- PM8607_IRQ_GPADC3
- PM8607_IRQ_HEADSET
- PM8607_IRQ_HOOK
- PM8607_IRQ_MICIN
- PM8607_IRQ_ONKEY
- PM8607_IRQ_PEN
- PM8607_IRQ_RTC
- PM8607_IRQ_TINT
- PM8607_IRQ_VBAT
- PM8607_IRQ_VCHG
- PM8607_IRQ_VSYS
- PM8607_LDO
- PM8607_LDO1
- PM8607_LDO10
- PM8607_LDO12
- PM8607_LDO14
- PM8607_LDO2
- PM8607_LDO3
- PM8607_LDO4
- PM8607_LDO5
- PM8607_LDO6
- PM8607_LDO7
- PM8607_LDO8
- PM8607_LDO9
- PM8607_MEAS_EN1
- PM8607_MEAS_EN1_GPADC2
- PM8607_MEAS_EN1_GPADC3
- PM8607_MEAS_EN1_RFTMP
- PM8607_MEAS_EN1_TBAT
- PM8607_MEAS_EN1_TINT
- PM8607_MEAS_EN1_VBAT
- PM8607_MEAS_EN1_VCHG
- PM8607_MEAS_EN1_VSYS
- PM8607_MEAS_EN2
- PM8607_MEAS_EN3
- PM8607_MEAS_OFF_TIME1
- PM8607_MEAS_OFF_TIME2
- PM8607_MISC2
- PM8607_PD_PREBIAS
- PM8607_PD_PREBIAS_MASK
- PM8607_PD_PRECHG_MASK
- PM8607_POWER_UP_LOG
- PM8607_RTC1
- PM8607_RTC_COUNTER1
- PM8607_RTC_COUNTER2
- PM8607_RTC_COUNTER3
- PM8607_RTC_COUNTER4
- PM8607_RTC_EXPIRE1
- PM8607_RTC_EXPIRE2
- PM8607_RTC_EXPIRE3
- PM8607_RTC_EXPIRE4
- PM8607_RTC_MISC1
- PM8607_RTC_MISC2
- PM8607_RTC_MISC3
- PM8607_RTC_TRIM1
- PM8607_RTC_TRIM2
- PM8607_RTC_TRIM3
- PM8607_RTC_TRIM4
- PM8607_SLEEP_BUCK1
- PM8607_SLEEP_BUCK2
- PM8607_SLEEP_BUCK3
- PM8607_SLEEP_MODE1
- PM8607_SLEEP_MODE2
- PM8607_SLEEP_MODE3
- PM8607_SLEEP_MODE4
- PM8607_STATUS_1
- PM8607_STATUS_2
- PM8607_STATUS_BAT
- PM8607_STATUS_CC
- PM8607_STATUS_CHG
- PM8607_STATUS_EXTON
- PM8607_STATUS_HEADSET
- PM8607_STATUS_HOOK
- PM8607_STATUS_MICIN
- PM8607_STATUS_ONKEY
- PM8607_STATUS_OV
- PM8607_STATUS_PEN
- PM8607_STATUS_VBUS
- PM8607_SUPPLIES_EN11
- PM8607_SUPPLIES_EN12
- PM8607_SUPPLIES_EN21
- PM8607_SUPPLIES_EN22
- PM8607_TINT_HIGHTH
- PM8607_TINT_LOWTH
- PM8607_TINT_MEAS1
- PM8607_TINT_MEAS2
- PM8607_TSI_PREBIAS
- PM8607_VBAT_AVG
- PM8607_VBAT_HIGHTH
- PM8607_VBAT_LOWTH
- PM8607_VBAT_MAX
- PM8607_VBAT_MEAS1
- PM8607_VBAT_MEAS2
- PM8607_VBAT_MIN
- PM8607_VCHG_AVG
- PM8607_VCHG_HIGHTH
- PM8607_VCHG_LOWTH
- PM8607_VCHG_MAX
- PM8607_VCHG_MEAS1
- PM8607_VCHG_MEAS2
- PM8607_VCHG_MIN
- PM8607_VERSION_MASK
- PM8607_VIBRATOR_PWM
- PM8607_VIBRATOR_SET
- PM8607_VSYS_AVG
- PM8607_VSYS_HIGHTH
- PM8607_VSYS_LOWTH
- PM8607_VSYS_MAX
- PM8607_VSYS_MEAS1
- PM8607_VSYS_MEAS2
- PM8607_VSYS_MIN
- PM8607_WAKEUP
- PM860X_ADC_ANA_1
- PM860X_ADC_ANA_2
- PM860X_ADC_ANA_3
- PM860X_ADC_ANA_4
- PM860X_ADC_EN_1
- PM860X_ADC_EN_2
- PM860X_ADC_OFFSET_1
- PM860X_ADC_OFFSET_2
- PM860X_ANA_INPUT_SEL_1
- PM860X_ANA_INPUT_SEL_2
- PM860X_ANA_TO_ANA
- PM860X_AUDIO_CAL_1
- PM860X_AUDIO_CAL_2
- PM860X_AUDIO_CAL_3
- PM860X_AUDIO_CAL_4
- PM860X_AUDIO_CAL_5
- PM860X_AUDIO_SUPPLIES_1
- PM860X_AUDIO_SUPPLIES_2
- PM860X_CLK_DIR_IN
- PM860X_CLK_DIR_OUT
- PM860X_DAC_EN_1
- PM860X_DAC_EN_2
- PM860X_DAC_OFFSET
- PM860X_DAPM_OUTPUT
- PM860X_DET_HEADSET
- PM860X_DET_HOOK
- PM860X_DET_MASK
- PM860X_DET_MIC
- PM860X_DMIC_DELAY
- PM860X_EAR_CTRL_1
- PM860X_EAR_CTRL_2
- PM860X_EC_PATH
- PM860X_EQUALIZER_D1_1
- PM860X_EQUALIZER_D1_2
- PM860X_EQUALIZER_N0_1
- PM860X_EQUALIZER_N0_2
- PM860X_EQUALIZER_N1_1
- PM860X_EQUALIZER_N1_2
- PM860X_HIFIL_GAIN_LEFT
- PM860X_HIFIL_GAIN_RIGHT
- PM860X_HIFIR_GAIN_LEFT
- PM860X_HIFIR_GAIN_RIGHT
- PM860X_HS1_CTRL
- PM860X_HS2_CTRL
- PM860X_I2S_IFACE_1
- PM860X_I2S_IFACE_2
- PM860X_I2S_IFACE_3
- PM860X_I2S_IFACE_4
- PM860X_I2S_IFACE_5
- PM860X_LO1_CTRL
- PM860X_LO2_CTRL
- PM860X_LOFI_GAIN_LEFT
- PM860X_LOFI_GAIN_RIGHT
- PM860X_OFFSET_LEFT_1
- PM860X_OFFSET_LEFT_2
- PM860X_OFFSET_RIGHT_1
- PM860X_OFFSET_RIGHT_2
- PM860X_PCM_IFACE_1
- PM860X_PCM_IFACE_2
- PM860X_PCM_IFACE_3
- PM860X_PCM_IFACE_4
- PM860X_PCM_RATE
- PM860X_PLL_ADJ_1
- PM860X_PLL_ADJ_2
- PM860X_RATES
- PM860X_SHORTS
- PM860X_SHORT_HEADSET
- PM860X_SHORT_LINEOUT
- PM860X_SIDETONE_L_GAIN
- PM860X_SIDETONE_R_GAIN
- PM860X_SIDETONE_SHIFT
- PM860X_TEMP_TBAT
- PM860X_TEMP_TINT
- PM8821_BLOCKS_PER_MASTER
- PM8821_MPP_1P8
- PM8821_MPP_VPH
- PM8821_NR_IRQS
- PM8821_SSBI_ADDR_IRQ_CLEAR
- PM8821_SSBI_ADDR_IRQ_MASK
- PM8821_SSBI_ADDR_IRQ_ROOT
- PM8821_SSBI_ADDR_IRQ_RT_STATUS
- PM8821_SSBI_REG
- PM8821_SSBI_REG_ADDR_IRQ_BASE
- PM8821_SSBI_REG_ADDR_IRQ_MASTER0
- PM8821_SSBI_REG_ADDR_IRQ_MASTER1
- PM8841_MPP_S3
- PM8841_MPP_VPH
- PM8841_SUBTYPE
- PM8901_MPP_DIG
- PM8901_MPP_L5
- PM8901_MPP_MSMIO
- PM8901_MPP_S4
- PM8901_MPP_VPH
- PM8909_SUBTYPE
- PM8916_GPIO1_BAT_ALRM_OUT
- PM8916_GPIO1_KEYP_DRV
- PM8916_GPIO2_DIV_CLK
- PM8916_GPIO2_SLEEP_CLK
- PM8916_GPIO3_KEYP_DRV
- PM8916_GPIO4_KEYP_DRV
- PM8916_GPIO_L2
- PM8916_GPIO_L5
- PM8916_GPIO_VPH
- PM8916_MPP_L2
- PM8916_MPP_L5
- PM8916_MPP_VPH
- PM8916_SUBTYPE
- PM8916_WDT_DEFAULT_TIMEOUT
- PM8916_WDT_MAX_TIMEOUT
- PM8916_WDT_MIN_TIMEOUT
- PM8917_GPIO20_BAT_ALRM_OUT
- PM8917_GPIO21_23_UART_TX
- PM8917_GPIO25_26_EXT_REG_EN
- PM8917_GPIO37_38_MP3_CLK
- PM8917_GPIO37_38_XO_SLEEP_CLK
- PM8917_GPIO9_18_KEYP_DRV
- PM8917_GPIO_L15
- PM8917_GPIO_L17
- PM8917_GPIO_L3
- PM8917_GPIO_L4
- PM8917_GPIO_S4
- PM8917_GPIO_VPH
- PM8921_GPIO_BB
- PM8921_GPIO_L15
- PM8921_GPIO_L17
- PM8921_GPIO_L3
- PM8921_GPIO_L4
- PM8921_GPIO_S4
- PM8921_GPIO_VPH
- PM8921_MPP_L15
- PM8921_MPP_L17
- PM8921_MPP_S4
- PM8921_MPP_VPH
- PM8921_SLEEP_CTRL
- PM8941_GPIO15_18_DIV_CLK
- PM8941_GPIO15_18_SLEEP_CLK
- PM8941_GPIO23_26_KYPD_DRV
- PM8941_GPIO23_26_LPG_DRV_HI
- PM8941_GPIO31_BAT_ALRM_OUT
- PM8941_GPIO33_36_LPG_DRV_3D
- PM8941_GPIO33_36_LPG_DRV_HI
- PM8941_GPIO9_14_KYPD_DRV
- PM8941_GPIO_L1
- PM8941_GPIO_L6
- PM8941_GPIO_S3
- PM8941_GPIO_VPH
- PM8941_MPP_L1
- PM8941_MPP_L6
- PM8941_MPP_S3
- PM8941_MPP_VPH
- PM8941_SUBTYPE
- PM8941_WLED_DEFAULT_BRIGHTNESS
- PM8941_WLED_REG_BOOST
- PM8941_WLED_REG_BOOST_MASK
- PM8941_WLED_REG_FREQ
- PM8941_WLED_REG_FREQ_MASK
- PM8941_WLED_REG_MOD_EN
- PM8941_WLED_REG_MOD_EN_BIT
- PM8941_WLED_REG_MOD_EN_MASK
- PM8941_WLED_REG_OVP
- PM8941_WLED_REG_OVP_MASK
- PM8941_WLED_REG_SINK
- PM8941_WLED_REG_SINK_MASK
- PM8941_WLED_REG_SINK_SHFT
- PM8941_WLED_REG_STR_CABC_BASE
- PM8941_WLED_REG_STR_CABC_EN
- PM8941_WLED_REG_STR_CABC_MASK
- PM8941_WLED_REG_STR_MOD_EN
- PM8941_WLED_REG_STR_MOD_EN_BASE
- PM8941_WLED_REG_STR_MOD_MASK
- PM8941_WLED_REG_STR_MOD_SRC_BASE
- PM8941_WLED_REG_STR_MOD_SRC_EXT
- PM8941_WLED_REG_STR_MOD_SRC_INT
- PM8941_WLED_REG_STR_MOD_SRC_MASK
- PM8941_WLED_REG_STR_OFFSET
- PM8941_WLED_REG_STR_SCALE_BASE
- PM8941_WLED_REG_STR_SCALE_MASK
- PM8941_WLED_REG_SYNC
- PM8941_WLED_REG_SYNC_ALL
- PM8941_WLED_REG_SYNC_CLEAR
- PM8941_WLED_REG_SYNC_LED1
- PM8941_WLED_REG_SYNC_LED2
- PM8941_WLED_REG_SYNC_LED3
- PM8941_WLED_REG_SYNC_MASK
- PM8941_WLED_REG_VAL_BASE
- PM8941_WLED_REG_VAL_MAX
- PM8994_GPIO_L12
- PM8994_GPIO_S4
- PM8994_GPIO_VPH
- PM8994_MPP_L12
- PM8994_MPP_L19
- PM8994_MPP_S4
- PM8994_MPP_VPH
- PM8994_SUBTYPE
- PM8998_SUBTYPE
- PM8XXX_ALARM_CTRL_OFFSET
- PM8XXX_ALARM_RW_OFFSET
- PM8XXX_BANK_WRITE
- PM8XXX_CHANNEL_125V
- PM8XXX_CHANNEL_INTERNAL
- PM8XXX_CHANNEL_INTERNAL_2
- PM8XXX_CHANNEL_MUXOFF
- PM8XXX_CONFIG_ALEVEL
- PM8XXX_CONFIG_AMUX
- PM8XXX_CONFIG_DTEST_SELECTOR
- PM8XXX_CONFIG_PAIRED
- PM8XXX_GPIO_BIAS_NP
- PM8XXX_GPIO_BIAS_PD
- PM8XXX_GPIO_BIAS_PU_1P5
- PM8XXX_GPIO_BIAS_PU_1P5_30
- PM8XXX_GPIO_BIAS_PU_30
- PM8XXX_GPIO_BIAS_PU_31P5
- PM8XXX_GPIO_MODE_ENABLED
- PM8XXX_GPIO_MODE_INPUT
- PM8XXX_GPIO_MODE_OUTPUT
- PM8XXX_GPIO_OPEN_DRAIN
- PM8XXX_GPIO_PHYSICAL_OFFSET
- PM8XXX_GPIO_PUSH_PULL
- PM8XXX_MATRIX_MAX_SIZE
- PM8XXX_MAX_COLS
- PM8XXX_MAX_GPIOS
- PM8XXX_MAX_MPPS
- PM8XXX_MAX_ROWS
- PM8XXX_MIN_COLS
- PM8XXX_MIN_ROWS
- PM8XXX_MPP_ANALOG
- PM8XXX_MPP_AOUT_CTRL_DISABLE
- PM8XXX_MPP_AOUT_CTRL_ENABLE
- PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN
- PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN
- PM8XXX_MPP_BI_PULLUP_10KOHM
- PM8XXX_MPP_BI_PULLUP_1KOHM
- PM8XXX_MPP_BI_PULLUP_30KOHM
- PM8XXX_MPP_BI_PULLUP_OPEN
- PM8XXX_MPP_CS_CTRL_DISABLE
- PM8XXX_MPP_CS_CTRL_ENABLE
- PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN
- PM8XXX_MPP_CS_CTRL_MPP_LOW_EN
- PM8XXX_MPP_DIGITAL
- PM8XXX_MPP_DIN_TO_DBUS1
- PM8XXX_MPP_DIN_TO_DBUS2
- PM8XXX_MPP_DIN_TO_DBUS3
- PM8XXX_MPP_DIN_TO_INT
- PM8XXX_MPP_DOUT_CTRL_HIGH
- PM8XXX_MPP_DOUT_CTRL_INV_MPP
- PM8XXX_MPP_DOUT_CTRL_LOW
- PM8XXX_MPP_DOUT_CTRL_MPP
- PM8XXX_MPP_DTEST_CS_CTRL_EN1
- PM8XXX_MPP_DTEST_CS_CTRL_EN2
- PM8XXX_MPP_DTEST_CS_CTRL_EN3
- PM8XXX_MPP_DTEST_CS_CTRL_EN4
- PM8XXX_MPP_DTEST_DBUS1
- PM8XXX_MPP_DTEST_DBUS2
- PM8XXX_MPP_DTEST_DBUS3
- PM8XXX_MPP_DTEST_DBUS4
- PM8XXX_MPP_SINK
- PM8XXX_MPP_TYPE_A_INPUT
- PM8XXX_MPP_TYPE_A_OUTPUT
- PM8XXX_MPP_TYPE_DTEST_OUTPUT
- PM8XXX_MPP_TYPE_DTEST_SINK
- PM8XXX_MPP_TYPE_D_BI_DIR
- PM8XXX_MPP_TYPE_D_INPUT
- PM8XXX_MPP_TYPE_D_OUTPUT
- PM8XXX_MPP_TYPE_SINK
- PM8XXX_NR_IRQS
- PM8XXX_QCOM_DRIVE_STRENGH
- PM8XXX_QCOM_PULL_UP_STRENGTH
- PM8XXX_ROW_SHIFT
- PM8XXX_RTC_READ_OFFSET
- PM8XXX_RTC_WRITE_OFFSET
- PM8xxx_RTC_ALARM_CLEAR
- PM8xxx_RTC_ENABLE
- PMA
- PMA8084_GPIO15_18_DIV_CLK
- PMA8084_GPIO15_18_SLEEP_CLK
- PMA8084_GPIO19_21_KEYP_DRV
- PMA8084_GPIO22_BAT_ALRM_OUT
- PMA8084_GPIO4_5_LPG_DRV
- PMA8084_GPIO5_14_KEYP_DRV
- PMA8084_GPIO7_10_LPG_DRV
- PMA8084_GPIO_L1
- PMA8084_GPIO_L6
- PMA8084_GPIO_S4
- PMA8084_GPIO_VPH
- PMA8084_MPP_L1
- PMA8084_MPP_L6
- PMA8084_MPP_S4
- PMA8084_MPP_VPH
- PMA8084_SUBTYPE
- PMACZILOG_CONSOLE
- PMACZILOG_FLAG_BREAK
- PMACZILOG_FLAG_HAS_DMA
- PMACZILOG_FLAG_IS_CHANNEL_A
- PMACZILOG_FLAG_IS_CONS
- PMACZILOG_FLAG_IS_EXTCLK
- PMACZILOG_FLAG_IS_INTMODEM
- PMACZILOG_FLAG_IS_IRDA
- PMACZILOG_FLAG_IS_KGDB
- PMACZILOG_FLAG_IS_OPEN
- PMACZILOG_FLAG_MODEM_STATUS
- PMACZILOG_FLAG_REGS_HELD
- PMACZILOG_FLAG_RSRC_REQUESTED
- PMACZILOG_FLAG_TX_ACTIVE
- PMACZILOG_FLAG_TX_STOPPED
- PMACZILOG_MAJOR
- PMACZILOG_MINOR
- PMACZILOG_NAME
- PMAC_AMP_AVAIL
- PMAC_AWACS
- PMAC_BURGUNDY
- PMAC_DACA
- PMAC_FTR_1394_CABLE_POWER
- PMAC_FTR_1394_ENABLE
- PMAC_FTR_AACK_DELAY_ENABLE
- PMAC_FTR_AIRPORT_ENABLE
- PMAC_FTR_BMAC_ENABLE
- PMAC_FTR_DEF
- PMAC_FTR_DEVICE_CAN_WAKE
- PMAC_FTR_ENABLE_MPIC
- PMAC_FTR_GET_MB_INFO
- PMAC_FTR_GMAC_ENABLE
- PMAC_FTR_GMAC_PHY_RESET
- PMAC_FTR_IDE_ENABLE
- PMAC_FTR_IDE_RESET
- PMAC_FTR_MESH_ENABLE
- PMAC_FTR_MODEM_ENABLE
- PMAC_FTR_READ_GPIO
- PMAC_FTR_RESET_CPU
- PMAC_FTR_SCC_ENABLE
- PMAC_FTR_SLEEP_STATE
- PMAC_FTR_SOUND_CHIP_ENABLE
- PMAC_FTR_SWIM3_ENABLE
- PMAC_FTR_USB_ENABLE
- PMAC_FTR_WRITE_GPIO
- PMAC_HD_CTL
- PMAC_HD_CTL_AC
- PMAC_HD_CTL_ADD
- PMAC_HD_CTL_AS
- PMAC_HD_CTL_AST
- PMAC_HD_CTL_CCRC
- PMAC_HD_CTL_FC
- PMAC_HD_CTL_RC
- PMAC_HD_CTL_RL2
- PMAC_HD_CTL_RST
- PMAC_HD_CTL_RXSH
- PMAC_HD_CTL_TAG
- PMAC_IDE_REG
- PMAC_MAX_FRAGS
- PMAC_MB_CAN_SLEEP
- PMAC_MB_HAS_FW_POWER
- PMAC_MB_INFO_FLAGS
- PMAC_MB_INFO_MODEL
- PMAC_MB_INFO_NAME
- PMAC_MB_MAY_SLEEP
- PMAC_MB_MOBILE
- PMAC_MB_OLD_CORE99
- PMAC_RX_IPG
- PMAC_RX_IPG_MASK
- PMAC_SCC_ASYNC
- PMAC_SCC_FLAG_XMON
- PMAC_SCC_I2S1
- PMAC_SCC_IRDA
- PMAC_SCREAMER
- PMAC_SNAPPER
- PMAC_SUPPORT_AUTOMUTE
- PMAC_TUMBLER
- PMAC_TYPE_101_PBOOK
- PMAC_TYPE_ALCHEMY
- PMAC_TYPE_ANS
- PMAC_TYPE_COMET
- PMAC_TYPE_CUBE
- PMAC_TYPE_EMAC
- PMAC_TYPE_FLAT_PANEL_IMAC
- PMAC_TYPE_FW_IBOOK
- PMAC_TYPE_FW_IMAC
- PMAC_TYPE_GAZELLE
- PMAC_TYPE_GOSSAMER
- PMAC_TYPE_HOOPER
- PMAC_TYPE_IBOOK2
- PMAC_TYPE_IMAC_G5
- PMAC_TYPE_KANGA
- PMAC_TYPE_ORIG_IBOOK
- PMAC_TYPE_ORIG_IMAC
- PMAC_TYPE_PANGEA_IMAC
- PMAC_TYPE_PISMO
- PMAC_TYPE_POWERMAC_G5
- PMAC_TYPE_POWERMAC_G5_U3L
- PMAC_TYPE_PSURGE
- PMAC_TYPE_QUICKSILVER
- PMAC_TYPE_RACKMAC
- PMAC_TYPE_SAWTOOTH
- PMAC_TYPE_SILK
- PMAC_TYPE_TITANIUM
- PMAC_TYPE_TITANIUM2
- PMAC_TYPE_TITANIUM3
- PMAC_TYPE_TITANIUM4
- PMAC_TYPE_UNKNOWN_CORE99
- PMAC_TYPE_UNKNOWN_HEATHROW
- PMAC_TYPE_UNKNOWN_INTREPID
- PMAC_TYPE_UNKNOWN_K2
- PMAC_TYPE_UNKNOWN_OHARE
- PMAC_TYPE_UNKNOWN_PADDINGTON
- PMAC_TYPE_UNKNOWN_PANGEA
- PMAC_TYPE_UNKNOWN_SHASTA
- PMAC_TYPE_WALLSTREET
- PMAC_TYPE_WINDTUNNEL
- PMAC_TYPE_XSERVE_G5
- PMAC_TYPE_YIKES
- PMAC_TYPE_YOSEMITE
- PMAC_XPRAM_MACHINE_LOC
- PMAC_XPRAM_SOUND_VOLUME
- PMADC
- PMADL
- PMADR
- PMAD_ALL
- PMAD_LANCE
- PMAGB_B_BT459
- PMAGB_B_FBMEM
- PMAGB_B_GP0
- PMAGB_B_GP1
- PMAGB_B_ROM
- PMAGB_B_SFB
- PMAGB_B_SIZE
- PMAG_AA_BT431_OFFSET
- PMAG_AA_BT455_OFFSET
- PMAG_AA_ONBOARD_FBMEM_OFFSET
- PMAG_BA_BT438
- PMAG_BA_BT459
- PMAG_BA_FBMEM
- PMAG_BA_IRQ
- PMAG_BA_ROM
- PMAG_BA_SIZE
- PMALERTINTCTL
- PMALERTINTCTL_CLR
- PMALERTINTCTL_EN
- PMALERTINTCTL_MASK
- PMALERTINTCTL_SET
- PMASK
- PMAT0
- PMAT0_BITS
- PMAT1
- PMAT1_BITS
- PMAT_DET
- PMAT_MODE
- PMAT_SAVE_MATCH
- PMAX_LANCE
- PMAX_PROM_AUTOBOOT
- PMAX_PROM_CLOSE
- PMAX_PROM_ENTRY
- PMAX_PROM_GETCHAR
- PMAX_PROM_GETENV
- PMAX_PROM_GETS
- PMAX_PROM_HALT
- PMAX_PROM_LSEEK
- PMAX_PROM_OPEN
- PMAX_PROM_PRINTF
- PMAX_PROM_PUTCHAR
- PMAX_PROM_READ
- PMA_CMN_CTRL1
- PMA_LANE_CFG
- PMA_PMA_LED_ACTIVITY_LBN
- PMA_PMD_10000T_ADV_LBN
- PMA_PMD_10000T_ADV_WIDTH
- PMA_PMD_1000T_ADV_LBN
- PMA_PMD_1000T_ADV_WIDTH
- PMA_PMD_100TX_ADV_LBN
- PMA_PMD_100TX_ADV_WIDTH
- PMA_PMD_EXT_CLK312_WIDTH
- PMA_PMD_EXT_CLK_OUT_LBN
- PMA_PMD_EXT_CLK_OUT_WIDTH
- PMA_PMD_EXT_GMII_EN_LBN
- PMA_PMD_EXT_GMII_EN_WIDTH
- PMA_PMD_EXT_LPOWER_LBN
- PMA_PMD_EXT_LPOWER_WIDTH
- PMA_PMD_EXT_ROBUST_LBN
- PMA_PMD_EXT_ROBUST_WIDTH
- PMA_PMD_EXT_SSR_LBN
- PMA_PMD_EXT_SSR_WIDTH
- PMA_PMD_FTX_CTRL2_REG
- PMA_PMD_FTX_STATIC_LBN
- PMA_PMD_LED_AUTO
- PMA_PMD_LED_CTRL_REG
- PMA_PMD_LED_FLASH
- PMA_PMD_LED_LINK_LBN
- PMA_PMD_LED_MASK
- PMA_PMD_LED_OFF
- PMA_PMD_LED_ON
- PMA_PMD_LED_OVERR_REG
- PMA_PMD_LED_RX_LBN
- PMA_PMD_LED_SPEED_LBN
- PMA_PMD_LED_TX_LBN
- PMA_PMD_LNPGA_POWERDOWN_LBN
- PMA_PMD_LNPGA_POWERDOWN_WIDTH
- PMA_PMD_MODE_REG
- PMA_PMD_RXIN_SEL_LBN
- PMA_PMD_SPEED_ENABLE_REG
- PMA_PMD_SPEED_LBN
- PMA_PMD_SPEED_WIDTH
- PMA_PMD_VEND1_LBTXD_LBN
- PMA_PMD_VEND1_REG
- PMA_PMD_XCONTROL_REG
- PMA_PMD_XSTATUS_REG
- PMA_PMD_XSTAT_FLP_LBN
- PMA_PMD_XSTAT_MDIX_LBN
- PMBA
- PMBASE
- PMBASE_OFFSET
- PMBASE_SIZE
- PMBCTRL
- PMBCTRL_R
- PMBR1
- PMBUS_ATTR_ALLOC_SIZE
- PMBUS_CAPABILITY
- PMBUS_CLEAR_FAULTS
- PMBUS_COEFFICIENTS
- PMBUS_FAN_COMMAND_1
- PMBUS_FAN_COMMAND_2
- PMBUS_FAN_COMMAND_3
- PMBUS_FAN_COMMAND_4
- PMBUS_FAN_CONFIG_12
- PMBUS_FAN_CONFIG_34
- PMBUS_H
- PMBUS_HAVE_FAN12
- PMBUS_HAVE_FAN34
- PMBUS_HAVE_IIN
- PMBUS_HAVE_IOUT
- PMBUS_HAVE_PIN
- PMBUS_HAVE_POUT
- PMBUS_HAVE_PWM12
- PMBUS_HAVE_PWM34
- PMBUS_HAVE_SAMPLES
- PMBUS_HAVE_STATUS_FAN12
- PMBUS_HAVE_STATUS_FAN34
- PMBUS_HAVE_STATUS_INPUT
- PMBUS_HAVE_STATUS_IOUT
- PMBUS_HAVE_STATUS_TEMP
- PMBUS_HAVE_STATUS_VMON
- PMBUS_HAVE_STATUS_VOUT
- PMBUS_HAVE_TEMP
- PMBUS_HAVE_TEMP2
- PMBUS_HAVE_TEMP3
- PMBUS_HAVE_VCAP
- PMBUS_HAVE_VIN
- PMBUS_HAVE_VMON
- PMBUS_HAVE_VOUT
- PMBUS_IIN_OC_FAULT_LIMIT
- PMBUS_IIN_OC_WARN_LIMIT
- PMBUS_IOUT_OC_FAULT_LIMIT
- PMBUS_IOUT_OC_FAULT_RESPONSE
- PMBUS_IOUT_OC_LV_FAULT_LIMIT
- PMBUS_IOUT_OC_LV_FAULT_RESPONSE
- PMBUS_IOUT_OC_WARN_LIMIT
- PMBUS_IOUT_UC_FAULT_LIMIT
- PMBUS_IOUT_UC_FAULT_RESPONSE
- PMBUS_MFR_DATE
- PMBUS_MFR_ID
- PMBUS_MFR_LOCATION
- PMBUS_MFR_MODEL
- PMBUS_MFR_REVISION
- PMBUS_MFR_SERIAL
- PMBUS_NAME_SIZE
- PMBUS_ON_OFF_CONFIG
- PMBUS_OPERATION
- PMBUS_OT_FAULT_LIMIT
- PMBUS_OT_FAULT_RESPONSE
- PMBUS_OT_WARN_LIMIT
- PMBUS_PAGE
- PMBUS_PAGES
- PMBUS_PAGE_VIRTUAL
- PMBUS_PHASE
- PMBUS_PIN_OP_WARN_LIMIT
- PMBUS_POUT_MAX
- PMBUS_POUT_OP_FAULT_LIMIT
- PMBUS_POUT_OP_WARN_LIMIT
- PMBUS_QUERY
- PMBUS_READ_DUTY_CYCLE
- PMBUS_READ_FAN_SPEED_1
- PMBUS_READ_FAN_SPEED_2
- PMBUS_READ_FAN_SPEED_3
- PMBUS_READ_FAN_SPEED_4
- PMBUS_READ_FREQUENCY
- PMBUS_READ_IIN
- PMBUS_READ_IOUT
- PMBUS_READ_PIN
- PMBUS_READ_POUT
- PMBUS_READ_TEMPERATURE_1
- PMBUS_READ_TEMPERATURE_2
- PMBUS_READ_TEMPERATURE_3
- PMBUS_READ_VCAP
- PMBUS_READ_VIN
- PMBUS_READ_VOUT
- PMBUS_REGULATOR
- PMBUS_REVISION
- PMBUS_SKIP_STATUS_CHECK
- PMBUS_STATUS_BYTE
- PMBUS_STATUS_CML
- PMBUS_STATUS_FAN_12
- PMBUS_STATUS_FAN_34
- PMBUS_STATUS_INPUT
- PMBUS_STATUS_IOUT
- PMBUS_STATUS_MFR_SPECIFIC
- PMBUS_STATUS_OTHER
- PMBUS_STATUS_TEMPERATURE
- PMBUS_STATUS_VOUT
- PMBUS_STATUS_WORD
- PMBUS_UT_FAULT_LIMIT
- PMBUS_UT_FAULT_RESPONSE
- PMBUS_UT_WARN_LIMIT
- PMBUS_VIN_OV_FAULT_LIMIT
- PMBUS_VIN_OV_FAULT_RESPONSE
- PMBUS_VIN_OV_WARN_LIMIT
- PMBUS_VIN_UV_FAULT_LIMIT
- PMBUS_VIN_UV_WARN_LIMIT
- PMBUS_VIRT_BASE
- PMBUS_VIRT_CURR_SAMPLES
- PMBUS_VIRT_FAN_TARGET_1
- PMBUS_VIRT_FAN_TARGET_2
- PMBUS_VIRT_FAN_TARGET_3
- PMBUS_VIRT_FAN_TARGET_4
- PMBUS_VIRT_IN_SAMPLES
- PMBUS_VIRT_POWER_SAMPLES
- PMBUS_VIRT_PWM_1
- PMBUS_VIRT_PWM_2
- PMBUS_VIRT_PWM_3
- PMBUS_VIRT_PWM_4
- PMBUS_VIRT_PWM_ENABLE_1
- PMBUS_VIRT_PWM_ENABLE_2
- PMBUS_VIRT_PWM_ENABLE_3
- PMBUS_VIRT_PWM_ENABLE_4
- PMBUS_VIRT_READ_IIN_AVG
- PMBUS_VIRT_READ_IIN_MAX
- PMBUS_VIRT_READ_IIN_MIN
- PMBUS_VIRT_READ_IOUT_AVG
- PMBUS_VIRT_READ_IOUT_MAX
- PMBUS_VIRT_READ_IOUT_MIN
- PMBUS_VIRT_READ_PIN_AVG
- PMBUS_VIRT_READ_PIN_MAX
- PMBUS_VIRT_READ_PIN_MIN
- PMBUS_VIRT_READ_POUT_AVG
- PMBUS_VIRT_READ_POUT_MAX
- PMBUS_VIRT_READ_POUT_MIN
- PMBUS_VIRT_READ_TEMP2_AVG
- PMBUS_VIRT_READ_TEMP2_MAX
- PMBUS_VIRT_READ_TEMP2_MIN
- PMBUS_VIRT_READ_TEMP_AVG
- PMBUS_VIRT_READ_TEMP_MAX
- PMBUS_VIRT_READ_TEMP_MIN
- PMBUS_VIRT_READ_VIN_AVG
- PMBUS_VIRT_READ_VIN_MAX
- PMBUS_VIRT_READ_VIN_MIN
- PMBUS_VIRT_READ_VMON
- PMBUS_VIRT_READ_VOUT_AVG
- PMBUS_VIRT_READ_VOUT_MAX
- PMBUS_VIRT_READ_VOUT_MIN
- PMBUS_VIRT_RESET_IIN_HISTORY
- PMBUS_VIRT_RESET_IOUT_HISTORY
- PMBUS_VIRT_RESET_PIN_HISTORY
- PMBUS_VIRT_RESET_POUT_HISTORY
- PMBUS_VIRT_RESET_TEMP2_HISTORY
- PMBUS_VIRT_RESET_TEMP_HISTORY
- PMBUS_VIRT_RESET_VIN_HISTORY
- PMBUS_VIRT_RESET_VOUT_HISTORY
- PMBUS_VIRT_SAMPLES
- PMBUS_VIRT_STATUS_VMON
- PMBUS_VIRT_TEMP_SAMPLES
- PMBUS_VIRT_VMON_OV_FAULT_LIMIT
- PMBUS_VIRT_VMON_OV_WARN_LIMIT
- PMBUS_VIRT_VMON_UV_FAULT_LIMIT
- PMBUS_VIRT_VMON_UV_WARN_LIMIT
- PMBUS_VOUT_CAL_OFFSET
- PMBUS_VOUT_COMMAND
- PMBUS_VOUT_DROOP
- PMBUS_VOUT_MARGIN_HIGH
- PMBUS_VOUT_MARGIN_LOW
- PMBUS_VOUT_MAX
- PMBUS_VOUT_MODE
- PMBUS_VOUT_OV_FAULT_LIMIT
- PMBUS_VOUT_OV_FAULT_RESPONSE
- PMBUS_VOUT_OV_WARN_LIMIT
- PMBUS_VOUT_SCALE_LOOP
- PMBUS_VOUT_SCALE_MONITOR
- PMBUS_VOUT_TRANSITION_RATE
- PMBUS_VOUT_TRIM
- PMBUS_VOUT_UV_FAULT_LIMIT
- PMBUS_VOUT_UV_FAULT_RESPONSE
- PMBUS_VOUT_UV_WARN_LIMIT
- PMB_ADDR
- PMB_BUS_ID_SHIFT
- PMB_C
- PMB_CACHE_MASK
- PMB_CTRL
- PMB_DATA
- PMB_E_MASK
- PMB_E_SHIFT
- PMB_IRMCR
- PMB_NO_ENTRY
- PMB_PASCR
- PMB_PFN_MASK
- PMB_RD_DATA
- PMB_SZ_128M
- PMB_SZ_16M
- PMB_SZ_512M
- PMB_SZ_64M
- PMB_SZ_MASK
- PMB_TIMEOUT
- PMB_UB
- PMB_V
- PMB_WR_DATA
- PMB_WT
- PMC
- PMC0_CPU1_PMC_ENABLE
- PMC0_CPU1_POWERDOWN
- PMC0_CPU1_WAIT_MTCOMS_ACK
- PMC0_HAS_OVFL
- PMC1
- PMC2
- PMC3
- PMC551_DRAM_BLK0
- PMC551_DRAM_BLK1
- PMC551_DRAM_BLK2
- PMC551_DRAM_BLK3
- PMC551_DRAM_BLK_GET_SIZE
- PMC551_DRAM_BLK_SET_COL_MUX
- PMC551_DRAM_BLK_SET_ROW_MUX
- PMC551_DRAM_CFG
- PMC551_PCI_MEM_MAP0
- PMC551_PCI_MEM_MAP1
- PMC551_PCI_MEM_MAP_APERTURE_MASK
- PMC551_PCI_MEM_MAP_ENABLE
- PMC551_PCI_MEM_MAP_MAP_ADDR_MASK
- PMC551_PCI_MEM_MAP_REG_EN
- PMC551_SDRAM_CMD
- PMC551_SDRAM_MA
- PMC551_SYS_CTRL_REG
- PMC551_VERSION
- PMCAP
- PMCAT_CLR0
- PMCAT_CLR1
- PMCAT_CLR2
- PMCAT_CLR3
- PMCAT_CNN1
- PMCAT_CNN3
- PMCAT_EMU_CLR_MASK
- PMCAT_OVF0
- PMCAT_OVF1
- PMCAT_OVF2
- PMCAT_OVF3
- PMCCFILTR_EL0
- PMCCNTR_EL0
- PMCCR1_ASSERT_PME
- PMCCR1_CURR_STATE
- PMCCR1_NEXT_STATE
- PMCCR1_NEXT_STATE_SHIFT
- PMCCR1_PME_EN
- PMCCR1_POWER_OFF
- PMCCR1_USE_STATE
- PMCCR_DLPEN
- PMCCR_SLPEN
- PMCC_D0_EN
- PMCC_D1_DIS
- PMCC_D1_EN
- PMCC_D2_DIS
- PMCC_D2_EN
- PMCC_D3C_EN
- PMCC_D3H_EN
- PMCC_DSI
- PMCER_ALL
- PMCER_ETSEC1
- PMCER_ETSEC2
- PMCER_GPIO
- PMCER_INT1
- PMCER_INT2
- PMCER_PCI
- PMCER_PMCI
- PMCER_TIMER
- PMCER_USB
- PMCH
- PMCNTENCLR
- PMCNTENSET
- PMCNTENSET_EL0
- PMCNT_RESET
- PMCONV
- PMCR
- PMCRAID_ABORT_CMD
- PMCRAID_ADD_CMD_PARAM_LEN
- PMCRAID_AENWAIT_TIMEOUT
- PMCRAID_AEN_ATTR_EVENT
- PMCRAID_AEN_ATTR_MAX
- PMCRAID_AEN_ATTR_UNSPEC
- PMCRAID_AEN_CMD_EVENT
- PMCRAID_AEN_CMD_MAX
- PMCRAID_AEN_CMD_UNSPEC
- PMCRAID_AEN_GROUP
- PMCRAID_AEN_HDR_SIZE
- PMCRAID_BIST_TIMEOUT
- PMCRAID_CANCEL_ALL_REQUESTS
- PMCRAID_CCN_EXT_SIZE
- PMCRAID_CHECK_FOR_RESET_TIMEOUT
- PMCRAID_DEVFILE
- PMCRAID_DEVICE_ID_LEN
- PMCRAID_DRIVER_ILID
- PMCRAID_DRIVER_IOCTL
- PMCRAID_DRIVER_NAME
- PMCRAID_DRIVER_VERSION
- PMCRAID_ERROR_INTERRUPTS
- PMCRAID_FW_VERSION_1
- PMCRAID_HCAM_CODE_CONFIG_CHANGE
- PMCRAID_HCAM_CODE_LOG_DATA
- PMCRAID_HOSTRCB_LDNSIZE
- PMCRAID_HOST_CONTROLLED_ASYNC
- PMCRAID_IDENTIFY_HRRQ
- PMCRAID_INTERNAL_TIMEOUT
- PMCRAID_INVALID_RES_HANDLE
- PMCRAID_IOADLS_EXTERNAL
- PMCRAID_IOADLS_INTERNAL
- PMCRAID_IOADL_ALIGNMENT
- PMCRAID_IOARCB_ALIGNMENT
- PMCRAID_IOASA_ALIGNMENT
- PMCRAID_IOASC_AC_TERMINATED_BY_HOST
- PMCRAID_IOASC_GC_IOARCB_NOTFOUND
- PMCRAID_IOASC_GOOD_COMPLETION
- PMCRAID_IOASC_HW_CANNOT_COMMUNICATE
- PMCRAID_IOASC_HW_DEVICE_BUS_STATUS_ERROR
- PMCRAID_IOASC_HW_DEVICE_TIMEOUT
- PMCRAID_IOASC_HW_IOA_RESET_REQUIRED
- PMCRAID_IOASC_IOA_WAS_RESET
- PMCRAID_IOASC_IR_INVALID_RESOURCE_HANDLE
- PMCRAID_IOASC_ME_READ_ERROR_NO_REALLOC
- PMCRAID_IOASC_NR_INIT_CMD_REQUIRED
- PMCRAID_IOASC_NR_IOA_RESET_REQUIRED
- PMCRAID_IOASC_NR_SYNC_REQUIRED
- PMCRAID_IOASC_PCI_ACCESS_ERROR
- PMCRAID_IOASC_SENSE_CODE
- PMCRAID_IOASC_SENSE_KEY
- PMCRAID_IOASC_SENSE_MASK
- PMCRAID_IOASC_SENSE_QUAL
- PMCRAID_IOASC_SENSE_STATUS
- PMCRAID_IOASC_TIME_STAMP_OUT_OF_SYNC
- PMCRAID_IOASC_UA_BUS_WAS_RESET
- PMCRAID_IOASC_UA_BUS_WAS_RESET_BY_OTHER
- PMCRAID_IOA_BUS_ID
- PMCRAID_IOA_LUN_ID
- PMCRAID_IOA_MAX_SECTORS
- PMCRAID_IOA_RES_HANDLE
- PMCRAID_IOA_SHUTDOWN
- PMCRAID_IOA_TARGET_ID
- PMCRAID_IOCTL_DOWNLOAD_MICROCODE
- PMCRAID_IOCTL_PASSTHROUGH_COMMAND
- PMCRAID_IOCTL_RESET_ADAPTER
- PMCRAID_IOCTL_SIGNATURE
- PMCRAID_LUN_LEN
- PMCRAID_MAX_ADAPTERS
- PMCRAID_MAX_BUS_TO_SCAN
- PMCRAID_MAX_CDB_LEN
- PMCRAID_MAX_CMD
- PMCRAID_MAX_CMD_PER_LUN
- PMCRAID_MAX_HCAM_CMD
- PMCRAID_MAX_INTERNAL_CMD
- PMCRAID_MAX_IOADLS
- PMCRAID_MAX_IO_CMD
- PMCRAID_MAX_NUM_LUNS_PER_TARGET
- PMCRAID_MAX_NUM_TARGETS_PER_BUS
- PMCRAID_MAX_RESOURCES
- PMCRAID_MAX_VSET_LUNS_PER_TARGET
- PMCRAID_MAX_VSET_TARGETS
- PMCRAID_NUM_MSIX_VECTORS
- PMCRAID_PASSTHROUGH_IOCTL
- PMCRAID_PCI_DEASSERT_TIMEOUT
- PMCRAID_PCI_INTERRUPTS
- PMCRAID_PHYS_BUS_ID
- PMCRAID_PRODUCT_ID_LEN
- PMCRAID_QUERY_CMD_STATUS
- PMCRAID_QUERY_IOA_CONFIG
- PMCRAID_QUERY_RESOURCE_STATE
- PMCRAID_REQUEST_SENSE_TIMEOUT
- PMCRAID_REQ_TM_STR_LEN
- PMCRAID_RESET_ATTEMPTS
- PMCRAID_RESET_BUS_TIMEOUT
- PMCRAID_RESET_DEVICE
- PMCRAID_RESET_HOST_TIMEOUT
- PMCRAID_RESET_TIMEOUT
- PMCRAID_SCSI_SERVICE_ACTION
- PMCRAID_SCSI_SET_TIMESTAMP
- PMCRAID_SENSE_DATA_LEN
- PMCRAID_SERIAL_NUM_LEN
- PMCRAID_SET_SUPPORTED_DEVICES
- PMCRAID_SET_SUP_DEV_TIMEOUT
- PMCRAID_SHUTDOWN_ABBREV
- PMCRAID_SHUTDOWN_NONE
- PMCRAID_SHUTDOWN_NORMAL
- PMCRAID_SHUTDOWN_PREPARE_FOR_NORMAL
- PMCRAID_SHUTDOWN_TIMEOUT
- PMCRAID_SYNC_COMPLETE_AFTER_CANCEL
- PMCRAID_TIMESTAMP_LEN
- PMCRAID_TRANSOP_TIMEOUT
- PMCRAID_VENDOR_ID_LEN
- PMCRAID_VIRTUAL_ENCL_BUS_ID
- PMCRAID_VSET_BUS_ID
- PMCRAID_VSET_IO_TIMEOUT
- PMCRAID_VSET_LUN_ID
- PMCRAID_VSET_MAX_SECTORS
- PMCRAID_WR_BUF_DOWNLOAD_AND_SAVE
- PMCR_BACKOFF_EN
- PMCR_BACKPR_EN
- PMCR_CLKF
- PMCR_EL0
- PMCR_EXT_PHY
- PMCR_FORCE_FDX
- PMCR_FORCE_LNK
- PMCR_FORCE_MODE
- PMCR_FORCE_SPEED_100
- PMCR_FORCE_SPEED_1000
- PMCR_IFG_XMIT
- PMCR_MAC_MODE
- PMCR_PMCLR
- PMCR_PMEN
- PMCR_PMM_MASK
- PMCR_PMST
- PMCR_RX_EN
- PMCR_RX_FC_EN
- PMCR_SF
- PMCR_SPEED_MASK
- PMCR_TX_EN
- PMCR_TX_FC_EN
- PMCSR_SLP
- PMCS_ENMASK
- PMCS_LFDET
- PMCS_LFEN
- PMCS_LRDET
- PMCS_LREN
- PMCS_MFDET
- PMCS_MFEN
- PMCS_STMASK
- PMCS_WF0DET
- PMCS_WF0EN
- PMCS_WF1DET
- PMCS_WF1EN
- PMCS_WF2DET
- PMCS_WF2EN
- PMCS_WF3DET
- PMCS_WF3EN
- PMCS_WF4DET
- PMCS_WF4EN
- PMCS_WF5DET
- PMCS_WF5EN
- PMCS_WF6DET
- PMCS_WF6EN
- PMCS_WF7DET
- PMCS_WF7EN
- PMCTRH
- PMCTRL
- PMCTRL_TXL1_AFTER_L0S
- PMC_ALLOW_MSIX_VECTOR0
- PMC_ALL_INTERRUPT_BITS
- PMC_ALT_PRES_OFFSET
- PMC_ATOM_H
- PMC_BASE_ADDR_DEFAULT
- PMC_BASE_ADDR_MASK
- PMC_BASE_ADDR_OFFSET
- PMC_BIT16
- PMC_BIT32
- PMC_BIT8
- PMC_BLINK_TIMER
- PMC_CFG_NO_REBOOT_DIS
- PMC_CFG_NO_REBOOT_EN
- PMC_CFG_NO_REBOOT_MASK
- PMC_CLK
- PMC_CLK_CTL_FORCE_OFF
- PMC_CLK_CTL_FORCE_ON
- PMC_CLK_CTL_GATED_ON_D3
- PMC_CLK_CTL_OFFSET
- PMC_CLK_CTL_RESERVED
- PMC_CLK_CTL_SIZE
- PMC_CLK_FREQ_PLL
- PMC_CLK_FREQ_XTAL
- PMC_CLK_NUM
- PMC_CLK_OUT_CNTRL
- PMC_CNTRL
- PMC_CNTRL_CPU_PWRREQ_OE
- PMC_CNTRL_CPU_PWRREQ_POLARITY
- PMC_CNTRL_INTR_POLARITY
- PMC_CNTRL_MAIN_RST
- PMC_CNTRL_SIDE_EFFECT_LP0
- PMC_CNTRL_SYSCLK_OE
- PMC_CNTRL_SYSCLK_POLARITY
- PMC_CORE_H
- PMC_CPUPWRGOOD_TIMER
- PMC_CPUPWROFF_TIMER
- PMC_CRITICAL_IOA_OP_IN_PROGRESS
- PMC_CTRL
- PMC_CTRL_BLINK_ENB
- PMC_CTRL_SIDE_EFFECT_LP0
- PMC_D3_STS_0
- PMC_D3_STS_1
- PMC_DEVICE_EVENT_RESET_FAILED
- PMC_DEVICE_EVENT_RESET_START
- PMC_DEVICE_EVENT_RESET_SUCCESS
- PMC_DEVICE_EVENT_SHUTDOWN_FAILED
- PMC_DEVICE_EVENT_SHUTDOWN_START
- PMC_DEVICE_EVENT_SHUTDOWN_SUCCESS
- PMC_DEVICE_S6
- PMC_DEVICE_S7
- PMC_DEVICE_S8
- PMC_DEVNAME
- PMC_DFL_VAL
- PMC_DPD_PADS_ORIDE
- PMC_DPD_PADS_ORIDE_BLINK_ENB
- PMC_Def
- PMC_FAILURE
- PMC_FSM
- PMC_FUNC_DIS
- PMC_FUNC_DIS_2
- PMC_GCR_PMC_CFG_REG
- PMC_GCR_TELEM_DEEP_S0IX_REG
- PMC_GCR_TELEM_SHLW_S0IX_REG
- PMC_GLOBAL_INT_BIT0
- PMC_GLOBAL_INT_BIT2
- PMC_HOST_RRQ_VALID
- PMC_I2S0_MUX
- PMC_I2S1_MUX
- PMC_IDLE_ON
- PMC_IDLE_REG
- PMC_IMPL_E_33V_PWR
- PMC_INDEX
- PMC_INIT
- PMC_IOARCB_TRANSFER_FAILED
- PMC_IOARRIN_LOST
- PMC_IOA_ERROR_INTERRUPTS
- PMC_IOA_PROCESSOR_IN_ERROR_STATE
- PMC_IOA_UNIT_CHECK
- PMC_IO_DPD_REQ
- PMC_IO_DPD_STATUS
- PMC_IPC_NORTHPEAK_CTRL
- PMC_IPC_PHY_CONFIG
- PMC_IPC_PMC_FW_MSG_CTRL
- PMC_IPC_PMC_TELEMTRY
- PMC_IPC_PMIC_ACCESS
- PMC_IPC_PMIC_ACCESS_READ
- PMC_IPC_PMIC_ACCESS_WRITE
- PMC_IPC_PMIC_BLACKLIST_SEL
- PMC_IPC_PM_DEBUG
- PMC_IPC_USB_PWR_CTRL
- PMC_IRQ_CAUSE
- PMC_IRQ_MASK
- PMC_IS_CONTROL
- PMC_IS_COUNTING
- PMC_IS_IMPL
- PMC_IS_LAST
- PMC_IS_MONITOR
- PMC_MAIN
- PMC_MASK_CLK_CTL
- PMC_MASK_CLK_FREQ
- PMC_MAX_IDS
- PMC_MAX_PCKS
- PMC_MCK
- PMC_MCK2
- PMC_MMIO_REG_LEN
- PMC_Mask
- PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE
- PMC_NO_INDEX
- PMC_OBPNAME
- PMC_OPERATIONAL_STATUS
- PMC_OVFL_NOTIFY
- PMC_PLLM_WB0_OVERRIDE
- PMC_PLLM_WB0_OVERRIDE_2
- PMC_PLLP_WB0_OVERRIDE
- PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE
- PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE
- PMC_PLL_ACR
- PMC_PLL_ACR_DEFAULT
- PMC_PLL_ACR_LOOP_FILTER_MSK
- PMC_PLL_ACR_UTMIBG
- PMC_PLL_ACR_UTMIVR
- PMC_PLL_CTRL0
- PMC_PLL_CTRL0_DIV_MSK
- PMC_PLL_CTRL0_ENLOCK
- PMC_PLL_CTRL0_ENPLL
- PMC_PLL_CTRL0_ENPLLCK
- PMC_PLL_CTRL1
- PMC_PLL_CTRL1_FRACR_MSK
- PMC_PLL_CTRL1_MUL_MSK
- PMC_PLL_ISR0
- PMC_PLL_UPDT
- PMC_PLL_UPDT_UPDATE
- PMC_PM
- PMC_PMBM_BUSY
- PMC_PMBM_READ
- PMC_PMBM_SLAVE_ERR
- PMC_PMBM_START
- PMC_PMBM_TIMEOUT
- PMC_PMBM_WRITE
- PMC_PMD_DEP
- PMC_PRES_OFFSET
- PMC_PSS
- PMC_PSS_BIT_CHT_DFX_CLUSTER1
- PMC_PSS_BIT_CHT_DFX_CLUSTER2
- PMC_PSS_BIT_CHT_DFX_CLUSTER3
- PMC_PSS_BIT_CHT_DFX_CLUSTER4
- PMC_PSS_BIT_CHT_DFX_CLUSTER5
- PMC_PSS_BIT_CHT_DFX_MASTER
- PMC_PSS_BIT_CHT_GMM
- PMC_PSS_BIT_CHT_ISH
- PMC_PSS_BIT_CHT_UFS
- PMC_PSS_BIT_CHT_USB_SUS
- PMC_PSS_BIT_CHT_UXD
- PMC_PSS_BIT_CHT_UXD_FD
- PMC_PSS_BIT_CHT_UX_ENG
- PMC_PSS_BIT_DFX
- PMC_PSS_BIT_GBE
- PMC_PSS_BIT_HDA
- PMC_PSS_BIT_LPE
- PMC_PSS_BIT_LPSS
- PMC_PSS_BIT_OTG_CTRL
- PMC_PSS_BIT_OTG_VCCA
- PMC_PSS_BIT_OTG_VCCA_CLK
- PMC_PSS_BIT_OTG_VCCS
- PMC_PSS_BIT_PCIE
- PMC_PSS_BIT_SATA
- PMC_PSS_BIT_SEC
- PMC_PSS_BIT_USB
- PMC_PSS_BIT_USB_SUS
- PMC_PSS_BIT_USH_CTRL
- PMC_PSS_BIT_USH_SUS
- PMC_PSS_BIT_USH_VCCA
- PMC_PSS_BIT_USH_VCCS
- PMC_PWR_DET
- PMC_PWR_DET_VALUE
- PMC_Print
- PMC_REG_BASE
- PMC_REG_BIT_WIDTH
- PMC_RELEASE
- PMC_RESERVED
- PMC_RST_STATUS_AOTAG
- PMC_RST_STATUS_LP0
- PMC_RST_STATUS_POR
- PMC_RST_STATUS_SENSOR
- PMC_RST_STATUS_SW_MAIN
- PMC_RST_STATUS_WATCHDOG
- PMC_RSVD_MASK
- PMC_Read
- PMC_S0I1_TMR
- PMC_S0I2_TMR
- PMC_S0I3_TMR
- PMC_S0IR_TMR
- PMC_S0IX_WAKE_EN
- PMC_S0_TMR
- PMC_SATA_PWRGT
- PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL
- PMC_SATA_PWRGT_PLLE_IDDQ_VALUE
- PMC_SCRATCH0_MODE_BOOTLOADER
- PMC_SCRATCH0_MODE_MASK
- PMC_SCRATCH0_MODE_RCM
- PMC_SCRATCH0_MODE_RECOVERY
- PMC_SCRATCH37
- PMC_SCRATCH38
- PMC_SCRATCH39
- PMC_SCRATCH41
- PMC_SCRATCH54
- PMC_SCRATCH54_ADDR_SHIFT
- PMC_SCRATCH54_DATA_SHIFT
- PMC_SCRATCH55
- PMC_SCRATCH55_16BITOP
- PMC_SCRATCH55_CHECKSUM_SHIFT
- PMC_SCRATCH55_CNTRL_ID_SHIFT
- PMC_SCRATCH55_I2CSLV1_SHIFT
- PMC_SCRATCH55_PINMUX_SHIFT
- PMC_SCRATCH55_RESET_TEGRA
- PMC_SENSOR_CTRL
- PMC_SENSOR_CTRL_ENABLE_RST
- PMC_SENSOR_CTRL_SCRATCH_WRITE
- PMC_SLOW
- PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG
- PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT
- PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT
- PMC_SW_RST
- PMC_SYSTEM_BUS_MMIO_ERROR
- PMC_TMR_SHIFT
- PMC_TRANSITION_TO_OPERATIONAL
- PMC_TYPE_CORE
- PMC_TYPE_GCK
- PMC_TYPE_PERIPHERAL
- PMC_TYPE_SYSTEM
- PMC_UTMI
- PMC_Val
- PMC_WAKE_EN_SETTING
- PMC_Write
- PMConfig
- PMConfigBits
- PMControl
- PMD0_MERR_MASK
- PMD1_MERR_MASK
- PMD2_MERR_MASK
- PMD3_MERR_MASK
- PMD9635_SUBTYPE
- PMDAC
- PMDATA
- PMDATA_ADDR
- PMDA_ALL
- PMDCSR
- PMDCSR_VAL
- PMDECODE
- PMDIR
- PMDIR_ADDR
- PMDR
- PMDS
- PMDS_PER_MID_PAGE
- PMD_ALIGN
- PMD_APTABLE
- PMD_APTABLE_SHIFT
- PMD_ATTRINDX
- PMD_ATTRINDX_MASK
- PMD_BAD_BITS
- PMD_BIT4
- PMD_BITS
- PMD_BIT_FUNC
- PMD_CACHE_INDEX
- PMD_DOMAIN
- PMD_DOMAIN_MASK
- PMD_ENTRY_SIZE
- PMD_FLAGS
- PMD_FLAGS_DEC
- PMD_FLAGS_DEC_WP
- PMD_FLAGS_ENC
- PMD_FLAGS_LARGE
- PMD_FLAGS_SMP
- PMD_FLAGS_UP
- PMD_FRAG_NR
- PMD_FRAG_SIZE
- PMD_FRAG_SIZE_SHIFT
- PMD_HYP
- PMD_INDEX
- PMD_INDEX_SIZE
- PMD_IS_COUNTING
- PMD_IS_IMPL
- PMD_IS_LAST
- PMD_LEVEL_MULT
- PMD_MASK
- PMD_MASKED_BITS
- PMD_MAYBE_NG
- PMD_ORDER
- PMD_PAGE_MASK
- PMD_PAGE_SIZE
- PMD_PMD_DEP
- PMD_PRESENT
- PMD_PROTECTION
- PMD_PWR_MW_REG
- PMD_PWR_REG
- PMD_PXNTABLE
- PMD_RCV_SIGDET_GLOBAL
- PMD_RCV_SIGDET_LANE0
- PMD_RCV_SIGDET_LANE1
- PMD_RCV_SIGDET_LANE2
- PMD_RCV_SIGDET_LANE3
- PMD_S2_RDONLY
- PMD_S2_RDWR
- PMD_S2_XN
- PMD_SECT_AF
- PMD_SECT_AP1
- PMD_SECT_AP2
- PMD_SECT_APX
- PMD_SECT_AP_READ
- PMD_SECT_AP_WRITE
- PMD_SECT_BUFFERABLE
- PMD_SECT_BUFFERED
- PMD_SECT_CACHEABLE
- PMD_SECT_CACHE_MASK
- PMD_SECT_CONT
- PMD_SECT_EXEC
- PMD_SECT_MINICACHE
- PMD_SECT_NG
- PMD_SECT_NONSHARED_DEV
- PMD_SECT_PXN
- PMD_SECT_RDONLY
- PMD_SECT_READ
- PMD_SECT_S
- PMD_SECT_SUPER
- PMD_SECT_TEX
- PMD_SECT_UNCACHED
- PMD_SECT_USER
- PMD_SECT_UXN
- PMD_SECT_VALID
- PMD_SECT_WB
- PMD_SECT_WBWA
- PMD_SECT_WRITE
- PMD_SECT_WT
- PMD_SECT_XN
- PMD_SECT_nG
- PMD_SHIFT
- PMD_SIZE
- PMD_SK_CONN
- PMD_SK_PMD
- PMD_TABLE_BIT
- PMD_TABLE_SIZE
- PMD_TYPE_FAULT
- PMD_TYPE_INVALID
- PMD_TYPE_MASK
- PMD_TYPE_SECT
- PMD_TYPE_TABLE
- PMD_T_LOG2
- PMD_VAL_BITS
- PMD_YOUNG
- PME
- PMECC_CFG_AUTO_ENABLE
- PMECC_CFG_BCH_STRENGTH
- PMECC_CFG_BCH_STRENGTH_MASK
- PMECC_CFG_NSECTORS
- PMECC_CFG_READ_OP
- PMECC_CFG_SECTOR1024
- PMECC_CFG_SECTOR512
- PMECC_CFG_SPARE_ENABLE
- PMECC_CFG_WRITE_OP
- PMECC_CLK_133MHZ
- PMECC_CTRL_DATA
- PMECC_CTRL_DISABLE
- PMECC_CTRL_ENABLE
- PMECC_CTRL_RST
- PMECC_CTRL_USER
- PMECC_ERROR_INT
- PMECC_GF_13_PRIMITIVE_POLY
- PMECC_GF_14_PRIMITIVE_POLY
- PMECC_GF_DIMENSION_13
- PMECC_GF_DIMENSION_14
- PMECC_LOOKUP_TABLE_SIZE_1024
- PMECC_LOOKUP_TABLE_SIZE_512
- PMECC_MAX_TIMEOUT_MS
- PMECC_SR_BUSY
- PMECC_SR_ENABLE
- PMECR_AUTO_WAKE_EN
- PMECR_PME_DELAY
- PMECR_PME_POL
- PMECR_PM_ENERGY
- PMECR_PM_MASK
- PMECR_PM_NORMAL
- PMECR_PM_POWERSAVE
- PMECR_PM_SHIFT
- PMECR_PM_SOFTDOWN
- PMECR_WAKEUP_NORMAL
- PMECR_WKEVT_ENERGY
- PMECR_WKEVT_FRAME
- PMECR_WKEVT_GET
- PMECR_WKEVT_LINK
- PMECR_WKEVT_MAGICPKT
- PMECR_WKEVT_MASK
- PMECR_WKEVT_SHIFT
- PMECR_WOL_ENERGY
- PMECR_WOL_LINKUP
- PMECR_WOL_MAGICPKT
- PMECR_WOL_WAKEUP
- PMEEnable
- PMEGS_NUM
- PMEG_MASK
- PMEM_A_CLK
- PMEM_CLK
- PMEM_RESET
- PMEN0
- PMEN1
- PMEN2
- PMEN3
- PMERRLOC_CALC_DONE
- PMERRLOC_DISABLE
- PMERRLOC_ELCFG_NUM_ERRORS
- PMERRLOC_ELCFG_SECTOR_1024
- PMERRLOC_ELCFG_SECTOR_512
- PMERRLOC_ELSR_BUSY
- PMERRLOC_ERR_NUM_MASK
- PMESP
- PMESTS
- PMEStatus
- PMEVCNTR0_EL0
- PMEVCNTR30_EL0
- PMEVTYPER0_EL0
- PMEVTYPER30_EL0
- PMEVTYPER_CASES
- PMEVTYPER_READ_CASE
- PMEVTYPER_WRITE_CASE
- PMEXECUTE
- PME_ACK_TIMEOUT
- PME_D0
- PME_D1
- PME_D2
- PME_D3C
- PME_D3H
- PME_DEBUG_0
- PME_DISR_EN_ENL23D
- PME_DISR_EN_EXL23D
- PME_DISR_EN_PTOD
- PME_EN
- PME_ENABLE
- PME_ENABLE_PF_BITMAP
- PME_FORCE_CTL
- PME_INTR_CIR_PASS_BIT
- PME_OVR
- PME_POLARITY
- PME_SIGNAL
- PME_STATUS_PF_BITMAP
- PME_TIMEOUT
- PME_TO_ACK
- PME_TURN_OFF
- PME_WAKEUP_ENABLE
- PME_WOL_ENERGY
- PME_WOL_LINKUP
- PME_WOL_MAGICPKT
- PMEnable
- PMFLUSHDONE_LNEBLK
- PMFLUSHDONE_LNICRSDROP
- PMFLUSH_GAPL3UNBLOCK
- PMFUSES_AVFSSIZE
- PMF_CMD_COUNT
- PMF_CMD_DELAY
- PMF_CMD_GEN_I2C
- PMF_CMD_LIST
- PMF_CMD_MASK_AND_COMPARE
- PMF_CMD_READ_CFG
- PMF_CMD_READ_GPIO
- PMF_CMD_READ_I2C
- PMF_CMD_READ_I2C_SUBADDR
- PMF_CMD_READ_REG16
- PMF_CMD_READ_REG16_MASK_SHR_XOR
- PMF_CMD_READ_REG32
- PMF_CMD_READ_REG32_MASK_SHR_XOR
- PMF_CMD_READ_REG8
- PMF_CMD_READ_REG8_MASK_SHR_XOR
- PMF_CMD_RMW_CFG
- PMF_CMD_RMW_I2C
- PMF_CMD_RMW_I2C_SUBADDR
- PMF_CMD_SET_I2C_MODE
- PMF_CMD_SHIFT_BYTES_LEFT
- PMF_CMD_SHIFT_BYTES_RIGHT
- PMF_CMD_WAIT_REG16
- PMF_CMD_WAIT_REG32
- PMF_CMD_WAIT_REG8
- PMF_CMD_WRITE_CFG
- PMF_CMD_WRITE_GPIO
- PMF_CMD_WRITE_I2C
- PMF_CMD_WRITE_I2C_SUBADDR
- PMF_CMD_WRITE_REG16
- PMF_CMD_WRITE_REG16_SHL_MASK
- PMF_CMD_WRITE_REG32
- PMF_CMD_WRITE_REG32_SHL_MASK
- PMF_CMD_WRITE_REG8
- PMF_CMD_WRITE_REG8_SHL_MASK
- PMF_DMAE_C
- PMF_FLAGS_HIGH_SPEED
- PMF_FLAGS_INT_GEN
- PMF_FLAGS_LOW_SPEED
- PMF_FLAGS_ON_DEMAND
- PMF_FLAGS_ON_INIT
- PMF_FLAGS_ON_SLEEP
- PMF_FLAGS_ON_WAKE
- PMF_FLAGS_SIDE_EFFECTS
- PMF_FLGAS_ON_TERM
- PMF_GPIO
- PMF_PARSE_CALL
- PMF_STD_ARGS
- PMGC0_FAC
- PMGC0_FCECE
- PMGC0_PMIE
- PMGSL_PARAMS
- PMG_PWRSTATE
- PMHL
- PMHP
- PMHPL
- PMHPR
- PMHP_MASK
- PMI8962_SUBTYPE
- PMI8994_SUBTYPE
- PMI8998_SUBTYPE
- PMIC
- PMIC4_BOB_MODE_AUTO
- PMIC4_BOB_MODE_PASS
- PMIC4_BOB_MODE_PFM
- PMIC4_BOB_MODE_PWM
- PMIC4_LDO_MODE_HPM
- PMIC4_LDO_MODE_LPM
- PMIC4_LDO_MODE_RETENTION
- PMIC4_SMPS_MODE_AUTO
- PMIC4_SMPS_MODE_PFM
- PMIC4_SMPS_MODE_PWM
- PMIC4_SMPS_MODE_RETENTION
- PMIC5_BOB_MODE_AUTO
- PMIC5_BOB_MODE_PASS
- PMIC5_BOB_MODE_PFM
- PMIC5_BOB_MODE_PWM
- PMIC5_CHG_TEMP_SCALE_FACTOR
- PMIC5_LDO_MODE_HPM
- PMIC5_LDO_MODE_LPM
- PMIC5_LDO_MODE_RETENTION
- PMIC5_SMB_TEMP_CONSTANT
- PMIC5_SMB_TEMP_SCALE_FACTOR
- PMIC5_SMPS_MODE_AUTO
- PMIC5_SMPS_MODE_PFM
- PMIC5_SMPS_MODE_PWM
- PMIC5_SMPS_MODE_RETENTION
- PMIC_A0LOCK_REG
- PMIC_ARB0_H_CLK
- PMIC_ARB0_RESET
- PMIC_ARB1_H_CLK
- PMIC_ARB1_RESET
- PMIC_ARB_APID_MASK
- PMIC_ARB_APID_VALID
- PMIC_ARB_CHANNEL_OBS
- PMIC_ARB_CHANNEL_RW
- PMIC_ARB_CHAN_IS_IRQ_OWNER
- PMIC_ARB_CMD
- PMIC_ARB_CMD_MAX_BYTE_COUNT
- PMIC_ARB_CONFIG
- PMIC_ARB_INT_EN
- PMIC_ARB_MAX_PERIPHS
- PMIC_ARB_MAX_PPID
- PMIC_ARB_MAX_TRANS_BYTES
- PMIC_ARB_OP_AUTHENTICATE
- PMIC_ARB_OP_EXT_READ
- PMIC_ARB_OP_EXT_READL
- PMIC_ARB_OP_EXT_WRITE
- PMIC_ARB_OP_EXT_WRITEL
- PMIC_ARB_OP_MSTR_READ
- PMIC_ARB_OP_MSTR_WRITE
- PMIC_ARB_OP_READ
- PMIC_ARB_OP_RESET
- PMIC_ARB_OP_SHUTDOWN
- PMIC_ARB_OP_SLEEP
- PMIC_ARB_OP_WAKEUP
- PMIC_ARB_OP_WRITE
- PMIC_ARB_OP_ZERO_WRITE
- PMIC_ARB_PPID_MASK
- PMIC_ARB_RDATA0
- PMIC_ARB_RDATA1
- PMIC_ARB_STATUS
- PMIC_ARB_STATUS_DENIED
- PMIC_ARB_STATUS_DONE
- PMIC_ARB_STATUS_DROPPED
- PMIC_ARB_STATUS_FAILURE
- PMIC_ARB_TIMEOUT_US
- PMIC_ARB_VERSION
- PMIC_ARB_VERSION_V2_MIN
- PMIC_ARB_VERSION_V3_MIN
- PMIC_ARB_VERSION_V5_MIN
- PMIC_ARB_WDATA0
- PMIC_ARB_WDATA1
- PMIC_CHIP_ID_DA9063
- PMIC_CLK_EN
- PMIC_DA9063_AD
- PMIC_DA9063_BB
- PMIC_DA9063_CA
- PMIC_ENABLE_TIME_US
- PMIC_GPIO_ADDRESS_RANGE
- PMIC_GPIO_CONF_ANALOG_PASS
- PMIC_GPIO_CONF_ATEST
- PMIC_GPIO_CONF_DTEST_BUFFER
- PMIC_GPIO_CONF_PULL_UP
- PMIC_GPIO_CONF_STRENGTH
- PMIC_GPIO_DIG_IN_DTEST_SEL_MASK
- PMIC_GPIO_FUNC_DTEST1
- PMIC_GPIO_FUNC_DTEST2
- PMIC_GPIO_FUNC_DTEST3
- PMIC_GPIO_FUNC_DTEST4
- PMIC_GPIO_FUNC_FUNC1
- PMIC_GPIO_FUNC_FUNC2
- PMIC_GPIO_FUNC_FUNC3
- PMIC_GPIO_FUNC_FUNC4
- PMIC_GPIO_FUNC_INDEX_DTEST1
- PMIC_GPIO_FUNC_INDEX_DTEST2
- PMIC_GPIO_FUNC_INDEX_DTEST3
- PMIC_GPIO_FUNC_INDEX_DTEST4
- PMIC_GPIO_FUNC_INDEX_FUNC1
- PMIC_GPIO_FUNC_INDEX_FUNC2
- PMIC_GPIO_FUNC_INDEX_FUNC3
- PMIC_GPIO_FUNC_INDEX_FUNC4
- PMIC_GPIO_FUNC_INDEX_NORMAL
- PMIC_GPIO_FUNC_INDEX_PAIRED
- PMIC_GPIO_FUNC_NORMAL
- PMIC_GPIO_FUNC_PAIRED
- PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK
- PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN
- PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK
- PMIC_GPIO_LV_MV_OUTPUT_INVERT
- PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT
- PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK
- PMIC_GPIO_MODE_ANALOG_PASS_THRU
- PMIC_GPIO_MODE_DIGITAL_INPUT
- PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT
- PMIC_GPIO_MODE_DIGITAL_OUTPUT
- PMIC_GPIO_OUT_BUF_CMOS
- PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS
- PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS
- PMIC_GPIO_PHYSICAL_OFFSET
- PMIC_GPIO_PULL_DISABLE
- PMIC_GPIO_PULL_DOWN
- PMIC_GPIO_PULL_UP_1P5
- PMIC_GPIO_PULL_UP_1P5_30
- PMIC_GPIO_PULL_UP_30
- PMIC_GPIO_PULL_UP_31P5
- PMIC_GPIO_REG_DIG_IN_CTL
- PMIC_GPIO_REG_DIG_OUT_CTL
- PMIC_GPIO_REG_DIG_PULL_CTL
- PMIC_GPIO_REG_DIG_VIN_CTL
- PMIC_GPIO_REG_EN_CTL
- PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL
- PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL
- PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK
- PMIC_GPIO_REG_MASTER_EN_SHIFT
- PMIC_GPIO_REG_MODE_CTL
- PMIC_GPIO_REG_MODE_DIR_MASK
- PMIC_GPIO_REG_MODE_DIR_SHIFT
- PMIC_GPIO_REG_MODE_FUNCTION_MASK
- PMIC_GPIO_REG_MODE_FUNCTION_SHIFT
- PMIC_GPIO_REG_MODE_VALUE_SHIFT
- PMIC_GPIO_REG_OUT_STRENGTH_MASK
- PMIC_GPIO_REG_OUT_STRENGTH_SHIFT
- PMIC_GPIO_REG_OUT_TYPE_MASK
- PMIC_GPIO_REG_OUT_TYPE_SHIFT
- PMIC_GPIO_REG_PULL_MASK
- PMIC_GPIO_REG_PULL_SHIFT
- PMIC_GPIO_REG_SUBTYPE
- PMIC_GPIO_REG_TYPE
- PMIC_GPIO_REG_VIN_MASK
- PMIC_GPIO_REG_VIN_SHIFT
- PMIC_GPIO_STRENGTH_HIGH
- PMIC_GPIO_STRENGTH_LOW
- PMIC_GPIO_STRENGTH_MED
- PMIC_GPIO_STRENGTH_NO
- PMIC_GPIO_SUBTYPE_GPIOC_4CH
- PMIC_GPIO_SUBTYPE_GPIOC_8CH
- PMIC_GPIO_SUBTYPE_GPIO_4CH
- PMIC_GPIO_SUBTYPE_GPIO_8CH
- PMIC_GPIO_SUBTYPE_GPIO_LV
- PMIC_GPIO_SUBTYPE_GPIO_MV
- PMIC_GPIO_TYPE
- PMIC_INT
- PMIC_INT1
- PMIC_INT2
- PMIC_INT3
- PMIC_INT4
- PMIC_INT_GPIO83
- PMIC_MAX_REGISTER_ADDRESS
- PMIC_MODULE_EN
- PMIC_MPP_ADDRESS_RANGE
- PMIC_MPP_AMUX_ROUTE_ABUS1
- PMIC_MPP_AMUX_ROUTE_ABUS2
- PMIC_MPP_AMUX_ROUTE_ABUS3
- PMIC_MPP_AMUX_ROUTE_ABUS4
- PMIC_MPP_AMUX_ROUTE_CH5
- PMIC_MPP_AMUX_ROUTE_CH6
- PMIC_MPP_AMUX_ROUTE_CH7
- PMIC_MPP_AMUX_ROUTE_CH8
- PMIC_MPP_ANALOG
- PMIC_MPP_AOUT_LVL_0V3125
- PMIC_MPP_AOUT_LVL_0V625
- PMIC_MPP_AOUT_LVL_1V25
- PMIC_MPP_AOUT_LVL_1V25_2
- PMIC_MPP_AOUT_LVL_ABUS1
- PMIC_MPP_AOUT_LVL_ABUS2
- PMIC_MPP_AOUT_LVL_ABUS3
- PMIC_MPP_AOUT_LVL_MPP
- PMIC_MPP_CONF_AMUX_ROUTE
- PMIC_MPP_CONF_ANALOG_LEVEL
- PMIC_MPP_CONF_DTEST_SELECTOR
- PMIC_MPP_CONF_PAIRED
- PMIC_MPP_DIGITAL
- PMIC_MPP_FUNC_DTEST1
- PMIC_MPP_FUNC_DTEST2
- PMIC_MPP_FUNC_DTEST3
- PMIC_MPP_FUNC_DTEST4
- PMIC_MPP_FUNC_NORMAL
- PMIC_MPP_FUNC_PAIRED
- PMIC_MPP_MODE_ANALOG_BIDIR
- PMIC_MPP_MODE_ANALOG_INPUT
- PMIC_MPP_MODE_ANALOG_OUTPUT
- PMIC_MPP_MODE_CURRENT_SINK
- PMIC_MPP_MODE_DIGITAL_BIDIR
- PMIC_MPP_MODE_DIGITAL_INPUT
- PMIC_MPP_MODE_DIGITAL_OUTPUT
- PMIC_MPP_PHYSICAL_OFFSET
- PMIC_MPP_PULL_UP_0P6KOHM
- PMIC_MPP_PULL_UP_10KOHM
- PMIC_MPP_PULL_UP_30KOHM
- PMIC_MPP_PULL_UP_OPEN
- PMIC_MPP_REG_AIN_CTL
- PMIC_MPP_REG_AIN_ROUTE_MASK
- PMIC_MPP_REG_AIN_ROUTE_SHIFT
- PMIC_MPP_REG_AOUT_CTL
- PMIC_MPP_REG_DIG_IN_CTL
- PMIC_MPP_REG_DIG_PULL_CTL
- PMIC_MPP_REG_DIG_VIN_CTL
- PMIC_MPP_REG_EN_CTL
- PMIC_MPP_REG_MASTER_EN_SHIFT
- PMIC_MPP_REG_MODE_CTL
- PMIC_MPP_REG_MODE_DIR_MASK
- PMIC_MPP_REG_MODE_DIR_SHIFT
- PMIC_MPP_REG_MODE_FUNCTION_MASK
- PMIC_MPP_REG_MODE_FUNCTION_SHIFT
- PMIC_MPP_REG_MODE_VALUE_MASK
- PMIC_MPP_REG_PULL_MASK
- PMIC_MPP_REG_PULL_SHIFT
- PMIC_MPP_REG_RT_STS
- PMIC_MPP_REG_RT_STS_VAL_MASK
- PMIC_MPP_REG_SINK_CTL
- PMIC_MPP_REG_SUBTYPE
- PMIC_MPP_REG_TYPE
- PMIC_MPP_REG_VIN_MASK
- PMIC_MPP_REG_VIN_SHIFT
- PMIC_MPP_SELECTOR_DTEST_FIRST
- PMIC_MPP_SELECTOR_NORMAL
- PMIC_MPP_SELECTOR_PAIRED
- PMIC_MPP_SINK
- PMIC_MPP_SUBTYPE_4CH_FULL_FUNC
- PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT
- PMIC_MPP_SUBTYPE_4CH_NO_SINK
- PMIC_MPP_SUBTYPE_8CH_FULL_FUNC
- PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT
- PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK
- PMIC_MPP_TYPE
- PMIC_MT6323
- PMIC_MT6351
- PMIC_MT6357
- PMIC_MT6358
- PMIC_MT6380
- PMIC_MT6397
- PMIC_PMIC_INT
- PMIC_POWER_OPREGION_ID
- PMIC_REGS_OPREGION_ID
- PMIC_REUMSE
- PMIC_REV2
- PMIC_REV3
- PMIC_REV4
- PMIC_RST_STATUS
- PMIC_SHUTDOWN
- PMIC_SSBI2_CLK
- PMIC_SSBI2_RESET
- PMIC_SSBI2_SRC
- PMIC_SUBTYPE
- PMIC_TEMP
- PMIC_THERMAL_OPREGION_ID
- PMIC_TYPE
- PMIC_TYPE_DA9063
- PMIC_TYPE_DA9063L
- PMIC_TYPE_VALUE
- PMIC_WDT_DEFAULT_TIMEOUT
- PMIC_WDT_MAX_TIMEOUT
- PMIC_WDT_MIN_TIMEOUT
- PMIC_WD_BARK_STS_BIT
- PMII_ADMIN_t
- PMINSTR
- PMINTENCLR
- PMINTENSET
- PMINTENSET_EL1
- PMIR
- PMIRQONMSBEN
- PMI_ACK
- PMI_ADDRESS_WIDTH
- PMI_CAP_ID
- PMI_CAP_LIST__CAP_ID_MASK
- PMI_CAP_LIST__CAP_ID__MASK
- PMI_CAP_LIST__CAP_ID__SHIFT
- PMI_CAP_LIST__NEXT_PTR_MASK
- PMI_CAP_LIST__NEXT_PTR__MASK
- PMI_CAP_LIST__NEXT_PTR__SHIFT
- PMI_CAP__AUX_CURRENT_MASK
- PMI_CAP__AUX_CURRENT__MASK
- PMI_CAP__AUX_CURRENT__SHIFT
- PMI_CAP__D1_SUPPORT_MASK
- PMI_CAP__D1_SUPPORT__MASK
- PMI_CAP__D1_SUPPORT__SHIFT
- PMI_CAP__D2_SUPPORT_MASK
- PMI_CAP__D2_SUPPORT__MASK
- PMI_CAP__D2_SUPPORT__SHIFT
- PMI_CAP__DEV_SPECIFIC_INIT_MASK
- PMI_CAP__DEV_SPECIFIC_INIT__MASK
- PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
- PMI_CAP__PME_CLOCK_MASK
- PMI_CAP__PME_CLOCK__MASK
- PMI_CAP__PME_CLOCK__SHIFT
- PMI_CAP__PME_SUPPORT_MASK
- PMI_CAP__PME_SUPPORT__MASK
- PMI_CAP__PME_SUPPORT__SHIFT
- PMI_CAP__VERSION_MASK
- PMI_CAP__VERSION__MASK
- PMI_CAP__VERSION__SHIFT
- PMI_CHG_SCALE_1
- PMI_CHG_SCALE_2
- PMI_DATA
- PMI_NXT_CAP_PTR
- PMI_PMC_REG
- PMI_PMSCR_REG
- PMI_READ_DATA0
- PMI_READ_DATA1
- PMI_READ_DATA2
- PMI_READ_TYPE
- PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
- PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK
- PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
- PMI_STATUS_CNTL__BUS_PWR_EN_MASK
- PMI_STATUS_CNTL__BUS_PWR_EN__MASK
- PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
- PMI_STATUS_CNTL__DATA_SCALE_MASK
- PMI_STATUS_CNTL__DATA_SCALE__MASK
- PMI_STATUS_CNTL__DATA_SCALE__SHIFT
- PMI_STATUS_CNTL__DATA_SELECT_MASK
- PMI_STATUS_CNTL__DATA_SELECT__MASK
- PMI_STATUS_CNTL__DATA_SELECT__SHIFT
- PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
- PMI_STATUS_CNTL__NO_SOFT_RESET__MASK
- PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
- PMI_STATUS_CNTL__PME_EN_MASK
- PMI_STATUS_CNTL__PME_EN__MASK
- PMI_STATUS_CNTL__PME_EN__SHIFT
- PMI_STATUS_CNTL__PME_STATUS_MASK
- PMI_STATUS_CNTL__PME_STATUS__MASK
- PMI_STATUS_CNTL__PME_STATUS__SHIFT
- PMI_STATUS_CNTL__PMI_DATA_MASK
- PMI_STATUS_CNTL__PMI_DATA__MASK
- PMI_STATUS_CNTL__PMI_DATA__SHIFT
- PMI_STATUS_CNTL__POWER_STATE_MASK
- PMI_STATUS_CNTL__POWER_STATE__MASK
- PMI_STATUS_CNTL__POWER_STATE__SHIFT
- PMI_TIMEOUT
- PMI_TYPE_FREQ_CHANGE
- PMI_TYPE_POWER_BUTTON
- PMI_WRITE_DATA0
- PMI_WRITE_DATA1
- PMI_WRITE_DATA2
- PMI_WRITE_TYPE
- PMJCTL
- PMKID_DISABLE
- PMKID_ENABLE
- PMKID_FOUND
- PMK_LIST_MAX
- PMK_MAX_LEN
- PMLCA_CE
- PMLCA_EVENT_MASK
- PMLCA_EVENT_SHIFT
- PMLCA_FC
- PMLCA_FCM0
- PMLCA_FCM1
- PMLCA_FCS
- PMLCA_FCU
- PMLCA_FGCS0
- PMLCA_FGCS1
- PMLCB_THRESHMUL_MASK
- PMLCB_THRESHMUL_SHIFT
- PMLCB_THRESHOLD_MASK
- PMLCB_THRESHOLD_SHIFT
- PML_ADDRESS
- PML_ADDRESS_HIGH
- PML_ENTITY_NUM
- PMMIN
- PMMISC
- PMMOVEM
- PMMP
- PMM_1T_RESET_REG_P0
- PMM_1T_RESET_REG_P1
- PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK
- PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT
- PMM_GENERAL_CNTL__PMM_DISABLE_MASK
- PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT
- PMM_GENERAL_CNTL__PMM_MODE_MASK
- PMM_GENERAL_CNTL__PMM_MODE__SHIFT
- PMM_GLOBAL_MODE
- PMM_NPS_MODE
- PMM_PERPORT_MODE
- PMM_REG_ACC_PATH
- PMM_REG_CTL
- PMNC_FIFOAV
- PMNC_POL
- PMNORM
- PMOD_BYPASS
- PMOD_DATAMODEM
- PMOD_DISABLE
- PMOD_DTMF
- PMOD_DTMF_TRANS
- PMOD_FAX
- PMOD_HALFDUPLEX
- PMOD_V110
- PMOPHI
- PMOPLO
- PMOP_END
- PMOP_START
- PMOS0_ACTIVE_BITS
- PMOS0_ENABLE
- PMOS0_EN_OVERCURRENT_DEBOUNCE
- PMOS0_OVERCURRENT_LEVEL_2_4V
- PMOS0_SW_LED_POLARITY_ENABLE
- PMOS1_ACTIVE_BITS
- PMOS_SEL
- PMOS_STRG_400mA
- PMOS_STRG_800mA
- PMOS_STRG_MASK
- PMOVEM
- PMOVSRCLR
- PMOVSRCLR_RESET
- PMOVSSET_EL0
- PMP
- PMPLL
- PMPT_CONTEXT
- PMPUEN
- PMPUEN_ADDR
- PMP_GSCR_SII_POL
- PMQH_ATIMFAIL
- PMQH_BSSCFG
- PMQH_DASAT
- PMQH_DATA_MASK
- PMQH_DEL_ENTRY
- PMQH_DEL_MULT
- PMQH_NOT_EMPTY
- PMQH_OFLO
- PMQH_PMOFF
- PMQH_PMON
- PMR
- PMREGISTER
- PMRESRn_EN
- PMRN_PMC0
- PMRN_PMC1
- PMRN_PMC2
- PMRN_PMC3
- PMRN_PMC4
- PMRN_PMC5
- PMRN_PMGC0
- PMRN_PMLCA0
- PMRN_PMLCA1
- PMRN_PMLCA2
- PMRN_PMLCA3
- PMRN_PMLCA4
- PMRN_PMLCA5
- PMRN_PMLCB0
- PMRN_PMLCB1
- PMRN_PMLCB2
- PMRN_PMLCB3
- PMRN_PMLCB4
- PMRN_PMLCB5
- PMRN_UPMC0
- PMRN_UPMC1
- PMRN_UPMC2
- PMRN_UPMC3
- PMRN_UPMC4
- PMRN_UPMC5
- PMRN_UPMGC0
- PMRN_UPMLCA0
- PMRN_UPMLCA1
- PMRN_UPMLCA2
- PMRN_UPMLCA3
- PMRN_UPMLCA4
- PMRN_UPMLCA5
- PMRN_UPMLCB0
- PMRN_UPMLCB1
- PMRN_UPMLCB2
- PMRN_UPMLCB3
- PMRN_UPMLCB4
- PMRN_UPMLCB5
- PMRXMAXPAGE_G
- PMRXMAXPAGE_M
- PMRXMAXPAGE_S
- PMRXNUMCHN_F
- PMRXNUMCHN_S
- PMRXNUMCHN_V
- PMRX_E_PCMD_PAR_ERROR_F
- PMRX_E_PCMD_PAR_ERROR_S
- PMRX_E_PCMD_PAR_ERROR_V
- PMRX_FRAMING_ERROR_F
- PMRX_INTR_MASK
- PMR_ACTIVE
- PMR_ADDR
- PMR_B0
- PMR_B1
- PMR_B2
- PMR_B3
- PMR_B4
- PMR_BANK
- PMR_HARDSTOP
- PMR_RD_CMD
- PMR_SOFTSTOP
- PMR_SOFTSTOPFAULT
- PMR_WR_CMD
- PMS7003_CHAN
- PMS7003_CHECKSUM_LENGTH
- PMS7003_CMD_LENGTH
- PMS7003_DRIVER_NAME
- PMS7003_MAGIC
- PMS7003_MAX_DATA_LENGTH
- PMS7003_PM10_OFFSET
- PMS7003_PM1_OFFSET
- PMS7003_PM2P5_OFFSET
- PMS7003_PM_MAX
- PMS7003_PM_MIN
- PMS7003_TIMEOUT
- PMSAv7_ACR_SHARED
- PMSAv7_ACR_XN
- PMSAv7_AP_PL1RO_PL0NA
- PMSAv7_AP_PL1RW_PL0NA
- PMSAv7_AP_PL1RW_PL0R0
- PMSAv7_AP_PL1RW_PL0RW
- PMSAv7_BG_REGION
- PMSAv7_DATA_SIDE
- PMSAv7_INSTR_SIDE
- PMSAv7_MIN_SUBREG_SIZE
- PMSAv7_NR_SUBREGS
- PMSAv7_PROBE_REGION
- PMSAv7_RAM_REGION
- PMSAv7_RASR
- PMSAv7_RBAR
- PMSAv7_RGN_CACHEABLE
- PMSAv7_RGN_NORMAL
- PMSAv7_RGN_SHARED_CACHEABLE
- PMSAv7_RGN_STRONGLY_ORDERED
- PMSAv7_RNR
- PMSAv7_ROM_REGION
- PMSAv7_RSR_ALL_MEM
- PMSAv7_RSR_EN
- PMSAv7_RSR_SD
- PMSAv7_RSR_SZ
- PMSAv8_AP_PL1RO_PL0RO
- PMSAv8_AP_PL1RW_PL0NA
- PMSAv8_AP_PL1RW_PL0RW
- PMSAv8_BAR_XN
- PMSAv8_KERNEL_REGION
- PMSAv8_LAR_EN
- PMSAv8_LAR_IDX
- PMSAv8_MAIR
- PMSAv8_MAIR0
- PMSAv8_MAIR1
- PMSAv8_MINALIGN
- PMSAv8_RBAR
- PMSAv8_RBAR_A
- PMSAv8_RGN_DEVICE_nGnRnE
- PMSAv8_RGN_NORMAL
- PMSAv8_RGN_SHARED
- PMSAv8_RLAR
- PMSAv8_RLAR_A
- PMSAv8_RNR
- PMSAv8_XIP_REGION
- PMSEL
- PMSELR_EL0
- PMSEL_ADDR
- PMSG_AUTO_RESUME
- PMSG_AUTO_SUSPEND
- PMSG_FREEZE
- PMSG_HIBERNATE
- PMSG_INVALID
- PMSG_IS_AUTO
- PMSG_NAME
- PMSG_ON
- PMSG_QUIESCE
- PMSG_RECOVER
- PMSG_REMOTE_RESUME
- PMSG_RESTORE
- PMSG_RESUME
- PMSG_SUSPEND
- PMSG_THAW
- PMSG_USER_RESUME
- PMSG_USER_SUSPEND
- PMSR
- PMSR_DPX
- PMSR_EEE100M
- PMSR_EEE1G
- PMSR_LINK
- PMSR_PSAFE_ENABLE
- PMSR_RX_FC
- PMSR_SPEED_10
- PMSR_SPEED_100
- PMSR_SPEED_1000
- PMSR_SPEED_MASK
- PMSR_SPR_EM_DISABLE
- PMSR_TX_FC
- PMSTATR
- PMSU_BASE_OFFSET
- PMSU_BOOT_ADDR_REDIRECT_OFFSET
- PMSU_CONTROL_AND_CONFIG
- PMSU_CONTROL_AND_CONFIG_DFS_REQ
- PMSU_CONTROL_AND_CONFIG_L2_PWDDN
- PMSU_CONTROL_AND_CONFIG_PWDDN_REQ
- PMSU_CPU_POWER_DOWN_CONTROL
- PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP
- PMSU_DFLT_ARMADA38X_DELAY
- PMSU_EVENT_STATUS_AND_MASK
- PMSU_EVENT_STATUS_AND_MASK_DFS_DONE
- PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK
- PMSU_POWERDOWN_DELAY
- PMSU_POWERDOWN_DELAY_MASK
- PMSU_POWERDOWN_DELAY_PMU
- PMSU_PREPARE_DEEP_IDLE
- PMSU_PREPARE_NORMAL
- PMSU_PREPARE_SNOOP_DISABLE
- PMSU_REG_SIZE
- PMSU_STATUS_AND_MASK
- PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT
- PMSU_STATUS_AND_MASK_DBG_WAKEUP
- PMSU_STATUS_AND_MASK_FIQ_MASK
- PMSU_STATUS_AND_MASK_FIQ_WAKEUP
- PMSU_STATUS_AND_MASK_IRQ_MASK
- PMSU_STATUS_AND_MASK_IRQ_WAKEUP
- PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT
- PMSWINC_EL0
- PMS_BAR
- PMS_DEF_PRIO
- PMS_FIFONO_MASK
- PMS_FIFONO_MDP
- PMS_FIFONO_MEP
- PMS_FIFONO_SHIFT
- PMS_IS_MEP
- PMS_MSGTYPE_DATA
- PMS_RETRY_SHIFT
- PMS_TELID_MASK
- PMS_TELID_SHIFT
- PMS_TELID_UNSEGM_MAMAC
- PMTMR_EXPECTED_RATE
- PMTMR_TICKS_PER_SEC
- PMTXMAXPAGE_G
- PMTXMAXPAGE_M
- PMTXMAXPAGE_S
- PMTXNUMCHN_G
- PMTXNUMCHN_M
- PMTXNUMCHN_S
- PMTX_C_PCMD_PAR_ERROR_F
- PMTX_C_PCMD_PAR_ERROR_S
- PMTX_C_PCMD_PAR_ERROR_V
- PMTX_FRAMING_ERROR_F
- PMTX_INTR_MASK
- PMT_CTL
- PMT_CTL_DEV_RDY
- PMT_CTL_ED_EN
- PMT_CTL_EEE_WAKEUP_EN_
- PMT_CTL_EEE_WUPS_
- PMT_CTL_ETH_PHY_D3_COLD_OVR_
- PMT_CTL_ETH_PHY_D3_OVR_
- PMT_CTL_ETH_PHY_EDPD_PLL_CTL_
- PMT_CTL_ETH_PHY_RST_
- PMT_CTL_ETH_PHY_WAKE_EN_
- PMT_CTL_GPIO_WAKEUP_EN_
- PMT_CTL_MAC_D3_RX_CLK_OVR_
- PMT_CTL_MAC_SRST_
- PMT_CTL_PHY_PWRUP
- PMT_CTL_PHY_PWRUP_
- PMT_CTL_PHY_RST
- PMT_CTL_PHY_RST_
- PMT_CTL_PHY_WAKE_EN_
- PMT_CTL_READY_
- PMT_CTL_RES_CLR_WKP_EN
- PMT_CTL_RES_CLR_WKP_EN_
- PMT_CTL_RES_CLR_WKP_MASK_
- PMT_CTL_RES_CLR_WKP_STS_
- PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_
- PMT_CTL_SUS_MODE
- PMT_CTL_SUS_MODE_0
- PMT_CTL_SUS_MODE_0_
- PMT_CTL_SUS_MODE_1
- PMT_CTL_SUS_MODE_1_
- PMT_CTL_SUS_MODE_2
- PMT_CTL_SUS_MODE_2_
- PMT_CTL_SUS_MODE_3
- PMT_CTL_SUS_MODE_3_
- PMT_CTL_SUS_MODE_MASK_
- PMT_CTL_WOL_EN
- PMT_CTL_WOL_EN_
- PMT_CTL_WUPS
- PMT_CTL_WUPS_ED
- PMT_CTL_WUPS_MAC_
- PMT_CTL_WUPS_MASK_
- PMT_CTL_WUPS_MLT_
- PMT_CTL_WUPS_MULTI
- PMT_CTL_WUPS_NO
- PMT_CTL_WUPS_PHY_
- PMT_CTL_WUPS_WOL
- PMT_CTRL
- PMT_CTRL_ED_EN_
- PMT_CTRL_PHY_RST_
- PMT_CTRL_PME_EN_
- PMT_CTRL_PME_IND_
- PMT_CTRL_PME_POL_
- PMT_CTRL_PME_TYPE_
- PMT_CTRL_PM_MODE_
- PMT_CTRL_PM_MODE_D0_
- PMT_CTRL_PM_MODE_D1_
- PMT_CTRL_PM_MODE_D2_
- PMT_CTRL_PM_MODE_D3_
- PMT_CTRL_READY_
- PMT_CTRL_WOL_EN_
- PMT_CTRL_WUPS_
- PMT_CTRL_WUPS_ED_
- PMT_CTRL_WUPS_MULTI_
- PMT_CTRL_WUPS_NOWAKE_
- PMT_CTRL_WUPS_WOL_
- PMT_NOT_SUPPORTED
- PMT_SUPPORTED
- PMU0_CFG
- PMU1_CFG
- PMU1_CKE
- PMU1_PCIE1_CTL
- PMU1_PCIE1_MSI
- PMU1_PCIE1_PDI
- PMU1_PCIE2_CTL
- PMU1_PCIE2_MSI
- PMU1_PCIE2_PDI
- PMU1_PCIE_CTL
- PMU1_PCIE_MSI
- PMU1_PCIE_PDI
- PMU1_PCIE_PHY
- PMUCNT2REG
- PMUL64
- PMULL_MIN_LEN
- PMUNAME
- PMUNIMPL
- PMURES_BIT
- PMUSERENR_EL0
- PMUXCR_ELBCDIU_DIU
- PMUXCR_ELBCDIU_MASK
- PMUXCR_ELBCDIU_NOR16
- PMU_68K_V1
- PMU_68K_V2
- PMU_A12_0_PD_EN
- PMU_ADB_CMD
- PMU_ADB_POLL_OFF
- PMU_AHBM
- PMU_AHBS
- PMU_ALIVE_USE_LF
- PMU_ANALOG_DCDC_1V0
- PMU_ANALOG_DCDC_1VX
- PMU_ANALOG_DCDC_2V5
- PMU_ANALOG_DSL_AFE
- PMU_ANALOG_PCIE0_P
- PMU_ANALOG_PCIE1_P
- PMU_ANALOG_PCIE2_P
- PMU_ANALOG_USB0_P
- PMU_ANALOG_USB1_P
- PMU_ANA_CR_A
- PMU_ANA_CR_B
- PMU_ANA_SR
- PMU_ARMINT_WAKEUP_EN
- PMU_ASC0
- PMU_ASC1
- PMU_ASE_SDIO
- PMU_BACKLIGHT_BRIGHT
- PMU_BATTERY_STATE
- PMU_BATT_CHARGING
- PMU_BATT_PRESENT
- PMU_BATT_TYPE_COMET
- PMU_BATT_TYPE_HOOPER
- PMU_BATT_TYPE_MASK
- PMU_BATT_TYPE_SMART
- PMU_BUS_PD_EN
- PMU_CACHED
- PMU_CHIP_PD_EN
- PMU_CLK_CORE_SRC_GATE_EN
- PMU_CLK_CR1_A
- PMU_CLK_CR1_B
- PMU_CLK_CR_A
- PMU_CLK_CR_B
- PMU_CLK_SR
- PMU_CLK_SR1
- PMU_CLR_ALIVE
- PMU_CLR_BUS
- PMU_CLR_CORE
- PMU_CLR_CPUP
- PMU_CLR_DMA
- PMU_CLR_GPU
- PMU_CLR_HEVC
- PMU_CLR_PERI
- PMU_CLR_VIDEO
- PMU_CLR_VIO
- PMU_CNT_MAX_PERIOD
- PMU_CPU_SPEED
- PMU_CTRL_LCDNDIF
- PMU_CTRL_OFFSET
- PMU_DDR0IO_RET_DE_REQ
- PMU_DDR0IO_RET_EN
- PMU_DDR0_GATING_EN
- PMU_DDR1IO_RET_DE_REQ
- PMU_DDR1IO_RET_EN
- PMU_DDR1_GATING_EN
- PMU_DEU
- PMU_DFE
- PMU_DFS_RATIO_MASK
- PMU_DFS_RATIO_SHIFT
- PMU_DMA
- PMU_DRIVER_VERSION
- PMU_EBU
- PMU_ENV_LID_CLOSED
- PMU_EPHY
- PMU_EVENTS_H
- PMU_EVENT_ATTR
- PMU_EVENT_ATTR_STRING
- PMU_EVENT_GROUP
- PMU_EVENT_SYMBOL
- PMU_EVENT_SYMBOL_ERR
- PMU_EVENT_SYMBOL_PREFIX
- PMU_EVENT_SYMBOL_SUFFIX
- PMU_EVT_LID
- PMU_EVT_POWER
- PMU_FIRST_COUNTER
- PMU_FIXED_NR_BITS
- PMU_FIXED_NR_MASK
- PMU_FIXED_NR_SHIFT
- PMU_FL_EXCL_CNTRS
- PMU_FL_EXCL_ENABLED
- PMU_FL_HAS_RSP_1
- PMU_FL_NO_HT_SHARING
- PMU_FL_PAIR
- PMU_FL_PEBS_ALL
- PMU_FL_TFA
- PMU_FORMAT_ATTR
- PMU_FPI
- PMU_FSM_REG
- PMU_F_ENABLED
- PMU_F_ERR_IBE
- PMU_F_ERR_LSDA
- PMU_F_ERR_MASK
- PMU_F_IN_USE
- PMU_F_RESERVED
- PMU_GENERAL_NR_BITS
- PMU_GENERAL_NR_MASK
- PMU_GENERAL_NR_SHIFT
- PMU_GET_BRIGHTBUTTON
- PMU_GET_COVER
- PMU_GET_VERSION
- PMU_GET_VOLBUTTON
- PMU_GLOBAL_INT_DISABLE
- PMU_GPHY
- PMU_GPIOINT_WAKEUP_EN
- PMU_GPT
- PMU_HDMI_PHY_CONTROL
- PMU_HDMI_PHY_ENABLE_BIT
- PMU_HEATHROW_BASED
- PMU_I2C_BUS_POWER
- PMU_I2C_BUS_STATUS
- PMU_I2C_BUS_SYSCLK
- PMU_I2C_CMD
- PMU_I2C_MODE_COMBINED
- PMU_I2C_MODE_SIMPLE
- PMU_I2C_MODE_STDSUB
- PMU_I2C_STATUS_BUSY
- PMU_I2C_STATUS_DATAREAD
- PMU_I2C_STATUS_OK
- PMU_INPUT_CLAMP_EN
- PMU_INTERRUPT_CAUSE
- PMU_INT_ACK
- PMU_INT_ADB
- PMU_INT_ADB_AUTO
- PMU_INT_AUTO_SRQ_POLL
- PMU_INT_BATTERY
- PMU_INT_ENVIRONMENT
- PMU_INT_PCEJECT
- PMU_INT_SNDBRT
- PMU_INT_TICK
- PMU_INT_WAITING_CHARGER
- PMU_IOC_CAN_SLEEP
- PMU_IOC_CAN_SLEEP32
- PMU_IOC_GET_BACKLIGHT
- PMU_IOC_GET_BACKLIGHT32
- PMU_IOC_GET_MODEL
- PMU_IOC_GET_MODEL32
- PMU_IOC_GRAB_BACKLIGHT
- PMU_IOC_GRAB_BACKLIGHT32
- PMU_IOC_HAS_ADB
- PMU_IOC_HAS_ADB32
- PMU_IOC_SET_BACKLIGHT
- PMU_IOC_SET_BACKLIGHT32
- PMU_IOC_SLEEP
- PMU_ISO
- PMU_ISO_GPU_MASK
- PMU_ISO_VIDEO_MASK
- PMU_KEYLARGO_BASED
- PMU_L2FLUSH_EN
- PMU_MAX_BATTERIES
- PMU_MAX_COUNTERS
- PMU_MAX_PMCS
- PMU_MAX_PMDS
- PMU_MAX_TRANSITION_DLY
- PMU_MEM_MAP
- PMU_MINOR
- PMU_MPP_GENERAL_CTRL
- PMU_NAME_SIZE
- PMU_NR_COUNTERS
- PMU_OHARE_BASED
- PMU_OSC_24M_DIS
- PMU_OVERFLOW_MASK
- PMU_PACKET
- PMU_PADDINGTON_BASED
- PMU_PCEJECT
- PMU_PCI
- PMU_PCIE_CLK
- PMU_PLL_PD_EN
- PMU_PMAMR0
- PMU_PMAMR1
- PMU_PMCNTENCLR
- PMU_PMCNTENSET
- PMU_PMCR
- PMU_PMCR_E
- PMU_PMCR_P
- PMU_PMC_OI
- PMU_PMEVCNTR
- PMU_PMEVCNTR0
- PMU_PMEVCNTR1
- PMU_PMEVCNTR2
- PMU_PMEVCNTR3
- PMU_PMEVCNTR_EL0
- PMU_PMEVTYPER
- PMU_PMEVTYPER0
- PMU_PMEVTYPER1
- PMU_PMEVTYPER2
- PMU_PMEVTYPER3
- PMU_PMEVTYPER_EL0
- PMU_PMINTENCLR
- PMU_PMINTENSET
- PMU_PMOVSCLR
- PMU_PMOVSR
- PMU_PMOVSSET
- PMU_PMU_USE_LF
- PMU_POW0_HARD_DRIVE
- PMU_POW0_OFF
- PMU_POW0_ON
- PMU_POWER_CTRL
- PMU_POWER_CTRL0
- PMU_POWER_EVENTS
- PMU_POW_BACKLIGHT
- PMU_POW_CHARGER
- PMU_POW_IRLED
- PMU_POW_MEDIABAY
- PMU_POW_OFF
- PMU_POW_ON
- PMU_PPE
- PMU_PPE_DP
- PMU_PPE_DPLUM
- PMU_PPE_DPLUS
- PMU_PPE_EMA
- PMU_PPE_QSB
- PMU_PPE_SLL01
- PMU_PPE_TC
- PMU_PPE_TOP
- PMU_PROBE
- PMU_PWDCR
- PMU_PWDCR1
- PMU_PWDSR
- PMU_PWDSR1
- PMU_PWR
- PMU_PWRDN_CON
- PMU_PWRDN_SCU
- PMU_PWRDN_ST
- PMU_PWROFF_COMB
- PMU_PWR_AC_PRESENT
- PMU_PWR_CLR_POWERUP_EVENTS
- PMU_PWR_CLR_WAKEUP_EVENTS
- PMU_PWR_GET_POWERUP_EVENTS
- PMU_PWR_GET_WAKEUP_EVENTS
- PMU_PWR_GPU_PWR_DWN_MASK
- PMU_PWR_MODE_EN
- PMU_PWR_SET_POWERUP_EVENTS
- PMU_PWR_SET_WAKEUP_EVENTS
- PMU_PWR_VPU_PWR_DWN_MASK
- PMU_PWR_WAKEUP_AC_CHANGE
- PMU_PWR_WAKEUP_AC_INSERT
- PMU_PWR_WAKEUP_KEY
- PMU_PWR_WAKEUP_LID_OPEN
- PMU_PWR_WAKEUP_RING
- PMU_RCTL_LOGIC_DISABLE_MASK
- PMU_RCTL_MACPHY_DISABLE_MASK
- PMU_READY_DELAY_MS
- PMU_READ_NVRAM
- PMU_READ_RTC
- PMU_READ_XPRAM
- PMU_REGS_OFFS
- PMU_RESET
- PMU_RES_DEP_ADD
- PMU_RES_DEP_REMOVE
- PMU_RES_DEP_SET
- PMU_RETPROBE_FILE
- PMU_SAMPLE_PV
- PMU_SAMPLE_REAL
- PMU_SAMPLE_USER
- PMU_SCU_EN
- PMU_SDIO
- PMU_SET_INTR_MASK
- PMU_SET_RTC
- PMU_SET_VOLBUTTON
- PMU_SHUTDOWN
- PMU_SIGNAL_SELECT_0
- PMU_SIGNAL_SELECT_1
- PMU_SLEEP
- PMU_SLOW_CLK_PERIOD
- PMU_SMART_BATTERY_STATE
- PMU_SPI
- PMU_SREF0_ENTER_EN
- PMU_SREF1_ENTER_EN
- PMU_STP
- PMU_SWITCH
- PMU_SW_RST_GPU_MASK
- PMU_SW_RST_VIDEO_MASK
- PMU_SW_SET
- PMU_SYSTEM_READY
- PMU_TABLE_END
- PMU_TDC0_AVG_NUM_MASK
- PMU_TDC0_AVG_NUM_OFFS
- PMU_TDC0_OTF_CAL_MASK
- PMU_TDC0_REF_CAL_CNT_MASK
- PMU_TDC0_REF_CAL_CNT_OFFS
- PMU_TDC0_SEL_VCAL_MASK
- PMU_TDC0_SEL_VCAL_OFFS
- PMU_TDC0_START_CAL_MASK
- PMU_TDC0_SW_RST_MASK
- PMU_TDC1_TEMP_VALID_MASK
- PMU_TEMP_DIOD_CTRL1_REG
- PMU_TM_DISABLE_MASK
- PMU_TM_DISABLE_OFFS
- PMU_TYPE1_BASE
- PMU_TYPE1_SIZE
- PMU_TYPE2_BASE
- PMU_TYPE2_SIZE
- PMU_TYPE_COUNTER
- PMU_TYPE_DMC
- PMU_TYPE_EVNTSEL
- PMU_TYPE_FILE
- PMU_TYPE_INVALID
- PMU_TYPE_IOB
- PMU_TYPE_IOB_SLOW
- PMU_TYPE_L3C
- PMU_TYPE_MC
- PMU_TYPE_MCB
- PMU_UNKNOWN
- PMU_USB0
- PMU_USB0_P
- PMU_USB1
- PMU_USB1_P
- PMU_USIF
- PMU_V3_CNT_MAX_PERIOD
- PMU_VER_END
- PMU_VER_START
- PMU_WAKEUP_RESET_EN
- PMU_WRITE_NVRAM
- PMU_WRITE_XPRAM
- PMU_XTALFREQ_REG_ILPCTR_MASK
- PMU_XTALFREQ_REG_MEASURE_MASK
- PMU_XTALFREQ_REG_MEASURE_SHIFT
- PMU_XTAL_FREQ_RATIO
- PMVCM
- PMVER
- PMVR
- PMX2_SOFTRESET_3D_RST
- PMX2_SOFTRESET_ALL
- PMX2_SOFTRESET_C1_RST
- PMX2_SOFTRESET_C2_RST
- PMX2_SOFTRESET_DAC_RST
- PMX2_SOFTRESET_REG_RST
- PMX2_SOFTRESET_ROM_RST
- PMX2_SOFTRESET_SD_RST
- PMX2_SOFTRESET_TA_RST
- PMX2_SOFTRESET_TLB_RST
- PMX2_SOFTRESET_VGA_RST
- PMX2_SOFTRESET_VIDIN_RST
- PMX_CAN0_PL_32_33_VAL
- PMX_CAN1_PL_30_31_VAL
- PMX_CLCD1_MASK
- PMX_CLCD2_MASK
- PMX_CLCD_PL_69_VAL
- PMX_CLCD_PL_70_VAL
- PMX_CLCD_PL_71_72_VAL
- PMX_CLCD_PL_73_VAL
- PMX_CLCD_PL_74_VAL
- PMX_CLCD_PL_75_76_VAL
- PMX_CLCD_PL_77_78_79_VAL
- PMX_CLCD_PL_80_TO_85_VAL
- PMX_CLCD_PL_86_87_VAL
- PMX_CLCD_PL_88_89_VAL
- PMX_CLCD_PL_90_91_VAL
- PMX_CLCD_PL_92_93_VAL
- PMX_CLCD_PL_94_95_VAL
- PMX_CLCD_PL_96_97_VAL
- PMX_CLCD_PL_98_VAL
- PMX_CONFIG_REG
- PMX_DATA
- PMX_EGPIO00_MASK
- PMX_EGPIO01_MASK
- PMX_EGPIO02_MASK
- PMX_EGPIO03_MASK
- PMX_EGPIO04_MASK
- PMX_EGPIO05_MASK
- PMX_EGPIO06_MASK
- PMX_EGPIO07_MASK
- PMX_EGPIO08_MASK
- PMX_EGPIO09_MASK
- PMX_EGPIO10_MASK
- PMX_EGPIO11_MASK
- PMX_EGPIO12_MASK
- PMX_EGPIO13_MASK
- PMX_EGPIO14_MASK
- PMX_EGPIO15_MASK
- PMX_EGPIO_0_GRP_MASK
- PMX_EGPIO_1_GRP_MASK
- PMX_EMI1_PL_90_91_VAL
- PMX_EMI1_PL_92_93_VAL
- PMX_EMI1_PL_94_95_VAL
- PMX_EMI1_PL_96_97_VAL
- PMX_EMI_PL_50_51_VAL
- PMX_EMI_PL_52_53_VAL
- PMX_EMI_PL_69_VAL
- PMX_EMI_PL_74_VAL
- PMX_EMI_PL_75_76_VAL
- PMX_EMI_PL_77_78_79_VAL
- PMX_EMI_PL_80_TO_85_VAL
- PMX_EMI_PL_86_87_VAL
- PMX_EMI_PL_88_89_VAL
- PMX_FIRDA_MASK
- PMX_FSMC_EMI_PL_46_47_VAL
- PMX_FSMC_EMI_PL_48_49_VAL
- PMX_FSMC_EMI_PL_54_55_56_VAL
- PMX_FSMC_EMI_PL_58_59_VAL
- PMX_FSMC_EMI_PL_70_VAL
- PMX_FSMC_EMI_PL_71_72_VAL
- PMX_FSMC_EMI_PL_73_VAL
- PMX_FSMC_PL_52_53_VAL
- PMX_FSMC_PL_57_VAL
- PMX_FSMC_PL_60_VAL
- PMX_FSMC_PL_61_TO_64_VAL
- PMX_FSMC_PL_65_TO_68_VAL
- PMX_FUNC
- PMX_GMIICLK_MASK
- PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK
- PMX_GMIID47_MASK
- PMX_GMII_MASK
- PMX_GPIO_PIN0_MASK
- PMX_GPIO_PIN1_MASK
- PMX_GPIO_PIN2_MASK
- PMX_GPIO_PIN3_MASK
- PMX_GPIO_PIN4_MASK
- PMX_GPIO_PIN5_MASK
- PMX_GPT0_TMR0_MASK
- PMX_GPT0_TMR1_MASK
- PMX_GPT1_TMR0_MASK
- PMX_GPT1_TMR1_MASK
- PMX_I2C0_MASK
- PMX_I2C1_PL_8_9_VAL
- PMX_I2C1_PL_98_VAL
- PMX_I2C1_PL_99_VAL
- PMX_I2C1_PORT_8_9_VAL
- PMX_I2C1_PORT_98_99_VAL
- PMX_I2C1_PORT_SEL_MASK
- PMX_I2C2_PL_0_1_VAL
- PMX_I2C2_PL_19_VAL
- PMX_I2C2_PL_20_VAL
- PMX_I2C2_PL_2_3_VAL
- PMX_I2C2_PL_75_76_VAL
- PMX_I2C2_PL_96_97_VAL
- PMX_I2C2_PORT_0_1_VAL
- PMX_I2C2_PORT_19_20_VAL
- PMX_I2C2_PORT_2_3_VAL
- PMX_I2C2_PORT_75_76_VAL
- PMX_I2C2_PORT_96_97_VAL
- PMX_I2C2_PORT_SEL_MASK
- PMX_I2C_MASK
- PMX_I2S0_MASK
- PMX_I2S1_MASK
- PMX_I2S_PL_39_VAL
- PMX_I2S_PL_40_VAL
- PMX_I2S_PL_41_42_VAL
- PMX_I2S_REF_CLK_PL_35_VAL
- PMX_KBD_COL0_MASK
- PMX_KBD_COL1_MASK
- PMX_KBD_ROW0_MASK
- PMX_KBD_ROW1_MASK
- PMX_KBD_ROWCOL25_MASK
- PMX_KBD_ROWCOL68_MASK
- PMX_KEYBOARD_6X6_MASK
- PMX_MCIADDR0ALE_MASK
- PMX_MCIADDR1CLECLK_MASK
- PMX_MCIADDR2_MASK
- PMX_MCICDCF1_MASK
- PMX_MCICDCF2_MASK
- PMX_MCICDSDMMC_MASK
- PMX_MCICDXD_MASK
- PMX_MCICECF_MASK
- PMX_MCICESDMMC_MASK
- PMX_MCICEXD_MASK
- PMX_MCICFINTR_MASK
- PMX_MCICS0CE_MASK
- PMX_MCICS1_MASK
- PMX_MCIDATA0_MASK
- PMX_MCIDATA1SD_MASK
- PMX_MCIDATA1_MASK
- PMX_MCIDATA2SD_MASK
- PMX_MCIDATA2_MASK
- PMX_MCIDATA3SD_MASK
- PMX_MCIDATA3_MASK
- PMX_MCIDATA4_MASK
- PMX_MCIDATA5_MASK
- PMX_MCIDATA6_MASK
- PMX_MCIDATA7_MASK
- PMX_MCIDATADIR_MASK
- PMX_MCIDMAACK_MASK
- PMX_MCIDMARQWP_MASK
- PMX_MCIFALL_1_MASK
- PMX_MCIFALL_2_MASK
- PMX_MCIIORDRE_MASK
- PMX_MCIIORDY_MASK
- PMX_MCIIOWRWE_MASK
- PMX_MCILEDS_MASK
- PMX_MCIRESETCF_MASK
- PMX_MCISDCMD_MASK
- PMX_MCI_DATA8_15_MASK
- PMX_MDC_MDIO_MASK
- PMX_MII2_PL_80_TO_85_VAL
- PMX_MII2_PL_86_87_VAL
- PMX_MII2_PL_88_89_VAL
- PMX_MII2_PL_90_91_VAL
- PMX_MII2_PL_92_93_VAL
- PMX_MII2_PL_94_95_VAL
- PMX_MII2_PL_96_97_VAL
- PMX_MII_MASK
- PMX_NAND16BIT_1_MASK
- PMX_NAND8BIT_0_MASK
- PMX_NAND8BIT_1_MASK
- PMX_NAND8_MASK
- PMX_NAND_4CHIPS_MASK
- PMX_NFAD23_MASK
- PMX_NFAD24_MASK
- PMX_NFAD25_MASK
- PMX_NFCE1_MASK
- PMX_NFCE2_MASK
- PMX_NFCE3_MASK
- PMX_NFIO8_15_MASK
- PMX_NFRSTPWDWN0_MASK
- PMX_NFRSTPWDWN1_MASK
- PMX_NFRSTPWDWN2_MASK
- PMX_NFRSTPWDWN3_MASK
- PMX_NFWPRT1_MASK
- PMX_NFWPRT2_MASK
- PMX_NFWPRT3_MASK
- PMX_PCI_REG1_MASK
- PMX_PCI_REG2_MASK
- PMX_PL_0_1_MASK
- PMX_PL_100_101_MASK
- PMX_PL_10_11_MASK
- PMX_PL_12_MASK
- PMX_PL_13_14_MASK
- PMX_PL_13_MASK
- PMX_PL_14_MASK
- PMX_PL_15_16_MASK
- PMX_PL_15_MASK
- PMX_PL_17_18_MASK
- PMX_PL_19_MASK
- PMX_PL_20_MASK
- PMX_PL_21_TO_27_MASK
- PMX_PL_28_29_MASK
- PMX_PL_28_MASK
- PMX_PL_29_MASK
- PMX_PL_2_3_MASK
- PMX_PL_30_31_MASK
- PMX_PL_30_MASK
- PMX_PL_31_MASK
- PMX_PL_32_33_MASK
- PMX_PL_34_MASK
- PMX_PL_35_MASK
- PMX_PL_36_MASK
- PMX_PL_37_38_MASK
- PMX_PL_39_MASK
- PMX_PL_40_MASK
- PMX_PL_41_42_MASK
- PMX_PL_41_MASK
- PMX_PL_42_MASK
- PMX_PL_43_MASK
- PMX_PL_44_45_MASK
- PMX_PL_46_47_MASK
- PMX_PL_48_49_MASK
- PMX_PL_4_5_MASK
- PMX_PL_50_51_MASK
- PMX_PL_50_MASK
- PMX_PL_51_MASK
- PMX_PL_52_53_MASK
- PMX_PL_54_55_56_MASK
- PMX_PL_57_MASK
- PMX_PL_58_59_MASK
- PMX_PL_58_MASK
- PMX_PL_59_MASK
- PMX_PL_5_MASK
- PMX_PL_60_MASK
- PMX_PL_61_TO_64_MASK
- PMX_PL_65_TO_68_MASK
- PMX_PL_69_MASK
- PMX_PL_6_7_MASK
- PMX_PL_6_MASK
- PMX_PL_70_MASK
- PMX_PL_71_72_MASK
- PMX_PL_73_MASK
- PMX_PL_74_MASK
- PMX_PL_75_76_MASK
- PMX_PL_77_78_79_MASK
- PMX_PL_7_MASK
- PMX_PL_80_TO_85_MASK
- PMX_PL_86_87_MASK
- PMX_PL_86_MASK
- PMX_PL_87_MASK
- PMX_PL_88_89_MASK
- PMX_PL_8_9_MASK
- PMX_PL_90_91_MASK
- PMX_PL_92_93_MASK
- PMX_PL_94_95_MASK
- PMX_PL_96_97_MASK
- PMX_PL_98_MASK
- PMX_PL_99_MASK
- PMX_PWM0_1_PL_37_38_VAL
- PMX_PWM0_1_PL_88_89_VAL
- PMX_PWM0_EXT_PL_31_VAL
- PMX_PWM0_PL_15_VAL
- PMX_PWM0_PL_43_VAL
- PMX_PWM0_PL_60_VAL
- PMX_PWM1_EXT_PL_30_VAL
- PMX_PWM1_PL_14_VAL
- PMX_PWM1_PL_42_VAL
- PMX_PWM1_PL_59_VAL
- PMX_PWM2_PL_13_VAL
- PMX_PWM2_PL_34_VAL
- PMX_PWM2_PL_41_VAL
- PMX_PWM2_PL_58_VAL
- PMX_PWM2_PL_87_VAL
- PMX_PWM3_PL_12_VAL
- PMX_PWM3_PL_40_VAL
- PMX_PWM3_PL_57_VAL
- PMX_PWM3_PL_86_VAL
- PMX_PWM_0_1_PL_8_9_VAL
- PMX_PWM_2_PL_29_VAL
- PMX_PWM_2_PL_7_VAL
- PMX_PWM_3_PL_28_VAL
- PMX_PWM_3_PL_6_VAL
- PMX_PWM_MASK
- PMX_RGMII_REG0_MASK
- PMX_RGMII_REG1_MASK
- PMX_RGMII_REG2_MASK
- PMX_RMII_PL_10_11_VAL
- PMX_RMII_PL_13_14_VAL
- PMX_RMII_PL_15_16_VAL
- PMX_RMII_PL_17_18_VAL
- PMX_RMII_PL_19_VAL
- PMX_RMII_PL_20_VAL
- PMX_RMII_PL_21_TO_27_VAL
- PMX_RS485_PL_77_78_79_VAL
- PMX_RXCLK_RDV_TXEN_D03_MASK
- PMX_SDHCI_CD_PL_12_VAL
- PMX_SDHCI_CD_PL_51_VAL
- PMX_SDHCI_CD_PORT_12_VAL
- PMX_SDHCI_CD_PORT_51_VAL
- PMX_SDHCI_CD_PORT_SEL_MASK
- PMX_SDHCI_PL_100_101_VAL
- PMX_SDHCI_PL_43_VAL
- PMX_SDHCI_PL_44_45_VAL
- PMX_SDHCI_PL_46_47_VAL
- PMX_SDHCI_PL_48_49_VAL
- PMX_SDHCI_PL_50_VAL
- PMX_SDHCI_PL_99_VAL
- PMX_SMII_0_1_2_MASK
- PMX_SMII_PL_10_11_VAL
- PMX_SMII_PL_21_TO_27_VAL
- PMX_SMINCS2_MASK
- PMX_SMINCS3_MASK
- PMX_SMI_MASK
- PMX_SPP_PL_69_VAL
- PMX_SPP_PL_70_VAL
- PMX_SPP_PL_71_72_VAL
- PMX_SPP_PL_73_VAL
- PMX_SPP_PL_74_VAL
- PMX_SPP_PL_75_76_VAL
- PMX_SPP_PL_77_78_79_VAL
- PMX_SPP_PL_80_TO_85_VAL
- PMX_SSP0_CS0_MASK
- PMX_SSP0_CS1_2_MASK
- PMX_SSP0_MASK
- PMX_SSP1_PL_17_18_19_20_VAL
- PMX_SSP1_PL_36_VAL
- PMX_SSP1_PL_37_38_VAL
- PMX_SSP1_PL_39_VAL
- PMX_SSP1_PL_48_49_VAL
- PMX_SSP1_PL_50_51_VAL
- PMX_SSP1_PL_65_TO_68_VAL
- PMX_SSP1_PL_94_95_VAL
- PMX_SSP1_PL_96_97_VAL
- PMX_SSP1_PORT_17_TO_20_VAL
- PMX_SSP1_PORT_36_TO_39_VAL
- PMX_SSP1_PORT_48_TO_51_VAL
- PMX_SSP1_PORT_65_TO_68_VAL
- PMX_SSP1_PORT_94_TO_97_VAL
- PMX_SSP1_PORT_SEL_MASK
- PMX_SSP2_PL_13_14_15_16_VAL
- PMX_SSP2_PL_32_33_VAL
- PMX_SSP2_PL_34_VAL
- PMX_SSP2_PL_35_VAL
- PMX_SSP2_PL_44_45_VAL
- PMX_SSP2_PL_46_47_VAL
- PMX_SSP2_PL_61_TO_64_VAL
- PMX_SSP2_PL_90_91_VAL
- PMX_SSP2_PL_92_93_VAL
- PMX_SSP2_PORT_13_TO_16_VAL
- PMX_SSP2_PORT_32_TO_35_VAL
- PMX_SSP2_PORT_44_TO_47_VAL
- PMX_SSP2_PORT_61_TO_64_VAL
- PMX_SSP2_PORT_90_TO_93_VAL
- PMX_SSP2_PORT_SEL_MASK
- PMX_SSP_CS_MASK
- PMX_SSP_MASK
- PMX_TIMER_0_1_MASK
- PMX_TIMER_2_3_MASK
- PMX_TOUCH_XY_MASK
- PMX_TOUCH_X_PL_36_VAL
- PMX_TOUCH_Y_PL_5_VAL
- PMX_UART0_MASK
- PMX_UART0_MODEM_MASK
- PMX_UART1_ENH_PL_2_3_VAL
- PMX_UART1_ENH_PL_31_VAL
- PMX_UART1_ENH_PL_32_33_VAL
- PMX_UART1_ENH_PL_34_VAL
- PMX_UART1_ENH_PL_35_VAL
- PMX_UART1_ENH_PL_36_VAL
- PMX_UART1_ENH_PL_43_VAL
- PMX_UART1_ENH_PL_44_45_VAL
- PMX_UART1_ENH_PL_4_5_VAL
- PMX_UART1_ENH_PL_6_7_VAL
- PMX_UART1_ENH_PL_80_TO_85_VAL
- PMX_UART1_ENH_PORT_32_TO_34_36_VAL
- PMX_UART1_ENH_PORT_3_TO_5_7_VAL
- PMX_UART1_ENH_PORT_44_45_34_36_VAL
- PMX_UART1_ENH_PORT_81_TO_85_VAL
- PMX_UART1_ENH_PORT_SEL_MASK
- PMX_UART1_PL_28_29_VAL
- PMX_UART2_PL_0_1_VAL
- PMX_UART3_PL_15_16_VAL
- PMX_UART3_PL_41_42_VAL
- PMX_UART3_PL_52_53_VAL
- PMX_UART3_PL_73_VAL
- PMX_UART3_PL_74_VAL
- PMX_UART3_PL_8_9_VAL
- PMX_UART3_PL_94_95_VAL
- PMX_UART3_PL_98_VAL
- PMX_UART3_PL_99_VAL
- PMX_UART3_PORT_15_VAL
- PMX_UART3_PORT_41_VAL
- PMX_UART3_PORT_52_VAL
- PMX_UART3_PORT_73_VAL
- PMX_UART3_PORT_8_VAL
- PMX_UART3_PORT_94_VAL
- PMX_UART3_PORT_99_VAL
- PMX_UART3_PORT_SEL_MASK
- PMX_UART4_PL_100_101_VAL
- PMX_UART4_PL_13_14_VAL
- PMX_UART4_PL_39_VAL
- PMX_UART4_PL_40_VAL
- PMX_UART4_PL_6_7_VAL
- PMX_UART4_PL_71_72_VAL
- PMX_UART4_PL_92_93_VAL
- PMX_UART4_PORT_101_VAL
- PMX_UART4_PORT_13_VAL
- PMX_UART4_PORT_39_VAL
- PMX_UART4_PORT_6_VAL
- PMX_UART4_PORT_71_VAL
- PMX_UART4_PORT_92_VAL
- PMX_UART4_PORT_SEL_MASK
- PMX_UART5_PL_37_38_VAL
- PMX_UART5_PL_4_5_VAL
- PMX_UART5_PL_69_VAL
- PMX_UART5_PL_70_VAL
- PMX_UART5_PL_90_91_VAL
- PMX_UART5_PORT_37_VAL
- PMX_UART5_PORT_4_VAL
- PMX_UART5_PORT_69_VAL
- PMX_UART5_PORT_90_VAL
- PMX_UART5_PORT_SEL_MASK
- PMX_UART6_PL_2_3_VAL
- PMX_UART6_PL_88_89_VAL
- PMX_UART6_PORT_2_VAL
- PMX_UART6_PORT_88_VAL
- PMX_UART6_PORT_SEL_MASK
- PM_128K
- PM_16K
- PM_16M
- PM_1G
- PM_1K
- PM_1M
- PM_256K
- PM_256M
- PM_2M
- PM_3000_MTSLOT
- PM_32K
- PM_32M
- PM_4K
- PM_4M
- PM_512K
- PM_6250_MTSLOT
- PM_64K
- PM_64M
- PM_8K
- PM_8M
- PM_ACKNOWLEDGE_CB
- PM_ADDR_MASK
- PM_ALIGNED
- PM_API
- PM_API_NAME_LEN
- PM_APPLIANCE_PC
- PM_ASSERT_RESET
- PM_ASSERT_RESET_0
- PM_ASSERT_RESET_1
- PM_AUDIO
- PM_AUTO
- PM_AVS_EVENT
- PM_AVS_INTEN
- PM_AVS_RSTDR
- PM_AVS_STAT
- PM_BASE
- PM_BUSEVENT_MSK
- PM_BYTE_MSK
- PM_BYTE_SH
- PM_CACTIVE_STA_OFFSET
- PM_CACTIVE_STA_REG
- PM_CACTIVE_STA_REG_MASK
- PM_CACTIVE_STA_REG_OFFSET_CIM
- PM_CACTIVE_STA_REG_OFFSET_CRYPTO
- PM_CACTIVE_STA_REG_OFFSET_DMC
- PM_CACTIVE_STA_REG_OFFSET_GDMA
- PM_CACTIVE_STA_REG_OFFSET_GPIO
- PM_CACTIVE_STA_REG_OFFSET_GPU
- PM_CACTIVE_STA_REG_OFFSET_HCIE
- PM_CACTIVE_STA_REG_OFFSET_I2S
- PM_CACTIVE_STA_REG_OFFSET_LCDC
- PM_CACTIVE_STA_REG_OFFSET_PCIE0
- PM_CACTIVE_STA_REG_OFFSET_PCIE1
- PM_CACTIVE_STA_REG_OFFSET_RAID
- PM_CACTIVE_STA_REG_OFFSET_RTC
- PM_CACTIVE_STA_REG_OFFSET_SATA
- PM_CACTIVE_STA_REG_OFFSET_SDIO
- PM_CACTIVE_STA_REG_OFFSET_SMC_NFI
- PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S
- PM_CACTIVE_STA_REG_OFFSET_SWITCH
- PM_CACTIVE_STA_REG_OFFSET_TIMER
- PM_CACTIVE_STA_REG_OFFSET_UART1
- PM_CACTIVE_STA_REG_OFFSET_UART2
- PM_CACTIVE_STA_REG_OFFSET_UART3
- PM_CACTIVE_STA_REG_OFFSET_USB_HOST
- PM_CACTIVE_STA_REG_OFFSET_USB_OTG
- PM_CAM0
- PM_CAM0_CTRLEN
- PM_CAM0_LDOHPEN
- PM_CAM0_LDOLPEN
- PM_CAM1
- PM_CAM1_CTRLEN
- PM_CAM1_LDOHPEN
- PM_CAM1_LDOLPEN
- PM_CCP2TX
- PM_CCP2TX_CTRLEN
- PM_CCP2TX_LDOEN
- PM_CFG_IOBASE0
- PM_CFG_IOBASE1
- PM_CFG_REVID
- PM_CLK_CTRL_REG
- PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV
- PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL
- PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV
- PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE
- PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL
- PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN
- PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE
- PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV
- PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL
- PM_CLK_CTRL_REG_OFFSET_I2S_MCLK
- PM_CLK_CTRL_REG_OFFSET_MDC_DIV
- PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN
- PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN
- PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL
- PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL
- PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE
- PM_CLK_FORCE_CTL
- PM_CLK_GATE_OFFSET
- PM_CLK_GATE_REG
- PM_CLK_GATE_REG_MASK
- PM_CLK_GATE_REG_OFFSET_CIM
- PM_CLK_GATE_REG_OFFSET_CRYPTO
- PM_CLK_GATE_REG_OFFSET_GDMA
- PM_CLK_GATE_REG_OFFSET_GPIO
- PM_CLK_GATE_REG_OFFSET_GPU
- PM_CLK_GATE_REG_OFFSET_HCIE
- PM_CLK_GATE_REG_OFFSET_I2S
- PM_CLK_GATE_REG_OFFSET_LCDC
- PM_CLK_GATE_REG_OFFSET_PCIE
- PM_CLK_GATE_REG_OFFSET_RAID
- PM_CLK_GATE_REG_OFFSET_RTC
- PM_CLK_GATE_REG_OFFSET_SATA
- PM_CLK_GATE_REG_OFFSET_SDIO
- PM_CLK_GATE_REG_OFFSET_SMC_NFI
- PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C
- PM_CLK_GATE_REG_OFFSET_SWITCH
- PM_CLK_GATE_REG_OFFSET_TIMER
- PM_CLK_GATE_REG_OFFSET_UART1
- PM_CLK_GATE_REG_OFFSET_UART2
- PM_CLK_GATE_REG_OFFSET_UART3
- PM_CLK_GATE_REG_OFFSET_USB_HOST
- PM_CLK_GATE_REG_OFFSET_USB_OTG
- PM_CLOCK_DISABLE
- PM_CLOCK_ENABLE
- PM_CLOCK_GETDIVIDER
- PM_CLOCK_GETPARENT
- PM_CLOCK_GETRATE
- PM_CLOCK_GETSTATE
- PM_CLOCK_SETDIVIDER
- PM_CLOCK_SETPARENT
- PM_CLOCK_SETRATE
- PM_CLOS_OFFSET
- PM_CMD
- PM_CMD_CFG_TRIGGER_NC
- PM_CMD_CMD
- PM_CMD_CM_DELAY
- PM_CMD_CM_IMMEDIATE
- PM_CMD_CM_NOP
- PM_CMD_CM_TRIGGER
- PM_CMD_IOC
- PM_CMD_SYS_STATE_S5
- PM_COLD_CONFIG
- PM_COMBINE_MSK
- PM_COMBINE_MSKS
- PM_COMBINE_SH
- PM_CONFIG
- PM_CONFIG__Enable_BAPM_MASK
- PM_CONFIG__Enable_BAPM__SHIFT
- PM_CONFIG__Enable_HTC_Limit_MASK
- PM_CONFIG__Enable_HTC_Limit__SHIFT
- PM_CONFIG__Enable_Hybrid_Boost_MASK
- PM_CONFIG__Enable_Hybrid_Boost__SHIFT
- PM_CONFIG__Enable_LPMx_MASK
- PM_CONFIG__Enable_LPMx__SHIFT
- PM_CONFIG__Enable_LoadLine_MASK
- PM_CONFIG__Enable_LoadLine__SHIFT
- PM_CONFIG__Enable_NBDPM_MASK
- PM_CONFIG__Enable_NBDPM__SHIFT
- PM_CONFIG__Enable_PDM_MASK
- PM_CONFIG__Enable_PDM__SHIFT
- PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK
- PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT
- PM_CONFIG__Enable_TDC_Limit_MASK
- PM_CONFIG__Enable_TDC_Limit__SHIFT
- PM_CONFIG__Enable_VPC_Accumulators_MASK
- PM_CONFIG__Enable_VPC_Accumulators__SHIFT
- PM_CONFIG__NBPSTATE_AllCpusIdle_MASK
- PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT
- PM_CONFIG__Override_Calc_Temp_MASK
- PM_CONFIG__Override_Calc_Temp__SHIFT
- PM_CONFIG__Override_VPC_Current_MASK
- PM_CONFIG__Override_VPC_Current__SHIFT
- PM_CONFIG__PSTATE_AllCpusIdle_MASK
- PM_CONFIG__PSTATE_AllCpusIdle__SHIFT
- PM_CONFIG__Reserved1_MASK
- PM_CONFIG__Reserved1__SHIFT
- PM_CONFIG__Reserved2_MASK
- PM_CONFIG__Reserved2__SHIFT
- PM_CONFIG__Reserved3_MASK
- PM_CONFIG__Reserved3__SHIFT
- PM_CONFIG__Reserved_MASK
- PM_CONFIG__Reserved__SHIFT
- PM_CONFIG__SVI_Mode_MASK
- PM_CONFIG__SVI_Mode__SHIFT
- PM_CPU_CLK_DIV
- PM_CPU_PWR
- PM_CR_BASE
- PM_CR_RESET
- PM_CSR_REG
- PM_CSR_REG_OFFSET_CSR_EN
- PM_CSR_REG_OFFSET_CSR_NUM
- PM_CTL_DEV_RDY_
- PM_CTL_ED_EN_
- PM_CTL_PHY_RST_
- PM_CTL_RES_CLR_WKP_EN
- PM_CTL_RES_CLR_WKP_STS
- PM_CTL_SUS_MODE_
- PM_CTL_SUS_MODE_0
- PM_CTL_SUS_MODE_1
- PM_CTL_SUS_MODE_2
- PM_CTL_SUS_MODE_3
- PM_CTL_WOL_EN_
- PM_CTL_WUPS_
- PM_CTL_WUPS_ED_
- PM_CTL_WUPS_MULTI_
- PM_CTL_WUPS_NO_
- PM_CTL_WUPS_WOL_
- PM_CTRL
- PM_CTRL1
- PM_CTRL2
- PM_CTRL3
- PM_CTRL4
- PM_CTRL_ASPM_L0S_EN
- PM_CTRL_ASPM_L1_EN
- PM_CTRL_CLK_PWM_VER1_1
- PM_CTRL_CLK_REQ_EN
- PM_CTRL_CLK_SWH_L1
- PM_CTRL_ENABLE
- PM_CTRL_HOTRST
- PM_CTRL_L0S_BUFSRX_EN
- PM_CTRL_L0S_ENTRY_TIMER_MASK
- PM_CTRL_L0S_ENTRY_TIMER_SHIFT
- PM_CTRL_L1_ENTRY_TIMER_MASK
- PM_CTRL_L1_ENTRY_TIMER_SHIFT
- PM_CTRL_LCKDET_TIMER_DEF
- PM_CTRL_LCKDET_TIMER_MASK
- PM_CTRL_LCKDET_TIMER_SHIFT
- PM_CTRL_MAC_ASPM_CHK
- PM_CTRL_PM_REQ_TIMER_MASK
- PM_CTRL_PM_REQ_TIMER_SHIFT
- PM_CTRL_PM_REQ_TO_DEF
- PM_CTRL_RBER_EN
- PM_CTRL_RCVR_WT_TIMER
- PM_CTRL_RXL1_AFTER_L0S
- PM_CTRL_SA_DLY_EN
- PM_CTRL_SERDES_BUFS_RX_L1_EN
- PM_CTRL_SERDES_L1_EN
- PM_CTRL_SERDES_PD_EX_L1
- PM_CTRL_SERDES_PLL_L1_EN
- PM_CTRL_SPRSDWER_EN
- PM_CTR_BASE
- PM_CURRENT_STATE
- PM_CYC
- PM_Card_Disable
- PM_DATA
- PM_DDR2CAL0
- PM_DDR2START
- PM_DEBUG_STATISTIC_NOTIFIC
- PM_DEEP_STANDBY
- PM_DEFAULT_MASK
- PM_DESKTOP
- PM_DFT
- PM_DIR_ENTRY_U1
- PM_DIR_ENTRY_U2
- PM_DIR_ENTRY_U3
- PM_DIR_LINK_REJECT
- PM_DIVCFG
- PM_DIVCFG_VGACLK
- PM_DIVCFG_VGACLK_MASK
- PM_DIVSTATUS
- PM_DMOE
- PM_DOMAIN_COUNT
- PM_DOMAIN_VFE0
- PM_DOMAIN_VFE1
- PM_DPHY_STANDBY_CLEAR
- PM_DQMH
- PM_DQML
- PM_DSI0
- PM_DSI0_CTRLEN
- PM_DSI0_LDOHPEN
- PM_DSI0_LDOLPEN
- PM_DSI1
- PM_DSI1_CTRLEN
- PM_DSI1_LDOHPEN
- PM_DSI1_LDOLPEN
- PM_DSP2_CONFIG
- PM_DSP2_ON_OFF
- PM_DSP_CONFIG
- PM_DSP_ON_OFF
- PM_DTB_MISS
- PM_DUMMY
- PM_DYN_CLK_CNTL
- PM_ENAB
- PM_END_OF_BUFFER
- PM_ENTERPRISE_SERVER
- PM_ENTRY_BYTES
- PM_EVENT_AUTO
- PM_EVENT_AUTO_RESUME
- PM_EVENT_AUTO_SUSPEND
- PM_EVENT_DEBUG
- PM_EVENT_FREEZE
- PM_EVENT_HIBERNATE
- PM_EVENT_INVALID
- PM_EVENT_ON
- PM_EVENT_PRETHAW
- PM_EVENT_QUIESCE
- PM_EVENT_RECOVER
- PM_EVENT_REMOTE
- PM_EVENT_REMOTE_RESUME
- PM_EVENT_RESTORE
- PM_EVENT_RESUME
- PM_EVENT_SLEEP
- PM_EVENT_SUSPEND
- PM_EVENT_THAW
- PM_EVENT_USER
- PM_EVENT_USER_RESUME
- PM_EVENT_USER_SUSPEND
- PM_EVGENCTRL
- PM_EVGENOFFTIM
- PM_EVGENONTIM
- PM_Enable
- PM_FAIL
- PM_FAST
- PM_FAST_PWRDOWN
- PM_FILE
- PM_FLTR_RESET
- PM_FORCE_LINK_ACCEPT
- PM_FORCE_U1_ENTRY
- PM_FORCE_U2_ENTRY
- PM_FPGA_GET_STATUS
- PM_FPGA_LOAD
- PM_FPU
- PM_FRAME_ASSOC
- PM_FRAME_MGMT
- PM_FRAME_NONE
- PM_FUSES_10__BAPMTI_GpuTjHyst_MASK
- PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT
- PM_FUSES_10__BAPMTI_TjMax_0_MASK
- PM_FUSES_10__BAPMTI_TjMax_0__SHIFT
- PM_FUSES_10__BAPMTI_TjMax_1_MASK
- PM_FUSES_10__BAPMTI_TjMax_1__SHIFT
- PM_FUSES_10__BapmVddCVidHiSidd2_0_MASK
- PM_FUSES_10__BapmVddCVidHiSidd2_0__SHIFT
- PM_FUSES_10__BapmVddCVidHiSidd2_1_MASK
- PM_FUSES_10__BapmVddCVidHiSidd2_1__SHIFT
- PM_FUSES_10__BapmVddCVidHiSidd2_2_MASK
- PM_FUSES_10__BapmVddCVidHiSidd2_2__SHIFT
- PM_FUSES_10__BapmVddCVidHiSidd2_3_MASK
- PM_FUSES_10__BapmVddCVidHiSidd2_3__SHIFT
- PM_FUSES_10__GnbLPML_0_MASK
- PM_FUSES_10__GnbLPML_0__SHIFT
- PM_FUSES_10__GnbLPML_1_MASK
- PM_FUSES_10__GnbLPML_1__SHIFT
- PM_FUSES_10__GnbLPML_2_MASK
- PM_FUSES_10__GnbLPML_2__SHIFT
- PM_FUSES_10__GnbLPML_3_MASK
- PM_FUSES_10__GnbLPML_3__SHIFT
- PM_FUSES_10__LPMLTemperatureScaler_0_MASK
- PM_FUSES_10__LPMLTemperatureScaler_0__SHIFT
- PM_FUSES_10__LPMLTemperatureScaler_1_MASK
- PM_FUSES_10__LPMLTemperatureScaler_1__SHIFT
- PM_FUSES_10__LPMLTemperatureScaler_2_MASK
- PM_FUSES_10__LPMLTemperatureScaler_2__SHIFT
- PM_FUSES_10__LPMLTemperatureScaler_3_MASK
- PM_FUSES_10__LPMLTemperatureScaler_3__SHIFT
- PM_FUSES_11__BAPMTI_GpuTjMax_MASK
- PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT
- PM_FUSES_11__BapmVddCVidHiSidd2_4_MASK
- PM_FUSES_11__BapmVddCVidHiSidd2_4__SHIFT
- PM_FUSES_11__BapmVddCVidHiSidd2_5_MASK
- PM_FUSES_11__BapmVddCVidHiSidd2_5__SHIFT
- PM_FUSES_11__BapmVddCVidHiSidd2_6_MASK
- PM_FUSES_11__BapmVddCVidHiSidd2_6__SHIFT
- PM_FUSES_11__BapmVddCVidHiSidd2_7_MASK
- PM_FUSES_11__BapmVddCVidHiSidd2_7__SHIFT
- PM_FUSES_11__GnbLPML_4_MASK
- PM_FUSES_11__GnbLPML_4__SHIFT
- PM_FUSES_11__GnbLPML_5_MASK
- PM_FUSES_11__GnbLPML_5__SHIFT
- PM_FUSES_11__GnbLPML_6_MASK
- PM_FUSES_11__GnbLPML_6__SHIFT
- PM_FUSES_11__GnbLPML_7_MASK
- PM_FUSES_11__GnbLPML_7__SHIFT
- PM_FUSES_11__LPMLTemperatureScaler_4_MASK
- PM_FUSES_11__LPMLTemperatureScaler_4__SHIFT
- PM_FUSES_11__LPMLTemperatureScaler_5_MASK
- PM_FUSES_11__LPMLTemperatureScaler_5__SHIFT
- PM_FUSES_11__LPMLTemperatureScaler_6_MASK
- PM_FUSES_11__LPMLTemperatureScaler_6__SHIFT
- PM_FUSES_11__LPMLTemperatureScaler_7_MASK
- PM_FUSES_11__LPMLTemperatureScaler_7__SHIFT
- PM_FUSES_11__LhtcHystLmt_MASK
- PM_FUSES_11__LhtcHystLmt__SHIFT
- PM_FUSES_11__LhtcPstateLimit_MASK
- PM_FUSES_11__LhtcPstateLimit__SHIFT
- PM_FUSES_11__LhtcTmpLmt_MASK
- PM_FUSES_11__LhtcTmpLmt__SHIFT
- PM_FUSES_12__FuzzyFan_ErrorRateSetDelta_MASK
- PM_FUSES_12__FuzzyFan_ErrorRateSetDelta__SHIFT
- PM_FUSES_12__FuzzyFan_ErrorSetDelta_MASK
- PM_FUSES_12__FuzzyFan_ErrorSetDelta__SHIFT
- PM_FUSES_12__GnbLPML_10_MASK
- PM_FUSES_12__GnbLPML_10__SHIFT
- PM_FUSES_12__GnbLPML_11_MASK
- PM_FUSES_12__GnbLPML_11__SHIFT
- PM_FUSES_12__GnbLPML_8_MASK
- PM_FUSES_12__GnbLPML_8__SHIFT
- PM_FUSES_12__GnbLPML_9_MASK
- PM_FUSES_12__GnbLPML_9__SHIFT
- PM_FUSES_12__LPMLTemperatureScaler_10_MASK
- PM_FUSES_12__LPMLTemperatureScaler_10__SHIFT
- PM_FUSES_12__LPMLTemperatureScaler_11_MASK
- PM_FUSES_12__LPMLTemperatureScaler_11__SHIFT
- PM_FUSES_12__LPMLTemperatureScaler_8_MASK
- PM_FUSES_12__LPMLTemperatureScaler_8__SHIFT
- PM_FUSES_12__LPMLTemperatureScaler_9_MASK
- PM_FUSES_12__LPMLTemperatureScaler_9__SHIFT
- PM_FUSES_12__MaxPwrCpu_0_MASK
- PM_FUSES_12__MaxPwrCpu_0__SHIFT
- PM_FUSES_12__MaxPwrCpu_1_MASK
- PM_FUSES_12__MaxPwrCpu_1__SHIFT
- PM_FUSES_12__NomPwrCpu_0_MASK
- PM_FUSES_12__NomPwrCpu_0__SHIFT
- PM_FUSES_12__NomPwrCpu_1_MASK
- PM_FUSES_12__NomPwrCpu_1__SHIFT
- PM_FUSES_13__FuzzyFan_PwmSetDelta_MASK
- PM_FUSES_13__FuzzyFan_PwmSetDelta__SHIFT
- PM_FUSES_13__GnbLPML_12_MASK
- PM_FUSES_13__GnbLPML_12__SHIFT
- PM_FUSES_13__GnbLPML_13_MASK
- PM_FUSES_13__GnbLPML_13__SHIFT
- PM_FUSES_13__GnbLPML_14_MASK
- PM_FUSES_13__GnbLPML_14__SHIFT
- PM_FUSES_13__GnbLPML_15_MASK
- PM_FUSES_13__GnbLPML_15__SHIFT
- PM_FUSES_13__LPMLTemperatureScaler_12_MASK
- PM_FUSES_13__LPMLTemperatureScaler_12__SHIFT
- PM_FUSES_13__LPMLTemperatureScaler_13_MASK
- PM_FUSES_13__LPMLTemperatureScaler_13__SHIFT
- PM_FUSES_13__LPMLTemperatureScaler_14_MASK
- PM_FUSES_13__LPMLTemperatureScaler_14__SHIFT
- PM_FUSES_13__LPMLTemperatureScaler_15_MASK
- PM_FUSES_13__LPMLTemperatureScaler_15__SHIFT
- PM_FUSES_13__MidPwrCpu_0_MASK
- PM_FUSES_13__MidPwrCpu_0__SHIFT
- PM_FUSES_13__MidPwrCpu_1_MASK
- PM_FUSES_13__MidPwrCpu_1__SHIFT
- PM_FUSES_13__NomPwrGpu_MASK
- PM_FUSES_13__NomPwrGpu__SHIFT
- PM_FUSES_13__Reserved6_MASK
- PM_FUSES_13__Reserved6__SHIFT
- PM_FUSES_14__FuzzyFan_ErrorRateSetDelta_MASK
- PM_FUSES_14__FuzzyFan_ErrorRateSetDelta__SHIFT
- PM_FUSES_14__FuzzyFan_ErrorSetDelta_MASK
- PM_FUSES_14__FuzzyFan_ErrorSetDelta__SHIFT
- PM_FUSES_14__GnbLPMLMaxVid_MASK
- PM_FUSES_14__GnbLPMLMaxVid__SHIFT
- PM_FUSES_14__GnbLPMLMinVid_MASK
- PM_FUSES_14__GnbLPMLMinVid__SHIFT
- PM_FUSES_14__GnbLPML_0_MASK
- PM_FUSES_14__GnbLPML_0__SHIFT
- PM_FUSES_14__GnbLPML_1_MASK
- PM_FUSES_14__GnbLPML_1__SHIFT
- PM_FUSES_14__GnbLPML_2_MASK
- PM_FUSES_14__GnbLPML_2__SHIFT
- PM_FUSES_14__GnbLPML_3_MASK
- PM_FUSES_14__GnbLPML_3__SHIFT
- PM_FUSES_14__MaxPwrGpu_MASK
- PM_FUSES_14__MaxPwrGpu__SHIFT
- PM_FUSES_14__MinPwrGpu_MASK
- PM_FUSES_14__MinPwrGpu__SHIFT
- PM_FUSES_14__Reserved1_0_MASK
- PM_FUSES_14__Reserved1_0__SHIFT
- PM_FUSES_14__Reserved1_1_MASK
- PM_FUSES_14__Reserved1_1__SHIFT
- PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK
- PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT
- PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK
- PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT
- PM_FUSES_15__FuzzyFan_PwmSetDelta_MASK
- PM_FUSES_15__FuzzyFan_PwmSetDelta__SHIFT
- PM_FUSES_15__GnbLPML_4_MASK
- PM_FUSES_15__GnbLPML_4__SHIFT
- PM_FUSES_15__GnbLPML_5_MASK
- PM_FUSES_15__GnbLPML_5__SHIFT
- PM_FUSES_15__GnbLPML_6_MASK
- PM_FUSES_15__GnbLPML_6__SHIFT
- PM_FUSES_15__GnbLPML_7_MASK
- PM_FUSES_15__GnbLPML_7__SHIFT
- PM_FUSES_15__MidPwrTempHyst_MASK
- PM_FUSES_15__MidPwrTempHyst__SHIFT
- PM_FUSES_15__PCIe1PhyOffset_MASK
- PM_FUSES_15__PCIe1PhyOffset__SHIFT
- PM_FUSES_15__PCIe2PhyOffset_MASK
- PM_FUSES_15__PCIe2PhyOffset__SHIFT
- PM_FUSES_15__PCIe3PhyOffset_MASK
- PM_FUSES_15__PCIe3PhyOffset__SHIFT
- PM_FUSES_15__Reserved6_MASK
- PM_FUSES_15__Reserved6__SHIFT
- PM_FUSES_16__DCE1PhyOffset_MASK
- PM_FUSES_16__DCE1PhyOffset__SHIFT
- PM_FUSES_16__DCE2PhyOffset_MASK
- PM_FUSES_16__DCE2PhyOffset__SHIFT
- PM_FUSES_16__GnbLPML_0_MASK
- PM_FUSES_16__GnbLPML_0__SHIFT
- PM_FUSES_16__GnbLPML_10_MASK
- PM_FUSES_16__GnbLPML_10__SHIFT
- PM_FUSES_16__GnbLPML_11_MASK
- PM_FUSES_16__GnbLPML_11__SHIFT
- PM_FUSES_16__GnbLPML_1_MASK
- PM_FUSES_16__GnbLPML_1__SHIFT
- PM_FUSES_16__GnbLPML_2_MASK
- PM_FUSES_16__GnbLPML_2__SHIFT
- PM_FUSES_16__GnbLPML_3_MASK
- PM_FUSES_16__GnbLPML_3__SHIFT
- PM_FUSES_16__GnbLPML_8_MASK
- PM_FUSES_16__GnbLPML_8__SHIFT
- PM_FUSES_16__GnbLPML_9_MASK
- PM_FUSES_16__GnbLPML_9__SHIFT
- PM_FUSES_16__TDC_VDD_PkgLimit_MASK
- PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT
- PM_FUSES_17__GnbLPML_12_MASK
- PM_FUSES_17__GnbLPML_12__SHIFT
- PM_FUSES_17__GnbLPML_13_MASK
- PM_FUSES_17__GnbLPML_13__SHIFT
- PM_FUSES_17__GnbLPML_14_MASK
- PM_FUSES_17__GnbLPML_14__SHIFT
- PM_FUSES_17__GnbLPML_15_MASK
- PM_FUSES_17__GnbLPML_15__SHIFT
- PM_FUSES_17__GnbLPML_4_MASK
- PM_FUSES_17__GnbLPML_4__SHIFT
- PM_FUSES_17__GnbLPML_5_MASK
- PM_FUSES_17__GnbLPML_5__SHIFT
- PM_FUSES_17__GnbLPML_6_MASK
- PM_FUSES_17__GnbLPML_6__SHIFT
- PM_FUSES_17__GnbLPML_7_MASK
- PM_FUSES_17__GnbLPML_7__SHIFT
- PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK
- PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT
- PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK
- PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT
- PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK
- PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT
- PM_FUSES_18__GnbLPMLMaxVid_MASK
- PM_FUSES_18__GnbLPMLMaxVid__SHIFT
- PM_FUSES_18__GnbLPMLMinVid_MASK
- PM_FUSES_18__GnbLPMLMinVid__SHIFT
- PM_FUSES_18__GnbLPML_10_MASK
- PM_FUSES_18__GnbLPML_10__SHIFT
- PM_FUSES_18__GnbLPML_11_MASK
- PM_FUSES_18__GnbLPML_11__SHIFT
- PM_FUSES_18__GnbLPML_8_MASK
- PM_FUSES_18__GnbLPML_8__SHIFT
- PM_FUSES_18__GnbLPML_9_MASK
- PM_FUSES_18__GnbLPML_9__SHIFT
- PM_FUSES_18__Reserved1_0_MASK
- PM_FUSES_18__Reserved1_0__SHIFT
- PM_FUSES_18__Reserved1_1_MASK
- PM_FUSES_18__Reserved1_1__SHIFT
- PM_FUSES_18__TDC_MAWt_MASK
- PM_FUSES_18__TDC_MAWt__SHIFT
- PM_FUSES_18__TdcWaterfallCtl_MASK
- PM_FUSES_18__TdcWaterfallCtl__SHIFT
- PM_FUSES_18__TdpAgeRate_MASK
- PM_FUSES_18__TdpAgeRate__SHIFT
- PM_FUSES_18__TdpAgeValue_MASK
- PM_FUSES_18__TdpAgeValue__SHIFT
- PM_FUSES_19__BapmFuseOverride_MASK
- PM_FUSES_19__BapmFuseOverride__SHIFT
- PM_FUSES_19__BapmLhtcCap_MASK
- PM_FUSES_19__BapmLhtcCap__SHIFT
- PM_FUSES_19__BapmVddCBaseLeakageHiSidd_MASK
- PM_FUSES_19__BapmVddCBaseLeakageHiSidd__SHIFT
- PM_FUSES_19__BapmVddCBaseLeakageLoSidd_MASK
- PM_FUSES_19__BapmVddCBaseLeakageLoSidd__SHIFT
- PM_FUSES_19__GnbLPML_12_MASK
- PM_FUSES_19__GnbLPML_12__SHIFT
- PM_FUSES_19__GnbLPML_13_MASK
- PM_FUSES_19__GnbLPML_13__SHIFT
- PM_FUSES_19__GnbLPML_14_MASK
- PM_FUSES_19__GnbLPML_14__SHIFT
- PM_FUSES_19__GnbLPML_15_MASK
- PM_FUSES_19__GnbLPML_15__SHIFT
- PM_FUSES_19__SmuCoolingIndex_MASK
- PM_FUSES_19__SmuCoolingIndex__SHIFT
- PM_FUSES_19__SmuSocIndex_MASK
- PM_FUSES_19__SmuSocIndex__SHIFT
- PM_FUSES_1__BapmPstateVid_0_MASK
- PM_FUSES_1__BapmPstateVid_0__SHIFT
- PM_FUSES_1__BapmPstateVid_1_MASK
- PM_FUSES_1__BapmPstateVid_1__SHIFT
- PM_FUSES_1__BapmPstateVid_2_MASK
- PM_FUSES_1__BapmPstateVid_2__SHIFT
- PM_FUSES_1__BapmPstateVid_3_MASK
- PM_FUSES_1__BapmPstateVid_3__SHIFT
- PM_FUSES_1__BapmVddCVidHiSidd_0_MASK
- PM_FUSES_1__BapmVddCVidHiSidd_0__SHIFT
- PM_FUSES_1__BapmVddCVidHiSidd_1_MASK
- PM_FUSES_1__BapmVddCVidHiSidd_1__SHIFT
- PM_FUSES_1__BapmVddCVidHiSidd_2_MASK
- PM_FUSES_1__BapmVddCVidHiSidd_2__SHIFT
- PM_FUSES_1__BapmVddCVidHiSidd_3_MASK
- PM_FUSES_1__BapmVddCVidHiSidd_3__SHIFT
- PM_FUSES_1__SviLoadLineEn_MASK
- PM_FUSES_1__SviLoadLineEn__SHIFT
- PM_FUSES_1__SviLoadLineOffsetVddC_MASK
- PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT
- PM_FUSES_1__SviLoadLineTrimVddC_MASK
- PM_FUSES_1__SviLoadLineTrimVddC__SHIFT
- PM_FUSES_1__SviLoadLineVddC_MASK
- PM_FUSES_1__SviLoadLineVddC__SHIFT
- PM_FUSES_20__GnbLPMLMaxVid_MASK
- PM_FUSES_20__GnbLPMLMaxVid__SHIFT
- PM_FUSES_20__GnbLPMLMinVid_MASK
- PM_FUSES_20__GnbLPMLMinVid__SHIFT
- PM_FUSES_20__Reserved1_0_MASK
- PM_FUSES_20__Reserved1_0__SHIFT
- PM_FUSES_20__Reserved1_1_MASK
- PM_FUSES_20__Reserved1_1__SHIFT
- PM_FUSES_20__SamClkDid_0_MASK
- PM_FUSES_20__SamClkDid_0__SHIFT
- PM_FUSES_20__SamClkDid_1_MASK
- PM_FUSES_20__SamClkDid_1__SHIFT
- PM_FUSES_20__SamClkDid_2_MASK
- PM_FUSES_20__SamClkDid_2__SHIFT
- PM_FUSES_20__SamClkDid_3_MASK
- PM_FUSES_20__SamClkDid_3__SHIFT
- PM_FUSES_21__AmbientTempBase_MASK
- PM_FUSES_21__AmbientTempBase__SHIFT
- PM_FUSES_21__BapmVddCBaseLeakageHiSidd_MASK
- PM_FUSES_21__BapmVddCBaseLeakageHiSidd__SHIFT
- PM_FUSES_21__BapmVddCBaseLeakageLoSidd_MASK
- PM_FUSES_21__BapmVddCBaseLeakageLoSidd__SHIFT
- PM_FUSES_21__LPMLTemperatureMax_MASK
- PM_FUSES_21__LPMLTemperatureMax__SHIFT
- PM_FUSES_21__LPMLTemperatureMin_MASK
- PM_FUSES_21__LPMLTemperatureMin__SHIFT
- PM_FUSES_21__SamClkDid_4_MASK
- PM_FUSES_21__SamClkDid_4__SHIFT
- PM_FUSES_22__LPMLTemperatureScaler_0_MASK
- PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT
- PM_FUSES_22__LPMLTemperatureScaler_1_MASK
- PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT
- PM_FUSES_22__LPMLTemperatureScaler_2_MASK
- PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT
- PM_FUSES_22__LPMLTemperatureScaler_3_MASK
- PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT
- PM_FUSES_23__LPMLTemperatureScaler_4_MASK
- PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT
- PM_FUSES_23__LPMLTemperatureScaler_5_MASK
- PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT
- PM_FUSES_23__LPMLTemperatureScaler_6_MASK
- PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT
- PM_FUSES_23__LPMLTemperatureScaler_7_MASK
- PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT
- PM_FUSES_24__LPMLTemperatureScaler_10_MASK
- PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT
- PM_FUSES_24__LPMLTemperatureScaler_11_MASK
- PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT
- PM_FUSES_24__LPMLTemperatureScaler_8_MASK
- PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT
- PM_FUSES_24__LPMLTemperatureScaler_9_MASK
- PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT
- PM_FUSES_25__LPMLTemperatureScaler_12_MASK
- PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT
- PM_FUSES_25__LPMLTemperatureScaler_13_MASK
- PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT
- PM_FUSES_25__LPMLTemperatureScaler_14_MASK
- PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT
- PM_FUSES_25__LPMLTemperatureScaler_15_MASK
- PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT
- PM_FUSES_26__GnbLPML_0_MASK
- PM_FUSES_26__GnbLPML_0__SHIFT
- PM_FUSES_26__GnbLPML_1_MASK
- PM_FUSES_26__GnbLPML_1__SHIFT
- PM_FUSES_26__GnbLPML_2_MASK
- PM_FUSES_26__GnbLPML_2__SHIFT
- PM_FUSES_26__GnbLPML_3_MASK
- PM_FUSES_26__GnbLPML_3__SHIFT
- PM_FUSES_27__GnbLPML_4_MASK
- PM_FUSES_27__GnbLPML_4__SHIFT
- PM_FUSES_27__GnbLPML_5_MASK
- PM_FUSES_27__GnbLPML_5__SHIFT
- PM_FUSES_27__GnbLPML_6_MASK
- PM_FUSES_27__GnbLPML_6__SHIFT
- PM_FUSES_27__GnbLPML_7_MASK
- PM_FUSES_27__GnbLPML_7__SHIFT
- PM_FUSES_28__GnbLPML_10_MASK
- PM_FUSES_28__GnbLPML_10__SHIFT
- PM_FUSES_28__GnbLPML_11_MASK
- PM_FUSES_28__GnbLPML_11__SHIFT
- PM_FUSES_28__GnbLPML_8_MASK
- PM_FUSES_28__GnbLPML_8__SHIFT
- PM_FUSES_28__GnbLPML_9_MASK
- PM_FUSES_28__GnbLPML_9__SHIFT
- PM_FUSES_29__GnbLPML_12_MASK
- PM_FUSES_29__GnbLPML_12__SHIFT
- PM_FUSES_29__GnbLPML_13_MASK
- PM_FUSES_29__GnbLPML_13__SHIFT
- PM_FUSES_29__GnbLPML_14_MASK
- PM_FUSES_29__GnbLPML_14__SHIFT
- PM_FUSES_29__GnbLPML_15_MASK
- PM_FUSES_29__GnbLPML_15__SHIFT
- PM_FUSES_2__BapmPstateVid_4_MASK
- PM_FUSES_2__BapmPstateVid_4__SHIFT
- PM_FUSES_2__BapmPstateVid_5_MASK
- PM_FUSES_2__BapmPstateVid_5__SHIFT
- PM_FUSES_2__BapmPstateVid_6_MASK
- PM_FUSES_2__BapmPstateVid_6__SHIFT
- PM_FUSES_2__BapmPstateVid_7_MASK
- PM_FUSES_2__BapmPstateVid_7__SHIFT
- PM_FUSES_2__BapmVddCVidHiSidd_4_MASK
- PM_FUSES_2__BapmVddCVidHiSidd_4__SHIFT
- PM_FUSES_2__BapmVddCVidHiSidd_5_MASK
- PM_FUSES_2__BapmVddCVidHiSidd_5__SHIFT
- PM_FUSES_2__BapmVddCVidHiSidd_6_MASK
- PM_FUSES_2__BapmVddCVidHiSidd_6__SHIFT
- PM_FUSES_2__BapmVddCVidHiSidd_7_MASK
- PM_FUSES_2__BapmVddCVidHiSidd_7__SHIFT
- PM_FUSES_2__TDC_MAWt_MASK
- PM_FUSES_2__TDC_MAWt__SHIFT
- PM_FUSES_2__TDC_VDDC_PkgLimit_MASK
- PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT
- PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK
- PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT
- PM_FUSES_30__NbVid_0_MASK
- PM_FUSES_30__NbVid_0__SHIFT
- PM_FUSES_30__NbVid_1_MASK
- PM_FUSES_30__NbVid_1__SHIFT
- PM_FUSES_30__NbVid_2_MASK
- PM_FUSES_30__NbVid_2__SHIFT
- PM_FUSES_30__NbVid_3_MASK
- PM_FUSES_30__NbVid_3__SHIFT
- PM_FUSES_31__CpuVid_0_MASK
- PM_FUSES_31__CpuVid_0__SHIFT
- PM_FUSES_31__CpuVid_1_MASK
- PM_FUSES_31__CpuVid_1__SHIFT
- PM_FUSES_31__CpuVid_2_MASK
- PM_FUSES_31__CpuVid_2__SHIFT
- PM_FUSES_31__CpuVid_3_MASK
- PM_FUSES_31__CpuVid_3__SHIFT
- PM_FUSES_32__CpuVid_4_MASK
- PM_FUSES_32__CpuVid_4__SHIFT
- PM_FUSES_32__CpuVid_5_MASK
- PM_FUSES_32__CpuVid_5__SHIFT
- PM_FUSES_32__CpuVid_6_MASK
- PM_FUSES_32__CpuVid_6__SHIFT
- PM_FUSES_32__CpuVid_7_MASK
- PM_FUSES_32__CpuVid_7__SHIFT
- PM_FUSES_33__GnbLPMLMaxVid_MASK
- PM_FUSES_33__GnbLPMLMaxVid__SHIFT
- PM_FUSES_33__GnbLPMLMinVid_MASK
- PM_FUSES_33__GnbLPMLMinVid__SHIFT
- PM_FUSES_33__Tdp2Watt_MASK
- PM_FUSES_33__Tdp2Watt__SHIFT
- PM_FUSES_34__Lpml_0_MASK
- PM_FUSES_34__Lpml_0__SHIFT
- PM_FUSES_34__Lpml_1_MASK
- PM_FUSES_34__Lpml_1__SHIFT
- PM_FUSES_34__Lpml_2_MASK
- PM_FUSES_34__Lpml_2__SHIFT
- PM_FUSES_34__Lpml_3_MASK
- PM_FUSES_34__Lpml_3__SHIFT
- PM_FUSES_35__Lpml_4_MASK
- PM_FUSES_35__Lpml_4__SHIFT
- PM_FUSES_35__Lpml_5_MASK
- PM_FUSES_35__Lpml_5__SHIFT
- PM_FUSES_35__Lpml_6_MASK
- PM_FUSES_35__Lpml_6__SHIFT
- PM_FUSES_35__Lpml_7_MASK
- PM_FUSES_35__Lpml_7__SHIFT
- PM_FUSES_36__Lpmv_0_MASK
- PM_FUSES_36__Lpmv_0__SHIFT
- PM_FUSES_36__Lpmv_1_MASK
- PM_FUSES_36__Lpmv_1__SHIFT
- PM_FUSES_36__Lpmv_2_MASK
- PM_FUSES_36__Lpmv_2__SHIFT
- PM_FUSES_36__Lpmv_3_MASK
- PM_FUSES_36__Lpmv_3__SHIFT
- PM_FUSES_37__Lpmv_4_MASK
- PM_FUSES_37__Lpmv_4__SHIFT
- PM_FUSES_37__Lpmv_5_MASK
- PM_FUSES_37__Lpmv_5__SHIFT
- PM_FUSES_37__Lpmv_6_MASK
- PM_FUSES_37__Lpmv_6__SHIFT
- PM_FUSES_37__Lpmv_7_MASK
- PM_FUSES_37__Lpmv_7__SHIFT
- PM_FUSES_38__EClkDid_0_MASK
- PM_FUSES_38__EClkDid_0__SHIFT
- PM_FUSES_38__EClkDid_1_MASK
- PM_FUSES_38__EClkDid_1__SHIFT
- PM_FUSES_38__EClkDid_2_MASK
- PM_FUSES_38__EClkDid_2__SHIFT
- PM_FUSES_38__EClkDid_3_MASK
- PM_FUSES_38__EClkDid_3__SHIFT
- PM_FUSES_39__BoostLock_MASK
- PM_FUSES_39__BoostLock__SHIFT
- PM_FUSES_39__C6CstatePower_MASK
- PM_FUSES_39__C6CstatePower__SHIFT
- PM_FUSES_39__CoreDis_MASK
- PM_FUSES_39__CoreDis__SHIFT
- PM_FUSES_39__EClkDid_4_MASK
- PM_FUSES_39__EClkDid_4__SHIFT
- PM_FUSES_3__BapmVddCVidLoSidd_0_MASK
- PM_FUSES_3__BapmVddCVidLoSidd_0__SHIFT
- PM_FUSES_3__BapmVddCVidLoSidd_1_MASK
- PM_FUSES_3__BapmVddCVidLoSidd_1__SHIFT
- PM_FUSES_3__BapmVddCVidLoSidd_2_MASK
- PM_FUSES_3__BapmVddCVidLoSidd_2__SHIFT
- PM_FUSES_3__BapmVddCVidLoSidd_3_MASK
- PM_FUSES_3__BapmVddCVidLoSidd_3__SHIFT
- PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK
- PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT
- PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK
- PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT
- PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK
- PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT
- PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK
- PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT
- PM_FUSES_3__LPMLTemperatureMax_MASK
- PM_FUSES_3__LPMLTemperatureMax__SHIFT
- PM_FUSES_3__LPMLTemperatureMin_MASK
- PM_FUSES_3__LPMLTemperatureMin__SHIFT
- PM_FUSES_3__Reserved_MASK
- PM_FUSES_3__Reserved__SHIFT
- PM_FUSES_3__TdcWaterfallCtl_MASK
- PM_FUSES_3__TdcWaterfallCtl__SHIFT
- PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK
- PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT
- PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK
- PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT
- PM_FUSES_41__VddNbVid_0_MASK
- PM_FUSES_41__VddNbVid_0__SHIFT
- PM_FUSES_41__VddNbVid_1_MASK
- PM_FUSES_41__VddNbVid_1__SHIFT
- PM_FUSES_41__VddNbVid_2_MASK
- PM_FUSES_41__VddNbVid_2__SHIFT
- PM_FUSES_41__VddNbVid_3_MASK
- PM_FUSES_41__VddNbVid_3__SHIFT
- PM_FUSES_42__VddNbVidOffset_0_MASK
- PM_FUSES_42__VddNbVidOffset_0__SHIFT
- PM_FUSES_42__VddNbVidOffset_1_MASK
- PM_FUSES_42__VddNbVidOffset_1__SHIFT
- PM_FUSES_42__VddNbVidOffset_2_MASK
- PM_FUSES_42__VddNbVidOffset_2__SHIFT
- PM_FUSES_42__VddNbVid_4_MASK
- PM_FUSES_42__VddNbVid_4__SHIFT
- PM_FUSES_43__BapmDisable_MASK
- PM_FUSES_43__BapmDisable__SHIFT
- PM_FUSES_43__CoreTdpLimit0_MASK
- PM_FUSES_43__CoreTdpLimit0__SHIFT
- PM_FUSES_43__VddNbVidOffset_3_MASK
- PM_FUSES_43__VddNbVidOffset_3__SHIFT
- PM_FUSES_43__VddNbVidOffset_4_MASK
- PM_FUSES_43__VddNbVidOffset_4__SHIFT
- PM_FUSES_44__LpmlL2_0_MASK
- PM_FUSES_44__LpmlL2_0__SHIFT
- PM_FUSES_44__LpmlL2_1_MASK
- PM_FUSES_44__LpmlL2_1__SHIFT
- PM_FUSES_44__LpmlL2_2_MASK
- PM_FUSES_44__LpmlL2_2__SHIFT
- PM_FUSES_44__LpmlL2_3_MASK
- PM_FUSES_44__LpmlL2_3__SHIFT
- PM_FUSES_45__LpmlL2_4_MASK
- PM_FUSES_45__LpmlL2_4__SHIFT
- PM_FUSES_45__LpmlL2_5_MASK
- PM_FUSES_45__LpmlL2_5__SHIFT
- PM_FUSES_45__LpmlL2_6_MASK
- PM_FUSES_45__LpmlL2_6__SHIFT
- PM_FUSES_45__LpmlL2_7_MASK
- PM_FUSES_45__LpmlL2_7__SHIFT
- PM_FUSES_46__BaseCpcTdpLimit1_MASK
- PM_FUSES_46__BaseCpcTdpLimit1__SHIFT
- PM_FUSES_46__BaseCpcTdpLimit2_MASK
- PM_FUSES_46__BaseCpcTdpLimit2__SHIFT
- PM_FUSES_46__BaseCpcTdpLimit_MASK
- PM_FUSES_46__BaseCpcTdpLimit__SHIFT
- PM_FUSES_46__CoolPdmTc_MASK
- PM_FUSES_46__CoolPdmTc__SHIFT
- PM_FUSES_47__CoolPdmThr1_MASK
- PM_FUSES_47__CoolPdmThr1__SHIFT
- PM_FUSES_47__CoolPdmThr2_MASK
- PM_FUSES_47__CoolPdmThr2__SHIFT
- PM_FUSES_47__GpuPdmTc_MASK
- PM_FUSES_47__GpuPdmTc__SHIFT
- PM_FUSES_47__HeatPdmTc_MASK
- PM_FUSES_47__HeatPdmTc__SHIFT
- PM_FUSES_48__GpuActThr_MASK
- PM_FUSES_48__GpuActThr__SHIFT
- PM_FUSES_48__HeatPdmThr1_MASK
- PM_FUSES_48__HeatPdmThr1__SHIFT
- PM_FUSES_48__HeatPdmThr2_MASK
- PM_FUSES_48__HeatPdmThr2__SHIFT
- PM_FUSES_48__PkgPwr_MAWt_MASK
- PM_FUSES_48__PkgPwr_MAWt__SHIFT
- PM_FUSES_49__GpuPdmMult_MASK
- PM_FUSES_49__GpuPdmMult__SHIFT
- PM_FUSES_49__SocketTdp_MASK
- PM_FUSES_49__SocketTdp__SHIFT
- PM_FUSES_4__BapmVddCVidLoSidd_4_MASK
- PM_FUSES_4__BapmVddCVidLoSidd_4__SHIFT
- PM_FUSES_4__BapmVddCVidLoSidd_5_MASK
- PM_FUSES_4__BapmVddCVidLoSidd_5__SHIFT
- PM_FUSES_4__BapmVddCVidLoSidd_6_MASK
- PM_FUSES_4__BapmVddCVidLoSidd_6__SHIFT
- PM_FUSES_4__BapmVddCVidLoSidd_7_MASK
- PM_FUSES_4__BapmVddCVidLoSidd_7__SHIFT
- PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK
- PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT
- PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK
- PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT
- PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK
- PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT
- PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK
- PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT
- PM_FUSES_4__LPMLTemperatureScaler_0_MASK
- PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT
- PM_FUSES_4__LPMLTemperatureScaler_1_MASK
- PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT
- PM_FUSES_4__LPMLTemperatureScaler_2_MASK
- PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT
- PM_FUSES_4__LPMLTemperatureScaler_3_MASK
- PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT
- PM_FUSES_50__NumBoostStates_MASK
- PM_FUSES_50__NumBoostStates__SHIFT
- PM_FUSES_50__Reserved1_MASK
- PM_FUSES_50__Reserved1__SHIFT
- PM_FUSES_50__Reserved2_MASK
- PM_FUSES_50__Reserved2__SHIFT
- PM_FUSES_51__FUSE_DATA_MASK
- PM_FUSES_51__FUSE_DATA__SHIFT
- PM_FUSES_52__FUSE_DATA_MASK
- PM_FUSES_52__FUSE_DATA__SHIFT
- PM_FUSES_53__FUSE_DATA_MASK
- PM_FUSES_53__FUSE_DATA__SHIFT
- PM_FUSES_54__FUSE_DATA_MASK
- PM_FUSES_54__FUSE_DATA__SHIFT
- PM_FUSES_55__FUSE_DATA_MASK
- PM_FUSES_55__FUSE_DATA__SHIFT
- PM_FUSES_56__FUSE_DATA_MASK
- PM_FUSES_56__FUSE_DATA__SHIFT
- PM_FUSES_57__FUSE_DATA_MASK
- PM_FUSES_57__FUSE_DATA__SHIFT
- PM_FUSES_58__FUSE_DATA_MASK
- PM_FUSES_58__FUSE_DATA__SHIFT
- PM_FUSES_59__FUSE_DATA_MASK
- PM_FUSES_59__FUSE_DATA__SHIFT
- PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK
- PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT
- PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK
- PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT
- PM_FUSES_5__CpuIdModel_MASK
- PM_FUSES_5__CpuIdModel__SHIFT
- PM_FUSES_5__LPMLTemperatureScaler_4_MASK
- PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT
- PM_FUSES_5__LPMLTemperatureScaler_5_MASK
- PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT
- PM_FUSES_5__LPMLTemperatureScaler_6_MASK
- PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT
- PM_FUSES_5__LPMLTemperatureScaler_7_MASK
- PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT
- PM_FUSES_5__SviLoadLineEn_MASK
- PM_FUSES_5__SviLoadLineEn__SHIFT
- PM_FUSES_5__VddCVid_0_MASK
- PM_FUSES_5__VddCVid_0__SHIFT
- PM_FUSES_5__VddCVid_1_MASK
- PM_FUSES_5__VddCVid_1__SHIFT
- PM_FUSES_5__VddCVid_2_MASK
- PM_FUSES_5__VddCVid_2__SHIFT
- PM_FUSES_5__VddCVid_3_MASK
- PM_FUSES_5__VddCVid_3__SHIFT
- PM_FUSES_60__FUSE_DATA_MASK
- PM_FUSES_60__FUSE_DATA__SHIFT
- PM_FUSES_61__FUSE_DATA_MASK
- PM_FUSES_61__FUSE_DATA__SHIFT
- PM_FUSES_62__FUSE_DATA_MASK
- PM_FUSES_62__FUSE_DATA__SHIFT
- PM_FUSES_63__FUSE_DATA_MASK
- PM_FUSES_63__FUSE_DATA__SHIFT
- PM_FUSES_64__FUSE_DATA_MASK
- PM_FUSES_64__FUSE_DATA__SHIFT
- PM_FUSES_65__FUSE_DATA_MASK
- PM_FUSES_65__FUSE_DATA__SHIFT
- PM_FUSES_6__LPMLTemperatureScaler_10_MASK
- PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT
- PM_FUSES_6__LPMLTemperatureScaler_11_MASK
- PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT
- PM_FUSES_6__LPMLTemperatureScaler_8_MASK
- PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT
- PM_FUSES_6__LPMLTemperatureScaler_9_MASK
- PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT
- PM_FUSES_6__SviLoadLineTrimVddNb_MASK
- PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT
- PM_FUSES_6__SviLoadLineTrimVdd_MASK
- PM_FUSES_6__SviLoadLineTrimVdd__SHIFT
- PM_FUSES_6__SviLoadLineVddNb_MASK
- PM_FUSES_6__SviLoadLineVddNb__SHIFT
- PM_FUSES_6__SviLoadLineVdd_MASK
- PM_FUSES_6__SviLoadLineVdd__SHIFT
- PM_FUSES_6__VddCVid_4_MASK
- PM_FUSES_6__VddCVid_4__SHIFT
- PM_FUSES_6__VddCVid_5_MASK
- PM_FUSES_6__VddCVid_5__SHIFT
- PM_FUSES_6__VddCVid_6_MASK
- PM_FUSES_6__VddCVid_6__SHIFT
- PM_FUSES_6__VddCVid_7_MASK
- PM_FUSES_6__VddCVid_7__SHIFT
- PM_FUSES_7__BAPMTI_TjOffset_0_MASK
- PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT
- PM_FUSES_7__LPMLTemperatureScaler_12_MASK
- PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT
- PM_FUSES_7__LPMLTemperatureScaler_13_MASK
- PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT
- PM_FUSES_7__LPMLTemperatureScaler_14_MASK
- PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT
- PM_FUSES_7__LPMLTemperatureScaler_15_MASK
- PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT
- PM_FUSES_7__SviLoadLineEn_MASK
- PM_FUSES_7__SviLoadLineEn__SHIFT
- PM_FUSES_7__SviLoadLineOffsetVddC_MASK
- PM_FUSES_7__SviLoadLineOffsetVddC__SHIFT
- PM_FUSES_7__SviLoadLineOffsetVddNb_MASK
- PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT
- PM_FUSES_7__SviLoadLineOffsetVdd_MASK
- PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT
- PM_FUSES_7__SviLoadLineTrimVddC_MASK
- PM_FUSES_7__SviLoadLineTrimVddC__SHIFT
- PM_FUSES_7__SviLoadLineVddC_MASK
- PM_FUSES_7__SviLoadLineVddC__SHIFT
- PM_FUSES_8__BAPMTI_TjOffset_1_MASK
- PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT
- PM_FUSES_8__BAPMTI_TjOffset_2_MASK
- PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT
- PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK
- PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT
- PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK
- PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT
- PM_FUSES_8__TDC_MAWt_MASK
- PM_FUSES_8__TDC_MAWt__SHIFT
- PM_FUSES_8__TDC_VDDC_PkgLimit_MASK
- PM_FUSES_8__TDC_VDDC_PkgLimit__SHIFT
- PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc_MASK
- PM_FUSES_8__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT
- PM_FUSES_9__BAPMTI_TjHyst_0_MASK
- PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT
- PM_FUSES_9__BAPMTI_TjHyst_1_MASK
- PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT
- PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK
- PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT
- PM_FUSES_9__LPMLTemperatureMax_MASK
- PM_FUSES_9__LPMLTemperatureMax__SHIFT
- PM_FUSES_9__LPMLTemperatureMin_MASK
- PM_FUSES_9__LPMLTemperatureMin__SHIFT
- PM_FUSES_9__Reserved6_MASK
- PM_FUSES_9__Reserved6__SHIFT
- PM_FUSES_9__Reserved_MASK
- PM_FUSES_9__Reserved__SHIFT
- PM_FUSES_9__TdcWaterfallCtl_MASK
- PM_FUSES_9__TdcWaterfallCtl__SHIFT
- PM_GET_API_VERSION
- PM_GET_CHIPID
- PM_GET_TRUSTZONE_VERSION
- PM_GNRIC
- PM_GRAFX
- PM_GRS
- PM_GRS_MSK
- PM_GRS_SH
- PM_H264RSTN
- PM_HDMI
- PM_HDMI_CTRLEN
- PM_HDMI_LDOPD
- PM_HDMI_RSTDR
- PM_HIBERNATION_PREPARE
- PM_HINT_FULLON
- PM_HINT_NORMAL
- PM_HS_CFG_OFFSET
- PM_HS_CFG_REG
- PM_HS_CFG_REG_MASK
- PM_HS_CFG_REG_MASK_SUPPORT
- PM_HS_CFG_REG_OFFSET_CIM
- PM_HS_CFG_REG_OFFSET_CRYPTO
- PM_HS_CFG_REG_OFFSET_DMC
- PM_HS_CFG_REG_OFFSET_GDMA
- PM_HS_CFG_REG_OFFSET_GPIO
- PM_HS_CFG_REG_OFFSET_GPU
- PM_HS_CFG_REG_OFFSET_HCIE
- PM_HS_CFG_REG_OFFSET_I2S
- PM_HS_CFG_REG_OFFSET_LCDC
- PM_HS_CFG_REG_OFFSET_PCIE0
- PM_HS_CFG_REG_OFFSET_PCIE1
- PM_HS_CFG_REG_OFFSET_RAID
- PM_HS_CFG_REG_OFFSET_RTC
- PM_HS_CFG_REG_OFFSET_SATA
- PM_HS_CFG_REG_OFFSET_SDIO
- PM_HS_CFG_REG_OFFSET_SMC_NFI
- PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S
- PM_HS_CFG_REG_OFFSET_SWITCH
- PM_HS_CFG_REG_OFFSET_TIMER
- PM_HS_CFG_REG_OFFSET_UART1
- PM_HS_CFG_REG_OFFSET_UART2
- PM_HS_CFG_REG_OFFSET_UART3
- PM_HS_CFG_REG_OFFSET_USB_HOST
- PM_HS_CFG_REG_OFFSET_USB_OTG
- PM_HUGE_MASK
- PM_H_INCLUDED
- PM_ICACHE_MISS
- PM_ICS
- PM_ICS_IE
- PM_ICS_INT_STATUS
- PM_ICS_IP
- PM_ICS_SW_INT_STS
- PM_IDU
- PM_IFU
- PM_IMAGE
- PM_INDEX
- PM_INFO_DDR_TYPE_OFFSET
- PM_INFO_MMDC_IO_NUM_OFFSET
- PM_INFO_MMDC_IO_VAL_OFFSET
- PM_INFO_MX6Q_CCM_P_OFFSET
- PM_INFO_MX6Q_CCM_V_OFFSET
- PM_INFO_MX6Q_GPC_P_OFFSET
- PM_INFO_MX6Q_GPC_V_OFFSET
- PM_INFO_MX6Q_IOMUXC_P_OFFSET
- PM_INFO_MX6Q_IOMUXC_V_OFFSET
- PM_INFO_MX6Q_L2_P_OFFSET
- PM_INFO_MX6Q_L2_V_OFFSET
- PM_INFO_MX6Q_MMDC_P_OFFSET
- PM_INFO_MX6Q_MMDC_V_OFFSET
- PM_INFO_MX6Q_SRC_P_OFFSET
- PM_INFO_MX6Q_SRC_V_OFFSET
- PM_INFO_PBASE_OFFSET
- PM_INFO_PM_INFO_SIZE_OFFSET
- PM_INFO_RESUME_ADDR_OFFSET
- PM_INITIATE
- PM_INITIATE_FAIL
- PM_INITIATE_SUCCESS
- PM_INIT_SUSPEND_CB
- PM_INRUSH_10_MA
- PM_INRUSH_20_MA
- PM_INRUSH_3_5_MA
- PM_INRUSH_5_MA
- PM_INRUSH_MASK
- PM_INRUSH_SHIFT
- PM_INST_CMPL
- PM_INTERVAL_CNTL_0__LCLK_DPM_MASK
- PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT
- PM_INTERVAL_CNTL_0__LOADLINE_MASK
- PM_INTERVAL_CNTL_0__LOADLINE__SHIFT
- PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK
- PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT
- PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK
- PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT
- PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK
- PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT
- PM_INTERVAL_CNTL_1__NB_DPM_MASK
- PM_INTERVAL_CNTL_1__NB_DPM__SHIFT
- PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK
- PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT
- PM_INTERVAL_CNTL_1__TDP_CNTL_MASK
- PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT
- PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK
- PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT
- PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK
- PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT
- PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK
- PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT
- PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK
- PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT
- PM_IOCTL
- PM_IRQF_BITS_MASK
- PM_IRQF_BITS_SHIFT
- PM_IRQF_CLR
- PM_IRQF_LVL_SEL
- PM_IRQF_MASK_ALL
- PM_IRQF_MASK_FE
- PM_IRQF_MASK_RE
- PM_IRQF_WRITE
- PM_ISFUNC
- PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND2_SIGNAL_GROUP_NUMBER1
- PM_ISLAND2_SIGNAL_GROUP_NUMBER2
- PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER
- PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER
- PM_ISPOW
- PM_ISPRSTN
- PM_ISU
- PM_ISU0
- PM_ISU0_ALT
- PM_ISU1
- PM_ITB_MISS
- PM_I_CNTL_1
- PM_L1_1_EN
- PM_L1_1_EN_MASK
- PM_L1_2_EN
- PM_L1_2_EN_MASK
- PM_L2SEL_MSK
- PM_L2SEL_SH
- PM_LANWake
- PM_LAST
- PM_LASTUNIT
- PM_LEVEL_ENC
- PM_LEVEL_INDEX
- PM_LEVEL_PDE
- PM_LEVEL_SHIFT
- PM_LEVEL_SIZE
- PM_LGO_COLLISION_SEND_LAU
- PM_LLA
- PM_LLAV
- PM_LOAD_STORE
- PM_LSU0
- PM_LSU1
- PM_LSU1L
- PM_LSU1U
- PM_LUT_ADDR
- PM_LUT_DATA
- PM_LUT_PGM
- PM_LUT_SEL
- PM_LWPTN
- PM_LinkUp
- PM_LongWF
- PM_MANUAL
- PM_MAP_4k
- PM_MAP_MASK
- PM_MAX
- PM_MAX_LENGTH
- PM_MAX_MTSLOT
- PM_MEMREP
- PM_METHOD_DPM
- PM_METHOD_DYNPM
- PM_METHOD_PROFILE
- PM_MIN_S3_WIDTH_TIMER_BYPASS
- PM_MISPREDICT
- PM_MMAP_EXCLUSIVE
- PM_MOBILE
- PM_MRDONE
- PM_Magic
- PM_Mask
- PM_NONE
- PM_NORMAL
- PM_NOTIFY_CB
- PM_NSTATS
- PM_NUM_COUNTERS
- PM_OFF
- PM_OFFSET
- PM_OK_BITS
- PM_OMAP4_CPU_OSWR_DISABLE
- PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD
- PM_OPS
- PM_OUT_OF_DATA_SPACE
- PM_OUT_OF_METADATA_SPACE
- PM_PADS0
- PM_PADS2
- PM_PADS3
- PM_PADS4
- PM_PADS5
- PM_PADS6
- PM_PASSWORD
- PM_PCGR
- PM_PCGR_BCLK64DDR
- PM_PCGR_BCLK64VGA
- PM_PCGR_BCLKDDR
- PM_PCGR_BCLKDMAC
- PM_PCGR_BCLKH264D
- PM_PCGR_BCLKH264E
- PM_PCGR_BCLKMME
- PM_PCGR_BCLKNAND
- PM_PCGR_BCLKPCI
- PM_PCGR_BCLKUMAL
- PM_PCGR_BCLKUSB
- PM_PCGR_BCLKVGA
- PM_PCGR_GECLK
- PM_PCGR_HDCLK
- PM_PCGR_HECLK
- PM_PCGR_NANDCLK
- PM_PCGR_PCICLK
- PM_PCGR_SATACLK
- PM_PCGR_VECLK
- PM_PCGR_VGACLK
- PM_PEER
- PM_PERFORMANCE_SERVER
- PM_PERIRSTN
- PM_PER_MEMORIES_ERRATUM_i582
- PM_PFRAME
- PM_PFRAME_BITS
- PM_PFRAME_MASK
- PM_PGCR
- PM_PGSR
- PM_PLLDDRCFG
- PM_PLLDDRSTATUS
- PM_PLLDFCDONE
- PM_PLLDFCDONE_DDRDFC
- PM_PLLDFCDONE_SYSDFC
- PM_PLLDFCDONE_VGADFC
- PM_PLLSYSCFG
- PM_PLLSYSSTATUS
- PM_PLLVGACFG
- PM_PLLVGASTATUS
- PM_PLL_CPU_SEL
- PM_PLL_HM_PD_CTRL_REG
- PM_PLL_HM_PD_CTRL_REG_MASK
- PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S
- PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD
- PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD
- PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII
- PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB
- PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0
- PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1
- PM_PLL_HM_PD_OFFSET
- PM_PLL_LCD_I2S_CTRL_OFFSET
- PM_PLL_LCD_I2S_CTRL_REG
- PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV
- PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M
- PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P
- PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S
- PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL
- PM_PLL_PWRDOWN
- PM_PMCR
- PM_PMCR_CFBDDR
- PM_PMCR_CFBDIVBCLK
- PM_PMCR_CFBSYS
- PM_PMCR_CFBVGA
- PM_PMCR_IFB
- PM_PMCR_SFB
- PM_PMCSEL_MSK
- PM_PMC_MSK
- PM_PMC_MSKS
- PM_PMC_SH
- PM_PME
- PM_PM_INIT_FINALIZE
- PM_PORT_FLAGS
- PM_PORT_MASK
- PM_PORT_SET
- PM_POST_HIBERNATION
- PM_POST_RESTORE
- PM_POST_SUSPEND
- PM_POWOK
- PM_POWUP
- PM_PPCR
- PM_PREPWSTST_CORE_P
- PM_PRESENT
- PM_PROC
- PM_PROFILE_AUTO
- PM_PROFILE_DEFAULT
- PM_PROFILE_DEFAULT_IDX
- PM_PROFILE_HIGH
- PM_PROFILE_HIGH_MH_IDX
- PM_PROFILE_HIGH_SH_IDX
- PM_PROFILE_LOW
- PM_PROFILE_LOW_MH_IDX
- PM_PROFILE_LOW_SH_IDX
- PM_PROFILE_MAX
- PM_PROFILE_MID
- PM_PROFILE_MID_MH_IDX
- PM_PROFILE_MID_SH_IDX
- PM_PTE_LEVEL
- PM_PWER
- PM_PWER_GPIOHIGH
- PM_PWER_RTC
- PM_PWRDN_PPLL
- PM_PWR_DOWN
- PM_PWR_STA_OFFSET
- PM_PWR_STA_REG
- PM_PWR_STA_REG_REG_MASK
- PM_PWR_STA_REG_REG_OFFSET_CIM
- PM_PWR_STA_REG_REG_OFFSET_CRYPTO
- PM_PWR_STA_REG_REG_OFFSET_DMC
- PM_PWR_STA_REG_REG_OFFSET_GDMA
- PM_PWR_STA_REG_REG_OFFSET_GPIO
- PM_PWR_STA_REG_REG_OFFSET_GPU
- PM_PWR_STA_REG_REG_OFFSET_HCIE
- PM_PWR_STA_REG_REG_OFFSET_I2S
- PM_PWR_STA_REG_REG_OFFSET_LCDC
- PM_PWR_STA_REG_REG_OFFSET_PCIE0
- PM_PWR_STA_REG_REG_OFFSET_PCIE1
- PM_PWR_STA_REG_REG_OFFSET_RAID
- PM_PWR_STA_REG_REG_OFFSET_RTC
- PM_PWR_STA_REG_REG_OFFSET_SATA
- PM_PWR_STA_REG_REG_OFFSET_SDIO
- PM_PWR_STA_REG_REG_OFFSET_SMC_NFI
- PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S
- PM_PWR_STA_REG_REG_OFFSET_SWITCH
- PM_PWR_STA_REG_REG_OFFSET_TIMER
- PM_PWR_STA_REG_REG_OFFSET_UART1
- PM_PWR_STA_REG_REG_OFFSET_UART2
- PM_PWR_STA_REG_REG_OFFSET_UART3
- PM_PWR_STA_REG_REG_OFFSET_USB_HOST
- PM_PWR_STA_REG_REG_OFFSET_USB_OTG
- PM_PWSTCTRL_MPU_P
- PM_PXBG
- PM_PXLDO
- PM_QID_CLOCK_GET_ATTRIBUTES
- PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS
- PM_QID_CLOCK_GET_NAME
- PM_QID_CLOCK_GET_NUM_CLOCKS
- PM_QID_CLOCK_GET_PARENTS
- PM_QID_CLOCK_GET_TOPOLOGY
- PM_QID_INVALID
- PM_QOS_ADD_REQ
- PM_QOS_CONFIG_OFFSET
- PM_QOS_CPU_DMA_LATENCY
- PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE
- PM_QOS_DEFAULT_VALUE
- PM_QOS_FLAGS_ALL
- PM_QOS_FLAGS_NONE
- PM_QOS_FLAGS_SOME
- PM_QOS_FLAGS_UNDEFINED
- PM_QOS_FLAG_NO_POWER_OFF
- PM_QOS_INFO_OFFSET
- PM_QOS_LATENCY_ANY
- PM_QOS_LATENCY_ANY_NS
- PM_QOS_LATENCY_TOLERANCE_DEFAULT_VALUE
- PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT
- PM_QOS_MAX
- PM_QOS_MIN
- PM_QOS_NUM_CLASSES
- PM_QOS_REMOVE_REQ
- PM_QOS_RESERVED
- PM_QOS_RESUME_LATENCY_DEFAULT_VALUE
- PM_QOS_RESUME_LATENCY_NO_CONSTRAINT
- PM_QOS_RESUME_LATENCY_NO_CONSTRAINT_NS
- PM_QOS_SUM
- PM_QOS_UNITIALIZED
- PM_QOS_UPDATE_REQ
- PM_QUERY_DATA
- PM_READ
- PM_READ_ONLY
- PM_REGULAT_CTRL_REG
- PM_REG_
- PM_RELEASE_NODE
- PM_REPLAY
- PM_REQUEST_NODE
- PM_RESET_ACTION_ASSERT
- PM_RESET_ACTION_PULSE
- PM_RESET_ACTION_RELEASE
- PM_RESET_ASSERT
- PM_RESET_GET_STATUS
- PM_RESTORE_PREPARE
- PM_RSTC
- PM_RSTC_RESET
- PM_RSTC_WRCFG_CLR
- PM_RSTC_WRCFG_FULL_RESET
- PM_RSTC_WRCFG_SET
- PM_RSTS
- PM_RSTS_HADWRH_SET
- PM_RSTS_RASPBERRYPI_HALT
- PM_RTA_ERRATUM_i608
- PM_RX_BASE_ADDR
- PM_RX_DBG_CTRL_A
- PM_RX_DBG_DATA_A
- PM_RX_DBG_STAT_MSB_A
- PM_RX_F
- PM_RX_INT_CAUSE_A
- PM_RX_S
- PM_RX_STAT_CONFIG_A
- PM_RX_STAT_COUNT_A
- PM_RX_STAT_LSB_A
- PM_RX_V
- PM_Radio_Off
- PM_S1
- PM_S2_COMMAND
- PM_S3
- PM_SDA10
- PM_SDCE
- PM_SDCLK
- PM_SDRC_WAKEUP_ERRATUM_i583
- PM_SET_REQUIREMENT
- PM_SET_SUSPEND_MODE
- PM_SIG_GROUP_MFC_MAX
- PM_SIG_GROUP_SPU
- PM_SIG_GROUP_SPU_EVENT
- PM_SIG_GROUP_SPU_TRIGGER
- PM_SIP_SVC
- PM_SLEEP_MODE_NR
- PM_SLEEP_MODE_PC
- PM_SLEEP_MODE_RET
- PM_SLEEP_MODE_SPC
- PM_SLEEP_MODE_STBY
- PM_SLEEP_NOTIFICATION
- PM_SMPS
- PM_SOFT_DIRTY
- PM_SOFT_RST_OFFSET
- PM_SOFT_RST_REG
- PM_SOFT_RST_REG_MASK
- PM_SOFT_RST_REG_OFFST_CIM
- PM_SOFT_RST_REG_OFFST_CPU0
- PM_SOFT_RST_REG_OFFST_CPU1
- PM_SOFT_RST_REG_OFFST_CRYPTO
- PM_SOFT_RST_REG_OFFST_DMC
- PM_SOFT_RST_REG_OFFST_GDMA
- PM_SOFT_RST_REG_OFFST_GLOBAL
- PM_SOFT_RST_REG_OFFST_GPIO
- PM_SOFT_RST_REG_OFFST_GPU
- PM_SOFT_RST_REG_OFFST_HCIE
- PM_SOFT_RST_REG_OFFST_I2S
- PM_SOFT_RST_REG_OFFST_LCDC
- PM_SOFT_RST_REG_OFFST_PCIE
- PM_SOFT_RST_REG_OFFST_RAID
- PM_SOFT_RST_REG_OFFST_RTC
- PM_SOFT_RST_REG_OFFST_SATA
- PM_SOFT_RST_REG_OFFST_SDIO
- PM_SOFT_RST_REG_OFFST_SMC_NFI
- PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C
- PM_SOFT_RST_REG_OFFST_SWITCH
- PM_SOFT_RST_REG_OFFST_TIMER
- PM_SOFT_RST_REG_OFFST_UART1
- PM_SOFT_RST_REG_OFFST_UART2
- PM_SOFT_RST_REG_OFFST_UART3
- PM_SOFT_RST_REG_OFFST_USB_HOST
- PM_SOFT_RST_REG_OFFST_USB_OTG
- PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG
- PM_SOHO_SERVER
- PM_SPARER
- PM_SPAREW
- PM_SPCSEL_MSK
- PM_SPCSEL_SH
- PM_SPU_EVENT_SIGNAL_GROUP_NUMBER
- PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER
- PM_SSC
- PM_SSS
- PM_STALLED
- PM_STATE_SIZE
- PM_STATUS
- PM_STS
- PM_STS_BUSY
- PM_SUBUNIT_MSK
- PM_SUBUNIT_MSKS
- PM_SUBUNIT_SH
- PM_SUSPEND
- PM_SUSPEND_FLAG_FW_RESUME
- PM_SUSPEND_FLAG_FW_SUSPEND
- PM_SUSPEND_FLAG_NO_PLATFORM
- PM_SUSPEND_MAX
- PM_SUSPEND_MEM
- PM_SUSPEND_MIN
- PM_SUSPEND_MODE_FIRST
- PM_SUSPEND_MODE_POWER_OFF
- PM_SUSPEND_MODE_STD
- PM_SUSPEND_ON
- PM_SUSPEND_PREPARE
- PM_SUSPEND_STANDBY
- PM_SUSPEND_TO_IDLE
- PM_SWAP
- PM_SWAP_OFFSET
- PM_SWRESET
- PM_SWRESET_GEDIV
- PM_SWRESET_USB
- PM_SWRESET_VGADIV
- PM_SYS_CLK_CTRL_OFFSET
- PM_Sleep
- PM_Snooze
- PM_TABLET
- PM_TAKEN
- PM_THRESH_MSK
- PM_THRESH_SH
- PM_THRMULT_MSKS
- PM_TP
- PM_TRACE_H
- PM_TRANSMIT_DISABLE
- PM_TRANSMIT_ENABLE
- PM_TREE
- PM_TX_DBG_CTRL_A
- PM_TX_DBG_DATA_A
- PM_TX_DBG_STAT_MSB_A
- PM_TX_F
- PM_TX_INT_CAUSE_A
- PM_TX_S
- PM_TX_STAT_CONFIG_A
- PM_TX_STAT_COUNT_A
- PM_TX_STAT_LSB_A
- PM_TX_V
- PM_U1_AUTO_EXIT
- PM_U1_ENABLE
- PM_U2_AUTO_EXIT
- PM_U2_ENABLE
- PM_U3_AUTO_EXIT
- PM_UNALIGNED
- PM_UNIT_MSK
- PM_UNIT_MSKS
- PM_UNIT_SH
- PM_UNSPECIFIED
- PM_USB
- PM_USB_CTRLEN
- PM_USE_CPU_RDY
- PM_V3DRSTN
- PM_VEBOX_CS_ERROR_INTERRUPT
- PM_VEBOX_USER_INTERRUPT
- PM_VGA_DSP_CONFIG
- PM_VGA_DSP_ON_OFF
- PM_VPU
- PM_WAKEUP_TIME
- PM_WAKE_EN
- PM_WARM_BOOT
- PM_WARM_CONFIG
- PM_WDOG
- PM_WDOG_TIME_SET
- PM_WDT_CTRL_REG
- PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY
- PM_WKC
- PM_WKDEP
- PM_WKEN
- PM_WKEN1
- PM_WKS
- PM_WKST
- PM_WKST1
- PM_WORKSTATION
- PM_WRITE
- PM_WU_CTRL0_REG
- PM_WU_CTRL1_REG
- PM_WakeUp
- PM_XOSC
- PN
- PN0_DATA
- PN0_FN
- PN0_IN
- PN0_OUT
- PN1_DATA
- PN1_FN
- PN1_IN
- PN1_OUT
- PN26G0XA_STATUS_ECC_1_7_CORRECTED
- PN26G0XA_STATUS_ECC_8_CORRECTED
- PN26G0XA_STATUS_ECC_BITMASK
- PN26G0XA_STATUS_ECC_ERRORED
- PN26G0XA_STATUS_ECC_NONE_DETECTED
- PN2_DATA
- PN2_DMA_FF_UNDERFLOW
- PN2_DMA_FF_UNDERFLOW_ENA
- PN2_DMA_FF_UNDERFLOW_ENA_MASK
- PN2_DMA_FF_UNDERFLOW_MASK
- PN2_DMA_FRAME_IRQ0
- PN2_DMA_FRAME_IRQ0_ENA
- PN2_DMA_FRAME_IRQ0_ENA_MASK
- PN2_DMA_FRAME_IRQ0_MASK
- PN2_DMA_FRAME_IRQ1
- PN2_DMA_FRAME_IRQ1_ENA
- PN2_DMA_FRAME_IRQ1_ENA_MASK
- PN2_DMA_FRAME_IRQ1_MASK
- PN2_FN
- PN2_GRA_FF_UNDERFLOW
- PN2_GRA_FF_UNDERFLOW_ENA
- PN2_GRA_FF_UNDERFLOW_ENA_MASK
- PN2_GRA_FF_UNDERFLOW_MASK
- PN2_GRA_FRAME_IRQ0
- PN2_GRA_FRAME_IRQ0_ENA
- PN2_GRA_FRAME_IRQ0_ENA_MASK
- PN2_GRA_FRAME_IRQ0_MASK
- PN2_GRA_FRAME_IRQ1
- PN2_GRA_FRAME_IRQ1_ENA
- PN2_GRA_FRAME_IRQ1_ENA_MASK
- PN2_GRA_FRAME_IRQ1_MASK
- PN2_IN
- PN2_IOPAD_CONTROL
- PN2_LCD_DMAZM_HPXL_VLN
- PN2_LCD_DMA_HPXL_VLN
- PN2_LCD_DMA_OVSA_HPXL_VLN
- PN2_LCD_DMA_PITCH_UV
- PN2_LCD_DMA_PITCH_YC
- PN2_LCD_DMA_START_ADDR_C0
- PN2_LCD_DMA_START_ADDR_C1
- PN2_LCD_DMA_START_ADDR_U0
- PN2_LCD_DMA_START_ADDR_U1
- PN2_LCD_DMA_START_ADDR_V0
- PN2_LCD_DMA_START_ADDR_V1
- PN2_LCD_DMA_START_ADDR_Y0
- PN2_LCD_DMA_START_ADDR_Y1
- PN2_LCD_GRAZM_HPXL_VLN
- PN2_LCD_GRA_CUTHPXL
- PN2_LCD_GRA_CUTVLN
- PN2_LCD_GRA_HPXL_VLN
- PN2_LCD_GRA_OVSA_HPXL_VLN
- PN2_LCD_GRA_PITCH
- PN2_LCD_GRA_START_ADDR0
- PN2_LCD_GRA_START_ADDR1
- PN2_LCD_HWC_HPXL_VLN
- PN2_LCD_HWC_OVSA_HPXL_VLN
- PN2_OUT
- PN2_SYNC_IRQ_ENA_MASK
- PN2_SYNC_IRQ_MASK
- PN2_VSYNC_IRQ
- PN2_VSYNC_IRQ_ENA
- PN3_DATA
- PN3_FN
- PN3_IN
- PN3_OUT
- PN4_DATA
- PN4_FN
- PN4_IN
- PN4_OUT
- PN533_ACR122_FRAME_MAX_PAYLOAD_LEN
- PN533_ACR122_PC_TO_RDR_ESCAPE
- PN533_ACR122_PC_TO_RDR_ICCPOWERON
- PN533_ACR122_RDR_TO_PC_ESCAPE
- PN533_ACR122_RX_FRAME_HEADER_LEN
- PN533_ACR122_RX_FRAME_TAIL_LEN
- PN533_ACR122_TX_FRAME_HEADER_LEN
- PN533_ACR122_TX_FRAME_TAIL_LEN
- PN533_ALL_PROTOCOLS
- PN533_CFGITEM_MAX_RETRIES
- PN533_CFGITEM_PASORI
- PN533_CFGITEM_RF_FIELD
- PN533_CFGITEM_RF_FIELD_AUTO_RFCA
- PN533_CFGITEM_RF_FIELD_OFF
- PN533_CFGITEM_RF_FIELD_ON
- PN533_CFGITEM_TIMING
- PN533_CMD_DATAEXCH_DATA_MAXLEN
- PN533_CMD_DATAEXCH_HEAD_LEN
- PN533_CMD_DATAFRAME_MAXLEN
- PN533_CMD_GET_FIRMWARE_VERSION
- PN533_CMD_IN_ATR
- PN533_CMD_IN_COMM_THRU
- PN533_CMD_IN_DATA_EXCHANGE
- PN533_CMD_IN_JUMP_FOR_DEP
- PN533_CMD_IN_LIST_PASSIVE_TARGET
- PN533_CMD_IN_RELEASE
- PN533_CMD_MI_MASK
- PN533_CMD_RESPONSE
- PN533_CMD_RET_MASK
- PN533_CMD_RET_SUCCESS
- PN533_CMD_RF_CONFIGURATION
- PN533_CMD_SAM_CONFIGURATION
- PN533_CMD_TG_GET_DATA
- PN533_CMD_TG_INIT_AS_TARGET
- PN533_CMD_TG_SET_DATA
- PN533_CMD_TG_SET_META_DATA
- PN533_CMD_UNDEF
- PN533_CONFIG_MAX_RETRIES_ENDLESS
- PN533_CONFIG_MAX_RETRIES_NO_RETRY
- PN533_CONFIG_TIMING_102
- PN533_CONFIG_TIMING_204
- PN533_CONFIG_TIMING_409
- PN533_CONFIG_TIMING_819
- PN533_DEVICE_ACR122U
- PN533_DEVICE_PASORI
- PN533_DEVICE_PN532
- PN533_DEVICE_STD
- PN533_EXT_FRAME_CHECKSUM
- PN533_EXT_FRAME_HEADER_LEN
- PN533_FELICA_OPC_SENSF_REQ
- PN533_FELICA_OPC_SENSF_RES
- PN533_FELICA_SENSF_NFCID2_DEP_B1
- PN533_FELICA_SENSF_NFCID2_DEP_B2
- PN533_FELICA_SENSF_RC_ADVANCED_PROTOCOL
- PN533_FELICA_SENSF_RC_NO_SYSTEM_CODE
- PN533_FELICA_SENSF_RC_SYSTEM_CODE
- PN533_FELICA_SENSF_SC_ALL
- PN533_FRAME_CMD
- PN533_I2C_DRIVER_NAME
- PN533_INIT_TARGET_DEP
- PN533_INIT_TARGET_PASSIVE
- PN533_INIT_TARGET_RESP_ACTIVE
- PN533_INIT_TARGET_RESP_DEP
- PN533_INIT_TARGET_RESP_FRAME_MASK
- PN533_LISTEN_MOD
- PN533_LISTEN_TIME
- PN533_NO_TYPE_B_PROTOCOLS
- PN533_POLL_INTERVAL
- PN533_POLL_MOD_106KBPS_A
- PN533_POLL_MOD_106KBPS_JEWEL
- PN533_POLL_MOD_212KBPS_FELICA
- PN533_POLL_MOD_424KBPS_FELICA
- PN533_POLL_MOD_847KBPS_B
- PN533_POLL_MOD_MAX
- PN533_PRODUCT_ID
- PN533_PROTO_REQ_ACK_RESP
- PN533_PROTO_REQ_RESP
- PN533_STD_FRAME_ACK_SIZE
- PN533_STD_FRAME_CHECKSUM
- PN533_STD_FRAME_DIR_IN
- PN533_STD_FRAME_DIR_OUT
- PN533_STD_FRAME_HEADER_LEN
- PN533_STD_FRAME_IDENTIFIER
- PN533_STD_FRAME_MAX_PAYLOAD_LEN
- PN533_STD_FRAME_POSTAMBLE
- PN533_STD_FRAME_SOF
- PN533_STD_FRAME_TAIL_LEN
- PN533_STD_IS_EXTENDED
- PN533_TYPE_A_SEL_CASCADE
- PN533_TYPE_A_SEL_PROT
- PN533_TYPE_A_SEL_PROT_DEP
- PN533_TYPE_A_SEL_PROT_ISO14443
- PN533_TYPE_A_SEL_PROT_ISO14443_DEP
- PN533_TYPE_A_SEL_PROT_MIFARE
- PN533_TYPE_A_SENS_RES_NFCID1
- PN533_TYPE_A_SENS_RES_PLATCONF
- PN533_TYPE_A_SENS_RES_PLATCONF_JEWEL
- PN533_TYPE_A_SENS_RES_SSD
- PN533_TYPE_A_SENS_RES_SSD_JEWEL
- PN533_TYPE_B_AFI_ALL_FAMILIES
- PN533_TYPE_B_OPC_SENSB_RES
- PN533_TYPE_B_POLL_METHOD_PROBABILISTIC
- PN533_TYPE_B_POLL_METHOD_TIMESLOT
- PN533_TYPE_B_PROT_FCSI
- PN533_TYPE_B_PROT_TYPE
- PN533_TYPE_B_PROT_TYPE_RFU_MASK
- PN533_VENDOR_ID
- PN544_CB_TYPE_READER_F
- PN544_CMDS_HEADROOM
- PN544_DEP_ATR_REQ
- PN544_DEP_ATR_RES
- PN544_DEP_MERGE
- PN544_DEP_MODE
- PN544_DRIVER_NAME
- PN544_FELICA_ID
- PN544_FELICA_RAW
- PN544_FW_CMD_CHECK
- PN544_FW_CMD_RESET
- PN544_FW_CMD_RESULT_ACCESS_DENIED
- PN544_FW_CMD_RESULT_BAD_CRC
- PN544_FW_CMD_RESULT_CHUNK_ERROR
- PN544_FW_CMD_RESULT_CHUNK_OK
- PN544_FW_CMD_RESULT_COMMAND_REJECTED
- PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR
- PN544_FW_CMD_RESULT_INVALID_LENGTH
- PN544_FW_CMD_RESULT_INVALID_PARAMETER
- PN544_FW_CMD_RESULT_MEMORY_ERROR
- PN544_FW_CMD_RESULT_PROTOCOL_ERROR
- PN544_FW_CMD_RESULT_TIMEOUT
- PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND
- PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR
- PN544_FW_CMD_RESULT_WRITE_FAILED
- PN544_FW_CMD_SECURE_CHUNK_WRITE
- PN544_FW_CMD_SECURE_WRITE
- PN544_FW_CMD_WRITE
- PN544_FW_I2C_MAX_PAYLOAD
- PN544_FW_I2C_WRITE_DATA_MAX_LEN
- PN544_FW_I2C_WRITE_FRAME_HEADER_LEN
- PN544_FW_MODE
- PN544_FW_SECURE_BLOB_HEADER_LEN
- PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN
- PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN
- PN544_FW_SECURE_FRAME_HEADER_LEN
- PN544_FW_WRITE_BUFFER_MAX_LEN
- PN544_GPIO_NAME_EN
- PN544_GPIO_NAME_FW
- PN544_GPIO_NAME_IRQ
- PN544_HCI_CMD_ATTREQUEST
- PN544_HCI_CMD_CONTINUE_ACTIVATION
- PN544_HCI_EVT_ACTIVATED
- PN544_HCI_EVT_CONTINUE_MI
- PN544_HCI_EVT_DEACTIVATED
- PN544_HCI_EVT_RCV_DATA
- PN544_HCI_EVT_SND_DATA
- PN544_HCI_EVT_SWITCH_MODE
- PN544_HCI_I2C_DRIVER_NAME
- PN544_HCI_I2C_LLC_CRC
- PN544_HCI_I2C_LLC_LEN
- PN544_HCI_I2C_LLC_LEN_CRC
- PN544_HCI_I2C_LLC_MAX_PAYLOAD
- PN544_HCI_I2C_LLC_MAX_SIZE
- PN544_HCI_I2C_LLC_MIN_SIZE
- PN544_HCI_MODE
- PN544_HCI_RESETVEN_TIME
- PN544_HW_VARIANT_C2
- PN544_HW_VARIANT_C3
- PN544_I2C_FRAME_HEADROOM
- PN544_I2C_FRAME_TAILROOM
- PN544_ID_MGMT_FULL_VERSION_SW
- PN544_JEWEL_RAW_CMD
- PN544_MIFARE_CMD
- PN544_NFC_ESE_DEFAULT_MODE
- PN544_NFC_WI_MGMT_GATE
- PN544_PL_EMULATION
- PN544_PL_NFCT_DEACTIVATED
- PN544_PL_RDPHASES
- PN544_POLLING_LOOP_MGMT_GATE
- PN544_RF_READER_A_AUTO_ACTIVATION
- PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION
- PN544_RF_READER_CMD_ACTIVATE_NEXT
- PN544_RF_READER_CMD_PRESENCE_CHECK
- PN544_RF_READER_F_GATE
- PN544_RF_READER_ISO15693_GATE
- PN544_RF_READER_JEWEL_GATE
- PN544_RF_READER_NFCIP1_INITIATOR_GATE
- PN544_RF_READER_NFCIP1_TARGET_GATE
- PN544_SE_MODE_OFF
- PN544_SE_MODE_ON
- PN544_ST_COLD
- PN544_ST_FW_READY
- PN544_ST_READY
- PN544_SWP_DEFAULT_MODE
- PN544_SWP_MGMT_GATE
- PN544_SYS_MGMT_GATE
- PN544_SYS_MGMT_INFO_NOTIFICATION
- PN544_TEST_SWP
- PN544_WRITE
- PN5_DATA
- PN5_FN
- PN5_IN
- PN5_OUT
- PN6_DATA
- PN6_FN
- PN6_IN
- PN6_OUT
- PN7_DATA
- PN7_FN
- PN7_IN
- PN7_OUT
- PNADDR_ANY
- PNADDR_BROADCAST
- PNAME
- PND2_BLOB_SIZE
- PND2_MSG_SIZE
- PNDIS_802_11_ASSOCIATION_INFORMATION
- PNDIS_802_11_KEY
- PNDIS_802_11_REMOVE_KEY
- PND_MAX_PHYS_BIT
- PNEGOTIATE_MESSAGE
- PNEIGH_HASHMASK
- PNETIDS_LEN
- PNFSD_SUPPORTED_ATTRS_WORD1
- PNFSD_SUPPORTED_ATTRS_WORD2
- PNFS_ATTEMPTED
- PNFS_BLOCK_EXTENT_SIZE
- PNFS_BLOCK_INVALID_DATA
- PNFS_BLOCK_MAX_DEVICES
- PNFS_BLOCK_MAX_UUIDS
- PNFS_BLOCK_NONE_DATA
- PNFS_BLOCK_READWRITE_DATA
- PNFS_BLOCK_READ_DATA
- PNFS_BLOCK_UUID_LEN
- PNFS_BLOCK_VOLUME_CONCAT
- PNFS_BLOCK_VOLUME_SCSI
- PNFS_BLOCK_VOLUME_SIMPLE
- PNFS_BLOCK_VOLUME_SLICE
- PNFS_BLOCK_VOLUME_STRIPE
- PNFS_DEVICE_RETRY_TIMEOUT
- PNFS_LAYOUTGET_ON_OPEN
- PNFS_LAYOUTGET_RETRY_TIMEOUT
- PNFS_LAYOUTRET_ON_ERROR
- PNFS_LAYOUTRET_ON_SETATTR
- PNFS_LAYOUTSTATS_MAXDEV
- PNFS_LAYOUTSTATS_MAXSIZE
- PNFS_LAYOUT_MAXSIZE
- PNFS_NOT_ATTEMPTED
- PNFS_OSD_CAP_KEY_SEC_NONE
- PNFS_OSD_CAP_KEY_SEC_SSV
- PNFS_OSD_ERR_BAD_CRED
- PNFS_OSD_ERR_EIO
- PNFS_OSD_ERR_NOT_FOUND
- PNFS_OSD_ERR_NO_ACCESS
- PNFS_OSD_ERR_NO_SPACE
- PNFS_OSD_ERR_RESOURCE
- PNFS_OSD_ERR_UNREACHABLE
- PNFS_OSD_MISSING
- PNFS_OSD_RAID_0
- PNFS_OSD_RAID_4
- PNFS_OSD_RAID_5
- PNFS_OSD_RAID_PQ
- PNFS_OSD_VERSION_1
- PNFS_OSD_VERSION_2
- PNFS_READ_WHOLE_PAGE
- PNFS_SCSI_RANGE_SIZE
- PNFS_TRY_AGAIN
- PNFS_UPDATE_LAYOUT_BLOCKED
- PNFS_UPDATE_LAYOUT_BULK_RECALL
- PNFS_UPDATE_LAYOUT_EXIT
- PNFS_UPDATE_LAYOUT_FOUND_CACHED
- PNFS_UPDATE_LAYOUT_INVALID_OPEN
- PNFS_UPDATE_LAYOUT_IO_TEST_FAIL
- PNFS_UPDATE_LAYOUT_MDSTHRESH
- PNFS_UPDATE_LAYOUT_NOMEM
- PNFS_UPDATE_LAYOUT_NO_PNFS
- PNFS_UPDATE_LAYOUT_RD_ZEROLEN
- PNFS_UPDATE_LAYOUT_RETRY
- PNFS_UPDATE_LAYOUT_RETURN
- PNFS_UPDATE_LAYOUT_SEND_LAYOUTGET
- PNFS_UPDATE_LAYOUT_UNKNOWN
- PNIC2
- PNL_2_MASK
- PNL_2_OFFSET
- PNL_2_PRI
- PNL_2_SEC
- PNL_2_USAGE
- PNL_PACK
- PNL_PAUTOLF
- PNL_PBIDIR
- PNL_PBUSY
- PNL_PD0
- PNL_PD1
- PNL_PD2
- PNL_PD3
- PNL_PD4
- PNL_PD5
- PNL_PD6
- PNL_PD7
- PNL_PERRORP
- PNL_PINITP
- PNL_PINPUT
- PNL_PINTEN
- PNL_POUTPA
- PNL_PSELECD
- PNL_PSELECP
- PNL_PSTROBE
- PNL_SEQ_MASK
- PNL_SEQ_OFF
- PNL_SEQ_OFFSET
- PNL_SEQ_ON
- PNL_SEQ_USAGE
- PNMI_INIT
- PNORM
- PNOR_DESC
- PNO_MODE_IMMEDIATE
- PNO_MODE_MAX
- PNO_MODE_ON_RESUME
- PNO_MODE_ON_SUSPEND
- PNPBIOS_BOOTABLE
- PNPBIOS_DOCK
- PNPBIOS_INPUT
- PNPBIOS_NO_CONFIG
- PNPBIOS_NO_DISABLE
- PNPBIOS_OUTPUT
- PNPBIOS_REMOVABLE
- PNPEV_ABOUT_TO_CHANGE_CONFIG
- PNPEV_CONFIG_CHANGED_FAILED
- PNPEV_DOCK_CHANGED
- PNPEV_SYSTEM_DEVICE_CHANGED
- PNPEV_UNKNOWN_SYSTEM_EVENT
- PNPIPE_CTRLREQ_MAX
- PNPIPE_ENCAP
- PNPIPE_ENCAP_IP
- PNPIPE_ENCAP_NONE
- PNPIPE_HANDLE
- PNPIPE_IFINDEX
- PNPIPE_INITSTATE
- PNPMODE_DYNAMIC
- PNPMODE_STATIC
- PNPMSG_ABORT
- PNPMSG_OK
- PNPMSG_PNP_OS_ACTIVE
- PNPMSG_PNP_OS_INACTIVE
- PNPMSG_POWER_OFF
- PNPMSG_UNDOCK_DEFAULT_ACTION
- PNPORT_RESOURCE_ROUTING
- PNP_ACTIVATE
- PNP_ADD_PORT
- PNP_ATTACHED
- PNP_BAD_PARAMETER
- PNP_BUFFER_TOO_SMALL
- PNP_BUSY
- PNP_CNF_DMA
- PNP_CNF_INT
- PNP_CNF_IO_H
- PNP_CNF_IO_L
- PNP_CNF_MEM
- PNP_CONFIGURABLE
- PNP_CONFIG_CHANGE_FAILED_NO_BATTERY
- PNP_CONFIG_CHANGE_FAILED_RESOURCE_CONFLICT
- PNP_CONFIG_FORCE
- PNP_CONFIG_NORMAL
- PNP_CONSOLE
- PNP_CS16
- PNP_CS32
- PNP_CSN_CNT_OFF
- PNP_DISABLE
- PNP_DRIVER_RES_DISABLE
- PNP_DRIVER_RES_DO_NOT_CHANGE
- PNP_DS
- PNP_EISA_ID_MASK
- PNP_EVENTS_NOT_PENDING
- PNP_FAULTY
- PNP_FUNCTION_NOT_SUPPORTED
- PNP_FUNCTION_OK
- PNP_GET_APM_ID_TABLE
- PNP_GET_DOCKING_STATION_INFORMATION
- PNP_GET_ESCD_INFO
- PNP_GET_EVENT
- PNP_GET_NUM_SYS_DEV_NODES
- PNP_GET_PNP_ISA_CONFIG_STRUC
- PNP_GET_STATIC_ALLOCED_RES_INFO
- PNP_GET_SYS_DEV_NODE
- PNP_HARDWARE_ERROR
- PNP_ID_LEN
- PNP_INFO_SVCLASS_ID
- PNP_INVALID_HANDLE
- PNP_IRQ_FRMT
- PNP_IRQ_NR
- PNP_ISA_STRUCT_LEN
- PNP_MAX_DEVICES
- PNP_MESSAGE_NOT_SUPPORTED
- PNP_NAME_LEN
- PNP_NOT_SET_STATICALLY
- PNP_NO_ISA_PNP_CARDS
- PNP_OPTION_DEPENDENT
- PNP_OPTION_PRIORITY_MASK
- PNP_OPTION_PRIORITY_SHIFT
- PNP_OPTION_SET_MASK
- PNP_OPTION_SET_SHIFT
- PNP_RD_PORT_OFF
- PNP_READ
- PNP_READY
- PNP_READ_ESCD
- PNP_REMOVABLE
- PNP_RES_PRIORITY_ACCEPTABLE
- PNP_RES_PRIORITY_FUNCTIONAL
- PNP_RES_PRIORITY_INVALID
- PNP_RES_PRIORITY_PREFERRED
- PNP_RSRC_DATA
- PNP_RSRC_READY
- PNP_SEND_MESSAGE
- PNP_SET_FAILED
- PNP_SET_STATIC_ALLOCED_RES_INFO
- PNP_SET_SYS_DEV_NODE
- PNP_SIGNATURE
- PNP_STATUS
- PNP_SUCCESS
- PNP_SYSTEM_NOT_DOCKED
- PNP_TS1
- PNP_TS2
- PNP_UNABLE_TO_DETERMINE_DOCK_CAPABILITIES
- PNP_UNKNOWN_FUNCTION
- PNP_USE_ESCD_SUPPORT
- PNP_WAKE
- PNP_WRITE
- PNP_WRITE_ESCD
- PNP_WRITE_PORT
- PNR_ARR
- PNS_PEP_CONNECT_REQ
- PNS_PEP_CONNECT_RESP
- PNS_PEP_CTRL_REQ
- PNS_PEP_CTRL_RESP
- PNS_PEP_DISABLE_REQ
- PNS_PEP_DISABLE_RESP
- PNS_PEP_DISCONNECT_REQ
- PNS_PEP_DISCONNECT_RESP
- PNS_PEP_ENABLE_REQ
- PNS_PEP_ENABLE_RESP
- PNS_PEP_RESET_REQ
- PNS_PEP_RESET_RESP
- PNS_PEP_STATUS_IND
- PNS_PIPE_ALIGNED_DATA
- PNS_PIPE_CREATED_IND
- PNS_PIPE_CREATE_REQ
- PNS_PIPE_CREATE_RESP
- PNS_PIPE_DATA
- PNS_PIPE_DISABLED_IND
- PNS_PIPE_ENABLED_IND
- PNS_PIPE_REDIRECTED_IND
- PNS_PIPE_REMOVE_REQ
- PNS_PIPE_REMOVE_RESP
- PNS_PIPE_RESET_IND
- PNTKN
- PNVRAM
- PNV_CORE_IDLE_LOCK_BIT
- PNV_CORE_IDLE_THREAD_BITS
- PNV_CORE_IDLE_THREAD_WINKLE_BITS
- PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT
- PNV_CORE_IDLE_WINKLE_COUNT
- PNV_CORE_IDLE_WINKLE_COUNT_BITS
- PNV_CORE_IDLE_WINKLE_COUNT_SHIFT
- PNV_EEH_DBGFS_ENTRY
- PNV_GMBUSUNIT_CLOCK_GATE_DISABLE
- PNV_IDLE_NAME_LEN
- PNV_IODA1_DMA32_SEGSIZE
- PNV_IODA1_M64_NUM
- PNV_IODA1_M64_SEGS
- PNV_IODA_PE_BUS
- PNV_IODA_PE_BUS_ALL
- PNV_IODA_PE_DEV
- PNV_IODA_PE_MASTER
- PNV_IODA_PE_SLAVE
- PNV_IODA_PE_VF
- PNV_IODA_STOPPED_STATE
- PNV_OCXL_ACTAG_MAX
- PNV_OCXL_PASID_BITS
- PNV_OCXL_PASID_MAX
- PNV_OCXL_TL_BITS_PER_RATE
- PNV_OCXL_TL_MAX_TEMPLATE
- PNV_OCXL_TL_P9_RECV_CAP
- PNV_OCXL_TL_RATE_BUF_SIZE
- PNV_PCI_DIAG_BUF_SIZE
- PNV_PHB_FLAG_EEH
- PNV_PHB_IODA1
- PNV_PHB_IODA2
- PNV_PHB_MODEL_NPU
- PNV_PHB_MODEL_NPU2
- PNV_PHB_MODEL_P7IOC
- PNV_PHB_MODEL_PHB3
- PNV_PHB_MODEL_UNKNOWN
- PNV_PHB_NPU_NVLINK
- PNV_PHB_NPU_OCAPI
- PNV_PHP_FLAG_BROKEN_PDC
- PNV_PHP_STATE_INITIALIZED
- PNV_PHP_STATE_OFFLINE
- PNV_PHP_STATE_POPULATED
- PNV_PHP_STATE_REGISTERED
- PNV_THREAD_NAP
- PNV_THREAD_RUNNING
- PNV_THREAD_SLEEP
- PNV_THREAD_WINKLE
- PNX8330_CONFIG_MODULE_MAJREV
- PNX8330_CONFIG_POLYFUSE_7
- PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_MASK
- PNX8330_CONFIG_POLYFUSE_7_BOOT_MODE_SHIFT
- PNX8330_FIELD
- PNX8330_PIC_SPU_INT
- PNX8330_REGFIELD
- PNX8330_WRITEFIELD
- PNX8335_CLOCK_PLL_CPU_CTL
- PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK
- PNX8335_CLOCK_PLL_CPU_CTL_FREQ_SHIFT
- PNX8335_CONFIG_MODULE_MAJREV
- PNX8335_DEBUG0
- PNX8335_DEBUG1
- PNX8335_DEBUG2
- PNX8335_DEBUG3
- PNX8335_DEBUG4
- PNX8335_DEBUG5
- PNX8335_DEBUG6
- PNX8335_DEBUG7
- PNX8335_FIELD
- PNX8335_IP3902_MODULE_ID
- PNX8335_IP3902_MODULE_ID_MODULE_ID_MASK
- PNX8335_IP3902_MODULE_ID_MODULE_ID_SHIFT
- PNX8335_IP3902_MODULE_ID_VALUE
- PNX8335_IP3902_PORTS_END
- PNX8335_IP3902_PORTS_START
- PNX8335_NAND_ALE_MASK
- PNX8335_NAND_BASE
- PNX8335_NAND_CLE_MASK
- PNX8335_PIC_AVCHIP_IRQ_INT
- PNX8335_PIC_DENC_TTX_INT
- PNX8335_PIC_DISP_HD_INT
- PNX8335_PIC_DISP_SCALER_INT
- PNX8335_PIC_DTL_EMULATOR_C_IR_INT
- PNX8335_PIC_DTL_EMULATOR_Y_IR_INT
- PNX8335_PIC_DTL_WRITER_C_INT
- PNX8335_PIC_DTL_WRITER_Y_INT
- PNX8335_PIC_ETHERNET_INT
- PNX8335_PIC_IR1_IRQ_INT
- PNX8335_PIC_MIU_INT
- PNX8335_PIC_MMI_CDMMU_INT
- PNX8335_PIC_MMI_SIF0_INT
- PNX8335_PIC_MMI_SIF1_INT
- PNX8335_PIC_OSD_HD1_INT
- PNX8335_PIC_PIBCS_INT
- PNX8335_PIC_SATA_INT
- PNX8335_PIC_SYNC_HD_INT
- PNX8335_PIC_TDGR_DE_INT
- PNX8335_PIC_VMSP1_0_INT
- PNX8335_PIC_VMSP1_1_INT
- PNX8335_PIC_VMSP1_DMA_INT
- PNX8335_REGFIELD
- PNX8335_SATA_MODULE_ID
- PNX8335_SATA_MODULE_ID_MODULE_ID_MASK
- PNX8335_SATA_MODULE_ID_MODULE_ID_SHIFT
- PNX8335_SATA_MODULE_ID_VALUE
- PNX8335_SATA_PORTS_END
- PNX8335_SATA_PORTS_START
- PNX8335_WRITEFIELD
- PNX833X_BASE
- PNX833X_BIT
- PNX833X_CLOCK_CPUCP_CTL
- PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK
- PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT
- PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET
- PNX833X_CONFIG
- PNX833X_CONFIG_CPU_COUNTERS_CONTROL
- PNX833X_CONFIG_CPU_WATCHDOG
- PNX833X_CONFIG_CPU_WATCHDOG_COMPARE
- PNX833X_CONFIG_MODULE_ID
- PNX833X_CONFIG_MODULE_ID_MAJREV_MASK
- PNX833X_CONFIG_MODULE_ID_MAJREV_SHIFT
- PNX833X_CONFIG_MUX
- PNX833X_CONFIG_MUX_IDE_MUX
- PNX833X_CONFIG_USB
- PNX833X_FIELD
- PNX833X_GPIO_0_INT
- PNX833X_GPIO_10_INT
- PNX833X_GPIO_11_INT
- PNX833X_GPIO_12_INT
- PNX833X_GPIO_13_INT
- PNX833X_GPIO_14_INT
- PNX833X_GPIO_15_INT
- PNX833X_GPIO_1_INT
- PNX833X_GPIO_2_INT
- PNX833X_GPIO_3_INT
- PNX833X_GPIO_4_INT
- PNX833X_GPIO_5_INT
- PNX833X_GPIO_6_INT
- PNX833X_GPIO_7_INT
- PNX833X_GPIO_8_INT
- PNX833X_GPIO_9_INT
- PNX833X_GPIO_IRQ_BASE
- PNX833X_GPIO_NUM_IRQ
- PNX833X_I2C0_PORTS_END
- PNX833X_I2C0_PORTS_START
- PNX833X_I2C1_PORTS_END
- PNX833X_I2C1_PORTS_START
- PNX833X_IDE_MODULE_ID
- PNX833X_IDE_MODULE_ID_MODULE_ID_MASK
- PNX833X_IDE_MODULE_ID_MODULE_ID_SHIFT
- PNX833X_IDE_MODULE_ID_VALUE
- PNX833X_IDE_PORTS_END
- PNX833X_IDE_PORTS_START
- PNX833X_MIU_CONFIG_SPI
- PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK
- PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT
- PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK
- PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT
- PNX833X_MIU_CONFIG_SPI_OPCODE_MASK
- PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT
- PNX833X_MIU_CONFIG_SPI_SYNC_MASK
- PNX833X_MIU_CONFIG_SPI_SYNC_SHIFT
- PNX833X_MIU_SEL0
- PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK
- PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT
- PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK
- PNX833X_MIU_SEL0_BURST_PAGE_LEN_SHIFT
- PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK
- PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT
- PNX833X_MIU_SEL0_TIMING
- PNX833X_MIU_SEL1
- PNX833X_MIU_SEL1_TIMING
- PNX833X_MIU_SEL2
- PNX833X_MIU_SEL2_TIMING
- PNX833X_MIU_SEL3
- PNX833X_MIU_SEL3_TIMING
- PNX833X_PIC_AOI_INT
- PNX833X_PIC_AUDIO_DEC_INT
- PNX833X_PIC_CLOCK_INT
- PNX833X_PIC_CONFIG_INT
- PNX833X_PIC_DEINTERLACER_INT
- PNX833X_PIC_DISP1_INT
- PNX833X_PIC_DISPLAY2_INT
- PNX833X_PIC_GPIO_INT
- PNX833X_PIC_I2C0_INT
- PNX833X_PIC_I2C1_INT
- PNX833X_PIC_IDE_DMA_INT
- PNX833X_PIC_IDE_INT
- PNX833X_PIC_INT_PRIORITY
- PNX833X_PIC_INT_REG
- PNX833X_PIC_INT_SRC
- PNX833X_PIC_INT_SRC_INT_SRC_MASK
- PNX833X_PIC_INT_SRC_INT_SRC_SHIFT
- PNX833X_PIC_IRQ_BASE
- PNX833X_PIC_IR_INT
- PNX833X_PIC_NUM_IRQ
- PNX833X_PIC_OSD_INT
- PNX833X_PIC_PIBC_INT
- PNX833X_PIC_REG
- PNX833X_PIC_SC_INT
- PNX833X_PIC_SGDX_DMA_INT
- PNX833X_PIC_SGDX_PARSER_INT
- PNX833X_PIC_SGDX_TPD_INT
- PNX833X_PIC_SYNC_INT
- PNX833X_PIC_TS_IN0_DMA_INT
- PNX833X_PIC_TS_IN0_DV_INT
- PNX833X_PIC_TS_IN0_TRD_INT
- PNX833X_PIC_TS_IN1_DMA_INT
- PNX833X_PIC_TS_IN1_DV_INT
- PNX833X_PIC_TS_IN1_TRD_INT
- PNX833X_PIC_TS_OUT_INT
- PNX833X_PIC_UART0_INT
- PNX833X_PIC_UART1_INT
- PNX833X_PIC_USB_INT
- PNX833X_PIC_VC_INT
- PNX833X_PIC_VIDEO_DEC_INT
- PNX833X_PIC_VMSP1_INT
- PNX833X_PIC_VMSP2_INT
- PNX833X_PIC_VMSP_DMA_INT
- PNX833X_PIO_DIR
- PNX833X_PIO_DIR2
- PNX833X_PIO_IN
- PNX833X_PIO_IN2
- PNX833X_PIO_INT_CLEAR
- PNX833X_PIO_INT_EDGE
- PNX833X_PIO_INT_ENABLE
- PNX833X_PIO_INT_HI
- PNX833X_PIO_INT_LO
- PNX833X_PIO_INT_STATUS
- PNX833X_PIO_OUT
- PNX833X_PIO_OUT2
- PNX833X_PIO_SEL
- PNX833X_PIO_SEL2
- PNX833X_REG
- PNX833X_REGBIT
- PNX833X_REGFIELD
- PNX833X_RESET
- PNX833X_RESET_CONFIG
- PNX833X_RESET_CONTROL
- PNX833X_RESET_CONTROL_2
- PNX833X_TIMER_IRQ
- PNX833X_UART0_PORTS_END
- PNX833X_UART0_PORTS_START
- PNX833X_UART1_PORTS_END
- PNX833X_UART1_PORTS_START
- PNX833X_USB_PORTS_END
- PNX833X_USB_PORTS_START
- PNX833X_WRITEFIELD
- PNX833X_WRITE_CONFIG_SPI
- PNX8XXX_BAUD
- PNX8XXX_CFG
- PNX8XXX_CONSOLE
- PNX8XXX_FIFO
- PNX8XXX_ICLR
- PNX8XXX_IEN
- PNX8XXX_ISET
- PNX8XXX_ISR_PASS_LIMIT
- PNX8XXX_ISTAT
- PNX8XXX_LCR
- PNX8XXX_MCR
- PNX8XXX_MID
- PNX8XXX_NR_PORTS
- PNX8XXX_PD
- PNX8XXX_UART_FIFO_RBRTHR
- PNX8XXX_UART_FIFO_RXBRK
- PNX8XXX_UART_FIFO_RXFE
- PNX8XXX_UART_FIFO_RXFIFO
- PNX8XXX_UART_FIFO_RXPAR
- PNX8XXX_UART_FIFO_TXFIFO
- PNX8XXX_UART_FIFO_TXFIFO_STA
- PNX8XXX_UART_INT_ALLRX
- PNX8XXX_UART_INT_ALLTX
- PNX8XXX_UART_INT_BREAK
- PNX8XXX_UART_INT_EMPTY
- PNX8XXX_UART_INT_FRERR
- PNX8XXX_UART_INT_PARITY
- PNX8XXX_UART_INT_RCVTO
- PNX8XXX_UART_INT_RX
- PNX8XXX_UART_INT_RXOVRN
- PNX8XXX_UART_INT_TX
- PNX8XXX_UART_LCR_2STOPB
- PNX8XXX_UART_LCR_8BIT
- PNX8XXX_UART_LCR_PAREN
- PNX8XXX_UART_LCR_PAREVN
- PNX8XXX_UART_LCR_RX_NEXT
- PNX8XXX_UART_LCR_RX_RST
- PNX8XXX_UART_LCR_TXBREAK
- PNX8XXX_UART_LCR_TX_RST
- PNX8XXX_UART_MCR_CTS
- PNX8XXX_UART_MCR_DCD
- PNX8XXX_UART_MCR_DTR
- PNX8XXX_UART_MCR_LOOP
- PNX8XXX_UART_MCR_RTS
- PNX8XXX_UART_MCR_SCR
- PNX_FIELD
- PNX_I2C_PM
- PNX_TIMEOUT_VALUE
- PNX_WATCHDOG_TIMEOUT
- PNX_WRITEFIELD
- PNY_USB_TV_NTSC_FM
- PN_BASE
- PN_COMMGR
- PN_COMMON_MESSAGE
- PN_COMM_ISA_ENTITY_NOT_REACHABLE_RESP
- PN_COMM_SERVICE_NOT_IDENTIFIED_RESP
- PN_CON_CLR
- PN_CON_DATAIF_EN
- PN_CON_EN
- PN_CON_LAST
- PN_CON_RES_FORCE_NRDY
- PN_CON_RES_FORCE_STALL
- PN_CON_RES_MASK
- PN_CON_RES_NORMAL
- PN_CON_RES_WEN
- PN_DEV_H
- PN_DEV_PC
- PN_HASHMASK
- PN_HASHSIZE
- PN_INT_BFRDY
- PN_INT_LSTTR
- PN_INV
- PN_LEGACY_FLOW_CONTROL
- PN_LEN
- PN_MAX_FLOW_CONTROL
- PN_MEDIA_SOS
- PN_MEDIA_USB
- PN_MOD_DIR
- PN_MOD_EPNUM
- PN_MOD_EPNUM_MASK
- PN_MOD_TYPE
- PN_MOD_TYPE_MASK
- PN_MOD_TYPE_SHIFT
- PN_MULTI_CREDIT_FLOW_CONTROL
- PN_NO_ADDR
- PN_NO_FLOW_CONTROL
- PN_ONE_CREDIT_FLOW_CONTROL
- PN_PEP_IND_FLOW_CONTROL
- PN_PEP_IND_ID_MCFC_GRANT_CREDITS
- PN_PEP_TYPE_COMMON
- PN_PIPE_DISABLE
- PN_PIPE_ENABLE
- PN_PIPE_ERR_ALL_PIPES_IN_USE
- PN_PIPE_ERR_DEV_DISCONNECTED
- PN_PIPE_ERR_GENERAL
- PN_PIPE_ERR_INVALID_CTRL_ID
- PN_PIPE_ERR_INVALID_HANDLE
- PN_PIPE_ERR_INVALID_PARAM
- PN_PIPE_ERR_NOT_ALLOWED
- PN_PIPE_ERR_NOT_SUPPORTED
- PN_PIPE_ERR_OVERLOAD
- PN_PIPE_ERR_PEP_IN_USE
- PN_PIPE_ERR_TIMEOUT
- PN_PIPE_INVALID_HANDLE
- PN_PIPE_NO_ERROR
- PN_PIPE_SB_ALIGNED_DATA
- PN_PIPE_SB_CONNECT_REQ_PEP_SUB_TYPE
- PN_PIPE_SB_CREATE_REQ_PEP_SUB_TYPE
- PN_PIPE_SB_NEGOTIATED_FC
- PN_PIPE_SB_PREFERRED_FC_RX
- PN_PIPE_SB_REDIRECT_REQ_PEP_SUB_TYPE
- PN_PIPE_SB_REQUIRED_FC_TX
- PN_PREFIX
- PN_PROTO_PHONET
- PN_PROTO_PIPE
- PN_PROTO_TRANSPORT
- PN_RAMMAP_BASEAD
- PN_RAMMAP_BASEAD_MASK
- PN_RAMMAP_DATA
- PN_RAMMAP_MPKT
- PN_RAMMAP_MPKT_MASK
- PN_RAMMAP_MPKT_SHIFT
- PN_RAMMAP_RAMAREA_16KB
- PN_RAMMAP_RAMAREA_1KB
- PN_RAMMAP_RAMAREA_2KB
- PN_RAMMAP_RAMAREA_4KB
- PN_RAMMAP_RAMAREA_8KB
- PN_RAMMAP_RAMAREA_MASK
- PN_RAMMAP_RAMAREA_SHIFT
- PN_RAMMAP_RAMIF
- PN_RAMMAP_RAMIF_MASK
- PN_RAMMAP_RAMIF_SHIFT
- PN_REG
- PN_SCHEDSTAT
- PN_XNUM
- PO1030_ADCOFFSET
- PO1030_AUTOCTRL1
- PO1030_AUTOCTRL2
- PO1030_AUTO_SUBSAMPLING
- PO1030_AWB_BLUE_TUNING
- PO1030_AWB_RED_TUNING
- PO1030_BLUE_GAIN
- PO1030_BLUE_GAIN_DEFAULT
- PO1030_CONTROL1
- PO1030_CONTROL2
- PO1030_CONTROL3
- PO1030_CONTROL4
- PO1030_CT0
- PO1030_CT1
- PO1030_CT2
- PO1030_CT3
- PO1030_CT4
- PO1030_CT5
- PO1030_CT6
- PO1030_CT7
- PO1030_CT8
- PO1030_Cb_U_GAIN
- PO1030_Cr_V_GAIN
- PO1030_DEVID_H
- PO1030_DEVID_L
- PO1030_EDGE_ENH_OFF
- PO1030_EGA
- PO1030_EXPOSURE_DEFAULT
- PO1030_FLICKERDELTA60
- PO1030_FLICKER_DELTA50
- PO1030_FRAMEHEIGHT_H
- PO1030_FRAMEHEIGHT_L
- PO1030_FRAMEWIDTH_H
- PO1030_FRAMEWIDTH_L
- PO1030_FRAME_EQUAL
- PO1030_GC0
- PO1030_GC1
- PO1030_GC2
- PO1030_GC3
- PO1030_GC4
- PO1030_GC5
- PO1030_GC6
- PO1030_GC7
- PO1030_GLOBALGAIN
- PO1030_GLOBALGAINMAX
- PO1030_GLOBALGAINMIN
- PO1030_GLOBALIBIAS
- PO1030_GLOBAL_GAIN_DEFAULT
- PO1030_GREEN_1_GAIN
- PO1030_GREEN_2_GAIN
- PO1030_GREEN_GAIN_DEFAULT
- PO1030_HFLIP
- PO1030_HREF_ENABLE
- PO1030_INTEGLINES_H
- PO1030_INTEGLINES_L
- PO1030_INTEGLINES_M
- PO1030_OUTFORMCTRL1
- PO1030_OUTFORMCTRL2
- PO1030_OUTFORMCTRL3
- PO1030_OUTFORMCTRL4
- PO1030_OUTFORMCTRL5
- PO1030_PERIOD50_H
- PO1030_PERIOD50_L
- PO1030_PERIOD60_H
- PO1030_PERIOD60_L
- PO1030_PIXELIBIAS
- PO1030_RAW_RGB_BAYER
- PO1030_RED_GAIN
- PO1030_RED_GAIN_DEFAULT
- PO1030_REGCLK167
- PO1030_SENSOR
- PO1030_SENSOR_RESET
- PO1030_SHUTTER_MODE
- PO1030_SUBSAMPLING
- PO1030_VFLIP
- PO1030_WEIGHT_WIN_2X
- PO1030_WINDOWHEIGHT_H
- PO1030_WINDOWHEIGHT_L
- PO1030_WINDOWWIDTH_H
- PO1030_WINDOWWIDTH_L
- PO1030_WINDOWX_H
- PO1030_WINDOWX_L
- PO1030_WINDOWY_H
- PO1030_WINDOWY_L
- PO1030_YCONTRAST
- PO1030_YSATURATION
- PO1030_YTARGET
- POAO
- POAU
- POCCTRL
- POCCTRL0
- POCCTRL1
- POCCTRL2
- POCCTRL3
- POCR
- POCR_FEIE
- POCR_FSRIE
- POC_BUFFER_SIZE
- POC_CMP
- PODHD_STARTUP_DELAY
- PODM_BB_Config_Type
- PODM_RATE_ADAPTIVE
- PODM_RA_INFO_T
- PODM_RF_CAL_T
- PODM_RF_Config_Type
- PODM_RF_RADIO_PATH_E
- PODM_STA_INFO_T
- PODSLOT_EASI_BASE
- PODSLOT_EASI_SIZE
- PODSLOT_IOC0_BASE
- PODSLOT_IOC4_BASE
- PODSLOT_IOC_SIZE
- PODSLOT_MEMC_BASE
- PODSLOT_MEMC_SIZE
- POD_BUFSIZE_DUMPREQ
- POD_BUSY_MIDISEND
- POD_BUSY_READ
- POD_BUSY_WRITE
- POD_CHANNEL_DIRTY
- POD_CONTROL_SIZE
- POD_DUMP_MEMORY
- POD_MONITOR_LEVEL
- POD_NAME_LENGTH
- POD_NAME_OFFSET
- POD_SAVE_PRESSED
- POD_STARTUP_DELAY
- POD_STARTUP_DONE
- POD_STARTUP_SETUP
- POD_STARTUP_VERSIONREQ
- POD_SYSEX_CODE
- POD_SYSEX_DUMP
- POD_SYSEX_DUMPMEM
- POD_SYSEX_DUMPREQ
- POD_SYSEX_FINISH
- POD_SYSEX_SAVE
- POD_SYSEX_STORE
- POD_SYSEX_SYSTEM
- POD_SYSEX_SYSTEMREQ
- POD_SYSTEM_INVALID
- POE2_12
- POE2_OEI3
- POFFSET
- POFF_MASK
- POF_BOOT_LOADER_CODE_SIZE
- POF_BOOT_LOADER_OFF_IN_PAGE
- POF_BOOT_LOADER_PAGE_SIZE
- POF_BOOT_LOADER_TOTAL_SIZE
- POF_READY_TIME_OUT_SEC
- POF_READ_FILE_HEAD
- POF_READ_TAG_DATA
- POF_READ_TAG_HEAD
- POINTER
- POINTERCLR
- POINTER_CLEAR
- POINTER_DEBUG
- POINTER_RETURN_FLAG
- POINTER_VALUE
- POINTLIST
- POINT_HIGH
- POISON
- POISONED_REG
- POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK
- POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK
- POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT
- POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK
- POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT
- POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK
- POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT
- POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK
- POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT
- POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK
- POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT
- POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK
- POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT
- POISON_BUF_VAL
- POISON_END
- POISON_FREE
- POISON_FREE_INITMEM
- POISON_INUSE
- POISON_POINTER_DELTA
- POISON_REG
- POKER_FAIL_MASK
- POKER_FAIL_MASK_SET
- POKE_MAX_OPCODE_SIZE
- POLADBGRDPTR_M
- POLADBGRDPTR_S
- POLADBGRDPTR_V
- POLADBGWRPTR_G
- POLADBGWRPTR_M
- POLADBGWRPTR_S
- POLARIS10_SMC_SIZE
- POLARIS11_GB_ADDR_CONFIG_GOLDEN
- POLARIS_AVMODE_ANALOGT_TV
- POLARIS_AVMODE_DEFAULT
- POLARIS_AVMODE_DIGITAL
- POLARIS_AVMODE_ENXTERNAL_AV
- POLARIS_DENSE_CONFIG_BASE
- POLARIS_DENSE_IO_BASE
- POLARIS_DENSE_MEM_BASE
- POLARIS_EVK
- POLARIS_HAE_ADDRESS
- POLARIS_IACK_BASE
- POLARIS_IACK_SC
- POLARIS_SPARSE_CONFIG_BASE
- POLARIS_SPARSE_IO_BASE
- POLARIS_SPARSE_MEM_BASE
- POLARIS_W_CMD
- POLARIS_W_DEVID
- POLARIS_W_STATUS
- POLARIS_W_VENID
- POLARITY_LOW
- POLARITY_OK
- POLARIZATION_HRZ
- POLARIZATION_UNKNOWN
- POLARIZATION_VH
- POLARIZATION_VL
- POLARIZATION_VM
- POLCTRL_ADRS
- POLCTRL_DATA_POL_FALL
- POLCTRL_DATA_POL_RISE
- POLCTRL_EN_ACT_H
- POLCTRL_EN_ACT_L
- POLCTRL_EN_POL_FALL
- POLCTRL_EN_POL_RISE
- POLCTRL_SYNC_ACT_H
- POLCTRL_SYNC_ACT_L
- POLCTRL_SYNC_POL_FALL
- POLCTRL_SYNC_POL_RISE
- POLICER_ACTION
- POLICER_MODE_DISABLE
- POLICER_MODE_MASK
- POLICER_MODE_MEF
- POLICER_MODE_RFC2698
- POLICER_MODE_RFC4115
- POLICER_MODE_SHIFT
- POLICE_BURST_SIZE_M
- POLICE_CBS_S
- POLICE_CIR_S
- POLICE_COLOR_MAP_M
- POLICE_COLOR_MAP_S
- POLICE_COLOR_NOT_AWARE
- POLICE_DROP_ALL
- POLICE_DROP_SRP
- POLICE_ENABLE
- POLICE_PACKET_DROPPED
- POLICE_PACKET_GREEN
- POLICE_PACKET_RED
- POLICE_PACKET_TYPE_M
- POLICE_PACKET_TYPE_S
- POLICE_PACKET_YELLOW
- POLICE_PBS_S
- POLICE_PIR_S
- POLICY
- POLICYDB_BOUNDS_MAXDEPTH
- POLICYDB_CAPABILITY_ALWAYSNETWORK
- POLICYDB_CAPABILITY_CGROUPSECLABEL
- POLICYDB_CAPABILITY_EXTSOCKCLASS
- POLICYDB_CAPABILITY_MAX
- POLICYDB_CAPABILITY_NETPEER
- POLICYDB_CAPABILITY_NNP_NOSUID_TRANSITION
- POLICYDB_CAPABILITY_OPENPERM
- POLICYDB_CONFIG_MLS
- POLICYDB_MAGIC
- POLICYDB_STRING
- POLICYDB_VERSION_AVTAB
- POLICYDB_VERSION_BASE
- POLICYDB_VERSION_BOOL
- POLICYDB_VERSION_BOUNDARY
- POLICYDB_VERSION_CONSTRAINT_NAMES
- POLICYDB_VERSION_DEFAULT_TYPE
- POLICYDB_VERSION_FILENAME_TRANS
- POLICYDB_VERSION_INFINIBAND
- POLICYDB_VERSION_IPV6
- POLICYDB_VERSION_MAX
- POLICYDB_VERSION_MIN
- POLICYDB_VERSION_MLS
- POLICYDB_VERSION_NEW_OBJECT_DEFAULTS
- POLICYDB_VERSION_NLCLASS
- POLICYDB_VERSION_PERMISSIVE
- POLICYDB_VERSION_POLCAP
- POLICYDB_VERSION_RANGETRANS
- POLICYDB_VERSION_ROLETRANS
- POLICYDB_VERSION_VALIDATETRANS
- POLICYDB_VERSION_XPERMS_IOCTL
- POLICY_AA
- POLICY_AB
- POLICY_AM
- POLICY_AS
- POLICY_BA
- POLICY_BB
- POLICY_BM
- POLICY_BS
- POLICY_DEFAULT
- POLICY_DEFAULT_DPC_PROMOTE_TIME_US
- POLICY_DEFAULT_EXECUTION_QUANTUM_US
- POLICY_DEFAULT_FAULT_TIME_US
- POLICY_DEFAULT_PREEMPTION_TIME_US
- POLICY_DEMOTE
- POLICY_FILE_FLAGS
- POLICY_MA
- POLICY_MAX_NUM_WI
- POLICY_MB
- POLICY_MIN_DIV
- POLICY_MM
- POLICY_MS
- POLICY_PERFORMANCE
- POLICY_POWERSAVE
- POLICY_POWER_SUPERSAVE
- POLICY_PREEMPT_TO_IDLE
- POLICY_PROMOTE
- POLICY_RESET_ENGINE
- POLICY_SA
- POLICY_SB
- POLICY_SM
- POLICY_SS
- POLICY_WRITEBACK
- POLLERR
- POLLEX_SET
- POLLFD_PER_PAGE
- POLLFLAG
- POLLFREE
- POLLHUP
- POLLIN
- POLLING_INTERVAL
- POLLING_LLT_THRESHOLD
- POLLING_MODE
- POLLING_READY_TIMEOUT_COUNT
- POLLING_TRANSFER
- POLLING_WAIT_CNT
- POLLINT
- POLLIN_SET
- POLLJIFFIES_CONTROLVM_FAST
- POLLJIFFIES_CONTROLVM_SLOW
- POLLJIFFIES_NORMALCHANNEL
- POLLMSG
- POLLNVAL
- POLLOUT
- POLLOUT_SET
- POLLPRI
- POLLRDBAND
- POLLRDHUP
- POLLRDNORM
- POLLREMOVE
- POLLWRBAND
- POLLWRNORM
- POLL_100_USEC
- POLL_1_MSEC
- POLL_1_USEC
- POLL_BUSY_LOOP
- POLL_CFG_GDSCR
- POLL_CONTINUOUS
- POLL_COUNT
- POLL_CQ
- POLL_CTRL
- POLL_DELAY_MS
- POLL_DEMAND
- POLL_ENABLED
- POLL_ERR
- POLL_FREQUENCY
- POLL_HUP
- POLL_IDLE_RELAX_COUNT
- POLL_IMS_ENABLE_MASK
- POLL_IN
- POLL_INTERVAL
- POLL_INTERVAL_BURST
- POLL_INTERVAL_CEC_MS
- POLL_INTERVAL_DEFAULT
- POLL_INTERVAL_MAX
- POLL_INTERVAL_MS
- POLL_INTERVAL_SEC
- POLL_INTERVAL_US
- POLL_LAST_IDX
- POLL_LATCH_CNT
- POLL_LATCH_REGISTER
- POLL_LIST_ADDR_HI
- POLL_LIST_ADDR_LO
- POLL_LOOPS
- POLL_LOOP_COUNT
- POLL_MAX_ATTEMPT
- POLL_MAX_READS
- POLL_MSEC
- POLL_MSECS
- POLL_MSG
- POLL_OUT
- POLL_PERIOD
- POLL_PHY
- POLL_PRI
- POLL_RST_DELAY_MS
- POLL_RST_MAX
- POLL_SECONDS
- POLL_SLEEP
- POLL_SLOTS
- POLL_SPURIOUS_IRQ_INTERVAL
- POLL_STACK_ALLOC
- POLL_TABLE_FULL
- POLL_TIME
- POLL_TIMEOUT
- POLL_TIMEOUT_US
- POLL_TMOUT_MS
- POLL_TOUT
- POLL_USEC
- POLL_WAIT
- POLL_WHILE_FALSE
- POLL_WHILE_TRUE
- POLO_GPIO_CFG1_REG
- POLO_GPIO_CFG2_REG
- POLO_GPIO_CFG3_REG
- POLO_GPIO_CFG4_REG
- POLO_GPIO_CFG5_REG
- POLO_GPIO_CFG6_REG
- POLO_GPIO_CFG7_REG
- POLO_GPIO_DAT1_REG
- POLO_GPIO_DAT2_REG
- POLO_GPIO_DAT3_REG
- POLO_GPIO_DAT4_REG
- POLO_GPIO_DAT5_REG
- POLO_GPIO_DAT6_REG
- POLO_GPIO_DAT7_REG
- POLO_GPIO_OD1_REG
- POLO_GPIO_OD2_REG
- POLO_ZEUS_SUB_FAMILY
- POLY
- POLY1305_BLOCK_SIZE
- POLY1305_DIGEST_SIZE
- POLY1305_KEY_SIZE
- POLYNOM
- POLY_3RD_ORDER_COUNT
- POLY_DISABLED
- POLY_DUALMODE
- POLY_MAX
- POLY_MIN
- POLY_TEXT_TYPE
- POLY_TEXT_TYPE_16
- POLY_TEXT_TYPE_8
- POL_CNTL_ADDR
- POL_CODE
- POL_DE_SHIFT
- POL_HSYNC_SHIFT
- POL_IX_PORT
- POL_IX_QUEUE
- POL_MODE_DATARATE
- POL_MODE_FRMRATE_HI
- POL_MODE_FRMRATE_LO
- POL_MODE_LINERATE
- POL_ORDER
- POL_TIME_INTERVAL_VAL
- POL_VSYNC_SHIFT
- POM_BIST_REG
- POM_GRP_EXECMASKX
- POM_INT
- POM_INT_ENA_W1S
- POM_PERF_CTL
- PONG_AVAIL
- PONG_BUFFER_ADDRESS
- PONG_VALID
- PONG_WRITE
- PONKEY_CC_FLAG_CLEAR
- PONKEY_PU_INACTIVE
- PONKEY_PWR_OFF
- PONKEY_TURNOFF_MASK
- PONKEY_TURNOFF_TIMER_MASK
- PONTIS_CS_CLK
- PONTIS_CS_CS
- PONTIS_CS_RDATA
- PONTIS_CS_WDATA
- PONTIS_DEVICE_DESC
- PON_CNTL_1
- PON_CNTL_1_PULL_UP_EN
- PON_CNTL_1_USB_PWR_EN
- PON_CNTL_1_WD_EN_RESET
- PON_CNTL_PULL_UP
- PON_CNTL_TRIG_DELAY_MASK
- PON_DBC_CTL
- PON_DBC_DELAY_MASK
- PON_DIS
- PON_EN
- PON_INT_RT_STS
- PON_KPDPWR_N_SET
- PON_KPDPWR_PULL_UP
- PON_PMIC_WD_RESET_PET
- PON_PMIC_WD_RESET_S1_TIMER
- PON_PMIC_WD_RESET_S2_CTL
- PON_PMIC_WD_RESET_S2_CTL2
- PON_PMIC_WD_RESET_S2_TIMER
- PON_PS_HOLD_ENABLE
- PON_PS_HOLD_RST_CTL
- PON_PS_HOLD_RST_CTL2
- PON_PS_HOLD_TYPE_HARD_RESET
- PON_PS_HOLD_TYPE_MASK
- PON_PS_HOLD_TYPE_SHUTDOWN
- PON_PULL_CTL
- PON_RESIN_N_SET
- PON_RESIN_PULL_UP
- PON_REV2
- PON_RT_STS
- PON_SOFT_RB_SPARE
- POODLE_AUDIO_CLOCK
- POODLE_GPIO_AC_IN
- POODLE_GPIO_ADC_TEMP_ON
- POODLE_GPIO_BAT_COVER
- POODLE_GPIO_BYPASS_ON
- POODLE_GPIO_CF_CD
- POODLE_GPIO_CF_IRQ
- POODLE_GPIO_CF_STSCHG
- POODLE_GPIO_CHARGE_ON
- POODLE_GPIO_CHRG_FULL
- POODLE_GPIO_CHRG_ON
- POODLE_GPIO_CO
- POODLE_GPIO_CP401
- POODLE_GPIO_DISCHARGE_ON
- POODLE_GPIO_GA_INT
- POODLE_GPIO_HP_IN
- POODLE_GPIO_HS_OUT
- POODLE_GPIO_IR_ON
- POODLE_GPIO_L_LCLK
- POODLE_GPIO_L_PCLK
- POODLE_GPIO_MAIN_BAT_LOW
- POODLE_GPIO_ON_KEY
- POODLE_GPIO_SD_PWR
- POODLE_GPIO_SD_PWR1
- POODLE_GPIO_TP_CS
- POODLE_GPIO_TP_INT
- POODLE_GPIO_USB_PULLUP
- POODLE_GPIO_VPEN
- POODLE_GPIO_WAKEUP
- POODLE_GPIO_nSD_CLK
- POODLE_GPIO_nSD_DETECT
- POODLE_GPIO_nSD_INT
- POODLE_GPIO_nSD_WP
- POODLE_HP
- POODLE_HP_OFF
- POODLE_IRQ_GPIO_AC_IN
- POODLE_IRQ_GPIO_CF_CD
- POODLE_IRQ_GPIO_CF_IRQ
- POODLE_IRQ_GPIO_CO
- POODLE_IRQ_GPIO_GA_INT
- POODLE_IRQ_GPIO_HP_IN
- POODLE_IRQ_GPIO_MAIN_BAT_LOW
- POODLE_IRQ_GPIO_ON_KEY
- POODLE_IRQ_GPIO_TP_INT
- POODLE_IRQ_GPIO_WAKEUP
- POODLE_IRQ_GPIO_nSD_DETECT
- POODLE_IRQ_GPIO_nSD_INT
- POODLE_LOCOMO_GPIO_232VCC_ON
- POODLE_LOCOMO_GPIO_AMP_ON
- POODLE_LOCOMO_GPIO_JK_B
- POODLE_LOCOMO_GPIO_MUTE_L
- POODLE_LOCOMO_GPIO_MUTE_R
- POODLE_NR_IRQS
- POODLE_SCOOP_CHARGE_ON
- POODLE_SCOOP_CP401
- POODLE_SCOOP_GPIO_BASE
- POODLE_SCOOP_HS_OUT
- POODLE_SCOOP_IO_DIR
- POODLE_SCOOP_IO_OUT
- POODLE_SCOOP_L_LCLK
- POODLE_SCOOP_L_PCLK
- POODLE_SCOOP_VPEN
- POODLE_SPK_OFF
- POODLE_SPK_ON
- POOL_ALLOC_SIZE
- POOL_DISASSOCIATED
- POOL_ENTRY_SIZE
- POOL_EXHAUST
- POOL_HANDLE
- POOL_ID
- POOL_INDEX
- POOL_MANAGER_ACTIVE
- POOL_POISON_ALLOCATED
- POOL_POISON_FREED
- POOL_QUEUE
- POOL_READ
- POOL_RELIEVE
- POOL_SHIFT
- POOL_SIZE
- POOL_WARN
- POOL_WRITE
- POOR
- POPALTMODE
- POPF
- POPG_EN
- POPP
- POPULATE_MAP
- POPULATE_ONE2ONE
- POPULATE_ZERO_SHADOW
- POP_BASIC_STACK
- POP_CR
- POP_FPU
- POP_FS
- POP_GS
- POP_GS_EX
- POP_NVREGS
- POP_NVREGS_BELOW_FPU
- POP_SECTION_IRQENTRY
- POP_SS_OPCODE
- POP_VMX
- PORB
- PORCTRL
- PORRSTDET
- PORT
- PORT0
- PORT0_BASE
- PORT0_DEFAULT_ATTEN_MASK
- PORT0_DEFAULT_ATTEN_SHIFT
- PORT0_DEFAULT_ATTEN_SMASK
- PORT0_INT
- PORT0_LOCAL_ATTEN_MASK
- PORT0_LOCAL_ATTEN_SHIFT
- PORT0_LOCAL_ATTEN_SMASK
- PORT0_PHY_ADDRESS
- PORT0_PORT_TYPE_MASK
- PORT0_PORT_TYPE_SHIFT
- PORT0_PORT_TYPE_SMASK
- PORT0_REG
- PORT0_REMOTE_ATTEN_MASK
- PORT0_REMOTE_ATTEN_SHIFT
- PORT0_REMOTE_ATTEN_SMASK
- PORT1
- PORT100_CAPABILITIES
- PORT100_CMD_GET_COMMAND_TYPE
- PORT100_CMD_GET_FIRMWARE_VERSION
- PORT100_CMD_IN_COMM_RF
- PORT100_CMD_IN_SET_PROTOCOL
- PORT100_CMD_IN_SET_RF
- PORT100_CMD_RESPONSE
- PORT100_CMD_SET_COMMAND_TYPE
- PORT100_CMD_STATUS_OK
- PORT100_CMD_STATUS_TIMEOUT
- PORT100_CMD_SWITCH_RF
- PORT100_CMD_TG_COMM_RF
- PORT100_CMD_TG_SET_PROTOCOL
- PORT100_CMD_TG_SET_RF
- PORT100_CMD_TG_SET_RF_OFF
- PORT100_CMD_TYPE_0
- PORT100_CMD_TYPE_1
- PORT100_CMD_TYPE_IS_SUPPORTED
- PORT100_COMM_RF_HEAD_MAX_LEN
- PORT100_COMM_TYPE_IN_106A
- PORT100_COMM_TYPE_IN_106B
- PORT100_COMM_TYPE_IN_212F
- PORT100_COMM_TYPE_IN_424F
- PORT100_COMM_TYPE_TG_106A
- PORT100_COMM_TYPE_TG_212F
- PORT100_COMM_TYPE_TG_424F
- PORT100_FRAME_ACK
- PORT100_FRAME_ACK_SIZE
- PORT100_FRAME_CHECKSUM
- PORT100_FRAME_CMD
- PORT100_FRAME_DIRECTION
- PORT100_FRAME_DIR_IN
- PORT100_FRAME_DIR_OUT
- PORT100_FRAME_EXT
- PORT100_FRAME_HEADER_LEN
- PORT100_FRAME_MAX_PAYLOAD_LEN
- PORT100_FRAME_POSTAMBLE
- PORT100_FRAME_SOF
- PORT100_FRAME_TAIL_LEN
- PORT100_IN_MAX_NUM_PROTOCOLS
- PORT100_IN_PROT_ADD_CRC
- PORT100_IN_PROT_ADD_EOF
- PORT100_IN_PROT_ADD_PARITY
- PORT100_IN_PROT_ADD_SOF
- PORT100_IN_PROT_BITWISE_AC_RECV_MODE
- PORT100_IN_PROT_CHECK_CRC
- PORT100_IN_PROT_CHECK_EOF
- PORT100_IN_PROT_CHECK_PARITY
- PORT100_IN_PROT_CHECK_SOF
- PORT100_IN_PROT_CRM
- PORT100_IN_PROT_CRM_MIN_LEN
- PORT100_IN_PROT_CRYPTO1
- PORT100_IN_PROT_DEAF_TIME
- PORT100_IN_PROT_END
- PORT100_IN_PROT_GUARD_TIME_AT_INITIATOR
- PORT100_IN_PROT_INITIAL_GUARD_TIME
- PORT100_IN_PROT_MULTI_CARD
- PORT100_IN_PROT_RFCA
- PORT100_IN_PROT_T1_TAG_FRAME
- PORT100_IN_PROT_VALID_BIT_NUMBER
- PORT100_MDAA_TGT_HAS_BEEN_ACTIVATED_MASK
- PORT100_MDAA_TGT_WAS_ACTIVATED_MASK
- PORT100_PROTOCOLS
- PORT100_TG_MAX_NUM_PROTOCOLS
- PORT100_TG_PROT_CRM
- PORT100_TG_PROT_END
- PORT100_TG_PROT_RF_OFF
- PORT100_TG_PROT_TU
- PORT115_I2C_SCL2_MARK
- PORT115_I2C_SCL3_MARK
- PORT116_I2C_SDA2_MARK
- PORT116_I2C_SDA3_MARK
- PORT128_LCD2VSYN_MARK
- PORT129_LCD2CS__MARK
- PORT129_LCD2HSYN_MARK
- PORT130_MSIOF2_RXD_MARK
- PORT131_KEYOUT11_MARK
- PORT131_KEYOUT6_MARK
- PORT131_MSIOF2_SS1_MARK
- PORT132_KEYOUT10_MARK
- PORT132_KEYOUT7_MARK
- PORT132_MSIOF2_SS2_MARK
- PORT136_KEYOUT8_MARK
- PORT137_KEYOUT9_MARK
- PORT138_KEYOUT8_MARK
- PORT139_KEYOUT9_MARK
- PORT142_KEYOUT10_MARK
- PORT143_KEYOUT11_MARK
- PORT143_KEYOUT6_MARK
- PORT144_KEYOUT7_MARK
- PORT145_LCD2DISP_MARK
- PORT145_LCD2RS_MARK
- PORT146_LCD2WR__MARK
- PORT149_KEYOUT9_MARK
- PORT149_RDWR_MARK
- PORT153_MSIOF2_SS1_MARK
- PORT156_MSIOF2_SS2_MARK
- PORT157_MSIOF2_RXD_MARK
- PORT159_SCIFA5_SCK_MARK
- PORT159_SCIFB_SCK_MARK
- PORT160_SCIFA5_TXD_MARK
- PORT160_SCIFB_TXD_MARK
- PORT161_SCIFA5_CTS__MARK
- PORT161_SCIFB_CTS__MARK
- PORT162_SCIFA5_RXD_MARK
- PORT162_SCIFB_RXD_MARK
- PORT163_SCIFA5_RTS__MARK
- PORT163_SCIFB_RTS__MARK
- PORT16_VIO_CKOR_MARK
- PORT193_SCIFA5_CTS__MARK
- PORT194_SCIFA5_RTS__MARK
- PORT195_SCIFA5_RXD_MARK
- PORT196_SCIFA5_TXD_MARK
- PORT197_SCIFA5_SCK_MARK
- PORT19_VIO_CKO2_MARK
- PORT1_BASE
- PORT1_DEFAULT_ATTEN_MASK
- PORT1_DEFAULT_ATTEN_SHIFT
- PORT1_DEFAULT_ATTEN_SMASK
- PORT1_INIT1
- PORT1_INIT2
- PORT1_INT
- PORT1_LOCAL_ATTEN_MASK
- PORT1_LOCAL_ATTEN_SHIFT
- PORT1_LOCAL_ATTEN_SMASK
- PORT1_PHY_ADDRESS
- PORT1_PORT_TYPE_MASK
- PORT1_PORT_TYPE_SHIFT
- PORT1_PORT_TYPE_SMASK
- PORT1_POWER
- PORT1_REMOTE_ATTEN_MASK
- PORT1_REMOTE_ATTEN_SHIFT
- PORT1_REMOTE_ATTEN_SMASK
- PORT2
- PORT207_MSIOF0L_SS1_MARK
- PORT208_MSIOF0L_SS2_MARK
- PORT210_MSIOF0L_SS1_MARK
- PORT211_MSIOF0L_SS2_MARK
- PORT217_LCD2DISP_MARK
- PORT217_LCD2RS_MARK
- PORT218_VIO_CKOR_MARK
- PORT219_LCD2WR__MARK
- PORT221_LCD2CS__MARK
- PORT221_LCD2HSYN_MARK
- PORT222_LCD2VSYN_MARK
- PORT226_VIO_CKO2_MARK
- PORT236_I2C_SDA2_MARK
- PORT237_I2C_SCL2_MARK
- PORT241_IRDA_OUT_MARK
- PORT241_IROUT_MARK
- PORT242_IRDA_IN_MARK
- PORT243_IRDA_FIRSEL_MARK
- PORT243_VIO_CKO2_MARK
- PORT244_SCIFA5_CTS__MARK
- PORT244_SCIFB_CTS__MARK
- PORT245_SCIFA5_RTS__MARK
- PORT245_SCIFB_RTS__MARK
- PORT246_SCIFA5_RXD_MARK
- PORT246_SCIFB_RXD_MARK
- PORT247_SCIFA5_TXD_MARK
- PORT247_SCIFB_TXD_MARK
- PORT248_I2C_SCL3_MARK
- PORT248_SCIFA5_SCK_MARK
- PORT248_SCIFB_SCK_MARK
- PORT249_I2C_SDA3_MARK
- PORT249_IROUT_MARK
- PORT27_I2C_SCL2_MARK
- PORT27_I2C_SCL3_MARK
- PORT27_IROUT_MARK
- PORT28_I2C_SDA2_MARK
- PORT28_I2C_SDA3_MARK
- PORT28_TPU1TO1_MARK
- PORT29_TPU1TO1_MARK
- PORT2CHANNEL
- PORT3
- PORT30_VIO_CKOR_MARK
- PORT31_IROUT_MARK
- PORT4
- PORT47_FSICSPDIF_MARK
- PORT49_IRDA_OUT_MARK
- PORT49_IROUT_MARK
- PORT5
- PORT53_FSICSPDIF_MARK
- PORT53_IRDA_IN_MARK
- PORT54_IRDA_FIRSEL_MARK
- PORT58_KEYOUT7_MARK
- PORT59_KEYOUT6_MARK
- PORT6
- PORT7
- PORT8
- PORT9
- PORT91_RDWR_MARK
- PORTA
- PORTADDR_ENH
- PORTADDR_SET
- PORTADR
- PORTAL_ECSR_ERR
- PORTAL_IDX
- PORTAL_OPAQUE
- PORTAL_SDQCR
- PORTAL_TYPE_IPV4
- PORTAL_TYPE_IPV6
- PORTAXICFG
- PORTAXICFG_EN_CONTEXT_SET
- PORTAXICFG_OUTTRANS_SET
- PORTA_DIRECTION
- PORTA_HOTPLUG_ENABLE
- PORTA_HOTPLUG_LONG_DETECT
- PORTA_HOTPLUG_NO_DETECT
- PORTA_HOTPLUG_SHORT_DETECT
- PORTA_HOTPLUG_STATUS_MASK
- PORTA_I2S_BUFFER_BASE
- PORTA_IOCTL
- PORTA_TS_BUFFER_BASE
- PORTB
- PORTB_DIRECTION
- PORTB_HOTPLUG_ENABLE
- PORTB_HOTPLUG_INT_EN
- PORTB_HOTPLUG_INT_LONG_PULSE
- PORTB_HOTPLUG_INT_SHORT_PLUSE
- PORTB_HOTPLUG_INT_STATUS
- PORTB_HOTPLUG_LIVE_STATUS_G4X
- PORTB_HOTPLUG_LIVE_STATUS_GM45
- PORTB_HOTPLUG_LONG_DETECT
- PORTB_HOTPLUG_NO_DETECT
- PORTB_HOTPLUG_SHORT_DETECT
- PORTB_HOTPLUG_STATUS_MASK
- PORTB_I2S_BUFFER_BASE
- PORTB_IOCTL
- PORTB_PULSE_DURATION_100ms
- PORTB_PULSE_DURATION_2ms
- PORTB_PULSE_DURATION_4_5ms
- PORTB_PULSE_DURATION_6ms
- PORTB_PULSE_DURATION_MASK
- PORTB_TS_BUFFER_BASE
- PORTC
- PORTCFG
- PORTCR_PULMD_DOWN
- PORTCR_PULMD_MASK
- PORTCR_PULMD_OFF
- PORTCR_PULMD_UP
- PORTC_DIRECTION
- PORTC_HOTPLUG_ENABLE
- PORTC_HOTPLUG_INT_EN
- PORTC_HOTPLUG_INT_LONG_PULSE
- PORTC_HOTPLUG_INT_SHORT_PULSE
- PORTC_HOTPLUG_INT_STATUS
- PORTC_HOTPLUG_LIVE_STATUS_G4X
- PORTC_HOTPLUG_LIVE_STATUS_GM45
- PORTC_HOTPLUG_LONG_DETECT
- PORTC_HOTPLUG_NO_DETECT
- PORTC_HOTPLUG_SHORT_DETECT
- PORTC_HOTPLUG_STATUS_MASK
- PORTC_IOCTL
- PORTC_PULSE_DURATION_100ms
- PORTC_PULSE_DURATION_2ms
- PORTC_PULSE_DURATION_4_5ms
- PORTC_PULSE_DURATION_6ms
- PORTC_PULSE_DURATION_MASK
- PORTD
- PORTD_HOTPLUG_ENABLE
- PORTD_HOTPLUG_INT_EN
- PORTD_HOTPLUG_INT_LONG_PULSE
- PORTD_HOTPLUG_INT_SHORT_PULSE
- PORTD_HOTPLUG_INT_STATUS
- PORTD_HOTPLUG_LIVE_STATUS_G4X
- PORTD_HOTPLUG_LIVE_STATUS_GM45
- PORTD_HOTPLUG_LONG_DETECT
- PORTD_HOTPLUG_NO_DETECT
- PORTD_HOTPLUG_SHORT_DETECT
- PORTD_HOTPLUG_STATUS_MASK
- PORTD_PULSE_DURATION_100ms
- PORTD_PULSE_DURATION_2ms
- PORTD_PULSE_DURATION_4_5ms
- PORTD_PULSE_DURATION_6ms
- PORTD_PULSE_DURATION_MASK
- PORTE
- PORTENABLE_F
- PORTENABLE_S
- PORTENABLE_V
- PORTE_BROADCAST_RCVD
- PORTE_BYTES_DMAED
- PORTE_HARD_RESET
- PORTE_HOTPLUG_ENABLE
- PORTE_HOTPLUG_LONG_DETECT
- PORTE_HOTPLUG_NO_DETECT
- PORTE_HOTPLUG_SHORT_DETECT
- PORTE_HOTPLUG_STATUS_MASK
- PORTE_LINK_RESET_ERR
- PORTE_TIMER_EVENT
- PORTF
- PORTG
- PORTH
- PORTHLPMC
- PORTJ
- PORTK
- PORTL
- PORTLI
- PORTM
- PORTMAN2X4_MODE_INPUT_TRIGGERED
- PORTMAN_NUM_INPUT_PORTS
- PORTMAN_NUM_OUTPUT_PORTS
- PORTMAP_G
- PORTMAP_M
- PORTMAP_S
- PORTMASK2CHAN
- PORTNUM2CHAN
- PORTPHY1CFG
- PORTPHY1CFG_FRCPHYRDY_SET
- PORTPHY2CFG
- PORTPHY3CFG
- PORTPHY4CFG
- PORTPHY5CFG
- PORTPHY5CFG_RTCHG_SET
- PORTPMSC
- PORTRAIT_GEN_CNTL
- PORTRANSCFG
- PORTRANSCFG_RXWM_SET
- PORTS
- PORTSC
- PORTSCX_CONNECT_STATUS_CHANGE
- PORTSCX_CURRENT_CONNECT_STATUS
- PORTSCX_FORCE_FULL_SPEED_CONNECT
- PORTSCX_LINE_STATUS_BITS
- PORTSCX_LINE_STATUS_BIT_POS
- PORTSCX_LINE_STATUS_JSTATE
- PORTSCX_LINE_STATUS_KSTATE
- PORTSCX_LINE_STATUS_SE0
- PORTSCX_LINE_STATUS_UNDEF
- PORTSCX_OVER_CURRENT_ACT
- PORTSCX_OVER_CURRENT_CHG
- PORTSCX_PAR_XCVR_SELECT
- PORTSCX_PHY_LOW_POWER_SPD
- PORTSCX_PHY_TYPE_SEL
- PORTSCX_PIC_AMBER
- PORTSCX_PIC_BIT_POS
- PORTSCX_PIC_GREEN
- PORTSCX_PIC_OFF
- PORTSCX_PIC_UNDEF
- PORTSCX_PORT_ENABLE
- PORTSCX_PORT_EN_DIS_CHANGE
- PORTSCX_PORT_FORCE_FULL_SPEED
- PORTSCX_PORT_FORCE_RESUME
- PORTSCX_PORT_INDICTOR_CTRL
- PORTSCX_PORT_POWER
- PORTSCX_PORT_RESET
- PORTSCX_PORT_SPEED_FULL
- PORTSCX_PORT_SPEED_HIGH
- PORTSCX_PORT_SPEED_LOW
- PORTSCX_PORT_SPEED_MASK
- PORTSCX_PORT_SPEED_UNDEF
- PORTSCX_PORT_SUSPEND
- PORTSCX_PORT_TEST_CTRL
- PORTSCX_PORT_WIDTH
- PORTSCX_PTC_BIT_POS
- PORTSCX_PTC_DISABLE
- PORTSCX_PTC_FORCE_EN
- PORTSCX_PTC_JSTATE
- PORTSCX_PTC_KSTATE
- PORTSCX_PTC_PACKET
- PORTSCX_PTC_SEQNAK
- PORTSCX_PTS_BIT_POS
- PORTSCX_PTS_FSLS
- PORTSCX_PTS_ULPI
- PORTSCX_PTS_UTMI
- PORTSCX_PTW
- PORTSCX_PTW_16BIT
- PORTSCX_PTW_8BIT
- PORTSCX_SPEED_BIT_POS
- PORTSCX_W1C_BITS
- PORTSCX_WAKE_ON_CONNECT_DIS
- PORTSCX_WAKE_ON_CONNECT_EN
- PORTSCX_WAKE_ON_OVER_CURRENT
- PORTSC_CCS
- PORTSC_CONFIG_CHANGE
- PORTSC_CONNECT_STATUS_CHANGE
- PORTSC_CONN_CHANGE
- PORTSC_CONN_STATUS
- PORTSC_CSC
- PORTSC_CURRENT_CONNECT_STATUS
- PORTSC_FPR
- PORTSC_FSL_PFSC
- PORTSC_HSP
- PORTSC_LINE_STATUS_BITS
- PORTSC_LINE_STATUS_BIT_POS
- PORTSC_LINE_STATUS_JSTATE
- PORTSC_LINE_STATUS_KSTATE
- PORTSC_LINE_STATUS_SE0
- PORTSC_LINE_STATUS_UNDEF
- PORTSC_LINK_CHANGE
- PORTSC_OCC
- PORTSC_OVER_CURRENT_ACT
- PORTSC_OVER_CUURENT_CHG
- PORTSC_PEC
- PORTSC_PFSC
- PORTSC_PHCD
- PORTSC_PHY_LOW_POWER_SPD
- PORTSC_PHY_TYPE_SEL
- PORTSC_PIC_AMBER
- PORTSC_PIC_BIT_POS
- PORTSC_PIC_GREEN
- PORTSC_PIC_OFF
- PORTSC_PIC_UNDEF
- PORTSC_PORT_ENABLE
- PORTSC_PORT_EN_DIS_CHANGE
- PORTSC_PORT_FORCE_FULL_SPEED
- PORTSC_PORT_FORCE_RESUME
- PORTSC_PORT_INDICTOR_CTRL
- PORTSC_PORT_POWER
- PORTSC_PORT_RESET
- PORTSC_PORT_SPEED_FULL
- PORTSC_PORT_SPEED_HIGH
- PORTSC_PORT_SPEED_LOW
- PORTSC_PORT_SPEED_MASK
- PORTSC_PORT_SPEED_UNDEF
- PORTSC_PORT_SUSPEND
- PORTSC_PORT_TEST_CTRL
- PORTSC_PP
- PORTSC_PTC
- PORTSC_PTC_BIT_POS
- PORTSC_PTC_DISABLE
- PORTSC_PTC_FORCE_EN
- PORTSC_PTC_JSTATE
- PORTSC_PTC_KSTATE
- PORTSC_PTC_PACKET
- PORTSC_PTC_SEQNAK
- PORTSC_PTS
- PORTSC_PTS_BIT_POS
- PORTSC_PTS_FSLS_SERIAL
- PORTSC_PTS_ULPI
- PORTSC_PTS_UTMI
- PORTSC_PTW
- PORTSC_PTW_16BIT
- PORTSC_PTW_8BIT
- PORTSC_RESET_CHANGE
- PORTSC_SPEED_BIT_POS
- PORTSC_STS
- PORTSC_SUSP
- PORTSC_SUSPEND_STS_ACK
- PORTSC_SUSPEND_STS_ERR
- PORTSC_SUSPEND_STS_NYET
- PORTSC_SUSPEND_STS_STALL
- PORTSC_TRANSCEIVER_WIDTH
- PORTSC_W1C_BITS
- PORTSC_WAKE_ON_CONNECT_DIS
- PORTSC_WAKE_ON_CONNECT_EN
- PORTSC_WAKE_ON_OVER_CURRENT
- PORTSC_WKCN
- PORTSEL1
- PORTSEL2
- PORTSEL_10T
- PORTSEL_AUI
- PORTSEL_DAI
- PORTSEL_GPSI
- PORTSTATE_ENABLED
- PORTSTATE_LOOPBACK
- PORTSTATE_TXBREAK
- PORTSTATE_TXFLUSH
- PORTS_0_3_COAL_DONE
- PORTS_4_7_COAL_DONE
- PORTS_PER_ASIC
- PORTS_PER_CHAIN
- PORTS_PER_CONTROLLER
- PORTX_CAP_SHIFT
- PORT_0
- PORT_0_2031
- PORT_1
- PORT_1000BT_EEE_DISABLE
- PORT_1000_LINK_GOOD
- PORT_100BT4_CAPABLE
- PORT_100BTX_ABLE
- PORT_100BTX_CAPABLE
- PORT_100BTX_FD_ABLE
- PORT_100BTX_FD_CAPABLE
- PORT_100BT_EEE_DISABLE
- PORT_100BT_FIXED_LATENCY
- PORT_100_LINK_GOOD
- PORT_10BT_ABLE
- PORT_10BT_CAPABLE
- PORT_10BT_FD_ABLE
- PORT_10BT_FD_CAPABLE
- PORT_10BT_PREAMBLE
- PORT_16450
- PORT_16550
- PORT_16550A
- PORT_16550A_FSL64
- PORT_16650
- PORT_16650V2
- PORT_16654
- PORT_16750
- PORT_16850
- PORT_16C950
- PORT_1_2031
- PORT_21285
- PORT_3RD_PARTY_RESET
- PORT_802_1P_ENABLE
- PORT_802_1P_PRIO_ENABLE
- PORT_802_1P_REMAPPING
- PORT_8250
- PORT_8250_CIR
- PORT_A
- PORT_ABORT
- PORT_ACL_ENABLE
- PORT_ACL_FORCE_DLR_MISS
- PORT_ACL_INDEX_M
- PORT_ACL_INT
- PORT_ACL_PRIO_ENABLE
- PORT_ACL_READ_DONE
- PORT_ACL_WRITE
- PORT_ACL_WRITE_DONE
- PORT_ACTIVATE_UPPER_ADDR
- PORT_ALL
- PORT_ALTDUMP
- PORT_ALTERA_JTAGUART
- PORT_ALTERA_UART
- PORT_ALTR_16550_F128
- PORT_ALTR_16550_F32
- PORT_ALTR_16550_F64
- PORT_ALTSCP
- PORT_AMBA
- PORT_APBUART
- PORT_APP1
- PORT_APP2
- PORT_AR7
- PORT_AR933X
- PORT_ARC
- PORT_ASC
- PORT_ASSIGN_LAST
- PORT_ASSOC_VECTOR
- PORT_ASSOC_VECTOR_MONITOR
- PORT_ASSOC_VECTOR_PAV_MASK
- PORT_ATMEL
- PORT_ATTR
- PORT_ATTR_RO
- PORT_AUI
- PORT_AUTHEN_BLOCK
- PORT_AUTHEN_MODE
- PORT_AUTHEN_PASS
- PORT_AUTHEN_TRAP
- PORT_AUTO_MDIX_DISABLE
- PORT_AUTO_NEG_1000BT
- PORT_AUTO_NEG_1000BT_FD
- PORT_AUTO_NEG_100BT4
- PORT_AUTO_NEG_100BTX
- PORT_AUTO_NEG_100BTX_FD
- PORT_AUTO_NEG_10BT
- PORT_AUTO_NEG_10BT_FD
- PORT_AUTO_NEG_802_3
- PORT_AUTO_NEG_ACKNOWLEDGE
- PORT_AUTO_NEG_ASYM_PAUSE
- PORT_AUTO_NEG_CAPABLE
- PORT_AUTO_NEG_COMPLETE
- PORT_AUTO_NEG_DISABLE
- PORT_AUTO_NEG_ENABLE
- PORT_AUTO_NEG_MANUAL
- PORT_AUTO_NEG_MASTER
- PORT_AUTO_NEG_MASTER_PREFERRED
- PORT_AUTO_NEG_NEXT_PAGE
- PORT_AUTO_NEG_PAUSE
- PORT_AUTO_NEG_REMOTE_FAULT
- PORT_AUTO_NEG_RESTART
- PORT_AUTO_NEG_SELECTOR
- PORT_AUTO_NEG_SYM_PAUSE
- PORT_AXICC
- PORT_B
- PORT_BACK_PRESSURE
- PORT_BASE
- PORT_BASED_POLICING
- PORT_BASED_PRIORITY_0
- PORT_BASED_PRIORITY_1
- PORT_BASED_PRIORITY_2
- PORT_BASED_PRIORITY_3
- PORT_BASED_PRIORITY_BASE
- PORT_BASED_PRIORITY_MASK
- PORT_BASED_PRIORITY_SHIFT
- PORT_BASED_PRIO_0
- PORT_BASED_PRIO_1
- PORT_BASED_PRIO_2
- PORT_BASED_PRIO_3
- PORT_BASED_PRIO_M
- PORT_BASED_PRIO_S
- PORT_BCM63XX
- PORT_BEACON_MAX_LIMIT
- PORT_BESLD
- PORT_BFIN
- PORT_BFIN_SPORT
- PORT_BMI_FIFO_UNITS
- PORT_BNC
- PORT_BRCM_TRUMANAGE
- PORT_BROADCAST_STORM
- PORT_BSW0
- PORT_BSW1
- PORT_BSW2
- PORT_BYT
- PORT_C
- PORT_CABLE_10M_SHORT
- PORT_CABLE_DIAG_PAIR_M
- PORT_CABLE_DIAG_PAIR_S
- PORT_CABLE_DIAG_RESULT
- PORT_CABLE_DIAG_RESULT_M
- PORT_CABLE_DIAG_RESULT_S
- PORT_CABLE_DIAG_SELECT_M
- PORT_CABLE_DIAG_SELECT_S
- PORT_CABLE_FAULT_COUNTER
- PORT_CABLE_FAULT_COUNTER_H
- PORT_CABLE_FAULT_COUNTER_L
- PORT_CABLE_STAT_FAILED
- PORT_CABLE_STAT_NORMAL
- PORT_CABLE_STAT_OPEN
- PORT_CABLE_STAT_SHORT
- PORT_CAPABILITY_LOCATION_IN_SMP
- PORT_CAP_DEVICE
- PORT_CAP_DISABLED
- PORT_CAP_HOST
- PORT_CAP_MASK
- PORT_CAP_MMIO_SIZE
- PORT_CAP_OTG
- PORT_CAP_PORT_NUM
- PORT_CAP_SUPP_INT_NUM
- PORT_CAS
- PORT_CE4100
- PORT_CEC
- PORT_CERR_CMD_BOUNDARY
- PORT_CERR_CMD_MSTABRT
- PORT_CERR_CMD_PCIPERR
- PORT_CERR_CMD_TGTABRT
- PORT_CERR_DATA
- PORT_CERR_DEV
- PORT_CERR_DIRECTION
- PORT_CERR_INCONSISTENT
- PORT_CERR_OVERRUN
- PORT_CERR_PKT_PROT
- PORT_CERR_SDB
- PORT_CERR_SEND
- PORT_CERR_SENDSERVICE
- PORT_CERR_SGT_BOUNDARY
- PORT_CERR_SGT_MSTABRT
- PORT_CERR_SGT_PCIPERR
- PORT_CERR_SGT_TGTABRT
- PORT_CERR_UNDERRUN
- PORT_CERR_XFR_MSTABRT
- PORT_CERR_XFR_PCIPERR
- PORT_CERR_XFR_TGTABRT
- PORT_CERR_XFR_UNDEF
- PORT_CG_MAP_NUM
- PORT_CHANGE_MASK
- PORT_CIRRUS
- PORT_CLK_RATE
- PORT_CLK_SEL
- PORT_CLK_SEL_LCPLL_1350
- PORT_CLK_SEL_LCPLL_2700
- PORT_CLK_SEL_LCPLL_810
- PORT_CLK_SEL_MASK
- PORT_CLK_SEL_NONE
- PORT_CLK_SEL_SPLL
- PORT_CLK_SEL_WRPLL
- PORT_CLK_SEL_WRPLL1
- PORT_CLK_SEL_WRPLL2
- PORT_CLPS711X
- PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS
- PORT_CMD
- PORT_CMD_ACTIVATE
- PORT_CMD_ALPE
- PORT_CMD_ASP
- PORT_CMD_ATAPI
- PORT_CMD_CLO
- PORT_CMD_ERR
- PORT_CMD_ESP
- PORT_CMD_FBSCP
- PORT_CMD_FIS_ON
- PORT_CMD_FIS_RX
- PORT_CMD_HPCP
- PORT_CMD_ICC_ACTIVE
- PORT_CMD_ICC_MASK
- PORT_CMD_ICC_PARTIAL
- PORT_CMD_ICC_SLUMBER
- PORT_CMD_ISSUE
- PORT_CMD_LIST_ON
- PORT_CMD_PMP
- PORT_CMD_POWER_ON
- PORT_CMD_SPIN_UP
- PORT_CMD_START
- PORT_CMT_IN_TEAM
- PORT_CMT_PORT_ACTIVE
- PORT_CMT_PORT_INACTIVE
- PORT_CMT_PORT_ROLE
- PORT_CMT_TEAM0
- PORT_CMT_TEAM1
- PORT_CMT_TEAM_MASK
- PORT_CNTR_LAST
- PORT_COLLISION_TEST
- PORT_COMMAND
- PORT_COMMAND_ISSUE
- PORT_CONFIG
- PORT_CONFIG_1000MB_SPEED
- PORT_CONFIG_100MB_SPEED
- PORT_CONFIG_10MB_SPEED
- PORT_CONFIG_AUTO_NEG_ENABLED
- PORT_CONFIG_DEFAULT
- PORT_CONFIG_EXT
- PORT_CONFIG_FULL_DUPLEX_ENABLED
- PORT_CONFIG_HALF_DUPLEX_ENABLED
- PORT_CONFIG_LINK_SPEED_MASK
- PORT_CONFIG_LOAD
- PORT_CONFIG_SYM_PAUSE_ENABLED
- PORT_CONFIG_WRITE
- PORT_CONNECT
- PORT_CONNECTIVITY_MASK
- PORT_CONNECTIVITY_SHIFT
- PORT_CONNECT_CHANGE
- PORT_CONNECT_DET
- PORT_CONTEXT
- PORT_CONTROL
- PORT_CONTROL_CC
- PORT_CONTROL_DFP
- PORT_CONTROL_DRM
- PORT_CONTROL_DS
- PORT_CONTROL_EF
- PORT_CONTROL_EI
- PORT_CONTROL_ET
- PORT_CONTROL_FI
- PORT_CONTROL_FORCE_FLOW_CTRL
- PORT_CONTROL_HEADER
- PORT_CONTROL_HH
- PORT_CONTROL_IFP
- PORT_CONTROL_INGRESS_MODE
- PORT_CONTROL_IPV
- PORT_CONTROL_ITP
- PORT_CONTROL_MAC
- PORT_CONTROL_OI
- PORT_CONTROL_RCB
- PORT_CONTROL_RLB
- PORT_CONTROL_STATE_BLOCKING
- PORT_CONTROL_STATE_DISABLED
- PORT_CONTROL_STATE_FORWARDING
- PORT_CONTROL_STATE_LEARNING
- PORT_CONTROL_STATE_MASK
- PORT_CONTROL_TRAILER
- PORT_CONTROL_VLAN_TUNNEL
- PORT_COUNT
- PORT_COUNTER_NUM
- PORT_COUNT_IFG
- PORT_COUNT_IFG_S
- PORT_COUNT_PREAMBLE
- PORT_COUNT_PREAMBLE_S
- PORT_CPB_CPBLAR
- PORT_CPB_PTQFIFO
- PORT_CPM
- PORT_CRC_ERR_CNT
- PORT_CRC_ERR_THRESH
- PORT_CRIS
- PORT_CSC
- PORT_CS_32BIT_ACTV
- PORT_CS_CDB16
- PORT_CS_DEV_RST
- PORT_CS_INIT
- PORT_CS_IRQ_WOC
- PORT_CS_PMP_EN
- PORT_CS_PMP_RESUME
- PORT_CS_PORT_RST
- PORT_CS_RDY
- PORT_CTRL
- PORT_CTRL_ADDR
- PORT_CTRL_BLOCK_STATE
- PORT_CTRL_CLR
- PORT_CTRL_DIS_STATE
- PORT_CTRL_FWD_STATE
- PORT_CTRL_LATENCY
- PORT_CTRL_LEARN_STATE
- PORT_CTRL_LISTEN_STATE
- PORT_CTRL_NO_STP
- PORT_CTRL_RX_BCST_EN
- PORT_CTRL_RX_DISABLE
- PORT_CTRL_RX_MCST_EN
- PORT_CTRL_RX_UCST_EN
- PORT_CTRL_SFTRST
- PORT_CTRL_SFTRST_ACK
- PORT_CTRL_STAT
- PORT_CTRL_STAT_PAGE
- PORT_CTRL_STP_STATE_MASK
- PORT_CTRL_STP_STATE_S
- PORT_CTRL_TX_DISABLE
- PORT_C_MASK
- PORT_D
- PORT_DA
- PORT_DA830
- PORT_DATA
- PORT_DATABASE_24XX_SIZE
- PORT_DATABASE_SIZE
- PORT_DECODE_ERR_CNT
- PORT_DECODE_ERR_THRESH
- PORT_DEFAULT_VID
- PORT_DEVSLP
- PORT_DEVSLP_ADSE
- PORT_DEVSLP_DETO_OFFSET
- PORT_DEVSLP_DITO_OFFSET
- PORT_DEVSLP_DM_MASK
- PORT_DEVSLP_DM_OFFSET
- PORT_DEVSLP_DSP
- PORT_DEVSLP_MDAT_OFFSET
- PORT_DEV_ADDR
- PORT_DEV_INIT_MASK
- PORT_DEV_REMOVE
- PORT_DEV_SMP_INIT
- PORT_DEV_SMP_TRGT
- PORT_DEV_SSP_INIT
- PORT_DEV_SSP_TRGT
- PORT_DEV_STP_INIT
- PORT_DEV_STP_TRGT
- PORT_DEV_TRGT_MASK
- PORT_DEV_TYPE_MASK
- PORT_DFCR
- PORT_DFER
- PORT_DFT2_G4X
- PORT_DFT_I9XX
- PORT_DFWR
- PORT_DFX0
- PORT_DIAG
- PORT_DIFFSERV_ENABLE
- PORT_DIFFSERV_PRIO_ENABLE
- PORT_DIGICOLOR
- PORT_DIR_INPUT
- PORT_DIR_OUTPUT
- PORT_DISABLED
- PORT_DISCARD_EGRESS_ERRS
- PORT_DISCARD_NON_VID
- PORT_DISCONNECT_DET
- PORT_DONE
- PORT_DROP_NON_VLAN
- PORT_DROP_TAG
- PORT_DRVCR
- PORT_DRVCRA
- PORT_DRVCRB
- PORT_DZ
- PORT_E
- PORT_EFMUART
- PORT_EN
- PORT_ENABLE
- PORT_ENABLED
- PORT_ENABLE_JABBER
- PORT_ENERGY_DETECT
- PORT_ERROR
- PORT_ERROR_MASK
- PORT_ERROR_READ
- PORT_EVT_EN
- PORT_EVT_STST
- PORT_EXEC_DIAG
- PORT_EXEC_FIFO
- PORT_EXTENDED_CAPABILITY
- PORT_EXTENDED_STATUS
- PORT_F
- PORT_FATAL_ERROR_STATUS_BLE
- PORT_FATAL_ERROR_STATUS_EP0
- PORT_FATAL_ERROR_STATUS_EP1
- PORT_FATAL_ERROR_STATUS_ICE
- PORT_FATAL_ERROR_STATUS_IDE_RE
- PORT_FATAL_ERROR_STATUS_IDE_WE
- PORT_FATAL_ERROR_STATUS_IFB_RE
- PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0
- PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1
- PORT_FATAL_ERROR_STATUS_ILE
- PORT_FATAL_ERROR_STATUS_MA
- PORT_FATAL_ERROR_STATUS_MPE
- PORT_FATAL_ERROR_STATUS_OCE
- PORT_FATAL_ERROR_STATUS_ODE_RE
- PORT_FATAL_ERROR_STATUS_ODE_WE
- PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0
- PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1
- PORT_FATAL_ERROR_STATUS_OFB_WE
- PORT_FATAL_ERROR_STATUS_OPE
- PORT_FATAL_ERROR_STATUS_RPE
- PORT_FATAL_ERROR_STATUS_SCE
- PORT_FATAL_ERROR_STATUS_SDE_RE
- PORT_FATAL_ERROR_STATUS_SDE_WE
- PORT_FATAL_ERROR_STATUS_SPE
- PORT_FATAL_ERROR_STATUS_TA
- PORT_FBS
- PORT_FBS_ADO_OFFSET
- PORT_FBS_DEC
- PORT_FBS_DEV_MASK
- PORT_FBS_DEV_OFFSET
- PORT_FBS_DWE_OFFSET
- PORT_FBS_EN
- PORT_FBS_SDE
- PORT_FEATURE_BAR1_SIZE_128K
- PORT_FEATURE_BAR1_SIZE_128M
- PORT_FEATURE_BAR1_SIZE_16M
- PORT_FEATURE_BAR1_SIZE_1G
- PORT_FEATURE_BAR1_SIZE_1M
- PORT_FEATURE_BAR1_SIZE_256K
- PORT_FEATURE_BAR1_SIZE_256M
- PORT_FEATURE_BAR1_SIZE_2M
- PORT_FEATURE_BAR1_SIZE_32M
- PORT_FEATURE_BAR1_SIZE_4M
- PORT_FEATURE_BAR1_SIZE_512K
- PORT_FEATURE_BAR1_SIZE_512M
- PORT_FEATURE_BAR1_SIZE_64K
- PORT_FEATURE_BAR1_SIZE_64M
- PORT_FEATURE_BAR1_SIZE_8M
- PORT_FEATURE_BAR1_SIZE_DISABLED
- PORT_FEATURE_BAR1_SIZE_MASK
- PORT_FEATURE_BAR1_SIZE_SHIFT
- PORT_FEATURE_BAR2_SIZE_128K
- PORT_FEATURE_BAR2_SIZE_128M
- PORT_FEATURE_BAR2_SIZE_16M
- PORT_FEATURE_BAR2_SIZE_1G
- PORT_FEATURE_BAR2_SIZE_1M
- PORT_FEATURE_BAR2_SIZE_256K
- PORT_FEATURE_BAR2_SIZE_256M
- PORT_FEATURE_BAR2_SIZE_2M
- PORT_FEATURE_BAR2_SIZE_32M
- PORT_FEATURE_BAR2_SIZE_4M
- PORT_FEATURE_BAR2_SIZE_512K
- PORT_FEATURE_BAR2_SIZE_512M
- PORT_FEATURE_BAR2_SIZE_64K
- PORT_FEATURE_BAR2_SIZE_64M
- PORT_FEATURE_BAR2_SIZE_8M
- PORT_FEATURE_BAR2_SIZE_DISABLED
- PORT_FEATURE_BAR2_SIZE_MASK
- PORT_FEATURE_BAR2_SIZE_SHIFT
- PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT
- PORT_FEATURE_BMC_LINK_OVERRIDE_EN
- PORT_FEATURE_BMC_LINK_OVERRIDE_MASK
- PORT_FEATURE_CONNECTED_SWITCH_MASK
- PORT_FEATURE_CONNECTED_SWITCH_SHIFT
- PORT_FEATURE_CON_SWITCH_10G_SWITCH
- PORT_FEATURE_CON_SWITCH_1G_SWITCH
- PORT_FEATURE_CON_SWITCH_AUTO_DETECT
- PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
- PORT_FEATURE_EN_SIZE_MASK
- PORT_FEATURE_EN_SIZE_SHIFT
- PORT_FEATURE_FLOW_CONTROL_AUTO
- PORT_FEATURE_FLOW_CONTROL_BOTH
- PORT_FEATURE_FLOW_CONTROL_MASK
- PORT_FEATURE_FLOW_CONTROL_NONE
- PORT_FEATURE_FLOW_CONTROL_RX
- PORT_FEATURE_FLOW_CONTROL_SHIFT
- PORT_FEATURE_FLOW_CONTROL_TX
- PORT_FEATURE_ID_AFU
- PORT_FEATURE_ID_ERROR
- PORT_FEATURE_ID_HEADER
- PORT_FEATURE_ID_STP
- PORT_FEATURE_ID_UINT
- PORT_FEATURE_ID_UMSG
- PORT_FEATURE_LINK_SPEED_100M_FULL
- PORT_FEATURE_LINK_SPEED_100M_HALF
- PORT_FEATURE_LINK_SPEED_10G_CX4
- PORT_FEATURE_LINK_SPEED_10M_FULL
- PORT_FEATURE_LINK_SPEED_10M_HALF
- PORT_FEATURE_LINK_SPEED_1G
- PORT_FEATURE_LINK_SPEED_20G
- PORT_FEATURE_LINK_SPEED_2_5G
- PORT_FEATURE_LINK_SPEED_AUTO
- PORT_FEATURE_LINK_SPEED_MASK
- PORT_FEATURE_LINK_SPEED_SHIFT
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK
- PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL
- PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT
- PORT_FEATURE_MBA_BOOT_RETRY_MASK
- PORT_FEATURE_MBA_BOOT_RETRY_SHIFT
- PORT_FEATURE_MBA_ENABLED
- PORT_FEATURE_MBA_EXP_ROM_SIZE_128K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_16K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_16M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_1M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_256K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_2K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_2M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_32K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_32M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_4K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_4M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_512K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_64K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_8K
- PORT_FEATURE_MBA_EXP_ROM_SIZE_8M
- PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED
- PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK
- PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT
- PORT_FEATURE_MBA_HOTKEY_CTRL_B
- PORT_FEATURE_MBA_HOTKEY_CTRL_S
- PORT_FEATURE_MBA_HOTKEY_MASK
- PORT_FEATURE_MBA_LINK_SPEED_100FD
- PORT_FEATURE_MBA_LINK_SPEED_100HD
- PORT_FEATURE_MBA_LINK_SPEED_10FD
- PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4
- PORT_FEATURE_MBA_LINK_SPEED_10HD
- PORT_FEATURE_MBA_LINK_SPEED_1GBPS
- PORT_FEATURE_MBA_LINK_SPEED_20GBPS
- PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS
- PORT_FEATURE_MBA_LINK_SPEED_AUTO
- PORT_FEATURE_MBA_LINK_SPEED_MASK
- PORT_FEATURE_MBA_LINK_SPEED_SHIFT
- PORT_FEATURE_MBA_MSG_TIMEOUT_MASK
- PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT
- PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP
- PORT_FEATURE_MBA_RES_PAUSE_CAP
- PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE
- PORT_FEATURE_MBA_VLAN_EN
- PORT_FEATURE_MBA_VLAN_TAG_MASK
- PORT_FEATURE_MBA_VLAN_TAG_SHIFT
- PORT_FEATURE_MFW_ENABLED
- PORT_FEATURE_RESOURCE_CFG_DIAG
- PORT_FEATURE_RESOURCE_CFG_ISCSI
- PORT_FEATURE_RESOURCE_CFG_L2
- PORT_FEATURE_RESOURCE_CFG_RDMA
- PORT_FEATURE_RESOURCE_CFG_VALID
- PORT_FEATURE_SMBUS_ADDR_MASK
- PORT_FEATURE_SMBUS_ADDR_SHIFT
- PORT_FEATURE_WOL_ACPI_UPON_MGMT
- PORT_FEATURE_WOL_DEFAULT_ACPI
- PORT_FEATURE_WOL_DEFAULT_DISABLE
- PORT_FEATURE_WOL_DEFAULT_MAGIC
- PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI
- PORT_FEATURE_WOL_DEFAULT_MASK
- PORT_FEATURE_WOL_DEFAULT_SHIFT
- PORT_FEATURE_WOL_ENABLED
- PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP
- PORT_FEATURE_WOL_RES_PAUSE_CAP
- PORT_FEAT_CFG_DCBX_DISABLED
- PORT_FEAT_CFG_DCBX_ENABLED
- PORT_FEAT_CFG_DCBX_MASK
- PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
- PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
- PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
- PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
- PORT_FEAT_CFG_EEE_POWER_MODE_MASK
- PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
- PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED
- PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED
- PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT
- PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG
- PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE
- PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI
- PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
- PORT_FEAT_CFG_VF_BAR2_SIZE_128K
- PORT_FEAT_CFG_VF_BAR2_SIZE_16K
- PORT_FEAT_CFG_VF_BAR2_SIZE_16M
- PORT_FEAT_CFG_VF_BAR2_SIZE_1M
- PORT_FEAT_CFG_VF_BAR2_SIZE_256K
- PORT_FEAT_CFG_VF_BAR2_SIZE_2M
- PORT_FEAT_CFG_VF_BAR2_SIZE_32K
- PORT_FEAT_CFG_VF_BAR2_SIZE_32M
- PORT_FEAT_CFG_VF_BAR2_SIZE_4K
- PORT_FEAT_CFG_VF_BAR2_SIZE_4M
- PORT_FEAT_CFG_VF_BAR2_SIZE_512K
- PORT_FEAT_CFG_VF_BAR2_SIZE_64K
- PORT_FEAT_CFG_VF_BAR2_SIZE_64M
- PORT_FEAT_CFG_VF_BAR2_SIZE_8K
- PORT_FEAT_CFG_VF_BAR2_SIZE_8M
- PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED
- PORT_FEAT_CFG_VF_BAR2_SIZE_MASK
- PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT
- PORT_FIBER_MODE
- PORT_FIBRE
- PORT_FIFO_THRES
- PORT_FIRST_ERROR
- PORT_FIS_ADDR
- PORT_FIS_ADDR_HI
- PORT_FIS_CFG
- PORT_FORCE_100_MBIT
- PORT_FORCE_FLOW_CTRL
- PORT_FORCE_FULL_DUPLEX
- PORT_FORCE_LINK
- PORT_FORCE_MDIX
- PORT_FORCE_RX_FLOW_CTRL
- PORT_FORCE_TX_FLOW_CTRL
- PORT_FULL_DUPLEX
- PORT_FULL_MASK
- PORT_FWD_TYPE_PASSTHRU
- PORT_FWD_TYPE_VEB
- PORT_FWD_TYPE_VEPA
- PORT_G
- PORT_GMII_1GPS_MODE
- PORT_GMII_MAC_MODE
- PORT_GMII_SEL
- PORT_GMII_SEL_S1
- PORT_GP_1
- PORT_GP_10
- PORT_GP_11
- PORT_GP_12
- PORT_GP_14
- PORT_GP_15
- PORT_GP_16
- PORT_GP_17
- PORT_GP_18
- PORT_GP_20
- PORT_GP_21
- PORT_GP_22
- PORT_GP_23
- PORT_GP_24
- PORT_GP_25
- PORT_GP_26
- PORT_GP_27
- PORT_GP_28
- PORT_GP_29
- PORT_GP_30
- PORT_GP_32
- PORT_GP_32_REV
- PORT_GP_4
- PORT_GP_6
- PORT_GP_8
- PORT_GP_9
- PORT_GP_CFG_1
- PORT_GP_CFG_10
- PORT_GP_CFG_11
- PORT_GP_CFG_12
- PORT_GP_CFG_14
- PORT_GP_CFG_15
- PORT_GP_CFG_16
- PORT_GP_CFG_17
- PORT_GP_CFG_18
- PORT_GP_CFG_20
- PORT_GP_CFG_21
- PORT_GP_CFG_22
- PORT_GP_CFG_23
- PORT_GP_CFG_24
- PORT_GP_CFG_25
- PORT_GP_CFG_26
- PORT_GP_CFG_27
- PORT_GP_CFG_28
- PORT_GP_CFG_29
- PORT_GP_CFG_30
- PORT_GP_CFG_32
- PORT_GP_CFG_4
- PORT_GP_CFG_6
- PORT_GP_CFG_8
- PORT_GP_CFG_9
- PORT_GP_PUP_1
- PORT_GRXC_ENABLE
- PORT_H
- PORT_HASH_BITS
- PORT_HASH_SIZE
- PORT_HDCP_ANHI
- PORT_HDCP_ANINIT
- PORT_HDCP_ANLO
- PORT_HDCP_BKSVHI
- PORT_HDCP_BKSVLO
- PORT_HDCP_CONF
- PORT_HDCP_RPRIME
- PORT_HDCP_STATUS
- PORT_HDR_CAP
- PORT_HDR_CTRL
- PORT_HDR_DFH
- PORT_HDR_GUID_H
- PORT_HDR_GUID_L
- PORT_HDR_NEXT_AFU
- PORT_HDR_STS
- PORT_HDR_USRCLK_CMD0
- PORT_HDR_USRCLK_CMD1
- PORT_HDR_USRCLK_STS0
- PORT_HDR_USRCLK_STS1
- PORT_HIGHEST_PRIO
- PORT_HIRD
- PORT_HIRDM
- PORT_HIRD_MASK
- PORT_HIZA
- PORT_HIZCRA
- PORT_HIZCRB
- PORT_HIZCRC
- PORT_HLE
- PORT_HOTPLUG_EN
- PORT_HOTPLUG_STAT
- PORT_HP_MDIX
- PORT_HSCIF
- PORT_HSHK_ERR_CNT
- PORT_HSHK_ERR_THRESH
- PORT_HSIC
- PORT_HW_CFG_E3_FAULT_MDL_LED_MASK
- PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT
- PORT_HW_CFG_E3_I2C_MUX0_MASK
- PORT_HW_CFG_E3_I2C_MUX1_MASK
- PORT_HW_CFG_E3_MOD_ABS_MASK
- PORT_HW_CFG_E3_MOD_ABS_SHIFT
- PORT_HW_CFG_E3_OVER_CURRENT_MASK
- PORT_HW_CFG_E3_OVER_CURRENT_SHIFT
- PORT_HW_CFG_E3_PHY_RESET_MASK
- PORT_HW_CFG_E3_PHY_RESET_SHIFT
- PORT_HW_CFG_E3_PWR_DIS_MASK
- PORT_HW_CFG_E3_PWR_DIS_SHIFT
- PORT_HW_CFG_E3_PWR_DOWN_MASK
- PORT_HW_CFG_E3_PWR_DOWN_SHIFT
- PORT_HW_CFG_E3_TX_FAULT_MASK
- PORT_HW_CFG_E3_TX_FAULT_SHIFT
- PORT_HW_CFG_E3_TX_LASER_MASK
- PORT_HW_CFG_E3_TX_LASER_SHIFT
- PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED
- PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
- PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK
- PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT
- PORT_HW_CFG_ENABLE_CMS_DISABLED
- PORT_HW_CFG_ENABLE_CMS_ENABLED
- PORT_HW_CFG_ENABLE_CMS_MASK
- PORT_HW_CFG_ENABLE_CMS_SHIFT
- PORT_HW_CFG_ENABLE_FLR_MASK
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0
- PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1
- PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK
- PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE
- PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT
- PORT_HW_CFG_FAULT_MODULE_LED_DISABLED
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO1
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO2
- PORT_HW_CFG_FAULT_MODULE_LED_GPIO3
- PORT_HW_CFG_FAULT_MODULE_LED_MASK
- PORT_HW_CFG_FAULT_MODULE_LED_SHIFT
- PORT_HW_CFG_FCOE_UPPERMAC_MASK
- PORT_HW_CFG_FCOE_UPPERMAC_SHIFT
- PORT_HW_CFG_FLR_ENABLED
- PORT_HW_CFG_FORCE_KR_ENABLER_FORCED
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0
- PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1
- PORT_HW_CFG_FORCE_KR_ENABLER_MASK
- PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED
- PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT
- PORT_HW_CFG_GPIO0_CONFIG_HIGH
- PORT_HW_CFG_GPIO0_CONFIG_INPUT
- PORT_HW_CFG_GPIO0_CONFIG_LOW
- PORT_HW_CFG_GPIO0_CONFIG_MASK
- PORT_HW_CFG_GPIO0_CONFIG_NA
- PORT_HW_CFG_GPIO0_CONFIG_SHIFT
- PORT_HW_CFG_GPIO1_CONFIG_HIGH
- PORT_HW_CFG_GPIO1_CONFIG_INPUT
- PORT_HW_CFG_GPIO1_CONFIG_LOW
- PORT_HW_CFG_GPIO1_CONFIG_MASK
- PORT_HW_CFG_GPIO1_CONFIG_NA
- PORT_HW_CFG_GPIO1_CONFIG_SHIFT
- PORT_HW_CFG_GPIO2_CONFIG_HIGH
- PORT_HW_CFG_GPIO2_CONFIG_INPUT
- PORT_HW_CFG_GPIO2_CONFIG_LOW
- PORT_HW_CFG_GPIO2_CONFIG_MASK
- PORT_HW_CFG_GPIO2_CONFIG_NA
- PORT_HW_CFG_GPIO2_CONFIG_SHIFT
- PORT_HW_CFG_GPIO3_CONFIG_HIGH
- PORT_HW_CFG_GPIO3_CONFIG_INPUT
- PORT_HW_CFG_GPIO3_CONFIG_LOW
- PORT_HW_CFG_GPIO3_CONFIG_MASK
- PORT_HW_CFG_GPIO3_CONFIG_NA
- PORT_HW_CFG_GPIO3_CONFIG_SHIFT
- PORT_HW_CFG_LANE_SWAP_CFG_01230123
- PORT_HW_CFG_LANE_SWAP_CFG_01233210
- PORT_HW_CFG_LANE_SWAP_CFG_31203120
- PORT_HW_CFG_LANE_SWAP_CFG_32103210
- PORT_HW_CFG_LANE_SWAP_CFG_MASK
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
- PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
- PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
- PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
- PORT_HW_CFG_LANE_SWAP_CFG_SHIFT
- PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
- PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
- PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
- PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT
- PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK
- PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
- PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK
- PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT
- PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK
- PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT
- PORT_HW_CFG_NET_SERDES_IF_DXGXS
- PORT_HW_CFG_NET_SERDES_IF_KR
- PORT_HW_CFG_NET_SERDES_IF_KR2
- PORT_HW_CFG_NET_SERDES_IF_MASK
- PORT_HW_CFG_NET_SERDES_IF_SFI
- PORT_HW_CFG_NET_SERDES_IF_SGMII
- PORT_HW_CFG_NET_SERDES_IF_SHIFT
- PORT_HW_CFG_NET_SERDES_IF_XFI
- PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED
- PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
- PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK
- PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT
- PORT_HW_CFG_PCI_DEVICE_ID_MASK
- PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK
- PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK
- PORT_HW_CFG_PCI_VENDOR_ID_MASK
- PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK
- PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT
- PORT_HW_CFG_PF_NUM_VF_MASK
- PORT_HW_CFG_PF_NUM_VF_SHIFT
- PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
- PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
- PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
- PORT_HW_CFG_PHY_SELECTION_MASK
- PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
- PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
- PORT_HW_CFG_PHY_SELECTION_SHIFT
- PORT_HW_CFG_PHY_SWAPPED_DISABLED
- PORT_HW_CFG_PHY_SWAPPED_ENABLED
- PORT_HW_CFG_PHY_SWAPPED_MASK
- PORT_HW_CFG_PHY_SWAPPED_SHIFT
- PORT_HW_CFG_POWER_CONS_D0_MASK
- PORT_HW_CFG_POWER_CONS_D0_SHIFT
- PORT_HW_CFG_POWER_CONS_D1_MASK
- PORT_HW_CFG_POWER_CONS_D1_SHIFT
- PORT_HW_CFG_POWER_CONS_D2_MASK
- PORT_HW_CFG_POWER_CONS_D2_SHIFT
- PORT_HW_CFG_POWER_CONS_D3_MASK
- PORT_HW_CFG_POWER_CONS_D3_SHIFT
- PORT_HW_CFG_POWER_DIS_D0_MASK
- PORT_HW_CFG_POWER_DIS_D0_SHIFT
- PORT_HW_CFG_POWER_DIS_D1_MASK
- PORT_HW_CFG_POWER_DIS_D1_SHIFT
- PORT_HW_CFG_POWER_DIS_D2_MASK
- PORT_HW_CFG_POWER_DIS_D2_SHIFT
- PORT_HW_CFG_POWER_DIS_D3_MASK
- PORT_HW_CFG_POWER_DIS_D3_SHIFT
- PORT_HW_CFG_RJ45_PAIR_SWAP_MASK
- PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT
- PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK
- PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
- PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT
- PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK
- PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT
- PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK
- PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK
- PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT
- PORT_HW_CFG_SPEED_CAPABILITY2_D0__
- PORT_HW_CFG_SPEED_CAPABILITY2_D0___
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK
- PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT
- PORT_HW_CFG_SPEED_CAPABILITY2_D3__
- PORT_HW_CFG_SPEED_CAPABILITY2_D3___
- PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
- PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
- PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
- PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
- PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
- PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED
- PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT
- PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF
- PORT_HW_CFG_SPEED_CAPABILITY_D3_10G
- PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL
- PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF
- PORT_HW_CFG_SPEED_CAPABILITY_D3_1G
- PORT_HW_CFG_SPEED_CAPABILITY_D3_20G
- PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G
- PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK
- PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED
- PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT
- PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED
- PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
- PORT_HW_CFG_SWAP_PHY_POLARITY_MASK
- PORT_HW_CFG_TX_DRV_BROADCAST_MASK
- PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT
- PORT_HW_CFG_TX_DRV_IFIR_MASK
- PORT_HW_CFG_TX_DRV_IFIR_SHIFT
- PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK
- PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT
- PORT_HW_CFG_TX_DRV_POST2_MASK
- PORT_HW_CFG_TX_DRV_POST2_SHIFT
- PORT_HW_CFG_TX_EQUALIZATION_MASK
- PORT_HW_CFG_TX_EQUALIZATION_SHIFT
- PORT_HW_CFG_TX_LASER_GPIO0
- PORT_HW_CFG_TX_LASER_GPIO1
- PORT_HW_CFG_TX_LASER_GPIO2
- PORT_HW_CFG_TX_LASER_GPIO3
- PORT_HW_CFG_TX_LASER_MASK
- PORT_HW_CFG_TX_LASER_MDIO
- PORT_HW_CFG_TX_LASER_SHIFT
- PORT_HW_CFG_UPPERMAC_MASK
- PORT_HW_CFG_UPPERMAC_SHIFT
- PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK
- PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT
- PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK
- PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT
- PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK
- PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101
- PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK
- PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
- PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT
- PORT_I
- PORT_ICOM
- PORT_IC_OFFSET_UNITS
- PORT_ID
- PORT_ID0
- PORT_ID1
- PORT_IDMA_CTL
- PORT_IDMA_STAT
- PORT_IDPB
- PORT_IDPC
- PORT_IDPD
- PORT_ID_BYTE_LEN
- PORT_ID_PTR
- PORT_IMX
- PORT_IN
- PORT_INFO
- PORT_INGRESS_ALL
- PORT_INGRESS_BROADCAST
- PORT_INGRESS_FILTER
- PORT_INGRESS_LIMIT_MODE
- PORT_INGRESS_MULTICAST
- PORT_INGRESS_UNICAST
- PORT_INGRESS_VLAN_FILTER
- PORT_INIT_PORT
- PORT_INIT_TGT_PORT
- PORT_INPUT
- PORT_INSERT_TAG
- PORT_INS_TAG_FOR_PORT_2
- PORT_INS_TAG_FOR_PORT_3
- PORT_INS_TAG_FOR_PORT_4
- PORT_INS_TAG_FOR_PORT_5
- PORT_INS_TAG_FOR_PORT_5_S
- PORT_INTER
- PORT_INTERFACE_GMII
- PORT_INTERFACE_MII
- PORT_INTERFACE_RGMII
- PORT_INTERFACE_RMII
- PORT_INTERFACE_TYPE
- PORT_INTF_FULL_DUPLEX
- PORT_INTF_SPEED_M
- PORT_INTF_SPEED_S
- PORT_INT_EITHER_EDGE
- PORT_INT_FALLING_EDGE
- PORT_INT_LOGIC_ONE
- PORT_INT_LOGIC_ZERO
- PORT_INT_MASK
- PORT_INT_OFF
- PORT_INT_PIN_HIGH
- PORT_INT_RISING_EDGE
- PORT_INVALID
- PORT_IN_ALL
- PORT_IN_BROADCAST
- PORT_IN_FLOW_CTRL
- PORT_IN_FLOW_CTRL_S
- PORT_IN_LIMIT_MODE_M
- PORT_IN_LIMIT_MODE_S
- PORT_IN_MULTICAST
- PORT_IN_PACKET_BASED
- PORT_IN_PORT_BASED
- PORT_IN_PORT_BASED_S
- PORT_IN_RATE_ENABLE
- PORT_IN_RESET
- PORT_IN_UNICAST
- PORT_IO
- PORT_IP22ZILOG
- PORT_IRDA
- PORT_IRQ_8B10B
- PORT_IRQ_BAD_PMP
- PORT_IRQ_COLD_PRES
- PORT_IRQ_COMPLETE
- PORT_IRQ_COMWAKE
- PORT_IRQ_CONNECT
- PORT_IRQ_CRC
- PORT_IRQ_D2H_REG_FIS
- PORT_IRQ_DEV_ILCK
- PORT_IRQ_DEV_XCHG
- PORT_IRQ_DMAS_FIS
- PORT_IRQ_ENABLE_CLR
- PORT_IRQ_ENABLE_SET
- PORT_IRQ_ERR
- PORT_IRQ_ERROR
- PORT_IRQ_FREEZE
- PORT_IRQ_HANDLED
- PORT_IRQ_HANDSHAKE
- PORT_IRQ_HBUS_DATA_ERR
- PORT_IRQ_HBUS_ERR
- PORT_IRQ_IF_ERR
- PORT_IRQ_IF_NONFATAL
- PORT_IRQ_LEGACY
- PORT_IRQ_MASK
- PORT_IRQ_MASKED_MASK
- PORT_IRQ_OVERFLOW
- PORT_IRQ_PHYRDY
- PORT_IRQ_PHYRDY_CHG
- PORT_IRQ_PIOS_FIS
- PORT_IRQ_PORTRDY_CHG
- PORT_IRQ_PWR_CHG
- PORT_IRQ_RAW_MASK
- PORT_IRQ_RAW_SHIFT
- PORT_IRQ_SDB_FIS
- PORT_IRQ_SDB_NOTIFY
- PORT_IRQ_SG_DONE
- PORT_IRQ_STAT
- PORT_IRQ_STEER_MASK
- PORT_IRQ_STEER_SHIFT
- PORT_IRQ_TF_ERR
- PORT_IRQ_UNK_FIS
- PORT_ISAKMP
- PORT_ISFR
- PORT_ISOLATE
- PORT_JABBER_DETECT
- PORT_JSM
- PORT_JUMBO_FRAME
- PORT_L0_EXIT
- PORT_L1DS
- PORT_L1DS_MASK
- PORT_L1S_MASK
- PORT_L1S_SUCCESS
- PORT_L1_TIMEOUT
- PORT_LEARN_DISABLE
- PORT_LED_AMBER
- PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF
- PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON
- PORT_LED_CFG_REQ_ENABLES_LED0_COLOR
- PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID
- PORT_LED_CFG_REQ_ENABLES_LED0_ID
- PORT_LED_CFG_REQ_ENABLES_LED0_STATE
- PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF
- PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON
- PORT_LED_CFG_REQ_ENABLES_LED1_COLOR
- PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID
- PORT_LED_CFG_REQ_ENABLES_LED1_ID
- PORT_LED_CFG_REQ_ENABLES_LED1_STATE
- PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF
- PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON
- PORT_LED_CFG_REQ_ENABLES_LED2_COLOR
- PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID
- PORT_LED_CFG_REQ_ENABLES_LED2_ID
- PORT_LED_CFG_REQ_ENABLES_LED2_STATE
- PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF
- PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON
- PORT_LED_CFG_REQ_ENABLES_LED3_COLOR
- PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID
- PORT_LED_CFG_REQ_ENABLES_LED3_ID
- PORT_LED_CFG_REQ_ENABLES_LED3_STATE
- PORT_LED_CFG_REQ_LED0_COLOR_AMBER
- PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT
- PORT_LED_CFG_REQ_LED0_COLOR_GREEN
- PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER
- PORT_LED_CFG_REQ_LED0_COLOR_LAST
- PORT_LED_CFG_REQ_LED0_STATE_BLINK
- PORT_LED_CFG_REQ_LED0_STATE_BLINKALT
- PORT_LED_CFG_REQ_LED0_STATE_DEFAULT
- PORT_LED_CFG_REQ_LED0_STATE_LAST
- PORT_LED_CFG_REQ_LED0_STATE_OFF
- PORT_LED_CFG_REQ_LED0_STATE_ON
- PORT_LED_CFG_REQ_LED1_COLOR_AMBER
- PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT
- PORT_LED_CFG_REQ_LED1_COLOR_GREEN
- PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER
- PORT_LED_CFG_REQ_LED1_COLOR_LAST
- PORT_LED_CFG_REQ_LED1_STATE_BLINK
- PORT_LED_CFG_REQ_LED1_STATE_BLINKALT
- PORT_LED_CFG_REQ_LED1_STATE_DEFAULT
- PORT_LED_CFG_REQ_LED1_STATE_LAST
- PORT_LED_CFG_REQ_LED1_STATE_OFF
- PORT_LED_CFG_REQ_LED1_STATE_ON
- PORT_LED_CFG_REQ_LED2_COLOR_AMBER
- PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT
- PORT_LED_CFG_REQ_LED2_COLOR_GREEN
- PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER
- PORT_LED_CFG_REQ_LED2_COLOR_LAST
- PORT_LED_CFG_REQ_LED2_STATE_BLINK
- PORT_LED_CFG_REQ_LED2_STATE_BLINKALT
- PORT_LED_CFG_REQ_LED2_STATE_DEFAULT
- PORT_LED_CFG_REQ_LED2_STATE_LAST
- PORT_LED_CFG_REQ_LED2_STATE_OFF
- PORT_LED_CFG_REQ_LED2_STATE_ON
- PORT_LED_CFG_REQ_LED3_COLOR_AMBER
- PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT
- PORT_LED_CFG_REQ_LED3_COLOR_GREEN
- PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER
- PORT_LED_CFG_REQ_LED3_COLOR_LAST
- PORT_LED_CFG_REQ_LED3_STATE_BLINK
- PORT_LED_CFG_REQ_LED3_STATE_BLINKALT
- PORT_LED_CFG_REQ_LED3_STATE_DEFAULT
- PORT_LED_CFG_REQ_LED3_STATE_LAST
- PORT_LED_CFG_REQ_LED3_STATE_OFF
- PORT_LED_CFG_REQ_LED3_STATE_ON
- PORT_LED_CTRL
- PORT_LED_CTRL_TEST
- PORT_LED_GREEN
- PORT_LED_MASK
- PORT_LED_OFF
- PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD
- PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED
- PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED
- PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY
- PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID
- PORT_LED_QCAPS_RESP_LED0_TYPE_LAST
- PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED
- PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD
- PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED
- PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED
- PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY
- PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID
- PORT_LED_QCAPS_RESP_LED1_TYPE_LAST
- PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED
- PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD
- PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED
- PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED
- PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY
- PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID
- PORT_LED_QCAPS_RESP_LED2_TYPE_LAST
- PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED
- PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD
- PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED
- PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED
- PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY
- PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID
- PORT_LED_QCAPS_RESP_LED3_TYPE_LAST
- PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED
- PORT_LED_QCFG_RESP_LED0_COLOR_AMBER
- PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT
- PORT_LED_QCFG_RESP_LED0_COLOR_GREEN
- PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER
- PORT_LED_QCFG_RESP_LED0_COLOR_LAST
- PORT_LED_QCFG_RESP_LED0_STATE_BLINK
- PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT
- PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT
- PORT_LED_QCFG_RESP_LED0_STATE_LAST
- PORT_LED_QCFG_RESP_LED0_STATE_OFF
- PORT_LED_QCFG_RESP_LED0_STATE_ON
- PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY
- PORT_LED_QCFG_RESP_LED0_TYPE_INVALID
- PORT_LED_QCFG_RESP_LED0_TYPE_LAST
- PORT_LED_QCFG_RESP_LED0_TYPE_SPEED
- PORT_LED_QCFG_RESP_LED1_COLOR_AMBER
- PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT
- PORT_LED_QCFG_RESP_LED1_COLOR_GREEN
- PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER
- PORT_LED_QCFG_RESP_LED1_COLOR_LAST
- PORT_LED_QCFG_RESP_LED1_STATE_BLINK
- PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT
- PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT
- PORT_LED_QCFG_RESP_LED1_STATE_LAST
- PORT_LED_QCFG_RESP_LED1_STATE_OFF
- PORT_LED_QCFG_RESP_LED1_STATE_ON
- PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY
- PORT_LED_QCFG_RESP_LED1_TYPE_INVALID
- PORT_LED_QCFG_RESP_LED1_TYPE_LAST
- PORT_LED_QCFG_RESP_LED1_TYPE_SPEED
- PORT_LED_QCFG_RESP_LED2_COLOR_AMBER
- PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT
- PORT_LED_QCFG_RESP_LED2_COLOR_GREEN
- PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER
- PORT_LED_QCFG_RESP_LED2_COLOR_LAST
- PORT_LED_QCFG_RESP_LED2_STATE_BLINK
- PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT
- PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT
- PORT_LED_QCFG_RESP_LED2_STATE_LAST
- PORT_LED_QCFG_RESP_LED2_STATE_OFF
- PORT_LED_QCFG_RESP_LED2_STATE_ON
- PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY
- PORT_LED_QCFG_RESP_LED2_TYPE_INVALID
- PORT_LED_QCFG_RESP_LED2_TYPE_LAST
- PORT_LED_QCFG_RESP_LED2_TYPE_SPEED
- PORT_LED_QCFG_RESP_LED3_COLOR_AMBER
- PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT
- PORT_LED_QCFG_RESP_LED3_COLOR_GREEN
- PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER
- PORT_LED_QCFG_RESP_LED3_COLOR_LAST
- PORT_LED_QCFG_RESP_LED3_STATE_BLINK
- PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT
- PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT
- PORT_LED_QCFG_RESP_LED3_STATE_LAST
- PORT_LED_QCFG_RESP_LED3_STATE_OFF
- PORT_LED_QCFG_RESP_LED3_STATE_ON
- PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY
- PORT_LED_QCFG_RESP_LED3_TYPE_INVALID
- PORT_LED_QCFG_RESP_LED3_TYPE_LAST
- PORT_LED_QCFG_RESP_LED3_TYPE_SPEED
- PORT_LED_SELECT
- PORT_LH7A40X
- PORT_LINFLEXUART
- PORT_LINK_DETECT
- PORT_LINK_MD_10BT_ENABLE
- PORT_LINK_MD_PASS
- PORT_LINK_MODE
- PORT_LINK_MODE_1_LANES
- PORT_LINK_MODE_2_LANES
- PORT_LINK_MODE_4_LANES
- PORT_LINK_MODE_8_LANES
- PORT_LINK_MODE_MASK
- PORT_LINK_STATUS
- PORT_LINK_STATUS_FAIL
- PORT_LINK_STROBE
- PORT_LINK_UP_DETECT
- PORT_LOCAL_MASTER
- PORT_LOCAL_RX_OK
- PORT_LOGIC_ACK_F_ASPM_CTRL
- PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT
- PORT_LOGIC_GEN2_CTRL
- PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE
- PORT_LOGIC_LINK_WIDTH
- PORT_LOGIC_LINK_WIDTH_1_LANES
- PORT_LOGIC_LINK_WIDTH_2_LANES
- PORT_LOGIC_LINK_WIDTH_4_LANES
- PORT_LOGIC_LINK_WIDTH_8_LANES
- PORT_LOGIC_LINK_WIDTH_MASK
- PORT_LOGIC_LTSSM_STATE_L0
- PORT_LOGIC_LTSSM_STATE_MASK
- PORT_LOGIC_MSIX_DOORBELL
- PORT_LOGIC_MSI_CTRL_INT_0_EN
- PORT_LOGIC_SPEED_CHANGE
- PORT_LOOPBACK
- PORT_LOSTCOMM
- PORT_LPC3220
- PORT_LPM
- PORT_LPT
- PORT_LPUART
- PORT_LRAM
- PORT_LRAM_SLOT_SZ
- PORT_LST_ADDR
- PORT_LST_ADDR_HI
- PORT_LTP_CRC_MODE_14
- PORT_LTP_CRC_MODE_16
- PORT_LTP_CRC_MODE_48
- PORT_LTP_CRC_MODE_NONE
- PORT_LTP_CRC_MODE_PER_LANE
- PORT_LTQ_ASC
- PORT_M
- PORT_M32R_SIO
- PORT_MAC_BASED_802_1X
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT
- PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
- PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG
- PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI
- PORT_MAC_CFG_REQ_ENABLES_IPG
- PORT_MAC_CFG_REQ_ENABLES_LPBK
- PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB
- PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE
- PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI
- PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE
- PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI
- PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE
- PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK
- PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE
- PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS
- PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE
- PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE
- PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE
- PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE
- PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE
- PORT_MAC_CFG_REQ_LPBK_LAST
- PORT_MAC_CFG_REQ_LPBK_LOCAL
- PORT_MAC_CFG_REQ_LPBK_NONE
- PORT_MAC_CFG_REQ_LPBK_REMOTE
- PORT_MAC_CFG_RESP_LPBK_LAST
- PORT_MAC_CFG_RESP_LPBK_LOCAL
- PORT_MAC_CFG_RESP_LPBK_NONE
- PORT_MAC_CFG_RESP_LPBK_REMOTE
- PORT_MAC_LOOPBACK
- PORT_MAC_PRIO_ENABLE
- PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS
- PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS
- PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS
- PORT_MAC_ZILOG
- PORT_MAGIC_PACKET_DETECT
- PORT_MALFORMED_REQ0
- PORT_MALFORMED_REQ1
- PORT_MAP
- PORT_MAP_MASK
- PORT_MASK
- PORT_MASTER_FAULT
- PORT_MAX
- PORT_MAX3100
- PORT_MAX310X
- PORT_MCF
- PORT_MC_ADDR_HIGH
- PORT_MC_ADDR_LOW
- PORT_MDIX_STATUS
- PORT_MDM
- PORT_MEM
- PORT_MEM_MASK
- PORT_MEM_SHFT
- PORT_MEM_SIZE
- PORT_MEN_Z135
- PORT_MESON
- PORT_MF_CFG_E1HOV_TAG_DEFAULT
- PORT_MF_CFG_E1HOV_TAG_MASK
- PORT_MF_CFG_E1HOV_TAG_SHIFT
- PORT_MF_CFG_OV_TAG_DEFAULT
- PORT_MF_CFG_OV_TAG_MASK
- PORT_MF_CFG_OV_TAG_SHIFT
- PORT_MII
- PORT_MII_1000MBIT_S1
- PORT_MII_100MBIT
- PORT_MII_FULL_DUPLEX
- PORT_MII_INTERNAL_CLOCK
- PORT_MII_MAC_MODE
- PORT_MII_NOT_1GBIT
- PORT_MII_SEL
- PORT_MII_SEL_EDGE
- PORT_MII_SEL_M
- PORT_MII_SEL_S1
- PORT_MII_SUPPRESS_CAPABLE
- PORT_MIRROR_RX
- PORT_MIRROR_SNIFFER
- PORT_MIRROR_TX
- PORT_MLB_USIO
- PORT_MMD_DEVICE_ID_M
- PORT_MMD_OP_DATA_INCR_RW
- PORT_MMD_OP_DATA_INCR_W
- PORT_MMD_OP_DATA_NO_INCR
- PORT_MMD_OP_INDEX
- PORT_MMD_OP_MODE_M
- PORT_MMD_OP_MODE_S
- PORT_MN10300
- PORT_MN10300_CTS
- PORT_MODE
- PORT_MODE_EXT_EPHY
- PORT_MODE_EXT_GPHY
- PORT_MODE_EXT_RVMII_25
- PORT_MODE_EXT_RVMII_50
- PORT_MODE_INT_EPHY
- PORT_MODE_INT_GPHY
- PORT_MODE_MASK
- PORT_MODE_SHIFT
- PORT_MODULE_EVENT_ERROR_TYPE_MASK
- PORT_MODULE_EVENT_MODULE_STATUS_MASK
- PORT_MPC52xx
- PORT_MPS2UART
- PORT_MPSC
- PORT_MRFLD
- PORT_MSELCRA
- PORT_MSELCRB
- PORT_MSM
- PORT_MTK_BTIF
- PORT_MUX
- PORT_MVEBU
- PORT_NONE
- PORT_NOT_ESTABLISHED
- PORT_NPCM
- PORT_NS16550A
- PORT_NTESTS_SHIFT
- PORT_NUMBER_MASK
- PORT_NUMBER_SHIFT
- PORT_NUM_BLK
- PORT_NUM_EVENTS
- PORT_NWPSERIAL
- PORT_OC
- PORT_OCC
- PORT_OCTEON
- PORT_OFFSET
- PORT_OMAP
- PORT_OPENDRAIN
- PORT_OR_PRIO
- PORT_OTHER
- PORT_OUT
- PORT_OUTPUT
- PORT_OUT_RATE_ENABLE
- PORT_OVERRIDE_EN
- PORT_OVERRIDE_FULL_DUPLEX
- PORT_OVERRIDE_LINK
- PORT_OVERRIDE_RV_MII_25
- PORT_OVERRIDE_RX_FLOW
- PORT_OVERRIDE_SPEED_1000M
- PORT_OVERRIDE_SPEED_100M
- PORT_OVERRIDE_SPEED_10M
- PORT_OVERRIDE_SPEED_2000M
- PORT_OVERRIDE_SPEED_S
- PORT_OVERRIDE_TX_FLOW
- PORT_OWL
- PORT_OWNER
- PORT_PACR
- PORT_PADR
- PORT_PASS_ALL
- PORT_PATA0
- PORT_PATA1
- PORT_PATTERN
- PORT_PBCR
- PORT_PBDR
- PORT_PCCR
- PORT_PCDR
- PORT_PCH_2LINE
- PORT_PCH_8LINE
- PORT_PCR
- PORT_PCR_IRQC_OFFSET
- PORT_PDCR
- PORT_PDDR
- PORT_PE
- PORT_PEC
- PORT_PECR
- PORT_PEDR
- PORT_PFCR
- PORT_PFDR
- PORT_PGCR
- PORT_PGDR
- PORT_PHCR
- PORT_PHDR
- PORT_PHY1
- PORT_PHY2
- PORT_PHY3
- PORT_PHY4
- PORT_PHY5
- PORT_PHY_1000_STATIC_STATUS
- PORT_PHY_AUTO_MDIX_DISABLE
- PORT_PHY_CFG
- PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED
- PORT_PHY_CFG_CMD_ERR_CODE_LAST
- PORT_PHY_CFG_CMD_ERR_CODE_RETRY
- PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN
- PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
- PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
- PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF
- PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB
- PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB
- PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS
- PORT_PHY_CFG_REQ_AUTO_MODE_LAST
- PORT_PHY_CFG_REQ_AUTO_MODE_NONE
- PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW
- PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED
- PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
- PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE
- PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
- PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3
- PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4
- PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
- PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED
- PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
- PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
- PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
- PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK
- PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
- PORT_PHY_CFG_REQ_ENABLES_LPBK
- PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS
- PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER
- PORT_PHY_CFG_REQ_ENABLES_WIRESPEED
- PORT_PHY_CFG_REQ_FLAGS_DEPRECATED
- PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE
- PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE
- PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE
- PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE
- PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE
- PORT_PHY_CFG_REQ_FLAGS_FORCE
- PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN
- PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
- PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB
- PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST
- PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
- PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
- PORT_PHY_CFG_REQ_LPBK_EXTERNAL
- PORT_PHY_CFG_REQ_LPBK_LAST
- PORT_PHY_CFG_REQ_LPBK_LOCAL
- PORT_PHY_CFG_REQ_LPBK_NONE
- PORT_PHY_CFG_REQ_LPBK_REMOTE
- PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK
- PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT
- PORT_PHY_CFG_REQ_WIRESPEED_LAST
- PORT_PHY_CFG_REQ_WIRESPEED_OFF
- PORT_PHY_CFG_REQ_WIRESPEED_ON
- PORT_PHY_FORCE_LINK
- PORT_PHY_FORCE_MDI
- PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET
- PORT_PHY_ID_MASK
- PORT_PHY_INT
- PORT_PHY_INVALID
- PORT_PHY_ISOLATE
- PORT_PHY_LOOPBACK
- PORT_PHY_MODE_M
- PORT_PHY_PCS_LOOPBACK
- PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
- PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
- PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK
- PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT
- PORT_PHY_QCAPS_RESP_PORT_CNT_1
- PORT_PHY_QCAPS_RESP_PORT_CNT_2
- PORT_PHY_QCAPS_RESP_PORT_CNT_3
- PORT_PHY_QCAPS_RESP_PORT_CNT_4
- PORT_PHY_QCAPS_RESP_PORT_CNT_LAST
- PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN
- PORT_PHY_QCAPS_RESP_RSVD2_MASK
- PORT_PHY_QCAPS_RESP_RSVD2_SFT
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB
- PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB
- PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK
- PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT
- PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK
- PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT
- PORT_PHY_QCAPS_RESP_VALID_MASK
- PORT_PHY_QCAPS_RESP_VALID_SFT
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3
- PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB
- PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB
- PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
- PORT_PHY_QCFG_RESP_AUTO_MODE_LAST
- PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
- PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
- PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
- PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
- PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE
- PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX
- PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX
- PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
- PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF
- PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST
- PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
- PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
- PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST
- PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE
- PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED
- PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI
- PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK
- PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
- PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB
- PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST
- PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX
- PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX
- PORT_PHY_QCFG_RESP_LINK_LAST
- PORT_PHY_QCFG_RESP_LINK_LINK
- PORT_PHY_QCFG_RESP_LINK_NO_LINK
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB
- PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB
- PORT_PHY_QCFG_RESP_LINK_SIGNAL
- PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
- PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
- PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
- PORT_PHY_QCFG_RESP_LINK_SPEED_LAST
- PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
- PORT_PHY_QCFG_RESP_LPBK_LAST
- PORT_PHY_QCFG_RESP_LPBK_LOCAL
- PORT_PHY_QCFG_RESP_LPBK_NONE
- PORT_PHY_QCFG_RESP_LPBK_REMOTE
- PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC
- PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE
- PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST
- PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP
- PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN
- PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX
- PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST
- PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE
- PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
- PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED
- PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN
- PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG
- PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT
- PORT_PHY_QCFG_RESP_PARALLEL_DETECT
- PORT_PHY_QCFG_RESP_PAUSE_RX
- PORT_PHY_QCFG_RESP_PAUSE_TX
- PORT_PHY_QCFG_RESP_PHY_ADDR_MASK
- PORT_PHY_QCFG_RESP_PHY_ADDR_SFT
- PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4
- PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10
- PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX
- PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX
- PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET
- PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4
- PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L
- PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N
- PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S
- PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR
- PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE
- PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4
- PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASET
- PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE
- PORT_PHY_QCFG_RESP_PHY_TYPE_LAST
- PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY
- PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
- PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
- PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK
- PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT
- PORT_PHY_QCFG_RESP_WIRESPEED_LAST
- PORT_PHY_QCFG_RESP_WIRESPEED_OFF
- PORT_PHY_QCFG_RESP_WIRESPEED_ON
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT
- PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN
- PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST
- PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL
- PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL
- PORT_PHY_REMOTE_LOOPBACK
- PORT_PHY_RESET
- PORT_PHY_SOFT_RESET
- PORT_PHY_STAT_MASTER
- PORT_PHY_STAT_MDI
- PORT_PHY_UNKNOWN
- PORT_PIC32
- PORT_PICR
- PORT_PIN
- PORT_PIN_DIRECTIONS
- PORT_PIN_MASK
- PORT_PIN_POLARITIES
- PORT_PIPE_SELECT_SHIFT
- PORT_PJCR
- PORT_PJDR
- PORT_PKCR
- PORT_PKDR
- PORT_PLC
- PORT_PLCR
- PORT_PLDR
- PORT_PLL_10BIT_CLK_ENABLE
- PORT_PLL_DCO_AMP
- PORT_PLL_DCO_AMP_DEFAULT
- PORT_PLL_DCO_AMP_MASK
- PORT_PLL_DCO_AMP_OVR_EN_H
- PORT_PLL_ENABLE
- PORT_PLL_GAIN_CTL
- PORT_PLL_GAIN_CTL_MASK
- PORT_PLL_INT_COEFF
- PORT_PLL_INT_COEFF_MASK
- PORT_PLL_LOCK
- PORT_PLL_LOCK_THRESHOLD_MASK
- PORT_PLL_LOCK_THRESHOLD_SHIFT
- PORT_PLL_M2_FRAC_ENABLE
- PORT_PLL_M2_FRAC_MASK
- PORT_PLL_M2_MASK
- PORT_PLL_N
- PORT_PLL_N_MASK
- PORT_PLL_N_SHIFT
- PORT_PLL_P1
- PORT_PLL_P1_MASK
- PORT_PLL_P1_SHIFT
- PORT_PLL_P2
- PORT_PLL_P2_MASK
- PORT_PLL_P2_SHIFT
- PORT_PLL_POWER_ENABLE
- PORT_PLL_POWER_STATE
- PORT_PLL_PROP_COEFF_MASK
- PORT_PLL_RECALIBRATE
- PORT_PLL_REF_SEL
- PORT_PLL_TARGET_CNT_MASK
- PORT_PLS_MASK
- PORT_PMAC_ZILOG
- PORT_PMA_ATTR
- PORT_PMA_ATTR_EXT
- PORT_PMCR
- PORT_PMDR
- PORT_PMP
- PORT_PMP_QACTIVE
- PORT_PMP_SIZE
- PORT_PMP_STATUS
- PORT_PNCR
- PORT_PNDR
- PORT_PNX8XXX
- PORT_POWER
- PORT_POWER_DOWN
- PORT_POWER_SAVING
- PORT_POWER_SAVING_DISABLE
- PORT_PPCR
- PORT_PPDR
- PORT_PQCR
- PORT_PQDR
- PORT_PRCR
- PORT_PRDR
- PORT_PRD_ADDR
- PORT_PRD_CTL
- PORT_PRD_XFERLEN
- PORT_PRI
- PORT_PRIORITY_RATE
- PORT_PRIORITY_RATE_SHIFT
- PORT_PRIO_QUEUE_ENABLE
- PORT_PROFILE_MAX
- PORT_PROFILE_RESPONSE_BADSTATE
- PORT_PROFILE_RESPONSE_ERROR
- PORT_PROFILE_RESPONSE_INPROGRESS
- PORT_PROFILE_RESPONSE_INSUFFICIENT_RESOURCES
- PORT_PROFILE_RESPONSE_INVALID
- PORT_PROFILE_RESPONSE_SUCCESS
- PORT_PRS_RESULT_WORDS_NUM
- PORT_PSCR
- PORT_PSDR
- PORT_PSD_DIAG
- PORT_PSEL0
- PORT_PSEL1
- PORT_PSEL2
- PORT_PSEL3
- PORT_PSEL4
- PORT_PSELA
- PORT_PSELB
- PORT_PSELC
- PORT_PSELD
- PORT_PSELE
- PORT_PTCR
- PORT_PTDR
- PORT_PTP_INT
- PORT_PTS_MSK
- PORT_PTS_PTW
- PORT_PTS_SERIAL
- PORT_PTS_ULPI
- PORT_PTS_UTMI
- PORT_PUCR
- PORT_PUDR
- PORT_PVCR
- PORT_PVDR
- PORT_PWCR
- PORT_PWDR
- PORT_PXA
- PORT_PXCR
- PORT_PYCR
- PORT_PYDR
- PORT_PZCR
- PORT_QE
- PORT_QM_BURST_SIZE_S
- PORT_QM_DROP_PRIO_M
- PORT_QM_HI_WATER_MARK_S
- PORT_QM_LO_WATER_MARK_S
- PORT_QM_MIN_RESV_SPACE_M
- PORT_QM_QUEUE_INDEX_S
- PORT_QM_TX_CNT_AVAIL_S
- PORT_QM_TX_CNT_CALCULATED_S
- PORT_QM_TX_CNT_M
- PORT_QM_TX_CNT_USED_S
- PORT_QM_WATER_MARK_M
- PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED
- PORT_QUARK_X1000
- PORT_QUEUE_SPLIT_1
- PORT_QUEUE_SPLIT_2
- PORT_QUEUE_SPLIT_4
- PORT_QUEUE_SPLIT_ENABLE
- PORT_QUEUE_SPLIT_H
- PORT_QUEUE_SPLIT_L
- PORT_RATE_LIMIT_M
- PORT_RATE_PACKET_BASED
- PORT_RATE_PACKET_BASED_S
- PORT_RC
- PORT_RDA
- PORT_RECOVERY_TIMEOUT
- PORT_REG
- PORT_REGS_SIZE
- PORT_REG_CLK_SPEED_25_MHZ
- PORT_REMOTE_1000BT
- PORT_REMOTE_1000BT_FD
- PORT_REMOTE_100BTX
- PORT_REMOTE_100BTX_FD
- PORT_REMOTE_10BT
- PORT_REMOTE_10BT_FD
- PORT_REMOTE_ACKNOWLEDGE
- PORT_REMOTE_ASYM_PAUSE
- PORT_REMOTE_FAULT
- PORT_REMOTE_FAULT_DISABLE
- PORT_REMOTE_IDLE_CNT_M
- PORT_REMOTE_LOOPBACK
- PORT_REMOTE_NEXT_PAGE
- PORT_REMOTE_REMOTE_FAULT
- PORT_REMOTE_RX_OK
- PORT_REMOTE_SYM_PAUSE
- PORT_REMOVE_TAG
- PORT_REPORT
- PORT_REQUEST_ASSOCIATE
- PORT_REQUEST_DISASSOCIATE
- PORT_REQUEST_PREASSOCIATE
- PORT_REQUEST_PREASSOCIATE_RR
- PORT_RESET
- PORT_RESET_HW_MSEC
- PORT_RESET_MSEC
- PORT_RESET_SUCCESS
- PORT_RESET_TMO
- PORT_RESET_TRIES
- PORT_RESOURCE_DESC_TYPE_V1
- PORT_RESUME
- PORT_RES_EN
- PORT_RETRY_TIME
- PORT_REVERSED_POLARITY
- PORT_RGMII_ID_EG_ENABLE
- PORT_RGMII_ID_IG_ENABLE
- PORT_RGMII_ID_IN_ENABLE
- PORT_RGMII_ID_OUT_ENABLE
- PORT_RGMII_SEL
- PORT_RGMII_SEL_S1
- PORT_RM9000
- PORT_RMII_CLK_SEL
- PORT_RMII_SEL
- PORT_RMII_SEL_S1
- PORT_RP2
- PORT_RPQ_CNT
- PORT_RPQ_FIFO
- PORT_RSA
- PORT_RSA_MAX
- PORT_RT2880
- PORT_RWC_BITS
- PORT_RWE
- PORT_RX_CNTR
- PORT_RX_ENABLE
- PORT_RX_FLOW_CTRL
- PORT_RX_LANES
- PORT_S
- PORT_S3C2400
- PORT_S3C2410
- PORT_S3C2412
- PORT_S3C2440
- PORT_S3C6400
- PORT_SA1100
- PORT_SACTIVE
- PORT_SATA
- PORT_SB1250_DUART
- PORT_SC16IS7XX
- PORT_SC26XX
- PORT_SCI
- PORT_SCIF
- PORT_SCIFA
- PORT_SCIFB
- PORT_SCONTROL
- PORT_SCR
- PORT_SCR_ACT
- PORT_SCR_CTL
- PORT_SCR_ERR
- PORT_SCR_NTF
- PORT_SCR_STAT
- PORT_SCTL_IPM
- PORT_SCTL_SPD_GEN1
- PORT_SCTL_SPD_GEN2
- PORT_SCTL_SPD_GEN3
- PORT_SDBV
- PORT_SDMA_CONFIG_DEFAULT_VALUE
- PORT_SE0_STATUS
- PORT_SELFTEST
- PORT_SELF_VF
- PORT_SEL_PORT_4E_EN
- PORT_SERIAL_CONTROL
- PORT_SERIAL_CONTROL1
- PORT_SERROR
- PORT_SET_AID
- PORT_SET_BCN_CTRL
- PORT_SET_BSSID
- PORT_SET_MAC_ADDR
- PORT_SET_NET_TYPE
- PORT_SGMII_ADDR_M
- PORT_SGMII_AUTO_INCR
- PORT_SGMII_DATA_M
- PORT_SGMII_DEVICE_ID_M
- PORT_SGMII_DEVICE_ID_S
- PORT_SGMII_INT
- PORT_SGMII_SEL
- PORT_SHIFT
- PORT_SIFIVE_V0
- PORT_SIG
- PORT_SIGNAL_DETECT
- PORT_SIZE
- PORT_SIZE_MASK
- PORT_SLOT_STAT
- PORT_SPDIF
- PORT_SPD_CAP
- PORT_SPD_CAP_SHIFT
- PORT_SPEC_TAG
- PORT_SPEED_10
- PORT_SPEED_100
- PORT_SPEED_1000
- PORT_SPEED_1000MBIT
- PORT_SPEED_100MBIT
- PORT_SPEED_10GB
- PORT_SPEED_16GB
- PORT_SPEED_1GB
- PORT_SPEED_2GB
- PORT_SPEED_32GB
- PORT_SPEED_4GB
- PORT_SPEED_64GB
- PORT_SPEED_8GB
- PORT_SPEED_AUTO
- PORT_SPEED_MASK
- PORT_SPEED_UNKNOWN
- PORT_SPRD
- PORT_SRC_ADDR_FILTER
- PORT_SRP_ENABLE
- PORT_SSP_INIT_MASK
- PORT_SSP_TRGT_MASK
- PORT_SSTATUS
- PORT_SSTS
- PORT_STAG
- PORT_STARTECH
- PORT_START_CABLE_DIAG
- PORT_STAT
- PORT_STATE
- PORT_STATES
- PORT_STATE_OFFSET
- PORT_STATE_PHY8_CONN_RATE_MSK
- PORT_STATE_PHY8_CONN_RATE_OFF
- PORT_STATE_PHY8_PORT_NUM_MSK
- PORT_STATE_PHY8_PORT_NUM_OFF
- PORT_STATUS
- PORT_STATUS_64
- PORT_STATUS_AC0
- PORT_STATUS_AC1
- PORT_STATUS_AE0
- PORT_STATUS_AE1
- PORT_STATUS_DL
- PORT_STATUS_DUPLEX
- PORT_STATUS_F0_ENABLED
- PORT_STATUS_F1_ENABLED
- PORT_STATUS_F2_ENABLED
- PORT_STATUS_F3_ENABLED
- PORT_STATUS_FC
- PORT_STATUS_FULL_DUPLEX
- PORT_STATUS_IC
- PORT_STATUS_LINK
- PORT_STATUS_LINK_GOOD
- PORT_STATUS_MRC
- PORT_STATUS_MY_PAUSE
- PORT_STATUS_NL
- PORT_STATUS_PAUSE_EN
- PORT_STATUS_PHYMODE
- PORT_STATUS_PORTMODE
- PORT_STATUS_RESOLVED
- PORT_STATUS_REV_ID_1
- PORT_STATUS_REV_ID_2
- PORT_STATUS_REV_ID_3
- PORT_STATUS_REV_ID_MASK
- PORT_STATUS_SM0
- PORT_STATUS_SM1
- PORT_STATUS_SPEED
- PORT_STATUS_SPEED_100MBIT
- PORT_STATUS_UP0
- PORT_STATUS_UP1
- PORT_STATUS_X
- PORT_STAT_FULL_DUPLEX
- PORT_STAT_LINK_GOOD
- PORT_STAT_MASTER
- PORT_STAT_SPEED_1000MBIT
- PORT_STAT_SPEED_100MBIT
- PORT_STAT_SPEED_10MBIT
- PORT_STEERING
- PORT_STE_TYPE
- PORT_STM32
- PORT_STRIDE
- PORT_STS_AP1_EVT
- PORT_STS_AP2_EVT
- PORT_STS_PWR_STATE
- PORT_STS_PWR_STATE_AP1
- PORT_STS_PWR_STATE_AP2
- PORT_STS_PWR_STATE_AP6
- PORT_STS_PWR_STATE_NORM
- PORT_SUNHV
- PORT_SUNIX
- PORT_SUNSAB
- PORT_SUNZILOG
- PORT_SUSPEND
- PORT_SWITCH_ID
- PORT_SWITCH_ID_6060
- PORT_SWITCH_ID_6060_MASK
- PORT_SWITCH_ID_6060_R1
- PORT_SWITCH_ID_6060_R2
- PORT_SYNC_MODE_ENABLE
- PORT_SYNC_MODE_MASTER_SELECT
- PORT_SYNC_MODE_MASTER_SELECT_MASK
- PORT_SYNC_MODE_MASTER_SELECT_SHIFT
- PORT_TABLE_AUTO_LANE_SHEDDING_ENABLED
- PORT_TABLE_CABLE_REACH_CLASS
- PORT_TABLE_EXTERNAL_LOOPBACK_ALLOWED
- PORT_TABLE_LINK_SPEED_SUPPORTED
- PORT_TABLE_LINK_WIDTH_SUPPORTED
- PORT_TABLE_LOCAL_ATTEN_12G
- PORT_TABLE_LOCAL_ATTEN_25G
- PORT_TABLE_LOCAL_MAX_TIMEOUT
- PORT_TABLE_MAX
- PORT_TABLE_MTU_CAP
- PORT_TABLE_PORT_TYPE
- PORT_TABLE_REMOTE_ATTEN_12G
- PORT_TABLE_REMOTE_ATTEN_25G
- PORT_TABLE_RESERVED
- PORT_TABLE_RX_PRESET_IDX
- PORT_TABLE_TX_LANE_ENABLE_MASK
- PORT_TABLE_TX_PRESET_IDX_ACTIVE_EQ
- PORT_TABLE_TX_PRESET_IDX_ACTIVE_NO_EQ
- PORT_TABLE_VL_CAP
- PORT_TAIL_TAG_ENABLE
- PORT_TC1
- PORT_TC2
- PORT_TC3
- PORT_TC4
- PORT_TC5
- PORT_TC6
- PORT_TC_MAP_M
- PORT_TC_MAP_S
- PORT_TC_NONE
- PORT_TDM
- PORT_TEGRA
- PORT_TEGRA_TCU
- PORT_TEST
- PORT_TEST_FORCE
- PORT_TEST_MODE_SHIFT
- PORT_TEST_PKT
- PORT_TFDATA
- PORT_TF_ALT_STAT
- PORT_TF_COMMAND
- PORT_TF_DATA
- PORT_TF_DEVICE
- PORT_TF_FEATURE
- PORT_TF_LBAH
- PORT_TF_LBAL
- PORT_TF_LBAM
- PORT_TF_NSECT
- PORT_TGT_MASK
- PORT_TGT_PORT
- PORT_TILEGX
- PORT_TIMBUART
- PORT_TP
- PORT_TRANS
- PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME
- PORT_TS_QUERY_REQ_FLAGS_PATH
- PORT_TS_QUERY_REQ_FLAGS_PATH_LAST
- PORT_TS_QUERY_REQ_FLAGS_PATH_RX
- PORT_TS_QUERY_REQ_FLAGS_PATH_TX
- PORT_TV_FLAGS
- PORT_TV_FLAGS_MASK
- PORT_TXX9
- PORT_TX_CNTR
- PORT_TX_DFLEXDPCSSS
- PORT_TX_DFLEXDPMLE1
- PORT_TX_DFLEXDPPMS
- PORT_TX_DFLEXDPSP
- PORT_TX_DISABLE
- PORT_TX_ENABLE
- PORT_TX_FLOW_CTRL
- PORT_TX_LANES
- PORT_TYPE
- PORT_TYPE_10G
- PORT_TYPE_1G
- PORT_TYPE_CDP
- PORT_TYPE_CONV
- PORT_TYPE_DCP
- PORT_TYPE_DISCONNECTED
- PORT_TYPE_EVE
- PORT_TYPE_FIXED
- PORT_TYPE_I2S
- PORT_TYPE_MASK
- PORT_TYPE_MAX
- PORT_TYPE_NON_STANDARD
- PORT_TYPE_QSFP
- PORT_TYPE_SAS
- PORT_TYPE_SATA
- PORT_TYPE_SDP
- PORT_TYPE_SPDIF
- PORT_TYPE_UNKNOWN
- PORT_TYPE_VARIABLE
- PORT_U1_TIMEOUT
- PORT_U1_TIMEOUT_MASK
- PORT_U2_TIMEOUT
- PORT_U2_TIMEOUT_MASK
- PORT_U6_16550A
- PORT_UART00
- PORT_UARTLITE
- PORT_UCLKCR_W
- PORT_UNKNOWN
- PORT_USB11
- PORT_USER_PRIORITY_CEILING
- PORT_USER_PRIO_CEILING
- PORT_UTRCTL
- PORT_UUID_MAX
- PORT_V
- PORT_VALID
- PORT_VALID_SHIFT
- PORT_VDP_RESPONSE_INSUFFICIENT_RESOURCES
- PORT_VDP_RESPONSE_INVALID_FORMAT
- PORT_VDP_RESPONSE_OUT_OF_SYNC
- PORT_VDP_RESPONSE_SUCCESS
- PORT_VDP_RESPONSE_UNUSED_VTID
- PORT_VDP_RESPONSE_VTID_VERSION_VIOALTION
- PORT_VDP_RESPONSE_VTID_VIOLATION
- PORT_VLAN
- PORT_VLAN_CTRL_MASK
- PORT_VLAN_LOOKUP_VID_0
- PORT_VLAN_MAP
- PORT_VLAN_MAP_DBNUM_SHIFT
- PORT_VLAN_MAP_TABLE_MASK
- PORT_VLAN_MEMBERSHIP
- PORT_VLAN_PRIO_ENABLE
- PORT_VR41XX_DSIU
- PORT_VR41XX_SIU
- PORT_VSR_ADDR
- PORT_VSR_DATA
- PORT_VT8500
- PORT_WAKE_BITS
- PORT_WKCONN_E
- PORT_WKDISC_E
- PORT_WKOC_E
- PORT_WR
- PORT_WRC
- PORT_XR17D15X
- PORT_XR17V35X
- PORT_XSCALE
- PORT_XUARTPS
- PORT_XUSB
- PORT_ZS
- PORTnCR_PULMD_DOWN
- PORTnCR_PULMD_MASK
- PORTnCR_PULMD_OFF
- PORTnCR_PULMD_UP
- POR_EN
- POR_RESET_N
- POR_RETRY_COUNT
- POR_RST_COMPLETE_TIME
- POS
- POS1064
- POS1064_XCOLKEYH
- POS1064_XCOLKEYL
- POS1064_XCOLKEYMASKH
- POS1064_XCOLKEYMASKL
- POS1064_XCRCBITSEL
- POS1064_XCURADDH
- POS1064_XCURADDL
- POS1064_XCURCOL0BLUE
- POS1064_XCURCOL0GREEN
- POS1064_XCURCOL0RED
- POS1064_XCURCOL1BLUE
- POS1064_XCURCOL1GREEN
- POS1064_XCURCOL1RED
- POS1064_XCURCOL2BLUE
- POS1064_XCURCOL2GREEN
- POS1064_XCURCOL2RED
- POS1064_XCURCTRL
- POS1064_XGENCTRL
- POS1064_XGENIOCTRL
- POS1064_XGENIODATA
- POS1064_XMISCCTRL
- POS1064_XMULCTRL
- POS1064_XOUTPUTCONN
- POS1064_XPANMODE
- POS1064_XPIXCLKCTRL
- POS1064_XPWRCTRL
- POS1064_XSENSETEST
- POS1064_XVREFCTRL
- POS1064_XZOOMCTRL
- POS3026_XCLKCTRL
- POS3026_XCURCTRL
- POS3026_XGENCTRL
- POS3026_XLATCHCTRL
- POS3026_XMEMPLLCTRL
- POS3026_XMISCCTRL
- POS3026_XMUXCTRL
- POS3026_XTRUECOLORCTRL
- POSC
- POSCCLK
- POSDIFF
- POSDIV_SHIFT
- POSIFLEX_PP7000_PID
- POSIFLEX_VID
- POSITION_1_VECTOR
- POSITION_2_VECTORS_EDGE
- POSITION_2_VECTORS_EDGE_KILL
- POSITION_2_VECTORS_KILL
- POSITION_2_VECTORS_SPRITE
- POSITION_2_VECTORS_SPRITE_KILL
- POSITION_2_VECTORS_UNUSED
- POSITION_ADDR
- POSITION_BUFFER_SIZE
- POSITION_CENTROID
- POSITION_ENA
- POSITION_FOUND
- POSITION_NOT_FOUND
- POSITION_SAMPLE
- POSITION_TO_ELEMENT
- POSITIVE_GAIN_MASK
- POSITIVE_GAIN_MASK_SFT
- POSITIVE_GAIN_SFT
- POSIX_ACL_XATTR_VERSION
- POSIX_CTXT_DATA_LEN
- POSIX_FADV_DONTNEED
- POSIX_FADV_NOREUSE
- POSIX_FADV_NORMAL
- POSIX_FADV_RANDOM
- POSIX_FADV_SEQUENTIAL
- POSIX_FADV_WILLNEED
- POSIX_PROT
- POSNEG
- POSR
- POSR_FIFOE
- POSR_FSR
- POSR_OOK
- POST
- POSTAMBLE
- POSTDIV
- POSTDIV3
- POSTDIV_DIV_BY_1
- POSTDIV_DIV_BY_16
- POSTDIV_DIV_BY_2
- POSTDIV_DIV_BY_4
- POSTDIV_DIV_BY_8
- POSTDIV_MASK
- POSTED
- POSTED_INTR_DESC_ADDR
- POSTED_INTR_DESC_ADDR_HIGH
- POSTED_INTR_NESTED_VECTOR
- POSTED_INTR_NV
- POSTED_INTR_ON
- POSTED_INTR_SN
- POSTED_INTR_VECTOR
- POSTED_INTR_WAKEUP_VECTOR
- POSTED_WRITE_ENABLE
- POSTINDEXED
- POSTING_READ
- POSTPONE_WRITE
- POSTSTATUS
- POSTSUSPEND
- POSTWEN
- POST_ALL_UNDERRRUNS
- POST_BIOS_ROM
- POST_CHANGE
- POST_CLAMP_TF0
- POST_CLAMP_TF1
- POST_CMD_DELAY
- POST_CODE
- POST_COMMAND_DELAY
- POST_COMMIT
- POST_CONTENTS
- POST_CQE_DESC_COUNT
- POST_CSC_GAMMA_ENABLE
- POST_CURSOR2_DISABLED
- POST_CURSOR2_LEVEL1
- POST_CURSOR2_LEVEL2
- POST_CURSOR2_LEVEL3
- POST_CURSOR2_MAX_LEVEL
- POST_CURSOR_1
- POST_CURSOR_1_MASK
- POST_CURSOR_2
- POST_CURSOR_2_MASK
- POST_DELAY
- POST_DIV_1
- POST_DIV_16
- POST_DIV_2
- POST_DIV_32
- POST_DIV_4
- POST_DIV_8
- POST_DIV_SELECT
- POST_ERROR_BIT
- POST_ERR_MASK
- POST_ERR_RECOVERY_CODE_MASK
- POST_ERR_SHIFT
- POST_EX
- POST_LT_ADJ_REQ_LIMIT
- POST_LT_ADJ_REQ_TIMEOUT
- POST_MEM
- POST_RATE_CHANGE
- POST_RECV
- POST_SEND
- POST_SRQ_RECV
- POST_STAGE_ARMFW_RDY
- POST_STAGE_ARMFW_UE
- POST_STAGE_AWAITING_HOST_RDY
- POST_STAGE_BE_RESET
- POST_STAGE_FAT_LOG_START
- POST_STAGE_HOST_RDY
- POST_STAGE_MASK
- POST_STAGE_RECOVERABLE_ERR
- POST_TRIGGER_BITS
- POST_WARN_EVENT
- POST_WIN7_STORVSC_SENSE_BUFFER_SIZE
- POST_WRITE
- POST_WR_EN
- POS_FIX_AUTO
- POS_FIX_COMBO
- POS_FIX_FIFO
- POS_FIX_LPIB
- POS_FIX_POSBUF
- POS_FIX_SKL
- POS_FIX_VIACOMBO
- POS_L_MASK
- POS_MASK
- POS_POS
- POS_PRN
- POS_SHIFT
- POS_STATES_MAX
- POS_X1_H
- POS_X1_L
- POS_X2_H
- POS_X2_L
- POS_Y1_H
- POS_Y1_L
- POS_Y2_H
- POS_Y2_L
- POT_MAGIC1
- POT_MAGIC2
- POW
- POW10
- POW2
- POW2_BELOW32
- POW2_BELOW64
- POWDLY_1_1MS
- POWER
- POWER0_COM_DCLK
- POWER0_COM_DOUT
- POWER0_COM_OFF
- POWER0_COM_ON
- POWER0_DAC_OFF
- POWER0_DAC_ON
- POWER0_VCC5_OFF
- POWER0_VCC5_ON
- POWER1_GVSS_OFF
- POWER1_GVSS_ON
- POWER1_VDD_OFF
- POWER1_VDD_ON
- POWER1_VW_OFF
- POWER1_VW_ON
- POWER2
- POWER4
- POWER5
- POWER6
- POWER6_MMCRA_OTHER
- POWER6_MMCRA_SDSYNC
- POWER6_MMCRA_SIHV
- POWER6_MMCRA_SIPR
- POWER6_MMCRA_THRM
- POWER7
- POWER7P_MMCRA_SDAR_VALID
- POWER7P_MMCRA_SIAR_VALID
- POWER7_TLB_SETS
- POWER8
- POWER8_MMCRA_BHRB_MASK
- POWER8_MMCRA_IFM1
- POWER8_MMCRA_IFM2
- POWER8_MMCRA_IFM3
- POWER8_TLB_SETS
- POWER9
- POWER9_MMCRA_BHRB_MASK
- POWER9_MMCRA_IFM1
- POWER9_MMCRA_IFM2
- POWER9_MMCRA_IFM3
- POWER9_TLB_SETS_HASH
- POWER9_TLB_SETS_RADIX
- POWERCAP
- POWERCAP_CONSTRAINTS_ATTRS
- POWERCAP_CONSTRAINT_NAME_LEN
- POWERCAP_GET_DEV
- POWERCAP_ZONE_MAX_ATTRS
- POWERCFG
- POWERCFG_DISABLE
- POWERCFG_DMUTE
- POWERCFG_DSMUTE
- POWERCFG_ENABLE
- POWERCFG_GLOBAL_POWER_SAVINGS
- POWERCFG_LENOVO
- POWERCFG_LOCAL_POWER_SAVINGS
- POWERCFG_MAX_POWER_SAVINGS
- POWERCFG_MONO
- POWERCFG_RDSM
- POWERCFG_SEEK
- POWERCFG_SEEKUP
- POWERCFG_SKMODE
- POWERCONTAINMENT_FEATURE_BAPM
- POWERCONTAINMENT_FEATURE_DTE
- POWERCONTAINMENT_FEATURE_PkgPwrLimit
- POWERCONTAINMENT_FEATURE_TDCLimit
- POWERDOWN
- POWERDOWN_FREQ
- POWERDOWN_PLL
- POWERDOWN_TIMEOUT
- POWERI
- POWERMATE_PAYLOAD_SIZE_MAX
- POWERMATE_PAYLOAD_SIZE_MIN
- POWERMATE_PRODUCT_NEW
- POWERMATE_PRODUCT_OLD
- POWERMATE_VENDOR
- POWERMODE0
- POWERMODE0_MASK
- POWERMODE0_SHIFT
- POWERMODE1
- POWERMODE1_MASK
- POWERMODE1_SHIFT
- POWERMODE2
- POWERMODE2_MASK
- POWERMODE2_SHIFT
- POWERMODE3
- POWERMODE3_MASK
- POWERMODE3_SHIFT
- POWERNOW_IOPORT
- POWERNV_IOMMU_DEFAULT_LEVELS
- POWERNV_IOMMU_MAX_LEVELS
- POWERNV_MAX_PSTATES
- POWERNV_MAX_PSTATES_ORDER
- POWERNV_THRESHOLD_LATENCY_NS
- POWEROFF_CMD_PATH_LEN
- POWEROFF_STATE
- POWEROFF_THRESHOLD
- POWERON
- POWERON_CPU_0__POWERON_MASK
- POWERON_CPU_0__POWERON__SHIFT
- POWERON_CPU_1__POWERON_MASK
- POWERON_CPU_1__POWERON__SHIFT
- POWERON_STATE
- POWERPC_85XX_SMP_H_
- POWERPC_PERF_REQ_GEN_H_
- POWERQ
- POWERREADY_CPU_0__POWERREADY_MASK
- POWERREADY_CPU_0__POWERREADY__SHIFT
- POWERREADY_CPU_1__POWERREADY_MASK
- POWERREADY_CPU_1__POWERREADY__SHIFT
- POWERREG0_ADRS
- POWERREG1_ADRS
- POWERSAVE_BIAS_DEF
- POWERSAVE_BIAS_MAX
- POWERSAVE_CAM
- POWERSAVE_PSP
- POWERSAVE_PSPCAM
- POWERSOURCE_6PIN_CONNECTOR_ID1
- POWERSOURCE_6PIN_CONNECTOR_ID2
- POWERSOURCE_8PIN_CONNECTOR_ID1
- POWERSOURCE_8PIN_CONNECTOR_ID2
- POWERSOURCE_PCIE_ID1
- POWERSWITCH_DOWN_SEC
- POWERSWITCH_POLL_PER_SEC
- POWERTEC_FAS216_OFFSET
- POWERTEC_FAS216_SHIFT
- POWERTEC_INTR_BIT
- POWERTEC_INTR_CONTROL
- POWERTEC_INTR_DISABLE
- POWERTEC_INTR_ENABLE
- POWERTEC_INTR_STATUS
- POWERTEC_RESET_BIT
- POWERTEC_RESET_CONTROL
- POWERTEC_TERM_CONTROL
- POWERTEC_TERM_ENABLE
- POWERTUNE_DEFAULT_SET_MAX
- POWERUP
- POWER_100KOHM_TO_GND
- POWER_1KOHM_TO_GND
- POWER_ACTIVE
- POWER_ALARM_NAME
- POWER_ALL
- POWER_ATT_SET
- POWER_AUX
- POWER_AVERAGE_NAME
- POWER_AVG_INTERVAL_NAME
- POWER_BOUND
- POWER_BOUND_5G
- POWER_BUDGET
- POWER_BUDGET_3
- POWER_CAP
- POWER_CAP_MAX
- POWER_CAP_MAX_HOTPLUG
- POWER_CAP_MIN
- POWER_CAP_MIN_WARNING
- POWER_CAP_NAME
- POWER_CLASS_1_EN
- POWER_CLASS_2_EN
- POWER_CNTLMSAK
- POWER_CONNECTOR_DETECTION_PARAMETERS
- POWER_CONNECTOR_DETECTION_PS_ALLOCATION
- POWER_CONTROL
- POWER_CONTROL_INDEX
- POWER_CONTROL_LOW
- POWER_CORRECTION_FOR_THREE_CHAIN
- POWER_CORRECTION_FOR_TWO_CHAIN
- POWER_CTL
- POWER_CTL_VLD
- POWER_CTRL
- POWER_CTRL_1
- POWER_CTRL_2
- POWER_CTRL_3
- POWER_CTRL_4
- POWER_CTRL_7
- POWER_CTRL_AB
- POWER_CTRL_CD
- POWER_CTRL_EF
- POWER_CTRL_GH
- POWER_CTRL_OTG_ENAB
- POWER_CTRL_REG
- POWER_CUT
- POWER_CUT_EC_WRITE
- POWER_CUT_VID_WRITE
- POWER_CVT
- POWER_CYCLE_DELAY_MASK
- POWER_D1_SCLK_HILEN
- POWER_D1_SCLK_LOLEN
- POWER_DESC_MAX_ACTV_ICC_LVLS
- POWER_DESC_MAX_SIZE
- POWER_DETECTION_TH
- POWER_DOMAIN_ATTRIBUTES
- POWER_DOMAIN_AUDIO
- POWER_DOMAIN_AUX_A
- POWER_DOMAIN_AUX_B
- POWER_DOMAIN_AUX_C
- POWER_DOMAIN_AUX_D
- POWER_DOMAIN_AUX_E
- POWER_DOMAIN_AUX_F
- POWER_DOMAIN_AUX_IO_A
- POWER_DOMAIN_AUX_TBT1
- POWER_DOMAIN_AUX_TBT2
- POWER_DOMAIN_AUX_TBT3
- POWER_DOMAIN_AUX_TBT4
- POWER_DOMAIN_AUX_TBT5
- POWER_DOMAIN_AUX_TBT6
- POWER_DOMAIN_AUX_TC1
- POWER_DOMAIN_AUX_TC2
- POWER_DOMAIN_AUX_TC3
- POWER_DOMAIN_AUX_TC4
- POWER_DOMAIN_AUX_TC5
- POWER_DOMAIN_AUX_TC6
- POWER_DOMAIN_DISPLAY_CORE
- POWER_DOMAIN_DPLL_DC_OFF
- POWER_DOMAIN_GMBUS
- POWER_DOMAIN_GT_IRQ
- POWER_DOMAIN_INIT
- POWER_DOMAIN_MASK
- POWER_DOMAIN_MODESET
- POWER_DOMAIN_NUM
- POWER_DOMAIN_PIPE
- POWER_DOMAIN_PIPE_A
- POWER_DOMAIN_PIPE_A_PANEL_FITTER
- POWER_DOMAIN_PIPE_B
- POWER_DOMAIN_PIPE_B_PANEL_FITTER
- POWER_DOMAIN_PIPE_C
- POWER_DOMAIN_PIPE_C_PANEL_FITTER
- POWER_DOMAIN_PIPE_D
- POWER_DOMAIN_PIPE_D_PANEL_FITTER
- POWER_DOMAIN_PIPE_PANEL_FITTER
- POWER_DOMAIN_PORT_CRT
- POWER_DOMAIN_PORT_DDI_A_IO
- POWER_DOMAIN_PORT_DDI_A_LANES
- POWER_DOMAIN_PORT_DDI_B_IO
- POWER_DOMAIN_PORT_DDI_B_LANES
- POWER_DOMAIN_PORT_DDI_C_IO
- POWER_DOMAIN_PORT_DDI_C_LANES
- POWER_DOMAIN_PORT_DDI_D_IO
- POWER_DOMAIN_PORT_DDI_D_LANES
- POWER_DOMAIN_PORT_DDI_E_IO
- POWER_DOMAIN_PORT_DDI_E_LANES
- POWER_DOMAIN_PORT_DDI_F_IO
- POWER_DOMAIN_PORT_DDI_F_LANES
- POWER_DOMAIN_PORT_DDI_G_IO
- POWER_DOMAIN_PORT_DDI_H_IO
- POWER_DOMAIN_PORT_DDI_I_IO
- POWER_DOMAIN_PORT_DDI_TC1_IO
- POWER_DOMAIN_PORT_DDI_TC1_LANES
- POWER_DOMAIN_PORT_DDI_TC2_IO
- POWER_DOMAIN_PORT_DDI_TC2_LANES
- POWER_DOMAIN_PORT_DDI_TC3_IO
- POWER_DOMAIN_PORT_DDI_TC3_LANES
- POWER_DOMAIN_PORT_DDI_TC4_IO
- POWER_DOMAIN_PORT_DDI_TC4_LANES
- POWER_DOMAIN_PORT_DDI_TC5_IO
- POWER_DOMAIN_PORT_DDI_TC5_LANES
- POWER_DOMAIN_PORT_DDI_TC6_IO
- POWER_DOMAIN_PORT_DDI_TC6_LANES
- POWER_DOMAIN_PORT_DSI
- POWER_DOMAIN_PORT_OTHER
- POWER_DOMAIN_TRANSCODER
- POWER_DOMAIN_TRANSCODER_A
- POWER_DOMAIN_TRANSCODER_B
- POWER_DOMAIN_TRANSCODER_C
- POWER_DOMAIN_TRANSCODER_D
- POWER_DOMAIN_TRANSCODER_DSI_A
- POWER_DOMAIN_TRANSCODER_DSI_C
- POWER_DOMAIN_TRANSCODER_EDP
- POWER_DOMAIN_TRANSCODER_VDSC_PW2
- POWER_DOMAIN_VGA
- POWER_DOWN
- POWER_DOWN_ADC
- POWER_DOWN_ALL
- POWER_DOWN_DELAY_US_MAX
- POWER_DOWN_DELAY_US_MIN
- POWER_DOWN_DISABLE
- POWER_DOWN_ENABLE
- POWER_DOWN_ON_RESET
- POWER_DOWN_OUTPUT
- POWER_DOWN_PHY0
- POWER_DOWN_PHY1
- POWER_EN
- POWER_ENABLE
- POWER_ENB_SET
- POWER_EVENT_ATTR
- POWER_EVENT_PTR
- POWER_FAILURE
- POWER_FAULT
- POWER_FLAGS_ADVANCE_PM_ENA_MSK
- POWER_FLAGS_BT_SCO_ENA
- POWER_FLAGS_LPRX_ENA_MSK
- POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK
- POWER_FLAGS_POWER_SAVE_ENA_MSK
- POWER_FLAGS_SKIP_OVER_DTIM_MSK
- POWER_FLAGS_SNOOZE_ENA_MSK
- POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK
- POWER_FROM_ADCRSSI_READBACK
- POWER_HIGH_LOCK
- POWER_I
- POWER_INFO_MAX_MASK
- POWER_INFO_MAX_TIME_WIN_MASK
- POWER_INFO_MIN_MASK
- POWER_INFO_THERMAL_SPEC_MASK
- POWER_INPUT
- POWER_IRQ
- POWER_IS_ON
- POWER_KEEP_ALIVE_PERIOD_SEC
- POWER_KEYS
- POWER_LEV_SET
- POWER_LIMIT1
- POWER_LIMIT1_CLAMP
- POWER_LIMIT1_ENABLE
- POWER_LIMIT1_MASK
- POWER_LIMIT2
- POWER_LIMIT2_CLAMP
- POWER_LIMIT2_ENABLE
- POWER_LIMIT2_MASK
- POWER_LIMIT_EVENT
- POWER_LIMIT_SHOW
- POWER_LOW
- POWER_LOW_LOCK
- POWER_LPRX_RSSI_THRESHOLD
- POWER_LPRX_RSSI_THRESHOLD_MAX
- POWER_LPRX_RSSI_THRESHOLD_MIN
- POWER_MANAGE
- POWER_MANAGEMENT
- POWER_MANAGEMENT_2
- POWER_MANAGEMENT_LG
- POWER_MANAGEMENT_MASK
- POWER_MANAGEMENT_SHIFT
- POWER_MANAGER_CONTROLLER_BIT
- POWER_MANAGER_CONTROLLER_MASK
- POWER_MANAGER_CONTROLLER_NOT_RUNNING
- POWER_MANAGER_CONTROLLER_RUNNING
- POWER_MASK
- POWER_METER_CAN_CAP
- POWER_METER_CAN_MEASURE
- POWER_METER_CAN_NOTIFY
- POWER_METER_CAN_TRIP
- POWER_METER_IS_BATTERY
- POWER_MGMT
- POWER_MGMT_ACTIVE
- POWER_MGMT_SAVE1
- POWER_MGMT_SAVE2
- POWER_MNG_CTRL_REG
- POWER_MODE
- POWER_MODES
- POWER_MODE_ACTIVE
- POWER_MODE_APPS_IDLE
- POWER_MODE_APPS_SLEEP
- POWER_MODE_CHIP_SLEEP
- POWER_MODE_CORE_EXTIDLE
- POWER_MODE_CORE_INTIDLE
- POWER_MODE_CTRL
- POWER_MODE_CTRL_336CLK
- POWER_MODE_CTRL_ACPI
- POWER_MODE_CTRL_MODE_MASK
- POWER_MODE_CTRL_MODE_MODE0
- POWER_MODE_CTRL_MODE_MODE1
- POWER_MODE_CTRL_MODE_SLEEP
- POWER_MODE_CTRL_OSC_INPUT
- POWER_MODE_HIBERNATE
- POWER_MODE_SYS_SLEEP
- POWER_MODE_UDR
- POWER_NORMAL
- POWER_OFF
- POWER_OF_2
- POWER_ON
- POWER_ON_DOWN
- POWER_ON_REBOOT
- POWER_ON_RESET
- POWER_ON_RESET_ASCQ
- POWER_OR_RESET
- POWER_PACKET
- POWER_POLL_DELAY
- POWER_Q
- POWER_RESTART
- POWER_SAVE
- POWER_SAVE_HIGH
- POWER_SAVE_LOW
- POWER_SAVE_MEDIUM
- POWER_SAVE_MODE_ACTIVE
- POWER_SAVE_MODE_SAVE
- POWER_SAVE_OFF
- POWER_SAVE_OUTDOOR_MODE
- POWER_SAVING_CTRL_WK_CID
- POWER_SCALE
- POWER_SCALE_IN_MILLIWATT
- POWER_SENSE_LOW
- POWER_SENSOR
- POWER_SENSOR_ALWAYS
- POWER_SENSOR_GPIO
- POWER_SENSOR_I2C
- POWER_SET
- POWER_SOURCE
- POWER_SOURCE_AC
- POWER_SOURCE_COUNT
- POWER_SOURCE_DC
- POWER_SOURCE_LIMITED_POWER
- POWER_SOURCE_LIMITED_POWER_2
- POWER_SOURCE_MAX
- POWER_SOURCE_e
- POWER_STATE
- POWER_STATE_CHANGE_INTERRUPT
- POWER_STATE_CHANGE_INTERRUPT_ENABLE
- POWER_STATE_ENUM
- POWER_STATE_ENUM_DS
- POWER_STATE_ENUM_LS
- POWER_STATE_ENUM_ON
- POWER_STATE_ENUM_SD
- POWER_STATE_GET
- POWER_STATE_NOTIFY
- POWER_STATE_SET
- POWER_STATE_TYPE_BALANCED
- POWER_STATE_TYPE_BATTERY
- POWER_STATE_TYPE_DEFAULT
- POWER_STATE_TYPE_INTERNAL_3DPERF
- POWER_STATE_TYPE_INTERNAL_ACPI
- POWER_STATE_TYPE_INTERNAL_BOOT
- POWER_STATE_TYPE_INTERNAL_THERMAL
- POWER_STATE_TYPE_INTERNAL_ULV
- POWER_STATE_TYPE_INTERNAL_UVD
- POWER_STATE_TYPE_INTERNAL_UVD_HD
- POWER_STATE_TYPE_INTERNAL_UVD_HD2
- POWER_STATE_TYPE_INTERNAL_UVD_MVC
- POWER_STATE_TYPE_INTERNAL_UVD_SD
- POWER_STATE_TYPE_PERFORMANCE
- POWER_STATE_TYPE_POWERSAVE
- POWER_STA_DISABLE
- POWER_STA_ENABLE
- POWER_STDBY
- POWER_SUPPLY
- POWER_SUPPLY_ATTR
- POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL
- POWER_SUPPLY_CAPACITY_LEVEL_FULL
- POWER_SUPPLY_CAPACITY_LEVEL_HIGH
- POWER_SUPPLY_CAPACITY_LEVEL_LOW
- POWER_SUPPLY_CAPACITY_LEVEL_NORMAL
- POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN
- POWER_SUPPLY_CHARGE_TYPE_ADAPTIVE
- POWER_SUPPLY_CHARGE_TYPE_CUSTOM
- POWER_SUPPLY_CHARGE_TYPE_FAST
- POWER_SUPPLY_CHARGE_TYPE_NONE
- POWER_SUPPLY_CHARGE_TYPE_STANDARD
- POWER_SUPPLY_CHARGE_TYPE_TRICKLE
- POWER_SUPPLY_CHARGE_TYPE_UNKNOWN
- POWER_SUPPLY_DEFERRED_REGISTER_TIME
- POWER_SUPPLY_FAILURE
- POWER_SUPPLY_HEALTH_COLD
- POWER_SUPPLY_HEALTH_DEAD
- POWER_SUPPLY_HEALTH_GOOD
- POWER_SUPPLY_HEALTH_OVERCURRENT
- POWER_SUPPLY_HEALTH_OVERHEAT
- POWER_SUPPLY_HEALTH_OVERVOLTAGE
- POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE
- POWER_SUPPLY_HEALTH_UNKNOWN
- POWER_SUPPLY_HEALTH_UNSPEC_FAILURE
- POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE
- POWER_SUPPLY_OCV_TEMP_MAX
- POWER_SUPPLY_PROP_AUTHENTIC
- POWER_SUPPLY_PROP_CALIBRATE
- POWER_SUPPLY_PROP_CAPACITY
- POWER_SUPPLY_PROP_CAPACITY_ALERT_MAX
- POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN
- POWER_SUPPLY_PROP_CAPACITY_LEVEL
- POWER_SUPPLY_PROP_CHARGE_AVG
- POWER_SUPPLY_PROP_CHARGE_CONTROL_END_THRESHOLD
- POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT
- POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX
- POWER_SUPPLY_PROP_CHARGE_CONTROL_START_THRESHOLD
- POWER_SUPPLY_PROP_CHARGE_COUNTER
- POWER_SUPPLY_PROP_CHARGE_EMPTY
- POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN
- POWER_SUPPLY_PROP_CHARGE_FULL
- POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN
- POWER_SUPPLY_PROP_CHARGE_NOW
- POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT
- POWER_SUPPLY_PROP_CHARGE_TYPE
- POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT
- POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX
- POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE
- POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX
- POWER_SUPPLY_PROP_CURRENT_AVG
- POWER_SUPPLY_PROP_CURRENT_BOOT
- POWER_SUPPLY_PROP_CURRENT_MAX
- POWER_SUPPLY_PROP_CURRENT_NOW
- POWER_SUPPLY_PROP_CYCLE_COUNT
- POWER_SUPPLY_PROP_ENERGY_AVG
- POWER_SUPPLY_PROP_ENERGY_EMPTY
- POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN
- POWER_SUPPLY_PROP_ENERGY_FULL
- POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN
- POWER_SUPPLY_PROP_ENERGY_NOW
- POWER_SUPPLY_PROP_HEALTH
- POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT
- POWER_SUPPLY_PROP_INPUT_POWER_LIMIT
- POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT
- POWER_SUPPLY_PROP_MANUFACTURER
- POWER_SUPPLY_PROP_MODEL_NAME
- POWER_SUPPLY_PROP_ONLINE
- POWER_SUPPLY_PROP_POWER_AVG
- POWER_SUPPLY_PROP_POWER_NOW
- POWER_SUPPLY_PROP_PRECHARGE_CURRENT
- POWER_SUPPLY_PROP_PRESENT
- POWER_SUPPLY_PROP_SCOPE
- POWER_SUPPLY_PROP_SERIAL_NUMBER
- POWER_SUPPLY_PROP_STATUS
- POWER_SUPPLY_PROP_TECHNOLOGY
- POWER_SUPPLY_PROP_TEMP
- POWER_SUPPLY_PROP_TEMP_ALERT_MAX
- POWER_SUPPLY_PROP_TEMP_ALERT_MIN
- POWER_SUPPLY_PROP_TEMP_AMBIENT
- POWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX
- POWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN
- POWER_SUPPLY_PROP_TEMP_MAX
- POWER_SUPPLY_PROP_TEMP_MIN
- POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG
- POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW
- POWER_SUPPLY_PROP_TIME_TO_FULL_AVG
- POWER_SUPPLY_PROP_TIME_TO_FULL_NOW
- POWER_SUPPLY_PROP_TYPE
- POWER_SUPPLY_PROP_USB_TYPE
- POWER_SUPPLY_PROP_VOLTAGE_AVG
- POWER_SUPPLY_PROP_VOLTAGE_BOOT
- POWER_SUPPLY_PROP_VOLTAGE_MAX
- POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN
- POWER_SUPPLY_PROP_VOLTAGE_MIN
- POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN
- POWER_SUPPLY_PROP_VOLTAGE_NOW
- POWER_SUPPLY_PROP_VOLTAGE_OCV
- POWER_SUPPLY_SCOPE_DEVICE
- POWER_SUPPLY_SCOPE_SYSTEM
- POWER_SUPPLY_SCOPE_UNKNOWN
- POWER_SUPPLY_STATUS_CHARGING
- POWER_SUPPLY_STATUS_DISCHARGING
- POWER_SUPPLY_STATUS_FULL
- POWER_SUPPLY_STATUS_NOT_CHARGING
- POWER_SUPPLY_STATUS_UNKNOWN
- POWER_SUPPLY_TECHNOLOGY_LION
- POWER_SUPPLY_TECHNOLOGY_LIPO
- POWER_SUPPLY_TECHNOLOGY_LiFe
- POWER_SUPPLY_TECHNOLOGY_LiMn
- POWER_SUPPLY_TECHNOLOGY_NiCd
- POWER_SUPPLY_TECHNOLOGY_NiMH
- POWER_SUPPLY_TECHNOLOGY_UNKNOWN
- POWER_SUPPLY_TYPE_APPLE_BRICK_ID
- POWER_SUPPLY_TYPE_BATTERY
- POWER_SUPPLY_TYPE_MAINS
- POWER_SUPPLY_TYPE_UNKNOWN
- POWER_SUPPLY_TYPE_UPS
- POWER_SUPPLY_TYPE_USB
- POWER_SUPPLY_TYPE_USB_ACA
- POWER_SUPPLY_TYPE_USB_CDP
- POWER_SUPPLY_TYPE_USB_DCP
- POWER_SUPPLY_TYPE_USB_PD
- POWER_SUPPLY_TYPE_USB_PD_DRP
- POWER_SUPPLY_TYPE_USB_TYPE_C
- POWER_SUPPLY_USB_TYPE_ACA
- POWER_SUPPLY_USB_TYPE_APPLE_BRICK_ID
- POWER_SUPPLY_USB_TYPE_C
- POWER_SUPPLY_USB_TYPE_CDP
- POWER_SUPPLY_USB_TYPE_DCP
- POWER_SUPPLY_USB_TYPE_PD
- POWER_SUPPLY_USB_TYPE_PD_DRP
- POWER_SUPPLY_USB_TYPE_PD_PPS
- POWER_SUPPLY_USB_TYPE_SDP
- POWER_SUPPLY_USB_TYPE_UNKNOWN
- POWER_TABLE_CCK_ENTRY
- POWER_TABLE_CMD
- POWER_TABLE_NUM_ENTRIES
- POWER_TABLE_NUM_HT_OFDM_ENTRIES
- POWER_TARGET_ON
- POWER_TBL_CCK_ENTRY
- POWER_TBL_NUM_ENTRIES
- POWER_TBL_NUM_HT_OFDM_ENTRIES
- POWER_TRI_STATE
- POWER_UNIT
- POWER_UNIT_MASK
- POWER_UNIT_OFFSET
- POWER_UP
- POWER_UP_DELAY_MS
- POWER_UP_TIME
- POWE_TYPE
- POW_ADAPT_DEFAULT_P0
- POW_ADAPT_DEFAULT_P1
- POW_ADAPT_DEFAULT_P2
- POW_CODE
- POW_CYC_EV
- POW_CYC_MASK
- POW_SM
- POW_UP
- PO_DISABLE_GUARD_CHECK
- PO_DISABLE_INCR_REF_TAG
- PO_DIS_APP_TAG_REPL
- PO_DIS_APP_TAG_VALD
- PO_DIS_FRAME_MODE
- PO_DIS_HEADER_MODE
- PO_DIS_REF_TAG_REPL
- PO_DIS_REF_TAG_VALD
- PO_DIS_VALD_APP_ESC
- PO_DIS_VALD_APP_REF_ESC
- PO_ENABLE_DIF_BUNDLING
- PO_ENABLE_INCR_GUARD_SEED
- PO_MODE_DIF_INSERT
- PO_MODE_DIF_PASS
- PO_MODE_DIF_REMOVE
- PO_MODE_DIF_REPLACE
- PO_MODE_DIF_TCP_CKSUM
- PO_POST_DELAY
- PP
- PP0_DATA
- PP0_FN
- PP0_IN
- PP0_OUT
- PP1
- PP1EN
- PP1L
- PP1_DATA
- PP1_FN
- PP1_IN
- PP1_OUT
- PP2
- PP2EN
- PP2L
- PP2_DATA
- PP2_FN
- PP2_IN
- PP2_OUT
- PP3
- PP3_DATA
- PP3_FN
- PP3_IN
- PP3_OUT
- PP4_DATA
- PP4_FN
- PP4_IN
- PP4_OUT
- PP5C_RCT
- PP5C_RIT
- PP5_DATA
- PP5_FN
- PP5_IN
- PP5_OUT
- PPAACE_AF_MW
- PPAACE_AF_MW_SHIFT
- PPAACE_AF_WBAL
- PPAACE_AF_WBAL_SHIFT
- PPAACE_AF_WSE
- PPAACE_AF_WSE_SHIFT
- PPAR
- PPAR_SPR
- PPAR_SSPGPIO
- PPAR_SSPTRSS
- PPAR_UARTGPIO
- PPAR_UARTTR
- PPAR_UPR
- PPAT_CACHED
- PPAT_CACHED_PDE
- PPAT_DISPLAY_ELLC
- PPAT_UNCACHED
- PPA_AUTODETECT
- PPA_BURST_SIZE
- PPA_DEBUG
- PPA_EPP_16
- PPA_EPP_32
- PPA_EPP_8
- PPA_NIBBLE
- PPA_PS2
- PPA_RECON_TMO
- PPA_SELECT_TMO
- PPA_SPIN_TMO
- PPA_UNKNOWN
- PPA_VERSION
- PPBUF_BASE1
- PPBUF_BASE2
- PPB_MULT
- PPB_SCALE_WORD
- PPB_SHIFT_FP40
- PPB_SHIFT_FP44
- PPB_THRESH
- PPB_THRESH_RATE
- PPC
- PPC403
- PPC405
- PPC405EX_CE_RESET
- PPC405EX_SDR0_SRST
- PPC405_ERR77
- PPC405_ERR77_SYNC
- PPC40X_TLB_SIZE
- PPC440
- PPC440EPX_EHCI0_INSREG_BMT
- PPC440EP_ERR42
- PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT
- PPC440SPE_ADMA_ENGINES_NUM
- PPC440SPE_ADMA_THRESHOLD
- PPC440SPE_ADMA_WATCHDOG_MSEC
- PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
- PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT
- PPC440SPE_COHERENT
- PPC440SPE_DEFAULT_POLY
- PPC440SPE_DESC_INT
- PPC440SPE_DESC_PCHECK
- PPC440SPE_DESC_QCHECK
- PPC440SPE_DESC_RXOR
- PPC440SPE_DESC_RXOR12
- PPC440SPE_DESC_RXOR123
- PPC440SPE_DESC_RXOR124
- PPC440SPE_DESC_RXOR125
- PPC440SPE_DESC_RXOR_MSK
- PPC440SPE_DESC_RXOR_REV
- PPC440SPE_DESC_WXOR
- PPC440SPE_DMA0_ID
- PPC440SPE_DMA1_ID
- PPC440SPE_RXOR_RUN
- PPC440SPE_XOR_ID
- PPC440SPE_ZERO_P
- PPC440SPE_ZERO_Q
- PPC44x_EARLY_DEBUG_VIRTADDR
- PPC44x_EARLY_TLBS
- PPC44x_MMUCR_STS
- PPC44x_MMUCR_TID
- PPC44x_PGD_OFF_MASK_BIT
- PPC44x_PGD_OFF_SHIFT
- PPC44x_PTE_ADD_MASK_BIT
- PPC44x_PTE_ADD_SHIFT
- PPC44x_TLBE_SIZE
- PPC44x_TLB_16K
- PPC44x_TLB_16M
- PPC44x_TLB_1K
- PPC44x_TLB_1M
- PPC44x_TLB_256K
- PPC44x_TLB_256M
- PPC44x_TLB_4K
- PPC44x_TLB_64K
- PPC44x_TLB_ATTRIB
- PPC44x_TLB_ATTR_MASK
- PPC44x_TLB_E
- PPC44x_TLB_EPN_MASK
- PPC44x_TLB_ERPN_MASK
- PPC44x_TLB_G
- PPC44x_TLB_I
- PPC44x_TLB_M
- PPC44x_TLB_PAGEID
- PPC44x_TLB_PERM_MASK
- PPC44x_TLB_RPN_MASK
- PPC44x_TLB_SIZE
- PPC44x_TLB_SR
- PPC44x_TLB_SW
- PPC44x_TLB_SX
- PPC44x_TLB_TS
- PPC44x_TLB_U0
- PPC44x_TLB_U1
- PPC44x_TLB_U2
- PPC44x_TLB_U3
- PPC44x_TLB_UR
- PPC44x_TLB_UW
- PPC44x_TLB_UX
- PPC44x_TLB_VALID
- PPC44x_TLB_W
- PPC44x_TLB_XLAT
- PPC460EX_CE_RESET
- PPC460EX_SDR0_SRST
- PPC460SX_CE_RESET
- PPC460SX_SDR0_SRST
- PPC464
- PPC476
- PPC47x_MCSR_FPR
- PPC47x_MCSR_GPR
- PPC47x_MCSR_IPR
- PPC47x_MMUCR_STS
- PPC47x_MMUCR_TID
- PPC47x_TLB0_16K
- PPC47x_TLB0_16M
- PPC47x_TLB0_1G
- PPC47x_TLB0_1M
- PPC47x_TLB0_256M
- PPC47x_TLB0_4K
- PPC47x_TLB0_64K
- PPC47x_TLB0_BOLTED_R
- PPC47x_TLB0_EPN_MASK
- PPC47x_TLB0_TS
- PPC47x_TLB0_VALID
- PPC47x_TLB1_ERPN_MASK
- PPC47x_TLB1_RPN_MASK
- PPC47x_TLB2_ATTR_MASK
- PPC47x_TLB2_E
- PPC47x_TLB2_G
- PPC47x_TLB2_I
- PPC47x_TLB2_IL1D
- PPC47x_TLB2_IL1I
- PPC47x_TLB2_IMG
- PPC47x_TLB2_M
- PPC47x_TLB2_PERM_MASK
- PPC47x_TLB2_SR
- PPC47x_TLB2_SW
- PPC47x_TLB2_SX
- PPC47x_TLB2_S_RW
- PPC47x_TLB2_S_RWX
- PPC47x_TLB2_U0
- PPC47x_TLB2_U1
- PPC47x_TLB2_U2
- PPC47x_TLB2_U3
- PPC47x_TLB2_UR
- PPC47x_TLB2_UW
- PPC47x_TLB2_UX
- PPC47x_TLB2_U_RWX
- PPC47x_TLB2_W
- PPC47x_TLBE_SIZE
- PPC4XX_BYTE_ORDER
- PPC4XX_CTX_DONE_INT
- PPC4XX_DC_3DES_EN
- PPC4XX_EDAC_MESSAGE_SIZE
- PPC4XX_EDAC_MODULE_NAME
- PPC4XX_EDAC_MODULE_REVISION
- PPC4XX_GDR_SIZE
- PPC4XX_INPUT_THRESHOLD
- PPC4XX_INTERRUPT_CLR
- PPC4XX_INT_CFG
- PPC4XX_INT_DESCR_CNT
- PPC4XX_INT_TIMEOUT_CNT
- PPC4XX_INT_TIMEOUT_CNT_REVB
- PPC4XX_LAST_GD
- PPC4XX_LAST_PD
- PPC4XX_LAST_SD
- PPC4XX_NUM_GD
- PPC4XX_NUM_PD
- PPC4XX_NUM_SD
- PPC4XX_OUTPUT_THRESHOLD
- PPC4XX_PDR_POLL
- PPC4XX_PD_DONE_INT
- PPC4XX_PD_SIZE
- PPC4XX_PRNG_CTRL_AUTO_EN
- PPC4XX_RING_POLL
- PPC4XX_RING_RETRY
- PPC4XX_SDR_SIZE
- PPC4XX_SD_BUFFER_SIZE
- PPC4XX_SEC_VERSION_STR
- PPC4XX_TMO_ERR_INT
- PPC4XX_TRNG_CTRL
- PPC4XX_TRNG_CTRL_DALM
- PPC4XX_TRNG_DATA
- PPC4XX_TRNG_EN
- PPC4XX_TRNG_STAT
- PPC4XX_TRNG_STAT_B
- PPC64
- PPC64LE_LEP_OFFSET
- PPC64_ELF_ABI_v1
- PPC64_ELF_ABI_v2
- PPC64_HUGE_HPTE_BATCH
- PPC64_LOCAL_ENTRY_OFFSET
- PPC64_TLB_BATCH_NR
- PPC7450
- PPC750
- PPC860
- PPCA2
- PPCBRLK
- PPCCAP_ULTRAVISOR_BIT
- PPCCHLK
- PPCCOM
- PPCE300
- PPCEFS
- PPCFG_ESDF_EN
- PPCFG_PSSO_EN
- PPCFG_PSS_EN
- PPCFG_TTA
- PPCHTM
- PPCISEL
- PPCLAIM
- PPCLK_COUNT
- PPCLK_DCEFCLK
- PPCLK_DCLK
- PPCLK_DISPCLK
- PPCLK_ECLK
- PPCLK_FCLK
- PPCLK_GFXCLK
- PPCLK_PHYCLK
- PPCLK_PIXCLK
- PPCLK_SOCCLK
- PPCLK_UCLK
- PPCLK_VCLK
- PPCLK_e
- PPCLRIRQ
- PPCMODE_BI_FW
- PPCMODE_BI_SW
- PPCMODE_EPP_BYTE
- PPCMODE_EPP_DWORD
- PPCMODE_EPP_WORD
- PPCMODE_UNI_FW
- PPCMODE_UNI_SW
- PPCONNECT
- PPCPMR
- PPCPS
- PPCPWR2
- PPCR
- PPCRFMCI
- PPCR_CCF
- PPCR_F100_2MHz
- PPCR_F103_2MHz
- PPCR_F114_5MHz
- PPCR_F118_0MHz
- PPCR_F128_9MHz
- PPCR_F132_7MHz
- PPCR_F143_2MHz
- PPCR_F147_5MHz
- PPCR_F157_5MHz
- PPCR_F162_2MHz
- PPCR_F171_8MHz
- PPCR_F176_9MHz
- PPCR_F186_1MHz
- PPCR_F191_7MHz
- PPCR_F200_5MHz
- PPCR_F206_4MHz
- PPCR_F214_8MHz
- PPCR_F221_2MHz
- PPCR_F229_1MHz
- PPCR_F239_6MHz
- PPCR_F243_4MHz
- PPCR_F250_7MHz
- PPCR_F257_7MHz
- PPCR_F265_4MHz
- PPCR_F272_0MHz
- PPCR_F280_2MHz
- PPCR_F57_3MHz
- PPCR_F59_0MHz
- PPCR_F71_6MHz
- PPCR_F73_7MHz
- PPCR_F85_9MHz
- PPCR_F88_5MHz
- PPCR_Fx16
- PPCR_Fx20
- PPCR_Fx24
- PPCR_Fx28
- PPCR_Fx32
- PPCR_Fx36
- PPCR_Fx40
- PPCR_Fx44
- PPCR_Fx48
- PPCR_Fx52
- PPCR_Fx56
- PPCR_Fx60
- PPCR_Fx64
- PPCR_Fx68
- PPCR_Fx72
- PPCR_Fx76
- PPCSPE
- PPCSTRUCT
- PPCTMR
- PPCVEC
- PPCVEC2
- PPCVEC3
- PPCVLE
- PPCVSX
- PPCVSX2
- PPCVSX3
- PPC_40x_TURN_OFF_MSR_DR
- PPC_ACQUIRE_BARRIER
- PPC_ADD
- PPC_ADDI
- PPC_ADDIS
- PPC_ADMA_INIT_ALLOC
- PPC_ADMA_INIT_CHANNEL
- PPC_ADMA_INIT_COHERENT
- PPC_ADMA_INIT_IRQ1
- PPC_ADMA_INIT_IRQ2
- PPC_ADMA_INIT_MEMREG
- PPC_ADMA_INIT_MEMRES
- PPC_ADMA_INIT_OK
- PPC_ADMA_INIT_REGISTER
- PPC_AND
- PPC_ANDI
- PPC_AND_DOT
- PPC_ATOMIC_ENTRY_BARRIER
- PPC_ATOMIC_EXIT_BARRIER
- PPC_BCC
- PPC_BCC_SHORT
- PPC_BCTR
- PPC_BIT
- PPC_BIT32
- PPC_BIT8
- PPC_BITEXTRACT
- PPC_BITLSHIFT
- PPC_BITLSHIFT32
- PPC_BITLSHIFT8
- PPC_BITMASK
- PPC_BITMASK32
- PPC_BITMASK8
- PPC_BLR
- PPC_BLRL
- PPC_BPF_LDARX
- PPC_BPF_LL
- PPC_BPF_LOAD_CPU
- PPC_BPF_LWARX
- PPC_BPF_STDCX
- PPC_BPF_STL
- PPC_BPF_STLU
- PPC_BPF_STWCX
- PPC_BREAKPOINT_CONDITION_AND
- PPC_BREAKPOINT_CONDITION_AND_OR
- PPC_BREAKPOINT_CONDITION_BE
- PPC_BREAKPOINT_CONDITION_BE_ALL
- PPC_BREAKPOINT_CONDITION_BE_SHIFT
- PPC_BREAKPOINT_CONDITION_EXACT
- PPC_BREAKPOINT_CONDITION_MODE
- PPC_BREAKPOINT_CONDITION_NONE
- PPC_BREAKPOINT_CONDITION_OR
- PPC_BREAKPOINT_MODE_EXACT
- PPC_BREAKPOINT_MODE_MASK
- PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
- PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
- PPC_BREAKPOINT_TRIGGER_EXECUTE
- PPC_BREAKPOINT_TRIGGER_READ
- PPC_BREAKPOINT_TRIGGER_RW
- PPC_BREAKPOINT_TRIGGER_WRITE
- PPC_CAPABILITIES_BITMAP
- PPC_CCBR
- PPC_CLRBHRB
- PPC_CMPD
- PPC_CMPDI
- PPC_CMPLD
- PPC_CMPLDI
- PPC_CMPLW
- PPC_CMPLWI
- PPC_CMPW
- PPC_CMPWI
- PPC_CNTLZL
- PPC_COPY
- PPC_CP_ABORT
- PPC_DARN
- PPC_DBELL
- PPC_DBELL_CRIT
- PPC_DBELL_LPID
- PPC_DBELL_MSGTYPE
- PPC_DBELL_MSG_BRDCAST
- PPC_DBELL_PIR_MASK
- PPC_DBELL_SERVER
- PPC_DBELL_TYPE
- PPC_DBELL_TYPE_MASK
- PPC_DCBAL
- PPC_DCBZL
- PPC_DEBUG_FEATURE_DATA_BP_DAWR
- PPC_DEBUG_FEATURE_DATA_BP_MASK
- PPC_DEBUG_FEATURE_DATA_BP_RANGE
- PPC_DEBUG_FEATURE_INSN_BP_MASK
- PPC_DEBUG_FEATURE_INSN_BP_RANGE
- PPC_DIVDU
- PPC_DIVWU
- PPC_ELFNOTE_CAPABILITIES
- PPC_ELF_CORE_COPY_REGS
- PPC_ERATILX
- PPC_ERATIVAX
- PPC_ERATRE
- PPC_ERATSX
- PPC_ERATSX_DOT
- PPC_ERATWE
- PPC_EXTSW
- PPC_FEATURE2_ARCH_2_07
- PPC_FEATURE2_ARCH_3_00
- PPC_FEATURE2_DARN
- PPC_FEATURE2_DSCR
- PPC_FEATURE2_EBB
- PPC_FEATURE2_HAS_IEEE128
- PPC_FEATURE2_HTM
- PPC_FEATURE2_HTM_COMP
- PPC_FEATURE2_HTM_NOSC
- PPC_FEATURE2_HTM_NOSC_COMP
- PPC_FEATURE2_HTM_NO_SUSPEND
- PPC_FEATURE2_ISEL
- PPC_FEATURE2_SCV
- PPC_FEATURE2_TAR
- PPC_FEATURE2_VEC_CRYPTO
- PPC_FEATURE_32
- PPC_FEATURE_601_INSTR
- PPC_FEATURE_64
- PPC_FEATURE_ARCH_2_05
- PPC_FEATURE_ARCH_2_06
- PPC_FEATURE_BOOKE
- PPC_FEATURE_CELL
- PPC_FEATURE_HAS_4xxMAC
- PPC_FEATURE_HAS_ALTIVEC
- PPC_FEATURE_HAS_ALTIVEC_COMP
- PPC_FEATURE_HAS_DFP
- PPC_FEATURE_HAS_EFP_DOUBLE
- PPC_FEATURE_HAS_EFP_DOUBLE_COMP
- PPC_FEATURE_HAS_EFP_SINGLE
- PPC_FEATURE_HAS_EFP_SINGLE_COMP
- PPC_FEATURE_HAS_FPU
- PPC_FEATURE_HAS_MMU
- PPC_FEATURE_HAS_SPE
- PPC_FEATURE_HAS_SPE_COMP
- PPC_FEATURE_HAS_VSX
- PPC_FEATURE_HAS_VSX_COMP
- PPC_FEATURE_ICACHE_SNOOP
- PPC_FEATURE_NO_TB
- PPC_FEATURE_PA6T
- PPC_FEATURE_POWER4
- PPC_FEATURE_POWER5
- PPC_FEATURE_POWER5_PLUS
- PPC_FEATURE_POWER6_EXT
- PPC_FEATURE_PPC_LE
- PPC_FEATURE_PSERIES_PERFMON_COMPAT
- PPC_FEATURE_SMT
- PPC_FEATURE_TRUE_LE
- PPC_FEATURE_UNIFIED_CACHE
- PPC_FUNC_ADDR
- PPC_G_DBELL
- PPC_G_DBELL_CRIT
- PPC_G_DBELL_MC
- PPC_H
- PPC_HA
- PPC_HI
- PPC_HTW_E6500
- PPC_HTW_IBM
- PPC_HTW_NONE
- PPC_ICBT
- PPC_ICSWEPX
- PPC_ICSWX
- PPC_INDIRECT_TYPE_BIG_ENDIAN
- PPC_INDIRECT_TYPE_BROKEN_MRM
- PPC_INDIRECT_TYPE_EXT_REG
- PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
- PPC_INDIRECT_TYPE_NO_PCIE_LINK
- PPC_INDIRECT_TYPE_SET_CFG_TYPE
- PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
- PPC_INST_ADD
- PPC_INST_ADDC
- PPC_INST_ADDI
- PPC_INST_ADDIS
- PPC_INST_AND
- PPC_INST_ANDDOT
- PPC_INST_ANDI
- PPC_INST_BCTR
- PPC_INST_BHRBE
- PPC_INST_BLR
- PPC_INST_BLRL
- PPC_INST_BRANCH
- PPC_INST_BRANCH_COND
- PPC_INST_CLRBHRB
- PPC_INST_CMPD
- PPC_INST_CMPDI
- PPC_INST_CMPLD
- PPC_INST_CMPLDI
- PPC_INST_CMPLW
- PPC_INST_CMPLWI
- PPC_INST_CMPW
- PPC_INST_CMPWI
- PPC_INST_COPY
- PPC_INST_COPY_FIRST
- PPC_INST_CP_ABORT
- PPC_INST_DARN
- PPC_INST_DCBA
- PPC_INST_DCBAL
- PPC_INST_DCBA_MASK
- PPC_INST_DCBZL
- PPC_INST_DIVD
- PPC_INST_DIVDU
- PPC_INST_DIVWU
- PPC_INST_ERATILX
- PPC_INST_ERATIVAX
- PPC_INST_ERATRE
- PPC_INST_ERATSX
- PPC_INST_ERATSX_DOT
- PPC_INST_ERATWE
- PPC_INST_EXTSW
- PPC_INST_ICBT
- PPC_INST_ICSWEPX
- PPC_INST_ICSWX
- PPC_INST_ISEL
- PPC_INST_ISEL_MASK
- PPC_INST_ISYNC
- PPC_INST_LBZ
- PPC_INST_LBZCIX
- PPC_INST_LD
- PPC_INST_LDARX
- PPC_INST_LDBRX
- PPC_INST_LDX
- PPC_INST_LD_TOC
- PPC_INST_LFDX
- PPC_INST_LFSX
- PPC_INST_LHBRX
- PPC_INST_LHZ
- PPC_INST_LQARX
- PPC_INST_LSWI
- PPC_INST_LSWX
- PPC_INST_LVX
- PPC_INST_LWARX
- PPC_INST_LWSYNC
- PPC_INST_LWZ
- PPC_INST_LWZX
- PPC_INST_LXVD2X
- PPC_INST_MADDHD
- PPC_INST_MADDHDU
- PPC_INST_MADDLD
- PPC_INST_MCRXR
- PPC_INST_MCRXR_MASK
- PPC_INST_MFLR
- PPC_INST_MFSPR
- PPC_INST_MFSPR_DSCR
- PPC_INST_MFSPR_DSCR_MASK
- PPC_INST_MFSPR_DSCR_USER
- PPC_INST_MFSPR_DSCR_USER_MASK
- PPC_INST_MFSPR_PVR
- PPC_INST_MFSPR_PVR_MASK
- PPC_INST_MFTMR
- PPC_INST_MFVSRD
- PPC_INST_MSGCLR
- PPC_INST_MSGCLRP
- PPC_INST_MSGSND
- PPC_INST_MSGSNDP
- PPC_INST_MSGSYNC
- PPC_INST_MTCTR
- PPC_INST_MTLR
- PPC_INST_MTMSRD
- PPC_INST_MTSPR_DSCR
- PPC_INST_MTSPR_DSCR_MASK
- PPC_INST_MTSPR_DSCR_USER
- PPC_INST_MTSPR_DSCR_USER_MASK
- PPC_INST_MTTMR
- PPC_INST_MTVSRD
- PPC_INST_MULHWU
- PPC_INST_MULLD
- PPC_INST_MULLI
- PPC_INST_MULLW
- PPC_INST_NAP
- PPC_INST_NEG
- PPC_INST_NOP
- PPC_INST_OR
- PPC_INST_ORI
- PPC_INST_ORIS
- PPC_INST_PASTE
- PPC_INST_PASTE_LAST
- PPC_INST_POPCNTB
- PPC_INST_POPCNTB_MASK
- PPC_INST_POPCNTD
- PPC_INST_POPCNTW
- PPC_INST_RFCI
- PPC_INST_RFDI
- PPC_INST_RFEBB
- PPC_INST_RFID
- PPC_INST_RFMCI
- PPC_INST_RLDICL
- PPC_INST_RLDICR
- PPC_INST_RLWIMI
- PPC_INST_RLWINM
- PPC_INST_RLWINM_DOT
- PPC_INST_SC
- PPC_INST_SLBFEE
- PPC_INST_SLBIA
- PPC_INST_SLD
- PPC_INST_SLEEP
- PPC_INST_SLW
- PPC_INST_SRAD
- PPC_INST_SRADI
- PPC_INST_SRAW
- PPC_INST_SRAWI
- PPC_INST_SRD
- PPC_INST_SRW
- PPC_INST_STB
- PPC_INST_STBCIX
- PPC_INST_STD
- PPC_INST_STDCX
- PPC_INST_STDU
- PPC_INST_STDX
- PPC_INST_STD_LR
- PPC_INST_STFDX
- PPC_INST_STFSX
- PPC_INST_STH
- PPC_INST_STOP
- PPC_INST_STQCX
- PPC_INST_STRING
- PPC_INST_STRING_GEN_MASK
- PPC_INST_STRING_MASK
- PPC_INST_STSWI
- PPC_INST_STSWX
- PPC_INST_STVX
- PPC_INST_STW
- PPC_INST_STWCX
- PPC_INST_STWU
- PPC_INST_STXVD2X
- PPC_INST_SUB
- PPC_INST_SYNC
- PPC_INST_SYNC_MASK
- PPC_INST_TABORT
- PPC_INST_TLBIE
- PPC_INST_TLBIEL
- PPC_INST_TLBILX
- PPC_INST_TLBIVAX
- PPC_INST_TLBSRX_DOT
- PPC_INST_TRECHKPT
- PPC_INST_TRECLAIM
- PPC_INST_TSR
- PPC_INST_VCMPEQUB
- PPC_INST_VCMPEQUB_RC
- PPC_INST_VCMPEQUD
- PPC_INST_VCMPEQUD_RC
- PPC_INST_VPERMXOR
- PPC_INST_VPMSUMD
- PPC_INST_VPMSUMW
- PPC_INST_WAIT
- PPC_INST_WINKLE
- PPC_INST_XOR
- PPC_INST_XORI
- PPC_INST_XORIS
- PPC_INST_XVCPSGNDP
- PPC_INST_XXLOR
- PPC_INST_XXSWAPD
- PPC_ISA_3_0_INVALIDATE_ERAT
- PPC_JMP
- PPC_LBZ
- PPC_LBZ_OFFS
- PPC_LCMP
- PPC_LCMPI
- PPC_LCMPLI
- PPC_LD
- PPC_LDARX
- PPC_LDBRX
- PPC_LDD
- PPC_LDD0
- PPC_LDD1
- PPC_LDD2
- PPC_LDD3
- PPC_LDD4
- PPC_LDD5
- PPC_LDD6
- PPC_LDD7
- PPC_LDX
- PPC_LD_OFFS
- PPC_LHBRX
- PPC_LHBRX_OFFS
- PPC_LHZ
- PPC_LHZ_OFFS
- PPC_LI
- PPC_LI32
- PPC_LI64
- PPC_LIS
- PPC_LL
- PPC_LLARX
- PPC_LL_OFFS
- PPC_LO
- PPC_LONG
- PPC_LONG_ALIGN
- PPC_LQARX
- PPC_LR_STKOFF
- PPC_LWARX
- PPC_LWZ
- PPC_LWZ_OFFS
- PPC_L_BIAS
- PPC_L_FCLK
- PPC_L_LCLK
- PPC_L_PCLK
- PPC_MADDHD
- PPC_MADDHDU
- PPC_MADDLD
- PPC_MAX_HPT_ORDER
- PPC_MFBHRBE
- PPC_MIN_HPT_ORDER
- PPC_MIN_STKFRM
- PPC_MODULE_FEATURE_VEC_CRYPTO
- PPC_MR
- PPC_MSGCLR
- PPC_MSGCLRP
- PPC_MSGSND
- PPC_MSGSNDP
- PPC_MSGSYNC
- PPC_MSG_CALL_FUNCTION
- PPC_MSG_NMI_IPI
- PPC_MSG_RESCHEDULE
- PPC_MSG_RM_HOST_ACTION
- PPC_MSG_TICK_BROADCAST
- PPC_MTCTR
- PPC_MTLR
- PPC_MTOCRF
- PPC_MULD
- PPC_MULHWU
- PPC_MULI
- PPC_MULW
- PPC_NAP
- PPC_NEG
- PPC_NOP
- PPC_NTOHS_OFFS
- PPC_OP
- PPC_OPCODE_403
- PPC_OPCODE_405
- PPC_OPCODE_440
- PPC_OPCODE_476
- PPC_OPCODE_601
- PPC_OPCODE_64
- PPC_OPCODE_64_BRIDGE
- PPC_OPCODE_7450
- PPC_OPCODE_750
- PPC_OPCODE_860
- PPC_OPCODE_A2
- PPC_OPCODE_ALTIVEC
- PPC_OPCODE_ALTIVEC2
- PPC_OPCODE_ANY
- PPC_OPCODE_BOOKE
- PPC_OPCODE_BRLOCK
- PPC_OPCODE_CACHELCK
- PPC_OPCODE_CELL
- PPC_OPCODE_COMMON
- PPC_OPCODE_E200Z4
- PPC_OPCODE_E300
- PPC_OPCODE_E500
- PPC_OPCODE_E500MC
- PPC_OPCODE_E6500
- PPC_OPCODE_EFS
- PPC_OPCODE_HTM
- PPC_OPCODE_ISEL
- PPC_OPCODE_PMR
- PPC_OPCODE_POWER
- PPC_OPCODE_POWER2
- PPC_OPCODE_POWER4
- PPC_OPCODE_POWER5
- PPC_OPCODE_POWER6
- PPC_OPCODE_POWER7
- PPC_OPCODE_POWER8
- PPC_OPCODE_POWER9
- PPC_OPCODE_PPC
- PPC_OPCODE_PPCPS
- PPC_OPCODE_RFMCI
- PPC_OPCODE_SPE
- PPC_OPCODE_TITAN
- PPC_OPCODE_TMR
- PPC_OPCODE_VLE
- PPC_OPCODE_VSX
- PPC_OPCODE_VSX3
- PPC_OPERAND_ABSOLUTE
- PPC_OPERAND_CR_BIT
- PPC_OPERAND_CR_REG
- PPC_OPERAND_DQ
- PPC_OPERAND_DS
- PPC_OPERAND_FAKE
- PPC_OPERAND_FCR
- PPC_OPERAND_FPR
- PPC_OPERAND_FSL
- PPC_OPERAND_GPR
- PPC_OPERAND_GPR_0
- PPC_OPERAND_NEGATIVE
- PPC_OPERAND_NEXT
- PPC_OPERAND_OPTIONAL
- PPC_OPERAND_OPTIONAL32
- PPC_OPERAND_OPTIONAL_VALUE
- PPC_OPERAND_PARENS
- PPC_OPERAND_PLUS1
- PPC_OPERAND_RELATIVE
- PPC_OPERAND_SIGNED
- PPC_OPERAND_SIGNOPT
- PPC_OPERAND_UDI
- PPC_OPERAND_VR
- PPC_OPERAND_VSR
- PPC_OPROFILE_CELL
- PPC_OPROFILE_FSL_EMB
- PPC_OPROFILE_G4
- PPC_OPROFILE_INVALID
- PPC_OPROFILE_PA6T
- PPC_OPROFILE_POWER4
- PPC_OPROFILE_RS64
- PPC_OPSHIFT_INV
- PPC_OP_SE_VLE
- PPC_OR
- PPC_ORI
- PPC_ORIS
- PPC_PASTE
- PPC_PIN_SIZE
- PPC_PMCAT
- PPC_PMCTR
- PPC_PMC_DEFAULT
- PPC_PMC_G4
- PPC_PMC_IBM
- PPC_PMC_PA6T
- PPC_POPCNTB
- PPC_POPCNTD
- PPC_POPCNTW
- PPC_PTRACE_DELHWDEBUG
- PPC_PTRACE_GETHWDBGINFO
- PPC_PTRACE_PEEKDATA_3264
- PPC_PTRACE_PEEKTEXT_3264
- PPC_PTRACE_PEEKUSR_3264
- PPC_PTRACE_POKEDATA_3264
- PPC_PTRACE_POKETEXT_3264
- PPC_PTRACE_POKEUSR_3264
- PPC_PTRACE_SETHWDEBUG
- PPC_RADIX_INVALIDATE_ERAT_GUEST
- PPC_RADIX_INVALIDATE_ERAT_USER
- PPC_REG_BITS
- PPC_REG_DECODE
- PPC_REG_VAL
- PPC_RELEASE_BARRIER
- PPC_RFCI
- PPC_RFDI
- PPC_RFMCI
- PPC_RLDICL
- PPC_RLDICR
- PPC_RLWIMI
- PPC_RLWINM
- PPC_RLWINM_DOT
- PPC_RXD1
- PPC_RXD2
- PPC_RXD3
- PPC_RXD4
- PPC_SCLK
- PPC_SFRM
- PPC_SLBFEE_DOT
- PPC_SLBIA
- PPC_SLD
- PPC_SLDI
- PPC_SLEEP
- PPC_SLW
- PPC_SLWI
- PPC_SRAD
- PPC_SRADI
- PPC_SRAW
- PPC_SRAWI
- PPC_SRD
- PPC_SRDI
- PPC_SRW
- PPC_SRWI
- PPC_STB
- PPC_STD
- PPC_STDU
- PPC_STDX
- PPC_STH
- PPC_STL
- PPC_STLCX
- PPC_STLU
- PPC_STOP
- PPC_STQCX
- PPC_STW
- PPC_STWU
- PPC_SUB
- PPC_TLBIE
- PPC_TLBIEL
- PPC_TLBIE_5
- PPC_TLBILX
- PPC_TLBILX_ALL
- PPC_TLBILX_PID
- PPC_TLBILX_VA
- PPC_TLBIVAX
- PPC_TLBSRX_DOT
- PPC_TLNEI
- PPC_TXD1
- PPC_TXD2
- PPC_TXD3
- PPC_TXD4
- PPC_UNIT
- PPC_WAIT
- PPC_WARN_ALIGNMENT
- PPC_WARN_EMULATED
- PPC_WINKLE
- PPC_XOR
- PPC_XORI
- PPC_XORIS
- PPDATADIR
- PPDR
- PPDR_In
- PPDR_Out
- PPE
- PPE32_CGEN
- PPEF
- PPEN
- PPEV2_CFG_RSS_TBL_4N0_M
- PPEV2_CFG_RSS_TBL_4N0_S
- PPEV2_CFG_RSS_TBL_4N1_M
- PPEV2_CFG_RSS_TBL_4N1_S
- PPEV2_CFG_RSS_TBL_4N2_M
- PPEV2_CFG_RSS_TBL_4N2_S
- PPEV2_CFG_RSS_TBL_4N3_M
- PPEV2_CFG_RSS_TBL_4N3_S
- PPEV2_CFG_TSO_EN_REG
- PPEV2_INDRECTION_TBL_REG
- PPEV2_RSS_KEY_REG
- PPEV2_VLAN_STRIP_EN_REG
- PPEXCL
- PPE_BUF_SIZE_SHIFT
- PPE_CFG_AXI_DBG_REG
- PPE_CFG_BUS_BIG_ENDIEN
- PPE_CFG_BUS_CTRL_REG
- PPE_CFG_BUS_LOCAL_REL
- PPE_CFG_CPU_ADD_ADDR
- PPE_CFG_HEAT_DECT_TIME0_REG
- PPE_CFG_HEAT_DECT_TIME1_REG
- PPE_CFG_MAX_FRAME_LEN_REG
- PPE_CFG_PARSE_TAG_REG
- PPE_CFG_PAUSE_IDLE_CNT_REG
- PPE_CFG_POOL_GRP
- PPE_CFG_PRO_CHECK_EN_REG
- PPE_CFG_QID_MODE_CF_QID_MODE_M
- PPE_CFG_QID_MODE_CF_QID_MODE_S
- PPE_CFG_QID_MODE_DEF_QID_M
- PPE_CFG_QID_MODE_DEF_QID_S
- PPE_CFG_QOS_VMID_GEN
- PPE_CFG_QOS_VMID_GRP_SHIFT
- PPE_CFG_QOS_VMID_MODE
- PPE_CFG_RX_ADDR
- PPE_CFG_RX_BUF_SIZE
- PPE_CFG_RX_CTRL_ALIGN_SHIFT
- PPE_CFG_RX_CTRL_REG
- PPE_CFG_RX_DEPTH_SHIFT
- PPE_CFG_RX_FIFO_FSFU
- PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG
- PPE_CFG_RX_FIFO_SIZE
- PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG
- PPE_CFG_RX_FIFO_THRSLD_REG
- PPE_CFG_RX_PKT_ALIGN
- PPE_CFG_RX_PKT_INT
- PPE_CFG_RX_PKT_INT_REG
- PPE_CFG_RX_PKT_MODE_REG
- PPE_CFG_RX_START_SHIFT
- PPE_CFG_RX_VLAN_TAG_REG
- PPE_CFG_STS_MODE
- PPE_CFG_STS_RX_PKT_CNT_RC
- PPE_CFG_TAG_GEN_REG
- PPE_CFG_TNL_TO_BE_RST_REG
- PPE_CFG_TX_FIFO_THRSLD_REG
- PPE_CFG_XGE_MODE_REG
- PPE_CNT_CLR_CE_B
- PPE_CNT_CLR_SNAP_EN_B
- PPE_COMMON_CNT_CLR_CE_B
- PPE_COMMON_CNT_CLR_SNAP_EN_B
- PPE_COMMON_MODE_DEBUG
- PPE_COMMON_MODE_MAX
- PPE_COMMON_MODE_SERVICE
- PPE_COMMON_REG_OFFSET
- PPE_COM_CFG_QID_MODE_REG
- PPE_COM_COMMON_CNT_CLR_CE_REG
- PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG
- PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG
- PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG
- PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG
- PPE_COM_INTEN_REG
- PPE_COM_INTSTS_REG
- PPE_COM_RINT_REG
- PPE_CURR_BUF_CNT
- PPE_CURR_CFF_DATA_NUM_REG
- PPE_CURR_RX_FIFO0_REG
- PPE_CURR_RX_FIFO1_REG
- PPE_CURR_RX_ST_REG
- PPE_CURR_TNL_CAN_RST_REG
- PPE_CURR_TX_FIFO0_REG
- PPE_CURR_TX_FIFO1_REG
- PPE_CURR_TX_ST_REG
- PPE_ECO0_REG
- PPE_ECO1_REG
- PPE_ECO2_REG
- PPE_HIS_PRO_ERR_REG
- PPE_HIS_RX_APP_BUF_FAIL_CNT_REG
- PPE_HIS_RX_APP_BUF_WAIT_CNT_REG
- PPE_HIS_RX_PKT_CNT
- PPE_HIS_RX_PKT_DROP_FUL_CNT_REG
- PPE_HIS_RX_PKT_DROP_PRT_CNT_REG
- PPE_HIS_RX_PKT_NO_BUF_CNT_REG
- PPE_HIS_RX_SW_PKT_CNT_REG
- PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG
- PPE_HIS_TNL_FIFO_ERR_REG
- PPE_HIS_TX_BD_CNT_REG
- PPE_HIS_TX_PKT_CNT_REG
- PPE_HIS_TX_PKT_CS_FAIL_CNT_REG
- PPE_HIS_TX_PKT_EPT_CNT_REG
- PPE_HIS_TX_PKT_OK_CNT_REG
- PPE_INTEN
- PPE_INTEN_REG
- PPE_INTSTS
- PPE_INTSTS_REG
- PPE_INT_GAPTIME_B
- PPE_INT_GAPTIME_M
- PPE_MODE_GE
- PPE_MODE_XGE
- PPE_QID_MODE0
- PPE_QID_MODE1
- PPE_QID_MODE10
- PPE_QID_MODE11
- PPE_QID_MODE2
- PPE_QID_MODE3
- PPE_QID_MODE4
- PPE_QID_MODE5
- PPE_QID_MODE6
- PPE_QID_MODE7
- PPE_QID_MODE8
- PPE_QID_MODE9
- PPE_REG_OFFSET
- PPE_RINT
- PPE_RINT_REG
- PPE_TNL_0_5_CNT_CLR_CE_REG
- PPE_TX_BUF_HOLD
- PPF
- PPFCONTROL
- PPFEAR_MAX_NUM_ENTRIES
- PPFR
- PPFR_LCD
- PPFR_PPCEn
- PPFR_PerEn
- PPFR_SP1RX
- PPFR_SP1TX
- PPFR_SP2RX
- PPFR_SP2TX
- PPFR_SP3RX
- PPFR_SP3TX
- PPFR_SP4
- PPGETFLAGS
- PPGETMODE
- PPGETMODES
- PPGETPHASE
- PPGETTIME
- PPGETTIME32
- PPGETTIME64
- PPGPKT_STRUCT
- PPGTT_BUFFER
- PPHYSTATUS
- PPHY_SCR_t
- PPHY_STATUS_RPT_8192CD_T
- PPHY_STATUS_RPT_8812_T
- PPHY_SUSB
- PPIP32
- PPI_BUSYPPI
- PPI_CLRFLG
- PPI_CLRSIPO
- PPI_CLS_ATMR
- PPI_C_TX_READY_HS
- PPI_D0S_ATMR
- PPI_D0S_CLRSIPOCOUNT
- PPI_D1S_ATMR
- PPI_D1S_CLRSIPOCOUNT
- PPI_D2S_ATMR
- PPI_D2S_CLRSIPOCOUNT
- PPI_D3S_ATMR
- PPI_D3S_CLRSIPOCOUNT
- PPI_D_RX_ULPS_ESC
- PPI_LANEENABLE
- PPI_LINEINITCNT
- PPI_LPTXTIMECNT
- PPI_RANGE
- PPI_STARTPPI
- PPI_START_FUNCTION
- PPI_TPM_REQ_MAX
- PPI_TX_RX_TA
- PPI_VS_REQ_END
- PPI_VS_REQ_START
- PPLL_ANALOG_CNTL__regs_pw_spare_MASK
- PPLL_ANALOG_CNTL__regs_pw_spare__SHIFT
- PPLL_ATOMIC_UPDATE_EN
- PPLL_ATOMIC_UPDATE_R
- PPLL_ATOMIC_UPDATE_W
- PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_exp__SHIFT
- PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_gi_crse_mant__SHIFT
- PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_exp__SHIFT
- PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_gp_crse_mant__SHIFT
- PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_frac_res__SHIFT
- PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res_MASK
- PPLL_BW_CTRL_COARSE__reg_tmg_nctl_crse_res__SHIFT
- PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3_MASK
- PPLL_BW_CTRL_FINE__pw_pc_dpll_cfg_3__SHIFT
- PPLL_CAL_CTRL__pw_pc_bypass_freq_lock_MASK
- PPLL_CAL_CTRL__pw_pc_bypass_freq_lock__SHIFT
- PPLL_CAL_CTRL__pw_pc_kdco_cal_dis_MASK
- PPLL_CAL_CTRL__pw_pc_kdco_cal_dis__SHIFT
- PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis_MASK
- PPLL_CAL_CTRL__pw_pc_kdco_incr_cal_dis__SHIFT
- PPLL_CAL_CTRL__pw_pc_kdco_ratio_MASK
- PPLL_CAL_CTRL__pw_pc_kdco_ratio__SHIFT
- PPLL_CAL_CTRL__pw_pc_meas_win_sel_MASK
- PPLL_CAL_CTRL__pw_pc_meas_win_sel__SHIFT
- PPLL_CAL_CTRL__pw_pc_nctl_adj_dis_MASK
- PPLL_CAL_CTRL__pw_pc_nctl_adj_dis__SHIFT
- PPLL_CAL_CTRL__pw_pc_refclk_rate_MASK
- PPLL_CAL_CTRL__pw_pc_refclk_rate__SHIFT
- PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl_MASK
- PPLL_CAL_CTRL__pw_pc_tdc_cal_ctrl__SHIFT
- PPLL_CAL_CTRL__pw_pc_tdc_cal_en_MASK
- PPLL_CAL_CTRL__pw_pc_tdc_cal_en__SHIFT
- PPLL_CFG1
- PPLL_CLKOUT_CNTL__regs_cc_resetb_MASK
- PPLL_CLKOUT_CNTL__regs_cc_resetb__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_dvoclk_pre_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_idclk_en_MASK
- PPLL_CLKOUT_CNTL__regs_pw_idclk_en__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_idclk_obs_sel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_idclk_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_idclk_pre_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_pixclk_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_pixclk_pre_pdivsel__SHIFT
- PPLL_CLKOUT_CNTL__regs_pw_refclk_sel_MASK
- PPLL_CLKOUT_CNTL__regs_pw_refclk_sel__SHIFT
- PPLL_CNTL
- PPLL_DEBUG0__pw_pc_alt_nctl_MASK
- PPLL_DEBUG0__pw_pc_alt_nctl__SHIFT
- PPLL_DEBUG0__pw_pc_alt_nctl_en_MASK
- PPLL_DEBUG0__pw_pc_alt_nctl_en__SHIFT
- PPLL_DEBUG0__pw_pc_coarse_tdc_dis_MASK
- PPLL_DEBUG0__pw_pc_coarse_tdc_dis__SHIFT
- PPLL_DEBUG0__pw_pc_dft_capture_MASK
- PPLL_DEBUG0__pw_pc_dft_capture__SHIFT
- PPLL_DEBUG0__pw_pc_dft_sel_MASK
- PPLL_DEBUG0__pw_pc_dft_sel__SHIFT
- PPLL_DEBUG0__pw_pc_fine_tdc_dis_MASK
- PPLL_DEBUG0__pw_pc_fine_tdc_dis__SHIFT
- PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis_MASK
- PPLL_DEBUG0__pw_pc_nctl_coarse_step_dis__SHIFT
- PPLL_DEBUG0__pw_pc_phase_jump_trig_MASK
- PPLL_DEBUG0__pw_pc_phase_jump_trig__SHIFT
- PPLL_DEBUG0__pw_pc_trig_coarse_step_MASK
- PPLL_DEBUG0__pw_pc_trig_coarse_step__SHIFT
- PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL_MASK
- PPLL_DEBUG_MUX_CNTL__DEBUG_BUS_MUX_SEL__SHIFT
- PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK
- PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1__SHIFT
- PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2_MASK
- PPLL_DFT_CNTL__regs_pw_obs_clk_sel_2__SHIFT
- PPLL_DFT_CNTL__regs_pw_obs_div_sel_1_MASK
- PPLL_DFT_CNTL__regs_pw_obs_div_sel_1__SHIFT
- PPLL_DFT_CNTL__regs_pw_obs_en_MASK
- PPLL_DFT_CNTL__regs_pw_obs_en__SHIFT
- PPLL_DFT_CNTL__regs_pw_obs_sel_MASK
- PPLL_DFT_CNTL__regs_pw_obs_sel__SHIFT
- PPLL_DIV_0
- PPLL_DIV_1
- PPLL_DIV_2
- PPLL_DIV_3
- PPLL_DIV_SEL_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_FB_DIV_CHANGED__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_REF_DIV_CHANGED__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ACK__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_CURRENT_STATE__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_ENABLE__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_PENDING__SHIFT
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ_MASK
- PPLL_DIV_UPDATE_DEBUG__PLL_UPDATE_REQ__SHIFT
- PPLL_DIV_UPDATE_DEBUG__TieLow2_MASK
- PPLL_DIV_UPDATE_DEBUG__TieLow2__SHIFT
- PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING_MASK
- PPLL_DIV_UPDATE_DEBUG__dbg_UPDATE_PENDING__SHIFT
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE_MASK
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_CURRENT_STATE__SHIFT
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED_MASK
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_FB_DIV_CHANGED__SHIFT
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK_MASK
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ACK__SHIFT
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE_MASK
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_ENABLE__SHIFT
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ_MASK
- PPLL_DIV_UPDATE_DEBUG__tmg_reg_UPDATE_REQ__SHIFT
- PPLL_DRV
- PPLL_FB3_DIV_MASK
- PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac_MASK
- PPLL_FREQ_CTRL0__reg_tmg_fcw0_frac__SHIFT
- PPLL_FREQ_CTRL0__reg_tmg_fcw0_int_MASK
- PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT
- PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK
- PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac__SHIFT
- PPLL_FREQ_CTRL1__reg_tmg_fcw1_int_MASK
- PPLL_FREQ_CTRL1__reg_tmg_fcw1_int__SHIFT
- PPLL_FREQ_CTRL2__reg_tmg_fcw_denom_MASK
- PPLL_FREQ_CTRL2__reg_tmg_fcw_denom__SHIFT
- PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac_MASK
- PPLL_FREQ_CTRL2__reg_tmg_fcw_slew_frac__SHIFT
- PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1_MASK
- PPLL_FREQ_CTRL3__pw_pc_dpll_cfg_1__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK
- PPLL_FREQ_CTRL3__reg_tmg_fcw_sel__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_fracn_en_MASK
- PPLL_FREQ_CTRL3__reg_tmg_fracn_en__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en_MASK
- PPLL_FREQ_CTRL3__reg_tmg_freq_jump_en__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_refclk_div_MASK
- PPLL_FREQ_CTRL3__reg_tmg_refclk_div__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_ssc_en_MASK
- PPLL_FREQ_CTRL3__reg_tmg_ssc_en__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_tdc_resol_MASK
- PPLL_FREQ_CTRL3__reg_tmg_tdc_resol__SHIFT
- PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div_MASK
- PPLL_FREQ_CTRL3__reg_tmg_vco_pre_div__SHIFT
- PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel_MASK
- PPLL_LOOP_CTRL__pw_pc_clk_nctl_sel__SHIFT
- PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel_MASK
- PPLL_LOOP_CTRL__pw_pc_clk_tdc_sel__SHIFT
- PPLL_LOOP_CTRL__pw_pc_fb_slip_dis_MASK
- PPLL_LOOP_CTRL__pw_pc_fb_slip_dis__SHIFT
- PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk_MASK
- PPLL_LOOP_CTRL__pw_pc_fbclk_track_refclk__SHIFT
- PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en_MASK
- PPLL_LOOP_CTRL__pw_pc_fbdiv_mask_en__SHIFT
- PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis_MASK
- PPLL_LOOP_CTRL__pw_pc_nctl_sig_del_dis__SHIFT
- PPLL_LOOP_CTRL__pw_pc_phase_offset_MASK
- PPLL_LOOP_CTRL__pw_pc_phase_offset__SHIFT
- PPLL_LOOP_CTRL__pw_pc_prbs_en_MASK
- PPLL_LOOP_CTRL__pw_pc_prbs_en__SHIFT
- PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel_MASK
- PPLL_LOOP_CTRL__pw_pc_sig_del_patt_sel__SHIFT
- PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en_MASK
- PPLL_LOOP_CTRL__pw_pc_tdc_clk_gate_en__SHIFT
- PPLL_MODE_CNTL__pw_pc_multi_phase_en_MASK
- PPLL_MODE_CNTL__pw_pc_multi_phase_en__SHIFT
- PPLL_MODE_CNTL__pw_pc_refclk_gate_dis_MASK
- PPLL_MODE_CNTL__pw_pc_refclk_gate_dis__SHIFT
- PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK
- PPLL_MODE_CNTL__reg_tmg_pwr_state__SHIFT
- PPLL_OBSERVE0_OUT__disppll_core_obsout_MASK
- PPLL_OBSERVE0_OUT__disppll_core_obsout__SHIFT
- PPLL_OBSERVE0__pw_pc_anaobs_sel_MASK
- PPLL_OBSERVE0__pw_pc_anaobs_sel__SHIFT
- PPLL_OBSERVE0__pw_pc_clear_sticky_lock_MASK
- PPLL_OBSERVE0__pw_pc_clear_sticky_lock__SHIFT
- PPLL_OBSERVE0__pw_pc_dco_cfg_MASK
- PPLL_OBSERVE0__pw_pc_dco_cfg__SHIFT
- PPLL_OBSERVE0__pw_pc_lock_det_dis_MASK
- PPLL_OBSERVE0__pw_pc_lock_det_dis__SHIFT
- PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps_MASK
- PPLL_OBSERVE0__pw_pc_lock_det_tdc_steps__SHIFT
- PPLL_OBSERVE1__pw_pc_digobs_div_MASK
- PPLL_OBSERVE1__pw_pc_digobs_div__SHIFT
- PPLL_OBSERVE1__pw_pc_digobs_sel_MASK
- PPLL_OBSERVE1__pw_pc_digobs_sel__SHIFT
- PPLL_OBSERVE1__pw_pc_digobs_trig_div_MASK
- PPLL_OBSERVE1__pw_pc_digobs_trig_div__SHIFT
- PPLL_OBSERVE1__pw_pc_digobs_trig_sel_MASK
- PPLL_OBSERVE1__pw_pc_digobs_trig_sel__SHIFT
- PPLL_OBSERVE1__reg_tmg_lock_timer_MASK
- PPLL_OBSERVE1__reg_tmg_lock_timer__SHIFT
- PPLL_POST3_DIV_MASK
- PPLL_POSTDIV__reg_tmg_pixclk_pdiv2_MASK
- PPLL_POSTDIV__reg_tmg_pixclk_pdiv2__SHIFT
- PPLL_POSTDIV__reg_tmg_postdiv_MASK
- PPLL_POSTDIV__reg_tmg_postdiv__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_ref2core_sel_MASK
- PPLL_REFCLK_CNTL__regs_pw_ref2core_sel__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_en__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk0_recv_sel__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_en__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk1_recv_sel__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_en__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk2_recv_sel__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_en__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel_MASK
- PPLL_REFCLK_CNTL__regs_pw_refclk3_recv_sel__SHIFT
- PPLL_REFCLK_CNTL__regs_pw_refdivsrc_MASK
- PPLL_REFCLK_CNTL__regs_pw_refdivsrc__SHIFT
- PPLL_REF_DIV
- PPLL_REF_DIV_MASK
- PPLL_RESET
- PPLL_SLEEP
- PPLL_SPARE0__PLL_SPARE0_MASK
- PPLL_SPARE0__PLL_SPARE0__SHIFT
- PPLL_SPARE1__PLL_SPARE1_MASK
- PPLL_SPARE1__PLL_SPARE1__SHIFT
- PPLL_STATUS_DEBUG0__obsout_MASK
- PPLL_STATUS_DEBUG0__obsout__SHIFT
- PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp_MASK
- PPLL_STATUS_DEBUG1__core_disppll_pwr_ok_vddp__SHIFT
- PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp_MASK
- PPLL_STATUS_DEBUG1__core_disppll_rcu_dc_resetb_vddp__SHIFT
- PPLL_STATUS_DEBUG1__dbg_pll_rdy_MASK
- PPLL_STATUS_DEBUG1__dbg_pll_rdy__SHIFT
- PPLL_STATUS_DEBUG__PLL_CAL_RESULT_MASK
- PPLL_STATUS_DEBUG__PLL_CAL_RESULT__SHIFT
- PPLL_STATUS_DEBUG__PLL_DEBUG_BUS_MASK
- PPLL_STATUS_DEBUG__PLL_DEBUG_BUS__SHIFT
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB_MASK
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_ISO_ENB__SHIFT
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_S_MASK
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_S__SHIFT
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_V_MASK
- PPLL_STATUS_DEBUG__PLL_POWERGOOD_V__SHIFT
- PPLL_STATUS_DEBUG__PLL_UNLOCK_MASK
- PPLL_STATUS_DEBUG__PLL_UNLOCK__SHIFT
- PPLL_TURNOFF
- PPLL_UPDATE_CNTL__TieLow1_MASK
- PPLL_UPDATE_CNTL__TieLow1__SHIFT
- PPLL_UPDATE_CNTL__pc_pw_pll_rdy_MASK
- PPLL_UPDATE_CNTL__pc_pw_pll_rdy__SHIFT
- PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK_MASK
- PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_LOCK__SHIFT
- PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT_MASK
- PPLL_UPDATE_CNTL__reg_tmg_PLL_UPDATE_POINT__SHIFT
- PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING_MASK
- PPLL_UPDATE_CNTL__tmg_reg_UPDATE_PENDING__SHIFT
- PPLL_VGA_ATOMIC_UPDATE_EN
- PPLL_VREG_CFG__pw_pc_bleeder_ac_MASK
- PPLL_VREG_CFG__pw_pc_bleeder_ac__SHIFT
- PPLL_VREG_CFG__pw_pc_bleeder_en_MASK
- PPLL_VREG_CFG__pw_pc_bleeder_en__SHIFT
- PPLL_VREG_CFG__pw_pc_dpll_cfg_2_MASK
- PPLL_VREG_CFG__pw_pc_dpll_cfg_2__SHIFT
- PPLL_VREG_CFG__pw_pc_is_1p2_MASK
- PPLL_VREG_CFG__pw_pc_is_1p2__SHIFT
- PPLL_VREG_CFG__pw_pc_reg_obs_sel_MASK
- PPLL_VREG_CFG__pw_pc_reg_obs_sel__SHIFT
- PPLL_VREG_CFG__pw_pc_reg_off_hi_MASK
- PPLL_VREG_CFG__pw_pc_reg_off_hi__SHIFT
- PPLL_VREG_CFG__pw_pc_reg_off_lo_MASK
- PPLL_VREG_CFG__pw_pc_reg_off_lo__SHIFT
- PPLL_VREG_CFG__pw_pc_reg_on_mode_MASK
- PPLL_VREG_CFG__pw_pc_reg_on_mode__SHIFT
- PPLL_VREG_CFG__pw_pc_rlad_tap_sel_MASK
- PPLL_VREG_CFG__pw_pc_rlad_tap_sel__SHIFT
- PPLL_VREG_CFG__pw_pc_scale_driver_MASK
- PPLL_VREG_CFG__pw_pc_scale_driver__SHIFT
- PPLL_VREG_CFG__pw_pc_sel_bump_MASK
- PPLL_VREG_CFG__pw_pc_sel_bump__SHIFT
- PPLL_VREG_CFG__pw_pc_sel_rladder_x_MASK
- PPLL_VREG_CFG__pw_pc_sel_rladder_x__SHIFT
- PPLL_VREG_CFG__pw_pc_short_rc_filt_x_MASK
- PPLL_VREG_CFG__pw_pc_short_rc_filt_x__SHIFT
- PPLL_VREG_CFG__pw_pc_vref_pwr_on_MASK
- PPLL_VREG_CFG__pw_pc_vref_pwr_on__SHIFT
- PPLN
- PPL_ERROR_STOP
- PPL_HDR_ENTRY_SPACE
- PPL_HDR_MAX_ENTRIES
- PPL_HDR_RESERVED
- PPL_HEADER_SIZE
- PPL_INVALID_STATE
- PPL_IO_INLINE_BVECS
- PPL_PAUSED
- PPL_RESET
- PPL_RESTORED
- PPL_RUNNING
- PPL_SAVED
- PPL_SPACE_SIZE
- PPL_UNINITIALIZED
- PPM256
- PPMASK
- PPMDRIFTMAX_HI
- PPMMAX_MASK
- PPMU_ALT_SIPR
- PPMU_ARCH_207S
- PPMU_BEVT0SEL
- PPMU_BEVT1SEL
- PPMU_BEVT2SEL
- PPMU_BEVT3SEL
- PPMU_BEVTxSEL
- PPMU_CCNT
- PPMU_CCNT_MASK
- PPMU_CNTENC
- PPMU_CNTENS
- PPMU_COUNTER_RESET
- PPMU_DISABLE
- PPMU_ENABLE
- PPMU_EVENT
- PPMU_FLAG
- PPMU_HAS_SIER
- PPMU_HAS_SSLOT
- PPMU_INTENC
- PPMU_INTENS
- PPMU_LIMITED_PMC5_6
- PPMU_LIMITED_PMC_OK
- PPMU_LIMITED_PMC_REQD
- PPMU_NO_CONT_SAMPLING
- PPMU_NO_SIAR
- PPMU_NO_SIPR
- PPMU_ONLY_COUNT_RUN
- PPMU_PMCNT0
- PPMU_PMCNT0_MASK
- PPMU_PMCNT1
- PPMU_PMCNT1_MASK
- PPMU_PMCNT2
- PPMU_PMCNT2_MASK
- PPMU_PMCNT3_HIGH
- PPMU_PMCNT3_LOW
- PPMU_PMCNT3_MASK
- PPMU_PMNC
- PPMU_PMNCNT0
- PPMU_PMNCNT1
- PPMU_PMNCNT2
- PPMU_PMNCNT3
- PPMU_PMNCNT_MAX
- PPMU_PMNCT
- PPMU_PMNC_CC_DIVIDER_MASK
- PPMU_PMNC_CC_RESET_MASK
- PPMU_PMNC_CC_RESET_SHIFT
- PPMU_PMNC_COUNTER_RESET_MASK
- PPMU_PMNC_COUNTER_RESET_SHIFT
- PPMU_PMNC_ENABLE_MASK
- PPMU_PMNC_ENABLE_SHIFT
- PPMU_PMNC_START_MODE_MASK
- PPMU_READ_OVERFLOW_CNT
- PPMU_READ_PENDING_CNT
- PPMU_READ_UNDERFLOW_CNT
- PPMU_RO_BUSY_CYCLE_CNT
- PPMU_RO_DATA_CNT
- PPMU_RO_LATENCY
- PPMU_RO_REQUEST_CNT
- PPMU_RW_BUSY_CYCLE_CNT
- PPMU_SIAR_VALID
- PPMU_V2_CCNT
- PPMU_V2_CH_EV0_TYPE
- PPMU_V2_CH_EV1_TYPE
- PPMU_V2_CH_EV2_TYPE
- PPMU_V2_CH_EV3_TYPE
- PPMU_V2_CH_EVx_TYPE
- PPMU_V2_CIG_CFG0
- PPMU_V2_CIG_CFG1
- PPMU_V2_CIG_CFG2
- PPMU_V2_CIG_RESULT
- PPMU_V2_CNTENC
- PPMU_V2_CNTENS
- PPMU_V2_CNT_AUTO
- PPMU_V2_CNT_RESET
- PPMU_V2_EVT3_RW_DATA_CNT
- PPMU_V2_FLAG
- PPMU_V2_INTENC
- PPMU_V2_INTENS
- PPMU_V2_INTERRUPT_RESET
- PPMU_V2_MODE_AUTO
- PPMU_V2_MODE_CIG
- PPMU_V2_MODE_MANUAL
- PPMU_V2_PMCNT0
- PPMU_V2_PMCNT1
- PPMU_V2_PMCNT2
- PPMU_V2_PMCNT3_HIGH
- PPMU_V2_PMCNT3_LOW
- PPMU_V2_PMNC
- PPMU_V2_PMNCT
- PPMU_V2_PMNC_START_MODE_MASK
- PPMU_V2_PMNC_START_MODE_SHIFT
- PPMU_V2_RO_DATA_CNT
- PPMU_V2_SM_ID_A
- PPMU_V2_SM_ID_V
- PPMU_V2_SM_OTHERS_A
- PPMU_V2_SM_OTHERS_V
- PPMU_V2_WO_DATA_CNT
- PPMU_WO_BUSY_CYCLE_CNT
- PPMU_WO_DATA_CNT
- PPMU_WO_LATENCY
- PPMU_WO_REQUEST_CNT
- PPMU_WRITE_OVERFLOW_CNT
- PPMU_WRITE_PENDING_CNT
- PPMU_WRITE_UNDERFLOW_CNT
- PPM_FRACTION
- PPM_SCALE
- PPM_SCALE_INV
- PPM_SCALE_INV_SHIFT
- PPN
- PPN64
- PPNEGOT
- PPN_MASK
- PPOD_CLUSTER_SIZE
- PPOD_COLOR
- PPOD_COLOR_SHIFT
- PPOD_IDX_MAX_SIZE
- PPOD_IDX_SHIFT
- PPOD_PAGES_MAX
- PPOD_PAGES_SHIFT
- PPOD_PI_CHECK_CTL
- PPOD_PI_CHECK_CTL_MASK
- PPOD_PI_CHECK_CTL_SHIFT
- PPOD_PI_EXTRACT_CTL
- PPOD_PI_EXTRACT_CTL_FLAG
- PPOD_PI_EXTRACT_CTL_SHIFT
- PPOD_PI_REPORT_CTL
- PPOD_PI_REPORT_CTL_MASK
- PPOD_PI_REPORT_CTL_SHIFT
- PPOD_PI_TYPE
- PPOD_PI_TYPE_MASK
- PPOD_PI_TYPE_SHIFT
- PPOD_SIZE_SHIFT
- PPOD_TAG
- PPOD_TAG_SHIFT
- PPOD_TID
- PPOD_TID_SHIFT
- PPOD_VALID
- PPOD_VALID_FLAG
- PPOD_VALID_SHIFT
- PPORT_2819_GET
- PPORT_2819_OFF
- PPORT_2863_GET
- PPORT_2863_OFF
- PPORT_802_3_GET
- PPORT_802_3_OFF
- PPORT_ETH_EXT_GET
- PPORT_ETH_EXT_OFF
- PPORT_PER_PRIO_GET
- PPORT_PER_PRIO_OFF
- PPORT_PER_TC_CONGEST_PRIO_OFF
- PPORT_PER_TC_PRIO_OFF
- PPORT_PHY_STATISTICAL_GET
- PPORT_PHY_STATISTICAL_OFF
- PPPIOCATTACH
- PPPIOCATTCHAN
- PPPIOCCONNECT
- PPPIOCDETACH
- PPPIOCDISCONN
- PPPIOCGASYNCMAP
- PPPIOCGCHAN
- PPPIOCGDEBUG
- PPPIOCGFLAGS
- PPPIOCGIDLE
- PPPIOCGIDLE32
- PPPIOCGL2TPSTATS
- PPPIOCGMRU
- PPPIOCGNPMODE
- PPPIOCGRASYNCMAP
- PPPIOCGUNIT
- PPPIOCGXASYNCMAP
- PPPIOCNEWUNIT
- PPPIOCSACTIVE
- PPPIOCSACTIVE32
- PPPIOCSASYNCMAP
- PPPIOCSCOMPRESS
- PPPIOCSCOMPRESS32
- PPPIOCSDEBUG
- PPPIOCSFLAGS
- PPPIOCSMAXCID
- PPPIOCSMRRU
- PPPIOCSMRU
- PPPIOCSNPMODE
- PPPIOCSPASS
- PPPIOCSPASS32
- PPPIOCSRASYNCMAP
- PPPIOCSXASYNCMAP
- PPPIOCXFERUNIT
- PPPOATM_ENCAPS_AUTODETECT
- PPPOATM_ENCAPS_LLC
- PPPOATM_ENCAPS_VC
- PPPOEIOCDFWD
- PPPOEIOCSFWD
- PPPOEIOCSFWD32
- PPPOE_HASH_BITS
- PPPOE_HASH_MASK
- PPPOE_HASH_SIZE
- PPPOE_SES_HLEN
- PPPOL2TP_DRV_VERSION
- PPPOL2TP_HEADER_OVERHEAD
- PPPOL2TP_L2TP_HDR_SIZE_NOSEQ
- PPPOL2TP_L2TP_HDR_SIZE_SEQ
- PPPOL2TP_MSG_CONTROL
- PPPOL2TP_MSG_DATA
- PPPOL2TP_MSG_DEBUG
- PPPOL2TP_MSG_SEQ
- PPPOL2TP_SO_DEBUG
- PPPOL2TP_SO_LNSMODE
- PPPOL2TP_SO_RECVSEQ
- PPPOL2TP_SO_REORDERTO
- PPPOL2TP_SO_SENDSEQ
- PPPOLARIS10_TARGETACTIVITY_DFLT
- PPPOX_BOUND
- PPPOX_CONNECTED
- PPPOX_DEAD
- PPPOX_NONE
- PPPOX_RELAY
- PPPSYNC_MAX_RQLEN
- PPP_ADDRESS
- PPP_ALLSTATIONS
- PPP_AT
- PPP_ATCP
- PPP_CBCP
- PPP_CCP
- PPP_CCPFRAG
- PPP_CHAP
- PPP_COMP
- PPP_COMPFRAG
- PPP_CONTROL
- PPP_ESCAPE
- PPP_FCS
- PPP_FCSLEN
- PPP_FLAG
- PPP_GOODFCS
- PPP_HDRLEN
- PPP_INITFCS
- PPP_IP
- PPP_IPCP
- PPP_IPV6
- PPP_IPV6CP
- PPP_IPX
- PPP_IPXCP
- PPP_LCP
- PPP_LCP_ECHOREP
- PPP_LCP_ECHOREQ
- PPP_LQR
- PPP_MAJOR
- PPP_MAX_RQLEN
- PPP_MP
- PPP_MPLSCP
- PPP_MPLS_MC
- PPP_MPLS_UC
- PPP_MP_CB
- PPP_MP_MAX_QLEN
- PPP_MRU
- PPP_PAP
- PPP_PROTO
- PPP_PROTOCOL
- PPP_TRANS
- PPP_UI
- PPP_VERSION
- PPP_VJC_COMP
- PPP_VJC_UNCOMP
- PPR0
- PPRCONTROL
- PPRDATA
- PPRECONTROL
- PPREGKEY_VEGA10QUADRATICEQUATION_DFLT
- PPREGKEY_VEGA12QUADRATICEQUATION_DFLT
- PPREGKEY_VEGA20QUADRATICEQUATION_DFLT
- PPRELEASE
- PPRFIFO
- PPRINT_MAPV_KIND_BASIC
- PPRINT_MAPV_KIND_INT128
- PPRSTATUS
- PPR_1
- PPR_2
- PPR_3
- PPR_4
- PPR_CONTROL__PPR_IntCoallesce_En_MASK
- PPR_CONTROL__PPR_IntCoallesce_En__SHIFT
- PPR_CONTROL__PPR_IntReqDelay_MASK
- PPR_CONTROL__PPR_IntReqDelay__SHIFT
- PPR_CONTROL__PPR_IntTimeDelay_MASK
- PPR_CONTROL__PPR_IntTimeDelay__SHIFT
- PPR_CONTROL__Reserved_MASK
- PPR_CONTROL__Reserved__SHIFT
- PPR_DEVID
- PPR_ENTRY_SIZE
- PPR_FAILURE
- PPR_FAULT_EXEC
- PPR_FAULT_GN
- PPR_FAULT_READ
- PPR_FAULT_RSVD
- PPR_FAULT_USER
- PPR_FAULT_WRITE
- PPR_FLAGS
- PPR_INVALID
- PPR_LOG_ENTRIES
- PPR_LOG_SIZE
- PPR_LOG_SIZE_512
- PPR_LOG_SIZE_SHIFT
- PPR_OPT_DT
- PPR_OPT_IU
- PPR_OPT_MASK
- PPR_OPT_QAS
- PPR_PASID
- PPR_PASID1
- PPR_PASID2
- PPR_PRIORITY
- PPR_REQ_FAULT
- PPR_REQ_TYPE
- PPR_STATUS_MASK
- PPR_STATUS_SHIFT
- PPR_SUCCESS
- PPR_TAG
- PPSCMDx
- PPSEN0
- PPSETFLAGS
- PPSETMODE
- PPSETPHASE
- PPSETTIME
- PPSETTIME32
- PPSETTIME64
- PPSMC_CACHistoryStart
- PPSMC_CACHistoryStop
- PPSMC_CACLongTermAvgDisable
- PPSMC_CACLongTermAvgEnable
- PPSMC_DISPLAY_WATERMARK_HIGH
- PPSMC_DISPLAY_WATERMARK_LOW
- PPSMC_DPM2FLAGS_OCP
- PPSMC_DPM2FLAGS_PWRSHFT
- PPSMC_DPM2FLAGS_TDPCLMP
- PPSMC_DPMStateHistoryStart
- PPSMC_DPMStateHistoryStop
- PPSMC_EVENT_STATUS_DC
- PPSMC_EVENT_STATUS_GPIO17
- PPSMC_EVENT_STATUS_REGULATORHOT
- PPSMC_EVENT_STATUS_THERMAL
- PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE
- PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE
- PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK
- PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK
- PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH
- PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17
- PPSMC_EXTRAFLAGS_PCC_TO_GPIO17
- PPSMC_FlushDataCache
- PPSMC_FlushInstrCache
- PPSMC_GET_AVFS_CURVE
- PPSMC_GET_OVERDRIVE_CURVE
- PPSMC_GeminiModeMaster
- PPSMC_GeminiModeNone
- PPSMC_GeminiModeSlave
- PPSMC_HasDisplay
- PPSMC_MSG_ACPDPM_Config
- PPSMC_MSG_ACPDPM_Disable
- PPSMC_MSG_ACPDPM_Enable
- PPSMC_MSG_ACPDPM_GetEnabledMask
- PPSMC_MSG_ACPDPM_SetEnabledMask
- PPSMC_MSG_ACPPowerOFF
- PPSMC_MSG_ACPPowerON
- PPSMC_MSG_ACP_AutoDPM_ON
- PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT
- PPSMC_MSG_API_GetAsicPower
- PPSMC_MSG_API_GetMclkBusy
- PPSMC_MSG_API_GetMclkFrequency
- PPSMC_MSG_API_GetSclkBusy
- PPSMC_MSG_API_GetSclkFrequency
- PPSMC_MSG_API_GetSvi2Volt_Mvdd
- PPSMC_MSG_API_GetSvi2Volt_Vddc
- PPSMC_MSG_API_GetSvi2Volt_Vddci
- PPSMC_MSG_API_SetSvi2Volt_Mvdd
- PPSMC_MSG_API_SetSvi2Volt_Vddc
- PPSMC_MSG_API_SetSvi2Volt_Vddci
- PPSMC_MSG_ActiveProcessNotify
- PPSMC_MSG_AgmReadPsm
- PPSMC_MSG_AgmResetPsm
- PPSMC_MSG_AgmStartPsm
- PPSMC_MSG_AllStateSweep_Start
- PPSMC_MSG_AllStateSweep_Stop
- PPSMC_MSG_AllowGfxOff
- PPSMC_MSG_AllowLowGfxclkInterrupt
- PPSMC_MSG_AllowLowSclkInterrupt
- PPSMC_MSG_ApplyAvfsCksOffVoltage
- PPSMC_MSG_ArmD3
- PPSMC_MSG_BACO_Cancel
- PPSMC_MSG_BACO_StartMonitor
- PPSMC_MSG_BREAK
- PPSMC_MSG_BacoAudioD3PME
- PPSMC_MSG_BacoWorkAroundFlushVDCI
- PPSMC_MSG_CAC_COLLECTION_OFF
- PPSMC_MSG_CAC_COLLECTION_ON
- PPSMC_MSG_CAC_CORRELATION_OFF
- PPSMC_MSG_CAC_CORRELATION_ON
- PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI
- PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO
- PPSMC_MSG_CancelBacoMonitor
- PPSMC_MSG_CancelDisableOVRDSCLKDS
- PPSMC_MSG_CancelThrottleOVRDSCLKDS
- PPSMC_MSG_ChangeNearTDPLimit
- PPSMC_MSG_ChangeSafePowerLimit
- PPSMC_MSG_ClkTableXferToDram
- PPSMC_MSG_ClkTableXferToSmu
- PPSMC_MSG_CollectCAC_PowerCorreln
- PPSMC_MSG_CollectCAC_SQonly
- PPSMC_MSG_CollectCAC_TemperaturePwr
- PPSMC_MSG_CollectCAC_WeightCalib
- PPSMC_MSG_CondExecDramAddrHi
- PPSMC_MSG_CondExecDramAddrLo
- PPSMC_MSG_ConfigureGfxDidt
- PPSMC_MSG_ConfigureTelemetry
- PPSMC_MSG_ControlIgpuATS
- PPSMC_MSG_DCEPowerOFF
- PPSMC_MSG_DCEPowerON
- PPSMC_MSG_DCE_AllowVoltageAdjustment
- PPSMC_MSG_DCE_RemoveVoltageAdjustment
- PPSMC_MSG_DISABLE_THERMAL_DPM
- PPSMC_MSG_DISPCLK_FROM_DFS
- PPSMC_MSG_DISPCLK_FROM_FCH
- PPSMC_MSG_DISPLAYPHYStatusNotify
- PPSMC_MSG_DPMStateSweepStart
- PPSMC_MSG_DPMStateSweepStop
- PPSMC_MSG_DPM_Activity_Mode
- PPSMC_MSG_DPM_AutoRotate_Mode
- PPSMC_MSG_DPM_Config
- PPSMC_MSG_DPM_Disable
- PPSMC_MSG_DPM_Disable_VCE_HS
- PPSMC_MSG_DPM_Enable
- PPSMC_MSG_DPM_Enable_VCE_HS
- PPSMC_MSG_DPM_FPS_Mode
- PPSMC_MSG_DPM_ForceState
- PPSMC_MSG_DPM_N_LevelsDisabled
- PPSMC_MSG_DPM_Voltage_Pwrmgt
- PPSMC_MSG_DPREFCLK_FROM_DFS
- PPSMC_MSG_DPREFCLK_FROM_FCH
- PPSMC_MSG_DRV_DRAM_ADDR_HI
- PPSMC_MSG_DRV_DRAM_ADDR_LO
- PPSMC_MSG_DYNAMICDISPPHYPOWER
- PPSMC_MSG_DeviceDriverReset
- PPSMC_MSG_Didt_Block_Function
- PPSMC_MSG_DisableACDCGPIOInterrupt
- PPSMC_MSG_DisableAllSmuFeatures
- PPSMC_MSG_DisableAvfs
- PPSMC_MSG_DisableBAPM
- PPSMC_MSG_DisableCac
- PPSMC_MSG_DisableClockGatingFeature
- PPSMC_MSG_DisableDTE
- PPSMC_MSG_DisableDpmDidt
- PPSMC_MSG_DisableFFC
- PPSMC_MSG_DisableGfxOff
- PPSMC_MSG_DisableLowMemoryPstate
- PPSMC_MSG_DisableSmuFeatures
- PPSMC_MSG_DisableSmuFeaturesHigh
- PPSMC_MSG_DisableSmuFeaturesLow
- PPSMC_MSG_DisableULV
- PPSMC_MSG_DisableVddGfx
- PPSMC_MSG_Disable_PCC
- PPSMC_MSG_DisallowGfxOff
- PPSMC_MSG_DramAddrHiPhysical
- PPSMC_MSG_DramAddrHiVirtual
- PPSMC_MSG_DramAddrLoPhysical
- PPSMC_MSG_DramAddrLoVirtual
- PPSMC_MSG_DramBufferSize
- PPSMC_MSG_DramLogSetDramAddrHigh
- PPSMC_MSG_DramLogSetDramAddrLow
- PPSMC_MSG_DramLogSetDramSize
- PPSMC_MSG_DriverDramAddrHi
- PPSMC_MSG_DriverDramAddrLo
- PPSMC_MSG_DriverResetMode
- PPSMC_MSG_ENABLE_THERMAL_DPM
- PPSMC_MSG_EnableACDCGPIOInterrupt
- PPSMC_MSG_EnableAcgBtcTestMode
- PPSMC_MSG_EnableAcgSpreadSpectrum
- PPSMC_MSG_EnableAllSmuFeatures
- PPSMC_MSG_EnableAvfs
- PPSMC_MSG_EnableBAPM
- PPSMC_MSG_EnableCac
- PPSMC_MSG_EnableClockGatingFeature
- PPSMC_MSG_EnableDPMLevel
- PPSMC_MSG_EnableDTE
- PPSMC_MSG_EnableDpmDidt
- PPSMC_MSG_EnableFFC
- PPSMC_MSG_EnableGfxOff
- PPSMC_MSG_EnableLowMemoryPstate
- PPSMC_MSG_EnableModeSwitchRLCNotification
- PPSMC_MSG_EnablePostCode
- PPSMC_MSG_EnableSmuFeatures
- PPSMC_MSG_EnableSmuFeaturesHigh
- PPSMC_MSG_EnableSmuFeaturesLow
- PPSMC_MSG_EnableThermalInterrupt
- PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown
- PPSMC_MSG_EnableULV
- PPSMC_MSG_EnableVRHotGPIOInterrupt
- PPSMC_MSG_EnableVddGfx
- PPSMC_MSG_Enable_PCC
- PPSMC_MSG_EnterBaco
- PPSMC_MSG_EnterULV
- PPSMC_MSG_ExecuteJob
- PPSMC_MSG_ExitBaco
- PPSMC_MSG_ExitULV
- PPSMC_MSG_ExtremitiesTest_Start
- PPSMC_MSG_ExtremitiesTest_Stop
- PPSMC_MSG_ForceGfxContentSave
- PPSMC_MSG_ForceHigh
- PPSMC_MSG_ForceMediumOrHigh
- PPSMC_MSG_ForcePowerDownGfx
- PPSMC_MSG_ForceTDPClamping
- PPSMC_MSG_GFX_CU_PG_DISABLE
- PPSMC_MSG_GFX_CU_PG_ENABLE
- PPSMC_MSG_GPIO17
- PPSMC_MSG_GetAVFSVoltageByDpm
- PPSMC_MSG_GetAverageGfxActivity
- PPSMC_MSG_GetAverageGfxclkActualFrequency
- PPSMC_MSG_GetAverageGfxclkFrequency
- PPSMC_MSG_GetAverageGioActivity
- PPSMC_MSG_GetAverageGraphicsActivity
- PPSMC_MSG_GetAverageSocclkFrequency
- PPSMC_MSG_GetAverageUclkFrequency
- PPSMC_MSG_GetClockFreqMHz
- PPSMC_MSG_GetConservativePowerLimit
- PPSMC_MSG_GetCurrPkgPwr
- PPSMC_MSG_GetCurrentGfxclkIndex
- PPSMC_MSG_GetCurrentLinkIndex
- PPSMC_MSG_GetCurrentRpm
- PPSMC_MSG_GetCurrentSocclkIndex
- PPSMC_MSG_GetCurrentUclkIndex
- PPSMC_MSG_GetCurrentUvdIndex
- PPSMC_MSG_GetCurrentVceIndex
- PPSMC_MSG_GetData
- PPSMC_MSG_GetDcModeMaxDpmFreq
- PPSMC_MSG_GetDebugData
- PPSMC_MSG_GetDpmClockFreq
- PPSMC_MSG_GetDpmFreqByIndex
- PPSMC_MSG_GetDriverIfVersion
- PPSMC_MSG_GetEnabledPsm
- PPSMC_MSG_GetEnabledSmuFeatures
- PPSMC_MSG_GetEnabledSmuFeaturesHigh
- PPSMC_MSG_GetEnabledSmuFeaturesLow
- PPSMC_MSG_GetFclkFrequency
- PPSMC_MSG_GetFeatureStatus
- PPSMC_MSG_GetGfxclkFrequency
- PPSMC_MSG_GetHbmCode
- PPSMC_MSG_GetLiquidTemperature
- PPSMC_MSG_GetMaxAclkLevel
- PPSMC_MSG_GetMaxDpmFreq
- PPSMC_MSG_GetMaxEclkLevel
- PPSMC_MSG_GetMaxGfxclkFrequency
- PPSMC_MSG_GetMaxLclkLevel
- PPSMC_MSG_GetMaxNclkLevel
- PPSMC_MSG_GetMaxPstate
- PPSMC_MSG_GetMaxSclkLevel
- PPSMC_MSG_GetMaxUvdLevel
- PPSMC_MSG_GetMemVidOffset
- PPSMC_MSG_GetMinDpmFreq
- PPSMC_MSG_GetMinGfxclkFrequency
- PPSMC_MSG_GetPlxTemperature
- PPSMC_MSG_GetPptLimit
- PPSMC_MSG_GetSmuVersion
- PPSMC_MSG_GetSocVidOffset
- PPSMC_MSG_GetSsVoltageByDpm
- PPSMC_MSG_GetTelemetry1Offset
- PPSMC_MSG_GetTelemetry1Slope
- PPSMC_MSG_GetTelemetry2Offset
- PPSMC_MSG_GetTelemetry2Slope
- PPSMC_MSG_GetTemperatureEdge
- PPSMC_MSG_GetTemperatureHBM
- PPSMC_MSG_GetTemperatureHotspot
- PPSMC_MSG_GetTemperatureLiquid
- PPSMC_MSG_GetTemperaturePlx
- PPSMC_MSG_GetTemperatureVrMem
- PPSMC_MSG_GetTemperatureVrSoc
- PPSMC_MSG_GetUcodeVersion
- PPSMC_MSG_GetVidOffset_1
- PPSMC_MSG_GetVidOffset_2
- PPSMC_MSG_GetVoltageByDpm
- PPSMC_MSG_GetVoltageByDpmOverdrive
- PPSMC_MSG_GetVrMvddTemperature
- PPSMC_MSG_GetVrVddcTemperature
- PPSMC_MSG_GfxDeviceDriverReset
- PPSMC_MSG_GpuChangeState
- PPSMC_MSG_Halt
- PPSMC_MSG_HasDisplay
- PPSMC_MSG_IOMMUPowerOFF
- PPSMC_MSG_IOMMUPowerON
- PPSMC_MSG_InferredStateSweep_Start
- PPSMC_MSG_InferredStateSweep_Stop
- PPSMC_MSG_InitJobs
- PPSMC_MSG_InitializeAcg
- PPSMC_MSG_IsDeviceRunning
- PPSMC_MSG_LCLKDPM_Disable
- PPSMC_MSG_LCLKDPM_Enable
- PPSMC_MSG_LCLKDPM_GetEnabledMask
- PPSMC_MSG_LCLKDPM_SetEnabledMask
- PPSMC_MSG_LCLK_AutoDPM_ON
- PPSMC_MSG_LCLK_DPM_Config
- PPSMC_MSG_LedConfig
- PPSMC_MSG_LevelDown
- PPSMC_MSG_LevelUp
- PPSMC_MSG_LoadMetaData
- PPSMC_MSG_LoadUcodes
- PPSMC_MSG_LoadVBios
- PPSMC_MSG_MASTER_AutoDPM_OFF
- PPSMC_MSG_MASTER_AutoDPM_ON
- PPSMC_MSG_MASTER_DeepSleep_OFF
- PPSMC_MSG_MASTER_DeepSleep_ON
- PPSMC_MSG_MCLKDPM_Config
- PPSMC_MSG_MCLKDPM_Disable
- PPSMC_MSG_MCLKDPM_Enable
- PPSMC_MSG_MCLKDPM_ForceState
- PPSMC_MSG_MCLKDPM_FreezeLevel
- PPSMC_MSG_MCLKDPM_GetEnabledMask
- PPSMC_MSG_MCLKDPM_NoForcedLevel
- PPSMC_MSG_MCLKDPM_SetEnabledMask
- PPSMC_MSG_MCLKDPM_UnfreezeLevel
- PPSMC_MSG_MCLK_AutoDPM_ON
- PPSMC_MSG_MaximizePerf
- PPSMC_MSG_MclkRetrainingTest
- PPSMC_MSG_MmPowerMonitorRestart
- PPSMC_MSG_MmPowerMonitorStart
- PPSMC_MSG_MmPowerMonitorStop
- PPSMC_MSG_NBDPM_Config
- PPSMC_MSG_NBDPM_Disable
- PPSMC_MSG_NBDPM_Enable
- PPSMC_MSG_NBDPM_ForceNominal
- PPSMC_MSG_NBDPM_ForcePerformance
- PPSMC_MSG_NBDPM_UnForce
- PPSMC_MSG_NoDisplay
- PPSMC_MSG_NoForcedLevel
- PPSMC_MSG_NotifyPowerSource
- PPSMC_MSG_NumOfDisplays
- PPSMC_MSG_OVRDDisableSCLKDS
- PPSMC_MSG_OneLevelsDisabled
- PPSMC_MSG_OptimizeBattery
- PPSMC_MSG_OverDriveSetPercentage
- PPSMC_MSG_OverDriveSetTargetTdp
- PPSMC_MSG_OverridePcieParameters
- PPSMC_MSG_OverrideVoltageControl_SetVddc
- PPSMC_MSG_OverrideVoltageControl_SetVddci
- PPSMC_MSG_PCIE_CascadePLLPowerDown
- PPSMC_MSG_PCIE_CascadePLLPowerUp
- PPSMC_MSG_PCIE_DDIPhyPowerDown
- PPSMC_MSG_PCIE_DDIPhyPowerUp
- PPSMC_MSG_PCIE_DDIPowerDown
- PPSMC_MSG_PCIE_DDIPowerUp
- PPSMC_MSG_PCIE_PHYPowerDown
- PPSMC_MSG_PCIE_PHYPowerUp
- PPSMC_MSG_PCIeDPM_Disable
- PPSMC_MSG_PCIeDPM_Enable
- PPSMC_MSG_PCIeDPM_ForceLevel
- PPSMC_MSG_PCIeDPM_GetEnabledMask
- PPSMC_MSG_PCIeDPM_SetEnabledMask
- PPSMC_MSG_PCIeDPM_UnForceLevel
- PPSMC_MSG_PCIe_AutoDPM_ON
- PPSMC_MSG_PG_PowerDownSIMD
- PPSMC_MSG_PG_PowerUpSIMD
- PPSMC_MSG_PG_SIMD_Config
- PPSMC_MSG_PM_Controller_Start
- PPSMC_MSG_PM_Controller_Stop
- PPSMC_MSG_PM_STATUS_TO_DRAM_OFF
- PPSMC_MSG_PM_STATUS_TO_DRAM_ON
- PPSMC_MSG_PerformBtc
- PPSMC_MSG_PkgPwrLimitDisable
- PPSMC_MSG_PkgPwrLimitEnable
- PPSMC_MSG_PkgPwrSetLimit
- PPSMC_MSG_PmStatusLogSample
- PPSMC_MSG_PmStatusLogStart
- PPSMC_MSG_PowerDownIspByTile
- PPSMC_MSG_PowerDownJpeg
- PPSMC_MSG_PowerDownSdma
- PPSMC_MSG_PowerDownVcn
- PPSMC_MSG_PowerDownVcn0
- PPSMC_MSG_PowerDownVcn1
- PPSMC_MSG_PowerGateAtHub
- PPSMC_MSG_PowerGateMmHub
- PPSMC_MSG_PowerStateNotify
- PPSMC_MSG_PowerUpGfx
- PPSMC_MSG_PowerUpIspByTile
- PPSMC_MSG_PowerUpJpeg
- PPSMC_MSG_PowerUpSdma
- PPSMC_MSG_PowerUpVcn
- PPSMC_MSG_PowerUpVcn0
- PPSMC_MSG_PowerUpVcn1
- PPSMC_MSG_PrepareMp1ForReset
- PPSMC_MSG_PrepareMp1ForShutdown
- PPSMC_MSG_PrepareMp1ForUnload
- PPSMC_MSG_QueryPowerLimit
- PPSMC_MSG_ReadSerialNumBottom32
- PPSMC_MSG_ReadSerialNumTop32
- PPSMC_MSG_ReadVftCell
- PPSMC_MSG_ReenableAcDcInterrupt
- PPSMC_MSG_ReleaseI2CBus
- PPSMC_MSG_ReleaseI2CControl
- PPSMC_MSG_RemoveDCClamp
- PPSMC_MSG_RemoveMargins
- PPSMC_MSG_Remove_DC_Clamp
- PPSMC_MSG_RequestDisplayClockByFreq
- PPSMC_MSG_RequestI2CBus
- PPSMC_MSG_RequestI2CControl
- PPSMC_MSG_ResetDPMCounters
- PPSMC_MSG_ResetToDefaults
- PPSMC_MSG_Reset_Service
- PPSMC_MSG_Resume
- PPSMC_MSG_ResumeFromMinimumPower
- PPSMC_MSG_RunAcgBtc
- PPSMC_MSG_RunAcgInClosedLoop
- PPSMC_MSG_RunAcgInOpenLoop
- PPSMC_MSG_RunAfllBtc
- PPSMC_MSG_RunBtc
- PPSMC_MSG_RunGfxDcBtc
- PPSMC_MSG_RunSocDcBtc
- PPSMC_MSG_RunningOnAC
- PPSMC_MSG_SAMPowerOFF
- PPSMC_MSG_SAMPowerON
- PPSMC_MSG_SAMUDPM_Config
- PPSMC_MSG_SAMUDPM_Disable
- PPSMC_MSG_SAMUDPM_Enable
- PPSMC_MSG_SAMUDPM_GetEnabledMask
- PPSMC_MSG_SAMUDPM_SetEnabledMask
- PPSMC_MSG_SAMU_AutoDPM_ON
- PPSMC_MSG_SCLKDPM_FreezeLevel
- PPSMC_MSG_SCLKDPM_GetEnabledMask
- PPSMC_MSG_SCLKDPM_SetEnabledMask
- PPSMC_MSG_SCLKDPM_UnfreezeLevel
- PPSMC_MSG_SCLK_AutoDPM_ON
- PPSMC_MSG_SDMAPowerOFF
- PPSMC_MSG_SDMAPowerON
- PPSMC_MSG_SMU_DRAM_ADDR_HI
- PPSMC_MSG_SMU_DRAM_ADDR_LO
- PPSMC_MSG_START_DRAM_LOGGING
- PPSMC_MSG_STOP_DRAM_LOGGING
- PPSMC_MSG_SYSPLLPowerOff
- PPSMC_MSG_SYSPLLPowerOn
- PPSMC_MSG_SecureSRBMRead
- PPSMC_MSG_SecureSRBMWrite
- PPSMC_MSG_SetAclkHardMax
- PPSMC_MSG_SetAclkHardMin
- PPSMC_MSG_SetAclkSoftMax
- PPSMC_MSG_SetAclkSoftMin
- PPSMC_MSG_SetAddress
- PPSMC_MSG_SetAllowFclkSwitch
- PPSMC_MSG_SetAllowedFeaturesMaskHigh
- PPSMC_MSG_SetAllowedFeaturesMaskLow
- PPSMC_MSG_SetCACHistoryMode
- PPSMC_MSG_SetClkTableAddrHi
- PPSMC_MSG_SetClkTableAddrLo
- PPSMC_MSG_SetClockGateMask
- PPSMC_MSG_SetCustomGfxDpmParameters
- PPSMC_MSG_SetCustomPolicy
- PPSMC_MSG_SetData
- PPSMC_MSG_SetDfSwitchType
- PPSMC_MSG_SetDisplayCount
- PPSMC_MSG_SetDisplayPhyConfig
- PPSMC_MSG_SetDisplaySizePowerParams
- PPSMC_MSG_SetDppclkVoltageByFreq
- PPSMC_MSG_SetDriverDramAddrHigh
- PPSMC_MSG_SetDriverDramAddrLow
- PPSMC_MSG_SetEclkHardMax
- PPSMC_MSG_SetEclkHardMin
- PPSMC_MSG_SetEclkSoftMax
- PPSMC_MSG_SetEclkSoftMin
- PPSMC_MSG_SetEnabledLevels
- PPSMC_MSG_SetFanMaxRpm
- PPSMC_MSG_SetFanMinPwm
- PPSMC_MSG_SetFanPwmMax
- PPSMC_MSG_SetFanRpmMax
- PPSMC_MSG_SetFanSclkTarget
- PPSMC_MSG_SetFanTemperatureTarget
- PPSMC_MSG_SetFclkGfxClkRatio
- PPSMC_MSG_SetFloorSocVoltage
- PPSMC_MSG_SetForcedLevels
- PPSMC_MSG_SetForcedLevelsAndJump
- PPSMC_MSG_SetFpsThresholdHi
- PPSMC_MSG_SetFpsThresholdLo
- PPSMC_MSG_SetGBDroopSettings
- PPSMC_MSG_SetGeminiApertureHigh
- PPSMC_MSG_SetGeminiApertureLow
- PPSMC_MSG_SetGeminiMode
- PPSMC_MSG_SetGfxCGPG
- PPSMC_MSG_SetGfxclkOverdriveByFreqVid
- PPSMC_MSG_SetGpuPllDfsForSclk
- PPSMC_MSG_SetHardMaxByFreq
- PPSMC_MSG_SetHardMinByFreq
- PPSMC_MSG_SetHardMinDcefclkByFreq
- PPSMC_MSG_SetHardMinDcfclkByFreq
- PPSMC_MSG_SetHardMinFclkByFreq
- PPSMC_MSG_SetHardMinGfxClk
- PPSMC_MSG_SetHardMinIspclkByFreq
- PPSMC_MSG_SetHardMinSocclkByFreq
- PPSMC_MSG_SetHardMinSocclkByIndex
- PPSMC_MSG_SetHardMinVceByIndex
- PPSMC_MSG_SetHardMinVcn
- PPSMC_MSG_SetHbmFanCode
- PPSMC_MSG_SetHbmThrottleCode
- PPSMC_MSG_SetLclkHardMax
- PPSMC_MSG_SetLclkHardMin
- PPSMC_MSG_SetLclkSoftMax
- PPSMC_MSG_SetLclkSoftMin
- PPSMC_MSG_SetLoggerAddressHigh
- PPSMC_MSG_SetLoggerAddressLow
- PPSMC_MSG_SetLoggerBufferSize
- PPSMC_MSG_SetLowGfxclkInterruptThreshold
- PPSMC_MSG_SetLowSclkIntrThreshold
- PPSMC_MSG_SetMGpuFanBoostLimitRpm
- PPSMC_MSG_SetMemVidOffset
- PPSMC_MSG_SetMemoryChannelConfig
- PPSMC_MSG_SetMemoryChannelEnable
- PPSMC_MSG_SetMinDeepSleepDcefclk
- PPSMC_MSG_SetMinDeepSleepDcfclk
- PPSMC_MSG_SetMinDeepSleepSclk
- PPSMC_MSG_SetMinDisplayClock
- PPSMC_MSG_SetMinLinkDpmByIndex
- PPSMC_MSG_SetMinVddcrSocVoltage
- PPSMC_MSG_SetMinVideoFclkFreq
- PPSMC_MSG_SetMinVideoGfxclkFreq
- PPSMC_MSG_SetMmPwrLogDramAddrHi
- PPSMC_MSG_SetMmPwrLogDramAddrLo
- PPSMC_MSG_SetNclkHardMax
- PPSMC_MSG_SetNclkHardMin
- PPSMC_MSG_SetNclkSoftMax
- PPSMC_MSG_SetNclkSoftMin
- PPSMC_MSG_SetPccThrottleLevel
- PPSMC_MSG_SetPhyclkVoltageByFreq
- PPSMC_MSG_SetPowerLimitPercentage
- PPSMC_MSG_SetPptLimit
- PPSMC_MSG_SetPstateHardMax
- PPSMC_MSG_SetPstateHardMin
- PPSMC_MSG_SetPstateSoftMax
- PPSMC_MSG_SetPstateSoftMin
- PPSMC_MSG_SetRccPfcPmeRestoreRegister
- PPSMC_MSG_SetSclkHardMax
- PPSMC_MSG_SetSclkHardMin
- PPSMC_MSG_SetSclkSoftMax
- PPSMC_MSG_SetSclkSoftMin
- PPSMC_MSG_SetSocVidOffset
- PPSMC_MSG_SetSoftMaxByFreq
- PPSMC_MSG_SetSoftMaxFclkByFreq
- PPSMC_MSG_SetSoftMaxGfxClk
- PPSMC_MSG_SetSoftMaxGfxclkByIndex
- PPSMC_MSG_SetSoftMaxSocclkByFreq
- PPSMC_MSG_SetSoftMaxSocclkByIndex
- PPSMC_MSG_SetSoftMaxUclkByIndex
- PPSMC_MSG_SetSoftMaxUvdByIndex
- PPSMC_MSG_SetSoftMaxVceByIndex
- PPSMC_MSG_SetSoftMaxVcn
- PPSMC_MSG_SetSoftMinByFreq
- PPSMC_MSG_SetSoftMinGfxclkByIndex
- PPSMC_MSG_SetSoftMinJpeg
- PPSMC_MSG_SetSoftMinSocclkByIndex
- PPSMC_MSG_SetSoftMinUclkByIndex
- PPSMC_MSG_SetSoftMinUvdByIndex
- PPSMC_MSG_SetSoftMinVceByIndex
- PPSMC_MSG_SetSoftMinVcn
- PPSMC_MSG_SetSystemVirtualDramAddrHigh
- PPSMC_MSG_SetSystemVirtualDramAddrLow
- PPSMC_MSG_SetTDPLimit
- PPSMC_MSG_SetTjMax
- PPSMC_MSG_SetToolsDramAddrHigh
- PPSMC_MSG_SetToolsDramAddrLow
- PPSMC_MSG_SetUclkDownHyst
- PPSMC_MSG_SetUclkFastSwitch
- PPSMC_MSG_SetUlvIpMask
- PPSMC_MSG_SetUvdHardMax
- PPSMC_MSG_SetUvdHardMin
- PPSMC_MSG_SetUvdSoftMax
- PPSMC_MSG_SetUvdSoftMin
- PPSMC_MSG_SetVBITimeout
- PPSMC_MSG_SetVBITimeout_VEGAM
- PPSMC_MSG_SetVidOffset_1
- PPSMC_MSG_SetVidOffset_2
- PPSMC_MSG_SetVideoFps
- PPSMC_MSG_SetWatermarkFrequency
- PPSMC_MSG_SetWorkloadMask
- PPSMC_MSG_SetXgmiMode
- PPSMC_MSG_SmcSpaceSetAddress
- PPSMC_MSG_SoftReset
- PPSMC_MSG_Spmi_Enable
- PPSMC_MSG_Spmi_Timer
- PPSMC_MSG_StartBacoMonitor
- PPSMC_MSG_SwitchNextHigherInfState
- PPSMC_MSG_SwitchNextLowerInfState
- PPSMC_MSG_SwitchToAC
- PPSMC_MSG_SwitchToInitialState
- PPSMC_MSG_SwitchToLowestInfState
- PPSMC_MSG_SwitchToMinimumPower
- PPSMC_MSG_SwitchToNonInfState
- PPSMC_MSG_SwitchToSwState
- PPSMC_MSG_SwitchToSwStateLast
- PPSMC_MSG_TDCLimitDisable
- PPSMC_MSG_TDCLimitEnable
- PPSMC_MSG_THERMAL_OVERDRIVE_Disable
- PPSMC_MSG_THERMAL_OVERDRIVE_Enable
- PPSMC_MSG_TMON_AutoCaliberate_Disable
- PPSMC_MSG_TMON_AutoCaliberate_Enable
- PPSMC_MSG_Test
- PPSMC_MSG_TestMessage
- PPSMC_MSG_Thermal_Cntl_Disable
- PPSMC_MSG_Thermal_Cntl_Enable
- PPSMC_MSG_ThrottleOVRDSCLKDS
- PPSMC_MSG_TransferTableDram2Smu
- PPSMC_MSG_TransferTableSmu2Dram
- PPSMC_MSG_TwoLevelsDisabled
- PPSMC_MSG_UVDDPM_Config
- PPSMC_MSG_UVDDPM_Disable
- PPSMC_MSG_UVDDPM_Enable
- PPSMC_MSG_UVDDPM_GetEnabledMask
- PPSMC_MSG_UVDDPM_SetEnabledMask
- PPSMC_MSG_UVDPowerOFF
- PPSMC_MSG_UVDPowerON
- PPSMC_MSG_UVD_AutoDPM_ON
- PPSMC_MSG_UVD_DPM_Config
- PPSMC_MSG_UVD_HANDSHAKE_OFF
- PPSMC_MSG_UcodeAddressHigh
- PPSMC_MSG_UcodeAddressLow
- PPSMC_MSG_UcodeLoadStatus
- PPSMC_MSG_UpdatePkgPwrPidAlpha
- PPSMC_MSG_UpdatePmeRestore
- PPSMC_MSG_UseBackupPPTable
- PPSMC_MSG_UseDefaultPPTable
- PPSMC_MSG_UseNewGPIOScheme
- PPSMC_MSG_VBIOS_DRAM_ADDR_HI
- PPSMC_MSG_VBIOS_DRAM_ADDR_LO
- PPSMC_MSG_VCEDPM_Config
- PPSMC_MSG_VCEDPM_Disable
- PPSMC_MSG_VCEDPM_Enable
- PPSMC_MSG_VCEDPM_GetEnabledMask
- PPSMC_MSG_VCEDPM_SetEnabledMask
- PPSMC_MSG_VCEPowerOFF
- PPSMC_MSG_VCEPowerON
- PPSMC_MSG_VCE_AutoDPM_ON
- PPSMC_MSG_VddC_Request
- PPSMC_MSG_VddNB_Request
- PPSMC_MSG_VftTableIsValid
- PPSMC_MSG_Voltage_Cntl_Disable
- PPSMC_MSG_Voltage_Cntl_Enable
- PPSMC_MSG_WaflTest
- PPSMC_MSG_WaitForMclkSwitchFinish
- PPSMC_MSG_XDMAPowerOFF
- PPSMC_MSG_XDMAPowerON
- PPSMC_MSG_ZeroLevelsDisabled
- PPSMC_MSG_spare1
- PPSMC_MSG_spare2
- PPSMC_Message_Count
- PPSMC_Msg
- PPSMC_NoDisplay
- PPSMC_OCPActive
- PPSMC_OCPInactive
- PPSMC_PowerShiftActive
- PPSMC_PowerShiftInactive
- PPSMC_Result
- PPSMC_Result_CmdRejectedBusy
- PPSMC_Result_CmdRejectedPrereq
- PPSMC_Result_Failed
- PPSMC_Result_NoMore
- PPSMC_Result_NotNow
- PPSMC_Result_OK
- PPSMC_Result_UnknownCmd
- PPSMC_Result_UnknownVT
- PPSMC_STATEFLAG_AUTO_PULSE_SKIP
- PPSMC_STATEFLAG_DEEPSLEEP_BYPASS
- PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE
- PPSMC_STATEFLAG_POWERBOOST
- PPSMC_STATEFLAG_POWERSHIFT
- PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT
- PPSMC_STATEFLAG_SLOW_READ_MARGIN
- PPSMC_SWSTATE_FLAG_DC
- PPSMC_SWSTATE_FLAG_PCIE_X1
- PPSMC_SWSTATE_FLAG_UVD
- PPSMC_SWSTATE_FLAG_VCE
- PPSMC_SYSTEMFLAG_12CHANNEL
- PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP
- PPSMC_SYSTEMFLAG_GDDR5
- PPSMC_SYSTEMFLAG_GPIO_DC
- PPSMC_SYSTEMFLAG_REGULATOR_HOT
- PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG
- PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO
- PPSMC_SYSTEMFLAG_STEPVDDC
- PPSMC_StartFanControl
- PPSMC_StopFanControl
- PPSMC_TDPClampingActive
- PPSMC_TDPClampingInactive
- PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL
- PPSMC_THERMAL_PROTECT_TYPE_INTERNAL
- PPSMC_THERMAL_PROTECT_TYPE_NONE
- PPSMC_isERROR
- PPSM_MSG_SmcSpaceWriteByteInc
- PPSM_MSG_SmcSpaceWriteDWordInc
- PPSM_MSG_SmcSpaceWriteWordInc
- PPSR
- PPSS_H_CLK
- PPSS_PROC_CLK
- PPSS_PROC_RESET
- PPSS_RESET
- PPSS_TIMER0_CLK
- PPSS_TIMER1_CLK
- PPS_API_VERS
- PPS_API_VERS_1
- PPS_BASE
- PPS_BLC_PMIC
- PPS_BLC_SOC
- PPS_CANPOLL
- PPS_CANWAIT
- PPS_CAPTUREASSERT
- PPS_CAPTUREBOTH
- PPS_CAPTURECLEAR
- PPS_ECHOASSERT
- PPS_ECHOCLEAR
- PPS_FETCH
- PPS_GETCAP
- PPS_GETPARAMS
- PPS_GPIO_NAME
- PPS_INTCOUNT
- PPS_INTMAX
- PPS_INTMIN
- PPS_KC_BIND
- PPS_KC_HARDPPS
- PPS_KC_HARDPPS_FLL
- PPS_KC_HARDPPS_PLL
- PPS_MAXIDX
- PPS_MAXWANDER
- PPS_MAX_NAME_LEN
- PPS_MAX_SOURCES
- PPS_MINIDX
- PPS_OFFSETASSERT
- PPS_OFFSETCLEAR
- PPS_OUPUT_RELOAD_PERIOD
- PPS_POPCORN
- PPS_SETPARAMS
- PPS_TIME_INVALID
- PPS_TSFMT_NTPFP
- PPS_TSFMT_TSPEC
- PPS_TTY_MAGIC
- PPS_VALID
- PPS_VERSION
- PPSx_MASK
- PPTABLE
- PPTABLE_ARCTURUS_SMU_VERSION
- PPTABLE_NV10_SMU_VERSION
- PPTABLE_V10_SMU_VERSION
- PPTABLE_V12_SMU_VERSION
- PPTABLE_V20_SMU_VERSION
- PPTP_ANALOG_TYPE
- PPTP_ASYNC_FRAMING
- PPTP_BAD_CALLID
- PPTP_BAD_FORMAT
- PPTP_BAD_VALUE
- PPTP_BEARER_CAP_ANALOG
- PPTP_BEARER_CAP_DIGITAL
- PPTP_CALL_CLEAR_REQ
- PPTP_CALL_CLEAR_REQUEST
- PPTP_CALL_DISCONNECT_NOTIFY
- PPTP_CALL_ERROR
- PPTP_CALL_IN_CONF
- PPTP_CALL_IN_REP
- PPTP_CALL_IN_REQ
- PPTP_CALL_NONE
- PPTP_CALL_OUT_CONF
- PPTP_CALL_OUT_REQ
- PPTP_CONTROL_PORT
- PPTP_DIGITAL_TYPE
- PPTP_DONT_CARE_BEARER_TYPE
- PPTP_DONT_CARE_FRAMING
- PPTP_DRIVER_VERSION
- PPTP_ECHO_GENERAL_ERROR
- PPTP_ECHO_OK
- PPTP_ECHO_REPLY
- PPTP_ECHO_REQUEST
- PPTP_ERROR_CODE_NONE
- PPTP_FRAME_CAP_ASYNC
- PPTP_FRAME_CAP_SYNC
- PPTP_GRE_STREAM_TIMEOUT
- PPTP_GRE_TIMEOUT
- PPTP_HEADER_OVERHEAD
- PPTP_INCALL_ACCEPT
- PPTP_INCALL_DONT_ACCEPT
- PPTP_INCALL_GENERAL_ERROR
- PPTP_IN_CALL_CONNECT
- PPTP_IN_CALL_REPLY
- PPTP_IN_CALL_REQUEST
- PPTP_MAGIC_COOKIE
- PPTP_MSG_MAX
- PPTP_NOT_CONNECTED
- PPTP_NO_RESOURCE
- PPTP_OUTCALL_BUSY
- PPTP_OUTCALL_CONNECT
- PPTP_OUTCALL_DONT_ACCEPT
- PPTP_OUTCALL_GENERAL_ERROR
- PPTP_OUTCALL_NO_CARRIER
- PPTP_OUTCALL_NO_DIAL_TONE
- PPTP_OUTCALL_TIMEOUT
- PPTP_OUT_CALL_REPLY
- PPTP_OUT_CALL_REQUEST
- PPTP_PACKET_CONTROL
- PPTP_PACKET_MGMT
- PPTP_REMOVE_DEVICE_ERROR
- PPTP_SESSION_CONFIRMED
- PPTP_SESSION_ERROR
- PPTP_SESSION_NONE
- PPTP_SESSION_REQUESTED
- PPTP_SESSION_STOPREQ
- PPTP_SET_LINK_INFO
- PPTP_START_ALREADY_CONNECTED
- PPTP_START_GENERAL_ERROR
- PPTP_START_NOT_AUTHORIZED
- PPTP_START_OK
- PPTP_START_SESSION_REPLY
- PPTP_START_SESSION_REQUEST
- PPTP_START_UNKNOWN_PROTOCOL
- PPTP_STOP_GENERAL_ERROR
- PPTP_STOP_LOCAL_SHUTDOWN
- PPTP_STOP_NONE
- PPTP_STOP_OK
- PPTP_STOP_PROTOCOL
- PPTP_STOP_SESSION_REPLY
- PPTP_STOP_SESSION_REQUEST
- PPTP_SYNC_FRAMING
- PPTP_WAN_ERROR_NOTIFY
- PPTT_ABORT_PACKAGE
- PPT_THROTTLER_COUNT
- PPT_THROTTLER_PPT0
- PPT_THROTTLER_PPT1
- PPT_THROTTLER_PPT2
- PPT_THROTTLER_PPT3
- PPT_THROTTLER_e
- PPTable_Generic_SubTable_Header
- PPTable_t
- PPU_CYCLES_EVENT_NUM
- PPU_CYCLES_GRP_NUM
- PPU_PROFILING
- PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT
- PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT
- PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT
- PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT
- PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT
- PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT
- PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT
- PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT
- PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT
- PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT
- PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT
- PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT
- PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT
- PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT
- PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT
- PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT
- PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT
- PPVEGAM_TARGETACTIVITY_DFLT
- PPWCONTROL
- PPWCTLONIRQ
- PPWDATA
- PPWECONTROL
- PPWFIFO
- PPWSTATUS
- PPYIELD
- PP_ACG_MASK
- PP_AC_DC_SWITCH_GPIO_PINID
- PP_ALLOC_CACHE_REFILL
- PP_ALLOC_CACHE_SIZE
- PP_ASSERT
- PP_ASSERT_WITH_CODE
- PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES
- PP_ATOMFWCTRL_H
- PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES
- PP_ATOMVOLTAGECTRL_H
- PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE
- PP_ATOM_POWER_BUDGET_SHOW_WAIVER
- PP_ATOM_POWER_BUDGET_SHOW_WARNING
- PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR
- PP_AVFS_MASK
- PP_AutoNegCTL
- PP_AutoNegST
- PP_BIT_FDP
- PP_BIT_IDP
- PP_BLK
- PP_BLK_TE
- PP_BLOCK_GFX_3D
- PP_BLOCK_GFX_CG
- PP_BLOCK_GFX_CP
- PP_BLOCK_GFX_MG
- PP_BLOCK_GFX_RLC
- PP_BLOCK_MASK
- PP_BLOCK_SHIFT
- PP_BLOCK_SYS_BIF
- PP_BLOCK_SYS_DRM
- PP_BLOCK_SYS_HDP
- PP_BLOCK_SYS_MC
- PP_BLOCK_SYS_ROM
- PP_BLOCK_SYS_SDMA
- PP_BUFFER_SIZE
- PP_BufCFG
- PP_BufEvent
- PP_BusCTL
- PP_BusST
- PP_CAP
- PP_CG_MSG_ID
- PP_CLAIMED
- PP_CLOCK_STRETCH_MASK
- PP_CMD_FEED
- PP_CMD_IEN
- PP_CMD_INIT
- PP_CMD_SELI
- PP_CMD_STB
- PP_CONTROL
- PP_CS8900_ISADMA
- PP_CS8900_ISAINT
- PP_CS8900_ISAMemB
- PP_CS8920_ISADMA
- PP_CS8920_ISAINT
- PP_CS8920_ISAMemB
- PP_CYCLE
- PP_CYCLE_DELAY_ACTIVE
- PP_ChipID
- PP_Clock
- PP_Clocks
- PP_DAL_POWERLEVEL
- PP_DAL_POWERLEVEL_0
- PP_DAL_POWERLEVEL_1
- PP_DAL_POWERLEVEL_2
- PP_DAL_POWERLEVEL_3
- PP_DAL_POWERLEVEL_4
- PP_DAL_POWERLEVEL_5
- PP_DAL_POWERLEVEL_6
- PP_DAL_POWERLEVEL_7
- PP_DAL_POWERLEVEL_INVALID
- PP_DAL_POWERLEVEL_LOW
- PP_DAL_POWERLEVEL_NOMINAL
- PP_DAL_POWERLEVEL_PERFORMANCE
- PP_DAL_POWERLEVEL_ULTRALOW
- PP_DBG_LOG
- PP_DCEFCLK
- PP_DCEFCLK_DPM_MASK
- PP_DEBUG_H
- PP_DIR_DCLV_2G
- PP_DIVISOR
- PP_DebugReg
- PP_DmaByteCnt
- PP_DmaFrameCnt
- PP_EECMD
- PP_EEData
- PP_ENABLE_GFX_CG_THRU_SMU
- PP_EXCL
- PP_FASTREAD
- PP_FASTWRITE
- PP_FBC_BUDGET_CTL
- PP_FBC_LOSSY_MODE
- PP_FBC_MODE
- PP_FCLK
- PP_FEATURE_MASK
- PP_FLAGMASK
- PP_FLAG_ALL
- PP_FLAG_DMA_MAP
- PP_GFXOFF_MASK
- PP_GROUP_GFX
- PP_GROUP_MASK
- PP_GROUP_MAX
- PP_GROUP_SHIFT
- PP_GROUP_SYS
- PP_GROUP_UNKNOWN
- PP_HOST_TO_SMC_UL
- PP_HOST_TO_SMC_US
- PP_HWMGR_PPT_H
- PP_HWMON_TEMP
- PP_IA
- PP_INTERRUPT_TIMEOUT
- PP_INT_COUNT_VAL
- PP_INVALID_POWER_STATE_ID
- PP_IOCTL
- PP_ISABootBase
- PP_ISABootMask
- PP_ISAIOB
- PP_ISASOF
- PP_ISQ
- PP_LAF
- PP_LINE_COUNT
- PP_LineCTL
- PP_LineST
- PP_MAJOR
- PP_MAX_CLOCK_LEVELS
- PP_MCLK
- PP_MCLK_DPM_MASK
- PP_MMProfilingState
- PP_MMProfilingState_NA
- PP_MMProfilingState_Started
- PP_MMProfilingState_Stopped
- PP_MP1_STATE_NONE
- PP_MP1_STATE_RESET
- PP_MP1_STATE_SHUTDOWN
- PP_MP1_STATE_UNLOAD
- PP_MSG
- PP_MSK_POFM
- PP_MSK_PSUM_MB
- PP_MSK_PSUM_UNITS
- PP_Max_PCIEGen
- PP_Max_PCIELane
- PP_Min_PCIEGen
- PP_Min_PCIELane
- PP_NIslands_CACTABLES
- PP_NIslands_DPM2Parameters
- PP_NIslands_Dpm2PerfLevel
- PP_OD_COMMIT_DPM_TABLE
- PP_OD_DPM_TABLE_COMMAND
- PP_OD_EDIT_MCLK_VDDC_TABLE
- PP_OD_EDIT_SCLK_VDDC_TABLE
- PP_OD_EDIT_VDDC_CURVE
- PP_OD_FUZZY_FAN_CONTROL_MASK
- PP_OD_RESTORE_DEFAULT_TABLE
- PP_OFF_DELAYS
- PP_OFF_FLAGS
- PP_OFF_MAX_ADD_PARTS
- PP_OFF_NBR_ADD_PARTS
- PP_OFF_PART_UNITS
- PP_OFF_RESERVED
- PP_ON
- PP_ON_DELAYS
- PP_OUT_LINE_COUNT
- PP_OVERDRIVE_MASK
- PP_PCIE
- PP_PCIEGen
- PP_PCIEGen1
- PP_PCIEGen2
- PP_PCIEGen3
- PP_PCIEGenInvalid
- PP_PCIELANES_H
- PP_PCIE_DPM_MASK
- PP_POLICY_MASK
- PP_POWERSTATE_H
- PP_POWER_CONTAINMENT_MASK
- PP_PREFIX
- PP_PSM_H
- PP_RD_PTR_IRQ
- PP_READ10
- PP_READY
- PP_REFERENCE_DIVIDER_MASK
- PP_REFERENCE_DIVIDER_SHIFT
- PP_RWRW
- PP_RWRX
- PP_RWXX
- PP_RXRX
- PP_RXXX
- PP_RefreshrateSource
- PP_RefreshrateSource_EDID
- PP_RefreshrateSource_Explicit
- PP_RxCFG
- PP_RxCTL
- PP_RxEvent
- PP_RxFrame
- PP_RxLength
- PP_RxMiss
- PP_RxStatus
- PP_SCLK
- PP_SCLK_DEEP_SLEEP_MASK
- PP_SCLK_DPM_MASK
- PP_SEQUENCE_MASK
- PP_SEQUENCE_NONE
- PP_SEQUENCE_OFF
- PP_SEQUENCE_ON
- PP_SEQUENCE_POWER_DOWN
- PP_SEQUENCE_POWER_UP
- PP_SEQUENCE_STATE_MASK
- PP_SEQUENCE_STATE_OFF_IDLE
- PP_SEQUENCE_STATE_OFF_S0_1
- PP_SEQUENCE_STATE_OFF_S0_2
- PP_SEQUENCE_STATE_OFF_S0_3
- PP_SEQUENCE_STATE_ON_IDLE
- PP_SEQUENCE_STATE_ON_S1_1
- PP_SEQUENCE_STATE_ON_S1_2
- PP_SEQUENCE_STATE_ON_S1_3
- PP_SEQUENCE_STATE_RESET
- PP_SISLANDS_SMC_H
- PP_SIslands_CacConfig
- PP_SIslands_DPM2Parameters
- PP_SIslands_DPM2Status
- PP_SIslands_Dpm2PerfLevel
- PP_SIslands_FanTable
- PP_SIslands_PAPMParameters
- PP_SIslands_PAPMStatus
- PP_SMC_H
- PP_SMC_POWER_PROFILE
- PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT
- PP_SMC_POWER_PROFILE_COMPUTE
- PP_SMC_POWER_PROFILE_COUNT
- PP_SMC_POWER_PROFILE_CUSTOM
- PP_SMC_POWER_PROFILE_FULLSCREEN3D
- PP_SMC_POWER_PROFILE_POWERSAVING
- PP_SMC_POWER_PROFILE_VIDEO
- PP_SMC_POWER_PROFILE_VR
- PP_SMC_TO_HOST_UL
- PP_SMC_TO_HOST_US
- PP_SMC_VOLTAGE_CONTROL_MASK
- PP_SMU10_SMUMANAGER_H
- PP_SMU_NUM_DCFCLK_DPM_LEVELS
- PP_SMU_NUM_FCLK_DPM_LEVELS
- PP_SMU_NUM_MEMCLK_DPM_LEVELS
- PP_SMU_NUM_SOCCLK_DPM_LEVELS
- PP_SMU_NV_DISPCLK
- PP_SMU_NV_PHYCLK
- PP_SMU_NV_PIXELCLK
- PP_SMU_RESULT_FAIL
- PP_SMU_RESULT_OK
- PP_SMU_RESULT_UNDEFINED
- PP_SMU_RESULT_UNSUPPORTED
- PP_SMU_UNSUPPORTED
- PP_SMU_VER_MAX
- PP_SMU_VER_NV
- PP_SMU_VER_RN
- PP_SMU_VER_RV
- PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX
- PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN
- PP_SOCCLK
- PP_SOCCLK_DPM_MASK
- PP_START_POS
- PP_STATE_CG
- PP_STATE_DS
- PP_STATE_LS
- PP_STATE_MASK
- PP_STATE_SD
- PP_STATE_SHIFT
- PP_STATE_SUPPORT_CG
- PP_STATE_SUPPORT_DS
- PP_STATE_SUPPORT_LS
- PP_STATE_SUPPORT_MASK
- PP_STATE_SUPPORT_SD
- PP_STATE_SUPPORT_SHIFT
- PP_STATUS
- PP_STAT_ACK
- PP_STAT_BSY
- PP_STAT_ERR
- PP_STAT_POUT
- PP_STAT_SEL
- PP_STUTTER_MODE
- PP_SYNC_CONFIG_HEIGHT
- PP_SYNC_CONFIG_VSYNC
- PP_SYNC_THRESH
- PP_SYNC_WRCOUNT
- PP_SelfCTL
- PP_SelfST
- PP_StateClassificationBlock
- PP_StateClassificationFlag
- PP_StateClassificationFlag_3DPerformance
- PP_StateClassificationFlag_3DPerformanceLow
- PP_StateClassificationFlag_ACOverdriveTemplate
- PP_StateClassificationFlag_ACPI
- PP_StateClassificationFlag_BACO
- PP_StateClassificationFlag_Boot
- PP_StateClassificationFlag_DCOverdriveTemplate
- PP_StateClassificationFlag_Forced
- PP_StateClassificationFlag_HD2
- PP_StateClassificationFlag_LimitedPowerSource
- PP_StateClassificationFlag_LimitedPowerSource_2
- PP_StateClassificationFlag_Rest
- PP_StateClassificationFlag_Thermal
- PP_StateClassificationFlag_ULV
- PP_StateClassificationFlag_User2DPerformance
- PP_StateClassificationFlag_User3DPerformance
- PP_StateClassificationFlag_UserDCPerformance
- PP_StateClassificationFlag_Uvd
- PP_StateClassificationFlag_UvdHD
- PP_StateClassificationFlag_UvdMVC
- PP_StateClassificationFlag_UvdSD
- PP_StateClassificationFlags
- PP_StateDisplayBlock
- PP_StateLinkedList
- PP_StateMemroyBlock
- PP_StatePcieBlock
- PP_StateSoftwareAlgorithmBlock
- PP_StateUILabel
- PP_StateUILabel_BACO
- PP_StateUILabel_Balanced
- PP_StateUILabel_Battery
- PP_StateUILabel_MiddleHigh
- PP_StateUILabel_MiddleLow
- PP_StateUILabel_None
- PP_StateUILabel_Performance
- PP_StateValidationBlock
- PP_TABLE_MAX
- PP_TABLE_V0
- PP_TABLE_V1
- PP_TABLE_V2
- PP_TABLE_VERSION
- PP_TDR
- PP_TEAR_CHECK_EN
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES
- PP_TEMP_EDGE
- PP_TEMP_JUNCTION
- PP_TEMP_MAX
- PP_TEMP_MEM
- PP_THERMAL_H
- PP_TIMEOUT_MAX_TRIALS
- PP_TemperatureRange
- PP_TestCTL
- PP_TxCFG
- PP_TxCMD
- PP_TxCol
- PP_TxCommand
- PP_TxEvent
- PP_TxFrame
- PP_TxLength
- PP_ULV_MASK
- PP_UVD_CLOCKS
- PP_UVD_HANDSHAKE_MASK
- PP_VBI_TIME_SUPPORT_MASK
- PP_VERSION
- PP_VSYNC_INIT_VAL
- PP_W91284PIC
- PP_WRITE10
- PP_WR_PTR_IRQ
- PQ0_DATA
- PQ0_FN
- PQ0_IN
- PQ0_OUT
- PQ1_DATA
- PQ1_FN
- PQ1_IN
- PQ1_OUT
- PQ2_DATA
- PQ2_FN
- PQ2_IN
- PQ2_OUT
- PQ2_SCCR
- PQ2_SCMR
- PQ3_DATA
- PQ3_FN
- PQ3_IN
- PQ3_OUT
- PQ4_DATA
- PQ4_FN
- PQ4_IN
- PQ4_OUT
- PQCR
- PQI_ADMIN_INDEX_ALIGNMENT
- PQI_ADMIN_IQ_ELEMENT_LENGTH
- PQI_ADMIN_IQ_NUM_ELEMENTS
- PQI_ADMIN_OQ_ELEMENT_LENGTH
- PQI_ADMIN_OQ_NUM_ELEMENTS
- PQI_ADMIN_QUEUE_CREATE_POLL_INTERVAL_MSECS
- PQI_ADMIN_QUEUE_CREATE_TIMEOUT_JIFFIES
- PQI_ADMIN_REQUEST_TIMEOUT_SECS
- PQI_AIO_SERV_RESPONSE_COMPLETE
- PQI_AIO_SERV_RESPONSE_FAILURE
- PQI_AIO_SERV_RESPONSE_TMF_COMPLETE
- PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN
- PQI_AIO_SERV_RESPONSE_TMF_REJECTED
- PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED
- PQI_AIO_STATUS_AIO_PATH_DISABLED
- PQI_AIO_STATUS_INVALID_DEVICE
- PQI_AIO_STATUS_IO_ABORTED
- PQI_AIO_STATUS_IO_ERROR
- PQI_AIO_STATUS_NO_PATH_TO_DEVICE
- PQI_AIO_STATUS_OVERRUN
- PQI_AIO_STATUS_UNDERRUN
- PQI_CMD_STATUS_ABORTED
- PQI_CONFIG_TABLE_ALL_SECTIONS
- PQI_CONFIG_TABLE_MAX_LENGTH
- PQI_CONFIG_TABLE_SECTION_DEBUG
- PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA
- PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES
- PQI_CONFIG_TABLE_SECTION_GENERAL_INFO
- PQI_CONFIG_TABLE_SECTION_HEARTBEAT
- PQI_CONFIG_TABLE_SECTION_SOFT_RESET
- PQI_CONFIG_TABLE_SIGNATURE
- PQI_CREATE_ADMIN_QUEUE_PAIR
- PQI_DATA_IN_OUT_ABORTED
- PQI_DATA_IN_OUT_BUFFER_ERROR
- PQI_DATA_IN_OUT_BUFFER_OVERFLOW
- PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE
- PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA
- PQI_DATA_IN_OUT_ERROR
- PQI_DATA_IN_OUT_GOOD
- PQI_DATA_IN_OUT_HARDWARE_ERROR
- PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION
- PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED
- PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT
- PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED
- PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR
- PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ
- PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED
- PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST
- PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED
- PQI_DATA_IN_OUT_PROTOCOL_ERROR
- PQI_DATA_IN_OUT_TIMEOUT
- PQI_DATA_IN_OUT_UNDERFLOW
- PQI_DATA_IN_OUT_UNSOLICITED_ABORT
- PQI_DEFAULT_QUEUE_GROUP
- PQI_DELETE_ADMIN_QUEUE_PAIR
- PQI_DEVICE_REGISTERS_OFFSET
- PQI_DEVICE_SIGNATURE
- PQI_DEVICE_STATE_ADMIN_QUEUE_PAIR_READY
- PQI_DEVICE_STATE_ALL_REGISTERS_READY
- PQI_DEVICE_STATE_ERROR
- PQI_DEVICE_STATE_POWER_ON_AND_RESET
- PQI_DEVICE_STATE_STATUS_AVAILABLE
- PQI_DEV_INFO_BUFFER_LENGTH
- PQI_ERROR_BUFFER_ELEMENT_LENGTH
- PQI_EVENT_OFA_CANCELLED
- PQI_EVENT_OFA_MEMORY_ALLOCATION
- PQI_EVENT_OFA_QUIESCE
- PQI_EVENT_OQ_ELEMENT_LENGTH
- PQI_EVENT_TYPE_AIO_CONFIG_CHANGE
- PQI_EVENT_TYPE_AIO_STATE_CHANGE
- PQI_EVENT_TYPE_HARDWARE
- PQI_EVENT_TYPE_HOTPLUG
- PQI_EVENT_TYPE_LOGICAL_DEVICE
- PQI_EVENT_TYPE_OFA
- PQI_EVENT_TYPE_PHYSICAL_DEVICE
- PQI_EXTERNAL_RAID_VOLUME_BUS
- PQI_EXTRA_SGL_MEMORY
- PQI_FETCH_PTRAID_DATA
- PQI_FIRMWARE_FEATURE_OFA
- PQI_FIRMWARE_FEATURE_SMP
- PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE
- PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY
- PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ
- PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ
- PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ
- PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ
- PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY
- PQI_GENERAL_ADMIN_IU_LENGTH
- PQI_GENERAL_ADMIN_STATUS_SUCCESS
- PQI_HBA_BUS
- PQI_HEARTBEAT_TIMER_INTERVAL
- PQI_HZ
- PQI_INQUIRY_PAGE0_RETRIES
- PQI_IQ_PROPERTY_IS_AIO_QUEUE
- PQI_LEGACY_INTX_MASK
- PQI_LEGACY_INTX_PENDING
- PQI_LUN_RESET_PENDING_IO_TIMEOUT_SECS
- PQI_LUN_RESET_RETRIES
- PQI_LUN_RESET_RETRY_INTERVAL_MSECS
- PQI_LUN_RESET_TIMEOUT_SECS
- PQI_MAX_BUS
- PQI_MAX_EMBEDDED_SG_DESCRIPTORS
- PQI_MAX_EVENT_DESCRIPTORS
- PQI_MAX_MSIX_VECTORS
- PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE
- PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE
- PQI_MAX_OPERATIONAL_QUEUE_ID
- PQI_MAX_OUTSTANDING_REQUESTS
- PQI_MAX_OUTSTANDING_REQUESTS_KDUMP
- PQI_MAX_QUEUE_GROUPS
- PQI_MAX_TRANSFER_SIZE
- PQI_MAX_TRANSFER_SIZE_KDUMP
- PQI_MIN_MSIX_VECTORS
- PQI_MIN_OPERATIONAL_QUEUE_ID
- PQI_MODE
- PQI_MODE_READY_POLL_INTERVAL_MSECS
- PQI_MODE_READY_TIMEOUT_SECS
- PQI_NUM_EVENT_QUEUE_ELEMENTS
- PQI_NUM_SUPPORTED_EVENTS
- PQI_OFA_MAX_SG_DESCRIPTORS
- PQI_OFA_MEMORY_DESCRIPTOR_LENGTH
- PQI_OFA_SIGNATURE
- PQI_OFA_VERSION
- PQI_OPERATIONAL_INDEX_ALIGNMENT
- PQI_OPERATIONAL_IQ_ELEMENT_LENGTH
- PQI_OPERATIONAL_OQ_ELEMENT_LENGTH
- PQI_PENDING_IO_TIMEOUT_SECS
- PQI_PHYSICAL_DEVICE_BUS
- PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH
- PQI_POST_RESET_DELAY_B4_MSGU_READY
- PQI_PROTOCOL_SOP
- PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT
- PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT
- PQI_RAID_BYPASS_INELIGIBLE
- PQI_RAID_VOLUME_BUS
- PQI_REPORT_EVENT_CONFIG_BUFFER_LENGTH
- PQI_REQUEST_HEADER_LENGTH
- PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT
- PQI_REQUEST_IU_AIO_PATH_IO
- PQI_REQUEST_IU_GENERAL_ADMIN
- PQI_REQUEST_IU_RAID_PATH_IO
- PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG
- PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG
- PQI_REQUEST_IU_TASK_MANAGEMENT
- PQI_REQUEST_IU_VENDOR_GENERAL
- PQI_RESCAN_WORK_DELAY
- PQI_RESERVED_IO_SLOTS
- PQI_RESERVED_IO_SLOTS_EVENT_ACK
- PQI_RESERVED_IO_SLOTS_LUN_RESET
- PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS
- PQI_RESET_ACTION_COMPLETED
- PQI_RESET_ACTION_RESET
- PQI_RESET_POLL_INTERVAL_MSECS
- PQI_RESET_TYPE_FIRM_RESET
- PQI_RESET_TYPE_HARD_RESET
- PQI_RESET_TYPE_NO_RESET
- PQI_RESET_TYPE_SOFT_RESET
- PQI_RESPONSE_IU_AIO_PATH_DISABLED
- PQI_RESPONSE_IU_AIO_PATH_IO_ERROR
- PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS
- PQI_RESPONSE_IU_GENERAL_ADMIN
- PQI_RESPONSE_IU_GENERAL_MANAGEMENT
- PQI_RESPONSE_IU_RAID_PATH_IO_ERROR
- PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS
- PQI_RESPONSE_IU_TASK_MANAGEMENT
- PQI_RESPONSE_IU_VENDOR_EVENT
- PQI_RESPONSE_IU_VENDOR_GENERAL
- PQI_SAS_SCSI_INVALID_DEVTYPE
- PQI_SOFT_RESET_ABORT
- PQI_SOFT_RESET_INITIATE
- PQI_SOFT_RESET_STATUS_POLL_INTERVAL_SECS
- PQI_SOFT_RESET_STATUS_TIMEOUT_SECS
- PQI_STATUS_IDLE
- PQI_SYNC_FLAGS_INTERRUPTABLE
- PQI_UPDATE_TIME_WORK_INTERVAL
- PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE
- PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE
- PQI_VSEP_CISS_BTL
- PQI_WAIT_FOR_COMPLETION_IO_TIMEOUT_SECS
- PQR_ASSOC_OFFSET
- PQ_ATC_EN
- PQ_FLAGS_ACK
- PQ_FLAGS_LB
- PQ_FLAGS_LLT
- PQ_FLAGS_MCOS
- PQ_FLAGS_MTC
- PQ_FLAGS_OFLD
- PQ_FLAGS_OOO
- PQ_FLAGS_RLS
- PQ_FLAGS_VFS
- PQ_INFO_ELEMENT
- PQ_INFO_RAM_GRC_ADDRESS
- PQ_INIT_DEFAULT_TC
- PQ_INIT_DEFAULT_WRR_GROUP
- PQ_INIT_PF_RL
- PQ_INIT_SHARE_VPORT
- PQ_INIT_STATUS_NA
- PQ_INIT_STATUS_READY_FOR_CP
- PQ_INIT_STATUS_READY_FOR_HOST
- PQ_INIT_VF_RL
- PQ_MDS_8E1T1_BRD_REV
- PQ_MDS_8E1T1_PLD_REV
- PQ_PRESENTED
- PQ_QUEUED
- PQ_VOLATILE
- PR
- PR0_DATA
- PR0_FN
- PR0_IN
- PR0_OUT
- PR1_DATA
- PR1_FN
- PR1_IN
- PR1_OUT
- PR2_DATA
- PR2_FN
- PR2_IN
- PR2_OUT
- PR3_DATA
- PR3_FN
- PR3_IN
- PR3_OUT
- PRA
- PRAM0_SIZE
- PRAM1_SIZE
- PRAMDAC_Def
- PRAMDAC_Mask
- PRAMDAC_Print
- PRAMDAC_Read
- PRAMDAC_Val
- PRAMDAC_Write
- PRAMFC_Def
- PRAMFC_Mask
- PRAMFC_Print
- PRAMFC_Read
- PRAMFC_Val
- PRAMFC_Write
- PRAM_Def
- PRAM_FW_VERSION_BIG_ENDIEN
- PRAM_FW_VERSION_BIG_ENDIEN_SHIFT
- PRAM_FW_VERSION_CHIP_VERSION
- PRAM_FW_VERSION_CHIP_VERSION_SHIFT
- PRAM_FW_VERSION_OPTIMIZED
- PRAM_FW_VERSION_OPTIMIZED_SHIFT
- PRAM_FW_VERSION_STORM_ID
- PRAM_FW_VERSION_STORM_ID_SHIFT
- PRAM_Mask
- PRAM_PAGESIZE
- PRAM_Print
- PRAM_Read
- PRAM_SIZE
- PRAM_Val
- PRAM_Write
- PRARGSZ
- PRATEID_IDX
- PRATR_TABLE_MODE
- PRA_OFF
- PRB0_BASE
- PRB0_CTL
- PRB0_HEAD
- PRB0_START
- PRB0_TAIL
- PRB1_BASE
- PRB1_CTL
- PRB1_HEAD
- PRB1_START
- PRB1_TAIL
- PRB2_BASE
- PRBAR
- PRBS7
- PRBS_CTRL_REG
- PRB_CTRL_NIEN
- PRB_CTRL_PACKET_READ
- PRB_CTRL_PACKET_WRITE
- PRB_CTRL_PROTOCOL
- PRB_CTRL_SRST
- PRB_MX_ADDR
- PRB_MX_ADDR_ARE
- PRB_MX_ADDR_CLOCK_SHIFT
- PRB_MX_ADDR_FC_CLOCK
- PRB_MX_ADDR_MAX_MODS
- PRB_MX_ADDR_MAX_MUX
- PRB_MX_ADDR_MOD_SEL_DA1
- PRB_MX_ADDR_MOD_SEL_DA2
- PRB_MX_ADDR_MOD_SEL_FRB
- PRB_MX_ADDR_MOD_SEL_IDE1
- PRB_MX_ADDR_MOD_SEL_IDE2
- PRB_MX_ADDR_MOD_SEL_IMP1
- PRB_MX_ADDR_MOD_SEL_IMP2
- PRB_MX_ADDR_MOD_SEL_MAC1
- PRB_MX_ADDR_MOD_SEL_MAC2
- PRB_MX_ADDR_MOD_SEL_MOP
- PRB_MX_ADDR_MOD_SEL_ODE1
- PRB_MX_ADDR_MOD_SEL_ODE2
- PRB_MX_ADDR_MOD_SEL_OMP1
- PRB_MX_ADDR_MOD_SEL_OMP2
- PRB_MX_ADDR_MOD_SEL_ORS1
- PRB_MX_ADDR_MOD_SEL_ORS2
- PRB_MX_ADDR_MOD_SEL_REG
- PRB_MX_ADDR_MOD_SEL_SHIFT
- PRB_MX_ADDR_MOD_SEL_TBD
- PRB_MX_ADDR_MOD_SEL_VQM1
- PRB_MX_ADDR_MOD_SEL_VQM2
- PRB_MX_ADDR_PCI_CLOCK
- PRB_MX_ADDR_PRB_WORD_COUNT
- PRB_MX_ADDR_SWP
- PRB_MX_ADDR_SYS_CLOCK
- PRB_MX_ADDR_UP
- PRB_MX_ADDR_VALID_FC_MOD
- PRB_MX_ADDR_VALID_PCI_MOD
- PRB_MX_ADDR_VALID_SYS_MOD
- PRB_MX_ADDR_VALID_TOTAL
- PRB_MX_ADDR_VALID_XGM_MOD
- PRB_MX_ADDR_XGM_CLOCK
- PRB_MX_DATA
- PRB_MX_DUMP_TOT_COUNT
- PRB_PROT_NCQ
- PRB_PROT_PACKET
- PRB_PROT_READ
- PRB_PROT_TCQ
- PRB_PROT_TRANSPARENT
- PRB_PROT_WRITE
- PRC
- PRCC_KCKDIS
- PRCC_KCKEN
- PRCC_KCKSR
- PRCC_KCLK_STORE
- PRCC_NUM_PERIPH_CLUSTERS
- PRCC_PCKDIS
- PRCC_PCKEN
- PRCC_PCKSR
- PRCC_PCLK_STORE
- PRCC_PERIPHS_PER_CLUSTER
- PRCC_SHOW
- PRCI_CLKMUXSTATUSREG_OFFSET
- PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK
- PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT
- PRCI_CLK_COREPLL
- PRCI_CLK_DDRPLL
- PRCI_CLK_GEMGXLPLL
- PRCI_CLK_TLCLK
- PRCI_CORECLKSEL_CORECLKSEL_MASK
- PRCI_CORECLKSEL_CORECLKSEL_SHIFT
- PRCI_CORECLKSEL_OFFSET
- PRCI_COREPLLCFG0_BYPASS_MASK
- PRCI_COREPLLCFG0_BYPASS_SHIFT
- PRCI_COREPLLCFG0_DIVF_MASK
- PRCI_COREPLLCFG0_DIVF_SHIFT
- PRCI_COREPLLCFG0_DIVQ_MASK
- PRCI_COREPLLCFG0_DIVQ_SHIFT
- PRCI_COREPLLCFG0_DIVR_MASK
- PRCI_COREPLLCFG0_DIVR_SHIFT
- PRCI_COREPLLCFG0_FSE_MASK
- PRCI_COREPLLCFG0_FSE_SHIFT
- PRCI_COREPLLCFG0_LOCK_MASK
- PRCI_COREPLLCFG0_LOCK_SHIFT
- PRCI_COREPLLCFG0_OFFSET
- PRCI_COREPLLCFG0_RANGE_MASK
- PRCI_COREPLLCFG0_RANGE_SHIFT
- PRCI_DDRPLLCFG0_BYPASS_MASK
- PRCI_DDRPLLCFG0_BYPASS_SHIFT
- PRCI_DDRPLLCFG0_DIVF_MASK
- PRCI_DDRPLLCFG0_DIVF_SHIFT
- PRCI_DDRPLLCFG0_DIVQ_MASK
- PRCI_DDRPLLCFG0_DIVQ_SHIFT
- PRCI_DDRPLLCFG0_DIVR_MASK
- PRCI_DDRPLLCFG0_DIVR_SHIFT
- PRCI_DDRPLLCFG0_FSE_MASK
- PRCI_DDRPLLCFG0_FSE_SHIFT
- PRCI_DDRPLLCFG0_LOCK_MASK
- PRCI_DDRPLLCFG0_LOCK_SHIFT
- PRCI_DDRPLLCFG0_OFFSET
- PRCI_DDRPLLCFG0_RANGE_MASK
- PRCI_DDRPLLCFG0_RANGE_SHIFT
- PRCI_DDRPLLCFG1_CKE_MASK
- PRCI_DDRPLLCFG1_CKE_SHIFT
- PRCI_DDRPLLCFG1_OFFSET
- PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK
- PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT
- PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK
- PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT
- PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK
- PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT
- PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK
- PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT
- PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK
- PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT
- PRCI_DEVICESRESETREG_OFFSET
- PRCI_GEMGXLPLLCFG0_BYPASS_MASK
- PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT
- PRCI_GEMGXLPLLCFG0_DIVF_MASK
- PRCI_GEMGXLPLLCFG0_DIVF_SHIFT
- PRCI_GEMGXLPLLCFG0_DIVQ_MASK
- PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT
- PRCI_GEMGXLPLLCFG0_DIVR_MASK
- PRCI_GEMGXLPLLCFG0_DIVR_SHIFT
- PRCI_GEMGXLPLLCFG0_FSE_MASK
- PRCI_GEMGXLPLLCFG0_FSE_SHIFT
- PRCI_GEMGXLPLLCFG0_LOCK_MASK
- PRCI_GEMGXLPLLCFG0_LOCK_SHIFT
- PRCI_GEMGXLPLLCFG0_OFFSET
- PRCI_GEMGXLPLLCFG0_RANGE_MASK
- PRCI_GEMGXLPLLCFG0_RANGE_SHIFT
- PRCI_GEMGXLPLLCFG1_CKE_MASK
- PRCI_GEMGXLPLLCFG1_CKE_SHIFT
- PRCI_GEMGXLPLLCFG1_OFFSET
- PRCMU_ACLK
- PRCMU_APEATCLK
- PRCMU_APETRACECLK
- PRCMU_AP_DEEP_IDLE
- PRCMU_AP_DEEP_SLEEP
- PRCMU_AP_IDLE
- PRCMU_AP_NO_CHANGE
- PRCMU_AP_SLEEP
- PRCMU_ARMPENDINGIT_ER
- PRCMU_ARMSS
- PRCMU_AUTO_PM_OFF
- PRCMU_AUTO_PM_ON
- PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF
- PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF
- PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF
- PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF
- PRCMU_AUTO_PM_POLICY_NO_CHANGE
- PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT
- PRCMU_AUTO_PM_POWER_ON_HSEM
- PRCMU_B2R2CLK
- PRCMU_BMLCLK
- PRCMU_CAMCLK
- PRCMU_CDCLK
- PRCMU_CLKSRC_ACLK
- PRCMU_CLKSRC_ARMCLKFIX
- PRCMU_CLKSRC_ARMPLL_OBSCLK
- PRCMU_CLKSRC_CLK009
- PRCMU_CLKSRC_CLK38M
- PRCMU_CLKSRC_HDMICLK
- PRCMU_CLKSRC_HSIRXCLK
- PRCMU_CLKSRC_HSITXCLK
- PRCMU_CLKSRC_I2CCLK
- PRCMU_CLKSRC_LCDCLK
- PRCMU_CLKSRC_MSP02CLK
- PRCMU_CLKSRC_SDMMCCLK
- PRCMU_CLKSRC_SIAMMDSPCLK
- PRCMU_CLKSRC_SYSCLK
- PRCMU_CLKSRC_TIMCLK
- PRCMU_CLKSRC_TVCLK
- PRCMU_CLK_38
- PRCMU_CLK_38_DIV
- PRCMU_CLK_38_SRC
- PRCMU_CLK_PLL_DIV_SHIFT
- PRCMU_CLK_PLL_SW_SHIFT
- PRCMU_DEEPIDLE_OK
- PRCMU_DEEP_SLEEP_OK
- PRCMU_DEFAULT_LOW_TEMP
- PRCMU_DEFAULT_MEASURE_TIME
- PRCMU_DISABLE_ESCAPE_CLOCK_DIV
- PRCMU_DISABLE_PLLDSI
- PRCMU_DMACLK
- PRCMU_DPI_CLOCK_SETTING
- PRCMU_DSI0CLK
- PRCMU_DSI0CLK_LCD
- PRCMU_DSI0ESCCLK
- PRCMU_DSI0ESCCLK_LCD
- PRCMU_DSI1CLK
- PRCMU_DSI1CLK_LCD
- PRCMU_DSI1ESCCLK
- PRCMU_DSI1ESCCLK_LCD
- PRCMU_DSI2ESCCLK
- PRCMU_DSI2ESCCLK_LCD
- PRCMU_DSIALTCLK
- PRCMU_DSI_CLOCK_SETTING
- PRCMU_DSI_LP_CLOCK_SETTING
- PRCMU_DSI_PLLOUT_SEL_SETTING
- PRCMU_DSI_RESET_SW
- PRCMU_ENABLE_ESCAPE_CLOCK_DIV
- PRCMU_ENABLE_PLLDSI
- PRCMU_FW_PROJECT_A9420
- PRCMU_FW_PROJECT_L8540
- PRCMU_FW_PROJECT_L8580
- PRCMU_FW_PROJECT_NAME_LEN
- PRCMU_FW_PROJECT_U8400
- PRCMU_FW_PROJECT_U8420
- PRCMU_FW_PROJECT_U8500
- PRCMU_FW_PROJECT_U8500_C1
- PRCMU_FW_PROJECT_U8500_C2
- PRCMU_FW_PROJECT_U8500_C3
- PRCMU_FW_PROJECT_U8500_C4
- PRCMU_FW_PROJECT_U8500_MBB
- PRCMU_FW_PROJECT_U8500_MBL
- PRCMU_FW_PROJECT_U8500_MBL2
- PRCMU_FW_PROJECT_U8520
- PRCMU_FW_PROJECT_U9500
- PRCMU_FW_PROJECT_U9500_MBL
- PRCMU_FW_PROJECT_U9540
- PRCMU_G1CLK
- PRCMU_GIC_NUMBER_REGS
- PRCMU_HDMICLK
- PRCMU_HSIRXCLK
- PRCMU_HSITXCLK
- PRCMU_HVACLK
- PRCMU_I2CCLK
- PRCMU_I2C_READ
- PRCMU_I2C_STOP_EN
- PRCMU_I2C_WRITE
- PRCMU_IDLE_OK
- PRCMU_IPI2CCLK
- PRCMU_LCDCLK
- PRCMU_MCDECLK
- PRCMU_MSP02CLK
- PRCMU_MSP1CLK
- PRCMU_NUM_CLKS
- PRCMU_NUM_REG_CLOCKS
- PRCMU_PER1CLK
- PRCMU_PER2CLK
- PRCMU_PER3CLK
- PRCMU_PER5CLK
- PRCMU_PER6CLK
- PRCMU_PER7CLK
- PRCMU_PLLDDR
- PRCMU_PLLDSI
- PRCMU_PLLDSI_FREQ_SETTING
- PRCMU_PLLDSI_LCD
- PRCMU_PLLDSI_LOCKP_LOCKED
- PRCMU_PLLSOC0
- PRCMU_PLLSOC1
- PRCMU_PRCMU2ARMPENDINGIT_ER
- PRCMU_QOS_APE_OPP
- PRCMU_QOS_ARM_OPP
- PRCMU_QOS_DDR_OPP
- PRCMU_QOS_DEFAULT_VALUE
- PRCMU_RELEASE_RESET_DSS
- PRCMU_RESET_DSIPLL
- PRCMU_RNGCLK
- PRCMU_RTCCLK
- PRCMU_SDMMCCLK
- PRCMU_SDMMCHCLK
- PRCMU_SGACLK
- PRCMU_SIACLK
- PRCMU_SIAMMDSPCLK
- PRCMU_SLEEP_OK
- PRCMU_SLIMCLK
- PRCMU_SPARE1CLK
- PRCMU_SPARE2CLK
- PRCMU_SSPCLK
- PRCMU_SVAMMCSPCLK
- PRCMU_SYSCLK
- PRCMU_TIMCLK
- PRCMU_TIMER_DOWNCOUNT
- PRCMU_TIMER_MODE
- PRCMU_TIMER_REF
- PRCMU_TVCLK
- PRCMU_UARTCLK
- PRCMU_UICCCLK
- PRCMU_UNCLAMP_DSIPLL
- PRCMU_WAKEUP
- PRCMU_WAKEUP_INDEX_ABB
- PRCMU_WAKEUP_INDEX_ABB_FIFO
- PRCMU_WAKEUP_INDEX_ARM
- PRCMU_WAKEUP_INDEX_CD_IRQ
- PRCMU_WAKEUP_INDEX_HSI0
- PRCMU_WAKEUP_INDEX_HSI1
- PRCMU_WAKEUP_INDEX_RTC
- PRCMU_WAKEUP_INDEX_RTT0
- PRCMU_WAKEUP_INDEX_RTT1
- PRCMU_WAKEUP_INDEX_USB
- PRCMU_WDOG_ALL
- PRCMU_WDOG_CPU1
- PRCMU_WDOG_CPU2
- PRCM_A9PL_FORCE_CLKEN
- PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN
- PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN
- PRCM_A9_MASK_ACK
- PRCM_A9_MASK_REQ
- PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ
- PRCM_A9_RESETN_CLR
- PRCM_A9_RESETN_SET
- PRCM_ACK_MB0
- PRCM_ACK_MB0_AP_PWRSTTR_STATUS
- PRCM_ACK_MB0_EVENT_4500_NUMBERS
- PRCM_ACK_MB0_READ_POINTER
- PRCM_ACK_MB0_WAKEUP_0_4500
- PRCM_ACK_MB0_WAKEUP_0_8500
- PRCM_ACK_MB0_WAKEUP_1_4500
- PRCM_ACK_MB0_WAKEUP_1_8500
- PRCM_ACK_MB1
- PRCM_ACK_MB1_APE_VOLTAGE_STATUS
- PRCM_ACK_MB1_CURRENT_APE_OPP
- PRCM_ACK_MB1_CURRENT_ARM_OPP
- PRCM_ACK_MB1_DVFS_STATUS
- PRCM_ACK_MB2
- PRCM_ACK_MB2_DPS_STATUS
- PRCM_ACK_MB3
- PRCM_ACK_MB4
- PRCM_ACK_MB5
- PRCM_ACK_MB5_I2C_STATUS
- PRCM_ACK_MB5_I2C_VAL
- PRCM_ACLK_MGT
- PRCM_APEATCLK_MGT
- PRCM_APETRACECLK_MGT
- PRCM_APE_RESETN_CLR
- PRCM_APE_RESETN_DSIPLL_RESETN
- PRCM_APE_RESETN_SET
- PRCM_APE_SOFTRST
- PRCM_ARMCLKFIX_MGT
- PRCM_ARMITMSK127TO96
- PRCM_ARMITMSK31TO0
- PRCM_ARMITMSK63TO32
- PRCM_ARMITMSK95TO64
- PRCM_ARMITVAL127TO96
- PRCM_ARMITVAL31TO0
- PRCM_ARMITVAL63TO32
- PRCM_ARMITVAL95TO64
- PRCM_ARMIT_MASKXP70_IT
- PRCM_ARM_CHGCLKREQ
- PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ
- PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL
- PRCM_ARM_IT1_CLR
- PRCM_ARM_IT1_VAL
- PRCM_ARM_LS_CLAMP
- PRCM_ARM_PLLDIVPS
- PRCM_ARM_PLLDIVPS_ARM_BRM_RATE
- PRCM_ARM_PLLDIVPS_MAX_MASK
- PRCM_ARM_WFI_STANDBY
- PRCM_ARM_WFI_STANDBY_WFI0
- PRCM_ARM_WFI_STANDBY_WFI1
- PRCM_AVS_BASE
- PRCM_AVS_ISMODEENABLE
- PRCM_AVS_ISMODEENABLE_MASK
- PRCM_AVS_ISSLOWSTARTUP
- PRCM_AVS_ISSLOWSTARTUP_MASK
- PRCM_AVS_VAPE_100_OPP
- PRCM_AVS_VAPE_50_OPP
- PRCM_AVS_VARM_100_OPP
- PRCM_AVS_VARM_50_OPP
- PRCM_AVS_VARM_MAX_OPP
- PRCM_AVS_VARM_RET
- PRCM_AVS_VBB_100_OPP
- PRCM_AVS_VBB_50_OPP
- PRCM_AVS_VBB_MAX_OPP
- PRCM_AVS_VBB_RET
- PRCM_AVS_VMOD_100_OPP
- PRCM_AVS_VMOD_50_OPP
- PRCM_AVS_VOLTAGE
- PRCM_AVS_VOLTAGE_MASK
- PRCM_AVS_VSAFE
- PRCM_B2R2CLK_MGT
- PRCM_BMLCLK_MGT
- PRCM_BOOT_STATUS
- PRCM_CGATING_BYPASS
- PRCM_CGATING_BYPASS_ICN2
- PRCM_CLKOCR
- PRCM_CLKOCR_CLK1TYPE
- PRCM_CLKOCR_CLKODIV0_MASK
- PRCM_CLKOCR_CLKODIV0_SHIFT
- PRCM_CLKOCR_CLKODIV1_MASK
- PRCM_CLKOCR_CLKODIV1_SHIFT
- PRCM_CLKOCR_CLKOSEL0_MASK
- PRCM_CLKOCR_CLKOSEL0_SHIFT
- PRCM_CLKOCR_CLKOSEL1_MASK
- PRCM_CLKOCR_CLKOSEL1_SHIFT
- PRCM_CLKOCR_CLKOUT0_MASK
- PRCM_CLKOCR_CLKOUT0_REF_CLK
- PRCM_CLKOCR_CLKOUT1_MASK
- PRCM_CLKOCR_CLKOUT1_REF_CLK
- PRCM_CLK_MGT_CLK38
- PRCM_CLK_MGT_CLK38DIV
- PRCM_CLK_MGT_CLKEN
- PRCM_CLK_MGT_CLKPLLDIV_MASK
- PRCM_CLK_MGT_CLKPLLSW_DDR
- PRCM_CLK_MGT_CLKPLLSW_MASK
- PRCM_CLK_MGT_CLKPLLSW_SOC0
- PRCM_CLK_MGT_CLKPLLSW_SOC1
- PRCM_CM_EN_MUX_WLAN_FREF
- PRCM_CPU_PO_RST_CTRL
- PRCM_CPU_PO_RST_CTRL_CORE
- PRCM_CPU_PO_RST_CTRL_CORE_ALL
- PRCM_CPU_PWROFF_REG
- PRCM_CPU_PWR_CLAMP_REG
- PRCM_CPU_SOFT_ENTRY_REG
- PRCM_DDR_SUBSYS_APE_MINBW
- PRCM_DMACLK_MGT
- PRCM_DSIALTCLK_MGT
- PRCM_DSITVCLK_DIV
- PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK
- PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT
- PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN
- PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK
- PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT
- PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN
- PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK
- PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT
- PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN
- PRCM_DSI_PLLOUT_SEL
- PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK
- PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT
- PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK
- PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT
- PRCM_DSI_PLLOUT_SEL_OFF
- PRCM_DSI_PLLOUT_SEL_PHI
- PRCM_DSI_PLLOUT_SEL_PHI_2
- PRCM_DSI_PLLOUT_SEL_PHI_4
- PRCM_DSI_SW_RESET
- PRCM_DSI_SW_RESET_DSI0_SW_RESETN
- PRCM_DSI_SW_RESET_DSI1_SW_RESETN
- PRCM_DSI_SW_RESET_DSI2_SW_RESETN
- PRCM_EPOD_C_SET
- PRCM_FLAGS
- PRCM_GPIOCR
- PRCM_GPIOCR_ALTCX
- PRCM_GPIOCR_DBG_STM_MOD_CMD1
- PRCM_GPIOCR_DBG_UARTMOD_CMD0
- PRCM_GPIOCR_SPI2_SELECT
- PRCM_HDMICLK_MGT
- PRCM_HOLD_EVT
- PRCM_HOSTACCESS_REQ
- PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ
- PRCM_HOSTACCESS_REQ_WAKE_REQ
- PRCM_HSIRXCLK_MGT
- PRCM_HSITXCLK_MGT
- PRCM_I2CCLK_MGT
- PRCM_IDX_GPIOCR1
- PRCM_IDX_GPIOCR2
- PRCM_IDX_GPIOCR3
- PRCM_IDX_GPIOCR_ALTC1
- PRCM_IDX_GPIOCR_ALTC2
- PRCM_IDX_GPIOCR_ALTC3
- PRCM_IDX_GPIOCR_ALTC4
- PRCM_IDX_GPIOCR_ALTC_MAX
- PRCM_IOCR
- PRCM_IOCR_IOFORCE
- PRCM_IPI2CCLK_MGT
- PRCM_ITCLEAR5
- PRCM_ITSTATUS0
- PRCM_ITSTATUS1
- PRCM_ITSTATUS2
- PRCM_ITSTATUS3
- PRCM_ITSTATUS4
- PRCM_ITSTATUS5
- PRCM_LCDCLK_MGT
- PRCM_MBOX_CPU_CLR
- PRCM_MBOX_CPU_SET
- PRCM_MBOX_CPU_VAL
- PRCM_MBOX_HEADER_ACK_MB0
- PRCM_MBOX_HEADER_REQ_MB0
- PRCM_MBOX_HEADER_REQ_MB1
- PRCM_MBOX_HEADER_REQ_MB2
- PRCM_MBOX_HEADER_REQ_MB3
- PRCM_MBOX_HEADER_REQ_MB4
- PRCM_MBOX_HEADER_REQ_MB5
- PRCM_MCDECLK_MGT
- PRCM_MMIP_LS_CLAMP_CLR
- PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP
- PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI
- PRCM_MMIP_LS_CLAMP_SET
- PRCM_MOD_AWAKE_STATUS
- PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE
- PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE
- PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO
- PRCM_MSP02CLK_MGT
- PRCM_MSP1CLK_MGT
- PRCM_PER1CLK_MGT
- PRCM_PER2CLK_MGT
- PRCM_PER3CLK_MGT
- PRCM_PER5CLK_MGT
- PRCM_PER6CLK_MGT
- PRCM_PER7CLK_MGT
- PRCM_PLLARM_ENABLE
- PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON
- PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE
- PRCM_PLLARM_FREQ
- PRCM_PLLARM_LOCKP
- PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3
- PRCM_PLLDDR_FREQ
- PRCM_PLLDSI_ENABLE
- PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE
- PRCM_PLLDSI_FREQ
- PRCM_PLLDSI_LOCKP
- PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10
- PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3
- PRCM_PLLSOC0_FREQ
- PRCM_PLLSOC1_FREQ
- PRCM_PLL_FREQ_DIV2EN
- PRCM_PLL_FREQ_D_MASK
- PRCM_PLL_FREQ_D_SHIFT
- PRCM_PLL_FREQ_N_MASK
- PRCM_PLL_FREQ_N_SHIFT
- PRCM_PLL_FREQ_R_MASK
- PRCM_PLL_FREQ_R_SHIFT
- PRCM_PLL_FREQ_SELDIV2
- PRCM_POWER_STATE_SET
- PRCM_POWER_STATE_VAL
- PRCM_PWROFF_GATING_REG
- PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I
- PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I
- PRCM_PWROFF_GATING_REG_CORE
- PRCM_PWR_SWITCH_REG
- PRCM_REQ_MB0
- PRCM_REQ_MB0_AP_PLL_STATE
- PRCM_REQ_MB0_AP_POWER_STATE
- PRCM_REQ_MB0_DO_NOT_WFI
- PRCM_REQ_MB0_ULP_CLOCK_STATE
- PRCM_REQ_MB0_WAKEUP_4500
- PRCM_REQ_MB0_WAKEUP_8500
- PRCM_REQ_MB1
- PRCM_REQ_MB1_APE_OPP
- PRCM_REQ_MB1_ARM_OPP
- PRCM_REQ_MB1_PLL_ON_OFF
- PRCM_REQ_MB2
- PRCM_REQ_MB2_AUTO_PM_IDLE
- PRCM_REQ_MB2_AUTO_PM_SLEEP
- PRCM_REQ_MB2_B2R2_MCDE
- PRCM_REQ_MB2_ESRAM12
- PRCM_REQ_MB2_ESRAM34
- PRCM_REQ_MB2_SGA
- PRCM_REQ_MB2_SIA_MMDSP
- PRCM_REQ_MB2_SIA_PIPE
- PRCM_REQ_MB2_SVA_MMDSP
- PRCM_REQ_MB2_SVA_PIPE
- PRCM_REQ_MB3
- PRCM_REQ_MB3_ANC_FIR_COEFF
- PRCM_REQ_MB3_ANC_IIR_COEFF
- PRCM_REQ_MB3_ANC_SHIFTER
- PRCM_REQ_MB3_ANC_WARP
- PRCM_REQ_MB3_SIDETONE_FIR_COEFF
- PRCM_REQ_MB3_SIDETONE_FIR_GAIN
- PRCM_REQ_MB3_SYSCLK_MGT
- PRCM_REQ_MB4
- PRCM_REQ_MB4_A9WDOG_0
- PRCM_REQ_MB4_A9WDOG_1
- PRCM_REQ_MB4_A9WDOG_2
- PRCM_REQ_MB4_A9WDOG_3
- PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE
- PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE
- PRCM_REQ_MB4_ESRAM0_ST
- PRCM_REQ_MB4_HOTDOG_THRESHOLD
- PRCM_REQ_MB4_HOTMON_CONFIG
- PRCM_REQ_MB4_HOTMON_HIGH
- PRCM_REQ_MB4_HOTMON_LOW
- PRCM_REQ_MB4_HOT_PERIOD
- PRCM_REQ_MB5
- PRCM_REQ_MB5_I2C_HW_BITS
- PRCM_REQ_MB5_I2C_REG
- PRCM_REQ_MB5_I2C_SLAVE_OP
- PRCM_REQ_MB5_I2C_VAL
- PRCM_RESOUTN_CLR
- PRCM_RESOUTN_SET
- PRCM_RNGCLK_MGT
- PRCM_ROMCODE_A2P
- PRCM_ROMCODE_P2A
- PRCM_SDMMCCLK_MGT
- PRCM_SEM
- PRCM_SEM_PRCM_SEM
- PRCM_SGACLK_MGT
- PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN
- PRCM_SIAMMDSPCLK_MGT
- PRCM_SLIMCLK_MGT
- PRCM_SRAM_A9
- PRCM_SRAM_LS_SLEEP
- PRCM_SSPCLK_MGT
- PRCM_SVAMMCSPCLK_MGT
- PRCM_SW_RST_REASON
- PRCM_TCR
- PRCM_TCR_DOZE_MODE
- PRCM_TCR_STOP_TIMERS
- PRCM_TCR_TENSEL_MASK
- PRCM_TVCLK_MGT
- PRCM_UARTCLK_MGT
- PRCM_UICCCLK_MGT
- PRCM_UNIPROCLK_MGT
- PRCM_XP70_CUR_PWR_STATE
- PRC_ALARM_ACTION_RR_R0_STOP
- PRC_ALARM_ACTION_RR_R1_STOP
- PRC_ALARM_ACTION_RR_R2_STOP
- PRC_ALARM_ACTION_RR_R3_STOP
- PRC_ALARM_ACTION_RR_R4_STOP
- PRC_ALARM_ACTION_RR_R5_STOP
- PRC_ALARM_ACTION_RR_R6_STOP
- PRC_ALARM_ACTION_RR_R7_STOP
- PRC_ALARM_ACTION_RW_R0_STOP
- PRC_ALARM_ACTION_RW_R1_STOP
- PRC_ALARM_ACTION_RW_R2_STOP
- PRC_ALARM_ACTION_RW_R3_STOP
- PRC_ALARM_ACTION_RW_R4_STOP
- PRC_ALARM_ACTION_RW_R5_STOP
- PRC_ALARM_ACTION_RW_R6_STOP
- PRC_ALARM_ACTION_RW_R7_STOP
- PRC_CTRL_BIMODAL_INTERRUPT
- PRC_CTRL_GROUP_READS
- PRC_CTRL_NO_SNOOP
- PRC_CTRL_NO_SNOOP_BUFF
- PRC_CTRL_NO_SNOOP_DESC
- PRC_CTRL_RC_ENABLED
- PRC_CTRL_RING_MODE
- PRC_CTRL_RING_MODE_1
- PRC_CTRL_RING_MODE_3
- PRC_CTRL_RING_MODE_5
- PRC_CTRL_RING_MODE_x
- PRC_CTRL_RXD_BACKOFF_INTERVAL
- PRC_FILL_ERR
- PRC_FORCE
- PRC_OK
- PRC_PBC
- PRC_PCI_AB_F_WR_Rn
- PRC_PCI_AB_RD_Rn
- PRC_PCI_AB_WR_Rn
- PRC_PCI_DP_F_WR_Rn
- PRC_PCI_DP_RD_Rn
- PRC_PCI_DP_WR_Rn
- PRC_SC_DISABLE
- PRC_STATUS_ERR
- PRC_THRESHOLD
- PRD12
- PRD34
- PRDCT_ID_LEN
- PRDCT_REV_LEN
- PRDT_DATA_BYTE_COUNT_MAX
- PRDT_DATA_BYTE_COUNT_PAD
- PRD_BYTES
- PRD_CDB
- PRD_CHAIN
- PRD_CHAINED_ENTRY
- PRD_CTL_DMAEN
- PRD_CTL_START
- PRD_CTL_WR
- PRD_DATA
- PRD_DIRECT_INTR
- PRD_DMA
- PRD_DRAIN
- PRD_END
- PRD_ENTRIES
- PRD_EOP
- PRD_EOT
- PRD_IBIAS_CLK_SHIFT
- PRD_IBIAS_D0_SHIFT
- PRD_IBIAS_D1_SHIFT
- PRD_IBIAS_D2_SHIFT
- PRD_INT_SEL
- PRD_INT_SEL_F0
- PRD_INT_SEL_F1
- PRD_INT_SEL_F2
- PRD_INT_SEL_F3
- PRD_INT_SEL_PBSR
- PRD_INT_SEL_SRAM
- PRD_IOM
- PRD_JMP
- PRD_LEN_LIMIT
- PRD_LEN_MAX
- PRD_NXT_PRD_CNT
- PRD_REQ_MASK
- PRD_REQ_SIZE
- PRD_SIZE_MAX
- PRD_WRITE
- PRE
- PREA
- PREAD
- PREALLOCATED_PMDS
- PREALLOCATED_USER_PMDS
- PREALLOCATION_SIZE
- PREALLOC_BUFFER
- PREALLOC_BUFFER_MAX
- PREALLOC_DMA_DEBUG_ENTRIES
- PREALLOC_INSTR
- PREALLOC_NID
- PREALLOC_TB_SIZE
- PREAMBLE
- PREAMBLE_AUTO
- PREAMBLE_EN
- PREAMBLE_LEN
- PREAMBLE_LONG
- PREAMBLE_SHORT
- PREAMBLE_TYPE_AUTO
- PREAMBLE_TYPE_LONG
- PREAMBLE_TYPE_SHORT
- PREBOOT
- PREC
- PRECALC
- PRECALC_00_15
- PRECALC_16_31
- PRECALC_32_79
- PRECALC_BUF
- PRECALC_RESET_WY
- PRECALC_ROTATE_WY
- PRECALC_WK
- PRECHARGE_THRESHOLD
- PRECISION
- PRECISION_LOST_DOWN
- PRECISION_LOST_UP
- PRECISION_MAX
- PRECOMPUTE
- PRECOMPUTE_AVX
- PRECOMPUTE_AVX2
- PREC_PALETTE
- PREC_PAL_DATA
- PREC_PAL_EXT2_GC_MAX
- PREC_PAL_EXT_GC_MAX
- PREC_PAL_GC_MAX
- PREC_PAL_INDEX
- PREC_PAL_MULTI_SEG_DATA
- PREC_PAL_MULTI_SEG_INDEX
- PREC_PIPEGCMAX
- PREDEFINED_APP_IDX_MAX
- PREDICATE_ALWAYS
- PREDICATE_BIT
- PREDICTION_BUFFER_SIZE
- PREDICTION_FACTOR
- PREDICTION_MAX
- PREDICTION_PERIOD_MAX
- PREDICTION_PERIOD_MIN
- PREDIV
- PREDIV2
- PREDIV_MASK
- PREDIV_SHIFT
- PRED_CMD_IBPB
- PRED_FUNC_MAX
- PRED_FUNC_START
- PRED_KERNEL_STACK
- PRED_LEAVE_SYSCALL
- PRED_NON_SYSCALL
- PRED_SYSCALL
- PRED_USER_STACK
- PREEMPHASIS_DISABLED
- PREEMPHASIS_EN_MASK
- PREEMPHASIS_EN_SHIFT
- PREEMPHASIS_EU
- PREEMPHASIS_USA
- PREEMPH_GEN1
- PREEMPH_GEN1_SHIFT
- PREEMPH_GEN2
- PREEMPH_GEN2_SHIFT
- PREEMPH_GEN3
- PREEMPH_GEN3_SHIFT
- PREEMPH_MASK
- PREEMPH_WIDTH_HALF_BIT
- PREEMPT
- PREEMPT_ABORT
- PREEMPT_AND_ABORT
- PREEMPT_BITS
- PREEMPT_DISABLED
- PREEMPT_DISABLE_OFFSET
- PREEMPT_ENABLED
- PREEMPT_FAULTED
- PREEMPT_H
- PREEMPT_LOCK_OFFSET
- PREEMPT_MASK
- PREEMPT_NEED_RESCHED
- PREEMPT_NONE
- PREEMPT_OFFSET
- PREEMPT_PENDING
- PREEMPT_QUEUES
- PREEMPT_QUEUES_NO_UNMAP
- PREEMPT_SHIFT
- PREEMPT_START
- PREEMPT_TIME
- PREEMPT_TRIGGERED
- PREF
- PREFD
- PREFDROPINT_F
- PREFDROPINT_S
- PREFDROPINT_V
- PREFERRED_BPP
- PREFERRED_BSSID
- PREFERRED_MODE
- PREFETCH
- PREFETCHW_INSTR
- PREFETCH_BITS
- PREFETCH_BUF_EN
- PREFETCH_CONFIG1_CS_SHIFT
- PREFETCH_DIST
- PREFETCH_ENB
- PREFETCH_FIFOTHRESHOLD
- PREFETCH_FIFOTHRESHOLD_MAX
- PREFETCH_FLUSH
- PREFETCH_FLUSH_CNT
- PREFETCH_HINT_SHFT
- PREFETCH_LINES
- PREFETCH_MODE
- PREFETCH_MODE__PREFETCH_BURST_LENGTH
- PREFETCH_MODE__PREFETCH_EN
- PREFETCH_SENTINEL
- PREFETCH_SIZE
- PREFETCH_STATUS_COUNT
- PREFETCH_STATUS_FIFO_CNT
- PREFETCH_STRIDE
- PREFI
- PREFIRM
- PREFIX
- PREFIXES_MAP
- PREFIX_ADDRESS
- PREFIX_BLK
- PREFIX_CACHEINFO
- PREFIX_CS
- PREFIX_CS_
- PREFIX_DEFAULT
- PREFIX_DELTA
- PREFIX_DS
- PREFIX_DS_
- PREFIX_ES
- PREFIX_ES_
- PREFIX_FASTWR
- PREFIX_FS
- PREFIX_FS_
- PREFIX_GS
- PREFIX_GS_
- PREFIX_IO16
- PREFIX_LEN
- PREFIX_LENGTH
- PREFIX_LOCK
- PREFIX_MAX
- PREFIX_REPE
- PREFIX_REPNE
- PREFIX_SIZE
- PREFIX_SS
- PREFIX_SS_
- PREFIX_UNSPEC
- PREFS
- PREFTREE_INIT
- PREF_AHEAD
- PREF_APPROVAL
- PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
- PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK
- PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
- PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
- PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK
- PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK
- PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
- PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
- PREF_BASE_UPPER__PREF_BASE_UPPER__MASK
- PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
- PREF_DISAPPROVAL
- PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
- PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK
- PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
- PREF_SIZE
- PREF_TAG
- PREF_TYPE
- PREF_UNIT_ADDR_HI
- PREF_UNIT_ADDR_LO
- PREF_UNIT_CTRL
- PREF_UNIT_FIFO_LEV
- PREF_UNIT_FIFO_RP
- PREF_UNIT_FIFO_WM
- PREF_UNIT_FIFO_WP
- PREF_UNIT_GET_IDX
- PREF_UNIT_LAST_IDX
- PREF_UNIT_MASK_IDX
- PREF_UNIT_OP_OFF
- PREF_UNIT_OP_ON
- PREF_UNIT_PUT_IDX
- PREF_UNIT_RST_CLR
- PREF_UNIT_RST_SET
- PREG
- PREG17_DUPLEX
- PREG17_LNKUP
- PREG17_MDI
- PREG17_SPDRSV
- PREG17_SPEED
- PREG17_SPEED_1000M
- PREG17_SPEED_100M
- PREG17_SPEED_10M
- PREGISTER
- PREGS
- PREG_AUX_BUS_WPROT_0
- PREG_PRPH_WPROT_22000
- PREG_PRPH_WPROT_9000
- PREG_WFPM_ACCESS
- PREHDR_ABS
- PREHDR_RSLS_SHIFT
- PREINDEXED
- PREINIT_DELAY
- PRELOAD_REQ
- PREMPH_SET
- PREMULT2
- PREN_MM_EXT
- PREN_PREAMBLE
- PREN_PREAMBLE_EXT
- PREOFF_YUV_TO_RGB_HI
- PREOFF_YUV_TO_RGB_LO
- PREOFF_YUV_TO_RGB_ME
- PREOP_OPTYPE
- PREP
- PREPARE
- PREPARE_CNT_MAX
- PREPARE_COUNT_MASK
- PREPARE_COUNT_SHIFT
- PREPARE_FOR_SUSPEND
- PREPARE_HAL_BUF
- PREPARE_HAL_PTT_MSG_BUF
- PREPOST_REG
- PREP_FOR_SUSPEND_ABORTED
- PREP_FOR_SUSPEND_ENABLED
- PREP_FOR_SUSPEND_FLAGS
- PREP_FOR_SUSPEND_OVERWRITE
- PREP_FOR_SUSPEND_PENDING
- PREP_IE_FLAGS
- PREP_IE_HOPCOUNT
- PREP_IE_LIFETIME
- PREP_IE_METRIC
- PREP_IE_ORIG_ADDR
- PREP_IE_ORIG_SN
- PREP_IE_TARGET_ADDR
- PREP_IE_TARGET_SN
- PREP_IE_TTL
- PREP_PKT_POINTERS
- PREP_RD_SS_DATA
- PREQDIS
- PREQ_IE_FLAGS
- PREQ_IE_HOPCOUNT
- PREQ_IE_LIFETIME
- PREQ_IE_METRIC
- PREQ_IE_ORIG_ADDR
- PREQ_IE_ORIG_SN
- PREQ_IE_PREQ_ID
- PREQ_IE_TARGET_ADDR
- PREQ_IE_TARGET_F
- PREQ_IE_TARGET_SN
- PREQ_IE_TTL
- PREQ_Q_F_REFRESH
- PREQ_Q_F_START
- PRER
- PREREG1_1350MA
- PREREG1_180MA
- PREREG1_450MA
- PREREG1_540MA
- PREREG1_90MA
- PREREG1_VSYS_4_5V
- PRERELEASE
- PREREQ
- PRESCALE
- PRESCALED_TIMER_BASE
- PRESCALER_12
- PRESCALER_17
- PRESCALER_21
- PRESCALE_512
- PRESCALE_CONTROL__PRESCALE_MODE_MASK
- PRESCALE_CONTROL__PRESCALE_MODE__SHIFT
- PRESCALE_EXPONENT
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK
- PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT
- PRESCALE_MASK
- PRESCALE_MAX
- PRESCALE_MIN
- PRESCALE_MODE_BYPASS
- PRESCALE_MODE_PROGRAM
- PRESCALE_MODE_UNITY
- PRESCALE_OFFSET
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK
- PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT
- PRESCALE_SHIFT
- PRESCALE_VALUES_B__PRESCALE_BIAS_B_MASK
- PRESCALE_VALUES_B__PRESCALE_BIAS_B__SHIFT
- PRESCALE_VALUES_B__PRESCALE_SCALE_B_MASK
- PRESCALE_VALUES_B__PRESCALE_SCALE_B__SHIFT
- PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK
- PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT
- PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK
- PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT
- PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK
- PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT
- PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK
- PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT
- PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK
- PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT
- PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK
- PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT
- PRESCALE_VALUES_G__PRESCALE_BIAS_G_MASK
- PRESCALE_VALUES_G__PRESCALE_BIAS_G__SHIFT
- PRESCALE_VALUES_G__PRESCALE_SCALE_G_MASK
- PRESCALE_VALUES_G__PRESCALE_SCALE_G__SHIFT
- PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK
- PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT
- PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK
- PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT
- PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK
- PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT
- PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK
- PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT
- PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK
- PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT
- PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK
- PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT
- PRESCALE_VALUES_R__PRESCALE_BIAS_R_MASK
- PRESCALE_VALUES_R__PRESCALE_BIAS_R__SHIFT
- PRESCALE_VALUES_R__PRESCALE_SCALE_R_MASK
- PRESCALE_VALUES_R__PRESCALE_SCALE_R__SHIFT
- PRESCL_CTRL0
- PRESCL_CTRL0_I2C
- PRESCL_CTRL0_I3C
- PRESCL_CTRL0_MAX
- PRESCL_CTRL1
- PRESCL_CTRL1_OD_LOW
- PRESCL_CTRL1_OD_LOW_MASK
- PRESCL_CTRL1_PP_LOW
- PRESCL_CTRL1_PP_LOW_MASK
- PRESENT
- PRESENT_BIT
- PRESENT_COPY
- PRESENT_EXT_STATUS
- PRESENT_IOBASE_0
- PRESENT_IOBASE_1
- PRESENT_IOBASE_2
- PRESENT_IOBASE_3
- PRESENT_IOSIZE
- PRESENT_OPTION
- PRESENT_PIN_REPLACE
- PRESENT_STATE
- PRESENT_STATUS
- PRESERVE_DDB_LIST
- PRESERVE_FLAG_FIELDS
- PRESETOUT_MARK
- PRESET_AGC_FORMATTER
- PRESET_CONTOUR_FORMATTER
- PRESET_DICT
- PRESET_MANUAL_BLUE_GAIN_FORMATTER
- PRESET_MANUAL_RED_GAIN_FORMATTER
- PRESET_SHUTTER_FORMATTER
- PRESET_TIMEOUT_VALUE
- PRESET_TIMEOUT_VALUE_MASK
- PRESET_TIMEOUT_VALUE_SHIFT
- PRESL
- PRESPONSE_TIMEOUT_VALUE
- PRESPONSE_TIMEOUT_VALUE_MASK
- PRESPONSE_TIMEOUT_VALUE_SHIFT
- PRESSED
- PRESSURE_MAX
- PRESSURE_MIN
- PRESSURE_OFFSET
- PRESS_MASK
- PRESUSPEND
- PRESUSPEND_UNDO
- PRES_STATUS_BAT_PRES
- PRETIMEOUT_SEC
- PREV
- PREVENT_TRANSMIT_BIT_STUFF
- PREVIEW_INPUT_CCDC
- PREVIEW_INPUT_MEMORY
- PREVIEW_INPUT_NONE
- PREVIEW_LAYER
- PREVIEW_OUTPUT_MEMORY
- PREVIEW_OUTPUT_RESIZER
- PREVRXD
- PREVSTATE
- PREVTXD
- PREV_MARGIN_BOTTOM
- PREV_MARGIN_LEFT
- PREV_MARGIN_RIGHT
- PREV_MARGIN_TOP
- PREV_MAX_IN_HEIGHT
- PREV_MAX_OUT_WIDTH_REV_1
- PREV_MAX_OUT_WIDTH_REV_15
- PREV_MAX_OUT_WIDTH_REV_2
- PREV_MIN_IN_HEIGHT
- PREV_MIN_IN_WIDTH
- PREV_MIN_OUT_HEIGHT
- PREV_MIN_OUT_WIDTH
- PREV_PADS_NUM
- PREV_PAD_SINK
- PREV_PAD_SOURCE
- PREV_PARENT
- PREV_PRINT_REGISTER
- PREV_REQ_PTR
- PREV_RES_PTR
- PREV_RX
- PREV_TX
- PREZ_MUST_WAIT_FOR_POSTZ_DONE
- PRE_BNEZAD
- PRE_BYPASS
- PRE_CHANGE
- PRE_CLAMP_TF0
- PRE_CLAMP_TF1
- PRE_CMD_DELAY
- PRE_COMMIT
- PRE_CSC_GAMC_AUTO_INCREMENT
- PRE_CSC_GAMC_DATA
- PRE_CSC_GAMC_INDEX
- PRE_CSC_GAMMA_ENABLE
- PRE_DELAY
- PRE_EMPHASIS_DISABLED
- PRE_EMPHASIS_LEVEL1
- PRE_EMPHASIS_LEVEL2
- PRE_EMPHASIS_LEVEL3
- PRE_EMPHASIS_LEVEL_0
- PRE_EMPHASIS_LEVEL_1
- PRE_EMPHASIS_LEVEL_2
- PRE_EMPHASIS_LEVEL_3
- PRE_EMPHASIS_MAX_LEVEL
- PRE_EMPHASIS_SET_MASK
- PRE_EMPHASIS_SET_SHIFT
- PRE_EX
- PRE_FETCH
- PRE_MAPPED
- PRE_MEA_EN
- PRE_MEA_THRE_CNT
- PRE_MEM_BASE
- PRE_MEM_LENGTH
- PRE_PLL
- PRE_PLL_CLK_DIV
- PRE_RATE_CHANGE
- PRE_SLEEP_SEQUENCE
- PRE_START
- PRE_TBTT_USEC
- PRE_TEST_MODE
- PRE_TEST_VALUE
- PRE_WIN8_STORVSC_SENSE_BUFFER_SIZE
- PRF2PRI
- PRFVIT
- PRF_FRZ
- PRGMCNT
- PRGMRST
- PRGM_MODEL_REV_LEVEL
- PRG_BUFFER_OFS
- PRG_CL_RESET_VALID
- PRG_DONE
- PRG_ETH0
- PRG_ETH0_CLK_M250_DIV_SHIFT
- PRG_ETH0_CLK_M250_DIV_WIDTH
- PRG_ETH0_CLK_M250_SEL_MASK
- PRG_ETH0_CLK_M250_SEL_SHIFT
- PRG_ETH0_EXT_PHY_MODE_MASK
- PRG_ETH0_EXT_RGMII_MODE
- PRG_ETH0_EXT_RMII_MODE
- PRG_ETH0_INVERTED_RMII_CLK
- PRG_ETH0_RGMII_MODE
- PRG_ETH0_RGMII_TX_CLK_EN
- PRG_ETH0_TXDLY_MASK
- PRG_ETH0_TXDLY_SHIFT
- PRG_ETH0_TX_AND_PHY_REF_CLK
- PRI
- PRID_COMP_ALCHEMY
- PRID_COMP_BROADCOM
- PRID_COMP_CAVIUM
- PRID_COMP_INGENIC_D0
- PRID_COMP_INGENIC_D1
- PRID_COMP_INGENIC_E1
- PRID_COMP_LEGACY
- PRID_COMP_LEXRA
- PRID_COMP_LOONGSON
- PRID_COMP_LSI
- PRID_COMP_MASK
- PRID_COMP_MIPS
- PRID_COMP_NETLOGIC
- PRID_COMP_NXP
- PRID_COMP_SANDCRAFT
- PRID_COMP_SIBYTE
- PRID_COMP_TOSHIBA
- PRID_IMP_1004K
- PRID_IMP_1074K
- PRID_IMP_20KC
- PRID_IMP_24K
- PRID_IMP_24KE
- PRID_IMP_25KF
- PRID_IMP_34K
- PRID_IMP_4KC
- PRID_IMP_4KEC
- PRID_IMP_4KECR2
- PRID_IMP_4KEMPR2
- PRID_IMP_4KSC
- PRID_IMP_4KSD
- PRID_IMP_5KC
- PRID_IMP_5KE
- PRID_IMP_74K
- PRID_IMP_AU1_REV1
- PRID_IMP_AU1_REV2
- PRID_IMP_BMIPS32_REV4
- PRID_IMP_BMIPS32_REV8
- PRID_IMP_BMIPS3300
- PRID_IMP_BMIPS3300_ALT
- PRID_IMP_BMIPS3300_BUG
- PRID_IMP_BMIPS43XX
- PRID_IMP_BMIPS5000
- PRID_IMP_BMIPS5200
- PRID_IMP_CAVIUM_CN30XX
- PRID_IMP_CAVIUM_CN31XX
- PRID_IMP_CAVIUM_CN38XX
- PRID_IMP_CAVIUM_CN50XX
- PRID_IMP_CAVIUM_CN52XX
- PRID_IMP_CAVIUM_CN56XX
- PRID_IMP_CAVIUM_CN58XX
- PRID_IMP_CAVIUM_CN61XX
- PRID_IMP_CAVIUM_CN63XX
- PRID_IMP_CAVIUM_CN66XX
- PRID_IMP_CAVIUM_CN68XX
- PRID_IMP_CAVIUM_CN70XX
- PRID_IMP_CAVIUM_CN73XX
- PRID_IMP_CAVIUM_CN78XX
- PRID_IMP_CAVIUM_CNF71XX
- PRID_IMP_CAVIUM_CNF75XX
- PRID_IMP_I6400
- PRID_IMP_I6500
- PRID_IMP_INTERAPTIV_MP
- PRID_IMP_INTERAPTIV_UP
- PRID_IMP_LOONGSON_32
- PRID_IMP_LOONGSON_64
- PRID_IMP_M14KC
- PRID_IMP_M14KEC
- PRID_IMP_M5150
- PRID_IMP_M6250
- PRID_IMP_MAGIC
- PRID_IMP_MASK
- PRID_IMP_NETLOGIC_AU13XX
- PRID_IMP_NETLOGIC_XLP2XX
- PRID_IMP_NETLOGIC_XLP3XX
- PRID_IMP_NETLOGIC_XLP5XX
- PRID_IMP_NETLOGIC_XLP8XX
- PRID_IMP_NETLOGIC_XLP9XX
- PRID_IMP_NETLOGIC_XLR308
- PRID_IMP_NETLOGIC_XLR308C
- PRID_IMP_NETLOGIC_XLR508C
- PRID_IMP_NETLOGIC_XLR516C
- PRID_IMP_NETLOGIC_XLR532
- PRID_IMP_NETLOGIC_XLR532C
- PRID_IMP_NETLOGIC_XLR716
- PRID_IMP_NETLOGIC_XLR732
- PRID_IMP_NETLOGIC_XLS104
- PRID_IMP_NETLOGIC_XLS108
- PRID_IMP_NETLOGIC_XLS204
- PRID_IMP_NETLOGIC_XLS208
- PRID_IMP_NETLOGIC_XLS404
- PRID_IMP_NETLOGIC_XLS404B
- PRID_IMP_NETLOGIC_XLS408
- PRID_IMP_NETLOGIC_XLS408B
- PRID_IMP_NETLOGIC_XLS412B
- PRID_IMP_NETLOGIC_XLS416B
- PRID_IMP_NETLOGIC_XLS608
- PRID_IMP_NETLOGIC_XLS608B
- PRID_IMP_NETLOGIC_XLS616B
- PRID_IMP_NEVADA
- PRID_IMP_P5600
- PRID_IMP_P6600
- PRID_IMP_PR4450
- PRID_IMP_PROAPTIV_MP
- PRID_IMP_PROAPTIV_UP
- PRID_IMP_QEMU_GENERIC
- PRID_IMP_R10000
- PRID_IMP_R12000
- PRID_IMP_R14000
- PRID_IMP_R2000
- PRID_IMP_R3000
- PRID_IMP_R4000
- PRID_IMP_R4300
- PRID_IMP_R4600
- PRID_IMP_R4640
- PRID_IMP_R4650
- PRID_IMP_R4700
- PRID_IMP_R5000
- PRID_IMP_R5432
- PRID_IMP_R5500
- PRID_IMP_R6000
- PRID_IMP_R6000A
- PRID_IMP_R8000
- PRID_IMP_RM7000
- PRID_IMP_RM9000
- PRID_IMP_SB1
- PRID_IMP_SB1A
- PRID_IMP_SONIC
- PRID_IMP_SR71000
- PRID_IMP_TX39
- PRID_IMP_TX49
- PRID_IMP_UNKNOWN
- PRID_IMP_VR41XX
- PRID_IMP_XBURST
- PRID_OPT_MASK
- PRID_REV_34K_V1_0_2
- PRID_REV_BMIPS4380_HI
- PRID_REV_BMIPS4380_LO
- PRID_REV_ENCODE_332
- PRID_REV_ENCODE_44
- PRID_REV_LOONGSON1B
- PRID_REV_LOONGSON1C
- PRID_REV_LOONGSON2E
- PRID_REV_LOONGSON2F
- PRID_REV_LOONGSON3A_R1
- PRID_REV_LOONGSON3A_R2_0
- PRID_REV_LOONGSON3A_R2_1
- PRID_REV_LOONGSON3A_R3_0
- PRID_REV_LOONGSON3A_R3_1
- PRID_REV_LOONGSON3B_R1
- PRID_REV_LOONGSON3B_R2
- PRID_REV_MASK
- PRID_REV_R2000A
- PRID_REV_R3000
- PRID_REV_R3000A
- PRID_REV_R4400
- PRID_REV_TX3912
- PRID_REV_TX3922
- PRID_REV_TX3927
- PRID_REV_TX4927
- PRID_REV_TX4937
- PRID_REV_VR4111
- PRID_REV_VR4121
- PRID_REV_VR4122
- PRID_REV_VR4130
- PRID_REV_VR4181
- PRID_REV_VR4181A
- PRID_VR4122_REV1_0
- PRID_VR4122_REV2_0
- PRID_VR4122_REV2_1
- PRID_VR4122_REV3_0
- PRID_VR4122_REV3_1
- PRID_VR4131_REV1_2
- PRID_VR4131_REV2_0
- PRID_VR4131_REV2_1
- PRID_VR4131_REV2_2
- PRID_VR4133
- PRID_VR4181A_REV1_0
- PRID_VR4181A_REV1_1
- PRIMA2_CLOCK_FREQ
- PRIMA2_CODEC_ENABLE_BITS
- PRIMA2_CODEC_RESET_BITS
- PRIMAD_CPUDV_MASK
- PRIMAD_EBCDV_MASK
- PRIMAD_OPBDV_MASK
- PRIMAD_PLBDV_MASK
- PRIMARI_ACB
- PRIMARY
- PRIMARYBUSMASK
- PRIMARY_ADAPTER
- PRIMARY_A_FLIP_DONE
- PRIMARY_BUS
- PRIMARY_B_FLIP_DONE
- PRIMARY_CLK_DETECT
- PRIMARY_CLOCK
- PRIMARY_CONNECTOR
- PRIMARY_CONTEXT
- PRIMARY_C_FLIP_DONE
- PRIMARY_DIC
- PRIMARY_EU
- PRIMARY_FAULT_REG_LEN
- PRIMARY_FORMAT_NUM
- PRIMARY_HWQ
- PRIMARY_MI2S_RX
- PRIMARY_MI2S_TX
- PRIMARY_MONITOR
- PRIMARY_PLANE
- PRIMARY_PLL
- PRIMARY_RING
- PRIMARY_ROUTER
- PRIMARY_TC
- PRIMARY_TDM_RX_0
- PRIMARY_TDM_RX_1
- PRIMARY_TDM_RX_2
- PRIMARY_TDM_RX_3
- PRIMARY_TDM_RX_4
- PRIMARY_TDM_RX_5
- PRIMARY_TDM_RX_6
- PRIMARY_TDM_RX_7
- PRIMARY_TDM_TX_0
- PRIMARY_TDM_TX_1
- PRIMARY_TDM_TX_2
- PRIMARY_TDM_TX_3
- PRIMARY_TDM_TX_4
- PRIMARY_TDM_TX_5
- PRIMARY_TDM_TX_6
- PRIMARY_TDM_TX_7
- PRIMARY_TIMEOUT
- PRIMARY_TS
- PRIMARY_VGA
- PRIMARY_WIN
- PRIMCNSTALPHA
- PRIME
- PRIME_CHNL_OFFSET_DONT_CARE
- PRIME_CHNL_OFFSET_LOWER
- PRIME_CHNL_OFFSET_UPPER
- PRIME_TIMEOUT
- PRIMITIVES_CASE
- PRIMITIVES_CASE_COMMON
- PRIMITIVES_DATA
- PRIMITIVES_ERR_CASE
- PRIMITIVE_INFO_INIT
- PRIMITIVE_RECVD
- PRIMITIVE_TYPE_LINES
- PRIMITIVE_TYPE_LINE_LOOP
- PRIMITIVE_TYPE_LINE_STRIP
- PRIMITIVE_TYPE_POINTS
- PRIMITIVE_TYPE_QUADS
- PRIMITIVE_TYPE_TRIANGLES
- PRIMITIVE_TYPE_TRIANGLE_FAN
- PRIMITIVE_TYPE_TRIANGLE_STRIP
- PRIMPOS
- PRIMQ
- PRIMSIZE
- PRIMUS
- PRIM_CONST_ALPHA_ENABLE
- PRIM_MODE
- PRIM_SEL_UP20
- PRING_HI_END
- PRING_HI_START
- PRING_LO_END
- PRING_LO_HI
- PRING_LO_HI_END
- PRING_LO_HI_START
- PRING_LO_START
- PRINT
- PRINTD
- PRINTDB
- PRINTDD
- PRINTDDB
- PRINTDDE
- PRINTDDM
- PRINTDE
- PRINTDM
- PRINTER_DEVTYPE
- PRINTER_MINORS
- PRINTER_NOT_ERROR
- PRINTER_PAPER_EMPTY
- PRINTER_PRODUCT_NUM
- PRINTER_SELECTED
- PRINTER_TYPE
- PRINTER_VENDOR_NUM
- PRINTF
- PRINTF_BUFFER_SIZE
- PRINTF_DFL
- PRINTK
- PRINTK2
- PRINTK3
- PRINTKE
- PRINTKI
- PRINTK_1
- PRINTK_2
- PRINTK_3
- PRINTK_4
- PRINTK_5
- PRINTK_6
- PRINTK_7
- PRINTK_8
- PRINTK_ERROR
- PRINTK_HEADER
- PRINTK_MAX_SINGLE_HEADER_LEN
- PRINTK_NMI_CONTEXT_MASK
- PRINTK_NMI_DIRECT_CONTEXT_MASK
- PRINTK_PENDING_OUTPUT
- PRINTK_PENDING_WAKEUP
- PRINTK_SAFE_CONTEXT_MASK
- PRINTR
- PRINTREGS
- PRINTSTR
- PRINT_ADAP_STATS
- PRINT_ADDR
- PRINT_ARGS
- PRINT_ATTRf
- PRINT_ATTRn
- PRINT_BUFF
- PRINT_BUFFER_SIZE
- PRINT_CCK_RATE
- PRINT_CH_STATS
- PRINT_CH_STATS2
- PRINT_CMDP_byte
- PRINT_CMDP_word
- PRINT_CREG_16bit
- PRINT_CREG_32bit
- PRINT_CREG_8bit
- PRINT_DEBUG
- PRINT_DIRECTORY_ITEMS
- PRINT_DIRECT_ITEMS
- PRINT_ERR
- PRINT_ERROR
- PRINT_FATAL
- PRINT_FIELD
- PRINT_FLAG
- PRINT_HT_CAP
- PRINT_INFO
- PRINT_LEAF_ITEMS
- PRINT_LMIP_byte
- PRINT_LMIP_dword
- PRINT_LMIP_qword
- PRINT_LMIP_word
- PRINT_LREG_16bit
- PRINT_LREG_32bit
- PRINT_LREG_8bit
- PRINT_MASKED_VAL
- PRINT_MASKED_VALP
- PRINT_MASKED_VAL_L2
- PRINT_MASKED_VAL_MISC
- PRINT_MESSAGES
- PRINT_MF_COUNT
- PRINT_MIS_byte
- PRINT_MIS_dword
- PRINT_MIS_qword
- PRINT_MIS_word
- PRINT_MREG_16bit
- PRINT_MREG_32bit
- PRINT_MREG_8bit
- PRINT_NSS_SUPP
- PRINT_OFDM_RATE
- PRINT_PKT
- PRINT_POS
- PRINT_RAW_ADDR
- PRINT_REG_16bit
- PRINT_REG_32bit
- PRINT_REG_8bit
- PRINT_RINGS
- PRINT_STATS_LE32
- PRINT_STAT_LE32
- PRINT_TID_STATS
- PRINT_TYPE_FMT_NAME
- PRINT_TYPE_FUNC_NAME
- PRINT_WARN
- PRIO
- PRIOMAP_MIN_SZ
- PRIOMASK
- PRIORITY_ALWAYS_ON
- PRIORITY_A_CNT
- PRIORITY_BASE
- PRIORITY_B_CNT
- PRIORITY_DEFAULT
- PRIORITY_HIGH
- PRIORITY_LEVEL
- PRIORITY_LOW
- PRIORITY_MARK_MASK
- PRIORITY_MASK
- PRIORITY_OFF
- PRIORITY_PER_ID
- PRIORITY_REASON_CMD_CRC_ERR
- PRIORITY_REASON_CMD_PARITY_ERR
- PRIORITY_REASON_DATA_OUT_CRC_ERR
- PRIORITY_REASON_DATA_OUT_PARITY_ERR
- PRIORITY_REASON_LQ_CRC_ERR
- PRIORITY_REASON_MSG_OUT_PARITY_ERR
- PRIORITY_REASON_NO_DISCONNECT
- PRIORITY_REASON_PROTOCOL_ERR
- PRIORITY_REASON_SCSI_TASK_MANAGEMENT
- PRIORITY_REASON_TARGET_BUSY
- PRIORITY_REASON_UNKNOWN
- PRIORITY_SCHEME_SELECT
- PRIORITY_SELECT_USB
- PRIORITY_SELECT_USB2
- PRIORITY_SELECT_USB3
- PRIO_8021D_BE
- PRIO_8021D_BK
- PRIO_8021D_CL
- PRIO_8021D_EE
- PRIO_8021D_NC
- PRIO_8021D_NONE
- PRIO_8021D_VI
- PRIO_8021D_VO
- PRIO_802_1P_ENTRIES
- PRIO_CTRL
- PRIO_DATA
- PRIO_LEVELS
- PRIO_MAP_0_LO
- PRIO_MAP_2_HI
- PRIO_MAP_3_HI
- PRIO_MAX
- PRIO_MIN
- PRIO_PGRP
- PRIO_PROCESS
- PRIO_QUEUES
- PRIO_SCHEME_SELECT_M
- PRIO_SCHEME_SELECT_S
- PRIO_SETUP
- PRIO_TO_NICE
- PRIO_USER
- PRIPTR
- PRIQ_0_PERM_EXEC
- PRIQ_0_PERM_PRIV
- PRIQ_0_PERM_READ
- PRIQ_0_PERM_WRITE
- PRIQ_0_PRG_LAST
- PRIQ_0_SID
- PRIQ_0_SSID
- PRIQ_0_SSID_V
- PRIQ_1_ADDR_MASK
- PRIQ_1_PRG_IDX
- PRIQ_ENT_DWORDS
- PRIQ_ENT_SZ_SHIFT
- PRIQ_MAX_SZ_SHIFT
- PRIQ_MSI_INDEX
- PRISM2_AUTH_OPEN
- PRISM2_AUTH_SHARED_KEY
- PRISM2_CALLBACK_DISABLE
- PRISM2_CALLBACK_ENABLE
- PRISM2_CALLBACK_RX_END
- PRISM2_CALLBACK_RX_START
- PRISM2_CALLBACK_TX_END
- PRISM2_CALLBACK_TX_START
- PRISM2_DATA_MAXLEN
- PRISM2_DOWNLOAD_NON_VOLATILE
- PRISM2_DOWNLOAD_SUPPORT
- PRISM2_DOWNLOAD_VOLATILE
- PRISM2_DOWNLOAD_VOLATILE_GENESIS
- PRISM2_DOWNLOAD_VOLATILE_GENESIS_PERSISTENT
- PRISM2_DOWNLOAD_VOLATILE_PERSISTENT
- PRISM2_DUMMY_FID
- PRISM2_DUMP_RX_HDR
- PRISM2_DUMP_TXEXC_HDR
- PRISM2_DUMP_TX_HDR
- PRISM2_FRAG_CACHE_LEN
- PRISM2_FW_VER
- PRISM2_GET_ENCRYPTION
- PRISM2_HOSTAPD_ADD_STA
- PRISM2_HOSTAPD_FLUSH
- PRISM2_HOSTAPD_GENERIC_ELEMENT_HDR_LEN
- PRISM2_HOSTAPD_GET_INFO_STA
- PRISM2_HOSTAPD_GET_RID
- PRISM2_HOSTAPD_MAX_BUF_SIZE
- PRISM2_HOSTAPD_MLME
- PRISM2_HOSTAPD_REMOVE_STA
- PRISM2_HOSTAPD_RID_HDR_LEN
- PRISM2_HOSTAPD_SCAN_REQ
- PRISM2_HOSTAPD_SET_ASSOC_AP_ADDR
- PRISM2_HOSTAPD_SET_FLAGS_STA
- PRISM2_HOSTAPD_SET_GENERIC_ELEMENT
- PRISM2_HOSTAPD_SET_RID
- PRISM2_HOSTAPD_STA_CLEAR_STATS
- PRISM2_HOSTSCAN
- PRISM2_INFO_PENDING_LINKSTATUS
- PRISM2_INFO_PENDING_SCANRESULTS
- PRISM2_IOCTL_ADDMAC
- PRISM2_IOCTL_DELMAC
- PRISM2_IOCTL_DOWNLOAD
- PRISM2_IOCTL_GET_PRISM2_PARAM
- PRISM2_IOCTL_HOSTAPD
- PRISM2_IOCTL_INQUIRE
- PRISM2_IOCTL_KICKMAC
- PRISM2_IOCTL_MACCMD
- PRISM2_IOCTL_MONITOR
- PRISM2_IOCTL_PRISM2_PARAM
- PRISM2_IOCTL_READMIF
- PRISM2_IOCTL_RESET
- PRISM2_IOCTL_SET_RID_WORD
- PRISM2_IOCTL_WDS_ADD
- PRISM2_IOCTL_WDS_DEL
- PRISM2_IOCTL_WRITEMIF
- PRISM2_IO_DEBUG_CMD_ERROR
- PRISM2_IO_DEBUG_CMD_INB
- PRISM2_IO_DEBUG_CMD_INSW
- PRISM2_IO_DEBUG_CMD_INTERRUPT
- PRISM2_IO_DEBUG_CMD_INW
- PRISM2_IO_DEBUG_CMD_OUTB
- PRISM2_IO_DEBUG_CMD_OUTSW
- PRISM2_IO_DEBUG_CMD_OUTW
- PRISM2_IO_DEBUG_ENTRY
- PRISM2_IO_DEBUG_SIZE
- PRISM2_MAX_DOWNLOAD_AREA_LEN
- PRISM2_MAX_DOWNLOAD_LEN
- PRISM2_MAX_FRAME_SIZE
- PRISM2_MAX_INTERRUPT_EVENTS
- PRISM2_MAX_MTU
- PRISM2_MIN_MTU
- PRISM2_MONITOR_80211
- PRISM2_MONITOR_CAPHDR
- PRISM2_MONITOR_PRISM
- PRISM2_MONITOR_RADIOTAP
- PRISM2_NON_VOLATILE_DOWNLOAD
- PRISM2_NUM_CIPHER_SUITES
- PRISM2_PARAM_ALC
- PRISM2_PARAM_ANTSEL_RX
- PRISM2_PARAM_ANTSEL_TX
- PRISM2_PARAM_AP_AUTH_ALGS
- PRISM2_PARAM_AP_AUTOM_AP_WDS
- PRISM2_PARAM_AP_BRIDGE_PACKETS
- PRISM2_PARAM_AP_MAX_INACTIVITY
- PRISM2_PARAM_AP_NULLFUNC_ACK
- PRISM2_PARAM_AP_SCAN
- PRISM2_PARAM_BASIC_RATES
- PRISM2_PARAM_BCRX_STA_KEY
- PRISM2_PARAM_BEACON_INT
- PRISM2_PARAM_DROP_UNENCRYPTED
- PRISM2_PARAM_DTIM_PERIOD
- PRISM2_PARAM_DUMP
- PRISM2_PARAM_ENH_SEC
- PRISM2_PARAM_HOSTAPD
- PRISM2_PARAM_HOSTAPD_STA
- PRISM2_PARAM_HOSTSCAN
- PRISM2_PARAM_HOST_DECRYPT
- PRISM2_PARAM_HOST_ENCRYPT
- PRISM2_PARAM_HOST_ROAMING
- PRISM2_PARAM_IEEE_802_1X
- PRISM2_PARAM_IO_DEBUG
- PRISM2_PARAM_MAX_WDS
- PRISM2_PARAM_MONITOR_ALLOW_FCSERR
- PRISM2_PARAM_MONITOR_TYPE
- PRISM2_PARAM_OPER_RATES
- PRISM2_PARAM_OTHER_AP_POLICY
- PRISM2_PARAM_PRIVACY_INVOKED
- PRISM2_PARAM_PSEUDO_IBSS
- PRISM2_PARAM_SCAN_CHANNEL_MASK
- PRISM2_PARAM_TKIP_COUNTERMEASURES
- PRISM2_PARAM_TXRATECTRL
- PRISM2_PARAM_WDS_TYPE
- PRISM2_PARAM_WPA
- PRISM2_PCCARD
- PRISM2_PCI
- PRISM2_PDA_SIZE
- PRISM2_PLX
- PRISM2_RX_MGMT
- PRISM2_RX_MONITOR
- PRISM2_RX_NON_ASSOC
- PRISM2_RX_NULLFUNC_ACK
- PRISM2_SCAN
- PRISM2_SET_ENCRYPTION
- PRISM2_TXFID_COUNT
- PRISM2_TXFID_EMPTY
- PRISM2_TXFID_LEN
- PRISM2_TXFID_RESERVED
- PRISM2_TXPOWER_AUTO
- PRISM2_TXPOWER_FIXED
- PRISM2_TXPOWER_OFF
- PRISM2_TXPOWER_UNKNOWN
- PRISM2_USB_FWFILE
- PRISM54_ADD_MAC
- PRISM54_DBG_GET_OID
- PRISM54_DBG_OID
- PRISM54_DBG_SET_OID
- PRISM54_DEL_MAC
- PRISM54_GET_MAC
- PRISM54_GET_OID
- PRISM54_GET_POLICY
- PRISM54_GET_PRISMHDR
- PRISM54_GET_WPA
- PRISM54_KICK_ALL
- PRISM54_KICK_MAC
- PRISM54_RESET
- PRISM54_SET_OID_ADDR
- PRISM54_SET_OID_STR
- PRISM54_SET_OID_U32
- PRISM54_SET_POLICY
- PRISM54_SET_PRISMHDR
- PRISM54_SET_WPA
- PRISM_DEV
- PRISM_FW_PDEV
- PRISM_HDR_SIZE
- PRIV
- PRIVATEER_680_INTERRUPT_MASK
- PRIVATEER_HOTPLUG_INTERRUPT_MASK
- PRIVATEER_MCHK__CORR_ECC
- PRIVATEER_MCHK__DC_TAG_PERR
- PRIVATEER_MCHK__ISTREAM_CMOV_FLT
- PRIVATEER_MCHK__ISTREAM_CMOV_PRX
- PRIVATEER_MCHK__OS_BUGCHECK
- PRIVATEER_MCHK__PAL_BUGCHECK
- PRIVATEER_MCHK__PROC_HRD_ERR
- PRIVATEER_MCHK__SYS_CORR_ERR
- PRIVATEER_MCHK__SYS_ENVIRON
- PRIVATEER_MCHK__SYS_HRD_ERR
- PRIVATE_BASE
- PRIVATE_MASK
- PRIVATE_REG
- PRIVATE_STREAM1
- PRIVATE_STREAM2
- PRIVATE_VALUE
- PRIVCFG
- PRIVCFG_MASK
- PRIVCFG_SHIFT
- PRIVCMD_MMAPBATCH_MFN_ERROR
- PRIVCMD_MMAPBATCH_PAGED_ERROR
- PRIVPKTSIZ
- PRIVROOT_NAME
- PRIV_ALIGN
- PRIV_ATTR
- PRIV_BYTES
- PRIV_DEV_ATTR
- PRIV_ENUM2
- PRIV_FLAGS_ADAP
- PRIV_FLAGS_COUNT
- PRIV_FLAGS_PORT
- PRIV_FLAG_PORT_TX_VM
- PRIV_FLAG_PORT_TX_VM_BIT
- PRIV_F_SW_DBG_STATS
- PRIV_HYPER
- PRIV_INSTR_INT_ENABLE
- PRIV_INSTR_INT_STAT
- PRIV_MEM_START_REG
- PRIV_MEM_WIN_SIZE
- PRIV_MODE
- PRIV_PKTID_INFO_REQ
- PRIV_PKTID_INFO_RESP
- PRIV_PKTID_RESET_REQ
- PRIV_PKTID_SET_DEBUG
- PRIV_PKTID_SET_DEF_MODE
- PRIV_PKTID_SET_MODE
- PRIV_PROBLEM
- PRIV_QP
- PRIV_QUEUE_SYNC_TIME_MS
- PRIV_REG_INT_ENABLE
- PRIV_REG_INT_STAT
- PRIV_REG_INT_STATUS
- PRIV_STATE
- PRIV_STR_SIZE
- PRIV_SUPER
- PRIV_SW
- PRIV_TO_DEV
- PRIV_VMA_LOCKED
- PRIV_WL_GAP
- PRI_CAPTURE
- PRI_CH_RADAR_FOUND
- PRI_CTRL_PRI_LVL0
- PRI_CTRL_PRI_LVL1
- PRI_FILTER_OFFSET
- PRI_HIGH
- PRI_LOST_MASK
- PRI_LOS_01_MASK
- PRI_LOS_10_MASK
- PRI_LOW
- PRI_MASK
- PRI_NONE
- PRI_PEND
- PRI_PLAYBACK
- PRI_QUEUE_SIZE
- PRI_READ_FULL_STATUS
- PRI_READ_KEYS
- PRI_READ_RESERVATION
- PRI_REPORT_CAPABILITIES
- PRI_RESP_DENY
- PRI_RESP_FAIL
- PRI_RESP_SUCC
- PRI_RING_EMPTY
- PRI_RING_HEAD
- PRI_RING_LENGTH
- PRI_RING_START
- PRI_RING_TAIL
- PRI_SHIFT
- PRI_TOLERANCE
- PRI_TP_MASK
- PRI_TP_OFF
- PRI_TP_OFFSET
- PRI_TP_ON
- PRI_TP_USAGE
- PRI_ld64
- PRI_lu64
- PRI_lx64
- PRI_xen_long
- PRI_xen_pfn
- PRI_xen_ulong
- PRId64
- PRIo64
- PRIu64
- PRIx64
- PRJQUOTA
- PRLAR
- PRLC_GCLK
- PRLC_GCLK_COUNT_MASK
- PRLC_GCLK_COUNT_SHFT
- PRLC_GCLK_EN
- PRLC_GCLK_EN_MASK
- PRLC_GCLK_EN_SHFT
- PRLC_GCLK_MASK
- PRLC_GCLK_SHFT
- PRLC_MAX_COUNT_MASK
- PRLC_MAX_COUNT_SHFT
- PRLC_USE_INT
- PRLC_USE_INT_MASK
- PRLC_USE_INT_SHFT
- PRLEN_BMSK
- PRLEN_SHFT
- PRLI
- PRLI_ACC_RCVD
- PRLI_PHASE
- PRLI_RCVD
- PRLI_RJT_RCVD
- PRLI_TMO
- PRLO
- PRLO_RCVD
- PRLX_PAGE_LEN
- PRL_DEFAULT
- PRM1_X_H
- PRM1_X_L
- PRM1_Y_H
- PRM1_Y_L
- PRM2_X_H
- PRM2_X_L
- PRM2_Y_H
- PRM2_Y_L
- PRM_DMA_PAD_BYTES_NUM
- PRM_Def
- PRM_HAS_IO_WAKEUP
- PRM_HAS_VOLTAGE
- PRM_INSTANCE_UNKNOWN
- PRM_L_MASK
- PRM_Mask
- PRM_Print
- PRM_RDY_STS
- PRM_REG_DBG_DWORD_ENABLE
- PRM_REG_DBG_FORCE_FRAME
- PRM_REG_DBG_FORCE_VALID
- PRM_REG_DBG_SELECT
- PRM_REG_DBG_SHIFT
- PRM_REG_DISABLE_PRM
- PRM_Read
- PRM_SWOFF_TIME
- PRM_SWOFF_TIME_DEFAULT
- PRM_SYS_CONFIG_1
- PRM_Val
- PRM_Write
- PRNGCONT
- PRNGEN
- PRNG_CHUNKSIZE_SHA512_MAX
- PRNG_CHUNKSIZE_SHA512_MIN
- PRNG_CHUNKSIZE_TDES_MAX
- PRNG_CHUNKSIZE_TDES_MIN
- PRNG_CLK
- PRNG_CONFIG
- PRNG_CONFIG_HW_ENABLE
- PRNG_DATA_OUT
- PRNG_FIXED_SIZE
- PRNG_GEN_ENTROPY_FAILED
- PRNG_GEN_FAILED
- PRNG_INSTANTIATE_FAILED
- PRNG_LFSR_CFG
- PRNG_LFSR_CFG_CLOCKS
- PRNG_LFSR_CFG_MASK
- PRNG_MODE_AUTO
- PRNG_MODE_SHA512
- PRNG_MODE_TDES
- PRNG_MODE_TRNG
- PRNG_NEED_RESET
- PRNG_RESEED_FAILED
- PRNG_RESEED_LIMIT_SHA512
- PRNG_RESEED_LIMIT_SHA512_LOWER
- PRNG_RESEED_LIMIT_TDES
- PRNG_RESEED_LIMIT_TDES_LOWER
- PRNG_RESET
- PRNG_SEED_FAILED
- PRNG_SELFTEST_FAILED
- PRNG_SRC
- PRNG_STATUS
- PRNG_STATUS_DATA_AVAIL
- PROBEDEF_STR
- PROBED_SSID_FILTER
- PROBEREQ_CONFIRM
- PROBEREQ_FTYPE
- PROBERESP_FTYPE
- PROBERSP_PG
- PROBES_BITFIELD
- PROBES_BRANCH
- PROBES_BRANCH_IMM
- PROBES_BRANCH_REG
- PROBES_CLZ
- PROBES_DATA_PROCESSING_IMM
- PROBES_DATA_PROCESSING_REG
- PROBES_EXTEND
- PROBES_EXTEND_ADD
- PROBES_LDMSTM
- PROBES_LDRSTRD
- PROBES_LOAD
- PROBES_LOAD_EXTRA
- PROBES_MMI
- PROBES_MOV_HALFWORD
- PROBES_MOV_IP_SP
- PROBES_MRS
- PROBES_MUL1
- PROBES_MUL2
- PROBES_MUL_ADD
- PROBES_MUL_ADD_LONG
- PROBES_PACK
- PROBES_PRELOAD_IMM
- PROBES_PRELOAD_REG
- PROBES_REV
- PROBES_SATURATE
- PROBES_SATURATING_ARITHMETIC
- PROBES_SEV
- PROBES_STORE
- PROBES_STORE_EXTRA
- PROBES_SWP
- PROBES_T16_ADDSUB
- PROBES_T16_ADD_SP
- PROBES_T16_ADR
- PROBES_T16_BLX
- PROBES_T16_BRANCH
- PROBES_T16_BRANCH_COND
- PROBES_T16_CBZ
- PROBES_T16_CMP
- PROBES_T16_HIREGOPS
- PROBES_T16_IT
- PROBES_T16_LDMSTM
- PROBES_T16_LDRHSTRH
- PROBES_T16_LDRSTR
- PROBES_T16_LDR_LIT
- PROBES_T16_LOGICAL
- PROBES_T16_POP
- PROBES_T16_PUSH
- PROBES_T16_SEV
- PROBES_T16_SIGN_EXTEND
- PROBES_T16_WFE
- PROBES_T32_ADDSUB
- PROBES_T32_ADDWSUBW
- PROBES_T32_ADDWSUBW_PC
- PROBES_T32_BITFIELD
- PROBES_T32_BRANCH
- PROBES_T32_BRANCH_COND
- PROBES_T32_CMP
- PROBES_T32_EMULATE_NONE
- PROBES_T32_LDMSTM
- PROBES_T32_LDRDSTRD
- PROBES_T32_LDRSTR
- PROBES_T32_LDR_LIT
- PROBES_T32_LOGICAL
- PROBES_T32_MEDIA
- PROBES_T32_MOV
- PROBES_T32_MOVW
- PROBES_T32_MRS
- PROBES_T32_MUL_ADD
- PROBES_T32_MUL_ADD2
- PROBES_T32_MUL_ADD_LONG
- PROBES_T32_PLDI
- PROBES_T32_REVERSE
- PROBES_T32_SAT
- PROBES_T32_SEV
- PROBES_T32_SIGN_EXTEND
- PROBES_T32_SIMULATE_NOP
- PROBES_T32_TABLE_BRANCH
- PROBES_T32_TST
- PROBES_T32_WFE
- PROBES_WFE
- PROBE_ARG_PARAMS
- PROBE_ARG_VARS
- PROBE_BUFFER_SIZE
- PROBE_CONTEXT
- PROBE_DEFAULT_STRATEGY
- PROBE_DELAY_MS
- PROBE_DUMP_SEG_NUM
- PROBE_FORCE_SYNCHRONOUS
- PROBE_LENGTH
- PROBE_MUX_ADDR_REG_CPUCLK
- PROBE_MUX_ADDR_REG_MODULE_SEL_MASK
- PROBE_MUX_ADDR_REG_MUX_SEL_MASK
- PROBE_MUX_ADDR_REG_NRXCLK
- PROBE_MUX_ADDR_REG_PCICLK
- PROBE_MUX_ADDR_REG_RE
- PROBE_MUX_ADDR_REG_SYSCLK
- PROBE_MUX_ADDR_REG_UP
- PROBE_MUX_EN
- PROBE_MUX_SEL_HI_MASK
- PROBE_MUX_SEL_LOW_MASK
- PROBE_MUX_SUB_MUX_MASK
- PROBE_OPTION_MAX
- PROBE_OPTION_MAX_3945
- PROBE_PREFER_ASYNCHRONOUS
- PROBE_PRINT
- PROBE_RESPONSE_DATA_NOTIF
- PROBE_RESP_RETRY_CNT
- PROBE_TYPE_BITFIELD
- PROBE_TYPE_END
- PROBE_TYPE_S
- PROBE_TYPE_STRING
- PROBE_TYPE_U
- PROBE_TYPE_X
- PROBLEM_STATE
- PROBS_TOTAL
- PROC
- PROC41
- PROC42
- PROCEED_TO_RECOVER
- PROCESS
- PROCESSING_MAD
- PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID
- PROCESSPPTABLES_H
- PROCESS_ACTIVE_TIME_MS
- PROCESS_ALL_AENS
- PROCESS_AND
- PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
- PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
- PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION
- PROCESS_BACK_OFF_TIME_MS
- PROCESS_CLOCK
- PROCESS_CORNERS_NUM
- PROCESS_DISABLE_ALL
- PROCESS_FLAG
- PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
- PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION
- PROCESS_INFO_DOT_0
- PROCESS_INFO_DOT_1
- PROCESS_INFO_DOT_4
- PROCESS_INFO_MASK
- PROCESS_INFO_SHIFT
- PROCESS_KILL_COUNTER_MASK
- PROCESS_KILL_COUNTER_SHIFT
- PROCESS_KILL_GLOB_AEU_BIT_MASK
- PROCESS_KILL_GLOB_AEU_BIT_SHIFT
- PROCESS_MSG
- PROCESS_OR
- PROCESS_RELEASE
- PROCESS_RESTORE_TIME_MS
- PROCESS_RX_EN
- PROCESS_RX_PACKET
- PROCESS_TDM_EN
- PROCESS_TEST_LOCKED
- PROCESS_TX_EN
- PROCESS_UNLOCK
- PROCID
- PROCID_MASK
- PROCID_SHIFT
- PROCMON_0_85V_DOT_0
- PROCMON_0_95V_DOT_0
- PROCMON_0_95V_DOT_1
- PROCMON_1_05V_DOT_0
- PROCMON_1_05V_DOT_1
- PROCSPEECH
- PROC_286
- PROC_386
- PROC_486
- PROC_68000
- PROC_68010
- PROC_68020
- PROC_68030
- PROC_68040
- PROC_8086
- PROC_960HX
- PROC_960RX
- PROC_ADDR
- PROC_ADDR_DA
- PROC_ADDR_ERR
- PROC_ADDR_FUNC0_CTL
- PROC_ADDR_FUNC0_MBI
- PROC_ADDR_FUNC0_MBO
- PROC_ADDR_FUNC2_CTL
- PROC_ADDR_FUNC2_MBI
- PROC_ADDR_FUNC2_MBO
- PROC_ADDR_MDE
- PROC_ADDR_MPI_RISC
- PROC_ADDR_R
- PROC_ADDR_RDY
- PROC_ADDR_REGBLOCK
- PROC_ADDR_RISC_REG
- PROC_ALPHA
- PROC_BLOCK_SIZE
- PROC_CGROUP_INIT_INO
- PROC_CMD_1588_DEFAULT_INIT
- PROC_CMD_CRC16
- PROC_CMD_FAILED
- PROC_CMD_FIBER_1000BASE_X
- PROC_CMD_FIBER_100BASE_FX
- PROC_CMD_FIBER_DISABLE
- PROC_CMD_FIBER_MEDIA_CONF
- PROC_CMD_FIBER_PORT
- PROC_CMD_MCB_ACCESS_MAC_CONF
- PROC_CMD_NCOMPLETED
- PROC_CMD_NCOMPLETED_TIMEOUT_MS
- PROC_CMD_NOP
- PROC_CMD_NO_MAC_CONF
- PROC_CMD_PHY_INIT
- PROC_CMD_QSGMII_MAC
- PROC_CMD_QSGMII_PORT
- PROC_CMD_READ
- PROC_CMD_READ_MOD_WRITE_PORT
- PROC_CMD_RECONF_PORT
- PROC_CMD_RST_CONF_PORT
- PROC_CMD_SGMII_MAC
- PROC_CMD_SGMII_PORT
- PROC_CMD_WRITE
- PROC_CN_MCAST_IGNORE
- PROC_CN_MCAST_LISTEN
- PROC_CONF_BASENAME
- PROC_DATA
- PROC_DEBUG
- PROC_DYNAMIC_FIRST
- PROC_ENTRY_SIZE
- PROC_EVENT_COMM
- PROC_EVENT_COREDUMP
- PROC_EVENT_EXEC
- PROC_EVENT_EXIT
- PROC_EVENT_FORK
- PROC_EVENT_GID
- PROC_EVENT_NONE
- PROC_EVENT_PTRACE
- PROC_EVENT_SID
- PROC_EVENT_UID
- PROC_EXP
- PROC_FASTOPEN_KEY
- PROC_FIFO
- PROC_FILE_DEFINE
- PROC_FS_JFS
- PROC_GET_BOOT_DESCRIPTOR
- PROC_GET_COM_ENTRY
- PROC_GET_CURRENT_COM_MAPPING
- PROC_GET_EDGE_MANUF_DESCRIPTOR
- PROC_GET_MAPPING_TO_PATH
- PROC_GET_PRODUCT_INFO
- PROC_GET_STRINGS
- PROC_HOST
- PROC_I
- PROC_I2C_
- PROC_IA64
- PROC_IDLE
- PROC_INFO
- PROC_INFO_ADD
- PROC_INFO_BH_STAT
- PROC_INFO_INC
- PROC_INFO_MAX
- PROC_INTEL
- PROC_INTERFACE
- PROC_INTERFACE_VERSION
- PROC_IPC_INIT_INO
- PROC_KERN
- PROC_KPAGECGROUP
- PROC_KPAGECOUNT
- PROC_KPAGEFLAGS
- PROC_LIMIT
- PROC_LOG_BASENAME
- PROC_MEMX
- PROC_MIPS4000
- PROC_MOTOROLA
- PROC_NUMBUF
- PROC_PENTIUM
- PROC_PERF
- PROC_PID_INIT_INO
- PROC_POWERPC
- PROC_POWER_CAPABILITY_CHANGED
- PROC_PPC601
- PROC_PPC603
- PROC_PPC604
- PROC_R4000
- PROC_READ_SETUP
- PROC_ROOT_INO
- PROC_SET_COM_ENTRY
- PROC_SET_COM_MAPPING
- PROC_SEXIUM
- PROC_STATISTICS
- PROC_SUBDIR_NAME
- PROC_SUPER_MAGIC
- PROC_TABLE
- PROC_TABLE_DEREG
- PROC_TABLE_GTSE
- PROC_TABLE_HPT_PT
- PROC_TABLE_HPT_SLB
- PROC_TABLE_NEW
- PROC_TABLE_OP_MASK
- PROC_TABLE_RADIX
- PROC_TABLE_TYPE_MASK
- PROC_TEST
- PROC_THERMAL_NONE
- PROC_THERMAL_PCI
- PROC_THERMAL_PLATFORM_DEV
- PROC_TOSHIBA
- PROC_ULTRASPARC
- PROC_USER_INIT_INO
- PROC_UTS_INIT_INO
- PROC_VTABLE
- PROC_WRITELEN
- PROC_i960
- PRODID_3COM_3C562
- PRODID_3COM_3CCFEM556
- PRODID_3COM_3CXEM556
- PRODID_ACCTON_EN2226
- PRODID_ADAPTEC_SCSI
- PRODID_ATT_KIT
- PRODID_FUJITSU_LA501
- PRODID_FUJITSU_MBH10302
- PRODID_FUJITSU_MBH10304
- PRODID_IBM_HOME_AND_AWAY
- PRODID_INTEL_2PLUS
- PRODID_INTEL_DUAL_RS232
- PRODID_KME_KXLC005_A
- PRODID_KME_KXLC005_B
- PRODID_LINKSYS_3400
- PRODID_LINKSYS_PCMLM28
- PRODID_MEGAHERTZ_EM3288
- PRODID_MEGAHERTZ_VARIOUS
- PRODID_MOTOROLA_MARINER
- PRODID_NATINST_QUAD_RS232
- PRODID_NOKIA_CARDPHONE
- PRODID_OLICOM_OC2231
- PRODID_OLICOM_OC2232
- PRODID_OMEGA_QSP_100
- PRODID_OSITECH_JACK_144
- PRODID_OSITECH_JACK_288
- PRODID_OSITECH_JACK_336
- PRODID_OSITECH_SEVEN
- PRODID_POSSIO_GCC
- PRODID_PSION_NET100
- PRODID_QUATECH_DUAL_RS232
- PRODID_QUATECH_DUAL_RS232_D1
- PRODID_QUATECH_DUAL_RS232_D2
- PRODID_QUATECH_DUAL_RS232_G
- PRODID_QUATECH_DUAL_RS422
- PRODID_QUATECH_QUAD_RS232
- PRODID_QUATECH_QUAD_RS422
- PRODID_QUATECH_SPP100
- PRODID_SMC_ETHER
- PRODID_SOCKET_DUAL_RS232
- PRODID_SOCKET_EIO
- PRODID_SOCKET_LPE
- PRODID_SOCKET_LPE_CF
- PRODID_TDK_CF010
- PRODID_TDK_GN3410
- PRODID_TDK_MN3200
- PRODID_TDK_NP9610
- PRODIGY192_DEVICE_DESC
- PRODIGY192_STAC9460_ADDR
- PRODIGY_HIFI_DEVICE_DESC
- PRODIGY_HP_SEL
- PRODIGY_SPI_CLK
- PRODIGY_SPI_MOSI
- PRODIGY_WM_CS
- PRODUCER_CRCI_DISABLE
- PRODUCER_CRCI_MSK
- PRODUCER_CRCI_X_SEL
- PRODUCER_CRCI_Y_SEL
- PRODUCER_PIPE_ID_MSK
- PRODUCER_PIPE_ID_SHFT
- PRODUCER_PIPE_LOGICAL_SIZE
- PRODUCER_TRANS_END_EN
- PRODUCT
- PRODUCT_BRANDING
- PRODUCT_ID
- PRODUCT_ID_ADD
- PRODUCT_ID_CA42
- PRODUCT_ID_CM109
- PRODUCT_ID_CYPHIDCOM
- PRODUCT_ID_CYPHIDCOM_FRWD
- PRODUCT_ID_EARTHMATEUSB
- PRODUCT_ID_EARTHMATEUSB_LT20
- PRODUCT_ID_KVM
- PRODUCT_ID_LCS8138TX
- PRODUCT_ID_LENGTH
- PRODUCT_ID_LUAKTX
- PRODUCT_ID_MASK
- PRODUCT_ID_OFFSET
- PRODUCT_ID_PRESTIGE
- PRODUCT_ID_REG0
- PRODUCT_ID_REG1
- PRODUCT_ID_REG10
- PRODUCT_ID_REG11
- PRODUCT_ID_REG12
- PRODUCT_ID_REG13
- PRODUCT_ID_REG14
- PRODUCT_ID_REG15
- PRODUCT_ID_REG2
- PRODUCT_ID_REG3
- PRODUCT_ID_REG4
- PRODUCT_ID_REG5
- PRODUCT_ID_REG6
- PRODUCT_ID_REG7
- PRODUCT_ID_REG8
- PRODUCT_ID_REG9
- PRODUCT_ID_RTL8150
- PRODUCT_ID_SIZE
- PRODUCT_ID_SP128AR
- PRODUCT_ID_STRING_ENABLE
- PRODUCT_ID_UPS
- PRODUCT_INFO_OFFSET
- PRODUCT_STRING_READ
- PRODUCT_TYPE_DIRECT_DRIVE
- PRODUCT_TYPE_EXTENSION
- PRODUCT_TYPE_MONITOR
- PRODUCT_TYPE_PANEL
- PRODUCT_TYPE_REPEATER
- PRODUCT_TYPE_TEST
- PRODUCT_TYPE_TV
- PROD_ACORN_ETHER1
- PROD_ACORN_MFM
- PROD_ACORN_SCSI
- PROD_ALSYS_SCSIATAPI
- PROD_ANT_ETHER3
- PROD_ANT_ETHERB
- PROD_ANT_ETHERM
- PROD_ARXE_SCSI
- PROD_ATOMWIDE_3PSERIAL
- PROD_CONS_PTR_1K
- PROD_CONS_PTR_4K
- PROD_CONS_PTR_OFF
- PROD_CUMANA_SCSI_1
- PROD_CUMANA_SCSI_2
- PROD_EESOX_SCSI2
- PROD_I3_ETHERLAN500
- PROD_I3_ETHERLAN600
- PROD_I3_ETHERLAN600A
- PROD_ICS2_IDE
- PROD_ICS_IDE
- PROD_ID
- PROD_ID_1
- PROD_ID_2
- PROD_ID_2a
- PROD_ID_3
- PROD_ID_4
- PROD_ID_ASIC_REV_MASK
- PROD_ID_LEN
- PROD_MCS_CONNECT32
- PROD_MORLEY_SCSI_UNCACHED
- PROD_OAK_SCSI
- PROD_PROPERTY_REG
- PROD_SERPORT_DSPORT
- PROD_YELLOWSTONE_RAPIDE32
- PROFF_FCC1
- PROFF_FCC2
- PROFF_FCC3
- PROFF_FCC_SIZE
- PROFF_I2C_BASE
- PROFF_IDMA1_BASE
- PROFF_IDMA2_BASE
- PROFF_IDMA3_BASE
- PROFF_IDMA4_BASE
- PROFF_IIC
- PROFF_MCC1
- PROFF_MCC2
- PROFF_RAND
- PROFF_REVNUM
- PROFF_RTMR
- PROFF_SCC1
- PROFF_SCC2
- PROFF_SCC3
- PROFF_SCC4
- PROFF_SCC_SIZE
- PROFF_SMC1
- PROFF_SMC1_BASE
- PROFF_SMC2
- PROFF_SMC2_BASE
- PROFF_SMC_SIZE
- PROFF_SPI
- PROFF_SPI_BASE
- PROFF_TIMERS
- PROFILEHZ
- PROFILES_PER_PAGE
- PROFILE_ATTR
- PROFILE_COUNT
- PROFILE_DSP2
- PROFILE_FILTER
- PROFILE_GRPSHIFT
- PROFILE_GRPSZ
- PROFILE_IS_HAT
- PROFILE_MEDIATES
- PROFILE_MEDIATES_AF
- PROFILE_MISMATCH
- PROFILE_MODE
- PROFILE_MUNMAP
- PROFILE_RECORDS_SIZE
- PROFILE_SEL
- PROFILE_TASK_EXIT
- PROFILING_INTLEVEL
- PROFI_DPRAM_SIZE
- PROF_1100
- PROF_7500
- PROF_ADD
- PROF_REPLACE
- PROG
- PROGIF
- PROGNAME
- PROGRAM_CSD
- PROGRAM_ERROR
- PROGRAM_ERROR_N_1
- PROGRAM_EXCEPTION
- PROGRAM_LOAD_DONE
- PROGRAM_LOAD_EEPROM
- PROGRAM_LOAD_ERR
- PROGRAM_LOAD_HOST
- PROGRAM_ROM
- PROGRAM_SRAM
- PROGRAM_VERSION
- PROGRAM_WAIT_CNT
- PROGRAM_WAIT_CNT__VALUE
- PROGRESS_PARAMS_DS_CNT
- PROG_ARRAY_FD
- PROG_BLOCK_SIE
- PROG_CHUNK
- PROG_DONE
- PROG_HLT
- PROG_ID_MAX
- PROG_INTERFACE
- PROG_INTERFACE__PROG_INTERFACE_MASK
- PROG_INTERFACE__PROG_INTERFACE__MASK
- PROG_INTERFACE__PROG_INTERFACE__SHIFT
- PROG_IN_SIE
- PROG_MAX_RM9200_CSS
- PROG_NAME
- PROG_NAME_ARGS
- PROG_NAME_LIST
- PROG_PHY_LINK_RATE
- PROG_PHY_LINK_RATE_MAX_MSK
- PROG_PHY_LINK_RATE_MAX_OFF
- PROG_PHY_LINK_RATE_MIN_MSK
- PROG_PHY_LINK_RATE_MIN_OFF
- PROG_PHY_LINK_RATE_OOB_MSK
- PROG_PHY_LINK_RATE_OOB_OFF
- PROG_PRES
- PROG_RAM_HCLK_OFF
- PROG_RAM_SCLK_OFF
- PROG_REQUEST
- PROG_RESET
- PROG_SEQ
- PROG_SOURCE_MAX
- PROG_START
- PROG_STATUS_MASK
- PROG_STREAM_DIR
- PROG_STREAM_MAP
- PROG_SYNC
- PROLOGUE_OFFSET
- PROLOGUE_SIZE
- PROLOG_ADDITION_1REG_GEN
- PROLOG_ADDITION_2REGS_CRIT
- PROLOG_ADDITION_2REGS_DBG
- PROLOG_ADDITION_2REGS_GEN
- PROLOG_ADDITION_2REGS_MC
- PROLOG_ADDITION_MASKABLE_GEN
- PROLOG_ADDITION_NONE_CRIT
- PROLOG_ADDITION_NONE_DBG
- PROLOG_ADDITION_NONE_GDBELL
- PROLOG_ADDITION_NONE_GEN
- PROLOG_ADDITION_NONE_MC
- PROM
- PROMBLOCK
- PROMDEV_IKBD
- PROMDEV_ITTYA
- PROMDEV_ITTYB
- PROMDEV_I_UNK
- PROMDEV_KBD
- PROMDEV_OSCREEN
- PROMDEV_OTTYA
- PROMDEV_OTTYB
- PROMDEV_O_UNK
- PROMDEV_SCREEN
- PROMDEV_TTYA
- PROMDEV_TTYB
- PROMINTR_MAX
- PROMISC
- PROMISCOUS_MODE
- PROMISCUOUS
- PROMISC_MODE
- PROMISC_REQUESTED
- PROMISC_SUPPORTED
- PROMISCset
- PROMOP_BIST1
- PROMOP_BIST2
- PROMOP_BIST_MASK
- PROMOP_BIST_SHIFT
- PROMOP_CMD_MASK
- PROMOP_HALT
- PROMOP_IMODE
- PROMOP_INVALID
- PROMOP_MAGIC
- PROMOP_MAGIC_MASK
- PROMOP_OPTIONS_MASK
- PROMOP_POWERDOWN
- PROMOP_REBOOT
- PROMOP_REG
- PROMOP_RESTART
- PROMOP_SKIP_DEVINIT
- PROMOP_SKIP_DIAGS
- PROMOP_SKIP_MEMINIT
- PROMOS
- PROMOTE_NOT
- PROMOTE_PERMANENT
- PROMOTE_TEMPORARY
- PROMOTION_COUNT
- PROMREG_MAX
- PROMVADDR_MAX
- PROM_ANDB_RMW
- PROM_ANDH_RMW
- PROM_ANDW_RMW
- PROM_ARGVIZE
- PROM_ATOB
- PROM_AUTOBOOT
- PROM_Addr_Ena
- PROM_BEVEXCEPT
- PROM_BEVUTLB
- PROM_BUG
- PROM_Busy
- PROM_CLEARCACHE
- PROM_CLEARNOFAULT
- PROM_CLOSE
- PROM_CMD
- PROM_DATA
- PROM_DEBUG
- PROM_DISABLECMD
- PROM_DISPLAY_ADDR
- PROM_DUMPCMD
- PROM_E2BIG
- PROM_EACCESS
- PROM_EADDRNOTAVAIL
- PROM_EAGAIN
- PROM_EBADF
- PROM_EBUSY
- PROM_ECONNABORTED
- PROM_EFAULT
- PROM_EINVAL
- PROM_EIO
- PROM_EISDIR
- PROM_EMFILE
- PROM_EMLINK
- PROM_ENABLECMD
- PROM_ENAMETOOLONG
- PROM_END
- PROM_ENOCONNECT
- PROM_ENODEV
- PROM_ENOENT
- PROM_ENOEXEC
- PROM_ENOMEM
- PROM_ENOSPC
- PROM_ENOTDIR
- PROM_ENOTTY
- PROM_ENTRY
- PROM_ENV
- PROM_ENV_FILE
- PROM_ENV_SIZE
- PROM_ENXIO
- PROM_EROFS
- PROM_ERROR
- PROM_ESUCCESS
- PROM_ETIMEDOUT
- PROM_EXEC
- PROM_Erase
- PROM_FLAG_ARCS
- PROM_FLAG_DONT_FREE_TEMP
- PROM_FLAG_USE_AS_CONSOLE
- PROM_FLUSHCACHE
- PROM_FRAME_SIZE
- PROM_GETCHAR
- PROM_GETENV
- PROM_GETPKT
- PROM_GETS
- PROM_GET_HWCONF
- PROM_GET_MEMCONF
- PROM_HELP
- PROM_INITPROTO
- PROM_IOCTL
- PROM_JUMP_TABLE_ENTRY
- PROM_LONGJMP
- PROM_MAP_CACHED
- PROM_MAP_DEFAULT
- PROM_MAP_EXEC
- PROM_MAP_GLOB
- PROM_MAP_IE
- PROM_MAP_LOCKED
- PROM_MAP_READ
- PROM_MAP_SE
- PROM_MAP_WRITE
- PROM_MASK
- PROM_MAX_PMEMBLOCKS
- PROM_MODE
- PROM_MODE_BAD_PROTOCOL
- PROM_MODE_CRC_FAILED
- PROM_MODE_CTRL
- PROM_MODE_DUPLICATED
- PROM_MODE_MGMT
- PROM_MODE_OFF
- PROM_MODE_UNKNOWN
- PROM_MONITOR_ADDR
- PROM_NOTIMPLEMENT
- PROM_NULL_COMPONENT
- PROM_NULL_MDESC
- PROM_NV_GET
- PROM_NV_SET
- PROM_OPEN
- PROM_ORB_RMW
- PROM_ORH_RMW
- PROM_ORW_RMW
- PROM_P1275
- PROM_PARSER
- PROM_PRINTENVCMD
- PROM_PRINTF
- PROM_PROTODISABLE
- PROM_PROTOENABLE
- PROM_PUTCHAR
- PROM_PUTC_ADDR
- PROM_PUTPKT
- PROM_PUTS
- PROM_RANGE
- PROM_READ
- PROM_REBOOT
- PROM_REINIT
- PROM_RESET
- PROM_RESTART
- PROM_Read
- PROM_SETENV
- PROM_SETENVCMD
- PROM_SETJMP
- PROM_SHOWCHAR
- PROM_SIZE
- PROM_START
- PROM_STRCAT
- PROM_STRCMP
- PROM_STRCPY
- PROM_STRLEN
- PROM_UNSETENVCMD
- PROM_V0
- PROM_V2
- PROM_V3
- PROM_VEC
- PROM_WRITE
- PROM_Write
- PROPBASER_RES0_MASK
- PROPERTIES_CHANGED_REQUEST
- PROPERTIES_CHANGED_RESPONSE
- PROPERTIES_DESTROYED
- PROPERTIES_PROVIDED
- PROPERTIES_REQUEST
- PROPERTIES_REQUIRED
- PROPERTIES_RESPONSE
- PROPERTY_ENTRY_BOOL
- PROPERTY_ENTRY_INTEGER
- PROPERTY_ENTRY_INTEGER_ARRAY
- PROPERTY_ENTRY_STRING
- PROPERTY_ENTRY_STRING_ARRAY
- PROPERTY_ENTRY_U16
- PROPERTY_ENTRY_U16_ARRAY
- PROPERTY_ENTRY_U32
- PROPERTY_ENTRY_U32_ARRAY
- PROPERTY_ENTRY_U64
- PROPERTY_ENTRY_U64_ARRAY
- PROPERTY_ENTRY_U8
- PROPERTY_ENTRY_U8_ARRAY
- PROPERTY_SET
- PROPNODECHARS
- PROPNODECHARSSTRICT
- PROPRIETARY_TLV_BASE_ID
- PROP_BATCH
- PROP_CURR
- PROP_ENUM
- PROP_LEN_MAX
- PROP_MAX
- PROP_NAME
- PROP_UPDATE_AND_INV_VLPI
- PROP_UPDATE_VLPI
- PROP_VOLT
- PROP_loops
- PROSAVAGE_I2C_ENAB
- PROSAVAGE_I2C_SCL_IN
- PROSAVAGE_I2C_SCL_OUT
- PROSAVAGE_I2C_SDA_IN
- PROSAVAGE_I2C_SDA_OUT
- PROSPECTOR
- PROTECTED
- PROTECTED_DACL_SECINFO
- PROTECTED_SACL_SECINFO
- PROTECTION
- PROTECTIONS_MASK
- PROTECTIONS_SHIFT
- PROTECTION_INFO_CTX_DIF_TO_PEER_MASK
- PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT
- PROTECTION_INFO_CTX_HOST_INTERFACE_MASK
- PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT
- PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK
- PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT
- PROTECTION_INFO_CTX_RESERVED0_MASK
- PROTECTION_INFO_CTX_RESERVED0_SHIFT
- PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK
- PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT
- PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK
- PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT
- PROTECTION_MODE
- PROTECTION_MODE_AUTO
- PROTECTION_MODE_FORCE_DISABLE
- PROTECTION_MODE_FORCE_ENABLE
- PROTECTION_OVERRIDE
- PROTECTION_OVERRIDE_DEPTH_DWORDS
- PROTECTION_OVERRIDE_DEPTH_ELEMENTS
- PROTECTION_OVERRIDE_ELEMENT_ADDRESS_MASK
- PROTECTION_OVERRIDE_ELEMENT_ADDRESS_SHIFT
- PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR
- PROTECTION_OVERRIDE_ELEMENT_DWORDS
- PROTECTION_OVERRIDE_ELEMENT_READ_MASK
- PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_MASK
- PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_SHIFT
- PROTECTION_OVERRIDE_ELEMENT_READ_SHIFT
- PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_MASK
- PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_SHIFT
- PROTECTION_OVERRIDE_ELEMENT_WRITE_MASK
- PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_MASK
- PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_SHIFT
- PROTECTION_OVERRIDE_ELEMENT_WRITE_SHIFT
- PROTECT_ARRAY
- PROTECT_CTX
- PROTECT_CTX_NOIRQ
- PROTECT_CTX_NOPRINT
- PROTEGO_R2X0
- PROTEGO_SPECIAL_1
- PROTEGO_SPECIAL_3
- PROTEGO_SPECIAL_4
- PROTKEYBLOBSIZE
- PROTO
- PROTOCOLID_COMMON
- PROTOCOLID_CORE
- PROTOCOLID_ETH
- PROTOCOLID_FCOE
- PROTOCOLID_ISCSI
- PROTOCOLID_IWARP
- PROTOCOLID_PREROCE
- PROTOCOLID_RESERVED0
- PROTOCOLID_RESERVED1
- PROTOCOLID_ROCE
- PROTOCOL_ACCEPTED
- PROTOCOL_ATTRIBUTES
- PROTOCOL_EAP
- PROTOCOL_EN
- PROTOCOL_ERR
- PROTOCOL_F
- PROTOCOL_ID
- PROTOCOL_MASK
- PROTOCOL_MESSAGE_ATTRIBUTES
- PROTOCOL_NO_SECURITY
- PROTOCOL_OVERHEAD
- PROTOCOL_REGISTER_1
- PROTOCOL_REGISTER_10
- PROTOCOL_REGISTER_11
- PROTOCOL_REGISTER_12
- PROTOCOL_REGISTER_13
- PROTOCOL_REGISTER_14
- PROTOCOL_REGISTER_15
- PROTOCOL_REGISTER_2
- PROTOCOL_REGISTER_3
- PROTOCOL_REGISTER_4
- PROTOCOL_REGISTER_5
- PROTOCOL_REGISTER_6
- PROTOCOL_REGISTER_7
- PROTOCOL_REGISTER_8
- PROTOCOL_REGISTER_9
- PROTOCOL_REV_MAJOR
- PROTOCOL_REV_MAJOR_MASK
- PROTOCOL_REV_MINOR
- PROTOCOL_REV_MINOR_MASK
- PROTOCOL_S
- PROTOCOL_SELECT_CMD
- PROTOCOL_SINGLE_TMDS_A
- PROTOCOL_SMP
- PROTOCOL_SSP
- PROTOCOL_STATE_BIT_OFFSET
- PROTOCOL_STATIC_WEP
- PROTOCOL_STP
- PROTOCOL_V
- PROTOCOL_VER
- PROTOCOL_VERSION
- PROTOCOL_WPA
- PROTOCOL_WPA2
- PROTOCOL_WPA2_MIXED
- PROTOC_TYPE_SIZE
- PROTO_BITWIDTH
- PROTO_ERROR_VALID_MASK
- PROTO_ERR_IMPL_LOGO
- PROTO_GADGET
- PROTO_HOST
- PROTO_INUSE_NR
- PROTO_REV_MAJOR_MASK
- PROTO_REV_MINOR_MASK
- PROTO_SRAM_LINES
- PROTO_TCP
- PROTO_UDP
- PROTO_UNDEF
- PROT_A1_IN
- PROT_A1_OUT
- PROT_A2_IN
- PROT_A2_OUT
- PROT_ADDR1
- PROT_ADDR2
- PROT_ADDR3
- PROT_ADI
- PROT_BITS_OFFS
- PROT_DEFAULT
- PROT_DEVICE_nGnRE
- PROT_DEVICE_nGnRnE
- PROT_EXEC
- PROT_FCOE
- PROT_GROWSDOWN
- PROT_GROWSUP
- PROT_ISCSI
- PROT_MASK
- PROT_NONE
- PROT_NORMAL
- PROT_NORMAL_NC
- PROT_NORMAL_WT
- PROT_OFFLOAD_CONFIG_CMD
- PROT_OFFLOAD_GROUP
- PROT_PKEY0
- PROT_PKEY1
- PROT_PKEY2
- PROT_PKEY3
- PROT_PTE_DEVICE
- PROT_PTE_S2_DEVICE
- PROT_READ
- PROT_SAO
- PROT_SECT_DEFAULT
- PROT_SECT_DEVICE
- PROT_SECT_DEVICE_nGnRE
- PROT_SECT_NORMAL
- PROT_SECT_NORMAL_EXEC
- PROT_SEM
- PROT_SOCK
- PROT_STAT_PAGE
- PROT_TYPE_ALC
- PROT_TYPE_DAT
- PROT_TYPE_IEP
- PROT_TYPE_KEYC
- PROT_TYPE_LA
- PROT_WRITE
- PROVIDE32
- PROVIDE_LENGTH
- PROVIDIA9685
- PROVISIONING_KEY
- PROXIMITY_DISABLE
- PROXIMITY_ENABLE
- PROXIMITY_OFFSET
- PROXY_BY_BDF
- PROXY_BY_INDEX
- PROXY_NONE
- PROXY_POISON
- PROX_ABOVE_THRESHOLD
- PROX_BELOW_THRESHOLD
- PROX_IGNORE_LUX_LIMIT
- PROX_STAT_CAL
- PROX_STAT_SAMP
- PRO_CLEAR
- PRO_ERASE
- PRO_EX_SET_CMD
- PRO_FEATURES
- PRO_FORMAT
- PRO_GET_INT
- PRO_PREEMPT
- PRO_PREEMPT_AND_ABORT
- PRO_READ_2K_DATA
- PRO_READ_ATRB
- PRO_READ_DATA
- PRO_READ_LONG_DATA
- PRO_READ_QUAD_DATA
- PRO_READ_REG
- PRO_READ_SHORT_DATA
- PRO_REGISTER
- PRO_REGISTER_AND_IGNORE_EXISTING_KEY
- PRO_REGISTER_AND_MOVE
- PRO_RELEASE
- PRO_REPLACE_LOST_RESERVATION
- PRO_RESERVE
- PRO_SET_CMD
- PRO_SET_RW_REG_ADRS
- PRO_SLEEP
- PRO_STOP
- PRO_VERSION_MAX
- PRO_VERSION_MIN
- PRO_WRITE_2K_DATA
- PRO_WRITE_DATA
- PRO_WRITE_LONG_DATA
- PRO_WRITE_QUAD_DATA
- PRO_WRITE_REG
- PRO_WRITE_SHORT_DATA
- PRPENCVF_NUM_PADS
- PRPENCVF_SINK_PAD
- PRPENCVF_SRC_PAD
- PRPH_ASSIGN
- PRPH_BASE
- PRPH_BLOCKBIT
- PRPH_CLEARBIT
- PRPH_END
- PRPH_SETBIT
- PRP_CH1_OUT_IMAGE_SIZE
- PRP_CH1_PIXEL_FORMAT_CNTL
- PRP_CH1_RZ_HORI_COEF1
- PRP_CH1_RZ_HORI_COEF2
- PRP_CH1_RZ_HORI_VALID
- PRP_CH1_RZ_VERT_COEF1
- PRP_CH1_RZ_VERT_COEF2
- PRP_CH1_RZ_VERT_VALID
- PRP_CH2_OUT_IMAGE_SIZE
- PRP_CH2_RZ_HORI_COEF1
- PRP_CH2_RZ_HORI_COEF2
- PRP_CH2_RZ_HORI_VALID
- PRP_CH2_RZ_VERT_COEF1
- PRP_CH2_RZ_VERT_COEF2
- PRP_CH2_RZ_VERT_VALID
- PRP_CNTL
- PRP_CNTL_CH1BYP
- PRP_CNTL_CH1EN
- PRP_CNTL_CH1_LEN
- PRP_CNTL_CH1_OUT_RGB16
- PRP_CNTL_CH1_OUT_RGB32
- PRP_CNTL_CH1_OUT_RGB8
- PRP_CNTL_CH1_OUT_YUV422
- PRP_CNTL_CH1_TSKIP
- PRP_CNTL_CH2B1EN
- PRP_CNTL_CH2B2EN
- PRP_CNTL_CH2EN
- PRP_CNTL_CH2FEN
- PRP_CNTL_CH2_LEN
- PRP_CNTL_CH2_OUT_YUV420
- PRP_CNTL_CH2_OUT_YUV422
- PRP_CNTL_CH2_OUT_YUV444
- PRP_CNTL_CH2_TSKIP
- PRP_CNTL_CLKEN
- PRP_CNTL_CSIEN
- PRP_CNTL_DATA_IN_RGB16
- PRP_CNTL_DATA_IN_RGB32
- PRP_CNTL_DATA_IN_YUV420
- PRP_CNTL_DATA_IN_YUV422
- PRP_CNTL_INPUT_FIFO_LEVEL
- PRP_CNTL_IN_TSKIP
- PRP_CNTL_RZ_FIFO_LEVEL
- PRP_CNTL_SKIP_FRAME
- PRP_CNTL_SWRST
- PRP_CNTL_WEN
- PRP_CSC_COEF_012
- PRP_CSC_COEF_345
- PRP_CSC_COEF_678
- PRP_DEST_CB_PTR
- PRP_DEST_CH1_LINE_STRIDE
- PRP_DEST_CR_PTR
- PRP_DEST_RGB1_PTR
- PRP_DEST_RGB2_PTR
- PRP_DEST_Y_PTR
- PRP_INTRSTATUS
- PRP_INTR_CH1FC
- PRP_INTR_CH1WERR
- PRP_INTR_CH2FC
- PRP_INTR_CH2OVF
- PRP_INTR_CH2WERR
- PRP_INTR_CNTL
- PRP_INTR_LBOVF
- PRP_INTR_RDERR
- PRP_INTR_ST_CH1B1CI
- PRP_INTR_ST_CH1B2CI
- PRP_INTR_ST_CH1WERR
- PRP_INTR_ST_CH2B1CI
- PRP_INTR_ST_CH2B2CI
- PRP_INTR_ST_CH2OVF
- PRP_INTR_ST_CH2WERR
- PRP_INTR_ST_LBOVF
- PRP_INTR_ST_RDERR
- PRP_NUM_PADS
- PRP_SINK_PAD
- PRP_SIZE_HEIGHT
- PRP_SIZE_WIDTH
- PRP_SOURCE_CB_PTR
- PRP_SOURCE_CR_PTR
- PRP_SOURCE_Y_PTR
- PRP_SRC_FRAME_SIZE
- PRP_SRC_LINE_STRIDE
- PRP_SRC_PAD_PRPENC
- PRP_SRC_PAD_PRPVF
- PRP_SRC_PIXEL_FORMAT_CNTL
- PRQ
- PRQ_ED_ADR
- PRQ_ORDER
- PRQ_RD_PTR
- PRQ_RING_MASK
- PRQ_ST_ADR
- PRQ_WR_PTR
- PRR
- PRRN_SCOPE
- PRRR
- PRRR_MT
- PRRR_NOS
- PRR_BVD1_EVENT
- PRR_BVD1_STATUS
- PRR_BVD2_EVENT
- PRR_BVD2_STATUS
- PRR_PHY_RST
- PRR_READY_EVENT
- PRR_READY_STATUS
- PRR_WP_EVENT
- PRR_WP_STATUS
- PRS
- PRSC0_CLK_CFG
- PRSC1_CLK_CFG
- PRSC2_CLK_CFG
- PRSC_OCK_MASK
- PRSC_OCK_SHIFT
- PRSEL
- PRSNT_CHANGE_DETECTED
- PRSNT_CHANGE_INTR_MASK
- PRSNT_MASK
- PRSNT_SHIFT
- PRSR
- PRSR_A0
- PRSR_CON_NT
- PRSR_DATA
- PRSR_ST_OK
- PRSSI_STA
- PRST
- PRSTATUS_SIZE
- PRST_ACODEC
- PRST_CIF1TO4
- PRST_CVBS
- PRST_DBG
- PRST_DBG_NIU
- PRST_DDRMON
- PRST_DDRPHY
- PRST_DDRUPCTL
- PRST_DSP_CFG_NIU
- PRST_DSP_DBG_NIU
- PRST_DSP_GRF
- PRST_DSP_INTC
- PRST_DSP_IOP_NIU
- PRST_DSP_MAILBOX
- PRST_DSP_PFM_MON
- PRST_EFUSE
- PRST_EFUSE512
- PRST_GPIO1
- PRST_GPIO2
- PRST_GPIO3
- PRST_GRF
- PRST_HDMI
- PRST_HDMIPHY
- PRST_I2C1
- PRST_I2C2
- PRST_I2C3
- PRST_MIPI_CSI_PHY
- PRST_MIPI_DSI
- PRST_MIPI_DSI_PHY
- PRST_MSCH_NIU
- PRST_PERIPH_NIU
- PRST_PMU_GPIO0
- PRST_PMU_GRF
- PRST_PMU_I2C0
- PRST_PMU_INTMEM
- PRST_PMU_PWM0
- PRST_PWM1
- PRST_SARADC
- PRST_SPI
- PRST_TIMER0
- PRST_TOP_NIU
- PRST_TSADC
- PRST_UART0
- PRST_UART1
- PRST_UART2
- PRST_USBGRF
- PRST_VADCPHY
- PRST_VDACPHY
- PRST_VIO_NIU
- PRST_VIP0
- PRST_VIP1
- PRST_VIP2
- PRST_VIP4
- PRST_WDT
- PRSVDPAGE_LOC
- PRS_DISABLED
- PRS_ENABLED
- PRS_ERROR
- PRS_ETH_OUTPUT_FORMAT
- PRS_ETH_TUNN_OUTPUT_FORMAT
- PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET
- PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT
- PRS_FLAG_ETHTYPE_NON_UNICAST
- PRS_FLAG_ETHTYPE_UNICAST
- PRS_FLAG_OVERETH_IPV4
- PRS_FLAG_OVERETH_IPV6
- PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN
- PRS_FLAG_OVERETH_UNKNOWN
- PRS_FLAG_OVERIP_TCP
- PRS_FLAG_OVERIP_UDP
- PRS_FLAG_OVERIP_UNKNOWN
- PRS_FLAG_PUREACK_PIGGY
- PRS_FLAG_PUREACK_PURE
- PRS_GFT_CAM_LINES_NO_MATCH
- PRS_REG_A_PRSU_20
- PRS_REG_CFC_LD_CURRENT_CREDIT
- PRS_REG_CFC_SEARCH_CURRENT_CREDIT
- PRS_REG_CFC_SEARCH_INITIAL_CREDIT
- PRS_REG_CID_PORT_0
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4
- PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4
- PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5
- PRS_REG_CM_HDR_GFT
- PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT
- PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT
- PRS_REG_CM_HDR_LOOPBACK_TYPE_1
- PRS_REG_CM_HDR_LOOPBACK_TYPE_2
- PRS_REG_CM_HDR_LOOPBACK_TYPE_3
- PRS_REG_CM_HDR_LOOPBACK_TYPE_4
- PRS_REG_CM_HDR_TYPE_0
- PRS_REG_CM_HDR_TYPE_1
- PRS_REG_CM_HDR_TYPE_2
- PRS_REG_CM_HDR_TYPE_3
- PRS_REG_CM_HDR_TYPE_4
- PRS_REG_CM_NO_MATCH_HDR
- PRS_REG_DBG_DWORD_ENABLE
- PRS_REG_DBG_FORCE_FRAME
- PRS_REG_DBG_FORCE_VALID
- PRS_REG_DBG_SELECT
- PRS_REG_DBG_SHIFT
- PRS_REG_E1HOV_MODE
- PRS_REG_ENCAPSULATION_TYPE_EN
- PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT
- PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK
- PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT
- PRS_REG_EVENT_ID_1
- PRS_REG_EVENT_ID_2
- PRS_REG_EVENT_ID_3
- PRS_REG_FCOE_TYPE
- PRS_REG_FLUSH_REGIONS_TYPE_0
- PRS_REG_FLUSH_REGIONS_TYPE_1
- PRS_REG_FLUSH_REGIONS_TYPE_2
- PRS_REG_FLUSH_REGIONS_TYPE_3
- PRS_REG_FLUSH_REGIONS_TYPE_4
- PRS_REG_FLUSH_REGIONS_TYPE_5
- PRS_REG_FLUSH_REGIONS_TYPE_6
- PRS_REG_FLUSH_REGIONS_TYPE_7
- PRS_REG_GFT_CAM
- PRS_REG_GFT_PROFILE_MASK_RAM
- PRS_REG_GRE_PROTOCOL
- PRS_REG_HDRS_AFTER_BASIC
- PRS_REG_HDRS_AFTER_BASIC_PORT_0
- PRS_REG_HDRS_AFTER_BASIC_PORT_1
- PRS_REG_HDRS_AFTER_TAG_0
- PRS_REG_HDRS_AFTER_TAG_0_PORT_0
- PRS_REG_HDRS_AFTER_TAG_0_PORT_1
- PRS_REG_INC_VALUE
- PRS_REG_LIGHT_L2_ETHERTYPE_EN
- PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET
- PRS_REG_LOAD_L2_FILTER
- PRS_REG_MSG_INFO
- PRS_REG_MUST_HAVE_HDRS
- PRS_REG_MUST_HAVE_HDRS_PORT_0
- PRS_REG_MUST_HAVE_HDRS_PORT_1
- PRS_REG_NGE_COMP_VER
- PRS_REG_NGE_PORT
- PRS_REG_NIC_MODE
- PRS_REG_NO_MATCH_EVENT_ID
- PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES
- PRS_REG_NUM_OF_DEAD_CYCLES
- PRS_REG_NUM_OF_PACKETS
- PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES
- PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET
- PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET
- PRS_REG_OUTPUT_FORMAT_4_0_BB_K2
- PRS_REG_PACKET_REGIONS_TYPE_0
- PRS_REG_PACKET_REGIONS_TYPE_1
- PRS_REG_PACKET_REGIONS_TYPE_2
- PRS_REG_PACKET_REGIONS_TYPE_3
- PRS_REG_PACKET_REGIONS_TYPE_4
- PRS_REG_PACKET_REGIONS_TYPE_5
- PRS_REG_PACKET_REGIONS_TYPE_6
- PRS_REG_PACKET_REGIONS_TYPE_7
- PRS_REG_PENDING_BRB_CAC0_RQ
- PRS_REG_PENDING_BRB_PRS_RQ
- PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST
- PRS_REG_PRS_INT_STS
- PRS_REG_PRS_PRTY_MASK
- PRS_REG_PRS_PRTY_STS
- PRS_REG_PRS_PRTY_STS_CLR
- PRS_REG_PURE_REGIONS
- PRS_REG_ROCE_DEST_QP_MAX_PF
- PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET
- PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET
- PRS_REG_SEARCH_FCOE
- PRS_REG_SEARCH_FCOE_RT_OFFSET
- PRS_REG_SEARCH_GFT
- PRS_REG_SEARCH_NON_IP_AS_GFT
- PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET
- PRS_REG_SEARCH_OPENFLOW
- PRS_REG_SEARCH_OPENFLOW_RT_OFFSET
- PRS_REG_SEARCH_RESP_INITIATOR_TYPE
- PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET
- PRS_REG_SEARCH_ROCE
- PRS_REG_SEARCH_ROCE_RT_OFFSET
- PRS_REG_SEARCH_TAG1
- PRS_REG_SEARCH_TCP
- PRS_REG_SEARCH_TCP_FIRST_FRAG
- PRS_REG_SEARCH_TCP_RT_OFFSET
- PRS_REG_SEARCH_TENANT_ID
- PRS_REG_SEARCH_UDP
- PRS_REG_SERIAL_NUM_STATUS_LSB
- PRS_REG_SERIAL_NUM_STATUS_MSB
- PRS_REG_SOFT_RST
- PRS_REG_SRC_CURRENT_CREDIT
- PRS_REG_TAG_ETHERTYPE_0
- PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET
- PRS_REG_TAG_LEN_0
- PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET
- PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET
- PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET
- PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET
- PRS_REG_TCM_CURRENT_CREDIT
- PRS_REG_TSDM_CURRENT_CREDIT
- PRS_REG_USE_LIGHT_L2
- PRS_REG_VLAN_TYPE_0
- PRS_REG_VXLAN_PORT
- PRTB_ENTRIES
- PRTB_MASK
- PRTB_SIZE_SHIFT
- PRTCIF_CTLR
- PRTCIF_CTLR_BENL_2ND_BYTE
- PRTCIF_CTLR_BENL_3RD_BYTE
- PRTCIF_CTLR_BENL_LSB
- PRTCIF_CTLR_BENL_MASK
- PRTCIF_CTLR_BENL_MSB
- PRTCIF_CTLR_BENU_2ND_BYTE
- PRTCIF_CTLR_BENU_3RD_BYTE
- PRTCIF_CTLR_BENU_LSB
- PRTCIF_CTLR_BENU_MASK
- PRTCIF_CTLR_BENU_MSB
- PRTCIF_CTLR_BUSY
- PRTCIF_CTLR_DIR
- PRTCIF_CTLR_SIZE
- PRTCIF_INTEN
- PRTCIF_INTEN_MASK
- PRTCIF_INTEN_RTCIF
- PRTCIF_INTEN_RTCSS
- PRTCIF_INTFLG
- PRTCIF_INTFLG_MASK
- PRTCIF_INTFLG_RTCIF
- PRTCIF_INTFLG_RTCSS
- PRTCIF_LDATA
- PRTCIF_UDATA
- PRTCON
- PRTCON_PROTECT
- PRTCSS_RTC_ADAY0
- PRTCSS_RTC_ADAY1
- PRTCSS_RTC_AHOUR
- PRTCSS_RTC_AMIN
- PRTCSS_RTC_CCTRL
- PRTCSS_RTC_CCTRL_AIEN
- PRTCSS_RTC_CCTRL_ALMFLG
- PRTCSS_RTC_CCTRL_CAEN
- PRTCSS_RTC_CCTRL_CALBUSY
- PRTCSS_RTC_CCTRL_DAEN
- PRTCSS_RTC_CCTRL_HAEN
- PRTCSS_RTC_CCTRL_MAEN
- PRTCSS_RTC_CLKC_CNT
- PRTCSS_RTC_CTRL
- PRTCSS_RTC_CTRL_TE
- PRTCSS_RTC_CTRL_TIEN
- PRTCSS_RTC_CTRL_TMMD
- PRTCSS_RTC_CTRL_TMRFLG
- PRTCSS_RTC_CTRL_WDRT
- PRTCSS_RTC_CTRL_WDTBUS
- PRTCSS_RTC_CTRL_WDTFLG
- PRTCSS_RTC_CTRL_WEN
- PRTCSS_RTC_DAY0
- PRTCSS_RTC_DAY1
- PRTCSS_RTC_HOUR
- PRTCSS_RTC_INTC_EXTENA1
- PRTCSS_RTC_INTC_EXTENA1_MASK
- PRTCSS_RTC_MIN
- PRTCSS_RTC_SEC
- PRTCSS_RTC_TMR0
- PRTCSS_RTC_TMR1
- PRTCSS_RTC_WDT
- PRTDCB_GENS
- PRTDCB_GENS_DCBX_STATUS_M
- PRTDCB_GENS_DCBX_STATUS_S
- PRTENABLE_F
- PRTENABLE_S
- PRTENABLE_V
- PRTGEN_STATUS
- PRTRPB_RDPC
- PRTSTR
- PRTS_MASK
- PRTS_REG
- PRTYEN
- PRT_CHANNEL_DOMAIN
- PRT_CHANNEL_DOMAIN_2G
- PRT_CHANNEL_DOMAIN_5G
- PRT_CHANNEL_INFO
- PRT_CHANNEL_PLAN
- PRT_CHANNEL_PLAN_2G
- PRT_CHANNEL_PLAN_5G
- PRT_CHANNEL_PLAN_MAP
- PRT_CUSTOMER_ID
- PRT_HIGH_THROUGHPUT
- PRT_HT_INF0_CAPBILITY
- PRT_HT_INF1_CAPBILITY
- PRT_LINK_DETECT_T
- PRT_PMKID_LIST
- PRT_RF_TYPE_819xU
- PRT_SCAN_TYPE
- PRT_SMOOTH_DATA_4RF
- PRT_STATUS
- PRT_TIMER
- PRT_TO_QID_MASK
- PRT_TO_QID_SHIFT
- PRU
- PRUNE_PERIOD
- PRUSR_ACC_CTL_mskDMA_EN
- PRUSR_ACC_CTL_mskPFM_EN
- PRUSR_ACC_CTL_offDMA_EN
- PRUSR_ACC_CTL_offPFM_EN
- PRVIT
- PRV_STATE_BOOT
- PRV_STATE_INIT
- PRV_STATE_OFF
- PRV_STATE_POSTBOOT
- PRV_STATE_PREBOOT
- PRV_STATE_PREINIT
- PRV_STATE_READY
- PRV_STATE_SLEEP
- PRV_WBDGAIN_CHNG
- PRV_WBGAIN_CHNG
- PRW
- PRX
- PRX2
- PRXREPORT
- PRXS0_ANTSEL_0
- PRXS0_ANTSEL_1
- PRXS0_ANTSEL_2
- PRXS0_ANTSEL_3
- PRXS0_ANTSEL_MASK
- PRXS0_ANTSEL_SHIFT
- PRXS0_BAND
- PRXS0_CCK
- PRXS0_CLIP_MASK
- PRXS0_CLIP_SHIFT
- PRXS0_FT_MASK
- PRXS0_GAIN_CTL
- PRXS0_LCRS
- PRXS0_OFDM
- PRXS0_PLCPFV
- PRXS0_PLCPHCF
- PRXS0_PREN
- PRXS0_RSVD
- PRXS0_RXANT_UPSUBBAND
- PRXS0_SHORTH
- PRXS0_STDN
- PRXS0_UNSRATE
- PRXS0_UNUSED
- PRXS1_HTPHY_ANTCFG_MASK
- PRXS1_HTPHY_CORE_MASK
- PRXS1_HTPHY_MMPLCPLenL_MASK
- PRXS1_JSSI_MASK
- PRXS1_JSSI_SHIFT
- PRXS1_SQ_MASK
- PRXS1_SQ_SHIFT
- PRXS1_nphy_PWR0_MASK
- PRXS1_nphy_PWR1_MASK
- PRXS2_HTPHY_MMPLCH_RATE_MASK
- PRXS2_HTPHY_MMPLCPLenH_MASK
- PRXS2_HTPHY_RXPWR_ANT0
- PRXS3_HTPHY_RXPWR_ANT1
- PRXS3_HTPHY_RXPWR_ANT2
- PRXS4_HTPHY_CFO
- PRXS4_HTPHY_RXPWR_ANT3
- PRXS5_HTPHY_AR
- PRXS5_HTPHY_FFO
- PRZ_FLAG_NO_LOCK
- PRZ_FLAG_ZAP_OLD
- PR_24_BITS
- PR_53_BITS
- PR_64_BITS
- PR_A
- PR_APTPL_BUF_LEN
- PR_APTPL_MAX_IPORT_LEN
- PR_APTPL_MAX_TPORT_LEN
- PR_BASE_MASK
- PR_CACHE
- PR_CAPBSET_DROP
- PR_CAPBSET_READ
- PR_CAP_AMBIENT
- PR_CAP_AMBIENT_CLEAR_ALL
- PR_CAP_AMBIENT_IS_SET
- PR_CAP_AMBIENT_LOWER
- PR_CAP_AMBIENT_RAISE
- PR_CONNECTED
- PR_DISCQ
- PR_EEP
- PR_ENDIAN_BIG
- PR_ENDIAN_LITTLE
- PR_ENDIAN_PPC_LITTLE
- PR_EXCLUSIVE_ACCESS
- PR_EXCLUSIVE_ACCESS_ALL_REGS
- PR_EXCLUSIVE_ACCESS_REG_ONLY
- PR_FL_IGNORE_KEY
- PR_FPEMU_NOPRINT
- PR_FPEMU_SIGFPE
- PR_FP_ALL_EXCEPT
- PR_FP_EXC_ASYNC
- PR_FP_EXC_DISABLED
- PR_FP_EXC_DIV
- PR_FP_EXC_INV
- PR_FP_EXC_NONRECOV
- PR_FP_EXC_OVF
- PR_FP_EXC_PRECISE
- PR_FP_EXC_RES
- PR_FP_EXC_SW_ENABLE
- PR_FP_EXC_UND
- PR_FP_MODE_FR
- PR_FP_MODE_FRE
- PR_GET_CHILD_SUBREAPER
- PR_GET_DUMPABLE
- PR_GET_ENDIAN
- PR_GET_FPEMU
- PR_GET_FPEXC
- PR_GET_FP_MODE
- PR_GET_KEEPCAPS
- PR_GET_NAME
- PR_GET_NO_NEW_PRIVS
- PR_GET_PDEATHSIG
- PR_GET_SECCOMP
- PR_GET_SECUREBITS
- PR_GET_SPECULATION_CTRL
- PR_GET_TAGGED_ADDR_CTRL
- PR_GET_THP_DISABLE
- PR_GET_TID_ADDRESS
- PR_GET_TIMERSLACK
- PR_GET_TIMING
- PR_GET_TSC
- PR_GET_UNALIGN
- PR_HOST_STATUS_IDLE
- PR_IB_SUPPORTED
- PR_INFO
- PR_INPUTQ
- PR_IN_SZ
- PR_IS
- PR_LIMIT_MASK
- PR_LIMIT_SHIFT
- PR_LINES
- PR_LINESTRIP
- PR_MASK
- PR_MCE_KILL
- PR_MCE_KILL_CLEAR
- PR_MCE_KILL_DEFAULT
- PR_MCE_KILL_EARLY
- PR_MCE_KILL_GET
- PR_MCE_KILL_LATE
- PR_MCE_KILL_SET
- PR_MIN
- PR_MPX_DISABLE_MANAGEMENT
- PR_MPX_ENABLE_MANAGEMENT
- PR_NOT_SUPPORTED
- PR_OFF
- PR_OPA_SUPPORTED
- PR_OUT_SZ
- PR_PAC_APDAKEY
- PR_PAC_APDBKEY
- PR_PAC_APGAKEY
- PR_PAC_APIAKEY
- PR_PAC_APIBKEY
- PR_PAC_RESET_KEYS
- PR_POLYGON
- PR_QNUM
- PR_RECTS
- PR_REG_ISID_ID_LEN
- PR_REG_ISID_LEN
- PR_RES
- PR_RESERVED_BITS
- PR_RPE
- PR_SCOPE_LU_SCOPE
- PR_SECCOMP_EXT
- PR_SET_CHILD_SUBREAPER
- PR_SET_DUMPABLE
- PR_SET_ENDIAN
- PR_SET_FPEMU
- PR_SET_FPEXC
- PR_SET_FP_MODE
- PR_SET_KEEPCAPS
- PR_SET_MM
- PR_SET_MM_ARG_END
- PR_SET_MM_ARG_START
- PR_SET_MM_AUXV
- PR_SET_MM_BRK
- PR_SET_MM_END_CODE
- PR_SET_MM_END_DATA
- PR_SET_MM_ENV_END
- PR_SET_MM_ENV_START
- PR_SET_MM_EXE_FILE
- PR_SET_MM_MAP
- PR_SET_MM_MAP_SIZE
- PR_SET_MM_START_BRK
- PR_SET_MM_START_CODE
- PR_SET_MM_START_DATA
- PR_SET_MM_START_STACK
- PR_SET_NAME
- PR_SET_NO_NEW_PRIVS
- PR_SET_PDEATHSIG
- PR_SET_PTRACER
- PR_SET_PTRACER_ANY
- PR_SET_SECCOMP
- PR_SET_SECUREBITS
- PR_SET_SPECULATION_CTRL
- PR_SET_TAGGED_ADDR_CTRL
- PR_SET_THP_DISABLE
- PR_SET_TIMERSLACK
- PR_SET_TIMING
- PR_SET_TSC
- PR_SET_UNALIGN
- PR_SHIFT
- PR_SPEC_DISABLE
- PR_SPEC_DISABLE_NOEXEC
- PR_SPEC_ENABLE
- PR_SPEC_FORCE_DISABLE
- PR_SPEC_INDIRECT_BRANCH
- PR_SPEC_NOT_AFFECTED
- PR_SPEC_PRCTL
- PR_SPEC_STORE_BYPASS
- PR_STATISTICS
- PR_STOP
- PR_SVE_GET_VL
- PR_SVE_SET_VL
- PR_SVE_SET_VL_ONEXEC
- PR_SVE_VL_INHERIT
- PR_SVE_VL_LEN_MASK
- PR_TAGGED_ADDR_ENABLE
- PR_TASK_PERF_EVENTS_DISABLE
- PR_TASK_PERF_EVENTS_ENABLE
- PR_TEST
- PR_TIMING_STATISTICAL
- PR_TIMING_TIMESTAMP
- PR_TRIANGLES
- PR_TRIFAN
- PR_TRISTRIP_0
- PR_TRISTRIP_1
- PR_TSC_ENABLE
- PR_TSC_SIGSEGV
- PR_TYPE_EXCLUSIVE_ACCESS
- PR_TYPE_EXCLUSIVE_ACCESS_ALLREG
- PR_TYPE_EXCLUSIVE_ACCESS_REGONLY
- PR_TYPE_WRITE_EXCLUSIVE
- PR_TYPE_WRITE_EXCLUSIVE_ALLREG
- PR_TYPE_WRITE_EXCLUSIVE_REGONLY
- PR_UNALIGN_NOPRINT
- PR_UNALIGN_SIGBUS
- PR_UTIL_H
- PR_VERSION
- PR_WAIT_TIMEOUT
- PR_WPE
- PR_WRITE_EXCLUSIVE
- PR_WRITE_EXCLUSIVE_ALL_REGS
- PR_WRITE_EXCLUSIVE_REG_ONLY
- PRxCDAR
- PS
- PS0_10_FN1
- PS0_10_FN2
- PS0_11_FN1
- PS0_11_FN2
- PS0_12_FN1
- PS0_12_FN2
- PS0_13_FN1
- PS0_13_FN2
- PS0_14_FN1
- PS0_14_FN2
- PS0_15_FN1
- PS0_15_FN2
- PS0_2_FN1
- PS0_2_FN2
- PS0_3_FN1
- PS0_3_FN2
- PS0_4_FN1
- PS0_4_FN2
- PS0_5_FN1
- PS0_5_FN2
- PS0_6_FN1
- PS0_6_FN2
- PS0_7_FN1
- PS0_7_FN2
- PS0_8_FN1
- PS0_8_FN2
- PS0_9_FN1
- PS0_9_FN2
- PS16
- PS1_10_FN1
- PS1_10_FN2
- PS1_2_FN1
- PS1_2_FN2
- PS1_8_FN1
- PS1_8_FN2
- PS1_9_FN1
- PS1_9_FN2
- PS2
- PS2CLKDIV
- PS2CR
- PS2CR_ENA
- PS2CR_FKC
- PS2CR_FKD
- PS2DATA
- PS2ESDI_MAJOR
- PS2MULT_BSYNC
- PS2MULT_ESCAPE
- PS2MULT_KBD_PORT
- PS2MULT_KB_SELECTOR
- PS2MULT_MOUSE_PORT
- PS2MULT_MS_SELECTOR
- PS2MULT_NUM_PORTS
- PS2MULT_SESSION_END
- PS2MULT_SESSION_START
- PS2PP_EXTRA_BTN
- PS2PP_HWHEEL
- PS2PP_KIND_MX
- PS2PP_KIND_TP3
- PS2PP_KIND_TRACKMAN
- PS2PP_KIND_WHEEL
- PS2PP_NAV_BTN
- PS2PP_SIDE_BTN
- PS2PP_TASK_BTN
- PS2PP_WHEEL
- PS2PRECNT
- PS2STAT
- PS2STAT_ENA
- PS2STAT_KBC
- PS2STAT_KBD
- PS2STAT_RXB
- PS2STAT_RXF
- PS2STAT_RXP
- PS2STAT_STP
- PS2STAT_TXB
- PS2STAT_TXE
- PS2_12_FN1
- PS2_12_FN2
- PS2_13_FN1
- PS2_13_FN2
- PS2_2_FN1
- PS2_2_FN2
- PS2_4_FN1
- PS2_4_FN2
- PS2_5_FN1
- PS2_5_FN2
- PS2_6_FN1
- PS2_6_FN2
- PS2_7_FN1
- PS2_7_FN2
- PS2_ACK_BIT
- PS2_ALWAYS_1
- PS2_CMD_GETID
- PS2_CMD_RESEND
- PS2_CMD_RESET_BAT
- PS2_CMD_SETRES
- PS2_CMD_SETSCALE11
- PS2_CNT
- PS2_COMMAND
- PS2_CONTROL_RESET
- PS2_CONTROL_RX_CLOCK_ENABLE
- PS2_CONTROL_RX_INT_ENABLE
- PS2_CONTROL_TX_CLOCK_DISABLE
- PS2_CONTROL_TX_ENABLE
- PS2_CONTROL_TX_INT_ENABLE
- PS2_CTRL
- PS2_CTRL_CLK
- PS2_CTRL_DAT
- PS2_CTRL_ENABLE
- PS2_CTRL_RXIRQ
- PS2_CTRL_TXIRQ
- PS2_DATA
- PS2_DATA_BIT0
- PS2_DATA_BIT1
- PS2_DATA_BIT2
- PS2_DATA_BIT3
- PS2_DATA_BIT4
- PS2_DATA_BIT5
- PS2_DATA_BIT6
- PS2_DATA_BIT7
- PS2_DEV_RET_ACK
- PS2_DEV_RET_NACK
- PS2_FCTL_RXOFIEN
- PS2_FCTL_RXRDYIEN
- PS2_FCTL_RXRST
- PS2_FCTL_RXUFIEN
- PS2_FCTL_TXOFIEN
- PS2_FCTL_TXRDYIEN
- PS2_FCTL_TXRST
- PS2_FCTL_TXUFIEN
- PS2_FIFO_ERROR_BIT
- PS2_FLAG_ACK
- PS2_FLAG_ACK_CMD
- PS2_FLAG_CMD
- PS2_FLAG_CMD1
- PS2_FLAG_NAK
- PS2_FLAG_WAITID
- PS2_FSTS_RXOF
- PS2_FSTS_RXRDY
- PS2_FSTS_RXUF
- PS2_FSTS_TXOF
- PS2_FSTS_TXRDY
- PS2_FSTS_TXUF
- PS2_GCTL_BUSEN
- PS2_GCTL_INTEN
- PS2_GCTL_INTFLAG
- PS2_GCTL_MASTER
- PS2_GCTL_RESET
- PS2_LCTL_ACKERREN
- PS2_LCTL_NOACK
- PS2_LCTL_PARERREN
- PS2_LCTL_RXDTOEN
- PS2_LCTL_STOPERREN
- PS2_LCTL_TXDTOEN
- PS2_LEFT
- PS2_LINE_ERROR_BIT
- PS2_LSTS_ACKERR
- PS2_LSTS_PARERR
- PS2_LSTS_RXTDO
- PS2_LSTS_STOPERR
- PS2_LSTS_TXTDO
- PS2_MIDDLE
- PS2_MODE_RX
- PS2_MODE_TX
- PS2_PARITY_BIT
- PS2_REG_CLKDR
- PS2_REG_DATA
- PS2_REG_FCTL
- PS2_REG_FSTS
- PS2_REG_GCTL
- PS2_REG_LCTL
- PS2_REG_LSTS
- PS2_RET_ACK
- PS2_RET_BAT
- PS2_RET_ERR
- PS2_RET_ID
- PS2_RET_NAK
- PS2_RIGHT
- PS2_SAMPLE_CLK
- PS2_SCLK
- PS2_START_BIT
- PS2_STATUS
- PS2_STATUS_CLOCK_INHIBIT
- PS2_STATUS_CLOCK_SIGNAL
- PS2_STATUS_ERROR_FRAMING
- PS2_STATUS_ERROR_PARITY
- PS2_STATUS_RX_FULL
- PS2_STATUS_RX_INPROGRESS
- PS2_STATUS_TX_EMPTY
- PS2_STATUS_TX_INPROGRESS
- PS2_STAT_CLK
- PS2_STAT_DAT
- PS2_STAT_PARITY
- PS2_STAT_RXFULL
- PS2_STAT_RX_BUF_OVER
- PS2_STAT_RX_FRM_ERR
- PS2_STAT_RX_INT_EN
- PS2_STAT_RX_VAL
- PS2_STAT_TXBUSY
- PS2_STAT_TXEMPTY
- PS2_STAT_TX_INT_EN
- PS2_STAT_TX_ISNOT_FUL
- PS2_STOP_BIT
- PS2_TX_TIMEOUT
- PS2_X_OVERFLOW
- PS2_X_SIGN
- PS2_Y_OVERFLOW
- PS2_Y_SIGN
- PS32
- PS3AV_AVB_NUM_AUDIO
- PS3AV_AVB_NUM_AV_AUDIO
- PS3AV_AVB_NUM_AV_VIDEO
- PS3AV_AVB_NUM_VIDEO
- PS3AV_AVMULTI_MAX
- PS3AV_AV_LAYOUT_0
- PS3AV_AV_LAYOUT_1
- PS3AV_AV_PORT_MAX
- PS3AV_BUF_SIZE
- PS3AV_CID_AUDIO_ACTIVE
- PS3AV_CID_AUDIO_CTRL
- PS3AV_CID_AUDIO_INACTIVE
- PS3AV_CID_AUDIO_INIT
- PS3AV_CID_AUDIO_MODE
- PS3AV_CID_AUDIO_MUTE
- PS3AV_CID_AUDIO_SPDIF_BIT
- PS3AV_CID_AVB_PARAM
- PS3AV_CID_AV_AUDIO_MUTE
- PS3AV_CID_AV_AUDIO_PARAM
- PS3AV_CID_AV_DISABLE_EVENT
- PS3AV_CID_AV_ENABLE_EVENT
- PS3AV_CID_AV_FIN
- PS3AV_CID_AV_GET_HW_CONF
- PS3AV_CID_AV_GET_MONITOR_INFO
- PS3AV_CID_AV_HDMI_MODE
- PS3AV_CID_AV_INIT
- PS3AV_CID_AV_TV_MUTE
- PS3AV_CID_AV_VIDEO_CS
- PS3AV_CID_AV_VIDEO_DISABLE_SIG
- PS3AV_CID_AV_VIDEO_MUTE
- PS3AV_CID_EVENT_HDCP_AUTH
- PS3AV_CID_EVENT_HDCP_DONE
- PS3AV_CID_EVENT_HDCP_ERROR
- PS3AV_CID_EVENT_HDCP_FAIL
- PS3AV_CID_EVENT_PLUGGED
- PS3AV_CID_EVENT_UNPLUGGED
- PS3AV_CID_MASK
- PS3AV_CID_VIDEO_FORMAT
- PS3AV_CID_VIDEO_INIT
- PS3AV_CID_VIDEO_MODE
- PS3AV_CID_VIDEO_PITCH
- PS3AV_CMD_AUDIO_CTRL_AVCLK_18
- PS3AV_CMD_AUDIO_CTRL_AVCLK_22
- PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_OFF
- PS3AV_CMD_AUDIO_CTRL_DE_EMPHASIS_ON
- PS3AV_CMD_AUDIO_CTRL_ID_AVCLK
- PS3AV_CMD_AUDIO_CTRL_ID_DAC_DE_EMPHASIS
- PS3AV_CMD_AUDIO_CTRL_ID_DAC_RESET
- PS3AV_CMD_AUDIO_CTRL_RESET_ASSERT
- PS3AV_CMD_AUDIO_CTRL_RESET_NEGATE
- PS3AV_CMD_AUDIO_DOWNMIX_PERMITTED
- PS3AV_CMD_AUDIO_DOWNMIX_PROHIBITED
- PS3AV_CMD_AUDIO_FORMAT_BITSTREAM
- PS3AV_CMD_AUDIO_FORMAT_PCM
- PS3AV_CMD_AUDIO_FS_176K
- PS3AV_CMD_AUDIO_FS_192K
- PS3AV_CMD_AUDIO_FS_32K
- PS3AV_CMD_AUDIO_FS_44K
- PS3AV_CMD_AUDIO_FS_48K
- PS3AV_CMD_AUDIO_FS_88K
- PS3AV_CMD_AUDIO_FS_96K
- PS3AV_CMD_AUDIO_LAYOUT_2CH
- PS3AV_CMD_AUDIO_LAYOUT_6CH
- PS3AV_CMD_AUDIO_LAYOUT_8CH
- PS3AV_CMD_AUDIO_MAP_OUTPUT_0
- PS3AV_CMD_AUDIO_MAP_OUTPUT_1
- PS3AV_CMD_AUDIO_MAP_OUTPUT_2
- PS3AV_CMD_AUDIO_MAP_OUTPUT_3
- PS3AV_CMD_AUDIO_NUM_OF_CH_2
- PS3AV_CMD_AUDIO_NUM_OF_CH_3
- PS3AV_CMD_AUDIO_NUM_OF_CH_4
- PS3AV_CMD_AUDIO_NUM_OF_CH_5
- PS3AV_CMD_AUDIO_NUM_OF_CH_6
- PS3AV_CMD_AUDIO_NUM_OF_CH_7
- PS3AV_CMD_AUDIO_NUM_OF_CH_8
- PS3AV_CMD_AUDIO_PORT_AVMULTI_0
- PS3AV_CMD_AUDIO_PORT_HDMI_0
- PS3AV_CMD_AUDIO_PORT_HDMI_1
- PS3AV_CMD_AUDIO_PORT_SPDIF_0
- PS3AV_CMD_AUDIO_PORT_SPDIF_1
- PS3AV_CMD_AUDIO_SOURCE_SERIAL
- PS3AV_CMD_AUDIO_SOURCE_SPDIF
- PS3AV_CMD_AUDIO_SWAP_0
- PS3AV_CMD_AUDIO_SWAP_1
- PS3AV_CMD_AUDIO_WORD_BITS_16
- PS3AV_CMD_AUDIO_WORD_BITS_20
- PS3AV_CMD_AUDIO_WORD_BITS_24
- PS3AV_CMD_AVPORT_AVMULTI_0
- PS3AV_CMD_AVPORT_HDMI_0
- PS3AV_CMD_AVPORT_HDMI_1
- PS3AV_CMD_AVPORT_SPDIF_0
- PS3AV_CMD_AVPORT_SPDIF_1
- PS3AV_CMD_AV_ASPECT_16_9
- PS3AV_CMD_AV_ASPECT_4_3
- PS3AV_CMD_AV_CS_10
- PS3AV_CMD_AV_CS_12
- PS3AV_CMD_AV_CS_8
- PS3AV_CMD_AV_CS_RGB_10
- PS3AV_CMD_AV_CS_RGB_12
- PS3AV_CMD_AV_CS_RGB_8
- PS3AV_CMD_AV_CS_XVYCC_10
- PS3AV_CMD_AV_CS_XVYCC_12
- PS3AV_CMD_AV_CS_XVYCC_8
- PS3AV_CMD_AV_CS_YUV422_10
- PS3AV_CMD_AV_CS_YUV422_12
- PS3AV_CMD_AV_CS_YUV422_8
- PS3AV_CMD_AV_CS_YUV444_10
- PS3AV_CMD_AV_CS_YUV444_12
- PS3AV_CMD_AV_CS_YUV444_8
- PS3AV_CMD_AV_DITHER_10BIT
- PS3AV_CMD_AV_DITHER_12BIT
- PS3AV_CMD_AV_DITHER_8BIT
- PS3AV_CMD_AV_DITHER_OFF
- PS3AV_CMD_AV_DITHER_ON
- PS3AV_CMD_AV_HDMI_DVI
- PS3AV_CMD_AV_HDMI_EDID_PASS
- PS3AV_CMD_AV_HDMI_HDCP_OFF
- PS3AV_CMD_AV_HDMI_MODE_NORMAL
- PS3AV_CMD_AV_INPUTLEN_16
- PS3AV_CMD_AV_INPUTLEN_20
- PS3AV_CMD_AV_INPUTLEN_24
- PS3AV_CMD_AV_LAYOUT_176
- PS3AV_CMD_AV_LAYOUT_192
- PS3AV_CMD_AV_LAYOUT_32
- PS3AV_CMD_AV_LAYOUT_44
- PS3AV_CMD_AV_LAYOUT_48
- PS3AV_CMD_AV_LAYOUT_88
- PS3AV_CMD_AV_LAYOUT_96
- PS3AV_CMD_AV_MCLK_128
- PS3AV_CMD_AV_MCLK_256
- PS3AV_CMD_AV_MCLK_512
- PS3AV_CMD_AV_SUPER_WHITE_OFF
- PS3AV_CMD_AV_SUPER_WHITE_ON
- PS3AV_CMD_AV_VID_1080I_50HZ
- PS3AV_CMD_AV_VID_1080I_60HZ
- PS3AV_CMD_AV_VID_1080P_50HZ
- PS3AV_CMD_AV_VID_1080P_60HZ
- PS3AV_CMD_AV_VID_480I
- PS3AV_CMD_AV_VID_480P
- PS3AV_CMD_AV_VID_576I
- PS3AV_CMD_AV_VID_576P
- PS3AV_CMD_AV_VID_720P_50HZ
- PS3AV_CMD_AV_VID_720P_60HZ
- PS3AV_CMD_AV_VID_SXGA
- PS3AV_CMD_AV_VID_WUXGA
- PS3AV_CMD_AV_VID_WXGA
- PS3AV_CMD_EVENT_BIT_HDCP_DONE
- PS3AV_CMD_EVENT_BIT_HDCP_FAIL
- PS3AV_CMD_EVENT_BIT_HDCP_REAUTH
- PS3AV_CMD_EVENT_BIT_HDCP_TOPOLOGY
- PS3AV_CMD_EVENT_BIT_PLUGGED
- PS3AV_CMD_EVENT_BIT_UNPLUGGED
- PS3AV_CMD_MUTE_OFF
- PS3AV_CMD_MUTE_ON
- PS3AV_CMD_VIDEO_CL_CNV_DISABLE_LUT
- PS3AV_CMD_VIDEO_CL_CNV_ENABLE_LUT
- PS3AV_CMD_VIDEO_CS_NONE
- PS3AV_CMD_VIDEO_CS_RGB
- PS3AV_CMD_VIDEO_CS_RGB_10
- PS3AV_CMD_VIDEO_CS_RGB_12
- PS3AV_CMD_VIDEO_CS_RGB_8
- PS3AV_CMD_VIDEO_CS_XVYCC_10
- PS3AV_CMD_VIDEO_CS_XVYCC_12
- PS3AV_CMD_VIDEO_CS_XVYCC_8
- PS3AV_CMD_VIDEO_CS_YUV422
- PS3AV_CMD_VIDEO_CS_YUV422_10
- PS3AV_CMD_VIDEO_CS_YUV422_12
- PS3AV_CMD_VIDEO_CS_YUV422_8
- PS3AV_CMD_VIDEO_CS_YUV444
- PS3AV_CMD_VIDEO_CS_YUV444_10
- PS3AV_CMD_VIDEO_CS_YUV444_12
- PS3AV_CMD_VIDEO_CS_YUV444_8
- PS3AV_CMD_VIDEO_FMT_X8R8G8B8
- PS3AV_CMD_VIDEO_FORMAT_ARGB_8BIT
- PS3AV_CMD_VIDEO_FORMAT_BLACK
- PS3AV_CMD_VIDEO_HEAD_A
- PS3AV_CMD_VIDEO_HEAD_B
- PS3AV_CMD_VIDEO_ORDER_BGR
- PS3AV_CMD_VIDEO_ORDER_RGB
- PS3AV_CMD_VIDEO_OUT_FORMAT_RGB_12BIT
- PS3AV_CMD_VIDEO_SYNC_CSYNC
- PS3AV_CMD_VIDEO_SYNC_HSYNC
- PS3AV_CMD_VIDEO_SYNC_VSYNC
- PS3AV_CMD_VIDEO_VID_1080I_50HZ
- PS3AV_CMD_VIDEO_VID_1080I_60HZ
- PS3AV_CMD_VIDEO_VID_1080P_50HZ
- PS3AV_CMD_VIDEO_VID_1080P_60HZ
- PS3AV_CMD_VIDEO_VID_480I
- PS3AV_CMD_VIDEO_VID_480I_A
- PS3AV_CMD_VIDEO_VID_480P
- PS3AV_CMD_VIDEO_VID_576I
- PS3AV_CMD_VIDEO_VID_576P
- PS3AV_CMD_VIDEO_VID_720P_50HZ
- PS3AV_CMD_VIDEO_VID_720P_60HZ
- PS3AV_CMD_VIDEO_VID_NONE
- PS3AV_CMD_VIDEO_VID_SXGA
- PS3AV_CMD_VIDEO_VID_WUXGA
- PS3AV_CMD_VIDEO_VID_WXGA
- PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_50
- PS3AV_DEFAULT_AVMULTI_MODE_ID_REG_60
- PS3AV_DEFAULT_HDMI_MODE_ID_REG_50
- PS3AV_DEFAULT_HDMI_MODE_ID_REG_60
- PS3AV_EVENT_CMD_MASK
- PS3AV_EVENT_ID_MASK
- PS3AV_HDMI_MAX
- PS3AV_HDR_SIZE
- PS3AV_HEAD_MAX
- PS3AV_MODE_1080I50
- PS3AV_MODE_1080I60
- PS3AV_MODE_1080P50
- PS3AV_MODE_1080P60
- PS3AV_MODE_480I
- PS3AV_MODE_480P
- PS3AV_MODE_576I
- PS3AV_MODE_576P
- PS3AV_MODE_720P50
- PS3AV_MODE_720P60
- PS3AV_MODE_AUTO
- PS3AV_MODE_COLOR
- PS3AV_MODE_DITHER
- PS3AV_MODE_DVI
- PS3AV_MODE_FULL
- PS3AV_MODE_HDCP_OFF
- PS3AV_MODE_MASK
- PS3AV_MODE_RGB
- PS3AV_MODE_SXGA
- PS3AV_MODE_WHITE
- PS3AV_MODE_WUXGA
- PS3AV_MODE_WXGA
- PS3AV_MONITOR_TYPE_DVI
- PS3AV_MONITOR_TYPE_HDMI
- PS3AV_MUTE_PORT_MAX
- PS3AV_OPT_PORT_MAX
- PS3AV_PKT_AVB_PARAM_MAX_BUF_SIZE
- PS3AV_REGION_50
- PS3AV_REGION_60
- PS3AV_REGION_RGB
- PS3AV_REPLY_BIT
- PS3AV_RESBIT_1280x720P
- PS3AV_RESBIT_1920x1080I
- PS3AV_RESBIT_1920x1080P
- PS3AV_RESBIT_720x480P
- PS3AV_RESBIT_720x576P
- PS3AV_RESBIT_SXGA
- PS3AV_RESBIT_VGA
- PS3AV_RESBIT_WUXGA
- PS3AV_RESBIT_WXGA
- PS3AV_RES_MASK_50
- PS3AV_RES_MASK_60
- PS3AV_RES_MASK_VESA
- PS3AV_STATUS_BUFFER_OVERFLOW
- PS3AV_STATUS_FAILURE
- PS3AV_STATUS_INVALID_AUDIO_CH
- PS3AV_STATUS_INVALID_AUDIO_PARAM
- PS3AV_STATUS_INVALID_AV_PARAM
- PS3AV_STATUS_INVALID_COLOR_SPACE
- PS3AV_STATUS_INVALID_COMMAND
- PS3AV_STATUS_INVALID_FS
- PS3AV_STATUS_INVALID_PORT
- PS3AV_STATUS_INVALID_SAMPLE_SIZE
- PS3AV_STATUS_INVALID_VID
- PS3AV_STATUS_INVALID_VIDEO_PARAM
- PS3AV_STATUS_NO_SEL
- PS3AV_STATUS_NO_SYNC_HEAD
- PS3AV_STATUS_RECEIVE_VUART_ERROR
- PS3AV_STATUS_SUCCESS
- PS3AV_STATUS_SYSCON_COMMUNICATE_FAIL
- PS3AV_STATUS_UNSUPPORTED_COMMAND
- PS3AV_STATUS_UNSUPPORTED_HDMI_MODE
- PS3AV_STATUS_UNSUPPORTED_VERSION
- PS3AV_VERSION
- PS3DISK_MAX_DISKS
- PS3DISK_MINORS
- PS3DISK_NAME
- PS3FB_IOCTL_FSEL
- PS3FB_IOCTL_GETMODE
- PS3FB_IOCTL_OFF
- PS3FB_IOCTL_ON
- PS3FB_IOCTL_SCREENINFO
- PS3FB_IOCTL_SETMODE
- PS3REMOTE
- PS3ROM_MAX_SECTORS
- PS3_10_FN1
- PS3_10_FN2
- PS3_11_FN1
- PS3_11_FN2
- PS3_12_FN1
- PS3_12_FN2
- PS3_13_FN1
- PS3_13_FN2
- PS3_14_FN1
- PS3_14_FN2
- PS3_15_FN1
- PS3_15_FN2
- PS3_1_FN1
- PS3_1_FN2
- PS3_2_FN1
- PS3_2_FN2
- PS3_7_FN1
- PS3_7_FN2
- PS3_8_FN1
- PS3_8_FN2
- PS3_9_FN1
- PS3_9_FN2
- PS3_AUDIO_A1_3WMCTRL_ASOEN0
- PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED
- PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED
- PS3_AUDIO_A2_3WMCTRL_ASOEN0
- PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED
- PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED
- PS3_AUDIO_A3_3WMCTRL_ASOEN0
- PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED
- PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED
- PS3_AUDIO_AO_3WCTRL
- PS3_AUDIO_AO_3WCTRL_ASOBRST
- PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE
- PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET
- PS3_AUDIO_AO_3WCTRL_ASODB_16BIT
- PS3_AUDIO_AO_3WCTRL_ASODB_20BIT
- PS3_AUDIO_AO_3WCTRL_ASODB_24BIT
- PS3_AUDIO_AO_3WCTRL_ASODB_MASK
- PS3_AUDIO_AO_3WCTRL_ASODB_RESVD
- PS3_AUDIO_AO_3WCTRL_ASODF
- PS3_AUDIO_AO_3WCTRL_ASODF_LSB
- PS3_AUDIO_AO_3WCTRL_ASODF_MSB
- PS3_AUDIO_AO_3WMCTRL
- PS3_AUDIO_AO_3WMCTRL_ASOBCLKD
- PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED
- PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED
- PS3_AUDIO_AO_3WMCTRL_ASOEN
- PS3_AUDIO_AO_3WMCTRL_ASOEN0
- PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED
- PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED
- PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED
- PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED
- PS3_AUDIO_AO_3WMCTRL_ASOLRCKD
- PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED
- PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED
- PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL
- PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0
- PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1
- PS3_AUDIO_AO_3WMCTRL_ASOPLRCK
- PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT
- PS3_AUDIO_AO_3WMCTRL_ASORUN
- PS3_AUDIO_AO_3WMCTRL_ASORUN0
- PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING
- PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED
- PS3_AUDIO_AO_3WMCTRL_ASORUN1
- PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING
- PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED
- PS3_AUDIO_AO_3WMCTRL_ASORUN2
- PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING
- PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED
- PS3_AUDIO_AO_3WMCTRL_ASORUN3
- PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING
- PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED
- PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING
- PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED
- PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12
- PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2
- PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4
- PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8
- PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK
- PS3_AUDIO_AO_3W_LDATA
- PS3_AUDIO_AO_3W_RDATA
- PS3_AUDIO_AO_MCTRL
- PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED
- PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED
- PS3_AUDIO_AO_MCTRL_MCLKC0_MASK
- PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2
- PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3
- PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED
- PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED
- PS3_AUDIO_AO_MCTRL_MCLKC1_MASK
- PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2
- PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3
- PS3_AUDIO_AO_MCTRL_MR0_DEFAULT
- PS3_AUDIO_AO_MCTRL_MR0_MASK
- PS3_AUDIO_AO_MCTRL_MR1_DEFAULT
- PS3_AUDIO_AO_MCTRL_MR1_MASK
- PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT
- PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK
- PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT
- PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK
- PS3_AUDIO_AO_SPDCS
- PS3_AUDIO_AO_SPDCTRL
- PS3_AUDIO_AO_SPDCTRL_SPOBRST
- PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE
- PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET
- PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT
- PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT
- PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT
- PS3_AUDIO_AO_SPDCTRL_SPODB_MASK
- PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD
- PS3_AUDIO_AO_SPDCTRL_SPODF
- PS3_AUDIO_AO_SPDCTRL_SPODF_LSB
- PS3_AUDIO_AO_SPDCTRL_SPODF_MSB
- PS3_AUDIO_AO_SPDCTRL_SPOEN
- PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED
- PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED
- PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL
- PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0
- PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1
- PS3_AUDIO_AO_SPDCTRL_SPORUN
- PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING
- PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED
- PS3_AUDIO_AO_SPDCTRL_SPOSR
- PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12
- PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2
- PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4
- PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8
- PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN
- PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK
- PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF
- PS3_AUDIO_AO_SPDUB
- PS3_AUDIO_AO_SPD_DATA
- PS3_AUDIO_AO_SPD_REGBASE
- PS3_AUDIO_AX_AOBP
- PS3_AUDIO_AX_AOBP_ASO0BRN_MASK
- PS3_AUDIO_AX_AOBP_ASO0BWN_MASK
- PS3_AUDIO_AX_AOBP_ASO1BRN_MASK
- PS3_AUDIO_AX_AOBP_ASO1BWN_MASK
- PS3_AUDIO_AX_AOBP_ASO2BRN_MASK
- PS3_AUDIO_AX_AOBP_ASO2BWN_MASK
- PS3_AUDIO_AX_AOBP_ASO3BRN_MASK
- PS3_AUDIO_AX_AOBP_ASO3BWN_MASK
- PS3_AUDIO_AX_AOBP_ASOBRN_MASK
- PS3_AUDIO_AX_AOBP_ASOBWN_MASK
- PS3_AUDIO_AX_IC
- PS3_AUDIO_AX_IC_AASOIMD_EVERY1
- PS3_AUDIO_AX_IC_AASOIMD_EVERY2
- PS3_AUDIO_AX_IC_AASOIMD_EVERY4
- PS3_AUDIO_AX_IC_AASOIMD_MASK
- PS3_AUDIO_AX_IC_SPO0IMD_EVERY1
- PS3_AUDIO_AX_IC_SPO0IMD_EVERY2
- PS3_AUDIO_AX_IC_SPO0IMD_EVERY4
- PS3_AUDIO_AX_IC_SPO0IMD_MASK
- PS3_AUDIO_AX_IC_SPO1IMD_EVERY1
- PS3_AUDIO_AX_IC_SPO1IMD_EVERY2
- PS3_AUDIO_AX_IC_SPO1IMD_EVERY4
- PS3_AUDIO_AX_IC_SPO1IMD_MASK
- PS3_AUDIO_AX_IE
- PS3_AUDIO_AX_IE_ASO0BEIE
- PS3_AUDIO_AX_IE_ASO0BUIE
- PS3_AUDIO_AX_IE_ASO1BEIE
- PS3_AUDIO_AX_IE_ASO1BUIE
- PS3_AUDIO_AX_IE_ASO2BEIE
- PS3_AUDIO_AX_IE_ASO2BUIE
- PS3_AUDIO_AX_IE_ASO3BEIE
- PS3_AUDIO_AX_IE_ASO3BUIE
- PS3_AUDIO_AX_IE_ASOBEIE
- PS3_AUDIO_AX_IE_ASOBUIE
- PS3_AUDIO_AX_IE_SPO0BEIE
- PS3_AUDIO_AX_IE_SPO0BTCIE
- PS3_AUDIO_AX_IE_SPO0BUIE
- PS3_AUDIO_AX_IE_SPO1BEIE
- PS3_AUDIO_AX_IE_SPO1BTCIE
- PS3_AUDIO_AX_IE_SPO1BUIE
- PS3_AUDIO_AX_IE_SPOBEIE
- PS3_AUDIO_AX_IE_SPOBTCIE
- PS3_AUDIO_AX_IE_SPOBUIE
- PS3_AUDIO_AX_IS
- PS3_AUDIO_AX_ISBP
- PS3_AUDIO_AX_ISBP_SPO0BRN_MASK
- PS3_AUDIO_AX_ISBP_SPO0BWN_MASK
- PS3_AUDIO_AX_ISBP_SPO1BRN_MASK
- PS3_AUDIO_AX_ISBP_SPO1BWN_MASK
- PS3_AUDIO_AX_ISBP_SPOBRN_MASK
- PS3_AUDIO_AX_ISBP_SPOBWN_MASK
- PS3_AUDIO_AX_MCTRL
- PS3_AUDIO_AX_MCTRL_AAOMT
- PS3_AUDIO_AX_MCTRL_AASOMT
- PS3_AUDIO_AX_MCTRL_ASO0MT
- PS3_AUDIO_AX_MCTRL_ASO1MT
- PS3_AUDIO_AX_MCTRL_ASO2MT
- PS3_AUDIO_AX_MCTRL_ASO3MT
- PS3_AUDIO_AX_MCTRL_ASOMT
- PS3_AUDIO_AX_MCTRL_ASPOMT
- PS3_AUDIO_AX_MCTRL_SPO0MT
- PS3_AUDIO_AX_MCTRL_SPO1MT
- PS3_AUDIO_AX_MCTRL_SPOMT
- PS3_AUDIO_CONFIG
- PS3_AUDIO_CONFIG_CLEAR
- PS3_AUDIO_DEST
- PS3_AUDIO_DEST_START_MASK
- PS3_AUDIO_DEST_TARGET_AUDIOFIFO
- PS3_AUDIO_DEST_TARGET_MASK
- PS3_AUDIO_DMAC_BLOCK_SIZE
- PS3_AUDIO_DMAC_MAX_BLOCKS
- PS3_AUDIO_DMAC_REGBASE
- PS3_AUDIO_DMASIZE
- PS3_AUDIO_DMASIZE_BLOCKS_MASK
- PS3_AUDIO_FIFO_SIZE
- PS3_AUDIO_FIFO_STAGE_COUNT
- PS3_AUDIO_FIFO_STAGE_SIZE
- PS3_AUDIO_INTR_0
- PS3_AUDIO_INTR_0_CHAN
- PS3_AUDIO_INTR_0_CHAN0
- PS3_AUDIO_INTR_0_CHAN1
- PS3_AUDIO_INTR_0_CHAN2
- PS3_AUDIO_INTR_0_CHAN3
- PS3_AUDIO_INTR_0_CHAN4
- PS3_AUDIO_INTR_0_CHAN5
- PS3_AUDIO_INTR_0_CHAN6
- PS3_AUDIO_INTR_0_CHAN7
- PS3_AUDIO_INTR_0_CHAN8
- PS3_AUDIO_INTR_0_CHAN9
- PS3_AUDIO_INTR_EN_0
- PS3_AUDIO_IOID
- PS3_AUDIO_KICK
- PS3_AUDIO_KICK_EVENT_ALWAYS
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA0
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA1
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA2
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA3
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA4
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA5
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA6
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA7
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA8
- PS3_AUDIO_KICK_EVENT_AUDIO_DMA9
- PS3_AUDIO_KICK_EVENT_MASK
- PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY
- PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW
- PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY
- PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW
- PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY
- PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW
- PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY
- PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW
- PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE
- PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY
- PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW
- PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE
- PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY
- PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW
- PS3_AUDIO_KICK_REQUEST
- PS3_AUDIO_KICK_REQUEST_ACTIVE
- PS3_AUDIO_KICK_REQUEST_IDLE
- PS3_AUDIO_KICK_STATUS_CLEAR
- PS3_AUDIO_KICK_STATUS_DMA
- PS3_AUDIO_KICK_STATUS_DONE
- PS3_AUDIO_KICK_STATUS_ERROR
- PS3_AUDIO_KICK_STATUS_EVENT
- PS3_AUDIO_KICK_STATUS_MASK
- PS3_AUDIO_KICK_STATUS_NOTIFY
- PS3_AUDIO_KICK_STATUS_PENDING
- PS3_AUDIO_NORMAL_DMA_COUNT
- PS3_AUDIO_NORMAL_DMA_START_CH
- PS3_AUDIO_NULL_DMA_COUNT
- PS3_AUDIO_NULL_DMA_START_CH
- PS3_AUDIO_SOURCE
- PS3_AUDIO_SOURCE_START_MASK
- PS3_AUDIO_SOURCE_TARGET_MASK
- PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY
- PS3_BINDING_CPU_0
- PS3_BINDING_CPU_1
- PS3_BINDING_CPU_ANY
- PS3_BMP_MINALIGN
- PS3_BUS_TYPE_SB
- PS3_BUS_TYPE_STORAGE
- PS3_DEVICE_TYPE_IOC0
- PS3_DEVICE_TYPE_LPM
- PS3_DEVICE_TYPE_SB
- PS3_DEVICE_TYPE_VUART
- PS3_DEV_TYPE_SB_GELIC
- PS3_DEV_TYPE_SB_GPIO
- PS3_DEV_TYPE_SB_USB
- PS3_DEV_TYPE_STOR_DISK
- PS3_DEV_TYPE_STOR_FLASH
- PS3_DEV_TYPE_STOR_ROM
- PS3_DMA_16M
- PS3_DMA_1M
- PS3_DMA_4K
- PS3_DMA_64K
- PS3_DMA_INTERNAL
- PS3_DMA_OTHER
- PS3_INTERRUPT_TYPE_EVENT_PORT
- PS3_INTERRUPT_TYPE_OTHER
- PS3_INTERRUPT_TYPE_SB_EHCI
- PS3_INTERRUPT_TYPE_SB_OHCI
- PS3_INVALID_OUTLET
- PS3_LPAR_ID_CURRENT
- PS3_LPAR_ID_PME
- PS3_LPAR_VAS_ID_CURRENT
- PS3_LPM_DEFAULT_TB_CACHE_SIZE
- PS3_LPM_RIGHTS_USE_LPM
- PS3_LPM_RIGHTS_USE_TB
- PS3_LPM_SHADOW_REG_INIT
- PS3_LPM_TB_TYPE_INTERNAL
- PS3_LPM_TB_TYPE_NONE
- PS3_MATCH_ID_AV_SETTINGS
- PS3_MATCH_ID_EHCI
- PS3_MATCH_ID_GELIC
- PS3_MATCH_ID_GPU
- PS3_MATCH_ID_LPM
- PS3_MATCH_ID_OHCI
- PS3_MATCH_ID_SOUND
- PS3_MATCH_ID_STOR_DISK
- PS3_MATCH_ID_STOR_FLASH
- PS3_MATCH_ID_STOR_ROM
- PS3_MATCH_ID_SYSTEM_MANAGER
- PS3_MATCH_SUB_ID_GPU_FB
- PS3_MATCH_SUB_ID_GPU_RAMDISK
- PS3_MMIO_4K
- PS3_MMIO_64K
- PS3_MODULE_ALIAS_AV_SETTINGS
- PS3_MODULE_ALIAS_EHCI
- PS3_MODULE_ALIAS_GELIC
- PS3_MODULE_ALIAS_GPU_FB
- PS3_MODULE_ALIAS_GPU_RAMDISK
- PS3_MODULE_ALIAS_LPM
- PS3_MODULE_ALIAS_OHCI
- PS3_MODULE_ALIAS_SOUND
- PS3_MODULE_ALIAS_STOR_DISK
- PS3_MODULE_ALIAS_STOR_FLASH
- PS3_MODULE_ALIAS_STOR_ROM
- PS3_MODULE_ALIAS_SYSTEM_MANAGER
- PS3_NOTIFICATION_DEV_ID
- PS3_NOTIFICATION_INTERRUPT_ID
- PS3_PARAM_AV_MULTI_OUT_NTSC
- PS3_PARAM_AV_MULTI_OUT_PAL_RGB
- PS3_PARAM_AV_MULTI_OUT_PAL_YCBCR
- PS3_PARAM_AV_MULTI_OUT_SECAM
- PS3_PLUG_MAX
- PS3_PM_BOOKMARK_START
- PS3_PM_BOOKMARK_STOP
- PS3_PM_BOOKMARK_TAG_KERNEL
- PS3_PM_BOOKMARK_TAG_MASK_HI
- PS3_PM_BOOKMARK_TAG_MASK_LO
- PS3_PM_BOOKMARK_TAG_USER
- PS3_PM_CONTROL_PPU_COUNT_MODE_MASK
- PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM
- PS3_PM_CONTROL_PPU_TH0_BOOKMARK
- PS3_PM_CONTROL_PPU_TH1_BOOKMARK
- PS3_PM_COUNTER_MASK_HI
- PS3_PM_COUNTER_MASK_LO
- PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START
- PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP
- PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START
- PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP
- PS3_PM_START_STOP_START_MASK
- PS3_PM_START_STOP_STOP_MASK
- PS3_REG_TYPE_SB_EHCI
- PS3_REG_TYPE_SB_GPIO
- PS3_REG_TYPE_SB_OHCI
- PS3_SM_ATTR_ALL
- PS3_SM_ATTR_CONTROLLER
- PS3_SM_ATTR_POWER
- PS3_SM_ATTR_RESET
- PS3_SM_ATTR_THERMAL
- PS3_SM_BUTTON_EVENT_HARD
- PS3_SM_BUTTON_EVENT_SOFT
- PS3_SM_CMD_SHUTDOWN
- PS3_SM_EVENT_POWER_PRESSED
- PS3_SM_EVENT_POWER_RELEASED
- PS3_SM_EVENT_RESET_PRESSED
- PS3_SM_EVENT_RESET_RELEASED
- PS3_SM_EVENT_THERMAL_ALERT
- PS3_SM_EVENT_THERMAL_CLEARED
- PS3_SM_NEXT_OP_LPAR_REBOOT
- PS3_SM_NEXT_OP_SYS_REBOOT
- PS3_SM_NEXT_OP_SYS_SHUTDOWN
- PS3_SM_RX_MSG_LEN_MAX
- PS3_SM_RX_MSG_LEN_MIN
- PS3_SM_SERVICE_ID_COMMAND
- PS3_SM_SERVICE_ID_EXTERN_EVENT
- PS3_SM_SERVICE_ID_REQUEST
- PS3_SM_SERVICE_ID_REQUEST_ERROR
- PS3_SM_SERVICE_ID_RESPONSE
- PS3_SM_SERVICE_ID_SET_ATTR
- PS3_SM_SERVICE_ID_SET_NEXT_OP
- PS3_SM_WAKE_DEFAULT
- PS3_SM_WAKE_P_O_R
- PS3_SM_WAKE_W_O_L
- PS3_SPU_RESOURCE_TYPE_EXCLUSIVE
- PS3_SPU_RESOURCE_TYPE_SHARED
- PS3_SYSTEM_BUS_DRIVER
- PS3_VENDOR_ID_NONE
- PS3_VENDOR_ID_SONY
- PS3_VERBOSE_RESULT
- PS3_WRITE_PM_MASK
- PS4_0_FN1
- PS4_0_FN2
- PS4_10_FN1
- PS4_10_FN2
- PS4_12_FN1
- PS4_12_FN2
- PS4_13_FN1
- PS4_13_FN2
- PS4_14_FN1
- PS4_14_FN2
- PS4_1_FN1
- PS4_1_FN2
- PS4_2_FN1
- PS4_2_FN2
- PS4_3_FN1
- PS4_3_FN2
- PS4_4_FN1
- PS4_4_FN2
- PS4_8_FN1
- PS4_8_FN2
- PS4_9_FN1
- PS4_9_FN2
- PS5_10_FN1
- PS5_10_FN2
- PS5_11_FN1
- PS5_11_FN2
- PS5_2_FN1
- PS5_2_FN2
- PS5_3_FN1
- PS5_3_FN2
- PS5_4_FN1
- PS5_4_FN2
- PS5_5_FN1
- PS5_5_FN2
- PS5_6_FN1
- PS5_6_FN2
- PS5_7_FN1
- PS5_7_FN2
- PS5_8_FN1
- PS5_8_FN2
- PS5_9_FN1
- PS5_9_FN2
- PS64
- PS6_0_FN1
- PS6_0_FN2
- PS6_10_FN1
- PS6_10_FN2
- PS6_11_FN1
- PS6_11_FN2
- PS6_12_FN1
- PS6_12_FN2
- PS6_13_FN1
- PS6_13_FN2
- PS6_14_FN1
- PS6_14_FN2
- PS6_15_FN1
- PS6_15_FN2
- PS6_1_FN1
- PS6_1_FN2
- PS6_2_FN1
- PS6_2_FN2
- PS6_3_FN1
- PS6_3_FN2
- PS6_4_FN1
- PS6_4_FN2
- PS6_5_FN1
- PS6_5_FN2
- PS6_6_FN1
- PS6_6_FN2
- PS6_7_FN1
- PS6_7_FN2
- PS6_8_FN1
- PS6_8_FN2
- PS6_9_FN1
- PS6_9_FN2
- PS7_10_FN1
- PS7_10_FN2
- PS7_11_FN1
- PS7_11_FN2
- PS7_12_FN1
- PS7_12_FN2
- PS7_13_FN1
- PS7_13_FN2
- PS7_14_FN1
- PS7_14_FN2
- PS7_15_FN1
- PS7_15_FN2
- PS7_4_FN1
- PS7_4_FN2
- PS7_5_FN1
- PS7_5_FN2
- PS7_6_FN1
- PS7_6_FN2
- PS7_7_FN1
- PS7_7_FN2
- PS7_8_FN1
- PS7_8_FN2
- PS7_9_FN1
- PS7_9_FN2
- PS8
- PS8622_MAX_BRIGHTNESS
- PS8622_POWER_FALL_T16_MAX_US
- PS8622_POWER_OFF_T17_MS
- PS8622_POWER_RISE_T1_MAX_US
- PS8622_POWER_RISE_T1_MIN_US
- PS8622_PWMO_END_T12_MS
- PS8622_RST_HIGH_T2_MAX_US
- PS8622_RST_HIGH_T2_MIN_US
- PS8_10_FN1
- PS8_10_FN2
- PS8_11_FN1
- PS8_11_FN2
- PS8_12_FN1
- PS8_12_FN2
- PS8_13_FN1
- PS8_13_FN2
- PS8_14_FN1
- PS8_14_FN2
- PS8_15_FN1
- PS8_15_FN2
- PS8_8_FN1
- PS8_8_FN2
- PS8_9_FN1
- PS8_9_FN2
- PSA0_0
- PSA0_1
- PSA10_0
- PSA10_1
- PSA11_PSA10_FN1
- PSA11_PSA10_FN2
- PSA12_0
- PSA12_1
- PSA13_0
- PSA13_1
- PSA13_PSA12_FN1
- PSA13_PSA12_FN2
- PSA14_0
- PSA14_1
- PSA14_IRQ7
- PSA14_KEYIN4
- PSA15_0
- PSA15_1
- PSA15_IRQ6
- PSA15_KEYIN0
- PSA15_PSA14_FN1
- PSA15_PSA14_FN2
- PSA1_0
- PSA1_1
- PSA2_0
- PSA2_1
- PSA3_0
- PSA3_1
- PSA3_PSA2_FN1
- PSA3_PSA2_FN2
- PSA4_IRQ2
- PSA4_SDHID2
- PSA5_0
- PSA5_1
- PSA5_PSA4_FN1
- PSA5_PSA4_FN2
- PSA5_PSA4_FN3
- PSA6_0
- PSA6_1
- PSA7_0
- PSA7_1
- PSA8_0
- PSA8_1
- PSA9_0
- PSA9_1
- PSA9_BS
- PSA9_IRQ4
- PSAMPLE_ATTR_DATA
- PSAMPLE_ATTR_GROUP_REFCOUNT
- PSAMPLE_ATTR_GROUP_SEQ
- PSAMPLE_ATTR_IIFINDEX
- PSAMPLE_ATTR_MAX
- PSAMPLE_ATTR_OIFINDEX
- PSAMPLE_ATTR_ORIGSIZE
- PSAMPLE_ATTR_SAMPLE_GROUP
- PSAMPLE_ATTR_SAMPLE_RATE
- PSAMPLE_CMD_DEL_GROUP
- PSAMPLE_CMD_GET_GROUP
- PSAMPLE_CMD_NEW_GROUP
- PSAMPLE_CMD_SAMPLE
- PSAMPLE_GENL_NAME
- PSAMPLE_GENL_VERSION
- PSAMPLE_MAX_PACKET_SIZE
- PSAMPLE_NL_MCGRP_CONFIG
- PSAMPLE_NL_MCGRP_CONFIG_NAME
- PSAMPLE_NL_MCGRP_SAMPLE
- PSAMPLE_NL_MCGRP_SAMPLE_NAME
- PSB0_0
- PSB0_1
- PSB0_SIOF1_TXD
- PSB0_SIUAOSLD
- PSB10_0
- PSB10_1
- PSB10_SIOSCK
- PSB10_SIUBOBT
- PSB11_0
- PSB11_1
- PSB11_SIOSTRB1
- PSB11_SIUBOLR
- PSB12_0
- PSB12_1
- PSB12_SIOSTRB0
- PSB12_SIUBIBT
- PSB13_0
- PSB13_1
- PSB13_PSB12_LCDC_RGB
- PSB13_PSB12_LCDC_SYS
- PSB13_SIOD
- PSB13_SIUBILR
- PSB14_0
- PSB14_1
- PSB14_SIORXD
- PSB14_SIUBISLD
- PSB15_PSB14_FN1
- PSB15_PSB14_FN2
- PSB15_SIOTXD
- PSB15_SIUBOSLD
- PSB1_0
- PSB1_1
- PSB1_SIOF1_MCK
- PSB1_SIUMCKA
- PSB2_0
- PSB2_1
- PSB2_SIM_RST
- PSB2_SIOF0_SS2
- PSB3_0
- PSB3_1
- PSB3_PSB2_FN1
- PSB3_PSB2_FN2
- PSB3_SIOF0_SS1
- PSB3_TS_SPSYNC
- PSB4_0
- PSB4_1
- PSB4_SIOF0_SYNC
- PSB4_TS_SDEN
- PSB5_0
- PSB5_1
- PSB5_PSB4_FN1
- PSB5_PSB4_FN2
- PSB5_SIOF0_SCK
- PSB5_TS_SCK
- PSB6_0
- PSB6_1
- PSB6_IRDA_IN
- PSB6_SIOF0_RXD
- PSB7_0
- PSB7_1
- PSB7_IRDA_OUT
- PSB7_PSB6_FN1
- PSB7_PSB6_FN2
- PSB7_SIOF0_TXD
- PSB8_0
- PSB8_1
- PSB8_IRQ3
- PSB8_SIOF0_MCK
- PSB9_0
- PSB9_1
- PSB9_PSB8_FN1
- PSB9_PSB8_FN2
- PSB9_PSB8_FN3
- PSB9_SIOMCK
- PSB9_SIUMCKB
- PSBBREG_AFE0
- PSBBREG_RF0
- PSBBREG_RF1
- PSBBREG_RF2
- PSBBREG_TOTALCNT
- PSB_2D_ALPHA_CTRL
- PSB_2D_ALPHA_ENABLE
- PSB_2D_BLIT_BH
- PSB_2D_CK_COL_CLRMASK
- PSB_2D_CK_COL_MASK
- PSB_2D_CK_COL_SHIFT
- PSB_2D_CK_MASK_CLRMASK
- PSB_2D_CK_MASK_MASK
- PSB_2D_CK_MASK_SHIFT
- PSB_2D_CLIPCOUNT_CLRMASK
- PSB_2D_CLIPCOUNT_MASK
- PSB_2D_CLIPCOUNT_MAX
- PSB_2D_CLIPCOUNT_SHIFT
- PSB_2D_CLIP_BH
- PSB_2D_CLIP_ENABLE
- PSB_2D_CLIP_XMAX_CLRMASK
- PSB_2D_CLIP_XMAX_MASK
- PSB_2D_CLIP_XMAX_SHIFT
- PSB_2D_CLIP_XMIN_CLRMASK
- PSB_2D_CLIP_XMIN_MASK
- PSB_2D_CLIP_XMIN_SHIFT
- PSB_2D_CLIP_YMAX_CLRMASK
- PSB_2D_CLIP_YMAX_MASK
- PSB_2D_CLIP_YMAX_SHIFT
- PSB_2D_CLIP_YMIN_CLRMASK
- PSB_2D_CLIP_YMIN_MASK
- PSB_2D_CLIP_YMIN_SHIFT
- PSB_2D_COPYORDER_BL2TR
- PSB_2D_COPYORDER_BR2TL
- PSB_2D_COPYORDER_CLRMASK
- PSB_2D_COPYORDER_MASK
- PSB_2D_COPYORDER_TL2BR
- PSB_2D_COPYORDER_TR2BL
- PSB_2D_CTRL_BH
- PSB_2D_DSTALPHA_INVERT
- PSB_2D_DSTALPHA_INVERT_CLR
- PSB_2D_DSTALPHA_OP_CLRMASK
- PSB_2D_DSTALPHA_OP_DG
- PSB_2D_DSTALPHA_OP_DST
- PSB_2D_DSTALPHA_OP_GBL
- PSB_2D_DSTALPHA_OP_MASK
- PSB_2D_DSTALPHA_OP_ONE
- PSB_2D_DSTALPHA_OP_SG
- PSB_2D_DSTALPHA_OP_SHIFT
- PSB_2D_DSTALPHA_OP_SRC
- PSB_2D_DSTALPHA_OP_ZERO
- PSB_2D_DSTCK_CLRMASK
- PSB_2D_DSTCK_CTRL
- PSB_2D_DSTCK_DISABLE
- PSB_2D_DSTCK_PASS
- PSB_2D_DSTCK_REJECT
- PSB_2D_DST_0888ARGB
- PSB_2D_DST_1555ARGB
- PSB_2D_DST_332RGB
- PSB_2D_DST_4444ARGB
- PSB_2D_DST_555RGB
- PSB_2D_DST_565RGB
- PSB_2D_DST_8888ARGB
- PSB_2D_DST_8888AYUV
- PSB_2D_DST_ADDR_ALIGNSHIFT
- PSB_2D_DST_ADDR_CLRMASK
- PSB_2D_DST_ADDR_MASK
- PSB_2D_DST_ADDR_SHIFT
- PSB_2D_DST_FORMAT_MASK
- PSB_2D_DST_STRIDE_CLRMASK
- PSB_2D_DST_STRIDE_MASK
- PSB_2D_DST_STRIDE_SHIFT
- PSB_2D_DST_SURF_BH
- PSB_2D_DST_XSIZE_CLRMASK
- PSB_2D_DST_XSIZE_MASK
- PSB_2D_DST_XSIZE_SHIFT
- PSB_2D_DST_XSTART_CLRMASK
- PSB_2D_DST_XSTART_MASK
- PSB_2D_DST_XSTART_SHIFT
- PSB_2D_DST_YSIZE_CLRMASK
- PSB_2D_DST_YSIZE_MASK
- PSB_2D_DST_YSIZE_SHIFT
- PSB_2D_DST_YSTART_CLRMASK
- PSB_2D_DST_YSTART_MASK
- PSB_2D_DST_YSTART_SHIFT
- PSB_2D_FENCE_BH
- PSB_2D_FILLCOLOUR_MASK
- PSB_2D_FILLCOLOUR_SHIFT
- PSB_2D_FLUSH_BH
- PSB_2D_GBLALPHA_CLRMASK
- PSB_2D_GBLALPHA_MASK
- PSB_2D_GBLALPHA_SHIFT
- PSB_2D_MASKOFF_XSTART_MASK
- PSB_2D_MASKOFF_XSTART_SHIFT
- PSB_2D_MASKOFF_YSTART_MASK
- PSB_2D_MASKOFF_YSTART_SHIFT
- PSB_2D_MASK_ADDR_ALIGNSHIFT
- PSB_2D_MASK_ADDR_CLRMASK
- PSB_2D_MASK_ADDR_MASK
- PSB_2D_MASK_ADDR_SHIFT
- PSB_2D_MASK_OFF_BH
- PSB_2D_MASK_STRIDE_CLRMASK
- PSB_2D_MASK_STRIDE_MASK
- PSB_2D_MASK_STRIDE_SHIFT
- PSB_2D_MASK_SURF_BH
- PSB_2D_PATPAL_ADDR_CLRMASK
- PSB_2D_PATPAL_ADDR_MASK
- PSB_2D_PATPAL_ADDR_SHIFT
- PSB_2D_PATPAL_BYTEALIGN
- PSB_2D_PAT_0888ARGB
- PSB_2D_PAT_1555ARGB
- PSB_2D_PAT_1_PAL
- PSB_2D_PAT_2_PAL
- PSB_2D_PAT_332RGB
- PSB_2D_PAT_4444ARGB
- PSB_2D_PAT_4_ALPHA
- PSB_2D_PAT_4_PAL
- PSB_2D_PAT_555RGB
- PSB_2D_PAT_565RGB
- PSB_2D_PAT_8888ARGB
- PSB_2D_PAT_8_ALPHA
- PSB_2D_PAT_8_PAL
- PSB_2D_PAT_ADDR_ALIGNSHIFT
- PSB_2D_PAT_ADDR_CLRMASK
- PSB_2D_PAT_ADDR_MASK
- PSB_2D_PAT_ADDR_SHIFT
- PSB_2D_PAT_BH
- PSB_2D_PAT_CLRMASK
- PSB_2D_PAT_FORMAT_MASK
- PSB_2D_PAT_HEIGHT_MASK
- PSB_2D_PAT_HEIGHT_SHIFT
- PSB_2D_PAT_MASK
- PSB_2D_PAT_PAL_BH
- PSB_2D_PAT_STRIDE_CLRMASK
- PSB_2D_PAT_STRIDE_MASK
- PSB_2D_PAT_STRIDE_SHIFT
- PSB_2D_PAT_SURF_BH
- PSB_2D_PAT_WIDTH_MASK
- PSB_2D_PAT_WIDTH_SHIFT
- PSB_2D_PAT_XSTART_MASK
- PSB_2D_PAT_XSTART_SHIFT
- PSB_2D_PAT_YSTART_MASK
- PSB_2D_PAT_YSTART_SHIFT
- PSB_2D_PRE_MULTIPLICATION_CLRMASK
- PSB_2D_PRE_MULTIPLICATION_ENABLE
- PSB_2D_RESERVED1_BH
- PSB_2D_RESERVED2_BH
- PSB_2D_ROP3A_CLRMASK
- PSB_2D_ROP3A_MASK
- PSB_2D_ROP3A_SHIFT
- PSB_2D_ROP3B_CLRMASK
- PSB_2D_ROP3B_MASK
- PSB_2D_ROP3B_SHIFT
- PSB_2D_ROP3_BLACKNESS
- PSB_2D_ROP3_DST
- PSB_2D_ROP3_PAT
- PSB_2D_ROP3_PATCOPY
- PSB_2D_ROP3_SRC
- PSB_2D_ROP3_SRCCOPY
- PSB_2D_ROP3_WHITENESS
- PSB_2D_ROP4_MASK
- PSB_2D_ROT_180DEGS
- PSB_2D_ROT_270DEGS
- PSB_2D_ROT_90DEGS
- PSB_2D_ROT_CLRMASK
- PSB_2D_ROT_MASK
- PSB_2D_ROT_NONE
- PSB_2D_SIZE
- PSB_2D_SRCALPHA_INVERT
- PSB_2D_SRCALPHA_INVERT_CLR
- PSB_2D_SRCALPHA_OP_CLRMASK
- PSB_2D_SRCALPHA_OP_DG
- PSB_2D_SRCALPHA_OP_DST
- PSB_2D_SRCALPHA_OP_GBL
- PSB_2D_SRCALPHA_OP_MASK
- PSB_2D_SRCALPHA_OP_ONE
- PSB_2D_SRCALPHA_OP_SG
- PSB_2D_SRCALPHA_OP_SHIFT
- PSB_2D_SRCALPHA_OP_SRC
- PSB_2D_SRCALPHA_OP_ZERO
- PSB_2D_SRCCK_CLRMASK
- PSB_2D_SRCCK_CTRL
- PSB_2D_SRCCK_DISABLE
- PSB_2D_SRCCK_PASS
- PSB_2D_SRCCK_REJECT
- PSB_2D_SRCOFF_XSTART_MASK
- PSB_2D_SRCOFF_XSTART_SHIFT
- PSB_2D_SRCOFF_YSTART_MASK
- PSB_2D_SRCOFF_YSTART_SHIFT
- PSB_2D_SRCPAL_ADDR_CLRMASK
- PSB_2D_SRCPAL_ADDR_MASK
- PSB_2D_SRCPAL_ADDR_SHIFT
- PSB_2D_SRCPAL_BYTEALIGN
- PSB_2D_SRC_0888ARGB
- PSB_2D_SRC_1555ARGB
- PSB_2D_SRC_1555ARGB_LOOKUP
- PSB_2D_SRC_1_PAL
- PSB_2D_SRC_2_PAL
- PSB_2D_SRC_332RGB
- PSB_2D_SRC_4444ARGB
- PSB_2D_SRC_4_ALPHA
- PSB_2D_SRC_4_PAL
- PSB_2D_SRC_555RGB
- PSB_2D_SRC_565RGB
- PSB_2D_SRC_8888ARGB
- PSB_2D_SRC_8888UYVY
- PSB_2D_SRC_8_ALPHA
- PSB_2D_SRC_8_PAL
- PSB_2D_SRC_ADDR_ALIGNSHIFT
- PSB_2D_SRC_ADDR_CLRMASK
- PSB_2D_SRC_ADDR_MASK
- PSB_2D_SRC_ADDR_SHIFT
- PSB_2D_SRC_FORMAT_MASK
- PSB_2D_SRC_OFF_BH
- PSB_2D_SRC_PAL_BH
- PSB_2D_SRC_RESERVED
- PSB_2D_SRC_STRIDE_CLRMASK
- PSB_2D_SRC_STRIDE_MASK
- PSB_2D_SRC_STRIDE_SHIFT
- PSB_2D_SRC_SURF_BH
- PSB_2D_USE_FILL
- PSB_2D_USE_PAT
- PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK
- PSB_2D_ZERO_SOURCE_ALPHA_ENABLE
- PSB_APMBA
- PSB_APM_CMD
- PSB_APM_STS
- PSB_AUX_RESOURCE
- PSB_BACKLIGHT_PWM_CTL_SHIFT
- PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR
- PSB_BLC_MAX_PWM_REG_FREQ
- PSB_BLC_MIN_PWM_REG_FREQ
- PSB_BLC_PWM_PRECISION_FACTOR
- PSB_BSM
- PSB_COMM_2D
- PSB_COMM_3D
- PSB_COMM_FW
- PSB_COMM_HP
- PSB_COMM_TA
- PSB_COMM_USER_IRQ
- PSB_COMM_USER_IRQ_LOST
- PSB_CR_2D_BLIT_STATUS
- PSB_CR_2D_SOCIF
- PSB_CR_BIF_3D_REQ_BASE
- PSB_CR_BIF_BANK0
- PSB_CR_BIF_BANK1
- PSB_CR_BIF_CTRL
- PSB_CR_BIF_DIR_LIST_BASE0
- PSB_CR_BIF_DIR_LIST_BASE1
- PSB_CR_BIF_FAULT
- PSB_CR_BIF_INT_STAT
- PSB_CR_BIF_TWOD_REQ_BASE
- PSB_CR_CLKGATECTL
- PSB_CR_CORE_ID
- PSB_CR_CORE_REVISION
- PSB_CR_DESIGNER_REV_FIELD1
- PSB_CR_DESIGNER_REV_FIELD2
- PSB_CR_EVENT_HOST_CLEAR
- PSB_CR_EVENT_HOST_CLEAR2
- PSB_CR_EVENT_HOST_ENABLE
- PSB_CR_EVENT_HOST_ENABLE2
- PSB_CR_EVENT_KICK
- PSB_CR_EVENT_KICKER
- PSB_CR_EVENT_STATUS
- PSB_CR_EVENT_STATUS2
- PSB_CR_PDS_EXEC_BASE
- PSB_CR_SOFT_RESET
- PSB_CR_USE_CODE_BASE
- PSB_CR_USE_CODE_BASE0
- PSB_CR_USE_CODE_BASE1
- PSB_CR_USE_CODE_BASE10
- PSB_CR_USE_CODE_BASE11
- PSB_CR_USE_CODE_BASE12
- PSB_CR_USE_CODE_BASE13
- PSB_CR_USE_CODE_BASE14
- PSB_CR_USE_CODE_BASE15
- PSB_CR_USE_CODE_BASE2
- PSB_CR_USE_CODE_BASE3
- PSB_CR_USE_CODE_BASE4
- PSB_CR_USE_CODE_BASE5
- PSB_CR_USE_CODE_BASE6
- PSB_CR_USE_CODE_BASE7
- PSB_CR_USE_CODE_BASE8
- PSB_CR_USE_CODE_BASE9
- PSB_D_DBI_BF
- PSB_D_ENTRY
- PSB_D_GENERAL
- PSB_D_HV
- PSB_D_INIT
- PSB_D_IRQ
- PSB_D_MSVDX
- PSB_D_PM
- PSB_D_REG
- PSB_D_RENDER
- PSB_D_TOPAZ
- PSB_GATT_RESOURCE
- PSB_GMCH_CTRL
- PSB_GTT_RESOURCE
- PSB_HIGH_REG_OFFS
- PSB_HWSTAM
- PSB_ID_STRING
- PSB_ID_STRING_LEN
- PSB_INSTPM
- PSB_INT_ENABLE_R
- PSB_INT_IDENTITY_R
- PSB_INT_MASK_R
- PSB_LANE0
- PSB_LANE1
- PSB_LANE2
- PSB_LANE3
- PSB_LID_DELAY
- PSB_LOW_REG_OFFS
- PSB_LPC_GBA
- PSB_MASK
- PSB_MAX_RELOC_PAGES
- PSB_MMIO_RESOURCE
- PSB_MMU_CACHED_MEMORY
- PSB_MMU_RO_MEMORY
- PSB_MMU_WO_MEMORY
- PSB_MSVDX_CLOCKGATING
- PSB_NUM_HW_SCENES
- PSB_NUM_PIPE
- PSB_NUM_VBLANKS
- PSB_OSPMBA
- PSB_PCIx_MSI_ADDR_LOC
- PSB_PCIx_MSI_DATA_LOC
- PSB_PDE_MASK
- PSB_PDE_SHIFT
- PSB_PGETBL_CTL
- PSB_PMPOLICY_CLOCKGATING
- PSB_PMPOLICY_NOPM
- PSB_PMPOLICY_POWERDOWN
- PSB_PMSTATE_CLOCKGATED
- PSB_PMSTATE_POWERDOWN
- PSB_PMSTATE_POWERUP
- PSB_PM_SSC
- PSB_PM_SSS
- PSB_PTE_CACHED
- PSB_PTE_RO
- PSB_PTE_SHIFT
- PSB_PTE_VALID
- PSB_PTE_WO
- PSB_PUNIT_PORT
- PSB_PWRGT_DISPLAY_MASK
- PSB_PWRGT_GFX_D0
- PSB_PWRGT_GFX_D3
- PSB_PWRGT_GFX_MASK
- PSB_PWRGT_GFX_MASK_B0
- PSB_PWRGT_GFX_OFF
- PSB_PWRGT_GFX_ON
- PSB_PWRGT_GL3_MASK
- PSB_PWRGT_VID_DEC_MASK
- PSB_PWRGT_VID_ENC_MASK
- PSB_PWR_STATE_OFF
- PSB_PWR_STATE_ON
- PSB_RASTER
- PSB_RASTER_BLOCK
- PSB_RETURN
- PSB_RMSVDX32
- PSB_RSGX32
- PSB_RVDC32
- PSB_SCENE_HW_COOKIE_SIZE
- PSB_SGX_2D_SLAVE_PORT
- PSB_SGX_OFFSET
- PSB_SGX_SIZE
- PSB_TA
- PSB_TA_MEM_HW_COOKIE_SIZE
- PSB_TOPAZ_CLOCKGATING
- PSB_TT_PRIV0_LIMIT
- PSB_TT_PRIV0_PLIMIT
- PSB_UIRQ_FIRE_RASTER_REPLY
- PSB_UIRQ_FIRE_TA_REPLY
- PSB_UIRQ_OOM_REPLY
- PSB_UIRQ_VISTEST
- PSB_USE_OFFSET_MASK
- PSB_USE_OFFSET_SIZE
- PSB_VDC_OFFSET
- PSB_VDC_SIZE
- PSB_VERSION_1_4
- PSB_WATCHDOG_DELAY
- PSB_WMSVDX32
- PSB_WSGX32
- PSB_WVDC32
- PSC
- PSC0_0
- PSC0_1
- PSC0_NAF
- PSC0_VIO
- PSC10_0
- PSC10_1
- PSC11_0
- PSC11_1
- PSC11_PSC10_FN1
- PSC11_PSC10_FN2
- PSC11_PSC10_FN3
- PSC11_SIOF1_SS2
- PSC11_SIUAILR
- PSC12_0
- PSC12_1
- PSC12_SIOF1_SS1
- PSC12_SIUAIBT
- PSC13_0
- PSC13_1
- PSC13_PSC12_FN1
- PSC13_PSC12_FN2
- PSC13_SIOF1_SYNC
- PSC13_SIUAOLR
- PSC14_0
- PSC14_1
- PSC14_SIOF1_SCK
- PSC14_SIUAOBT
- PSC15_0
- PSC15_1
- PSC15_PSC14_FN1
- PSC15_PSC14_FN2
- PSC15_SIOF1_RXD
- PSC15_SIUAISLD
- PSC1_0
- PSC1_1
- PSC1_RESET
- PSC1_SDATA_OUT
- PSC1_SYNC
- PSC2_0
- PSC2_1
- PSC2_RESET
- PSC2_SDATA_OUT
- PSC2_SYNC
- PSC3_SOURCE_BASE
- PSC4_0
- PSC4_1
- PSC4_SOURCE_BASE
- PSC5_0
- PSC5_1
- PSC5_SOURCE_BASE
- PSC6_0
- PSC6_1
- PSC6_SOURCE_BASE
- PSC724_DEVICE_DESC
- PSC724_SPI_CLK
- PSC724_SPI_DATA
- PSC724_SPI_DELAY
- PSC724_SPI_LOAD
- PSC724_SPI_MASK
- PSC7_0
- PSC7_1
- PSC7_PSC6_FN1
- PSC7_PSC6_FN2
- PSC7_PSC6_FN3
- PSC8_0
- PSC8_1
- PSC9_0
- PSC9_1
- PSC9_PSC8_FN1
- PSC9_PSC8_FN2
- PSCADESC
- PSCADESC_EX
- PSCALE_BMEM_ADDR
- PSCALE_BMEM_DAT
- PSCALE_CTRL
- PSCALE_RST
- PSCFG_AUTOSLEEP
- PSCFG_BBPSPROG
- PSCFG_PHILIPMD
- PSCFG_SLEEPSYN
- PSCFG_WAKECALEN
- PSCFG_WAKESYN
- PSCFG_WAKETMREN
- PSCHED_NS2TICKS
- PSCHED_PASTPERFECT
- PSCHED_SHIFT
- PSCHED_TICKS2NS
- PSCHED_TICKS_PER_SEC
- PSCI_0_2_64BIT
- PSCI_0_2_AFFINITY_LEVEL_OFF
- PSCI_0_2_AFFINITY_LEVEL_ON
- PSCI_0_2_AFFINITY_LEVEL_ON_PENDING
- PSCI_0_2_FN
- PSCI_0_2_FN64
- PSCI_0_2_FN64_AFFINITY_INFO
- PSCI_0_2_FN64_BASE
- PSCI_0_2_FN64_CPU_ON
- PSCI_0_2_FN64_CPU_SUSPEND
- PSCI_0_2_FN64_MIGRATE
- PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU
- PSCI_0_2_FN_AFFINITY_INFO
- PSCI_0_2_FN_BASE
- PSCI_0_2_FN_CPU_OFF
- PSCI_0_2_FN_CPU_ON
- PSCI_0_2_FN_CPU_SUSPEND
- PSCI_0_2_FN_MIGRATE
- PSCI_0_2_FN_MIGRATE_INFO_TYPE
- PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
- PSCI_0_2_FN_PSCI_VERSION
- PSCI_0_2_FN_SYSTEM_OFF
- PSCI_0_2_FN_SYSTEM_RESET
- PSCI_0_2_POWER_STATE_AFFL_MASK
- PSCI_0_2_POWER_STATE_AFFL_SHIFT
- PSCI_0_2_POWER_STATE_ID_MASK
- PSCI_0_2_POWER_STATE_ID_SHIFT
- PSCI_0_2_POWER_STATE_MASK
- PSCI_0_2_POWER_STATE_TYPE_MASK
- PSCI_0_2_POWER_STATE_TYPE_SHIFT
- PSCI_0_2_TOS_MP
- PSCI_0_2_TOS_UP_MIGRATE
- PSCI_0_2_TOS_UP_NO_MIGRATE
- PSCI_1_0_EXT_POWER_STATE_ID_MASK
- PSCI_1_0_EXT_POWER_STATE_ID_SHIFT
- PSCI_1_0_EXT_POWER_STATE_MASK
- PSCI_1_0_EXT_POWER_STATE_TYPE_MASK
- PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT
- PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK
- PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT
- PSCI_1_0_FN64_SYSTEM_SUSPEND
- PSCI_1_0_FN_PSCI_FEATURES
- PSCI_1_0_FN_SET_SUSPEND_MODE
- PSCI_1_0_FN_SYSTEM_SUSPEND
- PSCI_1_0_OS_INITIATED
- PSCI_1_0_SUSPEND_MODE_OSI
- PSCI_1_0_SUSPEND_MODE_PC
- PSCI_1_1_FN64_SYSTEM_RESET2
- PSCI_1_1_FN_SYSTEM_RESET2
- PSCI_CONDUIT_HVC
- PSCI_CONDUIT_NONE
- PSCI_CONDUIT_SMC
- PSCI_FN_CPU_OFF
- PSCI_FN_CPU_ON
- PSCI_FN_CPU_SUSPEND
- PSCI_FN_MAX
- PSCI_FN_MIGRATE
- PSCI_FN_NATIVE
- PSCI_POWER_STATE_TYPE_POWER_DOWN
- PSCI_POWER_STATE_TYPE_STANDBY
- PSCI_RET_ALREADY_ON
- PSCI_RET_DENIED
- PSCI_RET_DISABLED
- PSCI_RET_INTERNAL_FAILURE
- PSCI_RET_INVALID_ADDRESS
- PSCI_RET_INVALID_PARAMS
- PSCI_RET_NOT_PRESENT
- PSCI_RET_NOT_SUPPORTED
- PSCI_RET_ON_PENDING
- PSCI_RET_SUCCESS
- PSCI_VERSION
- PSCI_VERSION_MAJOR
- PSCI_VERSION_MAJOR_MASK
- PSCI_VERSION_MAJOR_SHIFT
- PSCI_VERSION_MINOR
- PSCI_VERSION_MINOR_MASK
- PSCR
- PSCRATCH0
- PSCRATCH1
- PSCRATCH2
- PSCRATCH3
- PSCRATCH4
- PSCR_ACRSTX
- PSCSI_DEFAULT_QUEUEDEPTH
- PSCSI_DEV
- PSCSI_VERSION
- PSCSR0
- PSCSR1
- PSCSR2
- PSCSR3
- PSCTL_ALBCN
- PSCTL_GO2DOZE
- PSCTL_LNBCN
- PSCTL_PS
- PSCTL_PSEN
- PSCTL_WAKEDONE
- PSC_5125
- PSC_AC97CDC_ID
- PSC_AC97CDC_ID_MASK
- PSC_AC97CDC_INDX
- PSC_AC97CDC_INDX_MASK
- PSC_AC97CDC_OFFSET
- PSC_AC97CDC_RD
- PSC_AC97CFG_DD_DISABLE
- PSC_AC97CFG_DE_ENABLE
- PSC_AC97CFG_GET_LEN
- PSC_AC97CFG_GE_ENABLE
- PSC_AC97CFG_LEN_MASK
- PSC_AC97CFG_OFFSET
- PSC_AC97CFG_RT_FIFO1
- PSC_AC97CFG_RT_FIFO2
- PSC_AC97CFG_RT_FIFO4
- PSC_AC97CFG_RT_FIFO8
- PSC_AC97CFG_RT_MASK
- PSC_AC97CFG_RXSLOT_ENA
- PSC_AC97CFG_RXSLOT_MASK
- PSC_AC97CFG_SET_LEN
- PSC_AC97CFG_SE_ENABLE
- PSC_AC97CFG_TT_FIFO1
- PSC_AC97CFG_TT_FIFO2
- PSC_AC97CFG_TT_FIFO4
- PSC_AC97CFG_TT_FIFO8
- PSC_AC97CFG_TT_MASK
- PSC_AC97CFG_TXSLOT_ENA
- PSC_AC97CFG_TXSLOT_MASK
- PSC_AC97EVNT_CD
- PSC_AC97EVNT_GR
- PSC_AC97EVNT_OFFSET
- PSC_AC97EVNT_RD
- PSC_AC97EVNT_RO
- PSC_AC97EVNT_RR
- PSC_AC97EVNT_RU
- PSC_AC97EVNT_TD
- PSC_AC97EVNT_TO
- PSC_AC97EVNT_TR
- PSC_AC97EVNT_TU
- PSC_AC97GPI_OFFSET
- PSC_AC97GPO_OFFSET
- PSC_AC97MSK_ALLMASK
- PSC_AC97MSK_CD
- PSC_AC97MSK_GR
- PSC_AC97MSK_OFFSET
- PSC_AC97MSK_RD
- PSC_AC97MSK_RO
- PSC_AC97MSK_RR
- PSC_AC97MSK_RU
- PSC_AC97MSK_TD
- PSC_AC97MSK_TO
- PSC_AC97MSK_TR
- PSC_AC97MSK_TU
- PSC_AC97PCR_OFFSET
- PSC_AC97PCR_RC
- PSC_AC97PCR_RP
- PSC_AC97PCR_RS
- PSC_AC97PCR_TC
- PSC_AC97PCR_TP
- PSC_AC97PCR_TS
- PSC_AC97RST_OFFSET
- PSC_AC97RST_RST
- PSC_AC97RST_SNC
- PSC_AC97STAT_CB
- PSC_AC97STAT_CP
- PSC_AC97STAT_CR
- PSC_AC97STAT_DI
- PSC_AC97STAT_DR
- PSC_AC97STAT_OFFSET
- PSC_AC97STAT_RB
- PSC_AC97STAT_RE
- PSC_AC97STAT_RF
- PSC_AC97STAT_RR
- PSC_AC97STAT_SR
- PSC_AC97STAT_TB
- PSC_AC97STAT_TE
- PSC_AC97STAT_TF
- PSC_AC97STAT_TR
- PSC_AC97TXRX_OFFSET
- PSC_ADDR_BASE
- PSC_BASE
- PSC_CMD_BASE
- PSC_CM_RESET
- PSC_CTL_BASE
- PSC_CTRL
- PSC_CTRL_DISABLE
- PSC_CTRL_ENABLE
- PSC_CTRL_OFFSET
- PSC_CTRL_SUSPEND
- PSC_CURRENT_IN
- PSC_CURRENT_IN_L
- PSC_CURRENT_OUT
- PSC_DATA_VL_DISABLE
- PSC_DATA_VL_ENABLE
- PSC_ENETRD_ADDR
- PSC_ENETRD_CMD
- PSC_ENETRD_CTL
- PSC_ENETRD_LEN
- PSC_ENETWR_ADDR
- PSC_ENETWR_CMD
- PSC_ENETWR_CTL
- PSC_ENETWR_LEN
- PSC_FAN
- PSC_FDC_ADDR
- PSC_FDC_CMD
- PSC_FDC_CTL
- PSC_FDC_LEN
- PSC_GLOBAL_DISABLE
- PSC_GLOBAL_ENABLE
- PSC_GLOBAL_VLARB_DISABLE
- PSC_GLOBAL_VLARB_ENABLE
- PSC_I2SCFG_BI
- PSC_I2SCFG_BUF
- PSC_I2SCFG_DD_DISABLE
- PSC_I2SCFG_DE_ENABLE
- PSC_I2SCFG_DIV16
- PSC_I2SCFG_DIV2
- PSC_I2SCFG_DIV4
- PSC_I2SCFG_DIV8
- PSC_I2SCFG_DIV_MASK
- PSC_I2SCFG_GET_LEN
- PSC_I2SCFG_LB
- PSC_I2SCFG_MLF
- PSC_I2SCFG_MLJ
- PSC_I2SCFG_MS
- PSC_I2SCFG_OFFSET
- PSC_I2SCFG_RT_FIFO1
- PSC_I2SCFG_RT_FIFO2
- PSC_I2SCFG_RT_FIFO4
- PSC_I2SCFG_RT_FIFO8
- PSC_I2SCFG_RT_MASK
- PSC_I2SCFG_SET_LEN
- PSC_I2SCFG_SET_WS
- PSC_I2SCFG_TT_FIFO1
- PSC_I2SCFG_TT_FIFO2
- PSC_I2SCFG_TT_FIFO4
- PSC_I2SCFG_TT_FIFO8
- PSC_I2SCFG_TT_MASK
- PSC_I2SCFG_WI
- PSC_I2SCFG_WS
- PSC_I2SCFG_WS_MASK
- PSC_I2SCFG_XM
- PSC_I2SEVENT_OFFSET
- PSC_I2SEVNT_RD
- PSC_I2SEVNT_RO
- PSC_I2SEVNT_RR
- PSC_I2SEVNT_RU
- PSC_I2SEVNT_TD
- PSC_I2SEVNT_TO
- PSC_I2SEVNT_TR
- PSC_I2SEVNT_TU
- PSC_I2SMASK_OFFSET
- PSC_I2SMSK_ALLMASK
- PSC_I2SMSK_RD
- PSC_I2SMSK_RO
- PSC_I2SMSK_RR
- PSC_I2SMSK_RU
- PSC_I2SMSK_TD
- PSC_I2SMSK_TO
- PSC_I2SMSK_TR
- PSC_I2SMSK_TU
- PSC_I2SPCR_OFFSET
- PSC_I2SPCR_RC
- PSC_I2SPCR_RP
- PSC_I2SPCR_RS
- PSC_I2SPCR_TC
- PSC_I2SPCR_TP
- PSC_I2SPCR_TS
- PSC_I2SRXTX_OFFSET
- PSC_I2SSTAT_DI
- PSC_I2SSTAT_DR
- PSC_I2SSTAT_OFFSET
- PSC_I2SSTAT_RB
- PSC_I2SSTAT_RE
- PSC_I2SSTAT_RF
- PSC_I2SSTAT_RR
- PSC_I2SSTAT_SR
- PSC_I2SSTAT_TB
- PSC_I2SSTAT_TE
- PSC_I2SSTAT_TF
- PSC_I2SSTAT_TR
- PSC_I2SUDF_OFFSET
- PSC_I2S_FORMATS
- PSC_I2S_RATES
- PSC_LEN_BASE
- PSC_MYSTERY
- PSC_NTG
- PSC_NTPC
- PSC_NUM_CLASSES
- PSC_POWER
- PSC_POWER_L
- PSC_PP_DEF
- PSC_PWM
- PSC_SCCATX_ADDR
- PSC_SCCATX_CMD
- PSC_SCCATX_CTL
- PSC_SCCATX_LEN
- PSC_SCCA_ADDR
- PSC_SCCA_CMD
- PSC_SCCA_CTL
- PSC_SCCA_LEN
- PSC_SCCB_ADDR
- PSC_SCCB_CMD
- PSC_SCCB_CTL
- PSC_SCCB_LEN
- PSC_SCSI_ADDR
- PSC_SCSI_CMD
- PSC_SCSI_CTL
- PSC_SCSI_LEN
- PSC_SEL
- PSC_SEL_CLK_EXTCLK
- PSC_SEL_CLK_INTCLK
- PSC_SEL_CLK_MASK
- PSC_SEL_CLK_SERCLK
- PSC_SEL_OFFSET
- PSC_SEL_PS_AC97MODE
- PSC_SEL_PS_DISABLED
- PSC_SEL_PS_I2SMODE
- PSC_SEL_PS_MASK
- PSC_SEL_PS_SMBUSMODE
- PSC_SEL_PS_SPIMODE
- PSC_SET0
- PSC_SET1
- PSC_SMBCFG
- PSC_SMBCFG_DD_DISABLE
- PSC_SMBCFG_DE_ENABLE
- PSC_SMBCFG_DIV16
- PSC_SMBCFG_DIV2
- PSC_SMBCFG_DIV4
- PSC_SMBCFG_DIV8
- PSC_SMBCFG_GCE
- PSC_SMBCFG_RT_FIFO1
- PSC_SMBCFG_RT_FIFO2
- PSC_SMBCFG_RT_FIFO4
- PSC_SMBCFG_RT_FIFO8
- PSC_SMBCFG_RT_MASK
- PSC_SMBCFG_SET_DIV
- PSC_SMBCFG_SET_SLV
- PSC_SMBCFG_SFM
- PSC_SMBCFG_TT_FIFO1
- PSC_SMBCFG_TT_FIFO2
- PSC_SMBCFG_TT_FIFO4
- PSC_SMBCFG_TT_FIFO8
- PSC_SMBCFG_TT_MASK
- PSC_SMBEVNT
- PSC_SMBEVNT_AL
- PSC_SMBEVNT_ALLCLR
- PSC_SMBEVNT_AN
- PSC_SMBEVNT_DN
- PSC_SMBEVNT_MD
- PSC_SMBEVNT_RO
- PSC_SMBEVNT_RR
- PSC_SMBEVNT_RU
- PSC_SMBEVNT_SD
- PSC_SMBEVNT_TO
- PSC_SMBEVNT_TR
- PSC_SMBEVNT_TU
- PSC_SMBMSK
- PSC_SMBMSK_AL
- PSC_SMBMSK_ALLMASK
- PSC_SMBMSK_AN
- PSC_SMBMSK_DN
- PSC_SMBMSK_MD
- PSC_SMBMSK_RO
- PSC_SMBMSK_RR
- PSC_SMBMSK_RU
- PSC_SMBMSK_SD
- PSC_SMBMSK_TO
- PSC_SMBMSK_TR
- PSC_SMBMSK_TU
- PSC_SMBPCR
- PSC_SMBPCR_DC
- PSC_SMBPCR_MS
- PSC_SMBSTAT
- PSC_SMBSTAT_BB
- PSC_SMBSTAT_DI
- PSC_SMBSTAT_DR
- PSC_SMBSTAT_MB
- PSC_SMBSTAT_RE
- PSC_SMBSTAT_RF
- PSC_SMBSTAT_RR
- PSC_SMBSTAT_SB
- PSC_SMBSTAT_SR
- PSC_SMBSTAT_TE
- PSC_SMBSTAT_TF
- PSC_SMBSTAT_TR
- PSC_SMBTMR
- PSC_SMBTMR_SET_CH
- PSC_SMBTMR_SET_CL
- PSC_SMBTMR_SET_PS
- PSC_SMBTMR_SET_PU
- PSC_SMBTMR_SET_SH
- PSC_SMBTMR_SET_SU
- PSC_SMBTMR_SET_TH
- PSC_SMBTXRX
- PSC_SMBTXRX_DATAMASK
- PSC_SMBTXRX_RSR
- PSC_SMBTXRX_STP
- PSC_SND_BITS2GO
- PSC_SND_CTL
- PSC_SND_HUH3
- PSC_SND_HUH4
- PSC_SND_HUH5
- PSC_SND_INADDR
- PSC_SND_LEN
- PSC_SND_OUTADDR
- PSC_SND_SOURCE
- PSC_SND_STATUS1
- PSC_SND_STATUS2
- PSC_SPICFG_BI
- PSC_SPICFG_CDE
- PSC_SPICFG_CGE
- PSC_SPICFG_CLR_BAUD
- PSC_SPICFG_CLR_LEN
- PSC_SPICFG_DD_DISABLE
- PSC_SPICFG_DE_ENABLE
- PSC_SPICFG_DIV16
- PSC_SPICFG_DIV2
- PSC_SPICFG_DIV4
- PSC_SPICFG_DIV8
- PSC_SPICFG_LB
- PSC_SPICFG_MLF
- PSC_SPICFG_MO
- PSC_SPICFG_PSE
- PSC_SPICFG_RT_FIFO1
- PSC_SPICFG_RT_FIFO2
- PSC_SPICFG_RT_FIFO4
- PSC_SPICFG_RT_FIFO8
- PSC_SPICFG_RT_MASK
- PSC_SPICFG_SET_BAUD
- PSC_SPICFG_SET_DIV
- PSC_SPICFG_SET_LEN
- PSC_SPICFG_TT_FIFO1
- PSC_SPICFG_TT_FIFO2
- PSC_SPICFG_TT_FIFO4
- PSC_SPICFG_TT_FIFO8
- PSC_SPICFG_TT_MASK
- PSC_SPIEVNT_MD
- PSC_SPIEVNT_MM
- PSC_SPIEVNT_RO
- PSC_SPIEVNT_RR
- PSC_SPIEVNT_RU
- PSC_SPIEVNT_SD
- PSC_SPIEVNT_TO
- PSC_SPIEVNT_TR
- PSC_SPIEVNT_TU
- PSC_SPIMSK_ALLMASK
- PSC_SPIMSK_MD
- PSC_SPIMSK_MM
- PSC_SPIMSK_RO
- PSC_SPIMSK_RR
- PSC_SPIMSK_RU
- PSC_SPIMSK_SD
- PSC_SPIMSK_TO
- PSC_SPIMSK_TR
- PSC_SPIMSK_TU
- PSC_SPIPCR_MS
- PSC_SPIPCR_RC
- PSC_SPIPCR_SP
- PSC_SPIPCR_SS
- PSC_SPIPCR_TC
- PSC_SPISTAT_DI
- PSC_SPISTAT_DR
- PSC_SPISTAT_MB
- PSC_SPISTAT_RE
- PSC_SPISTAT_RF
- PSC_SPISTAT_RR
- PSC_SPISTAT_SB
- PSC_SPISTAT_SR
- PSC_SPISTAT_TE
- PSC_SPISTAT_TF
- PSC_SPISTAT_TR
- PSC_SPITXRX_LC
- PSC_SPITXRX_SR
- PSC_STATE_DISABLE
- PSC_STATE_ENABLE
- PSC_STATE_SWRSTDISABLE
- PSC_STATE_SYNCRST
- PSC_STREAM_NAME_LEN
- PSC_TEMPERATURE
- PSC_VOLTAGE_IN
- PSC_VOLTAGE_OUT
- PSD
- PSD0_0
- PSD0_1
- PSD0_DV
- PSD0_LCDD19_LCDD0
- PSD10_0
- PSD10_1
- PSD10_LCDLCLK
- PSD10_VIO_D0
- PSD11_0
- PSD11_1
- PSD11_PSD10_FN1
- PSD11_PSD10_FN2
- PSD11_PSD10_FN3
- PSD11_SCIF1
- PSD11_VIO
- PSD12_0
- PSD12_1
- PSD12_SCIF1
- PSD12_VIO
- PSD13_0
- PSD13_1
- PSD13_PSD12_FN1
- PSD13_PSD12_FN2
- PSD13_SCIF2
- PSD13_VIO
- PSD14_0
- PSD14_1
- PSD15_0
- PSD15_1
- PSD15_PSD14_FN1
- PSD15_PSD14_FN2
- PSD1_0
- PSD1_1
- PSD1_PSD0_FN1
- PSD1_PSD0_FN2
- PSD2_0
- PSD2_1
- PSD2_LCDDON
- PSD2_LCDDON2
- PSD3_0
- PSD3_1
- PSD3_LCDVEPWC2_LCDVCPWC2
- PSD3_LCDVEPWC_LCDVCPWC
- PSD3_PSD2_FN1
- PSD3_PSD2_FN2
- PSD4256G6V
- PSD4_0
- PSD4_1
- PSD5_0
- PSD5_1
- PSD5_CS6B_CE1B
- PSD5_LCDCS2
- PSD5_PSD4_FN1
- PSD5_PSD4_FN2
- PSD6_0
- PSD6_1
- PSD6_SCIF0_CTS
- PSD6_SIUAISPD
- PSD7_0
- PSD7_1
- PSD7_PSD6_FN1
- PSD7_PSD6_FN2
- PSD7_SCIF0_RTS
- PSD7_SIUAOSPD
- PSD8_0
- PSD8_1
- PSD8_SCIF0_SCK
- PSD8_TPUTO
- PSD9_0
- PSD9_1
- PSD9_PSD8_FN1
- PSD9_PSD8_FN2
- PSD9_SIOMCK_SIUMCKB
- PSD9_SIUFCKB
- PSDM_REG_DBG_DWORD_ENABLE
- PSDM_REG_DBG_FORCE_FRAME
- PSDM_REG_DBG_FORCE_VALID
- PSDM_REG_DBG_SELECT
- PSDM_REG_DBG_SHIFT
- PSDM_REG_ENABLE_IN1
- PSDR
- PSDR_Flt
- PSDR_OutL
- PSDUNIT_CLKGATE_DIS
- PSD_CHM
- PSD_CHMIN
- PSD_POOL_SIZE
- PSD_RESCAN
- PSD_SCAN_INTERVAL
- PSD_TH2
- PSE
- PSE0_0
- PSE0_1
- PSE0_NAF0
- PSE0_VIO_D8
- PSE10_0
- PSE10_1
- PSE11_0
- PSE11_1
- PSE11_SIUFCKA
- PSE11_SIUMCKA_SIOF1_MCK
- PSE12_0
- PSE12_1
- PSE12_DACK
- PSE12_LCDVSYN2
- PSE13_0
- PSE13_1
- PSE13_SIOF0_RXD_IRDA_IN
- PSE13_TS_SDAT
- PSE14_0
- PSE14_1
- PSE14_SIM_CLK
- PSE14_SIOF0_TXD_IRDA_OUT
- PSE15_0
- PSE15_1
- PSE15_SIM_D
- PSE15_SIOF0_MCK_IRQ3
- PSE1_0
- PSE1_1
- PSE1_NAF1
- PSE1_VIO_D9
- PSE2_0
- PSE2_1
- PSE2_NAF2
- PSE2_VIO_D10
- PSE3_0
- PSE3_1
- PSE3_FLCTL
- PSE3_VIO
- PSE4_0
- PSE4_1
- PSE5_0
- PSE5_1
- PSE6_0
- PSE6_1
- PSE7_0
- PSE7_1
- PSE8_0
- PSE8_1
- PSE9_0
- PSE9_1
- PSECS_PER_SEC
- PSEC_PER_SEC
- PSEC_TO_MSEC
- PSEC_TO_NSEC
- PSEL
- PSELA
- PSELA_11_10_00
- PSELA_11_10_01
- PSELA_11_10_10
- PSELA_13_12_00
- PSELA_13_12_10
- PSELA_15_14_00
- PSELA_15_14_10
- PSELA_1_0_00
- PSELA_1_0_01
- PSELA_1_0_10
- PSELA_3_2_00
- PSELA_3_2_01
- PSELA_3_2_10
- PSELA_3_2_11
- PSELA_5_4_00
- PSELA_5_4_01
- PSELA_5_4_10
- PSELA_5_4_11
- PSELA_7_6_00
- PSELA_7_6_01
- PSELA_7_6_10
- PSELA_9_8_00
- PSELA_9_8_01
- PSELA_9_8_10
- PSELB_11_10_00
- PSELB_11_10_01
- PSELB_11_10_10
- PSELB_11_10_11
- PSELB_13_12_00
- PSELB_13_12_01
- PSELB_13_12_10
- PSELB_13_12_11
- PSELB_15_14_00
- PSELB_15_14_11
- PSELB_9_8_00
- PSELB_9_8_11
- PSELC_11_10_00
- PSELC_11_10_10
- PSELC_13_12_00
- PSELC_13_12_01
- PSELC_13_12_10
- PSELC_15_14_00
- PSELC_15_14_01
- PSELC_15_14_10
- PSELC_9_8_00
- PSELC_9_8_10
- PSELD_11_10_00
- PSELD_11_10_01
- PSELD_15_14_00
- PSELD_15_14_01
- PSELD_15_14_10
- PSELD_1_0_00
- PSELD_1_0_10
- PSELE
- PSEM_REG_DBG_DWORD_ENABLE
- PSEM_REG_DBG_FORCE_FRAME
- PSEM_REG_DBG_FORCE_VALID
- PSEM_REG_DBG_FRAME_MODE_BB_K2
- PSEM_REG_DBG_MODE1_CFG_BB_K2
- PSEM_REG_DBG_SELECT
- PSEM_REG_DBG_SHIFT
- PSEM_REG_ENABLE_IN
- PSEM_REG_FAST_MEMORY
- PSEM_REG_SLOW_DBG_ACTIVE_BB_K2
- PSEM_REG_SLOW_DBG_EMPTY_BB_K2
- PSEM_REG_SLOW_DBG_MODE_BB_K2
- PSEM_REG_SYNC_DBG_EMPTY
- PSERIES_ELOG_SECT_ID_CALL_HOME
- PSERIES_ELOG_SECT_ID_DUMP_LOCATOR
- PSERIES_ELOG_SECT_ID_EPOW
- PSERIES_ELOG_SECT_ID_EXTENDED_UH
- PSERIES_ELOG_SECT_ID_FAILING_MTMS
- PSERIES_ELOG_SECT_ID_FW_ERROR
- PSERIES_ELOG_SECT_ID_HMC_ID
- PSERIES_ELOG_SECT_ID_HOTPLUG
- PSERIES_ELOG_SECT_ID_IMPACT_PART_ID
- PSERIES_ELOG_SECT_ID_IO_EVENT
- PSERIES_ELOG_SECT_ID_LOGIC_RESOURCE_ID
- PSERIES_ELOG_SECT_ID_MANUFACT_INFO
- PSERIES_ELOG_SECT_ID_MCE
- PSERIES_ELOG_SECT_ID_PRIMARY_SRC
- PSERIES_ELOG_SECT_ID_PRIV_HDR
- PSERIES_ELOG_SECT_ID_SECONDARY_SRC
- PSERIES_ELOG_SECT_ID_USER_DEF
- PSERIES_ELOG_SECT_ID_USER_HDR
- PSERIES_HP_ELOG_ACTION_ADD
- PSERIES_HP_ELOG_ACTION_READD
- PSERIES_HP_ELOG_ACTION_REMOVE
- PSERIES_HP_ELOG_ID_DRC_COUNT
- PSERIES_HP_ELOG_ID_DRC_IC
- PSERIES_HP_ELOG_ID_DRC_INDEX
- PSERIES_HP_ELOG_ID_DRC_NAME
- PSERIES_HP_ELOG_RESOURCE_CPU
- PSERIES_HP_ELOG_RESOURCE_MEM
- PSERIES_HP_ELOG_RESOURCE_PHB
- PSERIES_HP_ELOG_RESOURCE_PMEM
- PSERIES_HP_ELOG_RESOURCE_SLOT
- PSERIES_IOEI_RPC_MAX_LEN
- PSERIES_IOEI_SCOPE_EADS_GLOBAL
- PSERIES_IOEI_SCOPE_EADS_SLOT
- PSERIES_IOEI_SCOPE_NOT_APP
- PSERIES_IOEI_SCOPE_PHB
- PSERIES_IOEI_SCOPE_RIO_BRIDGE
- PSERIES_IOEI_SCOPE_RIO_HUB
- PSERIES_IOEI_SCOPE_SERVICE_PROC
- PSERIES_IOEI_SCOPE_TORRENT_HUB
- PSERIES_IOEI_SUBTYPE_DUMP_SIZE_CHANGE
- PSERIES_IOEI_SUBTYPE_NODE_OFFLINE
- PSERIES_IOEI_SUBTYPE_NODE_ONLINE
- PSERIES_IOEI_SUBTYPE_NOT_APP
- PSERIES_IOEI_SUBTYPE_REBALANCE_REQ
- PSERIES_IOEI_SUBTYPE_TORRENT_HFI_CFGED
- PSERIES_IOEI_SUBTYPE_TORRENT_IRV_UPDATE
- PSERIES_IOEI_TYPE_ERR_DETECTED
- PSERIES_IOEI_TYPE_ERR_RECOVERED
- PSERIES_IOEI_TYPE_EVENT
- PSERIES_IOEI_TYPE_RPC_PASS_THRU
- PSET_MAGIC
- PSEUDO_EDO
- PSEUDO_PALETTE_SIZE
- PSEUDO_YUV_FMT
- PSEUDO_YUV_FMT_LOOSE
- PSEUDO_YUV_FMT_LOOSE_TILED
- PSEUDO_YUV_FMT_TILED
- PSEV_10MS_TIMER
- PSEV_CON_OFF
- PSEV_CON_ON
- PSEV_CTS_OFF
- PSEV_CTS_ON
- PSEV_DCD_OFF
- PSEV_DCD_ON
- PSEV_DSR_OFF
- PSEV_DSR_ON
- PSEV_FLAGS_DET
- PSEV_GSTN_CLR
- PSEV_LINE_RX_B
- PSEV_LINE_RX_H
- PSEV_LINE_TX_B
- PSEV_LINE_TX_H
- PSEV_REM_REN
- PSEV_REM_RET
- PSEV_RSP_CONN
- PSEV_RSP_DISC
- PSEV_RSP_FCERR
- PSEV_RSP_READY
- PSEV_RSP_SILDET
- PSEV_RSP_SILOFF
- PSEV_V24_OFF
- PSF_CFG0
- PSF_CFG1
- PSF_CFG2
- PSF_CFG3
- PSF_CFG4
- PSF_CUIR_COMPLETED
- PSF_CUIR_DENIED
- PSF_CUIR_DEVICE_ONLINE
- PSF_CUIR_ERROR_IN_REQ
- PSF_CUIR_INVALID
- PSF_CUIR_LAST_PATH
- PSF_CUIR_NOT_RECOGNIZED
- PSF_CUIR_NOT_SUPPORTED
- PSF_CUIR_SOFTWARE_FAILURE
- PSF_CUIR_VARY_FAILURE
- PSF_ENDIAN
- PSF_ERR_EN
- PSF_EVNT
- PSF_EVNT_EN
- PSF_IPV4
- PSF_ORDER_CUIR_RESPONSE
- PSF_ORDER_PRSSD
- PSF_ORDER_SSC
- PSF_PCF_RD
- PSF_PTPVER
- PSF_RX
- PSF_RXTS_EN
- PSF_SUBORDER_LCQ
- PSF_SUBORDER_QHA
- PSF_SUBORDER_VSQ
- PSF_TRIG_EN
- PSF_TX
- PSF_TXTS_EN
- PSG_ENV_FREQ_10
- PSG_FREQ
- PSHFT
- PSHIFT
- PSHORT
- PSIZE
- PSI_AVGS
- PSI_CPU
- PSI_CPU_SOME
- PSI_FREQ
- PSI_IO
- PSI_IO_FULL
- PSI_IO_SOME
- PSI_MEM
- PSI_MEM_FULL
- PSI_MEM_SOME
- PSI_NONIDLE
- PSI_POLL
- PSI_SEL_VR0_PLANE0_PSI0
- PSI_SEL_VR0_PLANE0_PSI1
- PSI_SEL_VR0_PLANE1_PSI0
- PSI_SEL_VR0_PLANE1_PSI1
- PSI_SEL_VR1_PLANE0_PSI0
- PSI_SEL_VR1_PLANE0_PSI1
- PSI_SEL_VR1_PLANE1_PSI0
- PSI_SEL_VR1_PLANE1_PSI1
- PSKIP_ON_ALLOW_STOP_HI
- PSKIP_ON_ALLOW_STOP_HI_MASK
- PSKIP_ON_ALLOW_STOP_HI_SHIFT
- PSK_8
- PSLC_ASAP
- PSLC_AUTO
- PSLC_COUNTDOWN
- PSLC_ON_HANG_ONLY
- PSLEEP
- PSLOTCNT
- PSLR
- PSLR_SL_ROD
- PSL_2048_250MHZ_CYCLES
- PSL_COMMANDS
- PSMOUSE_ACTIVATED
- PSMOUSE_ALPS
- PSMOUSE_AUTO
- PSMOUSE_BAD_DATA
- PSMOUSE_BYD
- PSMOUSE_CMD_DISABLE
- PSMOUSE_CMD_ENABLE
- PSMOUSE_CMD_GETID
- PSMOUSE_CMD_GETINFO
- PSMOUSE_CMD_MODE
- PSMOUSE_CMD_POLL
- PSMOUSE_CMD_RESET_BAT
- PSMOUSE_CMD_RESET_DIS
- PSMOUSE_CMD_RESET_WRAP
- PSMOUSE_CMD_SETPOLL
- PSMOUSE_CMD_SETRATE
- PSMOUSE_CMD_SETRES
- PSMOUSE_CMD_SETSCALE11
- PSMOUSE_CMD_SETSCALE21
- PSMOUSE_CMD_SETSTREAM
- PSMOUSE_CORTRON
- PSMOUSE_CYPRESS
- PSMOUSE_DEFINE_ATTR
- PSMOUSE_DEFINE_RO_ATTR
- PSMOUSE_DEFINE_WO_ATTR
- PSMOUSE_ELANTECH
- PSMOUSE_ELANTECH_SMBUS
- PSMOUSE_FOCALTECH
- PSMOUSE_FSP
- PSMOUSE_FULL_PACKET
- PSMOUSE_GENPS
- PSMOUSE_GOOD_DATA
- PSMOUSE_HGPK
- PSMOUSE_IGNORE
- PSMOUSE_IMEX
- PSMOUSE_IMPS
- PSMOUSE_INITIALIZING
- PSMOUSE_LIFEBOOK
- PSMOUSE_MINOR
- PSMOUSE_NONE
- PSMOUSE_OOB_EXTRA_BTNS
- PSMOUSE_OOB_NONE
- PSMOUSE_PS2
- PSMOUSE_PS2PP
- PSMOUSE_RESYNCING
- PSMOUSE_RET_ACK
- PSMOUSE_RET_BAT
- PSMOUSE_RET_ID
- PSMOUSE_RET_NAK
- PSMOUSE_RST
- PSMOUSE_SCALE11
- PSMOUSE_SCALE21
- PSMOUSE_SYNAPTICS
- PSMOUSE_SYNAPTICS_RELATIVE
- PSMOUSE_SYNAPTICS_SMBUS
- PSMOUSE_THINKPS
- PSMOUSE_TOUCHKIT_PS2
- PSMOUSE_TRACKPOINT
- PSMOUSE_VMMOUSE
- PSM_BUFFER_SIZE
- PSM_CAM
- PSM_CONFIG_REG0
- PSM_CONFIG_REG1
- PSM_CONFIG_REG1_AC_PRESENT_STATUS
- PSM_CONFIG_REG1_CLK_RUN_ASF
- PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK
- PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA
- PSM_CONFIG_REG1_DIS_LOADER
- PSM_CONFIG_REG1_DIS_PERST
- PSM_CONFIG_REG1_DIS_PIG
- PSM_CONFIG_REG1_DIS_PSM_TIMER
- PSM_CONFIG_REG1_DO_PWDN
- PSM_CONFIG_REG1_EN_AC_PRESENT
- PSM_CONFIG_REG1_EN_GPHY_INT_PSM
- PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ
- PSM_CONFIG_REG1_EN_PCIE_TIMER
- PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT
- PSM_CONFIG_REG1_EN_PSM
- PSM_CONFIG_REG1_EN_PSM_HOT_RST
- PSM_CONFIG_REG1_EN_PSM_LOAD
- PSM_CONFIG_REG1_EN_PSM_PCIE_L1
- PSM_CONFIG_REG1_EN_PSM_PERST
- PSM_CONFIG_REG1_EN_REG18_PD
- PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ
- PSM_CONFIG_REG1_EN_SPU_TIMER
- PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT
- PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO
- PSM_CONFIG_REG1_GPHY_ENERGY_STS
- PSM_CONFIG_REG1_GPHY_INT
- PSM_CONFIG_REG1_LATCH_VAUX
- PSM_CONFIG_REG1_MUX_PHY_LINK
- PSM_CONFIG_REG1_POLARITY_AC_PRESENT
- PSM_CONFIG_REG1_PSM_PCIE_L1_POL
- PSM_CONFIG_REG1_PTP_CLK_SEL
- PSM_CONFIG_REG1_PTP_MODE
- PSM_CONFIG_REG1_TIMER_STAT
- PSM_CONFIG_REG1_UART_CLK_DISABLE
- PSM_CONFIG_REG1_UART_FC_CTS_VAL
- PSM_CONFIG_REG1_UART_FC_DCD_VAL
- PSM_CONFIG_REG1_UART_FC_DSR_VAL
- PSM_CONFIG_REG1_UART_FC_RI_VAL
- PSM_CONFIG_REG1_UART_MODE_MSK
- PSM_CONFIG_REG1_UART_RST
- PSM_CONFIG_REG1_VAUX_ONE
- PSM_CONFIG_REG2
- PSM_CONFIG_REG3
- PSM_CONFIG_REG4
- PSM_CONFIG_REG4_DEBUG_TIMER
- PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
- PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
- PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK
- PSM_FRAME_COUNT
- PSM_FRAME_SIZE
- PSM_MINIMAL_STATION_COUNT
- PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION
- PSN
- PSNE_CNT_PER_PG
- PSNE_MAX_IDX_PER_PG
- PSNR
- PSN_MASK
- PSN_MODIFY_MASK
- PSN_SHIFT
- PSOCK_LIB_H
- PSOC_BTL_MAX_OFFSET
- PSOC_BTL_SECTION
- PSOC_CS_TRACE_MAX_OFFSET
- PSOC_CS_TRACE_SECTION
- PSOC_CTI_MAX_OFFSET
- PSOC_CTI_SECTION
- PSOC_DFT_EFUSE_MAX_OFFSET
- PSOC_DFT_EFUSE_SECTION
- PSOC_EFUSE_MAX_OFFSET
- PSOC_EFUSE_SECTION
- PSOC_EMMC_MAX_OFFSET
- PSOC_EMMC_PLL_MAX_OFFSET
- PSOC_EMMC_PLL_SECTION
- PSOC_EMMC_SECTION
- PSOC_ETF_MAX_OFFSET
- PSOC_ETF_SECTION
- PSOC_ETR_MAX_OFFSET
- PSOC_ETR_SECTION
- PSOC_FUNNEL_MAX_OFFSET
- PSOC_FUNNEL_SECTION
- PSOC_GLOBAL_CONF_APP_STATUS_IND_MASK
- PSOC_GLOBAL_CONF_APP_STATUS_IND_SHIFT
- PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK
- PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT
- PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK
- PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT
- PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK
- PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BOOT_STG2_SRC_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_MEM_REPAIR_BPS_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_BPS_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PLL_CFG_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SPARE_SHIFT
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK
- PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_SHIFT
- PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK
- PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT
- PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK
- PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT
- PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK
- PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT
- PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK
- PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT
- PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK
- PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT
- PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK
- PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT
- PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK
- PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK
- PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT
- PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK
- PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT
- PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK
- PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT
- PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK
- PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT
- PSOC_GLOBAL_CONF_MAX_OFFSET
- PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK
- PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT
- PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK
- PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT
- PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK
- PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT
- PSOC_GLOBAL_CONF_MII_ADDR_VAL_MASK
- PSOC_GLOBAL_CONF_MII_ADDR_VAL_SHIFT
- PSOC_GLOBAL_CONF_MII_SPEED_VAL_MASK
- PSOC_GLOBAL_CONF_MII_SPEED_VAL_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_CPU_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_IF_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_DMA_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_IC_IF_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_MC_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_MME_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_IF_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PCI_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PLL_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_PSOC_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_SRAM_SHIFT
- PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_MASK
- PSOC_GLOBAL_CONF_MNL_RST_CFG_TPC_SHIFT
- PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK
- PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT
- PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK
- PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT
- PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK
- PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT
- PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK
- PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT
- PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK
- PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT
- PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK
- PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT
- PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK
- PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT
- PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK
- PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT
- PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK
- PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT
- PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK
- PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK
- PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK
- PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_CPU_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_IF_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_DMA_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_IC_IF_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MC_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_MME_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_IF_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PCI_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PLL_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_PSOC_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_SRAM_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_MASK
- PSOC_GLOBAL_CONF_PRSTN_RST_CFG_TPC_SHIFT
- PSOC_GLOBAL_CONF_PRSTN_VAL_MASK
- PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT
- PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK
- PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT
- PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK
- PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT
- PSOC_GLOBAL_CONF_SECTION
- PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK
- PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK
- PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT
- PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK
- PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT
- PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK
- PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT
- PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK
- PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_IF_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PCI_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PLL_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_SHIFT
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_MASK
- PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT
- PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK
- PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT
- PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK
- PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT
- PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK
- PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT
- PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK
- PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT
- PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK
- PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK
- PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT
- PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_MASK
- PSOC_GLOBAL_CONF_UBOOT_MAGIC_VAL_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_IF_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_DMA_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_IC_IF_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_MC_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_MC_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_MME_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_MME_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_IF_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_PCI_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_PLL_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_PSOC_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_SRAM_SHIFT
- PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_MASK
- PSOC_GLOBAL_CONF_UNIT_RST_N_TPC_SHIFT
- PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_MASK
- PSOC_GLOBAL_CONF_WARM_REBOOT_CNTR_SHIFT
- PSOC_GLOBAL_CONF_WD_MASK_IND_MASK
- PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_CPU_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_IF_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_DMA_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_IC_IF_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_MC_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_MC_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_MME_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_MME_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_IF_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_PCI_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_PLL_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_PSOC_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_SRAM_SHIFT
- PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_MASK
- PSOC_GLOBAL_CONF_WD_RST_CFG_TPC_SHIFT
- PSOC_GPIO0_MAX_OFFSET
- PSOC_GPIO0_SECTION
- PSOC_GPIO1_MAX_OFFSET
- PSOC_GPIO1_SECTION
- PSOC_GPIO2_MAX_OFFSET
- PSOC_GPIO2_SECTION
- PSOC_GPIO3_MAX_OFFSET
- PSOC_GPIO3_SECTION
- PSOC_GPIO4_MAX_OFFSET
- PSOC_GPIO4_SECTION
- PSOC_I2C_M0_MAX_OFFSET
- PSOC_I2C_M0_SECTION
- PSOC_I2C_M1_MAX_OFFSET
- PSOC_I2C_M1_SECTION
- PSOC_I2C_S_MAX_OFFSET
- PSOC_I2C_S_SECTION
- PSOC_MII_MAX_OFFSET
- PSOC_MII_SECTION
- PSOC_MME_PLL_MAX_OFFSET
- PSOC_MME_PLL_SECTION
- PSOC_PCI_PLL_MAX_OFFSET
- PSOC_PCI_PLL_SECTION
- PSOC_PM_MAX_OFFSET
- PSOC_PM_SECTION
- PSOC_PWM0_MAX_OFFSET
- PSOC_PWM0_SECTION
- PSOC_PWM1_MAX_OFFSET
- PSOC_PWM1_SECTION
- PSOC_PWM2_MAX_OFFSET
- PSOC_PWM2_SECTION
- PSOC_PWM3_MAX_OFFSET
- PSOC_PWM3_SECTION
- PSOC_SPI_MAX_OFFSET
- PSOC_SPI_SECTION
- PSOC_STM_MAX_OFFSET
- PSOC_STM_SECTION
- PSOC_TIMER_MAX_OFFSET
- PSOC_TIMER_SECTION
- PSOC_TIMESTAMP_MAX_OFFSET
- PSOC_TIMESTAMP_SECTION
- PSOC_TS_CTI_MAX_OFFSET
- PSOC_TS_CTI_SECTION
- PSOC_TS_MAX_OFFSET
- PSOC_TS_SECTION
- PSOC_UART_0_MAX_OFFSET
- PSOC_UART_0_SECTION
- PSOC_UART_1_MAX_OFFSET
- PSOC_UART_1_SECTION
- PSOC_WDOG_MAX_OFFSET
- PSOC_WDOG_SECTION
- PSPA_OB_HW_EVENT_PID0_OFFSET
- PSPA_OB_HW_EVENT_PID10_OFFSET
- PSPA_OB_HW_EVENT_PID11_OFFSET
- PSPA_OB_HW_EVENT_PID12_OFFSET
- PSPA_OB_HW_EVENT_PID13_OFFSET
- PSPA_OB_HW_EVENT_PID14_OFFSET
- PSPA_OB_HW_EVENT_PID15_OFFSET
- PSPA_OB_HW_EVENT_PID1_OFFSET
- PSPA_OB_HW_EVENT_PID2_OFFSET
- PSPA_OB_HW_EVENT_PID3_OFFSET
- PSPA_OB_HW_EVENT_PID4_OFFSET
- PSPA_OB_HW_EVENT_PID5_OFFSET
- PSPA_OB_HW_EVENT_PID6_OFFSET
- PSPA_OB_HW_EVENT_PID7_OFFSET
- PSPA_OB_HW_EVENT_PID8_OFFSET
- PSPA_OB_HW_EVENT_PID9_OFFSET
- PSPA_PHYSTATE0_OFFSET
- PSPA_PHYSTATE10_OFFSET
- PSPA_PHYSTATE11_OFFSET
- PSPA_PHYSTATE12_OFFSET
- PSPA_PHYSTATE13_OFFSET
- PSPA_PHYSTATE14_OFFSET
- PSPA_PHYSTATE15_OFFSET
- PSPA_PHYSTATE1_OFFSET
- PSPA_PHYSTATE2_OFFSET
- PSPA_PHYSTATE3_OFFSET
- PSPA_PHYSTATE4_OFFSET
- PSPA_PHYSTATE5_OFFSET
- PSPA_PHYSTATE6_OFFSET
- PSPA_PHYSTATE7_OFFSET
- PSPA_PHYSTATE8_OFFSET
- PSPA_PHYSTATE9_OFFSET
- PSPC
- PSPOLL_DELIVERY_FAILURE_EVENT_ID
- PSPOLL_PG
- PSPOLL_TYPE
- PSPR
- PSP_1_MEG
- PSP_ASD_SHARED_MEM_SIZE
- PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI_MASK
- PSP_BASE_ADDR_HI__PSP_BASE_ADDR_HI__SHIFT
- PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO_MASK
- PSP_BASE_ADDR_LO__PSP_BASE_ADDR_LO__SHIFT
- PSP_BASE_ADDR_LO__PSP_MMIO_EN_MASK
- PSP_BASE_ADDR_LO__PSP_MMIO_EN__SHIFT
- PSP_BASE_ADDR_LO__PSP_MMIO_LOCK_MASK
- PSP_BASE_ADDR_LO__PSP_MMIO_LOCK__SHIFT
- PSP_BINARY_ALIGNMENT
- PSP_BL__LOAD_KEY_DATABASE
- PSP_BL__LOAD_SOSDRV
- PSP_BL__LOAD_SYSDRV
- PSP_BOOTLOADER_1_MEG_ALIGNMENT
- PSP_BOOTLOADER_8_MEM_ALIGNMENT
- PSP_CMDRESP_CMD_SHIFT
- PSP_CMDRESP_ERR_MASK
- PSP_CMDRESP_IOC
- PSP_CMDRESP_RESP
- PSP_CMD_BUFFER_SIZE
- PSP_CMD_COMPLETE
- PSP_DIRECTORY_TABLE_ENTRIES
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_0__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_10__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_11__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_12__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_13__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_14__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_15__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_16__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_17__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_18__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_19__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_1__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_20__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_21__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_22__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_23__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_24__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_25__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_26__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_27__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_28__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_29__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_2__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_30__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_31__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_3__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_4__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_5__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_6__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_7__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_8__SHIFT
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9_MASK
- PSP_EGRESS_POISON_STATUS_HI__PSPEgressPoisonStatusHi_9__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_0__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_10__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_11__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_12__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_13__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_14__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_15__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_16__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_17__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_18__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_19__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_1__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_20__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_21__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_22__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_23__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_24__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_25__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_26__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_27__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_28__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_29__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_2__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_30__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_31__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_3__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_4__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_5__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_6__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_7__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_8__SHIFT
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9_MASK
- PSP_EGRESS_POISON_STATUS_LO__PSPEgressPoisonStatusLo_9__SHIFT
- PSP_ENV_SIZE
- PSP_FENCE_BUFFER_SIZE
- PSP_GFX_CMD_BUF_VERSION
- PSP_HEADER_SIZE
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_0__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_1__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_2__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_3__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_4__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_5__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_6__SHIFT
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7_MASK
- PSP_INTERNAL_POISON_STATUS__PSPIntPoisonStatus_7__SHIFT
- PSP_PARITY_CONTROL_0__PspParityCorrThreshold_MASK
- PSP_PARITY_CONTROL_0__PspParityCorrThreshold__SHIFT
- PSP_PARITY_CONTROL_0__PspParityUCPThreshold_MASK
- PSP_PARITY_CONTROL_0__PspParityUCPThreshold__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP0__ResetEn_MASK
- PSP_PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP1__ResetEn_MASK
- PSP_PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP2__ResetEn_MASK
- PSP_PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP3__ResetEn_MASK
- PSP_PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP4__ResetEn_MASK
- PSP_PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT
- PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP0__ResetEn_MASK
- PSP_PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP1__ResetEn_MASK
- PSP_PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP2__ResetEn_MASK
- PSP_PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP3__ResetEn_MASK
- PSP_PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP4__ResetEn_MASK
- PSP_PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT
- PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK
- PSP_PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK
- PSP_PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT
- PSP_PARITY_STATUS__ParityErrCorr_MASK
- PSP_PARITY_STATUS__ParityErrCorr__SHIFT
- PSP_PARITY_STATUS__ParityErrFatal_MASK
- PSP_PARITY_STATUS__ParityErrFatal__SHIFT
- PSP_PARITY_STATUS__ParityErrNonFatal_MASK
- PSP_PARITY_STATUS__ParityErrNonFatal__SHIFT
- PSP_PARITY_STATUS__ParityErrSerr_MASK
- PSP_PARITY_STATUS__ParityErrSerr__SHIFT
- PSP_PBRT
- PSP_PP_BAL
- PSP_PP_GFX
- PSP_PP_PC
- PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK
- PSP_ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PSP_ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- PSP_ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK
- PSP_ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- PSP_RAS_SHARED_MEM_SIZE
- PSP_REG_IH_RB_CNTL
- PSP_REG_IH_RB_CNTL_RING1
- PSP_REG_IH_RB_CNTL_RING2
- PSP_REG_LAST
- PSP_RING_TYPE__INVALID
- PSP_RING_TYPE__KM
- PSP_RING_TYPE__UM
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromAPML__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_10__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_11__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_12__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_13__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_14__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_15__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_16__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_17__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_18__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_19__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_20__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_21__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_22__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_23__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_24__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_25__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_26__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_27__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_28__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_29__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_30__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_31__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_8__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromIOHCPortN_9__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPin__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromPrivate__SHIFT
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl_MASK
- PSP_SYNCFLOOD_STATUS__PSPSyncfloodFromRASCntl__SHIFT
- PSP_TMR_SIZE
- PSP_XGMI_SHARED_MEM_SIZE
- PSQ
- PSQM
- PSR
- PSR2_ADD_VERTICAL_LINE_COUNT
- PSR2_SU_STATUS
- PSR2_SU_STATUS_FRAMES
- PSR2_SU_STATUS_MASK
- PSR2_SU_STATUS_SHIFT
- PSR2_VSC_ENABLE_PROG_HEADER
- PSRMS2SEG_END
- PSRMS2SEG_START
- PSRMS4SEG_END
- PSRMS4SEG_START
- PSROM_t
- PSR_0_LINES_TO_WAIT
- PSR_1_LINE_TO_WAIT
- PSR_4_LINES_TO_WAIT
- PSR_8_LINES_TO_WAIT
- PSR_AA32_A_BIT
- PSR_AA32_C_BIT
- PSR_AA32_DIT_BIT
- PSR_AA32_ENDSTATE
- PSR_AA32_E_BIT
- PSR_AA32_F_BIT
- PSR_AA32_GE_MASK
- PSR_AA32_IT_MASK
- PSR_AA32_I_BIT
- PSR_AA32_MODE_ABT
- PSR_AA32_MODE_FIQ
- PSR_AA32_MODE_HYP
- PSR_AA32_MODE_IRQ
- PSR_AA32_MODE_MASK
- PSR_AA32_MODE_SVC
- PSR_AA32_MODE_SYS
- PSR_AA32_MODE_UND
- PSR_AA32_MODE_USR
- PSR_AA32_N_BIT
- PSR_AA32_PAN_BIT
- PSR_AA32_Q_BIT
- PSR_AA32_SSBS_BIT
- PSR_AA32_T_BIT
- PSR_AA32_V_BIT
- PSR_AA32_Z_BIT
- PSR_ACTIVE
- PSR_A_BIT
- PSR_BIT
- PSR_BITS_TO_CLEAR
- PSR_BITS_TO_SET
- PSR_BN
- PSR_BO
- PSR_C
- PSR_CMD_COMPLETED
- PSR_CMD_RECEIVED
- PSR_CPU
- PSR_CRC_SEL_HARDWARE
- PSR_CRC_SEL_MANUALLY
- PSR_CUR_SPEED_MASK
- PSR_CUR_SPEED_SHIFT
- PSR_CWP
- PSR_C_BIT
- PSR_DEFAULT_BITS
- PSR_DIT_BIT
- PSR_DMAEN
- PSR_DT
- PSR_D_BIT
- PSR_EC
- PSR_EF
- PSR_ENABLE
- PSR_END
- PSR_ENDIAN_MASK
- PSR_ENDSTATE
- PSR_EP
- PSR_ET
- PSR_EVENT
- PSR_EVENT_FRONT_BUFFER_MODIFY
- PSR_EVENT_GRAPHICS_RESET
- PSR_EVENT_HDCP_ENABLE
- PSR_EVENT_KVMR_SESSION_ENABLE
- PSR_EVENT_LPSP_MODE_EXIT
- PSR_EVENT_MEMORY_UP
- PSR_EVENT_PCH_INTERRUPT
- PSR_EVENT_PIPE_REGISTERS_UPDATE
- PSR_EVENT_PSR2_DISABLED
- PSR_EVENT_PSR2_WD_TIMER_EXPIRE
- PSR_EVENT_PSR_DISABLE
- PSR_EVENT_REGISTER_UPDATE
- PSR_EVENT_SU_CRC_FIFO_UNDERRUN
- PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN
- PSR_EVENT_VBI_ENABLE
- PSR_EVENT_WD_TIMER_EXPIRE
- PSR_EW
- PSR_EXIT
- PSR_E_BIT
- PSR_FRAME_UP_TYPE_BURST
- PSR_FRAME_UP_TYPE_SINGLE
- PSR_F_BIT
- PSR_GEN
- PSR_I
- PSR_IC
- PSR_ICC
- PSR_IGNORE_BITS
- PSR_IL_BIT
- PSR_IMPL
- PSR_IMPL_LEON
- PSR_IMPL_SHIFT
- PSR_IMPL_SHIFTED_MASK
- PSR_IMPL_TI
- PSR_INACTIVE
- PSR_ISETSTATE
- PSR_ISET_MASK
- PSR_IT
- PSR_IT_MASK
- PSR_I_BIT
- PSR_J_BIT
- PSR_LE
- PSR_LEC_MASK
- PSR_LMON
- PSR_MC
- PSR_MODE32_BIT
- PSR_MODE_EL0t
- PSR_MODE_EL1h
- PSR_MODE_EL1t
- PSR_MODE_EL2h
- PSR_MODE_EL2t
- PSR_MODE_EL3h
- PSR_MODE_EL3t
- PSR_MODE_MASK
- PSR_N
- PSR_N_BIT
- PSR_ONE_BITS
- PSR_PAGEBITS
- PSR_PAN_BIT
- PSR_PIL
- PSR_PS
- PSR_PSREN
- PSR_Q_BIT
- PSR_RT
- PSR_R_BIT
- PSR_S
- PSR_SET
- PSR_SETUP_TIME
- PSR_SET_WAITLOOP
- PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING
- PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING
- PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC
- PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB
- PSR_SINK_STATE_INACTIVE
- PSR_SINK_STATE_SINK_INTERNAL_ERROR
- PSR_SSBS_BIT
- PSR_START
- PSR_SYSCALL
- PSR_S_BIT
- PSR_T_BIT
- PSR_UAO_BIT
- PSR_V
- PSR_V8PLUS
- PSR_VERS
- PSR_VERS_SHIFT
- PSR_VERS_SHIFTED_MASK
- PSR_VID_CRC_ENABLE
- PSR_VID_CRC_FLUSH
- PSR_VSC_BIT_7_SET
- PSR_V_BIT
- PSR_WAIT_LINE_FLAG_TIMEOUT_MS
- PSR_WINBITS
- PSR_XCC
- PSR_Z
- PSR_Z_BIT
- PSR_c
- PSR_f
- PSR_s
- PSR_x
- PSS
- PSS1
- PSS2
- PSSCR_EC
- PSSCR_EC_SHIFT
- PSSCR_ESL
- PSSCR_ESL_SHIFT
- PSSCR_FAKE_SUSPEND
- PSSCR_FAKE_SUSPEND_LG
- PSSCR_GUEST_VIS
- PSSCR_HV_DEFAULT_MASK
- PSSCR_HV_DEFAULT_VAL
- PSSCR_MTL_MASK
- PSSCR_PLS
- PSSCR_PLS_SHIFT
- PSSCR_PSLL_MASK
- PSSCR_RL_MASK
- PSSCR_SD
- PSSCR_TR_MASK
- PSSIG_SPE1
- PSSIG_SPE2
- PSSIG_SPE3
- PSSIG_SRADIOPE
- PSSIG_WPE1
- PSSIG_WPE2
- PSSIG_WPE3
- PSSIG_WRADIOPE
- PSSR
- PSSR_BFS
- PSSR_DH
- PSSR_OTGPH
- PSSR_PH
- PSSR_RDH
- PSSR_SS
- PSSR_SSS
- PSSR_STS
- PSSR_VFS
- PSST
- PSSTATUS
- PSST_FXSENDAMOUNT_C
- PSST_FXSENDAMOUNT_C_MASK
- PSST_LOOPSTARTADDR
- PSST_LOOPSTARTADDR_MASK
- PSSWITCH
- PSS_CTL_REG
- PSS_ERR_STATUS_REG
- PSS_GPIO_OE_REG
- PSS_GPIO_OUT_REG
- PSS_LMEM_INIT_TIME
- PSS_SHIFT
- PSS_SMEM_PAGE_START
- PSS_SMEM_PGNUM
- PSS_SMEM_PGOFF
- PSTART
- PSTATE
- PSTATE_ACCEPTOR
- PSTATE_ACQUIRE
- PSTATE_AG
- PSTATE_AM
- PSTATE_CLE
- PSTATE_CLOSING
- PSTATE_DATI
- PSTATE_DLEV_DAT0
- PSTATE_IDLE
- PSTATE_IE
- PSTATE_IG
- PSTATE_IRRELEVANT
- PSTATE_IT_1_0_MASK
- PSTATE_IT_1_0_SHIFT
- PSTATE_IT_7_2_MASK
- PSTATE_IT_7_2_SHIFT
- PSTATE_Imm_shift
- PSTATE_MCDE
- PSTATE_MG
- PSTATE_MM
- PSTATE_NEGOTIATE
- PSTATE_OFFSET
- PSTATE_PAN
- PSTATE_PEF
- PSTATE_PRIV
- PSTATE_PROPOSER
- PSTATE_PSO
- PSTATE_PURGE
- PSTATE_RED
- PSTATE_REJECT
- PSTATE_REPLY_OPTIONAL
- PSTATE_RESPONSE_GOT
- PSTATE_RESPONSE_SENT
- PSTATE_RMO
- PSTATE_RUN
- PSTATE_SSBS
- PSTATE_TLE
- PSTATE_TSO
- PSTATE_UAO
- PSTA_INFO_T
- PSTFIRM
- PSTIME
- PSTIMER
- PSTOPO_PSTOP1
- PSTOPO_PSTOP2
- PSTOPO_PSTOP3
- PSTOREFS_MAGIC
- PSTORE_CPU_IN_IP
- PSTORE_DEFAULT_KMSG_BYTES
- PSTORE_EFI_ATTRIBUTES
- PSTORE_FLAGS_CONSOLE
- PSTORE_FLAGS_DMESG
- PSTORE_FLAGS_FTRACE
- PSTORE_FLAGS_PMSG
- PSTORE_NAMELEN
- PSTORE_TYPE_CONSOLE
- PSTORE_TYPE_DMESG
- PSTORE_TYPE_FTRACE
- PSTORE_TYPE_MAX
- PSTORE_TYPE_MCE
- PSTORE_TYPE_PMSG
- PSTORE_TYPE_PPC_COMMON
- PSTORE_TYPE_PPC_OF
- PSTORE_TYPE_PPC_OPAL
- PSTORE_TYPE_PPC_RTAS
- PSTORM_CTL_FRAME_ETHTYPE_OFFSET
- PSTORM_CTL_FRAME_ETHTYPE_SIZE
- PSTORM_ETH_PF_STAT_OFFSET
- PSTORM_ETH_PF_STAT_SIZE
- PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK
- PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT
- PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK
- PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT
- PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK
- PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT
- PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK
- PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT
- PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK
- PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT
- PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK
- PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT
- PSTORM_FCOE_TX_STATS_OFFSET
- PSTORM_FCOE_TX_STATS_SIZE
- PSTORM_INTEG_TEST_DATA_OFFSET
- PSTORM_INTEG_TEST_DATA_SIZE
- PSTORM_ISCSI_TX_STATS_OFFSET
- PSTORM_ISCSI_TX_STATS_SIZE
- PSTORM_QUEUE_STAT_OFFSET
- PSTORM_QUEUE_STAT_SIZE
- PSTORM_QZONE_SIZE
- PSTORM_RDMA_ASSERT_LEVEL_OFFSET
- PSTORM_RDMA_ASSERT_LEVEL_SIZE
- PSTORM_RDMA_QUEUE_STAT_OFFSET
- PSTORM_RDMA_QUEUE_STAT_SIZE
- PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET
- PSTORM_ROCE_DCQCN_SENT_STATS_SIZE
- PSTR
- PSTR_DELAY_US
- PSTR_OFFS
- PSTR_RETRIES
- PSTTS
- PST_ALPAVAIL
- PST_EXTLPOAVAIL
- PST_HTAVAIL
- PST_INTPEND
- PST_RESINIT
- PST_SBCLKST
- PST_SBCLKST_ALP
- PST_SBCLKST_HT
- PST_SBCLKST_ILP
- PST_WDRESET
- PSUPPLY_FAN_OFF
- PSUPPLY_FAN_ON
- PSUPPLY_FAN_REG
- PSURGE_DUAL
- PSURGE_NONE
- PSURGE_PRI_INTR
- PSURGE_QUAD_BIC
- PSURGE_QUAD_BIS
- PSURGE_QUAD_BOARD_ID
- PSURGE_QUAD_CKSTOP_CTL
- PSURGE_QUAD_CKSTOP_RDBK
- PSURGE_QUAD_COTTON
- PSURGE_QUAD_ICEGRASS
- PSURGE_QUAD_IN
- PSURGE_QUAD_IRQ_CLR
- PSURGE_QUAD_IRQ_PRIMARY
- PSURGE_QUAD_IRQ_SET
- PSURGE_QUAD_OKEE
- PSURGE_QUAD_OUT
- PSURGE_QUAD_PRIMARY_ARB
- PSURGE_QUAD_REG_ADDR
- PSURGE_QUAD_RESET_CTL
- PSURGE_QUAD_WHICH_CPU
- PSURGE_START
- PSW
- PSW32_ADDR_AMODE
- PSW32_ADDR_INSN
- PSW32_ASC_ACCREG
- PSW32_ASC_HOME
- PSW32_ASC_PRIMARY
- PSW32_ASC_SECONDARY
- PSW32_DEFAULT_KEY
- PSW32_MASK_ASC
- PSW32_MASK_BASE
- PSW32_MASK_CC
- PSW32_MASK_DAT
- PSW32_MASK_EXT
- PSW32_MASK_IO
- PSW32_MASK_KEY
- PSW32_MASK_MCHECK
- PSW32_MASK_PER
- PSW32_MASK_PM
- PSW32_MASK_PSTATE
- PSW32_MASK_RI
- PSW32_MASK_USER
- PSW32_MASK_WAIT
- PSW32_USER_BITS
- PSWHST2_REG_DBGSYN_ALMOST_FULL_THR
- PSWHST2_REG_DBG_DWORD_ENABLE
- PSWHST2_REG_DBG_FORCE_FRAME
- PSWHST2_REG_DBG_FORCE_VALID
- PSWHST2_REG_DBG_SELECT
- PSWHST2_REG_DBG_SHIFT
- PSWHST_REG_DBG_DWORD_ENABLE
- PSWHST_REG_DBG_FORCE_FRAME
- PSWHST_REG_DBG_FORCE_VALID
- PSWHST_REG_DBG_SELECT
- PSWHST_REG_DBG_SHIFT
- PSWHST_REG_DISCARD_INTERNAL_WRITES
- PSWHST_REG_INCORRECT_ACCESS_ADDRESS
- PSWHST_REG_INCORRECT_ACCESS_DATA
- PSWHST_REG_INCORRECT_ACCESS_LENGTH
- PSWHST_REG_INCORRECT_ACCESS_VALID
- PSWHST_REG_ZONE_PERMISSION_TABLE
- PSWM
- PSWPIN
- PSWPOUT
- PSWRD2_REG_CONF11
- PSWRD2_REG_DBG_DWORD_ENABLE
- PSWRD2_REG_DBG_FORCE_FRAME
- PSWRD2_REG_DBG_FORCE_VALID
- PSWRD2_REG_DBG_SELECT
- PSWRD2_REG_DBG_SHIFT
- PSWRD_REG_DBG_DWORD_ENABLE
- PSWRD_REG_DBG_FORCE_FRAME
- PSWRD_REG_DBG_FORCE_VALID
- PSWRD_REG_DBG_SELECT
- PSWRD_REG_DBG_SHIFT
- PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET
- PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET
- PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET
- PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_CDUT_P_SIZE
- PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET
- PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_DBG_DWORD_ENABLE
- PSWRQ2_REG_DBG_FORCE_FRAME
- PSWRQ2_REG_DBG_FORCE_VALID
- PSWRQ2_REG_DBG_SELECT
- PSWRQ2_REG_DBG_SHIFT
- PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET
- PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET
- PSWRQ2_REG_ILT_MEMORY
- PSWRQ2_REG_ILT_MEMORY_RT_OFFSET
- PSWRQ2_REG_ILT_MEMORY_RT_SIZE
- PSWRQ2_REG_L2P_VALIDATE_VFID
- PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_QM_P_SIZE_RT_OFFSET
- PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET
- PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET
- PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_TM_P_SIZE_RT_OFFSET
- PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET
- PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET
- PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET
- PSWRQ2_REG_VF_BASE_RT_OFFSET
- PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET
- PSWRQ2_REG_WR_MBS0
- PSWRQ_REG_DBG_DWORD_ENABLE
- PSWRQ_REG_DBG_FORCE_FRAME
- PSWRQ_REG_DBG_FORCE_VALID
- PSWRQ_REG_DBG_SELECT
- PSWRQ_REG_DBG_SHIFT
- PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
- PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_0_BASE_CLASS__BASE_CLASS_MASK
- PSWUSCFG0_0_BASE_CLASS__BASE_CLASS__SHIFT
- PSWUSCFG0_0_BIST__BIST_CAP_MASK
- PSWUSCFG0_0_BIST__BIST_CAP__SHIFT
- PSWUSCFG0_0_BIST__BIST_COMP_MASK
- PSWUSCFG0_0_BIST__BIST_COMP__SHIFT
- PSWUSCFG0_0_BIST__BIST_STRT_MASK
- PSWUSCFG0_0_BIST__BIST_STRT__SHIFT
- PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK
- PSWUSCFG0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- PSWUSCFG0_0_CAP_PTR__CAP_PTR_MASK
- PSWUSCFG0_0_CAP_PTR__CAP_PTR__SHIFT
- PSWUSCFG0_0_COMMAND__AD_STEPPING_MASK
- PSWUSCFG0_0_COMMAND__AD_STEPPING__SHIFT
- PSWUSCFG0_0_COMMAND__BUS_MASTER_EN_MASK
- PSWUSCFG0_0_COMMAND__BUS_MASTER_EN__SHIFT
- PSWUSCFG0_0_COMMAND__FAST_B2B_EN_MASK
- PSWUSCFG0_0_COMMAND__FAST_B2B_EN__SHIFT
- PSWUSCFG0_0_COMMAND__INT_DIS_MASK
- PSWUSCFG0_0_COMMAND__INT_DIS__SHIFT
- PSWUSCFG0_0_COMMAND__IO_ACCESS_EN_MASK
- PSWUSCFG0_0_COMMAND__IO_ACCESS_EN__SHIFT
- PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN_MASK
- PSWUSCFG0_0_COMMAND__MEM_ACCESS_EN__SHIFT
- PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
- PSWUSCFG0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
- PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN_MASK
- PSWUSCFG0_0_COMMAND__PAL_SNOOP_EN__SHIFT
- PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK
- PSWUSCFG0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
- PSWUSCFG0_0_COMMAND__SERR_EN_MASK
- PSWUSCFG0_0_COMMAND__SERR_EN__SHIFT
- PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN_MASK
- PSWUSCFG0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK
- PSWUSCFG0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT
- PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
- PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
- PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
- PSWUSCFG0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
- PSWUSCFG0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
- PSWUSCFG0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
- PSWUSCFG0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
- PSWUSCFG0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
- PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
- PSWUSCFG0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG_MASK
- PSWUSCFG0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE_MASK
- PSWUSCFG0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
- PSWUSCFG0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC_MASK
- PSWUSCFG0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
- PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
- PSWUSCFG0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__LTR_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__OBFF_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
- PSWUSCFG0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
- PSWUSCFG0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
- PSWUSCFG0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
- PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN_MASK
- PSWUSCFG0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
- PSWUSCFG0_0_DEVICE_ID__DEVICE_ID_MASK
- PSWUSCFG0_0_DEVICE_ID__DEVICE_ID__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS2__RESERVED_MASK
- PSWUSCFG0_0_DEVICE_STATUS2__RESERVED__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR_MASK
- PSWUSCFG0_0_DEVICE_STATUS__AUX_PWR__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR_MASK
- PSWUSCFG0_0_DEVICE_STATUS__CORR_ERR__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR_MASK
- PSWUSCFG0_0_DEVICE_STATUS__FATAL_ERR__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK
- PSWUSCFG0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
- PSWUSCFG0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
- PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED_MASK
- PSWUSCFG0_0_DEVICE_STATUS__USR_DETECTED__SHIFT
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
- PSWUSCFG0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
- PSWUSCFG0_0_HEADER__DEVICE_TYPE_MASK
- PSWUSCFG0_0_HEADER__DEVICE_TYPE__SHIFT
- PSWUSCFG0_0_HEADER__HEADER_TYPE_MASK
- PSWUSCFG0_0_HEADER__HEADER_TYPE__SHIFT
- PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- PSWUSCFG0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- PSWUSCFG0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_BASE__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
- PSWUSCFG0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
- PSWUSCFG0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
- PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_0_LATENCY__LATENCY_TIMER_MASK
- PSWUSCFG0_0_LATENCY__LATENCY_TIMER__SHIFT
- PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
- PSWUSCFG0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
- PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED_MASK
- PSWUSCFG0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT
- PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
- PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
- PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
- PSWUSCFG0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
- PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
- PSWUSCFG0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
- PSWUSCFG0_0_LINK_CAP_16GT__RESERVED_MASK
- PSWUSCFG0_0_LINK_CAP_16GT__RESERVED__SHIFT
- PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
- PSWUSCFG0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
- PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
- PSWUSCFG0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
- PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
- PSWUSCFG0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
- PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK
- PSWUSCFG0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
- PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY_MASK
- PSWUSCFG0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
- PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
- PSWUSCFG0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
- PSWUSCFG0_0_LINK_CAP__LINK_SPEED_MASK
- PSWUSCFG0_0_LINK_CAP__LINK_SPEED__SHIFT
- PSWUSCFG0_0_LINK_CAP__LINK_WIDTH_MASK
- PSWUSCFG0_0_LINK_CAP__LINK_WIDTH__SHIFT
- PSWUSCFG0_0_LINK_CAP__PM_SUPPORT_MASK
- PSWUSCFG0_0_LINK_CAP__PM_SUPPORT__SHIFT
- PSWUSCFG0_0_LINK_CAP__PORT_NUMBER_MASK
- PSWUSCFG0_0_LINK_CAP__PORT_NUMBER__SHIFT
- PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
- PSWUSCFG0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
- PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK
- PSWUSCFG0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
- PSWUSCFG0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
- PSWUSCFG0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
- PSWUSCFG0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
- PSWUSCFG0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
- PSWUSCFG0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
- PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN_MASK
- PSWUSCFG0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT
- PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED_MASK
- PSWUSCFG0_0_LINK_CNTL_16GT__RESERVED__SHIFT
- PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
- PSWUSCFG0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
- PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
- PSWUSCFG0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
- PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
- PSWUSCFG0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
- PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC_MASK
- PSWUSCFG0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT
- PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
- PSWUSCFG0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
- PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
- PSWUSCFG0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
- PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
- PSWUSCFG0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
- PSWUSCFG0_0_LINK_CNTL__LINK_DIS_MASK
- PSWUSCFG0_0_LINK_CNTL__LINK_DIS__SHIFT
- PSWUSCFG0_0_LINK_CNTL__PM_CONTROL_MASK
- PSWUSCFG0_0_LINK_CNTL__PM_CONTROL__SHIFT
- PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
- PSWUSCFG0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
- PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK_MASK
- PSWUSCFG0_0_LINK_CNTL__RETRAIN_LINK__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
- PSWUSCFG0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
- PSWUSCFG0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
- PSWUSCFG0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
- PSWUSCFG0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
- PSWUSCFG0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
- PSWUSCFG0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
- PSWUSCFG0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
- PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
- PSWUSCFG0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
- PSWUSCFG0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
- PSWUSCFG0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
- PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
- PSWUSCFG0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
- PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE_MASK
- PSWUSCFG0_0_LINK_STATUS__DL_ACTIVE__SHIFT
- PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
- PSWUSCFG0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
- PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
- PSWUSCFG0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
- PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING_MASK
- PSWUSCFG0_0_LINK_STATUS__LINK_TRAINING__SHIFT
- PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
- PSWUSCFG0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
- PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
- PSWUSCFG0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
- PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
- PSWUSCFG0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
- PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
- PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
- PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
- PSWUSCFG0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_MSI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE_MASK
- PSWUSCFG0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT
- PSWUSCFG0_0_MSI_MAP_CAP__EN_MASK
- PSWUSCFG0_0_MSI_MAP_CAP__EN__SHIFT
- PSWUSCFG0_0_MSI_MAP_CAP__FIXD_MASK
- PSWUSCFG0_0_MSI_MAP_CAP__FIXD__SHIFT
- PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
- PSWUSCFG0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
- PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
- PSWUSCFG0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT_MASK
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN_MASK
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_EN__SHIFT
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
- PSWUSCFG0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
- PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
- PSWUSCFG0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
- PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA_MASK
- PSWUSCFG0_0_MSI_MSG_DATA__MSI_DATA__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
- PSWUSCFG0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
- PSWUSCFG0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
- PSWUSCFG0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE_MASK
- PSWUSCFG0_0_PCIE_CAP__DEVICE_TYPE__SHIFT
- PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK
- PSWUSCFG0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
- PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
- PSWUSCFG0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
- PSWUSCFG0_0_PCIE_CAP__VERSION_MASK
- PSWUSCFG0_0_PCIE_CAP__VERSION__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK
- PSWUSCFG0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK
- PSWUSCFG0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK
- PSWUSCFG0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK
- PSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
- PSWUSCFG0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
- PSWUSCFG0_0_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
- PSWUSCFG0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
- PSWUSCFG0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
- PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
- PSWUSCFG0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
- PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR_MASK
- PSWUSCFG0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
- PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR_MASK
- PSWUSCFG0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
- PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR_MASK
- PSWUSCFG0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
- PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR_MASK
- PSWUSCFG0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
- PSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
- PSWUSCFG0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
- PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
- PSWUSCFG0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
- PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
- PSWUSCFG0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
- PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
- PSWUSCFG0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
- PSWUSCFG0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
- PSWUSCFG0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
- PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
- PSWUSCFG0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
- PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
- PSWUSCFG0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
- PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
- PSWUSCFG0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
- PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
- PSWUSCFG0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
- PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
- PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
- PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
- PSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
- PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
- PSWUSCFG0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
- PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
- PSWUSCFG0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
- PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
- PSWUSCFG0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
- PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE_MASK
- PSWUSCFG0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
- PSWUSCFG0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
- PSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
- PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
- PSWUSCFG0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
- PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
- PSWUSCFG0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
- PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
- PSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
- PSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
- PSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
- PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_PMI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_PMI_CAP__AUX_CURRENT_MASK
- PSWUSCFG0_0_PMI_CAP__AUX_CURRENT__SHIFT
- PSWUSCFG0_0_PMI_CAP__D1_SUPPORT_MASK
- PSWUSCFG0_0_PMI_CAP__D1_SUPPORT__SHIFT
- PSWUSCFG0_0_PMI_CAP__D2_SUPPORT_MASK
- PSWUSCFG0_0_PMI_CAP__D2_SUPPORT__SHIFT
- PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
- PSWUSCFG0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
- PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
- PSWUSCFG0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
- PSWUSCFG0_0_PMI_CAP__PME_CLOCK_MASK
- PSWUSCFG0_0_PMI_CAP__PME_CLOCK__SHIFT
- PSWUSCFG0_0_PMI_CAP__PME_SUPPORT_MASK
- PSWUSCFG0_0_PMI_CAP__PME_SUPPORT__SHIFT
- PSWUSCFG0_0_PMI_CAP__VERSION_MASK
- PSWUSCFG0_0_PMI_CAP__VERSION__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__PME_EN__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
- PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE_MASK
- PSWUSCFG0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
- PSWUSCFG0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
- PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
- PSWUSCFG0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
- PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE_MASK
- PSWUSCFG0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
- PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID_MASK
- PSWUSCFG0_0_REVISION_ID__MAJOR_REV_ID__SHIFT
- PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID_MASK
- PSWUSCFG0_0_REVISION_ID__MINOR_REV_ID__SHIFT
- PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR_MASK
- PSWUSCFG0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT
- PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_SSID_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID_MASK
- PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_0_STATUS__CAP_LIST_MASK
- PSWUSCFG0_0_STATUS__CAP_LIST__SHIFT
- PSWUSCFG0_0_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_0_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_0_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS_MASK
- PSWUSCFG0_0_STATUS__IMMEDIATE_READINESS__SHIFT
- PSWUSCFG0_0_STATUS__INT_STATUS_MASK
- PSWUSCFG0_0_STATUS__INT_STATUS__SHIFT
- PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_0_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_0_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- PSWUSCFG0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
- PSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
- PSWUSCFG0_0_SUB_CLASS__SUB_CLASS_MASK
- PSWUSCFG0_0_SUB_CLASS__SUB_CLASS__SHIFT
- PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH_MASK
- PSWUSCFG0_0_VENDOR_CAP_LIST__LENGTH__SHIFT
- PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_0_VENDOR_ID__VENDOR_ID_MASK
- PSWUSCFG0_0_VENDOR_ID__VENDOR_ID__SHIFT
- PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
- PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_1_BASE_CLASS__BASE_CLASS_MASK
- PSWUSCFG0_1_BASE_CLASS__BASE_CLASS__SHIFT
- PSWUSCFG0_1_BIST__BIST_CAP_MASK
- PSWUSCFG0_1_BIST__BIST_CAP__SHIFT
- PSWUSCFG0_1_BIST__BIST_COMP_MASK
- PSWUSCFG0_1_BIST__BIST_COMP__SHIFT
- PSWUSCFG0_1_BIST__BIST_STRT_MASK
- PSWUSCFG0_1_BIST__BIST_STRT__SHIFT
- PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK
- PSWUSCFG0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- PSWUSCFG0_1_CAP_PTR__CAP_PTR_MASK
- PSWUSCFG0_1_CAP_PTR__CAP_PTR__SHIFT
- PSWUSCFG0_1_COMMAND__AD_STEPPING_MASK
- PSWUSCFG0_1_COMMAND__AD_STEPPING__SHIFT
- PSWUSCFG0_1_COMMAND__BUS_MASTER_EN_MASK
- PSWUSCFG0_1_COMMAND__BUS_MASTER_EN__SHIFT
- PSWUSCFG0_1_COMMAND__FAST_B2B_EN_MASK
- PSWUSCFG0_1_COMMAND__FAST_B2B_EN__SHIFT
- PSWUSCFG0_1_COMMAND__INT_DIS_MASK
- PSWUSCFG0_1_COMMAND__INT_DIS__SHIFT
- PSWUSCFG0_1_COMMAND__IO_ACCESS_EN_MASK
- PSWUSCFG0_1_COMMAND__IO_ACCESS_EN__SHIFT
- PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN_MASK
- PSWUSCFG0_1_COMMAND__MEM_ACCESS_EN__SHIFT
- PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
- PSWUSCFG0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
- PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN_MASK
- PSWUSCFG0_1_COMMAND__PAL_SNOOP_EN__SHIFT
- PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK
- PSWUSCFG0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
- PSWUSCFG0_1_COMMAND__SERR_EN_MASK
- PSWUSCFG0_1_COMMAND__SERR_EN__SHIFT
- PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN_MASK
- PSWUSCFG0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK
- PSWUSCFG0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT
- PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
- PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
- PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
- PSWUSCFG0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
- PSWUSCFG0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
- PSWUSCFG0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
- PSWUSCFG0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
- PSWUSCFG0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
- PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
- PSWUSCFG0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG_MASK
- PSWUSCFG0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE_MASK
- PSWUSCFG0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
- PSWUSCFG0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC_MASK
- PSWUSCFG0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT
- PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
- PSWUSCFG0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__LTR_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__OBFF_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
- PSWUSCFG0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
- PSWUSCFG0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
- PSWUSCFG0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
- PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN_MASK
- PSWUSCFG0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT
- PSWUSCFG0_1_DEVICE_ID__DEVICE_ID_MASK
- PSWUSCFG0_1_DEVICE_ID__DEVICE_ID__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS2__RESERVED_MASK
- PSWUSCFG0_1_DEVICE_STATUS2__RESERVED__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR_MASK
- PSWUSCFG0_1_DEVICE_STATUS__AUX_PWR__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR_MASK
- PSWUSCFG0_1_DEVICE_STATUS__CORR_ERR__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR_MASK
- PSWUSCFG0_1_DEVICE_STATUS__FATAL_ERR__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK
- PSWUSCFG0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
- PSWUSCFG0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
- PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED_MASK
- PSWUSCFG0_1_DEVICE_STATUS__USR_DETECTED__SHIFT
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK
- PSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK
- PSWUSCFG0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT
- PSWUSCFG0_1_HEADER__DEVICE_TYPE_MASK
- PSWUSCFG0_1_HEADER__DEVICE_TYPE__SHIFT
- PSWUSCFG0_1_HEADER__HEADER_TYPE_MASK
- PSWUSCFG0_1_HEADER__HEADER_TYPE__SHIFT
- PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- PSWUSCFG0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- PSWUSCFG0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_BASE__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
- PSWUSCFG0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK
- PSWUSCFG0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
- PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_1_LATENCY__LATENCY_TIMER_MASK
- PSWUSCFG0_1_LATENCY__LATENCY_TIMER__SHIFT
- PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
- PSWUSCFG0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
- PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED_MASK
- PSWUSCFG0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT
- PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
- PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
- PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
- PSWUSCFG0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
- PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
- PSWUSCFG0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
- PSWUSCFG0_1_LINK_CAP_16GT__RESERVED_MASK
- PSWUSCFG0_1_LINK_CAP_16GT__RESERVED__SHIFT
- PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
- PSWUSCFG0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
- PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
- PSWUSCFG0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
- PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
- PSWUSCFG0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
- PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK
- PSWUSCFG0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
- PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY_MASK
- PSWUSCFG0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT
- PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
- PSWUSCFG0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
- PSWUSCFG0_1_LINK_CAP__LINK_SPEED_MASK
- PSWUSCFG0_1_LINK_CAP__LINK_SPEED__SHIFT
- PSWUSCFG0_1_LINK_CAP__LINK_WIDTH_MASK
- PSWUSCFG0_1_LINK_CAP__LINK_WIDTH__SHIFT
- PSWUSCFG0_1_LINK_CAP__PM_SUPPORT_MASK
- PSWUSCFG0_1_LINK_CAP__PM_SUPPORT__SHIFT
- PSWUSCFG0_1_LINK_CAP__PORT_NUMBER_MASK
- PSWUSCFG0_1_LINK_CAP__PORT_NUMBER__SHIFT
- PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
- PSWUSCFG0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
- PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK
- PSWUSCFG0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK
- PSWUSCFG0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
- PSWUSCFG0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
- PSWUSCFG0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
- PSWUSCFG0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK
- PSWUSCFG0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
- PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN_MASK
- PSWUSCFG0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT
- PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED_MASK
- PSWUSCFG0_1_LINK_CNTL_16GT__RESERVED__SHIFT
- PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
- PSWUSCFG0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
- PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK
- PSWUSCFG0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
- PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
- PSWUSCFG0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
- PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC_MASK
- PSWUSCFG0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT
- PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
- PSWUSCFG0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
- PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
- PSWUSCFG0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
- PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
- PSWUSCFG0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
- PSWUSCFG0_1_LINK_CNTL__LINK_DIS_MASK
- PSWUSCFG0_1_LINK_CNTL__LINK_DIS__SHIFT
- PSWUSCFG0_1_LINK_CNTL__PM_CONTROL_MASK
- PSWUSCFG0_1_LINK_CNTL__PM_CONTROL__SHIFT
- PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK
- PSWUSCFG0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
- PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK_MASK
- PSWUSCFG0_1_LINK_CNTL__RETRAIN_LINK__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK
- PSWUSCFG0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
- PSWUSCFG0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
- PSWUSCFG0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
- PSWUSCFG0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
- PSWUSCFG0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
- PSWUSCFG0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
- PSWUSCFG0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
- PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
- PSWUSCFG0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
- PSWUSCFG0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
- PSWUSCFG0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
- PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK
- PSWUSCFG0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
- PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE_MASK
- PSWUSCFG0_1_LINK_STATUS__DL_ACTIVE__SHIFT
- PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
- PSWUSCFG0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
- PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
- PSWUSCFG0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
- PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING_MASK
- PSWUSCFG0_1_LINK_STATUS__LINK_TRAINING__SHIFT
- PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
- PSWUSCFG0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
- PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK
- PSWUSCFG0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
- PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
- PSWUSCFG0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
- PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK
- PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
- PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
- PSWUSCFG0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_MSI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE_MASK
- PSWUSCFG0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT
- PSWUSCFG0_1_MSI_MAP_CAP__EN_MASK
- PSWUSCFG0_1_MSI_MAP_CAP__EN__SHIFT
- PSWUSCFG0_1_MSI_MAP_CAP__FIXD_MASK
- PSWUSCFG0_1_MSI_MAP_CAP__FIXD__SHIFT
- PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
- PSWUSCFG0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
- PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
- PSWUSCFG0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT_MASK
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN_MASK
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_EN__SHIFT
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
- PSWUSCFG0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
- PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK
- PSWUSCFG0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
- PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA_MASK
- PSWUSCFG0_1_MSI_MSG_DATA__MSI_DATA__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
- PSWUSCFG0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
- PSWUSCFG0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
- PSWUSCFG0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE_MASK
- PSWUSCFG0_1_PCIE_CAP__DEVICE_TYPE__SHIFT
- PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK
- PSWUSCFG0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
- PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK
- PSWUSCFG0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
- PSWUSCFG0_1_PCIE_CAP__VERSION_MASK
- PSWUSCFG0_1_PCIE_CAP__VERSION__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK
- PSWUSCFG0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK
- PSWUSCFG0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK
- PSWUSCFG0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE_MASK
- PSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL__CCIX_PCIE_COMPATIBLE_TLP_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
- PSWUSCFG0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK
- PSWUSCFG0_1_PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK
- PSWUSCFG0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT
- PSWUSCFG0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK
- PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK
- PSWUSCFG0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT
- PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR_MASK
- PSWUSCFG0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT
- PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR_MASK
- PSWUSCFG0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT
- PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR_MASK
- PSWUSCFG0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT
- PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR_MASK
- PSWUSCFG0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK
- PSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
- PSWUSCFG0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
- PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
- PSWUSCFG0_1_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
- PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
- PSWUSCFG0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
- PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
- PSWUSCFG0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
- PSWUSCFG0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
- PSWUSCFG0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
- PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
- PSWUSCFG0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
- PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
- PSWUSCFG0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
- PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
- PSWUSCFG0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
- PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
- PSWUSCFG0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
- PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
- PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
- PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
- PSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
- PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
- PSWUSCFG0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
- PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK
- PSWUSCFG0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
- PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK
- PSWUSCFG0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT
- PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE_MASK
- PSWUSCFG0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
- PSWUSCFG0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK
- PSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT
- PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
- PSWUSCFG0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
- PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
- PSWUSCFG0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
- PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
- PSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
- PSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
- PSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
- PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_PMI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_PMI_CAP__AUX_CURRENT_MASK
- PSWUSCFG0_1_PMI_CAP__AUX_CURRENT__SHIFT
- PSWUSCFG0_1_PMI_CAP__D1_SUPPORT_MASK
- PSWUSCFG0_1_PMI_CAP__D1_SUPPORT__SHIFT
- PSWUSCFG0_1_PMI_CAP__D2_SUPPORT_MASK
- PSWUSCFG0_1_PMI_CAP__D2_SUPPORT__SHIFT
- PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK
- PSWUSCFG0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
- PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
- PSWUSCFG0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
- PSWUSCFG0_1_PMI_CAP__PME_CLOCK_MASK
- PSWUSCFG0_1_PMI_CAP__PME_CLOCK__SHIFT
- PSWUSCFG0_1_PMI_CAP__PME_SUPPORT_MASK
- PSWUSCFG0_1_PMI_CAP__PME_SUPPORT__SHIFT
- PSWUSCFG0_1_PMI_CAP__VERSION_MASK
- PSWUSCFG0_1_PMI_CAP__VERSION__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__PME_EN__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT
- PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE_MASK
- PSWUSCFG0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
- PSWUSCFG0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
- PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
- PSWUSCFG0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
- PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE_MASK
- PSWUSCFG0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT
- PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID_MASK
- PSWUSCFG0_1_REVISION_ID__MAJOR_REV_ID__SHIFT
- PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID_MASK
- PSWUSCFG0_1_REVISION_ID__MINOR_REV_ID__SHIFT
- PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR_MASK
- PSWUSCFG0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT
- PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_SSID_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID_MASK
- PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_1_STATUS__CAP_LIST_MASK
- PSWUSCFG0_1_STATUS__CAP_LIST__SHIFT
- PSWUSCFG0_1_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_1_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_1_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS_MASK
- PSWUSCFG0_1_STATUS__IMMEDIATE_READINESS__SHIFT
- PSWUSCFG0_1_STATUS__INT_STATUS_MASK
- PSWUSCFG0_1_STATUS__INT_STATUS__SHIFT
- PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_1_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_1_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- PSWUSCFG0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
- PSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
- PSWUSCFG0_1_SUB_CLASS__SUB_CLASS_MASK
- PSWUSCFG0_1_SUB_CLASS__SUB_CLASS__SHIFT
- PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH_MASK
- PSWUSCFG0_1_VENDOR_CAP_LIST__LENGTH__SHIFT
- PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_1_VENDOR_ID__VENDOR_ID_MASK
- PSWUSCFG0_1_VENDOR_ID__VENDOR_ID__SHIFT
- PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK
- PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_BASE_CLASS__BASE_CLASS_MASK
- PSWUSCFG0_BASE_CLASS__BASE_CLASS__SHIFT
- PSWUSCFG0_BIST__BIST_CAP_MASK
- PSWUSCFG0_BIST__BIST_CAP__SHIFT
- PSWUSCFG0_BIST__BIST_COMP_MASK
- PSWUSCFG0_BIST__BIST_COMP__SHIFT
- PSWUSCFG0_BIST__BIST_STRT_MASK
- PSWUSCFG0_BIST__BIST_STRT__SHIFT
- PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE_MASK
- PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- PSWUSCFG0_CAP_PTR__CAP_PTR_MASK
- PSWUSCFG0_CAP_PTR__CAP_PTR__SHIFT
- PSWUSCFG0_COMMAND__AD_STEPPING_MASK
- PSWUSCFG0_COMMAND__AD_STEPPING__SHIFT
- PSWUSCFG0_COMMAND__BUS_MASTER_EN_MASK
- PSWUSCFG0_COMMAND__BUS_MASTER_EN__SHIFT
- PSWUSCFG0_COMMAND__FAST_B2B_EN_MASK
- PSWUSCFG0_COMMAND__FAST_B2B_EN__SHIFT
- PSWUSCFG0_COMMAND__INT_DIS_MASK
- PSWUSCFG0_COMMAND__INT_DIS__SHIFT
- PSWUSCFG0_COMMAND__IO_ACCESS_EN_MASK
- PSWUSCFG0_COMMAND__IO_ACCESS_EN__SHIFT
- PSWUSCFG0_COMMAND__MEM_ACCESS_EN_MASK
- PSWUSCFG0_COMMAND__MEM_ACCESS_EN__SHIFT
- PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK
- PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT
- PSWUSCFG0_COMMAND__PAL_SNOOP_EN_MASK
- PSWUSCFG0_COMMAND__PAL_SNOOP_EN__SHIFT
- PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE_MASK
- PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT
- PSWUSCFG0_COMMAND__SERR_EN_MASK
- PSWUSCFG0_COMMAND__SERR_EN__SHIFT
- PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN_MASK
- PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN__SHIFT
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK
- PSWUSCFG0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT
- PSWUSCFG0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK
- PSWUSCFG0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK
- PSWUSCFG0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT
- PSWUSCFG0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__FRS_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK
- PSWUSCFG0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT
- PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK
- PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT
- PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK
- PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK
- PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT
- PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK
- PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT
- PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK
- PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT
- PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG_MASK
- PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG__SHIFT
- PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE_MASK
- PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE__SHIFT
- PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK
- PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT
- PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK
- PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT
- PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC_MASK
- PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC__SHIFT
- PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK
- PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK
- PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK
- PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK
- PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK
- PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK
- PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK
- PSWUSCFG0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK
- PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK
- PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK
- PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__LTR_EN_MASK
- PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__OBFF_EN_MASK
- PSWUSCFG0_DEVICE_CNTL2__OBFF_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK
- PSWUSCFG0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT
- PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK
- PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT
- PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK
- PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT
- PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT
- PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN_MASK
- PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN__SHIFT
- PSWUSCFG0_DEVICE_ID__DEVICE_ID_MASK
- PSWUSCFG0_DEVICE_ID__DEVICE_ID__SHIFT
- PSWUSCFG0_DEVICE_STATUS2__RESERVED_MASK
- PSWUSCFG0_DEVICE_STATUS2__RESERVED__SHIFT
- PSWUSCFG0_DEVICE_STATUS__AUX_PWR_MASK
- PSWUSCFG0_DEVICE_STATUS__AUX_PWR__SHIFT
- PSWUSCFG0_DEVICE_STATUS__CORR_ERR_MASK
- PSWUSCFG0_DEVICE_STATUS__CORR_ERR__SHIFT
- PSWUSCFG0_DEVICE_STATUS__FATAL_ERR_MASK
- PSWUSCFG0_DEVICE_STATUS__FATAL_ERR__SHIFT
- PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR_MASK
- PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT
- PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK
- PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT
- PSWUSCFG0_DEVICE_STATUS__USR_DETECTED_MASK
- PSWUSCFG0_DEVICE_STATUS__USR_DETECTED__SHIFT
- PSWUSCFG0_HEADER__DEVICE_TYPE_MASK
- PSWUSCFG0_HEADER__DEVICE_TYPE__SHIFT
- PSWUSCFG0_HEADER__HEADER_TYPE_MASK
- PSWUSCFG0_HEADER__HEADER_TYPE__SHIFT
- PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
- PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
- PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK
- PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK
- PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK
- PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
- PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
- PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
- PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN_MASK
- PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
- PSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK
- PSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK
- PSWUSCFG0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT
- PSWUSCFG0_LATENCY__LATENCY_TIMER_MASK
- PSWUSCFG0_LATENCY__LATENCY_TIMER__SHIFT
- PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK
- PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT
- PSWUSCFG0_LINK_CAP2__DRS_SUPPORTED_MASK
- PSWUSCFG0_LINK_CAP2__DRS_SUPPORTED__SHIFT
- PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK
- PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT
- PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK
- PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT
- PSWUSCFG0_LINK_CAP2__RESERVED_MASK
- PSWUSCFG0_LINK_CAP2__RESERVED__SHIFT
- PSWUSCFG0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK
- PSWUSCFG0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT
- PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK
- PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT
- PSWUSCFG0_LINK_CAP_16GT__RESERVED_MASK
- PSWUSCFG0_LINK_CAP_16GT__RESERVED__SHIFT
- PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK
- PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT
- PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK
- PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT
- PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK
- PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT
- PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY_MASK
- PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT
- PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY_MASK
- PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY__SHIFT
- PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK
- PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT
- PSWUSCFG0_LINK_CAP__LINK_SPEED_MASK
- PSWUSCFG0_LINK_CAP__LINK_SPEED__SHIFT
- PSWUSCFG0_LINK_CAP__LINK_WIDTH_MASK
- PSWUSCFG0_LINK_CAP__LINK_WIDTH__SHIFT
- PSWUSCFG0_LINK_CAP__PM_SUPPORT_MASK
- PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT
- PSWUSCFG0_LINK_CAP__PORT_NUMBER_MASK
- PSWUSCFG0_LINK_CAP__PORT_NUMBER__SHIFT
- PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK
- PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT
- PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK
- PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT
- PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS_MASK
- PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT
- PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE_MASK
- PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT
- PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK
- PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT
- PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK
- PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT
- PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK
- PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT
- PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED_MASK
- PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT
- PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN_MASK
- PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN__SHIFT
- PSWUSCFG0_LINK_CNTL_16GT__RESERVED_MASK
- PSWUSCFG0_LINK_CNTL_16GT__RESERVED__SHIFT
- PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK
- PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT
- PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG_MASK
- PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT
- PSWUSCFG0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK
- PSWUSCFG0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT
- PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC_MASK
- PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC__SHIFT
- PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK
- PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT
- PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK
- PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT
- PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK
- PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT
- PSWUSCFG0_LINK_CNTL__LINK_DIS_MASK
- PSWUSCFG0_LINK_CNTL__LINK_DIS__SHIFT
- PSWUSCFG0_LINK_CNTL__PM_CONTROL_MASK
- PSWUSCFG0_LINK_CNTL__PM_CONTROL__SHIFT
- PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY_MASK
- PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT
- PSWUSCFG0_LINK_CNTL__RETRAIN_LINK_MASK
- PSWUSCFG0_LINK_CNTL__RETRAIN_LINK__SHIFT
- PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK
- PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT
- PSWUSCFG0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK
- PSWUSCFG0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT
- PSWUSCFG0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK
- PSWUSCFG0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK
- PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT
- PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK
- PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT
- PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK
- PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT
- PSWUSCFG0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK
- PSWUSCFG0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT
- PSWUSCFG0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK
- PSWUSCFG0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK
- PSWUSCFG0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT
- PSWUSCFG0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK
- PSWUSCFG0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT
- PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED_MASK
- PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT
- PSWUSCFG0_LINK_STATUS__DL_ACTIVE_MASK
- PSWUSCFG0_LINK_STATUS__DL_ACTIVE__SHIFT
- PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK
- PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT
- PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK
- PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT
- PSWUSCFG0_LINK_STATUS__LINK_TRAINING_MASK
- PSWUSCFG0_LINK_STATUS__LINK_TRAINING__SHIFT
- PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK
- PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT
- PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG_MASK
- PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT
- PSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK
- PSWUSCFG0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT
- PSWUSCFG0_MARGINING_PORT_STATUS__MARGINING_READY_MASK
- PSWUSCFG0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT
- PSWUSCFG0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK
- PSWUSCFG0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_MSI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_MSI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK
- PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT
- PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK
- PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT
- PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT_MASK
- PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT__SHIFT
- PSWUSCFG0_MSI_MSG_CNTL__MSI_EN_MASK
- PSWUSCFG0_MSI_MSG_CNTL__MSI_EN__SHIFT
- PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK
- PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT
- PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK
- PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT
- PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK
- PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT
- PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64_MASK
- PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT
- PSWUSCFG0_MSI_MSG_DATA__MSI_DATA_MASK
- PSWUSCFG0_MSI_MSG_DATA__MSI_DATA__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK
- PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK
- PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK
- PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK
- PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK
- PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK
- PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK
- PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT
- PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK
- PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK
- PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK
- PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK
- PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT
- PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK
- PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK
- PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_CAP__DEVICE_TYPE_MASK
- PSWUSCFG0_PCIE_CAP__DEVICE_TYPE__SHIFT
- PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM_MASK
- PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT
- PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED_MASK
- PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT
- PSWUSCFG0_PCIE_CAP__VERSION_MASK
- PSWUSCFG0_PCIE_CAP__VERSION__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK
- PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK
- PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR_MASK
- PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR__SHIFT
- PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR_MASK
- PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR__SHIFT
- PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR_MASK
- PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR__SHIFT
- PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR_MASK
- PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR__SHIFT
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK
- PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT
- PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK
- PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT
- PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK
- PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT
- PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK
- PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT
- PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK
- PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT
- PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK
- PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT
- PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED_MASK
- PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED__SHIFT
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK
- PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK
- PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT
- PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK
- PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT
- PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK
- PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT
- PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK
- PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT
- PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK
- PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT
- PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK
- PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT
- PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK
- PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT
- PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK
- PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT
- PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP_MASK
- PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT
- PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE_MASK
- PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE__SHIFT
- PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK
- PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK
- PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT
- PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK
- PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK
- PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK
- PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT
- PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK
- PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK
- PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT
- PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK
- PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK
- PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT
- PSWUSCFG0_PMI_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_PMI_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_PMI_CAP__AUX_CURRENT_MASK
- PSWUSCFG0_PMI_CAP__AUX_CURRENT__SHIFT
- PSWUSCFG0_PMI_CAP__D1_SUPPORT_MASK
- PSWUSCFG0_PMI_CAP__D1_SUPPORT__SHIFT
- PSWUSCFG0_PMI_CAP__D2_SUPPORT_MASK
- PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT
- PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT_MASK
- PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT
- PSWUSCFG0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK
- PSWUSCFG0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT
- PSWUSCFG0_PMI_CAP__PME_CLOCK_MASK
- PSWUSCFG0_PMI_CAP__PME_CLOCK__SHIFT
- PSWUSCFG0_PMI_CAP__PME_SUPPORT_MASK
- PSWUSCFG0_PMI_CAP__PME_SUPPORT__SHIFT
- PSWUSCFG0_PMI_CAP__VERSION_MASK
- PSWUSCFG0_PMI_CAP__VERSION__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__PME_EN_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__PME_EN__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA__SHIFT
- PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE_MASK
- PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE__SHIFT
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK
- PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT
- PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK
- PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT
- PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK
- PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT
- PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE_MASK
- PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE__SHIFT
- PSWUSCFG0_REVISION_ID__MAJOR_REV_ID_MASK
- PSWUSCFG0_REVISION_ID__MAJOR_REV_ID__SHIFT
- PSWUSCFG0_REVISION_ID__MINOR_REV_ID_MASK
- PSWUSCFG0_REVISION_ID__MINOR_REV_ID__SHIFT
- PSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK
- PSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__CAP_LIST_MASK
- PSWUSCFG0_SECONDARY_STATUS__CAP_LIST__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_SECONDARY_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN_MASK
- PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK
- PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT
- PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK
- PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT
- PSWUSCFG0_STATUS__CAP_LIST_MASK
- PSWUSCFG0_STATUS__CAP_LIST__SHIFT
- PSWUSCFG0_STATUS__DEVSEL_TIMING_MASK
- PSWUSCFG0_STATUS__DEVSEL_TIMING__SHIFT
- PSWUSCFG0_STATUS__FAST_BACK_CAPABLE_MASK
- PSWUSCFG0_STATUS__FAST_BACK_CAPABLE__SHIFT
- PSWUSCFG0_STATUS__IMMEDIATE_READINESS_MASK
- PSWUSCFG0_STATUS__IMMEDIATE_READINESS__SHIFT
- PSWUSCFG0_STATUS__INT_STATUS_MASK
- PSWUSCFG0_STATUS__INT_STATUS__SHIFT
- PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR_MASK
- PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT
- PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED_MASK
- PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED__SHIFT
- PSWUSCFG0_STATUS__PCI_66_CAP_MASK
- PSWUSCFG0_STATUS__PCI_66_CAP__SHIFT
- PSWUSCFG0_STATUS__PCI_66_EN_MASK
- PSWUSCFG0_STATUS__PCI_66_EN__SHIFT
- PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT_MASK
- PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT_MASK
- PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT_MASK
- PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK
- PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT
- PSWUSCFG0_SUB_CLASS__SUB_CLASS_MASK
- PSWUSCFG0_SUB_CLASS__SUB_CLASS__SHIFT
- PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID_MASK
- PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID__SHIFT
- PSWUSCFG0_VENDOR_CAP_LIST__LENGTH_MASK
- PSWUSCFG0_VENDOR_CAP_LIST__LENGTH__SHIFT
- PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR_MASK
- PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT
- PSWUSCFG0_VENDOR_ID__VENDOR_ID_MASK
- PSWUSCFG0_VENDOR_ID__VENDOR_ID__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK
- PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK
- PSWUSP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK
- PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK
- PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK
- PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK
- PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK
- PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK
- PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK
- PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK
- PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT
- PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK
- PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT
- PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK
- PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK
- PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT
- PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK
- PSWUSP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK
- PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- PSWWR2_REG_CDU_FULL_TH2
- PSWWR_REG_DBG_DWORD_ENABLE
- PSWWR_REG_DBG_FORCE_FRAME
- PSWWR_REG_DBG_FORCE_VALID
- PSWWR_REG_DBG_SELECT
- PSWWR_REG_DBG_SHIFT
- PSWWR_REG_USDM_FULL_TH
- PSW_ADDR_24
- PSW_ADDR_31
- PSW_ADDR_AMODE
- PSW_ADDR_INSN
- PSW_ASC_ACCREG
- PSW_ASC_HOME
- PSW_ASC_PRIMARY
- PSW_ASC_SECONDARY
- PSW_B
- PSW_BITS_AMODE_24BIT
- PSW_BITS_AMODE_31BIT
- PSW_BITS_AMODE_64BIT
- PSW_BITS_AS_ACCREG
- PSW_BITS_AS_HOME
- PSW_BITS_AS_PRIMARY
- PSW_BITS_AS_SECONDARY
- PSW_C
- PSW_CB
- PSW_CLK_CTRL
- PSW_CPL_ANY
- PSW_CPL_NO
- PSW_D
- PSW_DE
- PSW_DEFAULT_KEY
- PSW_E
- PSW_EN
- PSW_F
- PSW_G
- PSW_H
- PSW_HI_CB
- PSW_I
- PSW_INTL_1
- PSW_KERNEL_BITS
- PSW_L
- PSW_M
- PSW_MASK_ADDR_MODE
- PSW_MASK_ASC
- PSW_MASK_BA
- PSW_MASK_BASE
- PSW_MASK_CC
- PSW_MASK_DAT
- PSW_MASK_EA
- PSW_MASK_EXT
- PSW_MASK_IO
- PSW_MASK_KEY
- PSW_MASK_MCHECK
- PSW_MASK_PER
- PSW_MASK_PM
- PSW_MASK_PSTATE
- PSW_MASK_RI
- PSW_MASK_UNASSIGNED
- PSW_MASK_USER
- PSW_MASK_WAIT
- PSW_N
- PSW_O
- PSW_P
- PSW_POWER_CTRL
- PSW_Q
- PSW_R
- PSW_S
- PSW_SM_D
- PSW_SM_I
- PSW_SM_P
- PSW_SM_Q
- PSW_SM_QUIET
- PSW_SM_R
- PSW_SM_W
- PSW_SYSTEM
- PSW_T
- PSW_USER_BITS
- PSW_V
- PSW_W
- PSW_W_BIT
- PSW_W_SM
- PSW_X
- PSW_Y
- PSW_Z
- PSW_clr
- PSW_init
- PSW_mskAEN
- PSW_mskBE
- PSW_mskCPL
- PSW_mskDEX
- PSW_mskDME
- PSW_mskDRBE
- PSW_mskDT
- PSW_mskGIE
- PSW_mskHSS
- PSW_mskIFCON
- PSW_mskIME
- PSW_mskINTL
- PSW_mskIT
- PSW_mskPOM
- PSW_mskWBNA
- PSW_offAEN
- PSW_offBE
- PSW_offCPL
- PSW_offDEX
- PSW_offDME
- PSW_offDRBE
- PSW_offDT
- PSW_offGIE
- PSW_offHSS
- PSW_offIFCON
- PSW_offIME
- PSW_offINTL
- PSW_offIT
- PSW_offPOM
- PSW_offWBNA
- PSW_valINIT
- PSW_valWBNA
- PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK
- PSX80_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT
- PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK
- PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT
- PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK
- PSX80_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT
- PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__SPARE_REGS_MASK
- PSX80_BIF_CPM_CONTROL__SPARE_REGS__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT
- PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK
- PSX80_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT
- PSX80_BIF_LM_CONTROL__LoopbackFifoPtr_MASK
- PSX80_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT
- PSX80_BIF_LM_CONTROL__LoopbackHalfRate_MASK
- PSX80_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT
- PSX80_BIF_LM_CONTROL__LoopbackSelect_MASK
- PSX80_BIF_LM_CONTROL__LoopbackSelect__SHIFT
- PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK
- PSX80_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT
- PSX80_BIF_LM_LANEENABLE__LANE_enable_MASK
- PSX80_BIF_LM_LANEENABLE__LANE_enable__SHIFT
- PSX80_BIF_LM_PCIERXMUX0__RXLANE0_MASK
- PSX80_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT
- PSX80_BIF_LM_PCIERXMUX0__RXLANE1_MASK
- PSX80_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT
- PSX80_BIF_LM_PCIERXMUX0__RXLANE2_MASK
- PSX80_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT
- PSX80_BIF_LM_PCIERXMUX0__RXLANE3_MASK
- PSX80_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT
- PSX80_BIF_LM_PCIERXMUX1__RXLANE4_MASK
- PSX80_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT
- PSX80_BIF_LM_PCIERXMUX1__RXLANE5_MASK
- PSX80_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT
- PSX80_BIF_LM_PCIERXMUX1__RXLANE6_MASK
- PSX80_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT
- PSX80_BIF_LM_PCIERXMUX1__RXLANE7_MASK
- PSX80_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT
- PSX80_BIF_LM_PCIERXMUX2__RXLANE10_MASK
- PSX80_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT
- PSX80_BIF_LM_PCIERXMUX2__RXLANE11_MASK
- PSX80_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT
- PSX80_BIF_LM_PCIERXMUX2__RXLANE8_MASK
- PSX80_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT
- PSX80_BIF_LM_PCIERXMUX2__RXLANE9_MASK
- PSX80_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT
- PSX80_BIF_LM_PCIERXMUX3__RXLANE12_MASK
- PSX80_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT
- PSX80_BIF_LM_PCIERXMUX3__RXLANE13_MASK
- PSX80_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT
- PSX80_BIF_LM_PCIERXMUX3__RXLANE14_MASK
- PSX80_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT
- PSX80_BIF_LM_PCIERXMUX3__RXLANE15_MASK
- PSX80_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT
- PSX80_BIF_LM_PCIETXMUX0__TXLANE0_MASK
- PSX80_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT
- PSX80_BIF_LM_PCIETXMUX0__TXLANE1_MASK
- PSX80_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT
- PSX80_BIF_LM_PCIETXMUX0__TXLANE2_MASK
- PSX80_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT
- PSX80_BIF_LM_PCIETXMUX0__TXLANE3_MASK
- PSX80_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT
- PSX80_BIF_LM_PCIETXMUX1__TXLANE4_MASK
- PSX80_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT
- PSX80_BIF_LM_PCIETXMUX1__TXLANE5_MASK
- PSX80_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT
- PSX80_BIF_LM_PCIETXMUX1__TXLANE6_MASK
- PSX80_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT
- PSX80_BIF_LM_PCIETXMUX1__TXLANE7_MASK
- PSX80_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT
- PSX80_BIF_LM_PCIETXMUX2__TXLANE10_MASK
- PSX80_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT
- PSX80_BIF_LM_PCIETXMUX2__TXLANE11_MASK
- PSX80_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT
- PSX80_BIF_LM_PCIETXMUX2__TXLANE8_MASK
- PSX80_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT
- PSX80_BIF_LM_PCIETXMUX2__TXLANE9_MASK
- PSX80_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT
- PSX80_BIF_LM_PCIETXMUX3__TXLANE12_MASK
- PSX80_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT
- PSX80_BIF_LM_PCIETXMUX3__TXLANE13_MASK
- PSX80_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT
- PSX80_BIF_LM_PCIETXMUX3__TXLANE14_MASK
- PSX80_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT
- PSX80_BIF_LM_PCIETXMUX3__TXLANE15_MASK
- PSX80_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK
- PSX80_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK
- PSX80_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT
- PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK
- PSX80_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMDeemph3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMTxEn3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK
- PSX80_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff0_MASK
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff1_MASK
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff2_MASK
- PSX80_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK
- PSX80_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT
- PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK
- PSX80_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK
- PSX80_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT
- PSX80_BIF_LM_POWERCONTROL3__TxCoeff3_MASK
- PSX80_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LaneNum0_MASK
- PSX80_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LaneNum1_MASK
- PSX80_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LaneNum2_MASK
- PSX80_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LaneNum3_MASK
- PSX80_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LinkNum0_MASK
- PSX80_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LinkNum1_MASK
- PSX80_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LinkNum2_MASK
- PSX80_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__LinkNum3_MASK
- PSX80_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__SpcMode0_MASK
- PSX80_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__SpcMode1_MASK
- PSX80_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__SpcMode2_MASK
- PSX80_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT
- PSX80_BIF_LM_POWERCONTROL4__SpcMode3_MASK
- PSX80_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK
- PSX80_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK
- PSX80_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK
- PSX80_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK
- PSX80_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT
- PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK
- PSX80_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT
- PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- PSX80_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK
- PSX80_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT
- PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK
- PSX80_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- PSX80_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK
- PSX80_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT
- PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK
- PSX80_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK
- PSX80_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK
- PSX80_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK
- PSX80_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK
- PSX80_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK
- PSX80_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK
- PSX80_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK
- PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK
- PSX80_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK
- PSX80_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK
- PSX80_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT
- PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- PSX80_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK
- PSX80_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT
- PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK
- PSX80_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT
- PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- PSX80_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK
- PSX80_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- PSX80_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK
- PSX80_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT
- PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK
- PSX80_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT
- PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK
- PSX80_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT
- PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- PSX80_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK
- PSX80_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK
- PSX80_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT
- PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK
- PSX80_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT
- PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK
- PSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT
- PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK
- PSX80_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT
- PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK
- PSX80_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK
- PSX80_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK
- PSX80_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK
- PSX80_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK
- PSX80_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK
- PSX80_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK
- PSX80_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT
- PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK
- PSX80_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT
- PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK
- PSX80_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT
- PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK
- PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT
- PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK
- PSX80_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT
- PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK
- PSX80_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT
- PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK
- PSX80_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK
- PSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK
- PSX80_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK
- PSX80_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK
- PSX80_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK
- PSX80_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK
- PSX80_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT
- PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK
- PSX80_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT
- PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK
- PSX80_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT
- PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK
- PSX80_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT
- PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK
- PSX80_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK
- PSX80_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT
- PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK
- PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT
- PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK
- PSX80_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT
- PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK
- PSX80_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT
- PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK
- PSX80_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT
- PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK
- PSX80_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT
- PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK
- PSX80_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK
- PSX80_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK
- PSX80_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK
- PSX80_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK
- PSX80_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK
- PSX80_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK
- PSX80_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK
- PSX80_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK
- PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT
- PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK
- PSX80_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT
- PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK
- PSX80_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT
- PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK
- PSX80_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT
- PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK
- PSX80_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT
- PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK
- PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT
- PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK
- PSX80_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT
- PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK
- PSX80_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- PSX80_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK
- PSX80_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK
- PSX80_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT
- PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK
- PSX80_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT
- PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK
- PSX80_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT
- PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK
- PSX80_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT
- PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK
- PSX80_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT
- PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK
- PSX80_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT
- PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK
- PSX80_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT
- PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- PSX80_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK
- PSX80_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT
- PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK
- PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK
- PSX80_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK
- PSX80_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK
- PSX80_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT
- PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK
- PSX80_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT
- PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK
- PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT
- PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK
- PSX80_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK
- PSX80_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT
- PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK
- PSX80_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT
- PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK
- PSX80_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT
- PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK
- PSX80_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT
- PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK
- PSX80_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK
- PSX80_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK
- PSX80_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETCPM_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETHLTR_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETLC_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETLC__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETMNTR_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETPCFG_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETPHY0_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETPHY1_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETPIF0_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETPIF1_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK
- PSX80_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK
- PSX80_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK
- PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK
- PSX80_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT
- PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK
- PSX80_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT
- PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK
- PSX80_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT
- PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK
- PSX80_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT
- PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK
- PSX80_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT
- PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK
- PSX80_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK
- PSX80_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK
- PSX80_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK
- PSX80_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK
- PSX80_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK
- PSX80_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK
- PSX80_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK
- PSX80_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT
- PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK
- PSX80_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT
- PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK
- PSX80_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK
- PSX80_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK
- PSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK
- PSX80_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK
- PSX80_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__dsm_en_MASK
- PSX80_PHY0_COM_COMMON_DFX__dsm_en__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__dsm_sel_MASK
- PSX80_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__force_cdr_en_MASK
- PSX80_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK
- PSX80_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__nelb_en_MASK
- PSX80_PHY0_COM_COMMON_DFX__nelb_en__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK
- PSX80_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK
- PSX80_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT
- PSX80_PHY0_COM_COMMON_DFX__prbs_seed_MASK
- PSX80_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK
- PSX80_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK
- PSX80_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK
- PSX80_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK
- PSX80_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK
- PSX80_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT
- PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK
- PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
- PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK
- PSX80_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT
- PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK
- PSX80_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT
- PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK
- PSX80_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT
- PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK
- PSX80_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
- PSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
- PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK
- PSX80_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK
- PSX80_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT
- PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK
- PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT
- PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK
- PSX80_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK
- PSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK
- PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT
- PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK
- PSX80_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK
- PSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK
- PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT
- PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK
- PSX80_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK
- PSX80_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK
- PSX80_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK
- PSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK
- PSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK
- PSX80_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK
- PSX80_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK
- PSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK
- PSX80_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK
- PSX80_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK
- PSX80_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK
- PSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK
- PSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK
- PSX80_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT
- PSX80_PHY0_TX_DFX_BROADCAST__felb_en_MASK
- PSX80_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_BROADCAST__obs_en_MASK
- PSX80_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_BROADCAST__obs_sel_MASK
- PSX80_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_BROADCAST__prbs_en_MASK
- PSX80_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE0__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE0__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE0__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE0__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE0__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE0__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE0__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE0__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE1__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE1__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE1__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE1__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE1__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE1__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE1__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE1__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE2__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE2__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE2__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE2__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE2__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE2__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE2__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE2__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE3__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE3__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE3__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE3__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE3__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE3__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE3__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE3__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE4__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE4__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE4__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE4__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE4__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE4__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE4__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE4__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE5__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE5__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE5__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE5__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE5__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE5__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE5__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE5__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE6__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE6__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE6__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE6__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE6__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE6__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE6__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE6__prbs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE7__felb_en_MASK
- PSX80_PHY0_TX_DFX_LANE7__felb_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE7__obs_en_MASK
- PSX80_PHY0_TX_DFX_LANE7__obs_en__SHIFT
- PSX80_PHY0_TX_DFX_LANE7__obs_sel_MASK
- PSX80_PHY0_TX_DFX_LANE7__obs_sel__SHIFT
- PSX80_PHY0_TX_DFX_LANE7__prbs_en_MASK
- PSX80_PHY0_TX_DFX_LANE7__prbs_en__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK
- PSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK
- PSX80_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT
- PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT
- PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK
- PSX80_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK
- PSX80_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK
- PSX80_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK
- PSX80_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK
- PSX80_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT
- PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK
- PSX80_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK
- PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT
- PSX80_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT
- PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK
- PSX80_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT
- PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK
- PSX80_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT
- PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK
- PSX80_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT
- PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK
- PSX80_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT
- PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK
- PSX80_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT
- PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK
- PSX80_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK
- PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK
- PSX80_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK
- PSX80_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK
- PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK
- PSX80_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_STATUS_MASK
- PSX80_PIF0_CTRL__PIF_PLL_STATUS__SHIFT
- PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK
- PSX80_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT
- PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK
- PSX80_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK
- PSX80_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_00_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_01_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_02_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_03_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_04_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_05_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_06_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_07_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_08_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_09_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_10_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_11_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_12_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_13_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_14_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT
- PSX80_PIF0_HW_DEBUG__HW_15_DEBUG_MASK
- PSX80_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT
- PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK
- PSX80_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK
- PSX80_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK
- PSX80_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK
- PSX80_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__FREQDIV_0_MASK
- PSX80_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__GANGMODE_0_MASK
- PSX80_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK
- PSX80_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK
- PSX80_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK
- PSX80_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK
- PSX80_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK
- PSX80_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK
- PSX80_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__RXPWR_0_MASK
- PSX80_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK
- PSX80_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK
- PSX80_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT
- PSX80_PIF0_LANE0_OVRD2__TXPWR_0_MASK
- PSX80_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK
- PSX80_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK
- PSX80_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT
- PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK
- PSX80_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK
- PSX80_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK
- PSX80_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK
- PSX80_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__FREQDIV_1_MASK
- PSX80_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__GANGMODE_1_MASK
- PSX80_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK
- PSX80_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK
- PSX80_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK
- PSX80_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK
- PSX80_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK
- PSX80_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK
- PSX80_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__RXPWR_1_MASK
- PSX80_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK
- PSX80_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK
- PSX80_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT
- PSX80_PIF0_LANE1_OVRD2__TXPWR_1_MASK
- PSX80_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK
- PSX80_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK
- PSX80_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT
- PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK
- PSX80_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK
- PSX80_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK
- PSX80_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK
- PSX80_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__FREQDIV_2_MASK
- PSX80_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__GANGMODE_2_MASK
- PSX80_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK
- PSX80_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK
- PSX80_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK
- PSX80_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK
- PSX80_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK
- PSX80_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK
- PSX80_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__RXPWR_2_MASK
- PSX80_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK
- PSX80_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK
- PSX80_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT
- PSX80_PIF0_LANE2_OVRD2__TXPWR_2_MASK
- PSX80_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK
- PSX80_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK
- PSX80_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT
- PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK
- PSX80_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK
- PSX80_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK
- PSX80_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK
- PSX80_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__FREQDIV_3_MASK
- PSX80_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__GANGMODE_3_MASK
- PSX80_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK
- PSX80_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK
- PSX80_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK
- PSX80_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK
- PSX80_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK
- PSX80_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK
- PSX80_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__RXPWR_3_MASK
- PSX80_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK
- PSX80_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK
- PSX80_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT
- PSX80_PIF0_LANE3_OVRD2__TXPWR_3_MASK
- PSX80_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK
- PSX80_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK
- PSX80_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT
- PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK
- PSX80_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK
- PSX80_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK
- PSX80_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK
- PSX80_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__FREQDIV_4_MASK
- PSX80_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__GANGMODE_4_MASK
- PSX80_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK
- PSX80_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK
- PSX80_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK
- PSX80_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK
- PSX80_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK
- PSX80_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK
- PSX80_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__RXPWR_4_MASK
- PSX80_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK
- PSX80_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK
- PSX80_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT
- PSX80_PIF0_LANE4_OVRD2__TXPWR_4_MASK
- PSX80_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK
- PSX80_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK
- PSX80_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT
- PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK
- PSX80_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK
- PSX80_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK
- PSX80_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK
- PSX80_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__FREQDIV_5_MASK
- PSX80_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__GANGMODE_5_MASK
- PSX80_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK
- PSX80_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK
- PSX80_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK
- PSX80_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK
- PSX80_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK
- PSX80_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK
- PSX80_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__RXPWR_5_MASK
- PSX80_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK
- PSX80_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK
- PSX80_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT
- PSX80_PIF0_LANE5_OVRD2__TXPWR_5_MASK
- PSX80_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK
- PSX80_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK
- PSX80_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT
- PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK
- PSX80_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK
- PSX80_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK
- PSX80_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK
- PSX80_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__FREQDIV_6_MASK
- PSX80_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__GANGMODE_6_MASK
- PSX80_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK
- PSX80_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK
- PSX80_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK
- PSX80_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK
- PSX80_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK
- PSX80_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK
- PSX80_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__RXPWR_6_MASK
- PSX80_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK
- PSX80_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK
- PSX80_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT
- PSX80_PIF0_LANE6_OVRD2__TXPWR_6_MASK
- PSX80_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK
- PSX80_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK
- PSX80_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT
- PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK
- PSX80_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK
- PSX80_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK
- PSX80_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK
- PSX80_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__FREQDIV_7_MASK
- PSX80_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__GANGMODE_7_MASK
- PSX80_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK
- PSX80_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK
- PSX80_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK
- PSX80_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK
- PSX80_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK
- PSX80_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK
- PSX80_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__RXPWR_7_MASK
- PSX80_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK
- PSX80_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK
- PSX80_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT
- PSX80_PIF0_LANE7_OVRD2__TXPWR_7_MASK
- PSX80_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK
- PSX80_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT
- PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK
- PSX80_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT
- PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK
- PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT
- PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK
- PSX80_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT
- PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK
- PSX80_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT
- PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK
- PSX80_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT
- PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK
- PSX80_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT
- PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK
- PSX80_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK
- PSX80_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK
- PSX80_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK
- PSX80_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK
- PSX80_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK
- PSX80_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT
- PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK
- PSX80_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_S2_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK
- PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT
- PSX80_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT
- PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK
- PSX80_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT
- PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK
- PSX80_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT
- PSX80_PIF0_SCRATCH__PIF_SCRATCH_MASK
- PSX80_PIF0_SCRATCH__PIF_SCRATCH__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK
- PSX80_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK
- PSX80_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK
- PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK
- PSX80_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK
- PSX80_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK
- PSX80_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK
- PSX80_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK
- PSX80_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT
- PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK
- PSX80_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT
- PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK
- PSX80_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK
- PSX80_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK
- PSX80_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK
- PSX80_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK
- PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK
- PSX80_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK
- PSX80_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK
- PSX80_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK
- PSX80_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK
- PSX80_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK
- PSX80_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK
- PSX80_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT
- PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK
- PSX80_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_S2_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK
- PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT
- PSX80_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT
- PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK
- PSX80_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK
- PSX80_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT
- PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK
- PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT
- PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK
- PSX80_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK
- PSX80_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX80_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX80_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX80_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX80_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX80_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK
- PSX80_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK
- PSX80_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX80_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX80_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX80_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK
- PSX80_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT
- PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK
- PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT
- PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK
- PSX80_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT
- PSX80_WRP_BIOSTIMER_CMD__Microseconds_MASK
- PSX80_WRP_BIOSTIMER_CMD__Microseconds__SHIFT
- PSX80_WRP_BIOSTIMER_CNTL__ClockRate_MASK
- PSX80_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT
- PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK
- PSX80_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT
- PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK
- PSX80_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK
- PSX80_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK
- PSX80_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT
- PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK
- PSX80_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT
- PSX80_WRP_DTM_CNTL__Determinism_En_DTM_MASK
- PSX80_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy0_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy10_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy11_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy12_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy13_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy14_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy15_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy16_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy17_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy18_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy1_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy2_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy3_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy4_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy5_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy6_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy7_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy8_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT
- PSX80_WRP_DTM_CNTL__Dtm_Dummy9_MASK
- PSX80_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT
- PSX80_WRP_DTM_CNTL__TxClk1x_Cntl_MASK
- PSX80_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT
- PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK
- PSX80_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT
- PSX80_WRP_DTM_CNTL__Warm_RstTimer_MASK
- PSX80_WRP_DTM_CNTL__Warm_RstTimer__SHIFT
- PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK
- PSX80_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT
- PSX80_WRP_DTM_CNTL__refClk_Cntl_MASK
- PSX80_WRP_DTM_CNTL__refClk_Cntl__SHIFT
- PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK
- PSX80_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK
- PSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT
- PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK
- PSX80_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT
- PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK
- PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT
- PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK
- PSX80_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT
- PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK
- PSX80_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK
- PSX80_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT
- PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK
- PSX80_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT
- PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK
- PSX80_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK
- PSX80_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT
- PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK
- PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT
- PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK
- PSX80_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT
- PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK
- PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT
- PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK
- PSX80_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT
- PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK
- PSX80_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT
- PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK
- PSX80_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT
- PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK
- PSX80_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT
- PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK
- PSX80_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT
- PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK
- PSX80_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT
- PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK
- PSX80_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT
- PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK
- PSX80_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT
- PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK
- PSX80_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT
- PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK
- PSX80_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT
- PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK
- PSX80_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT
- PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK
- PSX80_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT
- PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK
- PSX80_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT
- PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK
- PSX80_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT
- PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK
- PSX80_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT
- PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK
- PSX80_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT
- PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK
- PSX80_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT
- PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK
- PSX80_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT
- PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK
- PSX80_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT
- PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK
- PSX80_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT
- PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK
- PSX80_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT
- PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK
- PSX80_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT
- PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK
- PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT
- PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK
- PSX80_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT
- PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK
- PSX80_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT
- PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK
- PSX80_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT
- PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK
- PSX80_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK
- PSX80_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT
- PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK
- PSX80_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT
- PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK
- PSX80_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT
- PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK
- PSX80_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT
- PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK
- PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT
- PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK
- PSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT
- PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK
- PSX80_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT
- PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK
- PSX80_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT
- PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK
- PSX80_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT
- PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK
- PSX80_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT
- PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK
- PSX81_BIF_CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT
- PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO_MASK
- PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_AUTO__SHIFT
- PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT_MASK
- PSX81_BIF_CPM_CONTROL__MASTER_PCIE_PLL_SELECT__SHIFT
- PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__SPARE_REGS_MASK
- PSX81_BIF_CPM_CONTROL__SPARE_REGS__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_GSKT_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_PERM_GATE_PLL_PDN__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_PIF_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT
- PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK
- PSX81_BIF_CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT
- PSX81_BIF_LM_CONTROL__LoopbackFifoPtr_MASK
- PSX81_BIF_LM_CONTROL__LoopbackFifoPtr__SHIFT
- PSX81_BIF_LM_CONTROL__LoopbackHalfRate_MASK
- PSX81_BIF_LM_CONTROL__LoopbackHalfRate__SHIFT
- PSX81_BIF_LM_CONTROL__LoopbackSelect_MASK
- PSX81_BIF_LM_CONTROL__LoopbackSelect__SHIFT
- PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect_MASK
- PSX81_BIF_LM_CONTROL__PRBSPCIeLbSelect__SHIFT
- PSX81_BIF_LM_LANEENABLE__LANE_enable_MASK
- PSX81_BIF_LM_LANEENABLE__LANE_enable__SHIFT
- PSX81_BIF_LM_PCIERXMUX0__RXLANE0_MASK
- PSX81_BIF_LM_PCIERXMUX0__RXLANE0__SHIFT
- PSX81_BIF_LM_PCIERXMUX0__RXLANE1_MASK
- PSX81_BIF_LM_PCIERXMUX0__RXLANE1__SHIFT
- PSX81_BIF_LM_PCIERXMUX0__RXLANE2_MASK
- PSX81_BIF_LM_PCIERXMUX0__RXLANE2__SHIFT
- PSX81_BIF_LM_PCIERXMUX0__RXLANE3_MASK
- PSX81_BIF_LM_PCIERXMUX0__RXLANE3__SHIFT
- PSX81_BIF_LM_PCIERXMUX1__RXLANE4_MASK
- PSX81_BIF_LM_PCIERXMUX1__RXLANE4__SHIFT
- PSX81_BIF_LM_PCIERXMUX1__RXLANE5_MASK
- PSX81_BIF_LM_PCIERXMUX1__RXLANE5__SHIFT
- PSX81_BIF_LM_PCIERXMUX1__RXLANE6_MASK
- PSX81_BIF_LM_PCIERXMUX1__RXLANE6__SHIFT
- PSX81_BIF_LM_PCIERXMUX1__RXLANE7_MASK
- PSX81_BIF_LM_PCIERXMUX1__RXLANE7__SHIFT
- PSX81_BIF_LM_PCIERXMUX2__RXLANE10_MASK
- PSX81_BIF_LM_PCIERXMUX2__RXLANE10__SHIFT
- PSX81_BIF_LM_PCIERXMUX2__RXLANE11_MASK
- PSX81_BIF_LM_PCIERXMUX2__RXLANE11__SHIFT
- PSX81_BIF_LM_PCIERXMUX2__RXLANE8_MASK
- PSX81_BIF_LM_PCIERXMUX2__RXLANE8__SHIFT
- PSX81_BIF_LM_PCIERXMUX2__RXLANE9_MASK
- PSX81_BIF_LM_PCIERXMUX2__RXLANE9__SHIFT
- PSX81_BIF_LM_PCIERXMUX3__RXLANE12_MASK
- PSX81_BIF_LM_PCIERXMUX3__RXLANE12__SHIFT
- PSX81_BIF_LM_PCIERXMUX3__RXLANE13_MASK
- PSX81_BIF_LM_PCIERXMUX3__RXLANE13__SHIFT
- PSX81_BIF_LM_PCIERXMUX3__RXLANE14_MASK
- PSX81_BIF_LM_PCIERXMUX3__RXLANE14__SHIFT
- PSX81_BIF_LM_PCIERXMUX3__RXLANE15_MASK
- PSX81_BIF_LM_PCIERXMUX3__RXLANE15__SHIFT
- PSX81_BIF_LM_PCIETXMUX0__TXLANE0_MASK
- PSX81_BIF_LM_PCIETXMUX0__TXLANE0__SHIFT
- PSX81_BIF_LM_PCIETXMUX0__TXLANE1_MASK
- PSX81_BIF_LM_PCIETXMUX0__TXLANE1__SHIFT
- PSX81_BIF_LM_PCIETXMUX0__TXLANE2_MASK
- PSX81_BIF_LM_PCIETXMUX0__TXLANE2__SHIFT
- PSX81_BIF_LM_PCIETXMUX0__TXLANE3_MASK
- PSX81_BIF_LM_PCIETXMUX0__TXLANE3__SHIFT
- PSX81_BIF_LM_PCIETXMUX1__TXLANE4_MASK
- PSX81_BIF_LM_PCIETXMUX1__TXLANE4__SHIFT
- PSX81_BIF_LM_PCIETXMUX1__TXLANE5_MASK
- PSX81_BIF_LM_PCIETXMUX1__TXLANE5__SHIFT
- PSX81_BIF_LM_PCIETXMUX1__TXLANE6_MASK
- PSX81_BIF_LM_PCIETXMUX1__TXLANE6__SHIFT
- PSX81_BIF_LM_PCIETXMUX1__TXLANE7_MASK
- PSX81_BIF_LM_PCIETXMUX1__TXLANE7__SHIFT
- PSX81_BIF_LM_PCIETXMUX2__TXLANE10_MASK
- PSX81_BIF_LM_PCIETXMUX2__TXLANE10__SHIFT
- PSX81_BIF_LM_PCIETXMUX2__TXLANE11_MASK
- PSX81_BIF_LM_PCIETXMUX2__TXLANE11__SHIFT
- PSX81_BIF_LM_PCIETXMUX2__TXLANE8_MASK
- PSX81_BIF_LM_PCIETXMUX2__TXLANE8__SHIFT
- PSX81_BIF_LM_PCIETXMUX2__TXLANE9_MASK
- PSX81_BIF_LM_PCIETXMUX2__TXLANE9__SHIFT
- PSX81_BIF_LM_PCIETXMUX3__TXLANE12_MASK
- PSX81_BIF_LM_PCIETXMUX3__TXLANE12__SHIFT
- PSX81_BIF_LM_PCIETXMUX3__TXLANE13_MASK
- PSX81_BIF_LM_PCIETXMUX3__TXLANE13__SHIFT
- PSX81_BIF_LM_PCIETXMUX3__TXLANE14_MASK
- PSX81_BIF_LM_PCIETXMUX3__TXLANE14__SHIFT
- PSX81_BIF_LM_PCIETXMUX3__TXLANE15_MASK
- PSX81_BIF_LM_PCIETXMUX3__TXLANE15__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMDeemph2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMLaneUnused2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMSkipBit2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxClkEn2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxEn2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMargin2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn1__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2_MASK
- PSX81_BIF_LM_POWERCONTROL1__LMTxMarginEn2__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0_MASK
- PSX81_BIF_LM_POWERCONTROL1__TxCoeffID0__SHIFT
- PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1_MASK
- PSX81_BIF_LM_POWERCONTROL1__TxCoeffID1__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMDeemph3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMDeemph3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMLaneUnused3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMSkipBit3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMTxClkEn3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMTxEn3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMTxEn3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMTxMargin3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3_MASK
- PSX81_BIF_LM_POWERCONTROL2__LMTxMarginEn3__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff0_MASK
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff0__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff1_MASK
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff1__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff2_MASK
- PSX81_BIF_LM_POWERCONTROL2__TxCoeff2__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2_MASK
- PSX81_BIF_LM_POWERCONTROL2__TxCoeffID2__SHIFT
- PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3_MASK
- PSX81_BIF_LM_POWERCONTROL2__TxCoeffID3__SHIFT
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0_MASK
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl0__SHIFT
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1_MASK
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl1__SHIFT
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2_MASK
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl2__SHIFT
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3_MASK
- PSX81_BIF_LM_POWERCONTROL3__RxEqCtl3__SHIFT
- PSX81_BIF_LM_POWERCONTROL3__TxCoeff3_MASK
- PSX81_BIF_LM_POWERCONTROL3__TxCoeff3__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LaneNum0_MASK
- PSX81_BIF_LM_POWERCONTROL4__LaneNum0__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LaneNum1_MASK
- PSX81_BIF_LM_POWERCONTROL4__LaneNum1__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LaneNum2_MASK
- PSX81_BIF_LM_POWERCONTROL4__LaneNum2__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LaneNum3_MASK
- PSX81_BIF_LM_POWERCONTROL4__LaneNum3__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LinkNum0_MASK
- PSX81_BIF_LM_POWERCONTROL4__LinkNum0__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LinkNum1_MASK
- PSX81_BIF_LM_POWERCONTROL4__LinkNum1__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LinkNum2_MASK
- PSX81_BIF_LM_POWERCONTROL4__LinkNum2__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__LinkNum3_MASK
- PSX81_BIF_LM_POWERCONTROL4__LinkNum3__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__SpcMode0_MASK
- PSX81_BIF_LM_POWERCONTROL4__SpcMode0__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__SpcMode1_MASK
- PSX81_BIF_LM_POWERCONTROL4__SpcMode1__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__SpcMode2_MASK
- PSX81_BIF_LM_POWERCONTROL4__SpcMode2__SHIFT
- PSX81_BIF_LM_POWERCONTROL4__SpcMode3_MASK
- PSX81_BIF_LM_POWERCONTROL4__SpcMode3__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0_MASK
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed0__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1_MASK
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed1__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2_MASK
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed2__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3_MASK
- PSX81_BIF_LM_POWERCONTROL__LMLinkSpeed3__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0_MASK
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd0__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1_MASK
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd1__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2_MASK
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd2__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3_MASK
- PSX81_BIF_LM_POWERCONTROL__LMRxPhyCmd3__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0_MASK
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd0__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1_MASK
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd1__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2_MASK
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd2__SHIFT
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3_MASK
- PSX81_BIF_LM_POWERCONTROL__LMTxPhyCmd3__SHIFT
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0_MASK
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade0__SHIFT
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1_MASK
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade1__SHIFT
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2_MASK
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade2__SHIFT
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3_MASK
- PSX81_BIF_LM_PRBSCONTROL__LMLaneDegrade3__SHIFT
- PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect_MASK
- PSX81_BIF_LM_PRBSCONTROL__PRBSPCIeSelect__SHIFT
- PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- PSX81_BIF_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS_MASK
- PSX81_BIF_PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT
- PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK
- PSX81_BIF_PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- PSX81_BIF_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK
- PSX81_BIF_PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT
- PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__MST_MEM_DS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__MST_MEM_LS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN_MASK
- PSX81_BIF_PCIE_CNTL2__MST_MEM_SD_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK
- PSX81_BIF_PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK
- PSX81_BIF_PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN_MASK
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN_MASK
- PSX81_BIF_PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK
- PSX81_BIF_PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK
- PSX81_BIF_PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK
- PSX81_BIF_PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK
- PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK
- PSX81_BIF_PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK
- PSX81_BIF_PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK
- PSX81_BIF_PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT
- PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- PSX81_BIF_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK
- PSX81_BIF_PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT
- PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK
- PSX81_BIF_PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT
- PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- PSX81_BIF_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK
- PSX81_BIF_PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- PSX81_BIF_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK
- PSX81_BIF_PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT
- PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK
- PSX81_BIF_PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT
- PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG_MASK
- PSX81_BIF_PCIE_CNTL__TX_CPL_DEBUG__SHIFT
- PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- PSX81_BIF_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK
- PSX81_BIF_PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN_MASK
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_LANE_EN__SHIFT
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN_MASK
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_PORT_EN__SHIFT
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT_MASK
- PSX81_BIF_PCIE_DEBUG_CNTL__DEBUG_SELECT__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_00_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_01_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_02_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_03_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_04_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_05_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_06_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_07_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_08_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_09_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_10_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_11_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_12_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_13_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_14_DEBUG__SHIFT
- PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG_MASK
- PSX81_BIF_PCIE_HW_DEBUG__HW_15_DEBUG__SHIFT
- PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK
- PSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT
- PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK
- PSX81_BIF_PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT
- PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN_MASK
- PSX81_BIF_PCIE_LC_PM_CNTL__LC_L1_POWER_GATING_EN__SHIFT
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40_MASK
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41_MASK
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42_MASK
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43_MASK
- PSX81_BIF_PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44_MASK
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45_MASK
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46_MASK
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47_MASK
- PSX81_BIF_PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24_MASK
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25_MASK
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26_MASK
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27_MASK
- PSX81_BIF_PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28_MASK
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29_MASK
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30_MASK
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31_MASK
- PSX81_BIF_PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32_MASK
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33_MASK
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34_MASK
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35_MASK
- PSX81_BIF_PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36_MASK
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37_MASK
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38_MASK
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39_MASK
- PSX81_BIF_PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT
- PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK
- PSX81_BIF_PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT
- PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK
- PSX81_BIF_PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT
- PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK
- PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT
- PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK
- PSX81_BIF_PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT
- PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK
- PSX81_BIF_PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT
- PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK
- PSX81_BIF_PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK
- PSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK
- PSX81_BIF_PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK
- PSX81_BIF_PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK
- PSX81_BIF_PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK
- PSX81_BIF_PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT_MASK
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_CHECKER_DEBUG_BUS_SELECT__SHIFT
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR_MASK
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_CLR__SHIFT
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK
- PSX81_BIF_PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT
- PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK
- PSX81_BIF_PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT
- PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK
- PSX81_BIF_PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT
- PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK
- PSX81_BIF_PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT
- PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK
- PSX81_BIF_PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_EN__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK
- PSX81_BIF_PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT
- PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK
- PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT
- PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK
- PSX81_BIF_PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT
- PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK
- PSX81_BIF_PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT
- PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK
- PSX81_BIF_PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT
- PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK
- PSX81_BIF_PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT
- PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK
- PSX81_BIF_PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK
- PSX81_BIF_PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK
- PSX81_BIF_PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK
- PSX81_BIF_PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG_MASK
- PSX81_BIF_PCIE_P_CNTL__P_ELASTDESKEW_HW_DEBUG__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK
- PSX81_BIF_PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK
- PSX81_BIF_PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN_MASK
- PSX81_BIF_PCIE_P_CNTL__P_PWRDN_EN__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG_MASK
- PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_HW_DEBUG__SHIFT
- PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE_MASK
- PSX81_BIF_PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT
- PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK
- PSX81_BIF_PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT
- PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK
- PSX81_BIF_PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT
- PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK
- PSX81_BIF_PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT
- PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK
- PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT
- PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK
- PSX81_BIF_PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT
- PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED_MASK
- PSX81_BIF_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- PSX81_BIF_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK
- PSX81_BIF_PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK
- PSX81_BIF_PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT
- PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK
- PSX81_BIF_PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT
- PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK
- PSX81_BIF_PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT
- PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK
- PSX81_BIF_PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT
- PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK
- PSX81_BIF_PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT
- PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK
- PSX81_BIF_PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT
- PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK
- PSX81_BIF_PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT
- PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- PSX81_BIF_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ARI_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_ECRC_GEN_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK
- PSX81_BIF_PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT
- PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN_MASK
- PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_DBG_I2C_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK
- PSX81_BIF_PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK
- PSX81_BIF_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_ECN1P1_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_FLR_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_INTERNAL_ERR_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK
- PSX81_BIF_PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT
- PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK
- PSX81_BIF_PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT
- PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK
- PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT
- PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK
- PSX81_BIF_PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK
- PSX81_BIF_PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT
- PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK
- PSX81_BIF_PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT
- PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK
- PSX81_BIF_PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT
- PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK
- PSX81_BIF_PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT
- PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK
- PSX81_BIF_PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK
- PSX81_BIF_PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_0__BIF_STRAPREG_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN_MASK
- PSX81_BIF_SWRST_COMMAND_1__CMDCFGEN__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETCPM_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETCPM__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETHLTR_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETHLTR__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB0__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETIMPARB1__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETLANEMUX__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETLC_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETLC__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETMNTR_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETMNTR__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETPCFG_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETPCFG__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETPHY0_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETPHY0__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETPHY1_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETPHY1__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETPIF0_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETPIF0__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETPIF1_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETPIF1__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETSRBM0__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETSRBM1__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS_MASK
- PSX81_BIF_SWRST_COMMAND_1__RESETWRAPREGS__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK_MASK
- PSX81_BIF_SWRST_COMMAND_1__SWITCHCLK__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0_MASK
- PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF0__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1_MASK
- PSX81_BIF_SWRST_COMMAND_1__SYNCIDLEPIF1__SHIFT
- PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP_MASK
- PSX81_BIF_SWRST_COMMAND_1__TOGGLESTRAP__SHIFT
- PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK
- PSX81_BIF_SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT
- PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE_MASK
- PSX81_BIF_SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT
- PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK
- PSX81_BIF_SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT
- PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE_MASK
- PSX81_BIF_SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN_MASK
- PSX81_BIF_SWRST_CONTROL_0__BIF_STRAPREG_RESETRCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__CMDCFG_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB0_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETIMPARB1_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETLANEMUX_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETLC_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETPHY1_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETPIF0_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETPIF1_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETSRBM0_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETSRBM1_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__RESETWRAPREGS_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF0_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN_MASK
- PSX81_BIF_SWRST_CONTROL_1__SYNCIDLEPIF1_RCEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN_MASK
- PSX81_BIF_SWRST_CONTROL_2__BIF_STRAPREG_RESETATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__CMDCFG_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB0_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETIMPARB1_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETLANEMUX_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETLC_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETPHY1_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETPIF0_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETPIF1_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETSRBM0_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETSRBM1_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__RESETWRAPREGS_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF0_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN_MASK
- PSX81_BIF_SWRST_CONTROL_3__SYNCIDLEPIF1_ATEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN_MASK
- PSX81_BIF_SWRST_CONTROL_4__BIF_STRAPREG_WRRESETEN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRCMDCFG_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB0_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETIMPARB1_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETLANEMUX_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETLC_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPHY1_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF0_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETPIF1_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM0_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETSRBM1_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRRESETWRAPREGS_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF0_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN_MASK
- PSX81_BIF_SWRST_CONTROL_5__WRSYNCIDLEPIF1_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN_MASK
- PSX81_BIF_SWRST_CONTROL_6__CONNECTWITHWRAPREGS_EN__SHIFT
- PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN_MASK
- PSX81_BIF_SWRST_CONTROL_6__WARMRESET_EN__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_HOLD__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__BYPASS_PIF_HOLD__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__HLDTRAIN_XFER_MODE__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__MUXSEL_XFER_MODE__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT
- PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK
- PSX81_BIF_SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_cdr_time__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_alg_sel__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_dfe_time__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_ber__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_fom_time__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_leq_time__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL1__adapt_cfg_oc_time__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_ref_loop_gain__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_dfe_tap_loop_gain__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_fom_loop_gain__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_leq_loop_gain__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_ofc_loop_gain__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_lt__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt_MASK
- PSX81_PHY0_COM_COMMON_ADAPTCTL2__adapt_cfg_pi_off_range_rt__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_dfe_tp2_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen12_pi_off_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1__adapt_cfg_gen3_pi_off_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_dfe_tp1_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_dcattn_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen12_leq_pole_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_dcattn_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL__adapt_cfg_gen3_leq_pole_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_exec__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_inst__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG1__adapt_dbg_apu_mode__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp1_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1__adapt_dbg_gen3_dfe_tp2_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_doff_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_eoff_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val_MASK
- PSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL__adapt_dbg_xoff_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val_MASK
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en_MASK
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_en__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12_MASK
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen12__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3_MASK
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_gain_gen3__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit_MASK
- PSX81_PHY0_COM_COMMON_CDR_FRCTL__cdr_fr_limit__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val_MASK
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_byp_val__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3_MASK
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_ph_gain_gen3__SHIFT
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3_MASK
- PSX81_PHY0_COM_COMMON_CDR_PHCTL__cdr_pi_stpsz_gen3__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__dsm_en_MASK
- PSX81_PHY0_COM_COMMON_DFX__dsm_en__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__dsm_sel_MASK
- PSX81_PHY0_COM_COMMON_DFX__dsm_sel__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__force_cdr_en_MASK
- PSX81_PHY0_COM_COMMON_DFX__force_cdr_en__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response_MASK
- PSX81_PHY0_COM_COMMON_DFX__hold_rdy_response__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__nelb_en_MASK
- PSX81_PHY0_COM_COMMON_DFX__nelb_en__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en_MASK
- PSX81_PHY0_COM_COMMON_DFX__ovrd_clk_en__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on_MASK
- PSX81_PHY0_COM_COMMON_DFX__ovrd_pll_on__SHIFT
- PSX81_PHY0_COM_COMMON_DFX__prbs_seed_MASK
- PSX81_PHY0_COM_COMMON_DFX__prbs_seed__SHIFT
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code_MASK
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_code__SHIFT
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel_MASK
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dac_test_ofc_sel__SHIFT
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0_MASK
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_dis_ps0__SHIFT
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal_MASK
- PSX81_PHY0_COM_COMMON_ELECIDLE__ei_det_initiate_ofc_cal__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_ph_gain_gen12__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_cdr_pi_stpsz_gen12__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_dll_flock_disable__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ei_det_thresh_sel__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_ron_ctl__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rtt_ctl__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_rxdetect_samp_time__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_spare__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid_MASK
- PSX81_PHY0_COM_COMMON_FUSE1__fuse1_valid__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare_MASK
- PSX81_PHY0_COM_COMMON_FUSE2__fuse2_spare__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid_MASK
- PSX81_PHY0_COM_COMMON_FUSE2__fuse2_valid__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_dll_cpi_sel__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_bw_adj__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_lcpll_ref_adj__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_refresh_cal_en__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ron_override_val__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_ropll_ref_adj__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_rtt_override_val__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_spare__SHIFT
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid_MASK
- PSX81_PHY0_COM_COMMON_FUSE3__fuse3_valid__SHIFT
- PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay_MASK
- PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgdelay__SHIFT
- PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask_MASK
- PSX81_PHY0_COM_COMMON_LANE_PWRMGMT__pgmask__SHIFT
- PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel_MASK
- PSX81_PHY0_COM_COMMON_LNCNTRL__cdr_lock_time_sel__SHIFT
- PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis_MASK
- PSX81_PHY0_COM_COMMON_LNCNTRL__clkgate_dis__SHIFT
- PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel_MASK
- PSX81_PHY0_COM_COMMON_LNCNTRL__dll_lock_time_sel__SHIFT
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom_MASK
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph35_gen2_nom__SHIFT
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom_MASK
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph60_gen2_nom__SHIFT
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom_MASK
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__deemph_gen1_nom__SHIFT
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom_MASK
- PSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM__tx_margin_nom__SHIFT
- PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel_MASK
- PSX81_PHY0_COM_COMMON_RXTESTDEBUG__rx2tx_bypass_sel__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_1__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_2__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_3__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH35__deemph_3pt5db_4__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_1__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_2__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_3__SHIFT
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4_MASK
- PSX81_PHY0_COM_COMMON_SELDEEMPH60__deemph_6db_4__SHIFT
- PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en_MASK
- PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_en__SHIFT
- PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel_MASK
- PSX81_PHY0_COM_COMMON_TXTESTDEBUG__test_single_leg_sel__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcPllSpare__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__FuseProcRefAdj__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciFuseProcess__PhyFuseValid__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ClearLockDetect__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__CpiDac__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLockTimer__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__FastLock__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__LpfRes__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__ManaregRampTimer__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__PllLocked__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllControl__VcoRange__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEnOvrd__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrEn__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRateOvrd__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__Clk2CtlrRate__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__FullRateClkEn__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__HalfRateClkEn__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllClkFreq__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode__PllFreqModeOvrd__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllMeasCtl__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1__PllTp__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_MeasOut__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PLL_Tpo__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ADCRefIn__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__AutoTrigRoCal__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalDone__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__CalFail__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ContinueCal__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__ManTrigRoCal__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3__PLL_AdcOut__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4__AltDiv__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl11_8__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5__VregCtl7_0__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate_MASK
- PSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn_MASK
- PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownEn__SHIFT
- PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd_MASK
- PSX81_PHY0_HTPLL_ROPLL_PowerDownEn__PllPowerDownOvrd__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl__LCTankI__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortForce__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControlExt__BgRcFiltShortTimer__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ClearLockDetect__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac3_0__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__CpiDac7_4__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLockTimer__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__FastLock__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__LpfRes__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__ManaregRampTimer__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__PllLocked__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRangeBin__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllControl__VcoRange__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEnOvrd__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__FullRateClkEn__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEnOvrd__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode__HalfRateClkEn__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllMeasCtl__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1__PllTp__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_MeasOut__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PLC_Tpo__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2__PllDsmObsSel__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ADCRefIn__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalDone__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__CalFail__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ContinueCal__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__FinalFbCnt__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__ManCalRdyNext__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__PLC_AdcOut__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3__StartCntEn__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4__AltDiv__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl11_8__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5__VregCtl7_0__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__MeasCycleCnt__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate_MASK
- PSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl__PllControlUpdate__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn_MASK
- PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownEn__SHIFT
- PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd_MASK
- PSX81_PHY0_LCPLL_LCPLL_PowerDownEn__PllPowerDownOvrd__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_BROADCAST__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE0__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE1__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE2__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE3__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE4__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE5__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE6__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_mode__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_down_time_sel__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_pwr_save_off__SHIFT
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel_MASK
- PSX81_PHY0_RX_ADAPTCTL_LANE7__adapt_cfg_track_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_BROADCAST__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE0__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE1__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE2__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE3__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE4__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE5__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE6__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_out__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_bus_sel__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_en__SHIFT
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst_MASK
- PSX81_PHY0_RX_ADAPTDBG1_LANE7__adapt_dbg_force_rst__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen12_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_dcattn_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_leq_pole_byp_en__SHIFT
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en_MASK
- PSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7__adapt_cfg_gen3_pi_off_byp_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__freq_div2__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__link_speed__SHIFT
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en_MASK
- PSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7__twosym_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6__rx_pwr__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__eidet_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pg_en__SHIFT
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr_MASK
- PSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7__rx_pwr__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_BROADCAST__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE0__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE1__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE2__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE3__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE4__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE5__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE6__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_doff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_eoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp1_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_gen3_dfe_tp2_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_leq_dcattn_byp_ovr_disable__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__adapt_dbg_xoff_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_fr_byp_en__SHIFT
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en_MASK
- PSX81_PHY0_RX_DBG_BYP_EN_LANE7__cdr_ph_byp_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_BROADCAST__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE0__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE1__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE2__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE3__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE4__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE5__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE6__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_analog_obs_en__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_clk_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_dbg_vreg_ref_sel__SHIFT
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl_MASK
- PSX81_PHY0_RX_DLL_CTL_LANE7__dll_surge_ctrl__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_async_ei__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_dac_test_en__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_comp_out__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_ofc_out_of_bounds__SHIFT
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj_MASK
- PSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7__ei_det_thresh_adj__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_BROADCAST__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE0__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE1__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE2__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE3__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE4__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE5__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE6__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__enable_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trk__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__request_trn__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__response_mode__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_eye_fom__SHIFT
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid_MASK
- PSX81_PHY0_RX_FOMCALCCTL_LANE7__rx_fom_valid__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_BROADCAST__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE0__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE1__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE2__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE3__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE4__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE5__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE6__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_clr__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__prbs_err__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_ac_cap__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_byp_res__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_dfr_force__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_leq_en__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_force_short_vdc_out__SHIFT
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate_MASK
- PSX81_PHY0_RX_RXTEST_REGS_LANE7__rx_raw_pin_gate__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_BROADCAST__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE0__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE1__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE2__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE3__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE4__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE5__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE6__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dac_vdc__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_data_sign__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_dfr_dis__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_term_mode__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_fixed_polarity__SHIFT
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri_MASK
- PSX81_PHY0_RX_RX_CTL_LANE7__rx_vdc_dac_tri__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__freq_div2__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__gang_mode__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__link_speed__SHIFT
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en_MASK
- PSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7__twosym_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6__tx_pwr__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pg_en__SHIFT
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr_MASK
- PSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7__tx_pwr__SHIFT
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_BROADCAST__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE0__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE1__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE2__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE3__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE4__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE5__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE6__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0_MASK
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_c0__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cm1__SHIFT
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1_MASK
- PSX81_PHY0_TX_DEEMPH_LANE7__gen3_coeff_cp1__SHIFT
- PSX81_PHY0_TX_DFX_BROADCAST__felb_en_MASK
- PSX81_PHY0_TX_DFX_BROADCAST__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_BROADCAST__obs_en_MASK
- PSX81_PHY0_TX_DFX_BROADCAST__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_BROADCAST__obs_sel_MASK
- PSX81_PHY0_TX_DFX_BROADCAST__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_BROADCAST__prbs_en_MASK
- PSX81_PHY0_TX_DFX_BROADCAST__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE0__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE0__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE0__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE0__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE0__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE0__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE0__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE0__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE1__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE1__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE1__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE1__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE1__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE1__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE1__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE1__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE2__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE2__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE2__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE2__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE2__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE2__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE2__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE2__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE3__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE3__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE3__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE3__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE3__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE3__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE3__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE3__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE4__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE4__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE4__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE4__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE4__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE4__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE4__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE4__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE5__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE5__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE5__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE5__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE5__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE5__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE5__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE5__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE6__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE6__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE6__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE6__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE6__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE6__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE6__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE6__prbs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE7__felb_en_MASK
- PSX81_PHY0_TX_DFX_LANE7__felb_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE7__obs_en_MASK
- PSX81_PHY0_TX_DFX_LANE7__obs_en__SHIFT
- PSX81_PHY0_TX_DFX_LANE7__obs_sel_MASK
- PSX81_PHY0_TX_DFX_LANE7__obs_sel__SHIFT
- PSX81_PHY0_TX_DFX_LANE7__prbs_en_MASK
- PSX81_PHY0_TX_DFX_LANE7__prbs_en__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__alloc_error__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__first_allocation_done__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_binary__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__ron_comp_valid__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__too_many_allocated__SHIFT
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated_MASK
- PSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7__total_legs_allocated__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE0__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE1__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE2__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE3__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE4__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE5__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE6__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__deemph35_sel__SHIFT
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel_MASK
- PSX81_PHY0_TX_TSTMARGDEEMPH_LANE7__txmarg_sel__SHIFT
- PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_BROADCAST__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE0__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE1__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE2__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE3__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE4__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE5__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE6__rxdetect_response__SHIFT
- PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response_MASK
- PSX81_PHY0_TX_TXCNTRL_LANE7__rxdetect_response__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_0__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_1__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_2__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_3__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_4__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_5__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_6__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_RX_RDY_7__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_0__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_1__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_2__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_3__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_4__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_5__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_6__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7_MASK
- PSX81_PIF0_BIF_CMD_STATUS__BPHY_CORE_TX_RDY_7__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_0__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_1__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_2__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_3__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_4__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_5__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_6__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7_MASK
- PSX81_PIF0_BIF_CMD_STATUS__RXPHYSTATUS_7__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_0__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_1__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_2__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_3__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_4__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_5__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_6__SHIFT
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7_MASK
- PSX81_PIF0_BIF_CMD_STATUS__TXPHYSTATUS_7__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PEND_PWR__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_IGNR_PWR_NOT_ON__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCHL_MODE__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_SCH_REQ_MODE__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_DIS__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE_MASK
- PSX81_PIF0_CMD_BUS_CTRL__CMD_BUS_STAG_MODE__SHIFT
- PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES_MASK
- PSX81_PIF0_CMD_BUS_CTRL__SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_0__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_1__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_2__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_3__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_4__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_5__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_6__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__CMD_BUS_LANE_DIS_7__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH_OVRD_EN__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__DEEMPH__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ_OVRD_EN__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__PLLFREQ__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__RESPONSEMODE_PIF_OVRD__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN_MASK
- PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG_OVRD_EN__SHIFT
- PSX81_PIF0_CMD_BUS_GLB_OVRD__TXMARG__SHIFT
- PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1_MASK
- PSX81_PIF0_CTRL__DTM_FORCE_FREQDIV_X1__SHIFT
- PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD_MASK
- PSX81_PIF0_CTRL__PHY_RST_PWROK_VDD__SHIFT
- PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE_MASK
- PSX81_PIF0_CTRL__PIF_DEGRADE_PWR_PLL_MODE__SHIFT
- PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG_MASK
- PSX81_PIF0_CTRL__PIF_LANEUNUSED_AFFECT_GANG__SHIFT
- PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE_MASK
- PSX81_PIF0_CTRL__PIF_PG_ABORT_DISABLE__SHIFT
- PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE_MASK
- PSX81_PIF0_CTRL__PIF_PG_EXIT_MODE__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE_MASK
- PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_OFF_VOTE__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE_MASK
- PSX81_PIF0_CTRL__PIF_PLL_DEGRADE_S2_VOTE__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT_MASK
- PSX81_PIF0_CTRL__PIF_PLL_HNDSHK_EARLY_ABORT__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT_MASK
- PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EARLY_EXIT__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN_MASK
- PSX81_PIF0_CTRL__PIF_PLL_PWRDN_EN__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_STATUS_MASK
- PSX81_PIF0_CTRL__PIF_PLL_STATUS__SHIFT
- PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE_MASK
- PSX81_PIF0_CTRL__PIF_PLL_UNUSED_OFF_VOTE__SHIFT
- PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X16_LANE_15_0_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_11_10_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_13_12_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_15_14_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_1_0_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_3_2_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_5_4_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_7_6_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X2_LANE_9_8_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X4_LANE_11_8_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X4_LANE_15_12_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X4_LANE_3_0_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X4_LANE_7_4_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X8_LANE_15_8_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD_MASK
- PSX81_PIF0_GLB_OVRD2__X8_LANE_7_0_OVRD__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_EN__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_0__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_1__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_2__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_3__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_4__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_5__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_6__SHIFT
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7_MASK
- PSX81_PIF0_GLB_OVRD__RXDETECT_OVERRIDE_VAL_7__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_00_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_00_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_01_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_01_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_02_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_02_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_03_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_03_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_04_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_04_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_05_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_05_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_06_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_06_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_07_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_07_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_08_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_08_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_09_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_09_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_10_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_10_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_11_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_11_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_12_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_12_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_13_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_13_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_14_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_14_DEBUG__SHIFT
- PSX81_PIF0_HW_DEBUG__HW_15_DEBUG_MASK
- PSX81_PIF0_HW_DEBUG__HW_15_DEBUG__SHIFT
- PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0_MASK
- PSX81_PIF0_LANE0_OVRD2__COEFFICIENTID_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0_MASK
- PSX81_PIF0_LANE0_OVRD2__COEFFICIENT_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0_MASK
- PSX81_PIF0_LANE0_OVRD2__ELECIDLEDETEN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0_MASK
- PSX81_PIF0_LANE0_OVRD2__ENABLEFOM_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__FREQDIV_0_MASK
- PSX81_PIF0_LANE0_OVRD2__FREQDIV_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__GANGMODE_0_MASK
- PSX81_PIF0_LANE0_OVRD2__GANGMODE_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0_MASK
- PSX81_PIF0_LANE0_OVRD2__LINKSPEED_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0_MASK
- PSX81_PIF0_LANE0_OVRD2__REQUESTFOM_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0_MASK
- PSX81_PIF0_LANE0_OVRD2__REQUESTTRK_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0_MASK
- PSX81_PIF0_LANE0_OVRD2__REQUESTTRN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0_MASK
- PSX81_PIF0_LANE0_OVRD2__RESPONSEMODE_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0_MASK
- PSX81_PIF0_LANE0_OVRD2__RXPGENABLE_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__RXPWR_0_MASK
- PSX81_PIF0_LANE0_OVRD2__RXPWR_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0_MASK
- PSX81_PIF0_LANE0_OVRD2__TWOSYMENABLE_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0_MASK
- PSX81_PIF0_LANE0_OVRD2__TXPGENABLE_0__SHIFT
- PSX81_PIF0_LANE0_OVRD2__TXPWR_0_MASK
- PSX81_PIF0_LANE0_OVRD2__TXPWR_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0_MASK
- PSX81_PIF0_LANE0_OVRD__CDREN_OVRD_VAL_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__COEFFICIENTID_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__COEFFICIENT_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__ELECIDLEDETEN_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__ENABLEFOM_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__FREQDIV_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__GANGMODE_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__LINKSPEED_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__REQUESTFOM_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__REQUESTTRK_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__REQUESTTRN_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__RESPONSEMODE_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__RXPGENABLE_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__RXPWR_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__TWOSYMENABLE_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__TXPGENABLE_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0_MASK
- PSX81_PIF0_LANE0_OVRD__TXPWR_OVRD_EN_0__SHIFT
- PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1_MASK
- PSX81_PIF0_LANE1_OVRD2__COEFFICIENTID_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1_MASK
- PSX81_PIF0_LANE1_OVRD2__COEFFICIENT_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1_MASK
- PSX81_PIF0_LANE1_OVRD2__ELECIDLEDETEN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1_MASK
- PSX81_PIF0_LANE1_OVRD2__ENABLEFOM_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__FREQDIV_1_MASK
- PSX81_PIF0_LANE1_OVRD2__FREQDIV_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__GANGMODE_1_MASK
- PSX81_PIF0_LANE1_OVRD2__GANGMODE_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1_MASK
- PSX81_PIF0_LANE1_OVRD2__LINKSPEED_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1_MASK
- PSX81_PIF0_LANE1_OVRD2__REQUESTFOM_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1_MASK
- PSX81_PIF0_LANE1_OVRD2__REQUESTTRK_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1_MASK
- PSX81_PIF0_LANE1_OVRD2__REQUESTTRN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1_MASK
- PSX81_PIF0_LANE1_OVRD2__RESPONSEMODE_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1_MASK
- PSX81_PIF0_LANE1_OVRD2__RXPGENABLE_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__RXPWR_1_MASK
- PSX81_PIF0_LANE1_OVRD2__RXPWR_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1_MASK
- PSX81_PIF0_LANE1_OVRD2__TWOSYMENABLE_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1_MASK
- PSX81_PIF0_LANE1_OVRD2__TXPGENABLE_1__SHIFT
- PSX81_PIF0_LANE1_OVRD2__TXPWR_1_MASK
- PSX81_PIF0_LANE1_OVRD2__TXPWR_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1_MASK
- PSX81_PIF0_LANE1_OVRD__CDREN_OVRD_VAL_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__COEFFICIENTID_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__COEFFICIENT_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__ELECIDLEDETEN_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__ENABLEFOM_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__FREQDIV_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__GANGMODE_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__LINKSPEED_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__REQUESTFOM_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__REQUESTTRK_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__REQUESTTRN_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__RESPONSEMODE_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__RXPGENABLE_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__RXPWR_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__TWOSYMENABLE_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__TXPGENABLE_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1_MASK
- PSX81_PIF0_LANE1_OVRD__TXPWR_OVRD_EN_1__SHIFT
- PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2_MASK
- PSX81_PIF0_LANE2_OVRD2__COEFFICIENTID_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2_MASK
- PSX81_PIF0_LANE2_OVRD2__COEFFICIENT_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2_MASK
- PSX81_PIF0_LANE2_OVRD2__ELECIDLEDETEN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2_MASK
- PSX81_PIF0_LANE2_OVRD2__ENABLEFOM_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__FREQDIV_2_MASK
- PSX81_PIF0_LANE2_OVRD2__FREQDIV_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__GANGMODE_2_MASK
- PSX81_PIF0_LANE2_OVRD2__GANGMODE_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2_MASK
- PSX81_PIF0_LANE2_OVRD2__LINKSPEED_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2_MASK
- PSX81_PIF0_LANE2_OVRD2__REQUESTFOM_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2_MASK
- PSX81_PIF0_LANE2_OVRD2__REQUESTTRK_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2_MASK
- PSX81_PIF0_LANE2_OVRD2__REQUESTTRN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2_MASK
- PSX81_PIF0_LANE2_OVRD2__RESPONSEMODE_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2_MASK
- PSX81_PIF0_LANE2_OVRD2__RXPGENABLE_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__RXPWR_2_MASK
- PSX81_PIF0_LANE2_OVRD2__RXPWR_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2_MASK
- PSX81_PIF0_LANE2_OVRD2__TWOSYMENABLE_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2_MASK
- PSX81_PIF0_LANE2_OVRD2__TXPGENABLE_2__SHIFT
- PSX81_PIF0_LANE2_OVRD2__TXPWR_2_MASK
- PSX81_PIF0_LANE2_OVRD2__TXPWR_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2_MASK
- PSX81_PIF0_LANE2_OVRD__CDREN_OVRD_VAL_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__COEFFICIENTID_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__COEFFICIENT_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__ELECIDLEDETEN_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__ENABLEFOM_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__FREQDIV_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__GANGMODE_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__LINKSPEED_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__REQUESTFOM_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__REQUESTTRK_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__REQUESTTRN_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__RESPONSEMODE_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__RXPGENABLE_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__RXPWR_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__TWOSYMENABLE_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__TXPGENABLE_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2_MASK
- PSX81_PIF0_LANE2_OVRD__TXPWR_OVRD_EN_2__SHIFT
- PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3_MASK
- PSX81_PIF0_LANE3_OVRD2__COEFFICIENTID_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3_MASK
- PSX81_PIF0_LANE3_OVRD2__COEFFICIENT_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3_MASK
- PSX81_PIF0_LANE3_OVRD2__ELECIDLEDETEN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3_MASK
- PSX81_PIF0_LANE3_OVRD2__ENABLEFOM_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__FREQDIV_3_MASK
- PSX81_PIF0_LANE3_OVRD2__FREQDIV_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__GANGMODE_3_MASK
- PSX81_PIF0_LANE3_OVRD2__GANGMODE_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3_MASK
- PSX81_PIF0_LANE3_OVRD2__LINKSPEED_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3_MASK
- PSX81_PIF0_LANE3_OVRD2__REQUESTFOM_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3_MASK
- PSX81_PIF0_LANE3_OVRD2__REQUESTTRK_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3_MASK
- PSX81_PIF0_LANE3_OVRD2__REQUESTTRN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3_MASK
- PSX81_PIF0_LANE3_OVRD2__RESPONSEMODE_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3_MASK
- PSX81_PIF0_LANE3_OVRD2__RXPGENABLE_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__RXPWR_3_MASK
- PSX81_PIF0_LANE3_OVRD2__RXPWR_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3_MASK
- PSX81_PIF0_LANE3_OVRD2__TWOSYMENABLE_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3_MASK
- PSX81_PIF0_LANE3_OVRD2__TXPGENABLE_3__SHIFT
- PSX81_PIF0_LANE3_OVRD2__TXPWR_3_MASK
- PSX81_PIF0_LANE3_OVRD2__TXPWR_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3_MASK
- PSX81_PIF0_LANE3_OVRD__CDREN_OVRD_VAL_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__COEFFICIENTID_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__COEFFICIENT_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__ELECIDLEDETEN_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__ENABLEFOM_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__FREQDIV_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__GANGMODE_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__LINKSPEED_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__REQUESTFOM_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__REQUESTTRK_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__REQUESTTRN_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__RESPONSEMODE_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__RXPGENABLE_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__RXPWR_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__TWOSYMENABLE_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__TXPGENABLE_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3_MASK
- PSX81_PIF0_LANE3_OVRD__TXPWR_OVRD_EN_3__SHIFT
- PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4_MASK
- PSX81_PIF0_LANE4_OVRD2__COEFFICIENTID_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4_MASK
- PSX81_PIF0_LANE4_OVRD2__COEFFICIENT_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4_MASK
- PSX81_PIF0_LANE4_OVRD2__ELECIDLEDETEN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4_MASK
- PSX81_PIF0_LANE4_OVRD2__ENABLEFOM_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__FREQDIV_4_MASK
- PSX81_PIF0_LANE4_OVRD2__FREQDIV_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__GANGMODE_4_MASK
- PSX81_PIF0_LANE4_OVRD2__GANGMODE_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4_MASK
- PSX81_PIF0_LANE4_OVRD2__LINKSPEED_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4_MASK
- PSX81_PIF0_LANE4_OVRD2__REQUESTFOM_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4_MASK
- PSX81_PIF0_LANE4_OVRD2__REQUESTTRK_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4_MASK
- PSX81_PIF0_LANE4_OVRD2__REQUESTTRN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4_MASK
- PSX81_PIF0_LANE4_OVRD2__RESPONSEMODE_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4_MASK
- PSX81_PIF0_LANE4_OVRD2__RXPGENABLE_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__RXPWR_4_MASK
- PSX81_PIF0_LANE4_OVRD2__RXPWR_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4_MASK
- PSX81_PIF0_LANE4_OVRD2__TWOSYMENABLE_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4_MASK
- PSX81_PIF0_LANE4_OVRD2__TXPGENABLE_4__SHIFT
- PSX81_PIF0_LANE4_OVRD2__TXPWR_4_MASK
- PSX81_PIF0_LANE4_OVRD2__TXPWR_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4_MASK
- PSX81_PIF0_LANE4_OVRD__CDREN_OVRD_VAL_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__COEFFICIENTID_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__COEFFICIENT_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__ELECIDLEDETEN_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__ENABLEFOM_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__FREQDIV_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__GANGMODE_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__LINKSPEED_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__REQUESTFOM_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__REQUESTTRK_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__REQUESTTRN_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__RESPONSEMODE_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__RXPGENABLE_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__RXPWR_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__TWOSYMENABLE_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__TXPGENABLE_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4_MASK
- PSX81_PIF0_LANE4_OVRD__TXPWR_OVRD_EN_4__SHIFT
- PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5_MASK
- PSX81_PIF0_LANE5_OVRD2__COEFFICIENTID_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5_MASK
- PSX81_PIF0_LANE5_OVRD2__COEFFICIENT_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5_MASK
- PSX81_PIF0_LANE5_OVRD2__ELECIDLEDETEN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5_MASK
- PSX81_PIF0_LANE5_OVRD2__ENABLEFOM_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__FREQDIV_5_MASK
- PSX81_PIF0_LANE5_OVRD2__FREQDIV_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__GANGMODE_5_MASK
- PSX81_PIF0_LANE5_OVRD2__GANGMODE_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5_MASK
- PSX81_PIF0_LANE5_OVRD2__LINKSPEED_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5_MASK
- PSX81_PIF0_LANE5_OVRD2__REQUESTFOM_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5_MASK
- PSX81_PIF0_LANE5_OVRD2__REQUESTTRK_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5_MASK
- PSX81_PIF0_LANE5_OVRD2__REQUESTTRN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5_MASK
- PSX81_PIF0_LANE5_OVRD2__RESPONSEMODE_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5_MASK
- PSX81_PIF0_LANE5_OVRD2__RXPGENABLE_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__RXPWR_5_MASK
- PSX81_PIF0_LANE5_OVRD2__RXPWR_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5_MASK
- PSX81_PIF0_LANE5_OVRD2__TWOSYMENABLE_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5_MASK
- PSX81_PIF0_LANE5_OVRD2__TXPGENABLE_5__SHIFT
- PSX81_PIF0_LANE5_OVRD2__TXPWR_5_MASK
- PSX81_PIF0_LANE5_OVRD2__TXPWR_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5_MASK
- PSX81_PIF0_LANE5_OVRD__CDREN_OVRD_VAL_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__COEFFICIENTID_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__COEFFICIENT_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__ELECIDLEDETEN_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__ENABLEFOM_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__FREQDIV_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__GANGMODE_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__LINKSPEED_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__REQUESTFOM_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__REQUESTTRK_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__REQUESTTRN_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__RESPONSEMODE_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__RXPGENABLE_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__RXPWR_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__TWOSYMENABLE_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__TXPGENABLE_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5_MASK
- PSX81_PIF0_LANE5_OVRD__TXPWR_OVRD_EN_5__SHIFT
- PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6_MASK
- PSX81_PIF0_LANE6_OVRD2__COEFFICIENTID_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6_MASK
- PSX81_PIF0_LANE6_OVRD2__COEFFICIENT_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6_MASK
- PSX81_PIF0_LANE6_OVRD2__ELECIDLEDETEN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6_MASK
- PSX81_PIF0_LANE6_OVRD2__ENABLEFOM_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__FREQDIV_6_MASK
- PSX81_PIF0_LANE6_OVRD2__FREQDIV_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__GANGMODE_6_MASK
- PSX81_PIF0_LANE6_OVRD2__GANGMODE_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6_MASK
- PSX81_PIF0_LANE6_OVRD2__LINKSPEED_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6_MASK
- PSX81_PIF0_LANE6_OVRD2__REQUESTFOM_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6_MASK
- PSX81_PIF0_LANE6_OVRD2__REQUESTTRK_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6_MASK
- PSX81_PIF0_LANE6_OVRD2__REQUESTTRN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6_MASK
- PSX81_PIF0_LANE6_OVRD2__RESPONSEMODE_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6_MASK
- PSX81_PIF0_LANE6_OVRD2__RXPGENABLE_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__RXPWR_6_MASK
- PSX81_PIF0_LANE6_OVRD2__RXPWR_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6_MASK
- PSX81_PIF0_LANE6_OVRD2__TWOSYMENABLE_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6_MASK
- PSX81_PIF0_LANE6_OVRD2__TXPGENABLE_6__SHIFT
- PSX81_PIF0_LANE6_OVRD2__TXPWR_6_MASK
- PSX81_PIF0_LANE6_OVRD2__TXPWR_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6_MASK
- PSX81_PIF0_LANE6_OVRD__CDREN_OVRD_VAL_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__COEFFICIENTID_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__COEFFICIENT_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__ELECIDLEDETEN_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__ENABLEFOM_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__FREQDIV_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__GANGMODE_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__LINKSPEED_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__REQUESTFOM_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__REQUESTTRK_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__REQUESTTRN_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__RESPONSEMODE_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__RXPGENABLE_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__RXPWR_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__TWOSYMENABLE_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__TXPGENABLE_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6_MASK
- PSX81_PIF0_LANE6_OVRD__TXPWR_OVRD_EN_6__SHIFT
- PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7_MASK
- PSX81_PIF0_LANE7_OVRD2__COEFFICIENTID_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7_MASK
- PSX81_PIF0_LANE7_OVRD2__COEFFICIENT_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7_MASK
- PSX81_PIF0_LANE7_OVRD2__ELECIDLEDETEN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7_MASK
- PSX81_PIF0_LANE7_OVRD2__ENABLEFOM_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__FREQDIV_7_MASK
- PSX81_PIF0_LANE7_OVRD2__FREQDIV_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__GANGMODE_7_MASK
- PSX81_PIF0_LANE7_OVRD2__GANGMODE_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7_MASK
- PSX81_PIF0_LANE7_OVRD2__LINKSPEED_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7_MASK
- PSX81_PIF0_LANE7_OVRD2__REQUESTFOM_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7_MASK
- PSX81_PIF0_LANE7_OVRD2__REQUESTTRK_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7_MASK
- PSX81_PIF0_LANE7_OVRD2__REQUESTTRN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7_MASK
- PSX81_PIF0_LANE7_OVRD2__RESPONSEMODE_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7_MASK
- PSX81_PIF0_LANE7_OVRD2__RXPGENABLE_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__RXPWR_7_MASK
- PSX81_PIF0_LANE7_OVRD2__RXPWR_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7_MASK
- PSX81_PIF0_LANE7_OVRD2__TWOSYMENABLE_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7_MASK
- PSX81_PIF0_LANE7_OVRD2__TXPGENABLE_7__SHIFT
- PSX81_PIF0_LANE7_OVRD2__TXPWR_7_MASK
- PSX81_PIF0_LANE7_OVRD2__TXPWR_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7_MASK
- PSX81_PIF0_LANE7_OVRD__CDREN_OVRD_VAL_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__COEFFICIENTID_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__COEFFICIENT_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__ELECIDLEDETEN_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__ENABLEFOM_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__FREQDIV_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__GANGMODE_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__LINKSPEED_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__REQUESTFOM_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__REQUESTTRK_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__REQUESTTRN_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__RESPONSEMODE_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__RXPGENABLE_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__RXPWR_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__TWOSYMENABLE_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__TXPGENABLE_OVRD_EN_7__SHIFT
- PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7_MASK
- PSX81_PIF0_LANE7_OVRD__TXPWR_OVRD_EN_7__SHIFT
- PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1_MASK
- PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_DIS_IN_PS1__SHIFT
- PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE_MASK
- PSX81_PIF0_RX_CTRL2__EI_DET_CYCLE_MODE__SHIFT
- PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME_MASK
- PSX81_PIF0_RX_CTRL2__EI_DET_OFF_TIME__SHIFT
- PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME_MASK
- PSX81_PIF0_RX_CTRL2__EI_DET_ON_TIME__SHIFT
- PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S_MASK
- PSX81_PIF0_RX_CTRL2__FORCE_CDREN_IN_L0S__SHIFT
- PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY_MASK
- PSX81_PIF0_RX_CTRL2__RXPHYSTATUS_DELAY__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE_MASK
- PSX81_PIF0_RX_CTRL2__RX_CDR_XTND_MODE__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI_MASK
- PSX81_PIF0_RX_CTRL2__RX_L0S_TO_L0_DETECT_EI__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE_MASK
- PSX81_PIF0_RX_CTRL2__RX_L1_PG_PHY_STATUS_MODE__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE_MASK
- PSX81_PIF0_RX_CTRL2__RX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT_MASK
- PSX81_PIF0_RX_CTRL2__RX_RDY_DASRT_COUNT__SHIFT
- PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT_MASK
- PSX81_PIF0_RX_CTRL2__RX_STATUS_DASRT_COUNT__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_L1__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_GATING_IN_UNUSED__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE_MODE__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_DEGRADE__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_INIT__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_OFF__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_PLL_OFF__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_S2_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_S2__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_SPDCHNG__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE_MASK
- PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED_MODE__SHIFT
- PSX81_PIF0_RX_CTRL__RXPWR_IN_UNUSED__SHIFT
- PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE_MASK
- PSX81_PIF0_RX_CTRL__RX_EI_DET_IN_PS2_DEGRADE__SHIFT
- PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT_MASK
- PSX81_PIF0_RX_CTRL__RX_HLD_EIE_COUNT__SHIFT
- PSX81_PIF0_SCRATCH__PIF_SCRATCH_MASK
- PSX81_PIF0_SCRATCH__PIF_SCRATCH__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR_MASK
- PSX81_PIF0_STRAP_0__STRAP_FORCE_OWN_MSTR__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_12__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_13__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_14__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_15__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_BIT_16__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE_MASK
- PSX81_PIF0_STRAP_0__STRAP_PIF_CDR_EN_MODE__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1_MASK
- PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS1__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2_MASK
- PSX81_PIF0_STRAP_0__STRAP_RX_DIS_HLD_EIE_IN_PS2__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER_MASK
- PSX81_PIF0_STRAP_0__STRAP_RX_EI_FILTER__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS_MASK
- PSX81_PIF0_STRAP_0__STRAP_RX_RDY_XTND_DIS__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS_MASK
- PSX81_PIF0_STRAP_0__STRAP_RX_STATUS_XTND_DIS__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS_MASK
- PSX81_PIF0_STRAP_0__STRAP_TX_RDY_XTND_DIS__SHIFT
- PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS_MASK
- PSX81_PIF0_STRAP_0__STRAP_TX_STATUS_XTND_DIS__SHIFT
- PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY_MASK
- PSX81_PIF0_TX_CTRL2__TXPHYSTATUS_DELAY__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1_MASK
- PSX81_PIF0_TX_CTRL2__TX_DELAY_FIFO_INIT_IN_S1__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG_MASK
- PSX81_PIF0_TX_CTRL2__TX_FIFO_INIT_UPCONFIG__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID_MASK
- PSX81_PIF0_TX_CTRL2__TX_FORCE_DATA_VALID__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE_MASK
- PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MODE__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP_MASK
- PSX81_PIF0_TX_CTRL2__TX_HIGH_IMP_STAG_MP__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY_MASK
- PSX81_PIF0_TX_CTRL2__TX_HIZ_TO_L0_DLY__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY_MASK
- PSX81_PIF0_TX_CTRL2__TX_L0_TO_HIZ_DLY__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE_MASK
- PSX81_PIF0_TX_CTRL2__TX_L1_PG_PHY_STATUS_MODE__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2_MASK
- PSX81_PIF0_TX_CTRL2__TX_LINKSPEED_ACK_IN_S2__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE_MASK
- PSX81_PIF0_TX_CTRL2__TX_OFF_PG_PHY_STATUS_MODE__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT_MASK
- PSX81_PIF0_TX_CTRL2__TX_RDY_DASRT_COUNT__SHIFT
- PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT_MASK
- PSX81_PIF0_TX_CTRL2__TX_STATUS_DASRT_COUNT__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_L1__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_GATING_IN_UNUSED__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE_MODE__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_DEGRADE__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_INIT__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_OFF__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_PLL_OFF__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_S2_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_S2__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_SPDCHNG__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE_MASK
- PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED_MODE__SHIFT
- PSX81_PIF0_TX_CTRL__TXPWR_IN_UNUSED__SHIFT
- PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT_MASK
- PSX81_WRP_BIF_INT_CNTL__INT_LINKAUTONOMOUSBWINT__SHIFT
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_MASK
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_MASK
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET__SHIFT
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_MASK
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT__SHIFT
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_MASK
- PSX81_WRP_BIF_LANE_EQUALIZATION_CNTL__STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET__SHIFT
- PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID_MASK
- PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_ID__SHIFT
- PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID_MASK
- PSX81_WRP_BIF_SSID__STRAP_BIF_SUBSYS_VEN_ID__SHIFT
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN_MASK
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_EN__SHIFT
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION_MASK
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_SOURCE_VALIDATION__SHIFT
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING_MASK
- PSX81_WRP_BIF_STRAP_ACS__STRAP_BIF_ACS_TRANSLATION_BLOCKING__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX81_WRP_BIF_STRAP_ASPM_A__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX81_WRP_BIF_STRAP_ASPM_B__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX81_WRP_BIF_STRAP_ASPM_C__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX81_WRP_BIF_STRAP_ASPM_D__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L0S_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY_MASK
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_L1_EXIT_LATENCY__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_BIF_PM_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1_MASK
- PSX81_WRP_BIF_STRAP_ASPM_E__STRAP_ENABLE_SIGNAL_EXIT_L1__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_CPL_ABORT_ERR_EN__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_ERR_REPORTING_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_INTERNAL_ERR_EN__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_AT_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_BE_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CFG_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_CPL_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_EP_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_IO_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_MSG_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR_MASK
- PSX81_WRP_BIF_STRAP_ERROR_IGNORE__STRAP_BIF_RX_IGNORE_TC_ERR__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_2VC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_AER_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ARI_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_ECN1P1_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_EN_DEC_TO_HIDDEN_REG__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_FORCE_MASTER_TIMEOUT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_GEN2_COMPLIANCE__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_LTR_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_MULTI_FUNC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_OBFF_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TL_ALT_BUF_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_1__STRAP_BIF_TPH_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_KILL_GEN3__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_MSI_MULTI_CAP__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN__SHIFT
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK
- PSX81_WRP_BIF_STRAP_FEATURE_EN_2__STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_CHECK_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_ECRC_GEN_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_FORCE_GEN3_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_GEN3_COMPLIANCE__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_CORE__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_A__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_B__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_C__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_D__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_DE_EMPHASIS_SEL__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_2P5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_5GT__SHIFT
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT_MASK
- PSX81_WRP_BIF_STRAP_LC_MISC_PORT_E__STRAP_BIF_LC_SPC_MODE_8GT__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_ALWAYS_USE_FAST_TXCLK__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_BIF_FORCE_GEN2_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_CORE__STRAP_PLL_CMP_FREQ_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_BYPASS_EQ__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_FS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_LF__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_EQ_SEARCH_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED_MASK
- PSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E__STRAP_BIF_TARGET_LINK_SPEED__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_A__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_B__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_C__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_D__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_INITIAL_N_FTS__SHIFT
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN_MASK
- PSX81_WRP_BIF_STRAP_LINK_TRAINING_E__STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_A__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_B__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_C__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_D__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_BCH_ECC_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_E2E_PREFIX_EN__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_EXTENDED_FMT_SUPPORTED__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_FIRST_RCVD_ERR_LOG__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MAX_PAYLOAD_SUPPORT__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_MC_ECRC_REGEN_SUPP__SHIFT
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL_MASK
- PSX81_WRP_BIF_STRAP_MISC_PORT_E__STRAP_BIF_POISONED_ADVISORY_NONFATAL__SHIFT
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG_MASK
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_BIF_PI_HW_DEBUG__SHIFT
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ_MASK
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PRBS_CLK_ADJ__SHIFT
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS_MASK
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS__SHIFT
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG_MASK
- PSX81_WRP_BIF_STRAP_PI_CNTL__STRAP_RXP_HW_DEBUG__SHIFT
- PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE_MASK
- PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_FORCE_CDR_MODE__SHIFT
- PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL_MASK
- PSX81_WRP_BIF_STRAP_TEST_DFT__STRAP_BIF_TX_TEST_ALL__SHIFT
- PSX81_WRP_BIOSTIMER_CMD__Microseconds_MASK
- PSX81_WRP_BIOSTIMER_CMD__Microseconds__SHIFT
- PSX81_WRP_BIOSTIMER_CNTL__ClockRate_MASK
- PSX81_WRP_BIOSTIMER_CNTL__ClockRate__SHIFT
- PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare_MASK
- PSX81_WRP_BIOSTIMER_DEBUG__Microseconds_compare__SHIFT
- PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0_MASK
- PSX81_WRP_CFG_LNC_WINDOW__CFG_LNC_WINDOW0__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_Enable__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_FastCkStable__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdIdle__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdRestart__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_cmdStart__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_delayOverride__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeCharz__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeMaintainLock__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeOverrideDelay__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_modeWidePhase__SHIFT
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare_MASK
- PSX81_WRP_DELAYLINE_COMMAND__CFG_DPC_spare__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_commandComplete__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_controllerIdle__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_freqRatio__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negAlignmentVld__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_negDelayValue__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_phaseLocked__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posAlignmentVld__SHIFT
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue_MASK
- PSX81_WRP_DELAYLINE_STATUS__DPC_CFG_posDelayValue__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Clk_2sym__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Dummy19__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_GsktClk_2sym__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Period__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Rcv__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_Sti_TXCLK_Send__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_earlyRst_slide__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_hardRst_slide__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__Dtm_txPhyStsOk_slide__SHIFT
- PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout_MASK
- PSX81_WRP_DTM_CNTL_LEGACY__fifoInit_one_dropout__SHIFT
- PSX81_WRP_DTM_CNTL__Determinism_En_DTM_MASK
- PSX81_WRP_DTM_CNTL__Determinism_En_DTM__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy0_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy0__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy10_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy10__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy11_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy11__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy12_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy12__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy13_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy13__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy14_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy14__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy15_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy15__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy16_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy16__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy17_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy17__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy18_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy18__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy1_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy1__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy2_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy2__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy3_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy3__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy4_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy4__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy5_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy5__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy6_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy6__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy7_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy7__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy8_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy8__SHIFT
- PSX81_WRP_DTM_CNTL__Dtm_Dummy9_MASK
- PSX81_WRP_DTM_CNTL__Dtm_Dummy9__SHIFT
- PSX81_WRP_DTM_CNTL__TxClk1x_Cntl_MASK
- PSX81_WRP_DTM_CNTL__TxClk1x_Cntl__SHIFT
- PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl_MASK
- PSX81_WRP_DTM_CNTL__TxClkGskt_Cntl__SHIFT
- PSX81_WRP_DTM_CNTL__Warm_RstTimer_MASK
- PSX81_WRP_DTM_CNTL__Warm_RstTimer__SHIFT
- PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer_MASK
- PSX81_WRP_DTM_CNTL__dtmClk_Sel_Timer__SHIFT
- PSX81_WRP_DTM_CNTL__refClk_Cntl_MASK
- PSX81_WRP_DTM_CNTL__refClk_Cntl__SHIFT
- PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl_MASK
- PSX81_WRP_DTM_CNTL__rxElasWidth_Cntl__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_dropoutTime_DI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_startTime_DI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x__DentistGate_stopTime_DI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_dropoutTime_DI_clkGskt__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_startTime_DI_clkGskt__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt__DentistGate_stopTime_DI_clkGskt__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_dropoutTime_FI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_startTime_FI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x__DentistGate_stopTime_FI_clk10x__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_dropoutTime_FI_clkGskt__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_startTime_FI_clkGskt__SHIFT
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt_MASK
- PSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt__DentistGate_stopTime_FI_clkGskt__SHIFT
- PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl_MASK
- PSX81_WRP_DTM_RX_BP_CNTL__Dbg_Cntl__SHIFT
- PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl_MASK
- PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_Cntl__SHIFT
- PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue_MASK
- PSX81_WRP_DTM_RX_BP_CNTL__rxElasBP_SlideValue__SHIFT
- PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override_MASK
- PSX81_WRP_DTM_RX_BP_CNTL__td_hold_training_override__SHIFT
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period_MASK
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Period__SHIFT
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv_MASK
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Rcv__SHIFT
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send_MASK
- PSX81_WRP_DTM_STI_LCLK_CTRL__Dtm_Sti_LCLK_Send__SHIFT
- PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0_MASK
- PSX81_WRP_IMPCTL_CNTL_PIF0__ArbEn0__SHIFT
- PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0_MASK
- PSX81_WRP_IMPCTL_CNTL_PIF0__QuickSimOverRide0__SHIFT
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1_MASK
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_BW_CNT_EN1__SHIFT
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2_MASK
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN2__SHIFT
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3_MASK
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_EN3__SHIFT
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4_MASK
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_OVRD_VAL4__SHIFT
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0_MASK
- PSX81_WRP_LNCNT_CONTROL__CFG_LNC_WINDOW_EN0__SHIFT
- PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0_MASK
- PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD0__SHIFT
- PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4_MASK
- PSX81_WRP_LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD4__SHIFT
- PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0_MASK
- PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT0__SHIFT
- PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16_MASK
- PSX81_WRP_LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT16__SHIFT
- PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC_MASK
- PSX81_WRP_LNC_BW_WACC__LNC_BW_WACC__SHIFT
- PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC_MASK
- PSX81_WRP_LNC_CMN_WACC__LNC_CMN_WACC__SHIFT
- PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC_MASK
- PSX81_WRP_LNC_TOTAL_WACC__LNC_TOTAL_WACC__SHIFT
- PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2_MASK
- PSX81_WRP_PCIE_EFUSE2__PCIE_EFUSE2__SHIFT
- PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3_MASK
- PSX81_WRP_PCIE_EFUSE3__PCIE_EFUSE3__SHIFT
- PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4_MASK
- PSX81_WRP_PCIE_EFUSE4__PCIE_EFUSE4__SHIFT
- PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5_MASK
- PSX81_WRP_PCIE_EFUSE5__PCIE_EFUSE5__SHIFT
- PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6_MASK
- PSX81_WRP_PCIE_EFUSE6__PCIE_EFUSE6__SHIFT
- PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7_MASK
- PSX81_WRP_PCIE_EFUSE7__PCIE_EFUSE7__SHIFT
- PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE_MASK
- PSX81_WRP_PCIE_EFUSE__PCIE_EFUSE__SHIFT
- PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING_MASK
- PSX81_WRP_PCIE_HOLD_TRAINING_A__HOLD_TRAINING__SHIFT
- PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING_MASK
- PSX81_WRP_PCIE_HOLD_TRAINING_B__HOLD_TRAINING__SHIFT
- PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING_MASK
- PSX81_WRP_PCIE_HOLD_TRAINING_C__HOLD_TRAINING__SHIFT
- PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING_MASK
- PSX81_WRP_PCIE_HOLD_TRAINING_D__HOLD_TRAINING__SHIFT
- PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING_MASK
- PSX81_WRP_PCIE_HOLD_TRAINING_E__HOLD_TRAINING__SHIFT
- PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG_MASK
- PSX81_WRP_PCIE_LINK_CONFIG__STRAP_BIF_LINK_CONFIG__SHIFT
- PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB_MASK
- PSX81_WRP_PCIE_PORT_IS_SB_A__PORT_IS_SB__SHIFT
- PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB_MASK
- PSX81_WRP_PCIE_PORT_IS_SB_B__PORT_IS_SB__SHIFT
- PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB_MASK
- PSX81_WRP_PCIE_PORT_IS_SB_C__PORT_IS_SB__SHIFT
- PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB_MASK
- PSX81_WRP_PCIE_PORT_IS_SB_D__PORT_IS_SB__SHIFT
- PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB_MASK
- PSX81_WRP_PCIE_PORT_IS_SB_E__PORT_IS_SB__SHIFT
- PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn_MASK
- PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrEn__SHIFT
- PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal_MASK
- PSX81_WRP_PCIE_RXDET_OVERRIDE__RxDetOvrVal__SHIFT
- PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE_MASK
- PSX81_WRP_PCIE_WRAP_DTM_MISC__DTM_BULKPHY_FREQDIV_OVERRIDE__SHIFT
- PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY_MASK
- PSX81_WRP_PCIE_WRAP_MISC__HOLD_TRAINING_STICKY__SHIFT
- PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START_MASK
- PSX81_WRP_PCIE_WRAP_MISC__STRAP_BIF_QUICKSIM_START__SHIFT
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI_MASK
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_DI__SHIFT
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI_MASK
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_ATSEL_FI__SHIFT
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI_MASK
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_DI__SHIFT
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI_MASK
- PSX81_WRP_PCIE_WRAP_PIF_MISC__DTM_PIF_DELAY_FI__SHIFT
- PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK_MASK
- PSX81_WRP_PCIE_WRAP_REG_TARG_MISC__CLKEN_MASK__SHIFT
- PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1_MASK
- PSX81_WRP_PCIE_WRAP_SCRATCH1__PCIE_WRAP_SCRATCH1__SHIFT
- PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2_MASK
- PSX81_WRP_PCIE_WRAP_SCRATCH2__PCIE_WRAP_SCRATCH2__SHIFT
- PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN_MASK
- PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_BIFCORE_REGISTER_DAISYCHAIN__SHIFT
- PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN_MASK
- PSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN__END_WRAPPER_REGISTER_DAISYCHAIN__SHIFT
- PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK
- PSX81_WRP_REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT
- PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK
- PSX81_WRP_REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT
- PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK
- PSX81_WRP_REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT
- PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK
- PSX81_WRP_REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT
- PSYCHO_CEAFSR_BLK
- PSYCHO_CEAFSR_BMSK
- PSYCHO_CEAFSR_DOFF
- PSYCHO_CEAFSR_ESYND
- PSYCHO_CEAFSR_MID
- PSYCHO_CEAFSR_PDRD
- PSYCHO_CEAFSR_PDWR
- PSYCHO_CEAFSR_PPIO
- PSYCHO_CEAFSR_RESV1
- PSYCHO_CEAFSR_RESV2
- PSYCHO_CEAFSR_SDRD
- PSYCHO_CEAFSR_SDWR
- PSYCHO_CEAFSR_SPIO
- PSYCHO_CE_AFAR
- PSYCHO_CE_AFSR
- PSYCHO_CONFIGSPACE
- PSYCHO_CONFIG_BASE
- PSYCHO_CONFIG_ENCODE
- PSYCHO_CONTROL
- PSYCHO_CONTROL_APCKEN
- PSYCHO_CONTROL_APERR
- PSYCHO_CONTROL_IAP
- PSYCHO_CONTROL_IGN
- PSYCHO_CONTROL_IMPL
- PSYCHO_CONTROL_MID
- PSYCHO_CONTROL_MODE
- PSYCHO_CONTROL_RESV
- PSYCHO_CONTROL_VER
- PSYCHO_ECCCTRL_CE
- PSYCHO_ECCCTRL_EE
- PSYCHO_ECCCTRL_UE
- PSYCHO_ECC_CTRL
- PSYCHO_ICLR_A_SLOT0
- PSYCHO_ICLR_SCSI
- PSYCHO_IMAP_A_SLOT0
- PSYCHO_IMAP_B_SLOT0
- PSYCHO_IOMMU_CONTROL
- PSYCHO_IOMMU_CTRL_DENAB
- PSYCHO_IOMMU_CTRL_ENAB
- PSYCHO_IOMMU_CTRL_LCKEN
- PSYCHO_IOMMU_CTRL_LCKPTR
- PSYCHO_IOMMU_CTRL_RESV
- PSYCHO_IOMMU_CTRL_RESV2
- PSYCHO_IOMMU_CTRL_TBWSZ
- PSYCHO_IOMMU_CTRL_TSBSZ
- PSYCHO_IOMMU_CTRL_XLTEERR
- PSYCHO_IOMMU_CTRL_XLTESTAT
- PSYCHO_IOMMU_DATA
- PSYCHO_IOMMU_DATA_CACHE
- PSYCHO_IOMMU_DATA_PPAGE
- PSYCHO_IOMMU_DATA_VALID
- PSYCHO_IOMMU_FLUSH
- PSYCHO_IOMMU_TAG
- PSYCHO_IOMMU_TAG_ERR
- PSYCHO_IOMMU_TAG_ERRSTS
- PSYCHO_IOMMU_TAG_SIZE
- PSYCHO_IOMMU_TAG_STREAM
- PSYCHO_IOMMU_TAG_VPAGE
- PSYCHO_IOMMU_TAG_WRITE
- PSYCHO_IOMMU_TSBBASE
- PSYCHO_IOMMU_TSBSZ_128K
- PSYCHO_IOMMU_TSBSZ_16K
- PSYCHO_IOMMU_TSBSZ_1K
- PSYCHO_IOMMU_TSBSZ_2K
- PSYCHO_IOMMU_TSBSZ_32K
- PSYCHO_IOMMU_TSBSZ_4K
- PSYCHO_IOMMU_TSBSZ_64K
- PSYCHO_IOMMU_TSBSZ_8K
- PSYCHO_IOSPACE_A
- PSYCHO_IOSPACE_B
- PSYCHO_IOSPACE_SIZE
- PSYCHO_IRQ_RETRY
- PSYCHO_MEMSPACE_A
- PSYCHO_MEMSPACE_B
- PSYCHO_MEMSPACE_SIZE
- PSYCHO_OBIO_IMAP_BASE
- PSYCHO_ONBOARD_IRQ_BASE
- PSYCHO_PCIAFSR_BLK
- PSYCHO_PCIAFSR_BMSK
- PSYCHO_PCIAFSR_MID
- PSYCHO_PCIAFSR_PMA
- PSYCHO_PCIAFSR_PPERR
- PSYCHO_PCIAFSR_PRTRY
- PSYCHO_PCIAFSR_PTA
- PSYCHO_PCIAFSR_RESV1
- PSYCHO_PCIAFSR_RESV2
- PSYCHO_PCIAFSR_RESV3
- PSYCHO_PCIAFSR_SMA
- PSYCHO_PCIAFSR_SPERR
- PSYCHO_PCIAFSR_SRTRY
- PSYCHO_PCIAFSR_STA
- PSYCHO_PCIA_CTRL
- PSYCHO_PCIA_DIAG
- PSYCHO_PCIB_CTRL
- PSYCHO_PCIB_DIAG
- PSYCHO_PCICTRL_AEN
- PSYCHO_PCICTRL_ARB_PARK
- PSYCHO_PCICTRL_EEN
- PSYCHO_PCICTRL_RESV1
- PSYCHO_PCICTRL_RESV2
- PSYCHO_PCICTRL_RESV3
- PSYCHO_PCICTRL_RESV4
- PSYCHO_PCICTRL_SBH_ERR
- PSYCHO_PCICTRL_SBH_INT
- PSYCHO_PCICTRL_SERR
- PSYCHO_PCICTRL_SPEED
- PSYCHO_PCICTRL_WEN
- PSYCHO_PCIDIAG_DDWSYNC
- PSYCHO_PCIDIAG_DISYNC
- PSYCHO_PCIDIAG_DRETRY
- PSYCHO_PCIDIAG_IDDPAR
- PSYCHO_PCIDIAG_IPAPAR
- PSYCHO_PCIDIAG_IPDPAR
- PSYCHO_PCIDIAG_LPBACK
- PSYCHO_PCIDIAG_RESV
- PSYCHO_PCI_AFAR_A
- PSYCHO_PCI_AFAR_B
- PSYCHO_PCI_AFSR_A
- PSYCHO_PCI_AFSR_B
- PSYCHO_STCERR_READ
- PSYCHO_STCERR_WRITE
- PSYCHO_STCLINE_EPTR
- PSYCHO_STCLINE_FOFN
- PSYCHO_STCLINE_LADDR
- PSYCHO_STCLINE_LINDX
- PSYCHO_STCLINE_SPTR
- PSYCHO_STCLINE_VALID
- PSYCHO_STCTAG_PPN
- PSYCHO_STCTAG_VALID
- PSYCHO_STCTAG_VPN
- PSYCHO_STCTAG_WRITE
- PSYCHO_STC_DATA_A
- PSYCHO_STC_DATA_B
- PSYCHO_STC_ERR_A
- PSYCHO_STC_ERR_B
- PSYCHO_STC_LINE_A
- PSYCHO_STC_LINE_B
- PSYCHO_STC_TAG_A
- PSYCHO_STC_TAG_B
- PSYCHO_STRBUF_CONTROL_A
- PSYCHO_STRBUF_CONTROL_B
- PSYCHO_STRBUF_CTRL_DENAB
- PSYCHO_STRBUF_CTRL_ENAB
- PSYCHO_STRBUF_CTRL_LENAB
- PSYCHO_STRBUF_CTRL_LPTR
- PSYCHO_STRBUF_CTRL_RRDIS
- PSYCHO_STRBUF_FLUSH_A
- PSYCHO_STRBUF_FLUSH_B
- PSYCHO_STRBUF_FSYNC_A
- PSYCHO_STRBUF_FSYNC_B
- PSYCHO_STRBUF_RERUN_DISABLE
- PSYCHO_STRBUF_RERUN_ENABLE
- PSYCHO_UEAFSR_BLK
- PSYCHO_UEAFSR_BMSK
- PSYCHO_UEAFSR_DOFF
- PSYCHO_UEAFSR_MID
- PSYCHO_UEAFSR_PDRD
- PSYCHO_UEAFSR_PDWR
- PSYCHO_UEAFSR_PPIO
- PSYCHO_UEAFSR_RESV1
- PSYCHO_UEAFSR_RESV2
- PSYCHO_UEAFSR_SDRD
- PSYCHO_UEAFSR_SDWR
- PSYCHO_UEAFSR_SPIO
- PSYCHO_UE_AFAR
- PSYCHO_UE_AFSR
- PSYSTEM_PARAMETER_BLOCK
- PSY_EVENT_PROP_CHANGED
- PSY_MAX_NAME_LEN
- PSY_NAME_MAX
- PSY_PROP
- PSZ_CIF
- PSZ_MAX
- PSZ_QCIF
- PSZ_QSIF
- PSZ_SIF
- PSZ_SQCIF
- PSZ_VGA
- PS_ACK
- PS_ACTIVE
- PS_ACTIVE_SET
- PS_ALL_ON
- PS_AUTO_POLL
- PS_AWAKE
- PS_BEACON_SYNC
- PS_BIT3
- PS_BIT4
- PS_BIT7
- PS_BIT8
- PS_C
- PS_CALLINC_MASK
- PS_CALLINC_SHIFT
- PS_CFG_MAX_ES_WR_CYCLE_BIT
- PS_CFG_MAX_FETCH_CYCLE_BIT
- PS_CFG_PFIFO_EMPTY_CNT_BIT
- PS_CFG_STARTCODE_WID_24_BIT
- PS_CLKSEL
- PS_CLKSEL_SHT
- PS_CODE_SET_ASCII
- PS_CODE_SET_BINARY
- PS_CODE_SET_UTF8
- PS_CONFIRM_INDEX
- PS_CONF_WAIT
- PS_CONNECTED
- PS_CTL
- PS_DEALLOC
- PS_DENY_DISCONNECT
- PS_DENY_DRV_INITIAL
- PS_DENY_DRV_REMOVE
- PS_DENY_IOCTL
- PS_DENY_JOIN
- PS_DENY_MGNT_TX
- PS_DENY_OTHERS
- PS_DENY_REASON
- PS_DENY_SCAN
- PS_DENY_SUSPEND
- PS_DEPTH_COUNT
- PS_DEPTH_COUNT_UDW
- PS_DESIGNATOR_EUI64
- PS_DESIGNATOR_NAA
- PS_DESIGNATOR_NAME
- PS_DESIGNATOR_T10
- PS_DISABLED
- PS_DISABLE_REQ_SENT
- PS_DISCONNECTED
- PS_DONE
- PS_DONE_TS
- PS_DPS
- PS_ENABLE
- PS_ENABLED
- PS_ENABLE_REQ_SENT
- PS_EXCM_BIT
- PS_FAST_INTERVAL
- PS_FAULT_DISCH
- PS_FAULT_FAST_OCP
- PS_FAULT_OCP
- PS_FAULT_OVP
- PS_FILTER_BILINEAR
- PS_FILTER_EDGE_ENHANCE
- PS_FILTER_MASK
- PS_FILTER_MEDIUM
- PS_HOLD_OFFSET
- PS_IMR_ENABLE
- PS_INT
- PS_INTLEVEL_MASK
- PS_INTLEVEL_SHIFT
- PS_INTLEVEL_WIDTH
- PS_INVOCATION_COUNT
- PS_INVOCATION_COUNT_UDW
- PS_ISR_ENABLE
- PS_IS_ACTIVE
- PS_IS_RF_ON
- PS_JOIN
- PS_LCLK
- PS_LCT
- PS_LINKUP_OFFSET
- PS_LP
- PS_M
- PS_MANUAL_POLL
- PS_MAX_INTERVAL
- PS_MISSING
- PS_MODE
- PS_MODE_ACTION_ENTER_PS
- PS_MODE_ACTION_EXIT_PS
- PS_MODE_ACTION_SLEEP_CONFIRMED
- PS_MODE_ACTIVE
- PS_MODE_AUTO
- PS_MODE_DTIM
- PS_MODE_IBSS
- PS_MODE_MAX
- PS_MODE_MIN
- PS_MODE_NUM
- PS_MODE_UAPSD
- PS_MODE_UAPSD_WMM
- PS_MODE_VOIP
- PS_MODE_WWLAN
- PS_NONE
- PS_OFF
- PS_OFF_BCN
- PS_OFF_VIF
- PS_OWB_MASK
- PS_OWB_SHIFT
- PS_OWB_WIDTH
- PS_PAGE_BUFFERS
- PS_PARTIAL_FLUSH
- PS_PHASE_MASK
- PS_PHASE_TRIP
- PS_PLANE_SEL
- PS_PLANE_SEL_MASK
- PS_PLANE_Y_SEL
- PS_PLANE_Y_SEL_MASK
- PS_PLL_VCO_MAX
- PS_PLL_VCO_MIN
- PS_PRIO
- PS_PWRUP_PROGRESS
- PS_PWR_GATE_DIS_OVERRIDE
- PS_PWR_GATE_SETTLING_TIME_128
- PS_PWR_GATE_SETTLING_TIME_32
- PS_PWR_GATE_SETTLING_TIME_64
- PS_PWR_GATE_SETTLING_TIME_96
- PS_PWR_GATE_SLPEN_16
- PS_PWR_GATE_SLPEN_24
- PS_PWR_GATE_SLPEN_32
- PS_PWR_GATE_SLPEN_8
- PS_RDY_CHECK
- PS_READY
- PS_REG
- PS_REPORT_EVENT_ID
- PS_RETRY
- PS_RF_OFF
- PS_RING_MASK
- PS_RING_SHIFT
- PS_S
- PS_SAVE_SET
- PS_SCALER_EN
- PS_SCALER_MODE_NORMAL
- PS_SCALER_MODE_PLANAR
- PS_SCROLL_SPEED
- PS_SEQ
- PS_SEQ_MASK
- PS_SLEEP
- PS_SNOOZE
- PS_STATE
- PS_STATE_AWAKE
- PS_STATE_FULL_POWER
- PS_STATE_HW
- PS_STATE_HW_MASK
- PS_STATE_MASK
- PS_STATE_PRE_SLEEP
- PS_STATE_S0
- PS_STATE_S1
- PS_STATE_S2
- PS_STATE_S3
- PS_STATE_S4
- PS_STATE_SLEEP
- PS_STATE_SLEEP_CFM
- PS_STAT_BAT_CHRG_DIR
- PS_STAT_VBAT_ABOVE_VHOLD
- PS_STAT_VBUS_ABOVE_VHOLD
- PS_STAT_VBUS_PRESENT
- PS_STAT_VBUS_TRIGGER
- PS_STAT_VBUS_VALID
- PS_STREAM
- PS_ST_ACTIVE
- PS_T
- PS_TIMEOUT_DISK
- PS_TIMEOUT_OTHER
- PS_TOGGLE
- PS_TO_REG
- PS_UM_BIT
- PS_UV_RGB_PHASE
- PS_VADAPT_EN
- PS_VADAPT_MODE_LEAST_ADAPT
- PS_VADAPT_MODE_MASK
- PS_VADAPT_MODE_MOD_ADAPT
- PS_VADAPT_MODE_MOST_ADAPT
- PS_VERSION
- PS_VERT3TAP
- PS_VERT_INT_INVERT_FIELD0
- PS_VERT_INT_INVERT_FIELD1
- PS_V_FILTER_BYPASS
- PS_WAIT_FOR_ANI
- PS_WAIT_FOR_BEACON
- PS_WAIT_FOR_CAB
- PS_WAIT_FOR_PSPOLL_DATA
- PS_WAIT_FOR_TX_ACK
- PS_WAKEUP
- PS_WIN_POS
- PS_WIN_SZ
- PS_WOE_BIT
- PS_WOE_MASK
- PS_Y_PHASE
- PSbIsNextTBTTWakeUp
- PSs
- PSvDisablePowerSaving
- PSvEnablePowerSaving
- PT
- PT1_FETCH_DELAY
- PT1_FETCH_DELAY_DELTA
- PT1_FE_CLK_20MHZ
- PT1_FE_CLK_25MHZ
- PT1_NR_ADAPS
- PT1_NR_BUFS
- PT1_NR_UPACKETS
- PT1_P1_REG
- PT1_P2_REG
- PT1_PAGE_SHIFT
- PT1_PAGE_SIZE
- PT2254_DBS_IN_10
- PT2254_DBS_IN_2
- PT2254_L_CHANNEL
- PT2254_R_CHANNEL
- PT2258_CMD_MUTE
- PT2258_CMD_RESET
- PT2258_CMD_UNMUTE
- PT2PT_LocalID
- PT2PT_RemoteID
- PT2_P1_REG
- PT2_P2_REG
- PT32E_ROOT_LEVEL
- PT32_BASE_ADDR_MASK
- PT32_DIR_BASE_ADDR_MASK
- PT32_DIR_PSE36_MASK
- PT32_DIR_PSE36_SHIFT
- PT32_DIR_PSE36_SIZE
- PT32_ENT_PER_PAGE
- PT32_INDEX
- PT32_LEVEL_BITS
- PT32_LEVEL_SHIFT
- PT32_LVL_ADDR_MASK
- PT32_LVL_OFFSET_MASK
- PT32_PT_BITS
- PT32_ROOT_LEVEL
- PT3_ACCESS_UNIT
- PT3_BUF_CANARY
- PT3_CMD_ADDR_INIT_DEMOD
- PT3_CMD_ADDR_INIT_TUNER
- PT3_CMD_ADDR_NORMAL
- PT3_FETCH_DELAY
- PT3_FETCH_DELAY_DELTA
- PT3_H
- PT3_I2C_BASE
- PT3_I2C_MAX
- PT3_I2C_RESET
- PT3_I2C_RUN
- PT3_INITIAL_BUF_DROPS
- PT3_NUM_FE
- PT4_P1_REG
- PT4_P2_REG
- PT5631_PDM_CMD_EXE
- PT64_BASE_ADDR_MASK
- PT64_ENT_PER_PAGE
- PT64_EPT_EXECUTABLE_MASK
- PT64_EPT_READABLE_MASK
- PT64_INDEX
- PT64_LEVEL_BITS
- PT64_LEVEL_SHIFT
- PT64_LVL_ADDR_MASK
- PT64_LVL_OFFSET_MASK
- PT64_NX_MASK
- PT64_NX_SHIFT
- PT64_PERM_MASK
- PT64_PT_BITS
- PT64_ROOT_4LEVEL
- PT64_ROOT_5LEVEL
- PT64_ROOT_MAX_LEVEL
- PT64_SECOND_AVAIL_BITS_SHIFT
- PTA0_DATA
- PTA0_FN
- PTA0_IN
- PTA0_OUT
- PTA1_DATA
- PTA1_FN
- PTA1_IN
- PTA1_OUT
- PTA2_DATA
- PTA2_FN
- PTA2_IN
- PTA2_OUT
- PTA3_DATA
- PTA3_FN
- PTA3_IN
- PTA3_OUT
- PTA4_DATA
- PTA4_FN
- PTA4_IN
- PTA4_OUT
- PTA5_DATA
- PTA5_FN
- PTA5_IN
- PTA5_OUT
- PTA6_DATA
- PTA6_FN
- PTA6_IN
- PTA6_OUT
- PTA7_DATA
- PTA7_FN
- PTA7_IN
- PTA7_OUT
- PTABLE_SIZE
- PTAG
- PTARGMS2SEG_END
- PTARGMS2SEG_START
- PTARGMS4SEG_END
- PTARGMS4SEG_START
- PTA_ACK_MODE_DEF
- PTA_AFH_LEVERAGE_ON_DEF
- PTA_ALLOW_PA_SD_DEF
- PTA_ANTENNA_TYPE_DEF
- PTA_ANTI_STARVE_NUM_CYCLE_DEF
- PTA_ANTI_STARVE_PERIOD_DEF
- PTA_AUTO_MODE_NO_CTS_DEF
- PTA_BT_HP_MAXTIME_DEF
- PTA_BT_HP_RESPECTED_DEF
- PTA_CMD_GET_DEVICES
- PTA_CYCLE_TIME_FAST_DEF
- PTA_ELP_HP_DEF
- PTA_HPDM_MAX_TIME_DEF
- PTA_MAX_NUM_CTS_DEF
- PTA_NUMBER_OF_BT_PACKETS_DEF
- PTA_NUMBER_OF_WLAN_PACKETS_DEF
- PTA_NUMBER_QUIET_CYCLE_DEF
- PTA_OFFSET_MASK
- PTA_PROTECTIVE_RX_TIME_DEF
- PTA_PROTECTIVE_RX_TIME_FAST_DEF
- PTA_PROTECTIVE_TX_TIME_DEF
- PTA_PROTECTIVE_TX_TIME_FAST_DEF
- PTA_RX_FOR_AVALANCHE_DEF
- PTA_SENSE_DISABLE_TIMER_DEF
- PTA_SIGNALING_TYPE_DEF
- PTA_SLOPE_MASK
- PTA_SLOPE_SHIFT
- PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF
- PTA_TIME_BEFORE_BEACON_DEF
- PTA_TIME_OUT_NEXT_WLAN_DEF
- PTA_WLAN_HP_MAX_TIME_DEF
- PTA_WLAN_RX_MIN_RATE_DEF
- PTB
- PTB0_DATA
- PTB0_FN
- PTB0_IN
- PTB0_OUT
- PTB1_DATA
- PTB1_FN
- PTB1_IN
- PTB1_OUT
- PTB2_DATA
- PTB2_FN
- PTB2_IN
- PTB2_OUT
- PTB3_DATA
- PTB3_FN
- PTB3_IN
- PTB3_OUT
- PTB4_DATA
- PTB4_FN
- PTB4_IN
- PTB4_OUT
- PTB5_DATA
- PTB5_FN
- PTB5_IN
- PTB5_OUT
- PTB6_DATA
- PTB6_FN
- PTB6_IN
- PTB6_OUT
- PTB7_DATA
- PTB7_FN
- PTB7_IN
- PTB7_OUT
- PTB_MASK
- PTC0_DATA
- PTC0_FN
- PTC0_IN
- PTC0_OUT
- PTC1_DATA
- PTC1_FN
- PTC1_IN
- PTC1_OUT
- PTC2_DATA
- PTC2_FN
- PTC2_IN
- PTC2_OUT
- PTC3_DATA
- PTC3_FN
- PTC3_IN
- PTC3_OUT
- PTC4_DATA
- PTC4_FN
- PTC4_IN
- PTC4_OUT
- PTC5_DATA
- PTC5_FN
- PTC5_IN
- PTC5_OUT
- PTC6_DATA
- PTC6_FN
- PTC6_IN
- PTC6_OUT
- PTC7_DATA
- PTC7_FN
- PTC7_IN
- PTC7_OUT
- PTCMD
- PTC_RSVD
- PTC_RX_WM_VAL
- PTD0_DATA
- PTD0_FN
- PTD0_IN
- PTD0_OUT
- PTD1_DATA
- PTD1_FN
- PTD1_IN
- PTD1_OUT
- PTD2_DATA
- PTD2_FN
- PTD2_IN
- PTD2_OUT
- PTD3_DATA
- PTD3_FN
- PTD3_IN
- PTD3_OUT
- PTD4_DATA
- PTD4_FN
- PTD4_IN
- PTD4_OUT
- PTD5_DATA
- PTD5_FN
- PTD5_IN
- PTD5_OUT
- PTD6_DATA
- PTD6_FN
- PTD6_IN
- PTD6_OUT
- PTD7_DATA
- PTD7_FN
- PTD7_IN
- PTD7_OUT
- PTD_ACTIVE
- PTD_ACTIVE_MSK
- PTD_B5_5
- PTD_B5_5_MSK
- PTD_BUFFEROVERRUN
- PTD_BUFFERUNDERRUN
- PTD_CC
- PTD_CC_BITSTUFFING
- PTD_CC_CRC
- PTD_CC_DATATOGGLEM
- PTD_CC_MSK
- PTD_CC_NOERROR
- PTD_CC_STALL
- PTD_COUNT
- PTD_COUNT_MSK
- PTD_DATAOVERRUN
- PTD_DATAUNDERRUN
- PTD_DEVNOTRESP
- PTD_DIR
- PTD_DIR_IN
- PTD_DIR_MSK
- PTD_DIR_OUT
- PTD_DIR_SETUP
- PTD_DIR_STR
- PTD_EP
- PTD_EP_MSK
- PTD_FA
- PTD_FA_MSK
- PTD_FMT
- PTD_FMT_MSK
- PTD_GET_ACTIVE
- PTD_GET_B5_5
- PTD_GET_CC
- PTD_GET_COUNT
- PTD_GET_DIR
- PTD_GET_EP
- PTD_GET_FA
- PTD_GET_FMT
- PTD_GET_LAST
- PTD_GET_LEN
- PTD_GET_MPS
- PTD_GET_PR
- PTD_GET_SF_INT
- PTD_GET_SF_ISO
- PTD_GET_SPD
- PTD_GET_TOGGLE
- PTD_HEADER_SIZE
- PTD_LAST
- PTD_LAST_MSK
- PTD_LEN
- PTD_LEN_MSK
- PTD_MPS
- PTD_MPS_MSK
- PTD_NOTACCESSED
- PTD_OFFSET
- PTD_PIDCHECKFAIL
- PTD_PR
- PTD_PR_MSK
- PTD_SF_INT
- PTD_SF_INT_MSK
- PTD_SF_ISO
- PTD_SF_ISO_MSK
- PTD_SPD
- PTD_SPD_MSK
- PTD_STATE_QTD_DONE
- PTD_STATE_QTD_RELOAD
- PTD_STATE_URB_RETIRE
- PTD_TOGGLE
- PTD_TOGGLE_MSK
- PTD_TRACE
- PTD_UNEXPECTEDPID
- PTE
- PTE0_DATA
- PTE0_FN
- PTE0_IN
- PTE0_OUT
- PTE1_DATA
- PTE1_FN
- PTE1_IN
- PTE1_OUT
- PTE2_DATA
- PTE2_FN
- PTE2_IN
- PTE2_OUT
- PTE3_DATA
- PTE3_FN
- PTE3_IN
- PTE3_OUT
- PTE4_DATA
- PTE4_FN
- PTE4_IN
- PTE4_OUT
- PTE5_DATA
- PTE5_FN
- PTE5_IN
- PTE5_OUT
- PTE6_DATA
- PTE6_FN
- PTE6_IN
- PTE6_OUT
- PTE7_DATA
- PTE7_FN
- PTE7_IN
- PTE7_OUT
- PTEG_FLAG_ACCESSED
- PTEG_FLAG_DIRTY
- PTEG_SIZE
- PTEH_ASID_SHIFT
- PTEH_MATCH_ASID
- PTEH_SHARED
- PTEH_VALID
- PTES
- PTE_ADDR_HIGH
- PTE_ADDR_LOW
- PTE_ADDR_MASK
- PTE_AF
- PTE_AP2
- PTE_ATOMIC_UPDATES
- PTE_ATTRINDX
- PTE_ATTRINDX_MASK
- PTE_BAP_SHIFT
- PTE_BITS
- PTE_BITS_IN_PD0
- PTE_BITS_MUST_MATCH
- PTE_BITS_NON_RWX_IN_PD1
- PTE_BITS_RWX
- PTE_BIT_FUNC
- PTE_BUFFERABLE
- PTE_C
- PTE_CACHEABLE
- PTE_CONT
- PTE_DBM
- PTE_DEVMAP
- PTE_DIRTY
- PTE_ENTRIES_IN_HOP
- PTE_ENTRY_SIZE
- PTE_EXEC
- PTE_EXT_AF
- PTE_EXT_AP0
- PTE_EXT_AP1
- PTE_EXT_APX
- PTE_EXT_AP_MASK
- PTE_EXT_AP_UNO_SRO
- PTE_EXT_AP_UNO_SRW
- PTE_EXT_AP_URO_SRW
- PTE_EXT_AP_URW_SRW
- PTE_EXT_COHERENT
- PTE_EXT_NG
- PTE_EXT_PXN
- PTE_EXT_SHARED
- PTE_EXT_TEX
- PTE_EXT_XN
- PTE_FILE_MAX_BITS
- PTE_FLAGS
- PTE_FLAGS_DEC
- PTE_FLAGS_DEC_WP
- PTE_FLAGS_ENC
- PTE_FLAGS_MASK
- PTE_FLAGS_OFFSET
- PTE_FMT
- PTE_FRAG_NR
- PTE_FRAG_SIZE
- PTE_FRAG_SIZE_SHIFT
- PTE_FREE
- PTE_H
- PTE_HWTABLE_OFF
- PTE_HWTABLE_PTRS
- PTE_HWTABLE_SIZE
- PTE_HYP
- PTE_HYP_XN
- PTE_IDENT
- PTE_IDENT_ATTR
- PTE_INDEX
- PTE_INDEX_SIZE
- PTE_INDX_MSK
- PTE_INDX_SHIFT
- PTE_INUSE
- PTE_LEVEL_MULT
- PTE_LEVEL_PAGE_SIZE
- PTE_LIST_EXT
- PTE_M
- PTE_MAGNITUDE
- PTE_MASK
- PTE_MAYBE_NG
- PTE_NG
- PTE_ORDER
- PTE_PAGE_SIZE
- PTE_PARENT_SIZE
- PTE_PFN_MASK
- PTE_PHYS_ADDR_MASK
- PTE_PHYS_ADDR_SHIFT
- PTE_PHYS_MASK
- PTE_PREFETCH_NUM
- PTE_PRESENT
- PTE_PROT_NONE
- PTE_PXN
- PTE_R
- PTE_RDONLY
- PTE_READ
- PTE_READ_ONLY
- PTE_ROW_HEIGHT_LINEAR
- PTE_ROW_HEIGHT_LINEAR_1024L
- PTE_ROW_HEIGHT_LINEAR_128L
- PTE_ROW_HEIGHT_LINEAR_16L
- PTE_ROW_HEIGHT_LINEAR_256L
- PTE_ROW_HEIGHT_LINEAR_32L
- PTE_ROW_HEIGHT_LINEAR_512L
- PTE_ROW_HEIGHT_LINEAR_64L
- PTE_ROW_HEIGHT_LINEAR_8L
- PTE_RPN_MASK
- PTE_RPN_SHIFT
- PTE_S2_MEMATTR
- PTE_S2_MEMATTR_MASK
- PTE_S2_RDONLY
- PTE_S2_RDWR
- PTE_S2_XN
- PTE_SEC
- PTE_SHARED
- PTE_SHIFT
- PTE_SIZE
- PTE_SIZE_LOG
- PTE_SMALL_AP_MASK
- PTE_SMALL_AP_UNO_SRO
- PTE_SMALL_AP_UNO_SRW
- PTE_SMALL_AP_URO_SRW
- PTE_SMALL_AP_URW_SRW
- PTE_SPECIAL
- PTE_STRIDE
- PTE_TABLE_BIT
- PTE_TABLE_SIZE
- PTE_TYPE_EXT
- PTE_TYPE_FAULT
- PTE_TYPE_INVALID
- PTE_TYPE_LARGE
- PTE_TYPE_MASK
- PTE_TYPE_MIDDLE
- PTE_TYPE_PAGE
- PTE_TYPE_SMALL
- PTE_T_LOG2
- PTE_T_ORDER
- PTE_USER
- PTE_UXN
- PTE_V
- PTE_VALID
- PTE_WIMGE_SHIFT
- PTE_WRITE
- PTE_YOUNG
- PTF0_DATA
- PTF0_FN
- PTF0_IN
- PTF0_OUT
- PTF1_DATA
- PTF1_FN
- PTF1_IN
- PTF1_OUT
- PTF2_DATA
- PTF2_FN
- PTF2_IN
- PTF2_OUT
- PTF3_DATA
- PTF3_FN
- PTF3_IN
- PTF3_OUT
- PTF4_DATA
- PTF4_FN
- PTF4_IN
- PTF4_OUT
- PTF5_DATA
- PTF5_FN
- PTF5_IN
- PTF5_OUT
- PTF6
- PTF6_DATA
- PTF6_FN
- PTF6_IN
- PTF6_OUT
- PTF7_DATA
- PTF7_FN
- PTF7_IN
- PTF7_OUT
- PTFF_ATO
- PTFF_QAF
- PTFF_QSI
- PTFF_QTO
- PTFF_QUI
- PTFF_SFS
- PTFF_SGS
- PTFF_STO
- PTF_CHECK
- PTF_HORIZONTAL
- PTF_VERTICAL
- PTG0_DATA
- PTG0_FN
- PTG0_IN
- PTG0_OUT
- PTG1_DATA
- PTG1_FN
- PTG1_IN
- PTG1_OUT
- PTG2_DATA
- PTG2_FN
- PTG2_IN
- PTG2_OUT
- PTG3_DATA
- PTG3_FN
- PTG3_IN
- PTG3_OUT
- PTG4_DATA
- PTG4_FN
- PTG4_IN
- PTG4_OUT
- PTG5_DATA
- PTG5_FN
- PTG5_IN
- PTG5_OUT
- PTG6_DATA
- PTG6_FN
- PTG6_IN
- PTG6_OUT
- PTG7_DATA
- PTG7_FN
- PTG7_IN
- PTG7_OUT
- PTGS_TO_GS
- PTGS_TO_GS_EX
- PTH0_DATA
- PTH0_FN
- PTH0_IN
- PTH0_OUT
- PTH1_DATA
- PTH1_FN
- PTH1_IN
- PTH1_OUT
- PTH2_DATA
- PTH2_FN
- PTH2_IN
- PTH2_OUT
- PTH3_DATA
- PTH3_FN
- PTH3_IN
- PTH3_OUT
- PTH4_DATA
- PTH4_FN
- PTH4_IN
- PTH4_OUT
- PTH5_DATA
- PTH5_FN
- PTH5_IN
- PTH5_OUT
- PTH6_DATA
- PTH6_FN
- PTH6_IN
- PTH6_OUT
- PTH7_DATA
- PTH7_FN
- PTH7_IN
- PTH7_OUT
- PTHREAD_JOIN
- PTHRH_DEFAULT_THRESHOLD
- PTHRU_FRAME
- PTI0_DATA
- PTI0_FN
- PTI0_IN
- PTI0_OUT
- PTI1_DATA
- PTI1_FN
- PTI1_IN
- PTI1_OUT
- PTI2_DATA
- PTI2_FN
- PTI2_IN
- PTI2_OUT
- PTI3_DATA
- PTI3_FN
- PTI3_IN
- PTI3_OUT
- PTI4_DATA
- PTI4_FN
- PTI4_IN
- PTI4_OUT
- PTI5_DATA
- PTI5_FN
- PTI5_IN
- PTI5_OUT
- PTI6_DATA
- PTI6_FN
- PTI6_IN
- PTI6_OUT
- PTI7_DATA
- PTI7_FN
- PTI7_IN
- PTI7_OUT
- PTIMER_Def
- PTIMER_Mask
- PTIMER_Print
- PTIMER_Read
- PTIMER_TEST
- PTIMER_Val
- PTIMER_Write
- PTIME_MASK
- PTIM_CCVR
- PTIM_CTLR
- PTIM_LVR
- PTIM_TSR
- PTITTY_MINOR_NUM
- PTITTY_MINOR_START
- PTI_AUTO
- PTI_CLKDIV
- PTI_CLONE_PMD
- PTI_CLONE_PTE
- PTI_CONSUMED_PCID_BITS
- PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK
- PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT
- PTI_CONTROL__PTI_ENABLE_MASK
- PTI_CONTROL__PTI_ENABLE__SHIFT
- PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK
- PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT
- PTI_EN
- PTI_FCEN
- PTI_FORCE_OFF
- PTI_FORCE_ON
- PTI_LASTDWORD_DTS
- PTI_LEVEL_KERNEL_IMAGE
- PTI_MODE
- PTI_PATGENMODE
- PTI_PGTABLE_SWITCH_BIT
- PTI_RESET_LIMIT
- PTI_SWITCH_MASK
- PTI_USER_PCID_BIT
- PTI_USER_PCID_MASK
- PTI_USER_PGD_FILL
- PTI_USER_PGTABLE_AND_PCID_MASK
- PTI_USER_PGTABLE_BIT
- PTI_USER_PGTABLE_MASK
- PTJ0_DATA
- PTJ0_FN
- PTJ0_IN
- PTJ0_OUT
- PTJ1_DATA
- PTJ1_FN
- PTJ1_IN
- PTJ1_OUT
- PTJ2_DATA
- PTJ2_FN
- PTJ2_IN
- PTJ2_OUT
- PTJ3_DATA
- PTJ3_FN
- PTJ3_IN
- PTJ3_OUT
- PTJ4_DATA
- PTJ4_FN
- PTJ4_IN
- PTJ4_OUT
- PTJ5_DATA
- PTJ5_FN
- PTJ5_IN
- PTJ5_OUT
- PTJ6_DATA
- PTJ6_FN
- PTJ6_IN
- PTJ6_OUT
- PTJ7_DATA
- PTJ7_FN
- PTJ7_OUT
- PTK0
- PTK0_DATA
- PTK0_FN
- PTK0_IN
- PTK0_OUT
- PTK1_DATA
- PTK1_FN
- PTK1_IN
- PTK1_OUT
- PTK2_DATA
- PTK2_FN
- PTK2_IN
- PTK2_OUT
- PTK3_DATA
- PTK3_FN
- PTK3_IN
- PTK3_OUT
- PTK4_DATA
- PTK4_FN
- PTK4_IN
- PTK4_OUT
- PTK5_DATA
- PTK5_FN
- PTK5_IN
- PTK5_OUT
- PTK6_DATA
- PTK6_FN
- PTK6_IN
- PTK6_OUT
- PTK7_DATA
- PTK7_FN
- PTK7_IN
- PTK7_OUT
- PTKN
- PTL0_DATA
- PTL0_FN
- PTL0_IN
- PTL0_OUT
- PTL1_DATA
- PTL1_FN
- PTL1_IN
- PTL1_OUT
- PTL2_DATA
- PTL2_FN
- PTL2_IN
- PTL2_OUT
- PTL3_DATA
- PTL3_FN
- PTL3_IN
- PTL3_OUT
- PTL4_DATA
- PTL4_FN
- PTL4_IN
- PTL4_OUT
- PTL5_DATA
- PTL5_FN
- PTL5_IN
- PTL5_OUT
- PTL6_DATA
- PTL6_FN
- PTL6_IN
- PTL6_OUT
- PTL7_DATA
- PTL7_FN
- PTL7_IN
- PTL7_OUT
- PTLD_REG_DBG_DWORD_ENABLE_E5
- PTLD_REG_DBG_FORCE_FRAME_E5
- PTLD_REG_DBG_FORCE_VALID_E5
- PTLD_REG_DBG_SELECT_E5
- PTLD_REG_DBG_SHIFT_E5
- PTM0_DATA
- PTM0_FN
- PTM0_IN
- PTM0_OUT
- PTM1_DATA
- PTM1_FN
- PTM1_IN
- PTM1_OUT
- PTM2_DATA
- PTM2_FN
- PTM2_IN
- PTM2_OUT
- PTM3_DATA
- PTM3_FN
- PTM3_IN
- PTM3_OUT
- PTM4_DATA
- PTM4_FN
- PTM4_IN
- PTM4_OUT
- PTM5_DATA
- PTM5_FN
- PTM5_IN
- PTM5_OUT
- PTM6_DATA
- PTM6_FN
- PTM6_IN
- PTM6_OUT
- PTM7_DATA
- PTM7_FN
- PTM7_IN
- PTM7_OUT
- PTMEMTYPE
- PTMEMTYPE_MASK
- PTMEMTYPE_SHIFT
- PTMR_PRE
- PTMSYNCREQ_EN_OFFSET
- PTMSYNCREQ_MASK_OFFSET
- PTMTCFG
- PTMTCFG_MASK
- PTMTCFG_SHIFT
- PTMX_MINOR
- PTN0_DATA
- PTN0_FN
- PTN0_IN
- PTN0_OUT
- PTN1_DATA
- PTN1_FN
- PTN1_IN
- PTN1_OUT
- PTN2_DATA
- PTN2_FN
- PTN2_IN
- PTN2_OUT
- PTN3460_EDID_ADDR
- PTN3460_EDID_EMULATION_ADDR
- PTN3460_EDID_EMULATION_SELECTION
- PTN3460_EDID_ENABLE_EMULATION
- PTN3460_EDID_SRAM_LOAD_ADDR
- PTN3_DATA
- PTN3_FN
- PTN3_IN
- PTN3_OUT
- PTN4_DATA
- PTN4_FN
- PTN4_IN
- PTN4_OUT
- PTN5150_DFP_ATTACHED
- PTN5150_REG_CC_PORT_ATTACHMENT_MASK
- PTN5150_REG_CC_PORT_ATTACHMENT_SHIFT
- PTN5150_REG_CC_STATUS
- PTN5150_REG_CC_VBUS_DETECTION_MASK
- PTN5150_REG_CC_VBUS_DETECTION_SHIFT
- PTN5150_REG_CONTROL
- PTN5150_REG_CON_DET
- PTN5150_REG_DEVICE_ID
- PTN5150_REG_DEVICE_ID_VENDOR_MASK
- PTN5150_REG_DEVICE_ID_VENDOR_SHIFT
- PTN5150_REG_DEVICE_ID_VERSION_MASK
- PTN5150_REG_DEVICE_ID_VERSION_SHIFT
- PTN5150_REG_END
- PTN5150_REG_INT_CABLE_ATTACH_MASK
- PTN5150_REG_INT_CABLE_ATTACH_SHIFT
- PTN5150_REG_INT_CABLE_DETACH_MASK
- PTN5150_REG_INT_CABLE_DETACH_SHIFT
- PTN5150_REG_INT_MASK
- PTN5150_REG_INT_REG_STATUS
- PTN5150_REG_INT_STATUS
- PTN5150_REG_RESET
- PTN5150_REG_VCONN_STATUS
- PTN5150_UFP_ATTACHED
- PTN5_DATA
- PTN5_FN
- PTN5_IN
- PTN5_OUT
- PTN6_DATA
- PTN6_FN
- PTN6_IN
- PTN6_OUT
- PTN7_DATA
- PTN7_FN
- PTN7_IN
- PTN7_OUT
- PTO0_DATA
- PTO0_FN
- PTO0_IN
- PTO0_OUT
- PTO1_DATA
- PTO1_FN
- PTO1_IN
- PTO1_OUT
- PTO2_DATA
- PTO2_FN
- PTO2_IN
- PTO2_OUT
- PTO3_DATA
- PTO3_FN
- PTO3_IN
- PTO3_OUT
- PTO4_DATA
- PTO4_FN
- PTO4_IN
- PTO4_OUT
- PTO5_DATA
- PTO5_FN
- PTO5_IN
- PTO5_OUT
- PTO6_DATA
- PTO6_FN
- PTO6_IN
- PTO6_OUT
- PTO7_DATA
- PTO7_FN
- PTO7_IN
- PTO7_OUT
- PTOV
- PTO_DIR_REG
- PTO_ENB_REG
- PTO_IE_REG
- PTO_MIS_REG
- PTO_RDATA_REG
- PTO_WDATA_REG
- PTP
- PTP0_DATA
- PTP0_FN
- PTP0_IN
- PTP0_OUT
- PTP1_DATA
- PTP1_FN
- PTP1_IN
- PTP1_OUT
- PTP2_DATA
- PTP2_FN
- PTP2_IN
- PTP2_OUT
- PTP3_DATA
- PTP3_FN
- PTP3_IN
- PTP3_OUT
- PTP4_DATA
- PTP4_FN
- PTP4_IN
- PTP4_OUT
- PTP5_DATA
- PTP5_FN
- PTP5_IN
- PTP5_OUT
- PTP6_DATA
- PTP6_FN
- PTP6_IN
- PTP6_OUT
- PTP7_DATA
- PTP7_FN
- PTP7_IN
- PTP7_OUT
- PTPAHX
- PTPALX
- PTPCORESEL
- PTPRESERVED_MASK
- PTPRESERVED_SHIFT
- PTP_1STEP
- PTP_802_1AS
- PTP_ADDRESS
- PTP_ALL_HIGH_PRIO
- PTP_ALTERNATE_MASTER
- PTP_BINARY_ROLLOVER_MODE
- PTP_BUF_TIMESTAMPS
- PTP_CAP_INFO
- PTP_CAP_INFO_TX_TS_CNT_GET_
- PTP_CFG_CLK_ADJ_CFG_DIR
- PTP_CFG_CLK_ADJ_CFG_ENA
- PTP_CFG_CLK_ADJ_FREQ_NS
- PTP_CFG_MISC
- PTP_CFG_MISC_PTP_EN
- PTP_CLASS_IPV4
- PTP_CLASS_IPV6
- PTP_CLASS_L2
- PTP_CLASS_L4
- PTP_CLASS_NONE
- PTP_CLASS_PMASK
- PTP_CLASS_V1
- PTP_CLASS_V1_IPV4
- PTP_CLASS_V1_IPV6
- PTP_CLASS_V2
- PTP_CLASS_V2_IPV4
- PTP_CLASS_V2_IPV6
- PTP_CLASS_V2_L2
- PTP_CLASS_V2_VLAN
- PTP_CLASS_VLAN
- PTP_CLASS_VMASK
- PTP_CLKDIV_MASK
- PTP_CLKDIV_SHIFT
- PTP_CLKOUT_EN
- PTP_CLKOUT_SEL
- PTP_CLKOUT_SPEEDSEL
- PTP_CLKSRC
- PTP_CLK_ADJ_ENABLE
- PTP_CLK_CFG_ADJ_CFG
- PTP_CLK_CFG_ADJ_FREQ
- PTP_CLK_ENABLE
- PTP_CLK_MAGIC
- PTP_CLK_REQ_EXTTS
- PTP_CLK_REQ_PEROUT
- PTP_CLK_REQ_PPS
- PTP_CLK_RESET
- PTP_CLOCK_ALARM
- PTP_CLOCK_CFG
- PTP_CLOCK_CFG_PTP_EN
- PTP_CLOCK_COMP
- PTP_CLOCK_EXTTS
- PTP_CLOCK_GETCAPS
- PTP_CLOCK_GETCAPS2
- PTP_CLOCK_HI
- PTP_CLOCK_LO
- PTP_CLOCK_MAX_ADJTIME
- PTP_CLOCK_NS
- PTP_CLOCK_PPS
- PTP_CLOCK_PPSUSR
- PTP_CLOCK_RATE_ADJ
- PTP_CLOCK_RATE_ADJ_DIR_
- PTP_CLOCK_SEC
- PTP_CLOCK_STEP_ADJ
- PTP_CLOCK_STEP_ADJ_DIR_
- PTP_CLOCK_STEP_ADJ_VALUE_MASK_
- PTP_CLOCK_SUBNS
- PTP_CLOCK_TARGET_NS_X
- PTP_CLOCK_TARGET_RELOAD_NS_X
- PTP_CLOCK_TARGET_RELOAD_SEC_X
- PTP_CLOCK_TARGET_SEC_X
- PTP_CMD_CTL
- PTP_CMD_CTL_PTP_CLK_STP_NSEC_
- PTP_CMD_CTL_PTP_CLOCK_LOAD_
- PTP_CMD_CTL_PTP_CLOCK_READ_
- PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_
- PTP_CMD_CTL_PTP_DISABLE_
- PTP_CMD_CTL_PTP_ENABLE_
- PTP_CMD_CTL_PTP_RESET_
- PTP_COC
- PTP_CTL
- PTP_DELAY_CHECK
- PTP_DIGITAL_ROLLOVER_MODE
- PTP_DISABLE
- PTP_DOMAIN_CHECK
- PTP_DOMAIN_M
- PTP_DOMAIN_MASK
- PTP_DOMAIN_SHIFT
- PTP_DPORT_OFFSET
- PTP_DROP_SYNC_DELAY_REQ
- PTP_DTE_PM_OPS
- PTP_EDATA
- PTP_ENABLE
- PTP_ENABLE_FEATURE
- PTP_ENABLE_PPS
- PTP_ENABLE_PPS2
- PTP_ESTS
- PTP_ETH_ENABLE
- PTP_ETR
- PTP_EVENT_PORT
- PTP_EVNT
- PTP_EV_PORT
- PTP_EXTTS_EDGES
- PTP_EXTTS_REQUEST
- PTP_EXTTS_REQUEST2
- PTP_EXTTS_V1_VALID_FLAGS
- PTP_EXTTS_VALID_FLAGS
- PTP_FALLING_EDGE
- PTP_FLAG_ISR_ENABLED
- PTP_FLAG_PTP_CLOCK_REGISTERED
- PTP_GENERAL_CONFIG
- PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_
- PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_
- PTP_GENERAL_CONFIG_RELOAD_ADD_X_
- PTP_GENERAL_PORT
- PTP_GEN_BIT
- PTP_GMAC3_X_OFFSET
- PTP_GMAC4_OFFSET
- PTP_GPIOMON
- PTP_GPIO_INDEX_S
- PTP_INT
- PTP_INTCTL
- PTP_INT_BIT_TIMER_A_
- PTP_INT_BIT_TIMER_B_
- PTP_INT_BIT_TX_SWTS_ERR_
- PTP_INT_BIT_TX_TS_
- PTP_INT_EN_CLR
- PTP_INT_EN_SET
- PTP_INT_GPIO_MASK
- PTP_INT_GPIO_SHIFT
- PTP_INT_STS
- PTP_IN_TRANSMIT_PACKET_MAXNUM
- PTP_IPV4_UDP_ENABLE
- PTP_IPV6_UDP_ENABLE
- PTP_L2_MULTICAST_SA
- PTP_L4_MULTICAST_SA
- PTP_LATENCY
- PTP_LATENCY_RX_SET_
- PTP_LATENCY_TX_SET_
- PTP_LOAD_CLK
- PTP_LOAD_TIME
- PTP_MASTER
- PTP_MASTER_MODE
- PTP_MAX_ALARMS
- PTP_MAX_SAMPLES
- PTP_MAX_TIMESTAMPS
- PTP_MC_STAT
- PTP_MIN_LENGTH
- PTP_OFF
- PTP_OFFSET_MASK
- PTP_OFFSET_SHIFT
- PTP_PACKET_STATE_MATCHED
- PTP_PACKET_STATE_MATCH_UNWANTED
- PTP_PACKET_STATE_TIMED_OUT
- PTP_PACKET_STATE_UNMATCHED
- PTP_PDELAY_CHECK
- PTP_PEROUT_ONE_SHOT
- PTP_PEROUT_REQUEST
- PTP_PEROUT_REQUEST2
- PTP_PEROUT_V1_VALID_FLAGS
- PTP_PEROUT_VALID_FLAGS
- PTP_PF_EXTTS
- PTP_PF_NONE
- PTP_PF_PEROUT
- PTP_PF_PHYSYNC
- PTP_PIN_ACTION_CLOCK
- PTP_PIN_ACTION_DELTA
- PTP_PIN_ACTION_IDLE
- PTP_PIN_ACTION_LOAD
- PTP_PIN_ACTION_NOSYNC
- PTP_PIN_ACTION_SAVE
- PTP_PIN_ACTION_SYNC
- PTP_PIN_CFG
- PTP_PIN_CFG_ACTION
- PTP_PIN_CFG_ACTION_MASK
- PTP_PIN_CFG_DOM
- PTP_PIN_CFG_RSZ
- PTP_PIN_CFG_SYNC
- PTP_PIN_GETFUNC
- PTP_PIN_GETFUNC2
- PTP_PIN_SETFUNC
- PTP_PIN_SETFUNC2
- PTP_PIN_TOD_NSEC
- PTP_PIN_TOD_NSEC_RSZ
- PTP_PIN_TOD_SEC_LSB
- PTP_PIN_TOD_SEC_LSB_RSZ
- PTP_PIN_TOD_SEC_MSB
- PTP_PIN_TOD_SEC_MSB_RSZ
- PTP_PORT_PDELAY_RESP_INT
- PTP_PORT_SYNC_INT
- PTP_PORT_XDELAY_REQ_INT
- PTP_PPS_DEFAULTS
- PTP_PPS_EVENT
- PTP_PPS_MODE
- PTP_RATEH
- PTP_RATEL
- PTP_RATE_DIR
- PTP_RATE_HI_MASK
- PTP_RATE_HI_SHIFT
- PTP_RDCKSUM
- PTP_RD_CLK
- PTP_READ_TIME
- PTP_RESET
- PTP_RISING_EDGE
- PTP_RTC_SUB_NANOSEC_M
- PTP_RXCFG0
- PTP_RXCFG1
- PTP_RXCFG2
- PTP_RXCFG3
- PTP_RXCFG4
- PTP_RXHASH
- PTP_RXTS
- PTP_SFDCFG
- PTP_SHOW_INT
- PTP_SLAVE_MODE
- PTP_SSIR
- PTP_SSIR_SSINC_MASK
- PTP_STAT_COUNT
- PTP_STEP_ADJ
- PTP_STEP_CLK
- PTP_STEP_DIR
- PTP_STNSR
- PTP_STNSUR
- PTP_STNSUR_ADDSUB_SHIFT
- PTP_STRICT_FLAGS
- PTP_STS
- PTP_STSR
- PTP_STSUR
- PTP_SUPPORTED
- PTP_SW_STAT
- PTP_SYNC_ATTEMPTS
- PTP_SYNC_CHECK
- PTP_SYS_OFFSET
- PTP_SYS_OFFSET2
- PTP_SYS_OFFSET_EXTENDED
- PTP_SYS_OFFSET_EXTENDED2
- PTP_SYS_OFFSET_PRECISE
- PTP_SYS_OFFSET_PRECISE2
- PTP_TAR
- PTP_TCR
- PTP_TCR_SNAPTYPSEL_1
- PTP_TCR_TSADDREG
- PTP_TCR_TSCFUPDT
- PTP_TCR_TSCTRLSSR
- PTP_TCR_TSENA
- PTP_TCR_TSENALL
- PTP_TCR_TSENMACADDR
- PTP_TCR_TSEVNTENA
- PTP_TCR_TSINIT
- PTP_TCR_TSIPENA
- PTP_TCR_TSIPV4ENA
- PTP_TCR_TSIPV6ENA
- PTP_TCR_TSMSTRENA
- PTP_TCR_TSTRIG
- PTP_TCR_TSUPDT
- PTP_TCR_TSVER2ENA
- PTP_TC_P2P
- PTP_TDR
- PTP_TMP_RATE
- PTP_TMP_RATE_ENABLE
- PTP_TOU_INDEX_S
- PTP_TRDH
- PTP_TRDL
- PTP_TRIG
- PTP_TRIG_UNIT_M
- PTP_TSI_INDEX_S
- PTP_TSTS
- PTP_TS_BUFFER_SIZE
- PTP_TS_L2
- PTP_TS_L2_L4
- PTP_TS_L4
- PTP_TS_NONE
- PTP_TS_UNIT_M
- PTP_TXCFG0
- PTP_TXCFG1
- PTP_TXTS
- PTP_TX_EGRESS_NS
- PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_
- PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_
- PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_
- PTP_TX_EGRESS_NS_TS_NS_MASK_
- PTP_TX_EGRESS_SEC
- PTP_TX_MOD
- PTP_TX_MOD2
- PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_
- PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_
- PTP_TX_MSG_HEADER
- PTP_TX_MSG_HEADER_MSG_TYPE_
- PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_
- PTP_UDP_CHECKSUM
- PTP_UNICAST_ENABLE
- PTP_UNIT_M
- PTP_V1_MIN_LENGTH
- PTP_V1_SEQUENCE_LENGTH
- PTP_V1_SEQUENCE_OFFSET
- PTP_V1_UUID_LENGTH
- PTP_V1_UUID_OFFSET
- PTP_V1_VERSION_LENGTH
- PTP_V1_VERSION_OFFSET
- PTP_V2_MC_UUID_LENGTH
- PTP_V2_MC_UUID_OFFSET
- PTP_V2_MIN_LENGTH
- PTP_V2_SEQUENCE_LENGTH
- PTP_V2_SEQUENCE_OFFSET
- PTP_V2_UUID_LENGTH
- PTP_V2_UUID_OFFSET
- PTP_V2_VERSION_LENGTH
- PTP_V2_VERSION_OFFSET
- PTP_VERSION_M
- PTP_VERSION_V1
- PTP_VERSION_V2
- PTP_VERSION_V2_MASK
- PTP_WRCKSUM
- PTP_XGMAC_OFFSET
- PTQ0
- PTQ0_DATA
- PTQ0_FN
- PTQ0_IN
- PTQ0_OUT
- PTQ1
- PTQ1_DATA
- PTQ1_FN
- PTQ1_IN
- PTQ1_OUT
- PTQ2
- PTQ2_DATA
- PTQ2_FN
- PTQ2_IN
- PTQ2_OUT
- PTQ3_DATA
- PTQ3_FN
- PTQ3_IN
- PTQ3_OUT
- PTQ4_DATA
- PTQ4_FN
- PTQ4_IN
- PTQ4_OUT
- PTQ5_DATA
- PTQ5_FN
- PTQ5_IN
- PTQ5_OUT
- PTQ6_DATA
- PTQ6_FN
- PTQ6_IN
- PTQ6_OUT
- PTQ7_DATA
- PTQ7_FN
- PTQ7_IN
- PTQ7_OUT
- PTR
- PTR0_DATA
- PTR0_FN
- PTR0_IN
- PTR0_OUT
- PTR1_DATA
- PTR1_FN
- PTR1_IN
- PTR1_OUT
- PTR2
- PTR2USHORT
- PTR2_DATA
- PTR2_FN
- PTR2_IN
- PTR2_OUT
- PTR32
- PTR32BIT
- PTR3_DATA
- PTR3_FN
- PTR3_IN
- PTR3_OUT
- PTR4_DATA
- PTR4_FN
- PTR4_IN
- PTR4_OUT
- PTR5_DATA
- PTR5_FN
- PTR5_IN
- PTR5_OUT
- PTR64BIT
- PTR6_DATA
- PTR6_FN
- PTR6_IN
- PTR6_OUT
- PTR7_DATA
- PTR7_FN
- PTR7_IN
- PTR7_OUT
- PTRACE_ARCH_PRCTL
- PTRACE_ATTACH
- PTRACE_CONT
- PTRACE_DEBUG
- PTRACE_DETACH
- PTRACE_DISABLE_TE
- PTRACE_ENABLE_TE
- PTRACE_EVENTMSG_SYSCALL_ENTRY
- PTRACE_EVENTMSG_SYSCALL_EXIT
- PTRACE_EVENT_CLONE
- PTRACE_EVENT_EXEC
- PTRACE_EVENT_EXIT
- PTRACE_EVENT_FORK
- PTRACE_EVENT_SECCOMP
- PTRACE_EVENT_STOP
- PTRACE_EVENT_VFORK
- PTRACE_EVENT_VFORK_DONE
- PTRACE_FULL_FAULTINFO
- PTRACE_GETCRUNCHREGS
- PTRACE_GETDSPREGS
- PTRACE_GETEVENTMSG
- PTRACE_GETEVRREGS
- PTRACE_GETFDPIC
- PTRACE_GETFDPIC_EXEC
- PTRACE_GETFDPIC_INTERP
- PTRACE_GETFPAREGS
- PTRACE_GETFPREGS
- PTRACE_GETFPREGS64
- PTRACE_GETFPXREGS
- PTRACE_GETHBPREGS
- PTRACE_GETREGS
- PTRACE_GETREGS64
- PTRACE_GETREGSET
- PTRACE_GETSIGINFO
- PTRACE_GETSIGMASK
- PTRACE_GETVFPREGS
- PTRACE_GETVRREGS
- PTRACE_GETVSRREGS
- PTRACE_GETWMMXREGS
- PTRACE_GETXTREGS
- PTRACE_GET_DEBUGREG
- PTRACE_GET_LAST_BREAK
- PTRACE_GET_SYSCALL_INFO
- PTRACE_GET_THREAD_AREA
- PTRACE_GET_THREAD_AREA_3264
- PTRACE_GET_WATCH_REGS
- PTRACE_HBP_ADDR_SZ
- PTRACE_HBP_CTRL_SZ
- PTRACE_HBP_PAD_SZ
- PTRACE_INTERRUPT
- PTRACE_KILL
- PTRACE_LISTEN
- PTRACE_MODE_ATTACH
- PTRACE_MODE_ATTACH_FSCREDS
- PTRACE_MODE_ATTACH_REALCREDS
- PTRACE_MODE_FSCREDS
- PTRACE_MODE_NOAUDIT
- PTRACE_MODE_READ
- PTRACE_MODE_READ_FSCREDS
- PTRACE_MODE_READ_REALCREDS
- PTRACE_MODE_REALCREDS
- PTRACE_OLDSETOPTIONS
- PTRACE_OLD_GETSIGINFO
- PTRACE_OLD_SETSIGINFO
- PTRACE_O_EXITKILL
- PTRACE_O_MASK
- PTRACE_O_SUSPEND_SECCOMP
- PTRACE_O_TRACECLONE
- PTRACE_O_TRACEEXEC
- PTRACE_O_TRACEEXIT
- PTRACE_O_TRACEFORK
- PTRACE_O_TRACESECCOMP
- PTRACE_O_TRACESYSGOOD
- PTRACE_O_TRACEVFORK
- PTRACE_O_TRACEVFORKDONE
- PTRACE_PEEKDATA
- PTRACE_PEEKDATA_3264
- PTRACE_PEEKDATA_AREA
- PTRACE_PEEKSIGINFO
- PTRACE_PEEKSIGINFO_SHARED
- PTRACE_PEEKTEXT
- PTRACE_PEEKTEXT_3264
- PTRACE_PEEKTEXT_AREA
- PTRACE_PEEKUSR
- PTRACE_PEEKUSR_AREA
- PTRACE_PEEK_SYSTEM_CALL
- PTRACE_PERM_SHIFT
- PTRACE_POKEDATA
- PTRACE_POKEDATA_3264
- PTRACE_POKEDATA_AREA
- PTRACE_POKETEXT
- PTRACE_POKETEXT_3264
- PTRACE_POKETEXT_AREA
- PTRACE_POKEUSR
- PTRACE_POKEUSR_AREA
- PTRACE_POKE_SYSTEM_CALL
- PTRACE_PROT
- PTRACE_READDATA
- PTRACE_READTEXT
- PTRACE_SECCOMP_GET_FILTER
- PTRACE_SECCOMP_GET_METADATA
- PTRACE_SEIZE
- PTRACE_SETCRUNCHREGS
- PTRACE_SETDSPREGS
- PTRACE_SETEVRREGS
- PTRACE_SETFPAREGS
- PTRACE_SETFPREGS
- PTRACE_SETFPREGS64
- PTRACE_SETFPXREGS
- PTRACE_SETHBPREGS
- PTRACE_SETOPTIONS
- PTRACE_SETREGS
- PTRACE_SETREGS64
- PTRACE_SETREGSET
- PTRACE_SETSIGINFO
- PTRACE_SETSIGMASK
- PTRACE_SETVFPREGS
- PTRACE_SETVRREGS
- PTRACE_SETVSRREGS
- PTRACE_SETWMMXREGS
- PTRACE_SETXTREGS
- PTRACE_SET_DEBUGREG
- PTRACE_SET_SYSCALL
- PTRACE_SET_THREAD_AREA
- PTRACE_SET_WATCH_REGS
- PTRACE_SINGLEBLOCK
- PTRACE_SINGLESTEP
- PTRACE_SPARC_DETACH
- PTRACE_SYSCALL
- PTRACE_SYSCALL_ENTER
- PTRACE_SYSCALL_EXIT
- PTRACE_SYSCALL_INFO_ENTRY
- PTRACE_SYSCALL_INFO_EXIT
- PTRACE_SYSCALL_INFO_NONE
- PTRACE_SYSCALL_INFO_SECCOMP
- PTRACE_SYSEMU
- PTRACE_SYSEMU_SINGLESTEP
- PTRACE_TE_ABORT_RAND
- PTRACE_TRACEME
- PTRACE_WRITEDATA
- PTRACE_WRITETEXT
- PTRAG_END
- PTRAG_START
- PTRAUTH_KEY
- PTRAUTH_REG_OFFSET
- PTRCONST
- PTREE_RAM
- PTREGS
- PTREGS_INFO
- PTREGS_OFF
- PTRLOG
- PTRP_F
- PTRP_S
- PTRP_V
- PTRRELOC
- PTRSIZE
- PTRS_PER_IOPGD
- PTRS_PER_IOPTE
- PTRS_PER_P4D
- PTRS_PER_PAGE
- PTRS_PER_PGD
- PTRS_PER_PGD_SHIFT
- PTRS_PER_PMD
- PTRS_PER_PTD_SHIFT
- PTRS_PER_PTE
- PTRS_PER_PTE_SHIFT
- PTRS_PER_PUD
- PTRS_PER_S2_PGD
- PTRTREESIZE
- PTRX
- PTRX_FXSENDAMOUNT_A
- PTRX_FXSENDAMOUNT_A_MASK
- PTRX_FXSENDAMOUNT_B
- PTRX_FXSENDAMOUNT_B_MASK
- PTRX_PITCHTARGET
- PTRX_PITCHTARGET_MASK
- PTR_32_BIT_STRUCTURE
- PTR_32_BIT_UNION
- PTR_ADD
- PTR_ADDI
- PTR_ADDIU
- PTR_ADDRESS_MASK
- PTR_ADDU
- PTR_ALIGN
- PTR_AS_ARR_CASE
- PTR_ATTO_CONFIG_PAGE_SCSI_PORT_2
- PTR_ATTO_DEVICE_INFO
- PTR_AUTOINC
- PTR_AUTO_INC
- PTR_BA
- PTR_BADADDR
- PTR_BSTATUS
- PTR_BUCKET
- PTR_BUCKET_NR
- PTR_CACHE
- PTR_CHANNELNUM_MASK
- PTR_CHECK_DEV
- PTR_CH_CONS_INFO
- PTR_CH_MALLOC_HDR
- PTR_CMD_BUFFER_DESCRIPTOR
- PTR_CNT_PER_PG
- PTR_CONFIG
- PTR_CONFIG_EXTENDED_PAGE_HEADER
- PTR_CONFIG_PAGE_BIOS_1
- PTR_CONFIG_PAGE_BIOS_2
- PTR_CONFIG_PAGE_BIOS_4
- PTR_CONFIG_PAGE_FC_DEVICE_0
- PTR_CONFIG_PAGE_FC_PORT_0
- PTR_CONFIG_PAGE_FC_PORT_1
- PTR_CONFIG_PAGE_FC_PORT_10
- PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
- PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
- PTR_CONFIG_PAGE_FC_PORT_2
- PTR_CONFIG_PAGE_FC_PORT_3
- PTR_CONFIG_PAGE_FC_PORT_4
- PTR_CONFIG_PAGE_FC_PORT_5
- PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
- PTR_CONFIG_PAGE_FC_PORT_6
- PTR_CONFIG_PAGE_FC_PORT_7
- PTR_CONFIG_PAGE_FC_PORT_8
- PTR_CONFIG_PAGE_FC_PORT_9
- PTR_CONFIG_PAGE_HEADER
- PTR_CONFIG_PAGE_HEADER_UNION
- PTR_CONFIG_PAGE_INBAND_0
- PTR_CONFIG_PAGE_IOC_0
- PTR_CONFIG_PAGE_IOC_1
- PTR_CONFIG_PAGE_IOC_2
- PTR_CONFIG_PAGE_IOC_2_RAID_VOL
- PTR_CONFIG_PAGE_IOC_3
- PTR_CONFIG_PAGE_IOC_4
- PTR_CONFIG_PAGE_IOC_5
- PTR_CONFIG_PAGE_IOC_6
- PTR_CONFIG_PAGE_IO_UNIT_0
- PTR_CONFIG_PAGE_IO_UNIT_1
- PTR_CONFIG_PAGE_IO_UNIT_2
- PTR_CONFIG_PAGE_IO_UNIT_3
- PTR_CONFIG_PAGE_IO_UNIT_4
- PTR_CONFIG_PAGE_LAN_0
- PTR_CONFIG_PAGE_LAN_1
- PTR_CONFIG_PAGE_LOG_0
- PTR_CONFIG_PAGE_MANUFACTURING_0
- PTR_CONFIG_PAGE_MANUFACTURING_1
- PTR_CONFIG_PAGE_MANUFACTURING_10
- PTR_CONFIG_PAGE_MANUFACTURING_2
- PTR_CONFIG_PAGE_MANUFACTURING_3
- PTR_CONFIG_PAGE_MANUFACTURING_4
- PTR_CONFIG_PAGE_MANUFACTURING_5
- PTR_CONFIG_PAGE_MANUFACTURING_6
- PTR_CONFIG_PAGE_MANUFACTURING_7
- PTR_CONFIG_PAGE_MANUFACTURING_8
- PTR_CONFIG_PAGE_MANUFACTURING_9
- PTR_CONFIG_PAGE_RAID_PHYS_DISK_0
- PTR_CONFIG_PAGE_RAID_PHYS_DISK_1
- PTR_CONFIG_PAGE_RAID_VOL_0
- PTR_CONFIG_PAGE_RAID_VOL_1
- PTR_CONFIG_PAGE_SAS_DEVICE_0
- PTR_CONFIG_PAGE_SAS_DEVICE_1
- PTR_CONFIG_PAGE_SAS_DEVICE_2
- PTR_CONFIG_PAGE_SAS_ENCLOSURE_0
- PTR_CONFIG_PAGE_SAS_EXPANDER_0
- PTR_CONFIG_PAGE_SAS_EXPANDER_1
- PTR_CONFIG_PAGE_SAS_IO_UNIT_0
- PTR_CONFIG_PAGE_SAS_IO_UNIT_1
- PTR_CONFIG_PAGE_SAS_IO_UNIT_2
- PTR_CONFIG_PAGE_SAS_IO_UNIT_3
- PTR_CONFIG_PAGE_SAS_PHY_0
- PTR_CONFIG_PAGE_SAS_PHY_1
- PTR_CONFIG_PAGE_SCSI_DEVICE_0
- PTR_CONFIG_PAGE_SCSI_DEVICE_1
- PTR_CONFIG_PAGE_SCSI_DEVICE_2
- PTR_CONFIG_PAGE_SCSI_DEVICE_3
- PTR_CONFIG_PAGE_SCSI_PORT_0
- PTR_CONFIG_PAGE_SCSI_PORT_1
- PTR_CONFIG_PAGE_SCSI_PORT_2
- PTR_CPUID
- PTR_CTL6
- PTR_DEV_BITS
- PTR_DIAG_DATA_UPLOAD_HEADER
- PTR_DIFF
- PTR_DIRTY_BIT
- PTR_EA
- PTR_ECCINJ
- PTR_ERR
- PTR_ERR_ENOTSUP
- PTR_ERR_OR_ZERO
- PTR_ESTATUS
- PTR_EVENT_DATA_DISCOVERY_ERROR
- PTR_EVENT_DATA_EVENT_CHANGE
- PTR_EVENT_DATA_LINK_STATUS
- PTR_EVENT_DATA_LOGOUT
- PTR_EVENT_DATA_LOG_ENTRY
- PTR_EVENT_DATA_LOG_ENTRY_ADDED
- PTR_EVENT_DATA_LOOP_STATE
- PTR_EVENT_DATA_QUEUE_FULL
- PTR_EVENT_DATA_RAID
- PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
- PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
- PTR_EVENT_DATA_SAS_DISCOVERY
- PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE
- PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
- PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
- PTR_EVENT_DATA_SAS_PHY_LINK_STATUS
- PTR_EVENT_DATA_SAS_SES
- PTR_EVENT_DATA_SAS_SMP_ERROR
- PTR_EVENT_DATA_SCSI
- PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE
- PTR_EXCEPTION
- PTR_FC_PORT_PERSISTENT
- PTR_FC_PORT_PERSISTENT_PHYSICAL_ID
- PTR_FIELD
- PTR_FMT
- PTR_FP
- PTR_FW_DOWNLOAD_TCSGE
- PTR_FW_UPLOAD_TCSGE
- PTR_GP
- PTR_HASH
- PTR_HI
- PTR_IDX
- PTR_IENABLE
- PTR_INVALID
- PTR_IOC_3_PHYS_DISK
- PTR_IOC_4_SEP
- PTR_IOC_5_HOT_SPARE
- PTR_IOC_FACTS
- PTR_IPENDING
- PTR_IR2_PD_INFO
- PTR_IR2_STATE_CHANGED
- PTR_L
- PTR_LA
- PTR_LEVEL_IRQ
- PTR_LI
- PTR_LO
- PTR_LPTB_IRQ7
- PTR_LPT_REG_DIR
- PTR_MASK
- PTR_MAX_IDX_PER_PG
- PTR_MPI25_ENCRYPTED_HASH_DATA
- PTR_MPI25_ENCRYPTED_HASH_ENTRY
- PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT
- PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR
- PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR
- PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
- PTR_MPI25_FW_DOWNLOAD_REQUEST
- PTR_MPI25_FW_UPLOAD_REQUEST
- PTR_MPI25_IEEE_SGE_CHAIN64
- PTR_MPI25_SCSI_IO_CDB_UNION
- PTR_MPI25_SCSI_IO_REQUEST
- PTR_MPI25_SGE_IO_UNION
- PTR_MPI25_TOOLBOX_DIAGNOSTIC_CLI_REQUEST
- PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR
- PTR_MPI26_COMPONENT_IMAGE_HEADER
- PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0
- PTR_MPI26_CONFIG_PAGE_IO_UNIT_11
- PTR_MPI26_CONFIG_PAGE_PCIEDEV_0
- PTR_MPI26_CONFIG_PAGE_PCIEDEV_2
- PTR_MPI26_CONFIG_PAGE_PCIELINK_1
- PTR_MPI26_CONFIG_PAGE_PCIELINK_2
- PTR_MPI26_CONFIG_PAGE_PCIELINK_3
- PTR_MPI26_CONFIG_PAGE_PIOUNIT_0
- PTR_MPI26_CONFIG_PAGE_PIOUNIT_1
- PTR_MPI26_CONFIG_PAGE_PSWITCH_0
- PTR_MPI26_CONFIG_PAGE_PSWITCH_1
- PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT
- PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE
- PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE
- PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION
- PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER
- PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST
- PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
- PTR_MPI26_HASH_EXCLUSION_FORMAT
- PTR_MPI26_IOUNIT11_SPINUP_GROUP
- PTR_MPI26_IOUNIT_CONTROL_REPLY
- PTR_MPI26_IOUNIT_CONTROL_REQUEST
- PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY
- PTR_MPI26_NVME_ENCAPSULATED_REQUEST
- PTR_MPI26_PCIELINK2_LINK_EVENT
- PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG
- PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR
- PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
- PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA
- PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA
- PTR_MPI26_TOOLBOX_LANE_MARGINING_REPLY
- PTR_MPI2_ADAPTER_INFO
- PTR_MPI2_ADAPTER_ORDER_AUX
- PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR
- PTR_MPI2_BIOS4_ENTRY
- PTR_MPI2_BIOSPAGE2_BOOT_DEVICE
- PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER
- PTR_MPI2_BOOT_DEVICE_DEVICE_NAME
- PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
- PTR_MPI2_BOOT_DEVICE_SAS_WWID
- PTR_MPI2_CHIP_REVISION_ID
- PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER
- PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION
- PTR_MPI2_CONFIG_PAGE_BIOS_1
- PTR_MPI2_CONFIG_PAGE_BIOS_2
- PTR_MPI2_CONFIG_PAGE_BIOS_3
- PTR_MPI2_CONFIG_PAGE_BIOS_4
- PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
- PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
- PTR_MPI2_CONFIG_PAGE_ETHERNET_0
- PTR_MPI2_CONFIG_PAGE_ETHERNET_1
- PTR_MPI2_CONFIG_PAGE_EXPANDER_0
- PTR_MPI2_CONFIG_PAGE_EXPANDER_1
- PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS
- PTR_MPI2_CONFIG_PAGE_HEADER
- PTR_MPI2_CONFIG_PAGE_HEADER_UNION
- PTR_MPI2_CONFIG_PAGE_IOC_0
- PTR_MPI2_CONFIG_PAGE_IOC_1
- PTR_MPI2_CONFIG_PAGE_IOC_6
- PTR_MPI2_CONFIG_PAGE_IOC_7
- PTR_MPI2_CONFIG_PAGE_IOC_8
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_0
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_1
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_10
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_3
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_5
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_6
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_7
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_8
- PTR_MPI2_CONFIG_PAGE_IO_UNIT_9
- PTR_MPI2_CONFIG_PAGE_LOG_0
- PTR_MPI2_CONFIG_PAGE_MAN_0
- PTR_MPI2_CONFIG_PAGE_MAN_1
- PTR_MPI2_CONFIG_PAGE_MAN_2
- PTR_MPI2_CONFIG_PAGE_MAN_3
- PTR_MPI2_CONFIG_PAGE_MAN_4
- PTR_MPI2_CONFIG_PAGE_MAN_5
- PTR_MPI2_CONFIG_PAGE_MAN_6
- PTR_MPI2_CONFIG_PAGE_MAN_7
- PTR_MPI2_CONFIG_PAGE_MAN_PS
- PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
- PTR_MPI2_CONFIG_PAGE_RAID_VOL_0
- PTR_MPI2_CONFIG_PAGE_RAID_VOL_1
- PTR_MPI2_CONFIG_PAGE_RD_PDISK_0
- PTR_MPI2_CONFIG_PAGE_RD_PDISK_1
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT16
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7
- PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8
- PTR_MPI2_CONFIG_PAGE_SAS_DEV_0
- PTR_MPI2_CONFIG_PAGE_SAS_DEV_1
- PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
- PTR_MPI2_CONFIG_PAGE_SAS_PHY_0
- PTR_MPI2_CONFIG_PAGE_SAS_PHY_1
- PTR_MPI2_CONFIG_PAGE_SAS_PHY_2
- PTR_MPI2_CONFIG_PAGE_SAS_PHY_3
- PTR_MPI2_CONFIG_PAGE_SAS_PHY_4
- PTR_MPI2_CONFIG_PAGE_SAS_PORT_0
- PTR_MPI2_CONFIG_REPLY
- PTR_MPI2_CONFIG_REQUEST
- PTR_MPI2_DEFAULT_REPLY
- PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR
- PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR
- PTR_MPI2_DIAG_BUFFER_POST_REPLY
- PTR_MPI2_DIAG_BUFFER_POST_REQUEST
- PTR_MPI2_DIAG_DATA_UPLOAD_HEADER
- PTR_MPI2_DIAG_RELEASE_REPLY
- PTR_MPI2_DIAG_RELEASE_REQUEST
- PTR_MPI2_ETHERNET_IP_ADDR
- PTR_MPI2_EVENT_ACK_REPLY
- PTR_MPI2_EVENT_ACK_REQUEST
- PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT
- PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED
- PTR_MPI2_EVENT_DATA_HBD_PHY
- PTR_MPI2_EVENT_DATA_HOST_MESSAGE
- PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
- PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS
- PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK
- PTR_MPI2_EVENT_DATA_IR_VOLUME
- PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED
- PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE
- PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
- PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
- PTR_MPI2_EVENT_DATA_SAS_DISCOVERY
- PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
- PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
- PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
- PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE
- PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER
- PTR_MPI2_EVENT_DATA_SAS_QUIESCE
- PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
- PTR_MPI2_EVENT_DATA_TASK_SET_FULL
- PTR_MPI2_EVENT_DATA_TEMPERATURE
- PTR_MPI2_EVENT_HBD_DESCRIPTOR
- PTR_MPI2_EVENT_HBD_PHY_SAS
- PTR_MPI2_EVENT_IR_CONFIG_ELEMENT
- PTR_MPI2_EVENT_NOTIFICATION_REPLY
- PTR_MPI2_EVENT_NOTIFICATION_REQUEST
- PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY
- PTR_MPI2_EXT_IMAGE_HEADER
- PTR_MPI2_FLASH_LAYOUT
- PTR_MPI2_FLASH_LAYOUT_DATA
- PTR_MPI2_FLASH_REGION
- PTR_MPI2_FW_DOWNLOAD_REPLY
- PTR_MPI2_FW_DOWNLOAD_REQUEST
- PTR_MPI2_FW_DOWNLOAD_TCSGE
- PTR_MPI2_FW_IMAGE_HEADER
- PTR_MPI2_FW_UPLOAD_REPLY
- PTR_MPI2_FW_UPLOAD_REQUEST
- PTR_MPI2_FW_UPLOAD_TCSGE
- PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
- PTR_MPI2_IEEE_SGE_CHAIN_UNION
- PTR_MPI2_IEEE_SGE_SIMPLE32
- PTR_MPI2_IEEE_SGE_SIMPLE64
- PTR_MPI2_IEEE_SGE_SIMPLE_UNION
- PTR_MPI2_IEEE_SGE_UNION
- PTR_MPI2_INIT_IMAGE_FOOTER
- PTR_MPI2_IOC_FACTS_REPLY
- PTR_MPI2_IOC_FACTS_REQUEST
- PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY
- PTR_MPI2_IOC_INIT_REPLY
- PTR_MPI2_IOC_INIT_REQUEST
- PTR_MPI2_IOUNIT10_FUNCTION
- PTR_MPI2_IOUNIT8_SENSOR
- PTR_MPI2_IOUNIT9_SENSOR
- PTR_MPI2_LOG_0_ENTRY
- PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS
- PTR_MPI2_MANPAGE7_CONNECTOR_INFO
- PTR_MPI2_MANUFACTURING5_ENTRY
- PTR_MPI2_MPI_SGE_IO_UNION
- PTR_MPI2_MPI_SGE_UNION
- PTR_MPI2_PORT_ENABLE_REPLY
- PTR_MPI2_PORT_ENABLE_REQUEST
- PTR_MPI2_PORT_FACTS_REPLY
- PTR_MPI2_PORT_FACTS_REQUEST
- PTR_MPI2_PWR_MGMT_CONTROL_REPLY
- PTR_MPI2_PWR_MGMT_CONTROL_REQUEST
- PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT
- PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA
- PTR_MPI2_RAIDPHYSDISK0_SETTINGS
- PTR_MPI2_RAIDPHYSDISK1_PATH
- PTR_MPI2_RAIDVOL0_PHYS_DISK
- PTR_MPI2_RAIDVOL0_SETTINGS
- PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
- PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
- PTR_MPI2_RAID_ACTION_DATA
- PTR_MPI2_RAID_ACTION_FW_UPDATE_MODE
- PTR_MPI2_RAID_ACTION_HOT_SPARE
- PTR_MPI2_RAID_ACTION_RATE_DATA
- PTR_MPI2_RAID_ACTION_REPLY
- PTR_MPI2_RAID_ACTION_REPLY_DATA
- PTR_MPI2_RAID_ACTION_REQUEST
- PTR_MPI2_RAID_ACTION_START_RAID_FUNCTION
- PTR_MPI2_RAID_ACTION_STOP_RAID_FUNCTION
- PTR_MPI2_RAID_COMPATIBILITY_INPUT_STRUCT
- PTR_MPI2_RAID_COMPATIBILITY_RESULT_STRUCT
- PTR_MPI2_RAID_ONLINE_CAPACITY_EXPANSION
- PTR_MPI2_RAID_VOLUME_CREATION_STRUCT
- PTR_MPI2_RAID_VOLUME_PHYSDISK
- PTR_MPI2_RAID_VOL_INDICATOR
- PTR_MPI2_REPLY_DESCRIPTORS_UNION
- PTR_MPI2_REQUEST_DESCRIPTOR_UNION
- PTR_MPI2_REQUEST_HEADER
- PTR_MPI2_SASPHY2_PHY_EVENT
- PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG
- PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP
- PTR_MPI2_SAS_IOUNIT_CONTROL_REPLY
- PTR_MPI2_SAS_IOUNIT_CONTROL_REQUEST
- PTR_MPI2_SAS_IO_UNIT0_PHY_DATA
- PTR_MPI2_SAS_IO_UNIT1_PHY_DATA
- PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
- PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
- PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
- PTR_MPI2_SATA_PASSTHROUGH_REPLY
- PTR_MPI2_SATA_PASSTHROUGH_REQUEST
- PTR_MPI2_SATA_PT_SGE_UNION
- PTR_MPI2_SCSI_IO_CDB_EEDP32
- PTR_MPI2_SCSI_IO_CDB_UNION
- PTR_MPI2_SCSI_IO_REPLY
- PTR_MPI2_SCSI_IO_REQUEST
- PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR
- PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
- PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
- PTR_MPI2_SCSI_TASK_MANAGE_REPLY
- PTR_MPI2_SCSI_TASK_MANAGE_REQUEST
- PTR_MPI2_SEND_HOST_MESSAGE_REPLY
- PTR_MPI2_SEND_HOST_MESSAGE_REQUEST
- PTR_MPI2_SEP_REPLY
- PTR_MPI2_SEP_REQUEST
- PTR_MPI2_SGE_CHAIN32
- PTR_MPI2_SGE_CHAIN64
- PTR_MPI2_SGE_CHAIN_UNION
- PTR_MPI2_SGE_IO_UNION
- PTR_MPI2_SGE_SIMPLE32
- PTR_MPI2_SGE_SIMPLE64
- PTR_MPI2_SGE_SIMPLE_UNION
- PTR_MPI2_SGE_TRANSACTION128
- PTR_MPI2_SGE_TRANSACTION32
- PTR_MPI2_SGE_TRANSACTION64
- PTR_MPI2_SGE_TRANSACTION96
- PTR_MPI2_SGE_TRANSACTION_UNION
- PTR_MPI2_SGE_TRANS_SIMPLE_UNION
- PTR_MPI2_SIMPLE_SGE_UNION
- PTR_MPI2_SMP_PASSTHROUGH_REPLY
- PTR_MPI2_SMP_PASSTHROUGH_REQUEST
- PTR_MPI2_SUPPORTED_DEVICE
- PTR_MPI2_SUPPORTED_DEVICES_DATA
- PTR_MPI2_SYSTEM_INTERFACE_REGS
- PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
- PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
- PTR_MPI2_TOOLBOX_BEACON_REQUEST
- PTR_MPI2_TOOLBOX_CLEAN_REQUEST
- PTR_MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST
- PTR_MPI2_TOOLBOX_DIAG_CLI_REPLY
- PTR_MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST
- PTR_MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST
- PTR_MPI2_TOOLBOX_ISTWI_REPLY
- PTR_MPI2_TOOLBOX_LANE_MARGINING_REQUEST
- PTR_MPI2_TOOLBOX_MEM_MOVE_REQUEST
- PTR_MPI2_TOOLBOX_REPLY
- PTR_MPI2_TOOLBOX_TEXT_DISPLAY_REQUEST
- PTR_MPI_ADAPTER_INFO
- PTR_MPI_BIOSPAGE2_BOOT_DEVICE
- PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER
- PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER
- PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT
- PTR_MPI_BOOT_DEVICE_FC_WWN
- PTR_MPI_BOOT_DEVICE_PCI_ADDRESS
- PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER
- PTR_MPI_BOOT_DEVICE_SAS_WWN
- PTR_MPI_CHIP_REVISION_ID
- PTR_MPI_DEVICE_INFO
- PTR_MPI_EVENT_DATA_IR2
- PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE
- PTR_MPI_EXT_IMAGE_HEADER
- PTR_MPI_FW_HEADER
- PTR_MPI_IR2_RC_EVENT_DATA
- PTR_MPI_LOG_0_ENTRY
- PTR_MPI_MANPAGE7_CONNECTOR_INFO
- PTR_MPI_RAID_VOL_INDICATOR
- PTR_MPI_SAS_IO_UNIT0_PHY_DATA
- PTR_MPI_SAS_IO_UNIT1_PHY_DATA
- PTR_MPI_SCSI_IO32_ADDRESS
- PTR_MPI_SCSI_IO32_BUS_TARGET_ID_FORM
- PTR_MPI_SCSI_IO32_CDB_EEDP16
- PTR_MPI_SCSI_IO32_CDB_EEDP32
- PTR_MPI_SCSI_IO32_CDB_UNION
- PTR_MPI_TARGET_FCP_CMD_BUFFER
- PTR_MPI_TARGET_FCP_RSP_BUFFER
- PTR_MPI_TARGET_SCSI_SPI_CMD_BUFFER
- PTR_MPI_TARGET_SCSI_SPI_STATUS_IU
- PTR_MPI_TARGET_SSP_CMD_BUFFER
- PTR_MPI_TARGET_SSP_RSP_IU
- PTR_MPI_TARGET_SSP_TASK_BUFFER
- PTR_MPI_TB_FC_MANAGE_AI_UNION
- PTR_MPI_TB_FC_MANAGE_BUS_TID_AI
- PTR_MPI_TB_FC_MANAGE_FRAME_SIZE_AI
- PTR_MPI_TB_FC_MANAGE_PID_AI
- PTR_MPI_VERSION_FORMAT
- PTR_MPI_VERSION_STRUCT
- PTR_MPUACC
- PTR_MPUBASE
- PTR_MSG_CONFIG
- PTR_MSG_CONFIG_REPLY
- PTR_MSG_DEFAULT_REPLY
- PTR_MSG_DIAG_BUFFER_POST_REPLY
- PTR_MSG_DIAG_BUFFER_POST_REQUEST
- PTR_MSG_DIAG_RELEASE_REPLY
- PTR_MSG_DIAG_RELEASE_REQUEST
- PTR_MSG_EVENT_ACK
- PTR_MSG_EVENT_ACK_REPLY
- PTR_MSG_EVENT_NOTIFY
- PTR_MSG_EVENT_NOTIFY_REPLY
- PTR_MSG_EXLINK_SERVICE_SEND_REPLY
- PTR_MSG_EXLINK_SERVICE_SEND_REQUEST
- PTR_MSG_FC_ABORT_REPLY
- PTR_MSG_FC_ABORT_REQUEST
- PTR_MSG_FC_COMMON_TRANSPORT_SEND_REPLY
- PTR_MSG_FC_COMMON_TRANSPORT_SEND_REQUEST
- PTR_MSG_FC_PRIMITIVE_SEND_REPLY
- PTR_MSG_FC_PRIMITIVE_SEND_REQUEST
- PTR_MSG_FW_DOWNLOAD
- PTR_MSG_FW_DOWNLOAD_REPLY
- PTR_MSG_FW_UPLOAD
- PTR_MSG_FW_UPLOAD_REPLY
- PTR_MSG_IOC_FACTS_REPLY
- PTR_MSG_IOC_INIT
- PTR_MSG_IOC_INIT_REPLY
- PTR_MSG_LAN_RECEIVE_POST_REPLY
- PTR_MSG_LAN_RECEIVE_POST_REQUEST
- PTR_MSG_LAN_RESET_REPLY
- PTR_MSG_LAN_RESET_REQUEST
- PTR_MSG_LAN_SEND_REPLY
- PTR_MSG_LAN_SEND_REQUEST
- PTR_MSG_LINK_SERVICE_BUFFER_POST_REPLY
- PTR_MSG_LINK_SERVICE_BUFFER_POST_REQUEST
- PTR_MSG_LINK_SERVICE_RSP_REPLY
- PTR_MSG_LINK_SERVICE_RSP_REQUEST
- PTR_MSG_MAILBOX_REPLY
- PTR_MSG_MAILBOX_REQUEST
- PTR_MSG_PORT_ENABLE
- PTR_MSG_PORT_ENABLE_REPLY
- PTR_MSG_PORT_FACTS
- PTR_MSG_PORT_FACTS_REPLY
- PTR_MSG_PRIORITY_CMD_RECEIVED_REPLY
- PTR_MSG_RAID_ACTION_REPLY
- PTR_MSG_RAID_ACTION_REQUEST
- PTR_MSG_REQUEST_HEADER
- PTR_MSG_SAS_IOUNIT_CONTROL_REPLY
- PTR_MSG_SAS_IOUNIT_CONTROL_REQUEST
- PTR_MSG_SATA_PASSTHROUGH_REPLY
- PTR_MSG_SATA_PASSTHROUGH_REQUEST
- PTR_MSG_SCSIIO32_IO_REPLY
- PTR_MSG_SCSI_IO32_REQUEST
- PTR_MSG_SCSI_IO_RAID_PT_REPLY
- PTR_MSG_SCSI_IO_RAID_PT_REQUEST
- PTR_MSG_SCSI_IO_REPLY
- PTR_MSG_SCSI_IO_REQUEST
- PTR_MSG_SCSI_TASK_MGMT_REPLY
- PTR_MSG_SEP_REPLY
- PTR_MSG_SEP_REQUEST
- PTR_MSG_SMP_PASSTHROUGH_REPLY
- PTR_MSG_SMP_PASSTHROUGH_REQUEST
- PTR_MSG_TARGET_ASSIST_EXT_REQUEST
- PTR_MSG_TARGET_ASSIST_REQUEST
- PTR_MSG_TARGET_CMD_BUFFER_POST_BASE_LIST_REPLY
- PTR_MSG_TARGET_CMD_BUFFER_POST_ERROR_REPLY
- PTR_MSG_TARGET_CMD_BUFFER_POST_REPLY
- PTR_MSG_TARGET_CMD_BUFFER_POST_REQUEST
- PTR_MSG_TARGET_CMD_BUF_POST_LIST_REQUEST
- PTR_MSG_TARGET_ERROR_REPLY
- PTR_MSG_TARGET_MODE_ABORT
- PTR_MSG_TARGET_MODE_ABORT_REPLY
- PTR_MSG_TARGET_STATUS_SEND_REQUEST
- PTR_MSG_TOOLBOX_BEACON_REQUEST
- PTR_MSG_TOOLBOX_CLEAN_REQUEST
- PTR_MSG_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST
- PTR_MSG_TOOLBOX_FC_MANAGE_REQUEST
- PTR_MSG_TOOLBOX_ISTWI_READ_WRITE_REQUEST
- PTR_MSG_TOOLBOX_MEM_MOVE_REQUEST
- PTR_MSG_TOOLBOX_REPLY
- PTR_PC
- PTR_PG
- PTR_PTEADDR
- PTR_R0
- PTR_R1
- PTR_R10
- PTR_R11
- PTR_R12
- PTR_R13
- PTR_R14
- PTR_R15
- PTR_R16
- PTR_R17
- PTR_R18
- PTR_R19
- PTR_R2
- PTR_R20
- PTR_R21
- PTR_R22
- PTR_R23
- PTR_R24
- PTR_R25
- PTR_R3
- PTR_R4
- PTR_R5
- PTR_R6
- PTR_R7
- PTR_R8
- PTR_R9
- PTR_RA
- PTR_RAID_PHYS_DISK0_ERROR_DATA
- PTR_RAID_PHYS_DISK0_INQUIRY_DATA
- PTR_RAID_PHYS_DISK0_SETTINGS
- PTR_RAID_PHYS_DISK0_STATUS
- PTR_RAID_PHYS_DISK1_PATH
- PTR_RAID_VOL0_PHYS_DISK
- PTR_RAID_VOL0_SETTINGS
- PTR_RAID_VOL0_STATUS
- PTR_RCV
- PTR_READ
- PTR_REG
- PTR_RESERVED
- PTR_RET
- PTR_RING_PEEK_CALL
- PTR_RING_PEEK_CALL_ANY
- PTR_RING_PEEK_CALL_BH
- PTR_RING_PEEK_CALL_IRQ
- PTR_S
- PTR_SCALESHIFT
- PTR_SCSI_TASK_MGMT
- PTR_SGE_CHAIN32
- PTR_SGE_CHAIN64
- PTR_SGE_CHAIN_UNION
- PTR_SGE_IO_UNION
- PTR_SGE_MPI_UNION
- PTR_SGE_SIMPLE32
- PTR_SGE_SIMPLE64
- PTR_SGE_SIMPLE_UNION
- PTR_SGE_TRANSACTION128
- PTR_SGE_TRANSACTION32
- PTR_SGE_TRANSACTION64
- PTR_SGE_TRANSACTION96
- PTR_SGE_TRANSACTION_UNION
- PTR_SGE_TRANS_SIMPLE_UNION
- PTR_SLL
- PTR_SLLV
- PTR_SP
- PTR_SRA
- PTR_SRAV
- PTR_SRL
- PTR_SRLV
- PTR_STATUS
- PTR_STI
- PTR_STR
- PTR_SUB
- PTR_SUBU
- PTR_TLBACC
- PTR_TLBMISC
- PTR_TO_CTX
- PTR_TO_FLOW_KEYS
- PTR_TO_MAP_VALUE
- PTR_TO_MAP_VALUE_OR_NULL
- PTR_TO_PACKET
- PTR_TO_PACKET_END
- PTR_TO_PACKET_META
- PTR_TO_SOCKET
- PTR_TO_SOCKET_OR_NULL
- PTR_TO_SOCK_COMMON
- PTR_TO_SOCK_COMMON_OR_NULL
- PTR_TO_STACK
- PTR_TO_TCP_SOCK
- PTR_TO_TCP_SOCK_OR_NULL
- PTR_TO_TP_BUFFER
- PTR_TO_XDP_SOCK
- PTR_VAL_NO_CRNG
- PTR_WD_NOSWAP
- PTR_WD_SWAP
- PTR_WIDTH
- PTR_WWN_FORMAT
- PTR__MSG_TARGET_CMD_BUF_POST_BASE_REQUEST
- PTS0_DATA
- PTS0_FN
- PTS0_IN
- PTS0_OUT
- PTS1
- PTS1_DATA
- PTS1_FN
- PTS1_IN
- PTS1_OUT
- PTS2
- PTS2_DATA
- PTS2_FN
- PTS2_IN
- PTS2_OUT
- PTS3
- PTS3_DATA
- PTS3_FN
- PTS3_IN
- PTS3_OUT
- PTS4
- PTS4_DATA
- PTS4_FN
- PTS4_IN
- PTS4_OUT
- PTS5_DATA
- PTS5_FN
- PTS5_IN
- PTS5_OUT
- PTS6_DATA
- PTS6_FN
- PTS6_IN
- PTS6_OUT
- PTS7_DATA
- PTS7_FN
- PTS7_IN
- PTS7_OUT
- PTSCR
- PTSCR_EEBIST_EN
- PTSCR_EEBIST_FAIL
- PTSCR_EELOAD_EN
- PTSCR_RBIST_DONE
- PTSCR_RBIST_EN
- PTSCR_RBIST_FAIL
- PTSCR_RBIST_RST
- PTSHCFG
- PTSHCFG_MASK
- PTSHCFG_SHIFT
- PTSTAT
- PTS_ACTION
- PTS_DTS
- PTS_DTS_FLAGS
- PTS_HSIC
- PTS_ONLY
- PTS_SERIAL
- PTS_ULPI
- PTS_UTMI
- PTT0_DATA
- PTT0_FN
- PTT0_IN
- PTT0_OUT
- PTT1_DATA
- PTT1_FN
- PTT1_IN
- PTT1_OUT
- PTT2_DATA
- PTT2_FN
- PTT2_IN
- PTT2_OUT
- PTT3_DATA
- PTT3_FN
- PTT3_IN
- PTT3_OUT
- PTT4_DATA
- PTT4_FN
- PTT4_IN
- PTT4_OUT
- PTT5_DATA
- PTT5_FN
- PTT5_IN
- PTT5_OUT
- PTT6_DATA
- PTT6_FN
- PTT6_IN
- PTT6_OUT
- PTT7_DATA
- PTT7_FN
- PTT7_IN
- PTT7_OUT
- PTTYPE
- PTTYPE_EPT
- PTT_AC_COOKIE
- PTT_AC_NAME
- PTT_EOL
- PTT_GEN_ERR
- PTT_HOST_UNIQ
- PTT_OFF
- PTT_ON
- PTT_RELAY_SID
- PTT_SRV_ERR
- PTT_SRV_NAME
- PTT_SYS_ERR
- PTT_VENDOR
- PTU
- PTU0_DATA
- PTU0_FN
- PTU0_IN
- PTU0_OUT
- PTU1_DATA
- PTU1_FN
- PTU1_IN
- PTU1_OUT
- PTU2_DATA
- PTU2_FN
- PTU2_IN
- PTU2_OUT
- PTU3_DATA
- PTU3_FN
- PTU3_IN
- PTU3_OUT
- PTU4_DATA
- PTU4_FN
- PTU4_IN
- PTU4_OUT
- PTU5_DATA
- PTU5_FN
- PTU5_IN
- PTU5_OUT
- PTU6_DATA
- PTU6_FN
- PTU6_IN
- PTU6_OUT
- PTU7_DATA
- PTU7_FN
- PTU7_IN
- PTU7_OUT
- PTU_PDE_PAGE_MASK
- PTU_PDE_PAGE_SFT
- PTU_PDE_VALID
- PTU_PTE_LAST
- PTU_PTE_NEXT_TO_LAST
- PTU_PTE_PAGE_MASK
- PTU_PTE_PAGE_SFT
- PTU_PTE_VALID
- PTU_REG_ATC_INIT_ARRAY
- PTU_REG_DBG_DWORD_ENABLE
- PTU_REG_DBG_FORCE_FRAME
- PTU_REG_DBG_FORCE_VALID
- PTU_REG_DBG_SELECT
- PTU_REG_DBG_SHIFT
- PTV
- PTV0_DATA
- PTV0_FN
- PTV0_IN
- PTV0_OUT
- PTV1_DATA
- PTV1_FN
- PTV1_IN
- PTV1_OUT
- PTV2_DATA
- PTV2_FN
- PTV2_IN
- PTV2_OUT
- PTV3_DATA
- PTV3_FN
- PTV3_IN
- PTV3_OUT
- PTV4_DATA
- PTV4_FN
- PTV4_IN
- PTV4_OUT
- PTV5_DATA
- PTV5_FN
- PTV5_IN
- PTV5_OUT
- PTV6_DATA
- PTV6_FN
- PTV6_IN
- PTV6_OUT
- PTV7_DATA
- PTV7_FN
- PTV7_IN
- PTV7_OUT
- PTV_MASK
- PTV_PRESCALER
- PTV_PTE_MASK
- PTV_PTE_SHIFT
- PTV_PT_MASK
- PTW0_DATA
- PTW0_FN
- PTW0_IN
- PTW0_OUT
- PTW1_DATA
- PTW1_FN
- PTW1_IN
- PTW1_OUT
- PTW2_DATA
- PTW2_FN
- PTW2_IN
- PTW2_OUT
- PTW3_DATA
- PTW3_FN
- PTW3_IN
- PTW3_OUT
- PTW4_DATA
- PTW4_FN
- PTW4_IN
- PTW4_OUT
- PTW5_DATA
- PTW5_FN
- PTW5_IN
- PTW5_OUT
- PTW6_DATA
- PTW6_FN
- PTW6_IN
- PTW6_OUT
- PTW7_DATA
- PTW7_FN
- PTW7_IN
- PTW7_OUT
- PTWCR
- PTW_Param
- PTW_Param_Apache
- PTX0_DATA
- PTX0_FN
- PTX0_IN
- PTX0_OUT
- PTX1_DATA
- PTX1_FN
- PTX1_IN
- PTX1_OUT
- PTX2_DATA
- PTX2_FN
- PTX2_IN
- PTX2_OUT
- PTX3_DATA
- PTX3_FN
- PTX3_IN
- PTX3_OUT
- PTX4_DATA
- PTX4_FN
- PTX4_IN
- PTX4_OUT
- PTX5_DATA
- PTX5_FN
- PTX5_IN
- PTX5_OUT
- PTX6_DATA
- PTX6_FN
- PTX6_IN
- PTX6_OUT
- PTX7_DATA
- PTX7_FN
- PTX7_IN
- PTX7_OUT
- PTXCR
- PTXDESC_8723B
- PTXPWRTRACK_CFG
- PTY
- PTY0_DATA
- PTY0_FN
- PTY0_IN
- PTY0_OUT
- PTY1_DATA
- PTY1_FN
- PTY1_IN
- PTY1_OUT
- PTY2_DATA
- PTY2_FN
- PTY2_IN
- PTY2_OUT
- PTY3_DATA
- PTY3_FN
- PTY3_IN
- PTY3_OUT
- PTY4_DATA
- PTY4_FN
- PTY4_IN
- PTY4_OUT
- PTY5_DATA
- PTY5_FN
- PTY5_IN
- PTY5_OUT
- PTY6_DATA
- PTY6_FN
- PTY6_IN
- PTY6_OUT
- PTY7_DATA
- PTY7_FN
- PTY7_IN
- PTY7_OUT
- PTYPE
- PTYPE_ENDPOINT
- PTYPE_HASH_MASK
- PTYPE_HASH_SIZE
- PTYPE_LEGACY_ENDPOINT
- PTYPE_ROOT_PORT
- PTY_MASTER_MAJOR
- PTY_MAX
- PTY_NR
- PTY_SLAVE_MAJOR
- PTY_TYPE_MASTER
- PTY_TYPE_SLAVE
- PTZ0_DATA
- PTZ0_FN
- PTZ0_IN
- PTZ0_OUT
- PTZ1_DATA
- PTZ1_FN
- PTZ1_IN
- PTZ1_OUT
- PTZ2_DATA
- PTZ2_FN
- PTZ2_IN
- PTZ2_OUT
- PTZ3_DATA
- PTZ3_FN
- PTZ3_IN
- PTZ3_OUT
- PTZ4_DATA
- PTZ4_FN
- PTZ4_IN
- PTZ4_OUT
- PTZ5_DATA
- PTZ5_FN
- PTZ5_IN
- PTZ5_OUT
- PTZ6_DATA
- PTZ6_FN
- PTZ6_IN
- PTZ6_OUT
- PTZ7_DATA
- PTZ7_FN
- PTZ7_IN
- PTZ7_OUT
- PT_A0
- PT_A1
- PT_A10
- PT_A11
- PT_A12
- PT_A13
- PT_A14
- PT_A15
- PT_A16
- PT_A17
- PT_A18
- PT_A19
- PT_A2
- PT_A20
- PT_A21
- PT_A22
- PT_A23
- PT_A24
- PT_A25
- PT_A26
- PT_A27
- PT_A28
- PT_A29
- PT_A3
- PT_A30
- PT_A31
- PT_A4
- PT_A4_ORG
- PT_A5
- PT_A6
- PT_A7
- PT_A8
- PT_A9
- PT_ACCESSED_MASK
- PT_ACCESSED_SHIFT
- PT_ACR0
- PT_ACR1
- PT_ACR10
- PT_ACR11
- PT_ACR12
- PT_ACR13
- PT_ACR14
- PT_ACR15
- PT_ACR2
- PT_ACR3
- PT_ACR4
- PT_ACR5
- PT_ACR6
- PT_ACR7
- PT_ACR8
- PT_ACR9
- PT_ADDR_INDX
- PT_AR_BSP
- PT_AR_BSPSTORE
- PT_AR_CCV
- PT_AR_CSD
- PT_AR_EC
- PT_AR_FPSR
- PT_AR_LC
- PT_AR_PFS
- PT_AR_RNAT
- PT_AR_RSC
- PT_AR_SSD
- PT_AR_UNAT
- PT_AUR_BSP
- PT_AUR_BSPSTORE
- PT_AUR_CCV
- PT_AUR_EC
- PT_AUR_FPSR
- PT_AUR_LC
- PT_AUR_PFS
- PT_AUR_RNAT
- PT_AUR_RSC
- PT_AUR_UNAT
- PT_B0
- PT_B1
- PT_B10
- PT_B11
- PT_B12
- PT_B13
- PT_B14
- PT_B15
- PT_B16
- PT_B17
- PT_B18
- PT_B19
- PT_B2
- PT_B20
- PT_B21
- PT_B22
- PT_B23
- PT_B24
- PT_B25
- PT_B26
- PT_B27
- PT_B28
- PT_B29
- PT_B3
- PT_B30
- PT_B31
- PT_B4
- PT_B5
- PT_B6
- PT_B7
- PT_B8
- PT_B9
- PT_BASE_ADDR_MASK
- PT_BLOCKSTEP
- PT_BLOCKSTEP_BIT
- PT_BUFSIZE
- PT_CAP
- PT_CAP_cr3_filtering
- PT_CAP_cycle_thresholds
- PT_CAP_ip_filtering
- PT_CAP_max_subleaf
- PT_CAP_mtc
- PT_CAP_mtc_periods
- PT_CAP_num_address_ranges
- PT_CAP_output_subsys
- PT_CAP_payloads_lip
- PT_CAP_power_event_trace
- PT_CAP_psb_cyc
- PT_CAP_psb_periods
- PT_CAP_ptwrite
- PT_CAP_single_range_output
- PT_CAP_topa_multiple_entries
- PT_CAP_topa_output
- PT_CCR
- PT_CFM
- PT_CK
- PT_CLOCKRATE_REG
- PT_COLOR_BLUE
- PT_COLOR_BRIGHT
- PT_COLOR_DEFAULT
- PT_COLOR_ERROR
- PT_COLOR_GREEN
- PT_COLOR_HEADER_BAR
- PT_COLOR_RED
- PT_COLOR_YELLOW
- PT_CONFIG_MASK
- PT_CPUID_LEAVES
- PT_CPUID_REGS_NUM
- PT_CR_10
- PT_CR_11
- PT_CR_9
- PT_CR_IIP
- PT_CR_IPSR
- PT_CSR
- PT_CTR
- PT_D0
- PT_D1
- PT_D2
- PT_D3
- PT_D4
- PT_D5
- PT_D6
- PT_D7
- PT_DAR
- PT_DATA
- PT_DATA_ADDR
- PT_DBR
- PT_DEFAULT_TIMEOUT
- PT_DIRECTION_REG
- PT_DIRECTORY_LEVEL
- PT_DIRTY_MASK
- PT_DIRTY_SHIFT
- PT_DIR_PAT_MASK
- PT_DIR_PAT_SHIFT
- PT_DP
- PT_DRR_WEIGHT_DEFAULT_10G
- PT_DRR_WEIGHT_DEFAULT_1G
- PT_DRR_WT
- PT_DRR_WT_VAL
- PT_DSCR
- PT_DSISR
- PT_DTRACE
- PT_DYNAMIC
- PT_EAGER
- PT_EAR
- PT_ENDREGS
- PT_ENTRIES
- PT_EOF
- PT_ER0
- PT_ER1
- PT_ER2
- PT_ER3
- PT_ER4
- PT_ER5
- PT_ER6
- PT_ESR
- PT_EVENT_FLAG
- PT_EXITING
- PT_EXITKILL
- PT_EXPECTED
- PT_EXR
- PT_F10
- PT_F100
- PT_F101
- PT_F102
- PT_F103
- PT_F104
- PT_F105
- PT_F106
- PT_F107
- PT_F108
- PT_F109
- PT_F11
- PT_F110
- PT_F111
- PT_F112
- PT_F113
- PT_F114
- PT_F115
- PT_F116
- PT_F117
- PT_F118
- PT_F119
- PT_F12
- PT_F120
- PT_F121
- PT_F122
- PT_F123
- PT_F124
- PT_F125
- PT_F126
- PT_F127
- PT_F13
- PT_F14
- PT_F15
- PT_F16
- PT_F17
- PT_F18
- PT_F19
- PT_F2
- PT_F20
- PT_F21
- PT_F22
- PT_F23
- PT_F24
- PT_F25
- PT_F26
- PT_F27
- PT_F28
- PT_F29
- PT_F3
- PT_F30
- PT_F31
- PT_F32
- PT_F33
- PT_F34
- PT_F35
- PT_F36
- PT_F37
- PT_F38
- PT_F39
- PT_F4
- PT_F40
- PT_F41
- PT_F42
- PT_F43
- PT_F44
- PT_F45
- PT_F46
- PT_F47
- PT_F48
- PT_F49
- PT_F5
- PT_F50
- PT_F51
- PT_F52
- PT_F53
- PT_F54
- PT_F55
- PT_F56
- PT_F57
- PT_F58
- PT_F59
- PT_F6
- PT_F60
- PT_F61
- PT_F62
- PT_F63
- PT_F64
- PT_F65
- PT_F66
- PT_F67
- PT_F68
- PT_F69
- PT_F7
- PT_F70
- PT_F71
- PT_F72
- PT_F73
- PT_F74
- PT_F75
- PT_F76
- PT_F77
- PT_F78
- PT_F79
- PT_F8
- PT_F80
- PT_F81
- PT_F82
- PT_F83
- PT_F84
- PT_F85
- PT_F86
- PT_F87
- PT_F88
- PT_F89
- PT_F9
- PT_F90
- PT_F91
- PT_F92
- PT_F93
- PT_F94
- PT_F95
- PT_F96
- PT_F97
- PT_F98
- PT_F99
- PT_FAILED
- PT_FILTERS_NUM
- PT_FIRST_AVAIL_BITS_SHIFT
- PT_FIX_EXEC_STACK
- PT_FLAG_ETHERNET_FRAME
- PT_FLAG_ISCSI_PDU
- PT_FLAG_ISNS_PDU
- PT_FLAG_SEND_BUFFER
- PT_FLAG_WAIT_4_RESPONSE
- PT_FP
- PT_FPC
- PT_FPR0
- PT_FPR0_HI
- PT_FPR0_LO
- PT_FPR1
- PT_FPR10
- PT_FPR10_HI
- PT_FPR10_LO
- PT_FPR11
- PT_FPR11_HI
- PT_FPR11_LO
- PT_FPR12
- PT_FPR12_HI
- PT_FPR12_LO
- PT_FPR13
- PT_FPR13_HI
- PT_FPR13_LO
- PT_FPR14
- PT_FPR14_HI
- PT_FPR14_LO
- PT_FPR15
- PT_FPR15_HI
- PT_FPR15_LO
- PT_FPR1_HI
- PT_FPR1_LO
- PT_FPR2
- PT_FPR2_HI
- PT_FPR2_LO
- PT_FPR3
- PT_FPR31
- PT_FPR3_HI
- PT_FPR3_LO
- PT_FPR4
- PT_FPR4_HI
- PT_FPR4_LO
- PT_FPR5
- PT_FPR5_HI
- PT_FPR5_LO
- PT_FPR6
- PT_FPR6_HI
- PT_FPR6_LO
- PT_FPR7
- PT_FPR7_HI
- PT_FPR7_LO
- PT_FPR8
- PT_FPR8_HI
- PT_FPR8_LO
- PT_FPR9
- PT_FPR9_HI
- PT_FPR9_LO
- PT_FPSCR
- PT_FPSCR32
- PT_FSR
- PT_G0
- PT_G1
- PT_G2
- PT_G3
- PT_G4
- PT_G5
- PT_G6
- PT_G7
- PT_GLOBAL_MASK
- PT_GNU_EH_FRAME
- PT_GNU_STACK
- PT_GPR
- PT_GPR0
- PT_GPR1
- PT_GPR10
- PT_GPR11
- PT_GPR12
- PT_GPR13
- PT_GPR14
- PT_GPR15
- PT_GPR16
- PT_GPR17
- PT_GPR18
- PT_GPR19
- PT_GPR2
- PT_GPR20
- PT_GPR21
- PT_GPR22
- PT_GPR23
- PT_GPR24
- PT_GPR25
- PT_GPR26
- PT_GPR27
- PT_GPR28
- PT_GPR29
- PT_GPR3
- PT_GPR30
- PT_GPR31
- PT_GPR4
- PT_GPR5
- PT_GPR6
- PT_GPR7
- PT_GPR8
- PT_GPR9
- PT_GUEST_ACCESSED_MASK
- PT_GUEST_ACCESSED_SHIFT
- PT_GUEST_DIRTY_MASK
- PT_GUEST_DIRTY_SHIFT
- PT_HAVE_ACCESSED_DIRTY
- PT_HI
- PT_HIOS
- PT_HIPROC
- PT_HP_CORE_COMM
- PT_HP_CORE_KERNEL
- PT_HP_CORE_LOADABLE
- PT_HP_CORE_MMF
- PT_HP_CORE_NONE
- PT_HP_CORE_PROC
- PT_HP_CORE_SHM
- PT_HP_CORE_STACK
- PT_HP_CORE_VERSION
- PT_HP_FASTBIND
- PT_HP_HSL_ANNOT
- PT_HP_OPT_ANNOT
- PT_HP_PARALLEL
- PT_HP_STACK
- PT_HP_TLS
- PT_I0
- PT_I1
- PT_I2
- PT_I3
- PT_I4
- PT_I5
- PT_I6
- PT_I7
- PT_IA_64_UNWIND
- PT_IBR
- PT_IEEE_IP
- PT_ILC
- PT_INDEX
- PT_INITIAL
- PT_INPUTDATA_REG
- PT_INTERP
- PT_INVALID
- PT_INVALID_FLUSH
- PT_KERNEL_MODE
- PT_LASTOFF
- PT_LEVEL_BITS
- PT_LNK
- PT_LO
- PT_LOAD
- PT_LOOS
- PT_LOPROC
- PT_LS4_FIRST_PACKET_LEN
- PT_LS4_PAYLOAD_OFFSET
- PT_LS4_REQUEST
- PT_LS4_UNSOL
- PT_LVL_ADDR_MASK
- PT_LVL_OFFSET_MASK
- PT_MAGIC
- PT_MAJOR
- PT_MAX_FULL_LEVELS
- PT_MAX_HUGEPAGE_LEVEL
- PT_MAX_PUT_REG
- PT_MAX_RETRIES
- PT_MEDIA
- PT_MIPS_ABIFLAGS
- PT_MIPS_OPTIONS
- PT_MIPS_REGINFO
- PT_MIPS_RTPROC
- PT_MODE_HOST_GUEST
- PT_MODE_SYSTEM
- PT_MQ
- PT_MSR
- PT_NAME
- PT_NAMELEN
- PT_NAT_BITS
- PT_NIP
- PT_NONE
- PT_NOTE
- PT_NPC
- PT_NULL
- PT_OFFSET
- PT_OLD_TIMESPEC
- PT_OLD_TIMEVAL
- PT_OPT_FLAG_SHIFT
- PT_ORIGGPR2
- PT_ORIG_D0
- PT_ORIG_ER0
- PT_ORIG_GPR11
- PT_ORIG_R3
- PT_OUTPUTDATA_REG
- PT_P4D
- PT_PAGE_SIZE_MASK
- PT_PAGE_SIZE_SHIFT
- PT_PAGE_TABLE_LEVEL
- PT_PARISC_ARCHEXT
- PT_PARISC_UNWIND
- PT_PASSED
- PT_PAT_MASK
- PT_PAT_SHIFT
- PT_PC
- PT_PCD_MASK
- PT_PDPE_LEVEL
- PT_PENDING
- PT_PGD
- PT_PHDR
- PT_PMD
- PT_PR
- PT_PRESENT_MASK
- PT_PSR
- PT_PSWADDR
- PT_PSWMASK
- PT_PTE
- PT_PTRACED
- PT_PUD
- PT_PWT_MASK
- PT_R0
- PT_R1
- PT_R10
- PT_R11
- PT_R12
- PT_R13
- PT_R14
- PT_R15
- PT_R16
- PT_R17
- PT_R18
- PT_R19
- PT_R2
- PT_R20
- PT_R21
- PT_R22
- PT_R23
- PT_R24
- PT_R25
- PT_R26
- PT_R27
- PT_R28
- PT_R29
- PT_R3
- PT_R30
- PT_R31
- PT_R4
- PT_R5
- PT_R6
- PT_R7
- PT_R8
- PT_R9
- PT_READ
- PT_READING
- PT_READY_TMO
- PT_READ_INDX
- PT_REG
- PT_REGS_ARM64
- PT_REGS_AX
- PT_REGS_BP
- PT_REGS_BX
- PT_REGS_COUNT
- PT_REGS_CS
- PT_REGS_CX
- PT_REGS_DI
- PT_REGS_DS
- PT_REGS_DX
- PT_REGS_EFLAGS
- PT_REGS_ES
- PT_REGS_FP
- PT_REGS_IP
- PT_REGS_MAGIC
- PT_REGS_OFFSET
- PT_REGS_ORIG_SYSCALL
- PT_REGS_PARM1
- PT_REGS_PARM2
- PT_REGS_PARM3
- PT_REGS_PARM4
- PT_REGS_PARM5
- PT_REGS_R10
- PT_REGS_R11
- PT_REGS_R12
- PT_REGS_R13
- PT_REGS_R14
- PT_REGS_R15
- PT_REGS_R8
- PT_REGS_R9
- PT_REGS_RC
- PT_REGS_RESTART_SYSCALL
- PT_REGS_RET
- PT_REGS_S390
- PT_REGS_SAVES
- PT_REGS_SET_SYSCALL_RETURN
- PT_REGS_SI
- PT_REGS_SP
- PT_REGS_SS
- PT_REGS_SYSCALL_NR
- PT_REGS_SYSCALL_RET
- PT_REGS_UNWIND_INFO
- PT_REG_SIZE
- PT_RELATIVE_CONTROL_FORMATTER
- PT_RESET_CONTROL_FORMATTER
- PT_RESET_TMO
- PT_RESULT
- PT_REWIND
- PT_REWIND_TMO
- PT_RILC
- PT_S390_PGSTE
- PT_SEIZED
- PT_SHLIB
- PT_SIG_1_ADDR
- PT_SIG_1_DATA
- PT_SIG_2_ADDR
- PT_SIG_2_DATA
- PT_SIG_3_ADDR
- PT_SIG_3_DATA
- PT_SIG_4_ADDR
- PT_SIG_4_DATA
- PT_SINGLESTEP
- PT_SINGLESTEP_BIT
- PT_SIZE
- PT_SOFTE
- PT_SP
- PT_SPIN
- PT_SPIN_DEL
- PT_SR
- PT_ST
- PT_STATUS
- PT_STATUS_FORMATTER
- PT_SUSPEND_SECCOMP
- PT_SYNC_REG
- PT_SYSCALLNO
- PT_SYSCALL_NR
- PT_SYSCALL_NR_OFFSET
- PT_SYSCALL_RET_OFFSET
- PT_TESTING
- PT_TEXT_ADDR
- PT_TEXT_END_ADDR
- PT_TEXT_LEN
- PT_TIMESPEC
- PT_TIMEVAL
- PT_TLS
- PT_TMO
- PT_TNPC
- PT_TOTAL_GPIO
- PT_TPC
- PT_TRACESYSGOOD
- PT_TRACE_CLONE
- PT_TRACE_EXEC
- PT_TRACE_EXIT
- PT_TRACE_FORK
- PT_TRACE_SECCOMP
- PT_TRACE_VFORK
- PT_TRACE_VFORK_DONE
- PT_TRAP
- PT_TSR
- PT_TSTATE
- PT_UNITS
- PT_USE
- PT_USER_MASK
- PT_USER_SHIFT
- PT_USE_CNT
- PT_USP
- PT_V9_FP
- PT_V9_G0
- PT_V9_G1
- PT_V9_G2
- PT_V9_G3
- PT_V9_G4
- PT_V9_G5
- PT_V9_G6
- PT_V9_G7
- PT_V9_I0
- PT_V9_I1
- PT_V9_I2
- PT_V9_I3
- PT_V9_I4
- PT_V9_I5
- PT_V9_I6
- PT_V9_I7
- PT_V9_MAGIC
- PT_V9_TNPC
- PT_V9_TPC
- PT_V9_TSTATE
- PT_V9_Y
- PT_VALID
- PT_VERSION
- PT_VR0
- PT_VR0_32
- PT_VRSAVE
- PT_VRSAVE_32
- PT_VSCR
- PT_VSCR_32
- PT_VSR0
- PT_VSR0_32
- PT_VSR31
- PT_WIM
- PT_WRITABLE_MASK
- PT_WRITABLE_SHIFT
- PT_WRITE
- PT_WRITE_OK
- PT_WRITING
- PT_XER
- PT_Y
- PTxCDAR
- PU
- PU16
- PU32
- PU64
- PU8
- PUADEN_BOOT0P_MASK
- PUADEN_BOOT0P_SHIFT
- PUADEN_BOOT1P_MASK
- PUADEN_BOOT1P_SHIFT
- PUADEN_EN3P_MASK
- PUADEN_EN3P_SHIFT
- PUADEN_I2CCTLP_MASK
- PUADEN_I2CCTLP_SHIFT
- PUADEN_I2CSRP_MASK
- PUADEN_I2CSRP_SHIFT
- PUADEN_PWRHOLDP_MASK
- PUADEN_PWRHOLDP_SHIFT
- PUADEN_PWRONP_MASK
- PUADEN_PWRONP_SHIFT
- PUADEN_SLEEPP_MASK
- PUADEN_SLEEPP_SHIFT
- PUBCP_SLEEP
- PUBCP_SLEEP_MODE
- PUBKEY_ALGO_MAX
- PUBKEY_ALGO_RSA
- PUBLICATION
- PUBLIC_ACT_VENDORSPEC
- PUBLIC_DRV_MB
- PUBLIC_FUNC
- PUBLIC_GLOBAL
- PUBLIC_MAX_SECTIONS
- PUBLIC_MFW_MB
- PUBLIC_PATH
- PUBLIC_PORT
- PUBLIC_QUEUE_IDX
- PUB_ACTION_ATTR_ID
- PUB_KEY_BUF_SIZE
- PUB_NOT_ASSOC
- PUCAN_BUS_BUSOFF
- PUCAN_BUS_PASSIVE
- PUCAN_BUS_WARNING
- PUCAN_CMD_CLR_DIS_OPTION
- PUCAN_CMD_END_OF_COLLECTION
- PUCAN_CMD_FILTER_STD
- PUCAN_CMD_LISTEN_ONLY_MODE
- PUCAN_CMD_NOP
- PUCAN_CMD_NORMAL_MODE
- PUCAN_CMD_RESERVED2
- PUCAN_CMD_RESET_MODE
- PUCAN_CMD_RX_BARRIER
- PUCAN_CMD_SET_EN_OPTION
- PUCAN_CMD_SET_STD_FILTER
- PUCAN_CMD_TIMING_FAST
- PUCAN_CMD_TIMING_SLOW
- PUCAN_CMD_TX_ABORT
- PUCAN_CMD_WR_ERR_CNT
- PUCAN_ERMSG_BIT_ERROR
- PUCAN_ERMSG_ERR_CNT_DEC
- PUCAN_ERMSG_FORM_ERROR
- PUCAN_ERMSG_OTHER_ERROR
- PUCAN_ERMSG_STUFF_ERROR
- PUCAN_FLTSTD_ROW_IDX_BITS
- PUCAN_FLTSTD_ROW_IDX_MAX
- PUCAN_H
- PUCAN_MSG_BITRATE_SWITCH
- PUCAN_MSG_BUSLOAD
- PUCAN_MSG_CACHE_CRITICAL
- PUCAN_MSG_CAN_RX
- PUCAN_MSG_CAN_TX
- PUCAN_MSG_CHANNEL_DLC
- PUCAN_MSG_ERROR
- PUCAN_MSG_ERROR_STATE_IND
- PUCAN_MSG_EXT_DATA_LEN
- PUCAN_MSG_EXT_ID
- PUCAN_MSG_LOOPED_BACK
- PUCAN_MSG_RTR
- PUCAN_MSG_SELF_RECEIVE
- PUCAN_MSG_SINGLE_SHOT
- PUCAN_MSG_STATUS
- PUCAN_OPTION_BUSLOAD
- PUCAN_OPTION_CANDFDISO
- PUCAN_OPTION_ERROR
- PUCAN_RX_BARRIER
- PUCAN_TFAST_BRP
- PUCAN_TFAST_BRP_BITS
- PUCAN_TFAST_BRP_MASK
- PUCAN_TFAST_SJW
- PUCAN_TFAST_SJW_BITS
- PUCAN_TFAST_SJW_MASK
- PUCAN_TFAST_TSEG1
- PUCAN_TFAST_TSEG1_MASK
- PUCAN_TFAST_TSEG2
- PUCAN_TFAST_TSEG2_MASK
- PUCAN_TFAST_TSGEG1_BITS
- PUCAN_TFAST_TSGEG2_BITS
- PUCAN_TSLOW_BRP
- PUCAN_TSLOW_BRP_BITS
- PUCAN_TSLOW_BRP_MASK
- PUCAN_TSLOW_SJW_BITS
- PUCAN_TSLOW_SJW_MASK
- PUCAN_TSLOW_SJW_T
- PUCAN_TSLOW_TSEG1
- PUCAN_TSLOW_TSEG1_MASK
- PUCAN_TSLOW_TSEG2
- PUCAN_TSLOW_TSEG2_MASK
- PUCAN_TSLOW_TSGEG1_BITS
- PUCAN_TSLOW_TSGEG2_BITS
- PUCAN_TX_ABORT_FLUSH
- PUCAN_WRERRCNT_RE
- PUCAN_WRERRCNT_TE
- PUCHAR
- PUDA_CQ_CREATED
- PUDA_HASH_CRC_COMPLETE
- PUDA_QP_CREATED
- PUDA_RX_COMPLETE
- PUDA_TX_COMPLETE
- PUDCDN
- PUD_2711_MASK
- PUD_2711_REG_OFFSET
- PUD_2711_REG_SHIFT
- PUD_BAD_BITS
- PUD_BITS
- PUD_CACHE_INDEX
- PUD_FLAGS
- PUD_INDEX
- PUD_INDEX_SIZE
- PUD_LEVEL_MULT
- PUD_MASK
- PUD_MASKED_BITS
- PUD_ORDER
- PUD_PAGE_MASK
- PUD_PAGE_SIZE
- PUD_S2_RDONLY
- PUD_S2_RDWR
- PUD_S2_XN
- PUD_SHIFT
- PUD_SIZE
- PUD_TABLE_BIT
- PUD_TABLE_SIZE
- PUD_TYPE_MASK
- PUD_TYPE_SECT
- PUD_TYPE_TABLE
- PUD_VAL_BITS
- PUE2
- PULLBYTE
- PULLCTL_CONF
- PULLTYPESEL_SHIFT
- PULLUDEN_SHIFT
- PULLUPDOWN_REG_A
- PULL_DIS
- PULL_DISABLE
- PULL_DOWN
- PULL_DOWN_ENABLE_OFF
- PULL_DOWN_MASK
- PULL_DOWN_SHIFT
- PULL_DWN_CTRL_0
- PULL_DWN_CTRL_1
- PULL_DWN_CTRL_2
- PULL_DWN_CTRL_3
- PULL_DWN_CTRL_4
- PULL_DWN_CTRL_NA
- PULL_ENA
- PULL_ENABLE
- PULL_EN_SET
- PULL_MASK
- PULL_PG
- PULL_PINS_BITS
- PULL_PINS_MASK
- PULL_PINS_PER_REG
- PULL_PRESENT
- PULL_REG
- PULL_REGS_OFFSET
- PULL_REG_7XX
- PULL_SHIFT
- PULL_TYPE_IO_1V8_ONLY
- PULL_TYPE_IO_DEFAULT
- PULL_TYPE_MAX
- PULL_UNKNOWN
- PULL_UP
- PULL_UP_20K
- PULL_UP_4_7K
- PULL_UP_DN
- PULL_UP_ENABLE_OFF
- PULL_UP_MASK
- PULL_UP_RESISTOR
- PULL_UP_SEL_OFF
- PULL_UP_SHIFT
- PULL_WIDTH
- PULONG
- PULSE
- PULSE0
- PULSE1
- PULSE2
- PULSE3
- PULSEN_BIT
- PULSE_BIT
- PULSE_END
- PULSE_LAST_END_A
- PULSE_LAST_END_B
- PULSE_LAST_END_C
- PULSE_LAST_END_D
- PULSE_LAST_START_A
- PULSE_LAST_START_B
- PULSE_LAST_START_C
- PULSE_LAST_START_D
- PULSE_LEN
- PULSE_MASK
- PULSE_MODE_NORMAL
- PULSE_MODE_ONE_CLOCK
- PULSE_MODE_OPT_NO_HSA
- PULSE_MODE_OPT_SEND
- PULSE_POLARITY_HIGH
- PULSE_POLARITY_LOW
- PULSE_PROG
- PULSE_QUAL_ALWAYS
- PULSE_QUAL_VACTIVE
- PULSE_QUAL_VACTIVE1
- PULSE_SPUE
- PULSE_START
- PULSE_TIME_0_MS
- PULSE_TIME_128_MS
- PULSE_TIME_160_MS
- PULSE_TIME_196_MS
- PULSE_TIME_224_MS
- PULSE_TIME_256_MS
- PULSE_TIME_288_MS
- PULSE_TIME_320_MS
- PULSE_TIME_32_MS
- PULSE_TIME_352_MS
- PULSE_TIME_384_MS
- PULSE_TIME_416_MS
- PULSE_TIME_448_MS
- PULSE_TIME_480_MS
- PULSE_TIME_64_MS
- PULSE_TIME_92_MS
- PULS_1300MS
- PULS_170MS
- PULS_21MS
- PULS_340MS
- PULS_42MS
- PULS_670MS
- PULS_84MS
- PULS_NO_STR
- PUN
- PUNC
- PUNCT
- PUNCT_DEC
- PUNCT_INC
- PUNC_ALL
- PUNC_LEVEL
- PUNC_LEVEL_DEC
- PUNC_LEVEL_INC
- PUNC_MOST
- PUNC_SOME
- PUNIMPL
- PUNIT_DEVICE_NAME
- PUNIT_FUSE_BUS1
- PUNIT_FUSE_BUS2
- PUNIT_GPU_DUTYCYCLE_REG
- PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
- PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
- PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
- PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
- PUNIT_GPU_STATUS_MAX_FREQ_MASK
- PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
- PUNIT_GPU_STATUS_REG
- PUNIT_MAILBOX_BUSY_BIT
- PUNIT_MAILBOX_DATA
- PUNIT_MAILBOX_INTERFACE
- PUNIT_PWGT_IDX_DISP2D
- PUNIT_PWGT_IDX_DPIO_CMN_BC
- PUNIT_PWGT_IDX_DPIO_CMN_D
- PUNIT_PWGT_IDX_DPIO_RX0
- PUNIT_PWGT_IDX_DPIO_RX1
- PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01
- PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23
- PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01
- PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23
- PUNIT_PWGT_IDX_MEDIA
- PUNIT_PWGT_IDX_RENDER
- PUNIT_PWRGT_CLK_GATE
- PUNIT_PWRGT_MASK
- PUNIT_PWRGT_PWR_GATE
- PUNIT_PWRGT_PWR_ON
- PUNIT_PWRGT_RESET
- PUNIT_REG_CZ_TIMESTAMP
- PUNIT_REG_DDR_SETUP2
- PUNIT_REG_DSPSSPM
- PUNIT_REG_GPU_FREQ_REQ
- PUNIT_REG_GPU_FREQ_STS
- PUNIT_REG_GPU_LFM
- PUNIT_REG_ISPSSPM0
- PUNIT_REG_ISPSSPM1
- PUNIT_REG_MEDIA_TURBO_FREQ_REQ
- PUNIT_REG_PWRGT_CTRL
- PUNIT_REG_PWRGT_STATUS
- PUNIT_REG_VEDSSPM0
- PUNIT_REG_VEDSSPM1
- PUNIT_SEMAPHORE_ACQUIRE
- PUNIT_SEMAPHORE_BIT
- PUNIT_SEMAPHORE_BYT
- PUNIT_SEMAPHORE_CHT
- PUP
- PUPD_BASE1
- PUPD_BASE2
- PUPD_DATA
- PUPD_SET
- PURE_LB_TC
- PURGE_ALL
- PUSB_PWR_FST_REG_ACCESS
- PUSB_PWR_FST_REG_ACCESS_STAT
- PUSB_PWR_PSO_DS
- PUSB_PWR_PSO_EN
- PUSB_PWR_STB_CLK_SWITCH_DONE
- PUSB_PWR_STB_CLK_SWITCH_EN
- PUSHF
- PUSHORT
- PUSHP
- PUSHPULL
- PUSHR_CMD
- PUSHR_TX
- PUSH_BASIC_STACK
- PUSH_CNT
- PUSH_CONSTANT_DEREF_DISABLE
- PUSH_CR
- PUSH_FPU
- PUSH_GS
- PUSH_LR
- PUSH_NVREGS
- PUSH_NVREGS_BELOW_FPU
- PUSH_SECTION_IRQENTRY
- PUSH_TIME_DEFAULT
- PUSH_TIME_ODD
- PUSH_VMX
- PUSH_WIDTH
- PUT
- PUTBYTE
- PUTOPT
- PUTOPT_U64
- PUTREG
- PUTU32
- PUT_16
- PUT_16BE
- PUT_16LE
- PUT_32
- PUT_32BE
- PUT_32LE
- PUT_64
- PUT_64BE
- PUT_64LE
- PUT_BBP_RESET
- PUT_BE
- PUT_BITS
- PUT_BLOCK_2
- PUT_BLOCK_4
- PUT_BYTE
- PUT_B_FREE_SPACE
- PUT_B_I_POS_UNFM_POINTER
- PUT_B_LEVEL
- PUT_B_NR_ITEMS
- PUT_B_N_CHILD_NUM
- PUT_COUNTER
- PUT_EXTRADATA
- PUT_FIELD
- PUT_LE
- PUT_RING
- PUT_SB_BLOCK_COUNT
- PUT_SB_BMAP_NR
- PUT_SB_FREE_BLOCKS
- PUT_SB_REISERFS_STATE
- PUT_SB_ROOT_BLOCK
- PUT_SB_TREE_HEIGHT
- PUT_SB_VERSION
- PUT_SIGSET
- PUT_SINFO
- PUT_SINFO_U64
- PUT_STAT_S32
- PUT_STAT_U32
- PUT_STAT_U64
- PUT_TIDVAL_U64
- PUT_TSTAT_U32
- PUT_TSTAT_U64
- PUT_TXQVAL_U32
- PUT_U64
- PUT_USER
- PUV3_I2C_PM
- PU_BRIGHTNESS_CONTROL
- PU_CMD
- PU_CONTRAST_CONTROL
- PU_DAT
- PU_HUE_CONTROL
- PU_PD_REG
- PU_PD_SEL_0
- PU_PD_SEL_1
- PU_PD_SEL_2
- PU_PD_SEL_3
- PU_PD_SEL_4
- PU_PD_SEL_NA
- PU_SATURATION_CONTROL
- PU_SHARPNESS_CONTROL
- PU_SOC_VOLTAGE_HIGH
- PU_SOC_VOLTAGE_NORMAL
- PV
- PV1
- PV2
- PV32P2_BEL
- PV32P2_V21
- PV32P2_V22A
- PV32P2_V22B
- PV32P2_V22C
- PV32P2_V23R
- PV32P3_AMOD
- PV32P3_V23B
- PV32P3_V32B
- PV32P4_120
- PV32P4_144
- PV32P4_48
- PV32P4_96
- PV32P4_B96
- PV32P4_UT120
- PV32P4_UT144
- PV32P4_UT48
- PV32P4_UT96
- PV32P4_UTB96
- PV32P5_120
- PV32P5_144
- PV32P5_48
- PV32P5_96
- PV32P5_B96
- PV32P5_UT120
- PV32P5_UT144
- PV32P5_UT48
- PV32P5_UT96
- PV32P5_UTB96
- PV32P6_ATN
- PV32P6_CTN
- PV88060_BUCK
- PV88060_BUCK_EN
- PV88060_BUCK_ILIM_MASK
- PV88060_BUCK_ILIM_SHIFT
- PV88060_BUCK_MODE_AUTO
- PV88060_BUCK_MODE_MASK
- PV88060_BUCK_MODE_SHIFT
- PV88060_BUCK_MODE_SLEEP
- PV88060_BUCK_MODE_SYNC
- PV88060_E_OVER_TEMP
- PV88060_E_VDD_FLT
- PV88060_ID_BUCK1
- PV88060_ID_LDO1
- PV88060_ID_LDO2
- PV88060_ID_LDO3
- PV88060_ID_LDO4
- PV88060_ID_LDO5
- PV88060_ID_LDO6
- PV88060_ID_LDO7
- PV88060_ID_SW1
- PV88060_ID_SW2
- PV88060_ID_SW3
- PV88060_ID_SW4
- PV88060_ID_SW5
- PV88060_ID_SW6
- PV88060_LDO
- PV88060_LDO_EN
- PV88060_MAX_REGULATORS
- PV88060_M_OVER_TEMP
- PV88060_M_VDD_FLT
- PV88060_REG_BUCK1_CONF0
- PV88060_REG_BUCK1_CONF1
- PV88060_REG_EVENT_A
- PV88060_REG_LDO1_CONF
- PV88060_REG_LDO2_CONF
- PV88060_REG_LDO3_CONF
- PV88060_REG_LDO4_CONF
- PV88060_REG_LDO5_CONF
- PV88060_REG_LDO6_CONF
- PV88060_REG_LDO7_CONF
- PV88060_REG_MASK_A
- PV88060_REG_MASK_B
- PV88060_REG_MASK_C
- PV88060_REG_SW1_CONF
- PV88060_REG_SW2_CONF
- PV88060_REG_SW3_CONF
- PV88060_REG_SW4_CONF
- PV88060_REG_SW5_CONF
- PV88060_REG_SW6_CONF
- PV88060_SW
- PV88060_SW_EN
- PV88060_VBUCK_MASK
- PV88060_VLDO_MASK
- PV88080AA_REG_BUCK1_CONF0
- PV88080AA_REG_BUCK1_CONF1
- PV88080AA_REG_BUCK1_CONF2
- PV88080AA_REG_BUCK1_CONF5
- PV88080AA_REG_BUCK2_CONF0
- PV88080AA_REG_BUCK2_CONF1
- PV88080AA_REG_BUCK2_CONF2
- PV88080AA_REG_BUCK2_CONF5
- PV88080AA_REG_BUCK3_CONF0
- PV88080AA_REG_BUCK3_CONF1
- PV88080AA_REG_BUCK3_CONF2
- PV88080AA_REG_BUCK3_CONF5
- PV88080AA_REG_HVBUCK_CONF1
- PV88080AA_REG_HVBUCK_CONF2
- PV88080BA_REG_BUCK1_CONF0
- PV88080BA_REG_BUCK1_CONF1
- PV88080BA_REG_BUCK1_CONF2
- PV88080BA_REG_BUCK1_CONF5
- PV88080BA_REG_BUCK2_CONF0
- PV88080BA_REG_BUCK2_CONF1
- PV88080BA_REG_BUCK2_CONF2
- PV88080BA_REG_BUCK2_CONF5
- PV88080BA_REG_BUCK3_CONF0
- PV88080BA_REG_BUCK3_CONF1
- PV88080BA_REG_BUCK3_CONF2
- PV88080BA_REG_BUCK3_CONF5
- PV88080BA_REG_HVBUCK_CONF1
- PV88080BA_REG_HVBUCK_CONF2
- PV88080_BUCK
- PV88080_BUCK1_EN
- PV88080_BUCK1_ILIM_MASK
- PV88080_BUCK1_ILIM_SHIFT
- PV88080_BUCK1_MODE_MASK
- PV88080_BUCK2_EN
- PV88080_BUCK2_ILIM_MASK
- PV88080_BUCK2_ILIM_SHIFT
- PV88080_BUCK2_MODE_MASK
- PV88080_BUCK3_EN
- PV88080_BUCK3_ILIM_MASK
- PV88080_BUCK3_ILIM_SHIFT
- PV88080_BUCK3_MODE_MASK
- PV88080_BUCK_MODE_AUTO
- PV88080_BUCK_MODE_SLEEP
- PV88080_BUCK_MODE_SYNC
- PV88080_BUCK_VDAC_RANGE_1
- PV88080_BUCK_VDAC_RANGE_2
- PV88080_BUCK_VDAC_RANGE_MASK
- PV88080_BUCK_VDAC_RANGE_SHIFT
- PV88080_BUCK_VRANGE_GAIN_1
- PV88080_BUCK_VRANGE_GAIN_2
- PV88080_BUCK_VRANGE_GAIN_MASK
- PV88080_BUCK_VRANGE_GAIN_SHIFT
- PV88080_E_OVER_TEMP
- PV88080_E_VDD_FLT
- PV88080_HVBUCK
- PV88080_HVBUCK_EN
- PV88080_ID_BUCK1
- PV88080_ID_BUCK2
- PV88080_ID_BUCK3
- PV88080_ID_HVBUCK
- PV88080_MAX_REGULATORS
- PV88080_M_OVER_TEMP
- PV88080_M_VDD_FLT
- PV88080_REG_EVENT_A
- PV88080_REG_MASK_A
- PV88080_REG_MASK_B
- PV88080_REG_MASK_C
- PV88080_VBUCK1_MASK
- PV88080_VBUCK2_MASK
- PV88080_VBUCK3_MASK
- PV88080_VHVBUCK_MASK
- PV88090_BUCK
- PV88090_BUCK1_EN
- PV88090_BUCK1_ILIM_MASK
- PV88090_BUCK1_ILIM_SHIFT
- PV88090_BUCK1_MODE_MASK
- PV88090_BUCK2_EN
- PV88090_BUCK2_ILIM_MASK
- PV88090_BUCK2_ILIM_SHIFT
- PV88090_BUCK2_MODE_MASK
- PV88090_BUCK3_EN
- PV88090_BUCK3_ILIM_MASK
- PV88090_BUCK3_ILIM_SHIFT
- PV88090_BUCK3_MODE_MASK
- PV88090_BUCK_MODE_AUTO
- PV88090_BUCK_MODE_SLEEP
- PV88090_BUCK_MODE_SYNC
- PV88090_BUCK_VDAC_RANGE_1
- PV88090_BUCK_VDAC_RANGE_2
- PV88090_BUCK_VDAC_RANGE_MASK
- PV88090_BUCK_VDAC_RANGE_SHIFT
- PV88090_BUCK_VRANGE_GAIN_1
- PV88090_BUCK_VRANGE_GAIN_2
- PV88090_BUCK_VRANGE_GAIN_MASK
- PV88090_BUCK_VRANGE_GAIN_SHIFT
- PV88090_E_OVER_TEMP
- PV88090_E_VDD_FLT
- PV88090_ID_BUCK1
- PV88090_ID_BUCK2
- PV88090_ID_BUCK3
- PV88090_ID_LDO1
- PV88090_ID_LDO2
- PV88090_LDO
- PV88090_LDO1_EN
- PV88090_LDO2_EN
- PV88090_MAX_REGULATORS
- PV88090_M_OVER_TEMP
- PV88090_M_VDD_FLT
- PV88090_REG_BUCK1_CONF0
- PV88090_REG_BUCK1_CONF1
- PV88090_REG_BUCK1_CONF2
- PV88090_REG_BUCK2_CONF0
- PV88090_REG_BUCK2_CONF1
- PV88090_REG_BUCK2_CONF2
- PV88090_REG_BUCK3_CONF0
- PV88090_REG_BUCK3_CONF1
- PV88090_REG_BUCK3_CONF2
- PV88090_REG_BUCK_FOLD_RANGE
- PV88090_REG_EVENT_A
- PV88090_REG_LDO1_CONT
- PV88090_REG_LDO2_CONT
- PV88090_REG_LDO3_CONT
- PV88090_REG_MASK_A
- PV88090_REG_MASK_B
- PV88090_VBUCK1_MASK
- PV88090_VBUCK2_MASK
- PV88090_VBUCK3_MASK
- PV88090_VLDO1_MASK
- PV88090_VLDO2_MASK
- PVCALLS_ACCEPT
- PVCALLS_BIND
- PVCALLS_CONNECT
- PVCALLS_FLAG_ACCEPT_INFLIGHT
- PVCALLS_FLAG_POLL_INFLIGHT
- PVCALLS_FLAG_POLL_RET
- PVCALLS_FRONT_MAX_SPIN
- PVCALLS_INVALID_ID
- PVCALLS_LISTEN
- PVCALLS_NR_RSP_PER_RING
- PVCALLS_POLL
- PVCALLS_RELEASE
- PVCALLS_RING_ORDER
- PVCALLS_SOCKET
- PVCALLS_STATUS_BIND
- PVCALLS_STATUS_LISTEN
- PVCALLS_STATUS_UNINITALIZED
- PVCALLS_VERSIONS
- PVCLOCK_COUNTS_FROM_ZERO
- PVCLOCK_GUEST_STOPPED
- PVCLOCK_TSC_STABLE_BIT
- PVCR
- PVCR_CommandDelay
- PVCR_VCSA
- PVC_BUSY
- PVC_CMDFLAG_CONTINUE
- PVC_CMDFLAG_INTERFACE
- PVC_CMDFLAG_INTERRUPT
- PVC_CMDFLAG_SERIALIZE
- PVC_DATA_M_100
- PVC_DATA_M_200
- PVC_DATA_SHIFT_100
- PVC_DATA_SHIFT_200
- PVC_DISPMEM
- PVC_EG_TAG
- PVC_EG_TAG_MASK
- PVC_ERRORCODE_INVALID_COMMAND
- PVC_ERRORCODE_INVALID_CONTROL
- PVC_ERRORCODE_INVALID_DATA
- PVC_ERRORCODE_NAK
- PVC_ERRORCODE_TIMEOUT
- PVC_ERRORCODE_UNKNOWN
- PVC_E_100
- PVC_E_200
- PVC_HARDWARE_DESCRIPTOR
- PVC_INFRARED_UNIT
- PVC_INTERFACE_DESCRIPTOR
- PVC_LINELEN
- PVC_NLINES
- PVC_REG_100
- PVC_REG_200
- PVC_RESPONSEFLAG_CONTINUED
- PVC_RESPONSEFLAG_ERROR
- PVC_RESPONSEFLAG_INTERFACE
- PVC_RESPONSEFLAG_OVERFLOW
- PVC_RESPONSEFLAG_RESET
- PVC_RS_100
- PVC_RS_200
- PVC_RW_100
- PVC_RW_200
- PVC_VISIBLE_CHARS
- PVDD
- PVD_FLAGS_VSID_COMMON
- PVGAMCTRL
- PVH_CANARY_SEL
- PVH_CS_SEL
- PVH_DS_SEL
- PVH_GDT_ENTRY_CANARY
- PVH_GDT_ENTRY_CS
- PVH_GDT_ENTRY_DS
- PVI_MASK_MIPI
- PVMW_MIGRATION
- PVMW_SYNC
- PVM_MAX_KMALLOC_PAGES
- PVM_MAX_PP_ARRAY_COUNT
- PVOID
- PVOP_CALL0
- PVOP_CALL1
- PVOP_CALL2
- PVOP_CALL3
- PVOP_CALL4
- PVOP_CALLEE0
- PVOP_CALLEE1
- PVOP_CALLEE2
- PVOP_CALLEE_CLOBBERS
- PVOP_CALL_ARG1
- PVOP_CALL_ARG2
- PVOP_CALL_ARG3
- PVOP_CALL_ARG4
- PVOP_CALL_ARGS
- PVOP_CALL_CLOBBERS
- PVOP_RETMASK
- PVOP_TEST_NULL
- PVOP_VCALL0
- PVOP_VCALL1
- PVOP_VCALL2
- PVOP_VCALL3
- PVOP_VCALL4
- PVOP_VCALLEE0
- PVOP_VCALLEE1
- PVOP_VCALLEE2
- PVOP_VCALLEE_CLOBBERS
- PVOP_VCALL_ARGS
- PVOP_VCALL_CLOBBERS
- PVPANIC_PANICKED
- PVR
- PVR0_ENDI
- PVR0_PVR_FULL_MASK
- PVR0_USER1_MASK
- PVR0_USE_BARREL_MASK
- PVR0_USE_BTC
- PVR0_USE_DCACHE_MASK
- PVR0_USE_DIV_MASK
- PVR0_USE_EXC_MASK
- PVR0_USE_FPU_MASK
- PVR0_USE_HW_MUL_MASK
- PVR0_USE_ICACHE_MASK
- PVR0_USE_MMU
- PVR0_VERSION_MASK
- PVR10_TARGET_FAMILY_MASK
- PVR11_MMU_DTLB_SIZE
- PVR11_MMU_ITLB_SIZE
- PVR11_MMU_PRIVINS
- PVR11_MMU_TLB_ACCESS
- PVR11_MMU_ZONES
- PVR11_MSR_RESET_VALUE_MASK
- PVR11_USE_MMU
- PVR1_USER2_MASK
- PVR2_AREA_OPTIMISED
- PVR2_CASCADE_CHAN
- PVR2_CID_AUDIOMODE
- PVR2_CID_CROPCAPBH
- PVR2_CID_CROPCAPBL
- PVR2_CID_CROPCAPBT
- PVR2_CID_CROPCAPBW
- PVR2_CID_CROPCAPPAD
- PVR2_CID_CROPCAPPAN
- PVR2_CID_CROPH
- PVR2_CID_CROPL
- PVR2_CID_CROPT
- PVR2_CID_CROPW
- PVR2_CID_FREQUENCY
- PVR2_CID_HRES
- PVR2_CID_INPUT
- PVR2_CID_STDAVAIL
- PVR2_CID_STDCUR
- PVR2_CID_STDDETECT
- PVR2_CID_VRES
- PVR2_CLIENT_ID_CS53L32A
- PVR2_CLIENT_ID_CX25840
- PVR2_CLIENT_ID_DEMOD
- PVR2_CLIENT_ID_MSP3400
- PVR2_CLIENT_ID_NULL
- PVR2_CLIENT_ID_SAA7115
- PVR2_CLIENT_ID_TUNER
- PVR2_CLIENT_ID_WM8775
- PVR2_COMPOSE_BE
- PVR2_COMPOSE_LE
- PVR2_CTLD_INFO_DESC_SIZE
- PVR2_CTL_BUFFSIZE
- PVR2_CTL_READ_ENDPOINT
- PVR2_CTL_WRITE_ENDPOINT
- PVR2_CVAL_HSM_FAIL
- PVR2_CVAL_HSM_FULL
- PVR2_CVAL_HSM_HIGH
- PVR2_CVAL_INPUT_COMPOSITE
- PVR2_CVAL_INPUT_DTV
- PVR2_CVAL_INPUT_MAX
- PVR2_CVAL_INPUT_RADIO
- PVR2_CVAL_INPUT_SVIDEO
- PVR2_CVAL_INPUT_TV
- PVR2_DECOMPOSE_BE
- PVR2_DECOMPOSE_LE
- PVR2_DIGITAL_SCHEME_HAUPPAUGE
- PVR2_DIGITAL_SCHEME_NONE
- PVR2_DIGITAL_SCHEME_ONAIR
- PVR2_DIV_ZERO_EXC_MASK
- PVR2_DMA_ADDR
- PVR2_DMA_BASE
- PVR2_DMA_COUNT
- PVR2_DMA_LMMODE0
- PVR2_DMA_LMMODE1
- PVR2_DMA_MODE
- PVR2_DOPB_BUS_EXC_MASK
- PVR2_DVB_BUFFER_COUNT
- PVR2_DVB_BUFFER_SIZE
- PVR2_D_LMB_MASK
- PVR2_D_OPB_MASK
- PVR2_D_PLB_MASK
- PVR2_EDGE_IS_POSITIVE_MASK
- PVR2_FIRMWARE_160xxx
- PVR2_FIRMWARE_24xxx
- PVR2_FIRMWARE_29xxx
- PVR2_FIRMWARE_73xxx
- PVR2_FIRMWARE_75xxx
- PVR2_FIRMWARE_ENDPOINT
- PVR2_FPU_EXC_MASK
- PVR2_GPIO_DIR
- PVR2_GPIO_IN
- PVR2_GPIO_OUT
- PVR2_I2C_FUNC_CNT
- PVR2_ILL_OPCODE_EXC_MASK
- PVR2_INTERCONNECT
- PVR2_INTERRUPT_IS_EDGE_MASK
- PVR2_IOPB_BUS_EXC_MASK
- PVR2_IR_SCHEME_24XXX
- PVR2_IR_SCHEME_24XXX_MCE
- PVR2_IR_SCHEME_29XXX
- PVR2_IR_SCHEME_NONE
- PVR2_IR_SCHEME_ZILOG
- PVR2_I_LMB_MASK
- PVR2_I_OPB_MASK
- PVR2_I_PLB_MASK
- PVR2_LED_SCHEME_HAUPPAUGE
- PVR2_LED_SCHEME_NONE
- PVR2_OPCODE_0x0_ILL_MASK
- PVR2_PATHWAY_ANALOG
- PVR2_PATHWAY_DIGITAL
- PVR2_PATHWAY_UNKNOWN
- PVR2_ROUTING_SCHEME_AV400
- PVR2_ROUTING_SCHEME_GOTVIEW
- PVR2_ROUTING_SCHEME_HAUP160XXX
- PVR2_ROUTING_SCHEME_HAUPPAUGE
- PVR2_ROUTING_SCHEME_ONAIR
- PVR2_STATE_COLD
- PVR2_STATE_DEAD
- PVR2_STATE_ERROR
- PVR2_STATE_NONE
- PVR2_STATE_READY
- PVR2_STATE_RUN
- PVR2_STATE_WARM
- PVR2_SUBDEV_SET_CONTROL
- PVR2_TRACE_BUF_FLOW
- PVR2_TRACE_BUF_POOL
- PVR2_TRACE_CHIPS
- PVR2_TRACE_CTL
- PVR2_TRACE_CTXT
- PVR2_TRACE_DATA_FLOW
- PVR2_TRACE_DEBUGIFC
- PVR2_TRACE_DVB_FEED
- PVR2_TRACE_EEPROM
- PVR2_TRACE_ENCODER
- PVR2_TRACE_ERROR_LEGS
- PVR2_TRACE_FIRMWARE
- PVR2_TRACE_GPIO
- PVR2_TRACE_I2C
- PVR2_TRACE_I2C_CMD
- PVR2_TRACE_I2C_CORE
- PVR2_TRACE_I2C_TRAF
- PVR2_TRACE_INFO
- PVR2_TRACE_INIT
- PVR2_TRACE_OPEN_CLOSE
- PVR2_TRACE_START_STOP
- PVR2_TRACE_STATE
- PVR2_TRACE_STBITS
- PVR2_TRACE_STD
- PVR2_TRACE_STRUCT
- PVR2_TRACE_SYSFS
- PVR2_TRACE_TOLERANCE
- PVR2_TRACE_TRAP
- PVR2_TRACE_V4LIOCTL
- PVR2_UNALIGNED_EXC_MASK
- PVR2_UNK_ENDPOINT
- PVR2_USE_BARREL_MASK
- PVR2_USE_DIV_MASK
- PVR2_USE_DPLBEXC
- PVR2_USE_EXTEND_FSL
- PVR2_USE_FPU2_MASK
- PVR2_USE_FPU_MASK
- PVR2_USE_FSL_EXC
- PVR2_USE_HW_MUL_MASK
- PVR2_USE_IPLBEXC
- PVR2_USE_MSR_INSTR
- PVR2_USE_MUL64_MASK
- PVR2_USE_PCMP_INSTR
- PVR2_VBI_ENDPOINT
- PVR2_VID_ENDPOINT
- PVR3_DEBUG_ENABLED_MASK
- PVR3_FSL_LINKS_MASK
- PVR3_NUMBER_OF_PC_BRK_MASK
- PVR3_NUMBER_OF_RD_ADDR_BRK_MASK
- PVR3_NUMBER_OF_WR_ADDR_BRK_MASK
- PVR4_ICACHE_ADDR_TAG_BITS_MASK
- PVR4_ICACHE_ALLOW_WR_MASK
- PVR4_ICACHE_ALWAYS_USED
- PVR4_ICACHE_BYTE_SIZE_MASK
- PVR4_ICACHE_INTERFACE
- PVR4_ICACHE_LINE_LEN_MASK
- PVR4_USE_ICACHE_MASK
- PVR5_DCACHE_ADDR_TAG_BITS_MASK
- PVR5_DCACHE_ALLOW_WR_MASK
- PVR5_DCACHE_ALWAYS_USED
- PVR5_DCACHE_BYTE_SIZE_MASK
- PVR5_DCACHE_INTERFACE
- PVR5_DCACHE_LINE_LEN_MASK
- PVR5_DCACHE_USE_WRITEBACK
- PVR5_USE_DCACHE_MASK
- PVR6_ICACHE_BASEADDR_MASK
- PVR7_ICACHE_HIGHADDR_MASK
- PVR8_DCACHE_BASEADDR_MASK
- PVR9_DCACHE_HIGHADDR_MASK
- PVRDMA_ACCESS_FLAGS_MAX
- PVRDMA_ACCESS_LOCAL_WRITE
- PVRDMA_ACCESS_MW_BIND
- PVRDMA_ACCESS_ON_DEMAND
- PVRDMA_ACCESS_REMOTE_ATOMIC
- PVRDMA_ACCESS_REMOTE_READ
- PVRDMA_ACCESS_REMOTE_WRITE
- PVRDMA_AH_GRH
- PVRDMA_ATOMIC_OP_COMP_SWAP
- PVRDMA_ATOMIC_OP_FETCH_ADD
- PVRDMA_ATOMIC_OP_MASK_COMP_SWAP
- PVRDMA_ATOMIC_OP_MASK_FETCH_ADD
- PVRDMA_BMME_FLAG_FAST_REG_WR
- PVRDMA_BMME_FLAG_LOCAL_INV
- PVRDMA_BMME_FLAG_REMOTE_INV
- PVRDMA_BOARD_ID
- PVRDMA_CMD_CREATE_BIND
- PVRDMA_CMD_CREATE_BIND_RESP_NOOP
- PVRDMA_CMD_CREATE_CQ
- PVRDMA_CMD_CREATE_CQ_RESP
- PVRDMA_CMD_CREATE_MR
- PVRDMA_CMD_CREATE_MR_RESP
- PVRDMA_CMD_CREATE_PD
- PVRDMA_CMD_CREATE_PD_RESP
- PVRDMA_CMD_CREATE_QP
- PVRDMA_CMD_CREATE_QP_RESP
- PVRDMA_CMD_CREATE_SRQ
- PVRDMA_CMD_CREATE_SRQ_RESP
- PVRDMA_CMD_CREATE_UC
- PVRDMA_CMD_CREATE_UC_RESP
- PVRDMA_CMD_DESTROY_BIND
- PVRDMA_CMD_DESTROY_BIND_RESP_NOOP
- PVRDMA_CMD_DESTROY_CQ
- PVRDMA_CMD_DESTROY_CQ_RESP_NOOP
- PVRDMA_CMD_DESTROY_MR
- PVRDMA_CMD_DESTROY_MR_RESP_NOOP
- PVRDMA_CMD_DESTROY_PD
- PVRDMA_CMD_DESTROY_PD_RESP_NOOP
- PVRDMA_CMD_DESTROY_QP
- PVRDMA_CMD_DESTROY_QP_RESP
- PVRDMA_CMD_DESTROY_SRQ
- PVRDMA_CMD_DESTROY_SRQ_RESP
- PVRDMA_CMD_DESTROY_UC
- PVRDMA_CMD_DESTROY_UC_RESP_NOOP
- PVRDMA_CMD_FIRST
- PVRDMA_CMD_FIRST_RESP
- PVRDMA_CMD_MAX
- PVRDMA_CMD_MAX_RESP
- PVRDMA_CMD_MODIFY_QP
- PVRDMA_CMD_MODIFY_QP_RESP
- PVRDMA_CMD_MODIFY_SRQ
- PVRDMA_CMD_MODIFY_SRQ_RESP
- PVRDMA_CMD_QUERY_PKEY
- PVRDMA_CMD_QUERY_PKEY_RESP
- PVRDMA_CMD_QUERY_PORT
- PVRDMA_CMD_QUERY_PORT_RESP
- PVRDMA_CMD_QUERY_QP
- PVRDMA_CMD_QUERY_QP_RESP
- PVRDMA_CMD_QUERY_SRQ
- PVRDMA_CMD_QUERY_SRQ_RESP
- PVRDMA_CMD_RESIZE_CQ
- PVRDMA_CMD_RESIZE_CQ_RESP
- PVRDMA_CMD_TIMEOUT
- PVRDMA_CQ_FLAG_ARMED
- PVRDMA_CQ_FLAG_ARMED_SOL
- PVRDMA_CQ_NEXT_COMP
- PVRDMA_CQ_REPORT_MISSED_EVENTS
- PVRDMA_CQ_SOLICITED
- PVRDMA_CQ_SOLICITED_MASK
- PVRDMA_DEVICE_CTL_ACTIVATE
- PVRDMA_DEVICE_CTL_RESET
- PVRDMA_DEVICE_CTL_UNQUIESCE
- PVRDMA_DEVICE_MODE_IB
- PVRDMA_DEVICE_MODE_IWARP
- PVRDMA_DEVICE_MODE_ROCE
- PVRDMA_EVENT_CLIENT_REREGISTER
- PVRDMA_EVENT_COMM_EST
- PVRDMA_EVENT_CQ_ERR
- PVRDMA_EVENT_DEVICE_FATAL
- PVRDMA_EVENT_GID_CHANGE
- PVRDMA_EVENT_LID_CHANGE
- PVRDMA_EVENT_PATH_MIG
- PVRDMA_EVENT_PATH_MIG_ERR
- PVRDMA_EVENT_PKEY_CHANGE
- PVRDMA_EVENT_PORT_ACTIVE
- PVRDMA_EVENT_PORT_ERR
- PVRDMA_EVENT_QP_ACCESS_ERR
- PVRDMA_EVENT_QP_FATAL
- PVRDMA_EVENT_QP_LAST_WQE_REACHED
- PVRDMA_EVENT_QP_REQ_ERR
- PVRDMA_EVENT_SM_CHANGE
- PVRDMA_EVENT_SQ_DRAINED
- PVRDMA_EVENT_SRQ_ERR
- PVRDMA_EVENT_SRQ_LIMIT_REACHED
- PVRDMA_GET_CAP
- PVRDMA_GID_TYPE_FLAG_ROCE_V1
- PVRDMA_GID_TYPE_FLAG_ROCE_V2
- PVRDMA_GOS_BITS_32
- PVRDMA_GOS_BITS_64
- PVRDMA_GOS_BITS_UNK
- PVRDMA_GOS_TYPE_LINUX
- PVRDMA_GOS_TYPE_UNK
- PVRDMA_INTR_CAUSE_ASYNC
- PVRDMA_INTR_CAUSE_CQ
- PVRDMA_INTR_CAUSE_RESPONSE
- PVRDMA_INTR_VECTOR_ASYNC
- PVRDMA_INTR_VECTOR_CQ
- PVRDMA_INTR_VECTOR_RESPONSE
- PVRDMA_INVALID_IDX
- PVRDMA_IS_VERSION17
- PVRDMA_IS_VERSION18
- PVRDMA_LINK_LAYER_ETHERNET
- PVRDMA_LINK_LAYER_INFINIBAND
- PVRDMA_LINK_LAYER_UNSPECIFIED
- PVRDMA_MASK
- PVRDMA_MAX_FAST_REG_PAGES
- PVRDMA_MAX_INTERRUPTS
- PVRDMA_MIG_ARMED
- PVRDMA_MIG_MIGRATED
- PVRDMA_MIG_REARM
- PVRDMA_MR_FLAG_DMA
- PVRDMA_MR_FLAG_FRMR
- PVRDMA_MTU_1024
- PVRDMA_MTU_2048
- PVRDMA_MTU_256
- PVRDMA_MTU_4096
- PVRDMA_MTU_512
- PVRDMA_MW_TYPE_1
- PVRDMA_MW_TYPE_2
- PVRDMA_NUM_RING_PAGES
- PVRDMA_PAGE_DIR_DIR
- PVRDMA_PAGE_DIR_MAX_PAGES
- PVRDMA_PAGE_DIR_PAGE
- PVRDMA_PAGE_DIR_TABLE
- PVRDMA_PCI_RESOURCE_LAST
- PVRDMA_PCI_RESOURCE_MSIX
- PVRDMA_PCI_RESOURCE_REG
- PVRDMA_PCI_RESOURCE_UAR
- PVRDMA_PDIR_SHIFT
- PVRDMA_PORT_ACTIVE
- PVRDMA_PORT_ACTIVE_DEFER
- PVRDMA_PORT_ARMED
- PVRDMA_PORT_AUTO_MIGR_SUP
- PVRDMA_PORT_BOOT_MGMT_SUP
- PVRDMA_PORT_CAP_FLAGS_MAX
- PVRDMA_PORT_CAP_MASK_NOTICE_SUP
- PVRDMA_PORT_CLIENT_REG_SUP
- PVRDMA_PORT_CM_SUP
- PVRDMA_PORT_DEVICE_MGMT_SUP
- PVRDMA_PORT_DOWN
- PVRDMA_PORT_DR_NOTICE_SUP
- PVRDMA_PORT_EXTENDED_SPEEDS_SUP
- PVRDMA_PORT_INIT
- PVRDMA_PORT_IP_BASED_GIDS
- PVRDMA_PORT_LED_INFO_SUP
- PVRDMA_PORT_LINK_LATENCY_SUP
- PVRDMA_PORT_MKEY_NVRAM
- PVRDMA_PORT_NOP
- PVRDMA_PORT_NOTICE_SUP
- PVRDMA_PORT_OPT_IPD_SUP
- PVRDMA_PORT_PKEY_NVRAM
- PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP
- PVRDMA_PORT_REINIT_SUP
- PVRDMA_PORT_SL_MAP_SUP
- PVRDMA_PORT_SM
- PVRDMA_PORT_SM_DISABLED
- PVRDMA_PORT_SNMP_TUNNEL_SUP
- PVRDMA_PORT_SYS_IMAGE_GUID_SUP
- PVRDMA_PORT_TRAP_SUP
- PVRDMA_PORT_VENDOR_CLASS_SUP
- PVRDMA_PPN64_VERSION
- PVRDMA_PTABLE_SHIFT
- PVRDMA_QPS_ERR
- PVRDMA_QPS_INIT
- PVRDMA_QPS_RESET
- PVRDMA_QPS_RTR
- PVRDMA_QPS_RTS
- PVRDMA_QPS_SQD
- PVRDMA_QPS_SQE
- PVRDMA_QPT_GSI
- PVRDMA_QPT_MAX
- PVRDMA_QPT_RAW_ETHERTYPE
- PVRDMA_QPT_RAW_IPV6
- PVRDMA_QPT_RAW_PACKET
- PVRDMA_QPT_RC
- PVRDMA_QPT_SMI
- PVRDMA_QPT_UC
- PVRDMA_QPT_UD
- PVRDMA_QPT_XRC_INI
- PVRDMA_QPT_XRC_TGT
- PVRDMA_QP_ACCESS_FLAGS
- PVRDMA_QP_ALT_PATH
- PVRDMA_QP_ATTR_MASK_MAX
- PVRDMA_QP_AV
- PVRDMA_QP_CAP
- PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
- PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO
- PVRDMA_QP_CUR_STATE
- PVRDMA_QP_DEST_QPN
- PVRDMA_QP_EN_SQD_ASYNC_NOTIFY
- PVRDMA_QP_MAX_DEST_RD_ATOMIC
- PVRDMA_QP_MAX_QP_RD_ATOMIC
- PVRDMA_QP_MIN_RNR_TIMER
- PVRDMA_QP_NUM_HEADER_PAGES
- PVRDMA_QP_PATH_MIG_STATE
- PVRDMA_QP_PATH_MTU
- PVRDMA_QP_PKEY_INDEX
- PVRDMA_QP_PORT
- PVRDMA_QP_QKEY
- PVRDMA_QP_RETRY_CNT
- PVRDMA_QP_RNR_RETRY
- PVRDMA_QP_RQ_PSN
- PVRDMA_QP_SQ_PSN
- PVRDMA_QP_STATE
- PVRDMA_QP_TIMEOUT
- PVRDMA_RATE_100_GBPS
- PVRDMA_RATE_10_GBPS
- PVRDMA_RATE_112_GBPS
- PVRDMA_RATE_120_GBPS
- PVRDMA_RATE_14_GBPS
- PVRDMA_RATE_168_GBPS
- PVRDMA_RATE_200_GBPS
- PVRDMA_RATE_20_GBPS
- PVRDMA_RATE_25_GBPS
- PVRDMA_RATE_2_5_GBPS
- PVRDMA_RATE_300_GBPS
- PVRDMA_RATE_30_GBPS
- PVRDMA_RATE_40_GBPS
- PVRDMA_RATE_56_GBPS
- PVRDMA_RATE_5_GBPS
- PVRDMA_RATE_60_GBPS
- PVRDMA_RATE_80_GBPS
- PVRDMA_RATE_PORT_CURRENT
- PVRDMA_REG_CTL
- PVRDMA_REG_DSRHIGH
- PVRDMA_REG_DSRLOW
- PVRDMA_REG_ERR
- PVRDMA_REG_ICR
- PVRDMA_REG_IMR
- PVRDMA_REG_MACH
- PVRDMA_REG_MACL
- PVRDMA_REG_REQUEST
- PVRDMA_REG_VERSION
- PVRDMA_REV_ID
- PVRDMA_ROCEV1_VERSION
- PVRDMA_ROCEV2_VERSION
- PVRDMA_SEND_FENCE
- PVRDMA_SEND_FLAGS_MAX
- PVRDMA_SEND_INLINE
- PVRDMA_SEND_IP_CSUM
- PVRDMA_SEND_SIGNALED
- PVRDMA_SEND_SOLICITED
- PVRDMA_SIGNAL_ALL_WR
- PVRDMA_SIGNAL_REQ_WR
- PVRDMA_SPEED_DDR
- PVRDMA_SPEED_EDR
- PVRDMA_SPEED_FDR
- PVRDMA_SPEED_FDR10
- PVRDMA_SPEED_QDR
- PVRDMA_SPEED_SDR
- PVRDMA_SUPPORTED
- PVRDMA_UAR_CQ_ARM
- PVRDMA_UAR_CQ_ARM_SOL
- PVRDMA_UAR_CQ_OFFSET
- PVRDMA_UAR_CQ_POLL
- PVRDMA_UAR_HANDLE_MASK
- PVRDMA_UAR_QP_OFFSET
- PVRDMA_UAR_QP_RECV
- PVRDMA_UAR_QP_SEND
- PVRDMA_UAR_SRQ_OFFSET
- PVRDMA_UAR_SRQ_RECV
- PVRDMA_UVERBS_ABI_VERSION
- PVRDMA_VERSION
- PVRDMA_WC_BAD_RESP_ERR
- PVRDMA_WC_BIND_MW
- PVRDMA_WC_COMP_SWAP
- PVRDMA_WC_FAST_REG_MR
- PVRDMA_WC_FATAL_ERR
- PVRDMA_WC_FETCH_ADD
- PVRDMA_WC_FLAGS_MAX
- PVRDMA_WC_GENERAL_ERR
- PVRDMA_WC_GRH
- PVRDMA_WC_INV_EECN_ERR
- PVRDMA_WC_INV_EEC_STATE_ERR
- PVRDMA_WC_IP_CSUM_OK
- PVRDMA_WC_LOCAL_INV
- PVRDMA_WC_LOC_ACCESS_ERR
- PVRDMA_WC_LOC_EEC_OP_ERR
- PVRDMA_WC_LOC_LEN_ERR
- PVRDMA_WC_LOC_PROT_ERR
- PVRDMA_WC_LOC_QP_OP_ERR
- PVRDMA_WC_LOC_RDD_VIOL_ERR
- PVRDMA_WC_LSO
- PVRDMA_WC_MASKED_COMP_SWAP
- PVRDMA_WC_MASKED_FETCH_ADD
- PVRDMA_WC_MW_BIND_ERR
- PVRDMA_WC_RDMA_READ
- PVRDMA_WC_RDMA_WRITE
- PVRDMA_WC_RECV
- PVRDMA_WC_RECV_RDMA_WITH_IMM
- PVRDMA_WC_REM_ABORT_ERR
- PVRDMA_WC_REM_ACCESS_ERR
- PVRDMA_WC_REM_INV_RD_REQ_ERR
- PVRDMA_WC_REM_INV_REQ_ERR
- PVRDMA_WC_REM_OP_ERR
- PVRDMA_WC_RESP_TIMEOUT_ERR
- PVRDMA_WC_RETRY_EXC_ERR
- PVRDMA_WC_RNR_RETRY_EXC_ERR
- PVRDMA_WC_SEND
- PVRDMA_WC_SUCCESS
- PVRDMA_WC_WITH_IMM
- PVRDMA_WC_WITH_INVALIDATE
- PVRDMA_WC_WITH_NETWORK_HDR_TYPE
- PVRDMA_WC_WITH_SMAC
- PVRDMA_WC_WITH_VLAN
- PVRDMA_WC_WR_FLUSH_ERR
- PVRDMA_WIDTH_12X
- PVRDMA_WIDTH_1X
- PVRDMA_WIDTH_4X
- PVRDMA_WIDTH_8X
- PVRDMA_WR_ATOMIC_CMP_AND_SWP
- PVRDMA_WR_ATOMIC_FETCH_AND_ADD
- PVRDMA_WR_BIND_MW
- PVRDMA_WR_ERROR
- PVRDMA_WR_FAST_REG_MR
- PVRDMA_WR_LOCAL_INV
- PVRDMA_WR_LSO
- PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP
- PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD
- PVRDMA_WR_RDMA_READ
- PVRDMA_WR_RDMA_READ_WITH_INV
- PVRDMA_WR_RDMA_WRITE
- PVRDMA_WR_RDMA_WRITE_WITH_IMM
- PVRDMA_WR_REG_SIG_MR
- PVRDMA_WR_SEND
- PVRDMA_WR_SEND_WITH_IMM
- PVRDMA_WR_SEND_WITH_INV
- PVRDMA_ZERO_BASED
- PVR_403GA
- PVR_403GB
- PVR_403GC
- PVR_403GCX
- PVR_405GP
- PVR_476
- PVR_476FPE
- PVR_476_ISS
- PVR_601
- PVR_602
- PVR_603
- PVR_603e
- PVR_603ev
- PVR_603r
- PVR_604
- PVR_604e
- PVR_604r
- PVR_620
- PVR_630
- PVR_630p
- PVR_740
- PVR_7400
- PVR_740P
- PVR_7410
- PVR_7450
- PVR_750
- PVR_750P
- PVR_8240
- PVR_8245
- PVR_8260
- PVR_8540
- PVR_8560
- PVR_8xx
- PVR_970
- PVR_970FX
- PVR_970GX
- PVR_970MP
- PVR_ARCH_204
- PVR_ARCH_205
- PVR_ARCH_206
- PVR_ARCH_206p
- PVR_ARCH_207
- PVR_ARCH_300
- PVR_AREA_OPTIMISED
- PVR_AUTOCTS
- PVR_BE
- PVR_CFG
- PVR_CORE
- PVR_DCACHE_ADDR_TAG_BITS
- PVR_DCACHE_ALLOW_WR
- PVR_DCACHE_BASEADDR
- PVR_DCACHE_BYTE_SIZE
- PVR_DCACHE_HIGHADDR
- PVR_DCACHE_LINE_LEN
- PVR_DCACHE_USE_FSL
- PVR_DCACHE_USE_WRITEBACK
- PVR_DEBUG_ENABLED
- PVR_DIV_ZERO_EXCEPTION
- PVR_DOPB_BUS_EXCEPTION
- PVR_DSR
- PVR_DTR
- PVR_D_LMB
- PVR_D_OPB
- PVR_EDGE_IS_POSITIVE
- PVR_ENDIAN
- PVR_FAM
- PVR_FORMAT_PIX
- PVR_FORMAT_VBI
- PVR_FPU_EXCEPTION
- PVR_FSL_EXCEPTION
- PVR_FSL_LINKS
- PVR_GPIO_DELAY
- PVR_ICACHE_ADDR_TAG_BITS
- PVR_ICACHE_ALLOW_WR
- PVR_ICACHE_BASEADDR
- PVR_ICACHE_BYTE_SIZE
- PVR_ICACHE_HIGHADDR
- PVR_ICACHE_LINE_LEN
- PVR_ICACHE_USE_FSL
- PVR_ICESTAR
- PVR_ILL_OPCODE_EXCEPTION
- PVR_INTERRUPT_IS_EDGE
- PVR_IOPB_BUS_EXCEPTION
- PVR_IS_FULL
- PVR_I_LMB
- PVR_I_OPB
- PVR_MAJ
- PVR_MEM
- PVR_MIN
- PVR_MMU_DTLB_SIZE
- PVR_MMU_ITLB_SIZE
- PVR_MMU_PRIVINS
- PVR_MMU_TLB_ACCESS
- PVR_MMU_ZONES
- PVR_MSR_BIT
- PVR_MSR_RESET_VALUE
- PVR_NORTHSTAR
- PVR_NP405H
- PVR_NP405L
- PVR_NUM
- PVR_NUMBER_OF_PC_BRK
- PVR_NUMBER_OF_RD_ADDR_BRK
- PVR_NUMBER_OF_WR_ADDR_BRK
- PVR_OPCODE_0x0_ILLEGAL
- PVR_PA6T
- PVR_POWER4
- PVR_POWER4p
- PVR_POWER5
- PVR_POWER5p
- PVR_POWER6
- PVR_POWER7
- PVR_POWER7p
- PVR_POWER8
- PVR_POWER8E
- PVR_POWER8NVL
- PVR_POWER9
- PVR_POWER9_CUMULUS
- PVR_PULSAR
- PVR_REV
- PVR_RI
- PVR_RS232
- PVR_RS422
- PVR_SSTAR
- PVR_STB03XXX
- PVR_TARGET_FAMILY
- PVR_UNALIGNED_EXCEPTION
- PVR_USER1
- PVR_USER2
- PVR_USE_BARREL
- PVR_USE_DCACHE
- PVR_USE_DIV
- PVR_USE_FPU
- PVR_USE_FPU2
- PVR_USE_HW_MUL
- PVR_USE_ICACHE
- PVR_USE_MMU
- PVR_USE_MSR_INSTR
- PVR_USE_MUL64
- PVR_USE_PCMP_INSTR
- PVR_V35
- PVR_VER
- PVR_VERSION
- PVR_VER_832x
- PVR_VER_836x
- PVR_VER_E500MC
- PVR_VER_E500V1
- PVR_VER_E500V2
- PVR_VER_E5500
- PVR_VER_E6500
- PVSCSICmdDescAbortCmd
- PVSCSICmdDescConfigCmd
- PVSCSICmdDescResetDevice
- PVSCSICmdDescSetupMsgRing
- PVSCSICmdDescSetupReqCall
- PVSCSICmdDescSetupRings
- PVSCSICommands
- PVSCSIConfigPageAddressType
- PVSCSIConfigPageController
- PVSCSIConfigPageHeader
- PVSCSIConfigPageType
- PVSCSIMemSpace
- PVSCSIMsgDescDevStatusChanged
- PVSCSIMsgType
- PVSCSIRegOffset
- PVSCSIRingCmpDesc
- PVSCSIRingMsgDesc
- PVSCSIRingReqDesc
- PVSCSIRingsState
- PVSCSISGElement
- PVSCSI_CMD_ABORT_CMD
- PVSCSI_CMD_ADAPTER_RESET
- PVSCSI_CMD_CONFIG
- PVSCSI_CMD_DEVICE_UNPLUG
- PVSCSI_CMD_FIRST
- PVSCSI_CMD_ISSUE_SCSI
- PVSCSI_CMD_LAST
- PVSCSI_CMD_RESET_BUS
- PVSCSI_CMD_RESET_DEVICE
- PVSCSI_CMD_SETUP_MSG_RING
- PVSCSI_CMD_SETUP_REQCALLTHRESHOLD
- PVSCSI_CMD_SETUP_RINGS
- PVSCSI_CONFIG_BUSTARGET_ADDRESS
- PVSCSI_CONFIG_CONTROLLER_ADDRESS
- PVSCSI_CONFIG_PAGE_CONTROLLER
- PVSCSI_CONFIG_PAGE_DEVICE
- PVSCSI_CONFIG_PAGE_PHY
- PVSCSI_CONFIG_PHY_ADDRESS
- PVSCSI_DEFAULT_NUM_PAGES_MSG_RING
- PVSCSI_DEFAULT_NUM_PAGES_PER_RING
- PVSCSI_DEFAULT_QUEUE_DEPTH
- PVSCSI_DRIVER_VERSION_STRING
- PVSCSI_FLAG_CMD_DIR_NONE
- PVSCSI_FLAG_CMD_DIR_TODEVICE
- PVSCSI_FLAG_CMD_DIR_TOHOST
- PVSCSI_FLAG_CMD_OUT_OF_BAND_CDB
- PVSCSI_FLAG_CMD_WITH_SG_LIST
- PVSCSI_INTR_ALL_SUPPORTED
- PVSCSI_INTR_CMPL_0
- PVSCSI_INTR_CMPL_1
- PVSCSI_INTR_CMPL_MASK
- PVSCSI_INTR_MSG_0
- PVSCSI_INTR_MSG_1
- PVSCSI_INTR_MSG_MASK
- PVSCSI_LINUX_DRIVER_DESC
- PVSCSI_MAX_INTRS
- PVSCSI_MAX_NUM_PAGES_CMP_RING
- PVSCSI_MAX_NUM_PAGES_MSG_RING
- PVSCSI_MAX_NUM_PAGES_REQ_RING
- PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE
- PVSCSI_MAX_NUM_SG_ENTRIES_PER_SEGMENT
- PVSCSI_MAX_REQ_QUEUE_DEPTH
- PVSCSI_MEM_SPACE_COMMAND_NUM_PAGES
- PVSCSI_MEM_SPACE_COMMAND_PAGE
- PVSCSI_MEM_SPACE_INTR_STATUS_NUM_PAGES
- PVSCSI_MEM_SPACE_INTR_STATUS_PAGE
- PVSCSI_MEM_SPACE_KICK_IO_NUM_PAGES
- PVSCSI_MEM_SPACE_KICK_IO_PAGE
- PVSCSI_MEM_SPACE_MISC_NUM_PAGES
- PVSCSI_MEM_SPACE_MISC_PAGE
- PVSCSI_MEM_SPACE_MSIX_NUM_PAGES
- PVSCSI_MEM_SPACE_MSIX_PBA_PAGE
- PVSCSI_MEM_SPACE_MSIX_TABLE_PAGE
- PVSCSI_MEM_SPACE_NUM_PAGES
- PVSCSI_MEM_SPACE_SIZE
- PVSCSI_MSG_DEV_ADDED
- PVSCSI_MSG_DEV_REMOVED
- PVSCSI_MSG_LAST
- PVSCSI_REG_OFFSET_COMMAND
- PVSCSI_REG_OFFSET_COMMAND_DATA
- PVSCSI_REG_OFFSET_COMMAND_STATUS
- PVSCSI_REG_OFFSET_DEBUG
- PVSCSI_REG_OFFSET_INTR_MASK
- PVSCSI_REG_OFFSET_INTR_STATUS
- PVSCSI_REG_OFFSET_KICK_NON_RW_IO
- PVSCSI_REG_OFFSET_KICK_RW_IO
- PVSCSI_REG_OFFSET_LAST_STS_0
- PVSCSI_REG_OFFSET_LAST_STS_1
- PVSCSI_REG_OFFSET_LAST_STS_2
- PVSCSI_REG_OFFSET_LAST_STS_3
- PVSCSI_RW
- PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES
- PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
- PVSync
- PVTCTLEN
- PVTCTLEN_EN
- PVTCTLMODE
- PVTCTLMODE_MASK
- PVTCTLMODE_TEMPMON
- PVTCTLSEL
- PVTCTLSEL_MASK
- PVTCTLSEL_MONITOR
- PVTI_SIZE
- PVTMON_CONTROL0
- PVTMON_CONTROL0_SEL_MASK
- PVTMON_CONTROL0_SEL_TEMP_MONITOR
- PVTMON_CONTROL0_SEL_TEST_MODE
- PVTMON_STATUS
- PV_AV_MASK
- PV_AV_SHIFT
- PV_CALLEE_SAVE
- PV_CALLEE_SAVE_REGS_THUNK
- PV_CONTROL
- PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI
- PV_CONTROL_CLK_SELECT_DSI
- PV_CONTROL_CLK_SELECT_MASK
- PV_CONTROL_CLK_SELECT_SHIFT
- PV_CONTROL_CLK_SELECT_VEC
- PV_CONTROL_CLR_AT_START
- PV_CONTROL_EN
- PV_CONTROL_FIFO_CLR
- PV_CONTROL_FIFO_LEVEL_MASK
- PV_CONTROL_FIFO_LEVEL_SHIFT
- PV_CONTROL_FORMAT_24
- PV_CONTROL_FORMAT_DSIC_16
- PV_CONTROL_FORMAT_DSIV_16
- PV_CONTROL_FORMAT_DSIV_18
- PV_CONTROL_FORMAT_DSIV_24
- PV_CONTROL_FORMAT_MASK
- PV_CONTROL_FORMAT_SHIFT
- PV_CONTROL_PIXEL_REP_MASK
- PV_CONTROL_PIXEL_REP_SHIFT
- PV_CONTROL_TRIGGER_UNDERFLOW
- PV_CONTROL_WAIT_HSTART
- PV_EXTRA_CLOBBERS
- PV_FLAGS_ARG
- PV_HACT_ACT
- PV_HE_MIN
- PV_HE_PER_LINE
- PV_HORZA
- PV_HORZA_HBP_MASK
- PV_HORZA_HBP_SHIFT
- PV_HORZA_HSYNC_MASK
- PV_HORZA_HSYNC_SHIFT
- PV_HORZB
- PV_HORZB_HACTIVE_MASK
- PV_HORZB_HACTIVE_SHIFT
- PV_HORZB_HFP_MASK
- PV_HORZB_HFP_SHIFT
- PV_INTEN
- PV_INTSTAT
- PV_INT_HACT_START
- PV_INT_HBP_START
- PV_INT_HFP_START
- PV_INT_HSYNC_START
- PV_INT_VACT_START
- PV_INT_VBP_START
- PV_INT_VFP_END
- PV_INT_VFP_START
- PV_INT_VID_IDLE
- PV_INT_VSYNC_START
- PV_PLAYTV_USB_PRO_PAL_FM
- PV_PREV_CHECK_MASK
- PV_PT_MASK
- PV_PT_SHIFT
- PV_PV_MASK
- PV_RESTORE_ALL_CALLER_REGS
- PV_RESTORE_REGS
- PV_SAVE_ALL_CALLER_REGS
- PV_SAVE_REGS
- PV_STAT
- PV_THUNK_NAME
- PV_UNLOCK
- PV_UNLOCK_SLOWPATH
- PV_VCONTROL_COMMAND
- PV_VCONTROL_CONTINUOUS
- PV_VCONTROL_DSI
- PV_VCONTROL_INTERLACE
- PV_VCONTROL_ODD_DELAY_MASK
- PV_VCONTROL_ODD_DELAY_SHIFT
- PV_VCONTROL_ODD_FIRST
- PV_VCONTROL_VIDEN
- PV_VERTA
- PV_VERTA_EVEN
- PV_VERTA_VBP_MASK
- PV_VERTA_VBP_SHIFT
- PV_VERTA_VSYNC_MASK
- PV_VERTA_VSYNC_SHIFT
- PV_VERTB
- PV_VERTB_EVEN
- PV_VERTB_VACTIVE_MASK
- PV_VERTB_VACTIVE_SHIFT
- PV_VERTB_VFP_MASK
- PV_VERTB_VFP_SHIFT
- PV_VEXTRA_CLOBBERS
- PV_VSYNCD_EVEN
- PV_V_CONTROL
- PW
- PW0
- PW0_ENABLE
- PW1
- PW1_ENABLE
- PW2
- PW20_WAIT_IDLE_BIT
- PW2_ENABLE
- PW3
- PW3_ENABLE
- PW4_ENABLE
- PWARN
- PWCFG_LEGACY_WOLEN
- PWCFG_LEGACY_WOLSR
- PWCFG_LEGCY_WOL
- PWCFG_PCISTICK
- PWCFG_PHYPWOPT
- PWCFG_PMCSR_PME_EN
- PWCFG_PMCSR_PME_SR
- PWCFG_WOLTYPE
- PWCTRL1
- PWC_CDR
- PWC_CDR_DEFAULT
- PWC_CID_CUSTOM
- PWC_DEBUG
- PWC_DEBUG_FLOW
- PWC_DEBUG_IOCTL
- PWC_DEBUG_LEVEL
- PWC_DEBUG_LEVEL_FLOW
- PWC_DEBUG_LEVEL_IOCTL
- PWC_DEBUG_LEVEL_MEMORY
- PWC_DEBUG_LEVEL_MODULE
- PWC_DEBUG_LEVEL_OPEN
- PWC_DEBUG_LEVEL_PROBE
- PWC_DEBUG_LEVEL_READ
- PWC_DEBUG_LEVEL_SIZE
- PWC_DEBUG_LEVEL_TRACE
- PWC_DEBUG_MEMORY
- PWC_DEBUG_MODULE
- PWC_DEBUG_OPEN
- PWC_DEBUG_PROBE
- PWC_DEBUG_READ
- PWC_DEBUG_SIZE
- PWC_DEBUG_TRACE
- PWC_DEC1_H
- PWC_DEC23_H
- PWC_DV2LDR
- PWC_DV2LDR_SHT
- PWC_ERROR
- PWC_EV12V
- PWC_EV25V
- PWC_FLAG
- PWC_FPS_MAX_KIARA
- PWC_FPS_MAX_NALA
- PWC_FPS_MAX_TIMON
- PWC_FRAME_SIZE
- PWC_H
- PWC_INFO
- PWC_KIARA_H
- PWC_NAME
- PWC_STATUS
- PWC_TIMON_H
- PWC_TRACE
- PWC_VERSION
- PWC_WARNING
- PWDB_IN_RANGE
- PWDCR
- PWDCR_DIS_XRX
- PWDCR_EN_XRX
- PWDSET
- PWDSET_OFDMPD_DOWN
- PWDSET_OFDMPD_MASK
- PWDSET_PSKPD_DOWN
- PWDSET_PSKPD_MASK
- PWDSR
- PWDSR_XRX
- PWD_EN_BIT
- PWD_SUSPEND_EN
- PWD_SUSPND_EN
- PWEN
- PWEN_MARK
- PWER
- PWER_GPIO
- PWER_GPIO0
- PWER_GPIO1
- PWER_GPIO10
- PWER_GPIO11
- PWER_GPIO12
- PWER_GPIO13
- PWER_GPIO14
- PWER_GPIO15
- PWER_GPIO16
- PWER_GPIO17
- PWER_GPIO18
- PWER_GPIO19
- PWER_GPIO2
- PWER_GPIO20
- PWER_GPIO21
- PWER_GPIO22
- PWER_GPIO23
- PWER_GPIO24
- PWER_GPIO25
- PWER_GPIO26
- PWER_GPIO27
- PWER_GPIO3
- PWER_GPIO4
- PWER_GPIO5
- PWER_GPIO6
- PWER_GPIO7
- PWER_GPIO8
- PWER_GPIO9
- PWER_RTC
- PWER_WE35
- PWER_WEMUX2_GPIO36
- PWER_WEMUX2_GPIO38
- PWER_WEMUX2_GPIO40
- PWER_WEMUX2_GPIO53
- PWER_WEMUX2_MASK
- PWER_WEMUX3_GPIO113
- PWER_WEMUX3_GPIO31
- PWER_WEMUX3_MASK
- PWIDX_ADC
- PWIDX_CLFE
- PWIDX_FRONT
- PWIDX_MIC
- PWIDX_SIZE
- PWIDX_SURR
- PWL
- PWLAN_PWR_CFG
- PWM
- PWM0
- PWM0CLKDIV0
- PWM0CLKDIV1
- PWM0DIV
- PWM0DUTY
- PWM0DUTYCYCLE
- PWM0PER
- PWM0_AND_SSP0_CS1_REG0_MASK
- PWM0_A_MARK
- PWM0_B_MARK
- PWM0_CLK_DIV
- PWM0_CLK_ENABLE
- PWM0_C_MARK
- PWM0_DUTY_CYCLE
- PWM0_D_MARK
- PWM0_ENABLE
- PWM0_MARK
- PWM1
- PWM1A_MARK
- PWM1B_MARK
- PWM1C_MARK
- PWM1DIV
- PWM1DUTY
- PWM1D_MARK
- PWM1E_MARK
- PWM1F_MARK
- PWM1G_MARK
- PWM1H_MARK
- PWM1PER
- PWM1_AND_KBD_COL5_REG0_MASK
- PWM1_A_MARK
- PWM1_B_MARK
- PWM1_C_MARK
- PWM1_D_MARK
- PWM1_GATING_DIS
- PWM1_IRQ_NUM
- PWM1_MARK
- PWM2
- PWM2A_MARK
- PWM2B_MARK
- PWM2C_MARK
- PWM2D_MARK
- PWM2E_MARK
- PWM2F_MARK
- PWM2G_MARK
- PWM2H_MARK
- PWM2_AND_GPT0_TMR0_CPT_REG0_MASK
- PWM2_A_MARK
- PWM2_B_MARK
- PWM2_C_MARK
- PWM2_D_MARK
- PWM2_GATING_DIS
- PWM2_IRQ_NUM
- PWM2_MARK
- PWM3
- PWM3_AND_GPT0_TMR1_CLK_REG0_MASK
- PWM3_A_MARK
- PWM3_B_MARK
- PWM3_C_MARK
- PWM3_MARK
- PWM4
- PWM45DWIDTH_FIXUP
- PWM45THRES_FIXUP
- PWM4_A_MARK
- PWM4_B_MARK
- PWM4_C_MARK
- PWM4_MARK
- PWM5_A_MARK
- PWM5_B_MARK
- PWM5_C_MARK
- PWM5_D_MARK
- PWM5_MARK
- PWM6_A_MARK
- PWM6_B_MARK
- PWM6_C_MARK
- PWM6_MARK
- PWMA
- PWMB
- PWMC
- PWMCFG
- PWMCH_OFFSET
- PWMCLK_PRESCALE_HIGH
- PWMCLK_PRESCALE_LOW
- PWMCNT
- PWMCNT_ADDR
- PWMCON
- PWMCR
- PWMCR_MAX_PRESCALE
- PWMCR_MIN_PRESCALE
- PWMCR_PRESCALE_SHIFT
- PWMCR_PWM_ENABLE
- PWMCR_SD
- PWMCS_EN_PWM0
- PWMCS_EN_PWM1
- PWMCS_EN_PWM2
- PWMC_ADDR
- PWMC_CLKSEL_MASK
- PWMC_CLKSEL_SHIFT
- PWMC_CLKSRC
- PWMC_EN
- PWMC_IRQ
- PWMC_IRQEN
- PWMC_LOAD
- PWMC_PIN
- PWMC_PRESCALER_MASK
- PWMC_PRESCALER_SHIFT
- PWMC_PWMEN
- PWMC_REPEAT_MASK
- PWMC_REPEAT_SHIFT
- PWMD
- PWMDCR
- PWMDCR_FD
- PWMDCR_MAX_DUTY
- PWMDCR_MIN_DUTY
- PWMDWIDTH
- PWME
- PWMF
- PWMFSW0_B_MARK
- PWMFSW0_C_MARK
- PWMFSW0_D_MARK
- PWMFSW0_E_MARK
- PWMFSW0_MARK
- PWMF_EXPORTED
- PWMF_REQUESTED
- PWMG
- PWMGDUR
- PWMH
- PWMHDUR
- PWMLDUR
- PWMMCR
- PWMMCR_PWM_ENABLE
- PWMO
- PWMOFF
- PWMP
- PWMPCR
- PWMPCR_MAX_PERIOD
- PWMPCR_MIN_PERIOD
- PWMP_ADDR
- PWMR
- PWMRST
- PWMR_ADDR
- PWMR_CCPEN
- PWMR_CC_EN
- PWMR_CLS
- PWMR_LDMSK
- PWMR_PW
- PWMR_PW_MASK
- PWMR_PW_SHIFT
- PWMR_SCR0
- PWMR_SCR1
- PWMR_SRC_LCD
- PWMR_SRC_LINE
- PWMR_SRC_MASK
- PWMR_SRC_PIXEL
- PWMS
- PWMS_ADDR
- PWMT1
- PWMT2
- PWMTHRES
- PWMU0_MARK
- PWMU1_MARK
- PWMU2_MARK
- PWMU3_MARK
- PWMU4_MARK
- PWMU5_MARK
- PWMV1_CDTY
- PWMV1_CPRD
- PWMV1_CUPD
- PWMV2_CDTY
- PWMV2_CDTYUPD
- PWMV2_CPRD
- PWMV2_CPRDUPD
- PWMW
- PWMWAVENUM
- PWMW_ADDR
- PWMX0_MARK
- PWMX1_MARK
- PWMX2_MARK
- PWMX3_MARK
- PWMX4_MARK
- PWMX5_MARK
- PWMX6_MARK
- PWMX7_MARK
- PWM_ACTIVE0
- PWM_ACT_STATE
- PWM_ACZ_FROM_REG
- PWM_ACZ_TO_REG
- PWM_ADDRESS
- PWM_BASED
- PWM_BASE_CLK
- PWM_BASE_UNIT_SHIFT
- PWM_BLINK_OFF_DURATION_OFF
- PWM_BLINK_ON_DURATION_OFF
- PWM_BYPASS
- PWM_CFG0_ADDR
- PWM_CFG1_ADDR
- PWM_CFG2_ADDR
- PWM_CH_CFG
- PWM_CH_CFG_DUTY_SHIFT
- PWM_CH_CFG_TMBASE_SHIFT
- PWM_CH_PRD
- PWM_CH_PRD_BASE
- PWM_CH_PRD_OFFSET
- PWM_CH_REG_OFFSET
- PWM_CH_REG_SIZE
- PWM_CH_SIZE
- PWM_CLKDIV_MASK
- PWM_CLKDIV_MAX
- PWM_CLKDIV_SHIFT
- PWM_CLK_DIV_MAX
- PWM_CLK_GATING
- PWM_CMR
- PWM_CMR_CPOL
- PWM_CMR_CPRE_MSK
- PWM_CMR_UPD_CDTY
- PWM_CNT
- PWM_CONFIG
- PWM_CONFIG_REG
- PWM_CONTINUOUS
- PWM_CONTROL
- PWM_CONTROL_LOGIC
- PWM_CONTROL_MASK
- PWM_CONTROL_OFFSET
- PWM_CONTROL_POLARITY_SHIFT
- PWM_CONTROL_SHIFT
- PWM_CONTROL_SMOOTH_SHIFT
- PWM_CONTROL_TRIGGER_SHIFT
- PWM_CONTROL_TYPE_SHIFT
- PWM_CPT_EDGE
- PWM_CPT_EDGE_MASK
- PWM_CPT_EN
- PWM_CPT_INT_EN
- PWM_CPT_INT_STAT
- PWM_CPT_VAL
- PWM_CTRL
- PWM_CTRL2
- PWM_CTRL_ADDR
- PWM_CTRL_CFG
- PWM_CTRL_CFG_DIV_MASK
- PWM_CTRL_CFG_DIV_SHIFT
- PWM_CTRL_CFG_NO_SUB_DIV
- PWM_CTRL_CFG_SUB_DIV0
- PWM_CTRL_CFG_SUB_DIV0_DIV1
- PWM_CTRL_CFG_SUB_DIV1
- PWM_CTRL_OUTPUT_EN
- PWM_CTRL_REG
- PWM_CTRL_TIMER_EN
- PWM_CWORD_LSB
- PWM_CWORD_MSB
- PWM_DEFAULT_PERIOD
- PWM_DIS
- PWM_DISABLE_ADDR
- PWM_DISABLE_DATA
- PWM_DIV_CLK_0
- PWM_DIV_CLK_100
- PWM_DIV_CLK_128
- PWM_DTY_MASK
- PWM_DUTY
- PWM_DUTY_MASK
- PWM_DUTY_NEGATIVE
- PWM_DUTY_POSITIVE
- PWM_DUTY_SHIFT
- PWM_DUTY_WIDTH
- PWM_EN
- PWM_ENA
- PWM_ENABLE
- PWM_ENABLE_ADDR
- PWM_ENABLE_CTLEN
- PWM_ENABLE_DATA
- PWM_ENABLE_MASK
- PWM_ENABLE_MODE_MASK
- PWM_ENABLE_SHIFT
- PWM_END
- PWM_EN_FROM_REG
- PWM_EN_TO_REG
- PWM_FREQ
- PWM_FREQUENCY
- PWM_FREQ_FROM_REG
- PWM_FREQ_TO_REG
- PWM_FROM_CNT
- PWM_FROM_REG
- PWM_GOTOSTART
- PWM_GPIO
- PWM_HIGH_MASK
- PWM_HIGH_WIDTH_MASK
- PWM_HIGH_WIDTH_SHIFT
- PWM_HRC
- PWM_IMX_TPM_CNT
- PWM_IMX_TPM_CnSC
- PWM_IMX_TPM_CnSC_CHF
- PWM_IMX_TPM_CnSC_ELS
- PWM_IMX_TPM_CnSC_ELS_INVERSED
- PWM_IMX_TPM_CnSC_ELS_NORMAL
- PWM_IMX_TPM_CnSC_MSA
- PWM_IMX_TPM_CnSC_MSB
- PWM_IMX_TPM_CnV
- PWM_IMX_TPM_GLOBAL
- PWM_IMX_TPM_MOD
- PWM_IMX_TPM_MOD_MOD
- PWM_IMX_TPM_MOD_WIDTH
- PWM_IMX_TPM_PARAM
- PWM_IMX_TPM_PARAM_CHAN
- PWM_IMX_TPM_SC
- PWM_IMX_TPM_SC_CMOD
- PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK
- PWM_IMX_TPM_SC_CPWMS
- PWM_IMX_TPM_SC_PS
- PWM_INACTIVE_NEGATIVE
- PWM_INACTIVE_POSITIVE
- PWM_INT_ACK
- PWM_INT_ACK_MASK
- PWM_IRQ_NUM
- PWM_ISR
- PWM_KEEP_MASK
- PWM_KEEP_SHIFT
- PWM_LEGACY_MODE
- PWM_LOCK_EN
- PWM_LOGIC_ENABLE
- PWM_LOOKUP
- PWM_LOOKUP_WITH_MODULE
- PWM_LOOP
- PWM_LOW_MASK
- PWM_LP_DISABLE
- PWM_LRC
- PWM_LUMINANCE_SCALE
- PWM_MAX
- PWM_MAX_LEVEL
- PWM_MAX_PERIOD_NS
- PWM_MAX_REG
- PWM_MIN_FROM_REG
- PWM_MIN_REG
- PWM_MIN_TO_REG
- PWM_MODE
- PWM_MODE_AUTO
- PWM_MODE_MANUAL
- PWM_MODE_MSK
- PWM_MODE_OFF
- PWM_MODE_ON
- PWM_NONSTOP
- PWM_OE
- PWM_OFF_FROM_REG
- PWM_OFF_TO_REG
- PWM_OMAP_DMTIMER_INT_CAPTURE
- PWM_OMAP_DMTIMER_INT_MATCH
- PWM_OMAP_DMTIMER_INT_OVERFLOW
- PWM_OMAP_DMTIMER_SRC_32_KHZ
- PWM_OMAP_DMTIMER_SRC_EXT_CLK
- PWM_OMAP_DMTIMER_SRC_SYS_CLK
- PWM_OMAP_DMTIMER_TRIGGER_NONE
- PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW
- PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE
- PWM_ON
- PWM_ON_MIN
- PWM_ON_PERIOD_MAX
- PWM_ON_TIME_DIV_MASK
- PWM_OUTPUT
- PWM_OUTPUT_ENABLE
- PWM_OUTPUT_FREQ_25KHZ
- PWM_OUTPUT_LEFT
- PWM_OUT_EN
- PWM_OUT_VAL
- PWM_PERIOD
- PWM_PERIOD0
- PWM_PERIOD_BIT_WIDTH
- PWM_PERIOD_MASK
- PWM_PERIOD_MIN
- PWM_PHASEIN_ENABLE
- PWM_PHASEIN_INC
- PWM_PHASEIN_INT_ENABLE
- PWM_PHASEIN_VB_COUNT
- PWM_PIN_LEVEL
- PWM_PIPE_B
- PWM_POLARITY
- PWM_POLARITY_INVERSED
- PWM_POLARITY_INVERTED
- PWM_POLARITY_MASK
- PWM_POLARITY_NORMAL
- PWM_POLARITY_SHIFT
- PWM_PRD
- PWM_PRD_MASK
- PWM_PRESCALE_HIGH_MASK
- PWM_PRESCALE_LOW_MASK
- PWM_PRESCAL_MASK
- PWM_PRESCAL_OFF
- PWM_PULSE
- PWM_RAMP
- PWM_RDY
- PWM_RDY_BASE
- PWM_RDY_OFFSET
- PWM_REG
- PWM_REG_DTY
- PWM_REG_PRD
- PWM_REG_PRESCAL
- PWM_RR_EN_FROM_REG
- PWM_RR_EN_TO_REG
- PWM_RR_FROM_REG
- PWM_RR_TO_REG
- PWM_SCALE_SHIFT
- PWM_SCALE_WIDTH
- PWM_SEND_TRIG
- PWM_SET
- PWM_SETUP
- PWM_SIFIVE_CMPWIDTH
- PWM_SIFIVE_DEFAULT_PERIOD
- PWM_SIFIVE_PWMCFG
- PWM_SIFIVE_PWMCFG_CENTER
- PWM_SIFIVE_PWMCFG_DEGLITCH
- PWM_SIFIVE_PWMCFG_EN_ALWAYS
- PWM_SIFIVE_PWMCFG_EN_ONCE
- PWM_SIFIVE_PWMCFG_GANG
- PWM_SIFIVE_PWMCFG_IP
- PWM_SIFIVE_PWMCFG_SCALE
- PWM_SIFIVE_PWMCFG_STICKY
- PWM_SIFIVE_PWMCFG_ZERO_CMP
- PWM_SIFIVE_PWMCMP0
- PWM_SIFIVE_PWMCOUNT
- PWM_SIFIVE_PWMS
- PWM_SIFIVE_SIZE_PWMCMP
- PWM_SINGLE
- PWM_SIZE
- PWM_SR
- PWM_SR_ALL_CH_ON
- PWM_START
- PWM_STOP_TIME
- PWM_SW_UPDATE
- PWM_TIMEBASE_ENABLE
- PWM_TIMEBASE_VALUE
- PWM_TO_CNT
- PWM_TO_REG
- PWM_UNIT_ATTRS
- PWM_WAIT_TRIG
- PWMxON_LENGTH
- PWN_CNT_DEFAULT
- PWPR_B0WI
- PWPR_PFSWE
- PWR1_ASM_CON1
- PWR1_ASM_CON1_INIT_VAL
- PWR2COM
- PWR2_ASM_CON1
- PWR2_ASM_CON1_INIT_VAL
- PWR2_TOP_CON
- PWRAP_ADC_CMD_ADDR
- PWRAP_ADC_RDATA_ADDR
- PWRAP_ADC_RDATA_ADDR1
- PWRAP_ADC_RDATA_ADDR2
- PWRAP_ADC_RDY_ADDR
- PWRAP_CAP_BRIDGE
- PWRAP_CAP_DCM
- PWRAP_CAP_INT1_EN
- PWRAP_CAP_RESET
- PWRAP_CAP_WDT_SRC1
- PWRAP_CIPHER_EN
- PWRAP_CIPHER_IV_SEL
- PWRAP_CIPHER_KEY_SEL
- PWRAP_CIPHER_LOAD
- PWRAP_CIPHER_MODE
- PWRAP_CIPHER_RDY
- PWRAP_CIPHER_START
- PWRAP_CIPHER_SWRST
- PWRAP_CLR
- PWRAP_CRC_EN
- PWRAP_CSHEXT
- PWRAP_CSHEXT_READ
- PWRAP_CSHEXT_WRITE
- PWRAP_CSLEXT_END
- PWRAP_CSLEXT_READ
- PWRAP_CSLEXT_START
- PWRAP_CSLEXT_WRITE
- PWRAP_DCM_DBC_PRD
- PWRAP_DCM_EN
- PWRAP_DEBUG_INT_SEL
- PWRAP_DEW_BASE
- PWRAP_DEW_CIPHER_EN
- PWRAP_DEW_CIPHER_IV_SEL
- PWRAP_DEW_CIPHER_KEY_SEL
- PWRAP_DEW_CIPHER_LOAD
- PWRAP_DEW_CIPHER_MODE
- PWRAP_DEW_CIPHER_RDY
- PWRAP_DEW_CIPHER_START
- PWRAP_DEW_CIPHER_SWRST
- PWRAP_DEW_CRC_EN
- PWRAP_DEW_CRC_VAL
- PWRAP_DEW_DIO_EN
- PWRAP_DEW_EVENT_FLAG
- PWRAP_DEW_EVENT_OUT_EN
- PWRAP_DEW_EVENT_SRC
- PWRAP_DEW_EVENT_SRC_EN
- PWRAP_DEW_EVENT_TEST
- PWRAP_DEW_MON_FLAG_SEL
- PWRAP_DEW_MON_GRP_SEL
- PWRAP_DEW_RDDMY_NO
- PWRAP_DEW_READ_TEST
- PWRAP_DEW_READ_TEST_VAL
- PWRAP_DEW_WRITE_TEST
- PWRAP_DEW_WRITE_TEST_VAL
- PWRAP_DIO_EN
- PWRAP_DRV_CON1
- PWRAP_DVFS_ADR0
- PWRAP_DVFS_ADR1
- PWRAP_DVFS_ADR10
- PWRAP_DVFS_ADR11
- PWRAP_DVFS_ADR12
- PWRAP_DVFS_ADR13
- PWRAP_DVFS_ADR14
- PWRAP_DVFS_ADR15
- PWRAP_DVFS_ADR2
- PWRAP_DVFS_ADR3
- PWRAP_DVFS_ADR4
- PWRAP_DVFS_ADR5
- PWRAP_DVFS_ADR6
- PWRAP_DVFS_ADR7
- PWRAP_DVFS_ADR8
- PWRAP_DVFS_ADR9
- PWRAP_DVFS_STEP_CTRL0
- PWRAP_DVFS_STEP_CTRL1
- PWRAP_DVFS_STEP_CTRL2
- PWRAP_DVFS_WDATA0
- PWRAP_DVFS_WDATA1
- PWRAP_DVFS_WDATA10
- PWRAP_DVFS_WDATA11
- PWRAP_DVFS_WDATA12
- PWRAP_DVFS_WDATA13
- PWRAP_DVFS_WDATA14
- PWRAP_DVFS_WDATA15
- PWRAP_DVFS_WDATA2
- PWRAP_DVFS_WDATA3
- PWRAP_DVFS_WDATA4
- PWRAP_DVFS_WDATA5
- PWRAP_DVFS_WDATA6
- PWRAP_DVFS_WDATA7
- PWRAP_DVFS_WDATA8
- PWRAP_DVFS_WDATA9
- PWRAP_EINT_STA0_ADR
- PWRAP_EINT_STA1_ADR
- PWRAP_EVENT_DST_EN
- PWRAP_EVENT_IN_EN
- PWRAP_EVENT_STA
- PWRAP_EVENT_STACLR
- PWRAP_EXT_CK
- PWRAP_EXT_CK_WRITE
- PWRAP_EXT_GPS_AUXADC_RDATA_ADDR
- PWRAP_FILTER_CON0
- PWRAP_GET_WACS_FSM
- PWRAP_GET_WACS_RDATA
- PWRAP_GET_WACS_REQ
- PWRAP_GPIO_PULLEN0_CLR
- PWRAP_GPSINF_0_STA
- PWRAP_GPSINF_1_STA
- PWRAP_GPS_STA
- PWRAP_HARB_HPRIO
- PWRAP_HARB_INIT
- PWRAP_HARB_STA0
- PWRAP_HARB_STA1
- PWRAP_HIPRIO_ARB_EN
- PWRAP_INIT_DONE0
- PWRAP_INIT_DONE1
- PWRAP_INIT_DONE2
- PWRAP_INIT_DONE_MD32
- PWRAP_INIT_DONE_P2P
- PWRAP_INT1_CLR
- PWRAP_INT1_EN
- PWRAP_INT1_FLG
- PWRAP_INT_CLR
- PWRAP_INT_EN
- PWRAP_INT_FLG
- PWRAP_INT_FLG_RAW
- PWRAP_INT_GPS_AUXADC_CMD
- PWRAP_INT_GPS_AUXADC_CMD_ADDR
- PWRAP_INT_GPS_AUXADC_RDATA_ADDR
- PWRAP_MAN_CMD
- PWRAP_MAN_CMD_OP_CK
- PWRAP_MAN_CMD_OP_CSH
- PWRAP_MAN_CMD_OP_CSL
- PWRAP_MAN_CMD_OP_OUTD
- PWRAP_MAN_CMD_OP_OUTQ
- PWRAP_MAN_CMD_OP_OUTS
- PWRAP_MAN_CMD_SPI_WRITE
- PWRAP_MAN_CMD_SPI_WRITE_NEW
- PWRAP_MAN_EN
- PWRAP_MAN_RDATA
- PWRAP_MAN_VLDCLR
- PWRAP_MSB_FIRST
- PWRAP_MT2701
- PWRAP_MT6765
- PWRAP_MT6797
- PWRAP_MT7622
- PWRAP_MT8135
- PWRAP_MT8135_BRIDGE_INIT_DONE3
- PWRAP_MT8135_BRIDGE_INIT_DONE4
- PWRAP_MT8135_BRIDGE_INT_EN
- PWRAP_MT8135_BRIDGE_IORD_ARB_EN
- PWRAP_MT8135_BRIDGE_TIMER_EN
- PWRAP_MT8135_BRIDGE_WACS3_EN
- PWRAP_MT8135_BRIDGE_WACS4_EN
- PWRAP_MT8135_BRIDGE_WDT_SRC_EN
- PWRAP_MT8135_BRIDGE_WDT_UNIT
- PWRAP_MT8173
- PWRAP_MT8183
- PWRAP_MT8516
- PWRAP_MUX_SEL
- PWRAP_OP_TYPE
- PWRAP_PWRAP_ADC_CMD
- PWRAP_RDDMY
- PWRAP_RG_SPI_CON0
- PWRAP_RG_SPI_CON13
- PWRAP_RG_SPI_CON2
- PWRAP_RG_SPI_CON3
- PWRAP_RG_SPI_CON4
- PWRAP_RG_SPI_CON5
- PWRAP_RG_SPI_CON6
- PWRAP_RG_SPI_CON7
- PWRAP_RG_SPI_CON8
- PWRAP_RG_SPI_RECORD0
- PWRAP_RRARB_EN
- PWRAP_RRARB_INIT
- PWRAP_RRARB_STA0
- PWRAP_RRARB_STA1
- PWRAP_SIDLY
- PWRAP_SIG_ADR
- PWRAP_SIG_ERRVAL
- PWRAP_SIG_MODE
- PWRAP_SIG_VALUE
- PWRAP_SI_CK_CON
- PWRAP_SI_SAMPLE_CTRL
- PWRAP_SLV_CAP_DUALIO
- PWRAP_SLV_CAP_SECURITY
- PWRAP_SLV_CAP_SPI
- PWRAP_SMT_CON1
- PWRAP_SPI2_CTRL
- PWRAP_SPISLV_KEY
- PWRAP_SPMINF_STA
- PWRAP_STA
- PWRAP_STATE_INIT_DONE0
- PWRAP_STATE_SYNC_IDLE0
- PWRAP_STAUPD_CTRL
- PWRAP_STAUPD_GRPEN
- PWRAP_STAUPD_MAN_TRIG
- PWRAP_STAUPD_PRD
- PWRAP_STAUPD_STA
- PWRAP_SW_RST
- PWRAP_TIMER_EN
- PWRAP_TIMER_STA
- PWRAP_WACS0_CMD
- PWRAP_WACS0_EN
- PWRAP_WACS0_RDATA
- PWRAP_WACS0_VLDCLR
- PWRAP_WACS1_CMD
- PWRAP_WACS1_EN
- PWRAP_WACS1_RDATA
- PWRAP_WACS1_VLDCLR
- PWRAP_WACS2_CMD
- PWRAP_WACS2_EN
- PWRAP_WACS2_RDATA
- PWRAP_WACS2_VLDCLR
- PWRAP_WACS_FSM_IDLE
- PWRAP_WACS_FSM_REQ
- PWRAP_WACS_FSM_WFDLE
- PWRAP_WACS_FSM_WFVLDCLR
- PWRAP_WACS_INIT_DONE
- PWRAP_WACS_MD32_EN
- PWRAP_WACS_P2P_EN
- PWRAP_WACS_SYNC_BUSY
- PWRAP_WACS_WACS_SYNC_IDLE
- PWRAP_WDT_FLG
- PWRAP_WDT_SRC_EN
- PWRAP_WDT_SRC_EN_1
- PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE
- PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE
- PWRAP_WDT_SRC_EN_STAUPD_TRIG
- PWRAP_WDT_SRC_MASK_ALL
- PWRAP_WDT_SRC_MASK_NO_STAUPD
- PWRAP_WDT_UNIT
- PWRAP_WRAP_EN
- PWRAP_WRAP_STA
- PWRBIT_OW_EN
- PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK
- PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK
- PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT
- PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK
- PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT
- PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK
- PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT
- PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK
- PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT
- PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK
- PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT
- PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK
- PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT
- PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK
- PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT
- PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK
- PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK
- PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK
- PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT
- PWRCOM
- PWRCR
- PWRCR_BKPRST
- PWRCR_BUPINIT
- PWRCR_INT2
- PWRCR_PDWNACK
- PWRCR_PDWNREQ
- PWRCR_SCIEN
- PWRCR_SCISEL0
- PWRCR_SCISEL1
- PWRCSR0
- PWRCSR1
- PWRCSR1_BBP_CURR_STATE
- PWRCSR1_BBP_DESIRE_STATE
- PWRCSR1_PUT_TO_SLEEP
- PWRCSR1_RF_CURR_STATE
- PWRCSR1_RF_DESIRE_STATE
- PWRCSR1_SET_STATE
- PWRCTRL_PD_ACTIVE
- PWRCTRL_PIN_VALID
- PWRCTRL_POLARITY_HIGH
- PWRCTRL_PU_ACTIVE
- PWRCTXA
- PWRCTX_EN
- PWRCTX_MAXCNT_BCSUNIT
- PWRCTX_MAXCNT_RCSUNIT
- PWRCTX_MAXCNT_VCSUNIT0
- PWRCTX_MAXCNT_VCSUNIT1
- PWRCTX_MAXCNT_VECSUNIT
- PWRC_G12A_ETH_ID
- PWRC_G12A_VPU_ID
- PWRC_INT_MASK
- PWRC_INT_STATUS
- PWRC_KEY_DETECT_UP_TIME
- PWRC_ON_KEY_BIT
- PWRC_PIN_STATUS
- PWRC_SM1_AUDIO_ID
- PWRC_SM1_ETH_ID
- PWRC_SM1_GE2D_ID
- PWRC_SM1_NNA_ID
- PWRC_SM1_PCIE_ID
- PWRC_SM1_USB_ID
- PWRC_SM1_VPU_ID
- PWRDM_HAS_HDWR_SAR
- PWRDM_HAS_LOWPOWERSTATECHANGE
- PWRDM_HAS_MPU_QUIRK
- PWRDM_MAX_CLKDMS
- PWRDM_MAX_MEM_BANKS
- PWRDM_MAX_PWRSTS
- PWRDM_POWER_INACTIVE
- PWRDM_POWER_OFF
- PWRDM_POWER_ON
- PWRDM_POWER_RET
- PWRDM_STATE_NOW
- PWRDM_STATE_PREV
- PWRDM_TRACE_STATES_FLAG
- PWRDM_TRANSITION_BAILOUT
- PWRDN
- PWRDNCS0
- PWRDNCS1
- PWRDN_B
- PWRDN_IRQ
- PWRDN_IRQ_ENA
- PWRDN_IRQ_ENA_MASK
- PWRDN_IRQ_LEVEL
- PWRDN_IRQ_LEVEL_MASK
- PWRDN_IRQ_MASK
- PWRDN_WAIT_BUSY_OFF
- PWRDN_WAIT_PPLL_OFF
- PWRDN_WAIT_PWRSEQ_OFF
- PWRDOWN
- PWRDWN
- PWRDWN_SEQ_HOLD_CHANNEL
- PWRDWN_SEQ_NO_SEQUENCING
- PWRDWN_SEQ_POWERDOWN_PLL
- PWRDWN_SEQ_RESET_PLL
- PWREN
- PWREN_EN
- PWRER_DELAY_US
- PWRER_OFFS
- PWRER_RETRIES
- PWRGATE_ENABLE
- PWRGATE_STATUS
- PWRGATE_TOGGLE
- PWRGATE_TOGGLE_START
- PWRGT_STATUS
- PWRHW_SMC_IND_DATA__SMC_IND_DATA_MASK
- PWRHW_SMC_IND_DATA__SMC_IND_DATA__SHIFT
- PWRHW_SMC_IND_INDEX__SMC_IND_ADDR_MASK
- PWRHW_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT
- PWRITE
- PWRITEM
- PWRLINEFLTR
- PWRM2_I2SIPU_PWR_DOWN
- PWRM2_I2SIPU_PWR_UP
- PWRM2_I2SOPU_PWR_DOWN
- PWRM2_I2SOPU_PWR_UP
- PWRMGMT_SUBTYPE_TPC
- PWRMGTCR0_AV_IDLE_CNT
- PWRMGTCR0_AV_IDLE_CNT_SHIFT
- PWRMGTCR0_AV_IDLE_PD_EN
- PWRMGTCR0_PW20_ENT
- PWRMGTCR0_PW20_ENT_SHIFT
- PWRMGTCR0_PW20_WAIT
- PWRMGT_DISABLE_CPU_CSTATES_MASK
- PWRMGT_DISABLE_CPU_CSTATES_SHIFT
- PWRMGT_DISABLE_CPU_PSTATES_MASK
- PWRMGT_DISABLE_CPU_PSTATES_SHIFT
- PWRMGT_SEPARATION_TIME_MASK
- PWRMGT_SEPARATION_TIME_SHIFT
- PWRMNGMT
- PWRMOD
- PWRMODE_DEEPSLEEP
- PWRMODE_IDLE
- PWRMODE_SLEEP
- PWRMODE_STANDBY
- PWRM_BANDWIDTH_CONTROL
- PWRM_BER_CONTROL
- PWROFFCR_OFFS
- PWROFFSR_OFFS
- PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK
- PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT
- PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK
- PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT
- PWRONCR_OFFS
- PWRONSR_OFFS
- PWRON_D20F_INT
- PWRON_D20F_INT_MASK
- PWRON_D20R_INT
- PWRON_D20R_INT_MASK
- PWRON_D4SR_INT
- PWRON_D4SR_INT_MASK
- PWRON_RESET_PCMCIA_BOOT
- PWRS
- PWRSAVE_SPDWN_EN
- PWRSEQ_DELAY_MS
- PWRSEQ_DELAY_UNIT
- PWRSEQ_DELAY_US
- PWRSR_OFFS
- PWRSTS_INACTIVE
- PWRSTS_INA_ON
- PWRSTS_OFF
- PWRSTS_OFF_ON
- PWRSTS_OFF_RET
- PWRSTS_OFF_RET_ON
- PWRSTS_ON
- PWRSTS_RET
- PWRSTS_RET_ON
- PWRSVE
- PWRSVE_ISA
- PWRTBL_NUM_COEFF
- PWRTRACK_METHOD
- PWRUP_WAIT_MEM_INIT_DONE
- PWRUP_WAIT_PPLL_ON
- PWR_AB8500_H
- PWR_ACPI_INTERRUPT__AZ_CG_req_MASK
- PWR_ACPI_INTERRUPT__AZ_CG_req__SHIFT
- PWR_ACPI_INTERRUPT__AZ_CG_resp_MASK
- PWR_ACPI_INTERRUPT__AZ_CG_resp__SHIFT
- PWR_ACPI_INTERRUPT__BIF_CG_req_MASK
- PWR_ACPI_INTERRUPT__BIF_CG_req__SHIFT
- PWR_ACP_RESP__RESPONSE_MASK
- PWR_ACP_RESP__RESPONSE__SHIFT
- PWR_ADC_PDN
- PWR_AVFS0_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS0_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS0_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS0_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS0_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS0_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS10_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS10_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS10_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS10_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS10_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS10_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS11_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS11_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS11_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS11_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS11_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS11_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS12_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS12_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS12_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS12_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS12_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS12_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS13_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS13_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS13_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS13_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS13_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS13_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS14_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS14_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS14_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS14_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS14_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS14_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS15_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS15_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS15_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS15_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS15_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS15_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS16_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS16_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS16_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS16_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS16_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS16_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS17_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS17_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS17_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS17_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS17_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS17_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS18_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS18_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS18_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS18_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS18_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS18_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS19_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS19_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS19_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS19_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS19_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS19_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS1_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS1_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS1_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS1_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS1_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS1_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS20_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS20_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS20_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS20_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS20_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS20_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS21_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS21_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS21_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS21_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS21_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS21_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS22_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS22_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS22_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS22_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS22_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS22_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS23_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS23_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS23_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS23_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS23_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS23_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS24_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS24_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS24_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS24_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS24_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS24_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS25_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS25_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS25_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS25_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS25_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS25_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS26_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS26_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS26_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS26_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS26_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS26_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS27_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS27_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS27_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS27_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS27_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS27_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS2_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS2_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS2_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS2_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS2_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS2_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS3_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS3_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS3_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS3_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS3_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS3_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS4_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS4_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS4_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS4_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS4_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS4_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS5_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS5_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS5_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS5_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS5_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS5_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS6_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS6_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS6_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS6_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS6_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS6_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS7_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS7_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS7_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS7_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS7_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS7_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS8_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS8_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS8_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS8_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS8_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS8_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS9_CNTL_STATUS__AlarmFlag_MASK
- PWR_AVFS9_CNTL_STATUS__AlarmFlag__SHIFT
- PWR_AVFS9_CNTL_STATUS__MmDatOut_MASK
- PWR_AVFS9_CNTL_STATUS__MmDatOut__SHIFT
- PWR_AVFS9_CNTL_STATUS__PsmTdo_MASK
- PWR_AVFS9_CNTL_STATUS__PsmTdo__SHIFT
- PWR_AVFS_CNTL__AvfsRst_MASK
- PWR_AVFS_CNTL__AvfsRst__SHIFT
- PWR_AVFS_CNTL__DeepSleepIsolateEn_MASK
- PWR_AVFS_CNTL__DeepSleepIsolateEn__SHIFT
- PWR_AVFS_CNTL__Isolate_MASK
- PWR_AVFS_CNTL__Isolate__SHIFT
- PWR_AVFS_CNTL__MmBusIn_MASK
- PWR_AVFS_CNTL__MmBusIn__SHIFT
- PWR_AVFS_CNTL__MmLclRdEn_MASK
- PWR_AVFS_CNTL__MmLclRdEn__SHIFT
- PWR_AVFS_CNTL__MmLclSz_MASK
- PWR_AVFS_CNTL__MmLclSz__SHIFT
- PWR_AVFS_CNTL__MmLclWrEn_MASK
- PWR_AVFS_CNTL__MmLclWrEn__SHIFT
- PWR_AVFS_CNTL__MmState_MASK
- PWR_AVFS_CNTL__MmState__SHIFT
- PWR_AVFS_CNTL__PccIsolateEn_MASK
- PWR_AVFS_CNTL__PccIsolateEn__SHIFT
- PWR_AVFS_CNTL__PsmEn_MASK
- PWR_AVFS_CNTL__PsmEn__SHIFT
- PWR_AVFS_CNTL__PsmGater_MASK
- PWR_AVFS_CNTL__PsmGater__SHIFT
- PWR_AVFS_CNTL__PsmScanMode_MASK
- PWR_AVFS_CNTL__PsmScanMode__SHIFT
- PWR_AVFS_CNTL__PsmTrst_MASK
- PWR_AVFS_CNTL__PsmTrst__SHIFT
- PWR_AVFS_CNTL__SkipPhaseEn_MASK
- PWR_AVFS_CNTL__SkipPhaseEn__SHIFT
- PWR_AVFS_SEL__AvfsSel_MASK
- PWR_AVFS_SEL__AvfsSel__SHIFT
- PWR_AV_EN
- PWR_AV_MODE
- PWR_BASEADDR_MAC
- PWR_BASEADDR_PCIE
- PWR_BASEADDR_SDIO
- PWR_BASEADDR_USB
- PWR_BASE__INST0_SEG0
- PWR_BASE__INST0_SEG1
- PWR_BASE__INST0_SEG2
- PWR_BASE__INST0_SEG3
- PWR_BASE__INST0_SEG4
- PWR_BASE__INST1_SEG0
- PWR_BASE__INST1_SEG1
- PWR_BASE__INST1_SEG2
- PWR_BASE__INST1_SEG3
- PWR_BASE__INST1_SEG4
- PWR_BASE__INST2_SEG0
- PWR_BASE__INST2_SEG1
- PWR_BASE__INST2_SEG2
- PWR_BASE__INST2_SEG3
- PWR_BASE__INST2_SEG4
- PWR_BASE__INST3_SEG0
- PWR_BASE__INST3_SEG1
- PWR_BASE__INST3_SEG2
- PWR_BASE__INST3_SEG3
- PWR_BASE__INST3_SEG4
- PWR_BASE__INST4_SEG0
- PWR_BASE__INST4_SEG1
- PWR_BASE__INST4_SEG2
- PWR_BASE__INST4_SEG3
- PWR_BASE__INST4_SEG4
- PWR_BLON
- PWR_BUSY
- PWR_BUSY_CLOCK_CYCLES
- PWR_BUTTON
- PWR_CAM
- PWR_CKS_CNTL__CKS_BYPASS_MASK
- PWR_CKS_CNTL__CKS_BYPASS__SHIFT
- PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK
- PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT
- PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK
- PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT
- PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK
- PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT
- PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK
- PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT
- PWR_CKS_CNTL__CKS_PCCEnable_MASK
- PWR_CKS_CNTL__CKS_PCCEnable__SHIFT
- PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK
- PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT
- PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK
- PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT
- PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK
- PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT
- PWR_CKS_CNTL__CKS_TEMP_COMP_MASK
- PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT
- PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK
- PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT
- PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK
- PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT
- PWR_CKS_ENABLE__DS_HAND_SHAKE_EN_MASK
- PWR_CKS_ENABLE__DS_HAND_SHAKE_EN__SHIFT
- PWR_CKS_ENABLE__IGNORE_DROOP_DETECT_MASK
- PWR_CKS_ENABLE__IGNORE_DROOP_DETECT__SHIFT
- PWR_CKS_ENABLE__MET_CTRL_SEL_MASK
- PWR_CKS_ENABLE__MET_CTRL_SEL__SHIFT
- PWR_CKS_ENABLE__PCC_HAND_SHAKE_EN_MASK
- PWR_CKS_ENABLE__PCC_HAND_SHAKE_EN__SHIFT
- PWR_CKS_ENABLE__STRETCH_ENABLE_MASK
- PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT
- PWR_CKS_ENABLE__masterReset_MASK
- PWR_CKS_ENABLE__masterReset__SHIFT
- PWR_CKS_ENABLE__staticEnable_MASK
- PWR_CKS_ENABLE__staticEnable__SHIFT
- PWR_CLKC
- PWR_CLK_DIS_BIT
- PWR_CLK_DIS_CTL_MASK
- PWR_CLK_DIS_CTL_MASK_SFT
- PWR_CLK_DIS_CTL_SFT
- PWR_CLK_OUT_PDN
- PWR_CMD_DELAY
- PWR_CMD_END
- PWR_CMD_POLLING
- PWR_CMD_READ
- PWR_CMD_WRITE
- PWR_CNT
- PWR_CONFIG_TCP_ESTIMATED
- PWR_CONFIG_TCP_MEASURED
- PWR_CONFIG_TDP
- PWR_CONFIG_TGP
- PWR_CORE_CLOCK_CYCLES
- PWR_CPU_MASK
- PWR_CR
- PWR_CR_DBP
- PWR_CTL_EN
- PWR_CTRL
- PWR_CTRL1
- PWR_CTRL1_CLAMP_N_EN
- PWR_CTRL1_CORE1_DOWN_RATIO
- PWR_CTRL1_CORE2_DOWN_RATIO
- PWR_CTRL1_DIV1_DOWN_EN
- PWR_CTRL1_DIV2_DOWN_EN
- PWR_CTRL1_USE_CORE0_WFE
- PWR_CTRL1_USE_CORE0_WFI
- PWR_CTRL1_USE_CORE1_WFE
- PWR_CTRL1_USE_CORE1_WFI
- PWR_CTRL1_USE_CORE2_WFE
- PWR_CTRL1_USE_CORE2_WFI
- PWR_CTRL1_USE_CORE3_WFE
- PWR_CTRL1_USE_CORE3_WFI
- PWR_CTRL1_VREF_SUPPLY_TRIM
- PWR_CTRL2
- PWR_CTRL2_CORE1_UP_RATIO
- PWR_CTRL2_CORE2_UP_RATIO
- PWR_CTRL2_DIV1_UP_EN
- PWR_CTRL2_DIV2_UP_EN
- PWR_CTRL2_DUR_STANDBY1_VAL
- PWR_CTRL2_DUR_STANDBY2_VAL
- PWR_CTRL2_KFC
- PWR_CTRL_KFC
- PWR_CTRL_STATUS_MASK
- PWR_CTRL_STATUS_SHIFT
- PWR_CUT_ALL_MSK
- PWR_CUT_A_MSK
- PWR_CUT_B_MSK
- PWR_CUT_C_MSK
- PWR_CUT_D_MSK
- PWR_CUT_E_MSK
- PWR_CUT_F_MSK
- PWR_CUT_G_MSK
- PWR_CUT_TESTCHIP_MSK
- PWR_Command_Table
- PWR_DAC_PDN
- PWR_DATA
- PWR_DATA_EEPRPAD_RFE_CTRL_EN
- PWR_DC_REQ__REQUEST_MASK
- PWR_DC_REQ__REQUEST__SHIFT
- PWR_DC_RESP__RESPONSE_MASK
- PWR_DC_RESP__RESPONSE__SHIFT
- PWR_DEMOD_EN
- PWR_DESC_ACTIVE_LVLS_VCCQ2_0
- PWR_DESC_ACTIVE_LVLS_VCCQ_0
- PWR_DESC_ACTIVE_LVLS_VCC_0
- PWR_DESC_LEN
- PWR_DESC_TYPE
- PWR_DEVACT
- PWR_DEVOFF
- PWR_DEVSLP
- PWR_DFY_Section
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK
- PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK
- PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_0_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_10_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_11_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_12_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_13_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_14_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_15_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_1_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_2_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_3_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_4_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_5_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_6_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_7_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_8_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_9_CONTROL__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK
- PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK
- PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK
- PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT
- PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK
- PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT
- PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK
- PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT
- PWR_DOWN_LN_1_0
- PWR_DOWN_LN_2_1_0
- PWR_DOWN_LN_3
- PWR_DOWN_LN_3_1
- PWR_DOWN_LN_3_1_0
- PWR_DOWN_LN_3_2
- PWR_DOWN_LN_3_2_1
- PWR_DOWN_LN_MASK
- PWR_DOWN_LN_SHIFT
- PWR_DOWN_MASK
- PWR_DOWN_ON_RESET
- PWR_DOWN_SHIFT
- PWR_DWN
- PWR_EN
- PWR_ENABLE_WARMRESET
- PWR_ERROR_CAP
- PWR_EVENT_EXIT
- PWR_EVNT_IRQ_STAT_REG
- PWR_EVNT_LPM_IN_L2_MASK
- PWR_EVNT_LPM_OUT_L2_MASK
- PWR_FAB_ALL_MSK
- PWR_FAB_TSMC_MSK
- PWR_FAB_UMC_MSK
- PWR_FATAL_ERROR
- PWR_FE_CTL
- PWR_FLT_ERR_MSG_LEN
- PWR_GATE_CTRL
- PWR_GATE_EN
- PWR_GATING_EN
- PWR_GLOBAL_CTRL
- PWR_GPIO_PIN
- PWR_HWID
- PWR_HWIP
- PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK
- PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT
- PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK
- PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT
- PWR_IH_CONTROL__MAX_CREDIT_MASK
- PWR_IH_CONTROL__MAX_CREDIT__SHIFT
- PWR_INTF_ALL_MSK
- PWR_INTF_PCI_MSK
- PWR_INTF_SDIO_MSK
- PWR_INTF_USB_MSK
- PWR_INTR_OFFSET
- PWR_ISO_BIT
- PWR_ISO_EN
- PWR_LED
- PWR_LED_STATE_MASK
- PWR_LED_STATE_SHIFT
- PWR_LINE_IN_PDN
- PWR_LOCAL
- PWR_LVL_WAKEUP
- PWR_MAP
- PWR_MAXPS
- PWR_MGT_ACTIVITY_PIN_EN
- PWR_MGT_ACTIVITY_PIN_ON
- PWR_MGT_AUTO_PWR_UP_EN
- PWR_MGT_KEYBD_SNOOP
- PWR_MGT_MODE_MASK
- PWR_MGT_MODE_PCI
- PWR_MGT_MODE_PIN
- PWR_MGT_MODE_REG
- PWR_MGT_MODE_REGISTER
- PWR_MGT_MODE_TIMER
- PWR_MGT_ON
- PWR_MGT_SELF_REFRESH
- PWR_MGT_SELW4MS
- PWR_MGT_SLOWDOWN_MCLK
- PWR_MGT_STANDBY_POL
- PWR_MGT_STATUS_MASK
- PWR_MGT_STATUS_SUSPEND
- PWR_MGT_SUSPEND_POL
- PWR_MGT_TRISTATE_MEM_EN
- PWR_MIC_PDN
- PWR_MINPS
- PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK
- PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT
- PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK
- PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT
- PWR_MODE
- PWR_MODE_BTN_ONLY
- PWR_MODE_FULL_ACTIVE
- PWR_MODE_IDLE
- PWR_MODE_MASK
- PWR_MODE_OFF
- PWR_MODE_SLEEP
- PWR_NEON_MASK
- PWR_OFF
- PWR_OK
- PWR_OK_MASK
- PWR_OK_SHIFT
- PWR_OK_STATUS_MASK
- PWR_OK_STATUS_SHIFT
- PWR_ON
- PWR_ON_2ND_BIT
- PWR_ON_BIT
- PWR_ON_MASK
- PWR_ON_SHIFT
- PWR_ON_STATUS_MASK
- PWR_ON_STATUS_SHIFT
- PWR_OSC_PDN
- PWR_OUT_PDN
- PWR_PCC_CONTROL__PCC_POLARITY_MASK
- PWR_PCC_CONTROL__PCC_POLARITY__SHIFT
- PWR_PCC_GPIO_SELECT__GPIO_MASK
- PWR_PCC_GPIO_SELECT__GPIO__SHIFT
- PWR_PIN_CFG
- PWR_POWER_OFF
- PWR_PWRON_IRQ
- PWR_REG
- PWR_REG11
- PWR_REG18
- PWR_REMOTE
- PWR_RESETOUT_EN
- PWR_RST_BYPASS_DIS
- PWR_RST_BYPASS_EN
- PWR_RST_B_BIT
- PWR_SAVE_WAKEUP_IND
- PWR_SEL_MASK
- PWR_SLEEP_INTERVAL
- PWR_SOURCE_SELECT
- PWR_ST
- PWR_STA
- PWR_STATE_D0
- PWR_STATE_D1
- PWR_STATE_D2
- PWR_STATE_D3
- PWR_STATE_TARGET
- PWR_STATUS_ACTIVE
- PWR_STATUS_AUDIO
- PWR_STATUS_BDP
- PWR_STATUS_BTN_ONLY
- PWR_STATUS_CONN
- PWR_STATUS_DISP
- PWR_STATUS_ETH
- PWR_STATUS_ETHSYS
- PWR_STATUS_HIF
- PWR_STATUS_HIF0
- PWR_STATUS_HIF1
- PWR_STATUS_IDLE
- PWR_STATUS_IFR_MSC
- PWR_STATUS_ISP
- PWR_STATUS_MASK
- PWR_STATUS_MFG
- PWR_STATUS_MFG_2D
- PWR_STATUS_MFG_ASYNC
- PWR_STATUS_OFF
- PWR_STATUS_SHT
- PWR_STATUS_USB
- PWR_STATUS_USB2
- PWR_STATUS_VDEC
- PWR_STATUS_VENC
- PWR_STATUS_VENC_LT
- PWR_STATUS_WB
- PWR_STAT_MAX_CONT_MISSED_BCNS_SPREAD
- PWR_STOPON_PRWON
- PWR_STOPON_SYSEN
- PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK
- PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT
- PWR_SVI2_PLANE1_LOAD__PSI1_MASK
- PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT
- PWR_SVI2_STATUS__PLANE1_VID_MASK
- PWR_SVI2_STATUS__PLANE1_VID__SHIFT
- PWR_SVI2_STATUS__PLANE2_VID_MASK
- PWR_SVI2_STATUS__PLANE2_VID__SHIFT
- PWR_SW_EN
- PWR_TUNER_EN
- PWR_UAPSD
- PWR_UP
- PWR_UP_ALL_LANES
- PWR_USB33
- PWR_UVD_RESP__RESPONSE_MASK
- PWR_UVD_RESP__RESPONSE__SHIFT
- PWR_VCE_RESP__RESPONSE_MASK
- PWR_VCE_RESP__RESPONSE__SHIFT
- PWR_VIRT_RESET_REQ__PF_FLR_MASK
- PWR_VIRT_RESET_REQ__PF_FLR__SHIFT
- PWR_VIRT_RESET_REQ__VF_FLR_MASK
- PWR_VIRT_RESET_REQ__VF_FLR__SHIFT
- PWR_VOIP
- PWSR
- PWT
- PW_DETECT
- PW_MASK
- PW_MGMT1
- PW_MGMT2
- PW_MGMT3
- PW_MGMT4
- PW_PULLUP
- PW_RESETB
- PW_SHIFT
- PX30
- PX30_BCSH_BCS
- PX30_BCSH_COL_BAR
- PX30_BCSH_CTRL
- PX30_BCSH_H
- PX30_BLANKING_VALUE
- PX30_CLKGATE_CON
- PX30_CLKSEL0
- PX30_CLKSEL_CON
- PX30_CPUCLK_RATE
- PX30_DIV_ACLKM_MASK
- PX30_DIV_ACLKM_SHIFT
- PX30_DIV_PCLK_DBG_MASK
- PX30_DIV_PCLK_DBG_SHIFT
- PX30_DRV_BANK_STRIDE
- PX30_DRV_BITS_PER_PIN
- PX30_DRV_GRF_OFFSET
- PX30_DRV_PINS_PER_REG
- PX30_DRV_PMU_OFFSET
- PX30_DSP_BG
- PX30_DSP_CTRL0
- PX30_DSP_CTRL2
- PX30_DSP_HACT_ST_END
- PX30_DSP_HTOTAL_HS_END
- PX30_DSP_VACT_ST_END
- PX30_DSP_VACT_ST_END_F1
- PX30_DSP_VS_ST_END_F1
- PX30_DSP_VTOTAL_VS_END
- PX30_EMMC_CON0
- PX30_EMMC_CON1
- PX30_FLAG_REG
- PX30_FLAG_REG_FRM_VALID
- PX30_FRC_LOWER01_0
- PX30_FRC_LOWER01_1
- PX30_FRC_LOWER10_0
- PX30_FRC_LOWER10_1
- PX30_FRC_LOWER11_0
- PX30_FRC_LOWER11_1
- PX30_GAMMA_LUT_ADDR
- PX30_GLB_SRST_FST
- PX30_GLB_SRST_SND
- PX30_GMAC_PHY_INTF_SEL_RMII
- PX30_GMAC_SPEED_100M
- PX30_GMAC_SPEED_10M
- PX30_GRF_GMAC_CON1
- PX30_GRF_SOC_CON2
- PX30_GRF_SOC_STATUS0
- PX30_HWC_ALPHA_CTRL
- PX30_HWC_CTRL0
- PX30_HWC_CTRL1
- PX30_HWC_DSP_ST
- PX30_HWC_LUT_ADDR
- PX30_HWC_MST
- PX30_INTR_CLEAR
- PX30_INTR_EN
- PX30_INTR_STATUS
- PX30_IO_VSEL
- PX30_IO_VSEL_VCCIO6_SRC
- PX30_IO_VSEL_VCCIO6_SUPPLY_NUM
- PX30_LINE_FLAG
- PX30_MCU_CTRL
- PX30_MCU_RW_BYPASS_PORT
- PX30_MISC_CON
- PX30_MODE_CON
- PX30_PD_A35_0
- PX30_PD_A35_1
- PX30_PD_A35_2
- PX30_PD_A35_3
- PX30_PD_CRYPTO
- PX30_PD_DDR
- PX30_PD_GMAC
- PX30_PD_GPU
- PX30_PD_MMC_NAND
- PX30_PD_PMU
- PX30_PD_SCU
- PX30_PD_SDCARD
- PX30_PD_USB
- PX30_PD_VI
- PX30_PD_VO
- PX30_PD_VPU
- PX30_PLL_CON
- PX30_PMU_CLKGATE_CON
- PX30_PMU_CLKSEL_CON
- PX30_PMU_MODE
- PX30_PMU_PLL_CON
- PX30_PULL_BANK_STRIDE
- PX30_PULL_BITS_PER_PIN
- PX30_PULL_GRF_OFFSET
- PX30_PULL_PINS_PER_REG
- PX30_PULL_PMU_OFFSET
- PX30_REG_CFG_DONE
- PX30_SCHMITT_BANK_STRIDE
- PX30_SCHMITT_GRF_OFFSET
- PX30_SCHMITT_PINS_PER_GRF_REG
- PX30_SCHMITT_PINS_PER_PMU_REG
- PX30_SCHMITT_PMU_OFFSET
- PX30_SDIO_CON0
- PX30_SDIO_CON1
- PX30_SDMMC_CON0
- PX30_SDMMC_CON1
- PX30_SOFTRST_CON
- PX30_SYS_CTRL0
- PX30_SYS_CTRL1
- PX30_SYS_CTRL2
- PX30_VERSION
- PX30_VOP_STATUS
- PX30_WIN0_ACT_INFO
- PX30_WIN0_ALPHA_CTRL
- PX30_WIN0_CBR_MST0
- PX30_WIN0_COLOR_KEY
- PX30_WIN0_CTRL0
- PX30_WIN0_CTRL1
- PX30_WIN0_DSP_INFO
- PX30_WIN0_DSP_ST
- PX30_WIN0_SCL_FACTOR_CBR
- PX30_WIN0_SCL_FACTOR_YRGB
- PX30_WIN0_SCL_OFFSET
- PX30_WIN0_VIR
- PX30_WIN0_YRGB_MST0
- PX30_WIN1_ALPHA_CTRL
- PX30_WIN1_COLOR_KEY
- PX30_WIN1_CTRL0
- PX30_WIN1_CTRL1
- PX30_WIN1_DSP_INFO
- PX30_WIN1_DSP_ST
- PX30_WIN1_MST
- PX30_WIN1_VIR
- PX30_WIN2_ALPHA_CTRL
- PX30_WIN2_COLOR_KEY
- PX30_WIN2_CTRL0
- PX30_WIN2_CTRL1
- PX30_WIN2_DSP_INFO0
- PX30_WIN2_DSP_ST0
- PX30_WIN2_MST0
- PX30_WIN2_VIR0_1
- PX30_WIN2_VIR2_3
- PXA168_CLK_CCIC0
- PXA168_CLK_CCIC0_PHY
- PXA168_CLK_CCIC0_SPHY
- PXA168_CLK_CLK32
- PXA168_CLK_DFC
- PXA168_CLK_DISP0
- PXA168_CLK_GPIO
- PXA168_CLK_KPC
- PXA168_CLK_PLL1
- PXA168_CLK_PLL1_12
- PXA168_CLK_PLL1_13
- PXA168_CLK_PLL1_13_1_5
- PXA168_CLK_PLL1_16
- PXA168_CLK_PLL1_192
- PXA168_CLK_PLL1_2
- PXA168_CLK_PLL1_24
- PXA168_CLK_PLL1_2_1_5
- PXA168_CLK_PLL1_3_16
- PXA168_CLK_PLL1_4
- PXA168_CLK_PLL1_48
- PXA168_CLK_PLL1_6
- PXA168_CLK_PLL1_8
- PXA168_CLK_PLL1_96
- PXA168_CLK_PWM0
- PXA168_CLK_PWM1
- PXA168_CLK_PWM2
- PXA168_CLK_PWM3
- PXA168_CLK_RTC
- PXA168_CLK_SDH0
- PXA168_CLK_SDH1
- PXA168_CLK_SDH2
- PXA168_CLK_SPH
- PXA168_CLK_SSP0
- PXA168_CLK_SSP1
- PXA168_CLK_SSP2
- PXA168_CLK_SSP3
- PXA168_CLK_SSP4
- PXA168_CLK_TIMER
- PXA168_CLK_TWSI0
- PXA168_CLK_TWSI1
- PXA168_CLK_TWSI2
- PXA168_CLK_TWSI3
- PXA168_CLK_UART0
- PXA168_CLK_UART1
- PXA168_CLK_UART2
- PXA168_CLK_UART_PLL
- PXA168_CLK_USB
- PXA168_CLK_USB_PLL
- PXA168_CLK_VCTCXO
- PXA168_DEVICE
- PXA168_ETH_PHY_ADDR_DEFAULT
- PXA168_NR_CLKS
- PXA168_SSP
- PXA168_U2H_PHYBASE
- PXA168_U2H_REGBASE
- PXA168_U2O_PHYBASE
- PXA168_U2O_REGBASE
- PXA1928_APBC_NR_CLKS
- PXA1928_APMU_NR_CLKS
- PXA1928_CLK_DMA
- PXA1928_CLK_GC2D
- PXA1928_CLK_GC3D
- PXA1928_CLK_GPIO
- PXA1928_CLK_HSIC
- PXA1928_CLK_KPC
- PXA1928_CLK_NAND
- PXA1928_CLK_OWIRE
- PXA1928_CLK_PWM0
- PXA1928_CLK_PWM1
- PXA1928_CLK_PWM2
- PXA1928_CLK_PWM3
- PXA1928_CLK_RTC
- PXA1928_CLK_SDH0
- PXA1928_CLK_SDH1
- PXA1928_CLK_SDH2
- PXA1928_CLK_SDH3
- PXA1928_CLK_SDH4
- PXA1928_CLK_SSP0
- PXA1928_CLK_SSP1
- PXA1928_CLK_SSP2
- PXA1928_CLK_SW_JTAG
- PXA1928_CLK_TB_ROTARY
- PXA1928_CLK_THSENS_CPU
- PXA1928_CLK_THSENS_GC
- PXA1928_CLK_THSENS_GLOB
- PXA1928_CLK_THSENS_VPU
- PXA1928_CLK_TIMER1
- PXA1928_CLK_TWSI0
- PXA1928_CLK_TWSI1
- PXA1928_CLK_TWSI2
- PXA1928_CLK_TWSI3
- PXA1928_CLK_TWSI4
- PXA1928_CLK_TWSI5
- PXA1928_CLK_UART0
- PXA1928_CLK_UART1
- PXA1928_CLK_UART2
- PXA1928_CLK_UART3
- PXA1928_CLK_USB
- PXA1928_GPIO
- PXA210
- PXA210_B0
- PXA210_B1
- PXA210_B2
- PXA210_C0
- PXA250_A0
- PXA250_A1
- PXA250_B0
- PXA250_B1
- PXA250_B2
- PXA250_C0
- PXA255_A0
- PXA25X_CKEN
- PXA25X_CKEN_1RATE
- PXA25X_CKEN_1RATE_AO
- PXA25X_GPIO
- PXA25X_OSC3_CKEN
- PXA25X_PBUS147_CKEN
- PXA25X_PBUS95_CKEN
- PXA25x
- PXA25x_CCCR
- PXA25x_CLKCFG
- PXA25x_NSSP
- PXA25x_SSP
- PXA26X_GPIO
- PXA27X_CKEN
- PXA27X_CKEN_1RATE
- PXA27X_CKEN_1RATE_AO
- PXA27X_GPIO
- PXA27X_PBUS_CKEN
- PXA27x_CCCR
- PXA27x_CLKCFG
- PXA27x_SSP
- PXA2XX_AC97_RATES
- PXA2XX_CS_ASSERT
- PXA2XX_CS_DEASSERT
- PXA2XX_I2S_RATES
- PXA2XX_I2S_SYSCLK
- PXA2XX_LIB_H
- PXA2XX_SMEMC_BASE
- PXA2XX_SMEMC_PHYS
- PXA2XX_UDC_CMD_CONNECT
- PXA2XX_UDC_CMD_DISCONNECT
- PXA2XX_UDC_H
- PXA300_CS0_PHYS
- PXA300_CS1_PHYS
- PXA3XX_CKEN
- PXA3XX_CKEN_1RATE
- PXA3XX_GCU_BATCH_WORDS
- PXA3XX_GCU_BUFFER_WORDS
- PXA3XX_GCU_IOCTL_RESET
- PXA3XX_GCU_IOCTL_WAIT_IDLE
- PXA3XX_GCU_SHARED_MAGIC
- PXA3XX_GPIO
- PXA3XX_PBUS_CKEN
- PXA3XX_SMEMC_BASE
- PXA3XX_SMEMC_PHYS
- PXA3_DDR_HCAL
- PXA3_DDR_HCAL_HCEN
- PXA3_DDR_HCAL_HCPROG
- PXA3_DDR_HCAL_HCRNG
- PXA3_DMCIER
- PXA3_DMCIER_EDLP
- PXA3_DMCISR
- PXA3_MDCNFG
- PXA3_MDCNFG_DMCEN
- PXA3_RCOMP
- PXA3_RCOMP_SWEVAL
- PXA3xx_CS2_PHYS
- PXA3xx_CS3_PHYS
- PXA3xx_PM_S0D0C1
- PXA3xx_PM_S0D1C2
- PXA3xx_PM_S0D2C2
- PXA3xx_PM_S2D3C4
- PXA3xx_PM_S3D4C4
- PXA3xx_SSP
- PXA910_CLK_CCIC0
- PXA910_CLK_CCIC0_PHY
- PXA910_CLK_CCIC0_SPHY
- PXA910_CLK_CLK32
- PXA910_CLK_DFC
- PXA910_CLK_DISP0
- PXA910_CLK_GPIO
- PXA910_CLK_KPC
- PXA910_CLK_PLL1
- PXA910_CLK_PLL1_12
- PXA910_CLK_PLL1_13
- PXA910_CLK_PLL1_13_1_5
- PXA910_CLK_PLL1_16
- PXA910_CLK_PLL1_192
- PXA910_CLK_PLL1_2
- PXA910_CLK_PLL1_24
- PXA910_CLK_PLL1_2_1_5
- PXA910_CLK_PLL1_3_16
- PXA910_CLK_PLL1_4
- PXA910_CLK_PLL1_48
- PXA910_CLK_PLL1_6
- PXA910_CLK_PLL1_8
- PXA910_CLK_PLL1_96
- PXA910_CLK_PWM0
- PXA910_CLK_PWM1
- PXA910_CLK_PWM2
- PXA910_CLK_PWM3
- PXA910_CLK_RTC
- PXA910_CLK_SDH0
- PXA910_CLK_SDH1
- PXA910_CLK_SDH2
- PXA910_CLK_SPH
- PXA910_CLK_SSP0
- PXA910_CLK_SSP1
- PXA910_CLK_TIMER0
- PXA910_CLK_TIMER1
- PXA910_CLK_TWSI0
- PXA910_CLK_TWSI1
- PXA910_CLK_TWSI2
- PXA910_CLK_TWSI3
- PXA910_CLK_UART0
- PXA910_CLK_UART1
- PXA910_CLK_UART2
- PXA910_CLK_UART_PLL
- PXA910_CLK_USB
- PXA910_CLK_USB_PLL
- PXA910_CLK_VCTCXO
- PXA910_DEVICE
- PXA910_NR_CLKS
- PXA910_SQU
- PXA910_SSP
- PXA93X_GPIO
- PXAD_PRIO_HIGHEST
- PXAD_PRIO_LOW
- PXAD_PRIO_LOWEST
- PXAD_PRIO_NORMAL
- PXAV3_RPM_DELAY_MS
- PXA_BIT
- PXA_BUS_13Mhz
- PXA_BUS_60Mhz
- PXA_BUS_HSS
- PXA_BUS_RUN
- PXA_CAMERA_DATAWIDTH_10
- PXA_CAMERA_DATAWIDTH_4
- PXA_CAMERA_DATAWIDTH_5
- PXA_CAMERA_DATAWIDTH_8
- PXA_CAMERA_DATAWIDTH_9
- PXA_CAMERA_HSP
- PXA_CAMERA_MASTER
- PXA_CAMERA_MCLK_EN
- PXA_CAMERA_PCLK_EN
- PXA_CAMERA_PCP
- PXA_CAMERA_VSP
- PXA_CAM_DRV_NAME
- PXA_CAM_VERSION
- PXA_CKEN
- PXA_CKEN_1RATE
- PXA_CONSOLE
- PXA_CORE_13Mhz
- PXA_CORE_60Mhz
- PXA_CORE_RUN
- PXA_CORE_TURBO
- PXA_CS0_PHYS
- PXA_CS1_PHYS
- PXA_CS2_PHYS
- PXA_CS3_PHYS
- PXA_CS4_PHYS
- PXA_CS5_PHYS
- PXA_DCMD_BURST16
- PXA_DCMD_BURST32
- PXA_DCMD_BURST8
- PXA_DCMD_ENDIAN
- PXA_DCMD_ENDIRQEN
- PXA_DCMD_FLOWSRC
- PXA_DCMD_FLOWTRG
- PXA_DCMD_INCSRCADDR
- PXA_DCMD_INCTRGADDR
- PXA_DCMD_LENGTH
- PXA_DCMD_STARTIRQEN
- PXA_DCMD_STR
- PXA_DCMD_WIDTH1
- PXA_DCMD_WIDTH2
- PXA_DCMD_WIDTH4
- PXA_DCSR_BUSERR
- PXA_DCSR_CLRCMPST
- PXA_DCSR_CMPST
- PXA_DCSR_ENDINTR
- PXA_DCSR_EORINTR
- PXA_DCSR_EORIRQEN
- PXA_DCSR_EORJMPEN
- PXA_DCSR_EORSTOPEN
- PXA_DCSR_NODESC
- PXA_DCSR_REQPEND
- PXA_DCSR_RUN
- PXA_DCSR_SETCMPST
- PXA_DCSR_STARTINTR
- PXA_DCSR_STOPIRQEN
- PXA_DCSR_STOPSTATE
- PXA_DCSR_STR
- PXA_EP_BULK
- PXA_EP_CTRL
- PXA_EP_DEF
- PXA_EP_INT
- PXA_EP_IN_BULK
- PXA_EP_IN_INT
- PXA_EP_IN_ISO
- PXA_EP_ISO
- PXA_EP_OUT_BULK
- PXA_EP_OUT_ISO
- PXA_FLAG_CARD_PERMANENT
- PXA_FLAG_ENABLE_CLOCK_GATING
- PXA_FLAG_SD_8_BIT_CAPABLE_SLOT
- PXA_FUNCTION
- PXA_GPIO_IRQ_BASE
- PXA_GPIO_ONLY_PIN
- PXA_GPIO_PIN
- PXA_GPIO_TO_IRQ
- PXA_IRQ
- PXA_ISA_IRQ
- PXA_LCD_13Mhz
- PXA_LCD_RUN
- PXA_MBUS_LAYOUT_PACKED
- PXA_MBUS_LAYOUT_PLANAR_2Y_C
- PXA_MBUS_LAYOUT_PLANAR_2Y_U_V
- PXA_MBUS_LAYOUT_PLANAR_Y_C
- PXA_MBUS_ORDER_BE
- PXA_MBUS_ORDER_LE
- PXA_MBUS_PACKING_2X8_PADHI
- PXA_MBUS_PACKING_EXTEND16
- PXA_MBUS_PACKING_NONE
- PXA_MEM_13Mhz
- PXA_MEM_RUN
- PXA_MEM_SYSTEM_BUS
- PXA_NAME
- PXA_NAME_LEN
- PXA_NR_BUILTIN_GPIO
- PXA_NR_IRQS
- PXA_PIN
- PXA_PINCTRL_PIN
- PXA_SPH
- PXA_SSP_AUDIO_DIV_ACDS
- PXA_SSP_AUDIO_DIV_SCDB
- PXA_SSP_CLK_AUDIO
- PXA_SSP_CLK_AUDIO_DIV_1
- PXA_SSP_CLK_AUDIO_DIV_16
- PXA_SSP_CLK_AUDIO_DIV_2
- PXA_SSP_CLK_AUDIO_DIV_32
- PXA_SSP_CLK_AUDIO_DIV_4
- PXA_SSP_CLK_AUDIO_DIV_8
- PXA_SSP_CLK_EXT
- PXA_SSP_CLK_NET
- PXA_SSP_CLK_NET_PLL
- PXA_SSP_CLK_PLL
- PXA_SSP_CLK_SCDB_1
- PXA_SSP_CLK_SCDB_4
- PXA_SSP_CLK_SCDB_8
- PXA_SSP_DIV_SCR
- PXA_SSP_FORMATS
- PXA_SSP_PLL_OUT
- PXA_SSP_RATES
- PXA_U2OEHCI
- PXA_UDC_NUM_ENDPOINTS
- PXA_UHC_MAX_PORTNUM
- PXA_USB_PHY_MMP2
- PXA_USB_PHY_PXA168
- PXA_USB_PHY_PXA910
- PXC200_muxsel
- PXDaddress
- PXDlength
- PXE1610_NUM_PAGES
- PXI_Clk10
- PXI_Star
- PXIe_Clk100
- PXLASYNC_LO_MASK_CAMIF_GSCL
- PXLFMT
- PXLY_RC_FRAG_IP_PKT
- PXLY_RC_IP_CHKSUM
- PXLY_RC_JUMBO_FRAME
- PXLY_RC_LLC_SNAP
- PXLY_RC_MAC_FILTER
- PXLY_RC_TCP_2_TUPLE
- PXLY_RC_TCP_3_TUPLE
- PXLY_RC_TCP_6_TUPLE
- PXLY_RC_TCP_UDP_CHKSUM
- PXLY_RC_UDP_6_TUPLE
- PXLY_RC_UNTAG_FILTER
- PXLY_RC_VALID
- PXLY_RC_VLAN_FILTER
- PXLY_RC_VLAN_PERM
- PXLY_RC_VLAN_TAG_FILTER
- PXLY_RC_VLAN_XTRACT
- PXL_PLLCTRL
- PXL_PLLPARAM
- PXL_RGB
- PXM_FLAG_LEN
- PXM_INVAL
- PXO_SRC
- PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
- PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
- PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
- PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
- PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
- PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
- PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
- PXP2_REG_HST_DATA_FIFO_STATUS
- PXP2_REG_HST_HEADER_FIFO_STATUS
- PXP2_REG_PGL_ADDR_88_F0
- PXP2_REG_PGL_ADDR_88_F1
- PXP2_REG_PGL_ADDR_8C_F0
- PXP2_REG_PGL_ADDR_8C_F1
- PXP2_REG_PGL_ADDR_90_F0
- PXP2_REG_PGL_ADDR_90_F1
- PXP2_REG_PGL_ADDR_94_F0
- PXP2_REG_PGL_ADDR_94_F1
- PXP2_REG_PGL_CONTROL0
- PXP2_REG_PGL_CONTROL1
- PXP2_REG_PGL_DEBUG
- PXP2_REG_PGL_EXP_ROM2
- PXP2_REG_PGL_INT_CSDM_0
- PXP2_REG_PGL_INT_CSDM_1
- PXP2_REG_PGL_INT_CSDM_2
- PXP2_REG_PGL_INT_CSDM_3
- PXP2_REG_PGL_INT_CSDM_4
- PXP2_REG_PGL_INT_CSDM_5
- PXP2_REG_PGL_INT_CSDM_6
- PXP2_REG_PGL_INT_CSDM_7
- PXP2_REG_PGL_INT_TSDM_0
- PXP2_REG_PGL_INT_TSDM_1
- PXP2_REG_PGL_INT_TSDM_2
- PXP2_REG_PGL_INT_TSDM_3
- PXP2_REG_PGL_INT_TSDM_4
- PXP2_REG_PGL_INT_TSDM_5
- PXP2_REG_PGL_INT_TSDM_6
- PXP2_REG_PGL_INT_TSDM_7
- PXP2_REG_PGL_INT_USDM_0
- PXP2_REG_PGL_INT_USDM_1
- PXP2_REG_PGL_INT_USDM_2
- PXP2_REG_PGL_INT_USDM_3
- PXP2_REG_PGL_INT_USDM_4
- PXP2_REG_PGL_INT_USDM_5
- PXP2_REG_PGL_INT_USDM_6
- PXP2_REG_PGL_INT_USDM_7
- PXP2_REG_PGL_INT_XSDM_0
- PXP2_REG_PGL_INT_XSDM_1
- PXP2_REG_PGL_INT_XSDM_2
- PXP2_REG_PGL_INT_XSDM_3
- PXP2_REG_PGL_INT_XSDM_4
- PXP2_REG_PGL_INT_XSDM_5
- PXP2_REG_PGL_INT_XSDM_6
- PXP2_REG_PGL_INT_XSDM_7
- PXP2_REG_PGL_PRETEND_FUNC_F0
- PXP2_REG_PGL_PRETEND_FUNC_F1
- PXP2_REG_PGL_PRETEND_FUNC_F2
- PXP2_REG_PGL_PRETEND_FUNC_F3
- PXP2_REG_PGL_PRETEND_FUNC_F4
- PXP2_REG_PGL_PRETEND_FUNC_F5
- PXP2_REG_PGL_PRETEND_FUNC_F6
- PXP2_REG_PGL_PRETEND_FUNC_F7
- PXP2_REG_PGL_READ_BLOCKED
- PXP2_REG_PGL_TAGS_LIMIT
- PXP2_REG_PGL_TXW_CDTS
- PXP2_REG_PGL_WRITE_BLOCKED
- PXP2_REG_PSWRQ_BW_ADD1
- PXP2_REG_PSWRQ_BW_ADD10
- PXP2_REG_PSWRQ_BW_ADD11
- PXP2_REG_PSWRQ_BW_ADD2
- PXP2_REG_PSWRQ_BW_ADD28
- PXP2_REG_PSWRQ_BW_ADD3
- PXP2_REG_PSWRQ_BW_ADD6
- PXP2_REG_PSWRQ_BW_ADD7
- PXP2_REG_PSWRQ_BW_ADD8
- PXP2_REG_PSWRQ_BW_ADD9
- PXP2_REG_PSWRQ_BW_CREDIT
- PXP2_REG_PSWRQ_BW_L1
- PXP2_REG_PSWRQ_BW_L10
- PXP2_REG_PSWRQ_BW_L11
- PXP2_REG_PSWRQ_BW_L2
- PXP2_REG_PSWRQ_BW_L28
- PXP2_REG_PSWRQ_BW_L3
- PXP2_REG_PSWRQ_BW_L6
- PXP2_REG_PSWRQ_BW_L7
- PXP2_REG_PSWRQ_BW_L8
- PXP2_REG_PSWRQ_BW_L9
- PXP2_REG_PSWRQ_BW_RD
- PXP2_REG_PSWRQ_BW_UB1
- PXP2_REG_PSWRQ_BW_UB10
- PXP2_REG_PSWRQ_BW_UB11
- PXP2_REG_PSWRQ_BW_UB2
- PXP2_REG_PSWRQ_BW_UB28
- PXP2_REG_PSWRQ_BW_UB3
- PXP2_REG_PSWRQ_BW_UB6
- PXP2_REG_PSWRQ_BW_UB7
- PXP2_REG_PSWRQ_BW_UB8
- PXP2_REG_PSWRQ_BW_UB9
- PXP2_REG_PSWRQ_BW_WR
- PXP2_REG_PSWRQ_CDU0_L2P
- PXP2_REG_PSWRQ_QM0_L2P
- PXP2_REG_PSWRQ_SRC0_L2P
- PXP2_REG_PSWRQ_TM0_L2P
- PXP2_REG_PSWRQ_TSDM0_L2P
- PXP2_REG_PXP2_INT_MASK_0
- PXP2_REG_PXP2_INT_STS
- PXP2_REG_PXP2_INT_STS_0
- PXP2_REG_PXP2_INT_STS_1
- PXP2_REG_PXP2_INT_STS_CLR_0
- PXP2_REG_PXP2_PRTY_MASK_0
- PXP2_REG_PXP2_PRTY_MASK_1
- PXP2_REG_PXP2_PRTY_STS_0
- PXP2_REG_PXP2_PRTY_STS_1
- PXP2_REG_PXP2_PRTY_STS_CLR_0
- PXP2_REG_PXP2_PRTY_STS_CLR_1
- PXP2_REG_RD_ALMOST_FULL_0
- PXP2_REG_RD_BLK_CNT
- PXP2_REG_RD_BLK_NUM_CFG
- PXP2_REG_RD_CDURD_SWAP_MODE
- PXP2_REG_RD_DISABLE_INPUTS
- PXP2_REG_RD_INIT_DONE
- PXP2_REG_RD_MAX_BLKS_VQ10
- PXP2_REG_RD_MAX_BLKS_VQ11
- PXP2_REG_RD_MAX_BLKS_VQ17
- PXP2_REG_RD_MAX_BLKS_VQ18
- PXP2_REG_RD_MAX_BLKS_VQ19
- PXP2_REG_RD_MAX_BLKS_VQ22
- PXP2_REG_RD_MAX_BLKS_VQ25
- PXP2_REG_RD_MAX_BLKS_VQ6
- PXP2_REG_RD_MAX_BLKS_VQ9
- PXP2_REG_RD_PBF_SWAP_MODE
- PXP2_REG_RD_PORT_IS_IDLE_0
- PXP2_REG_RD_PORT_IS_IDLE_1
- PXP2_REG_RD_QM_SWAP_MODE
- PXP2_REG_RD_SRC_SWAP_MODE
- PXP2_REG_RD_SR_CNT
- PXP2_REG_RD_SR_NUM_CFG
- PXP2_REG_RD_START_INIT
- PXP2_REG_RD_TM_SWAP_MODE
- PXP2_REG_RQ_BW_RD_ADD0
- PXP2_REG_RQ_BW_RD_ADD12
- PXP2_REG_RQ_BW_RD_ADD13
- PXP2_REG_RQ_BW_RD_ADD14
- PXP2_REG_RQ_BW_RD_ADD15
- PXP2_REG_RQ_BW_RD_ADD16
- PXP2_REG_RQ_BW_RD_ADD17
- PXP2_REG_RQ_BW_RD_ADD18
- PXP2_REG_RQ_BW_RD_ADD19
- PXP2_REG_RQ_BW_RD_ADD20
- PXP2_REG_RQ_BW_RD_ADD22
- PXP2_REG_RQ_BW_RD_ADD23
- PXP2_REG_RQ_BW_RD_ADD24
- PXP2_REG_RQ_BW_RD_ADD25
- PXP2_REG_RQ_BW_RD_ADD26
- PXP2_REG_RQ_BW_RD_ADD27
- PXP2_REG_RQ_BW_RD_ADD4
- PXP2_REG_RQ_BW_RD_ADD5
- PXP2_REG_RQ_BW_RD_L0
- PXP2_REG_RQ_BW_RD_L12
- PXP2_REG_RQ_BW_RD_L13
- PXP2_REG_RQ_BW_RD_L14
- PXP2_REG_RQ_BW_RD_L15
- PXP2_REG_RQ_BW_RD_L16
- PXP2_REG_RQ_BW_RD_L17
- PXP2_REG_RQ_BW_RD_L18
- PXP2_REG_RQ_BW_RD_L19
- PXP2_REG_RQ_BW_RD_L20
- PXP2_REG_RQ_BW_RD_L22
- PXP2_REG_RQ_BW_RD_L23
- PXP2_REG_RQ_BW_RD_L24
- PXP2_REG_RQ_BW_RD_L25
- PXP2_REG_RQ_BW_RD_L26
- PXP2_REG_RQ_BW_RD_L27
- PXP2_REG_RQ_BW_RD_L4
- PXP2_REG_RQ_BW_RD_L5
- PXP2_REG_RQ_BW_RD_UBOUND0
- PXP2_REG_RQ_BW_RD_UBOUND12
- PXP2_REG_RQ_BW_RD_UBOUND13
- PXP2_REG_RQ_BW_RD_UBOUND14
- PXP2_REG_RQ_BW_RD_UBOUND15
- PXP2_REG_RQ_BW_RD_UBOUND16
- PXP2_REG_RQ_BW_RD_UBOUND17
- PXP2_REG_RQ_BW_RD_UBOUND18
- PXP2_REG_RQ_BW_RD_UBOUND19
- PXP2_REG_RQ_BW_RD_UBOUND20
- PXP2_REG_RQ_BW_RD_UBOUND22
- PXP2_REG_RQ_BW_RD_UBOUND23
- PXP2_REG_RQ_BW_RD_UBOUND24
- PXP2_REG_RQ_BW_RD_UBOUND25
- PXP2_REG_RQ_BW_RD_UBOUND26
- PXP2_REG_RQ_BW_RD_UBOUND27
- PXP2_REG_RQ_BW_RD_UBOUND4
- PXP2_REG_RQ_BW_RD_UBOUND5
- PXP2_REG_RQ_BW_WR_ADD29
- PXP2_REG_RQ_BW_WR_ADD30
- PXP2_REG_RQ_BW_WR_L29
- PXP2_REG_RQ_BW_WR_L30
- PXP2_REG_RQ_BW_WR_UBOUND29
- PXP2_REG_RQ_BW_WR_UBOUND30
- PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR
- PXP2_REG_RQ_CDU_ENDIAN_M
- PXP2_REG_RQ_CDU_FIRST_ILT
- PXP2_REG_RQ_CDU_LAST_ILT
- PXP2_REG_RQ_CDU_P_SIZE
- PXP2_REG_RQ_CFG_DONE
- PXP2_REG_RQ_DBG_ENDIAN_M
- PXP2_REG_RQ_DISABLE_INPUTS
- PXP2_REG_RQ_DRAM_ALIGN
- PXP2_REG_RQ_DRAM_ALIGN_RD
- PXP2_REG_RQ_DRAM_ALIGN_SEL
- PXP2_REG_RQ_ELT_DISABLE
- PXP2_REG_RQ_HC_ENDIAN_M
- PXP2_REG_RQ_ILT_MODE
- PXP2_REG_RQ_ONCHIP_AT
- PXP2_REG_RQ_ONCHIP_AT_B0
- PXP2_REG_RQ_PDR_LIMIT
- PXP2_REG_RQ_QM_ENDIAN_M
- PXP2_REG_RQ_QM_FIRST_ILT
- PXP2_REG_RQ_QM_LAST_ILT
- PXP2_REG_RQ_QM_P_SIZE
- PXP2_REG_RQ_RBC_DONE
- PXP2_REG_RQ_RD_MBS0
- PXP2_REG_RQ_RD_MBS1
- PXP2_REG_RQ_SRC_ENDIAN_M
- PXP2_REG_RQ_SRC_FIRST_ILT
- PXP2_REG_RQ_SRC_LAST_ILT
- PXP2_REG_RQ_SRC_P_SIZE
- PXP2_REG_RQ_TM_ENDIAN_M
- PXP2_REG_RQ_TM_FIRST_ILT
- PXP2_REG_RQ_TM_LAST_ILT
- PXP2_REG_RQ_TM_P_SIZE
- PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY
- PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR
- PXP2_REG_RQ_VQ0_ENTRY_CNT
- PXP2_REG_RQ_VQ10_ENTRY_CNT
- PXP2_REG_RQ_VQ11_ENTRY_CNT
- PXP2_REG_RQ_VQ12_ENTRY_CNT
- PXP2_REG_RQ_VQ13_ENTRY_CNT
- PXP2_REG_RQ_VQ14_ENTRY_CNT
- PXP2_REG_RQ_VQ15_ENTRY_CNT
- PXP2_REG_RQ_VQ16_ENTRY_CNT
- PXP2_REG_RQ_VQ17_ENTRY_CNT
- PXP2_REG_RQ_VQ18_ENTRY_CNT
- PXP2_REG_RQ_VQ19_ENTRY_CNT
- PXP2_REG_RQ_VQ1_ENTRY_CNT
- PXP2_REG_RQ_VQ20_ENTRY_CNT
- PXP2_REG_RQ_VQ21_ENTRY_CNT
- PXP2_REG_RQ_VQ22_ENTRY_CNT
- PXP2_REG_RQ_VQ23_ENTRY_CNT
- PXP2_REG_RQ_VQ24_ENTRY_CNT
- PXP2_REG_RQ_VQ25_ENTRY_CNT
- PXP2_REG_RQ_VQ26_ENTRY_CNT
- PXP2_REG_RQ_VQ27_ENTRY_CNT
- PXP2_REG_RQ_VQ28_ENTRY_CNT
- PXP2_REG_RQ_VQ29_ENTRY_CNT
- PXP2_REG_RQ_VQ2_ENTRY_CNT
- PXP2_REG_RQ_VQ30_ENTRY_CNT
- PXP2_REG_RQ_VQ31_ENTRY_CNT
- PXP2_REG_RQ_VQ3_ENTRY_CNT
- PXP2_REG_RQ_VQ4_ENTRY_CNT
- PXP2_REG_RQ_VQ5_ENTRY_CNT
- PXP2_REG_RQ_VQ6_ENTRY_CNT
- PXP2_REG_RQ_VQ7_ENTRY_CNT
- PXP2_REG_RQ_VQ8_ENTRY_CNT
- PXP2_REG_RQ_VQ9_ENTRY_CNT
- PXP2_REG_RQ_WR_MBS0
- PXP2_REG_RQ_WR_MBS1
- PXP2_REG_WR_CDU_MPS
- PXP2_REG_WR_CSDM_MPS
- PXP2_REG_WR_DBG_MPS
- PXP2_REG_WR_DMAE_MPS
- PXP2_REG_WR_DMAE_TH
- PXP2_REG_WR_HC_MPS
- PXP2_REG_WR_QM_MPS
- PXP2_REG_WR_REV_MODE
- PXP2_REG_WR_SRC_MPS
- PXP2_REG_WR_TM_MPS
- PXP2_REG_WR_TSDM_MPS
- PXP2_REG_WR_USDMDP_TH
- PXP2_REG_WR_USDM_MPS
- PXP2_REG_WR_XSDM_MPS
- PXPCS_TL_CONTROL_5
- PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN
- PXPCS_TL_CONTROL_5_DL_ERR_ATTN
- PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT
- PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1
- PXPCS_TL_CONTROL_5_ERR_ECRC
- PXPCS_TL_CONTROL_5_ERR_ECRC1
- PXPCS_TL_CONTROL_5_ERR_FC_PRTL
- PXPCS_TL_CONTROL_5_ERR_FC_PRTL1
- PXPCS_TL_CONTROL_5_ERR_MALF_TLP
- PXPCS_TL_CONTROL_5_ERR_MALF_TLP1
- PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT
- PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1
- PXPCS_TL_CONTROL_5_ERR_PSND_TLP
- PXPCS_TL_CONTROL_5_ERR_PSND_TLP1
- PXPCS_TL_CONTROL_5_ERR_RX_OFLOW
- PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1
- PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL
- PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1
- PXPCS_TL_CONTROL_5_ERR_UNSPPORT
- PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
- PXPCS_TL_CONTROL_5_MPS_ERR_ATTN
- PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN
- PXPCS_TL_CONTROL_5_PHY_ERR_ATTN
- PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT
- PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1
- PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG
- PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR
- PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE
- PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW
- PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN
- PXPCS_TL_FUNC345_STAT
- PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2
- PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3
- PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4
- PXPCS_TL_FUNC345_STAT_ERR_ECRC2
- PXPCS_TL_FUNC345_STAT_ERR_ECRC3
- PXPCS_TL_FUNC345_STAT_ERR_ECRC4
- PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2
- PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3
- PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4
- PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2
- PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3
- PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4
- PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2
- PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3
- PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4
- PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2
- PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3
- PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4
- PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2
- PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3
- PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4
- PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2
- PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3
- PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4
- PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
- PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
- PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
- PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2
- PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3
- PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4
- PXPCS_TL_FUNC678_STAT
- PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5
- PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6
- PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7
- PXPCS_TL_FUNC678_STAT_ERR_ECRC5
- PXPCS_TL_FUNC678_STAT_ERR_ECRC6
- PXPCS_TL_FUNC678_STAT_ERR_ECRC7
- PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5
- PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6
- PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7
- PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5
- PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6
- PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7
- PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5
- PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6
- PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7
- PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5
- PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6
- PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7
- PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5
- PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6
- PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7
- PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5
- PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6
- PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7
- PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
- PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
- PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
- PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5
- PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6
- PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7
- PXP_ADMIN_WINDOW_ALLOWED_LENGTH
- PXP_BAR0_END_GRC
- PXP_BAR0_END_IGU
- PXP_BAR0_END_MSDM
- PXP_BAR0_END_PSDM
- PXP_BAR0_END_TSDM
- PXP_BAR0_END_USDM
- PXP_BAR0_END_XSDM
- PXP_BAR0_END_YSDM
- PXP_BAR0_FIRST_INVALID_ADDRESS
- PXP_BAR0_GRC_LENGTH
- PXP_BAR0_IGU_LENGTH
- PXP_BAR0_SDM_LENGTH
- PXP_BAR0_SDM_RESERVED_LENGTH
- PXP_BAR0_START_GRC
- PXP_BAR0_START_IGU
- PXP_BAR0_START_MSDM
- PXP_BAR0_START_PSDM
- PXP_BAR0_START_TSDM
- PXP_BAR0_START_USDM
- PXP_BAR0_START_XSDM
- PXP_BAR0_START_YSDM
- PXP_BAR_DQ
- PXP_BAR_GRC
- PXP_BAR_IGU
- PXP_BAR_MSDM
- PXP_BAR_PSDM
- PXP_BAR_TSDM
- PXP_BAR_USDM
- PXP_BAR_XSDM
- PXP_BAR_YSDM
- PXP_CONCRETE_FID_PATH_MASK
- PXP_CONCRETE_FID_PATH_SHIFT
- PXP_CONCRETE_FID_PFID_MASK
- PXP_CONCRETE_FID_PFID_SHIFT
- PXP_CONCRETE_FID_PORT_MASK
- PXP_CONCRETE_FID_PORT_SHIFT
- PXP_CONCRETE_FID_VFID_MASK
- PXP_CONCRETE_FID_VFID_SHIFT
- PXP_CONCRETE_FID_VFVALID_MASK
- PXP_CONCRETE_FID_VFVALID_SHIFT
- PXP_ERR_CFG_REG
- PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END
- PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH
- PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM
- PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE
- PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START
- PXP_EXTERNAL_BAR_PF_WINDOW_END
- PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH
- PXP_EXTERNAL_BAR_PF_WINDOW_NUM
- PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE
- PXP_EXTERNAL_BAR_PF_WINDOW_START
- PXP_GLOBAL_ENTRY_SIZE
- PXP_IGNORE_PCIE_ERRORS
- PXP_ILT_BLOCK_FACTOR_MULTIPLIER
- PXP_ILT_PAGE_SIZE_NUM_BITS_MIN
- PXP_NUM_GLOBAL_WINDOWS
- PXP_NUM_ILT_RECORDS_BB
- PXP_NUM_ILT_RECORDS_K2
- PXP_NUM_PF_WINDOWS
- PXP_PER_PF_ENTRY_SIZE
- PXP_PF_GLOBAL_PRETEND_ADDR
- PXP_PF_ME_CONCRETE_ADDR
- PXP_PF_ME_OPAQUE_ADDR
- PXP_PF_ME_OPAQUE_MASK_ADDR
- PXP_PF_WINDOW_ADMIN_END
- PXP_PF_WINDOW_ADMIN_GLOBAL_END
- PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH
- PXP_PF_WINDOW_ADMIN_GLOBAL_START
- PXP_PF_WINDOW_ADMIN_LENGTH
- PXP_PF_WINDOW_ADMIN_PER_PF_END
- PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH
- PXP_PF_WINDOW_ADMIN_PER_PF_START
- PXP_PF_WINDOW_ADMIN_START
- PXP_PRETEND_CMD_IS_CONCRETE_MASK
- PXP_PRETEND_CMD_IS_CONCRETE_SHIFT
- PXP_PRETEND_CMD_PATH_MASK
- PXP_PRETEND_CMD_PATH_SHIFT
- PXP_PRETEND_CMD_PORT_MASK
- PXP_PRETEND_CMD_PORT_SHIFT
- PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK
- PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT
- PXP_PRETEND_CMD_PRETEND_PATH_MASK
- PXP_PRETEND_CMD_PRETEND_PATH_SHIFT
- PXP_PRETEND_CMD_PRETEND_PORT_MASK
- PXP_PRETEND_CMD_PRETEND_PORT_SHIFT
- PXP_PRETEND_CMD_RESERVED0_MASK
- PXP_PRETEND_CMD_RESERVED0_SHIFT
- PXP_PRETEND_CMD_RESERVED1_MASK
- PXP_PRETEND_CMD_RESERVED1_SHIFT
- PXP_PRETEND_CMD_USE_PORT_MASK
- PXP_PRETEND_CMD_USE_PORT_SHIFT
- PXP_PRETEND_CONCRETE_FID_PFID_MASK
- PXP_PRETEND_CONCRETE_FID_PFID_SHIFT
- PXP_PRETEND_CONCRETE_FID_RESERVED_MASK
- PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT
- PXP_PRETEND_CONCRETE_FID_VFID_MASK
- PXP_PRETEND_CONCRETE_FID_VFID_SHIFT
- PXP_PRETEND_CONCRETE_FID_VFVALID_MASK
- PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT
- PXP_PTT_ENTRY_OFFSET_MASK
- PXP_PTT_ENTRY_OFFSET_SHIFT
- PXP_PTT_ENTRY_RESERVED0_MASK
- PXP_PTT_ENTRY_RESERVED0_SHIFT
- PXP_QUEUES_ZONE_MAX_NUM
- PXP_REG_HST_ARB_IS_IDLE
- PXP_REG_HST_CLIENTS_WAITING_TO_ARB
- PXP_REG_HST_DISCARD_DOORBELLS
- PXP_REG_HST_DISCARD_DOORBELLS_STATUS
- PXP_REG_HST_DISCARD_INTERNAL_WRITES
- PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS
- PXP_REG_HST_INBOUND_INT
- PXP_REG_HST_ZONE_PERMISSION_TABLE
- PXP_REG_PXP_INT_MASK_0
- PXP_REG_PXP_INT_MASK_1
- PXP_REG_PXP_INT_STS_0
- PXP_REG_PXP_INT_STS_1
- PXP_REG_PXP_INT_STS_CLR_0
- PXP_REG_PXP_INT_STS_CLR_1
- PXP_REG_PXP_PRTY_MASK
- PXP_REG_PXP_PRTY_STS
- PXP_REG_PXP_PRTY_STS_CLR
- PXP_VF_ADDR_CSDM_GLOBAL_END
- PXP_VF_ADDR_CSDM_GLOBAL_SIZE
- PXP_VF_ADDR_CSDM_GLOBAL_START
- PXP_VF_ADDR_DB_END
- PXP_VF_ADDR_DB_SIZE
- PXP_VF_ADDR_DB_START
- PXP_VF_ADDR_IGU_END
- PXP_VF_ADDR_IGU_SIZE
- PXP_VF_ADDR_IGU_START
- PXP_VF_ADDR_USDM_QUEUES_END
- PXP_VF_ADDR_USDM_QUEUES_SIZE
- PXP_VF_ADDR_USDM_QUEUES_START
- PXP_VF_BAR0
- PXP_VF_BAR0_DQ_LENGTH
- PXP_VF_BAR0_DQ_OPAQUE_OFFSET
- PXP_VF_BAR0_END_DQ
- PXP_VF_BAR0_END_GRC
- PXP_VF_BAR0_END_IGU
- PXP_VF_BAR0_END_IGU2
- PXP_VF_BAR0_END_MSDM_ZONE_B
- PXP_VF_BAR0_END_PSDM_ZONE_B
- PXP_VF_BAR0_END_SDM_ZONE_A
- PXP_VF_BAR0_END_TSDM_ZONE_B
- PXP_VF_BAR0_END_USDM_ZONE_B
- PXP_VF_BAR0_END_XSDM_ZONE_B
- PXP_VF_BAR0_END_YSDM_ZONE_B
- PXP_VF_BAR0_GRC_LENGTH
- PXP_VF_BAR0_GRC_WINDOW_LENGTH
- PXP_VF_BAR0_IGU2_LENGTH
- PXP_VF_BAR0_IGU_LENGTH
- PXP_VF_BAR0_ME_CONCRETE_ADDRESS
- PXP_VF_BAR0_ME_OPAQUE_ADDRESS
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B
- PXP_VF_BAR0_START_DQ
- PXP_VF_BAR0_START_GRC
- PXP_VF_BAR0_START_IGU
- PXP_VF_BAR0_START_IGU2
- PXP_VF_BAR0_START_MSDM_ZONE_B
- PXP_VF_BAR0_START_PSDM_ZONE_B
- PXP_VF_BAR0_START_SDM_ZONE_A
- PXP_VF_BAR0_START_TSDM_ZONE_B
- PXP_VF_BAR0_START_USDM_ZONE_B
- PXP_VF_BAR0_START_XSDM_ZONE_B
- PXP_VF_BAR0_START_YSDM_ZONE_B
- PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK
- PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT
- PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK
- PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT
- PXP_VF_ZONE_A_PERMISSION_VALID_MASK
- PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT
- PXP_VF_ZONE_A_PERMISSION_VFID_MASK
- PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT
- PXRC_PRODUCT_ID
- PXRC_VENDOR_ID
- PXSEG
- PXS_RCU
- PXVFREQ
- PXVFREQ_PX_MASK
- PXVFREQ_PX_SHIFT
- PXW
- PXWL
- PX_ANALOG_IN
- PX_ANALOG_OUT
- PX_BRDCFG0
- PX_BRDCFG0_DIU_MASK
- PX_BRDCFG0_DLINK
- PX_BRDCFG0_DVISEL
- PX_BRDCFG0_ELBC_DIU
- PX_BRDCFG0_ELBC_SPI_ELBC
- PX_BRDCFG0_ELBC_SPI_MASK
- PX_BRDCFG0_ELBC_SPI_NULL
- PX_BRDCFG1
- PX_BRDCFG1_BACKLIGHT
- PX_BRDCFG1_DDCEN
- PX_BRDCFG1_DFPEN
- PX_BRDCFG1_DVIEN
- PX_CFG_PXC200F
- PX_CON_BYTE_EN_BYTES
- PX_CON_BYTE_EN_MASK
- PX_CON_BYTE_EN_SHIFT
- PX_CON_SEND
- PX_CTL
- PX_CTL_ALTACC
- PX_DIGITAL_IN
- PX_DIGITAL_OUT
- PX_FLAG_PXC200A
- PX_I2C_CMD_CFG
- PX_I2C_PIC
- PX_MAX_PROTO
- PX_NUM
- PX_PROTO_OE
- PX_PROTO_OL2TP
- PX_PROTO_PPTP
- PX_PXC200A_CARDID
- PX_RX_POL
- PX_STA_BUFSTS
- PYRA_BIN_ATTRIBUTE_R
- PYRA_BIN_ATTRIBUTE_RW
- PYRA_BIN_ATTRIBUTE_W
- PYRA_COMMAND_B
- PYRA_COMMAND_CONTROL
- PYRA_COMMAND_INFO
- PYRA_COMMAND_PROFILE_BUTTONS
- PYRA_COMMAND_PROFILE_SETTINGS
- PYRA_COMMAND_SETTINGS
- PYRA_CONTROL_REQUEST_PROFILE_BUTTONS
- PYRA_CONTROL_REQUEST_PROFILE_SETTINGS
- PYRA_MOUSE_EVENT_AUDIO_TYPE_MUTE
- PYRA_MOUSE_EVENT_AUDIO_TYPE_VOLUME_DOWN
- PYRA_MOUSE_EVENT_AUDIO_TYPE_VOLUME_UP
- PYRA_MOUSE_EVENT_BUTTON_PRESS
- PYRA_MOUSE_EVENT_BUTTON_RELEASE
- PYRA_MOUSE_EVENT_BUTTON_TYPE_CPI
- PYRA_MOUSE_EVENT_BUTTON_TYPE_MACRO
- PYRA_MOUSE_EVENT_BUTTON_TYPE_MULTIMEDIA
- PYRA_MOUSE_EVENT_BUTTON_TYPE_PROFILE_1
- PYRA_MOUSE_EVENT_BUTTON_TYPE_PROFILE_2
- PYRA_MOUSE_EVENT_BUTTON_TYPE_QUICKLAUNCH
- PYRA_MOUSE_EVENT_BUTTON_TYPE_SENSITIVITY
- PYRA_MOUSE_EVENT_BUTTON_TYPE_SHORTCUT
- PYRA_MOUSE_EVENT_BUTTON_TYPE_TILT
- PYRA_MOUSE_REPORT_NUMBER_AUDIO
- PYRA_MOUSE_REPORT_NUMBER_BUTTON
- PYRA_MOUSE_REPORT_NUMBER_HID
- PYRA_SIZE_CONTROL
- PYRA_SIZE_INFO
- PYRA_SIZE_PROFILE_BUTTONS
- PYRA_SIZE_PROFILE_SETTINGS
- PYRA_SIZE_SETTINGS
- PYRA_SYSFS_R
- PYRA_SYSFS_RW
- PYRA_SYSFS_W
- PYXIS_DAC_OFFSET
- PYXIS_GPO
- PYXIS_IIC_CTRL
- PYXIS_INT_CNFG
- PYXIS_INT_HILO
- PYXIS_INT_MASK
- PYXIS_INT_REQ
- PYXIS_INT_ROUTE
- PYXIS_INT_TIME
- PYXIS_RESET
- PYXIS_RT_COUNT
- PYX_TRANSPORT_STATUS_INTERVAL
- PYX_TRANSPORT_WINDOW_CLOSED_THRESHOLD
- PYX_TRANSPORT_WINDOW_CLOSED_WAIT_LONG
- PYX_TRANSPORT_WINDOW_CLOSED_WAIT_SHORT
- PZ
- P_802_1P_CTRL
- P_ACK_IRQ
- P_ACK_IRQ_EN
- P_ALL
- P_ALLOW_PRX_FRONTEND_SHUTOFF
- P_ALLOW_UNDER_ALLOCATION_MASK
- P_ARRAY_SIZE
- P_ASIO_BUFFER_MANAGEMENT_MASK
- P_ASPM_A1_MODE_SELECT
- P_ASPM_CLKREQ_PAD_CTL
- P_ASPM_CLKRUN_REQUEST
- P_ASPM_CONTROL_MSK
- P_ASPM_FORCE_CLKREQ_ENA
- P_ASPM_GPHY_LINK_DOWN
- P_ASPM_INT_FIFO_EMPTY
- P_AUD_REF_CLK
- P_AUTH_CHALLENGE
- P_AUTH_RESPONSE
- P_AUTO_EOB
- P_AUTO_EOB_SEL_128
- P_AUTO_EOB_SEL_256
- P_AUTO_EOB_SEL_512
- P_AUTO_EOB_SEL_64
- P_AUTO_EOB_SEL_SHIFT
- P_BARRIER
- P_BARRIER_ACK
- P_BCAST_STORM_CTRL
- P_BECOME_SYNC_SOURCE
- P_BECOME_SYNC_TARGET
- P_BIAS_PLL
- P_BIAS_PLL_NSS_NOC
- P_BIMC
- P_BITMAP
- P_BI_TCXO
- P_BUSY_IRP
- P_BUSY_IRQ
- P_BUSY_IRQ_EN
- P_B_FRAME_QP
- P_CAM_CC_PLL0_OUT_EVEN
- P_CAM_CC_PLL1_OUT_EVEN
- P_CAM_CC_PLL2_OUT_EVEN
- P_CAM_CC_PLL3_OUT_EVEN
- P_CF1_DIS_REL_EVT_RST
- P_CF1_ENA_CFG_LDR_DONE
- P_CF1_ENA_TXBMU_RD_IDLE
- P_CF1_ENA_TXBMU_WR_IDLE
- P_CF1_GAT_LDR_NOT_FIN
- P_CF1_GAT_PCIE_RESET
- P_CF1_GAT_PCIE_RX_IDLE
- P_CF1_PCIE_RST_CLKREQ
- P_CF1_PRST_PHY_CLKREQ
- P_CF1_REL_LDR_NOT_FIN
- P_CF1_REL_PCIE_RESET
- P_CF1_REL_VMAIN_AVLBL
- P_CHOICE
- P_CLK_ASF_REGS_DIS
- P_CLK_COR_COMMON_DIS
- P_CLK_COR_LNK1_BIU_DIS
- P_CLK_COR_LNK1_BMU_DIS
- P_CLK_COR_LNK1_D0_DIS
- P_CLK_COR_LNK1_D3_DIS
- P_CLK_COR_LNK1_GM_DIS
- P_CLK_COR_REGS_D0_DIS
- P_CLK_COR_REGS_D3_DIS
- P_CLK_COR_YTB_ARB_DIS
- P_CLK_GATE_PEX_UNIT_ENA
- P_CLK_GATE_ROOT_COR_ENA
- P_CLK_MACSEC_DIS
- P_CLK_MAC_LNK1_D0_DIS
- P_CLK_MAC_LNK1_D3_DIS
- P_CLK_PCI_COMMON_DIS
- P_CLK_PCI_LNK1_BIU_DIS
- P_CLK_PCI_LNK1_BMU_DIS
- P_CLK_PCI_MST_ARB_DIS
- P_CLK_PCI_REGS_D0_DIS
- P_CLK_PCI_REGS_D3_DIS
- P_CLK_REF_LNK1_GM_DIS
- P_CMD
- P_COMMENT
- P_COMPRESSED_BITMAP
- P_CONNECTION_FEATURES
- P_CONN_ST_CHG_REPLY
- P_CONN_ST_CHG_REQ
- P_CORE_BI_PLL_TEST_SE
- P_CSUM_RS_REQUEST
- P_CTL_BYPASS_VMAIN_AV
- P_CTL_DIV_CORE_CLK_ENA
- P_CTL_SRESET_VMAIN_AV
- P_CTL_TIM_VMAIN_AV_MSK
- P_CXO
- P_DATA
- P_DATAI
- P_DATAO
- P_DATA_MODE_MASK
- P_DATA_REPLY
- P_DATA_REQUEST
- P_DDRPLL
- P_DDRPLLAPSS
- P_DEFAULT
- P_DEFAULT_IRQS_EN
- P_DELAY_PROBE
- P_DIRECTION
- P_DISP_CC_PLL0_OUT_MAIN
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK
- P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK
- P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT
- P_DOWN
- P_DO_NOT_RESET_ANALOG_LEVELS
- P_DROP_TAG_CTRL
- P_DSI0PLL
- P_DSI0PLL_BYTE
- P_DSI0_PHYPLL_BYTE
- P_DSI0_PHYPLL_DSI
- P_DSI0_PHY_PLL_OUT_BYTECLK
- P_DSI0_PHY_PLL_OUT_DSICLK
- P_DSI1PLL
- P_DSI1PLL_BYTE
- P_DSI1_PHY_PLL_OUT_BYTECLK
- P_DSI1_PHY_PLL_OUT_DSICLK
- P_DSI1_PLL_BYTECLK
- P_DSI1_PLL_DSICLK
- P_DSI2_PLL_BYTECLK
- P_DSI2_PLL_DSICLK
- P_DS_IRQ
- P_DS_IRQ_EN
- P_EDPLINK
- P_EDPVCO
- P_EN
- P_ENERGY_OFF_IRQ
- P_ENERGY_ON_IRQ
- P_ERR_EN
- P_ERR_IRP
- P_ERR_IRQ
- P_ERR_IRQ_EN
- P_EXT_MCLK
- P_EXT_PRI_I2S
- P_EXT_SEC_I2S
- P_FENCING
- P_FEPLL125DLY
- P_FEPLL200
- P_FEPLL500
- P_FEPLLWCSS2G
- P_FEPLLWCSS5G
- P_FLAG
- P_FORCE_ASPM_REQUEST
- P_FORCE_CTRL
- P_FRAME
- P_FUTEX_OP
- P_FW
- P_GAT_CLKRUN_REQ_REL
- P_GAT_GPHY_LINK_DOWN
- P_GAT_GPHY_N_REC_PACKET
- P_GAT_INT_FIFO_EMPTY
- P_GAT_LOADER_FINISHED
- P_GAT_MAIN_PWR_N_AVAIL
- P_GAT_PCIE_ENTER_L1_ST
- P_GAT_PCIE_RESET_ASS
- P_GAT_PCIE_RST_ASSERTED
- P_GAT_PCIE_RX_EL_IDLE
- P_GAT_PME_DE_ASSERTED
- P_GPHY_IRQ
- P_GPLL0
- P_GPLL0_AUX
- P_GPLL0_DIV
- P_GPLL0_DIV2
- P_GPLL0_EARLY_DIV
- P_GPLL0_OUT_AUX
- P_GPLL0_OUT_EVEN
- P_GPLL0_OUT_MAIN
- P_GPLL0_OUT_MAIN_DIV
- P_GPLL1
- P_GPLL1_AUX
- P_GPLL1_EARLY_DIV
- P_GPLL1_OUT_MAIN
- P_GPLL2
- P_GPLL2_AUX
- P_GPLL2_EARLY
- P_GPLL3
- P_GPLL3_OUT_MAIN
- P_GPLL4
- P_GPLL4_OUT_AUX
- P_GPLL4_OUT_MAIN
- P_GPLL6
- P_GPLL6_OUT_AUX
- P_GPLL7_OUT_MAIN
- P_GPLL9_OUT_MAIN
- P_GPU_CC_PLL1_OUT_EVEN
- P_GPU_CC_PLL1_OUT_MAIN
- P_GPU_CC_PLL1_OUT_ODD
- P_HCR_DDS
- P_HCR_DSW
- P_HCR_TEST
- P_HDMIPLL
- P_HDMI_PHY_PLL_CLK
- P_HDMI_PLL
- P_ID_AMD_EXT
- P_ID_AMD_STD
- P_ID_INTEL_DATA
- P_ID_INTEL_EXT
- P_ID_INTEL_PERFORMANCE
- P_ID_INTEL_STD
- P_ID_MITSUBISHI_EXT
- P_ID_MITSUBISHI_STD
- P_ID_NONE
- P_ID_RESERVED
- P_ID_SST_OLD
- P_ID_SST_PAGE
- P_ID_ST_ADV
- P_ID_WINBOND
- P_IGNORE_EDB_ERR
- P_IMPLY
- P_INC
- P_INCONSISTENT
- P_INITIAL_DATA
- P_INITIAL_META
- P_INS_SRC_PVID_CTRL
- P_IRQ
- P_IRQ_MASK
- P_IRQ_MSK
- P_IRQ_OFF
- P_IR_ERR
- P_IR_PE
- P_IR_SLCT
- P_LINK_DOWN_IRQ
- P_LINK_STATUS
- P_LINK_UP_IRQ
- P_LOCAL_CTRL
- P_LOCK_GROUP_MASK
- P_LOCK_GROUP_SHIFT
- P_MASK
- P_MAX
- P_MAX_OPT_CMD
- P_MAY_IGNORE
- P_MENU
- P_MIN
- P_MIRROR_CTRL
- P_MMAP_PROT
- P_MMPLL0
- P_MMPLL1
- P_MMPLL2
- P_MMPLL3
- P_MMPLL4
- P_MMPLL5
- P_MMPLL8
- P_MMPLL9
- P_MMSLEEP
- P_MODE
- P_MREMAP_FLAG
- P_MSGI
- P_MSGO
- P_MSG_FLAG
- P_NEG_ACK
- P_NEG_DREPLY
- P_NEG_RESTART_CTRL
- P_NEG_RS_DREPLY
- P_NSS_CRYPTO_PLL
- P_NUM_IRQ
- P_OCR_ACK_DSEL
- P_OCR_ACK_OP
- P_OCR_BUSY_DSEL
- P_OCR_BUSY_OP
- P_OCR_DATA_SRC
- P_OCR_DS_DSEL
- P_OCR_EN_DIAG
- P_OCR_EN_VER
- P_OCR_IDLE
- P_OCR_MEM_CLR
- P_OCR_SRST
- P_OCR_V_ILCK
- P_OP
- P_OPTION
- P_OR
- P_OR_AFXN
- P_OR_INIT
- P_OR_SLCT_IN
- P_OR_V1
- P_OR_V2
- P_OR_V3
- P_OUTDATED
- P_OUT_OF_DESC_EN
- P_OUT_OF_SYNC
- P_OV_REPLY
- P_OV_REQUEST
- P_OV_RESULT
- P_PASS_ALL_CTRL
- P_PCIE20_PHY0_PIPE
- P_PCIE20_PHY1_PIPE
- P_PCIE_0_1_PIPE_CLK
- P_PCIE_0_PIPE_CLK
- P_PEX_LTSSM_DET_STAT
- P_PEX_LTSSM_L1_STAT
- P_PEX_LTSSM_STAT
- P_PEX_LTSSM_STAT_MSK
- P_PE_IRP
- P_PE_IRQ
- P_PE_IRQ_EN
- P_PGID
- P_PHY_CTRL
- P_PID
- P_PIDFD
- P_PING
- P_PING_ACK
- P_PLL0
- P_PLL0_EARLY_DIV_CLK_SRC
- P_PLL14
- P_PLL15
- P_PLL18
- P_PLL2
- P_PLL3
- P_PLL4
- P_PLL8
- P_PLL_BUF_PDNB
- P_PLL_PDNB
- P_PLL_PWRDN_IN_L1L23
- P_POLICY_FLAG
- P_PRCSD_DESC_EN
- P_PREFETCH_LIMIT_16
- P_PREFETCH_LIMIT_32
- P_PREFETCH_LIMIT_4
- P_PREFETCH_LIMIT_SHIFT
- P_PREPARE_FOR_MPEG3_MASK
- P_PRIMARY
- P_PRIO_CTRL
- P_PROMPT
- P_PROTOCOL
- P_PROTOCOL_UPDATE
- P_PXO
- P_RANGE
- P_RATE_LIMIT_CTRL
- P_RECV_ACK
- P_REL_CLKRUN_REQ_REL
- P_REL_GPHY_LINK_UP
- P_REL_GPHY_REC_PACKET
- P_REL_INT_FIFO_N_EMPTY
- P_REL_LOADER_NOT_FIN
- P_REL_MAIN_PWR_AVAIL
- P_REL_PCIE_EXIT_L1_ST
- P_REL_PCIE_RESET_ASS
- P_REL_PCIE_RST_DE_ASS
- P_REL_PCIE_RX_EX_IDLE
- P_REL_PME_ASSERTED
- P_REMOTE_STATUS
- P_RETRY_WRITE
- P_RS_CANCEL
- P_RS_DATA_REPLY
- P_RS_DATA_REQUEST
- P_RS_DEALLOCATED
- P_RS_IS_IN_SYNC
- P_RS_THIN_REQ
- P_RS_WRITE_ACK
- P_SATA_ASIC0_CLK
- P_SATA_RX_CLK
- P_SCHEDSTAT
- P_SECCOMP_SET_MODE_OP
- P_SELECT
- P_SIGNUM
- P_SIZE
- P_SIZES
- P_SK_FLAG
- P_SK_TYPE
- P_SLCT_IRP
- P_SLCT_IRQ
- P_SLCT_IRQ_EN
- P_SLEEP_CLK
- P_SPEED_STATUS
- P_STATE
- P_STATE_CHG_REPLY
- P_STATE_CHG_REQ
- P_STATE_TRANSITION_CAPABLE
- P_STATUS
- P_STP_CTRL
- P_SUPERSEDED
- P_SW_OFSTS_MASK
- P_SYMBOL
- P_SYNC_PARAM
- P_SYNC_PARAM89
- P_SYNC_UUID
- P_SYS_MODE
- P_SYS_STRM
- P_TAG_CTRL
- P_TCR_ACK
- P_TCR_BUSY
- P_TCR_DIR
- P_TCR_DS
- P_TIMER_EN
- P_TIMER_VALUE_MSK
- P_TRIM
- P_TRNSFR_END_EN
- P_TST_J
- P_TST_K
- P_TST_NORMAL
- P_TST_PACKET
- P_TST_SE0_NAK
- P_TXQ_PSM_VDD
- P_TXQ_PSM_VDD_MASK
- P_TXQ_PSM_VDD_SHIFT
- P_UBI32_PLL
- P_UNDERRUN_SKIP_SOUND_MASK
- P_UNIPHY0_RX
- P_UNIPHY0_TX
- P_UNIPHY1_RX
- P_UNIPHY1_TX
- P_UNIPHY2_RX
- P_UNIPHY2_TX
- P_UNKNOWN
- P_UNPLUG_REMOTE
- P_USB3PHY_0_PIPE
- P_USB3PHY_1_PIPE
- P_UUIDS
- P_VIDEO_PLL0_OUT_EVEN
- P_VIDEO_PLL0_OUT_MAIN
- P_VIDEO_PLL0_OUT_ODD
- P_WAKE_EN
- P_WRITE_ACK
- P_WRITE_NWD
- P_WSAME
- P_XO
- P_ZEROES
- P_ns
- PaceMsaAccess
- PadEnable
- PageA1_in
- PageA1_out
- PageA2_in
- PageA2_out
- PageAdrs
- PageAnon
- PageCompound
- PageDoubleMap
- PageFileIo
- PageFsCache
- PageHeadHuge
- PageHighMem
- PageHuge
- PageHugeObject
- PageHugeTemporary
- PageKsm
- PageMappingFlags
- PageMovable
- PageNum
- PageNum_128
- PageNum_256
- PageNum_512
- PagePoisoned
- PageSlab
- PageTable
- PageTail
- PageTransCompound
- PageTransCompoundMap
- PageTransHuge
- PageTransTail
- PageType
- Page_Invalidate_T
- Page_dcache_dirty
- Page_mask
- Page_rxb
- Page_size
- Page_txb
- Pal1Bit
- Pal2Bit
- Pal4Bit
- Pal8Bit
- PalmPixDC85
- Panel300_1024x600
- Panel300_1024x768
- Panel300_1152x768
- Panel300_1280x1024
- Panel300_1280x768
- Panel300_1280x960
- Panel300_640x480
- Panel300_800x600
- Panel300_Barco1366
- Panel300_Custom
- Panel310_1024x600
- Panel310_1024x768
- Panel310_1152x768
- Panel310_1152x864
- Panel310_1280x1024
- Panel310_1280x768
- Panel310_1280x960
- Panel310_1400x1050
- Panel310_1600x1200
- Panel310_320x240_1
- Panel310_320x240_2
- Panel310_320x240_3
- Panel310_640x480
- Panel310_800x600
- Panel310_Custom
- Panel661_1024x600
- Panel661_1024x768
- Panel661_1152x864
- Panel661_1280x1024
- Panel661_1280x720
- Panel661_1280x768
- Panel661_1280x800
- Panel661_1280x854
- Panel661_1280x960
- Panel661_1400x1050
- Panel661_1600x1200
- Panel661_1680x1050
- Panel661_640x480
- Panel661_800x600
- Panel661_Custom
- Panel_1024x600
- Panel_1024x768
- Panel_1152x768
- Panel_1152x864
- Panel_1280x1024
- Panel_1280x720
- Panel_1280x768
- Panel_1280x768_2
- Panel_1280x768_3
- Panel_1280x800
- Panel_1280x800_2
- Panel_1280x854
- Panel_1280x960
- Panel_1400x1050
- Panel_1600x1200
- Panel_1680x1050
- Panel_320x240_1
- Panel_320x240_2
- Panel_320x240_3
- Panel_640x480
- Panel_800x600
- Panel_848x480
- Panel_856x480
- Panel_Barco1366
- Panel_Custom
- ParallelController
- ParameterData
- Parent
- ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK
- ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT
- ParityCorr_ACTION_CONTROL__IntrGenSel_MASK
- ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT
- ParityCorr_ACTION_CONTROL__LinkDis_En_MASK
- ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT
- ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK
- ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT
- ParityErr
- ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK
- ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- ParityFatal_ACTION_CONTROL__IntrGenSel_MASK
- ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- ParityFatal_ACTION_CONTROL__LinkDis_En_MASK
- ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK
- ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK
- ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT
- ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK
- ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT
- ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK
- ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT
- ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK
- ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT
- ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK
- ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT
- ParitySerr_ACTION_CONTROL__IntrGenSel_MASK
- ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT
- ParitySerr_ACTION_CONTROL__LinkDis_En_MASK
- ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT
- ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK
- ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT
- Parmfield
- ParseFailed
- ParseOK
- ParseQualifiedString
- ParseRes
- ParseUnknown
- PartitionBlock
- PatchCR
- PathA
- PathB
- PathC
- PathConfigure
- PathD
- Pause
- PauseCmd
- PauseFrame
- Pb
- PciErr
- Pelif
- Pelse
- Pendif
- PerfCounter_Vals
- PerfFilterTable
- PerfectFilter
- PerfectFilterVlan
- PerformComparison
- PerformFIX
- PerformFLT
- PerformLDF
- PerformLFM
- PerformSFM
- PerformSTF
- Performance
- PeripheralClass
- PersistentData_t
- PersistentPhysicalId_t
- Pfalse_ALARM_STATISTICS
- Phase
- PhaseTableAddr
- PhaseTableSize
- PhyAddr
- PhyAddrMask
- PhyCtrl
- PhyCtrlAne
- PhyCtrlDux
- PhyCtrlPhyBaseAddr
- PhyCtrlReset
- PhyCtrlSpd10
- PhyCtrlSpd100
- PhyCtrl_bits
- PhyCtrlconfigbits
- PhyData
- PhyDataR
- PhyEvent175
- PhyMedia
- PhyPkt
- PhyStatus
- Phy_Mib_Type
- PhysAddr01
- PhysAddr23
- PhysAddr45
- PhysDevAddr
- PhysDevAddr_struct
- PidData
- PingCount_Reg
- PioctlData
- Pipe
- PipeCloseReason
- PipeCmdCode
- PipeConfig
- PipeErrors
- PipeFlagsBits
- PipeInterleaveSize
- PipePollFlags
- PipeRegs
- PipeTiling
- PipeWakeFlags
- PitRegsPtr
- PitRegs_t
- Pixclkdiv_Pd
- PixelBusReg
- PixelClockAdjustmentForProgressiveToInterlaceUnit
- PixelPipeCounterId
- PixelPipeStride
- PkrMap
- PkrXsel
- PkrXsel2
- PkrYsel
- PktCntrDisable
- PktRejected
- PktRxOk
- PktStatus
- PktTooLong
- PktTxed
- PlatformEFIORead1Byte
- PlatformEFIORead2Byte
- PlatformEFIORead4Byte
- PlatformEFIOWrite1Byte
- PlatformEFIOWrite2Byte
- PlatformEFIOWrite4Byte
- PlayModeSelector
- Please
- PllSetting_t
- PmDoorBellResponseSent
- PnALPHAR
- PnALPHAR_ABIT_0
- PnALPHAR_ABIT_1
- PnALPHAR_ABIT_X
- PnBTR
- PnDDCR
- PnDDCR2
- PnDDCR2_CODE
- PnDDCR2_DIVU
- PnDDCR2_DIVY
- PnDDCR2_NV21
- PnDDCR2_Y420
- PnDDCR4
- PnDDCR4_CODE
- PnDDCR4_EDF_ARGB8888
- PnDDCR4_EDF_MASK
- PnDDCR4_EDF_NONE
- PnDDCR4_EDF_RGB666
- PnDDCR4_EDF_RGB888
- PnDDCR4_SDFS_MASK
- PnDDCR4_SDFS_RGB
- PnDDCR4_SDFS_YC
- PnDDCR4_VSPS
- PnDDCR_CODE
- PnDDCR_LRGB0
- PnDDCR_LRGB1
- PnDPXR
- PnDPYR
- PnDSA0R
- PnDSA1R
- PnDSA2R
- PnDSA_MASK
- PnDSXR
- PnDSYR
- PnMLR
- PnMR
- PnMR_BM_AD
- PnMR_BM_AR
- PnMR_BM_MD
- PnMR_BM_VC
- PnMR_CPSL_CP1
- PnMR_CPSL_CP2
- PnMR_CPSL_CP3
- PnMR_CPSL_CP4
- PnMR_DC
- PnMR_DDDF_16BPP
- PnMR_DDDF_8BPP
- PnMR_DDDF_ARGB
- PnMR_DDDF_MASK
- PnMR_DDDF_YC
- PnMR_SPIM_ALP
- PnMR_SPIM_EOR
- PnMR_SPIM_TP
- PnMR_SPIM_TP_OFF
- PnMR_TC_CP
- PnMR_TC_R
- PnMR_VISL_VIN0
- PnMR_VISL_VIN1
- PnMR_VISL_VIN2
- PnMR_VISL_VIN3
- PnMR_WAE
- PnMR_YCDF_YUYV
- PnMWR
- PnSPXR
- PnSPYR
- PnSWAPR
- PnSWAPR_DIGN
- PnSWAPR_SPBY
- PnSWAPR_SPLW
- PnSWAPR_SPQW
- PnSWAPR_SPWD
- PnTC1R
- PnTC2R
- PnTC3R
- PnTC3R_CODE
- PnWAMWR
- PnWASPR
- Pnco01
- Pnco02
- Pnco03
- PofFileHdr_tag
- PofRecHdr_tag
- PofTimeStamp_tag
- PointerController
- PointerPeripheral
- Poly3rdOrderCoeff
- PortAddr
- PortEnableReply_t
- PortEnable_t
- PortFactsReply_t
- PortFacts_t
- Pos
- Post01
- PowerAuto
- PowerCalculatorData_t
- PowerDown
- PowerGatingMode_e
- PowerGatingSettings_e
- PowerScan
- PowerScanInit
- PowerStatus
- PowerUp
- Power_Calculator_Data
- Power_Mgnt
- Power_Sharing_t
- PptpCallDisconnectNotify
- PptpClearCallRequest
- PptpControlHeader
- PptpEchoReply
- PptpEchoRequest
- PptpInCallConnected
- PptpInCallReply
- PptpInCallRequest
- PptpOutCallReply
- PptpOutCallRequest
- PptpSetLinkInfo
- PptpStartSessionReply
- PptpStartSessionRequest
- PptpStopSessionReply
- PptpStopSessionRequest
- PptpWanErrorNotify
- Pr
- Pre01
- PreEndControl
- PreEndFetch
- PreVBlankGap
- Pref_Load
- Pref_LoadRetained
- Pref_LoadStreamed
- Pref_PrepareForStore
- Pref_Store
- Pref_StoreRetained
- Pref_StoreStreamed
- Pref_WriteBackInvalidate
- Prefix
- PrimaryDCache
- PrimaryICache
- PrimeIocFifos
- PrintRegisters
- PrinterPeripheral
- PrintfDone
- PrintfReady
- PriorityCommandReceivedReply_t
- Priv
- PrivUD
- Pro_CMDParm
- Pro_CatagoryReg
- Pro_ClassReg
- Pro_DataAddr0
- Pro_DataAddr1
- Pro_DataAddr2
- Pro_DataAddr3
- Pro_DataCount0
- Pro_DataCount1
- Pro_IFModeReg
- Pro_IntReg
- Pro_StatusReg
- Pro_SystemParm
- Pro_TPCParm
- Pro_TypeReg
- ProcessEventNotification
- ProcessorArchitecture
- ProcessorClass
- ProgramClock
- ProgramFileID
- ProgrammingCRT2
- Progress_UUIE
- Progress_UUIE_fastStart
- Proscope
- Prot
- ProtA1_in
- ProtA1_out
- ProtA2_in
- ProtA2_out
- Protection
- PulseSpace
- PutByte
- PutWord
- Pw_Track_Flag
- PwcfgSet
- PwrConfig_e
- PwrcsrClr
- PwrcsrClr1
- PwrcsrSet
- PwrcsrSet1
- PxD_FLAG_ATTACHED
- PxD_FLAG_MASK
- PxD_FLAG_PRESENT
- PxD_FLAG_SHIFT
- PxD_FLAG_VALID
- PxD_VALUE_SHIFT
- PyInit_perf_trace_context
- PyVarObject_HEAD_INIT
- Py_TYPE
[..]