[..]
- O
- O0
- O1
- O2
- O2CB_MAP_STABILIZE_COUNT
- O2CLUSTER_HEARTBEAT_H
- O2CLUSTER_MASKLOG_H
- O2CLUSTER_NODEMANAGER_H
- O2CLUSTER_QUORUM_H
- O2CLUSTER_SYS_H
- O2CLUSTER_TCP_H
- O2CLUSTER_TCP_INTERNAL_H
- O2HB_CB_MAGIC
- O2HB_DB_TYPE_FAILEDREGIONS
- O2HB_DB_TYPE_LIVENODES
- O2HB_DB_TYPE_LIVEREGIONS
- O2HB_DB_TYPE_QUORUMREGIONS
- O2HB_DB_TYPE_REGION_ELAPSED_TIME
- O2HB_DB_TYPE_REGION_LIVENODES
- O2HB_DB_TYPE_REGION_NUMBER
- O2HB_DB_TYPE_REGION_PINNED
- O2HB_DEBUG_DIR
- O2HB_DEBUG_FAILEDREGIONS
- O2HB_DEBUG_LIVENODES
- O2HB_DEBUG_LIVEREGIONS
- O2HB_DEBUG_QUORUMREGIONS
- O2HB_DEBUG_REGION_ELAPSED_TIME
- O2HB_DEBUG_REGION_NUMBER
- O2HB_DEBUG_REGION_PINNED
- O2HB_DEFAULT_BLOCK_BITS
- O2HB_DEFAULT_DEAD_THRESHOLD
- O2HB_HEARTBEAT_GLOBAL
- O2HB_HEARTBEAT_LOCAL
- O2HB_HEARTBEAT_NUM_MODES
- O2HB_LIVE_THRESHOLD
- O2HB_MAX_REGION_NAME_LEN
- O2HB_MAX_WRITE_TIMEOUT_MS
- O2HB_MIN_DEAD_THRESHOLD
- O2HB_NEGO_APPROVE_MSG
- O2HB_NEGO_TIMEOUT_MS
- O2HB_NEGO_TIMEOUT_MSG
- O2HB_NODE_DOWN_CB
- O2HB_NODE_UP_CB
- O2HB_NUM_CB
- O2HB_PIN_CUT_OFF
- O2HB_REGION_TIMEOUT_MS
- O2NET_DEBUG_DIR
- O2NET_DRIVER_READY
- O2NET_DRIVER_UNINITED
- O2NET_ERR_DIED
- O2NET_ERR_MAX
- O2NET_ERR_NONE
- O2NET_ERR_NO_HNDLR
- O2NET_ERR_OVERFLOW
- O2NET_HB_PRI
- O2NET_IDLE_TIMEOUT_MS_DEFAULT
- O2NET_KEEPALIVE_DELAY_MS_DEFAULT
- O2NET_MAX_PAYLOAD_BYTES
- O2NET_MSG_KEEP_REQ_MAGIC
- O2NET_MSG_KEEP_RESP_MAGIC
- O2NET_MSG_MAGIC
- O2NET_MSG_STATUS_MAGIC
- O2NET_PROTOCOL_VERSION
- O2NET_QUORUM_DELAY_MS
- O2NET_RECONNECT_DELAY_MS_DEFAULT
- O2NET_STATS_STR_VERSION
- O2NET_TCP_USER_TIMEOUT
- O2NM_API_VERSION
- O2NM_FENCE_METHODS
- O2NM_FENCE_PANIC
- O2NM_FENCE_RESET
- O2NM_INVALID_NODE_NUM
- O2NM_MAX_NAME_LEN
- O2NM_MAX_NODES
- O2NM_MAX_REGIONS
- O2NM_NODE_ATTR_ADDRESS
- O2NM_NODE_ATTR_NUM
- O2NM_NODE_ATTR_PORT
- O2_DLL_LOCK_STATUS
- O2_FIFO_BUFFER
- O2_FIFO_ENA
- O2_FIFO_PCI_FIFO
- O2_FIFO_POSTWR
- O2_FIFO_ZVIDEO_3
- O2_MHPG_CHANNEL
- O2_MHPG_CINT_ENA
- O2_MHPG_CSC_ENA
- O2_MHPG_DMA
- O2_MODE_A
- O2_MODE_A_2
- O2_MODE_A_CD_PULSE
- O2_MODE_A_HOST_SUSP
- O2_MODE_A_PWR_MASK
- O2_MODE_A_QUIET
- O2_MODE_A_SUSP_EDGE
- O2_MODE_B
- O2_MODE_B_2
- O2_MODE_B_IDENT
- O2_MODE_B_ID_BSTEP
- O2_MODE_B_ID_CSTEP
- O2_MODE_B_ID_O2
- O2_MODE_B_IRQ15_RI
- O2_MODE_B_VS1
- O2_MODE_B_VS2
- O2_MODE_C
- O2_MODE_C_DREQ_BVD2
- O2_MODE_C_DREQ_INPACK
- O2_MODE_C_DREQ_MASK
- O2_MODE_C_DREQ_WP
- O2_MODE_C_IREQ_SEL
- O2_MODE_C_MGMT_SEL
- O2_MODE_C_ZVIDEO
- O2_MODE_D
- O2_MODE_D_CB_CLKRUN
- O2_MODE_D_IRQ_MODE
- O2_MODE_D_ISA_IRQ
- O2_MODE_D_PCI_CLKRUN
- O2_MODE_D_PCI_FIFO
- O2_MODE_D_SKT_ACTV
- O2_MODE_D_W97_IRQ
- O2_MODE_E
- O2_MODE_E_LED_OUT
- O2_MODE_E_MHPG_DMA
- O2_MODE_E_SKTA_ACTV
- O2_MODE_E_SPKR_OUT
- O2_MUX_AUX_VCC_3V
- O2_MUX_CONTROL
- O2_MUX_PCI_VCC_5V
- O2_MUX_PME_MUX
- O2_MUX_RING_OUT
- O2_MUX_SCTA_ACTV_ENA
- O2_MUX_SCTB_ACTV_ENA
- O2_MUX_SER_IRQ_ROUTE
- O2_MUX_SER_PCI
- O2_MUX_SKTA_TURBO
- O2_MUX_SKTB_ACTV
- O2_MUX_SKTB_TURBO
- O2_PLL_DLL_WDT_CONTROL1
- O2_PLL_FORCE_ACTIVE
- O2_PLL_LOCK_STATUS
- O2_PLL_SOFT_RESET
- O2_RESERVED1
- O2_RESERVED2
- O2_RES_READ_PREFETCH
- O2_RES_WRITE_BURST
- O2_SD_ADMA1
- O2_SD_ADMA2
- O2_SD_CAPS
- O2_SD_CAP_REG0
- O2_SD_CAP_REG2
- O2_SD_CLKREQ
- O2_SD_CLK_SETTING
- O2_SD_DELAY_CTRL
- O2_SD_DETECT_SETTING
- O2_SD_DEV_CTRL
- O2_SD_FREG0_LEDOFF
- O2_SD_FREG4_ENABLE_CLK_SET
- O2_SD_FUNC_REG0
- O2_SD_FUNC_REG3
- O2_SD_FUNC_REG4
- O2_SD_HW_TUNING_DISABLE
- O2_SD_INF_MOD
- O2_SD_LD0_CTRL
- O2_SD_LED_ENABLE
- O2_SD_LOCK_WP
- O2_SD_MISC_CTRL4
- O2_SD_MISC_REG5
- O2_SD_MISC_SETTING
- O2_SD_MULTI_VCC3V
- O2_SD_PLL_SETTING
- O2_SD_TEST_REG
- O2_SD_TUNING_CTRL
- O2_SD_UHS1_CAP_SETTING
- O2_SD_UHS2_L1_CTRL
- O2_SD_VENDOR_SETTING
- O2_SD_VENDOR_SETTING2
- O3
- O32_ARGC
- O32_ARGSZ
- O32_FRAMESZ
- O32_NFRAMESZ
- O32_SPSZ
- O32_STATC
- O32_STATSZ
- O32_STK
- O32_SZREG
- O4
- O5
- O7
- O9
- OABUFFER_SIZE_128K
- OABUFFER_SIZE_16M
- OABUFFER_SIZE_1M
- OABUFFER_SIZE_256K
- OABUFFER_SIZE_2M
- OABUFFER_SIZE_4M
- OABUFFER_SIZE_512K
- OABUFFER_SIZE_8M
- OACEC0_0
- OACEC0_1
- OACEC1_0
- OACEC1_1
- OACEC2_0
- OACEC2_1
- OACEC3_0
- OACEC3_1
- OACEC4_0
- OACEC4_1
- OACEC5_0
- OACEC5_1
- OACEC6_0
- OACEC6_1
- OACEC7_0
- OACEC7_1
- OACEC_COMPARE_ANY_EQUAL
- OACEC_COMPARE_EQUAL
- OACEC_COMPARE_GREATER_OR_EQUAL
- OACEC_COMPARE_GREATER_THAN
- OACEC_COMPARE_LESS_OR_EQUAL
- OACEC_COMPARE_LESS_THAN
- OACEC_COMPARE_NOT_EQUAL
- OACEC_COMPARE_VALUE_MASK
- OACEC_COMPARE_VALUE_SHIFT
- OACEC_CONSIDERATIONS_MASK
- OACEC_CONSIDERATIONS_SHIFT
- OACEC_MASK_MASK
- OACEC_SELECT_BOOLEAN
- OACEC_SELECT_NOA
- OACEC_SELECT_PREV
- OAL_CONT_ENTRY
- OAL_LAST_ENTRY
- OAM_GID
- OAR
- OAREPORTTRIG1
- OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK
- OAREPORTTRIG1_THRESHOLD_MASK
- OAREPORTTRIG2
- OAREPORTTRIG2_INVERT_A_0
- OAREPORTTRIG2_INVERT_A_1
- OAREPORTTRIG2_INVERT_A_10
- OAREPORTTRIG2_INVERT_A_11
- OAREPORTTRIG2_INVERT_A_12
- OAREPORTTRIG2_INVERT_A_13
- OAREPORTTRIG2_INVERT_A_14
- OAREPORTTRIG2_INVERT_A_15
- OAREPORTTRIG2_INVERT_A_2
- OAREPORTTRIG2_INVERT_A_3
- OAREPORTTRIG2_INVERT_A_4
- OAREPORTTRIG2_INVERT_A_5
- OAREPORTTRIG2_INVERT_A_6
- OAREPORTTRIG2_INVERT_A_7
- OAREPORTTRIG2_INVERT_A_8
- OAREPORTTRIG2_INVERT_A_9
- OAREPORTTRIG2_INVERT_B_0
- OAREPORTTRIG2_INVERT_B_1
- OAREPORTTRIG2_INVERT_B_2
- OAREPORTTRIG2_INVERT_B_3
- OAREPORTTRIG2_INVERT_C_0
- OAREPORTTRIG2_INVERT_C_1
- OAREPORTTRIG2_INVERT_D_0
- OAREPORTTRIG2_REPORT_TRIGGER_ENABLE
- OAREPORTTRIG2_THRESHOLD_ENABLE
- OAREPORTTRIG3
- OAREPORTTRIG3_NOA_SELECT_10_SHIFT
- OAREPORTTRIG3_NOA_SELECT_11_SHIFT
- OAREPORTTRIG3_NOA_SELECT_12_SHIFT
- OAREPORTTRIG3_NOA_SELECT_13_SHIFT
- OAREPORTTRIG3_NOA_SELECT_14_SHIFT
- OAREPORTTRIG3_NOA_SELECT_15_SHIFT
- OAREPORTTRIG3_NOA_SELECT_8_SHIFT
- OAREPORTTRIG3_NOA_SELECT_9_SHIFT
- OAREPORTTRIG3_NOA_SELECT_MASK
- OAREPORTTRIG4
- OAREPORTTRIG4_NOA_SELECT_0_SHIFT
- OAREPORTTRIG4_NOA_SELECT_1_SHIFT
- OAREPORTTRIG4_NOA_SELECT_2_SHIFT
- OAREPORTTRIG4_NOA_SELECT_3_SHIFT
- OAREPORTTRIG4_NOA_SELECT_4_SHIFT
- OAREPORTTRIG4_NOA_SELECT_5_SHIFT
- OAREPORTTRIG4_NOA_SELECT_6_SHIFT
- OAREPORTTRIG4_NOA_SELECT_7_SHIFT
- OAREPORTTRIG4_NOA_SELECT_MASK
- OAREPORTTRIG5
- OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK
- OAREPORTTRIG5_THRESHOLD_MASK
- OAREPORTTRIG6
- OAREPORTTRIG6_INVERT_A_0
- OAREPORTTRIG6_INVERT_A_1
- OAREPORTTRIG6_INVERT_A_10
- OAREPORTTRIG6_INVERT_A_11
- OAREPORTTRIG6_INVERT_A_12
- OAREPORTTRIG6_INVERT_A_13
- OAREPORTTRIG6_INVERT_A_14
- OAREPORTTRIG6_INVERT_A_15
- OAREPORTTRIG6_INVERT_A_2
- OAREPORTTRIG6_INVERT_A_3
- OAREPORTTRIG6_INVERT_A_4
- OAREPORTTRIG6_INVERT_A_5
- OAREPORTTRIG6_INVERT_A_6
- OAREPORTTRIG6_INVERT_A_7
- OAREPORTTRIG6_INVERT_A_8
- OAREPORTTRIG6_INVERT_A_9
- OAREPORTTRIG6_INVERT_B_0
- OAREPORTTRIG6_INVERT_B_1
- OAREPORTTRIG6_INVERT_B_2
- OAREPORTTRIG6_INVERT_B_3
- OAREPORTTRIG6_INVERT_C_0
- OAREPORTTRIG6_INVERT_C_1
- OAREPORTTRIG6_INVERT_D_0
- OAREPORTTRIG6_REPORT_TRIGGER_ENABLE
- OAREPORTTRIG6_THRESHOLD_ENABLE
- OAREPORTTRIG7
- OAREPORTTRIG7_NOA_SELECT_10_SHIFT
- OAREPORTTRIG7_NOA_SELECT_11_SHIFT
- OAREPORTTRIG7_NOA_SELECT_12_SHIFT
- OAREPORTTRIG7_NOA_SELECT_13_SHIFT
- OAREPORTTRIG7_NOA_SELECT_14_SHIFT
- OAREPORTTRIG7_NOA_SELECT_15_SHIFT
- OAREPORTTRIG7_NOA_SELECT_8_SHIFT
- OAREPORTTRIG7_NOA_SELECT_9_SHIFT
- OAREPORTTRIG7_NOA_SELECT_MASK
- OAREPORTTRIG8
- OAREPORTTRIG8_NOA_SELECT_0_SHIFT
- OAREPORTTRIG8_NOA_SELECT_1_SHIFT
- OAREPORTTRIG8_NOA_SELECT_2_SHIFT
- OAREPORTTRIG8_NOA_SELECT_3_SHIFT
- OAREPORTTRIG8_NOA_SELECT_4_SHIFT
- OAREPORTTRIG8_NOA_SELECT_5_SHIFT
- OAREPORTTRIG8_NOA_SELECT_6_SHIFT
- OAREPORTTRIG8_NOA_SELECT_7_SHIFT
- OAREPORTTRIG8_NOA_SELECT_MASK
- OAREPORT_REASON_CLK_RATIO
- OAREPORT_REASON_CTX_SWITCH
- OAREPORT_REASON_MASK
- OAREPORT_REASON_SHIFT
- OAREPORT_REASON_TIMER
- OARR_SIZE_CFG_SHIFT
- OARR_VALID
- OARR_VALID_SHIFT
- OASTARTTRIG1
- OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ
- OASTARTTRIG1_THRESHOLD_MASK
- OASTARTTRIG2
- OASTARTTRIG2_EVENT_SELECT_0
- OASTARTTRIG2_EVENT_SELECT_1
- OASTARTTRIG2_EVENT_SELECT_2
- OASTARTTRIG2_EVENT_SELECT_3
- OASTARTTRIG2_INVERT_A_0
- OASTARTTRIG2_INVERT_A_1
- OASTARTTRIG2_INVERT_A_10
- OASTARTTRIG2_INVERT_A_11
- OASTARTTRIG2_INVERT_A_12
- OASTARTTRIG2_INVERT_A_13
- OASTARTTRIG2_INVERT_A_14
- OASTARTTRIG2_INVERT_A_15
- OASTARTTRIG2_INVERT_A_2
- OASTARTTRIG2_INVERT_A_3
- OASTARTTRIG2_INVERT_A_4
- OASTARTTRIG2_INVERT_A_5
- OASTARTTRIG2_INVERT_A_6
- OASTARTTRIG2_INVERT_A_7
- OASTARTTRIG2_INVERT_A_8
- OASTARTTRIG2_INVERT_A_9
- OASTARTTRIG2_INVERT_B_0
- OASTARTTRIG2_INVERT_B_1
- OASTARTTRIG2_INVERT_B_2
- OASTARTTRIG2_INVERT_B_3
- OASTARTTRIG2_INVERT_C_0
- OASTARTTRIG2_INVERT_C_1
- OASTARTTRIG2_INVERT_D_0
- OASTARTTRIG2_START_TRIG_FLAG_MBZ
- OASTARTTRIG2_THRESHOLD_ENABLE
- OASTARTTRIG3
- OASTARTTRIG3_NOA_SELECT_10_SHIFT
- OASTARTTRIG3_NOA_SELECT_11_SHIFT
- OASTARTTRIG3_NOA_SELECT_12_SHIFT
- OASTARTTRIG3_NOA_SELECT_13_SHIFT
- OASTARTTRIG3_NOA_SELECT_14_SHIFT
- OASTARTTRIG3_NOA_SELECT_15_SHIFT
- OASTARTTRIG3_NOA_SELECT_8_SHIFT
- OASTARTTRIG3_NOA_SELECT_9_SHIFT
- OASTARTTRIG3_NOA_SELECT_MASK
- OASTARTTRIG4
- OASTARTTRIG4_NOA_SELECT_0_SHIFT
- OASTARTTRIG4_NOA_SELECT_1_SHIFT
- OASTARTTRIG4_NOA_SELECT_2_SHIFT
- OASTARTTRIG4_NOA_SELECT_3_SHIFT
- OASTARTTRIG4_NOA_SELECT_4_SHIFT
- OASTARTTRIG4_NOA_SELECT_5_SHIFT
- OASTARTTRIG4_NOA_SELECT_6_SHIFT
- OASTARTTRIG4_NOA_SELECT_7_SHIFT
- OASTARTTRIG4_NOA_SELECT_MASK
- OASTARTTRIG5
- OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ
- OASTARTTRIG5_THRESHOLD_MASK
- OASTARTTRIG6
- OASTARTTRIG6_EVENT_SELECT_4
- OASTARTTRIG6_EVENT_SELECT_5
- OASTARTTRIG6_EVENT_SELECT_6
- OASTARTTRIG6_EVENT_SELECT_7
- OASTARTTRIG6_INVERT_A_0
- OASTARTTRIG6_INVERT_A_1
- OASTARTTRIG6_INVERT_A_10
- OASTARTTRIG6_INVERT_A_11
- OASTARTTRIG6_INVERT_A_12
- OASTARTTRIG6_INVERT_A_13
- OASTARTTRIG6_INVERT_A_14
- OASTARTTRIG6_INVERT_A_15
- OASTARTTRIG6_INVERT_A_2
- OASTARTTRIG6_INVERT_A_3
- OASTARTTRIG6_INVERT_A_4
- OASTARTTRIG6_INVERT_A_5
- OASTARTTRIG6_INVERT_A_6
- OASTARTTRIG6_INVERT_A_7
- OASTARTTRIG6_INVERT_A_8
- OASTARTTRIG6_INVERT_A_9
- OASTARTTRIG6_INVERT_B_0
- OASTARTTRIG6_INVERT_B_1
- OASTARTTRIG6_INVERT_B_2
- OASTARTTRIG6_INVERT_B_3
- OASTARTTRIG6_INVERT_C_0
- OASTARTTRIG6_INVERT_C_1
- OASTARTTRIG6_INVERT_D_0
- OASTARTTRIG6_START_TRIG_FLAG_MBZ
- OASTARTTRIG6_THRESHOLD_ENABLE
- OASTARTTRIG7
- OASTARTTRIG7_NOA_SELECT_10_SHIFT
- OASTARTTRIG7_NOA_SELECT_11_SHIFT
- OASTARTTRIG7_NOA_SELECT_12_SHIFT
- OASTARTTRIG7_NOA_SELECT_13_SHIFT
- OASTARTTRIG7_NOA_SELECT_14_SHIFT
- OASTARTTRIG7_NOA_SELECT_15_SHIFT
- OASTARTTRIG7_NOA_SELECT_8_SHIFT
- OASTARTTRIG7_NOA_SELECT_9_SHIFT
- OASTARTTRIG7_NOA_SELECT_MASK
- OASTARTTRIG8
- OASTARTTRIG8_NOA_SELECT_0_SHIFT
- OASTARTTRIG8_NOA_SELECT_1_SHIFT
- OASTARTTRIG8_NOA_SELECT_2_SHIFT
- OASTARTTRIG8_NOA_SELECT_3_SHIFT
- OASTARTTRIG8_NOA_SELECT_4_SHIFT
- OASTARTTRIG8_NOA_SELECT_5_SHIFT
- OASTARTTRIG8_NOA_SELECT_6_SHIFT
- OASTARTTRIG8_NOA_SELECT_7_SHIFT
- OASTARTTRIG8_NOA_SELECT_MASK
- OAS_FIND_ANY_TARGET
- OAS_FIND_ANY_VPORT
- OAS_LUN_DISABLE
- OAS_LUN_ENABLE
- OAS_LUN_STATUS_EXISTS
- OAS_LUN_VALID
- OA_BUFFER_SIZE
- OA_EXPONENT_MAX
- OA_PERFCNT1_HI
- OA_PERFCNT1_LO
- OA_PERFCNT2_HI
- OA_PERFCNT2_LO
- OA_PERFCNT3_HI
- OA_PERFCNT3_LO
- OA_PERFCNT4_HI
- OA_PERFCNT4_LO
- OA_PERFMATRIX_HI
- OA_PERFMATRIX_LO
- OA_TAIL_MARGIN_NSEC
- OA_TAKEN
- OB
- OBCR_ODS_16mA
- OBDR_SIG_LEN
- OBDR_SIG_OFFSET
- OBDR_TAPE_INQ_SIZE
- OBDR_TAPE_SIG
- OBD_SEND_START
- OBD_SEND_STOP
- OBEX_CTRL_IDX
- OBEX_DATA_IDX
- OBF
- OBFF_CFG
- OBFF_DISABLE
- OBFF_EN_MASK
- OBF_RETRY_TIMEOUT
- OBJADDR_AUTO_INC
- OBJADDR_IHR_SEL
- OBJADDR_RCMTA_SEL
- OBJADDR_RINC
- OBJADDR_SCR_SEL
- OBJADDR_SEL_MASK
- OBJADDR_SHM_SEL
- OBJADDR_SRCHM_SEL
- OBJADDR_UCM_SEL
- OBJADDR_WINC
- OBJAGG_OBJ_ROOT_ID_INVALID
- OBJAGG_OPT_ALGO_SIMPLE_GREEDY
- OBJECT_ACE_FLAGS
- OBJECT_ALLOCATED
- OBJECT_ENUM_ID1
- OBJECT_ENUM_ID2
- OBJECT_ENUM_ID3
- OBJECT_ENUM_ID4
- OBJECT_ENUM_ID5
- OBJECT_ENUM_ID6
- OBJECT_EXISTS
- OBJECT_EXISTS_CLEAN
- OBJECT_FULL_SCAN
- OBJECT_ID_ATTR
- OBJECT_ID_MASK
- OBJECT_ID_SHIFT
- OBJECT_INHERIT_ACE
- OBJECT_NONEXISTENT
- OBJECT_NO_SCAN
- OBJECT_PENDING
- OBJECT_R
- OBJECT_REPORTED
- OBJECT_R_VAL
- OBJECT_TYPE_AUDIO
- OBJECT_TYPE_CLOCK_SOURCE
- OBJECT_TYPE_CONNECTOR
- OBJECT_TYPE_CONTROLLER
- OBJECT_TYPE_COUNT
- OBJECT_TYPE_ENCODER
- OBJECT_TYPE_ENGINE
- OBJECT_TYPE_GENERIC
- OBJECT_TYPE_GPU
- OBJECT_TYPE_MASK
- OBJECT_TYPE_ROUTER
- OBJECT_TYPE_SHIFT
- OBJECT_TYPE_UNKNOWN
- OBJFREELIST_SLAB
- OBJID_ack_timeout
- OBJID_acting_as_ap_status
- OBJID_adhoc_missed_bcn
- OBJID_adhoc_scan_cycle_max
- OBJID_allow_bcast_ID_prbrsp
- OBJID_assoc_resp_timeout
- OBJID_basic_rate_set
- OBJID_beacon_period
- OBJID_curr_country_code
- OBJID_current_ess_id
- OBJID_cw_max_msb
- OBJID_cw_min_msb
- OBJID_det_rssi_thresh_offset
- OBJID_det_sync_thresh
- OBJID_difs
- OBJID_dtim_period
- OBJID_frag_threshold
- OBJID_hop_pattern
- OBJID_hop_time
- OBJID_infra_missed_bcn
- OBJID_infra_scan_cycle_max
- OBJID_infra_super_cycle_max
- OBJID_low_snr_count_thresh
- OBJID_mac_address
- OBJID_max_scan_dwell_time
- OBJID_med_busy_thresh_offset
- OBJID_network_type
- OBJID_noise_filter_gain
- OBJID_noise_limit_offset
- OBJID_pifs
- OBJID_power_mgt_state
- OBJID_privacy_can_join
- OBJID_privacy_must_start
- OBJID_promiscuous_mode
- OBJID_reserved
- OBJID_retry_max
- OBJID_roaming_low_snr
- OBJID_rts_threshold
- OBJID_scan_dwell_time
- OBJID_scanning_mode
- OBJID_sifs
- OBJID_slot_time
- OBJID_test_max_chan_num
- OBJID_test_min_chan_num
- OBJID_test_mode
- OBJID_unique_word
- OBJS_PER_BYTE
- OBJUSERROLETYPE
- OBJ_ALLOCATED
- OBJ_ALLOCATED_TAG
- OBJ_ID_INDEX_DATA
- OBJ_INDEX_BITS
- OBJ_INDEX_MASK
- OBJ_LOCK_NORMAL
- OBJ_LOCK_SHRINKER
- OBJ_MASK
- OBJ_OP_DISCARD
- OBJ_OP_READ
- OBJ_OP_WRITE
- OBJ_OP_ZEROOUT
- OBJ_REQUEST_BIO
- OBJ_REQUEST_BVECS
- OBJ_REQUEST_NODATA
- OBJ_REQUEST_OWN_BVECS
- OBJ_TAG_BITS
- OBJ_TARGET_ANON
- OBJ_TARGET_SCSI_DEVICE_ID
- OBJ_TARGET_SCSI_NAME
- OBJ_TREE
- OBJ_USED
- OBPC
- OBP_INT_LEVEL_ONBOARD
- OBP_INT_LEVEL_SBUS
- OBP_INT_LEVEL_SOFT
- OBP_INT_LEVEL_VME
- OBP_PS2KBD_NAME1
- OBP_PS2KBD_NAME2
- OBP_PS2MS_NAME1
- OBP_PS2MS_NAME2
- OBP_TRANS_LOOKUP
- OBQDBGADDR_G
- OBQDBGADDR_M
- OBQDBGADDR_S
- OBQDBGADDR_V
- OBQDBGBUSY_F
- OBQDBGBUSY_S
- OBQDBGBUSY_V
- OBQDBGEN_F
- OBQDBGEN_S
- OBQDBGEN_V
- OBQNCSIPARERR_F
- OBQNCSIPARERR_S
- OBQNCSIPARERR_V
- OBQSELECT_F
- OBQSELECT_S
- OBQSELECT_V
- OBQSGEPARERR_F
- OBQSGEPARERR_S
- OBQSGEPARERR_V
- OBQULP0PARERR_F
- OBQULP0PARERR_S
- OBQULP0PARERR_V
- OBQULP1PARERR_F
- OBQULP1PARERR_S
- OBQULP1PARERR_V
- OBQULP2PARERR_F
- OBQULP2PARERR_S
- OBQULP2PARERR_V
- OBQULP3PARERR_F
- OBQULP3PARERR_S
- OBQULP3PARERR_V
- OBSERVE0__anaobs_sel_MASK
- OBSERVE0__anaobs_sel__SHIFT
- OBSERVE0__clear_sticky_lock_MASK
- OBSERVE0__clear_sticky_lock__SHIFT
- OBSERVE0__dco_cfg_MASK
- OBSERVE0__dco_cfg__SHIFT
- OBSERVE0__lock_det_dis_MASK
- OBSERVE0__lock_det_dis__SHIFT
- OBSERVE0__lock_det_tdc_steps_MASK
- OBSERVE0__lock_det_tdc_steps__SHIFT
- OBSERVE1__digobs_div_MASK
- OBSERVE1__digobs_div__SHIFT
- OBSERVE1__digobs_sel_MASK
- OBSERVE1__digobs_sel__SHIFT
- OBSERVE1__digobs_trig_div_MASK
- OBSERVE1__digobs_trig_div__SHIFT
- OBSERVE1__digobs_trig_sel_MASK
- OBSERVE1__digobs_trig_sel__SHIFT
- OBSERVE1__lock_timer_MASK
- OBSERVE1__lock_timer__SHIFT
- OBSOLETE_CNODE
- OBSOLETE_PMAC_NVRAM_GET_OFFSET
- OBSOLETE_ZNODE
- OBUFLEN
- OBUFP
- OBUFSIZE
- OBUFSPC
- OBUF_0U
- OBUF_0V
- OBUF_0Y
- OBUF_1U
- OBUF_1V
- OBUF_1Y
- OBUF_BYPASS_DIS
- OBUF_BYPASS_EN
- OBUF_BYPASS_SEL
- OBUF_FULL
- OBUF_FULL_RECOUT
- OBUF_HALF_RECOUT
- OBUF_IS_HALF_RECOUT_WIDTH_SEL
- OBUF_RECOUT
- OBUF_USE_FULL_BUFFER_SEL
- OBUF__MEM_PG
- OBUF__MEM_PG__0
- OBUS
- OBVAL0
- OBVAL1
- OBVAL2
- OBVAL3
- OBVAL4
- OBVAL5
- OBVAL6
- OBVAL7
- OBWIN0
- OBWIN1
- OBWIN2
- OBWIN3
- OBX_STATE
- OB_3032MAC_IOCB_REQ_IC
- OB_3032MAC_IOCB_REQ_TC
- OB_3032MAC_IOCB_REQ_UC
- OB_BASE_ADDR_HI_OFFSET
- OB_BASE_ADDR_LO_OFFSET
- OB_CIPCI_BAR
- OB_CIPCI_BAR_OFFSET
- OB_CTRL_REV1_2_OFFSET
- OB_CTRL_REV3_5_OFFSET
- OB_DYNAMIC_COALES_OFFSET
- OB_ENABLEN
- OB_INTERRUPT_COALES_OFFSET
- OB_IP_IOCB_REQ_C
- OB_IP_IOCB_REQ_D
- OB_IP_IOCB_REQ_E
- OB_IP_IOCB_REQ_H
- OB_IP_IOCB_REQ_I
- OB_IP_IOCB_REQ_L
- OB_IP_IOCB_REQ_O
- OB_IP_IOCB_REQ_R
- OB_IP_IOCB_REQ_U
- OB_LO_IO
- OB_MAC_IOCB_DFP
- OB_MAC_IOCB_LEN_MASK
- OB_MAC_IOCB_REQ_C
- OB_MAC_IOCB_REQ_D
- OB_MAC_IOCB_REQ_E
- OB_MAC_IOCB_REQ_F
- OB_MAC_IOCB_REQ_I
- OB_MAC_IOCB_REQ_L
- OB_MAC_IOCB_REQ_MA
- OB_MAC_IOCB_REQ_OI
- OB_MAC_IOCB_REQ_R
- OB_MAC_IOCB_REQ_X
- OB_MAC_IOCB_RSP_B
- OB_MAC_IOCB_RSP_E
- OB_MAC_IOCB_RSP_H
- OB_MAC_IOCB_RSP_I
- OB_MAC_IOCB_RSP_L
- OB_MAC_IOCB_RSP_OI
- OB_MAC_IOCB_RSP_P
- OB_MAC_IOCB_RSP_S
- OB_MAC_IOCB_V
- OB_MAC_TRANSPORT_HDR_SHIFT
- OB_MAC_TSO_IOCB_D
- OB_MAC_TSO_IOCB_DFP
- OB_MAC_TSO_IOCB_I
- OB_MAC_TSO_IOCB_IC
- OB_MAC_TSO_IOCB_IP4
- OB_MAC_TSO_IOCB_IP6
- OB_MAC_TSO_IOCB_LSO
- OB_MAC_TSO_IOCB_OI
- OB_MAC_TSO_IOCB_RSP_B
- OB_MAC_TSO_IOCB_RSP_E
- OB_MAC_TSO_IOCB_RSP_I
- OB_MAC_TSO_IOCB_RSP_L
- OB_MAC_TSO_IOCB_RSP_OI
- OB_MAC_TSO_IOCB_RSP_P
- OB_MAC_TSO_IOCB_RSP_S
- OB_MAC_TSO_IOCB_TC
- OB_MAC_TSO_IOCB_UC
- OB_MAC_TSO_IOCB_V
- OB_MEMMAP
- OB_OFFSET_HI
- OB_OFFSET_INDEX
- OB_PI_BASE_ADDR_HI_OFFSET
- OB_PI_BASE_ADDR_LO_OFFSET
- OB_PROPERITY_OFFSET
- OB_PROPERTY_INT_ENABLE
- OB_REG_SIZE_SHIFT
- OB_SIZE
- OB_WIN_SIZE
- OB_XLAT_EN_VAL
- OC1_ALARM_COUNT
- OC1_CFG
- OC1_CFG_ALARM_POLARITY_MASK
- OC1_CFG_EN_THROTTLE_MASK
- OC1_CFG_HW_RESTORE_MASK
- OC1_CFG_LONG_LATENCY_MASK
- OC1_CFG_PWR_GOOD_MASK_MASK
- OC1_CFG_THROTTLE_MODE_MASK
- OC1_CNT_THRESHOLD
- OC1_FILTER
- OC1_STATS
- OC1_THROTTLE_PERIOD
- OCAP_1x
- OCAP_2x
- OCAP_3x
- OCAP_4x
- OCB_ADDR
- OCB_DATA1
- OCB_DATA3
- OCB_WORK_HOUSEKEEPING
- OCCR0
- OCCR0_INIT_VAL
- OCCR0_OCI
- OCCR0_OFF
- OCCR0_ON
- OCCR0_WB
- OCCR0_WT
- OCCR1
- OCCR1_INIT_VAL
- OCCR1_NOLOCK
- OCCR_BASE
- OCCR_REG0
- OCCR_REG1
- OCC_CMD_DATA_BYTES
- OCC_CMD_IN_PRG_WAIT_MS
- OCC_COMMON_H
- OCC_DATA_ATTN
- OCC_ERROR_COUNT_THRESHOLD
- OCC_EXT_STAT_DVFS_OT
- OCC_EXT_STAT_DVFS_POWER
- OCC_EXT_STAT_MEM_THROTTLE
- OCC_EXT_STAT_QUICK_DROP
- OCC_FRU_TYPE_VRM
- OCC_INIT_ATTR
- OCC_LOAD
- OCC_MAX_REASON
- OCC_MAX_THROTTLE_STATUS
- OCC_RESET
- OCC_RESET_THROTTLE
- OCC_RESP_BAD_STATE
- OCC_RESP_CHKSUM_ERR
- OCC_RESP_CMD_INVAL
- OCC_RESP_CMD_IN_PRG
- OCC_RESP_CMD_LEN_INVAL
- OCC_RESP_CRIT_EXCEPT
- OCC_RESP_CRIT_HW
- OCC_RESP_CRIT_INIT
- OCC_RESP_CRIT_OCB
- OCC_RESP_CRIT_WATCHDOG
- OCC_RESP_DATA_BYTES
- OCC_RESP_DATA_INVAL
- OCC_RESP_INT_ERR
- OCC_RESP_SUCCESS
- OCC_SAFE_TIMEOUT
- OCC_SBE_STATUS_WORDS
- OCC_SRAM_ADDR_CMD
- OCC_SRAM_ADDR_RESP
- OCC_SRAM_BYTES
- OCC_SRAM_CMD_ADDR
- OCC_SRAM_RSP_ADDR
- OCC_STATE_SAFE
- OCC_STAT_ACTIVE
- OCC_STAT_MASTER
- OCC_TEMP_SENSOR_FAULT
- OCC_THROTTLE
- OCC_TIMEOUT_MS
- OCC_UPDATE_FREQUENCY
- OCELOT_ACE_TYPE_ANY
- OCELOT_ACE_TYPE_ARP
- OCELOT_ACE_TYPE_ETYPE
- OCELOT_ACE_TYPE_IPV4
- OCELOT_ACE_TYPE_IPV6
- OCELOT_ACE_TYPE_LLC
- OCELOT_ACE_TYPE_SNAP
- OCELOT_ACL_ACTION_DROP
- OCELOT_ACL_ACTION_TRAP
- OCELOT_BUFFER_CELL_SZ
- OCELOT_FUNC_PER_PIN
- OCELOT_GPIO_ALT0
- OCELOT_GPIO_ALT1
- OCELOT_GPIO_IN
- OCELOT_GPIO_INTR
- OCELOT_GPIO_INTR_ENA
- OCELOT_GPIO_INTR_IDENT
- OCELOT_GPIO_OE
- OCELOT_GPIO_OUT
- OCELOT_GPIO_OUT_CLR
- OCELOT_GPIO_OUT_SET
- OCELOT_GPIO_SD_MAP
- OCELOT_IF_SI_OWNER_OFFSET
- OCELOT_NR_IRQ
- OCELOT_P
- OCELOT_PART_ID
- OCELOT_PIN
- OCELOT_POLICER_DISCARD
- OCELOT_PTP_QUEUE_SZ
- OCELOT_SPEED_10
- OCELOT_SPEED_100
- OCELOT_SPEED_1000
- OCELOT_SPEED_2500
- OCELOT_STATS_CHECK_DELAY
- OCELOT_VCAP_BIT_0
- OCELOT_VCAP_BIT_1
- OCELOT_VCAP_BIT_ANY
- OCFAR
- OCFB_CTRL
- OCFB_CTRL_CD16
- OCFB_CTRL_CD24
- OCFB_CTRL_CD32
- OCFB_CTRL_CD8
- OCFB_CTRL_HIE
- OCFB_CTRL_PC
- OCFB_CTRL_VBL1
- OCFB_CTRL_VBL2
- OCFB_CTRL_VBL4
- OCFB_CTRL_VBL8
- OCFB_CTRL_VEN
- OCFB_HTIM
- OCFB_HVLEN
- OCFB_NAME
- OCFB_PALETTE
- OCFB_STAT
- OCFB_VBARA
- OCFB_VTIM
- OCFS1_MAJOR_VERSION
- OCFS1_MAX_CLUSTER_NAME_LEN
- OCFS1_MAX_MOUNT_POINT_LEN
- OCFS1_MAX_VOL_ID_LENGTH
- OCFS1_MAX_VOL_LABEL_LEN
- OCFS1_MAX_VOL_SIGNATURE_LEN
- OCFS1_MINOR_VERSION
- OCFS1_VOLUME_SIGNATURE
- OCFS2_32BIT_POS_MASK
- OCFS2_ACL_H
- OCFS2_AC_USE_INODE
- OCFS2_AC_USE_LOCAL
- OCFS2_AC_USE_MAIN
- OCFS2_AC_USE_META
- OCFS2_ALLOC_H
- OCFS2_AOPS_H
- OCFS2_APPEND_FL
- OCFS2_AST_ATTACH
- OCFS2_AST_CONVERT
- OCFS2_AST_DOWNCONVERT
- OCFS2_AST_INVALID
- OCFS2_BACKUP_SB_START
- OCFS2_BH_IGNORE_CACHE
- OCFS2_BH_READAHEAD
- OCFS2_BITMAP_FL
- OCFS2_BLOCKCHECK_H
- OCFS2_BTREE_FL
- OCFS2_BUFFER_HEAD_IO_H
- OCFS2_CACHE_FL_INLINE
- OCFS2_CACHE_INFO_MAX_ARRAY
- OCFS2_CHAIN_FL
- OCFS2_CHECK_RESERVATIONS
- OCFS2_CLASSIC_CLUSTER_STACK
- OCFS2_CLEAR_COMPAT_FEATURE
- OCFS2_CLEAR_INCOMPAT_FEATURE
- OCFS2_CLEAR_RO_COMPAT_FEATURE
- OCFS2_CLUSTER_NAME_LEN
- OCFS2_CLUSTER_O2CB_GLOBAL_HEARTBEAT
- OCFS2_COMPRBLK_FL
- OCFS2_COMPR_FL
- OCFS2_CONTROL_HANDSHAKE_INVALID
- OCFS2_CONTROL_HANDSHAKE_PROTOCOL
- OCFS2_CONTROL_HANDSHAKE_READ
- OCFS2_CONTROL_HANDSHAKE_VALID
- OCFS2_CONTROL_MESSAGE_DOWN_OP
- OCFS2_CONTROL_MESSAGE_DOWN_TOTAL_LEN
- OCFS2_CONTROL_MESSAGE_NODENUM_LEN
- OCFS2_CONTROL_MESSAGE_OP_LEN
- OCFS2_CONTROL_MESSAGE_SETNODE_OP
- OCFS2_CONTROL_MESSAGE_SETNODE_TOTAL_LEN
- OCFS2_CONTROL_MESSAGE_SETVERSION_OP
- OCFS2_CONTROL_MESSAGE_SETVERSION_TOTAL_LEN
- OCFS2_CONTROL_MESSAGE_VERNUM_LEN
- OCFS2_CONTROL_PROTO
- OCFS2_CONTROL_PROTO_LEN
- OCFS2_DCACHE_H
- OCFS2_DEALLOC_FL
- OCFS2_DEFAULT_ATIME_QUANTUM
- OCFS2_DEFAULT_COMMIT_INTERVAL
- OCFS2_DEFAULT_RESV_LEVEL
- OCFS2_DELETE_INODE_CREDITS
- OCFS2_DENTRY_LOCK_INO_START
- OCFS2_DIO_ORPHANED_FL
- OCFS2_DIO_ORPHAN_PREFIX
- OCFS2_DIO_ORPHAN_PREFIX_LEN
- OCFS2_DIRSYNC_FL
- OCFS2_DIRTY_FL
- OCFS2_DIR_H
- OCFS2_DIR_LINK_ADDITIONAL_CREDITS
- OCFS2_DIR_MEMBER_LEN
- OCFS2_DIR_MIN_REC_LEN
- OCFS2_DIR_PAD
- OCFS2_DIR_REC_LEN
- OCFS2_DIR_ROUND
- OCFS2_DIR_TRAILER_SIGNATURE
- OCFS2_DLM_DEBUG_STR_VERSION
- OCFS2_DQUOT
- OCFS2_DX_ENTRIES_MAX
- OCFS2_DX_FLAG_INLINE
- OCFS2_DX_LEAF_SIGNATURE
- OCFS2_DX_LINK_MAX
- OCFS2_DX_ROOT_REMOVE_CREDITS
- OCFS2_DX_ROOT_SIGNATURE
- OCFS2_ECOMPR_FL
- OCFS2_ERROR_FS
- OCFS2_EXPAND_REFCOUNT_TREE_CREDITS
- OCFS2_EXPORT_H
- OCFS2_EXTENT_BLOCK_SIGNATURE
- OCFS2_EXT_REFCOUNTED
- OCFS2_EXT_UNWRITTEN
- OCFS2_FEATURE_COMPAT_BACKUP_SB
- OCFS2_FEATURE_COMPAT_JBD2_SB
- OCFS2_FEATURE_COMPAT_SUPP
- OCFS2_FEATURE_INCOMPAT_APPEND_DIO
- OCFS2_FEATURE_INCOMPAT_CLUSTERINFO
- OCFS2_FEATURE_INCOMPAT_DISCONTIG_BG
- OCFS2_FEATURE_INCOMPAT_EXTENDED_SLOT_MAP
- OCFS2_FEATURE_INCOMPAT_HEARTBEAT_DEV
- OCFS2_FEATURE_INCOMPAT_INDEXED_DIRS
- OCFS2_FEATURE_INCOMPAT_INLINE_DATA
- OCFS2_FEATURE_INCOMPAT_LOCAL_MOUNT
- OCFS2_FEATURE_INCOMPAT_META_ECC
- OCFS2_FEATURE_INCOMPAT_REFCOUNT_TREE
- OCFS2_FEATURE_INCOMPAT_RESIZE_INPROG
- OCFS2_FEATURE_INCOMPAT_SPARSE_ALLOC
- OCFS2_FEATURE_INCOMPAT_SUPP
- OCFS2_FEATURE_INCOMPAT_TUNEFS_INPROG
- OCFS2_FEATURE_INCOMPAT_USERSPACE_STACK
- OCFS2_FEATURE_INCOMPAT_XATTR
- OCFS2_FEATURE_RO_COMPAT_GRPQUOTA
- OCFS2_FEATURE_RO_COMPAT_SUPP
- OCFS2_FEATURE_RO_COMPAT_UNWRITTEN
- OCFS2_FEATURE_RO_COMPAT_USRQUOTA
- OCFS2_FIEMAP_FLAGS
- OCFS2_FILECHECK_ARGS_LEN
- OCFS2_FILECHECK_ERR_BLOCKECC
- OCFS2_FILECHECK_ERR_BLOCKNO
- OCFS2_FILECHECK_ERR_END
- OCFS2_FILECHECK_ERR_FAILED
- OCFS2_FILECHECK_ERR_GENERATION
- OCFS2_FILECHECK_ERR_INJBD
- OCFS2_FILECHECK_ERR_INPROGRESS
- OCFS2_FILECHECK_ERR_INVALIDINO
- OCFS2_FILECHECK_ERR_READONLY
- OCFS2_FILECHECK_ERR_START
- OCFS2_FILECHECK_ERR_SUCCESS
- OCFS2_FILECHECK_ERR_UNSUPPORTED
- OCFS2_FILECHECK_ERR_VALIDFLAG
- OCFS2_FILECHECK_MAXSIZE
- OCFS2_FILECHECK_MINSIZE
- OCFS2_FILECHECK_TYPE_CHK
- OCFS2_FILECHECK_TYPE_FIX
- OCFS2_FILECHECK_TYPE_SET
- OCFS2_FILE_H
- OCFS2_FIRST_LOCAL_SYSTEM_INODE
- OCFS2_FIRST_ONLINE_SYSTEM_INODE
- OCFS2_FI_FLAG_FILECHECK_CHK
- OCFS2_FI_FLAG_FILECHECK_FIX
- OCFS2_FI_FLAG_ORPHAN_RECOVERY
- OCFS2_FI_FLAG_SYSFILE
- OCFS2_FL_MODIFIABLE
- OCFS2_FL_VISIBLE
- OCFS2_GLOBAL_INFO_OFF
- OCFS2_GLOBAL_QMAGICS
- OCFS2_GLOBAL_QVERSIONS
- OCFS2_GROUP_ADD_CREDITS
- OCFS2_GROUP_DESC_SIGNATURE
- OCFS2_GROUP_EXTEND_CREDITS
- OCFS2_H
- OCFS2_HASH_SHIFT
- OCFS2_HAS_COMPAT_FEATURE
- OCFS2_HAS_INCOMPAT_FEATURE
- OCFS2_HAS_REFCOUNT_FL
- OCFS2_HAS_RO_COMPAT_FEATURE
- OCFS2_HAS_XATTR_FL
- OCFS2_HB_GLOBAL
- OCFS2_HB_LOCAL
- OCFS2_HB_NONE
- OCFS2_HEARTBEAT_FL
- OCFS2_HEARTBEAT_H
- OCFS2_I
- OCFS2_IMAGIC_FL
- OCFS2_IMMUTABLE_FL
- OCFS2_INDEXED_DIR_FL
- OCFS2_INDEX_FL
- OCFS2_INFO_BLOCKSIZE
- OCFS2_INFO_CLUSTERSIZE
- OCFS2_INFO_FL_ERROR
- OCFS2_INFO_FL_FILLED
- OCFS2_INFO_FL_NON_COHERENT
- OCFS2_INFO_FREEFRAG
- OCFS2_INFO_FREEINODE
- OCFS2_INFO_FS_FEATURES
- OCFS2_INFO_JOURNAL_SIZE
- OCFS2_INFO_LABEL
- OCFS2_INFO_MAGIC
- OCFS2_INFO_MAXSLOTS
- OCFS2_INFO_MAX_HIST
- OCFS2_INFO_MAX_REQUEST
- OCFS2_INFO_NUM_TYPES
- OCFS2_INFO_UUID
- OCFS2_INLINE_DATA_FL
- OCFS2_INLINE_XATTR_FL
- OCFS2_INODE_ADD_TO_ORPHAN_CREDITS
- OCFS2_INODE_BITMAP
- OCFS2_INODE_DELETED
- OCFS2_INODE_DEL_FROM_ORPHAN_CREDITS
- OCFS2_INODE_DIO_ORPHAN_ENTRY
- OCFS2_INODE_H
- OCFS2_INODE_JOURNAL
- OCFS2_INODE_MAYBE_ORPHANED
- OCFS2_INODE_OPEN_DIRECT
- OCFS2_INODE_SIGNATURE
- OCFS2_INODE_SKIP_ORPHAN_DIR
- OCFS2_INODE_SYSTEM_FILE
- OCFS2_INODE_UPDATE_CREDITS
- OCFS2_INVALID_SLOT
- OCFS2_IOC32_GETFLAGS
- OCFS2_IOC32_SETFLAGS
- OCFS2_IOCB_NUM_LOCKS
- OCFS2_IOCB_RW_LOCK
- OCFS2_IOCB_RW_LOCK_LEVEL
- OCFS2_IOCTL_H
- OCFS2_IOCTL_PROTO_H
- OCFS2_IOC_ALLOCSP
- OCFS2_IOC_ALLOCSP64
- OCFS2_IOC_FREESP
- OCFS2_IOC_FREESP64
- OCFS2_IOC_GETFLAGS
- OCFS2_IOC_GROUP_ADD
- OCFS2_IOC_GROUP_ADD64
- OCFS2_IOC_GROUP_EXTEND
- OCFS2_IOC_INFO
- OCFS2_IOC_MOVE_EXT
- OCFS2_IOC_REFLINK
- OCFS2_IOC_RESVSP
- OCFS2_IOC_RESVSP64
- OCFS2_IOC_SETFLAGS
- OCFS2_IOC_UNRESVSP
- OCFS2_IOC_UNRESVSP64
- OCFS2_IS_VALID_DINODE
- OCFS2_IS_VALID_DIR_TRAILER
- OCFS2_IS_VALID_DX_LEAF
- OCFS2_IS_VALID_DX_ROOT
- OCFS2_IS_VALID_EXTENT_BLOCK
- OCFS2_IS_VALID_GROUP_DESC
- OCFS2_IS_VALID_REFCOUNT_BLOCK
- OCFS2_IS_VALID_XATTR_BLOCK
- OCFS2_JOURNAL_ACCESS_CREATE
- OCFS2_JOURNAL_ACCESS_UNDO
- OCFS2_JOURNAL_ACCESS_WRITE
- OCFS2_JOURNAL_DATA_FL
- OCFS2_JOURNAL_DIRTY_FL
- OCFS2_JOURNAL_FL
- OCFS2_JOURNAL_FREE
- OCFS2_JOURNAL_H
- OCFS2_JOURNAL_IN_SHUTDOWN
- OCFS2_JOURNAL_LOADED
- OCFS2_LAST_GLOBAL_SYSTEM_INODE
- OCFS2_LAST_LOCAL_SYSTEM_INODE
- OCFS2_LA_DISABLED
- OCFS2_LA_ENABLED
- OCFS2_LA_ENABLE_INTERVAL
- OCFS2_LA_EVENT_ENOSPC
- OCFS2_LA_EVENT_FRAGMENTED
- OCFS2_LA_EVENT_SLIDE
- OCFS2_LA_MAX_DEFAULT_MB
- OCFS2_LA_OLD_DEFAULT
- OCFS2_LA_THROTTLED
- OCFS2_LA_UNUSED
- OCFS2_LINKS_HI_SHIFT
- OCFS2_LINK_MAX
- OCFS2_LOCALALLOC_H
- OCFS2_LOCAL_ALLOC
- OCFS2_LOCAL_ALLOC_FL
- OCFS2_LOCAL_INFO_OFF
- OCFS2_LOCAL_QINFO_WRITE_CREDITS
- OCFS2_LOCAL_QMAGICS
- OCFS2_LOCAL_QVERSIONS
- OCFS2_LOCKID_H
- OCFS2_LOCKINGVER_H
- OCFS2_LOCKING_PROTOCOL_MAJOR
- OCFS2_LOCKING_PROTOCOL_MINOR
- OCFS2_LOCKS_H
- OCFS2_LOCK_ATTACHED
- OCFS2_LOCK_BLOCKED
- OCFS2_LOCK_BUSY
- OCFS2_LOCK_FREEING
- OCFS2_LOCK_ID_MAX_LEN
- OCFS2_LOCK_ID_PAD
- OCFS2_LOCK_INITIALIZED
- OCFS2_LOCK_LOCAL
- OCFS2_LOCK_NEEDS_REFRESH
- OCFS2_LOCK_NOCACHE
- OCFS2_LOCK_NONBLOCK
- OCFS2_LOCK_NONBLOCK_FINISHED
- OCFS2_LOCK_PENDING
- OCFS2_LOCK_QUEUED
- OCFS2_LOCK_REFRESHING
- OCFS2_LOCK_TYPE_DATA
- OCFS2_LOCK_TYPE_DENTRY
- OCFS2_LOCK_TYPE_FLOCK
- OCFS2_LOCK_TYPE_META
- OCFS2_LOCK_TYPE_NFS_SYNC
- OCFS2_LOCK_TYPE_OPEN
- OCFS2_LOCK_TYPE_ORPHAN_SCAN
- OCFS2_LOCK_TYPE_QINFO
- OCFS2_LOCK_TYPE_REFCOUNT
- OCFS2_LOCK_TYPE_RENAME
- OCFS2_LOCK_TYPE_RW
- OCFS2_LOCK_TYPE_SUPER
- OCFS2_LOCK_TYPE_TRIM_FS
- OCFS2_LOCK_UPCONVERT_FINISHING
- OCFS2_LVB_VERSION
- OCFS2_MAJOR_REV_LEVEL
- OCFS2_MAXQUOTAS
- OCFS2_MAX_BACKUP_SUPERBLOCKS
- OCFS2_MAX_BG_BITMAP_SIZE
- OCFS2_MAX_BLOCKSIZE
- OCFS2_MAX_CLUSTERSIZE
- OCFS2_MAX_CLUSTERS_PER_PAGE
- OCFS2_MAX_CTXT_PAGES
- OCFS2_MAX_EXTENT_MAP_ITEMS
- OCFS2_MAX_FILENAME_LEN
- OCFS2_MAX_HB_CTL_PATH
- OCFS2_MAX_PATH_DEPTH
- OCFS2_MAX_RESV_LEVEL
- OCFS2_MAX_RESV_WINDOW_BITS
- OCFS2_MAX_SLOTS
- OCFS2_MAX_TO_STEAL
- OCFS2_MAX_TRANS_DATA
- OCFS2_MAX_VOL_LABEL_LEN
- OCFS2_MAX_XATTR_TREE_LEAF_SIZE
- OCFS2_META_LOCK_GETBH
- OCFS2_META_LOCK_NOQUEUE
- OCFS2_META_LOCK_RECOVERY
- OCFS2_MINOR_REV_LEVEL
- OCFS2_MIN_BLOCKSIZE
- OCFS2_MIN_CLUSTERSIZE
- OCFS2_MIN_JOURNAL_SIZE
- OCFS2_MIN_RESV_LEVEL
- OCFS2_MIN_RESV_WINDOW_BITS
- OCFS2_MIN_XATTR_INLINE_SIZE
- OCFS2_MMAP_H
- OCFS2_MOUNT_BARRIER
- OCFS2_MOUNT_COHERENCY_BUFFERED
- OCFS2_MOUNT_DATA_WRITEBACK
- OCFS2_MOUNT_ERRORS_CONT
- OCFS2_MOUNT_ERRORS_PANIC
- OCFS2_MOUNT_ERRORS_ROFS
- OCFS2_MOUNT_GRPQUOTA
- OCFS2_MOUNT_HB_GLOBAL
- OCFS2_MOUNT_HB_LOCAL
- OCFS2_MOUNT_HB_NONE
- OCFS2_MOUNT_INODE64
- OCFS2_MOUNT_JOURNAL_ASYNC_COMMIT
- OCFS2_MOUNT_LOCALFLOCKS
- OCFS2_MOUNT_NOINTR
- OCFS2_MOUNT_NOUSERXATTR
- OCFS2_MOUNT_NO_POSIX_ACL
- OCFS2_MOUNT_POSIX_ACL
- OCFS2_MOUNT_USRQUOTA
- OCFS2_MOVE_EXTENTS_H
- OCFS2_MOVE_EXT_FL_AUTO_DEFRAG
- OCFS2_MOVE_EXT_FL_COMPLETE
- OCFS2_MOVE_EXT_FL_PART_DEFRAG
- OCFS2_NAMEI_H
- OCFS2_NOATIME_FL
- OCFS2_NOCOMP_FL
- OCFS2_NODE_MAP_MAX_NODES
- OCFS2_NODUMP_FL
- OCFS2_NOTAIL_FL
- OCFS2_NSEC_MASK
- OCFS2_NUM_LOCK_TYPES
- OCFS2_ORPHANED_FL
- OCFS2_ORPHAN_LVB_VERSION
- OCFS2_ORPHAN_NAMELEN
- OCFS2_OSB_ERROR_FS
- OCFS2_OSB_HARD_RO
- OCFS2_OSB_SOFT_RO
- OCFS2_QBLK_RESERVED_SPACE
- OCFS2_QINFO_LVB_VERSION
- OCFS2_QINFO_WRITE_CREDITS
- OCFS2_QSYNC_CREDITS
- OCFS2_QUOTA_BLOCK_UPDATE_CREDITS
- OCFS2_QUOTA_FL
- OCFS2_QWRITE_CREDITS
- OCFS2_RAW_SB
- OCFS2_REFCOUNTTREE_H
- OCFS2_REFCOUNT_BLOCK_SIGNATURE
- OCFS2_REFCOUNT_LEAF_FL
- OCFS2_REFCOUNT_TREE_CREATE_CREDITS
- OCFS2_REFCOUNT_TREE_FL
- OCFS2_REFCOUNT_TREE_REMOVE_CREDITS
- OCFS2_REFCOUNT_TREE_SET_CREDITS
- OCFS2_RESERVATIONS_H
- OCFS2_RESERVED_FL
- OCFS2_RESIZE_H
- OCFS2_RESV_FLAG_DIR
- OCFS2_RESV_FLAG_INUSE
- OCFS2_RESV_FLAG_TMP
- OCFS2_RESV_TYPES
- OCFS2_SB
- OCFS2_SECRM_FL
- OCFS2_SEC_BITS
- OCFS2_SEC_SHIFT
- OCFS2_SET_COMPAT_FEATURE
- OCFS2_SET_INCOMPAT_FEATURE
- OCFS2_SET_RO_COMPAT_FEATURE
- OCFS2_SIMPLE_DIR_EXTEND_CREDITS
- OCFS2_STACK_LABEL_LEN
- OCFS2_STACK_PLUGIN_O2CB
- OCFS2_STACK_PLUGIN_USER
- OCFS2_SUBALLOC_ALLOC
- OCFS2_SUBALLOC_FREE
- OCFS2_SUPER_BLOCK_BLKNO
- OCFS2_SUPER_BLOCK_FL
- OCFS2_SUPER_BLOCK_SIGNATURE
- OCFS2_SUPER_H
- OCFS2_SUPER_MAGIC
- OCFS2_SYMLINK_H
- OCFS2_SYNC_FL
- OCFS2_SYSFILE_H
- OCFS2_SYSTEM_FL
- OCFS2_TEXT_UUID_LEN
- OCFS2_TOPDIR_FL
- OCFS2_TRIMFS_LVB_VERSION
- OCFS2_TRUNCATE_LOG_FLUSH_INTERVAL
- OCFS2_TRUNCATE_LOG_FLUSH_ONE_REC
- OCFS2_TRUNCATE_LOG_UPDATE
- OCFS2_TUNEFS_INPROG_REMOVE_SLOT
- OCFS2_UNLOCK_CANCEL_CONVERT
- OCFS2_UNLOCK_DROP_LOCK
- OCFS2_UNLOCK_INVALID
- OCFS2_UNRM_FL
- OCFS2_UNUSED2_FL
- OCFS2_UNUSED3_FL
- OCFS2_UPTODATE_H
- OCFS2_VALID_ATTRS
- OCFS2_VALID_FL
- OCFS2_VOL_UUID_LEN
- OCFS2_WINDOW_MOVE_CREDITS
- OCFS2_WRITE_BUFFER
- OCFS2_WRITE_DIRECT
- OCFS2_WRITE_MMAP
- OCFS2_XATTR_BLOCK_CREATE_CREDITS
- OCFS2_XATTR_BLOCK_SIGNATURE
- OCFS2_XATTR_BLOCK_UPDATE_CREDITS
- OCFS2_XATTR_BUCKET_SIZE
- OCFS2_XATTR_ENTRY_LOCAL
- OCFS2_XATTR_FREE_IN_BLOCK
- OCFS2_XATTR_FREE_IN_IBODY
- OCFS2_XATTR_H
- OCFS2_XATTR_HEADER_GAP
- OCFS2_XATTR_INDEXED
- OCFS2_XATTR_INDEX_POSIX_ACL_ACCESS
- OCFS2_XATTR_INDEX_POSIX_ACL_DEFAULT
- OCFS2_XATTR_INDEX_SECURITY
- OCFS2_XATTR_INDEX_TRUSTED
- OCFS2_XATTR_INDEX_USER
- OCFS2_XATTR_INLINE_SIZE
- OCFS2_XATTR_MAX
- OCFS2_XATTR_MAX_BLOCKS_PER_BUCKET
- OCFS2_XATTR_ROOT_SIZE
- OCFS2_XATTR_ROUND
- OCFS2_XATTR_SIZE
- OCFS2_XATTR_TYPE_MASK
- OCF_LENGTH_CPC_NAME
- OCF_LENGTH_HMC_NETWORK
- OCI2C_CMD
- OCI2C_CMD_IACK
- OCI2C_CMD_READ
- OCI2C_CMD_READ_ACK
- OCI2C_CMD_READ_NACK
- OCI2C_CMD_START
- OCI2C_CMD_STOP
- OCI2C_CMD_WRITE
- OCI2C_CONTROL
- OCI2C_CTRL_EN
- OCI2C_CTRL_IEN
- OCI2C_DATA
- OCI2C_PREHIGH
- OCI2C_PRELOW
- OCI2C_STATUS
- OCI2C_STAT_ARBLOST
- OCI2C_STAT_BUSY
- OCI2C_STAT_IF
- OCI2C_STAT_NACK
- OCI2C_STAT_TIP
- OCL1_POWER_DOWN_EN
- OCL2_LDOFUSE_PWR_DIS
- OCMBISTDN
- OCMBISTEN
- OCMBISTFAIL
- OCMBISTREPAIR
- OCMBLKRST
- OCMD_BUFFER0
- OCMD_BUFFER1
- OCMD_BUFFER_SELECT
- OCMD_BUF_TYPE_FIELD
- OCMD_BUF_TYPE_FRAME
- OCMD_BUF_TYPE_MASK
- OCMD_BYTEORDER_MASK
- OCMD_ENABLE
- OCMD_FIELD0
- OCMD_FIELD1
- OCMD_FIELD_SELECT
- OCMD_MIRROR_BOTH
- OCMD_MIRROR_HORIZONTAL
- OCMD_MIRROR_MASK
- OCMD_MIRROR_MODE
- OCMD_MIRROR_VERTICAL
- OCMD_RGB_555
- OCMD_RGB_565
- OCMD_RGB_888
- OCMD_SOURCE_FORMAT_MASK
- OCMD_TEST_MODE
- OCMD_TILED_SURFACE
- OCMD_TVSYNCFLIP_ENABLE
- OCMD_TVSYNCFLIP_PARITY
- OCMD_UV_SWAP
- OCMD_YUV_410_PLANAR
- OCMD_YUV_411_PACKED
- OCMD_YUV_420_PLANAR
- OCMD_YUV_422_PACKED
- OCMD_YUV_422_PLANAR
- OCMD_Y_AND_UV_SWAP
- OCMD_Y_SWAP
- OCMEMCX_AHB_CLK
- OCMEMCX_OCMEMNOC_CLK
- OCMEMCX_RESET
- OCMEMNOC_CLK
- OCMEMNOC_CLK_SRC
- OCMEMNOC_RESET
- OCMEM_AXI_READ_REQUEST_HELD_OFF
- OCMEM_AXI_REQUEST_HELD_OFF
- OCMEM_AXI_WRITE_DATA_HELD_OFF
- OCMEM_AXI_WRITE_REQUEST_HELD_OFF
- OCMINITIALIZED
- OCM_BASE_ADDR
- OCM_BIOS_CHIM_DE
- OCM_DE_ADDC2C_RES0
- OCM_DE_ADDC2C_RES1
- OCM_DE_ADDC2C_RES2
- OCM_DE_ADDC2C_RES3
- OCM_DE_BIOS_CHIM
- OCM_DE_BIOS_CHIM_DYNAMIC
- OCM_DE_BIOS_CHIM_OSM
- OCM_DE_BIOS_INTL
- OCM_DE_OCM_DIR
- OCM_DE_RAID_ENGN
- OCM_DE_WIN_DRVR
- OCM_INIT_DIR_ENTRIES
- OCM_MAX_SIZE
- OCM_WIN
- OCM_WIN_P3P
- OCONF_CC_OUT_8BIT
- OCONF_CSC_BYPASS
- OCONF_CSC_MODE_BT601
- OCONF_CSC_MODE_BT709
- OCONF_GAMMA2_ENABLE
- OCONF_PIPE_A
- OCONF_PIPE_B
- OCONF_PIPE_MASK
- OCONF_TEST_MODE
- OCONF_THREE_LINE_BUFFER
- OCONF_TWO_LINE_BUFFER
- OCON_FS
- OCON_FSUSE
- OCON_IBENDPORT
- OCON_IBPKEY
- OCON_ISID
- OCON_NETIF
- OCON_NODE
- OCON_NODE6
- OCON_NUM
- OCON_PORT
- OCORESEND
- OCORESOFFSET
- OCORES_FLAG_BROKEN_IRQ
- OCORES_I2C_PM
- OCOTP_ANA1
- OCOTP_CFG3
- OCOTP_CFG3_6ULL_SPEED_792MHZ
- OCOTP_CFG3_6ULL_SPEED_900MHZ
- OCOTP_CFG3_6UL_SPEED_696MHZ
- OCOTP_CFG3_MKT_SEGMENT_MASK
- OCOTP_CFG3_MKT_SEGMENT_SHIFT
- OCOTP_CFG3_SPEED_1P2GHZ
- OCOTP_CFG3_SPEED_852MHZ
- OCOTP_CFG3_SPEED_996MHZ
- OCOTP_CFG3_SPEED_GRADE_MASK
- OCOTP_CFG3_SPEED_GRADE_SHIFT
- OCOTP_CFG3_SPEED_SHIFT
- OCOTP_CTRL_ADDR
- OCOTP_CTRL_ADDR_MASK
- OCOTP_CTRL_BUSY
- OCOTP_CTRL_CLR
- OCOTP_CTRL_ERR
- OCOTP_CTRL_REG
- OCOTP_CTRL_RELOAD_SHADOWS
- OCOTP_CTRL_SET
- OCOTP_CTRL_WR_UNLOCK
- OCOTP_CTRL_WR_UNLOCK_KEY
- OCOTP_CTRL_WR_UNLOCK_MASK
- OCOTP_DATA
- OCOTP_DATA_OFFSET
- OCOTP_MEM0
- OCOTP_READ_CTRL_READ_FUSE
- OCOTP_READ_CTRL_REG
- OCOTP_READ_FUSE_DATA
- OCOTP_TIMEOUT
- OCOTP_TIMING
- OCOTP_TIMING_RELAX
- OCOTP_TIMING_RELAX_MASK
- OCOTP_TIMING_STROBE_PROG
- OCOTP_TIMING_STROBE_PROG_MASK
- OCOTP_TIMING_STROBE_READ
- OCOTP_TIMING_STROBE_READ_MASK
- OCOTP_UID_HIGH
- OCOTP_UID_LOW
- OCOTP_WORD_COUNT
- OCOTP_WORD_OFFSET
- OCP2SCP_TIMING
- OCPAR
- OCPAR_FLAG
- OCPAR_GPHY_READ_CMD
- OCPAR_GPHY_WRITE_CMD
- OCPBASE_DMEM_88XX
- OCPBASE_EMEM_88XX
- OCPBASE_TXBUF_88XX
- OCPC0
- OCPC0_MASK
- OCPC0_SHIFT
- OCPC1
- OCPC1_MASK
- OCPC1_SHIFT
- OCPC2
- OCPC2_MASK
- OCPC2_SHIFT
- OCPC3
- OCPC3_MASK
- OCPC3_SHIFT
- OCPC4
- OCPC4_MASK
- OCPC4_SHIFT
- OCPC5
- OCPC5_MASK
- OCPC5_SHIFT
- OCPC6
- OCPC6_MASK
- OCPC6_SHIFT
- OCPC7
- OCPC7_MASK
- OCPC7_SHIFT
- OCPCLR
- OCPCTL
- OCPDR
- OCPDR_DATA_MASK
- OCPDR_GPHY_REG_SHIFT
- OCPDR_READ_CMD
- OCPDR_REG_MASK
- OCPDR_WRITE_CMD
- OCPIF_CAN_BURST
- OCPIF_SWSUP_IDLE
- OCPI_BASE
- OCPI_CMD_FAULT
- OCPI_FAULT
- OCPI_PROT
- OCPI_SEC
- OCPI_SINT0
- OCPI_SINT1
- OCPI_TABORT
- OCPPARA1
- OCPPARA2
- OCPSTAT
- OCP_ADC_CFG
- OCP_ADC_IOFFSET
- OCP_ALDPS_CONFIG
- OCP_BASE_MII
- OCP_CMD_LOOP
- OCP_CMD_READ
- OCP_CMD_WRITE
- OCP_DOWN_SPEED
- OCP_EEE_ABLE
- OCP_EEE_ADV
- OCP_EEE_AR
- OCP_EEE_CFG
- OCP_EEE_CONFIG1
- OCP_EEE_CONFIG2
- OCP_EEE_CONFIG3
- OCP_EEE_DATA
- OCP_EEE_LPABLE
- OCP_EN
- OCP_ERR1_REG
- OCP_ERR2_REG
- OCP_ERR_IRQ
- OCP_LIMIT_HIGH
- OCP_MOD
- OCP_NCTL_CFG
- OCP_PHY_PATCH_CMD
- OCP_PHY_PATCH_STAT
- OCP_PHY_STATE
- OCP_PHY_STATUS
- OCP_POWER_CFG
- OCP_READY_MASK
- OCP_REG_CLK_POLARITY
- OCP_REG_CLK_PULL
- OCP_REG_CLK_TYPE
- OCP_REG_POLARITY
- OCP_SRAM_ADDR
- OCP_SRAM_DATA
- OCP_STATUS_MASK
- OCP_STATUS_NO_RESP
- OCP_STATUS_OK
- OCP_STATUS_REQ_FAILED
- OCP_STATUS_RESP_ERROR
- OCP_STD_PHY_BASE
- OCP_STS_REG
- OCP_SYSCLK_CFG
- OCP_SYSCONFIG
- OCP_THD_191_1080
- OCP_THD_244_946
- OCP_THD_283_783
- OCP_THD_315_417
- OCP_THD_MASK
- OCP_TIME_100
- OCP_TIME_1100
- OCP_TIME_200
- OCP_TIME_400
- OCP_TIME_60
- OCP_TIME_600
- OCP_TIME_800
- OCP_TIME_MASK
- OCP_USER_DSP
- OCP_USER_IVA
- OCP_USER_MPU
- OCP_USER_SDMA
- OCQ_WIN_OFFSET
- OCRAM_OCP_RESET
- OCRAM_RESET
- OCRDMA_ABI_USER_H
- OCRDMA_ABI_VERSION
- OCRDMA_ADDR_CHECK_DISABLE
- OCRDMA_ADDR_CHECK_ENABLE
- OCRDMA_AE_LSC_ER_MASK
- OCRDMA_AE_LSC_ER_SHIFT
- OCRDMA_AE_LSC_LD_MASK
- OCRDMA_AE_LSC_LD_SHIFT
- OCRDMA_AE_LSC_LLINK_DOWN
- OCRDMA_AE_LSC_LLINK_MASK
- OCRDMA_AE_LSC_LLINK_UP
- OCRDMA_AE_LSC_LS_MASK
- OCRDMA_AE_LSC_LS_SHIFT
- OCRDMA_AE_LSC_PLINK_DOWN
- OCRDMA_AE_LSC_PLINK_UP
- OCRDMA_AE_LSC_PORT_NUM_MASK
- OCRDMA_AE_LSC_PPF_MASK
- OCRDMA_AE_LSC_PPS_MASK
- OCRDMA_AE_LSC_PPS_SHIFT
- OCRDMA_AE_LSC_PT_MASK
- OCRDMA_AE_LSC_PT_SHIFT
- OCRDMA_AE_LSC_QOS_MASK
- OCRDMA_AE_LSC_QOS_SHIFT
- OCRDMA_AE_MCQE_AE
- OCRDMA_AE_MCQE_CQID_MASK
- OCRDMA_AE_MCQE_CQVALID
- OCRDMA_AE_MCQE_EVENT_CODE_MASK
- OCRDMA_AE_MCQE_EVENT_CODE_SHIFT
- OCRDMA_AE_MCQE_EVENT_TYPE_MASK
- OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT
- OCRDMA_AE_MCQE_QPID_MASK
- OCRDMA_AE_MCQE_QPVALID
- OCRDMA_AE_MCQE_VALID
- OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK
- OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT
- OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK
- OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT
- OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK
- OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT
- OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK
- OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT
- OCRDMA_AE_MPA_MCQE_REQ_ID_MASK
- OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT
- OCRDMA_AE_PVID_MCQE_ENABLED_MASK
- OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT
- OCRDMA_AE_PVID_MCQE_TAG_MASK
- OCRDMA_AE_PVID_MCQE_TAG_SHIFT
- OCRDMA_AE_QP_MCQE_EVENT_AE_MASK
- OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT
- OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK
- OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT
- OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK
- OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT
- OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK
- OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT
- OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK
- OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT
- OCRDMA_AE_QP_MCQE_QP_ID_MASK
- OCRDMA_AE_QP_MCQE_QP_ID_SHIFT
- OCRDMA_AH_ID_MASK
- OCRDMA_AH_L3_TYPE_MASK
- OCRDMA_AH_L3_TYPE_SHIFT
- OCRDMA_AH_TBL_PAGES
- OCRDMA_AH_VLAN_VALID_MASK
- OCRDMA_AH_VLAN_VALID_SHIFT
- OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK
- OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT
- OCRDMA_ALLOC_LKEY_FMR_MASK
- OCRDMA_ALLOC_LKEY_FMR_SHIFT
- OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK
- OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT
- OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK
- OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT
- OCRDMA_ALLOC_LKEY_PD_ID_MASK
- OCRDMA_ALLOC_LKEY_PD_ID_SHIFT
- OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK
- OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT
- OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK
- OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT
- OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK
- OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT
- OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK
- OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT
- OCRDMA_ALLOC_MW_PD_ID_MASK
- OCRDMA_ALLOC_MW_PD_ID_SHIFT
- OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK
- OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT
- OCRDMA_ALLOC_PD_ENABLE_DPP
- OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK
- OCRDMA_ALLOC_PD_RSP_DPP
- OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT
- OCRDMA_ALLOC_PD_RSP_PDID_MASK
- OCRDMA_APP_PARAM_APP_PROTO_MASK
- OCRDMA_APP_PARAM_PROTO_SEL_MASK
- OCRDMA_APP_PARAM_PROTO_SEL_SHIFT
- OCRDMA_APP_PARAM_VALID_MASK
- OCRDMA_APP_PARAM_VALID_SHIFT
- OCRDMA_ASIC_GEN_LANCER
- OCRDMA_ASIC_GEN_SKH_R
- OCRDMA_ASIC_REV_A0
- OCRDMA_ASIC_REV_B0
- OCRDMA_ASIC_REV_C0
- OCRDMA_ASPEED_SUPP_MASK
- OCRDMA_ASYNC_EVENT_COS_VALUE
- OCRDMA_ASYNC_EVENT_PVID_STATE
- OCRDMA_ASYNC_EVENT_QOS_VALUE
- OCRDMA_ASYNC_EVENT_TYPE
- OCRDMA_ASYNC_GRP5_EVE_CODE
- OCRDMA_ASYNC_LINK_EVE_CODE
- OCRDMA_ASYNC_RDMA_EVE_CODE
- OCRDMA_AV_VALID
- OCRDMA_AV_VLAN_VALID
- OCRDMA_BE_ROCE_ABI_VERSION
- OCRDMA_BIND_MW
- OCRDMA_CMD_ALLOC_LKEY
- OCRDMA_CMD_ALLOC_MW
- OCRDMA_CMD_ALLOC_PD
- OCRDMA_CMD_ALLOC_PD_RANGE
- OCRDMA_CMD_ATTACH_MCAST
- OCRDMA_CMD_CREATE_AH_TBL
- OCRDMA_CMD_CREATE_CQ
- OCRDMA_CMD_CREATE_EQ
- OCRDMA_CMD_CREATE_MQ
- OCRDMA_CMD_CREATE_MQ_EXT
- OCRDMA_CMD_CREATE_QP
- OCRDMA_CMD_CREATE_RBQ
- OCRDMA_CMD_CREATE_SRQ
- OCRDMA_CMD_DEALLOC_LKEY
- OCRDMA_CMD_DEALLOC_PD
- OCRDMA_CMD_DEALLOC_PD_RANGE
- OCRDMA_CMD_DELETE_AH_TBL
- OCRDMA_CMD_DELETE_CQ
- OCRDMA_CMD_DELETE_EQ
- OCRDMA_CMD_DELETE_MQ
- OCRDMA_CMD_DELETE_QP
- OCRDMA_CMD_DELETE_SRQ
- OCRDMA_CMD_DESTROY_RBQ
- OCRDMA_CMD_DETACH_MCAST
- OCRDMA_CMD_GET_CTRL_ATTRIBUTES
- OCRDMA_CMD_GET_DCBX_CONFIG
- OCRDMA_CMD_GET_FW_CONFIG
- OCRDMA_CMD_GET_FW_VER
- OCRDMA_CMD_GET_RDMA_STATS
- OCRDMA_CMD_MAX
- OCRDMA_CMD_MODIFY_EQ_DELAY
- OCRDMA_CMD_MODIFY_QP
- OCRDMA_CMD_MODIFY_SRQ
- OCRDMA_CMD_PHY_DETAILS
- OCRDMA_CMD_QUERY_CONFIG
- OCRDMA_CMD_QUERY_MW
- OCRDMA_CMD_QUERY_NSMR
- OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1
- OCRDMA_CMD_QUERY_QP
- OCRDMA_CMD_QUERY_SRQ
- OCRDMA_CMD_REGISTER_NSMR
- OCRDMA_CMD_REGISTER_NSMR_CONT
- OCRDMA_CMD_REREGISTER_NSMR
- OCRDMA_CMD_RSVD1
- OCRDMA_CMP_SWP
- OCRDMA_CQE_BAD_RESP_ERR
- OCRDMA_CQE_BUFTAG_MASK
- OCRDMA_CQE_BUFTAG_SHIFT
- OCRDMA_CQE_FATAL_ERR
- OCRDMA_CQE_GENERAL_ERR
- OCRDMA_CQE_IMM
- OCRDMA_CQE_INVALIDATE
- OCRDMA_CQE_INV_EECN_ERR
- OCRDMA_CQE_INV_EEC_STATE_ERR
- OCRDMA_CQE_LOC_ACCESS_ERR
- OCRDMA_CQE_LOC_EEC_OP_ERR
- OCRDMA_CQE_LOC_LEN_ERR
- OCRDMA_CQE_LOC_PROT_ERR
- OCRDMA_CQE_LOC_QP_OP_ERR
- OCRDMA_CQE_LOC_RDD_VIOL_ERR
- OCRDMA_CQE_MW_BIND_ERR
- OCRDMA_CQE_PKEY_MASK
- OCRDMA_CQE_PKEY_SHIFT
- OCRDMA_CQE_QPN_MASK
- OCRDMA_CQE_QPN_SHIFT
- OCRDMA_CQE_QTYPE
- OCRDMA_CQE_QTYPE_RQ
- OCRDMA_CQE_QTYPE_SQ
- OCRDMA_CQE_REM_ABORT_ERR
- OCRDMA_CQE_REM_ACCESS_ERR
- OCRDMA_CQE_REM_INV_RD_REQ_ERR
- OCRDMA_CQE_REM_INV_REQ_ERR
- OCRDMA_CQE_REM_OP_ERR
- OCRDMA_CQE_RESP_TIMEOUT_ERR
- OCRDMA_CQE_RETRY_EXC_ERR
- OCRDMA_CQE_RNR_RETRY_EXC_ERR
- OCRDMA_CQE_SRCQP_MASK
- OCRDMA_CQE_STATUS
- OCRDMA_CQE_STATUS_MASK
- OCRDMA_CQE_STATUS_SHIFT
- OCRDMA_CQE_SUCCESS
- OCRDMA_CQE_UD_L3TYPE_MASK
- OCRDMA_CQE_UD_L3TYPE_SHIFT
- OCRDMA_CQE_UD_STATUS_MASK
- OCRDMA_CQE_UD_STATUS_SHIFT
- OCRDMA_CQE_UD_XFER_LEN_MASK
- OCRDMA_CQE_UD_XFER_LEN_SHIFT
- OCRDMA_CQE_VALID
- OCRDMA_CQE_WQEIDX_MASK
- OCRDMA_CQE_WQEIDX_SHIFT
- OCRDMA_CQE_WRITE_IMM
- OCRDMA_CQE_WR_FLUSH_ERR
- OCRDMA_CQ_ERROR
- OCRDMA_CQ_OVERRUN_ERROR
- OCRDMA_CQ_PAGE_SIZE
- OCRDMA_CQ_QPCAT_ERROR
- OCRDMA_CREATE_AH_ENTRY_SIZE_MASK
- OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT
- OCRDMA_CREATE_AH_NUM_PAGES_MASK
- OCRDMA_CREATE_AH_NUM_PAGES_SHIFT
- OCRDMA_CREATE_AH_PAGE_SIZE_MASK
- OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT
- OCRDMA_CREATE_CQ_CMD_PDID_SHIFT
- OCRDMA_CREATE_CQ_CNT_SHIFT
- OCRDMA_CREATE_CQ_COALESCWM_MASK
- OCRDMA_CREATE_CQ_COALESCWM_SHIFT
- OCRDMA_CREATE_CQ_CQE_COUNT_MASK
- OCRDMA_CREATE_CQ_DEF_FLAGS
- OCRDMA_CREATE_CQ_DELAY_SHIFT
- OCRDMA_CREATE_CQ_DPP
- OCRDMA_CREATE_CQ_EQID_SHIFT
- OCRDMA_CREATE_CQ_EQ_ID_MASK
- OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID
- OCRDMA_CREATE_CQ_FLAGS_EVENTABLE
- OCRDMA_CREATE_CQ_FLAGS_NODELAY
- OCRDMA_CREATE_CQ_FLAGS_VALID
- OCRDMA_CREATE_CQ_MAX_PAGES
- OCRDMA_CREATE_CQ_PAGE_CNT_MASK
- OCRDMA_CREATE_CQ_PAGE_SIZE_MASK
- OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT
- OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK
- OCRDMA_CREATE_CQ_TYPE_SHIFT
- OCRDMA_CREATE_CQ_VER0
- OCRDMA_CREATE_CQ_VER2
- OCRDMA_CREATE_CQ_VER3
- OCRDMA_CREATE_EQ_CNT_SHIFT
- OCRDMA_CREATE_EQ_VALID
- OCRDMA_CREATE_MQ_ASYNC_CQ_VALID
- OCRDMA_CREATE_MQ_CQ_ID_SHIFT
- OCRDMA_CREATE_MQ_RING_SIZE_SHIFT
- OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT
- OCRDMA_CREATE_MQ_VALID
- OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK
- OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT
- OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK
- OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT
- OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT
- OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK
- OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT
- OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK
- OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT
- OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK
- OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT
- OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK
- OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT
- OCRDMA_CREATE_QP_REQ_FMR_EN_MASK
- OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT
- OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK
- OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT
- OCRDMA_CREATE_QP_REQ_INB_WREN_MASK
- OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK
- OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK
- OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK
- OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK
- OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK
- OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK
- OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT
- OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK
- OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT
- OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK
- OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT
- OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK
- OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT
- OCRDMA_CREATE_QP_REQ_PD_ID_MASK
- OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT
- OCRDMA_CREATE_QP_REQ_QPT_MASK
- OCRDMA_CREATE_QP_REQ_QPT_SHIFT
- OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK
- OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT
- OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK
- OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT
- OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT
- OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT
- OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK
- OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT
- OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK
- OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT
- OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK
- OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT
- OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK
- OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT
- OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK
- OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT
- OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK
- OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK
- OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT
- OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK
- OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK
- OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK
- OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK
- OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK
- OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK
- OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT
- OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK
- OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT
- OCRDMA_CREATE_QP_RSP_QP_ID_MASK
- OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT
- OCRDMA_CREATE_QP_RSP_RQ_ID_MASK
- OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT
- OCRDMA_CREATE_QP_RSP_SQ_ID_MASK
- OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT
- OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT
- OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK
- OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT
- OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK
- OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT
- OCRDMA_CREATE_SRQ_PD_ID_MASK
- OCRDMA_CREATE_SRQ_PD_ID_SHIFT
- OCRDMA_CREATE_SRQ_PG_SZ_MASK
- OCRDMA_CREATE_SRQ_PG_SZ_SHIFT
- OCRDMA_CREATE_SRQ_RQE_SIZE_MASK
- OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT
- OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK
- OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT
- OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK
- OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT
- OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK
- OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT
- OCRDMA_DB_CQ_NUM_POPPED_SHIFT
- OCRDMA_DB_CQ_OFFSET
- OCRDMA_DB_CQ_REARM_SHIFT
- OCRDMA_DB_CQ_RING_ID_EXT_MASK
- OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT
- OCRDMA_DB_CQ_RING_ID_MASK
- OCRDMA_DB_CQ_SOLICIT_SHIFT
- OCRDMA_DB_EQ_OFFSET
- OCRDMA_DB_ERRSTATS
- OCRDMA_DB_GEN2_RQ_OFFSET
- OCRDMA_DB_GEN2_SQ_OFFSET
- OCRDMA_DB_GEN2_SRQ_OFFSET
- OCRDMA_DB_MQ_OFFSET
- OCRDMA_DB_RQ_OFFSET
- OCRDMA_DB_RQ_SHIFT
- OCRDMA_DB_SQ_OFFSET
- OCRDMA_DB_SQ_SHIFT
- OCRDMA_DB_SRQ_OFFSET
- OCRDMA_DCBX_APP_ENTRY_SHIFT
- OCRDMA_DCBX_APP_PARAM
- OCRDMA_DCBX_OPCODE
- OCRDMA_DCBX_OP_PARAM_SHIFT
- OCRDMA_DCBX_PARAM_TYPE
- OCRDMA_DCBX_PROTO
- OCRDMA_DCBX_STATE_FLAGS
- OCRDMA_DCBX_STATE_MASK
- OCRDMA_DCBX_TC_SUPPORT_MASK
- OCRDMA_DCBX_TC_SUPPORT_SHIFT
- OCRDMA_DEFAULT_SERVICE_LEVEL
- OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK
- OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT
- OCRDMA_DESTROY_CQ_QID_MASK
- OCRDMA_DESTROY_CQ_QID_SHIFT
- OCRDMA_DESTROY_SRQ_ID_MASK
- OCRDMA_DESTROY_SRQ_ID_SHIFT
- OCRDMA_DEVICE_FATAL_EVENT
- OCRDMA_DPP_CQE_SIZE
- OCRDMA_DPP_PAGE_SIZE
- OCRDMA_DRV_STATS
- OCRDMA_EQE_FOR_CQE_MASK
- OCRDMA_EQE_MAJOR_CODE_MASK
- OCRDMA_EQE_MAJOR_CODE_SHIFT
- OCRDMA_EQE_RESOURCE_ID_MASK
- OCRDMA_EQE_RESOURCE_ID_SHIFT
- OCRDMA_EQE_VALID_MASK
- OCRDMA_EQE_VALID_SHIFT
- OCRDMA_EQ_CLR_SHIFT
- OCRDMA_EQ_ID_EXT_MASK
- OCRDMA_EQ_ID_EXT_MASK_SHIFT
- OCRDMA_EQ_ID_MASK
- OCRDMA_EQ_LEN
- OCRDMA_EQ_MINOR_OTHER
- OCRDMA_EQ_TYPE_SHIFT
- OCRDMA_EX_PHY_DETAILS_MASK
- OCRDMA_FETCH_ADD
- OCRDMA_FLAGS_LINK_STATUS_INIT
- OCRDMA_FLAG_AH_VLAN_PR
- OCRDMA_FLAG_FENCE_L
- OCRDMA_FLAG_FENCE_R
- OCRDMA_FLAG_IMM
- OCRDMA_FLAG_INV
- OCRDMA_FLAG_SIG
- OCRDMA_FLAG_SOLICIT
- OCRDMA_FN_MODE_RDMA
- OCRDMA_FR_MR
- OCRDMA_FSPEED_SUPP_MASK
- OCRDMA_FSPEED_SUPP_SHIFT
- OCRDMA_FUTURE_DETAILS_MASK
- OCRDMA_FUTURE_DETAILS_SHIFT
- OCRDMA_GEN2_CQ_PAGE_SIZE
- OCRDMA_GEN2_MAX_CQE
- OCRDMA_GEN2_WQE_SIZE
- OCRDMA_HBA_ATTRB_ASIC_GEN_MASK
- OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT
- OCRDMA_HBA_ATTRB_ASIC_REV_MASK
- OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT
- OCRDMA_HBA_ATTRB_CDBLEN_MASK
- OCRDMA_HBA_ATTRB_CV_MASK
- OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK
- OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT
- OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK
- OCRDMA_HBA_ATTRB_GUID0_MASK
- OCRDMA_HBA_ATTRB_GUID0_SHIFT
- OCRDMA_HBA_ATTRB_GUID13_MASK
- OCRDMA_HBA_ATTRB_GUID14_MASK
- OCRDMA_HBA_ATTRB_GUID14_SHIFT
- OCRDMA_HBA_ATTRB_GUID15_MASK
- OCRDMA_HBA_ATTRB_GUID15_SHIFT
- OCRDMA_HBA_ATTRB_HBA_ST_MASK
- OCRDMA_HBA_ATTRB_HBA_ST_SHIFT
- OCRDMA_HBA_ATTRB_IF_TYPE_MASK
- OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT
- OCRDMA_HBA_ATTRB_ISCSI_FET_MASK
- OCRDMA_HBA_ATTRB_ISCSI_VER_MASK
- OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT
- OCRDMA_HBA_ATTRB_LDTOUT_MASK
- OCRDMA_HBA_ATTRB_MAX_DOMS_MASK
- OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT
- OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK
- OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT
- OCRDMA_HBA_ATTRB_NETFIL_MASK
- OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK
- OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK
- OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT
- OCRDMA_HBA_ATTRB_PCI_DID_MASK
- OCRDMA_HBA_ATTRB_PCI_DID_SHIFT
- OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK
- OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT
- OCRDMA_HBA_ATTRB_PCI_SSID_MASK
- OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT
- OCRDMA_HBA_ATTRB_PCI_SVID_MASK
- OCRDMA_HBA_ATTRB_PCI_VID_MASK
- OCRDMA_HBA_ATTRB_PCNT_MASK
- OCRDMA_HBA_ATTRB_PCNT_SHIFT
- OCRDMA_HBA_ATTRB_PTNUM_MASK
- OCRDMA_HBA_ATTRB_PTNUM_SHIFT
- OCRDMA_HBA_ATTRB_PT_MASK
- OCRDMA_HBA_ATTRB_PT_SHIFT
- OCRDMA_IF_TYPE_MASK
- OCRDMA_IF_TYPE_SHIFT
- OCRDMA_L3_TYPE_IB_GRH
- OCRDMA_L3_TYPE_IPV4
- OCRDMA_L3_TYPE_IPV6
- OCRDMA_LINK_DUP_MASK
- OCRDMA_LINK_DUP_SHIFT
- OCRDMA_LINK_ST_MASK
- OCRDMA_LKEY_FLAG_LOCAL_WR
- OCRDMA_LKEY_FLAG_REMOTE_RD
- OCRDMA_LKEY_FLAG_REMOTE_WR
- OCRDMA_LKEY_FLAG_VATO
- OCRDMA_LKEY_INV
- OCRDMA_MAJOR_CODE_COMPLETION
- OCRDMA_MAJOR_CODE_SENTINAL
- OCRDMA_MAX_AH
- OCRDMA_MAX_ASYNC_ERRORS
- OCRDMA_MAX_CQ
- OCRDMA_MAX_CQE
- OCRDMA_MAX_CQE_ERR
- OCRDMA_MAX_DBGFS_MEM
- OCRDMA_MAX_QP
- OCRDMA_MAX_Q_PAGES
- OCRDMA_MAX_Q_PAGE_SIZE_CNT
- OCRDMA_MAX_SERVICE_LEVEL_INDEX
- OCRDMA_MAX_SGID
- OCRDMA_MAX_STAG
- OCRDMA_MAX_WQE_MEM_SIZE
- OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES
- OCRDMA_MBX_CQE_STATUS_DMA_FAILED
- OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES
- OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES
- OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER
- OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING
- OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK
- OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT
- OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK
- OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT
- OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK
- OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET
- OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK
- OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET
- OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK
- OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT
- OCRDMA_MBX_RSP_ASTATUS_MASK
- OCRDMA_MBX_RSP_ASTATUS_SHIFT
- OCRDMA_MBX_RSP_OPCODE_MASK
- OCRDMA_MBX_RSP_OPCODE_SHIFT
- OCRDMA_MBX_RSP_STATUS_MASK
- OCRDMA_MBX_RSP_STATUS_SHIFT
- OCRDMA_MBX_RSP_SUBSYS_MASK
- OCRDMA_MBX_RSP_SUBSYS_SHIFT
- OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP
- OCRDMA_MBX_STATUS_FAILED
- OCRDMA_MBX_STATUS_ILLEGAL_FIELD
- OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS
- OCRDMA_MBX_STATUS_INVALID_CHANGE
- OCRDMA_MBX_STATUS_INVALID_CQ
- OCRDMA_MBX_STATUS_INVALID_FBO
- OCRDMA_MBX_STATUS_INVALID_LENGTH
- OCRDMA_MBX_STATUS_INVALID_LKEY
- OCRDMA_MBX_STATUS_INVALID_PBE_SIZE
- OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY
- OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT
- OCRDMA_MBX_STATUS_INVALID_PD
- OCRDMA_MBX_STATUS_INVALID_QP
- OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER
- OCRDMA_MBX_STATUS_INVALID_SRQ_ID
- OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE
- OCRDMA_MBX_STATUS_INVALID_VA
- OCRDMA_MBX_STATUS_IRD_EXCEEDS
- OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS
- OCRDMA_MBX_STATUS_MTU_EXCEEDS
- OCRDMA_MBX_STATUS_MW_BOUND
- OCRDMA_MBX_STATUS_MW_STILL_BOUND
- OCRDMA_MBX_STATUS_OOR
- OCRDMA_MBX_STATUS_ORD_EXCEEDS
- OCRDMA_MBX_STATUS_PD_INUSE
- OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS
- OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID
- OCRDMA_MBX_STATUS_QP_BOUND
- OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS
- OCRDMA_MBX_STATUS_RQE_EXCEEDS
- OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS
- OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS
- OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS
- OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS
- OCRDMA_MBX_STATUS_SRQ_ERROR
- OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS
- OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS
- OCRDMA_MCH_OPCODE_MASK
- OCRDMA_MCH_OPCODE_SHIFT
- OCRDMA_MCH_SUBSYS_MASK
- OCRDMA_MCH_SUBSYS_SHIFT
- OCRDMA_MCQE_AE_MASK
- OCRDMA_MCQE_AE_SHIFT
- OCRDMA_MCQE_CMPL_MASK
- OCRDMA_MCQE_CMPL_SHIFT
- OCRDMA_MCQE_CONS_MASK
- OCRDMA_MCQE_CONS_SHIFT
- OCRDMA_MCQE_ESTATUS_MASK
- OCRDMA_MCQE_ESTATUS_SHIFT
- OCRDMA_MCQE_STATUS_MASK
- OCRDMA_MCQE_STATUS_SHIFT
- OCRDMA_MCQE_VALID_MASK
- OCRDMA_MCQE_VALID_SHIFT
- OCRDMA_MIN_HPAGE_SIZE
- OCRDMA_MIN_Q_PAGE_SIZE
- OCRDMA_MODIFY_QP_FLAGS_ATOMIC
- OCRDMA_MODIFY_QP_FLAGS_RD
- OCRDMA_MODIFY_QP_FLAGS_SEND
- OCRDMA_MODIFY_QP_FLAGS_WR
- OCRDMA_MODIFY_QP_ID_MASK
- OCRDMA_MODIFY_QP_ID_SHIFT
- OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK
- OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT
- OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK
- OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT
- OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK
- OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT
- OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK
- OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT
- OCRDMA_MODIFY_SRQ_ID_MASK
- OCRDMA_MODIFY_SRQ_ID_SHIFT
- OCRDMA_MODIFY_SRQ_LIMIT_SHIFT
- OCRDMA_MODIFY_SRQ_MAX_RQE_MASK
- OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT
- OCRDMA_MODIFY_SRQ__LIMIT_MASK
- OCRDMA_MQE_EMBEDDED
- OCRDMA_MQE_HDR_EMB_MASK
- OCRDMA_MQE_HDR_EMB_SHIFT
- OCRDMA_MQE_HDR_SGE_CNT_MASK
- OCRDMA_MQE_HDR_SGE_CNT_SHIFT
- OCRDMA_MQE_HDR_SPECIAL_MASK
- OCRDMA_MQE_HDR_SPECIAL_SHIFT
- OCRDMA_MQE_NONEMBEDDED
- OCRDMA_MQ_CQ_LEN
- OCRDMA_MQ_ID_MASK
- OCRDMA_MQ_LEN
- OCRDMA_MQ_NUM_MQE_SHIFT
- OCRDMA_NODE_DESC
- OCRDMA_NUM_EQE_SHIFT
- OCRDMA_PARAMETER_TYPE_ADMIN
- OCRDMA_PARAMETER_TYPE_OPER
- OCRDMA_PARAMETER_TYPE_PEER
- OCRDMA_PHYS_LINK_SPEED_100GBPS
- OCRDMA_PHYS_LINK_SPEED_100MBPS
- OCRDMA_PHYS_LINK_SPEED_10GBPS
- OCRDMA_PHYS_LINK_SPEED_10MBPS
- OCRDMA_PHYS_LINK_SPEED_1GBPS
- OCRDMA_PHYS_LINK_SPEED_20GBPS
- OCRDMA_PHYS_LINK_SPEED_25GBPS
- OCRDMA_PHYS_LINK_SPEED_40GBPS
- OCRDMA_PHYS_LINK_SPEED_ZERO
- OCRDMA_PHY_PFLT_MASK
- OCRDMA_PHY_PFLT_SHIFT
- OCRDMA_PHY_PS_MASK
- OCRDMA_PHY_PS_SHIFT
- OCRDMA_PHY_SPEED_100MBPS
- OCRDMA_PHY_SPEED_10GBPS
- OCRDMA_PHY_SPEED_10MBPS
- OCRDMA_PHY_SPEED_1GBPS
- OCRDMA_PHY_SPEED_40GBPS
- OCRDMA_PHY_SPEED_ZERO
- OCRDMA_PHY_TYPE_MASK
- OCRDMA_PLFC_MASK
- OCRDMA_PLFC_SHIFT
- OCRDMA_PLRFC_MASK
- OCRDMA_PLRFC_SHIFT
- OCRDMA_PLTFC_MASK
- OCRDMA_PLTFC_SHIFT
- OCRDMA_PORT_NUM_MASK
- OCRDMA_POST_RQ
- OCRDMA_PROTO_SELECT_L2
- OCRDMA_PROTO_SELECT_L4
- OCRDMA_PT_MASK
- OCRDMA_PT_SHIFT
- OCRDMA_QOS_LNKSP_MASK
- OCRDMA_QOS_LNKSP_SHIFT
- OCRDMA_QPS_ERR
- OCRDMA_QPS_INIT
- OCRDMA_QPS_RST
- OCRDMA_QPS_RTR
- OCRDMA_QPS_RTS
- OCRDMA_QPS_SQD
- OCRDMA_QPS_SQE
- OCRDMA_QPS_SQ_DRAINING
- OCRDMA_QPT_GSI
- OCRDMA_QPT_RC
- OCRDMA_QPT_UD
- OCRDMA_QP_ACCESS_ERROR
- OCRDMA_QP_COMM_EST_EVENT
- OCRDMA_QP_FAST_REG
- OCRDMA_QP_INB_RD
- OCRDMA_QP_INB_WR
- OCRDMA_QP_LAST_WQE_EVENT
- OCRDMA_QP_LKEY0
- OCRDMA_QP_MW_BIND
- OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK
- OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT
- OCRDMA_QP_PARAMS_DEST_QPN_MASK
- OCRDMA_QP_PARAMS_DEST_QPN_SHIFT
- OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK
- OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT
- OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN
- OCRDMA_QP_PARAMS_FLAGS_FMR_EN
- OCRDMA_QP_PARAMS_FLAGS_INBRD_EN
- OCRDMA_QP_PARAMS_FLAGS_INBWR_EN
- OCRDMA_QP_PARAMS_FLAGS_INB_ATEN
- OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK
- OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT
- OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN
- OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC
- OCRDMA_QP_PARAMS_FLOW_LABEL_MASK
- OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT
- OCRDMA_QP_PARAMS_HOP_LMT_MASK
- OCRDMA_QP_PARAMS_HOP_LMT_SHIFT
- OCRDMA_QP_PARAMS_MAX_IRD_MASK
- OCRDMA_QP_PARAMS_MAX_IRD_SHIFT
- OCRDMA_QP_PARAMS_MAX_ORD_MASK
- OCRDMA_QP_PARAMS_MAX_ORD_SHIFT
- OCRDMA_QP_PARAMS_MAX_RQE_MASK
- OCRDMA_QP_PARAMS_MAX_RQE_SHIFT
- OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK
- OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT
- OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK
- OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT
- OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK
- OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT
- OCRDMA_QP_PARAMS_MAX_WQE_MASK
- OCRDMA_QP_PARAMS_MAX_WQE_SHIFT
- OCRDMA_QP_PARAMS_PATH_MTU_MASK
- OCRDMA_QP_PARAMS_PATH_MTU_SHIFT
- OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT
- OCRDMA_QP_PARAMS_PKEY_INDEX_MASK
- OCRDMA_QP_PARAMS_RETRY_CNT_MASK
- OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT
- OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK
- OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT
- OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK
- OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT
- OCRDMA_QP_PARAMS_RQ_CQID_MASK
- OCRDMA_QP_PARAMS_RQ_CQID_SHIFT
- OCRDMA_QP_PARAMS_RQ_PSN_MASK
- OCRDMA_QP_PARAMS_RQ_PSN_SHIFT
- OCRDMA_QP_PARAMS_SL_MASK
- OCRDMA_QP_PARAMS_SL_SHIFT
- OCRDMA_QP_PARAMS_SQ_PSN_MASK
- OCRDMA_QP_PARAMS_SQ_PSN_SHIFT
- OCRDMA_QP_PARAMS_SRQ_ID_MASK
- OCRDMA_QP_PARAMS_SRQ_ID_SHIFT
- OCRDMA_QP_PARAMS_STATE_MASK
- OCRDMA_QP_PARAMS_STATE_SHIFT
- OCRDMA_QP_PARAMS_TCLASS_MASK
- OCRDMA_QP_PARAMS_TCLASS_SHIFT
- OCRDMA_QP_PARAMS_VLAN_MASK
- OCRDMA_QP_PARAMS_VLAN_SHIFT
- OCRDMA_QP_PARAMS_WQ_CQID_MASK
- OCRDMA_QP_PARAMS_WQ_CQID_SHIFT
- OCRDMA_QP_PARA_ACK_TO_VALID
- OCRDMA_QP_PARA_BIND_EN_VALID
- OCRDMA_QP_PARA_DST_QPN_VALID
- OCRDMA_QP_PARA_FLOW_LBL_VALID
- OCRDMA_QP_PARA_FMR_EN_VALID
- OCRDMA_QP_PARA_INBAT_EN_VALID
- OCRDMA_QP_PARA_INB_RDEN_VALID
- OCRDMA_QP_PARA_INB_WREN_VALID
- OCRDMA_QP_PARA_MAX_IRD_VALID
- OCRDMA_QP_PARA_MAX_ORD_VALID
- OCRDMA_QP_PARA_MAX_RQE_VALID
- OCRDMA_QP_PARA_MAX_WQE_VALID
- OCRDMA_QP_PARA_PKEY_VALID
- OCRDMA_QP_PARA_PMTU_VALID
- OCRDMA_QP_PARA_QKEY_VALID
- OCRDMA_QP_PARA_QPS_VALID
- OCRDMA_QP_PARA_RETRY_CNT_VALID
- OCRDMA_QP_PARA_RNT_VALID
- OCRDMA_QP_PARA_RQPSN_VALID
- OCRDMA_QP_PARA_RRC_VALID
- OCRDMA_QP_PARA_SGE_RECV_VALID
- OCRDMA_QP_PARA_SGE_SEND_VALID
- OCRDMA_QP_PARA_SGE_WR_VALID
- OCRDMA_QP_PARA_SQD_ASYNC_VALID
- OCRDMA_QP_PARA_SQPSN_VALID
- OCRDMA_QP_PARA_VLAN_EN_VALID
- OCRDMA_QP_PARA_ZLKEY_EN_VALID
- OCRDMA_QUERY_SRQ_ID_MASK
- OCRDMA_QUERY_SRQ_ID_SHIFT
- OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK
- OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT
- OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK
- OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT
- OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK
- OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT
- OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK
- OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT
- OCRDMA_QUERY_UP_QP_ID_MASK
- OCRDMA_QUERY_UP_QP_ID_SHIFT
- OCRDMA_Q_PAGE_BASE_SIZE
- OCRDMA_READ
- OCRDMA_REARM_SHIFT
- OCRDMA_REG_NSMR_BIND_MEMWIN_MASK
- OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT
- OCRDMA_REG_NSMR_CONT_LAST_MASK
- OCRDMA_REG_NSMR_CONT_LAST_SHIFT
- OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK
- OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT
- OCRDMA_REG_NSMR_CONT_PBL_SHIFT
- OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK
- OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK
- OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT
- OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK
- OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT
- OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK
- OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT
- OCRDMA_REG_NSMR_HPAGE_SIZE_MASK
- OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT
- OCRDMA_REG_NSMR_LAST_MASK
- OCRDMA_REG_NSMR_LAST_SHIFT
- OCRDMA_REG_NSMR_LOCAL_WR_MASK
- OCRDMA_REG_NSMR_LOCAL_WR_SHIFT
- OCRDMA_REG_NSMR_LRKEY_INDEX_MASK
- OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT
- OCRDMA_REG_NSMR_LRKEY_MASK
- OCRDMA_REG_NSMR_LRKEY_SHIFT
- OCRDMA_REG_NSMR_NUM_PBL_MASK
- OCRDMA_REG_NSMR_NUM_PBL_SHIFT
- OCRDMA_REG_NSMR_PBE_SIZE_MASK
- OCRDMA_REG_NSMR_PBE_SIZE_SHIFT
- OCRDMA_REG_NSMR_PD_ID_MASK
- OCRDMA_REG_NSMR_PD_ID_SHIFT
- OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK
- OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT
- OCRDMA_REG_NSMR_REMOTE_INV_MASK
- OCRDMA_REG_NSMR_REMOTE_INV_SHIFT
- OCRDMA_REG_NSMR_REMOTE_RD_MASK
- OCRDMA_REG_NSMR_REMOTE_RD_SHIFT
- OCRDMA_REG_NSMR_REMOTE_WR_MASK
- OCRDMA_REG_NSMR_REMOTE_WR_SHIFT
- OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK
- OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT
- OCRDMA_REG_NSMR_ZB_SHIFT
- OCRDMA_REG_NSMR_ZB_SHIFT_MASK
- OCRDMA_RESET_STATS
- OCRDMA_RESV0
- OCRDMA_RESV1
- OCRDMA_ROCE_DRV_DESC
- OCRDMA_ROCE_DRV_VERSION
- OCRDMA_RSRC_STATS
- OCRDMA_RXQP_ERRSTATS
- OCRDMA_RXSTATS
- OCRDMA_RX_DBG_STATS
- OCRDMA_SEND
- OCRDMA_SLI_ASIC_GEN_NUM_MASK
- OCRDMA_SLI_ASIC_GEN_NUM_SHIFT
- OCRDMA_SLI_ASIC_ID_OFFSET
- OCRDMA_SLI_ASIC_REV_MASK
- OCRDMA_SQ_DRAINED_EVENT
- OCRDMA_SRQCAT_ERROR
- OCRDMA_SRQ_LIMIT_EVENT
- OCRDMA_STATE_FLAG_ADDVERTISED
- OCRDMA_STATE_FLAG_ENABLED
- OCRDMA_STATE_FLAG_NEG_FAILD
- OCRDMA_STATE_FLAG_SYNC
- OCRDMA_STATE_FLAG_UNSUPPORTED
- OCRDMA_STATE_FLAG_WILLING
- OCRDMA_STATS_TYPE
- OCRDMA_SUBSYS_COMMON
- OCRDMA_SUBSYS_DCBX
- OCRDMA_SUBSYS_ROCE
- OCRDMA_TCV_AEV_OPV_ST
- OCRDMA_TXQP_ERRSTATS
- OCRDMA_TXSTATS
- OCRDMA_TX_DBG_STATS
- OCRDMA_TYPE_INLINE
- OCRDMA_TYPE_LKEY
- OCRDMA_UVERBS
- OCRDMA_VID_PCP_SHIFT
- OCRDMA_WQESTATS
- OCRDMA_WQE_ALIGN_BYTES
- OCRDMA_WQE_FLAGS_SHIFT
- OCRDMA_WQE_LKEY_FLAGS_MASK
- OCRDMA_WQE_LKEY_FLAGS_SHIFT
- OCRDMA_WQE_NXT_WQE_SIZE_SHIFT
- OCRDMA_WQE_OPCODE
- OCRDMA_WQE_OPCODE_MASK
- OCRDMA_WQE_OPCODE_SHIFT
- OCRDMA_WQE_SIZE
- OCRDMA_WQE_SIZE_MASK
- OCRDMA_WQE_SIZE_SHIFT
- OCRDMA_WQE_STRIDE
- OCRDMA_WQE_TYPE_MASK
- OCRDMA_WQE_TYPE_SHIFT
- OCRDMA_WRITE
- OCRNL
- OCR_CONTEXT
- OCR_DEBUG
- OCR_DEFAULT
- OCR_MODE_BIPHASE
- OCR_MODE_CLOCK
- OCR_MODE_MASK
- OCR_MODE_NORMAL
- OCR_MODE_TEST
- OCR_TX0_INVERT
- OCR_TX0_PULLDOWN
- OCR_TX0_PULLUP
- OCR_TX0_PUSHPULL
- OCR_TX1_INVERT
- OCR_TX1_PULLDOWN
- OCR_TX1_PULLUP
- OCR_TX1_PUSHPULL
- OCR_TX_MASK
- OCR_TX_SHIFT
- OCSC_HW_CGC_EN
- OCSD_MIN_VER
- OCSEL
- OCSEL_OCSRC_ENABLE
- OCSEL_OCSRC_OSCIN
- OCSEL_OCSRC_PLL0_SYSCLK
- OCSEL_OCSRC_PLL1_OBSCLK
- OCSEL_OCSRC_PLL1_SYSCLK
- OCSPI_FRM_ERR
- OCSPI_PAR_ERROR_F
- OCSPI_PAR_ERROR_S
- OCSPI_PAR_ERROR_V
- OCS_ABORTED
- OCS_EN
- OCS_FATAL_ERROR
- OCS_INVALID_CMD_TABLE_ATTR
- OCS_INVALID_COMMAND_STATUS
- OCS_INVALID_PRDT_ATTR
- OCS_MISMATCH_DATA_BUF_SIZE
- OCS_MISMATCH_RESP_UPIU_SIZE
- OCS_PEER_COMM_FAILURE
- OCS_SUCCESS
- OCTA_CRC
- OCTA_CRC_CHUNK
- OCTA_CRC_IN_EN
- OCTA_CRC_OUT_EN
- OCTEON_32BYTE_INSTR
- OCTEON_38XX_FAMILY_MASK
- OCTEON_38XX_FAMILY_REV_MASK
- OCTEON_38XX_MODEL_MASK
- OCTEON_38XX_MODEL_REV_MASK
- OCTEON_58XX_FAMILY_MASK
- OCTEON_58XX_FAMILY_REV_MASK
- OCTEON_58XX_MODEL_MASK
- OCTEON_58XX_MODEL_MINOR_REV_MASK
- OCTEON_58XX_MODEL_REV_MASK
- OCTEON_5XXX_MODEL_MASK
- OCTEON_64BYTE_INSTR
- OCTEON_ALL_INTR
- OCTEON_ARGV_MAX_ARGS
- OCTEON_BAR1_ENTRY_SIZE
- OCTEON_BAR2_PCI_ADDRESS
- OCTEON_BL_FLAG_BREAK
- OCTEON_BL_FLAG_CONSOLE_PCI
- OCTEON_BL_FLAG_CONSOLE_UART1
- OCTEON_BL_FLAG_DEBUG
- OCTEON_BL_FLAG_NO_MAGIC
- OCTEON_BOOT_MOVEABLE_MAGIC1
- OCTEON_CF_BUSY_POLL_INTERVAL
- OCTEON_CN2350_10GB_SUBSYS_ID_1
- OCTEON_CN2350_10GB_SUBSYS_ID_2
- OCTEON_CN2350_25GB_SUBSYS_ID
- OCTEON_CN2360_10GB_SUBSYS_ID
- OCTEON_CN2360_25GB_SUBSYS_ID
- OCTEON_CN23XX_PCIID_PF
- OCTEON_CN23XX_PF
- OCTEON_CN23XX_PF_VID
- OCTEON_CN23XX_REV_1_0
- OCTEON_CN23XX_REV_1_1
- OCTEON_CN23XX_REV_2_0
- OCTEON_CN23XX_VF
- OCTEON_CN23XX_VF_VID
- OCTEON_CN3005
- OCTEON_CN3005_PASS1
- OCTEON_CN3005_PASS1_0
- OCTEON_CN3005_PASS1_1
- OCTEON_CN3010
- OCTEON_CN3010_PASS1
- OCTEON_CN3010_PASS1_0
- OCTEON_CN3010_PASS1_1
- OCTEON_CN3020
- OCTEON_CN3020_PASS1
- OCTEON_CN3020_PASS1_0
- OCTEON_CN3020_PASS1_1
- OCTEON_CN30XX
- OCTEON_CN30XX_PASS1
- OCTEON_CN30XX_PASS1_1
- OCTEON_CN31XX
- OCTEON_CN31XX_PASS1
- OCTEON_CN31XX_PASS1_1
- OCTEON_CN36XX
- OCTEON_CN36XX_PASS2
- OCTEON_CN36XX_PASS3
- OCTEON_CN38XX
- OCTEON_CN38XX_PASS1
- OCTEON_CN38XX_PASS2
- OCTEON_CN38XX_PASS3
- OCTEON_CN3XXX
- OCTEON_CN50XX
- OCTEON_CN50XX_PASS1
- OCTEON_CN50XX_PASS1_0
- OCTEON_CN50XX_PASS1_X
- OCTEON_CN52XX
- OCTEON_CN52XX_PASS1
- OCTEON_CN52XX_PASS1_0
- OCTEON_CN52XX_PASS1_X
- OCTEON_CN52XX_PASS2
- OCTEON_CN52XX_PASS2_0
- OCTEON_CN52XX_PASS2_X
- OCTEON_CN54XX
- OCTEON_CN54XX_PASS1
- OCTEON_CN54XX_PASS2
- OCTEON_CN55XX
- OCTEON_CN55XX_PASS1
- OCTEON_CN55XX_PASS2
- OCTEON_CN56XX
- OCTEON_CN56XX_PASS1
- OCTEON_CN56XX_PASS1_0
- OCTEON_CN56XX_PASS1_1
- OCTEON_CN56XX_PASS1_X
- OCTEON_CN56XX_PASS2
- OCTEON_CN56XX_PASS2_0
- OCTEON_CN56XX_PASS2_1
- OCTEON_CN56XX_PASS2_X
- OCTEON_CN57XX
- OCTEON_CN57XX_PASS1
- OCTEON_CN57XX_PASS2
- OCTEON_CN58XX
- OCTEON_CN58XX_PASS1
- OCTEON_CN58XX_PASS1_0
- OCTEON_CN58XX_PASS1_1
- OCTEON_CN58XX_PASS1_2
- OCTEON_CN58XX_PASS1_X
- OCTEON_CN58XX_PASS2
- OCTEON_CN58XX_PASS2_0
- OCTEON_CN58XX_PASS2_1
- OCTEON_CN58XX_PASS2_2
- OCTEON_CN58XX_PASS2_3
- OCTEON_CN58XX_PASS2_X
- OCTEON_CN5XXX
- OCTEON_CN60XX
- OCTEON_CN61XX
- OCTEON_CN61XX_PASS1_0
- OCTEON_CN61XX_PASS1_1
- OCTEON_CN61XX_PASS1_X
- OCTEON_CN62XX
- OCTEON_CN63XX
- OCTEON_CN63XX_PASS1_0
- OCTEON_CN63XX_PASS1_1
- OCTEON_CN63XX_PASS1_2
- OCTEON_CN63XX_PASS1_X
- OCTEON_CN63XX_PASS2_0
- OCTEON_CN63XX_PASS2_1
- OCTEON_CN63XX_PASS2_2
- OCTEON_CN63XX_PASS2_X
- OCTEON_CN66XX
- OCTEON_CN66XX_PASS1_0
- OCTEON_CN66XX_PASS1_2
- OCTEON_CN66XX_PASS1_X
- OCTEON_CN66XX_PCIID
- OCTEON_CN68XX
- OCTEON_CN68XX_PASS1
- OCTEON_CN68XX_PASS1_0
- OCTEON_CN68XX_PASS1_1
- OCTEON_CN68XX_PASS1_2
- OCTEON_CN68XX_PASS1_X
- OCTEON_CN68XX_PASS2
- OCTEON_CN68XX_PASS2_0
- OCTEON_CN68XX_PASS2_1
- OCTEON_CN68XX_PASS2_2
- OCTEON_CN68XX_PASS2_X
- OCTEON_CN68XX_PCIID
- OCTEON_CN6XXX
- OCTEON_CN70XX
- OCTEON_CN70XX_PASS1_0
- OCTEON_CN70XX_PASS1_1
- OCTEON_CN70XX_PASS1_2
- OCTEON_CN70XX_PASS1_X
- OCTEON_CN70XX_PASS2_0
- OCTEON_CN70XX_PASS2_X
- OCTEON_CN71XX
- OCTEON_CN73XX
- OCTEON_CN73XX_PASS1_0
- OCTEON_CN73XX_PASS1_1
- OCTEON_CN73XX_PASS1_X
- OCTEON_CN76XX
- OCTEON_CN78XX
- OCTEON_CN78XX_PASS1_0
- OCTEON_CN78XX_PASS1_1
- OCTEON_CN78XX_PASS1_X
- OCTEON_CN78XX_PASS2_0
- OCTEON_CN78XX_PASS2_X
- OCTEON_CN7XXX
- OCTEON_CNF71XX
- OCTEON_CNF71XX_PASS1_0
- OCTEON_CNF71XX_PASS1_1
- OCTEON_CNF71XX_PASS1_X
- OCTEON_CNF75XX
- OCTEON_CNF75XX_PASS1_0
- OCTEON_CNF75XX_PASS1_X
- OCTEON_CNF7XXX
- OCTEON_CONFIG_TYPE_DEFAULT
- OCTEON_CONSOLE_MAX_READ_BYTES
- OCTEON_CONSOLE_POLL_INTERVAL_MS
- OCTEON_CR_OPCODE_PRIORITY
- OCTEON_DDR0_BASE
- OCTEON_DDR0_SIZE
- OCTEON_DDR1_BASE
- OCTEON_DDR1_SIZE
- OCTEON_DDR2_BASE
- OCTEON_DDR2_SIZE
- OCTEON_DMA_BAR_TYPE_BIG
- OCTEON_DMA_BAR_TYPE_INVALID
- OCTEON_DMA_BAR_TYPE_PCIE
- OCTEON_DMA_BAR_TYPE_PCIE2
- OCTEON_DMA_BAR_TYPE_SMALL
- OCTEON_DMA_INTR_PKT
- OCTEON_DMA_INTR_TIME
- OCTEON_DONE_SC_LIST
- OCTEON_ETHERNET_H
- OCTEON_FAMILY_MASK
- OCTEON_FEATURE_CIU2
- OCTEON_FEATURE_CIU3
- OCTEON_FEATURE_CN68XX_WQE
- OCTEON_FEATURE_DFA
- OCTEON_FEATURE_DFM
- OCTEON_FEATURE_DORM_CRYPTO
- OCTEON_FEATURE_FAU
- OCTEON_FEATURE_FPA3
- OCTEON_FEATURE_HFA
- OCTEON_FEATURE_ILK
- OCTEON_FEATURE_KEY_MEMORY
- OCTEON_FEATURE_LED_CONTROLLER
- OCTEON_FEATURE_MDIO_CLAUSE_45
- OCTEON_FEATURE_MGMT_PORT
- OCTEON_FEATURE_NO_WPTR
- OCTEON_FEATURE_NPEI
- OCTEON_FEATURE_PCIE
- OCTEON_FEATURE_PKND
- OCTEON_FEATURE_RAID
- OCTEON_FEATURE_SAAD
- OCTEON_FEATURE_SRIO
- OCTEON_FEATURE_TRA
- OCTEON_FEATURE_USB
- OCTEON_FEATURE_ZIP
- OCTEON_GET_VF_STATS
- OCTEON_HAS_CRYPTO
- OCTEON_H_CLKDIV_SEL
- OCTEON_INPUT_INTR
- OCTEON_IRQ_5
- OCTEON_IRQ_LAST
- OCTEON_IRQ_MBOX0
- OCTEON_IRQ_MBOX1
- OCTEON_IRQ_MBOX2
- OCTEON_IRQ_MBOX3
- OCTEON_IRQ_MSI_BIT0
- OCTEON_IRQ_MSI_LAST
- OCTEON_IRQ_PCI_INT0
- OCTEON_IRQ_PCI_INT1
- OCTEON_IRQ_PCI_INT2
- OCTEON_IRQ_PCI_INT3
- OCTEON_IRQ_PCI_MSI0
- OCTEON_IRQ_PCI_MSI1
- OCTEON_IRQ_PCI_MSI2
- OCTEON_IRQ_PCI_MSI3
- OCTEON_IRQ_PERF
- OCTEON_IRQ_RML
- OCTEON_IRQ_SW0
- OCTEON_IRQ_SW1
- OCTEON_IRQ_TIMER
- OCTEON_IRQ_TIMER0
- OCTEON_IRQ_TIMER1
- OCTEON_IRQ_TIMER2
- OCTEON_IRQ_TIMER3
- OCTEON_IRQ_TWSI
- OCTEON_IRQ_TWSI2
- OCTEON_IRQ_WDOG0
- OCTEON_IRQ_WORKQ0
- OCTEON_IS_COMMON_BINARY
- OCTEON_IS_MODEL
- OCTEON_IS_OCTEON1
- OCTEON_IS_OCTEON1PLUS
- OCTEON_IS_OCTEON2
- OCTEON_IS_OCTEON3
- OCTEON_IS_OCTEONPLUS
- OCTEON_MAJOR_REV
- OCTEON_MAX_BASE_IOQ
- OCTEON_MAX_FEATURE
- OCTEON_MAX_H_CLK_RATE
- OCTEON_MAX_MC
- OCTEON_MAX_MTU
- OCTEON_MAX_PHY_MEM_SIZE
- OCTEON_MBOX_DATA_MAX
- OCTEON_MBOX_INTR
- OCTEON_MBOX_REQUEST
- OCTEON_MBOX_RESPONSE
- OCTEON_MBOX_STATE_ERROR
- OCTEON_MBOX_STATE_IDLE
- OCTEON_MBOX_STATE_REQUEST_RECEIVED
- OCTEON_MBOX_STATE_REQUEST_RECEIVING
- OCTEON_MBOX_STATE_RESPONSE_PENDING
- OCTEON_MBOX_STATE_RESPONSE_RECEIVED
- OCTEON_MBOX_STATE_RESPONSE_RECEIVING
- OCTEON_MBOX_STATUS_BUSY
- OCTEON_MBOX_STATUS_FAILED
- OCTEON_MBOX_STATUS_SUCCESS
- OCTEON_MGMT_NAPI_WEIGHT
- OCTEON_MGMT_RX_HEADROOM
- OCTEON_MGMT_RX_RING_SIZE
- OCTEON_MGMT_TX_RING_SIZE
- OCTEON_MINOR_REV
- OCTEON_MIN_H_CLK_RATE
- OCTEON_MODEL
- OCTEON_MSI_INT_HANDLER_X
- OCTEON_OPCODE_MASK
- OCTEON_ORDERED_LIST
- OCTEON_ORDERED_SC_LIST
- OCTEON_OUTPUT_INTR
- OCTEON_PCI_32BIT_BYTE_SWAP
- OCTEON_PCI_32BIT_LW_SWAP
- OCTEON_PCI_64BIT_SWAP
- OCTEON_PCI_BAR1_HOLE_BITS
- OCTEON_PCI_BAR1_HOLE_SIZE
- OCTEON_PCI_CONSOLE_BLOCK_NAME
- OCTEON_PCI_CONSOLE_MAJOR_VERSION
- OCTEON_PCI_CONSOLE_MINOR_VERSION
- OCTEON_PCI_IOSPACE_BASE
- OCTEON_PCI_IOSPACE_SIZE
- OCTEON_PCI_IO_BUF_OWNER_HOST
- OCTEON_PCI_IO_BUF_OWNER_OCTEON
- OCTEON_PCI_MEMSPACE_OFFSET
- OCTEON_PCI_PASSTHROUGH
- OCTEON_PFVFACK
- OCTEON_PFVFERR
- OCTEON_PFVFSIG
- OCTEON_PF_CHANGED_VF_MACADDR
- OCTEON_PRID_MASK
- OCTEON_REQUEST_DONE
- OCTEON_REQUEST_INTERRUPTED
- OCTEON_REQUEST_INVALID_BUFCNT
- OCTEON_REQUEST_INVALID_BUFSIZE
- OCTEON_REQUEST_INVALID_IQ
- OCTEON_REQUEST_INVALID_RESP_ORDER
- OCTEON_REQUEST_NOT_RUNNING
- OCTEON_REQUEST_NO_DEVICE
- OCTEON_REQUEST_NO_IQ_SPACE
- OCTEON_REQUEST_NO_MEMORY
- OCTEON_REQUEST_NO_PENDING_ENTRY
- OCTEON_REQUEST_NO_PERMISSION
- OCTEON_REQUEST_PENDING
- OCTEON_REQUEST_TIMEOUT
- OCTEON_RESP_NORESPONSE
- OCTEON_RESP_ORDERED
- OCTEON_RESP_UNORDERED
- OCTEON_SERIAL_LEN
- OCTEON_SPI_CFG
- OCTEON_SPI_DAT0
- OCTEON_SPI_MAX_BYTES
- OCTEON_SPI_MAX_CLOCK_HZ
- OCTEON_SPI_STS
- OCTEON_SPI_TX
- OCTEON_SYNCW_STR
- OCTEON_UBOOT_VER_BUF_SIZE
- OCTEON_UNORDERED_BLOCKING_LIST
- OCTEON_UNORDERED_NONBLOCKING_LIST
- OCTEON_VF_ACTIVE
- OCTEON_VF_FLR_REQUEST
- OCTEON_ZOMBIE_SC_LIST
- OCTNET_CMD_ADD_VLAN_FILTER
- OCTNET_CMD_CHANGE_DEVFLAGS
- OCTNET_CMD_CHANGE_MACADDR
- OCTNET_CMD_CHANGE_MTU
- OCTNET_CMD_CLEAR_STATS
- OCTNET_CMD_DELETE_SA
- OCTNET_CMD_DEL_VLAN_FILTER
- OCTNET_CMD_FAIL
- OCTNET_CMD_GPIO_ACCESS
- OCTNET_CMD_GROUP1
- OCTNET_CMD_ID_ACTIVE
- OCTNET_CMD_IPSECV2_AH_ESP_CTL
- OCTNET_CMD_LRO_DISABLE
- OCTNET_CMD_LRO_ENABLE
- OCTNET_CMD_MDIO_READ_WRITE
- OCTNET_CMD_Q
- OCTNET_CMD_QUEUE_COUNT_CTL
- OCTNET_CMD_RXCSUM_DISABLE
- OCTNET_CMD_RXCSUM_ENABLE
- OCTNET_CMD_RX_CTL
- OCTNET_CMD_SET_FLOW_CTL
- OCTNET_CMD_SET_MULTI_LIST
- OCTNET_CMD_SET_RSS
- OCTNET_CMD_SET_SETTINGS
- OCTNET_CMD_SET_UC_LIST
- OCTNET_CMD_SET_VF_LINKSTATE
- OCTNET_CMD_SET_VF_SPOOFCHK
- OCTNET_CMD_SIZE
- OCTNET_CMD_TNL_RX_CSUM_CTL
- OCTNET_CMD_TNL_TX_CSUM_CTL
- OCTNET_CMD_TXCSUM_DISABLE
- OCTNET_CMD_TXCSUM_ENABLE
- OCTNET_CMD_UPDATE_SA
- OCTNET_CMD_VERBOSE_DISABLE
- OCTNET_CMD_VERBOSE_ENABLE
- OCTNET_CMD_VLAN_FILTER_CTL
- OCTNET_CMD_VLAN_FILTER_DISABLE
- OCTNET_CMD_VLAN_FILTER_ENABLE
- OCTNET_CMD_VXLAN_PORT_ADD
- OCTNET_CMD_VXLAN_PORT_CONFIG
- OCTNET_CMD_VXLAN_PORT_DEL
- OCTNET_CMD_WRITE_SA
- OCTNET_DEFAULT_FRM_SIZE
- OCTNET_DEFAULT_MTU
- OCTNET_FRM_HEADER_SIZE
- OCTNET_FRM_LENGTH_SIZE
- OCTNET_FRM_PTP_HEADER_SIZE
- OCTNET_GROUP1_LAST_CMD
- OCTNET_IFFLAG_ALLMULTI
- OCTNET_IFFLAG_BROADCAST
- OCTNET_IFFLAG_MULTICAST
- OCTNET_IFFLAG_PROMISC
- OCTNET_IFFLAG_UNICAST
- OCTNET_MAX_FRM_SIZE
- OCTNET_MIN_FRM_SIZE
- OCTNIC_GSO_MAX_HEADER_SIZE
- OCTNIC_GSO_MAX_SIZE
- OCTNIC_LROIPV4
- OCTNIC_LROIPV6
- OCTNIC_MAX_SG
- OCTNIC_NCMD_AUTONEG_ON
- OCTNIC_NCMD_PHY_ON
- OCTRL
- OCTRL_MASK
- OCTSTR
- OCT_32B_INSTR_SIZE
- OCT_64B_INSTR_SIZE
- OCT_BOARD_NAME
- OCT_DEV_BEGIN_STATE
- OCT_DEV_CONSOLE_INIT_DONE
- OCT_DEV_CORE_OK
- OCT_DEV_DISPATCH_INIT_DONE
- OCT_DEV_DROQ_INIT_DONE
- OCT_DEV_HOST_OK
- OCT_DEV_INSTR_QUEUE_INIT_DONE
- OCT_DEV_INTR_DMA0_FORCE
- OCT_DEV_INTR_DMA1_FORCE
- OCT_DEV_INTR_PKT_DATA
- OCT_DEV_INTR_SET_DONE
- OCT_DEV_IN_RESET
- OCT_DEV_IO_QUEUES_DONE
- OCT_DEV_MBOX_SETUP_DONE
- OCT_DEV_MSIX_ALLOC_VECTOR_DONE
- OCT_DEV_PCI_ENABLE_DONE
- OCT_DEV_PCI_MAP_DONE
- OCT_DEV_RESP_LIST_INIT_DONE
- OCT_DEV_RUNNING
- OCT_DEV_SC_BUFF_POOL_INIT_DONE
- OCT_DEV_STATES
- OCT_DEV_STATE_INVALID
- OCT_DK201_PID
- OCT_DROQ_DESC_SIZE
- OCT_DROQ_INFO_SIZE
- OCT_DROQ_RECVBUF_SIZE
- OCT_DROQ_SIZE
- OCT_DRV_OFFLINE
- OCT_DRV_ONLINE
- OCT_ETHTOOL_REGDUMP_LEN
- OCT_ETHTOOL_REGDUMP_LEN_23XX
- OCT_ETHTOOL_REGDUMP_LEN_23XX_VF
- OCT_ETHTOOL_REGSVER
- OCT_FW_VER
- OCT_IQ_STATS_SIZE
- OCT_LINK_INFO_SIZE
- OCT_LINK_STATS_SIZE
- OCT_MDIO45_RESP_SIZE
- OCT_MDIO_BITFIELD_FIELD
- OCT_MEM_REGIONS
- OCT_PRIV_FLAG_DEFAULT
- OCT_PRIV_FLAG_TX_BYTES
- OCT_RECV_INFO_SIZE
- OCT_RECV_PKT_SIZE
- OCT_REG_CR_OFF
- OCT_RH_SIZE
- OCT_SERIAL_LEN
- OCT_SG_ENTRY_SIZE
- OCT_TAG_TYPE_STRING
- OCT_TIMESTAMP_RESP_SIZE
- OCT_US101_PID
- OCT_VID
- OCV_MODE_ACTIVE
- OCV_MODE_SLEEP
- OCW2_EOI
- OCW2_SEOI
- OCW3_IIR
- OCW3_ISR
- OCW3_POLL
- OCXLFLASH_FS_MAGIC
- OCXL_AFU_EVENT_XSL_FAULT_ERROR
- OCXL_AFU_NAME_SZ
- OCXL_BIG_ENDIAN
- OCXL_CFG_TIMEOUT
- OCXL_DVSEC_ACTAG_MASK
- OCXL_DVSEC_AFU_CTRL_ACTAG_BASE
- OCXL_DVSEC_AFU_CTRL_ACTAG_EN
- OCXL_DVSEC_AFU_CTRL_ACTAG_SUP
- OCXL_DVSEC_AFU_CTRL_AFU_IDX
- OCXL_DVSEC_AFU_CTRL_ENABLE
- OCXL_DVSEC_AFU_CTRL_ID
- OCXL_DVSEC_AFU_CTRL_PASID_BASE
- OCXL_DVSEC_AFU_CTRL_PASID_EN
- OCXL_DVSEC_AFU_CTRL_PASID_SUP
- OCXL_DVSEC_AFU_CTRL_TERM_PASID
- OCXL_DVSEC_AFU_IDX_MASK
- OCXL_DVSEC_AFU_INFO_AFU_IDX
- OCXL_DVSEC_AFU_INFO_DATA
- OCXL_DVSEC_AFU_INFO_ID
- OCXL_DVSEC_AFU_INFO_OFF
- OCXL_DVSEC_FUNC_ID
- OCXL_DVSEC_FUNC_OFF_ACTAG
- OCXL_DVSEC_FUNC_OFF_INDEX
- OCXL_DVSEC_ID_OFFSET
- OCXL_DVSEC_PASID_LOG_MASK
- OCXL_DVSEC_PASID_MASK
- OCXL_DVSEC_TEMPL_AFU_VERSION
- OCXL_DVSEC_TEMPL_ALL_MEM_SZ
- OCXL_DVSEC_TEMPL_LPC_MEM_START
- OCXL_DVSEC_TEMPL_LPC_MEM_SZ
- OCXL_DVSEC_TEMPL_MMIO_GLOBAL
- OCXL_DVSEC_TEMPL_MMIO_GLOBAL_SZ
- OCXL_DVSEC_TEMPL_MMIO_PP
- OCXL_DVSEC_TEMPL_MMIO_PP_SZ
- OCXL_DVSEC_TEMPL_NAME
- OCXL_DVSEC_TEMPL_VERSION
- OCXL_DVSEC_TEMPL_WWID
- OCXL_DVSEC_TL_BACKOFF_TIMERS
- OCXL_DVSEC_TL_ID
- OCXL_DVSEC_TL_RECV_CAP
- OCXL_DVSEC_TL_RECV_RATE
- OCXL_DVSEC_TL_SEND_CAP
- OCXL_DVSEC_TL_SEND_RATE
- OCXL_DVSEC_VENDOR_CFG_VERS
- OCXL_DVSEC_VENDOR_DLX_VERS
- OCXL_DVSEC_VENDOR_ID
- OCXL_DVSEC_VENDOR_OFFSET
- OCXL_DVSEC_VENDOR_TLX_VERS
- OCXL_EXT_CAP_ID_DVSEC
- OCXL_HOST_ENDIAN
- OCXL_IOCTL_ATTACH
- OCXL_IOCTL_ENABLE_P9_WAIT
- OCXL_IOCTL_FEATURES_FLAGS0_P9_WAIT
- OCXL_IOCTL_GET_FEATURES
- OCXL_IOCTL_GET_METADATA
- OCXL_IOCTL_IRQ_ALLOC
- OCXL_IOCTL_IRQ_FREE
- OCXL_IOCTL_IRQ_SET_FD
- OCXL_KERNEL_EVENT_FLAG_LAST
- OCXL_LITTLE_ENDIAN
- OCXL_MAGIC
- OCXL_MAX_AFU_PER_FUNCTION
- OCXL_MAX_IRQS
- OCXL_NUM_MINORS
- OCXL_TEMPL_LEN_1_0
- OCXL_TEMPL_LEN_1_1
- OCXL_TEMPL_NAME_LEN
- OCX_COM_COPR_BADID
- OCX_COM_INT
- OCX_COM_INT_CE
- OCX_COM_INT_ENA_ALL
- OCX_COM_INT_ENA_W1C
- OCX_COM_INT_ENA_W1S
- OCX_COM_INT_W1S
- OCX_COM_IO_BADID
- OCX_COM_LANE_INT_CE
- OCX_COM_LANE_INT_UE
- OCX_COM_LINKX_INT
- OCX_COM_LINKX_INT_ENA_ALL
- OCX_COM_LINKX_INT_ENA_W1C
- OCX_COM_LINKX_INT_ENA_W1S
- OCX_COM_LINKX_INT_W1S
- OCX_COM_LINK_ALIGN_DONE
- OCX_COM_LINK_ALIGN_FAIL
- OCX_COM_LINK_BAD_WORD
- OCX_COM_LINK_BLK_ERR
- OCX_COM_LINK_INT_CE
- OCX_COM_LINK_INT_UE
- OCX_COM_LINK_LNK_DATA
- OCX_COM_LINK_REINIT
- OCX_COM_LINK_REPLAY_DBE
- OCX_COM_LINK_REPLAY_SBE
- OCX_COM_LINK_RXFIFO_DBE
- OCX_COM_LINK_RXFIFO_SBE
- OCX_COM_LINK_STOP
- OCX_COM_LINK_TXFIFO_DBE
- OCX_COM_LINK_TXFIFO_SBE
- OCX_COM_LINK_UP
- OCX_COM_MEM_BADID
- OCX_COM_RX_LANE
- OCX_COM_WIN_REQ_BADID
- OCX_COM_WIN_REQ_TOUT
- OCX_DEBUGFS_ATTR
- OCX_INTS
- OCX_LANE_BAD_64B67B
- OCX_LANE_BDRY_SYNC_LOSS
- OCX_LANE_CRC32_ERR
- OCX_LANE_DSKEW_FIFO_OVFL
- OCX_LANE_SCRM_SYNC_LOSS
- OCX_LANE_SERDES_LOCK_LOSS
- OCX_LANE_UKWN_CNTL_WORD
- OCX_LINK_INTS
- OCX_LNE_BAD_CNT
- OCX_LNE_CFG
- OCX_LNE_CFG_RX_BDRY_LOCK_DIS
- OCX_LNE_CFG_RX_STAT_ENA
- OCX_LNE_CFG_RX_STAT_RDCLR
- OCX_LNE_CFG_RX_STAT_WRAP_DIS
- OCX_LNE_INT
- OCX_LNE_INT_EN
- OCX_LNE_INT_ENA_ALL
- OCX_LNE_STAT
- OCX_MESSAGE_SIZE
- OCX_OTHER_SIZE
- OCX_RLKX_ECC_CTL
- OCX_RX_LANES
- OCX_RX_LANE_STATS
- OCX_TLKX_ECC_CTL
- OC_BLOCK
- OC_BUF
- OC_DEVICE_ID1
- OC_DEVICE_ID2
- OC_DEVICE_ID3
- OC_DEVICE_ID4
- OC_DEVICE_ID5
- OC_DEVICE_ID6
- OC_DISCONNECT
- OC_INT
- OC_INTR_DISABLE
- OC_INTR_ENABLE
- OC_INTR_OC1_MASK
- OC_INTR_OC2_MASK
- OC_INTR_OC3_MASK
- OC_INTR_OC4_MASK
- OC_INTR_OC5_MASK
- OC_INTR_STATUS
- OC_INT_EN
- OC_MAILBOX_FC_CONTROL_CMD
- OC_MAILBOX_RETRY_COUNT
- OC_MODE_GLOBAL
- OC_MODE_PERPORT
- OC_NAME
- OC_NAME_BE
- OC_NAME_LANCER
- OC_NAME_SH
- OC_NAME_UNKNOWN
- OC_PDCTL
- OC_POWER_DOWN
- OC_PULL_AHEAD
- OC_SKH_DEVICE_PF
- OC_SKH_DEVICE_VF
- OC_SKH_ID1
- OC_STATS_CTL
- OC_STATS_CTL_CLR_ALL
- OC_STATS_CTL_EN_ALL
- OC_SUBSYS_DEVICE_ID1
- OC_SUBSYS_DEVICE_ID2
- OC_SUBSYS_DEVICE_ID3
- OC_SUBSYS_DEVICE_ID4
- OC_THROTTLE_MODE_BRIEF
- OC_THROTTLE_MODE_DISABLED
- OD
- OD1_MOUT_EN_RDMA1
- OD8_ACOUSTIC_LIMIT_SCLK
- OD8_FAN_SPEED_MIN
- OD8_FAN_ZERO_RPM_CONTROL
- OD8_FEATURE_ID
- OD8_GFXCLK_CURVE
- OD8_GFXCLK_LIMITS
- OD8_HOTCURVE_TEMPERATURE
- OD8_MEMORY_TIMING_TUNE
- OD8_POWER_LIMIT
- OD8_SETTING_AC_TIMING
- OD8_SETTING_COUNT
- OD8_SETTING_FAN_ACOUSTIC_LIMIT
- OD8_SETTING_FAN_MIN_SPEED
- OD8_SETTING_FAN_TARGET_TEMP
- OD8_SETTING_FAN_ZERO_RPM_CONTROL
- OD8_SETTING_GFXCLK_FMAX
- OD8_SETTING_GFXCLK_FMIN
- OD8_SETTING_GFXCLK_FREQ1
- OD8_SETTING_GFXCLK_FREQ2
- OD8_SETTING_GFXCLK_FREQ3
- OD8_SETTING_GFXCLK_VOLTAGE1
- OD8_SETTING_GFXCLK_VOLTAGE2
- OD8_SETTING_GFXCLK_VOLTAGE3
- OD8_SETTING_ID
- OD8_SETTING_OPERATING_TEMP_MAX
- OD8_SETTING_POWER_PERCENTAGE
- OD8_SETTING_UCLK_FMAX
- OD8_TEMPERATURE_FAN
- OD8_TEMPERATURE_SYSTEM
- OD8_UCLK_MAX
- ODBL
- ODCR_CLEAR_ALL
- ODCU_REG
- ODDF_MARK
- ODD_COUNTERS
- ODD_CSR
- ODD_DMA_START
- ODD_DMA_STRIDE
- ODD_FLD_MASK
- ODD_MECH_TYPE_DRAWER
- ODD_MECH_TYPE_SLOT
- ODD_MECH_TYPE_UNSUPPORTED
- ODD_PIXEL_FMT
- ODD_SPACING
- ODEBUG_BATCH_SIZE
- ODEBUG_CHUNK_MASK
- ODEBUG_CHUNK_SHIFT
- ODEBUG_CHUNK_SIZE
- ODEBUG_FREE_WORK_DELAY
- ODEBUG_FREE_WORK_MAX
- ODEBUG_HASH_BITS
- ODEBUG_HASH_SIZE
- ODEBUG_POOL_MIN_LEVEL
- ODEBUG_POOL_PERCPU_SIZE
- ODEBUG_POOL_SIZE
- ODEBUG_STATE_ACTIVE
- ODEBUG_STATE_DESTROYED
- ODEBUG_STATE_INACTIVE
- ODEBUG_STATE_INIT
- ODEBUG_STATE_MAX
- ODEBUG_STATE_NONE
- ODEBUG_STATE_NOTAVAILABLE
- ODEN_CMD
- ODEN_DAT
- ODFBPWR
- ODFBPWR_MODE
- ODFBPWR_MODE_ACT
- ODFBPWR_MODE_ACT_LP
- ODFBPWR_MODE_SHUTD
- ODFBPWR_MODE_SLEEP
- ODFBPWR_SLOW
- ODFBSTAT
- ODFBSTAT_ACT
- ODFBSTAT_SDN
- ODFBSTAT_SLP
- ODF_BANK
- ODF_DIV_1
- ODF_DIV_2
- ODF_DIV_4
- ODF_DIV_8
- ODF_MAX
- ODF_MIN
- ODIE_ADDR_IO
- ODIE_DATA_IO
- ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK
- ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT
- ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK
- ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT
- ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK
- ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL_MASK
- ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SRC_SEL__SHIFT
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK
- ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK
- ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT
- ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK
- ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT
- ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK
- ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT
- ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK
- ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT
- ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK
- ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT
- ODMR_CLEAR_ALL
- ODMR_MASK_ALL
- ODM_1T1R
- ODM_1T2R
- ODM_1TPATHDIV
- ODM_2T2R
- ODM_2T3R
- ODM_2T4R
- ODM_2TPATHDIV
- ODM_3T3R
- ODM_3T4R
- ODM_4T4R
- ODM_ABILITY_E
- ODM_ABOVE
- ODM_AD_DA_LSB_MASK
- ODM_AD_HOC
- ODM_AFE_SETTING
- ODM_ANALOG_REGISTER
- ODM_AP_MODE
- ODM_ASSOCIATE_ENTRY_NUM
- ODM_Ability_E
- ODM_BANDMAX
- ODM_BAND_2_4G
- ODM_BAND_5G
- ODM_BAND_ON_BOTH
- ODM_BAND_TYPE_E
- ODM_BB_ADAPTIVITY
- ODM_BB_ANT_DIV
- ODM_BB_CCK_PD
- ODM_BB_CFO_TRACKING
- ODM_BB_Config_Type
- ODM_BB_DIG
- ODM_BB_DYNAMIC_TXPWR
- ODM_BB_FA_CNT
- ODM_BB_PATH_DIV
- ODM_BB_PSD
- ODM_BB_PWRSV
- ODM_BB_PWR_SAVE
- ODM_BB_PWR_TRA
- ODM_BB_PWR_TRAIN
- ODM_BB_RATE_ADAPTIVE
- ODM_BB_RA_MASK
- ODM_BB_RESET
- ODM_BB_RSSI_MONITOR
- ODM_BB_RXHP
- ODM_BELOW
- ODM_BIT
- ODM_BIT_BB_ATC_11N
- ODM_BIT_BB_RX_PATH_11AC
- ODM_BIT_BB_RX_PATH_11N
- ODM_BIT_CCK_RPT_FORMAT_11AC
- ODM_BIT_CCK_RPT_FORMAT_11N
- ODM_BIT_IGI_11AC
- ODM_BIT_IGI_11N
- ODM_BOARD_BT
- ODM_BOARD_COMBO
- ODM_BOARD_DEFAULT
- ODM_BOARD_EXT_LNA
- ODM_BOARD_EXT_LNA_5G
- ODM_BOARD_EXT_PA
- ODM_BOARD_EXT_PA_5G
- ODM_BOARD_EXT_TRSW
- ODM_BOARD_HIGHPWR
- ODM_BOARD_MINICARD
- ODM_BOARD_NORMAL
- ODM_BOARD_SLIM
- ODM_BOARD_TYPE_E
- ODM_BT_BUSY
- ODM_BT_COEXIST_E
- ODM_BT_NONE
- ODM_BT_OFF
- ODM_BT_ON
- ODM_BW10M
- ODM_BW160M
- ODM_BW20M
- ODM_BW40M
- ODM_BW80M
- ODM_BW_E
- ODM_CCA_1R_A
- ODM_CCA_1R_B
- ODM_CCA_2R
- ODM_CCA_PATH_E
- ODM_CCK_ANT_SELECT
- ODM_CCK_CCA_TH
- ODM_CCK_CNT_RESET
- ODM_CCK_FA_CNT_LSB
- ODM_CCK_FA_CNT_MSB
- ODM_CCK_MATCH_FILTER
- ODM_CCK_NEW_FUNCTION
- ODM_CCK_PD_THRESH
- ODM_CCK_RAKE_MAC
- ODM_CCK_RF_REG1
- ODM_CCK_TX_DIVERSITY
- ODM_CE
- ODM_CHANNEL
- ODM_CLIENT_MODE
- ODM_CMNINFO_5G_EXT_LNA
- ODM_CMNINFO_5G_EXT_PA
- ODM_CMNINFO_ABILITY
- ODM_CMNINFO_ALNA
- ODM_CMNINFO_ANT_TEST
- ODM_CMNINFO_APA
- ODM_CMNINFO_BAND
- ODM_CMNINFO_BINHCT_TEST
- ODM_CMNINFO_BOARD_TYPE
- ODM_CMNINFO_BT_BUSY
- ODM_CMNINFO_BT_DIG
- ODM_CMNINFO_BT_DISABLED
- ODM_CMNINFO_BT_DISABLE_EDCA
- ODM_CMNINFO_BT_ENABLED
- ODM_CMNINFO_BT_HS_CONNECT_PROCESS
- ODM_CMNINFO_BT_HS_RSSI
- ODM_CMNINFO_BT_LIMITED_DIG
- ODM_CMNINFO_BT_OPERATION
- ODM_CMNINFO_BUDDY_ADAPTOR
- ODM_CMNINFO_BW
- ODM_CMNINFO_BWIFI_TEST
- ODM_CMNINFO_CHNL
- ODM_CMNINFO_CUT_VER
- ODM_CMNINFO_DBG_COMP
- ODM_CMNINFO_DBG_LEVEL
- ODM_CMNINFO_DMSP_GET_VALUE
- ODM_CMNINFO_DMSP_IS_MASTER
- ODM_CMNINFO_DRV_STOP
- ODM_CMNINFO_E
- ODM_CMNINFO_EXT_LNA
- ODM_CMNINFO_EXT_PA
- ODM_CMNINFO_EXT_TRSW
- ODM_CMNINFO_FAB_VER
- ODM_CMNINFO_FORCED_IGI_LB
- ODM_CMNINFO_FORCED_RATE
- ODM_CMNINFO_GLNA
- ODM_CMNINFO_GPA
- ODM_CMNINFO_IC_TYPE
- ODM_CMNINFO_INIT_ON
- ODM_CMNINFO_INTERFACE
- ODM_CMNINFO_IS1ANTENNA
- ODM_CMNINFO_LINK
- ODM_CMNINFO_LINK_IN_PROGRESS
- ODM_CMNINFO_MAC_PHY_MODE
- ODM_CMNINFO_MAC_STATUS
- ODM_CMNINFO_MAX
- ODM_CMNINFO_MP_MODE
- ODM_CMNINFO_MP_TEST_CHIP
- ODM_CMNINFO_NET_CLOSED
- ODM_CMNINFO_ONE_PATH_CCA
- ODM_CMNINFO_PACKAGE_TYPE
- ODM_CMNINFO_PATCH_ID
- ODM_CMNINFO_PHY_STATUS
- ODM_CMNINFO_PLATFORM
- ODM_CMNINFO_PNP_IN
- ODM_CMNINFO_POWER_SAVING
- ODM_CMNINFO_RA_THRESHOLD_HIGH
- ODM_CMNINFO_RA_THRESHOLD_LOW
- ODM_CMNINFO_RFDEFAULTPATH
- ODM_CMNINFO_RFE_TYPE
- ODM_CMNINFO_RF_ANTENNA_TYPE
- ODM_CMNINFO_RF_TYPE
- ODM_CMNINFO_RSSI_MIN
- ODM_CMNINFO_RX_UNI
- ODM_CMNINFO_SCAN
- ODM_CMNINFO_SEC_CHNL_OFFSET
- ODM_CMNINFO_SEC_MODE
- ODM_CMNINFO_SMART_CONCURRENT
- ODM_CMNINFO_STATION_STATE
- ODM_CMNINFO_STA_STATUS
- ODM_CMNINFO_TX_UNI
- ODM_CMNINFO_WIFI_DIRECT
- ODM_CMNINFO_WIFI_DISPLAY
- ODM_CMNINFO_WM_MODE
- ODM_COMP_ANT_DIV
- ODM_COMP_CALIBRATION
- ODM_COMP_CCK_PD
- ODM_COMP_CFO_TRACKING
- ODM_COMP_COMMON
- ODM_COMP_DIG
- ODM_COMP_DYNAMIC_PRICCA
- ODM_COMP_DYNAMIC_TXPWR
- ODM_COMP_EARLY_MODE
- ODM_COMP_EDCA_TURBO
- ODM_COMP_FA_CNT
- ODM_COMP_INIT
- ODM_COMP_MP
- ODM_COMP_PATH_DIV
- ODM_COMP_PSD
- ODM_COMP_PWR_SAVE
- ODM_COMP_PWR_TRA
- ODM_COMP_PWR_TRAIN
- ODM_COMP_RATE_ADAPTIVE
- ODM_COMP_RA_MASK
- ODM_COMP_RSSI_MONITOR
- ODM_COMP_RXHP
- ODM_COMP_RX_GAIN_TRACK
- ODM_COMP_TX_PWR_TRACK
- ODM_CUT_A
- ODM_CUT_B
- ODM_CUT_C
- ODM_CUT_D
- ODM_CUT_E
- ODM_CUT_F
- ODM_CUT_I
- ODM_CUT_J
- ODM_CUT_K
- ODM_CUT_TEST
- ODM_CUT_VERSION_E
- ODM_CfoTracking
- ODM_CfoTrackingInit
- ODM_CfoTrackingReset
- ODM_CheckPowerStatus
- ODM_ClearTxPowerTrackingState
- ODM_CmnInfoHook
- ODM_CmnInfoInit
- ODM_CmnInfoPtrArrayHook
- ODM_CmnInfoUpdate
- ODM_ConfigBBWithHeaderFile
- ODM_ConfigRFWithHeaderFile
- ODM_ConfigRFWithTxPwrTrackHeaderFile
- ODM_DBG_LOUD
- ODM_DBG_OFF
- ODM_DBG_SERIOUS
- ODM_DBG_TRACE
- ODM_DBG_WARNING
- ODM_DIG
- ODM_DMDP
- ODM_DMInit
- ODM_DMSP
- ODM_DMWatchdog
- ODM_DONT_CARE
- ODM_DPDT
- ODM_DUMMY
- ODM_EDCA_BE_PARAM
- ODM_EDCA_BK_PARAM
- ODM_EDCA_VI_PARAM
- ODM_EDCA_VO_PARAM
- ODM_ENABLE_3_WIRE
- ODM_ENDIAN_BIG
- ODM_ENDIAN_LITTLE
- ODM_ENDIAN_TYPE
- ODM_EdcaTurboInit
- ODM_FAB_E
- ODM_FA_STATISTICS
- ODM_FPGA_PHY0_PAGE8
- ODM_FW_Config_Type
- ODM_GAIN_SETTING
- ODM_GetRightChnlPlaceforIQK
- ODM_Get_Rate_Bitmap
- ODM_H2C_CMD
- ODM_H2C_PSD_RESULT
- ODM_H2C_PathDiv
- ODM_H2C_RSSI_REPORT
- ODM_H2C_WIFI_CALIBRATION
- ODM_HIGH_POWER
- ODM_HW_ANTDIV
- ODM_IC_TYPE_E
- ODM_INTERFACE_E
- ODM_ITRF_ALL
- ODM_ITRF_SDIO
- ODM_InbandNoise_Monitor
- ODM_InitDebugSetting
- ODM_LINK
- ODM_MAC_EARLY_MODE
- ODM_MAC_EDCA_TURBO
- ODM_MAC_PHY_MODE_E
- ODM_MAX_CHANNEL_NUM
- ODM_MAX_H2CCMD
- ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK
- ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT
- ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK
- ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT
- ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK
- ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT
- ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK
- ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT
- ODM_NOISE_MONITOR
- ODM_NO_LINK
- ODM_OFDM_FA_CNT1
- ODM_OFDM_FA_CNT2
- ODM_OFDM_FA_CNT3
- ODM_OFDM_FA_CNT4
- ODM_OFDM_PHY0_PAGE_C
- ODM_OFDM_PHY0_PAGE_D
- ODM_OFDM_RX_ANT
- ODM_OPERATION_MODE_E
- ODM_PACKAGE_DEFAULT
- ODM_PACKAGE_QFN68
- ODM_PACKAGE_TFBGA79
- ODM_PACKAGE_TFBGA90
- ODM_PAUSE_CCKPD
- ODM_PAUSE_DIG
- ODM_POWERSAVE
- ODM_PRINT_ADDR
- ODM_PSD2AFH
- ODM_PSDREG
- ODM_PSD_REPORT
- ODM_PSD_SETTING
- ODM_Package_TYPE_E
- ODM_ParsingCFO
- ODM_Pause_CCKPD_TYPE
- ODM_Pause_DIG_TYPE
- ODM_PhyStatusQuery
- ODM_PhyStatusQuery_92CSeries
- ODM_RAInfo_Init
- ODM_RAInfo_Init_all
- ODM_RAMASK
- ODM_RAStateCheck
- ODM_RATE_ADAPTIVE
- ODM_RA_GetDecisionRate_8188E
- ODM_RA_GetHwPwrStatus_8188E
- ODM_RA_GetShortGI_8188E
- ODM_RA_INFO_T
- ODM_RA_SetRSSI_8188E
- ODM_RA_Set_TxRPT_Time
- ODM_RA_TxRPT2Handle_8188E
- ODM_RA_UpdateRateInfo_8188E
- ODM_REG
- ODM_REG_ANTDIV_PARA1_11N
- ODM_REG_ANTDIV_PARA2_11N
- ODM_REG_ANTDIV_PARA3_11N
- ODM_REG_ANTSEL_CTRL_11N
- ODM_REG_ANTSEL_PATH_11N
- ODM_REG_ANTSEL_PIN_11N
- ODM_REG_ANT_MAPPING1_11N
- ODM_REG_ANT_MAPPING2_11N
- ODM_REG_ANT_TRAIN_PARA1_11N
- ODM_REG_ANT_TRAIN_PARA2_11N
- ODM_REG_BB_3WIRE_11N
- ODM_REG_BB_ATC_11N
- ODM_REG_BB_CTRL_11N
- ODM_REG_BB_PWR_SAV1_11N
- ODM_REG_BB_PWR_SAV2_11N
- ODM_REG_BB_PWR_SAV3_11N
- ODM_REG_BB_PWR_SAV4_11N
- ODM_REG_BB_PWR_SAV5_11N
- ODM_REG_BB_RST_11N
- ODM_REG_BB_RX_PATH_11AC
- ODM_REG_BB_RX_PATH_11N
- ODM_REG_BLUETOOTH_11N
- ODM_REG_CCK_ANTDIV_PARA1_11N
- ODM_REG_CCK_ANTDIV_PARA2_11N
- ODM_REG_CCK_ANTDIV_PARA3_11N
- ODM_REG_CCK_ANTDIV_PARA4_11N
- ODM_REG_CCK_CCA_11AC
- ODM_REG_CCK_CCA_11N
- ODM_REG_CCK_CCA_CNT_11N
- ODM_REG_CCK_FA_11AC
- ODM_REG_CCK_FA_LSB_11N
- ODM_REG_CCK_FA_MSB_11N
- ODM_REG_CCK_FA_RST_11AC
- ODM_REG_CCK_FA_RST_11N
- ODM_REG_CCK_FILTER_PARA1_11N
- ODM_REG_CCK_FILTER_PARA2_11N
- ODM_REG_CCK_FILTER_PARA3_11N
- ODM_REG_CCK_FILTER_PARA4_11N
- ODM_REG_CCK_FILTER_PARA5_11N
- ODM_REG_CCK_FILTER_PARA6_11N
- ODM_REG_CCK_FILTER_PARA7_11N
- ODM_REG_CCK_FILTER_PARA8_11N
- ODM_REG_CCK_RPT_FORMAT_11AC
- ODM_REG_CCK_RPT_FORMAT_11N
- ODM_REG_CHNBW_11N
- ODM_REG_CONFIG_ANTA_11N
- ODM_REG_DBG_RPT_11N
- ODM_REG_EARLY_MODE_11N
- ODM_REG_EDCA_BE_11N
- ODM_REG_EDCA_BK_11N
- ODM_REG_EDCA_VI_11N
- ODM_REG_EDCA_VO_11N
- ODM_REG_FPGA0_IQK_11N
- ODM_REG_IGI_A_11AC
- ODM_REG_IGI_A_11N
- ODM_REG_IGI_B_11AC
- ODM_REG_IGI_B_11N
- ODM_REG_IGI_C_11N
- ODM_REG_IGI_D_11N
- ODM_REG_IQK_AGC_PTS_11N
- ODM_REG_IQK_AGC_RSP_11N
- ODM_REG_L1SBD_PD_CH_11N
- ODM_REG_LNA_SWITCH_11N
- ODM_REG_NHM_CNT_11N
- ODM_REG_NHM_TH3_TO_TH0_11N
- ODM_REG_NHM_TH7_TO_TH4_11N
- ODM_REG_NHM_TH9_TH10_11N
- ODM_REG_NHM_TIMER_11N
- ODM_REG_OFDM_BBON_11N
- ODM_REG_OFDM_FA_11AC
- ODM_REG_OFDM_FA_HOLDC_11N
- ODM_REG_OFDM_FA_RSTC_11N
- ODM_REG_OFDM_FA_RSTD_11N
- ODM_REG_OFDM_FA_RST_11AC
- ODM_REG_OFDM_FA_TYPE1_11N
- ODM_REG_OFDM_FA_TYPE2_11N
- ODM_REG_OFDM_FA_TYPE3_11N
- ODM_REG_OFDM_FA_TYPE4_11N
- ODM_REG_OFDM_RFON_11N
- ODM_REG_PATH_SWITCH_11N
- ODM_REG_PIN_CTRL_11N
- ODM_REG_PMPD_ANAEN_11N
- ODM_REG_PSD_CTRL_11N
- ODM_REG_PSD_DATA_11N
- ODM_REG_RESP_TX_11N
- ODM_REG_RF_0B_11N
- ODM_REG_RF_25_11N
- ODM_REG_RF_26_11N
- ODM_REG_RF_27_11N
- ODM_REG_RF_2B_11N
- ODM_REG_RF_2C_11N
- ODM_REG_RF_MODE_11N
- ODM_REG_RF_PIN_11N
- ODM_REG_RPT_11N
- ODM_REG_RSSI_BT_11N
- ODM_REG_RSSI_CTRL_11N
- ODM_REG_RSSI_MONITOR_11N
- ODM_REG_RX2RX_11N
- ODM_REG_RXIQI_MATRIX_11N
- ODM_REG_RXIQK_11N
- ODM_REG_RXIQK_MATRIX_LSB_11N
- ODM_REG_RXIQK_PI_A_11N
- ODM_REG_RXIQK_TONE_A_11N
- ODM_REG_RXRF_A3_11N
- ODM_REG_RX_ANT_CTRL_11N
- ODM_REG_RX_CCK_11N
- ODM_REG_RX_DEFAULT_A_11N
- ODM_REG_RX_DEFUALT_A_11N
- ODM_REG_RX_DEFUALT_B_11N
- ODM_REG_RX_OFDM_11N
- ODM_REG_RX_OFF_11N
- ODM_REG_RX_WAIT_CCA_11N
- ODM_REG_RX_WAIT_RIFS_11N
- ODM_REG_SC_CNT_11N
- ODM_REG_SLEEP_11N
- ODM_REG_STANDBY_11N
- ODM_REG_TRMUX_11N
- ODM_REG_TX2RX_11N
- ODM_REG_TX2TX_11N
- ODM_REG_TXAGC_A_1_MCS32_11N
- ODM_REG_TXAGC_A_24_54_11N
- ODM_REG_TXAGC_A_6_18_11N
- ODM_REG_TXAGC_A_MCS0_3_11N
- ODM_REG_TXAGC_A_MCS12_15_11N
- ODM_REG_TXAGC_A_MCS4_7_11N
- ODM_REG_TXAGC_A_MCS8_11_11N
- ODM_REG_TXIQK_11N
- ODM_REG_TXIQK_MATRIXA_11N
- ODM_REG_TXIQK_MATRIXA_LSB2_11N
- ODM_REG_TXIQK_MATRIXB_11N
- ODM_REG_TXIQK_MATRIXB_LSB2_11N
- ODM_REG_TXIQK_MATRIX_LSB1_11N
- ODM_REG_TXIQK_PI_A_11N
- ODM_REG_TXIQK_TONE_A_11N
- ODM_REG_TXPAUSE_11N
- ODM_REG_TX_ANT_CTRL_11N
- ODM_REG_TX_CCK_BBON_11N
- ODM_REG_TX_CCK_RFON_11N
- ODM_REG_T_METER_11N
- ODM_REG_T_METER_88E_11N
- ODM_REG_T_METER_92D_11N
- ODM_RESUME_CCKPD
- ODM_RESUME_DIG
- ODM_RF_CALIBRATION
- ODM_RF_CAL_T
- ODM_RF_CONTENT
- ODM_RF_Calibration_Structure
- ODM_RF_Config_Type
- ODM_RF_INTERFACE_OUTPUT
- ODM_RF_PATH_A
- ODM_RF_PATH_AB
- ODM_RF_PATH_ABC
- ODM_RF_PATH_ABCD
- ODM_RF_PATH_AC
- ODM_RF_PATH_ACD
- ODM_RF_PATH_AD
- ODM_RF_PATH_B
- ODM_RF_PATH_BC
- ODM_RF_PATH_BCD
- ODM_RF_PATH_BD
- ODM_RF_PATH_C
- ODM_RF_PATH_CD
- ODM_RF_PATH_D
- ODM_RF_PATH_E
- ODM_RF_PATH_MAX
- ODM_RF_RADIO_PATH_E
- ODM_RF_RX_A
- ODM_RF_RX_B
- ODM_RF_RX_C
- ODM_RF_RX_D
- ODM_RF_RX_GAIN_TRACK
- ODM_RF_Saving
- ODM_RF_TX_A
- ODM_RF_TX_B
- ODM_RF_TX_C
- ODM_RF_TX_D
- ODM_RF_TX_PWR_TRACK
- ODM_RF_TYPE_E
- ODM_RSSI_MONITOR
- ODM_RTL8188E
- ODM_RTL8723B
- ODM_RT_ASSERT
- ODM_RT_TRACE
- ODM_RT_TRACE_F
- ODM_R_AGC_PAR
- ODM_R_ANT_SELECT
- ODM_R_A_AGC_CORE1
- ODM_R_A_AGC_CORE2
- ODM_R_A_RXIQI
- ODM_R_B_AGC_CORE1
- ODM_R_HTSTF_AGC_PAR
- ODM_ReadAndConfig_MP_8723B_AGC_TAB
- ODM_ReadAndConfig_MP_8723B_MAC_REG
- ODM_ReadAndConfig_MP_8723B_PHY_REG
- ODM_ReadAndConfig_MP_8723B_PHY_REG_PG
- ODM_ReadAndConfig_MP_8723B_RadioA
- ODM_ReadAndConfig_MP_8723B_TXPWR_LMT
- ODM_ReadAndConfig_MP_8723B_TxPowerTrack_SDIO
- ODM_SCAN
- ODM_SECURITY_E
- ODM_SEC_AESCCMP
- ODM_SEC_CHNL_OFFSET_E
- ODM_SEC_OPEN
- ODM_SEC_RESERVE
- ODM_SEC_SMS4
- ODM_SEC_TKIP
- ODM_SEC_WEP104
- ODM_SEC_WEP40
- ODM_SMSP
- ODM_STA_INFO_T
- ODM_SW_ANTDIV
- ODM_SetIQCbyRFpath
- ODM_TARGET_CHNL_NUM_2G_5G
- ODM_TSMC
- ODM_TXAGC_A_1_MCS32
- ODM_TXAGC_A_24_54
- ODM_TXAGC_A_6_18
- ODM_TXAGC_A_MCS0_MCS3
- ODM_TXAGC_A_MCS12_MCS15
- ODM_TXAGC_A_MCS4_MCS7
- ODM_TXAGC_A_MCS8_MCS11
- ODM_TXAGC_B_11_A_2_11
- ODM_TXAGC_B_24_54
- ODM_TXAGC_B_MCS0_MCS3
- ODM_TXAGC_B_MCS12_MCS15
- ODM_TXAGC_B_MCS32_5
- ODM_TXAGC_B_MCS4_MCS7
- ODM_TXAGC_B_MCS8_MCS11
- ODM_TXPAUSE
- ODM_TXPWRTRACK_MAX_IDX8723B
- ODM_TXPWRTRACK_MAX_IDX_88E
- ODM_TXPowerTrackingCallback_ThermalMeter
- ODM_TXPowerTrackingCheck
- ODM_TX_PWR_TRAINING_A
- ODM_TX_PWR_TRAINING_B
- ODM_TYPE_ALNA_E
- ODM_TYPE_APA_E
- ODM_TYPE_GLNA_E
- ODM_TYPE_GPA_E
- ODM_TxPwrTrackSetPwr_8723B
- ODM_UMC
- ODM_WEP_WPA_MIXED
- ODM_WIFI_DIRECT
- ODM_WIFI_DISPLAY
- ODM_WIRELESS_MODE_E
- ODM_WM_A
- ODM_WM_AC
- ODM_WM_AUTO
- ODM_WM_B
- ODM_WM_G
- ODM_WM_N24G
- ODM_WM_N5G
- ODM_WM_UNKNOW
- ODM_WM_UNKNOWN
- ODM_Write_CCK_CCA_Thres
- ODM_Write_DIG
- ODM__MEM_PG
- ODM__MEM_PG__0
- ODM_dbg_enter
- ODM_dbg_exit
- ODM_dbg_trace
- ODP_CAP_SET_MAX
- ODP_DMA_ADDR_MASK
- ODP_READ_ALLOWED_BIT
- ODP_WRITE_ALLOWED_BIT
- ODR100F
- ODR12_5F
- ODR200F
- ODR25F
- ODR400F
- ODR50F
- ODR800F
- ODSR_CLEAR
- OD_INFO
- OD_MCLK
- OD_MOUT_EN_RDMA0
- OD_NORMAL_SAMPLE
- OD_RANGE
- OD_RELAYMODE
- OD_REL_CMD
- OD_REL_DAT
- OD_SCLK
- OD_SUB_SAMPLE
- OD_VDDC_CURVE
- OE
- OEC
- OEH_HE_ADDR
- OEH_HS_ADDR
- OEH_VE_ADDR
- OEH_VS_ADDR
- OEM0
- OEM0_DATA_AVAIL
- OEM1
- OEM1_DATA_AVAIL
- OEM2_DATA_AVAIL
- OEMID
- OEMLCDDelayEnable
- OEMLCDEnable
- OEMLCDPIDTableAddr
- OEMLCDPOSEnable
- OEMLCDPanelIDSupport
- OEMLCDPtr_1Addr
- OEMLCDPtr_2Addr
- OEMLVDSPIDTableSize
- OEMTVDelayEnable
- OEMTVEnable
- OEMTVFilterEnable
- OEMTVFlickerEnable
- OEMTVPhaseEnable
- OEMTVPtrAddr
- OEMUtilIDCodeAddr
- OEM_ALPHA
- OEM_AST
- OEM_ATT
- OEM_CFG_CHANNEL_TYPE_MASK
- OEM_CFG_CHANNEL_TYPE_OFFSET
- OEM_CFG_CHANNEL_TYPE_STAGGED
- OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION
- OEM_CFG_FUNC_HOST_PRI_CTRL_MASK
- OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET
- OEM_CFG_FUNC_HOST_PRI_CTRL_OS
- OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC
- OEM_CFG_FUNC_TC_0
- OEM_CFG_FUNC_TC_1
- OEM_CFG_FUNC_TC_2
- OEM_CFG_FUNC_TC_3
- OEM_CFG_FUNC_TC_4
- OEM_CFG_FUNC_TC_5
- OEM_CFG_FUNC_TC_6
- OEM_CFG_FUNC_TC_7
- OEM_CFG_FUNC_TC_MASK
- OEM_CFG_FUNC_TC_OFFSET
- OEM_CFG_SCHED_TYPE_ETS
- OEM_CFG_SCHED_TYPE_MASK
- OEM_CFG_SCHED_TYPE_OFFSET
- OEM_CFG_SCHED_TYPE_VNIC_BW
- OEM_DATA_AVAIL
- OEM_DATA_REQ_SIZE
- OEM_DATA_RSP_SIZE
- OEM_DPT
- OEM_GRP_CMD_GET_SLOT_GA
- OEM_GRP_CMD_REQUEST_HOTSWAP_CTRL
- OEM_GRP_CMD_SET_POWER_STATE
- OEM_GRP_CMD_SET_RESET_STATE
- OEM_ID_FROM_USB_PRODUCT_ID
- OEM_ID_ICP
- OEM_ID_INTEL
- OEM_NAME
- OEM_NEC
- OEM_OLIVETTI
- OEM_SNI
- OEM_SUN
- OEM_USER_DATA
- OEN_OFF
- OEN_TRI_SEL_ALL_OFF_r0
- OEN_TRI_SEL_ALL_OFF_r1
- OEN_TRI_SEL_ALL_ON
- OEN_TRI_SEL_MASK
- OESPI_FRM_ERR
- OESPI_PAR_ERROR_F
- OESPI_PAR_ERROR_S
- OESPI_PAR_ERROR_V
- OETH_IRQ
- OETH_REGS_PADDR
- OETH_REGS_SIZE
- OETH_SRAMBUFF_PADDR
- OETH_SRAMBUFF_SIZE
- OEV1_HE_ADDR
- OEV1_HS_ADDR
- OEV1_VE_ADDR
- OEV1_VS_ADDR
- OEV2_HE_ADDR
- OEV2_HS_ADDR
- OEV2_VE_ADDR
- OEV2_VS_ADDR
- OEV3_HE_ADDR
- OEV3_HS_ADDR
- OEV3_VE_ADDR
- OEV3_VS_ADDR
- OE_FLUSH__FINAL
- OE_FLUSH__HALF
- OE_FLUSH__NONE
- OE_FLUSH__ROUND
- OE_FLUSH__TIME
- OE_FLUSH__TOP
- OF
- OFB_DATA_MAX
- OFC_UPDATE
- OFD
- OFDEL
- OFDHASHSAVE_F
- OFDHASHSAVE_S
- OFDHASHSAVE_V
- OFDLKPEN_F
- OFDLKPEN_S
- OFDLKPEN_V
- OFDM
- OFDM0_SYNC_PATH_NOTCH_FILTER
- OFDM0_X_AGC_CORE1_IGI_MASK
- OFDMAPEN_F
- OFDMAPEN_S
- OFDMAPEN_V
- OFDMCCA_TH
- OFDM_36M_INDEX
- OFDM_48M_INDEX
- OFDM_54M_INDEX
- OFDM_ACK_TOUT_VALUE
- OFDM_AGC_CTL
- OFDM_AGC_GAIN_1
- OFDM_AGC_TARGET
- OFDM_AGC_TARGET_DEFAULT
- OFDM_AGC_TARGET_IMPULSE
- OFDM_ALL_OFF
- OFDM_BDI_CTL
- OFDM_CAS_CTL
- OFDM_CHC_CTL_1
- OFDM_CHC_SNR
- OFDM_COR_CTL
- OFDM_COR_INSTAT
- OFDM_COR_INTEN
- OFDM_COR_MODEGUARD
- OFDM_COR_STAT
- OFDM_CP_COMM_EXEC_STOP
- OFDM_CP_COMM_EXEC__A
- OFDM_CRL_FREQ_1
- OFDM_ContinuousTx
- OFDM_EC_SB_PRIOR_HI
- OFDM_EC_SB_PRIOR_LO
- OFDM_EC_SB_PRIOR__A
- OFDM_EC_VD_ERR_BIT_CNT__A
- OFDM_EC_VD_IN_BIT_CNT__A
- OFDM_EQ_TOP_TD_REQ_SMB_CNT__A
- OFDM_EQ_TOP_TD_SQR_ERR_EXP__A
- OFDM_EQ_TOP_TD_SQR_ERR_I__A
- OFDM_EQ_TOP_TD_SQR_ERR_Q__A
- OFDM_EQ_TOP_TD_TPS_CODE_HP__A
- OFDM_EQ_TOP_TD_TPS_CODE_HP__M
- OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8
- OFDM_EQ_TOP_TD_TPS_CONST_64QAM
- OFDM_EQ_TOP_TD_TPS_CONST__A
- OFDM_EQ_TOP_TD_TPS_CONST__M
- OFDM_EQ_TOP_TD_TPS_PWR_OFS__A
- OFDM_ITB_CTL
- OFDM_ITB_FREQ_1
- OFDM_ITB_FREQ_2
- OFDM_LC_COMM_EXEC_STOP
- OFDM_LC_COMM_EXEC__A
- OFDM_LOCK_TIME
- OFDM_LSTF_CONTINUE_TX
- OFDM_LSTF_MASK
- OFDM_LSTF_PRIME_CH_HIGH
- OFDM_LSTF_PRIME_CH_LOW
- OFDM_LSTF_PRIME_CH_MASK
- OFDM_LSTF_SINGLE_CARRIER
- OFDM_LSTF_SINGLE_TONE
- OFDM_MPDU_FAIL_BIT
- OFDM_MPDU_OK_BIT
- OFDM_MSC_REV
- OFDM_PHY
- OFDM_PLCP_BITS
- OFDM_PLCP_BITS_HALF
- OFDM_PLCP_BITS_QUARTER
- OFDM_PPDU_BIT
- OFDM_PPM_CTL_1
- OFDM_PREAMBLE_TIME
- OFDM_PREAMBLE_TIME_HALF
- OFDM_PREAMBLE_TIME_QUARTER
- OFDM_PROT_CFG
- OFDM_PROT_CFG_PROTECT_CTRL
- OFDM_PROT_CFG_PROTECT_NAV_LONG
- OFDM_PROT_CFG_PROTECT_NAV_SHORT
- OFDM_PROT_CFG_PROTECT_RATE
- OFDM_PROT_CFG_RTS_TH_EN
- OFDM_PROT_CFG_TX_OP_ALLOW_CCK
- OFDM_PROT_CFG_TX_OP_ALLOW_GF20
- OFDM_PROT_CFG_TX_OP_ALLOW_GF40
- OFDM_PROT_CFG_TX_OP_ALLOW_MM20
- OFDM_PROT_CFG_TX_OP_ALLOW_MM40
- OFDM_PROT_CFG_TX_OP_ALLOW_OFDM
- OFDM_RATE
- OFDM_RATE_BIT
- OFDM_RF_PATH_RX_A
- OFDM_RF_PATH_RX_B
- OFDM_RF_PATH_RX_C
- OFDM_RF_PATH_RX_D
- OFDM_RF_PATH_RX_MASK
- OFDM_RF_PATH_TX_A
- OFDM_RF_PATH_TX_B
- OFDM_RF_PATH_TX_C
- OFDM_RF_PATH_TX_D
- OFDM_RF_PATH_TX_MASK
- OFDM_SCR_CTL
- OFDM_SC_COMM_EXEC_STOP
- OFDM_SC_COMM_EXEC__A
- OFDM_SC_COMM_STATE__A
- OFDM_SC_RA_RAM_BE_OPT_DELAY__A
- OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A
- OFDM_SC_RA_RAM_CMD_ADDR__A
- OFDM_SC_RA_RAM_CMD_GET_OP_PARAM
- OFDM_SC_RA_RAM_CMD_NULL
- OFDM_SC_RA_RAM_CMD_PROC_START
- OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM
- OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING
- OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM
- OFDM_SC_RA_RAM_CMD_SET_TIMER
- OFDM_SC_RA_RAM_CMD_USER_IO
- OFDM_SC_RA_RAM_CMD__A
- OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M
- OFDM_SC_RA_RAM_CONFIG__A
- OFDM_SC_RA_RAM_ECHO_THRES_2K__B
- OFDM_SC_RA_RAM_ECHO_THRES_2K__M
- OFDM_SC_RA_RAM_ECHO_THRES_8K__B
- OFDM_SC_RA_RAM_ECHO_THRES_8K__M
- OFDM_SC_RA_RAM_ECHO_THRES__A
- OFDM_SC_RA_RAM_FR_THRES_8K__A
- OFDM_SC_RA_RAM_LOCKTRACK_MIN
- OFDM_SC_RA_RAM_LOCK_DEMOD__M
- OFDM_SC_RA_RAM_LOCK_FEC__M
- OFDM_SC_RA_RAM_LOCK_MPEG__M
- OFDM_SC_RA_RAM_LOCK_NODVBT__M
- OFDM_SC_RA_RAM_LOCK__A
- OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A
- OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A
- OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A
- OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A
- OFDM_SC_RA_RAM_OP_AUTO_CONST__M
- OFDM_SC_RA_RAM_OP_AUTO_GUARD__M
- OFDM_SC_RA_RAM_OP_AUTO_HIER__M
- OFDM_SC_RA_RAM_OP_AUTO_MODE__M
- OFDM_SC_RA_RAM_OP_AUTO_RATE__M
- OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16
- OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64
- OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK
- OFDM_SC_RA_RAM_OP_PARAM_GUARD_16
- OFDM_SC_RA_RAM_OP_PARAM_GUARD_32
- OFDM_SC_RA_RAM_OP_PARAM_GUARD_4
- OFDM_SC_RA_RAM_OP_PARAM_GUARD_8
- OFDM_SC_RA_RAM_OP_PARAM_HIER_A1
- OFDM_SC_RA_RAM_OP_PARAM_HIER_A2
- OFDM_SC_RA_RAM_OP_PARAM_HIER_A4
- OFDM_SC_RA_RAM_OP_PARAM_HIER_NO
- OFDM_SC_RA_RAM_OP_PARAM_MODE_2K
- OFDM_SC_RA_RAM_OP_PARAM_MODE_8K
- OFDM_SC_RA_RAM_OP_PARAM_MODE__M
- OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI
- OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO
- OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2
- OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3
- OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4
- OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6
- OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8
- OFDM_SC_RA_RAM_OP_PARAM__A
- OFDM_SC_RA_RAM_PARAM0__A
- OFDM_SC_RA_RAM_PARAM1__A
- OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A
- OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M
- OFDM_SIFS_TIME
- OFDM_SIFS_TIME_HALF
- OFDM_SIFS_TIME_QUARTER
- OFDM_SNR_CARRIER_2
- OFDM_SYMBOL_TIME
- OFDM_SYMBOL_TIME_HALF
- OFDM_SYMBOL_TIME_QUARTER
- OFDM_SYR_CTL
- OFDM_SYR_OFFSET_1
- OFDM_SYR_OFFSET_2
- OFDM_SYR_STAT
- OFDM_SingleCarrier
- OFDM_SingleTone
- OFDM_TABLE_LENGTH
- OFDM_TABLE_SIZE
- OFDM_TABLE_SIZE_92C
- OFDM_TABLE_SIZE_92D
- OFDM_TPS_RCVD_1
- OFDM_TPS_RCVD_2
- OFDM_TPS_RCVD_3
- OFDM_TPS_RCVD_4
- OFDM_TPS_RESERVED_1
- OFDM_TPS_RESERVED_2
- OFDM_TRL_NOMINALRATE_1
- OFDM_TRL_NOMINALRATE_2
- OFDM_TRL_TIME_1
- OFDM_TX_MODE
- OFDM_Table_Length
- OFDPA_CTRL_DFLT_BRIDGING
- OFDPA_CTRL_DFLT_OVS
- OFDPA_CTRL_IPV4_MCAST
- OFDPA_CTRL_IPV6_MCAST
- OFDPA_CTRL_LINK_LOCAL_MCAST
- OFDPA_CTRL_LOCAL_ARP
- OFDPA_CTRL_MAX
- OFDPA_INTERNAL_VLAN_BITMAP_LEN
- OFDPA_INTERNAL_VLAN_ID_BASE
- OFDPA_N_INTERNAL_VLANS
- OFDPA_OP_FLAG_LEARNED
- OFDPA_OP_FLAG_NOWAIT
- OFDPA_OP_FLAG_REFRESH
- OFDPA_OP_FLAG_REMOVE
- OFDPA_PRIORITY_ACL_CTRL
- OFDPA_PRIORITY_ACL_DFLT
- OFDPA_PRIORITY_ACL_NORMAL
- OFDPA_PRIORITY_BRIDGING_TENANT
- OFDPA_PRIORITY_BRIDGING_TENANT_DFLT_EXACT
- OFDPA_PRIORITY_BRIDGING_TENANT_DFLT_WILD
- OFDPA_PRIORITY_BRIDGING_VLAN
- OFDPA_PRIORITY_BRIDGING_VLAN_DFLT_EXACT
- OFDPA_PRIORITY_BRIDGING_VLAN_DFLT_WILD
- OFDPA_PRIORITY_IG_PORT
- OFDPA_PRIORITY_TERM_MAC_MCAST
- OFDPA_PRIORITY_TERM_MAC_UCAST
- OFDPA_PRIORITY_UNKNOWN
- OFDPA_PRIORITY_VLAN
- OFDPA_UNTAGGED_VID
- OFDPA_VLAN_BITMAP_LEN
- OFDRATE0_G
- OFDRATE0_M
- OFDRATE0_S
- OFDRATE1_G
- OFDRATE1_M
- OFDRATE1_S
- OFDRATE2_G
- OFDRATE2_M
- OFDRATE2_S
- OFDRATE3_G
- OFDRATE3_M
- OFDRATE3_S
- OFDVRTSEL_F
- OFDVRTSEL_S
- OFDVRTSEL_V
- OFE_STAT
- OFF
- OFF22K
- OFF2PG
- OFFCHIP_HS_DEALLOC
- OFFCHIP_IRQ_BASE
- OFFCNT
- OFFI
- OFFLD_PARAMS_DATA_SEQ_INORDER
- OFFLD_PARAMS_DDE
- OFFLD_PARAMS_ERL
- OFFLD_PARAMS_HDE
- OFFLD_PARAMS_IMD
- OFFLD_PARAMS_IR2T
- OFFLD_PARAMS_MAX_R2T
- OFFLD_PARAMS_PDU_SEQ_INORDER
- OFFLEN
- OFFLEN_SHIFT
- OFFLOAD
- OFFLOADS_MAX_FT
- OFFLOADS_MIN_LEVEL
- OFFLOADS_NUM_PRIOS
- OFFLOADS_QUERY_CMD
- OFFLOAD_BUF_SIZE
- OFFLOAD_CONFIGURED_BIT
- OFFLOAD_DB_DROP
- OFFLOAD_DB_EMPTY
- OFFLOAD_DB_FULL
- OFFLOAD_DEVMAP_BIT
- OFFLOAD_DISABLE
- OFFLOAD_ENABLED_BIT
- OFFLOAD_IS_ON
- OFFLOAD_PORT_DOWN
- OFFLOAD_PORT_UP
- OFFLOAD_STATUS_DOWN
- OFFLOAD_STATUS_UP
- OFFOUT_EN
- OFFOUT_VAL
- OFFS
- OFFSET
- OFFSET0
- OFFSET1
- OFFSET2
- OFFSET3
- OFFSETA
- OFFSETB
- OFFSETS_B_CONV
- OFFSET_0_2
- OFFSET_1_3
- OFFSET_4
- OFFSET_4OP
- OFFSET_7
- OFFSET_8
- OFFSET_A3DIN
- OFFSET_A3DOUT
- OFFSET_ABSCENT
- OFFSET_AC98IN
- OFFSET_AC98OUT
- OFFSET_ADBDMA
- OFFSET_ADBDMAB
- OFFSET_ADD
- OFFSET_BITS
- OFFSET_BIT_MASK
- OFFSET_BIT_SHIFT
- OFFSET_CANCEL_RX
- OFFSET_CLK_NS_REG
- OFFSET_CLOCK_DIV
- OFFSET_COARSE
- OFFSET_CODECIN
- OFFSET_CODECOUT
- OFFSET_COMPENSATION_EN
- OFFSET_CON
- OFFSET_CONTINUOUS
- OFFSET_CONTROL
- OFFSET_DATA_HIGH
- OFFSET_DATA_LOW
- OFFSET_DATA_PORT
- OFFSET_DCM_EN
- OFFSET_DEBUGCTRL
- OFFSET_DEBUGSTAT
- OFFSET_DELAY_LEN
- OFFSET_EFXIN
- OFFSET_EFXOUT
- OFFSET_EN
- OFFSET_EQIN
- OFFSET_EQOUT
- OFFSET_ESID
- OFFSET_EXT_CONF
- OFFSET_FIFO_ADDR_CLR
- OFFSET_FIFO_STAT
- OFFSET_FIFO_THRESH
- OFFSET_FROM_REG
- OFFSET_GPIO_NUMBER
- OFFSET_HS
- OFFSET_IAR
- OFFSET_ICR
- OFFSET_IMR
- OFFSET_INTR_MASK
- OFFSET_INTR_STAT
- OFFSET_INT_EN
- OFFSET_INT_FLAG
- OFFSET_IN_256B_BLOCK
- OFFSET_IO_CONFIG
- OFFSET_IPR
- OFFSET_IRR
- OFFSET_LTIMING
- OFFSET_MASK
- OFFSET_MAX
- OFFSET_MIN
- OFFSET_MIXIN
- OFFSET_MIXOUT
- OFFSET_MSEC
- OFFSET_NOT_RUNNING
- OFFSET_PATH_DIR
- OFFSET_RST
- OFFSET_RSV_DEBUG
- OFFSET_RX_4G_MODE
- OFFSET_RX_C2HFFQ
- OFFSET_RX_LEN
- OFFSET_RX_MEM_ADDR
- OFFSET_RX_RX0FFQ
- OFFSET_SAMPLERATE
- OFFSET_SDIO_LOCAL
- OFFSET_SERDES_START
- OFFSET_SHIFT
- OFFSET_SHT
- OFFSET_SIGN_BIT
- OFFSET_SLAVE_ADDR
- OFFSET_SOFTRESET
- OFFSET_SPDIFIN
- OFFSET_SPDIFOUT
- OFFSET_SPORTIN
- OFFSET_SPORTOUT
- OFFSET_SRCIN
- OFFSET_SRCOUT
- OFFSET_START
- OFFSET_STEP
- OFFSET_STEP_PPT
- OFFSET_STRIDE
- OFFSET_SUBTRACT
- OFFSET_SZ
- OFFSET_TIMING
- OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE
- OFFSET_TO_ATOM_ROM_HEADER_POINTER
- OFFSET_TO_ATOM_ROM_IMAGE_SIZE
- OFFSET_TO_DP_AUX_PORT
- OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS
- OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER
- OFFSET_TO_GET_ATOMBIOS_STRINGS_START
- OFFSET_TO_GET_ATOMBIOS_STRING_START
- OFFSET_TO_PAGE_ADDR
- OFFSET_TO_PAGE_IDX
- OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER
- OFFSET_TO_REG
- OFFSET_TO_REG_CHANGE
- OFFSET_TO_REG_DATA
- OFFSET_TO_REG_DDR
- OFFSET_TO_REG_INT_EN
- OFFSET_TO_REG_INT_TYPE
- OFFSET_TO_REG_WRMASK
- OFFSET_TRANSAC_LEN
- OFFSET_TRANSFER_LEN
- OFFSET_TRANSFER_LEN_AUX
- OFFSET_TX_4G_MODE
- OFFSET_TX_BCNQ
- OFFSET_TX_BEQ
- OFFSET_TX_BKQ
- OFFSET_TX_CMDQ
- OFFSET_TX_HCCAQ
- OFFSET_TX_HIQ
- OFFSET_TX_LEN
- OFFSET_TX_MEM_ADDR
- OFFSET_TX_MGTQ
- OFFSET_TX_VIQ
- OFFSET_TX_VOQ
- OFFSET_UFS_PHY_SOFT_RESET
- OFFSET_UNITS
- OFFSET_VSID
- OFFSET_WLAN_IOREG
- OFFSET_WT0
- OFFSET_WT1
- OFFSET_WTOUT
- OFFSET_X
- OFFSET_XTALKIN
- OFFSET_XTALKOUT
- OFFSET_X_DEFAULT
- OFFSET_Y
- OFFSET_Y_DEFAULT
- OFFSET_Z
- OFFSET_b
- OFFSET_d
- OFFSET_e
- OFFSET_f
- OFFSIZE_OFFSET_MASK
- OFFSIZE_OFFSET_SHIFT
- OFFSIZE_SIZE_MASK
- OFFSIZE_SIZE_SHIFT
- OFFST
- OFFS_CON
- OFFS_CPUCTL
- OFFS_DAT
- OFFS_UP
- OFFS_WDTMRCTL
- OFFT_OFFSET_MAX
- OFF_B
- OFF_CNG_THRES
- OFF_EN
- OFF_FLAGS
- OFF_GB
- OFF_GR
- OFF_IHL
- OFF_LOWER_LT
- OFF_MODE_NAME
- OFF_PRIV1
- OFF_PRIV2
- OFF_PRIV3
- OFF_PTP_CONTROL
- OFF_PTP_SEQUENCE_ID
- OFF_PTP_SOURCE_UUID
- OFF_PULL_EN
- OFF_PULL_UP
- OFF_R
- OFF_SEQ
- OFF_SIZE
- OFF_SLAB
- OFF_STATE
- OFF_STATE_MASK
- OFF_STATE_SHIFT
- OFF_TOCB1
- OFF_TOCB2
- OFF_TOCB3
- OFF_TOCB4
- OFF_UPPER_LT
- OFF_VMDB
- OFILL
- OFLO_BIT
- OFMARKER
- OFMARKINT
- OFMT_BRAW
- OFMT_MASK
- OFMT_P_BRAW
- OFMT_RGB
- OFMT_YUV
- OFNI_BS_2SFFJ
- OFNI_EDONI_2SFFJ
- OFN_REG_RESULT_OFFSET
- OFON_PWRDN
- OFST_DMA_CTL
- OFST_DMA_DESC_H
- OFST_DMA_DESC_L
- OFST_H3A_EN_SHIFT
- OFST_IPIPE_EN_SHIFT
- OFST_SDRAM_EN_SHIFT
- OFST_STATUS
- OFST_TS_CTL
- OFST_TS_ERR
- OFSX
- OFSY
- OFSZ
- OFS_U2_PHY_AC0
- OFS_U2_PHY_AC1
- OFS_U2_PHY_AC2
- OFS_U2_PHY_ACR0
- OFS_U2_PHY_ACR1
- OFS_U2_PHY_ACR2
- OFS_U2_PHY_ACR3
- OFS_U2_PHY_ACR4
- OFS_U2_PHY_AMON0
- OFS_U2_PHY_DCR0
- OFS_U2_PHY_DCR1
- OFS_U2_PHY_DTM0
- OFS_U2_PHY_DTM1
- OFW
- OFW_BOUND
- OFW_MIN
- OF_953X
- OF_957X
- OF_BAD_ADDR
- OF_BLK
- OF_CHECK_ADDR_COUNT
- OF_CHECK_COUNTS
- OF_CONF_REQ
- OF_DATA_IN
- OF_DATA_OUT
- OF_DECLARE_1
- OF_DECLARE_1_RET
- OF_DECLARE_2
- OF_DEFAULTNORMLOG
- OF_DETACHED
- OF_DEV_AUXDATA
- OF_DISABLE_SDP
- OF_DISC_DISABLED
- OF_DT_BEGIN_NODE
- OF_DT_END
- OF_DT_END_NODE
- OF_DT_HEADER
- OF_DT_MAGIC
- OF_DT_NOP
- OF_DT_PROP
- OF_DT_VERSION
- OF_DYNAMIC
- OF_EARLYCON_DECLARE
- OF_ENABLE_TAG
- OF_EXPL_CONF
- OF_FAST_POST
- OF_FMT_422_CCIR
- OF_FMT_422_SMPT
- OF_FMT_444
- OF_FMT_MASK
- OF_FORCE_DISC
- OF_GPIO_ACTIVE_LOW
- OF_GPIO_ARGS_MIN
- OF_GPIO_OPEN_DRAIN
- OF_GPIO_PULL_DOWN
- OF_GPIO_PULL_UP
- OF_GPIO_SINGLE_ENDED
- OF_GPIO_TRANSITORY
- OF_I3C_REG1_IS_I2C_DEV
- OF_IMAP_NO_PHANDLE
- OF_IMAP_OLDWORLD_MAC
- OF_INC_RC
- OF_IS_DYNAMIC
- OF_IS_TPM2
- OF_MARK_DYNAMIC
- OF_MAX_ADDR_CELLS
- OF_NO_DATA
- OF_OVERLAY
- OF_OVERLAY_FREE_CSET
- OF_OVERLAY_POST_APPLY
- OF_OVERLAY_POST_REMOVE
- OF_OVERLAY_PRE_APPLY
- OF_OVERLAY_PRE_REMOVE
- OF_PCI_ADDR0_ALIAS
- OF_PCI_ADDR0_BARREG
- OF_PCI_ADDR0_BUS
- OF_PCI_ADDR0_DEV
- OF_PCI_ADDR0_FN
- OF_PCI_ADDR0_PREFETCH
- OF_PCI_ADDR0_RELOC
- OF_PCI_ADDR0_SPACE
- OF_PCI_ADDR0_SPACE_CFG
- OF_PCI_ADDR0_SPACE_IO
- OF_PCI_ADDR0_SPACE_MASK
- OF_PCI_ADDR0_SPACE_MMIO32
- OF_PCI_ADDR0_SPACE_MMIO64
- OF_PHANDLE_ILLEGAL
- OF_PLATFORM_DRIVER
- OF_POPULATED
- OF_POPULATED_BUS
- OF_RECONFIG_ADD_PROPERTY
- OF_RECONFIG_ATTACH_NODE
- OF_RECONFIG_CHANGE_ADD
- OF_RECONFIG_CHANGE_REMOVE
- OF_RECONFIG_DETACH_NODE
- OF_RECONFIG_NO_CHANGE
- OF_RECONFIG_REMOVE_PROPERTY
- OF_RECONFIG_UPDATE_PROPERTY
- OF_REG_SIZE
- OF_ROOT_NODE_ADDR_CELLS_DEFAULT
- OF_ROOT_NODE_SIZE_CELLS_DEFAULT
- OF_RT_ARGS_MIN
- OF_SECONDARY_BOOT
- OF_SEND_RDP
- OF_SSTS
- OF_SS_MODE_0
- OF_SS_MODE_1
- OF_SS_MODE_2
- OF_SS_MODE_3
- OF_TABLE
- OF_TERM_EXCH
- OF_TRC
- OF_USE_NATIVE_MODE
- OF_VECTOR
- OF_VP_ENABLE
- OF_WA_CLAIM
- OF_WA_LONGTRAIL
- OF_WORKAROUNDS
- OG
- OGAMC0
- OGAMC1
- OGAMC2
- OGAMC3
- OGAMC4
- OGAMC5
- OGW0
- OGW1
- OHARE_FCR
- OHARE_MBCR
- OHCI1394_ARRQ
- OHCI1394_ARRS
- OHCI1394_ATRetries
- OHCI1394_AsReqFilterHiClear
- OHCI1394_AsReqFilterHiSet
- OHCI1394_AsReqFilterLoClear
- OHCI1394_AsReqFilterLoSet
- OHCI1394_AsReqRcvCommandPtr
- OHCI1394_AsReqRcvContextBase
- OHCI1394_AsReqRcvContextControlClear
- OHCI1394_AsReqRcvContextControlSet
- OHCI1394_AsReqTrCommandPtr
- OHCI1394_AsReqTrContextBase
- OHCI1394_AsReqTrContextControlClear
- OHCI1394_AsReqTrContextControlSet
- OHCI1394_AsRspRcvCommandPtr
- OHCI1394_AsRspRcvContextBase
- OHCI1394_AsRspRcvContextControlClear
- OHCI1394_AsRspRcvContextControlSet
- OHCI1394_AsRspTrCommandPtr
- OHCI1394_AsRspTrContextBase
- OHCI1394_AsRspTrContextControlClear
- OHCI1394_AsRspTrContextControlSet
- OHCI1394_BusID
- OHCI1394_BusOptions
- OHCI1394_CSRCompareData
- OHCI1394_CSRControl
- OHCI1394_CSRData
- OHCI1394_ConfigROMhdr
- OHCI1394_ConfigROMmap
- OHCI1394_FairnessControl
- OHCI1394_GUIDHi
- OHCI1394_GUIDLo
- OHCI1394_GUID_ROM
- OHCI1394_HCControlClear
- OHCI1394_HCControlSet
- OHCI1394_HCControl_BIBimageValid
- OHCI1394_HCControl_LPS
- OHCI1394_HCControl_aPhyEnhanceEnable
- OHCI1394_HCControl_linkEnable
- OHCI1394_HCControl_noByteSwapData
- OHCI1394_HCControl_postedWriteEnable
- OHCI1394_HCControl_programPhyEnable
- OHCI1394_HCControl_softReset
- OHCI1394_IRMultiChanMaskHiClear
- OHCI1394_IRMultiChanMaskHiSet
- OHCI1394_IRMultiChanMaskLoClear
- OHCI1394_IRMultiChanMaskLoSet
- OHCI1394_InitialBandwidthAvailable
- OHCI1394_InitialChannelsAvailableHi
- OHCI1394_InitialChannelsAvailableLo
- OHCI1394_IntEventClear
- OHCI1394_IntEventSet
- OHCI1394_IntMaskClear
- OHCI1394_IntMaskSet
- OHCI1394_IsoRcvCommandPtr
- OHCI1394_IsoRcvContextBase
- OHCI1394_IsoRcvContextControlClear
- OHCI1394_IsoRcvContextControlSet
- OHCI1394_IsoRcvContextMatch
- OHCI1394_IsoRecvIntEventClear
- OHCI1394_IsoRecvIntEventSet
- OHCI1394_IsoRecvIntMaskClear
- OHCI1394_IsoRecvIntMaskSet
- OHCI1394_IsoXmitCommandPtr
- OHCI1394_IsoXmitContextBase
- OHCI1394_IsoXmitContextControlClear
- OHCI1394_IsoXmitContextControlSet
- OHCI1394_IsoXmitIntEventClear
- OHCI1394_IsoXmitIntEventSet
- OHCI1394_IsoXmitIntMaskClear
- OHCI1394_IsoXmitIntMaskSet
- OHCI1394_IsochronousCycleTimer
- OHCI1394_LinkControlClear
- OHCI1394_LinkControlSet
- OHCI1394_LinkControl_cycleMaster
- OHCI1394_LinkControl_cycleSource
- OHCI1394_LinkControl_cycleTimerEnable
- OHCI1394_LinkControl_rcvPhyPkt
- OHCI1394_LinkControl_rcvSelfID
- OHCI1394_MAX_AT_REQ_RETRIES
- OHCI1394_MAX_AT_RESP_RETRIES
- OHCI1394_MAX_PHYS_RESP_RETRIES
- OHCI1394_NodeID
- OHCI1394_NodeID_busNumber
- OHCI1394_NodeID_idValid
- OHCI1394_NodeID_nodeNumber
- OHCI1394_NodeID_root
- OHCI1394_PCI_HCI_Control
- OHCI1394_PhyControl
- OHCI1394_PhyControl_Read
- OHCI1394_PhyControl_ReadData
- OHCI1394_PhyControl_ReadDone
- OHCI1394_PhyControl_Write
- OHCI1394_PhyControl_WritePending
- OHCI1394_PhyReqFilterHiClear
- OHCI1394_PhyReqFilterHiSet
- OHCI1394_PhyReqFilterLoClear
- OHCI1394_PhyReqFilterLoSet
- OHCI1394_PhyUpperBound
- OHCI1394_PostedWriteAddressHi
- OHCI1394_PostedWriteAddressLo
- OHCI1394_REGISTER_SIZE
- OHCI1394_RQPkt
- OHCI1394_RSPkt
- OHCI1394_SelfIDBuffer
- OHCI1394_SelfIDCount
- OHCI1394_SelfIDCount_selfIDError
- OHCI1394_VendorID
- OHCI1394_Version
- OHCI1394_busReset
- OHCI1394_cycle64Seconds
- OHCI1394_cycleInconsistent
- OHCI1394_cycleLost
- OHCI1394_cycleSynch
- OHCI1394_cycleTooLong
- OHCI1394_evt_bus_reset
- OHCI1394_evt_data_read
- OHCI1394_evt_data_write
- OHCI1394_evt_descriptor_read
- OHCI1394_evt_flushed
- OHCI1394_evt_long_packet
- OHCI1394_evt_missing_ack
- OHCI1394_evt_no_status
- OHCI1394_evt_overrun
- OHCI1394_evt_reserved_b
- OHCI1394_evt_reserved_c
- OHCI1394_evt_tcode_err
- OHCI1394_evt_timeout
- OHCI1394_evt_underrun
- OHCI1394_evt_unknown
- OHCI1394_isochRx
- OHCI1394_isochTx
- OHCI1394_lockRespErr
- OHCI1394_masterIntEnable
- OHCI1394_phy
- OHCI1394_phyRegRcvd
- OHCI1394_phy_tcode
- OHCI1394_postedWriteErr
- OHCI1394_regAccessFail
- OHCI1394_reqTxComplete
- OHCI1394_respTxComplete
- OHCI1394_selfIDComplete
- OHCI1394_unrecoverableError
- OHCI_BLF
- OHCI_CLF
- OHCI_CMDSTATUS
- OHCI_CONTROL
- OHCI_CONTROL_INIT
- OHCI_CTRL_BLE
- OHCI_CTRL_CBSR
- OHCI_CTRL_CLE
- OHCI_CTRL_HCFS
- OHCI_CTRL_IE
- OHCI_CTRL_IR
- OHCI_CTRL_MASK
- OHCI_CTRL_PLE
- OHCI_CTRL_RWC
- OHCI_CTRL_RWE
- OHCI_FMINTERVAL
- OHCI_HCCTRL_LEN
- OHCI_HCCTRL_OFFSET
- OHCI_HCFS
- OHCI_HCR
- OHCI_INTRDISABLE
- OHCI_INTRENABLE
- OHCI_INTRSTATUS
- OHCI_INTR_FNO
- OHCI_INTR_INIT
- OHCI_INTR_MIE
- OHCI_INTR_OC
- OHCI_INTR_RD
- OHCI_INTR_RHSC
- OHCI_INTR_SF
- OHCI_INTR_SO
- OHCI_INTR_UE
- OHCI_INTR_WDH
- OHCI_LOOP_COUNT
- OHCI_MAX_CLKS
- OHCI_OCR
- OHCI_OVRCUR_POL
- OHCI_PARAM_DEBUG_AT_AR
- OHCI_PARAM_DEBUG_BUSRESETS
- OHCI_PARAM_DEBUG_IRQS
- OHCI_PARAM_DEBUG_SELFIDS
- OHCI_PRIV_PORT1_HOST_MASK
- OHCI_PRIV_PORT1_HOST_SHIFT
- OHCI_PRIV_REG
- OHCI_PRIV_REG_SWAP_MASK
- OHCI_PRIV_REG_SWAP_SHIFT
- OHCI_QUIRK_AMD756
- OHCI_QUIRK_AMD_PLL
- OHCI_QUIRK_AMD_PREFETCH
- OHCI_QUIRK_BE_DESC
- OHCI_QUIRK_BE_MMIO
- OHCI_QUIRK_FRAME_NO
- OHCI_QUIRK_GLOBAL_SUSPEND
- OHCI_QUIRK_HUB_POWER
- OHCI_QUIRK_INITRESET
- OHCI_QUIRK_NEC
- OHCI_QUIRK_QEMU
- OHCI_QUIRK_SUPERIO
- OHCI_QUIRK_ZFMICRO
- OHCI_RH_HALTED
- OHCI_RH_RUNNING
- OHCI_RH_SUSPENDED
- OHCI_SCHED_ENABLES
- OHCI_SOC
- OHCI_TCODE_PHY_PACKET
- OHCI_USB_OPER
- OHCI_USB_RESET
- OHCI_USB_RESUME
- OHCI_USB_SUSPEND
- OHCI_VERSION_1_1
- OH_BAY_DEV_MASK
- OH_BAY_FLOPPY_ENABLE
- OH_BAY_IDE_ENABLE
- OH_BAY_PCI_ENABLE
- OH_BAY_POWER_N
- OH_BAY_RESET_N
- OH_FLOPPY_ENABLE
- OH_IDE0_ENABLE
- OH_IDE0_RESET_N
- OH_IDE1_RESET_N
- OH_IOBUS_ENABLE
- OH_MESH_ENABLE
- OH_SCCA_IO
- OH_SCCB_IO
- OH_SCC_ENABLE
- OH_SCC_RESET
- OH_VIA_ENABLE
- OID
- OID_
- OID_802_11_CAPABILITY
- OID_802_11_PMKID
- OID_CE_USB_READ_REGISTRY
- OID_CE_USB_WRITE_REGISTRY
- OID_COUNTER_FIRST
- OID_COUNTER_LAST
- OID_COUNTER_RCV_ERROR
- OID_COUNTER_UNKOWN
- OID_COUNTER_XMIT_ERROR
- OID_FLAG_CACHED
- OID_FLAG_TYPE
- OID_GEN_RECEIVE_SCALE_CAPABILITIES
- OID_GEN_RECEIVE_SCALE_PARAMETERS
- OID_INL_COMPONENT_ID
- OID_INL_COMPONENT_NR
- OID_INL_CONFIG
- OID_INL_CONFORMANCE_FLEXIBLE
- OID_INL_CONFORMANCE_NONE
- OID_INL_CONFORMANCE_STRICT
- OID_INL_DOT11D_CONFORMANCE
- OID_INL_INTERFACE_ID
- OID_INL_MEMADDR
- OID_INL_MEMORY
- OID_INL_MODE
- OID_INL_OUTPUTPOWER
- OID_INL_PHYCAPABILITIES
- OID_INL_TUNNEL
- OID_INL_VERSION
- OID_MP_SEG1
- OID_MP_SEG2
- OID_MP_SEG3
- OID_MP_SEG4
- OID_NDIS_SEG1
- OID_NDIS_SEG10
- OID_NDIS_SEG2
- OID_NDIS_SEG3
- OID_NDIS_SEG4
- OID_NDIS_SEG5
- OID_NDIS_SEG6
- OID_NDIS_SEG7
- OID_NDIS_SEG8
- OID_NDIS_SEG9
- OID_NUM_LAST
- OID_OFFLOAD_ENCAPSULATION
- OID_RT_AP_GET_ASSOCIATED_STATION_LIST
- OID_RT_AP_GET_CURRENT_TIME_STAMP
- OID_RT_AP_SET_DTIM_PERIOD
- OID_RT_AP_SET_PASSPHRASE
- OID_RT_AP_SUPPORTED
- OID_RT_AP_SWITCH_INTO_AP_MODE
- OID_RT_AUTH_STATUS
- OID_RT_CHANNELPLAN_BY_COUNTRY
- OID_RT_CURRENT_TX_POWER_LEVEL
- OID_RT_DEDICATE_PROBE
- OID_RT_DESIRED_RATES
- OID_RT_DRIVER_OPTION
- OID_RT_FORCED_DATA_RATE
- OID_RT_GET_AP_IP
- OID_RT_GET_BSS_WIRELESS_MODE
- OID_RT_GET_CCA_ERR
- OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES
- OID_RT_GET_CCA_FALLBACK_THRESHOLD
- OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES
- OID_RT_GET_CCA_UPGRADE_THRESHOLD
- OID_RT_GET_CHANNEL
- OID_RT_GET_CHANNELPLAN
- OID_RT_GET_CHANNEL_LIST
- OID_RT_GET_CONNECT_STATE
- OID_RT_GET_DCST_CURRENT_THRESHOLD
- OID_RT_GET_DCST_EVALUATE_PERIOD
- OID_RT_GET_DCST_TIME_UNIT_INDEX
- OID_RT_GET_DRIVER_UP_DELTA_TIME
- OID_RT_GET_EFUSE_CURRENT_SIZE
- OID_RT_GET_EFUSE_MAX_SIZE
- OID_RT_GET_ENC_KEY_MATCH_COUNT
- OID_RT_GET_ENC_KEY_MISMATCH_COUNT
- OID_RT_GET_HARDWARE_RADIO_OFF
- OID_RT_GET_HARDWARE_VERSION
- OID_RT_GET_HEADER_FAIL
- OID_RT_GET_IS_PRIVACY
- OID_RT_GET_IS_ROAMING
- OID_RT_GET_KEY_MISMATCH
- OID_RT_GET_LARGE_PACKET_CRC
- OID_RT_GET_LOG
- OID_RT_GET_MIDDLE_PACKET_CRC
- OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR
- OID_RT_GET_PHY_RX_PACKET_RECEIVED
- OID_RT_GET_POWER_MODE
- OID_RT_GET_PREAMBLE_MODE
- OID_RT_GET_RF_VENDER
- OID_RT_GET_RX_ICV_ERR
- OID_RT_GET_RX_RETRY
- OID_RT_GET_RX_TOTAL_PACKET
- OID_RT_GET_SCAN_IN_PROGRESS
- OID_RT_GET_SIGNAL_QUALITY
- OID_RT_GET_SMALL_PACKET_CRC
- OID_RT_GET_TOTAL_RX_BYTES
- OID_RT_GET_TOTAL_TX_BYTES
- OID_RT_GET_TX_BEACON_ERR
- OID_RT_GET_TX_BEACON_OK
- OID_RT_GET_TX_INFO
- OID_RT_GET_TX_RETRY
- OID_RT_INTEL_PROMISCUOUS_MODE
- OID_RT_MH_VENDER_ID
- OID_RT_POLL_RX_STATUS
- OID_RT_PRO8187_WI_POLL
- OID_RT_PRO8711_JOIN_BSS
- OID_RT_PRO8711_PKT_LOSS
- OID_RT_PRO8711_WI_POLL
- OID_RT_PRO_871X_DRV_EXT
- OID_RT_PRO_ADD_STA_INFO
- OID_RT_PRO_BURST_READ_REGISTER
- OID_RT_PRO_BURST_WRITE_REGISTER
- OID_RT_PRO_CFG_DEBUG_MESSAGE
- OID_RT_PRO_DELE_STA_INFO
- OID_RT_PRO_EFUSE
- OID_RT_PRO_EFUSE_MAP
- OID_RT_PRO_ENCRYPTION_CTRL
- OID_RT_PRO_FOR_EVM_TEST_SETTING
- OID_RT_PRO_GET_CR_SIGNAL_QUALITY
- OID_RT_PRO_GET_INTEGRATOR
- OID_RT_PRO_GET_SIGNAL_QUALITY
- OID_RT_PRO_GET_THERMAL_METER
- OID_RT_PRO_GET_TX_POWER_CONTROL
- OID_RT_PRO_H2C_C2H_LBK_TEST
- OID_RT_PRO_H2C_CMD_EVENT_MODE
- OID_RT_PRO_H2C_CMD_MODE
- OID_RT_PRO_H2C_CMD_RSP_MODE
- OID_RT_PRO_H2C_GET_RATE_TABLE
- OID_RT_PRO_H2C_QUERY_RESULT
- OID_RT_PRO_H2C_SET_COMMAND
- OID_RT_PRO_H2C_SET_RATE_TABLE
- OID_RT_PRO_QRY_PWRMGT_TEST
- OID_RT_PRO_QRY_PWRSTATE
- OID_RT_PRO_QUERY_CURRENT_ADDRESS
- OID_RT_PRO_QUERY_DR_VARIABLE
- OID_RT_PRO_QUERY_EEPROM_TYPE
- OID_RT_PRO_QUERY_PERMANENT_ADDRESS
- OID_RT_PRO_QUERY_RF_TYPE
- OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR
- OID_RT_PRO_QUERY_RX_PACKET_RECEIVED
- OID_RT_PRO_QUERY_TX_PACKET_SENT
- OID_RT_PRO_READ16_EEPROM
- OID_RT_PRO_READ_BB_REG
- OID_RT_PRO_READ_CIS_DATA
- OID_RT_PRO_READ_EEPROM
- OID_RT_PRO_READ_EEPROM_BYTE
- OID_RT_PRO_READ_EFUSE
- OID_RT_PRO_READ_MAC_ADDRESS
- OID_RT_PRO_READ_POWER_CONTROL
- OID_RT_PRO_READ_REGISTER
- OID_RT_PRO_READ_RF_REG
- OID_RT_PRO_READ_TSSI
- OID_RT_PRO_RECEIVE_PACKET
- OID_RT_PRO_RESET_DUT
- OID_RT_PRO_RESET_RX_PACKET_RECEIVED
- OID_RT_PRO_RESET_TX_PACKET_SENT
- OID_RT_PRO_RF_READ_REGISTRY
- OID_RT_PRO_RF_WRITE_REGISTRY
- OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST
- OID_RT_PRO_RW_EFUSE_PGPKT
- OID_RT_PRO_RX_FILTER
- OID_RT_PRO_RX_FILTER_PATTERN
- OID_RT_PRO_RX_PACKET_TYPE
- OID_RT_PRO_SCSI_ACCESS_TEST
- OID_RT_PRO_SCSI_AUTO_TEST
- OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN
- OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT
- OID_RT_PRO_SET_ANTENNA_BB
- OID_RT_PRO_SET_BASIC_RATE
- OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE
- OID_RT_PRO_SET_BB_RF_STANDBY_MODE
- OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX
- OID_RT_PRO_SET_CHANNEL_DIRECT_CALL
- OID_RT_PRO_SET_CONTINUOUS_TX
- OID_RT_PRO_SET_CR_NEW_FILTER
- OID_RT_PRO_SET_CR_SCRAMBLER
- OID_RT_PRO_SET_CR_SETPOINT
- OID_RT_PRO_SET_CR_TX_CONFIG
- OID_RT_PRO_SET_DATA_RATE
- OID_RT_PRO_SET_DATA_RATE_EX
- OID_RT_PRO_SET_FILTER_BB
- OID_RT_PRO_SET_FW_DIG_STATE
- OID_RT_PRO_SET_FW_RA_STATE
- OID_RT_PRO_SET_INITIAL_GAIN
- OID_RT_PRO_SET_INTEGRATOR
- OID_RT_PRO_SET_MANUAL_DIVERSITY_BB
- OID_RT_PRO_SET_MODULATION
- OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS
- OID_RT_PRO_SET_PKT_TEST_MODE
- OID_RT_PRO_SET_POWER_TRACKING
- OID_RT_PRO_SET_PREAMBLE
- OID_RT_PRO_SET_PWRSTATE
- OID_RT_PRO_SET_RF_INTFS
- OID_RT_PRO_SET_RX_CHARGE_PUMP
- OID_RT_PRO_SET_SCRAMBLER
- OID_RT_PRO_SET_SIGNAL_QUALITY
- OID_RT_PRO_SET_SINGLE_CARRIER_TX
- OID_RT_PRO_SET_SINGLE_TONE_TX
- OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL
- OID_RT_PRO_SET_TX_AGC_OFFSET
- OID_RT_PRO_SET_TX_ANTENNA_BB
- OID_RT_PRO_SET_TX_CHARGE_PUMP
- OID_RT_PRO_SET_TX_POWER_CONTROL
- OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL
- OID_RT_PRO_START_TEST
- OID_RT_PRO_STOP_TEST
- OID_RT_PRO_SYNCPAGERW_SRAM
- OID_RT_PRO_USB_MAC_AC_FIFO_WRITE
- OID_RT_PRO_USB_MAC_RX_FIFO_POLLING
- OID_RT_PRO_USB_MAC_RX_FIFO_READ
- OID_RT_PRO_USB_VENDOR_REQ
- OID_RT_PRO_WAIT_C2H_EVENT
- OID_RT_PRO_WRITE16_EEPROM
- OID_RT_PRO_WRITE_BB_REG
- OID_RT_PRO_WRITE_CIS_DATA
- OID_RT_PRO_WRITE_EEPROM
- OID_RT_PRO_WRITE_EEPROM_BYTE
- OID_RT_PRO_WRITE_EFUSE
- OID_RT_PRO_WRITE_MAC_ADDRESS
- OID_RT_PRO_WRITE_POWER_CONTROL
- OID_RT_PRO_WRITE_REGISTER
- OID_RT_PRO_WRITE_RF_REG
- OID_RT_PRO_WRITE_TXCMD
- OID_RT_QRY_POLL_WKITEM
- OID_RT_RD_ATTRIB_MEM
- OID_RT_RESCAN
- OID_RT_RESET_LOG
- OID_RT_RESET_PHY_RX_PACKET_COUNT
- OID_RT_RF_OFF
- OID_RT_RF_READ_WRITE
- OID_RT_RF_READ_WRITE_OFFSET
- OID_RT_RPO_ASYNC_RWIO_POLL
- OID_RT_RPO_ASYNC_RWIO_TEST
- OID_RT_RPO_SET_PWRMGT_TEST
- OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL
- OID_RT_RRO_RX_PKT_VIA_IOCTRL
- OID_RT_SCAN_AVAILABLE_BSSID
- OID_RT_SCAN_WITH_MAGIC_PACKET
- OID_RT_SET_BANDWIDTH
- OID_RT_SET_BCN_INTVL
- OID_RT_SET_BURST_READ_REG
- OID_RT_SET_BURST_WRITE_REG
- OID_RT_SET_CHANNEL
- OID_RT_SET_CHANNELPLAN
- OID_RT_SET_CRYSTAL_CAP
- OID_RT_SET_DEFAULT_KEY_ID
- OID_RT_SET_ENCRYPTION_ALGORITHM
- OID_RT_SET_INDICATE_HIDDEN_AP
- OID_RT_SET_KEY_LENGTH
- OID_RT_SET_NO_AUTO_RESCAN
- OID_RT_SET_POWER_DOWN
- OID_RT_SET_PREAMBLE_MODE
- OID_RT_SET_RATE_ADAPTIVE
- OID_RT_SET_READ16_EEPROM
- OID_RT_SET_READ_REG
- OID_RT_SET_RSSI_ROAM_SIGNAL_TH
- OID_RT_SET_RSSI_ROAM_TRAFFIC_TH
- OID_RT_SET_RX_PACKET_TYPE
- OID_RT_SET_SNIFFER_MODE
- OID_RT_SET_WRITE16_EEPROM
- OID_RT_SET_WRITE_REG
- OID_RT_SET_WRITE_TXCMD
- OID_RT_SUPPORTED_RATES
- OID_RT_SUPPORTED_WIRELESS_MODE
- OID_RT_UTILITY_FALSE_ALARM_COUNTERS
- OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS
- OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS
- OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS
- OID_RT_UTILITY_GET_RSSI_STATUS
- OID_RT_UTILITY_SELECT_DEBUG_MODE
- OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER
- OID_RT_WIRELESS_MODE
- OID_RT_WIRELESS_MODE_FOR_SCAN_LIST
- OID_RT_WIRELESS_MODE_STARTING_ADHOC
- OID_RT_WR_ATTRIB_MEM
- OID_STR
- OID_STRUCT
- OID_STRUCT_C
- OID_STRUCT_MLME
- OID_STRUCT_MLMEEX
- OID_TCP_CONNECTION_OFFLOAD_CURRENT_CONFIG
- OID_TCP_CONNECTION_OFFLOAD_HARDWARE_CAPABILITIES
- OID_TCP_OFFLOAD_CURRENT_CONFIG
- OID_TCP_OFFLOAD_HARDWARE_CAPABILITIES
- OID_TCP_OFFLOAD_PARAMETERS
- OID_TYPE_ADDR
- OID_TYPE_ATTACH
- OID_TYPE_BSS
- OID_TYPE_BSSLIST
- OID_TYPE_BUFFER
- OID_TYPE_FREQUENCIES
- OID_TYPE_KEY
- OID_TYPE_MLME
- OID_TYPE_MLMEEX
- OID_TYPE_RAW
- OID_TYPE_SSID
- OID_TYPE_U32
- OID_U32
- OID_U32_C
- OID_UNKNOWN
- OID__NR
- OID_authorityKeyIdentifier
- OID_basicConstraints
- OID_certAuthInfoAccess
- OID_certPolicies
- OID_commonName
- OID_contentType
- OID_countryName
- OID_crlDistributionPoints
- OID_data
- OID_description
- OID_email_address
- OID_extKeyUsage
- OID_generationalQualifier
- OID_givenName
- OID_gost2012Digest256
- OID_gost2012Digest512
- OID_gost2012PKey256
- OID_gost2012PKey512
- OID_gost2012Signature256
- OID_gost2012Signature512
- OID_gostCPSignA
- OID_gostCPSignB
- OID_gostCPSignC
- OID_gostTC26Sign256A
- OID_gostTC26Sign256B
- OID_gostTC26Sign256C
- OID_gostTC26Sign256D
- OID_gostTC26Sign512A
- OID_gostTC26Sign512B
- OID_gostTC26Sign512C
- OID_id_dsa
- OID_id_dsa_with_sha1
- OID_id_ecPublicKey
- OID_id_ecdsa_with_sha1
- OID_initials
- OID_issuerAltName
- OID_keyUsage
- OID_locality
- OID_md2
- OID_md2WithRSAEncryption
- OID_md3WithRSAEncryption
- OID_md4
- OID_md4WithRSAEncryption
- OID_md5
- OID_messageDigest
- OID_msIndirectData
- OID_msIndividualSPKeyPurpose
- OID_msOutlookExpress
- OID_msPeImageDataObjId
- OID_msSpOpusInfo
- OID_msStatementType
- OID_name
- OID_organizationName
- OID_organizationUnitName
- OID_rsaEncryption
- OID_sha1
- OID_sha1WithRSAEncryption
- OID_sha224
- OID_sha224WithRSAEncryption
- OID_sha256
- OID_sha256WithRSAEncryption
- OID_sha384
- OID_sha384WithRSAEncryption
- OID_sha512
- OID_sha512WithRSAEncryption
- OID_signed_data
- OID_signingTime
- OID_smimeAuthenticatedAttrs
- OID_smimeCapabilites
- OID_stateOrProvinceName
- OID_subjectAltName
- OID_subjectKeyIdentifier
- OID_surname
- OID_title
- OIEN
- OIER
- OIER_E
- OIER_E0
- OIER_E1
- OIER_E2
- OIER_E3
- OIF_ISP_PAD
- OIF_JPEG_PAD
- OIF_NUM_PADS
- OIF_SOURCE_PAD
- OIM
- OIMM5
- OIRQ
- OIS
- OI_LS_NORMAL
- OI_LS_PARENT
- OI_LS_REFLINK_TARGET
- OI_LS_RENAME1
- OI_LS_RENAME2
- OI_STAT_ACTIVE
- OI_STAT_LAST
- OI_STAT_PRESENT
- OI_STAT_VALID
- OK
- OKAY_TO_TAKEBACK
- OKISEMI_ML7223m_IOH
- OKISEMI_ML7223n_IOH
- OK_ENC_OR_DEC
- OK_STAT
- OK_id
- OLAND_MC_UCODE_SIZE
- OLAND_SMC_UCODE_SIZE
- OLAND_SMC_UCODE_START
- OLCUC
- OLC_FOR_AR9280_20_LATER
- OLC_FOR_AR9287_10_LATER
- OLD
- OLDCLR
- OLDCMD
- OLDDIM
- OLDDST
- OLDINSTR
- OLDINSTR_2
- OLDINSTR_3
- OLDINSTR_PADDING
- OLDMEM_BASE
- OLDMEM_BASE_OFFSET
- OLDMEM_SIZE
- OLDMEM_SIZE_OFFSET
- OLDSRC
- OLD_BACKLIGHT_MAX
- OLD_BUF_SIZE
- OLD_BUSY
- OLD_CD
- OLD_CL_ADDRESS
- OLD_CL_MAGIC
- OLD_DT_HIOS
- OLD_DT_LOOS
- OLD_ERR_STS_WAR_OFFSET
- OLD_FLAT_RELOC_TYPE_BSS
- OLD_FLAT_RELOC_TYPE_DATA
- OLD_FLAT_RELOC_TYPE_TEXT
- OLD_FLAT_VERSION
- OLD_ICH_FORCE_HPET_RESUME
- OLD_IO
- OLD_LANCE
- OLD_MODE
- OLD_MSG
- OLD_NCURSES
- OLD_RIEBL
- OLD_RINGBUF_TYPE_DATA
- OLD_RINGBUF_TYPE_PADDING
- OLD_RINGBUF_TYPE_TIME_EXTEND
- OLD_RINGBUF_TYPE_TIME_STAMP
- OLD_SCLK_MIPI_CLK_NAME
- OLD_SCSI_PHASE
- OLD_STYLE
- OLD_TO_NEW
- OLD_ZNODE_AGE
- OLF
- OLF1
- OLIMEX_ARM_USB_OCD_H_PID
- OLIMEX_ARM_USB_OCD_PID
- OLIMEX_ARM_USB_TINY_H_PID
- OLIMEX_ARM_USB_TINY_PID
- OLIMEX_VID
- OLIVETTI_PRODUCT_OLICARD100
- OLIVETTI_PRODUCT_OLICARD120
- OLIVETTI_PRODUCT_OLICARD140
- OLIVETTI_PRODUCT_OLICARD145
- OLIVETTI_PRODUCT_OLICARD155
- OLIVETTI_PRODUCT_OLICARD160
- OLIVETTI_PRODUCT_OLICARD200
- OLIVETTI_PRODUCT_OLICARD500
- OLIVETTI_VENDOR_ID
- OLOGSIZE
- OLPC_DCON_BLANK
- OLPC_DCON_H_
- OLPC_DCON_IRQ
- OLPC_DCON_LOAD
- OLPC_DCON_STAT0
- OLPC_DCON_STAT1
- OLPC_F_DCON
- OLPC_F_PRESENT
- OLPC_GPIO_DCON_BLANK
- OLPC_GPIO_DCON_IRQ
- OLPC_GPIO_DCON_LOAD
- OLPC_GPIO_DCON_STAT0
- OLPC_GPIO_DCON_STAT1
- OLPC_GPIO_ECSCI
- OLPC_GPIO_LID
- OLPC_GPIO_MIC_AC
- OLPC_GPIO_SMB_CLK
- OLPC_GPIO_SMB_DATA
- OLPC_GPIO_THRM_ALRM
- OLPC_GPIO_WORKAUX
- OLPC_OFW_PDE_NR
- OLPC_OFW_SIG
- OLQF_CLEAN
- OLT_LED_CTL
- OLYMPUS_MXL_INFO
- OMAGIC
- OMAP1510P1_PPT_CONTROL
- OMAP1510P1_PPT_DATA
- OMAP1510P1_PPT_STATUS
- OMAP1510_BASE_BAUD
- OMAP1510_BIG_SLEEP_REQUEST
- OMAP1510_DEEP_SLEEP_REQUEST
- OMAP1510_DMA_LCD_BASE
- OMAP1510_DMA_LCD_BOT_F1_L
- OMAP1510_DMA_LCD_BOT_F1_U
- OMAP1510_DMA_LCD_CTRL
- OMAP1510_DMA_LCD_TOP_F1_L
- OMAP1510_DMA_LCD_TOP_F1_U
- OMAP1510_DSPREG_BASE
- OMAP1510_DSPREG_SIZE
- OMAP1510_DSPREG_START
- OMAP1510_DSP_BASE
- OMAP1510_DSP_MMU_BASE
- OMAP1510_DSP_SIZE
- OMAP1510_DSP_START
- OMAP1510_FPGA_AUDIO
- OMAP1510_FPGA_BASE
- OMAP1510_FPGA_BOARD_REV
- OMAP1510_FPGA_DIP
- OMAP1510_FPGA_ETHR_START
- OMAP1510_FPGA_FPGA_IO
- OMAP1510_FPGA_HID_ATN
- OMAP1510_FPGA_HID_MISO
- OMAP1510_FPGA_HID_MOSI
- OMAP1510_FPGA_HID_RESETn
- OMAP1510_FPGA_HID_SCLK
- OMAP1510_FPGA_HID_nHSUS
- OMAP1510_FPGA_HID_nSS
- OMAP1510_FPGA_HID_rsrvd
- OMAP1510_FPGA_HOST_RESET
- OMAP1510_FPGA_IMR_HI
- OMAP1510_FPGA_IMR_LO
- OMAP1510_FPGA_ISR_HI
- OMAP1510_FPGA_ISR_LO
- OMAP1510_FPGA_LCD_PANEL_CONTROL
- OMAP1510_FPGA_LED_DIGIT
- OMAP1510_FPGA_OMAP1510_STATUS
- OMAP1510_FPGA_PCR_48MHZ_CLK
- OMAP1510_FPGA_PCR_4MHZ_CLK
- OMAP1510_FPGA_PCR_COM1_EN
- OMAP1510_FPGA_PCR_COM2_EN
- OMAP1510_FPGA_PCR_EXP_PD0
- OMAP1510_FPGA_PCR_EXP_PD1
- OMAP1510_FPGA_PCR_IF_PD0
- OMAP1510_FPGA_PCR_RSRVD_BIT0
- OMAP1510_FPGA_POWER
- OMAP1510_FPGA_RESET_VALUE
- OMAP1510_FPGA_REV_HIGH
- OMAP1510_FPGA_REV_LOW
- OMAP1510_FPGA_RST
- OMAP1510_FPGA_SIZE
- OMAP1510_FPGA_START
- OMAP1510_FPGA_TOUCHSCREEN
- OMAP1510_FPGA_UART1
- OMAP1510_FPGA_UART2
- OMAP1510_GPIO_BASE
- OMAP1510_GPIO_DATA_INPUT
- OMAP1510_GPIO_DATA_OUTPUT
- OMAP1510_GPIO_DIR_CONTROL
- OMAP1510_GPIO_INT_CONTROL
- OMAP1510_GPIO_INT_MASK
- OMAP1510_GPIO_INT_STATUS
- OMAP1510_GPIO_PIN_CONTROL
- OMAP1510_IDLE_CLOCK_DOMAINS
- OMAP1510_IDLE_LOOP_REQUEST
- OMAP1510_IDLLCD_ARM_SHIFT
- OMAP1510_IH_GPIO_BASE
- OMAP1510_INT_ETHER
- OMAP1510_INT_FPGA
- OMAP1510_INT_FPGA10
- OMAP1510_INT_FPGA11
- OMAP1510_INT_FPGA12
- OMAP1510_INT_FPGA17
- OMAP1510_INT_FPGA2
- OMAP1510_INT_FPGA22
- OMAP1510_INT_FPGA23
- OMAP1510_INT_FPGA3
- OMAP1510_INT_FPGA4
- OMAP1510_INT_FPGA5
- OMAP1510_INT_FPGA6
- OMAP1510_INT_FPGA7
- OMAP1510_INT_FPGA8
- OMAP1510_INT_FPGA9
- OMAP1510_INT_FPGAUART1
- OMAP1510_INT_FPGAUART2
- OMAP1510_INT_FPGA_ACK
- OMAP1510_INT_FPGA_ATN
- OMAP1510_INT_FPGA_CAM
- OMAP1510_INT_FPGA_CD
- OMAP1510_INT_FPGA_RTC_A
- OMAP1510_INT_FPGA_RTC_B
- OMAP1510_INT_FPGA_TS
- OMAP1510_LB_CLOCK_DIV
- OMAP1510_LB_MEMSIZE
- OMAP1510_LB_MMU_CAM_H
- OMAP1510_LB_MMU_CAM_L
- OMAP1510_LB_MMU_CTL
- OMAP1510_LB_MMU_LCK
- OMAP1510_LB_MMU_LD_TLB
- OMAP1510_LB_MMU_RAM_H
- OMAP1510_LB_MMU_RAM_L
- OMAP1510_LB_OFFSET
- OMAP1510_MCBSP1_BASE
- OMAP1510_MCBSP2_BASE
- OMAP1510_MCBSP3_BASE
- OMAP15XX_MCBSP_COUNT
- OMAP15XX_MCBSP_RES_SZ
- OMAP15XX_NR_MMC
- OMAP1610_DMA_LCD_BASE
- OMAP1610_DMA_LCD_BOT_B1_L
- OMAP1610_DMA_LCD_BOT_B1_U
- OMAP1610_DMA_LCD_BOT_B2_L
- OMAP1610_DMA_LCD_BOT_B2_U
- OMAP1610_DMA_LCD_CCR
- OMAP1610_DMA_LCD_CSDP
- OMAP1610_DMA_LCD_CTRL
- OMAP1610_DMA_LCD_LCH_CTRL
- OMAP1610_DMA_LCD_SRC_EI_B1
- OMAP1610_DMA_LCD_SRC_EN_B1
- OMAP1610_DMA_LCD_SRC_FI_B1_L
- OMAP1610_DMA_LCD_SRC_FI_B1_U
- OMAP1610_DMA_LCD_SRC_FN_B1
- OMAP1610_DMA_LCD_TOP_B1_L
- OMAP1610_DMA_LCD_TOP_B1_U
- OMAP1610_DMA_LCD_TOP_B2_L
- OMAP1610_DMA_LCD_TOP_B2_U
- OMAP1610_ETHR_START
- OMAP1610_GPIO1_BASE
- OMAP1610_GPIO2_BASE
- OMAP1610_GPIO3_BASE
- OMAP1610_GPIO4_BASE
- OMAP1610_GPIO_CLEAR_DATAOUT
- OMAP1610_GPIO_CLEAR_IRQENABLE1
- OMAP1610_GPIO_CLEAR_WAKEUPENA
- OMAP1610_GPIO_DATAIN
- OMAP1610_GPIO_DATAOUT
- OMAP1610_GPIO_DIRECTION
- OMAP1610_GPIO_EDGE_CTRL1
- OMAP1610_GPIO_EDGE_CTRL2
- OMAP1610_GPIO_IRQENABLE1
- OMAP1610_GPIO_IRQSTATUS1
- OMAP1610_GPIO_REVISION
- OMAP1610_GPIO_SET_DATAOUT
- OMAP1610_GPIO_SET_IRQENABLE1
- OMAP1610_GPIO_SET_WAKEUPENA
- OMAP1610_GPIO_SYSCONFIG
- OMAP1610_GPIO_SYSSTATUS
- OMAP1610_GPIO_WAKEUPENABLE
- OMAP1610_GPTIMER1_BASE
- OMAP1610_GPTIMER2_BASE
- OMAP1610_GPTIMER3_BASE
- OMAP1610_GPTIMER4_BASE
- OMAP1610_GPTIMER5_BASE
- OMAP1610_GPTIMER6_BASE
- OMAP1610_GPTIMER7_BASE
- OMAP1610_GPTIMER8_BASE
- OMAP1610_IDLECT1_SLEEP_VAL
- OMAP1610_IDLECT2_SLEEP_VAL
- OMAP1610_IDLECT3
- OMAP1610_IDLECT3_SLEEP_ORMASK
- OMAP1610_IDLECT3_VAL
- OMAP1610_IDLE_LOOP_REQUEST
- OMAP1610_MCBSP1_BASE
- OMAP1610_MCBSP2_BASE
- OMAP1610_MCBSP3_BASE
- OMAP1610_RESET_CONTROL
- OMAP16XX_ARM_IDLECT3
- OMAP16XX_BASE_BAUD
- OMAP16XX_CONF_VOLTAGE_VDDSHV6
- OMAP16XX_CONF_VOLTAGE_VDDSHV7
- OMAP16XX_CONF_VOLTAGE_VDDSHV8
- OMAP16XX_CONF_VOLTAGE_VDDSHV9
- OMAP16XX_DSPREG_BASE
- OMAP16XX_DSPREG_SIZE
- OMAP16XX_DSPREG_START
- OMAP16XX_DSP_BASE
- OMAP16XX_DSP_MMU_BASE
- OMAP16XX_DSP_SIZE
- OMAP16XX_DSP_START
- OMAP16XX_MAILBOX_BASE
- OMAP16XX_MCBSP_COUNT
- OMAP16XX_MCBSP_RES_SZ
- OMAP16XX_MMCSD2_SSW_MPU_CONF
- OMAP16XX_NR_MMC
- OMAP16XX_SEC_BASE
- OMAP16XX_SEC_DES
- OMAP16XX_SEC_RNG
- OMAP16XX_SEC_SHA1MD5
- OMAP16XX_SUBLVDS_CONF_VALID
- OMAP1710_ETHR_START
- OMAP1UART1
- OMAP1UART2
- OMAP1UART3
- OMAP1XXX_PINS_SZ
- OMAP1_32KSYNC_TIMER_BASE
- OMAP1_32K_TIMER_BASE
- OMAP1_32K_TIMER_CR
- OMAP1_32K_TIMER_TCR
- OMAP1_32K_TIMER_TVR
- OMAP1_CAMERA_BASE
- OMAP1_CAMERA_IOSIZE
- OMAP1_CAMERA_LCLK_RISING
- OMAP1_CAMERA_MIN_BUF_COUNT
- OMAP1_CAMERA_RST_HIGH
- OMAP1_CAMERA_RST_LOW
- OMAP1_CAM_DMA_CONTIG
- OMAP1_CAM_DMA_SG
- OMAP1_DMA_BASE
- OMAP1_DMA_SYNC_IRQ
- OMAP1_DMA_TOUT_IRQ
- OMAP1_DM_TIMER_COUNT
- OMAP1_DPLL1_SANE_VALUE
- OMAP1_I2C_BASE
- OMAP1_IO_ADDRESS
- OMAP1_IO_OFFSET
- OMAP1_IO_PHYS
- OMAP1_IO_SIZE
- OMAP1_IO_VIRT
- OMAP1_MMC1_BASE
- OMAP1_MMC2_BASE
- OMAP1_MMC_SIZE
- OMAP1_MPUIO_BASE
- OMAP1_MPUIO_VBASE
- OMAP1_OHCI_BASE
- OMAP1_OTG_BASE
- OMAP1_RNG_BASE
- OMAP1_SPI100K_MAX_FREQ
- OMAP1_SRAM_PA
- OMAP1_UART1_BASE
- OMAP1_UART2_BASE
- OMAP1_UART3_BASE
- OMAP1_UDC_BASE
- OMAP2420_32KSYNCT_BASE
- OMAP2420_AUTOSTATE_IVA_MASK
- OMAP2420_CLKOUT2_DIV_SHIFT
- OMAP2420_CLKOUT2_DIV_WIDTH
- OMAP2420_CLKOUT2_EN_SHIFT
- OMAP2420_CLKOUT2_SOURCE_MASK
- OMAP2420_CM_BASE
- OMAP2420_CM_REGADDR
- OMAP2420_CORE_IOPAD
- OMAP2420_DSP_BASE
- OMAP2420_DSP_IPI_BASE
- OMAP2420_DSP_MEM_BASE
- OMAP2420_DSP_MMU_BASE
- OMAP2420_EN_MMC_MASK
- OMAP2420_EN_MMC_SHIFT
- OMAP2420_EN_VLYNQ_MASK
- OMAP2420_EN_VLYNQ_SHIFT
- OMAP2420_GPMC_BASE
- OMAP2420_L4_CORE_FW_DSS_CORE_REGION
- OMAP2420_L4_CORE_FW_DSS_DISPC_REGION
- OMAP2420_L4_CORE_FW_DSS_RFBI_REGION
- OMAP2420_L4_CORE_FW_DSS_TA_REGION
- OMAP2420_L4_CORE_FW_DSS_VENC_REGION
- OMAP2420_MMC_SIZE
- OMAP2420_PRCM_BASE
- OMAP2420_PRCM_CLKCFG_CTRL
- OMAP2420_PRCM_CLKCFG_STATUS
- OMAP2420_PRCM_CLKEMUL_CTRL
- OMAP2420_PRCM_CLKOUT_CTRL
- OMAP2420_PRCM_CLKSRC_CTRL
- OMAP2420_PRCM_CLKSSETUP
- OMAP2420_PRCM_IRQENABLE_MPU
- OMAP2420_PRCM_IRQSTATUS_MPU
- OMAP2420_PRCM_POLCTRL
- OMAP2420_PRCM_REVISION
- OMAP2420_PRCM_SYSCONFIG
- OMAP2420_PRCM_VOLTCTRL
- OMAP2420_PRCM_VOLTSETUP
- OMAP2420_PRCM_VOLTST
- OMAP2420_PRM_BASE
- OMAP2420_PRM_REGADDR
- OMAP2420_REV_ES1_0
- OMAP2420_REV_ES2_0
- OMAP2420_SDRC_BASE
- OMAP2420_SMS_BASE
- OMAP2420_ST_I2C1_SHIFT
- OMAP2420_ST_I2C2_SHIFT
- OMAP2420_ST_MMC_MASK
- OMAP2420_ST_MMC_SHIFT
- OMAP2420_ST_VLYNQ_MASK
- OMAP2420_ST_VLYNQ_SHIFT
- OMAP242X_CLASS
- OMAP242X_CONTROL_DEVCONF
- OMAP242X_CONTROL_OCM_RAM_PERM
- OMAP242X_CTRL_BASE
- OMAP242X_CTRL_REGADDR
- OMAP242X_SDRC_REGADDR
- OMAP242X_SMS_REGADDR
- OMAP2430_32KSYNCT_BASE
- OMAP2430_AUTOSTATE_MDM_MASK
- OMAP2430_CM_BASE
- OMAP2430_CM_IDLEST3
- OMAP2430_CM_REGADDR
- OMAP2430_CORE_IOPAD
- OMAP2430_EN_GPIO5_MASK
- OMAP2430_EN_GPIO5_SHIFT
- OMAP2430_EN_MCSPI3_MASK
- OMAP2430_EN_MCSPI3_SHIFT
- OMAP2430_EN_MDM_INTC_MASK
- OMAP2430_EN_MDM_INTC_SHIFT
- OMAP2430_EN_MMCHS1_MASK
- OMAP2430_EN_MMCHS1_SHIFT
- OMAP2430_EN_MMCHS2_MASK
- OMAP2430_EN_MMCHS2_SHIFT
- OMAP2430_EN_USBHS_MASK
- OMAP2430_EN_USBHS_SHIFT
- OMAP2430_MDM_MOD
- OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT
- OMAP2430_PRCM_BASE
- OMAP2430_PRCM_CLKCFG_CTRL
- OMAP2430_PRCM_CLKCFG_STATUS
- OMAP2430_PRCM_CLKEMUL_CTRL
- OMAP2430_PRCM_CLKOUT_CTRL
- OMAP2430_PRCM_CLKSRC_CTRL
- OMAP2430_PRCM_CLKSSETUP
- OMAP2430_PRCM_IRQENABLE_MPU
- OMAP2430_PRCM_IRQSTATUS_MPU
- OMAP2430_PRCM_POLCTRL
- OMAP2430_PRCM_REVISION
- OMAP2430_PRCM_SYSCONFIG
- OMAP2430_PRCM_VOLTCTRL
- OMAP2430_PRCM_VOLTSETUP
- OMAP2430_PRCM_VOLTST
- OMAP2430_PRM_BASE
- OMAP2430_PRM_REGADDR
- OMAP2430_REV_ES1_0
- OMAP2430_ST_GPIO5_MASK
- OMAP2430_ST_GPIO5_SHIFT
- OMAP2430_ST_I2CHS1_SHIFT
- OMAP2430_ST_I2CHS2_SHIFT
- OMAP2430_ST_MCBSP3_SHIFT
- OMAP2430_ST_MCBSP4_SHIFT
- OMAP2430_ST_MCBSP5_SHIFT
- OMAP2430_ST_MCSPI3_MASK
- OMAP2430_ST_MCSPI3_SHIFT
- OMAP2430_ST_MDM_INTC_MASK
- OMAP2430_ST_MDM_INTC_SHIFT
- OMAP2430_ST_MDM_MASK
- OMAP2430_ST_MDM_SHIFT
- OMAP2430_ST_MMCHS1_MASK
- OMAP2430_ST_MMCHS1_SHIFT
- OMAP2430_ST_MMCHS2_MASK
- OMAP2430_ST_MMCHS2_SHIFT
- OMAP2430_ST_USBHS_MASK
- OMAP2430_ST_USBHS_SHIFT
- OMAP243X_CLASS
- OMAP243X_CONTROL_CSIRXFE
- OMAP243X_CONTROL_DEVCONF1
- OMAP243X_CONTROL_IVA2_BOOTADDR
- OMAP243X_CONTROL_IVA2_BOOTMOD
- OMAP243X_CONTROL_IVA2_GEMCFG
- OMAP243X_CONTROL_PBIAS_LITE
- OMAP243X_CTRL_BASE
- OMAP243X_CTRL_REGADDR
- OMAP243X_DSP_BASE
- OMAP243X_DSP_MEM_BASE
- OMAP243X_DSP_MMU_BASE
- OMAP243X_GPMC_BASE
- OMAP243X_GPMC_PHYS
- OMAP243X_GPMC_SIZE
- OMAP243X_GPMC_VIRT
- OMAP243X_HS_BASE
- OMAP243X_MMC1_ACTIVE_OVERWRITE
- OMAP243X_SCM_BASE
- OMAP243X_SDRC_BASE
- OMAP243X_SDRC_PHYS
- OMAP243X_SDRC_REGADDR
- OMAP243X_SDRC_SIZE
- OMAP243X_SDRC_VIRT
- OMAP243X_SMS_BASE
- OMAP243X_SMS_PHYS
- OMAP243X_SMS_REGADDR
- OMAP243X_SMS_SIZE
- OMAP243X_SMS_VIRT
- OMAP24XX_AUTOIDLE_MASK
- OMAP24XX_AUTOSTATE_DSP_MASK
- OMAP24XX_AUTOSTATE_DSS_MASK
- OMAP24XX_AUTOSTATE_GFX_MASK
- OMAP24XX_AUTOSTATE_L3_MASK
- OMAP24XX_AUTOSTATE_L4_MASK
- OMAP24XX_AUTOSTATE_MPU_MASK
- OMAP24XX_AUTO_54M_MASK
- OMAP24XX_AUTO_96M_MASK
- OMAP24XX_AUTO_DPLL_MASK
- OMAP24XX_AUTO_DPLL_SHIFT
- OMAP24XX_AUTO_EXTVOLT_MASK
- OMAP24XX_BASE_BAUD
- OMAP24XX_CAMERA_BASE
- OMAP24XX_CLKOUT_DIV_SHIFT
- OMAP24XX_CLKOUT_DIV_WIDTH
- OMAP24XX_CLKOUT_EN_SHIFT
- OMAP24XX_CLKOUT_SOURCE_MASK
- OMAP24XX_CLKSEL_DSS2_MASK
- OMAP24XX_CLKSTCTRL_DISABLE_AUTO
- OMAP24XX_CLKSTCTRL_ENABLE_AUTO
- OMAP24XX_CM_AUTOIDLE4
- OMAP24XX_CM_FCLKEN2
- OMAP24XX_CM_ICLKEN4
- OMAP24XX_CM_IDLEST4
- OMAP24XX_CM_IDLEST_VAL
- OMAP24XX_CONTROL_CUST_KEY_0
- OMAP24XX_CONTROL_CUST_KEY_1
- OMAP24XX_CONTROL_DEBOBS
- OMAP24XX_CONTROL_EMU_SUPPORT
- OMAP24XX_CONTROL_EXT_SEC_RAM_START_ADD
- OMAP24XX_CONTROL_EXT_SEC_RAM_STOP_ADD
- OMAP24XX_CONTROL_GENERAL_PURPOSE_STATUS
- OMAP24XX_CONTROL_OCM_PUB_RAM_ADD
- OMAP24XX_CONTROL_PSA_CMD
- OMAP24XX_CONTROL_PSA_CTRL
- OMAP24XX_CONTROL_PSA_VALUE
- OMAP24XX_CONTROL_RAND_KEY_0
- OMAP24XX_CONTROL_RAND_KEY_1
- OMAP24XX_CONTROL_RAND_KEY_2
- OMAP24XX_CONTROL_RAND_KEY_3
- OMAP24XX_CONTROL_SEC_EMU
- OMAP24XX_CONTROL_SEC_ERR_STATUS
- OMAP24XX_CONTROL_SEC_STATUS
- OMAP24XX_CONTROL_SEC_TAP
- OMAP24XX_CONTROL_SEC_TEST
- OMAP24XX_CONTROL_STATUS
- OMAP24XX_CONTROL_TEST_KEY_0
- OMAP24XX_CONTROL_TEST_KEY_1
- OMAP24XX_CONTROL_TEST_KEY_2
- OMAP24XX_CONTROL_TEST_KEY_3
- OMAP24XX_CONTROL_TEST_KEY_4
- OMAP24XX_CONTROL_TEST_KEY_5
- OMAP24XX_CONTROL_TEST_KEY_6
- OMAP24XX_CONTROL_TEST_KEY_7
- OMAP24XX_CONTROL_TEST_KEY_8
- OMAP24XX_CONTROL_TEST_KEY_9
- OMAP24XX_CORE_CLK_SRC_MASK
- OMAP24XX_DSP_MOD
- OMAP24XX_EMULATION_EN_SHIFT
- OMAP24XX_EN_54M_PLL_SHIFT
- OMAP24XX_EN_96M_PLL_SHIFT
- OMAP24XX_EN_CORE_SHIFT
- OMAP24XX_EN_DSS1_MASK
- OMAP24XX_EN_GPIOS_MASK
- OMAP24XX_EN_GPIOS_SHIFT
- OMAP24XX_EN_GPMC_MASK
- OMAP24XX_EN_GPMC_SHIFT
- OMAP24XX_EN_GPT10_MASK
- OMAP24XX_EN_GPT10_SHIFT
- OMAP24XX_EN_GPT11_MASK
- OMAP24XX_EN_GPT11_SHIFT
- OMAP24XX_EN_GPT12_MASK
- OMAP24XX_EN_GPT12_SHIFT
- OMAP24XX_EN_GPT1_MASK
- OMAP24XX_EN_GPT1_SHIFT
- OMAP24XX_EN_GPT2_MASK
- OMAP24XX_EN_GPT2_SHIFT
- OMAP24XX_EN_GPT3_MASK
- OMAP24XX_EN_GPT3_SHIFT
- OMAP24XX_EN_GPT4_MASK
- OMAP24XX_EN_GPT4_SHIFT
- OMAP24XX_EN_GPT5_MASK
- OMAP24XX_EN_GPT5_SHIFT
- OMAP24XX_EN_GPT6_MASK
- OMAP24XX_EN_GPT6_SHIFT
- OMAP24XX_EN_GPT7_MASK
- OMAP24XX_EN_GPT7_SHIFT
- OMAP24XX_EN_GPT8_MASK
- OMAP24XX_EN_GPT8_SHIFT
- OMAP24XX_EN_GPT9_MASK
- OMAP24XX_EN_GPT9_SHIFT
- OMAP24XX_EN_MCBSP1_MASK
- OMAP24XX_EN_MCBSP1_SHIFT
- OMAP24XX_EN_MCBSP2_MASK
- OMAP24XX_EN_MCBSP2_SHIFT
- OMAP24XX_EN_MCSPI1_MASK
- OMAP24XX_EN_MCSPI1_SHIFT
- OMAP24XX_EN_MCSPI2_MASK
- OMAP24XX_EN_MCSPI2_SHIFT
- OMAP24XX_EN_UART1_MASK
- OMAP24XX_EN_UART1_SHIFT
- OMAP24XX_EN_UART2_MASK
- OMAP24XX_EN_UART2_SHIFT
- OMAP24XX_EN_UART3_MASK
- OMAP24XX_EN_UART3_SHIFT
- OMAP24XX_EN_USB_MASK
- OMAP24XX_EN_USB_SHIFT
- OMAP24XX_EXTWMPU_RST_SHIFT
- OMAP24XX_FORCESTATE_MASK
- OMAP24XX_GPIO_CLEARDATAOUT
- OMAP24XX_GPIO_CLEARIRQENABLE1
- OMAP24XX_GPIO_CLEARWKUENA
- OMAP24XX_GPIO_CTRL
- OMAP24XX_GPIO_DATAIN
- OMAP24XX_GPIO_DATAOUT
- OMAP24XX_GPIO_DEBOUNCE_EN
- OMAP24XX_GPIO_DEBOUNCE_VAL
- OMAP24XX_GPIO_FALLINGDETECT
- OMAP24XX_GPIO_IRQENABLE1
- OMAP24XX_GPIO_IRQENABLE2
- OMAP24XX_GPIO_IRQSTATUS1
- OMAP24XX_GPIO_IRQSTATUS2
- OMAP24XX_GPIO_LEVELDETECT0
- OMAP24XX_GPIO_LEVELDETECT1
- OMAP24XX_GPIO_OE
- OMAP24XX_GPIO_REVISION
- OMAP24XX_GPIO_RISINGDETECT
- OMAP24XX_GPIO_SETDATAOUT
- OMAP24XX_GPIO_SETIRQENABLE1
- OMAP24XX_GPIO_SETWKUENA
- OMAP24XX_GPIO_WAKE_EN
- OMAP24XX_GR_MOD
- OMAP24XX_IC_BASE
- OMAP24XX_IVA_INTC_BASE
- OMAP24XX_MAILBOX_BASE
- OMAP24XX_MEMRETCTRL_MASK
- OMAP24XX_MPU_WD_RST_SHIFT
- OMAP24XX_NR_MMC
- OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT
- OMAP24XX_PM_WKEN2
- OMAP24XX_PM_WKST2
- OMAP24XX_PRCM_IRQENABLE_DSP
- OMAP24XX_PRCM_IRQENABLE_IVA
- OMAP24XX_PRCM_IRQSTATUS_DSP
- OMAP24XX_PRCM_IRQSTATUS_IVA
- OMAP24XX_PWRDM_POWER_OFF
- OMAP24XX_PWRDM_POWER_ON
- OMAP24XX_PWRDM_POWER_RET
- OMAP24XX_SECU_VIOL_RST_SHIFT
- OMAP24XX_SECU_WD_RST_SHIFT
- OMAP24XX_SEC_AES_BASE
- OMAP24XX_SEC_BASE
- OMAP24XX_SEC_DES_BASE
- OMAP24XX_SEC_PKA_BASE
- OMAP24XX_SEC_RNG_BASE
- OMAP24XX_SEC_SHA1MD5_BASE
- OMAP24XX_SETOFF_LEVEL_SHIFT
- OMAP24XX_SETRET_LEVEL_SHIFT
- OMAP24XX_ST_32KSYNC_MASK
- OMAP24XX_ST_32KSYNC_SHIFT
- OMAP24XX_ST_54M_APLL_SHIFT
- OMAP24XX_ST_96M_APLL_SHIFT
- OMAP24XX_ST_AES_SHIFT
- OMAP24XX_ST_GPIOS_MASK
- OMAP24XX_ST_GPIOS_SHIFT
- OMAP24XX_ST_GPT10_MASK
- OMAP24XX_ST_GPT10_SHIFT
- OMAP24XX_ST_GPT11_MASK
- OMAP24XX_ST_GPT11_SHIFT
- OMAP24XX_ST_GPT12_MASK
- OMAP24XX_ST_GPT12_SHIFT
- OMAP24XX_ST_GPT1_MASK
- OMAP24XX_ST_GPT1_SHIFT
- OMAP24XX_ST_GPT2_MASK
- OMAP24XX_ST_GPT2_SHIFT
- OMAP24XX_ST_GPT3_MASK
- OMAP24XX_ST_GPT3_SHIFT
- OMAP24XX_ST_GPT4_MASK
- OMAP24XX_ST_GPT4_SHIFT
- OMAP24XX_ST_GPT5_MASK
- OMAP24XX_ST_GPT5_SHIFT
- OMAP24XX_ST_GPT6_MASK
- OMAP24XX_ST_GPT6_SHIFT
- OMAP24XX_ST_GPT7_MASK
- OMAP24XX_ST_GPT7_SHIFT
- OMAP24XX_ST_GPT8_MASK
- OMAP24XX_ST_GPT8_SHIFT
- OMAP24XX_ST_GPT9_MASK
- OMAP24XX_ST_GPT9_SHIFT
- OMAP24XX_ST_HDQ_SHIFT
- OMAP24XX_ST_MAILBOXES_SHIFT
- OMAP24XX_ST_MCBSP1_MASK
- OMAP24XX_ST_MCBSP1_SHIFT
- OMAP24XX_ST_MCBSP2_MASK
- OMAP24XX_ST_MCBSP2_SHIFT
- OMAP24XX_ST_MCSPI1_MASK
- OMAP24XX_ST_MCSPI1_SHIFT
- OMAP24XX_ST_MCSPI2_MASK
- OMAP24XX_ST_MCSPI2_SHIFT
- OMAP24XX_ST_MPU_WDT_SHIFT
- OMAP24XX_ST_RNG_SHIFT
- OMAP24XX_ST_SHA_SHIFT
- OMAP24XX_ST_UART1_MASK
- OMAP24XX_ST_UART1_SHIFT
- OMAP24XX_ST_UART2_MASK
- OMAP24XX_ST_UART2_SHIFT
- OMAP24XX_ST_UART3_MASK
- OMAP24XX_ST_UART3_SHIFT
- OMAP24XX_ST_USB_MASK
- OMAP24XX_ST_USB_SHIFT
- OMAP24XX_USBSTANDBYCTRL
- OMAP24XX_VA_READPERM0
- OMAP24XX_VA_REQINFOPERM0
- OMAP24XX_VA_WRITEPERM0
- OMAP24XX_VOLT_LEVEL_SHIFT
- OMAP2XXX_APLL_AUTOIDLE_DISABLE
- OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP
- OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP
- OMAP2XXX_EN_DPLL_FRBYPASS
- OMAP2XXX_EN_DPLL_LOCKED
- OMAP2XXX_EN_DPLL_LPBYPASS
- OMAP2_32KSYNCNT_CR_OFF_HIGH
- OMAP2_32KSYNCNT_CR_OFF_LOW
- OMAP2_32KSYNCNT_REV_OFF
- OMAP2_32KSYNCNT_REV_SCHEME
- OMAP2_APLL_AUTOIDLE_DISABLE
- OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP
- OMAP2_ARCH_ID_H
- OMAP2_CM_CLKSTCTRL
- OMAP2_CONTROL_DEVCONF0
- OMAP2_CONTROL_GENERAL
- OMAP2_CONTROL_INTERFACE
- OMAP2_CONTROL_MSUSPENDMUX_0
- OMAP2_CONTROL_MSUSPENDMUX_1
- OMAP2_CONTROL_MSUSPENDMUX_2
- OMAP2_CONTROL_MSUSPENDMUX_3
- OMAP2_CONTROL_MSUSPENDMUX_4
- OMAP2_CONTROL_MSUSPENDMUX_5
- OMAP2_CONTROL_PADCONFS
- OMAP2_CONTROL_RPUB_KEY_H_0
- OMAP2_CONTROL_RPUB_KEY_H_1
- OMAP2_CONTROL_RPUB_KEY_H_2
- OMAP2_CONTROL_RPUB_KEY_H_3
- OMAP2_CONTROL_SEC_CTRL
- OMAP2_CONTROL_SYSCONFIG
- OMAP2_DEVICETYPE_MASK
- OMAP2_DEVICE_TYPE_BAD
- OMAP2_DEVICE_TYPE_EMU
- OMAP2_DEVICE_TYPE_GP
- OMAP2_DEVICE_TYPE_SEC
- OMAP2_DEVICE_TYPE_TEST
- OMAP2_DMA_CSR_CLEAR_MASK
- OMAP2_DMA_MISALIGNED_ERR_IRQ
- OMAP2_DMA_PKT_IRQ
- OMAP2_DMA_SECURE_ERR_IRQ
- OMAP2_DMA_SUPERVISOR_ERR_IRQ
- OMAP2_DMA_TRANS_ERR_IRQ
- OMAP2_EMU_IO_ADDRESS
- OMAP2_EMU_IO_OFFSET
- OMAP2_EN_APLL_LOCKED
- OMAP2_EN_APLL_STOPPED
- OMAP2_I2C_CON_OFFSET
- OMAP2_L3_CORE_FW_CONNID_DSS
- OMAP2_L3_IO_ADDRESS
- OMAP2_L3_IO_OFFSET
- OMAP2_L4_IO_ADDRESS
- OMAP2_L4_IO_OFFSET
- OMAP2_MAILBOX_IRQENABLE
- OMAP2_MAILBOX_IRQSTATUS
- OMAP2_MCBSP1_CLKR_MASK
- OMAP2_MCBSP1_CLKS_MASK
- OMAP2_MCBSP1_FSR_MASK
- OMAP2_MCBSP2_CLKS_MASK
- OMAP2_MCBSP3_CLKS_MASK
- OMAP2_MCBSP4_CLKS_MASK
- OMAP2_MCBSP5_CLKS_MASK
- OMAP2_MCSPI_CHCONF0
- OMAP2_MCSPI_CHCONF_CLKD_MASK
- OMAP2_MCSPI_CHCONF_CLKG
- OMAP2_MCSPI_CHCONF_DMAR
- OMAP2_MCSPI_CHCONF_DMAW
- OMAP2_MCSPI_CHCONF_DPE0
- OMAP2_MCSPI_CHCONF_DPE1
- OMAP2_MCSPI_CHCONF_EPOL
- OMAP2_MCSPI_CHCONF_FFER
- OMAP2_MCSPI_CHCONF_FFET
- OMAP2_MCSPI_CHCONF_FORCE
- OMAP2_MCSPI_CHCONF_IS
- OMAP2_MCSPI_CHCONF_PHA
- OMAP2_MCSPI_CHCONF_POL
- OMAP2_MCSPI_CHCONF_TRM_MASK
- OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
- OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
- OMAP2_MCSPI_CHCONF_TURBO
- OMAP2_MCSPI_CHCONF_WL_MASK
- OMAP2_MCSPI_CHCTRL0
- OMAP2_MCSPI_CHCTRL_EN
- OMAP2_MCSPI_CHCTRL_EXTCLK_MASK
- OMAP2_MCSPI_CHSTAT0
- OMAP2_MCSPI_CHSTAT_EOT
- OMAP2_MCSPI_CHSTAT_RXS
- OMAP2_MCSPI_CHSTAT_TXFFE
- OMAP2_MCSPI_CHSTAT_TXS
- OMAP2_MCSPI_IRQENABLE
- OMAP2_MCSPI_IRQSTATUS
- OMAP2_MCSPI_IRQSTATUS_EOW
- OMAP2_MCSPI_MAX_DIVIDER
- OMAP2_MCSPI_MAX_FIFODEPTH
- OMAP2_MCSPI_MAX_FIFOWCNT
- OMAP2_MCSPI_MAX_FREQ
- OMAP2_MCSPI_MODULCTRL
- OMAP2_MCSPI_MODULCTRL_MS
- OMAP2_MCSPI_MODULCTRL_SINGLE
- OMAP2_MCSPI_MODULCTRL_STEST
- OMAP2_MCSPI_REVISION
- OMAP2_MCSPI_RX0
- OMAP2_MCSPI_SYSSTATUS
- OMAP2_MCSPI_SYST
- OMAP2_MCSPI_TX0
- OMAP2_MCSPI_WAKEUPENABLE
- OMAP2_MCSPI_WAKEUPENABLE_WKEN
- OMAP2_MCSPI_XFERLEVEL
- OMAP2_MMC1_BASE
- OMAP2_MMCSDIO1ADPCLKISEL
- OMAP2_MMCSDIO2ADPCLKISEL
- OMAP2_OHCI_BASE
- OMAP2_OTG_BASE
- OMAP2_PBIASLITEPWRDNZ0
- OMAP2_PBIASLITEVMODE0
- OMAP2_PBIASSPEEDCTRL0
- OMAP2_PM_PWSTCTRL
- OMAP2_PM_PWSTST
- OMAP2_PRCM_CLKCFG_CTRL_OFFSET
- OMAP2_PRCM_CLKCFG_STATUS_OFFSET
- OMAP2_PRCM_CLKEMUL_CTRL_OFFSET
- OMAP2_PRCM_CLKOUT_CTRL_OFFSET
- OMAP2_PRCM_CLKSRC_CTRL_OFFSET
- OMAP2_PRCM_CLKSSETUP_OFFSET
- OMAP2_PRCM_IRQENABLE_MPU_OFFSET
- OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
- OMAP2_PRCM_POLCTRL_OFFSET
- OMAP2_PRCM_REVISION_OFFSET
- OMAP2_PRCM_SYSCONFIG_OFFSET
- OMAP2_PRCM_VOLTCTRL_OFFSET
- OMAP2_PRCM_VOLTSETUP_OFFSET
- OMAP2_PRCM_VOLTST_OFFSET
- OMAP2_RM_RSTCTRL
- OMAP2_RM_RSTST
- OMAP2_RM_RSTTIME
- OMAP2_RNG_OUTPUT_SIZE
- OMAP2_SOC_OMAP2420
- OMAP2_SOC_OMAP2430
- OMAP2_SRAM_PA
- OMAP2_SRAM_PUB_PA
- OMAP2_SYSBOOT_0_MASK
- OMAP2_SYSBOOT_1_MASK
- OMAP2_SYSBOOT_2_MASK
- OMAP2_SYSBOOT_3_MASK
- OMAP2_SYSBOOT_4_MASK
- OMAP2_SYSBOOT_5_MASK
- OMAP2_UART1_BASE
- OMAP2_UART2_BASE
- OMAP2_UART3_BASE
- OMAP2_UDC_BASE
- OMAP32_ID_0
- OMAP32_ID_1
- OMAP3430ES1_CLKTRCTRL_D2D_MASK
- OMAP3430ES1_CLKTRCTRL_GFX_MASK
- OMAP3430ES1_ST_FSHOSTUSB_MASK
- OMAP3430ES1_ST_FSHOSTUSB_SHIFT
- OMAP3430ES1_ST_HSOTGUSB_MASK
- OMAP3430ES1_ST_HSOTGUSB_SHIFT
- OMAP3430ES2_CLKTRCTRL_SGX_MASK
- OMAP3430ES2_CLKTRCTRL_USBHOST_MASK
- OMAP3430ES2_CM_AUTOIDLE2_PLL
- OMAP3430ES2_CM_CLKEN2
- OMAP3430ES2_CM_CLKSEL4
- OMAP3430ES2_CM_CLKSEL5
- OMAP3430ES2_CM_FCLKEN3
- OMAP3430ES2_EN_USBHOST2_SHIFT
- OMAP3430ES2_PM_IVAGRPSEL3
- OMAP3430ES2_PM_MPUGRPSEL3
- OMAP3430ES2_PM_WKEN3
- OMAP3430ES2_PM_WKST3
- OMAP3430ES2_SAVEANDRESTORE_SHIFT
- OMAP3430ES2_SGX_MOD
- OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT
- OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT
- OMAP3430ES2_ST_DSS_IDLE_SHIFT
- OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK
- OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT
- OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK
- OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
- OMAP3430ES2_ST_SSI_IDLE_SHIFT
- OMAP3430ES2_ST_USBHOST_IDLE_SHIFT
- OMAP3430ES2_ST_USBTLL_SHIFT
- OMAP3430ES2_USBHOST_MOD
- OMAP3430_32KSYNCT_BASE
- OMAP3430_AUTOIDLE_MASK
- OMAP3430_AUTO_PERIPH_DPLL_MASK
- OMAP3430_CAM_MOD
- OMAP3430_CCR_MOD
- OMAP3430_CLKACTIVITY_IVA2_MASK
- OMAP3430_CLKOUT_EN_SHIFT
- OMAP3430_CLKTRCTRL_CAM_MASK
- OMAP3430_CLKTRCTRL_DSS_MASK
- OMAP3430_CLKTRCTRL_EMU_MASK
- OMAP3430_CLKTRCTRL_IVA2_MASK
- OMAP3430_CLKTRCTRL_L3_MASK
- OMAP3430_CLKTRCTRL_L4_MASK
- OMAP3430_CLKTRCTRL_MPU_MASK
- OMAP3430_CLKTRCTRL_NEON_MASK
- OMAP3430_CLKTRCTRL_PER_MASK
- OMAP3430_CMDRA0_MASK
- OMAP3430_CMDRA1_MASK
- OMAP3430_CM_AUTOIDLE_PLL
- OMAP3430_CM_BASE
- OMAP3430_CM_CLKEN_PLL
- OMAP3430_CM_CLKOUT_CTRL
- OMAP3430_CM_CLKSEL1
- OMAP3430_CM_CLKSEL1_PLL
- OMAP3430_CM_CLKSEL2_EMU
- OMAP3430_CM_CLKSEL2_PLL
- OMAP3430_CM_CLKSEL3
- OMAP3430_CM_CLKSEL3_EMU
- OMAP3430_CM_CLKSTST
- OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK
- OMAP3430_CM_IDLEST_PLL
- OMAP3430_CM_POLCTRL
- OMAP3430_CM_SLEEPDEP
- OMAP3430_CM_SYSCONFIG
- OMAP3430_CORE2_IOPAD
- OMAP3430_CORE_DPLL_RECAL_EN_SHIFT
- OMAP3430_CORE_DPLL_ST_SHIFT
- OMAP3430_DATA_SHIFT
- OMAP3430_DPLL_FINT_BAND1_MAX
- OMAP3430_DPLL_FINT_BAND1_MIN
- OMAP3430_DPLL_FINT_BAND2_MAX
- OMAP3430_DPLL_FINT_BAND2_MIN
- OMAP3430_DSS_MOD
- OMAP3430_EMU_MOD
- OMAP3430_EN_CORE_MASK
- OMAP3430_EN_CORE_SHIFT
- OMAP3430_EN_D2D_MASK
- OMAP3430_EN_D2D_SHIFT
- OMAP3430_EN_FSHOSTUSB_MASK
- OMAP3430_EN_FSHOSTUSB_SHIFT
- OMAP3430_EN_GPIO1_MASK
- OMAP3430_EN_GPIO1_SHIFT
- OMAP3430_EN_GPIO2_MASK
- OMAP3430_EN_GPIO2_SHIFT
- OMAP3430_EN_GPIO3_MASK
- OMAP3430_EN_GPIO3_SHIFT
- OMAP3430_EN_GPIO4_MASK
- OMAP3430_EN_GPIO4_SHIFT
- OMAP3430_EN_GPIO5_MASK
- OMAP3430_EN_GPIO5_SHIFT
- OMAP3430_EN_GPIO6_MASK
- OMAP3430_EN_GPIO6_SHIFT
- OMAP3430_EN_GPT10_MASK
- OMAP3430_EN_GPT10_SHIFT
- OMAP3430_EN_GPT11_MASK
- OMAP3430_EN_GPT11_SHIFT
- OMAP3430_EN_GPT12_MASK
- OMAP3430_EN_GPT12_SHIFT
- OMAP3430_EN_GPT1_MASK
- OMAP3430_EN_GPT1_SHIFT
- OMAP3430_EN_GPT2_MASK
- OMAP3430_EN_GPT2_SHIFT
- OMAP3430_EN_GPT3_MASK
- OMAP3430_EN_GPT3_SHIFT
- OMAP3430_EN_GPT4_MASK
- OMAP3430_EN_GPT4_SHIFT
- OMAP3430_EN_GPT5_MASK
- OMAP3430_EN_GPT5_SHIFT
- OMAP3430_EN_GPT6_MASK
- OMAP3430_EN_GPT6_SHIFT
- OMAP3430_EN_GPT7_MASK
- OMAP3430_EN_GPT7_SHIFT
- OMAP3430_EN_GPT8_MASK
- OMAP3430_EN_GPT8_SHIFT
- OMAP3430_EN_GPT9_MASK
- OMAP3430_EN_GPT9_SHIFT
- OMAP3430_EN_HSOTGUSB_MASK
- OMAP3430_EN_HSOTGUSB_SHIFT
- OMAP3430_EN_I2C1_MASK
- OMAP3430_EN_I2C1_SHIFT
- OMAP3430_EN_I2C2_MASK
- OMAP3430_EN_I2C2_SHIFT
- OMAP3430_EN_I2C3_MASK
- OMAP3430_EN_I2C3_SHIFT
- OMAP3430_EN_IO_CHAIN_MASK
- OMAP3430_EN_IO_MASK
- OMAP3430_EN_MCBSP1_MASK
- OMAP3430_EN_MCBSP1_SHIFT
- OMAP3430_EN_MCBSP2_MASK
- OMAP3430_EN_MCBSP2_SHIFT
- OMAP3430_EN_MCBSP3_MASK
- OMAP3430_EN_MCBSP3_SHIFT
- OMAP3430_EN_MCBSP4_MASK
- OMAP3430_EN_MCBSP4_SHIFT
- OMAP3430_EN_MCBSP5_MASK
- OMAP3430_EN_MCBSP5_SHIFT
- OMAP3430_EN_MCSPI1_MASK
- OMAP3430_EN_MCSPI1_SHIFT
- OMAP3430_EN_MCSPI2_MASK
- OMAP3430_EN_MCSPI2_SHIFT
- OMAP3430_EN_MCSPI3_MASK
- OMAP3430_EN_MCSPI3_SHIFT
- OMAP3430_EN_MCSPI4_MASK
- OMAP3430_EN_MCSPI4_SHIFT
- OMAP3430_EN_MMC1_MASK
- OMAP3430_EN_MMC1_SHIFT
- OMAP3430_EN_MMC2_MASK
- OMAP3430_EN_MMC2_SHIFT
- OMAP3430_EN_MMC3_MASK
- OMAP3430_EN_MMC3_SHIFT
- OMAP3430_EN_MPU_MASK
- OMAP3430_EN_MPU_SHIFT
- OMAP3430_EN_PER_SHIFT
- OMAP3430_EN_SR1_MASK
- OMAP3430_EN_SR1_SHIFT
- OMAP3430_EN_SR2_MASK
- OMAP3430_EN_SR2_SHIFT
- OMAP3430_EN_UART1_MASK
- OMAP3430_EN_UART1_SHIFT
- OMAP3430_EN_UART2_MASK
- OMAP3430_EN_UART2_SHIFT
- OMAP3430_EN_UART3_MASK
- OMAP3430_EN_UART3_SHIFT
- OMAP3430_ERRORGAIN_MASK
- OMAP3430_ERROROFFSET_MASK
- OMAP3430_EXTERNAL_WARM_RST_SHIFT
- OMAP3430_FORCEUPDATE_MASK
- OMAP3430_GLOBAL_COLD_RST_MASK
- OMAP3430_GLOBAL_COLD_RST_SHIFT
- OMAP3430_GLOBAL_SW_RST_SHIFT
- OMAP3430_GRPSEL_GPIO1_MASK
- OMAP3430_GRPSEL_GPIO2_MASK
- OMAP3430_GRPSEL_GPIO3_MASK
- OMAP3430_GRPSEL_GPIO4_MASK
- OMAP3430_GRPSEL_GPIO5_MASK
- OMAP3430_GRPSEL_GPIO6_MASK
- OMAP3430_GRPSEL_GPT12_MASK
- OMAP3430_GRPSEL_GPT1_MASK
- OMAP3430_GRPSEL_GPT5_MASK
- OMAP3430_GRPSEL_GPT6_MASK
- OMAP3430_GRPSEL_GPT7_MASK
- OMAP3430_GRPSEL_GPT8_MASK
- OMAP3430_GRPSEL_MCBSP1_MASK
- OMAP3430_GRPSEL_MCBSP2_MASK
- OMAP3430_GRPSEL_MCBSP3_MASK
- OMAP3430_GRPSEL_MCBSP4_MASK
- OMAP3430_GRPSEL_MCBSP5_MASK
- OMAP3430_GRPSEL_UART3_MASK
- OMAP3430_GR_MOD
- OMAP3430_HSEN_MASK
- OMAP3430_ICECRUSHER_RST_SHIFT
- OMAP3430_ICEPICK_RST_SHIFT
- OMAP3430_INITVDD_MASK
- OMAP3430_INITVOLTAGE_MASK
- OMAP3430_ISP_BASE
- OMAP3430_ISP_BASE2
- OMAP3430_ISP_MMU_BASE
- OMAP3430_IVA2_MOD
- OMAP3430_L1FLATMEMONSTATE_MASK
- OMAP3430_L1FLATMEMRETSTATE_MASK
- OMAP3430_L1FLATMEMSTATEST_MASK
- OMAP3430_L2FLATMEMONSTATE_MASK
- OMAP3430_L2FLATMEMRETSTATE_MASK
- OMAP3430_L2FLATMEMSTATEST_MASK
- OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK
- OMAP3430_LASTLOGICSTATEENTERED_MASK
- OMAP3430_LASTMEM1STATEENTERED_MASK
- OMAP3430_LASTMEM2STATEENTERED_MASK
- OMAP3430_LASTPOWERSTATEENTERED_MASK
- OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK
- OMAP3430_LOGICSTATEST_MASK
- OMAP3430_MCODE_MASK
- OMAP3430_MPU_DPLL_RECAL_EN_SHIFT
- OMAP3430_MPU_DPLL_ST_SHIFT
- OMAP3430_MPU_WD_RST_SHIFT
- OMAP3430_NEON_MOD
- OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT
- OMAP3430_PERIPH_DPLL_ST_SHIFT
- OMAP3430_PER_MOD
- OMAP3430_PM_IVAGRPSEL
- OMAP3430_PM_IVAGRPSEL1
- OMAP3430_PM_MPUGRPSEL
- OMAP3430_PM_MPUGRPSEL1
- OMAP3430_PM_PREPWSTST
- OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT
- OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT
- OMAP3430_PM_WKEN_DSS_EN_DSS_MASK
- OMAP3430_PRM_BASE
- OMAP3430_PRM_CLKOUT_CTRL
- OMAP3430_PRM_CLKSEL
- OMAP3430_PRM_CLKSETUP
- OMAP3430_PRM_CLKSRC_CTRL
- OMAP3430_PRM_IRQENABLE_IVA2
- OMAP3430_PRM_IRQENABLE_MPU
- OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT
- OMAP3430_PRM_IRQSTATUS_IVA2
- OMAP3430_PRM_IRQSTATUS_MPU
- OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT
- OMAP3430_PRM_POLCTRL
- OMAP3430_PRM_POLCTRL_CLKOUT_POL
- OMAP3430_PRM_POLCTRL_CLKREQ_POL
- OMAP3430_PRM_POLCTRL_EXTVOL_POL
- OMAP3430_PRM_POLCTRL_OFFMODE_POL
- OMAP3430_PRM_REVISION
- OMAP3430_PRM_RSTCTRL
- OMAP3430_PRM_RSTST
- OMAP3430_PRM_RSTTIME
- OMAP3430_PRM_SRAM_PCHARGE
- OMAP3430_PRM_SYSCONFIG
- OMAP3430_PRM_VC_BYPASS_VAL
- OMAP3430_PRM_VC_CH_CONF
- OMAP3430_PRM_VC_CMD_VAL_0
- OMAP3430_PRM_VC_CMD_VAL_1
- OMAP3430_PRM_VC_I2C_CFG
- OMAP3430_PRM_VC_SMPS_CMD_RA
- OMAP3430_PRM_VC_SMPS_SA
- OMAP3430_PRM_VC_SMPS_SA_SA0_MASK
- OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT
- OMAP3430_PRM_VC_SMPS_SA_SA1_MASK
- OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT
- OMAP3430_PRM_VC_SMPS_VOL_RA
- OMAP3430_PRM_VOLTCTRL
- OMAP3430_PRM_VOLTCTRL_AUTO_OFF
- OMAP3430_PRM_VOLTCTRL_AUTO_RET
- OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP
- OMAP3430_PRM_VOLTCTRL_SEL_OFF
- OMAP3430_PRM_VOLTCTRL_SEL_VMODE
- OMAP3430_PRM_VOLTOFFSET
- OMAP3430_PRM_VOLTSETUP1
- OMAP3430_PRM_VOLTSETUP2
- OMAP3430_PRM_VP1_CONFIG
- OMAP3430_PRM_VP1_STATUS
- OMAP3430_PRM_VP1_VLIMITTO
- OMAP3430_PRM_VP1_VOLTAGE
- OMAP3430_PRM_VP1_VSTEPMAX
- OMAP3430_PRM_VP1_VSTEPMIN
- OMAP3430_PRM_VP2_CONFIG
- OMAP3430_PRM_VP2_STATUS
- OMAP3430_PRM_VP2_VLIMITTO
- OMAP3430_PRM_VP2_VOLTAGE
- OMAP3430_PRM_VP2_VSTEPMAX
- OMAP3430_PRM_VP2_VSTEPMIN
- OMAP3430_REGADDR_SHIFT
- OMAP3430_REV_ES1_0
- OMAP3430_REV_ES2_0
- OMAP3430_REV_ES2_1
- OMAP3430_REV_ES3_0
- OMAP3430_REV_ES3_1
- OMAP3430_REV_ES3_1_2
- OMAP3430_REV_MASK
- OMAP3430_REV_SHIFT
- OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK
- OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK
- OMAP3430_RST1_IVA2_MASK
- OMAP3430_RST2_IVA2_MASK
- OMAP3430_RST3_IVA2_MASK
- OMAP3430_SECURE_WD_RST_SHIFT
- OMAP3430_SECURITY_VIOL_RST_SHIFT
- OMAP3430_SETUP_TIME1_MASK
- OMAP3430_SETUP_TIME2_MASK
- OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
- OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
- OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
- OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
- OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
- OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
- OMAP3430_SLAVEADDR_SHIFT
- OMAP3430_SMPSWAITTIMEMAX_SHIFT
- OMAP3430_SMPSWAITTIMEMIN_SHIFT
- OMAP3430_SR1_SENNAVGWEIGHT
- OMAP3430_SR1_SENPAVGWEIGHT
- OMAP3430_SR2_SENNAVGWEIGHT
- OMAP3430_SR2_SENPAVGWEIGHT
- OMAP3430_SREN_MASK
- OMAP3430_SR_ACCUMDATA
- OMAP3430_SR_ERRMAXLIMIT
- OMAP3430_SR_ERRWEIGHT
- OMAP3430_ST_32KSYNC_MASK
- OMAP3430_ST_32KSYNC_SHIFT
- OMAP3430_ST_AES2_SHIFT
- OMAP3430_ST_D2D_MASK
- OMAP3430_ST_D2D_SHIFT
- OMAP3430_ST_GPIO1_MASK
- OMAP3430_ST_GPIO1_SHIFT
- OMAP3430_ST_GPIO2_MASK
- OMAP3430_ST_GPIO2_SHIFT
- OMAP3430_ST_GPIO3_MASK
- OMAP3430_ST_GPIO3_SHIFT
- OMAP3430_ST_GPIO4_MASK
- OMAP3430_ST_GPIO4_SHIFT
- OMAP3430_ST_GPIO5_MASK
- OMAP3430_ST_GPIO5_SHIFT
- OMAP3430_ST_GPIO6_MASK
- OMAP3430_ST_GPIO6_SHIFT
- OMAP3430_ST_GPT10_MASK
- OMAP3430_ST_GPT10_SHIFT
- OMAP3430_ST_GPT11_MASK
- OMAP3430_ST_GPT11_SHIFT
- OMAP3430_ST_GPT12_MASK
- OMAP3430_ST_GPT12_SHIFT
- OMAP3430_ST_GPT1_MASK
- OMAP3430_ST_GPT1_SHIFT
- OMAP3430_ST_GPT2_MASK
- OMAP3430_ST_GPT2_SHIFT
- OMAP3430_ST_GPT3_MASK
- OMAP3430_ST_GPT3_SHIFT
- OMAP3430_ST_GPT4_MASK
- OMAP3430_ST_GPT4_SHIFT
- OMAP3430_ST_GPT5_MASK
- OMAP3430_ST_GPT5_SHIFT
- OMAP3430_ST_GPT6_MASK
- OMAP3430_ST_GPT6_SHIFT
- OMAP3430_ST_GPT7_MASK
- OMAP3430_ST_GPT7_SHIFT
- OMAP3430_ST_GPT8_MASK
- OMAP3430_ST_GPT8_SHIFT
- OMAP3430_ST_GPT9_MASK
- OMAP3430_ST_GPT9_SHIFT
- OMAP3430_ST_HDQ_SHIFT
- OMAP3430_ST_I2C1_MASK
- OMAP3430_ST_I2C1_SHIFT
- OMAP3430_ST_I2C2_MASK
- OMAP3430_ST_I2C2_SHIFT
- OMAP3430_ST_I2C3_MASK
- OMAP3430_ST_I2C3_SHIFT
- OMAP3430_ST_IO_CHAIN_MASK
- OMAP3430_ST_IO_MASK
- OMAP3430_ST_IVA2_SHIFT
- OMAP3430_ST_MAILBOXES_SHIFT
- OMAP3430_ST_MCBSP1_MASK
- OMAP3430_ST_MCBSP1_SHIFT
- OMAP3430_ST_MCBSP2_SHIFT
- OMAP3430_ST_MCBSP3_SHIFT
- OMAP3430_ST_MCBSP4_SHIFT
- OMAP3430_ST_MCBSP5_MASK
- OMAP3430_ST_MCBSP5_SHIFT
- OMAP3430_ST_MCSPI1_MASK
- OMAP3430_ST_MCSPI1_SHIFT
- OMAP3430_ST_MCSPI2_MASK
- OMAP3430_ST_MCSPI2_SHIFT
- OMAP3430_ST_MCSPI3_MASK
- OMAP3430_ST_MCSPI3_SHIFT
- OMAP3430_ST_MCSPI4_MASK
- OMAP3430_ST_MCSPI4_SHIFT
- OMAP3430_ST_MMC1_MASK
- OMAP3430_ST_MMC1_SHIFT
- OMAP3430_ST_MMC2_MASK
- OMAP3430_ST_MMC2_SHIFT
- OMAP3430_ST_MMC3_MASK
- OMAP3430_ST_MMC3_SHIFT
- OMAP3430_ST_SAD2D_SHIFT
- OMAP3430_ST_SDMA_SHIFT
- OMAP3430_ST_SHA12_SHIFT
- OMAP3430_ST_SR1_MASK
- OMAP3430_ST_SR1_SHIFT
- OMAP3430_ST_SR2_MASK
- OMAP3430_ST_SR2_SHIFT
- OMAP3430_ST_UART1_MASK
- OMAP3430_ST_UART1_SHIFT
- OMAP3430_ST_UART2_MASK
- OMAP3430_ST_UART2_SHIFT
- OMAP3430_ST_UART3_MASK
- OMAP3430_ST_UART3_SHIFT
- OMAP3430_ST_WDT2_SHIFT
- OMAP3430_SYS_CLKIN_SEL_SHIFT
- OMAP3430_SYS_CLKIN_SEL_WIDTH
- OMAP3430_TIMEOUTEN_MASK
- OMAP3430_TIMEOUT_SHIFT
- OMAP3430_VALID_MASK
- OMAP3430_VC_CMD_OFF_SHIFT
- OMAP3430_VC_CMD_ONLP_SHIFT
- OMAP3430_VC_CMD_ON_MASK
- OMAP3430_VC_CMD_ON_SHIFT
- OMAP3430_VC_CMD_RET_SHIFT
- OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT
- OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT
- OMAP3430_VDDMAX_SHIFT
- OMAP3430_VDDMIN_SHIFT
- OMAP3430_VDD_CORE_OPP1_UV
- OMAP3430_VDD_CORE_OPP2_UV
- OMAP3430_VDD_CORE_OPP3_UV
- OMAP3430_VDD_MPU_OPP1_UV
- OMAP3430_VDD_MPU_OPP2_UV
- OMAP3430_VDD_MPU_OPP3_UV
- OMAP3430_VDD_MPU_OPP4_UV
- OMAP3430_VDD_MPU_OPP5_UV
- OMAP3430_VOLRA0_MASK
- OMAP3430_VOLRA1_MASK
- OMAP3430_VP1_TRANXDONE_ST_MASK
- OMAP3430_VP1_VLIMITTO_VDDMAX
- OMAP3430_VP1_VLIMITTO_VDDMIN
- OMAP3430_VP2_TRANXDONE_ST_MASK
- OMAP3430_VP2_VLIMITTO_VDDMAX
- OMAP3430_VP2_VLIMITTO_VDDMIN
- OMAP3430_VPENABLE_MASK
- OMAP3430_VPVOLTAGE_MASK
- OMAP3430_VSTEPMAX_SHIFT
- OMAP3430_VSTEPMIN_SHIFT
- OMAP343X_CLASS
- OMAP343X_CONTROL_CORE_DPLL_SPREADING
- OMAP343X_CONTROL_CSI
- OMAP343X_CONTROL_CSIRXFE
- OMAP343X_CONTROL_CSIRXFE_CSIB_INV
- OMAP343X_CONTROL_CSIRXFE_PWRDNZ
- OMAP343X_CONTROL_CSIRXFE_RESENABLE
- OMAP343X_CONTROL_CSIRXFE_RESET
- OMAP343X_CONTROL_CSIRXFE_SELFORM
- OMAP343X_CONTROL_DEBOBS
- OMAP343X_CONTROL_DEVCONF1
- OMAP343X_CONTROL_DSS_DPLL_SPREADING
- OMAP343X_CONTROL_FUSE_OPP1_VDD1
- OMAP343X_CONTROL_FUSE_OPP1_VDD2
- OMAP343X_CONTROL_FUSE_OPP2_VDD1
- OMAP343X_CONTROL_FUSE_OPP2_VDD2
- OMAP343X_CONTROL_FUSE_OPP3_VDD1
- OMAP343X_CONTROL_FUSE_OPP3_VDD2
- OMAP343X_CONTROL_FUSE_OPP4_VDD1
- OMAP343X_CONTROL_FUSE_OPP5_VDD1
- OMAP343X_CONTROL_FUSE_SR
- OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS
- OMAP343X_CONTROL_GENERAL_WKUP
- OMAP343X_CONTROL_IVA2_BOOTADDR
- OMAP343X_CONTROL_IVA2_BOOTMOD
- OMAP343X_CONTROL_MEM_DFTRW0
- OMAP343X_CONTROL_MEM_DFTRW1
- OMAP343X_CONTROL_MEM_WKUP
- OMAP343X_CONTROL_PADCONFS_WKUP
- OMAP343X_CONTROL_PADCONF_OFF
- OMAP343X_CONTROL_PADCONF_SYSNIRQ
- OMAP343X_CONTROL_PBIAS_LITE
- OMAP343X_CONTROL_PER_DPLL_SPREADING
- OMAP343X_CONTROL_PROG_IO0
- OMAP343X_CONTROL_PROG_IO1
- OMAP343X_CONTROL_RAND_KEY_0
- OMAP343X_CONTROL_RAND_KEY_1
- OMAP343X_CONTROL_RAND_KEY_2
- OMAP343X_CONTROL_RAND_KEY_3
- OMAP343X_CONTROL_RPUB_KEY_H_4
- OMAP343X_CONTROL_SEC_ERR_STATUS
- OMAP343X_CONTROL_SEC_ERR_STATUS_DEBUG
- OMAP343X_CONTROL_SEC_STATUS
- OMAP343X_CONTROL_SRAMLDO4
- OMAP343X_CONTROL_SRAMLDO5
- OMAP343X_CONTROL_STATUS
- OMAP343X_CONTROL_TEMP_SENSOR
- OMAP343X_CONTROL_TEST_KEY_0
- OMAP343X_CONTROL_TEST_KEY_1
- OMAP343X_CONTROL_TEST_KEY_10
- OMAP343X_CONTROL_TEST_KEY_11
- OMAP343X_CONTROL_TEST_KEY_12
- OMAP343X_CONTROL_TEST_KEY_13
- OMAP343X_CONTROL_TEST_KEY_2
- OMAP343X_CONTROL_TEST_KEY_3
- OMAP343X_CONTROL_TEST_KEY_4
- OMAP343X_CONTROL_TEST_KEY_5
- OMAP343X_CONTROL_TEST_KEY_6
- OMAP343X_CONTROL_TEST_KEY_7
- OMAP343X_CONTROL_TEST_KEY_8
- OMAP343X_CONTROL_TEST_KEY_9
- OMAP343X_CONTROL_USBHOST_DPLL_SPREADING
- OMAP343X_CONTROL_WKUP_DEBOBS0
- OMAP343X_CONTROL_WKUP_DEBOBS1
- OMAP343X_CONTROL_WKUP_DEBOBS2
- OMAP343X_CONTROL_WKUP_DEBOBS3
- OMAP343X_CONTROL_WKUP_DEBOBS4
- OMAP343X_CONTROL_WKUP_DEBOBSMUX
- OMAP343X_CTRL_BASE
- OMAP343X_CTRL_REGADDR
- OMAP343X_PADCONF_ETK
- OMAP343X_PADCONF_ETK_CLK
- OMAP343X_PADCONF_ETK_CTL
- OMAP343X_PADCONF_ETK_D0
- OMAP343X_PADCONF_ETK_D1
- OMAP343X_PADCONF_ETK_D10
- OMAP343X_PADCONF_ETK_D11
- OMAP343X_PADCONF_ETK_D12
- OMAP343X_PADCONF_ETK_D13
- OMAP343X_PADCONF_ETK_D14
- OMAP343X_PADCONF_ETK_D15
- OMAP343X_PADCONF_ETK_D2
- OMAP343X_PADCONF_ETK_D3
- OMAP343X_PADCONF_ETK_D4
- OMAP343X_PADCONF_ETK_D5
- OMAP343X_PADCONF_ETK_D6
- OMAP343X_PADCONF_ETK_D7
- OMAP343X_PADCONF_ETK_D8
- OMAP343X_PADCONF_ETK_D9
- OMAP343X_PBIASLITEPWRDNZ1
- OMAP343X_PBIASLITESUPPLY_HIGH0
- OMAP343X_PBIASLITESUPPLY_HIGH1
- OMAP343X_PBIASLITEVMODE1
- OMAP343X_PBIASLITEVMODEERROR0
- OMAP343X_PBIASLITEVMODEERROR1
- OMAP343X_PBIASSPEEDCTRL1
- OMAP343X_SCM_BASE
- OMAP343X_SCRATCHPAD
- OMAP343X_SCRATCHPAD_REGADDR
- OMAP343X_SCRATCHPAD_ROM
- OMAP343X_SCRATCHPAD_ROM_OFFSET
- OMAP343X_SDRC_BASE
- OMAP343X_SDRC_PHYS
- OMAP343X_SDRC_SIZE
- OMAP343X_SDRC_VIRT
- OMAP343X_SMS_BASE
- OMAP343X_SMS_PHYS
- OMAP343X_SMS_REGADDR
- OMAP343X_SMS_SIZE
- OMAP343X_SMS_VIRT
- OMAP34XX_CLKSTCTRL_DISABLE_AUTO
- OMAP34XX_CLKSTCTRL_ENABLE_AUTO
- OMAP34XX_CLKSTCTRL_FORCE_SLEEP
- OMAP34XX_CLKSTCTRL_FORCE_WAKEUP
- OMAP34XX_CM_IDLEST_VAL
- OMAP34XX_CM_REGADDR
- OMAP34XX_CONTROL_WKUP_CTRL
- OMAP34XX_EHCI_BASE
- OMAP34XX_GPMC_BASE
- OMAP34XX_GPMC_PHYS
- OMAP34XX_GPMC_SIZE
- OMAP34XX_GPMC_VIRT
- OMAP34XX_HSUSB_OTG_BASE
- OMAP34XX_IC_BASE
- OMAP34XX_MAILBOX_BASE
- OMAP34XX_NR_GPIOS
- OMAP34XX_OHCI_BASE
- OMAP34XX_PRM_REGADDR
- OMAP34XX_SDRC_REGADDR
- OMAP34XX_SEC_AES_BASE
- OMAP34XX_SEC_BASE
- OMAP34XX_SEC_SHA1MD5_BASE
- OMAP34XX_SR1_BASE
- OMAP34XX_SR2_BASE
- OMAP34XX_UHH_CONFIG_BASE
- OMAP34XX_USBTLL_BASE
- OMAP34XX_VA_ADDR_MATCH2
- OMAP34XX_VA_READPERM0
- OMAP34XX_VA_REQINFOPERM0
- OMAP34XX_VA_SMS_RG_ATT0
- OMAP34XX_VA_WRITEPERM0
- OMAP34xx_IRQ_L3_APP
- OMAP3630_CONTROL_CAMERA_PHY_CTRL
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_GPI
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT
- OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2
- OMAP3630_CONTROL_FUSE_OPP100_VDD1
- OMAP3630_CONTROL_FUSE_OPP100_VDD2
- OMAP3630_CONTROL_FUSE_OPP120_VDD1
- OMAP3630_CONTROL_FUSE_OPP1G_VDD1
- OMAP3630_CONTROL_FUSE_OPP50_VDD1
- OMAP3630_CONTROL_FUSE_OPP50_VDD2
- OMAP3630_CORE2_IOPAD
- OMAP3630_EN_UART4_MASK
- OMAP3630_EN_UART4_SHIFT
- OMAP3630_GRPSEL_UART4_MASK
- OMAP3630_PRG_SDMMC1_SPEEDCTRL
- OMAP3630_REV_ES1_0
- OMAP3630_REV_ES1_1
- OMAP3630_REV_ES1_2
- OMAP3630_ST_UART4_MASK
- OMAP3630_ST_UART4_SHIFT
- OMAP3630_VDD_CORE_OPP100_UV
- OMAP3630_VDD_CORE_OPP50_UV
- OMAP3630_VDD_MPU_OPP100_UV
- OMAP3630_VDD_MPU_OPP120_UV
- OMAP3630_VDD_MPU_OPP1G_UV
- OMAP3630_VDD_MPU_OPP50_UV
- OMAP3630_VP1_VLIMITTO_VDDMAX
- OMAP3630_VP1_VLIMITTO_VDDMIN
- OMAP3630_VP2_VLIMITTO_VDDMAX
- OMAP3630_VP2_VLIMITTO_VDDMIN
- OMAP363X_CLASS
- OMAP36XX_CONTROL_MEM_RTA_CTRL
- OMAP36XX_GPIO_IO_PWRDNZ
- OMAP36XX_RTA_DISABLE
- OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION
- OMAP3ISP_AEWB_MAX_BUF_SIZE
- OMAP3ISP_AEWB_MAX_SATURATION_LIM
- OMAP3ISP_AEWB_MAX_SUB_INC
- OMAP3ISP_AEWB_MAX_WINHC
- OMAP3ISP_AEWB_MAX_WINSTART
- OMAP3ISP_AEWB_MAX_WINVC
- OMAP3ISP_AEWB_MAX_WIN_H
- OMAP3ISP_AEWB_MAX_WIN_W
- OMAP3ISP_AEWB_MIN_SUB_INC
- OMAP3ISP_AEWB_MIN_WINHC
- OMAP3ISP_AEWB_MIN_WINVC
- OMAP3ISP_AEWB_MIN_WIN_H
- OMAP3ISP_AEWB_MIN_WIN_W
- OMAP3ISP_AF_COEF_MAX
- OMAP3ISP_AF_GG_RB_CUSTOM
- OMAP3ISP_AF_GR_BG_BAYER
- OMAP3ISP_AF_GR_GB_BAYER
- OMAP3ISP_AF_IIRSH_MAX
- OMAP3ISP_AF_IIRSH_MIN
- OMAP3ISP_AF_MAX_BUF_SIZE
- OMAP3ISP_AF_MODE_PEAK
- OMAP3ISP_AF_MODE_SUMMED
- OMAP3ISP_AF_NUM_COEF
- OMAP3ISP_AF_PAXEL_HEIGHT_MAX
- OMAP3ISP_AF_PAXEL_HEIGHT_MIN
- OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX
- OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN
- OMAP3ISP_AF_PAXEL_HZSTART_MAX
- OMAP3ISP_AF_PAXEL_HZSTART_MIN
- OMAP3ISP_AF_PAXEL_INCREMENT_MAX
- OMAP3ISP_AF_PAXEL_INCREMENT_MIN
- OMAP3ISP_AF_PAXEL_SIZE
- OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX
- OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN
- OMAP3ISP_AF_PAXEL_VTSTART_MAX
- OMAP3ISP_AF_PAXEL_VTSTART_MIN
- OMAP3ISP_AF_PAXEL_WIDTH_MAX
- OMAP3ISP_AF_PAXEL_WIDTH_MIN
- OMAP3ISP_AF_RB_GG_CUSTOM
- OMAP3ISP_AF_RG_BG_BAYER
- OMAP3ISP_AF_RG_GB_BAYER
- OMAP3ISP_AF_THRESHOLD_MAX
- OMAP3ISP_ALAW_BIT10_1
- OMAP3ISP_ALAW_BIT11_2
- OMAP3ISP_ALAW_BIT12_3
- OMAP3ISP_ALAW_BIT9_0
- OMAP3ISP_CCDC_ALAW
- OMAP3ISP_CCDC_BCOMP
- OMAP3ISP_CCDC_BLCLAMP
- OMAP3ISP_CCDC_CONFIG_LSC
- OMAP3ISP_CCDC_CULL
- OMAP3ISP_CCDC_FPC
- OMAP3ISP_CCDC_LPF
- OMAP3ISP_CCDC_NEVENTS
- OMAP3ISP_CCDC_TBL_LSC
- OMAP3ISP_CFAFMT_BAYER
- OMAP3ISP_CFAFMT_DNSPL
- OMAP3ISP_CFAFMT_HONEYCOMB
- OMAP3ISP_CFAFMT_RGBFOVEON
- OMAP3ISP_CFAFMT_RRGGBBFOVEON
- OMAP3ISP_CFAFMT_SONYVGA
- OMAP3ISP_HIST_BINS_128
- OMAP3ISP_HIST_BINS_256
- OMAP3ISP_HIST_BINS_32
- OMAP3ISP_HIST_BINS_64
- OMAP3ISP_HIST_CFA_BAYER
- OMAP3ISP_HIST_CFA_FOVEONX3
- OMAP3ISP_HIST_MAX_BIT_WIDTH
- OMAP3ISP_HIST_MAX_BUF_SIZE
- OMAP3ISP_HIST_MAX_REGIONS
- OMAP3ISP_HIST_MAX_WB_GAIN
- OMAP3ISP_HIST_MAX_WG
- OMAP3ISP_HIST_MEM_SIZE
- OMAP3ISP_HIST_MEM_SIZE_BINS
- OMAP3ISP_HIST_MIN_BIT_WIDTH
- OMAP3ISP_HIST_MIN_REGIONS
- OMAP3ISP_HIST_MIN_WB_GAIN
- OMAP3ISP_HIST_SOURCE_CCDC
- OMAP3ISP_HIST_SOURCE_MEM
- OMAP3ISP_PHY_TYPE_COMPLEX_IO
- OMAP3ISP_PHY_TYPE_CSIPHY
- OMAP3ISP_PREV_BLKADJ
- OMAP3ISP_PREV_BRIGHTNESS
- OMAP3ISP_PREV_CFA
- OMAP3ISP_PREV_CFA_BLK_SIZE
- OMAP3ISP_PREV_CFA_TBL_SIZE
- OMAP3ISP_PREV_CHROMA_SUPP
- OMAP3ISP_PREV_COLOR_CONV
- OMAP3ISP_PREV_CONTRAST
- OMAP3ISP_PREV_DEFECT_COR
- OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS
- OMAP3ISP_PREV_DRK_FRM_CAPTURE
- OMAP3ISP_PREV_DRK_FRM_SUBTRACT
- OMAP3ISP_PREV_FEATURES_END
- OMAP3ISP_PREV_GAMMA
- OMAP3ISP_PREV_GAMMA_TBL_SIZE
- OMAP3ISP_PREV_HRZ_MED
- OMAP3ISP_PREV_INVALAW
- OMAP3ISP_PREV_LENS_SHADING
- OMAP3ISP_PREV_LUMAENH
- OMAP3ISP_PREV_NF
- OMAP3ISP_PREV_NF_TBL_SIZE
- OMAP3ISP_PREV_RGB2RGB
- OMAP3ISP_PREV_WB
- OMAP3ISP_PREV_YC_LIMIT
- OMAP3ISP_PREV_YENH_TBL_SIZE
- OMAP3ISP_RGB_MAX
- OMAP3PLUS_DPLL_FINT_JTYPE_MAX
- OMAP3PLUS_DPLL_FINT_JTYPE_MIN
- OMAP3PLUS_DPLL_FINT_MAX
- OMAP3PLUS_DPLL_FINT_MIN
- OMAP3XXX_EN_DPLL_FRBYPASS
- OMAP3XXX_EN_DPLL_LOCKED
- OMAP3XXX_EN_DPLL_LPBYPASS
- OMAP3_CHECK_FEATURE
- OMAP3_CLKSETUP
- OMAP3_CM_CLKOUT_CTRL_OFFSET
- OMAP3_CONTROL_OMAP_STATUS
- OMAP3_CORE1_IOPAD
- OMAP3_DPLL5_FREQ_FOR_USBHOST
- OMAP3_HAS_192MHZ_CLK
- OMAP3_HAS_FEATURE
- OMAP3_HAS_IO_CHAIN_CTRL
- OMAP3_HAS_IO_WAKEUP
- OMAP3_HAS_ISP
- OMAP3_HAS_IVA
- OMAP3_HAS_L2CACHE
- OMAP3_HAS_NEON
- OMAP3_HAS_SDRC
- OMAP3_HAS_SGX
- OMAP3_HS_USB_PORTS
- OMAP3_ISP_CCDC_H
- OMAP3_ISP_CCP2_H
- OMAP3_ISP_CORE_H
- OMAP3_ISP_CSI2_H
- OMAP3_ISP_CSI_PHY_H
- OMAP3_ISP_H3A_H
- OMAP3_ISP_HIST_H
- OMAP3_ISP_IOMEM_CCDC
- OMAP3_ISP_IOMEM_CCP2
- OMAP3_ISP_IOMEM_CSI2A_REGS1
- OMAP3_ISP_IOMEM_CSI2A_REGS2
- OMAP3_ISP_IOMEM_CSI2C_REGS1
- OMAP3_ISP_IOMEM_CSI2C_REGS2
- OMAP3_ISP_IOMEM_CSIPHY1
- OMAP3_ISP_IOMEM_CSIPHY2
- OMAP3_ISP_IOMEM_H3A
- OMAP3_ISP_IOMEM_HIST
- OMAP3_ISP_IOMEM_LAST
- OMAP3_ISP_IOMEM_MAIN
- OMAP3_ISP_IOMEM_PREV
- OMAP3_ISP_IOMEM_RESZ
- OMAP3_ISP_IOMEM_SBL
- OMAP3_ISP_MASK
- OMAP3_ISP_PREVIEW_H
- OMAP3_ISP_REG_H
- OMAP3_ISP_RESIZER_H
- OMAP3_ISP_SBL_CCDC_LSC_READ
- OMAP3_ISP_SBL_CCDC_WRITE
- OMAP3_ISP_SBL_CSI1_READ
- OMAP3_ISP_SBL_CSI1_WRITE
- OMAP3_ISP_SBL_CSI2A_WRITE
- OMAP3_ISP_SBL_CSI2C_WRITE
- OMAP3_ISP_SBL_PREVIEW_READ
- OMAP3_ISP_SBL_PREVIEW_WRITE
- OMAP3_ISP_SBL_READ
- OMAP3_ISP_SBL_RESIZER_READ
- OMAP3_ISP_SBL_RESIZER_WRITE
- OMAP3_ISP_SBL_WRITE
- OMAP3_ISP_SHIFT
- OMAP3_ISP_STAT_H
- OMAP3_ISP_SUBCLK_AEWB
- OMAP3_ISP_SUBCLK_AF
- OMAP3_ISP_SUBCLK_CCDC
- OMAP3_ISP_SUBCLK_HIST
- OMAP3_ISP_SUBCLK_PREVIEW
- OMAP3_ISP_SUBCLK_RESIZER
- OMAP3_ISP_USER_H
- OMAP3_ISP_VIDEO_H
- OMAP3_IVA2_BOOTMOD_IDLE
- OMAP3_IVA2_BOOTMOD_MASK
- OMAP3_IVA2_BOOTMOD_SHIFT
- OMAP3_IVA_MASK
- OMAP3_IVA_SHIFT
- OMAP3_L2CACHE_MASK
- OMAP3_L2CACHE_SHIFT
- OMAP3_L3_CORE_FW_INIT_ID_DSS
- OMAP3_L4_CORE_FW_DSS_CORE_REGION
- OMAP3_L4_CORE_FW_DSS_DISPC_REGION
- OMAP3_L4_CORE_FW_DSS_DSI_REGION
- OMAP3_L4_CORE_FW_DSS_PROT_GROUP
- OMAP3_L4_CORE_FW_DSS_RFBI_REGION
- OMAP3_L4_CORE_FW_DSS_TA_REGION
- OMAP3_L4_CORE_FW_DSS_VENC_REGION
- OMAP3_L4_CORE_FW_I2C1_REGION
- OMAP3_L4_CORE_FW_I2C1_TA_REGION
- OMAP3_L4_CORE_FW_I2C2_REGION
- OMAP3_L4_CORE_FW_I2C2_TA_REGION
- OMAP3_L4_CORE_FW_I2C3_REGION
- OMAP3_L4_CORE_FW_I2C3_TA_REGION
- OMAP3_NEON_MASK
- OMAP3_NEON_SHIFT
- OMAP3_OFF_VOLTAGE_UV
- OMAP3_ONLP_VOLTAGE_UV
- OMAP3_ON_VOLTAGE_UV
- OMAP3_PADCONF_SAD2D_IDLEACK
- OMAP3_PADCONF_SAD2D_MSTANDBY
- OMAP3_PADCONF_WAKEUPENABLE0
- OMAP3_PADCONF_WAKEUPEVENT0
- OMAP3_PANDORA_AMP_POWER_GPIO
- OMAP3_PANDORA_DAC_POWER_GPIO
- OMAP3_PRM_CLKOUT_CTRL_OFFSET
- OMAP3_PRM_CLKSEL_OFFSET
- OMAP3_PRM_CLKSETUP_OFFSET
- OMAP3_PRM_CLKSRC_CTRL_OFFSET
- OMAP3_PRM_IRQENABLE_MPU_OFFSET
- OMAP3_PRM_IRQSTATUS_MPU_OFFSET
- OMAP3_PRM_POLCTRL_OFFSET
- OMAP3_PRM_REVISION_OFFSET
- OMAP3_PRM_RSTCTRL_OFFSET
- OMAP3_PRM_RSTST_OFFSET
- OMAP3_PRM_RSTTIME_OFFSET
- OMAP3_PRM_SRAM_PCHARGE_OFFSET
- OMAP3_PRM_SYSCONFIG_OFFSET
- OMAP3_PRM_VC_BYPASS_VAL_OFFSET
- OMAP3_PRM_VC_CH_CONF_OFFSET
- OMAP3_PRM_VC_CMD_VAL_0_OFFSET
- OMAP3_PRM_VC_CMD_VAL_1_OFFSET
- OMAP3_PRM_VC_I2C_CFG_OFFSET
- OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET
- OMAP3_PRM_VC_SMPS_SA_OFFSET
- OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET
- OMAP3_PRM_VOLTCTRL_OFFSET
- OMAP3_PRM_VOLTOFFSET_OFFSET
- OMAP3_PRM_VOLTSETUP1_OFFSET
- OMAP3_PRM_VOLTSETUP2_OFFSET
- OMAP3_PRM_VP1_CONFIG_OFFSET
- OMAP3_PRM_VP1_STATUS_OFFSET
- OMAP3_PRM_VP1_VLIMITTO_OFFSET
- OMAP3_PRM_VP1_VOLTAGE_OFFSET
- OMAP3_PRM_VP1_VSTEPMAX_OFFSET
- OMAP3_PRM_VP1_VSTEPMIN_OFFSET
- OMAP3_PRM_VP2_CONFIG_OFFSET
- OMAP3_PRM_VP2_STATUS_OFFSET
- OMAP3_PRM_VP2_VLIMITTO_OFFSET
- OMAP3_PRM_VP2_VOLTAGE_OFFSET
- OMAP3_PRM_VP2_VSTEPMAX_OFFSET
- OMAP3_PRM_VP2_VSTEPMIN_OFFSET
- OMAP3_RET_VOLTAGE_UV
- OMAP3_SAVE_SECURE_RAM_SZ
- OMAP3_SGX_MASK
- OMAP3_SGX_SHIFT
- OMAP3_SHOW_FEATURE
- OMAP3_SOC_AM35XX
- OMAP3_SOC_OMAP3430_ES1
- OMAP3_SOC_OMAP3430_ES2_PLUS
- OMAP3_SOC_OMAP3630
- OMAP3_SRAM_PA
- OMAP3_SRAM_PUB_PA
- OMAP3_SRI2C_SLAVE_ADDR
- OMAP3_UART1_BASE
- OMAP3_UART1_RX
- OMAP3_UART2_BASE
- OMAP3_UART2_RX
- OMAP3_UART3_BASE
- OMAP3_UART3_RX
- OMAP3_UART4_AM35XX_BASE
- OMAP3_UART4_BASE
- OMAP3_VDD_CORE_SR_CONTROL_REG
- OMAP3_VDD_MPU_SR_CONTROL_REG
- OMAP3_VOLTOFFSET
- OMAP3_VOLTSETUP2
- OMAP3_VP_CONFIG_ERROROFFSET
- OMAP3_VP_VDD_CORE_ID
- OMAP3_VP_VDD_MPU_ID
- OMAP3_VP_VLIMITTO_TIMEOUT_US
- OMAP3_VP_VSTEPMAX_VSTEPMAX
- OMAP3_VP_VSTEPMIN_VSTEPMIN
- OMAP3_WKUP_IOPAD
- OMAP4430_32KSYNCT_BASE
- OMAP4430_ABE_STATDEP_SHIFT
- OMAP4430_ADC_END_VALUE
- OMAP4430_ADC_START_VALUE
- OMAP4430_AUTO_DPLL_MODE_MASK
- OMAP4430_BGAP_TEMPSOFF_MASK
- OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK
- OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK
- OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK
- OMAP4430_BGAP_TSHUT_MASK
- OMAP4430_C2C_RST_SHIFT
- OMAP4430_CLKSEL_0_0_SHIFT
- OMAP4430_CLKSEL_0_0_WIDTH
- OMAP4430_CLKSEL_0_1_SHIFT
- OMAP4430_CLKSEL_0_1_WIDTH
- OMAP4430_CLKSEL_24_25_SHIFT
- OMAP4430_CLKSEL_24_25_WIDTH
- OMAP4430_CLKSEL_60M_SHIFT
- OMAP4430_CLKSEL_60M_WIDTH
- OMAP4430_CLKSEL_AESS_FCLK_SHIFT
- OMAP4430_CLKSEL_AESS_FCLK_WIDTH
- OMAP4430_CLKSEL_CORE_SHIFT
- OMAP4430_CLKSEL_CORE_WIDTH
- OMAP4430_CLKSEL_DIV_SHIFT
- OMAP4430_CLKSEL_DIV_WIDTH
- OMAP4430_CLKSEL_FCLK_SHIFT
- OMAP4430_CLKSEL_FCLK_WIDTH
- OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT
- OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH
- OMAP4430_CLKSEL_L3_SHIFT
- OMAP4430_CLKSEL_L3_WIDTH
- OMAP4430_CLKSEL_L4_SHIFT
- OMAP4430_CLKSEL_L4_WIDTH
- OMAP4430_CLKSEL_MASK
- OMAP4430_CLKSEL_OPP_SHIFT
- OMAP4430_CLKSEL_OPP_WIDTH
- OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT
- OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH
- OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK
- OMAP4430_CLKSEL_SGX_FCLK_MASK
- OMAP4430_CLKSEL_SHIFT
- OMAP4430_CLKSEL_SOURCE_24_24_MASK
- OMAP4430_CLKSEL_SOURCE_MASK
- OMAP4430_CLKSEL_UTMI_P1_SHIFT
- OMAP4430_CLKSEL_UTMI_P1_WIDTH
- OMAP4430_CLKSEL_UTMI_P2_SHIFT
- OMAP4430_CLKSEL_UTMI_P2_WIDTH
- OMAP4430_CLKSEL_WIDTH
- OMAP4430_CLKTRCTRL_MASK
- OMAP4430_CLKTRCTRL_SHIFT
- OMAP4430_CM1_ABE_ABE_CDOFFS
- OMAP4430_CM1_ABE_AESS_CLKCTRL
- OMAP4430_CM1_ABE_CLKSTCTRL
- OMAP4430_CM1_ABE_DMIC_CLKCTRL
- OMAP4430_CM1_ABE_INST
- OMAP4430_CM1_ABE_L4ABE_CLKCTRL
- OMAP4430_CM1_ABE_MCASP_CLKCTRL
- OMAP4430_CM1_ABE_MCBSP1_CLKCTRL
- OMAP4430_CM1_ABE_MCBSP2_CLKCTRL
- OMAP4430_CM1_ABE_MCBSP3_CLKCTRL
- OMAP4430_CM1_ABE_PDM_CLKCTRL
- OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL
- OMAP4430_CM1_ABE_TIMER5_CLKCTRL
- OMAP4430_CM1_ABE_TIMER6_CLKCTRL
- OMAP4430_CM1_ABE_TIMER7_CLKCTRL
- OMAP4430_CM1_ABE_TIMER8_CLKCTRL
- OMAP4430_CM1_ABE_WDT3_CLKCTRL
- OMAP4430_CM1_BASE
- OMAP4430_CM1_CKGEN_INST
- OMAP4430_CM1_INSTR_INST
- OMAP4430_CM1_MPU_INST
- OMAP4430_CM1_MPU_MPU_CDOFFS
- OMAP4430_CM1_OCP_SOCKET_INST
- OMAP4430_CM1_PARTITION
- OMAP4430_CM1_RESTORE_INST
- OMAP4430_CM1_TESLA_INST
- OMAP4430_CM1_TESLA_TESLA_CDOFFS
- OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS
- OMAP4430_CM2_ALWAYS_ON_INST
- OMAP4430_CM2_BASE
- OMAP4430_CM2_CAM_CAM_CDOFFS
- OMAP4430_CM2_CAM_INST
- OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS
- OMAP4430_CM2_CEFUSE_INST
- OMAP4430_CM2_CKGEN_INST
- OMAP4430_CM2_CORE_D2D_CDOFFS
- OMAP4430_CM2_CORE_DUCATI_CDOFFS
- OMAP4430_CM2_CORE_INST
- OMAP4430_CM2_CORE_L3INSTR_CDOFFS
- OMAP4430_CM2_CORE_L3_1_CDOFFS
- OMAP4430_CM2_CORE_L3_2_CDOFFS
- OMAP4430_CM2_CORE_L4CFG_CDOFFS
- OMAP4430_CM2_CORE_MEMIF_CDOFFS
- OMAP4430_CM2_CORE_SDMA_CDOFFS
- OMAP4430_CM2_DSS_DSS_CDOFFS
- OMAP4430_CM2_DSS_INST
- OMAP4430_CM2_GFX_GFX_CDOFFS
- OMAP4430_CM2_GFX_INST
- OMAP4430_CM2_INSTR_INST
- OMAP4430_CM2_IVAHD_INST
- OMAP4430_CM2_IVAHD_IVAHD_CDOFFS
- OMAP4430_CM2_L3INIT_INST
- OMAP4430_CM2_L3INIT_L3INIT_CDOFFS
- OMAP4430_CM2_L4PER_INST
- OMAP4430_CM2_L4PER_L4PER_CDOFFS
- OMAP4430_CM2_L4PER_L4SEC_CDOFFS
- OMAP4430_CM2_OCP_SOCKET_INST
- OMAP4430_CM2_PARTITION
- OMAP4430_CM2_RESTORE_INST
- OMAP4430_CMDRA_VDD_CORE_L_MASK
- OMAP4430_CMDRA_VDD_IVA_L_MASK
- OMAP4430_CMDRA_VDD_MPU_L_MASK
- OMAP4430_CM_ABE_DSS_SYS_CLKSEL
- OMAP4430_CM_ABE_PLL_REF_CLKSEL
- OMAP4430_CM_ALWON_CLKSTCTRL
- OMAP4430_CM_ALWON_MDMINTC_CLKCTRL
- OMAP4430_CM_ALWON_SR_CORE_CLKCTRL
- OMAP4430_CM_ALWON_SR_IVA_CLKCTRL
- OMAP4430_CM_ALWON_SR_MPU_CLKCTRL
- OMAP4430_CM_ALWON_USBPHY_CLKCTRL
- OMAP4430_CM_AUTOIDLE_DPLL_ABE
- OMAP4430_CM_AUTOIDLE_DPLL_CORE
- OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY
- OMAP4430_CM_AUTOIDLE_DPLL_IVA
- OMAP4430_CM_AUTOIDLE_DPLL_MPU
- OMAP4430_CM_AUTOIDLE_DPLL_PER
- OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO
- OMAP4430_CM_AUTOIDLE_DPLL_USB
- OMAP4430_CM_BASE
- OMAP4430_CM_BYPCLK_DPLL_IVA
- OMAP4430_CM_BYPCLK_DPLL_MPU
- OMAP4430_CM_CAM_CLKSTCTRL
- OMAP4430_CM_CAM_DYNAMICDEP
- OMAP4430_CM_CAM_FDIF_CLKCTRL
- OMAP4430_CM_CAM_ISS_CLKCTRL
- OMAP4430_CM_CAM_STATICDEP
- OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL
- OMAP4430_CM_CEFUSE_CLKSTCTRL
- OMAP4430_CM_CLKDCOLDO_DPLL_USB
- OMAP4430_CM_CLKMODE_DPLL_ABE
- OMAP4430_CM_CLKMODE_DPLL_CORE
- OMAP4430_CM_CLKMODE_DPLL_DDRPHY
- OMAP4430_CM_CLKMODE_DPLL_IVA
- OMAP4430_CM_CLKMODE_DPLL_MPU
- OMAP4430_CM_CLKMODE_DPLL_PER
- OMAP4430_CM_CLKMODE_DPLL_UNIPRO
- OMAP4430_CM_CLKMODE_DPLL_USB
- OMAP4430_CM_CLKSEL_ABE
- OMAP4430_CM_CLKSEL_CORE
- OMAP4430_CM_CLKSEL_DPLL_ABE
- OMAP4430_CM_CLKSEL_DPLL_CORE
- OMAP4430_CM_CLKSEL_DPLL_DDRPHY
- OMAP4430_CM_CLKSEL_DPLL_IVA
- OMAP4430_CM_CLKSEL_DPLL_MPU
- OMAP4430_CM_CLKSEL_DPLL_PER
- OMAP4430_CM_CLKSEL_DPLL_UNIPRO
- OMAP4430_CM_CLKSEL_DPLL_USB
- OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT
- OMAP4430_CM_CLKSEL_USB_60MHZ
- OMAP4430_CM_CM1_PROFILING_CLKCTRL
- OMAP4430_CM_CM2_PROFILING_CLKCTRL
- OMAP4430_CM_CORE_DVFS_CURRENT
- OMAP4430_CM_CORE_DVFS_PERF1
- OMAP4430_CM_CORE_DVFS_PERF2
- OMAP4430_CM_CORE_DVFS_PERF3
- OMAP4430_CM_CORE_DVFS_PERF4
- OMAP4430_CM_CPU0_CLKSTCTRL
- OMAP4430_CM_CPU0_CPU0_CLKCTRL
- OMAP4430_CM_CPU1_CLKSTCTRL
- OMAP4430_CM_CPU1_CPU1_CLKCTRL
- OMAP4430_CM_D2D_CLKSTCTRL
- OMAP4430_CM_D2D_DYNAMICDEP
- OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL
- OMAP4430_CM_D2D_SAD2D_CLKCTRL
- OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL
- OMAP4430_CM_D2D_STATICDEP
- OMAP4430_CM_DIV_M2_DPLL_ABE
- OMAP4430_CM_DIV_M2_DPLL_CORE
- OMAP4430_CM_DIV_M2_DPLL_DDRPHY
- OMAP4430_CM_DIV_M2_DPLL_MPU
- OMAP4430_CM_DIV_M2_DPLL_PER
- OMAP4430_CM_DIV_M2_DPLL_UNIPRO
- OMAP4430_CM_DIV_M2_DPLL_USB
- OMAP4430_CM_DIV_M3_DPLL_ABE
- OMAP4430_CM_DIV_M3_DPLL_CORE
- OMAP4430_CM_DIV_M3_DPLL_PER
- OMAP4430_CM_DIV_M4_DPLL_CORE
- OMAP4430_CM_DIV_M4_DPLL_DDRPHY
- OMAP4430_CM_DIV_M4_DPLL_IVA
- OMAP4430_CM_DIV_M4_DPLL_PER
- OMAP4430_CM_DIV_M5_DPLL_CORE
- OMAP4430_CM_DIV_M5_DPLL_DDRPHY
- OMAP4430_CM_DIV_M5_DPLL_IVA
- OMAP4430_CM_DIV_M5_DPLL_PER
- OMAP4430_CM_DIV_M6_DPLL_CORE
- OMAP4430_CM_DIV_M6_DPLL_DDRPHY
- OMAP4430_CM_DIV_M6_DPLL_PER
- OMAP4430_CM_DIV_M7_DPLL_CORE
- OMAP4430_CM_DIV_M7_DPLL_PER
- OMAP4430_CM_DLL_CTRL
- OMAP4430_CM_DSS_CLKSTCTRL
- OMAP4430_CM_DSS_DEISS_CLKCTRL
- OMAP4430_CM_DSS_DSS_CLKCTRL
- OMAP4430_CM_DSS_DYNAMICDEP
- OMAP4430_CM_DSS_STATICDEP
- OMAP4430_CM_DUCATI_CLKSTCTRL
- OMAP4430_CM_DUCATI_DUCATI_CLKCTRL
- OMAP4430_CM_DUCATI_DYNAMICDEP
- OMAP4430_CM_DUCATI_STATICDEP
- OMAP4430_CM_DYN_DEP_PRESCAL
- OMAP4430_CM_EMU_CLKSTCTRL
- OMAP4430_CM_EMU_DEBUGSS_CLKCTRL
- OMAP4430_CM_EMU_DYNAMICDEP
- OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE
- OMAP4430_CM_GFX_CLKSTCTRL
- OMAP4430_CM_GFX_DYNAMICDEP
- OMAP4430_CM_GFX_GFX_CLKCTRL
- OMAP4430_CM_GFX_STATICDEP
- OMAP4430_CM_IDLEST_DPLL_ABE
- OMAP4430_CM_IDLEST_DPLL_CORE
- OMAP4430_CM_IDLEST_DPLL_DDRPHY
- OMAP4430_CM_IDLEST_DPLL_IVA
- OMAP4430_CM_IDLEST_DPLL_MPU
- OMAP4430_CM_IDLEST_DPLL_PER
- OMAP4430_CM_IDLEST_DPLL_UNIPRO
- OMAP4430_CM_IDLEST_DPLL_USB
- OMAP4430_CM_IVAHD_CLKSTCTRL
- OMAP4430_CM_IVAHD_DYNAMICDEP
- OMAP4430_CM_IVAHD_IVAHD_CLKCTRL
- OMAP4430_CM_IVAHD_SL2_CLKCTRL
- OMAP4430_CM_IVAHD_STATICDEP
- OMAP4430_CM_IVA_DVFS_CURRENT
- OMAP4430_CM_IVA_DVFS_PERF_ABE
- OMAP4430_CM_IVA_DVFS_PERF_IVAHD
- OMAP4430_CM_IVA_DVFS_PERF_TESLA
- OMAP4430_CM_L3INIT_CCPTX_CLKCTRL
- OMAP4430_CM_L3INIT_CLKSTCTRL
- OMAP4430_CM_L3INIT_DYNAMICDEP
- OMAP4430_CM_L3INIT_EMAC_CLKCTRL
- OMAP4430_CM_L3INIT_HSI_CLKCTRL
- OMAP4430_CM_L3INIT_MMC1_CLKCTRL
- OMAP4430_CM_L3INIT_MMC2_CLKCTRL
- OMAP4430_CM_L3INIT_MMC6_CLKCTRL
- OMAP4430_CM_L3INIT_P1500_CLKCTRL
- OMAP4430_CM_L3INIT_PCIESS_CLKCTRL
- OMAP4430_CM_L3INIT_SATA_CLKCTRL
- OMAP4430_CM_L3INIT_STATICDEP
- OMAP4430_CM_L3INIT_TPPSS_CLKCTRL
- OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL
- OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL
- OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL
- OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL
- OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL
- OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL
- OMAP4430_CM_L3INIT_XHPI_CLKCTRL
- OMAP4430_CM_L3INSTR_CLKSTCTRL
- OMAP4430_CM_L3INSTR_L3_3_CLKCTRL
- OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL
- OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL
- OMAP4430_CM_L3_1_CLKSTCTRL
- OMAP4430_CM_L3_1_DYNAMICDEP
- OMAP4430_CM_L3_1_L3_1_CLKCTRL
- OMAP4430_CM_L3_2_CLKSTCTRL
- OMAP4430_CM_L3_2_DYNAMICDEP
- OMAP4430_CM_L3_2_GPMC_CLKCTRL
- OMAP4430_CM_L3_2_L3_2_CLKCTRL
- OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL
- OMAP4430_CM_L4CFG_CLKSTCTRL
- OMAP4430_CM_L4CFG_DYNAMICDEP
- OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL
- OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL
- OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL
- OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL
- OMAP4430_CM_L4PER_ADC_CLKCTRL
- OMAP4430_CM_L4PER_CLKSTCTRL
- OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL
- OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL
- OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL
- OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL
- OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL
- OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL
- OMAP4430_CM_L4PER_DYNAMICDEP
- OMAP4430_CM_L4PER_ELM_CLKCTRL
- OMAP4430_CM_L4PER_GPIO2_CLKCTRL
- OMAP4430_CM_L4PER_GPIO3_CLKCTRL
- OMAP4430_CM_L4PER_GPIO4_CLKCTRL
- OMAP4430_CM_L4PER_GPIO5_CLKCTRL
- OMAP4430_CM_L4PER_GPIO6_CLKCTRL
- OMAP4430_CM_L4PER_HDQ1W_CLKCTRL
- OMAP4430_CM_L4PER_HECC1_CLKCTRL
- OMAP4430_CM_L4PER_HECC2_CLKCTRL
- OMAP4430_CM_L4PER_I2C1_CLKCTRL
- OMAP4430_CM_L4PER_I2C2_CLKCTRL
- OMAP4430_CM_L4PER_I2C3_CLKCTRL
- OMAP4430_CM_L4PER_I2C4_CLKCTRL
- OMAP4430_CM_L4PER_I2C5_CLKCTRL
- OMAP4430_CM_L4PER_L4PER_CLKCTRL
- OMAP4430_CM_L4PER_MCASP2_CLKCTRL
- OMAP4430_CM_L4PER_MCASP3_CLKCTRL
- OMAP4430_CM_L4PER_MCBSP4_CLKCTRL
- OMAP4430_CM_L4PER_MCSPI1_CLKCTRL
- OMAP4430_CM_L4PER_MCSPI2_CLKCTRL
- OMAP4430_CM_L4PER_MCSPI3_CLKCTRL
- OMAP4430_CM_L4PER_MCSPI4_CLKCTRL
- OMAP4430_CM_L4PER_MGATE_CLKCTRL
- OMAP4430_CM_L4PER_MMCSD3_CLKCTRL
- OMAP4430_CM_L4PER_MMCSD4_CLKCTRL
- OMAP4430_CM_L4PER_MMCSD5_CLKCTRL
- OMAP4430_CM_L4PER_MSPROHG_CLKCTRL
- OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL
- OMAP4430_CM_L4PER_UART1_CLKCTRL
- OMAP4430_CM_L4PER_UART2_CLKCTRL
- OMAP4430_CM_L4PER_UART3_CLKCTRL
- OMAP4430_CM_L4PER_UART4_CLKCTRL
- OMAP4430_CM_L4SEC_AES1_CLKCTRL
- OMAP4430_CM_L4SEC_AES2_CLKCTRL
- OMAP4430_CM_L4SEC_CLKSTCTRL
- OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL
- OMAP4430_CM_L4SEC_DES3DES_CLKCTRL
- OMAP4430_CM_L4SEC_DYNAMICDEP
- OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL
- OMAP4430_CM_L4SEC_RNG_CLKCTRL
- OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL
- OMAP4430_CM_L4SEC_STATICDEP
- OMAP4430_CM_L4_WKUP_CLKSEL
- OMAP4430_CM_MEMIF_CLKSTCTRL
- OMAP4430_CM_MEMIF_DLL_CLKCTRL
- OMAP4430_CM_MEMIF_DLL_H_CLKCTRL
- OMAP4430_CM_MEMIF_DMM_CLKCTRL
- OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL
- OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL
- OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL
- OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL
- OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL
- OMAP4430_CM_MPU_CLKSTCTRL
- OMAP4430_CM_MPU_DYNAMICDEP
- OMAP4430_CM_MPU_MPU_CLKCTRL
- OMAP4430_CM_MPU_STATICDEP
- OMAP4430_CM_PRM_PROFILING_CLKCTRL
- OMAP4430_CM_RESTORE_ST
- OMAP4430_CM_SCALE_FCLK
- OMAP4430_CM_SDMA_CLKSTCTRL
- OMAP4430_CM_SDMA_DYNAMICDEP
- OMAP4430_CM_SDMA_SDMA_CLKCTRL
- OMAP4430_CM_SDMA_STATICDEP
- OMAP4430_CM_SHADOW_FREQ_CONFIG1
- OMAP4430_CM_SHADOW_FREQ_CONFIG2
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO
- OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO
- OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB
- OMAP4430_CM_SYS_CLKSEL
- OMAP4430_CM_TESLA_CLKSTCTRL
- OMAP4430_CM_TESLA_DYNAMICDEP
- OMAP4430_CM_TESLA_STATICDEP
- OMAP4430_CM_TESLA_TESLA_CLKCTRL
- OMAP4430_CM_WKUP_BANDGAP_CLKCTRL
- OMAP4430_CM_WKUP_CLKSTCTRL
- OMAP4430_CM_WKUP_GPIO1_CLKCTRL
- OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL
- OMAP4430_CM_WKUP_L4WKUP_CLKCTRL
- OMAP4430_CM_WKUP_RTC_CLKCTRL
- OMAP4430_CM_WKUP_SARRAM_CLKCTRL
- OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL
- OMAP4430_CM_WKUP_TIMER12_CLKCTRL
- OMAP4430_CM_WKUP_TIMER1_CLKCTRL
- OMAP4430_CM_WKUP_USIM_CLKCTRL
- OMAP4430_CM_WKUP_WDT1_CLKCTRL
- OMAP4430_CM_WKUP_WDT2_CLKCTRL
- OMAP4430_DATA_SHIFT
- OMAP4430_DPLL_BYP_CLKSEL_SHIFT
- OMAP4430_DPLL_BYP_CLKSEL_WIDTH
- OMAP4430_DPLL_CLKOUTHIF_DIV_MASK
- OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT
- OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK
- OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK
- OMAP4430_DPLL_CLKOUT_DIV_MASK
- OMAP4430_DPLL_CLKOUT_DIV_SHIFT
- OMAP4430_DPLL_CLKOUT_DIV_WIDTH
- OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK
- OMAP4430_DPLL_DIV_0_7_MASK
- OMAP4430_DPLL_DIV_MASK
- OMAP4430_DPLL_EN_MASK
- OMAP4430_DPLL_LPMODE_EN_MASK
- OMAP4430_DPLL_MULT_MASK
- OMAP4430_DPLL_MULT_USB_MASK
- OMAP4430_DPLL_REGM4XEN_MASK
- OMAP4430_DPLL_SD_DIV_MASK
- OMAP4430_DSS_STATDEP_SHIFT
- OMAP4430_DUCATI_STATDEP_SHIFT
- OMAP4430_ERRORGAIN_MASK
- OMAP4430_ERROROFFSET_MASK
- OMAP4430_EXTERNAL_WARM_RST_SHIFT
- OMAP4430_FORCEUPDATE_MASK
- OMAP4430_FUSE_OPP_BGAP
- OMAP4430_GFX_STATDEP_SHIFT
- OMAP4430_GLOBAL_COLD_RST_SHIFT
- OMAP4430_GLOBAL_WARM_SW_RST_SHIFT
- OMAP4430_GLOBAL_WUEN_MASK
- OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK
- OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK
- OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK
- OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK
- OMAP4430_HSMCODE_MASK
- OMAP4430_HSMODEEN_MASK
- OMAP4430_HSSCLL_SHIFT
- OMAP4430_ICEPICK_RST_SHIFT
- OMAP4430_IDLEST_MASK
- OMAP4430_IDLEST_SHIFT
- OMAP4430_INITVDD_MASK
- OMAP4430_INITVOLTAGE_MASK
- OMAP4430_INVALID_PRCM_PARTITION
- OMAP4430_IVAHD_STATDEP_SHIFT
- OMAP4430_L3INIT_STATDEP_SHIFT
- OMAP4430_L3_1_STATDEP_SHIFT
- OMAP4430_L3_2_STATDEP_SHIFT
- OMAP4430_L4CFG_STATDEP_SHIFT
- OMAP4430_L4PER_STATDEP_SHIFT
- OMAP4430_L4SEC_STATDEP_SHIFT
- OMAP4430_L4WKUP_STATDEP_SHIFT
- OMAP4430_LASTPOWERSTATEENTERED_MASK
- OMAP4430_LASTPOWERSTATEENTERED_SHIFT
- OMAP4430_LOGICRETSTATE_MASK
- OMAP4430_LOGICRETSTATE_SHIFT
- OMAP4430_LOGICSTATEST_MASK
- OMAP4430_LOGICSTATEST_SHIFT
- OMAP4430_LOSTCONTEXT_DFF_MASK
- OMAP4430_LOSTMEM_AESSMEM_MASK
- OMAP4430_LOWPOWERSTATECHANGE_MASK
- OMAP4430_LOWPOWERSTATECHANGE_SHIFT
- OMAP4430_MAX_FREQ
- OMAP4430_MEMIF_STATDEP_SHIFT
- OMAP4430_MIN_FREQ
- OMAP4430_MODULEMODE_MASK
- OMAP4430_MODULEMODE_SHIFT
- OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT
- OMAP4430_MPU_WDT_RST_SHIFT
- OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
- OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
- OMAP4430_OCP_NRET_BANK_STATEST_MASK
- OMAP4430_OFF_SHIFT
- OMAP4430_ONLP_SHIFT
- OMAP4430_ON_MASK
- OMAP4430_ON_SHIFT
- OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT
- OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT
- OMAP4430_OPTFCLKEN_CLK32K_SHIFT
- OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT
- OMAP4430_OPTFCLKEN_DBCLK_SHIFT
- OMAP4430_OPTFCLKEN_DSSCLK_SHIFT
- OMAP4430_OPTFCLKEN_FCLK0_SHIFT
- OMAP4430_OPTFCLKEN_FCLK1_SHIFT
- OMAP4430_OPTFCLKEN_FCLK2_SHIFT
- OMAP4430_OPTFCLKEN_FCLK_SHIFT
- OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT
- OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT
- OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT
- OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT
- OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT
- OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT
- OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT
- OMAP4430_OPTFCLKEN_PHY_48M_SHIFT
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT
- OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT
- OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT
- OMAP4430_OPTFCLKEN_TV_CLK_SHIFT
- OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT
- OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT
- OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT
- OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT
- OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT
- OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT
- OMAP4430_OPTFCLKEN_XCLK_SHIFT
- OMAP4430_PAD_CLKS_GATE_SHIFT
- OMAP4430_PMD_STM_MUX_CTRL_SHIFT
- OMAP4430_PMD_STM_MUX_CTRL_WIDTH
- OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT
- OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH
- OMAP4430_PM_ABE_DMIC_WKDEP
- OMAP4430_PM_ABE_MCASP_WKDEP
- OMAP4430_PM_ABE_MCBSP1_WKDEP
- OMAP4430_PM_ABE_MCBSP2_WKDEP
- OMAP4430_PM_ABE_MCBSP3_WKDEP
- OMAP4430_PM_ABE_PDM_WKDEP
- OMAP4430_PM_ABE_PWRSTCTRL
- OMAP4430_PM_ABE_PWRSTST
- OMAP4430_PM_ABE_SLIMBUS_WKDEP
- OMAP4430_PM_ABE_TIMER5_WKDEP
- OMAP4430_PM_ABE_TIMER6_WKDEP
- OMAP4430_PM_ABE_TIMER7_WKDEP
- OMAP4430_PM_ABE_TIMER8_WKDEP
- OMAP4430_PM_ABE_WDT3_WKDEP
- OMAP4430_PM_ALWON_SR_CORE_WKDEP
- OMAP4430_PM_ALWON_SR_IVA_WKDEP
- OMAP4430_PM_ALWON_SR_MPU_WKDEP
- OMAP4430_PM_CAM_PWRSTCTRL
- OMAP4430_PM_CAM_PWRSTST
- OMAP4430_PM_CEFUSE_PWRSTCTRL
- OMAP4430_PM_CEFUSE_PWRSTST
- OMAP4430_PM_CORE_PWRSTCTRL
- OMAP4430_PM_CORE_PWRSTST
- OMAP4430_PM_CPU0_PWRSTCTRL
- OMAP4430_PM_CPU0_PWRSTST
- OMAP4430_PM_CPU1_PWRSTCTRL
- OMAP4430_PM_CPU1_PWRSTST
- OMAP4430_PM_DSS_DSS_WKDEP
- OMAP4430_PM_DSS_PWRSTCTRL
- OMAP4430_PM_DSS_PWRSTST
- OMAP4430_PM_EMU_PWRSTCTRL
- OMAP4430_PM_EMU_PWRSTST
- OMAP4430_PM_GFX_PWRSTCTRL
- OMAP4430_PM_GFX_PWRSTST
- OMAP4430_PM_IVAHD_PWRSTCTRL
- OMAP4430_PM_IVAHD_PWRSTST
- OMAP4430_PM_L3INIT_HSI_WKDEP
- OMAP4430_PM_L3INIT_MMC1_WKDEP
- OMAP4430_PM_L3INIT_MMC2_WKDEP
- OMAP4430_PM_L3INIT_MMC6_WKDEP
- OMAP4430_PM_L3INIT_PCIESS_WKDEP
- OMAP4430_PM_L3INIT_PWRSTCTRL
- OMAP4430_PM_L3INIT_PWRSTST
- OMAP4430_PM_L3INIT_SATA_WKDEP
- OMAP4430_PM_L3INIT_UNIPRO1_WKDEP
- OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP
- OMAP4430_PM_L3INIT_USB_HOST_WKDEP
- OMAP4430_PM_L3INIT_USB_OTG_WKDEP
- OMAP4430_PM_L3INIT_USB_TLL_WKDEP
- OMAP4430_PM_L3INIT_XHPI_WKDEP
- OMAP4430_PM_L4PER_DMTIMER10_WKDEP
- OMAP4430_PM_L4PER_DMTIMER11_WKDEP
- OMAP4430_PM_L4PER_DMTIMER2_WKDEP
- OMAP4430_PM_L4PER_DMTIMER3_WKDEP
- OMAP4430_PM_L4PER_DMTIMER4_WKDEP
- OMAP4430_PM_L4PER_DMTIMER9_WKDEP
- OMAP4430_PM_L4PER_GPIO2_WKDEP
- OMAP4430_PM_L4PER_GPIO3_WKDEP
- OMAP4430_PM_L4PER_GPIO4_WKDEP
- OMAP4430_PM_L4PER_GPIO5_WKDEP
- OMAP4430_PM_L4PER_GPIO6_WKDEP
- OMAP4430_PM_L4PER_HECC1_WKDEP
- OMAP4430_PM_L4PER_HECC2_WKDEP
- OMAP4430_PM_L4PER_I2C1_WKDEP
- OMAP4430_PM_L4PER_I2C2_WKDEP
- OMAP4430_PM_L4PER_I2C3_WKDEP
- OMAP4430_PM_L4PER_I2C4_WKDEP
- OMAP4430_PM_L4PER_I2C5_WKDEP
- OMAP4430_PM_L4PER_MCASP2_WKDEP
- OMAP4430_PM_L4PER_MCASP3_WKDEP
- OMAP4430_PM_L4PER_MCBSP4_WKDEP
- OMAP4430_PM_L4PER_MCSPI1_WKDEP
- OMAP4430_PM_L4PER_MCSPI2_WKDEP
- OMAP4430_PM_L4PER_MCSPI3_WKDEP
- OMAP4430_PM_L4PER_MCSPI4_WKDEP
- OMAP4430_PM_L4PER_MMCSD3_WKDEP
- OMAP4430_PM_L4PER_MMCSD4_WKDEP
- OMAP4430_PM_L4PER_MMCSD5_WKDEP
- OMAP4430_PM_L4PER_PWRSTCTRL
- OMAP4430_PM_L4PER_PWRSTST
- OMAP4430_PM_L4PER_SLIMBUS2_WKDEP
- OMAP4430_PM_L4PER_UART1_WKDEP
- OMAP4430_PM_L4PER_UART2_WKDEP
- OMAP4430_PM_L4PER_UART3_WKDEP
- OMAP4430_PM_L4PER_UART4_WKDEP
- OMAP4430_PM_MPU_PWRSTCTRL
- OMAP4430_PM_MPU_PWRSTST
- OMAP4430_PM_TESLA_PWRSTCTRL
- OMAP4430_PM_TESLA_PWRSTST
- OMAP4430_PM_WKUP_GPIO1_WKDEP
- OMAP4430_PM_WKUP_KEYBOARD_WKDEP
- OMAP4430_PM_WKUP_RTC_WKDEP
- OMAP4430_PM_WKUP_TIMER12_WKDEP
- OMAP4430_PM_WKUP_TIMER1_WKDEP
- OMAP4430_PM_WKUP_USIM_WKDEP
- OMAP4430_PM_WKUP_WDT2_WKDEP
- OMAP4430_PRCM_MPU_BASE
- OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS
- OMAP4430_PRCM_MPU_CPU0_INST
- OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS
- OMAP4430_PRCM_MPU_CPU1_INST
- OMAP4430_PRCM_MPU_DEVICE_PRM_INST
- OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST
- OMAP4430_PRCM_MPU_PARTITION
- OMAP4430_PRCM_MPU_PRM_PSCON_COUNT
- OMAP4430_PRCM_MPU_PRM_RSTST
- OMAP4430_PRM_ABE_INST
- OMAP4430_PRM_ALWAYS_ON_INST
- OMAP4430_PRM_BASE
- OMAP4430_PRM_CAM_INST
- OMAP4430_PRM_CEFUSE_INST
- OMAP4430_PRM_CKGEN_INST
- OMAP4430_PRM_CLKREQCTRL
- OMAP4430_PRM_CORE_INST
- OMAP4430_PRM_DEVICE_INST
- OMAP4430_PRM_DEVICE_OFF_CTRL
- OMAP4430_PRM_DSS_INST
- OMAP4430_PRM_EMU_CM_EMU_CDOFFS
- OMAP4430_PRM_EMU_CM_INST
- OMAP4430_PRM_EMU_INST
- OMAP4430_PRM_GFX_INST
- OMAP4430_PRM_INSTR_INST
- OMAP4430_PRM_IO_COUNT
- OMAP4430_PRM_IO_PMCTRL
- OMAP4430_PRM_IRQENABLE_DUCATI
- OMAP4430_PRM_IRQENABLE_MPU
- OMAP4430_PRM_IRQENABLE_MPU_2
- OMAP4430_PRM_IRQENABLE_TESLA
- OMAP4430_PRM_IRQSTATUS_DUCATI
- OMAP4430_PRM_IRQSTATUS_MPU
- OMAP4430_PRM_IRQSTATUS_MPU_2
- OMAP4430_PRM_IRQSTATUS_TESLA
- OMAP4430_PRM_IVAHD_INST
- OMAP4430_PRM_L3INIT_INST
- OMAP4430_PRM_L4PER_INST
- OMAP4430_PRM_LDO_ABB_IVA_CTRL
- OMAP4430_PRM_LDO_ABB_IVA_SETUP
- OMAP4430_PRM_LDO_ABB_MPU_CTRL
- OMAP4430_PRM_LDO_ABB_MPU_SETUP
- OMAP4430_PRM_LDO_BANDGAP_SETUP
- OMAP4430_PRM_LDO_SRAM_CORE_CTRL
- OMAP4430_PRM_LDO_SRAM_CORE_SETUP
- OMAP4430_PRM_LDO_SRAM_IVA_CTRL
- OMAP4430_PRM_LDO_SRAM_IVA_SETUP
- OMAP4430_PRM_LDO_SRAM_MPU_CTRL
- OMAP4430_PRM_LDO_SRAM_MPU_SETUP
- OMAP4430_PRM_MODEM_IF_CTRL
- OMAP4430_PRM_MPU_INST
- OMAP4430_PRM_OCP_SOCKET_INST
- OMAP4430_PRM_PARTITION
- OMAP4430_PRM_PHASE1_CNDP
- OMAP4430_PRM_PHASE2A_CNDP
- OMAP4430_PRM_PHASE2B_CNDP
- OMAP4430_PRM_PSCON_COUNT
- OMAP4430_PRM_PWRREQCTRL
- OMAP4430_PRM_RSTCTRL
- OMAP4430_PRM_RSTST
- OMAP4430_PRM_RSTTIME
- OMAP4430_PRM_SRAM_COUNT
- OMAP4430_PRM_SRAM_WKUP_SETUP
- OMAP4430_PRM_TESLA_INST
- OMAP4430_PRM_VC_CFG_CHANNEL
- OMAP4430_PRM_VC_CFG_I2C_CLK
- OMAP4430_PRM_VC_CFG_I2C_MODE
- OMAP4430_PRM_VC_ERRST
- OMAP4430_PRM_VC_SMPS_SA
- OMAP4430_PRM_VC_VAL_BYPASS
- OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L
- OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L
- OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L
- OMAP4430_PRM_VC_VAL_SMPS_RA_CMD
- OMAP4430_PRM_VC_VAL_SMPS_RA_VOL
- OMAP4430_PRM_VOLTCTRL
- OMAP4430_PRM_VOLTSETUP_CORE_OFF
- OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP
- OMAP4430_PRM_VOLTSETUP_IVA_OFF
- OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP
- OMAP4430_PRM_VOLTSETUP_MPU_OFF
- OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP
- OMAP4430_PRM_VOLTSETUP_WARMRESET
- OMAP4430_PRM_VP_CORE_CONFIG
- OMAP4430_PRM_VP_CORE_STATUS
- OMAP4430_PRM_VP_CORE_VLIMITTO
- OMAP4430_PRM_VP_CORE_VOLTAGE
- OMAP4430_PRM_VP_CORE_VSTEPMAX
- OMAP4430_PRM_VP_CORE_VSTEPMIN
- OMAP4430_PRM_VP_IVA_CONFIG
- OMAP4430_PRM_VP_IVA_STATUS
- OMAP4430_PRM_VP_IVA_VLIMITTO
- OMAP4430_PRM_VP_IVA_VOLTAGE
- OMAP4430_PRM_VP_IVA_VSTEPMAX
- OMAP4430_PRM_VP_IVA_VSTEPMIN
- OMAP4430_PRM_VP_MPU_CONFIG
- OMAP4430_PRM_VP_MPU_STATUS
- OMAP4430_PRM_VP_MPU_VLIMITTO
- OMAP4430_PRM_VP_MPU_VOLTAGE
- OMAP4430_PRM_VP_MPU_VSTEPMAX
- OMAP4430_PRM_VP_MPU_VSTEPMIN
- OMAP4430_PRM_WKUP_CM_INST
- OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS
- OMAP4430_PRM_WKUP_INST
- OMAP4430_RAMP_DOWN_COUNT_SHIFT
- OMAP4430_RAMP_UP_COUNT_SHIFT
- OMAP4430_RAMP_UP_PRESCAL_SHIFT
- OMAP4430_REGADDR_SHIFT
- OMAP4430_REGM4XEN_MULT
- OMAP4430_RET_SHIFT
- OMAP4430_REVISION_CM1
- OMAP4430_REVISION_CM2
- OMAP4430_REVISION_PRCM
- OMAP4430_REVISION_PRM
- OMAP4430_REV_ES1_0
- OMAP4430_REV_ES2_0
- OMAP4430_REV_ES2_1
- OMAP4430_REV_ES2_2
- OMAP4430_REV_ES2_3
- OMAP4430_RM_ABE_AESS_CONTEXT
- OMAP4430_RM_ABE_DMIC_CONTEXT
- OMAP4430_RM_ABE_MCASP_CONTEXT
- OMAP4430_RM_ABE_MCBSP1_CONTEXT
- OMAP4430_RM_ABE_MCBSP2_CONTEXT
- OMAP4430_RM_ABE_MCBSP3_CONTEXT
- OMAP4430_RM_ABE_PDM_CONTEXT
- OMAP4430_RM_ABE_SLIMBUS_CONTEXT
- OMAP4430_RM_ABE_TIMER5_CONTEXT
- OMAP4430_RM_ABE_TIMER6_CONTEXT
- OMAP4430_RM_ABE_TIMER7_CONTEXT
- OMAP4430_RM_ABE_TIMER8_CONTEXT
- OMAP4430_RM_ABE_WDT3_CONTEXT
- OMAP4430_RM_ALWON_MDMINTC_CONTEXT
- OMAP4430_RM_ALWON_SR_CORE_CONTEXT
- OMAP4430_RM_ALWON_SR_IVA_CONTEXT
- OMAP4430_RM_ALWON_SR_MPU_CONTEXT
- OMAP4430_RM_CAM_FDIF_CONTEXT
- OMAP4430_RM_CAM_ISS_CONTEXT
- OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT
- OMAP4430_RM_CPU0_CPU0_CONTEXT
- OMAP4430_RM_CPU0_CPU0_RSTCTRL
- OMAP4430_RM_CPU0_CPU0_RSTST
- OMAP4430_RM_CPU1_CPU1_CONTEXT
- OMAP4430_RM_CPU1_CPU1_RSTCTRL
- OMAP4430_RM_CPU1_CPU1_RSTST
- OMAP4430_RM_D2D_MODEM_ICR_CONTEXT
- OMAP4430_RM_D2D_SAD2D_CONTEXT
- OMAP4430_RM_D2D_SAD2D_FW_CONTEXT
- OMAP4430_RM_DSS_DEISS_CONTEXT
- OMAP4430_RM_DSS_DSS_CONTEXT
- OMAP4430_RM_DUCATI_DUCATI_CONTEXT
- OMAP4430_RM_DUCATI_RSTCTRL
- OMAP4430_RM_DUCATI_RSTST
- OMAP4430_RM_EMU_DEBUGSS_CONTEXT
- OMAP4430_RM_GFX_GFX_CONTEXT
- OMAP4430_RM_IVAHD_IVAHD_CONTEXT
- OMAP4430_RM_IVAHD_RSTCTRL
- OMAP4430_RM_IVAHD_RSTST
- OMAP4430_RM_IVAHD_SL2_CONTEXT
- OMAP4430_RM_L3INIT_CCPTX_CONTEXT
- OMAP4430_RM_L3INIT_EMAC_CONTEXT
- OMAP4430_RM_L3INIT_HSI_CONTEXT
- OMAP4430_RM_L3INIT_MMC1_CONTEXT
- OMAP4430_RM_L3INIT_MMC2_CONTEXT
- OMAP4430_RM_L3INIT_MMC6_CONTEXT
- OMAP4430_RM_L3INIT_P1500_CONTEXT
- OMAP4430_RM_L3INIT_PCIESS_CONTEXT
- OMAP4430_RM_L3INIT_SATA_CONTEXT
- OMAP4430_RM_L3INIT_TPPSS_CONTEXT
- OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT
- OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT
- OMAP4430_RM_L3INIT_USB_HOST_CONTEXT
- OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT
- OMAP4430_RM_L3INIT_USB_OTG_CONTEXT
- OMAP4430_RM_L3INIT_USB_TLL_CONTEXT
- OMAP4430_RM_L3INIT_XHPI_CONTEXT
- OMAP4430_RM_L3INSTR_L3_3_CONTEXT
- OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT
- OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT
- OMAP4430_RM_L3_1_L3_1_CONTEXT
- OMAP4430_RM_L3_2_GPMC_CONTEXT
- OMAP4430_RM_L3_2_L3_2_CONTEXT
- OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT
- OMAP4430_RM_L4CFG_HW_SEM_CONTEXT
- OMAP4430_RM_L4CFG_L4_CFG_CONTEXT
- OMAP4430_RM_L4CFG_MAILBOX_CONTEXT
- OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT
- OMAP4430_RM_L4PER_ADC_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER10_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER11_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER2_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER3_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER4_CONTEXT
- OMAP4430_RM_L4PER_DMTIMER9_CONTEXT
- OMAP4430_RM_L4PER_ELM_CONTEXT
- OMAP4430_RM_L4PER_GPIO2_CONTEXT
- OMAP4430_RM_L4PER_GPIO3_CONTEXT
- OMAP4430_RM_L4PER_GPIO4_CONTEXT
- OMAP4430_RM_L4PER_GPIO5_CONTEXT
- OMAP4430_RM_L4PER_GPIO6_CONTEXT
- OMAP4430_RM_L4PER_HDQ1W_CONTEXT
- OMAP4430_RM_L4PER_HECC1_CONTEXT
- OMAP4430_RM_L4PER_HECC2_CONTEXT
- OMAP4430_RM_L4PER_I2C1_CONTEXT
- OMAP4430_RM_L4PER_I2C2_CONTEXT
- OMAP4430_RM_L4PER_I2C3_CONTEXT
- OMAP4430_RM_L4PER_I2C4_CONTEXT
- OMAP4430_RM_L4PER_I2C5_CONTEXT
- OMAP4430_RM_L4PER_L4_PER_CONTEXT
- OMAP4430_RM_L4PER_MCASP2_CONTEXT
- OMAP4430_RM_L4PER_MCASP3_CONTEXT
- OMAP4430_RM_L4PER_MCBSP4_CONTEXT
- OMAP4430_RM_L4PER_MCSPI1_CONTEXT
- OMAP4430_RM_L4PER_MCSPI2_CONTEXT
- OMAP4430_RM_L4PER_MCSPI3_CONTEXT
- OMAP4430_RM_L4PER_MCSPI4_CONTEXT
- OMAP4430_RM_L4PER_MGATE_CONTEXT
- OMAP4430_RM_L4PER_MMCSD3_CONTEXT
- OMAP4430_RM_L4PER_MMCSD4_CONTEXT
- OMAP4430_RM_L4PER_MMCSD5_CONTEXT
- OMAP4430_RM_L4PER_MSPROHG_CONTEXT
- OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT
- OMAP4430_RM_L4PER_UART1_CONTEXT
- OMAP4430_RM_L4PER_UART2_CONTEXT
- OMAP4430_RM_L4PER_UART3_CONTEXT
- OMAP4430_RM_L4PER_UART4_CONTEXT
- OMAP4430_RM_L4SEC_AES1_CONTEXT
- OMAP4430_RM_L4SEC_AES2_CONTEXT
- OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT
- OMAP4430_RM_L4SEC_DES3DES_CONTEXT
- OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT
- OMAP4430_RM_L4SEC_RNG_CONTEXT
- OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT
- OMAP4430_RM_MEMIF_DLL_CONTEXT
- OMAP4430_RM_MEMIF_DLL_H_CONTEXT
- OMAP4430_RM_MEMIF_DMM_CONTEXT
- OMAP4430_RM_MEMIF_EMIF_1_CONTEXT
- OMAP4430_RM_MEMIF_EMIF_2_CONTEXT
- OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT
- OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT
- OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT
- OMAP4430_RM_MPU_MPU_CONTEXT
- OMAP4430_RM_MPU_RSTST
- OMAP4430_RM_SDMA_SDMA_CONTEXT
- OMAP4430_RM_TESLA_RSTCTRL
- OMAP4430_RM_TESLA_RSTST
- OMAP4430_RM_TESLA_TESLA_CONTEXT
- OMAP4430_RM_WKUP_GPIO1_CONTEXT
- OMAP4430_RM_WKUP_KEYBOARD_CONTEXT
- OMAP4430_RM_WKUP_L4WKUP_CONTEXT
- OMAP4430_RM_WKUP_RTC_CONTEXT
- OMAP4430_RM_WKUP_SARRAM_CONTEXT
- OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT
- OMAP4430_RM_WKUP_TIMER12_CONTEXT
- OMAP4430_RM_WKUP_TIMER1_CONTEXT
- OMAP4430_RM_WKUP_USIM_CONTEXT
- OMAP4430_RM_WKUP_WDT1_CONTEXT
- OMAP4430_RM_WKUP_WDT2_CONTEXT
- OMAP4430_RST_GLOBAL_WARM_SW_MASK
- OMAP4430_SA_VDD_CORE_L_0_6_MASK
- OMAP4430_SA_VDD_CORE_L_SHIFT
- OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK
- OMAP4430_SA_VDD_IVA_L_SHIFT
- OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK
- OMAP4430_SA_VDD_MPU_L_SHIFT
- OMAP4430_SCALE_FCLK_SHIFT
- OMAP4430_SCALE_FCLK_WIDTH
- OMAP4430_SCLH_SHIFT
- OMAP4430_SCLL_SHIFT
- OMAP4430_SCRM_PARTITION
- OMAP4430_SECURE_WDT_RST_SHIFT
- OMAP4430_SINGLE_MODE_MASK
- OMAP4430_SLAVEADDR_SHIFT
- OMAP4430_SLIMBUS_CLK_GATE_SHIFT
- OMAP4430_SMPSWAITTIMEMAX_SHIFT
- OMAP4430_SMPSWAITTIMEMIN_SHIFT
- OMAP4430_SRMODEEN_MASK
- OMAP4430_ST_DPLL_CLK_MASK
- OMAP4430_SYS_CLKSEL_SHIFT
- OMAP4430_SYS_CLKSEL_WIDTH
- OMAP4430_TEMP_SENSOR_CTRL_OFFSET
- OMAP4430_TESLA_STATDEP_SHIFT
- OMAP4430_TIMEOUTEN_MASK
- OMAP4430_TIMEOUT_SHIFT
- OMAP4430_VALID_MASK
- OMAP4430_VDDMAX_SHIFT
- OMAP4430_VDDMIN_SHIFT
- OMAP4430_VDD_CORE_OPP100_UV
- OMAP4430_VDD_CORE_OPP50_UV
- OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT
- OMAP4430_VDD_IVA_OPP100_UV
- OMAP4430_VDD_IVA_OPP50_UV
- OMAP4430_VDD_IVA_OPPTURBO_UV
- OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT
- OMAP4430_VDD_MPU_OPP100_UV
- OMAP4430_VDD_MPU_OPP50_UV
- OMAP4430_VDD_MPU_OPPNITRO_UV
- OMAP4430_VDD_MPU_OPPTURBO_UV
- OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT
- OMAP4430_VOLRA_VDD_CORE_L_MASK
- OMAP4430_VOLRA_VDD_IVA_L_MASK
- OMAP4430_VOLRA_VDD_MPU_L_MASK
- OMAP4430_VPENABLE_MASK
- OMAP4430_VPVOLTAGE_MASK
- OMAP4430_VP_CORE_TRANXDONE_ST_MASK
- OMAP4430_VP_IVA_TRANXDONE_ST_MASK
- OMAP4430_VP_MPU_TRANXDONE_ST_MASK
- OMAP4430_VSTEPMAX_SHIFT
- OMAP4430_VSTEPMIN_SHIFT
- OMAP4430_WUCLK_CTRL_MASK
- OMAP4430_WUCLK_STATUS_MASK
- OMAP4430_WUCLK_STATUS_SHIFT
- OMAP443X_CLASS
- OMAP443X_CTRL_BASE
- OMAP443X_SCM_BASE
- OMAP4460_ADC_END_VALUE
- OMAP4460_ADC_START_VALUE
- OMAP4460_BGAP_COUNTER_OFFSET
- OMAP4460_BGAP_CTRL_OFFSET
- OMAP4460_BGAP_STATUS_OFFSET
- OMAP4460_BGAP_TEMPSOFF_MASK
- OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK
- OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK
- OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK
- OMAP4460_BGAP_THRESHOLD_OFFSET
- OMAP4460_BGAP_TSHUT_OFFSET
- OMAP4460_COLD_FLAG_MASK
- OMAP4460_COUNTER_MASK
- OMAP4460_FUSE_OPP_BGAP
- OMAP4460_HOT_FLAG_MASK
- OMAP4460_MASK_COLD_MASK
- OMAP4460_MASK_HOT_MASK
- OMAP4460_MAX_FREQ
- OMAP4460_MIN_FREQ
- OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT
- OMAP4460_REV_ES1_0
- OMAP4460_REV_ES1_1
- OMAP4460_SINGLE_MODE_MASK
- OMAP4460_TEMP_SENSOR_CTRL_OFFSET
- OMAP4460_TSHUT_COLD
- OMAP4460_TSHUT_COLD_MASK
- OMAP4460_TSHUT_HOT
- OMAP4460_TSHUT_HOT_MASK
- OMAP4460_T_COLD
- OMAP4460_T_COLD_MASK
- OMAP4460_T_HOT
- OMAP4460_T_HOT_MASK
- OMAP4460_VDD_CORE_OPP100_OV_UV
- OMAP4460_VDD_CORE_OPP100_UV
- OMAP4460_VDD_CORE_OPP50_UV
- OMAP4460_VDD_IVA_OPP100_UV
- OMAP4460_VDD_IVA_OPP50_UV
- OMAP4460_VDD_IVA_OPPNITRO_UV
- OMAP4460_VDD_IVA_OPPTURBO_UV
- OMAP4460_VDD_MPU_OPP100_UV
- OMAP4460_VDD_MPU_OPP50_UV
- OMAP4460_VDD_MPU_OPPNITRO_UV
- OMAP4460_VDD_MPU_OPPTURBO_UV
- OMAP446X_CLASS
- OMAP4470_REV_ES1_0
- OMAP447X_CLASS
- OMAP44XX_CM1_REGADDR
- OMAP44XX_CM2_REGADDR
- OMAP44XX_CONTROL_FUSE_CORE_OPP100
- OMAP44XX_CONTROL_FUSE_CORE_OPP100OV
- OMAP44XX_CONTROL_FUSE_CORE_OPP50
- OMAP44XX_CONTROL_FUSE_IVA_OPP100
- OMAP44XX_CONTROL_FUSE_IVA_OPP50
- OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO
- OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO
- OMAP44XX_CONTROL_FUSE_MPU_OPP100
- OMAP44XX_CONTROL_FUSE_MPU_OPP50
- OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO
- OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO
- OMAP44XX_DMA_REQ_START
- OMAP44XX_DMM_BASE
- OMAP44XX_EMIF1_BASE
- OMAP44XX_EMIF2_BASE
- OMAP44XX_GIC_CPU_BASE
- OMAP44XX_GIC_DIST_BASE
- OMAP44XX_GPMC_BASE
- OMAP44XX_HSUSB_EHCI_BASE
- OMAP44XX_HSUSB_OHCI_BASE
- OMAP44XX_HSUSB_OTG_BASE
- OMAP44XX_IC_BASE
- OMAP44XX_IRQ_GIC_START
- OMAP44XX_IVA_INTC_BASE
- OMAP44XX_L2CACHE_BASE
- OMAP44XX_LOCAL_TWD_BASE
- OMAP44XX_MAILBOX_BASE
- OMAP44XX_MCPDM_BASE
- OMAP44XX_PRCM_MPU_REGADDR
- OMAP44XX_PRM_REGADDR
- OMAP44XX_SAR_RAM_BASE
- OMAP44XX_SCRM_REGADDR
- OMAP44XX_UHH_CONFIG_BASE
- OMAP44XX_USBTLL_BASE
- OMAP44XX_WKUPGEN_BASE
- OMAP4XXX_EN_DPLL_FRBYPASS
- OMAP4XXX_EN_DPLL_LOCKED
- OMAP4XXX_EN_DPLL_LPBYPASS
- OMAP4XXX_EN_DPLL_MNBYPASS
- OMAP4_ACCURACY_MASK
- OMAP4_ACCURACY_SHIFT
- OMAP4_AESS_CLKCTRL
- OMAP4_ALTCLKSRC_MODE_MASK
- OMAP4_ALTCLKSRC_MODE_SHIFT
- OMAP4_APEWARMRSTST_MASK
- OMAP4_APEWARMRSTST_SHIFT
- OMAP4_C2C_CLKCTRL
- OMAP4_CAMERARX_CSI21_CAMMODE_MASK
- OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT
- OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK
- OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT
- OMAP4_CAMERARX_CSI21_LANEENABLE_MASK
- OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT
- OMAP4_CAMERARX_CSI22_CAMMODE_MASK
- OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT
- OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK
- OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT
- OMAP4_CAMERARX_CSI22_LANEENABLE_MASK
- OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT
- OMAP4_CLKCTRL_INDEX
- OMAP4_CLKCTRL_OFFSET
- OMAP4_CLKDIV_MASK
- OMAP4_CLKDIV_SHIFT
- OMAP4_CLKDIV_WIDTH
- OMAP4_CLK_32KHZ_MASK
- OMAP4_CLK_32KHZ_SHIFT
- OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_CLKSTCTRL_OFFSET
- OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
- OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
- OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET
- OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET
- OMAP4_CM_ALWON_CLKSTCTRL_OFFSET
- OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET
- OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
- OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
- OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
- OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET
- OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET
- OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET
- OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET
- OMAP4_CM_CAM_CLKSTCTRL_OFFSET
- OMAP4_CM_CAM_DYNAMICDEP_OFFSET
- OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
- OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
- OMAP4_CM_CAM_STATICDEP_OFFSET
- OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET
- OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET
- OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET
- OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET
- OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET
- OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET
- OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET
- OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET
- OMAP4_CM_CLKMODE_DPLL_PER_OFFSET
- OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET
- OMAP4_CM_CLKMODE_DPLL_USB_OFFSET
- OMAP4_CM_CLKSEL_ABE_OFFSET
- OMAP4_CM_CLKSEL_CORE_OFFSET
- OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET
- OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET
- OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET
- OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET
- OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET
- OMAP4_CM_CLKSEL_DPLL_PER_OFFSET
- OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET
- OMAP4_CM_CLKSEL_DPLL_USB_OFFSET
- OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET
- OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET
- OMAP4_CM_CLKSTCTRL
- OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET
- OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET
- OMAP4_CM_CORE_DVFS_CURRENT_OFFSET
- OMAP4_CM_CORE_DVFS_PERF1_OFFSET
- OMAP4_CM_CORE_DVFS_PERF2_OFFSET
- OMAP4_CM_CORE_DVFS_PERF3_OFFSET
- OMAP4_CM_CORE_DVFS_PERF4_OFFSET
- OMAP4_CM_CPU0_CLKSTCTRL_OFFSET
- OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET
- OMAP4_CM_CPU1_CLKSTCTRL_OFFSET
- OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET
- OMAP4_CM_D2D_CLKSTCTRL_OFFSET
- OMAP4_CM_D2D_DYNAMICDEP_OFFSET
- OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET
- OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
- OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
- OMAP4_CM_D2D_STATICDEP_OFFSET
- OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET
- OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET
- OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET
- OMAP4_CM_DIV_M2_DPLL_PER_OFFSET
- OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET
- OMAP4_CM_DIV_M2_DPLL_USB_OFFSET
- OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET
- OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M3_DPLL_PER_OFFSET
- OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET
- OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET
- OMAP4_CM_DIV_M4_DPLL_PER_OFFSET
- OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET
- OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET
- OMAP4_CM_DIV_M5_DPLL_PER_OFFSET
- OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET
- OMAP4_CM_DIV_M6_DPLL_PER_OFFSET
- OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET
- OMAP4_CM_DIV_M7_DPLL_PER_OFFSET
- OMAP4_CM_DLL_CTRL_OFFSET
- OMAP4_CM_DSS_CLKSTCTRL_OFFSET
- OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET
- OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
- OMAP4_CM_DSS_DYNAMICDEP_OFFSET
- OMAP4_CM_DSS_STATICDEP_OFFSET
- OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET
- OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
- OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET
- OMAP4_CM_DUCATI_STATICDEP_OFFSET
- OMAP4_CM_DYN_DEP_PRESCAL_OFFSET
- OMAP4_CM_EMU_CLKSTCTRL_OFFSET
- OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
- OMAP4_CM_EMU_DYNAMICDEP_OFFSET
- OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET
- OMAP4_CM_GFX_CLKSTCTRL_OFFSET
- OMAP4_CM_GFX_DYNAMICDEP_OFFSET
- OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
- OMAP4_CM_GFX_STATICDEP_OFFSET
- OMAP4_CM_IDLEST_DPLL_ABE_OFFSET
- OMAP4_CM_IDLEST_DPLL_CORE_OFFSET
- OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET
- OMAP4_CM_IDLEST_DPLL_IVA_OFFSET
- OMAP4_CM_IDLEST_DPLL_MPU_OFFSET
- OMAP4_CM_IDLEST_DPLL_PER_OFFSET
- OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET
- OMAP4_CM_IDLEST_DPLL_USB_OFFSET
- OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET
- OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET
- OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
- OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
- OMAP4_CM_IVAHD_STATICDEP_OFFSET
- OMAP4_CM_IVA_DVFS_CURRENT_OFFSET
- OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET
- OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET
- OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET
- OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET
- OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET
- OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_STATICDEP_OFFSET
- OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
- OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET
- OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET
- OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
- OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
- OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
- OMAP4_CM_L3_1_CLKSTCTRL_OFFSET
- OMAP4_CM_L3_1_DYNAMICDEP_OFFSET
- OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
- OMAP4_CM_L3_2_CLKSTCTRL_OFFSET
- OMAP4_CM_L3_2_DYNAMICDEP_OFFSET
- OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
- OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
- OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
- OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET
- OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET
- OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
- OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
- OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
- OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_CLKSTCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_DYNAMICDEP_OFFSET
- OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
- OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET
- OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET
- OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET
- OMAP4_CM_L4SEC_STATICDEP_OFFSET
- OMAP4_CM_L4_WKUP_CLKSEL_OFFSET
- OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET
- OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET
- OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET
- OMAP4_CM_MPU_CLKSTCTRL_OFFSET
- OMAP4_CM_MPU_DYNAMICDEP_OFFSET
- OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
- OMAP4_CM_MPU_STATICDEP_OFFSET
- OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET
- OMAP4_CM_RESTORE_ST_OFFSET
- OMAP4_CM_SCALE_FCLK_OFFSET
- OMAP4_CM_SDMA_CLKSTCTRL_OFFSET
- OMAP4_CM_SDMA_DYNAMICDEP_OFFSET
- OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
- OMAP4_CM_SDMA_STATICDEP_OFFSET
- OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET
- OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET
- OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET
- OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET
- OMAP4_CM_STATICDEP
- OMAP4_CM_SYS_CLKSEL_OFFSET
- OMAP4_CM_TESLA_CLKSTCTRL_OFFSET
- OMAP4_CM_TESLA_DYNAMICDEP_OFFSET
- OMAP4_CM_TESLA_STATICDEP_OFFSET
- OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_CLKSTCTRL_OFFSET
- OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET
- OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
- OMAP4_COLDRST_MASK
- OMAP4_COLDRST_SHIFT
- OMAP4_COUNTER_32K_CLKCTRL
- OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR
- OMAP4_CTRL_MODULE_CORE_STATUS
- OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1
- OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX
- OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY
- OMAP4_CTRL_MODULE_PAD_WKUP
- OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2
- OMAP4_CTRL_MODULE_WKUP
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8
- OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9
- OMAP4_CTRL_MODULE_WKUP_IP_HWINFO
- OMAP4_CTRL_MODULE_WKUP_IP_REVISION
- OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG
- OMAP4_D2DWARMRSTST_MASK
- OMAP4_D2DWARMRSTST_SHIFT
- OMAP4_DEBUGSS_CLKCTRL
- OMAP4_DEF_CTRL_NOSOFTMODE
- OMAP4_DEF_CTRL_PTV_SHIFT
- OMAP4_DEF_IRQENABLE_EVENTEN
- OMAP4_DEF_IRQENABLE_LONGKEY
- OMAP4_DEF_WUP_EVENT_ENA
- OMAP4_DEF_WUP_LONG_KEY_ENA
- OMAP4_DISABLECLK_MASK
- OMAP4_DISABLECLK_SHIFT
- OMAP4_DMA_SYSTEM_CLKCTRL
- OMAP4_DMIC_CLKCTRL
- OMAP4_DMM_CLKCTRL
- OMAP4_DOWNTIME_MASK
- OMAP4_DOWNTIME_SHIFT
- OMAP4_DPLL_ABE_DEFFREQ
- OMAP4_DPLL_LP_FINT_MAX
- OMAP4_DPLL_LP_FOUT_MAX
- OMAP4_DPLL_USB_DEFFREQ
- OMAP4_DRAM_BARRIER_VA
- OMAP4_DSI1_LANEENABLE_MASK
- OMAP4_DSI1_LANEENABLE_SHIFT
- OMAP4_DSI1_PIPD_MASK
- OMAP4_DSI1_PIPD_SHIFT
- OMAP4_DSI2_LANEENABLE_MASK
- OMAP4_DSI2_LANEENABLE_SHIFT
- OMAP4_DSI2_PIPD_MASK
- OMAP4_DSI2_PIPD_SHIFT
- OMAP4_DSIPHY_SYSCON_OFFSET
- OMAP4_DSP_CLKCTRL
- OMAP4_DSS_CORE_CLKCTRL
- OMAP4_ELM_CLKCTRL
- OMAP4_EMIF1_CLKCTRL
- OMAP4_EMIF2_CLKCTRL
- OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK
- OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT
- OMAP4_ENABLE_EXT_MASK
- OMAP4_ENABLE_EXT_SHIFT
- OMAP4_ENABLE_INT_MASK
- OMAP4_ENABLE_INT_SHIFT
- OMAP4_ENABLE_MASK
- OMAP4_ENABLE_SHIFT
- OMAP4_EXTWARMRSTST_MASK
- OMAP4_EXTWARMRSTST_SHIFT
- OMAP4_FDIF_CLKCTRL
- OMAP4_GPIO1_CLKCTRL
- OMAP4_GPIO2_CLKCTRL
- OMAP4_GPIO3_CLKCTRL
- OMAP4_GPIO4_CLKCTRL
- OMAP4_GPIO5_CLKCTRL
- OMAP4_GPIO6_CLKCTRL
- OMAP4_GPIO_CLEARDATAOUT
- OMAP4_GPIO_CLEARIRQENABLE1
- OMAP4_GPIO_CLEARWKUENA
- OMAP4_GPIO_CTRL
- OMAP4_GPIO_DATAIN
- OMAP4_GPIO_DATAOUT
- OMAP4_GPIO_DEBOUNCENABLE
- OMAP4_GPIO_DEBOUNCINGTIME
- OMAP4_GPIO_DEBOUNCINGTIME_MASK
- OMAP4_GPIO_EOI
- OMAP4_GPIO_FALLINGDETECT
- OMAP4_GPIO_IRQENABLE1
- OMAP4_GPIO_IRQENABLE2
- OMAP4_GPIO_IRQSTATUS0
- OMAP4_GPIO_IRQSTATUS1
- OMAP4_GPIO_IRQSTATUS2
- OMAP4_GPIO_IRQSTATUSCLR0
- OMAP4_GPIO_IRQSTATUSCLR1
- OMAP4_GPIO_IRQSTATUSRAW0
- OMAP4_GPIO_IRQSTATUSRAW1
- OMAP4_GPIO_IRQSTATUSSET0
- OMAP4_GPIO_IRQSTATUSSET1
- OMAP4_GPIO_IRQWAKEN0
- OMAP4_GPIO_IRQWAKEN1
- OMAP4_GPIO_LEVELDETECT0
- OMAP4_GPIO_LEVELDETECT1
- OMAP4_GPIO_OE
- OMAP4_GPIO_REVISION
- OMAP4_GPIO_RISINGDETECT
- OMAP4_GPIO_SETDATAOUT
- OMAP4_GPIO_SETIRQENABLE1
- OMAP4_GPIO_SETWKUENA
- OMAP4_GPIO_WAKE_EN
- OMAP4_GPMC_CLKCTRL
- OMAP4_GPU_CLKCTRL
- OMAP4_HAL_SAVEALL_INDEX
- OMAP4_HAL_SAVEGIC_INDEX
- OMAP4_HAL_SAVEHW_INDEX
- OMAP4_HAL_SAVESECURERAM_INDEX
- OMAP4_HAS_FEATURE
- OMAP4_HAS_PERF_SILICON
- OMAP4_HDQ1W_CLKCTRL
- OMAP4_HSI_CLKCTRL
- OMAP4_I2C1_CLKCTRL
- OMAP4_I2C2_CLKCTRL
- OMAP4_I2C3_CLKCTRL
- OMAP4_I2C4_CLKCTRL
- OMAP4_I2C_CON_OFFSET
- OMAP4_IDLEST_MASK
- OMAP4_IDLEST_SHIFT
- OMAP4_IOPAD
- OMAP4_IPU_CLKCTRL
- OMAP4_IP_HWINFO_MASK
- OMAP4_IP_HWINFO_SHIFT
- OMAP4_IP_REV_CUSTOM_MASK
- OMAP4_IP_REV_CUSTOM_SHIFT
- OMAP4_IP_REV_FUNC_MASK
- OMAP4_IP_REV_FUNC_SHIFT
- OMAP4_IP_REV_MAJOR_MASK
- OMAP4_IP_REV_MAJOR_SHIFT
- OMAP4_IP_REV_MINOR_MASK
- OMAP4_IP_REV_MINOR_SHIFT
- OMAP4_IP_REV_RTL_MASK
- OMAP4_IP_REV_RTL_SHIFT
- OMAP4_IP_REV_SCHEME_MASK
- OMAP4_IP_REV_SCHEME_SHIFT
- OMAP4_IP_SYSCONFIG_IDLEMODE_MASK
- OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT
- OMAP4_ISS_CLKCTRL
- OMAP4_ISS_CSI2_H
- OMAP4_ISS_CSI_PHY_H
- OMAP4_ISS_IPIPEIF_H
- OMAP4_ISS_IPIPE_H
- OMAP4_ISS_ISP_SUBCLK_BL
- OMAP4_ISS_ISP_SUBCLK_H3A
- OMAP4_ISS_ISP_SUBCLK_IPIPE
- OMAP4_ISS_ISP_SUBCLK_IPIPEIF
- OMAP4_ISS_ISP_SUBCLK_ISIF
- OMAP4_ISS_ISP_SUBCLK_RSZ
- OMAP4_ISS_MEM_BTE
- OMAP4_ISS_MEM_CAMERARX_CORE1
- OMAP4_ISS_MEM_CAMERARX_CORE2
- OMAP4_ISS_MEM_CSI2_A_REGS1
- OMAP4_ISS_MEM_CSI2_B_REGS1
- OMAP4_ISS_MEM_ISP_IPIPE
- OMAP4_ISS_MEM_ISP_IPIPEIF
- OMAP4_ISS_MEM_ISP_ISIF
- OMAP4_ISS_MEM_ISP_RESIZER
- OMAP4_ISS_MEM_ISP_SYS1
- OMAP4_ISS_MEM_LAST
- OMAP4_ISS_MEM_TOP
- OMAP4_ISS_RESIZER_H
- OMAP4_ISS_SUBCLK_CCP2
- OMAP4_ISS_SUBCLK_CSI2_A
- OMAP4_ISS_SUBCLK_CSI2_B
- OMAP4_ISS_SUBCLK_ISP
- OMAP4_ISS_SUBCLK_SIMCOP
- OMAP4_ISS_VIDEO_H
- OMAP4_IVA_CLKCTRL
- OMAP4_KBD_CLKCTRL
- OMAP4_KBD_COLUMNOUTPUTS
- OMAP4_KBD_CTRL
- OMAP4_KBD_DEBOUNCINGTIME
- OMAP4_KBD_FULLCODE31_0
- OMAP4_KBD_FULLCODE63_32
- OMAP4_KBD_IRQENABLE
- OMAP4_KBD_IRQSTATUS
- OMAP4_KBD_LONGKEYTIME
- OMAP4_KBD_PENDING
- OMAP4_KBD_REVISION
- OMAP4_KBD_ROWINPUTS
- OMAP4_KBD_STATEMACHINE
- OMAP4_KBD_SYSCONFIG
- OMAP4_KBD_SYSSTATUS
- OMAP4_KBD_TIMEOUT
- OMAP4_KBD_WAKEUPENABLE
- OMAP4_KEYPAD_DEBOUNCINGTIME_MS
- OMAP4_KEYPAD_PTV_DIV_128
- OMAP4_L3_INSTR_CLKCTRL
- OMAP4_L3_IO_ADDRESS
- OMAP4_L3_IO_OFFSET
- OMAP4_L3_MAIN_1_CLKCTRL
- OMAP4_L3_MAIN_2_CLKCTRL
- OMAP4_L3_MAIN_3_CLKCTRL
- OMAP4_L3_PER_IO_ADDRESS
- OMAP4_L3_PER_IO_OFFSET
- OMAP4_L4_ABE_CLKCTRL
- OMAP4_L4_CFG_CLKCTRL
- OMAP4_L4_PER_CLKCTRL
- OMAP4_L4_WKUP_CLKCTRL
- OMAP4_MAILBOX_CLKCTRL
- OMAP4_MAILBOX_IRQENABLE
- OMAP4_MAILBOX_IRQENABLE_CLR
- OMAP4_MAILBOX_IRQSTATUS
- OMAP4_MAPPING_MASK
- OMAP4_MAPPING_SHIFT
- OMAP4_MAPPING_WIDTH
- OMAP4_MAX_MODULE_DISABLE_TIME
- OMAP4_MAX_MODULE_READY_TIME
- OMAP4_MAX_PRCM_PARTITIONS
- OMAP4_MCASP_CLKCTRL
- OMAP4_MCBSP1_CLKCTRL
- OMAP4_MCBSP2_CLKCTRL
- OMAP4_MCBSP3_CLKCTRL
- OMAP4_MCBSP4_CLKCTRL
- OMAP4_MCPDM_CLKCTRL
- OMAP4_MCSPI1_CLKCTRL
- OMAP4_MCSPI2_CLKCTRL
- OMAP4_MCSPI3_CLKCTRL
- OMAP4_MCSPI4_CLKCTRL
- OMAP4_MCSPI_REG_OFFSET
- OMAP4_MMC1_CLKCTRL
- OMAP4_MMC2_CLKCTRL
- OMAP4_MMC3_CLKCTRL
- OMAP4_MMC4_CLKCTRL
- OMAP4_MMC5_CLKCTRL
- OMAP4_MMC_REG_OFFSET
- OMAP4_MMU1_BASE
- OMAP4_MMU2_BASE
- OMAP4_MODEMWARMRSTST_MASK
- OMAP4_MODEMWARMRSTST_SHIFT
- OMAP4_MODULEMODE_MASK
- OMAP4_MON_L2X0_AUXCTRL_INDEX
- OMAP4_MON_L2X0_CTRL_INDEX
- OMAP4_MON_L2X0_DBG_CTRL_INDEX
- OMAP4_MON_L2X0_PREFETCH_INDEX
- OMAP4_MON_SCU_PWR_INDEX
- OMAP4_MPU_CLKCTRL
- OMAP4_NR_BANKS
- OMAP4_NR_IRQS
- OMAP4_OCMC_RAM_CLKCTRL
- OMAP4_OCP2SCP_USB_PHY_CLKCTRL
- OMAP4_OCP_WP_NOC_CLKCTRL
- OMAP4_OFF_VOLTAGE_UV
- OMAP4_ONLP_VOLTAGE_UV
- OMAP4_ON_VOLTAGE_UV
- OMAP4_P1_MODE_CLEAR
- OMAP4_P1_MODE_HSIC
- OMAP4_P1_MODE_TLL
- OMAP4_P2_MODE_CLEAR
- OMAP4_P2_MODE_HSIC
- OMAP4_P2_MODE_TLL
- OMAP4_PM_ABE_DMIC_WKDEP_OFFSET
- OMAP4_PM_ABE_MCASP_WKDEP_OFFSET
- OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET
- OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET
- OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET
- OMAP4_PM_ABE_PDM_WKDEP_OFFSET
- OMAP4_PM_ABE_PWRSTCTRL_OFFSET
- OMAP4_PM_ABE_PWRSTST_OFFSET
- OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET
- OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET
- OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET
- OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET
- OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET
- OMAP4_PM_ABE_WDT3_WKDEP_OFFSET
- OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET
- OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET
- OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET
- OMAP4_PM_CAM_PWRSTCTRL_OFFSET
- OMAP4_PM_CAM_PWRSTST_OFFSET
- OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET
- OMAP4_PM_CEFUSE_PWRSTST_OFFSET
- OMAP4_PM_CORE_PWRSTCTRL_OFFSET
- OMAP4_PM_CORE_PWRSTST_OFFSET
- OMAP4_PM_CPU0_PWRSTCTRL_OFFSET
- OMAP4_PM_CPU0_PWRSTST_OFFSET
- OMAP4_PM_CPU1_PWRSTCTRL_OFFSET
- OMAP4_PM_CPU1_PWRSTST_OFFSET
- OMAP4_PM_DSS_DSS_WKDEP_OFFSET
- OMAP4_PM_DSS_PWRSTCTRL_OFFSET
- OMAP4_PM_DSS_PWRSTST_OFFSET
- OMAP4_PM_EMU_PWRSTCTRL_OFFSET
- OMAP4_PM_EMU_PWRSTST_OFFSET
- OMAP4_PM_GFX_PWRSTCTRL_OFFSET
- OMAP4_PM_GFX_PWRSTST_OFFSET
- OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET
- OMAP4_PM_IVAHD_PWRSTST_OFFSET
- OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET
- OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET
- OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET
- OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET
- OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET
- OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET
- OMAP4_PM_L3INIT_PWRSTST_OFFSET
- OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET
- OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET
- OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET
- OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET
- OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET
- OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET
- OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET
- OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET
- OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET
- OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET
- OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET
- OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET
- OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET
- OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET
- OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET
- OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET
- OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET
- OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET
- OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET
- OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET
- OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET
- OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET
- OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET
- OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET
- OMAP4_PM_L4PER_PWRSTCTRL_OFFSET
- OMAP4_PM_L4PER_PWRSTST_OFFSET
- OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET
- OMAP4_PM_L4PER_UART1_WKDEP_OFFSET
- OMAP4_PM_L4PER_UART2_WKDEP_OFFSET
- OMAP4_PM_L4PER_UART3_WKDEP_OFFSET
- OMAP4_PM_L4PER_UART4_WKDEP_OFFSET
- OMAP4_PM_MPU_PWRSTCTRL_OFFSET
- OMAP4_PM_MPU_PWRSTST_OFFSET
- OMAP4_PM_PWSTCTRL
- OMAP4_PM_PWSTST
- OMAP4_PM_TESLA_PWRSTCTRL_OFFSET
- OMAP4_PM_TESLA_PWRSTST_OFFSET
- OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET
- OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET
- OMAP4_PM_WKUP_RTC_WKDEP_OFFSET
- OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET
- OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET
- OMAP4_PM_WKUP_USIM_WKDEP_OFFSET
- OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET
- OMAP4_POLARITY_MASK
- OMAP4_POLARITY_SHIFT
- OMAP4_PPA_CPU_ACTRL_SMP_INDEX
- OMAP4_PPA_L2_POR_INDEX
- OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET
- OMAP4_PRCM_MPU_PRM_RSTST_OFFSET
- OMAP4_PRM_CLKREQCTRL_OFFSET
- OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET
- OMAP4_PRM_IO_COUNT_OFFSET
- OMAP4_PRM_IO_PMCTRL_OFFSET
- OMAP4_PRM_IRQENABLE_DUCATI_OFFSET
- OMAP4_PRM_IRQENABLE_MPU_2_OFFSET
- OMAP4_PRM_IRQENABLE_MPU_OFFSET
- OMAP4_PRM_IRQENABLE_TESLA_OFFSET
- OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET
- OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET
- OMAP4_PRM_IRQSTATUS_MPU_OFFSET
- OMAP4_PRM_IRQSTATUS_TESLA_OFFSET
- OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET
- OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET
- OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET
- OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET
- OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET
- OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET
- OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET
- OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET
- OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET
- OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET
- OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET
- OMAP4_PRM_MODEM_IF_CTRL_OFFSET
- OMAP4_PRM_PHASE1_CNDP_OFFSET
- OMAP4_PRM_PHASE2A_CNDP_OFFSET
- OMAP4_PRM_PHASE2B_CNDP_OFFSET
- OMAP4_PRM_PSCON_COUNT_OFFSET
- OMAP4_PRM_PWRREQCTRL_OFFSET
- OMAP4_PRM_RSTCTRL_OFFSET
- OMAP4_PRM_RSTST_OFFSET
- OMAP4_PRM_RSTTIME_OFFSET
- OMAP4_PRM_SRAM_COUNT_OFFSET
- OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET
- OMAP4_PRM_VC_CFG_CHANNEL_OFFSET
- OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET
- OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET
- OMAP4_PRM_VC_ERRST_OFFSET
- OMAP4_PRM_VC_SMPS_SA_OFFSET
- OMAP4_PRM_VC_VAL_BYPASS_OFFSET
- OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET
- OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET
- OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET
- OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET
- OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET
- OMAP4_PRM_VOLTCTRL_OFFSET
- OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET
- OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET
- OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET
- OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET
- OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET
- OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET
- OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET
- OMAP4_PRM_VP_CORE_CONFIG_OFFSET
- OMAP4_PRM_VP_CORE_STATUS_OFFSET
- OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET
- OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET
- OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET
- OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET
- OMAP4_PRM_VP_IVA_CONFIG_OFFSET
- OMAP4_PRM_VP_IVA_STATUS_OFFSET
- OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET
- OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET
- OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET
- OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET
- OMAP4_PRM_VP_MPU_CONFIG_OFFSET
- OMAP4_PRM_VP_MPU_STATUS_OFFSET
- OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET
- OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET
- OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET
- OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET
- OMAP4_PWRONRST_MASK
- OMAP4_PWRONRST_SHIFT
- OMAP4_RET_VOLTAGE_UV
- OMAP4_REVISION_CM1_OFFSET
- OMAP4_REVISION_CM2_OFFSET
- OMAP4_REVISION_PRCM_OFFSET
- OMAP4_REVISION_PRM_OFFSET
- OMAP4_REV_MASK
- OMAP4_REV_SHIFT
- OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
- OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
- OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
- OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
- OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
- OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
- OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
- OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
- OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
- OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
- OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
- OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
- OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
- OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET
- OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
- OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
- OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
- OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
- OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
- OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET
- OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET
- OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET
- OMAP4_RM_CPU0_CPU0_RSTST_OFFSET
- OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET
- OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET
- OMAP4_RM_CPU1_CPU1_RSTST_OFFSET
- OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET
- OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
- OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
- OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET
- OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
- OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
- OMAP4_RM_DUCATI_RSTCTRL_OFFSET
- OMAP4_RM_DUCATI_RSTST_OFFSET
- OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
- OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
- OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
- OMAP4_RM_IVAHD_RSTCTRL_OFFSET
- OMAP4_RM_IVAHD_RSTST_OFFSET
- OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
- OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET
- OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
- OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
- OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
- OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
- OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
- OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
- OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
- OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
- OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
- OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
- OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET
- OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
- OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
- OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
- OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
- OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
- OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET
- OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
- OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET
- OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
- OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET
- OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
- OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
- OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
- OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET
- OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET
- OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET
- OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
- OMAP4_RM_MPU_RSTST_OFFSET
- OMAP4_RM_RSTCTRL
- OMAP4_RM_RSTST
- OMAP4_RM_RSTTIME
- OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
- OMAP4_RM_TESLA_RSTCTRL_OFFSET
- OMAP4_RM_TESLA_RSTST_OFFSET
- OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
- OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
- OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
- OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
- OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET
- OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET
- OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
- OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET
- OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
- OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET
- OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET
- OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
- OMAP4_RNG_OUTPUT_SIZE
- OMAP4_RSTTIME_MASK
- OMAP4_RSTTIME_SHIFT
- OMAP4_RST_CTRL_ST_OFFSET
- OMAP4_SCRM_ACCCLKREQ
- OMAP4_SCRM_ACCCLKREQ_OFFSET
- OMAP4_SCRM_ALTCLKSRC
- OMAP4_SCRM_ALTCLKSRC_OFFSET
- OMAP4_SCRM_APEWARMRSTST
- OMAP4_SCRM_APEWARMRSTST_OFFSET
- OMAP4_SCRM_AUXCLK0
- OMAP4_SCRM_AUXCLK0_OFFSET
- OMAP4_SCRM_AUXCLK1
- OMAP4_SCRM_AUXCLK1_OFFSET
- OMAP4_SCRM_AUXCLK2
- OMAP4_SCRM_AUXCLK2_OFFSET
- OMAP4_SCRM_AUXCLK3
- OMAP4_SCRM_AUXCLK3_OFFSET
- OMAP4_SCRM_AUXCLK4
- OMAP4_SCRM_AUXCLK4_OFFSET
- OMAP4_SCRM_AUXCLK5
- OMAP4_SCRM_AUXCLK5_OFFSET
- OMAP4_SCRM_AUXCLKREQ0
- OMAP4_SCRM_AUXCLKREQ0_OFFSET
- OMAP4_SCRM_AUXCLKREQ1
- OMAP4_SCRM_AUXCLKREQ1_OFFSET
- OMAP4_SCRM_AUXCLKREQ2
- OMAP4_SCRM_AUXCLKREQ2_OFFSET
- OMAP4_SCRM_AUXCLKREQ3
- OMAP4_SCRM_AUXCLKREQ3_OFFSET
- OMAP4_SCRM_AUXCLKREQ4
- OMAP4_SCRM_AUXCLKREQ4_OFFSET
- OMAP4_SCRM_AUXCLKREQ5
- OMAP4_SCRM_AUXCLKREQ5_OFFSET
- OMAP4_SCRM_BASE
- OMAP4_SCRM_CLKSETUPTIME
- OMAP4_SCRM_CLKSETUPTIME_OFFSET
- OMAP4_SCRM_D2DCLKM
- OMAP4_SCRM_D2DCLKM_OFFSET
- OMAP4_SCRM_D2DCLKREQ
- OMAP4_SCRM_D2DCLKREQ_OFFSET
- OMAP4_SCRM_D2DRSTCTRL
- OMAP4_SCRM_D2DRSTCTRL_OFFSET
- OMAP4_SCRM_D2DWARMRSTST
- OMAP4_SCRM_D2DWARMRSTST_OFFSET
- OMAP4_SCRM_EXTCLKREQ
- OMAP4_SCRM_EXTCLKREQ_OFFSET
- OMAP4_SCRM_EXTPWRONRSTCTRL
- OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET
- OMAP4_SCRM_EXTWARMRSTST
- OMAP4_SCRM_EXTWARMRSTST_OFFSET
- OMAP4_SCRM_MODEMCLKM
- OMAP4_SCRM_MODEMCLKM_OFFSET
- OMAP4_SCRM_MODEMRSTCTRL
- OMAP4_SCRM_MODEMRSTCTRL_OFFSET
- OMAP4_SCRM_MODEMWARMRSTST
- OMAP4_SCRM_MODEMWARMRSTST_OFFSET
- OMAP4_SCRM_PMICSETUPTIME
- OMAP4_SCRM_PMICSETUPTIME_OFFSET
- OMAP4_SCRM_PWRREQ
- OMAP4_SCRM_PWRREQ_OFFSET
- OMAP4_SCRM_REVISION_SCRM
- OMAP4_SCRM_REVISION_SCRM_OFFSET
- OMAP4_SCRM_RSTTIME
- OMAP4_SCRM_RSTTIME_OFFSET
- OMAP4_SETUPTIME_MASK
- OMAP4_SETUPTIME_SHIFT
- OMAP4_SILICON_TYPE_PERFORMANCE
- OMAP4_SILICON_TYPE_STANDARD
- OMAP4_SL2IF_CLKCTRL
- OMAP4_SLEEPTIME_MASK
- OMAP4_SLEEPTIME_SHIFT
- OMAP4_SLIMBUS1_CLKCTRL
- OMAP4_SLIMBUS2_CLKCTRL
- OMAP4_SMARTREFLEX_CORE_CLKCTRL
- OMAP4_SMARTREFLEX_IVA_CLKCTRL
- OMAP4_SMARTREFLEX_MPU_CLKCTRL
- OMAP4_SPINLOCK_CLKCTRL
- OMAP4_SRCSELECT_MASK
- OMAP4_SRCSELECT_SHIFT
- OMAP4_SRI2C_SLAVE_ADDR
- OMAP4_SYSCLK_MASK
- OMAP4_SYSCLK_SHIFT
- OMAP4_TIMER10_CLKCTRL
- OMAP4_TIMER11_CLKCTRL
- OMAP4_TIMER1_CLKCTRL
- OMAP4_TIMER2_CLKCTRL
- OMAP4_TIMER3_CLKCTRL
- OMAP4_TIMER4_CLKCTRL
- OMAP4_TIMER5_CLKCTRL
- OMAP4_TIMER6_CLKCTRL
- OMAP4_TIMER7_CLKCTRL
- OMAP4_TIMER8_CLKCTRL
- OMAP4_TIMER9_CLKCTRL
- OMAP4_UART1_BASE
- OMAP4_UART1_CLKCTRL
- OMAP4_UART2_BASE
- OMAP4_UART2_CLKCTRL
- OMAP4_UART2_RX
- OMAP4_UART3_BASE
- OMAP4_UART3_CLKCTRL
- OMAP4_UART3_RX
- OMAP4_UART4_BASE
- OMAP4_UART4_CLKCTRL
- OMAP4_UART4_RX
- OMAP4_UHH_HOSTCONFIG_APP_START_CLK
- OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR
- OMAP4_UHH_SYSCONFIG_NOIDLE
- OMAP4_UHH_SYSCONFIG_NOSTDBY
- OMAP4_UHH_SYSCONFIG_SOFTRESET
- OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR
- OMAP4_USB_HOST_FS_CLKCTRL
- OMAP4_USB_HOST_HS_CLKCTRL
- OMAP4_USB_OTG_HS_CLKCTRL
- OMAP4_USB_TLL_HS_CLKCTRL
- OMAP4_VAL_DEBOUNCINGTIME_16MS
- OMAP4_VAL_IRQDISABLE
- OMAP4_VDD_CORE_SR_CMD_REG
- OMAP4_VDD_CORE_SR_VOLT_REG
- OMAP4_VDD_IVA_SR_CMD_REG
- OMAP4_VDD_IVA_SR_VOLT_REG
- OMAP4_VDD_MPU_SR_CMD_REG
- OMAP4_VDD_MPU_SR_VOLT_REG
- OMAP4_VP_CONFIG_ERROROFFSET
- OMAP4_VP_CORE_VLIMITTO_VDDMAX
- OMAP4_VP_CORE_VLIMITTO_VDDMIN
- OMAP4_VP_IVA_VLIMITTO_VDDMAX
- OMAP4_VP_IVA_VLIMITTO_VDDMIN
- OMAP4_VP_MPU_VLIMITTO_VDDMAX
- OMAP4_VP_MPU_VLIMITTO_VDDMIN
- OMAP4_VP_VDD_CORE_ID
- OMAP4_VP_VDD_IVA_ID
- OMAP4_VP_VDD_MPU_ID
- OMAP4_VP_VLIMITTO_TIMEOUT_US
- OMAP4_VP_VSTEPMAX_VSTEPMAX
- OMAP4_VP_VSTEPMIN_VSTEPMIN
- OMAP4_WAKEUPTIME_MASK
- OMAP4_WAKEUPTIME_SHIFT
- OMAP4_WARMRST_MASK
- OMAP4_WARMRST_SHIFT
- OMAP4_WD_TIMER2_CLKCTRL
- OMAP4_WD_TIMER3_CLKCTRL
- OMAP4_WKUP_MODE_MASK
- OMAP4_WKUP_MODE_SHIFT
- OMAP5430_ADC_END_VALUE
- OMAP5430_ADC_START_VALUE
- OMAP5430_BGAP_CTRL_OFFSET
- OMAP5430_BGAP_DTEMP_CORE_1_OFFSET
- OMAP5430_BGAP_DTEMP_CORE_2_OFFSET
- OMAP5430_BGAP_DTEMP_GPU_1_OFFSET
- OMAP5430_BGAP_DTEMP_GPU_2_OFFSET
- OMAP5430_BGAP_DTEMP_MPU_1_OFFSET
- OMAP5430_BGAP_DTEMP_MPU_2_OFFSET
- OMAP5430_BGAP_STATUS_OFFSET
- OMAP5430_BGAP_TEMPSOFF_MASK
- OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK
- OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK
- OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK
- OMAP5430_BGAP_THRESHOLD_CORE_OFFSET
- OMAP5430_BGAP_THRESHOLD_GPU_OFFSET
- OMAP5430_BGAP_THRESHOLD_MPU_OFFSET
- OMAP5430_BGAP_TSHUT_CORE_OFFSET
- OMAP5430_BGAP_TSHUT_GPU_OFFSET
- OMAP5430_BGAP_TSHUT_MPU_OFFSET
- OMAP5430_COLD_CORE_FLAG_MASK
- OMAP5430_COLD_GPU_FLAG_MASK
- OMAP5430_COLD_MPU_FLAG_MASK
- OMAP5430_CORE_MAX_FREQ
- OMAP5430_CORE_MIN_FREQ
- OMAP5430_CORE_TSHUT_COLD
- OMAP5430_CORE_TSHUT_HOT
- OMAP5430_CORE_T_COLD
- OMAP5430_CORE_T_HOT
- OMAP5430_COUNTER_MASK
- OMAP5430_FUSE_OPP_BGAP_CORE
- OMAP5430_FUSE_OPP_BGAP_GPU
- OMAP5430_FUSE_OPP_BGAP_MPU
- OMAP5430_GPU_MAX_FREQ
- OMAP5430_GPU_MIN_FREQ
- OMAP5430_GPU_TSHUT_COLD
- OMAP5430_GPU_TSHUT_HOT
- OMAP5430_GPU_T_COLD
- OMAP5430_GPU_T_HOT
- OMAP5430_HOT_CORE_FLAG_MASK
- OMAP5430_HOT_GPU_FLAG_MASK
- OMAP5430_HOT_MPU_FLAG_MASK
- OMAP5430_MASK_COLD_CORE_MASK
- OMAP5430_MASK_COLD_GPU_MASK
- OMAP5430_MASK_COLD_MPU_MASK
- OMAP5430_MASK_COUNTER_DELAY_MASK
- OMAP5430_MASK_FREEZE_CORE_MASK
- OMAP5430_MASK_FREEZE_GPU_MASK
- OMAP5430_MASK_FREEZE_MPU_MASK
- OMAP5430_MASK_HOT_CORE_MASK
- OMAP5430_MASK_HOT_GPU_MASK
- OMAP5430_MASK_HOT_MPU_MASK
- OMAP5430_MPU_MAX_FREQ
- OMAP5430_MPU_MIN_FREQ
- OMAP5430_MPU_TSHUT_COLD
- OMAP5430_MPU_TSHUT_HOT
- OMAP5430_MPU_T_COLD
- OMAP5430_MPU_T_HOT
- OMAP5430_REV_ES2_0
- OMAP5430_TEMP_SENSOR_CORE_OFFSET
- OMAP5430_TEMP_SENSOR_GPU_OFFSET
- OMAP5430_TEMP_SENSOR_MPU_OFFSET
- OMAP5430_TSHUT_COLD_MASK
- OMAP5430_TSHUT_HOT_MASK
- OMAP5430_T_COLD_MASK
- OMAP5430_T_HOT_MASK
- OMAP5432_REV_ES2_0
- OMAP54XX_32KSYNCT_BASE
- OMAP54XX_ABE_STATDEP_SHIFT
- OMAP54XX_AUTO_DPLL_MODE_MASK
- OMAP54XX_CLASS
- OMAP54XX_CLKSEL_0_0_SHIFT
- OMAP54XX_CLKSEL_0_0_WIDTH
- OMAP54XX_CLKSEL_AESS_FCLK_SHIFT
- OMAP54XX_CLKSEL_AESS_FCLK_WIDTH
- OMAP54XX_CLKSEL_DIV_SHIFT
- OMAP54XX_CLKSEL_DIV_WIDTH
- OMAP54XX_CLKSEL_FCLK_SHIFT
- OMAP54XX_CLKSEL_FCLK_WIDTH
- OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT
- OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH
- OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT
- OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH
- OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT
- OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH
- OMAP54XX_CLKSEL_OPP_SHIFT
- OMAP54XX_CLKSEL_OPP_WIDTH
- OMAP54XX_CLKSEL_SHIFT
- OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT
- OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH
- OMAP54XX_CLKSEL_SOURCE_SHIFT
- OMAP54XX_CLKSEL_SOURCE_WIDTH
- OMAP54XX_CLKSEL_UTMI_P1_SHIFT
- OMAP54XX_CLKSEL_UTMI_P1_WIDTH
- OMAP54XX_CLKSEL_UTMI_P2_SHIFT
- OMAP54XX_CLKSEL_UTMI_P2_WIDTH
- OMAP54XX_CLKSEL_WIDTH
- OMAP54XX_CM_ABE_AESS_CLKCTRL
- OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET
- OMAP54XX_CM_ABE_DMIC_CLKCTRL
- OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_L4_ABE_CLKCTRL
- OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_MCASP_CLKCTRL
- OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_MCBSP1_CLKCTRL
- OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_MCBSP2_CLKCTRL
- OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_MCBSP3_CLKCTRL
- OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_MCPDM_CLKCTRL
- OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL
- OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_TIMER5_CLKCTRL
- OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_TIMER6_CLKCTRL
- OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_TIMER7_CLKCTRL
- OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_TIMER8_CLKCTRL
- OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET
- OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL
- OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_ABE
- OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_CORE
- OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_IVA
- OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_MPU
- OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_PER
- OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1
- OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2
- OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_AUTOIDLE_DPLL_USB
- OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET
- OMAP54XX_CM_BYPCLK_DPLL_IVA
- OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET
- OMAP54XX_CM_BYPCLK_DPLL_MPU
- OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET
- OMAP54XX_CM_C2C_C2C_CLKCTRL
- OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET
- OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL
- OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET
- OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET
- OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET
- OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL
- OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET
- OMAP54XX_CM_C2C_STATICDEP_OFFSET
- OMAP54XX_CM_CAM_CAL_CLKCTRL
- OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET
- OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET
- OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET
- OMAP54XX_CM_CAM_FDIF_CLKCTRL
- OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET
- OMAP54XX_CM_CAM_ISS_CLKCTRL
- OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET
- OMAP54XX_CM_CAM_STATICDEP_OFFSET
- OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1
- OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2
- OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_CLKDCOLDO_DPLL_USB
- OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_ABE
- OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_CORE
- OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_IVA
- OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_MPU
- OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_PER
- OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1
- OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2
- OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_CLKMODE_DPLL_USB
- OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET
- OMAP54XX_CM_CLKSEL_ABE
- OMAP54XX_CM_CLKSEL_ABE_DSS_SYS
- OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET
- OMAP54XX_CM_CLKSEL_ABE_OFFSET
- OMAP54XX_CM_CLKSEL_ABE_PLL_REF
- OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET
- OMAP54XX_CM_CLKSEL_CORE
- OMAP54XX_CM_CLKSEL_CORE_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_ABE
- OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_CORE
- OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_IVA
- OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_MPU
- OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_PER
- OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1
- OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2
- OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_CLKSEL_DPLL_USB
- OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET
- OMAP54XX_CM_CLKSEL_SYS
- OMAP54XX_CM_CLKSEL_SYS_OFFSET
- OMAP54XX_CM_CLKSEL_USB_60MHZ
- OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET
- OMAP54XX_CM_CLKSEL_WKUPAON
- OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET
- OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL
- OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET
- OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL
- OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET
- OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET
- OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL
- OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET
- OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL
- OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET
- OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL
- OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET
- OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL
- OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET
- OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL
- OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET
- OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS
- OMAP54XX_CM_CORE_AON_ABE_INST
- OMAP54XX_CM_CORE_AON_BASE
- OMAP54XX_CM_CORE_AON_CKGEN_INST
- OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET
- OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET
- OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS
- OMAP54XX_CM_CORE_AON_DSP_INST
- OMAP54XX_CM_CORE_AON_INSTR_INST
- OMAP54XX_CM_CORE_AON_MPU_INST
- OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS
- OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST
- OMAP54XX_CM_CORE_AON_PARTITION
- OMAP54XX_CM_CORE_AON_REGADDR
- OMAP54XX_CM_CORE_AON_RESTORE_INST
- OMAP54XX_CM_CORE_BASE
- OMAP54XX_CM_CORE_CAM_CAM_CDOFFS
- OMAP54XX_CM_CORE_CAM_INST
- OMAP54XX_CM_CORE_CKGEN_INST
- OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS
- OMAP54XX_CM_CORE_COREAON_INST
- OMAP54XX_CM_CORE_CORE_C2C_CDOFFS
- OMAP54XX_CM_CORE_CORE_DMA_CDOFFS
- OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS
- OMAP54XX_CM_CORE_CORE_INST
- OMAP54XX_CM_CORE_CORE_IPU_CDOFFS
- OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS
- OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS
- OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS
- OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS
- OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS
- OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS
- OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS
- OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS
- OMAP54XX_CM_CORE_CUSTEFUSE_INST
- OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET
- OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET
- OMAP54XX_CM_CORE_DSS_DSS_CDOFFS
- OMAP54XX_CM_CORE_DSS_INST
- OMAP54XX_CM_CORE_GPU_GPU_CDOFFS
- OMAP54XX_CM_CORE_GPU_INST
- OMAP54XX_CM_CORE_INSTR_INST
- OMAP54XX_CM_CORE_IVA_INST
- OMAP54XX_CM_CORE_IVA_IVA_CDOFFS
- OMAP54XX_CM_CORE_L3INIT_INST
- OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS
- OMAP54XX_CM_CORE_OCP_SOCKET_INST
- OMAP54XX_CM_CORE_PARTITION
- OMAP54XX_CM_CORE_REGADDR
- OMAP54XX_CM_CORE_RESTORE_INST
- OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET
- OMAP54XX_CM_CPU0_CPU0_CLKCTRL
- OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET
- OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET
- OMAP54XX_CM_CPU1_CPU1_CLKCTRL
- OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET
- OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET
- OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL
- OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET
- OMAP54XX_CM_DIV_H11_DPLL_CORE
- OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H11_DPLL_IVA
- OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET
- OMAP54XX_CM_DIV_H11_DPLL_PER
- OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET
- OMAP54XX_CM_DIV_H12_DPLL_CORE
- OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H12_DPLL_IVA
- OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET
- OMAP54XX_CM_DIV_H12_DPLL_PER
- OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET
- OMAP54XX_CM_DIV_H13_DPLL_CORE
- OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H13_DPLL_PER
- OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET
- OMAP54XX_CM_DIV_H14_DPLL_CORE
- OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H14_DPLL_PER
- OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET
- OMAP54XX_CM_DIV_H21_DPLL_CORE
- OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H22_DPLL_CORE
- OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H23_DPLL_CORE
- OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_H24_DPLL_CORE
- OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_ABE
- OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_CORE
- OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_MPU
- OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_PER
- OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1
- OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2
- OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_DIV_M2_DPLL_USB
- OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET
- OMAP54XX_CM_DIV_M3_DPLL_ABE
- OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET
- OMAP54XX_CM_DIV_M3_DPLL_CORE
- OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET
- OMAP54XX_CM_DIV_M3_DPLL_PER
- OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET
- OMAP54XX_CM_DLL_CTRL_OFFSET
- OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET
- OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL
- OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
- OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET
- OMAP54XX_CM_DMA_STATICDEP_OFFSET
- OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET
- OMAP54XX_CM_DSP_DSP_CLKCTRL
- OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET
- OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET
- OMAP54XX_CM_DSP_STATICDEP_OFFSET
- OMAP54XX_CM_DSS_BB2D_CLKCTRL
- OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET
- OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET
- OMAP54XX_CM_DSS_DSS_CLKCTRL
- OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
- OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET
- OMAP54XX_CM_DSS_STATICDEP_OFFSET
- OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET
- OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET
- OMAP54XX_CM_EMIF_DMM_CLKCTRL
- OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET
- OMAP54XX_CM_EMIF_EMIF1_CLKCTRL
- OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET
- OMAP54XX_CM_EMIF_EMIF2_CLKCTRL
- OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET
- OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL
- OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET
- OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL
- OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET
- OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET
- OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL
- OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
- OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET
- OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL
- OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET
- OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET
- OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET
- OMAP54XX_CM_GPU_GPU_CLKCTRL
- OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET
- OMAP54XX_CM_GPU_STATICDEP_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_ABE
- OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_CORE
- OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_IVA
- OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_MPU
- OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_PER
- OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_UNIPRO1
- OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_UNIPRO2
- OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_IDLEST_DPLL_USB
- OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET
- OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET
- OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET
- OMAP54XX_CM_IPU_IPU_CLKCTRL
- OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET
- OMAP54XX_CM_IPU_STATICDEP_OFFSET
- OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET
- OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET
- OMAP54XX_CM_IVA_IVA_CLKCTRL
- OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET
- OMAP54XX_CM_IVA_SL2_CLKCTRL
- OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET
- OMAP54XX_CM_IVA_STATICDEP_OFFSET
- OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L3INIT_HSI_CLKCTRL
- OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL
- OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_MMC1_CLKCTRL
- OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_MMC2_CLKCTRL
- OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL
- OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL
- OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL
- OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_SATA_CLKCTRL
- OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_STATICDEP_OFFSET
- OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL
- OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL
- OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL
- OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL
- OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL
- OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL
- OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL
- OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL
- OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET
- OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL
- OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET
- OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL
- OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
- OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL
- OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET
- OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL
- OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET
- OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL
- OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET
- OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL
- OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
- OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL
- OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
- OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL
- OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL
- OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET
- OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL
- OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L4PER_ELM_CLKCTRL
- OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO2_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO3_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO4_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO5_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO6_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO7_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_GPIO8_CLKCTRL
- OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL
- OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_I2C1_CLKCTRL
- OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_I2C2_CLKCTRL
- OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_I2C3_CLKCTRL
- OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_I2C4_CLKCTRL
- OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_I2C5_CLKCTRL
- OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_L4_PER_CLKCTRL
- OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL
- OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL
- OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL
- OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL
- OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MMC3_CLKCTRL
- OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MMC4_CLKCTRL
- OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_MMC5_CLKCTRL
- OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER10_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER11_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER2_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER3_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER4_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_TIMER9_CLKCTRL
- OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART1_CLKCTRL
- OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART2_CLKCTRL
- OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART3_CLKCTRL
- OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART4_CLKCTRL
- OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART5_CLKCTRL
- OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET
- OMAP54XX_CM_L4PER_UART6_CLKCTRL
- OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_AES1_CLKCTRL
- OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_AES2_CLKCTRL
- OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET
- OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL
- OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL
- OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET
- OMAP54XX_CM_L4SEC_FPKA_CLKCTRL
- OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_RNG_CLKCTRL
- OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL
- OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET
- OMAP54XX_CM_L4SEC_STATICDEP_OFFSET
- OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET
- OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET
- OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL
- OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET
- OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL
- OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET
- OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL
- OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET
- OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET
- OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET
- OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET
- OMAP54XX_CM_MPU_MPU_CLKCTRL
- OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET
- OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL
- OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET
- OMAP54XX_CM_MPU_STATICDEP_OFFSET
- OMAP54XX_CM_PRM_PROFILING_CLKCTRL
- OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET
- OMAP54XX_CM_RESTORE_ST_OFFSET
- OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET
- OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET
- OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET
- OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL
- OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL
- OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL
- OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_KBD_CLKCTRL
- OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL
- OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL
- OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL
- OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL
- OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL
- OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL
- OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET
- OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL
- OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
- OMAP54XX_CTRL_BASE
- OMAP54XX_DIVHS_0_4_MASK
- OMAP54XX_DIVHS_0_6_MASK
- OMAP54XX_DIVHS_MASK
- OMAP54XX_DMA_REQ_START
- OMAP54XX_DPLL_DIV_MASK
- OMAP54XX_DPLL_EN_MASK
- OMAP54XX_DPLL_LPMODE_EN_MASK
- OMAP54XX_DPLL_MULT_MASK
- OMAP54XX_DPLL_REGM4XEN_MASK
- OMAP54XX_DPLL_SD_DIV_MASK
- OMAP54XX_DSP_STATDEP_SHIFT
- OMAP54XX_DSS_STATDEP_SHIFT
- OMAP54XX_EMIF_STATDEP_SHIFT
- OMAP54XX_GPU_STATDEP_SHIFT
- OMAP54XX_IPU_STATDEP_SHIFT
- OMAP54XX_IRQ_GIC_START
- OMAP54XX_IVA_STATDEP_SHIFT
- OMAP54XX_L3INIT_STATDEP_SHIFT
- OMAP54XX_L3MAIN1_STATDEP_SHIFT
- OMAP54XX_L3MAIN2_STATDEP_SHIFT
- OMAP54XX_L4CFG_STATDEP_SHIFT
- OMAP54XX_L4PER_STATDEP_SHIFT
- OMAP54XX_L4SEC_STATDEP_SHIFT
- OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT
- OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_CLK32K_SHIFT
- OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT
- OMAP54XX_OPTFCLKEN_DBCLK_SHIFT
- OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT
- OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT
- OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT
- OMAP54XX_PAD_CLKS_GATE_SHIFT
- OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET
- OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET
- OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET
- OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET
- OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET
- OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET
- OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET
- OMAP54XX_PM_ABE_PWRSTST_OFFSET
- OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET
- OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET
- OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET
- OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET
- OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET
- OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET
- OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET
- OMAP54XX_PM_CAM_PWRSTST_OFFSET
- OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET
- OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET
- OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET
- OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET
- OMAP54XX_PM_CORE_PWRSTST_OFFSET
- OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET
- OMAP54XX_PM_CPU0_PWRSTST_OFFSET
- OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET
- OMAP54XX_PM_CPU1_PWRSTST_OFFSET
- OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET
- OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET
- OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET
- OMAP54XX_PM_DSP_PWRSTST_OFFSET
- OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET
- OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET
- OMAP54XX_PM_DSS_PWRSTST_OFFSET
- OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET
- OMAP54XX_PM_EMU_PWRSTST_OFFSET
- OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET
- OMAP54XX_PM_GPU_PWRSTST_OFFSET
- OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET
- OMAP54XX_PM_IVA_PWRSTST_OFFSET
- OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET
- OMAP54XX_PM_L3INIT_PWRSTST_OFFSET
- OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET
- OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET
- OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET
- OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET
- OMAP54XX_PM_MPU_PWRSTST_OFFSET
- OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET
- OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET
- OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET
- OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET
- OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET
- OMAP54XX_PRCM_MPU_BASE
- OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS
- OMAP54XX_PRCM_MPU_CM_C0_INST
- OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS
- OMAP54XX_PRCM_MPU_CM_C1_INST
- OMAP54XX_PRCM_MPU_DEVICE_INST
- OMAP54XX_PRCM_MPU_OCP_SOCKET_INST
- OMAP54XX_PRCM_MPU_PARTITION
- OMAP54XX_PRCM_MPU_PRM_C0_INST
- OMAP54XX_PRCM_MPU_PRM_C1_INST
- OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET
- OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET
- OMAP54XX_PRCM_MPU_REGADDR
- OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET
- OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET
- OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET
- OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET
- OMAP54XX_PRM_ABE_INST
- OMAP54XX_PRM_BANDGAP_SETUP_OFFSET
- OMAP54XX_PRM_BASE
- OMAP54XX_PRM_CAM_INST
- OMAP54XX_PRM_CKGEN_INST
- OMAP54XX_PRM_CLKREQCTRL_OFFSET
- OMAP54XX_PRM_COREAON_INST
- OMAP54XX_PRM_CORE_INST
- OMAP54XX_PRM_CUSTEFUSE_INST
- OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET
- OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET
- OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET
- OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET
- OMAP54XX_PRM_DEBUG_OUT_OFFSET
- OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET
- OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET
- OMAP54XX_PRM_DEVICE_INST
- OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET
- OMAP54XX_PRM_DSP_INST
- OMAP54XX_PRM_DSS_INST
- OMAP54XX_PRM_EMU_CM_EMU_CDOFFS
- OMAP54XX_PRM_EMU_CM_INST
- OMAP54XX_PRM_EMU_INST
- OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET
- OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET
- OMAP54XX_PRM_GPU_INST
- OMAP54XX_PRM_INSTR_INST
- OMAP54XX_PRM_IO_COUNT_OFFSET
- OMAP54XX_PRM_IO_PMCTRL_OFFSET
- OMAP54XX_PRM_IRQENABLE_DSP_OFFSET
- OMAP54XX_PRM_IRQENABLE_IPU_OFFSET
- OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET
- OMAP54XX_PRM_IRQENABLE_MPU_OFFSET
- OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET
- OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET
- OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET
- OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET
- OMAP54XX_PRM_IVA_INST
- OMAP54XX_PRM_L3INIT_INST
- OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET
- OMAP54XX_PRM_MPU_INST
- OMAP54XX_PRM_OCP_SOCKET_INST
- OMAP54XX_PRM_PARTITION
- OMAP54XX_PRM_PHASE1_CNDP_OFFSET
- OMAP54XX_PRM_PHASE2A_CNDP_OFFSET
- OMAP54XX_PRM_PHASE2B_CNDP_OFFSET
- OMAP54XX_PRM_PSCON_COUNT_OFFSET
- OMAP54XX_PRM_PWRREQCTRL_OFFSET
- OMAP54XX_PRM_REGADDR
- OMAP54XX_PRM_RSTCTRL_OFFSET
- OMAP54XX_PRM_RSTST_OFFSET
- OMAP54XX_PRM_RSTTIME_OFFSET
- OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET
- OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET
- OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET
- OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET
- OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET
- OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET
- OMAP54XX_PRM_SRAM_COUNT_OFFSET
- OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET
- OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET
- OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET
- OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET
- OMAP54XX_PRM_VC_CORE_ERRST_OFFSET
- OMAP54XX_PRM_VC_MM_ERRST_OFFSET
- OMAP54XX_PRM_VC_MPU_ERRST_OFFSET
- OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET
- OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET
- OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET
- OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET
- OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET
- OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET
- OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET
- OMAP54XX_PRM_VOLTCTRL_OFFSET
- OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET
- OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET
- OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET
- OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET
- OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET
- OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET
- OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET
- OMAP54XX_PRM_VOLTST_MM_OFFSET
- OMAP54XX_PRM_VOLTST_MPU_OFFSET
- OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET
- OMAP54XX_PRM_VP_CORE_STATUS_OFFSET
- OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET
- OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET
- OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET
- OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET
- OMAP54XX_PRM_VP_MM_CONFIG_OFFSET
- OMAP54XX_PRM_VP_MM_STATUS_OFFSET
- OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET
- OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET
- OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET
- OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET
- OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET
- OMAP54XX_PRM_VP_MPU_STATUS_OFFSET
- OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET
- OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET
- OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET
- OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET
- OMAP54XX_PRM_WKUPAON_CM_INST
- OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS
- OMAP54XX_PRM_WKUPAON_INST
- OMAP54XX_REVISION_CM_CORE_AON_OFFSET
- OMAP54XX_REVISION_CM_CORE_OFFSET
- OMAP54XX_REVISION_PRCM_MPU_OFFSET
- OMAP54XX_REVISION_PRM_OFFSET
- OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET
- OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET
- OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET
- OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET
- OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET
- OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET
- OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET
- OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET
- OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET
- OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET
- OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET
- OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET
- OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET
- OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET
- OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET
- OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET
- OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET
- OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET
- OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
- OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET
- OMAP54XX_RM_DSP_RSTCTRL_OFFSET
- OMAP54XX_RM_DSP_RSTST_OFFSET
- OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET
- OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET
- OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET
- OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET
- OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET
- OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET
- OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET
- OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET
- OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET
- OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET
- OMAP54XX_RM_IPU_RSTCTRL_OFFSET
- OMAP54XX_RM_IPU_RSTST_OFFSET
- OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET
- OMAP54XX_RM_IVA_RSTCTRL_OFFSET
- OMAP54XX_RM_IVA_RSTST_OFFSET
- OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET
- OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET
- OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
- OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET
- OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET
- OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
- OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET
- OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET
- OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET
- OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
- OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
- OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET
- OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET
- OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET
- OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET
- OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET
- OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET
- OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET
- OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET
- OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET
- OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
- OMAP54XX_SAR_RAM_BASE
- OMAP54XX_SCM_BASE
- OMAP54XX_SCRM_PARTITION
- OMAP54XX_SCRM_REGADDR
- OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT
- OMAP54XX_ST_DPLL_CLK_MASK
- OMAP54XX_SYS_CLKSEL_SHIFT
- OMAP54XX_SYS_CLKSEL_WIDTH
- OMAP54XX_WKUPAON_STATDEP_SHIFT
- OMAP5XXX_CONTROL_STATUS
- OMAP5_ACCURACY_MASK
- OMAP5_ACCURACY_SHIFT
- OMAP5_ACCURACY_WIDTH
- OMAP5_AMBA_IF_MODE_OFFSET
- OMAP5_APEWARMRSTST_MASK
- OMAP5_APEWARMRSTST_SHIFT
- OMAP5_APEWARMRSTST_WIDTH
- OMAP5_AUXCOREBOOT0_OFFSET
- OMAP5_AUXCOREBOOT1_OFFSET
- OMAP5_CLKCTRL_INDEX
- OMAP5_CLKCTRL_OFFSET
- OMAP5_CLKDIV_MASK
- OMAP5_CLKDIV_SHIFT
- OMAP5_CLKDIV_WIDTH
- OMAP5_CLK_32KHZ_MASK
- OMAP5_CLK_32KHZ_SHIFT
- OMAP5_CLK_32KHZ_WIDTH
- OMAP5_COLDRST_MASK
- OMAP5_COLDRST_SHIFT
- OMAP5_COLDRST_WIDTH
- OMAP5_CORE_COUNT
- OMAP5_COUNTER_32K_CLKCTRL
- OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET
- OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET
- OMAP5_D2DWARMRSTST_MASK
- OMAP5_D2DWARMRSTST_SHIFT
- OMAP5_D2DWARMRSTST_WIDTH
- OMAP5_DEVICETYPE_MASK
- OMAP5_DISABLECLK_MASK
- OMAP5_DISABLECLK_SHIFT
- OMAP5_DISABLECLK_WIDTH
- OMAP5_DMA_SYSTEM_CLKCTRL
- OMAP5_DMIC_CLKCTRL
- OMAP5_DMM_CLKCTRL
- OMAP5_DOWNTIME_MASK
- OMAP5_DOWNTIME_SHIFT
- OMAP5_DOWNTIME_WIDTH
- OMAP5_DPLL_ABE_DEFFREQ
- OMAP5_DPLL_USB_DEFFREQ
- OMAP5_DRA7_MON_SET_ACR_INDEX
- OMAP5_DRA7_MON_SET_CNTFRQ_INDEX
- OMAP5_DSI1_LANEENABLE_SHIFT
- OMAP5_DSI2_LANEENABLE_SHIFT
- OMAP5_DSIPHY_SYSCON_OFFSET
- OMAP5_DSI_LANEENABLE_MASK
- OMAP5_DSS_CORE_CLKCTRL
- OMAP5_EMIF1_CLKCTRL
- OMAP5_EMIF2_CLKCTRL
- OMAP5_ENABLE_0_0_MASK
- OMAP5_ENABLE_0_0_SHIFT
- OMAP5_ENABLE_0_0_WIDTH
- OMAP5_ENABLE_EXT_MASK
- OMAP5_ENABLE_EXT_SHIFT
- OMAP5_ENABLE_EXT_WIDTH
- OMAP5_ENABLE_INT_MASK
- OMAP5_ENABLE_INT_SHIFT
- OMAP5_ENABLE_INT_WIDTH
- OMAP5_ENABLE_MASK
- OMAP5_ENABLE_SHIFT
- OMAP5_ENABLE_WIDTH
- OMAP5_EXTWARMRSTST_MASK
- OMAP5_EXTWARMRSTST_SHIFT
- OMAP5_EXTWARMRSTST_WIDTH
- OMAP5_GPIO1_CLKCTRL
- OMAP5_GPIO2_CLKCTRL
- OMAP5_GPIO3_CLKCTRL
- OMAP5_GPIO4_CLKCTRL
- OMAP5_GPIO5_CLKCTRL
- OMAP5_GPIO6_CLKCTRL
- OMAP5_GPIO7_CLKCTRL
- OMAP5_GPIO8_CLKCTRL
- OMAP5_GPU_CLKCTRL
- OMAP5_I2C1_CLKCTRL
- OMAP5_I2C2_CLKCTRL
- OMAP5_I2C3_CLKCTRL
- OMAP5_I2C4_CLKCTRL
- OMAP5_I2C5_CLKCTRL
- OMAP5_IOPAD
- OMAP5_KBD_CLKCTRL
- OMAP5_L3_INSTR_CLKCTRL
- OMAP5_L3_MAIN_1_CLKCTRL
- OMAP5_L3_MAIN_2_CLKCTRL
- OMAP5_L3_MAIN_3_CLKCTRL
- OMAP5_L4_ABE_CLKCTRL
- OMAP5_L4_CFG_CLKCTRL
- OMAP5_L4_PER_CLKCTRL
- OMAP5_L4_WKUP_CLKCTRL
- OMAP5_LUT_OFFSET
- OMAP5_MAILBOX_CLKCTRL
- OMAP5_MAPPING_MASK
- OMAP5_MAPPING_SHIFT
- OMAP5_MAPPING_WIDTH
- OMAP5_MCBSP1_CLKCTRL
- OMAP5_MCBSP2_CLKCTRL
- OMAP5_MCBSP3_CLKCTRL
- OMAP5_MCPDM_CLKCTRL
- OMAP5_MCSPI1_CLKCTRL
- OMAP5_MCSPI2_CLKCTRL
- OMAP5_MCSPI3_CLKCTRL
- OMAP5_MCSPI4_CLKCTRL
- OMAP5_MMC1_CLKCTRL
- OMAP5_MMC2_CLKCTRL
- OMAP5_MMC3_CLKCTRL
- OMAP5_MMC4_CLKCTRL
- OMAP5_MMC5_CLKCTRL
- OMAP5_MMU_DSP_CLKCTRL
- OMAP5_MMU_IPU_CLKCTRL
- OMAP5_MODEMWARMRSTST_MASK
- OMAP5_MODEMWARMRSTST_SHIFT
- OMAP5_MODEMWARMRSTST_WIDTH
- OMAP5_MODE_MASK
- OMAP5_MODE_SHIFT
- OMAP5_MODE_WIDTH
- OMAP5_MON_AMBA_IF_INDEX
- OMAP5_MPU_CLKCTRL
- OMAP5_OCP2SCP1_CLKCTRL
- OMAP5_OCP2SCP3_CLKCTRL
- OMAP5_POLARITY_MASK
- OMAP5_POLARITY_SHIFT
- OMAP5_POLARITY_WIDTH
- OMAP5_PWRONRST_MASK
- OMAP5_PWRONRST_SHIFT
- OMAP5_PWRONRST_WIDTH
- OMAP5_REV_MASK
- OMAP5_REV_SHIFT
- OMAP5_REV_WIDTH
- OMAP5_RSTTIME_MASK
- OMAP5_RSTTIME_SHIFT
- OMAP5_RSTTIME_WIDTH
- OMAP5_SAR_BACKUP_STATUS_OFFSET
- OMAP5_SATA_CLKCTRL
- OMAP5_SCRM_ACCCLKREQ
- OMAP5_SCRM_ACCCLKREQ_OFFSET
- OMAP5_SCRM_ALTCLKSRC
- OMAP5_SCRM_ALTCLKSRC_OFFSET
- OMAP5_SCRM_APEWARMRSTST
- OMAP5_SCRM_APEWARMRSTST_OFFSET
- OMAP5_SCRM_AUXCLK0
- OMAP5_SCRM_AUXCLK0_OFFSET
- OMAP5_SCRM_AUXCLK1
- OMAP5_SCRM_AUXCLK1_OFFSET
- OMAP5_SCRM_AUXCLK2
- OMAP5_SCRM_AUXCLK2_OFFSET
- OMAP5_SCRM_AUXCLK3
- OMAP5_SCRM_AUXCLK3_OFFSET
- OMAP5_SCRM_AUXCLK4
- OMAP5_SCRM_AUXCLK4_OFFSET
- OMAP5_SCRM_AUXCLK5
- OMAP5_SCRM_AUXCLK5_OFFSET
- OMAP5_SCRM_AUXCLKREQ0
- OMAP5_SCRM_AUXCLKREQ0_OFFSET
- OMAP5_SCRM_AUXCLKREQ1
- OMAP5_SCRM_AUXCLKREQ1_OFFSET
- OMAP5_SCRM_AUXCLKREQ2
- OMAP5_SCRM_AUXCLKREQ2_OFFSET
- OMAP5_SCRM_AUXCLKREQ3
- OMAP5_SCRM_AUXCLKREQ3_OFFSET
- OMAP5_SCRM_AUXCLKREQ4
- OMAP5_SCRM_AUXCLKREQ4_OFFSET
- OMAP5_SCRM_AUXCLKREQ5
- OMAP5_SCRM_AUXCLKREQ5_OFFSET
- OMAP5_SCRM_BASE
- OMAP5_SCRM_CLKSETUPTIME
- OMAP5_SCRM_CLKSETUPTIME_OFFSET
- OMAP5_SCRM_D2DCLKM
- OMAP5_SCRM_D2DCLKM_OFFSET
- OMAP5_SCRM_D2DCLKREQ
- OMAP5_SCRM_D2DCLKREQ_OFFSET
- OMAP5_SCRM_D2DRSTCTRL
- OMAP5_SCRM_D2DRSTCTRL_OFFSET
- OMAP5_SCRM_D2DWARMRSTST
- OMAP5_SCRM_D2DWARMRSTST_OFFSET
- OMAP5_SCRM_EXTCLKREQ
- OMAP5_SCRM_EXTCLKREQ_OFFSET
- OMAP5_SCRM_EXTPWRONRSTCTRL
- OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET
- OMAP5_SCRM_EXTWARMRSTST
- OMAP5_SCRM_EXTWARMRSTST_OFFSET
- OMAP5_SCRM_MODEMCLKM
- OMAP5_SCRM_MODEMCLKM_OFFSET
- OMAP5_SCRM_MODEMRSTCTRL
- OMAP5_SCRM_MODEMRSTCTRL_OFFSET
- OMAP5_SCRM_MODEMWARMRSTST
- OMAP5_SCRM_MODEMWARMRSTST_OFFSET
- OMAP5_SCRM_PMICSETUPTIME
- OMAP5_SCRM_PMICSETUPTIME_OFFSET
- OMAP5_SCRM_PWRREQ
- OMAP5_SCRM_PWRREQ_OFFSET
- OMAP5_SCRM_REVISION_SCRM
- OMAP5_SCRM_REVISION_SCRM_OFFSET
- OMAP5_SCRM_RSTTIME
- OMAP5_SCRM_RSTTIME_OFFSET
- OMAP5_SETUPTIME_MASK
- OMAP5_SETUPTIME_SHIFT
- OMAP5_SETUPTIME_WIDTH
- OMAP5_SLEEPTIME_MASK
- OMAP5_SLEEPTIME_SHIFT
- OMAP5_SLEEPTIME_WIDTH
- OMAP5_SPINLOCK_CLKCTRL
- OMAP5_SRCSELECT_MASK
- OMAP5_SRCSELECT_SHIFT
- OMAP5_SRCSELECT_WIDTH
- OMAP5_SYSCLK_MASK
- OMAP5_SYSCLK_SHIFT
- OMAP5_SYSCLK_WIDTH
- OMAP5_TIMER10_CLKCTRL
- OMAP5_TIMER11_CLKCTRL
- OMAP5_TIMER1_CLKCTRL
- OMAP5_TIMER2_CLKCTRL
- OMAP5_TIMER3_CLKCTRL
- OMAP5_TIMER4_CLKCTRL
- OMAP5_TIMER5_CLKCTRL
- OMAP5_TIMER6_CLKCTRL
- OMAP5_TIMER7_CLKCTRL
- OMAP5_TIMER8_CLKCTRL
- OMAP5_TIMER9_CLKCTRL
- OMAP5_UART1_BASE
- OMAP5_UART1_CLKCTRL
- OMAP5_UART2_BASE
- OMAP5_UART2_CLKCTRL
- OMAP5_UART3_BASE
- OMAP5_UART3_CLKCTRL
- OMAP5_UART4_BASE
- OMAP5_UART4_CLKCTRL
- OMAP5_UART5_BASE
- OMAP5_UART5_CLKCTRL
- OMAP5_UART6_BASE
- OMAP5_UART6_CLKCTRL
- OMAP5_USB_HOST_HS_CLKCTRL
- OMAP5_USB_OTG_SS_CLKCTRL
- OMAP5_USB_TLL_HS_CLKCTRL
- OMAP5_WAKEUPGENENB_OFFSET_CPU0
- OMAP5_WAKEUPGENENB_OFFSET_CPU1
- OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0
- OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1
- OMAP5_WAKEUPTIME_MASK
- OMAP5_WAKEUPTIME_SHIFT
- OMAP5_WAKEUPTIME_WIDTH
- OMAP5_WARMRST_MASK
- OMAP5_WARMRST_SHIFT
- OMAP5_WARMRST_WIDTH
- OMAP5_WD_TIMER2_CLKCTRL
- OMAP7XX_CONFIG_BASE
- OMAP7XX_DSPREG_BASE
- OMAP7XX_DSPREG_SIZE
- OMAP7XX_DSPREG_START
- OMAP7XX_DSP_BASE
- OMAP7XX_DSP_MMU_BASE
- OMAP7XX_DSP_M_CTL
- OMAP7XX_DSP_SIZE
- OMAP7XX_DSP_START
- OMAP7XX_FLASH_ACFG_0
- OMAP7XX_FLASH_ACFG_1
- OMAP7XX_FLASH_CFG_0
- OMAP7XX_FLASH_CFG_1
- OMAP7XX_GPIO1_BASE
- OMAP7XX_GPIO2_BASE
- OMAP7XX_GPIO3_BASE
- OMAP7XX_GPIO4_BASE
- OMAP7XX_GPIO5_BASE
- OMAP7XX_GPIO6_BASE
- OMAP7XX_GPIO_DATA_INPUT
- OMAP7XX_GPIO_DATA_OUTPUT
- OMAP7XX_GPIO_DIR_CONTROL
- OMAP7XX_GPIO_INT_CONTROL
- OMAP7XX_GPIO_INT_MASK
- OMAP7XX_GPIO_INT_STATUS
- OMAP7XX_ICR_BASE
- OMAP7XX_IDLECT1_SLEEP_VAL
- OMAP7XX_IDLECT2_SLEEP_VAL
- OMAP7XX_IDLECT3
- OMAP7XX_IDLECT3_VAL
- OMAP7XX_IDLE_LOOP_REQUEST
- OMAP7XX_IO_CONF_0
- OMAP7XX_IO_CONF_1
- OMAP7XX_IO_CONF_10
- OMAP7XX_IO_CONF_11
- OMAP7XX_IO_CONF_12
- OMAP7XX_IO_CONF_13
- OMAP7XX_IO_CONF_2
- OMAP7XX_IO_CONF_3
- OMAP7XX_IO_CONF_4
- OMAP7XX_IO_CONF_5
- OMAP7XX_IO_CONF_6
- OMAP7XX_IO_CONF_7
- OMAP7XX_IO_CONF_8
- OMAP7XX_IO_CONF_9
- OMAP7XX_MCBSP1_BASE
- OMAP7XX_MCBSP2_BASE
- OMAP7XX_MCBSP_COUNT
- OMAP7XX_MCBSP_RES_SZ
- OMAP7XX_MODE2_OFFSET
- OMAP7XX_MODE_1
- OMAP7XX_MODE_2
- OMAP7XX_PCC_UPLD_CTRL
- OMAP7XX_PCC_UPLD_CTRL_BASE
- OMAP7XX_PINS_SZ
- OMAP7XX_PORT_SHIFT
- OMAP7XX_SPI1_BASE
- OMAP7XX_SPI2_BASE
- OMAPBL_MAX_INTENSITY
- OMAPDSS_DRIVE_SIG_FALLING_EDGE
- OMAPDSS_DRIVE_SIG_RISING_EDGE
- OMAPDSS_SIG_ACTIVE_HIGH
- OMAPDSS_SIG_ACTIVE_LOW
- OMAPDSS_VER_AM35xx
- OMAPDSS_VER_AM43xx
- OMAPDSS_VER_DRA7xx
- OMAPDSS_VER_OMAP24xx
- OMAPDSS_VER_OMAP34xx_ES1
- OMAPDSS_VER_OMAP34xx_ES3
- OMAPDSS_VER_OMAP3630
- OMAPDSS_VER_OMAP4
- OMAPDSS_VER_OMAP4430_ES1
- OMAPDSS_VER_OMAP4430_ES2
- OMAPDSS_VER_OMAP5
- OMAPDSS_VER_UNKNOWN
- OMAPFB_ACTIVE
- OMAPFB_AUTO_UPDATE
- OMAPFB_CAPS_GENERIC_MASK
- OMAPFB_CAPS_LCDC_MASK
- OMAPFB_CAPS_MANUAL_UPDATE
- OMAPFB_CAPS_PANEL_MASK
- OMAPFB_CAPS_PLANE_RELOCATE_MEM
- OMAPFB_CAPS_PLANE_SCALE
- OMAPFB_CAPS_SET_BACKLIGHT
- OMAPFB_CAPS_TEARSYNC
- OMAPFB_CAPS_WINDOW_OVERLAY
- OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE
- OMAPFB_CAPS_WINDOW_ROTATE
- OMAPFB_CAPS_WINDOW_SCALE
- OMAPFB_CHANNEL_OUT_DIGIT
- OMAPFB_CHANNEL_OUT_LCD
- OMAPFB_COLOR_ARGB16
- OMAPFB_COLOR_ARGB32
- OMAPFB_COLOR_CLUT_1BPP
- OMAPFB_COLOR_CLUT_2BPP
- OMAPFB_COLOR_CLUT_4BPP
- OMAPFB_COLOR_CLUT_8BPP
- OMAPFB_COLOR_KEY_DISABLED
- OMAPFB_COLOR_KEY_GFX_DST
- OMAPFB_COLOR_KEY_VID_SRC
- OMAPFB_COLOR_RGB24P
- OMAPFB_COLOR_RGB24U
- OMAPFB_COLOR_RGB444
- OMAPFB_COLOR_RGB565
- OMAPFB_COLOR_RGBA32
- OMAPFB_COLOR_RGBX32
- OMAPFB_COLOR_YUV420
- OMAPFB_COLOR_YUV422
- OMAPFB_COLOR_YUY422
- OMAPFB_CTRL_TEST
- OMAPFB_DISABLED
- OMAPFB_EVENT_DISABLED
- OMAPFB_EVENT_READY
- OMAPFB_FORMAT_FLAG_DISABLE_OVERLAY
- OMAPFB_FORMAT_FLAG_DOUBLE
- OMAPFB_FORMAT_FLAG_ENABLE_OVERLAY
- OMAPFB_FORMAT_FLAG_FORCE_VSYNC
- OMAPFB_FORMAT_FLAG_TEARSYNC
- OMAPFB_FORMAT_MASK
- OMAPFB_GET_CAPS
- OMAPFB_GET_COLOR_KEY
- OMAPFB_GET_DISPLAY_INFO
- OMAPFB_GET_OVERLAY_COLORMODE
- OMAPFB_GET_UPDATE_MODE
- OMAPFB_GET_VRAM_INFO
- OMAPFB_LCD_TEST
- OMAPFB_MANUAL_UPDATE
- OMAPFB_MAX_OVL_PER_FB
- OMAPFB_MEMORY_READ
- OMAPFB_MEMTYPE_MAX
- OMAPFB_MEMTYPE_SDRAM
- OMAPFB_MEMTYPE_SRAM
- OMAPFB_MEM_IDX_ENABLED
- OMAPFB_MEM_IDX_MASK
- OMAPFB_MIRROR
- OMAPFB_PLANE_GFX
- OMAPFB_PLANE_NUM
- OMAPFB_PLANE_VID1
- OMAPFB_PLANE_VID2
- OMAPFB_PLANE_XRES_MIN
- OMAPFB_PLANE_YRES_MIN
- OMAPFB_QUERY_MEM
- OMAPFB_QUERY_PLANE
- OMAPFB_SETUP_MEM
- OMAPFB_SETUP_PLANE
- OMAPFB_SET_COLOR_KEY
- OMAPFB_SET_TEARSYNC
- OMAPFB_SET_UPDATE_MODE
- OMAPFB_SUSPENDED
- OMAPFB_SYNC_GFX
- OMAPFB_UPDATE_DISABLED
- OMAPFB_UPDATE_WINDOW
- OMAPFB_UPDATE_WINDOW_OLD
- OMAPFB_VSYNC
- OMAPFB_WAITFORGO
- OMAPFB_WAITFORVSYNC
- OMAP_16XX_WATCHDOG_BASE
- OMAP_16XX_WCLR
- OMAP_16XX_WCRR
- OMAP_16XX_WD_SYSCONFIG
- OMAP_16XX_WD_SYSSTATUS
- OMAP_16XX_WIDR
- OMAP_16XX_WLDR
- OMAP_16XX_WSPR
- OMAP_16XX_WTGR
- OMAP_16XX_WWPS
- OMAP_32K_TICKS_PER_SEC
- OMAP_32K_TIMER_TICK_PERIOD
- OMAP_AES_CACHE_SIZE
- OMAP_AES_QUEUE_LENGTH
- OMAP_ALIGNED
- OMAP_ALIGN_MASK
- OMAP_AMBA_IF_MODE
- OMAP_ARCH_OMAP4_SAR_LAYOUT_H
- OMAP_ARCH_OMAP_SECURE_H
- OMAP_ARCH_WAKEUPGEN_H
- OMAP_AUTOEXTCLKMODE_MASK
- OMAP_AUTOEXTCLKMODE_SHIFT
- OMAP_AUX_CORE_BOOT_0
- OMAP_AUX_CORE_BOOT_1
- OMAP_BO_CACHED
- OMAP_BO_CACHE_MASK
- OMAP_BO_MEM_DMABUF
- OMAP_BO_MEM_DMA_API
- OMAP_BO_MEM_SHMEM
- OMAP_BO_SCANOUT
- OMAP_BO_TILED
- OMAP_BO_TILED_16
- OMAP_BO_TILED_32
- OMAP_BO_TILED_8
- OMAP_BO_TILED_MASK
- OMAP_BO_UNCACHED
- OMAP_BO_USER_MASK
- OMAP_BO_WC
- OMAP_BULK_EP
- OMAP_C2C_RST_SRC_ID_SHIFT
- OMAP_CLKSEL_GFX_MASK
- OMAP_CLKSEL_GFX_SHIFT
- OMAP_CLKSEL_GFX_WIDTH
- OMAP_CONSOLE
- OMAP_COREDOMAINWKUP_RST_MASK
- OMAP_CPUIDLE_CX_NO_CLKDM_IDLE
- OMAP_CRYPTO_BAD_DATA_LENGTH
- OMAP_CRYPTO_COPY_DATA
- OMAP_CRYPTO_COPY_MASK
- OMAP_CRYPTO_DATA_COPIED
- OMAP_CRYPTO_FORCE_COPY
- OMAP_CRYPTO_FORCE_SINGLE_ENTRY
- OMAP_CRYPTO_NOT_ALIGNED
- OMAP_CRYPTO_SG_COPIED
- OMAP_CRYPTO_ZERO_BUF
- OMAP_CS0_PHYS
- OMAP_CS0_SIZE
- OMAP_CS1A_PHYS
- OMAP_CS1A_SIZE
- OMAP_CS1B_PHYS
- OMAP_CS1B_SIZE
- OMAP_CS1_PHYS
- OMAP_CS1_SIZE
- OMAP_CS2A_PHYS
- OMAP_CS2A_SIZE
- OMAP_CS2B_PHYS
- OMAP_CS2B_SIZE
- OMAP_CS2_PHYS
- OMAP_CS2_SIZE
- OMAP_CS3_PHYS
- OMAP_CS3_SIZE
- OMAP_CTRL_DEV_AVALID
- OMAP_CTRL_DEV_BVALID
- OMAP_CTRL_DEV_IDDIG
- OMAP_CTRL_DEV_PHY_PD
- OMAP_CTRL_DEV_SESSEND
- OMAP_CTRL_DEV_VBUSVALID
- OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT
- OMAP_CTRL_PCIE_PCS_MASK
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK
- OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT
- OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF
- OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON
- OMAP_CTRL_TYPE_AM437USB2
- OMAP_CTRL_TYPE_DRA7USB2
- OMAP_CTRL_TYPE_OTGHS
- OMAP_CTRL_TYPE_PCIE
- OMAP_CTRL_TYPE_PIPE3
- OMAP_CTRL_TYPE_USB2
- OMAP_CTRL_USB2_PHY_PD
- OMAP_DES_CACHE_SIZE
- OMAP_DES_QUEUE_LENGTH
- OMAP_DEVICE_STATE_ENABLED
- OMAP_DEVICE_STATE_IDLE
- OMAP_DEVICE_STATE_SHUTDOWN
- OMAP_DEVICE_STATE_UNKNOWN
- OMAP_DEVICE_SUSPENDED
- OMAP_DEV_PHY_PD
- OMAP_DIE_ID_0
- OMAP_DIE_ID_1
- OMAP_DISPLAY_TYPE_DBI
- OMAP_DISPLAY_TYPE_DPI
- OMAP_DISPLAY_TYPE_DSI
- OMAP_DISPLAY_TYPE_DVI
- OMAP_DISPLAY_TYPE_HDMI
- OMAP_DISPLAY_TYPE_NONE
- OMAP_DISPLAY_TYPE_SDI
- OMAP_DISPLAY_TYPE_VENC
- OMAP_DMA_ACTIVE
- OMAP_DMA_AMODE_CONSTANT
- OMAP_DMA_AMODE_DOUBLE_IDX
- OMAP_DMA_AMODE_POST_INC
- OMAP_DMA_AMODE_SINGLE_IDX
- OMAP_DMA_BIG_ENDIAN
- OMAP_DMA_BLOCK_IRQ
- OMAP_DMA_BUSWIDTHS
- OMAP_DMA_CCR_BUFFERING_DISABLE
- OMAP_DMA_CCR_EN
- OMAP_DMA_CCR_RD_ACTIVE
- OMAP_DMA_CCR_SEL_SRC_DST_SYNC
- OMAP_DMA_CCR_WR_ACTIVE
- OMAP_DMA_CHAIN_ACTIVE
- OMAP_DMA_CHAIN_INACTIVE
- OMAP_DMA_CHAIN_INCQHEAD
- OMAP_DMA_CHAIN_INCQTAIL
- OMAP_DMA_CHAIN_QEMPTY
- OMAP_DMA_CHAIN_QFULL
- OMAP_DMA_CHAIN_QINIT
- OMAP_DMA_CHAIN_QLAST
- OMAP_DMA_COLOR_DIS
- OMAP_DMA_CONSTANT_FILL
- OMAP_DMA_DATA_BURST_16
- OMAP_DMA_DATA_BURST_4
- OMAP_DMA_DATA_BURST_8
- OMAP_DMA_DATA_BURST_DIS
- OMAP_DMA_DATA_TYPE_S16
- OMAP_DMA_DATA_TYPE_S32
- OMAP_DMA_DATA_TYPE_S8
- OMAP_DMA_DROP_IRQ
- OMAP_DMA_DST_SYNC
- OMAP_DMA_DST_SYNC_PREFETCH
- OMAP_DMA_DYNAMIC_CHAIN
- OMAP_DMA_FRAME_IRQ
- OMAP_DMA_HALF_IRQ
- OMAP_DMA_LAST_IRQ
- OMAP_DMA_LCD_CCR
- OMAP_DMA_LCD_CTRL
- OMAP_DMA_LCH_2D
- OMAP_DMA_LCH_G
- OMAP_DMA_LCH_P
- OMAP_DMA_LCH_PD
- OMAP_DMA_LITTLE_ENDIAN
- OMAP_DMA_NO_DEVICE
- OMAP_DMA_PORT_EMIFF
- OMAP_DMA_PORT_EMIFS
- OMAP_DMA_PORT_MPUI
- OMAP_DMA_PORT_OCP_T1
- OMAP_DMA_PORT_OCP_T2
- OMAP_DMA_PORT_TIPB
- OMAP_DMA_REG_16BIT
- OMAP_DMA_REG_2X16BIT
- OMAP_DMA_REG_32BIT
- OMAP_DMA_REG_NONE
- OMAP_DMA_SRC_SYNC
- OMAP_DMA_STATIC_CHAIN
- OMAP_DMA_SYNC_BLOCK
- OMAP_DMA_SYNC_ELEMENT
- OMAP_DMA_SYNC_FRAME
- OMAP_DMA_SYNC_PACKET
- OMAP_DMA_TRANSPARENT_COPY
- OMAP_DMA_TX_KICK
- OMAP_DMA_USB_W2FC_RX0
- OMAP_DMA_USB_W2FC_TX0
- OMAP_DMA_WRITE_LAST_NON_POSTED
- OMAP_DMA_WRITE_NON_POSTED
- OMAP_DMA_WRITE_POSTED
- OMAP_DMICOUTFORMAT_LJUST
- OMAP_DMICOUTFORMAT_RJUST
- OMAP_DMIC_ABE_DMIC_CLK
- OMAP_DMIC_CLK_DIV
- OMAP_DMIC_CLK_DIV_MASK
- OMAP_DMIC_CTRL_REG
- OMAP_DMIC_DATA_REG
- OMAP_DMIC_DMAENABLE_CLR_REG
- OMAP_DMIC_DMAENABLE_SET_REG
- OMAP_DMIC_DMAWAKEEN_REG
- OMAP_DMIC_DMA_ENABLE
- OMAP_DMIC_FIFO_CTRL_REG
- OMAP_DMIC_FIFO_DMIC1L_DATA_REG
- OMAP_DMIC_FIFO_DMIC1R_DATA_REG
- OMAP_DMIC_FIFO_DMIC2L_DATA_REG
- OMAP_DMIC_FIFO_DMIC2R_DATA_REG
- OMAP_DMIC_FIFO_DMIC3L_DATA_REG
- OMAP_DMIC_FIFO_DMIC3R_DATA_REG
- OMAP_DMIC_FORMAT
- OMAP_DMIC_IRQ
- OMAP_DMIC_IRQENABLE_CLR_REG
- OMAP_DMIC_IRQENABLE_SET_REG
- OMAP_DMIC_IRQSTATUS_RAW_REG
- OMAP_DMIC_IRQSTATUS_REG
- OMAP_DMIC_IRQWAKE_EN_REG
- OMAP_DMIC_IRQ_ALMST_EMPTY
- OMAP_DMIC_IRQ_EMPTY
- OMAP_DMIC_IRQ_FULL
- OMAP_DMIC_IRQ_MASK
- OMAP_DMIC_POLAR1
- OMAP_DMIC_POLAR2
- OMAP_DMIC_POLAR3
- OMAP_DMIC_POLAR_MASK
- OMAP_DMIC_RESET
- OMAP_DMIC_REVISION_REG
- OMAP_DMIC_SYSCLK_PAD_CLKS
- OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS
- OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS
- OMAP_DMIC_SYSCONFIG_REG
- OMAP_DMIC_THRES_MAX
- OMAP_DMIC_UP1_ENABLE
- OMAP_DMIC_UP2_ENABLE
- OMAP_DMIC_UP3_ENABLE
- OMAP_DMIC_UP_ENABLE_MASK
- OMAP_DMM_PRIV_H
- OMAP_DMM_TILER_H
- OMAP_DOMAINWKUP_RST_MASK
- OMAP_DSS_CHANNEL_DIGIT
- OMAP_DSS_CHANNEL_LCD
- OMAP_DSS_CHANNEL_LCD2
- OMAP_DSS_CHANNEL_LCD3
- OMAP_DSS_CHANNEL_WB
- OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
- OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
- OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
- OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
- OMAP_DSS_CLK_SRC_FCK
- OMAP_DSS_COLOR_ARGB16
- OMAP_DSS_COLOR_ARGB16_1555
- OMAP_DSS_COLOR_ARGB32
- OMAP_DSS_COLOR_CLUT1
- OMAP_DSS_COLOR_CLUT2
- OMAP_DSS_COLOR_CLUT4
- OMAP_DSS_COLOR_CLUT8
- OMAP_DSS_COLOR_KEY_GFX_DST
- OMAP_DSS_COLOR_KEY_VID_SRC
- OMAP_DSS_COLOR_NV12
- OMAP_DSS_COLOR_RGB12U
- OMAP_DSS_COLOR_RGB16
- OMAP_DSS_COLOR_RGB24P
- OMAP_DSS_COLOR_RGB24U
- OMAP_DSS_COLOR_RGBA16
- OMAP_DSS_COLOR_RGBA32
- OMAP_DSS_COLOR_RGBX16
- OMAP_DSS_COLOR_RGBX32
- OMAP_DSS_COLOR_UYVY
- OMAP_DSS_COLOR_XRGB16_1555
- OMAP_DSS_COLOR_YUV2
- OMAP_DSS_DEVICE_OP_DETECT
- OMAP_DSS_DEVICE_OP_EDID
- OMAP_DSS_DEVICE_OP_HPD
- OMAP_DSS_DEVICE_OP_MODES
- OMAP_DSS_DISPLAY_ACTIVE
- OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
- OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
- OMAP_DSS_DISPLAY_DISABLED
- OMAP_DSS_DSI_BURST_MODE
- OMAP_DSS_DSI_CMD_MODE
- OMAP_DSS_DSI_EVENT_MODE
- OMAP_DSS_DSI_FMT_RGB565
- OMAP_DSS_DSI_FMT_RGB666
- OMAP_DSS_DSI_FMT_RGB666_PACKED
- OMAP_DSS_DSI_FMT_RGB888
- OMAP_DSS_DSI_PULSE_MODE
- OMAP_DSS_DSI_VIDEO_MODE
- OMAP_DSS_GFX
- OMAP_DSS_LOAD_CLUT_AND_FRAME
- OMAP_DSS_LOAD_CLUT_ONCE_FRAME
- OMAP_DSS_LOAD_CLUT_ONLY
- OMAP_DSS_LOAD_FRAME_ONLY
- OMAP_DSS_MAX_DSI_PINS
- OMAP_DSS_OUTPUT_DBI
- OMAP_DSS_OUTPUT_DPI
- OMAP_DSS_OUTPUT_DSI1
- OMAP_DSS_OUTPUT_DSI2
- OMAP_DSS_OUTPUT_HDMI
- OMAP_DSS_OUTPUT_SDI
- OMAP_DSS_OUTPUT_VENC
- OMAP_DSS_OVL_CAP_GLOBAL_ALPHA
- OMAP_DSS_OVL_CAP_POS
- OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
- OMAP_DSS_OVL_CAP_REPLICATION
- OMAP_DSS_OVL_CAP_SCALE
- OMAP_DSS_OVL_CAP_ZORDER
- OMAP_DSS_ROT_0
- OMAP_DSS_ROT_180
- OMAP_DSS_ROT_270
- OMAP_DSS_ROT_90
- OMAP_DSS_ROT_DMA
- OMAP_DSS_ROT_NONE
- OMAP_DSS_ROT_TILER
- OMAP_DSS_ROT_VRFB
- OMAP_DSS_VENC_TYPE_COMPOSITE
- OMAP_DSS_VENC_TYPE_SVIDEO
- OMAP_DSS_VIDEO1
- OMAP_DSS_VIDEO2
- OMAP_DSS_VIDEO3
- OMAP_DSS_WB
- OMAP_DWC3_ID_FLOAT
- OMAP_DWC3_ID_GROUND
- OMAP_DWC3_VBUS_OFF
- OMAP_DWC3_VBUS_VALID
- OMAP_ECC_BCH16_CODE_HW
- OMAP_ECC_BCH4_CODE_HW
- OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
- OMAP_ECC_BCH8_CODE_HW
- OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
- OMAP_ECC_HAM1_CODE_HW
- OMAP_ECC_HAM1_CODE_SW
- OMAP_EHCI_DEVICE
- OMAP_EHCI_PORT_MODE_HSIC
- OMAP_EHCI_PORT_MODE_PHY
- OMAP_EHCI_PORT_MODE_TLL
- OMAP_EMIFS_CONFIG_BM
- OMAP_EMIFS_CONFIG_FR
- OMAP_EMIFS_CONFIG_PDE
- OMAP_EMIFS_CONFIG_PWD_EN
- OMAP_EMIFS_CONFIG_WP
- OMAP_ENABLE_MASK
- OMAP_EN_GFX_MASK
- OMAP_EN_GFX_SHIFT
- OMAP_EN_WKUP_MASK
- OMAP_EN_WKUP_SHIFT
- OMAP_EXTWARM_RST_SRC_ID_SHIFT
- OMAP_FIREWALL_L3
- OMAP_FIREWALL_L4
- OMAP_FPGA_IRQ_BASE
- OMAP_FPGA_IRQ_END
- OMAP_FPGA_NR_IRQS
- OMAP_FUNC_MUX_ARM_BASE
- OMAP_GEM_READ
- OMAP_GEM_WRITE
- OMAP_GLOBALCOLD_RST_MASK
- OMAP_GLOBALCOLD_RST_SHIFT
- OMAP_GLOBALWARM_RST_MASK
- OMAP_GLOBALWARM_RST_SHIFT
- OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT
- OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT
- OMAP_GPIO_IS_MPUIO
- OMAP_GPIO_LABEL
- OMAP_GPIO_SMSC_IRQ
- OMAP_GRADIENT_CONST_W_PCB_4430
- OMAP_GRADIENT_CONST_W_PCB_4460
- OMAP_GRADIENT_CONST_W_PCB_4470
- OMAP_GRADIENT_CONST_W_PCB_5430_CPU
- OMAP_GRADIENT_CONST_W_PCB_5430_GPU
- OMAP_GRADIENT_SLOPE_W_PCB_4430
- OMAP_GRADIENT_SLOPE_W_PCB_4460
- OMAP_GRADIENT_SLOPE_W_PCB_4470
- OMAP_GRADIENT_SLOPE_W_PCB_5430_CPU
- OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU
- OMAP_HDQ_CTRL_STATUS
- OMAP_HDQ_CTRL_STATUS_CLOCKENABLE
- OMAP_HDQ_CTRL_STATUS_DIR
- OMAP_HDQ_CTRL_STATUS_GO
- OMAP_HDQ_CTRL_STATUS_INITIALIZATION
- OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK
- OMAP_HDQ_CTRL_STATUS_PRESENCE
- OMAP_HDQ_CTRL_STATUS_SINGLE
- OMAP_HDQ_FLAG_CLEAR
- OMAP_HDQ_FLAG_SET
- OMAP_HDQ_INT_STATUS
- OMAP_HDQ_INT_STATUS_RXCOMPLETE
- OMAP_HDQ_INT_STATUS_TIMEOUT
- OMAP_HDQ_INT_STATUS_TXCOMPLETE
- OMAP_HDQ_MAX_USER
- OMAP_HDQ_REVISION
- OMAP_HDQ_RX_DATA
- OMAP_HDQ_SYSCONFIG
- OMAP_HDQ_SYSCONFIG_AUTOIDLE
- OMAP_HDQ_SYSCONFIG_NOIDLE
- OMAP_HDQ_SYSCONFIG_SOFTRESET
- OMAP_HDQ_SYSSTATUS
- OMAP_HDQ_SYSSTATUS_RESETDONE
- OMAP_HDQ_TIMEOUT
- OMAP_HDQ_TX_DATA
- OMAP_HSMMC_AC12
- OMAP_HSMMC_ARG
- OMAP_HSMMC_BLK
- OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
- OMAP_HSMMC_CAPA
- OMAP_HSMMC_CMD
- OMAP_HSMMC_CON
- OMAP_HSMMC_DATA
- OMAP_HSMMC_HCTL
- OMAP_HSMMC_IE
- OMAP_HSMMC_ISE
- OMAP_HSMMC_PSTATE
- OMAP_HSMMC_READ
- OMAP_HSMMC_RSP10
- OMAP_HSMMC_RSP32
- OMAP_HSMMC_RSP54
- OMAP_HSMMC_RSP76
- OMAP_HSMMC_SDMASA
- OMAP_HSMMC_STAT
- OMAP_HSMMC_SUPPORTS_DUAL_VOLT
- OMAP_HSMMC_SWAKEUP_MISSING
- OMAP_HSMMC_SYSCTL
- OMAP_HSMMC_SYSSTATUS
- OMAP_HSMMC_WRITE
- OMAP_I2C_BUFSTAT_REG
- OMAP_I2C_BUF_RDMA_EN
- OMAP_I2C_BUF_REG
- OMAP_I2C_BUF_RXFIF_CLR
- OMAP_I2C_BUF_TXFIF_CLR
- OMAP_I2C_BUF_XDMA_EN
- OMAP_I2C_BUS_FREE_TIMEOUT
- OMAP_I2C_CMDLINE_SETUP
- OMAP_I2C_CNT_REG
- OMAP_I2C_CON_BE
- OMAP_I2C_CON_EN
- OMAP_I2C_CON_MST
- OMAP_I2C_CON_OPMODE_HS
- OMAP_I2C_CON_REG
- OMAP_I2C_CON_RM
- OMAP_I2C_CON_STB
- OMAP_I2C_CON_STP
- OMAP_I2C_CON_STT
- OMAP_I2C_CON_TRX
- OMAP_I2C_CON_XA
- OMAP_I2C_DATA_REG
- OMAP_I2C_FLAG_16BIT_DATA_REG
- OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK
- OMAP_I2C_FLAG_BUS_SHIFT_1
- OMAP_I2C_FLAG_BUS_SHIFT_2
- OMAP_I2C_FLAG_BUS_SHIFT_NONE
- OMAP_I2C_FLAG_BUS_SHIFT__SHIFT
- OMAP_I2C_FLAG_FORCE_19200_INT_CLK
- OMAP_I2C_FLAG_NO_FIFO
- OMAP_I2C_FLAG_SIMPLE_CLOCK
- OMAP_I2C_IE_AL
- OMAP_I2C_IE_ARDY
- OMAP_I2C_IE_NACK
- OMAP_I2C_IE_RDR
- OMAP_I2C_IE_REG
- OMAP_I2C_IE_RRDY
- OMAP_I2C_IE_XDR
- OMAP_I2C_IE_XRDY
- OMAP_I2C_IP_V2_INTERRUPTS_MASK
- OMAP_I2C_IP_V2_IRQENABLE_CLR
- OMAP_I2C_IP_V2_IRQENABLE_SET
- OMAP_I2C_IP_V2_IRQSTATUS_RAW
- OMAP_I2C_IP_V2_REVNB_HI
- OMAP_I2C_IP_V2_REVNB_LO
- OMAP_I2C_IP_VERSION_1
- OMAP_I2C_IP_VERSION_2
- OMAP_I2C_IV_REG
- OMAP_I2C_MAX_CONTROLLERS
- OMAP_I2C_OA_REG
- OMAP_I2C_OMAP1_REV_2
- OMAP_I2C_PM_TIMEOUT
- OMAP_I2C_PSC_REG
- OMAP_I2C_REV_ON_2430
- OMAP_I2C_REV_ON_3430_3530
- OMAP_I2C_REV_ON_3630
- OMAP_I2C_REV_ON_4430_PLUS
- OMAP_I2C_REV_REG
- OMAP_I2C_REV_SCHEME_0_MAJOR
- OMAP_I2C_REV_SCHEME_0_MINOR
- OMAP_I2C_REV_SCHEME_1_MAJOR
- OMAP_I2C_REV_SCHEME_1_MINOR
- OMAP_I2C_SA_REG
- OMAP_I2C_SCHEME
- OMAP_I2C_SCHEME_0
- OMAP_I2C_SCHEME_1
- OMAP_I2C_SCLH_HSSCLH
- OMAP_I2C_SCLH_REG
- OMAP_I2C_SCLL_HSSCLL
- OMAP_I2C_SCLL_REG
- OMAP_I2C_SIZE
- OMAP_I2C_STAT_AAS
- OMAP_I2C_STAT_AL
- OMAP_I2C_STAT_ARDY
- OMAP_I2C_STAT_BB
- OMAP_I2C_STAT_BF
- OMAP_I2C_STAT_NACK
- OMAP_I2C_STAT_RDR
- OMAP_I2C_STAT_REG
- OMAP_I2C_STAT_ROVR
- OMAP_I2C_STAT_RRDY
- OMAP_I2C_STAT_XDR
- OMAP_I2C_STAT_XRDY
- OMAP_I2C_STAT_XUDF
- OMAP_I2C_SYSC_REG
- OMAP_I2C_SYSS_REG
- OMAP_I2C_SYSTEST_FREE
- OMAP_I2C_SYSTEST_REG
- OMAP_I2C_SYSTEST_SCL_I
- OMAP_I2C_SYSTEST_SCL_I_FUNC
- OMAP_I2C_SYSTEST_SCL_O
- OMAP_I2C_SYSTEST_SCL_O_FUNC
- OMAP_I2C_SYSTEST_SDA_I
- OMAP_I2C_SYSTEST_SDA_I_FUNC
- OMAP_I2C_SYSTEST_SDA_O
- OMAP_I2C_SYSTEST_SDA_O_FUNC
- OMAP_I2C_SYSTEST_ST_EN
- OMAP_I2C_SYSTEST_TMODE_MASK
- OMAP_I2C_SYSTEST_TMODE_SHIFT
- OMAP_I2C_TIMEOUT
- OMAP_I2C_WE_AAS_WE
- OMAP_I2C_WE_ALL
- OMAP_I2C_WE_AL_WE
- OMAP_I2C_WE_ARDY_WE
- OMAP_I2C_WE_BF_WE
- OMAP_I2C_WE_DRDY_WE
- OMAP_I2C_WE_GC_WE
- OMAP_I2C_WE_NACK_WE
- OMAP_I2C_WE_RDR_WE
- OMAP_I2C_WE_REG
- OMAP_I2C_WE_STC_WE
- OMAP_I2C_WE_XDR_WE
- OMAP_ICECRUSHER_RST_SRC_ID_SHIFT
- OMAP_ICEPICK_RST_SRC_ID_SHIFT
- OMAP_IH1_BASE
- OMAP_IH1_CONTROL
- OMAP_IH1_ILR0
- OMAP_IH1_ISR
- OMAP_IH1_ITR
- OMAP_IH1_MIR
- OMAP_IH1_SIR_FIQ
- OMAP_IH1_SIR_IRQ
- OMAP_IH2_0_BASE
- OMAP_IH2_0_CONTROL
- OMAP_IH2_0_ILR0
- OMAP_IH2_0_ISR
- OMAP_IH2_0_ITR
- OMAP_IH2_0_MIR
- OMAP_IH2_0_SIR_FIQ
- OMAP_IH2_0_SIR_IRQ
- OMAP_IH2_1_BASE
- OMAP_IH2_1_CONTROL
- OMAP_IH2_1_ILR1
- OMAP_IH2_1_ISR
- OMAP_IH2_1_ITR
- OMAP_IH2_1_MIR
- OMAP_IH2_1_SIR_FIQ
- OMAP_IH2_1_SIR_IRQ
- OMAP_IH2_2_BASE
- OMAP_IH2_2_CONTROL
- OMAP_IH2_2_ILR2
- OMAP_IH2_2_ISR
- OMAP_IH2_2_ITR
- OMAP_IH2_2_MIR
- OMAP_IH2_2_SIR_FIQ
- OMAP_IH2_2_SIR_IRQ
- OMAP_IH2_3_BASE
- OMAP_IH2_3_CONTROL
- OMAP_IH2_3_ILR3
- OMAP_IH2_3_ISR
- OMAP_IH2_3_ITR
- OMAP_IH2_3_MIR
- OMAP_IH2_3_SIR_FIQ
- OMAP_IH2_3_SIR_IRQ
- OMAP_IH2_BASE
- OMAP_IH2_CONTROL
- OMAP_IH2_ILR0
- OMAP_IH2_ISR
- OMAP_IH2_ITR
- OMAP_IH2_MIR
- OMAP_IH2_SIR_FIQ
- OMAP_IH2_SIR_IRQ
- OMAP_INTC_START
- OMAP_INTRANSITION_MASK
- OMAP_INT_EP
- OMAP_IO
- OMAP_IOMMU_PGSIZES
- OMAP_IOPAD_OFFSET
- OMAP_IOR
- OMAP_IOW
- OMAP_IOWR
- OMAP_IRQ_BIT
- OMAP_IRQ_END
- OMAP_ISO_EP
- OMAP_L2C_AUX_CTRL
- OMAP_L3_CODE_ADDR_HOLE
- OMAP_L3_CODE_IN_BAND_ERR
- OMAP_L3_CODE_NOERROR
- OMAP_L3_CODE_PROTECT_VIOLATION
- OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT
- OMAP_L3_CODE_REQ_TOUT_NO_RESP
- OMAP_L3_CODE_UNSUP_CMD
- OMAP_L3_IA_CAM_1
- OMAP_L3_IA_CAM_2
- OMAP_L3_IA_CAM_3
- OMAP_L3_IA_DAP
- OMAP_L3_IA_IVA_SS_1
- OMAP_L3_IA_IVA_SS_2
- OMAP_L3_IA_IVA_SS_3
- OMAP_L3_IA_IVA_SS_DMA_1
- OMAP_L3_IA_IVA_SS_DMA_2
- OMAP_L3_IA_IVA_SS_DMA_3
- OMAP_L3_IA_IVA_SS_DMA_4
- OMAP_L3_IA_IVA_SS_DMA_5
- OMAP_L3_IA_IVA_SS_DMA_6
- OMAP_L3_IA_MPU_SS_1
- OMAP_L3_IA_MPU_SS_2
- OMAP_L3_IA_MPU_SS_3
- OMAP_L3_IA_MPU_SS_4
- OMAP_L3_IA_MPU_SS_5
- OMAP_L3_IA_SGX
- OMAP_L3_LCD
- OMAP_L3_SAD2D
- OMAP_L3_SDMA_RD_1
- OMAP_L3_SDMA_RD_2
- OMAP_L3_SDMA_RD_3
- OMAP_L3_SDMA_RD_4
- OMAP_L3_SDMA_WR_1
- OMAP_L3_SDMA_WR_2
- OMAP_L3_USBHOST
- OMAP_L3_USBOTG
- OMAP_LCDC_BASE
- OMAP_LCDC_CONTROL
- OMAP_LCDC_CTRL_LCD_EN
- OMAP_LCDC_CTRL_LCD_TFT
- OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL
- OMAP_LCDC_DISPLAY_STATUS
- OMAP_LCDC_HSVS_OPPOSITE
- OMAP_LCDC_HSVS_RISING_EDGE
- OMAP_LCDC_INV_HSYNC
- OMAP_LCDC_INV_OUTPUT_EN
- OMAP_LCDC_INV_PIX_CLOCK
- OMAP_LCDC_INV_VSYNC
- OMAP_LCDC_IRQ
- OMAP_LCDC_IRQ_DONE
- OMAP_LCDC_IRQ_LINE
- OMAP_LCDC_IRQ_LINE_NIRQ
- OMAP_LCDC_IRQ_LOADED_PALETTE
- OMAP_LCDC_IRQ_MASK
- OMAP_LCDC_IRQ_VSYNC
- OMAP_LCDC_LINE_INT
- OMAP_LCDC_LOAD_FRAME
- OMAP_LCDC_LOAD_PALETTE
- OMAP_LCDC_LOAD_PALETTE_AND_FRAME
- OMAP_LCDC_PANEL_TFT
- OMAP_LCDC_SIGNAL_MASK
- OMAP_LCDC_SIZE
- OMAP_LCDC_STATUS
- OMAP_LCDC_STAT_ABC
- OMAP_LCDC_STAT_DONE
- OMAP_LCDC_STAT_FUF
- OMAP_LCDC_STAT_LINE_INT
- OMAP_LCDC_STAT_LOADED_PALETTE
- OMAP_LCDC_STAT_SYNC_LOST
- OMAP_LCDC_STAT_VSYNC
- OMAP_LCDC_SUBPANEL
- OMAP_LCDC_TIMING0
- OMAP_LCDC_TIMING1
- OMAP_LCDC_TIMING2
- OMAP_LCD_DMA_B1_BOTTOM
- OMAP_LCD_DMA_B1_TOP
- OMAP_LCD_DMA_B2_BOTTOM
- OMAP_LCD_DMA_B2_TOP
- OMAP_LOGICRETSTATE_MASK
- OMAP_LPG1_BASE
- OMAP_LPG1_LCR
- OMAP_LPG1_PMR
- OMAP_LPG2_BASE
- OMAP_LPG2_LCR
- OMAP_LPG2_PMR
- OMAP_MAILBOX_H
- OMAP_MAX_GPIO_LINES
- OMAP_MAX_HSUART_PORTS
- OMAP_MCBSP_CLKGDV
- OMAP_MCBSP_RATES
- OMAP_MCBSP_REG_DRR
- OMAP_MCBSP_REG_DRR1
- OMAP_MCBSP_REG_DRR2
- OMAP_MCBSP_REG_DXR
- OMAP_MCBSP_REG_DXR1
- OMAP_MCBSP_REG_DXR2
- OMAP_MCBSP_REG_IRQEN
- OMAP_MCBSP_REG_IRQST
- OMAP_MCBSP_REG_MCR1
- OMAP_MCBSP_REG_MCR2
- OMAP_MCBSP_REG_PCR0
- OMAP_MCBSP_REG_RBUFFSTAT
- OMAP_MCBSP_REG_RCCR
- OMAP_MCBSP_REG_RCERA
- OMAP_MCBSP_REG_RCERB
- OMAP_MCBSP_REG_RCERC
- OMAP_MCBSP_REG_RCERD
- OMAP_MCBSP_REG_RCERE
- OMAP_MCBSP_REG_RCERF
- OMAP_MCBSP_REG_RCERG
- OMAP_MCBSP_REG_RCERH
- OMAP_MCBSP_REG_RCR1
- OMAP_MCBSP_REG_RCR2
- OMAP_MCBSP_REG_SPCR1
- OMAP_MCBSP_REG_SPCR2
- OMAP_MCBSP_REG_SRGR1
- OMAP_MCBSP_REG_SRGR2
- OMAP_MCBSP_REG_SSELCR
- OMAP_MCBSP_REG_SYSCON
- OMAP_MCBSP_REG_THRSH1
- OMAP_MCBSP_REG_THRSH2
- OMAP_MCBSP_REG_WAKEUPEN
- OMAP_MCBSP_REG_XBUFFSTAT
- OMAP_MCBSP_REG_XCCR
- OMAP_MCBSP_REG_XCERA
- OMAP_MCBSP_REG_XCERB
- OMAP_MCBSP_REG_XCERC
- OMAP_MCBSP_REG_XCERD
- OMAP_MCBSP_REG_XCERE
- OMAP_MCBSP_REG_XCERF
- OMAP_MCBSP_REG_XCERG
- OMAP_MCBSP_REG_XCERH
- OMAP_MCBSP_REG_XCR1
- OMAP_MCBSP_REG_XCR2
- OMAP_MCBSP_SOC_SINGLE_S16_EXT
- OMAP_MCBSP_ST_CHANNEL_VOLUME
- OMAP_MCBSP_ST_CONTROLS
- OMAP_MCBSP_SYSCLK_CLK
- OMAP_MCBSP_SYSCLK_CLKR_EXT
- OMAP_MCBSP_SYSCLK_CLKS_EXT
- OMAP_MCBSP_SYSCLK_CLKS_FCLK
- OMAP_MCBSP_SYSCLK_CLKX_EXT
- OMAP_MCBSP_WORD_12
- OMAP_MCBSP_WORD_16
- OMAP_MCBSP_WORD_20
- OMAP_MCBSP_WORD_24
- OMAP_MCBSP_WORD_32
- OMAP_MCBSP_WORD_8
- OMAP_MCPDM_FORMATS
- OMAP_MCPDM_RATES
- OMAP_MEM0_ONSTATE_MASK
- OMAP_MEM0_RETSTATE_MASK
- OMAP_MEM0_STATEST_MASK
- OMAP_MEM1_ONSTATE_MASK
- OMAP_MEM1_RETSTATE_MASK
- OMAP_MEM1_STATEST_MASK
- OMAP_MEM2_ONSTATE_MASK
- OMAP_MEM2_RETSTATE_MASK
- OMAP_MEM2_STATEST_MASK
- OMAP_MEM3_ONSTATE_MASK
- OMAP_MEM3_RETSTATE_MASK
- OMAP_MEM3_STATEST_MASK
- OMAP_MEM4_ONSTATE_MASK
- OMAP_MEM4_RETSTATE_MASK
- OMAP_MEM4_STATEST_MASK
- OMAP_MMC_CMDTYPE_AC
- OMAP_MMC_CMDTYPE_ADTC
- OMAP_MMC_CMDTYPE_BC
- OMAP_MMC_CMDTYPE_BCR
- OMAP_MMC_COVER_POLL_DELAY
- OMAP_MMC_MAX_CLOCK
- OMAP_MMC_MAX_SLOTS
- OMAP_MMC_MIN_CLOCK
- OMAP_MMC_NR_RES
- OMAP_MMC_READ
- OMAP_MMC_REG
- OMAP_MMC_REG_ARGH
- OMAP_MMC_REG_ARGL
- OMAP_MMC_REG_BLEN
- OMAP_MMC_REG_BUF
- OMAP_MMC_REG_CMD
- OMAP_MMC_REG_CON
- OMAP_MMC_REG_CTO
- OMAP_MMC_REG_DATA
- OMAP_MMC_REG_DTO
- OMAP_MMC_REG_IE
- OMAP_MMC_REG_IOSR
- OMAP_MMC_REG_NBLK
- OMAP_MMC_REG_REV
- OMAP_MMC_REG_RSP0
- OMAP_MMC_REG_RSP1
- OMAP_MMC_REG_RSP2
- OMAP_MMC_REG_RSP3
- OMAP_MMC_REG_RSP4
- OMAP_MMC_REG_RSP5
- OMAP_MMC_REG_RSP6
- OMAP_MMC_REG_RSP7
- OMAP_MMC_REG_SDIO
- OMAP_MMC_REG_STAT
- OMAP_MMC_REG_SYSC
- OMAP_MMC_REG_SYSS
- OMAP_MMC_STAT_A_EMPTY
- OMAP_MMC_STAT_A_FULL
- OMAP_MMC_STAT_CARD_BUSY
- OMAP_MMC_STAT_CARD_ERR
- OMAP_MMC_STAT_CARD_IRQ
- OMAP_MMC_STAT_CMD_CRC
- OMAP_MMC_STAT_CMD_TOUT
- OMAP_MMC_STAT_DATA_CRC
- OMAP_MMC_STAT_DATA_TOUT
- OMAP_MMC_STAT_END_BUSY
- OMAP_MMC_STAT_END_OF_CMD
- OMAP_MMC_STAT_END_OF_DATA
- OMAP_MMC_STAT_OCR_BUSY
- OMAP_MMC_WRITE
- OMAP_MODE13X_SPEED
- OMAP_MPUIO
- OMAP_MPUIO_GPIO_DEBOUNCING
- OMAP_MPUIO_GPIO_EVENT_MODE
- OMAP_MPUIO_GPIO_INT
- OMAP_MPUIO_GPIO_INT_EDGE
- OMAP_MPUIO_GPIO_MASKIT
- OMAP_MPUIO_INPUT_LATCH
- OMAP_MPUIO_IO_CNTL
- OMAP_MPUIO_KBC
- OMAP_MPUIO_KBD_INT
- OMAP_MPUIO_KBD_MASKIT
- OMAP_MPUIO_KBR_LATCH
- OMAP_MPUIO_LABEL
- OMAP_MPUIO_LATCH
- OMAP_MPUIO_OUTPUT
- OMAP_MPU_TIMER1_BASE
- OMAP_MPU_TIMER2_BASE
- OMAP_MPU_TIMER3_BASE
- OMAP_MPU_TIMER_BASE
- OMAP_MPU_TIMER_OFFSET
- OMAP_MPU_WATCHDOG_BASE
- OMAP_MPU_WD_RST_SRC_ID_SHIFT
- OMAP_NAME
- OMAP_NAND_IO_READ
- OMAP_NAND_IO_WRITE
- OMAP_NAND_TIMEOUT_MS
- OMAP_OFFLOADMODE_MASK
- OMAP_OFFLOADMODE_SHIFT
- OMAP_OFFTIMEVAL_MASK
- OMAP_OFFTIMEVAL_SHIFT
- OMAP_OHCI_BASE
- OMAP_OHCI_DEVICE
- OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0
- OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM
- OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0
- OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM
- OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0
- OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
- OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0
- OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM
- OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0
- OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM
- OMAP_ONLOADMODE_MASK
- OMAP_ONLOADMODE_SHIFT
- OMAP_ONTIMEVAL_MASK
- OMAP_ONTIMEVAL_SHIFT
- OMAP_OSK_ETHR_START
- OMAP_OTG_ASESSVLD
- OMAP_OTG_BSESSEND
- OMAP_OTG_BSESSVLD
- OMAP_OTG_CTRL
- OMAP_OTG_ID
- OMAP_OTG_VBUSVLD
- OMAP_OTG_XCEIV_OUTPUTS
- OMAP_PADCONF_OFFSET
- OMAP_PARAM_CHIPSET_ID
- OMAP_PORT_SHIFT
- OMAP_POWERSTATEST_MASK
- OMAP_POWERSTATEST_SHIFT
- OMAP_POWERSTATE_MASK
- OMAP_POWERSTATE_SHIFT
- OMAP_PRCM_IRQ
- OMAP_PRCM_MAX_NR_PENDING_REG
- OMAP_PRODUCTION_ID_0
- OMAP_PRODUCTION_ID_1
- OMAP_PTMSYNCREQ_EN
- OMAP_PTMSYNCREQ_MASK
- OMAP_PWL_BASE
- OMAP_PWL_CLK_ENABLE
- OMAP_PWL_ENABLE
- OMAP_REV2_TLL_CHANNEL_COUNT
- OMAP_RSTTIME1_MASK
- OMAP_RSTTIME1_SHIFT
- OMAP_RSTTIME2_MASK
- OMAP_RSTTIME2_SHIFT
- OMAP_RST_DPLL3_MASK
- OMAP_RST_GS_MASK
- OMAP_RTC_ALARM2_DAYS_REG
- OMAP_RTC_ALARM2_HOURS_REG
- OMAP_RTC_ALARM2_MINUTES_REG
- OMAP_RTC_ALARM2_MONTHS_REG
- OMAP_RTC_ALARM2_SECONDS_REG
- OMAP_RTC_ALARM2_YEARS_REG
- OMAP_RTC_ALARM_DAYS_REG
- OMAP_RTC_ALARM_HOURS_REG
- OMAP_RTC_ALARM_MINUTES_REG
- OMAP_RTC_ALARM_MONTHS_REG
- OMAP_RTC_ALARM_SECONDS_REG
- OMAP_RTC_ALARM_YEARS_REG
- OMAP_RTC_BASE
- OMAP_RTC_COMP_LSB_REG
- OMAP_RTC_COMP_MSB_REG
- OMAP_RTC_CTRL_AUTO_COMP
- OMAP_RTC_CTRL_DISABLE
- OMAP_RTC_CTRL_MODE_12_24
- OMAP_RTC_CTRL_REG
- OMAP_RTC_CTRL_ROUND_30S
- OMAP_RTC_CTRL_SET_32_COUNTER
- OMAP_RTC_CTRL_SPLIT
- OMAP_RTC_CTRL_STOP
- OMAP_RTC_CTRL_TEST
- OMAP_RTC_DAYS_REG
- OMAP_RTC_HOURS_REG
- OMAP_RTC_INTERRUPTS_IT_ALARM
- OMAP_RTC_INTERRUPTS_IT_ALARM2
- OMAP_RTC_INTERRUPTS_IT_TIMER
- OMAP_RTC_INTERRUPTS_REG
- OMAP_RTC_IRQWAKEEN
- OMAP_RTC_IRQWAKEEN_ALARM_WAKEEN
- OMAP_RTC_KICK0_REG
- OMAP_RTC_KICK0_VALUE
- OMAP_RTC_KICK1_REG
- OMAP_RTC_KICK1_VALUE
- OMAP_RTC_MAX_READY_TIME
- OMAP_RTC_MINUTES_REG
- OMAP_RTC_MONTHS_REG
- OMAP_RTC_OSC_32KCLK_EN
- OMAP_RTC_OSC_OSC32K_GZ_DISABLE
- OMAP_RTC_OSC_REG
- OMAP_RTC_OSC_SEL_32KCLK_SRC
- OMAP_RTC_PMIC_EXT_WKUP_EN
- OMAP_RTC_PMIC_EXT_WKUP_POL
- OMAP_RTC_PMIC_POWER_EN_EN
- OMAP_RTC_PMIC_REG
- OMAP_RTC_SCRATCH0_REG
- OMAP_RTC_SCRATCH1_REG
- OMAP_RTC_SCRATCH2_REG
- OMAP_RTC_SECONDS_REG
- OMAP_RTC_STATUS_1D_EVENT
- OMAP_RTC_STATUS_1H_EVENT
- OMAP_RTC_STATUS_1M_EVENT
- OMAP_RTC_STATUS_1S_EVENT
- OMAP_RTC_STATUS_ALARM
- OMAP_RTC_STATUS_ALARM2
- OMAP_RTC_STATUS_BUSY
- OMAP_RTC_STATUS_POWER_UP
- OMAP_RTC_STATUS_REG
- OMAP_RTC_STATUS_RUN
- OMAP_RTC_WEEKS_REG
- OMAP_RTC_YEARS_REG
- OMAP_SDMA_CHANNELS
- OMAP_SDMA_REQUESTS
- OMAP_SDRC_REGADDR
- OMAP_SECURE_RAM_STORAGE
- OMAP_SECU_VIOL_RST_SRC_ID_SHIFT
- OMAP_SECU_WD_RST_SRC_ID_SHIFT
- OMAP_SERIAL_DRIVER_NAME
- OMAP_SERIAL_NAME
- OMAP_SETUP_TIME_MASK
- OMAP_SETUP_TIME_SHIFT
- OMAP_SHAM_QUEUE_LENGTH
- OMAP_SHA_DMA_THRESHOLD
- OMAP_SMS_REGADDR
- OMAP_SOC_MAX_NAME_LENGTH
- OMAP_SOSSI_BASE
- OMAP_SR_CORE
- OMAP_SR_IVA
- OMAP_SR_MPU
- OMAP_SR_NR
- OMAP_ST_GFX_MASK
- OMAP_ST_REG_IRQENABLE
- OMAP_ST_REG_IRQSTATUS
- OMAP_ST_REG_REV
- OMAP_ST_REG_SFIRCR
- OMAP_ST_REG_SGAINCR
- OMAP_ST_REG_SSELCR
- OMAP_ST_REG_SYSCONFIG
- OMAP_SYSCLKDIV_MASK
- OMAP_SYSCLKDIV_SHIFT
- OMAP_SYSCLKDIV_WIDTH
- OMAP_SYSCLKSEL_MASK
- OMAP_SYSCLKSEL_SHIFT
- OMAP_TAP_DIE_ID_0
- OMAP_TAP_DIE_ID_1
- OMAP_TAP_DIE_ID_2
- OMAP_TAP_DIE_ID_3
- OMAP_TAP_DIE_ID_44XX_0
- OMAP_TAP_DIE_ID_44XX_1
- OMAP_TAP_DIE_ID_44XX_2
- OMAP_TAP_DIE_ID_44XX_3
- OMAP_TAP_IDCODE
- OMAP_TC_EMIFF_PRIOR
- OMAP_TC_EMIFS_PRIOR
- OMAP_TC_OCPT1_PRIOR
- OMAP_TC_OCPT2_PRIOR
- OMAP_TIMER32K_BASE
- OMAP_TIMER_ALWON
- OMAP_TIMER_CAPTURE2_REG
- OMAP_TIMER_CAPTURE_REG
- OMAP_TIMER_COUNTER_REG
- OMAP_TIMER_CTRL_AR
- OMAP_TIMER_CTRL_CAPTMODE
- OMAP_TIMER_CTRL_CE
- OMAP_TIMER_CTRL_GPOCFG
- OMAP_TIMER_CTRL_POSTED
- OMAP_TIMER_CTRL_PRE
- OMAP_TIMER_CTRL_PT
- OMAP_TIMER_CTRL_PTV_SHIFT
- OMAP_TIMER_CTRL_REG
- OMAP_TIMER_CTRL_SCPWM
- OMAP_TIMER_CTRL_ST
- OMAP_TIMER_CTRL_TCM_BOTHEDGES
- OMAP_TIMER_CTRL_TCM_HIGHTOLOW
- OMAP_TIMER_CTRL_TCM_LOWTOHIGH
- OMAP_TIMER_ERRATA_I103_I767
- OMAP_TIMER_HAS_DSP_IRQ
- OMAP_TIMER_HAS_PWM
- OMAP_TIMER_ID_OFFSET
- OMAP_TIMER_IF_CTRL_REG
- OMAP_TIMER_INT_CAPTURE
- OMAP_TIMER_INT_MATCH
- OMAP_TIMER_INT_OVERFLOW
- OMAP_TIMER_LOAD_REG
- OMAP_TIMER_MATCH_REG
- OMAP_TIMER_NEEDS_RESET
- OMAP_TIMER_NONPOSTED
- OMAP_TIMER_OCP_CFG_OFFSET
- OMAP_TIMER_POSTED
- OMAP_TIMER_SECURE
- OMAP_TIMER_SRC_32_KHZ
- OMAP_TIMER_SRC_EXT_CLK
- OMAP_TIMER_SRC_SYS_CLK
- OMAP_TIMER_TICK_COUNT_REG
- OMAP_TIMER_TICK_INT_MASK_COUNT_REG
- OMAP_TIMER_TICK_INT_MASK_SET_REG
- OMAP_TIMER_TICK_NEG_REG
- OMAP_TIMER_TICK_POS_REG
- OMAP_TIMER_TRIGGER_NONE
- OMAP_TIMER_TRIGGER_OVERFLOW
- OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE
- OMAP_TIMER_TRIGGER_REG
- OMAP_TIMER_V1_INT_EN_OFFSET
- OMAP_TIMER_V1_STAT_OFFSET
- OMAP_TIMER_V1_SYS_STAT_OFFSET
- OMAP_TIMER_V2_FUNC_OFFSET
- OMAP_TIMER_V2_IRQENABLE_CLR
- OMAP_TIMER_V2_IRQENABLE_SET
- OMAP_TIMER_V2_IRQSTATUS
- OMAP_TIMER_V2_IRQSTATUS_RAW
- OMAP_TIMER_WAKEUP_EN_REG
- OMAP_TIMER_WRITE_PEND_REG
- OMAP_TIMESTAMPCYCLEHI
- OMAP_TIMESTAMPCYCLELO
- OMAP_TLL_CHANNEL_1_EN_MASK
- OMAP_TLL_CHANNEL_2_EN_MASK
- OMAP_TLL_CHANNEL_3_EN_MASK
- OMAP_TLL_CHANNEL_CONF
- OMAP_TLL_CHANNEL_CONF_CHANEN
- OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS
- OMAP_TLL_CHANNEL_CONF_CHRGVBUS
- OMAP_TLL_CHANNEL_CONF_DRVVBUS
- OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT
- OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
- OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE
- OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
- OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE
- OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
- OMAP_TLL_CHANNEL_COUNT
- OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM
- OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0
- OMAP_TLL_FSLSMODE_3PIN_PHY
- OMAP_TLL_FSLSMODE_3PIN_TLL
- OMAP_TLL_FSLSMODE_4PIN_PHY
- OMAP_TLL_FSLSMODE_4PIN_TLL
- OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0
- OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM
- OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0
- OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM
- OMAP_TLL_SHARED_CONF
- OMAP_TLL_SHARED_CONF_FCLK_IS_ON
- OMAP_TLL_SHARED_CONF_FCLK_REQ
- OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN
- OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN
- OMAP_TLL_SHARED_CONF_USB_DIVRATION
- OMAP_TLL_ULPI_DEBUG
- OMAP_TLL_ULPI_FUNCTION_CTRL
- OMAP_TLL_ULPI_INTERFACE_CTRL
- OMAP_TLL_ULPI_INT_EN_FALL
- OMAP_TLL_ULPI_INT_EN_RISE
- OMAP_TLL_ULPI_INT_LATCH
- OMAP_TLL_ULPI_INT_STATUS
- OMAP_TLL_ULPI_OTG_CTRL
- OMAP_TLL_ULPI_SCRATCH_REGISTER
- OMAP_TRIP_COLD
- OMAP_TRIP_HOT
- OMAP_TRIP_NUMBER
- OMAP_TRIP_SHUTDOWN
- OMAP_TRIP_STEP
- OMAP_TWL4030_LEFT
- OMAP_TWL4030_RIGHT
- OMAP_TYPE_OFFSET
- OMAP_UART_DMA_CH_FREE
- OMAP_UART_FCR_RX_FIFO_TRIG_MASK
- OMAP_UART_FCR_RX_TRIG
- OMAP_UART_FCR_TX_FIFO_TRIG_MASK
- OMAP_UART_FCR_TX_TRIG
- OMAP_UART_INFO_OFS
- OMAP_UART_LEGACY_MVR_MAJ_MASK
- OMAP_UART_LEGACY_MVR_MAJ_SHIFT
- OMAP_UART_LEGACY_MVR_MIN_MASK
- OMAP_UART_MVR_MAJ_MASK
- OMAP_UART_MVR_MAJ_SHIFT
- OMAP_UART_MVR_MIN_MASK
- OMAP_UART_MVR_SCHEME_SHIFT
- OMAP_UART_REV_42
- OMAP_UART_REV_46
- OMAP_UART_REV_52
- OMAP_UART_REV_63
- OMAP_UART_SCR_DMAMODE_1
- OMAP_UART_SCR_DMAMODE_CTL
- OMAP_UART_SCR_DMAMODE_MASK
- OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
- OMAP_UART_SCR_TX_EMPTY
- OMAP_UART_SCR_TX_TRIG_GRANU1_MASK
- OMAP_UART_SW_CLR
- OMAP_UART_SW_RX
- OMAP_UART_SW_TX
- OMAP_UART_SYSC_SOFTRESET
- OMAP_UART_SYSS_RESETDONE
- OMAP_UART_TCR_HALT
- OMAP_UART_TCR_RESTORE
- OMAP_UART_TCR_TRIG
- OMAP_UART_TX_WAKEUP_EN
- OMAP_UART_WER_HAS_TX_WAKEUP
- OMAP_UART_WER_MOD_WKUP
- OMAP_UHH_DEBUG_CSR
- OMAP_UHH_HOSTCONFIG
- OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN
- OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
- OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN
- OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS
- OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS
- OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS
- OMAP_UHH_HOSTCONFIG_ULPI_BYPASS
- OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS
- OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
- OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS
- OMAP_UHH_REVISION
- OMAP_UHH_SYSCONFIG
- OMAP_UHH_SYSCONFIG_AUTOIDLE
- OMAP_UHH_SYSCONFIG_CACTIVITY
- OMAP_UHH_SYSCONFIG_ENAWAKEUP
- OMAP_UHH_SYSCONFIG_MIDLEMODE
- OMAP_UHH_SYSCONFIG_SIDLEMODE
- OMAP_UHH_SYSCONFIG_SOFTRESET
- OMAP_UHH_SYSSTATUS
- OMAP_UNKNOWN_RST_SRC_ID_SHIFT
- OMAP_USB2_CALIBRATE_FALSE_DISCONNECT
- OMAP_USB2_HAS_SET_VBUS
- OMAP_USB2_HAS_START_SRP
- OMAP_USB2_PHY_PD
- OMAP_USBHS_PORT_MODE_UNUSED
- OMAP_USBHS_REV1
- OMAP_USBHS_REV2
- OMAP_USBTLL_IRQENABLE
- OMAP_USBTLL_IRQSTATUS
- OMAP_USBTLL_REV1
- OMAP_USBTLL_REV2
- OMAP_USBTLL_REV3
- OMAP_USBTLL_REV4
- OMAP_USBTLL_REVISION
- OMAP_USBTLL_SYSCONFIG
- OMAP_USBTLL_SYSCONFIG_AUTOIDLE
- OMAP_USBTLL_SYSCONFIG_CACTIVITY
- OMAP_USBTLL_SYSCONFIG_ENAWAKEUP
- OMAP_USBTLL_SYSCONFIG_SIDLEMODE
- OMAP_USBTLL_SYSCONFIG_SOFTRESET
- OMAP_USBTLL_SYSSTATUS
- OMAP_USBTLL_SYSSTATUS_RESETDONE
- OMAP_UWIRE_BASE
- OMAP_VC_CHANNEL_CFG_MUTANT
- OMAP_VC_CHANNEL_DEFAULT
- OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT
- OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT
- OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT
- OMAP_VIDEO1
- OMAP_VIDEO2
- OMAP_VOUTDEF_H
- OMAP_VOUTLIB_H
- OMAP_VOUT_MAX_BUF_SIZE
- OMAP_VOUT_VRFB_H
- OMAP_VRFB_LINE_LEN
- OMAP_VRFB_SIZE
- OMAP_WATCHDOG_CNTRL
- OMAP_WATCHDOG_CRR
- OMAP_WATCHDOG_LDR
- OMAP_WATCHDOG_REV
- OMAP_WATCHDOG_SPR
- OMAP_WATCHDOG_STATUS
- OMAP_WATCHDOG_SYS_CONFIG
- OMAP_WATCHDOG_TGR
- OMAP_WATCHDOG_WPS
- OMAP_WDT_LOAD_TIM
- OMAP_WDT_READ_TIM
- OMAP_WDT_SPR
- OMAP_WDT_TIMER
- OMAP_WDT_TIMER_MODE
- OMAP_WDT_WPS
- OMAP_WKG_CONTROL_0
- OMAP_WKG_ENB_A_0
- OMAP_WKG_ENB_A_1
- OMAP_WKG_ENB_B_0
- OMAP_WKG_ENB_B_1
- OMAP_WKG_ENB_C_0
- OMAP_WKG_ENB_C_1
- OMAP_WKG_ENB_D_0
- OMAP_WKG_ENB_D_1
- OMAP_WKG_ENB_E_0
- OMAP_WKG_ENB_E_1
- OMAP_WKUPGEN_BASE
- OMAX_SB_LEN
- OMCR4
- OME_NUMBER_ENTRIES
- OMFS_DIR
- OMFS_DIR_START
- OMFS_EXTENT_CONT
- OMFS_EXTENT_START
- OMFS_FILE
- OMFS_IMAGIC
- OMFS_INODE_CONTINUATION
- OMFS_INODE_NORMAL
- OMFS_INODE_SYSTEM
- OMFS_MAGIC
- OMFS_MAX_BLOCKS
- OMFS_MAX_BLOCK_SIZE
- OMFS_MAX_CLUSTER_SIZE
- OMFS_NAMELEN
- OMFS_SB
- OMFS_XOR_COUNT
- OMI_CAAM
- OMI_FMAN
- OMI_QMAN
- OMI_QMAN_PRIV
- OMNINET_BULKOUTSIZE
- OMNINET_HEADERLEN
- OMNINET_PAYLOADSIZE
- OMPIC_CPUBYTES
- OMPIC_CTRL
- OMPIC_CTRL_DST
- OMPIC_CTRL_IRQ_ACK
- OMPIC_CTRL_IRQ_GEN
- OMPIC_DATA
- OMPIC_STAT
- OMPIC_STAT_IRQ_PENDING
- OMR0
- OMR1
- OMR1BARL
- OMR2BARL
- OMR3BARL
- OMR_BP
- OMR_CA
- OMR_DEF
- OMR_FC
- OMR_FDX
- OMR_FKD
- OMR_HBD
- OMR_HO
- OMR_HP
- OMR_IF
- OMR_MII_10
- OMR_MII_100
- OMR_OM
- OMR_PB
- OMR_PCS
- OMR_PM
- OMR_PR
- OMR_PS
- OMR_RA
- OMR_SB
- OMR_SC
- OMR_SCR
- OMR_SDP
- OMR_SF
- OMR_SIA
- OMR_SR
- OMR_ST
- OMR_SYM
- OMR_TR
- OMR_TTM
- OMSR_CLEAR
- OMT_SIZE
- OM_CHECK_SUBMODEL
- OM_DVBT
- OM_DVBT_Diversity_End
- OM_DVBT_Diversity_Front
- OM_Default
- OM_FLAG_MASK
- OM_IGNORE_MINOR_REVISION
- OM_IGNORE_REVISION
- OM_MATCH_5XXX_FAMILY_MODELS
- OM_MATCH_6XXX_FAMILY_MODELS
- OM_MATCH_7XXX_FAMILY_MODELS
- OM_MATCH_F7XXX_FAMILY_MODELS
- OM_MATCH_FAMILY_MODELS
- OM_MATCH_PREVIOUS_MODELS
- OM_NONE
- OM_QAM_ITU_A
- OM_QAM_ITU_B
- OM_QAM_ITU_C
- OM_STAT
- OM_uint32
- ON
- ON20_VERSION
- ON22K
- ON26_VERSION
- ON64
- ONBOARD_SONIC_PROM_BASE
- ONBOARD_SONIC_REGISTERS
- ONCE
- ONCE_KCTRL_INITIALIZED
- ONCHIP_ADDR1
- ONCHIP_ADDR2
- OND_IO_ERROR
- OND_SUSPEND_IO
- ONE
- ONEMEG_DRIVE
- ONEM_BUF_WHAT_BIT
- ONENAND_BADBLOCK_POS
- ONENAND_BBT_READ_ECC_ERROR
- ONENAND_BBT_READ_ERROR
- ONENAND_BBT_READ_FATAL_ERROR
- ONENAND_BOOTRAM
- ONENAND_BSA_BOOTRAM
- ONENAND_BSA_DATARAM0
- ONENAND_BSA_DATARAM1
- ONENAND_BSA_MASK
- ONENAND_BSA_SHIFT
- ONENAND_BSC_MASK
- ONENAND_BUFRAM_SIZE
- ONENAND_CHECK_BYTE_ACCESS
- ONENAND_CMD_2X_CACHE_PROG
- ONENAND_CMD_2X_PROG
- ONENAND_CMD_BUFFERRAM
- ONENAND_CMD_ERASE
- ONENAND_CMD_ERASE_VERIFY
- ONENAND_CMD_LOCK
- ONENAND_CMD_LOCK_TIGHT
- ONENAND_CMD_MULTIBLOCK_ERASE
- ONENAND_CMD_OTP_ACCESS
- ONENAND_CMD_PROG
- ONENAND_CMD_PROGOOB
- ONENAND_CMD_READ
- ONENAND_CMD_READID
- ONENAND_CMD_READOOB
- ONENAND_CMD_RESET
- ONENAND_CMD_UNLOCK
- ONENAND_CMD_UNLOCK_ALL
- ONENAND_CTRL_ERASE
- ONENAND_CTRL_ERROR
- ONENAND_CTRL_LOAD
- ONENAND_CTRL_LOCK
- ONENAND_CTRL_ONGO
- ONENAND_CTRL_OTP_BL
- ONENAND_CTRL_OTP_L
- ONENAND_CTRL_PROGRAM
- ONENAND_CTRL_RSTB
- ONENAND_CURRENT_BUFFERRAM
- ONENAND_DATARAM
- ONENAND_DDP_CHIP0
- ONENAND_DDP_CHIP1
- ONENAND_DDP_SHIFT
- ONENAND_DEVICE_DENSITY_1Gb
- ONENAND_DEVICE_DENSITY_2Gb
- ONENAND_DEVICE_DENSITY_4Gb
- ONENAND_DEVICE_DENSITY_512Mb
- ONENAND_DEVICE_DENSITY_8Gb
- ONENAND_DEVICE_DENSITY_MASK
- ONENAND_DEVICE_DENSITY_SHIFT
- ONENAND_DEVICE_IS_DDP
- ONENAND_DEVICE_IS_DEMUX
- ONENAND_DEVICE_VCC_MASK
- ONENAND_ECC_1BIT
- ONENAND_ECC_1BIT_ALL
- ONENAND_ECC_2BIT
- ONENAND_ECC_2BIT_ALL
- ONENAND_ECC_3BIT
- ONENAND_ECC_4BIT
- ONENAND_ECC_4BIT_UNCORRECTABLE
- ONENAND_ERASE_START
- ONENAND_ERASE_STATUS
- ONENAND_ERASE_VERIFY
- ONENAND_FPA_MASK
- ONENAND_FPA_SHIFT
- ONENAND_FSA_MASK
- ONENAND_GET_SYS_CFG1
- ONENAND_HAS_2PLANE
- ONENAND_HAS_4KB_PAGE
- ONENAND_HAS_CACHE_PROGRAM
- ONENAND_HAS_CONT_LOCK
- ONENAND_HAS_NOP_1
- ONENAND_HAS_UNLOCK_ALL
- ONENAND_INT_CLEAR
- ONENAND_INT_ERASE
- ONENAND_INT_MASTER
- ONENAND_INT_READ
- ONENAND_INT_RESET
- ONENAND_INT_WRITE
- ONENAND_IS_2PLANE
- ONENAND_IS_4KB_PAGE
- ONENAND_IS_CACHE_PROGRAM
- ONENAND_IS_DDP
- ONENAND_IS_MLC
- ONENAND_IS_NOP_1
- ONENAND_LOCK_END
- ONENAND_LOCK_START
- ONENAND_LOCK_TIGHT_END
- ONENAND_LOCK_TIGHT_START
- ONENAND_MAIN_ACCESS_ONLY
- ONENAND_MAIN_SPARE_ACCESS
- ONENAND_MEMORY_MAP
- ONENAND_MEM_RESET_COLD
- ONENAND_MEM_RESET_HOT
- ONENAND_MEM_RESET_WARM
- ONENAND_MFR_NUMONYX
- ONENAND_MFR_SAMSUNG
- ONENAND_MULTI_ERASE_SET
- ONENAND_NEXT_BUFFERRAM
- ONENAND_OOBBUF_ALLOC
- ONENAND_OTP_ACCESS
- ONENAND_OTP_LOCK_OFFSET
- ONENAND_PAGEBUF_ALLOC
- ONENAND_PAGES_PER_BLOCK
- ONENAND_PIPELINE_READ
- ONENAND_REG_BOOT_BUFFER_SIZE
- ONENAND_REG_COMMAND
- ONENAND_REG_CTRL_STATUS
- ONENAND_REG_DATA_BUFFER_SIZE
- ONENAND_REG_DEVICE_ID
- ONENAND_REG_ECC_M0
- ONENAND_REG_ECC_M1
- ONENAND_REG_ECC_M2
- ONENAND_REG_ECC_M3
- ONENAND_REG_ECC_S0
- ONENAND_REG_ECC_S1
- ONENAND_REG_ECC_S2
- ONENAND_REG_ECC_S3
- ONENAND_REG_ECC_STATUS
- ONENAND_REG_END_BLOCK_ADDRESS
- ONENAND_REG_INTERRUPT
- ONENAND_REG_MANUFACTURER_ID
- ONENAND_REG_NUM_BUFFERS
- ONENAND_REG_START_ADDRESS1
- ONENAND_REG_START_ADDRESS2
- ONENAND_REG_START_ADDRESS3
- ONENAND_REG_START_ADDRESS4
- ONENAND_REG_START_ADDRESS5
- ONENAND_REG_START_ADDRESS6
- ONENAND_REG_START_ADDRESS7
- ONENAND_REG_START_ADDRESS8
- ONENAND_REG_START_BLOCK_ADDRESS
- ONENAND_REG_START_BUFFER
- ONENAND_REG_SYS_CFG1
- ONENAND_REG_SYS_CFG2
- ONENAND_REG_TECHNOLOGY
- ONENAND_REG_VERSION_ID
- ONENAND_REG_WP_STATUS
- ONENAND_SET_BUFFERRAM0
- ONENAND_SET_BUFFERRAM1
- ONENAND_SET_NEXT_BUFFERRAM
- ONENAND_SET_PREV_BUFFERRAM
- ONENAND_SET_SYS_CFG1
- ONENAND_SKIP_INITIAL_UNLOCKING
- ONENAND_SKIP_UNLOCK_CHECK
- ONENAND_SPARERAM
- ONENAND_SPARE_ACCESS_ONLY
- ONENAND_SYS_CFG1_BL_16
- ONENAND_SYS_CFG1_BL_32
- ONENAND_SYS_CFG1_BL_4
- ONENAND_SYS_CFG1_BL_8
- ONENAND_SYS_CFG1_BL_CONT
- ONENAND_SYS_CFG1_BL_SHIFT
- ONENAND_SYS_CFG1_BRL_10
- ONENAND_SYS_CFG1_BRL_3
- ONENAND_SYS_CFG1_BRL_4
- ONENAND_SYS_CFG1_BRL_5
- ONENAND_SYS_CFG1_BRL_6
- ONENAND_SYS_CFG1_BRL_7
- ONENAND_SYS_CFG1_BRL_8
- ONENAND_SYS_CFG1_BRL_9
- ONENAND_SYS_CFG1_BRL_SHIFT
- ONENAND_SYS_CFG1_HF
- ONENAND_SYS_CFG1_INT
- ONENAND_SYS_CFG1_IOBE
- ONENAND_SYS_CFG1_NO_ECC
- ONENAND_SYS_CFG1_RDY
- ONENAND_SYS_CFG1_RDY_CONF
- ONENAND_SYS_CFG1_SYNC_READ
- ONENAND_SYS_CFG1_SYNC_WRITE
- ONENAND_SYS_CFG1_VHF
- ONENAND_TECHNOLOGY_IS_MLC
- ONENAND_UNLOCK_ALL
- ONENAND_UNLOCK_END
- ONENAND_UNLOCK_START
- ONENAND_VERSION_PROCESS_SHIFT
- ONENAND_WP_LS
- ONENAND_WP_LTS
- ONENAND_WP_US
- ONES
- ONESHOT_CAP_INT
- ONESHOT_CAP_INT_AK
- ONESHOT_CAP_INT_EN
- ONES_ADD
- ONETOUCH_BUTTON
- ONETOUCH_PKT_LEN
- ONEXT
- ONE_ADDITIONAL_TRANSACTION
- ONE_AT_A_TIME_RX
- ONE_AT_A_TIME_TX
- ONE_BANK
- ONE_BYTE
- ONE_DB_BNDWDTH_THRSHLD_REG
- ONE_DB_SIZE
- ONE_EIGHTH_FP
- ONE_EIGTH
- ONE_FP
- ONE_FRAGMENT
- ONE_GHZ_IN_KHZ
- ONE_HALF
- ONE_HOUR_IN_SECONDS
- ONE_LED
- ONE_LINE
- ONE_MASK
- ONE_MB
- ONE_MHZ
- ONE_MORE_0
- ONE_MORE_1
- ONE_MORE_2
- ONE_MORE_3
- ONE_MORE_4
- ONE_MORE_5
- ONE_OVER_AREA
- ONE_OVER_AREA_UC
- ONE_PIPE
- ONE_PORT_FLAG
- ONE_PT_CALIB
- ONE_PT_CALIB2
- ONE_QUARTER
- ONE_RB_PER_SE
- ONE_RTC_TICK
- ONE_SAMPLE
- ONE_SHADER_ENGIN
- ONE_SIXTEENTH
- ONE_STATEID
- ONE_T
- ONE_THIRD_SECOND
- ONE_THIRD_VTCLOCK
- ONFICTL
- ONFI_CRC_BASE
- ONFI_DEVICE_FEATURES
- ONFI_DEVICE_FEATURES__VALUE
- ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L
- ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE
- ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U
- ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE
- ONFI_DEVICE_NO_OF_LUNS
- ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS
- ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE
- ONFI_DIN_CNT
- ONFI_DYN_TIMING_MAX
- ONFI_EXT_SECTION_MAX
- ONFI_FEATURE_16_BIT_BUS
- ONFI_FEATURE_ADDR_READ_RETRY
- ONFI_FEATURE_ADDR_TIMING_MODE
- ONFI_FEATURE_EXT_PARAM_PAGE
- ONFI_FEATURE_NUMBER
- ONFI_FEATURE_ON_DIE_ECC
- ONFI_FEATURE_ON_DIE_ECC_EN
- ONFI_OPTIONAL_COMMANDS
- ONFI_OPTIONAL_COMMANDS__VALUE
- ONFI_OPT_CMD_SET_GET_FEATURES
- ONFI_PGM_CACHE_TIMING_MODE
- ONFI_PGM_CACHE_TIMING_MODE__VALUE
- ONFI_SECTION_TYPE_0
- ONFI_SECTION_TYPE_1
- ONFI_SECTION_TYPE_2
- ONFI_SUBFEATURE_PARAM_LEN
- ONFI_TIMING_MODE
- ONFI_TIMING_MODE_0
- ONFI_TIMING_MODE_1
- ONFI_TIMING_MODE_2
- ONFI_TIMING_MODE_3
- ONFI_TIMING_MODE_4
- ONFI_TIMING_MODE_5
- ONFI_TIMING_MODE_UNKNOWN
- ONFI_TIMING_MODE__VALUE
- ONFI_VERSION_1_0
- ONFI_VERSION_2_0
- ONFI_VERSION_2_1
- ONFI_VERSION_2_2
- ONFI_VERSION_2_3
- ONFI_VERSION_3_0
- ONFI_VERSION_3_1
- ONFI_VERSION_3_2
- ONFI_VERSION_4_0
- ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0_MASK
- ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_0__SHIFT
- ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1_MASK
- ONION_NO_STREAMS_PEND__ONION3_NO_STREAMS_PEND_1__SHIFT
- ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND_MASK
- ONION_NO_STREAMS_PEND__ONION_NO_STREAMS_PEND__SHIFT
- ONKEY_STATUS
- ONLCR
- ONLINE
- ONLOOP
- ONLRET
- ONLY_16BIT_IO
- ONLY_32BIT_IO
- ONLY_PLM
- ONLY_TESTING
- ONOCR
- ONST
- ONS_MANID
- ONYX_ADC_HPF_ALWAYS
- ONYX_ADC_INPUT_MIC
- ONYX_ADC_PGA_GAIN_MASK
- ONYX_ADPSV
- ONYX_DAC_FILTER_ALWAYS
- ONYX_DAPSV
- ONYX_DIGDEEMPH_CTRL
- ONYX_DIGDEEMPH_MASK
- ONYX_DIGDEEMPH_SHIFT
- ONYX_DIGOUT_DISABLE
- ONYX_HPF_DISABLE
- ONYX_INTF
- ONYX_MASK_DIN_TO_BPZ
- ONYX_MRST
- ONYX_MUTE_LEFT
- ONYX_MUTE_RIGHT
- ONYX_OUTPHASE_INVERTED
- ONYX_OVR1
- ONYX_REG_ADC_CONTROL
- ONYX_REG_ADC_HPF_BYPASS
- ONYX_REG_CONTROL
- ONYX_REG_DAC_ATTEN_LEFT
- ONYX_REG_DAC_ATTEN_RIGHT
- ONYX_REG_DAC_CONTROL
- ONYX_REG_DAC_DEEMPH
- ONYX_REG_DAC_FILTER
- ONYX_REG_DAC_OUTPHASE
- ONYX_REG_DIG_INFO1
- ONYX_REG_DIG_INFO2
- ONYX_REG_DIG_INFO3
- ONYX_REG_DIG_INFO4
- ONYX_ROLLOFF_FAST
- ONYX_SILICONVERSION
- ONYX_SPDIF_ENABLE
- ONYX_SRST
- ONYX_VALIDL
- ONYX_VALIDR
- ONYX_WORDLEN_MASK
- ON_ALE_MARK
- ON_BD_USB_DRV
- ON_BD_USB_OVC
- ON_CLE_MARK
- ON_DQ0_MARK
- ON_DQ1_MARK
- ON_DQ2_MARK
- ON_DQ3_MARK
- ON_DQ4_MARK
- ON_DQ5_MARK
- ON_DQ6_MARK
- ON_DQ7_MARK
- ON_ERRORS_ACTIONS
- ON_ERRORS_CONTINUE
- ON_ERRORS_PANIC
- ON_ERRORS_RECOVER
- ON_ERRORS_REMOUNT_RO
- ON_ERROR_PANIC
- ON_ERROR_UNREGISTER
- ON_FLAGS
- ON_HALT_STR
- ON_MONITOR_ADD
- ON_MONITOR_ADD_EN
- ON_MONITOR_ADD_MASK
- ON_NCE0_MARK
- ON_NRE_MARK
- ON_NWE_MARK
- ON_NWP_MARK
- ON_OFF_IRQ1_MASK
- ON_OFF_IRQ2_MASK
- ON_PANIC_STR
- ON_POFF_STR
- ON_REIPL_STR
- ON_RESTART_STR
- ON_R_B0_MARK
- ON_SAME_PAGE
- ON_SEQ
- ON_STATE
- OOB1_REG_BANK
- OOBS_AUTOK_DIS
- OOBS_CONFIG
- OOBS_VAL_MASK
- OOB_64
- OOB_ALIGN_0_DATA
- OOB_ALIGN_1_DATA
- OOB_BFLTR
- OOB_BURST_MAX
- OOB_CMD_DRIVER_START
- OOB_CMD_DRIVER_STOP
- OOB_CMD_RESET
- OOB_CM_SIZE
- OOB_CRX_DRIVE_STRENGTH
- OOB_CTRL1
- OOB_CTRL1_BURST_MAX_MASK
- OOB_CTRL1_BURST_MAX_SHIFT
- OOB_CTRL1_BURST_MIN_MASK
- OOB_CTRL1_BURST_MIN_SHIFT
- OOB_CTRL1_WAKE_IDLE_MAX_MASK
- OOB_CTRL1_WAKE_IDLE_MAX_SHIFT
- OOB_CTRL1_WAKE_IDLE_MIN_MASK
- OOB_CTRL1_WAKE_IDLE_MIN_SHIFT
- OOB_CTRL2
- OOB_CTRL2_BURST_CNT_MASK
- OOB_CTRL2_BURST_CNT_SHIFT
- OOB_CTRL2_RESET_IDLE_MAX_MASK
- OOB_CTRL2_RESET_IDLE_MAX_SHIFT
- OOB_CTRL2_RESET_IDLE_MIN_MASK
- OOB_CTRL2_RESET_IDLE_MIN_SHIFT
- OOB_CTRL2_SEL_ENA_RC_SHIFT
- OOB_CTRL2_SEL_ENA_SHIFT
- OOB_DATA_KBITS
- OOB_DISABLE
- OOB_DONE
- OOB_DONE_CLR
- OOB_DONE_EN
- OOB_DRX_DRIVE_STRENGTH
- OOB_ERROR
- OOB_ERROR_CLR
- OOB_ERROR_EN
- OOB_IDLE_MAX
- OOB_INIT_MAX
- OOB_INIT_MIN
- OOB_INIT_NEG
- OOB_MAX
- OOB_MODE
- OOB_NOT_CONNECTED
- OOB_PHY_RESET_COUNT
- OOB_REG_BANK
- OOB_RX_THROTTLE
- OOB_SAS_MAX
- OOB_SAS_MIN
- OOB_SAS_NEG
- OOB_SIG_GEN
- OOB_SIZE
- OOB_STATUS
- OOB_STATUS_CLEAR
- OOB_STATUS_ERROR_MASK
- OOB_TEREDO_EN
- OOB_TIMEOUT
- OOB_TIMEOUT_CLR
- OOB_TIMEOUT_EN
- OOB_TIMER_ENABLE
- OOB_TX_THROTTLE
- OOB_WAKE_MAX
- OOB_WAKE_MIN
- OOB_WAKE_NEG
- OOB_XMIT
- OOK
- OOKPEAK_THRESHDEC_16_TIMES
- OOKPEAK_THRESHDEC_4_TIMES
- OOKPEAK_THRESHDEC_8_TIMES
- OOKPEAK_THRESHDEC_EVERY_2ND
- OOKPEAK_THRESHDEC_EVERY_4TH
- OOKPEAK_THRESHDEC_EVERY_8TH
- OOKPEAK_THRESHDEC_ONCE
- OOKPEAK_THRESHDEC_TWICE
- OOKPEAK_THRESHSTEP_0_5_DB
- OOKPEAK_THRESHSTEP_1_0_DB
- OOKPEAK_THRESHSTEP_1_5_DB
- OOKPEAK_THRESHSTEP_2_0_DB
- OOKPEAK_THRESHSTEP_3_0_DB
- OOKPEAK_THRESHSTEP_4_0_DB
- OOKPEAK_THRESHSTEP_5_0_DB
- OOKPEAK_THRESHSTEP_6_0_DB
- OOKPEAK_THRESHTYPE_AVERAGE
- OOKPEAK_THRESHTYPE_FIXED
- OOKPEAK_THRESHTYPE_PEAK
- OOM_ADJUST_MAX
- OOM_ADJUST_MIN
- OOM_ASYNC
- OOM_CONTROL
- OOM_DISABLE
- OOM_FAILED
- OOM_KILL
- OOM_REFILL
- OOM_SCORE_ADJ_MAX
- OOM_SCORE_ADJ_MIN
- OOM_SKIPPED
- OOM_SUCCESS
- OOO_TXQ_IDX_OFFSET
- OOPS_HDR_VERSION
- OOS_HANDED_TO_NETWORK
- OO_MASK
- OO_SHIFT
- OP
- OP0_L32I_N
- OP0_S32I_N
- OP1_L16SI
- OP1_L16UI
- OP1_L32AI
- OP1_L32I
- OP1_S16I
- OP1_S32I
- OP1_S32RI
- OP1_SI_BIT
- OP1_SI_MASK
- OP2
- OP3
- OP31
- OP59
- OP63
- OPAD_DATA
- OPAL_ACTIVATE
- OPAL_ACTIVEKEY
- OPAL_ADD_PE_TO_DOMAIN
- OPAL_ADMIN1
- OPAL_ADMIN1_UID
- OPAL_ADMINSP_UID
- OPAL_ANYBODY_UID
- OPAL_ASSERT_RESET
- OPAL_ASYNC_COMPLETION
- OPAL_AUTHENTICATE
- OPAL_AUTHORITY_TABLE
- OPAL_BOOLEAN_EXPR
- OPAL_BUSY
- OPAL_BUSY_DELAY_MS
- OPAL_BUSY_EVENT
- OPAL_CALL
- OPAL_CEC_POWER_DOWN
- OPAL_CEC_REBOOT
- OPAL_CEC_REBOOT2
- OPAL_CHECK_ASYNC_COMPLETION
- OPAL_CHECK_TOKEN
- OPAL_CLOSED
- OPAL_COMPARE_RID_DEVICE_NUMBER
- OPAL_COMPARE_RID_FUNCTION_NUMBER
- OPAL_CONFIG_CPU_IDLE_STATE
- OPAL_CONFIG_IDLE_APPLY
- OPAL_CONFIG_IDLE_FASTSLEEP
- OPAL_CONFIG_IDLE_UNDO
- OPAL_CONSOLE_FLUSH
- OPAL_CONSOLE_READ
- OPAL_CONSOLE_WRITE
- OPAL_CONSOLE_WRITE_BUFFER_SPACE
- OPAL_CONSTRAINED
- OPAL_C_PIN_ADMIN1
- OPAL_C_PIN_MSID
- OPAL_C_PIN_SID
- OPAL_C_PIN_TABLE
- OPAL_DEASSERT_RESET
- OPAL_DISABLE_M64
- OPAL_DISABLE_MVE
- OPAL_DISCOVERY_COMID
- OPAL_DTA_TOKENID_BYTESTRING
- OPAL_DTA_TOKENID_INVALID
- OPAL_DTA_TOKENID_SINT
- OPAL_DTA_TOKENID_TOKEN
- OPAL_DTA_TOKENID_UINT
- OPAL_DUMP_ACK
- OPAL_DUMP_INFO
- OPAL_DUMP_INFO2
- OPAL_DUMP_INIT
- OPAL_DUMP_READ
- OPAL_DUMP_REGION_HOST_END
- OPAL_DUMP_REGION_HOST_START
- OPAL_DUMP_REGION_LOG_BUF
- OPAL_DUMP_RESEND
- OPAL_EAUTHENTICATE
- OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
- OPAL_EEH_ACTION_CLEAR_FREEZE_DMA
- OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO
- OPAL_EEH_ACTION_SET_FREEZE_ALL
- OPAL_EEH_ACTION_SET_FREEZE_DMA
- OPAL_EEH_ACTION_SET_FREEZE_MMIO
- OPAL_EEH_IOC_ERROR
- OPAL_EEH_NO_ERROR
- OPAL_EEH_PE_DMA_ERROR
- OPAL_EEH_PE_ERROR
- OPAL_EEH_PE_MMIO_ERROR
- OPAL_EEH_PHB_ERROR
- OPAL_EEH_SEV_INF
- OPAL_EEH_SEV_IOC_DEAD
- OPAL_EEH_SEV_NO_ERROR
- OPAL_EEH_SEV_PE_ER
- OPAL_EEH_SEV_PHB_DEAD
- OPAL_EEH_SEV_PHB_FENCED
- OPAL_EEH_STOPPED_DMA_FREEZE
- OPAL_EEH_STOPPED_MMIO_DMA_FREEZE
- OPAL_EEH_STOPPED_MMIO_FREEZE
- OPAL_EEH_STOPPED_NOT_FROZEN
- OPAL_EEH_STOPPED_PERM_UNAVAIL
- OPAL_EEH_STOPPED_RESET
- OPAL_EEH_STOPPED_TEMP_UNAVAIL
- OPAL_EGET
- OPAL_ELOG_ACK
- OPAL_ELOG_READ
- OPAL_ELOG_RESEND
- OPAL_ELOG_SEND
- OPAL_ELOG_SIZE
- OPAL_ELOG_WRITE
- OPAL_EMPTY
- OPAL_EMPTYATOM
- OPAL_ENABLE_M64_NON_SPLIT
- OPAL_ENABLE_M64_SPLIT
- OPAL_ENABLE_MVE
- OPAL_ENDCOLUMN
- OPAL_ENDLIST
- OPAL_ENDNAME
- OPAL_ENDOFDATA
- OPAL_ENDOFSESSION
- OPAL_ENDROW
- OPAL_ENDTRANSACTON
- OPAL_ENTERPRISE_BANDMASTER0_UID
- OPAL_ENTERPRISE_ERASEMASTER_UID
- OPAL_ENTERPRISE_LOCKINGSP_UID
- OPAL_ENTERPRISE_LOCKING_INFO_TABLE
- OPAL_ERASE
- OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA
- OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER
- OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET
- OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA
- OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER
- OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET
- OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA
- OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA
- OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA
- OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA
- OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA
- OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR
- OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA
- OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR
- OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64
- OPAL_ESET
- OPAL_EVENT_CONSOLE_INPUT
- OPAL_EVENT_CONSOLE_OUTPUT
- OPAL_EVENT_DUMP_AVAIL
- OPAL_EVENT_EPOW
- OPAL_EVENT_ERROR_LOG
- OPAL_EVENT_ERROR_LOG_AVAIL
- OPAL_EVENT_LED_STATUS
- OPAL_EVENT_MSG_PENDING
- OPAL_EVENT_NVRAM
- OPAL_EVENT_OPAL_INTERNAL
- OPAL_EVENT_PCI_ERROR
- OPAL_EVENT_RTC
- OPAL_FADUMP_MIN_BOOT_MEM
- OPAL_FADUMP_VERSION
- OPAL_FALSE
- OPAL_FLASH_ERASE
- OPAL_FLASH_MANAGE
- OPAL_FLASH_READ
- OPAL_FLASH_UPDATE
- OPAL_FLASH_VALIDATE
- OPAL_FLASH_WRITE
- OPAL_GENKEY
- OPAL_GET
- OPAL_GETACL
- OPAL_GET_COMPLETION_TOKEN_STATUS
- OPAL_GET_DEVICE_TREE
- OPAL_GET_DPO_STATUS
- OPAL_GET_EPOW_STATUS
- OPAL_GET_MSG
- OPAL_GET_MSI_32
- OPAL_GET_MSI_64
- OPAL_GET_PARAM
- OPAL_GET_POWERCAP
- OPAL_GET_POWER_SHIFT_RATIO
- OPAL_GET_XIVE
- OPAL_GET_XIVE_SOURCE
- OPAL_HALF_UID_AUTHORITY_OBJ_REF
- OPAL_HALF_UID_BOOLEAN_ACE
- OPAL_HANDLE_HMI
- OPAL_HANDLE_HMI2
- OPAL_HANDLE_INTERRUPT
- OPAL_HARDWARE
- OPAL_HARDWARE_FROZEN
- OPAL_HMI_FLAGS_DEC_LOST
- OPAL_HMI_FLAGS_HDEC_LOST
- OPAL_HMI_FLAGS_NEW_EVENT
- OPAL_HMI_FLAGS_TB_RESYNC
- OPAL_HMI_FLAGS_TOD_TB_FAIL
- OPAL_HOSTPROPERTIES
- OPAL_HYPERVISOR_MAINTENANCE_HANDLER
- OPAL_I2C_ADDR_10
- OPAL_I2C_ARBT_LOST
- OPAL_I2C_BKEND_ACCESS
- OPAL_I2C_BKEND_OVERRUN
- OPAL_I2C_INVALID_CMD
- OPAL_I2C_LBUS_PARITY
- OPAL_I2C_NACK_RCVD
- OPAL_I2C_RAW_READ
- OPAL_I2C_RAW_WRITE
- OPAL_I2C_REQUEST
- OPAL_I2C_SM_READ
- OPAL_I2C_SM_WRITE
- OPAL_I2C_STOP_ERR
- OPAL_I2C_TIMEOUT
- OPAL_IGNORE_RID_DEVICE_NUMBER
- OPAL_IGNORE_RID_FUNCTION_NUMBER
- OPAL_IMC_COUNTERS_CORE
- OPAL_IMC_COUNTERS_INIT
- OPAL_IMC_COUNTERS_NEST
- OPAL_IMC_COUNTERS_START
- OPAL_IMC_COUNTERS_STOP
- OPAL_IMC_COUNTERS_TRACE
- OPAL_INTERNAL_ERROR
- OPAL_INT_EOI
- OPAL_INT_GET_XIRR
- OPAL_INT_SET_CPPR
- OPAL_INT_SET_MFRR
- OPAL_INVALID_CALL
- OPAL_INVAL_PARAM
- OPAL_IO_WINDOW_TYPE
- OPAL_IPMI_MSG_FORMAT_VERSION_1
- OPAL_IPMI_RECV
- OPAL_IPMI_SEND
- OPAL_KEY_MAX
- OPAL_LAST
- OPAL_LEDS_GET_INDICATOR
- OPAL_LEDS_SET_INDICATOR
- OPAL_LIFECYCLE
- OPAL_LK
- OPAL_LOCKINGRANGE_ACE_RDLOCKED
- OPAL_LOCKINGRANGE_ACE_WRLOCKED
- OPAL_LOCKINGRANGE_GLOBAL
- OPAL_LOCKINGSP_UID
- OPAL_LOCKING_INFO_TABLE
- OPAL_LOCKING_LOCKED
- OPAL_LOCKING_READONLY
- OPAL_LOCKING_READWRITE
- OPAL_LPC_FW
- OPAL_LPC_IO
- OPAL_LPC_MEM
- OPAL_LPC_READ
- OPAL_LPC_WRITE
- OPAL_M32_WINDOW_TYPE
- OPAL_M64_WINDOW_TYPE
- OPAL_MACHINE_CHECK_HANDLER
- OPAL_MANUFACTURED_INACTIVE
- OPAL_MAP_PE
- OPAL_MAXRANGES
- OPAL_MAX_ERRLOG_SIZE
- OPAL_MAX_LRS
- OPAL_MBR
- OPAL_MBRCONTROL
- OPAL_MBRDONE
- OPAL_MBRENABLE
- OPAL_MBR_DISABLE
- OPAL_MBR_DONE
- OPAL_MBR_ENABLE
- OPAL_MBR_NOT_DONE
- OPAL_MEM_DYNAMIC_DEALLOC
- OPAL_MEM_ERR_TYPE_DYN_DALLOC
- OPAL_MEM_ERR_TYPE_RESILIENCE
- OPAL_MEM_RESILIENCE_CE
- OPAL_MEM_RESILIENCE_UE
- OPAL_MEM_RESILIENCE_UE_SCRUB
- OPAL_METHOD_LENGTH
- OPAL_MPIPL_ADD_RANGE
- OPAL_MPIPL_FREE_PRESERVED_MEMORY
- OPAL_MPIPL_QUERY_TAG
- OPAL_MPIPL_REGISTER_TAG
- OPAL_MPIPL_REMOVE_ALL
- OPAL_MPIPL_REMOVE_RANGE
- OPAL_MPIPL_TAG_BOOT_MEM
- OPAL_MPIPL_TAG_CPU
- OPAL_MPIPL_TAG_KERNEL
- OPAL_MPIPL_TAG_OPAL
- OPAL_MPIPL_UPDATE
- OPAL_MPIPL_VERSION
- OPAL_MSG_ASYNC_COMP
- OPAL_MSG_DPO
- OPAL_MSG_EPOW
- OPAL_MSG_HMI_EVT
- OPAL_MSG_MEM_ERR
- OPAL_MSG_OCC
- OPAL_MSG_PRD
- OPAL_MSG_PRD2
- OPAL_MSG_SHUTDOWN
- OPAL_MSG_TYPE_MAX
- OPAL_MSID_KEYLEN
- OPAL_NEXT
- OPAL_NMMU_SET_PTCR
- OPAL_NO_MEM
- OPAL_NPU_DESTROY_CONTEXT
- OPAL_NPU_INIT_CONTEXT
- OPAL_NPU_MAP_LPAR
- OPAL_NPU_SPA_CLEAR_CACHE
- OPAL_NPU_SPA_SETUP
- OPAL_NPU_TL_SET
- OPAL_NX_COPROC_INIT
- OPAL_OLD_I2C_REQUEST
- OPAL_P7IOC_DIAG_TYPE_BI
- OPAL_P7IOC_DIAG_TYPE_CI
- OPAL_P7IOC_DIAG_TYPE_I2C
- OPAL_P7IOC_DIAG_TYPE_LAST
- OPAL_P7IOC_DIAG_TYPE_MISC
- OPAL_P7IOC_DIAG_TYPE_NONE
- OPAL_P7IOC_DIAG_TYPE_RGC
- OPAL_P7IOC_NUM_PEST_REGS
- OPAL_PARAMETER
- OPAL_PARTIAL
- OPAL_PCI_CONFIG_READ_BYTE
- OPAL_PCI_CONFIG_READ_HALF_WORD
- OPAL_PCI_CONFIG_READ_WORD
- OPAL_PCI_CONFIG_WRITE_BYTE
- OPAL_PCI_CONFIG_WRITE_HALF_WORD
- OPAL_PCI_CONFIG_WRITE_WORD
- OPAL_PCI_EEH_FREEZE_CLEAR
- OPAL_PCI_EEH_FREEZE_SET
- OPAL_PCI_EEH_FREEZE_STATUS
- OPAL_PCI_EEH_FREEZE_STATUS2
- OPAL_PCI_ERR_INJECT
- OPAL_PCI_FENCE_PHB
- OPAL_PCI_GET_HUB_DIAG_DATA
- OPAL_PCI_GET_PBCQ_TUNNEL_BAR
- OPAL_PCI_GET_PHB_DIAG_DATA
- OPAL_PCI_GET_PHB_DIAG_DATA2
- OPAL_PCI_GET_POWER_STATE
- OPAL_PCI_GET_PRESENCE_STATE
- OPAL_PCI_GET_XIVE_REISSUE
- OPAL_PCI_MAP_PE_DMA_WINDOW
- OPAL_PCI_MAP_PE_DMA_WINDOW_REAL
- OPAL_PCI_MAP_PE_MMIO_WINDOW
- OPAL_PCI_MASK_PE_ERROR
- OPAL_PCI_MSI_EOI
- OPAL_PCI_NEXT_ERROR
- OPAL_PCI_P2P_ENABLE
- OPAL_PCI_P2P_LOAD
- OPAL_PCI_P2P_STORE
- OPAL_PCI_PHB_MMIO_ENABLE
- OPAL_PCI_POLL
- OPAL_PCI_REINIT
- OPAL_PCI_RESET
- OPAL_PCI_SET_HUB_TCE_MEMORY
- OPAL_PCI_SET_MVE
- OPAL_PCI_SET_MVE_ENABLE
- OPAL_PCI_SET_P2P
- OPAL_PCI_SET_PBCQ_TUNNEL_BAR
- OPAL_PCI_SET_PE
- OPAL_PCI_SET_PELTV
- OPAL_PCI_SET_PHB_CAPI_MODE
- OPAL_PCI_SET_PHB_MEM_WINDOW
- OPAL_PCI_SET_PHB_TABLE_MEMORY
- OPAL_PCI_SET_PHB_TCE_MEMORY
- OPAL_PCI_SET_POWER_STATE
- OPAL_PCI_SET_XIVE_PE
- OPAL_PCI_SET_XIVE_REISSUE
- OPAL_PCI_SHPC
- OPAL_PCI_SLOT_EMPTY
- OPAL_PCI_SLOT_OFFLINE
- OPAL_PCI_SLOT_ONLINE
- OPAL_PCI_SLOT_POWER_OFF
- OPAL_PCI_SLOT_POWER_ON
- OPAL_PCI_SLOT_PRESENT
- OPAL_PCI_TCE_KILL
- OPAL_PCI_TCE_KILL_ALL
- OPAL_PCI_TCE_KILL_PAGES
- OPAL_PCI_TCE_KILL_PE
- OPAL_PERMISSION
- OPAL_PHB3_NUM_PEST_REGS
- OPAL_PHB4_NUM_PEST_REGS
- OPAL_PHB_CAPI_MODE_CAPI
- OPAL_PHB_CAPI_MODE_DMA
- OPAL_PHB_CAPI_MODE_DMA_TVT1
- OPAL_PHB_CAPI_MODE_PCIE
- OPAL_PHB_CAPI_MODE_SNOOP_OFF
- OPAL_PHB_CAPI_MODE_SNOOP_ON
- OPAL_PHB_ERROR_DATA_TYPE_P7IOC
- OPAL_PHB_ERROR_DATA_TYPE_PHB3
- OPAL_PHB_ERROR_DATA_TYPE_PHB4
- OPAL_PHB_ERROR_DATA_VERSION_1
- OPAL_PIN
- OPAL_PM_LOSE_FULL_CONTEXT
- OPAL_PM_LOSE_HYP_CONTEXT
- OPAL_PM_NAP_ENABLED
- OPAL_PM_SLEEP_ENABLED
- OPAL_PM_SLEEP_ENABLED_ER1
- OPAL_PM_STOP_INST_DEEP
- OPAL_PM_STOP_INST_FAST
- OPAL_PM_TIMEBASE_STOP
- OPAL_PM_WINKLE_ENABLED
- OPAL_POLL_EVENTS
- OPAL_PRD_GET_INFO
- OPAL_PRD_KERNEL_VERSION
- OPAL_PRD_MSG
- OPAL_PRD_MSG_TYPE_ATTN
- OPAL_PRD_MSG_TYPE_ATTN_ACK
- OPAL_PRD_MSG_TYPE_FINI
- OPAL_PRD_MSG_TYPE_INIT
- OPAL_PRD_MSG_TYPE_OCC_ERROR
- OPAL_PRD_MSG_TYPE_OCC_RESET
- OPAL_PRD_SCOM_READ
- OPAL_PRD_SCOM_WRITE
- OPAL_PROPERTIES
- OPAL_PSID_UID
- OPAL_QUERY_CPU_STATUS
- OPAL_QUIESCE
- OPAL_RANDOM
- OPAL_RANGELENGTH
- OPAL_RANGESTART
- OPAL_READLOCKED
- OPAL_READLOCKENABLED
- OPAL_READ_NVRAM
- OPAL_READ_TPO
- OPAL_REBOOT_FULL_IPL
- OPAL_REBOOT_MPIPL
- OPAL_REBOOT_NORMAL
- OPAL_REBOOT_PLATFORM_ERROR
- OPAL_REGISTER_DUMP_REGION
- OPAL_REGISTER_OPAL_EXCEPTION_HANDLER
- OPAL_REINIT_CPUS
- OPAL_REINIT_CPUS_HILE_BE
- OPAL_REINIT_CPUS_HILE_LE
- OPAL_REINIT_CPUS_MMU_HASH
- OPAL_REINIT_CPUS_MMU_RADIX
- OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED
- OPAL_REINIT_PCI_DEV
- OPAL_REMOVE_PE_FROM_DOMAIN
- OPAL_RESERVED1
- OPAL_RESERVED2
- OPAL_RESET_PCI_FUNDAMENTAL
- OPAL_RESET_PCI_HOT
- OPAL_RESET_PCI_IODA_TABLE
- OPAL_RESET_PCI_LINK
- OPAL_RESET_PHB_COMPLETE
- OPAL_RESET_PHB_ERROR
- OPAL_RESOURCE
- OPAL_RESYNC_TIMEBASE
- OPAL_RETURN_CPU
- OPAL_REVERT
- OPAL_REVERTSP
- OPAL_RO
- OPAL_RTC_READ
- OPAL_RTC_WRITE
- OPAL_RW
- OPAL_SENSOR_GROUP_CLEAR
- OPAL_SENSOR_GROUP_ENABLE
- OPAL_SENSOR_READ
- OPAL_SENSOR_READ_U64
- OPAL_SET
- OPAL_SET_PARAM
- OPAL_SET_POWERCAP
- OPAL_SET_POWER_SHIFT_RATIO
- OPAL_SET_SLOT_LED_STATUS
- OPAL_SET_SYSTEM_ATTENTION_LED
- OPAL_SET_XIVE
- OPAL_SID_UID
- OPAL_SIGNAL_SYSTEM_RESET
- OPAL_SLOT_LED_STATE_OFF
- OPAL_SLOT_LED_STATE_ON
- OPAL_SLOT_LED_TYPE_ATTN
- OPAL_SLOT_LED_TYPE_FAULT
- OPAL_SLOT_LED_TYPE_ID
- OPAL_SLOT_LED_TYPE_MAX
- OPAL_SLW_SET_REG
- OPAL_SMUID_UID
- OPAL_SOFTPATCH_HANDLER
- OPAL_STARTCOLUMN
- OPAL_STARTLIST
- OPAL_STARTNAME
- OPAL_STARTROW
- OPAL_STARTSESSION
- OPAL_STARTTRANSACTON
- OPAL_START_CPU
- OPAL_SUCCESS
- OPAL_SYNC_HOST_REBOOT
- OPAL_SYSCOOL_INSF
- OPAL_SYSEPOW_COOLING
- OPAL_SYSEPOW_MAX
- OPAL_SYSEPOW_POWER
- OPAL_SYSEPOW_TEMP
- OPAL_SYSPARAM_READ
- OPAL_SYSPARAM_RW
- OPAL_SYSPARAM_WRITE
- OPAL_SYSPOWER_CHNG
- OPAL_SYSPOWER_FAIL
- OPAL_SYSPOWER_INCL
- OPAL_SYSPOWER_UPS
- OPAL_SYSTEMP_AMB
- OPAL_SYSTEMP_HMD
- OPAL_SYSTEMP_INT
- OPAL_TABLE
- OPAL_TABLE_COLUMN
- OPAL_TABLE_COLUMNS
- OPAL_TABLE_COMMON
- OPAL_TABLE_KIND
- OPAL_TABLE_LASTID
- OPAL_TABLE_MAX
- OPAL_TABLE_MIN
- OPAL_TABLE_NAME
- OPAL_TABLE_ROWS
- OPAL_TABLE_ROWS_FREE
- OPAL_TABLE_ROW_BYTES
- OPAL_TABLE_TABLE
- OPAL_TABLE_TEMPLATE
- OPAL_TABLE_UID
- OPAL_TEST
- OPAL_THISSP_UID
- OPAL_THREAD_INACTIVE
- OPAL_THREAD_STARTED
- OPAL_THREAD_UNAVAILABLE
- OPAL_TIMEOUT
- OPAL_TRUE
- OPAL_UID_HEXFF
- OPAL_UID_LENGTH
- OPAL_UID_LENGTH_HALF
- OPAL_UNMAP_PE
- OPAL_UNREGISTER_DUMP_REGION
- OPAL_UNSUPPORTED
- OPAL_USER1
- OPAL_USER1_UID
- OPAL_USER2
- OPAL_USER2_UID
- OPAL_USER3
- OPAL_USER4
- OPAL_USER5
- OPAL_USER6
- OPAL_USER7
- OPAL_USER8
- OPAL_USER9
- OPAL_VALUES
- OPAL_WHERE
- OPAL_WIDTH_LONG
- OPAL_WIDTH_MEDIUM
- OPAL_WIDTH_SHORT
- OPAL_WIDTH_TINY
- OPAL_WIDTH_TOKEN
- OPAL_WRITELOCKED
- OPAL_WRITELOCKENABLED
- OPAL_WRITE_NVRAM
- OPAL_WRITE_OPPANEL
- OPAL_WRITE_OPPANEL_ASYNC
- OPAL_WRITE_TPO
- OPAL_WRONG_STATE
- OPAL_XIVE_ALLOCATE_IRQ
- OPAL_XIVE_ALLOCATE_VP_BLOCK
- OPAL_XIVE_ANY_CHIP
- OPAL_XIVE_DONATE_PAGE
- OPAL_XIVE_DUMP
- OPAL_XIVE_EQ_ALWAYS_NOTIFY
- OPAL_XIVE_EQ_ENABLED
- OPAL_XIVE_EQ_ESCALATE
- OPAL_XIVE_FREE_ACTIVE
- OPAL_XIVE_FREE_IRQ
- OPAL_XIVE_FREE_VP_BLOCK
- OPAL_XIVE_GET_IRQ_CONFIG
- OPAL_XIVE_GET_IRQ_INFO
- OPAL_XIVE_GET_QUEUE_INFO
- OPAL_XIVE_GET_QUEUE_STATE
- OPAL_XIVE_GET_VP_INFO
- OPAL_XIVE_GET_VP_STATE
- OPAL_XIVE_IRQ_EOI_VIA_FW
- OPAL_XIVE_IRQ_LSI
- OPAL_XIVE_IRQ_MASK_VIA_FW
- OPAL_XIVE_IRQ_SHIFT_BUG
- OPAL_XIVE_IRQ_STORE_EOI
- OPAL_XIVE_IRQ_TRIGGER_PAGE
- OPAL_XIVE_MODE_EMU
- OPAL_XIVE_MODE_EXPL
- OPAL_XIVE_PROVISIONING
- OPAL_XIVE_RESET
- OPAL_XIVE_SET_IRQ_CONFIG
- OPAL_XIVE_SET_QUEUE_INFO
- OPAL_XIVE_SET_QUEUE_STATE
- OPAL_XIVE_SET_VP_INFO
- OPAL_XIVE_SYNC
- OPAL_XIVE_VP_ENABLED
- OPAL_XIVE_VP_SINGLE_ESCALATION
- OPAL_XSCOM_READ
- OPAL_XSCOM_WRITE
- OPAMP_CK
- OPAQUE
- OPA_16B_AGE_MASK
- OPA_16B_AGE_SHIFT
- OPA_16B_BECN_MASK
- OPA_16B_BECN_SHIFT
- OPA_16B_BTH_PAD_MASK
- OPA_16B_DLID_HIGH_SHFT
- OPA_16B_DLID_HIGH_SHIFT
- OPA_16B_DLID_MASK
- OPA_16B_DLID_SHIFT
- OPA_16B_ENTROPY_MASK
- OPA_16B_FECN_MASK
- OPA_16B_FECN_SHIFT
- OPA_16B_L2_MASK
- OPA_16B_L2_SHIFT
- OPA_16B_L2_TYPE
- OPA_16B_L4_9B
- OPA_16B_L4_ETHR
- OPA_16B_L4_FM
- OPA_16B_L4_FM_HLEN
- OPA_16B_L4_FM_PAD
- OPA_16B_L4_IB_GLOBAL
- OPA_16B_L4_IB_LOCAL
- OPA_16B_L4_MASK
- OPA_16B_LEN_MASK
- OPA_16B_LEN_SHFT
- OPA_16B_LEN_SHIFT
- OPA_16B_LID_MASK
- OPA_16B_MAKE_QW
- OPA_16B_MGMT_QPN_MASK
- OPA_16B_PKEY_MASK
- OPA_16B_PKEY_SHFT
- OPA_16B_PKEY_SHIFT
- OPA_16B_RC_MASK
- OPA_16B_RC_SHFT
- OPA_16B_RC_SHIFT
- OPA_16B_SC_MASK
- OPA_16B_SC_SHFT
- OPA_16B_SC_SHIFT
- OPA_16B_SLID_HIGH_SHFT
- OPA_16B_SLID_HIGH_SHIFT
- OPA_16B_SLID_MASK
- OPA_16B_SLID_SHIFT
- OPA_ACTIVE_TUNING
- OPA_ADDR_H
- OPA_AM_ASYNC
- OPA_AM_ASYNC_MASK
- OPA_AM_ASYNC_SHIFT
- OPA_AM_ASYNC_SMASK
- OPA_AM_CI_ADDR
- OPA_AM_CI_ADDR_MASK
- OPA_AM_CI_ADDR_SHIFT
- OPA_AM_CI_ADDR_SMASK
- OPA_AM_CI_LEN
- OPA_AM_CI_LEN_MASK
- OPA_AM_CI_LEN_SHIFT
- OPA_AM_CI_LEN_SMASK
- OPA_AM_NBLK
- OPA_AM_NBLK_MASK
- OPA_AM_NBLK_SHIFT
- OPA_AM_NBLK_SMASK
- OPA_AM_NPORT
- OPA_AM_NPORT_MASK
- OPA_AM_NPORT_SHIFT
- OPA_AM_NPORT_SMASK
- OPA_AM_PORTNUM
- OPA_AM_PORTNUM_MASK
- OPA_AM_PORTNUM_SHIFT
- OPA_AM_PORTNUM_SMASK
- OPA_AM_START_BLK
- OPA_AM_START_BLK_MASK
- OPA_AM_START_BLK_SHIFT
- OPA_AM_START_BLK_SMASK
- OPA_AM_START_SM_CFG
- OPA_AM_START_SM_CFG_MASK
- OPA_AM_START_SM_CFG_SHIFT
- OPA_AM_START_SM_CFG_SMASK
- OPA_ATTRIB_ID_AGGREGATE
- OPA_ATTRIB_ID_BUFFER_CONTROL_TABLE
- OPA_ATTRIB_ID_CABLE_INFO
- OPA_ATTRIB_ID_CONGESTION_CONTROL_TABLE
- OPA_ATTRIB_ID_CONGESTION_INFO
- OPA_ATTRIB_ID_HFI_CONGESTION_LOG
- OPA_ATTRIB_ID_HFI_CONGESTION_SETTING
- OPA_ATTRIB_ID_NODE_DESCRIPTION
- OPA_ATTRIB_ID_NODE_INFO
- OPA_ATTRIB_ID_PARTITION_TABLE
- OPA_ATTRIB_ID_PORT_INFO
- OPA_ATTRIB_ID_PORT_STATE_INFO
- OPA_ATTRIB_ID_SC_TO_SL_MAP
- OPA_ATTRIB_ID_SC_TO_VLNT_MAP
- OPA_ATTRIB_ID_SC_TO_VLR_MAP
- OPA_ATTRIB_ID_SC_TO_VLT_MAP
- OPA_ATTRIB_ID_SL_TO_SC_MAP
- OPA_ATTRIB_ID_SM_INFO
- OPA_ATTRIB_ID_VL_ARBITRATION
- OPA_BTH_MIG_REQ
- OPA_CAP_MASK3_IsAddrRangeConfigSupported
- OPA_CAP_MASK3_IsAsyncSC2VLSupported
- OPA_CAP_MASK3_IsEthOnFabricSupported
- OPA_CAP_MASK3_IsPassThroughSupported
- OPA_CAP_MASK3_IsSharedSpaceSupported
- OPA_CAP_MASK3_IsSnoopSupported
- OPA_CAP_MASK3_IsVLMarkerSupported
- OPA_CAP_MASK3_IsVLrSupported
- OPA_CC_LOG_TYPE_HFI
- OPA_CLASSPORTINFO_REC_FIELD
- OPA_CLASS_PORT_INFO_PR_SUPPORT
- OPA_COLLECTIVE_NR
- OPA_CONG_LOG_ELEMS
- OPA_DEFAULT_GID_PREFIX
- OPA_EI_CODE_SMASK
- OPA_EI_STATUS_SMASK
- OPA_EMA_CLASS_VERSION
- OPA_EM_ATTR_CLASS_PORT_INFO
- OPA_EM_ATTR_DELETE_VESW
- OPA_EM_ATTR_IFACE_MCAST_MACS
- OPA_EM_ATTR_IFACE_UCAST_MACS
- OPA_EM_ATTR_VESWPORT_ERROR_COUNTERS
- OPA_EM_ATTR_VESWPORT_INFO
- OPA_EM_ATTR_VESWPORT_MAC_ENTRIES
- OPA_EM_ATTR_VESWPORT_SUMMARY_COUNTERS
- OPA_GID_INDEX
- OPA_INTEL_EMA_NOTICE_TYPE_INFO
- OPA_INVALID_INDEX
- OPA_LDR_FMCONFIG_OFFSET
- OPA_LDR_PORTRCV_OFFSET
- OPA_LED_MASK
- OPA_LED_SHIFT
- OPA_LID_PERMISSIVE
- OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT
- OPA_LINKDOWN_REASON_BAD_CREDIT_ACK
- OPA_LINKDOWN_REASON_BAD_CTRL_DIST
- OPA_LINKDOWN_REASON_BAD_DLID
- OPA_LINKDOWN_REASON_BAD_HEAD_DIST
- OPA_LINKDOWN_REASON_BAD_L2
- OPA_LINKDOWN_REASON_BAD_MID_TAIL
- OPA_LINKDOWN_REASON_BAD_PKT_LEN
- OPA_LINKDOWN_REASON_BAD_PREEMPT
- OPA_LINKDOWN_REASON_BAD_SC
- OPA_LINKDOWN_REASON_BAD_SLID
- OPA_LINKDOWN_REASON_BAD_TAIL_DIST
- OPA_LINKDOWN_REASON_BAD_VL_MARKER
- OPA_LINKDOWN_REASON_CHASSIS_CONFIG
- OPA_LINKDOWN_REASON_DISCONNECTED
- OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED
- OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT
- OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN
- OPA_LINKDOWN_REASON_FM_BOUNCE
- OPA_LINKDOWN_REASON_LINKSPEED_POLICY
- OPA_LINKDOWN_REASON_LINKWIDTH_POLICY
- OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED
- OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN
- OPA_LINKDOWN_REASON_NONE
- OPA_LINKDOWN_REASON_NOT_INSTALLED
- OPA_LINKDOWN_REASON_PKT_TOO_LONG
- OPA_LINKDOWN_REASON_PKT_TOO_SHORT
- OPA_LINKDOWN_REASON_POWER_POLICY
- OPA_LINKDOWN_REASON_PREEMPT_ERROR
- OPA_LINKDOWN_REASON_PREEMPT_VL15
- OPA_LINKDOWN_REASON_RCV_ERROR_0
- OPA_LINKDOWN_REASON_RCV_ERROR_10
- OPA_LINKDOWN_REASON_RCV_ERROR_14
- OPA_LINKDOWN_REASON_RCV_ERROR_15
- OPA_LINKDOWN_REASON_RCV_ERROR_24
- OPA_LINKDOWN_REASON_RCV_ERROR_25
- OPA_LINKDOWN_REASON_RCV_ERROR_26
- OPA_LINKDOWN_REASON_RCV_ERROR_27
- OPA_LINKDOWN_REASON_RCV_ERROR_28
- OPA_LINKDOWN_REASON_RCV_ERROR_29
- OPA_LINKDOWN_REASON_RCV_ERROR_30
- OPA_LINKDOWN_REASON_RCV_ERROR_8
- OPA_LINKDOWN_REASON_REBOOT
- OPA_LINKDOWN_REASON_SMA_DISABLED
- OPA_LINKDOWN_REASON_SPEED_POLICY
- OPA_LINKDOWN_REASON_SWITCH_MGMT
- OPA_LINKDOWN_REASON_TRANSIENT
- OPA_LINKDOWN_REASON_UNKNOWN
- OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER
- OPA_LINKDOWN_REASON_WIDTH_POLICY
- OPA_LINKINIT_INSUFIC_CAPABILITY
- OPA_LINKINIT_OUTSIDE_POLICY
- OPA_LINKINIT_QUARANTINED
- OPA_LINKINIT_REASON_CLEAR
- OPA_LINKINIT_REASON_FLAPPING
- OPA_LINKINIT_REASON_LINKUP
- OPA_LINKINIT_REASON_NOP
- OPA_LINK_SPEED_12_5G
- OPA_LINK_SPEED_25G
- OPA_LINK_SPEED_NOP
- OPA_LINK_WIDTH_1X
- OPA_LINK_WIDTH_2X
- OPA_LINK_WIDTH_3X
- OPA_LINK_WIDTH_4X
- OPA_LINK_WIDTH_RESET
- OPA_LINK_WIDTH_RESET_OLD
- OPA_MAKE_ID
- OPA_MAX_PREEMPT_CAP
- OPA_MAX_SCS
- OPA_MAX_SLS
- OPA_MAX_VLS
- OPA_MCAST_NR
- OPA_MGMT_BASE_VERSION
- OPA_MGMT_CLASS_INTEL_EMA
- OPA_MGMT_MAD_DATA
- OPA_MGMT_MAD_SIZE
- OPA_MGMT_RMPP_DATA
- OPA_MODE_EN
- OPA_MODE_EN_MASK
- OPA_MTU_0
- OPA_MTU_1024
- OPA_MTU_10240
- OPA_MTU_2048
- OPA_MTU_256
- OPA_MTU_4096
- OPA_MTU_512
- OPA_MTU_8192
- OPA_NOTICE_TRAP_LSE_CHG
- OPA_NOTICE_TRAP_LWDE_CHG
- OPA_NOTICE_TRAP_LWE_CHG
- OPA_NOTICE_TRAP_NODE_DESC_CHG
- OPA_NUM_PKEY_BLOCKS_PER_SMP
- OPA_PARTITION_TABLE_BLK_SIZE
- OPA_PASSIVE_TUNING
- OPA_PATH_REC_FIELD
- OPA_PI_MASK_BUF_UNIT_BUF_ALLOC
- OPA_PI_MASK_BUF_UNIT_CREDIT_ACK
- OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE
- OPA_PI_MASK_BUF_UNIT_VL15_INIT
- OPA_PI_MASK_CLIENT_REREGISTER
- OPA_PI_MASK_COLLECT_MASK
- OPA_PI_MASK_DOWNDEF_STATE
- OPA_PI_MASK_EX_BUFFER_OVERRUN
- OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT
- OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK
- OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST
- OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST
- OPA_PI_MASK_FM_CFG_BAD_PREEMPT
- OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST
- OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT
- OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER
- OPA_PI_MASK_HOQ_LIFE
- OPA_PI_MASK_INTERLEAVE_DIST_ENABLE
- OPA_PI_MASK_INTERLEAVE_DIST_SUP
- OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX
- OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX
- OPA_PI_MASK_LED_ENABLE
- OPA_PI_MASK_LINKINIT_REASON
- OPA_PI_MASK_LMC
- OPA_PI_MASK_LOCAL_PHY_ERRORS
- OPA_PI_MASK_MKEY_PROT_BIT
- OPA_PI_MASK_MTU_CAP
- OPA_PI_MASK_MULTICAST_MASK
- OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS
- OPA_PI_MASK_NEIGH_MGMT_ALLOWED
- OPA_PI_MASK_NEIGH_MTU_PVL0
- OPA_PI_MASK_NEIGH_MTU_PVL1
- OPA_PI_MASK_NEIGH_NODE_TYPE
- OPA_PI_MASK_OFFLINE_REASON
- OPA_PI_MASK_OPERATIONAL_VL
- OPA_PI_MASK_OVERRUN_ERRORS
- OPA_PI_MASK_PARTITION_ENFORCE_IN
- OPA_PI_MASK_PARTITION_ENFORCE_OUT
- OPA_PI_MASK_PASS_THROUGH_DR_CONTROL
- OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE
- OPA_PI_MASK_PORT_LINK_ACTIVE
- OPA_PI_MASK_PORT_LINK_CRC_ACTIVE
- OPA_PI_MASK_PORT_LINK_CRC_ENABLED
- OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED
- OPA_PI_MASK_PORT_LINK_ENABLED
- OPA_PI_MASK_PORT_LINK_SUPPORTED
- OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY
- OPA_PI_MASK_PORT_MODE_PKEY_CONVERT
- OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING
- OPA_PI_MASK_PORT_MODE_SECURITY_CHECK
- OPA_PI_MASK_PORT_MODE_VL_MARKER
- OPA_PI_MASK_PORT_PASS_THROUGH
- OPA_PI_MASK_PORT_PHYSICAL_CONF
- OPA_PI_MASK_PORT_PHYSICAL_STATE
- OPA_PI_MASK_PORT_RCV_BAD_DLID
- OPA_PI_MASK_PORT_RCV_BAD_L2
- OPA_PI_MASK_PORT_RCV_BAD_LT
- OPA_PI_MASK_PORT_RCV_BAD_MidTail
- OPA_PI_MASK_PORT_RCV_BAD_PKTLEN
- OPA_PI_MASK_PORT_RCV_BAD_SC
- OPA_PI_MASK_PORT_RCV_BAD_SLID
- OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER
- OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG
- OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT
- OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR
- OPA_PI_MASK_PORT_RCV_PREEMPT_VL15
- OPA_PI_MASK_PORT_STATE
- OPA_PI_MASK_RESPONSE_TIME_VALUE
- OPA_PI_MASK_SA_QP
- OPA_PI_MASK_SMSL
- OPA_PI_MASK_SM_TRAP_QP
- OPA_PI_MASK_SUBNET_TIMEOUT
- OPA_PI_MASK_UNSLEEP_STATE
- OPA_PI_MASK_VL_CAP
- OPA_PI_MASK_VL_STALL
- OPA_PM_ATTRIB_ID_CLEAR_PORT_STATUS
- OPA_PM_ATTRIB_ID_DATA_PORT_COUNTERS
- OPA_PM_ATTRIB_ID_ERROR_INFO
- OPA_PM_ATTRIB_ID_ERROR_PORT_COUNTERS
- OPA_PM_ATTRIB_ID_PORT_STATUS
- OPA_PM_STATUS_REQUEST_TOO_LARGE
- OPA_PORTPHYSSTATE_MAX
- OPA_PORTPHYSSTATE_OFFLINE
- OPA_PORTPHYSSTATE_TEST
- OPA_PORT_INFO_H
- OPA_PORT_LINK_MODE_NOP
- OPA_PORT_LINK_MODE_OPA
- OPA_PORT_LTP_CRC_MODE_14
- OPA_PORT_LTP_CRC_MODE_16
- OPA_PORT_LTP_CRC_MODE_48
- OPA_PORT_LTP_CRC_MODE_NONE
- OPA_PORT_LTP_CRC_MODE_PER_LANE
- OPA_PORT_PACKET_FORMAT_10B
- OPA_PORT_PACKET_FORMAT_16B
- OPA_PORT_PACKET_FORMAT_8B
- OPA_PORT_PACKET_FORMAT_9B
- OPA_PORT_PACKET_FORMAT_NOP
- OPA_PORT_PHYS_CONF_DISCONNECTED
- OPA_PORT_PHYS_CONF_FIXED
- OPA_PORT_PHYS_CONF_SI_PHOTO
- OPA_PORT_PHYS_CONF_STANDARD
- OPA_PORT_PHYS_CONF_VARIABLE
- OPA_SA_CLASS_VERSION
- OPA_SMA_TRAP_DATA_LINK_WIDTH
- OPA_SMI_H
- OPA_SMP_DR_DATA_SIZE
- OPA_SMP_LID_DATA_SIZE
- OPA_SMP_MAX_PATH_HOPS
- OPA_SM_CLASS_VERSION
- OPA_SPECIAL_OUI
- OPA_TO_IB_UCAST_LID
- OPA_TRAL_DEL_MULTICAST_GROUP
- OPA_TRAP_ADD_MULTICAST_GROUP
- OPA_TRAP_BAD_M_KEY
- OPA_TRAP_BAD_P_KEY
- OPA_TRAP_BAD_Q_KEY
- OPA_TRAP_CHANGE_CAPABILITY
- OPA_TRAP_CHANGE_SYSGUID
- OPA_TRAP_EXCESSIVE_BUFFER_OVERRUN
- OPA_TRAP_FLOW_WATCHDOG
- OPA_TRAP_GID_NOW_IN_SERVICE
- OPA_TRAP_GID_OUT_OF_SERVICE
- OPA_TRAP_LINK_INTEGRITY
- OPA_TRAP_PORT_CHANGE_STATE
- OPA_TRAP_REPATH
- OPA_TRAP_SWITCH_BAD_PKEY
- OPA_TRAP_UNPATH
- OPA_TX_TIMEOUT_MS
- OPA_UNKNOWN_TUNING
- OPA_VESWPORT_TRAP_ETH_LINK_STATUS_CHANGE
- OPA_VESWPORT_TRAP_IFACE_MCAST_MAC_CHANGE
- OPA_VESWPORT_TRAP_IFACE_UCAST_MAC_CHANGE
- OPA_VESW_MAX_NUM_DEF_PORT
- OPA_VLARB_HIGH_ELEMENTS
- OPA_VLARB_LOW_ELEMENTS
- OPA_VLARB_PREEMPT_ELEMENTS
- OPA_VLARB_PREEMPT_MATRIX
- OPA_VNIC_CLASS_CAP_TRAP
- OPA_VNIC_DLID_SD_GET_DLID
- OPA_VNIC_DLID_SD_IS_SRC_MAC
- OPA_VNIC_EMA_DATA
- OPA_VNIC_ENCAP_RC_DEFAULT
- OPA_VNIC_ENCAP_RC_EXT
- OPA_VNIC_ENCAP_RC_IPV4
- OPA_VNIC_ENCAP_RC_IPV4_TCP
- OPA_VNIC_ENCAP_RC_IPV4_UDP
- OPA_VNIC_ENCAP_RC_IPV6
- OPA_VNIC_ENCAP_RC_IPV6_TCP
- OPA_VNIC_ENCAP_RC_IPV6_UDP
- OPA_VNIC_ETH_LINK_DOWN
- OPA_VNIC_ETH_LINK_UP
- OPA_VNIC_FLOW_TBL_SIZE
- OPA_VNIC_HDR_LEN
- OPA_VNIC_HDR_QW_LEN
- OPA_VNIC_ICRC_LEN
- OPA_VNIC_ICRC_TAIL_LEN
- OPA_VNIC_INVALID_PORT
- OPA_VNIC_INVAL_ATTR
- OPA_VNIC_L2_HDR_LEN
- OPA_VNIC_L4_ETHR
- OPA_VNIC_L4_HDR_LEN
- OPA_VNIC_L4_HDR_SHFT
- OPA_VNIC_MAC_HASH_IDX
- OPA_VNIC_MAC_TBL_HASH_BITS
- OPA_VNIC_MAC_TBL_MAX_ENTRIES
- OPA_VNIC_MAC_TBL_SIZE
- OPA_VNIC_MAX_NUM_PCP
- OPA_VNIC_MAX_NUM_VPORT
- OPA_VNIC_MAX_SMAC_LIMIT
- OPA_VNIC_SKB_HEADROOM
- OPA_VNIC_SKB_MDATA_ENCAP_ERR
- OPA_VNIC_SKB_MDATA_LEN
- OPA_VNIC_STATE_DROP_ALL
- OPA_VNIC_STATE_FORWARDING
- OPA_VNIC_TAIL_LEN
- OPA_VNIC_TRAP_BURST_LIMIT
- OPA_VNIC_TRAP_TIMEOUT
- OPA_VNIC_UNSUP_ATTR
- OPA_VNIC_VLAN_PCP
- OPC2_MASK
- OPC2_OFFSET
- OPCODE
- OPCODE1
- OPCODE1_MASK
- OPCODE2
- OPCODE2_MASK
- OPCODE3
- OPCODE3_MASK
- OPCODE4
- OPCODE4_MASK
- OPCODES
- OPCODE_ACTIVATE_VCIN
- OPCODE_ACTIVATE_VCOUT
- OPCODE_ADD
- OPCODE_AT_BLOCK_ERASE
- OPCODE_AT_BUF1_COMPARE
- OPCODE_AT_BUF1_ERASE_PROGRAM
- OPCODE_AT_BUF1_LOAD
- OPCODE_AT_BUF1_PROGRAM
- OPCODE_AT_BUF1_REPROGRAM
- OPCODE_AT_BUF1_WRITE
- OPCODE_AT_BUF1_WRITE_ERASE_PROGRAM
- OPCODE_AT_BUF2_COMPARE
- OPCODE_AT_BUF2_ERASE_PROGRAM
- OPCODE_AT_BUF2_LOAD
- OPCODE_AT_BUF2_PROGRAM
- OPCODE_AT_BUF2_REPROGRAM
- OPCODE_AT_BUF2_WRITE
- OPCODE_AT_BUF2_WRITE_ERASE_PROGRAM
- OPCODE_AT_PAGE_ERASE
- OPCODE_AT_PAGE_READ
- OPCODE_AT_READ
- OPCODE_AT_STATUS
- OPCODE_AUTH_MAC
- OPCODE_BF
- OPCODE_BFS
- OPCODE_BF_S
- OPCODE_BITS
- OPCODE_BRA
- OPCODE_BRAF
- OPCODE_BRAF_REG
- OPCODE_BRA_DISP
- OPCODE_BSR
- OPCODE_BSRF
- OPCODE_BSRF_REG
- OPCODE_BSR_DISP
- OPCODE_BT
- OPCODE_BTF_DISP
- OPCODE_BTS
- OPCODE_BT_S
- OPCODE_BUFSIZE
- OPCODE_CHECK_MASK_DISABLED
- OPCODE_CHECK_VAL_DISABLED
- OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS
- OPCODE_COMMON_CQ_CREATE
- OPCODE_COMMON_CQ_DESTROY
- OPCODE_COMMON_DELETE_OBJECT
- OPCODE_COMMON_ENABLE_DISABLE_BEACON
- OPCODE_COMMON_ENABLE_DISABLE_VF
- OPCODE_COMMON_EQ_CREATE
- OPCODE_COMMON_EQ_DESTROY
- OPCODE_COMMON_FIRMWARE_CONFIG
- OPCODE_COMMON_FUNCTION_RESET
- OPCODE_COMMON_GET_ACTIVE_PROFILE
- OPCODE_COMMON_GET_BEACON_STATE
- OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
- OPCODE_COMMON_GET_CNTL_ATTRIBUTES
- OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES
- OPCODE_COMMON_GET_FLOW_CONTROL
- OPCODE_COMMON_GET_FN_PRIVILEGES
- OPCODE_COMMON_GET_FUNC_CONFIG
- OPCODE_COMMON_GET_FW_VERSION
- OPCODE_COMMON_GET_HSW_CONFIG
- OPCODE_COMMON_GET_IFACE_LIST
- OPCODE_COMMON_GET_MAC_LIST
- OPCODE_COMMON_GET_PHY_DETAILS
- OPCODE_COMMON_GET_PORT_NAME
- OPCODE_COMMON_GET_PROFILE_CONFIG
- OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES
- OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES
- OPCODE_COMMON_ISCSI_CLEANUP
- OPCODE_COMMON_ISCSI_DEFQ_CREATE
- OPCODE_COMMON_ISCSI_DEFQ_DESTROY
- OPCODE_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS
- OPCODE_COMMON_ISCSI_NTWK_CONFIG_STATELESS_IP_ADDR
- OPCODE_COMMON_ISCSI_NTWK_GET_ALL_IF_ID
- OPCODE_COMMON_ISCSI_NTWK_GET_DEFAULT_GATEWAY
- OPCODE_COMMON_ISCSI_NTWK_GET_IF_INFO
- OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG
- OPCODE_COMMON_ISCSI_NTWK_MODIFY_DEFAULT_GATEWAY
- OPCODE_COMMON_ISCSI_NTWK_MODIFY_IP_ADDR
- OPCODE_COMMON_ISCSI_NTWK_REL_STATELESS_IP_ADDR
- OPCODE_COMMON_ISCSI_NTWK_SET_VLAN
- OPCODE_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA
- OPCODE_COMMON_ISCSI_TCP_CONNECT_AND_OFFLOAD
- OPCODE_COMMON_ISCSI_WRBQ_CREATE
- OPCODE_COMMON_ISCSI_WRBQ_DESTROY
- OPCODE_COMMON_MANAGE_FAT
- OPCODE_COMMON_MANAGE_IFACE_FILTERS
- OPCODE_COMMON_MCC_CREATE
- OPCODE_COMMON_MCC_CREATE_EXT
- OPCODE_COMMON_MCC_DESTROY
- OPCODE_COMMON_MODIFY_EQ_DELAY
- OPCODE_COMMON_NTWK_INTERFACE_CREATE
- OPCODE_COMMON_NTWK_INTERFACE_DESTROY
- OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
- OPCODE_COMMON_NTWK_MAC_QUERY
- OPCODE_COMMON_NTWK_MAC_SET
- OPCODE_COMMON_NTWK_MULTICAST_SET
- OPCODE_COMMON_NTWK_PMAC_ADD
- OPCODE_COMMON_NTWK_PMAC_DEL
- OPCODE_COMMON_NTWK_RX_FILTER
- OPCODE_COMMON_NTWK_VLAN_CONFIG
- OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
- OPCODE_COMMON_READ_FLASH
- OPCODE_COMMON_READ_FLASHROM
- OPCODE_COMMON_READ_OBJECT
- OPCODE_COMMON_READ_TRANSRECV_DATA
- OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS
- OPCODE_COMMON_SEEPROM_READ
- OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP
- OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES
- OPCODE_COMMON_SET_FEATURES
- OPCODE_COMMON_SET_FLOW_CONTROL
- OPCODE_COMMON_SET_FN_PRIVILEGES
- OPCODE_COMMON_SET_FRAME_SIZE
- OPCODE_COMMON_SET_HOST_DATA
- OPCODE_COMMON_SET_HSW_CONFIG
- OPCODE_COMMON_SET_INTERRUPT_ENABLE
- OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG
- OPCODE_COMMON_SET_MAC_LIST
- OPCODE_COMMON_SET_PROFILE_CONFIG
- OPCODE_COMMON_SET_QOS
- OPCODE_COMMON_TCP_UPLOAD
- OPCODE_COMMON_WRITE_FLASH
- OPCODE_COMMON_WRITE_FLASHROM
- OPCODE_COMMON_WRITE_OBJECT
- OPCODE_COPY
- OPCODE_CORE
- OPCODE_CTRL_REG
- OPCODE_DEACTIVATE_VCIN
- OPCODE_DEACTIVATE_VCOUT
- OPCODE_DELETE
- OPCODE_DIOR
- OPCODE_DIOR_4B
- OPCODE_ECDH
- OPCODE_ENCRYPT
- OPCODE_ERROR_INT_ENABLE
- OPCODE_ETH_ACPI_CONFIG
- OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
- OPCODE_ETH_GET_PPORT_STATS
- OPCODE_ETH_GET_STATISTICS
- OPCODE_ETH_PROMISCUOUS
- OPCODE_ETH_RSS_CONFIG
- OPCODE_ETH_RX_CREATE
- OPCODE_ETH_RX_DESTROY
- OPCODE_ETH_TX_CREATE
- OPCODE_ETH_TX_DESTROY
- OPCODE_FLDDS
- OPCODE_FLDDX
- OPCODE_FLDD_L
- OPCODE_FLDWS
- OPCODE_FLDWSR
- OPCODE_FLDWX
- OPCODE_FLDWXR
- OPCODE_FLDW_L
- OPCODE_FSTDS
- OPCODE_FSTDX
- OPCODE_FSTD_L
- OPCODE_FSTWS
- OPCODE_FSTWSR
- OPCODE_FSTWX
- OPCODE_FSTWXR
- OPCODE_FSTW_L
- OPCODE_FUNC_ID_MASK
- OPCODE_GENKEY
- OPCODE_GET_OC3
- OPCODE_GET_PROM
- OPCODE_GET_STATS
- OPCODE_IB_3032_IP_IOCB
- OPCODE_IB_3032_MAC_IOCB
- OPCODE_IB_AE_IOCB
- OPCODE_IB_IP_IOCB
- OPCODE_IB_MAC_IOCB
- OPCODE_IB_MPI_IOCB
- OPCODE_INITIALIZE
- OPCODE_INPLACE_BIT
- OPCODE_INVALID
- OPCODE_ISCSI_INI_BOOT_GET_BOOT_TARGET
- OPCODE_ISCSI_INI_CFG_GET_HBA_NAME
- OPCODE_ISCSI_INI_CFG_SET_HBA_NAME
- OPCODE_ISCSI_INI_DRIVER_INVALIDATE_CONNECTION
- OPCODE_ISCSI_INI_DRIVER_OFFLOAD_SESSION
- OPCODE_ISCSI_INI_DRIVER_REOPEN_ALL_SESSIONS
- OPCODE_ISCSI_INI_SESSION_GET_A_SESSION
- OPCODE_ISCSI_INI_SESSION_LOGOUT_TARGET
- OPCODE_JMP
- OPCODE_JMP_REG
- OPCODE_JSR
- OPCODE_JSR_REG
- OPCODE_LDCD_I
- OPCODE_LDCD_S
- OPCODE_LDCW_I
- OPCODE_LDCW_S
- OPCODE_LDDA_I
- OPCODE_LDDA_S
- OPCODE_LDD_I
- OPCODE_LDD_L
- OPCODE_LDD_S
- OPCODE_LDH_I
- OPCODE_LDH_L
- OPCODE_LDH_S
- OPCODE_LDWA_I
- OPCODE_LDWA_S
- OPCODE_LDWM
- OPCODE_LDW_I
- OPCODE_LDW_L
- OPCODE_LDW_M
- OPCODE_LDW_S
- OPCODE_LOWLEVEL_HOST_DDR_DMA
- OPCODE_LOWLEVEL_LOOPBACK_TEST
- OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
- OPCODE_MASK
- OPCODE_MASK_BITS
- OPCODE_NIC
- OPCODE_NIC_CMD
- OPCODE_NIC_CORE_DRV_ACTIVE
- OPCODE_NIC_IF_CFG
- OPCODE_NIC_INFO
- OPCODE_NIC_INTRMOD_CFG
- OPCODE_NIC_INTRMOD_PARAMS
- OPCODE_NIC_MDIO45
- OPCODE_NIC_NW_DATA
- OPCODE_NIC_PORT_STATS
- OPCODE_NIC_QCOUNT_UPDATE
- OPCODE_NIC_SET_TRUSTED_VF
- OPCODE_NIC_SYNC_OCTEON_TIME
- OPCODE_NIC_TIMESTAMP
- OPCODE_NIC_UBOOT_CTL
- OPCODE_NIC_VF_DRV_NOTICE
- OPCODE_NIC_VF_PORT_STATS
- OPCODE_NIC_VF_REP_CMD
- OPCODE_NIC_VF_REP_PKT
- OPCODE_NONE
- OPCODE_NOP
- OPCODE_OB_MAC_IOCB
- OPCODE_OB_MAC_IOCB_FN0
- OPCODE_OB_MAC_IOCB_FN2
- OPCODE_OB_MAC_TSO_IOCB
- OPCODE_OFFSET
- OPCODE_POLL_LIST
- OPCODE_POLL_READ_LIST
- OPCODE_POLL_WRITE_LIST
- OPCODE_PRIV_VALID
- OPCODE_QIOR
- OPCODE_QIOR_4B
- OPCODE_RANDOM
- OPCODE_RDID
- OPCODE_READ
- OPCODE_READ_MODIFY_WRITE
- OPCODE_READ_WRITE_LIST
- OPCODE_REQUEST_INTR
- OPCODE_RESET_STATS
- OPCODE_RTE
- OPCODE_RTS
- OPCODE_SEQ_END
- OPCODE_SEQ_PAUSE
- OPCODE_SET_OC3
- OPCODE_SET_VPI_BITS
- OPCODE_SSL_KEYBLOCK
- OPCODE_STD
- OPCODE_STDA
- OPCODE_STD_L
- OPCODE_STH
- OPCODE_STH_L
- OPCODE_STW
- OPCODE_STWA
- OPCODE_STWM
- OPCODE_STW_L
- OPCODE_STW_M
- OPCODE_ST_BE
- OPCODE_ST_CSA
- OPCODE_ST_DP
- OPCODE_ST_PP
- OPCODE_ST_RDSR
- OPCODE_ST_READ
- OPCODE_ST_READ4B
- OPCODE_ST_RES
- OPCODE_ST_SE
- OPCODE_ST_SSE
- OPCODE_ST_WRDIS
- OPCODE_ST_WREN
- OPCODE_ST_WRSR
- OPCODE_SUBCODE
- OPCODE_TID
- OPCODE_TMPL_END
- OPCODE_UPDATE
- OPCODE_USER_VALID
- OPCODE_WRITE_LIST
- OPCR_FLAG
- OPCR_MPOa_C_TO
- OPCR_MPOa_RTSN
- OPCR_MPOa_RxC16X
- OPCR_MPOa_RxC1X
- OPCR_MPOa_RxRDY_FF
- OPCR_MPOa_TxC16X
- OPCR_MPOa_TxC1X
- OPCR_MPOa_TxRDY
- OPCR_MPOb_C_TO
- OPCR_MPOb_RTSN
- OPCR_MPOb_RxC16X
- OPCR_MPOb_RxC1X
- OPCR_MPOb_RxRDY_FF
- OPCR_MPOb_TxC16X
- OPCR_MPOb_TxC1X
- OPCR_MPOb_TxRDY
- OPCR_MPP_INPUT
- OPCR_MPP_OUTPUT
- OPCR_OVERHEAD_ID_MASK
- OPCR_OVERHEAD_ID_SHIFT
- OPCR_SPEED_MASK
- OPCR_SPEED_SHIFT
- OPCR_SPENDH
- OPCR_SPENDN0
- OPCR_SPENDN1
- OPCR_XSPEED_MASK
- OPCR_XSPEED_SHIFT
- OPC_2E_INEXACTEXCEPTION
- OPC_2E_INVALIDEXCEPTION
- OPC_2E_OVERFLOWEXCEPTION
- OPC_2E_UNDERFLOWEXCEPTION
- OPC_AUIPC
- OPC_FLTC
- OPC_FLTI
- OPC_FLTL
- OPC_FLTV
- OPC_INB_DEK_MANAGEMENT
- OPC_INB_DEREG_DEV_HANDLE
- OPC_INB_DEV_HANDLE_ACCEPT
- OPC_INB_ECHO
- OPC_INB_FLASH_OP_EXT
- OPC_INB_FW_FLASH_UPDATE
- OPC_INB_GET_CONTROLLER_CONFIG
- OPC_INB_GET_DEVICE_INFO
- OPC_INB_GET_DEVICE_STATE
- OPC_INB_GET_DEV_HANDLE
- OPC_INB_GET_DEV_INFO
- OPC_INB_GET_NVMD_DATA
- OPC_INB_GET_PHY_PROFILE
- OPC_INB_GET_TIME_STAMP
- OPC_INB_GPIO
- OPC_INB_KEK_MANAGEMENT
- OPC_INB_LOCAL_PHY_CONTROL
- OPC_INB_PCIE_DIAG_EXEC
- OPC_INB_PHYSTART
- OPC_INB_PHYSTOP
- OPC_INB_PORT_CONTROL
- OPC_INB_REG_DEV
- OPC_INB_RSVD
- OPC_INB_RSVD1
- OPC_INB_RSVD2
- OPC_INB_RSVD3
- OPC_INB_RSVD4
- OPC_INB_SAS_DIAG_EXECUTE
- OPC_INB_SAS_DIAG_MODE_START_END
- OPC_INB_SAS_HW_EVENT_ACK
- OPC_INB_SAS_RE_INITIALIZE
- OPC_INB_SATA_ABORT
- OPC_INB_SATA_DIF_ENC_IO
- OPC_INB_SATA_HOST_OPSTART
- OPC_INB_SET_CONTROLLER_CONFIG
- OPC_INB_SET_DEVICE_STATE
- OPC_INB_SET_DEV_INFO
- OPC_INB_SET_NVMD_DATA
- OPC_INB_SET_PHY_PROFILE
- OPC_INB_SGPIO_REGISTER
- OPC_INB_SMP_ABORT
- OPC_INB_SMP_REQUEST
- OPC_INB_SMP_RESPONSE
- OPC_INB_SSPINIEDCIOSTART
- OPC_INB_SSPINIEXTEDCIOSTART
- OPC_INB_SSPINIEXTIOSTART
- OPC_INB_SSPINIIOSTART
- OPC_INB_SSPINITMSTART
- OPC_INB_SSPTGTEDCIOSTART
- OPC_INB_SSPTGTIOSTART
- OPC_INB_SSPTGTRSPSTART
- OPC_INB_SSP_ABORT
- OPC_INB_SSP_INI_DIF_ENC_IO
- OPC_INTA
- OPC_INTL
- OPC_INTM
- OPC_INTS
- OPC_JALR
- OPC_JSR
- OPC_LD
- OPC_MISC
- OPC_MOVE
- OPC_OUB_DEK_MANAGEMENT_RESP
- OPC_OUB_DEREG_DEV
- OPC_OUB_DEVICE_HANDLE_REMOVAL
- OPC_OUB_DEV_HANDLE_ARRIV
- OPC_OUB_DEV_INFO
- OPC_OUB_DEV_REGIST
- OPC_OUB_ECHO
- OPC_OUB_FLASH_OP_EXT
- OPC_OUB_FW_FLASH_UPDATE
- OPC_OUB_GENERAL_EVENT
- OPC_OUB_GET_CONTROLLER_CONFIG
- OPC_OUB_GET_DEVICE_INFO
- OPC_OUB_GET_DEVICE_STATE
- OPC_OUB_GET_DEV_HANDLE
- OPC_OUB_GET_NVMD_DATA
- OPC_OUB_GET_PHY_PROFILE
- OPC_OUB_GET_TIME_STAMP
- OPC_OUB_GPIO_EVENT
- OPC_OUB_GPIO_RESPONSE
- OPC_OUB_HW_EVENT
- OPC_OUB_KEK_MANAGEMENT_RESP
- OPC_OUB_LOCAL_PHY_CNTRL
- OPC_OUB_PCIE_DIAG_EXECUTE
- OPC_OUB_PHY_START_RESP
- OPC_OUB_PHY_STOP_RESP
- OPC_OUB_PORT_CONTROL
- OPC_OUB_RSVD
- OPC_OUB_RSVD1
- OPC_OUB_RSVD2
- OPC_OUB_RSVD3
- OPC_OUB_RSVD4
- OPC_OUB_RSVD5
- OPC_OUB_SAS_DIAG_EXECUTE
- OPC_OUB_SAS_DIAG_MODE_START_END
- OPC_OUB_SAS_HW_EVENT_ACK
- OPC_OUB_SAS_RE_INITIALIZE
- OPC_OUB_SATA_ABORT_RSP
- OPC_OUB_SATA_COMP
- OPC_OUB_SATA_EVENT
- OPC_OUB_SET_CONTROLLER_CONFIG
- OPC_OUB_SET_DEVICE_STATE
- OPC_OUB_SET_DEV_INFO
- OPC_OUB_SET_NVMD_DATA
- OPC_OUB_SET_PHY_PROFILE
- OPC_OUB_SGPIO_RESP
- OPC_OUB_SKIP_ENTRY
- OPC_OUB_SMP_ABORT_RSP
- OPC_OUB_SMP_COMP
- OPC_OUB_SMP_RECV_EVENT
- OPC_OUB_SSP_ABORT_RSP
- OPC_OUB_SSP_COALESCED_COMP_RESP
- OPC_OUB_SSP_COMP
- OPC_OUB_SSP_EVENT
- OPC_OUB_SSP_RECV_EVENT
- OPC_OUB_THERM_HW_EVENT
- OPC_PAL
- OPC_TCHMOVE
- OPDESC
- OPE
- OPEN
- OPENA_WT_CONTI_TIME
- OPENBIOS_MAC_BASE
- OPENBIOS_MAC_OFFSET
- OPENBRACE_COMMENT
- OPENBSD_MAXPARTITIONS
- OPENBSD_PARTITION
- OPENED
- OPENFLAGS
- OPENOWNER_POOL_SIZE
- OPENPIC_CPU_REG_SIZE
- OPENPIC_CPU_REG_START
- OPENPIC_FLAG_IDR_CRIT
- OPENPIC_FLAG_ILR
- OPENPIC_GLB_REG_SIZE
- OPENPIC_GLB_REG_START
- OPENPIC_MSI_REG_SIZE
- OPENPIC_MSI_REG_START
- OPENPIC_REG_SIZE
- OPENPIC_SRC_REG_SIZE
- OPENPIC_SRC_REG_START
- OPENPIC_SUMMARY_REG_SIZE
- OPENPIC_SUMMARY_REG_START
- OPENPIC_TMR_REG_SIZE
- OPENPIC_TMR_REG_START
- OPENPROM_ROOT_INO
- OPENPROM_SUPER_MAGIC
- OPENX_REQ
- OPENX_RSP
- OPEN_ACK
- OPEN_AUTH
- OPEN_AUTH_REQUEST
- OPEN_AUTH_RESPONSE
- OPEN_CHANNEL
- OPEN_CLOCK
- OPEN_CON_1
- OPEN_CON_2
- OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK
- OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT
- OPEN_DRAIN_SELECT__RESERVED_MASK
- OPEN_DRAIN_SELECT__RESERVED__SHIFT
- OPEN_FIXED_SECTION
- OPEN_FLAGS
- OPEN_FMODE
- OPEN_FREE_SPACE_QUERY
- OPEN_INGRESS_SVC
- OPEN_INT
- OPEN_NO_RECALL
- OPEN_PSX_REQ
- OPEN_PSX_RSP
- OPEN_REPARSE_POINT
- OPEN_REQ
- OPEN_REQUIRED
- OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET
- OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR
- OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET
- OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR
- OPEN_RETRY_INTERVAL_REG_MASK
- OPEN_RSP
- OPEN_RSP_EXT
- OPEN_SOUND_SYSTEM
- OPEN_STATEID_MUTEX
- OPEN_TEXT_SECTION
- OPEN_TIMEOUT
- OPEN_TO
- OPEN_TREE_CLOEXEC
- OPEN_TREE_CLONE
- OPERAND_AR
- OPERAND_BASE
- OPERAND_CR
- OPERAND_DISP
- OPERAND_FPR
- OPERAND_GPR
- OPERAND_INDEX
- OPERAND_LENGTH
- OPERAND_PCREL
- OPERAND_SIGNED
- OPERAND_VR
- OPERATION
- OPERATION_DONE_SHIFT
- OPERATION_MODE
- OPERA_I2C_TUNER
- OPERA_READ_MSG
- OPERA_TUNER_REQ
- OPERA_WRITE_FX2
- OPERA_WRITE_MSG
- OPERCHAN_ATTR_ID
- OPER_CREATE_NODE
- OPER_WRITE_PROP
- OPFN_CODE
- OPFN_MASK
- OPFN_PARAM_PRN
- OPFORM
- OPIOCGET
- OPIOCGETCHILD
- OPIOCGETNEXT
- OPIOCGETOPTNODE
- OPIOCNEXTPROP
- OPIOCSET
- OPL
- OPL3SA2_DMA_CONFIG
- OPL3SA2_DOUBLE
- OPL3SA2_DOUBLE_TLV
- OPL3SA2_IRQ_CONFIG
- OPL3SA2_IRQ_STATUS
- OPL3SA2_MASTER_LEFT
- OPL3SA2_MASTER_RIGHT
- OPL3SA2_MIC
- OPL3SA2_MISC
- OPL3SA2_PM_ADOWN
- OPL3SA2_PM_CTRL
- OPL3SA2_PM_D0
- OPL3SA2_PM_D3
- OPL3SA2_PM_PDN
- OPL3SA2_PM_PDX
- OPL3SA2_PM_PSV
- OPL3SA2_SINGLE
- OPL3SA2_SINGLE_TLV
- OPL3SA2_SYS_CTRL
- OPL3SA3_ANLG_DOWN
- OPL3SA3_BASS
- OPL3SA3_DGTL_DOWN
- OPL3SA3_TREBLE
- OPL3SA3_WIDE
- OPL3_ATTACK_MASK
- OPL3_BASSDRUM_ON
- OPL3_BLOCKNUM_MASK
- OPL3_COMPOSITE_SINE_WAVE_MODE
- OPL3_CONNECTION_BIT
- OPL3_CYMBAL_ON
- OPL3_DECAY_MASK
- OPL3_ENABLE_WAVE_SELECT
- OPL3_FEEDBACK_MASK
- OPL3_FNUM_HIGH_MASK
- OPL3_HIHAT_ON
- OPL3_HW_AUTO
- OPL3_HW_MASK
- OPL3_HW_OPL2
- OPL3_HW_OPL3
- OPL3_HW_OPL3_CS
- OPL3_HW_OPL3_CS4281
- OPL3_HW_OPL3_FM801
- OPL3_HW_OPL3_SV
- OPL3_HW_OPL4
- OPL3_HW_OPL4_ML
- OPL3_HW_RIPTIDE
- OPL3_IRQ
- OPL3_IRQ_RESET
- OPL3_KEYBOARD_SPLIT
- OPL3_KEYON_BIT
- OPL3_KSL_MASK
- OPL3_KSR
- OPL3_LEFT
- OPL3_LEFT_4OP_0
- OPL3_LEFT_4OP_1
- OPL3_LEFT_4OP_2
- OPL3_MULTIPLE_MASK
- OPL3_OPL3_ENABLE
- OPL3_OPL4_ENABLE
- OPL3_PATCH
- OPL3_PATCH_HASH_SIZE
- OPL3_PERCUSSION_ENABLE
- OPL3_REG_AM_VIB
- OPL3_REG_ATTACK_DECAY
- OPL3_REG_CONNECTION_SELECT
- OPL3_REG_FEEDBACK_CONNECTION
- OPL3_REG_FNUM_LOW
- OPL3_REG_KBD_SPLIT
- OPL3_REG_KEYON_BLOCK
- OPL3_REG_KSL_LEVEL
- OPL3_REG_MODE
- OPL3_REG_PERCUSSION
- OPL3_REG_SUSTAIN_RELEASE
- OPL3_REG_TEST
- OPL3_REG_TIMER1
- OPL3_REG_TIMER2
- OPL3_REG_TIMER_CONTROL
- OPL3_REG_WAVE_SELECT
- OPL3_RELEASE_MASK
- OPL3_RIGHT
- OPL3_RIGHT_4OP_0
- OPL3_RIGHT_4OP_1
- OPL3_RIGHT_4OP_2
- OPL3_SAMPLE
- OPL3_SNAREDRUM_ON
- OPL3_STEREO_BITS
- OPL3_SUPPORT_SYNTH
- OPL3_SUSTAIN_MASK
- OPL3_SUSTAIN_ON
- OPL3_TIMER1_MASK
- OPL3_TIMER1_START
- OPL3_TIMER2_MASK
- OPL3_TIMER2_START
- OPL3_TOMTOM_ON
- OPL3_TOTAL_LEVEL_MASK
- OPL3_TREMOLO_DEPTH
- OPL3_TREMOLO_ON
- OPL3_VIBRATO_DEPTH
- OPL3_VIBRATO_ON
- OPL3_VOICE_TO_LEFT
- OPL3_VOICE_TO_RIGHT
- OPL3_WAVE_SELECT_MASK
- OPL4_ATC_BIT
- OPL4_ATTACK_RATE_MASK
- OPL4_BLOCK_MASK
- OPL4_CHORUS_SEND_MASK
- OPL4_DAMP_BIT
- OPL4_DECAY1_RATE_MASK
- OPL4_DECAY2_RATE_MASK
- OPL4_DECAY_LEVEL_MASK
- OPL4_DEVICE_ID_MASK
- OPL4_F_NUMBER_HIGH_MASK
- OPL4_F_NUMBER_LOW_MASK
- OPL4_KEY_ON_BIT
- OPL4_LEVEL_DIRECT_BIT
- OPL4_LFO_FREQUENCY_MASK
- OPL4_LFO_RESET_BIT
- OPL4_MAX_VOICES
- OPL4_MIX_LEFT_MASK
- OPL4_MIX_RIGHT_MASK
- OPL4_MODE_BIT
- OPL4_MTYPE_BIT
- OPL4_OUTPUT_CHANNEL_BIT
- OPL4_PAN_POT_MASK
- OPL4_PSEUDO_REVERB_BIT
- OPL4_RATE_INTERPOLATION_MASK
- OPL4_REG_ATC
- OPL4_REG_ATTACK_DECAY1
- OPL4_REG_F_NUMBER
- OPL4_REG_LEVEL
- OPL4_REG_LEVEL_DECAY2
- OPL4_REG_LFO_VIBRATO
- OPL4_REG_MEMORY_ADDRESS_HIGH
- OPL4_REG_MEMORY_ADDRESS_LOW
- OPL4_REG_MEMORY_ADDRESS_MID
- OPL4_REG_MEMORY_CONFIGURATION
- OPL4_REG_MEMORY_DATA
- OPL4_REG_MISC
- OPL4_REG_MIX_CONTROL_FM
- OPL4_REG_MIX_CONTROL_PCM
- OPL4_REG_OCTAVE
- OPL4_REG_RELEASE_CORRECTION
- OPL4_REG_TEST0
- OPL4_REG_TEST1
- OPL4_REG_TONE_NUMBER
- OPL4_REG_TREMOLO
- OPL4_RELEASE_RATE_MASK
- OPL4_REVERB_SEND_MASK
- OPL4_STATUS_BUSY
- OPL4_STATUS_LOAD
- OPL4_TONE_HEADER_MASK
- OPL4_TONE_NUMBER_BIT8
- OPL4_TOTAL_LEVEL_MASK
- OPL4_TREMOLO_DEPTH_MASK
- OPL4_VIBRATO_DEPTH_MASK
- OPLOCK_BATCH
- OPLOCK_EXCLUSIVE
- OPLOCK_NONE
- OPLOCK_READ
- OPL_MASK
- OPMASK
- OPMENU0
- OPMENU1
- OPMODE
- OPMODE_AUTO
- OPMODE_AUTODETECT
- OPMODE_AUTOSELECT
- OPMODE_DFU_MODE_WITH_FLASH
- OPMODE_HW_CONFIG_MODE
- OPMODE_MANUAL
- OPMODE_MODE_RECEIVE
- OPMODE_MODE_SLEEP
- OPMODE_MODE_STANDBY
- OPMODE_MODE_SYNTHESIZER
- OPMODE_MODE_TRANSMIT
- OPMODE_NONE
- OPMODE_NORMAL_NIC_WITHOUT_FLASH
- OPMODE_NORMAL_NIC_WITH_FLASH
- OPN_ACPT
- OPN_IGNR
- OPN_RJCT
- OPORTMXACLKSEL0EX
- OPORTMXCTR1
- OPORTMXCTR1_FSSEL_11_025
- OPORTMXCTR1_FSSEL_12
- OPORTMXCTR1_FSSEL_16
- OPORTMXCTR1_FSSEL_176_4
- OPORTMXCTR1_FSSEL_192
- OPORTMXCTR1_FSSEL_22_05
- OPORTMXCTR1_FSSEL_24
- OPORTMXCTR1_FSSEL_32
- OPORTMXCTR1_FSSEL_44_1
- OPORTMXCTR1_FSSEL_48
- OPORTMXCTR1_FSSEL_8
- OPORTMXCTR1_FSSEL_88_2
- OPORTMXCTR1_FSSEL_96
- OPORTMXCTR1_FSSEL_MASK
- OPORTMXCTR1_I2SLRSEL_I2S
- OPORTMXCTR1_I2SLRSEL_LEFT
- OPORTMXCTR1_I2SLRSEL_MASK
- OPORTMXCTR1_I2SLRSEL_RIGHT
- OPORTMXCTR1_OUTBITSEL_16
- OPORTMXCTR1_OUTBITSEL_20
- OPORTMXCTR1_OUTBITSEL_24
- OPORTMXCTR1_OUTBITSEL_32
- OPORTMXCTR1_OUTBITSEL_MASK
- OPORTMXCTR2
- OPORTMXCTR2_ACLKSEL_A1
- OPORTMXCTR2_ACLKSEL_A2
- OPORTMXCTR2_ACLKSEL_A2PLL
- OPORTMXCTR2_ACLKSEL_F1
- OPORTMXCTR2_ACLKSEL_F2
- OPORTMXCTR2_ACLKSEL_MASK
- OPORTMXCTR2_ACLKSEL_RX1
- OPORTMXCTR2_ACLKSEL_RX2
- OPORTMXCTR2_DACCKSEL_1_1
- OPORTMXCTR2_DACCKSEL_1_2
- OPORTMXCTR2_DACCKSEL_1_3
- OPORTMXCTR2_DACCKSEL_2_3
- OPORTMXCTR2_DACCKSEL_MASK
- OPORTMXCTR2_EXTLSIFSSEL_24
- OPORTMXCTR2_EXTLSIFSSEL_36
- OPORTMXCTR2_EXTLSIFSSEL_MASK
- OPORTMXCTR2_MSSEL_MASK
- OPORTMXCTR2_MSSEL_MASTER
- OPORTMXCTR2_MSSEL_SLAVE
- OPORTMXCTR3
- OPORTMXCTR3_IECTHUR_IECIN
- OPORTMXCTR3_IECTHUR_IECOUT
- OPORTMXCTR3_IECTHUR_MASK
- OPORTMXCTR3_PMSEL_MASK
- OPORTMXCTR3_PMSEL_MUTE
- OPORTMXCTR3_PMSEL_PAUSE
- OPORTMXCTR3_PMSW_MASK
- OPORTMXCTR3_PMSW_MUTE_OFF
- OPORTMXCTR3_PMSW_MUTE_ON
- OPORTMXCTR3_SRCSEL_CDDTS
- OPORTMXCTR3_SRCSEL_MASK
- OPORTMXCTR3_SRCSEL_PCM
- OPORTMXCTR3_SRCSEL_STREAM
- OPORTMXCTR3_VALID_MASK
- OPORTMXCTR3_VALID_PCM
- OPORTMXCTR3_VALID_STREAM
- OPORTMXDEBUG
- OPORTMXDSDMUTEDAT
- OPORTMXDSDPORT
- OPORTMXDSDSEL
- OPORTMXDXDFREQMODE
- OPORTMXEXNOE
- OPORTMXMASK
- OPORTMXMASK_DXMSK_MASK
- OPORTMXMASK_DXMSK_OFF
- OPORTMXMASK_DXMSK_ON
- OPORTMXMASK_IUDXMSK_MASK
- OPORTMXMASK_IUDXMSK_OFF
- OPORTMXMASK_IUDXMSK_ON
- OPORTMXMASK_IUXCKMSK_MASK
- OPORTMXMASK_IUXCKMSK_OFF
- OPORTMXMASK_IUXCKMSK_ON
- OPORTMXMASK_XCKMSK_MASK
- OPORTMXMASK_XCKMSK_OFF
- OPORTMXMASK_XCKMSK_ON
- OPORTMXPATH
- OPORTMXPAUDAT
- OPORTMXPAUDAT_PAUSEPC_CMN
- OPORTMXPAUDAT_PAUSEPD_AAC
- OPORTMXPAUDAT_PAUSEPD_AC3
- OPORTMXPAUDAT_PAUSEPD_DTS1
- OPORTMXPAUDAT_PAUSEPD_DTS2
- OPORTMXPAUDAT_PAUSEPD_DTS3
- OPORTMXPAUDAT_PAUSEPD_MP3
- OPORTMXPAUDAT_PAUSEPD_MPA
- OPORTMXRATE_I
- OPORTMXRATE_I_ACLKSEL_AI1ADCCK
- OPORTMXRATE_I_ACLKSEL_AI2ADCCK
- OPORTMXRATE_I_ACLKSEL_AI3ADCCK
- OPORTMXRATE_I_ACLKSEL_APLL
- OPORTMXRATE_I_ACLKSEL_APLLA1
- OPORTMXRATE_I_ACLKSEL_APLLA2
- OPORTMXRATE_I_ACLKSEL_APLLF1
- OPORTMXRATE_I_ACLKSEL_APLLF2
- OPORTMXRATE_I_ACLKSEL_HDMI1
- OPORTMXRATE_I_ACLKSEL_HDMI2
- OPORTMXRATE_I_ACLKSEL_MASK
- OPORTMXRATE_I_ACLKSRC_APLL
- OPORTMXRATE_I_ACLKSRC_HSC
- OPORTMXRATE_I_ACLKSRC_MASK
- OPORTMXRATE_I_ACLKSRC_USB
- OPORTMXRATE_I_EQU_EQUAL
- OPORTMXRATE_I_EQU_MASK
- OPORTMXRATE_I_EQU_NOTEQUAL
- OPORTMXRATE_I_FSSEL_11_025
- OPORTMXRATE_I_FSSEL_12
- OPORTMXRATE_I_FSSEL_16
- OPORTMXRATE_I_FSSEL_176_4
- OPORTMXRATE_I_FSSEL_192
- OPORTMXRATE_I_FSSEL_22_05
- OPORTMXRATE_I_FSSEL_24
- OPORTMXRATE_I_FSSEL_32
- OPORTMXRATE_I_FSSEL_44_1
- OPORTMXRATE_I_FSSEL_48
- OPORTMXRATE_I_FSSEL_8
- OPORTMXRATE_I_FSSEL_88_2
- OPORTMXRATE_I_FSSEL_96
- OPORTMXRATE_I_FSSEL_MASK
- OPORTMXRATE_I_LRCKSTP_MASK
- OPORTMXRATE_I_LRCKSTP_START
- OPORTMXRATE_I_LRCKSTP_STOP
- OPORTMXRATE_I_MCKSEL_33
- OPORTMXRATE_I_MCKSEL_36
- OPORTMXRATE_I_MCKSEL_HSC27
- OPORTMXRATE_I_MCKSEL_MASK
- OPORTMXRATE_I_SRCBPMD_BYPASS
- OPORTMXRATE_I_SRCBPMD_MASK
- OPORTMXRATE_I_SRCBPMD_SRC
- OPORTMXREPET
- OPORTMXREPET_PMLENGTH_AAC
- OPORTMXREPET_PMLENGTH_AC3
- OPORTMXREPET_PMLENGTH_DTS1
- OPORTMXREPET_PMLENGTH_DTS2
- OPORTMXREPET_PMLENGTH_DTS3
- OPORTMXREPET_PMLENGTH_MP3
- OPORTMXREPET_PMLENGTH_MPA
- OPORTMXREPET_STRLENGTH_AAC
- OPORTMXREPET_STRLENGTH_AC3
- OPORTMXREPET_STRLENGTH_DTS1
- OPORTMXREPET_STRLENGTH_DTS2
- OPORTMXREPET_STRLENGTH_DTS3
- OPORTMXREPET_STRLENGTH_MP3
- OPORTMXREPET_STRLENGTH_MPA
- OPORTMXSRC1CTR
- OPORTMXSRC1CTR_FSICK_32
- OPORTMXSRC1CTR_FSICK_44_1
- OPORTMXSRC1CTR_FSICK_48
- OPORTMXSRC1CTR_FSICK_MASK
- OPORTMXSRC1CTR_FSIIPNUM_SHIFT
- OPORTMXSRC1CTR_FSIIPSEL_INNER
- OPORTMXSRC1CTR_FSIIPSEL_MASK
- OPORTMXSRC1CTR_FSIIPSEL_OUTER
- OPORTMXSRC1CTR_FSISEL_ACLK
- OPORTMXSRC1CTR_FSISEL_DD
- OPORTMXSRC1CTR_FSISEL_MASK
- OPORTMXSRC1CTR_FSOCK_32
- OPORTMXSRC1CTR_FSOCK_44_1
- OPORTMXSRC1CTR_FSOCK_48
- OPORTMXSRC1CTR_FSOCK_MASK
- OPORTMXSRC1CTR_LOCK_LOCK
- OPORTMXSRC1CTR_LOCK_MASK
- OPORTMXSRC1CTR_LOCK_UNLOCK
- OPORTMXSRC1CTR_SRCPATH_BYPASS
- OPORTMXSRC1CTR_SRCPATH_CALC
- OPORTMXSRC1CTR_SRCPATH_MASK
- OPORTMXSRC1CTR_SYNC_ASYNC
- OPORTMXSRC1CTR_SYNC_MASK
- OPORTMXSRC1CTR_SYNC_SYNC
- OPORTMXSRC1CTR_THMODE_BYPASS
- OPORTMXSRC1CTR_THMODE_MASK
- OPORTMXSRC1CTR_THMODE_SRC
- OPORTMXSYNC
- OPORTMXT0RSTCTR_RST_MASK
- OPORTMXT0RSTCTR_RST_OFF
- OPORTMXT0RSTCTR_RST_ON
- OPORTMXT0SLOTCTR_MUTEOFF_MASK
- OPORTMXT0SLOTCTR_MUTEOFF_MUTE
- OPORTMXT0SLOTCTR_MUTEOFF_UNMUTE
- OPORTMXTYRSTCTR
- OPORTMXTYSLOTCTR
- OPORTMXTYSLOTCTR_MODE
- OPORTMXTYSLOTCTR_SLOTSEL_MASK
- OPORTMXTYSLOTCTR_SLOTSEL_SLOT0
- OPORTMXTYSLOTCTR_SLOTSEL_SLOT1
- OPORTMXTYSLOTCTR_SLOTSEL_SLOT2
- OPORTMXTYSLOTCTR_SLOTSEL_SLOT3
- OPORTMXTYSLOTCTR_SLOTSEL_SLOT4
- OPORTMXTYVOLGAINSTATUS
- OPORTMXTYVOLGAINSTATUS_CUR_MASK
- OPORTMXTYVOLPARA1
- OPORTMXTYVOLPARA1_SLOPEU_MASK
- OPORTMXTYVOLPARA2
- OPORTMXTYVOLPARA2_FADE_FADEIN
- OPORTMXTYVOLPARA2_FADE_FADEOUT
- OPORTMXTYVOLPARA2_FADE_MASK
- OPORTMXTYVOLPARA2_FADE_NOOP
- OPORTMXTYVOLPARA2_TARGET_MASK
- OPORT_SLOT_MAX
- OPOST
- OPP
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK
- OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT
- OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK
- OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT
- OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK
- OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT
- OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK
- OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK
- OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT
- OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT
- OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT
- OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT
- OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT
- OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT
- OPPDM_EFUSE_CLASS0_OPTIMIZED_VOLTAGE
- OPPDM_HAS_NO_ABB
- OPP_COMMON_MASK_SH_LIST_DCE_100
- OPP_COMMON_MASK_SH_LIST_DCE_110
- OPP_COMMON_MASK_SH_LIST_DCE_112
- OPP_COMMON_MASK_SH_LIST_DCE_120
- OPP_COMMON_MASK_SH_LIST_DCE_80
- OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE
- OPP_COMMON_REG_LIST_BASE
- OPP_COMMON_REG_VARIABLE_LIST
- OPP_DCE_100_REG_LIST
- OPP_DCE_110_REG_LIST
- OPP_DCE_112_REG_LIST
- OPP_DCE_120_REG_LIST
- OPP_DCE_80_REG_LIST
- OPP_DCN10_REG_FIELD_LIST
- OPP_DCN20_REG_FIELD_LIST
- OPP_DPG_MASK_SH_LIST
- OPP_DPG_REG_LIST
- OPP_EVENT_ADD
- OPP_EVENT_DISABLE
- OPP_EVENT_ENABLE
- OPP_EVENT_REMOVE
- OPP_ID_INVALID
- OPP_INITIALIZER
- OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
- OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
- OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
- OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
- OPP_MASK_SH_LIST_DCN
- OPP_MASK_SH_LIST_DCN10
- OPP_MASK_SH_LIST_DCN20
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK
- OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT
- OPP_PIPE_CLOCK_DISABLE
- OPP_PIPE_CLOCK_ENABLE
- OPP_PIPE_CLOCK_ENABLE_CONTROL
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK
- OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT
- OPP_PIPE_CRC_CONT_EN
- OPP_PIPE_CRC_DISABLE
- OPP_PIPE_CRC_EN
- OPP_PIPE_CRC_ENABLE
- OPP_PIPE_CRC_INTERLACE_EN
- OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED
- OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE
- OPP_PIPE_CRC_INTERLACE_MODE
- OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD
- OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD
- OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM
- OPP_PIPE_CRC_INTERLACE_MODE_TOP
- OPP_PIPE_CRC_MODE_CONTINUOUS
- OPP_PIPE_CRC_MODE_ONE_SHOT
- OPP_PIPE_CRC_ONE_SHOT_PENDING
- OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING
- OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING
- OPP_PIPE_CRC_PIXEL_SELECT
- OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS
- OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS
- OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS
- OPP_PIPE_CRC_PIXEL_SELECT_RESERVED
- OPP_PIPE_CRC_SOURCE_SELECT
- OPP_PIPE_CRC_SOURCE_SELECT_FMT
- OPP_PIPE_CRC_SOURCE_SELECT_SFT
- OPP_PIPE_CRC_STEREO_EN
- OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO
- OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO
- OPP_PIPE_CRC_STEREO_MODE
- OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE
- OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE
- OPP_PIPE_CRC_STEREO_MODE_LEFT
- OPP_PIPE_CRC_STEREO_MODE_RIGHT
- OPP_PIPE_DIGTIAL_BYPASS_CONTROL
- OPP_PIPE_DIGTIAL_BYPASS_DISABLE
- OPP_PIPE_DIGTIAL_BYPASS_ENABLE
- OPP_REGAMMA_BYPASS
- OPP_REGAMMA_SRGB
- OPP_REGAMMA_USER
- OPP_REGAMMA_XVYCC
- OPP_REG_FIELD_LIST
- OPP_REG_LIST_DCN
- OPP_REG_LIST_DCN10
- OPP_REG_LIST_DCN20
- OPP_REG_VARIABLE_LIST_DCN2_0
- OPP_SF
- OPP_TABLE_ACCESS_EXCLUSIVE
- OPP_TABLE_ACCESS_SHARED
- OPP_TABLE_ACCESS_UNKNOWN
- OPP_TEST_CLK_SEL_CONTROL
- OPP_TEST_CLK_SEL_DISPCLK_ABM0
- OPP_TEST_CLK_SEL_DISPCLK_OPP0
- OPP_TEST_CLK_SEL_DISPCLK_OPP1
- OPP_TEST_CLK_SEL_DISPCLK_OPP2
- OPP_TEST_CLK_SEL_DISPCLK_OPP3
- OPP_TEST_CLK_SEL_DISPCLK_OPP4
- OPP_TEST_CLK_SEL_DISPCLK_OPP5
- OPP_TEST_CLK_SEL_DISPCLK_P
- OPP_TEST_CLK_SEL_DISPCLK_R
- OPP_TEST_CLK_SEL_RESERVED0
- OPP_TOLERANCE
- OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK
- OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT
- OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK
- OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT
- OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK
- OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT
- OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK
- OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT
- OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK
- OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT
- OPP_TOP_CLOCK_DISABLED_STATUS
- OPP_TOP_CLOCK_ENABLED_STATUS
- OPP_TOP_CLOCK_ENABLE_STATUS
- OPP_TOP_CLOCK_GATING_CONTROL
- OPP_TOP_CLOCK_GATING_DISABLED
- OPP_TOP_CLOCK_GATING_ENABLED
- OPREGION_ACPI_OFFSET
- OPREGION_ASLE_EXT_OFFSET
- OPREGION_ASLE_OFFSET
- OPREGION_HEADER_OFFSET
- OPREGION_PCI_ADDR
- OPREGION_SCIC_EXIT_MASK
- OPREGION_SCIC_FUNC_MASK
- OPREGION_SCIC_FUNC_SHIFT
- OPREGION_SCIC_SUBFUNC_MASK
- OPREGION_SCIC_SUBFUNC_SHIFT
- OPREGION_SIGNATURE
- OPREGION_SIZE
- OPREGION_SWSCI_OFFSET
- OPREGION_VBT_OFFSET
- OPRINTK
- OPRND_SHIFT
- OPROFILEFS_MAGIC
- OPROFILE_BUFFER_SYNC_H
- OPROFILE_CPU_BUFFER_H
- OPROFILE_FMT_UUID
- OPROFILE_H
- OPROFILE_MAX_PMC_NUM
- OPROFILE_PMSEL_FIELD_WIDTH
- OPROFILE_PM_PMCSEL_MSK
- OPROFILE_PM_UNIT_MSK
- OPROFILE_PM_UNIT_SHIFT
- OPROFILE_STATS_H
- OPROFILE_UNIT_FIELD_WIDTH
- OPROF_H
- OPROMCHILD
- OPROMCONS_NOT_WSCONS
- OPROMCONS_OPENPROM
- OPROMCONS_STDIN_IS_KBD
- OPROMCONS_STDOUT_IS_FB
- OPROMGETBOOTARGS
- OPROMGETCONS
- OPROMGETFBNAME
- OPROMGETOPT
- OPROMGETPROP
- OPROMMAXPARAM
- OPROMNEXT
- OPROMNXTOPT
- OPROMNXTPROP
- OPROMPATH2NODE
- OPROMPCI2NODE
- OPROMSETCUR
- OPROMSETOPT
- OPROMSETOPT2
- OPROMU2P
- OPRT_CHG
- OPR_MGMT_MPI_ENC_ERR_KEK_UNWRAP_FAIL
- OPR_MGMT_MPI_ENC_ERR_NVRAM_OPERATION_FAILURE
- OPR_MGMT_MPI_ENC_ERR_OPR_ID_NOT_FOUND
- OPR_MGMT_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED
- OPR_MGMT_MPI_ENC_ERR_OPR_PARAM_ILLEGAL
- OPR_MGMT_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH
- OPR_MGMT_OP_NOT_SUPPORTED
- OPS
- OPSIZ
- OPSTS_CONTROL
- OPSTS_DSRS
- OPSTS_DTR
- OPSTS_LL
- OPSTS_RTS
- OPSTS_SS
- OPS_MAX
- OPT
- OPT1_L1_INT_STATUS_MASK_POL
- OPT1_PCIE_BRIDGE_HOLE_DET_EN
- OPT1_RD_BE_OPT_EN
- OPT1_RD_REPLY_BE_FIX_EN
- OPT2_CFG_TYPE1_BD_SEL
- OPT2_CFG_TYPE1_BUS_NO_MASK
- OPT2_CFG_TYPE1_BUS_NO_SHIFT
- OPT2_TX_CREDIT_CHK_EN
- OPT2_UBUS_UR_DECODE_DIS
- OPT3001_CONFIGURATION
- OPT3001_CONFIGURATION_CRF
- OPT3001_CONFIGURATION_CT
- OPT3001_CONFIGURATION_FC_MASK
- OPT3001_CONFIGURATION_FH
- OPT3001_CONFIGURATION_FL
- OPT3001_CONFIGURATION_L
- OPT3001_CONFIGURATION_ME
- OPT3001_CONFIGURATION_M_CONTINUOUS
- OPT3001_CONFIGURATION_M_MASK
- OPT3001_CONFIGURATION_M_SHUTDOWN
- OPT3001_CONFIGURATION_M_SINGLE
- OPT3001_CONFIGURATION_OVF
- OPT3001_CONFIGURATION_POL
- OPT3001_CONFIGURATION_RN_AUTO
- OPT3001_CONFIGURATION_RN_MASK
- OPT3001_DEVICE_ID
- OPT3001_HIGH_LIMIT
- OPT3001_INT_TIME_LONG
- OPT3001_INT_TIME_SHORT
- OPT3001_LOW_LIMIT
- OPT3001_LOW_LIMIT_EOC_ENABLE
- OPT3001_MANUFACTURER_ID
- OPT3001_REG_EXPONENT
- OPT3001_REG_MANTISSA
- OPT3001_RESULT
- OPT3001_RESULT_READY_LONG
- OPT3001_RESULT_READY_SHORT
- OPTABLE
- OPTABLES
- OPTARG_BALANCE_PERFORMANCE
- OPTARG_BALANCE_POWER
- OPTARG_NORMAL
- OPTARG_PERFORMANCE
- OPTARG_POWER
- OPTB
- OPTC
- OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK
- OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT
- OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK
- OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT
- OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK
- OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT
- OPTC_DSC_DISABLED
- OPTC_DSC_ENABLED_444
- OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED
- OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT
- OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK
- OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT
- OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK
- OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT
- OPTD
- OPTE
- OPTEE_MAX_ARG_SIZE
- OPTEE_MSG_ATTR_CACHE_MASK
- OPTEE_MSG_ATTR_CACHE_PREDEFINED
- OPTEE_MSG_ATTR_CACHE_SHIFT
- OPTEE_MSG_ATTR_META
- OPTEE_MSG_ATTR_NONCONTIG
- OPTEE_MSG_ATTR_TYPE_MASK
- OPTEE_MSG_ATTR_TYPE_NONE
- OPTEE_MSG_ATTR_TYPE_RMEM_INOUT
- OPTEE_MSG_ATTR_TYPE_RMEM_INPUT
- OPTEE_MSG_ATTR_TYPE_RMEM_OUTPUT
- OPTEE_MSG_ATTR_TYPE_TMEM_INOUT
- OPTEE_MSG_ATTR_TYPE_TMEM_INPUT
- OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT
- OPTEE_MSG_ATTR_TYPE_VALUE_INOUT
- OPTEE_MSG_ATTR_TYPE_VALUE_INPUT
- OPTEE_MSG_ATTR_TYPE_VALUE_OUTPUT
- OPTEE_MSG_CMD_CANCEL
- OPTEE_MSG_CMD_CLOSE_SESSION
- OPTEE_MSG_CMD_INVOKE_COMMAND
- OPTEE_MSG_CMD_OPEN_SESSION
- OPTEE_MSG_CMD_REGISTER_SHM
- OPTEE_MSG_CMD_UNREGISTER_SHM
- OPTEE_MSG_FUNCID_CALLS_REVISION
- OPTEE_MSG_FUNCID_CALLS_UID
- OPTEE_MSG_FUNCID_CALL_WITH_ARG
- OPTEE_MSG_FUNCID_GET_OS_REVISION
- OPTEE_MSG_FUNCID_GET_OS_UUID
- OPTEE_MSG_GET_ARG_SIZE
- OPTEE_MSG_LOGIN_APPLICATION
- OPTEE_MSG_LOGIN_APPLICATION_GROUP
- OPTEE_MSG_LOGIN_APPLICATION_USER
- OPTEE_MSG_LOGIN_GROUP
- OPTEE_MSG_LOGIN_PUBLIC
- OPTEE_MSG_LOGIN_USER
- OPTEE_MSG_NONCONTIG_PAGE_SIZE
- OPTEE_MSG_OS_OPTEE_UUID_0
- OPTEE_MSG_OS_OPTEE_UUID_1
- OPTEE_MSG_OS_OPTEE_UUID_2
- OPTEE_MSG_OS_OPTEE_UUID_3
- OPTEE_MSG_REVISION_MAJOR
- OPTEE_MSG_REVISION_MINOR
- OPTEE_MSG_RPC_CMD_FS
- OPTEE_MSG_RPC_CMD_GET_TIME
- OPTEE_MSG_RPC_CMD_LOAD_TA
- OPTEE_MSG_RPC_CMD_RPMB
- OPTEE_MSG_RPC_CMD_SHM_ALLOC
- OPTEE_MSG_RPC_CMD_SHM_FREE
- OPTEE_MSG_RPC_CMD_SUSPEND
- OPTEE_MSG_RPC_CMD_WAIT_QUEUE
- OPTEE_MSG_RPC_SHM_TYPE_APPL
- OPTEE_MSG_RPC_SHM_TYPE_KERNEL
- OPTEE_MSG_RPC_WAIT_QUEUE_SLEEP
- OPTEE_MSG_RPC_WAIT_QUEUE_WAKEUP
- OPTEE_MSG_UID_0
- OPTEE_MSG_UID_1
- OPTEE_MSG_UID_2
- OPTEE_MSG_UID_3
- OPTEE_PRIVATE_H
- OPTEE_SHM_NUM_PRIV_PAGES
- OPTEE_SMC_CALLS_COUNT
- OPTEE_SMC_CALLS_REVISION
- OPTEE_SMC_CALLS_UID
- OPTEE_SMC_CALL_GET_OS_REVISION
- OPTEE_SMC_CALL_GET_OS_UUID
- OPTEE_SMC_CALL_RETURN_FROM_RPC
- OPTEE_SMC_CALL_WITH_ARG
- OPTEE_SMC_DISABLE_SHM_CACHE
- OPTEE_SMC_ENABLE_SHM_CACHE
- OPTEE_SMC_EXCHANGE_CAPABILITIES
- OPTEE_SMC_FAST_CALL_VAL
- OPTEE_SMC_FUNCID_CALLS_COUNT
- OPTEE_SMC_FUNCID_CALLS_REVISION
- OPTEE_SMC_FUNCID_CALLS_UID
- OPTEE_SMC_FUNCID_CALL_WITH_ARG
- OPTEE_SMC_FUNCID_DISABLE_SHM_CACHE
- OPTEE_SMC_FUNCID_ENABLE_SHM_CACHE
- OPTEE_SMC_FUNCID_EXCHANGE_CAPABILITIES
- OPTEE_SMC_FUNCID_GET_OS_REVISION
- OPTEE_SMC_FUNCID_GET_OS_UUID
- OPTEE_SMC_FUNCID_GET_SHM_CONFIG
- OPTEE_SMC_FUNCID_RETURN_FROM_RPC
- OPTEE_SMC_GET_SHM_CONFIG
- OPTEE_SMC_H
- OPTEE_SMC_NSEC_CAP_UNIPROCESSOR
- OPTEE_SMC_RETURN_EBADADDR
- OPTEE_SMC_RETURN_EBADCMD
- OPTEE_SMC_RETURN_EBUSY
- OPTEE_SMC_RETURN_ENOMEM
- OPTEE_SMC_RETURN_ENOTAVAIL
- OPTEE_SMC_RETURN_ERESUME
- OPTEE_SMC_RETURN_ETHREAD_LIMIT
- OPTEE_SMC_RETURN_GET_RPC_FUNC
- OPTEE_SMC_RETURN_IS_RPC
- OPTEE_SMC_RETURN_OK
- OPTEE_SMC_RETURN_RPC_ALLOC
- OPTEE_SMC_RETURN_RPC_CMD
- OPTEE_SMC_RETURN_RPC_FOREIGN_INTR
- OPTEE_SMC_RETURN_RPC_FREE
- OPTEE_SMC_RETURN_RPC_FUNC_MASK
- OPTEE_SMC_RETURN_RPC_PREFIX
- OPTEE_SMC_RETURN_RPC_PREFIX_MASK
- OPTEE_SMC_RETURN_UNKNOWN_FUNCTION
- OPTEE_SMC_RPC_FUNC_ALLOC
- OPTEE_SMC_RPC_FUNC_CMD
- OPTEE_SMC_RPC_FUNC_FOREIGN_INTR
- OPTEE_SMC_RPC_FUNC_FREE
- OPTEE_SMC_RPC_VAL
- OPTEE_SMC_SEC_CAP_DYNAMIC_SHM
- OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM
- OPTEE_SMC_SEC_CAP_UNREGISTERED_SHM
- OPTEE_SMC_SHM_CACHED
- OPTEE_SMC_STD_CALL_VAL
- OPTF
- OPTI46X
- OPTI611A
- OPTICS_CDROM_MAJOR
- OPTIMAL_ML
- OPTIMIZER_HIDE_VAR
- OPTIMIZE_DELAY
- OPTIMUM_SX_OFF
- OPTIMUM_SX_PER
- OPTIMUS_AUDIO_CAPS_MASK
- OPTIMUS_CAPS_MASK
- OPTIMUS_DISPLAY_HOTPLUG
- OPTIMUS_DYNAMIC_PWR_CAP
- OPTIMUS_ENABLED
- OPTIMUS_HDA_CODEC_MASK
- OPTIMUS_STATUS_MASK
- OPTIMUS_STATUS_OFF
- OPTIMUS_STATUS_ON_ENABLED
- OPTIMUS_STATUS_PWR_STABLE
- OPTIONAL_GET
- OPTIONAL_HANDLER
- OPTIONAL_TLV_TYPE_START
- OPTIONS
- OPTION_ARGUMENT
- OPTION_BIT
- OPTION_BOOLEAN
- OPTION_CALLBACK
- OPTION_DEFAULT
- OPTION_DISABLED
- OPTION_DYN_IPG_ENABLE
- OPTION_ENABLED
- OPTION_END
- OPTION_FAST_OPEN_COOKIE
- OPTION_GROUP
- OPTION_INCR
- OPTION_INTEGER
- OPTION_INTR_COAL_ENABLE
- OPTION_JUMBO_ENABLE
- OPTION_L1_HOLD
- OPTION_L2_CLEANUP
- OPTION_L2_FIXEDTEI
- OPTION_L2_PMX
- OPTION_L2_PTP
- OPTION_LONG
- OPTION_MD5
- OPTION_MULTICAST_ENABLE
- OPTION_NUMBER_END
- OPTION_NUMBER_MSS
- OPTION_NUMBER_NONE
- OPTION_NUMBER_SACK
- OPTION_NUMBER_SACK_PERM
- OPTION_NUMBER_WINDOW_SCALE
- OPTION_NUMBER_WRITE0
- OPTION_OFF
- OPTION_ON
- OPTION_PRODUCT_COBRA
- OPTION_PRODUCT_COBRA_BUS
- OPTION_PRODUCT_COLT
- OPTION_PRODUCT_ETNA_KOI_MODEM
- OPTION_PRODUCT_ETNA_MODEM
- OPTION_PRODUCT_ETNA_MODEM_EX
- OPTION_PRODUCT_ETNA_MODEM_GT
- OPTION_PRODUCT_ETNA_MODEM_LITE
- OPTION_PRODUCT_FUJI_MODEM_EX
- OPTION_PRODUCT_FUJI_MODEM_GT
- OPTION_PRODUCT_FUJI_MODEM_LIGHT
- OPTION_PRODUCT_GTM380_MODEM
- OPTION_PRODUCT_GT_MAX_READY
- OPTION_PRODUCT_KOI_MODEM
- OPTION_PRODUCT_RICOLA
- OPTION_PRODUCT_RICOLA_LIGHT
- OPTION_PRODUCT_RICOLA_NDIS
- OPTION_PRODUCT_RICOLA_NDIS_LIGHT
- OPTION_PRODUCT_RICOLA_NDIS_QUAD
- OPTION_PRODUCT_RICOLA_NDIS_QUAD_LIGHT
- OPTION_PRODUCT_RICOLA_QUAD
- OPTION_PRODUCT_RICOLA_QUAD_LIGHT
- OPTION_PRODUCT_SCORPION_MODEM
- OPTION_PRODUCT_VIPER
- OPTION_PRODUCT_VIPER_BUS
- OPTION_ROM_CONFIG
- OPTION_ROM_EXEC
- OPTION_ROM_MICROCODE
- OPTION_SACK_ADVERTISE
- OPTION_SET_PTR
- OPTION_SET_UINT
- OPTION_SMC
- OPTION_STRING
- OPTION_TS
- OPTION_U64
- OPTION_UINTEGER
- OPTION_ULONG
- OPTION_UNSET
- OPTION_VENDOR_ID
- OPTION_VLAN_ENABLE
- OPTION_WAKE_MAGIC_ENABLE
- OPTION_WAKE_PHY_ENABLE
- OPTION_WOL_ENABLE
- OPTION_WSCALE
- OPTO
- OPTO_MASK
- OPTROM_BURST_DWORDS
- OPTROM_BURST_SIZE
- OPTROM_SIZE_2300
- OPTROM_SIZE_2322
- OPTROM_SIZE_24XX
- OPTROM_SIZE_25XX
- OPTROM_SIZE_28XX
- OPTROM_SIZE_81XX
- OPTROM_SIZE_82XX
- OPTROM_SIZE_83XX
- OPTSTRING
- OPTS_EVSWITCH
- OPTYPE_BIOS
- OPTYPE_FCOE_BIOS
- OPTYPE_FCOE_FW_ACTIVE
- OPTYPE_FCOE_FW_BACKUP
- OPTYPE_FLASHISM_JUMPVECTOR
- OPTYPE_ISCSI_ACTIVE
- OPTYPE_ISCSI_BACKUP
- OPTYPE_MASK
- OPTYPE_NCSI_FW
- OPTYPE_OFFSET_SPECIFIED
- OPTYPE_PHY_FW
- OPTYPE_PXE_BIOS
- OPTYPE_READ_NO_ADDR
- OPTYPE_READ_WITH_ADDR
- OPTYPE_REDBOOT
- OPTYPE_REDBOOT_CONFIG
- OPTYPE_REDBOOT_DIR
- OPTYPE_SH_PHY_FW
- OPTYPE_UFI_DIR
- OPTYPE_WRITE_NO_ADDR
- OPTYPE_WRITE_WITH_ADDR
- OPT_14_CSR
- OPT_14_CSR_BIT0
- OPT_ALL
- OPT_ALLOW_OTHER
- OPT_ANY
- OPT_ARGUMENT
- OPT_AUTO_SENDTGTS_DISABLE
- OPT_BIT
- OPT_BLKSIZE
- OPT_BOOLEAN
- OPT_BOOLEAN_FLAG
- OPT_BOOLEAN_SET
- OPT_BURST_MAX
- OPT_BUS_CHECK
- OPT_BW
- OPT_BW_NOTHP
- OPT_BW_RAM
- OPT_BW_RAM_NOTHP
- OPT_CALLBACK
- OPT_CALLBACK_DEFAULT
- OPT_CALLBACK_DEFAULT_NOOPT
- OPT_CALLBACK_NOOPT
- OPT_CALLBACK_OPTARG
- OPT_COMB_ADD
- OPT_COMB_BLEND_DISABLED
- OPT_COMB_MAX
- OPT_COMB_MIN
- OPT_COMB_NONE
- OPT_COMB_REVSUBTRACT
- OPT_COMB_SAFE_ADD
- OPT_COMB_SUBTRACT
- OPT_CONV
- OPT_CONV_NOTHP
- OPT_DATE
- OPT_DEBUG
- OPT_DEFAULT_PERMISSIONS
- OPT_DEFAULT_SYNC
- OPT_DIFF_SUPPORT
- OPT_DISCONNECTION
- OPT_DISC_SESSION
- OPT_DPRINT
- OPT_END
- OPT_ENTRY_STATE
- OPT_EQUAL
- OPT_ERR
- OPT_EXCLUDE
- OPT_FD
- OPT_FIRMWARE_RESET
- OPT_FORCE_SYNC_NEGO
- OPT_FRAME_SIZE
- OPT_GET_SPR
- OPT_GROUP
- OPT_GROUP_ID
- OPT_HDR
- OPT_HOST_ID
- OPT_IARB
- OPT_INCR
- OPT_INDEX_OFF
- OPT_INDEX_ON
- OPT_INTEGER
- OPT_INTVAL
- OPT_IPV6_DEVICE
- OPT_IRQM
- OPT_IS_FW_ASSIGNED_IPV6
- OPT_LARGEPAGE
- OPT_LED_PIN
- OPT_LONG
- OPT_LOWERDIR
- OPT_MASTER_PARITY
- OPT_MAX_READ
- OPT_MAX_WIDE
- OPT_MEDIUM_ERR_ADDR
- OPT_MEDIUM_ERR_NUM
- OPT_METACOPY_OFF
- OPT_METACOPY_ON
- OPT_MODE
- OPT_MPU_16BIT
- OPT_MSGTYPE
- OPT_NFS_EXPORT_OFF
- OPT_NFS_EXPORT_ON
- OPT_NORMAL
- OPT_OPTIMIZE
- OPT_PAGE2048
- OPT_PAGE4096
- OPT_PAGE512
- OPT_PAGE512_8BIT
- OPT_PARENT
- OPT_PCI_FIX_UP
- OPT_PMF
- OPT_PROMPT
- OPT_RECOVERY
- OPT_REDIRECT_DIR
- OPT_REVERSE_PROBE
- OPT_ROOTMODE
- OPT_RXBA_ENTRIES_PER_SUBCRQ
- OPT_RX_BUFADD_Q_PER_RX_COMP_Q
- OPT_RX_COMP_QUEUES
- OPT_SAFE_SETUP
- OPT_SAVE_REG_TO_PACA
- OPT_SCSI_PARITY
- OPT_SETTLE_DELAY
- OPT_SET_PTR
- OPT_SET_SPR
- OPT_SET_UINT
- OPT_SHORT
- OPT_SLOT_SIZE
- OPT_SMALLPAGE
- OPT_SOURCE
- OPT_SPECIAL_FEATURES
- OPT_SRF
- OPT_STATS
- OPT_STRING
- OPT_STRING_NOEMPTY
- OPT_STRING_OPTARG
- OPT_STRING_OPTARG_SET
- OPT_STRVAL
- OPT_SUBTYPE
- OPT_SWAP_PORT
- OPT_SYSTEM_RESET
- OPT_TAGS
- OPT_TX_COMP_SUB_QUEUES
- OPT_TX_ENTRIES_PER_SUBCRQ
- OPT_U64
- OPT_UINTEGER
- OPT_ULONG
- OPT_UNSET
- OPT_UNUSED_1
- OPT_UPPERDIR
- OPT_USER_ID
- OPT_USE_NVRAM
- OPT_VERBOSE
- OPT_WORKDIR
- OPT_XINO_AUTO
- OPT_XINO_OFF
- OPT_XINO_ON
- OPT_ZONE_DMA
- OPT_ZONE_DMA32
- OPT_ZONE_HIGHMEM
- OPT__ABBREV
- OPT__DRY_RUN
- OPT__QUIET
- OPT__VERBOSE
- OPT__VERBOSITY
- OPTi931_AUX_LEFT_INPUT
- OPTi931_AUX_RIGHT_INPUT
- OPTi93X
- OPTi93X_IRQ_CAPTURE
- OPTi93X_IRQ_PLAYBACK
- OPTi93X_MIC_LEFT_INPUT
- OPTi93X_MIC_RIGHT_INPUT
- OPTi93X_OUT_LEFT
- OPTi93X_OUT_RIGHT
- OPTi93X_PORT
- OPTi93X_STATUS
- OPTi9XX_HW_82C924
- OPTi9XX_HW_82C925
- OPTi9XX_HW_82C928
- OPTi9XX_HW_82C929
- OPTi9XX_HW_82C930
- OPTi9XX_HW_82C931
- OPTi9XX_HW_82C933
- OPTi9XX_HW_DETECT
- OPTi9XX_HW_LAST
- OPTi9XX_MC_REG
- OPU
- OPVUP
- OPVUPRT
- OPVUPRT_MASK
- OPVUP_MASK
- OPXLFMT_RGB666
- OPXLFMT_RGB888
- OP_19_XOP_RFCI
- OP_19_XOP_RFDI
- OP_19_XOP_RFI
- OP_19_XOP_RFID
- OP_2D
- OP_2_0_0_5
- OP_31
- OP_31_LFDUX
- OP_31_LFDX
- OP_31_LFSUX
- OP_31_LFSX
- OP_31_LWIZX
- OP_31_STFIWX
- OP_31_STFSUX
- OP_31_STFSX
- OP_31_STFUX
- OP_31_STFX
- OP_31_XOP_DCBA
- OP_31_XOP_DCBF
- OP_31_XOP_DCBI
- OP_31_XOP_DCBST
- OP_31_XOP_DCBZ
- OP_31_XOP_EIOIO
- OP_31_XOP_FAKE_SC1
- OP_31_XOP_LBZUX
- OP_31_XOP_LBZX
- OP_31_XOP_LDBRX
- OP_31_XOP_LDUX
- OP_31_XOP_LDX
- OP_31_XOP_LFDUX
- OP_31_XOP_LFDX
- OP_31_XOP_LFIWAX
- OP_31_XOP_LFIWZX
- OP_31_XOP_LFSUX
- OP_31_XOP_LFSX
- OP_31_XOP_LHAUX
- OP_31_XOP_LHAX
- OP_31_XOP_LHBRX
- OP_31_XOP_LHZUX
- OP_31_XOP_LHZX
- OP_31_XOP_LVX
- OP_31_XOP_LWAUX
- OP_31_XOP_LWAX
- OP_31_XOP_LWBRX
- OP_31_XOP_LWZUX
- OP_31_XOP_LWZX
- OP_31_XOP_LXSDX
- OP_31_XOP_LXSIWAX
- OP_31_XOP_LXSIWZX
- OP_31_XOP_LXSSPX
- OP_31_XOP_LXVD2X
- OP_31_XOP_LXVDSX
- OP_31_XOP_LXVW4X
- OP_31_XOP_MFMSR
- OP_31_XOP_MFSPR
- OP_31_XOP_MFSR
- OP_31_XOP_MFSRIN
- OP_31_XOP_MSGCLRP
- OP_31_XOP_MSGSNDP
- OP_31_XOP_MTMSR
- OP_31_XOP_MTMSRD
- OP_31_XOP_MTSPR
- OP_31_XOP_MTSR
- OP_31_XOP_MTSRIN
- OP_31_XOP_SLBFEE
- OP_31_XOP_SLBIA
- OP_31_XOP_SLBIE
- OP_31_XOP_SLBMFEE
- OP_31_XOP_SLBMFEV
- OP_31_XOP_SLBMTE
- OP_31_XOP_STBUX
- OP_31_XOP_STBX
- OP_31_XOP_STDBRX
- OP_31_XOP_STDUX
- OP_31_XOP_STDX
- OP_31_XOP_STFDUX
- OP_31_XOP_STFDX
- OP_31_XOP_STFIWX
- OP_31_XOP_STFSUX
- OP_31_XOP_STFSX
- OP_31_XOP_STHBRX
- OP_31_XOP_STHUX
- OP_31_XOP_STHX
- OP_31_XOP_STVX
- OP_31_XOP_STWBRX
- OP_31_XOP_STWUX
- OP_31_XOP_STWX
- OP_31_XOP_STXSDX
- OP_31_XOP_STXSIWX
- OP_31_XOP_STXSSPX
- OP_31_XOP_STXVD2X
- OP_31_XOP_STXVW4X
- OP_31_XOP_TABORT
- OP_31_XOP_TBEGIN
- OP_31_XOP_TLBIE
- OP_31_XOP_TLBIEL
- OP_31_XOP_TLBSYNC
- OP_31_XOP_TRAP
- OP_31_XOP_TRAP_64
- OP_31_XOP_TRCHKPT
- OP_31_XOP_TRECLAIM
- OP_31_XOP_WRTEE
- OP_31_XOP_WRTEEI
- OP_3DPRIMITIVE
- OP_3DSTATE_AA_LINE_PARAMS
- OP_3DSTATE_BINDING_TABLE_EDIT_DS
- OP_3DSTATE_BINDING_TABLE_EDIT_GS
- OP_3DSTATE_BINDING_TABLE_EDIT_HS
- OP_3DSTATE_BINDING_TABLE_EDIT_PS
- OP_3DSTATE_BINDING_TABLE_EDIT_VS
- OP_3DSTATE_BINDING_TABLE_POINTERS_DS
- OP_3DSTATE_BINDING_TABLE_POINTERS_GS
- OP_3DSTATE_BINDING_TABLE_POINTERS_HS
- OP_3DSTATE_BINDING_TABLE_POINTERS_PS
- OP_3DSTATE_BINDING_TABLE_POINTERS_VS
- OP_3DSTATE_BINDING_TABLE_POOL_ALLOC
- OP_3DSTATE_BLEND_STATE_POINTERS
- OP_3DSTATE_CC_STATE_POINTERS
- OP_3DSTATE_CHROMA_KEY
- OP_3DSTATE_CLEAR_PARAMS
- OP_3DSTATE_CLIP
- OP_3DSTATE_COMPONENT_PACKING
- OP_3DSTATE_CONSTANT_DS
- OP_3DSTATE_CONSTANT_GS
- OP_3DSTATE_CONSTANT_HS
- OP_3DSTATE_CONSTANT_PS
- OP_3DSTATE_CONSTANT_VS
- OP_3DSTATE_DEPTH_BUFFER
- OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS
- OP_3DSTATE_DRAWING_RECTANGLE
- OP_3DSTATE_DS
- OP_3DSTATE_DX9_CONSTANTB_PS
- OP_3DSTATE_DX9_CONSTANTB_VS
- OP_3DSTATE_DX9_CONSTANTF_PS
- OP_3DSTATE_DX9_CONSTANTF_VS
- OP_3DSTATE_DX9_CONSTANTI_PS
- OP_3DSTATE_DX9_CONSTANTI_VS
- OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC
- OP_3DSTATE_DX9_GENERATE_ACTIVE_PS
- OP_3DSTATE_DX9_GENERATE_ACTIVE_VS
- OP_3DSTATE_DX9_LOCAL_VALID_PS
- OP_3DSTATE_DX9_LOCAL_VALID_VS
- OP_3DSTATE_GATHER_CONSTANT_DS
- OP_3DSTATE_GATHER_CONSTANT_GS
- OP_3DSTATE_GATHER_CONSTANT_HS
- OP_3DSTATE_GATHER_CONSTANT_PS
- OP_3DSTATE_GATHER_CONSTANT_VS
- OP_3DSTATE_GATHER_POOL_ALLOC
- OP_3DSTATE_GS
- OP_3DSTATE_GS_SVB_INDEX
- OP_3DSTATE_HIER_DEPTH_BUFFER
- OP_3DSTATE_HS
- OP_3DSTATE_INDEX_BUFFER
- OP_3DSTATE_LINE_STIPPLE
- OP_3DSTATE_MONOFILTER_SIZE
- OP_3DSTATE_MULTISAMPLE_BDW
- OP_3DSTATE_POLY_STIPPLE_OFFSET
- OP_3DSTATE_POLY_STIPPLE_PATTERN
- OP_3DSTATE_PS
- OP_3DSTATE_PS_BLEND
- OP_3DSTATE_PS_EXTRA
- OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS
- OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS
- OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS
- OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS
- OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS
- OP_3DSTATE_RASTER
- OP_3DSTATE_SAMPLER_PALETTE_LOAD0
- OP_3DSTATE_SAMPLER_PALETTE_LOAD1
- OP_3DSTATE_SAMPLER_STATE_POINTERS_DS
- OP_3DSTATE_SAMPLER_STATE_POINTERS_GS
- OP_3DSTATE_SAMPLER_STATE_POINTERS_HS
- OP_3DSTATE_SAMPLER_STATE_POINTERS_PS
- OP_3DSTATE_SAMPLER_STATE_POINTERS_VS
- OP_3DSTATE_SAMPLE_MASK
- OP_3DSTATE_SAMPLE_PATTERN
- OP_3DSTATE_SBE
- OP_3DSTATE_SBE_SWIZ
- OP_3DSTATE_SCISSOR_STATE_POINTERS
- OP_3DSTATE_SF
- OP_3DSTATE_SO_BUFFER
- OP_3DSTATE_SO_DECL_LIST
- OP_3DSTATE_STENCIL_BUFFER
- OP_3DSTATE_STREAMOUT
- OP_3DSTATE_TE
- OP_3DSTATE_URB_DS
- OP_3DSTATE_URB_GS
- OP_3DSTATE_URB_HS
- OP_3DSTATE_URB_VS
- OP_3DSTATE_VERTEX_BUFFERS
- OP_3DSTATE_VERTEX_ELEMENTS
- OP_3DSTATE_VF
- OP_3DSTATE_VF_INSTANCING
- OP_3DSTATE_VF_SGVS
- OP_3DSTATE_VF_STATISTICS
- OP_3DSTATE_VF_STATISTICS_GM45
- OP_3DSTATE_VF_TOPOLOGY
- OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC
- OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP
- OP_3DSTATE_VS
- OP_3DSTATE_WM
- OP_3DSTATE_WM_CHROMAKEY
- OP_3DSTATE_WM_DEPTH_STENCIL
- OP_3DSTATE_WM_HZ_OP
- OP_3D_MEDIA
- OP_3D_MEDIA_0_1_4
- OP_4A_PS_ADD
- OP_4A_PS_DIV
- OP_4A_PS_MADD
- OP_4A_PS_MADDS0
- OP_4A_PS_MADDS1
- OP_4A_PS_MSUB
- OP_4A_PS_MUL
- OP_4A_PS_MULS0
- OP_4A_PS_MULS1
- OP_4A_PS_NMADD
- OP_4A_PS_NMSUB
- OP_4A_PS_RES
- OP_4A_PS_RSQRTE
- OP_4A_PS_SEL
- OP_4A_PS_SUB
- OP_4A_PS_SUM0
- OP_4A_PS_SUM1
- OP_4XW_PSQ_STUX
- OP_4XW_PSQ_STX
- OP_4X_PSQ_LUX
- OP_4X_PSQ_LX
- OP_4X_PS_ABS
- OP_4X_PS_CMPO0
- OP_4X_PS_CMPO1
- OP_4X_PS_CMPU0
- OP_4X_PS_CMPU1
- OP_4X_PS_MERGE00
- OP_4X_PS_MERGE01
- OP_4X_PS_MERGE10
- OP_4X_PS_MERGE11
- OP_4X_PS_MR
- OP_4X_PS_NABS
- OP_4X_PS_NEG
- OP_59_FADDS
- OP_59_FDIVS
- OP_59_FMADDS
- OP_59_FMSUBS
- OP_59_FMULS
- OP_59_FNMADDS
- OP_59_FNMSUBS
- OP_59_FRES
- OP_59_FRSQRTES
- OP_59_FSQRTS
- OP_59_FSUBS
- OP_63_FABS
- OP_63_FADD
- OP_63_FCMPO
- OP_63_FCMPU
- OP_63_FCPSGN
- OP_63_FCTIW
- OP_63_FCTIWZ
- OP_63_FDIV
- OP_63_FMADD
- OP_63_FMR
- OP_63_FMSUB
- OP_63_FMUL
- OP_63_FNEG
- OP_63_FNMADD
- OP_63_FNMSUB
- OP_63_FRE
- OP_63_FRSP
- OP_63_FRSQRTE
- OP_63_FSEL
- OP_63_FSQRT
- OP_63_FSUB
- OP_63_MCRFS
- OP_63_MFFS
- OP_63_MTFSB0
- OP_63_MTFSB1
- OP_63_MTFSF
- OP_63_MTFSFI
- OP_ABS
- OP_ACCEPT
- OP_ACCESS
- OP_ACTION
- OP_ACTION_DATA
- OP_ACTION_INDEX
- OP_ACTION_NOOP
- OP_ADD
- OP_ADDR64
- OP_ADDR64VLAN
- OP_ADDR_BUSW
- OP_ADDR_BYTES
- OP_ADDR_DDR
- OP_ADD_ARP_CACHE_ENTRY
- OP_ADD_LOCAL_MAC_IPADDR_ENTRY
- OP_AEQ_CREATE
- OP_AEQ_DESTROY
- OP_ALG_AAI_3385
- OP_ALG_AAI_802
- OP_ALG_AAI_AEAD
- OP_ALG_AAI_BC8
- OP_ALG_AAI_CBC
- OP_ALG_AAI_CBC_XCBCMAC
- OP_ALG_AAI_CCM
- OP_ALG_AAI_CFB
- OP_ALG_AAI_CHECKODD
- OP_ALG_AAI_CMAC
- OP_ALG_AAI_CTR_MOD104
- OP_ALG_AAI_CTR_MOD112
- OP_ALG_AAI_CTR_MOD120
- OP_ALG_AAI_CTR_MOD128
- OP_ALG_AAI_CTR_MOD16
- OP_ALG_AAI_CTR_MOD24
- OP_ALG_AAI_CTR_MOD32
- OP_ALG_AAI_CTR_MOD40
- OP_ALG_AAI_CTR_MOD48
- OP_ALG_AAI_CTR_MOD56
- OP_ALG_AAI_CTR_MOD64
- OP_ALG_AAI_CTR_MOD72
- OP_ALG_AAI_CTR_MOD8
- OP_ALG_AAI_CTR_MOD80
- OP_ALG_AAI_CTR_MOD88
- OP_ALG_AAI_CTR_MOD96
- OP_ALG_AAI_CTR_XCBCMAC
- OP_ALG_AAI_CUST_POLY
- OP_ALG_AAI_DIS
- OP_ALG_AAI_DK
- OP_ALG_AAI_DOC
- OP_ALG_AAI_DOS
- OP_ALG_AAI_ECB
- OP_ALG_AAI_EDGE
- OP_ALG_AAI_F8
- OP_ALG_AAI_F9
- OP_ALG_AAI_GCM
- OP_ALG_AAI_GSM
- OP_ALG_AAI_HASH
- OP_ALG_AAI_HMAC
- OP_ALG_AAI_HMAC_PRECOMP
- OP_ALG_AAI_KEYSTREAM
- OP_ALG_AAI_MASK
- OP_ALG_AAI_OFB
- OP_ALG_AAI_RNG
- OP_ALG_AAI_RNG4_AI
- OP_ALG_AAI_RNG4_PS
- OP_ALG_AAI_RNG4_SH_0
- OP_ALG_AAI_RNG4_SH_1
- OP_ALG_AAI_RNG4_SK
- OP_ALG_AAI_RNG_NZB
- OP_ALG_AAI_RNG_OBP
- OP_ALG_AAI_SHIFT
- OP_ALG_AAI_SMAC
- OP_ALG_AAI_XCBC_MAC
- OP_ALG_AAI_XTS
- OP_ALG_ALGSEL_3DES
- OP_ALG_ALGSEL_AES
- OP_ALG_ALGSEL_ARC4
- OP_ALG_ALGSEL_CHACHA20
- OP_ALG_ALGSEL_CRC
- OP_ALG_ALGSEL_DES
- OP_ALG_ALGSEL_KASUMI
- OP_ALG_ALGSEL_MASK
- OP_ALG_ALGSEL_MD5
- OP_ALG_ALGSEL_POLY1305
- OP_ALG_ALGSEL_RNG
- OP_ALG_ALGSEL_SHA1
- OP_ALG_ALGSEL_SHA224
- OP_ALG_ALGSEL_SHA256
- OP_ALG_ALGSEL_SHA384
- OP_ALG_ALGSEL_SHA512
- OP_ALG_ALGSEL_SHIFT
- OP_ALG_ALGSEL_SNOW
- OP_ALG_ALGSEL_SNOW_F8
- OP_ALG_ALGSEL_SNOW_F9
- OP_ALG_ALGSEL_SUBMASK
- OP_ALG_AS_FINALIZE
- OP_ALG_AS_INIT
- OP_ALG_AS_INITFINAL
- OP_ALG_AS_MASK
- OP_ALG_AS_SHIFT
- OP_ALG_AS_UPDATE
- OP_ALG_CHA_MDHA
- OP_ALG_DECRYPT
- OP_ALG_DIR_MASK
- OP_ALG_DIR_SHIFT
- OP_ALG_ENCRYPT
- OP_ALG_ICV_MASK
- OP_ALG_ICV_OFF
- OP_ALG_ICV_ON
- OP_ALG_ICV_SHIFT
- OP_ALG_PK
- OP_ALG_PKMODE_A_RAM
- OP_ALG_PKMODE_B_RAM
- OP_ALG_PKMODE_CLEARMEM
- OP_ALG_PKMODE_CPYMEM_N_SZ
- OP_ALG_PKMODE_CPYMEM_SRC_SZ
- OP_ALG_PKMODE_DST_REG_A
- OP_ALG_PKMODE_DST_REG_B
- OP_ALG_PKMODE_DST_REG_E
- OP_ALG_PKMODE_DST_REG_MASK
- OP_ALG_PKMODE_DST_REG_N
- OP_ALG_PKMODE_DST_REG_SHIFT
- OP_ALG_PKMODE_DST_SEG_0
- OP_ALG_PKMODE_DST_SEG_1
- OP_ALG_PKMODE_DST_SEG_2
- OP_ALG_PKMODE_DST_SEG_3
- OP_ALG_PKMODE_DST_SEG_MASK
- OP_ALG_PKMODE_DST_SEG_SHIFT
- OP_ALG_PKMODE_E_RAM
- OP_ALG_PKMODE_MOD_ADD
- OP_ALG_PKMODE_MOD_CRT_CNST
- OP_ALG_PKMODE_MOD_ECC_ADD
- OP_ALG_PKMODE_MOD_ECC_DBL
- OP_ALG_PKMODE_MOD_ECC_MULT
- OP_ALG_PKMODE_MOD_EXPO
- OP_ALG_PKMODE_MOD_F2M
- OP_ALG_PKMODE_MOD_GCD
- OP_ALG_PKMODE_MOD_INV
- OP_ALG_PKMODE_MOD_IN_MONTY
- OP_ALG_PKMODE_MOD_MONT_CNST
- OP_ALG_PKMODE_MOD_MULT
- OP_ALG_PKMODE_MOD_OUT_MONTY
- OP_ALG_PKMODE_MOD_PRIMALITY
- OP_ALG_PKMODE_MOD_R2_IN
- OP_ALG_PKMODE_MOD_REDUCT
- OP_ALG_PKMODE_MOD_SUB_AB
- OP_ALG_PKMODE_MOD_SUB_BA
- OP_ALG_PKMODE_N_RAM
- OP_ALG_PKMODE_OUT_A
- OP_ALG_PKMODE_OUT_B
- OP_ALG_PKMODE_PRJECTV
- OP_ALG_PKMODE_SRC_REG_A
- OP_ALG_PKMODE_SRC_REG_B
- OP_ALG_PKMODE_SRC_REG_MASK
- OP_ALG_PKMODE_SRC_REG_N
- OP_ALG_PKMODE_SRC_REG_SHIFT
- OP_ALG_PKMODE_SRC_SEG_0
- OP_ALG_PKMODE_SRC_SEG_1
- OP_ALG_PKMODE_SRC_SEG_2
- OP_ALG_PKMODE_SRC_SEG_3
- OP_ALG_PKMODE_SRC_SEG_MASK
- OP_ALG_PKMODE_SRC_SEG_SHIFT
- OP_ALG_PKMODE_TIME_EQ
- OP_ALG_PK_FUN_MASK
- OP_ALG_TYPE_CLASS1
- OP_ALG_TYPE_CLASS2
- OP_ALG_TYPE_MASK
- OP_ALG_TYPE_SHIFT
- OP_ALLOC
- OP_ALLOCATE
- OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY
- OP_ALLOC_STAG
- OP_ALU_A_SRC
- OP_ALU_BASE
- OP_ALU_B_SRC
- OP_ALU_DST
- OP_ALU_DST_AB
- OP_ALU_DST_LMEXTN
- OP_ALU_OP
- OP_ALU_SRC_LMEXTN
- OP_ALU_SW
- OP_ALU_WR_AB
- OP_AMOUNT
- OP_AMOUNT_0
- OP_AMOUNT_2
- OP_AMOUNT_4
- OP_AMOUNT_8
- OP_AND
- OP_BACKCHANNEL_CTL
- OP_BALU_BASE
- OP_BA_ADDR_HI
- OP_BA_A_SRC
- OP_BA_B_SRC
- OP_BA_DEFBR
- OP_BBYTE_BASE
- OP_BB_ADDR_HI
- OP_BB_ADDR_LO
- OP_BB_A_SRC
- OP_BB_BYTE
- OP_BB_B_SRC
- OP_BB_DEFBR
- OP_BB_EQ
- OP_BB_I8
- OP_BB_SRC_LMEXTN
- OP_BCH0
- OP_BCOPY
- OP_BIND
- OP_BIND_CONN_TO_SESSION
- OP_BITS
- OP_BLOCK_ERASE
- OP_BOOL
- OP_BR_ADDR_HI
- OP_BR_ADDR_LO
- OP_BR_ALU_A_SRC
- OP_BR_ALU_BASE
- OP_BR_ALU_BASE_MASK
- OP_BR_ALU_B_SRC
- OP_BR_ALU_DEFBR
- OP_BR_ALU_DST_LMEXTN
- OP_BR_ALU_IMM_HI
- OP_BR_ALU_SRC_LMEXTN
- OP_BR_BASE
- OP_BR_BASE_MASK
- OP_BR_BIT_ADDR_HI
- OP_BR_BIT_ADDR_LO
- OP_BR_BIT_A_SRC
- OP_BR_BIT_BASE
- OP_BR_BIT_BASE_MASK
- OP_BR_BIT_BV
- OP_BR_BIT_B_SRC
- OP_BR_BIT_DEFBR
- OP_BR_BIT_SRC_LMEXTN
- OP_BR_CSS
- OP_BR_DEFBR
- OP_BR_EV_PIP
- OP_BR_MASK
- OP_BSTORE
- OP_BT_PRIORITY_DETECTED
- OP_BT_SCAN
- OP_BUFFER
- OP_BUFFER_FLAGS
- OP_BURSTSIZE
- OP_BUSW_1
- OP_BUSW_2
- OP_BUSW_4
- OP_BUSW_8
- OP_CACHEME
- OP_CALL
- OP_CAPABLE
- OP_CARB_BASE
- OP_CARB_OR
- OP_CB_GETATTR
- OP_CB_ILLEGAL
- OP_CB_LAYOUTRECALL
- OP_CB_NOTIFY
- OP_CB_NOTIFY_DEVICEID
- OP_CB_NOTIFY_LOCK
- OP_CB_OFFLOAD
- OP_CB_PUSH_DELEG
- OP_CB_RECALL
- OP_CB_RECALLABLE_OBJ_AVAIL
- OP_CB_RECALL_ANY
- OP_CB_RECALL_SLOT
- OP_CB_SEQUENCE
- OP_CB_WANTS_CANCELLED
- OP_CEQ_CREATE
- OP_CEQ_DESTROY
- OP_CFG_ADDR_NUM
- OP_CFG_DUMMY_NUM
- OP_CFG_FM_CS
- OP_CFG_MEM_IF_TYPE
- OP_CHANGE_HAT
- OP_CHANGE_ONEXEC
- OP_CHANGE_PROFILE
- OP_CHMOD
- OP_CHOWN
- OP_CLEAR_STATEID
- OP_CLONE
- OP_CLOSE
- OP_CMD_A_SRC
- OP_CMD_BUSW
- OP_CMD_BYTES
- OP_CMD_B_SRC
- OP_CMD_CNT
- OP_CMD_CTX
- OP_CMD_DDR
- OP_CMD_INDIR
- OP_CMD_MODE
- OP_CMD_SIG
- OP_CMD_TGT_CMD
- OP_CMD_TOKEN
- OP_CMD_XFER
- OP_CMP
- OP_CMPA
- OP_CMPS
- OP_COMMIT
- OP_COMMIT_FPM_VALUES
- OP_COMPARE_BUF1
- OP_COMPARE_BUF2
- OP_COMPLETED
- OP_COMPLETED_COMMANDS
- OP_CONNECT
- OP_CONVERT_NORMAL_TO_TUNNEL
- OP_CONVERT_TUNNEL_TO_NORMAL
- OP_COPY
- OP_COPY_NOTIFY
- OP_COUNTER_H
- OP_CQ_CREATE
- OP_CQ_DESTROY
- OP_CREATE
- OP_CREATE_SESSION
- OP_CRYPKEY
- OP_CTRL
- OP_CTRL_DMA_OP_READY
- OP_CTRL_RD_OPCODE
- OP_CTRL_RW_OP
- OP_CTRL_WR_OPCODE
- OP_CTR_OVERFLOW
- OP_DATA_BTN_MASK
- OP_DATA_BUSW
- OP_DATA_DDR
- OP_DATA_LEFT_BTN
- OP_DATA_MIDDLE_BTN
- OP_DATA_RIGHT_BTN
- OP_DATA_VALID
- OP_DCMD_READ_CONFIG
- OP_DD
- OP_DEALLOCATE
- OP_DEALLOC_STAG
- OP_DEL
- OP_DELEGPURGE
- OP_DELEGRETURN
- OP_DELETE_ARP_CACHE_ENTRY
- OP_DELETE_LOCAL_MAC_IPADDR_ENTRY
- OP_DEL_LOGDRV
- OP_DESTROY_CLIENTID
- OP_DESTROY_SESSION
- OP_DEST_LEAVE
- OP_DEST_MEM
- OP_DEST_PUSH
- OP_DEST_PUSHF
- OP_DEST_REG
- OP_DEST_REG_INDIRECT
- OP_DEVICEADDR
- OP_DEVINFO
- OP_DEVLC
- OP_DEVLIST
- OP_DIV
- OP_DONE_INTR_SHIFT
- OP_DPO
- OP_DPOA
- OP_DPOL
- OP_DPR
- OP_DPRA
- OP_DPRL
- OP_DQS_EN
- OP_DS
- OP_DSC
- OP_DSS
- OP_DSSC
- OP_DSTP
- OP_DUMMY_CYC
- OP_DUP
- OP_DUPN
- OP_DYNA
- OP_END
- OP_ENDPTCOMPLETE
- OP_ENDPTCTRL
- OP_ENDPTFLUSH
- OP_ENDPTLISTADDR
- OP_ENDPTPRIME
- OP_ENDPTSETUPSTAT
- OP_ENDPTSTAT
- OP_ENHC_EN
- OP_EPERM
- OP_EPOLL_ADD
- OP_EPOLL_DEL
- OP_EPOLL_MOD
- OP_EQ
- OP_EQU
- OP_ERASE_BLOCK
- OP_ERASE_PAGE
- OP_EVENT_MASK
- OP_EXCHANGE_ID
- OP_EXEC
- OP_EXIT
- OP_EXP
- OP_EXPORT
- OP_EXPT
- OP_EXPV
- OP_F
- OP_FAILED
- OP_FETCH_ID
- OP_FINAL
- OP_FLOCK
- OP_FLUSH
- OP_FLUSH_N_INV
- OP_FMMAP
- OP_FMPROT
- OP_FPERM
- OP_FRECEIVE
- OP_FREE_STATEID
- OP_GAMER
- OP_GAMERR
- OP_GAMIR
- OP_GAMIRR
- OP_GAMXR
- OP_GEN_AE
- OP_GEN_AGG_VECT
- OP_GEN_PARAM
- OP_GEN_TYPE
- OP_GETATTR
- OP_GETDEVICEINFO
- OP_GETDEVICELIST
- OP_GETFH
- OP_GETPEERNAME
- OP_GETSOCKNAME
- OP_GETSOCKOPT
- OP_GET_DIR_DELEGATION
- OP_GET_LDID_MAP
- OP_GPGPU_WALKER
- OP_GT
- OP_HANDLES_WRONGSEC
- OP_HAS_RETURN_VALUE
- OP_I
- OP_IDLE
- OP_IF_MODE_AND
- OP_IF_MODE_OR
- OP_ILLEGAL
- OP_IMM
- OP_IMMED_A_SRC
- OP_IMMED_BASE
- OP_IMMED_B_SRC
- OP_IMMED_DST_LMEXTN
- OP_IMMED_IMM
- OP_IMMED_INV
- OP_IMMED_SHIFT
- OP_IMMED_SRC_LMEXTN
- OP_IMMED_WIDTH
- OP_IMMED_WR_AB
- OP_IMPL_H
- OP_IMPORT
- OP_INHERIT
- OP_INT_MASK
- OP_INV
- OP_INV_IC
- OP_IN_PROGRESS
- OP_IO_ADVISE
- OP_IPO
- OP_IPOA
- OP_IPOL
- OP_IPR
- OP_IPRA
- OP_IPRL
- OP_IS
- OP_ISC
- OP_ISS
- OP_ISSC
- OP_ISTP
- OP_IS_LOAD_STORE
- OP_IS_PUTFH_LIKE
- OP_IVLOAD
- OP_IVSET
- OP_IVSTORE
- OP_JMP
- OP_JMPZ
- OP_LARGESEND
- OP_LAST
- OP_LAYOUTCOMMIT
- OP_LAYOUTERROR
- OP_LAYOUTGET
- OP_LAYOUTRETURN
- OP_LAYOUTSTATS
- OP_LBZ
- OP_LBZU
- OP_LCD_CENTERING
- OP_LCD_MODE
- OP_LCD_PANEL_ID
- OP_LCSR_ADDR
- OP_LCSR_A_SRC
- OP_LCSR_BASE
- OP_LCSR_B_SRC
- OP_LCSR_DST_LMEXTN
- OP_LCSR_SRC_LMEXTN
- OP_LCSR_WRITE
- OP_LD
- OP_LDF_A_SRC
- OP_LDF_BASE
- OP_LDF_BMASK
- OP_LDF_B_SRC
- OP_LDF_DST_LMEXTN
- OP_LDF_I8
- OP_LDF_SC
- OP_LDF_SHF
- OP_LDF_SRC_LMEXTN
- OP_LDF_SW
- OP_LDF_WR_AB
- OP_LDF_ZF
- OP_LDH
- OP_LDW
- OP_LENGTH_BIAS
- OP_LEN_2D
- OP_LEN_3D_MEDIA
- OP_LEN_MFX_VC
- OP_LEN_MI
- OP_LEN_VEBOX
- OP_LFD
- OP_LFDU
- OP_LFS
- OP_LFSU
- OP_LH
- OP_LHA
- OP_LHAU
- OP_LHZ
- OP_LHZU
- OP_LINK
- OP_LISTEN
- OP_LMW
- OP_LOCK
- OP_LOCKT
- OP_LOCKU
- OP_LOOKUP
- OP_LOOKUPP
- OP_LQ
- OP_LRGLEN
- OP_LRGLENVLAN
- OP_LSOV2
- OP_LT
- OP_LWZ
- OP_LWZU
- OP_MACSEC
- OP_MANAGE_APBVT_ENTRY
- OP_MANAGE_HMC_PM_FUNC_TABLE
- OP_MANAGE_PUSH_PAGE
- OP_MANAGE_QHASH_TABLE_ENTRY
- OP_MANAGE_VF_PBLE_BP
- OP_MASK
- OP_MAX
- OP_MAX_COUNTER
- OP_MEDIA_CURBE_LOAD
- OP_MEDIA_GATEWAY_STATE
- OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD
- OP_MEDIA_OBJECT
- OP_MEDIA_OBJECT_PRT
- OP_MEDIA_OBJECT_WALKER
- OP_MEDIA_POOL_STATE
- OP_MEDIA_STATE_FLUSH
- OP_MEDIA_VFE_STATE
- OP_MEM
- OP_MEM_STR
- OP_MESQ
- OP_MFC_AVC_PAK_OBJECT
- OP_MFC_MPEG2_PAK_OBJECT
- OP_MFC_MPEG2_SLICEGROUP_STATE
- OP_MFD_AVC_BSD_OBJECT
- OP_MFD_AVC_DPB_STATE
- OP_MFD_AVC_PICID_STATE
- OP_MFD_AVC_SLICEADDR
- OP_MFD_IT_OBJECT
- OP_MFD_JPEG_BSD_OBJECT
- OP_MFD_MPEG2_BSD_OBJECT
- OP_MFD_VC1_BSD_OBJECT
- OP_MFD_VC1_LONG_PIC_STATE
- OP_MFD_VC1_SHORT_PIC_STATE
- OP_MFX
- OP_MFX_2_6_0_0
- OP_MFX_2_6_0_8
- OP_MFX_2_6_0_9
- OP_MFX_AVC_DIRECTMODE_STATE
- OP_MFX_AVC_IMG_STATE
- OP_MFX_AVC_QM_STATE
- OP_MFX_AVC_REF_IDX_STATE
- OP_MFX_AVC_SLICE_STATE
- OP_MFX_AVC_WEIGHTOFFSET_STATE
- OP_MFX_BSP_BUF_BASE_ADDR_STATE
- OP_MFX_FQM_STATE
- OP_MFX_IND_OBJ_BASE_ADDR_STATE
- OP_MFX_JPEG_HUFF_TABLE_STATE
- OP_MFX_JPEG_PIC_STATE
- OP_MFX_MPEG2_PIC_STATE
- OP_MFX_MPEG2_QM_STATE
- OP_MFX_PAK_INSERT_OBJECT
- OP_MFX_PIPE_BUF_ADDR_STATE
- OP_MFX_PIPE_MODE_SELECT
- OP_MFX_QM_STATE
- OP_MFX_STATE_POINTER
- OP_MFX_STITCH_OBJECT
- OP_MFX_SURFACE_STATE
- OP_MFX_VC1_DIRECTMODE_STATE
- OP_MFX_VC1_PRED_PIPE_STATE
- OP_MFX_WAIT
- OP_MI_2E
- OP_MI_2F
- OP_MI_ARB_CHECK
- OP_MI_ARB_ON_OFF
- OP_MI_BATCH_BUFFER_END
- OP_MI_BATCH_BUFFER_START
- OP_MI_CLFLUSH
- OP_MI_CONDITIONAL_BATCH_BUFFER_END
- OP_MI_DISPLAY_FLIP
- OP_MI_FLUSH
- OP_MI_FLUSH_DW
- OP_MI_LOAD_REGISTER_IMM
- OP_MI_LOAD_REGISTER_MEM
- OP_MI_LOAD_REGISTER_REG
- OP_MI_LOAD_SCAN_LINES_INCL
- OP_MI_LOAD_URB_MEM
- OP_MI_MATH
- OP_MI_NOOP
- OP_MI_PREDICATE
- OP_MI_REPORT_HEAD
- OP_MI_REPORT_PERF_COUNT
- OP_MI_RS_CONTEXT
- OP_MI_RS_CONTROL
- OP_MI_RS_STORE_DATA_IMM
- OP_MI_SEMAPHORE_MBOX
- OP_MI_SEMAPHORE_SIGNAL
- OP_MI_SEMAPHORE_WAIT
- OP_MI_SET_APPID
- OP_MI_SET_CONTEXT
- OP_MI_SET_PREDICATE
- OP_MI_STORE_DATA_IMM
- OP_MI_STORE_DATA_INDEX
- OP_MI_STORE_REGISTER_MEM
- OP_MI_STORE_URM_MEM
- OP_MI_SUSPEND_FLUSH
- OP_MI_TOPOLOGY_FILTER
- OP_MI_UPDATE_GTT
- OP_MI_URB_ATOMIC_ALLOC
- OP_MI_URB_CLEAR
- OP_MI_USER_INTERRUPT
- OP_MI_WAIT_FOR_EVENT
- OP_MKDIR
- OP_MKNOD
- OP_MM
- OP_MOD
- OP_MODE
- OP_MODE_20MHZ_HT_STA_ASSOCED
- OP_MODE_ACTIVE
- OP_MODE_CD
- OP_MODE_CONF_REG
- OP_MODE_FBFC
- OP_MODE_FBS
- OP_MODE_MASK
- OP_MODE_MAY_BE_LEGACY_STAS
- OP_MODE_MIXED
- OP_MODE_OFFSET
- OP_MODE_PURE
- OP_MODE_SHIFT
- OP_MODE_SLEEP
- OP_MODIFIES_SOMETHING
- OP_MOD_XYZ
- OP_MOUNT
- OP_MREAD_BUFFER1
- OP_MREAD_BUFFER2
- OP_MR_REG_NON_SHARED
- OP_MSS
- OP_MSSVLAN
- OP_MULT
- OP_MUL_A_SRC
- OP_MUL_BASE
- OP_MUL_B_SRC
- OP_MUL_DST_AB
- OP_MUL_DST_LMEXTN
- OP_MUL_SRC_LMEXTN
- OP_MUL_STEP
- OP_MUL_SW
- OP_MUL_TYPE
- OP_MUL_WR_AB
- OP_MWERASE_BUFFER1
- OP_MWERASE_BUFFER2
- OP_MWRITE_BUFFER1
- OP_MWRITE_BUFFER2
- OP_MW_ALLOC
- OP_NEXT
- OP_NONE
- OP_NONTRIVIAL_ERROR_ENCODE
- OP_NOP
- OP_NOT
- OP_NP
- OP_NULL
- OP_NVERIFY
- OP_OCTA_CRC_EN
- OP_OFFLINE
- OP_OFFLOAD_CANCEL
- OP_OFFLOAD_STATUS
- OP_OPEN
- OP_OPENATTR
- OP_OPEN_CONFIRM
- OP_OPEN_DOWNGRADE
- OP_OR
- OP_OTGSC
- OP_PACKET
- OP_PAGE_PROGRAM_WITH_ECC
- OP_PAGE_READ
- OP_PAGE_READ_WITH_ECC
- OP_PAGE_READ_WITH_ECC_SPARE
- OP_PCHR
- OP_PCLID_BLOB
- OP_PCLID_DKP_MD5
- OP_PCLID_DKP_RIF_MD5
- OP_PCLID_DKP_RIF_SHA1
- OP_PCLID_DKP_RIF_SHA224
- OP_PCLID_DKP_RIF_SHA256
- OP_PCLID_DKP_RIF_SHA384
- OP_PCLID_DKP_RIF_SHA512
- OP_PCLID_DKP_SHA1
- OP_PCLID_DKP_SHA224
- OP_PCLID_DKP_SHA256
- OP_PCLID_DKP_SHA384
- OP_PCLID_DKP_SHA512
- OP_PCLID_DSASIGN
- OP_PCLID_DSAVERIFY
- OP_PCLID_DTLS
- OP_PCLID_DTLS10_PRF
- OP_PCLID_IKEV1_PRF
- OP_PCLID_IKEV2_PRF
- OP_PCLID_IPSEC
- OP_PCLID_MACSEC
- OP_PCLID_MASK
- OP_PCLID_PRF
- OP_PCLID_PUBLICKEYPAIR
- OP_PCLID_RSADEC_PRVKEY
- OP_PCLID_RSAENC_PUBKEY
- OP_PCLID_SECRETKEY
- OP_PCLID_SHIFT
- OP_PCLID_SRTP
- OP_PCLID_SSL30
- OP_PCLID_SSL30_PRF
- OP_PCLID_TLS10
- OP_PCLID_TLS10_PRF
- OP_PCLID_TLS11
- OP_PCLID_TLS11_PRF
- OP_PCLID_TLS12
- OP_PCLID_WIFI
- OP_PCLID_WIMAX
- OP_PCLINFO_MASK
- OP_PCL_DKP_DST_IMM
- OP_PCL_DKP_DST_MASK
- OP_PCL_DKP_DST_PTR
- OP_PCL_DKP_DST_SEQ
- OP_PCL_DKP_DST_SGF
- OP_PCL_DKP_DST_SHIFT
- OP_PCL_DKP_KEY_MASK
- OP_PCL_DKP_KEY_SHIFT
- OP_PCL_DKP_SRC_IMM
- OP_PCL_DKP_SRC_MASK
- OP_PCL_DKP_SRC_PTR
- OP_PCL_DKP_SRC_SEQ
- OP_PCL_DKP_SRC_SGF
- OP_PCL_DKP_SRC_SHIFT
- OP_PCL_DTLS_3DES_EDE_CBC_MD5
- OP_PCL_DTLS_3DES_EDE_CBC_SHA
- OP_PCL_DTLS_3DES_EDE_CBC_SHA160
- OP_PCL_DTLS_3DES_EDE_CBC_SHA224
- OP_PCL_DTLS_3DES_EDE_CBC_SHA256
- OP_PCL_DTLS_3DES_EDE_CBC_SHA384
- OP_PCL_DTLS_3DES_EDE_CBC_SHA512
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_10
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_11
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_12
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_13
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_14
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_15
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_16
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_17
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_18
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_2
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_3
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_4
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_5
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_6
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_7
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_8
- OP_PCL_DTLS_3DES_EDE_CBC_SHA_9
- OP_PCL_DTLS_AES_128_CBC_SHA
- OP_PCL_DTLS_AES_128_CBC_SHA160
- OP_PCL_DTLS_AES_128_CBC_SHA224
- OP_PCL_DTLS_AES_128_CBC_SHA256
- OP_PCL_DTLS_AES_128_CBC_SHA384
- OP_PCL_DTLS_AES_128_CBC_SHA512
- OP_PCL_DTLS_AES_128_CBC_SHA_10
- OP_PCL_DTLS_AES_128_CBC_SHA_11
- OP_PCL_DTLS_AES_128_CBC_SHA_12
- OP_PCL_DTLS_AES_128_CBC_SHA_13
- OP_PCL_DTLS_AES_128_CBC_SHA_14
- OP_PCL_DTLS_AES_128_CBC_SHA_15
- OP_PCL_DTLS_AES_128_CBC_SHA_16
- OP_PCL_DTLS_AES_128_CBC_SHA_17
- OP_PCL_DTLS_AES_128_CBC_SHA_2
- OP_PCL_DTLS_AES_128_CBC_SHA_3
- OP_PCL_DTLS_AES_128_CBC_SHA_4
- OP_PCL_DTLS_AES_128_CBC_SHA_5
- OP_PCL_DTLS_AES_128_CBC_SHA_6
- OP_PCL_DTLS_AES_128_CBC_SHA_7
- OP_PCL_DTLS_AES_128_CBC_SHA_8
- OP_PCL_DTLS_AES_128_CBC_SHA_9
- OP_PCL_DTLS_AES_192_CBC_SHA160
- OP_PCL_DTLS_AES_192_CBC_SHA224
- OP_PCL_DTLS_AES_192_CBC_SHA256
- OP_PCL_DTLS_AES_192_CBC_SHA384
- OP_PCL_DTLS_AES_192_CBC_SHA512
- OP_PCL_DTLS_AES_256_CBC_SHA
- OP_PCL_DTLS_AES_256_CBC_SHA160
- OP_PCL_DTLS_AES_256_CBC_SHA224
- OP_PCL_DTLS_AES_256_CBC_SHA256
- OP_PCL_DTLS_AES_256_CBC_SHA384
- OP_PCL_DTLS_AES_256_CBC_SHA512
- OP_PCL_DTLS_AES_256_CBC_SHA_10
- OP_PCL_DTLS_AES_256_CBC_SHA_11
- OP_PCL_DTLS_AES_256_CBC_SHA_12
- OP_PCL_DTLS_AES_256_CBC_SHA_13
- OP_PCL_DTLS_AES_256_CBC_SHA_14
- OP_PCL_DTLS_AES_256_CBC_SHA_15
- OP_PCL_DTLS_AES_256_CBC_SHA_16
- OP_PCL_DTLS_AES_256_CBC_SHA_17
- OP_PCL_DTLS_AES_256_CBC_SHA_2
- OP_PCL_DTLS_AES_256_CBC_SHA_3
- OP_PCL_DTLS_AES_256_CBC_SHA_4
- OP_PCL_DTLS_AES_256_CBC_SHA_5
- OP_PCL_DTLS_AES_256_CBC_SHA_6
- OP_PCL_DTLS_AES_256_CBC_SHA_7
- OP_PCL_DTLS_AES_256_CBC_SHA_8
- OP_PCL_DTLS_AES_256_CBC_SHA_9
- OP_PCL_DTLS_DES40_CBC_MD5
- OP_PCL_DTLS_DES40_CBC_SHA
- OP_PCL_DTLS_DES40_CBC_SHA_2
- OP_PCL_DTLS_DES40_CBC_SHA_3
- OP_PCL_DTLS_DES40_CBC_SHA_4
- OP_PCL_DTLS_DES40_CBC_SHA_5
- OP_PCL_DTLS_DES40_CBC_SHA_6
- OP_PCL_DTLS_DES40_CBC_SHA_7
- OP_PCL_DTLS_DES_CBC_MD5
- OP_PCL_DTLS_DES_CBC_SHA
- OP_PCL_DTLS_DES_CBC_SHA_2
- OP_PCL_DTLS_DES_CBC_SHA_3
- OP_PCL_DTLS_DES_CBC_SHA_4
- OP_PCL_DTLS_DES_CBC_SHA_5
- OP_PCL_DTLS_DES_CBC_SHA_6
- OP_PCL_DTLS_DES_CBC_SHA_7
- OP_PCL_IPSEC_3DES
- OP_PCL_IPSEC_AES_CBC
- OP_PCL_IPSEC_AES_CCM12
- OP_PCL_IPSEC_AES_CCM16
- OP_PCL_IPSEC_AES_CCM8
- OP_PCL_IPSEC_AES_CTR
- OP_PCL_IPSEC_AES_GCM12
- OP_PCL_IPSEC_AES_GCM16
- OP_PCL_IPSEC_AES_GCM8
- OP_PCL_IPSEC_AES_XCBC_MAC_96
- OP_PCL_IPSEC_AES_XTS
- OP_PCL_IPSEC_AUTH_MASK
- OP_PCL_IPSEC_CIPHER_MASK
- OP_PCL_IPSEC_DES
- OP_PCL_IPSEC_DES_IV64
- OP_PCL_IPSEC_HMAC_MD5_128
- OP_PCL_IPSEC_HMAC_MD5_96
- OP_PCL_IPSEC_HMAC_NULL
- OP_PCL_IPSEC_HMAC_SHA1_160
- OP_PCL_IPSEC_HMAC_SHA1_96
- OP_PCL_IPSEC_HMAC_SHA2_256_128
- OP_PCL_IPSEC_HMAC_SHA2_384_192
- OP_PCL_IPSEC_HMAC_SHA2_512_256
- OP_PCL_MACSEC
- OP_PCL_PKPROT_DECRYPT
- OP_PCL_PKPROT_ECC
- OP_PCL_PKPROT_F2M
- OP_PCL_PKPROT_TEST
- OP_PCL_SRTP_AES_CTR
- OP_PCL_SRTP_AUTH_MASK
- OP_PCL_SRTP_CIPHER_MASK
- OP_PCL_SRTP_HMAC_SHA1_160
- OP_PCL_SSL30_3DES_EDE_CBC_MD5
- OP_PCL_SSL30_3DES_EDE_CBC_SHA
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_10
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_11
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_12
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_13
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_14
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_15
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_16
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_17
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_18
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_2
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_3
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_4
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_5
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_6
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_7
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_8
- OP_PCL_SSL30_3DES_EDE_CBC_SHA_9
- OP_PCL_SSL30_AES_128_CBC_SHA
- OP_PCL_SSL30_AES_128_CBC_SHA_10
- OP_PCL_SSL30_AES_128_CBC_SHA_11
- OP_PCL_SSL30_AES_128_CBC_SHA_12
- OP_PCL_SSL30_AES_128_CBC_SHA_13
- OP_PCL_SSL30_AES_128_CBC_SHA_14
- OP_PCL_SSL30_AES_128_CBC_SHA_15
- OP_PCL_SSL30_AES_128_CBC_SHA_16
- OP_PCL_SSL30_AES_128_CBC_SHA_17
- OP_PCL_SSL30_AES_128_CBC_SHA_2
- OP_PCL_SSL30_AES_128_CBC_SHA_3
- OP_PCL_SSL30_AES_128_CBC_SHA_4
- OP_PCL_SSL30_AES_128_CBC_SHA_5
- OP_PCL_SSL30_AES_128_CBC_SHA_6
- OP_PCL_SSL30_AES_128_CBC_SHA_7
- OP_PCL_SSL30_AES_128_CBC_SHA_8
- OP_PCL_SSL30_AES_128_CBC_SHA_9
- OP_PCL_SSL30_AES_256_CBC_SHA
- OP_PCL_SSL30_AES_256_CBC_SHA_10
- OP_PCL_SSL30_AES_256_CBC_SHA_11
- OP_PCL_SSL30_AES_256_CBC_SHA_12
- OP_PCL_SSL30_AES_256_CBC_SHA_13
- OP_PCL_SSL30_AES_256_CBC_SHA_14
- OP_PCL_SSL30_AES_256_CBC_SHA_15
- OP_PCL_SSL30_AES_256_CBC_SHA_16
- OP_PCL_SSL30_AES_256_CBC_SHA_17
- OP_PCL_SSL30_AES_256_CBC_SHA_2
- OP_PCL_SSL30_AES_256_CBC_SHA_3
- OP_PCL_SSL30_AES_256_CBC_SHA_4
- OP_PCL_SSL30_AES_256_CBC_SHA_5
- OP_PCL_SSL30_AES_256_CBC_SHA_6
- OP_PCL_SSL30_AES_256_CBC_SHA_7
- OP_PCL_SSL30_AES_256_CBC_SHA_8
- OP_PCL_SSL30_AES_256_CBC_SHA_9
- OP_PCL_SSL30_DES40_CBC_MD5
- OP_PCL_SSL30_DES40_CBC_SHA
- OP_PCL_SSL30_DES40_CBC_SHA_2
- OP_PCL_SSL30_DES40_CBC_SHA_3
- OP_PCL_SSL30_DES40_CBC_SHA_4
- OP_PCL_SSL30_DES40_CBC_SHA_5
- OP_PCL_SSL30_DES40_CBC_SHA_6
- OP_PCL_SSL30_DES40_CBC_SHA_7
- OP_PCL_SSL30_DES_CBC_MD5
- OP_PCL_SSL30_DES_CBC_SHA
- OP_PCL_SSL30_DES_CBC_SHA_2
- OP_PCL_SSL30_DES_CBC_SHA_3
- OP_PCL_SSL30_DES_CBC_SHA_4
- OP_PCL_SSL30_DES_CBC_SHA_5
- OP_PCL_SSL30_DES_CBC_SHA_6
- OP_PCL_SSL30_DES_CBC_SHA_7
- OP_PCL_SSL30_RC4_128_MD5
- OP_PCL_SSL30_RC4_128_MD5_2
- OP_PCL_SSL30_RC4_128_MD5_3
- OP_PCL_SSL30_RC4_128_SHA
- OP_PCL_SSL30_RC4_128_SHA_10
- OP_PCL_SSL30_RC4_128_SHA_2
- OP_PCL_SSL30_RC4_128_SHA_3
- OP_PCL_SSL30_RC4_128_SHA_4
- OP_PCL_SSL30_RC4_128_SHA_5
- OP_PCL_SSL30_RC4_128_SHA_6
- OP_PCL_SSL30_RC4_128_SHA_7
- OP_PCL_SSL30_RC4_128_SHA_8
- OP_PCL_SSL30_RC4_128_SHA_9
- OP_PCL_SSL30_RC4_40_MD5
- OP_PCL_SSL30_RC4_40_MD5_2
- OP_PCL_SSL30_RC4_40_MD5_3
- OP_PCL_SSL30_RC4_40_SHA
- OP_PCL_TLS10_3DES_EDE_CBC_MD5
- OP_PCL_TLS10_3DES_EDE_CBC_SHA
- OP_PCL_TLS10_3DES_EDE_CBC_SHA160
- OP_PCL_TLS10_3DES_EDE_CBC_SHA224
- OP_PCL_TLS10_3DES_EDE_CBC_SHA256
- OP_PCL_TLS10_3DES_EDE_CBC_SHA384
- OP_PCL_TLS10_3DES_EDE_CBC_SHA512
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_10
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_11
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_12
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_13
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_14
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_15
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_16
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_17
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_18
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_2
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_3
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_4
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_5
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_6
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_7
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_8
- OP_PCL_TLS10_3DES_EDE_CBC_SHA_9
- OP_PCL_TLS10_AES_128_CBC_SHA
- OP_PCL_TLS10_AES_128_CBC_SHA160
- OP_PCL_TLS10_AES_128_CBC_SHA224
- OP_PCL_TLS10_AES_128_CBC_SHA256
- OP_PCL_TLS10_AES_128_CBC_SHA384
- OP_PCL_TLS10_AES_128_CBC_SHA512
- OP_PCL_TLS10_AES_128_CBC_SHA_10
- OP_PCL_TLS10_AES_128_CBC_SHA_11
- OP_PCL_TLS10_AES_128_CBC_SHA_12
- OP_PCL_TLS10_AES_128_CBC_SHA_13
- OP_PCL_TLS10_AES_128_CBC_SHA_14
- OP_PCL_TLS10_AES_128_CBC_SHA_15
- OP_PCL_TLS10_AES_128_CBC_SHA_16
- OP_PCL_TLS10_AES_128_CBC_SHA_17
- OP_PCL_TLS10_AES_128_CBC_SHA_2
- OP_PCL_TLS10_AES_128_CBC_SHA_3
- OP_PCL_TLS10_AES_128_CBC_SHA_4
- OP_PCL_TLS10_AES_128_CBC_SHA_5
- OP_PCL_TLS10_AES_128_CBC_SHA_6
- OP_PCL_TLS10_AES_128_CBC_SHA_7
- OP_PCL_TLS10_AES_128_CBC_SHA_8
- OP_PCL_TLS10_AES_128_CBC_SHA_9
- OP_PCL_TLS10_AES_192_CBC_SHA160
- OP_PCL_TLS10_AES_192_CBC_SHA224
- OP_PCL_TLS10_AES_192_CBC_SHA256
- OP_PCL_TLS10_AES_192_CBC_SHA384
- OP_PCL_TLS10_AES_192_CBC_SHA512
- OP_PCL_TLS10_AES_256_CBC_SHA
- OP_PCL_TLS10_AES_256_CBC_SHA160
- OP_PCL_TLS10_AES_256_CBC_SHA224
- OP_PCL_TLS10_AES_256_CBC_SHA256
- OP_PCL_TLS10_AES_256_CBC_SHA384
- OP_PCL_TLS10_AES_256_CBC_SHA512
- OP_PCL_TLS10_AES_256_CBC_SHA_10
- OP_PCL_TLS10_AES_256_CBC_SHA_11
- OP_PCL_TLS10_AES_256_CBC_SHA_12
- OP_PCL_TLS10_AES_256_CBC_SHA_13
- OP_PCL_TLS10_AES_256_CBC_SHA_14
- OP_PCL_TLS10_AES_256_CBC_SHA_15
- OP_PCL_TLS10_AES_256_CBC_SHA_16
- OP_PCL_TLS10_AES_256_CBC_SHA_17
- OP_PCL_TLS10_AES_256_CBC_SHA_2
- OP_PCL_TLS10_AES_256_CBC_SHA_3
- OP_PCL_TLS10_AES_256_CBC_SHA_4
- OP_PCL_TLS10_AES_256_CBC_SHA_5
- OP_PCL_TLS10_AES_256_CBC_SHA_6
- OP_PCL_TLS10_AES_256_CBC_SHA_7
- OP_PCL_TLS10_AES_256_CBC_SHA_8
- OP_PCL_TLS10_AES_256_CBC_SHA_9
- OP_PCL_TLS10_DES40_CBC_MD5
- OP_PCL_TLS10_DES40_CBC_SHA
- OP_PCL_TLS10_DES40_CBC_SHA_2
- OP_PCL_TLS10_DES40_CBC_SHA_3
- OP_PCL_TLS10_DES40_CBC_SHA_4
- OP_PCL_TLS10_DES40_CBC_SHA_5
- OP_PCL_TLS10_DES40_CBC_SHA_6
- OP_PCL_TLS10_DES40_CBC_SHA_7
- OP_PCL_TLS10_DES_CBC_MD5
- OP_PCL_TLS10_DES_CBC_SHA
- OP_PCL_TLS10_DES_CBC_SHA_2
- OP_PCL_TLS10_DES_CBC_SHA_3
- OP_PCL_TLS10_DES_CBC_SHA_4
- OP_PCL_TLS10_DES_CBC_SHA_5
- OP_PCL_TLS10_DES_CBC_SHA_6
- OP_PCL_TLS10_DES_CBC_SHA_7
- OP_PCL_TLS10_RC4_128_MD5
- OP_PCL_TLS10_RC4_128_MD5_2
- OP_PCL_TLS10_RC4_128_MD5_3
- OP_PCL_TLS10_RC4_128_SHA
- OP_PCL_TLS10_RC4_128_SHA_10
- OP_PCL_TLS10_RC4_128_SHA_2
- OP_PCL_TLS10_RC4_128_SHA_3
- OP_PCL_TLS10_RC4_128_SHA_4
- OP_PCL_TLS10_RC4_128_SHA_5
- OP_PCL_TLS10_RC4_128_SHA_6
- OP_PCL_TLS10_RC4_128_SHA_7
- OP_PCL_TLS10_RC4_128_SHA_8
- OP_PCL_TLS10_RC4_128_SHA_9
- OP_PCL_TLS10_RC4_40_MD5
- OP_PCL_TLS10_RC4_40_MD5_2
- OP_PCL_TLS10_RC4_40_MD5_3
- OP_PCL_TLS10_RC4_40_SHA
- OP_PCL_TLS11_3DES_EDE_CBC_MD5
- OP_PCL_TLS11_3DES_EDE_CBC_SHA
- OP_PCL_TLS11_3DES_EDE_CBC_SHA160
- OP_PCL_TLS11_3DES_EDE_CBC_SHA224
- OP_PCL_TLS11_3DES_EDE_CBC_SHA256
- OP_PCL_TLS11_3DES_EDE_CBC_SHA384
- OP_PCL_TLS11_3DES_EDE_CBC_SHA512
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_10
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_11
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_12
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_13
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_14
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_15
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_16
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_17
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_18
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_2
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_3
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_4
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_5
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_6
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_7
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_8
- OP_PCL_TLS11_3DES_EDE_CBC_SHA_9
- OP_PCL_TLS11_AES_128_CBC_SHA
- OP_PCL_TLS11_AES_128_CBC_SHA160
- OP_PCL_TLS11_AES_128_CBC_SHA224
- OP_PCL_TLS11_AES_128_CBC_SHA256
- OP_PCL_TLS11_AES_128_CBC_SHA384
- OP_PCL_TLS11_AES_128_CBC_SHA512
- OP_PCL_TLS11_AES_128_CBC_SHA_10
- OP_PCL_TLS11_AES_128_CBC_SHA_11
- OP_PCL_TLS11_AES_128_CBC_SHA_12
- OP_PCL_TLS11_AES_128_CBC_SHA_13
- OP_PCL_TLS11_AES_128_CBC_SHA_14
- OP_PCL_TLS11_AES_128_CBC_SHA_15
- OP_PCL_TLS11_AES_128_CBC_SHA_16
- OP_PCL_TLS11_AES_128_CBC_SHA_17
- OP_PCL_TLS11_AES_128_CBC_SHA_2
- OP_PCL_TLS11_AES_128_CBC_SHA_3
- OP_PCL_TLS11_AES_128_CBC_SHA_4
- OP_PCL_TLS11_AES_128_CBC_SHA_5
- OP_PCL_TLS11_AES_128_CBC_SHA_6
- OP_PCL_TLS11_AES_128_CBC_SHA_7
- OP_PCL_TLS11_AES_128_CBC_SHA_8
- OP_PCL_TLS11_AES_128_CBC_SHA_9
- OP_PCL_TLS11_AES_192_CBC_SHA160
- OP_PCL_TLS11_AES_192_CBC_SHA224
- OP_PCL_TLS11_AES_192_CBC_SHA256
- OP_PCL_TLS11_AES_192_CBC_SHA384
- OP_PCL_TLS11_AES_192_CBC_SHA512
- OP_PCL_TLS11_AES_256_CBC_SHA
- OP_PCL_TLS11_AES_256_CBC_SHA160
- OP_PCL_TLS11_AES_256_CBC_SHA224
- OP_PCL_TLS11_AES_256_CBC_SHA256
- OP_PCL_TLS11_AES_256_CBC_SHA384
- OP_PCL_TLS11_AES_256_CBC_SHA512
- OP_PCL_TLS11_AES_256_CBC_SHA_10
- OP_PCL_TLS11_AES_256_CBC_SHA_11
- OP_PCL_TLS11_AES_256_CBC_SHA_12
- OP_PCL_TLS11_AES_256_CBC_SHA_13
- OP_PCL_TLS11_AES_256_CBC_SHA_14
- OP_PCL_TLS11_AES_256_CBC_SHA_15
- OP_PCL_TLS11_AES_256_CBC_SHA_16
- OP_PCL_TLS11_AES_256_CBC_SHA_17
- OP_PCL_TLS11_AES_256_CBC_SHA_2
- OP_PCL_TLS11_AES_256_CBC_SHA_3
- OP_PCL_TLS11_AES_256_CBC_SHA_4
- OP_PCL_TLS11_AES_256_CBC_SHA_5
- OP_PCL_TLS11_AES_256_CBC_SHA_6
- OP_PCL_TLS11_AES_256_CBC_SHA_7
- OP_PCL_TLS11_AES_256_CBC_SHA_8
- OP_PCL_TLS11_AES_256_CBC_SHA_9
- OP_PCL_TLS11_DES40_CBC_MD5
- OP_PCL_TLS11_DES40_CBC_SHA
- OP_PCL_TLS11_DES40_CBC_SHA_2
- OP_PCL_TLS11_DES40_CBC_SHA_3
- OP_PCL_TLS11_DES40_CBC_SHA_4
- OP_PCL_TLS11_DES40_CBC_SHA_5
- OP_PCL_TLS11_DES40_CBC_SHA_6
- OP_PCL_TLS11_DES40_CBC_SHA_7
- OP_PCL_TLS11_DES_CBC_MD5
- OP_PCL_TLS11_DES_CBC_SHA
- OP_PCL_TLS11_DES_CBC_SHA_2
- OP_PCL_TLS11_DES_CBC_SHA_3
- OP_PCL_TLS11_DES_CBC_SHA_4
- OP_PCL_TLS11_DES_CBC_SHA_5
- OP_PCL_TLS11_DES_CBC_SHA_6
- OP_PCL_TLS11_DES_CBC_SHA_7
- OP_PCL_TLS11_RC4_128_MD5
- OP_PCL_TLS11_RC4_128_MD5_2
- OP_PCL_TLS11_RC4_128_MD5_3
- OP_PCL_TLS11_RC4_128_SHA
- OP_PCL_TLS11_RC4_128_SHA_10
- OP_PCL_TLS11_RC4_128_SHA_2
- OP_PCL_TLS11_RC4_128_SHA_3
- OP_PCL_TLS11_RC4_128_SHA_4
- OP_PCL_TLS11_RC4_128_SHA_5
- OP_PCL_TLS11_RC4_128_SHA_6
- OP_PCL_TLS11_RC4_128_SHA_7
- OP_PCL_TLS11_RC4_128_SHA_8
- OP_PCL_TLS11_RC4_128_SHA_9
- OP_PCL_TLS11_RC4_40_MD5
- OP_PCL_TLS11_RC4_40_MD5_2
- OP_PCL_TLS11_RC4_40_MD5_3
- OP_PCL_TLS11_RC4_40_SHA
- OP_PCL_TLS12_3DES_EDE_CBC_MD5
- OP_PCL_TLS12_3DES_EDE_CBC_SHA
- OP_PCL_TLS12_3DES_EDE_CBC_SHA160
- OP_PCL_TLS12_3DES_EDE_CBC_SHA224
- OP_PCL_TLS12_3DES_EDE_CBC_SHA256
- OP_PCL_TLS12_3DES_EDE_CBC_SHA384
- OP_PCL_TLS12_3DES_EDE_CBC_SHA512
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_10
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_11
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_12
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_13
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_14
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_15
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_16
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_17
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_18
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_2
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_3
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_4
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_5
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_6
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_7
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_8
- OP_PCL_TLS12_3DES_EDE_CBC_SHA_9
- OP_PCL_TLS12_AES_128_CBC_SHA
- OP_PCL_TLS12_AES_128_CBC_SHA160
- OP_PCL_TLS12_AES_128_CBC_SHA224
- OP_PCL_TLS12_AES_128_CBC_SHA256
- OP_PCL_TLS12_AES_128_CBC_SHA256_2
- OP_PCL_TLS12_AES_128_CBC_SHA256_3
- OP_PCL_TLS12_AES_128_CBC_SHA256_4
- OP_PCL_TLS12_AES_128_CBC_SHA256_5
- OP_PCL_TLS12_AES_128_CBC_SHA256_6
- OP_PCL_TLS12_AES_128_CBC_SHA384
- OP_PCL_TLS12_AES_128_CBC_SHA512
- OP_PCL_TLS12_AES_128_CBC_SHA_10
- OP_PCL_TLS12_AES_128_CBC_SHA_11
- OP_PCL_TLS12_AES_128_CBC_SHA_12
- OP_PCL_TLS12_AES_128_CBC_SHA_13
- OP_PCL_TLS12_AES_128_CBC_SHA_14
- OP_PCL_TLS12_AES_128_CBC_SHA_15
- OP_PCL_TLS12_AES_128_CBC_SHA_16
- OP_PCL_TLS12_AES_128_CBC_SHA_17
- OP_PCL_TLS12_AES_128_CBC_SHA_2
- OP_PCL_TLS12_AES_128_CBC_SHA_3
- OP_PCL_TLS12_AES_128_CBC_SHA_4
- OP_PCL_TLS12_AES_128_CBC_SHA_5
- OP_PCL_TLS12_AES_128_CBC_SHA_6
- OP_PCL_TLS12_AES_128_CBC_SHA_7
- OP_PCL_TLS12_AES_128_CBC_SHA_8
- OP_PCL_TLS12_AES_128_CBC_SHA_9
- OP_PCL_TLS12_AES_192_CBC_SHA160
- OP_PCL_TLS12_AES_192_CBC_SHA224
- OP_PCL_TLS12_AES_192_CBC_SHA256
- OP_PCL_TLS12_AES_192_CBC_SHA384
- OP_PCL_TLS12_AES_192_CBC_SHA512
- OP_PCL_TLS12_AES_256_CBC_SHA
- OP_PCL_TLS12_AES_256_CBC_SHA160
- OP_PCL_TLS12_AES_256_CBC_SHA224
- OP_PCL_TLS12_AES_256_CBC_SHA256
- OP_PCL_TLS12_AES_256_CBC_SHA256_2
- OP_PCL_TLS12_AES_256_CBC_SHA256_3
- OP_PCL_TLS12_AES_256_CBC_SHA256_4
- OP_PCL_TLS12_AES_256_CBC_SHA256_5
- OP_PCL_TLS12_AES_256_CBC_SHA256_6
- OP_PCL_TLS12_AES_256_CBC_SHA384
- OP_PCL_TLS12_AES_256_CBC_SHA512
- OP_PCL_TLS12_AES_256_CBC_SHA_10
- OP_PCL_TLS12_AES_256_CBC_SHA_11
- OP_PCL_TLS12_AES_256_CBC_SHA_12
- OP_PCL_TLS12_AES_256_CBC_SHA_13
- OP_PCL_TLS12_AES_256_CBC_SHA_14
- OP_PCL_TLS12_AES_256_CBC_SHA_15
- OP_PCL_TLS12_AES_256_CBC_SHA_16
- OP_PCL_TLS12_AES_256_CBC_SHA_17
- OP_PCL_TLS12_AES_256_CBC_SHA_2
- OP_PCL_TLS12_AES_256_CBC_SHA_3
- OP_PCL_TLS12_AES_256_CBC_SHA_4
- OP_PCL_TLS12_AES_256_CBC_SHA_5
- OP_PCL_TLS12_AES_256_CBC_SHA_6
- OP_PCL_TLS12_AES_256_CBC_SHA_7
- OP_PCL_TLS12_AES_256_CBC_SHA_8
- OP_PCL_TLS12_AES_256_CBC_SHA_9
- OP_PCL_TLS12_DES40_CBC_MD5
- OP_PCL_TLS12_DES40_CBC_SHA
- OP_PCL_TLS12_DES40_CBC_SHA_2
- OP_PCL_TLS12_DES40_CBC_SHA_3
- OP_PCL_TLS12_DES40_CBC_SHA_4
- OP_PCL_TLS12_DES40_CBC_SHA_5
- OP_PCL_TLS12_DES40_CBC_SHA_6
- OP_PCL_TLS12_DES40_CBC_SHA_7
- OP_PCL_TLS12_DES_CBC_MD5
- OP_PCL_TLS12_DES_CBC_SHA
- OP_PCL_TLS12_DES_CBC_SHA_2
- OP_PCL_TLS12_DES_CBC_SHA_3
- OP_PCL_TLS12_DES_CBC_SHA_4
- OP_PCL_TLS12_DES_CBC_SHA_5
- OP_PCL_TLS12_DES_CBC_SHA_6
- OP_PCL_TLS12_DES_CBC_SHA_7
- OP_PCL_TLS12_RC4_128_MD5
- OP_PCL_TLS12_RC4_128_MD5_2
- OP_PCL_TLS12_RC4_128_MD5_3
- OP_PCL_TLS12_RC4_128_SHA
- OP_PCL_TLS12_RC4_128_SHA_10
- OP_PCL_TLS12_RC4_128_SHA_2
- OP_PCL_TLS12_RC4_128_SHA_3
- OP_PCL_TLS12_RC4_128_SHA_4
- OP_PCL_TLS12_RC4_128_SHA_5
- OP_PCL_TLS12_RC4_128_SHA_6
- OP_PCL_TLS12_RC4_128_SHA_7
- OP_PCL_TLS12_RC4_128_SHA_8
- OP_PCL_TLS12_RC4_128_SHA_9
- OP_PCL_TLS12_RC4_40_MD5
- OP_PCL_TLS12_RC4_40_MD5_2
- OP_PCL_TLS12_RC4_40_MD5_3
- OP_PCL_TLS12_RC4_40_SHA
- OP_PCL_WIFI
- OP_PCL_WIMAX_OFDM
- OP_PCL_WIMAX_OFDMA
- OP_PINT
- OP_PIPELINE_SELECT
- OP_PIPE_CONTROL
- OP_PIVOTROOT
- OP_POPA
- OP_POPE
- OP_POPT
- OP_POPV
- OP_PORTSC
- OP_POST_CREATE
- OP_PREAMBLE_EN
- OP_PRNT
- OP_PROF_LOAD
- OP_PROF_REPL
- OP_PROF_RM
- OP_PROGRAM_PAGE
- OP_PROGRAM_PAGE_SPARE
- OP_PROGRAM_VIA_BUF1
- OP_PROGRAM_VIA_BUF2
- OP_PSH0
- OP_PSHA
- OP_PSHE
- OP_PSHL
- OP_PSHV
- OP_PSQ_L
- OP_PSQ_LU
- OP_PSQ_ST
- OP_PSQ_STU
- OP_PSTR
- OP_PTRACE
- OP_PUTFH
- OP_PUTIDX
- OP_PUTPUBFH
- OP_PUTROOTFH
- OP_QP_CREATE
- OP_QP_DESTROY
- OP_QP_FLUSH_WQES
- OP_QP_MODIFY
- OP_QP_UPLOAD_CONTEXT
- OP_QUERY_FPM_VALUES
- OP_RATE_SET_I
- OP_RD
- OP_READ
- OP_READDIR
- OP_READLINK
- OP_READ_BUFFER1
- OP_READ_BUFFER2
- OP_READ_CONTINUOUS
- OP_READ_ID
- OP_READ_PAGE
- OP_READ_PLUS
- OP_READ_SECURITY
- OP_READ_STATUS
- OP_RECALIBRATION_MASK
- OP_RECLAIM_COMPLETE
- OP_RECVMSG
- OP_REF_SIZE
- OP_REG
- OP_RELEASE_LOCKOWNER
- OP_RELO_TYPE
- OP_REMOVE
- OP_RENAME
- OP_RENAME_DEST
- OP_RENAME_SRC
- OP_RENEW
- OP_REPEAT
- OP_REPLY
- OP_REPORT_BASELINE_MASK
- OP_REP_CRYPKEY
- OP_REP_DEVINFO
- OP_REP_DEVLIST
- OP_REP_EXPORT
- OP_REP_IMPORT
- OP_REP_UNEXPORT
- OP_REP_UNSPEC
- OP_REQUEST
- OP_REQUESTED_COMMANDS
- OP_REQ_CRYPKEY
- OP_REQ_DEVINFO
- OP_REQ_DEVLIST
- OP_REQ_EXPORT
- OP_REQ_IMPORT
- OP_REQ_UNEXPORT
- OP_REQ_UNSPEC
- OP_RESET_DEVICE
- OP_RESTOREFH
- OP_RESUME
- OP_RET
- OP_REVA
- OP_REWRITE_VIA_BUF1
- OP_REWRITE_VIA_BUF2
- OP_RMDIR
- OP_RSS_HASH
- OP_RT_RA_MASK
- OP_RUNNING_INTERRUPT
- OP_RUNNING_POLL
- OP_RUNNING_POLL_INTR
- OP_RX
- OP_RXCHKS
- OP_RXCHKSVLAN
- OP_RXSTAT
- OP_RXTIMESTAMP
- OP_RXTIMEVLAN
- OP_RXVLAN
- OP_RX_STOP
- OP_RX_STOP_DATA
- OP_S
- OP_SAMM
- OP_SAVEFH
- OP_SCALAR
- OP_SD
- OP_SEARCH
- OP_SECINFO
- OP_SECINFO_NO_NAME
- OP_SEEK
- OP_SEL_MASK
- OP_SEL_READ
- OP_SEL_SEARCH
- OP_SEL_SHIFT
- OP_SEL_WRITE
- OP_SENDMSG
- OP_SEQUENCE
- OP_SETATTR
- OP_SETCLIENTID
- OP_SETCLIENTID_CONFIRM
- OP_SETPROCATTR
- OP_SETRLIMIT
- OP_SETSOCKOPT
- OP_SET_SSV
- OP_SH
- OP_SHF_A_SRC
- OP_SHF_BASE
- OP_SHF_B_SRC
- OP_SHF_DST
- OP_SHF_DST_AB
- OP_SHF_DST_LMEXTN
- OP_SHF_I8
- OP_SHF_OP
- OP_SHF_SC
- OP_SHF_SHIFT
- OP_SHF_SRC_LMEXTN
- OP_SHF_SW
- OP_SHF_WR_AB
- OP_SHL
- OP_SHORT_DATA
- OP_SHR
- OP_SHUTDOWN
- OP_SIGNAL
- OP_SINT
- OP_SIZE_CQP_STAT_ARRAY
- OP_SIZE_PREFIX
- OP_SM
- OP_SNB_3DSTATE_CLEAR_PARAMS
- OP_SNB_3DSTATE_DEPTH_BUFFER
- OP_SNB_3DSTATE_HIER_DEPTH_BUFFER
- OP_SNB_3DSTATE_STENCIL_BUFFER
- OP_SRC_ADD
- OP_SRC_AND
- OP_SRC_CONST
- OP_SRC_POP
- OP_SRC_POPF
- OP_SRC_REG
- OP_SRC_REG_INDIRECT
- OP_ST
- OP_STACK
- OP_STACK_ONEXEC
- OP_START
- OP_STATE
- OP_STATE_BASE_ADDRESS
- OP_STATE_GOOD
- OP_STATE_PERM_ERR
- OP_STATE_PREFETCH
- OP_STATE_SIP
- OP_STATE_TEMP_ERR
- OP_STATUS_DEV
- OP_STATUS_MASK
- OP_STATUS_POWER
- OP_STATUS_SRC
- OP_STB
- OP_STBU
- OP_STD
- OP_STFD
- OP_STFDU
- OP_STFS
- OP_STFSU
- OP_STH
- OP_STHU
- OP_STMW
- OP_STR
- OP_STR_AFU
- OP_STR_CONTROL_ADAPTER
- OP_STR_DONE
- OP_STR_DOWNLOAD_ADAPTER
- OP_STW
- OP_STWU
- OP_SUB
- OP_SUP_DEL_LOGDRV
- OP_SUSPEND
- OP_SW
- OP_SWP
- OP_SWPN
- OP_SYMLINK
- OP_SYSCTL
- OP_TCPCHKSUM
- OP_TCPINIT
- OP_TCPIS
- OP_TCPLCK
- OP_TCPLISW
- OP_TCPLSW
- OP_TCPLW
- OP_TCPSTART
- OP_TCPWRITE
- OP_TEST_STATEID
- OP_TRANSFER_BUF1
- OP_TRANSFER_BUF2
- OP_TRAP
- OP_TRAP_64
- OP_TRUNC
- OP_TSF_RESET
- OP_TTCTRL
- OP_TX
- OP_TXINDEXLE
- OP_TX_FIRST
- OP_TX_STOP
- OP_TX_TO_RX
- OP_TYPE_CLASS1_ALG
- OP_TYPE_CLASS2_ALG
- OP_TYPE_CLUSTER
- OP_TYPE_CORE
- OP_TYPE_DECAP_PROTOCOL
- OP_TYPE_ENCAP_PROTOCOL
- OP_TYPE_MASK
- OP_TYPE_PK
- OP_TYPE_SHIFT
- OP_TYPE_UNI_PROTOCOL
- OP_T_THRES
- OP_ULPI_VIEWPORT
- OP_UMOUNT
- OP_UNEXPORT
- OP_UNLINK
- OP_UNSPEC
- OP_UPDATE
- OP_UPDATE_PE_SDS
- OP_USBCMD
- OP_USBINTR
- OP_USBMODE
- OP_USBSTS
- OP_V
- OP_VEB
- OP_VEB_DNDI_IECP_STATE
- OP_VEB_STATE
- OP_VEB_SURFACE_STATE
- OP_VERIFY
- OP_VER_CCHA_MISC
- OP_VER_CCHA_NUM
- OP_VER_CCHA_REV
- OP_VER_CCHA_VID
- OP_VFLUSH
- OP_VFS_STATE_GIVEN_UP
- OP_VFS_STATE_INPROGR
- OP_VFS_STATE_PURGED
- OP_VFS_STATE_SERVICED
- OP_VFS_STATE_UNKNOWN
- OP_VFS_STATE_WAITING
- OP_VLAN
- OP_VLOAD
- OP_VS
- OP_VSC
- OP_VSET
- OP_VSTORE
- OP_WAIT
- OP_WANT_DELEGATION
- OP_WB
- OP_WB_ZR
- OP_WR
- OP_WRITE
- OP_WRITE_BUFFER1
- OP_WRITE_BUFFER2
- OP_WRITE_MASK
- OP_WRITE_SAME
- OP_WRITE_SECURITY
- OP_WRITE_SECURITY_REVC
- OP_WRITE_TAG
- OP_WR_64
- OP_X86_MODEL_H
- OP_XMM
- OP_XOR
- OP_XY_COLOR_BLT
- OP_XY_FULL_BLT
- OP_XY_FULL_IMMEDIATE_PATTERN_BLT
- OP_XY_FULL_MONO_PATTERN_BLT
- OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT
- OP_XY_FULL_MONO_SRC_BLT
- OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT
- OP_XY_MONO_PAT_BLT
- OP_XY_MONO_PAT_FIXED_BLT
- OP_XY_MONO_SRC_COPY_BLT
- OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT
- OP_XY_PAT_BLT
- OP_XY_PAT_BLT_IMMEDIATE
- OP_XY_PAT_CHROMA_BLT
- OP_XY_PAT_CHROMA_BLT_IMMEDIATE
- OP_XY_PIXEL_BLT
- OP_XY_SCANLINES_BLT
- OP_XY_SETUP_BLT
- OP_XY_SETUP_CLIP_BLT
- OP_XY_SETUP_MONO_PATTERN_SL_BLT
- OP_XY_SRC_COPY_BLT
- OP_XY_SRC_COPY_CHROMA_BLT
- OP_XY_TEXT_BLT
- OP_XY_TEXT_IMMEDIATE_BLT
- OP_ZEROS
- OP_ZP
- OP_ZR
- OQ0_INT_SRC_MSK
- OQ_INT_COAL_CNT
- OQ_INT_COAL_TIME
- OQ_INT_SRC
- OQ_INT_SRC_MSK
- OR
- OR0
- OR1
- OR2
- OR3
- OR32_CONSOLE_BAUD
- OR4
- OR5
- OR51132_H
- OR51132_QAM_FIRMWARE
- OR51132_VSB_FIRMWARE
- OR51211_DEFAULT_FIRMWARE
- OR51211_H
- OR6
- OR7
- ORANGEFS_ALL
- ORANGEFS_APPEND_FL
- ORANGEFS_ATTR_SYS_ALL_NOHINT
- ORANGEFS_ATTR_SYS_ALL_SETABLE
- ORANGEFS_ATTR_SYS_ATIME
- ORANGEFS_ATTR_SYS_ATIME_SET
- ORANGEFS_ATTR_SYS_BLKSIZE
- ORANGEFS_ATTR_SYS_COMMON_ALL
- ORANGEFS_ATTR_SYS_CTIME
- ORANGEFS_ATTR_SYS_DFILE_COUNT
- ORANGEFS_ATTR_SYS_DIRENT_COUNT
- ORANGEFS_ATTR_SYS_GID
- ORANGEFS_ATTR_SYS_LNK_TARGET
- ORANGEFS_ATTR_SYS_MIRROR_COPIES_COUNT
- ORANGEFS_ATTR_SYS_MTIME
- ORANGEFS_ATTR_SYS_MTIME_SET
- ORANGEFS_ATTR_SYS_PERM
- ORANGEFS_ATTR_SYS_SIZE
- ORANGEFS_ATTR_SYS_TYPE
- ORANGEFS_ATTR_SYS_UID
- ORANGEFS_BUFMAP_WAIT_TIMEOUT_SECS
- ORANGEFS_CACHE_CREATE_FLAGS
- ORANGEFS_CLIENT_DEBUG_FILE
- ORANGEFS_DEFAULT_OP_TIMEOUT_SECS
- ORANGEFS_DEFAULT_SLOT_TIMEOUT_SECS
- ORANGEFS_DEVREQ_MAGIC
- ORANGEFS_DEV_CLIENT_MASK
- ORANGEFS_DEV_CLIENT_STRING
- ORANGEFS_DEV_DEBUG
- ORANGEFS_DEV_GET_MAGIC
- ORANGEFS_DEV_GET_MAX_DOWNSIZE
- ORANGEFS_DEV_GET_MAX_UPSIZE
- ORANGEFS_DEV_MAGIC
- ORANGEFS_DEV_MAP
- ORANGEFS_DEV_MAXNR
- ORANGEFS_DEV_REMOUNT_ALL
- ORANGEFS_DEV_UPSTREAM
- ORANGEFS_EADDRNTFD
- ORANGEFS_ECANCEL
- ORANGEFS_EDETAIL
- ORANGEFS_EDEVINIT
- ORANGEFS_EHOSTNTFD
- ORANGEFS_ENORECVR
- ORANGEFS_ENOTPVFS
- ORANGEFS_ERROR_BIT
- ORANGEFS_ERROR_CLASS_BITS
- ORANGEFS_ERROR_NUMBER_BITS
- ORANGEFS_ESECURITY
- ORANGEFS_ETRYAGAIN
- ORANGEFS_FEATURE_READAHEAD
- ORANGEFS_FS_ID_NULL
- ORANGEFS_GETATTR_NEW
- ORANGEFS_GETATTR_SIZE
- ORANGEFS_G_EXECUTE
- ORANGEFS_G_READ
- ORANGEFS_G_SGID
- ORANGEFS_G_WRITE
- ORANGEFS_I
- ORANGEFS_IMMUTABLE_FL
- ORANGEFS_IO_READ
- ORANGEFS_IO_WRITE
- ORANGEFS_ITERATE_END
- ORANGEFS_ITERATE_START
- ORANGEFS_KERNEL_PROTO_VERSION
- ORANGEFS_KMOD_DEBUG_FILE
- ORANGEFS_KMOD_DEBUG_HELP_FILE
- ORANGEFS_KOBJ_ID
- ORANGEFS_LOOKUP_LINK_NO_FOLLOW
- ORANGEFS_MAX_DEBUG_STRING_LEN
- ORANGEFS_MAX_DIRENT_COUNT_READDIR
- ORANGEFS_MAX_SERVER_ADDR_LEN
- ORANGEFS_MAX_XATTR_LISTLEN
- ORANGEFS_MAX_XATTR_NAMELEN
- ORANGEFS_MAX_XATTR_VALUELEN
- ORANGEFS_MINIMUM_USERSPACE_VERSION
- ORANGEFS_MIRROR_FL
- ORANGEFS_NAME_MAX
- ORANGEFS_NOATIME_FL
- ORANGEFS_NON_ERRNO_ERROR_BIT
- ORANGEFS_OPT_INTR
- ORANGEFS_OPT_LOCAL_LOCK
- ORANGEFS_OP_ASYNC
- ORANGEFS_OP_CANCELLATION
- ORANGEFS_OP_INTERRUPTIBLE
- ORANGEFS_OP_NO_MUTEX
- ORANGEFS_OP_PRIORITY
- ORANGEFS_OP_WRITEBACK
- ORANGEFS_O_EXECUTE
- ORANGEFS_O_READ
- ORANGEFS_O_WRITE
- ORANGEFS_PARAM_REQUEST_GET
- ORANGEFS_PARAM_REQUEST_OP_ACACHE_HARD_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_ACACHE_RECLAIM_PERCENTAGE
- ORANGEFS_PARAM_REQUEST_OP_ACACHE_SOFT_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_ACACHE_TIMEOUT_MSECS
- ORANGEFS_PARAM_REQUEST_OP_CAPCACHE_HARD_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_CAPCACHE_RECLAIM_PERCENTAGE
- ORANGEFS_PARAM_REQUEST_OP_CAPCACHE_SOFT_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_CAPCACHE_TIMEOUT_SECS
- ORANGEFS_PARAM_REQUEST_OP_CCACHE_HARD_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_CCACHE_RECLAIM_PERCENTAGE
- ORANGEFS_PARAM_REQUEST_OP_CCACHE_SOFT_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_CCACHE_TIMEOUT_SECS
- ORANGEFS_PARAM_REQUEST_OP_CLIENT_DEBUG
- ORANGEFS_PARAM_REQUEST_OP_NCACHE_HARD_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_NCACHE_RECLAIM_PERCENTAGE
- ORANGEFS_PARAM_REQUEST_OP_NCACHE_SOFT_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_NCACHE_TIMEOUT_MSECS
- ORANGEFS_PARAM_REQUEST_OP_PERF_HISTORY_SIZE
- ORANGEFS_PARAM_REQUEST_OP_PERF_RESET
- ORANGEFS_PARAM_REQUEST_OP_PERF_TIME_INTERVAL_SECS
- ORANGEFS_PARAM_REQUEST_OP_READAHEAD_COUNT
- ORANGEFS_PARAM_REQUEST_OP_READAHEAD_COUNT_SIZE
- ORANGEFS_PARAM_REQUEST_OP_READAHEAD_READCNT
- ORANGEFS_PARAM_REQUEST_OP_READAHEAD_SIZE
- ORANGEFS_PARAM_REQUEST_OP_STATIC_ACACHE_HARD_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_STATIC_ACACHE_RECLAIM_PERCENTAGE
- ORANGEFS_PARAM_REQUEST_OP_STATIC_ACACHE_SOFT_LIMIT
- ORANGEFS_PARAM_REQUEST_OP_STATIC_ACACHE_TIMEOUT_MSECS
- ORANGEFS_PARAM_REQUEST_OP_TWO_MASK_VALUES
- ORANGEFS_PARAM_REQUEST_SET
- ORANGEFS_PERF_COUNT_REQUEST_ACACHE
- ORANGEFS_PERF_COUNT_REQUEST_CAPCACHE
- ORANGEFS_PERF_COUNT_REQUEST_NCACHE
- ORANGEFS_PURGE_RETRY_COUNT
- ORANGEFS_READDIR_DEFAULT_DESC_COUNT
- ORANGEFS_REQDEVICE_NAME
- ORANGEFS_SB
- ORANGEFS_SUPER_MAGIC
- ORANGEFS_TYPE_DATAFILE
- ORANGEFS_TYPE_DIRDATA
- ORANGEFS_TYPE_DIRECTORY
- ORANGEFS_TYPE_INTERNAL
- ORANGEFS_TYPE_METAFILE
- ORANGEFS_TYPE_NONE
- ORANGEFS_TYPE_SYMLINK
- ORANGEFS_U_EXECUTE
- ORANGEFS_U_READ
- ORANGEFS_U_SUID
- ORANGEFS_U_WRITE
- ORANGEFS_VERBOSE
- ORANGEFS_VERSION
- ORANGEFS_VFS_OP_CANCEL
- ORANGEFS_VFS_OP_CREATE
- ORANGEFS_VFS_OP_FEATURES
- ORANGEFS_VFS_OP_FILE_IO
- ORANGEFS_VFS_OP_FSKEY
- ORANGEFS_VFS_OP_FSYNC
- ORANGEFS_VFS_OP_FS_MOUNT
- ORANGEFS_VFS_OP_FS_UMOUNT
- ORANGEFS_VFS_OP_GETATTR
- ORANGEFS_VFS_OP_GETXATTR
- ORANGEFS_VFS_OP_INVALID
- ORANGEFS_VFS_OP_LISTXATTR
- ORANGEFS_VFS_OP_LOOKUP
- ORANGEFS_VFS_OP_MKDIR
- ORANGEFS_VFS_OP_PARAM
- ORANGEFS_VFS_OP_PERF_COUNT
- ORANGEFS_VFS_OP_RA_FLUSH
- ORANGEFS_VFS_OP_READDIR
- ORANGEFS_VFS_OP_READDIRPLUS
- ORANGEFS_VFS_OP_REMOVE
- ORANGEFS_VFS_OP_REMOVEXATTR
- ORANGEFS_VFS_OP_RENAME
- ORANGEFS_VFS_OP_SETATTR
- ORANGEFS_VFS_OP_SETXATTR
- ORANGEFS_VFS_OP_STATFS
- ORANGEFS_VFS_OP_SYMLINK
- ORANGEFS_VFS_OP_TRUNCATE
- ORANGEFS_XATTR_CREATE
- ORANGEFS_XATTR_REPLACE
- ORANGEFS_dev_map_desc
- ORANGEFS_dev_map_desc32
- ORANGEFS_io_type
- ORANGEFS_keyval_pair
- ORANGEFS_khandle_cmp
- ORANGEFS_khandle_from
- ORANGEFS_khandle_to
- ORANGEFS_sys_attr_s
- ORANGEFS_util_translate_mode
- ORB_AREA_SIZE
- ORB_NOTIFY
- ORB_REQUEST_FORMAT
- ORCCR
- ORCNTH
- ORCNTL
- ORCSCB_COMPLETE
- ORCSCB_POST
- ORC_BUSDEVRST
- ORC_CMD_ABORT_SCB
- ORC_CMD_ECHO
- ORC_CMD_GET_BUS_STATUS
- ORC_CMD_GET_NVM
- ORC_CMD_ISSUE_SCB
- ORC_CMD_NOP
- ORC_CMD_SET_NVM
- ORC_CMD_VERSION
- ORC_EBIOSADR0
- ORC_EBIOSADR1
- ORC_EBIOSADR2
- ORC_EBIOSDATA
- ORC_EXECSCSI
- ORC_FWBASEADR
- ORC_GCFG
- ORC_GIMSK
- ORC_GINTS
- ORC_GSTAT
- ORC_HCTRL
- ORC_HDATA
- ORC_HSTUS
- ORC_MAXQUEUE
- ORC_MAXTAGS
- ORC_MAX_SCBS
- ORC_NVRAM
- ORC_OFFSET_SCB
- ORC_PQCNT
- ORC_PQUEUE
- ORC_PRGMCTR0
- ORC_PRGMCTR1
- ORC_REG_BP
- ORC_REG_BP_INDIRECT
- ORC_REG_DI
- ORC_REG_DX
- ORC_REG_MAX
- ORC_REG_PREV_SP
- ORC_REG_R10
- ORC_REG_R13
- ORC_REG_SP
- ORC_REG_SP_INDIRECT
- ORC_REG_UNDEFINED
- ORC_RISCCTL
- ORC_RISCRAM
- ORC_RQUEUE
- ORC_RQUEUECNT
- ORC_SCBBASE0
- ORC_SCBBASE1
- ORC_SCBSIZE
- ORC_TYPE_CALL
- ORC_TYPE_REGS
- ORC_TYPE_REGS_IRET
- ORC_UNWIND_TABLE
- ORDERED
- ORDERED_Q
- ORDERED_QUEUE_TAG
- ORDERED_TAG
- ORDERING
- ORDER_BGRX
- ORDER_CALLEE
- ORDER_CALLER
- ORDER_FALLBACK
- ORDER_RGBX
- ORDER_XBGR
- ORDER_XRGB
- ORDINALTABLE1
- ORDINALTABLE2
- ORD_LIMIT_TO_ORRQ_SLOTS
- OREN36
- OREN538
- ORF
- ORF1
- ORH_HLEN
- ORIENT
- ORIENT_CONF
- ORIENT_DEADZONE
- ORIENT_DIVISOR
- ORIGINAL_NET_BUFLIST
- ORIGINAL_PKTINFO
- ORIGINAL_SAMP_FREQ
- ORIGINAL_TCB
- ORIGIN_CPU
- ORIGIN_CS
- ORIGIN_DIRTYFB
- ORIGIN_FLIP
- ORIGIN_GTT
- ORIGIN_HASH_SIZE
- ORIGIN_MASK
- ORIG_EAX
- ORIG_NAME
- ORIG_RAX
- ORIG_ROOT_DEV
- ORIG_TYPE_NAME
- ORINOCO_ALG_NONE
- ORINOCO_ALG_TKIP
- ORINOCO_ALG_WEP
- ORINOCO_CFG_H
- ORINOCO_INTEN
- ORINOCO_MAX_KEYS
- ORINOCO_MAX_KEY_SIZE
- ORINOCO_MAX_MTU
- ORINOCO_MIN_MTU
- ORINOCO_SEQ_LEN
- ORION5X_BRIDGE_PHYS_BASE
- ORION5X_BRIDGE_VIRT_BASE
- ORION5X_BRIDGE_WINS_BASE
- ORION5X_BRIDGE_WINS_SZ
- ORION5X_CRYPTO_PHYS_BASE
- ORION5X_DDR_PHYS_BASE
- ORION5X_DDR_VIRT_BASE
- ORION5X_DDR_WINS_BASE
- ORION5X_DDR_WINS_SZ
- ORION5X_DEV_BUS_PHYS_BASE
- ORION5X_DEV_BUS_REG
- ORION5X_DEV_BUS_VIRT_BASE
- ORION5X_ETH_PHYS_BASE
- ORION5X_ETH_VIRT_BASE
- ORION5X_NR_IRQS
- ORION5X_PCIE_IO_BUS_BASE
- ORION5X_PCIE_IO_PHYS_BASE
- ORION5X_PCIE_IO_SIZE
- ORION5X_PCIE_MEM_PHYS_BASE
- ORION5X_PCIE_MEM_SIZE
- ORION5X_PCIE_VIRT_BASE
- ORION5X_PCIE_WA_PHYS_BASE
- ORION5X_PCIE_WA_SIZE
- ORION5X_PCIE_WA_VIRT_BASE
- ORION5X_PCI_IO_BUS_BASE
- ORION5X_PCI_IO_PHYS_BASE
- ORION5X_PCI_IO_SIZE
- ORION5X_PCI_MEM_PHYS_BASE
- ORION5X_PCI_MEM_SIZE
- ORION5X_PCI_REG
- ORION5X_PCI_VIRT_BASE
- ORION5X_REGS_PHYS_BASE
- ORION5X_REGS_SIZE
- ORION5X_REGS_VIRT_BASE
- ORION5X_SATA_PHYS_BASE
- ORION5X_SATA_VIRT_BASE
- ORION5X_SRAM_PHYS_BASE
- ORION5X_SRAM_SIZE
- ORION5X_USB0_PHYS_BASE
- ORION5X_USB0_VIRT_BASE
- ORION5X_USB1_PHYS_BASE
- ORION5X_USB1_VIRT_BASE
- ORION5X_XOR_PHYS_BASE
- ORION5X_XOR_VIRT_BASE
- ORION_ACC_FIRST_EXT_BIT
- ORION_ACC_FIRST_EXT_MASK
- ORION_ACC_FIRST_MASK
- ORION_ACC_FIRST_SHIFT
- ORION_ACC_NEXT_EXT_BIT
- ORION_ACC_NEXT_EXT_MASK
- ORION_ACC_NEXT_MASK
- ORION_ACC_NEXT_SHIFT
- ORION_ALE_WR_EXT_BIT
- ORION_ALE_WR_EXT_MASK
- ORION_ALE_WR_MASK
- ORION_ALE_WR_SHIFT
- ORION_BADR_SKEW_SHIFT
- ORION_BLINK_HALF_PERIOD
- ORION_BRIDGE_IRQ_CAUSE
- ORION_BRIDGE_IRQ_MASK
- ORION_DEV_0
- ORION_DEV_1
- ORION_DEV_WIDTH_SHIFT
- ORION_FW_REV
- ORION_IRQS_PER_CHIP
- ORION_IRQ_CAUSE
- ORION_IRQ_ENDP_MASK
- ORION_IRQ_FIQ_MASK
- ORION_IRQ_MASK
- ORION_MBUS_DEVBUS_ATTR
- ORION_MBUS_DEVBUS_BOOT_ATTR
- ORION_MBUS_DEVBUS_BOOT_TARGET
- ORION_MBUS_DEVBUS_TARGET
- ORION_MBUS_PCIE_IO_ATTR
- ORION_MBUS_PCIE_IO_TARGET
- ORION_MBUS_PCIE_MEM_ATTR
- ORION_MBUS_PCIE_MEM_TARGET
- ORION_MBUS_PCIE_WA_ATTR
- ORION_MBUS_PCIE_WA_TARGET
- ORION_MBUS_PCI_IO_ATTR
- ORION_MBUS_PCI_IO_TARGET
- ORION_MBUS_PCI_MEM_ATTR
- ORION_MBUS_PCI_MEM_TARGET
- ORION_MBUS_SRAM_ATTR
- ORION_MBUS_SRAM_TARGET
- ORION_NUM_CHIPSELECTS
- ORION_ONESHOT_MAX
- ORION_ONESHOT_MIN
- ORION_RESERVED
- ORION_RSTOUT_MASK_OFFSET
- ORION_SPI
- ORION_SPI_CLK_PRESCALE_MASK
- ORION_SPI_CS
- ORION_SPI_CS_MASK
- ORION_SPI_CS_SHIFT
- ORION_SPI_DATA_IN_REG
- ORION_SPI_DATA_OUT_REG
- ORION_SPI_IF_8_16_BIT_MODE
- ORION_SPI_IF_CONFIG_REG
- ORION_SPI_IF_CTRL_REG
- ORION_SPI_IF_RXLSBF
- ORION_SPI_IF_TXLSBF
- ORION_SPI_INT_CAUSE_REG
- ORION_SPI_MODE_CPHA
- ORION_SPI_MODE_CPOL
- ORION_SPI_MODE_MASK
- ORION_SPI_TIMING_PARAMS_REG
- ORION_SPI_TMISO_SAMPLE_1
- ORION_SPI_TMISO_SAMPLE_2
- ORION_SPI_TMISO_SAMPLE_MASK
- ORION_SPI_WAIT_RDY_MAX_LOOP
- ORION_TURN_OFF_EXT_BIT
- ORION_TURN_OFF_EXT_MASK
- ORION_TURN_OFF_MASK
- ORION_TURN_OFF_SHIFT
- ORION_VEND_0
- ORION_VEND_1
- ORION_WR_HIGH_EXT_BIT
- ORION_WR_HIGH_EXT_MASK
- ORION_WR_HIGH_MASK
- ORION_WR_HIGH_SHIFT
- ORION_WR_LOW_EXT_BIT
- ORION_WR_LOW_EXT_MASK
- ORION_WR_LOW_MASK
- ORION_WR_LOW_SHIFT
- ORI_LINK
- ORPHAN_CLEANUP_DONE
- ORPHAN_CLEANUP_STARTED
- ORPHAN_DIR_SYSTEM_INODE
- ORPHAN_INO
- ORPHAN_NEED_TRUNCATE
- ORPHAN_NO_NEED_TRUNCATE
- ORPHAN_SCAN_ACTIVE
- ORPHAN_SCAN_INACTIVE
- ORPHAN_SCAN_SCHEDULE_TIMEOUT
- ORRQ_SLOTS_TO_ORD_LIMIT
- ORX_COMM_EXEC_ACTIVE
- ORX_COMM_EXEC_HOLD
- ORX_COMM_EXEC_STOP
- ORX_COMM_EXEC__A
- ORX_COMM_EXEC__M
- ORX_COMM_EXEC__PRE
- ORX_COMM_EXEC__W
- ORX_COMM_INT_MSK__A
- ORX_COMM_INT_MSK__M
- ORX_COMM_INT_MSK__PRE
- ORX_COMM_INT_MSK__W
- ORX_COMM_INT_REQ_CON_REQ__B
- ORX_COMM_INT_REQ_CON_REQ__M
- ORX_COMM_INT_REQ_CON_REQ__PRE
- ORX_COMM_INT_REQ_CON_REQ__W
- ORX_COMM_INT_REQ_DDC_REQ__B
- ORX_COMM_INT_REQ_DDC_REQ__M
- ORX_COMM_INT_REQ_DDC_REQ__PRE
- ORX_COMM_INT_REQ_DDC_REQ__W
- ORX_COMM_INT_REQ_EQU_REQ__B
- ORX_COMM_INT_REQ_EQU_REQ__M
- ORX_COMM_INT_REQ_EQU_REQ__PRE
- ORX_COMM_INT_REQ_EQU_REQ__W
- ORX_COMM_INT_REQ_FWP_REQ__B
- ORX_COMM_INT_REQ_FWP_REQ__M
- ORX_COMM_INT_REQ_FWP_REQ__PRE
- ORX_COMM_INT_REQ_FWP_REQ__W
- ORX_COMM_INT_REQ_NSU_REQ__B
- ORX_COMM_INT_REQ_NSU_REQ__M
- ORX_COMM_INT_REQ_NSU_REQ__PRE
- ORX_COMM_INT_REQ_NSU_REQ__W
- ORX_COMM_INT_REQ__A
- ORX_COMM_INT_REQ__M
- ORX_COMM_INT_REQ__PRE
- ORX_COMM_INT_REQ__W
- ORX_COMM_INT_STA__A
- ORX_COMM_INT_STA__M
- ORX_COMM_INT_STA__PRE
- ORX_COMM_INT_STA__W
- ORX_COMM_INT_STM__A
- ORX_COMM_INT_STM__M
- ORX_COMM_INT_STM__PRE
- ORX_COMM_INT_STM__W
- ORX_COMM_MB__A
- ORX_COMM_MB__M
- ORX_COMM_MB__PRE
- ORX_COMM_MB__W
- ORX_COMM_STATE__A
- ORX_COMM_STATE__M
- ORX_COMM_STATE__PRE
- ORX_COMM_STATE__W
- ORX_CON_COMM_EXEC_ACTIVE
- ORX_CON_COMM_EXEC_HOLD
- ORX_CON_COMM_EXEC_STOP
- ORX_CON_COMM_EXEC__A
- ORX_CON_COMM_EXEC__M
- ORX_CON_COMM_EXEC__PRE
- ORX_CON_COMM_EXEC__W
- ORX_CON_CPH_AMP_R__A
- ORX_CON_CPH_AMP_R__M
- ORX_CON_CPH_AMP_R__PRE
- ORX_CON_CPH_AMP_R__W
- ORX_CON_CPH_APT_W_ATH__B
- ORX_CON_CPH_APT_W_ATH__M
- ORX_CON_CPH_APT_W_ATH__PRE
- ORX_CON_CPH_APT_W_ATH__W
- ORX_CON_CPH_APT_W_PTH__B
- ORX_CON_CPH_APT_W_PTH__M
- ORX_CON_CPH_APT_W_PTH__PRE
- ORX_CON_CPH_APT_W_PTH__W
- ORX_CON_CPH_APT_W__A
- ORX_CON_CPH_APT_W__M
- ORX_CON_CPH_APT_W__PRE
- ORX_CON_CPH_APT_W__W
- ORX_CON_CPH_DLY_W__A
- ORX_CON_CPH_DLY_W__M
- ORX_CON_CPH_DLY_W__PRE
- ORX_CON_CPH_DLY_W__W
- ORX_CON_CPH_FRQ_R__A
- ORX_CON_CPH_FRQ_R__M
- ORX_CON_CPH_FRQ_R__PRE
- ORX_CON_CPH_FRQ_R__W
- ORX_CON_CPH_KDF_W__A
- ORX_CON_CPH_KDF_W__M
- ORX_CON_CPH_KDF_W__PRE
- ORX_CON_CPH_KDF_W__W
- ORX_CON_CPH_KIF_W__A
- ORX_CON_CPH_KIF_W__M
- ORX_CON_CPH_KIF_W__PRE
- ORX_CON_CPH_KIF_W__W
- ORX_CON_CPH_KPF_W__A
- ORX_CON_CPH_KPF_W__M
- ORX_CON_CPH_KPF_W__PRE
- ORX_CON_CPH_KPF_W__W
- ORX_CON_CPH_PHI_R__A
- ORX_CON_CPH_PHI_R__M
- ORX_CON_CPH_PHI_R__PRE
- ORX_CON_CPH_PHI_R__W
- ORX_CON_CPH_TCL_W__A
- ORX_CON_CPH_TCL_W__M
- ORX_CON_CPH_TCL_W__PRE
- ORX_CON_CPH_TCL_W__W
- ORX_CON_CPH_WLC_W_LATC__B
- ORX_CON_CPH_WLC_W_LATC__M
- ORX_CON_CPH_WLC_W_LATC__PRE
- ORX_CON_CPH_WLC_W_LATC__W
- ORX_CON_CPH_WLC_W_WLIM__B
- ORX_CON_CPH_WLC_W_WLIM__M
- ORX_CON_CPH_WLC_W_WLIM__PRE
- ORX_CON_CPH_WLC_W_WLIM__W
- ORX_CON_CPH_WLC_W__A
- ORX_CON_CPH_WLC_W__M
- ORX_CON_CPH_WLC_W__PRE
- ORX_CON_CPH_WLC_W__W
- ORX_CON_CTI_DTI_R__A
- ORX_CON_CTI_DTI_R__M
- ORX_CON_CTI_DTI_R__PRE
- ORX_CON_CTI_DTI_R__W
- ORX_CON_CTI_KDT_W__A
- ORX_CON_CTI_KDT_W__M
- ORX_CON_CTI_KDT_W__PRE
- ORX_CON_CTI_KDT_W__W
- ORX_CON_CTI_KIT_W__A
- ORX_CON_CTI_KIT_W__M
- ORX_CON_CTI_KIT_W__PRE
- ORX_CON_CTI_KIT_W__W
- ORX_CON_CTI_KPT_W__A
- ORX_CON_CTI_KPT_W__M
- ORX_CON_CTI_KPT_W__PRE
- ORX_CON_CTI_KPT_W__W
- ORX_CON_CTI_TAT_W__A
- ORX_CON_CTI_TAT_W__M
- ORX_CON_CTI_TAT_W__PRE
- ORX_CON_CTI_TAT_W__W
- ORX_CON_KRN_AMP_R__A
- ORX_CON_KRN_AMP_R__M
- ORX_CON_KRN_AMP_R__PRE
- ORX_CON_KRN_AMP_R__W
- ORX_CON_KRP_AMP_R__A
- ORX_CON_KRP_AMP_R__M
- ORX_CON_KRP_AMP_R__PRE
- ORX_CON_KRP_AMP_R__W
- ORX_CON_LDT_W_CON_LDT_W__B
- ORX_CON_LDT_W_CON_LDT_W__M
- ORX_CON_LDT_W_CON_LDT_W__PRE
- ORX_CON_LDT_W_CON_LDT_W__W
- ORX_CON_LDT_W__A
- ORX_CON_LDT_W__M
- ORX_CON_LDT_W__PRE
- ORX_CON_LDT_W__W
- ORX_CON_RST_W_CPH__B
- ORX_CON_RST_W_CPH__M
- ORX_CON_RST_W_CPH__PRE
- ORX_CON_RST_W_CPH__W
- ORX_CON_RST_W_CTI__B
- ORX_CON_RST_W_CTI__M
- ORX_CON_RST_W_CTI__PRE
- ORX_CON_RST_W_CTI__W
- ORX_CON_RST_W_KRN__B
- ORX_CON_RST_W_KRN__M
- ORX_CON_RST_W_KRN__PRE
- ORX_CON_RST_W_KRN__W
- ORX_CON_RST_W_KRP__B
- ORX_CON_RST_W_KRP__M
- ORX_CON_RST_W_KRP__PRE
- ORX_CON_RST_W_KRP__W
- ORX_CON_RST_W__A
- ORX_CON_RST_W__M
- ORX_CON_RST_W__PRE
- ORX_CON_RST_W__W
- ORX_DDC_COMM_EXEC_ACTIVE
- ORX_DDC_COMM_EXEC_HOLD
- ORX_DDC_COMM_EXEC_STOP
- ORX_DDC_COMM_EXEC__A
- ORX_DDC_COMM_EXEC__M
- ORX_DDC_COMM_EXEC__PRE
- ORX_DDC_COMM_EXEC__W
- ORX_DDC_COMM_INT_MSK__A
- ORX_DDC_COMM_INT_MSK__M
- ORX_DDC_COMM_INT_MSK__PRE
- ORX_DDC_COMM_INT_MSK__W
- ORX_DDC_COMM_INT_REQ__A
- ORX_DDC_COMM_INT_REQ__M
- ORX_DDC_COMM_INT_REQ__PRE
- ORX_DDC_COMM_INT_REQ__W
- ORX_DDC_COMM_INT_STA__A
- ORX_DDC_COMM_INT_STA__M
- ORX_DDC_COMM_INT_STA__PRE
- ORX_DDC_COMM_INT_STA__W
- ORX_DDC_COMM_INT_STM__A
- ORX_DDC_COMM_INT_STM__M
- ORX_DDC_COMM_INT_STM__PRE
- ORX_DDC_COMM_INT_STM__W
- ORX_DDC_COMM_MB_CTL_MUX__B
- ORX_DDC_COMM_MB_CTL_MUX__M
- ORX_DDC_COMM_MB_CTL_MUX__PRE
- ORX_DDC_COMM_MB_CTL_MUX__W
- ORX_DDC_COMM_MB_CTL_OFF
- ORX_DDC_COMM_MB_CTL_ON
- ORX_DDC_COMM_MB_CTL__B
- ORX_DDC_COMM_MB_CTL__M
- ORX_DDC_COMM_MB_CTL__PRE
- ORX_DDC_COMM_MB_CTL__W
- ORX_DDC_COMM_MB_OBS_MUX__B
- ORX_DDC_COMM_MB_OBS_MUX__M
- ORX_DDC_COMM_MB_OBS_MUX__PRE
- ORX_DDC_COMM_MB_OBS_MUX__W
- ORX_DDC_COMM_MB_OBS_OFF
- ORX_DDC_COMM_MB_OBS_ON
- ORX_DDC_COMM_MB_OBS__B
- ORX_DDC_COMM_MB_OBS__M
- ORX_DDC_COMM_MB_OBS__PRE
- ORX_DDC_COMM_MB_OBS__W
- ORX_DDC_COMM_MB__A
- ORX_DDC_COMM_MB__M
- ORX_DDC_COMM_MB__PRE
- ORX_DDC_COMM_MB__W
- ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING
- ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING
- ORX_DDC_DEC_MAP_W_DIFF_DECOD__B
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- ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE
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- ORX_DDC_DEC_MAP_W_QUADR0__B
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- ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE
- ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT
- ORX_DDC_DEC_MAP_W_QUADR1__B
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- ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE
- ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT
- ORX_DDC_DEC_MAP_W_QUADR2__B
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- ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE
- ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT
- ORX_DDC_DEC_MAP_W_QUADR3__B
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- ORX_DDC_OFO_SET_W_CRXHITIME__B
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- ORX_DDC_OFO_SET_W_CRXINV__M
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- ORX_DDC_OFO_SET_W__A
- ORX_DDC_OFO_SET_W__M
- ORX_DDC_OFO_SET_W__PRE
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- ORX_EQU_COMM_EXEC_ACTIVE
- ORX_EQU_COMM_EXEC_HOLD
- ORX_EQU_COMM_EXEC_STOP
- ORX_EQU_COMM_EXEC__A
- ORX_EQU_COMM_EXEC__M
- ORX_EQU_COMM_EXEC__PRE
- ORX_EQU_COMM_EXEC__W
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- ORX_EQU_COMM_INT_MSK_FBF_READ__W
- ORX_EQU_COMM_INT_MSK_FFF_READ__B
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- ORX_EQU_COMM_INT_MSK_FFF_READ__PRE
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- ORX_EQU_COMM_INT_STA__A
- ORX_EQU_COMM_INT_STA__M
- ORX_EQU_COMM_INT_STA__PRE
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- ORX_EQU_COMM_INT_STM_FBF_READ__B
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- ORX_EQU_COMM_INT_STM_FFF_READ__B
- ORX_EQU_COMM_INT_STM_FFF_READ__M
- ORX_EQU_COMM_INT_STM_FFF_READ__PRE
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- ORX_EQU_COMM_INT_STM__A
- ORX_EQU_COMM_INT_STM__M
- ORX_EQU_COMM_INT_STM__PRE
- ORX_EQU_COMM_INT_STM__W
- ORX_EQU_COMM_MB_CTL_MUX__B
- ORX_EQU_COMM_MB_CTL_MUX__M
- ORX_EQU_COMM_MB_CTL_MUX__PRE
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- ORX_EQU_COMM_MB_CTL_OFF
- ORX_EQU_COMM_MB_CTL_ON
- ORX_EQU_COMM_MB_CTL__B
- ORX_EQU_COMM_MB_CTL__M
- ORX_EQU_COMM_MB_CTL__PRE
- ORX_EQU_COMM_MB_CTL__W
- ORX_EQU_COMM_MB_OBS_MUX__B
- ORX_EQU_COMM_MB_OBS_MUX__M
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- ORX_EQU_COMM_MB_OBS__B
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- ORX_EQU_ERR_ECI_R__A
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- ORX_EQU_ERR_EDQ_R__M
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- ORX_EQU_ERR_SEL_W_CMA_ERROR
- ORX_EQU_ERR_SEL_W_DDA_ERROR
- ORX_EQU_ERR_SEL_W__A
- ORX_EQU_ERR_SEL_W__M
- ORX_EQU_ERR_SEL_W__PRE
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- ORX_EQU_ERR_TIS_W_CMA_SIGNALS
- ORX_EQU_ERR_TIS_W_DDA_SIGNALS
- ORX_EQU_ERR_TIS_W__A
- ORX_EQU_ERR_TIS_W__M
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- ORX_EQU_FBF_C0IM_RW__A
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- ORX_EQU_FBF_C1IM_RW__A
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- ORX_EQU_FBF_C2IM_RW__A
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- ORX_EQU_FBF_C3IM_RW__A
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- ORX_EQU_FBF_C4IM_RW__A
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- ORX_EQU_FBF_C5IM_RW__A
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- ORX_EQU_FBF_LEA_W__A
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- ORX_EQU_FBF_RWT_W__A
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- ORX_EQU_FBF_UPD_W_LMS_UPDATE
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- ORX_EQU_FBF_UPD_W__A
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- ORX_EQU_FFF_C0IM_RW__A
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- ORX_EQU_FFF_C0RE_RW__A
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- ORX_EQU_FFF_C10IM_RW__A
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- ORX_EQU_FFF_C1IM_RW__A
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- ORX_EQU_FFF_C1IM_RW__PRE
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- ORX_EQU_FFF_C1RE_RW__A
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- ORX_EQU_FFF_C1RE_RW__PRE
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- ORX_EQU_FFF_C2IM_RW__A
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- ORX_EQU_FFF_C2RE_RW__A
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- ORX_EQU_FFF_C3IM_RW__A
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- ORX_EQU_FFF_C4IM_RW__A
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- ORX_EQU_FFF_C5IM_RW__A
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- ORX_EQU_FFF_C6IM_RW__A
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- ORX_EQU_FFF_C7IM_RW__A
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- ORX_EQU_FFF_C7RE_RW__A
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- ORX_EQU_FFF_C8IM_RW__A
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- ORX_EQU_FFF_C9IM_RW__A
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- ORX_EQU_FFF_LEA_W__A
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- ORX_EQU_FFF_RWT_W__A
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- ORX_EQU_FFF_SCL_W_SCALE_GAIN_1
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- ORX_EQU_FFF_SCL_W__A
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- ORX_EQU_FFF_UPD_W_LMS_UPDATE
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- ORX_EQU_MER_LDT_W__A
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- ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS
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- ORX_EQU_MXB_SEL_W__A
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- ORX_FWP_AAG_LEN_W__A
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- ORX_FWP_COMM_EXEC_ACTIVE
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- ORX_FWP_PFI_A_W_RATE_1544KBPS
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- ORX_FWP_SRC_DGN_W_MANT__M
- ORX_FWP_SRC_DGN_W_MANT__PRE
- ORX_FWP_SRC_DGN_W_MANT__W
- ORX_FWP_SRC_DGN_W__A
- ORX_FWP_SRC_DGN_W__M
- ORX_FWP_SRC_DGN_W__PRE
- ORX_FWP_SRC_DGN_W__W
- ORX_NSU_AOX_LOFRQ_W__A
- ORX_NSU_AOX_LOFRQ_W__M
- ORX_NSU_AOX_LOFRQ_W__PRE
- ORX_NSU_AOX_LOFRQ_W__W
- ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B
- ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M
- ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE
- ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W
- ORX_NSU_AOX_LOMDE_W_PLL_DIV__B
- ORX_NSU_AOX_LOMDE_W_PLL_DIV__M
- ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE
- ORX_NSU_AOX_LOMDE_W_PLL_DIV__W
- ORX_NSU_AOX_LOMDE_W_RESET_VCO__B
- ORX_NSU_AOX_LOMDE_W_RESET_VCO__M
- ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE
- ORX_NSU_AOX_LOMDE_W_RESET_VCO__W
- ORX_NSU_AOX_LOMDE_W__A
- ORX_NSU_AOX_LOMDE_W__M
- ORX_NSU_AOX_LOMDE_W__PRE
- ORX_NSU_AOX_LOMDE_W__W
- ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB
- ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB
- ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB
- ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB
- ORX_NSU_AOX_LOPOW_W__A
- ORX_NSU_AOX_LOPOW_W__M
- ORX_NSU_AOX_LOPOW_W__PRE
- ORX_NSU_AOX_LOPOW_W__W
- ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYADC__B
- ORX_NSU_AOX_STDBY_W_STDBYADC__M
- ORX_NSU_AOX_STDBY_W_STDBYADC__PRE
- ORX_NSU_AOX_STDBY_W_STDBYADC__W
- ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYAMP__B
- ORX_NSU_AOX_STDBY_W_STDBYAMP__M
- ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE
- ORX_NSU_AOX_STDBY_W_STDBYAMP__W
- ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYBIAS__B
- ORX_NSU_AOX_STDBY_W_STDBYBIAS__M
- ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE
- ORX_NSU_AOX_STDBY_W_STDBYBIAS__W
- ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYFLT__B
- ORX_NSU_AOX_STDBY_W_STDBYFLT__M
- ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE
- ORX_NSU_AOX_STDBY_W_STDBYFLT__W
- ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYPD__B
- ORX_NSU_AOX_STDBY_W_STDBYPD__M
- ORX_NSU_AOX_STDBY_W_STDBYPD__PRE
- ORX_NSU_AOX_STDBY_W_STDBYPD__W
- ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYPLL__B
- ORX_NSU_AOX_STDBY_W_STDBYPLL__M
- ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE
- ORX_NSU_AOX_STDBY_W_STDBYPLL__W
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE
- ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W
- ORX_NSU_AOX_STDBY_W__A
- ORX_NSU_AOX_STDBY_W__M
- ORX_NSU_AOX_STDBY_W__PRE
- ORX_NSU_AOX_STDBY_W__W
- ORX_NSU_AOX_STHR_W__A
- ORX_NSU_AOX_STHR_W__M
- ORX_NSU_AOX_STHR_W__PRE
- ORX_NSU_AOX_STHR_W__W
- ORX_NSU_COMM_EXEC_ACTIVE
- ORX_NSU_COMM_EXEC_HOLD
- ORX_NSU_COMM_EXEC_STOP
- ORX_NSU_COMM_EXEC__A
- ORX_NSU_COMM_EXEC__M
- ORX_NSU_COMM_EXEC__PRE
- ORX_NSU_COMM_EXEC__W
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE
- ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W
- ORX_NSU_NSS_BITSWAP_W__A
- ORX_NSU_NSS_BITSWAP_W__M
- ORX_NSU_NSS_BITSWAP_W__PRE
- ORX_NSU_NSS_BITSWAP_W__W
- ORX_NSU_TUN_BPF_W__A
- ORX_NSU_TUN_BPF_W__M
- ORX_NSU_TUN_BPF_W__PRE
- ORX_NSU_TUN_BPF_W__W
- ORX_NSU_TUN_IFGAIN_W__A
- ORX_NSU_TUN_IFGAIN_W__M
- ORX_NSU_TUN_IFGAIN_W__PRE
- ORX_NSU_TUN_IFGAIN_W__W
- ORX_NSU_TUN_RFGAIN_W__A
- ORX_NSU_TUN_RFGAIN_W__M
- ORX_NSU_TUN_RFGAIN_W__PRE
- ORX_NSU_TUN_RFGAIN_W__W
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE
- ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W
- ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC
- ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC
- ORX_TOP_AIF_CTRL_W_INV_MSB__B
- ORX_TOP_AIF_CTRL_W_INV_MSB__M
- ORX_TOP_AIF_CTRL_W_INV_MSB__PRE
- ORX_TOP_AIF_CTRL_W_INV_MSB__W
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE
- ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W
- ORX_TOP_AIF_CTRL_W__A
- ORX_TOP_AIF_CTRL_W__M
- ORX_TOP_AIF_CTRL_W__PRE
- ORX_TOP_AIF_CTRL_W__W
- ORX_TOP_COMM_EXEC_ACTIVE
- ORX_TOP_COMM_EXEC_HOLD
- ORX_TOP_COMM_EXEC_STOP
- ORX_TOP_COMM_EXEC__A
- ORX_TOP_COMM_EXEC__M
- ORX_TOP_COMM_EXEC__PRE
- ORX_TOP_COMM_EXEC__W
- ORX_TOP_COMM_KEY_KEY
- ORX_TOP_COMM_KEY__A
- ORX_TOP_COMM_KEY__M
- ORX_TOP_COMM_KEY__PRE
- ORX_TOP_COMM_KEY__W
- ORX_TOP_MDE_W_RATE_1544KBPS
- ORX_TOP_MDE_W_RATE_2048KBPS_RO
- ORX_TOP_MDE_W_RATE_2048KBPS_SQRT
- ORX_TOP_MDE_W_RATE_3088KBPS
- ORX_TOP_MDE_W__A
- ORX_TOP_MDE_W__M
- ORX_TOP_MDE_W__PRE
- ORX_TOP_MDE_W__W
- ORX_TST_AOX_TST_W__A
- ORX_TST_AOX_TST_W__M
- ORX_TST_AOX_TST_W__PRE
- ORX_TST_AOX_TST_W__W
- ORX_TST_COMM_EXEC_ACTIVE
- ORX_TST_COMM_EXEC_HOLD
- ORX_TST_COMM_EXEC_STOP
- ORX_TST_COMM_EXEC__A
- ORX_TST_COMM_EXEC__M
- ORX_TST_COMM_EXEC__PRE
- ORX_TST_COMM_EXEC__W
- OR_ACS_DIV1
- OR_ACS_DIV2
- OR_ACS_DIV4
- OR_ACS_MSK
- OR_AM_MSK
- OR_ATM_MSK
- OR_BI
- OR_CSNT_SAM
- OR_EHTR
- OR_FCM_AM
- OR_FCM_AM_SHIFT
- OR_FCM_BCTLD
- OR_FCM_BCTLD_SHIFT
- OR_FCM_CHT
- OR_FCM_CHT_SHIFT
- OR_FCM_CSCT
- OR_FCM_CSCT_SHIFT
- OR_FCM_CST
- OR_FCM_CST_SHIFT
- OR_FCM_EHTR
- OR_FCM_EHTR_SHIFT
- OR_FCM_PGS
- OR_FCM_PGS_SHIFT
- OR_FCM_RST
- OR_FCM_RST_SHIFT
- OR_FCM_SCY
- OR_FCM_SCY_1
- OR_FCM_SCY_2
- OR_FCM_SCY_3
- OR_FCM_SCY_4
- OR_FCM_SCY_5
- OR_FCM_SCY_6
- OR_FCM_SCY_7
- OR_FCM_SCY_SHIFT
- OR_FCM_TRLX
- OR_FCM_TRLX_SHIFT
- OR_G5LA
- OR_G5LS
- OR_GPCM_AM
- OR_GPCM_AM_SHIFT
- OR_LO
- OR_R0_R0
- OR_SCY_0_CLK
- OR_SCY_10_CLK
- OR_SCY_11_CLK
- OR_SCY_12_CLK
- OR_SCY_13_CLK
- OR_SCY_14_CLK
- OR_SCY_15_CLK
- OR_SCY_1_CLK
- OR_SCY_2_CLK
- OR_SCY_3_CLK
- OR_SCY_4_CLK
- OR_SCY_5_CLK
- OR_SCY_6_CLK
- OR_SCY_7_CLK
- OR_SCY_8_CLK
- OR_SCY_9_CLK
- OR_SCY_MSK
- OR_SETA
- OR_TRLX
- OS
- OS2_Info_S
- OS400
- OS400_FORMAT
- OSAK_VERSION
- OSAMP_DEFAULT_DIVISOR
- OSAMP_DIVISORS_MASK
- OSBuildNumber
- OSC
- OSC1TIMER0_RESET
- OSC1TIMER1_RESET
- OSCC
- OSCCLKENB
- OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY
- OSCCLK_PHY_CLKOUT_USB30_PHY
- OSCCON
- OSCCR
- OSCC_OOK
- OSCC_OON
- OSCC_PEN
- OSCDIV
- OSCIN_CLK_NAME
- OSCNPRINTF
- OSCOUT1CLK25MHZ
- OSCR
- OSCR4
- OSC_BANK
- OSC_BUFE_BM
- OSC_CAL_ACK
- OSC_CAL_CNT
- OSC_CAL_REQ
- OSC_CAPABILITIES_MASK_ERROR
- OSC_CLK
- OSC_CLKF
- OSC_CLK_32K_VLD
- OSC_CLK_FORCE_CONTROL
- OSC_CONTROL_DWORD
- OSC_CTRL
- OSC_CTRL_MASK
- OSC_CTRL_OSC_FREQ_12MHZ
- OSC_CTRL_OSC_FREQ_13MHZ
- OSC_CTRL_OSC_FREQ_16_8MHZ
- OSC_CTRL_OSC_FREQ_19_2MHZ
- OSC_CTRL_OSC_FREQ_26MHZ
- OSC_CTRL_OSC_FREQ_38_4MHZ
- OSC_CTRL_OSC_FREQ_48MHZ
- OSC_CTRL_OSC_FREQ_MASK
- OSC_CTRL_OSC_FREQ_SHIFT
- OSC_CTRL_PLL_REF_DIV_1
- OSC_CTRL_PLL_REF_DIV_2
- OSC_CTRL_PLL_REF_DIV_4
- OSC_CTRL_PLL_REF_DIV_MASK
- OSC_CTRL_PLL_REF_DIV_SHIFT
- OSC_CUR_MASK
- OSC_CUR_SHIFT
- OSC_EN
- OSC_FRCDIV_MASK
- OSC_FRCDIV_SHIFT
- OSC_FREQ
- OSC_FREQ_DET
- OSC_FREQ_DET_BUSY
- OSC_FREQ_DET_CNT_MASK
- OSC_FREQ_DET_STATUS
- OSC_FREQ_DET_TRIG
- OSC_HAS_STOPPED
- OSC_INVALID_REVISION_ERROR
- OSC_INVALID_UUID_ERROR
- OSC_NEW_MASK
- OSC_NEW_SHIFT
- OSC_OSCE_BM
- OSC_OSCR_BM
- OSC_PCI_ASPM_SUPPORT
- OSC_PCI_CLOCK_PM_SUPPORT
- OSC_PCI_CONTROL_MASKS
- OSC_PCI_EXPRESS_AER_CONTROL
- OSC_PCI_EXPRESS_CAPABILITY_CONTROL
- OSC_PCI_EXPRESS_LTR_CONTROL
- OSC_PCI_EXPRESS_NATIVE_HP_CONTROL
- OSC_PCI_EXPRESS_PME_CONTROL
- OSC_PCI_EXT_CONFIG_SUPPORT
- OSC_PCI_HPX_TYPE_3_SUPPORT
- OSC_PCI_MSI_SUPPORT
- OSC_PCI_SEGMENT_GROUPS_SUPPORT
- OSC_PCI_SHPC_NATIVE_HP_CONTROL
- OSC_PCI_SUPPORT_MASKS
- OSC_QUERY_DWORD
- OSC_QUERY_ENABLE
- OSC_R2V_BM
- OSC_RBG_BM
- OSC_REFE_BM
- OSC_REF_CYCLE
- OSC_REQUEST_ERROR
- OSC_ROSC_EN
- OSC_RSV
- OSC_SB_APEI_SUPPORT
- OSC_SB_CPCV2_SUPPORT
- OSC_SB_CPC_DIVERSE_HIGH_SUPPORT
- OSC_SB_CPC_SUPPORT
- OSC_SB_HOTPLUG_OST_SUPPORT
- OSC_SB_OSLPI_SUPPORT
- OSC_SB_PAD_SUPPORT
- OSC_SB_PCLPI_SUPPORT
- OSC_SB_PPC_OST_SUPPORT
- OSC_SB_PR3_SUPPORT
- OSC_SRC_SEL
- OSC_SUPPORT_DWORD
- OSC_SWEN
- OSD1_AFBCD_CHROMA_PTR
- OSD1_AFBCD_CONV_CTRL
- OSD1_AFBCD_ENABLE
- OSD1_AFBCD_FRAME_PTR
- OSD1_AFBCD_HDR_PTR
- OSD1_AFBCD_MODE
- OSD1_AFBCD_PIXEL_HSCOPE
- OSD1_AFBCD_PIXEL_VSCOPE
- OSD1_AFBCD_SIZE_IN
- OSD1_AFBCD_STATUS
- OSD1_BLEND_SRC_CTRL
- OSD2_BLEND_SRC_CTRL
- OSD2_HSC_CTRL0
- OSD2_HSC_INI_PAT_CTRL
- OSD2_HSC_INI_PHASE
- OSD2_HSC_PHASE_STEP
- OSD2_SCALE_COEF
- OSD2_SCALE_COEF_IDX
- OSD2_SCI_WH_M1
- OSD2_SCO_H_START_END
- OSD2_SCO_V_START_END
- OSD2_SC_CTRL0
- OSD2_SC_DUMMY_DATA
- OSD2_VSC_CTRL0
- OSD2_VSC_INI_PHASE
- OSD2_VSC_PHASE_STEP
- OSD34_HSC_CTRL0
- OSD34_HSC_INI_PAT_CTRL
- OSD34_HSC_INI_PHASE
- OSD34_HSC_PHASE_STEP
- OSD34_SCALE_COEF
- OSD34_SCALE_COEF_IDX
- OSD34_SCI_WH_M1
- OSD34_SCO_H_START_END
- OSD34_SCO_V_START_END
- OSD34_SC_CTRL0
- OSD34_SC_DUMMY_DATA
- OSD34_VSC_CTRL0
- OSD34_VSC_INI_PHASE
- OSD34_VSC_PHASE_STEP
- OSDEF
- OSDMAP_CLIENT_DATA_COMPAT_VER
- OSDMAP_WRAPPER_COMPAT_VER
- OSDQBusy
- OSDQFull
- OSDQOver
- OSDSR_ABIC_HCOEF
- OSDSR_ABIC_HCOEF0
- OSDSR_ABIC_VCOEF
- OSDSR_ABIC_VCOEF0
- OSDSR_CBIC_HCOEF
- OSDSR_CBIC_HCOEF0
- OSDSR_CBIC_VCOEF
- OSDSR_CBIC_VCOEF0
- OSDSR_CONST_PARA
- OSDSR_CTRL_MODE
- OSDSR_DEMO_WIND_LR
- OSDSR_DEMO_WIND_TB
- OSDSR_FRM_END_STAT
- OSDSR_HVBLEND_TH
- OSDSR_HV_SIZEIN
- OSDSR_INT_BLANK_NUM
- OSDSR_RKE_EXTWIN
- OSDSR_UK_BST_GAIN
- OSDSR_UK_GRAD2DADJA_LIMIT
- OSDSR_UK_GRAD2DADJA_TH_RATE
- OSDSR_UK_GRAD2DDIAG_LIMIT
- OSDSR_UK_GRAD2DDIAG_TH_RATE
- OSDSR_VAR_PARA
- OSDSR_YBIC_HCOEF
- OSDSR_YBIC_HCOEF0
- OSDSR_YBIC_VCOEF
- OSDSR_YBIC_VCOEF0
- OSDSetBlock
- OSDSetColor
- OSDSetPalette
- OSDWIN_OSD0
- OSDWIN_OSD1
- OSD_0_VID_8
- OSD_1_VID_7
- OSD_2_VID_6
- OSD_3_VID_5
- OSD_4_VID_4
- OSD_5_VID_3
- OSD_6_VID_2
- OSD_8_VID_0
- OSD_AUX_CHN
- OSD_BASE
- OSD_BASEPX
- OSD_BASEPX_BPX
- OSD_BASEPY
- OSD_BASEPY_BPY
- OSD_BITMAP1
- OSD_BITMAP1HR
- OSD_BITMAP2
- OSD_BITMAP2HR
- OSD_BITMAP4
- OSD_BITMAP4HR
- OSD_BITMAP8
- OSD_BITMAP8HR
- OSD_BLEND_PATH_SEL_ENABLE
- OSD_BLEND_POSTBLD_SRC_OSD1
- OSD_BLEND_POSTBLD_SRC_OSD2
- OSD_BLEND_POSTBLD_SRC_VD1
- OSD_BLEND_POSTBLD_SRC_VD2
- OSD_BLK0_ENABLE
- OSD_BLK_MODE_16
- OSD_BLK_MODE_24
- OSD_BLK_MODE_32
- OSD_BLK_MODE_422
- OSD_CANVAS_SEL
- OSD_CLUTRAMCR
- OSD_CLUTRAMCR_CADDR
- OSD_CLUTRAMCR_CADDR_SHIFT
- OSD_CLUTRAMCR_CR
- OSD_CLUTRAMCR_CR_SHIFT
- OSD_CLUTRAMYCB
- OSD_CLUTRAMYCB_CB
- OSD_CLUTRAMYCB_CB_SHIFT
- OSD_CLUTRAMYCB_Y
- OSD_CLUTRAMYCB_Y_SHIFT
- OSD_COLOR1
- OSD_COLOR2
- OSD_COLOR3
- OSD_COLOR4
- OSD_COLOR5
- OSD_COLOR6
- OSD_COLOR7
- OSD_COLOR8
- OSD_COLOR_MATRIX_16_RGB565
- OSD_COLOR_MATRIX_16_RGB655
- OSD_COLOR_MATRIX_24_RGB
- OSD_COLOR_MATRIX_32_ABGR
- OSD_COLOR_MATRIX_32_ARGB
- OSD_COLOR_MATRIX_32_BGRA
- OSD_COLOR_MATRIX_32_RGBA
- OSD_CTRL0
- OSD_CTRL0_GL0_EN
- OSD_CTRL0_GL0_SEL
- OSD_CTRL0_GL1_EN
- OSD_CTRL0_GL1_SEL
- OSD_CTRL0_VL0_EN
- OSD_CTRL0_VL0_SEL
- OSD_CTRL0_VL1_EN
- OSD_CTRL0_VL1_SEL
- OSD_CTRL0_VL2_EN
- OSD_CTRL0_VL2_SEL
- OSD_CURSOR
- OSD_CURXL
- OSD_CURXL_RCSW
- OSD_CURXP
- OSD_CURXP_RCSX
- OSD_CURYL
- OSD_CURYL_RCSH
- OSD_CURYP
- OSD_CURYP_RCSY
- OSD_Clear
- OSD_Close
- OSD_Command
- OSD_DITHER_CTRL0
- OSD_ENABLE
- OSD_ENDIANNESS_BE
- OSD_ENDIANNESS_LE
- OSD_EOTF_LUT_SIZE
- OSD_EXTMODE
- OSD_EXTMODE_ATNOSD0EN
- OSD_EXTMODE_ATNOSD1EN
- OSD_EXTMODE_EXPFILHEN
- OSD_EXTMODE_EXPFILVEN
- OSD_EXTMODE_EXPMDSEL
- OSD_EXTMODE_OSD0BLDCHR
- OSD_EXTMODE_OSD1BLDCHR
- OSD_EXTMODE_OSDHRSZ15
- OSD_EXTMODE_SCRNHEXP
- OSD_EXTMODE_SCRNHEXP_SHIFT
- OSD_EXTMODE_SCRNVEXP
- OSD_EXTMODE_VIDHRSZ15
- OSD_EXTMODE_ZMFILV0HEN
- OSD_EXTMODE_ZMFILV0VEN
- OSD_EXTMODE_ZMFILV1HEN
- OSD_EXTMODE_ZMFILV1VEN
- OSD_Fill
- OSD_FillBlock
- OSD_FillRow
- OSD_GET_CAPABILITY
- OSD_GLOBAL_ALPHA_SHIFT
- OSD_GetPixel
- OSD_Hide
- OSD_INTERLACE_ENABLED
- OSD_INTERLACE_EVEN
- OSD_INTERLACE_ODD
- OSD_INT_AUX_UPT
- OSD_INT_BUS_ERR
- OSD_INT_CFG_ERR
- OSD_INT_CLRSTA
- OSD_INT_ENABLE
- OSD_INT_ERROR
- OSD_INT_GL0_LBW
- OSD_INT_GL1_LBW
- OSD_INT_MAIN_UPT
- OSD_INT_MSK
- OSD_INT_STA
- OSD_INT_VL0_LBW
- OSD_INT_VL1_LBW
- OSD_INT_VL2_LBW
- OSD_Line
- OSD_MAIN_CHN
- OSD_MISCCTL
- OSD_MISCCTL_BLDSEL
- OSD_MISCCTL_BMAPT
- OSD_MISCCTL_CPBSY
- OSD_MISCCTL_DM365M
- OSD_MISCCTL_DMANG
- OSD_MISCCTL_PPRV
- OSD_MISCCTL_PPSW
- OSD_MISCCTL_RGBEN
- OSD_MISCCTL_RGBWIN
- OSD_MISCCTL_RSEL
- OSD_MISCCTL_S420D
- OSD_MISCCTL_TMON
- OSD_MODE
- OSD_MODE_BCLUT
- OSD_MODE_CABG
- OSD_MODE_CABG_SHIFT
- OSD_MODE_CS
- OSD_MODE_EF
- OSD_MODE_FSINV
- OSD_MODE_OHRSZ
- OSD_MODE_OVRSZ
- OSD_MODE_VHRSZ
- OSD_MODE_VVRSZ
- OSD_MoveWindow
- OSD_OETF_LUT_SIZE
- OSD_OPREPLY_FRONT_LEN
- OSD_OSDATRMD
- OSD_OSDATRMD_BLNK
- OSD_OSDATRMD_BLNKINT
- OSD_OSDATRMD_BLNKINT_SHIFT
- OSD_OSDATRMD_OASW
- OSD_OSDATRMD_OFFA
- OSD_OSDATRMD_OHZA
- OSD_OSDATRMD_OHZA_SHIFT
- OSD_OSDATRMD_OVZA
- OSD_OSDATRMD_OVZA_SHIFT
- OSD_OSDWIN0ADL
- OSD_OSDWIN0ADL_O0AL
- OSD_OSDWIN0ADR
- OSD_OSDWIN0MD
- OSD_OSDWIN0MD_ATN0E
- OSD_OSDWIN0MD_BLND0
- OSD_OSDWIN0MD_BLND0_SHIFT
- OSD_OSDWIN0MD_BMP0MD
- OSD_OSDWIN0MD_BMP0MD_SHIFT
- OSD_OSDWIN0MD_BMW0
- OSD_OSDWIN0MD_BMW0_SHIFT
- OSD_OSDWIN0MD_CLUTS0
- OSD_OSDWIN0MD_OACT0
- OSD_OSDWIN0MD_OFF0
- OSD_OSDWIN0MD_OHZ0
- OSD_OSDWIN0MD_OHZ0_SHIFT
- OSD_OSDWIN0MD_OVZ0
- OSD_OSDWIN0MD_OVZ0_SHIFT
- OSD_OSDWIN0MD_RGB0E
- OSD_OSDWIN0MD_TE0
- OSD_OSDWIN0OFST
- OSD_OSDWIN0OFST_O0AH
- OSD_OSDWIN0OFST_O0LO
- OSD_OSDWIN0XL
- OSD_OSDWIN0XL_W0W
- OSD_OSDWIN0XP
- OSD_OSDWIN0XP_W0X
- OSD_OSDWIN0YL
- OSD_OSDWIN0YL_W0H
- OSD_OSDWIN0YP
- OSD_OSDWIN0YP_W0Y
- OSD_OSDWIN1ADL
- OSD_OSDWIN1ADL_O1AL
- OSD_OSDWIN1ADR
- OSD_OSDWIN1MD
- OSD_OSDWIN1MD_ATN1E
- OSD_OSDWIN1MD_BLND1
- OSD_OSDWIN1MD_BLND1_SHIFT
- OSD_OSDWIN1MD_BMP1MD
- OSD_OSDWIN1MD_BMP1MD_SHIFT
- OSD_OSDWIN1MD_BMW1
- OSD_OSDWIN1MD_BMW1_SHIFT
- OSD_OSDWIN1MD_CLUTS1
- OSD_OSDWIN1MD_OACT1
- OSD_OSDWIN1MD_OASW
- OSD_OSDWIN1MD_OFF1
- OSD_OSDWIN1MD_OHZ1
- OSD_OSDWIN1MD_OHZ1_SHIFT
- OSD_OSDWIN1MD_OVZ1
- OSD_OSDWIN1MD_OVZ1_SHIFT
- OSD_OSDWIN1MD_RGB1E
- OSD_OSDWIN1MD_TE1
- OSD_OSDWIN1OFST
- OSD_OSDWIN1OFST_O1AH
- OSD_OSDWIN1OFST_O1LO
- OSD_OSDWIN1XL
- OSD_OSDWIN1XL_W1W
- OSD_OSDWIN1XP
- OSD_OSDWIN1XP_W1X
- OSD_OSDWIN1YL
- OSD_OSDWIN1YL_W1H
- OSD_OSDWIN1YP
- OSD_OSDWIN1YP_W1Y
- OSD_OSDWINADH
- OSD_OSDWINADH_O0AH
- OSD_OSDWINADH_O0AH_SHIFT
- OSD_OSDWINADH_O1AH
- OSD_OSDWINADH_O1AH_SHIFT
- OSD_OUTPUT_COLOR_RGB
- OSD_OUTPUT_COLOR_YUV
- OSD_Open
- OSD_OpenRaw
- OSD_PATH_MISC_CTRL
- OSD_PPVWIN0ADR
- OSD_Query
- OSD_RECTCUR
- OSD_RECTCUR_CLUTSR
- OSD_RECTCUR_RCACT
- OSD_RECTCUR_RCAD
- OSD_RECTCUR_RCAD_SHIFT
- OSD_RECTCUR_RCHW
- OSD_RECTCUR_RCHW_SHIFT
- OSD_RECTCUR_RCVW
- OSD_RECTCUR_RCVW_SHIFT
- OSD_REPLACE_EN
- OSD_REPLACE_SHIFT
- OSD_RST_CLR
- OSD_SEND_CMD
- OSD_SRCADD_ADD_SFT
- OSD_SRCADD_OFSET_SFT
- OSD_SRC_ADDR_HIGH4
- OSD_SRC_ADDR_HIGH7
- OSD_STRIDE
- OSD_SetBlock
- OSD_SetColor
- OSD_SetPalette
- OSD_SetPixel
- OSD_SetRow
- OSD_SetTrans
- OSD_SetWindow
- OSD_Show
- OSD_TEXT_MAX
- OSD_TRANSPBMPIDX
- OSD_TRANSPBMPIDX_BMP0
- OSD_TRANSPBMPIDX_BMP0_SHIFT
- OSD_TRANSPBMPIDX_BMP1
- OSD_TRANSPBMPIDX_BMP1_SHIFT
- OSD_TRANSPVAL
- OSD_TRANSPVALL
- OSD_TRANSPVALL_RGBL
- OSD_TRANSPVALU
- OSD_TRANSPVALU_RGBU
- OSD_TRANSPVALU_RGBU_SHIFT
- OSD_TRANSPVALU_Y
- OSD_TRANSPVALU_Y_SHIFT
- OSD_TRANSPVAL_RGBTRANS
- OSD_Test
- OSD_Text
- OSD_VBNDRY
- OSD_VIDEODSIZE
- OSD_VIDEOHSIZE
- OSD_VIDEONSIZE
- OSD_VIDEOQSIZE
- OSD_VIDEOTDSIZE
- OSD_VIDEOTHSIZE
- OSD_VIDEOTQSIZE
- OSD_VIDEOTSIZE
- OSD_VIDWIN0ADL
- OSD_VIDWIN0ADL_V0AL
- OSD_VIDWIN0ADR
- OSD_VIDWIN0OFST
- OSD_VIDWIN0OFST_V0AH
- OSD_VIDWIN0OFST_V0LO
- OSD_VIDWIN0XL
- OSD_VIDWIN0XL_V0W
- OSD_VIDWIN0XP
- OSD_VIDWIN0XP_V0X
- OSD_VIDWIN0YL
- OSD_VIDWIN0YL_V0H
- OSD_VIDWIN0YP
- OSD_VIDWIN0YP_V0Y
- OSD_VIDWIN1ADL
- OSD_VIDWIN1ADL_V1AL
- OSD_VIDWIN1ADR
- OSD_VIDWIN1OFST
- OSD_VIDWIN1OFST_V1AH
- OSD_VIDWIN1OFST_V1LO
- OSD_VIDWIN1XL
- OSD_VIDWIN1XL_V1W
- OSD_VIDWIN1XP
- OSD_VIDWIN1XP_V1X
- OSD_VIDWIN1YL
- OSD_VIDWIN1YL_V1H
- OSD_VIDWIN1YP
- OSD_VIDWIN1YP_V1Y
- OSD_VIDWINADH
- OSD_VIDWINADH_V0AH
- OSD_VIDWINADH_V0AH_SHIFT
- OSD_VIDWINADH_V1AH
- OSD_VIDWINADH_V1AH_SHIFT
- OSD_VIDWINMD
- OSD_VIDWINMD_ACT0
- OSD_VIDWINMD_ACT1
- OSD_VIDWINMD_V0EFC
- OSD_VIDWINMD_V1EFC
- OSD_VIDWINMD_VFF0
- OSD_VIDWINMD_VFF1
- OSD_VIDWINMD_VFINV
- OSD_VIDWINMD_VHZ0
- OSD_VIDWINMD_VHZ0_SHIFT
- OSD_VIDWINMD_VHZ1
- OSD_VIDWINMD_VHZ1_SHIFT
- OSD_VIDWINMD_VVZ0
- OSD_VIDWINMD_VVZ0_SHIFT
- OSD_VIDWINMD_VVZ1
- OSD_VIDWINMD_VVZ1_SHIFT
- OSD_VL0_OFFSET
- OSD_VL_OFFSET
- OSD_W0BMP01
- OSD_W0BMP23
- OSD_W0BMP45
- OSD_W0BMP67
- OSD_W0BMP89
- OSD_W0BMPAB
- OSD_W0BMPCD
- OSD_W0BMPEF
- OSD_W1BMP01
- OSD_W1BMP23
- OSD_W1BMP45
- OSD_W1BMP67
- OSD_W1BMP89
- OSD_W1BMPAB
- OSD_W1BMPCD
- OSD_W1BMPEF
- OSD_WINADL_MASK
- OSD_WINOFST_AH_SHIFT
- OSD_WINOFST_MASK
- OSD_WRITETOOBIG
- OSD_YCRCB422
- OSD_YCRCB444
- OSD_YCRCB444HR
- OSFOPT_ECHO
- OSFOPT_ECHOREPLY
- OSFOPT_EMPTY
- OSFOPT_EOL
- OSFOPT_MSS
- OSFOPT_NOP
- OSFOPT_POCP
- OSFOPT_POSP
- OSFOPT_SACK
- OSFOPT_SACKP
- OSFOPT_TS
- OSFOPT_WSO
- OSF_ATTR_FINGER
- OSF_ATTR_MAX
- OSF_ATTR_UNSPEC
- OSF_MSG_ADD
- OSF_MSG_MAX
- OSF_MSG_REMOVE
- OSF_WSS_MAX
- OSF_WSS_MODULO
- OSF_WSS_MSS
- OSF_WSS_MTU
- OSF_WSS_PLAIN
- OSIFI2C_READ
- OSIFI2C_SET_BIT_RATE
- OSIFI2C_STATUS
- OSIFI2C_STOP
- OSIFI2C_WRITE
- OSIOCGNETADDR
- OSIOCSNETADDR
- OSIRIS_CTRL0_BOOT_INT
- OSIRIS_CTRL0_FIX8
- OSIRIS_CTRL0_NANDSEL
- OSIRIS_CTRL0_PCMCIA
- OSIRIS_CTRL0_PCMCIA_nIOIS16
- OSIRIS_CTRL0_PCMCIA_nWAIT
- OSIRIS_CTRL1_FIX8
- OSIRIS_GPIO_DVS
- OSIRIS_ID_REVMASK
- OSIRIS_IOADDR
- OSIRIS_PA_CPLD
- OSIRIS_PA_CTRL0
- OSIRIS_PA_CTRL1
- OSIRIS_PA_CTRL2
- OSIRIS_PA_CTRL3
- OSIRIS_PA_IDREG
- OSIRIS_VA_CTRL0
- OSIRIS_VA_CTRL1
- OSIRIS_VA_CTRL2
- OSIRIS_VA_CTRL3
- OSIRIS_VA_IDREG
- OSITECH_AUI_CTL
- OSITECH_AUI_PWR
- OSITECH_ISR
- OSITECH_PWRDOWN
- OSITECH_RESET
- OSITECH_RESET_ISR
- OSI_AUI_PWR
- OSI_LAN_PWRDOWN
- OSI_LAN_RESET
- OSI_MODEM_PWRDOWN
- OSI_MODEM_RESET
- OSI_SC_MAGIC_R3
- OSI_SC_MAGIC_R4
- OSI_STRING_ENTRIES_MAX
- OSI_STRING_LENGTH_MAX
- OSK_TPS_GPIO_BASE
- OSK_TPS_GPIO_DSP_PWR_EN
- OSK_TPS_GPIO_LAN_RESET
- OSK_TPS_GPIO_LED_D2
- OSK_TPS_GPIO_LED_D3
- OSK_TPS_GPIO_LED_D9
- OSK_TPS_GPIO_USB_PWR_EN
- OSL_DEBUGGER_EXEC_THREAD
- OSL_DEBUGGER_MAIN_THREAD
- OSL_EC_BURST_HANDLER
- OSL_EC_POLL_HANDLER
- OSL_GLOBAL_LOCK_HANDLER
- OSL_GPE_HANDLER
- OSL_NOTIFY_HANDLER
- OSMR0
- OSMR1
- OSMR2
- OSMR3
- OSMR4
- OSMajorVersion
- OSMinorVersion
- OSName
- OSQ_LOCK_UNLOCKED
- OSQ_UNLOCKED_VAL
- OSSR
- OSSR_M
- OSSR_M0
- OSSR_M1
- OSSR_M2
- OSSR_M3
- OSSSYS_BASE__INST0_SEG0
- OSSSYS_BASE__INST0_SEG1
- OSSSYS_BASE__INST0_SEG2
- OSSSYS_BASE__INST0_SEG3
- OSSSYS_BASE__INST0_SEG4
- OSSSYS_BASE__INST0_SEG5
- OSSSYS_BASE__INST1_SEG0
- OSSSYS_BASE__INST1_SEG1
- OSSSYS_BASE__INST1_SEG2
- OSSSYS_BASE__INST1_SEG3
- OSSSYS_BASE__INST1_SEG4
- OSSSYS_BASE__INST1_SEG5
- OSSSYS_BASE__INST2_SEG0
- OSSSYS_BASE__INST2_SEG1
- OSSSYS_BASE__INST2_SEG2
- OSSSYS_BASE__INST2_SEG3
- OSSSYS_BASE__INST2_SEG4
- OSSSYS_BASE__INST2_SEG5
- OSSSYS_BASE__INST3_SEG0
- OSSSYS_BASE__INST3_SEG1
- OSSSYS_BASE__INST3_SEG2
- OSSSYS_BASE__INST3_SEG3
- OSSSYS_BASE__INST3_SEG4
- OSSSYS_BASE__INST3_SEG5
- OSSSYS_BASE__INST4_SEG0
- OSSSYS_BASE__INST4_SEG1
- OSSSYS_BASE__INST4_SEG2
- OSSSYS_BASE__INST4_SEG3
- OSSSYS_BASE__INST4_SEG4
- OSSSYS_BASE__INST4_SEG5
- OSSSYS_BASE__INST5_SEG0
- OSSSYS_BASE__INST5_SEG1
- OSSSYS_BASE__INST5_SEG2
- OSSSYS_BASE__INST5_SEG3
- OSSSYS_BASE__INST5_SEG4
- OSSSYS_BASE__INST5_SEG5
- OSSSYS_BASE__INST6_SEG0
- OSSSYS_BASE__INST6_SEG1
- OSSSYS_BASE__INST6_SEG2
- OSSSYS_BASE__INST6_SEG3
- OSSSYS_BASE__INST6_SEG4
- OSSSYS_BASE__INST6_SEG5
- OSSSYS_BASE__INST7_SEG0
- OSSSYS_BASE__INST7_SEG1
- OSSSYS_BASE__INST7_SEG2
- OSSSYS_BASE__INST7_SEG3
- OSSSYS_BASE__INST7_SEG4
- OSSSYS_BASE__INST7_SEG5
- OSSSYS_HWID
- OSSSYS_HWIP
- OSST_MAJOR
- OSS_1_0_D_H
- OSS_1_0_SH_MASK_H
- OSS_2_0_D_H
- OSS_2_0_SH_MASK_H
- OSS_2_4_D_H
- OSS_2_4_ENUM_H
- OSS_2_4_SH_MASK_H
- OSS_3_0_1_D_H
- OSS_3_0_1_ENUM_H
- OSS_3_0_1_SH_MASK_H
- OSS_3_0_D_H
- OSS_3_0_ENUM_H
- OSS_3_0_SH_MASK_H
- OSS_60HZ
- OSS_ALSAEMULVER
- OSS_BASE
- OSS_DEBUG
- OSS_GETVERSION
- OSS_IOPISM
- OSS_IOPSCC
- OSS_IP_60HZ
- OSS_IP_IOPISM
- OSS_IP_IOPSCC
- OSS_IP_NUBUS
- OSS_IP_NUBUS0
- OSS_IP_NUBUS1
- OSS_IP_NUBUS2
- OSS_IP_NUBUS3
- OSS_IP_NUBUS4
- OSS_IP_NUBUS5
- OSS_IP_PARITY
- OSS_IP_SCSI
- OSS_IP_SOUND
- OSS_IP_UNUSED1
- OSS_IP_UNUSED2
- OSS_IP_UNUSED3
- OSS_IP_VIA1
- OSS_IRQLEV_IOPISM
- OSS_IRQLEV_IOPSCC
- OSS_IRQLEV_NUBUS
- OSS_IRQLEV_SCSI
- OSS_IRQLEV_VIA1
- OSS_NUBUS0
- OSS_NUBUS1
- OSS_NUBUS2
- OSS_NUBUS3
- OSS_NUBUS4
- OSS_NUBUS5
- OSS_NUM_SOURCES
- OSS_PARITY
- OSS_POWEROFF
- OSS_SCSI
- OSS_SOUND
- OSS_UNUSED1
- OSS_UNUSED2
- OSS_UNUSED3
- OSS_VIA1
- OSTAT_FLT
- OSTAT_INIT
- OSTAT_OFF
- OSTAT_ON
- OSTAT_RUN
- OSTAT_SHUT
- OSTAT_TEST
- OSTAT_WARN
- OSTM_CMP
- OSTM_CNT
- OSTM_CTL
- OSTM_TE
- OSTM_TS
- OSTM_TT
- OSTYPE_LINUX
- OST_OIER
- OST_OIER_E0
- OST_OIER_E1
- OST_OIER_E2
- OST_OIER_E3
- OST_OSCR
- OST_OSMR0
- OST_OSMR1
- OST_OSMR2
- OST_OSMR3
- OST_OSSR
- OST_OSSR_M0
- OST_OSSR_M1
- OST_OSSR_M2
- OST_OSSR_M3
- OST_OWER
- OST_OWER_WME
- OST_PWMDCCR_FDCYCLE
- OST_PWM_DCCR
- OST_PWM_PCR
- OST_PWM_PWCR
- OSVersion
- OS_ACC_F_OK
- OS_ACC_RW_OK
- OS_ACC_R_OK
- OS_ACC_W_OK
- OS_ACC_X_OK
- OS_AIX_UNIX
- OS_AREA_DB_KEY_ANY
- OS_AREA_DB_KEY_MAX
- OS_AREA_DB_KEY_NONE
- OS_AREA_DB_KEY_RTC_DIFF
- OS_AREA_DB_KEY_VIDEO_MODE
- OS_AREA_DB_MAGIC_NUM
- OS_AREA_DB_OWNER_ANY
- OS_AREA_DB_OWNER_LINUX
- OS_AREA_DB_OWNER_MAX
- OS_AREA_DB_OWNER_NONE
- OS_AREA_DB_OWNER_PETITBOOT
- OS_AREA_DB_OWNER_PROTOTYPE
- OS_AREA_HEADER_MAGIC_NUM
- OS_AREA_SEGMENT_SIZE
- OS_ATT_UNIX
- OS_BANYAN
- OS_BASE_ID
- OS_BSDI_UNIX
- OS_CODE
- OS_DELAY
- OS_DGUX_UNIX
- OS_DOS
- OS_DRIVER_STATE_ACTIVE
- OS_DRIVER_STATE_DISABLED
- OS_DRIVER_STATE_LOADING
- OS_DRIVER_STATE_NOT_LOADED
- OS_FREE_BSD
- OS_GEN_UNIX
- OS_ID_HPRT
- OS_ID_HPUX
- OS_ID_LINUX
- OS_ID_MPEXL
- OS_ID_NONE
- OS_ID_NOVEL
- OS_ID_OSF
- OS_INFO_MAGIC
- OS_INFO_REIPL_BLOCK
- OS_INFO_VERSION_MAJOR
- OS_INFO_VERSION_MINOR
- OS_INFO_VMCOREINFO
- OS_INT_UNIX
- OS_LIB_PATH
- OS_LINUX
- OS_MAC_OS
- OS_MAILBOX_RETRY_COUNT
- OS_NEXTSTEP
- OS_NW286
- OS_NW386
- OS_NW4x
- OS_OLIVETTI_UNIX
- OS_OS22x
- OS_OS2L
- OS_OS2M
- OS_OTHER
- OS_PLAN9
- OS_QNX
- OS_SCO_UNIX
- OS_SENDMSG_MAX_FDS
- OS_SINIX_N
- OS_SOLARIS
- OS_STRING_IDX
- OS_STRING_QW_SIGN_LEN
- OS_SUPPORT_FSCR
- OS_SUPPORT_NONE
- OS_TSX
- OS_TYPE_BLOCKDEV
- OS_TYPE_CHARDEV
- OS_TYPE_DIR
- OS_TYPE_FIFO
- OS_TYPE_FILE
- OS_TYPE_LINUX
- OS_TYPE_SOCK
- OS_TYPE_SYMLINK
- OS_TYPE_UNKNOWN
- OS_UNIXWARE
- OS_WINDOWS
- OS_WINDOWS_95
- OS_WINDOWS_NT
- OTAPDLY
- OTAPDLYENA_MASK
- OTAPDLYENA_SHIFT
- OTAPDLYSEL_MASK
- OTAPDLYSEL_SHIFT
- OTAPDLY_EN
- OTAP_DELAY
- OTAR02
- OTAR13
- OTDD_F
- OTDD_S
- OTDD_V
- OTFPPU_RSZ_DATA_SOURCE
- OTF_INPUT_COMMAND_DISABLE
- OTF_INPUT_COMMAND_ENABLE
- OTF_INPUT_ERROR_NONE
- OTF_INPUT_FORMAT_BAYER
- OTF_INPUT_FORMAT_BAYER_DMA
- OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER
- OTF_INPUT_FORMAT_YUV420
- OTF_INPUT_FORMAT_YUV422
- OTF_INPUT_FORMAT_YUV444
- OTF_INPUT_ORDER_BAYER_GR_BG
- OTF_OUTPUT_COMMAND_DISABLE
- OTF_OUTPUT_COMMAND_ENABLE
- OTF_OUTPUT_CROP_DISABLE
- OTF_OUTPUT_CROP_ENABLE
- OTF_OUTPUT_ERROR_NONE
- OTF_OUTPUT_FORMAT_RGB
- OTF_OUTPUT_FORMAT_YUV420
- OTF_OUTPUT_FORMAT_YUV422
- OTF_OUTPUT_FORMAT_YUV444
- OTF_OUTPUT_ORDER_BAYER_GR_BG
- OTG
- OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG0_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG0_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG0_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG0_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG0_OTG_STATUS__OTG_H_BLANK_MASK
- OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG0_OTG_STATUS__OTG_V_BLANK_MASK
- OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG0_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG0_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG0_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG0_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK
- OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK
- OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT
- OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK
- OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_ERROR_COUNT__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_FIFO_ERROR__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT
- OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK
- OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT
- OTG1_DM_PULLDOWN
- OTG1_DM_PULLUP
- OTG1_DP_PULLDOWN
- OTG1_DP_PULLUP
- OTG1_ID_PULLDOWN
- OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG1_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG1_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG1_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG1_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG1_OTG_STATUS__OTG_H_BLANK_MASK
- OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG1_OTG_STATUS__OTG_V_BLANK_MASK
- OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG1_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG1_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG1_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG1_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK
- OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK
- OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT
- OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK
- OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_ERROR_COUNT__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_FIFO_ERROR__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT
- OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK
- OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT
- OTG1_VBUS_CHRG
- OTG1_VBUS_DISCHRG
- OTG1_VBUS_DRV
- OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG2_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG2_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG2_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG2_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG2_OTG_STATUS__OTG_H_BLANK_MASK
- OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG2_OTG_STATUS__OTG_V_BLANK_MASK
- OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG2_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG2_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG2_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG2_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK
- OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK
- OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT
- OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK
- OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_ERROR_COUNT__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_FIFO_ERROR__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT
- OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK
- OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG3_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG3_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG3_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG3_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG3_OTG_STATUS__OTG_H_BLANK_MASK
- OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG3_OTG_STATUS__OTG_V_BLANK_MASK
- OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG3_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG3_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG3_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG3_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK
- OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK
- OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT
- OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK
- OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_ERROR_COUNT__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_FIFO_ERROR__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT
- OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK
- OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG4_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG4_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG4_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG4_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG4_OTG_STATUS__OTG_H_BLANK_MASK
- OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG4_OTG_STATUS__OTG_V_BLANK_MASK
- OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG4_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG4_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG4_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG4_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE_MASK
- OTG4_PHYPLL_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK
- OTG4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT
- OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK
- OTG4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_ADD_PIXEL__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DIO_ERROR_COUNT__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DIO_FIFO_ERROR__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_ERROR_COUNT__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_FIFO_ERROR__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_HALF_RATE_EN_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DISPOUT_HALF_RATE_EN__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_DROP_PIXEL__SHIFT
- OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE_MASK
- OTG4_PIXEL_RATE_CNTL__OTG4_PIXEL_RATE_SOURCE__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT
- OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK
- OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK
- OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT
- OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER_MASK
- OTG5_OTG_AVSYNC_COUNTER__OTG_AVSYNC_COUNTER__SHIFT
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK
- OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK
- OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT
- OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK
- OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT
- OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK
- OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT
- OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK
- OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK
- OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK
- OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT
- OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK
- OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK
- OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT
- OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK
- OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT
- OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK
- OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT
- OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK
- OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT
- OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK
- OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT
- OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK
- OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT
- OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK
- OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT
- OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK
- OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT
- OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK
- OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT
- OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK
- OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT
- OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK
- OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT
- OTG5_OTG_CONTROL__OTG_SYNC_RESET_SEL_MASK
- OTG5_OTG_CONTROL__OTG_SYNC_RESET_SEL__SHIFT
- OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK
- OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT
- OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK
- OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT
- OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK
- OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT
- OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK
- OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT
- OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK
- OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT
- OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK
- OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT
- OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK
- OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT
- OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK
- OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT
- OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK
- OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT
- OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK
- OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT
- OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK
- OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT
- OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK
- OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT
- OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK
- OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT
- OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK
- OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT
- OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK
- OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT
- OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK
- OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT
- OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK
- OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT
- OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK
- OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT
- OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK
- OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT
- OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK
- OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT
- OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK
- OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT
- OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK
- OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT
- OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK
- OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT
- OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK
- OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT
- OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK
- OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT
- OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK
- OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT
- OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK
- OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT
- OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK
- OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT
- OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK
- OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT
- OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK
- OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT
- OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK
- OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT
- OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK
- OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT
- OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK
- OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT
- OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK
- OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT
- OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK
- OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK
- OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_MULTI_STREAM_MODE__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK
- OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK
- OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT
- OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK
- OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT
- OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK
- OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT
- OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK
- OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT
- OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK
- OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK
- OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT
- OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK
- OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT
- OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK
- OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT
- OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK
- OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT
- OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK
- OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT
- OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT_MASK
- OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_ALIGNMENT__SHIFT
- OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY_MASK
- OTG5_OTG_FIELD_INDICATION_CONTROL__OTG_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK
- OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK
- OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK
- OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK
- OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK
- OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK
- OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK
- OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK
- OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK
- OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT
- OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK
- OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK
- OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK
- OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK
- OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT
- OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK
- OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT
- OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT
- OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK
- OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT
- OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK
- OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT
- OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK
- OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT
- OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK
- OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT
- OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK
- OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT
- OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK
- OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT
- OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK
- OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT
- OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK
- OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT
- OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK
- OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT
- OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK
- OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT
- OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK
- OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT
- OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK
- OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK
- OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT
- OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT
- OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK
- OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT
- OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK
- OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT
- OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK
- OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT
- OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK
- OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT
- OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK
- OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT
- OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK
- OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT
- OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK
- OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT
- OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK
- OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT
- OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK
- OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT
- OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK
- OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT
- OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK
- OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT
- OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK
- OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT
- OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK
- OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT
- OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK
- OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT
- OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK
- OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK
- OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT
- OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK
- OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT
- OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK
- OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT
- OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK
- OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK
- OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT
- OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK
- OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT
- OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK
- OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT
- OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK
- OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT
- OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK
- OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT
- OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK
- OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK
- OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT
- OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK
- OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT
- OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT
- OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK
- OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT
- OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK
- OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT
- OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK
- OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT
- OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK
- OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT
- OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK
- OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT
- OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK
- OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT
- OTG5_OTG_STATUS__OTG_H_BLANK_MASK
- OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT
- OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK
- OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT
- OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK
- OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT
- OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK
- OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT
- OTG5_OTG_STATUS__OTG_V_BLANK_MASK
- OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT
- OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK
- OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT
- OTG5_OTG_STATUS__OTG_V_UPDATE_MASK
- OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK
- OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK
- OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK
- OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK
- OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK
- OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT
- OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA_MASK
- OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_DATA__SHIFT
- OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK_MASK
- OTG5_OTG_TEST_PATTERN_COLOR__OTG_TEST_PATTERN_MASK__SHIFT
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT_MASK
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_COLOR_FORMAT__SHIFT
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE_MASK
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_DYNAMIC_RANGE__SHIFT
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN_MASK
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_EN__SHIFT
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE_MASK
- OTG5_OTG_TEST_PATTERN_CONTROL__OTG_TEST_PATTERN_MODE__SHIFT
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES_MASK
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_HRES__SHIFT
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0_MASK
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC0__SHIFT
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1_MASK
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_INC1__SHIFT
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET_MASK
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_RAMP0_OFFSET__SHIFT
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES_MASK
- OTG5_OTG_TEST_PATTERN_PARAMETERS__OTG_TEST_PATTERN_VRES__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK
- OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT
- OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK
- OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK
- OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT
- OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK
- OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT
- OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK
- OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT
- OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK
- OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK
- OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK
- OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT
- OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK
- OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK
- OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT
- OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK
- OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT
- OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK
- OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT
- OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK
- OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT
- OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK
- OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT
- OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK
- OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT
- OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK
- OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT
- OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK
- OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT
- OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK
- OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT
- OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK
- OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT
- OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK
- OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT
- OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK
- OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT
- OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK
- OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT
- OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK
- OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT
- OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK
- OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT
- OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK
- OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT
- OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT
- OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK
- OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT
- OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK
- OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT
- OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK
- OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT
- OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK
- OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT
- OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE_MASK
- OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PHYPLL_PIXEL_RATE_SOURCE__SHIFT
- OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE_MASK
- OTG5_PHYPLL_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_PLL_SOURCE__SHIFT
- OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK
- OTG5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT
- OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK
- OTG5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_ADD_PIXEL__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DIO_ERROR_COUNT__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DIO_FIFO_ERROR__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_ERROR_COUNT__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_FIFO_ERROR__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_HALF_RATE_EN_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DISPOUT_HALF_RATE_EN__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_DROP_PIXEL__SHIFT
- OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE_MASK
- OTG5_PIXEL_RATE_CNTL__OTG5_PIXEL_RATE_SOURCE__SHIFT
- OTGCMD_A_DEV_DIS
- OTGCMD_A_DEV_EN
- OTGCMD_DEV_BUS_DROP
- OTGCMD_DEV_BUS_REQ
- OTGCMD_DEV_POWER_OFF
- OTGCMD_HOST_BUS_DROP
- OTGCMD_HOST_BUS_REQ
- OTGCMD_HOST_POWER_OFF
- OTGCMD_OTG_DIS
- OTGCMD_OTG_EN
- OTGCSR_A_BUS_DROP
- OTGCSR_A_BUS_REQ
- OTGCSR_HOST_SPD_TYP
- OTGCTL
- OTGCTL_HRESET_N
- OTGCTL_OTGSTAT1
- OTGCTL_OTGSTAT2
- OTGCTL_PRST_N_SW
- OTGCTL_ROUTE_MUSB
- OTGCTL_UTMI_LINE_STATE0
- OTGCTL_UTMI_LINE_STATE1
- OTGIEN_ID_CHANGE_INT
- OTGIEN_VBUSVALID_FALL_INT
- OTGIEN_VBUSVALID_RISE_INT
- OTGISR_OVC
- OTGPUID
- OTGREFCLK_STB_CLK_SWITCH_EN
- OTGSC_1MSIE
- OTGSC_1MSIS
- OTGSC_ASV
- OTGSC_ASVIE
- OTGSC_ASVIS
- OTGSC_AVV
- OTGSC_AVVIE
- OTGSC_AVVIS
- OTGSC_BSE
- OTGSC_BSEIE
- OTGSC_BSEIS
- OTGSC_BSV
- OTGSC_BSVIE
- OTGSC_BSVIS
- OTGSC_CTRL_DATA_PULSING
- OTGSC_CTRL_ID_PULL_EN
- OTGSC_CTRL_OTG_TERM
- OTGSC_CTRL_OTG_TERMINATION
- OTGSC_CTRL_VBUS_CHARGE
- OTGSC_CTRL_VBUS_DISCHARGE
- OTGSC_CTRL_VUSB_CHARGE
- OTGSC_CTRL_VUSB_DISCHARGE
- OTGSC_DPIE
- OTGSC_DPIS
- OTGSC_HABA
- OTGSC_HADP
- OTGSC_HA_BA
- OTGSC_HA_DATA_PULSE
- OTGSC_ID
- OTGSC_IDIE
- OTGSC_IDIS
- OTGSC_IDPU
- OTGSC_INTERRUPT_ENABLE_BITS_MASK
- OTGSC_INTERRUPT_STATUS_BITS_MASK
- OTGSC_INTR_1MS_TIMER
- OTGSC_INTR_1MS_TIMER_EN
- OTGSC_INTR_A_SESSION_VALID
- OTGSC_INTR_A_SESSION_VALID_EN
- OTGSC_INTR_A_VBUS_VALID
- OTGSC_INTR_A_VBUS_VALID_EN
- OTGSC_INTR_B_SESSION_END
- OTGSC_INTR_B_SESSION_END_EN
- OTGSC_INTR_B_SESSION_VALID
- OTGSC_INTR_B_SESSION_VALID_EN
- OTGSC_INTR_DATA_PULSING
- OTGSC_INTR_DATA_PULSING_EN
- OTGSC_INTR_USB_ID
- OTGSC_INTR_USB_ID_EN
- OTGSC_INTSTS_1MS
- OTGSC_INTSTS_A_SESSION_VALID
- OTGSC_INTSTS_A_VBUS_VALID
- OTGSC_INTSTS_B_SESSION_END
- OTGSC_INTSTS_B_SESSION_VALID
- OTGSC_INTSTS_DATA_PULSING
- OTGSC_INTSTS_MASK
- OTGSC_INTSTS_USB_ID
- OTGSC_INT_EN_BITS
- OTGSC_INT_STATUS_BITS
- OTGSC_STS_1MS_TOGGLE
- OTGSC_STS_A_SESSION_VALID
- OTGSC_STS_A_VBUS_VALID
- OTGSC_STS_B_SESSION_END
- OTGSC_STS_B_SESSION_VALID
- OTGSC_STS_DATA_PULSING
- OTGSC_STS_USB_ID
- OTGSTATE_DEV_STATE_MASK
- OTGSTATE_HOST_STATE
- OTGSTATE_HOST_STATE_IDLE
- OTGSTATE_HOST_STATE_MASK
- OTGSTATE_HOST_STATE_VBUS_FALL
- OTGSTS_DEV_ACTIVE
- OTGSTS_DEV_READY
- OTGSTS_HOST_ACTIVE
- OTGSTS_ID_VALUE
- OTGSTS_OTG_NRDY
- OTGSTS_OTG_NRDY_MASK
- OTGSTS_SESSION_VALID
- OTGSTS_STRAP
- OTGSTS_STRAP_GADGET
- OTGSTS_STRAP_HOST
- OTGSTS_STRAP_HOST_OTG
- OTGSTS_STRAP_NO_DEFAULT_CFG
- OTGSTS_VBUS_VALID
- OTGSTS_XHCI_READY
- OTGVPD
- OTGVPU
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE
- OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED
- OTG_ADD_PIXEL
- OTG_ADD_PIXEL_FORCE
- OTG_ADD_PIXEL_NOOP
- OTG_ASESSVLD
- OTG_A_BUSREQ
- OTG_A_DEVICE
- OTG_A_SETB_HNPEN
- OTG_BASE
- OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN
- OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE
- OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE
- OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE
- OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE
- OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE
- OTG_BSESSEND
- OTG_BSESSVLD
- OTG_BUSDROP
- OTG_B_BUSREQ
- OTG_B_DEVICE
- OTG_B_HNPEN
- OTG_B_SESS_END
- OTG_B_SESS_VLD
- OTG_CONTROL_OTG_DISABLE_POINT_CNTL
- OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE
- OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT
- OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST
- OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED
- OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE
- OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE
- OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE
- OTG_CONTROL_OTG_FIELD_NUMBER_CNTL
- OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP
- OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL
- OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY
- OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE
- OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE
- OTG_CONTROL_OTG_MASTER_EN
- OTG_CONTROL_OTG_MASTER_EN_FALSE
- OTG_CONTROL_OTG_MASTER_EN_TRUE
- OTG_CONTROL_OTG_SOF_PULL_EN
- OTG_CONTROL_OTG_SOF_PULL_EN_FALSE
- OTG_CONTROL_OTG_SOF_PULL_EN_TRUE
- OTG_CONTROL_OTG_START_POINT_CNTL
- OTG_CONTROL_OTG_START_POINT_CNTL_DP
- OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL
- OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN
- OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE
- OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE
- OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT
- OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0
- OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1
- OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2
- OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3
- OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE
- OTG_CRC_CNTL2_OTG_CRC_DSC_MODE
- OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE
- OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE
- OTG_CRC_CNTL_OTG_CRC_CONT_EN
- OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE
- OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE
- OTG_CRC_CNTL_OTG_CRC_EN
- OTG_CRC_CNTL_OTG_CRC_EN_FALSE
- OTG_CRC_CNTL_OTG_CRC_EN_TRUE
- OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE
- OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM
- OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD
- OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM
- OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP
- OTG_CRC_CNTL_OTG_CRC_STEREO_MODE
- OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES
- OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS
- OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT
- OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT
- OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS
- OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE
- OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB
- OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB
- OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B
- OTG_CTL_EN
- OTG_CTRL
- OTG_CTRL_BITS
- OTG_CTRL_MASK
- OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN
- OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE
- OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE
- OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE
- OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0
- OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1
- OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2
- OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3
- OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY
- OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE
- OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE
- OTG_DRIVER_SEL
- OTG_DROP_PIXEL
- OTG_DROP_PIXEL_FORCE
- OTG_DROP_PIXEL_NOOP
- OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME
- OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME
- OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME
- OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME
- OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME
- OTG_DRV_VBUS
- OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN
- OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE
- OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE
- OTG_EN
- OTG_EN_B
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE
- OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE
- OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE
- OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE
- OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE
- OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE
- OTG_FLAGS
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA
- OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB
- OTG_FORCESTDBY
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE
- OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4
- OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5
- OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD
- OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL
- OTG_GSL_MASTER_MODE
- OTG_GSL_MASTER_MODE_0
- OTG_GSL_MASTER_MODE_1
- OTG_GSL_MASTER_MODE_2
- OTG_GSL_MASTER_MODE_3
- OTG_HMC
- OTG_HORZ_REPETITION_COUNT
- OTG_HORZ_REPETITION_COUNT_0
- OTG_HORZ_REPETITION_COUNT_1
- OTG_HORZ_REPETITION_COUNT_10
- OTG_HORZ_REPETITION_COUNT_11
- OTG_HORZ_REPETITION_COUNT_12
- OTG_HORZ_REPETITION_COUNT_13
- OTG_HORZ_REPETITION_COUNT_14
- OTG_HORZ_REPETITION_COUNT_15
- OTG_HORZ_REPETITION_COUNT_2
- OTG_HORZ_REPETITION_COUNT_3
- OTG_HORZ_REPETITION_COUNT_4
- OTG_HORZ_REPETITION_COUNT_5
- OTG_HORZ_REPETITION_COUNT_6
- OTG_HORZ_REPETITION_COUNT_7
- OTG_HORZ_REPETITION_COUNT_8
- OTG_HORZ_REPETITION_COUNT_9
- OTG_H_SYNC_A_POL
- OTG_H_SYNC_A_POL_HIGH
- OTG_H_SYNC_A_POL_LOW
- OTG_H_TIMING_DIV_BY2
- OTG_H_TIMING_DIV_BY2_FALSE
- OTG_H_TIMING_DIV_BY2_TRUE
- OTG_H_TIMING_DIV_BY2_UPDATE_MODE
- OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0
- OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1
- OTG_ID
- OTG_IDLE_EN
- OTG_INTERFSEL
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2
- OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE
- OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE
- OTG_IOCTL_MAGIC
- OTG_IRQ_EN
- OTG_IRQ_SRC
- OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
- OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE
- OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE
- OTG_MASTER_UPDATE_LOCK_GSL_EN
- OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE
- OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE
- OTG_MST16
- OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE
- OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG
- OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE
- OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL
- OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR
- OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE
- OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE
- OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR
- OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE
- OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE
- OTG_OUTCTRL
- OTG_PADEN
- OTG_PD_VBUS
- OTG_PHY_CS_GPIO
- OTG_PHY_RESET_GPIO
- OTG_PIPE_ABORT
- OTG_PIPE_ABORT_0
- OTG_PIPE_ABORT_1
- OTG_PORT
- OTG_PTI_CONTROL_OTG_PIT_EN
- OTG_PTI_CONTROL_OTG_PIT_EN_FALSE
- OTG_PTI_CONTROL_OTG_PIT_EN_TRUE
- OTG_PULLDOWN
- OTG_PULLUP
- OTG_PU_ID
- OTG_PU_VBUS
- OTG_RESET
- OTG_RESET_DONE
- OTG_REV
- OTG_REVISION
- OTG_SCHEDULE_DELAY
- OTG_SIMENABLE
- OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL
- OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE
- OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED
- OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA
- OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB
- OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR
- OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE
- OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE
- OTG_SOFT_RESET
- OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY
- OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE
- OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE
- OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN
- OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE
- OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE
- OTG_START_LINE_CONTROL_OTG_PREFETCH_EN
- OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE
- OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE
- OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY
- OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE
- OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE
- OTG_STATE_A_HOST
- OTG_STATE_A_IDLE
- OTG_STATE_A_PERIPHERAL
- OTG_STATE_A_SUSPEND
- OTG_STATE_A_VBUS_ERR
- OTG_STATE_A_WAIT_BCON
- OTG_STATE_A_WAIT_VFALL
- OTG_STATE_A_WAIT_VRISE
- OTG_STATE_B_HOST
- OTG_STATE_B_IDLE
- OTG_STATE_B_PERIPHERAL
- OTG_STATE_B_SRP_INIT
- OTG_STATE_B_WAIT_ACON
- OTG_STATE_UNDEFINED
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE
- OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF
- OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON
- OTG_STEREO_CONTROL_OTG_STEREO_EN
- OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE
- OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE
- OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY
- OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE
- OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE
- OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY
- OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE
- OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE
- OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE
- OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT
- OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO
- OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED
- OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT
- OTG_STS_SELECTOR
- OTG_SYSCONFIG
- OTG_SYSCON_1
- OTG_SYSCON_2
- OTG_SYSCON_2_UHOST_EN_SHIFT
- OTG_SYSSTATUS
- OTG_TEST
- OTG_TIMER_MS
- OTG_TIMER_NUM
- OTG_TIME_A_AIDL_BDIS
- OTG_TIME_A_WAIT_BCON
- OTG_TIME_A_WAIT_VRISE
- OTG_TIME_B_ASE0_BRST
- OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR
- OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE
- OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0
- OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1
- OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN
- OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE
- OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING
- OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC
- OTG_TRIGA_FALLING_EDGE_DETECT_CNTL
- OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0
- OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1
- OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2
- OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3
- OTG_TRIGA_FREQUENCY_SELECT
- OTG_TRIGA_FREQUENCY_SELECT_0
- OTG_TRIGA_FREQUENCY_SELECT_1
- OTG_TRIGA_FREQUENCY_SELECT_2
- OTG_TRIGA_FREQUENCY_SELECT_3
- OTG_TRIGA_RISING_EDGE_DETECT_CNTL
- OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0
- OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1
- OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2
- OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3
- OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR
- OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE
- OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0
- OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1
- OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN
- OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE
- OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING
- OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC
- OTG_TRIGB_FALLING_EDGE_DETECT_CNTL
- OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0
- OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1
- OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2
- OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3
- OTG_TRIGB_FREQUENCY_SELECT
- OTG_TRIGB_FREQUENCY_SELECT_0
- OTG_TRIGB_FREQUENCY_SELECT_1
- OTG_TRIGB_FREQUENCY_SELECT_2
- OTG_TRIGB_FREQUENCY_SELECT_3
- OTG_TRIGB_RISING_EDGE_DETECT_CNTL
- OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0
- OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1
- OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2
- OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3
- OTG_UPDATE_LOCK_OTG_UPDATE_LOCK
- OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE
- OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE
- OTG_USB0_DM
- OTG_USB0_DP
- OTG_USB0_EN
- OTG_USB1_DM
- OTG_USB1_DP
- OTG_USB1_EN
- OTG_USB2_DM
- OTG_USB2_DP
- OTG_USB2_EN
- OTG_VBUSVLD
- OTG_VENDOR_CODE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE
- OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE
- OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE
- OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE
- OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE
- OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE
- OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED
- OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA
- OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB
- OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR
- OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE
- OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE
- OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE
- OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE
- OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE
- OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR
- OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE
- OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE
- OTG_V_SYNC_A_POL
- OTG_V_SYNC_A_POL_HIGH
- OTG_V_SYNC_A_POL_LOW
- OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD
- OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0
- OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE
- OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE
- OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN
- OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE
- OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE
- OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE
- OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK
- OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE
- OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE
- OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR
- OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE
- OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE
- OTG_XCEIV_INPUTS
- OTG_XCEIV_OUTPUTS
- OTHER
- OTHERBANDUNIT
- OTHERCONTROL
- OTHERS
- OTHERS_MASK
- OTHER_CLASS
- OTHER_COMMAND
- OTHER_FUNC_CTRL
- OTHER_FUNC_CTRL2
- OTHER_FUNC_CTRL2_VBAT_TIMER_EN
- OTHER_FUNC_CTRL_BDIS_ACON_EN
- OTHER_FUNC_CTRL_FIVEWIRE_MODE
- OTHER_GTPM_INSTANCE
- OTHER_GUC_INSTANCE
- OTHER_IFC_CTRL
- OTHER_IFC_CTRL2
- OTHER_IFC_CTRL2_ULPI_4PIN_2430
- OTHER_IFC_CTRL2_ULPI_STP_LOW
- OTHER_IFC_CTRL2_ULPI_TXEN_POL
- OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N
- OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N
- OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK
- OTHER_IFC_CTRL_ALT_INT_REROUTE
- OTHER_IFC_CTRL_CEA2011_MODE
- OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN
- OTHER_IFC_CTRL_HIZ_ULPI
- OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT
- OTHER_IFC_CTRL_OE_INT_EN
- OTHER_INT_ABNORMAL_STRESS
- OTHER_INT_BDIS_ACON
- OTHER_INT_DM_HI
- OTHER_INT_DP_HI
- OTHER_INT_EN_FALL
- OTHER_INT_EN_RISE
- OTHER_INT_LATCH
- OTHER_INT_MANU
- OTHER_INT_STS
- OTHER_INT_VB_SESS_VLD
- OTHER_IRQ
- OTHER_LABEL
- OTHER_MCAST_TABLE
- OTHER_PORT
- OTHER_TEXT_SECTIONS
- OTHER_VECTOR
- OTI6858_AUTHOR
- OTI6858_CTRL_EQUALS_PENDING
- OTI6858_CTRL_PKT_SIZE
- OTI6858_DESCRIPTION
- OTI6858_MAX_BAUD_RATE
- OTI6858_PRODUCT_ID
- OTI6858_REQ_CHECK_TXBUFF
- OTI6858_REQ_GET_STATUS
- OTI6858_REQ_SET_LINE
- OTI6858_REQ_T_CHECK_TXBUFF
- OTI6858_REQ_T_GET_STATUS
- OTI6858_REQ_T_SET_LINE
- OTI6858_VENDOR_ID
- OTM3225A_DATA_REG
- OTM3225A_INDEX_REG
- OTM8009A_BACKLIGHT_DEFAULT
- OTM8009A_BACKLIGHT_MAX
- OTMP_D1R_INT
- OTMP_D1R_INT_MASK
- OTOM_PA_CS8900A_BASE
- OTOM_PA_FLASH0_BASE
- OTOM_VA_CS8900A_BASE
- OTPC_ADDR_MASK
- OTPC_CMD_MASK
- OTPC_CMD_OTP_PROG_DISABLE
- OTPC_CMD_OTP_PROG_ENABLE
- OTPC_CMD_PROGRAM
- OTPC_CMD_READ
- OTPC_CMD_START_OFFSET
- OTPC_CMD_START_START
- OTPC_COMMAND_COMMAND_WIDTH
- OTPC_COMMAND_OFFSET
- OTPC_CPUADDR_REG_OFFSET
- OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH
- OTPC_CPU_STATUS_OFFSET
- OTPC_CPU_WRITE_REG_OFFSET
- OTPC_MODE_REG_OFFSET
- OTPC_MODE_REG_OTPC_MODE
- OTPC_PROG_EN_SEQ
- OTPC_RETRIES
- OTPC_STAT_CMD_DONE
- OTPC_STAT_PROG_OK
- OTPGETREGIONCOUNT
- OTPGETREGIONINFO
- OTPLOCK
- OTPSELECT
- OTP_6328_REG3_TP1_DISABLED
- OTP_ADDR1
- OTP_ADDR1_15_11
- OTP_ADDR2
- OTP_ADDR2_10_3
- OTP_ADDR3
- OTP_ADDR3_2_0
- OTP_ADDRESS
- OTP_ADDRESS_MAGIC0
- OTP_ADDRESS_MAGIC1
- OTP_ADDRESS_MAGIC2
- OTP_ADDR_HIGH
- OTP_ADDR_LOW
- OTP_ADDR_RANGE_
- OTP_BASE_ADDR
- OTP_CMD_GO
- OTP_CMD_GO_GO_
- OTP_CTRL
- OTP_CTRL_CLK_EN
- OTP_CTRL_OTP_CMD_INIT
- OTP_CTRL_OTP_CMD_READ
- OTP_CTRL_OTP_CMD_START
- OTP_CTRL_OTP_PROG_ENABLE
- OTP_ENABLE_WD
- OTP_FUNC_CMD
- OTP_FUNC_CMD_PROGRAM_
- OTP_FUNC_CMD_READ_
- OTP_FUNC_CMD_RESET_
- OTP_HIGH_IMAGE_SIZE_1000
- OTP_HIGH_IMAGE_SIZE_6x00
- OTP_HW_COUNT
- OTP_HW_DELAY
- OTP_INDICATOR_1
- OTP_INDICATOR_2
- OTP_INTR_MASK
- OTP_INTR_MASK_READY_
- OTP_INTR_STATUS
- OTP_INTR_STATUS_READY_
- OTP_LOW_IMAGE_SIZE_16K
- OTP_LOW_IMAGE_SIZE_2K
- OTP_LOW_IMAGE_SIZE_32K
- OTP_MAX_LL_ITEMS_1000
- OTP_MAX_LL_ITEMS_2x00
- OTP_MAX_LL_ITEMS_6x00
- OTP_MAX_LL_ITEMS_6x50
- OTP_MAX_PRG
- OTP_MAX_PRG_MAX_PROG
- OTP_MODE
- OTP_MODE_OTP_THRU_GRC
- OTP_PASS_FAIL
- OTP_PASS_FAIL_FAIL_
- OTP_PASS_FAIL_PASS_
- OTP_PGM_PW1
- OTP_PGM_PW2
- OTP_PRGM_DATA
- OTP_PRGM_MODE
- OTP_PRGM_MODE_BYTE_
- OTP_PWR_DN
- OTP_PWR_DN_PWRDN_N_
- OTP_RD_DATA
- OTP_READ_DATA
- OTP_READ_PW1
- OTP_READ_PW2
- OTP_RSRD
- OTP_RSTB_PW1
- OTP_RSTB_PW2
- OTP_STATUS
- OTP_STATUS_BUSY_
- OTP_STATUS_CMD_DONE
- OTP_STATUS_CPUMPEN_
- OTP_STATUS_OTP_LOCK_
- OTP_STATUS_PGMEN
- OTP_STATUS_WEB_
- OTP_TAAC_VAL
- OTP_TACCT_VAL
- OTP_TBCACC_VAL
- OTP_TCLEH_VAL
- OTP_TCLES_VAL
- OTP_TCPH_VAL
- OTP_TCPS_VAL
- OTP_TCRST
- OTP_TDLEH_VAL
- OTP_TDLES_VAL
- OTP_TPEH_VAL
- OTP_TPES_VAL
- OTP_TPGMVFY_VAL
- OTP_TPGRST_VAL
- OTP_TPGSV_VAL
- OTP_TPVHR_VAL
- OTP_TPVSA_VAL
- OTP_TPVSR_VAL
- OTP_TRDEP_VAL
- OTP_TRDES_VAL
- OTP_TREADEN_VAL
- OTP_TST_CMD
- OTP_TST_CMD_BLANKCHECK_
- OTP_TST_CMD_PRGVRFY_
- OTP_TST_CMD_TESTDEC_
- OTP_TST_CMD_TEST_DEC_SEL_
- OTP_TST_CMD_WRTEST_
- OTP_TWPED_VAL
- OTP_TWWL_VAL
- OTP_USER_BITS_6328_REG
- OTUS_MAGIC
- OTX2_ALIGN
- OTX2_MBOX_REQ_SIG
- OTX2_MBOX_RSP_SIG
- OTX2_MBOX_VERSION
- OT_EC_BL_BRIGHTNESS_ADDRESS
- OT_EC_BL_BRIGHTNESS_MAX
- OT_EC_BL_CONTROL_ADDRESS
- OT_EC_BL_CONTROL_ON_DATA
- OT_EC_BT_MASK
- OT_EC_CAMERA_MASK
- OT_EC_DEVICE_STATE_ADDRESS
- OT_EC_GPS_MASK
- OT_EC_TS_MASK
- OT_EC_WIFI_MASK
- OT_EC_WWAN_MASK
- OUF_SRC
- OUI
- OUI_ALESIS
- OUI_APOGEE
- OUI_APPLE
- OUI_ARMADEUS
- OUI_BROADCOM
- OUI_CRYSTALFONTZ
- OUI_DENX
- OUI_FOCUSRITE
- OUI_FSL
- OUI_I2SE
- OUI_LEN
- OUI_LOUD
- OUI_MAUDIO
- OUI_MICROSOFT
- OUI_MOTU
- OUI_MYTEK
- OUI_PRESONUS
- OUI_QCA
- OUI_RME
- OUI_SSL
- OUI_STANTON
- OUI_TCELECTRONIC
- OUI_WEISS
- OURADDR
- OUR_ID
- OUR_ID_EN
- OUR_NAME
- OUR_USB_ADDRESS
- OUT
- OUT12_MON34
- OUT32
- OUT34_MON12
- OUT4500
- OUTB
- OUTBOUNDDOORBELL_0
- OUTBOUNDDOORBELL_1
- OUTBOUNDDOORBELL_2
- OUTBOUNDDOORBELL_3
- OUTBOUNDDOORBELL_4
- OUTBOUND_DOORBELL_REGISTER_CPU_SIDE
- OUTBOUND_DOORBELL_REGISTER_PCI_SIDE
- OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE
- OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE
- OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE
- OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE
- OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE
- OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE
- OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE
- OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE
- OUTBOUND_MAC_IOCB
- OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE
- OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE
- OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE
- OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE
- OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE
- OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE
- OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE
- OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE
- OUTBOUND_QUEUE_PORT
- OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE
- OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE
- OUTBOUND_STATE_TIMEOUT
- OUTBUFLEN
- OUTBUFMAX
- OUTB_OFF
- OUTCLIP
- OUTCLIP_DEFAULT
- OUTCLK_ASRCK1_CLK
- OUTCLK_ESAI_RX
- OUTCLK_ESAI_TX
- OUTCLK_MLB_CLK
- OUTCLK_NONE
- OUTCLK_PAD
- OUTCLK_SPDIF_RX
- OUTCLK_SPDIF_TX
- OUTCLK_SSI1_RX
- OUTCLK_SSI1_TX
- OUTCLK_SSI2_RX
- OUTCLK_SSI2_TX
- OUTCLK_SSI3_RX
- OUTCLK_SSI3_TX
- OUTCONT_BUFLEN
- OUTCSET
- OUTCSET_CHDRV_4MA
- OUTCSET_CHDRV_8MA
- OUTCTR1
- OUTCTR2
- OUTDT
- OUTDTSEL
- OUTEN
- OUTER_DST_IP
- OUTER_DST_MAC
- OUTER_DST_PORT
- OUTER_ETH_TYPE
- OUTER_IP_PROTO
- OUTER_IP_TOS
- OUTER_L2_RSV
- OUTER_L3_RSV
- OUTER_L4_RSV
- OUTER_PROVIDER_VLAN
- OUTER_SRC_IP
- OUTER_SRC_MAC
- OUTER_SRC_PORT
- OUTER_TUN_FLOW_ID
- OUTER_TUN_VNI
- OUTER_VLAN
- OUTER_VLAN_TAG_FST
- OUTER_VLAN_TAG_SEC
- OUTFF_ENB
- OUTL
- OUTL_DSP
- OUTL_OFF
- OUTMC
- OUTMODE_ANALOG_ADC
- OUTMODE_DIVERSITY
- OUTMODE_HIGH_Z
- OUTMODE_MASK
- OUTMODE_MPEG2_FIFO
- OUTMODE_MPEG2_PAR_CONT_CLK
- OUTMODE_MPEG2_PAR_GATED_CLK
- OUTMODE_MPEG2_SERIAL
- OUTOFFB
- OUTOFFL
- OUTOFFW
- OUTOFRANGE
- OUTONB
- OUTONB_STD
- OUTONL
- OUTONW
- OUTP
- OUTPLL
- OUTPLLP
- OUTPUT
- OUTPUTSNOOPII_SCB_ADDR
- OUTPUTSNOOP_SCB_ADDR
- OUTPUTS_TRISTATE
- OUTPUT_10BIT_422_EMBEDDED_SYNC
- OUTPUT_10BIT_422_SEPERATE_SYNC
- OUTPUT_1V8
- OUTPUT_20BIT_422_SEPERATE_SYNC
- OUTPUT_3V3
- OUTPUT_CLEAR
- OUTPUT_CLK
- OUTPUT_CLK_SHIFT
- OUTPUT_CRT
- OUTPUT_CSC_BYPASS
- OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A_MASK
- OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C11_A__SHIFT
- OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A_MASK
- OUTPUT_CSC_C11_C12_A__OUTPUT_CSC_C12_A__SHIFT
- OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B_MASK
- OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C11_B__SHIFT
- OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B_MASK
- OUTPUT_CSC_C11_C12_B__OUTPUT_CSC_C12_B__SHIFT
- OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK
- OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT
- OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK
- OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT
- OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A_MASK
- OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C13_A__SHIFT
- OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A_MASK
- OUTPUT_CSC_C13_C14_A__OUTPUT_CSC_C14_A__SHIFT
- OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B_MASK
- OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C13_B__SHIFT
- OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B_MASK
- OUTPUT_CSC_C13_C14_B__OUTPUT_CSC_C14_B__SHIFT
- OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK
- OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT
- OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK
- OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT
- OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A_MASK
- OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C21_A__SHIFT
- OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A_MASK
- OUTPUT_CSC_C21_C22_A__OUTPUT_CSC_C22_A__SHIFT
- OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B_MASK
- OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C21_B__SHIFT
- OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B_MASK
- OUTPUT_CSC_C21_C22_B__OUTPUT_CSC_C22_B__SHIFT
- OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK
- OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT
- OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK
- OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT
- OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A_MASK
- OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C23_A__SHIFT
- OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A_MASK
- OUTPUT_CSC_C23_C24_A__OUTPUT_CSC_C24_A__SHIFT
- OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B_MASK
- OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C23_B__SHIFT
- OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B_MASK
- OUTPUT_CSC_C23_C24_B__OUTPUT_CSC_C24_B__SHIFT
- OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK
- OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT
- OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK
- OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT
- OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A_MASK
- OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C31_A__SHIFT
- OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A_MASK
- OUTPUT_CSC_C31_C32_A__OUTPUT_CSC_C32_A__SHIFT
- OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B_MASK
- OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C31_B__SHIFT
- OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B_MASK
- OUTPUT_CSC_C31_C32_B__OUTPUT_CSC_C32_B__SHIFT
- OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK
- OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT
- OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK
- OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT
- OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A_MASK
- OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C33_A__SHIFT
- OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A_MASK
- OUTPUT_CSC_C33_C34_A__OUTPUT_CSC_C34_A__SHIFT
- OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B_MASK
- OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C33_B__SHIFT
- OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B_MASK
- OUTPUT_CSC_C33_C34_B__OUTPUT_CSC_C34_B__SHIFT
- OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK
- OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT
- OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK
- OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT
- OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK
- OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
- OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK
- OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT
- OUTPUT_CSC_MATRIX_SIZE
- OUTPUT_CSC_PROG_COEFF
- OUTPUT_CSC_PROG_SHARED_MATRIXB
- OUTPUT_CSC_TV_RGB
- OUTPUT_CSC_YCBCR_601
- OUTPUT_CSC_YCBCR_709
- OUTPUT_CTL
- OUTPUT_DATA_REG
- OUTPUT_EN
- OUTPUT_ENABLE_CIR
- OUTPUT_ENABLE_CIRWB
- OUTPUT_ENABLE_OFF
- OUTPUT_EN_CLEAR
- OUTPUT_EN_SET
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK_MASK
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_ACK__SHIFT
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED_MASK
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_OVERFLOW_OCCURED__SHIFT
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK_MASK
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_ACK__SHIFT
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED_MASK
- OUTPUT_FIFO_ERROR__OUTPUT_FIFO_UNDERFLOW_OCCURED__SHIFT
- OUTPUT_HIGH
- OUTPUT_INVALID
- OUTPUT_LAST
- OUTPUT_LINE
- OUTPUT_LOW
- OUTPUT_MORE
- OUTPUT_ONLY
- OUTPUT_PANEL
- OUTPUT_PARM
- OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK
- OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT
- OUTPUT_PIN_SEL_MASK
- OUTPUT_POINT
- OUTPUT_POOL_SHIFT
- OUTPUT_POOL_WORDS
- OUTPUT_READY
- OUTPUT_REG_OFFSET
- OUTPUT_REPORT
- OUTPUT_SET
- OUTPUT_SNOOP_BUFFER
- OUTPUT_SOURCE_ENUM
- OUTPUT_STATUS0
- OUTPUT_STATUS1
- OUTPUT_STATUS2
- OUTPUT_STD_EIA0_1
- OUTPUT_STD_EIA0_2
- OUTPUT_STD_FULL
- OUTPUT_STD_MASK
- OUTPUT_STD_SHIFT
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK
- OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK
- OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK
- OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK
- OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ
- OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK
- OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK
- OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK
- OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT
- OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK
- OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT
- OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK
- OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT
- OUTPUT_TERMINAL_ID
- OUTPUT_TRIANGLE_CCW
- OUTPUT_TRIANGLE_CW
- OUTPUT_TYPE
- OUTPUT_TYPE_MAX
- OUTPUT_TYPE_SYNTH
- OUTPUT_URBS
- OUTPUT_VAL
- OUTPUT_VALUE_OFF
- OUTPUT_VAL_SHIFT
- OUTPUT_XSIZE_OFST
- OUTP_DBG
- OUTP_ERR
- OUTP_MSG
- OUTP_TRACE
- OUTRANGEERR_DISCARD
- OUTREG
- OUTREG16
- OUTREG8
- OUTREGP
- OUTSET2
- OUTSIDE_GUEST_MODE
- OUTSIZE
- OUTSTANDING_REQ
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK
- OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT
- OUTUNPACK
- OUTVACT_LPCMD_TIME
- OUTW
- OUTW_OFF
- OUTX
- OUTX_H
- OUTX_L
- OUTY
- OUTY_H
- OUTY_L
- OUTZ
- OUTZ_H
- OUTZ_L
- OUT_82c54_TIMER
- OUT_APP0
- OUT_APP1
- OUT_AUDIO_LEVEL_NOTIFIED
- OUT_BATCH
- OUT_BIT
- OUT_BIT_10
- OUT_BIT_12
- OUT_BIT_16
- OUT_BIT_8
- OUT_BIT_MASK
- OUT_BLOCK_WRITE_REQ
- OUT_BUFLEN
- OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK
- OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT
- OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK
- OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT
- OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK
- OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT
- OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK
- OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT
- OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK
- OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT
- OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK
- OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT
- OUT_CTRL1
- OUT_CTRL2
- OUT_CTRL_NS
- OUT_DATA_STAGE
- OUT_DIP0
- OUT_DIP1
- OUT_DIP2
- OUT_DIP3
- OUT_DIP4
- OUT_DIP5
- OUT_DIP6
- OUT_DIP7
- OUT_DISC
- OUT_DOORBELL_OFFSET
- OUT_EFFECTS_COUNT
- OUT_EFFECT_END_NID
- OUT_EFFECT_START_NID
- OUT_ENDPOINT_ENABLE
- OUT_ENDPOINT_TYPE
- OUT_EP
- OUT_EP_DOORBELL
- OUT_ETHTYP
- OUT_FIFO_BASE_ADDRESS
- OUT_FIFO_SIZE
- OUT_FMT_IDX
- OUT_FUNC_C1OUT
- OUT_FUNC_C1TX
- OUT_FUNC_C2OUT
- OUT_FUNC_C2TX
- OUT_FUNC_OC1
- OUT_FUNC_OC2
- OUT_FUNC_OC3
- OUT_FUNC_OC4
- OUT_FUNC_OC5
- OUT_FUNC_OC6
- OUT_FUNC_OC7
- OUT_FUNC_OC8
- OUT_FUNC_OC9
- OUT_FUNC_REFCLKO1
- OUT_FUNC_REFCLKO3
- OUT_FUNC_REFCLKO4
- OUT_FUNC_SDO1
- OUT_FUNC_SDO2
- OUT_FUNC_SDO3
- OUT_FUNC_SDO4
- OUT_FUNC_SDO5
- OUT_FUNC_SDO6
- OUT_FUNC_SS1
- OUT_FUNC_SS2
- OUT_FUNC_SS3
- OUT_FUNC_SS4
- OUT_FUNC_SS5
- OUT_FUNC_SS6
- OUT_FUNC_U1RTS
- OUT_FUNC_U1TX
- OUT_FUNC_U2RTS
- OUT_FUNC_U2TX
- OUT_FUNC_U3RTS
- OUT_FUNC_U3TX
- OUT_FUNC_U4RTS
- OUT_FUNC_U4TX
- OUT_FUNC_U5RTS
- OUT_FUNC_U5TX
- OUT_FUNC_U6RTS
- OUT_FUNC_U6TX
- OUT_I2S_0_CFG_OFFSET
- OUT_I2S_0_MCLK_CFG_OFFSET
- OUT_I2S_0_STREAM_CFG_OFFSET
- OUT_I2S_1_CFG_OFFSET
- OUT_I2S_1_MCLK_CFG_OFFSET
- OUT_I2S_1_STREAM_CFG_OFFSET
- OUT_I2S_2_CFG_OFFSET
- OUT_I2S_2_MCLK_CFG_OFFSET
- OUT_I2S_2_STREAM_CFG_OFFSET
- OUT_IGMP0
- OUT_IGMP1
- OUT_IP0
- OUT_IP1
- OUT_IP2
- OUT_IP3
- OUT_IPOFF
- OUT_ITAG0
- OUT_ITAG1
- OUT_ITAG2
- OUT_ITAG3
- OUT_LAST
- OUT_LVL_BIT
- OUT_MAC0
- OUT_MAC1
- OUT_MAC2
- OUT_MAC3
- OUT_MAC4
- OUT_MAC5
- OUT_MASK
- OUT_MODE_601
- OUT_MODE_656
- OUT_MODE_VIP11
- OUT_MODE_VIP20
- OUT_MPG
- OUT_MSG_ACK_FRG
- OUT_MSG_BRIDGE_APB_R
- OUT_MSG_BRIDGE_APB_W
- OUT_MSG_BRIDGE_I2C_R
- OUT_MSG_BRIDGE_I2C_W
- OUT_MSG_CONF_GPIO
- OUT_MSG_CONF_SVC
- OUT_MSG_CTL_MONIT
- OUT_MSG_DEBUG_HELP
- OUT_MSG_EC_REQUEST_PREAMBLE
- OUT_MSG_ENABLE_DIVERSITY
- OUT_MSG_ENABLE_TIME_SLICE
- OUT_MSG_FE_CHANNEL_SEARCH
- OUT_MSG_FE_CHANNEL_TUNE
- OUT_MSG_FE_FW_DL
- OUT_MSG_FE_SLEEP
- OUT_MSG_FE_SYNC
- OUT_MSG_HBM_ACK
- OUT_MSG_HOST_BUF_FAIL
- OUT_MSG_INIT_DEMOD
- OUT_MSG_INIT_PMU
- OUT_MSG_MONIT_DEMOD
- OUT_MSG_REQ_VERSION
- OUT_MSG_SCAN_CHANNEL
- OUT_MSG_SET_HBM
- OUT_MSG_SET_OUTPUT_MODE
- OUT_MSG_SET_PRIORITARY_CHANNEL
- OUT_MSG_SUBBAND_SEL
- OUT_NONE
- OUT_N_CHANNELS
- OUT_OF_RANGE
- OUT_OF_TABLE_CPCON
- OUT_OF_TXD
- OUT_ORDER_MODE
- OUT_OVLY
- OUT_PASSTHROUGH
- OUT_PID
- OUT_PIPE
- OUT_PKT0
- OUT_PKT2
- OUT_PKT3
- OUT_PKT4
- OUT_PKT7
- OUT_PROT
- OUT_QUEUE_TH
- OUT_RING
- OUT_RINGp
- OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK
- OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT
- OUT_RPA14
- OUT_RPA15
- OUT_RPB0
- OUT_RPB1
- OUT_RPB10
- OUT_RPB14
- OUT_RPB15
- OUT_RPB2
- OUT_RPB3
- OUT_RPB5
- OUT_RPB6
- OUT_RPB7
- OUT_RPB8
- OUT_RPB9
- OUT_RPC1
- OUT_RPC13
- OUT_RPC14
- OUT_RPC2
- OUT_RPC3
- OUT_RPC4
- OUT_RPD0
- OUT_RPD1
- OUT_RPD10
- OUT_RPD11
- OUT_RPD12
- OUT_RPD14
- OUT_RPD15
- OUT_RPD2
- OUT_RPD3
- OUT_RPD4
- OUT_RPD5
- OUT_RPD6
- OUT_RPD7
- OUT_RPD9
- OUT_RPE3
- OUT_RPE5
- OUT_RPE8
- OUT_RPE9
- OUT_RPF0
- OUT_RPF1
- OUT_RPF12
- OUT_RPF13
- OUT_RPF2
- OUT_RPF3
- OUT_RPF4
- OUT_RPF5
- OUT_RPF8
- OUT_RPG0
- OUT_RPG1
- OUT_RPG6
- OUT_RPG7
- OUT_RPG8
- OUT_RPG9
- OUT_SESID
- OUT_SIP0
- OUT_SIP1
- OUT_SIP2
- OUT_SIP3
- OUT_SIP4
- OUT_SIP5
- OUT_SIP6
- OUT_SIP7
- OUT_STATUS_STAGE
- OUT_STREAM_EXTRAPARAMETER_NOTIFIED
- OUT_STREAM_FORMAT_NOTIFIED
- OUT_STREAM_LEVEL_CURVE_NOTIFIED
- OUT_STREAM_LEVEL_NOTIFIED
- OUT_STREAM_PARAMETER_NOTIFIED
- OUT_TOKEN_FRAME
- OUT_UDMA_YUV
- OUT_VENDOR_REQ
- OUT_VOLUME
- OUT_VTAG0
- OUT_VTAG1
- OUT_YUV
- OV0_AUTO_FLIP_CNTRL
- OV0_BASE_ADDR
- OV0_DEINTERLACE_PATTERN
- OV0_FILTER_CNTL
- OV0_FLAG_CNTRL
- OV0_FOUR_TAP_COEF_0
- OV0_FOUR_TAP_COEF_1
- OV0_FOUR_TAP_COEF_2
- OV0_FOUR_TAP_COEF_3
- OV0_FOUR_TAP_COEF_4
- OV0_GAMMA_0_F
- OV0_GAMMA_10_1F
- OV0_GAMMA_20_3F
- OV0_GAMMA_380_3BF
- OV0_GAMMA_3C0_3FF
- OV0_GAMMA_40_7F
- OV0_GRPH_KEY_CLR_HIGH
- OV0_GRPH_KEY_CLR_LOW
- OV0_H_INC
- OV0_KEY_CNTL
- OV0_LIN_TRANS_A
- OV0_LIN_TRANS_B
- OV0_LIN_TRANS_C
- OV0_LIN_TRANS_D
- OV0_LIN_TRANS_E
- OV0_LIN_TRANS_F
- OV0_P1_BLANK_LINES_AT_TOP
- OV0_P1_H_ACCUM_INIT
- OV0_P1_V_ACCUM_INIT
- OV0_P1_X_START_END
- OV0_P23_BLANK_LINES_AT_TOP
- OV0_P23_H_ACCUM_INIT
- OV0_P23_V_ACCUM_INIT
- OV0_P2_X_START_END
- OV0_P3_X_START_END
- OV0_PIPELINE_CNTL
- OV0_REG_LOAD_CNTL
- OV0_SCALE_CNTL
- OV0_SLICE_CNTL
- OV0_STEP_BY
- OV0_SUBMIT_HISTORY
- OV0_TEST
- OV0_VID_BUF0_BASE_ADRS
- OV0_VID_BUF1_BASE_ADRS
- OV0_VID_BUF2_BASE_ADRS
- OV0_VID_BUF3_BASE_ADRS
- OV0_VID_BUF4_BASE_ADRS
- OV0_VID_BUF5_BASE_ADRS
- OV0_VID_BUF_PITCH0_VALUE
- OV0_VID_BUF_PITCH1_VALUE
- OV0_VID_KEY_CLR_HIGH
- OV0_VID_KEY_CLR_LOW
- OV0_V_INC
- OV0_Y_X_END
- OV0_Y_X_START
- OV13858_ANA_GAIN_DEFAULT
- OV13858_ANA_GAIN_MAX
- OV13858_ANA_GAIN_MIN
- OV13858_ANA_GAIN_STEP
- OV13858_CHIP_ID
- OV13858_DGTL_GAIN_DEFAULT
- OV13858_DGTL_GAIN_MAX
- OV13858_DGTL_GAIN_MIN
- OV13858_DGTL_GAIN_STEP
- OV13858_EXPOSURE_DEFAULT
- OV13858_EXPOSURE_MIN
- OV13858_EXPOSURE_STEP
- OV13858_LINK_FREQ_270MHZ
- OV13858_LINK_FREQ_540MHZ
- OV13858_LINK_FREQ_INDEX_0
- OV13858_LINK_FREQ_INDEX_1
- OV13858_MODE_STANDBY
- OV13858_MODE_STREAMING
- OV13858_NUM_OF_LINK_FREQS
- OV13858_NUM_OF_SKIP_FRAMES
- OV13858_PPL_270MHZ
- OV13858_PPL_540MHZ
- OV13858_REG_ANALOG_GAIN
- OV13858_REG_B_MWB_GAIN
- OV13858_REG_CHIP_ID
- OV13858_REG_EXPOSURE
- OV13858_REG_G_MWB_GAIN
- OV13858_REG_MIPI_SC_CTRL0
- OV13858_REG_MIPI_SC_CTRL1
- OV13858_REG_MODE_SELECT
- OV13858_REG_PLL1_CTRL_0
- OV13858_REG_PLL1_CTRL_1
- OV13858_REG_PLL1_CTRL_2
- OV13858_REG_PLL1_CTRL_3
- OV13858_REG_PLL1_CTRL_4
- OV13858_REG_PLL1_CTRL_5
- OV13858_REG_PLL2_CTRL_12
- OV13858_REG_PLL2_CTRL_B
- OV13858_REG_PLL2_CTRL_C
- OV13858_REG_PLL2_CTRL_D
- OV13858_REG_PLL2_CTRL_E
- OV13858_REG_PLL2_CTRL_F
- OV13858_REG_R_MWB_GAIN
- OV13858_REG_SOFTWARE_RST
- OV13858_REG_TEST_PATTERN
- OV13858_REG_VALUE_08BIT
- OV13858_REG_VALUE_16BIT
- OV13858_REG_VALUE_24BIT
- OV13858_REG_VTS
- OV13858_SOFTWARE_RST
- OV13858_TEST_PATTERN_ENABLE
- OV13858_TEST_PATTERN_MASK
- OV13858_VTS_30FPS
- OV13858_VTS_60FPS
- OV13858_VTS_MAX
- OV1_PPC_2_00
- OV1_PPC_2_01
- OV1_PPC_2_02
- OV1_PPC_2_03
- OV1_PPC_2_04
- OV1_PPC_2_05
- OV1_PPC_2_06
- OV1_PPC_2_07
- OV1_PPC_3_00
- OV2640_SIZE
- OV2659_H
- OV2659_ID
- OV265X_ID
- OV2680_CHIP_ID
- OV2680_FRAME_RATE
- OV2680_HEIGHT_MAX
- OV2680_MODE_720P_1280_720
- OV2680_MODE_MAX
- OV2680_MODE_QUXGA_800_600
- OV2680_MODE_UXGA_1600_1200
- OV2680_NUM_SUPPLIES
- OV2680_REG_CHIP_ID_HIGH
- OV2680_REG_CHIP_ID_LOW
- OV2680_REG_EXPOSURE_PK_HIGH
- OV2680_REG_FORMAT1
- OV2680_REG_FORMAT2
- OV2680_REG_GAIN_PK
- OV2680_REG_ISP_CTRL00
- OV2680_REG_R_MANUAL
- OV2680_REG_SOFT_RESET
- OV2680_REG_STREAM_CTRL
- OV2680_REG_TIMING_HTS
- OV2680_REG_TIMING_VTS
- OV2680_REG_VALUE_16BIT
- OV2680_REG_VALUE_24BIT
- OV2680_REG_VALUE_8BIT
- OV2680_WIDTH_MAX
- OV2680_XVCLK_VALUE
- OV2685_BITS_PER_SAMPLE
- OV2685_EXPOSURE_MIN
- OV2685_EXPOSURE_STEP
- OV2685_GAIN_DEFAULT
- OV2685_GAIN_MAX
- OV2685_GAIN_MIN
- OV2685_GAIN_STEP
- OV2685_LANES
- OV2685_LINK_FREQ_330MHZ
- OV2685_NUM_SUPPLIES
- OV2685_REG_CHIP_ID
- OV2685_REG_EXPOSURE
- OV2685_REG_GAIN
- OV2685_REG_TEST_PATTERN
- OV2685_REG_VALUE_08BIT
- OV2685_REG_VALUE_16BIT
- OV2685_REG_VALUE_24BIT
- OV2685_REG_VTS
- OV2685_TEST_PATTERN_BW_SQUARE
- OV2685_TEST_PATTERN_COLOR_BAR
- OV2685_TEST_PATTERN_COLOR_BAR_FADE
- OV2685_TEST_PATTERN_COLOR_SQUARE
- OV2685_TEST_PATTERN_DISABLED
- OV2685_TEST_PATTERN_RANDOM
- OV2685_VTS_MAX
- OV2685_XVCLK_FREQ
- OV2_REAL_MODE
- OV3_DFP
- OV3_FP
- OV3_VMX
- OV4_MIN_ENT_CAP
- OV511_RESET_OMNICE
- OV519_GPIO_DATA_OUT0
- OV519_GPIO_IO_CTRL0
- OV519_R10_H_SIZE
- OV519_R11_V_SIZE
- OV519_R12_X_OFFSETL
- OV519_R13_X_OFFSETH
- OV519_R14_Y_OFFSETL
- OV519_R15_Y_OFFSETH
- OV519_R16_DIVIDER
- OV519_R20_DFR
- OV519_R25_FORMAT
- OV519_R51_RESET1
- OV519_R54_EN_CLK1
- OV519_R57_SNAPSHOT
- OV534_OP_READ_2
- OV534_OP_WRITE_2
- OV534_OP_WRITE_3
- OV534_REG_ADDRESS
- OV534_REG_OPERATION
- OV534_REG_READ
- OV534_REG_STATUS
- OV534_REG_SUBADDR
- OV534_REG_WRITE
- OV5640_15_FPS
- OV5640_30_FPS
- OV5640_60_FPS
- OV5640_BIT_DIV
- OV5640_DEFAULT_SLAVE_ID
- OV5640_FMT_MUX_DITHER
- OV5640_FMT_MUX_RAW_CIP
- OV5640_FMT_MUX_RAW_DPC
- OV5640_FMT_MUX_RGB
- OV5640_FMT_MUX_SNR_RAW
- OV5640_FMT_MUX_YUV422
- OV5640_MIPI_DIV_PCLK
- OV5640_MIPI_DIV_SCLK
- OV5640_MODE_1080P_1920_1080
- OV5640_MODE_720P_1280_720
- OV5640_MODE_NTSC_720_480
- OV5640_MODE_PAL_720_576
- OV5640_MODE_QCIF_176_144
- OV5640_MODE_QSXGA_2592_1944
- OV5640_MODE_QVGA_320_240
- OV5640_MODE_VGA_640_480
- OV5640_MODE_XGA_1024_768
- OV5640_NUM_FRAMERATES
- OV5640_NUM_MODES
- OV5640_NUM_SUPPLIES
- OV5640_PCLK_ROOT_DIV
- OV5640_PLL_CTRL0_MIPI_MODE_8BIT
- OV5640_PLL_CTRL3_PLL_ROOT_DIV_2
- OV5640_PLL_MULT_MAX
- OV5640_PLL_MULT_MIN
- OV5640_PLL_PREDIV
- OV5640_PLL_ROOT_DIV
- OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS
- OV5640_REG_AEC_B50_STEP
- OV5640_REG_AEC_B60_STEP
- OV5640_REG_AEC_CTRL00
- OV5640_REG_AEC_CTRL0D
- OV5640_REG_AEC_CTRL0E
- OV5640_REG_AEC_CTRL0F
- OV5640_REG_AEC_CTRL10
- OV5640_REG_AEC_CTRL11
- OV5640_REG_AEC_CTRL1B
- OV5640_REG_AEC_CTRL1E
- OV5640_REG_AEC_CTRL1F
- OV5640_REG_AEC_PK_EXPOSURE_HI
- OV5640_REG_AEC_PK_EXPOSURE_LO
- OV5640_REG_AEC_PK_EXPOSURE_MED
- OV5640_REG_AEC_PK_MANUAL
- OV5640_REG_AEC_PK_REAL_GAIN
- OV5640_REG_AEC_PK_VTS
- OV5640_REG_AVG_READOUT
- OV5640_REG_AWB_B_GAIN
- OV5640_REG_AWB_G_GAIN
- OV5640_REG_AWB_MANUAL_CTRL
- OV5640_REG_AWB_R_GAIN
- OV5640_REG_CHIP_ID
- OV5640_REG_DEBUG_MODE
- OV5640_REG_FORMAT_CONTROL00
- OV5640_REG_FRAME_CTRL01
- OV5640_REG_HZ5060_CTRL00
- OV5640_REG_HZ5060_CTRL01
- OV5640_REG_IO_MIPI_CTRL00
- OV5640_REG_ISP_FORMAT_MUX_CTRL
- OV5640_REG_JPG_MODE_SELECT
- OV5640_REG_MIPI_CTRL00
- OV5640_REG_PAD_OUT
- OV5640_REG_PAD_OUTPUT00
- OV5640_REG_PAD_OUTPUT_ENABLE01
- OV5640_REG_PAD_OUTPUT_ENABLE02
- OV5640_REG_POLARITY_CTRL00
- OV5640_REG_PRE_ISP_TEST_SET1
- OV5640_REG_SCCB_SYS_CTRL1
- OV5640_REG_SC_PLL_CTRL0
- OV5640_REG_SC_PLL_CTRL1
- OV5640_REG_SC_PLL_CTRL2
- OV5640_REG_SC_PLL_CTRL3
- OV5640_REG_SDE_CTRL0
- OV5640_REG_SDE_CTRL1
- OV5640_REG_SDE_CTRL3
- OV5640_REG_SDE_CTRL4
- OV5640_REG_SDE_CTRL5
- OV5640_REG_SIGMADELTA_CTRL0C
- OV5640_REG_SLAVE_ID
- OV5640_REG_SYSTEM_CONTROL1
- OV5640_REG_SYS_CLOCK_ENABLE02
- OV5640_REG_SYS_CTRL0
- OV5640_REG_SYS_RESET02
- OV5640_REG_SYS_ROOT_DIVIDER
- OV5640_REG_TIMING_DVPHO
- OV5640_REG_TIMING_DVPVO
- OV5640_REG_TIMING_HTS
- OV5640_REG_TIMING_TC_REG20
- OV5640_REG_TIMING_TC_REG21
- OV5640_REG_TIMING_VTS
- OV5640_REG_VFIFO_HSIZE
- OV5640_REG_VFIFO_VSIZE
- OV5640_SCLK2X_ROOT_DIV
- OV5640_SCLK_ROOT_DIV
- OV5640_SYSDIV_MAX
- OV5640_SYSDIV_MIN
- OV5640_TEST_BAR
- OV5640_TEST_BAR_HOR_CHANGE
- OV5640_TEST_BAR_STANDARD
- OV5640_TEST_BAR_VERT_CHANGE_1
- OV5640_TEST_BAR_VERT_CHANGE_2
- OV5640_TEST_BLACK
- OV5640_TEST_ENABLE
- OV5640_TEST_RANDOM
- OV5640_TEST_ROLLING
- OV5640_TEST_SQUARE
- OV5640_TEST_SQUARE_BW
- OV5640_TEST_TRANSPARENT
- OV5640_XCLK_MAX
- OV5640_XCLK_MIN
- OV5642_DEFAULT_HEIGHT
- OV5642_DEFAULT_WIDTH
- OV5642_MAX_HEIGHT
- OV5642_MAX_WIDTH
- OV5642_SENSOR_SIZE_X
- OV5642_SENSOR_SIZE_Y
- OV5645_AEC_MANUAL_ENABLE
- OV5645_AEC_PK_MANUAL
- OV5645_AGC_MANUAL_ENABLE
- OV5645_AWB_MANUAL_CONTROL
- OV5645_AWB_MANUAL_ENABLE
- OV5645_CHIP_ID_HIGH
- OV5645_CHIP_ID_HIGH_BYTE
- OV5645_CHIP_ID_LOW
- OV5645_CHIP_ID_LOW_BYTE
- OV5645_IO_MIPI_CTRL00
- OV5645_ISP_VFLIP
- OV5645_MIPI_CTRL00
- OV5645_NUM_SUPPLIES
- OV5645_PAD_OUTPUT00
- OV5645_PRE_ISP_TEST_SETTING_1
- OV5645_SDE_SAT_U
- OV5645_SDE_SAT_V
- OV5645_SENSOR_MIRROR
- OV5645_SENSOR_VFLIP
- OV5645_SET_TEST_PATTERN
- OV5645_SYSTEM_CTRL0
- OV5645_SYSTEM_CTRL0_START
- OV5645_SYSTEM_CTRL0_STOP
- OV5645_TEST_PATTERN_ENABLE
- OV5645_TEST_PATTERN_MASK
- OV5645_TIMING_TC_REG20
- OV5645_TIMING_TC_REG21
- OV5647_COLUMN_START
- OV5647_COLUMN_START_DEF
- OV5647_COLUMN_START_MAX
- OV5647_COLUMN_START_MIN
- OV5647_REG_CHIPID_H
- OV5647_REG_CHIPID_L
- OV5647_REG_FRAME_OFF_NUMBER
- OV5647_REG_MIPI_CTRL00
- OV5647_REG_MIPI_CTRL14
- OV5647_ROW_START
- OV5647_ROW_START_DEF
- OV5647_ROW_START_MAX
- OV5647_ROW_START_MIN
- OV5647_SW_RESET
- OV5647_SW_STANDBY
- OV5647_WINDOW_HEIGHT
- OV5647_WINDOW_HEIGHT_DEF
- OV5647_WINDOW_HEIGHT_MAX
- OV5647_WINDOW_HEIGHT_MIN
- OV5647_WINDOW_WIDTH
- OV5647_WINDOW_WIDTH_DEF
- OV5647_WINDOW_WIDTH_MAX
- OV5647_WINDOW_WIDTH_MIN
- OV5670_CHIP_ID
- OV5670_DGTL_GAIN_DEFAULT
- OV5670_DGTL_GAIN_MAX
- OV5670_DGTL_GAIN_MIN
- OV5670_DGTL_GAIN_STEP
- OV5670_EXPOSURE_MIN
- OV5670_EXPOSURE_STEP
- OV5670_FIXED_PPL
- OV5670_LINK_FREQ_422MHZ
- OV5670_LINK_FREQ_422MHZ_INDEX
- OV5670_MODE_STANDBY
- OV5670_MODE_STREAMING
- OV5670_NUM_OF_SKIP_FRAMES
- OV5670_REG_ANALOG_GAIN
- OV5670_REG_B_DGTL_GAIN
- OV5670_REG_CHIP_ID
- OV5670_REG_EXPOSURE
- OV5670_REG_G_DGTL_GAIN
- OV5670_REG_HTS
- OV5670_REG_MODE_SELECT
- OV5670_REG_R_DGTL_GAIN
- OV5670_REG_SOFTWARE_RST
- OV5670_REG_TEST_PATTERN
- OV5670_REG_TEST_PATTERN_CTRL
- OV5670_REG_VALUE_08BIT
- OV5670_REG_VALUE_16BIT
- OV5670_REG_VALUE_24BIT
- OV5670_REG_VTS
- OV5670_SOFTWARE_RST
- OV5670_TEST_PATTERN_ENABLE
- OV5670_VTS_30FPS
- OV5670_VTS_MAX
- OV5675_ANAL_GAIN_MAX
- OV5675_ANAL_GAIN_MIN
- OV5675_ANAL_GAIN_STEP
- OV5675_CHIP_ID
- OV5675_DATA_LANES
- OV5675_DGTL_GAIN_DEFAULT
- OV5675_DGTL_GAIN_MAX
- OV5675_DGTL_GAIN_MIN
- OV5675_DGTL_GAIN_STEP
- OV5675_EXPOSURE_MAX_MARGIN
- OV5675_EXPOSURE_MIN
- OV5675_EXPOSURE_STEP
- OV5675_LINK_FREQ_450MHZ
- OV5675_LINK_FREQ_900MBPS
- OV5675_MCLK
- OV5675_MODE_STANDBY
- OV5675_MODE_STREAMING
- OV5675_REG_ANALOG_GAIN
- OV5675_REG_CHIP_ID
- OV5675_REG_EXPOSURE
- OV5675_REG_HTS
- OV5675_REG_MODE_SELECT
- OV5675_REG_MWB_B_GAIN
- OV5675_REG_MWB_G_GAIN
- OV5675_REG_MWB_R_GAIN
- OV5675_REG_TEST_PATTERN
- OV5675_REG_VALUE_08BIT
- OV5675_REG_VALUE_16BIT
- OV5675_REG_VALUE_24BIT
- OV5675_REG_VTS
- OV5675_RGB_DEPTH
- OV5675_SCLK
- OV5675_TEST_PATTERN_BAR_SHIFT
- OV5675_TEST_PATTERN_ENABLE
- OV5675_VTS_30FPS
- OV5675_VTS_30FPS_MIN
- OV5675_VTS_MAX
- OV5695_BITS_PER_SAMPLE
- OV5695_DIGI_GAIN_DEFAULT
- OV5695_DIGI_GAIN_H_SHIFT
- OV5695_DIGI_GAIN_L_MASK
- OV5695_DIGI_GAIN_MAX
- OV5695_DIGI_GAIN_MIN
- OV5695_DIGI_GAIN_STEP
- OV5695_EXPOSURE_MIN
- OV5695_EXPOSURE_STEP
- OV5695_LANES
- OV5695_LINK_FREQ_420MHZ
- OV5695_MODE_STREAMING
- OV5695_MODE_SW_STANDBY
- OV5695_NUM_SUPPLIES
- OV5695_PIXEL_RATE
- OV5695_REG_ANALOG_GAIN
- OV5695_REG_CHIP_ID
- OV5695_REG_CTRL_MODE
- OV5695_REG_DIGI_GAIN_H
- OV5695_REG_DIGI_GAIN_L
- OV5695_REG_EXPOSURE
- OV5695_REG_TEST_PATTERN
- OV5695_REG_VALUE_08BIT
- OV5695_REG_VALUE_16BIT
- OV5695_REG_VALUE_24BIT
- OV5695_REG_VTS
- OV5695_TEST_PATTERN_DISABLE
- OV5695_TEST_PATTERN_ENABLE
- OV5695_VTS_MAX
- OV5695_XVCLK_FREQ
- OV5_CMO
- OV5_DONATE_DEDICATE_CPU
- OV5_DRCONF_MEMORY
- OV5_DRC_INFO
- OV5_DRMEM_V2
- OV5_FEAT
- OV5_HASH_GTSE
- OV5_HASH_SEG_TBL
- OV5_HP_EVT
- OV5_INDX
- OV5_LARGE_PAGES
- OV5_LPAR
- OV5_MMU_DYNAMIC
- OV5_MMU_EITHER
- OV5_MMU_HASH
- OV5_MMU_RADIX
- OV5_MMU_SUPPORT
- OV5_MSI
- OV5_NMMU
- OV5_PFO_HW_842
- OV5_PFO_HW_ENCR
- OV5_PFO_HW_RNG
- OV5_PRRN
- OV5_RADIX_GTSE
- OV5_RESIZE_HPT
- OV5_SPLPAR
- OV5_SUB_PROCESSORS
- OV5_TYPE1_AFFINITY
- OV5_XCMO
- OV5_XIVE_EITHER
- OV5_XIVE_EXPLOIT
- OV5_XIVE_LEGACY
- OV5_XIVE_SUPPORT
- OV6650_MIDH
- OV6650_MIDL
- OV6650_PIDH
- OV6650_PIDL
- OV6_LINUX
- OV6xx0_SID
- OV7251_AEC_AGC_ADJ_0
- OV7251_AEC_AGC_ADJ_1
- OV7251_AEC_EXPO_0
- OV7251_AEC_EXPO_1
- OV7251_AEC_EXPO_2
- OV7251_CHIP_ID_HIGH
- OV7251_CHIP_ID_HIGH_BYTE
- OV7251_CHIP_ID_LOW
- OV7251_CHIP_ID_LOW_BYTE
- OV7251_PRE_ISP_00
- OV7251_PRE_ISP_00_TEST_PATTERN
- OV7251_SC_GP_IO_IN1
- OV7251_SC_MODE_SELECT
- OV7251_SC_MODE_SELECT_STREAMING
- OV7251_SC_MODE_SELECT_SW_STANDBY
- OV7251_TIMING_FORMAT1
- OV7251_TIMING_FORMAT1_VFLIP
- OV7251_TIMING_FORMAT2
- OV7251_TIMING_FORMAT2_MIRROR
- OV7610_REG_BLUE
- OV7610_REG_BRT
- OV7610_REG_CNT
- OV7610_REG_COM_C
- OV7610_REG_COM_I
- OV7610_REG_GAIN
- OV7610_REG_ID_HIGH
- OV7610_REG_ID_LOW
- OV7610_REG_RED
- OV7610_REG_SAT
- OV7660_ADC
- OV7660_AEB
- OV7660_AECH
- OV7660_AECHH
- OV7660_AEW
- OV7660_BAVE
- OV7660_BBIAS
- OV7660_BLUE_GAIN
- OV7660_BOS
- OV7660_CLKRC
- OV7660_COM1
- OV7660_COM10
- OV7660_COM12
- OV7660_COM13
- OV7660_COM2
- OV7660_COM3
- OV7660_COM4
- OV7660_COM5
- OV7660_COM6
- OV7660_COM7
- OV7660_COM8
- OV7660_COM9
- OV7660_DEFAULT_BLUE_GAIN
- OV7660_DEFAULT_EXPOSURE
- OV7660_DEFAULT_GAIN
- OV7660_DEFAULT_RED_GAIN
- OV7660_DEFAULT_SATURATION
- OV7660_GAIN
- OV7660_GBOS
- OV7660_GEAVE
- OV7660_GROS
- OV7660_GbBIAS
- OV7660_HREF
- OV7660_HSTART
- OV7660_HSTOP
- OV7660_HV
- OV7660_LAEC
- OV7660_LCC1
- OV7660_LCC2
- OV7660_LCC3
- OV7660_LCC4
- OV7660_LCC5
- OV7660_MIDH
- OV7660_MIDL
- OV7660_MVFP
- OV7660_MVFP_MIRROR
- OV7660_MVFP_VFLIP
- OV7660_OFON
- OV7660_PID
- OV7660_PSHFT
- OV7660_RAVE
- OV7660_RBIAS
- OV7660_RED_GAIN
- OV7660_REG_MVFP
- OV7660_ROS
- OV7660_RSVD16
- OV7660_RSVD29
- OV7660_RSVDA1
- OV7660_SENSOR
- OV7660_TSLB
- OV7660_VER
- OV7660_VPT
- OV7660_VREF
- OV7660_VSTART
- OV7660_VSTOP
- OV7670_COM11_EXP
- OV7670_COM11_HZAUTO
- OV7670_COM13_GAMMA
- OV7670_COM13_UVSAT
- OV7670_COM16_AWBGAIN
- OV7670_COM7_FMT_MASK
- OV7670_COM7_FMT_QVGA
- OV7670_COM7_FMT_VGA
- OV7670_COM7_RESET
- OV7670_COM8_AEC
- OV7670_COM8_AECSTEP
- OV7670_COM8_AGC
- OV7670_COM8_AWB
- OV7670_COM8_BFILT
- OV7670_COM8_FASTAEC
- OV7670_I2C_ADDR
- OV7670_MVFP_MIRROR
- OV7670_MVFP_VFLIP
- OV7670_R00_GAIN
- OV7670_R01_BLUE
- OV7670_R02_RED
- OV7670_R03_VREF
- OV7670_R04_COM1
- OV7670_R0C_COM3
- OV7670_R0D_COM4
- OV7670_R0E_COM5
- OV7670_R0F_COM6
- OV7670_R10_AECH
- OV7670_R11_CLKRC
- OV7670_R12_COM7
- OV7670_R13_COM8
- OV7670_R14_COM9
- OV7670_R15_COM10
- OV7670_R17_HSTART
- OV7670_R18_HSTOP
- OV7670_R19_VSTART
- OV7670_R1A_VSTOP
- OV7670_R1E_MVFP
- OV7670_R24_AEW
- OV7670_R25_AEB
- OV7670_R26_VPT
- OV7670_R32_HREF
- OV7670_R3A_TSLB
- OV7670_R3B_COM11
- OV7670_R3C_COM12
- OV7670_R3D_COM13
- OV7670_R3E_COM14
- OV7670_R3F_EDGE
- OV7670_R40_COM15
- OV7670_R41_COM16
- OV7670_R55_BRIGHT
- OV7670_R56_CONTRAS
- OV7670_R69_GFIX
- OV7670_R9F_HAECC1
- OV7670_RA0_HAECC2
- OV7670_RA5_BD50MAX
- OV7670_RA6_HAECC3
- OV7670_RA7_HAECC4
- OV7670_RA8_HAECC5
- OV7670_RA9_HAECC6
- OV7670_RAA_HAECC7
- OV7670_RAB_BD60MAX
- OV7720
- OV7725
- OV772X_AUTO_EDGECTRL
- OV772X_EDGE_LOWER_MASK
- OV772X_EDGE_STRENGTH_MASK
- OV772X_EDGE_THRESHOLD_MASK
- OV772X_EDGE_UPPER_MASK
- OV772X_FLAG_HFLIP
- OV772X_FLAG_VFLIP
- OV772X_MANUAL_EDGECTRL
- OV772X_MANUAL_EDGE_CTRL
- OV772X_MAX_HEIGHT
- OV772X_MAX_WIDTH
- OV7740_MAX_REGISTER
- OV7xx0_SID
- OV8610_REG_HUE
- OV8856_ANAL_GAIN_MAX
- OV8856_ANAL_GAIN_MIN
- OV8856_ANAL_GAIN_STEP
- OV8856_CHIP_ID
- OV8856_DATA_LANES
- OV8856_DGTL_GAIN_DEFAULT
- OV8856_DGTL_GAIN_MAX
- OV8856_DGTL_GAIN_MIN
- OV8856_DGTL_GAIN_STEP
- OV8856_EXPOSURE_MAX_MARGIN
- OV8856_EXPOSURE_MIN
- OV8856_EXPOSURE_STEP
- OV8856_LINK_FREQ_180MHZ
- OV8856_LINK_FREQ_360MBPS
- OV8856_LINK_FREQ_360MHZ
- OV8856_LINK_FREQ_720MBPS
- OV8856_MCLK
- OV8856_MODE_STANDBY
- OV8856_MODE_STREAMING
- OV8856_REG_ANALOG_GAIN
- OV8856_REG_CHIP_ID
- OV8856_REG_EXPOSURE
- OV8856_REG_HTS
- OV8856_REG_MODE_SELECT
- OV8856_REG_MWB_B_GAIN
- OV8856_REG_MWB_G_GAIN
- OV8856_REG_MWB_R_GAIN
- OV8856_REG_TEST_PATTERN
- OV8856_REG_VALUE_08BIT
- OV8856_REG_VALUE_16BIT
- OV8856_REG_VALUE_24BIT
- OV8856_REG_VTS
- OV8856_RGB_DEPTH
- OV8856_SCLK
- OV8856_TEST_PATTERN_BAR_SHIFT
- OV8856_TEST_PATTERN_ENABLE
- OV8856_VTS_MAX
- OV8xx0_SID
- OV9640_ACOM
- OV9640_ACOM_2X_ANALOG
- OV9640_ACOM_RSVD
- OV9640_ADC
- OV9640_ADVFH
- OV9640_ADVFL
- OV9640_AEB
- OV9640_AECH
- OV9640_AEW
- OV9640_ARBLM
- OV9640_BAVE
- OV9640_BBIAS
- OV9640_BLUE
- OV9640_BOS
- OV9640_CHLF
- OV9640_CLKRC
- OV9640_CLKRC_DIRECT
- OV9640_CLKRC_DIV
- OV9640_CLKRC_DPLL_EN
- OV9640_COM1
- OV9640_COM10
- OV9640_COM11
- OV9640_COM12
- OV9640_COM12_RSVD
- OV9640_COM12_YUV_AVG
- OV9640_COM13
- OV9640_COM13_GAMMA_NONE
- OV9640_COM13_GAMMA_RAW
- OV9640_COM13_GAMMA_Y
- OV9640_COM13_MATRIX_EN
- OV9640_COM13_RGB_AVG
- OV9640_COM13_YUV_DLY
- OV9640_COM13_Y_DELAY_EN
- OV9640_COM14
- OV9640_COM15
- OV9640_COM15_OR_00FF
- OV9640_COM15_OR_01FE
- OV9640_COM15_OR_10F0
- OV9640_COM15_RGB_555
- OV9640_COM15_RGB_565
- OV9640_COM15_RGB_NORM
- OV9640_COM16
- OV9640_COM16_RB_AVG
- OV9640_COM17
- OV9640_COM1_HREF_2SKIP
- OV9640_COM1_HREF_3SKIP
- OV9640_COM1_HREF_NOSKIP
- OV9640_COM1_QQFMT
- OV9640_COM2
- OV9640_COM2_SSM
- OV9640_COM3
- OV9640_COM3_VP
- OV9640_COM4
- OV9640_COM4_QQ_VP
- OV9640_COM4_RSVD
- OV9640_COM5
- OV9640_COM5_LONGEXP
- OV9640_COM5_SYSCLK
- OV9640_COM6
- OV9640_COM6_ADBLC_BIAS
- OV9640_COM6_ADBLC_OPTEN
- OV9640_COM6_FMT_RST
- OV9640_COM6_OPT_BLC
- OV9640_COM7
- OV9640_COM7_CIF
- OV9640_COM7_QCIF
- OV9640_COM7_QVGA
- OV9640_COM7_RAW_RGB
- OV9640_COM7_RGB
- OV9640_COM7_SCCB_RESET
- OV9640_COM7_VGA
- OV9640_COM8
- OV9640_COM9
- OV9640_DBLV
- OV9640_EDGE
- OV9640_EXHCH
- OV9640_EXHCL
- OV9640_GAIN
- OV9640_GBBIAS
- OV9640_GBOS
- OV9640_GEAVE
- OV9640_GROS
- OV9640_GSP
- OV9640_GST
- OV9640_HREF
- OV9640_HSTART
- OV9640_HSTOP
- OV9640_HSYEN
- OV9640_HSYST
- OV9640_HV
- OV9640_LAEC
- OV9640_LCC1
- OV9640_LCC2
- OV9640_LCC3
- OV9640_LCC4
- OV9640_LCC5
- OV9640_MANU
- OV9640_MANV
- OV9640_MBD
- OV9640_MIDH
- OV9640_MIDL
- OV9640_MTX1
- OV9640_MTX2
- OV9640_MTX3
- OV9640_MTX4
- OV9640_MTX5
- OV9640_MTX6
- OV9640_MTX7
- OV9640_MTX8
- OV9640_MTX9
- OV9640_MTXS
- OV9640_MVFP
- OV9640_MVFP_H
- OV9640_MVFP_V
- OV9640_OFON
- OV9640_PID
- OV9640_PSHFT
- OV9640_PSHFT_VAL
- OV9640_RAVE
- OV9640_RBIAS
- OV9640_RED
- OV9640_ROS
- OV9640_RSID
- OV9640_TSLB
- OV9640_TSLB_YUYV_UYVY
- OV9640_TSLB_YVYU_YUYV
- OV9640_V2
- OV9640_V3
- OV9640_VER
- OV9640_VFER
- OV9640_VPT
- OV9640_VSTART
- OV9640_VSTOP
- OV9640_YAVE
- OV9650_ACOM38
- OV9650_ACOMA8
- OV9650_ACOMA9
- OV9650_ADC
- OV9650_AEB
- OV9650_AECH
- OV9650_AECHM
- OV9650_AEC_EN
- OV9650_AEC_UNLIM_STEP_SIZE
- OV9650_AEW
- OV9650_AGC_EN
- OV9650_ARBLM
- OV9650_AWB_EN
- OV9650_BANDING
- OV9650_BAVE
- OV9650_BBIAS
- OV9650_BLUE
- OV9650_CHLF
- OV9650_CIF_SELECT
- OV9650_CLKRC
- OV9650_COM1
- OV9650_COM10
- OV9650_COM12
- OV9650_COM13
- OV9650_COM15
- OV9650_COM16
- OV9650_COM2
- OV9650_COM21
- OV9650_COM22
- OV9650_COM24
- OV9650_COM26
- OV9650_COM3
- OV9650_COM4
- OV9650_COM5
- OV9650_COM6
- OV9650_COM7
- OV9650_COM8
- OV9650_COM9
- OV9650_DBLC1
- OV9650_DBLV
- OV9650_DENOISE_ENABLE
- OV9650_FAST_AGC_AEC
- OV9650_GAIN
- OV9650_GEAVE
- OV9650_GbBIAS
- OV9650_Gr_COM
- OV9650_HFLIP
- OV9650_HREF
- OV9650_HSTART
- OV9650_HSTOP
- OV9650_HV
- OV9650_H_
- OV9650_ID
- OV9650_LCC1
- OV9650_LCC2
- OV9650_LCC3
- OV9650_LCC4
- OV9650_LCC5
- OV9650_LCCFB
- OV9650_LCCFR
- OV9650_LEFT_OFFSET
- OV9650_MVFP
- OV9650_OFON
- OV9650_OUTPUT_DRIVE_2X
- OV9650_PID
- OV9650_PSHFT
- OV9650_QCIF_SELECT
- OV9650_QVGA_SELECT
- OV9650_QVGA_VARIOPIXEL
- OV9650_RAW_RGB_SELECT
- OV9650_RBIAS
- OV9650_RED
- OV9650_REGISTER_RESET
- OV9650_RGB_SELECT
- OV9650_RSVD16
- OV9650_RSVD35
- OV9650_RSVD36
- OV9650_RSVD7
- OV9650_RSVD94
- OV9650_RSVD95
- OV9650_RSVD96
- OV9650_SENSOR
- OV9650_SLAM_MODE
- OV9650_SOFT_SLEEP
- OV9650_SYSTEM_CLK_SEL
- OV9650_TSLB
- OV9650_VARIOPIXEL
- OV9650_VER
- OV9650_VFLIP
- OV9650_VGA_SELECT
- OV9650_VPT
- OV9650_VREF
- OV9650_VSTOP
- OV9650_VSTRT
- OV9650_WHITE_PIXEL_ENABLE
- OV9650_WHITE_PIXEL_OPTION
- OV9652_ID
- OV965X_ID
- OV9740_AEC_3A1A
- OV9740_AEC_B50_STEP_HI
- OV9740_AEC_B50_STEP_LO
- OV9740_AEC_B60_STEP_HI
- OV9740_AEC_B60_STEP_LO
- OV9740_AEC_CTRL0D
- OV9740_AEC_CTRL0E
- OV9740_AEC_CTRL0F_WPT
- OV9740_AEC_CTRL10_BPT
- OV9740_AEC_CTRL1B_WPT2
- OV9740_AEC_CTRL1E_BPT2
- OV9740_AEC_ENABLE
- OV9740_AEC_HI_THRESHOLD
- OV9740_AEC_LO_THRESHOLD
- OV9740_AEC_MAXEXPO_50_H
- OV9740_AEC_MAXEXPO_50_L
- OV9740_AEC_MAXEXPO_60_H
- OV9740_AEC_MAXEXPO_60_L
- OV9740_ANALOG_CTRL01
- OV9740_ANALOG_CTRL02
- OV9740_ANALOG_CTRL03
- OV9740_ANALOG_CTRL04
- OV9740_ANALOG_CTRL10
- OV9740_ANALOG_CTRL12
- OV9740_ANALOG_CTRL15
- OV9740_ANALOG_CTRL20
- OV9740_ANALOG_CTRL21
- OV9740_ANALOG_CTRL22
- OV9740_ANALOG_CTRL30
- OV9740_ANALOG_CTRL31
- OV9740_ANALOG_CTRL32
- OV9740_ANALOG_CTRL33
- OV9740_AWB_ADV_CTRL01
- OV9740_AWB_ADV_CTRL02
- OV9740_AWB_ADV_CTRL03
- OV9740_AWB_ADV_CTRL04
- OV9740_AWB_ADV_CTRL05
- OV9740_AWB_ADV_CTRL06
- OV9740_AWB_ADV_CTRL07
- OV9740_AWB_ADV_CTRL08
- OV9740_AWB_ADV_CTRL09
- OV9740_AWB_ADV_CTRL10
- OV9740_AWB_ADV_CTRL11
- OV9740_AWB_CTRL00
- OV9740_AWB_CTRL01
- OV9740_AWB_CTRL02
- OV9740_AWB_CTRL03
- OV9740_AWB_CTRL0F
- OV9740_AWB_CTRL10
- OV9740_AWB_CTRL11
- OV9740_AWB_CTRL12
- OV9740_AWB_CTRL13
- OV9740_AWB_CTRL14
- OV9740_AWB_MANUAL_CTRL
- OV9740_BLC_AUTO_ENABLE
- OV9740_BLC_MODE
- OV9740_DVP_VSYNC_CTRL02
- OV9740_DVP_VSYNC_CTRL06
- OV9740_DVP_VSYNC_MODE
- OV9740_FRM_LENGTH_LN_HI
- OV9740_FRM_LENGTH_LN_LO
- OV9740_GAIN_CEILING_01
- OV9740_GAIN_CEILING_02
- OV9740_GRP_PARAM_HOLD
- OV9740_IMAGE_ORT
- OV9740_IO_CREL00
- OV9740_IO_CREL01
- OV9740_IO_CREL02
- OV9740_IO_OUTPUT_SEL01
- OV9740_IO_OUTPUT_SEL02
- OV9740_ISP_CTRL00
- OV9740_ISP_CTRL01
- OV9740_ISP_CTRL03
- OV9740_ISP_CTRL05
- OV9740_ISP_CTRL12
- OV9740_ISP_CTRL19
- OV9740_ISP_CTRL1A
- OV9740_ISP_CTRL1E
- OV9740_ISP_CTRL1F
- OV9740_ISP_CTRL20
- OV9740_ISP_CTRL21
- OV9740_LN_LENGTH_PCK_HI
- OV9740_LN_LENGTH_PCK_LO
- OV9740_MANUFACTURER_ID
- OV9740_MAX_HEIGHT
- OV9740_MAX_WIDTH
- OV9740_MIPI_3837
- OV9740_MIPI_CTRL00
- OV9740_MIPI_CTRL01
- OV9740_MIPI_CTRL03
- OV9740_MIPI_CTRL05
- OV9740_MIPI_CTRL_3012
- OV9740_MODEL_ID_HI
- OV9740_MODEL_ID_LO
- OV9740_MODE_SELECT
- OV9740_MSK_CORRUP_FM
- OV9740_PLL_CTRL3010
- OV9740_PLL_MODE_CTRL01
- OV9740_PLL_MULTIPLIER
- OV9740_PRE_PLL_CLK_DIV
- OV9740_REVISION_NUMBER
- OV9740_SC_CMMM_MIPI_CTR
- OV9740_SENSOR_CTRL03
- OV9740_SENSOR_CTRL04
- OV9740_SENSOR_CTRL05
- OV9740_SENSOR_CTRL07
- OV9740_SMIA_VERSION
- OV9740_SOFTWARE_RESET
- OV9740_TIMING_CTRL17
- OV9740_TIMING_CTRL19
- OV9740_TIMING_CTRL33
- OV9740_TIMING_CTRL35
- OV9740_VFIFO_CTRL00
- OV9740_VFIFO_RD_CTRL
- OV9740_VFIFO_READ_START_HI
- OV9740_VFIFO_READ_START_LO
- OV9740_VT_PIX_CLK_DIV
- OV9740_VT_SYS_CLK_DIV
- OV9740_X_ADDR_END_HI
- OV9740_X_ADDR_END_LO
- OV9740_X_ADDR_START_HI
- OV9740_X_ADDR_START_LO
- OV9740_X_OUTPUT_SIZE_HI
- OV9740_X_OUTPUT_SIZE_LO
- OV9740_Y_ADDR_END_HI
- OV9740_Y_ADDR_END_LO
- OV9740_Y_ADDR_START_HI
- OV9740_Y_ADDR_START_LO
- OV9740_Y_OUTPUT_SIZE_HI
- OV9740_Y_OUTPUT_SIZE_LO
- OVADD
- OVBUNIT_CLOCK_GATE_DISABLE
- OVCBIT
- OVCMON
- OVCN2_MARK
- OVCN_MARK
- OVCUNIT_CLOCK_GATE_DISABLE
- OVC_DOVCSTA
- OVC_OGAMC0
- OVC_OGAMC1
- OVC_OGAMC2
- OVC_OGAMC3
- OVC_OGAMC4
- OVC_OGAMC5
- OVC_OVADD
- OVERCOMMIT_ALWAYS
- OVERCOMMIT_GUESS
- OVERCOMMIT_NEVER
- OVERCURRENT
- OVERFLOW
- OVERFLOWED
- OVERFLOWEXCEPTION
- OVERFLOW_ADDR_MASK
- OVERFLOW_ADDR_SHIFT
- OVERFLOW_BIT
- OVERFLOW_BUFFER_SIZE
- OVERFLOW_CHECK
- OVERFLOW_CHECK_u64
- OVERFLOW_MS
- OVERFLOW_PROJID
- OVERFLOW_REG
- OVERFLOW_STACK_SIZE
- OVERFLOW_WAIT_COUNT
- OVERHEAT_INT_POLL_DELAY_MS
- OVERLAP
- OVERLAP_PIXELS
- OVERLAP_PIXELS_MASK
- OVERLAY
- OVERLAY1
- OVERLAY2
- OVERLAYFS_SUPER_MAGIC
- OVERLAY_ALPHA
- OVERLAY_ALPHA_PER_PIX
- OVERLAY_ATTR
- OVERLAY_BRIGHTNESS
- OVERLAY_CFG_VXLAN_PORT_UPDATE
- OVERLAY_COLOR_TEMPERATURE
- OVERLAY_CONTRAST
- OVERLAY_EOF_INT
- OVERLAY_EOF_INT_AK
- OVERLAY_EOF_INT_EN
- OVERLAY_EXCLUSIVE_HORZ
- OVERLAY_EXCLUSIVE_VERT
- OVERLAY_FEATURE_MAX
- OVERLAY_FEATURE_NVGRE
- OVERLAY_FEATURE_VXLAN
- OVERLAY_FLIP
- OVERLAY_FORMAT_RGB
- OVERLAY_FORMAT_YUV420_PLANAR
- OVERLAY_FORMAT_YUV422_PLANAR
- OVERLAY_FORMAT_YUV444_PACKED
- OVERLAY_FORMAT_YUV444_PLANAR
- OVERLAY_GAMMA
- OVERLAY_GAMMA_DISABLE
- OVERLAY_GAMMA_ENABLE
- OVERLAY_GRAPHICS_KEY_CLR
- OVERLAY_GRAPHICS_KEY_MSK
- OVERLAY_HUE
- OVERLAY_INFO
- OVERLAY_INFO_EXTERN
- OVERLAY_KEY_CNTL
- OVERLAY_NEEDS_PHYSICAL
- OVERLAY_OFFLOAD_DISABLE
- OVERLAY_OFFLOAD_ENABLE
- OVERLAY_OFFLOAD_ENABLE_P2
- OVERLAY_OFFLOAD_MAX
- OVERLAY_SATURATION
- OVERLAY_SCALE_CNTL
- OVERLAY_SCALE_INC
- OVERLAY_VIDEO_KEY_CLR
- OVERLAY_VIDEO_KEY_MSK
- OVERLAY_Y_X_END
- OVERLAY_Y_X_START
- OVERRIDE
- OVERRIDE_1
- OVERRIDE_2
- OVERRIDE_3
- OVERRIDE_4
- OVERRIDE_AUTO_PD_WAR
- OVERRIDE_BASE
- OVERRIDE_CGTT_DCEFCLK
- OVERRIDE_CGTT_DCEFCLK_NOOP
- OVERRIDE_CGTT_SCLK
- OVERRIDE_CGTT_SCLK_NOOP
- OVERRIDE_CMD_MASK
- OVERRIDE_CMD_SHIFT
- OVERRIDE_COS
- OVERRIDE_DATA_SHIFT
- OVERRIDE_DIRECT
- OVERRIDE_DONT_CHARGE
- OVERRIDE_HEIGHT
- OVERRIDE_IDPULLUP
- OVERRIDE_IDPULLUP_V0
- OVERRIDE_ITNL_TIMER
- OVERRIDE_LINE_OVR_EN
- OVERRIDE_MASTER
- OVERRIDE_NONE
- OVERRIDE_OFF
- OVERRIDE_SCLKEN_OVR
- OVERRIDE_SCLK_DOWN
- OVERRIDE_SCLK_OVR
- OVERRIDE_SCLK_UP
- OVERRIDE_SDATEN_OVR
- OVERRIDE_SDAT_DOWN
- OVERRIDE_SDAT_OVR
- OVERRIDE_SDAT_UP
- OVERRIDE_STRIDE
- OVERRIDE_WIDTH
- OVERRUN
- OVERRUN_ERROR_THRESHOLD
- OVERRUN_IE
- OVERRUN_IRQ_EN
- OVERRUN_UNDERRUN_SUPPORTED_BIT
- OVERWRITE
- OVERWRITE_RT_REG
- OVER_RUN
- OVER_TEMP_FLAG
- OVER_WRITE
- OVF
- OVFLW_CTRL
- OVFL_BIT
- OVFUNIT_CLOCK_GATE_DISABLE
- OVFX2_BULK_SIZE
- OVFX2_I2C_ADDR
- OVHUNIT_CLOCK_GATE_DISABLE
- OVL0_MOUT_EN_COLOR0
- OVL1C1
- OVL1C2
- OVL1_MOUT_EN_COLOR1
- OVL2C1
- OVL2C2
- OVL2C2_PFOR
- OVLAN_BITWIDTH
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK
- OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT
- OVLUNIT_CLOCK_GATE_DISABLE
- OVLYADR_MASK
- OVLYBUFADR_MASK
- OVLYCSEQ
- OVLYDMAACT
- OVLYDMAADR
- OVLYDMACNT
- OVLYDMACNT_MASK
- OVLYDMACTL
- OVLYDMADONE
- OVLYDOMAIN0
- OVLYDOMAIN1
- OVLYERR
- OVLYERRSTAT_MASK
- OVLYHALTERR
- OVLYLSEQ_MASK
- OVLY_OFST
- OVL_CATTR
- OVL_CLONE
- OVL_COLOR_SPACE_RGB
- OVL_COLOR_SPACE_UNKNOWN
- OVL_COLOR_SPACE_YUV601
- OVL_COLOR_SPACE_YUV709
- OVL_CONST_INO
- OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK
- OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT
- OVL_CONTROL1__OVL_ARRAY_MODE_MASK
- OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT
- OVL_CONTROL1__OVL_BANK_HEIGHT_MASK
- OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT
- OVL_CONTROL1__OVL_BANK_WIDTH_MASK
- OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT
- OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK
- OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT
- OVL_CONTROL1__OVL_DEPTH_MASK
- OVL_CONTROL1__OVL_DEPTH__SHIFT
- OVL_CONTROL1__OVL_FORMAT_MASK
- OVL_CONTROL1__OVL_FORMAT__SHIFT
- OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK
- OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT
- OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK
- OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT
- OVL_CONTROL1__OVL_NUM_BANKS_MASK
- OVL_CONTROL1__OVL_NUM_BANKS__SHIFT
- OVL_CONTROL1__OVL_PIPE_CONFIG_MASK
- OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT
- OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK
- OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT
- OVL_CONTROL1__OVL_TILE_SPLIT_MASK
- OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT
- OVL_CONTROL1__OVL_Z_MASK
- OVL_CONTROL1__OVL_Z__SHIFT
- OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK
- OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT
- OVL_CON_AEN
- OVL_CON_ALPHA
- OVL_CON_BYTE_SWAP
- OVL_CON_CLRFMT_ARGB8888
- OVL_CON_CLRFMT_RGB
- OVL_CON_CLRFMT_RGB565
- OVL_CON_CLRFMT_RGB888
- OVL_CON_CLRFMT_RGBA8888
- OVL_CON_CLRFMT_UYVY
- OVL_CON_CLRFMT_YUYV
- OVL_CON_MTX_YUV_TO_RGB
- OVL_COPY
- OVL_COPY_UP_CHUNK_SIZE
- OVL_DEDUPE
- OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK
- OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT
- OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK
- OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT
- OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK
- OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT
- OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK
- OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT
- OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK
- OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT
- OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK
- OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT
- OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK
- OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
- OVL_E
- OVL_ENABLE__OVLSCL_EN_MASK
- OVL_ENABLE__OVLSCL_EN__SHIFT
- OVL_ENABLE__OVL_ENABLE_MASK
- OVL_ENABLE__OVL_ENABLE__SHIFT
- OVL_END__OVL_X_END_MASK
- OVL_END__OVL_X_END__SHIFT
- OVL_END__OVL_Y_END_MASK
- OVL_END__OVL_Y_END__SHIFT
- OVL_E_CONNECTED
- OVL_E_OPAQUE
- OVL_E_UPPER_ALIAS
- OVL_FH_FLAG_ALL
- OVL_FH_FLAG_ANY_ENDIAN
- OVL_FH_FLAG_BIG_ENDIAN
- OVL_FH_FLAG_CPU_ENDIAN
- OVL_FH_FLAG_PATH_UPPER
- OVL_FH_MAGIC
- OVL_FH_VERSION
- OVL_FILEID
- OVL_FME_CPL_INT
- OVL_I
- OVL_IMPURE
- OVL_INDEX
- OVL_INDEXDIR_NAME
- OVL_MAX_NESTING
- OVL_MAX_STACK
- OVL_MOUT_EN_RDMA
- OVL_NLINK_ADD_UPPER
- OVL_PITCH__OVL_PITCH_MASK
- OVL_PITCH__OVL_PITCH__SHIFT
- OVL_RDMA_MEM_GMC
- OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
- OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
- OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK
- OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT
- OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK
- OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT
- OVL_SETFL_MASK
- OVL_START__OVL_X_START_MASK
- OVL_START__OVL_X_START__SHIFT
- OVL_START__OVL_Y_START_MASK
- OVL_START__OVL_Y_START__SHIFT
- OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK
- OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT
- OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK
- OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK
- OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT
- OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK
- OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
- OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK
- OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT
- OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK
- OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT
- OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK
- OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT
- OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK
- OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT
- OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK
- OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT
- OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK
- OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT
- OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK
- OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT
- OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK
- OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT
- OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK
- OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT
- OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK
- OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT
- OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK
- OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT
- OVL_TYPE_MERGE
- OVL_TYPE_ORIGIN
- OVL_TYPE_UPPER
- OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK
- OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT
- OVL_UPDATE__OVL_UPDATE_LOCK_MASK
- OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT
- OVL_UPDATE__OVL_UPDATE_PENDING_MASK
- OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT
- OVL_UPDATE__OVL_UPDATE_TAKEN_MASK
- OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT
- OVL_UPPERDATA
- OVL_WHITEOUTS
- OVL_WORKDIR_NAME
- OVL_XATTR_IMPURE
- OVL_XATTR_METACOPY
- OVL_XATTR_NLINK
- OVL_XATTR_OPAQUE
- OVL_XATTR_ORIGIN
- OVL_XATTR_PREFIX
- OVL_XATTR_REDIRECT
- OVL_XATTR_UPPER
- OVL_XINO_AUTO
- OVL_XINO_OFF
- OVL_XINO_ON
- OVLxC1_BPP
- OVLxC1_LPO
- OVLxC1_OEN
- OVLxC1_PPL
- OVLxC2_XPOS
- OVLxC2_YPOS
- OVOADDR
- OVOCLRC1
- OVOCLRCO
- OVOCMD
- OVOCONF
- OVOSTRIDE
- OVR2_CLR
- OVR2_WID_LEFT_RIGHT
- OVR2_WID_TOP_BOTTOM
- OVRACT
- OVRCR
- OVRCRE
- OVRFLOW_IEN
- OVRFLOW_INT
- OVRLD_CTRL
- OVRL_BLEND_MODE
- OVRL_PIX_FORMAT
- OVRL_SRC_DEST
- OVRN
- OVRUN
- OVRUNIT_CLOCK_GATE_DISABLE
- OVR_CLR
- OVR_ELM
- OVR_LBL
- OVR_MODE_SPARE_0
- OVR_MODE_SPARE_0_MASK
- OVR_MODE_SPARE_0_SHIFT
- OVR_MODE_SPARE_1
- OVR_MODE_SPARE_1_MASK
- OVR_MODE_SPARE_1_SHIFT
- OVR_VAL_SPARE_0
- OVR_VAL_SPARE_0_MASK
- OVR_VAL_SPARE_0_SHIFT
- OVR_VAL_SPARE_1
- OVR_VAL_SPARE_1_MASK
- OVR_VAL_SPARE_1_SHIFT
- OVR_WID_LEFT_RIGHT
- OVR_WID_TOP_BOTTOM
- OVSDLY
- OVSEND
- OVSP_LOCAL
- OVS_ACTION_ATTR_CHECK_PKT_LEN
- OVS_ACTION_ATTR_CLONE
- OVS_ACTION_ATTR_CT
- OVS_ACTION_ATTR_CT_CLEAR
- OVS_ACTION_ATTR_HASH
- OVS_ACTION_ATTR_MAX
- OVS_ACTION_ATTR_METER
- OVS_ACTION_ATTR_OUTPUT
- OVS_ACTION_ATTR_POP_ETH
- OVS_ACTION_ATTR_POP_MPLS
- OVS_ACTION_ATTR_POP_NSH
- OVS_ACTION_ATTR_POP_VLAN
- OVS_ACTION_ATTR_PUSH_ETH
- OVS_ACTION_ATTR_PUSH_MPLS
- OVS_ACTION_ATTR_PUSH_NSH
- OVS_ACTION_ATTR_PUSH_VLAN
- OVS_ACTION_ATTR_RECIRC
- OVS_ACTION_ATTR_SAMPLE
- OVS_ACTION_ATTR_SET
- OVS_ACTION_ATTR_SET_MASKED
- OVS_ACTION_ATTR_SET_TO_MASKED
- OVS_ACTION_ATTR_TRUNC
- OVS_ACTION_ATTR_UNSPEC
- OVS_ACTION_ATTR_USERSPACE
- OVS_ATTR_NESTED
- OVS_ATTR_VARIABLE
- OVS_BAND_ATTR_BURST
- OVS_BAND_ATTR_MAX
- OVS_BAND_ATTR_RATE
- OVS_BAND_ATTR_STATS
- OVS_BAND_ATTR_TYPE
- OVS_BAND_ATTR_UNSPEC
- OVS_CB
- OVS_CHECK_PKT_LEN_ATTR_ACTIONS_IF_GREATER
- OVS_CHECK_PKT_LEN_ATTR_ACTIONS_IF_LESS_EQUAL
- OVS_CHECK_PKT_LEN_ATTR_ARG
- OVS_CHECK_PKT_LEN_ATTR_MAX
- OVS_CHECK_PKT_LEN_ATTR_PKT_LEN
- OVS_CHECK_PKT_LEN_ATTR_UNSPEC
- OVS_CLONE_ATTR_EXEC
- OVS_CONNTRACK_H
- OVS_CS_F_DST_NAT
- OVS_CS_F_ESTABLISHED
- OVS_CS_F_INVALID
- OVS_CS_F_NAT_MASK
- OVS_CS_F_NEW
- OVS_CS_F_RELATED
- OVS_CS_F_REPLY_DIR
- OVS_CS_F_SRC_NAT
- OVS_CS_F_TRACKED
- OVS_CT_ATTR_COMMIT
- OVS_CT_ATTR_EVENTMASK
- OVS_CT_ATTR_FORCE_COMMIT
- OVS_CT_ATTR_HELPER
- OVS_CT_ATTR_LABELS
- OVS_CT_ATTR_MARK
- OVS_CT_ATTR_MAX
- OVS_CT_ATTR_NAT
- OVS_CT_ATTR_TIMEOUT
- OVS_CT_ATTR_UNSPEC
- OVS_CT_ATTR_ZONE
- OVS_CT_DST_NAT
- OVS_CT_LABELS_LEN
- OVS_CT_LABELS_LEN_32
- OVS_CT_LIMIT_ATTR_MAX
- OVS_CT_LIMIT_ATTR_UNSPEC
- OVS_CT_LIMIT_ATTR_ZONE_LIMIT
- OVS_CT_LIMIT_CMD_DEL
- OVS_CT_LIMIT_CMD_GET
- OVS_CT_LIMIT_CMD_SET
- OVS_CT_LIMIT_CMD_UNSPEC
- OVS_CT_LIMIT_DEFAULT
- OVS_CT_LIMIT_FAMILY
- OVS_CT_LIMIT_MCGROUP
- OVS_CT_LIMIT_UNLIMITED
- OVS_CT_LIMIT_VERSION
- OVS_CT_NAT
- OVS_CT_SRC_NAT
- OVS_DATAPATH_FAMILY
- OVS_DATAPATH_MCGROUP
- OVS_DATAPATH_VERSION
- OVS_DEFERRED_ACTION_THRESHOLD
- OVS_DP_ATTR_MAX
- OVS_DP_ATTR_MEGAFLOW_STATS
- OVS_DP_ATTR_NAME
- OVS_DP_ATTR_PAD
- OVS_DP_ATTR_STATS
- OVS_DP_ATTR_UNSPEC
- OVS_DP_ATTR_UPCALL_PID
- OVS_DP_ATTR_USER_FEATURES
- OVS_DP_CMD_DEL
- OVS_DP_CMD_GET
- OVS_DP_CMD_NEW
- OVS_DP_CMD_SET
- OVS_DP_CMD_UNSPEC
- OVS_DP_F_TC_RECIRC_SHARING
- OVS_DP_F_UNALIGNED
- OVS_DP_F_VPORT_PIDS
- OVS_DP_VER_FEATURES
- OVS_FLOW_ATTR_ACTIONS
- OVS_FLOW_ATTR_CLEAR
- OVS_FLOW_ATTR_KEY
- OVS_FLOW_ATTR_MASK
- OVS_FLOW_ATTR_MAX
- OVS_FLOW_ATTR_PAD
- OVS_FLOW_ATTR_PROBE
- OVS_FLOW_ATTR_STATS
- OVS_FLOW_ATTR_TCP_FLAGS
- OVS_FLOW_ATTR_UFID
- OVS_FLOW_ATTR_UFID_FLAGS
- OVS_FLOW_ATTR_UNSPEC
- OVS_FLOW_ATTR_USED
- OVS_FLOW_CMD_DEL
- OVS_FLOW_CMD_GET
- OVS_FLOW_CMD_NEW
- OVS_FLOW_CMD_SET
- OVS_FLOW_CMD_UNSPEC
- OVS_FLOW_FAMILY
- OVS_FLOW_MCGROUP
- OVS_FLOW_VERSION
- OVS_FRAG_TYPE_FIRST
- OVS_FRAG_TYPE_LATER
- OVS_FRAG_TYPE_MAX
- OVS_FRAG_TYPE_NONE
- OVS_HASH_ALG_L4
- OVS_KEY_ATTR_ARP
- OVS_KEY_ATTR_CT_LABELS
- OVS_KEY_ATTR_CT_MARK
- OVS_KEY_ATTR_CT_ORIG_TUPLE_IPV4
- OVS_KEY_ATTR_CT_ORIG_TUPLE_IPV6
- OVS_KEY_ATTR_CT_STATE
- OVS_KEY_ATTR_CT_ZONE
- OVS_KEY_ATTR_DP_HASH
- OVS_KEY_ATTR_ENCAP
- OVS_KEY_ATTR_ETHERNET
- OVS_KEY_ATTR_ETHERTYPE
- OVS_KEY_ATTR_ICMP
- OVS_KEY_ATTR_ICMPV6
- OVS_KEY_ATTR_IN_PORT
- OVS_KEY_ATTR_IPV4
- OVS_KEY_ATTR_IPV6
- OVS_KEY_ATTR_MAX
- OVS_KEY_ATTR_MPLS
- OVS_KEY_ATTR_ND
- OVS_KEY_ATTR_NSH
- OVS_KEY_ATTR_PRIORITY
- OVS_KEY_ATTR_RECIRC_ID
- OVS_KEY_ATTR_SCTP
- OVS_KEY_ATTR_SKB_MARK
- OVS_KEY_ATTR_TCP
- OVS_KEY_ATTR_TCP_FLAGS
- OVS_KEY_ATTR_TUNNEL
- OVS_KEY_ATTR_TUNNEL_INFO
- OVS_KEY_ATTR_UDP
- OVS_KEY_ATTR_UNSPEC
- OVS_KEY_ATTR_VLAN
- OVS_MASKED
- OVS_METER_ATTR_BANDS
- OVS_METER_ATTR_CLEAR
- OVS_METER_ATTR_ID
- OVS_METER_ATTR_KBPS
- OVS_METER_ATTR_MAX
- OVS_METER_ATTR_MAX_BANDS
- OVS_METER_ATTR_MAX_METERS
- OVS_METER_ATTR_PAD
- OVS_METER_ATTR_STATS
- OVS_METER_ATTR_UNSPEC
- OVS_METER_ATTR_USED
- OVS_METER_BAND_TYPE_DROP
- OVS_METER_BAND_TYPE_MAX
- OVS_METER_BAND_TYPE_UNSPEC
- OVS_METER_CMD_DEL
- OVS_METER_CMD_FEATURES
- OVS_METER_CMD_GET
- OVS_METER_CMD_SET
- OVS_METER_CMD_UNSPEC
- OVS_METER_FAMILY
- OVS_METER_MCGROUP
- OVS_METER_VERSION
- OVS_NAT_ATTR_DST
- OVS_NAT_ATTR_IP_MAX
- OVS_NAT_ATTR_IP_MIN
- OVS_NAT_ATTR_MAX
- OVS_NAT_ATTR_PERSISTENT
- OVS_NAT_ATTR_PROTO_HASH
- OVS_NAT_ATTR_PROTO_MAX
- OVS_NAT_ATTR_PROTO_MIN
- OVS_NAT_ATTR_PROTO_RANDOM
- OVS_NAT_ATTR_SRC
- OVS_NAT_ATTR_UNSPEC
- OVS_NLERR
- OVS_NSH_KEY_ATTR_BASE
- OVS_NSH_KEY_ATTR_MAX
- OVS_NSH_KEY_ATTR_MD1
- OVS_NSH_KEY_ATTR_MD2
- OVS_NSH_KEY_ATTR_UNSPEC
- OVS_PACKET_ATTR_ACTIONS
- OVS_PACKET_ATTR_EGRESS_TUN_KEY
- OVS_PACKET_ATTR_KEY
- OVS_PACKET_ATTR_LEN
- OVS_PACKET_ATTR_MAX
- OVS_PACKET_ATTR_MRU
- OVS_PACKET_ATTR_PACKET
- OVS_PACKET_ATTR_PROBE
- OVS_PACKET_ATTR_UNSPEC
- OVS_PACKET_ATTR_UNUSED1
- OVS_PACKET_ATTR_UNUSED2
- OVS_PACKET_ATTR_USERDATA
- OVS_PACKET_CMD_ACTION
- OVS_PACKET_CMD_EXECUTE
- OVS_PACKET_CMD_MISS
- OVS_PACKET_CMD_UNSPEC
- OVS_PACKET_FAMILY
- OVS_PACKET_VERSION
- OVS_RECURSION_LIMIT
- OVS_SAMPLE_ATTR_ACTIONS
- OVS_SAMPLE_ATTR_ARG
- OVS_SAMPLE_ATTR_MAX
- OVS_SAMPLE_ATTR_PROBABILITY
- OVS_SAMPLE_ATTR_UNSPEC
- OVS_SET_MASKED
- OVS_SW_FLOW_KEY_METADATA_SIZE
- OVS_TUNNEL_ATTR_DST_PORT
- OVS_TUNNEL_ATTR_EXTENSION
- OVS_TUNNEL_ATTR_MAX
- OVS_TUNNEL_ATTR_UNSPEC
- OVS_TUNNEL_KEY_ATTR_CSUM
- OVS_TUNNEL_KEY_ATTR_DONT_FRAGMENT
- OVS_TUNNEL_KEY_ATTR_ERSPAN_OPTS
- OVS_TUNNEL_KEY_ATTR_GENEVE_OPTS
- OVS_TUNNEL_KEY_ATTR_ID
- OVS_TUNNEL_KEY_ATTR_IPV4_DST
- OVS_TUNNEL_KEY_ATTR_IPV4_INFO_BRIDGE
- OVS_TUNNEL_KEY_ATTR_IPV4_SRC
- OVS_TUNNEL_KEY_ATTR_IPV6_DST
- OVS_TUNNEL_KEY_ATTR_IPV6_SRC
- OVS_TUNNEL_KEY_ATTR_MAX
- OVS_TUNNEL_KEY_ATTR_OAM
- OVS_TUNNEL_KEY_ATTR_PAD
- OVS_TUNNEL_KEY_ATTR_TOS
- OVS_TUNNEL_KEY_ATTR_TP_DST
- OVS_TUNNEL_KEY_ATTR_TP_SRC
- OVS_TUNNEL_KEY_ATTR_TTL
- OVS_TUNNEL_KEY_ATTR_VXLAN_OPTS
- OVS_UFID_F_OMIT_ACTIONS
- OVS_UFID_F_OMIT_KEY
- OVS_UFID_F_OMIT_MASK
- OVS_USERSPACE_ATTR_ACTIONS
- OVS_USERSPACE_ATTR_EGRESS_TUN_PORT
- OVS_USERSPACE_ATTR_MAX
- OVS_USERSPACE_ATTR_PID
- OVS_USERSPACE_ATTR_UNSPEC
- OVS_USERSPACE_ATTR_USERDATA
- OVS_VPORT_ATTR_IFINDEX
- OVS_VPORT_ATTR_MAX
- OVS_VPORT_ATTR_NAME
- OVS_VPORT_ATTR_NETNSID
- OVS_VPORT_ATTR_OPTIONS
- OVS_VPORT_ATTR_PAD
- OVS_VPORT_ATTR_PORT_NO
- OVS_VPORT_ATTR_STATS
- OVS_VPORT_ATTR_TYPE
- OVS_VPORT_ATTR_UNSPEC
- OVS_VPORT_ATTR_UPCALL_PID
- OVS_VPORT_CMD_DEL
- OVS_VPORT_CMD_GET
- OVS_VPORT_CMD_NEW
- OVS_VPORT_CMD_SET
- OVS_VPORT_CMD_UNSPEC
- OVS_VPORT_FAMILY
- OVS_VPORT_MCGROUP
- OVS_VPORT_TYPE_GENEVE
- OVS_VPORT_TYPE_GRE
- OVS_VPORT_TYPE_INTERNAL
- OVS_VPORT_TYPE_MAX
- OVS_VPORT_TYPE_NETDEV
- OVS_VPORT_TYPE_UNSPEC
- OVS_VPORT_TYPE_VXLAN
- OVS_VPORT_VERSION
- OVS_VXLAN_EXT_GBP
- OVS_VXLAN_EXT_MAX
- OVS_VXLAN_EXT_UNSPEC
- OVS_ZONE_LIMIT_DEFAULT_ZONE
- OVTEMP_AUTORECOVER
- OVT_CFG_SEL
- OVUUNIT_CLOCK_GATE_DISABLE
- OV_CESSATION_POLICY
- OV_C_OFFSET
- OV_DOVASTA
- OV_HIRES_SID
- OV_IGNORE
- OV_OGAMC0
- OV_OGAMC1
- OV_OGAMC2
- OV_OGAMC3
- OV_OGAMC4
- OV_OGAMC5
- OV_OVADD
- OV_PIPE_A
- OV_PIPE_C
- OV_PIPE_SELECT
- OV_PIPE_SELECT_POS
- OWCOLL
- OWER
- OWER_WME
- OWL_COMP_DIV
- OWL_COMP_DIV_FIXED
- OWL_COMP_FACTOR
- OWL_COMP_FIXED_FACTOR
- OWL_COMP_PASS
- OWL_CPU1_ADDR
- OWL_CPU1_FLAG
- OWL_CPUx_FLAG_BOOT
- OWL_DIVIDER
- OWL_DIVIDER_HW
- OWL_DMAX_CHAINED_CTL
- OWL_DMAX_CONSTANT
- OWL_DMAX_CURRENT_DESCRIPTOR_NUM
- OWL_DMAX_CURRENT_DESTINATION_POINTER
- OWL_DMAX_CURRENT_SOURCE_POINTER
- OWL_DMAX_DESTINATION
- OWL_DMAX_DESTINATION_STRIDE
- OWL_DMAX_FRAME_CNT
- OWL_DMAX_FRAME_LEN
- OWL_DMAX_INT_CTL
- OWL_DMAX_INT_STATUS
- OWL_DMAX_LINKLIST_CTL
- OWL_DMAX_MODE
- OWL_DMAX_NEXT_DESCRIPTOR
- OWL_DMAX_PAUSE
- OWL_DMAX_REMAIN_CNT
- OWL_DMAX_REMAIN_FRAME_CNT
- OWL_DMAX_SOURCE
- OWL_DMAX_SOURCE_STRIDE
- OWL_DMAX_START
- OWL_DMA_CHAN_BASE
- OWL_DMA_DBGSEL
- OWL_DMA_FRAME_MAX_LENGTH
- OWL_DMA_IDLE_STAT
- OWL_DMA_INTCTL_BLOCK
- OWL_DMA_INTCTL_FRAME
- OWL_DMA_INTCTL_HALF_FRAME
- OWL_DMA_INTCTL_LAST_FRAME
- OWL_DMA_INTCTL_SUPER_BLOCK
- OWL_DMA_INTSTAT_BLOCK
- OWL_DMA_INTSTAT_FRAME
- OWL_DMA_INTSTAT_HALF_FRAME
- OWL_DMA_INTSTAT_LAST_FRAME
- OWL_DMA_INTSTAT_SUPER_BLOCK
- OWL_DMA_IRQ_EN0
- OWL_DMA_IRQ_EN1
- OWL_DMA_IRQ_EN2
- OWL_DMA_IRQ_EN3
- OWL_DMA_IRQ_PD0
- OWL_DMA_IRQ_PD1
- OWL_DMA_IRQ_PD2
- OWL_DMA_IRQ_PD3
- OWL_DMA_LLC_DAV
- OWL_DMA_LLC_DAV_INC
- OWL_DMA_LLC_DAV_LOAD_NEXT
- OWL_DMA_LLC_DAV_LOAD_PREV
- OWL_DMA_LLC_SAV
- OWL_DMA_LLC_SAV_INC
- OWL_DMA_LLC_SAV_LOAD_NEXT
- OWL_DMA_LLC_SAV_LOAD_PREV
- OWL_DMA_LLC_SUSPEND
- OWL_DMA_MODE_CB
- OWL_DMA_MODE_CFE
- OWL_DMA_MODE_CME
- OWL_DMA_MODE_DAM
- OWL_DMA_MODE_DAM_CONST
- OWL_DMA_MODE_DAM_INC
- OWL_DMA_MODE_DAM_STRIDE
- OWL_DMA_MODE_DT
- OWL_DMA_MODE_DT_DCU
- OWL_DMA_MODE_DT_DEV
- OWL_DMA_MODE_DT_SRAM
- OWL_DMA_MODE_LME
- OWL_DMA_MODE_NDDBW
- OWL_DMA_MODE_NDDBW_32BIT
- OWL_DMA_MODE_NDDBW_8BIT
- OWL_DMA_MODE_PW
- OWL_DMA_MODE_SAM
- OWL_DMA_MODE_SAM_CONST
- OWL_DMA_MODE_SAM_INC
- OWL_DMA_MODE_SAM_STRIDE
- OWL_DMA_MODE_ST
- OWL_DMA_MODE_ST_DCU
- OWL_DMA_MODE_ST_DEV
- OWL_DMA_MODE_ST_SRAM
- OWL_DMA_MODE_TS
- OWL_DMA_NIC_QOS
- OWL_DMA_SECURE_ACCESS_CTL
- OWL_FACTOR
- OWL_FACTOR_HW
- OWL_FIX_FACT
- OWL_GATE
- OWL_GATE_HW
- OWL_GATE_NO_PARENT
- OWL_GPIO_CTLR_ENABLE
- OWL_GPIO_CTLR_PENDING
- OWL_GPIO_CTLR_SAMPLE_CLK_24M
- OWL_GPIO_INT_EDGE_FALLING
- OWL_GPIO_INT_EDGE_RISING
- OWL_GPIO_INT_LEVEL_HIGH
- OWL_GPIO_INT_LEVEL_LOW
- OWL_GPIO_INT_MASK
- OWL_GPIO_PORT
- OWL_GPIO_PORT_A
- OWL_GPIO_PORT_B
- OWL_GPIO_PORT_C
- OWL_GPIO_PORT_D
- OWL_GPIO_PORT_E
- OWL_GPIO_PORT_F
- OWL_I2C_CMD_AS
- OWL_I2C_CMD_DE
- OWL_I2C_CMD_MSS
- OWL_I2C_CMD_NS
- OWL_I2C_CMD_RBE
- OWL_I2C_CMD_SAS
- OWL_I2C_CMD_SBE
- OWL_I2C_CMD_SE
- OWL_I2C_CMD_SECL
- OWL_I2C_CMD_WRS
- OWL_I2C_CTL_AE
- OWL_I2C_CTL_EN
- OWL_I2C_CTL_GBCC
- OWL_I2C_CTL_GBCC_NONE
- OWL_I2C_CTL_GBCC_RSTART
- OWL_I2C_CTL_GBCC_START
- OWL_I2C_CTL_GBCC_STOP
- OWL_I2C_CTL_IRQE
- OWL_I2C_CTL_RB
- OWL_I2C_CTL_SHSM
- OWL_I2C_DEF_SPEED_HZ
- OWL_I2C_DIV_FACTOR
- OWL_I2C_FIFOCTL_NIB
- OWL_I2C_FIFOCTL_RFR
- OWL_I2C_FIFOCTL_TFR
- OWL_I2C_FIFOSTAT_RFD
- OWL_I2C_FIFOSTAT_RFE
- OWL_I2C_FIFOSTAT_RNB
- OWL_I2C_FIFOSTAT_TFD
- OWL_I2C_FIFOSTAT_TFF
- OWL_I2C_MAX_RETRIES
- OWL_I2C_MAX_SPEED_HZ
- OWL_I2C_REG_ADDR
- OWL_I2C_REG_CLKDIV
- OWL_I2C_REG_CMD
- OWL_I2C_REG_CTL
- OWL_I2C_REG_DATCNT
- OWL_I2C_REG_FIFOCTL
- OWL_I2C_REG_FIFOSTAT
- OWL_I2C_REG_RCNT
- OWL_I2C_REG_RXDAT
- OWL_I2C_REG_STAT
- OWL_I2C_REG_TXDAT
- OWL_I2C_STAT_BBB
- OWL_I2C_STAT_BEB
- OWL_I2C_STAT_IRQP
- OWL_I2C_STAT_LAB
- OWL_I2C_STAT_LBST
- OWL_I2C_STAT_RACK
- OWL_I2C_STAT_SAMB
- OWL_I2C_STAT_SRGC
- OWL_I2C_STAT_STAD
- OWL_I2C_STAT_STPD
- OWL_I2C_STAT_TCB
- OWL_I2C_TIMEOUT
- OWL_MUX
- OWL_MUX_HW
- OWL_PINCONF_DRV_12MA
- OWL_PINCONF_DRV_2MA
- OWL_PINCONF_DRV_4MA
- OWL_PINCONF_DRV_8MA
- OWL_PINCONF_PULL_DOWN
- OWL_PINCONF_PULL_HIZ
- OWL_PINCONF_PULL_HOLD
- OWL_PINCONF_PULL_UP
- OWL_PINCONF_SLEW_FAST
- OWL_PINCONF_SLEW_SLOW
- OWL_PLL
- OWL_PLL_DEF_DELAY
- OWL_PLL_HW
- OWL_PLL_NO_PARENT
- OWL_PLL_NO_PARENT_DELAY
- OWL_S500_AUDIOPLL_DELAY
- OWL_S500_COREPLL_DELAY
- OWL_S500_DDRPLL_DELAY
- OWL_S500_DEVPLL_DELAY
- OWL_S500_DISPLAYPLL_DELAY
- OWL_S500_ETHERNETPLL_DELAY
- OWL_S500_NANDPLL_DELAY
- OWL_SPS_PG_CTL
- OWL_SPS_PG_CTL_ACK_CPU2
- OWL_SPS_PG_CTL_ACK_CPU3
- OWL_SPS_PG_CTL_PWR_CPU2
- OWL_SPS_PG_CTL_PWR_CPU3
- OWL_Tx_CMP
- OWL_Tx_CTL
- OWL_Tx_CTL_EN
- OWL_Tx_CTL_INTEN
- OWL_Tx_CTL_PD
- OWL_Tx_VAL
- OWL_UART_CONSOLE
- OWL_UART_CTL
- OWL_UART_CTL_AFE
- OWL_UART_CTL_DWLS_5BITS
- OWL_UART_CTL_DWLS_6BITS
- OWL_UART_CTL_DWLS_7BITS
- OWL_UART_CTL_DWLS_8BITS
- OWL_UART_CTL_DWLS_MASK
- OWL_UART_CTL_EN
- OWL_UART_CTL_LBEN
- OWL_UART_CTL_PRS_EVEN
- OWL_UART_CTL_PRS_MARK
- OWL_UART_CTL_PRS_MASK
- OWL_UART_CTL_PRS_NONE
- OWL_UART_CTL_PRS_ODD
- OWL_UART_CTL_PRS_SPACE
- OWL_UART_CTL_RXDE
- OWL_UART_CTL_RXIE
- OWL_UART_CTL_STPS_2BITS
- OWL_UART_CTL_TRFS_TX
- OWL_UART_CTL_TXDE
- OWL_UART_CTL_TXIE
- OWL_UART_DEV_NAME
- OWL_UART_PORT_NUM
- OWL_UART_RXDAT
- OWL_UART_STAT
- OWL_UART_STAT_CTSS
- OWL_UART_STAT_RFEM
- OWL_UART_STAT_RIP
- OWL_UART_STAT_RTSS
- OWL_UART_STAT_RXER
- OWL_UART_STAT_RXST
- OWL_UART_STAT_TFER
- OWL_UART_STAT_TFES
- OWL_UART_STAT_TFFU
- OWL_UART_STAT_TIP
- OWL_UART_STAT_TRFL_MASK
- OWL_UART_STAT_UTBB
- OWL_UART_TXDAT
- OWN
- OWNED_BY_HOST
- OWNED_BY_NIC
- OWNER
- OWNER_AICMD
- OWNER_AOCMD
- OWNER_HASH_BITS
- OWNER_HASH_MASK
- OWNER_HASH_SIZE
- OWNER_MASK
- OWNER_NODE_SHIFT
- OWNER_NONSPINNABLE
- OWNER_NO_OWNER
- OWNER_NULL
- OWNER_READER
- OWNER_SECINFO
- OWNER_SPINNABLE
- OWNER_WRITER
- OWNID_EAF
- OWNID_EHP
- OWNID_FS1
- OWNID_FS2
- OWNID_FS_12
- OWNID_FS_16
- OWNID_FS_8
- OWNID_RAF
- OWN_BIT
- OWN_CHIP
- OWN_CLEAR
- OWN_CNIC_IRQ
- OWN_HOST
- OWN_MASK
- OWN_UPDATE
- OWNbit
- OW_BASE_ADDRESS
- OXFORD_FIRMWARE_ID_ADDRESS
- OXFORD_HARDWARE_ID_ADDRESS
- OXFORD_HARDWARE_ID_OXFW970
- OXFORD_HARDWARE_ID_OXFW971
- OXILICX_AHB_CLK
- OXILICX_AXI_CLK
- OXILICX_GDSC
- OXILICX_RESET
- OXILI_GDSC
- OXILI_GFX3D_CLK
- OXILI_OCMEMGX_CLK
- OXILI_RBBMTIMER_CLK
- OXILI_RESET
- OXNAS_DWMAC_CTRL_REGOFFSET
- OXNAS_DWMAC_DELAY_REGOFFSET
- OXNAS_GATE
- OXNAS_NAND_CMD_ALE
- OXNAS_NAND_CMD_CLE
- OXNAS_NAND_MAX_CHIPS
- OXNAS_PINCTRL_FUNCTION
- OXNAS_PINCTRL_GROUP
- OXU_ASO
- OXU_ASO_OP
- OXU_BO_MASK
- OXU_BO_SHIFT
- OXU_CHIPIRQEN_CLR
- OXU_CHIPIRQEN_SET
- OXU_CHIPIRQSTATUS
- OXU_CLKCTRL_SET
- OXU_CM_HOST_ONLY
- OXU_COMPARATOR
- OXU_DEVICEID
- OXU_ES_LITTLE
- OXU_HOSTIFCONFIG
- OXU_MAJ_REV_MASK
- OXU_MAJ_REV_SHIFT
- OXU_MIN_REV_MASK
- OXU_MIN_REV_SHIFT
- OXU_OTG_CAP_OFFSET
- OXU_OTG_CORE_OFFSET
- OXU_OTG_MEM
- OXU_OVRCCURPUPDEN
- OXU_PIOBURSTREADCTRL
- OXU_REV_2100
- OXU_REV_MASK
- OXU_REV_SHIFT
- OXU_SOFTRESET
- OXU_SPHPOEN
- OXU_SPH_CAP_OFFSET
- OXU_SPH_CORE_OFFSET
- OXU_SPH_MEM
- OXU_SRESET
- OXU_SYSCLKEN
- OXU_URB_TRACE
- OXU_USBMODE
- OXU_USBOTGCLKEN
- OXU_USBOTGI
- OXU_USBOTGLPWUI
- OXU_USBSPHCLKEN
- OXU_USBSPHI
- OXU_USBSPHLPWUI
- OXU_VBPS
- OXU_VERBOSE_DEBUG
- OXYGEN_2WIRE_ADDRESS_MASK
- OXYGEN_2WIRE_ADDRESS_SHIFT
- OXYGEN_2WIRE_BUSY
- OXYGEN_2WIRE_BUS_RESET
- OXYGEN_2WIRE_BUS_STATUS
- OXYGEN_2WIRE_CLOCK_SYNC
- OXYGEN_2WIRE_CONTROL
- OXYGEN_2WIRE_DATA
- OXYGEN_2WIRE_DIR_MASK
- OXYGEN_2WIRE_DIR_READ
- OXYGEN_2WIRE_DIR_WRITE
- OXYGEN_2WIRE_INTERRUPT_MASK
- OXYGEN_2WIRE_LENGTH_16
- OXYGEN_2WIRE_LENGTH_8
- OXYGEN_2WIRE_LENGTH_MASK
- OXYGEN_2WIRE_MANUAL_READ
- OXYGEN_2WIRE_MAP
- OXYGEN_2WIRE_SLAVE_AD_MASK
- OXYGEN_2WIRE_SLAVE_NO_RESPONSE
- OXYGEN_2WIRE_SPEED_FAST
- OXYGEN_2WIRE_SPEED_MASK
- OXYGEN_2WIRE_SPEED_STANDARD
- OXYGEN_2WIRE_WRITE_MAP_ONLY
- OXYGEN_AC97_CLOCK_DISABLE
- OXYGEN_AC97_CODEC0_BASE
- OXYGEN_AC97_CODEC0_CENTER
- OXYGEN_AC97_CODEC0_FRONTL
- OXYGEN_AC97_CODEC0_FRONTR
- OXYGEN_AC97_CODEC0_LINEL
- OXYGEN_AC97_CODEC0_LINER
- OXYGEN_AC97_CODEC0_REARL
- OXYGEN_AC97_CODEC0_REARR
- OXYGEN_AC97_CODEC0_SIDEL
- OXYGEN_AC97_CODEC0_SIDER
- OXYGEN_AC97_CODEC1_LINEL
- OXYGEN_AC97_CODEC1_LINEL_16
- OXYGEN_AC97_CODEC1_LINEL_18
- OXYGEN_AC97_CODEC1_LINEL_20
- OXYGEN_AC97_CODEC1_LINEL_VSR
- OXYGEN_AC97_CODEC1_LINER
- OXYGEN_AC97_CODEC1_LINER_16
- OXYGEN_AC97_CODEC1_LINER_18
- OXYGEN_AC97_CODEC1_LINER_20
- OXYGEN_AC97_CODEC1_LINER_VSR
- OXYGEN_AC97_CODEC1_SLOT3
- OXYGEN_AC97_CODEC1_SLOT3_VSR
- OXYGEN_AC97_CODEC1_SLOT4
- OXYGEN_AC97_CODEC1_SLOT4_VSR
- OXYGEN_AC97_CODEC_0
- OXYGEN_AC97_CODEC_1
- OXYGEN_AC97_COLD_RESET
- OXYGEN_AC97_CONTROL
- OXYGEN_AC97_INTERRUPT_MASK
- OXYGEN_AC97_INTERRUPT_STATUS
- OXYGEN_AC97_INT_CODEC_0
- OXYGEN_AC97_INT_CODEC_1
- OXYGEN_AC97_INT_READ_DONE
- OXYGEN_AC97_INT_WRITE_DONE
- OXYGEN_AC97_IN_CONFIG
- OXYGEN_AC97_NO_CODEC_0
- OXYGEN_AC97_OUT_CONFIG
- OXYGEN_AC97_REGS
- OXYGEN_AC97_REG_ADDR_MASK
- OXYGEN_AC97_REG_ADDR_SHIFT
- OXYGEN_AC97_REG_CODEC_MASK
- OXYGEN_AC97_REG_CODEC_SHIFT
- OXYGEN_AC97_REG_DATA_MASK
- OXYGEN_AC97_REG_DIR_MASK
- OXYGEN_AC97_REG_DIR_READ
- OXYGEN_AC97_REG_DIR_WRITE
- OXYGEN_AC97_RESUME
- OXYGEN_AC97_SUSPENDED
- OXYGEN_ADC_MONITOR
- OXYGEN_ADC_MONITOR_A
- OXYGEN_ADC_MONITOR_A_HALF_VOL
- OXYGEN_ADC_MONITOR_B
- OXYGEN_ADC_MONITOR_B_HALF_VOL
- OXYGEN_ADC_MONITOR_C
- OXYGEN_ADC_MONITOR_C_HALF_VOL
- OXYGEN_A_MONITOR_ROUTE_0_MASK
- OXYGEN_A_MONITOR_ROUTE_0_SHIFT
- OXYGEN_A_MONITOR_ROUTE_1_MASK
- OXYGEN_A_MONITOR_ROUTE_1_SHIFT
- OXYGEN_A_MONITOR_ROUTE_2_MASK
- OXYGEN_A_MONITOR_ROUTE_2_SHIFT
- OXYGEN_A_MONITOR_ROUTE_3_MASK
- OXYGEN_A_MONITOR_ROUTE_3_SHIFT
- OXYGEN_A_MONITOR_ROUTING
- OXYGEN_CHANNEL_A
- OXYGEN_CHANNEL_AC97
- OXYGEN_CHANNEL_B
- OXYGEN_CHANNEL_C
- OXYGEN_CHANNEL_MULTICH
- OXYGEN_CHANNEL_SPDIF
- OXYGEN_CODEC_ID_MASK
- OXYGEN_CODEC_VERSION
- OXYGEN_DEVICE_SENSE
- OXYGEN_DMA_AC97_ADDRESS
- OXYGEN_DMA_AC97_COUNT
- OXYGEN_DMA_AC97_TCOUNT
- OXYGEN_DMA_A_ADDRESS
- OXYGEN_DMA_A_BURST_16
- OXYGEN_DMA_A_BURST_8
- OXYGEN_DMA_A_BURST_MASK
- OXYGEN_DMA_A_COUNT
- OXYGEN_DMA_A_TCOUNT
- OXYGEN_DMA_B_ADDRESS
- OXYGEN_DMA_B_COUNT
- OXYGEN_DMA_B_TCOUNT
- OXYGEN_DMA_C_ADDRESS
- OXYGEN_DMA_C_COUNT
- OXYGEN_DMA_C_TCOUNT
- OXYGEN_DMA_FLUSH
- OXYGEN_DMA_MULTICH_ADDRESS
- OXYGEN_DMA_MULTICH_BURST_16
- OXYGEN_DMA_MULTICH_BURST_8
- OXYGEN_DMA_MULTICH_BURST_MASK
- OXYGEN_DMA_MULTICH_COUNT
- OXYGEN_DMA_MULTICH_TCOUNT
- OXYGEN_DMA_PAUSE
- OXYGEN_DMA_RESET
- OXYGEN_DMA_SPDIF_ADDRESS
- OXYGEN_DMA_SPDIF_COUNT
- OXYGEN_DMA_SPDIF_TCOUNT
- OXYGEN_DMA_STATUS
- OXYGEN_EEPROM_ADDRESS_MASK
- OXYGEN_EEPROM_BUSY
- OXYGEN_EEPROM_CONTROL
- OXYGEN_EEPROM_DATA
- OXYGEN_EEPROM_DIR_MASK
- OXYGEN_EEPROM_DIR_READ
- OXYGEN_EEPROM_DIR_WRITE
- OXYGEN_EEPROM_ID
- OXYGEN_EEPROM_STATUS
- OXYGEN_EEPROM_VALID
- OXYGEN_FORMAT_16
- OXYGEN_FORMAT_24
- OXYGEN_FORMAT_32
- OXYGEN_FUNCTION
- OXYGEN_FUNCTION_2WIRE
- OXYGEN_FUNCTION_2WIRE_SPI_MASK
- OXYGEN_FUNCTION_CLOCK_CRYSTAL
- OXYGEN_FUNCTION_CLOCK_MASK
- OXYGEN_FUNCTION_CLOCK_PLL
- OXYGEN_FUNCTION_ENABLE_SPI_4_5
- OXYGEN_FUNCTION_PWDN
- OXYGEN_FUNCTION_PWDN_EN
- OXYGEN_FUNCTION_PWDN_POL
- OXYGEN_FUNCTION_RESET_CODEC
- OXYGEN_FUNCTION_RESET_POL
- OXYGEN_FUNCTION_SPI
- OXYGEN_GPIO1_XSLAVE_RDY
- OXYGEN_GPIO_CONTROL
- OXYGEN_GPIO_DATA
- OXYGEN_GPIO_INTERRUPT_MASK
- OXYGEN_GPI_DATA
- OXYGEN_GPI_INTERRUPT_MASK
- OXYGEN_HEAD_PHONE_ACTIVE_SPK
- OXYGEN_HEAD_PHONE_DETECT
- OXYGEN_HEAD_PHONE_HP
- OXYGEN_HEAD_PHONE_MASK
- OXYGEN_HEAD_PHONE_PASSIVE_SPK
- OXYGEN_H_INCLUDED
- OXYGEN_I2S_A_FORMAT
- OXYGEN_I2S_BCLK_128
- OXYGEN_I2S_BCLK_256
- OXYGEN_I2S_BCLK_64
- OXYGEN_I2S_BCLK_MASK
- OXYGEN_I2S_BITS_16
- OXYGEN_I2S_BITS_20
- OXYGEN_I2S_BITS_24
- OXYGEN_I2S_BITS_32
- OXYGEN_I2S_BITS_MASK
- OXYGEN_I2S_B_FORMAT
- OXYGEN_I2S_C_FORMAT
- OXYGEN_I2S_FORMAT_I2S
- OXYGEN_I2S_FORMAT_LJUST
- OXYGEN_I2S_FORMAT_MASK
- OXYGEN_I2S_MASTER
- OXYGEN_I2S_MCLK
- OXYGEN_I2S_MCLK_MASK
- OXYGEN_I2S_MCLK_SHIFT
- OXYGEN_I2S_MULTICH_FORMAT
- OXYGEN_I2S_MUTE_MCLK
- OXYGEN_I2S_RATE_MASK
- OXYGEN_INTERRUPT_MASK
- OXYGEN_INTERRUPT_STATUS
- OXYGEN_INT_2WIRE
- OXYGEN_INT_AC97
- OXYGEN_INT_GPIO
- OXYGEN_INT_MCB
- OXYGEN_INT_MCU
- OXYGEN_INT_MIDI
- OXYGEN_INT_SPDIF_IN_DETECT
- OXYGEN_IO_SIZE
- OXYGEN_MCLKS
- OXYGEN_MCU_2WIRE_ADDRESS_10
- OXYGEN_MCU_2WIRE_ADDRESS_12
- OXYGEN_MCU_2WIRE_ADDRESS_14
- OXYGEN_MCU_2WIRE_ADDRESS_16
- OXYGEN_MCU_2WIRE_ADDRESS_MASK
- OXYGEN_MCU_2WIRE_BUSY
- OXYGEN_MCU_2WIRE_CONTROL
- OXYGEN_MCU_2WIRE_DATA
- OXYGEN_MCU_2WIRE_DRV_ACK
- OXYGEN_MCU_2WIRE_DRV_XACT
- OXYGEN_MCU_2WIRE_DRV_XACT_FAIL
- OXYGEN_MCU_2WIRE_INT_MASK
- OXYGEN_MCU_2WIRE_INT_POL
- OXYGEN_MCU_2WIRE_LENGTH_1
- OXYGEN_MCU_2WIRE_LENGTH_2
- OXYGEN_MCU_2WIRE_LENGTH_3
- OXYGEN_MCU_2WIRE_LENGTH_MASK
- OXYGEN_MCU_2WIRE_MAP
- OXYGEN_MCU_2WIRE_READ
- OXYGEN_MCU_2WIRE_RESET
- OXYGEN_MCU_2WIRE_STATUS
- OXYGEN_MCU_2WIRE_SYNC_DATA
- OXYGEN_MCU_2WIRE_SYNC_ENABLE
- OXYGEN_MCU_2WIRE_SYNC_MASK
- OXYGEN_MCU_2WIRE_SYNC_RDY_PIN
- OXYGEN_MCU_2WIRE_WRITE
- OXYGEN_MISC
- OXYGEN_MISC_CRYSTAL_24576
- OXYGEN_MISC_CRYSTAL_27
- OXYGEN_MISC_CRYSTAL_MASK
- OXYGEN_MISC_LATENCY_3F
- OXYGEN_MISC_MIDI
- OXYGEN_MISC_PCI_MEM_W_1_CLOCK
- OXYGEN_MISC_REC_A_FROM_MULTICH
- OXYGEN_MISC_REC_B_FROM_AC97
- OXYGEN_MISC_REC_C_FROM_SPDIF
- OXYGEN_MISC_WRITE_PCI_SUBID
- OXYGEN_MPU401
- OXYGEN_MPU401_CONTROL
- OXYGEN_MPU401_LOOPBACK
- OXYGEN_MULTICH_FORMAT_MASK
- OXYGEN_MULTICH_FORMAT_SHIFT
- OXYGEN_MUTE_I2S_ADC_1
- OXYGEN_MUTE_I2S_ADC_2
- OXYGEN_MUTE_I2S_ADC_3
- OXYGEN_OFFSBASE_44K
- OXYGEN_OFFSBASE_48K
- OXYGEN_OFFSBASE_MASK
- OXYGEN_OFFSIN_44K
- OXYGEN_OFFSIN_48K
- OXYGEN_PACKAGE_ID_8786
- OXYGEN_PACKAGE_ID_8787
- OXYGEN_PACKAGE_ID_8788
- OXYGEN_PACKAGE_ID_MASK
- OXYGEN_PCI_SUBID
- OXYGEN_PCI_SUBID_BROKEN_EEPROM
- OXYGEN_PLAY_CHANNELS
- OXYGEN_PLAY_CHANNELS_2
- OXYGEN_PLAY_CHANNELS_4
- OXYGEN_PLAY_CHANNELS_6
- OXYGEN_PLAY_CHANNELS_8
- OXYGEN_PLAY_CHANNELS_MASK
- OXYGEN_PLAY_DAC0_SOURCE_MASK
- OXYGEN_PLAY_DAC0_SOURCE_SHIFT
- OXYGEN_PLAY_DAC1_SOURCE_MASK
- OXYGEN_PLAY_DAC1_SOURCE_SHIFT
- OXYGEN_PLAY_DAC2_SOURCE_MASK
- OXYGEN_PLAY_DAC2_SOURCE_SHIFT
- OXYGEN_PLAY_DAC3_SOURCE_MASK
- OXYGEN_PLAY_DAC3_SOURCE_SHIFT
- OXYGEN_PLAY_FORMAT
- OXYGEN_PLAY_MULTICH_AC97
- OXYGEN_PLAY_MULTICH_I2S_DAC
- OXYGEN_PLAY_MULTICH_MASK
- OXYGEN_PLAY_MUTE01
- OXYGEN_PLAY_MUTE23
- OXYGEN_PLAY_MUTE45
- OXYGEN_PLAY_MUTE67
- OXYGEN_PLAY_MUTE_MASK
- OXYGEN_PLAY_ROUTING
- OXYGEN_PLAY_SPDIF_I2S_ADC_3
- OXYGEN_PLAY_SPDIF_MASK
- OXYGEN_PLAY_SPDIF_MULTICH_01
- OXYGEN_PLAY_SPDIF_MULTICH_23
- OXYGEN_PLAY_SPDIF_MULTICH_45
- OXYGEN_PLAY_SPDIF_MULTICH_67
- OXYGEN_PLAY_SPDIF_REC_A
- OXYGEN_PLAY_SPDIF_REC_B
- OXYGEN_PLAY_SPDIF_SPDIF
- OXYGEN_RATE_176400
- OXYGEN_RATE_192000
- OXYGEN_RATE_32000
- OXYGEN_RATE_44100
- OXYGEN_RATE_48000
- OXYGEN_RATE_64000
- OXYGEN_RATE_88200
- OXYGEN_RATE_96000
- OXYGEN_REC_A_ROUTE_AC97_0
- OXYGEN_REC_A_ROUTE_I2S_ADC_1
- OXYGEN_REC_A_ROUTE_MASK
- OXYGEN_REC_B_ROUTE_AC97_1
- OXYGEN_REC_B_ROUTE_I2S_ADC_2
- OXYGEN_REC_B_ROUTE_MASK
- OXYGEN_REC_CHANNELS
- OXYGEN_REC_CHANNELS_2_2_2
- OXYGEN_REC_CHANNELS_4_2_2
- OXYGEN_REC_CHANNELS_6_0_2
- OXYGEN_REC_CHANNELS_6_2_0
- OXYGEN_REC_CHANNELS_8_0_0
- OXYGEN_REC_CHANNELS_MASK
- OXYGEN_REC_C_ROUTE_I2S_ADC_3
- OXYGEN_REC_C_ROUTE_MASK
- OXYGEN_REC_C_ROUTE_SPDIF
- OXYGEN_REC_FORMAT
- OXYGEN_REC_FORMAT_A_MASK
- OXYGEN_REC_FORMAT_A_SHIFT
- OXYGEN_REC_FORMAT_B_MASK
- OXYGEN_REC_FORMAT_B_SHIFT
- OXYGEN_REC_FORMAT_C_MASK
- OXYGEN_REC_FORMAT_C_SHIFT
- OXYGEN_REC_ROUTING
- OXYGEN_REGS_H_INCLUDED
- OXYGEN_REVISION
- OXYGEN_REVISION_2
- OXYGEN_REVISION_MASK
- OXYGEN_SPDIF_C
- OXYGEN_SPDIF_CATEGORY_MASK
- OXYGEN_SPDIF_CATEGORY_SHIFT
- OXYGEN_SPDIF_CONTROL
- OXYGEN_SPDIF_CS_RATE_MASK
- OXYGEN_SPDIF_CS_RATE_SHIFT
- OXYGEN_SPDIF_FORMAT_MASK
- OXYGEN_SPDIF_FORMAT_SHIFT
- OXYGEN_SPDIF_INPUT_BITS
- OXYGEN_SPDIF_IN_CLOCK_192
- OXYGEN_SPDIF_IN_CLOCK_96
- OXYGEN_SPDIF_IN_CLOCK_MASK
- OXYGEN_SPDIF_LOCK_INT
- OXYGEN_SPDIF_LOCK_MASK
- OXYGEN_SPDIF_LOCK_PAR
- OXYGEN_SPDIF_LOCK_STATUS
- OXYGEN_SPDIF_LOOPBACK
- OXYGEN_SPDIF_NONAUDIO
- OXYGEN_SPDIF_ORIGINAL
- OXYGEN_SPDIF_OUTPUT_BITS
- OXYGEN_SPDIF_OUT_ENABLE
- OXYGEN_SPDIF_OUT_RATE_MASK
- OXYGEN_SPDIF_OUT_RATE_SHIFT
- OXYGEN_SPDIF_PREEMPHASIS
- OXYGEN_SPDIF_RATE_INT
- OXYGEN_SPDIF_RATE_MASK
- OXYGEN_SPDIF_SENSE_INT
- OXYGEN_SPDIF_SENSE_MASK
- OXYGEN_SPDIF_SENSE_PAR
- OXYGEN_SPDIF_SENSE_STATUS
- OXYGEN_SPDIF_SPDVALID
- OXYGEN_SPDIF_V
- OXYGEN_SPI_BUSY
- OXYGEN_SPI_CEN_LATCH_CLOCK_HI
- OXYGEN_SPI_CEN_LATCH_CLOCK_LO
- OXYGEN_SPI_CEN_MASK
- OXYGEN_SPI_CLOCK_1280
- OXYGEN_SPI_CLOCK_160
- OXYGEN_SPI_CLOCK_320
- OXYGEN_SPI_CLOCK_640
- OXYGEN_SPI_CLOCK_MASK
- OXYGEN_SPI_CODEC_MASK
- OXYGEN_SPI_CODEC_SHIFT
- OXYGEN_SPI_CONTROL
- OXYGEN_SPI_DATA1
- OXYGEN_SPI_DATA2
- OXYGEN_SPI_DATA3
- OXYGEN_SPI_DATA_LENGTH_2
- OXYGEN_SPI_DATA_LENGTH_3
- OXYGEN_SPI_DATA_LENGTH_MASK
- OXYGEN_SPI_TRIGGER
- OXYGEN_TEST
- OXYGEN_TEST_2WIRE_LOOPBACK
- OXYGEN_TEST_PLAYBACK_RAM
- OXYGEN_TEST_PLL
- OXYGEN_TEST_RAM_SUCCEEDED
- OXYGEN_TEST_RECORD_RAM
- O_ACCMODE
- O_APPEND
- O_BINARY
- O_BLKSEEK
- O_BSDLY
- O_CAM4X128TABLE__BUCKETID
- O_CAM4X128TABLE__CLASSID
- O_CAM4X128TABLE__USEBUCKET
- O_CLASS0_SPILL_MEM_SIZE__CLASS0SPILLMEMSIZE
- O_CLASS0_SPILL_MEM_START_0__CLASS0SPILLMEMSTART0
- O_CLASS0_SPILL_MEM_START_1__CLASS0SPILLMEMSTART1
- O_CLASS1_SPILL_MEM_SIZE__CLASS1SPILLMEMSIZE
- O_CLASS1_SPILL_MEM_START_0__CLASS1SPILLMEMSTART0
- O_CLASS1_SPILL_MEM_START_1__CLASS1SPILLMEMSTART1
- O_CLASS2_SPILL_MEM_SIZE__CLASS2SPILLMEMSIZE
- O_CLASS2_SPILL_MEM_START_0__CLASS2SPILLMEMSTART0
- O_CLASS2_SPILL_MEM_START_1__CLASS2SPILLMEMSTART1
- O_CLASS3_SPILL_MEM_SIZE__CLASS3SPILLMEMSIZE
- O_CLASS3_SPILL_MEM_START_0__CLASS3SPILLMEMSTART0
- O_CLASS3_SPILL_MEM_START_1__CLASS3SPILLMEMSTART1
- O_CLASSWATERMARKS__CLASS0WATERMARK
- O_CLASSWATERMARKS__CLASS1WATERMARK
- O_CLASSWATERMARKS__CLASS3WATERMARK
- O_CLOEXEC
- O_CORECONTROL__ERRORTHREAD
- O_CORECONTROL__SHUTDOWN
- O_CORECONTROL__SPEED
- O_CRDLY
- O_CREAT
- O_DESC_PACK_CTRL__BYTEOFFSET
- O_DESC_PACK_CTRL__MAXENTRY
- O_DESC_PACK_CTRL__PREPADENABLE
- O_DESC_PACK_CTRL__REGULARSIZE
- O_DIRECT
- O_DIRECTORY
- O_DMACNTRL1
- O_DMACR0__DATA0RDMAXCR
- O_DMACR0__DATA0WRMAXCR
- O_DMACR0__DATA1RDMAXCR
- O_DMACR0__DATA1WRMAXCR
- O_DMACR0__DATA2RDMAXCR
- O_DMACR0__DATA2WRMAXCR
- O_DMACR0__DATA3RDMAXCR
- O_DMACR0__DATA3WRMAXCR
- O_DMACR0__DATA4RDMAXCR
- O_DMACR0__DATA4WRMAXCR
- O_DMACR1__DATA5RDMAXCR
- O_DMACR1__DATA5WRMAXCR
- O_DMACR1__DATA6RDMAXCR
- O_DMACR1__DATA6WRMAXCR
- O_DMACR1__DATA7RDMAXCR
- O_DMACR1__DATA7WRMAXCR
- O_DMACR1__DATA8RDMAXCR
- O_DMACR1__DATA8WRMAXCR
- O_DMACR1__DATA9RDMAXCR
- O_DMACR1__DATA9WRMAXCR
- O_DMACR2__DATA10RDMAXCR
- O_DMACR2__DATA10WRMAXCR
- O_DMACR2__DATA11RDMAXCR
- O_DMACR2__DATA11WRMAXCR
- O_DMACR2__DATA12RDMAXCR
- O_DMACR2__DATA12WRMAXCR
- O_DMACR2__DATA13RDMAXCR
- O_DMACR2__DATA13WRMAXCR
- O_DMACR2__DATA14RDMAXCR
- O_DMACR2__DATA14WRMAXCR
- O_DMACR3__DATA15RDMAXCR
- O_DMACR3__DATA15WRMAXCR
- O_DMACR3__FROUTRDMAXCR
- O_DMACR3__FROUTWRMAXCR
- O_DMACR3__JUMFRINRDMAXCR
- O_DMACR3__JUMFRINWRMAXCR
- O_DMACR3__REGFRINRDMAXCR
- O_DMACR3__REGFRINWRMAXCR
- O_DMACR3__SPCLASSRDMAXCR
- O_DMACR3__SPCLASSWRMAXCR
- O_DSYNC
- O_EXCL
- O_FFDLY
- O_FORCE
- O_FREEWATERMARKS__FREEOUTWATERMARK
- O_FREEWATERMARKS__JUMFRWATERMARK
- O_FREEWATERMARKS__REGFRWATERMARK
- O_FROUT_SPILL_MEM_SIZE__FROUTSPILLMEMSIZE
- O_FROUT_SPILL_MEM_START_0__FROUTSPILLMEMSTART0
- O_FROUT_SPILL_MEM_START_1__FROUTSPILLMEMSTART1
- O_HALF_DUPLEX__abebe
- O_HALF_DUPLEX__abebt
- O_HALF_DUPLEX__bpnb
- O_HALF_DUPLEX__edxsdfr
- O_HALF_DUPLEX__lcol
- O_HALF_DUPLEX__nobo
- O_HALF_DUPLEX__retry
- O_INTERFACE_CONTROL__dlfct
- O_INTERFACE_CONTROL__enjab
- O_INTERFACE_CONTROL__frcq
- O_INTERFACE_CONTROL__ghdmode
- O_INTERFACE_CONTROL__hr100
- O_INTERFACE_CONTROL__hrrmi
- O_INTERFACE_CONTROL__hrstint
- O_INTERFACE_CONTROL__lhdmode
- O_INTERFACE_CONTROL__nocfr
- O_INTERFACE_CONTROL__phymod
- O_INTERFACE_CONTROL__rspd
- O_INTERFACE_CONTROL__tbimode
- O_INTERFACE_STATUS__jabber
- O_INTERFACE_STATUS__locar
- O_INTERFACE_STATUS__miilf
- O_INTERFACE_STATUS__sqerr
- O_INTERFACE_STATUS__ssrr
- O_INTERFACE_STATUS__xsdfr
- O_INTMASK__ABORT
- O_INTMASK__ASYNCFIFOFULL
- O_INTMASK__C0EARLYFULL
- O_INTMASK__C1EARLYFULL
- O_INTMASK__C2EARLYFULL
- O_INTMASK__C3EARLYFULL
- O_INTMASK__CLASS0FULL
- O_INTMASK__CLASS1FULL
- O_INTMASK__CLASS2FULL
- O_INTMASK__CLASS3FULL
- O_INTMASK__DISCARDPACKET
- O_INTMASK__FREEDESCFULL
- O_INTMASK__FREEEARLYFULL
- O_INTMASK__MDINT
- O_INTMASK__P2PSPILLECC
- O_INTMASK__RFEARLYEMPTY
- O_INTMASK__RFREEEMPTY
- O_INTMASK__RGMIIHALFDUPCOLLISION
- O_INTMASK__RXDATAFULL
- O_INTMASK__RXEARLYFULL
- O_INTMASK__SPI4RXERROR
- O_INTMASK__SPI4TXERROR
- O_INTMASK__STATCARRY
- O_INTMASK__TAGFULL
- O_INTMASK__TXFETCHERROR
- O_INTMASK__TXILLEGAL
- O_INTMASK__UNDERRUN
- O_INTREG__ABORT
- O_INTREG__ASYNCFIFOFULL
- O_INTREG__C0EARLYFULL
- O_INTREG__C1EARLYFULL
- O_INTREG__C2EARLYFULL
- O_INTREG__C3EARLYFULL
- O_INTREG__CLASS0FULL
- O_INTREG__CLASS1FULL
- O_INTREG__CLASS2FULL
- O_INTREG__CLASS3FULL
- O_INTREG__DISCARDPACKET
- O_INTREG__FREEDESCFULL
- O_INTREG__FREEEARLYFULL
- O_INTREG__MDINT
- O_INTREG__P2PSPILLECC
- O_INTREG__RFEARLYEMPTY
- O_INTREG__RFREEEMPTY
- O_INTREG__RGMIIHALFDUPCOLLISION
- O_INTREG__RXDATAFULL
- O_INTREG__RXEARLYFULL
- O_INTREG__SPI4RXERROR
- O_INTREG__SPI4TXERROR
- O_INTREG__STATCARRY
- O_INTREG__TAGFULL
- O_INTREG__TXFETCHERROR
- O_INTREG__TXILLEGAL
- O_INTREG__UNDERRUN
- O_INVISIBLE
- O_IPG_IFG__ipgr1
- O_IPG_IFG__ipgr2
- O_IPG_IFG__ipgt
- O_IPG_IFG__mifg
- O_JUMFRIN_SPILL_MEM_SIZE__JUMFRINSPILLMEMSIZE
- O_JUMFRIN_SPILL_MEM_START_0__JUMFRINSPILLMEMSTART0
- O_JUMFRIN_SPILL_MEM_START_1__JUMFRINSPILLMEMSTART1
- O_L2ALLOCCTRL__RXL2ALLOCATE
- O_L2ALLOCCTRL__TXL2ALLOCATE
- O_L2TYPE__EXTRAHDRPROTOOFFSET
- O_L2TYPE__EXTRAHDRPROTOSIZE
- O_L2TYPE__EXTRAHEADERSIZE
- O_L2TYPE__L2HDROFFSET
- O_L2TYPE__L2PROTO
- O_L2TYPE__PROTOOFFSET
- O_L3CTABLE__IPCHKSUMCOMPUTE
- O_L3CTABLE__L2PROTO
- O_L3CTABLE__L3HDROFFSET
- O_L3CTABLE__L3PROTOKEY
- O_L3CTABLE__L4CLASSIFY
- O_L3CTABLE__L4PROTOOFFSET
- O_L3CTABLE__LEN0
- O_L3CTABLE__LEN1
- O_L3CTABLE__LEN2
- O_L3CTABLE__OFFSET0
- O_L3CTABLE__OFFSET1
- O_L3CTABLE__OFFSET2
- O_L4CTABLE__LEN0
- O_L4CTABLE__LEN1
- O_L4CTABLE__OFFSET0
- O_L4CTABLE__OFFSET1
- O_L4CTABLE__TCPCHKSUMENABLE
- O_LARGEFILE
- O_MAC_CONFIG_1__hrrfn
- O_MAC_CONFIG_1__hrrmc
- O_MAC_CONFIG_1__intlb
- O_MAC_CONFIG_1__rxen
- O_MAC_CONFIG_1__rxfc
- O_MAC_CONFIG_1__simr
- O_MAC_CONFIG_1__srst
- O_MAC_CONFIG_1__srxen
- O_MAC_CONFIG_1__stxen
- O_MAC_CONFIG_1__txen
- O_MAC_CONFIG_1__txfc
- O_MAC_CONFIG_2__crce
- O_MAC_CONFIG_2__flchk
- O_MAC_CONFIG_2__fulld
- O_MAC_CONFIG_2__hugen
- O_MAC_CONFIG_2__prlen
- O_MAC_CONFIG_2__speed
- O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC
- O_MAC_FILTER_CONFIG__ALL_MCAST_EN
- O_MAC_FILTER_CONFIG__ALL_UCAST_EN
- O_MAC_FILTER_CONFIG__BROADCAST_EN
- O_MAC_FILTER_CONFIG__HASH_MCAST_EN
- O_MAC_FILTER_CONFIG__HASH_UCAST_EN
- O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID
- O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID
- O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID
- O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID
- O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN
- O_MASK
- O_MAXIMUM_FRAME_LENGTH__maxf
- O_MII_MGMT_ADDRESS__fgad
- O_MII_MGMT_ADDRESS__fiad
- O_MII_MGMT_COMMAND__rstat
- O_MII_MGMT_COMMAND__scan
- O_MII_MGMT_CONFIG__clks
- O_MII_MGMT_CONFIG__scinc
- O_MII_MGMT_CONFIG__spre
- O_MII_MGMT_INDICATORS__busy
- O_MII_MGMT_INDICATORS__nvalid
- O_MII_MGMT_INDICATORS__scan
- O_MII_MGMT_WRITE_DATA__ctld
- O_NDELAY
- O_NLDLY
- O_NOATIME
- O_NOCTTY
- O_NOFOLLOW
- O_NONBLOCK
- O_OCRNL
- O_OFDEL
- O_OFILL
- O_OLCUC
- O_ONLCR
- O_ONLRET
- O_ONOCR
- O_OPOST
- O_PARSERCONFIGREG__CRCHASHPOLY
- O_PARSERCONFIGREG__PREPADOFFSET
- O_PARSERCONFIGREG__USECAM
- O_PARSERCONFIGREG__USEHASH
- O_PARSERCONFIGREG__USEPROTO
- O_PATH
- O_PLL_LOCK_RD
- O_PLL_READY_RD
- O_PORTA
- O_PORTB
- O_RDONLY
- O_RDWR
- O_REG_FRIN_SPILL_MEM_SIZE__REGFRINSPILLMEMSIZE
- O_REG_FRIN_SPILL_MEM_START_0__REGFRINSPILLMEMSTART0
- O_REG_FRIN_SPILL_MEM_START_1__REGFRINSPILLMEMSTART1
- O_RSYNC
- O_RXDATAFIFO0__RX0DATAFIFOSIZE
- O_RXDATAFIFO0__RX0DATAFIFOSTART
- O_RXDATAFIFO0__RX1DATAFIFOSIZE
- O_RXDATAFIFO0__RX1DATAFIFOSTART
- O_RXDATAFIFO1__RX2DATAFIFOSIZE
- O_RXDATAFIFO1__RX2DATAFIFOSTART
- O_RXDATAFIFO1__RX3DATAFIFOSIZE
- O_RXDATAFIFO1__RX3DATAFIFOSTART
- O_RXDATAFIFO2__RX4DATAFIFOSIZE
- O_RXDATAFIFO2__RX4DATAFIFOSTART
- O_RXDATAFIFO2__RX5DATAFIFOSIZE
- O_RXDATAFIFO2__RX5DATAFIFOSTART
- O_RXDATAFIFO3__RX6DATAFIFOSIZE
- O_RXDATAFIFO3__RX6DATAFIFOSTART
- O_RXDATAFIFO3__RX7DATAFIFOSIZE
- O_RXDATAFIFO3__RX7DATAFIFOSTART
- O_RXDATAFIFO4__RX8DATAFIFOSIZE
- O_RXDATAFIFO4__RX8DATAFIFOSTART
- O_RXDATAFIFO4__RX9DATAFIFOSIZE
- O_RXDATAFIFO4__RX9DATAFIFOSTART
- O_RXDATAFIFO5__RX10DATAFIFOSIZE
- O_RXDATAFIFO5__RX10DATAFIFOSTART
- O_RXDATAFIFO5__RX11DATAFIFOSIZE
- O_RXDATAFIFO5__RX11DATAFIFOSTART
- O_RXDATAFIFO6__RX12DATAFIFOSIZE
- O_RXDATAFIFO6__RX12DATAFIFOSTART
- O_RXDATAFIFO6__RX13DATAFIFOSIZE
- O_RXDATAFIFO6__RX13DATAFIFOSTART
- O_RXDATAFIFO7__RX14DATAFIFOSIZE
- O_RXDATAFIFO7__RX14DATAFIFOSTART
- O_RXDATAFIFO7__RX15DATAFIFOSIZE
- O_RXDATAFIFO7__RX15DATAFIFOSTART
- O_RXWATERMARKS__RX0DATAWATERMARK
- O_RXWATERMARKS__RX10DATAWATERMARK
- O_RXWATERMARKS__RX11DATAWATERMARK
- O_RXWATERMARKS__RX12DATAWATERMARK
- O_RXWATERMARKS__RX13DATAWATERMARK
- O_RXWATERMARKS__RX14DATAWATERMARK
- O_RXWATERMARKS__RX15DATAWATERMARK
- O_RXWATERMARKS__RX1DATAWATERMARK
- O_RXWATERMARKS__RX3DATAWATERMARK
- O_RXWATERMARKS__RX4DATAWATERMARK
- O_RXWATERMARKS__RX5DATAWATERMARK
- O_RXWATERMARKS__RX6DATAWATERMARK
- O_RXWATERMARKS__RX7DATAWATERMARK
- O_RXWATERMARKS__RX8DATAWATERMARK
- O_RXWATERMARKS__RX9DATAWATERMARK
- O_RX_CONTROL__RGMII
- O_RX_CONTROL__RXENABLE
- O_RX_CONTROL__RXHALT
- O_RX_CONTROL__SOFTRESET
- O_SPI4CONTROL__LVDS_LVTTL
- O_SPI4CONTROL__SPI4ENABLE
- O_SPI4CONTROL__STATICDELAY
- O_SPI4STATICDELAY0__DATALINE0
- O_SPI4STATICDELAY0__DATALINE1
- O_SPI4STATICDELAY0__DATALINE2
- O_SPI4STATICDELAY0__DATALINE3
- O_SPI4STATICDELAY0__DATALINE4
- O_SPI4STATICDELAY0__DATALINE5
- O_SPI4STATICDELAY0__DATALINE6
- O_SPI4STATICDELAY0__DATALINE7
- O_SPI4STATICDELAY0__RXCONTROL
- O_SPI4STATICDELAY0__TXSTAT0
- O_SPI4STATICDELAY0__TXSTAT1
- O_SPI4STATICDELAY1__DATALINE10
- O_SPI4STATICDELAY1__DATALINE11
- O_SPI4STATICDELAY1__DATALINE12
- O_SPI4STATICDELAY1__DATALINE13
- O_SPI4STATICDELAY1__DATALINE14
- O_SPI4STATICDELAY1__DATALINE15
- O_SPI4STATICDELAY1__DATALINE8
- O_SPI4STATICDELAY1__DATALINE9
- O_SPIHNGY0__EG_HNGY_THRESH_0
- O_SPIHNGY0__EG_HNGY_THRESH_1
- O_SPIHNGY0__EG_HNGY_THRESH_2
- O_SPIHNGY0__EG_HNGY_THRESH_3
- O_SPIHNGY1__EG_HNGY_THRESH_4
- O_SPIHNGY1__EG_HNGY_THRESH_5
- O_SPIHNGY1__EG_HNGY_THRESH_6
- O_SPIHNGY1__EG_HNGY_THRESH_7
- O_SPIHNGY2__EG_HNGY_THRESH_10
- O_SPIHNGY2__EG_HNGY_THRESH_11
- O_SPIHNGY2__EG_HNGY_THRESH_8
- O_SPIHNGY2__EG_HNGY_THRESH_9
- O_SPIHNGY3__EG_HNGY_THRESH_12
- O_SPIHNGY3__EG_HNGY_THRESH_13
- O_SPIHNGY3__EG_HNGY_THRESH_14
- O_SPIHNGY3__EG_HNGY_THRESH_15
- O_SPISTRV0__EG_STRV_THRESH_0
- O_SPISTRV0__EG_STRV_THRESH_1
- O_SPISTRV0__EG_STRV_THRESH_2
- O_SPISTRV0__EG_STRV_THRESH_3
- O_SPISTRV1__EG_STRV_THRESH_4
- O_SPISTRV1__EG_STRV_THRESH_5
- O_SPISTRV1__EG_STRV_THRESH_6
- O_SPISTRV1__EG_STRV_THRESH_7
- O_SPISTRV2__EG_STRV_THRESH_10
- O_SPISTRV2__EG_STRV_THRESH_11
- O_SPISTRV2__EG_STRV_THRESH_8
- O_SPISTRV2__EG_STRV_THRESH_9
- O_SPISTRV3__EG_STRV_THRESH_12
- O_SPISTRV3__EG_STRV_THRESH_13
- O_SPISTRV3__EG_STRV_THRESH_14
- O_SPISTRV3__EG_STRV_THRESH_15
- O_STACK
- O_STATCTRL__AUTOZ
- O_STATCTRL__CLRCNT
- O_STATCTRL__GIG
- O_STATCTRL__OVERFLOWEN
- O_STATCTRL__STEN
- O_SYNC
- O_TABDLY
- O_TC_DMACNTRL1
- O_TC_PORTA
- O_TC_PORTB
- O_TC_STACK
- O_TEST__mbof
- O_TEST__rthdf
- O_TEST__sstct
- O_TEST__tpause
- O_TMPFILE
- O_TMPFILE_MASK
- O_TRUNC
- O_TXDATAFIFO0__TX0DATAFIFOSIZE
- O_TXDATAFIFO0__TX0DATAFIFOSTART
- O_TXDATAFIFO0__TX1DATAFIFOSIZE
- O_TXDATAFIFO0__TX1DATAFIFOSTART
- O_TXDATAFIFO1__TX2DATAFIFOSIZE
- O_TXDATAFIFO1__TX2DATAFIFOSTART
- O_TXDATAFIFO1__TX3DATAFIFOSIZE
- O_TXDATAFIFO1__TX3DATAFIFOSTART
- O_TXDATAFIFO2__TX4DATAFIFOSIZE
- O_TXDATAFIFO2__TX4DATAFIFOSTART
- O_TXDATAFIFO2__TX5DATAFIFOSIZE
- O_TXDATAFIFO2__TX5DATAFIFOSTART
- O_TXDATAFIFO3__TX6DATAFIFOSIZE
- O_TXDATAFIFO3__TX6DATAFIFOSTART
- O_TXDATAFIFO3__TX7DATAFIFOSIZE
- O_TXDATAFIFO3__TX7DATAFIFOSTART
- O_TXDATAFIFO4__TX8DATAFIFOSIZE
- O_TXDATAFIFO4__TX8DATAFIFOSTART
- O_TXDATAFIFO4__TX9DATAFIFOSIZE
- O_TXDATAFIFO4__TX9DATAFIFOSTART
- O_TXDATAFIFO5__TX10DATAFIFOSIZE
- O_TXDATAFIFO5__TX10DATAFIFOSTART
- O_TXDATAFIFO5__TX11DATAFIFOSIZE
- O_TXDATAFIFO5__TX11DATAFIFOSTART
- O_TXDATAFIFO6__TX12DATAFIFOSIZE
- O_TXDATAFIFO6__TX12DATAFIFOSTART
- O_TXDATAFIFO6__TX13DATAFIFOSIZE
- O_TXDATAFIFO6__TX13DATAFIFOSTART
- O_TXDATAFIFO7__TX14DATAFIFOSIZE
- O_TXDATAFIFO7__TX14DATAFIFOSTART
- O_TXDATAFIFO7__TX15DATAFIFOSIZE
- O_TXDATAFIFO7__TX15DATAFIFOSTART
- O_TXRETRY__BUSERRORRETRY
- O_TXRETRY__COLLISIONRETRY
- O_TXRETRY__RETRIES
- O_TXRETRY__UNDERRUNRETRY
- O_TX_CONTROL__TX0HALT
- O_TX_CONTROL__TX10HALT
- O_TX_CONTROL__TX11HALT
- O_TX_CONTROL__TX12HALT
- O_TX_CONTROL__TX13HALT
- O_TX_CONTROL__TX14HALT
- O_TX_CONTROL__TX15HALT
- O_TX_CONTROL__TX1HALT
- O_TX_CONTROL__TX2HALT
- O_TX_CONTROL__TX3HALT
- O_TX_CONTROL__TX4HALT
- O_TX_CONTROL__TX5HALT
- O_TX_CONTROL__TX6HALT
- O_TX_CONTROL__TX7HALT
- O_TX_CONTROL__TX8HALT
- O_TX_CONTROL__TX9HALT
- O_TX_CONTROL__TXENABLE
- O_TX_CONTROL__TXIDLE
- O_TX_CONTROL__TXTHRESHOLD
- O_VTDLY
- O_WRONLY
- O_XGMAC_CONFIG_0__hstloopback
- O_XGMAC_CONFIG_0__hstmacrst
- O_XGMAC_CONFIG_0__hstrstmiim
- O_XGMAC_CONFIG_0__hstrstrctl
- O_XGMAC_CONFIG_0__hstrstrfn
- O_XGMAC_CONFIG_0__hstrsttctl
- O_XGMAC_CONFIG_0__hstrsttfn
- O_XGMAC_CONFIG_1__hstbytswp
- O_XGMAC_CONFIG_1__hstdlyfcsrx
- O_XGMAC_CONFIG_1__hstdlyfcstx
- O_XGMAC_CONFIG_1__hstdrplt64
- O_XGMAC_CONFIG_1__hstgenfcs
- O_XGMAC_CONFIG_1__hstlenchk
- O_XGMAC_CONFIG_1__hstpadmode
- O_XGMAC_CONFIG_1__hstppen
- O_XGMAC_CONFIG_1__hstprmscrx
- O_XGMAC_CONFIG_1__hstrctlen
- O_XGMAC_CONFIG_1__hstrctlshrtp
- O_XGMAC_CONFIG_1__hstrfen
- O_XGMAC_CONFIG_1__hsttctlen
- O_XGMAC_CONFIG_1__hsttfen
- O_XGMAC_CONFIG_1__rfen
- O_XGMAC_CONFIG_1__tfen
- O_XGMAC_CONFIG_2__hstalnkflth
- O_XGMAC_CONFIG_2__hstipgexten
- O_XGMAC_CONFIG_2__hstipgextmod
- O_XGMAC_CONFIG_2__hstmipgext
- O_XGMAC_CONFIG_2__hstmlnkflth
- O_XGMAC_CONFIG_2__hstrctlfrcp
- O_XGMAC_CONFIG_2__hsttctlfrcp
- O_XGMAC_CONFIG_2__rflnkflt
- O_XGMAC_CONFIG_3__hstfltrfrm
- O_XGMAC_CONFIG_3__hstfltrfrmdc
- O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx
- O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx
- O_XGMAC_MIIM_COMMAND__hstldcmd
- O_XGMAC_MIIM_COMMAND__hstmiimcmd
- O_XGMAC_MIIM_CONFIG__hstclkdiv
- O_XGMAC_MIIM_CONFIG__hstnopram
- O_XGMAC_MIIM_FILED__hstopfield
- O_XGMAC_MIIM_FILED__hstphyadx
- O_XGMAC_MIIM_FILED__hstregadx
- O_XGMAC_MIIM_FILED__hststfield
- O_XGMAC_MIIM_FILED__hsttafield
- O_XGMAC_MIIM_FILED__miimrddat
- O_XGMAC_MIIM_INDICATOR__miimbusy
- O_XGMAC_MIIM_INDICATOR__miimmon
- O_XGMAC_MIIM_INDICATOR__miimmoncplt
- O_XGMAC_MIIM_INDICATOR__miimmonvld
- O_XGMAC_MIIM_INDICATOR__miimphylf
- O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec
- O_XGMAC_REV_LEVEL__revlvl
- O_XGMAC_STATION_ADDRESS_LS__hstmacadr0
- Object_Info
- OctetRcvOk
- OctetXmtOk
- Oelif
- OffFSELog
- Offline
- OffsetConfig
- Ofs_rxb
- Ofs_txb
- Oif
- Oiffy
- Ok
- OldOrNew
- OldRxBufAddr
- OldTSD0
- OnAction
- OnAction_back
- OnAction_dls
- OnAction_ht
- OnAction_p2p
- OnAction_qos
- OnAction_sa_query
- OnAction_wmm
- OnAssocReq
- OnAssocRsp
- OnAtim
- OnAuth
- OnAuthClient
- OnBeacon
- OnDeAuth
- OnDisassoc
- OnProbeReq
- OnProbeRsp
- Online
- Op0
- Op0_mask
- Op0_shift
- Op1
- Op1_mask
- Op1_shift
- Op2
- Op2_mask
- Op2_shift
- Op3264
- Op3MemWaits
- OpAcc
- OpAccHi
- OpAccLo
- OpBits
- OpCL
- OpCS
- OpDI
- OpDS
- OpDX
- OpES
- OpFS
- OpGS
- OpImm
- OpImm64
- OpImmByte
- OpImmFAddr
- OpImmU
- OpImmU16
- OpImmUByte
- OpImplicit
- OpLenInclude
- OpLoopback
- OpMask
- OpMem
- OpMem16
- OpMem32
- OpMem64
- OpMem8
- OpMemFAddr
- OpModes
- OpNone
- OpOne
- OpReg
- OpRxMerge
- OpSI
- OpSS
- OpTxMerge
- OpWin95bugfix
- OpXLat
- OpalDeviceCompare
- OpalEehFreezeActionToken
- OpalErrinjectFunc
- OpalErrinjectType
- OpalExceptionHandler
- OpalFreezeState
- OpalFuncCompare
- OpalHMIEvent
- OpalHMIEvt_V1
- OpalHMIEvt_V2
- OpalHMI_CoreXstopReason
- OpalHMI_DISPOSITION_NOT_RECOVERED
- OpalHMI_DISPOSITION_RECOVERED
- OpalHMI_Disposition
- OpalHMI_ERROR_CAPP_RECOVERY
- OpalHMI_ERROR_DEBUG_TRIG_FIR
- OpalHMI_ERROR_HA_OVERFLOW_WARN
- OpalHMI_ERROR_HYP_RESOURCE
- OpalHMI_ERROR_MALFUNC_ALERT
- OpalHMI_ERROR_PROC_RECOV_DONE
- OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN
- OpalHMI_ERROR_PROC_RECOV_MASKED
- OpalHMI_ERROR_SCOM_FIR
- OpalHMI_ERROR_TFAC
- OpalHMI_ERROR_TFMR_PARITY
- OpalHMI_ERROR_XSCOM_DONE
- OpalHMI_ERROR_XSCOM_FAIL
- OpalHMI_ErrType
- OpalHMI_NestAccelXstopReason
- OpalHMI_SEV_ERROR_SYNC
- OpalHMI_SEV_FATAL
- OpalHMI_SEV_NO_ERROR
- OpalHMI_SEV_WARNING
- OpalHMI_Severity
- OpalHMI_Version
- OpalHMI_XstopType
- OpalHmiEvtNode
- OpalIoP7IOCBiErrorData
- OpalIoP7IOCCiErrorData
- OpalIoP7IOCErrorData
- OpalIoP7IOCPhbErrorData
- OpalIoP7IOCRgcErrorData
- OpalIoPhb3ErrorData
- OpalIoPhb4ErrorData
- OpalIoPhbErrorCommon
- OpalLPCAddressType
- OpalM64Action
- OpalMemErrType
- OpalMemErr_DynErrType
- OpalMemErr_ResilErrType
- OpalMemErr_V1
- OpalMemErr_Version
- OpalMemoryErrorData
- OpalMmioWindowType
- OpalMsgNode
- OpalMveEnableAction
- OpalPciBus3Bits
- OpalPciBus4Bits
- OpalPciBus5Bits
- OpalPciBus6Bits
- OpalPciBus7Bits
- OpalPciBusAll
- OpalPciBusAny
- OpalPciBusCompare
- OpalPciErrorSeverity
- OpalPciReinitScope
- OpalPciResetScope
- OpalPciResetState
- OpalPciSlotPower
- OpalPciSlotPresence
- OpalPciStatusToken
- OpalPeAction
- OpalPeltvAction
- OpalPendingState
- OpalSlotLedState
- OpalSlotLedType
- OpalSysCooling
- OpalSysEpow
- OpalSysPower
- OpalSysTemp
- OpalSysparamPerm
- OpalThreadStatus
- OpenLogicalChannel
- OpenLogicalChannelAck
- OpenLogicalChannelAck_forwardMultiplexAckParameters
- OpenLogicalChannelAck_reverseLogicalChannelParameters
- OpenLogicalChannelAck_reverseLogicalChannelParameters_multiplexParameters
- OpenLogicalChannel_forwardLogicalChannelParameters
- OpenLogicalChannel_forwardLogicalChannelParameters_multiplexParameters
- OpenLogicalChannel_reverseLogicalChannelParameters
- OpenLogicalChannel_reverseLogicalChannelParameters_multiplexParameters
- OperationMode
- Opt_abort
- Opt_abort_on_full
- Opt_ac
- Opt_access
- Opt_acdirmax
- Opt_acdirmin
- Opt_acl
- Opt_acregmax
- Opt_acregmin
- Opt_actimeo
- Opt_active_logs
- Opt_addr
- Opt_adinicb
- Opt_afid
- Opt_all
- Opt_alloc
- Opt_alloc_size
- Opt_alloc_start
- Opt_allocsize
- Opt_allow_utime
- Opt_anchor
- Opt_appraise
- Opt_appraise_type
- Opt_assert
- Opt_asyncreaddir
- Opt_atime_quantum
- Opt_attr2
- Opt_audit
- Opt_auth_hash_name
- Opt_auth_key
- Opt_auto_da_alloc
- Opt_autocell
- Opt_backupgid
- Opt_backupuid
- Opt_barrier
- Opt_biosize
- Opt_blank_ip
- Opt_blank_pass
- Opt_blank_user
- Opt_blobauth
- Opt_block
- Opt_block_validity
- Opt_blocksize
- Opt_brl
- Opt_bs
- Opt_bsd_df
- Opt_bsdgroups
- Opt_bsize
- Opt_bulk_read
- Opt_cache
- Opt_cache_err
- Opt_cache_loose
- Opt_cache_none
- Opt_cache_ro
- Opt_cache_rw
- Opt_cache_strategy
- Opt_cache_strict
- Opt_cachetag
- Opt_caps_max
- Opt_caps_wanted_delay_max
- Opt_caps_wanted_delay_min
- Opt_case_asis
- Opt_case_lower
- Opt_cdp
- Opt_cdpl2
- Opt_cephx_require_signatures
- Opt_cephx_sign_messages
- Opt_charset
- Opt_check_integrity
- Opt_check_integrity_including_extent_data
- Opt_check_integrity_print_mask
- Opt_check_n
- Opt_check_none
- Opt_check_normal
- Opt_check_r
- Opt_check_s
- Opt_check_strict
- Opt_checkpoint_disable
- Opt_checkpoint_disable_cap
- Opt_checkpoint_disable_cap_perc
- Opt_checkpoint_enable
- Opt_chk_data_crc
- Opt_chkdsk_always
- Opt_chkdsk_errors
- Opt_chkdsk_no
- Opt_cifsacl
- Opt_clear_cache
- Opt_clientaddr
- Opt_clone_children
- Opt_codepage
- Opt_coherency_buffered
- Opt_coherency_full
- Opt_commit
- Opt_commit_interval
- Opt_compress
- Opt_compress_force
- Opt_compress_force_type
- Opt_compress_type
- Opt_congestion_kb
- Opt_context
- Opt_copyfrom
- Opt_cpuset_v2_mode
- Opt_crc
- Opt_cruft
- Opt_cruid
- Opt_cto
- Opt_data
- Opt_data_err_abort
- Opt_data_err_ignore
- Opt_data_flush
- Opt_data_journal
- Opt_data_ordered
- Opt_data_writeback
- Opt_datacow
- Opt_datasum
- Opt_dax
- Opt_dcache
- Opt_debug
- Opt_debug_want_extra_isize
- Opt_default
- Opt_defcontext
- Opt_defrag
- Opt_degraded
- Opt_delalloc
- Opt_deprecated
- Opt_dev_config
- Opt_dev_size
- Opt_device
- Opt_dfltgid
- Opt_dfltuid
- Opt_dioread_lock
- Opt_dioread_nolock
- Opt_dir_resv_level
- Opt_direct
- Opt_dirmode
- Opt_dirstat
- Opt_disable_ext_identify
- Opt_disable_roll_forward
- Opt_discard
- Opt_discard_minblk
- Opt_dmask
- Opt_dmode
- Opt_domain
- Opt_domainauto
- Opt_dont_appraise
- Opt_dont_hash
- Opt_dont_measure
- Opt_dos1xfloppy
- Opt_dots
- Opt_dyn
- Opt_dynperm
- Opt_eas_no
- Opt_eas_ro
- Opt_eas_rw
- Opt_echo_interval
- Opt_ecryptfs
- Opt_enc
- Opt_enc32
- Opt_enospc_debug
- Opt_err
- Opt_err_cont
- Opt_err_panic
- Opt_err_ro
- Opt_error
- Opt_errors
- Opt_errors_panic
- Opt_errors_withdraw
- Opt_euid_eq
- Opt_euid_gt
- Opt_euid_lt
- Opt_exclusive
- Opt_extent_cache
- Opt_fast_unmount
- Opt_fastboot
- Opt_fatal_errors
- Opt_fault_injection
- Opt_fault_type
- Opt_fd
- Opt_fd_async_io
- Opt_fd_buffered_io
- Opt_fd_dev_name
- Opt_fd_dev_size
- Opt_file_mode
- Opt_fileset
- Opt_filestreams
- Opt_find_err
- Opt_find_gid
- Opt_find_group
- Opt_find_uid
- Opt_find_user
- Opt_first
- Opt_flock
- Opt_flush
- Opt_flush_merge
- Opt_flushoncommit
- Opt_fmask
- Opt_fmode
- Opt_force
- Opt_forcegid
- Opt_forcemandatorylock
- Opt_forceuid
- Opt_fowner_eq
- Opt_fowner_gt
- Opt_fowner_lt
- Opt_fragment_all
- Opt_fragment_data
- Opt_fragment_metadata
- Opt_fsc
- Opt_fscache
- Opt_fscache_uniq
- Opt_fscontext
- Opt_fsdefault
- Opt_fsfloor
- Opt_fshat
- Opt_fsid
- Opt_fsmagic
- Opt_fsname
- Opt_fsroot
- Opt_fstransmute
- Opt_fsuuid
- Opt_fsync
- Opt_ftsuffix
- Opt_func
- Opt_gc_background
- Opt_gforget
- Opt_gid
- Opt_gignore
- Opt_gqnoenforce
- Opt_gquota
- Opt_grpid
- Opt_grpjquota
- Opt_grpquota
- Opt_handlecache
- Opt_handletimeout
- Opt_hard
- Opt_hash
- Opt_hb_global
- Opt_hb_local
- Opt_hb_none
- Opt_heap
- Opt_help
- Opt_hide
- Opt_hidepid
- Opt_hostdata
- Opt_huge
- Opt_hw_block_size
- Opt_hw_max_sectors
- Opt_i_version
- Opt_id
- Opt_ignore
- Opt_ignore_local_fs
- Opt_ignore_signature
- Opt_ikeep
- Opt_immutable
- Opt_indirect
- Opt_init_itable
- Opt_initiator_fabric
- Opt_initiator_node
- Opt_initiator_sid
- Opt_inline_data
- Opt_inline_dentry
- Opt_inline_xattr
- Opt_inline_xattr_size
- Opt_ino32
- Opt_inode32
- Opt_inode64
- Opt_inode_cache
- Opt_inode_readahead_blks
- Opt_integrity
- Opt_intr
- Opt_io_size_bits
- Opt_iocharset
- Opt_ip
- Opt_jid
- Opt_journal_async_commit
- Opt_journal_checksum
- Opt_journal_dev
- Opt_journal_ioprio
- Opt_journal_path
- Opt_jqfmt_vfsold
- Opt_jqfmt_vfsv0
- Opt_jqfmt_vfsv1
- Opt_key
- Opt_keyauth
- Opt_keyhandle
- Opt_kmsg_bytes
- Opt_largeio
- Opt_last_int
- Opt_last_string
- Opt_lastblock
- Opt_lazytime
- Opt_legacy
- Opt_load
- Opt_local_lock
- Opt_local_lock_all
- Opt_local_lock_err
- Opt_local_lock_flock
- Opt_local_lock_none
- Opt_local_lock_posix
- Opt_localalloc
- Opt_localcaching
- Opt_localflocks
- Opt_locallease
- Opt_loccookie
- Opt_lock
- Opt_lock_on_read
- Opt_lock_timeout
- Opt_lockproto
- Opt_locktable
- Opt_locktimeout
- Opt_logbsize
- Opt_logbufs
- Opt_logdev
- Opt_longad
- Opt_lookupcache
- Opt_lookupcache_all
- Opt_lookupcache_err
- Opt_lookupcache_none
- Opt_lookupcache_positive
- Opt_map_a
- Opt_map_n
- Opt_map_o
- Opt_mapchars
- Opt_mapped_lun
- Opt_mapposix
- Opt_mask
- Opt_max
- Opt_max_batch_time
- Opt_max_credits
- Opt_max_data_area_mb
- Opt_max_dir_size_kb
- Opt_max_inline
- Opt_maxproto
- Opt_mba_mbps
- Opt_mblk_io_submit
- Opt_mds_namespace
- Opt_measure
- Opt_memory_localevents
- Opt_meta
- Opt_mfsymlinks
- Opt_migratable
- Opt_migration
- Opt_min_batch_time
- Opt_min_enc_offload
- Opt_min_size
- Opt_minix_df
- Opt_minorversion
- Opt_minproto
- Opt_mmap
- Opt_mmifs
- Opt_mode
- Opt_modesid
- Opt_mount_timeout
- Opt_mountaddr
- Opt_mounthost
- Opt_mountport
- Opt_mountproto
- Opt_mountvers
- Opt_mpol
- Opt_msize
- Opt_mufs
- Opt_multiuser
- Opt_name
- Opt_namecase
- Opt_namelen
- Opt_nconnect
- Opt_netbiosname
- Opt_new
- Opt_newinstance
- Opt_nfs
- Opt_nfs_nostale_ro
- Opt_nfs_stale_rw
- Opt_nfsvers
- Opt_nl_reply_supported
- Opt_no_bulk_read
- Opt_no_chk_data_crc
- Opt_no_disconnect
- Opt_no_space_cache
- Opt_noac
- Opt_noacl
- Opt_noadinicb
- Opt_noalign
- Opt_noasyncreaddir
- Opt_noattr2
- Opt_noauto_da_alloc
- Opt_noautotune
- Opt_nobarrier
- Opt_nobh
- Opt_noblock_validity
- Opt_noblocksend
- Opt_nobrl
- Opt_nocase
- Opt_nocephx_require_signatures
- Opt_nocephx_sign_messages
- Opt_nocheck
- Opt_nocifsacl
- Opt_nocompress
- Opt_nocopyfrom
- Opt_nocrc
- Opt_nocto
- Opt_nodatacow
- Opt_nodatasum
- Opt_nodcache
- Opt_nodefrag
- Opt_nodelalloc
- Opt_nodevmap
- Opt_nodfs
- Opt_nodir
- Opt_nodirstat
- Opt_nodiscard
- Opt_nodots
- Opt_nodynperm
- Opt_noenospc_debug
- Opt_noextent_cache
- Opt_noflush_merge
- Opt_noflushoncommit
- Opt_noforcegid
- Opt_noforceuid
- Opt_nofscache
- Opt_nogrpid
- Opt_nohandlecache
- Opt_nohard
- Opt_noheap
- Opt_noikeep
- Opt_noinit_itable
- Opt_noinline_data
- Opt_noinline_dentry
- Opt_noinline_xattr
- Opt_noino32
- Opt_noinode_cache
- Opt_nointegrity
- Opt_nointr
- Opt_nojoliet
- Opt_nojournal_checksum
- Opt_nolargeio
- Opt_nolazytime
- Opt_nolease
- Opt_noload
- Opt_nolock
- Opt_nologreplay
- Opt_nomapchars
- Opt_nomapposix
- Opt_nombcache
- Opt_nomblk_io_submit
- Opt_nomigration
- Opt_none
- Opt_nonumtail_no
- Opt_nonumtail_yes
- Opt_noperm
- Opt_nopersistent
- Opt_nopoolperm
- Opt_noposix
- Opt_noposixpaths
- Opt_noprefix
- Opt_noquota
- Opt_noquotadf
- Opt_norbytes
- Opt_nordirplus
- Opt_norecovery
- Opt_norequire_active_mds
- Opt_noreservation
- Opt_noresilient
- Opt_noresvport
- Opt_norm_unmount
- Opt_norock
- Opt_noserverino
- Opt_nosetuids
- Opt_nosfu
- Opt_noshare
- Opt_nosharecache
- Opt_nosharesock
- Opt_nosoft
- Opt_nossd
- Opt_nossd_spread
- Opt_nostrict
- Opt_nostrictsync
- Opt_notcp_nodelay
- Opt_notreelog
- Opt_notrim
- Opt_notruncate
- Opt_nouid32
- Opt_nounix
- Opt_nouser_xattr
- Opt_nouuid
- Opt_novrs
- Opt_nowarn_on_error
- Opt_nr_blocks
- Opt_nr_inodes
- Opt_nsdelegate
- Opt_ntlm
- Opt_obj_role
- Opt_obj_type
- Opt_obj_user
- Opt_obsolete
- Opt_offgrpjquota
- Opt_offprjjquota
- Opt_offset
- Opt_offusrjquota
- Opt_oldalloc
- Opt_onerror_lock
- Opt_onerror_panic
- Opt_onerror_repair
- Opt_onerror_umount
- Opt_order
- Opt_orlov
- Opt_osd_idle_ttl
- Opt_osd_request_timeout
- Opt_osdkeepalivetimeout
- Opt_osdtimeout
- Opt_othmask
- Opt_override_compr
- Opt_overriderockperm
- Opt_ownmask
- Opt_pagesize
- Opt_partition
- Opt_pass
- Opt_pcr
- Opt_pcrinfo
- Opt_pcrlock
- Opt_perm
- Opt_permit_directio
- Opt_persistent
- Opt_pgrp
- Opt_policydigest
- Opt_policyhandle
- Opt_pool_ns
- Opt_poolperm
- Opt_port
- Opt_port_rtpi
- Opt_posix
- Opt_posixacl
- Opt_posixpaths
- Opt_pqnoenforce
- Opt_pquota
- Opt_prefix
- Opt_privport
- Opt_prjjquota
- Opt_prjquota
- Opt_protect
- Opt_proto
- Opt_ptmxmode
- Opt_qnoenforce
- Opt_queue_depth
- Opt_quiet
- Opt_quota
- Opt_quota_account
- Opt_quota_off
- Opt_quota_on
- Opt_quota_quantum
- Opt_quota_unset
- Opt_quotadf
- Opt_rasize
- Opt_ratio
- Opt_rbytes
- Opt_rd_nullio
- Opt_rd_pages
- Opt_rdirplus
- Opt_rdma
- Opt_read_only
- Opt_read_write
- Opt_readdir_max_bytes
- Opt_readdir_max_entries
- Opt_readonly
- Opt_recover_session
- Opt_recovery
- Opt_ref_verify
- Opt_release_agent
- Opt_remotename
- Opt_removed
- Opt_require_active_mds
- Opt_res_all_tg_pt
- Opt_res_holder
- Opt_res_scope
- Opt_res_type
- Opt_rescan_uuid_tree
- Opt_reservation
- Opt_reserve_root
- Opt_reserved
- Opt_resgid
- Opt_resilient
- Opt_resize
- Opt_resize_nosize
- Opt_resuid
- Opt_resv_level
- Opt_resvport
- Opt_retrans
- Opt_rfdno
- Opt_rgrplvb
- Opt_rmode
- Opt_rodir
- Opt_root
- Opt_rootcontext
- Opt_rootdir
- Opt_rootfs
- Opt_rp_size
- Opt_rq_depth
- Opt_rsize
- Opt_rtdev
- Opt_rwpidforward
- Opt_sa_res_key
- Opt_sb
- Opt_scsi_channel_id
- Opt_scsi_host_id
- Opt_scsi_lun_id
- Opt_scsi_target_id
- Opt_seal
- Opt_sec
- Opt_sec_err
- Opt_sec_krb5
- Opt_sec_krb5i
- Opt_sec_krb5p
- Opt_sec_lanman
- Opt_sec_lkey
- Opt_sec_lkeyi
- Opt_sec_lkeyp
- Opt_sec_none
- Opt_sec_ntlmi
- Opt_sec_ntlmssp
- Opt_sec_ntlmsspi
- Opt_sec_ntlmv2
- Opt_sec_ntlmv2i
- Opt_sec_spkm
- Opt_sec_spkmi
- Opt_sec_spkmp
- Opt_sec_sys
- Opt_seclabel
- Opt_secret
- Opt_serverino
- Opt_servern
- Opt_session
- Opt_setgid
- Opt_setuid
- Opt_setuidfromacl
- Opt_setuids
- Opt_sfu
- Opt_share
- Opt_sharecache
- Opt_shortad
- Opt_shortname_lower
- Opt_shortname_mixed
- Opt_shortname_win95
- Opt_shortname_winnt
- Opt_showassoc
- Opt_showexec
- Opt_sign
- Opt_size
- Opt_skip_balance
- Opt_sloppy
- Opt_slot
- Opt_snapdirname
- Opt_snapshot
- Opt_soft
- Opt_softerr
- Opt_source
- Opt_space_cache
- Opt_space_cache_version
- Opt_spectator
- Opt_sq_depth
- Opt_srcaddr
- Opt_ssd
- Opt_ssd_spread
- Opt_stack
- Opt_statfs_percent
- Opt_statfs_quantum
- Opt_stats_mode
- Opt_strictexpire
- Opt_strictsync
- Opt_stripe
- Opt_subj_role
- Opt_subj_type
- Opt_subj_user
- Opt_subvol
- Opt_subvol_empty
- Opt_subvolid
- Opt_subvolrootid
- Opt_suiddir
- Opt_sunit
- Opt_swalloc
- Opt_swidth
- Opt_sysvgroups
- Opt_target_fabric
- Opt_target_lun
- Opt_target_node
- Opt_tcp
- Opt_tcp_nodelay
- Opt_template
- Opt_test_dummy_encryption
- Opt_thread_pool
- Opt_time_offset
- Opt_timeo
- Opt_timeout
- Opt_timeshift
- Opt_tpgt
- Opt_trans
- Opt_treelog
- Opt_type_44bsd
- Opt_type_hp
- Opt_type_nextstep
- Opt_type_nextstepcd
- Opt_type_old
- Opt_type_openstep
- Opt_type_sun
- Opt_type_sunos
- Opt_type_sunx86
- Opt_type_ufs2
- Opt_tz_utc
- Opt_udev_path
- Opt_udp
- Opt_uforget
- Opt_uid
- Opt_uid_eq
- Opt_uid_gt
- Opt_uid_lt
- Opt_uignore
- Opt_umask
- Opt_uname
- Opt_undelete
- Opt_unhide
- Opt_uni_xl_no
- Opt_uni_xl_yes
- Opt_unix
- Opt_update
- Opt_upgrade
- Opt_uqnoenforce
- Opt_uquota
- Opt_usebackuproot
- Opt_usefree
- Opt_user
- Opt_user_subvol_rm_allowed
- Opt_user_xattr
- Opt_userspace
- Opt_usrjquota
- Opt_usrquota
- Opt_utf8
- Opt_utf8_hack
- Opt_utf8_no
- Opt_utf8_yes
- Opt_ver
- Opt_verbose
- Opt_vers
- Opt_vers_2
- Opt_vers_3
- Opt_vers_4
- Opt_vers_4_0
- Opt_vers_4_1
- Opt_vers_4_2
- Opt_vers_err
- Opt_version
- Opt_volume
- Opt_warn_on_error
- Opt_wfdno
- Opt_whint
- Opt_wsize
- Opt_wsync
- Opt_xattr
- Opt_xip
- Opt_xprt_err
- Opt_xprt_rdma
- Opt_xprt_rdma6
- Opt_xprt_tcp
- Opt_xprt_tcp6
- Opt_xprt_udp
- Opt_xprt_udp6
- Optimedia
- OrigIV
- Otc04
- Otc32
- OtherController
- OtherMemType
- OtherPHY
- OtherPeripheral
- Ots08
- OtsIndirect
- OutBound_SRB
- OutByteDsp
- OutOfBandMonitor_t
- OutReg
- OutWordDsp
- Outb
- OutboundDoorbellReg
- Outgoing
- Output
- OutputSelectOffset
- OverDriveTable_t
- Overflowflag
- Overflowtrap
- Overlap
- OverwriteFlag
[..]