[..]
- I
- I0
- I1
- I100
- I10NM
- I10NM_GET_DIMMMTR
- I10NM_GET_IMC_BAR
- I10NM_GET_IMC_MMIO_OFFSET
- I10NM_GET_IMC_MMIO_SIZE
- I10NM_GET_MCDDRTCFG
- I10NM_GET_SCK_BAR
- I10NM_GET_SCK_MMIO_BASE
- I10NM_NUM_CHANNELS
- I10NM_NUM_DIMMS
- I10NM_NUM_IMC
- I10NM_REVISION
- I14
- I16A
- I16A_MASK
- I16L
- I16L_MASK
- I16_16
- I16_32
- I16_LSB
- I16_MSB
- I18N_H
- I2
- I21
- I210_DTXMXPKTSZ_DEFAULT
- I210_I_PHY_ID
- I210_RXPBSIZE_DEFAULT
- I210_RXPBSIZE_MASK
- I210_RXPBSIZE_PB_30KB
- I210_RXPBSIZE_PB_32KB
- I210_SR_QUEUES_NUM
- I210_TXPBSIZE_DEFAULT
- I210_TXPBSIZE_MASK
- I210_TXPBSIZE_PB0_8KB
- I210_TXPBSIZE_PB1_8KB
- I210_TXPBSIZE_PB2_4KB
- I210_TXPBSIZE_PB3_4KB
- I21145
- I217_CGFREG
- I217_CGFREG_ENABLE_MTA_RESET
- I217_EEE_ADVERTISEMENT
- I217_EEE_CAPABILITY
- I217_EEE_LP_ABILITY
- I217_EEE_PCS_STATUS
- I217_E_PHY_ID
- I217_INBAND_CTRL
- I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK
- I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT
- I217_LPI_GPIO_CTRL
- I217_LPI_GPIO_CTRL_AUTO_EN_LPI
- I217_MEMPWR
- I217_MEMPWR_DISABLE_SMB_RELEASE
- I217_PLL_CLOCK_GATE_MASK
- I217_PLL_CLOCK_GATE_REG
- I217_PROXY_CTRL
- I217_PROXY_CTRL_AUTO_DISABLE
- I217_RX_CONFIG
- I217_SxCTRL
- I217_SxCTRL_ENABLE_LPI_RESET
- I218_ULP_CONFIG1
- I218_ULP_CONFIG1_DISABLE_SMB_PERST
- I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST
- I218_ULP_CONFIG1_EN_ULP_LANPHYPC
- I218_ULP_CONFIG1_INBAND_EXIT
- I218_ULP_CONFIG1_IND
- I218_ULP_CONFIG1_RESET_TO_SMBUS
- I218_ULP_CONFIG1_START
- I218_ULP_CONFIG1_STICKY_ULP
- I218_ULP_CONFIG1_WOL_HOST
- I225_I_PHY_ID
- I225_RXPBSIZE_DEFAULT
- I225_TXPBSIZE_DEFAULT
- I2400MU_BLK_SIZE
- I2400MU_FW_FILE_NAME_v1_4
- I2400MU_FW_FILE_NAME_v1_5
- I2400MU_MAX_NOTIFICATION_LEN
- I2400MU_PL_SIZE_MAX
- I2400M_ACK_BARKER
- I2400M_BM_ACK_BUF_SIZE
- I2400M_BM_CMD_BUF_SIZE
- I2400M_BM_CMD_RAW
- I2400M_BRH_DIRECT_ACCESS
- I2400M_BRH_HASH_PAYLOAD_ONLY
- I2400M_BRH_JUMP
- I2400M_BRH_OPCODE_MASK
- I2400M_BRH_READ
- I2400M_BRH_RESPONSE_MASK
- I2400M_BRH_RESPONSE_REQUIRED
- I2400M_BRH_RESPONSE_SHIFT
- I2400M_BRH_SIGNATURE
- I2400M_BRH_SIGNATURE_MASK
- I2400M_BRH_SIGNATURE_SHIFT
- I2400M_BRH_SIGNED_JUMP
- I2400M_BRH_USE_CHECKSUM
- I2400M_BRH_WRITE
- I2400M_BRI_MAC_REINIT
- I2400M_BRI_NO_REBOOT
- I2400M_BRI_SOFT
- I2400M_BUS_RESET_RETRIES
- I2400M_COLD_RESET_BARKER
- I2400M_CS_IPV4
- I2400M_CS_IPV4_0
- I2400M_D2H_MSG_BARKER
- I2400M_FW_POKE
- I2400M_H2D_PREVIEW_BARKER
- I2400M_HDIv_MAJOR
- I2400M_HDIv_MINOR
- I2400M_HDIv_MINOR_2
- I2400M_L3L4_VERSION
- I2400M_MAX_MTU
- I2400M_MAX_PLS_IN_MSG
- I2400M_MEDIA_STATUS_LINK_DOWN
- I2400M_MEDIA_STATUS_LINK_RENEW
- I2400M_MEDIA_STATUS_LINK_UP
- I2400M_MS_ACCESSIBILITY_ERROR
- I2400M_MS_BAD_STATE
- I2400M_MS_BUSY
- I2400M_MS_CORRUPTED_TLV
- I2400M_MS_DONE_IN_PROGRESS
- I2400M_MS_DONE_OK
- I2400M_MS_ILLEGAL_VALUE
- I2400M_MS_INVALID_OP
- I2400M_MS_MAX
- I2400M_MS_MISSING_PARAMS
- I2400M_MS_NOT_READY_FOR_POWERSAVE
- I2400M_MS_NO_RF
- I2400M_MS_PRODUCTION_ERROR
- I2400M_MS_THERMAL_CRITICAL
- I2400M_MS_UNINITIALIZED
- I2400M_MS_UNKNOWN_ERROR
- I2400M_MS_VERSION_ERROR
- I2400M_MT_CMD_CONNECT
- I2400M_MT_CMD_DISCONNECT
- I2400M_MT_CMD_ENTER_POWERSAVE
- I2400M_MT_CMD_EXIT_IDLE
- I2400M_MT_CMD_INIT
- I2400M_MT_CMD_MODE_OF_OP
- I2400M_MT_CMD_MONITOR_CONTROL
- I2400M_MT_CMD_RESET_DEVICE
- I2400M_MT_CMD_RF_CONTROL
- I2400M_MT_CMD_SCAN
- I2400M_MT_CMD_SEND_EAP_RESPONSE
- I2400M_MT_CMD_TERMINATE
- I2400M_MT_GET_DEVICE_INFO
- I2400M_MT_GET_LINK_STATUS
- I2400M_MT_GET_LM_VERSION
- I2400M_MT_GET_MEDIA_STATUS
- I2400M_MT_GET_SCAN_RESULT
- I2400M_MT_GET_STATE
- I2400M_MT_GET_STATISTICS
- I2400M_MT_GET_TLS_OPERATION_RESULT
- I2400M_MT_INVALID
- I2400M_MT_REPORT_ALT_ACCEPT
- I2400M_MT_REPORT_EAP_REQUEST
- I2400M_MT_REPORT_EAP_RESTART
- I2400M_MT_REPORT_KEY_REQUEST
- I2400M_MT_REPORT_MASK
- I2400M_MT_REPORT_POWERSAVE_READY
- I2400M_MT_REPORT_SCAN_RESULT
- I2400M_MT_REPORT_STATE
- I2400M_MT_RESERVED
- I2400M_MT_SET_EAP_FAIL
- I2400M_MT_SET_EAP_KEY
- I2400M_MT_SET_EAP_SUCCESS
- I2400M_MT_SET_INIT_CONFIG
- I2400M_MT_SET_SCAN_PARAM
- I2400M_NBOOT_BARKER
- I2400M_PLD_SIZE_MASK
- I2400M_PLD_TYPE_MASK
- I2400M_PLD_TYPE_SHIFT
- I2400M_PL_ALIGN
- I2400M_PL_SIZE_MAX
- I2400M_PT_CTRL
- I2400M_PT_DATA
- I2400M_PT_EDATA
- I2400M_PT_ILLEGAL
- I2400M_PT_RESET_COLD
- I2400M_PT_RESET_WARM
- I2400M_PT_TRACE
- I2400M_RESET_TYPE_COLD
- I2400M_RESET_TYPE_WARM
- I2400M_RF_SWITCH_OFF
- I2400M_RF_SWITCH_ON
- I2400M_ROQ_LOG_LENGTH
- I2400M_RO_CIN
- I2400M_RO_CIN_SHIFT
- I2400M_RO_FBN
- I2400M_RO_FBN_SHIFT
- I2400M_RO_NEEDED
- I2400M_RO_SN
- I2400M_RO_SN_SHIFT
- I2400M_RO_TYPE
- I2400M_RO_TYPE_PACKET
- I2400M_RO_TYPE_PACKET_WS
- I2400M_RO_TYPE_RESET
- I2400M_RO_TYPE_SHIFT
- I2400M_RO_TYPE_WS
- I2400M_RT_BUS
- I2400M_RT_COLD
- I2400M_RT_WARM
- I2400M_SBOOT_BARKER
- I2400M_SBOOT_BARKER_6050
- I2400M_SS_CONFIG
- I2400M_SS_CONNECTING
- I2400M_SS_DATA_PATH_CONNECTED
- I2400M_SS_DEVICE_DISCONNECT
- I2400M_SS_DISCONNECTING
- I2400M_SS_IDLE
- I2400M_SS_INIT
- I2400M_SS_MAX
- I2400M_SS_OUT_OF_ZONE
- I2400M_SS_PRODUCTION
- I2400M_SS_READY
- I2400M_SS_RF_OFF
- I2400M_SS_RF_SHUTDOWN
- I2400M_SS_SCAN
- I2400M_SS_SLEEPACTIVE
- I2400M_SS_STANDBY
- I2400M_SS_UNINITIALIZED
- I2400M_SS_WIMAX_CONNECTED
- I2400M_TLV_CONFIG_D2H_DATA_FORMAT
- I2400M_TLV_CONFIG_DL_HOST_REORDER
- I2400M_TLV_CONFIG_IDLE_PARAMETERS
- I2400M_TLV_CONFIG_IDLE_TIMEOUT
- I2400M_TLV_DETAILED_DEVICE_INFO
- I2400M_TLV_DEVICE_RESET_TYPE
- I2400M_TLV_L4_MESSAGE_VERSIONS
- I2400M_TLV_MEDIA_STATUS
- I2400M_TLV_RF_OPERATION
- I2400M_TLV_RF_STATUS
- I2400M_TLV_SYSTEM_STATE
- I2400M_TLV_TYPE_WAKEUP_MODE
- I2400M_TX_BUF_SIZE
- I2400M_TX_MSG_SIZE
- I2400M_TX_PLD_MAX
- I2400M_TX_PLD_SIZE
- I2400M_TX_QLEN
- I2400M_TX_SKIP
- I2400M_TX_TIMEOUT
- I2400M_USB_BOOT_RETRIES
- I2400M_WAKEUP_DISABLED
- I2400M_WAKEUP_ENABLED
- I2400M_WARM_RESET_BARKER
- I28F004B3B
- I28F004B3T
- I28F008B3B
- I28F008B3T
- I28F008S5
- I28F008SA
- I28F016B3B
- I28F016B3T
- I28F016S3
- I28F016S5
- I28F160B3B
- I28F160B3T
- I28F160C3B
- I28F160C3T
- I28F160F3B
- I28F160F3T
- I28F320B3B
- I28F320B3T
- I28F400B3B
- I28F400B3T
- I28F640B3B
- I28F640B3T
- I28F640C3B
- I28F800B3B
- I28F800B3T
- I2B
- I2C
- I2C0
- I2C0_ALI
- I2C0_DTEI
- I2C0_REF
- I2C0_REG4_MASK
- I2C0_RESET
- I2C0_SCL
- I2C0_SCLK
- I2C0_SCL_B_MARK
- I2C0_SCL_C_MARK
- I2C0_SCL_D_MARK
- I2C0_SCL_E_MARK
- I2C0_SCL_MARK
- I2C0_SDA
- I2C0_SDATA
- I2C0_SDA_B_MARK
- I2C0_SDA_C_MARK
- I2C0_SDA_D_MARK
- I2C0_SDA_E_MARK
- I2C0_SDA_MARK
- I2C0_SHUT
- I2C0_TACKI
- I2C0_WAITI
- I2C1
- I2C10_DESC
- I2C11_DESC
- I2C12_DESC
- I2C13_DESC
- I2C14_DESC
- I2C1_ADDR
- I2C1_ALI
- I2C1_CK
- I2C1_CTRL
- I2C1_DTEI
- I2C1_K
- I2C1_R
- I2C1_RDATA
- I2C1_REF
- I2C1_REG0_MASK
- I2C1_RESET
- I2C1_SCL
- I2C1_SCLK
- I2C1_SCL_B_MARK
- I2C1_SCL_C_MARK
- I2C1_SCL_D_MARK
- I2C1_SCL_E_MARK
- I2C1_SCL_MARK
- I2C1_SDA
- I2C1_SDATA
- I2C1_SDA_B_MARK
- I2C1_SDA_C_MARK
- I2C1_SDA_D_MARK
- I2C1_SDA_E_MARK
- I2C1_SDA_MARK
- I2C1_SHUT
- I2C1_STAT
- I2C1_TACKI
- I2C1_USE_CAN0
- I2C1_WAITI
- I2C1_WDATA
- I2C2
- I2C2_ADDR
- I2C2_CK
- I2C2_CTRL
- I2C2_K
- I2C2_R
- I2C2_RDATA
- I2C2_RESET
- I2C2_SCLK
- I2C2_SCL_B_MARK
- I2C2_SCL_C_MARK
- I2C2_SCL_D_MARK
- I2C2_SCL_E_MARK
- I2C2_SCL_MARK
- I2C2_SDATA
- I2C2_SDA_B_MARK
- I2C2_SDA_C_MARK
- I2C2_SDA_D_MARK
- I2C2_SDA_E_MARK
- I2C2_SDA_MARK
- I2C2_SHUT
- I2C2_STAT
- I2C2_USE_CAN1
- I2C2_WDATA
- I2C3
- I2C3_ADDR
- I2C3_CK
- I2C3_CTRL
- I2C3_DESC
- I2C3_K
- I2C3_R
- I2C3_RDATA
- I2C3_RESET
- I2C3_SCL
- I2C3_SCL_B_MARK
- I2C3_SCL_C_MARK
- I2C3_SCL_D_MARK
- I2C3_SCL_E_MARK
- I2C3_SCL_MARK
- I2C3_SDA
- I2C3_SDA_B_MARK
- I2C3_SDA_C_MARK
- I2C3_SDA_D_MARK
- I2C3_SDA_E_MARK
- I2C3_SDA_MARK
- I2C3_STAT
- I2C3_WDATA
- I2C4
- I2C4_CK
- I2C4_DESC
- I2C4_K
- I2C4_R
- I2C4_RESET
- I2C4_SCL_B_MARK
- I2C4_SCL_C_MARK
- I2C4_SCL_D_MARK
- I2C4_SCL_E_MARK
- I2C4_SCL_MARK
- I2C4_SDA_B_MARK
- I2C4_SDA_C_MARK
- I2C4_SDA_D_MARK
- I2C4_SDA_E_MARK
- I2C4_SDA_MARK
- I2C5
- I2C5_DESC
- I2C5_K
- I2C5_R
- I2C5_SCL
- I2C5_SCL_B_MARK
- I2C5_SCL_C_MARK
- I2C5_SCL_D_MARK
- I2C5_SCL_MARK
- I2C5_SDA
- I2C5_SDA_B_MARK
- I2C5_SDA_C_MARK
- I2C5_SDA_D_MARK
- I2C5_SDA_MARK
- I2C6
- I2C6_DESC
- I2C6_K
- I2C6_R
- I2C7_DESC
- I2C8_DESC
- I2C9_DESC
- I2CAUX_DEFAULT_I2C_HW_SPEED
- I2CAUX_DEFAULT_I2C_SW_SPEED
- I2CAUX_ENGINE_TYPE_AUX
- I2CAUX_ENGINE_TYPE_I2C_DDC_HW
- I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW
- I2CAUX_ENGINE_TYPE_I2C_SW
- I2CAUX_ENGINE_TYPE_UNKNOWN
- I2CAUX_TRANSACTION_ACTION_DP_READ
- I2CAUX_TRANSACTION_ACTION_DP_WRITE
- I2CAUX_TRANSACTION_ACTION_I2C_READ
- I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST
- I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE
- I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT
- I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
- I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C
- I2CAUX_TRANSACTION_READ
- I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW
- I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY
- I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
- I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE
- I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION
- I2CAUX_TRANSACTION_STATUS_FAILED_NACK
- I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION
- I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR
- I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT
- I2CAUX_TRANSACTION_STATUS_SUCCEEDED
- I2CAUX_TRANSACTION_STATUS_UNKNOWN
- I2CAUX_TRANSACTION_WRITE
- I2CBMAG_BIT
- I2CBMAL_BIT
- I2CBMAL_EVENT
- I2CBMDZ_BIT
- I2CBMFI_BIT
- I2CBMFI_EVENT
- I2CBMIS_BIT
- I2CBMIS_EVENT
- I2CBMNA_BIT
- I2CBMNA_EVENT
- I2CBMTO_BIT
- I2CBMTO_EVENT
- I2CCCR
- I2CCLKCTRL
- I2CCR
- I2CDR
- I2CER_BUSY
- I2CER_RXB
- I2CER_TXB
- I2CER_TXE
- I2CESRFIIE_BIT
- I2CESRFI_BIT
- I2CESRFI_EVENT
- I2CESRTOIE_BIT
- I2CESRTO_BIT
- I2CESRTO_EVENT
- I2CFCR
- I2CFIER
- I2CFSR
- I2CMADDR
- I2CMAL_BIT
- I2CMAL_EVENT
- I2CMAR
- I2CMBB_BIT
- I2CMCF_BIT
- I2CMCF_EVENT
- I2CMCR
- I2CMIER
- I2CMIF_BIT
- I2CMSR
- I2CM_ON
- I2COM_MASTER
- I2COM_START
- I2CRFDR
- I2CRPT
- I2CRXTX
- I2CR_DMAEN
- I2CR_IEN
- I2CR_IEN_OPCODE_0
- I2CR_IEN_OPCODE_1
- I2CR_IIEN
- I2CR_MSTA
- I2CR_MTX
- I2CR_RSTA
- I2CR_TXAK
- I2CSAR
- I2CSCR
- I2CSIER
- I2CSSR
- I2CTFDR
- I2CTIMCTRL
- I2CT_ON
- I2C_0
- I2C_025K_DEV
- I2C_05K_DEV
- I2C_0_PHYS_BASE
- I2C_1
- I2C_16K_DEV
- I2C_1K_DEV
- I2C_1_MUX_1
- I2C_1_MUX_3
- I2C_1_PHYS_BASE
- I2C_2
- I2C_2BYTE_ADDR
- I2C_2K_DEV
- I2C_32K_DEV
- I2C_4K_DEV
- I2C_7XX_SCL
- I2C_7XX_SDA
- I2C_8K_DEV
- I2C_A
- I2C_ABORT
- I2C_ABORT_TIMEOUT
- I2C_ACK
- I2C_ACKERR
- I2C_ACK_INTR
- I2C_ACPI_MAX_SCAN_DEPTH
- I2C_ADAPTER_DESIGNWARE
- I2C_ADAPTER_PANEL
- I2C_ADAPTER_SMBUS
- I2C_ADAPTER_VGADDC
- I2C_ADC
- I2C_ADDR
- I2C_ADDRESS
- I2C_ADDRESS_PTAD
- I2C_ADDRESS_SLAD
- I2C_ADDRS
- I2C_ADDR_24C16
- I2C_ADDR_24C64
- I2C_ADDR_7BITS_COUNT
- I2C_ADDR_7BITS_MAX
- I2C_ADDR_BATTERY
- I2C_ADDR_CFG
- I2C_ADDR_CHG
- I2C_ADDR_DEVICE_ID
- I2C_ADDR_DVD0_CALC
- I2C_ADDR_DVD1_CALC
- I2C_ADDR_FG
- I2C_ADDR_HAPTIC
- I2C_ADDR_HIGH
- I2C_ADDR_HI_MASK
- I2C_ADDR_HI_SHIFT
- I2C_ADDR_LEN
- I2C_ADDR_LNBP22
- I2C_ADDR_LOW
- I2C_ADDR_LOW_MASK
- I2C_ADDR_LOW_SHIFT
- I2C_ADDR_MODE_TEN
- I2C_ADDR_MSK
- I2C_ADDR_MSP3400
- I2C_ADDR_MSP3400_ALT
- I2C_ADDR_MUIC
- I2C_ADDR_OFFSET_SLAVE
- I2C_ADDR_OFFSET_TEN_BIT
- I2C_ADDR_ONLY
- I2C_ADDR_PIC16C54
- I2C_ADDR_PMIC
- I2C_ADDR_RTC
- I2C_ADDR_STB0899
- I2C_ADDR_STB6100
- I2C_ADDR_TDA10046
- I2C_ADDR_TDA7432
- I2C_ADDR_TDA8425
- I2C_ADDR_TDA9840
- I2C_ADDR_TDA985x_H
- I2C_ADDR_TDA985x_L
- I2C_ADDR_TDA9874
- I2C_ADDR_TDA9875
- I2C_ADDR_TEA6300
- I2C_ADDR_TEA6420
- I2C_ADDR_TEMP
- I2C_ADDR_TOPSYS
- I2C_ADDR_TUA6034
- I2C_ADDR_VPD
- I2C_ADV7175
- I2C_ADV7176
- I2C_ALF_IS_SUSPENDED
- I2C_ALF_SUSPEND_REPORTED
- I2C_ALI
- I2C_AMD_PCI_MP2_H
- I2C_AQ_COMB
- I2C_AQ_COMB_READ_SECOND
- I2C_AQ_COMB_SAME_ADDR
- I2C_AQ_COMB_WRITE_FIRST
- I2C_AQ_COMB_WRITE_THEN_READ
- I2C_AQ_NO_CLK_STRETCH
- I2C_AQ_NO_ZERO_LEN
- I2C_AQ_NO_ZERO_LEN_READ
- I2C_AQ_NO_ZERO_LEN_WRITE
- I2C_ARBITRATE_INTR
- I2C_ARB_LOST
- I2C_AUTO_SUSPEND_DELAY
- I2C_AUX_CH
- I2C_A_ADC_ABORT
- I2C_A_ADC_ABORT_MASK
- I2C_A_ADC_ADD
- I2C_A_ADC_ADD_MASK
- I2C_A_ADC_BYTE
- I2C_A_ADC_BYTE_MASK
- I2C_A_ADC_LAST
- I2C_A_ADC_LAST_MASK
- I2C_A_ADC_READ
- I2C_A_ADC_RW_MASK
- I2C_A_ADC_START
- I2C_A_ADC_TRANS_MASK
- I2C_A_ADDR
- I2C_A_CONTROL_REG_BASE
- I2C_A_CTL_STATUS
- I2C_A_FIFO_DATA
- I2C_A_FIFO_STATUS
- I2C_A_FS_EN
- I2C_A_SW_CTL
- I2C_A_TIME_OUT_CNT
- I2C_BC_ENABLE
- I2C_BC_SCLK_THRESHOLD
- I2C_BC_SCLK_THRESHOLD_SHIFT
- I2C_BC_STATUS
- I2C_BC_STOP_COND
- I2C_BC_TERMINATE
- I2C_BEIE
- I2C_BER
- I2C_BIT_ACKD0
- I2C_BIT_ACKE0
- I2C_BIT_ALD0
- I2C_BIT_COI0
- I2C_BIT_DFC0
- I2C_BIT_EXC0
- I2C_BIT_IICBSY
- I2C_BIT_IICE0
- I2C_BIT_IICRSV
- I2C_BIT_LREL0
- I2C_BIT_MSTS0
- I2C_BIT_SMC0
- I2C_BIT_SPD0
- I2C_BIT_SPIE0
- I2C_BIT_SPT0
- I2C_BIT_STCEN
- I2C_BIT_STCF
- I2C_BIT_STD0
- I2C_BIT_STT0
- I2C_BIT_TRC0
- I2C_BIT_WREL0
- I2C_BIT_WTIM0
- I2C_BOARD_INFO
- I2C_BRCR
- I2C_BSC0
- I2C_BSC1
- I2C_BUFFER_LENGTH
- I2C_BURST_LEN
- I2C_BUSY
- I2C_BUS_CLEAR
- I2C_BUS_CLEAR_CNFG
- I2C_BUS_CLEAR_STATUS
- I2C_BUS_MONITOR
- I2C_BYTE_COUNT
- I2C_BYTE_COUNT_COUNT_MASK
- I2C_B_ADDR
- I2C_B_CONTROL_REG_BASE
- I2C_B_CTL_STATUS
- I2C_B_FIFO_DATA
- I2C_B_FIFO_STATUS
- I2C_B_FS_EN
- I2C_B_SW_CTL
- I2C_B_TIME_OUT_CNT
- I2C_CATEGORY
- I2C_CBUS
- I2C_CBUS_ADDR
- I2C_CCR
- I2C_CCR_CC_MASK
- I2C_CCR_FMSM
- I2C_CCR_MASK
- I2C_CCR_RESET_UMASK
- I2C_CCR_RESET_VALUE
- I2C_CHANNEL_OPERATION_CHANNEL_CLIENT_MAX_ALLOWED
- I2C_CHANNEL_OPERATION_CHANNEL_IN_USE
- I2C_CHANNEL_OPERATION_ENGINE_BUSY
- I2C_CHANNEL_OPERATION_FAILED
- I2C_CHANNEL_OPERATION_HW_REQUEST_I2C_BUS
- I2C_CHANNEL_OPERATION_IS_BUSY
- I2C_CHANNEL_OPERATION_NOT_GRANTED
- I2C_CHANNEL_OPERATION_NOT_STARTED
- I2C_CHANNEL_OPERATION_NO_HANDLE_PROVIDED
- I2C_CHANNEL_OPERATION_NO_RESPONSE
- I2C_CHANNEL_OPERATION_OUT_NB_OF_RETRIES
- I2C_CHANNEL_OPERATION_SUCCEEDED
- I2C_CHANNEL_OPERATION_TIMEOUT
- I2C_CHANNEL_OPERATION_WRONG_PARAMETER
- I2C_CHIP_ERRATA
- I2C_CLASS_DDC
- I2C_CLASS_DEPRECATED
- I2C_CLASS_HWMON
- I2C_CLASS_SPD
- I2C_CLEAR_ACK
- I2C_CLEAR_ALL
- I2C_CLEAR_ALL_INTS
- I2C_CLEAR_ARBITRATE
- I2C_CLEAR_END
- I2C_CLEAR_OVER
- I2C_CLEAR_RECEIVE
- I2C_CLEAR_SEND
- I2C_CLEAR_START
- I2C_CLIENTS_MAX
- I2C_CLIENT_END
- I2C_CLIENT_HOST_NOTIFY
- I2C_CLIENT_PEC
- I2C_CLIENT_SCCB
- I2C_CLIENT_SLAVE
- I2C_CLIENT_TEN
- I2C_CLIENT_WAKE
- I2C_CLKEN_OVERRIDE
- I2C_CLKFREQ_REG_ADDR
- I2C_CLK_DIVISOR
- I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT
- I2C_CLK_ENB
- I2C_CLK_RATIO
- I2C_CLOCK_AND_ENABLE
- I2C_CMB_RW_EN
- I2C_CMD_ADDR
- I2C_CMD_COUNT
- I2C_CMD_FORCELAUNCH
- I2C_CMD_IACK
- I2C_CMD_LEN
- I2C_CMD_RD_CONT
- I2C_CMD_READ
- I2C_CMD_READ_ACK
- I2C_CMD_READ_NACK
- I2C_CMD_SLEEP_MAX_US
- I2C_CMD_SLEEP_MIN_US
- I2C_CMD_START
- I2C_CMD_STOP
- I2C_CMD_WITH_ADDR
- I2C_CMD_WITH_START
- I2C_CMD_WITH_STOP
- I2C_CMD_WRITE
- I2C_CNFG
- I2C_CNFG_DEBOUNCE_CNT_SHIFT
- I2C_CNFG_MULTI_MASTER_MODE
- I2C_CNFG_NEW_MASTER_FSM
- I2C_CNFG_NEW_MASTER_SFM
- I2C_CNFG_PACKET_MODE_EN
- I2C_CNTL_0
- I2C_CNTL_1
- I2C_COMMAND
- I2C_COMMAND_ENGINE_DEFAULT
- I2C_COMMAND_ENGINE_HW
- I2C_COMMAND_ENGINE_SW
- I2C_COMMON_MASK_SH_LIST_DCE110
- I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE
- I2C_COMMON_MASK_SH_LIST_DCN2
- I2C_CON
- I2C_CONFIG
- I2C_CONFIG_LOAD
- I2C_CONFIG_LOAD_TIMEOUT
- I2C_CONTROL
- I2C_CONTROLC
- I2C_CONTROLLER_DISABLED
- I2C_CONTROLLER_ENABLED
- I2C_CONTROLLER_NAME_COUNT
- I2C_CONTROLLER_NAME_LIQUID0
- I2C_CONTROLLER_NAME_LIQUID1
- I2C_CONTROLLER_NAME_LIQUID_0
- I2C_CONTROLLER_NAME_LIQUID_1
- I2C_CONTROLLER_NAME_PLX
- I2C_CONTROLLER_NAME_SPARE
- I2C_CONTROLLER_NAME_VR_GFX
- I2C_CONTROLLER_NAME_VR_HBM
- I2C_CONTROLLER_NAME_VR_MEM
- I2C_CONTROLLER_NAME_VR_MVDD
- I2C_CONTROLLER_NAME_VR_SOC
- I2C_CONTROLLER_NAME_VR_VDDCI
- I2C_CONTROLLER_PORT_0
- I2C_CONTROLLER_PORT_1
- I2C_CONTROLLER_PORT_COUNT
- I2C_CONTROLLER_PROTOCOL_COUNT
- I2C_CONTROLLER_PROTOCOL_SPARE_0
- I2C_CONTROLLER_PROTOCOL_SPARE_1
- I2C_CONTROLLER_PROTOCOL_SPARE_2
- I2C_CONTROLLER_PROTOCOL_TMP_0
- I2C_CONTROLLER_PROTOCOL_TMP_1
- I2C_CONTROLLER_PROTOCOL_TMP_TMP102A
- I2C_CONTROLLER_PROTOCOL_VR_0
- I2C_CONTROLLER_PROTOCOL_VR_1
- I2C_CONTROLLER_PROTOCOL_VR_IR35217
- I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5
- I2C_CONTROLLER_SPEED_FAST
- I2C_CONTROLLER_SPEED_SLOW
- I2C_CONTROLLER_THROTTLER_COUNT
- I2C_CONTROLLER_THROTTLER_LIQUID0
- I2C_CONTROLLER_THROTTLER_LIQUID1
- I2C_CONTROLLER_THROTTLER_LIQUID_0
- I2C_CONTROLLER_THROTTLER_LIQUID_1
- I2C_CONTROLLER_THROTTLER_PLX
- I2C_CONTROLLER_THROTTLER_TYPE_NONE
- I2C_CONTROLLER_THROTTLER_VR_GFX
- I2C_CONTROLLER_THROTTLER_VR_HBM
- I2C_CONTROLLER_THROTTLER_VR_MEM
- I2C_CONTROLLER_THROTTLER_VR_MVDD
- I2C_CONTROLLER_THROTTLER_VR_SOC
- I2C_CONTROLLER_THROTTLER_VR_VDDCI
- I2C_CONTROLS
- I2C_CONTROL_ACKERR_DET_EN
- I2C_CONTROL_ADDR
- I2C_CONTROL_ASYNC_MODE
- I2C_CONTROL_BYTE_CNT
- I2C_CONTROL_CLK_EXT_EN
- I2C_CONTROL_CNTL_END
- I2C_CONTROL_CNTL_START
- I2C_CONTROL_DEV_ID
- I2C_CONTROL_DIR_CHANGE
- I2C_CONTROL_DMAACK_EN
- I2C_CONTROL_DMA_EN
- I2C_CONTROL_GET_DATA
- I2C_CONTROL_NACK
- I2C_CONTROL_READ
- I2C_CONTROL_REG
- I2C_CONTROL_RS
- I2C_CONTROL_SET_DATA
- I2C_CONTROL_TRANSFER_LEN_CHANGE
- I2C_CONTROL_WRAPPER
- I2C_CON_MASTER
- I2C_CON_RESTART
- I2C_CON_SLAVEDISABLE
- I2C_CON_SPEED_FAST
- I2C_CON_SPEED_STD
- I2C_COUNT
- I2C_CR
- I2C_CR_ACK_ENABLE
- I2C_CR_DDC1_ENABLE
- I2C_CR_DDC2B_ENABLE
- I2C_CR_DMA_RX_EN
- I2C_CR_DMA_SLE
- I2C_CR_DMA_TX_EN
- I2C_CR_FON
- I2C_CR_FRX
- I2C_CR_FS
- I2C_CR_FTX
- I2C_CR_INTERRUPT_ENABLE
- I2C_CR_LM
- I2C_CR_OM
- I2C_CR_PE
- I2C_CR_PERIPHERAL_ENABLE
- I2C_CR_RESET_UMASK
- I2C_CR_RESET_VALUE
- I2C_CR_SAM
- I2C_CR_SGCM
- I2C_CR_SM
- I2C_CR_START_ENABLE
- I2C_CR_STOP_ENABLE
- I2C_CR_TRANS_ENABLE
- I2C_CTL
- I2C_CTRL
- I2C_CTRL_CTRL
- I2C_CTRL_DIR
- I2C_CTRL_EN
- I2C_CTRL_IEN
- I2C_CTRL_INT
- I2C_CTRL_MODE
- I2C_CTRL_REG_ADDR
- I2C_D0
- I2C_D1
- I2C_DA
- I2C_DATA0
- I2C_DATA1
- I2C_DATA10
- I2C_DATA11
- I2C_DATA12
- I2C_DATA13
- I2C_DATA14
- I2C_DATA15
- I2C_DATA2
- I2C_DATA3
- I2C_DATA4
- I2C_DATA5
- I2C_DATA6
- I2C_DATA7
- I2C_DATA8
- I2C_DATA9
- I2C_DATACMD
- I2C_DATACMD_DAT
- I2C_DATACMD_DAT_MASK
- I2C_DATACMD_READ
- I2C_DATACMD_WRITE
- I2C_DATA_ADDR
- I2C_DATA_LEN
- I2C_DATA_REG
- I2C_DATA_REG_ADDR
- I2C_DATA_STEP
- I2C_DAVINCI_INTR_ALL
- I2C_DCM_DISABLE
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT
- I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK
- I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT
- I2C_DEFAULT_CLK_DIV
- I2C_DEFAULT_SPEED
- I2C_DELAY_LEN
- I2C_DEMOD_EN
- I2C_DESC_TYPE_CONFIG
- I2C_DESC_TYPE_CONFIG_KLUDGE
- I2C_DESC_TYPE_DEVICE
- I2C_DESC_TYPE_FIRMWARE_AUTO
- I2C_DESC_TYPE_FIRMWARE_BASIC
- I2C_DESC_TYPE_FIRMWARE_BLANK
- I2C_DESC_TYPE_INFO_BASIC
- I2C_DESC_TYPE_ION
- I2C_DESC_TYPE_STRING
- I2C_DESC_TYPE_WATCHPORT_CALIBRATION_DATA
- I2C_DESC_TYPE_WATCHPORT_VERSION
- I2C_DESIGNWARE_H
- I2C_DEVICE_CS2000
- I2C_DEVICE_CS4362A
- I2C_DEVICE_CS4398
- I2C_DEVICE_ID_ANALOG_DEVICES
- I2C_DEVICE_ID_ATMEL
- I2C_DEVICE_ID_ESPROS_PHOTONICS_AG
- I2C_DEVICE_ID_FLIR
- I2C_DEVICE_ID_FUJITSU_SEMICONDUCTOR
- I2C_DEVICE_ID_GOODIX_01F0
- I2C_DEVICE_ID_ITE_LENOVO_LEGION_Y720
- I2C_DEVICE_ID_LG_7010
- I2C_DEVICE_ID_LG_8001
- I2C_DEVICE_ID_NONE
- I2C_DEVICE_ID_NXP_SEMICONDUCTORS
- I2C_DEVICE_ID_NXP_SEMICONDUCTORS_1
- I2C_DEVICE_ID_NXP_SEMICONDUCTORS_2
- I2C_DEVICE_ID_NXP_SEMICONDUCTORS_3
- I2C_DEVICE_ID_O2MICRO
- I2C_DEVICE_ID_ON_SEMICONDUCTOR
- I2C_DEVICE_ID_RAMTRON_INTERNATIONAL
- I2C_DEVICE_ID_SPRINTEK_CORPORATION
- I2C_DEVICE_ID_STMICROELECTRONICS
- I2C_DEVICE_PCM1796
- I2C_DEVICE_WACOM
- I2C_DEVICE_WM8776
- I2C_DEV_ADDR_A0
- I2C_DEV_ADDR_A2
- I2C_DEV_ADDR_SET
- I2C_DEV_SEL
- I2C_DEV_SIZE
- I2C_DEV_UP_ADDR_REG_ADDR
- I2C_DIR
- I2C_DISABLE
- I2C_DMAR
- I2C_DMA_4G_MODE
- I2C_DMA_CLR_FLAG
- I2C_DMA_CON_RX
- I2C_DMA_CON_TX
- I2C_DMA_EN
- I2C_DMA_HARD_RST
- I2C_DMA_INT_FLAG_NONE
- I2C_DMA_START_EN
- I2C_DR
- I2C_DRIVER_NAME
- I2C_DRV_NAME
- I2C_DR_D_MASK
- I2C_DR_RESET_UMASK
- I2C_DR_RESET_VALUE
- I2C_DTEI
- I2C_DUMP_SKB
- I2C_DVD_OPT
- I2C_D_ADC_DAT_MASK
- I2C_D_ADC_REG_MASK
- I2C_EB
- I2C_EB_CPM2
- I2C_ECCR
- I2C_ECCR_CC_MASK
- I2C_ECCR_MASK
- I2C_ECCR_RESET_UMASK
- I2C_ECCR_RESET_VALUE
- I2C_EMMA2RH
- I2C_EMMA_CNT
- I2C_EMMA_CSEL
- I2C_EMMA_INT
- I2C_EMMA_INTM
- I2C_EMMA_REPSTART
- I2C_EMMA_SHR
- I2C_EMMA_STA
- I2C_EMMA_START
- I2C_EMMA_STOP
- I2C_EMMA_SVA
- I2C_EN
- I2C_ENAB
- I2C_ENABLE
- I2C_ENABLE_DISABLE
- I2C_ENABLE_ENABLE
- I2C_END_INTR
- I2C_ENSTATUS
- I2C_ENSTATUS_ENABLE
- I2C_ERR
- I2C_ERROR_MASK
- I2C_ERR_ALD
- I2C_ERR_ARBITRATION_LOST
- I2C_ERR_BERR
- I2C_ERR_NONE
- I2C_ERR_NO_ACK
- I2C_ERR_RX_BUFFER_OVERFLOW
- I2C_ERR_UNKNOWN_INTERRUPT
- I2C_ESTAT_FIFO_SZ
- I2C_ESTAT_HI_WATER
- I2C_ESTAT_LO_WATER
- I2C_ESTAT_M_SCL
- I2C_ESTAT_M_SDA
- I2C_ESTAT_PORT_BUSY
- I2C_ESTAT_SCL_IN_SY
- I2C_ESTAT_SDA_IN_SY
- I2C_ESTAT_SELF_BUSY
- I2C_ESTAT_S_SCL
- I2C_ESTAT_S_SDA
- I2C_ESTAT_VERSION
- I2C_EXTEND
- I2C_FAST_MODE
- I2C_FAST_MODE_DUTY
- I2C_FAST_MODE_FREQ
- I2C_FAST_MODE_PLUS_DUTY
- I2C_FAST_MODE_PLUS_FREQ
- I2C_FAST_PLUS_MODE
- I2C_FIFO_ADDR_CLR
- I2C_FIFO_CONTROL
- I2C_FIFO_CONTROL_RX_FLUSH
- I2C_FIFO_CONTROL_RX_TRIG
- I2C_FIFO_CONTROL_TX_FLUSH
- I2C_FIFO_CONTROL_TX_TRIG
- I2C_FIFO_DEEP
- I2C_FIFO_EMPTY_THLD
- I2C_FIFO_FULL_THLD
- I2C_FIFO_HI_LVL
- I2C_FIFO_LO_LVL
- I2C_FIFO_MAX
- I2C_FIFO_STATUS
- I2C_FIFO_STATUS_RX_MASK
- I2C_FIFO_STATUS_RX_SHIFT
- I2C_FIFO_STATUS_TX_MASK
- I2C_FIFO_STATUS_TX_SHIFT
- I2C_FLAG
- I2C_FREQUENCY
- I2C_FREQ_MODE_FAST
- I2C_FREQ_MODE_FAST_PLUS
- I2C_FREQ_MODE_HIGH_SPEED
- I2C_FREQ_MODE_STANDARD
- I2C_FSI_AND_INT_MASK
- I2C_FSI_CMD
- I2C_FSI_ESTAT
- I2C_FSI_FIFO
- I2C_FSI_INTS
- I2C_FSI_INT_COND
- I2C_FSI_INT_MASK
- I2C_FSI_MODE
- I2C_FSI_OR_INT_MASK
- I2C_FSI_PORT_BUSY
- I2C_FSI_RESET_ERR
- I2C_FSI_RESET_I2C
- I2C_FSI_RESET_SCL
- I2C_FSI_RESET_SDA
- I2C_FSI_RESID_LEN
- I2C_FSI_SET_SCL
- I2C_FSI_SET_SDA
- I2C_FSI_STAT
- I2C_FSI_WATER_MARK
- I2C_FS_START_CON
- I2C_FUNCS
- I2C_FUNC_10BIT_ADDR
- I2C_FUNC_I2C
- I2C_FUNC_NOSTART
- I2C_FUNC_PROTOCOL_MANGLING
- I2C_FUNC_SLAVE
- I2C_FUNC_SMBUS_BLOCK_DATA
- I2C_FUNC_SMBUS_BLOCK_PROC_CALL
- I2C_FUNC_SMBUS_BYTE
- I2C_FUNC_SMBUS_BYTE_DATA
- I2C_FUNC_SMBUS_EMUL
- I2C_FUNC_SMBUS_HOST_NOTIFY
- I2C_FUNC_SMBUS_I2C_BLOCK
- I2C_FUNC_SMBUS_PEC
- I2C_FUNC_SMBUS_PROC_CALL
- I2C_FUNC_SMBUS_QUICK
- I2C_FUNC_SMBUS_READ_BLOCK_DATA
- I2C_FUNC_SMBUS_READ_BYTE
- I2C_FUNC_SMBUS_READ_BYTE_DATA
- I2C_FUNC_SMBUS_READ_I2C_BLOCK
- I2C_FUNC_SMBUS_READ_WORD_DATA
- I2C_FUNC_SMBUS_WORD_DATA
- I2C_FUNC_SMBUS_WRITE_BLOCK_DATA
- I2C_FUNC_SMBUS_WRITE_BYTE
- I2C_FUNC_SMBUS_WRITE_BYTE_DATA
- I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
- I2C_FUNC_SMBUS_WRITE_WORD_DATA
- I2C_GMBUS
- I2C_GPIO
- I2C_HDMI
- I2C_HDMI_ADDR
- I2C_HEADER_10BIT_ADDR
- I2C_HEADER_CONTINUE_XFER
- I2C_HEADER_CONT_ON_NAK
- I2C_HEADER_IE_ENABLE
- I2C_HEADER_READ
- I2C_HEADER_REPEAT_START
- I2C_HEADER_SLAVE_ADDR_SHIFT
- I2C_HID_CMD
- I2C_HID_H
- I2C_HID_PWR_ON
- I2C_HID_PWR_SLEEP
- I2C_HID_QUIRK_BAD_INPUT_SIZE
- I2C_HID_QUIRK_BOGUS_IRQ
- I2C_HID_QUIRK_NO_IRQ_AFTER_RESET
- I2C_HID_QUIRK_RESET_ON_RESUME
- I2C_HID_QUIRK_SET_PWR_WAKEUP_DEV
- I2C_HID_READ_PENDING
- I2C_HID_RESET_PENDING
- I2C_HID_STARTED
- I2C_HSFIX_MISC_REG
- I2C_HSMCR
- I2C_HSMODE_CFG
- I2C_HS_MODE
- I2C_HS_NACKERR
- I2C_HW
- I2C_HW_BUFFER_SIZE_DCE
- I2C_HW_BUFFER_SIZE_DCE100
- I2C_HW_CAP
- I2C_HW_ENGINE_COMMON_REG_LIST
- I2C_HW_ENGINE_ID_MASK
- I2C_HW_LANE_MUX
- I2C_ICR
- I2C_ICR_INIT
- I2C_IDX_RX_P0
- I2C_IDX_RX_P1
- I2C_IDX_TX_P0
- I2C_IDX_TX_P1
- I2C_IDX_TX_P2
- I2C_IF_ADDRESS
- I2C_IF_RDATA
- I2C_IF_STATUS
- I2C_IF_WDATA
- I2C_IF_WLOCK
- I2C_IMSCR
- I2C_IN
- I2C_INT
- I2C_INTE
- I2C_INTERFACE_TIMING_0
- I2C_INTERFACE_TIMING_1
- I2C_INT_AK
- I2C_INT_ARBITRATION_LOST
- I2C_INT_BE_ACCESS
- I2C_INT_BE_OVERRUN
- I2C_INT_BUSY
- I2C_INT_BUS_CLR_DONE
- I2C_INT_CMD_COMP
- I2C_INT_DAT_REQ
- I2C_INT_EN
- I2C_INT_IDLE
- I2C_INT_INV_CMD
- I2C_INT_LOST_ARB
- I2C_INT_MASK
- I2C_INT_NACK
- I2C_INT_NO_ACK
- I2C_INT_PACKET_XFER_COMPLETE
- I2C_INT_PARITY
- I2C_INT_RX_FIFO_DATA_REQ
- I2C_INT_STATUS
- I2C_INT_STATUS_REG
- I2C_INT_STOP_ERR
- I2C_INT_TX_FIFO_DATA_REQ
- I2C_IOP3XX_H
- I2C_IO_CONFIG_OPEN_DRAIN
- I2C_IO_CONFIG_PUSH_PULL
- I2C_IRQ_ACK_CLEAR
- I2C_IRQ_MSK_ENABLE
- I2C_ISR_INIT
- I2C_IS_TPM2
- I2C_ITG3200_H_
- I2C_IT_BERR
- I2C_IT_MAL
- I2C_IT_MTD
- I2C_IT_MTDWS
- I2C_IT_RFSE
- I2C_IT_RFSR
- I2C_IT_RXFE
- I2C_IT_RXFF
- I2C_IT_RXFNF
- I2C_IT_STD
- I2C_IT_TXFE
- I2C_IT_TXFF
- I2C_IT_TXFNE
- I2C_IT_TXFOVR
- I2C_IT_WTSR
- I2C_KEYBOARD_QUIRKS
- I2C_KS0127_ADDON
- I2C_KS0127_ONBOARD
- I2C_LOCK_ROOT_ADAPTER
- I2C_LOCK_SEGMENT
- I2C_LO_ADDR_REG_ADDR
- I2C_LPC2K_DEV_PM_OPS
- I2C_LRB
- I2C_MAJOR
- I2C_MASTER
- I2C_MASTER_APP_STRT_LAT
- I2C_MASTER_DIS_FILT
- I2C_MASTER_DIS_MM
- I2C_MASTER_RD
- I2C_MASTER_WR
- I2C_MASTER_WRRD
- I2C_MAX_ADDR
- I2C_MAX_BYTES
- I2C_MAX_RETRIES
- I2C_MAX_WORDS
- I2C_MAX_XFER_SIZE
- I2C_MCR
- I2C_MCR_A7
- I2C_MCR_AM
- I2C_MCR_EA10
- I2C_MCR_LENGTH
- I2C_MCR_OP
- I2C_MCR_SB
- I2C_MCR_STOP
- I2C_MHL
- I2C_MINI_CORE
- I2C_MINORS
- I2C_MISR
- I2C_MODE
- I2C_MODE_CLKDIV
- I2C_MODE_DIAG
- I2C_MODE_END
- I2C_MODE_ENHANCED
- I2C_MODE_FAST
- I2C_MODE_PACE_ALLOW
- I2C_MODE_PORT
- I2C_MODE_STANDARD
- I2C_MODE_WRAP
- I2C_MODULE_PREFIX
- I2C_MONITOR
- I2C_MOT_FALSE
- I2C_MOT_TRUE
- I2C_MOT_UNDEF
- I2C_MSB_2B_MSK
- I2C_MSP_CONTROL
- I2C_MSP_DEM
- I2C_MSP_DSP
- I2C_MSTR_CONFIG_LOAD
- I2C_MST_ADDR
- I2C_MST_CNTL
- I2C_MST_CNTL_BURST_SIZE_SHIFT
- I2C_MST_CNTL_CMD_READ
- I2C_MST_CNTL_CMD_WRITE
- I2C_MST_CNTL_CYCLE_TRIGGER
- I2C_MST_CNTL_GEN_NACK
- I2C_MST_CNTL_GEN_START
- I2C_MST_CNTL_GEN_STOP
- I2C_MST_CNTL_STATUS
- I2C_MST_CNTL_STATUS_BUS_BUSY
- I2C_MST_CNTL_STATUS_NO_ACK
- I2C_MST_CNTL_STATUS_OKAY
- I2C_MST_CNTL_STATUS_TIMEOUT
- I2C_MST_CORE_CLKEN_OVR
- I2C_MST_DATA
- I2C_MST_FIFO_CONTROL
- I2C_MST_FIFO_CONTROL_RX_FLUSH
- I2C_MST_FIFO_CONTROL_RX_TRIG
- I2C_MST_FIFO_CONTROL_TX_FLUSH
- I2C_MST_FIFO_CONTROL_TX_TRIG
- I2C_MST_FIFO_STATUS
- I2C_MST_FIFO_STATUS_RX_MASK
- I2C_MST_FIFO_STATUS_RX_SHIFT
- I2C_MST_FIFO_STATUS_TX_MASK
- I2C_MST_FIFO_STATUS_TX_SHIFT
- I2C_MST_HYBRID_PADCTL
- I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV
- I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV
- I2C_MST_HYBRID_PADCTL_MODE_I2C
- I2C_MST_I2C0_TIMING
- I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ
- I2C_MST_I2C0_TIMING_TIMEOUT_CHECK
- I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT
- I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
- I2C_MUX_ARBITRATOR
- I2C_MUX_GATE
- I2C_MUX_GPIO_NO_IDLE
- I2C_MUX_LOCKED
- I2C_MUX_REG
- I2C_M_DMA_SAFE
- I2C_M_IGNORE_NAK
- I2C_M_NOSTART
- I2C_M_NO_RD_ACK
- I2C_M_RD
- I2C_M_RECV_LEN
- I2C_M_REV_DIR_ADDR
- I2C_M_STOP
- I2C_M_TEN
- I2C_NACK_ADDR_ER
- I2C_NACK_DATA0123_ER
- I2C_NACK_DATA_ER
- I2C_NACK_REG_ADDR_ER
- I2C_NAK_7B_ADDR_NOACK
- I2C_NAK_TXDATA_NOACK
- I2C_NAME_SIZE
- I2C_NOP
- I2C_NOSTOP
- I2C_NOT_SPECIFIED
- I2C_NO_ACK
- I2C_NO_OPERATION
- I2C_NO_STOP
- I2C_NUM_ADDRESSES
- I2C_N_VAL
- I2C_N_VAL_V2
- I2C_OAR1
- I2C_OAR1_ADD_MASK
- I2C_OAR1_RESET_UMASK
- I2C_OAR1_RESET_VALUE
- I2C_OAR2
- I2C_OAR2_ADD_MASK
- I2C_OAR2_FR_10_1667MHZ
- I2C_OAR2_FR_1667_2667MHZ
- I2C_OAR2_FR_25_10MHZ
- I2C_OAR2_FR_2667_40MHZ
- I2C_OAR2_FR_40_5333MHZ
- I2C_OAR2_FR_5333_66MHZ
- I2C_OAR2_FR_66_80MHZ
- I2C_OAR2_FR_80_100MHZ
- I2C_OAR2_FR_MASK
- I2C_OAR2_MASK
- I2C_OAR2_RESET_UMASK
- I2C_OAR2_RESET_VALUE
- I2C_OCTEON_EVENT_WAIT
- I2C_OFS_IIC0
- I2C_OFS_IICACT0
- I2C_OFS_IICC0
- I2C_OFS_IICCL0
- I2C_OFS_IICF0
- I2C_OFS_IICS0
- I2C_OFS_IICSE0
- I2C_OFS_IICX0
- I2C_OFS_SVA0
- I2C_OK
- I2C_OMAP_ERRATA_I207
- I2C_OMAP_ERRATA_I462
- I2C_ON_GOING
- I2C_OUT
- I2C_OUT_OPT
- I2C_OVERLAY
- I2C_OVER_AUX_DEFER_WA_DELAY
- I2C_OVER_INTR
- I2C_OWN_SLAVE_ADDRESS
- I2C_PACKET_HEADER_SIZE
- I2C_PACKET_TRANSFER_STATUS
- I2C_PAGE_SIZE
- I2C_PCA9564_PLATFORM_H
- I2C_PCA_ADR
- I2C_PCA_CHIP_9564
- I2C_PCA_CHIP_9665
- I2C_PCA_CON
- I2C_PCA_CON_146kHz
- I2C_PCA_CON_217kHz
- I2C_PCA_CON_288kHz
- I2C_PCA_CON_330kHz
- I2C_PCA_CON_36kHz
- I2C_PCA_CON_44kHz
- I2C_PCA_CON_59kHz
- I2C_PCA_CON_88kHz
- I2C_PCA_CON_AA
- I2C_PCA_CON_CR
- I2C_PCA_CON_ENSIO
- I2C_PCA_CON_SI
- I2C_PCA_CON_STA
- I2C_PCA_CON_STO
- I2C_PCA_DAT
- I2C_PCA_IADR
- I2C_PCA_ICOUNT
- I2C_PCA_IMODE
- I2C_PCA_IND
- I2C_PCA_INDPTR
- I2C_PCA_IPRESET
- I2C_PCA_ISCLH
- I2C_PCA_ISCLL
- I2C_PCA_ITO
- I2C_PCA_MODE_FAST
- I2C_PCA_MODE_FASTP
- I2C_PCA_MODE_STD
- I2C_PCA_MODE_TURBO
- I2C_PCA_OSC_PER
- I2C_PCA_STA
- I2C_PCA_TO
- I2C_PCF8584_H
- I2C_PCF_AAS
- I2C_PCF_ACK
- I2C_PCF_AD0
- I2C_PCF_BB
- I2C_PCF_BER
- I2C_PCF_CLK
- I2C_PCF_CLK12
- I2C_PCF_CLK3
- I2C_PCF_CLK443
- I2C_PCF_CLK6
- I2C_PCF_CLKREG
- I2C_PCF_ENI
- I2C_PCF_ES1
- I2C_PCF_ES2
- I2C_PCF_ESO
- I2C_PCF_IDLE
- I2C_PCF_INI
- I2C_PCF_INTREG
- I2C_PCF_LAB
- I2C_PCF_LRB
- I2C_PCF_OWNADR
- I2C_PCF_PIN
- I2C_PCF_REPSTART
- I2C_PCF_STA
- I2C_PCF_START
- I2C_PCF_STO
- I2C_PCF_STOP
- I2C_PCF_STS
- I2C_PCF_TRNS11
- I2C_PCF_TRNS15
- I2C_PCF_TRNS45
- I2C_PCF_TRNS90
- I2C_PEC
- I2C_PFC_MUX
- I2C_PFC_PIN
- I2C_PHYS_BASE
- I2C_PIO_MODE_MAX_LEN
- I2C_PM_TIMEOUT
- I2C_PNX_REGION_SIZE
- I2C_PNX_SPEED_KHZ_DEFAULT
- I2C_PNX_TIMEOUT_DEFAULT
- I2C_PORT_BUSY_RESET
- I2C_PORT_GPIO
- I2C_PORT_SVD_SCL
- I2C_PRODUCT_ID_CIRQUE_121F
- I2C_PRODUCT_ID_HANTICK_5288
- I2C_PRODUCT_ID_PHILIPS_1301
- I2C_PRODUCT_ID_RAYDIUM_3118
- I2C_PRODUCT_ID_RAYDIUM_4B33
- I2C_PRODUCT_ID_SYNAPTICS_SYNA2393
- I2C_PROTOCOL_SMBUS_ALERT
- I2C_PROTOCOL_SMBUS_HOST_NOTIFY
- I2C_PXA_DEV_PM_OPS
- I2C_PXA_SLAVE_ADDR
- I2C_RCAR_GEN1
- I2C_RCAR_GEN2
- I2C_RCAR_GEN3
- I2C_RD
- I2C_RDRW_IOCTL_MAX_MSGS
- I2C_RDWR
- I2C_RDWR_IOCTL_MAX_MSGS
- I2C_RD_OK
- I2C_RD_TRANAC_VALUE
- I2C_READ
- I2C_READY
- I2C_READ_CMD
- I2C_READ_DONE
- I2C_READ_READY_MASK
- I2C_RECEIVE_INTR
- I2C_REG
- I2C_REGS_ADDR
- I2C_REGS_CNT
- I2C_REGS_OFFSET
- I2C_REG_ADR
- I2C_REG_CHANMASK
- I2C_REG_CKH
- I2C_REG_CKL
- I2C_REG_CTL
- I2C_REG_IRQMASK
- I2C_REG_IRQSRC
- I2C_REG_RFL
- I2C_REG_RX
- I2C_REG_RXB
- I2C_REG_SOFTRESET
- I2C_REG_STFL
- I2C_REG_STS
- I2C_REG_SX8650_STAT
- I2C_REG_TFL
- I2C_REG_TOUCH0
- I2C_REG_TOUCH1
- I2C_REG_TX
- I2C_REG_TXB
- I2C_REG_TXS
- I2C_REPEATED_START
- I2C_RESET
- I2C_RESET_BUS_ERROR
- I2C_RESET_SLEEP_MAX_US
- I2C_RESET_SLEEP_MIN_US
- I2C_RESTART
- I2C_RETRIES
- I2C_RETRY
- I2C_RETRY_COUNT
- I2C_RFIFO_RESET
- I2C_RFR
- I2C_RFTR
- I2C_RISEFALL_TIME
- I2C_RISR
- I2C_RST
- I2C_RS_MUL_CNFG
- I2C_RS_MUL_TRIG
- I2C_RS_TRANSFER
- I2C_RW_READ
- I2C_RX
- I2C_RXFLR
- I2C_RX_ACK
- I2C_RX_FIFO
- I2C_SAA7111A
- I2C_SCL
- I2C_SCL_CTRL_PU
- I2C_SCL_IN
- I2C_SCL_OUT
- I2C_SCR
- I2C_SDA
- I2C_SDA_CTRL_PU
- I2C_SDA_IN
- I2C_SDA_OUT
- I2C_SEG_NUM
- I2C_SEND_INTR
- I2C_SEND_RESET_LENGTH_10
- I2C_SEND_RESET_LENGTH_9
- I2C_SETUP_TIME_LIMIT_DCE
- I2C_SETUP_TIME_LIMIT_DCN
- I2C_SF
- I2C_SIZE
- I2C_SLAVE
- I2C_SLAVE_ADDRESS
- I2C_SLAVE_ADDRESS_ADDRESS_MASK
- I2C_SLAVE_ADDRESS_RW
- I2C_SLAVE_ADDR_REG
- I2C_SLAVE_BYTELEN
- I2C_SLAVE_DEVICE_MAGIC
- I2C_SLAVE_EVENT_START_READ
- I2C_SLAVE_EVENT_START_WRITE
- I2C_SLAVE_EVENT_STOP
- I2C_SLAVE_FLAG_ADDR16
- I2C_SLAVE_FLAG_RO
- I2C_SLAVE_FORCE
- I2C_SLAVE_READ_PROCESSED
- I2C_SLAVE_READ_REQUESTED
- I2C_SLAVE_RX_DATA
- I2C_SLAVE_RX_END
- I2C_SLAVE_RX_FIFO_EMPTY
- I2C_SLAVE_RX_START
- I2C_SLAVE_STOP
- I2C_SLAVE_WRITE_RECEIVED
- I2C_SLAVE_WRITE_REQUESTED
- I2C_SLVT
- I2C_SLVX
- I2C_SL_ADDR1
- I2C_SL_ADDR2
- I2C_SL_CNFG
- I2C_SL_CNFG_NACK
- I2C_SL_CNFG_NEWSL
- I2C_SL_DELAY_COUNT
- I2C_SL_IRQ
- I2C_SL_NACK
- I2C_SL_NEWSL
- I2C_SL_RCVD
- I2C_SL_RESP
- I2C_SL_STATUS
- I2C_SMBUS
- I2C_SMBUS_BLOCK_DATA
- I2C_SMBUS_BLOCK_MAX
- I2C_SMBUS_BLOCK_PROC_CALL
- I2C_SMBUS_BYTE
- I2C_SMBUS_BYTE_DATA
- I2C_SMBUS_I2C_BLOCK_BROKEN
- I2C_SMBUS_I2C_BLOCK_DATA
- I2C_SMBUS_PROC_CALL
- I2C_SMBUS_QUICK
- I2C_SMBUS_READ
- I2C_SMBUS_WORD_DATA
- I2C_SMBUS_WRITE
- I2C_SOFT_RST
- I2C_SPD_100K
- I2C_SPD_400K
- I2C_SPEED_100
- I2C_SPEED_100K
- I2C_SPEED_100KHZ_BIT
- I2C_SPEED_1M
- I2C_SPEED_400
- I2C_SPEED_400K
- I2C_SPEED_5M
- I2C_SPEED_COUNT
- I2C_SPEED_FAST_100K
- I2C_SPEED_FAST_400K
- I2C_SPEED_FAST_50K
- I2C_SPEED_FAST_PLUS_1M
- I2C_SPEED_HIGH_1M
- I2C_SPEED_HIGH_2M
- I2C_SR
- I2C_SR1
- I2C_SR1_ADD10_IND
- I2C_SR1_ADSL_IND
- I2C_SR1_BTF_IND
- I2C_SR1_BUSY_IND
- I2C_SR1_EVF_IND
- I2C_SR1_MSL_IND
- I2C_SR1_RESET_UMASK
- I2C_SR1_RESET_VALUE
- I2C_SR1_SB_IND
- I2C_SR1_TRA_IND
- I2C_SR2
- I2C_SR2_AF_IND
- I2C_SR2_ARLO_IND
- I2C_SR2_BERR_IND
- I2C_SR2_DDC2BF_IND
- I2C_SR2_ENDAD_IND
- I2C_SR2_MASK
- I2C_SR2_RESET_UMASK
- I2C_SR2_RESET_VALUE
- I2C_SR2_SCLFAL_IND
- I2C_SR2_STOPF_IND
- I2C_SR_CAUSE
- I2C_SR_EDATA
- I2C_SR_EDEVICE
- I2C_SR_LENGTH
- I2C_SR_OP
- I2C_SR_STATUS
- I2C_SR_TYPE
- I2C_STANDARD_FREQ
- I2C_STANDARD_MODE
- I2C_START
- I2C_START_INTR
- I2C_START_LEN
- I2C_STATE_MASK
- I2C_STATUS
- I2C_STATUS_AB
- I2C_STATUS_ACK
- I2C_STATUS_ACTIVITY
- I2C_STATUS_AF_INIT
- I2C_STATUS_ALWAYS_1
- I2C_STATUS_APD
- I2C_STATUS_BC
- I2C_STATUS_BSY
- I2C_STATUS_BUS_ACTIVE
- I2C_STATUS_CAL_DATA
- I2C_STATUS_CHECK_BIN_CRC
- I2C_STATUS_CIS_I2C
- I2C_STATUS_DCM
- I2C_STATUS_DR
- I2C_STATUS_ERR
- I2C_STATUS_ERROR_MASK
- I2C_STATUS_EXCEPTION
- I2C_STATUS_FRAME_COUNT
- I2C_STATUS_FROM_INIT
- I2C_STATUS_I2C_CIS_STREAM_OFF
- I2C_STATUS_I2C_N_CMD_MISMATCH
- I2C_STATUS_I2C_N_CMD_OVER
- I2C_STATUS_INIF_INIT_STATE
- I2C_STATUS_NAK
- I2C_STATUS_OK
- I2C_STATUS_RFF
- I2C_STATUS_RFNE
- I2C_STATUS_TFE
- I2C_STATUS_TFNF
- I2C_STATUS_TX
- I2C_STATUS_WR_BUFFER_FULL
- I2C_STAT_ANY_INT
- I2C_STAT_ANY_RESP
- I2C_STAT_ARBLOST
- I2C_STAT_BE_ACCESS
- I2C_STAT_BE_OVERRUN
- I2C_STAT_BUSY
- I2C_STAT_CMD_COMP
- I2C_STAT_DAT_REQ
- I2C_STAT_ERR
- I2C_STAT_FIFO_COUNT
- I2C_STAT_IF
- I2C_STAT_INIT
- I2C_STAT_INV_CMD
- I2C_STAT_LOST_ARB
- I2C_STAT_MAX_PORT
- I2C_STAT_NACK
- I2C_STAT_PARITY
- I2C_STAT_PORT_BUSY
- I2C_STAT_SCL_IN
- I2C_STAT_SDA_IN
- I2C_STAT_SELF_BUSY
- I2C_STAT_STOP_ERR
- I2C_STAT_TIP
- I2C_STD_MODE_DUTY
- I2C_STOP
- I2C_STOP_BIT
- I2C_STOP_LEN
- I2C_STOP_ON_BUS
- I2C_STOP_TIMEOUT
- I2C_ST_START_CON
- I2C_SWITCH_WIDTH
- I2C_SW_RETRIES
- I2C_SW_TIMEOUT
- I2C_SW_TIMEOUT_DELAY
- I2C_SYNC
- I2C_TACKI
- I2C_TAR
- I2C_TARGET_ADDR
- I2C_TAR_EEPROM
- I2C_TAR_PWIC
- I2C_TAR_SPD
- I2C_TAR_THERMAL
- I2C_TASKADDRESS
- I2C_TASKLENGTH
- I2C_TDA8540
- I2C_TDA8540_ALT1
- I2C_TDA8540_ALT2
- I2C_TDA8540_ALT3
- I2C_TDA8540_ALT4
- I2C_TDA8540_ALT5
- I2C_TDA8540_ALT6
- I2C_TDA9840
- I2C_TEA6415C
- I2C_TEA6420_1
- I2C_TEA6420_2
- I2C_TENBIT
- I2C_TEN_BIT_ADDRESS
- I2C_TFR
- I2C_TFTR
- I2C_THIGH_SHIFT
- I2C_TIMEOUT
- I2C_TIMEOUT_MS
- I2C_TIMEOUT_MSEC
- I2C_TIME_CLR_VALUE
- I2C_TIME_DEFAULT_VALUE
- I2C_TIMING
- I2C_TOUCHPAD_QUIRKS
- I2C_TPI
- I2C_TPI_ADDR
- I2C_TRANSACTION_DONE
- I2C_TRANSAC_COMP
- I2C_TRANSAC_START
- I2C_TRANSFER
- I2C_TRANS_DONE
- I2C_TRANS_REPEATED_START
- I2C_TRANS_STOP
- I2C_TRIM_OPT
- I2C_TRX
- I2C_TUNER
- I2C_TX
- I2C_TXFLR
- I2C_TX_FIFO
- I2C_TX_MODE
- I2C_TYPE_EXYNOS5
- I2C_TYPE_EXYNOS7
- I2C_UNMASK_ACK
- I2C_UNMASK_ALL
- I2C_UNMASK_ARBITRATE
- I2C_UNMASK_END
- I2C_UNMASK_OVER
- I2C_UNMASK_RECEIVE
- I2C_UNMASK_SEND
- I2C_UNMASK_START
- I2C_UNMASK_TOTAL
- I2C_USB_ADAP_MAX
- I2C_V3_SELECT
- I2C_V6_SELECT
- I2C_VENDOR_ID_CIRQUE
- I2C_VENDOR_ID_GOODIX
- I2C_VENDOR_ID_HANTICK
- I2C_VENDOR_ID_PHILIPS
- I2C_VENDOR_ID_RAYDIUM
- I2C_VENDOR_ID_SYNAPTICS
- I2C_VERSION
- I2C_VOLUME
- I2C_WAITI
- I2C_WAIT_DELAY
- I2C_WAIT_RETRY
- I2C_WATERMARK_HI
- I2C_WATERMARK_LO
- I2C_WA_PWR_ITER
- I2C_WA_RETRY_CNT
- I2C_WFIFO_RESET
- I2C_WRITE
- I2C_WRITE_CMD
- I2C_WRITE_READ
- I2C_WRRD_TRANAC_VALUE
- I2C_WR_OK
- I2C_XFER_TIMEOUT
- I2C__MEM_PG
- I2C__MEM_PG__0
- I2C__MSG_DATA0_ADDR
- I2C__MSG_DATA0_PORT
- I2C__MSG_DATA0_RD08_ADDR
- I2C__MSG_DATA0_RD08_PORT
- I2C__MSG_DATA0_RD08_REG
- I2C__MSG_DATA0_WR08_ADDR
- I2C__MSG_DATA0_WR08_PORT
- I2C__MSG_DATA0_WR08_REG
- I2C__MSG_DATA0_WR08_SYNC
- I2C__MSG_DATA1_RD08_VAL
- I2C__MSG_DATA1_WR08_VAL
- I2C__MSG_RD08
- I2C__MSG_WR08
- I2GE5G_CCUT
- I2MCFG_BOUNDCTL
- I2MCFG_I2CMFAST
- I2MCFG_I2MLDSEQ
- I2MCFG_NORETRY
- I2MCFG_SCLOECTL
- I2MCFG_WAITCTL
- I2MCFG_WBUSYCTL
- I2MCSR_AUTOLD
- I2MCSR_DONE
- I2MCSR_EEMR
- I2MCSR_EEMW
- I2MCSR_NACK
- I2MOD_EN
- I2OEVTGET
- I2OEVTREG
- I2OGETIOPS
- I2OHRTGET
- I2OHTML
- I2OLCTGET
- I2OPARMGET
- I2OPARMSET
- I2OPASSTHRU
- I2OPASSTHRU32
- I2ORESCANCMD
- I2ORESETCMD
- I2OSWDEL
- I2OSWDL
- I2OSWUL
- I2OUSRCMD
- I2OVALIDATE
- I2OVER15
- I2OVER20
- I2OVERSION
- I2O_BUS_CARDBUS
- I2O_BUS_EISA
- I2O_BUS_ISA
- I2O_BUS_LOCAL
- I2O_BUS_NUBUS
- I2O_BUS_PCI
- I2O_BUS_PCMCIA
- I2O_BUS_UNKNOWN
- I2O_CLAIM_AUTHORIZED
- I2O_CLAIM_MANAGEMENT
- I2O_CLAIM_PRIMARY
- I2O_CLAIM_SECONDARY
- I2O_CLASS_ATE_PERIPHERAL
- I2O_CLASS_ATE_PORT
- I2O_CLASS_BUS_ADAPTER
- I2O_CLASS_BUS_ADAPTER_PORT
- I2O_CLASS_DDM
- I2O_CLASS_END
- I2O_CLASS_EXECUTIVE
- I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL
- I2O_CLASS_FIBRE_CHANNEL_PORT
- I2O_CLASS_FLOPPY_CONTROLLER
- I2O_CLASS_FLOPPY_DEVICE
- I2O_CLASS_LAN
- I2O_CLASS_MATCH_ANYCLASS
- I2O_CLASS_PEER_TRANSPORT
- I2O_CLASS_PEER_TRANSPORT_AGENT
- I2O_CLASS_RANDOM_BLOCK_STORAGE
- I2O_CLASS_SCSI_PERIPHERAL
- I2O_CLASS_SEQUENTIAL_STORAGE
- I2O_CLASS_VERSION_10
- I2O_CLASS_VERSION_11
- I2O_CLASS_WAN
- I2O_CMD_ADAPTER_ASSIGN
- I2O_CMD_ADAPTER_CLEAR
- I2O_CMD_ADAPTER_CONNECT
- I2O_CMD_ADAPTER_READ
- I2O_CMD_ADAPTER_RELEASE
- I2O_CMD_ADAPTER_RESET
- I2O_CMD_BIOS_INFO_SET
- I2O_CMD_BLOCK_CFLUSH
- I2O_CMD_BLOCK_MEJECT
- I2O_CMD_BLOCK_MLOCK
- I2O_CMD_BLOCK_MMOUNT
- I2O_CMD_BLOCK_MUNLOCK
- I2O_CMD_BLOCK_READ
- I2O_CMD_BLOCK_WRITE
- I2O_CMD_BOOT_DEVICE_SET
- I2O_CMD_CONFIG_VALIDATE
- I2O_CMD_CONN_SETUP
- I2O_CMD_DDM_DESTROY
- I2O_CMD_DDM_ENABLE
- I2O_CMD_DDM_QUIESCE
- I2O_CMD_DDM_RESET
- I2O_CMD_DDM_SUSPEND
- I2O_CMD_DEVICE_ASSIGN
- I2O_CMD_DEVICE_RELEASE
- I2O_CMD_HRT_GET
- I2O_CMD_LCT_NOTIFY
- I2O_CMD_OUTBOUND_INIT
- I2O_CMD_OUTBOUND_INIT_COMPLETE
- I2O_CMD_OUTBOUND_INIT_FAILED
- I2O_CMD_OUTBOUND_INIT_IN_PROGRESS
- I2O_CMD_OUTBOUND_INIT_REJECTED
- I2O_CMD_PATH_ENABLE
- I2O_CMD_PATH_QUIESCE
- I2O_CMD_PATH_RESET
- I2O_CMD_SCSI_ABORT
- I2O_CMD_SCSI_BUSRESET
- I2O_CMD_SCSI_EXEC
- I2O_CMD_STATIC_MF_CREATE
- I2O_CMD_STATIC_MF_RELEASE
- I2O_CMD_STATUS_GET
- I2O_CMD_SW_DOWNLOAD
- I2O_CMD_SW_REMOVE
- I2O_CMD_SW_UPLOAD
- I2O_CMD_SYS_ENABLE
- I2O_CMD_SYS_MODIFY
- I2O_CMD_SYS_QUIESCE
- I2O_CMD_SYS_TAB_SET
- I2O_CMD_UTIL_ABORT
- I2O_CMD_UTIL_CLAIM
- I2O_CMD_UTIL_CONFIG_DIALOG
- I2O_CMD_UTIL_DEVICE_RELEASE
- I2O_CMD_UTIL_DEVICE_RESERVE
- I2O_CMD_UTIL_EVT_ACK
- I2O_CMD_UTIL_EVT_REGISTER
- I2O_CMD_UTIL_LOCK
- I2O_CMD_UTIL_LOCK_RELEASE
- I2O_CMD_UTIL_NOP
- I2O_CMD_UTIL_PARAMS_GET
- I2O_CMD_UTIL_PARAMS_SET
- I2O_CMD_UTIL_RELEASE
- I2O_CMD_UTIL_REPLY_FAULT_NOTIFY
- I2O_COMMAND_SIZE
- I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION
- I2O_DEVICE_RESET
- I2O_DMA1_CFG
- I2O_DPT_FLASH_FRAG_SIZE
- I2O_DPT_FLASH_READ
- I2O_DPT_FLASH_WRITE
- I2O_DPT_SG_FLAG_INTERPRET
- I2O_DPT_SG_FLAG_PHYSICAL
- I2O_DSC_BAD_KEY
- I2O_DSC_CHAIN_BUFFER_TOO_LARGE
- I2O_DSC_DEVICE_BUSY
- I2O_DSC_DEVICE_LOCKED
- I2O_DSC_DEVICE_NOT_AVAILABLE
- I2O_DSC_DEVICE_RESET
- I2O_DSC_INAPPROPRIATE_FUNCTION
- I2O_DSC_INSUFFICIENT_RESOURCE_HARD
- I2O_DSC_INSUFFICIENT_RESOURCE_SOFT
- I2O_DSC_INVALID_INITIATOR_ADDRESS
- I2O_DSC_INVALID_MESSAGE_FLAGS
- I2O_DSC_INVALID_OFFSET
- I2O_DSC_INVALID_PARAMETER
- I2O_DSC_INVALID_REQUEST
- I2O_DSC_INVALID_TARGET_ADDRESS
- I2O_DSC_MESSAGE_TOO_LARGE
- I2O_DSC_MESSAGE_TOO_SMALL
- I2O_DSC_MISSING_PARAMETER
- I2O_DSC_NO_SUCH_PAGE
- I2O_DSC_REPLY_BUFFER_FULL
- I2O_DSC_SUCCESS
- I2O_DSC_TCL_ERROR
- I2O_DSC_TIMEOUT
- I2O_DSC_UNKNOWN_ERROR
- I2O_DSC_UNKNOWN_FUNCTION
- I2O_DSC_UNSUPPORTED_FUNCTION
- I2O_DSC_UNSUPPORTED_VERSION
- I2O_EVT_CAPABILITY_CHANGED
- I2O_EVT_CAPABILITY_OTHER
- I2O_EVT_DATA_SIZE
- I2O_EVT_GEN_WARNING_ERROR_THRESHOLD
- I2O_EVT_GEN_WARNING_MEDIA_FAULT
- I2O_EVT_GEN_WARNING_NORMAL
- I2O_EVT_IND_BSA_CAPACITY_CHANGE
- I2O_EVT_IND_BSA_SCSI_SMART
- I2O_EVT_IND_BSA_VOLUME_LOAD
- I2O_EVT_IND_BSA_VOLUME_UNLOAD
- I2O_EVT_IND_BSA_VOLUME_UNLOAD_REQ
- I2O_EVT_IND_CAPABILITY_CHANGE
- I2O_EVT_IND_CONFIGURATION_FLAG
- I2O_EVT_IND_DEVICE_RESET
- I2O_EVT_IND_DEVICE_STATE
- I2O_EVT_IND_EVT_MASK_MODIFIED
- I2O_EVT_IND_EXEC_ADAPTER_FAULT
- I2O_EVT_IND_EXEC_CONNECTION_FAIL
- I2O_EVT_IND_EXEC_DDM_AVAILABILITY
- I2O_EVT_IND_EXEC_HW_FAIL
- I2O_EVT_IND_EXEC_MODIFIED_LCT
- I2O_EVT_IND_EXEC_NEW_LCT_ENTRY
- I2O_EVT_IND_EXEC_POWER_FAIL
- I2O_EVT_IND_EXEC_RESET_IMMINENT
- I2O_EVT_IND_EXEC_RESET_PENDING
- I2O_EVT_IND_EXEC_RESOURCE_LIMITS
- I2O_EVT_IND_EXEC_XCT_CHANGE
- I2O_EVT_IND_FIELD_MODIFIED
- I2O_EVT_IND_GENERAL_WARNING
- I2O_EVT_IND_LOCK_RELEASE
- I2O_EVT_IND_STATE_CHANGE
- I2O_EVT_IND_VENDOR_EVT
- I2O_EVT_Q_LEN
- I2O_EVT_SENSOR_STATE_CHANGED
- I2O_EVT_STATE_CHANGE_FAILED
- I2O_EVT_STATE_CHANGE_FAULTED
- I2O_EVT_STATE_CHANGE_NA_NO_RECOVER
- I2O_EVT_STATE_CHANGE_NA_RECOVER
- I2O_EVT_STATE_CHANGE_NORMAL
- I2O_EVT_STATE_CHANGE_QUIESCE_REQUEST
- I2O_EVT_STATE_CHANGE_RESTART
- I2O_EVT_STATE_CHANGE_SUSPENDED
- I2O_HBA_BUS_RESET
- I2O_HEADER_TEMPLATE
- I2O_IBDB_CLEAR
- I2O_IBDB_SET
- I2O_IBPOST_Q
- I2O_INTERRUPT_PENDING_B
- I2O_INT_MASK
- I2O_INT_STATUS
- I2O_IOPIM_P0EM
- I2O_IOPIM_P0SNE
- I2O_IOPIM_P1EM
- I2O_IOPIM_P1SNE
- I2O_MAGIC_NUMBER
- I2O_MAJOR
- I2O_MAX_MANAGERS
- I2O_MESSAGE_SIZE
- I2O_MINOR
- I2O_OBPOST_Q
- I2O_PARAMS_FIELD_GET
- I2O_PARAMS_FIELD_SET
- I2O_PARAMS_LIST_GET
- I2O_PARAMS_LIST_SET
- I2O_PARAMS_MORE_GET
- I2O_PARAMS_ROW_ADD
- I2O_PARAMS_ROW_DELETE
- I2O_PARAMS_SIZE_GET
- I2O_PARAMS_STATUS_BAD_KEY_ABORT
- I2O_PARAMS_STATUS_BAD_KEY_CONTINUE
- I2O_PARAMS_STATUS_BUFFER_FULL
- I2O_PARAMS_STATUS_BUFFER_TOO_SMALL
- I2O_PARAMS_STATUS_FIELD_UNREADABLE
- I2O_PARAMS_STATUS_FIELD_UNWRITEABLE
- I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS
- I2O_PARAMS_STATUS_INVALID_GROUP_ID
- I2O_PARAMS_STATUS_INVALID_OPERATION
- I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP
- I2O_PARAMS_STATUS_NO_KEY_FIELD
- I2O_PARAMS_STATUS_NO_SUCH_FIELD
- I2O_PARAMS_STATUS_OPERATION_ERROR
- I2O_PARAMS_STATUS_SCALAR_ERROR
- I2O_PARAMS_STATUS_SUCCESS
- I2O_PARAMS_STATUS_TABLE_ERROR
- I2O_PARAMS_STATUS_WRONG_GROUP_TYPE
- I2O_PARAMS_TABLE_CLEAR
- I2O_PARAMS_TABLE_GET
- I2O_POST_WAIT_OK
- I2O_POST_WAIT_TIMEOUT
- I2O_PRIVATE_MSG
- I2O_REG_ENABLE
- I2O_REPLY_STATUS_ABORT_DIRTY
- I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER
- I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER
- I2O_REPLY_STATUS_ERROR_DIRTY
- I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER
- I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER
- I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY
- I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER
- I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER
- I2O_REPLY_STATUS_PROGRESS_REPORT
- I2O_REPLY_STATUS_SUCCESS
- I2O_REPLY_STATUS_TRANSACTION_ERROR
- I2O_RTN_ADAPTER_ALREADY_INIT
- I2O_RTN_ADPTR_NOT_REGISTERED
- I2O_RTN_FREE_Q_EMPTY
- I2O_RTN_MALLOC_ERROR
- I2O_RTN_MSG_REPLY_TIMEOUT
- I2O_RTN_NOT_INIT
- I2O_RTN_NO_ERROR
- I2O_RTN_NO_FIRM_VER
- I2O_RTN_NO_LINK_SPEED
- I2O_RTN_NO_STATUS
- I2O_RTN_TCB_ERROR
- I2O_RTN_TRANSACTION_ERROR
- I2O_SCSI_DEVICE_DSC_MASK
- I2O_SCSI_DSC_ADAPTER_BUSY
- I2O_SCSI_DSC_AUTOSENSE_FAILED
- I2O_SCSI_DSC_BDR_MESSAGE_SENT
- I2O_SCSI_DSC_BUS_BUSY
- I2O_SCSI_DSC_CDB_RECEIVED
- I2O_SCSI_DSC_COMMAND_TIMEOUT
- I2O_SCSI_DSC_COMPLETE_WITH_ERROR
- I2O_SCSI_DSC_DATA_OVERRUN
- I2O_SCSI_DSC_DEVICE_NOT_PRESENT
- I2O_SCSI_DSC_FUNCTION_UNAVAILABLE
- I2O_SCSI_DSC_IDE_MESSAGE_SENT
- I2O_SCSI_DSC_INVALID_CDB
- I2O_SCSI_DSC_LUN_ALREADY_ENABLED
- I2O_SCSI_DSC_LUN_INVALID
- I2O_SCSI_DSC_MASK
- I2O_SCSI_DSC_MESSAGE_RECEIVED
- I2O_SCSI_DSC_MR_MESSAGE_RECEIVED
- I2O_SCSI_DSC_NO_ADAPTER
- I2O_SCSI_DSC_NO_NEXUS
- I2O_SCSI_DSC_PARITY_ERROR_FAILURE
- I2O_SCSI_DSC_PATH_INVALID
- I2O_SCSI_DSC_PROVIDE_FAILURE
- I2O_SCSI_DSC_QUEUE_FROZEN
- I2O_SCSI_DSC_REQUEST_ABORTED
- I2O_SCSI_DSC_REQUEST_INVALID
- I2O_SCSI_DSC_REQUEST_LENGTH_ERROR
- I2O_SCSI_DSC_REQUEST_TERMINATED
- I2O_SCSI_DSC_RESOURCE_UNAVAILABLE
- I2O_SCSI_DSC_SCSI_BUS_RESET
- I2O_SCSI_DSC_SCSI_IID_INVALID
- I2O_SCSI_DSC_SCSI_TID_INVALID
- I2O_SCSI_DSC_SELECTION_TIMEOUT
- I2O_SCSI_DSC_SEQUENCE_FAILURE
- I2O_SCSI_DSC_SUCCESS
- I2O_SCSI_DSC_UNABLE_TO_ABORT
- I2O_SCSI_DSC_UNABLE_TO_TERMINATE
- I2O_SCSI_DSC_UNACKNOWLEDGED_EVENT
- I2O_SCSI_DSC_UNEXPECTED_BUS_FREE
- I2O_SNFORMAT_ASCII
- I2O_SNFORMAT_BINARY
- I2O_SNFORMAT_DDM
- I2O_SNFORMAT_IEEE_REG128
- I2O_SNFORMAT_IEEE_REG64
- I2O_SNFORMAT_LAN48_MAC
- I2O_SNFORMAT_LAN64_MAC
- I2O_SNFORMAT_UNICODE
- I2O_SNFORMAT_UNKNOWN
- I2O_SNFORMAT_UNKNOWN2
- I2O_SNFORMAT_WAN
- I2O_SOFTWARE_MODULE_IOP_CONFIG
- I2O_SOFTWARE_MODULE_IOP_PRIVATE
- I2O_SOFTWARE_MODULE_IRTOS
- I2O_SUBCLASS_HDM
- I2O_SUBCLASS_ISM
- I2O_SUBCLASS_i960
- I2O_VENDOR_DPT
- I2S
- I2S0
- I2S0_BCLK
- I2S0_CNTL__I2S0_ENABLE_MASK
- I2S0_CNTL__I2S0_ENABLE__SHIFT
- I2S0_CNTL__I2S0_FIFO_START_ADDR_MASK
- I2S0_CNTL__I2S0_FIFO_START_ADDR__SHIFT
- I2S0_CNTL__I2S0_LRCLK_POLARITY_MASK
- I2S0_CNTL__I2S0_LRCLK_POLARITY__SHIFT
- I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT_MASK
- I2S0_CNTL__I2S0_SAMPLE_ALIGNMENT__SHIFT
- I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER_MASK
- I2S0_CNTL__I2S0_SAMPLE_BIT_ORDER__SHIFT
- I2S0_CNTL__I2S0_WORD_ALIGNMENT_MASK
- I2S0_CNTL__I2S0_WORD_ALIGNMENT__SHIFT
- I2S0_CNTL__I2S0_WORD_SIZE_MASK
- I2S0_CNTL__I2S0_WORD_SIZE__SHIFT
- I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET_MASK
- I2S0_CRC_TEST_CNTL__I2S0_CRC_SOFT_RESET__SHIFT
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN_MASK
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_CONT_EN__SHIFT
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN_MASK
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_EN__SHIFT
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES_MASK
- I2S0_CRC_TEST_CNTL__I2S0_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT
- I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0_MASK
- I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA0__SHIFT
- I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1_MASK
- I2S0_CRC_TEST_DATA_01__I2S0_CRC_TEST_DATA1__SHIFT
- I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2_MASK
- I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA2__SHIFT
- I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3_MASK
- I2S0_CRC_TEST_DATA_23__I2S0_CRC_TEST_DATA3__SHIFT
- I2S0_DIN0
- I2S0_DIV
- I2S0_DOUT0
- I2S0_HD_EN_W_NAME
- I2S0_MCLK
- I2S0_MCLK_EN_W_NAME
- I2S0_SPDIF0_SOFT_RESET
- I2S0_SPDIF0_SOFT_RESET_0
- I2S0_SPDIF0_SOFT_RESET_1
- I2S0_STATUS__I2S0_DATA_RDY_MASK
- I2S0_STATUS__I2S0_DATA_RDY__SHIFT
- I2S0_STATUS__I2S0_SAMPLE_RATE_MASK
- I2S0_STATUS__I2S0_SAMPLE_RATE__SHIFT
- I2S0_STATUS__STREAM0_AUDIO_ENABLE_MASK
- I2S0_STATUS__STREAM0_AUDIO_ENABLE__SHIFT
- I2S0_STATUS__STREAM0_IDLE_MASK
- I2S0_STATUS__STREAM0_IDLE__SHIFT
- I2S0_WCLK_MUX
- I2S0_WS
- I2S1
- I2S1_BCLK
- I2S1_BCLK_SW_CG_MASK
- I2S1_BCLK_SW_CG_MASK_SFT
- I2S1_BCLK_SW_CG_SFT
- I2S1_CNTL__I2S1_ENABLE_MASK
- I2S1_CNTL__I2S1_ENABLE__SHIFT
- I2S1_CNTL__I2S1_FIFO_START_ADDR_MASK
- I2S1_CNTL__I2S1_FIFO_START_ADDR__SHIFT
- I2S1_CNTL__I2S1_LRCLK_POLARITY_MASK
- I2S1_CNTL__I2S1_LRCLK_POLARITY__SHIFT
- I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT_MASK
- I2S1_CNTL__I2S1_SAMPLE_ALIGNMENT__SHIFT
- I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER_MASK
- I2S1_CNTL__I2S1_SAMPLE_BIT_ORDER__SHIFT
- I2S1_CNTL__I2S1_WORD_ALIGNMENT_MASK
- I2S1_CNTL__I2S1_WORD_ALIGNMENT__SHIFT
- I2S1_CNTL__I2S1_WORD_SIZE_MASK
- I2S1_CNTL__I2S1_WORD_SIZE__SHIFT
- I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET_MASK
- I2S1_CRC_TEST_CNTL__I2S1_CRC_SOFT_RESET__SHIFT
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN_MASK
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_CONT_EN__SHIFT
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN_MASK
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_EN__SHIFT
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES_MASK
- I2S1_CRC_TEST_CNTL__I2S1_CRC_TEST_NUMBER_OF_SAMPLES__SHIFT
- I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0_MASK
- I2S1_CRC_TEST_DATA_0__I2S1_CRC_TEST_DATA0__SHIFT
- I2S1_DIN0
- I2S1_DIV
- I2S1_DOUT0
- I2S1_HD_EN_MASK
- I2S1_HD_EN_MASK_SFT
- I2S1_HD_EN_SFT
- I2S1_HD_EN_W_NAME
- I2S1_MCLK
- I2S1_MCLK_EN_W_NAME
- I2S1_MODE_I2S
- I2S1_MODE_LEFT_J
- I2S1_MODE_MASK
- I2S1_MODE_RIGHT_J
- I2S1_MS_MODE
- I2S1_SEL_O03_O04
- I2S1_SEL_O28_O29
- I2S1_SOFT_RESET
- I2S1_SOFT_RESET_0
- I2S1_SOFT_RESET_1
- I2S1_STATUS__I2S1_DATA_RDY_MASK
- I2S1_STATUS__I2S1_DATA_RDY__SHIFT
- I2S1_STATUS__I2S1_SAMPLE_RATE_MASK
- I2S1_STATUS__I2S1_SAMPLE_RATE__SHIFT
- I2S1_STATUS__STREAM1_AUDIO_ENABLE_MASK
- I2S1_STATUS__STREAM1_AUDIO_ENABLE__SHIFT
- I2S1_STATUS__STREAM1_IDLE_MASK
- I2S1_STATUS__STREAM1_IDLE__SHIFT
- I2S1_WCLK_MUX
- I2S1_WS
- I2S2
- I2S2_32BIT_EN_MASK
- I2S2_32BIT_EN_MASK_SFT
- I2S2_32BIT_EN_SFT
- I2S2_BCLK_SW_CG_MASK
- I2S2_BCLK_SW_CG_MASK_SFT
- I2S2_BCLK_SW_CG_SFT
- I2S2_DIV
- I2S2_EN_MASK
- I2S2_EN_MASK_SFT
- I2S2_EN_SFT
- I2S2_FMT_MASK
- I2S2_FMT_MASK_SFT
- I2S2_FMT_SFT
- I2S2_HD_EN_MASK
- I2S2_HD_EN_MASK_SFT
- I2S2_HD_EN_SFT
- I2S2_HD_EN_W_NAME
- I2S2_LR_SWAP_MASK
- I2S2_LR_SWAP_MASK_SFT
- I2S2_LR_SWAP_SFT
- I2S2_MCLK_EN_W_NAME
- I2S2_OUT_MODE_MASK
- I2S2_OUT_MODE_MASK_SFT
- I2S2_OUT_MODE_SFT
- I2S2_SEL_O03_O04_MASK
- I2S2_SEL_O03_O04_MASK_SFT
- I2S2_SEL_O03_O04_SFT
- I2S2_SEL_O19_O20_MASK
- I2S2_SEL_O19_O20_MASK_SFT
- I2S2_SEL_O19_O20_SFT
- I2S2_WCLK_MUX
- I2S2_WLEN_MASK
- I2S2_WLEN_MASK_SFT
- I2S2_WLEN_SFT
- I2S3
- I2S3_BCK_INV_MASK
- I2S3_BCK_INV_MASK_SFT
- I2S3_BCK_INV_SFT
- I2S3_BCLK_SW_CG_MASK
- I2S3_BCLK_SW_CG_MASK_SFT
- I2S3_BCLK_SW_CG_SFT
- I2S3_EN_MASK
- I2S3_EN_MASK_SFT
- I2S3_EN_SFT
- I2S3_FMT_MASK
- I2S3_FMT_MASK_SFT
- I2S3_FMT_SFT
- I2S3_FPGA_BIT_MASK
- I2S3_FPGA_BIT_MASK_SFT
- I2S3_FPGA_BIT_SFT
- I2S3_FPGA_BIT_TEST_MASK
- I2S3_FPGA_BIT_TEST_MASK_SFT
- I2S3_FPGA_BIT_TEST_SFT
- I2S3_HD_EN_MASK
- I2S3_HD_EN_MASK_SFT
- I2S3_HD_EN_SFT
- I2S3_HD_EN_W_NAME
- I2S3_LOOPBACK_MASK
- I2S3_LOOPBACK_MASK_SFT
- I2S3_LOOPBACK_SFT
- I2S3_LR_SWAP_MASK
- I2S3_LR_SWAP_MASK_SFT
- I2S3_LR_SWAP_SFT
- I2S3_MCLK_EN_W_NAME
- I2S3_OUT_MODE_MASK
- I2S3_OUT_MODE_MASK_SFT
- I2S3_OUT_MODE_SFT
- I2S3_UPDATE_WORD_MASK
- I2S3_UPDATE_WORD_MASK_SFT
- I2S3_UPDATE_WORD_SFT
- I2S3_WCLK_MUX
- I2S3_WLEN_MASK
- I2S3_WLEN_MASK_SFT
- I2S3_WLEN_SFT
- I2S4_32BIT_EN_MASK
- I2S4_32BIT_EN_MASK_SFT
- I2S4_32BIT_EN_SFT
- I2S4_BCLK_SW_CG_MASK
- I2S4_BCLK_SW_CG_MASK_SFT
- I2S4_BCLK_SW_CG_SFT
- I2S4_EN_MASK
- I2S4_EN_MASK_SFT
- I2S4_EN_SFT
- I2S4_FMT_MASK
- I2S4_FMT_MASK_SFT
- I2S4_FMT_SFT
- I2S4_HD_EN_MASK
- I2S4_HD_EN_MASK_SFT
- I2S4_HD_EN_SFT
- I2S4_LR_SWAP_MASK
- I2S4_LR_SWAP_MASK_SFT
- I2S4_LR_SWAP_SFT
- I2S4_OUT_MODE_MASK
- I2S4_OUT_MODE_MASK_SFT
- I2S4_OUT_MODE_SFT
- I2S4_WLEN_MASK
- I2S4_WLEN_MASK_SFT
- I2S4_WLEN_SFT
- I2S5_32BIT_EN_MASK
- I2S5_32BIT_EN_MASK_SFT
- I2S5_32BIT_EN_SFT
- I2S5_EN_MASK
- I2S5_EN_MASK_SFT
- I2S5_EN_SFT
- I2S5_FMT_MASK
- I2S5_FMT_MASK_SFT
- I2S5_FMT_SFT
- I2S5_HD_EN_MASK
- I2S5_HD_EN_MASK_SFT
- I2S5_HD_EN_SFT
- I2S5_HD_EN_W_NAME
- I2S5_LR_SWAP_MASK
- I2S5_LR_SWAP_MASK_SFT
- I2S5_LR_SWAP_SFT
- I2S5_MCLK_EN_W_NAME
- I2S5_OUT_MODE_MASK
- I2S5_OUT_MODE_MASK_SFT
- I2S5_OUT_MODE_SFT
- I2S5_WLEN_MASK
- I2S5_WLEN_MASK_SFT
- I2S5_WLEN_SFT
- I2SAHB
- I2SA_L
- I2SA_R
- I2SB_L
- I2SB_R
- I2SCMC_BCMP_32X
- I2SCMC_BCMP_40X
- I2SCMC_BCMP_64X
- I2SCMC_BCMP_AUTO
- I2SCON
- I2SCTL
- I2SCTL_EA
- I2SCTL_EI
- I2SC_L
- I2SC_R
- I2SDIV_DV_MASK
- I2SDIV_DV_SHIFT
- I2SDIV_IDV_MASK
- I2SDIV_IDV_SHIFT
- I2SD_L
- I2SD_R
- I2SEND
- I2SFIC
- I2SFIC1
- I2SFICS
- I2SFSTA
- I2SIN_PAD_SEL_MASK
- I2SIN_PAD_SEL_MASK_SFT
- I2SIN_PAD_SEL_SFT
- I2SLVL0ADDR
- I2SLVL1ADDR
- I2SLVL2ADDR
- I2SLVL3ADDR
- I2SMOD
- I2SOFFSET
- I2SPCR_CLRFIFO
- I2SPCR_START
- I2SPCR_STOP
- I2SPSR
- I2SRXD
- I2SR_CLR_OPCODE_W0C
- I2SR_CLR_OPCODE_W1C
- I2SR_IAAS
- I2SR_IAL
- I2SR_IBB
- I2SR_ICF
- I2SR_IIF
- I2SR_RXAK
- I2SR_SRW
- I2SSIZE
- I2SSIZE_SHIFT
- I2SSIZE_TRNMSK
- I2SSTAT_BUSY
- I2SSTR0
- I2SSTR1
- I2STDM
- I2STRNCNT
- I2STXD
- I2STXDS
- I2SVER
- I2S_BCLK0
- I2S_BCLK1
- I2S_BLK_DEVICE_ADDRESS
- I2S_BT_INSTANCE
- I2S_BUS_NR
- I2S_BYPSRC_MASK
- I2S_BYPSRC_MASK_SFT
- I2S_BYPSRC_SFT
- I2S_CAP_STREAM_CFG_MASK
- I2S_CFG
- I2S_CFG1_FTHVL_MASK
- I2S_CFG1_FTHVL_SET
- I2S_CFG1_FTHVL_SHIFT
- I2S_CFG1_RXDMAEN
- I2S_CFG1_TXDMAEN
- I2S_CFG2_AFCNTR
- I2S_CFG2_IOSWP
- I2S_CFG2_IOSWP_SHIFT
- I2S_CFG2_LSBFRST
- I2S_CGFR_CHLEN
- I2S_CGFR_CHLEN_SHIFT
- I2S_CGFR_CKPOL
- I2S_CGFR_DATFMT
- I2S_CGFR_DATLEN_MASK
- I2S_CGFR_DATLEN_SET
- I2S_CGFR_DATLEN_SHIFT
- I2S_CGFR_FIXCH
- I2S_CGFR_I2SCFG_MASK
- I2S_CGFR_I2SCFG_SET
- I2S_CGFR_I2SCFG_SHIFT
- I2S_CGFR_I2SDIV_BIT_H
- I2S_CGFR_I2SDIV_MASK
- I2S_CGFR_I2SDIV_MAX
- I2S_CGFR_I2SDIV_SET
- I2S_CGFR_I2SDIV_SHIFT
- I2S_CGFR_I2SMOD
- I2S_CGFR_I2SSTD_MASK
- I2S_CGFR_I2SSTD_SET
- I2S_CGFR_I2SSTD_SHIFT
- I2S_CGFR_MCKOE
- I2S_CGFR_ODD
- I2S_CGFR_ODD_SHIFT
- I2S_CGFR_PCMSYNC
- I2S_CGFR_WSINV
- I2S_CH0_OFFSET
- I2S_CHANNEL_1_2
- I2S_CHANNEL_3_4
- I2S_CHANNEL_5_6
- I2S_CHANNEL_7_8
- I2S_CHNL_2_0
- I2S_CHNL_3_1
- I2S_CHNL_5_1
- I2S_CHNL_7_1
- I2S_CHNL_PLAY_MASK
- I2S_CHNL_PLAY_SHIFT
- I2S_CHNL_REC_MASK
- I2S_CHNL_REC_SHIFT
- I2S_CHN_2
- I2S_CHN_4
- I2S_CHN_6
- I2S_CHN_8
- I2S_CKIN
- I2S_CKR
- I2S_CKR_CKP_MASK
- I2S_CKR_CKP_NEG
- I2S_CKR_CKP_POS
- I2S_CKR_CKP_SHIFT
- I2S_CKR_MDIV
- I2S_CKR_MDIV_MASK
- I2S_CKR_MDIV_SHIFT
- I2S_CKR_MSS_MASK
- I2S_CKR_MSS_MASTER
- I2S_CKR_MSS_SHIFT
- I2S_CKR_MSS_SLAVE
- I2S_CKR_RLP_NORMAL
- I2S_CKR_RLP_OPPSITE
- I2S_CKR_RLP_SHIFT
- I2S_CKR_RSD
- I2S_CKR_RSD_MASK
- I2S_CKR_RSD_SHIFT
- I2S_CKR_TLP_NORMAL
- I2S_CKR_TLP_OPPSITE
- I2S_CKR_TLP_SHIFT
- I2S_CKR_TRCM
- I2S_CKR_TRCM_MASK
- I2S_CKR_TRCM_RXONLY
- I2S_CKR_TRCM_SHIFT
- I2S_CKR_TRCM_TXONLY
- I2S_CKR_TRCM_TXRX
- I2S_CKR_TSD
- I2S_CKR_TSD_MASK
- I2S_CKR_TSD_SHIFT
- I2S_CLOCK
- I2S_CLOCK_SPEED_18MHz
- I2S_CLOCK_SPEED_45MHz
- I2S_CLOCK_SPEED_49MHz
- I2S_CLR
- I2S_CLR_RXC
- I2S_CLR_TXC
- I2S_CMD0
- I2S_CMD1
- I2S_COMP_PARAM_1
- I2S_COMP_PARAM_2
- I2S_COMP_TYPE
- I2S_COMP_VERSION
- I2S_CORE_CTRL_OFFSET
- I2S_CR1_CRC33_17
- I2S_CR1_CSTART
- I2S_CR1_CSUSP
- I2S_CR1_HDDIR
- I2S_CR1_RCRCI
- I2S_CR1_SPE
- I2S_CR1_SSI
- I2S_CR1_TCRCI
- I2S_CSR_SHIFT
- I2S_D0
- I2S_D1
- I2S_DATA_FORMAT
- I2S_DEAGULT_FIFO_THRES
- I2S_DEC_PORT_EN
- I2S_DEC_START
- I2S_DMACR
- I2S_DMACR_RDE_DISABLE
- I2S_DMACR_RDE_ENABLE
- I2S_DMACR_RDE_SHIFT
- I2S_DMACR_RDL
- I2S_DMACR_RDL_MASK
- I2S_DMACR_RDL_SHIFT
- I2S_DMACR_TDE_DISABLE
- I2S_DMACR_TDE_ENABLE
- I2S_DMACR_TDE_SHIFT
- I2S_DMACR_TDL
- I2S_DMACR_TDL_MASK
- I2S_DMACR_TDL_SHIFT
- I2S_DWS_DATA_IN_16BIT
- I2S_DWS_DATA_IN_24BIT
- I2S_DWS_DATA_IN_SIZE_SHIFT
- I2S_DWS_DATA_OUT_16BIT
- I2S_DWS_DATA_OUT_24BIT
- I2S_DWS_DATA_OUT_SIZE_SHIFT
- I2S_DWS_NUM_CHANNELS_IN_MASK
- I2S_DWS_NUM_CHANNELS_IN_SHIFT
- I2S_DWS_NUM_CHANNELS_OUT_MASK
- I2S_DWS_NUM_CHANNELS_OUT_SHIFT
- I2S_ENABLE
- I2S_EN_MASK
- I2S_EN_MASK_SFT
- I2S_EN_SFT
- I2S_EQU_BYP
- I2S_FIFOLR
- I2S_FIFOLR_RFL_MASK
- I2S_FIFOLR_RFL_SHIFT
- I2S_FIFOLR_TFL0_MASK
- I2S_FIFOLR_TFL0_SHIFT
- I2S_FIFOLR_TFL1_MASK
- I2S_FIFOLR_TFL1_SHIFT
- I2S_FIFOLR_TFL2_MASK
- I2S_FIFOLR_TFL2_SHIFT
- I2S_FIFOLR_TFL3_MASK
- I2S_FIFOLR_TFL3_SHIFT
- I2S_FIFO_TH_FULL
- I2S_FIFO_TH_HALF
- I2S_FIFO_TH_NONE
- I2S_FIFO_TH_ONE_QUARTER
- I2S_FIFO_TH_THREE_QUARTER
- I2S_FMT_EIAJ
- I2S_FMT_I2S
- I2S_FMT_MASK
- I2S_FMT_MASK_SFT
- I2S_FMT_SFT
- I2S_FORMATS
- I2S_FORMAT_LEFT_J
- I2S_FORMAT_PHILIPS
- I2S_FORMAT_RIGHT_J
- I2S_HD_LOW_JITTER
- I2S_HD_NORMAL
- I2S_HWCFGR_I2S_SUPPORT_MASK
- I2S_I2SMOD_DATLEN_16
- I2S_I2SMOD_DATLEN_24
- I2S_I2SMOD_DATLEN_32
- I2S_I2SMOD_FD_MASTER
- I2S_I2SMOD_FD_SLAVE
- I2S_I2SMOD_RX_MASTER
- I2S_I2SMOD_RX_SLAVE
- I2S_I2SMOD_TX_MASTER
- I2S_I2SMOD_TX_SLAVE
- I2S_I2STIM_OFFSET
- I2S_I2STIM_VALID_MASK
- I2S_IER_CRCEIE
- I2S_IER_DPXPIE
- I2S_IER_EOTIE
- I2S_IER_MODFIE
- I2S_IER_OVRIE
- I2S_IER_RXPIE
- I2S_IER_TIFREIE
- I2S_IER_TSERFIE
- I2S_IER_TXPIE
- I2S_IER_TXTFIE
- I2S_IER_UDRIE
- I2S_IFCR_CRCEC
- I2S_IFCR_EOTC
- I2S_IFCR_MASK
- I2S_IFCR_MODFC
- I2S_IFCR_OVRC
- I2S_IFCR_SUSPC
- I2S_IFCR_TIFREC
- I2S_IFCR_TSERFC
- I2S_IFCR_TXTFC
- I2S_IFCR_UDRC
- I2S_INPUT_EN
- I2S_INTCR
- I2S_INTCR_RFT
- I2S_INTCR_RFT_SHIFT
- I2S_INTCR_RXFIE_DISABLE
- I2S_INTCR_RXFIE_ENABLE
- I2S_INTCR_RXFIE_SHIFT
- I2S_INTCR_RXOIC
- I2S_INTCR_RXOIE_DISABLE
- I2S_INTCR_RXOIE_ENABLE
- I2S_INTCR_RXOIE_SHIFT
- I2S_INTCR_TFT
- I2S_INTCR_TFT_MASK
- I2S_INTCR_TFT_SHIFT
- I2S_INTCR_TXUIC
- I2S_INTCR_TXUIE_DISABLE
- I2S_INTCR_TXUIE_ENABLE
- I2S_INTCR_TXUIE_SHIFT
- I2S_INTDEC
- I2S_INTSR
- I2S_INTSR_RXFI_ACT
- I2S_INTSR_RXFI_INA
- I2S_INTSR_RXFI_SHIFT
- I2S_INTSR_RXOI_ACT
- I2S_INTSR_RXOI_INA
- I2S_INTSR_RXOI_SHIFT
- I2S_INTSR_TXEIE_DISABLE
- I2S_INTSR_TXEIE_ENABLE
- I2S_INTSR_TXEIE_SHIFT
- I2S_INTSR_TXEI_ACT
- I2S_INTSR_TXEI_INA
- I2S_INTSR_TXEI_SHIFT
- I2S_INTSR_TXUI_ACT
- I2S_INTSR_TXUI_INA
- I2S_INTSR_TXUI_SHIFT
- I2S_INT_CLOCKS_STOPPED
- I2S_INT_EXTERNAL_SYNC_ERROR
- I2S_INT_EXTERNAL_SYNC_OK
- I2S_INT_FRAME_COUNT
- I2S_INT_MESSAGE_FLAG
- I2S_INT_NEW_PEAK
- I2S_INT_NEW_SAMPLE_RATE
- I2S_INT_STATUS_FLAG
- I2S_IN_CFG_REG_UPDATE_MASK
- I2S_IN_CTL
- I2S_IN_PAD_CONNSYS
- I2S_IN_PAD_IO_MUX
- I2S_IN_REG2_MASK
- I2S_IN_REG3_MASK
- I2S_IN_STREAM_CFG_0_GROUP_ID
- I2S_IN_STREAM_CFG_CAP_ENA
- I2S_IO_2CH_OUT_8CH_IN
- I2S_IO_4CH_OUT_6CH_IN
- I2S_IO_6CH_OUT_4CH_IN
- I2S_IO_8CH_OUT_2CH_IN
- I2S_IO_DIRECTION_MASK
- I2S_IPIDR_ID_MASK
- I2S_IPIDR_NUMBER
- I2S_LEFT_JUSTIFIED
- I2S_LOOPBACK_MASK
- I2S_LOOPBACK_MASK_SFT
- I2S_LOOPBACK_SFT
- I2S_LRCLK0
- I2S_LRCLK1
- I2S_LRCLK_HIGH_LEFT
- I2S_LRCLK_LOW_LEFT
- I2S_LRCLK_POLARITY
- I2S_LRCLK_STRENGTH_DISABLE
- I2S_LRCLK_STRENGTH_HIGH
- I2S_LRCLK_STRENGTH_LOW
- I2S_LRCLK_STRENGTH_MEDIUM
- I2S_MAX_FIFO_THRES
- I2S_MCK_11M2896
- I2S_MCK_12M288
- I2S_MCLK0
- I2S_MCLK1
- I2S_MEAS
- I2S_MERGER
- I2S_MIXER
- I2S_MODE
- I2S_MODE_CONFIG_SET
- I2S_MODE_MASK
- I2S_MODE_MASK_SFT
- I2S_MODE_SFT
- I2S_MS_MASTER
- I2S_MS_NOT_SET
- I2S_MS_SLAVE
- I2S_NCTS_STABLE
- I2S_NM_STABLE
- I2S_N_CTL
- I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK
- I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT
- I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT
- I2S_OUTPUT_EN
- I2S_OUT_ASSIGN
- I2S_OUT_CFGX_BITS_PER_SLOT
- I2S_OUT_CFGX_CLK_ENA
- I2S_OUT_CFGX_DATA_ALIGNMENT
- I2S_OUT_CFGX_DATA_ENABLE
- I2S_OUT_CFGX_FSYNC_WIDTH
- I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32
- I2S_OUT_CFGX_SLAVE_MODE
- I2S_OUT_CFGX_TDM_MODE
- I2S_OUT_CFGX_VALID_SLOT
- I2S_OUT_CFG_REG_UPDATE_MASK
- I2S_OUT_CTL
- I2S_OUT_MCLKRATE_SHIFT
- I2S_OUT_PLLCLKSEL_SHIFT
- I2S_OUT_REG3_MASK
- I2S_OUT_STREAM_CFG_CHANNEL_GROUPING
- I2S_OUT_STREAM_CFG_GROUP_ID
- I2S_OUT_STREAM_ENA
- I2S_PCM_LOOPBACK_CH_MASK
- I2S_PCM_LOOPBACK_CH_MASK_SFT
- I2S_PCM_LOOPBACK_CH_SFT
- I2S_PCR
- I2S_PENDING_CLOCKS_STOPPED
- I2S_PENDING_EXTERNAL_SYNC_ERROR
- I2S_PENDING_EXTERNAL_SYNC_OK
- I2S_PENDING_FRAME_COUNT
- I2S_PENDING_MESSAGE_FLAG
- I2S_PENDING_NEW_PEAK
- I2S_PENDING_NEW_SAMPLE_RATE
- I2S_PENDING_STATUS_FLAG
- I2S_RATE
- I2S_REF_PCLK_MASK
- I2S_REF_PCLK_PLL2_VAL
- I2S_REF_PCLK_SHIFT
- I2S_REF_PCLK_SYNTH_VAL
- I2S_REG_CODEC_MSG_IN
- I2S_REG_CODEC_MSG_OUT
- I2S_REG_DATA_WORD_SIZES
- I2S_REG_FRAME_COUNT
- I2S_REG_FRAME_MATCH
- I2S_REG_INTR_CTL
- I2S_REG_PEAK_LEVEL_IN0
- I2S_REG_PEAK_LEVEL_IN1
- I2S_REG_PEAK_LEVEL_SEL
- I2S_REG_SERIAL_FORMAT
- I2S_RIGHT_JUSTIFIED
- I2S_RXCR
- I2S_RXCR_CSR
- I2S_RXCR_CSR_MASK
- I2S_RXCR_CSR_SHIFT
- I2S_RXCR_FBM_LSB
- I2S_RXCR_FBM_MSB
- I2S_RXCR_FBM_SHIFT
- I2S_RXCR_HWT
- I2S_RXCR_IBM_LSJM
- I2S_RXCR_IBM_MASK
- I2S_RXCR_IBM_NORMAL
- I2S_RXCR_IBM_RSJM
- I2S_RXCR_IBM_SHIFT
- I2S_RXCR_PBM_MASK
- I2S_RXCR_PBM_MODE
- I2S_RXCR_PBM_SHIFT
- I2S_RXCR_SJM_L
- I2S_RXCR_SJM_R
- I2S_RXCR_SJM_SHIFT
- I2S_RXCR_TFS_I2S
- I2S_RXCR_TFS_MASK
- I2S_RXCR_TFS_PCM
- I2S_RXCR_TFS_SHIFT
- I2S_RXCR_VDW
- I2S_RXCR_VDW_MASK
- I2S_RXCR_VDW_SHIFT
- I2S_RXDMA
- I2S_RXDR
- I2S_RXDR_MASK
- I2S_RXTX
- I2S_SAMPLE_ALIGNMENT
- I2S_SAMPLE_BIT_ORDER
- I2S_SAMPLE_BIT_ORDER_LSB
- I2S_SAMPLE_BIT_ORDER_MSB
- I2S_SAMPLE_LEFT_ALIGNED
- I2S_SAMPLE_RIGHT_ALIGNED
- I2S_SCLK_STRENGTH_DISABLE
- I2S_SCLK_STRENGTH_HIGH
- I2S_SCLK_STRENGTH_LOW
- I2S_SCLK_STRENGTH_MEDIUM
- I2S_SF_CLOCK_SOURCE_18MHz
- I2S_SF_CLOCK_SOURCE_45MHz
- I2S_SF_CLOCK_SOURCE_49MHz
- I2S_SF_CLOCK_SOURCE_MASK
- I2S_SF_CLOCK_SOURCE_SHIFT
- I2S_SF_EXT_SAMPLE_FREQ_INT_MASK
- I2S_SF_EXT_SAMPLE_FREQ_INT_SHIFT
- I2S_SF_EXT_SAMPLE_FREQ_MASK
- I2S_SF_MCLKDIV_1
- I2S_SF_MCLKDIV_14
- I2S_SF_MCLKDIV_3
- I2S_SF_MCLKDIV_5
- I2S_SF_MCLKDIV_MASK
- I2S_SF_MCLKDIV_OTHER
- I2S_SF_MCLKDIV_SHIFT
- I2S_SF_SCLKDIV_1
- I2S_SF_SCLKDIV_3
- I2S_SF_SCLKDIV_MASK
- I2S_SF_SCLKDIV_OTHER
- I2S_SF_SCLKDIV_SHIFT
- I2S_SF_SCLK_MASTER
- I2S_SF_SERIAL_FORMAT_I2S_32X
- I2S_SF_SERIAL_FORMAT_I2S_64X
- I2S_SF_SERIAL_FORMAT_I2S_DAV
- I2S_SF_SERIAL_FORMAT_I2S_SILABS
- I2S_SF_SERIAL_FORMAT_MASK
- I2S_SF_SERIAL_FORMAT_SHIFT
- I2S_SF_SERIAL_FORMAT_SONY
- I2S_SHUT
- I2S_SIDR_ID_MASK
- I2S_SOFT_RST2_MASK
- I2S_SOFT_RST2_MASK_SFT
- I2S_SOFT_RST2_SFT
- I2S_SOFT_RST_MASK
- I2S_SOFT_RST_MASK_SFT
- I2S_SOFT_RST_SFT
- I2S_SPLITTER
- I2S_SP_INSTANCE
- I2S_SRC_MASK
- I2S_SRC_MASK_SFT
- I2S_SRC_SFT
- I2S_SR_CRCERR
- I2S_SR_DPXP
- I2S_SR_EOT
- I2S_SR_MASK
- I2S_SR_MODF
- I2S_SR_OVR
- I2S_SR_RXP
- I2S_SR_RXPLVL
- I2S_SR_RXWNE
- I2S_SR_SUSP
- I2S_SR_TIFRE
- I2S_SR_TSERF
- I2S_SR_TXC
- I2S_SR_TXP
- I2S_SR_TXTF
- I2S_SR_UDR
- I2S_STANDARD
- I2S_STAT
- I2S_STD_DSP
- I2S_STD_I2S
- I2S_STD_LEFT_J
- I2S_STD_RIGHT_J
- I2S_STREAM_CFG_MASK
- I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM
- I2S_TO_ACP_DMA_CH_NUM
- I2S_TXCR
- I2S_TXCR_CSR
- I2S_TXCR_CSR_MASK
- I2S_TXCR_CSR_SHIFT
- I2S_TXCR_FBM_LSB
- I2S_TXCR_FBM_MSB
- I2S_TXCR_FBM_SHIFT
- I2S_TXCR_HWT
- I2S_TXCR_IBM_LSJM
- I2S_TXCR_IBM_MASK
- I2S_TXCR_IBM_NORMAL
- I2S_TXCR_IBM_RSJM
- I2S_TXCR_IBM_SHIFT
- I2S_TXCR_PBM_MASK
- I2S_TXCR_PBM_MODE
- I2S_TXCR_PBM_SHIFT
- I2S_TXCR_RCNT_MASK
- I2S_TXCR_RCNT_SHIFT
- I2S_TXCR_SJM_L
- I2S_TXCR_SJM_R
- I2S_TXCR_SJM_SHIFT
- I2S_TXCR_TFS_I2S
- I2S_TXCR_TFS_MASK
- I2S_TXCR_TFS_PCM
- I2S_TXCR_TFS_SHIFT
- I2S_TXCR_VDW
- I2S_TXCR_VDW_MASK
- I2S_TXCR_VDW_SHIFT
- I2S_TXDMA
- I2S_TXDR
- I2S_TXDR_MASK
- I2S_TX_CFG
- I2S_UV_CH_EN
- I2S_UV_CH_EN_MASK
- I2S_UV_NORMAL_INFO_INV
- I2S_UV_TMDS_DEBUG
- I2S_UV_U
- I2S_UV_V
- I2S_VERR_MAJ_MASK
- I2S_VERR_MIN_MASK
- I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK
- I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT
- I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK
- I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT
- I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK
- I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT
- I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK
- I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT
- I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK
- I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT
- I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK
- I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT
- I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK
- I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT
- I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK
- I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT
- I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK
- I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT
- I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK
- I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT
- I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK
- I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT
- I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK
- I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT
- I2S_WLEN_16_BIT
- I2S_WLEN_32_BIT
- I2S_WLEN_MASK
- I2S_WLEN_MASK_SFT
- I2S_WLEN_SFT
- I2S_WORD_ALIGNMENT
- I2S_WORD_ALTERNATE_ALIGNMENT
- I2S_WORD_I2S_ALIGNMENT
- I2S_WORD_SIZE
- I2S_WORD_SIZE_16
- I2S_WORD_SIZE_32
- I2S_XFER
- I2S_XFER_RXS_SHIFT
- I2S_XFER_RXS_START
- I2S_XFER_RXS_STOP
- I2S_XFER_TXS_SHIFT
- I2S_XFER_TXS_START
- I2S_XFER_TXS_STOP
- I2_BITS
- I2_FIFO_SIZE
- I2_RTMUTEX
- I2bv
- I2bvIP
- I2cCmdType_e
- I2cControllerConfig_t
- I2cControllerName_e
- I2cControllerPort_e
- I2cControllerProtocol_e
- I2cControllerSpeed_e
- I2cControllerThrottler_e
- I2cPort_e
- I2cSpeed_e
- I3
- I3000
- I3000_C0DRA
- I3000_C0DRB
- I3000_C0DRC0
- I3000_C0DRC1
- I3000_C1DRA
- I3000_C1DRB
- I3000_CHANNELS
- I3000_DEAP
- I3000_DEAP_GRAIN
- I3000_DERRSYN
- I3000_DRB_SHIFT
- I3000_EDEAP
- I3000_ERRCMD
- I3000_ERRSTS
- I3000_ERRSTS_BITS
- I3000_ERRSTS_CE
- I3000_ERRSTS_UE
- I3000_MCHBAR
- I3000_MCHBAR_MASK
- I3000_MMR_WINDOW_SIZE
- I3000_RANKS
- I3000_RANKS_PER_CHANNEL
- I3100
- I3100_NSI_EMASK
- I3100_NSI_FERR
- I3100_NSI_NERR
- I3100_NSI_SMICMD
- I32
- I3200
- I3200_C0DRB
- I3200_C0ECCERRLOG
- I3200_C1DRB
- I3200_C1ECCERRLOG
- I3200_CAPID0
- I3200_CHANNELS
- I3200_DIMMS
- I3200_DRB_MASK
- I3200_DRB_SHIFT
- I3200_ECCERRLOG_CE
- I3200_ECCERRLOG_RANK_BITS
- I3200_ECCERRLOG_RANK_SHIFT
- I3200_ECCERRLOG_SYNDROME_BITS
- I3200_ECCERRLOG_SYNDROME_SHIFT
- I3200_ECCERRLOG_UE
- I3200_ERRSTS
- I3200_ERRSTS_BITS
- I3200_ERRSTS_CE
- I3200_ERRSTS_UE
- I3200_MCHBAR_HIGH
- I3200_MCHBAR_LOW
- I3200_MCHBAR_MASK
- I3200_MMR_WINDOW_SIZE
- I3200_RANKS
- I3200_RANKS_PER_CHANNEL
- I3200_TOM
- I3200_TOM_MASK
- I3200_TOM_SHIFT
- I32_16
- I347AT4_E_PHY_ID
- I347AT4_PAGE_SELECT
- I347AT4_PCDC
- I347AT4_PCDC_CABLE_LENGTH_UNIT
- I347AT4_PCDL0
- I347AT4_PCDL1
- I347AT4_PCDL2
- I347AT4_PCDL3
- I347AT4_PSCR_DOWNSHIFT_1X
- I347AT4_PSCR_DOWNSHIFT_2X
- I347AT4_PSCR_DOWNSHIFT_3X
- I347AT4_PSCR_DOWNSHIFT_4X
- I347AT4_PSCR_DOWNSHIFT_5X
- I347AT4_PSCR_DOWNSHIFT_6X
- I347AT4_PSCR_DOWNSHIFT_7X
- I347AT4_PSCR_DOWNSHIFT_8X
- I347AT4_PSCR_DOWNSHIFT_ENABLE
- I347AT4_PSCR_DOWNSHIFT_MASK
- I350_I_PHY_ID
- I365_ADDRWIN
- I365_CSC
- I365_CSCINT
- I365_CSC_ANY
- I365_CSC_BVD1
- I365_CSC_BVD2
- I365_CSC_DETECT
- I365_CSC_GPI
- I365_CSC_IRQ_MASK
- I365_CSC_READY
- I365_CSC_STSCHG
- I365_CS_BVD1
- I365_CS_BVD2
- I365_CS_DETECT
- I365_CS_GPI
- I365_CS_POWERON
- I365_CS_READY
- I365_CS_SPKR
- I365_CS_STSCHG
- I365_CS_WRPROT
- I365_CTL_16DELAY
- I365_CTL_GPI_CTL
- I365_CTL_GPI_ENA
- I365_CTL_RESET
- I365_CTL_RESUME
- I365_CTL_SW_IRQ
- I365_DF_VS1
- I365_DF_VS2
- I365_ENA_IO
- I365_ENA_MEM
- I365_GBLCTL
- I365_GBL_CSC_LEV
- I365_GBL_IRQ_0_LEV
- I365_GBL_IRQ_1_LEV
- I365_GBL_PWRDOWN
- I365_GBL_WRBACK
- I365_GENCTL
- I365_IDENT
- I365_IDENT_VADEM
- I365_INTCTL
- I365_INTR_ENA
- I365_IO
- I365_IOCTL
- I365_IOCTL_0WS
- I365_IOCTL_16BIT
- I365_IOCTL_IOCS16
- I365_IOCTL_MASK
- I365_IOCTL_WAIT
- I365_IRQ_MASK
- I365_MASK
- I365_MEM
- I365_MEM_0WS
- I365_MEM_16BIT
- I365_MEM_REG
- I365_MEM_WRPROT
- I365_MEM_WS0
- I365_MEM_WS1
- I365_PC_IOCARD
- I365_PC_RESET
- I365_POWER
- I365_PWR_AUTO
- I365_PWR_NORESET
- I365_PWR_OFF
- I365_PWR_OUT
- I365_REG
- I365_RING_ENA
- I365_STATUS
- I365_VCC_3V
- I365_VCC_5V
- I365_VCC_MASK
- I365_VPP1_12V
- I365_VPP1_5V
- I365_VPP1_MASK
- I365_VPP2_12V
- I365_VPP2_5V
- I365_VPP2_MASK
- I365_W_OFF
- I365_W_START
- I365_W_STOP
- I387
- I3C_ADDR_SLOT_FREE
- I3C_ADDR_SLOT_I2C_DEV
- I3C_ADDR_SLOT_I3C_DEV
- I3C_ADDR_SLOT_RSVD
- I3C_ADDR_SLOT_STATUS_MASK
- I3C_BCR_BRIDGE
- I3C_BCR_DEVICE_ROLE
- I3C_BCR_HDR_CAP
- I3C_BCR_I3C_MASTER
- I3C_BCR_I3C_SLAVE
- I3C_BCR_IBI_PAYLOAD
- I3C_BCR_IBI_REQ_CAP
- I3C_BCR_MAX_DATA_SPEED_LIM
- I3C_BCR_OFFLINE_CAP
- I3C_BROADCAST_ADDR
- I3C_BUS_I2C_FMP_TLOW_MIN_NS
- I3C_BUS_I2C_FM_PLUS_SCL_RATE
- I3C_BUS_I2C_FM_SCL_RATE
- I3C_BUS_I2C_FM_TLOW_MIN_NS
- I3C_BUS_MAX_DEVS
- I3C_BUS_MAX_I3C_SCL_RATE
- I3C_BUS_MODE_MIXED_FAST
- I3C_BUS_MODE_MIXED_LIMITED
- I3C_BUS_MODE_MIXED_SLOW
- I3C_BUS_MODE_PURE
- I3C_BUS_SDR1_SCL_RATE
- I3C_BUS_SDR2_SCL_RATE
- I3C_BUS_SDR3_SCL_RATE
- I3C_BUS_SDR4_SCL_RATE
- I3C_BUS_THIGH_MAX_NS
- I3C_BUS_TLOW_OD_MIN_NS
- I3C_BUS_TYP_I3C_SCL_RATE
- I3C_CCC_DEFSLVS
- I3C_CCC_DIRECT
- I3C_CCC_DISEC
- I3C_CCC_ENEC
- I3C_CCC_ENTAS
- I3C_CCC_ENTDAA
- I3C_CCC_ENTHDR
- I3C_CCC_ENTTM
- I3C_CCC_EVENT_HJ
- I3C_CCC_EVENT_MR
- I3C_CCC_EVENT_SIR
- I3C_CCC_EXIT_TEST_MODE
- I3C_CCC_GETACCMST
- I3C_CCC_GETBCR
- I3C_CCC_GETDCR
- I3C_CCC_GETHDRCAP
- I3C_CCC_GETMRL
- I3C_CCC_GETMWL
- I3C_CCC_GETMXDS
- I3C_CCC_GETPID
- I3C_CCC_GETSTATUS
- I3C_CCC_GETXTIME
- I3C_CCC_GETXTIME_ASYNC_MODE
- I3C_CCC_GETXTIME_OVERFLOW
- I3C_CCC_GETXTIME_SYNC_MODE
- I3C_CCC_H
- I3C_CCC_HDR_MODE
- I3C_CCC_ID
- I3C_CCC_MAX_SDR_FSCL
- I3C_CCC_MAX_SDR_FSCL_MASK
- I3C_CCC_RSTDAA
- I3C_CCC_SETBRGTGT
- I3C_CCC_SETDASA
- I3C_CCC_SETMRL
- I3C_CCC_SETMWL
- I3C_CCC_SETNEWDA
- I3C_CCC_SETXTIME
- I3C_CCC_SETXTIME_ASYNC_TRIGGER
- I3C_CCC_SETXTIME_DT
- I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0
- I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1
- I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2
- I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3
- I3C_CCC_SETXTIME_ODR
- I3C_CCC_SETXTIME_ST
- I3C_CCC_SETXTIME_TPH
- I3C_CCC_SETXTIME_TU
- I3C_CCC_STATUS_ACTIVITY_MODE
- I3C_CCC_STATUS_PENDING_INT
- I3C_CCC_STATUS_PROTOCOL_ERROR
- I3C_CCC_VENDOR
- I3C_CCC_VENDOR_TEST_MODE
- I3C_CLASS
- I3C_DCR_GENERIC_DEVICE
- I3C_DEVICE
- I3C_DEVICE_EXTRA_INFO
- I3C_DEV_H
- I3C_ERROR_M0
- I3C_ERROR_M1
- I3C_ERROR_M2
- I3C_ERROR_UNKNOWN
- I3C_HDR_DDR
- I3C_HDR_TSL
- I3C_HDR_TSP
- I3C_HOT_JOIN_ADDR
- I3C_INTERNALS_H
- I3C_LVR_I2C_FM_MODE
- I3C_LVR_I2C_INDEX
- I3C_LVR_I2C_INDEX_MASK
- I3C_MASTER_H
- I3C_MATCH_DCR
- I3C_MATCH_EXTRA_INFO
- I3C_MATCH_MANUF
- I3C_MATCH_MANUF_AND_PART
- I3C_MATCH_PART
- I3C_MAX_ADDR
- I3C_PID_EXTRA_INFO
- I3C_PID_INSTANCE_ID
- I3C_PID_MANUF_ID
- I3C_PID_PART_ID
- I3C_PID_RND_LOWER_32BITS
- I3C_PID_RND_VAL
- I3C_SDR0_FSCL_MAX
- I3C_SDR1_FSCL_8MHZ
- I3C_SDR2_FSCL_6MHZ
- I3C_SDR3_FSCL_4MHZ
- I3C_SDR4_FSCL_2MHZ
- I3C_TSCO_10NS
- I3C_TSCO_11NS
- I3C_TSCO_12NS
- I3C_TSCO_8NS
- I3C_TSCO_9NS
- I3C_VER_ID
- I3C_VER_TYPE
- I4
- I40E_2K_TOO_SMALL_WITH_PADDING
- I40E_64BYTE_MSS
- I40E_ADMINQ_DESC
- I40E_ADMINQ_DESC_ALIGNMENT
- I40E_ADMINQ_DETAILS
- I40E_ALT_BW_RELATIVE_MASK
- I40E_ALT_BW_VALID_MASK
- I40E_ALT_BW_VALUE_MASK
- I40E_ALT_STRUCT_DWORDS_PER_PF
- I40E_ALT_STRUCT_FIRST_PF_OFFSET
- I40E_ALT_STRUCT_MAX_BW_OFFSET
- I40E_ALT_STRUCT_MIN_BW_OFFSET
- I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET
- I40E_ALT_STRUCT_USER_PRIORITY_OFFSET
- I40E_APP_PROTOID_FCOE
- I40E_APP_PROTOID_FIP
- I40E_APP_PROTOID_ISCSI
- I40E_APP_SEL_ETHTYPE
- I40E_APP_SEL_TCPIP
- I40E_AQC_ADDR_VALID_MASK
- I40E_AQC_ADD_CLOUD_CMD_BB
- I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK
- I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT
- I40E_AQC_ADD_CLOUD_FILTER_FAIL
- I40E_AQC_ADD_CLOUD_FILTER_IIP
- I40E_AQC_ADD_CLOUD_FILTER_IMAC
- I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN
- I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID
- I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID
- I40E_AQC_ADD_CLOUD_FILTER_IP_PORT
- I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT
- I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT
- I40E_AQC_ADD_CLOUD_FILTER_MASK
- I40E_AQC_ADD_CLOUD_FILTER_OMAC
- I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC
- I40E_AQC_ADD_CLOUD_FILTER_SHIFT
- I40E_AQC_ADD_CLOUD_FILTER_SUCCESS
- I40E_AQC_ADD_CLOUD_FLAGS_IPV4
- I40E_AQC_ADD_CLOUD_FLAGS_IPV6
- I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC
- I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP
- I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC
- I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE
- I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6
- I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6
- I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7
- I40E_AQC_ADD_CLOUD_QUEUE_MASK
- I40E_AQC_ADD_CLOUD_QUEUE_SHIFT
- I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE
- I40E_AQC_ADD_CLOUD_TNL_TYPE_IP
- I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK
- I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC
- I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED
- I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT
- I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN
- I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE
- I40E_AQC_ADD_CLOUD_VNK_MASK
- I40E_AQC_ADD_CLOUD_VNK_SHIFT
- I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK
- I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT
- I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP
- I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC
- I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX
- I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE
- I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX
- I40E_AQC_ADD_PVLAN_TYPE_MASK
- I40E_AQC_ADD_PVLAN_TYPE_PRIMARY
- I40E_AQC_ADD_PVLAN_TYPE_REGULAR
- I40E_AQC_ADD_PVLAN_TYPE_SECONDARY
- I40E_AQC_ADD_PVLAN_TYPE_SHIFT
- I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK
- I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT
- I40E_AQC_ADD_TAG_FLAG_TO_QUEUE
- I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS
- I40E_AQC_ADD_VEB_ENABLE_L2_FILTER
- I40E_AQC_ADD_VEB_FLOATING
- I40E_AQC_ADD_VEB_PORT_TYPE_DATA
- I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT
- I40E_AQC_ADD_VEB_PORT_TYPE_MASK
- I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT
- I40E_AQC_ADD_VLAN_FAIL_REQUEST
- I40E_AQC_ADD_VLAN_FAIL_RESOURCE
- I40E_AQC_ADD_VLAN_LOCAL
- I40E_AQC_ADD_VLAN_SUCCESS
- I40E_AQC_CEE_APP_FCOE_MASK
- I40E_AQC_CEE_APP_FCOE_SHIFT
- I40E_AQC_CEE_APP_FIP_MASK
- I40E_AQC_CEE_APP_FIP_SHIFT
- I40E_AQC_CEE_APP_ISCSI_MASK
- I40E_AQC_CEE_APP_ISCSI_SHIFT
- I40E_AQC_CEE_APP_STATUS_MASK
- I40E_AQC_CEE_APP_STATUS_SHIFT
- I40E_AQC_CEE_FCOE_STATUS_MASK
- I40E_AQC_CEE_FCOE_STATUS_SHIFT
- I40E_AQC_CEE_FIP_STATUS_MASK
- I40E_AQC_CEE_FIP_STATUS_SHIFT
- I40E_AQC_CEE_ISCSI_STATUS_MASK
- I40E_AQC_CEE_ISCSI_STATUS_SHIFT
- I40E_AQC_CEE_PFC_STATUS_MASK
- I40E_AQC_CEE_PFC_STATUS_SHIFT
- I40E_AQC_CEE_PG_STATUS_MASK
- I40E_AQC_CEE_PG_STATUS_SHIFT
- I40E_AQC_GET_CLOUD_FILTERS
- I40E_AQC_GET_DDP_GET_CONF
- I40E_AQC_GET_DDP_GET_RDPU_CONF
- I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG
- I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG
- I40E_AQC_GET_PV_PV_TYPE
- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK
- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT
- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK
- I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT
- I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER
- I40E_AQC_LAN_ADDR_VALID
- I40E_AQC_MACVLAN_ADD_HASH_MATCH
- I40E_AQC_MACVLAN_ADD_IGNORE_VLAN
- I40E_AQC_MACVLAN_ADD_PERFECT_MATCH
- I40E_AQC_MACVLAN_ADD_TO_QUEUE
- I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC
- I40E_AQC_MACVLAN_CMD_QUEUE_MASK
- I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT
- I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK
- I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT
- I40E_AQC_MACVLAN_CMD_SEID_VALID
- I40E_AQC_MACVLAN_DEL_ALL_VSIS
- I40E_AQC_MACVLAN_DEL_HASH_MATCH
- I40E_AQC_MACVLAN_DEL_IGNORE_VLAN
- I40E_AQC_MACVLAN_DEL_PERFECT_MATCH
- I40E_AQC_MAX_NUM_WOL_FILTERS
- I40E_AQC_MC_MAG_EN
- I40E_AQC_MC_MAG_EN_VALID
- I40E_AQC_MIRROR_CLOUD_FILTER
- I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS
- I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS
- I40E_AQC_MIRROR_RULE_TYPE_MASK
- I40E_AQC_MIRROR_RULE_TYPE_SHIFT
- I40E_AQC_MIRROR_RULE_TYPE_VLAN
- I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS
- I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS
- I40E_AQC_MM_ERR_NO_RES
- I40E_AQC_MM_HASH_MATCH
- I40E_AQC_MM_PERFECT_MATCH
- I40E_AQC_MULTIPLE_PFS
- I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP
- I40E_AQC_NETWORK_KEY_INDEX_GRE
- I40E_AQC_NETWORK_KEY_INDEX_NGE
- I40E_AQC_NETWORK_KEY_INDEX_VXLAN
- I40E_AQC_PFC_IGNORE_CLEAR
- I40E_AQC_PFC_IGNORE_SET
- I40E_AQC_PHY_REG_EXERNAL_BASET
- I40E_AQC_PHY_REG_EXERNAL_MODULE
- I40E_AQC_PHY_REG_INTERNAL
- I40E_AQC_PORT_ADDR_VALID
- I40E_AQC_PV_ERR_FLAG_NO_COUNTER
- I40E_AQC_PV_ERR_FLAG_NO_ENTRY
- I40E_AQC_PV_ERR_FLAG_NO_PV
- I40E_AQC_PV_ERR_FLAG_NO_SCHED
- I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN
- I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN
- I40E_AQC_PV_FLAG_IS_CTRL_PORT
- I40E_AQC_PV_FLAG_PV_TYPE
- I40E_AQC_REMOVE_MACVLAN_FAIL
- I40E_AQC_REMOVE_MACVLAN_SUCCESS
- I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK
- I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT
- I40E_AQC_REMOVE_VLAN_ALL
- I40E_AQC_REMOVE_VLAN_FAIL
- I40E_AQC_REMOVE_VLAN_SUCCESS
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN
- I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED
- I40E_AQC_REPLACE_CLOUD_FILTER
- I40E_AQC_REPLACE_L1_FILTER
- I40E_AQC_SAN_ADDR_VALID
- I40E_AQC_SET_RSS_KEY_VSI_ID_MASK
- I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT
- I40E_AQC_SET_RSS_KEY_VSI_VALID
- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF
- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
- I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI
- I40E_AQC_SET_RSS_LUT_VSI_ID_MASK
- I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT
- I40E_AQC_SET_RSS_LUT_VSI_VALID
- I40E_AQC_SET_VSI_DEFAULT
- I40E_AQC_SET_VSI_PROMISC_BROADCAST
- I40E_AQC_SET_VSI_PROMISC_MULTICAST
- I40E_AQC_SET_VSI_PROMISC_TX
- I40E_AQC_SET_VSI_PROMISC_UNICAST
- I40E_AQC_SET_VSI_PROMISC_VLAN
- I40E_AQC_SET_VSI_VLAN_MASK
- I40E_AQC_SET_VSI_VLAN_VALID
- I40E_AQC_SET_WOL_FILTER
- I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR
- I40E_AQC_SET_WOL_FILTER_ACTION_SET
- I40E_AQC_SET_WOL_FILTER_ACTION_VALID
- I40E_AQC_SET_WOL_FILTER_INDEX_MASK
- I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT
- I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID
- I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL
- I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK
- I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT
- I40E_AQC_SINGLE_PF
- I40E_AQC_START_SPECIFIC_AGENT_MASK
- I40E_AQC_START_SPECIFIC_AGENT_SHIFT
- I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED
- I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN
- I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE
- I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS
- I40E_AQC_TUNNEL_TYPE_NGE
- I40E_AQC_TUNNEL_TYPE_TEREDO
- I40E_AQC_TUNNEL_TYPE_VXLAN
- I40E_AQC_TUNNEL_TYPE_VXLAN_GPE
- I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK
- I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT
- I40E_AQC_VEB_ERR_FLAG_NO_COUNTER
- I40E_AQC_VEB_ERR_FLAG_NO_ENTRY
- I40E_AQC_VEB_ERR_FLAG_NO_SCHED
- I40E_AQC_VEB_ERR_FLAG_NO_VEB
- I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI
- I40E_AQC_VLAN_PTYPE_ISOLATED_VSI
- I40E_AQC_VLAN_PTYPE_MASK
- I40E_AQC_VLAN_PTYPE_PROMISC_VSI
- I40E_AQC_VLAN_PTYPE_REGULAR_VSI
- I40E_AQC_VLAN_PTYPE_SHIFT
- I40E_AQC_VSI_PROM_CMD_SEID_MASK
- I40E_AQC_WOL_ADDR_VALID
- I40E_AQC_WOL_PRESERVE_ON_PFR
- I40E_AQC_WRITE_TYPE_LAA_ONLY
- I40E_AQC_WRITE_TYPE_LAA_WOL
- I40E_AQC_WRITE_TYPE_MASK
- I40E_AQC_WRITE_TYPE_PORT
- I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG
- I40E_AQ_25G_NIMB_UCODE_ERR
- I40E_AQ_25G_NOT_PRESENT
- I40E_AQ_25G_NO_ERR
- I40E_AQ_25G_NVM_CRC_ERR
- I40E_AQ_25G_SBUS_UCODE_ERR
- I40E_AQ_25G_SERDES_UCODE_ERR
- I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY
- I40E_AQ_ALTERNATE_MODE_BIOS_MASK
- I40E_AQ_ALTERNATE_MODE_BIOS_UEFI
- I40E_AQ_ALTERNATE_MODE_NONE
- I40E_AQ_ALTERNATE_MODE_OEM
- I40E_AQ_ALTERNATE_RESET_NEEDED
- I40E_AQ_ANVM_FEATURE
- I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP
- I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY
- I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR
- I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK
- I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT
- I40E_AQ_ANVM_IMMEDIATE_FIELD
- I40E_AQ_ANVM_READ_MULTIPLE_FEATURES
- I40E_AQ_ANVM_READ_SINGLE_FEATURE
- I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK
- I40E_AQ_AN_COMPLETED
- I40E_AQ_ARP_ADD_IPV4
- I40E_AQ_ARP_DEL_IPV4
- I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE
- I40E_AQ_ARP_ENA
- I40E_AQ_ARP_INIT_IPV4
- I40E_AQ_ARP_OFFLOAD_ENABLE
- I40E_AQ_ARP_UNSUP_CTL
- I40E_AQ_CAP_ID_1588
- I40E_AQ_CAP_ID_8021QBG
- I40E_AQ_CAP_ID_8021QBR
- I40E_AQ_CAP_ID_ALTERNATE_RAM
- I40E_AQ_CAP_ID_CEM
- I40E_AQ_CAP_ID_DCB
- I40E_AQ_CAP_ID_FCOE
- I40E_AQ_CAP_ID_FLEX10
- I40E_AQ_CAP_ID_FLOW_DIRECTOR
- I40E_AQ_CAP_ID_FUNCTIONS_VALID
- I40E_AQ_CAP_ID_ISCSI
- I40E_AQ_CAP_ID_IWARP
- I40E_AQ_CAP_ID_LED
- I40E_AQ_CAP_ID_MDIO
- I40E_AQ_CAP_ID_MNG_MODE
- I40E_AQ_CAP_ID_MSIX
- I40E_AQ_CAP_ID_NPAR_ACTIVE
- I40E_AQ_CAP_ID_NVM_MGMT
- I40E_AQ_CAP_ID_OS2BMC_CAP
- I40E_AQ_CAP_ID_RSS
- I40E_AQ_CAP_ID_RXQ
- I40E_AQ_CAP_ID_SDP
- I40E_AQ_CAP_ID_SRIOV
- I40E_AQ_CAP_ID_SWITCH_MODE
- I40E_AQ_CAP_ID_TXQ
- I40E_AQ_CAP_ID_VF
- I40E_AQ_CAP_ID_VF_MSIX
- I40E_AQ_CAP_ID_VMDQ
- I40E_AQ_CAP_ID_VSI
- I40E_AQ_CAP_ID_WOL_AND_PROXY
- I40E_AQ_CAP_ID_WSR_PROT
- I40E_AQ_CLUSTER_ID_ALTRAM
- I40E_AQ_CLUSTER_ID_AUX
- I40E_AQ_CLUSTER_ID_DCB
- I40E_AQ_CLUSTER_ID_EMP_MEM
- I40E_AQ_CLUSTER_ID_HMC
- I40E_AQ_CLUSTER_ID_MAC0
- I40E_AQ_CLUSTER_ID_MAC1
- I40E_AQ_CLUSTER_ID_MAC2
- I40E_AQ_CLUSTER_ID_MAC3
- I40E_AQ_CLUSTER_ID_PKT_BUF
- I40E_AQ_CLUSTER_ID_SWITCH_FLU
- I40E_AQ_CLUSTER_ID_TXSCHED
- I40E_AQ_CONFIG_CRC_ENA
- I40E_AQ_CONFIG_FEC_KR_ENA
- I40E_AQ_CONFIG_FEC_RS_ENA
- I40E_AQ_CONFIG_PACING_MASK
- I40E_AQ_CONN_TYPE_CASCADED
- I40E_AQ_CONN_TYPE_DEFAULT
- I40E_AQ_CONN_TYPE_REGULAR
- I40E_AQ_CPPM_EN_DMARC
- I40E_AQ_CPPM_EN_DMCTH
- I40E_AQ_CPPM_EN_DMCTLX
- I40E_AQ_CPPM_EN_HPTC
- I40E_AQ_CPPM_EN_LTRC
- I40E_AQ_DCB_SET_AGENT
- I40E_AQ_DRIVER_UNLOADING
- I40E_AQ_EEE_1000BASE_KX
- I40E_AQ_EEE_1000BASE_T
- I40E_AQ_EEE_100BASE_TX
- I40E_AQ_EEE_10GBASE_KR
- I40E_AQ_EEE_10GBASE_KX4
- I40E_AQ_EEE_10GBASE_T
- I40E_AQ_ENABLE_FEC_AUTO
- I40E_AQ_ENABLE_FEC_KR
- I40E_AQ_ENABLE_FEC_RS
- I40E_AQ_ETS_SEEPAGE_EN_MASK
- I40E_AQ_EVENT_AN_COMPLETED
- I40E_AQ_EVENT_EXCESSIVE_ERRORS
- I40E_AQ_EVENT_LINK_FAULT
- I40E_AQ_EVENT_LINK_UPDOWN
- I40E_AQ_EVENT_MEDIA_NA
- I40E_AQ_EVENT_MODULE_QUAL_FAIL
- I40E_AQ_EVENT_PHY_TEMP_ALARM
- I40E_AQ_EVENT_PORT_TX_SUSPENDED
- I40E_AQ_EVENT_SIGNAL_DETECT
- I40E_AQ_FEC
- I40E_AQ_FEC_EN
- I40E_AQ_FLAG_BUF
- I40E_AQ_FLAG_BUF_SHIFT
- I40E_AQ_FLAG_CMP
- I40E_AQ_FLAG_CMP_SHIFT
- I40E_AQ_FLAG_DD
- I40E_AQ_FLAG_DD_SHIFT
- I40E_AQ_FLAG_EI
- I40E_AQ_FLAG_EI_SHIFT
- I40E_AQ_FLAG_ERR
- I40E_AQ_FLAG_ERR_SHIFT
- I40E_AQ_FLAG_FE
- I40E_AQ_FLAG_FE_SHIFT
- I40E_AQ_FLAG_LB
- I40E_AQ_FLAG_LB_SHIFT
- I40E_AQ_FLAG_RD
- I40E_AQ_FLAG_RD_SHIFT
- I40E_AQ_FLAG_SI
- I40E_AQ_FLAG_SI_SHIFT
- I40E_AQ_FLAG_VFC
- I40E_AQ_FLAG_VFC_SHIFT
- I40E_AQ_FLAG_VFE
- I40E_AQ_FLAG_VFE_SHIFT
- I40E_AQ_LAA_FLAG_WR
- I40E_AQ_LARGE_BUF
- I40E_AQ_LB_MAC_LOCAL
- I40E_AQ_LB_PHY_LOCAL
- I40E_AQ_LB_PHY_REMOTE
- I40E_AQ_LEN
- I40E_AQ_LINK_FAULT
- I40E_AQ_LINK_FAULT_REMOTE
- I40E_AQ_LINK_FAULT_RX
- I40E_AQ_LINK_FAULT_TX
- I40E_AQ_LINK_FORCED_40G
- I40E_AQ_LINK_PAUSE_RX
- I40E_AQ_LINK_PAUSE_TX
- I40E_AQ_LINK_PHY_TEMP_ALARM
- I40E_AQ_LINK_POWER_CLASS_1
- I40E_AQ_LINK_POWER_CLASS_2
- I40E_AQ_LINK_POWER_CLASS_3
- I40E_AQ_LINK_POWER_CLASS_4
- I40E_AQ_LINK_TX_ACTIVE
- I40E_AQ_LINK_TX_DRAINED
- I40E_AQ_LINK_TX_FLUSHED
- I40E_AQ_LINK_TX_MASK
- I40E_AQ_LINK_TX_SHIFT
- I40E_AQ_LINK_UP
- I40E_AQ_LINK_UP_FUNCTION
- I40E_AQ_LINK_UP_PORT
- I40E_AQ_LINK_XCESSIVE_ERRORS
- I40E_AQ_LIST_CAP_PF_INDEX_EN
- I40E_AQ_LLDP_AGENT_RESTORE
- I40E_AQ_LLDP_AGENT_RESTORE_NOT
- I40E_AQ_LLDP_AGENT_SHUTDOWN
- I40E_AQ_LLDP_AGENT_START
- I40E_AQ_LLDP_AGENT_START_PERSIST
- I40E_AQ_LLDP_AGENT_STOP
- I40E_AQ_LLDP_AGENT_STOP_PERSIST
- I40E_AQ_LLDP_BRIDGE_TYPE_MASK
- I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE
- I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR
- I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT
- I40E_AQ_LLDP_MIB_LOCAL
- I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE
- I40E_AQ_LLDP_MIB_REMOTE
- I40E_AQ_LLDP_MIB_TYPE_MASK
- I40E_AQ_LLDP_MIB_UPDATE_DISABLE
- I40E_AQ_LLDP_MIB_UPDATE_ENABLE
- I40E_AQ_LLDP_TX_MASK
- I40E_AQ_LLDP_TX_SHIFT
- I40E_AQ_LOOPBACK_MASK
- I40E_AQ_LP_AN_ABILITY
- I40E_AQ_LSE_DISABLE
- I40E_AQ_LSE_ENABLE
- I40E_AQ_LSE_IS_ENABLED
- I40E_AQ_LSE_MASK
- I40E_AQ_LSE_NOP
- I40E_AQ_MEDIA_AVAILABLE
- I40E_AQ_MODULE_TYPE_EXT_MASK
- I40E_AQ_MODULE_TYPE_EXT_SHIFT
- I40E_AQ_NS_PROXY_ADD_0
- I40E_AQ_NS_PROXY_ADD_1
- I40E_AQ_NS_PROXY_ADD_IPV6_0
- I40E_AQ_NS_PROXY_ADD_IPV6_1
- I40E_AQ_NS_PROXY_COMMAND_SEQ
- I40E_AQ_NS_PROXY_DEL_0
- I40E_AQ_NS_PROXY_DEL_1
- I40E_AQ_NS_PROXY_DEL_IPV6_0
- I40E_AQ_NS_PROXY_DEL_IPV6_1
- I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE
- I40E_AQ_NS_PROXY_INIT_IPV6_TBL
- I40E_AQ_NS_PROXY_INIT_MAC_TBL
- I40E_AQ_NS_PROXY_OFFLOAD_ENABLE
- I40E_AQ_NVM_FLASH_ONLY
- I40E_AQ_NVM_LAST_CMD
- I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA
- I40E_AQ_NVM_PRESERVATION_FLAGS_ALL
- I40E_AQ_NVM_PRESERVATION_FLAGS_MASK
- I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED
- I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT
- I40E_AQ_NVM_REARRANGE_TO_FLAT
- I40E_AQ_NVM_REARRANGE_TO_STRUCT
- I40E_AQ_OEM_PARAM_MAC
- I40E_AQ_OEM_PARAM_TYPE_BW_CTL
- I40E_AQ_OEM_PARAM_TYPE_PF_CTL
- I40E_AQ_OEM_STATE_LINK_DOWN
- I40E_AQ_OEM_STATE_LINK_UP
- I40E_AQ_PD_FAULT
- I40E_AQ_PHY_AN_ENABLED
- I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW
- I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW
- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD
- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK
- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE
- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT
- I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT
- I40E_AQ_PHY_DEBUG_RESET_INTERNAL
- I40E_AQ_PHY_ENABLE_AN
- I40E_AQ_PHY_ENABLE_ATOMIC_LINK
- I40E_AQ_PHY_ENABLE_LINK
- I40E_AQ_PHY_FEC_ABILITY_KR
- I40E_AQ_PHY_FEC_ABILITY_RS
- I40E_AQ_PHY_FEC_CONFIG_MASK
- I40E_AQ_PHY_FEC_CONFIG_SHIFT
- I40E_AQ_PHY_FLAG_LOW_POWER
- I40E_AQ_PHY_FLAG_MODULE_QUAL
- I40E_AQ_PHY_FLAG_PAUSE_RX
- I40E_AQ_PHY_FLAG_PAUSE_TX
- I40E_AQ_PHY_LINK_ENABLE
- I40E_AQ_PHY_LINK_ENABLED
- I40E_AQ_PHY_LOW_POWER
- I40E_AQ_PHY_MAX_QMS
- I40E_AQ_PHY_REG_ACCESS_EXTERNAL
- I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE
- I40E_AQ_PHY_REG_ACCESS_INTERNAL
- I40E_AQ_PHY_REPORT_INITIAL_VALUES
- I40E_AQ_PHY_REPORT_QUALIFIED_MODULES
- I40E_AQ_PHY_RESTART_AN
- I40E_AQ_PHY_TYPE_EXT_25G_ACC
- I40E_AQ_PHY_TYPE_EXT_25G_AOC
- I40E_AQ_PHY_TYPE_EXT_25G_CR
- I40E_AQ_PHY_TYPE_EXT_25G_KR
- I40E_AQ_PHY_TYPE_EXT_25G_LR
- I40E_AQ_PHY_TYPE_EXT_25G_SR
- I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T
- I40E_AQ_PHY_TYPE_EXT_5GBASE_T
- I40E_AQ_PWR_CLASS_MASK
- I40E_AQ_PWR_CLASS_MASK_LB
- I40E_AQ_PWR_CLASS_SHIFT_LB
- I40E_AQ_QUALIFIED_MODULE
- I40E_AQ_RC_BAD_ADDR
- I40E_AQ_RC_E2BIG
- I40E_AQ_RC_EACCES
- I40E_AQ_RC_EAGAIN
- I40E_AQ_RC_EBUSY
- I40E_AQ_RC_EEXIST
- I40E_AQ_RC_EFAULT
- I40E_AQ_RC_EFBIG
- I40E_AQ_RC_EFLUSHED
- I40E_AQ_RC_EINTR
- I40E_AQ_RC_EINVAL
- I40E_AQ_RC_EIO
- I40E_AQ_RC_EMODE
- I40E_AQ_RC_ENOENT
- I40E_AQ_RC_ENOMEM
- I40E_AQ_RC_ENOSPC
- I40E_AQ_RC_ENOSYS
- I40E_AQ_RC_ENOTTY
- I40E_AQ_RC_ENXIO
- I40E_AQ_RC_EPERM
- I40E_AQ_RC_ERANGE
- I40E_AQ_RC_ESRCH
- I40E_AQ_RC_OK
- I40E_AQ_REQUEST_FEC_KR
- I40E_AQ_REQUEST_FEC_RS
- I40E_AQ_RESOURCE_ACCESS_READ
- I40E_AQ_RESOURCE_ACCESS_WRITE
- I40E_AQ_RESOURCE_NVM
- I40E_AQ_RESOURCE_NVM_READ_TIMEOUT
- I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT
- I40E_AQ_RESOURCE_SDP
- I40E_AQ_RESOURCE_TYPE_ETAG
- I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY
- I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS
- I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS
- I40E_AQ_RESOURCE_TYPE_IP_FILTERS
- I40E_AQ_RESOURCE_TYPE_MACADDR
- I40E_AQ_RESOURCE_TYPE_MIRROR_RULE
- I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH
- I40E_AQ_RESOURCE_TYPE_QUEUE_SETS
- I40E_AQ_RESOURCE_TYPE_STAG
- I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS
- I40E_AQ_RESOURCE_TYPE_UNICAST_HASH
- I40E_AQ_RESOURCE_TYPE_VEB
- I40E_AQ_RESOURCE_TYPE_VLAN
- I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS
- I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL
- I40E_AQ_RESOURCE_TYPE_VN2_KEYS
- I40E_AQ_RESOURCE_TYPE_VSI
- I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY
- I40E_AQ_SET_FEC_ABILITY_KR
- I40E_AQ_SET_FEC_ABILITY_RS
- I40E_AQ_SET_FEC_AUTO
- I40E_AQ_SET_FEC_REQUEST_KR
- I40E_AQ_SET_FEC_REQUEST_RS
- I40E_AQ_SET_MAC_CONFIG_CRC_EN
- I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN
- I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX
- I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX
- I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX
- I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX
- I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX
- I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX
- I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX
- I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX
- I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX
- I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX
- I40E_AQ_SET_MAC_CONFIG_PACING_MASK
- I40E_AQ_SET_MAC_CONFIG_PACING_NONE
- I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT
- I40E_AQ_SET_PHY_D3_LPAN_ENA
- I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK
- I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT
- I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA
- I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS
- I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS
- I40E_AQ_SET_SWITCH_BIT7_VALID
- I40E_AQ_SET_SWITCH_CFG_L2_FILTER
- I40E_AQ_SET_SWITCH_CFG_PROMISC
- I40E_AQ_SET_SWITCH_L4_SRC_PORT
- I40E_AQ_SET_SWITCH_L4_TYPE_BOTH
- I40E_AQ_SET_SWITCH_L4_TYPE_RSVD
- I40E_AQ_SET_SWITCH_L4_TYPE_TCP
- I40E_AQ_SET_SWITCH_L4_TYPE_UDP
- I40E_AQ_SET_SWITCH_MODE_DEFAULT
- I40E_AQ_SET_SWITCH_MODE_L4_PORT
- I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL
- I40E_AQ_SET_SWITCH_MODE_TUNNEL
- I40E_AQ_SIGNAL_DETECT
- I40E_AQ_SW_ELEM_REV_1
- I40E_AQ_SW_ELEM_TYPE_BMC
- I40E_AQ_SW_ELEM_TYPE_EMP
- I40E_AQ_SW_ELEM_TYPE_MAC
- I40E_AQ_SW_ELEM_TYPE_PA
- I40E_AQ_SW_ELEM_TYPE_PF
- I40E_AQ_SW_ELEM_TYPE_PV
- I40E_AQ_SW_ELEM_TYPE_VEB
- I40E_AQ_SW_ELEM_TYPE_VF
- I40E_AQ_SW_ELEM_TYPE_VSI
- I40E_AQ_TEST_CLOSE
- I40E_AQ_TEST_FULL
- I40E_AQ_TEST_INC
- I40E_AQ_TEST_NVM
- I40E_AQ_TEST_OPEN
- I40E_AQ_TEST_PARTIAL
- I40E_AQ_THERMAL_SENSOR_READ_CONFIG
- I40E_AQ_THERMAL_SENSOR_READ_TEMP
- I40E_AQ_THERMAL_SENSOR_SET_CONFIG
- I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG
- I40E_AQ_VSI_CAS_PV_ETAG_PRUNE
- I40E_AQ_VSI_CAS_PV_INSERT_TAG
- I40E_AQ_VSI_CAS_PV_TAGX_COPY
- I40E_AQ_VSI_CAS_PV_TAGX_LEAVE
- I40E_AQ_VSI_CAS_PV_TAGX_MASK
- I40E_AQ_VSI_CAS_PV_TAGX_REMOVE
- I40E_AQ_VSI_CAS_PV_TAGX_SHIFT
- I40E_AQ_VSI_CONN_TYPE_CASCADED
- I40E_AQ_VSI_CONN_TYPE_DEFAULT
- I40E_AQ_VSI_CONN_TYPE_NORMAL
- I40E_AQ_VSI_FLAG_CASCADED_PV
- I40E_AQ_VSI_PROP_CAS_PV_VALID
- I40E_AQ_VSI_PROP_EGRESS_UP_VALID
- I40E_AQ_VSI_PROP_INGRESS_UP_VALID
- I40E_AQ_VSI_PROP_OUTER_UP_VALID
- I40E_AQ_VSI_PROP_QUEUE_MAP_VALID
- I40E_AQ_VSI_PROP_QUEUE_OPT_VALID
- I40E_AQ_VSI_PROP_SCHED_VALID
- I40E_AQ_VSI_PROP_SECURITY_VALID
- I40E_AQ_VSI_PROP_SWITCH_VALID
- I40E_AQ_VSI_PROP_VLAN_VALID
- I40E_AQ_VSI_PVLAN_EMOD_MASK
- I40E_AQ_VSI_PVLAN_EMOD_NOTHING
- I40E_AQ_VSI_PVLAN_EMOD_SHIFT
- I40E_AQ_VSI_PVLAN_EMOD_STR
- I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH
- I40E_AQ_VSI_PVLAN_EMOD_STR_UP
- I40E_AQ_VSI_PVLAN_INSERT_PVID
- I40E_AQ_VSI_PVLAN_MODE_ALL
- I40E_AQ_VSI_PVLAN_MODE_MASK
- I40E_AQ_VSI_PVLAN_MODE_SHIFT
- I40E_AQ_VSI_PVLAN_MODE_TAGGED
- I40E_AQ_VSI_PVLAN_MODE_UNTAGGED
- I40E_AQ_VSI_QS_HANDLE_INVALID
- I40E_AQ_VSI_QUEUE_MASK
- I40E_AQ_VSI_QUEUE_SHIFT
- I40E_AQ_VSI_QUE_MAP_CONTIG
- I40E_AQ_VSI_QUE_MAP_NONCONTIG
- I40E_AQ_VSI_QUE_OPT_FCOE_ENA
- I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA
- I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF
- I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI
- I40E_AQ_VSI_QUE_OPT_TCP_ENA
- I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA
- I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD
- I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK
- I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK
- I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB
- I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB
- I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG
- I40E_AQ_VSI_SW_ID_MASK
- I40E_AQ_VSI_SW_ID_SHIFT
- I40E_AQ_VSI_TC_QUE_NUMBER_MASK
- I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT
- I40E_AQ_VSI_TC_QUE_OFFSET_MASK
- I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT
- I40E_AQ_VSI_TYPE_EMP_MNG
- I40E_AQ_VSI_TYPE_MASK
- I40E_AQ_VSI_TYPE_PF
- I40E_AQ_VSI_TYPE_SHIFT
- I40E_AQ_VSI_TYPE_VF
- I40E_AQ_VSI_TYPE_VMDQ2
- I40E_AQ_VSI_UP_TABLE_UP0_MASK
- I40E_AQ_VSI_UP_TABLE_UP0_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP1_MASK
- I40E_AQ_VSI_UP_TABLE_UP1_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP2_MASK
- I40E_AQ_VSI_UP_TABLE_UP2_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP3_MASK
- I40E_AQ_VSI_UP_TABLE_UP3_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP4_MASK
- I40E_AQ_VSI_UP_TABLE_UP4_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP5_MASK
- I40E_AQ_VSI_UP_TABLE_UP5_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP6_MASK
- I40E_AQ_VSI_UP_TABLE_UP6_SHIFT
- I40E_AQ_VSI_UP_TABLE_UP7_MASK
- I40E_AQ_VSI_UP_TABLE_UP7_SHIFT
- I40E_AQ_WORK_LIMIT
- I40E_ASQ_CMD_TIMEOUT
- I40E_BW_CREDIT_DIVISOR
- I40E_BW_MBPS_DIVISOR
- I40E_CAP_PHY_TYPE_1000BASE_KX
- I40E_CAP_PHY_TYPE_1000BASE_LX
- I40E_CAP_PHY_TYPE_1000BASE_SX
- I40E_CAP_PHY_TYPE_1000BASE_T
- I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL
- I40E_CAP_PHY_TYPE_100BASE_TX
- I40E_CAP_PHY_TYPE_10GBASE_AOC
- I40E_CAP_PHY_TYPE_10GBASE_CR1
- I40E_CAP_PHY_TYPE_10GBASE_CR1_CU
- I40E_CAP_PHY_TYPE_10GBASE_KR
- I40E_CAP_PHY_TYPE_10GBASE_KX4
- I40E_CAP_PHY_TYPE_10GBASE_LR
- I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU
- I40E_CAP_PHY_TYPE_10GBASE_SR
- I40E_CAP_PHY_TYPE_10GBASE_T
- I40E_CAP_PHY_TYPE_20GBASE_KR2
- I40E_CAP_PHY_TYPE_25GBASE_ACC
- I40E_CAP_PHY_TYPE_25GBASE_AOC
- I40E_CAP_PHY_TYPE_25GBASE_CR
- I40E_CAP_PHY_TYPE_25GBASE_KR
- I40E_CAP_PHY_TYPE_25GBASE_LR
- I40E_CAP_PHY_TYPE_25GBASE_SR
- I40E_CAP_PHY_TYPE_2_5GBASE_T
- I40E_CAP_PHY_TYPE_40GBASE_AOC
- I40E_CAP_PHY_TYPE_40GBASE_CR4
- I40E_CAP_PHY_TYPE_40GBASE_CR4_CU
- I40E_CAP_PHY_TYPE_40GBASE_KR4
- I40E_CAP_PHY_TYPE_40GBASE_LR4
- I40E_CAP_PHY_TYPE_40GBASE_SR4
- I40E_CAP_PHY_TYPE_5GBASE_T
- I40E_CAP_PHY_TYPE_SFI
- I40E_CAP_PHY_TYPE_SGMII
- I40E_CAP_PHY_TYPE_XAUI
- I40E_CAP_PHY_TYPE_XFI
- I40E_CAP_PHY_TYPE_XLAUI
- I40E_CAP_PHY_TYPE_XLPPI
- I40E_CEE_APP_SELECTOR_MASK
- I40E_CEE_APP_SEL_ETHTYPE
- I40E_CEE_APP_SEL_TCPIP
- I40E_CEE_DCBX_OUI
- I40E_CEE_DCBX_TYPE
- I40E_CEE_FEAT_TLV_ENABLE_MASK
- I40E_CEE_FEAT_TLV_ERR_MASK
- I40E_CEE_FEAT_TLV_WILLING_MASK
- I40E_CEE_MAX_FEAT_TYPE
- I40E_CEE_OPER_MAX_APPS
- I40E_CEE_PGID_PRIO_0_MASK
- I40E_CEE_PGID_PRIO_0_SHIFT
- I40E_CEE_PGID_PRIO_1_MASK
- I40E_CEE_PGID_PRIO_1_SHIFT
- I40E_CEE_PGID_STRICT
- I40E_CEE_SUBTYPE_APP_PRI
- I40E_CEE_SUBTYPE_CTRL
- I40E_CEE_SUBTYPE_PFC_CFG
- I40E_CEE_SUBTYPE_PG_CFG
- I40E_CHECK_CMD_LENGTH
- I40E_CHECK_STRUCT_LEN
- I40E_CLEAR_PF_SD_ENTRY
- I40E_CLIENT_FLAGS_LAUNCH_ON_PROBE
- I40E_CLIENT_FTYPE_PF
- I40E_CLIENT_FTYPE_VF
- I40E_CLIENT_IWARP
- I40E_CLIENT_MAX_USER_PRIORITY
- I40E_CLIENT_MSIX_ALL
- I40E_CLIENT_RESET_LEVEL_CORE
- I40E_CLIENT_RESET_LEVEL_PF
- I40E_CLIENT_STR_LENGTH
- I40E_CLIENT_VERSION_BUILD
- I40E_CLIENT_VERSION_MAJOR
- I40E_CLIENT_VERSION_MINOR
- I40E_CLIENT_VERSION_STR
- I40E_CLIENT_VSI_FLAG_TCP_ENABLE
- I40E_CLOUD_FIELD_IIP
- I40E_CLOUD_FIELD_IMAC
- I40E_CLOUD_FIELD_IVLAN
- I40E_CLOUD_FIELD_OMAC
- I40E_CLOUD_FIELD_TEN_ID
- I40E_CLOUD_FILTER_FLAGS_IIP
- I40E_CLOUD_FILTER_FLAGS_IMAC
- I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN
- I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID
- I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID
- I40E_CLOUD_FILTER_FLAGS_OMAC
- I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC
- I40E_CLOUD_FILTER_MODE1
- I40E_CLOUD_FILTER_MODE2
- I40E_CLOUD_FILTER_MODE3
- I40E_CLOUD_TNL_TYPE_NONE
- I40E_COMBINED_ACTIVITY
- I40E_CURRENT_NVM_VERSION_HI
- I40E_CURRENT_NVM_VERSION_LO
- I40E_DCBX_APPS_NON_WILLING
- I40E_DCBX_MAX_APPS
- I40E_DCBX_MODE_CEE
- I40E_DCBX_MODE_IEEE
- I40E_DCBX_STATUS_DISABLED
- I40E_DCBX_STATUS_DONE
- I40E_DCBX_STATUS_IN_PROGRESS
- I40E_DCBX_STATUS_MULTIPLE_PEERS
- I40E_DCBX_STATUS_NOT_STARTED
- I40E_DCB_PRIO_TYPE_ETS
- I40E_DCB_PRIO_TYPE_STRICT
- I40E_DCB_STRICT_PRIO_CREDITS
- I40E_DCB_VALID
- I40E_DDP_ADD_TRACKID
- I40E_DDP_NAME_SIZE
- I40E_DDP_PROFILE_NAME_MAX
- I40E_DDP_PROFILE_PATH
- I40E_DDP_REMOVE_TRACKID
- I40E_DDP_TRACKID_INVALID
- I40E_DDP_TRACKID_RDONLY
- I40E_DEBUG_ALL
- I40E_DEBUG_AQ
- I40E_DEBUG_AQ_COMMAND
- I40E_DEBUG_AQ_DESCRIPTOR
- I40E_DEBUG_AQ_DESC_BUFFER
- I40E_DEBUG_AQ_MESSAGE
- I40E_DEBUG_DCB
- I40E_DEBUG_DIAG
- I40E_DEBUG_FD
- I40E_DEBUG_FLOW
- I40E_DEBUG_HMC
- I40E_DEBUG_INIT
- I40E_DEBUG_IWARP
- I40E_DEBUG_LAN
- I40E_DEBUG_LINK
- I40E_DEBUG_NVM
- I40E_DEBUG_PACKAGE
- I40E_DEBUG_PHY
- I40E_DEBUG_RELEASE
- I40E_DEBUG_USER
- I40E_DEC_BP_REFCNT
- I40E_DEC_PD_REFCNT
- I40E_DEC_SD_REFCNT
- I40E_DEFAULT_ATR_SAMPLE_RATE
- I40E_DEFAULT_IRQ_WORK
- I40E_DEFAULT_MSG_ENABLE
- I40E_DEFAULT_NUM_DESCRIPTORS
- I40E_DEFAULT_NUM_INVALID_MSGS_ALLOWED
- I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED
- I40E_DEFAULT_NUM_VMDQ_VSI
- I40E_DEFAULT_QUEUES_PER_TC
- I40E_DEFAULT_QUEUES_PER_VF
- I40E_DEFAULT_RSS_HENA
- I40E_DEFAULT_RSS_HENA_EXPANDED
- I40E_DEFAULT_TRAFFIC_CLASS
- I40E_DESC_UNUSED
- I40E_DEV_ID_10G_B
- I40E_DEV_ID_10G_BASE_T
- I40E_DEV_ID_10G_BASE_T4
- I40E_DEV_ID_10G_BASE_T_BC
- I40E_DEV_ID_10G_BASE_T_X722
- I40E_DEV_ID_10G_SFP
- I40E_DEV_ID_1G_BASE_T_X722
- I40E_DEV_ID_20G_KR2
- I40E_DEV_ID_20G_KR2_A
- I40E_DEV_ID_25G_B
- I40E_DEV_ID_25G_SFP28
- I40E_DEV_ID_KX_B
- I40E_DEV_ID_KX_C
- I40E_DEV_ID_KX_X722
- I40E_DEV_ID_QEMU
- I40E_DEV_ID_QSFP_A
- I40E_DEV_ID_QSFP_B
- I40E_DEV_ID_QSFP_C
- I40E_DEV_ID_QSFP_X722
- I40E_DEV_ID_SFP_I_X722
- I40E_DEV_ID_SFP_X722
- I40E_DEV_ID_SFP_XL710
- I40E_DEV_ID_X710_N3000
- I40E_DEV_ID_XXV710_N3000
- I40E_DMA_CNTX_BASE_SIZE
- I40E_DMA_CNTX_SIZE_128K
- I40E_DMA_CNTX_SIZE_16K
- I40E_DMA_CNTX_SIZE_1K
- I40E_DMA_CNTX_SIZE_256K
- I40E_DMA_CNTX_SIZE_2K
- I40E_DMA_CNTX_SIZE_32K
- I40E_DMA_CNTX_SIZE_4K
- I40E_DMA_CNTX_SIZE_512
- I40E_DMA_CNTX_SIZE_64K
- I40E_DMA_CNTX_SIZE_8K
- I40E_EMPINT_GPIO_ENA
- I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT
- I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK
- I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT
- I40E_EMP_MODULE_PTR
- I40E_ERR_ADAPTER_STOPPED
- I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR
- I40E_ERR_ADMIN_QUEUE_ERROR
- I40E_ERR_ADMIN_QUEUE_FULL
- I40E_ERR_ADMIN_QUEUE_NO_WORK
- I40E_ERR_ADMIN_QUEUE_TIMEOUT
- I40E_ERR_AUTONEG_NOT_COMPLETE
- I40E_ERR_BACKING_PAGE_ERROR
- I40E_ERR_BAD_IWARP_CQE
- I40E_ERR_BAD_PTR
- I40E_ERR_BUF_TOO_SHORT
- I40E_ERR_CONFIG
- I40E_ERR_CQP_COMPL_ERROR
- I40E_ERR_DEVICE_NOT_SUPPORTED
- I40E_ERR_DIAG_TEST_FAILED
- I40E_ERR_FIRMWARE_API_VERSION
- I40E_ERR_FLUSHED_QUEUE
- I40E_ERR_INVALID_AEQ_ID
- I40E_ERR_INVALID_ALIGNMENT
- I40E_ERR_INVALID_ARP_INDEX
- I40E_ERR_INVALID_CEQ_ID
- I40E_ERR_INVALID_CQ_ID
- I40E_ERR_INVALID_FPM_FUNC_ID
- I40E_ERR_INVALID_FRAG_COUNT
- I40E_ERR_INVALID_HMCFN_ID
- I40E_ERR_INVALID_HMC_OBJ_COUNT
- I40E_ERR_INVALID_HMC_OBJ_INDEX
- I40E_ERR_INVALID_IMM_DATA_SIZE
- I40E_ERR_INVALID_LINK_SETTINGS
- I40E_ERR_INVALID_MAC_ADDR
- I40E_ERR_INVALID_PAGE_DESC_INDEX
- I40E_ERR_INVALID_PBLE_INDEX
- I40E_ERR_INVALID_PD_ID
- I40E_ERR_INVALID_PUSH_PAGE_INDEX
- I40E_ERR_INVALID_QP_ID
- I40E_ERR_INVALID_SD_INDEX
- I40E_ERR_INVALID_SD_TYPE
- I40E_ERR_INVALID_SIZE
- I40E_ERR_INVALID_SRQ_ARM_LIMIT
- I40E_ERR_INVALID_VF_ID
- I40E_ERR_LINK_SETUP
- I40E_ERR_MAC_TYPE
- I40E_ERR_MASTER_REQUESTS_PENDING
- I40E_ERR_MEMCPY_FAILED
- I40E_ERR_NOT_IMPLEMENTED
- I40E_ERR_NOT_READY
- I40E_ERR_NO_AVAILABLE_VSI
- I40E_ERR_NO_MEMORY
- I40E_ERR_NO_PBLCHUNKS_AVAILABLE
- I40E_ERR_NVM
- I40E_ERR_NVM_BLANK_MODE
- I40E_ERR_NVM_CHECKSUM
- I40E_ERR_OPCODE_MISMATCH
- I40E_ERR_PARAM
- I40E_ERR_PE_DOORBELL_NOT_ENABLED
- I40E_ERR_PHY
- I40E_ERR_QP_INVALID_MSG_SIZE
- I40E_ERR_QP_TOOMANY_WRS_POSTED
- I40E_ERR_QUEUE_EMPTY
- I40E_ERR_RESET_FAILED
- I40E_ERR_RING_FULL
- I40E_ERR_SRQ_ENABLED
- I40E_ERR_SWFW_SYNC
- I40E_ERR_TIMEOUT
- I40E_ERR_UNKNOWN_PHY
- I40E_ETHERTYPE_FLTR
- I40E_ETHER_TYPE_1588
- I40E_ETHER_TYPE_8021X
- I40E_ETHER_TYPE_ARP
- I40E_ETHER_TYPE_EVB_PROTOCOL1
- I40E_ETHER_TYPE_EVB_PROTOCOL2
- I40E_ETHER_TYPE_FIP
- I40E_ETHER_TYPE_LLDP
- I40E_ETHER_TYPE_MAC_CONTROL
- I40E_ETHER_TYPE_OUI_EXTENDED
- I40E_ETHER_TYPE_QCN_CNM
- I40E_ETHER_TYPE_RSV1
- I40E_ETHER_TYPE_RSV2
- I40E_ETH_TEST_EEPROM
- I40E_ETH_TEST_INTR
- I40E_ETH_TEST_LINK
- I40E_ETH_TEST_REG
- I40E_FCOE_CTX_FLTR
- I40E_FC_DEFAULT
- I40E_FC_FULL
- I40E_FC_NONE
- I40E_FC_PFC
- I40E_FC_RX_PAUSE
- I40E_FC_TX_PAUSE
- I40E_FDEVICT_PCTYPE_DEFAULT
- I40E_FDIR_BUFFER_FULL_MARGIN
- I40E_FDIR_BUFFER_HEAD_ROOM
- I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR
- I40E_FDIR_MAX_RAW_PACKET_SIZE
- I40E_FDIR_RING
- I40E_FDIR_RING_COUNT
- I40E_FD_ATR_STAT_IDX
- I40E_FD_ATR_TUNNEL_STAT_IDX
- I40E_FD_CLEAN_DELAY
- I40E_FD_SB_STAT_IDX
- I40E_FD_STAT_ATR
- I40E_FD_STAT_ATR_TUNNEL
- I40E_FD_STAT_PF_COUNT
- I40E_FD_STAT_PF_IDX
- I40E_FD_STAT_SB
- I40E_FILTER_ACTIVE
- I40E_FILTER_ACTIVITY
- I40E_FILTER_FAILED
- I40E_FILTER_INVALID
- I40E_FILTER_NEW
- I40E_FILTER_PCTYPE_FCOE_OTHER
- I40E_FILTER_PCTYPE_FCOE_OX
- I40E_FILTER_PCTYPE_FCOE_RX
- I40E_FILTER_PCTYPE_FRAG_IPV4
- I40E_FILTER_PCTYPE_FRAG_IPV6
- I40E_FILTER_PCTYPE_L2_PAYLOAD
- I40E_FILTER_PCTYPE_NONF_IPV4_OTHER
- I40E_FILTER_PCTYPE_NONF_IPV4_SCTP
- I40E_FILTER_PCTYPE_NONF_IPV4_TCP
- I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK
- I40E_FILTER_PCTYPE_NONF_IPV4_UDP
- I40E_FILTER_PCTYPE_NONF_IPV6_OTHER
- I40E_FILTER_PCTYPE_NONF_IPV6_SCTP
- I40E_FILTER_PCTYPE_NONF_IPV6_TCP
- I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK
- I40E_FILTER_PCTYPE_NONF_IPV6_UDP
- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP
- I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP
- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP
- I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP
- I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER
- I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX
- I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET
- I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES
- I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID
- I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES
- I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE
- I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE
- I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE
- I40E_FILTER_REMOVE
- I40E_FIND_PD_INDEX_LIMIT
- I40E_FIND_SD_INDEX_LIMIT
- I40E_FIRST_VF_FPM_ID
- I40E_FLAG_BASE_R_FEC
- I40E_FLAG_DCB_CAPABLE
- I40E_FLAG_DCB_ENABLED
- I40E_FLAG_DISABLE_FW_LLDP
- I40E_FLAG_FD_ATR_ENABLED
- I40E_FLAG_FD_SB_ENABLED
- I40E_FLAG_FD_SB_INACTIVE
- I40E_FLAG_FD_SB_TO_CLOUD_FILTER
- I40E_FLAG_HW_ATR_EVICT_ENABLED
- I40E_FLAG_IWARP_ENABLED
- I40E_FLAG_LEGACY_RX
- I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED
- I40E_FLAG_LINK_POLLING_ENABLED
- I40E_FLAG_MFP_ENABLED
- I40E_FLAG_MSIX_ENABLED
- I40E_FLAG_MSI_ENABLED
- I40E_FLAG_PTP
- I40E_FLAG_RSS_ENABLED
- I40E_FLAG_RS_FEC
- I40E_FLAG_RX_CSUM_ENABLED
- I40E_FLAG_SOURCE_PRUNING_DISABLED
- I40E_FLAG_SRIOV_ENABLED
- I40E_FLAG_TC_MQPRIO
- I40E_FLAG_TRUE_PROMISC_SUPPORT
- I40E_FLAG_VEB_MODE_ENABLED
- I40E_FLAG_VEB_STATS_ENABLED
- I40E_FLAG_VMDQ_ENABLED
- I40E_FLEX10_MODE_DCC
- I40E_FLEX10_MODE_DCI
- I40E_FLEX10_MODE_UNKNOWN
- I40E_FLEX10_STATUS_DCC_ERROR
- I40E_FLEX10_STATUS_VC_MODE
- I40E_FLEX_50_MASK
- I40E_FLEX_50_SHIFT
- I40E_FLEX_51_MASK
- I40E_FLEX_51_SHIFT
- I40E_FLEX_52_MASK
- I40E_FLEX_52_SHIFT
- I40E_FLEX_53_MASK
- I40E_FLEX_53_SHIFT
- I40E_FLEX_54_MASK
- I40E_FLEX_54_SHIFT
- I40E_FLEX_55_MASK
- I40E_FLEX_55_SHIFT
- I40E_FLEX_56_MASK
- I40E_FLEX_56_SHIFT
- I40E_FLEX_57_MASK
- I40E_FLEX_57_SHIFT
- I40E_FLEX_DEST_UNUSED
- I40E_FLEX_INDEX_ENTRIES
- I40E_FLEX_INPUT_MASK
- I40E_FLEX_PIT_GET_DST
- I40E_FLEX_PIT_GET_FSIZE
- I40E_FLEX_PIT_GET_SRC
- I40E_FLEX_PIT_IDX_START_L2
- I40E_FLEX_PIT_IDX_START_L3
- I40E_FLEX_PIT_IDX_START_L4
- I40E_FLEX_PIT_TABLE_SIZE
- I40E_FLEX_PREP_VAL
- I40E_FLEX_SET_DST_WORD
- I40E_FLEX_SET_FSIZE
- I40E_FLEX_SET_SRC_WORD
- I40E_FLOW_CONTROL_ETHTYPE
- I40E_FLOW_DIRECTOR_FLTR
- I40E_FW_API_VERSION_MAJOR
- I40E_FW_API_VERSION_MINOR_X710
- I40E_FW_API_VERSION_MINOR_X722
- I40E_FW_MINOR_VERSION
- I40E_GET_PFC_STAT
- I40E_GLCM_LAN_CACHESIZE
- I40E_GLCM_LAN_CACHESIZE_SETS_MASK
- I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT
- I40E_GLCM_LAN_CACHESIZE_WAYS_MASK
- I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT
- I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK
- I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLCM_PE_CACHESIZE
- I40E_GLCM_PE_CACHESIZE_SETS_MASK
- I40E_GLCM_PE_CACHESIZE_SETS_SHIFT
- I40E_GLCM_PE_CACHESIZE_WAYS_MASK
- I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT
- I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK
- I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLDCB_GENC
- I40E_GLDCB_GENC_PCIRTT_MASK
- I40E_GLDCB_GENC_PCIRTT_SHIFT
- I40E_GLDCB_RUPTI
- I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK
- I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT
- I40E_GLFCOE_RCTL
- I40E_GLFCOE_RCTL_FCOEVER_MASK
- I40E_GLFCOE_RCTL_FCOEVER_SHIFT
- I40E_GLFCOE_RCTL_ICRC_MASK
- I40E_GLFCOE_RCTL_ICRC_SHIFT
- I40E_GLFCOE_RCTL_MAX_SIZE_MASK
- I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT
- I40E_GLFCOE_RCTL_SAVBAD_MASK
- I40E_GLFCOE_RCTL_SAVBAD_SHIFT
- I40E_GLFOC_CACHESIZE
- I40E_GLFOC_CACHESIZE_SETS_MASK
- I40E_GLFOC_CACHESIZE_SETS_SHIFT
- I40E_GLFOC_CACHESIZE_WAYS_MASK
- I40E_GLFOC_CACHESIZE_WAYS_SHIFT
- I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK
- I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLGEN_CAR_DEBUG
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT
- I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK
- I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT
- I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK
- I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT
- I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK
- I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT
- I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK
- I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT
- I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK
- I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT
- I40E_GLGEN_CLKSTAT
- I40E_GLGEN_CLKSTAT_CLKMODE_MASK
- I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT
- I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK
- I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT
- I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK
- I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT
- I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK
- I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT
- I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK
- I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT
- I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK
- I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT
- I40E_GLGEN_GPIO_CTL
- I40E_GLGEN_GPIO_CTL_INT_MODE_MASK
- I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT
- I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK
- I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT
- I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK
- I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT
- I40E_GLGEN_GPIO_CTL_LED_MODE_MASK
- I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT
- I40E_GLGEN_GPIO_CTL_MAX_INDEX
- I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK
- I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT
- I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK
- I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT
- I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK
- I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT
- I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK
- I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT
- I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK
- I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT
- I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK
- I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT
- I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK
- I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK
- I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT
- I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT
- I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK
- I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT
- I40E_GLGEN_GPIO_SET
- I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK
- I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT
- I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK
- I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT
- I40E_GLGEN_GPIO_SET_SDP_DATA_MASK
- I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT
- I40E_GLGEN_GPIO_STAT
- I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK
- I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT
- I40E_GLGEN_GPIO_TRANSIT
- I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK
- I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT
- I40E_GLGEN_I2CCMD
- I40E_GLGEN_I2CCMD_DATA_MASK
- I40E_GLGEN_I2CCMD_DATA_SHIFT
- I40E_GLGEN_I2CCMD_E_MASK
- I40E_GLGEN_I2CCMD_E_SHIFT
- I40E_GLGEN_I2CCMD_MAX_INDEX
- I40E_GLGEN_I2CCMD_OP_MASK
- I40E_GLGEN_I2CCMD_OP_SHIFT
- I40E_GLGEN_I2CCMD_PHYADD_MASK
- I40E_GLGEN_I2CCMD_PHYADD_SHIFT
- I40E_GLGEN_I2CCMD_REGADD_MASK
- I40E_GLGEN_I2CCMD_REGADD_SHIFT
- I40E_GLGEN_I2CCMD_RESET_MASK
- I40E_GLGEN_I2CCMD_RESET_SHIFT
- I40E_GLGEN_I2CCMD_R_MASK
- I40E_GLGEN_I2CCMD_R_SHIFT
- I40E_GLGEN_I2CPARAMS
- I40E_GLGEN_I2CPARAMS_CLK_IN_MASK
- I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT
- I40E_GLGEN_I2CPARAMS_CLK_MASK
- I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK
- I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT
- I40E_GLGEN_I2CPARAMS_CLK_SHIFT
- I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK
- I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT
- I40E_GLGEN_I2CPARAMS_DATA_IN_MASK
- I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT
- I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK
- I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT
- I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK
- I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT
- I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK
- I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT
- I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK
- I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT
- I40E_GLGEN_I2CPARAMS_MAX_INDEX
- I40E_GLGEN_I2CPARAMS_READ_TIME_MASK
- I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT
- I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK
- I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT
- I40E_GLGEN_LED_CTL
- I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK
- I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT
- I40E_GLGEN_MDIO_CTRL
- I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK
- I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK
- I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT
- I40E_GLGEN_MDIO_CTRL_MAX_INDEX
- I40E_GLGEN_MDIO_I2C_SEL
- I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK
- I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX
- I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK
- I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK
- I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK
- I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK
- I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK
- I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK
- I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT
- I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK
- I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT
- I40E_GLGEN_MISC_SPARE
- I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK
- I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT
- I40E_GLGEN_MSCA
- I40E_GLGEN_MSCA_DEVADD_MASK
- I40E_GLGEN_MSCA_DEVADD_SHIFT
- I40E_GLGEN_MSCA_MAX_INDEX
- I40E_GLGEN_MSCA_MDIADD_MASK
- I40E_GLGEN_MSCA_MDIADD_SHIFT
- I40E_GLGEN_MSCA_MDICMD_MASK
- I40E_GLGEN_MSCA_MDICMD_SHIFT
- I40E_GLGEN_MSCA_MDIINPROGEN_MASK
- I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT
- I40E_GLGEN_MSCA_OPCODE_MASK
- I40E_GLGEN_MSCA_OPCODE_SHIFT
- I40E_GLGEN_MSCA_PHYADD_MASK
- I40E_GLGEN_MSCA_PHYADD_SHIFT
- I40E_GLGEN_MSCA_STCODE_MASK
- I40E_GLGEN_MSCA_STCODE_SHIFT
- I40E_GLGEN_MSRWD
- I40E_GLGEN_MSRWD_MAX_INDEX
- I40E_GLGEN_MSRWD_MDIRDDATA_MASK
- I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT
- I40E_GLGEN_MSRWD_MDIWRDATA_MASK
- I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT
- I40E_GLGEN_PCIFCNCNT
- I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK
- I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT
- I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK
- I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT
- I40E_GLGEN_PME_TO
- I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK
- I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT
- I40E_GLGEN_RSTAT
- I40E_GLGEN_RSTAT_CORERCNT_MASK
- I40E_GLGEN_RSTAT_CORERCNT_SHIFT
- I40E_GLGEN_RSTAT_DEVSTATE_MASK
- I40E_GLGEN_RSTAT_DEVSTATE_SHIFT
- I40E_GLGEN_RSTAT_EMPRCNT_MASK
- I40E_GLGEN_RSTAT_EMPRCNT_SHIFT
- I40E_GLGEN_RSTAT_GLOBRCNT_MASK
- I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT
- I40E_GLGEN_RSTAT_RESET_TYPE_MASK
- I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT
- I40E_GLGEN_RSTAT_TIME_TO_RST_MASK
- I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT
- I40E_GLGEN_RSTCTL
- I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK
- I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT
- I40E_GLGEN_RSTCTL_GRSTDEL_MASK
- I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT
- I40E_GLGEN_RTRIG
- I40E_GLGEN_RTRIG_CORER_MASK
- I40E_GLGEN_RTRIG_CORER_SHIFT
- I40E_GLGEN_RTRIG_EMPFWR_MASK
- I40E_GLGEN_RTRIG_EMPFWR_SHIFT
- I40E_GLGEN_RTRIG_GLOBR_MASK
- I40E_GLGEN_RTRIG_GLOBR_SHIFT
- I40E_GLGEN_STAT
- I40E_GLGEN_STAT_CLEAR
- I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK
- I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT
- I40E_GLGEN_STAT_DCBEN_MASK
- I40E_GLGEN_STAT_DCBEN_SHIFT
- I40E_GLGEN_STAT_EVBEN_MASK
- I40E_GLGEN_STAT_EVBEN_SHIFT
- I40E_GLGEN_STAT_FCOEN_MASK
- I40E_GLGEN_STAT_FCOEN_SHIFT
- I40E_GLGEN_STAT_HALT
- I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK
- I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT
- I40E_GLGEN_STAT_HWRSVD0_MASK
- I40E_GLGEN_STAT_HWRSVD0_SHIFT
- I40E_GLGEN_STAT_HWRSVD1_MASK
- I40E_GLGEN_STAT_HWRSVD1_SHIFT
- I40E_GLGEN_STAT_VTEN_MASK
- I40E_GLGEN_STAT_VTEN_SHIFT
- I40E_GLGEN_VFLRSTAT
- I40E_GLGEN_VFLRSTAT_MAX_INDEX
- I40E_GLGEN_VFLRSTAT_VFLRE_MASK
- I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT
- I40E_GLHMC_APBVTINUSEBASE
- I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK
- I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT
- I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX
- I40E_GLHMC_CEQPART
- I40E_GLHMC_CEQPART_MAX_INDEX
- I40E_GLHMC_CEQPART_PMCEQBASE_MASK
- I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT
- I40E_GLHMC_CEQPART_PMCEQSIZE_MASK
- I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT
- I40E_GLHMC_DBCQMAX
- I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK
- I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT
- I40E_GLHMC_DBCQPART
- I40E_GLHMC_DBCQPART_MAX_INDEX
- I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK
- I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT
- I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK
- I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT
- I40E_GLHMC_DBQPMAX
- I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK
- I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT
- I40E_GLHMC_DBQPPART
- I40E_GLHMC_DBQPPART_MAX_INDEX
- I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK
- I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT
- I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK
- I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT
- I40E_GLHMC_FCOEDDPBASE
- I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK
- I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT
- I40E_GLHMC_FCOEDDPBASE_MAX_INDEX
- I40E_GLHMC_FCOEDDPCNT
- I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK
- I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT
- I40E_GLHMC_FCOEDDPCNT_MAX_INDEX
- I40E_GLHMC_FCOEDDPOBJSZ
- I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK
- I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT
- I40E_GLHMC_FCOEFBASE
- I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK
- I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT
- I40E_GLHMC_FCOEFBASE_MAX_INDEX
- I40E_GLHMC_FCOEFCNT
- I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK
- I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT
- I40E_GLHMC_FCOEFCNT_MAX_INDEX
- I40E_GLHMC_FCOEFMAX
- I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK
- I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT
- I40E_GLHMC_FCOEFOBJSZ
- I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK
- I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT
- I40E_GLHMC_FCOEMAX
- I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK
- I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT
- I40E_GLHMC_FSIAVBASE
- I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK
- I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT
- I40E_GLHMC_FSIAVBASE_MAX_INDEX
- I40E_GLHMC_FSIAVCNT
- I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK
- I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT
- I40E_GLHMC_FSIAVCNT_MAX_INDEX
- I40E_GLHMC_FSIAVCNT_RSVD_MASK
- I40E_GLHMC_FSIAVCNT_RSVD_SHIFT
- I40E_GLHMC_FSIAVMAX
- I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK
- I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT
- I40E_GLHMC_FSIAVOBJSZ
- I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK
- I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT
- I40E_GLHMC_FSIMCBASE
- I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK
- I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT
- I40E_GLHMC_FSIMCBASE_MAX_INDEX
- I40E_GLHMC_FSIMCCNT
- I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK
- I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT
- I40E_GLHMC_FSIMCCNT_MAX_INDEX
- I40E_GLHMC_FSIMCMAX
- I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK
- I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT
- I40E_GLHMC_FSIMCOBJSZ
- I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK
- I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT
- I40E_GLHMC_LANQMAX
- I40E_GLHMC_LANQMAX_PMLANQMAX_MASK
- I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT
- I40E_GLHMC_LANRXBASE
- I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK
- I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT
- I40E_GLHMC_LANRXBASE_MAX_INDEX
- I40E_GLHMC_LANRXCNT
- I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK
- I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT
- I40E_GLHMC_LANRXCNT_MAX_INDEX
- I40E_GLHMC_LANRXOBJSZ
- I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK
- I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT
- I40E_GLHMC_LANTXBASE
- I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK
- I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT
- I40E_GLHMC_LANTXBASE_MAX_INDEX
- I40E_GLHMC_LANTXBASE_RSVD_MASK
- I40E_GLHMC_LANTXBASE_RSVD_SHIFT
- I40E_GLHMC_LANTXCNT
- I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK
- I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT
- I40E_GLHMC_LANTXCNT_MAX_INDEX
- I40E_GLHMC_LANTXOBJSZ
- I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK
- I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT
- I40E_GLHMC_PEARPBASE
- I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK
- I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT
- I40E_GLHMC_PEARPBASE_MAX_INDEX
- I40E_GLHMC_PEARPCNT
- I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK
- I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT
- I40E_GLHMC_PEARPCNT_MAX_INDEX
- I40E_GLHMC_PEARPMAX
- I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK
- I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT
- I40E_GLHMC_PEARPOBJSZ
- I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK
- I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT
- I40E_GLHMC_PECQBASE
- I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK
- I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT
- I40E_GLHMC_PECQBASE_MAX_INDEX
- I40E_GLHMC_PECQCNT
- I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK
- I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT
- I40E_GLHMC_PECQCNT_MAX_INDEX
- I40E_GLHMC_PECQOBJSZ
- I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK
- I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT
- I40E_GLHMC_PEHTCNT
- I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK
- I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT
- I40E_GLHMC_PEHTCNT_MAX_INDEX
- I40E_GLHMC_PEHTEBASE
- I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK
- I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT
- I40E_GLHMC_PEHTEBASE_MAX_INDEX
- I40E_GLHMC_PEHTEOBJSZ
- I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK
- I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT
- I40E_GLHMC_PEHTMAX
- I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK
- I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT
- I40E_GLHMC_PEMRBASE
- I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK
- I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT
- I40E_GLHMC_PEMRBASE_MAX_INDEX
- I40E_GLHMC_PEMRCNT
- I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK
- I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT
- I40E_GLHMC_PEMRCNT_MAX_INDEX
- I40E_GLHMC_PEMRMAX
- I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK
- I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT
- I40E_GLHMC_PEMROBJSZ
- I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK
- I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT
- I40E_GLHMC_PEPBLBASE
- I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK
- I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT
- I40E_GLHMC_PEPBLBASE_MAX_INDEX
- I40E_GLHMC_PEPBLCNT
- I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK
- I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT
- I40E_GLHMC_PEPBLCNT_MAX_INDEX
- I40E_GLHMC_PEPBLMAX
- I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK
- I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT
- I40E_GLHMC_PEPFFIRSTSD
- I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK
- I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT
- I40E_GLHMC_PEQ1BASE
- I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK
- I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT
- I40E_GLHMC_PEQ1BASE_MAX_INDEX
- I40E_GLHMC_PEQ1CNT
- I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK
- I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT
- I40E_GLHMC_PEQ1CNT_MAX_INDEX
- I40E_GLHMC_PEQ1FLBASE
- I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK
- I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT
- I40E_GLHMC_PEQ1FLBASE_MAX_INDEX
- I40E_GLHMC_PEQ1FLMAX
- I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK
- I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT
- I40E_GLHMC_PEQ1MAX
- I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK
- I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT
- I40E_GLHMC_PEQ1OBJSZ
- I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK
- I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT
- I40E_GLHMC_PEQPBASE
- I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK
- I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT
- I40E_GLHMC_PEQPBASE_MAX_INDEX
- I40E_GLHMC_PEQPCNT
- I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK
- I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT
- I40E_GLHMC_PEQPCNT_MAX_INDEX
- I40E_GLHMC_PEQPOBJSZ
- I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK
- I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT
- I40E_GLHMC_PESRQBASE
- I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK
- I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT
- I40E_GLHMC_PESRQBASE_MAX_INDEX
- I40E_GLHMC_PESRQCNT
- I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK
- I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT
- I40E_GLHMC_PESRQCNT_MAX_INDEX
- I40E_GLHMC_PESRQMAX
- I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK
- I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT
- I40E_GLHMC_PESRQOBJSZ
- I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK
- I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT
- I40E_GLHMC_PETIMERBASE
- I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK
- I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT
- I40E_GLHMC_PETIMERBASE_MAX_INDEX
- I40E_GLHMC_PETIMERCNT
- I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK
- I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT
- I40E_GLHMC_PETIMERCNT_MAX_INDEX
- I40E_GLHMC_PETIMERMAX
- I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK
- I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT
- I40E_GLHMC_PETIMEROBJSZ
- I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK
- I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT
- I40E_GLHMC_PEXFBASE
- I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK
- I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT
- I40E_GLHMC_PEXFBASE_MAX_INDEX
- I40E_GLHMC_PEXFCNT
- I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK
- I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT
- I40E_GLHMC_PEXFCNT_MAX_INDEX
- I40E_GLHMC_PEXFFLBASE
- I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK
- I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT
- I40E_GLHMC_PEXFFLBASE_MAX_INDEX
- I40E_GLHMC_PEXFFLMAX
- I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK
- I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT
- I40E_GLHMC_PEXFMAX
- I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK
- I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT
- I40E_GLHMC_PEXFOBJSZ
- I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK
- I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT
- I40E_GLHMC_PFASSIGN
- I40E_GLHMC_PFASSIGN_MAX_INDEX
- I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK
- I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT
- I40E_GLHMC_PFPESDPART
- I40E_GLHMC_PFPESDPART_MAX_INDEX
- I40E_GLHMC_PFPESDPART_PMSDBASE_MASK
- I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT
- I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK
- I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT
- I40E_GLHMC_SDPART
- I40E_GLHMC_SDPART_MAX_INDEX
- I40E_GLHMC_SDPART_PMSDBASE_MASK
- I40E_GLHMC_SDPART_PMSDBASE_SHIFT
- I40E_GLHMC_SDPART_PMSDSIZE_MASK
- I40E_GLHMC_SDPART_PMSDSIZE_SHIFT
- I40E_GLHMC_VFAPBVTINUSEBASE
- I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK
- I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT
- I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX
- I40E_GLHMC_VFCEQPART
- I40E_GLHMC_VFCEQPART_MAX_INDEX
- I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK
- I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT
- I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK
- I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT
- I40E_GLHMC_VFDBCQPART
- I40E_GLHMC_VFDBCQPART_MAX_INDEX
- I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK
- I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT
- I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK
- I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT
- I40E_GLHMC_VFDBQPPART
- I40E_GLHMC_VFDBQPPART_MAX_INDEX
- I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK
- I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT
- I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK
- I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT
- I40E_GLHMC_VFFSIAVBASE
- I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK
- I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT
- I40E_GLHMC_VFFSIAVBASE_MAX_INDEX
- I40E_GLHMC_VFFSIAVCNT
- I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK
- I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT
- I40E_GLHMC_VFFSIAVCNT_MAX_INDEX
- I40E_GLHMC_VFPDINV
- I40E_GLHMC_VFPDINV_MAX_INDEX
- I40E_GLHMC_VFPDINV_PMPDIDX_MASK
- I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT
- I40E_GLHMC_VFPDINV_PMSDIDX_MASK
- I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT
- I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK
- I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT
- I40E_GLHMC_VFPEARPBASE
- I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK
- I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT
- I40E_GLHMC_VFPEARPBASE_MAX_INDEX
- I40E_GLHMC_VFPEARPCNT
- I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK
- I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT
- I40E_GLHMC_VFPEARPCNT_MAX_INDEX
- I40E_GLHMC_VFPECQBASE
- I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK
- I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT
- I40E_GLHMC_VFPECQBASE_MAX_INDEX
- I40E_GLHMC_VFPECQCNT
- I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK
- I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT
- I40E_GLHMC_VFPECQCNT_MAX_INDEX
- I40E_GLHMC_VFPEHTCNT
- I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK
- I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT
- I40E_GLHMC_VFPEHTCNT_MAX_INDEX
- I40E_GLHMC_VFPEHTEBASE
- I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK
- I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT
- I40E_GLHMC_VFPEHTEBASE_MAX_INDEX
- I40E_GLHMC_VFPEMRBASE
- I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK
- I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT
- I40E_GLHMC_VFPEMRBASE_MAX_INDEX
- I40E_GLHMC_VFPEMRCNT
- I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK
- I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT
- I40E_GLHMC_VFPEMRCNT_MAX_INDEX
- I40E_GLHMC_VFPEPBLBASE
- I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK
- I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT
- I40E_GLHMC_VFPEPBLBASE_MAX_INDEX
- I40E_GLHMC_VFPEPBLCNT
- I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK
- I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT
- I40E_GLHMC_VFPEPBLCNT_MAX_INDEX
- I40E_GLHMC_VFPEQ1BASE
- I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK
- I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT
- I40E_GLHMC_VFPEQ1BASE_MAX_INDEX
- I40E_GLHMC_VFPEQ1CNT
- I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK
- I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT
- I40E_GLHMC_VFPEQ1CNT_MAX_INDEX
- I40E_GLHMC_VFPEQ1FLBASE
- I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK
- I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT
- I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX
- I40E_GLHMC_VFPEQPBASE
- I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK
- I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT
- I40E_GLHMC_VFPEQPBASE_MAX_INDEX
- I40E_GLHMC_VFPEQPCNT
- I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK
- I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT
- I40E_GLHMC_VFPEQPCNT_MAX_INDEX
- I40E_GLHMC_VFPESRQBASE
- I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK
- I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT
- I40E_GLHMC_VFPESRQBASE_MAX_INDEX
- I40E_GLHMC_VFPESRQCNT
- I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK
- I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT
- I40E_GLHMC_VFPESRQCNT_MAX_INDEX
- I40E_GLHMC_VFPETIMERBASE
- I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK
- I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT
- I40E_GLHMC_VFPETIMERBASE_MAX_INDEX
- I40E_GLHMC_VFPETIMERCNT
- I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK
- I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT
- I40E_GLHMC_VFPETIMERCNT_MAX_INDEX
- I40E_GLHMC_VFPEXFBASE
- I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK
- I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT
- I40E_GLHMC_VFPEXFBASE_MAX_INDEX
- I40E_GLHMC_VFPEXFCNT
- I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK
- I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT
- I40E_GLHMC_VFPEXFCNT_MAX_INDEX
- I40E_GLHMC_VFPEXFFLBASE
- I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK
- I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT
- I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX
- I40E_GLHMC_VFSDCMD
- I40E_GLHMC_VFSDCMD_MAX_INDEX
- I40E_GLHMC_VFSDCMD_PF_MASK
- I40E_GLHMC_VFSDCMD_PF_SHIFT
- I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK
- I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT
- I40E_GLHMC_VFSDCMD_PMSDIDX_MASK
- I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT
- I40E_GLHMC_VFSDCMD_PMSDWR_MASK
- I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT
- I40E_GLHMC_VFSDCMD_VF_MASK
- I40E_GLHMC_VFSDCMD_VF_SHIFT
- I40E_GLHMC_VFSDDATAHIGH
- I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX
- I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK
- I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT
- I40E_GLHMC_VFSDDATALOW
- I40E_GLHMC_VFSDDATALOW_MAX_INDEX
- I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK
- I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT
- I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK
- I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT
- I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK
- I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT
- I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK
- I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT
- I40E_GLHMC_VFSDPART
- I40E_GLHMC_VFSDPART_MAX_INDEX
- I40E_GLHMC_VFSDPART_PMSDBASE_MASK
- I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT
- I40E_GLHMC_VFSDPART_PMSDSIZE_MASK
- I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT
- I40E_GLINT_CTL
- I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK
- I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT
- I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK
- I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT
- I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK
- I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT
- I40E_GLLAN_RCTL_0
- I40E_GLLAN_RCTL_0_PXE_MODE_MASK
- I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT
- I40E_GLLAN_TSOMSK_F
- I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK
- I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT
- I40E_GLLAN_TSOMSK_L
- I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK
- I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT
- I40E_GLLAN_TSOMSK_M
- I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK
- I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT
- I40E_GLLAN_TXPRE_QDIS
- I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK
- I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT
- I40E_GLLAN_TXPRE_QDIS_MAX_INDEX
- I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK
- I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT
- I40E_GLLAN_TXPRE_QDIS_QINDX_MASK
- I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT
- I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK
- I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT
- I40E_GLNVM_ALTIMERS
- I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK
- I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT
- I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK
- I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT
- I40E_GLNVM_AL_REQ
- I40E_GLNVM_AL_REQ_CORER_MASK
- I40E_GLNVM_AL_REQ_CORER_SHIFT
- I40E_GLNVM_AL_REQ_GLOBR_MASK
- I40E_GLNVM_AL_REQ_GLOBR_SHIFT
- I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK
- I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT
- I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK
- I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT
- I40E_GLNVM_AL_REQ_PE_MASK
- I40E_GLNVM_AL_REQ_PE_SHIFT
- I40E_GLNVM_AL_REQ_POR_MASK
- I40E_GLNVM_AL_REQ_POR_SHIFT
- I40E_GLNVM_FLA
- I40E_GLNVM_FLASHID
- I40E_GLNVM_FLASHID_FLASHID_MASK
- I40E_GLNVM_FLASHID_FLASHID_SHIFT
- I40E_GLNVM_FLASHID_FLEEP_PERF_MASK
- I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT
- I40E_GLNVM_FLA_FL_BUSY_MASK
- I40E_GLNVM_FLA_FL_BUSY_SHIFT
- I40E_GLNVM_FLA_FL_CE_MASK
- I40E_GLNVM_FLA_FL_CE_SHIFT
- I40E_GLNVM_FLA_FL_DER_MASK
- I40E_GLNVM_FLA_FL_DER_SHIFT
- I40E_GLNVM_FLA_FL_GNT_MASK
- I40E_GLNVM_FLA_FL_GNT_SHIFT
- I40E_GLNVM_FLA_FL_REQ_MASK
- I40E_GLNVM_FLA_FL_REQ_SHIFT
- I40E_GLNVM_FLA_FL_SADDR_MASK
- I40E_GLNVM_FLA_FL_SADDR_SHIFT
- I40E_GLNVM_FLA_FL_SCK_MASK
- I40E_GLNVM_FLA_FL_SCK_SHIFT
- I40E_GLNVM_FLA_FL_SI_MASK
- I40E_GLNVM_FLA_FL_SI_SHIFT
- I40E_GLNVM_FLA_FL_SO_MASK
- I40E_GLNVM_FLA_FL_SO_SHIFT
- I40E_GLNVM_FLA_LOCKED_MASK
- I40E_GLNVM_FLA_LOCKED_SHIFT
- I40E_GLNVM_GENS
- I40E_GLNVM_GENS_ALT_PRST_MASK
- I40E_GLNVM_GENS_ALT_PRST_SHIFT
- I40E_GLNVM_GENS_BANK1VAL_MASK
- I40E_GLNVM_GENS_BANK1VAL_SHIFT
- I40E_GLNVM_GENS_FL_AUTO_RD_MASK
- I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT
- I40E_GLNVM_GENS_NVM_PRES_MASK
- I40E_GLNVM_GENS_NVM_PRES_SHIFT
- I40E_GLNVM_GENS_SR_SIZE_MASK
- I40E_GLNVM_GENS_SR_SIZE_SHIFT
- I40E_GLNVM_PROTCSR
- I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK
- I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT
- I40E_GLNVM_PROTCSR_MAX_INDEX
- I40E_GLNVM_SRCTL
- I40E_GLNVM_SRCTL_ADDR_MASK
- I40E_GLNVM_SRCTL_ADDR_SHIFT
- I40E_GLNVM_SRCTL_DONE_MASK
- I40E_GLNVM_SRCTL_DONE_SHIFT
- I40E_GLNVM_SRCTL_SRBUSY_MASK
- I40E_GLNVM_SRCTL_SRBUSY_SHIFT
- I40E_GLNVM_SRCTL_START_MASK
- I40E_GLNVM_SRCTL_START_SHIFT
- I40E_GLNVM_SRCTL_WRITE_MASK
- I40E_GLNVM_SRCTL_WRITE_SHIFT
- I40E_GLNVM_SRDATA
- I40E_GLNVM_SRDATA_RDDATA_MASK
- I40E_GLNVM_SRDATA_RDDATA_SHIFT
- I40E_GLNVM_SRDATA_WRDATA_MASK
- I40E_GLNVM_SRDATA_WRDATA_SHIFT
- I40E_GLNVM_ULD
- I40E_GLNVM_ULD_CONF_CORE_DONE_MASK
- I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_EMP_DONE_MASK
- I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK
- I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_LCB_DONE_MASK
- I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK
- I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK
- I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK
- I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK
- I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK
- I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT
- I40E_GLNVM_ULD_CONF_POR_DONE_MASK
- I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT
- I40E_GLNVM_ULD_CORER_DONE_MASK
- I40E_GLNVM_ULD_CORER_DONE_SHIFT
- I40E_GLNVM_ULD_GLOBR_DONE_MASK
- I40E_GLNVM_ULD_GLOBR_DONE_SHIFT
- I40E_GLNVM_ULD_PCIER_DONE_1_MASK
- I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT
- I40E_GLNVM_ULD_PCIER_DONE_2_MASK
- I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT
- I40E_GLNVM_ULD_PCIER_DONE_MASK
- I40E_GLNVM_ULD_PCIER_DONE_SHIFT
- I40E_GLNVM_ULD_PE_DONE_MASK
- I40E_GLNVM_ULD_PE_DONE_SHIFT
- I40E_GLNVM_ULD_POR_DONE_1_MASK
- I40E_GLNVM_ULD_POR_DONE_1_SHIFT
- I40E_GLNVM_ULD_POR_DONE_MASK
- I40E_GLNVM_ULD_POR_DONE_SHIFT
- I40E_GLNVM_ULT
- I40E_GLNVM_ULT_CONF_CORE_AE_MASK
- I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT
- I40E_GLNVM_ULT_CONF_EMP_AE_MASK
- I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT
- I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK
- I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT
- I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK
- I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT
- I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK
- I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT
- I40E_GLNVM_ULT_CONF_PCIR_AE_MASK
- I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT
- I40E_GLNVM_ULT_CONF_POR_AE_MASK
- I40E_GLNVM_ULT_CONF_POR_AE_SHIFT
- I40E_GLNVM_ULT_RESERVED_1_MASK
- I40E_GLNVM_ULT_RESERVED_1_SHIFT
- I40E_GLNVM_ULT_RESERVED_2_MASK
- I40E_GLNVM_ULT_RESERVED_2_SHIFT
- I40E_GLNVM_ULT_RESERVED_3_MASK
- I40E_GLNVM_ULT_RESERVED_3_SHIFT
- I40E_GLNVM_ULT_RESERVED_4_MASK
- I40E_GLNVM_ULT_RESERVED_4_SHIFT
- I40E_GLOBAL_STATS_LEN
- I40E_GLPBLOC_CACHESIZE
- I40E_GLPBLOC_CACHESIZE_SETS_MASK
- I40E_GLPBLOC_CACHESIZE_SETS_SHIFT
- I40E_GLPBLOC_CACHESIZE_WAYS_MASK
- I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT
- I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK
- I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLPCI_BYTCTH
- I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK
- I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT
- I40E_GLPCI_BYTCTL
- I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK
- I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT
- I40E_GLPCI_CAPCTRL
- I40E_GLPCI_CAPCTRL_VPD_EN_MASK
- I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT
- I40E_GLPCI_CAPSUP
- I40E_GLPCI_CAPSUP_ACS_EN_MASK
- I40E_GLPCI_CAPSUP_ACS_EN_SHIFT
- I40E_GLPCI_CAPSUP_ARI_EN_MASK
- I40E_GLPCI_CAPSUP_ARI_EN_SHIFT
- I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK
- I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT
- I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK
- I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT
- I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK
- I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT
- I40E_GLPCI_CAPSUP_IDO_EN_MASK
- I40E_GLPCI_CAPSUP_IDO_EN_SHIFT
- I40E_GLPCI_CAPSUP_IOV_EN_MASK
- I40E_GLPCI_CAPSUP_IOV_EN_SHIFT
- I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK
- I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT
- I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK
- I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT
- I40E_GLPCI_CAPSUP_LTR_EN_MASK
- I40E_GLPCI_CAPSUP_LTR_EN_SHIFT
- I40E_GLPCI_CAPSUP_MSI_MASK_MASK
- I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT
- I40E_GLPCI_CAPSUP_PCIE_VER_MASK
- I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT
- I40E_GLPCI_CAPSUP_SEC_EN_MASK
- I40E_GLPCI_CAPSUP_SEC_EN_SHIFT
- I40E_GLPCI_CAPSUP_TPH_EN_MASK
- I40E_GLPCI_CAPSUP_TPH_EN_SHIFT
- I40E_GLPCI_CAPSUP_WAKUP_EN_MASK
- I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT
- I40E_GLPCI_CNF
- I40E_GLPCI_CNF2
- I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK
- I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT
- I40E_GLPCI_CNF2_MSI_X_PF_N_MASK
- I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT
- I40E_GLPCI_CNF2_MSI_X_VF_N_MASK
- I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT
- I40E_GLPCI_CNF2_RO_DIS_MASK
- I40E_GLPCI_CNF2_RO_DIS_SHIFT
- I40E_GLPCI_CNF_FLEX10_MASK
- I40E_GLPCI_CNF_FLEX10_SHIFT
- I40E_GLPCI_CNF_WAKE_PIN_EN_MASK
- I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT
- I40E_GLPCI_CUR_CLNT_COMMON
- I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK
- I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK
- I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT
- I40E_GLPCI_CUR_CLNT_PIPEMON
- I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK
- I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_MNG_ALWD
- I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK
- I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_MNG_RSVD
- I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK
- I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_PMAT_ALWD
- I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK
- I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_PMAT_RSVD
- I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK
- I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_RLAN_ALWD
- I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK
- I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_RLAN_RSVD
- I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK
- I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_RXPE_ALWD
- I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK
- I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_RXPE_RSVD
- I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK
- I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_TDPU_ALWD
- I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK
- I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_TDPU_RSVD
- I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK
- I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_TLAN_ALWD
- I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK
- I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_TLAN_RSVD
- I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK
- I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_TXPE_ALWD
- I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK
- I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT
- I40E_GLPCI_CUR_TXPE_RSVD
- I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK
- I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK
- I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT
- I40E_GLPCI_CUR_WATMK_CLNT_COMMON
- I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK
- I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT
- I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK
- I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT
- I40E_GLPCI_DREVID
- I40E_GLPCI_DREVID_DEFAULT_REVID_MASK
- I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT
- I40E_GLPCI_GSCL_1
- I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK
- I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT
- I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK
- I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT
- I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK
- I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT
- I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK
- I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT
- I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK
- I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT
- I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK
- I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT
- I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK
- I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT
- I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK
- I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT
- I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK
- I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT
- I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK
- I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT
- I40E_GLPCI_GSCL_2
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK
- I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT
- I40E_GLPCI_GSCL_5_8
- I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK
- I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT
- I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK
- I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT
- I40E_GLPCI_GSCL_5_8_MAX_INDEX
- I40E_GLPCI_GSCN_0_3
- I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK
- I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT
- I40E_GLPCI_GSCN_0_3_MAX_INDEX
- I40E_GLPCI_LBARCTRL
- I40E_GLPCI_LBARCTRL_BAR32_MASK
- I40E_GLPCI_LBARCTRL_BAR32_SHIFT
- I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK
- I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT
- I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK
- I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT
- I40E_GLPCI_LBARCTRL_FL_SIZE_MASK
- I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT
- I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK
- I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT
- I40E_GLPCI_LBARCTRL_PREFBAR_MASK
- I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT
- I40E_GLPCI_LBARCTRL_RSVD_10_MASK
- I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT
- I40E_GLPCI_LBARCTRL_RSVD_4_MASK
- I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT
- I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK
- I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT
- I40E_GLPCI_LINKCAP
- I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK
- I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT
- I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK
- I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT
- I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK
- I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT
- I40E_GLPCI_NPQ_CFG
- I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK
- I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT
- I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK
- I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT
- I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK
- I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT
- I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK
- I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT
- I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK
- I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT
- I40E_GLPCI_PCIERR
- I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK
- I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT
- I40E_GLPCI_PKTCT
- I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK
- I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT
- I40E_GLPCI_PMSUP
- I40E_GLPCI_PMSUP_ASPM_SUP_MASK
- I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT
- I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK
- I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT
- I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK
- I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT
- I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK
- I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT
- I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK
- I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT
- I40E_GLPCI_PMSUP_OBFF_SUP_MASK
- I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT
- I40E_GLPCI_PMSUP_SLOT_CLK_MASK
- I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT
- I40E_GLPCI_PM_MUX_NPQ
- I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK
- I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT
- I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK
- I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT
- I40E_GLPCI_PM_MUX_PFB
- I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK
- I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT
- I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK
- I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT
- I40E_GLPCI_PQ_MAX_USED_SPC
- I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK
- I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT
- I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK
- I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT
- I40E_GLPCI_PWRDATA
- I40E_GLPCI_PWRDATA_COMM_POWER_MASK
- I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT
- I40E_GLPCI_PWRDATA_D0_POWER_MASK
- I40E_GLPCI_PWRDATA_D0_POWER_SHIFT
- I40E_GLPCI_PWRDATA_D3_POWER_MASK
- I40E_GLPCI_PWRDATA_D3_POWER_SHIFT
- I40E_GLPCI_PWRDATA_DATA_SCALE_MASK
- I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT
- I40E_GLPCI_REVID
- I40E_GLPCI_REVID_NVM_REVID_MASK
- I40E_GLPCI_REVID_NVM_REVID_SHIFT
- I40E_GLPCI_SERH
- I40E_GLPCI_SERH_SER_NUM_H_MASK
- I40E_GLPCI_SERH_SER_NUM_H_SHIFT
- I40E_GLPCI_SERL
- I40E_GLPCI_SERL_SER_NUM_L_MASK
- I40E_GLPCI_SERL_SER_NUM_L_SHIFT
- I40E_GLPCI_SPARE_BITS_0
- I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK
- I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT
- I40E_GLPCI_SPARE_BITS_1
- I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK
- I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT
- I40E_GLPCI_SUBVENID
- I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK
- I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT
- I40E_GLPCI_UPADD
- I40E_GLPCI_UPADD_ADDRESS_MASK
- I40E_GLPCI_UPADD_ADDRESS_SHIFT
- I40E_GLPCI_VENDORID
- I40E_GLPCI_VENDORID_VENDORID_MASK
- I40E_GLPCI_VENDORID_VENDORID_SHIFT
- I40E_GLPCI_VFSUP
- I40E_GLPCI_VFSUP_VF_PREFETCH_MASK
- I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT
- I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK
- I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT
- I40E_GLPCI_WATMK_CLNT_PIPEMON
- I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK
- I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_MNG_ALWD
- I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_PMAT_ALWD
- I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_RLAN_ALWD
- I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_RXPE_ALWD
- I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_TLAN_ALWD
- I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_TPDU_ALWD
- I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT
- I40E_GLPCI_WATMK_TXPE_ALWD
- I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK
- I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT
- I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK
- I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT
- I40E_GLPDOC_CACHESIZE
- I40E_GLPDOC_CACHESIZE_SETS_MASK
- I40E_GLPDOC_CACHESIZE_SETS_SHIFT
- I40E_GLPDOC_CACHESIZE_WAYS_MASK
- I40E_GLPDOC_CACHESIZE_WAYS_SHIFT
- I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK
- I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLPEOC_CACHESIZE
- I40E_GLPEOC_CACHESIZE_SETS_MASK
- I40E_GLPEOC_CACHESIZE_SETS_SHIFT
- I40E_GLPEOC_CACHESIZE_WAYS_MASK
- I40E_GLPEOC_CACHESIZE_WAYS_SHIFT
- I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK
- I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT
- I40E_GLPES_PFIP4RXDISCARD
- I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK
- I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT
- I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX
- I40E_GLPES_PFIP4RXFRAGSHI
- I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK
- I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT
- I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX
- I40E_GLPES_PFIP4RXFRAGSLO
- I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK
- I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT
- I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX
- I40E_GLPES_PFIP4RXMCOCTSHI
- I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK
- I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT
- I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP4RXMCOCTSLO
- I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK
- I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT
- I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP4RXMCPKTSHI
- I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK
- I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT
- I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP4RXMCPKTSLO
- I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK
- I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT
- I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP4RXOCTSHI
- I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK
- I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT
- I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP4RXOCTSLO
- I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK
- I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT
- I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP4RXPKTSHI
- I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK
- I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT
- I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP4RXPKTSLO
- I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK
- I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT
- I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP4RXTRUNC
- I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK
- I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT
- I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX
- I40E_GLPES_PFIP4TXFRAGSHI
- I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK
- I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT
- I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX
- I40E_GLPES_PFIP4TXFRAGSLO
- I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK
- I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT
- I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX
- I40E_GLPES_PFIP4TXMCOCTSHI
- I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK
- I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT
- I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP4TXMCOCTSLO
- I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK
- I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT
- I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP4TXMCPKTSHI
- I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK
- I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT
- I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP4TXMCPKTSLO
- I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK
- I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT
- I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP4TXNOROUTE
- I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK
- I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT
- I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX
- I40E_GLPES_PFIP4TXOCTSHI
- I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK
- I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT
- I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP4TXOCTSLO
- I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK
- I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT
- I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP4TXPKTSHI
- I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK
- I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT
- I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP4TXPKTSLO
- I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK
- I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT
- I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXDISCARD
- I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK
- I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT
- I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX
- I40E_GLPES_PFIP6RXFRAGSHI
- I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK
- I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT
- I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX
- I40E_GLPES_PFIP6RXFRAGSLO
- I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK
- I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT
- I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXMCOCTSHI
- I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK
- I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT
- I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP6RXMCOCTSLO
- I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK
- I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT
- I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXMCPKTSHI
- I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK
- I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT
- I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP6RXMCPKTSLO
- I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK
- I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT
- I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXOCTSHI
- I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK
- I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT
- I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP6RXOCTSLO
- I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK
- I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT
- I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXPKTSHI
- I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK
- I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT
- I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP6RXPKTSLO
- I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK
- I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT
- I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP6RXTRUNC
- I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK
- I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT
- I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX
- I40E_GLPES_PFIP6TXFRAGSHI
- I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK
- I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT
- I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX
- I40E_GLPES_PFIP6TXFRAGSLO
- I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK
- I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT
- I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX
- I40E_GLPES_PFIP6TXMCOCTSHI
- I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK
- I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT
- I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP6TXMCOCTSLO
- I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK
- I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT
- I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP6TXMCPKTSHI
- I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK
- I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT
- I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP6TXMCPKTSLO
- I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK
- I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT
- I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX
- I40E_GLPES_PFIP6TXNOROUTE
- I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK
- I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT
- I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX
- I40E_GLPES_PFIP6TXOCTSHI
- I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK
- I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT
- I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX
- I40E_GLPES_PFIP6TXOCTSLO
- I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK
- I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT
- I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX
- I40E_GLPES_PFIP6TXPKTSHI
- I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK
- I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT
- I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX
- I40E_GLPES_PFIP6TXPKTSLO
- I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK
- I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT
- I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX
- I40E_GLPES_PFRDMARXRDSHI
- I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX
- I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK
- I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT
- I40E_GLPES_PFRDMARXRDSLO
- I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX
- I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK
- I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT
- I40E_GLPES_PFRDMARXSNDSHI
- I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX
- I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK
- I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT
- I40E_GLPES_PFRDMARXSNDSLO
- I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX
- I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK
- I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT
- I40E_GLPES_PFRDMARXWRSHI
- I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX
- I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK
- I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT
- I40E_GLPES_PFRDMARXWRSLO
- I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX
- I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK
- I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT
- I40E_GLPES_PFRDMATXRDSHI
- I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX
- I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK
- I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT
- I40E_GLPES_PFRDMATXRDSLO
- I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX
- I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK
- I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT
- I40E_GLPES_PFRDMATXSNDSHI
- I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX
- I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK
- I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT
- I40E_GLPES_PFRDMATXSNDSLO
- I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX
- I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK
- I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT
- I40E_GLPES_PFRDMATXWRSHI
- I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX
- I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK
- I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT
- I40E_GLPES_PFRDMATXWRSLO
- I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX
- I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK
- I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT
- I40E_GLPES_PFRDMAVBNDHI
- I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX
- I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK
- I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT
- I40E_GLPES_PFRDMAVBNDLO
- I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX
- I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK
- I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT
- I40E_GLPES_PFRDMAVINVHI
- I40E_GLPES_PFRDMAVINVHI_MAX_INDEX
- I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK
- I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT
- I40E_GLPES_PFRDMAVINVLO
- I40E_GLPES_PFRDMAVINVLO_MAX_INDEX
- I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK
- I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT
- I40E_GLPES_PFRXVLANERR
- I40E_GLPES_PFRXVLANERR_MAX_INDEX
- I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK
- I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT
- I40E_GLPES_PFTCPRTXSEG
- I40E_GLPES_PFTCPRTXSEG_MAX_INDEX
- I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK
- I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT
- I40E_GLPES_PFTCPRXOPTERR
- I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX
- I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK
- I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT
- I40E_GLPES_PFTCPRXPROTOERR
- I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX
- I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK
- I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT
- I40E_GLPES_PFTCPRXSEGSHI
- I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX
- I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK
- I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT
- I40E_GLPES_PFTCPRXSEGSLO
- I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX
- I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK
- I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT
- I40E_GLPES_PFTCPTXSEGHI
- I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX
- I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK
- I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT
- I40E_GLPES_PFTCPTXSEGLO
- I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX
- I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK
- I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT
- I40E_GLPES_PFUDPRXPKTSHI
- I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX
- I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK
- I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT
- I40E_GLPES_PFUDPRXPKTSLO
- I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX
- I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK
- I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT
- I40E_GLPES_PFUDPTXPKTSHI
- I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX
- I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK
- I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT
- I40E_GLPES_PFUDPTXPKTSLO
- I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX
- I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK
- I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT
- I40E_GLPES_RDMARXMULTFPDUSHI
- I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK
- I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT
- I40E_GLPES_RDMARXMULTFPDUSLO
- I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK
- I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT
- I40E_GLPES_RDMARXOOODDPHI
- I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK
- I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT
- I40E_GLPES_RDMARXOOODDPLO
- I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK
- I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT
- I40E_GLPES_RDMARXOOONOMARK
- I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK
- I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT
- I40E_GLPES_RDMARXUNALIGN
- I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK
- I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT
- I40E_GLPES_TCPRXFOURHOLEHI
- I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK
- I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT
- I40E_GLPES_TCPRXFOURHOLELO
- I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK
- I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT
- I40E_GLPES_TCPRXONEHOLEHI
- I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK
- I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT
- I40E_GLPES_TCPRXONEHOLELO
- I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK
- I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT
- I40E_GLPES_TCPRXPUREACKHI
- I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK
- I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT
- I40E_GLPES_TCPRXPUREACKSLO
- I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK
- I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT
- I40E_GLPES_TCPRXTHREEHOLEHI
- I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK
- I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT
- I40E_GLPES_TCPRXTHREEHOLELO
- I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK
- I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT
- I40E_GLPES_TCPRXTWOHOLEHI
- I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK
- I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT
- I40E_GLPES_TCPRXTWOHOLELO
- I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK
- I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT
- I40E_GLPES_TCPTXRETRANSFASTHI
- I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK
- I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT
- I40E_GLPES_TCPTXRETRANSFASTLO
- I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK
- I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT
- I40E_GLPES_TCPTXTOUTSFASTHI
- I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK
- I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT
- I40E_GLPES_TCPTXTOUTSFASTLO
- I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK
- I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT
- I40E_GLPES_TCPTXTOUTSHI
- I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK
- I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT
- I40E_GLPES_TCPTXTOUTSLO
- I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK
- I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT
- I40E_GLPES_VFIP4RXDISCARD
- I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK
- I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT
- I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX
- I40E_GLPES_VFIP4RXFRAGSHI
- I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK
- I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT
- I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX
- I40E_GLPES_VFIP4RXFRAGSLO
- I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK
- I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT
- I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX
- I40E_GLPES_VFIP4RXMCOCTSHI
- I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK
- I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT
- I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP4RXMCOCTSLO
- I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK
- I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT
- I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP4RXMCPKTSHI
- I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK
- I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT
- I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP4RXMCPKTSLO
- I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK
- I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT
- I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP4RXOCTSHI
- I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK
- I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT
- I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP4RXOCTSLO
- I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK
- I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT
- I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP4RXPKTSHI
- I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK
- I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT
- I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP4RXPKTSLO
- I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK
- I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT
- I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP4RXTRUNC
- I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK
- I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT
- I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX
- I40E_GLPES_VFIP4TXFRAGSHI
- I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK
- I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT
- I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX
- I40E_GLPES_VFIP4TXFRAGSLO
- I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK
- I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT
- I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX
- I40E_GLPES_VFIP4TXMCOCTSHI
- I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK
- I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT
- I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP4TXMCOCTSLO
- I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK
- I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT
- I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP4TXMCPKTSHI
- I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK
- I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT
- I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP4TXMCPKTSLO
- I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK
- I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT
- I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP4TXNOROUTE
- I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK
- I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT
- I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX
- I40E_GLPES_VFIP4TXOCTSHI
- I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK
- I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT
- I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP4TXOCTSLO
- I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK
- I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT
- I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP4TXPKTSHI
- I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK
- I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT
- I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP4TXPKTSLO
- I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK
- I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT
- I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXDISCARD
- I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK
- I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT
- I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX
- I40E_GLPES_VFIP6RXFRAGSHI
- I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK
- I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT
- I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX
- I40E_GLPES_VFIP6RXFRAGSLO
- I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK
- I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT
- I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXMCOCTSHI
- I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK
- I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT
- I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP6RXMCOCTSLO
- I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK
- I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT
- I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXMCPKTSHI
- I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK
- I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT
- I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP6RXMCPKTSLO
- I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK
- I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT
- I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXOCTSHI
- I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK
- I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT
- I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP6RXOCTSLO
- I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK
- I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT
- I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXPKTSHI
- I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK
- I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT
- I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP6RXPKTSLO
- I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK
- I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT
- I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP6RXTRUNC
- I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK
- I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT
- I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX
- I40E_GLPES_VFIP6TXFRAGSHI
- I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK
- I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT
- I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX
- I40E_GLPES_VFIP6TXFRAGSLO
- I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK
- I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT
- I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX
- I40E_GLPES_VFIP6TXMCOCTSHI
- I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK
- I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT
- I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP6TXMCOCTSLO
- I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK
- I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT
- I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP6TXMCPKTSHI
- I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK
- I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT
- I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP6TXMCPKTSLO
- I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK
- I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT
- I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX
- I40E_GLPES_VFIP6TXNOROUTE
- I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK
- I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT
- I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX
- I40E_GLPES_VFIP6TXOCTSHI
- I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK
- I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT
- I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX
- I40E_GLPES_VFIP6TXOCTSLO
- I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK
- I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT
- I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX
- I40E_GLPES_VFIP6TXPKTSHI
- I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK
- I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT
- I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX
- I40E_GLPES_VFIP6TXPKTSLO
- I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK
- I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT
- I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX
- I40E_GLPES_VFRDMARXRDSHI
- I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX
- I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK
- I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT
- I40E_GLPES_VFRDMARXRDSLO
- I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX
- I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK
- I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT
- I40E_GLPES_VFRDMARXSNDSHI
- I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX
- I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK
- I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT
- I40E_GLPES_VFRDMARXSNDSLO
- I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX
- I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK
- I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT
- I40E_GLPES_VFRDMARXWRSHI
- I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX
- I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK
- I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT
- I40E_GLPES_VFRDMARXWRSLO
- I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX
- I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK
- I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT
- I40E_GLPES_VFRDMATXRDSHI
- I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX
- I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK
- I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT
- I40E_GLPES_VFRDMATXRDSLO
- I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX
- I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK
- I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT
- I40E_GLPES_VFRDMATXSNDSHI
- I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX
- I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK
- I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT
- I40E_GLPES_VFRDMATXSNDSLO
- I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX
- I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK
- I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT
- I40E_GLPES_VFRDMATXWRSHI
- I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX
- I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK
- I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT
- I40E_GLPES_VFRDMATXWRSLO
- I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX
- I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK
- I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT
- I40E_GLPES_VFRDMAVBNDHI
- I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX
- I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK
- I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT
- I40E_GLPES_VFRDMAVBNDLO
- I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX
- I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK
- I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT
- I40E_GLPES_VFRDMAVINVHI
- I40E_GLPES_VFRDMAVINVHI_MAX_INDEX
- I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK
- I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT
- I40E_GLPES_VFRDMAVINVLO
- I40E_GLPES_VFRDMAVINVLO_MAX_INDEX
- I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK
- I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT
- I40E_GLPES_VFRXVLANERR
- I40E_GLPES_VFRXVLANERR_MAX_INDEX
- I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK
- I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT
- I40E_GLPES_VFTCPRTXSEG
- I40E_GLPES_VFTCPRTXSEG_MAX_INDEX
- I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK
- I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT
- I40E_GLPES_VFTCPRXOPTERR
- I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX
- I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK
- I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT
- I40E_GLPES_VFTCPRXPROTOERR
- I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX
- I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK
- I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT
- I40E_GLPES_VFTCPRXSEGSHI
- I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX
- I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK
- I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT
- I40E_GLPES_VFTCPRXSEGSLO
- I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX
- I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK
- I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT
- I40E_GLPES_VFTCPTXSEGHI
- I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX
- I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK
- I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT
- I40E_GLPES_VFTCPTXSEGLO
- I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX
- I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK
- I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT
- I40E_GLPES_VFUDPRXPKTSHI
- I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX
- I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK
- I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT
- I40E_GLPES_VFUDPRXPKTSLO
- I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX
- I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK
- I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT
- I40E_GLPES_VFUDPTXPKTSHI
- I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX
- I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK
- I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT
- I40E_GLPES_VFUDPTXPKTSLO
- I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX
- I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK
- I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT
- I40E_GLPE_CPUSTATUS0
- I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK
- I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT
- I40E_GLPE_CPUSTATUS1
- I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK
- I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT
- I40E_GLPE_CPUSTATUS2
- I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK
- I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT
- I40E_GLPE_CPUTRIG0
- I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK
- I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT
- I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK
- I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT
- I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK
- I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT
- I40E_GLPE_DUAL40_RUPM
- I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK
- I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT
- I40E_GLPE_FWLDSTATUS
- I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK
- I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT
- I40E_GLPE_FWLDSTATUS_DONE_MASK
- I40E_GLPE_FWLDSTATUS_DONE_SHIFT
- I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK
- I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT
- I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK
- I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT
- I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK
- I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT
- I40E_GLPE_PFAEQEDROPCNT
- I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK
- I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT
- I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX
- I40E_GLPE_PFCEQEDROPCNT
- I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK
- I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT
- I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX
- I40E_GLPE_PFCQEDROPCNT
- I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK
- I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT
- I40E_GLPE_PFCQEDROPCNT_MAX_INDEX
- I40E_GLPE_RUPM_CQPPOOL
- I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK
- I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT
- I40E_GLPE_RUPM_FLRPOOL
- I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK
- I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT
- I40E_GLPE_RUPM_GCTL
- I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK
- I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT
- I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK
- I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT
- I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK
- I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT
- I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK
- I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT
- I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK
- I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT
- I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK
- I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT
- I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK
- I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT
- I40E_GLPE_RUPM_PTXPOOL
- I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK
- I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT
- I40E_GLPE_RUPM_PUSHPOOL
- I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK
- I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT
- I40E_GLPE_RUPM_TXHOST_EN
- I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK
- I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT
- I40E_GLPE_VFAEQEDROPCNT
- I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK
- I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT
- I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX
- I40E_GLPE_VFCEQEDROPCNT
- I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK
- I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT
- I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX
- I40E_GLPE_VFCQEDROPCNT
- I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK
- I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT
- I40E_GLPE_VFCQEDROPCNT_MAX_INDEX
- I40E_GLPE_VFFLMOBJCTRL
- I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX
- I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK
- I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT
- I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK
- I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT
- I40E_GLPE_VFFLMQ1ALLOCERR
- I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK
- I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT
- I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX
- I40E_GLPE_VFFLMXMITALLOCERR
- I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK
- I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT
- I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX
- I40E_GLPE_VFUDACTRL
- I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK
- I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT
- I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK
- I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT
- I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK
- I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT
- I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK
- I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT
- I40E_GLPE_VFUDACTRL_MAX_INDEX
- I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK
- I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT
- I40E_GLPE_VFUDAUCFBQPN
- I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX
- I40E_GLPE_VFUDAUCFBQPN_QPN_MASK
- I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT
- I40E_GLPE_VFUDAUCFBQPN_VALID_MASK
- I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT
- I40E_GLPM_WUMC
- I40E_GLPM_WUMC_MNG_WU_PF_MASK
- I40E_GLPM_WUMC_MNG_WU_PF_SHIFT
- I40E_GLPM_WUMC_NOTCO_MASK
- I40E_GLPM_WUMC_NOTCO_SHIFT
- I40E_GLPM_WUMC_RESERVED_4_MASK
- I40E_GLPM_WUMC_RESERVED_4_SHIFT
- I40E_GLPM_WUMC_ROL_MODE_MASK
- I40E_GLPM_WUMC_ROL_MODE_SHIFT
- I40E_GLPM_WUMC_SRST_PIN_VAL_MASK
- I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT
- I40E_GLPRT_BPRCH
- I40E_GLPRT_BPRCH_BPRCH_MASK
- I40E_GLPRT_BPRCH_BPRCH_SHIFT
- I40E_GLPRT_BPRCH_MAX_INDEX
- I40E_GLPRT_BPRCL
- I40E_GLPRT_BPRCL_BPRCL_MASK
- I40E_GLPRT_BPRCL_BPRCL_SHIFT
- I40E_GLPRT_BPRCL_MAX_INDEX
- I40E_GLPRT_BPTCH
- I40E_GLPRT_BPTCH_BPTCH_MASK
- I40E_GLPRT_BPTCH_BPTCH_SHIFT
- I40E_GLPRT_BPTCH_MAX_INDEX
- I40E_GLPRT_BPTCL
- I40E_GLPRT_BPTCL_BPTCL_MASK
- I40E_GLPRT_BPTCL_BPTCL_SHIFT
- I40E_GLPRT_BPTCL_MAX_INDEX
- I40E_GLPRT_CRCERRS
- I40E_GLPRT_CRCERRS_CRCERRS_MASK
- I40E_GLPRT_CRCERRS_CRCERRS_SHIFT
- I40E_GLPRT_CRCERRS_MAX_INDEX
- I40E_GLPRT_GORCH
- I40E_GLPRT_GORCH_GORCH_MASK
- I40E_GLPRT_GORCH_GORCH_SHIFT
- I40E_GLPRT_GORCH_MAX_INDEX
- I40E_GLPRT_GORCL
- I40E_GLPRT_GORCL_GORCL_MASK
- I40E_GLPRT_GORCL_GORCL_SHIFT
- I40E_GLPRT_GORCL_MAX_INDEX
- I40E_GLPRT_GOTCH
- I40E_GLPRT_GOTCH_GOTCH_MASK
- I40E_GLPRT_GOTCH_GOTCH_SHIFT
- I40E_GLPRT_GOTCH_MAX_INDEX
- I40E_GLPRT_GOTCL
- I40E_GLPRT_GOTCL_GOTCL_MASK
- I40E_GLPRT_GOTCL_GOTCL_SHIFT
- I40E_GLPRT_GOTCL_MAX_INDEX
- I40E_GLPRT_ILLERRC
- I40E_GLPRT_ILLERRC_ILLERRC_MASK
- I40E_GLPRT_ILLERRC_ILLERRC_SHIFT
- I40E_GLPRT_ILLERRC_MAX_INDEX
- I40E_GLPRT_LDPC
- I40E_GLPRT_LDPC_LDPC_MASK
- I40E_GLPRT_LDPC_LDPC_SHIFT
- I40E_GLPRT_LDPC_MAX_INDEX
- I40E_GLPRT_LXOFFRXC
- I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK
- I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT
- I40E_GLPRT_LXOFFRXC_MAX_INDEX
- I40E_GLPRT_LXOFFTXC
- I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK
- I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT
- I40E_GLPRT_LXOFFTXC_MAX_INDEX
- I40E_GLPRT_LXONRXC
- I40E_GLPRT_LXONRXC_LXONRXCNT_MASK
- I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT
- I40E_GLPRT_LXONRXC_MAX_INDEX
- I40E_GLPRT_LXONTXC
- I40E_GLPRT_LXONTXC_LXONTXC_MASK
- I40E_GLPRT_LXONTXC_LXONTXC_SHIFT
- I40E_GLPRT_LXONTXC_MAX_INDEX
- I40E_GLPRT_MLFC
- I40E_GLPRT_MLFC_MAX_INDEX
- I40E_GLPRT_MLFC_MLFC_MASK
- I40E_GLPRT_MLFC_MLFC_SHIFT
- I40E_GLPRT_MPRCH
- I40E_GLPRT_MPRCH_MAX_INDEX
- I40E_GLPRT_MPRCH_MPRCH_MASK
- I40E_GLPRT_MPRCH_MPRCH_SHIFT
- I40E_GLPRT_MPRCL
- I40E_GLPRT_MPRCL_MAX_INDEX
- I40E_GLPRT_MPRCL_MPRCL_MASK
- I40E_GLPRT_MPRCL_MPRCL_SHIFT
- I40E_GLPRT_MPTCH
- I40E_GLPRT_MPTCH_MAX_INDEX
- I40E_GLPRT_MPTCH_MPTCH_MASK
- I40E_GLPRT_MPTCH_MPTCH_SHIFT
- I40E_GLPRT_MPTCL
- I40E_GLPRT_MPTCL_MAX_INDEX
- I40E_GLPRT_MPTCL_MPTCL_MASK
- I40E_GLPRT_MPTCL_MPTCL_SHIFT
- I40E_GLPRT_MRFC
- I40E_GLPRT_MRFC_MAX_INDEX
- I40E_GLPRT_MRFC_MRFC_MASK
- I40E_GLPRT_MRFC_MRFC_SHIFT
- I40E_GLPRT_PRC1023H
- I40E_GLPRT_PRC1023H_MAX_INDEX
- I40E_GLPRT_PRC1023H_PRC1023H_MASK
- I40E_GLPRT_PRC1023H_PRC1023H_SHIFT
- I40E_GLPRT_PRC1023L
- I40E_GLPRT_PRC1023L_MAX_INDEX
- I40E_GLPRT_PRC1023L_PRC1023L_MASK
- I40E_GLPRT_PRC1023L_PRC1023L_SHIFT
- I40E_GLPRT_PRC127H
- I40E_GLPRT_PRC127H_MAX_INDEX
- I40E_GLPRT_PRC127H_PRC127H_MASK
- I40E_GLPRT_PRC127H_PRC127H_SHIFT
- I40E_GLPRT_PRC127L
- I40E_GLPRT_PRC127L_MAX_INDEX
- I40E_GLPRT_PRC127L_PRC127L_MASK
- I40E_GLPRT_PRC127L_PRC127L_SHIFT
- I40E_GLPRT_PRC1522H
- I40E_GLPRT_PRC1522H_MAX_INDEX
- I40E_GLPRT_PRC1522H_PRC1522H_MASK
- I40E_GLPRT_PRC1522H_PRC1522H_SHIFT
- I40E_GLPRT_PRC1522L
- I40E_GLPRT_PRC1522L_MAX_INDEX
- I40E_GLPRT_PRC1522L_PRC1522L_MASK
- I40E_GLPRT_PRC1522L_PRC1522L_SHIFT
- I40E_GLPRT_PRC255H
- I40E_GLPRT_PRC255H_MAX_INDEX
- I40E_GLPRT_PRC255H_PRTPRC255H_MASK
- I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT
- I40E_GLPRT_PRC255L
- I40E_GLPRT_PRC255L_MAX_INDEX
- I40E_GLPRT_PRC255L_PRC255L_MASK
- I40E_GLPRT_PRC255L_PRC255L_SHIFT
- I40E_GLPRT_PRC511H
- I40E_GLPRT_PRC511H_MAX_INDEX
- I40E_GLPRT_PRC511H_PRC511H_MASK
- I40E_GLPRT_PRC511H_PRC511H_SHIFT
- I40E_GLPRT_PRC511L
- I40E_GLPRT_PRC511L_MAX_INDEX
- I40E_GLPRT_PRC511L_PRC511L_MASK
- I40E_GLPRT_PRC511L_PRC511L_SHIFT
- I40E_GLPRT_PRC64H
- I40E_GLPRT_PRC64H_MAX_INDEX
- I40E_GLPRT_PRC64H_PRC64H_MASK
- I40E_GLPRT_PRC64H_PRC64H_SHIFT
- I40E_GLPRT_PRC64L
- I40E_GLPRT_PRC64L_MAX_INDEX
- I40E_GLPRT_PRC64L_PRC64L_MASK
- I40E_GLPRT_PRC64L_PRC64L_SHIFT
- I40E_GLPRT_PRC9522H
- I40E_GLPRT_PRC9522H_MAX_INDEX
- I40E_GLPRT_PRC9522H_PRC1522H_MASK
- I40E_GLPRT_PRC9522H_PRC1522H_SHIFT
- I40E_GLPRT_PRC9522L
- I40E_GLPRT_PRC9522L_MAX_INDEX
- I40E_GLPRT_PRC9522L_PRC1522L_MASK
- I40E_GLPRT_PRC9522L_PRC1522L_SHIFT
- I40E_GLPRT_PTC1023H
- I40E_GLPRT_PTC1023H_MAX_INDEX
- I40E_GLPRT_PTC1023H_PTC1023H_MASK
- I40E_GLPRT_PTC1023H_PTC1023H_SHIFT
- I40E_GLPRT_PTC1023L
- I40E_GLPRT_PTC1023L_MAX_INDEX
- I40E_GLPRT_PTC1023L_PTC1023L_MASK
- I40E_GLPRT_PTC1023L_PTC1023L_SHIFT
- I40E_GLPRT_PTC127H
- I40E_GLPRT_PTC127H_MAX_INDEX
- I40E_GLPRT_PTC127H_PTC127H_MASK
- I40E_GLPRT_PTC127H_PTC127H_SHIFT
- I40E_GLPRT_PTC127L
- I40E_GLPRT_PTC127L_MAX_INDEX
- I40E_GLPRT_PTC127L_PTC127L_MASK
- I40E_GLPRT_PTC127L_PTC127L_SHIFT
- I40E_GLPRT_PTC1522H
- I40E_GLPRT_PTC1522H_MAX_INDEX
- I40E_GLPRT_PTC1522H_PTC1522H_MASK
- I40E_GLPRT_PTC1522H_PTC1522H_SHIFT
- I40E_GLPRT_PTC1522L
- I40E_GLPRT_PTC1522L_MAX_INDEX
- I40E_GLPRT_PTC1522L_PTC1522L_MASK
- I40E_GLPRT_PTC1522L_PTC1522L_SHIFT
- I40E_GLPRT_PTC255H
- I40E_GLPRT_PTC255H_MAX_INDEX
- I40E_GLPRT_PTC255H_PTC255H_MASK
- I40E_GLPRT_PTC255H_PTC255H_SHIFT
- I40E_GLPRT_PTC255L
- I40E_GLPRT_PTC255L_MAX_INDEX
- I40E_GLPRT_PTC255L_PTC255L_MASK
- I40E_GLPRT_PTC255L_PTC255L_SHIFT
- I40E_GLPRT_PTC511H
- I40E_GLPRT_PTC511H_MAX_INDEX
- I40E_GLPRT_PTC511H_PTC511H_MASK
- I40E_GLPRT_PTC511H_PTC511H_SHIFT
- I40E_GLPRT_PTC511L
- I40E_GLPRT_PTC511L_MAX_INDEX
- I40E_GLPRT_PTC511L_PTC511L_MASK
- I40E_GLPRT_PTC511L_PTC511L_SHIFT
- I40E_GLPRT_PTC64H
- I40E_GLPRT_PTC64H_MAX_INDEX
- I40E_GLPRT_PTC64H_PTC64H_MASK
- I40E_GLPRT_PTC64H_PTC64H_SHIFT
- I40E_GLPRT_PTC64L
- I40E_GLPRT_PTC64L_MAX_INDEX
- I40E_GLPRT_PTC64L_PTC64L_MASK
- I40E_GLPRT_PTC64L_PTC64L_SHIFT
- I40E_GLPRT_PTC9522H
- I40E_GLPRT_PTC9522H_MAX_INDEX
- I40E_GLPRT_PTC9522H_PTC9522H_MASK
- I40E_GLPRT_PTC9522H_PTC9522H_SHIFT
- I40E_GLPRT_PTC9522L
- I40E_GLPRT_PTC9522L_MAX_INDEX
- I40E_GLPRT_PTC9522L_PTC9522L_MASK
- I40E_GLPRT_PTC9522L_PTC9522L_SHIFT
- I40E_GLPRT_PXOFFRXC
- I40E_GLPRT_PXOFFRXC_MAX_INDEX
- I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK
- I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT
- I40E_GLPRT_PXOFFTXC
- I40E_GLPRT_PXOFFTXC_MAX_INDEX
- I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK
- I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT
- I40E_GLPRT_PXONRXC
- I40E_GLPRT_PXONRXC_MAX_INDEX
- I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK
- I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT
- I40E_GLPRT_PXONTXC
- I40E_GLPRT_PXONTXC_MAX_INDEX
- I40E_GLPRT_PXONTXC_PRPXONTXC_MASK
- I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT
- I40E_GLPRT_RDPC
- I40E_GLPRT_RDPC_MAX_INDEX
- I40E_GLPRT_RDPC_RDPC_MASK
- I40E_GLPRT_RDPC_RDPC_SHIFT
- I40E_GLPRT_RFC
- I40E_GLPRT_RFC_MAX_INDEX
- I40E_GLPRT_RFC_RFC_MASK
- I40E_GLPRT_RFC_RFC_SHIFT
- I40E_GLPRT_RJC
- I40E_GLPRT_RJC_MAX_INDEX
- I40E_GLPRT_RJC_RJC_MASK
- I40E_GLPRT_RJC_RJC_SHIFT
- I40E_GLPRT_RLEC
- I40E_GLPRT_RLEC_MAX_INDEX
- I40E_GLPRT_RLEC_RLEC_MASK
- I40E_GLPRT_RLEC_RLEC_SHIFT
- I40E_GLPRT_ROC
- I40E_GLPRT_ROC_MAX_INDEX
- I40E_GLPRT_ROC_ROC_MASK
- I40E_GLPRT_ROC_ROC_SHIFT
- I40E_GLPRT_RUC
- I40E_GLPRT_RUC_MAX_INDEX
- I40E_GLPRT_RUC_RUC_MASK
- I40E_GLPRT_RUC_RUC_SHIFT
- I40E_GLPRT_RUPP
- I40E_GLPRT_RUPP_MAX_INDEX
- I40E_GLPRT_RUPP_RUPP_MASK
- I40E_GLPRT_RUPP_RUPP_SHIFT
- I40E_GLPRT_RXON2OFFCNT
- I40E_GLPRT_RXON2OFFCNT_MAX_INDEX
- I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK
- I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT
- I40E_GLPRT_TDOLD
- I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK
- I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT
- I40E_GLPRT_TDOLD_MAX_INDEX
- I40E_GLPRT_UPRCH
- I40E_GLPRT_UPRCH_MAX_INDEX
- I40E_GLPRT_UPRCH_UPRCH_MASK
- I40E_GLPRT_UPRCH_UPRCH_SHIFT
- I40E_GLPRT_UPRCL
- I40E_GLPRT_UPRCL_MAX_INDEX
- I40E_GLPRT_UPRCL_UPRCL_MASK
- I40E_GLPRT_UPRCL_UPRCL_SHIFT
- I40E_GLPRT_UPTCH
- I40E_GLPRT_UPTCH_MAX_INDEX
- I40E_GLPRT_UPTCH_UPTCH_MASK
- I40E_GLPRT_UPTCH_UPTCH_SHIFT
- I40E_GLPRT_UPTCL
- I40E_GLPRT_UPTCL_MAX_INDEX
- I40E_GLPRT_UPTCL_VUPTCH_MASK
- I40E_GLPRT_UPTCL_VUPTCH_SHIFT
- I40E_GLQF_APBVT
- I40E_GLQF_APBVT_APBVT_MASK
- I40E_GLQF_APBVT_APBVT_SHIFT
- I40E_GLQF_APBVT_MAX_INDEX
- I40E_GLQF_CTL
- I40E_GLQF_CTL_FDBEST_MASK
- I40E_GLQF_CTL_FDBEST_SHIFT
- I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK
- I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT
- I40E_GLQF_CTL_HTOEP_FCOE_MASK
- I40E_GLQF_CTL_HTOEP_FCOE_SHIFT
- I40E_GLQF_CTL_HTOEP_MASK
- I40E_GLQF_CTL_HTOEP_SHIFT
- I40E_GLQF_CTL_IGNORE_IP_MASK
- I40E_GLQF_CTL_IGNORE_IP_SHIFT
- I40E_GLQF_CTL_INVALPRIO_MASK
- I40E_GLQF_CTL_INVALPRIO_SHIFT
- I40E_GLQF_CTL_MAXFCBLEN_MASK
- I40E_GLQF_CTL_MAXFCBLEN_SHIFT
- I40E_GLQF_CTL_MAXFDBLEN_MASK
- I40E_GLQF_CTL_MAXFDBLEN_SHIFT
- I40E_GLQF_CTL_MAXPEBLEN_MASK
- I40E_GLQF_CTL_MAXPEBLEN_SHIFT
- I40E_GLQF_CTL_PCNT_ALLOC_MASK
- I40E_GLQF_CTL_PCNT_ALLOC_SHIFT
- I40E_GLQF_CTL_PROGPRIO_MASK
- I40E_GLQF_CTL_PROGPRIO_SHIFT
- I40E_GLQF_CTL_RSVD_MASK
- I40E_GLQF_CTL_RSVD_SHIFT
- I40E_GLQF_FDCNT_0
- I40E_GLQF_FDCNT_0_BESTCNT_MASK
- I40E_GLQF_FDCNT_0_BESTCNT_SHIFT
- I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK
- I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT
- I40E_GLQF_FDEVICTENA
- I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK
- I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT
- I40E_GLQF_FDEVICTENA_MAX_INDEX
- I40E_GLQF_FDEVICTFLAG
- I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK
- I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT
- I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK
- I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT
- I40E_GLQF_FD_MSK
- I40E_GLQF_FD_MSK_MASK_MASK
- I40E_GLQF_FD_MSK_MASK_SHIFT
- I40E_GLQF_FD_MSK_MAX_INDEX
- I40E_GLQF_FD_MSK_OFFSET_MASK
- I40E_GLQF_FD_MSK_OFFSET_SHIFT
- I40E_GLQF_FD_PCTYPES
- I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK
- I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT
- I40E_GLQF_FD_PCTYPES_MAX_INDEX
- I40E_GLQF_HASH_INSET
- I40E_GLQF_HASH_INSET_INSET_MASK
- I40E_GLQF_HASH_INSET_INSET_SHIFT
- I40E_GLQF_HASH_INSET_MAX_INDEX
- I40E_GLQF_HASH_MSK
- I40E_GLQF_HASH_MSK_MASK_MASK
- I40E_GLQF_HASH_MSK_MASK_SHIFT
- I40E_GLQF_HASH_MSK_MAX_INDEX
- I40E_GLQF_HASH_MSK_OFFSET_MASK
- I40E_GLQF_HASH_MSK_OFFSET_SHIFT
- I40E_GLQF_HKEY
- I40E_GLQF_HKEY_KEY_0_MASK
- I40E_GLQF_HKEY_KEY_0_SHIFT
- I40E_GLQF_HKEY_KEY_1_MASK
- I40E_GLQF_HKEY_KEY_1_SHIFT
- I40E_GLQF_HKEY_KEY_2_MASK
- I40E_GLQF_HKEY_KEY_2_SHIFT
- I40E_GLQF_HKEY_KEY_3_MASK
- I40E_GLQF_HKEY_KEY_3_SHIFT
- I40E_GLQF_HKEY_MAX_INDEX
- I40E_GLQF_HSYM
- I40E_GLQF_HSYM_MAX_INDEX
- I40E_GLQF_HSYM_SYMH_ENA_MASK
- I40E_GLQF_HSYM_SYMH_ENA_SHIFT
- I40E_GLQF_ORT
- I40E_GLQF_ORT_FIELD_CNT_MASK
- I40E_GLQF_ORT_FIELD_CNT_SHIFT
- I40E_GLQF_ORT_FLX_PAYLOAD_MASK
- I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT
- I40E_GLQF_ORT_MAX_INDEX
- I40E_GLQF_ORT_PIT_INDX_MASK
- I40E_GLQF_ORT_PIT_INDX_SHIFT
- I40E_GLQF_PCNT
- I40E_GLQF_PCNT_MAX_INDEX
- I40E_GLQF_PCNT_PCNT_MASK
- I40E_GLQF_PCNT_PCNT_SHIFT
- I40E_GLQF_PIT
- I40E_GLQF_PIT_DEST_OFF_MASK
- I40E_GLQF_PIT_DEST_OFF_SHIFT
- I40E_GLQF_PIT_FSIZE_MASK
- I40E_GLQF_PIT_FSIZE_SHIFT
- I40E_GLQF_PIT_MAX_INDEX
- I40E_GLQF_PIT_SOURCE_OFF_MASK
- I40E_GLQF_PIT_SOURCE_OFF_SHIFT
- I40E_GLQF_SWAP
- I40E_GLQF_SWAP_FLEN0_MASK
- I40E_GLQF_SWAP_FLEN0_SHIFT
- I40E_GLQF_SWAP_FLEN1_MASK
- I40E_GLQF_SWAP_FLEN1_SHIFT
- I40E_GLQF_SWAP_MAX_INDEX
- I40E_GLQF_SWAP_OFF0_SRC0_MASK
- I40E_GLQF_SWAP_OFF0_SRC0_SHIFT
- I40E_GLQF_SWAP_OFF0_SRC1_MASK
- I40E_GLQF_SWAP_OFF0_SRC1_SHIFT
- I40E_GLQF_SWAP_OFF1_SRC0_MASK
- I40E_GLQF_SWAP_OFF1_SRC0_SHIFT
- I40E_GLQF_SWAP_OFF1_SRC1_MASK
- I40E_GLQF_SWAP_OFF1_SRC1_SHIFT
- I40E_GLRPB_DPSS
- I40E_GLRPB_DPSS_DPS_TCN_MASK
- I40E_GLRPB_DPSS_DPS_TCN_SHIFT
- I40E_GLRPB_GHW
- I40E_GLRPB_GHW_GHW_MASK
- I40E_GLRPB_GHW_GHW_SHIFT
- I40E_GLRPB_GLW
- I40E_GLRPB_GLW_GLW_MASK
- I40E_GLRPB_GLW_GLW_SHIFT
- I40E_GLRPB_PHW
- I40E_GLRPB_PHW_PHW_MASK
- I40E_GLRPB_PHW_PHW_SHIFT
- I40E_GLRPB_PLW
- I40E_GLRPB_PLW_PLW_MASK
- I40E_GLRPB_PLW_PLW_SHIFT
- I40E_GLSW_BPRCH
- I40E_GLSW_BPRCH_BPRCH_MASK
- I40E_GLSW_BPRCH_BPRCH_SHIFT
- I40E_GLSW_BPRCH_MAX_INDEX
- I40E_GLSW_BPRCL
- I40E_GLSW_BPRCL_BPRCL_MASK
- I40E_GLSW_BPRCL_BPRCL_SHIFT
- I40E_GLSW_BPRCL_MAX_INDEX
- I40E_GLSW_BPTCH
- I40E_GLSW_BPTCH_BPTCH_MASK
- I40E_GLSW_BPTCH_BPTCH_SHIFT
- I40E_GLSW_BPTCH_MAX_INDEX
- I40E_GLSW_BPTCL
- I40E_GLSW_BPTCL_BPTCL_MASK
- I40E_GLSW_BPTCL_BPTCL_SHIFT
- I40E_GLSW_BPTCL_MAX_INDEX
- I40E_GLSW_GORCH
- I40E_GLSW_GORCH_GORCH_MASK
- I40E_GLSW_GORCH_GORCH_SHIFT
- I40E_GLSW_GORCH_MAX_INDEX
- I40E_GLSW_GORCL
- I40E_GLSW_GORCL_GORCL_MASK
- I40E_GLSW_GORCL_GORCL_SHIFT
- I40E_GLSW_GORCL_MAX_INDEX
- I40E_GLSW_GOTCH
- I40E_GLSW_GOTCH_GOTCH_MASK
- I40E_GLSW_GOTCH_GOTCH_SHIFT
- I40E_GLSW_GOTCH_MAX_INDEX
- I40E_GLSW_GOTCL
- I40E_GLSW_GOTCL_GOTCL_MASK
- I40E_GLSW_GOTCL_GOTCL_SHIFT
- I40E_GLSW_GOTCL_MAX_INDEX
- I40E_GLSW_MPRCH
- I40E_GLSW_MPRCH_MAX_INDEX
- I40E_GLSW_MPRCH_MPRCH_MASK
- I40E_GLSW_MPRCH_MPRCH_SHIFT
- I40E_GLSW_MPRCL
- I40E_GLSW_MPRCL_MAX_INDEX
- I40E_GLSW_MPRCL_MPRCL_MASK
- I40E_GLSW_MPRCL_MPRCL_SHIFT
- I40E_GLSW_MPTCH
- I40E_GLSW_MPTCH_MAX_INDEX
- I40E_GLSW_MPTCH_MPTCH_MASK
- I40E_GLSW_MPTCH_MPTCH_SHIFT
- I40E_GLSW_MPTCL
- I40E_GLSW_MPTCL_MAX_INDEX
- I40E_GLSW_MPTCL_MPTCL_MASK
- I40E_GLSW_MPTCL_MPTCL_SHIFT
- I40E_GLSW_RUPP
- I40E_GLSW_RUPP_MAX_INDEX
- I40E_GLSW_RUPP_RUPP_MASK
- I40E_GLSW_RUPP_RUPP_SHIFT
- I40E_GLSW_TDPC
- I40E_GLSW_TDPC_MAX_INDEX
- I40E_GLSW_TDPC_TDPC_MASK
- I40E_GLSW_TDPC_TDPC_SHIFT
- I40E_GLSW_UPRCH
- I40E_GLSW_UPRCH_MAX_INDEX
- I40E_GLSW_UPRCH_UPRCH_MASK
- I40E_GLSW_UPRCH_UPRCH_SHIFT
- I40E_GLSW_UPRCL
- I40E_GLSW_UPRCL_MAX_INDEX
- I40E_GLSW_UPRCL_UPRCL_MASK
- I40E_GLSW_UPRCL_UPRCL_SHIFT
- I40E_GLSW_UPTCH
- I40E_GLSW_UPTCH_MAX_INDEX
- I40E_GLSW_UPTCH_UPTCH_MASK
- I40E_GLSW_UPTCH_UPTCH_SHIFT
- I40E_GLSW_UPTCL
- I40E_GLSW_UPTCL_MAX_INDEX
- I40E_GLSW_UPTCL_UPTCL_MASK
- I40E_GLSW_UPTCL_UPTCL_SHIFT
- I40E_GLTPH_CTRL
- I40E_GLTPH_CTRL_DATA_PH_MASK
- I40E_GLTPH_CTRL_DATA_PH_SHIFT
- I40E_GLTPH_CTRL_DESC_PH_MASK
- I40E_GLTPH_CTRL_DESC_PH_SHIFT
- I40E_GLVEBTC_RBCH
- I40E_GLVEBTC_RBCH_MAX_INDEX
- I40E_GLVEBTC_RBCH_TCBCH_MASK
- I40E_GLVEBTC_RBCH_TCBCH_SHIFT
- I40E_GLVEBTC_RBCL
- I40E_GLVEBTC_RBCL_MAX_INDEX
- I40E_GLVEBTC_RBCL_TCBCL_MASK
- I40E_GLVEBTC_RBCL_TCBCL_SHIFT
- I40E_GLVEBTC_RPCH
- I40E_GLVEBTC_RPCH_MAX_INDEX
- I40E_GLVEBTC_RPCH_TCPCH_MASK
- I40E_GLVEBTC_RPCH_TCPCH_SHIFT
- I40E_GLVEBTC_RPCL
- I40E_GLVEBTC_RPCL_MAX_INDEX
- I40E_GLVEBTC_RPCL_TCPCL_MASK
- I40E_GLVEBTC_RPCL_TCPCL_SHIFT
- I40E_GLVEBTC_TBCH
- I40E_GLVEBTC_TBCH_MAX_INDEX
- I40E_GLVEBTC_TBCH_TCBCH_MASK
- I40E_GLVEBTC_TBCH_TCBCH_SHIFT
- I40E_GLVEBTC_TBCL
- I40E_GLVEBTC_TBCL_MAX_INDEX
- I40E_GLVEBTC_TBCL_TCBCL_MASK
- I40E_GLVEBTC_TBCL_TCBCL_SHIFT
- I40E_GLVEBTC_TPCH
- I40E_GLVEBTC_TPCH_MAX_INDEX
- I40E_GLVEBTC_TPCH_TCPCH_MASK
- I40E_GLVEBTC_TPCH_TCPCH_SHIFT
- I40E_GLVEBTC_TPCL
- I40E_GLVEBTC_TPCL_MAX_INDEX
- I40E_GLVEBTC_TPCL_TCPCL_MASK
- I40E_GLVEBTC_TPCL_TCPCL_SHIFT
- I40E_GLVEBVL_BPCH
- I40E_GLVEBVL_BPCH_MAX_INDEX
- I40E_GLVEBVL_BPCH_VLBPCH_MASK
- I40E_GLVEBVL_BPCH_VLBPCH_SHIFT
- I40E_GLVEBVL_BPCL
- I40E_GLVEBVL_BPCL_MAX_INDEX
- I40E_GLVEBVL_BPCL_VLBPCL_MASK
- I40E_GLVEBVL_BPCL_VLBPCL_SHIFT
- I40E_GLVEBVL_GORCH
- I40E_GLVEBVL_GORCH_MAX_INDEX
- I40E_GLVEBVL_GORCH_VLBCH_MASK
- I40E_GLVEBVL_GORCH_VLBCH_SHIFT
- I40E_GLVEBVL_GORCL
- I40E_GLVEBVL_GORCL_MAX_INDEX
- I40E_GLVEBVL_GORCL_VLBCL_MASK
- I40E_GLVEBVL_GORCL_VLBCL_SHIFT
- I40E_GLVEBVL_GOTCH
- I40E_GLVEBVL_GOTCH_MAX_INDEX
- I40E_GLVEBVL_GOTCH_VLBCH_MASK
- I40E_GLVEBVL_GOTCH_VLBCH_SHIFT
- I40E_GLVEBVL_GOTCL
- I40E_GLVEBVL_GOTCL_MAX_INDEX
- I40E_GLVEBVL_GOTCL_VLBCL_MASK
- I40E_GLVEBVL_GOTCL_VLBCL_SHIFT
- I40E_GLVEBVL_MPCH
- I40E_GLVEBVL_MPCH_MAX_INDEX
- I40E_GLVEBVL_MPCH_VLMPCH_MASK
- I40E_GLVEBVL_MPCH_VLMPCH_SHIFT
- I40E_GLVEBVL_MPCL
- I40E_GLVEBVL_MPCL_MAX_INDEX
- I40E_GLVEBVL_MPCL_VLMPCL_MASK
- I40E_GLVEBVL_MPCL_VLMPCL_SHIFT
- I40E_GLVEBVL_UPCH
- I40E_GLVEBVL_UPCH_MAX_INDEX
- I40E_GLVEBVL_UPCH_VLUPCH_MASK
- I40E_GLVEBVL_UPCH_VLUPCH_SHIFT
- I40E_GLVEBVL_UPCL
- I40E_GLVEBVL_UPCL_MAX_INDEX
- I40E_GLVEBVL_UPCL_VLUPCL_MASK
- I40E_GLVEBVL_UPCL_VLUPCL_SHIFT
- I40E_GLVFGEN_TIMER
- I40E_GLVFGEN_TIMER_GTIME_MASK
- I40E_GLVFGEN_TIMER_GTIME_SHIFT
- I40E_GLV_BPRCH
- I40E_GLV_BPRCH_BPRCH_MASK
- I40E_GLV_BPRCH_BPRCH_SHIFT
- I40E_GLV_BPRCH_MAX_INDEX
- I40E_GLV_BPRCL
- I40E_GLV_BPRCL_BPRCL_MASK
- I40E_GLV_BPRCL_BPRCL_SHIFT
- I40E_GLV_BPRCL_MAX_INDEX
- I40E_GLV_BPTCH
- I40E_GLV_BPTCH_BPTCH_MASK
- I40E_GLV_BPTCH_BPTCH_SHIFT
- I40E_GLV_BPTCH_MAX_INDEX
- I40E_GLV_BPTCL
- I40E_GLV_BPTCL_BPTCL_MASK
- I40E_GLV_BPTCL_BPTCL_SHIFT
- I40E_GLV_BPTCL_MAX_INDEX
- I40E_GLV_GORCH
- I40E_GLV_GORCH_GORCH_MASK
- I40E_GLV_GORCH_GORCH_SHIFT
- I40E_GLV_GORCH_MAX_INDEX
- I40E_GLV_GORCL
- I40E_GLV_GORCL_GORCL_MASK
- I40E_GLV_GORCL_GORCL_SHIFT
- I40E_GLV_GORCL_MAX_INDEX
- I40E_GLV_GOTCH
- I40E_GLV_GOTCH_GOTCH_MASK
- I40E_GLV_GOTCH_GOTCH_SHIFT
- I40E_GLV_GOTCH_MAX_INDEX
- I40E_GLV_GOTCL
- I40E_GLV_GOTCL_GOTCL_MASK
- I40E_GLV_GOTCL_GOTCL_SHIFT
- I40E_GLV_GOTCL_MAX_INDEX
- I40E_GLV_MPRCH
- I40E_GLV_MPRCH_MAX_INDEX
- I40E_GLV_MPRCH_MPRCH_MASK
- I40E_GLV_MPRCH_MPRCH_SHIFT
- I40E_GLV_MPRCL
- I40E_GLV_MPRCL_MAX_INDEX
- I40E_GLV_MPRCL_MPRCL_MASK
- I40E_GLV_MPRCL_MPRCL_SHIFT
- I40E_GLV_MPTCH
- I40E_GLV_MPTCH_MAX_INDEX
- I40E_GLV_MPTCH_MPTCH_MASK
- I40E_GLV_MPTCH_MPTCH_SHIFT
- I40E_GLV_MPTCL
- I40E_GLV_MPTCL_MAX_INDEX
- I40E_GLV_MPTCL_MPTCL_MASK
- I40E_GLV_MPTCL_MPTCL_SHIFT
- I40E_GLV_RDPC
- I40E_GLV_RDPC_MAX_INDEX
- I40E_GLV_RDPC_RDPC_MASK
- I40E_GLV_RDPC_RDPC_SHIFT
- I40E_GLV_RUPP
- I40E_GLV_RUPP_MAX_INDEX
- I40E_GLV_RUPP_RUPP_MASK
- I40E_GLV_RUPP_RUPP_SHIFT
- I40E_GLV_TEPC
- I40E_GLV_TEPC_MAX_INDEX
- I40E_GLV_TEPC_TEPC_MASK
- I40E_GLV_TEPC_TEPC_SHIFT
- I40E_GLV_UPRCH
- I40E_GLV_UPRCH_MAX_INDEX
- I40E_GLV_UPRCH_UPRCH_MASK
- I40E_GLV_UPRCH_UPRCH_SHIFT
- I40E_GLV_UPRCL
- I40E_GLV_UPRCL_MAX_INDEX
- I40E_GLV_UPRCL_UPRCL_MASK
- I40E_GLV_UPRCL_UPRCL_SHIFT
- I40E_GLV_UPTCH
- I40E_GLV_UPTCH_GLVUPTCH_MASK
- I40E_GLV_UPTCH_GLVUPTCH_SHIFT
- I40E_GLV_UPTCH_MAX_INDEX
- I40E_GLV_UPTCL
- I40E_GLV_UPTCL_MAX_INDEX
- I40E_GLV_UPTCL_UPTCL_MASK
- I40E_GLV_UPTCL_UPTCL_SHIFT
- I40E_GL_ARQBAH
- I40E_GL_ARQBAH_ARQBAH_MASK
- I40E_GL_ARQBAH_ARQBAH_SHIFT
- I40E_GL_ARQBAL
- I40E_GL_ARQBAL_ARQBAL_MASK
- I40E_GL_ARQBAL_ARQBAL_SHIFT
- I40E_GL_ARQH
- I40E_GL_ARQH_ARQH_MASK
- I40E_GL_ARQH_ARQH_SHIFT
- I40E_GL_ARQT
- I40E_GL_ARQT_ARQT_MASK
- I40E_GL_ARQT_ARQT_SHIFT
- I40E_GL_ATQBAH
- I40E_GL_ATQBAH_ATQBAH_MASK
- I40E_GL_ATQBAH_ATQBAH_SHIFT
- I40E_GL_ATQBAL
- I40E_GL_ATQBAL_ATQBAL_MASK
- I40E_GL_ATQBAL_ATQBAL_SHIFT
- I40E_GL_ATQH
- I40E_GL_ATQH_ATQH_MASK
- I40E_GL_ATQH_ATQH_SHIFT
- I40E_GL_ATQLEN
- I40E_GL_ATQLEN_ATQCRIT_MASK
- I40E_GL_ATQLEN_ATQCRIT_SHIFT
- I40E_GL_ATQLEN_ATQENABLE_MASK
- I40E_GL_ATQLEN_ATQENABLE_SHIFT
- I40E_GL_ATQLEN_ATQLEN_MASK
- I40E_GL_ATQLEN_ATQLEN_SHIFT
- I40E_GL_ATQLEN_ATQOVFL_MASK
- I40E_GL_ATQLEN_ATQOVFL_SHIFT
- I40E_GL_ATQLEN_ATQVFE_MASK
- I40E_GL_ATQLEN_ATQVFE_SHIFT
- I40E_GL_ATQT
- I40E_GL_ATQT_ATQT_MASK
- I40E_GL_ATQT_ATQT_SHIFT
- I40E_GL_FCOECRC
- I40E_GL_FCOECRC_FCOECRC_MASK
- I40E_GL_FCOECRC_FCOECRC_SHIFT
- I40E_GL_FCOECRC_MAX_INDEX
- I40E_GL_FCOEDDPC
- I40E_GL_FCOEDDPC_FCOEDDPC_MASK
- I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT
- I40E_GL_FCOEDDPC_MAX_INDEX
- I40E_GL_FCOEDIFEC
- I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK
- I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT
- I40E_GL_FCOEDIFEC_MAX_INDEX
- I40E_GL_FCOEDIFTCL
- I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK
- I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT
- I40E_GL_FCOEDIFTCL_MAX_INDEX
- I40E_GL_FCOEDIXEC
- I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK
- I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT
- I40E_GL_FCOEDIXEC_MAX_INDEX
- I40E_GL_FCOEDIXVC
- I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK
- I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT
- I40E_GL_FCOEDIXVC_MAX_INDEX
- I40E_GL_FCOEDWRCH
- I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK
- I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT
- I40E_GL_FCOEDWRCH_MAX_INDEX
- I40E_GL_FCOEDWRCL
- I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK
- I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT
- I40E_GL_FCOEDWRCL_MAX_INDEX
- I40E_GL_FCOEDWTCH
- I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK
- I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT
- I40E_GL_FCOEDWTCH_MAX_INDEX
- I40E_GL_FCOEDWTCL
- I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK
- I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT
- I40E_GL_FCOEDWTCL_MAX_INDEX
- I40E_GL_FCOELAST
- I40E_GL_FCOELAST_FCOELAST_MASK
- I40E_GL_FCOELAST_FCOELAST_SHIFT
- I40E_GL_FCOELAST_MAX_INDEX
- I40E_GL_FCOEPRC
- I40E_GL_FCOEPRC_FCOEPRC_MASK
- I40E_GL_FCOEPRC_FCOEPRC_SHIFT
- I40E_GL_FCOEPRC_MAX_INDEX
- I40E_GL_FCOEPTC
- I40E_GL_FCOEPTC_FCOEPTC_MASK
- I40E_GL_FCOEPTC_FCOEPTC_SHIFT
- I40E_GL_FCOEPTC_MAX_INDEX
- I40E_GL_FCOERPDC
- I40E_GL_FCOERPDC_FCOERPDC_MASK
- I40E_GL_FCOERPDC_FCOERPDC_SHIFT
- I40E_GL_FCOERPDC_MAX_INDEX
- I40E_GL_FWRESETCNT
- I40E_GL_FWRESETCNT_FWRESETCNT_MASK
- I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT
- I40E_GL_FWSTS
- I40E_GL_FWSTS_FWRI_MASK
- I40E_GL_FWSTS_FWRI_SHIFT
- I40E_GL_FWSTS_FWROWD_MASK
- I40E_GL_FWSTS_FWROWD_SHIFT
- I40E_GL_FWSTS_FWS0B_MASK
- I40E_GL_FWSTS_FWS0B_SHIFT
- I40E_GL_FWSTS_FWS1B_MASK
- I40E_GL_FWSTS_FWS1B_SHIFT
- I40E_GL_GP_FUSE
- I40E_GL_GP_FUSE_GL_GP_FUSE_MASK
- I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT
- I40E_GL_GP_FUSE_MAX_INDEX
- I40E_GL_MDET_RX
- I40E_GL_MDET_RX_EVENT_MASK
- I40E_GL_MDET_RX_EVENT_SHIFT
- I40E_GL_MDET_RX_FUNCTION_MASK
- I40E_GL_MDET_RX_FUNCTION_SHIFT
- I40E_GL_MDET_RX_QUEUE_MASK
- I40E_GL_MDET_RX_QUEUE_SHIFT
- I40E_GL_MDET_RX_VALID_MASK
- I40E_GL_MDET_RX_VALID_SHIFT
- I40E_GL_MDET_TX
- I40E_GL_MDET_TX_EVENT_MASK
- I40E_GL_MDET_TX_EVENT_SHIFT
- I40E_GL_MDET_TX_PF_NUM_MASK
- I40E_GL_MDET_TX_PF_NUM_SHIFT
- I40E_GL_MDET_TX_QUEUE_MASK
- I40E_GL_MDET_TX_QUEUE_SHIFT
- I40E_GL_MDET_TX_VALID_MASK
- I40E_GL_MDET_TX_VALID_SHIFT
- I40E_GL_MDET_TX_VF_NUM_MASK
- I40E_GL_MDET_TX_VF_NUM_SHIFT
- I40E_GL_MNG_FWSM
- I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK
- I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT
- I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK
- I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT
- I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK
- I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT
- I40E_GL_MNG_FWSM_FW_MODES_MASK
- I40E_GL_MNG_FWSM_FW_MODES_SHIFT
- I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK
- I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT
- I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK
- I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT
- I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK
- I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT
- I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK
- I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT
- I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK
- I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT
- I40E_GL_MNG_FWSM_RESET_CNT_MASK
- I40E_GL_MNG_FWSM_RESET_CNT_SHIFT
- I40E_GL_MNG_HWARB_CTRL
- I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK
- I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT
- I40E_GL_MTG_FLU_MSK_H
- I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK
- I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT
- I40E_GL_PPRS_SPARE
- I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK
- I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT
- I40E_GL_PRIV_FLAGS_STR_LEN
- I40E_GL_PRS_FVBM
- I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK
- I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT
- I40E_GL_PRS_FVBM_MAX_INDEX
- I40E_GL_PRS_FVBM_MSK_ENA_MASK
- I40E_GL_PRS_FVBM_MSK_ENA_SHIFT
- I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK
- I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT
- I40E_GL_RDPU_CNTRL
- I40E_GL_RDPU_CNTRL_ECO_MASK
- I40E_GL_RDPU_CNTRL_ECO_SHIFT
- I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK
- I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT
- I40E_GL_RXERR1_L
- I40E_GL_RXERR1_L_FCOEDIFRC_MASK
- I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT
- I40E_GL_RXERR1_L_MAX_INDEX
- I40E_GL_RXERR2_L
- I40E_GL_RXERR2_L_FCOEDIXAC_MASK
- I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT
- I40E_GL_RXERR2_L_MAX_INDEX
- I40E_GL_SWR_DEF_ACT
- I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK
- I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT
- I40E_GL_SWR_DEF_ACT_EN
- I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK
- I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT
- I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX
- I40E_GL_SWR_DEF_ACT_MAX_INDEX
- I40E_GL_TLAN_SPARE
- I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK
- I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT
- I40E_GL_TUPM_SPARE
- I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK
- I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT
- I40E_GL_UFUSE
- I40E_GL_UFUSE_CLS_LOCKOUT_MASK
- I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT
- I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK
- I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT
- I40E_GL_UFUSE_NIC_ID_MASK
- I40E_GL_UFUSE_NIC_ID_SHIFT
- I40E_GL_UFUSE_SOC
- I40E_GL_UFUSE_SOC_NIC_ID_MASK
- I40E_GL_UFUSE_SOC_NIC_ID_SHIFT
- I40E_GL_UFUSE_SOC_PORT_MODE_MASK
- I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT
- I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK
- I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT
- I40E_GL_UFUSE_ULT_LOCKOUT_MASK
- I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT
- I40E_GL_VF_CTRL_RX
- I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK
- I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT
- I40E_GL_VF_CTRL_RX_MAX_INDEX
- I40E_GL_VF_CTRL_TX
- I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK
- I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT
- I40E_GL_VF_CTRL_TX_MAX_INDEX
- I40E_HASH_FILTER_BASE_SIZE
- I40E_HASH_FILTER_SIZE_128K
- I40E_HASH_FILTER_SIZE_16K
- I40E_HASH_FILTER_SIZE_1K
- I40E_HASH_FILTER_SIZE_1M
- I40E_HASH_FILTER_SIZE_256K
- I40E_HASH_FILTER_SIZE_2K
- I40E_HASH_FILTER_SIZE_32K
- I40E_HASH_FILTER_SIZE_4K
- I40E_HASH_FILTER_SIZE_512K
- I40E_HASH_FILTER_SIZE_64K
- I40E_HASH_FILTER_SIZE_8K
- I40E_HASH_FLTR
- I40E_HASH_LUT_SIZE_128
- I40E_HASH_LUT_SIZE_512
- I40E_HI_DWORD
- I40E_HKEY_ARRAY_SIZE
- I40E_HLUT_ARRAY_SIZE
- I40E_HMC_DIRECT_BP_SIZE
- I40E_HMC_FCOE_CTX
- I40E_HMC_FCOE_FILT
- I40E_HMC_INFO_SIGNATURE
- I40E_HMC_L2OBJ_BASE_ALIGNMENT
- I40E_HMC_LAN_FULL
- I40E_HMC_LAN_MAX
- I40E_HMC_LAN_OBJ_SZ_128
- I40E_HMC_LAN_OBJ_SZ_16
- I40E_HMC_LAN_OBJ_SZ_256
- I40E_HMC_LAN_OBJ_SZ_32
- I40E_HMC_LAN_OBJ_SZ_512
- I40E_HMC_LAN_OBJ_SZ_64
- I40E_HMC_LAN_OBJ_SZ_8
- I40E_HMC_LAN_RX
- I40E_HMC_LAN_TX
- I40E_HMC_MAX_BP_COUNT
- I40E_HMC_MODEL_DIRECT_ONLY
- I40E_HMC_MODEL_DIRECT_PREFERRED
- I40E_HMC_MODEL_PAGED_ONLY
- I40E_HMC_MODEL_UNKNOWN
- I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT
- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP
- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2
- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP
- I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP
- I40E_HMC_OBJ_SIZE_FCOE_CNTX
- I40E_HMC_OBJ_SIZE_FCOE_FILT
- I40E_HMC_OBJ_SIZE_RXQ
- I40E_HMC_OBJ_SIZE_TXQ
- I40E_HMC_PAGED_BP_SIZE
- I40E_HMC_PD_BP_BUF_ALIGNMENT
- I40E_HMC_PD_CNT_IN_SD
- I40E_HMC_PROFILE_DEFAULT
- I40E_HMC_PROFILE_EQUAL
- I40E_HMC_PROFILE_FAVOR_VF
- I40E_HMC_STORE
- I40E_HW_100M_SGMII_CAPABLE
- I40E_HW_128_QP_RSS_CAPABLE
- I40E_HW_ATR_EVICT_CAPABLE
- I40E_HW_CAP_MAX_GPIO
- I40E_HW_FLAG_802_1AD_CAPABLE
- I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE
- I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE
- I40E_HW_FLAG_DROP_MODE
- I40E_HW_FLAG_FW_LLDP_PERSISTENT
- I40E_HW_FLAG_FW_LLDP_STOPPABLE
- I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK
- I40E_HW_GENEVE_OFFLOAD_CAPABLE
- I40E_HW_HAVE_CRT_RETIMER
- I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE
- I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE
- I40E_HW_NO_DCB_SUPPORT
- I40E_HW_NO_PCI_LINK_CHECK
- I40E_HW_OUTER_UDP_CSUM_CAPABLE
- I40E_HW_PHY_CONTROLS_LEDS
- I40E_HW_PORT_ID_VALID
- I40E_HW_PTP_L4_CAPABLE
- I40E_HW_RESTART_AUTONEG
- I40E_HW_RSS_AQ_CAPABLE
- I40E_HW_STOP_FW_LLDP
- I40E_HW_USE_SET_LLDP_MIB
- I40E_HW_WB_ON_ITR_CAPABLE
- I40E_HW_WOL_MC_MAGIC_PKT_WAKE
- I40E_I2C_EEPROM_DEV_ADDR
- I40E_I2C_EEPROM_DEV_ADDR2
- I40E_IDX_ITR0
- I40E_IDX_ITR1
- I40E_IDX_ITR2
- I40E_IEEE_8021QAZ_OUI
- I40E_IEEE_APP_PRIO_MASK
- I40E_IEEE_APP_PRIO_SHIFT
- I40E_IEEE_APP_SEL_MASK
- I40E_IEEE_APP_SEL_SHIFT
- I40E_IEEE_ETS_CBS_MASK
- I40E_IEEE_ETS_CBS_SHIFT
- I40E_IEEE_ETS_MAXTC_MASK
- I40E_IEEE_ETS_MAXTC_SHIFT
- I40E_IEEE_ETS_PRIO_0_MASK
- I40E_IEEE_ETS_PRIO_0_SHIFT
- I40E_IEEE_ETS_PRIO_1_MASK
- I40E_IEEE_ETS_PRIO_1_SHIFT
- I40E_IEEE_ETS_WILLING_MASK
- I40E_IEEE_ETS_WILLING_SHIFT
- I40E_IEEE_PFC_CAP_MASK
- I40E_IEEE_PFC_CAP_SHIFT
- I40E_IEEE_PFC_MBC_MASK
- I40E_IEEE_PFC_MBC_SHIFT
- I40E_IEEE_PFC_WILLING_MASK
- I40E_IEEE_PFC_WILLING_SHIFT
- I40E_IEEE_SUBTYPE_APP_PRI
- I40E_IEEE_SUBTYPE_ETS_CFG
- I40E_IEEE_SUBTYPE_ETS_REC
- I40E_IEEE_SUBTYPE_PFC_CFG
- I40E_IEEE_TSA_ETS
- I40E_IEEE_TSA_STRICT
- I40E_INC_BP_REFCNT
- I40E_INC_PD_REFCNT
- I40E_INC_SD_REFCNT
- I40E_INTERRUPT_BEST_CASE
- I40E_INTERRUPT_LOWEST
- I40E_INTERRUPT_MEDIUM
- I40E_INTRL_62K
- I40E_INTRL_83K
- I40E_INTRL_8K
- I40E_INT_NAME_STR_LEN
- I40E_INVALIDATE_PF_HMC_PD
- I40E_IP_DUMMY_PACKET_LEN
- I40E_ITR_100K
- I40E_ITR_18K
- I40E_ITR_20K
- I40E_ITR_50K
- I40E_ITR_8K
- I40E_ITR_ADAPTIVE_BULK
- I40E_ITR_ADAPTIVE_LATENCY
- I40E_ITR_ADAPTIVE_MAX_USECS
- I40E_ITR_ADAPTIVE_MIN_INC
- I40E_ITR_ADAPTIVE_MIN_USECS
- I40E_ITR_DYNAMIC
- I40E_ITR_MASK
- I40E_ITR_NONE
- I40E_ITR_RX_DEF
- I40E_ITR_TX_DEF
- I40E_IWARP_IRQ_PILE_ID
- I40E_L3_DST_MASK
- I40E_L3_DST_SHIFT
- I40E_L3_GLQF_ORT_IDX
- I40E_L3_SRC_MASK
- I40E_L3_SRC_SHIFT
- I40E_L3_V6_DST_MASK
- I40E_L3_V6_DST_SHIFT
- I40E_L3_V6_SRC_MASK
- I40E_L3_V6_SRC_SHIFT
- I40E_L4_DST_MASK
- I40E_L4_DST_SHIFT
- I40E_L4_GLQF_ORT_IDX
- I40E_L4_SRC_MASK
- I40E_L4_SRC_SHIFT
- I40E_LAST_OFFSET
- I40E_LB_MODE_MAC_LOCAL
- I40E_LB_MODE_NONE
- I40E_LB_MODE_PHY_LOCAL
- I40E_LB_MODE_PHY_REMOTE
- I40E_LED0
- I40E_LINK_ACTIVITY
- I40E_LINK_SPEED_1000MB_SHIFT
- I40E_LINK_SPEED_100MB
- I40E_LINK_SPEED_100MB_SHIFT
- I40E_LINK_SPEED_10GB
- I40E_LINK_SPEED_10GB_SHIFT
- I40E_LINK_SPEED_1GB
- I40E_LINK_SPEED_20GB
- I40E_LINK_SPEED_20GB_SHIFT
- I40E_LINK_SPEED_25GB
- I40E_LINK_SPEED_25GB_SHIFT
- I40E_LINK_SPEED_2_5GB
- I40E_LINK_SPEED_2_5GB_SHIFT
- I40E_LINK_SPEED_40GB
- I40E_LINK_SPEED_40GB_SHIFT
- I40E_LINK_SPEED_5GB
- I40E_LINK_SPEED_5GB_SHIFT
- I40E_LINK_SPEED_UNKNOWN
- I40E_LLDPDU_SIZE
- I40E_LLDP_CURRENT_STATUS_X722_OFFSET
- I40E_LLDP_CURRENT_STATUS_XL710_OFFSET
- I40E_LLDP_TLV_LEN_MASK
- I40E_LLDP_TLV_LEN_SHIFT
- I40E_LLDP_TLV_OUI_MASK
- I40E_LLDP_TLV_OUI_SHIFT
- I40E_LLDP_TLV_SUBTYPE_MASK
- I40E_LLDP_TLV_SUBTYPE_SHIFT
- I40E_LLDP_TLV_TYPE_MASK
- I40E_LLDP_TLV_TYPE_SHIFT
- I40E_MAC_ACTIVITY
- I40E_MAC_GENERIC
- I40E_MAC_UNKNOWN
- I40E_MAC_VF
- I40E_MAC_VLAN_FLTR
- I40E_MAC_X722
- I40E_MAC_X722_VF
- I40E_MAC_XL710
- I40E_MASK
- I40E_MAX_AQ_BUF_SIZE
- I40E_MAX_BUFFER_TXD
- I40E_MAX_BW_INACTIVE_ACCUM
- I40E_MAX_CHAINED_RX_BUFFERS
- I40E_MAX_CSR_SPACE
- I40E_MAX_DATA_PER_TXD
- I40E_MAX_DATA_PER_TXD_ALIGNED
- I40E_MAX_DEBUG_OUT_BUFFER
- I40E_MAX_FD_PROGRAM_ERROR
- I40E_MAX_FLEX_SRC_OFFSET
- I40E_MAX_INTRL
- I40E_MAX_ITR
- I40E_MAX_MACVLANS
- I40E_MAX_NUM_DESCRIPTORS
- I40E_MAX_NVM_TIMEOUT
- I40E_MAX_PF_UDP_OFFLOAD_PORTS
- I40E_MAX_PHY_TIMEOUT
- I40E_MAX_PROFILE_NUM
- I40E_MAX_READ_REQ_SIZE
- I40E_MAX_RXBUFFER
- I40E_MAX_TRAFFIC_CLASS
- I40E_MAX_USER_PRIORITY
- I40E_MAX_VEB
- I40E_MAX_VF_COUNT
- I40E_MAX_VF_PROMISC_FLAGS
- I40E_MAX_VF_QUEUES
- I40E_MAX_VF_VSI
- I40E_MAX_VLANID
- I40E_MAX_VSI_QP
- I40E_MDIO_CLAUSE22_OPCODE_READ_MASK
- I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK
- I40E_MDIO_CLAUSE22_STCODE_MASK
- I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK
- I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK
- I40E_MDIO_CLAUSE45_OPCODE_READ_MASK
- I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK
- I40E_MDIO_CLAUSE45_STCODE_MASK
- I40E_MEDIA_TYPE_BACKPLANE
- I40E_MEDIA_TYPE_BASET
- I40E_MEDIA_TYPE_CX4
- I40E_MEDIA_TYPE_DA
- I40E_MEDIA_TYPE_FIBER
- I40E_MEDIA_TYPE_UNKNOWN
- I40E_MEDIA_TYPE_VIRTUAL
- I40E_MEM_INIT_DONE_STAT
- I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT
- I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK
- I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT
- I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722
- I40E_MINOR_VER_GET_LINK_INFO_X722
- I40E_MINOR_VER_GET_LINK_INFO_XL710
- I40E_MIN_DESC_PENDING
- I40E_MIN_FD_FLUSH_INTERVAL
- I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE
- I40E_MIN_ITR
- I40E_MIN_MACVLAN_VECTORS
- I40E_MIN_MSIX
- I40E_MIN_NUM_DESCRIPTORS
- I40E_MIN_TX_LEN
- I40E_MIN_VSI_ALLOC
- I40E_MISC_STATS_LEN
- I40E_MNGSB_DADD
- I40E_MNGSB_DADD_ADDR_MASK
- I40E_MNGSB_DADD_ADDR_SHIFT
- I40E_MNGSB_DCNT
- I40E_MNGSB_DCNT_BYTE_CNT_MASK
- I40E_MNGSB_DCNT_BYTE_CNT_SHIFT
- I40E_MNGSB_FDCRC
- I40E_MNGSB_FDCRC_CRC_RES_MASK
- I40E_MNGSB_FDCRC_CRC_RES_SHIFT
- I40E_MNGSB_FDCS
- I40E_MNGSB_FDCS_CRC_CONT_MASK
- I40E_MNGSB_FDCS_CRC_CONT_SHIFT
- I40E_MNGSB_FDCS_CRC_SEED_EN_MASK
- I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT
- I40E_MNGSB_FDCS_CRC_SEED_MASK
- I40E_MNGSB_FDCS_CRC_SEED_SHIFT
- I40E_MNGSB_FDCS_CRC_WR_INH_MASK
- I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT
- I40E_MNGSB_FDS
- I40E_MNGSB_FDS_LAST_BC_MASK
- I40E_MNGSB_FDS_LAST_BC_SHIFT
- I40E_MNGSB_FDS_START_BC_MASK
- I40E_MNGSB_FDS_START_BC_SHIFT
- I40E_MNGSB_MSGCTL
- I40E_MNGSB_MSGCTL_BARCLR_MASK
- I40E_MNGSB_MSGCTL_BARCLR_SHIFT
- I40E_MNGSB_MSGCTL_CMDV_MASK
- I40E_MNGSB_MSGCTL_CMDV_SHIFT
- I40E_MNGSB_MSGCTL_EXP_RDW_MASK
- I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT
- I40E_MNGSB_MSGCTL_HDR_DWS_MASK
- I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT
- I40E_MNGSB_MSGCTL_MSG_MODE_MASK
- I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT
- I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK
- I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT
- I40E_MNGSB_RDATA
- I40E_MNGSB_RDATA_DATA_MASK
- I40E_MNGSB_RDATA_DATA_SHIFT
- I40E_MNGSB_RHDR0
- I40E_MNGSB_RHDR0_DESTINATION_MASK
- I40E_MNGSB_RHDR0_DESTINATION_SHIFT
- I40E_MNGSB_RHDR0_EH_MASK
- I40E_MNGSB_RHDR0_EH_SHIFT
- I40E_MNGSB_RHDR0_OPCODE_MASK
- I40E_MNGSB_RHDR0_OPCODE_SHIFT
- I40E_MNGSB_RHDR0_RESPONSE_MASK
- I40E_MNGSB_RHDR0_RESPONSE_SHIFT
- I40E_MNGSB_RHDR0_SOURCE_MASK
- I40E_MNGSB_RHDR0_SOURCE_SHIFT
- I40E_MNGSB_RHDR0_TAG_MASK
- I40E_MNGSB_RHDR0_TAG_SHIFT
- I40E_MNGSB_RSPCTL
- I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK
- I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT
- I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK
- I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT
- I40E_MNGSB_RSPCTL_RSP_ERR_MASK
- I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT
- I40E_MNGSB_RSPCTL_RSP_MODE_MASK
- I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT
- I40E_MNGSB_WDATA
- I40E_MNGSB_WDATA_DATA_MASK
- I40E_MNGSB_WDATA_DATA_SHIFT
- I40E_MNGSB_WHDR0
- I40E_MNGSB_WHDR0_DEST_SEL_MASK
- I40E_MNGSB_WHDR0_DEST_SEL_SHIFT
- I40E_MNGSB_WHDR0_OPCODE_SEL_MASK
- I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT
- I40E_MNGSB_WHDR0_RAW_DEST_MASK
- I40E_MNGSB_WHDR0_RAW_DEST_SHIFT
- I40E_MNGSB_WHDR0_TAG_MASK
- I40E_MNGSB_WHDR0_TAG_SHIFT
- I40E_MNGSB_WHDR1
- I40E_MNGSB_WHDR1_ADDR_MASK
- I40E_MNGSB_WHDR1_ADDR_SHIFT
- I40E_MNGSB_WHDR2
- I40E_MNGSB_WHDR2_LENGTH_MASK
- I40E_MNGSB_WHDR2_LENGTH_SHIFT
- I40E_MNG_PROTOCOL_NCSI
- I40E_MNG_PROTOCOL_OEM_COMMANDS
- I40E_MNG_PROTOCOL_PLDM
- I40E_MODULE_QSFP_MAX_LEN
- I40E_MODULE_REVISION_ADDR
- I40E_MODULE_SFF_8472_COMP
- I40E_MODULE_SFF_8472_SWAP
- I40E_MODULE_SFF_ADDR_MODE
- I40E_MODULE_SFF_DDM_IMPLEMENTED
- I40E_MODULE_TYPE_1000BASE_CX
- I40E_MODULE_TYPE_1000BASE_LX
- I40E_MODULE_TYPE_1000BASE_SX
- I40E_MODULE_TYPE_1000BASE_T
- I40E_MODULE_TYPE_10G_BASE_ER
- I40E_MODULE_TYPE_10G_BASE_LR
- I40E_MODULE_TYPE_10G_BASE_LRM
- I40E_MODULE_TYPE_10G_BASE_SR
- I40E_MODULE_TYPE_40G_ACTIVE
- I40E_MODULE_TYPE_40G_CR4
- I40E_MODULE_TYPE_40G_LR4
- I40E_MODULE_TYPE_40G_SR4
- I40E_MODULE_TYPE_ADDR
- I40E_MODULE_TYPE_QSFP
- I40E_MODULE_TYPE_QSFP28
- I40E_MODULE_TYPE_QSFP_PLUS
- I40E_MODULE_TYPE_SFP
- I40E_MSIX_PBA
- I40E_MSIX_PBA_MAX_INDEX
- I40E_MSIX_PBA_PENBIT_MASK
- I40E_MSIX_PBA_PENBIT_SHIFT
- I40E_MSIX_TADD
- I40E_MSIX_TADD_MAX_INDEX
- I40E_MSIX_TADD_MSIXTADD10_MASK
- I40E_MSIX_TADD_MSIXTADD10_SHIFT
- I40E_MSIX_TADD_MSIXTADD_MASK
- I40E_MSIX_TADD_MSIXTADD_SHIFT
- I40E_MSIX_TMSG
- I40E_MSIX_TMSG_MAX_INDEX
- I40E_MSIX_TMSG_MSIXTMSG_MASK
- I40E_MSIX_TMSG_MSIXTMSG_SHIFT
- I40E_MSIX_TUADD
- I40E_MSIX_TUADD_MAX_INDEX
- I40E_MSIX_TUADD_MSIXTUADD_MASK
- I40E_MSIX_TUADD_MSIXTUADD_SHIFT
- I40E_MSIX_TVCTRL
- I40E_MSIX_TVCTRL_MASK_MASK
- I40E_MSIX_TVCTRL_MASK_SHIFT
- I40E_MSIX_TVCTRL_MAX_INDEX
- I40E_MS_TO_GTIME
- I40E_NETDEV_STAT
- I40E_NETDEV_STATS_LEN
- I40E_NOT_SUPPORTED
- I40E_NO_VEB
- I40E_NO_VSI
- I40E_NVMUPD_CSUM_CON
- I40E_NVMUPD_CSUM_LCB
- I40E_NVMUPD_CSUM_SA
- I40E_NVMUPD_EXEC_AQ
- I40E_NVMUPD_GET_AQ_EVENT
- I40E_NVMUPD_GET_AQ_RESULT
- I40E_NVMUPD_IFACE_TIMEOUT
- I40E_NVMUPD_INVALID
- I40E_NVMUPD_MAX_DATA
- I40E_NVMUPD_READ_CON
- I40E_NVMUPD_READ_LCB
- I40E_NVMUPD_READ_SA
- I40E_NVMUPD_READ_SNT
- I40E_NVMUPD_STATE_ERROR
- I40E_NVMUPD_STATE_INIT
- I40E_NVMUPD_STATE_INIT_WAIT
- I40E_NVMUPD_STATE_READING
- I40E_NVMUPD_STATE_WRITE_WAIT
- I40E_NVMUPD_STATE_WRITING
- I40E_NVMUPD_STATUS
- I40E_NVMUPD_WRITE_CON
- I40E_NVMUPD_WRITE_ERA
- I40E_NVMUPD_WRITE_LCB
- I40E_NVMUPD_WRITE_SA
- I40E_NVMUPD_WRITE_SNT
- I40E_NVM_ADAPT_MASK
- I40E_NVM_ADAPT_SHIFT
- I40E_NVM_AQE
- I40E_NVM_CON
- I40E_NVM_CSUM
- I40E_NVM_ERA
- I40E_NVM_EXEC
- I40E_NVM_IMAGE_TYPE_CLOUD
- I40E_NVM_IMAGE_TYPE_EVB
- I40E_NVM_IMAGE_TYPE_UDP_CLOUD
- I40E_NVM_INVALID_PTR_VAL
- I40E_NVM_INVALID_VAL
- I40E_NVM_LCB
- I40E_NVM_LLDP_CFG_PTR
- I40E_NVM_MGMT_SEC_REV_DISABLED
- I40E_NVM_MGMT_UPDATE_DISABLED
- I40E_NVM_MOD_PNT_MASK
- I40E_NVM_OEM_CAPABILITIES_MASK
- I40E_NVM_OEM_CAPABILITIES_OFFSET
- I40E_NVM_OEM_GEN_OFFSET
- I40E_NVM_OEM_LENGTH
- I40E_NVM_OEM_LENGTH_OFFSET
- I40E_NVM_OEM_RELEASE_OFFSET
- I40E_NVM_OEM_VER_OFF
- I40E_NVM_PRESERVATION_FLAGS_ALL
- I40E_NVM_PRESERVATION_FLAGS_MASK
- I40E_NVM_PRESERVATION_FLAGS_SELECTED
- I40E_NVM_PRESERVATION_FLAGS_SHIFT
- I40E_NVM_READ
- I40E_NVM_RESOURCE_ID
- I40E_NVM_SA
- I40E_NVM_SECTOR_SIZE
- I40E_NVM_SNT
- I40E_NVM_TRANS_MASK
- I40E_NVM_TRANS_SHIFT
- I40E_NVM_VERSION_HI_MASK
- I40E_NVM_VERSION_HI_SHIFT
- I40E_NVM_VERSION_LO_MASK
- I40E_NVM_VERSION_LO_SHIFT
- I40E_NVM_WRITE
- I40E_OEM_EETRACK_ID
- I40E_OEM_GEN_SHIFT
- I40E_OEM_RELEASE_MASK
- I40E_OEM_SNAP_MASK
- I40E_OEM_SNAP_SHIFT
- I40E_OEM_VER_BUILD_MASK
- I40E_OEM_VER_BUILD_SHIFT
- I40E_OEM_VER_PATCH_MASK
- I40E_OEM_VER_SHIFT
- I40E_ORT_PREP_VAL
- I40E_ORT_SET_COUNT
- I40E_ORT_SET_IDX
- I40E_ORT_SET_PAYLOAD
- I40E_PACKET_HDR_PAD
- I40E_PE_ITR
- I40E_PE_QUAD_HASH_FLTR
- I40E_PFCM_LANCTXCTL
- I40E_PFCM_LANCTXCTL_OP_CODE_MASK
- I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT
- I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK
- I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT
- I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK
- I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT
- I40E_PFCM_LANCTXCTL_SUB_LINE_MASK
- I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT
- I40E_PFCM_LANCTXDATA
- I40E_PFCM_LANCTXDATA_DATA_MASK
- I40E_PFCM_LANCTXDATA_DATA_SHIFT
- I40E_PFCM_LANCTXDATA_MAX_INDEX
- I40E_PFCM_LANCTXSTAT
- I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK
- I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT
- I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK
- I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT
- I40E_PFCM_LAN_ERRDATA
- I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK
- I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT
- I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK
- I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT
- I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK
- I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT
- I40E_PFCM_LAN_ERRINFO
- I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK
- I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT
- I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK
- I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT
- I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK
- I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT
- I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK
- I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT
- I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK
- I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT
- I40E_PFCM_PE_ERRDATA
- I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK
- I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT
- I40E_PFCM_PE_ERRDATA_Q_NUM_MASK
- I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT
- I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK
- I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT
- I40E_PFCM_PE_ERRINFO
- I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK
- I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT
- I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK
- I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT
- I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK
- I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT
- I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK
- I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT
- I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK
- I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT
- I40E_PFC_STAT
- I40E_PFC_STATS_LEN
- I40E_PFGEN_CTRL
- I40E_PFGEN_CTRL_PFSWR_MASK
- I40E_PFGEN_CTRL_PFSWR_SHIFT
- I40E_PFGEN_DRUN
- I40E_PFGEN_DRUN_DRVUNLD_MASK
- I40E_PFGEN_DRUN_DRVUNLD_SHIFT
- I40E_PFGEN_PORTMDIO_NUM
- I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK
- I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT
- I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK
- I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT
- I40E_PFGEN_PORTNUM
- I40E_PFGEN_PORTNUM_PORT_NUM_MASK
- I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT
- I40E_PFGEN_STATE
- I40E_PFGEN_STATE_PFFCEN_MASK
- I40E_PFGEN_STATE_PFFCEN_SHIFT
- I40E_PFGEN_STATE_PFLINKEN_MASK
- I40E_PFGEN_STATE_PFLINKEN_SHIFT
- I40E_PFGEN_STATE_PFSCEN_MASK
- I40E_PFGEN_STATE_PFSCEN_SHIFT
- I40E_PFGEN_STATE_RESERVED_0_MASK
- I40E_PFGEN_STATE_RESERVED_0_SHIFT
- I40E_PFHMC_ERRORDATA
- I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK
- I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT
- I40E_PFHMC_ERRORINFO
- I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK
- I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT
- I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK
- I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT
- I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK
- I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT
- I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK
- I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT
- I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK
- I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT
- I40E_PFHMC_PDINV
- I40E_PFHMC_PDINV_PMPDIDX_MASK
- I40E_PFHMC_PDINV_PMPDIDX_SHIFT
- I40E_PFHMC_PDINV_PMSDIDX_MASK
- I40E_PFHMC_PDINV_PMSDIDX_SHIFT
- I40E_PFHMC_PDINV_PMSDPARTSEL_MASK
- I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT
- I40E_PFHMC_SDCMD
- I40E_PFHMC_SDCMD_PMSDIDX_MASK
- I40E_PFHMC_SDCMD_PMSDIDX_SHIFT
- I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK
- I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT
- I40E_PFHMC_SDCMD_PMSDWR_MASK
- I40E_PFHMC_SDCMD_PMSDWR_SHIFT
- I40E_PFHMC_SDDATAHIGH
- I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK
- I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT
- I40E_PFHMC_SDDATALOW
- I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK
- I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT
- I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK
- I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT
- I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK
- I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT
- I40E_PFHMC_SDDATALOW_PMSDVALID_MASK
- I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT
- I40E_PFINT_AEQCTL
- I40E_PFINT_AEQCTL_CAUSE_ENA_MASK
- I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT
- I40E_PFINT_AEQCTL_INTEVENT_MASK
- I40E_PFINT_AEQCTL_INTEVENT_SHIFT
- I40E_PFINT_AEQCTL_ITR_INDX_MASK
- I40E_PFINT_AEQCTL_ITR_INDX_SHIFT
- I40E_PFINT_AEQCTL_MSIX0_INDX_MASK
- I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT
- I40E_PFINT_AEQCTL_MSIX_INDX_MASK
- I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT
- I40E_PFINT_CEQCTL
- I40E_PFINT_CEQCTL_CAUSE_ENA_MASK
- I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT
- I40E_PFINT_CEQCTL_INTEVENT_MASK
- I40E_PFINT_CEQCTL_INTEVENT_SHIFT
- I40E_PFINT_CEQCTL_ITR_INDX_MASK
- I40E_PFINT_CEQCTL_ITR_INDX_SHIFT
- I40E_PFINT_CEQCTL_MAX_INDEX
- I40E_PFINT_CEQCTL_MSIX0_INDX_MASK
- I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT
- I40E_PFINT_CEQCTL_MSIX_INDX_MASK
- I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT
- I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK
- I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT
- I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK
- I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT
- I40E_PFINT_DYN_CTL0
- I40E_PFINT_DYN_CTL0_CLEARPBA_MASK
- I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT
- I40E_PFINT_DYN_CTL0_INTENA_MASK
- I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK
- I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT
- I40E_PFINT_DYN_CTL0_INTENA_SHIFT
- I40E_PFINT_DYN_CTL0_INTERVAL_MASK
- I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT
- I40E_PFINT_DYN_CTL0_ITR_INDX_MASK
- I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT
- I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK
- I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT
- I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK
- I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT
- I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK
- I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT
- I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK
- I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT
- I40E_PFINT_DYN_CTLN
- I40E_PFINT_DYN_CTLN_CLEARPBA_MASK
- I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT
- I40E_PFINT_DYN_CTLN_INTENA_MASK
- I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK
- I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT
- I40E_PFINT_DYN_CTLN_INTENA_SHIFT
- I40E_PFINT_DYN_CTLN_INTERVAL_MASK
- I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT
- I40E_PFINT_DYN_CTLN_ITR_INDX_MASK
- I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT
- I40E_PFINT_DYN_CTLN_MAX_INDEX
- I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK
- I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT
- I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK
- I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT
- I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK
- I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT
- I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK
- I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT
- I40E_PFINT_GPIO_ENA
- I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT
- I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK
- I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT
- I40E_PFINT_ICR0
- I40E_PFINT_ICR0_ADMINQ_MASK
- I40E_PFINT_ICR0_ADMINQ_SHIFT
- I40E_PFINT_ICR0_ECC_ERR_MASK
- I40E_PFINT_ICR0_ECC_ERR_SHIFT
- I40E_PFINT_ICR0_ENA
- I40E_PFINT_ICR0_ENA_ADMINQ_MASK
- I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT
- I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
- I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT
- I40E_PFINT_ICR0_ENA_GPIO_MASK
- I40E_PFINT_ICR0_ENA_GPIO_SHIFT
- I40E_PFINT_ICR0_ENA_GRST_MASK
- I40E_PFINT_ICR0_ENA_GRST_SHIFT
- I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
- I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT
- I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK
- I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT
- I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
- I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT
- I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
- I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT
- I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
- I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT
- I40E_PFINT_ICR0_ENA_RSVD_MASK
- I40E_PFINT_ICR0_ENA_RSVD_SHIFT
- I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK
- I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT
- I40E_PFINT_ICR0_ENA_TIMESYNC_MASK
- I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT
- I40E_PFINT_ICR0_ENA_VFLR_MASK
- I40E_PFINT_ICR0_ENA_VFLR_SHIFT
- I40E_PFINT_ICR0_GPIO_MASK
- I40E_PFINT_ICR0_GPIO_SHIFT
- I40E_PFINT_ICR0_GRST_MASK
- I40E_PFINT_ICR0_GRST_SHIFT
- I40E_PFINT_ICR0_HMC_ERR_MASK
- I40E_PFINT_ICR0_HMC_ERR_SHIFT
- I40E_PFINT_ICR0_INTEVENT_MASK
- I40E_PFINT_ICR0_INTEVENT_SHIFT
- I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK
- I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT
- I40E_PFINT_ICR0_MAL_DETECT_MASK
- I40E_PFINT_ICR0_MAL_DETECT_SHIFT
- I40E_PFINT_ICR0_PCI_EXCEPTION_MASK
- I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT
- I40E_PFINT_ICR0_PE_CRITERR_MASK
- I40E_PFINT_ICR0_PE_CRITERR_SHIFT
- I40E_PFINT_ICR0_QUEUE_0_MASK
- I40E_PFINT_ICR0_QUEUE_0_SHIFT
- I40E_PFINT_ICR0_QUEUE_1_MASK
- I40E_PFINT_ICR0_QUEUE_1_SHIFT
- I40E_PFINT_ICR0_QUEUE_2_MASK
- I40E_PFINT_ICR0_QUEUE_2_SHIFT
- I40E_PFINT_ICR0_QUEUE_3_MASK
- I40E_PFINT_ICR0_QUEUE_3_SHIFT
- I40E_PFINT_ICR0_QUEUE_4_MASK
- I40E_PFINT_ICR0_QUEUE_4_SHIFT
- I40E_PFINT_ICR0_QUEUE_5_MASK
- I40E_PFINT_ICR0_QUEUE_5_SHIFT
- I40E_PFINT_ICR0_QUEUE_6_MASK
- I40E_PFINT_ICR0_QUEUE_6_SHIFT
- I40E_PFINT_ICR0_QUEUE_7_MASK
- I40E_PFINT_ICR0_QUEUE_7_SHIFT
- I40E_PFINT_ICR0_STORM_DETECT_MASK
- I40E_PFINT_ICR0_STORM_DETECT_SHIFT
- I40E_PFINT_ICR0_SWINT_MASK
- I40E_PFINT_ICR0_SWINT_SHIFT
- I40E_PFINT_ICR0_TIMESYNC_MASK
- I40E_PFINT_ICR0_TIMESYNC_SHIFT
- I40E_PFINT_ICR0_VFLR_MASK
- I40E_PFINT_ICR0_VFLR_SHIFT
- I40E_PFINT_ITR0
- I40E_PFINT_ITR0_INTERVAL_MASK
- I40E_PFINT_ITR0_INTERVAL_SHIFT
- I40E_PFINT_ITR0_MAX_INDEX
- I40E_PFINT_ITRN
- I40E_PFINT_ITRN_INTERVAL_MASK
- I40E_PFINT_ITRN_INTERVAL_SHIFT
- I40E_PFINT_ITRN_MAX_INDEX
- I40E_PFINT_LNKLST0
- I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK
- I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT
- I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK
- I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT
- I40E_PFINT_LNKLSTN
- I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK
- I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT
- I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK
- I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT
- I40E_PFINT_LNKLSTN_MAX_INDEX
- I40E_PFINT_RATE0
- I40E_PFINT_RATE0_INTERVAL_MASK
- I40E_PFINT_RATE0_INTERVAL_SHIFT
- I40E_PFINT_RATE0_INTRL_ENA_MASK
- I40E_PFINT_RATE0_INTRL_ENA_SHIFT
- I40E_PFINT_RATEN
- I40E_PFINT_RATEN_INTERVAL_MASK
- I40E_PFINT_RATEN_INTERVAL_SHIFT
- I40E_PFINT_RATEN_INTRL_ENA_MASK
- I40E_PFINT_RATEN_INTRL_ENA_SHIFT
- I40E_PFINT_RATEN_MAX_INDEX
- I40E_PFINT_STAT_CTL0
- I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK
- I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT
- I40E_PFLAN_QALLOC
- I40E_PFLAN_QALLOC_FIRSTQ_MASK
- I40E_PFLAN_QALLOC_FIRSTQ_SHIFT
- I40E_PFLAN_QALLOC_LASTQ_MASK
- I40E_PFLAN_QALLOC_LASTQ_SHIFT
- I40E_PFLAN_QALLOC_VALID_MASK
- I40E_PFLAN_QALLOC_VALID_SHIFT
- I40E_PFPCI_CLASS
- I40E_PFPCI_CLASS_PF_IS_LAN_MASK
- I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT
- I40E_PFPCI_CLASS_RESERVED_1_MASK
- I40E_PFPCI_CLASS_RESERVED_1_SHIFT
- I40E_PFPCI_CLASS_STORAGE_CLASS_MASK
- I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT
- I40E_PFPCI_CNF
- I40E_PFPCI_CNF_EXROM_DIS_MASK
- I40E_PFPCI_CNF_EXROM_DIS_SHIFT
- I40E_PFPCI_CNF_INT_PIN_MASK
- I40E_PFPCI_CNF_INT_PIN_SHIFT
- I40E_PFPCI_CNF_IO_BAR_MASK
- I40E_PFPCI_CNF_IO_BAR_SHIFT
- I40E_PFPCI_CNF_MSI_EN_MASK
- I40E_PFPCI_CNF_MSI_EN_SHIFT
- I40E_PFPCI_DEVID
- I40E_PFPCI_DEVID_PF_DEV_ID_MASK
- I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT
- I40E_PFPCI_DEVID_VF_DEV_ID_MASK
- I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT
- I40E_PFPCI_FACTPS
- I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK
- I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT
- I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK
- I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT
- I40E_PFPCI_FUNC
- I40E_PFPCI_FUNC2
- I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK
- I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT
- I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK
- I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT
- I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK
- I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT
- I40E_PFPCI_FUNC_FUNC_DIS_MASK
- I40E_PFPCI_FUNC_FUNC_DIS_SHIFT
- I40E_PFPCI_ICAUSE
- I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK
- I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT
- I40E_PFPCI_IENA
- I40E_PFPCI_IENA_PCIE_ERR_EN_MASK
- I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT
- I40E_PFPCI_PF_FLUSH_DONE
- I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK
- I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT
- I40E_PFPCI_PM
- I40E_PFPCI_PM_PME_EN_MASK
- I40E_PFPCI_PM_PME_EN_SHIFT
- I40E_PFPCI_STATUS1
- I40E_PFPCI_STATUS1_FUNC_VALID_MASK
- I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT
- I40E_PFPCI_SUBSYSID
- I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK
- I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT
- I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK
- I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT
- I40E_PFPCI_VF_FLUSH_DONE
- I40E_PFPCI_VF_FLUSH_DONE1
- I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK
- I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT
- I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX
- I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK
- I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT
- I40E_PFPCI_VMINDEX
- I40E_PFPCI_VMINDEX_VMINDEX_MASK
- I40E_PFPCI_VMINDEX_VMINDEX_SHIFT
- I40E_PFPCI_VMPEND
- I40E_PFPCI_VMPEND_PENDING_MASK
- I40E_PFPCI_VMPEND_PENDING_SHIFT
- I40E_PFPCI_VM_FLUSH_DONE
- I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK
- I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT
- I40E_PFPE_AEQALLOC
- I40E_PFPE_AEQALLOC_AECOUNT_MASK
- I40E_PFPE_AEQALLOC_AECOUNT_SHIFT
- I40E_PFPE_CCQPHIGH
- I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK
- I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT
- I40E_PFPE_CCQPLOW
- I40E_PFPE_CCQPLOW_PECCQPLOW_MASK
- I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT
- I40E_PFPE_CCQPSTATUS
- I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK
- I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT
- I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK
- I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT
- I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK
- I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT
- I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK
- I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT
- I40E_PFPE_CQACK
- I40E_PFPE_CQACK_PECQID_MASK
- I40E_PFPE_CQACK_PECQID_SHIFT
- I40E_PFPE_CQARM
- I40E_PFPE_CQARM_PECQID_MASK
- I40E_PFPE_CQARM_PECQID_SHIFT
- I40E_PFPE_CQPDB
- I40E_PFPE_CQPDB_WQHEAD_MASK
- I40E_PFPE_CQPDB_WQHEAD_SHIFT
- I40E_PFPE_CQPERRCODES
- I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK
- I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT
- I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK
- I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT
- I40E_PFPE_CQPTAIL
- I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK
- I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT
- I40E_PFPE_CQPTAIL_WQTAIL_MASK
- I40E_PFPE_CQPTAIL_WQTAIL_SHIFT
- I40E_PFPE_FLMQ1ALLOCERR
- I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK
- I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT
- I40E_PFPE_FLMXMITALLOCERR
- I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK
- I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT
- I40E_PFPE_IPCONFIG0
- I40E_PFPE_IPCONFIG0_PEIPID_MASK
- I40E_PFPE_IPCONFIG0_PEIPID_SHIFT
- I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK
- I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT
- I40E_PFPE_MRTEIDXMASK
- I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK
- I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT
- I40E_PFPE_RCVUNEXPECTEDERROR
- I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK
- I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT
- I40E_PFPE_TCPNOWTIMER
- I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK
- I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT
- I40E_PFPE_UDACTRL
- I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK
- I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT
- I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK
- I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT
- I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK
- I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT
- I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK
- I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT
- I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK
- I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT
- I40E_PFPE_UDAUCFBQPN
- I40E_PFPE_UDAUCFBQPN_QPN_MASK
- I40E_PFPE_UDAUCFBQPN_QPN_SHIFT
- I40E_PFPE_UDAUCFBQPN_VALID_MASK
- I40E_PFPE_UDAUCFBQPN_VALID_SHIFT
- I40E_PFPE_WQEALLOC
- I40E_PFPE_WQEALLOC_PEQPID_MASK
- I40E_PFPE_WQEALLOC_PEQPID_SHIFT
- I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK
- I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT
- I40E_PFPM_APM
- I40E_PFPM_APM_APME_MASK
- I40E_PFPM_APM_APME_SHIFT
- I40E_PFPM_FHFT_LENGTH
- I40E_PFPM_FHFT_LENGTH_LENGTH_MASK
- I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT
- I40E_PFPM_FHFT_LENGTH_MAX_INDEX
- I40E_PFPM_WUC
- I40E_PFPM_WUC_EN_APM_D0_MASK
- I40E_PFPM_WUC_EN_APM_D0_SHIFT
- I40E_PFPM_WUFC
- I40E_PFPM_WUFC_FLX0_ACT_MASK
- I40E_PFPM_WUFC_FLX0_ACT_SHIFT
- I40E_PFPM_WUFC_FLX0_MASK
- I40E_PFPM_WUFC_FLX0_SHIFT
- I40E_PFPM_WUFC_FLX1_ACT_MASK
- I40E_PFPM_WUFC_FLX1_ACT_SHIFT
- I40E_PFPM_WUFC_FLX1_MASK
- I40E_PFPM_WUFC_FLX1_SHIFT
- I40E_PFPM_WUFC_FLX2_ACT_MASK
- I40E_PFPM_WUFC_FLX2_ACT_SHIFT
- I40E_PFPM_WUFC_FLX2_MASK
- I40E_PFPM_WUFC_FLX2_SHIFT
- I40E_PFPM_WUFC_FLX3_ACT_MASK
- I40E_PFPM_WUFC_FLX3_ACT_SHIFT
- I40E_PFPM_WUFC_FLX3_MASK
- I40E_PFPM_WUFC_FLX3_SHIFT
- I40E_PFPM_WUFC_FLX4_ACT_MASK
- I40E_PFPM_WUFC_FLX4_ACT_SHIFT
- I40E_PFPM_WUFC_FLX4_MASK
- I40E_PFPM_WUFC_FLX4_SHIFT
- I40E_PFPM_WUFC_FLX5_ACT_MASK
- I40E_PFPM_WUFC_FLX5_ACT_SHIFT
- I40E_PFPM_WUFC_FLX5_MASK
- I40E_PFPM_WUFC_FLX5_SHIFT
- I40E_PFPM_WUFC_FLX6_ACT_MASK
- I40E_PFPM_WUFC_FLX6_ACT_SHIFT
- I40E_PFPM_WUFC_FLX6_MASK
- I40E_PFPM_WUFC_FLX6_SHIFT
- I40E_PFPM_WUFC_FLX7_ACT_MASK
- I40E_PFPM_WUFC_FLX7_ACT_SHIFT
- I40E_PFPM_WUFC_FLX7_MASK
- I40E_PFPM_WUFC_FLX7_SHIFT
- I40E_PFPM_WUFC_FW_RST_WK_MASK
- I40E_PFPM_WUFC_FW_RST_WK_SHIFT
- I40E_PFPM_WUFC_LNKC_MASK
- I40E_PFPM_WUFC_LNKC_SHIFT
- I40E_PFPM_WUFC_MAG_MASK
- I40E_PFPM_WUFC_MAG_SHIFT
- I40E_PFPM_WUFC_MNG_MASK
- I40E_PFPM_WUFC_MNG_SHIFT
- I40E_PFPM_WUS
- I40E_PFPM_WUS_FLX0_MASK
- I40E_PFPM_WUS_FLX0_SHIFT
- I40E_PFPM_WUS_FLX1_MASK
- I40E_PFPM_WUS_FLX1_SHIFT
- I40E_PFPM_WUS_FLX2_MASK
- I40E_PFPM_WUS_FLX2_SHIFT
- I40E_PFPM_WUS_FLX3_MASK
- I40E_PFPM_WUS_FLX3_SHIFT
- I40E_PFPM_WUS_FLX4_MASK
- I40E_PFPM_WUS_FLX4_SHIFT
- I40E_PFPM_WUS_FLX5_MASK
- I40E_PFPM_WUS_FLX5_SHIFT
- I40E_PFPM_WUS_FLX6_MASK
- I40E_PFPM_WUS_FLX6_SHIFT
- I40E_PFPM_WUS_FLX7_MASK
- I40E_PFPM_WUS_FLX7_SHIFT
- I40E_PFPM_WUS_FW_RST_WK_MASK
- I40E_PFPM_WUS_FW_RST_WK_SHIFT
- I40E_PFPM_WUS_LNKC_MASK
- I40E_PFPM_WUS_LNKC_SHIFT
- I40E_PFPM_WUS_MAG_MASK
- I40E_PFPM_WUS_MAG_SHIFT
- I40E_PFPM_WUS_MNG_MASK
- I40E_PFPM_WUS_MNG_SHIFT
- I40E_PFPM_WUS_PME_STATUS_MASK
- I40E_PFPM_WUS_PME_STATUS_SHIFT
- I40E_PFQF_CTL_0
- I40E_PFQF_CTL_0_ETYPE_ENA_MASK
- I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT
- I40E_PFQF_CTL_0_FD_ENA_MASK
- I40E_PFQF_CTL_0_FD_ENA_SHIFT
- I40E_PFQF_CTL_0_HASHLUTSIZE_512
- I40E_PFQF_CTL_0_HASHLUTSIZE_MASK
- I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT
- I40E_PFQF_CTL_0_MACVLAN_ENA_MASK
- I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT
- I40E_PFQF_CTL_0_PEDSIZE_MASK
- I40E_PFQF_CTL_0_PEDSIZE_SHIFT
- I40E_PFQF_CTL_0_PEHSIZE_MASK
- I40E_PFQF_CTL_0_PEHSIZE_SHIFT
- I40E_PFQF_CTL_0_PFFCDSIZE_MASK
- I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT
- I40E_PFQF_CTL_0_PFFCHSIZE_MASK
- I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT
- I40E_PFQF_CTL_0_VFFCDSIZE_MASK
- I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT
- I40E_PFQF_CTL_0_VFFCHSIZE_MASK
- I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT
- I40E_PFQF_CTL_1
- I40E_PFQF_CTL_1_CLEARFDTABLE_MASK
- I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT
- I40E_PFQF_CTL_2
- I40E_PFQF_CTL_2_PEDSIZE_MASK
- I40E_PFQF_CTL_2_PEDSIZE_SHIFT
- I40E_PFQF_CTL_2_PEHSIZE_MASK
- I40E_PFQF_CTL_2_PEHSIZE_SHIFT
- I40E_PFQF_FDALLOC
- I40E_PFQF_FDALLOC_FDALLOC_MASK
- I40E_PFQF_FDALLOC_FDALLOC_SHIFT
- I40E_PFQF_FDALLOC_FDBEST_MASK
- I40E_PFQF_FDALLOC_FDBEST_SHIFT
- I40E_PFQF_FDSTAT
- I40E_PFQF_FDSTAT_BEST_CNT_MASK
- I40E_PFQF_FDSTAT_BEST_CNT_SHIFT
- I40E_PFQF_FDSTAT_GUARANT_CNT_MASK
- I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT
- I40E_PFQF_HENA
- I40E_PFQF_HENA_MAX_INDEX
- I40E_PFQF_HENA_PTYPE_ENA_MASK
- I40E_PFQF_HENA_PTYPE_ENA_SHIFT
- I40E_PFQF_HKEY
- I40E_PFQF_HKEY_KEY_0_MASK
- I40E_PFQF_HKEY_KEY_0_SHIFT
- I40E_PFQF_HKEY_KEY_1_MASK
- I40E_PFQF_HKEY_KEY_1_SHIFT
- I40E_PFQF_HKEY_KEY_2_MASK
- I40E_PFQF_HKEY_KEY_2_SHIFT
- I40E_PFQF_HKEY_KEY_3_MASK
- I40E_PFQF_HKEY_KEY_3_SHIFT
- I40E_PFQF_HKEY_MAX_INDEX
- I40E_PFQF_HLUT
- I40E_PFQF_HLUT_LUT0_MASK
- I40E_PFQF_HLUT_LUT0_SHIFT
- I40E_PFQF_HLUT_LUT1_MASK
- I40E_PFQF_HLUT_LUT1_SHIFT
- I40E_PFQF_HLUT_LUT2_MASK
- I40E_PFQF_HLUT_LUT2_SHIFT
- I40E_PFQF_HLUT_LUT3_MASK
- I40E_PFQF_HLUT_LUT3_SHIFT
- I40E_PFQF_HLUT_MAX_INDEX
- I40E_PFQF_HREGION
- I40E_PFQF_HREGION_MAX_INDEX
- I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT
- I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK
- I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT
- I40E_PFQF_HREGION_REGION_0_MASK
- I40E_PFQF_HREGION_REGION_0_SHIFT
- I40E_PFQF_HREGION_REGION_1_MASK
- I40E_PFQF_HREGION_REGION_1_SHIFT
- I40E_PFQF_HREGION_REGION_2_MASK
- I40E_PFQF_HREGION_REGION_2_SHIFT
- I40E_PFQF_HREGION_REGION_3_MASK
- I40E_PFQF_HREGION_REGION_3_SHIFT
- I40E_PFQF_HREGION_REGION_4_MASK
- I40E_PFQF_HREGION_REGION_4_SHIFT
- I40E_PFQF_HREGION_REGION_5_MASK
- I40E_PFQF_HREGION_REGION_5_SHIFT
- I40E_PFQF_HREGION_REGION_6_MASK
- I40E_PFQF_HREGION_REGION_6_SHIFT
- I40E_PFQF_HREGION_REGION_7_MASK
- I40E_PFQF_HREGION_REGION_7_SHIFT
- I40E_PF_ARQBAH
- I40E_PF_ARQBAH_ARQBAH_MASK
- I40E_PF_ARQBAH_ARQBAH_SHIFT
- I40E_PF_ARQBAL
- I40E_PF_ARQBAL_ARQBAL_MASK
- I40E_PF_ARQBAL_ARQBAL_SHIFT
- I40E_PF_ARQH
- I40E_PF_ARQH_ARQH_MASK
- I40E_PF_ARQH_ARQH_SHIFT
- I40E_PF_ARQLEN
- I40E_PF_ARQLEN_ARQCRIT_MASK
- I40E_PF_ARQLEN_ARQCRIT_SHIFT
- I40E_PF_ARQLEN_ARQENABLE_MASK
- I40E_PF_ARQLEN_ARQENABLE_SHIFT
- I40E_PF_ARQLEN_ARQLEN_MASK
- I40E_PF_ARQLEN_ARQLEN_SHIFT
- I40E_PF_ARQLEN_ARQOVFL_MASK
- I40E_PF_ARQLEN_ARQOVFL_SHIFT
- I40E_PF_ARQLEN_ARQVFE_MASK
- I40E_PF_ARQLEN_ARQVFE_SHIFT
- I40E_PF_ARQT
- I40E_PF_ARQT_ARQT_MASK
- I40E_PF_ARQT_ARQT_SHIFT
- I40E_PF_ATQBAH
- I40E_PF_ATQBAH_ATQBAH_MASK
- I40E_PF_ATQBAH_ATQBAH_SHIFT
- I40E_PF_ATQBAL
- I40E_PF_ATQBAL_ATQBAL_MASK
- I40E_PF_ATQBAL_ATQBAL_SHIFT
- I40E_PF_ATQH
- I40E_PF_ATQH_ATQH_MASK
- I40E_PF_ATQH_ATQH_SHIFT
- I40E_PF_ATQLEN
- I40E_PF_ATQLEN_ATQCRIT_MASK
- I40E_PF_ATQLEN_ATQCRIT_SHIFT
- I40E_PF_ATQLEN_ATQENABLE_MASK
- I40E_PF_ATQLEN_ATQENABLE_SHIFT
- I40E_PF_ATQLEN_ATQLEN_MASK
- I40E_PF_ATQLEN_ATQLEN_SHIFT
- I40E_PF_ATQLEN_ATQOVFL_MASK
- I40E_PF_ATQLEN_ATQOVFL_SHIFT
- I40E_PF_ATQLEN_ATQVFE_MASK
- I40E_PF_ATQLEN_ATQVFE_SHIFT
- I40E_PF_ATQT
- I40E_PF_ATQT_ATQT_MASK
- I40E_PF_ATQT_ATQT_SHIFT
- I40E_PF_FUNC_RID
- I40E_PF_FUNC_RID_BUS_NUMBER_MASK
- I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT
- I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK
- I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT
- I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK
- I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT
- I40E_PF_MDET_RX
- I40E_PF_MDET_RX_VALID_MASK
- I40E_PF_MDET_RX_VALID_SHIFT
- I40E_PF_MDET_TX
- I40E_PF_MDET_TX_VALID_MASK
- I40E_PF_MDET_TX_VALID_SHIFT
- I40E_PF_PCI_CIAA
- I40E_PF_PCI_CIAA_ADDRESS_MASK
- I40E_PF_PCI_CIAA_ADDRESS_SHIFT
- I40E_PF_PCI_CIAA_VF_NUM_MASK
- I40E_PF_PCI_CIAA_VF_NUM_SHIFT
- I40E_PF_PCI_CIAD
- I40E_PF_PCI_CIAD_DATA_MASK
- I40E_PF_PCI_CIAD_DATA_SHIFT
- I40E_PF_RESET_FLAG
- I40E_PF_RESET_WAIT_COUNT
- I40E_PF_RESET_WAIT_COUNT_A0
- I40E_PF_STAT
- I40E_PF_STATS_LEN
- I40E_PF_VT_PFALLOC
- I40E_PF_VT_PFALLOC_FIRSTVF_MASK
- I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT
- I40E_PF_VT_PFALLOC_LASTVF_MASK
- I40E_PF_VT_PFALLOC_LASTVF_SHIFT
- I40E_PF_VT_PFALLOC_VALID_MASK
- I40E_PF_VT_PFALLOC_VALID_SHIFT
- I40E_PHY_COM_REG_PAGE
- I40E_PHY_DEBUG_ALL
- I40E_PHY_LED_LINK_MODE_MASK
- I40E_PHY_LED_MANUAL_ON
- I40E_PHY_LED_MODE_MASK
- I40E_PHY_LED_MODE_ORIG
- I40E_PHY_LED_PROV_REG_1
- I40E_PHY_TYPES_BITMASK
- I40E_PHY_TYPE_1000BASE_KX
- I40E_PHY_TYPE_1000BASE_LX
- I40E_PHY_TYPE_1000BASE_SX
- I40E_PHY_TYPE_1000BASE_T
- I40E_PHY_TYPE_1000BASE_T_OPTICAL
- I40E_PHY_TYPE_100BASE_TX
- I40E_PHY_TYPE_10GBASE_AOC
- I40E_PHY_TYPE_10GBASE_CR1
- I40E_PHY_TYPE_10GBASE_CR1_CU
- I40E_PHY_TYPE_10GBASE_KR
- I40E_PHY_TYPE_10GBASE_KX4
- I40E_PHY_TYPE_10GBASE_LR
- I40E_PHY_TYPE_10GBASE_SFPP_CU
- I40E_PHY_TYPE_10GBASE_SR
- I40E_PHY_TYPE_10GBASE_T
- I40E_PHY_TYPE_20GBASE_KR2
- I40E_PHY_TYPE_25GBASE_ACC
- I40E_PHY_TYPE_25GBASE_AOC
- I40E_PHY_TYPE_25GBASE_CR
- I40E_PHY_TYPE_25GBASE_KR
- I40E_PHY_TYPE_25GBASE_LR
- I40E_PHY_TYPE_25GBASE_SR
- I40E_PHY_TYPE_2_5GBASE_T
- I40E_PHY_TYPE_40GBASE_AOC
- I40E_PHY_TYPE_40GBASE_CR4
- I40E_PHY_TYPE_40GBASE_CR4_CU
- I40E_PHY_TYPE_40GBASE_KR4
- I40E_PHY_TYPE_40GBASE_LR4
- I40E_PHY_TYPE_40GBASE_SR4
- I40E_PHY_TYPE_5GBASE_T
- I40E_PHY_TYPE_DEFAULT
- I40E_PHY_TYPE_EMPTY
- I40E_PHY_TYPE_MAX
- I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP
- I40E_PHY_TYPE_OFFSET
- I40E_PHY_TYPE_OFFSET2
- I40E_PHY_TYPE_SFI
- I40E_PHY_TYPE_SGMII
- I40E_PHY_TYPE_UNRECOGNIZED
- I40E_PHY_TYPE_UNSUPPORTED
- I40E_PHY_TYPE_XAUI
- I40E_PHY_TYPE_XFI
- I40E_PHY_TYPE_XLAUI
- I40E_PHY_TYPE_XLPPI
- I40E_PILE_VALID_BIT
- I40E_PRIORITY_MASK
- I40E_PRIV_FLAG
- I40E_PRIV_FLAGS_STR_LEN
- I40E_PROFILE_INFO_SIZE
- I40E_PROFILE_LIST_SIZE
- I40E_PRTDCB_FCCFG
- I40E_PRTDCB_FCCFG_TFCE_MASK
- I40E_PRTDCB_FCCFG_TFCE_SHIFT
- I40E_PRTDCB_FCRTV
- I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK
- I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT
- I40E_PRTDCB_FCTTVN
- I40E_PRTDCB_FCTTVN_MAX_INDEX
- I40E_PRTDCB_FCTTVN_TTV_2N_MASK
- I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK
- I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT
- I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT
- I40E_PRTDCB_GENC
- I40E_PRTDCB_GENC_FCOEUP_MASK
- I40E_PRTDCB_GENC_FCOEUP_SHIFT
- I40E_PRTDCB_GENC_FCOEUP_VALID_MASK
- I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT
- I40E_PRTDCB_GENC_NUMTC_MASK
- I40E_PRTDCB_GENC_NUMTC_SHIFT
- I40E_PRTDCB_GENC_PFCLDA_MASK
- I40E_PRTDCB_GENC_PFCLDA_SHIFT
- I40E_PRTDCB_GENC_RESERVED_1_MASK
- I40E_PRTDCB_GENC_RESERVED_1_SHIFT
- I40E_PRTDCB_GENS
- I40E_PRTDCB_GENS_DCBX_STATUS_MASK
- I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT
- I40E_PRTDCB_MFLCN
- I40E_PRTDCB_MFLCN_DPF_MASK
- I40E_PRTDCB_MFLCN_DPF_SHIFT
- I40E_PRTDCB_MFLCN_PMCF_MASK
- I40E_PRTDCB_MFLCN_PMCF_SHIFT
- I40E_PRTDCB_MFLCN_RFCE_MASK
- I40E_PRTDCB_MFLCN_RFCE_SHIFT
- I40E_PRTDCB_MFLCN_RPFCE_MASK
- I40E_PRTDCB_MFLCN_RPFCE_SHIFT
- I40E_PRTDCB_MFLCN_RPFCM_MASK
- I40E_PRTDCB_MFLCN_RPFCM_SHIFT
- I40E_PRTDCB_RETSC
- I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK
- I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT
- I40E_PRTDCB_RETSC_ETS_MODE_MASK
- I40E_PRTDCB_RETSC_ETS_MODE_SHIFT
- I40E_PRTDCB_RETSC_LLTC_MASK
- I40E_PRTDCB_RETSC_LLTC_SHIFT
- I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK
- I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT
- I40E_PRTDCB_RETSTCC
- I40E_PRTDCB_RETSTCC_BWSHARE_MASK
- I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT
- I40E_PRTDCB_RETSTCC_ETSTC_MASK
- I40E_PRTDCB_RETSTCC_ETSTC_SHIFT
- I40E_PRTDCB_RETSTCC_MAX_INDEX
- I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK
- I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT
- I40E_PRTDCB_RLPMC
- I40E_PRTDCB_RLPMC_TC2PFC_MASK
- I40E_PRTDCB_RLPMC_TC2PFC_SHIFT
- I40E_PRTDCB_RPPMC
- I40E_PRTDCB_RPPMC_LANRPPM_MASK
- I40E_PRTDCB_RPPMC_LANRPPM_SHIFT
- I40E_PRTDCB_RPPMC_RDMARPPM_MASK
- I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT
- I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK
- I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT
- I40E_PRTDCB_RUP
- I40E_PRTDCB_RUP2TC
- I40E_PRTDCB_RUP2TC_UP0TC_MASK
- I40E_PRTDCB_RUP2TC_UP0TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP1TC_MASK
- I40E_PRTDCB_RUP2TC_UP1TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP2TC_MASK
- I40E_PRTDCB_RUP2TC_UP2TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP3TC_MASK
- I40E_PRTDCB_RUP2TC_UP3TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP4TC_MASK
- I40E_PRTDCB_RUP2TC_UP4TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP5TC_MASK
- I40E_PRTDCB_RUP2TC_UP5TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP6TC_MASK
- I40E_PRTDCB_RUP2TC_UP6TC_SHIFT
- I40E_PRTDCB_RUP2TC_UP7TC_MASK
- I40E_PRTDCB_RUP2TC_UP7TC_SHIFT
- I40E_PRTDCB_RUPTQ
- I40E_PRTDCB_RUPTQ_MAX_INDEX
- I40E_PRTDCB_RUPTQ_RXQNUM_MASK
- I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT
- I40E_PRTDCB_RUP_NOVLANUP_MASK
- I40E_PRTDCB_RUP_NOVLANUP_SHIFT
- I40E_PRTDCB_TC2PFC
- I40E_PRTDCB_TC2PFC_TC2PFC_MASK
- I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT
- I40E_PRTDCB_TCMSTC
- I40E_PRTDCB_TCMSTC_MAX_INDEX
- I40E_PRTDCB_TCMSTC_MSTC_MASK
- I40E_PRTDCB_TCMSTC_MSTC_SHIFT
- I40E_PRTDCB_TCMSTC_RLPM
- I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX
- I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK
- I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT
- I40E_PRTDCB_TCPMC
- I40E_PRTDCB_TCPMC_CPM_MASK
- I40E_PRTDCB_TCPMC_CPM_SHIFT
- I40E_PRTDCB_TCPMC_LLTC_MASK
- I40E_PRTDCB_TCPMC_LLTC_SHIFT
- I40E_PRTDCB_TCPMC_RLPM
- I40E_PRTDCB_TCPMC_RLPM_CPM_MASK
- I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT
- I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK
- I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT
- I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK
- I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT
- I40E_PRTDCB_TCPMC_TCPM_MODE_MASK
- I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT
- I40E_PRTDCB_TCWSTC
- I40E_PRTDCB_TCWSTC_MAX_INDEX
- I40E_PRTDCB_TCWSTC_MSTC_MASK
- I40E_PRTDCB_TCWSTC_MSTC_SHIFT
- I40E_PRTDCB_TDPMC
- I40E_PRTDCB_TDPMC_DPM_MASK
- I40E_PRTDCB_TDPMC_DPM_SHIFT
- I40E_PRTDCB_TDPMC_TCPM_MODE_MASK
- I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT
- I40E_PRTDCB_TETSC_TCB
- I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK
- I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT
- I40E_PRTDCB_TETSC_TCB_LLTC_MASK
- I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT
- I40E_PRTDCB_TETSC_TPB
- I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK
- I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT
- I40E_PRTDCB_TETSC_TPB_LLTC_MASK
- I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT
- I40E_PRTDCB_TFCS
- I40E_PRTDCB_TFCS_TXOFF0_MASK
- I40E_PRTDCB_TFCS_TXOFF0_SHIFT
- I40E_PRTDCB_TFCS_TXOFF1_MASK
- I40E_PRTDCB_TFCS_TXOFF1_SHIFT
- I40E_PRTDCB_TFCS_TXOFF2_MASK
- I40E_PRTDCB_TFCS_TXOFF2_SHIFT
- I40E_PRTDCB_TFCS_TXOFF3_MASK
- I40E_PRTDCB_TFCS_TXOFF3_SHIFT
- I40E_PRTDCB_TFCS_TXOFF4_MASK
- I40E_PRTDCB_TFCS_TXOFF4_SHIFT
- I40E_PRTDCB_TFCS_TXOFF5_MASK
- I40E_PRTDCB_TFCS_TXOFF5_SHIFT
- I40E_PRTDCB_TFCS_TXOFF6_MASK
- I40E_PRTDCB_TFCS_TXOFF6_SHIFT
- I40E_PRTDCB_TFCS_TXOFF7_MASK
- I40E_PRTDCB_TFCS_TXOFF7_SHIFT
- I40E_PRTDCB_TFCS_TXOFF_MASK
- I40E_PRTDCB_TFCS_TXOFF_SHIFT
- I40E_PRTDCB_TFMSTC
- I40E_PRTDCB_TFMSTC_MAX_INDEX
- I40E_PRTDCB_TFMSTC_MSTC_MASK
- I40E_PRTDCB_TFMSTC_MSTC_SHIFT
- I40E_PRTDCB_TPFCTS
- I40E_PRTDCB_TPFCTS_MAX_INDEX
- I40E_PRTDCB_TPFCTS_PFCTIMER_MASK
- I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT
- I40E_PRTE_RUPM_TCCNTR03
- I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK
- I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT
- I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK
- I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT
- I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK
- I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT
- I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK
- I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT
- I40E_PRTGEN_CNF
- I40E_PRTGEN_CNF2
- I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK
- I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT
- I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK
- I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT
- I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK
- I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT
- I40E_PRTGEN_CNF_PORT_DIS_MASK
- I40E_PRTGEN_CNF_PORT_DIS_SHIFT
- I40E_PRTGEN_STATUS
- I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK
- I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT
- I40E_PRTGEN_STATUS_PORT_VALID_MASK
- I40E_PRTGEN_STATUS_PORT_VALID_SHIFT
- I40E_PRTGL_SAH
- I40E_PRTGL_SAH_FC_SAH_MASK
- I40E_PRTGL_SAH_FC_SAH_SHIFT
- I40E_PRTGL_SAH_MFS_MASK
- I40E_PRTGL_SAH_MFS_SHIFT
- I40E_PRTGL_SAL
- I40E_PRTGL_SAL_FC_SAL_MASK
- I40E_PRTGL_SAL_FC_SAL_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK
- I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL
- I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK
- I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK
- I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT
- I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART1
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART2
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK
- I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT
- I40E_PRTMAC_LINK_DOWN_COUNTER
- I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK
- I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK
- I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT
- I40E_PRTPE_RUPM_CNTR
- I40E_PRTPE_RUPM_CNTR_COUNT_MASK
- I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT
- I40E_PRTPE_RUPM_CTL
- I40E_PRTPE_RUPM_CTL_LLTC_MASK
- I40E_PRTPE_RUPM_CTL_LLTC_SHIFT
- I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK
- I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT
- I40E_PRTPE_RUPM_PFCCTL
- I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK
- I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT
- I40E_PRTPE_RUPM_PFCPC
- I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK
- I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT
- I40E_PRTPE_RUPM_PFCTCC
- I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK
- I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT
- I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK
- I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT
- I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK
- I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT
- I40E_PRTPE_RUPM_PTCTCCNTR47
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK
- I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT
- I40E_PRTPE_RUPM_PTXTCCNTR03
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK
- I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT
- I40E_PRTPE_RUPM_TCCNTR47
- I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK
- I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT
- I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK
- I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT
- I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK
- I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT
- I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK
- I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT
- I40E_PRTPE_RUPM_THRES
- I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK
- I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT
- I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK
- I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT
- I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK
- I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT
- I40E_PRTPM_EEEC
- I40E_PRTPM_EEEC_TEEE_DLY_MASK
- I40E_PRTPM_EEEC_TEEE_DLY_SHIFT
- I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK
- I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT
- I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK
- I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT
- I40E_PRTPM_EEEFWD
- I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK
- I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT
- I40E_PRTPM_EEER
- I40E_PRTPM_EEER_TW_SYSTEM_MASK
- I40E_PRTPM_EEER_TW_SYSTEM_SHIFT
- I40E_PRTPM_EEER_TX_LPI_EN_MASK
- I40E_PRTPM_EEER_TX_LPI_EN_SHIFT
- I40E_PRTPM_EEETXC
- I40E_PRTPM_EEETXC_TW_PHY_MASK
- I40E_PRTPM_EEETXC_TW_PHY_SHIFT
- I40E_PRTPM_EEE_STAT
- I40E_PRTPM_EEE_STAT_EEE_NEG_MASK
- I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT
- I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK
- I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT
- I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK
- I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT
- I40E_PRTPM_FHFHR
- I40E_PRTPM_FHFHR_MULTICAST_MASK
- I40E_PRTPM_FHFHR_MULTICAST_SHIFT
- I40E_PRTPM_FHFHR_UNICAST_MASK
- I40E_PRTPM_FHFHR_UNICAST_SHIFT
- I40E_PRTPM_GC
- I40E_PRTPM_GC_EMP_LINK_ON_MASK
- I40E_PRTPM_GC_EMP_LINK_ON_SHIFT
- I40E_PRTPM_GC_LCDMP_MASK
- I40E_PRTPM_GC_LCDMP_SHIFT
- I40E_PRTPM_GC_LPLU_ASSERTED_MASK
- I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT
- I40E_PRTPM_GC_MNG_VETO_MASK
- I40E_PRTPM_GC_MNG_VETO_SHIFT
- I40E_PRTPM_GC_RATD_MASK
- I40E_PRTPM_GC_RATD_SHIFT
- I40E_PRTPM_RLPIC
- I40E_PRTPM_RLPIC_ERLPIC_MASK
- I40E_PRTPM_RLPIC_ERLPIC_SHIFT
- I40E_PRTPM_SAH
- I40E_PRTPM_SAH_AV_MASK
- I40E_PRTPM_SAH_AV_SHIFT
- I40E_PRTPM_SAH_MAX_INDEX
- I40E_PRTPM_SAH_MC_MAG_EN_MASK
- I40E_PRTPM_SAH_MC_MAG_EN_SHIFT
- I40E_PRTPM_SAH_PFPM_SAH_MASK
- I40E_PRTPM_SAH_PFPM_SAH_SHIFT
- I40E_PRTPM_SAH_PF_NUM_MASK
- I40E_PRTPM_SAH_PF_NUM_SHIFT
- I40E_PRTPM_SAL
- I40E_PRTPM_SAL_MAX_INDEX
- I40E_PRTPM_SAL_PFPM_SAL_MASK
- I40E_PRTPM_SAL_PFPM_SAL_SHIFT
- I40E_PRTPM_TLPIC
- I40E_PRTPM_TLPIC_ETLPIC_MASK
- I40E_PRTPM_TLPIC_ETLPIC_SHIFT
- I40E_PRTQF_CTL_0
- I40E_PRTQF_CTL_0_HSYM_ENA_MASK
- I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT
- I40E_PRTQF_FD_FLXINSET
- I40E_PRTQF_FD_FLXINSET_INSET_MASK
- I40E_PRTQF_FD_FLXINSET_INSET_SHIFT
- I40E_PRTQF_FD_FLXINSET_MAX_INDEX
- I40E_PRTQF_FD_INSET
- I40E_PRTQF_FD_INSET_INSET_MASK
- I40E_PRTQF_FD_INSET_INSET_SHIFT
- I40E_PRTQF_FD_INSET_MAX_INDEX
- I40E_PRTQF_FD_MSK
- I40E_PRTQF_FD_MSK_MASK_MASK
- I40E_PRTQF_FD_MSK_MASK_SHIFT
- I40E_PRTQF_FD_MSK_MAX_INDEX
- I40E_PRTQF_FD_MSK_OFFSET_MASK
- I40E_PRTQF_FD_MSK_OFFSET_SHIFT
- I40E_PRTQF_FLX_PIT
- I40E_PRTQF_FLX_PIT_DEST_OFF_MASK
- I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT
- I40E_PRTQF_FLX_PIT_FSIZE_MASK
- I40E_PRTQF_FLX_PIT_FSIZE_SHIFT
- I40E_PRTQF_FLX_PIT_MAX_INDEX
- I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK
- I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT
- I40E_PRTRPB_DHW
- I40E_PRTRPB_DHW_DHW_TCN_MASK
- I40E_PRTRPB_DHW_DHW_TCN_SHIFT
- I40E_PRTRPB_DHW_MAX_INDEX
- I40E_PRTRPB_DLW
- I40E_PRTRPB_DLW_DLW_TCN_MASK
- I40E_PRTRPB_DLW_DLW_TCN_SHIFT
- I40E_PRTRPB_DLW_MAX_INDEX
- I40E_PRTRPB_DPS
- I40E_PRTRPB_DPS_DPS_TCN_MASK
- I40E_PRTRPB_DPS_DPS_TCN_SHIFT
- I40E_PRTRPB_DPS_MAX_INDEX
- I40E_PRTRPB_SHT
- I40E_PRTRPB_SHT_MAX_INDEX
- I40E_PRTRPB_SHT_SHT_TCN_MASK
- I40E_PRTRPB_SHT_SHT_TCN_SHIFT
- I40E_PRTRPB_SHW
- I40E_PRTRPB_SHW_SHW_MASK
- I40E_PRTRPB_SHW_SHW_SHIFT
- I40E_PRTRPB_SLT
- I40E_PRTRPB_SLT_MAX_INDEX
- I40E_PRTRPB_SLT_SLT_TCN_MASK
- I40E_PRTRPB_SLT_SLT_TCN_SHIFT
- I40E_PRTRPB_SLW
- I40E_PRTRPB_SLW_SLW_MASK
- I40E_PRTRPB_SLW_SLW_SHIFT
- I40E_PRTRPB_SPS
- I40E_PRTRPB_SPS_SPS_MASK
- I40E_PRTRPB_SPS_SPS_SHIFT
- I40E_PRTTSYN_ADJ
- I40E_PRTTSYN_ADJ_SIGN_MASK
- I40E_PRTTSYN_ADJ_SIGN_SHIFT
- I40E_PRTTSYN_ADJ_TSYNADJ_MASK
- I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT
- I40E_PRTTSYN_AUX_0
- I40E_PRTTSYN_AUX_0_EVNTLVL_MASK
- I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT
- I40E_PRTTSYN_AUX_0_MAX_INDEX
- I40E_PRTTSYN_AUX_0_OUTLVL_MASK
- I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT
- I40E_PRTTSYN_AUX_0_OUTMOD_MASK
- I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT
- I40E_PRTTSYN_AUX_0_OUT_ENA_MASK
- I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT
- I40E_PRTTSYN_AUX_0_PULSEW_MASK
- I40E_PRTTSYN_AUX_0_PULSEW_SHIFT
- I40E_PRTTSYN_AUX_1
- I40E_PRTTSYN_AUX_1_INSTNT_MASK
- I40E_PRTTSYN_AUX_1_INSTNT_SHIFT
- I40E_PRTTSYN_AUX_1_MAX_INDEX
- I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK
- I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT
- I40E_PRTTSYN_CLKO
- I40E_PRTTSYN_CLKO_MAX_INDEX
- I40E_PRTTSYN_CLKO_TSYNCLKO_MASK
- I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT
- I40E_PRTTSYN_CTL0
- I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK
- I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT
- I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK
- I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT
- I40E_PRTTSYN_CTL0_PF_ID_MASK
- I40E_PRTTSYN_CTL0_PF_ID_SHIFT
- I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK
- I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT
- I40E_PRTTSYN_CTL0_TSYNACT_MASK
- I40E_PRTTSYN_CTL0_TSYNACT_SHIFT
- I40E_PRTTSYN_CTL0_TSYNENA_MASK
- I40E_PRTTSYN_CTL0_TSYNENA_SHIFT
- I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK
- I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT
- I40E_PRTTSYN_CTL1
- I40E_PRTTSYN_CTL1_TSYNENA_MASK
- I40E_PRTTSYN_CTL1_TSYNENA_SHIFT
- I40E_PRTTSYN_CTL1_TSYNTYPE_MASK
- I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT
- I40E_PRTTSYN_CTL1_TSYNTYPE_V1
- I40E_PRTTSYN_CTL1_TSYNTYPE_V2
- I40E_PRTTSYN_CTL1_UDP_ENA_MASK
- I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT
- I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK
- I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT
- I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK
- I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT
- I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK
- I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT
- I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK
- I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT
- I40E_PRTTSYN_EVNT_H
- I40E_PRTTSYN_EVNT_H_MAX_INDEX
- I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK
- I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT
- I40E_PRTTSYN_EVNT_L
- I40E_PRTTSYN_EVNT_L_MAX_INDEX
- I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK
- I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT
- I40E_PRTTSYN_INC_H
- I40E_PRTTSYN_INC_H_TSYNINC_H_MASK
- I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT
- I40E_PRTTSYN_INC_L
- I40E_PRTTSYN_INC_L_TSYNINC_L_MASK
- I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT
- I40E_PRTTSYN_RXTIME_H
- I40E_PRTTSYN_RXTIME_H_MAX_INDEX
- I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK
- I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT
- I40E_PRTTSYN_RXTIME_L
- I40E_PRTTSYN_RXTIME_L_MAX_INDEX
- I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK
- I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT
- I40E_PRTTSYN_STAT_0
- I40E_PRTTSYN_STAT_0_EVENT0_MASK
- I40E_PRTTSYN_STAT_0_EVENT0_SHIFT
- I40E_PRTTSYN_STAT_0_EVENT1_MASK
- I40E_PRTTSYN_STAT_0_EVENT1_SHIFT
- I40E_PRTTSYN_STAT_0_TGT0_MASK
- I40E_PRTTSYN_STAT_0_TGT0_SHIFT
- I40E_PRTTSYN_STAT_0_TGT1_MASK
- I40E_PRTTSYN_STAT_0_TGT1_SHIFT
- I40E_PRTTSYN_STAT_0_TXTIME_MASK
- I40E_PRTTSYN_STAT_0_TXTIME_SHIFT
- I40E_PRTTSYN_STAT_1
- I40E_PRTTSYN_STAT_1_RXT0_MASK
- I40E_PRTTSYN_STAT_1_RXT0_SHIFT
- I40E_PRTTSYN_STAT_1_RXT1_MASK
- I40E_PRTTSYN_STAT_1_RXT1_SHIFT
- I40E_PRTTSYN_STAT_1_RXT2_MASK
- I40E_PRTTSYN_STAT_1_RXT2_SHIFT
- I40E_PRTTSYN_STAT_1_RXT3_MASK
- I40E_PRTTSYN_STAT_1_RXT3_SHIFT
- I40E_PRTTSYN_TGT_H
- I40E_PRTTSYN_TGT_H_MAX_INDEX
- I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK
- I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT
- I40E_PRTTSYN_TGT_L
- I40E_PRTTSYN_TGT_L_MAX_INDEX
- I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK
- I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT
- I40E_PRTTSYN_TIME_H
- I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK
- I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT
- I40E_PRTTSYN_TIME_L
- I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK
- I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT
- I40E_PRTTSYN_TXTIME_H
- I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK
- I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT
- I40E_PRTTSYN_TXTIME_L
- I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK
- I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT
- I40E_PRT_L2TAGSEN
- I40E_PRT_L2TAGSEN_ENABLE_MASK
- I40E_PRT_L2TAGSEN_ENABLE_SHIFT
- I40E_PRT_MNG_FTFT_DATA
- I40E_PRT_MNG_FTFT_DATA_DWORD_MASK
- I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT
- I40E_PRT_MNG_FTFT_DATA_MAX_INDEX
- I40E_PRT_MNG_FTFT_LENGTH
- I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK
- I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT
- I40E_PRT_MNG_FTFT_MASK
- I40E_PRT_MNG_FTFT_MASK_MASK_MASK
- I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT
- I40E_PRT_MNG_FTFT_MASK_MAX_INDEX
- I40E_PRT_MNG_MANC
- I40E_PRT_MNG_MANC_EN_BMC2NET_MASK
- I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT
- I40E_PRT_MNG_MANC_EN_BMC2OS_MASK
- I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT
- I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK
- I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT
- I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK
- I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT
- I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK
- I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT
- I40E_PRT_MNG_MANC_NET_TYPE_MASK
- I40E_PRT_MNG_MANC_NET_TYPE_SHIFT
- I40E_PRT_MNG_MANC_RCV_ALL_MASK
- I40E_PRT_MNG_MANC_RCV_ALL_SHIFT
- I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK
- I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT
- I40E_PRT_MNG_MAVTV
- I40E_PRT_MNG_MAVTV_MAX_INDEX
- I40E_PRT_MNG_MAVTV_VID_MASK
- I40E_PRT_MNG_MAVTV_VID_SHIFT
- I40E_PRT_MNG_MDEF
- I40E_PRT_MNG_MDEFVSI
- I40E_PRT_MNG_MDEFVSI_MAX_INDEX
- I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK
- I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT
- I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK
- I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT
- I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK
- I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT
- I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK
- I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT
- I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK
- I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT
- I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK
- I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT
- I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK
- I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT
- I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK
- I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT
- I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK
- I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT
- I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK
- I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT
- I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT_MAX_INDEX
- I40E_PRT_MNG_MDEF_EXT_MLD_MASK
- I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK
- I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT
- I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK
- I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT
- I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK
- I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT
- I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK
- I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT
- I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK
- I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT
- I40E_PRT_MNG_MDEF_MAX_INDEX
- I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK
- I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT
- I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK
- I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT
- I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK
- I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT
- I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK
- I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT
- I40E_PRT_MNG_MDEF_VLAN_AND_MASK
- I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT
- I40E_PRT_MNG_METF
- I40E_PRT_MNG_METF_ETYPE_MASK
- I40E_PRT_MNG_METF_ETYPE_SHIFT
- I40E_PRT_MNG_METF_MAX_INDEX
- I40E_PRT_MNG_METF_POLARITY_MASK
- I40E_PRT_MNG_METF_POLARITY_SHIFT
- I40E_PRT_MNG_MFUTP
- I40E_PRT_MNG_MFUTP_MAX_INDEX
- I40E_PRT_MNG_MFUTP_MFUTP_N_MASK
- I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT
- I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK
- I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT
- I40E_PRT_MNG_MFUTP_TCP_MASK
- I40E_PRT_MNG_MFUTP_TCP_SHIFT
- I40E_PRT_MNG_MFUTP_UDP_MASK
- I40E_PRT_MNG_MFUTP_UDP_SHIFT
- I40E_PRT_MNG_MIPAF4
- I40E_PRT_MNG_MIPAF4_MAX_INDEX
- I40E_PRT_MNG_MIPAF4_MIPAF_MASK
- I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT
- I40E_PRT_MNG_MIPAF6
- I40E_PRT_MNG_MIPAF6_MAX_INDEX
- I40E_PRT_MNG_MIPAF6_MIPAF_MASK
- I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT
- I40E_PRT_MNG_MMAH
- I40E_PRT_MNG_MMAH_MAX_INDEX
- I40E_PRT_MNG_MMAH_MMAH_MASK
- I40E_PRT_MNG_MMAH_MMAH_SHIFT
- I40E_PRT_MNG_MMAL
- I40E_PRT_MNG_MMAL_MAX_INDEX
- I40E_PRT_MNG_MMAL_MMAL_MASK
- I40E_PRT_MNG_MMAL_MMAL_SHIFT
- I40E_PRT_MNG_MNGONLY
- I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK
- I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT
- I40E_PRT_MNG_MSFM
- I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK
- I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT
- I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK
- I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT
- I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK
- I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT
- I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK
- I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT
- I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK
- I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT
- I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK
- I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT
- I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK
- I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT
- I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK
- I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT
- I40E_PTP_10GB_INCVAL_MULT
- I40E_PTP_1GB_INCVAL_MULT
- I40E_PTP_40GB_INCVAL
- I40E_PTR_TYPE
- I40E_PTT
- I40E_PTT_UNUSED_ENTRY
- I40E_QINT_RQCTL
- I40E_QINT_RQCTL_CAUSE_ENA_MASK
- I40E_QINT_RQCTL_CAUSE_ENA_SHIFT
- I40E_QINT_RQCTL_INTEVENT_MASK
- I40E_QINT_RQCTL_INTEVENT_SHIFT
- I40E_QINT_RQCTL_ITR_INDX_MASK
- I40E_QINT_RQCTL_ITR_INDX_SHIFT
- I40E_QINT_RQCTL_MAX_INDEX
- I40E_QINT_RQCTL_MSIX0_INDX_MASK
- I40E_QINT_RQCTL_MSIX0_INDX_SHIFT
- I40E_QINT_RQCTL_MSIX_INDX_MASK
- I40E_QINT_RQCTL_MSIX_INDX_SHIFT
- I40E_QINT_RQCTL_NEXTQ_INDX_MASK
- I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT
- I40E_QINT_RQCTL_NEXTQ_TYPE_MASK
- I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT
- I40E_QINT_TQCTL
- I40E_QINT_TQCTL_CAUSE_ENA_MASK
- I40E_QINT_TQCTL_CAUSE_ENA_SHIFT
- I40E_QINT_TQCTL_INTEVENT_MASK
- I40E_QINT_TQCTL_INTEVENT_SHIFT
- I40E_QINT_TQCTL_ITR_INDX_MASK
- I40E_QINT_TQCTL_ITR_INDX_SHIFT
- I40E_QINT_TQCTL_MAX_INDEX
- I40E_QINT_TQCTL_MSIX0_INDX_MASK
- I40E_QINT_TQCTL_MSIX0_INDX_SHIFT
- I40E_QINT_TQCTL_MSIX_INDX_MASK
- I40E_QINT_TQCTL_MSIX_INDX_SHIFT
- I40E_QINT_TQCTL_NEXTQ_INDX_MASK
- I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT
- I40E_QINT_TQCTL_NEXTQ_TYPE_MASK
- I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT
- I40E_QRX_ENA
- I40E_QRX_ENA_FAST_QDIS_MASK
- I40E_QRX_ENA_FAST_QDIS_SHIFT
- I40E_QRX_ENA_MAX_INDEX
- I40E_QRX_ENA_QENA_REQ_MASK
- I40E_QRX_ENA_QENA_REQ_SHIFT
- I40E_QRX_ENA_QENA_STAT_MASK
- I40E_QRX_ENA_QENA_STAT_SHIFT
- I40E_QRX_TAIL
- I40E_QRX_TAIL1
- I40E_QRX_TAIL1_MAX_INDEX
- I40E_QRX_TAIL1_TAIL_MASK
- I40E_QRX_TAIL1_TAIL_SHIFT
- I40E_QRX_TAIL_MAX_INDEX
- I40E_QRX_TAIL_TAIL_MASK
- I40E_QRX_TAIL_TAIL_SHIFT
- I40E_QTX_CTL
- I40E_QTX_CTL_MAX_INDEX
- I40E_QTX_CTL_PFVF_Q_MASK
- I40E_QTX_CTL_PFVF_Q_SHIFT
- I40E_QTX_CTL_PF_INDX_MASK
- I40E_QTX_CTL_PF_INDX_SHIFT
- I40E_QTX_CTL_PF_QUEUE
- I40E_QTX_CTL_VFVM_INDX_MASK
- I40E_QTX_CTL_VFVM_INDX_SHIFT
- I40E_QTX_CTL_VF_QUEUE
- I40E_QTX_CTL_VM_QUEUE
- I40E_QTX_ENA
- I40E_QTX_ENA_FAST_QDIS_MASK
- I40E_QTX_ENA_FAST_QDIS_SHIFT
- I40E_QTX_ENA_MAX_INDEX
- I40E_QTX_ENA_QENA_REQ_MASK
- I40E_QTX_ENA_QENA_REQ_SHIFT
- I40E_QTX_ENA_QENA_STAT_MASK
- I40E_QTX_ENA_QENA_STAT_SHIFT
- I40E_QTX_ENA_WAIT_COUNT
- I40E_QTX_HEAD
- I40E_QTX_HEAD_HEAD_MASK
- I40E_QTX_HEAD_HEAD_SHIFT
- I40E_QTX_HEAD_MAX_INDEX
- I40E_QTX_HEAD_RS_PENDING_MASK
- I40E_QTX_HEAD_RS_PENDING_SHIFT
- I40E_QTX_TAIL
- I40E_QTX_TAIL1
- I40E_QTX_TAIL1_MAX_INDEX
- I40E_QTX_TAIL1_TAIL_MASK
- I40E_QTX_TAIL1_TAIL_SHIFT
- I40E_QTX_TAIL_MAX_INDEX
- I40E_QTX_TAIL_TAIL_MASK
- I40E_QTX_TAIL_TAIL_SHIFT
- I40E_QUEUE_CTRL_DISABLE
- I40E_QUEUE_CTRL_DISABLECHECK
- I40E_QUEUE_CTRL_ENABLE
- I40E_QUEUE_CTRL_ENABLECHECK
- I40E_QUEUE_CTRL_FASTDISABLE
- I40E_QUEUE_CTRL_FASTDISABLECHECK
- I40E_QUEUE_CTRL_UNKNOWN
- I40E_QUEUE_END_OF_LIST
- I40E_QUEUE_INVALID_IDX
- I40E_QUEUE_STAT
- I40E_QUEUE_STATS_LEN
- I40E_QUEUE_TYPE_PE_AEQ
- I40E_QUEUE_TYPE_PE_CEQ
- I40E_QUEUE_TYPE_RX
- I40E_QUEUE_TYPE_TX
- I40E_QUEUE_TYPE_UNKNOWN
- I40E_QUEUE_WAIT_RETRY_LIMIT
- I40E_REG_MSS
- I40E_REG_MSS_MIN_MASK
- I40E_REQ_DESCRIPTOR_MULTIPLE
- I40E_RESET_CORER
- I40E_RESET_EMPR
- I40E_RESET_GLOBR
- I40E_RESET_POR
- I40E_RESOURCE_READ
- I40E_RESOURCE_WRITE
- I40E_RXBUFFER_1536
- I40E_RXBUFFER_2048
- I40E_RXBUFFER_256
- I40E_RXBUFFER_3072
- I40E_RXD_EOF
- I40E_RXD_QW1_ERROR_MASK
- I40E_RXD_QW1_ERROR_SHIFT
- I40E_RXD_QW1_LENGTH_HBUF_MASK
- I40E_RXD_QW1_LENGTH_HBUF_SHIFT
- I40E_RXD_QW1_LENGTH_PBUF_MASK
- I40E_RXD_QW1_LENGTH_PBUF_SHIFT
- I40E_RXD_QW1_LENGTH_SPH_MASK
- I40E_RXD_QW1_LENGTH_SPH_SHIFT
- I40E_RXD_QW1_PTYPE_MASK
- I40E_RXD_QW1_PTYPE_SHIFT
- I40E_RXD_QW1_STATUS_MASK
- I40E_RXD_QW1_STATUS_SHIFT
- I40E_RXD_QW1_STATUS_TSYNINDX_MASK
- I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT
- I40E_RXD_QW1_STATUS_TSYNVALID_MASK
- I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT
- I40E_RXQ_CTX_DBUFF_SHIFT
- I40E_RXQ_CTX_HBUFF_SHIFT
- I40E_RXR_FLAGS_BUILD_SKB_ENABLED
- I40E_RX_BUFFER_WRITE
- I40E_RX_DESC
- I40E_RX_DESC_ERROR_EIPE_SHIFT
- I40E_RX_DESC_ERROR_HBO_SHIFT
- I40E_RX_DESC_ERROR_IPE_SHIFT
- I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR
- I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN
- I40E_RX_DESC_ERROR_L3L4E_FC
- I40E_RX_DESC_ERROR_L3L4E_NONE
- I40E_RX_DESC_ERROR_L3L4E_PROT
- I40E_RX_DESC_ERROR_L3L4E_SHIFT
- I40E_RX_DESC_ERROR_L4E_SHIFT
- I40E_RX_DESC_ERROR_OVERSIZE_SHIFT
- I40E_RX_DESC_ERROR_PPRS_SHIFT
- I40E_RX_DESC_ERROR_RECIPE_SHIFT
- I40E_RX_DESC_ERROR_RXE_SHIFT
- I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT
- I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT
- I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT
- I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT
- I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT
- I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT
- I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT
- I40E_RX_DESC_FLTSTAT_NO_DATA
- I40E_RX_DESC_FLTSTAT_RSS_HASH
- I40E_RX_DESC_FLTSTAT_RSV
- I40E_RX_DESC_FLTSTAT_RSV_FD_ID
- I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT
- I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT
- I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT
- I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT
- I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT
- I40E_RX_DESC_PE_STATUS_PORTV_SHIFT
- I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT
- I40E_RX_DESC_PE_STATUS_QPID_SHIFT
- I40E_RX_DESC_PE_STATUS_URG_SHIFT
- I40E_RX_DESC_STATUS_CRCP_SHIFT
- I40E_RX_DESC_STATUS_DD_SHIFT
- I40E_RX_DESC_STATUS_EOF_SHIFT
- I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT
- I40E_RX_DESC_STATUS_FLM_SHIFT
- I40E_RX_DESC_STATUS_FLTSTAT_SHIFT
- I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT
- I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT
- I40E_RX_DESC_STATUS_L2TAG1P_SHIFT
- I40E_RX_DESC_STATUS_L3L4P_SHIFT
- I40E_RX_DESC_STATUS_LAST
- I40E_RX_DESC_STATUS_LPBK_SHIFT
- I40E_RX_DESC_STATUS_RESERVED_SHIFT
- I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
- I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
- I40E_RX_DESC_STATUS_UMBCAST_SHIFT
- I40E_RX_DMA_ATTR
- I40E_RX_DTYPE_HEADER_SPLIT
- I40E_RX_DTYPE_NO_SPLIT
- I40E_RX_DTYPE_SPLIT_ALWAYS
- I40E_RX_HDR_SIZE
- I40E_RX_INCREMENT
- I40E_RX_ITR
- I40E_RX_NEXT_DESC
- I40E_RX_NEXT_DESC_PREFETCH
- I40E_RX_PROG_STATUS_DESC_DD_SHIFT
- I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT
- I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS
- I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS
- I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT
- I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS
- I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT
- I40E_RX_PROG_STATUS_DESC_LENGTH
- I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT
- I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT
- I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT
- I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK
- I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT
- I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK
- I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT
- I40E_RX_PTYPE_FRAG
- I40E_RX_PTYPE_FRG
- I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
- I40E_RX_PTYPE_GRENAT4_MAC_PAY3
- I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
- I40E_RX_PTYPE_GRENAT6_MAC_PAY3
- I40E_RX_PTYPE_INNER_PROT_ICMP
- I40E_RX_PTYPE_INNER_PROT_NONE
- I40E_RX_PTYPE_INNER_PROT_SCTP
- I40E_RX_PTYPE_INNER_PROT_TCP
- I40E_RX_PTYPE_INNER_PROT_TIMESYNC
- I40E_RX_PTYPE_INNER_PROT_TS
- I40E_RX_PTYPE_INNER_PROT_UDP
- I40E_RX_PTYPE_L2_ARP
- I40E_RX_PTYPE_L2_EAPOL_PAY2
- I40E_RX_PTYPE_L2_ECP_PAY2
- I40E_RX_PTYPE_L2_EVB_PAY2
- I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3
- I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA
- I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3
- I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3
- I40E_RX_PTYPE_L2_FCOE_PAY3
- I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA
- I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER
- I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY
- I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP
- I40E_RX_PTYPE_L2_FCOE_VFT_PAY3
- I40E_RX_PTYPE_L2_FIP_PAY2
- I40E_RX_PTYPE_L2_LLDP_PAY2
- I40E_RX_PTYPE_L2_MACCNTRL_PAY2
- I40E_RX_PTYPE_L2_MAC_PAY2
- I40E_RX_PTYPE_L2_OUI_PAY2
- I40E_RX_PTYPE_L2_QCN_PAY2
- I40E_RX_PTYPE_L2_RESERVED
- I40E_RX_PTYPE_L2_TIMESYNC_PAY2
- I40E_RX_PTYPE_NOF
- I40E_RX_PTYPE_NOT_FRAG
- I40E_RX_PTYPE_OUTER_IP
- I40E_RX_PTYPE_OUTER_IPV4
- I40E_RX_PTYPE_OUTER_IPV6
- I40E_RX_PTYPE_OUTER_L2
- I40E_RX_PTYPE_OUTER_NONE
- I40E_RX_PTYPE_PAYLOAD_LAYER_NONE
- I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2
- I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3
- I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4
- I40E_RX_PTYPE_TUNNEL_END_IPV4
- I40E_RX_PTYPE_TUNNEL_END_IPV6
- I40E_RX_PTYPE_TUNNEL_END_NONE
- I40E_RX_PTYPE_TUNNEL_IP_GRENAT
- I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
- I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
- I40E_RX_PTYPE_TUNNEL_IP_IP
- I40E_RX_PTYPE_TUNNEL_NONE
- I40E_RX_SPLIT_IP
- I40E_RX_SPLIT_L2
- I40E_RX_SPLIT_SCTP
- I40E_RX_SPLIT_TCP_UDP
- I40E_SCTPIP_DUMMY_PACKET_LEN
- I40E_SD_TYPE_DIRECT
- I40E_SD_TYPE_INVALID
- I40E_SD_TYPE_PAGED
- I40E_SECTION_HEADER
- I40E_SECTION_TABLE
- I40E_SET_FC_AQ_FAIL_GET
- I40E_SET_FC_AQ_FAIL_NONE
- I40E_SET_FC_AQ_FAIL_SET
- I40E_SET_FC_AQ_FAIL_SET_UPDATE
- I40E_SET_FC_AQ_FAIL_UPDATE
- I40E_SET_PF_SD_ENTRY
- I40E_SKB_PAD
- I40E_SRRD_SRCTL_ATTEMPTS
- I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR
- I40E_SR_BOOT_CONFIG_PTR
- I40E_SR_CONTROL_WORD_1_MASK
- I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID
- I40E_SR_CONTROL_WORD_1_SHIFT
- I40E_SR_EMP_MODULE_PTR
- I40E_SR_EMP_SR_SETTINGS_PTR
- I40E_SR_LLDP_CFG_PTR
- I40E_SR_NVM_CONTROL_WORD
- I40E_SR_NVM_DEV_STARTER_VERSION
- I40E_SR_NVM_EETRACK_HI
- I40E_SR_NVM_EETRACK_LO
- I40E_SR_NVM_MAP_STRUCTURE_TYPE
- I40E_SR_NVM_OEM_VERSION_PTR
- I40E_SR_NVM_WAKE_ON_LAN
- I40E_SR_OCP_CFG_WORD0
- I40E_SR_OCP_ENABLED
- I40E_SR_PBA_BLOCK_PTR
- I40E_SR_PBA_FLAGS
- I40E_SR_PCIE_ALT_AUTO_LOAD_PTR
- I40E_SR_PCIE_ALT_MODULE_MAX_SIZE
- I40E_SR_SECTOR_SIZE_IN_WORDS
- I40E_SR_SW_CHECKSUM_BASE
- I40E_SR_SW_CHECKSUM_WORD
- I40E_SR_VPD_MODULE_MAX_SIZE
- I40E_SR_VPD_PTR
- I40E_SR_WORDS_IN_1KB
- I40E_STAT
- I40E_SUCCESS
- I40E_SWITCH_ELEMENT_TYPE_BMC
- I40E_SWITCH_ELEMENT_TYPE_EMP
- I40E_SWITCH_ELEMENT_TYPE_MAC
- I40E_SWITCH_ELEMENT_TYPE_PA
- I40E_SWITCH_ELEMENT_TYPE_PE
- I40E_SWITCH_ELEMENT_TYPE_PF
- I40E_SWITCH_ELEMENT_TYPE_VEB
- I40E_SWITCH_ELEMENT_TYPE_VF
- I40E_SWITCH_ELEMENT_TYPE_VSI
- I40E_SWITCH_MODE_MASK
- I40E_TCPIP_DUMMY_PACKET_LEN
- I40E_TEST_LEN
- I40E_TLV_STATUS_ERR
- I40E_TLV_STATUS_OPER
- I40E_TLV_STATUS_SYNC
- I40E_TLV_TYPE_END
- I40E_TLV_TYPE_ORG
- I40E_TRACE_NAME
- I40E_TRY_LINK_TIMEOUT
- I40E_TXD_CMD
- I40E_TXD_CTX_EIP_NOINC_IPID_CONST
- I40E_TXD_CTX_GRE_TUNNELING
- I40E_TXD_CTX_QW0_DECTTL_MASK
- I40E_TXD_CTX_QW0_DECTTL_SHIFT
- I40E_TXD_CTX_QW0_EIP_NOINC_MASK
- I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT
- I40E_TXD_CTX_QW0_EXT_IPLEN_MASK
- I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT
- I40E_TXD_CTX_QW0_EXT_IP_MASK
- I40E_TXD_CTX_QW0_EXT_IP_SHIFT
- I40E_TXD_CTX_QW0_L4T_CS_MASK
- I40E_TXD_CTX_QW0_L4T_CS_SHIFT
- I40E_TXD_CTX_QW0_NATLEN_MASK
- I40E_TXD_CTX_QW0_NATLEN_SHIFT
- I40E_TXD_CTX_QW0_NATT_MASK
- I40E_TXD_CTX_QW0_NATT_SHIFT
- I40E_TXD_CTX_QW1_CMD_MASK
- I40E_TXD_CTX_QW1_CMD_SHIFT
- I40E_TXD_CTX_QW1_DTYPE_MASK
- I40E_TXD_CTX_QW1_DTYPE_SHIFT
- I40E_TXD_CTX_QW1_MSS_MASK
- I40E_TXD_CTX_QW1_MSS_SHIFT
- I40E_TXD_CTX_QW1_TSO_LEN_MASK
- I40E_TXD_CTX_QW1_TSO_LEN_SHIFT
- I40E_TXD_CTX_QW1_VSI_MASK
- I40E_TXD_CTX_QW1_VSI_SHIFT
- I40E_TXD_CTX_UDP_TUNNELING
- I40E_TXD_FLTR_QW0_DEST_VSI_MASK
- I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT
- I40E_TXD_FLTR_QW0_FLEXOFF_MASK
- I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT
- I40E_TXD_FLTR_QW0_PCTYPE_MASK
- I40E_TXD_FLTR_QW0_PCTYPE_SHIFT
- I40E_TXD_FLTR_QW0_QINDEX_MASK
- I40E_TXD_FLTR_QW0_QINDEX_SHIFT
- I40E_TXD_FLTR_QW1_ATR_MASK
- I40E_TXD_FLTR_QW1_ATR_SHIFT
- I40E_TXD_FLTR_QW1_CMD_MASK
- I40E_TXD_FLTR_QW1_CMD_SHIFT
- I40E_TXD_FLTR_QW1_CNTINDEX_MASK
- I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT
- I40E_TXD_FLTR_QW1_CNT_ENA_MASK
- I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT
- I40E_TXD_FLTR_QW1_DEST_MASK
- I40E_TXD_FLTR_QW1_DEST_SHIFT
- I40E_TXD_FLTR_QW1_FD_STATUS_MASK
- I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT
- I40E_TXD_FLTR_QW1_PCMD_MASK
- I40E_TXD_FLTR_QW1_PCMD_SHIFT
- I40E_TXD_QW1_CMD_MASK
- I40E_TXD_QW1_CMD_SHIFT
- I40E_TXD_QW1_DTYPE_MASK
- I40E_TXD_QW1_DTYPE_SHIFT
- I40E_TXD_QW1_L2TAG1_MASK
- I40E_TXD_QW1_L2TAG1_SHIFT
- I40E_TXD_QW1_OFFSET_MASK
- I40E_TXD_QW1_OFFSET_SHIFT
- I40E_TXD_QW1_TX_BUF_SZ_MASK
- I40E_TXD_QW1_TX_BUF_SZ_SHIFT
- I40E_TXRX_COMMON_
- I40E_TXR_FLAGS_WB_ON_ITR
- I40E_TXR_FLAGS_XDP
- I40E_TX_CTXTDESC
- I40E_TX_CTX_DESC_IL2TAG2
- I40E_TX_CTX_DESC_IL2TAG2_IL2H
- I40E_TX_CTX_DESC_SWPE
- I40E_TX_CTX_DESC_SWTCH_LOCAL
- I40E_TX_CTX_DESC_SWTCH_NOTAG
- I40E_TX_CTX_DESC_SWTCH_UPLINK
- I40E_TX_CTX_DESC_SWTCH_VSI
- I40E_TX_CTX_DESC_TSO
- I40E_TX_CTX_DESC_TSYN
- I40E_TX_CTX_EXT_IP_IPV4
- I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM
- I40E_TX_CTX_EXT_IP_IPV6
- I40E_TX_CTX_EXT_IP_NONE
- I40E_TX_DESC
- I40E_TX_DESC_CMD_DUMMY
- I40E_TX_DESC_CMD_EOP
- I40E_TX_DESC_CMD_FCOET
- I40E_TX_DESC_CMD_ICRC
- I40E_TX_DESC_CMD_IIPT_IPV4
- I40E_TX_DESC_CMD_IIPT_IPV4_CSUM
- I40E_TX_DESC_CMD_IIPT_IPV6
- I40E_TX_DESC_CMD_IIPT_NONIP
- I40E_TX_DESC_CMD_IL2TAG1
- I40E_TX_DESC_CMD_L4T_EOFT_EOF_A
- I40E_TX_DESC_CMD_L4T_EOFT_EOF_N
- I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI
- I40E_TX_DESC_CMD_L4T_EOFT_EOF_T
- I40E_TX_DESC_CMD_L4T_EOFT_SCTP
- I40E_TX_DESC_CMD_L4T_EOFT_TCP
- I40E_TX_DESC_CMD_L4T_EOFT_UDP
- I40E_TX_DESC_CMD_L4T_EOFT_UNK
- I40E_TX_DESC_CMD_RS
- I40E_TX_DESC_DTYPE_CONTEXT
- I40E_TX_DESC_DTYPE_DATA
- I40E_TX_DESC_DTYPE_DDP_CTX
- I40E_TX_DESC_DTYPE_DESC_DONE
- I40E_TX_DESC_DTYPE_FCOE_CTX
- I40E_TX_DESC_DTYPE_FILTER_PROG
- I40E_TX_DESC_DTYPE_FLEX_CTX_1
- I40E_TX_DESC_DTYPE_FLEX_CTX_2
- I40E_TX_DESC_DTYPE_FLEX_DATA
- I40E_TX_DESC_DTYPE_NOP
- I40E_TX_DESC_LENGTH_IPLEN_SHIFT
- I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
- I40E_TX_DESC_LENGTH_MACLEN_SHIFT
- I40E_TX_FDIRDESC
- I40E_TX_FLAGS_FCCRC
- I40E_TX_FLAGS_FD_SB
- I40E_TX_FLAGS_FSO
- I40E_TX_FLAGS_HW_VLAN
- I40E_TX_FLAGS_IPV4
- I40E_TX_FLAGS_IPV6
- I40E_TX_FLAGS_NOTIFY_OTHER_EVENTS
- I40E_TX_FLAGS_SW_VLAN
- I40E_TX_FLAGS_TSO
- I40E_TX_FLAGS_TSYN
- I40E_TX_FLAGS_UDP_TUNNEL
- I40E_TX_FLAGS_VLAN_MASK
- I40E_TX_FLAGS_VLAN_PRIO_MASK
- I40E_TX_FLAGS_VLAN_PRIO_SHIFT
- I40E_TX_FLAGS_VLAN_SHIFT
- I40E_TX_ITR
- I40E_UDPIP_DUMMY_PACKET_LEN
- I40E_UDP_PORT_INDEX_UNUSED
- I40E_USERDEF_FLEX_FILTER
- I40E_USERDEF_FLEX_OFFSET
- I40E_USERDEF_FLEX_WORD
- I40E_VC_MAX_MAC_ADDR_PER_VF
- I40E_VC_MAX_VLAN_PER_VF
- I40E_VEB_STAT
- I40E_VEB_STATS_LEN
- I40E_VERIFY_TAG_MASK
- I40E_VERIFY_TAG_SHIFT
- I40E_VFCM_PE_ERRDATA
- I40E_VFCM_PE_ERRDATA1
- I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK
- I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT
- I40E_VFCM_PE_ERRDATA1_MAX_INDEX
- I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK
- I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT
- I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK
- I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT
- I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK
- I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT
- I40E_VFCM_PE_ERRDATA_Q_NUM_MASK
- I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT
- I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK
- I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT
- I40E_VFCM_PE_ERRINFO
- I40E_VFCM_PE_ERRINFO1
- I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT
- I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK
- I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT
- I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK
- I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT
- I40E_VFCM_PE_ERRINFO1_MAX_INDEX
- I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT
- I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT
- I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT
- I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK
- I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT
- I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK
- I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT
- I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT
- I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK
- I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT
- I40E_VFGEN_RSTAT
- I40E_VFGEN_RSTAT1
- I40E_VFGEN_RSTAT1_MAX_INDEX
- I40E_VFGEN_RSTAT1_VFR_STATE_MASK
- I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT
- I40E_VFGEN_RSTAT_VFR_STATE_MASK
- I40E_VFGEN_RSTAT_VFR_STATE_SHIFT
- I40E_VFINT_DYN_CTL0
- I40E_VFINT_DYN_CTL01
- I40E_VFINT_DYN_CTL01_CLEARPBA_MASK
- I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT
- I40E_VFINT_DYN_CTL01_INTENA_MASK
- I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK
- I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT
- I40E_VFINT_DYN_CTL01_INTENA_SHIFT
- I40E_VFINT_DYN_CTL01_INTERVAL_MASK
- I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT
- I40E_VFINT_DYN_CTL01_ITR_INDX_MASK
- I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK
- I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT
- I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK
- I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT
- I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK
- I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK
- I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT
- I40E_VFINT_DYN_CTL0_CLEARPBA_MASK
- I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT
- I40E_VFINT_DYN_CTL0_INTENA_MASK
- I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK
- I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT
- I40E_VFINT_DYN_CTL0_INTENA_SHIFT
- I40E_VFINT_DYN_CTL0_INTERVAL_MASK
- I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT
- I40E_VFINT_DYN_CTL0_ITR_INDX_MASK
- I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTL0_MAX_INDEX
- I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK
- I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT
- I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK
- I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT
- I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK
- I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK
- I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT
- I40E_VFINT_DYN_CTLN
- I40E_VFINT_DYN_CTLN1
- I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK
- I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT
- I40E_VFINT_DYN_CTLN1_INTENA_MASK
- I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK
- I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT
- I40E_VFINT_DYN_CTLN1_INTENA_SHIFT
- I40E_VFINT_DYN_CTLN1_INTERVAL_MASK
- I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT
- I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK
- I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTLN1_MAX_INDEX
- I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK
- I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT
- I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
- I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT
- I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK
- I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK
- I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT
- I40E_VFINT_DYN_CTLN_CLEARPBA_MASK
- I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT
- I40E_VFINT_DYN_CTLN_INTENA_MASK
- I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK
- I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT
- I40E_VFINT_DYN_CTLN_INTENA_SHIFT
- I40E_VFINT_DYN_CTLN_INTERVAL_MASK
- I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT
- I40E_VFINT_DYN_CTLN_ITR_INDX_MASK
- I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTLN_MAX_INDEX
- I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK
- I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT
- I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK
- I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT
- I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK
- I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT
- I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK
- I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT
- I40E_VFINT_ICR0
- I40E_VFINT_ICR01
- I40E_VFINT_ICR01_ADMINQ_MASK
- I40E_VFINT_ICR01_ADMINQ_SHIFT
- I40E_VFINT_ICR01_INTEVENT_MASK
- I40E_VFINT_ICR01_INTEVENT_SHIFT
- I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK
- I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT
- I40E_VFINT_ICR01_QUEUE_0_MASK
- I40E_VFINT_ICR01_QUEUE_0_SHIFT
- I40E_VFINT_ICR01_QUEUE_1_MASK
- I40E_VFINT_ICR01_QUEUE_1_SHIFT
- I40E_VFINT_ICR01_QUEUE_2_MASK
- I40E_VFINT_ICR01_QUEUE_2_SHIFT
- I40E_VFINT_ICR01_QUEUE_3_MASK
- I40E_VFINT_ICR01_QUEUE_3_SHIFT
- I40E_VFINT_ICR01_SWINT_MASK
- I40E_VFINT_ICR01_SWINT_SHIFT
- I40E_VFINT_ICR0_ADMINQ_MASK
- I40E_VFINT_ICR0_ADMINQ_SHIFT
- I40E_VFINT_ICR0_ENA
- I40E_VFINT_ICR0_ENA1
- I40E_VFINT_ICR0_ENA1_ADMINQ_MASK
- I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT
- I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK
- I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT
- I40E_VFINT_ICR0_ENA1_RSVD_MASK
- I40E_VFINT_ICR0_ENA1_RSVD_SHIFT
- I40E_VFINT_ICR0_ENA_ADMINQ_MASK
- I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT
- I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK
- I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT
- I40E_VFINT_ICR0_ENA_MAX_INDEX
- I40E_VFINT_ICR0_ENA_RSVD_MASK
- I40E_VFINT_ICR0_ENA_RSVD_SHIFT
- I40E_VFINT_ICR0_INTEVENT_MASK
- I40E_VFINT_ICR0_INTEVENT_SHIFT
- I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK
- I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT
- I40E_VFINT_ICR0_MAX_INDEX
- I40E_VFINT_ICR0_QUEUE_0_MASK
- I40E_VFINT_ICR0_QUEUE_0_SHIFT
- I40E_VFINT_ICR0_QUEUE_1_MASK
- I40E_VFINT_ICR0_QUEUE_1_SHIFT
- I40E_VFINT_ICR0_QUEUE_2_MASK
- I40E_VFINT_ICR0_QUEUE_2_SHIFT
- I40E_VFINT_ICR0_QUEUE_3_MASK
- I40E_VFINT_ICR0_QUEUE_3_SHIFT
- I40E_VFINT_ICR0_SWINT_MASK
- I40E_VFINT_ICR0_SWINT_SHIFT
- I40E_VFINT_ITR0
- I40E_VFINT_ITR01
- I40E_VFINT_ITR01_INTERVAL_MASK
- I40E_VFINT_ITR01_INTERVAL_SHIFT
- I40E_VFINT_ITR01_MAX_INDEX
- I40E_VFINT_ITR0_INTERVAL_MASK
- I40E_VFINT_ITR0_INTERVAL_SHIFT
- I40E_VFINT_ITR0_MAX_INDEX
- I40E_VFINT_ITRN
- I40E_VFINT_ITRN1
- I40E_VFINT_ITRN1_INTERVAL_MASK
- I40E_VFINT_ITRN1_INTERVAL_SHIFT
- I40E_VFINT_ITRN1_MAX_INDEX
- I40E_VFINT_ITRN_INTERVAL_MASK
- I40E_VFINT_ITRN_INTERVAL_SHIFT
- I40E_VFINT_ITRN_MAX_INDEX
- I40E_VFINT_STAT_CTL0
- I40E_VFINT_STAT_CTL01
- I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK
- I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT
- I40E_VFINT_STAT_CTL0_MAX_INDEX
- I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK
- I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT
- I40E_VFMSIX_PBA
- I40E_VFMSIX_PBA1
- I40E_VFMSIX_PBA1_MAX_INDEX
- I40E_VFMSIX_PBA1_PENBIT_MASK
- I40E_VFMSIX_PBA1_PENBIT_SHIFT
- I40E_VFMSIX_PBA_PENBIT_MASK
- I40E_VFMSIX_PBA_PENBIT_SHIFT
- I40E_VFMSIX_TADD
- I40E_VFMSIX_TADD1
- I40E_VFMSIX_TADD1_MAX_INDEX
- I40E_VFMSIX_TADD1_MSIXTADD10_MASK
- I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT
- I40E_VFMSIX_TADD1_MSIXTADD_MASK
- I40E_VFMSIX_TADD1_MSIXTADD_SHIFT
- I40E_VFMSIX_TADD_MAX_INDEX
- I40E_VFMSIX_TADD_MSIXTADD10_MASK
- I40E_VFMSIX_TADD_MSIXTADD10_SHIFT
- I40E_VFMSIX_TADD_MSIXTADD_MASK
- I40E_VFMSIX_TADD_MSIXTADD_SHIFT
- I40E_VFMSIX_TMSG
- I40E_VFMSIX_TMSG1
- I40E_VFMSIX_TMSG1_MAX_INDEX
- I40E_VFMSIX_TMSG1_MSIXTMSG_MASK
- I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT
- I40E_VFMSIX_TMSG_MAX_INDEX
- I40E_VFMSIX_TMSG_MSIXTMSG_MASK
- I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT
- I40E_VFMSIX_TUADD
- I40E_VFMSIX_TUADD1
- I40E_VFMSIX_TUADD1_MAX_INDEX
- I40E_VFMSIX_TUADD1_MSIXTUADD_MASK
- I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT
- I40E_VFMSIX_TUADD_MAX_INDEX
- I40E_VFMSIX_TUADD_MSIXTUADD_MASK
- I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT
- I40E_VFMSIX_TVCTRL
- I40E_VFMSIX_TVCTRL1
- I40E_VFMSIX_TVCTRL1_MASK_MASK
- I40E_VFMSIX_TVCTRL1_MASK_SHIFT
- I40E_VFMSIX_TVCTRL1_MAX_INDEX
- I40E_VFMSIX_TVCTRL_MASK_MASK
- I40E_VFMSIX_TVCTRL_MASK_SHIFT
- I40E_VFMSIX_TVCTRL_MAX_INDEX
- I40E_VFPE_AEQALLOC
- I40E_VFPE_AEQALLOC1
- I40E_VFPE_AEQALLOC1_AECOUNT_MASK
- I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT
- I40E_VFPE_AEQALLOC_AECOUNT_MASK
- I40E_VFPE_AEQALLOC_AECOUNT_SHIFT
- I40E_VFPE_AEQALLOC_MAX_INDEX
- I40E_VFPE_CCQPHIGH
- I40E_VFPE_CCQPHIGH1
- I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK
- I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT
- I40E_VFPE_CCQPHIGH_MAX_INDEX
- I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK
- I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT
- I40E_VFPE_CCQPLOW
- I40E_VFPE_CCQPLOW1
- I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK
- I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT
- I40E_VFPE_CCQPLOW_MAX_INDEX
- I40E_VFPE_CCQPLOW_PECCQPLOW_MASK
- I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT
- I40E_VFPE_CCQPSTATUS
- I40E_VFPE_CCQPSTATUS1
- I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK
- I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT
- I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK
- I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT
- I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK
- I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT
- I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK
- I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT
- I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK
- I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT
- I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK
- I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT
- I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK
- I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT
- I40E_VFPE_CCQPSTATUS_MAX_INDEX
- I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK
- I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT
- I40E_VFPE_CQACK
- I40E_VFPE_CQACK1
- I40E_VFPE_CQACK1_PECQID_MASK
- I40E_VFPE_CQACK1_PECQID_SHIFT
- I40E_VFPE_CQACK_MAX_INDEX
- I40E_VFPE_CQACK_PECQID_MASK
- I40E_VFPE_CQACK_PECQID_SHIFT
- I40E_VFPE_CQARM
- I40E_VFPE_CQARM1
- I40E_VFPE_CQARM1_PECQID_MASK
- I40E_VFPE_CQARM1_PECQID_SHIFT
- I40E_VFPE_CQARM_MAX_INDEX
- I40E_VFPE_CQARM_PECQID_MASK
- I40E_VFPE_CQARM_PECQID_SHIFT
- I40E_VFPE_CQPDB
- I40E_VFPE_CQPDB1
- I40E_VFPE_CQPDB1_WQHEAD_MASK
- I40E_VFPE_CQPDB1_WQHEAD_SHIFT
- I40E_VFPE_CQPDB_MAX_INDEX
- I40E_VFPE_CQPDB_WQHEAD_MASK
- I40E_VFPE_CQPDB_WQHEAD_SHIFT
- I40E_VFPE_CQPERRCODES
- I40E_VFPE_CQPERRCODES1
- I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK
- I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT
- I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK
- I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT
- I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK
- I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT
- I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK
- I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT
- I40E_VFPE_CQPERRCODES_MAX_INDEX
- I40E_VFPE_CQPTAIL
- I40E_VFPE_CQPTAIL1
- I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK
- I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT
- I40E_VFPE_CQPTAIL1_WQTAIL_MASK
- I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT
- I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK
- I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT
- I40E_VFPE_CQPTAIL_MAX_INDEX
- I40E_VFPE_CQPTAIL_WQTAIL_MASK
- I40E_VFPE_CQPTAIL_WQTAIL_SHIFT
- I40E_VFPE_IPCONFIG0
- I40E_VFPE_IPCONFIG01
- I40E_VFPE_IPCONFIG01_PEIPID_MASK
- I40E_VFPE_IPCONFIG01_PEIPID_SHIFT
- I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK
- I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT
- I40E_VFPE_IPCONFIG0_MAX_INDEX
- I40E_VFPE_IPCONFIG0_PEIPID_MASK
- I40E_VFPE_IPCONFIG0_PEIPID_SHIFT
- I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK
- I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT
- I40E_VFPE_MRTEIDXMASK
- I40E_VFPE_MRTEIDXMASK1
- I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK
- I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT
- I40E_VFPE_MRTEIDXMASK_MAX_INDEX
- I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK
- I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT
- I40E_VFPE_RCVUNEXPECTEDERROR
- I40E_VFPE_RCVUNEXPECTEDERROR1
- I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK
- I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT
- I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX
- I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK
- I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT
- I40E_VFPE_TCPNOWTIMER
- I40E_VFPE_TCPNOWTIMER1
- I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK
- I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT
- I40E_VFPE_TCPNOWTIMER_MAX_INDEX
- I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK
- I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT
- I40E_VFPE_WQEALLOC
- I40E_VFPE_WQEALLOC1
- I40E_VFPE_WQEALLOC1_PEQPID_MASK
- I40E_VFPE_WQEALLOC1_PEQPID_SHIFT
- I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK
- I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT
- I40E_VFPE_WQEALLOC_MAX_INDEX
- I40E_VFPE_WQEALLOC_PEQPID_MASK
- I40E_VFPE_WQEALLOC_PEQPID_SHIFT
- I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK
- I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT
- I40E_VFQF_HENA
- I40E_VFQF_HENA1
- I40E_VFQF_HENA1_MAX_INDEX
- I40E_VFQF_HENA1_PTYPE_ENA_MASK
- I40E_VFQF_HENA1_PTYPE_ENA_SHIFT
- I40E_VFQF_HENA_MAX_INDEX
- I40E_VFQF_HENA_PTYPE_ENA_MASK
- I40E_VFQF_HENA_PTYPE_ENA_SHIFT
- I40E_VFQF_HKEY
- I40E_VFQF_HKEY1
- I40E_VFQF_HKEY1_KEY_0_MASK
- I40E_VFQF_HKEY1_KEY_0_SHIFT
- I40E_VFQF_HKEY1_KEY_1_MASK
- I40E_VFQF_HKEY1_KEY_1_SHIFT
- I40E_VFQF_HKEY1_KEY_2_MASK
- I40E_VFQF_HKEY1_KEY_2_SHIFT
- I40E_VFQF_HKEY1_KEY_3_MASK
- I40E_VFQF_HKEY1_KEY_3_SHIFT
- I40E_VFQF_HKEY1_MAX_INDEX
- I40E_VFQF_HKEY_KEY_0_MASK
- I40E_VFQF_HKEY_KEY_0_SHIFT
- I40E_VFQF_HKEY_KEY_1_MASK
- I40E_VFQF_HKEY_KEY_1_SHIFT
- I40E_VFQF_HKEY_KEY_2_MASK
- I40E_VFQF_HKEY_KEY_2_SHIFT
- I40E_VFQF_HKEY_KEY_3_MASK
- I40E_VFQF_HKEY_KEY_3_SHIFT
- I40E_VFQF_HKEY_MAX_INDEX
- I40E_VFQF_HLUT
- I40E_VFQF_HLUT1
- I40E_VFQF_HLUT1_LUT0_MASK
- I40E_VFQF_HLUT1_LUT0_SHIFT
- I40E_VFQF_HLUT1_LUT1_MASK
- I40E_VFQF_HLUT1_LUT1_SHIFT
- I40E_VFQF_HLUT1_LUT2_MASK
- I40E_VFQF_HLUT1_LUT2_SHIFT
- I40E_VFQF_HLUT1_LUT3_MASK
- I40E_VFQF_HLUT1_LUT3_SHIFT
- I40E_VFQF_HLUT1_MAX_INDEX
- I40E_VFQF_HLUT_LUT0_MASK
- I40E_VFQF_HLUT_LUT0_SHIFT
- I40E_VFQF_HLUT_LUT1_MASK
- I40E_VFQF_HLUT_LUT1_SHIFT
- I40E_VFQF_HLUT_LUT2_MASK
- I40E_VFQF_HLUT_LUT2_SHIFT
- I40E_VFQF_HLUT_LUT3_MASK
- I40E_VFQF_HLUT_LUT3_SHIFT
- I40E_VFQF_HLUT_MAX_INDEX
- I40E_VFQF_HREGION
- I40E_VFQF_HREGION1
- I40E_VFQF_HREGION1_MAX_INDEX
- I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT
- I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK
- I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT
- I40E_VFQF_HREGION1_REGION_0_MASK
- I40E_VFQF_HREGION1_REGION_0_SHIFT
- I40E_VFQF_HREGION1_REGION_1_MASK
- I40E_VFQF_HREGION1_REGION_1_SHIFT
- I40E_VFQF_HREGION1_REGION_2_MASK
- I40E_VFQF_HREGION1_REGION_2_SHIFT
- I40E_VFQF_HREGION1_REGION_3_MASK
- I40E_VFQF_HREGION1_REGION_3_SHIFT
- I40E_VFQF_HREGION1_REGION_4_MASK
- I40E_VFQF_HREGION1_REGION_4_SHIFT
- I40E_VFQF_HREGION1_REGION_5_MASK
- I40E_VFQF_HREGION1_REGION_5_SHIFT
- I40E_VFQF_HREGION1_REGION_6_MASK
- I40E_VFQF_HREGION1_REGION_6_SHIFT
- I40E_VFQF_HREGION1_REGION_7_MASK
- I40E_VFQF_HREGION1_REGION_7_SHIFT
- I40E_VFQF_HREGION_MAX_INDEX
- I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT
- I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK
- I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT
- I40E_VFQF_HREGION_REGION_0_MASK
- I40E_VFQF_HREGION_REGION_0_SHIFT
- I40E_VFQF_HREGION_REGION_1_MASK
- I40E_VFQF_HREGION_REGION_1_SHIFT
- I40E_VFQF_HREGION_REGION_2_MASK
- I40E_VFQF_HREGION_REGION_2_SHIFT
- I40E_VFQF_HREGION_REGION_3_MASK
- I40E_VFQF_HREGION_REGION_3_SHIFT
- I40E_VFQF_HREGION_REGION_4_MASK
- I40E_VFQF_HREGION_REGION_4_SHIFT
- I40E_VFQF_HREGION_REGION_5_MASK
- I40E_VFQF_HREGION_REGION_5_SHIFT
- I40E_VFQF_HREGION_REGION_6_MASK
- I40E_VFQF_HREGION_REGION_6_SHIFT
- I40E_VFQF_HREGION_REGION_7_MASK
- I40E_VFQF_HREGION_REGION_7_SHIFT
- I40E_VF_ARQBAH
- I40E_VF_ARQBAH1
- I40E_VF_ARQBAH1_ARQBAH_MASK
- I40E_VF_ARQBAH1_ARQBAH_SHIFT
- I40E_VF_ARQBAH_ARQBAH_MASK
- I40E_VF_ARQBAH_ARQBAH_SHIFT
- I40E_VF_ARQBAH_MAX_INDEX
- I40E_VF_ARQBAL
- I40E_VF_ARQBAL1
- I40E_VF_ARQBAL1_ARQBAL_MASK
- I40E_VF_ARQBAL1_ARQBAL_SHIFT
- I40E_VF_ARQBAL_ARQBAL_MASK
- I40E_VF_ARQBAL_ARQBAL_SHIFT
- I40E_VF_ARQBAL_MAX_INDEX
- I40E_VF_ARQH
- I40E_VF_ARQH1
- I40E_VF_ARQH1_ARQH_MASK
- I40E_VF_ARQH1_ARQH_SHIFT
- I40E_VF_ARQH_ARQH_MASK
- I40E_VF_ARQH_ARQH_SHIFT
- I40E_VF_ARQH_MAX_INDEX
- I40E_VF_ARQLEN
- I40E_VF_ARQLEN1
- I40E_VF_ARQLEN1_ARQCRIT_MASK
- I40E_VF_ARQLEN1_ARQCRIT_SHIFT
- I40E_VF_ARQLEN1_ARQENABLE_MASK
- I40E_VF_ARQLEN1_ARQENABLE_SHIFT
- I40E_VF_ARQLEN1_ARQLEN_MASK
- I40E_VF_ARQLEN1_ARQLEN_SHIFT
- I40E_VF_ARQLEN1_ARQOVFL_MASK
- I40E_VF_ARQLEN1_ARQOVFL_SHIFT
- I40E_VF_ARQLEN1_ARQVFE_MASK
- I40E_VF_ARQLEN1_ARQVFE_SHIFT
- I40E_VF_ARQLEN_ARQCRIT_MASK
- I40E_VF_ARQLEN_ARQCRIT_SHIFT
- I40E_VF_ARQLEN_ARQENABLE_MASK
- I40E_VF_ARQLEN_ARQENABLE_SHIFT
- I40E_VF_ARQLEN_ARQLEN_MASK
- I40E_VF_ARQLEN_ARQLEN_SHIFT
- I40E_VF_ARQLEN_ARQOVFL_MASK
- I40E_VF_ARQLEN_ARQOVFL_SHIFT
- I40E_VF_ARQLEN_ARQVFE_MASK
- I40E_VF_ARQLEN_ARQVFE_SHIFT
- I40E_VF_ARQLEN_MAX_INDEX
- I40E_VF_ARQT
- I40E_VF_ARQT1
- I40E_VF_ARQT1_ARQT_MASK
- I40E_VF_ARQT1_ARQT_SHIFT
- I40E_VF_ARQT_ARQT_MASK
- I40E_VF_ARQT_ARQT_SHIFT
- I40E_VF_ARQT_MAX_INDEX
- I40E_VF_ATQBAH
- I40E_VF_ATQBAH1
- I40E_VF_ATQBAH1_ATQBAH_MASK
- I40E_VF_ATQBAH1_ATQBAH_SHIFT
- I40E_VF_ATQBAH_ATQBAH_MASK
- I40E_VF_ATQBAH_ATQBAH_SHIFT
- I40E_VF_ATQBAH_MAX_INDEX
- I40E_VF_ATQBAL
- I40E_VF_ATQBAL1
- I40E_VF_ATQBAL1_ATQBAL_MASK
- I40E_VF_ATQBAL1_ATQBAL_SHIFT
- I40E_VF_ATQBAL_ATQBAL_MASK
- I40E_VF_ATQBAL_ATQBAL_SHIFT
- I40E_VF_ATQBAL_MAX_INDEX
- I40E_VF_ATQH
- I40E_VF_ATQH1
- I40E_VF_ATQH1_ATQH_MASK
- I40E_VF_ATQH1_ATQH_SHIFT
- I40E_VF_ATQH_ATQH_MASK
- I40E_VF_ATQH_ATQH_SHIFT
- I40E_VF_ATQH_MAX_INDEX
- I40E_VF_ATQLEN
- I40E_VF_ATQLEN1
- I40E_VF_ATQLEN1_ATQCRIT_MASK
- I40E_VF_ATQLEN1_ATQCRIT_SHIFT
- I40E_VF_ATQLEN1_ATQENABLE_MASK
- I40E_VF_ATQLEN1_ATQENABLE_SHIFT
- I40E_VF_ATQLEN1_ATQLEN_MASK
- I40E_VF_ATQLEN1_ATQLEN_SHIFT
- I40E_VF_ATQLEN1_ATQOVFL_MASK
- I40E_VF_ATQLEN1_ATQOVFL_SHIFT
- I40E_VF_ATQLEN1_ATQVFE_MASK
- I40E_VF_ATQLEN1_ATQVFE_SHIFT
- I40E_VF_ATQLEN_ATQCRIT_MASK
- I40E_VF_ATQLEN_ATQCRIT_SHIFT
- I40E_VF_ATQLEN_ATQENABLE_MASK
- I40E_VF_ATQLEN_ATQENABLE_SHIFT
- I40E_VF_ATQLEN_ATQLEN_MASK
- I40E_VF_ATQLEN_ATQLEN_SHIFT
- I40E_VF_ATQLEN_ATQOVFL_MASK
- I40E_VF_ATQLEN_ATQOVFL_SHIFT
- I40E_VF_ATQLEN_ATQVFE_MASK
- I40E_VF_ATQLEN_ATQVFE_SHIFT
- I40E_VF_ATQLEN_MAX_INDEX
- I40E_VF_ATQT
- I40E_VF_ATQT1
- I40E_VF_ATQT1_ATQT_MASK
- I40E_VF_ATQT1_ATQT_SHIFT
- I40E_VF_ATQT_ATQT_MASK
- I40E_VF_ATQT_ATQT_SHIFT
- I40E_VF_ATQT_MAX_INDEX
- I40E_VF_HLUT_ARRAY_SIZE
- I40E_VF_STATE_ACTIVE
- I40E_VF_STATE_DISABLED
- I40E_VF_STATE_INIT
- I40E_VF_STATE_IWARPENA
- I40E_VF_STATE_MC_PROMISC
- I40E_VF_STATE_PRE_ENABLE
- I40E_VF_STATE_UC_PROMISC
- I40E_VIRTCHNL_SUPPORTED_QTYPES
- I40E_VIRTCHNL_VF_CAP_IWARP
- I40E_VIRTCHNL_VF_CAP_L2
- I40E_VIRTCHNL_VF_CAP_PRIVILEGE
- I40E_VLAN_ANY
- I40E_VLAN_MASK
- I40E_VLAN_PRIORITY_SHIFT
- I40E_VPGEN_VFRSTAT
- I40E_VPGEN_VFRSTAT_MAX_INDEX
- I40E_VPGEN_VFRSTAT_VFRD_MASK
- I40E_VPGEN_VFRSTAT_VFRD_SHIFT
- I40E_VPGEN_VFRTRIG
- I40E_VPGEN_VFRTRIG_MAX_INDEX
- I40E_VPGEN_VFRTRIG_VFSWR_MASK
- I40E_VPGEN_VFRTRIG_VFSWR_SHIFT
- I40E_VPINT_AEQCTL
- I40E_VPINT_AEQCTL_CAUSE_ENA_MASK
- I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT
- I40E_VPINT_AEQCTL_INTEVENT_MASK
- I40E_VPINT_AEQCTL_INTEVENT_SHIFT
- I40E_VPINT_AEQCTL_ITR_INDX_MASK
- I40E_VPINT_AEQCTL_ITR_INDX_SHIFT
- I40E_VPINT_AEQCTL_MAX_INDEX
- I40E_VPINT_AEQCTL_MSIX0_INDX_MASK
- I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT
- I40E_VPINT_AEQCTL_MSIX_INDX_MASK
- I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT
- I40E_VPINT_CEQCTL
- I40E_VPINT_CEQCTL_CAUSE_ENA_MASK
- I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT
- I40E_VPINT_CEQCTL_INTEVENT_MASK
- I40E_VPINT_CEQCTL_INTEVENT_SHIFT
- I40E_VPINT_CEQCTL_ITR_INDX_MASK
- I40E_VPINT_CEQCTL_ITR_INDX_SHIFT
- I40E_VPINT_CEQCTL_MAX_INDEX
- I40E_VPINT_CEQCTL_MSIX0_INDX_MASK
- I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT
- I40E_VPINT_CEQCTL_MSIX_INDX_MASK
- I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT
- I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK
- I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT
- I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK
- I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT
- I40E_VPINT_LNKLST0
- I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK
- I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT
- I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK
- I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT
- I40E_VPINT_LNKLST0_MAX_INDEX
- I40E_VPINT_LNKLSTN
- I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK
- I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT
- I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK
- I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT
- I40E_VPINT_LNKLSTN_MAX_INDEX
- I40E_VPINT_RATE0
- I40E_VPINT_RATE0_INTERVAL_MASK
- I40E_VPINT_RATE0_INTERVAL_SHIFT
- I40E_VPINT_RATE0_INTRL_ENA_MASK
- I40E_VPINT_RATE0_INTRL_ENA_SHIFT
- I40E_VPINT_RATE0_MAX_INDEX
- I40E_VPINT_RATEN
- I40E_VPINT_RATEN_INTERVAL_MASK
- I40E_VPINT_RATEN_INTERVAL_SHIFT
- I40E_VPINT_RATEN_INTRL_ENA_MASK
- I40E_VPINT_RATEN_INTRL_ENA_SHIFT
- I40E_VPINT_RATEN_MAX_INDEX
- I40E_VPLAN_MAPENA
- I40E_VPLAN_MAPENA_MAX_INDEX
- I40E_VPLAN_MAPENA_TXRX_ENA_MASK
- I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT
- I40E_VPLAN_QBASE
- I40E_VPLAN_QBASE_MAX_INDEX
- I40E_VPLAN_QBASE_VFFIRSTQ_MASK
- I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT
- I40E_VPLAN_QBASE_VFNUMQ_MASK
- I40E_VPLAN_QBASE_VFNUMQ_SHIFT
- I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK
- I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT
- I40E_VPLAN_QTABLE
- I40E_VPLAN_QTABLE_MAX_INDEX
- I40E_VPLAN_QTABLE_QINDEX_MASK
- I40E_VPLAN_QTABLE_QINDEX_SHIFT
- I40E_VPQF_CTL
- I40E_VPQF_CTL_FCDSIZE_MASK
- I40E_VPQF_CTL_FCDSIZE_SHIFT
- I40E_VPQF_CTL_FCHSIZE_MASK
- I40E_VPQF_CTL_FCHSIZE_SHIFT
- I40E_VPQF_CTL_MAX_INDEX
- I40E_VPQF_CTL_PEDSIZE_MASK
- I40E_VPQF_CTL_PEDSIZE_SHIFT
- I40E_VPQF_CTL_PEHSIZE_MASK
- I40E_VPQF_CTL_PEHSIZE_SHIFT
- I40E_VP_MDET_RX
- I40E_VP_MDET_RX_MAX_INDEX
- I40E_VP_MDET_RX_VALID_MASK
- I40E_VP_MDET_RX_VALID_SHIFT
- I40E_VP_MDET_TX
- I40E_VP_MDET_TX_MAX_INDEX
- I40E_VP_MDET_TX_VALID_MASK
- I40E_VP_MDET_TX_VALID_SHIFT
- I40E_VSIGEN_RSTAT
- I40E_VSIGEN_RSTAT_MAX_INDEX
- I40E_VSIGEN_RSTAT_VMRD_MASK
- I40E_VSIGEN_RSTAT_VMRD_SHIFT
- I40E_VSIGEN_RTRIG
- I40E_VSIGEN_RTRIG_MAX_INDEX
- I40E_VSIGEN_RTRIG_VMSWR_MASK
- I40E_VSIGEN_RTRIG_VMSWR_SHIFT
- I40E_VSILAN_QBASE
- I40E_VSILAN_QBASE_MAX_INDEX
- I40E_VSILAN_QBASE_VSIBASE_MASK
- I40E_VSILAN_QBASE_VSIBASE_SHIFT
- I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK
- I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT
- I40E_VSILAN_QTABLE
- I40E_VSILAN_QTABLE_MAX_INDEX
- I40E_VSILAN_QTABLE_QINDEX_0_MASK
- I40E_VSILAN_QTABLE_QINDEX_0_SHIFT
- I40E_VSILAN_QTABLE_QINDEX_1_MASK
- I40E_VSILAN_QTABLE_QINDEX_1_SHIFT
- I40E_VSIQF_CTL
- I40E_VSIQF_CTL_FCOE_ENA_MASK
- I40E_VSIQF_CTL_FCOE_ENA_SHIFT
- I40E_VSIQF_CTL_MAX_INDEX
- I40E_VSIQF_CTL_PEMFRAG_ENA_MASK
- I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT
- I40E_VSIQF_CTL_PEMUDP_ENA_MASK
- I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT
- I40E_VSIQF_CTL_PETCP_ENA_MASK
- I40E_VSIQF_CTL_PETCP_ENA_SHIFT
- I40E_VSIQF_CTL_PEUFRAG_ENA_MASK
- I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT
- I40E_VSIQF_CTL_PEUUDP_ENA_MASK
- I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT
- I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK
- I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT
- I40E_VSIQF_HKEY
- I40E_VSIQF_HKEY_KEY_0_MASK
- I40E_VSIQF_HKEY_KEY_0_SHIFT
- I40E_VSIQF_HKEY_KEY_1_MASK
- I40E_VSIQF_HKEY_KEY_1_SHIFT
- I40E_VSIQF_HKEY_KEY_2_MASK
- I40E_VSIQF_HKEY_KEY_2_SHIFT
- I40E_VSIQF_HKEY_KEY_3_MASK
- I40E_VSIQF_HKEY_KEY_3_SHIFT
- I40E_VSIQF_HKEY_MAX_INDEX
- I40E_VSIQF_HLUT
- I40E_VSIQF_HLUT_LUT0_MASK
- I40E_VSIQF_HLUT_LUT0_SHIFT
- I40E_VSIQF_HLUT_LUT1_MASK
- I40E_VSIQF_HLUT_LUT1_SHIFT
- I40E_VSIQF_HLUT_LUT2_MASK
- I40E_VSIQF_HLUT_LUT2_SHIFT
- I40E_VSIQF_HLUT_LUT3_MASK
- I40E_VSIQF_HLUT_LUT3_SHIFT
- I40E_VSIQF_HLUT_MAX_INDEX
- I40E_VSIQF_TCREGION
- I40E_VSIQF_TCREGION_MAX_INDEX
- I40E_VSIQF_TCREGION_TC_OFFSET2_MASK
- I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT
- I40E_VSIQF_TCREGION_TC_OFFSET_MASK
- I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT
- I40E_VSIQF_TCREGION_TC_SIZE2_MASK
- I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT
- I40E_VSIQF_TCREGION_TC_SIZE_MASK
- I40E_VSIQF_TCREGION_TC_SIZE_SHIFT
- I40E_VSI_CTRL
- I40E_VSI_FCOE
- I40E_VSI_FDIR
- I40E_VSI_FLAG_FILTER_CHANGED
- I40E_VSI_FLAG_VEB_OWNER
- I40E_VSI_IWARP
- I40E_VSI_MAIN
- I40E_VSI_MIRROR
- I40E_VSI_SRIOV
- I40E_VSI_STAT
- I40E_VSI_STATS_LEN
- I40E_VSI_TYPE_UNKNOWN
- I40E_VSI_VMDQ1
- I40E_VSI_VMDQ2
- I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK
- I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK
- I40E_X722_PFQF_HLUT
- I40E_X722_PFQF_HLUT_LUT0_MASK
- I40E_X722_PFQF_HLUT_LUT0_SHIFT
- I40E_X722_PFQF_HLUT_LUT1_MASK
- I40E_X722_PFQF_HLUT_LUT1_SHIFT
- I40E_X722_PFQF_HLUT_LUT2_MASK
- I40E_X722_PFQF_HLUT_LUT2_SHIFT
- I40E_X722_PFQF_HLUT_LUT3_MASK
- I40E_X722_PFQF_HLUT_LUT3_SHIFT
- I40E_X722_PFQF_HLUT_MAX_INDEX
- I40E_XDP_CONSUMED
- I40E_XDP_PASS
- I40E_XDP_REDIR
- I40E_XDP_TX
- I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK
- I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK
- I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK
- I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK
- I40IWCQ_INVSTAG_MASK
- I40IWCQ_INVSTAG_SHIFT
- I40IWCQ_OP_MASK
- I40IWCQ_OP_SHIFT
- I40IWCQ_PAYLDLEN_MASK
- I40IWCQ_PAYLDLEN_SHIFT
- I40IWCQ_PSHDROP_MASK
- I40IWCQ_PSHDROP_SHIFT
- I40IWCQ_QPID_MASK
- I40IWCQ_QPID_SHIFT
- I40IWCQ_SOEVENT_MASK
- I40IWCQ_SOEVENT_SHIFT
- I40IWCQ_SRQ_MASK
- I40IWCQ_SRQ_SHIFT
- I40IWCQ_STAG_MASK
- I40IWCQ_STAG_SHIFT
- I40IWCQ_TCPSEQNUM_MASK
- I40IWCQ_TCPSEQNUM_SHIFT
- I40IWQPC_ALIGNHDRS_MASK
- I40IWQPC_ALIGNHDRS_SHIFT
- I40IWQPC_ARPIDX_MASK
- I40IWQPC_ARPIDX_SHIFT
- I40IWQPC_AVOIDSTRETCHACK_MASK
- I40IWQPC_AVOIDSTRETCHACK_SHIFT
- I40IWQPC_BINDEN_MASK
- I40IWQPC_BINDEN_SHIFT
- I40IWQPC_CWND_MASK
- I40IWQPC_CWND_SHIFT
- I40IWQPC_DDP_VER_MASK
- I40IWQPC_DDP_VER_SHIFT
- I40IWQPC_DESTIPADDR0_MASK
- I40IWQPC_DESTIPADDR0_SHIFT
- I40IWQPC_DESTIPADDR1_MASK
- I40IWQPC_DESTIPADDR1_SHIFT
- I40IWQPC_DESTIPADDR2_MASK
- I40IWQPC_DESTIPADDR2_SHIFT
- I40IWQPC_DESTIPADDR3_MASK
- I40IWQPC_DESTIPADDR3_SHIFT
- I40IWQPC_DESTPORTNUM_MASK
- I40IWQPC_DESTPORTNUM_SHIFT
- I40IWQPC_DIS_VLAN_CHECKS_MASK
- I40IWQPC_DIS_VLAN_CHECKS_SHIFT
- I40IWQPC_DROPOOOSEG_MASK
- I40IWQPC_DROPOOOSEG_SHIFT
- I40IWQPC_DUPACK_THRESH_MASK
- I40IWQPC_DUPACK_THRESH_SHIFT
- I40IWQPC_ERR_RQ_IDX_MASK
- I40IWQPC_ERR_RQ_IDX_SHIFT
- I40IWQPC_ERR_RQ_IDX_VALID_MASK
- I40IWQPC_ERR_RQ_IDX_VALID_SHIFT
- I40IWQPC_EXCEPTION_LAN_QUEUE_MASK
- I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT
- I40IWQPC_FASTREGEN_MASK
- I40IWQPC_FASTREGEN_SHIFT
- I40IWQPC_FLOWLABEL_MASK
- I40IWQPC_FLOWLABEL_SHIFT
- I40IWQPC_IGNORE_TCP_OPT_MASK
- I40IWQPC_IGNORE_TCP_OPT_SHIFT
- I40IWQPC_IGNORE_TCP_UNS_OPT_MASK
- I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT
- I40IWQPC_INSERTL2TAG2_MASK
- I40IWQPC_INSERTL2TAG2_SHIFT
- I40IWQPC_INSERTVLANTAG_MASK
- I40IWQPC_INSERTVLANTAG_SHIFT
- I40IWQPC_IPV4_MASK
- I40IWQPC_IPV4_SHIFT
- I40IWQPC_IRDSIZE_MASK
- I40IWQPC_IRDSIZE_SHIFT
- I40IWQPC_IWARPMODE_MASK
- I40IWQPC_IWARPMODE_SHIFT
- I40IWQPC_KALIVE_TIMER_MAX_PROBES_MASK
- I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT
- I40IWQPC_KEEPALIVE_INTERVAL_MASK
- I40IWQPC_KEEPALIVE_INTERVAL_SHIFT
- I40IWQPC_KEEPALIVE_MASK
- I40IWQPC_KEEPALIVE_SHIFT
- I40IWQPC_LASTBYTESENT_MASK
- I40IWQPC_LASTBYTESENT_SHIFT
- I40IWQPC_LIMIT_MASK
- I40IWQPC_LIMIT_SHIFT
- I40IWQPC_LOCAL_IPADDR0_MASK
- I40IWQPC_LOCAL_IPADDR0_SHIFT
- I40IWQPC_LOCAL_IPADDR1_MASK
- I40IWQPC_LOCAL_IPADDR1_SHIFT
- I40IWQPC_LOCAL_IPADDR2_MASK
- I40IWQPC_LOCAL_IPADDR2_SHIFT
- I40IWQPC_LOCAL_IPADDR3_MASK
- I40IWQPC_LOCAL_IPADDR3_SHIFT
- I40IWQPC_MAXSNDWND_MASK
- I40IWQPC_MAXSNDWND_SHIFT
- I40IWQPC_NONAGLE_MASK
- I40IWQPC_NONAGLE_SHIFT
- I40IWQPC_ORDSIZE_MASK
- I40IWQPC_ORDSIZE_SHIFT
- I40IWQPC_PDIDX_MASK
- I40IWQPC_PDIDX_SHIFT
- I40IWQPC_PMENA_MASK
- I40IWQPC_PMENA_SHIFT
- I40IWQPC_PPIDX_MASK
- I40IWQPC_PPIDX_SHIFT
- I40IWQPC_PRIVEN_MASK
- I40IWQPC_PRIVEN_SHIFT
- I40IWQPC_Q2ADDR_MASK
- I40IWQPC_Q2ADDR_SHIFT
- I40IWQPC_QPCOMPCTX_MASK
- I40IWQPC_QPCOMPCTX_SHIFT
- I40IWQPC_QSHANDLE_MASK
- I40IWQPC_QSHANDLE_SHIFT
- I40IWQPC_RCVMARKERS_MASK
- I40IWQPC_RCVMARKERS_SHIFT
- I40IWQPC_RCVMARKOFFSET_MASK
- I40IWQPC_RCVMARKOFFSET_SHIFT
- I40IWQPC_RCVNOMPACRC_MASK
- I40IWQPC_RCVNOMPACRC_SHIFT
- I40IWQPC_RCVNXT_MASK
- I40IWQPC_RCVNXT_SHIFT
- I40IWQPC_RCVSCALE_MASK
- I40IWQPC_RCVSCALE_SHIFT
- I40IWQPC_RCVTPHEN_MASK
- I40IWQPC_RCVTPHEN_SHIFT
- I40IWQPC_RCVWND_MASK
- I40IWQPC_RCVWND_SHIFT
- I40IWQPC_RDMAP_VER_MASK
- I40IWQPC_RDMAP_VER_SHIFT
- I40IWQPC_RDOK_MASK
- I40IWQPC_RDOK_SHIFT
- I40IWQPC_REXMIT_THRESH_MASK
- I40IWQPC_REXMIT_THRESH_SHIFT
- I40IWQPC_RQADDR_MASK
- I40IWQPC_RQADDR_SHIFT
- I40IWQPC_RQSIZE_MASK
- I40IWQPC_RQSIZE_SHIFT
- I40IWQPC_RQTPHEN_MASK
- I40IWQPC_RQTPHEN_SHIFT
- I40IWQPC_RQTPHVAL_MASK
- I40IWQPC_RQTPHVAL_SHIFT
- I40IWQPC_RQWQESIZE_MASK
- I40IWQPC_RQWQESIZE_SHIFT
- I40IWQPC_RTTVAR_MASK
- I40IWQPC_RTTVAR_SHIFT
- I40IWQPC_RXCQNUM_MASK
- I40IWQPC_RXCQNUM_SHIFT
- I40IWQPC_SNAP_MASK
- I40IWQPC_SNAP_SHIFT
- I40IWQPC_SNDMARKERS_MASK
- I40IWQPC_SNDMARKERS_SHIFT
- I40IWQPC_SNDMARKOFFSET_MASK
- I40IWQPC_SNDMARKOFFSET_SHIFT
- I40IWQPC_SNDMAX_MASK
- I40IWQPC_SNDMAX_SHIFT
- I40IWQPC_SNDMSS_MASK
- I40IWQPC_SNDMSS_SHIFT
- I40IWQPC_SNDNXT_MASK
- I40IWQPC_SNDNXT_SHIFT
- I40IWQPC_SNDSCALE_MASK
- I40IWQPC_SNDSCALE_SHIFT
- I40IWQPC_SNDUNA_MASK
- I40IWQPC_SNDUNA_SHIFT
- I40IWQPC_SNDWL1_MASK
- I40IWQPC_SNDWL1_SHIFT
- I40IWQPC_SNDWL2_MASK
- I40IWQPC_SNDWL2_SHIFT
- I40IWQPC_SNDWND_MASK
- I40IWQPC_SNDWND_SHIFT
- I40IWQPC_SQADDR_MASK
- I40IWQPC_SQADDR_SHIFT
- I40IWQPC_SQSIZE_MASK
- I40IWQPC_SQSIZE_SHIFT
- I40IWQPC_SQTPHEN_MASK
- I40IWQPC_SQTPHEN_SHIFT
- I40IWQPC_SQTPHVAL_MASK
- I40IWQPC_SQTPHVAL_SHIFT
- I40IWQPC_SRCMACADDRIDX_MASK
- I40IWQPC_SRCMACADDRIDX_SHIFT
- I40IWQPC_SRCPORTNUM_MASK
- I40IWQPC_SRCPORTNUM_SHIFT
- I40IWQPC_SRQID_MASK
- I40IWQPC_SRQID_SHIFT
- I40IWQPC_SRTT_MASK
- I40IWQPC_SRTT_SHIFT
- I40IWQPC_SSTHRESH_MASK
- I40IWQPC_SSTHRESH_SHIFT
- I40IWQPC_STAT_INDEX_MASK
- I40IWQPC_STAT_INDEX_SHIFT
- I40IWQPC_TCPSTATE_MASK
- I40IWQPC_TCPSTATE_SHIFT
- I40IWQPC_TIMESTAMP_AGE_MASK
- I40IWQPC_TIMESTAMP_AGE_SHIFT
- I40IWQPC_TIMESTAMP_MASK
- I40IWQPC_TIMESTAMP_RECENT_MASK
- I40IWQPC_TIMESTAMP_RECENT_SHIFT
- I40IWQPC_TIMESTAMP_SHIFT
- I40IWQPC_TOS_MASK
- I40IWQPC_TOS_SHIFT
- I40IWQPC_TTL_MASK
- I40IWQPC_TTL_SHIFT
- I40IWQPC_TXCQNUM_MASK
- I40IWQPC_TXCQNUM_SHIFT
- I40IWQPC_USESRQ_MASK
- I40IWQPC_USESRQ_SHIFT
- I40IWQPC_USESTATSINSTANCE_MASK
- I40IWQPC_USESTATSINSTANCE_SHIFT
- I40IWQPC_VLANTAG_MASK
- I40IWQPC_VLANTAG_SHIFT
- I40IWQPC_WRRDRSPOK_MASK
- I40IWQPC_WRRDRSPOK_SHIFT
- I40IWQPC_WSCALE_MASK
- I40IWQPC_WSCALE_SHIFT
- I40IWQPC_XMITTPHEN_MASK
- I40IWQPC_XMITTPHEN_SHIFT
- I40IWQPRQ_ADDFRAGCNT_MASK
- I40IWQPRQ_ADDFRAGCNT_SHIFT
- I40IWQPRQ_COMPLCTX_MASK
- I40IWQPRQ_COMPLCTX_SHIFT
- I40IWQPRQ_FRAG_LEN_MASK
- I40IWQPRQ_FRAG_LEN_SHIFT
- I40IWQPRQ_STAG_MASK
- I40IWQPRQ_STAG_SHIFT
- I40IWQPRQ_TO_MASK
- I40IWQPRQ_TO_SHIFT
- I40IWQPRQ_VALID_MASK
- I40IWQPRQ_VALID_SHIFT
- I40IWQPSQ_ADDFRAGCNT_MASK
- I40IWQPSQ_ADDFRAGCNT_SHIFT
- I40IWQPSQ_BASEVA_TO_FBO_MASK
- I40IWQPSQ_BASEVA_TO_FBO_SHIFT
- I40IWQPSQ_COPYHOSTPBLS_MASK
- I40IWQPSQ_COPYHOSTPBLS_SHIFT
- I40IWQPSQ_FIRSTPMPBLIDXHI_MASK
- I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT
- I40IWQPSQ_FIRSTPMPBLIDXLO_MASK
- I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT
- I40IWQPSQ_FRAG_LEN_MASK
- I40IWQPSQ_FRAG_LEN_SHIFT
- I40IWQPSQ_FRAG_STAG_MASK
- I40IWQPSQ_FRAG_STAG_SHIFT
- I40IWQPSQ_FRAG_TO_MASK
- I40IWQPSQ_FRAG_TO_SHIFT
- I40IWQPSQ_HPAGESIZE_MASK
- I40IWQPSQ_HPAGESIZE_SHIFT
- I40IWQPSQ_INLINEDATAFLAG_MASK
- I40IWQPSQ_INLINEDATAFLAG_SHIFT
- I40IWQPSQ_INLINEDATALEN_MASK
- I40IWQPSQ_INLINEDATALEN_SHIFT
- I40IWQPSQ_LOCALFENCE_MASK
- I40IWQPSQ_LOCALFENCE_SHIFT
- I40IWQPSQ_LOCSTAG_MASK
- I40IWQPSQ_LOCSTAG_SHIFT
- I40IWQPSQ_LPBLSIZE_MASK
- I40IWQPSQ_LPBLSIZE_SHIFT
- I40IWQPSQ_MWLEN_MASK
- I40IWQPSQ_MWLEN_SHIFT
- I40IWQPSQ_MWSTAG_MASK
- I40IWQPSQ_MWSTAG_SHIFT
- I40IWQPSQ_OPCODE_MASK
- I40IWQPSQ_OPCODE_SHIFT
- I40IWQPSQ_PARENTMRSTAG_MASK
- I40IWQPSQ_PARENTMRSTAG_SHIFT
- I40IWQPSQ_PBLADDR_MASK
- I40IWQPSQ_PBLADDR_SHIFT
- I40IWQPSQ_PUSHWQE_MASK
- I40IWQPSQ_PUSHWQE_SHIFT
- I40IWQPSQ_READFENCE_MASK
- I40IWQPSQ_READFENCE_SHIFT
- I40IWQPSQ_REMSTAGINV_MASK
- I40IWQPSQ_REMSTAGINV_SHIFT
- I40IWQPSQ_REMSTAG_MASK
- I40IWQPSQ_REMSTAG_SHIFT
- I40IWQPSQ_REMTO_MASK
- I40IWQPSQ_REMTO_SHIFT
- I40IWQPSQ_SIGCOMPL_MASK
- I40IWQPSQ_SIGCOMPL_SHIFT
- I40IWQPSQ_STAGINDEX_MASK
- I40IWQPSQ_STAGINDEX_SHIFT
- I40IWQPSQ_STAGKEY_MASK
- I40IWQPSQ_STAGKEY_SHIFT
- I40IWQPSQ_STAGLEN_MASK
- I40IWQPSQ_STAGLEN_SHIFT
- I40IWQPSQ_STAGRIGHTS_MASK
- I40IWQPSQ_STAGRIGHTS_SHIFT
- I40IWQPSQ_STREAMMODE_MASK
- I40IWQPSQ_STREAMMODE_SHIFT
- I40IWQPSQ_VABASEDTO_MASK
- I40IWQPSQ_VABASEDTO_SHIFT
- I40IWQPSQ_VALID_MASK
- I40IWQPSQ_VALID_SHIFT
- I40IWQPSQ_WAITFORRCVPDU_MASK
- I40IWQPSQ_WAITFORRCVPDU_SHIFT
- I40IWQPSQ_WQDESCIDX_MASK
- I40IWQPSQ_WQDESCIDX_SHIFT
- I40IWQP_OP_BIND_MW
- I40IWQP_OP_FAST_REGISTER
- I40IWQP_OP_LOCAL_INVALIDATE
- I40IWQP_OP_NOP
- I40IWQP_OP_RDMA_READ
- I40IWQP_OP_RDMA_READ_LOC_INV
- I40IWQP_OP_RDMA_SEND
- I40IWQP_OP_RDMA_SEND_INV
- I40IWQP_OP_RDMA_SEND_SOL_EVENT
- I40IWQP_OP_RDMA_SEND_SOL_EVENT_INV
- I40IWQP_OP_RDMA_WRITE
- I40IWQP_TERM_DONOT_SEND_TERM_OR_FIN
- I40IWQP_TERM_SEND_FIN_ONLY
- I40IWQP_TERM_SEND_TERM_AND_FIN
- I40IWQP_TERM_SEND_TERM_ONLY
- I40IW_ABI_H
- I40IW_ABI_VER
- I40IW_ACCESS_FLAGS_ALL
- I40IW_ACCESS_FLAGS_BIND_WINDOW
- I40IW_ACCESS_FLAGS_LOCALREAD
- I40IW_ACCESS_FLAGS_LOCALWRITE
- I40IW_ACCESS_FLAGS_REMOTEREAD
- I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY
- I40IW_ACCESS_FLAGS_REMOTEWRITE
- I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY
- I40IW_ADDR_TYPE_VA_BASED
- I40IW_ADDR_TYPE_ZERO_BASED
- I40IW_AEQE_AECODE_MASK
- I40IW_AEQE_AECODE_SHIFT
- I40IW_AEQE_AESRC_MASK
- I40IW_AEQE_AESRC_SHIFT
- I40IW_AEQE_COMPCTX_MASK
- I40IW_AEQE_COMPCTX_SHIFT
- I40IW_AEQE_IWSTATE_MASK
- I40IW_AEQE_IWSTATE_SHIFT
- I40IW_AEQE_OVERFLOW_MASK
- I40IW_AEQE_OVERFLOW_SHIFT
- I40IW_AEQE_Q2DATA_MASK
- I40IW_AEQE_Q2DATA_SHIFT
- I40IW_AEQE_QPCQID_MASK
- I40IW_AEQE_QPCQID_SHIFT
- I40IW_AEQE_SIZE
- I40IW_AEQE_TCPSTATE_MASK
- I40IW_AEQE_TCPSTATE_SHIFT
- I40IW_AEQE_VALID_MASK
- I40IW_AEQE_VALID_SHIFT
- I40IW_AEQE_WQDESCIDX_MASK
- I40IW_AEQE_WQDESCIDX_SHIFT
- I40IW_AEQ_ALIGNMENT
- I40IW_AEQ_ALIGNMENT_MASK
- I40IW_AE_AMP_BAD_PD
- I40IW_AE_AMP_BAD_QP
- I40IW_AE_AMP_BAD_STAG_INDEX
- I40IW_AE_AMP_BAD_STAG_KEY
- I40IW_AE_AMP_BOUNDS_VIOLATION
- I40IW_AE_AMP_FASTREG_INVALID_LENGTH
- I40IW_AE_AMP_FASTREG_INVALID_RIGHTS
- I40IW_AE_AMP_FASTREG_MW_STAG
- I40IW_AE_AMP_FASTREG_PBL_TABLE_OVERFLOW
- I40IW_AE_AMP_FASTREG_SHARED
- I40IW_AE_AMP_FASTREG_VALID_STAG
- I40IW_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS
- I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS
- I40IW_AE_AMP_INVALIDATE_SHARED
- I40IW_AE_AMP_INVALID_STAG
- I40IW_AE_AMP_MWBIND_BIND_DISABLED
- I40IW_AE_AMP_MWBIND_INVALID_BOUNDS
- I40IW_AE_AMP_MWBIND_INVALID_RIGHTS
- I40IW_AE_AMP_MWBIND_OF_MR_STAG
- I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT
- I40IW_AE_AMP_MWBIND_TO_MW_STAG
- I40IW_AE_AMP_MWBIND_TO_ZERO_BASED_STAG
- I40IW_AE_AMP_MWBIND_VALID_STAG
- I40IW_AE_AMP_RIGHTS_VIOLATION
- I40IW_AE_AMP_TO_WRAP
- I40IW_AE_AMP_UNALLOCATED_STAG
- I40IW_AE_BAD_CLOSE
- I40IW_AE_CQ_OPERATION_ERROR
- I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN
- I40IW_AE_DDP_NO_L_BIT
- I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER
- I40IW_AE_DDP_UBE_INVALID_DDP_VERSION
- I40IW_AE_DDP_UBE_INVALID_MO
- I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE
- I40IW_AE_DDP_UBE_INVALID_QN
- I40IW_AE_IB_RREQ_AND_Q1_FULL
- I40IW_AE_INVALID_ARP_ENTRY
- I40IW_AE_INVALID_MAC_ENTRY
- I40IW_AE_INVALID_TCP_OPTION_RCVD
- I40IW_AE_LCE_CQ_CATASTROPHIC
- I40IW_AE_LCE_FUNCTION_CATASTROPHIC
- I40IW_AE_LCE_QP_CATASTROPHIC
- I40IW_AE_LLP_CLOSE_COMPLETE
- I40IW_AE_LLP_CONNECTION_RESET
- I40IW_AE_LLP_DOUBT_REACHABILITY
- I40IW_AE_LLP_FIN_RECEIVED
- I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR
- I40IW_AE_LLP_RX_VLAN_MISMATCH
- I40IW_AE_LLP_SEGMENT_TOO_LARGE
- I40IW_AE_LLP_SEGMENT_TOO_SMALL
- I40IW_AE_LLP_SYN_RECEIVED
- I40IW_AE_LLP_TERMINATE_RECEIVED
- I40IW_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES
- I40IW_AE_LLP_TOO_MANY_RETRIES
- I40IW_AE_PRIV_OPERATION_DENIED
- I40IW_AE_QP_SUSPEND_COMPLETE
- I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE
- I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION
- I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE
- I40IW_AE_RDMA_READ_WHILE_ORD_ZERO
- I40IW_AE_RESET_NOT_SENT
- I40IW_AE_RESET_SENT
- I40IW_AE_RESOURCE_EXHAUSTION
- I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST
- I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP
- I40IW_AE_SOURCE_CQ
- I40IW_AE_SOURCE_CQ_0110
- I40IW_AE_SOURCE_CQ_1010
- I40IW_AE_SOURCE_CQ_1110
- I40IW_AE_SOURCE_IN_RR_WR
- I40IW_AE_SOURCE_IN_RR_WR_1011
- I40IW_AE_SOURCE_OUT_RR
- I40IW_AE_SOURCE_OUT_RR_1111
- I40IW_AE_SOURCE_RQ
- I40IW_AE_SOURCE_RQ_0011
- I40IW_AE_SOURCE_RSVD
- I40IW_AE_SOURCE_SQ
- I40IW_AE_SOURCE_SQ_0111
- I40IW_AE_STAG_ZERO_INVALID
- I40IW_AE_STALE_ARP_ENTRY
- I40IW_AE_TERMINATE_SENT
- I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG
- I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT
- I40IW_AE_WQE_INVALID_PARAMETER
- I40IW_AE_WQE_LSMM_TOO_LONG
- I40IW_AE_WQE_UNEXPECTED_OPCODE
- I40IW_ARP_ADD
- I40IW_ARP_DELETE
- I40IW_ARP_RESOLVE
- I40IW_ATOMIC_RING_MOVE_HEAD
- I40IW_CCQ_OPRETVAL_MASK
- I40IW_CCQ_OPRETVAL_SHIFT
- I40IW_CEQE_CQCTX_MASK
- I40IW_CEQE_CQCTX_SHIFT
- I40IW_CEQE_SIZE
- I40IW_CEQE_VALID_MASK
- I40IW_CEQE_VALID_SHIFT
- I40IW_CEQ_ALIGNMENT
- I40IW_CEQ_ALIGNMENT_MASK
- I40IW_CEQ_MAX_COUNT
- I40IW_CM_DEFAULT_FRAME_CNT
- I40IW_CM_DEFAULT_FREE_PKTS
- I40IW_CM_DEFAULT_MSS
- I40IW_CM_DEFAULT_MTU
- I40IW_CM_DEFAULT_RCV_WND
- I40IW_CM_DEFAULT_RCV_WND_SCALE
- I40IW_CM_DEFAULT_RCV_WND_SCALED
- I40IW_CM_DEF_LOCAL_ID
- I40IW_CM_DEF_LOCAL_ID2
- I40IW_CM_DEF_SEQ
- I40IW_CM_DEF_SEQ2
- I40IW_CM_EVENT_ABORTED
- I40IW_CM_EVENT_CONNECTED
- I40IW_CM_EVENT_ESTABLISHED
- I40IW_CM_EVENT_MPA_ACCEPT
- I40IW_CM_EVENT_MPA_CONNECT
- I40IW_CM_EVENT_MPA_ESTABLISHED
- I40IW_CM_EVENT_MPA_REJECT
- I40IW_CM_EVENT_MPA_REQ
- I40IW_CM_EVENT_RESET
- I40IW_CM_EVENT_UNKNOWN
- I40IW_CM_FREE_PKT_LO_WATERMARK
- I40IW_CM_H
- I40IW_CM_HASHTABLE_SIZE
- I40IW_CM_LISTENER_ACTIVE_STATE
- I40IW_CM_LISTENER_EITHER_STATE
- I40IW_CM_LISTENER_PASSIVE_STATE
- I40IW_CM_STATE_ACCEPTING
- I40IW_CM_STATE_CLOSED
- I40IW_CM_STATE_CLOSE_WAIT
- I40IW_CM_STATE_CLOSING
- I40IW_CM_STATE_ESTABLISHED
- I40IW_CM_STATE_FIN_WAIT1
- I40IW_CM_STATE_FIN_WAIT2
- I40IW_CM_STATE_INITED
- I40IW_CM_STATE_LAST_ACK
- I40IW_CM_STATE_LISTENER_DESTROYED
- I40IW_CM_STATE_LISTENING
- I40IW_CM_STATE_MPAREJ_RCVD
- I40IW_CM_STATE_MPAREQ_RCVD
- I40IW_CM_STATE_MPAREQ_SENT
- I40IW_CM_STATE_OFFLOADED
- I40IW_CM_STATE_ONE_SIDE_ESTABLISHED
- I40IW_CM_STATE_SYN_RCVD
- I40IW_CM_STATE_SYN_SENT
- I40IW_CM_STATE_TIME_WAIT
- I40IW_CM_STATE_UNKNOWN
- I40IW_CM_TCP_TIMER_INTERVAL
- I40IW_CM_THREAD_STACK_SIZE
- I40IW_COMMIT_FPM_BUF_SIZE
- I40IW_COMPL_STATUS_ACCESS_VIOLATION
- I40IW_COMPL_STATUS_BASE_BOUND_VIOLATION
- I40IW_COMPL_STATUS_FLUSHED
- I40IW_COMPL_STATUS_INVALID_ACCESS
- I40IW_COMPL_STATUS_INVALID_FBO
- I40IW_COMPL_STATUS_INVALID_LENGTH
- I40IW_COMPL_STATUS_INVALID_PD_ID
- I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_ENTRY
- I40IW_COMPL_STATUS_INVALID_PHYS_BUFFER_SIZE
- I40IW_COMPL_STATUS_INVALID_REGION
- I40IW_COMPL_STATUS_INVALID_STAG
- I40IW_COMPL_STATUS_INVALID_TOTAL_LENGTH
- I40IW_COMPL_STATUS_INVALID_VIRT_ADDRESS
- I40IW_COMPL_STATUS_INVALID_WINDOW
- I40IW_COMPL_STATUS_INVALID_WQE
- I40IW_COMPL_STATUS_PHYS_BUFFER_LIST_TOO_LONG
- I40IW_COMPL_STATUS_QP_CATASTROPHIC
- I40IW_COMPL_STATUS_QP_NOT_PRIVLEDGED
- I40IW_COMPL_STATUS_RDMA_READ_ZERO_ORD
- I40IW_COMPL_STATUS_REMOTE_TERMINATION
- I40IW_COMPL_STATUS_STAG_INVALID_PDID
- I40IW_COMPL_STATUS_STAG_NOT_INVALID
- I40IW_COMPL_STATUS_SUCCESS
- I40IW_COMPL_STATUS_WRAP_ERROR
- I40IW_CQ0_ALIGNMENT
- I40IW_CQ0_ALIGNMENT_MASK
- I40IW_CQE_QTYPE_RQ
- I40IW_CQE_QTYPE_SQ
- I40IW_CQE_SIZE
- I40IW_CQPHC_DISABLE_PFPDUS_MASK
- I40IW_CQPHC_DISABLE_PFPDUS_SHIFT
- I40IW_CQPHC_ENABLED_VFS_MASK
- I40IW_CQPHC_ENABLED_VFS_SHIFT
- I40IW_CQPHC_EN_DC_TCP_MASK
- I40IW_CQPHC_EN_DC_TCP_SHIFT
- I40IW_CQPHC_HMC_PROFILE_MASK
- I40IW_CQPHC_HMC_PROFILE_SHIFT
- I40IW_CQPHC_QPCTX_MASK
- I40IW_CQPHC_QPCTX_SHIFT
- I40IW_CQPHC_SQBASE_MASK
- I40IW_CQPHC_SQBASE_SHIFT
- I40IW_CQPHC_SQSIZE_MASK
- I40IW_CQPHC_SQSIZE_SHIFT
- I40IW_CQPHC_SVER
- I40IW_CQPHC_SVER_MASK
- I40IW_CQPHC_SVER_SHIFT
- I40IW_CQPSQ_AEQ_AEQECNT_MASK
- I40IW_CQPSQ_AEQ_AEQECNT_SHIFT
- I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_MASK
- I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT
- I40IW_CQPSQ_AEQ_LPBLSIZE_MASK
- I40IW_CQPSQ_AEQ_LPBLSIZE_SHIFT
- I40IW_CQPSQ_AEQ_VMAP_MASK
- I40IW_CQPSQ_AEQ_VMAP_SHIFT
- I40IW_CQPSQ_CEQ_CEQID_MASK
- I40IW_CQPSQ_CEQ_CEQID_SHIFT
- I40IW_CQPSQ_CEQ_CEQSIZE_MASK
- I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT
- I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_MASK
- I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT
- I40IW_CQPSQ_CEQ_LPBLSIZE_MASK
- I40IW_CQPSQ_CEQ_LPBLSIZE_SHIFT
- I40IW_CQPSQ_CEQ_VMAP_MASK
- I40IW_CQPSQ_CEQ_VMAP_SHIFT
- I40IW_CQPSQ_CFPM_HMCFNID_MASK
- I40IW_CQPSQ_CFPM_HMCFNID_SHIFT
- I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_MASK
- I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT
- I40IW_CQPSQ_CQ_CEQIDVALID_MASK
- I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT
- I40IW_CQPSQ_CQ_CEQID_MASK
- I40IW_CQPSQ_CQ_CEQID_SHIFT
- I40IW_CQPSQ_CQ_CHKOVERFLOW_MASK
- I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT
- I40IW_CQPSQ_CQ_CQCTX_MASK
- I40IW_CQPSQ_CQ_CQCTX_SHIFT
- I40IW_CQPSQ_CQ_CQRESIZE_MASK
- I40IW_CQPSQ_CQ_CQRESIZE_SHIFT
- I40IW_CQPSQ_CQ_CQSIZE_MASK
- I40IW_CQPSQ_CQ_CQSIZE_SHIFT
- I40IW_CQPSQ_CQ_ENCEQEMASK_MASK
- I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT
- I40IW_CQPSQ_CQ_LPBLSIZE_MASK
- I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
- I40IW_CQPSQ_CQ_OP_MASK
- I40IW_CQPSQ_CQ_OP_SHIFT
- I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_MASK
- I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT
- I40IW_CQPSQ_CQ_VIRTMAP_MASK
- I40IW_CQPSQ_CQ_VIRTMAP_SHIFT
- I40IW_CQPSQ_FWQE_AECODE_MASK
- I40IW_CQPSQ_FWQE_AECODE_SHIFT
- I40IW_CQPSQ_FWQE_AESOURCE_MASK
- I40IW_CQPSQ_FWQE_AESOURCE_SHIFT
- I40IW_CQPSQ_FWQE_FLUSHRQ_MASK
- I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT
- I40IW_CQPSQ_FWQE_FLUSHSQ_MASK
- I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT
- I40IW_CQPSQ_FWQE_GENERATE_AE_MASK
- I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT
- I40IW_CQPSQ_FWQE_QPID_MASK
- I40IW_CQPSQ_FWQE_QPID_SHIFT
- I40IW_CQPSQ_FWQE_RQMJERR_MASK
- I40IW_CQPSQ_FWQE_RQMJERR_SHIFT
- I40IW_CQPSQ_FWQE_RQMNERR_MASK
- I40IW_CQPSQ_FWQE_RQMNERR_SHIFT
- I40IW_CQPSQ_FWQE_SQMJERR_MASK
- I40IW_CQPSQ_FWQE_SQMJERR_SHIFT
- I40IW_CQPSQ_FWQE_SQMNERR_MASK
- I40IW_CQPSQ_FWQE_SQMNERR_SHIFT
- I40IW_CQPSQ_FWQE_USERFLCODE_MASK
- I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT
- I40IW_CQPSQ_MAPT_ADDPORT_MASK
- I40IW_CQPSQ_MAPT_ADDPORT_SHIFT
- I40IW_CQPSQ_MAPT_PORT_MASK
- I40IW_CQPSQ_MAPT_PORT_SHIFT
- I40IW_CQPSQ_MAT_ARPENTRYIDX_MASK
- I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT
- I40IW_CQPSQ_MAT_ENTRYVALID_MASK
- I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT
- I40IW_CQPSQ_MAT_MACADDR_MASK
- I40IW_CQPSQ_MAT_MACADDR_SHIFT
- I40IW_CQPSQ_MAT_PERMANENT_MASK
- I40IW_CQPSQ_MAT_PERMANENT_SHIFT
- I40IW_CQPSQ_MAT_QUERY_MASK
- I40IW_CQPSQ_MAT_QUERY_SHIFT
- I40IW_CQPSQ_MAT_REACHMAX_MASK
- I40IW_CQPSQ_MAT_REACHMAX_SHIFT
- I40IW_CQPSQ_MHMC_FREEPMFN_MASK
- I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT
- I40IW_CQPSQ_MHMC_VFIDX_MASK
- I40IW_CQPSQ_MHMC_VFIDX_SHIFT
- I40IW_CQPSQ_MLIPA_FREEENTRY_MASK
- I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT
- I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_MASK
- I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT
- I40IW_CQPSQ_MLIPA_IPTABLEIDX_MASK
- I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT
- I40IW_CQPSQ_MLIPA_IPV4VALID_MASK
- I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT
- I40IW_CQPSQ_MLIPA_IPV4_MASK
- I40IW_CQPSQ_MLIPA_IPV4_SHIFT
- I40IW_CQPSQ_MLIPA_IPV6HI_MASK
- I40IW_CQPSQ_MLIPA_IPV6HI_SHIFT
- I40IW_CQPSQ_MLIPA_IPV6LO_MASK
- I40IW_CQPSQ_MLIPA_IPV6LO_SHIFT
- I40IW_CQPSQ_MLIPA_IPV6VALID_MASK
- I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT
- I40IW_CQPSQ_MLIPA_MAC0_MASK
- I40IW_CQPSQ_MLIPA_MAC0_SHIFT
- I40IW_CQPSQ_MLIPA_MAC1_MASK
- I40IW_CQPSQ_MLIPA_MAC1_SHIFT
- I40IW_CQPSQ_MLIPA_MAC2_MASK
- I40IW_CQPSQ_MLIPA_MAC2_SHIFT
- I40IW_CQPSQ_MLIPA_MAC3_MASK
- I40IW_CQPSQ_MLIPA_MAC3_SHIFT
- I40IW_CQPSQ_MLIPA_MAC4_MASK
- I40IW_CQPSQ_MLIPA_MAC4_SHIFT
- I40IW_CQPSQ_MLIPA_MAC5_MASK
- I40IW_CQPSQ_MLIPA_MAC5_SHIFT
- I40IW_CQPSQ_MPP_FREE_PAGE_MASK
- I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT
- I40IW_CQPSQ_MPP_PPIDX_MASK
- I40IW_CQPSQ_MPP_PPIDX_SHIFT
- I40IW_CQPSQ_MPP_QS_HANDLE_MASK
- I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT
- I40IW_CQPSQ_MVPBP_FIRST_PD_INX_MASK
- I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT
- I40IW_CQPSQ_MVPBP_INV_PD_ENT_MASK
- I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT
- I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_MASK
- I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT
- I40IW_CQPSQ_MVPBP_PD_PLPBA_MASK
- I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT
- I40IW_CQPSQ_MVPBP_SD_INX_MASK
- I40IW_CQPSQ_MVPBP_SD_INX_SHIFT
- I40IW_CQPSQ_OPCODE_MASK
- I40IW_CQPSQ_OPCODE_SHIFT
- I40IW_CQPSQ_PBUFADDR_MASK
- I40IW_CQPSQ_PBUFADDR_SHIFT
- I40IW_CQPSQ_QHASH_ADDR0_MASK
- I40IW_CQPSQ_QHASH_ADDR0_SHIFT
- I40IW_CQPSQ_QHASH_ADDR1_MASK
- I40IW_CQPSQ_QHASH_ADDR1_SHIFT
- I40IW_CQPSQ_QHASH_ADDR2_MASK
- I40IW_CQPSQ_QHASH_ADDR2_SHIFT
- I40IW_CQPSQ_QHASH_ADDR3_MASK
- I40IW_CQPSQ_QHASH_ADDR3_SHIFT
- I40IW_CQPSQ_QHASH_DEST_PORT_MASK
- I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT
- I40IW_CQPSQ_QHASH_ENTRYTYPE_MASK
- I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT
- I40IW_CQPSQ_QHASH_IPV4VALID_MASK
- I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT
- I40IW_CQPSQ_QHASH_MANAGE_MASK
- I40IW_CQPSQ_QHASH_MANAGE_SHIFT
- I40IW_CQPSQ_QHASH_OPCODE_MASK
- I40IW_CQPSQ_QHASH_OPCODE_SHIFT
- I40IW_CQPSQ_QHASH_QPN_MASK
- I40IW_CQPSQ_QHASH_QPN_SHIFT
- I40IW_CQPSQ_QHASH_QS_HANDLE_MASK
- I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT
- I40IW_CQPSQ_QHASH_SRC_PORT_MASK
- I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT
- I40IW_CQPSQ_QHASH_VLANID_MASK
- I40IW_CQPSQ_QHASH_VLANID_SHIFT
- I40IW_CQPSQ_QHASH_VLANVALID_MASK
- I40IW_CQPSQ_QHASH_VLANVALID_SHIFT
- I40IW_CQPSQ_QHASH_WQEVALID_MASK
- I40IW_CQPSQ_QHASH_WQEVALID_SHIFT
- I40IW_CQPSQ_QP_ARPTABIDXVALID_MASK
- I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT
- I40IW_CQPSQ_QP_CACHEDVARVALID_MASK
- I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT
- I40IW_CQPSQ_QP_CQNUMVALID_MASK
- I40IW_CQPSQ_QP_CQNUMVALID_SHIFT
- I40IW_CQPSQ_QP_DBSHADOWADDR_MASK
- I40IW_CQPSQ_QP_DBSHADOWADDR_SHIFT
- I40IW_CQPSQ_QP_FORCELOOPBACK_MASK
- I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT
- I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK
- I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT
- I40IW_CQPSQ_QP_MSSCHANGE_MASK
- I40IW_CQPSQ_QP_MSSCHANGE_SHIFT
- I40IW_CQPSQ_QP_NEWMSS_MASK
- I40IW_CQPSQ_QP_NEWMSS_SHIFT
- I40IW_CQPSQ_QP_NEXTIWSTATE_MASK
- I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT
- I40IW_CQPSQ_QP_OP_MASK
- I40IW_CQPSQ_QP_OP_SHIFT
- I40IW_CQPSQ_QP_ORDVALID_MASK
- I40IW_CQPSQ_QP_ORDVALID_SHIFT
- I40IW_CQPSQ_QP_QPCTX_MASK
- I40IW_CQPSQ_QP_QPCTX_SHIFT
- I40IW_CQPSQ_QP_QPID_MASK
- I40IW_CQPSQ_QP_QPID_SHIFT
- I40IW_CQPSQ_QP_QPTYPE_MASK
- I40IW_CQPSQ_QP_QPTYPE_SHIFT
- I40IW_CQPSQ_QP_REMOVEHASHENTRY_MASK
- I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT
- I40IW_CQPSQ_QP_RESETCON_MASK
- I40IW_CQPSQ_QP_RESETCON_SHIFT
- I40IW_CQPSQ_QP_TERMACT_MASK
- I40IW_CQPSQ_QP_TERMACT_SHIFT
- I40IW_CQPSQ_QP_TERMLEN_MASK
- I40IW_CQPSQ_QP_TERMLEN_SHIFT
- I40IW_CQPSQ_QP_TOECTXVALID_MASK
- I40IW_CQPSQ_QP_TOECTXVALID_SHIFT
- I40IW_CQPSQ_QP_VQ_MASK
- I40IW_CQPSQ_QP_VQ_SHIFT
- I40IW_CQPSQ_QUERYSTAG_IDX_MASK
- I40IW_CQPSQ_QUERYSTAG_IDX_SHIFT
- I40IW_CQPSQ_RESUMEQP_QPID_MASK
- I40IW_CQPSQ_RESUMEQP_QPID_SHIFT
- I40IW_CQPSQ_RESUMEQP_QSHANDLE_MASK
- I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT
- I40IW_CQPSQ_SHMCRP_HMC_PROFILE_MASK
- I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT
- I40IW_CQPSQ_SHMCRP_VFNUM_MASK
- I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT
- I40IW_CQPSQ_SRQ_ARMLIMITEVENT_MASK
- I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT
- I40IW_CQPSQ_SRQ_DBSHADOWAREA_MASK
- I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT
- I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_MASK
- I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT
- I40IW_CQPSQ_SRQ_LPBLSIZE_MASK
- I40IW_CQPSQ_SRQ_LPBLSIZE_SHIFT
- I40IW_CQPSQ_SRQ_PDID_MASK
- I40IW_CQPSQ_SRQ_PDID_SHIFT
- I40IW_CQPSQ_SRQ_RQSIZE_MASK
- I40IW_CQPSQ_SRQ_RQSIZE_SHIFT
- I40IW_CQPSQ_SRQ_RQWQESIZE_MASK
- I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT
- I40IW_CQPSQ_SRQ_SRQCTX_MASK
- I40IW_CQPSQ_SRQ_SRQCTX_SHIFT
- I40IW_CQPSQ_SRQ_SRQID_MASK
- I40IW_CQPSQ_SRQ_SRQID_SHIFT
- I40IW_CQPSQ_SRQ_SRQLIMIT_MASK
- I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT
- I40IW_CQPSQ_SRQ_TPHEN_MASK
- I40IW_CQPSQ_SRQ_TPHEN_SHIFT
- I40IW_CQPSQ_SRQ_VIRTMAP_MASK
- I40IW_CQPSQ_SRQ_VIRTMAP_SHIFT
- I40IW_CQPSQ_STAG_ARIGHTS_MASK
- I40IW_CQPSQ_STAG_ARIGHTS_SHIFT
- I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_MASK
- I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT
- I40IW_CQPSQ_STAG_HMCFNIDX_MASK
- I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT
- I40IW_CQPSQ_STAG_HPAGESIZE_MASK
- I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT
- I40IW_CQPSQ_STAG_IDX_MASK
- I40IW_CQPSQ_STAG_IDX_SHIFT
- I40IW_CQPSQ_STAG_KEY_MASK
- I40IW_CQPSQ_STAG_KEY_SHIFT
- I40IW_CQPSQ_STAG_LPBLSIZE_MASK
- I40IW_CQPSQ_STAG_LPBLSIZE_SHIFT
- I40IW_CQPSQ_STAG_MR_MASK
- I40IW_CQPSQ_STAG_MR_SHIFT
- I40IW_CQPSQ_STAG_PARENTSTAGIDX_MASK
- I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT
- I40IW_CQPSQ_STAG_PBA_MASK
- I40IW_CQPSQ_STAG_PBA_SHIFT
- I40IW_CQPSQ_STAG_PDID_MASK
- I40IW_CQPSQ_STAG_PDID_SHIFT
- I40IW_CQPSQ_STAG_REMACCENABLED_MASK
- I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT
- I40IW_CQPSQ_STAG_STAGLEN_MASK
- I40IW_CQPSQ_STAG_STAGLEN_SHIFT
- I40IW_CQPSQ_STAG_USEHMCFNIDX_MASK
- I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT
- I40IW_CQPSQ_STAG_USEPFRID_MASK
- I40IW_CQPSQ_STAG_USEPFRID_SHIFT
- I40IW_CQPSQ_STAG_VABASEDTO_MASK
- I40IW_CQPSQ_STAG_VABASEDTO_SHIFT
- I40IW_CQPSQ_STAG_VA_FBO_MASK
- I40IW_CQPSQ_STAG_VA_FBO_SHIFT
- I40IW_CQPSQ_SUSPENDQP_QPID_MASK
- I40IW_CQPSQ_SUSPENDQP_QPID_SHIFT
- I40IW_CQPSQ_TPHEN_MASK
- I40IW_CQPSQ_TPHEN_SHIFT
- I40IW_CQPSQ_TPHVAL_MASK
- I40IW_CQPSQ_TPHVAL_SHIFT
- I40IW_CQPSQ_UCTX_FREEZEQP_MASK
- I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT
- I40IW_CQPSQ_UCTX_QPCTXADDR_MASK
- I40IW_CQPSQ_UCTX_QPCTXADDR_SHIFT
- I40IW_CQPSQ_UCTX_QPID_MASK
- I40IW_CQPSQ_UCTX_QPID_SHIFT
- I40IW_CQPSQ_UCTX_QPTYPE_MASK
- I40IW_CQPSQ_UCTX_QPTYPE_SHIFT
- I40IW_CQPSQ_UCTX_RAWFORMAT_MASK
- I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT
- I40IW_CQPSQ_UPESD_ENTRY_COUNT_MASK
- I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT
- I40IW_CQPSQ_UPESD_ENTRY_VALID_MASK
- I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT
- I40IW_CQPSQ_UPESD_HMCFNID_MASK
- I40IW_CQPSQ_UPESD_HMCFNID_SHIFT
- I40IW_CQPSQ_UPESD_SDCMD_MASK
- I40IW_CQPSQ_UPESD_SDCMD_SHIFT
- I40IW_CQPSQ_UPESD_SDDATAHI_MASK
- I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT
- I40IW_CQPSQ_UPESD_SDDATALOW_MASK
- I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT
- I40IW_CQPSQ_UPESD_SKIP_ENTRY_MASK
- I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT
- I40IW_CQPSQ_WQEVALID_MASK
- I40IW_CQPSQ_WQEVALID_SHIFT
- I40IW_CQP_ALIGNMENT
- I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED
- I40IW_CQP_COMPL_RQ_WQE_FLUSHED
- I40IW_CQP_COMPL_SQ_WQE_FLUSHED
- I40IW_CQP_CTX_SIZE
- I40IW_CQP_INIT_WQE
- I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY
- I40IW_CQP_OP_ALLOC_STAG
- I40IW_CQP_OP_COMMIT_FPM_VALUES
- I40IW_CQP_OP_CREATE_ADDR_VECT
- I40IW_CQP_OP_CREATE_AEQ
- I40IW_CQP_OP_CREATE_CEQ
- I40IW_CQP_OP_CREATE_CQ
- I40IW_CQP_OP_CREATE_QP
- I40IW_CQP_OP_CREATE_SRQ
- I40IW_CQP_OP_CREATE_UDA_MCAST_GROUP
- I40IW_CQP_OP_DEALLOC_STAG
- I40IW_CQP_OP_DESTROY_ADDR_VECT
- I40IW_CQP_OP_DESTROY_AEQ
- I40IW_CQP_OP_DESTROY_CEQ
- I40IW_CQP_OP_DESTROY_CQ
- I40IW_CQP_OP_DESTROY_QP
- I40IW_CQP_OP_DESTROY_SRQ
- I40IW_CQP_OP_DESTROY_UDA_MCAST_GROUP
- I40IW_CQP_OP_FLUSH_WQES
- I40IW_CQP_OP_GEN_AE
- I40IW_CQP_OP_MANAGE_APBVT
- I40IW_CQP_OP_MANAGE_ARP
- I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE
- I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE
- I40IW_CQP_OP_MANAGE_PE_TEAM
- I40IW_CQP_OP_MANAGE_PUSH_PAGES
- I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY
- I40IW_CQP_OP_MANAGE_VF_PBLE_BP
- I40IW_CQP_OP_MODIFY_ADDR_VECT
- I40IW_CQP_OP_MODIFY_CQ
- I40IW_CQP_OP_MODIFY_QP
- I40IW_CQP_OP_MODIFY_SRQ
- I40IW_CQP_OP_MODIFY_UDA_MCAST_GROUP
- I40IW_CQP_OP_NOP
- I40IW_CQP_OP_QUERY_FPM_VALUES
- I40IW_CQP_OP_QUERY_STAG
- I40IW_CQP_OP_REG_MR
- I40IW_CQP_OP_REG_SMR
- I40IW_CQP_OP_RESUME_QP
- I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE
- I40IW_CQP_OP_SHMC_PAGES_ALLOCATED
- I40IW_CQP_OP_SUSPEND_QP
- I40IW_CQP_OP_UPDATE_PE_SDS
- I40IW_CQP_OP_UPLOAD_CONTEXT
- I40IW_CQP_SW_SQSIZE_2048
- I40IW_CQP_SW_SQSIZE_4
- I40IW_CQP_WAIT_EVENT
- I40IW_CQP_WAIT_POLL_CQ
- I40IW_CQP_WAIT_POLL_REGS
- I40IW_CQP_WQE_SIZE
- I40IW_CQ_DBSA_ARM_NEXT_MASK
- I40IW_CQ_DBSA_ARM_NEXT_SE_MASK
- I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT
- I40IW_CQ_DBSA_ARM_NEXT_SHIFT
- I40IW_CQ_DBSA_ARM_SEQ_NUM_MASK
- I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT
- I40IW_CQ_DBSA_CQEIDX_MASK
- I40IW_CQ_DBSA_CQEIDX_SHIFT
- I40IW_CQ_DBSA_SW_CQ_SELECT_MASK
- I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT
- I40IW_CQ_ERROR_MASK
- I40IW_CQ_ERROR_SHIFT
- I40IW_CQ_MAJERR_MASK
- I40IW_CQ_MAJERR_SHIFT
- I40IW_CQ_MINERR_MASK
- I40IW_CQ_MINERR_SHIFT
- I40IW_CQ_QPCTX_MASK
- I40IW_CQ_QPCTX_SHIFT
- I40IW_CQ_SQ_MASK
- I40IW_CQ_SQ_SHIFT
- I40IW_CQ_TYPE_CQP
- I40IW_CQ_TYPE_IEQ
- I40IW_CQ_TYPE_ILQ
- I40IW_CQ_TYPE_IWARP
- I40IW_CQ_VALID_MASK
- I40IW_CQ_VALID_SHIFT
- I40IW_CQ_WQEIDX_MASK
- I40IW_CQ_WQEIDX_SHIFT
- I40IW_DB_ADDR_OFFSET
- I40IW_DB_ID_ZERO
- I40IW_DDP_VER
- I40IW_DEBUG_AEQ
- I40IW_DEBUG_ALL
- I40IW_DEBUG_CM
- I40IW_DEBUG_CQ
- I40IW_DEBUG_CQE
- I40IW_DEBUG_CQP
- I40IW_DEBUG_DCB
- I40IW_DEBUG_DEV
- I40IW_DEBUG_ERR
- I40IW_DEBUG_HMC
- I40IW_DEBUG_IEQ
- I40IW_DEBUG_ILQ
- I40IW_DEBUG_INIT
- I40IW_DEBUG_MR
- I40IW_DEBUG_NONE
- I40IW_DEBUG_PBLE
- I40IW_DEBUG_PUDA
- I40IW_DEBUG_QP
- I40IW_DEBUG_USER
- I40IW_DEBUG_VERBS
- I40IW_DEBUG_VIRT
- I40IW_DEBUG_WQE
- I40IW_DEC_BP_REFCNT
- I40IW_DEC_PD_REFCNT
- I40IW_DEC_SD_REFCNT
- I40IW_DEFAULT_MTU
- I40IW_DEFAULT_RETRANS
- I40IW_DEFAULT_RETRYS
- I40IW_DEFAULT_REXMIT_THRESH
- I40IW_DEFAULT_RTT_VAR
- I40IW_DEFAULT_SS_THRESH
- I40IW_DEFAULT_TTL
- I40IW_DMA_COHERENT
- I40IW_DONE_COUNT
- I40IW_DO_NOT_SEND_RESET_EVENT
- I40IW_DRV_OPT_DISABLE_FIRST_WRITE
- I40IW_DRV_OPT_DISABLE_INTF
- I40IW_DRV_OPT_DISABLE_INT_MOD
- I40IW_DRV_OPT_DISABLE_MPA_CRC
- I40IW_DRV_OPT_DISABLE_VIRT_WQ
- I40IW_DRV_OPT_DUAL_LOGICAL_PORT
- I40IW_DRV_OPT_ENABLE_MPA_VER_0
- I40IW_DRV_OPT_ENABLE_MSI
- I40IW_DRV_OPT_ENABLE_PAU
- I40IW_DRV_OPT_MCAST_LOGPORT_MAP
- I40IW_DRV_OPT_NO_INLINE_DATA
- I40IW_D_H
- I40IW_ERR_BACKING_PAGE_ERROR
- I40IW_ERR_BAD_IWARP_CQE
- I40IW_ERR_BAD_PTR
- I40IW_ERR_BAD_STAG
- I40IW_ERR_BUF_TOO_SHORT
- I40IW_ERR_CONFIG
- I40IW_ERR_CQP_COMPL_ERROR
- I40IW_ERR_CQ_COMPL_ERROR
- I40IW_ERR_DEVICE_NOT_SUPPORTED
- I40IW_ERR_FIRMWARE_API_VERSION
- I40IW_ERR_FLUSHED_QUEUE
- I40IW_ERR_INVALID_AEQ_ID
- I40IW_ERR_INVALID_ALIGNMENT
- I40IW_ERR_INVALID_ARP_INDEX
- I40IW_ERR_INVALID_CEQ_ID
- I40IW_ERR_INVALID_CQ_ID
- I40IW_ERR_INVALID_FPM_FUNC_ID
- I40IW_ERR_INVALID_FRAG_COUNT
- I40IW_ERR_INVALID_HMCFN_ID
- I40IW_ERR_INVALID_HMC_OBJ_COUNT
- I40IW_ERR_INVALID_HMC_OBJ_INDEX
- I40IW_ERR_INVALID_INLINE_DATA_SIZE
- I40IW_ERR_INVALID_MAC_ADDR
- I40IW_ERR_INVALID_PAGE_DESC_INDEX
- I40IW_ERR_INVALID_PBLE_INDEX
- I40IW_ERR_INVALID_PD_ID
- I40IW_ERR_INVALID_PUSH_PAGE_INDEX
- I40IW_ERR_INVALID_QP_ID
- I40IW_ERR_INVALID_SD_INDEX
- I40IW_ERR_INVALID_SD_TYPE
- I40IW_ERR_INVALID_SIZE
- I40IW_ERR_INVALID_SRQ_ARM_LIMIT
- I40IW_ERR_INVALID_VF_ID
- I40IW_ERR_MEMCPY_FAILED
- I40IW_ERR_MPA_CRC
- I40IW_ERR_NOT_IMPLEMENTED
- I40IW_ERR_NOT_READY
- I40IW_ERR_NO_MEMORY
- I40IW_ERR_NO_PBLCHUNKS_AVAILABLE
- I40IW_ERR_NO_TXBUFS
- I40IW_ERR_NVM
- I40IW_ERR_NVM_BLANK_MODE
- I40IW_ERR_NVM_CHECKSUM
- I40IW_ERR_OPCODE_MISMATCH
- I40IW_ERR_PARAM
- I40IW_ERR_PE_DOORBELL_NOT_ENABLED
- I40IW_ERR_QP_INVALID_MSG_SIZE
- I40IW_ERR_QP_TOOMANY_WRS_POSTED
- I40IW_ERR_QUEUE_DESTROYED
- I40IW_ERR_QUEUE_EMPTY
- I40IW_ERR_RESET_FAILED
- I40IW_ERR_RING_FULL
- I40IW_ERR_RING_FULL2
- I40IW_ERR_RING_FULL3
- I40IW_ERR_SEQ_NUM
- I40IW_ERR_SRQ_ENABLED
- I40IW_ERR_SWFW_SYNC
- I40IW_ERR_TIMEOUT
- I40IW_ERR_list_empty
- I40IW_EVENT_TIMEOUT
- I40IW_EXTENDED_CQE_SIZE
- I40IW_FIRST_NON_PF_STAT
- I40IW_FIRST_USER_QP_ID
- I40IW_FIRST_VF_FPM_ID
- I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK
- I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK
- I40IW_FW_VERSION
- I40IW_GET_CURRENT_AEQ_ELEMENT
- I40IW_GET_CURRENT_CEQ_ELEMENT
- I40IW_GET_CURRENT_CQ_ELEMENT
- I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT
- I40IW_HMC_DIRECT_BP_SIZE
- I40IW_HMC_H
- I40IW_HMC_INFO_SIGNATURE
- I40IW_HMC_IW_APBVT_ENTRY
- I40IW_HMC_IW_ARP
- I40IW_HMC_IW_CQ
- I40IW_HMC_IW_FSIAV
- I40IW_HMC_IW_FSIMC
- I40IW_HMC_IW_HTE
- I40IW_HMC_IW_MAX
- I40IW_HMC_IW_MR
- I40IW_HMC_IW_PBLE
- I40IW_HMC_IW_Q1
- I40IW_HMC_IW_Q1FL
- I40IW_HMC_IW_QP
- I40IW_HMC_IW_SRQ
- I40IW_HMC_IW_TIMER
- I40IW_HMC_IW_XF
- I40IW_HMC_IW_XFFL
- I40IW_HMC_MAX_BP_COUNT
- I40IW_HMC_MAX_SD_COUNT
- I40IW_HMC_PAGED_BP_SHIFT
- I40IW_HMC_PAGED_BP_SIZE
- I40IW_HMC_PD_BP_BUF_ALIGNMENT
- I40IW_HMC_PD_CNT_IN_SD
- I40IW_HMC_PROFILE_DEFAULT
- I40IW_HMC_PROFILE_EQUAL
- I40IW_HMC_PROFILE_FAVOR_VF
- I40IW_HOST_CTX_ALIGNMENT_MASK
- I40IW_HW_DBG_HMC_INVALID_BP_MARK
- I40IW_HW_IRD_SETTING_16
- I40IW_HW_IRD_SETTING_2
- I40IW_HW_IRD_SETTING_32
- I40IW_HW_IRD_SETTING_4
- I40IW_HW_IRD_SETTING_64
- I40IW_HW_IRD_SETTING_8
- I40IW_HW_PAGE_SIZE
- I40IW_HW_STAT_INDEX_IP4RXDISCARD
- I40IW_HW_STAT_INDEX_IP4RXFRAGS
- I40IW_HW_STAT_INDEX_IP4RXMCPKTS
- I40IW_HW_STAT_INDEX_IP4RXOCTS
- I40IW_HW_STAT_INDEX_IP4RXPKTS
- I40IW_HW_STAT_INDEX_IP4RXTRUNC
- I40IW_HW_STAT_INDEX_IP4TXFRAGS
- I40IW_HW_STAT_INDEX_IP4TXMCPKTS
- I40IW_HW_STAT_INDEX_IP4TXNOROUTE
- I40IW_HW_STAT_INDEX_IP4TXOCTS
- I40IW_HW_STAT_INDEX_IP4TXPKTS
- I40IW_HW_STAT_INDEX_IP6RXDISCARD
- I40IW_HW_STAT_INDEX_IP6RXFRAGS
- I40IW_HW_STAT_INDEX_IP6RXMCPKTS
- I40IW_HW_STAT_INDEX_IP6RXOCTS
- I40IW_HW_STAT_INDEX_IP6RXPKTS
- I40IW_HW_STAT_INDEX_IP6RXTRUNC
- I40IW_HW_STAT_INDEX_IP6TXFRAGS
- I40IW_HW_STAT_INDEX_IP6TXMCPKTS
- I40IW_HW_STAT_INDEX_IP6TXNOROUTE
- I40IW_HW_STAT_INDEX_IP6TXOCTS
- I40IW_HW_STAT_INDEX_IP6TXPKTS
- I40IW_HW_STAT_INDEX_MAX_32
- I40IW_HW_STAT_INDEX_MAX_64
- I40IW_HW_STAT_INDEX_RDMARXRDS
- I40IW_HW_STAT_INDEX_RDMARXSNDS
- I40IW_HW_STAT_INDEX_RDMARXWRS
- I40IW_HW_STAT_INDEX_RDMATXRDS
- I40IW_HW_STAT_INDEX_RDMATXSNDS
- I40IW_HW_STAT_INDEX_RDMATXWRS
- I40IW_HW_STAT_INDEX_RDMAVBND
- I40IW_HW_STAT_INDEX_RDMAVINV
- I40IW_HW_STAT_INDEX_TCPRTXSEG
- I40IW_HW_STAT_INDEX_TCPRXOPTERR
- I40IW_HW_STAT_INDEX_TCPRXPROTOERR
- I40IW_HW_STAT_INDEX_TCPRXSEGS
- I40IW_HW_STAT_INDEX_TCPTXSEG
- I40IW_HW_VERSION
- I40IW_IEQ_MPA_FRAMING
- I40IW_INC_BP_REFCNT
- I40IW_INC_PD_REFCNT
- I40IW_INC_SD_REFCNT
- I40IW_INVALIDATE_PF_HMC_PD
- I40IW_INVALIDATE_VF_HMC_PD
- I40IW_INVALID_FCN_ID
- I40IW_INVALID_PUSH_PAGE_INDEX
- I40IW_INVALID_WQE_INDEX
- I40IW_IW_H
- I40IW_LEVEL_0
- I40IW_LEVEL_1
- I40IW_LEVEL_2
- I40IW_LONG_TIME
- I40IW_MACIP_ADD
- I40IW_MACIP_DELETE
- I40IW_MAC_HLEN
- I40IW_MANAGE_APBVT_ADD
- I40IW_MANAGE_APBVT_DEL
- I40IW_MAX_AEQ_ENTRIES
- I40IW_MAX_CEQID
- I40IW_MAX_CEQ_ENTRIES
- I40IW_MAX_CQID
- I40IW_MAX_CQ_SIZE
- I40IW_MAX_IETF_SIZE
- I40IW_MAX_INBOUND_MESSAGE_SIZE
- I40IW_MAX_INLINE_DATA_SIZE
- I40IW_MAX_IRD_SIZE
- I40IW_MAX_IW_QP_ID
- I40IW_MAX_MR_SIZE
- I40IW_MAX_ORD_SIZE
- I40IW_MAX_OUTBOUND_MESSAGE_SIZE
- I40IW_MAX_PAGES_PER_FMR
- I40IW_MAX_PDS
- I40IW_MAX_PE_ENABLED_VF_COUNT
- I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE
- I40IW_MAX_PUSH_PAGE_COUNT
- I40IW_MAX_QP_WRS
- I40IW_MAX_QUANTAS_PER_WR
- I40IW_MAX_RQ_WQE_SHIFT
- I40IW_MAX_SD_ENTRIES
- I40IW_MAX_SGE_RD
- I40IW_MAX_SQ_PAYLOAD_SIZE
- I40IW_MAX_STATS_COUNT
- I40IW_MAX_TIMEOUT
- I40IW_MAX_USER_PRIORITY
- I40IW_MAX_VF_FPM_ID
- I40IW_MAX_VF_PER_PF
- I40IW_MAX_WQE_SIZE_RQ
- I40IW_MAX_WQ_ENTRIES
- I40IW_MAX_WQ_FRAGMENT_COUNT
- I40IW_MIN_AEQ_ENTRIES
- I40IW_MIN_CEQID
- I40IW_MIN_CEQ_ENTRIES
- I40IW_MIN_CQID
- I40IW_MIN_CQ_SIZE
- I40IW_MIN_IW_QP_ID
- I40IW_MIN_PAGES_PER_FMR
- I40IW_MPA_REQUEST_ACCEPT
- I40IW_MPA_REQUEST_REJECT
- I40IW_MSIX_TABLE_SIZE
- I40IW_MTU_TO_MSS_IPV4
- I40IW_MTU_TO_MSS_IPV6
- I40IW_NOT_SUPPORTED
- I40IW_NO_ALLOC
- I40IW_NO_QSET
- I40IW_NO_VLAN
- I40IW_OP_TYPE_BIND_MW
- I40IW_OP_TYPE_FAST_REG_NSMR
- I40IW_OP_TYPE_INV_STAG
- I40IW_OP_TYPE_NOP
- I40IW_OP_TYPE_RDMA_READ
- I40IW_OP_TYPE_RDMA_READ_INV_STAG
- I40IW_OP_TYPE_RDMA_WRITE
- I40IW_OP_TYPE_REC
- I40IW_OP_TYPE_SEND
- I40IW_OP_TYPE_SEND_INV
- I40IW_OP_TYPE_SEND_SOL
- I40IW_OP_TYPE_SEND_SOL_INV
- I40IW_OSDEP_H
- I40IW_PAGE_SIZE_2M
- I40IW_PAGE_SIZE_4K
- I40IW_PASSIVE_STATE_INDICATED
- I40IW_PBLE_H
- I40IW_PE_DB_SIZE_4M
- I40IW_PE_DB_SIZE_8M
- I40IW_PF_FIRST_PUSH_PAGE_INDEX
- I40IW_PKT_TYPE_ACK
- I40IW_PKT_TYPE_FIN
- I40IW_PKT_TYPE_RST
- I40IW_PKT_TYPE_SYN
- I40IW_PKT_TYPE_SYNACK
- I40IW_PKT_TYPE_UNKNOWN
- I40IW_PUDA_H
- I40IW_PUDA_RSRC_TYPE_IEQ
- I40IW_PUDA_RSRC_TYPE_ILQ
- I40IW_PUSH_OFFSET
- I40IW_P_H
- I40IW_Q2_ALIGNMENT_MASK
- I40IW_Q2_BUFFER_SIZE
- I40IW_QHASH_MANAGE_TYPE_ADD
- I40IW_QHASH_MANAGE_TYPE_DELETE
- I40IW_QHASH_MANAGE_TYPE_MODIFY
- I40IW_QHASH_TYPE_TCP_ESTABLISHED
- I40IW_QHASH_TYPE_TCP_SYN
- I40IW_QP_CTX_SIZE
- I40IW_QP_DBSA_HW_SQ_TAIL_MASK
- I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT
- I40IW_QP_STATE_CLOSING
- I40IW_QP_STATE_ERROR
- I40IW_QP_STATE_IDLE
- I40IW_QP_STATE_INVALID
- I40IW_QP_STATE_RESERVED
- I40IW_QP_STATE_RTS
- I40IW_QP_STATE_TERMINATE
- I40IW_QP_SW_MAX_RQ_QUANTAS
- I40IW_QP_SW_MAX_SQ_QUANTAS
- I40IW_QP_SW_MIN_WQSIZE
- I40IW_QP_TYPE_CQP
- I40IW_QP_TYPE_IWARP
- I40IW_QP_TYPE_UDA
- I40IW_QP_WQE_MAX_SIZE
- I40IW_QP_WQE_MIN_SIZE
- I40IW_QUERY_FPM_BUF_SIZE
- I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_MASK
- I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT
- I40IW_QUERY_FPM_HTMULTIPLIER_MASK
- I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT
- I40IW_QUERY_FPM_MAX_CEQS_MASK
- I40IW_QUERY_FPM_MAX_CEQS_SHIFT
- I40IW_QUERY_FPM_MAX_CQS_MASK
- I40IW_QUERY_FPM_MAX_CQS_SHIFT
- I40IW_QUERY_FPM_MAX_PE_SDS_MASK
- I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT
- I40IW_QUERY_FPM_MAX_QPS_MASK
- I40IW_QUERY_FPM_MAX_QPS_SHIFT
- I40IW_QUERY_FPM_Q1BLOCKSIZE_MASK
- I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT
- I40IW_QUERY_FPM_TIMERBUCKET_MASK
- I40IW_QUERY_FPM_TIMERBUCKET_SHIFT
- I40IW_QUERY_FPM_XFBLOCKSIZE_MASK
- I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT
- I40IW_QUEUES_ALIGNMENT_MASK
- I40IW_RDMAP_VER
- I40IW_RDMA_MODE_IETF
- I40IW_RDMA_MODE_RDMAC
- I40IW_REGISTER_H
- I40IW_RETRY_TIMEOUT
- I40IW_RING_FULL_ERR
- I40IW_RING_GETCURRENT_HEAD
- I40IW_RING_GETCURRENT_TAIL
- I40IW_RING_GETSIZE
- I40IW_RING_GET_WQES_AVAILABLE
- I40IW_RING_INIT
- I40IW_RING_MORE_WORK
- I40IW_RING_MOVE_HEAD
- I40IW_RING_MOVE_HEAD_BY_COUNT
- I40IW_RING_MOVE_HEAD_NOCHECK
- I40IW_RING_MOVE_TAIL
- I40IW_RING_MOVE_TAIL_BY_COUNT
- I40IW_RING_SET_TAIL
- I40IW_RING_WORK_AVAILABLE
- I40IW_RQ_RSVD
- I40IW_RSRC_INDICATOR_TYPE_ADAPTER
- I40IW_RSRC_INDICATOR_TYPE_CQ
- I40IW_RSRC_INDICATOR_TYPE_QP
- I40IW_RSRC_INDICATOR_TYPE_SRQ
- I40IW_RSVD_MASK
- I40IW_RSVD_SHIFT
- I40IW_SD_BUF_ALIGNMENT
- I40IW_SD_TYPE_DIRECT
- I40IW_SD_TYPE_INVALID
- I40IW_SD_TYPE_PAGED
- I40IW_SEND_RESET_EVENT
- I40IW_SHADOWAREA_MASK
- I40IW_SHADOW_AREA_SIZE
- I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_MASK
- I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT
- I40IW_SHORT_TIME
- I40IW_SLEEP_COUNT
- I40IW_SQ_RSVD
- I40IW_STAG_STATE_INVALID
- I40IW_STAG_STATE_VALID
- I40IW_STAG_TYPE_NONSHARED
- I40IW_STAG_TYPE_SHARED
- I40IW_STATE_SYN_SEND
- I40IW_STATUS_H
- I40IW_SUCCESS
- I40IW_TCP_STATE_CLOSED
- I40IW_TCP_STATE_CLOSE_WAIT
- I40IW_TCP_STATE_CLOSING
- I40IW_TCP_STATE_ESTABLISHED
- I40IW_TCP_STATE_FIN_WAIT_1
- I40IW_TCP_STATE_FIN_WAIT_2
- I40IW_TCP_STATE_LAST_ACK
- I40IW_TCP_STATE_LISTEN
- I40IW_TCP_STATE_NON_EXISTENT
- I40IW_TCP_STATE_RESERVED_1
- I40IW_TCP_STATE_RESERVED_2
- I40IW_TCP_STATE_RESERVED_3
- I40IW_TCP_STATE_RESERVED_4
- I40IW_TCP_STATE_SYN_RECEIVED
- I40IW_TCP_STATE_TIME_WAIT
- I40IW_TERM_DONE
- I40IW_TERM_RCVD
- I40IW_TERM_SENT
- I40IW_TIMER_NODE_CLEANUP
- I40IW_TIMER_TYPE_CLOSE
- I40IW_TIMER_TYPE_RECV
- I40IW_TIMER_TYPE_SEND
- I40IW_TYPE_H
- I40IW_UDA_HDRLEN_MASK
- I40IW_UDA_HDRLEN_SHIFT
- I40IW_UDA_L3PROTO_MASK
- I40IW_UDA_L3PROTO_SHIFT
- I40IW_UDA_L4PROTO_MASK
- I40IW_UDA_L4PROTO_SHIFT
- I40IW_UDA_PAYLOADLEN_MASK
- I40IW_UDA_PAYLOADLEN_SHIFT
- I40IW_UDA_QPC_MAXFRAMESIZE_MASK
- I40IW_UDA_QPC_MAXFRAMESIZE_SHIFT
- I40IW_UDA_QPSQ_AVIDX_MASK
- I40IW_UDA_QPSQ_AVIDX_SHIFT
- I40IW_UDA_QPSQ_DOLOOPBACK_MASK
- I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT
- I40IW_UDA_QPSQ_IIPT_MASK
- I40IW_UDA_QPSQ_IIPT_SHIFT
- I40IW_UDA_QPSQ_IPLEN_MASK
- I40IW_UDA_QPSQ_IPLEN_SHIFT
- I40IW_UDA_QPSQ_L4LEN_MASK
- I40IW_UDA_QPSQ_L4LEN_SHIFT
- I40IW_UDA_QPSQ_L4T_MASK
- I40IW_UDA_QPSQ_L4T_SHIFT
- I40IW_UDA_QPSQ_MACLEN_MASK
- I40IW_UDA_QPSQ_MACLEN_SHIFT
- I40IW_UDA_QPSQ_NEXT_HEADER_MASK
- I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT
- I40IW_UDA_QPSQ_OPCODE_MASK
- I40IW_UDA_QPSQ_OPCODE_SHIFT
- I40IW_UDA_QPSQ_SIGCOMPL_MASK
- I40IW_UDA_QPSQ_SIGCOMPL_SHIFT
- I40IW_UDA_QPSQ_VALID_MASK
- I40IW_UDA_QPSQ_VALID_SHIFT
- I40IW_UPDATE_SD_BUF_SIZE
- I40IW_USER_H
- I40IW_VCHNL_CHNL_VER_V0
- I40IW_VCHNL_EVENT_TIMEOUT
- I40IW_VCHNL_MAX_VF_MSG_SIZE
- I40IW_VCHNL_OP_ADD_HMC_OBJ_RANGE
- I40IW_VCHNL_OP_ADD_HMC_OBJ_RANGE_V0
- I40IW_VCHNL_OP_DEL_HMC_OBJ_RANGE
- I40IW_VCHNL_OP_DEL_HMC_OBJ_RANGE_V0
- I40IW_VCHNL_OP_GET_HMC_FCN
- I40IW_VCHNL_OP_GET_HMC_FCN_V0
- I40IW_VCHNL_OP_GET_STATS
- I40IW_VCHNL_OP_GET_STATS_V0
- I40IW_VCHNL_OP_GET_VER
- I40IW_VCHNL_OP_GET_VER_V0
- I40IW_VERBS_H
- I40IW_VF_DB_ADDR_OFFSET
- I40IW_VF_FIRST_PUSH_PAGE_INDEX
- I40IW_VF_H
- I40IW_VF_PUSH_OFFSET
- I40IW_VIRTCHNL_H
- I40IW_VLAN_PRIO_SHIFT
- I40IW_VLAN_TAG_VALID_MASK
- I40IW_VLAN_TAG_VALID_SHIFT
- I40IW_VMALLOC
- I40IW_WQE_SIZE
- I40IW_WQE_SIZE_64
- I40_DDP_FLASH_REGION
- I46
- I460_4M_PS
- I460_AGPSIZ_MASK
- I460_BAPBASE_ENABLE
- I460_GXBCTL_BWC
- I460_GXBCTL_OOG
- I460_IOPAGES_PER_KPAGE
- I460_IO_PAGE_SHIFT
- I460_KPAGES_PER_IOPAGE
- I460_LARGE_IO_PAGES
- I460_SRAM_IO_DISABLE
- I4_BITS
- I4_FIFO_SIZE
- I5
- I5000P
- I5000V
- I5000X
- I5000_REVISION
- I5100_AMIR_0
- I5100_AMIR_1
- I5100_CHANNELS
- I5100_DIMM_ADDR_LINES
- I5100_DINJ0
- I5100_DMIR
- I5100_EMASK_MEM
- I5100_FERR_NF_MEM
- I5100_FERR_NF_MEM_ANY_MASK
- I5100_FERR_NF_MEM_M10ERR_MASK
- I5100_FERR_NF_MEM_M11ERR_MASK
- I5100_FERR_NF_MEM_M12ERR_MASK
- I5100_FERR_NF_MEM_M14ERR_MASK
- I5100_FERR_NF_MEM_M15ERR_MASK
- I5100_FERR_NF_MEM_M16ERR_MASK
- I5100_FERR_NF_MEM_M1ERR_MASK
- I5100_FERR_NF_MEM_M4ERR_MASK
- I5100_FERR_NF_MEM_M5ERR_MASK
- I5100_FERR_NF_MEM_M6ERR_MASK
- I5100_MAX_DIMM_SLOTS_PER_CHAN
- I5100_MAX_DMIRS
- I5100_MAX_RANKS_PER_CHAN
- I5100_MAX_RANKS_PER_DIMM
- I5100_MAX_RANK_INTERLEAVE
- I5100_MC
- I5100_MC_SCRBDONE_MASK
- I5100_MC_SCRBEN_MASK
- I5100_MEM0EINJMSK0
- I5100_MEM0EINJMSK1
- I5100_MEM1EINJMSK0
- I5100_MEM1EINJMSK1
- I5100_MEMXEINJMSK0_EINJEN
- I5100_MIR0
- I5100_MIR1
- I5100_MS
- I5100_MTR_0
- I5100_MTR_4
- I5100_NERR_NF_MEM
- I5100_NRECMEMA
- I5100_NRECMEMB
- I5100_RECMEMA
- I5100_RECMEMB
- I5100_REDMEMA
- I5100_REDMEMB
- I5100_SCRUB_REFRESH_RATE
- I5100_SPDCMD
- I5100_SPDDATA
- I5100_TOLM
- I5100_VALIDLOG
- I5400_REVISION
- I596_NULL
- I596_TOTAL_SIZE
- I5K_REG_AMB_BASE_ADDR
- I5K_REG_AMB_LEN_ADDR
- I5K_REG_CHAN0_PRESENCE_ADDR
- I5K_REG_CHAN1_PRESENCE_ADDR
- I6050U_FW_FILE_NAME_v1_5
- I642U64
- I6ALU
- I7
- I71
- I7300_REVISION
- I740_FFIX
- I740_ID_AGP
- I740_ID_PCI
- I740_MAX_VCO_FREQ
- I740_REF_FREQ
- I740_RFREQ
- I740_RFREQ_FIX
- I7CORE_REVISION
- I8
- I801_BLOCK_DATA
- I801_BLOCK_LAST
- I801_BLOCK_PROC_CALL
- I801_BYTE
- I801_BYTE_DATA
- I801_I2C_BLOCK_DATA
- I801_I2C_BLOCK_LAST
- I801_PEC_EN
- I801_PROC_CALL
- I801_QUICK
- I801_START
- I801_WORD_DATA
- I802_DEBUG_INC
- I8042_AUX_IRQ
- I8042_AUX_PHYS_DESC
- I8042_AUX_PORT_NO
- I8042_BUFFER_SIZE
- I8042_CMD_AUX_DISABLE
- I8042_CMD_AUX_ENABLE
- I8042_CMD_AUX_LOOP
- I8042_CMD_AUX_SEND
- I8042_CMD_AUX_TEST
- I8042_CMD_CTL_RCTR
- I8042_CMD_CTL_TEST
- I8042_CMD_CTL_WCTR
- I8042_CMD_KBD_DISABLE
- I8042_CMD_KBD_ENABLE
- I8042_CMD_KBD_LOOP
- I8042_CMD_KBD_TEST
- I8042_CMD_MUX_PFX
- I8042_CMD_MUX_SEND
- I8042_COMMAND_REG
- I8042_CTL_TIMEOUT
- I8042_CTR_AUXDIS
- I8042_CTR_AUXINT
- I8042_CTR_IGNKEYLOCK
- I8042_CTR_KBDDIS
- I8042_CTR_KBDINT
- I8042_CTR_XLATE
- I8042_DATA_REG
- I8042_KBD_IRQ
- I8042_KBD_PHYS_DESC
- I8042_KBD_PORT_NO
- I8042_MAP_IRQ
- I8042_MUX_PHYS_DESC
- I8042_MUX_PORT_NO
- I8042_NUM_MUX_PORTS
- I8042_NUM_PORTS
- I8042_REGION_SIZE
- I8042_REGION_START
- I8042_RESET_ALWAYS
- I8042_RESET_DEFAULT
- I8042_RESET_NEVER
- I8042_RESET_ON_S2RAM
- I8042_RET_CTL_TEST
- I8042_STATUS_REG
- I8042_STR_AUXDATA
- I8042_STR_CMDDAT
- I8042_STR_IBF
- I8042_STR_KEYLOCK
- I8042_STR_MUXERR
- I8042_STR_OBF
- I8042_STR_PARITY
- I8042_STR_TIMEOUT
- I80IFCONFAx
- I80IFCONFBx
- I80IFEN_ENABLE
- I80_HW_TRG
- I810REG_HWSTAM
- I810REG_INT_ENABLE_R
- I810REG_INT_IDENTITY_R
- I810REG_INT_MASK_R
- I810_ADDR
- I810_BACK
- I810_BASE
- I810_BUF_CLIENT
- I810_BUF_FREE
- I810_BUF_HARDWARE
- I810_BUF_MAPPED
- I810_BUF_UNMAPPED
- I810_CLEANUP_DMA
- I810_CTXREG_AA
- I810_CTXREG_B1
- I810_CTXREG_B2
- I810_CTXREG_CF0
- I810_CTXREG_CF1
- I810_CTXREG_FOG
- I810_CTXREG_LCS
- I810_CTXREG_MA0
- I810_CTXREG_MA1
- I810_CTXREG_MA2
- I810_CTXREG_MC0
- I810_CTXREG_MC1
- I810_CTXREG_MC2
- I810_CTXREG_MT
- I810_CTXREG_PV
- I810_CTXREG_SDM
- I810_CTXREG_ST0
- I810_CTXREG_ST1
- I810_CTXREG_VF
- I810_CTXREG_ZA
- I810_CTX_SETUP_SIZE
- I810_DEPTH
- I810_DEREF
- I810_DEREF16
- I810_DESTREG_DI0
- I810_DESTREG_DI1
- I810_DESTREG_DR0
- I810_DESTREG_DR1
- I810_DESTREG_DR2
- I810_DESTREG_DR3
- I810_DESTREG_DR4
- I810_DESTREG_DV0
- I810_DESTREG_DV1
- I810_DEST_SETUP_SIZE
- I810_DMA_BUF_NR
- I810_DMA_BUF_ORDER
- I810_DMA_BUF_SZ
- I810_DRAM_CTL
- I810_DRAM_ROW_0
- I810_DRAM_ROW_0_SDRAM
- I810_FRONT
- I810_GFX_MEM_WIN_32M
- I810_GFX_MEM_WIN_SIZE
- I810_GMADR_BAR
- I810_GMS
- I810_GMS_DISABLE
- I810_GTT_ORDER
- I810_INIT_DMA
- I810_INIT_DMA_1_4
- I810_LOG_MIN_TEX_REGION_SIZE
- I810_MMADR_BAR
- I810_NR_SAREA_CLIPRECTS
- I810_NR_TEX_REGIONS
- I810_PAGESIZE
- I810_PGETBL_CTL
- I810_PGETBL_ENABLED
- I810_PTE_BASE
- I810_PTE_LOCAL
- I810_PTE_MAIN_UNCACHED
- I810_PTE_VALID
- I810_READ
- I810_READ16
- I810_SMRAM_MISCC
- I810_TEXREG_MCS
- I810_TEXREG_MF
- I810_TEXREG_MI0
- I810_TEXREG_MI1
- I810_TEXREG_MI2
- I810_TEXREG_MI3
- I810_TEXREG_MLC
- I810_TEXREG_MLL
- I810_TEX_SETUP_SIZE
- I810_UPLOAD_BUFFERS
- I810_UPLOAD_CLIPRECTS
- I810_UPLOAD_CTX
- I810_UPLOAD_TEX0
- I810_UPLOAD_TEX0IMAGE
- I810_UPLOAD_TEX1
- I810_UPLOAD_TEX1IMAGE
- I810_VERBOSE
- I810_WRITE
- I810_WRITE16
- I82443BXGX_DRAMC
- I82443BXGX_DRAMC_DRAM_IS_EDO
- I82443BXGX_DRAMC_DRAM_IS_RSDRAM
- I82443BXGX_DRAMC_DRAM_IS_SDRAM
- I82443BXGX_DRAMC_OFFSET_DT
- I82443BXGX_DRB
- I82443BXGX_EAP
- I82443BXGX_EAP_OFFSET_EAP
- I82443BXGX_EAP_OFFSET_MBE
- I82443BXGX_EAP_OFFSET_SBE
- I82443BXGX_ERRCMD
- I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE
- I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE
- I82443BXGX_ERRSTS
- I82443BXGX_ERRSTS_OFFSET_MBFRE
- I82443BXGX_ERRSTS_OFFSET_MEF
- I82443BXGX_ERRSTS_OFFSET_SBFRE
- I82443BXGX_ERRSTS_OFFSET_SEF
- I82443BXGX_NBXCFG
- I82443BXGX_NBXCFG_INTEGRITY_EC
- I82443BXGX_NBXCFG_INTEGRITY_ECC
- I82443BXGX_NBXCFG_INTEGRITY_NONE
- I82443BXGX_NBXCFG_INTEGRITY_SCRUB
- I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ
- I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY
- I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE
- I82443BXGX_NBXCFG_OFFSET_NON_ECCROW
- I82443BXGX_NR_CHANS
- I82443BXGX_NR_CSROWS
- I82443BXGX_NR_DIMMS
- I82503
- I8253_BASE_REG
- I8254_BCD
- I8254_BINARY
- I8254_CMD_READBACK
- I8254_COUNTER0_REG
- I8254_COUNTER1_REG
- I8254_COUNTER2_REG
- I8254_CTRL_LATCH
- I8254_CTRL_LSB_MSB
- I8254_CTRL_LSB_ONLY
- I8254_CTRL_MSB_ONLY
- I8254_CTRL_READBACK
- I8254_CTRL_READBACK_COUNT
- I8254_CTRL_READBACK_SEL_CTR
- I8254_CTRL_READBACK_STATUS
- I8254_CTRL_REG
- I8254_CTRL_RW
- I8254_CTRL_SEL_CTR
- I8254_IO16
- I8254_IO32
- I8254_IO8
- I8254_MAX_COUNT
- I8254_MODE0
- I8254_MODE1
- I8254_MODE2
- I8254_MODE3
- I8254_MODE4
- I8254_MODE5
- I8254_OSC_BASE_100KHZ
- I8254_OSC_BASE_10KHZ
- I8254_OSC_BASE_10MHZ
- I8254_OSC_BASE_1KHZ
- I8254_OSC_BASE_1MHZ
- I8254_OSC_BASE_2MHZ
- I8254_OSC_BASE_4MHZ
- I8254_OSC_BASE_5MHZ
- I8254_PORT_CONTROL
- I8254_PORT_COUNTER0
- I8254_SELECT_COUNTER0
- I8254_STATUS_NOTREADY
- I82553AB
- I82553C
- I82555
- I8255_4020_REG
- I8255_CTRL_A_IO
- I8255_CTRL_A_MODE
- I8255_CTRL_B_IO
- I8255_CTRL_B_MODE
- I8255_CTRL_CW
- I8255_CTRL_C_HI_IO
- I8255_CTRL_C_LO_IO
- I8255_CTRL_REG
- I8255_DATA_A_REG
- I8255_DATA_B_REG
- I8255_DATA_C_REG
- I8255_SIZE
- I82577_ADDR_REG
- I82577_CFG_ASSERT_CRS_ON_TX
- I82577_CFG_ENABLE_DOWNSHIFT
- I82577_CFG_REG
- I82577_CTRL_REG
- I82577_DSTATUS_CABLE_LENGTH
- I82577_DSTATUS_CABLE_LENGTH_SHIFT
- I82577_E_PHY_ID
- I82577_MSE_THRESHOLD
- I82577_PHY_CTRL2_AUTO_MDI_MDIX
- I82577_PHY_CTRL2_MANUAL_MDIX
- I82577_PHY_CTRL2_MDIX_CFG_MASK
- I82577_PHY_CTRL_2
- I82577_PHY_DIAG_STATUS
- I82577_PHY_LBK_CTRL
- I82577_PHY_STATUS2_MDIX
- I82577_PHY_STATUS2_REV_POLARITY
- I82577_PHY_STATUS2_SPEED_1000MBPS
- I82577_PHY_STATUS2_SPEED_MASK
- I82577_PHY_STATUS_2
- I82578_ADDR_REG
- I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
- I82578_EPSCR_DOWNSHIFT_ENABLE
- I82578_E_PHY_ID
- I82579_EEE_1000_SUPPORTED
- I82579_EEE_100_SUPPORTED
- I82579_EEE_ADVERTISEMENT
- I82579_EEE_CAPABILITY
- I82579_EEE_LP_ABILITY
- I82579_EEE_PCS_STATUS
- I82579_EMI_ADDR
- I82579_EMI_DATA
- I82579_E_PHY_ID
- I82579_LPI_100_PLL_SHUT
- I82579_LPI_CTRL
- I82579_LPI_CTRL_1000_ENABLE
- I82579_LPI_CTRL_100_ENABLE
- I82579_LPI_CTRL_ENABLE_MASK
- I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
- I82579_LPI_PLL_SHUT
- I82579_LPI_UPDATE_TIMER
- I82579_MSE_LINK_DOWN
- I82579_MSE_THRESHOLD
- I82579_RX_CONFIG
- I82580_ADDR_REG
- I82580_CFG_ASSERT_CRS_ON_TX
- I82580_CFG_ENABLE_DOWNSHIFT
- I82580_CFG_REG
- I82580_CTRL_DOWNSHIFT_MASK
- I82580_CTRL_REG
- I82580_DSTATUS_CABLE_LENGTH
- I82580_DSTATUS_CABLE_LENGTH_SHIFT
- I82580_I_PHY_ID
- I82580_PHY_CTRL2_AUTO_MDI_MDIX
- I82580_PHY_CTRL2_MANUAL_MDIX
- I82580_PHY_CTRL2_MDIX_CFG_MASK
- I82580_PHY_CTRL_2
- I82580_PHY_DIAG_STATUS
- I82580_PHY_LBK_CTRL
- I82580_PHY_STATUS2_MDIX
- I82580_PHY_STATUS2_REV_POLARITY
- I82580_PHY_STATUS2_SPEED_1000MBPS
- I82580_PHY_STATUS2_SPEED_100MBPS
- I82580_PHY_STATUS2_SPEED_MASK
- I82580_PHY_STATUS_2
- I82586_NULL
- I8259A_IRQ_BASE
- I8259_CASCADE_IRQ
- I82802AB
- I82802AC
- I82860
- I82860_DERRCTL_STS
- I82860_EAP
- I82860_ERRSTS
- I82860_GBA
- I82860_GBA_MASK
- I82860_GBA_SHIFT
- I82860_MCHCFG
- I82875P
- I82875P_BAR6
- I82875P_DERRSYN
- I82875P_DES
- I82875P_DRA
- I82875P_DRB
- I82875P_DRB_SHIFT
- I82875P_DRC
- I82875P_EAP
- I82875P_ERRCMD
- I82875P_ERRSTS
- I82875P_NR_CSROWS
- I82875P_NR_DIMMS
- I82875P_PCICMD6
- I82975X
- I82975X_BNKARC
- I82975X_C0BNKARC
- I82975X_C1BNKARC
- I82975X_DERRSYN
- I82975X_DES
- I82975X_DRA
- I82975X_DRA_CH0R01
- I82975X_DRA_CH0R23
- I82975X_DRA_CH1R01
- I82975X_DRA_CH1R23
- I82975X_DRB
- I82975X_DRB_CH0R0
- I82975X_DRB_CH0R1
- I82975X_DRB_CH0R2
- I82975X_DRB_CH0R3
- I82975X_DRB_CH1R0
- I82975X_DRB_CH1R1
- I82975X_DRB_CH1R2
- I82975X_DRB_CH1R3
- I82975X_DRB_SHIFT
- I82975X_DRC
- I82975X_DRC_CH0M0
- I82975X_DRC_CH0M1
- I82975X_DRC_CH1M0
- I82975X_DRC_CH1M1
- I82975X_DRC_M1
- I82975X_EAP
- I82975X_ERRCMD
- I82975X_ERRSTS
- I82975X_MCHBAR
- I82975X_NR_CSROWS
- I82975X_NR_DIMMS
- I82975X_SCICMD
- I82975X_SMICMD
- I82975X_XEAP
- I830_BATCH_LIMIT
- I830_CLOCK_GATE
- I830_DRB3
- I830_ESMRAMC
- I830_FEATURES
- I830_FENCE_MAX_PITCH_VAL
- I830_FENCE_MAX_SIZE_VAL
- I830_FENCE_PITCH_SHIFT
- I830_FENCE_REG_VALID
- I830_FENCE_SIZE_BITS
- I830_FENCE_START_MASK
- I830_FENCE_TILING_Y_SHIFT
- I830_FIFO_LINE_SIZE
- I830_FIFO_SIZE
- I830_GMCH_CTRL
- I830_GMCH_ENABLED
- I830_GMCH_GMS_DISABLED
- I830_GMCH_GMS_LOCAL
- I830_GMCH_GMS_MASK
- I830_GMCH_GMS_STOLEN_1024
- I830_GMCH_GMS_STOLEN_512
- I830_GMCH_GMS_STOLEN_8192
- I830_GMCH_MEM_128M
- I830_GMCH_MEM_64M
- I830_GMCH_MEM_MASK
- I830_HIC
- I830_L2_CACHE_CLOCK_GATE_DISABLE
- I830_PIPES_POWER_DOMAINS
- I830_PTE_SYSTEM_CACHED
- I830_RDRAM_CHANNEL_TYPE
- I830_RDRAM_DDT
- I830_RDRAM_ND
- I830_TLB_ENTRIES
- I830_TSEG_SIZE_1M
- I830_TSEG_SIZE_512K
- I830_WA_SIZE
- I845_CURSOR_OFFSETS
- I845_ESMRAMC
- I845_FEATURES
- I845_PIPE_OFFSETS
- I845_TSEG_SIZE_1M
- I845_TSEG_SIZE_512K
- I845_TSEG_SIZE_MASK
- I852_GM
- I852_GME
- I855GM_FIFO_SIZE
- I855_CLOCK_100_133
- I855_CLOCK_100_200
- I855_CLOCK_133_200
- I855_CLOCK_166_250
- I855_CLOCK_CONTROL_MASK
- I855_GM
- I855_GMCH_GMS_MASK
- I855_GMCH_GMS_STOLEN_0M
- I855_GMCH_GMS_STOLEN_16M
- I855_GMCH_GMS_STOLEN_1M
- I855_GMCH_GMS_STOLEN_32M
- I855_GMCH_GMS_STOLEN_4M
- I855_GMCH_GMS_STOLEN_8M
- I855_GME
- I855_HPLLCC
- I85X_CAPID
- I85X_DRB3
- I85X_ESMRAMC
- I85X_VARIANT_MASK
- I85X_VARIANT_SHIFT
- I865_TOUD
- I8K_AC
- I8K_BATTERY
- I8K_BIOS_VERSION
- I8K_FAN_HIGH
- I8K_FAN_LEFT
- I8K_FAN_LOW
- I8K_FAN_MAX
- I8K_FAN_MAX_RPM
- I8K_FAN_MULT
- I8K_FAN_OFF
- I8K_FAN_RIGHT
- I8K_FAN_TURBO
- I8K_FN_DOWN
- I8K_FN_MASK
- I8K_FN_MUTE
- I8K_FN_NONE
- I8K_FN_SHIFT
- I8K_FN_STATUS
- I8K_FN_UP
- I8K_GET_FAN
- I8K_GET_SPEED
- I8K_GET_TEMP
- I8K_HWMON_HAVE_FAN1
- I8K_HWMON_HAVE_FAN2
- I8K_HWMON_HAVE_FAN3
- I8K_HWMON_HAVE_TEMP1
- I8K_HWMON_HAVE_TEMP10
- I8K_HWMON_HAVE_TEMP2
- I8K_HWMON_HAVE_TEMP3
- I8K_HWMON_HAVE_TEMP4
- I8K_HWMON_HAVE_TEMP5
- I8K_HWMON_HAVE_TEMP6
- I8K_HWMON_HAVE_TEMP7
- I8K_HWMON_HAVE_TEMP8
- I8K_HWMON_HAVE_TEMP9
- I8K_MACHINE_ID
- I8K_MAX_TEMP
- I8K_POWER_AC
- I8K_POWER_BATTERY
- I8K_POWER_STATUS
- I8K_PROC
- I8K_PROC_FMT
- I8K_SET_FAN
- I8K_SMM_FN_STATUS
- I8K_SMM_GET_DELL_SIG1
- I8K_SMM_GET_DELL_SIG2
- I8K_SMM_GET_FAN
- I8K_SMM_GET_FAN_TYPE
- I8K_SMM_GET_NOM_SPEED
- I8K_SMM_GET_SPEED
- I8K_SMM_GET_TEMP
- I8K_SMM_GET_TEMP_TYPE
- I8K_SMM_POWER_STATUS
- I8K_SMM_SET_FAN
- I8K_VOL_DOWN
- I8K_VOL_MUTE
- I8K_VOL_UP
- I8_32
- I8_8
- I8_BITS
- I8_FIFO_SIZE
- I915_ACTIVE_GRAB_BIT
- I915_ASLE_INTERRUPT
- I915_BD_BF_CLOCK_GATE_DISABLE
- I915_BIT_6_SWIZZLE_9
- I915_BIT_6_SWIZZLE_9_10
- I915_BIT_6_SWIZZLE_9_10_11
- I915_BIT_6_SWIZZLE_9_10_17
- I915_BIT_6_SWIZZLE_9_11
- I915_BIT_6_SWIZZLE_9_17
- I915_BIT_6_SWIZZLE_NONE
- I915_BIT_6_SWIZZLE_UNKNOWN
- I915_BOX_FLIP
- I915_BOX_LOST_CONTEXT
- I915_BOX_RING_EMPTY
- I915_BOX_TEXTURE_LOAD
- I915_BOX_WAIT
- I915_BO_CACHE_COHERENT_FOR_READ
- I915_BO_CACHE_COHERENT_FOR_WRITE
- I915_BSD_USER_INTERRUPT
- I915_BUDDY_ALLOCATED
- I915_BUDDY_FREE
- I915_BUDDY_HEADER_OFFSET
- I915_BUDDY_HEADER_ORDER
- I915_BUDDY_HEADER_STATE
- I915_BUDDY_MAX_ORDER
- I915_BUDDY_SPLIT
- I915_BY_CLOCK_GATE_DISABLE
- I915_CACHE_L3_LLC
- I915_CACHE_LLC
- I915_CACHE_NONE
- I915_CACHE_WT
- I915_CACHING_CACHED
- I915_CACHING_DISPLAY
- I915_CACHING_NONE
- I915_CC_CLOCK_GATE_DISABLE
- I915_CLFLUSH_FORCE
- I915_CLFLUSH_SYNC
- I915_CLIENT_FAST_HANG_JIFFIES
- I915_CLIENT_SCORE_BANNED
- I915_CLIENT_SCORE_CONTEXT_BAN
- I915_CLIENT_SCORE_HANG_FAST
- I915_CMD_HASH_ORDER
- I915_COLOR_UNEVICTABLE
- I915_COMPONENT_AUDIO
- I915_COMPONENT_HDCP
- I915_CONTEXT_CLONE_ENGINES
- I915_CONTEXT_CLONE_FLAGS
- I915_CONTEXT_CLONE_SCHEDATTR
- I915_CONTEXT_CLONE_SSEU
- I915_CONTEXT_CLONE_TIMELINE
- I915_CONTEXT_CLONE_UNKNOWN
- I915_CONTEXT_CLONE_VM
- I915_CONTEXT_CREATE_EXT_CLONE
- I915_CONTEXT_CREATE_EXT_SETPARAM
- I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE
- I915_CONTEXT_CREATE_FLAGS_UNKNOWN
- I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS
- I915_CONTEXT_DEFAULT_PRIORITY
- I915_CONTEXT_ENGINES_EXT_BOND
- I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE
- I915_CONTEXT_MAX_USER_PRIORITY
- I915_CONTEXT_MIN_USER_PRIORITY
- I915_CONTEXT_PARAM_BANNABLE
- I915_CONTEXT_PARAM_BAN_PERIOD
- I915_CONTEXT_PARAM_ENGINES
- I915_CONTEXT_PARAM_GTT_SIZE
- I915_CONTEXT_PARAM_NO_ERROR_CAPTURE
- I915_CONTEXT_PARAM_NO_ZEROMAP
- I915_CONTEXT_PARAM_PRIORITY
- I915_CONTEXT_PARAM_RECOVERABLE
- I915_CONTEXT_PARAM_SSEU
- I915_CONTEXT_PARAM_VM
- I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX
- I915_DEBUGFS_ENTRIES
- I915_DEBUG_INTERRUPT
- I915_DEFINE_CONTEXT_ENGINES_BOND
- I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE
- I915_DEFINE_CONTEXT_PARAM_ENGINES
- I915_DEIER_REG
- I915_DEPENDENCY_ALLOC
- I915_DEPENDENCY_EXTERNAL
- I915_DISPATCH_PINNED
- I915_DISPATCH_SECURE
- I915_DISPLAY_CLOCK_190_200_MHZ
- I915_DISPLAY_CLOCK_333_MHZ
- I915_DISPLAY_CLOCK_MASK
- I915_DISPLAY_PIPE_A_DPBM_INTERRUPT
- I915_DISPLAY_PIPE_A_EVENT_INTERRUPT
- I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT
- I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT
- I915_DISPLAY_PIPE_B_DPBM_INTERRUPT
- I915_DISPLAY_PIPE_B_EVENT_INTERRUPT
- I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT
- I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT
- I915_DISPLAY_PIPE_C_DPBM_INTERRUPT
- I915_DISPLAY_PIPE_C_EVENT_INTERRUPT
- I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT
- I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT
- I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
- I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
- I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT
- I915_DISPLAY_PORT_INTERRUPT
- I915_DI_CLOCK_GATE_DISABLE
- I915_DM_CLOCK_GATE_DISABLE
- I915_DRM_SUSPEND_HIBERNATE
- I915_DRM_SUSPEND_IDLE
- I915_DRM_SUSPEND_MEM
- I915_ENGINE_CLASS_COPY
- I915_ENGINE_CLASS_INVALID
- I915_ENGINE_CLASS_INVALID_NONE
- I915_ENGINE_CLASS_INVALID_VIRTUAL
- I915_ENGINE_CLASS_RENDER
- I915_ENGINE_CLASS_VIDEO
- I915_ENGINE_CLASS_VIDEO_ENHANCE
- I915_ENGINE_DEAD_TIMEOUT
- I915_ENGINE_HAS_PREEMPTION
- I915_ENGINE_HAS_SEMAPHORES
- I915_ENGINE_IS_VIRTUAL
- I915_ENGINE_NEEDS_BREADCRUMB_TASKLET
- I915_ENGINE_REQUIRES_CMD_PARSER
- I915_ENGINE_SAMPLE_COUNT
- I915_ENGINE_SUPPORTS_STATS
- I915_ENGINE_USING_CMD_PARSER
- I915_ENGINE_WEDGED_TIMEOUT
- I915_ERROR_CAPTURE
- I915_ERROR_INSTRUCTION
- I915_ERROR_MEMORY_REFRESH
- I915_ERROR_PAGE_TABLE
- I915_ERROR_UEVENT
- I915_EXEC_BATCH_FIRST
- I915_EXEC_BLT
- I915_EXEC_BSD
- I915_EXEC_BSD_DEFAULT
- I915_EXEC_BSD_MASK
- I915_EXEC_BSD_RING1
- I915_EXEC_BSD_RING2
- I915_EXEC_BSD_SHIFT
- I915_EXEC_CONSTANTS_ABSOLUTE
- I915_EXEC_CONSTANTS_MASK
- I915_EXEC_CONSTANTS_REL_GENERAL
- I915_EXEC_CONSTANTS_REL_SURFACE
- I915_EXEC_CONTEXT_ID_MASK
- I915_EXEC_DEFAULT
- I915_EXEC_FENCE_ARRAY
- I915_EXEC_FENCE_IN
- I915_EXEC_FENCE_OUT
- I915_EXEC_FENCE_SIGNAL
- I915_EXEC_FENCE_SUBMIT
- I915_EXEC_FENCE_WAIT
- I915_EXEC_GEN7_SOL_RESET
- I915_EXEC_HANDLE_LUT
- I915_EXEC_IS_PINNED
- I915_EXEC_NO_RELOC
- I915_EXEC_RENDER
- I915_EXEC_RESOURCE_STREAMER
- I915_EXEC_RING_MASK
- I915_EXEC_SECURE
- I915_EXEC_VEBOX
- I915_FENCE_FLAG_ACTIVE
- I915_FENCE_FLAG_SIGNAL
- I915_FENCE_GFP
- I915_FENCE_MAX_PITCH_VAL
- I915_FENCE_REG_NONE
- I915_FENCE_SIZE_BITS
- I915_FENCE_START_MASK
- I915_FENCE_TIMEOUT
- I915_FIFO_LINE_SIZE
- I915_FIFO_SIZE
- I915_FL_CLOCK_GATE_DISABLE
- I915_FORMAT_MOD_X_TILED
- I915_FORMAT_MOD_Y_TILED
- I915_FORMAT_MOD_Y_TILED_CCS
- I915_FORMAT_MOD_Yf_TILED
- I915_FORMAT_MOD_Yf_TILED_CCS
- I915_GCFGC
- I915_GC_RENDER_CLOCK_166_MHZ
- I915_GC_RENDER_CLOCK_200_MHZ
- I915_GC_RENDER_CLOCK_333_MHZ
- I915_GC_RENDER_CLOCK_MASK
- I915_GDRST
- I915_GEM_DOMAIN_COMMAND
- I915_GEM_DOMAIN_CPU
- I915_GEM_DOMAIN_GTT
- I915_GEM_DOMAIN_INSTRUCTION
- I915_GEM_DOMAIN_RENDER
- I915_GEM_DOMAIN_SAMPLER
- I915_GEM_DOMAIN_VERTEX
- I915_GEM_DOMAIN_WC
- I915_GEM_GPU_DOMAINS
- I915_GEM_HWS_PREEMPT
- I915_GEM_HWS_PREEMPT_ADDR
- I915_GEM_HWS_SCRATCH
- I915_GEM_HWS_SCRATCH_ADDR
- I915_GEM_HWS_SEQNO
- I915_GEM_HWS_SEQNO_ADDR
- I915_GEM_IDLE_TIMEOUT
- I915_GEM_IOCTLS_H
- I915_GEM_OBJECT_ASYNC_CANCEL
- I915_GEM_OBJECT_HAS_STRUCT_PAGE
- I915_GEM_OBJECT_IS_PROXY
- I915_GEM_OBJECT_IS_SHRINKABLE
- I915_GEM_OBJECT_NO_GGTT
- I915_GEM_OBJECT_UNBIND_ACTIVE
- I915_GEM_PPGTT_ALIASING
- I915_GEM_PPGTT_FULL
- I915_GEM_PPGTT_NONE
- I915_GFP_ALLOW_FAIL
- I915_GGTT_VIEW_NORMAL
- I915_GGTT_VIEW_PARTIAL
- I915_GGTT_VIEW_REMAPPED
- I915_GGTT_VIEW_ROTATED
- I915_GMADR_BAR
- I915_GMCH_GMS_STOLEN_48M
- I915_GMCH_GMS_STOLEN_64M
- I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT
- I915_GTT_MAX_PAGE_SIZE
- I915_GTT_MIN_ALIGNMENT
- I915_GTT_OFFSET_NONE
- I915_GTT_PAGE_MASK
- I915_GTT_PAGE_SHIFT
- I915_GTT_PAGE_SIZE
- I915_GTT_PAGE_SIZE_2M
- I915_GTT_PAGE_SIZE_4K
- I915_GTT_PAGE_SIZE_64K
- I915_HAS_HOTPLUG
- I915_HDMI_LPE_AUDIO_BASE
- I915_HDMI_LPE_AUDIO_SIZE
- I915_HI_DISPBASE
- I915_HWB_OOM_INTERRUPT
- I915_HWS_CSB_BUF0_INDEX
- I915_HWS_CSB_WRITE_INDEX
- I915_IDLE_ENGINES_TIMEOUT
- I915_IFPADDR
- I915_ISP_INTERRUPT
- I915_IZ_CLOCK_GATE_DISABLE
- I915_L3_PARITY_UEVENT
- I915_LOG_MIN_TEX_REGION_SIZE
- I915_LOW_FREQUENCY_ENABLE
- I915_LO_DISPBASE
- I915_LPE_PIPE_A_INTERRUPT
- I915_LPE_PIPE_B_INTERRUPT
- I915_LPE_PIPE_C_INTERRUPT
- I915_MADV_DONTNEED
- I915_MADV_WILLNEED
- I915_MAP_FORCE_WB
- I915_MAP_FORCE_WC
- I915_MAP_OVERRIDE
- I915_MAP_WB
- I915_MAP_WC
- I915_MASTER_ERROR_INTERRUPT
- I915_MAX_NUM_FENCES
- I915_MAX_NUM_FENCE_BITS
- I915_MAX_PHYS
- I915_MAX_PIPES
- I915_MAX_PLANES
- I915_MAX_PORTS
- I915_MAX_SLICES
- I915_MAX_SUBSLICES
- I915_MAX_TC_PORTS
- I915_MAX_TRANSCODERS
- I915_MAX_VCS
- I915_MAX_VECS
- I915_MAX_WM
- I915_MEM_REGION_AGP
- I915_MIPIA_INTERRUPT
- I915_MIPIC_INTERRUPT
- I915_MISC_INTERRUPT
- I915_MMADR_BAR
- I915_MMAP_WC
- I915_MM_NORMAL
- I915_MM_SHRINKER
- I915_MOCS_CACHED
- I915_MOCS_PTE
- I915_MOCS_UNCACHED
- I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP
- I915_MODE_FLAG_INHERITED
- I915_MODE_FLAG_USE_SCANLINE_COUNTER
- I915_MOTION_COMP_CLOCK_GATE_DISABLE
- I915_MPEG_CLOCK_GATE_DISABLE
- I915_NR_TEX_REGIONS
- I915_NUM_ENGINES
- I915_NUM_PHYS_VLV
- I915_NUM_PLLS
- I915_OA_FORMAT_A12
- I915_OA_FORMAT_A12_B8_C8
- I915_OA_FORMAT_A13
- I915_OA_FORMAT_A13_B8_C8
- I915_OA_FORMAT_A29
- I915_OA_FORMAT_A32u40_A4u32_B8_C8
- I915_OA_FORMAT_A45_B8_C8
- I915_OA_FORMAT_B4_C8
- I915_OA_FORMAT_B4_C8_A16
- I915_OA_FORMAT_C4_B8
- I915_OA_FORMAT_MAX
- I915_OVERLAY_DEPTH_MASK
- I915_OVERLAY_DISABLE_DEST_COLORKEY
- I915_OVERLAY_ENABLE
- I915_OVERLAY_FLAGS_MASK
- I915_OVERLAY_NO_SWAP
- I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
- I915_OVERLAY_RGB
- I915_OVERLAY_RGB15
- I915_OVERLAY_RGB16
- I915_OVERLAY_RGB24
- I915_OVERLAY_SWAP_MASK
- I915_OVERLAY_TYPE_MASK
- I915_OVERLAY_UPDATE_ATTRS
- I915_OVERLAY_UPDATE_GAMMA
- I915_OVERLAY_UV_SWAP
- I915_OVERLAY_YUV410
- I915_OVERLAY_YUV411
- I915_OVERLAY_YUV420
- I915_OVERLAY_YUV422
- I915_OVERLAY_YUV_PACKED
- I915_OVERLAY_YUV_PLANAR
- I915_OVERLAY_Y_AND_UV_SWAP
- I915_OVERLAY_Y_SWAP
- I915_PARAMS_FOR_EACH
- I915_PARAM_ALLOW_BATCHBUFFER
- I915_PARAM_CHIPSET_ID
- I915_PARAM_CMD_PARSER_VERSION
- I915_PARAM_CS_TIMESTAMP_FREQUENCY
- I915_PARAM_EU_TOTAL
- I915_PARAM_HAS_ALIASING_PPGTT
- I915_PARAM_HAS_BLT
- I915_PARAM_HAS_BSD
- I915_PARAM_HAS_BSD2
- I915_PARAM_HAS_COHERENT_PHYS_GTT
- I915_PARAM_HAS_COHERENT_RINGS
- I915_PARAM_HAS_CONTEXT_ISOLATION
- I915_PARAM_HAS_EXECBUF2
- I915_PARAM_HAS_EXEC_ASYNC
- I915_PARAM_HAS_EXEC_BATCH_FIRST
- I915_PARAM_HAS_EXEC_CAPTURE
- I915_PARAM_HAS_EXEC_CONSTANTS
- I915_PARAM_HAS_EXEC_FENCE
- I915_PARAM_HAS_EXEC_FENCE_ARRAY
- I915_PARAM_HAS_EXEC_HANDLE_LUT
- I915_PARAM_HAS_EXEC_NO_RELOC
- I915_PARAM_HAS_EXEC_SOFTPIN
- I915_PARAM_HAS_EXEC_SUBMIT_FENCE
- I915_PARAM_HAS_GEM
- I915_PARAM_HAS_GEN7_SOL_RESET
- I915_PARAM_HAS_GPU_RESET
- I915_PARAM_HAS_LLC
- I915_PARAM_HAS_OVERLAY
- I915_PARAM_HAS_PAGEFLIPPING
- I915_PARAM_HAS_PINNED_BATCHES
- I915_PARAM_HAS_POOLED_EU
- I915_PARAM_HAS_PRIME_VMAP_FLUSH
- I915_PARAM_HAS_RELAXED_DELTA
- I915_PARAM_HAS_RELAXED_FENCING
- I915_PARAM_HAS_RESOURCE_STREAMER
- I915_PARAM_HAS_SCHEDULER
- I915_PARAM_HAS_SECURE_BATCHES
- I915_PARAM_HAS_SEMAPHORES
- I915_PARAM_HAS_VEBOX
- I915_PARAM_HAS_WAIT_TIMEOUT
- I915_PARAM_HAS_WT
- I915_PARAM_HUC_STATUS
- I915_PARAM_IRQ_ACTIVE
- I915_PARAM_LAST_DISPATCH
- I915_PARAM_MIN_EU_IN_POOL
- I915_PARAM_MMAP_GTT_COHERENT
- I915_PARAM_MMAP_GTT_VERSION
- I915_PARAM_MMAP_VERSION
- I915_PARAM_NUM_FENCES_AVAIL
- I915_PARAM_REVISION
- I915_PARAM_SLICE_MASK
- I915_PARAM_SUBSLICE_MASK
- I915_PARAM_SUBSLICE_TOTAL
- I915_PDES
- I915_PDE_MASK
- I915_PERF_FLAG_DISABLED
- I915_PERF_FLAG_FD_CLOEXEC
- I915_PERF_FLAG_FD_NONBLOCK
- I915_PERF_IOCTL_DISABLE
- I915_PERF_IOCTL_ENABLE
- I915_PIPE_CONTROL_NOTIFY_INTERRUPT
- I915_PI_CLOCK_GATE_DISABLE
- I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE
- I915_PMU_ACTUAL_FREQUENCY
- I915_PMU_CLASS_SHIFT
- I915_PMU_ENGINE_BUSY
- I915_PMU_ENGINE_SEMA
- I915_PMU_ENGINE_WAIT
- I915_PMU_FORMAT_ATTR
- I915_PMU_INTERRUPTS
- I915_PMU_LAST
- I915_PMU_MASK_BITS
- I915_PMU_RC6_RESIDENCY
- I915_PMU_REQUESTED_FREQUENCY
- I915_PMU_SAMPLE_BITS
- I915_PMU_SAMPLE_INSTANCE_BITS
- I915_PMU_SAMPLE_MASK
- I915_PM_INTERRUPT
- I915_PRIORITY_COUNT
- I915_PRIORITY_DISPLAY
- I915_PRIORITY_INVALID
- I915_PRIORITY_MASK
- I915_PRIORITY_MAX
- I915_PRIORITY_MIN
- I915_PRIORITY_NORMAL
- I915_PRIORITY_NOSEMAPHORE
- I915_PRIORITY_UNPREEMPTABLE
- I915_PRIORITY_WAIT
- I915_PSR_DEBUG_DEFAULT
- I915_PSR_DEBUG_DISABLE
- I915_PSR_DEBUG_ENABLE
- I915_PSR_DEBUG_FORCE_PSR1
- I915_PSR_DEBUG_IRQ
- I915_PSR_DEBUG_MODE_MASK
- I915_PS_CLOCK_GATE_DISABLE
- I915_PTES
- I915_PTE_BAR
- I915_PTE_MASK
- I915_READ
- I915_READ_FW
- I915_REG_READ_8B_WA
- I915_REQUEST_H
- I915_REQUEST_NOPREEMPT
- I915_REQUEST_WAITBOOST
- I915_RESET_BACKOFF
- I915_RESET_ENGINE
- I915_RESET_H
- I915_RESET_MODESET
- I915_RESET_TIMEOUT
- I915_RESET_UEVENT
- I915_RND_STATE
- I915_RND_STATE_INITIALIZER
- I915_RND_SUBSTATE
- I915_SAGV_DISABLED
- I915_SAGV_ENABLED
- I915_SAGV_NOT_CONTROLLED
- I915_SAGV_UNKNOWN
- I915_SAMPLE_BUSY
- I915_SAMPLE_SEMA
- I915_SAMPLE_WAIT
- I915_SCATTERLIST_H
- I915_SCHEDULER_CAP_ENABLED
- I915_SCHEDULER_CAP_ENGINE_BUSY_STATS
- I915_SCHEDULER_CAP_PREEMPTION
- I915_SCHEDULER_CAP_PRIORITY
- I915_SCHEDULER_CAP_SEMAPHORES
- I915_SCHED_HAS_SEMAPHORE_CHAIN
- I915_SC_CLOCK_GATE_DISABLE
- I915_SELFTEST_DECLARE
- I915_SELFTEST_ONLY
- I915_SEQNO_DEAD_TIMEOUT
- I915_SETPARAM_ALLOW_BATCHBUFFER
- I915_SETPARAM_NUM_USED_FENCES
- I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
- I915_SETPARAM_USE_MI_BATCHBUFFER_START
- I915_SET_COLORKEY_DESTINATION
- I915_SET_COLORKEY_NONE
- I915_SET_COLORKEY_SOURCE
- I915_SF_SE_CLOCK_GATE_DISABLE
- I915_SHRINK_ACTIVE
- I915_SHRINK_BOUND
- I915_SHRINK_UNBOUND
- I915_SHRINK_VMAPS
- I915_SHRINK_WRITEBACK
- I915_SH_SV_CLOCK_GATE_DISABLE
- I915_STATE_WARN
- I915_STATE_WARN_ON
- I915_SW_FENCE_CHECKED_BIT
- I915_SW_FENCE_FLAG_ALLOC
- I915_SW_FENCE_MASK
- I915_SW_FENCE_PRIVATE_BIT
- I915_SW_FENCE_WORK_H
- I915_SYNC_STATUS_INTERRUPT
- I915_TILING_LAST
- I915_TILING_NONE
- I915_TILING_X
- I915_TILING_Y
- I915_TIMELINE_H
- I915_USERPTR_READ_ONLY
- I915_USERPTR_UNSYNCHRONIZED
- I915_USER_EXTENSIONS_H
- I915_USER_INTERRUPT
- I915_USER_PRIORITY
- I915_USER_PRIORITY_SHIFT
- I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC
- I915_VIDEO_CLASS_CAPABILITY_HEVC
- I915_VLD_IP_PR_CLOCK_GATE_DISABLE
- I915_VMA_BIND_MASK
- I915_VMA_CAN_FENCE
- I915_VMA_GGTT
- I915_VMA_GGTT_WRITE
- I915_VMA_GLOBAL_BIND
- I915_VMA_LOCAL_BIND
- I915_VMA_PIN_MASK
- I915_VMA_PIN_OVERFLOW
- I915_VMA_RELEASE_MAP
- I915_VMA_USERFAULT
- I915_VMA_USERFAULT_BIT
- I915_WAIT_ALL
- I915_WAIT_FOR_IDLE_BOOST
- I915_WAIT_INTERRUPTIBLE
- I915_WAIT_LOCKED
- I915_WAIT_PRIORITY
- I915_WEDGED
- I915_WINVALID_INTERRUPT
- I915_WM_CLOCK_GATE_DISABLE
- I915_WRITE
- I915_WRITE_FW
- I945_FIFO_SIZE
- I945_GC_RENDER_CLOCK_166_MHZ
- I945_GC_RENDER_CLOCK_200_MHZ
- I945_GC_RENDER_CLOCK_250_MHZ
- I945_GC_RENDER_CLOCK_400_MHZ
- I945_GC_RENDER_CLOCK_MASK
- I965_COLORS
- I965_CURSOR_DFT_WM
- I965_CURSOR_FIFO
- I965_CURSOR_MAX_WM
- I965_DAP_CLOCK_GATE_DISABLE
- I965_DG_CLOCK_GATE_DISABLE
- I965_DM_CLOCK_GATE_DISABLE
- I965_EM_CLOCK_GATE_DISABLE
- I965_EU_CLOCK_GATE_DISABLE
- I965_FBC_CLOCK_GATE_DISABLE
- I965_FENCE_MAX_PITCH_VAL
- I965_FENCE_PAGE
- I965_FENCE_PITCH_SHIFT
- I965_FENCE_REG_VALID
- I965_FENCE_TILING_Y_SHIFT
- I965_FIFO_SIZE
- I965_FT_CLOCK_GATE_DISABLE
- I965_GC_RENDER_CLOCK_267_MHZ
- I965_GC_RENDER_CLOCK_333_MHZ
- I965_GC_RENDER_CLOCK_444_MHZ
- I965_GC_RENDER_CLOCK_533_MHZ
- I965_GC_RENDER_CLOCK_MASK
- I965_GW_CLOCK_GATE_DISABLE
- I965_IC_CLOCK_GATE_DISABLE
- I965_IFPADDR
- I965_IF_CLOCK_GATE_DISABLE
- I965_ISC_CLOCK_GATE_DISABLE
- I965_MARI_CLOCK_GATE_DISABLE
- I965_MASF_CLOCK_GATE_DISABLE
- I965_MAWB_CLOCK_GATE_DISABLE
- I965_MSAC
- I965_MT_CLOCK_GATE_DISABLE
- I965_PGETBL_CTL2
- I965_PGETBL_SIZE_128KB
- I965_PGETBL_SIZE_1MB
- I965_PGETBL_SIZE_1_5MB
- I965_PGETBL_SIZE_256KB
- I965_PGETBL_SIZE_2MB
- I965_PGETBL_SIZE_512KB
- I965_PGETBL_SIZE_MASK
- I965_PIPECONF_ACTIVE
- I965_PL_CLOCK_GATE_DISABLE
- I965_QC_CLOCK_GATE_DISABLE
- I965_RCC_CLOCK_GATE_DISABLE
- I965_RCPB_CLOCK_GATE_DISABLE
- I965_RCZ_CLOCK_GATE_DISABLE
- I965_ROC_CLOCK_GATE_DISABLE
- I965_SI_CLOCK_GATE_DISABLE
- I965_SO_CLOCK_GATE_DISABLE
- I965_TC_CLOCK_GATE_DISABLE
- I965_TD_CLOCK_GATE_DISABLE
- I965_UC_CLOCK_GATE_DISABLE
- I9XX_COLORS
- I9XX_CURSOR_OFFSETS
- I9XX_PIPE_OFFSETS
- IA16
- IA16_MASK
- IA32_EAX
- IA32_EBP
- IA32_EBX
- IA32_ECX
- IA32_EDI
- IA32_EDX
- IA32_ESI
- IA32_ESP
- IA32_JA
- IA32_JAE
- IA32_JB
- IA32_JBE
- IA32_JE
- IA32_JG
- IA32_JGE
- IA32_JL
- IA32_JLE
- IA32_JNE
- IA32_MISC_ENABLE
- IA32_MISC_TURBO_EN
- IA32_MTRR_DEF_TYPE_E
- IA32_MTRR_DEF_TYPE_FE
- IA32_MTRR_DEF_TYPE_TYPE_MASK
- IA32_NR_syscalls
- IA32_PAGE_OFFSET
- IA32_PERF_CTL
- IA32_PERF_TURBO_DIS
- IA32_PQR_ASSOC
- IA32_STACK_TOP
- IA32_SYSCALL_VECTOR
- IA5STR
- IA64_CMCP_VECTOR
- IA64_CMC_VECTOR
- IA64_CPEP_VECTOR
- IA64_CPE_VECTOR
- IA64_DCR_BE
- IA64_DCR_BE_BIT
- IA64_DCR_DA
- IA64_DCR_DA_BIT
- IA64_DCR_DD
- IA64_DCR_DD_BIT
- IA64_DCR_DK
- IA64_DCR_DK_BIT
- IA64_DCR_DM
- IA64_DCR_DM_BIT
- IA64_DCR_DP
- IA64_DCR_DP_BIT
- IA64_DCR_DR
- IA64_DCR_DR_BIT
- IA64_DCR_DX
- IA64_DCR_DX_BIT
- IA64_DCR_LC
- IA64_DCR_LC_BIT
- IA64_DCR_PP
- IA64_DCR_PP_BIT
- IA64_DEF_FIRST_DEVICE_VECTOR
- IA64_DEF_LAST_DEVICE_VECTOR
- IA64_FETCHADD
- IA64_FIRST_DEVICE_VECTOR
- IA64_FIRST_ROTATING_FR
- IA64_FIRST_STACKED_GR
- IA64_FW_CALL
- IA64_GRANULE_SHIFT
- IA64_GRANULE_SIZE
- IA64_HAS_EXTRA_STATE
- IA64_INIT_RESUME
- IA64_INIT_WARM_BOOT
- IA64_INTRINSIC_API
- IA64_INTRINSIC_MACRO
- IA64_IPI_DEFAULT_BASE_ADDR
- IA64_IPI_DM_EXTINT
- IA64_IPI_DM_INIT
- IA64_IPI_DM_INT
- IA64_IPI_DM_NMI
- IA64_IPI_DM_PMI
- IA64_IPI_LOCAL_TLB_FLUSH
- IA64_IPI_RESCHEDULE
- IA64_IPI_VECTOR
- IA64_IRQ_MOVE_VECTOR
- IA64_IRQ_REDIRECTED
- IA64_ISR_CODE_FC
- IA64_ISR_CODE_LFETCH
- IA64_ISR_CODE_MASK
- IA64_ISR_CODE_PROBE
- IA64_ISR_CODE_PROBEF
- IA64_ISR_CODE_TAK
- IA64_ISR_CODE_TPA
- IA64_ISR_IR
- IA64_ISR_IR_BIT
- IA64_ISR_NA
- IA64_ISR_NA_BIT
- IA64_ISR_R
- IA64_ISR_RS
- IA64_ISR_RS_BIT
- IA64_ISR_R_BIT
- IA64_ISR_SP
- IA64_ISR_SP_BIT
- IA64_ISR_W
- IA64_ISR_W_BIT
- IA64_ISR_X
- IA64_ISR_X_BIT
- IA64_KR
- IA64_KR_CURRENT
- IA64_KR_CURRENT_STACK
- IA64_KR_FPU_OWNER
- IA64_KR_IO_BASE
- IA64_KR_PER_CPU_DATA
- IA64_KR_PT_BASE
- IA64_KR_TSSD
- IA64_LAST_DEVICE_VECTOR
- IA64_LOG_COUNT
- IA64_LOG_CURR_BUFFER
- IA64_LOG_CURR_INDEX
- IA64_LOG_INDEX_DEC
- IA64_LOG_INDEX_INC
- IA64_LOG_LOCK
- IA64_LOG_LOCK_INIT
- IA64_LOG_NEXT_BUFFER
- IA64_LOG_NEXT_INDEX
- IA64_LOG_UNLOCK
- IA64_MAX_DEVICE_VECTORS
- IA64_MAX_LOGS
- IA64_MAX_LOG_TYPES
- IA64_MAX_PHYS_BITS
- IA64_MAX_RSVD_REGIONS
- IA64_MAX_VECTORED_IRQ
- IA64_MCA_COLD_BOOT
- IA64_MCA_CORRECTED
- IA64_MCA_DEBUG
- IA64_MCA_HALT
- IA64_MCA_NEW_CONTEXT
- IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA
- IA64_MCA_RENDEZ_CHECKIN_DONE
- IA64_MCA_RENDEZ_CHECKIN_INIT
- IA64_MCA_RENDEZ_CHECKIN_NOTDONE
- IA64_MCA_RENDEZ_TIMEOUT
- IA64_MCA_RENDEZ_VECTOR
- IA64_MCA_SAME_CONTEXT
- IA64_MCA_WAKEUP_VECTOR
- IA64_MCA_WARM_BOOT
- IA64_MIN_VECTORED_IRQ
- IA64_MLX_TEMPLATE
- IA64_MOVL_OPCODE
- IA64_NATIVE_DO_SAVE_MIN
- IA64_NATIVE_NR_IRQS
- IA64_NSEC_PER_CYC_SHIFT
- IA64_NUM_DBG_REGS
- IA64_NUM_DEVICE_VECTORS
- IA64_NUM_PHYS_STACK_REG
- IA64_NUM_VECTORS
- IA64_OPCODE_MASK
- IA64_OPCODE_SHIFT
- IA64_PERFMON_VECTOR
- IA64_PSR_AC
- IA64_PSR_AC_BIT
- IA64_PSR_BE
- IA64_PSR_BE_BIT
- IA64_PSR_BITS_TO_CLEAR
- IA64_PSR_BITS_TO_SET
- IA64_PSR_BN
- IA64_PSR_BN_BIT
- IA64_PSR_CPL
- IA64_PSR_CPL0_BIT
- IA64_PSR_CPL1_BIT
- IA64_PSR_DA
- IA64_PSR_DA_BIT
- IA64_PSR_DB
- IA64_PSR_DB_BIT
- IA64_PSR_DD
- IA64_PSR_DD_BIT
- IA64_PSR_DFH
- IA64_PSR_DFH_BIT
- IA64_PSR_DFL
- IA64_PSR_DFL_BIT
- IA64_PSR_DI
- IA64_PSR_DI_BIT
- IA64_PSR_DT
- IA64_PSR_DT_BIT
- IA64_PSR_ED
- IA64_PSR_ED_BIT
- IA64_PSR_I
- IA64_PSR_IA
- IA64_PSR_IA_BIT
- IA64_PSR_IC
- IA64_PSR_IC_BIT
- IA64_PSR_ID
- IA64_PSR_ID_BIT
- IA64_PSR_IS
- IA64_PSR_IS_BIT
- IA64_PSR_IT
- IA64_PSR_IT_BIT
- IA64_PSR_I_BIT
- IA64_PSR_LP
- IA64_PSR_LP_BIT
- IA64_PSR_MC
- IA64_PSR_MC_BIT
- IA64_PSR_MFH
- IA64_PSR_MFH_BIT
- IA64_PSR_MFL
- IA64_PSR_MFL_BIT
- IA64_PSR_PK
- IA64_PSR_PK_BIT
- IA64_PSR_PP
- IA64_PSR_PP_BIT
- IA64_PSR_RI
- IA64_PSR_RI_BIT
- IA64_PSR_RT
- IA64_PSR_RT_BIT
- IA64_PSR_SI
- IA64_PSR_SI_BIT
- IA64_PSR_SP
- IA64_PSR_SP_BIT
- IA64_PSR_SS
- IA64_PSR_SS_BIT
- IA64_PSR_TB
- IA64_PSR_TB_BIT
- IA64_PSR_UM
- IA64_PSR_UP
- IA64_PSR_UP_BIT
- IA64_RBS_OFFSET
- IA64_REGION_ID_KERNEL
- IA64_SAL_AP_EXTERNAL_INT
- IA64_SAL_OEMFUNC_MAX
- IA64_SAL_OEMFUNC_MIN
- IA64_SAL_PLATFORM_FEATURE_BUS_LOCK
- IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT
- IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT
- IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT
- IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT
- IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT
- IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT
- IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT
- IA64_SC_FLAG_FPH_VALID
- IA64_SC_FLAG_FPH_VALID_BIT
- IA64_SC_FLAG_IN_SYSCALL
- IA64_SC_FLAG_IN_SYSCALL_BIT
- IA64_SC_FLAG_ONSTACK
- IA64_SC_FLAG_ONSTACK_BIT
- IA64_SPURIOUS_INT_VECTOR
- IA64_STK_OFFSET
- IA64_THREAD_DBG_VALID
- IA64_THREAD_FPEMU_MASK
- IA64_THREAD_FPEMU_NOPRINT
- IA64_THREAD_FPEMU_SHIFT
- IA64_THREAD_FPEMU_SIGFPE
- IA64_THREAD_FPH_VALID
- IA64_THREAD_MIGRATION
- IA64_THREAD_PM_VALID
- IA64_THREAD_UAC_MASK
- IA64_THREAD_UAC_NOPRINT
- IA64_THREAD_UAC_SHIFT
- IA64_THREAD_UAC_SIGBUS
- IA64_TIMER_VECTOR
- IA64_TR_ALLOC_BASE
- IA64_TR_ALLOC_MAX
- IA64_TR_CURRENT_STACK
- IA64_TR_KERNEL
- IA64_TR_PALCODE
- IAA_MMIO
- IAA_NCRAM
- IAA_RAM
- IAA_REGISTER
- IACK_SC
- IACR_ADDR_MASK
- IACR_ADDR_SHIFT
- IACR_RDEN
- IACR_TSEL_MASK
- IACR_TSEL_MIB
- IACR_TSEL_SHIFT
- IADC_CH_SEL_CTL
- IADC_CONV_REQ
- IADC_CONV_REQ_SET
- IADC_CONV_TIME_MAX_US
- IADC_CONV_TIME_MIN_US
- IADC_DATA
- IADC_DEF_AVG_SAMPLES
- IADC_DEF_DECIMATION
- IADC_DEF_HW_SETTLE_TIME
- IADC_DEF_PRESCALING
- IADC_DIG_DEC_RATIO_SEL_SHIFT
- IADC_DIG_PARAM
- IADC_EN_CTL1
- IADC_EN_CTL1_SET
- IADC_EXT_OFFSET_CSP_CSN
- IADC_EXT_RSENSE
- IADC_FAST_AVG_CTL
- IADC_FAST_AVG_EN
- IADC_FAST_AVG_EN_SET
- IADC_FOLLOW_WARM_RB
- IADC_GAIN_17P857MV
- IADC_HW_SETTLE_DELAY
- IADC_INT_OFFSET_CSP2_CSN2
- IADC_INT_RSENSE
- IADC_INT_RSENSE_DEFAULT_GF
- IADC_INT_RSENSE_DEFAULT_SMIC
- IADC_INT_RSENSE_DEFAULT_VALUE
- IADC_INT_RSENSE_DEVIATION
- IADC_INT_RSENSE_IDEAL_VALUE
- IADC_MODE_CTL
- IADC_NOMINAL_RSENSE
- IADC_NOMINAL_RSENSE_SIGN_MASK
- IADC_OP_MODE_NORMAL
- IADC_OP_MODE_SHIFT
- IADC_PERH_RESET_CTL3
- IADC_PERPH_SUBTYPE
- IADC_PERPH_SUBTYPE_IADC
- IADC_PERPH_TYPE
- IADC_PERPH_TYPE_ADC
- IADC_REF_GAIN_MICRO_VOLTS
- IADC_REVISION2
- IADC_REVISION2_SUPPORTED_IADC
- IADC_SEC_ACCESS
- IADC_SEC_ACCESS_DATA
- IADC_STATUS1
- IADC_STATUS1_EOC
- IADC_STATUS1_OP_MODE
- IADC_STATUS1_REQ_STS
- IADC_STATUS1_REQ_STS_EOC_MASK
- IADC_TRIM_EN
- IADEV
- IAGC
- IAGFREELIST_LWM
- IAGFREE_LOCK
- IAGFREE_LOCK_INIT
- IAGFREE_UNLOCK
- IAGTOLBLK
- IAG_EXTENT_SIZE
- IAG_SIZE
- IALIAS_BASE
- IALIAS_SIZE
- IAL_CONT_ENTRY
- IAL_FLAG_MASK
- IAL_LAST_ENTRY
- IAMR_EX_BIT
- IANA_SPECIFIER_ID
- IANA_VXLAN_UDP_PORT
- IAP_MODE
- IAQ_BUFFER_DEFAULT_VALS
- IAQ_BUFFER_EMPTY
- IAQ_BUFFER_VALID
- IAR
- IARB
- IARCHIVE
- IAREAD
- IARTN_Q
- IAR_ABORT_STS
- IAR_ABORT_STS_PLL_ABORTED
- IAR_ABORT_STS_SW_ABORTED
- IAR_ABORT_STS_TC3_ABORTED
- IAR_ACKDELAY
- IAR_AFC
- IAR_AGC_HYS
- IAR_AGC_THR1
- IAR_AGC_THR2
- IAR_ANA_SPARE_IN
- IAR_ANA_SPARE_OUT1
- IAR_ANA_SPARE_OUT2
- IAR_ANT_AGC_CTRL
- IAR_ANT_AGC_CTRL_ANTX_MASK
- IAR_ANT_AGC_CTRL_ANTX_SHIFT
- IAR_ANT_AGC_CTRL_FAD_EN_MASK
- IAR_ANT_AGC_CTRL_FAD_EN_SHIFT
- IAR_ANT_PAD_CTRL
- IAR_ANT_PAD_CTRL_ANTX_CTRLMODE
- IAR_ANT_PAD_CTRL_ANTX_EN
- IAR_ANT_PAD_CTRL_ANTX_HZ
- IAR_ANT_PAD_CTRL_ANTX_POL
- IAR_ANT_PAD_CTRL_ANTX_POL_SHIFT
- IAR_ATM_CTRL1
- IAR_ATM_CTRL2
- IAR_ATM_CTRL3
- IAR_ATT_RSSI1
- IAR_ATT_RSSI2
- IAR_BSM_CTRL
- IAR_CCA1_ED_OFFSET_COMP
- IAR_CCA1_THRESH
- IAR_CCA2_CORR_PEAKS
- IAR_CCA2_CORR_THRESH
- IAR_CCA_CTRL
- IAR_CCA_CTRL_AGC_FRZ_EN
- IAR_CCA_CTRL_CCA3_AND_NOT_OR
- IAR_CCA_CTRL_CONT_RSSI_EN
- IAR_CCA_CTRL_LQI_RSSI_NOT_CORR
- IAR_CCA_CTRL_POWER_COMP_EN_CCA1
- IAR_CCA_CTRL_POWER_COMP_EN_ED
- IAR_CCA_CTRL_POWER_COMP_EN_LQI
- IAR_CCCA_BUSY_CNT
- IAR_CHF_CC1
- IAR_CHF_CC2
- IAR_CHF_CCL
- IAR_CHF_IBUF
- IAR_CHF_IL
- IAR_CHF_IRIN
- IAR_CHF_IROUT
- IAR_CHF_PMA_GAIN
- IAR_CHF_QBUF
- IAR_CHF_QL
- IAR_CHF_QRIN
- IAR_CHF_QROUT
- IAR_CHF_TEST_CTRL
- IAR_CORR_NVAL
- IAR_CORR_VT
- IAR_DATA
- IAR_DTM_CTRL1
- IAR_DTM_CTRL1_ATM_LOCKED
- IAR_DTM_CTRL1_DTM_EN
- IAR_DTM_CTRL1_PAGE0
- IAR_DTM_CTRL1_PAGE1
- IAR_DTM_CTRL1_PAGE2
- IAR_DTM_CTRL1_PAGE3
- IAR_DTM_CTRL1_PAGE4
- IAR_DTM_CTRL1_PAGE5
- IAR_DTM_CTRL2
- IAR_DUAL_PAN_CTRL
- IAR_DUAL_PAN_CTRL_ACTIVE_NETWORK
- IAR_DUAL_PAN_CTRL_CURRENT_NETWORK
- IAR_DUAL_PAN_CTRL_DUAL_PAN_AUTO
- IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK
- IAR_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT
- IAR_DUAL_PAN_CTRL_PANCORDNTR1
- IAR_DUAL_PAN_DWELL
- IAR_DUAL_PAN_STS
- IAR_DUAL_PAN_STS_DUAL_PAN_REMAIN
- IAR_DUAL_PAN_STS_RECD_ON_PAN0
- IAR_DUAL_PAN_STS_RECD_ON_PAN1
- IAR_FAD_THR
- IAR_FILTERFAIL_CODE1
- IAR_FILTERFAIL_CODE2
- IAR_FILTERFAIL_CODE2_9_8
- IAR_FILTERFAIL_CODE2_PAN_SEL
- IAR_GPIO_DATA
- IAR_GPIO_DIR
- IAR_GPIO_DS
- IAR_GPIO_PUL_EN
- IAR_GPIO_PUL_SEL
- IAR_INDEX
- IAR_KMOD_CAL
- IAR_KMOD_CTRL
- IAR_LIM_FE_TEST_CTRL
- IAR_LNA_AGCGAIN
- IAR_LNA_TUNE
- IAR_LQI_OFFSET_COMP
- IAR_MACLONGADDRS0_0
- IAR_MACLONGADDRS0_16
- IAR_MACLONGADDRS0_24
- IAR_MACLONGADDRS0_32
- IAR_MACLONGADDRS0_40
- IAR_MACLONGADDRS0_48
- IAR_MACLONGADDRS0_56
- IAR_MACLONGADDRS0_8
- IAR_MACLONGADDRS1_0
- IAR_MACLONGADDRS1_16
- IAR_MACLONGADDRS1_24
- IAR_MACLONGADDRS1_32
- IAR_MACLONGADDRS1_40
- IAR_MACLONGADDRS1_48
- IAR_MACLONGADDRS1_56
- IAR_MACLONGADDRS1_8
- IAR_MACPANID0_LSB
- IAR_MACPANID0_MSB
- IAR_MACPANID1_LSB
- IAR_MACPANID1_MSB
- IAR_MACSHORTADDRS0_LSB
- IAR_MACSHORTADDRS0_MSB
- IAR_MACSHORTADDRS1_LSB
- IAR_MACSHORTADDRS1_MSB
- IAR_MISCELLANEOUS
- IAR_MISC_PAD_CTRL
- IAR_MISC_PAD_CTRL_ANTX_CURR
- IAR_MISC_PAD_CTRL_IRQ_B_OD
- IAR_MISC_PAD_CTRL_MISO_HIZ_EN
- IAR_MISC_PAD_CTRL_NON_GPIO_DS
- IAR_PART_ID
- IAR_PA_BIAS
- IAR_PA_CAL
- IAR_PA_PWRCAL
- IAR_PA_TEST_CTRL
- IAR_PA_TUNING
- IAR_PHY_STS
- IAR_PHY_STS_CRCVALID
- IAR_PHY_STS_FILTERFAIL_FLAG_SEL
- IAR_PHY_STS_PLL_LOCK
- IAR_PHY_STS_PLL_LOCK_ERR
- IAR_PHY_STS_PLL_UNLOCK
- IAR_PHY_STS_PREAMBLE_DET
- IAR_PHY_STS_SFD_DET
- IAR_PLL_DIG_CTRL
- IAR_PLL_FRAC1_LSB
- IAR_PLL_FRAC1_MSB
- IAR_PLL_INT1
- IAR_PLL_TEST_CTRL
- IAR_PMC_HP_TRIM
- IAR_PMC_LP_TRIM
- IAR_PMC_TEST_CTRL
- IAR_PN_LSB_0
- IAR_PN_LSB_1
- IAR_PN_MSB_0
- IAR_PN_MSB_1
- IAR_RNG
- IAR_RSSI
- IAR_RSSI_CAL1
- IAR_RSSI_CAL2
- IAR_RSSI_CTRL
- IAR_RSSI_OFFSET
- IAR_RSSI_SLOPE
- IAR_RX_BYTE_COUNT
- IAR_RX_FRAME_FILTER
- IAR_RX_FRAME_FLT_ACK_FT
- IAR_RX_FRAME_FLT_ACTIVE_PROMISCUOUS
- IAR_RX_FRAME_FLT_BEACON_FT
- IAR_RX_FRAME_FLT_CMD_FT
- IAR_RX_FRAME_FLT_DATA_FT
- IAR_RX_FRAME_FLT_FRM_VER
- IAR_RX_FRAME_FLT_FRM_VER_SHIFT
- IAR_RX_FRAME_FLT_NS_FT
- IAR_RX_MAX_CORR
- IAR_RX_MAX_PREAMBLE
- IAR_RX_WTR_MARK
- IAR_SCAN_DTM_PROTECT_0
- IAR_SCAN_DTM_PROTECT_1
- IAR_SEQ_MGR_CTRL
- IAR_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT
- IAR_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH
- IAR_SEQ_MGR_CTRL_LATCH_PREAMBLE
- IAR_SEQ_MGR_CTRL_NO_RX_RECYCLE
- IAR_SEQ_MGR_CTRL_PLL_ABORT_OVRD
- IAR_SEQ_MGR_CTRL_PSM_LOCK_DIS
- IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL
- IAR_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT
- IAR_SEQ_MGR_OVRD0
- IAR_SEQ_MGR_OVRD1
- IAR_SEQ_MGR_OVRD2
- IAR_SEQ_MGR_OVRD3
- IAR_SEQ_MGR_OVRD4
- IAR_SEQ_MGR_OVRD5
- IAR_SEQ_MGR_OVRD6
- IAR_SEQ_MGR_OVRD7
- IAR_SEQ_MGR_STS
- IAR_SEQ_MGR_STS_NEW_SEQ_INHIBIT
- IAR_SEQ_MGR_STS_RX_MODE
- IAR_SEQ_MGR_STS_RX_TIMEOUT_PENDING
- IAR_SEQ_MGR_STS_SEQ_IDLE
- IAR_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED
- IAR_SEQ_MGR_STS_XCVSEQ_ACTUAL
- IAR_SEQ_T_STS
- IAR_SLOT_PRELOAD
- IAR_SNF_THR
- IAR_SOFT_RESET
- IAR_SOFT_RESET_PLL_RST
- IAR_SOFT_RESET_REGS_RST
- IAR_SOFT_RESET_RX_RST
- IAR_SOFT_RESET_SEQ_MGR_RST
- IAR_SOFT_RESET_SOG_RST
- IAR_SOFT_RESET_TX_RST
- IAR_SRC_ADDR_CHECKSUM1
- IAR_SRC_ADDR_CHECKSUM2
- IAR_SRC_TBL_VALID1
- IAR_SRC_TBL_VALID2
- IAR_SYNC_CTRL
- IAR_TESTMODE_CTRL
- IAR_TEST_MODE_CTRL_CONTINUOUS_EN
- IAR_TEST_MODE_CTRL_FPGA_EN
- IAR_TEST_MODE_CTRL_HOT_ANT
- IAR_TEST_MODE_CTRL_IDEAL_PFC_EN
- IAR_TEST_MODE_CTRL_IDEAL_RSSI_EN
- IAR_TMR_PRESCALE
- IAR_TXDELAY
- IAR_TX_MODE_CTRL
- IAR_TX_MODE_CTRL_BT_EN
- IAR_TX_MODE_CTRL_DTS0
- IAR_TX_MODE_CTRL_DTS1
- IAR_TX_MODE_CTRL_DTS2
- IAR_TX_MODE_CTRL_TX_INV
- IAR_VCO_BEST_DIFF
- IAR_VCO_BIAS
- IAR_VCO_CAL
- IAR_VCO_CTRL1
- IAR_VCO_CTRL2
- IAR_VCO_TEST_CTRL
- IAR_VREGA_TRIM
- IAR_XTAL_COMP_MAX
- IAR_XTAL_COMP_MIN
- IAR_XTAL_CTRL
- IAR_XTAL_GM
- IAR_XTAL_TRIM
- IASELR1
- IASELR10
- IASELR11
- IASELR12
- IASELR13
- IASELR14
- IASELR15
- IASELR2
- IASELR3
- IASELR4
- IASELR5
- IASELR6
- IASELR7
- IASELR8
- IASELR9
- IAVF_2K_TOO_SMALL_WITH_PADDING
- IAVF_ADMINQ_DESC
- IAVF_ADMINQ_DESC_ALIGNMENT
- IAVF_ADMINQ_DETAILS
- IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK
- IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT
- IAVF_AQC_SET_RSS_KEY_VSI_VALID
- IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK
- IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF
- IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT
- IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI
- IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK
- IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT
- IAVF_AQC_SET_RSS_LUT_VSI_VALID
- IAVF_AQ_DRIVER_UNLOADING
- IAVF_AQ_FLAG_BUF
- IAVF_AQ_FLAG_BUF_SHIFT
- IAVF_AQ_FLAG_CMP
- IAVF_AQ_FLAG_CMP_SHIFT
- IAVF_AQ_FLAG_DD
- IAVF_AQ_FLAG_DD_SHIFT
- IAVF_AQ_FLAG_EI
- IAVF_AQ_FLAG_EI_SHIFT
- IAVF_AQ_FLAG_ERR
- IAVF_AQ_FLAG_ERR_SHIFT
- IAVF_AQ_FLAG_FE
- IAVF_AQ_FLAG_FE_SHIFT
- IAVF_AQ_FLAG_LB
- IAVF_AQ_FLAG_LB_SHIFT
- IAVF_AQ_FLAG_RD
- IAVF_AQ_FLAG_RD_SHIFT
- IAVF_AQ_FLAG_SI
- IAVF_AQ_FLAG_SI_SHIFT
- IAVF_AQ_FLAG_VFC
- IAVF_AQ_FLAG_VFC_SHIFT
- IAVF_AQ_FLAG_VFE
- IAVF_AQ_FLAG_VFE_SHIFT
- IAVF_AQ_LARGE_BUF
- IAVF_AQ_LEN
- IAVF_AQ_MAX_ERR
- IAVF_AQ_RC_BAD_ADDR
- IAVF_AQ_RC_E2BIG
- IAVF_AQ_RC_EACCES
- IAVF_AQ_RC_EAGAIN
- IAVF_AQ_RC_EBUSY
- IAVF_AQ_RC_EEXIST
- IAVF_AQ_RC_EFAULT
- IAVF_AQ_RC_EFBIG
- IAVF_AQ_RC_EFLUSHED
- IAVF_AQ_RC_EINTR
- IAVF_AQ_RC_EINVAL
- IAVF_AQ_RC_EIO
- IAVF_AQ_RC_EMODE
- IAVF_AQ_RC_ENOENT
- IAVF_AQ_RC_ENOMEM
- IAVF_AQ_RC_ENOSPC
- IAVF_AQ_RC_ENOSYS
- IAVF_AQ_RC_ENOTTY
- IAVF_AQ_RC_ENXIO
- IAVF_AQ_RC_EPERM
- IAVF_AQ_RC_ERANGE
- IAVF_AQ_RC_ESRCH
- IAVF_AQ_RC_OK
- IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG
- IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE
- IAVF_AQ_VSI_CAS_PV_INSERT_TAG
- IAVF_AQ_VSI_CAS_PV_TAGX_COPY
- IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE
- IAVF_AQ_VSI_CAS_PV_TAGX_MASK
- IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE
- IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT
- IAVF_AQ_VSI_PROP_CAS_PV_VALID
- IAVF_AQ_VSI_PROP_EGRESS_UP_VALID
- IAVF_AQ_VSI_PROP_INGRESS_UP_VALID
- IAVF_AQ_VSI_PROP_OUTER_UP_VALID
- IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID
- IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID
- IAVF_AQ_VSI_PROP_SCHED_VALID
- IAVF_AQ_VSI_PROP_SECURITY_VALID
- IAVF_AQ_VSI_PROP_SWITCH_VALID
- IAVF_AQ_VSI_PROP_VLAN_VALID
- IAVF_AQ_VSI_PVLAN_EMOD_MASK
- IAVF_AQ_VSI_PVLAN_EMOD_NOTHING
- IAVF_AQ_VSI_PVLAN_EMOD_SHIFT
- IAVF_AQ_VSI_PVLAN_EMOD_STR
- IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH
- IAVF_AQ_VSI_PVLAN_EMOD_STR_UP
- IAVF_AQ_VSI_PVLAN_INSERT_PVID
- IAVF_AQ_VSI_PVLAN_MODE_ALL
- IAVF_AQ_VSI_PVLAN_MODE_MASK
- IAVF_AQ_VSI_PVLAN_MODE_SHIFT
- IAVF_AQ_VSI_PVLAN_MODE_TAGGED
- IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED
- IAVF_AQ_VSI_QS_HANDLE_INVALID
- IAVF_AQ_VSI_QUEUE_MASK
- IAVF_AQ_VSI_QUEUE_SHIFT
- IAVF_AQ_VSI_QUE_MAP_CONTIG
- IAVF_AQ_VSI_QUE_MAP_NONCONTIG
- IAVF_AQ_VSI_QUE_OPT_FCOE_ENA
- IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA
- IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF
- IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI
- IAVF_AQ_VSI_QUE_OPT_TCP_ENA
- IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA
- IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD
- IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK
- IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK
- IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB
- IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB
- IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG
- IAVF_AQ_VSI_SW_ID_MASK
- IAVF_AQ_VSI_SW_ID_SHIFT
- IAVF_AQ_VSI_TC_QUE_NUMBER_MASK
- IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT
- IAVF_AQ_VSI_TC_QUE_OFFSET_MASK
- IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP0_MASK
- IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP1_MASK
- IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP2_MASK
- IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP3_MASK
- IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP4_MASK
- IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP5_MASK
- IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP6_MASK
- IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT
- IAVF_AQ_VSI_UP_TABLE_UP7_MASK
- IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT
- IAVF_ASQ_CMD_TIMEOUT
- IAVF_BUSY_WAIT_COUNT
- IAVF_BUSY_WAIT_DELAY
- IAVF_CF_FLAGS_IIP
- IAVF_CF_FLAGS_IMAC
- IAVF_CF_FLAGS_IMAC_IVLAN
- IAVF_CF_FLAGS_IMAC_IVLAN_TEN_ID
- IAVF_CF_FLAGS_IMAC_TEN_ID
- IAVF_CF_FLAGS_OMAC
- IAVF_CF_FLAGS_OMAC_TEN_ID_IMAC
- IAVF_CHECK_CMD_LENGTH
- IAVF_CHECK_STRUCT_LEN
- IAVF_CLIENT_FLAGS_LAUNCH_ON_PROBE
- IAVF_CLIENT_FTYPE_PF
- IAVF_CLIENT_FTYPE_VF
- IAVF_CLIENT_IWARP
- IAVF_CLIENT_MAX_USER_PRIORITY
- IAVF_CLIENT_MSIX_ALL
- IAVF_CLIENT_STR_LENGTH
- IAVF_CLIENT_VERSION_BUILD
- IAVF_CLIENT_VERSION_MAJOR
- IAVF_CLIENT_VERSION_MINOR
- IAVF_CLIENT_VERSION_STR
- IAVF_CLOUD_FIELD_IIP
- IAVF_CLOUD_FIELD_IMAC
- IAVF_CLOUD_FIELD_IVLAN
- IAVF_CLOUD_FIELD_OMAC
- IAVF_CLOUD_FIELD_TEN_ID
- IAVF_DEBUG_ALL
- IAVF_DEBUG_AQ
- IAVF_DEBUG_AQ_COMMAND
- IAVF_DEBUG_AQ_DESCRIPTOR
- IAVF_DEBUG_AQ_DESC_BUFFER
- IAVF_DEBUG_AQ_MESSAGE
- IAVF_DEBUG_DCB
- IAVF_DEBUG_DIAG
- IAVF_DEBUG_FD
- IAVF_DEBUG_FLOW
- IAVF_DEBUG_HMC
- IAVF_DEBUG_INIT
- IAVF_DEBUG_LAN
- IAVF_DEBUG_LINK
- IAVF_DEBUG_NVM
- IAVF_DEBUG_PACKAGE
- IAVF_DEBUG_PHY
- IAVF_DEBUG_RELEASE
- IAVF_DEBUG_USER
- IAVF_DEFAULT_IRQ_WORK
- IAVF_DEFAULT_RSS_HENA
- IAVF_DEFAULT_RSS_HENA_EXPANDED
- IAVF_DEFAULT_RXD
- IAVF_DEFAULT_TXD
- IAVF_DESC_UNUSED
- IAVF_DEV_ID_ADAPTIVE_VF
- IAVF_DEV_ID_VF
- IAVF_DEV_ID_VF_HV
- IAVF_DEV_ID_X722_VF
- IAVF_ERR_ADAPTER_STOPPED
- IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR
- IAVF_ERR_ADMIN_QUEUE_ERROR
- IAVF_ERR_ADMIN_QUEUE_FULL
- IAVF_ERR_ADMIN_QUEUE_NO_WORK
- IAVF_ERR_ADMIN_QUEUE_TIMEOUT
- IAVF_ERR_AUTONEG_NOT_COMPLETE
- IAVF_ERR_BACKING_PAGE_ERROR
- IAVF_ERR_BAD_IWARP_CQE
- IAVF_ERR_BAD_PTR
- IAVF_ERR_BUF_TOO_SHORT
- IAVF_ERR_CONFIG
- IAVF_ERR_CQP_COMPL_ERROR
- IAVF_ERR_DEVICE_NOT_SUPPORTED
- IAVF_ERR_DIAG_TEST_FAILED
- IAVF_ERR_FIRMWARE_API_VERSION
- IAVF_ERR_FLUSHED_QUEUE
- IAVF_ERR_INVALID_AEQ_ID
- IAVF_ERR_INVALID_ALIGNMENT
- IAVF_ERR_INVALID_ARP_INDEX
- IAVF_ERR_INVALID_CEQ_ID
- IAVF_ERR_INVALID_CQ_ID
- IAVF_ERR_INVALID_FPM_FUNC_ID
- IAVF_ERR_INVALID_FRAG_COUNT
- IAVF_ERR_INVALID_HMCFN_ID
- IAVF_ERR_INVALID_HMC_OBJ_COUNT
- IAVF_ERR_INVALID_HMC_OBJ_INDEX
- IAVF_ERR_INVALID_IMM_DATA_SIZE
- IAVF_ERR_INVALID_LINK_SETTINGS
- IAVF_ERR_INVALID_MAC_ADDR
- IAVF_ERR_INVALID_PAGE_DESC_INDEX
- IAVF_ERR_INVALID_PBLE_INDEX
- IAVF_ERR_INVALID_PD_ID
- IAVF_ERR_INVALID_PUSH_PAGE_INDEX
- IAVF_ERR_INVALID_QP_ID
- IAVF_ERR_INVALID_SD_INDEX
- IAVF_ERR_INVALID_SD_TYPE
- IAVF_ERR_INVALID_SIZE
- IAVF_ERR_INVALID_SRQ_ARM_LIMIT
- IAVF_ERR_INVALID_VF_ID
- IAVF_ERR_LINK_SETUP
- IAVF_ERR_MAC_TYPE
- IAVF_ERR_MASTER_REQUESTS_PENDING
- IAVF_ERR_MEMCPY_FAILED
- IAVF_ERR_NOT_IMPLEMENTED
- IAVF_ERR_NOT_READY
- IAVF_ERR_NO_AVAILABLE_VSI
- IAVF_ERR_NO_MEMORY
- IAVF_ERR_NO_PBLCHUNKS_AVAILABLE
- IAVF_ERR_NVM
- IAVF_ERR_NVM_BLANK_MODE
- IAVF_ERR_NVM_CHECKSUM
- IAVF_ERR_OPCODE_MISMATCH
- IAVF_ERR_PARAM
- IAVF_ERR_PE_DOORBELL_NOT_ENABLED
- IAVF_ERR_PHY
- IAVF_ERR_QP_INVALID_MSG_SIZE
- IAVF_ERR_QP_TOOMANY_WRS_POSTED
- IAVF_ERR_QUEUE_EMPTY
- IAVF_ERR_RESET_FAILED
- IAVF_ERR_RING_FULL
- IAVF_ERR_SRQ_ENABLED
- IAVF_ERR_SWFW_SYNC
- IAVF_ERR_TIMEOUT
- IAVF_ERR_UNKNOWN_PHY
- IAVF_FILTER_PCTYPE_FCOE_OTHER
- IAVF_FILTER_PCTYPE_FCOE_OX
- IAVF_FILTER_PCTYPE_FCOE_RX
- IAVF_FILTER_PCTYPE_FRAG_IPV4
- IAVF_FILTER_PCTYPE_FRAG_IPV6
- IAVF_FILTER_PCTYPE_L2_PAYLOAD
- IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER
- IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP
- IAVF_FILTER_PCTYPE_NONF_IPV4_TCP
- IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK
- IAVF_FILTER_PCTYPE_NONF_IPV4_UDP
- IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER
- IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP
- IAVF_FILTER_PCTYPE_NONF_IPV6_TCP
- IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK
- IAVF_FILTER_PCTYPE_NONF_IPV6_UDP
- IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP
- IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP
- IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP
- IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP
- IAVF_FLAG_ALLMULTI_ON
- IAVF_FLAG_AQ_ADD_CLOUD_FILTER
- IAVF_FLAG_AQ_ADD_MAC_FILTER
- IAVF_FLAG_AQ_ADD_VLAN_FILTER
- IAVF_FLAG_AQ_CONFIGURE_QUEUES
- IAVF_FLAG_AQ_CONFIGURE_RSS
- IAVF_FLAG_AQ_DEL_CLOUD_FILTER
- IAVF_FLAG_AQ_DEL_MAC_FILTER
- IAVF_FLAG_AQ_DEL_VLAN_FILTER
- IAVF_FLAG_AQ_DISABLE_CHANNELS
- IAVF_FLAG_AQ_DISABLE_QUEUES
- IAVF_FLAG_AQ_DISABLE_VLAN_STRIPPING
- IAVF_FLAG_AQ_ENABLE_CHANNELS
- IAVF_FLAG_AQ_ENABLE_QUEUES
- IAVF_FLAG_AQ_ENABLE_VLAN_STRIPPING
- IAVF_FLAG_AQ_GET_CONFIG
- IAVF_FLAG_AQ_GET_HENA
- IAVF_FLAG_AQ_HANDLE_RESET
- IAVF_FLAG_AQ_MAP_VECTORS
- IAVF_FLAG_AQ_RELEASE_ALLMULTI
- IAVF_FLAG_AQ_RELEASE_PROMISC
- IAVF_FLAG_AQ_REQUEST_ALLMULTI
- IAVF_FLAG_AQ_REQUEST_PROMISC
- IAVF_FLAG_AQ_SET_HENA
- IAVF_FLAG_AQ_SET_RSS_KEY
- IAVF_FLAG_AQ_SET_RSS_LUT
- IAVF_FLAG_CLIENT_NEEDS_CLOSE
- IAVF_FLAG_CLIENT_NEEDS_L2_PARAMS
- IAVF_FLAG_CLIENT_NEEDS_OPEN
- IAVF_FLAG_DCB_ENABLED
- IAVF_FLAG_LEGACY_RX
- IAVF_FLAG_PF_COMMS_FAILED
- IAVF_FLAG_PROMISC_ON
- IAVF_FLAG_QUEUES_DISABLED
- IAVF_FLAG_REINIT_ITR_NEEDED
- IAVF_FLAG_RESET_NEEDED
- IAVF_FLAG_RESET_PENDING
- IAVF_FLAG_RX_CSUM_ENABLED
- IAVF_FLAG_SERVICE_CLIENT_REQUESTED
- IAVF_FLAG_WB_ON_ITR_CAPABLE
- IAVF_FREE_VECTOR
- IAVF_FW_API_VERSION_MAJOR
- IAVF_FW_API_VERSION_MINOR_X710
- IAVF_FW_API_VERSION_MINOR_X722
- IAVF_FW_MINOR_VERSION
- IAVF_HKEY_ARRAY_SIZE
- IAVF_HLUT_ARRAY_SIZE
- IAVF_HW_CAP_MAX_GPIO
- IAVF_IDX_ITR0
- IAVF_IDX_ITR1
- IAVF_IDX_ITR2
- IAVF_INTRL_62K
- IAVF_INTRL_83K
- IAVF_INTRL_8K
- IAVF_ITR_100K
- IAVF_ITR_18K
- IAVF_ITR_20K
- IAVF_ITR_50K
- IAVF_ITR_8K
- IAVF_ITR_ADAPTIVE_BULK
- IAVF_ITR_ADAPTIVE_LATENCY
- IAVF_ITR_ADAPTIVE_MAX_USECS
- IAVF_ITR_ADAPTIVE_MIN_INC
- IAVF_ITR_ADAPTIVE_MIN_USECS
- IAVF_ITR_DYNAMIC
- IAVF_ITR_MASK
- IAVF_ITR_NONE
- IAVF_ITR_RX_DEF
- IAVF_ITR_TX_DEF
- IAVF_LAST_OFFSET
- IAVF_LINK_SPEED_1000MB_SHIFT
- IAVF_LINK_SPEED_100MB
- IAVF_LINK_SPEED_100MB_SHIFT
- IAVF_LINK_SPEED_10GB
- IAVF_LINK_SPEED_10GB_SHIFT
- IAVF_LINK_SPEED_1GB
- IAVF_LINK_SPEED_20GB
- IAVF_LINK_SPEED_20GB_SHIFT
- IAVF_LINK_SPEED_25GB
- IAVF_LINK_SPEED_25GB_SHIFT
- IAVF_LINK_SPEED_40GB
- IAVF_LINK_SPEED_40GB_SHIFT
- IAVF_LINK_SPEED_UNKNOWN
- IAVF_MAC_GENERIC
- IAVF_MAC_UNKNOWN
- IAVF_MAC_VF
- IAVF_MAC_X722
- IAVF_MAC_X722_VF
- IAVF_MAC_XL710
- IAVF_MASK
- IAVF_MAX_AQ_BUF_SIZE
- IAVF_MAX_BUFFER_TXD
- IAVF_MAX_CHAINED_RX_BUFFERS
- IAVF_MAX_DATA_PER_TXD
- IAVF_MAX_DATA_PER_TXD_ALIGNED
- IAVF_MAX_INTRL
- IAVF_MAX_ITR
- IAVF_MAX_READ_REQ_SIZE
- IAVF_MAX_REQ_QUEUES
- IAVF_MAX_RXBUFFER
- IAVF_MAX_RXD
- IAVF_MAX_TRAFFIC_CLASS
- IAVF_MAX_TXD
- IAVF_MAX_USER_PRIORITY
- IAVF_MAX_VF_VSI
- IAVF_MAX_VSI_QP
- IAVF_MBPS_DIVISOR
- IAVF_MINOR_VER_GET_LINK_INFO_XL710
- IAVF_MIN_DESC_PENDING
- IAVF_MIN_ITR
- IAVF_MIN_RXD
- IAVF_MIN_TXD
- IAVF_MIN_TX_LEN
- IAVF_NOT_SUPPORTED
- IAVF_PACKET_HDR_PAD
- IAVF_PE_ITR
- IAVF_PRIV_FLAG
- IAVF_PRIV_FLAGS_STR_LEN
- IAVF_PTT
- IAVF_PTT_UNUSED_ENTRY
- IAVF_QRX_TAIL1
- IAVF_QTX_CTL_PF_QUEUE
- IAVF_QTX_CTL_VF_QUEUE
- IAVF_QTX_CTL_VM_QUEUE
- IAVF_QTX_TAIL1
- IAVF_QUEUE_END_OF_LIST
- IAVF_QUEUE_INVALID_IDX
- IAVF_QUEUE_STAT
- IAVF_QUEUE_STATS_LEN
- IAVF_QUEUE_TYPE_PE_AEQ
- IAVF_QUEUE_TYPE_PE_CEQ
- IAVF_QUEUE_TYPE_RX
- IAVF_QUEUE_TYPE_TX
- IAVF_QUEUE_TYPE_UNKNOWN
- IAVF_REQ_DESCRIPTOR_MULTIPLE
- IAVF_RESET_WAIT_COUNT
- IAVF_RESET_WAIT_MS
- IAVF_RXBUFFER_1536
- IAVF_RXBUFFER_2048
- IAVF_RXBUFFER_256
- IAVF_RXBUFFER_3072
- IAVF_RXD_DD
- IAVF_RXD_EOF
- IAVF_RXD_QW1_ERROR_MASK
- IAVF_RXD_QW1_ERROR_SHIFT
- IAVF_RXD_QW1_LENGTH_HBUF_MASK
- IAVF_RXD_QW1_LENGTH_HBUF_SHIFT
- IAVF_RXD_QW1_LENGTH_PBUF_MASK
- IAVF_RXD_QW1_LENGTH_PBUF_SHIFT
- IAVF_RXD_QW1_LENGTH_SPH_MASK
- IAVF_RXD_QW1_LENGTH_SPH_SHIFT
- IAVF_RXD_QW1_PTYPE_MASK
- IAVF_RXD_QW1_PTYPE_SHIFT
- IAVF_RXD_QW1_STATUS_MASK
- IAVF_RXD_QW1_STATUS_SHIFT
- IAVF_RXD_QW1_STATUS_TSYNINDX_MASK
- IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT
- IAVF_RXD_QW1_STATUS_TSYNVALID_MASK
- IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT
- IAVF_RXQ_CTX_DBUFF_SHIFT
- IAVF_RXR_FLAGS_BUILD_SKB_ENABLED
- IAVF_RX_BUFFER_WRITE
- IAVF_RX_DESC
- IAVF_RX_DESC_ERROR_EIPE_SHIFT
- IAVF_RX_DESC_ERROR_HBO_SHIFT
- IAVF_RX_DESC_ERROR_IPE_SHIFT
- IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR
- IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN
- IAVF_RX_DESC_ERROR_L3L4E_FC
- IAVF_RX_DESC_ERROR_L3L4E_NONE
- IAVF_RX_DESC_ERROR_L3L4E_PROT
- IAVF_RX_DESC_ERROR_L3L4E_SHIFT
- IAVF_RX_DESC_ERROR_L4E_SHIFT
- IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT
- IAVF_RX_DESC_ERROR_PPRS_SHIFT
- IAVF_RX_DESC_ERROR_RECIPE_SHIFT
- IAVF_RX_DESC_ERROR_RXE_SHIFT
- IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT
- IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT
- IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT
- IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT
- IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT
- IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT
- IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT
- IAVF_RX_DESC_FLTSTAT_NO_DATA
- IAVF_RX_DESC_FLTSTAT_RSS_HASH
- IAVF_RX_DESC_FLTSTAT_RSV
- IAVF_RX_DESC_FLTSTAT_RSV_FD_ID
- IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT
- IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT
- IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT
- IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT
- IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT
- IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT
- IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT
- IAVF_RX_DESC_PE_STATUS_QPID_SHIFT
- IAVF_RX_DESC_PE_STATUS_URG_SHIFT
- IAVF_RX_DESC_STATUS_CRCP_SHIFT
- IAVF_RX_DESC_STATUS_DD_SHIFT
- IAVF_RX_DESC_STATUS_EOF_SHIFT
- IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT
- IAVF_RX_DESC_STATUS_FLM_SHIFT
- IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT
- IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT
- IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT
- IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT
- IAVF_RX_DESC_STATUS_L3L4P_SHIFT
- IAVF_RX_DESC_STATUS_LAST
- IAVF_RX_DESC_STATUS_LPBK_SHIFT
- IAVF_RX_DESC_STATUS_RESERVED_SHIFT
- IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
- IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
- IAVF_RX_DESC_STATUS_UMBCAST_SHIFT
- IAVF_RX_DMA_ATTR
- IAVF_RX_DTYPE_HEADER_SPLIT
- IAVF_RX_DTYPE_NO_SPLIT
- IAVF_RX_DTYPE_SPLIT_ALWAYS
- IAVF_RX_HDR_SIZE
- IAVF_RX_INCREMENT
- IAVF_RX_ITR
- IAVF_RX_NEXT_DESC
- IAVF_RX_NEXT_DESC_PREFETCH
- IAVF_RX_PROG_STATUS_DESC_DD_SHIFT
- IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT
- IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS
- IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS
- IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT
- IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS
- IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT
- IAVF_RX_PROG_STATUS_DESC_LENGTH
- IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT
- IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT
- IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT
- IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK
- IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT
- IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK
- IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT
- IAVF_RX_PTYPE_FRAG
- IAVF_RX_PTYPE_FRG
- IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4
- IAVF_RX_PTYPE_GRENAT4_MAC_PAY3
- IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4
- IAVF_RX_PTYPE_GRENAT6_MAC_PAY3
- IAVF_RX_PTYPE_INNER_PROT_ICMP
- IAVF_RX_PTYPE_INNER_PROT_NONE
- IAVF_RX_PTYPE_INNER_PROT_SCTP
- IAVF_RX_PTYPE_INNER_PROT_TCP
- IAVF_RX_PTYPE_INNER_PROT_TIMESYNC
- IAVF_RX_PTYPE_INNER_PROT_TS
- IAVF_RX_PTYPE_INNER_PROT_UDP
- IAVF_RX_PTYPE_L2_ARP
- IAVF_RX_PTYPE_L2_EAPOL_PAY2
- IAVF_RX_PTYPE_L2_ECP_PAY2
- IAVF_RX_PTYPE_L2_EVB_PAY2
- IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3
- IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA
- IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3
- IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3
- IAVF_RX_PTYPE_L2_FCOE_PAY3
- IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA
- IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER
- IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY
- IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP
- IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3
- IAVF_RX_PTYPE_L2_FIP_PAY2
- IAVF_RX_PTYPE_L2_LLDP_PAY2
- IAVF_RX_PTYPE_L2_MACCNTRL_PAY2
- IAVF_RX_PTYPE_L2_MAC_PAY2
- IAVF_RX_PTYPE_L2_OUI_PAY2
- IAVF_RX_PTYPE_L2_QCN_PAY2
- IAVF_RX_PTYPE_L2_RESERVED
- IAVF_RX_PTYPE_L2_TIMESYNC_PAY2
- IAVF_RX_PTYPE_NOF
- IAVF_RX_PTYPE_NOT_FRAG
- IAVF_RX_PTYPE_OUTER_IP
- IAVF_RX_PTYPE_OUTER_IPV4
- IAVF_RX_PTYPE_OUTER_IPV6
- IAVF_RX_PTYPE_OUTER_L2
- IAVF_RX_PTYPE_OUTER_NONE
- IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE
- IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2
- IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3
- IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4
- IAVF_RX_PTYPE_TUNNEL_END_IPV4
- IAVF_RX_PTYPE_TUNNEL_END_IPV6
- IAVF_RX_PTYPE_TUNNEL_END_NONE
- IAVF_RX_PTYPE_TUNNEL_IP_GRENAT
- IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
- IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
- IAVF_RX_PTYPE_TUNNEL_IP_IP
- IAVF_RX_PTYPE_TUNNEL_NONE
- IAVF_RX_SPLIT_IP
- IAVF_RX_SPLIT_L2
- IAVF_RX_SPLIT_SCTP
- IAVF_RX_SPLIT_TCP_UDP
- IAVF_SKB_PAD
- IAVF_STAT
- IAVF_STATS_LEN
- IAVF_SUCCESS
- IAVF_TRACE_NAME
- IAVF_TXD_CMD
- IAVF_TXD_CTX_EIP_NOINC_IPID_CONST
- IAVF_TXD_CTX_GRE_TUNNELING
- IAVF_TXD_CTX_QW0_DECTTL_MASK
- IAVF_TXD_CTX_QW0_DECTTL_SHIFT
- IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
- IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT
- IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK
- IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT
- IAVF_TXD_CTX_QW0_EXT_IP_MASK
- IAVF_TXD_CTX_QW0_EXT_IP_SHIFT
- IAVF_TXD_CTX_QW0_L4T_CS_MASK
- IAVF_TXD_CTX_QW0_L4T_CS_SHIFT
- IAVF_TXD_CTX_QW0_NATLEN_MASK
- IAVF_TXD_CTX_QW0_NATLEN_SHIFT
- IAVF_TXD_CTX_QW0_NATT_MASK
- IAVF_TXD_CTX_QW0_NATT_SHIFT
- IAVF_TXD_CTX_QW1_CMD_MASK
- IAVF_TXD_CTX_QW1_CMD_SHIFT
- IAVF_TXD_CTX_QW1_MSS_MASK
- IAVF_TXD_CTX_QW1_MSS_SHIFT
- IAVF_TXD_CTX_QW1_TSO_LEN_MASK
- IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT
- IAVF_TXD_CTX_QW1_VSI_MASK
- IAVF_TXD_CTX_QW1_VSI_SHIFT
- IAVF_TXD_CTX_UDP_TUNNELING
- IAVF_TXD_QW1_CMD_MASK
- IAVF_TXD_QW1_CMD_SHIFT
- IAVF_TXD_QW1_DTYPE_MASK
- IAVF_TXD_QW1_DTYPE_SHIFT
- IAVF_TXD_QW1_L2TAG1_MASK
- IAVF_TXD_QW1_L2TAG1_SHIFT
- IAVF_TXD_QW1_OFFSET_MASK
- IAVF_TXD_QW1_OFFSET_SHIFT
- IAVF_TXD_QW1_TX_BUF_SZ_MASK
- IAVF_TXD_QW1_TX_BUF_SZ_SHIFT
- IAVF_TXR_FLAGS_WB_ON_ITR
- IAVF_TX_CTXTDESC
- IAVF_TX_CTX_DESC_IL2TAG2
- IAVF_TX_CTX_DESC_IL2TAG2_IL2H
- IAVF_TX_CTX_DESC_SWPE
- IAVF_TX_CTX_DESC_SWTCH_LOCAL
- IAVF_TX_CTX_DESC_SWTCH_NOTAG
- IAVF_TX_CTX_DESC_SWTCH_UPLINK
- IAVF_TX_CTX_DESC_SWTCH_VSI
- IAVF_TX_CTX_DESC_TSO
- IAVF_TX_CTX_DESC_TSYN
- IAVF_TX_CTX_EXT_IP_IPV4
- IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM
- IAVF_TX_CTX_EXT_IP_IPV6
- IAVF_TX_CTX_EXT_IP_NONE
- IAVF_TX_DESC
- IAVF_TX_DESC_CMD_DUMMY
- IAVF_TX_DESC_CMD_EOP
- IAVF_TX_DESC_CMD_FCOET
- IAVF_TX_DESC_CMD_ICRC
- IAVF_TX_DESC_CMD_IIPT_IPV4
- IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM
- IAVF_TX_DESC_CMD_IIPT_IPV6
- IAVF_TX_DESC_CMD_IIPT_NONIP
- IAVF_TX_DESC_CMD_IL2TAG1
- IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A
- IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N
- IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI
- IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T
- IAVF_TX_DESC_CMD_L4T_EOFT_SCTP
- IAVF_TX_DESC_CMD_L4T_EOFT_TCP
- IAVF_TX_DESC_CMD_L4T_EOFT_UDP
- IAVF_TX_DESC_CMD_L4T_EOFT_UNK
- IAVF_TX_DESC_CMD_RS
- IAVF_TX_DESC_DTYPE_CONTEXT
- IAVF_TX_DESC_DTYPE_DATA
- IAVF_TX_DESC_DTYPE_DDP_CTX
- IAVF_TX_DESC_DTYPE_DESC_DONE
- IAVF_TX_DESC_DTYPE_FCOE_CTX
- IAVF_TX_DESC_DTYPE_FILTER_PROG
- IAVF_TX_DESC_DTYPE_FLEX_CTX_1
- IAVF_TX_DESC_DTYPE_FLEX_CTX_2
- IAVF_TX_DESC_DTYPE_FLEX_DATA
- IAVF_TX_DESC_DTYPE_NOP
- IAVF_TX_DESC_LENGTH_IPLEN_SHIFT
- IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT
- IAVF_TX_DESC_LENGTH_MACLEN_SHIFT
- IAVF_TX_FLAGS_FCCRC
- IAVF_TX_FLAGS_FD_SB
- IAVF_TX_FLAGS_FSO
- IAVF_TX_FLAGS_HW_VLAN
- IAVF_TX_FLAGS_IPV4
- IAVF_TX_FLAGS_IPV6
- IAVF_TX_FLAGS_NOTIFY_OTHER_EVENTS
- IAVF_TX_FLAGS_SW_VLAN
- IAVF_TX_FLAGS_TSO
- IAVF_TX_FLAGS_VLAN_MASK
- IAVF_TX_FLAGS_VLAN_PRIO_MASK
- IAVF_TX_FLAGS_VLAN_PRIO_SHIFT
- IAVF_TX_FLAGS_VLAN_SHIFT
- IAVF_TX_FLAGS_VXLAN_TUNNEL
- IAVF_TX_ITR
- IAVF_VFGEN_RSTAT
- IAVF_VFGEN_RSTAT_VFR_STATE_MASK
- IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT
- IAVF_VFINT_DYN_CTL01
- IAVF_VFINT_DYN_CTL01_INTENA_MASK
- IAVF_VFINT_DYN_CTL01_INTENA_SHIFT
- IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK
- IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT
- IAVF_VFINT_DYN_CTLN1
- IAVF_VFINT_DYN_CTLN1_INTENA_MASK
- IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT
- IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT
- IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK
- IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT
- IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK
- IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT
- IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
- IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT
- IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK
- IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT
- IAVF_VFINT_ICR01
- IAVF_VFINT_ICR0_ENA1
- IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK
- IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT
- IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT
- IAVF_VFINT_ITRN1
- IAVF_VFQF_HENA
- IAVF_VFQF_HKEY
- IAVF_VFQF_HKEY_MAX_INDEX
- IAVF_VFQF_HLUT
- IAVF_VFQF_HLUT_MAX_INDEX
- IAVF_VF_ARQBAH1
- IAVF_VF_ARQBAL1
- IAVF_VF_ARQH1
- IAVF_VF_ARQH1_ARQH_MASK
- IAVF_VF_ARQH1_ARQH_SHIFT
- IAVF_VF_ARQLEN1
- IAVF_VF_ARQLEN1_ARQCRIT_MASK
- IAVF_VF_ARQLEN1_ARQCRIT_SHIFT
- IAVF_VF_ARQLEN1_ARQENABLE_MASK
- IAVF_VF_ARQLEN1_ARQENABLE_SHIFT
- IAVF_VF_ARQLEN1_ARQOVFL_MASK
- IAVF_VF_ARQLEN1_ARQOVFL_SHIFT
- IAVF_VF_ARQLEN1_ARQVFE_MASK
- IAVF_VF_ARQLEN1_ARQVFE_SHIFT
- IAVF_VF_ARQT1
- IAVF_VF_ATQBAH1
- IAVF_VF_ATQBAL1
- IAVF_VF_ATQH1
- IAVF_VF_ATQLEN1
- IAVF_VF_ATQLEN1_ATQCRIT_MASK
- IAVF_VF_ATQLEN1_ATQCRIT_SHIFT
- IAVF_VF_ATQLEN1_ATQENABLE_MASK
- IAVF_VF_ATQLEN1_ATQENABLE_SHIFT
- IAVF_VF_ATQLEN1_ATQOVFL_MASK
- IAVF_VF_ATQLEN1_ATQOVFL_SHIFT
- IAVF_VF_ATQLEN1_ATQVFE_MASK
- IAVF_VF_ATQLEN1_ATQVFE_SHIFT
- IAVF_VF_ATQT1
- IAVF_VSI_CTRL
- IAVF_VSI_FCOE
- IAVF_VSI_FDIR
- IAVF_VSI_MAIN
- IAVF_VSI_MIRROR
- IAVF_VSI_SRIOV
- IAVF_VSI_TYPE_UNKNOWN
- IAVF_VSI_VMDQ1
- IAVF_VSI_VMDQ2
- IAWRITE
- IA_BUSY
- IA_BUSY_NO_DMA
- IA_CMD
- IA_CMDBUF
- IA_CNTL_STATUS__IA_ADC_BUSY_MASK
- IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT
- IA_CNTL_STATUS__IA_BUSY_MASK
- IA_CNTL_STATUS__IA_BUSY__SHIFT
- IA_CNTL_STATUS__IA_DMA_BUSY_MASK
- IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT
- IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK
- IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT
- IA_CNTL_STATUS__IA_GRP_BUSY_MASK
- IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT
- IA_CSS_BINARY_MODE_PRIMARY
- IA_CSS_BINARY_MODE_VIDEO
- IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK
- IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT
- IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK
- IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT
- IA_DEBUG_DATA__DATA_MASK
- IA_DEBUG_DATA__DATA__SHIFT
- IA_DEBUG_REG0__SPARE0_MASK
- IA_DEBUG_REG0__SPARE0__SHIFT
- IA_DEBUG_REG0__SPARE1_MASK
- IA_DEBUG_REG0__SPARE1__SHIFT
- IA_DEBUG_REG0__SPARE2_MASK
- IA_DEBUG_REG0__SPARE2__SHIFT
- IA_DEBUG_REG0__SPARE3_MASK
- IA_DEBUG_REG0__SPARE3__SHIFT
- IA_DEBUG_REG0__SPARE4_MASK
- IA_DEBUG_REG0__SPARE4__SHIFT
- IA_DEBUG_REG0__SPARE5_MASK
- IA_DEBUG_REG0__SPARE5__SHIFT
- IA_DEBUG_REG0__SPARE6_MASK
- IA_DEBUG_REG0__SPARE6__SHIFT
- IA_DEBUG_REG0__core_clk_busy_MASK
- IA_DEBUG_REG0__core_clk_busy__SHIFT
- IA_DEBUG_REG0__dma_busy_MASK
- IA_DEBUG_REG0__dma_busy__SHIFT
- IA_DEBUG_REG0__dma_grp_hp_valid_MASK
- IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT
- IA_DEBUG_REG0__dma_grp_valid_MASK
- IA_DEBUG_REG0__dma_grp_valid__SHIFT
- IA_DEBUG_REG0__dma_req_busy_MASK
- IA_DEBUG_REG0__dma_req_busy__SHIFT
- IA_DEBUG_REG0__grp_busy_MASK
- IA_DEBUG_REG0__grp_busy__SHIFT
- IA_DEBUG_REG0__grp_dma_hp_read_MASK
- IA_DEBUG_REG0__grp_dma_hp_read__SHIFT
- IA_DEBUG_REG0__grp_dma_read_MASK
- IA_DEBUG_REG0__grp_dma_read__SHIFT
- IA_DEBUG_REG0__ia_busy_MASK
- IA_DEBUG_REG0__ia_busy__SHIFT
- IA_DEBUG_REG0__ia_busy_extended_MASK
- IA_DEBUG_REG0__ia_busy_extended__SHIFT
- IA_DEBUG_REG0__ia_nodma_busy_MASK
- IA_DEBUG_REG0__ia_nodma_busy__SHIFT
- IA_DEBUG_REG0__ia_nodma_busy_extended_MASK
- IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT
- IA_DEBUG_REG0__mc_xl8r_busy_MASK
- IA_DEBUG_REG0__mc_xl8r_busy__SHIFT
- IA_DEBUG_REG0__reg_clk_busy_MASK
- IA_DEBUG_REG0__reg_clk_busy__SHIFT
- IA_DEBUG_REG0__sclk_core_vld_MASK
- IA_DEBUG_REG0__sclk_core_vld__SHIFT
- IA_DEBUG_REG0__sclk_reg_vld_MASK
- IA_DEBUG_REG0__sclk_reg_vld__SHIFT
- IA_DEBUG_REG1__current_data_valid_MASK
- IA_DEBUG_REG1__current_data_valid__SHIFT
- IA_DEBUG_REG1__discard_1st_chunk_MASK
- IA_DEBUG_REG1__discard_1st_chunk__SHIFT
- IA_DEBUG_REG1__discard_2nd_chunk_MASK
- IA_DEBUG_REG1__discard_2nd_chunk__SHIFT
- IA_DEBUG_REG1__dma_buf_type_q_MASK
- IA_DEBUG_REG1__dma_buf_type_q__SHIFT
- IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK
- IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT
- IA_DEBUG_REG1__dma_data_fifo_full_MASK
- IA_DEBUG_REG1__dma_data_fifo_full__SHIFT
- IA_DEBUG_REG1__dma_grp_valid_MASK
- IA_DEBUG_REG1__dma_grp_valid__SHIFT
- IA_DEBUG_REG1__dma_input_fifo_empty_MASK
- IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT
- IA_DEBUG_REG1__dma_input_fifo_full_MASK
- IA_DEBUG_REG1__dma_input_fifo_full__SHIFT
- IA_DEBUG_REG1__dma_mask_fifo_empty_MASK
- IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT
- IA_DEBUG_REG1__dma_mask_fifo_we_MASK
- IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT
- IA_DEBUG_REG1__dma_rdreq_dr_q_MASK
- IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT
- IA_DEBUG_REG1__dma_req_fifo_empty_MASK
- IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT
- IA_DEBUG_REG1__dma_req_fifo_full_MASK
- IA_DEBUG_REG1__dma_req_fifo_full__SHIFT
- IA_DEBUG_REG1__dma_req_path_q_MASK
- IA_DEBUG_REG1__dma_req_path_q__SHIFT
- IA_DEBUG_REG1__dma_ret_data_we_q_MASK
- IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT
- IA_DEBUG_REG1__dma_skid_fifo_empty_MASK
- IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT
- IA_DEBUG_REG1__dma_skid_fifo_full_MASK
- IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT
- IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK
- IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT
- IA_DEBUG_REG1__dma_zero_indices_q_MASK
- IA_DEBUG_REG1__dma_zero_indices_q__SHIFT
- IA_DEBUG_REG1__grp_dma_read_MASK
- IA_DEBUG_REG1__grp_dma_read__SHIFT
- IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK
- IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT
- IA_DEBUG_REG1__out_of_range_r2_q_MASK
- IA_DEBUG_REG1__out_of_range_r2_q__SHIFT
- IA_DEBUG_REG1__second_tc_ret_data_q_MASK
- IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT
- IA_DEBUG_REG1__stage2_dr_MASK
- IA_DEBUG_REG1__stage2_dr__SHIFT
- IA_DEBUG_REG1__stage2_rtr_MASK
- IA_DEBUG_REG1__stage2_rtr__SHIFT
- IA_DEBUG_REG1__stage3_dr_MASK
- IA_DEBUG_REG1__stage3_dr__SHIFT
- IA_DEBUG_REG1__stage3_rtr_MASK
- IA_DEBUG_REG1__stage3_rtr__SHIFT
- IA_DEBUG_REG1__stage4_dr_MASK
- IA_DEBUG_REG1__stage4_dr__SHIFT
- IA_DEBUG_REG1__stage4_rtr_MASK
- IA_DEBUG_REG1__stage4_rtr__SHIFT
- IA_DEBUG_REG1__start_new_packet_MASK
- IA_DEBUG_REG1__start_new_packet__SHIFT
- IA_DEBUG_REG2__hp_current_data_valid_MASK
- IA_DEBUG_REG2__hp_current_data_valid__SHIFT
- IA_DEBUG_REG2__hp_discard_1st_chunk_MASK
- IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT
- IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK
- IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT
- IA_DEBUG_REG2__hp_dma_buf_type_q_MASK
- IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT
- IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK
- IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT
- IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK
- IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT
- IA_DEBUG_REG2__hp_dma_grp_valid_MASK
- IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT
- IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK
- IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT
- IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK
- IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT
- IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK
- IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT
- IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK
- IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT
- IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK
- IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT
- IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK
- IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT
- IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK
- IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT
- IA_DEBUG_REG2__hp_dma_req_path_q_MASK
- IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT
- IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK
- IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT
- IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK
- IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT
- IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK
- IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT
- IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK
- IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT
- IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK
- IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT
- IA_DEBUG_REG2__hp_grp_dma_read_MASK
- IA_DEBUG_REG2__hp_grp_dma_read__SHIFT
- IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK
- IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT
- IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK
- IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT
- IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK
- IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT
- IA_DEBUG_REG2__hp_stage2_dr_MASK
- IA_DEBUG_REG2__hp_stage2_dr__SHIFT
- IA_DEBUG_REG2__hp_stage2_rtr_MASK
- IA_DEBUG_REG2__hp_stage2_rtr__SHIFT
- IA_DEBUG_REG2__hp_stage3_dr_MASK
- IA_DEBUG_REG2__hp_stage3_dr__SHIFT
- IA_DEBUG_REG2__hp_stage3_rtr_MASK
- IA_DEBUG_REG2__hp_stage3_rtr__SHIFT
- IA_DEBUG_REG2__hp_stage4_dr_MASK
- IA_DEBUG_REG2__hp_stage4_dr__SHIFT
- IA_DEBUG_REG2__hp_stage4_rtr_MASK
- IA_DEBUG_REG2__hp_stage4_rtr__SHIFT
- IA_DEBUG_REG2__hp_start_new_packet_MASK
- IA_DEBUG_REG2__hp_start_new_packet__SHIFT
- IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK
- IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT
- IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK
- IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT
- IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK
- IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT
- IA_DEBUG_REG3__discard_1st_chunk_MASK
- IA_DEBUG_REG3__discard_1st_chunk__SHIFT
- IA_DEBUG_REG3__discard_2nd_chunk_MASK
- IA_DEBUG_REG3__discard_2nd_chunk__SHIFT
- IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK
- IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT
- IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK
- IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT
- IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK
- IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT
- IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK
- IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT
- IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK
- IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT
- IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK
- IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT
- IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK
- IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT
- IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK
- IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT
- IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK
- IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT
- IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK
- IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT
- IA_DEBUG_REG3__dma_rdreq_send_out_MASK
- IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT
- IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK
- IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT
- IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK
- IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT
- IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK
- IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT
- IA_DEBUG_REG3__last_tc_req_p1_MASK
- IA_DEBUG_REG3__last_tc_req_p1__SHIFT
- IA_DEBUG_REG3__mc_out_rtr_MASK
- IA_DEBUG_REG3__mc_out_rtr__SHIFT
- IA_DEBUG_REG3__must_service_pipe0_req_MASK
- IA_DEBUG_REG3__must_service_pipe0_req__SHIFT
- IA_DEBUG_REG3__pair0_valid_p1_MASK
- IA_DEBUG_REG3__pair0_valid_p1__SHIFT
- IA_DEBUG_REG3__pair1_valid_p1_MASK
- IA_DEBUG_REG3__pair1_valid_p1__SHIFT
- IA_DEBUG_REG3__pair2_valid_p1_MASK
- IA_DEBUG_REG3__pair2_valid_p1__SHIFT
- IA_DEBUG_REG3__pair3_valid_p1_MASK
- IA_DEBUG_REG3__pair3_valid_p1__SHIFT
- IA_DEBUG_REG3__pipe0_dr_MASK
- IA_DEBUG_REG3__pipe0_dr__SHIFT
- IA_DEBUG_REG3__pipe0_rtr_MASK
- IA_DEBUG_REG3__pipe0_rtr__SHIFT
- IA_DEBUG_REG3__send_pipe1_req_MASK
- IA_DEBUG_REG3__send_pipe1_req__SHIFT
- IA_DEBUG_REG3__tc_out_rtr_MASK
- IA_DEBUG_REG3__tc_out_rtr__SHIFT
- IA_DEBUG_REG3__tc_req_count_q_MASK
- IA_DEBUG_REG3__tc_req_count_q__SHIFT
- IA_DEBUG_REG4__current_shift_is_vect1_q_MASK
- IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT
- IA_DEBUG_REG4__di_event_flag_p1_q_MASK
- IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT
- IA_DEBUG_REG4__di_first_group_of_draw_q_MASK
- IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT
- IA_DEBUG_REG4__di_major_mode_p1_q_MASK
- IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT
- IA_DEBUG_REG4__di_source_select_p1_q_MASK
- IA_DEBUG_REG4__di_source_select_p1_q__SHIFT
- IA_DEBUG_REG4__di_state_sel_p1_q_MASK
- IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT
- IA_DEBUG_REG4__draw_opaq_active_q_MASK
- IA_DEBUG_REG4__draw_opaq_active_q__SHIFT
- IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK
- IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT
- IA_DEBUG_REG4__grp_se0_fifo_empty_MASK
- IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT
- IA_DEBUG_REG4__grp_se0_fifo_full_MASK
- IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT
- IA_DEBUG_REG4__gs_mode_p1_q_MASK
- IA_DEBUG_REG4__gs_mode_p1_q__SHIFT
- IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK
- IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT
- IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK
- IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT
- IA_DEBUG_REG4__last_shift_of_draw_MASK
- IA_DEBUG_REG4__last_shift_of_draw__SHIFT
- IA_DEBUG_REG4__pipe0_dr_MASK
- IA_DEBUG_REG4__pipe0_dr__SHIFT
- IA_DEBUG_REG4__pipe0_rtr_MASK
- IA_DEBUG_REG4__pipe0_rtr__SHIFT
- IA_DEBUG_REG4__pipe1_dr_MASK
- IA_DEBUG_REG4__pipe1_dr__SHIFT
- IA_DEBUG_REG4__pipe1_rtr_MASK
- IA_DEBUG_REG4__pipe1_rtr__SHIFT
- IA_DEBUG_REG4__pipe2_dr_MASK
- IA_DEBUG_REG4__pipe2_dr__SHIFT
- IA_DEBUG_REG4__pipe2_rtr_MASK
- IA_DEBUG_REG4__pipe2_rtr__SHIFT
- IA_DEBUG_REG4__pipe3_dr_MASK
- IA_DEBUG_REG4__pipe3_dr__SHIFT
- IA_DEBUG_REG4__pipe3_rtr_MASK
- IA_DEBUG_REG4__pipe3_rtr__SHIFT
- IA_DEBUG_REG4__pipe4_dr_MASK
- IA_DEBUG_REG4__pipe4_dr__SHIFT
- IA_DEBUG_REG4__pipe4_rtr_MASK
- IA_DEBUG_REG4__pipe4_rtr__SHIFT
- IA_DEBUG_REG4__pipe5_dr_MASK
- IA_DEBUG_REG4__pipe5_dr__SHIFT
- IA_DEBUG_REG4__pipe5_rtr_MASK
- IA_DEBUG_REG4__pipe5_rtr__SHIFT
- IA_DEBUG_REG4__ready_to_read_di_MASK
- IA_DEBUG_REG4__ready_to_read_di__SHIFT
- IA_DEBUG_REG5__di_index_counter_q_15_0_MASK
- IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT
- IA_DEBUG_REG5__draw_input_fifo_empty_MASK
- IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT
- IA_DEBUG_REG5__draw_input_fifo_full_MASK
- IA_DEBUG_REG5__draw_input_fifo_full__SHIFT
- IA_DEBUG_REG5__instanceid_13_0_MASK
- IA_DEBUG_REG5__instanceid_13_0__SHIFT
- IA_DEBUG_REG6__after_group_partial_MASK
- IA_DEBUG_REG6__after_group_partial__SHIFT
- IA_DEBUG_REG6__curr_prim_partial_MASK
- IA_DEBUG_REG6__curr_prim_partial__SHIFT
- IA_DEBUG_REG6__current_shift_q_MASK
- IA_DEBUG_REG6__current_shift_q__SHIFT
- IA_DEBUG_REG6__current_stride_pre_MASK
- IA_DEBUG_REG6__current_stride_pre__SHIFT
- IA_DEBUG_REG6__current_stride_q_MASK
- IA_DEBUG_REG6__current_stride_q__SHIFT
- IA_DEBUG_REG6__extract_group_MASK
- IA_DEBUG_REG6__extract_group__SHIFT
- IA_DEBUG_REG6__first_group_partial_MASK
- IA_DEBUG_REG6__first_group_partial__SHIFT
- IA_DEBUG_REG6__grp_shift_debug_data_MASK
- IA_DEBUG_REG6__grp_shift_debug_data__SHIFT
- IA_DEBUG_REG6__next_group_partial_MASK
- IA_DEBUG_REG6__next_group_partial__SHIFT
- IA_DEBUG_REG6__next_stride_q_MASK
- IA_DEBUG_REG6__next_stride_q__SHIFT
- IA_DEBUG_REG6__second_group_partial_MASK
- IA_DEBUG_REG6__second_group_partial__SHIFT
- IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK
- IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT
- IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK
- IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT
- IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK
- IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT
- IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK
- IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT
- IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK
- IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT
- IA_DEBUG_REG7__reset_indx_state_q_MASK
- IA_DEBUG_REG7__reset_indx_state_q__SHIFT
- IA_DEBUG_REG7__shift_event_flag_p2_q_MASK
- IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT
- IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK
- IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT
- IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK
- IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT
- IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK
- IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT
- IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK
- IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT
- IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK
- IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT
- IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK
- IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT
- IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK
- IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT
- IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK
- IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT
- IA_DEBUG_REG8__di_prim_type_p1_q_MASK
- IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT
- IA_DEBUG_REG8__grp_components_valid_MASK
- IA_DEBUG_REG8__grp_components_valid__SHIFT
- IA_DEBUG_REG8__grp_continued_MASK
- IA_DEBUG_REG8__grp_continued__SHIFT
- IA_DEBUG_REG8__grp_eop_MASK
- IA_DEBUG_REG8__grp_eop__SHIFT
- IA_DEBUG_REG8__grp_eopg_MASK
- IA_DEBUG_REG8__grp_eopg__SHIFT
- IA_DEBUG_REG8__grp_event_flag_MASK
- IA_DEBUG_REG8__grp_event_flag__SHIFT
- IA_DEBUG_REG8__grp_null_primitive_MASK
- IA_DEBUG_REG8__grp_null_primitive__SHIFT
- IA_DEBUG_REG8__grp_output_path_MASK
- IA_DEBUG_REG8__grp_output_path__SHIFT
- IA_DEBUG_REG8__grp_state_sel_MASK
- IA_DEBUG_REG8__grp_state_sel__SHIFT
- IA_DEBUG_REG8__grp_sub_prim_type_MASK
- IA_DEBUG_REG8__grp_sub_prim_type__SHIFT
- IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK
- IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT
- IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK
- IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT
- IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK
- IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT
- IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK
- IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT
- IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK
- IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT
- IA_DEBUG_REG8__two_prim_input_p1_q_MASK
- IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT
- IA_DEBUG_REG9__SPARE0_MASK
- IA_DEBUG_REG9__SPARE0__SHIFT
- IA_DEBUG_REG9__SPARE1_MASK
- IA_DEBUG_REG9__SPARE1__SHIFT
- IA_DEBUG_REG9__eopg_between_prims_p6_MASK
- IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT
- IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK
- IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT
- IA_DEBUG_REG9__gfx_se_switch_p6_MASK
- IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT
- IA_DEBUG_REG9__grp_se1_fifo_empty_MASK
- IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT
- IA_DEBUG_REG9__grp_se1_fifo_full_MASK
- IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT
- IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK
- IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT
- IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK
- IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT
- IA_DEBUG_REG9__prim0_eoi_p6_MASK
- IA_DEBUG_REG9__prim0_eoi_p6__SHIFT
- IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK
- IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT
- IA_DEBUG_REG9__prim1_eoi_p6_MASK
- IA_DEBUG_REG9__prim1_eoi_p6__SHIFT
- IA_DEBUG_REG9__prim1_to_other_se_p6_MASK
- IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT
- IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK
- IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT
- IA_DEBUG_REG9__prim1_xfer_p6_MASK
- IA_DEBUG_REG9__prim1_xfer_p6__SHIFT
- IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK
- IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT
- IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK
- IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT
- IA_DEBUG_REG9__prim_counter_q_MASK
- IA_DEBUG_REG9__prim_counter_q__SHIFT
- IA_DEBUG_REG9__send_to_se1_p6_MASK
- IA_DEBUG_REG9__send_to_se1_p6__SHIFT
- IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK
- IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT
- IA_DEBUG_REG9__two_prim_output_p5_q_MASK
- IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT
- IA_DLED
- IA_ENHANCE__MISC_MASK
- IA_ENHANCE__MISC__SHIFT
- IA_L2PMXEVCNTCR_BASE
- IA_L2PMXEVCNTR_BASE
- IA_L2PMXEVFILTER_BASE
- IA_L2PMXEVTYPER_BASE
- IA_L2_REG_OFFSET
- IA_MASK
- IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK
- IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK
- IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK
- IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK
- IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK
- IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK
- IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK
- IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK
- IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT
- IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK
- IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT
- IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK
- IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT
- IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK
- IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT
- IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK
- IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT
- IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK
- IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT
- IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK
- IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT
- IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK
- IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT
- IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK
- IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT
- IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK
- IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT
- IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK
- IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT
- IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK
- IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT
- IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- IA_PERFCOUNT_SELECT
- IA_PRIMITIVES_COUNT
- IA_PRIMITIVES_COUNT_UDW
- IA_SHIFT
- IA_SKB_STATE
- IA_SUNI_STATS
- IA_TX_DONE
- IA_UTCL1_CNTL__BYPASS_MASK
- IA_UTCL1_CNTL__BYPASS__SHIFT
- IA_UTCL1_CNTL__DROP_MODE_MASK
- IA_UTCL1_CNTL__DROP_MODE__SHIFT
- IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK
- IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT
- IA_UTCL1_CNTL__FORCE_SNOOP_MASK
- IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT
- IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK
- IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT
- IA_UTCL1_CNTL__INVALIDATE_MASK
- IA_UTCL1_CNTL__INVALIDATE__SHIFT
- IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK
- IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT
- IA_UTCL1_CNTL__VMID_RESET_MODE_MASK
- IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT
- IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK
- IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT
- IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK
- IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT
- IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK
- IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT
- IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK
- IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT
- IA_UTCL1_STATUS_2__IA_BUSY_MASK
- IA_UTCL1_STATUS_2__IA_BUSY__SHIFT
- IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK
- IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT
- IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK
- IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT
- IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK
- IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT
- IA_UTCL1_STATUS_2__PRT_DETECTED_MASK
- IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT
- IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK
- IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT
- IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK
- IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT
- IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK
- IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT
- IA_UTCL1_STATUS__FAULT_DETECTED_MASK
- IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT
- IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK
- IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT
- IA_UTCL1_STATUS__PRT_DETECTED_MASK
- IA_UTCL1_STATUS__PRT_DETECTED__SHIFT
- IA_UTCL1_STATUS__PRT_UTCL1ID_MASK
- IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT
- IA_UTCL1_STATUS__RETRY_DETECTED_MASK
- IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT
- IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK
- IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT
- IA_VERTICES_COUNT
- IA_VERTICES_COUNT_UDW
- IA_VMID_OVERRIDE__ENABLE_MASK
- IA_VMID_OVERRIDE__ENABLE__SHIFT
- IA_VMID_OVERRIDE__VMID_MASK
- IA_VMID_OVERRIDE__VMID__SHIFT
- IB
- IB1_INT_ENABLE
- IB1_INT_STAT
- IB2_CTRL
- IB2_CTRL_LCD_BL_ON
- IB2_CTRL_LCD_MASK
- IB2_CTRL_LCD_SD
- IB2_INT_ENABLE
- IB2_INT_STAT
- IBA
- IBA6120_R_PKEY_DIS_SHIFT
- IBA7220_DDRSTAT_LINKLAT_MASK
- IBA7220_HDRHEAD_PKTINT_SHIFT
- IBA7220_IBCC_LINKCMD_SHIFT
- IBA7220_IBC_DLIDLMC_MASK
- IBA7220_IBC_DLIDLMC_SHIFT
- IBA7220_IBC_HRTBT_MASK
- IBA7220_IBC_HRTBT_SHIFT
- IBA7220_IBC_IBTA_1_2_MASK
- IBA7220_IBC_LANE_REV_SUPPORTED
- IBA7220_IBC_LREV_MASK
- IBA7220_IBC_LREV_SHIFT
- IBA7220_IBC_RXPOL_MASK
- IBA7220_IBC_RXPOL_SHIFT
- IBA7220_IBC_SPEED_AUTONEG
- IBA7220_IBC_SPEED_AUTONEG_MASK
- IBA7220_IBC_SPEED_DDR
- IBA7220_IBC_SPEED_SDR
- IBA7220_IBC_WIDTH_1X_ONLY
- IBA7220_IBC_WIDTH_4X_ONLY
- IBA7220_IBC_WIDTH_AUTONEG
- IBA7220_IBC_WIDTH_MASK
- IBA7220_IBC_WIDTH_SHIFT
- IBA7220_KRCVEGRCNT
- IBA7220_LEDBLINK_OFF_SHIFT
- IBA7220_LEDBLINK_ON_SHIFT
- IBA7220_LINKSPEED_SHIFT
- IBA7220_LINKWIDTH_SHIFT
- IBA7220_R_CTXTCFG_SHIFT
- IBA7220_R_INTRAVAIL_SHIFT
- IBA7220_R_PKEY_DIS_SHIFT
- IBA7220_R_TAILUPD_SHIFT
- IBA7220_TID_PA_SHIFT
- IBA7220_TID_SZ_2K
- IBA7220_TID_SZ_4K
- IBA7220_TID_SZ_SHIFT
- IBA7322_HDRHEAD_PKTINT_SHIFT
- IBA7322_IBCC_LINKCMD_SHIFT
- IBA7322_IBCC_LINKINITCMD_MASK
- IBA7322_IBC_DLIDLMC_MASK
- IBA7322_IBC_DLIDLMC_SHIFT
- IBA7322_IBC_HRTBT_LSB
- IBA7322_IBC_HRTBT_MASK
- IBA7322_IBC_HRTBT_RMASK
- IBA7322_IBC_IBTA_1_2_MASK
- IBA7322_IBC_MAX_SPEED_MASK
- IBA7322_IBC_RXPOL_LSB
- IBA7322_IBC_RXPOL_MASK
- IBA7322_IBC_SPEED_DDR
- IBA7322_IBC_SPEED_LSB
- IBA7322_IBC_SPEED_MASK
- IBA7322_IBC_SPEED_QDR
- IBA7322_IBC_SPEED_SDR
- IBA7322_IBC_WIDTH_1X_ONLY
- IBA7322_IBC_WIDTH_4X_ONLY
- IBA7322_IBC_WIDTH_AUTONEG
- IBA7322_LEDBLINK_OFF_SHIFT
- IBA7322_LEDBLINK_ON_SHIFT
- IBA7322_LINKSPEED_SHIFT
- IBA7322_LINKWIDTH_SHIFT
- IBA7322_REDIRECT_VEC_PER_REG
- IBA7322_SENDCHK_BTHQP
- IBA7322_SENDCHK_MINSZ
- IBA7322_SENDCHK_PKEY
- IBA7322_SENDCHK_RAW_IPV6
- IBA7322_SENDCHK_SLID
- IBA7322_TID_PA_SHIFT
- IBA7322_TID_SZ_2K
- IBA7322_TID_SZ_4K
- IBA7322_TID_SZ_SHIFT
- IBALL_3_5G_CONNECT
- IBAMABT
- IBANK_MASK
- IBANK_POS_MASK
- IBANK_POS_SHIFT
- IBANK_SHIFT
- IBAR2
- IBAR3L
- IBAT_TERM_CHG_IEOC
- IBAT_TERM_CHG_IEOC_BMS
- IBAT_TERM_CHG_IEOC_CHG
- IBAT_VDROP_H
- IBAT_VDROP_L
- IBAT_VIRTUAL_CHANNEL
- IBCBUSFRSPCPARITYERR
- IBCBUSTOSPCPARITYERR
- IBCR0
- IBCR2
- IBCT_NOTIFY
- IBCT_POISON
- IBCT_ZFIL_MODE
- IBC_DISABLE
- IBDF_HAS_UDEV_PATH
- IBENABLE_MASK
- IBFT_END
- IBFT_ISCSI_DATE
- IBFT_ISCSI_VERSION
- IBFT_SIGN_LEN
- IBFT_START
- IBF_RETRY_TIMEOUT
- IBIAS
- IBIAS_MASK
- IBIA_LEVEL_MASK
- IBIA_LEVEL_SHFT
- IBIA_NODE_ID_MASK
- IBIA_NODE_ID_SHFT
- IBIMR0
- IBIR
- IBIR_ACKED
- IBIR_ERROR
- IBIR_SLVID
- IBIR_THR
- IBIR_TYPE
- IBIR_TYPE_HJ
- IBIR_TYPE_IBI
- IBIR_TYPE_MR
- IBIR_XFER_BYTES
- IBISR0
- IBI_DATA_FIFO
- IBI_MR_REQ_REJECT
- IBI_QUEUE_CTRL
- IBI_QUEUE_STATUS
- IBI_REQ_REJECT_ALL
- IBI_SIR_REQ_REJECT
- IBI_THR
- IBLOCK
- IBLOCK_BIO_POOL_SIZE
- IBLOCK_DEV
- IBLOCK_MAX_BIO_PER_TASK
- IBLOCK_MAX_CDBS
- IBLOCK_VERSION
- IBLS_BUSY
- IBLS_ERROR
- IBLS_ERROR_SHFT
- IBLS_LENGTH_MASK
- IBM
- IBMASMFS_MAGIC
- IBMASM_CMD_COMPLETE
- IBMASM_CMD_FAILED
- IBMASM_CMD_MAX_BUFFER_SIZE
- IBMASM_CMD_PENDING
- IBMASM_CMD_TIMEOUT_EXTRA
- IBMASM_CMD_TIMEOUT_NORMAL
- IBMASM_DRIVER_VPD
- IBMASM_EVENT_MAX_SIZE
- IBMASM_NAME_SIZE
- IBMASM_NUM_EVENTS
- IBML_LOW_MEXT
- IBML_LOW_SEXT
- IBML_TIMEOUT
- IBMPC_MAP
- IBMVETH_BUFF_LIST_SIZE
- IBMVETH_BUFF_OH
- IBMVETH_BUF_CSUM_GOOD
- IBMVETH_BUF_LEN_MASK
- IBMVETH_BUF_LRG_SND
- IBMVETH_BUF_NO_CSUM
- IBMVETH_BUF_TOGGLE
- IBMVETH_BUF_VALID
- IBMVETH_FILT_LIST_SIZE
- IBMVETH_GET_STAT
- IBMVETH_ILLAN_ACTIVE_TRUNK
- IBMVETH_ILLAN_IPV4_TCP_CSUM
- IBMVETH_ILLAN_IPV6_TCP_CSUM
- IBMVETH_ILLAN_LRG_SND_SUPPORT
- IBMVETH_ILLAN_LRG_SR_ENABLED
- IBMVETH_ILLAN_PADDED_PKT_CSUM
- IBMVETH_ILLAN_TRUNK_PRI_MASK
- IBMVETH_IO_ENTITLEMENT_DEFAULT
- IBMVETH_MAX_BUF_SIZE
- IBMVETH_MAX_POOL_COUNT
- IBMVETH_MIN_MTU
- IBMVETH_NUM_BUFF_POOLS
- IBMVETH_RXQ_CSUM_GOOD
- IBMVETH_RXQ_LRG_PKT
- IBMVETH_RXQ_NO_CSUM
- IBMVETH_RXQ_OFF_MASK
- IBMVETH_RXQ_TOGGLE
- IBMVETH_RXQ_TOGGLE_SHIFT
- IBMVETH_RXQ_VALID
- IBMVETH_STAT_OFF
- IBMVFC_ABORT_TASK_SET
- IBMVFC_ABORT_TIMEOUT
- IBMVFC_ABORT_WAIT_TIMEOUT
- IBMVFC_ACA_TASK
- IBMVFC_ACTIVE
- IBMVFC_ADAPTER_RESID_VALID
- IBMVFC_ADISC
- IBMVFC_ADISC_CANCEL_TIMEOUT
- IBMVFC_ADISC_PLUS_CANCEL_TIMEOUT
- IBMVFC_ADISC_TIMEOUT
- IBMVFC_AE_ADAPTER_FAILED
- IBMVFC_AE_ELS_LOGO
- IBMVFC_AE_ELS_PLOGI
- IBMVFC_AE_ELS_PRLO
- IBMVFC_AE_HALT
- IBMVFC_AE_LINKDOWN
- IBMVFC_AE_LINKUP
- IBMVFC_AE_LINK_DEAD
- IBMVFC_AE_LINK_DOWN
- IBMVFC_AE_LINK_UP
- IBMVFC_AE_LS_LINK_BOUNCED
- IBMVFC_AE_LS_LINK_DEAD
- IBMVFC_AE_LS_LINK_DOWN
- IBMVFC_AE_LS_LINK_UP
- IBMVFC_AE_RESUME
- IBMVFC_AE_RSCN
- IBMVFC_AE_SCN_DOMAIN
- IBMVFC_AE_SCN_FABRIC
- IBMVFC_AE_SCN_GROUP
- IBMVFC_AE_SCN_NPORT
- IBMVFC_ASYNC_EVENT
- IBMVFC_BASIC_REJECT
- IBMVFC_CAN_FLUSH_ON_HALT
- IBMVFC_CAN_MIGRATE
- IBMVFC_CAN_SUPPRESS_ABTS
- IBMVFC_CLASS_3_ERR
- IBMVFC_CLIENT_MIGRATED
- IBMVFC_CLS3_ERROR
- IBMVFC_CMD_FORMAT
- IBMVFC_CMD_IN_PROGRESS
- IBMVFC_CMD_NOT_SUPPORTED
- IBMVFC_CMD_TIMEOUT
- IBMVFC_COMMAND_FAILED
- IBMVFC_CONFIG_ERROR
- IBMVFC_CRQ_CMD_RSP
- IBMVFC_CRQ_FAILURE
- IBMVFC_CRQ_INIT
- IBMVFC_CRQ_INIT_COMPLETE
- IBMVFC_CRQ_INIT_RSP
- IBMVFC_CRQ_XPORT_EVENT
- IBMVFC_DEBUG
- IBMVFC_DEFAULT_LOG_LEVEL
- IBMVFC_DEFAULT_TIMEOUT
- IBMVFC_DEV_LOSS_TMO
- IBMVFC_DISC_TARGETS
- IBMVFC_DISC_TGT_SCSI_ID_MASK
- IBMVFC_DRIVER_DATE
- IBMVFC_DRIVER_VERSION
- IBMVFC_ENETDOWN
- IBMVFC_FABRIC_BUSY
- IBMVFC_FABRIC_MAPPED
- IBMVFC_FABRIC_REJECT
- IBMVFC_FC_CT_IU
- IBMVFC_FC_ELS
- IBMVFC_FC_FAILURE
- IBMVFC_FC_SCSI_ERROR
- IBMVFC_FLUSH_ON_HALT
- IBMVFC_HALTED
- IBMVFC_HEAD_OF_QUEUE
- IBMVFC_HOST_ACTION_ALLOC_TGTS
- IBMVFC_HOST_ACTION_INIT
- IBMVFC_HOST_ACTION_INIT_WAIT
- IBMVFC_HOST_ACTION_LOGO
- IBMVFC_HOST_ACTION_LOGO_WAIT
- IBMVFC_HOST_ACTION_NONE
- IBMVFC_HOST_ACTION_QUERY
- IBMVFC_HOST_ACTION_QUERY_TGTS
- IBMVFC_HOST_ACTION_REENABLE
- IBMVFC_HOST_ACTION_RESET
- IBMVFC_HOST_ACTION_TGT_DEL
- IBMVFC_HOST_ACTION_TGT_DEL_FAILED
- IBMVFC_HOST_ACTION_TGT_INIT
- IBMVFC_HOST_IO_BUS
- IBMVFC_HOST_OFFLINE
- IBMVFC_HW_EVENT_LOGGED
- IBMVFC_HW_FAILURE
- IBMVFC_IMPLICIT_LOGOUT
- IBMVFC_INITIALIZING
- IBMVFC_INIT_TIMEOUT
- IBMVFC_INSUFFICIENT_RESOURCE
- IBMVFC_INTERNAL_CANCEL_KEY
- IBMVFC_INVALID_CT_IU_SIZE
- IBMVFC_INVALID_ELS_CMD_CODE
- IBMVFC_INVALID_PARAMETER
- IBMVFC_INVALID_VERSION
- IBMVFC_LINK_DEAD
- IBMVFC_LINK_DEAD_ERR
- IBMVFC_LINK_DOWN
- IBMVFC_LINK_DOWN_ERR
- IBMVFC_LINK_HALTED
- IBMVFC_LOGICAL_BUSY
- IBMVFC_LOGICAL_ERROR
- IBMVFC_LS_REJECT
- IBMVFC_LUN_RESET
- IBMVFC_MAD_CRQ_ERROR
- IBMVFC_MAD_DRIVER_FAILED
- IBMVFC_MAD_FAILED
- IBMVFC_MAD_FORMAT
- IBMVFC_MAD_NOT_SUPPORTED
- IBMVFC_MAD_SUCCESS
- IBMVFC_MAX_CDB_LEN
- IBMVFC_MAX_CMDS_PER_LUN
- IBMVFC_MAX_DISC_THREADS
- IBMVFC_MAX_HOST_INIT_RETRIES
- IBMVFC_MAX_LUN
- IBMVFC_MAX_NAME
- IBMVFC_MAX_REQUESTS_DEFAULT
- IBMVFC_MAX_SECTORS
- IBMVFC_MAX_TARGETS
- IBMVFC_MAX_TGT_INIT_RETRIES
- IBMVFC_MISSING_PARAMETER
- IBMVFC_NAME
- IBMVFC_NAME_SERVER_FAIL
- IBMVFC_NATIVE_FC
- IBMVFC_NO_CRQ
- IBMVFC_NO_MEM_DESC
- IBMVFC_NPIV_LOGIN
- IBMVFC_NPIV_LOGOUT
- IBMVFC_NUM_INTERNAL_REQ
- IBMVFC_NUM_TRACE_ENTRIES
- IBMVFC_NUM_TRACE_INDEX_BITS
- IBMVFC_ORDERED_TASK
- IBMVFC_OS_LINUX
- IBMVFC_PARTITION_MIGRATED
- IBMVFC_PARTNER_DEREGISTER
- IBMVFC_PARTNER_FAILED
- IBMVFC_PASSTHRU
- IBMVFC_PASSTHRU_CANCEL_KEY
- IBMVFC_PLOGI_REQUIRED
- IBMVFC_PORT_BUSY
- IBMVFC_PORT_LOGIN
- IBMVFC_PORT_NAME_NOT_REG
- IBMVFC_PORT_REJECT
- IBMVFC_PRLI_DATA_OVERLAY
- IBMVFC_PRLI_EST_IMG_PAIR
- IBMVFC_PRLI_INITIATOR_FUNC
- IBMVFC_PRLI_ORIG_PA_VALID
- IBMVFC_PRLI_READ_FCP_XFER_RDY_DISABLED
- IBMVFC_PRLI_RESP_PA_VALID
- IBMVFC_PRLI_RETRY
- IBMVFC_PRLI_TARGET_FUNC
- IBMVFC_PRLI_TASK_RETRY
- IBMVFC_PRLI_WR_FCP_XFER_RDY_DISABLED
- IBMVFC_PROCESS_LOGIN
- IBMVFC_PROTOCOL_ERROR
- IBMVFC_QUERY_TARGET
- IBMVFC_RDDATA
- IBMVFC_READ
- IBMVFC_SCATTERLIST
- IBMVFC_SCSI_FCP_TYPE
- IBMVFC_SERVER_NOT_AVAIL
- IBMVFC_SIMPLE_TASK
- IBMVFC_SW_FAILURE
- IBMVFC_TARGET_RESET
- IBMVFC_TGT_ACTION_DELETED_RPORT
- IBMVFC_TGT_ACTION_DEL_RPORT
- IBMVFC_TGT_ACTION_INIT
- IBMVFC_TGT_ACTION_INIT_WAIT
- IBMVFC_TGT_ACTION_NONE
- IBMVFC_TGT_MEMPOOL_SZ
- IBMVFC_TMF
- IBMVFC_TMF_ABORT_TASK
- IBMVFC_TMF_ABORT_TASK_SET
- IBMVFC_TMF_LUA_VALID
- IBMVFC_TMF_LUN_RESET
- IBMVFC_TMF_MAD
- IBMVFC_TMF_SUPPRESS_ABTS
- IBMVFC_TMF_TGT_RESET
- IBMVFC_TRACE_SIZE
- IBMVFC_TRANS_CANCELLED
- IBMVFC_TRANS_CANCELLED_IMPLICIT
- IBMVFC_TRC_END
- IBMVFC_TRC_START
- IBMVFC_UNABLE_TO_ESTABLISH
- IBMVFC_UNABLE_TO_PERFORM_REQ
- IBMVFC_UNABLE_TO_REGISTER
- IBMVFC_VENDOR_SPECIFIC
- IBMVFC_VIOS_FAILURE
- IBMVFC_VIOS_LOGGED
- IBMVFC_WRDATA
- IBMVFC_WRITE
- IBMVFC_XPORT_BUSY
- IBMVFC_XPORT_DEAD
- IBMVFC_XPORT_FAULT
- IBMVFC_XPORT_GENERAL
- IBMVMC_DRIVER_VERSION
- IBMVMC_H
- IBMVMC_PROTOCOL_VERSION
- IBMVNIC_100GBPS
- IBMVNIC_100MBPS
- IBMVNIC_10GBP
- IBMVNIC_10MBPS
- IBMVNIC_1GBPS
- IBMVNIC_200GBPS
- IBMVNIC_25GBPS
- IBMVNIC_40GBPS
- IBMVNIC_50GBPS
- IBMVNIC_AUTONEG
- IBMVNIC_AUTONEG_DUPLEX
- IBMVNIC_BUFFER_HLEN
- IBMVNIC_BUFFS_PER_POOL
- IBMVNIC_CAN_CHG_PHYS_PARMS
- IBMVNIC_CHG_TRACE_BUFF_SZ
- IBMVNIC_CRQ_CMD
- IBMVNIC_CRQ_CMD_RSP
- IBMVNIC_CRQ_INIT
- IBMVNIC_CRQ_INIT_CMD
- IBMVNIC_CRQ_INIT_COMPLETE
- IBMVNIC_CRQ_INIT_RSP
- IBMVNIC_CRQ_XPORT_EVENT
- IBMVNIC_DEVICE_FAILOVER
- IBMVNIC_DISABLE_ALL
- IBMVNIC_DISABLE_MC
- IBMVNIC_DRIVER_VERSION
- IBMVNIC_ENABLE_ALL
- IBMVNIC_ENABLE_MC
- IBMVNIC_END_FRAME
- IBMVNIC_ERROR_LEVEL
- IBMVNIC_EXACT_MC
- IBMVNIC_EXTERNAL_LOOPBACK
- IBMVNIC_FATAL_ERROR
- IBMVNIC_FULL_DUPLEX
- IBMVNIC_GET_STAT
- IBMVNIC_HALF_DUPLEX
- IBMVNIC_HDR_DESC
- IBMVNIC_HDR_EXT_DESC
- IBMVNIC_INITIAL_VERSION
- IBMVNIC_INIT_FAILED
- IBMVNIC_INTERNAL_LOOPBACK
- IBMVNIC_INVALID_MAP
- IBMVNIC_IO_ENTITLEMENT_DEFAULT
- IBMVNIC_IP_CHKSUM_GOOD
- IBMVNIC_LOGICAL_LNK_ACTIVE
- IBMVNIC_LOGICAL_LNK_DN
- IBMVNIC_LOGICAL_LNK_QUERY
- IBMVNIC_LOGICAL_LNK_UP
- IBMVNIC_MAC_ACL
- IBMVNIC_MAX_FRAGS_PER_CRQ
- IBMVNIC_MAX_LTB_SIZE
- IBMVNIC_MAX_QUEUES
- IBMVNIC_MAX_QUEUE_SZ
- IBMVNIC_NAME
- IBMVNIC_OPEN_FAILED
- IBMVNIC_PARTITION_MIGRATED
- IBMVNIC_PHYSICAL_PORT
- IBMVNIC_PHYS_LINK_ACTIVE
- IBMVNIC_PROMISC
- IBMVNIC_RESET_DELAY
- IBMVNIC_RX_WEIGHT
- IBMVNIC_SGE_DESC
- IBMVNIC_STATS_TIMEOUT
- IBMVNIC_STAT_OFF
- IBMVNIC_TCP_CHKSUM
- IBMVNIC_TCP_UDP_CHKSUM_GOOD
- IBMVNIC_TRACE_LEVEL
- IBMVNIC_TRACE_OFF
- IBMVNIC_TRACE_ON
- IBMVNIC_TRACE_PAUSE
- IBMVNIC_TRACE_RESUME
- IBMVNIC_TSO_BUFS
- IBMVNIC_TSO_BUF_SZ
- IBMVNIC_TSO_POOL_MASK
- IBMVNIC_TX_CHKSUM_OFFLOAD
- IBMVNIC_TX_COMP_NEEDED
- IBMVNIC_TX_DESC
- IBMVNIC_TX_DESC_VERSIONS
- IBMVNIC_TX_LSO
- IBMVNIC_TX_PROT_IPV4
- IBMVNIC_TX_PROT_IPV6
- IBMVNIC_TX_PROT_TCP
- IBMVNIC_TX_PROT_UDP
- IBMVNIC_TX_VLAN_INSERT
- IBMVNIC_TX_VLAN_PRESENT
- IBMVNIC_UDP_CHKSUM
- IBMVNIC_USE_SERVER_MAXES
- IBMVNIC_VLAN_ACL
- IBMVNIC_VLAN_STRIPPED
- IBMVSCSIS_NAMELEN
- IBMVSCSIS_VERSION
- IBMVSCSI_CMDS_PER_LUN_DEFAULT
- IBMVSCSI_H
- IBMVSCSI_HOST_ACTION_NONE
- IBMVSCSI_HOST_ACTION_REENABLE
- IBMVSCSI_HOST_ACTION_RESET
- IBMVSCSI_HOST_ACTION_UNBLOCK
- IBMVSCSI_MAX_CMDS_PER_LUN
- IBMVSCSI_MAX_LUN
- IBMVSCSI_MAX_REQUESTS_DEFAULT
- IBMVSCSI_MAX_SECTORS_DEFAULT
- IBMVSCSI_VERSION
- IBMVTPM_VALID_CMD
- IBM_4543_PRODUCT_ID
- IBM_454B_PRODUCT_ID
- IBM_454C_PRODUCT_ID
- IBM_BIOS_MODULE_ALIAS
- IBM_DEVICE
- IBM_DRCONNECTOR
- IBM_FANRPM
- IBM_FS3270_MAJOR
- IBM_HARDWARE_ID1
- IBM_HARDWARE_ID2
- IBM_POWERSUPPLY
- IBM_SURVEILLANCE
- IBM_TTY3270_MAJOR
- IBM_VENDOR_ID
- IBM_VETH_INVALID_MAP
- IBM_VOLTAGE
- IBOvals
- IBQDBGADDR_G
- IBQDBGADDR_M
- IBQDBGADDR_S
- IBQDBGADDR_V
- IBQDBGBUSY_F
- IBQDBGBUSY_S
- IBQDBGBUSY_V
- IBQDBGEN_F
- IBQDBGEN_S
- IBQDBGEN_V
- IBQNCSIPARERR_F
- IBQNCSIPARERR_S
- IBQNCSIPARERR_V
- IBQRDADDR_G
- IBQRDADDR_M
- IBQRDADDR_S
- IBQSELECT_F
- IBQSELECT_S
- IBQSELECT_V
- IBQSGEHIPARERR_F
- IBQSGEHIPARERR_S
- IBQSGEHIPARERR_V
- IBQSGELOPARERR_F
- IBQSGELOPARERR_S
- IBQSGELOPARERR_V
- IBQTP0PARERR_F
- IBQTP0PARERR_S
- IBQTP0PARERR_V
- IBQTP1PARERR_F
- IBQTP1PARERR_S
- IBQTP1PARERR_V
- IBQULPPARERR_F
- IBQULPPARERR_S
- IBQULPPARERR_V
- IBQWRADDR_G
- IBQWRADDR_M
- IBQWRADDR_S
- IBSCTL
- IBSCTL_LVT_OFFSET_MASK
- IBSCTL_LVT_OFFSET_VALID
- IBSD
- IBSD_RESYNC_TRIES
- IBSELR1
- IBSELR10
- IBSELR11
- IBSELR12
- IBSELR13
- IBSELR14
- IBSELR15
- IBSELR2
- IBSELR3
- IBSELR4
- IBSELR5
- IBSELR6
- IBSELR7
- IBSELR8
- IBSELR9
- IBSHIFT
- IBSS_HEARTBEAT_OFFLOAD
- IBSS_MERGE
- IBSS_PARA_IE_ID
- IBSS_PARA_IE_LEN
- IBSS_START_MAC_ID
- IBS_CAPS_AVAIL
- IBS_CAPS_BRNTRGT
- IBS_CAPS_DEFAULT
- IBS_CAPS_FETCHCTLEXTD
- IBS_CAPS_FETCHSAM
- IBS_CAPS_OPBRNFUSE
- IBS_CAPS_OPCNT
- IBS_CAPS_OPCNTEXT
- IBS_CAPS_OPDATA4
- IBS_CAPS_OPSAM
- IBS_CAPS_RDWROPCNT
- IBS_CAPS_RIPINVALIDCHK
- IBS_CPUID_FEATURES
- IBS_ENABLED
- IBS_FETCH_CNT
- IBS_FETCH_CODE
- IBS_FETCH_CONFIG_MASK
- IBS_FETCH_ENABLE
- IBS_FETCH_MAX_CNT
- IBS_FETCH_RAND_EN
- IBS_FETCH_SIZE
- IBS_FETCH_VAL
- IBS_MAX_STATES
- IBS_OP_CNT_CTL
- IBS_OP_CODE
- IBS_OP_CONFIG_MASK
- IBS_OP_CUR_CNT
- IBS_OP_CUR_CNT_RAND
- IBS_OP_ENABLE
- IBS_OP_MAX_CNT
- IBS_OP_MAX_CNT_EXT
- IBS_OP_SIZE
- IBS_OP_VAL
- IBS_RANDOM_BITS
- IBS_RANDOM_MASK
- IBS_RANDOM_MAXCNT_OFFSET
- IBS_RIP_INVALID
- IBS_STARTED
- IBS_STOPPED
- IBS_STOPPING
- IBS_TX_IDLE_TIMEOUT_MS
- IBS_WAKE_RETRANS_TIMEOUT_MS
- IBT_REG_MODE_16BIT
- IBT_REG_MODE_32BIT
- IBT_REG_MODE_8BIT
- IBUS_SERVO_COUNT
- IBW_SWR_OFFSET
- IBX_AUD_CFG
- IBX_AUD_CNTL_ST
- IBX_AUD_CNTL_ST2
- IBX_CP_READY
- IBX_ELD_ACK
- IBX_ELD_ADDRESS_MASK
- IBX_ELD_BUFFER_SIZE_MASK
- IBX_ELD_VALID
- IBX_HDMIW_HDMIEDID
- IB_6120_LT_STATE_CFGDEBOUNCE
- IB_6120_LT_STATE_CFGIDLE
- IB_6120_LT_STATE_CFGRCVFCFG
- IB_6120_LT_STATE_CFGWAITRMT
- IB_6120_LT_STATE_DISABLED
- IB_6120_LT_STATE_LINKUP
- IB_6120_LT_STATE_POLLACTIVE
- IB_6120_LT_STATE_POLLQUIET
- IB_6120_LT_STATE_RECOVERIDLE
- IB_6120_LT_STATE_RECOVERRETRAIN
- IB_6120_LT_STATE_RECOVERWAITRMT
- IB_6120_LT_STATE_SLEEPDELAY
- IB_6120_LT_STATE_SLEEPQUIET
- IB_6120_L_STATE_ACTIVE
- IB_6120_L_STATE_ACT_DEFER
- IB_6120_L_STATE_ARM
- IB_6120_L_STATE_DOWN
- IB_6120_L_STATE_INIT
- IB_7220_LT_STATE_CFGDEBOUNCE
- IB_7220_LT_STATE_CFGENH
- IB_7220_LT_STATE_CFGIDLE
- IB_7220_LT_STATE_CFGRCVFCFG
- IB_7220_LT_STATE_CFGWAITRMT
- IB_7220_LT_STATE_DISABLED
- IB_7220_LT_STATE_LINKUP
- IB_7220_LT_STATE_POLLACTIVE
- IB_7220_LT_STATE_POLLQUIET
- IB_7220_LT_STATE_RECOVERIDLE
- IB_7220_LT_STATE_RECOVERRETRAIN
- IB_7220_LT_STATE_RECOVERWAITRMT
- IB_7220_LT_STATE_SLEEPDELAY
- IB_7220_LT_STATE_SLEEPQUIET
- IB_7220_LT_STATE_TXREVLANES
- IB_7220_L_STATE_ACTIVE
- IB_7220_L_STATE_ACT_DEFER
- IB_7220_L_STATE_ARM
- IB_7220_L_STATE_DOWN
- IB_7220_L_STATE_INIT
- IB_7220_SERDES
- IB_7322_LT_STATE_CFGDEBOUNCE
- IB_7322_LT_STATE_CFGENH
- IB_7322_LT_STATE_CFGIDLE
- IB_7322_LT_STATE_CFGRCVFCFG
- IB_7322_LT_STATE_CFGTEST
- IB_7322_LT_STATE_CFGWAITENH
- IB_7322_LT_STATE_CFGWAITRMT
- IB_7322_LT_STATE_CFGWAITRMTTEST
- IB_7322_LT_STATE_DISABLED
- IB_7322_LT_STATE_LINKUP
- IB_7322_LT_STATE_POLLACTIVE
- IB_7322_LT_STATE_POLLQUIET
- IB_7322_LT_STATE_RECOVERIDLE
- IB_7322_LT_STATE_RECOVERRETRAIN
- IB_7322_LT_STATE_RECOVERWAITRMT
- IB_7322_LT_STATE_SLEEPDELAY
- IB_7322_LT_STATE_SLEEPQUIET
- IB_7322_LT_STATE_TXREVLANES
- IB_7322_L_STATE_ACTIVE
- IB_7322_L_STATE_ACT_DEFER
- IB_7322_L_STATE_ARM
- IB_7322_L_STATE_DOWN
- IB_7322_L_STATE_INIT
- IB_ACCESS_HUGETLB
- IB_ACCESS_LOCAL_WRITE
- IB_ACCESS_MW_BIND
- IB_ACCESS_ON_DEMAND
- IB_ACCESS_REMOTE
- IB_ACCESS_REMOTE_ATOMIC
- IB_ACCESS_REMOTE_READ
- IB_ACCESS_REMOTE_WRITE
- IB_ACCESS_SUPPORTED
- IB_ACK_IN_FLIGHT
- IB_ACK_REQUESTED
- IB_ADDR_H
- IB_AETH_CREDIT_INVAL
- IB_AETH_CREDIT_MASK
- IB_AETH_CREDIT_SHIFT
- IB_AETH_NAK_SHIFT
- IB_AE_IOCB_RSP_I
- IB_AE_IOCB_RSP_OI
- IB_AH_GRH
- IB_ATC_EN
- IB_ATOMIC_GLOB
- IB_ATOMIC_HCA
- IB_ATOMIC_NONE
- IB_BASE_ADDR_HI_OFFSET
- IB_BASE_ADDR_LO_OFFSET
- IB_BECN_MASK
- IB_BECN_SHIFT
- IB_BECN_SMASK
- IB_BM_ATTR_MOD_RESP
- IB_BTHE_E
- IB_BTHE_E_SHIFT
- IB_BTH_A_MASK
- IB_BTH_A_SHIFT
- IB_BTH_BYTES
- IB_BTH_MIG_REQ
- IB_BTH_M_MASK
- IB_BTH_M_SHIFT
- IB_BTH_OPCODE_MASK
- IB_BTH_OPCODE_SHIFT
- IB_BTH_PAD_MASK
- IB_BTH_PAD_SHIFT
- IB_BTH_PKEY_MASK
- IB_BTH_REQ_ACK
- IB_BTH_SE_MASK
- IB_BTH_SE_SHIFT
- IB_BTH_SOLICITED
- IB_BTH_TVER_MASK
- IB_BTH_TVER_SHIFT
- IB_CACHE_GID_DEFAULT_MODE_DELETE
- IB_CACHE_GID_DEFAULT_MODE_SET
- IB_CCT_ENTRIES
- IB_CCT_MIN_ENTRIES
- IB_CC_ATTR_CA_CONGESTION_SETTING
- IB_CC_ATTR_CLASSPORTINFO
- IB_CC_ATTR_CONGESTION_CONTROL_TABLE
- IB_CC_ATTR_CONGESTION_INFO
- IB_CC_ATTR_CONGESTION_KEY_INFO
- IB_CC_ATTR_CONGESTION_LOG
- IB_CC_ATTR_NOTICE
- IB_CC_ATTR_SWITCH_CONGESTION_SETTING
- IB_CC_ATTR_SWITCH_PORT_CONGESTION_SETTING
- IB_CC_ATTR_TIME_STAMP
- IB_CC_CCS_ENTRIES
- IB_CC_CCS_PC_SL_BASED
- IB_CC_CI_FLAGS_CREDIT_STARVATION
- IB_CC_CLEC_SERVICETYPE_RC
- IB_CC_CLEC_SERVICETYPE_RD
- IB_CC_CLEC_SERVICETYPE_UC
- IB_CC_CLEC_SERVICETYPE_UD
- IB_CC_CL_CA_LOGEVENTS_LEN
- IB_CC_CPI_CM_CAP2
- IB_CC_CPI_CM_ENHANCEDPORT0_CC
- IB_CC_CPI_CM_GET_SET_NOTICE
- IB_CC_CPI_CM_TRAP_GEN
- IB_CC_MAD_LOGDATA_LEN
- IB_CC_MAD_MGMTDATA_LEN
- IB_CC_SVCTYPE_RC
- IB_CC_SVCTYPE_RD
- IB_CC_SVCTYPE_UC
- IB_CC_SVCTYPE_UD
- IB_CC_TABLE_CAP_DEFAULT
- IB_CC_TABLE_ENTRY_INCREASE_DEFAULT
- IB_CC_TABLE_ENTRY_TIMER_DEFAULT
- IB_CC_THRESHOLD_MAX
- IB_CC_THRESHOLD_MIN
- IB_CC_THRESHOLD_NONE
- IB_CC_TRAP_KEY_VIOLATION
- IB_CI_BASE_ADDR_HI_OFFSET
- IB_CI_BASE_ADDR_LO_OFFSET
- IB_CLASS_PORT_INFO_RESP_TIME_FIELD_SIZE
- IB_CLASS_PORT_INFO_RESP_TIME_MASK
- IB_CMA_SERVICE_ID
- IB_CMA_SERVICE_ID_MASK
- IB_CMUDONE
- IB_CM_APR_INFO_LENGTH
- IB_CM_APR_INVALID_COMM_ID
- IB_CM_APR_INVALID_FLOW_LABEL
- IB_CM_APR_INVALID_GID
- IB_CM_APR_INVALID_HOP_LIMIT
- IB_CM_APR_INVALID_LID
- IB_CM_APR_INVALID_PACKET_RATE
- IB_CM_APR_INVALID_QPN_EECN
- IB_CM_APR_INVALID_SL
- IB_CM_APR_INVALID_TCLASS
- IB_CM_APR_IS_CURRENT
- IB_CM_APR_PRIVATE_DATA_SIZE
- IB_CM_APR_RECEIVED
- IB_CM_APR_REDIRECT
- IB_CM_APR_REJECT
- IB_CM_APR_SUCCESS
- IB_CM_APR_UNSUPPORTED
- IB_CM_ASSIGN_SERVICE_ID
- IB_CM_CLASS_VERSION
- IB_CM_DREP_PRIVATE_DATA_SIZE
- IB_CM_DREP_RECEIVED
- IB_CM_DREQ_ERROR
- IB_CM_DREQ_PRIVATE_DATA_SIZE
- IB_CM_DREQ_RCVD
- IB_CM_DREQ_RECEIVED
- IB_CM_DREQ_SENT
- IB_CM_ESTABLISHED
- IB_CM_H
- IB_CM_IDLE
- IB_CM_LAP_ERROR
- IB_CM_LAP_IDLE
- IB_CM_LAP_PRIVATE_DATA_SIZE
- IB_CM_LAP_RCVD
- IB_CM_LAP_RECEIVED
- IB_CM_LAP_SENT
- IB_CM_LAP_UNINIT
- IB_CM_LISTEN
- IB_CM_MRA_FLAG_DELAY
- IB_CM_MRA_LAP_RCVD
- IB_CM_MRA_LAP_SENT
- IB_CM_MRA_PRIVATE_DATA_SIZE
- IB_CM_MRA_RECEIVED
- IB_CM_MRA_REP_RCVD
- IB_CM_MRA_REP_SENT
- IB_CM_MRA_REQ_RCVD
- IB_CM_MRA_REQ_SENT
- IB_CM_REJ_ARI_LENGTH
- IB_CM_REJ_CONSUMER_DEFINED
- IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID
- IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES
- IB_CM_REJ_INVALID_ALT_FLOW_LABEL
- IB_CM_REJ_INVALID_ALT_GID
- IB_CM_REJ_INVALID_ALT_HOP_LIMIT
- IB_CM_REJ_INVALID_ALT_LID
- IB_CM_REJ_INVALID_ALT_PACKET_RATE
- IB_CM_REJ_INVALID_ALT_SL
- IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS
- IB_CM_REJ_INVALID_CLASS_VERSION
- IB_CM_REJ_INVALID_COMM_ID
- IB_CM_REJ_INVALID_COMM_INSTANCE
- IB_CM_REJ_INVALID_FLOW_LABEL
- IB_CM_REJ_INVALID_GID
- IB_CM_REJ_INVALID_HOP_LIMIT
- IB_CM_REJ_INVALID_LID
- IB_CM_REJ_INVALID_MTU
- IB_CM_REJ_INVALID_PACKET_RATE
- IB_CM_REJ_INVALID_RNR_RETRY
- IB_CM_REJ_INVALID_SERVICE_ID
- IB_CM_REJ_INVALID_SL
- IB_CM_REJ_INVALID_TRAFFIC_CLASS
- IB_CM_REJ_INVALID_TRANSPORT_TYPE
- IB_CM_REJ_NO_EEC
- IB_CM_REJ_NO_QP
- IB_CM_REJ_NO_RESOURCES
- IB_CM_REJ_PORT_CM_REDIRECT
- IB_CM_REJ_PORT_REDIRECT
- IB_CM_REJ_PRIVATE_DATA_SIZE
- IB_CM_REJ_RDC_NOT_EXIST
- IB_CM_REJ_RECEIVED
- IB_CM_REJ_STALE_CONN
- IB_CM_REJ_TIMEOUT
- IB_CM_REJ_UNSUPPORTED
- IB_CM_REP_ERROR
- IB_CM_REP_PRIVATE_DATA_SIZE
- IB_CM_REP_RCVD
- IB_CM_REP_RECEIVED
- IB_CM_REP_SENT
- IB_CM_REQ_ERROR
- IB_CM_REQ_PRIVATE_DATA_SIZE
- IB_CM_REQ_RCVD
- IB_CM_REQ_RECEIVED
- IB_CM_REQ_SENT
- IB_CM_RTU_PRIVATE_DATA_SIZE
- IB_CM_RTU_RECEIVED
- IB_CM_SIDR_REP_INFO_LENGTH
- IB_CM_SIDR_REP_PRIVATE_DATA_SIZE
- IB_CM_SIDR_REP_RECEIVED
- IB_CM_SIDR_REQ_ERROR
- IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE
- IB_CM_SIDR_REQ_RCVD
- IB_CM_SIDR_REQ_RECEIVED
- IB_CM_SIDR_REQ_SENT
- IB_CM_TIMEWAIT
- IB_CM_TIMEWAIT_EXIT
- IB_CM_USER_ESTABLISHED
- IB_COUNTER_BYTES
- IB_COUNTER_PACKETS
- IB_CQ_MODERATE
- IB_CQ_NEXT_COMP
- IB_CQ_REPORT_MISSED_EVENTS
- IB_CQ_SOLICITED
- IB_CQ_SOLICITED_MASK
- IB_CTRL2
- IB_DEFAULT_GID_PREFIX
- IB_DEFAULT_PKEY_FULL
- IB_DEFAULT_PKEY_PARTIAL
- IB_DEFAULT_Q_KEY
- IB_DEFAULT_SERVICE_LEASE
- IB_DETH_BYTES
- IB_DEVICE_ALLOW_USER_UNREG
- IB_DEVICE_AUTO_PATH_MIG
- IB_DEVICE_BAD_PKEY_CNTR
- IB_DEVICE_BAD_QKEY_CNTR
- IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
- IB_DEVICE_CHANGE_PHY_PORT
- IB_DEVICE_CROSS_CHANNEL
- IB_DEVICE_CURR_QP_STATE_MOD
- IB_DEVICE_INTEGRITY_HANDOVER
- IB_DEVICE_LOCAL_DMA_LKEY
- IB_DEVICE_MANAGED_FLOW_STEERING
- IB_DEVICE_MEM_MGT_EXTENSIONS
- IB_DEVICE_MEM_WINDOW
- IB_DEVICE_MEM_WINDOW_TYPE_2A
- IB_DEVICE_MEM_WINDOW_TYPE_2B
- IB_DEVICE_MODIFY_NODE_DESC
- IB_DEVICE_MODIFY_SYS_IMAGE_GUID
- IB_DEVICE_NAME_MAX
- IB_DEVICE_NODE_DESC_MAX
- IB_DEVICE_N_NOTIFY_CQ
- IB_DEVICE_ON_DEMAND_PAGING
- IB_DEVICE_PCI_WRITE_END_PADDING
- IB_DEVICE_PORT_ACTIVE_EVENT
- IB_DEVICE_RAW_IP_CSUM
- IB_DEVICE_RAW_MULTI
- IB_DEVICE_RAW_SCATTER_FCS
- IB_DEVICE_RC_IP_CSUM
- IB_DEVICE_RC_RNR_NAK_GEN
- IB_DEVICE_RDMA_NETDEV_OPA_VNIC
- IB_DEVICE_RESIZE_MAX_WR
- IB_DEVICE_SG_GAPS_REG
- IB_DEVICE_SHUTDOWN_PORT
- IB_DEVICE_SRQ_RESIZE
- IB_DEVICE_SYS_IMAGE_GUID
- IB_DEVICE_UD_AV_PORT_ENFORCE
- IB_DEVICE_UD_IP_CSUM
- IB_DEVICE_UD_TSO
- IB_DEVICE_VIRTUAL_FUNCTION
- IB_DEVICE_XRC
- IB_DM_MAD_H
- IB_DRV_NAME
- IB_ETH_BYTES
- IB_EVENT_CLIENT_REREGISTER
- IB_EVENT_COMM_EST
- IB_EVENT_CQ_ERR
- IB_EVENT_DEVICE_FATAL
- IB_EVENT_GID_CHANGE
- IB_EVENT_LID_CHANGE
- IB_EVENT_LIST
- IB_EVENT_PATH_MIG
- IB_EVENT_PATH_MIG_ERR
- IB_EVENT_PKEY_CHANGE
- IB_EVENT_PORT_ACTIVE
- IB_EVENT_PORT_ERR
- IB_EVENT_QP_ACCESS_ERR
- IB_EVENT_QP_FATAL
- IB_EVENT_QP_LAST_WQE_REACHED
- IB_EVENT_QP_REQ_ERR
- IB_EVENT_SM_CHANGE
- IB_EVENT_SQ_DRAINED
- IB_EVENT_SRQ_ERR
- IB_EVENT_SRQ_LIMIT_REACHED
- IB_EVENT_WQ_FATAL
- IB_EXT_ATOMICETH_BYTES
- IB_EXT_XRC_BYTES
- IB_E_BITSEXTANT
- IB_FECN_MASK
- IB_FECN_SHIFT
- IB_FECN_SMASK
- IB_FLAG_ERROR
- IB_FLAG_ERROR_MASK
- IB_FLOW_ACTION_ESP
- IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
- IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS
- IB_FLOW_ACTION_UNSPECIFIED
- IB_FLOW_ATTR_ALL_DEFAULT
- IB_FLOW_ATTR_FLAGS_DONT_TRAP
- IB_FLOW_ATTR_FLAGS_EGRESS
- IB_FLOW_ATTR_FLAGS_RESERVED
- IB_FLOW_ATTR_MC_DEFAULT
- IB_FLOW_ATTR_NORMAL
- IB_FLOW_ATTR_SNIFFER
- IB_FLOW_DOMAIN_ETHTOOL
- IB_FLOW_DOMAIN_NIC
- IB_FLOW_DOMAIN_NUM
- IB_FLOW_DOMAIN_RFS
- IB_FLOW_DOMAIN_USER
- IB_FLOW_SPEC_ACTION_COUNT
- IB_FLOW_SPEC_ACTION_DROP
- IB_FLOW_SPEC_ACTION_HANDLE
- IB_FLOW_SPEC_ACTION_TAG
- IB_FLOW_SPEC_ESP
- IB_FLOW_SPEC_ETH
- IB_FLOW_SPEC_GRE
- IB_FLOW_SPEC_IB
- IB_FLOW_SPEC_INNER
- IB_FLOW_SPEC_IPV4
- IB_FLOW_SPEC_IPV6
- IB_FLOW_SPEC_LAYER_MASK
- IB_FLOW_SPEC_MPLS
- IB_FLOW_SPEC_SUPPORT_LAYERS
- IB_FLOW_SPEC_TCP
- IB_FLOW_SPEC_UDP
- IB_FLOW_SPEC_VXLAN_TUNNEL
- IB_FMR_HASH_BITS
- IB_FMR_HASH_MASK
- IB_FMR_HASH_SIZE
- IB_FMR_MAX_REMAPS
- IB_FMR_POOL_H
- IB_FW_VERSION_NAME_MAX
- IB_GET_POST_CREDITS
- IB_GET_SEND_CREDITS
- IB_GID_TYPE_IB
- IB_GID_TYPE_ROCE
- IB_GID_TYPE_ROCE_UDP_ENCAP
- IB_GID_TYPE_SIZE
- IB_GRH_BYTES
- IB_GRH_FLOW_MASK
- IB_GRH_FLOW_SHIFT
- IB_GRH_NEXT_HDR
- IB_GRH_TCLASS_MASK
- IB_GRH_TCLASS_SHIFT
- IB_GRH_VERSION
- IB_GRH_VERSION_MASK
- IB_GRH_VERSION_SHIFT
- IB_GUARD_T10DIF_CRC
- IB_GUARD_T10DIF_CSUM
- IB_HDRS_H
- IB_HWE_BITSEXTANT
- IB_ICRC_BYTES
- IB_IOCTL_MAGIC
- IB_IP4_BYTES
- IB_IPV4_DONT_FRAG
- IB_IPV4_MORE_FRAG
- IB_IP_IOCB_RSP_3032_CE
- IB_IP_IOCB_RSP_3032_I
- IB_IP_IOCB_RSP_3032_ICE
- IB_IP_IOCB_RSP_3032_IPE
- IB_IP_IOCB_RSP_3032_NUC
- IB_IP_IOCB_RSP_3032_O
- IB_IP_IOCB_RSP_3032_R
- IB_IP_IOCB_RSP_3032_TCP
- IB_IP_IOCB_RSP_3032_UDP
- IB_IP_IOCB_RSP_3032_V
- IB_IP_IOCB_RSP_B
- IB_IP_IOCB_RSP_H0
- IB_IP_IOCB_RSP_H1
- IB_IP_IOCB_RSP_M
- IB_IP_IOCB_RSP_MA
- IB_IP_IOCB_RSP_R
- IB_IP_IOCB_RSP_S
- IB_ISSM_MINOR_BASE
- IB_LID_PERMISSIVE
- IB_LINKCMD_ACTIVE
- IB_LINKCMD_ARMED
- IB_LINKCMD_DOWN
- IB_LINKINITCMD_DISABLE
- IB_LINKINITCMD_NOP
- IB_LINKINITCMD_POLL
- IB_LINKINITCMD_SLEEP
- IB_LINK_LAYER_ETHERNET
- IB_LINK_LAYER_INFINIBAND
- IB_LINK_LAYER_UNSPECIFIED
- IB_LNH_IBA_GLOBAL
- IB_LNH_IBA_LOCAL
- IB_LNH_IP
- IB_LNH_MASK
- IB_LNH_RAW
- IB_LRH_BYTES
- IB_LVER_MASK
- IB_LVER_SHIFT
- IB_MAC_CSUM_ERR_MASK
- IB_MAC_IOCB_RSP_B
- IB_MAC_IOCB_RSP_C
- IB_MAC_IOCB_RSP_COS_SHIFT
- IB_MAC_IOCB_RSP_DL
- IB_MAC_IOCB_RSP_DS
- IB_MAC_IOCB_RSP_ERR_CODE_ERR
- IB_MAC_IOCB_RSP_ERR_CRC
- IB_MAC_IOCB_RSP_ERR_FRAME_LEN
- IB_MAC_IOCB_RSP_ERR_MASK
- IB_MAC_IOCB_RSP_ERR_OVERSIZE
- IB_MAC_IOCB_RSP_ERR_PREAMBLE
- IB_MAC_IOCB_RSP_ERR_UNDERSIZE
- IB_MAC_IOCB_RSP_FO
- IB_MAC_IOCB_RSP_H0
- IB_MAC_IOCB_RSP_H1
- IB_MAC_IOCB_RSP_HL
- IB_MAC_IOCB_RSP_HS
- IB_MAC_IOCB_RSP_HV
- IB_MAC_IOCB_RSP_I
- IB_MAC_IOCB_RSP_IE
- IB_MAC_IOCB_RSP_IH
- IB_MAC_IOCB_RSP_M
- IB_MAC_IOCB_RSP_MA
- IB_MAC_IOCB_RSP_M_HASH
- IB_MAC_IOCB_RSP_M_IPV4
- IB_MAC_IOCB_RSP_M_IPV6
- IB_MAC_IOCB_RSP_M_MASK
- IB_MAC_IOCB_RSP_M_NONE
- IB_MAC_IOCB_RSP_M_PROM
- IB_MAC_IOCB_RSP_M_REG
- IB_MAC_IOCB_RSP_M_TCP_V4
- IB_MAC_IOCB_RSP_M_TCP_V6
- IB_MAC_IOCB_RSP_NU
- IB_MAC_IOCB_RSP_OI
- IB_MAC_IOCB_RSP_P
- IB_MAC_IOCB_RSP_RSS_MASK
- IB_MAC_IOCB_RSP_S
- IB_MAC_IOCB_RSP_T
- IB_MAC_IOCB_RSP_TE
- IB_MAC_IOCB_RSP_U
- IB_MAC_IOCB_RSP_V
- IB_MAC_IOCB_RSP_V4
- IB_MAC_IOCB_RSP_V6
- IB_MAC_IOCB_RSP_VLAN_MASK
- IB_MAD_H
- IB_MAD_IGNORE_ALL
- IB_MAD_IGNORE_BKEY
- IB_MAD_IGNORE_MKEY
- IB_MAD_QPS_CORE
- IB_MAD_QP_MAX_SIZE
- IB_MAD_QP_MIN_SIZE
- IB_MAD_QP_RECV_SIZE
- IB_MAD_QP_SEND_SIZE
- IB_MAD_RECV_REQ_MAX_SG
- IB_MAD_RESULT_CONSUMED
- IB_MAD_RESULT_FAILURE
- IB_MAD_RESULT_REPLY
- IB_MAD_RESULT_SUCCESS
- IB_MAD_SEND_Q_PSN
- IB_MAD_SEND_REQ_MAX_SG
- IB_MAD_SNOOP_RECVS
- IB_MAD_SNOOP_SEND_COMPLETIONS
- IB_MAD_USER_RMPP
- IB_MANDATORY_FUNC
- IB_MEMMAP
- IB_MGMT_BASE_VERSION
- IB_MGMT_CLASSPORTINFO_ATTR_ID
- IB_MGMT_CLASS_BIS
- IB_MGMT_CLASS_BM
- IB_MGMT_CLASS_BOOT_MGMT
- IB_MGMT_CLASS_CM
- IB_MGMT_CLASS_CONG_MGMT
- IB_MGMT_CLASS_DEVICE_ADM
- IB_MGMT_CLASS_DEVICE_MGMT
- IB_MGMT_CLASS_PERF_MGMT
- IB_MGMT_CLASS_SNMP
- IB_MGMT_CLASS_SUBN_ADM
- IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE
- IB_MGMT_CLASS_SUBN_LID_ROUTED
- IB_MGMT_CLASS_VENDOR_RANGE2_END
- IB_MGMT_CLASS_VENDOR_RANGE2_START
- IB_MGMT_DEVICE_DATA
- IB_MGMT_DEVICE_HDR
- IB_MGMT_MAD_DATA
- IB_MGMT_MAD_HDR
- IB_MGMT_MAD_SIZE
- IB_MGMT_MAD_STATUS_BAD_VERSION
- IB_MGMT_MAD_STATUS_BUSY
- IB_MGMT_MAD_STATUS_INVALID_ATTRIB_VALUE
- IB_MGMT_MAD_STATUS_REDIRECT_REQD
- IB_MGMT_MAD_STATUS_SUCCESS
- IB_MGMT_MAD_STATUS_UNSUPPORTED_METHOD
- IB_MGMT_MAD_STATUS_UNSUPPORTED_METHOD_ATTRIB
- IB_MGMT_MAX_METHODS
- IB_MGMT_METHOD_GET
- IB_MGMT_METHOD_GET_RESP
- IB_MGMT_METHOD_REPORT
- IB_MGMT_METHOD_REPORT_RESP
- IB_MGMT_METHOD_RESP
- IB_MGMT_METHOD_SEND
- IB_MGMT_METHOD_SET
- IB_MGMT_METHOD_TRAP
- IB_MGMT_METHOD_TRAP_REPRESS
- IB_MGMT_RMPP_DATA
- IB_MGMT_RMPP_FLAG_ACTIVE
- IB_MGMT_RMPP_FLAG_FIRST
- IB_MGMT_RMPP_FLAG_LAST
- IB_MGMT_RMPP_HDR
- IB_MGMT_RMPP_NO_RESPTIME
- IB_MGMT_RMPP_STATUS_ABORT_MAX
- IB_MGMT_RMPP_STATUS_ABORT_MIN
- IB_MGMT_RMPP_STATUS_BADT
- IB_MGMT_RMPP_STATUS_BAD_LEN
- IB_MGMT_RMPP_STATUS_BAD_SEG
- IB_MGMT_RMPP_STATUS_BAD_STATUS
- IB_MGMT_RMPP_STATUS_RESX
- IB_MGMT_RMPP_STATUS_S2B
- IB_MGMT_RMPP_STATUS_SUCCESS
- IB_MGMT_RMPP_STATUS_T2L
- IB_MGMT_RMPP_STATUS_TMR
- IB_MGMT_RMPP_STATUS_UNSPEC
- IB_MGMT_RMPP_STATUS_UNV
- IB_MGMT_RMPP_STATUS_W2S
- IB_MGMT_RMPP_TYPE_ABORT
- IB_MGMT_RMPP_TYPE_ACK
- IB_MGMT_RMPP_TYPE_DATA
- IB_MGMT_RMPP_TYPE_STOP
- IB_MGMT_RMPP_VERSION
- IB_MGMT_SA_DATA
- IB_MGMT_SA_HDR
- IB_MGMT_VENDOR_DATA
- IB_MGMT_VENDOR_HDR
- IB_MIG_ARMED
- IB_MIG_MIGRATED
- IB_MIG_REARM
- IB_MPREG5
- IB_MPREG6
- IB_MR_CHECK_SIG_STATUS
- IB_MR_REREG_ACCESS
- IB_MR_REREG_PD
- IB_MR_REREG_SUPPORTED
- IB_MR_REREG_TRANS
- IB_MR_TYPE_DM
- IB_MR_TYPE_DMA
- IB_MR_TYPE_INTEGRITY
- IB_MR_TYPE_MEM_REG
- IB_MR_TYPE_SG_GAPS
- IB_MR_TYPE_USER
- IB_MSN_MASK
- IB_MTU_1024
- IB_MTU_2048
- IB_MTU_256
- IB_MTU_4096
- IB_MTU_512
- IB_MULTICAST_LID_BASE
- IB_MULTICAST_QPN
- IB_MW_TYPE_1
- IB_MW_TYPE_2
- IB_NAK_INVALID_RD_REQUEST
- IB_NAK_INVALID_REQUEST
- IB_NAK_PSN_ERROR
- IB_NAK_REMOTE_ACCESS_ERROR
- IB_NAK_REMOTE_OPERATIONAL_ERROR
- IB_NOTICE_PROD_CA
- IB_NOTICE_PROD_CLASS_MGR
- IB_NOTICE_PROD_ROUTER
- IB_NOTICE_PROD_SWITCH
- IB_NOTICE_TRAP_BAD_MKEY
- IB_NOTICE_TRAP_BAD_PKEY
- IB_NOTICE_TRAP_BAD_QKEY
- IB_NOTICE_TRAP_CAP_MASK_CHG
- IB_NOTICE_TRAP_DR_NOTICE
- IB_NOTICE_TRAP_DR_TRUNC
- IB_NOTICE_TRAP_EBO_THRESH
- IB_NOTICE_TRAP_FLOW_UPDATE
- IB_NOTICE_TRAP_LLI_THRESH
- IB_NOTICE_TRAP_LSE_CHG
- IB_NOTICE_TRAP_LWE_CHG
- IB_NOTICE_TRAP_NODE_DESC_CHG
- IB_NOTICE_TRAP_SYS_GUID_CHG
- IB_NOTICE_TYPE_FATAL
- IB_NOTICE_TYPE_INFO
- IB_NOTICE_TYPE_SECURITY
- IB_NOTICE_TYPE_SM
- IB_NOTICE_TYPE_URGENT
- IB_OB_READ_TIMES
- IB_ODP_SUPPORT
- IB_ODP_SUPPORT_ATOMIC
- IB_ODP_SUPPORT_IMPLICIT
- IB_ODP_SUPPORT_READ
- IB_ODP_SUPPORT_RECV
- IB_ODP_SUPPORT_SEND
- IB_ODP_SUPPORT_SRQ_RECV
- IB_ODP_SUPPORT_WRITE
- IB_OPCODE
- IB_OPCODE_ACK
- IB_OPCODE_ACKNOWLEDGE
- IB_OPCODE_ATOMIC_ACKNOWLEDGE
- IB_OPCODE_CNP
- IB_OPCODE_COMPARE_SWAP
- IB_OPCODE_FETCH_ADD
- IB_OPCODE_MSP
- IB_OPCODE_RC
- IB_OPCODE_RD
- IB_OPCODE_RDMA_READ_REQUEST
- IB_OPCODE_RDMA_READ_RESPONSE_FIRST
- IB_OPCODE_RDMA_READ_RESPONSE_LAST
- IB_OPCODE_RDMA_READ_RESPONSE_MIDDLE
- IB_OPCODE_RDMA_READ_RESPONSE_ONLY
- IB_OPCODE_RDMA_WRITE_FIRST
- IB_OPCODE_RDMA_WRITE_LAST
- IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE
- IB_OPCODE_RDMA_WRITE_MIDDLE
- IB_OPCODE_RDMA_WRITE_ONLY
- IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE
- IB_OPCODE_READ_REQ
- IB_OPCODE_READ_RESP
- IB_OPCODE_RESYNC
- IB_OPCODE_SEND_FIRST
- IB_OPCODE_SEND_LAST
- IB_OPCODE_SEND_LAST_WITH_IMMEDIATE
- IB_OPCODE_SEND_LAST_WITH_INVALIDATE
- IB_OPCODE_SEND_MIDDLE
- IB_OPCODE_SEND_ONLY
- IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE
- IB_OPCODE_SEND_ONLY_WITH_INVALIDATE
- IB_OPCODE_TID_RDMA
- IB_OPCODE_UC
- IB_OPCODE_UD
- IB_OPCODE_WRITE_DATA
- IB_OPCODE_WRITE_DATA_LAST
- IB_OPCODE_WRITE_REQ
- IB_OPCODE_WRITE_RESP
- IB_OPENIB_OUI
- IB_PACKET_TYPE
- IB_PACK_H
- IB_PATH_ALTERNATE
- IB_PATH_BIDIRECTIONAL
- IB_PATH_GMP
- IB_PATH_INBOUND
- IB_PATH_INBOUND_REVERSE
- IB_PATH_OUTBOUND
- IB_PATH_PRIMARY
- IB_PD_UNSAFE_GLOBAL_RKEY
- IB_PGUDP
- IB_PHYSPORTSTATE_CFG_DEBOUNCE
- IB_PHYSPORTSTATE_CFG_ENH
- IB_PHYSPORTSTATE_CFG_IDLE
- IB_PHYSPORTSTATE_CFG_TRAIN
- IB_PHYSPORTSTATE_CFG_WAIT_ENH
- IB_PHYSPORTSTATE_DISABLED
- IB_PHYSPORTSTATE_LINKUP
- IB_PHYSPORTSTATE_LINK_ERR_RECOVER
- IB_PHYSPORTSTATE_POLL
- IB_PHYSPORTSTATE_RECOVERY_IDLE
- IB_PHYSPORTSTATE_RECOVERY_RETRAIN
- IB_PHYSPORTSTATE_RECOVERY_WAITRMT
- IB_PHYSPORTSTATE_SLEEP
- IB_PIPCI_BAR
- IB_PIPCI_BAR_OFFSET
- IB_PMA_CLASS_CAP_ALLPORTSELECT
- IB_PMA_CLASS_CAP_EXT_WIDTH
- IB_PMA_CLASS_CAP_EXT_WIDTH_NOIETF
- IB_PMA_CLASS_CAP_XMIT_WAIT
- IB_PMA_CLASS_PORT_INFO
- IB_PMA_CONG_HW_CONTROL_SAMPLE
- IB_PMA_CONG_HW_CONTROL_TIMER
- IB_PMA_H
- IB_PMA_PORT_COUNTERS
- IB_PMA_PORT_COUNTERS_CONG
- IB_PMA_PORT_COUNTERS_EXT
- IB_PMA_PORT_RCV_DATA
- IB_PMA_PORT_RCV_PKTS
- IB_PMA_PORT_SAMPLES_CONTROL
- IB_PMA_PORT_SAMPLES_RESULT
- IB_PMA_PORT_SAMPLES_RESULT_EXT
- IB_PMA_PORT_XMIT_DATA
- IB_PMA_PORT_XMIT_PKTS
- IB_PMA_PORT_XMIT_WAIT
- IB_PMA_SAMPLE_STATUS_DONE
- IB_PMA_SAMPLE_STATUS_RUNNING
- IB_PMA_SAMPLE_STATUS_STARTED
- IB_PMA_SELX_PORT_MULTI_RCV_PACKETS
- IB_PMA_SELX_PORT_MULTI_XMIT_PACKETS
- IB_PMA_SELX_PORT_RCV_DATA
- IB_PMA_SELX_PORT_RCV_PACKETS
- IB_PMA_SELX_PORT_UNI_RCV_PACKETS
- IB_PMA_SELX_PORT_UNI_XMIT_PACKETS
- IB_PMA_SELX_PORT_XMIT_DATA
- IB_PMA_SELX_PORT_XMIT_PACKETS
- IB_PMA_SEL_CONG_ALL
- IB_PMA_SEL_CONG_PORT_DATA
- IB_PMA_SEL_CONG_ROUTING
- IB_PMA_SEL_CONG_XMIT
- IB_PMA_SEL_EXCESSIVE_BUFFER_OVERRUNS
- IB_PMA_SEL_LINK_DOWNED
- IB_PMA_SEL_LINK_ERROR_RECOVERY
- IB_PMA_SEL_LOCAL_LINK_INTEGRITY_ERRORS
- IB_PMA_SEL_PORT_RCV_DATA
- IB_PMA_SEL_PORT_RCV_ERRORS
- IB_PMA_SEL_PORT_RCV_PACKETS
- IB_PMA_SEL_PORT_RCV_REMPHYS_ERRORS
- IB_PMA_SEL_PORT_VL15_DROPPED
- IB_PMA_SEL_PORT_XMIT_DATA
- IB_PMA_SEL_PORT_XMIT_DISCARDS
- IB_PMA_SEL_PORT_XMIT_PACKETS
- IB_PMA_SEL_SYMBOL_ERROR
- IB_POLL_BATCH
- IB_POLL_BATCH_DIRECT
- IB_POLL_BUDGET_IRQ
- IB_POLL_BUDGET_WORKQUEUE
- IB_POLL_DIRECT
- IB_POLL_FLAGS
- IB_POLL_SOFTIRQ
- IB_POLL_UNBOUND_WORKQUEUE
- IB_POLL_WORKQUEUE
- IB_PORTPHYSSTATE_DISABLED
- IB_PORTPHYSSTATE_LINKUP
- IB_PORTPHYSSTATE_LINK_ERROR_RECOVERY
- IB_PORTPHYSSTATE_NOP
- IB_PORTPHYSSTATE_PHY_TEST
- IB_PORTPHYSSTATE_POLLING
- IB_PORTPHYSSTATE_TRAINING
- IB_PORT_ACTIVE
- IB_PORT_ACTIVE_DEFER
- IB_PORT_ARMED
- IB_PORT_AUTO_MIGR_SUP
- IB_PORT_BOOT_MGMT_SUP
- IB_PORT_CAP_MASK2_SUP
- IB_PORT_CAP_MASK_NOTICE_SUP
- IB_PORT_CLIENT_REG_SUP
- IB_PORT_CM_SUP
- IB_PORT_DEVICE_MGMT_SUP
- IB_PORT_DOWN
- IB_PORT_DR_NOTICE_SUP
- IB_PORT_EXTENDED_SPEEDS_SUP
- IB_PORT_EX_PORT_INFO_EX_SUP
- IB_PORT_HIERARCHY_INFO_SUP
- IB_PORT_INIT
- IB_PORT_INIT_TYPE
- IB_PORT_LED_INFO_SUP
- IB_PORT_LINK_LATENCY_SUP
- IB_PORT_LINK_SPEED_HDR_SUP
- IB_PORT_LINK_SPEED_WIDTH_TABLE_SUP
- IB_PORT_LINK_WIDTH_2X_SUP
- IB_PORT_MCAST_FDB_TOP_SUP
- IB_PORT_MCAST_PKEY_TRAP_SUPPRESSION_SUP
- IB_PORT_MKEY_NVRAM
- IB_PORT_NOP
- IB_PORT_NOTICE_SUP
- IB_PORT_OPA_MASK_CHG
- IB_PORT_OPT_IPD_SUP
- IB_PORT_OTHER_LOCAL_CHANGES_SUP
- IB_PORT_PHYS_STATE_DISABLED
- IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY
- IB_PORT_PHYS_STATE_LINK_UP
- IB_PORT_PHYS_STATE_PHY_TEST
- IB_PORT_PHYS_STATE_POLLING
- IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING
- IB_PORT_PHYS_STATE_SLEEP
- IB_PORT_PKEY_LISTED
- IB_PORT_PKEY_NOT_VALID
- IB_PORT_PKEY_NVRAM
- IB_PORT_PKEY_SW_EXT_PORT_TRAP_SUP
- IB_PORT_PKEY_VALID
- IB_PORT_REINIT_SUP
- IB_PORT_RESET_QKEY_CNTR
- IB_PORT_SET_NODE_DESC_SUP
- IB_PORT_SHUTDOWN
- IB_PORT_SL_MAP_SUP
- IB_PORT_SM
- IB_PORT_SM_DISABLED
- IB_PORT_SNMP_TUNNEL_SUP
- IB_PORT_SWITCH_PORT_STATE_TABLE_SUP
- IB_PORT_SYS_IMAGE_GUID_SUP
- IB_PORT_TRAP_SUP
- IB_PORT_VENDOR_CLASS_SUP
- IB_PORT_VENDOR_SPECIFIC_MADS_TABLE_SUP
- IB_PORT_VIRT_SUP
- IB_PROPERITY_OFFSET
- IB_PROT_T10DIF_TYPE_1
- IB_PROT_T10DIF_TYPE_2
- IB_PROT_T10DIF_TYPE_3
- IB_QP0
- IB_QP1
- IB_QP1_QKEY
- IB_QPN_MASK
- IB_QPS_ERR
- IB_QPS_INIT
- IB_QPS_RESET
- IB_QPS_RTR
- IB_QPS_RTS
- IB_QPS_SQD
- IB_QPS_SQE
- IB_QPT_DRIVER
- IB_QPT_GSI
- IB_QPT_MAX
- IB_QPT_RAW_ETHERTYPE
- IB_QPT_RAW_IPV6
- IB_QPT_RAW_PACKET
- IB_QPT_RC
- IB_QPT_RESERVED1
- IB_QPT_RESERVED10
- IB_QPT_RESERVED2
- IB_QPT_RESERVED3
- IB_QPT_RESERVED4
- IB_QPT_RESERVED5
- IB_QPT_RESERVED6
- IB_QPT_RESERVED7
- IB_QPT_RESERVED8
- IB_QPT_RESERVED9
- IB_QPT_SMI
- IB_QPT_UC
- IB_QPT_UD
- IB_QPT_XRC_INI
- IB_QPT_XRC_TGT
- IB_QP_ACCESS_FLAGS
- IB_QP_ALT_PATH
- IB_QP_AV
- IB_QP_CAP
- IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
- IB_QP_CREATE_CROSS_CHANNEL
- IB_QP_CREATE_CVLAN_STRIPPING
- IB_QP_CREATE_INTEGRITY_EN
- IB_QP_CREATE_IPOIB_UD_LSO
- IB_QP_CREATE_MANAGED_RECV
- IB_QP_CREATE_MANAGED_SEND
- IB_QP_CREATE_NETIF_QP
- IB_QP_CREATE_PCI_WRITE_END_PADDING
- IB_QP_CREATE_RESERVED_END
- IB_QP_CREATE_RESERVED_START
- IB_QP_CREATE_SCATTER_FCS
- IB_QP_CREATE_SOURCE_QPN
- IB_QP_CUR_STATE
- IB_QP_DEST_QPN
- IB_QP_EN_SQD_ASYNC_NOTIFY
- IB_QP_MAX_DEST_RD_ATOMIC
- IB_QP_MAX_QP_RD_ATOMIC
- IB_QP_MIN_RNR_TIMER
- IB_QP_PATH_MIG_STATE
- IB_QP_PATH_MTU
- IB_QP_PKEY_INDEX
- IB_QP_PORT
- IB_QP_QKEY
- IB_QP_RATE_LIMIT
- IB_QP_RESERVED1
- IB_QP_RESERVED2
- IB_QP_RESERVED3
- IB_QP_RESERVED4
- IB_QP_RETRY_CNT
- IB_QP_RNR_RETRY
- IB_QP_RQ_PSN
- IB_QP_SET_QKEY
- IB_QP_SQ_PSN
- IB_QP_STATE
- IB_QP_TIMEOUT
- IB_RANK_CFG_A
- IB_RATE_100_GBPS
- IB_RATE_10_GBPS
- IB_RATE_112_GBPS
- IB_RATE_120_GBPS
- IB_RATE_14_GBPS
- IB_RATE_168_GBPS
- IB_RATE_200_GBPS
- IB_RATE_20_GBPS
- IB_RATE_25_GBPS
- IB_RATE_28_GBPS
- IB_RATE_2_5_GBPS
- IB_RATE_300_GBPS
- IB_RATE_30_GBPS
- IB_RATE_400_GBPS
- IB_RATE_40_GBPS
- IB_RATE_50_GBPS
- IB_RATE_56_GBPS
- IB_RATE_5_GBPS
- IB_RATE_600_GBPS
- IB_RATE_60_GBPS
- IB_RATE_80_GBPS
- IB_RATE_PORT_CURRENT
- IB_RAW_PACKET_CAP_CVLAN_STRIPPING
- IB_RAW_PACKET_CAP_DELAY_DROP
- IB_RAW_PACKET_CAP_IP_CSUM
- IB_RAW_PACKET_CAP_SCATTER_FCS
- IB_RESERVED_OFFSET
- IB_RMPP_RESULT_CONSUMED
- IB_RMPP_RESULT_INTERNAL
- IB_RMPP_RESULT_PROCESSED
- IB_RMPP_RESULT_UNHANDLED
- IB_RNR_NAK
- IB_RNR_TIMER_000_01
- IB_RNR_TIMER_000_02
- IB_RNR_TIMER_000_03
- IB_RNR_TIMER_000_04
- IB_RNR_TIMER_000_06
- IB_RNR_TIMER_000_08
- IB_RNR_TIMER_000_12
- IB_RNR_TIMER_000_16
- IB_RNR_TIMER_000_24
- IB_RNR_TIMER_000_32
- IB_RNR_TIMER_000_48
- IB_RNR_TIMER_000_64
- IB_RNR_TIMER_000_96
- IB_RNR_TIMER_001_28
- IB_RNR_TIMER_001_92
- IB_RNR_TIMER_002_56
- IB_RNR_TIMER_003_84
- IB_RNR_TIMER_005_12
- IB_RNR_TIMER_007_68
- IB_RNR_TIMER_010_24
- IB_RNR_TIMER_015_36
- IB_RNR_TIMER_020_48
- IB_RNR_TIMER_030_72
- IB_RNR_TIMER_040_96
- IB_RNR_TIMER_061_44
- IB_RNR_TIMER_081_92
- IB_RNR_TIMER_122_88
- IB_RNR_TIMER_163_84
- IB_RNR_TIMER_245_76
- IB_RNR_TIMER_327_68
- IB_RNR_TIMER_491_52
- IB_RNR_TIMER_655_36
- IB_ROOT_PORT_REG_SIZE_SHIFT
- IB_SA_ATTR_CLASS_PORTINFO
- IB_SA_ATTR_GUID_INFO_REC
- IB_SA_ATTR_INFORM_INFO
- IB_SA_ATTR_INFORM_INFO_REC
- IB_SA_ATTR_LINEAR_FDB_REC
- IB_SA_ATTR_LINK_REC
- IB_SA_ATTR_MCAST_FDB_REC
- IB_SA_ATTR_MC_MEMBER_REC
- IB_SA_ATTR_MULTI_PATH_REC
- IB_SA_ATTR_NODE_REC
- IB_SA_ATTR_NOTICE
- IB_SA_ATTR_PARTITION_REC
- IB_SA_ATTR_PATH_REC
- IB_SA_ATTR_PORT_INFO_REC
- IB_SA_ATTR_RANDOM_FDB_REC
- IB_SA_ATTR_SERVICE_ASSOC_REC
- IB_SA_ATTR_SERVICE_REC
- IB_SA_ATTR_SL2VL_REC
- IB_SA_ATTR_SM_INFO_REC
- IB_SA_ATTR_SWITCH_REC
- IB_SA_ATTR_TRACE_REC
- IB_SA_ATTR_VL_ARB_REC
- IB_SA_BEST
- IB_SA_CANCEL
- IB_SA_CAP_MASK2_SENDONLY_FULL_MEM_SUPPORT
- IB_SA_CLASS_VERSION
- IB_SA_COMP_MASK
- IB_SA_CPI_MAX_RETRY_CNT
- IB_SA_CPI_RETRY_WAIT
- IB_SA_ENABLE_LOCAL_SERVICE
- IB_SA_EQ
- IB_SA_GT
- IB_SA_GUIDINFO_REC_BLOCK_NUM
- IB_SA_GUIDINFO_REC_GID0
- IB_SA_GUIDINFO_REC_GID1
- IB_SA_GUIDINFO_REC_GID2
- IB_SA_GUIDINFO_REC_GID3
- IB_SA_GUIDINFO_REC_GID4
- IB_SA_GUIDINFO_REC_GID5
- IB_SA_GUIDINFO_REC_GID6
- IB_SA_GUIDINFO_REC_GID7
- IB_SA_GUIDINFO_REC_LID
- IB_SA_GUIDINFO_REC_RES1
- IB_SA_GUIDINFO_REC_RES2
- IB_SA_H
- IB_SA_LOCAL_SVC_TIMEOUT_DEFAULT
- IB_SA_LOCAL_SVC_TIMEOUT_MAX
- IB_SA_LOCAL_SVC_TIMEOUT_MIN
- IB_SA_LT
- IB_SA_MCMEMBER_REC_FLOW_LABEL
- IB_SA_MCMEMBER_REC_HOP_LIMIT
- IB_SA_MCMEMBER_REC_JOIN_STATE
- IB_SA_MCMEMBER_REC_MGID
- IB_SA_MCMEMBER_REC_MLID
- IB_SA_MCMEMBER_REC_MTU
- IB_SA_MCMEMBER_REC_MTU_SELECTOR
- IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME
- IB_SA_MCMEMBER_REC_PACKET_LIFE_TIME_SELECTOR
- IB_SA_MCMEMBER_REC_PKEY
- IB_SA_MCMEMBER_REC_PORT_GID
- IB_SA_MCMEMBER_REC_PROXY_JOIN
- IB_SA_MCMEMBER_REC_QKEY
- IB_SA_MCMEMBER_REC_RATE
- IB_SA_MCMEMBER_REC_RATE_SELECTOR
- IB_SA_MCMEMBER_REC_SCOPE
- IB_SA_MCMEMBER_REC_SL
- IB_SA_MCMEMBER_REC_TRAFFIC_CLASS
- IB_SA_METHOD_DELETE
- IB_SA_METHOD_DELETE_RESP
- IB_SA_METHOD_GET_MULTI
- IB_SA_METHOD_GET_MULTI_RESP
- IB_SA_METHOD_GET_TABLE
- IB_SA_METHOD_GET_TABLE_RESP
- IB_SA_METHOD_GET_TRACE_TBL
- IB_SA_PATH_REC_DGID
- IB_SA_PATH_REC_DLID
- IB_SA_PATH_REC_FLOW_LABEL
- IB_SA_PATH_REC_HOP_LIMIT
- IB_SA_PATH_REC_MTU
- IB_SA_PATH_REC_MTU_SELECTOR
- IB_SA_PATH_REC_NUMB_PATH
- IB_SA_PATH_REC_PACKET_LIFE_TIME
- IB_SA_PATH_REC_PACKET_LIFE_TIME_SELECTOR
- IB_SA_PATH_REC_PKEY
- IB_SA_PATH_REC_PREFERENCE
- IB_SA_PATH_REC_QOS_CLASS
- IB_SA_PATH_REC_RATE
- IB_SA_PATH_REC_RATE_SELECTOR
- IB_SA_PATH_REC_RAW_TRAFFIC
- IB_SA_PATH_REC_REVERSIBLE
- IB_SA_PATH_REC_SERVICE_ID
- IB_SA_PATH_REC_SGID
- IB_SA_PATH_REC_SL
- IB_SA_PATH_REC_SLID
- IB_SA_PATH_REC_TRAFFIC_CLASS
- IB_SA_QUERY_OPA
- IB_SA_SERVICE_REC_SERVICE_DATA16_0
- IB_SA_SERVICE_REC_SERVICE_DATA16_1
- IB_SA_SERVICE_REC_SERVICE_DATA16_2
- IB_SA_SERVICE_REC_SERVICE_DATA16_3
- IB_SA_SERVICE_REC_SERVICE_DATA16_4
- IB_SA_SERVICE_REC_SERVICE_DATA16_5
- IB_SA_SERVICE_REC_SERVICE_DATA16_6
- IB_SA_SERVICE_REC_SERVICE_DATA16_7
- IB_SA_SERVICE_REC_SERVICE_DATA32_0
- IB_SA_SERVICE_REC_SERVICE_DATA32_1
- IB_SA_SERVICE_REC_SERVICE_DATA32_2
- IB_SA_SERVICE_REC_SERVICE_DATA32_3
- IB_SA_SERVICE_REC_SERVICE_DATA64_0
- IB_SA_SERVICE_REC_SERVICE_DATA64_1
- IB_SA_SERVICE_REC_SERVICE_DATA8_0
- IB_SA_SERVICE_REC_SERVICE_DATA8_1
- IB_SA_SERVICE_REC_SERVICE_DATA8_10
- IB_SA_SERVICE_REC_SERVICE_DATA8_11
- IB_SA_SERVICE_REC_SERVICE_DATA8_12
- IB_SA_SERVICE_REC_SERVICE_DATA8_13
- IB_SA_SERVICE_REC_SERVICE_DATA8_14
- IB_SA_SERVICE_REC_SERVICE_DATA8_15
- IB_SA_SERVICE_REC_SERVICE_DATA8_2
- IB_SA_SERVICE_REC_SERVICE_DATA8_3
- IB_SA_SERVICE_REC_SERVICE_DATA8_4
- IB_SA_SERVICE_REC_SERVICE_DATA8_5
- IB_SA_SERVICE_REC_SERVICE_DATA8_6
- IB_SA_SERVICE_REC_SERVICE_DATA8_7
- IB_SA_SERVICE_REC_SERVICE_DATA8_8
- IB_SA_SERVICE_REC_SERVICE_DATA8_9
- IB_SA_SERVICE_REC_SERVICE_GID
- IB_SA_SERVICE_REC_SERVICE_ID
- IB_SA_SERVICE_REC_SERVICE_KEY
- IB_SA_SERVICE_REC_SERVICE_LEASE
- IB_SA_SERVICE_REC_SERVICE_NAME
- IB_SA_SERVICE_REC_SERVICE_PKEY
- IB_SA_WELL_KNOWN_GUID
- IB_SC5_MASK
- IB_SC_MASK
- IB_SC_SHIFT
- IB_SDP_SERVICE_ID
- IB_SDP_SERVICE_ID_MASK
- IB_SEND_FENCE
- IB_SEND_INLINE
- IB_SEND_IP_CSUM
- IB_SEND_RESERVED_END
- IB_SEND_RESERVED_START
- IB_SEND_SIGNALED
- IB_SEND_SOLICITED
- IB_SEQ_NAK
- IB_SERDES_TRIM_DONE
- IB_SERVICE_ID_AGN_MASK
- IB_SET_POST_CREDITS
- IB_SET_SEND_CREDITS
- IB_SIDR_NO_QP
- IB_SIDR_REDIRECT
- IB_SIDR_REJECT
- IB_SIDR_SUCCESS
- IB_SIDR_UNSUPPORTED
- IB_SIDR_UNSUPPORTED_VERSION
- IB_SIGNAL_ALL_WR
- IB_SIGNAL_REQ_WR
- IB_SIG_BAD_APPTAG
- IB_SIG_BAD_GUARD
- IB_SIG_BAD_REFTAG
- IB_SIG_CHECK_APPTAG
- IB_SIG_CHECK_GUARD
- IB_SIG_CHECK_REFTAG
- IB_SIG_TYPE_NONE
- IB_SIG_TYPE_T10_DIF
- IB_SL_MASK
- IB_SL_SHIFT
- IB_SMI_DISCARD
- IB_SMI_FORWARD
- IB_SMI_H
- IB_SMI_HANDLE
- IB_SMI_LOCAL
- IB_SMI_SEND
- IB_SMP_ATTR_GUID_INFO
- IB_SMP_ATTR_LED_INFO
- IB_SMP_ATTR_LINEAR_FORWARD_TABLE
- IB_SMP_ATTR_MCAST_FORWARD_TABLE
- IB_SMP_ATTR_NODE_DESC
- IB_SMP_ATTR_NODE_INFO
- IB_SMP_ATTR_NOTICE
- IB_SMP_ATTR_PKEY_TABLE
- IB_SMP_ATTR_PORT_INFO
- IB_SMP_ATTR_RANDOM_FORWARD_TABLE
- IB_SMP_ATTR_SL_TO_VL_TABLE
- IB_SMP_ATTR_SM_INFO
- IB_SMP_ATTR_SWITCH_INFO
- IB_SMP_ATTR_VENDOR_DIAG
- IB_SMP_ATTR_VENDOR_MASK
- IB_SMP_ATTR_VL_ARB_TABLE
- IB_SMP_DATA_SIZE
- IB_SMP_DIRECTION
- IB_SMP_INVALID_FIELD
- IB_SMP_MAX_PATH_HOPS
- IB_SMP_UNSUP_METHOD
- IB_SMP_UNSUP_METH_ATTR
- IB_SMP_UNSUP_VERSION
- IB_SPEED_DDR
- IB_SPEED_EDR
- IB_SPEED_FDR
- IB_SPEED_FDR10
- IB_SPEED_HDR
- IB_SPEED_QDR
- IB_SPEED_SDR
- IB_SRPT_H
- IB_SRP_H
- IB_SRQT_BASIC
- IB_SRQT_TM
- IB_SRQT_XRC
- IB_SRQ_INIT_MASK
- IB_SRQ_LIMIT
- IB_SRQ_MAX_WR
- IB_STATUS_BITS
- IB_T10DIF_CRC
- IB_T10DIF_CSUM
- IB_TM_CAP_RNDV_RC
- IB_UDP_BYTES
- IB_UMAD_MAJOR
- IB_UMAD_MAX_AGENTS
- IB_UMAD_MAX_PORTS
- IB_UMAD_MINOR_BASE
- IB_UMAD_NUM_DYNAMIC_MINOR
- IB_UMAD_NUM_FIXED_MINOR
- IB_UMEM_H
- IB_UMEM_ODP_H
- IB_USER_IOCTL_CMDS_H
- IB_USER_IOCTL_VERBS_H
- IB_USER_LAST_QP_ATTR_MASK
- IB_USER_LEGACY_LAST_QP_ATTR_MASK
- IB_USER_MAD_ABI_VERSION
- IB_USER_MAD_ENABLE_PKEY
- IB_USER_MAD_H
- IB_USER_MAD_LONGS_PER_METHOD_MASK
- IB_USER_MAD_REGISTER_AGENT
- IB_USER_MAD_REGISTER_AGENT2
- IB_USER_MAD_REG_FLAGS_CAP
- IB_USER_MAD_UNREGISTER_AGENT
- IB_USER_MAD_USER_RMPP
- IB_USER_MARSHALL_H
- IB_USER_SA_H
- IB_USER_VERBS_ABI_VERSION
- IB_USER_VERBS_CMD_ALLOC_MW
- IB_USER_VERBS_CMD_ALLOC_PD
- IB_USER_VERBS_CMD_ATTACH_MCAST
- IB_USER_VERBS_CMD_BIND_MW
- IB_USER_VERBS_CMD_CLOSE_XRCD
- IB_USER_VERBS_CMD_COMMAND_MASK
- IB_USER_VERBS_CMD_CREATE_AH
- IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
- IB_USER_VERBS_CMD_CREATE_CQ
- IB_USER_VERBS_CMD_CREATE_QP
- IB_USER_VERBS_CMD_CREATE_SRQ
- IB_USER_VERBS_CMD_CREATE_XSRQ
- IB_USER_VERBS_CMD_DEALLOC_MW
- IB_USER_VERBS_CMD_DEALLOC_PD
- IB_USER_VERBS_CMD_DEREG_MR
- IB_USER_VERBS_CMD_DESTROY_AH
- IB_USER_VERBS_CMD_DESTROY_CQ
- IB_USER_VERBS_CMD_DESTROY_QP
- IB_USER_VERBS_CMD_DESTROY_SRQ
- IB_USER_VERBS_CMD_DETACH_MCAST
- IB_USER_VERBS_CMD_FLAG_EXTENDED
- IB_USER_VERBS_CMD_GET_CONTEXT
- IB_USER_VERBS_CMD_MODIFY_AH
- IB_USER_VERBS_CMD_MODIFY_QP
- IB_USER_VERBS_CMD_MODIFY_SRQ
- IB_USER_VERBS_CMD_OPEN_QP
- IB_USER_VERBS_CMD_OPEN_XRCD
- IB_USER_VERBS_CMD_PEEK_CQ
- IB_USER_VERBS_CMD_POLL_CQ
- IB_USER_VERBS_CMD_POST_RECV
- IB_USER_VERBS_CMD_POST_SEND
- IB_USER_VERBS_CMD_POST_SRQ_RECV
- IB_USER_VERBS_CMD_QUERY_AH
- IB_USER_VERBS_CMD_QUERY_DEVICE
- IB_USER_VERBS_CMD_QUERY_MR
- IB_USER_VERBS_CMD_QUERY_PORT
- IB_USER_VERBS_CMD_QUERY_QP
- IB_USER_VERBS_CMD_QUERY_SRQ
- IB_USER_VERBS_CMD_REG_MR
- IB_USER_VERBS_CMD_REG_SMR
- IB_USER_VERBS_CMD_REQ_NOTIFY_CQ
- IB_USER_VERBS_CMD_REREG_MR
- IB_USER_VERBS_CMD_RESIZE_CQ
- IB_USER_VERBS_CMD_THRESHOLD
- IB_USER_VERBS_EX_CMD_CREATE_CQ
- IB_USER_VERBS_EX_CMD_CREATE_FLOW
- IB_USER_VERBS_EX_CMD_CREATE_QP
- IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
- IB_USER_VERBS_EX_CMD_CREATE_WQ
- IB_USER_VERBS_EX_CMD_DESTROY_FLOW
- IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
- IB_USER_VERBS_EX_CMD_DESTROY_WQ
- IB_USER_VERBS_EX_CMD_MODIFY_CQ
- IB_USER_VERBS_EX_CMD_MODIFY_QP
- IB_USER_VERBS_EX_CMD_MODIFY_WQ
- IB_USER_VERBS_EX_CMD_QUERY_DEVICE
- IB_USER_VERBS_H
- IB_USER_VERBS_MAX_LOG_IND_TBL_SIZE
- IB_UVERBS_ACCESS_HUGETLB
- IB_UVERBS_ACCESS_LOCAL_WRITE
- IB_UVERBS_ACCESS_MW_BIND
- IB_UVERBS_ACCESS_ON_DEMAND
- IB_UVERBS_ACCESS_REMOTE_ATOMIC
- IB_UVERBS_ACCESS_REMOTE_READ
- IB_UVERBS_ACCESS_REMOTE_WRITE
- IB_UVERBS_ACCESS_ZERO_BASED
- IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH
- IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE
- IB_UVERBS_ADVISE_MR_FLAG_FLUSH
- IB_UVERBS_BASE_DEV
- IB_UVERBS_BASE_MINOR
- IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN
- IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION
- IB_UVERBS_CREATE_QP_MASK_IND_TABLE
- IB_UVERBS_CREATE_QP_SUP_COMP_MASK
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT
- IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL
- IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM
- IB_UVERBS_FLOW_ACTION_ESP_REPLAY_BMP
- IB_UVERBS_FLOW_ACTION_ESP_REPLAY_NONE
- IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ
- IB_UVERBS_MAJOR
- IB_UVERBS_MAX_DEVICES
- IB_UVERBS_NUM_DYNAMIC_MINOR
- IB_UVERBS_NUM_FIXED_MINOR
- IB_UVERBS_PCF_AUTO_MIGR_SUP
- IB_UVERBS_PCF_BOOT_MGMT_SUP
- IB_UVERBS_PCF_CAP_MASK_NOTICE_SUP
- IB_UVERBS_PCF_CLIENT_REG_SUP
- IB_UVERBS_PCF_CM_SUP
- IB_UVERBS_PCF_DEVICE_MGMT_SUP
- IB_UVERBS_PCF_DR_NOTICE_SUP
- IB_UVERBS_PCF_EXTENDED_SPEEDS_SUP
- IB_UVERBS_PCF_HIERARCHY_INFO_SUP
- IB_UVERBS_PCF_IP_BASED_GIDS
- IB_UVERBS_PCF_LED_INFO_SUP
- IB_UVERBS_PCF_LINK_LATENCY_SUP
- IB_UVERBS_PCF_LINK_SPEED_WIDTH_TABLE_SUP
- IB_UVERBS_PCF_MCAST_FDB_TOP_SUP
- IB_UVERBS_PCF_MCAST_PKEY_TRAP_SUPPRESSION_SUP
- IB_UVERBS_PCF_MKEY_NVRAM
- IB_UVERBS_PCF_NOTICE_SUP
- IB_UVERBS_PCF_OPT_IPD_SUP
- IB_UVERBS_PCF_PKEY_NVRAM
- IB_UVERBS_PCF_PKEY_SW_EXT_PORT_TRAP_SUP
- IB_UVERBS_PCF_REINIT_SUP
- IB_UVERBS_PCF_SL_MAP_SUP
- IB_UVERBS_PCF_SM
- IB_UVERBS_PCF_SM_DISABLED
- IB_UVERBS_PCF_SNMP_TUNNEL_SUP
- IB_UVERBS_PCF_SYS_IMAGE_GUID_SUP
- IB_UVERBS_PCF_TRAP_SUP
- IB_UVERBS_PCF_VENDOR_CLASS_SUP
- IB_UVERBS_PCF_VENDOR_SPECIFIC_MADS_TABLE_SUP
- IB_UVERBS_QPF_GRH_REQUIRED
- IB_UVERBS_READ_COUNTERS_PREFER_CACHED
- IB_UVERBS_WR_ATOMIC_CMP_AND_SWP
- IB_UVERBS_WR_ATOMIC_FETCH_AND_ADD
- IB_UVERBS_WR_BIND_MW
- IB_UVERBS_WR_LOCAL_INV
- IB_UVERBS_WR_MASKED_ATOMIC_CMP_AND_SWP
- IB_UVERBS_WR_MASKED_ATOMIC_FETCH_AND_ADD
- IB_UVERBS_WR_RDMA_READ
- IB_UVERBS_WR_RDMA_READ_WITH_INV
- IB_UVERBS_WR_RDMA_WRITE
- IB_UVERBS_WR_RDMA_WRITE_WITH_IMM
- IB_UVERBS_WR_SEND
- IB_UVERBS_WR_SEND_WITH_IMM
- IB_UVERBS_WR_SEND_WITH_INV
- IB_UVERBS_WR_TSO
- IB_VERBS_H
- IB_VLAN_BYTES
- IB_VLARB_HIGHPRI_0_31
- IB_VLARB_HIGHPRI_32_63
- IB_VLARB_LOWPRI_0_31
- IB_VLARB_LOWPRI_32_63
- IB_VL_VL0
- IB_VL_VL0_1
- IB_VL_VL0_14
- IB_VL_VL0_3
- IB_VL_VL0_7
- IB_WC_BAD_RESP_ERR
- IB_WC_COMP_SWAP
- IB_WC_FATAL_ERR
- IB_WC_FETCH_ADD
- IB_WC_GENERAL_ERR
- IB_WC_GRH
- IB_WC_INV_EECN_ERR
- IB_WC_INV_EEC_STATE_ERR
- IB_WC_IP_CSUM_OK
- IB_WC_LOCAL_INV
- IB_WC_LOC_ACCESS_ERR
- IB_WC_LOC_EEC_OP_ERR
- IB_WC_LOC_LEN_ERR
- IB_WC_LOC_PROT_ERR
- IB_WC_LOC_QP_OP_ERR
- IB_WC_LOC_RDD_VIOL_ERR
- IB_WC_LSO
- IB_WC_MASKED_COMP_SWAP
- IB_WC_MASKED_FETCH_ADD
- IB_WC_MW_BIND_ERR
- IB_WC_RDMA_READ
- IB_WC_RDMA_WRITE
- IB_WC_RECV
- IB_WC_RECV_RDMA_WITH_IMM
- IB_WC_REG_MR
- IB_WC_REM_ABORT_ERR
- IB_WC_REM_ACCESS_ERR
- IB_WC_REM_INV_RD_REQ_ERR
- IB_WC_REM_INV_REQ_ERR
- IB_WC_REM_OP_ERR
- IB_WC_RESP_TIMEOUT_ERR
- IB_WC_RETRY_EXC_ERR
- IB_WC_RNR_RETRY_EXC_ERR
- IB_WC_SEND
- IB_WC_STATUS_LIST
- IB_WC_SUCCESS
- IB_WC_WITH_IMM
- IB_WC_WITH_INVALIDATE
- IB_WC_WITH_NETWORK_HDR_TYPE
- IB_WC_WITH_SMAC
- IB_WC_WITH_VLAN
- IB_WC_WR_FLUSH_ERR
- IB_WIDTH_12X
- IB_WIDTH_1X
- IB_WIDTH_2X
- IB_WIDTH_4X
- IB_WIDTH_8X
- IB_WIN_SIZE
- IB_WQS_ERR
- IB_WQS_RDY
- IB_WQS_RESET
- IB_WQT_RQ
- IB_WQ_CUR_STATE
- IB_WQ_FLAGS
- IB_WQ_FLAGS_CVLAN_STRIPPING
- IB_WQ_FLAGS_DELAY_DROP
- IB_WQ_FLAGS_PCI_WRITE_END_PADDING
- IB_WQ_FLAGS_SCATTER_FCS
- IB_WQ_STATE
- IB_WR_ATOMIC_CMP_AND_SWP
- IB_WR_ATOMIC_FETCH_AND_ADD
- IB_WR_LOCAL_INV
- IB_WR_LSO
- IB_WR_MASKED_ATOMIC_CMP_AND_SWP
- IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
- IB_WR_OPFN
- IB_WR_RDMA_READ
- IB_WR_RDMA_READ_WITH_INV
- IB_WR_RDMA_WRITE
- IB_WR_RDMA_WRITE_WITH_IMM
- IB_WR_REG_MR
- IB_WR_REG_MR_INTEGRITY
- IB_WR_RESERVED1
- IB_WR_RESERVED10
- IB_WR_RESERVED2
- IB_WR_RESERVED3
- IB_WR_RESERVED4
- IB_WR_RESERVED5
- IB_WR_RESERVED6
- IB_WR_RESERVED7
- IB_WR_RESERVED8
- IB_WR_RESERVED9
- IB_WR_SEND
- IB_WR_SEND_WITH_IMM
- IB_WR_SEND_WITH_INV
- IB_WR_TID_RDMA_READ
- IB_WR_TID_RDMA_WRITE
- IB_ZERO_BASED
- IC1R
- IC2R
- IC3R
- IC3_VERSION
- IC4R
- IC5R
- IC6R
- IC6_VERSION
- IC7R
- IC8R
- IC9R
- ICACHE
- ICACHEF_ALIASING
- ICACHEF_VPIPT
- ICACHE_ALIAS
- ICACHE_ALIAS_EQ
- ICACHE_ALIAS_MASK
- ICACHE_ALIAS_ORDER
- ICACHE_ENABLE
- ICACHE_FLUSH
- ICACHE_MAX_ADDR
- ICACHE_POLICY_PIPT
- ICACHE_POLICY_VIPT
- ICACHE_POLICY_VPIPT
- ICACHE_REFILLS_WORKAROUND_WAR
- ICACHE_SET_MASK
- ICACHE_SIZE
- ICACHE_WAY_SHIFT
- ICACHE_WAY_SIZE
- ICACRT_msg_to_type50CRT_msg
- ICACRT_msg_to_type6CRT_msgX
- ICADE_MAX_USAGE
- ICALL_ACCEPT
- ICALL_IGNORE
- ICALL_REJECT
- ICAMEX_msg_to_type50MEX_msg
- ICAMEX_msg_to_type6MEX_msgX
- ICAN3_BUSERR_QUOTA_MAX
- ICAN3_CAN_CLOCK
- ICAN3_CAN_DLC_MASK
- ICAN3_CAN_TYPE_EFF
- ICAN3_CAN_TYPE_MASK
- ICAN3_CAN_TYPE_SFF
- ICAN3_ECHO
- ICAN3_EFF
- ICAN3_EFF_RTR
- ICAN3_FWTYPE_CAL_CANOPEN
- ICAN3_FWTYPE_ICANOS
- ICAN3_NEW_BUFFERS
- ICAN3_RX_BUFFERS
- ICAN3_SFF_RTR
- ICAN3_SNGL
- ICAN3_TX_BUFFERS
- ICANON
- ICARSACRT
- ICARSAMODEXPO
- ICAUSE
- ICB
- ICBI
- ICBR_RESERVED
- ICBTAG_FILE_TYPE_BITMAP
- ICBTAG_FILE_TYPE_BLOCK
- ICBTAG_FILE_TYPE_CHAR
- ICBTAG_FILE_TYPE_DIRECTORY
- ICBTAG_FILE_TYPE_EA
- ICBTAG_FILE_TYPE_FIFO
- ICBTAG_FILE_TYPE_IE
- ICBTAG_FILE_TYPE_MAIN
- ICBTAG_FILE_TYPE_MIRROR
- ICBTAG_FILE_TYPE_PIE
- ICBTAG_FILE_TYPE_REALTIME
- ICBTAG_FILE_TYPE_REGULAR
- ICBTAG_FILE_TYPE_SOCKET
- ICBTAG_FILE_TYPE_STREAMDIR
- ICBTAG_FILE_TYPE_SYMLINK
- ICBTAG_FILE_TYPE_TE
- ICBTAG_FILE_TYPE_UNDEF
- ICBTAG_FILE_TYPE_USE
- ICBTAG_FILE_TYPE_VAT15
- ICBTAG_FILE_TYPE_VAT20
- ICBTAG_FLAG_AD_EXTENDED
- ICBTAG_FLAG_AD_IN_ICB
- ICBTAG_FLAG_AD_LONG
- ICBTAG_FLAG_AD_MASK
- ICBTAG_FLAG_AD_SHORT
- ICBTAG_FLAG_ARCHIVE
- ICBTAG_FLAG_CONTIGUOUS
- ICBTAG_FLAG_MULTIVERSIONS
- ICBTAG_FLAG_NONRELOCATABLE
- ICBTAG_FLAG_SETGID
- ICBTAG_FLAG_SETUID
- ICBTAG_FLAG_SORTED
- ICBTAG_FLAG_STICKY
- ICBTAG_FLAG_STREAM
- ICBTAG_FLAG_SYSTEM
- ICBTAG_FLAG_TRANSFORMED
- ICBTAG_STRATEGY_TYPE_1
- ICBTAG_STRATEGY_TYPE_2
- ICBTAG_STRATEGY_TYPE_3
- ICBTAG_STRATEGY_TYPE_4
- ICBTAG_STRATEGY_TYPE_UNDEF
- ICB_H
- ICB_L
- ICB_RID
- ICB_VERSION
- ICC
- ICCCR
- ICCH
- ICCL
- ICCR
- ICCR0
- ICCR0_ICI
- ICCR0_INIT_VAL
- ICCR0_OFF
- ICCR0_ON
- ICCR1
- ICCR1_ICE
- ICCR1_IICRST
- ICCR1_INIT_VAL
- ICCR1_NOLOCK
- ICCR1_SOWP
- ICCR2_BBSY
- ICCR2_RS
- ICCR2_SP
- ICCR2_ST
- ICCR_BASE
- ICCR_BBSY
- ICCR_CACHE
- ICCR_DIM
- ICCR_ICE
- ICCR_IdleAllInt
- ICCR_IdleMskInt
- ICCR_NOCACHE
- ICCR_RACK
- ICCR_REG0
- ICCR_REG1
- ICCR_SCP
- ICCR_TRS
- ICC_AP0R0
- ICC_AP0R1
- ICC_AP0R2
- ICC_AP0R3
- ICC_AP1R0
- ICC_AP1R1
- ICC_AP1R2
- ICC_AP1R3
- ICC_BPR0_EL1_MASK
- ICC_BPR0_EL1_SHIFT
- ICC_BPR1
- ICC_BPR1_EL1_MASK
- ICC_BPR1_EL1_SHIFT
- ICC_BUCK_TURN_OFF_SR
- ICC_CTLR
- ICC_CTLR_EL1_A3V_MASK
- ICC_CTLR_EL1_A3V_SHIFT
- ICC_CTLR_EL1_CBPR_MASK
- ICC_CTLR_EL1_CBPR_SHIFT
- ICC_CTLR_EL1_EOImode_MASK
- ICC_CTLR_EL1_EOImode_SHIFT
- ICC_CTLR_EL1_EOImode_drop
- ICC_CTLR_EL1_EOImode_drop_dir
- ICC_CTLR_EL1_ExtRange
- ICC_CTLR_EL1_ID_BITS_MASK
- ICC_CTLR_EL1_ID_BITS_SHIFT
- ICC_CTLR_EL1_PRI_BITS_MASK
- ICC_CTLR_EL1_PRI_BITS_SHIFT
- ICC_CTLR_EL1_RSS
- ICC_CTLR_EL1_SEIS_MASK
- ICC_CTLR_EL1_SEIS_SHIFT
- ICC_DIR
- ICC_EOIR1
- ICC_EVENT_ENABLED
- ICC_HSRE
- ICC_IAR1
- ICC_IAR1_EL1_SPURIOUS
- ICC_IGRPEN0_EL1_MASK
- ICC_IGRPEN0_EL1_SHIFT
- ICC_IGRPEN1
- ICC_IGRPEN1_EL1_MASK
- ICC_IGRPEN1_EL1_SHIFT
- ICC_LDO_TURN_OFF_SR
- ICC_MAX_INT_COUNT_THRESHOLD
- ICC_MAX_INT_TICKS_THRESHOLD
- ICC_MIN_INT_COUNT_THRESHOLD
- ICC_MIN_INT_TICKS_THRESHOLD
- ICC_PMR
- ICC_PMR_EL1_MASK
- ICC_PMR_EL1_SHIFT
- ICC_RPR
- ICC_SAFE_INT_TICKS
- ICC_SGI1R
- ICC_SGI1R_AFFINITY_1_MASK
- ICC_SGI1R_AFFINITY_1_SHIFT
- ICC_SGI1R_AFFINITY_2_MASK
- ICC_SGI1R_AFFINITY_2_SHIFT
- ICC_SGI1R_AFFINITY_3_MASK
- ICC_SGI1R_AFFINITY_3_SHIFT
- ICC_SGI1R_IRQ_ROUTING_MODE_BIT
- ICC_SGI1R_RS_MASK
- ICC_SGI1R_RS_SHIFT
- ICC_SGI1R_SGI_ID_MASK
- ICC_SGI1R_SGI_ID_SHIFT
- ICC_SGI1R_TARGET_LIST_MASK
- ICC_SGI1R_TARGET_LIST_SHIFT
- ICC_SRE
- ICC_SRE_EL1_DFB
- ICC_SRE_EL1_DIB
- ICC_SRE_EL1_SRE
- ICC_SRE_EL2_ENABLE
- ICC_SRE_EL2_SRE
- ICDCTR16
- ICDCTR32
- ICDC_DSS0
- ICDC_DSS1
- ICDC_DSS2
- ICDC_DSS3
- ICDC_DSS4
- ICDC_DSS5
- ICDC_FIQ
- ICDC_IRQ
- ICDC_RGADW_OFFSET
- ICDC_RGADW_RGADDR_MASK
- ICDC_RGADW_RGADDR_OFFSET
- ICDC_RGADW_RGDIN_MASK
- ICDC_RGADW_RGDIN_OFFSET
- ICDC_RGADW_RGWR
- ICDC_RGDATA_IRQ
- ICDC_RGDATA_OFFSET
- ICDC_RGDATA_RGDOUT_MASK
- ICDC_RGDATA_RGDOUT_OFFSET
- ICDMAER
- ICDR
- ICD_PARTS
- ICE
- ICE1712_16BIT
- ICE1712_6FIRE_AK4524_CS_MASK
- ICE1712_6FIRE_CS8427_ADDR
- ICE1712_6FIRE_PCF9554_ADDR
- ICE1712_6FIRE_RW
- ICE1712_6FIRE_RX2
- ICE1712_6FIRE_SERIAL_CLOCK
- ICE1712_6FIRE_SERIAL_DATA
- ICE1712_6FIRE_TX2
- ICE1712_AC97_CAP_VSR
- ICE1712_AC97_COLD
- ICE1712_AC97_PBK_VSR
- ICE1712_AC97_READ
- ICE1712_AC97_READY
- ICE1712_AC97_WARM
- ICE1712_AC97_WRITE
- ICE1712_BUFFER0_AUTO
- ICE1712_BUFFER1
- ICE1712_BUFFER1_AUTO
- ICE1712_CAPTURE_START
- ICE1712_CAPTURE_START_SHADOW
- ICE1712_CFG_2xMPU401
- ICE1712_CFG_AC97_PACKED
- ICE1712_CFG_ADC_MASK
- ICE1712_CFG_CLOCK
- ICE1712_CFG_CLOCK384
- ICE1712_CFG_CLOCK512
- ICE1712_CFG_DAC_MASK
- ICE1712_CFG_EXT
- ICE1712_CFG_I2S_96KHZ
- ICE1712_CFG_I2S_CHIPID
- ICE1712_CFG_I2S_OTHER
- ICE1712_CFG_I2S_RESMASK
- ICE1712_CFG_I2S_VOLUME
- ICE1712_CFG_NO_CON_AC97
- ICE1712_CFG_PRO_I2S
- ICE1712_CFG_SPDIF_IN
- ICE1712_CFG_SPDIF_OUT
- ICE1712_DELTA_1010LT_CCLK
- ICE1712_DELTA_1010LT_CS
- ICE1712_DELTA_1010LT_CS_CHIP_A
- ICE1712_DELTA_1010LT_CS_CHIP_B
- ICE1712_DELTA_1010LT_CS_CHIP_C
- ICE1712_DELTA_1010LT_CS_CHIP_D
- ICE1712_DELTA_1010LT_CS_CS8427
- ICE1712_DELTA_1010LT_CS_NONE
- ICE1712_DELTA_1010LT_DIN
- ICE1712_DELTA_1010LT_DOUT
- ICE1712_DELTA_1010LT_WORDCLOCK
- ICE1712_DELTA_66E_CCLK
- ICE1712_DELTA_66E_CS_CHIP_A
- ICE1712_DELTA_66E_CS_CHIP_B
- ICE1712_DELTA_66E_CS_CS8427
- ICE1712_DELTA_66E_DIN
- ICE1712_DELTA_66E_DOUT
- ICE1712_DELTA_AP_CCLK
- ICE1712_DELTA_AP_CS_CODEC
- ICE1712_DELTA_AP_CS_DIGITAL
- ICE1712_DELTA_AP_DIN
- ICE1712_DELTA_AP_DOUT
- ICE1712_DELTA_CODEC_CHIP_A
- ICE1712_DELTA_CODEC_CHIP_B
- ICE1712_DELTA_CODEC_SERIAL_CLOCK
- ICE1712_DELTA_CODEC_SERIAL_DATA
- ICE1712_DELTA_DFS
- ICE1712_DELTA_SPDIF_INPUT_SELECT
- ICE1712_DELTA_SPDIF_IN_STAT
- ICE1712_DELTA_SPDIF_OUT_STAT_CLOCK
- ICE1712_DELTA_SPDIF_OUT_STAT_DATA
- ICE1712_DELTA_WORD_CLOCK_SELECT
- ICE1712_DELTA_WORD_CLOCK_STATUS
- ICE1712_DMA_AUTOINIT
- ICE1712_DMA_MODE_WRITE
- ICE1712_DOS_VOL
- ICE1712_DSC_ADDR0
- ICE1712_DSC_ADDR1
- ICE1712_DSC_CONTROL
- ICE1712_DSC_COUNT0
- ICE1712_DSC_COUNT1
- ICE1712_DSC_RATE
- ICE1712_DSC_VOLUME
- ICE1712_DS_DATA
- ICE1712_DS_INDEX
- ICE1712_DS_INTMASK
- ICE1712_DS_INTSTAT
- ICE1712_EWS88D_PCF_ADDR
- ICE1712_EWS88MT_CS8404_ADDR
- ICE1712_EWS88MT_INPUT_ADDR
- ICE1712_EWS88MT_OUTPUT_ADDR
- ICE1712_EWS88MT_OUTPUT_SENSE
- ICE1712_EWS88_CS8414_RATE
- ICE1712_EWS88_RW
- ICE1712_EWS88_RX2
- ICE1712_EWS88_SERIAL_CLOCK
- ICE1712_EWS88_SERIAL_DATA
- ICE1712_EWS88_TX2
- ICE1712_EWX2496_AIN_SEL
- ICE1712_EWX2496_AK4524_CS
- ICE1712_EWX2496_AOUT_SEL
- ICE1712_EWX2496_RW
- ICE1712_EWX2496_RX2
- ICE1712_EWX2496_SERIAL_CLOCK
- ICE1712_EWX2496_SERIAL_DATA
- ICE1712_EWX2496_TX2
- ICE1712_FLUSH
- ICE1712_GPIO
- ICE1712_I2C_BUSY
- ICE1712_I2C_EEPROM
- ICE1712_I2C_WRITE
- ICE1712_IREG_CAP_COUNT_HI
- ICE1712_IREG_CAP_COUNT_LO
- ICE1712_IREG_CAP_CTRL
- ICE1712_IREG_CONSUMER_POWERDOWN
- ICE1712_IREG_GPIO_DATA
- ICE1712_IREG_GPIO_DIRECTION
- ICE1712_IREG_GPIO_WRITE_MASK
- ICE1712_IREG_PBK_COUNT_HI
- ICE1712_IREG_PBK_COUNT_LO
- ICE1712_IREG_PBK_CTRL
- ICE1712_IREG_PBK_LEFT
- ICE1712_IREG_PBK_RATE_HI
- ICE1712_IREG_PBK_RATE_LO
- ICE1712_IREG_PBK_RATE_MID
- ICE1712_IREG_PBK_RIGHT
- ICE1712_IREG_PBK_SOFT
- ICE1712_IREG_PRO_POWERDOWN
- ICE1712_IRQ_CONCAP
- ICE1712_IRQ_CONPBK
- ICE1712_IRQ_FM
- ICE1712_IRQ_MPU1
- ICE1712_IRQ_MPU2
- ICE1712_IRQ_PBKDS
- ICE1712_IRQ_PROPCM
- ICE1712_IRQ_TIMER
- ICE1712_MT_AC97_CMD
- ICE1712_MT_AC97_DATA
- ICE1712_MT_AC97_INDEX
- ICE1712_MT_CAPTURE_ADDR
- ICE1712_MT_CAPTURE_CONTROL
- ICE1712_MT_CAPTURE_COUNT
- ICE1712_MT_CAPTURE_SIZE
- ICE1712_MT_I2S_FORMAT
- ICE1712_MT_IRQ
- ICE1712_MT_MONITOR_INDEX
- ICE1712_MT_MONITOR_PEAKDATA
- ICE1712_MT_MONITOR_PEAKINDEX
- ICE1712_MT_MONITOR_RATE
- ICE1712_MT_MONITOR_ROUTECTRL
- ICE1712_MT_MONITOR_VOLUME
- ICE1712_MT_PLAYBACK_ADDR
- ICE1712_MT_PLAYBACK_CONTROL
- ICE1712_MT_PLAYBACK_COUNT
- ICE1712_MT_PLAYBACK_SIZE
- ICE1712_MT_RATE
- ICE1712_MT_ROUTE_CAPTURE
- ICE1712_MT_ROUTE_PSDOUT03
- ICE1712_MT_ROUTE_SPDOUT
- ICE1712_MULTI_CAPSTATUS
- ICE1712_MULTI_CAPTURE
- ICE1712_MULTI_PBKSTATUS
- ICE1712_MULTI_PLAYBACK
- ICE1712_NATIVE
- ICE1712_PAUSE
- ICE1712_PLAYBACK_PAUSE
- ICE1712_PLAYBACK_START
- ICE1712_REG_AC97_CMD
- ICE1712_REG_AC97_DATA
- ICE1712_REG_AC97_INDEX
- ICE1712_REG_CONCAP_ADDR
- ICE1712_REG_CONCAP_COUNT
- ICE1712_REG_CONTROL
- ICE1712_REG_DATA
- ICE1712_REG_I2C_BYTE_ADDR
- ICE1712_REG_I2C_CTRL
- ICE1712_REG_I2C_DATA
- ICE1712_REG_I2C_DEV_ADDR
- ICE1712_REG_INDEX
- ICE1712_REG_IRQMASK
- ICE1712_REG_IRQSTAT
- ICE1712_REG_MPU1_CTRL
- ICE1712_REG_MPU1_DATA
- ICE1712_REG_MPU2_CTRL
- ICE1712_REG_MPU2_DATA
- ICE1712_REG_NMI_DATA
- ICE1712_REG_NMI_INDEX
- ICE1712_REG_NMI_STAT1
- ICE1712_REG_SERR_SHADOW
- ICE1712_REG_TIMER
- ICE1712_RESET
- ICE1712_ROUTE_AC97
- ICE1712_SERR_ASSERT_DS_DMA
- ICE1712_SERR_ASSERT_SB
- ICE1712_SERR_LEVEL
- ICE1712_SPDIF_MASTER
- ICE1712_START
- ICE1712_STDSP24_0_BOX
- ICE1712_STDSP24_0_DAREAR
- ICE1712_STDSP24_1_CHN1
- ICE1712_STDSP24_1_CHN2
- ICE1712_STDSP24_1_CHN3
- ICE1712_STDSP24_2_CHN4
- ICE1712_STDSP24_2_MIDI1
- ICE1712_STDSP24_2_MIDIIN
- ICE1712_STDSP24_3_INSEL
- ICE1712_STDSP24_3_MIDI2
- ICE1712_STDSP24_3_MUTE
- ICE1712_STDSP24_AK4524_CS
- ICE1712_STDSP24_BOX_CHN1
- ICE1712_STDSP24_BOX_CHN2
- ICE1712_STDSP24_BOX_CHN3
- ICE1712_STDSP24_BOX_CHN4
- ICE1712_STDSP24_BOX_MIDI1
- ICE1712_STDSP24_BOX_MIDI2
- ICE1712_STDSP24_CLOCK
- ICE1712_STDSP24_CLOCK_BIT
- ICE1712_STDSP24_DAREAR
- ICE1712_STDSP24_INSEL
- ICE1712_STDSP24_MUTE
- ICE1712_STDSP24_SERIAL_CLOCK
- ICE1712_STDSP24_SERIAL_DATA
- ICE1712_STDSP24_SET_ADDR
- ICE1712_STEREO
- ICE1712_SUBDEVICE_AUDIOPHILE
- ICE1712_SUBDEVICE_DELTA1010
- ICE1712_SUBDEVICE_DELTA1010E
- ICE1712_SUBDEVICE_DELTA1010LT
- ICE1712_SUBDEVICE_DELTA410
- ICE1712_SUBDEVICE_DELTA44
- ICE1712_SUBDEVICE_DELTA66
- ICE1712_SUBDEVICE_DELTA66E
- ICE1712_SUBDEVICE_DELTADIO2496
- ICE1712_SUBDEVICE_DMX6FIRE
- ICE1712_SUBDEVICE_EDIROLDA2496
- ICE1712_SUBDEVICE_EVENT_EZ8
- ICE1712_SUBDEVICE_EWS88D
- ICE1712_SUBDEVICE_EWS88MT
- ICE1712_SUBDEVICE_EWS88MT_NEW
- ICE1712_SUBDEVICE_EWX2496
- ICE1712_SUBDEVICE_MEDIASTATION
- ICE1712_SUBDEVICE_PHASE88
- ICE1712_SUBDEVICE_STAUDIO_ADCIII
- ICE1712_SUBDEVICE_STDSP24
- ICE1712_SUBDEVICE_STDSP24_MEDIA7_1
- ICE1712_SUBDEVICE_STDSP24_VALUE
- ICE1712_SUBDEVICE_TS88
- ICE1712_SUBDEVICE_VX442
- ICE1712_VX442_CCLK
- ICE1712_VX442_CODEC_CHIP_A
- ICE1712_VX442_CODEC_CHIP_B
- ICE1712_VX442_CS_DIGITAL
- ICE1712_VX442_DIN
- ICE1712_VX442_DOUT
- ICE40_SPI_HOUSEKEEPING_DELAY
- ICE40_SPI_MAX_SPEED
- ICE40_SPI_MIN_SPEED
- ICE40_SPI_NUM_ACTIVATION_BYTES
- ICE40_SPI_RESET_DELAY
- ICEDS
- ICELAND_SMC_SIZE
- ICEMACR
- ICEMACR_ADDR
- ICEMAMR
- ICEMAMR_ADDR
- ICEMCCR
- ICEMCCR_ADDR
- ICEMCCR_PD
- ICEMCCR_RW
- ICEMCMR
- ICEMCMR_ADDR
- ICEMCMR_PDM
- ICEMCMR_RWM
- ICEMCR
- ICEMCR_ADDR
- ICEMCR_BBIEN
- ICEMCR_CEN
- ICEMCR_HMDIS
- ICEMCR_PBEN
- ICEMCR_SB
- ICEMSR
- ICEMSR_ADDR
- ICEMSR_BBIRQ
- ICEMSR_BRKIRQ
- ICEMSR_EMIRQ
- ICEMSR_EMUEN
- ICEMT
- ICEMT1724
- ICEREG
- ICEREG1724
- ICE_AGG_TYPE_AGG
- ICE_AGG_TYPE_Q
- ICE_AGG_TYPE_QG
- ICE_AGG_TYPE_UNKNOWN
- ICE_AGG_TYPE_VSI
- ICE_ALL_STATS_LEN
- ICE_APP_PROT_ID_FCOE
- ICE_APP_PROT_ID_FIP
- ICE_APP_PROT_ID_ISCSI
- ICE_APP_SEL_ETHTYPE
- ICE_APP_SEL_TCPIP
- ICE_AQC_CAPS_DCB
- ICE_AQC_CAPS_MAX_MTU
- ICE_AQC_CAPS_MSIX
- ICE_AQC_CAPS_RSS
- ICE_AQC_CAPS_RXQS
- ICE_AQC_CAPS_SRIOV
- ICE_AQC_CAPS_TXQS
- ICE_AQC_CAPS_VALID_FUNCTIONS
- ICE_AQC_CAPS_VF
- ICE_AQC_CAPS_VSI
- ICE_AQC_CEE_APP_FCOE_M
- ICE_AQC_CEE_APP_FCOE_S
- ICE_AQC_CEE_APP_FIP_M
- ICE_AQC_CEE_APP_FIP_S
- ICE_AQC_CEE_APP_ISCSI_M
- ICE_AQC_CEE_APP_ISCSI_S
- ICE_AQC_CEE_FCOE_STATUS_M
- ICE_AQC_CEE_FCOE_STATUS_S
- ICE_AQC_CEE_FIP_STATUS_M
- ICE_AQC_CEE_FIP_STATUS_S
- ICE_AQC_CEE_ISCSI_STATUS_M
- ICE_AQC_CEE_ISCSI_STATUS_S
- ICE_AQC_CEE_PFC_STATUS_M
- ICE_AQC_CEE_PFC_STATUS_S
- ICE_AQC_CEE_PG_STATUS_M
- ICE_AQC_CEE_PG_STATUS_S
- ICE_AQC_CLEAR_PXE_RX_CNT
- ICE_AQC_DOWNLOAD_PKG_LAST_BUF
- ICE_AQC_DRIVER_UNLOADING
- ICE_AQC_ELEM_FLAG_SUSPEND_M
- ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M
- ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S
- ICE_AQC_ELEM_GENERIC_MODE_M
- ICE_AQC_ELEM_GENERIC_PRIO_M
- ICE_AQC_ELEM_GENERIC_PRIO_S
- ICE_AQC_ELEM_GENERIC_SP_M
- ICE_AQC_ELEM_GENERIC_SP_S
- ICE_AQC_ELEM_TYPE_ENTRY_POINT
- ICE_AQC_ELEM_TYPE_LEAF
- ICE_AQC_ELEM_TYPE_ROOT_PORT
- ICE_AQC_ELEM_TYPE_SE_GENERIC
- ICE_AQC_ELEM_TYPE_SE_PADDED
- ICE_AQC_ELEM_TYPE_TC
- ICE_AQC_ELEM_TYPE_UNDEFINED
- ICE_AQC_ELEM_VALID_CIR
- ICE_AQC_ELEM_VALID_EIR
- ICE_AQC_ELEM_VALID_GENERIC
- ICE_AQC_ELEM_VALID_SHARED
- ICE_AQC_FW_LOG_AQ_EN
- ICE_AQC_FW_LOG_AQ_VALID
- ICE_AQC_FW_LOG_CLEAR
- ICE_AQC_FW_LOG_CONF_BAD_INDX
- ICE_AQC_FW_LOG_CONF_SUCCESS
- ICE_AQC_FW_LOG_EN_M
- ICE_AQC_FW_LOG_EN_S
- ICE_AQC_FW_LOG_ERR_EN
- ICE_AQC_FW_LOG_FLOW_EN
- ICE_AQC_FW_LOG_ID_ADMINQ
- ICE_AQC_FW_LOG_ID_AUTH
- ICE_AQC_FW_LOG_ID_CTRL
- ICE_AQC_FW_LOG_ID_DCB
- ICE_AQC_FW_LOG_ID_DCBX
- ICE_AQC_FW_LOG_ID_DNL
- ICE_AQC_FW_LOG_ID_GENERAL
- ICE_AQC_FW_LOG_ID_HDMA
- ICE_AQC_FW_LOG_ID_I2C
- ICE_AQC_FW_LOG_ID_IOSF
- ICE_AQC_FW_LOG_ID_LINK
- ICE_AQC_FW_LOG_ID_LINK_TOPO
- ICE_AQC_FW_LOG_ID_LLDP
- ICE_AQC_FW_LOG_ID_M
- ICE_AQC_FW_LOG_ID_MAX
- ICE_AQC_FW_LOG_ID_MDIO
- ICE_AQC_FW_LOG_ID_MNG
- ICE_AQC_FW_LOG_ID_NETPROXY
- ICE_AQC_FW_LOG_ID_NVM
- ICE_AQC_FW_LOG_ID_PARSER
- ICE_AQC_FW_LOG_ID_POST
- ICE_AQC_FW_LOG_ID_RSVD
- ICE_AQC_FW_LOG_ID_S
- ICE_AQC_FW_LOG_ID_SCHEDULER
- ICE_AQC_FW_LOG_ID_SDP
- ICE_AQC_FW_LOG_ID_SW
- ICE_AQC_FW_LOG_ID_TASK_DISPATCH
- ICE_AQC_FW_LOG_ID_TXQ
- ICE_AQC_FW_LOG_ID_VPD
- ICE_AQC_FW_LOG_ID_WATCHDOG
- ICE_AQC_FW_LOG_INFO_EN
- ICE_AQC_FW_LOG_INIT_EN
- ICE_AQC_FW_LOG_MORE_DATA_AVAIL
- ICE_AQC_FW_LOG_UART_EN
- ICE_AQC_FW_LOG_UART_VALID
- ICE_AQC_GET_PHY_EN_MOD_QUAL
- ICE_AQC_GET_PHY_RQM
- ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE
- ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE
- ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M
- ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S
- ICE_AQC_GET_SW_CONF_RESP_IS_VF
- ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT
- ICE_AQC_GET_SW_CONF_RESP_TYPE_M
- ICE_AQC_GET_SW_CONF_RESP_TYPE_S
- ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT
- ICE_AQC_GET_SW_CONF_RESP_VSI
- ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M
- ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S
- ICE_AQC_GSET_RSS_KEY_VSI_ID_M
- ICE_AQC_GSET_RSS_KEY_VSI_ID_S
- ICE_AQC_GSET_RSS_KEY_VSI_VALID
- ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M
- ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M
- ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S
- ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL
- ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M
- ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF
- ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S
- ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI
- ICE_AQC_GSET_RSS_LUT_VSI_ID_M
- ICE_AQC_GSET_RSS_LUT_VSI_ID_S
- ICE_AQC_GSET_RSS_LUT_VSI_VALID
- ICE_AQC_MAN_MAC_ADDR_TYPE_LAN
- ICE_AQC_MAN_MAC_ADDR_TYPE_WOL
- ICE_AQC_MAN_MAC_LAN_ADDR_VALID
- ICE_AQC_MAN_MAC_PORT_ADDR_VALID
- ICE_AQC_MAN_MAC_READ_M
- ICE_AQC_MAN_MAC_READ_S
- ICE_AQC_MAN_MAC_SAN_ADDR_VALID
- ICE_AQC_MAN_MAC_UPDATE_LAA
- ICE_AQC_MAN_MAC_UPDATE_LAA_WOL
- ICE_AQC_MAN_MAC_WOL_ADDR_VALID
- ICE_AQC_MAN_MAC_WR_M
- ICE_AQC_MAN_MAC_WR_MC_MAG_EN
- ICE_AQC_MAN_MAC_WR_S
- ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP
- ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS
- ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS
- ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER
- ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR
- ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM
- ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR
- ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE
- ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE
- ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS
- ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS
- ICE_AQC_NVM_CHECKSUM_CORRECT
- ICE_AQC_NVM_CHECKSUM_RECALC
- ICE_AQC_NVM_CHECKSUM_VERIFY
- ICE_AQC_NVM_ERASE_LEN
- ICE_AQC_NVM_FLASH_ONLY
- ICE_AQC_NVM_LAST_CMD
- ICE_AQC_NVM_NO_PRESERVATION
- ICE_AQC_NVM_PCIR_REQ
- ICE_AQC_NVM_PRESERVATION_M
- ICE_AQC_NVM_PRESERVATION_S
- ICE_AQC_NVM_PRESERVE_ALL
- ICE_AQC_NVM_PRESERVE_SELECTED
- ICE_AQC_PHY_AN_MODE
- ICE_AQC_PHY_CAPS_MASK
- ICE_AQC_PHY_EEE_EN_1000BASE_KX
- ICE_AQC_PHY_EEE_EN_1000BASE_T
- ICE_AQC_PHY_EEE_EN_100BASE_TX
- ICE_AQC_PHY_EEE_EN_10GBASE_KR
- ICE_AQC_PHY_EEE_EN_10GBASE_T
- ICE_AQC_PHY_EEE_EN_25GBASE_KR
- ICE_AQC_PHY_EEE_EN_40GBASE_KR4
- ICE_AQC_PHY_EN_AUTO_FEC
- ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG
- ICE_AQC_PHY_EN_LINK
- ICE_AQC_PHY_EN_RX_LINK_PAUSE
- ICE_AQC_PHY_EN_TX_LINK_PAUSE
- ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN
- ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ
- ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN
- ICE_AQC_PHY_FEC_25G_KR_REQ
- ICE_AQC_PHY_FEC_25G_RS_528_REQ
- ICE_AQC_PHY_FEC_25G_RS_544_REQ
- ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN
- ICE_AQC_PHY_FEC_MASK
- ICE_AQC_PHY_LOW_POWER_MODE
- ICE_AQC_PORT_IDENT_LED_BLINK
- ICE_AQC_PORT_IDENT_LED_ORIG
- ICE_AQC_QUAL_MOD_COUNT_MAX
- ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q
- ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET
- ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S
- ICE_AQC_Q_DIS_CMD_FLUSH_PIPE
- ICE_AQC_Q_DIS_CMD_M
- ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET
- ICE_AQC_Q_DIS_CMD_PF_RESET
- ICE_AQC_Q_DIS_CMD_S
- ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL
- ICE_AQC_Q_DIS_CMD_VF_RESET
- ICE_AQC_Q_DIS_CMD_VM_RESET
- ICE_AQC_Q_DIS_TIMEOUT_M
- ICE_AQC_Q_DIS_TIMEOUT_S
- ICE_AQC_Q_DIS_VMVF_NUM_M
- ICE_AQC_Q_DIS_VMVF_NUM_S
- ICE_AQC_REPORT_MODE_M
- ICE_AQC_REPORT_MODE_S
- ICE_AQC_REPORT_NVM_CAP
- ICE_AQC_REPORT_SW_CFG
- ICE_AQC_REPORT_TOPO_CAP
- ICE_AQC_RESTART_AN_LINK_ENABLE
- ICE_AQC_RESTART_AN_LINK_RESTART
- ICE_AQC_RES_ACCESS_READ
- ICE_AQC_RES_ACCESS_WRITE
- ICE_AQC_RES_ID_CHNG_LOCK
- ICE_AQC_RES_ID_GLBL_LOCK
- ICE_AQC_RES_ID_NVM
- ICE_AQC_RES_ID_SDP
- ICE_AQC_RES_TYPE_SHARED_M
- ICE_AQC_RES_TYPE_SHARED_S
- ICE_AQC_RES_TYPE_VSI_LIST_PRUNE
- ICE_AQC_RES_TYPE_VSI_LIST_REP
- ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M
- ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S
- ICE_AQC_START_STOP_AGENT_M
- ICE_AQC_START_STOP_AGENT_START_DCBX
- ICE_AQC_START_STOP_AGENT_STOP_DCBX
- ICE_AQC_SW_RULES_T_LG_ACT
- ICE_AQC_SW_RULES_T_LKUP_RX
- ICE_AQC_SW_RULES_T_LKUP_TX
- ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR
- ICE_AQC_SW_RULES_T_PRUNE_LIST_SET
- ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR
- ICE_AQC_SW_RULES_T_VSI_LIST_SET
- ICE_AQC_TOPO_MAX_LEVEL_NUM
- ICE_AQ_AN_COMPLETED
- ICE_AQ_CFG_PACING_M
- ICE_AQ_CFG_PACING_S
- ICE_AQ_CFG_PACING_TYPE_AVG
- ICE_AQ_CFG_PACING_TYPE_FIXED
- ICE_AQ_CFG_PACING_TYPE_M
- ICE_AQ_FEC_EN
- ICE_AQ_FEC_MASK
- ICE_AQ_FLAG_BUF
- ICE_AQ_FLAG_BUF_S
- ICE_AQ_FLAG_ERR
- ICE_AQ_FLAG_ERR_S
- ICE_AQ_FLAG_LB
- ICE_AQ_FLAG_LB_S
- ICE_AQ_FLAG_RD
- ICE_AQ_FLAG_RD_S
- ICE_AQ_FLAG_SI
- ICE_AQ_FLAG_SI_S
- ICE_AQ_LEN
- ICE_AQ_LG_BUF
- ICE_AQ_LINK_25G_KR_FEC_EN
- ICE_AQ_LINK_25G_RS_528_FEC_EN
- ICE_AQ_LINK_25G_RS_544_FEC_EN
- ICE_AQ_LINK_EVENT_AN_COMPLETED
- ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS
- ICE_AQ_LINK_EVENT_LINK_FAULT
- ICE_AQ_LINK_EVENT_MEDIA_NA
- ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL
- ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM
- ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED
- ICE_AQ_LINK_EVENT_SIGNAL_DETECT
- ICE_AQ_LINK_EVENT_UPDOWN
- ICE_AQ_LINK_EXCESSIVE_ERRORS
- ICE_AQ_LINK_FAULT
- ICE_AQ_LINK_FAULT_REMOTE
- ICE_AQ_LINK_FAULT_RX
- ICE_AQ_LINK_FAULT_TX
- ICE_AQ_LINK_MEDIA_CONFLICT
- ICE_AQ_LINK_PAUSE_RX
- ICE_AQ_LINK_PAUSE_TX
- ICE_AQ_LINK_PHY_TEMP_ALARM
- ICE_AQ_LINK_PWR_BASET_HIGH
- ICE_AQ_LINK_PWR_BASET_LOW_HIGH
- ICE_AQ_LINK_PWR_QSFP_CLASS_1
- ICE_AQ_LINK_PWR_QSFP_CLASS_2
- ICE_AQ_LINK_PWR_QSFP_CLASS_3
- ICE_AQ_LINK_PWR_QSFP_CLASS_4
- ICE_AQ_LINK_SPEED_1000MB
- ICE_AQ_LINK_SPEED_100GB
- ICE_AQ_LINK_SPEED_100MB
- ICE_AQ_LINK_SPEED_10GB
- ICE_AQ_LINK_SPEED_10MB
- ICE_AQ_LINK_SPEED_20GB
- ICE_AQ_LINK_SPEED_2500MB
- ICE_AQ_LINK_SPEED_25GB
- ICE_AQ_LINK_SPEED_40GB
- ICE_AQ_LINK_SPEED_50GB
- ICE_AQ_LINK_SPEED_5GB
- ICE_AQ_LINK_SPEED_UNKNOWN
- ICE_AQ_LINK_TOPO_CONFLICT
- ICE_AQ_LINK_TOPO_CORRUPT
- ICE_AQ_LINK_TX_ACTIVE
- ICE_AQ_LINK_TX_DRAINED
- ICE_AQ_LINK_TX_FLUSHED
- ICE_AQ_LINK_TX_M
- ICE_AQ_LINK_TX_S
- ICE_AQ_LINK_UP
- ICE_AQ_LINK_UP_PORT
- ICE_AQ_LLDP_AGENT_PERSIST_DIS
- ICE_AQ_LLDP_AGENT_PERSIST_ENA
- ICE_AQ_LLDP_AGENT_SHUTDOWN
- ICE_AQ_LLDP_AGENT_START
- ICE_AQ_LLDP_AGENT_STATE_MASK
- ICE_AQ_LLDP_AGENT_STOP
- ICE_AQ_LLDP_BRID_TYPE_M
- ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID
- ICE_AQ_LLDP_BRID_TYPE_NON_TPMR
- ICE_AQ_LLDP_BRID_TYPE_S
- ICE_AQ_LLDP_MIB_LOCAL
- ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE
- ICE_AQ_LLDP_MIB_REMOTE
- ICE_AQ_LLDP_MIB_TYPE_M
- ICE_AQ_LLDP_MIB_TYPE_S
- ICE_AQ_LLDP_MIB_UPDATE_DIS
- ICE_AQ_LLDP_MIB_UPDATE_ENABLE
- ICE_AQ_LLDP_TX_ACTIVE
- ICE_AQ_LLDP_TX_FLUSHED
- ICE_AQ_LLDP_TX_M
- ICE_AQ_LLDP_TX_S
- ICE_AQ_LLDP_TX_SUSPENDED
- ICE_AQ_LP_AN_ABILITY
- ICE_AQ_LSE_DIS
- ICE_AQ_LSE_ENA
- ICE_AQ_LSE_IS_ENABLED
- ICE_AQ_LSE_M
- ICE_AQ_LSE_NOP
- ICE_AQ_MAC_LB_EN
- ICE_AQ_MAC_LB_OSC_CLK
- ICE_AQ_MAX_BUF_LEN
- ICE_AQ_MEDIA_AVAILABLE
- ICE_AQ_PD_FAULT
- ICE_AQ_PHY_ENA_AUTO_FEC
- ICE_AQ_PHY_ENA_AUTO_LINK_UPDT
- ICE_AQ_PHY_ENA_LESM
- ICE_AQ_PHY_ENA_LINK
- ICE_AQ_PHY_ENA_LOW_POWER
- ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY
- ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY
- ICE_AQ_PHY_ENA_VALID_MASK
- ICE_AQ_PHY_LOW_POWER
- ICE_AQ_PWR_CLASS_M
- ICE_AQ_QUALIFIED_MODULE
- ICE_AQ_RC_EBADBUF
- ICE_AQ_RC_EBADMAN
- ICE_AQ_RC_EBADSIG
- ICE_AQ_RC_EBUSY
- ICE_AQ_RC_EEXIST
- ICE_AQ_RC_ENOENT
- ICE_AQ_RC_ENOMEM
- ICE_AQ_RC_ENOSEC
- ICE_AQ_RC_ENOSPC
- ICE_AQ_RC_ENOSYS
- ICE_AQ_RC_EPERM
- ICE_AQ_RC_ESVN
- ICE_AQ_RC_OK
- ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS
- ICE_AQ_RES_GLBL_DONE
- ICE_AQ_RES_GLBL_IN_PROG
- ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS
- ICE_AQ_RES_GLBL_SUCCESS
- ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS
- ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS
- ICE_AQ_SET_MAC_FRAME_SIZE_MAX
- ICE_AQ_SIGNAL_DETECT
- ICE_AQ_VSI_FD_DEF_DROP
- ICE_AQ_VSI_FD_DEF_GRP_M
- ICE_AQ_VSI_FD_DEF_GRP_S
- ICE_AQ_VSI_FD_DEF_PRIORITY_M
- ICE_AQ_VSI_FD_DEF_PRIORITY_S
- ICE_AQ_VSI_FD_DEF_Q_M
- ICE_AQ_VSI_FD_DEF_Q_S
- ICE_AQ_VSI_FD_ENABLE
- ICE_AQ_VSI_FD_PROG_ENABLE
- ICE_AQ_VSI_FD_REPORT_Q_M
- ICE_AQ_VSI_FD_REPORT_Q_S
- ICE_AQ_VSI_FD_TX_AUTO_ENABLE
- ICE_AQ_VSI_IS_VALID
- ICE_AQ_VSI_KEEP_ALLOC
- ICE_AQ_VSI_NUM_M
- ICE_AQ_VSI_NUM_S
- ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST
- ICE_AQ_VSI_OUTER_TAG_COPY
- ICE_AQ_VSI_OUTER_TAG_INSERT
- ICE_AQ_VSI_OUTER_TAG_MODE_M
- ICE_AQ_VSI_OUTER_TAG_MODE_S
- ICE_AQ_VSI_OUTER_TAG_NONE
- ICE_AQ_VSI_OUTER_TAG_NOTHING
- ICE_AQ_VSI_OUTER_TAG_REMOVE
- ICE_AQ_VSI_OUTER_TAG_STAG
- ICE_AQ_VSI_OUTER_TAG_TYPE_M
- ICE_AQ_VSI_OUTER_TAG_TYPE_S
- ICE_AQ_VSI_OUTER_TAG_VLAN_8100
- ICE_AQ_VSI_OUTER_TAG_VLAN_9100
- ICE_AQ_VSI_PASID_ID_M
- ICE_AQ_VSI_PASID_ID_S
- ICE_AQ_VSI_PASID_ID_VALID
- ICE_AQ_VSI_PROP_EGRESS_UP_VALID
- ICE_AQ_VSI_PROP_FLOW_DIR_VALID
- ICE_AQ_VSI_PROP_INGRESS_UP_VALID
- ICE_AQ_VSI_PROP_OUTER_TAG_VALID
- ICE_AQ_VSI_PROP_OUTER_UP_VALID
- ICE_AQ_VSI_PROP_PASID_VALID
- ICE_AQ_VSI_PROP_Q_OPT_VALID
- ICE_AQ_VSI_PROP_RXQ_MAP_VALID
- ICE_AQ_VSI_PROP_SECURITY_VALID
- ICE_AQ_VSI_PROP_SW_VALID
- ICE_AQ_VSI_PROP_VLAN_VALID
- ICE_AQ_VSI_PVLAN_INSERT_PVID
- ICE_AQ_VSI_Q_M
- ICE_AQ_VSI_Q_MAP_CONTIG
- ICE_AQ_VSI_Q_MAP_NONCONTIG
- ICE_AQ_VSI_Q_OPT_PE_FLTR_EN
- ICE_AQ_VSI_Q_OPT_PROF_TC_OVR
- ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M
- ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S
- ICE_AQ_VSI_Q_OPT_RSS_HASH_M
- ICE_AQ_VSI_Q_OPT_RSS_HASH_S
- ICE_AQ_VSI_Q_OPT_RSS_JHASH
- ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL
- ICE_AQ_VSI_Q_OPT_RSS_LUT_M
- ICE_AQ_VSI_Q_OPT_RSS_LUT_PF
- ICE_AQ_VSI_Q_OPT_RSS_LUT_S
- ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI
- ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ
- ICE_AQ_VSI_Q_OPT_RSS_TPLZ
- ICE_AQ_VSI_Q_OPT_RSS_XOR
- ICE_AQ_VSI_Q_OPT_TC_OVR_M
- ICE_AQ_VSI_Q_OPT_TC_OVR_S
- ICE_AQ_VSI_Q_S
- ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD
- ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF
- ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M
- ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S
- ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA
- ICE_AQ_VSI_SW_FLAG_ALLOW_LB
- ICE_AQ_VSI_SW_FLAG_LAN_ENA
- ICE_AQ_VSI_SW_FLAG_LOCAL_LB
- ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M
- ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S
- ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA
- ICE_AQ_VSI_SW_FLAG_SRC_PRUNE
- ICE_AQ_VSI_SW_VEB_STAT_ID_M
- ICE_AQ_VSI_SW_VEB_STAT_ID_S
- ICE_AQ_VSI_SW_VEB_STAT_ID_VALID
- ICE_AQ_VSI_TC_Q_NUM_M
- ICE_AQ_VSI_TC_Q_NUM_S
- ICE_AQ_VSI_TC_Q_OFFSET_M
- ICE_AQ_VSI_TC_Q_OFFSET_S
- ICE_AQ_VSI_TYPE_EMP_MNG
- ICE_AQ_VSI_TYPE_M
- ICE_AQ_VSI_TYPE_PF
- ICE_AQ_VSI_TYPE_S
- ICE_AQ_VSI_TYPE_VF
- ICE_AQ_VSI_TYPE_VMDQ2
- ICE_AQ_VSI_UP_TABLE_UP0_M
- ICE_AQ_VSI_UP_TABLE_UP0_S
- ICE_AQ_VSI_UP_TABLE_UP1_M
- ICE_AQ_VSI_UP_TABLE_UP1_S
- ICE_AQ_VSI_UP_TABLE_UP2_M
- ICE_AQ_VSI_UP_TABLE_UP2_S
- ICE_AQ_VSI_UP_TABLE_UP3_M
- ICE_AQ_VSI_UP_TABLE_UP3_S
- ICE_AQ_VSI_UP_TABLE_UP4_M
- ICE_AQ_VSI_UP_TABLE_UP4_S
- ICE_AQ_VSI_UP_TABLE_UP5_M
- ICE_AQ_VSI_UP_TABLE_UP5_S
- ICE_AQ_VSI_UP_TABLE_UP6_M
- ICE_AQ_VSI_UP_TABLE_UP6_S
- ICE_AQ_VSI_UP_TABLE_UP7_M
- ICE_AQ_VSI_UP_TABLE_UP7_S
- ICE_AQ_VSI_VLAN_EMOD_M
- ICE_AQ_VSI_VLAN_EMOD_NOTHING
- ICE_AQ_VSI_VLAN_EMOD_S
- ICE_AQ_VSI_VLAN_EMOD_STR
- ICE_AQ_VSI_VLAN_EMOD_STR_BOTH
- ICE_AQ_VSI_VLAN_EMOD_STR_UP
- ICE_AQ_VSI_VLAN_MODE_ALL
- ICE_AQ_VSI_VLAN_MODE_M
- ICE_AQ_VSI_VLAN_MODE_S
- ICE_AQ_VSI_VLAN_MODE_TAGGED
- ICE_AQ_VSI_VLAN_MODE_UNTAGGED
- ICE_BAR0
- ICE_BLK_ACL
- ICE_BLK_COUNT
- ICE_BLK_FD
- ICE_BLK_PE
- ICE_BLK_RSS
- ICE_BLK_SW
- ICE_BOOST_BIT_FIELDS
- ICE_BOOST_REMAINING_HV_KEY
- ICE_BYTES_PER_DWORD
- ICE_BYTES_PER_WORD
- ICE_CACHE_LINE_BYTES
- ICE_CAPS_VALID_FUNCS_M
- ICE_CEE_APP_SELECTOR_M
- ICE_CEE_APP_SEL_ETHTYPE
- ICE_CEE_APP_SEL_TCPIP
- ICE_CEE_DCBX_OUI
- ICE_CEE_DCBX_TYPE
- ICE_CEE_FEAT_TLV_ENA_M
- ICE_CEE_FEAT_TLV_ERR_M
- ICE_CEE_FEAT_TLV_WILLING_M
- ICE_CEE_MAX_FEAT_TYPE
- ICE_CEE_PGID_PRIO_0_M
- ICE_CEE_PGID_PRIO_0_S
- ICE_CEE_PGID_PRIO_1_M
- ICE_CEE_PGID_PRIO_1_S
- ICE_CEE_PGID_STRICT
- ICE_CEE_SUBTYPE_APP_PRI
- ICE_CEE_SUBTYPE_PFC_CFG
- ICE_CEE_SUBTYPE_PG_CFG
- ICE_CHANGE_LOCK_RES_ID
- ICE_CHANGE_LOCK_TIMEOUT
- ICE_CQ_INIT_REGS
- ICE_CTL_Q_ADMIN
- ICE_CTL_Q_DESC
- ICE_CTL_Q_DESC_UNUSED
- ICE_CTL_Q_DETAILS
- ICE_CTL_Q_MAILBOX
- ICE_CTL_Q_SQ_CMD_TIMEOUT
- ICE_CTL_Q_SQ_CMD_USEC
- ICE_CTL_Q_UNKNOWN
- ICE_CTX_STORE
- ICE_DBG_AQ_CMD
- ICE_DBG_AQ_MSG
- ICE_DBG_FW_LOG
- ICE_DBG_INIT
- ICE_DBG_LAN
- ICE_DBG_LINK
- ICE_DBG_NVM
- ICE_DBG_PHY
- ICE_DBG_PKG
- ICE_DBG_QCTX
- ICE_DBG_RES
- ICE_DBG_SCHED
- ICE_DBG_SW
- ICE_DBG_USER
- ICE_DCBX_APPS_NON_WILLING
- ICE_DCBX_MAX_APPS
- ICE_DCBX_MODE_CEE
- ICE_DCBX_MODE_IEEE
- ICE_DCBX_STATUS_DIS
- ICE_DCBX_STATUS_DONE
- ICE_DCBX_STATUS_IN_PROGRESS
- ICE_DCBX_STATUS_NOT_STARTED
- ICE_DDP_PKG_FILE
- ICE_DDP_PKG_PATH
- ICE_DEFAULT_PTG
- ICE_DEFAULT_VSIG
- ICE_DESCS_FOR_CTX_DESC
- ICE_DESCS_FOR_SKB_DATA_PTR
- ICE_DESCS_PER_CACHE_LINE
- ICE_DESC_UNUSED
- ICE_DEV_ID_E810C_BACKPLANE
- ICE_DEV_ID_E810C_QSFP
- ICE_DEV_ID_E810C_SFP
- ICE_DFLT_INTRL
- ICE_DFLT_INTR_PER_VF
- ICE_DFLT_IRQ_WORK
- ICE_DFLT_MIN_RX_DESC
- ICE_DFLT_NETIF_M
- ICE_DFLT_NUM_INVAL_MSGS_ALLOWED
- ICE_DFLT_NUM_RX_DESC
- ICE_DFLT_NUM_TX_DESC
- ICE_DFLT_QS_PER_VF
- ICE_DFLT_RX_ITR
- ICE_DFLT_TRAFFIC_CLASS
- ICE_DFLT_TX_ITR
- ICE_DFLT_VSI_INVAL
- ICE_DROP_PACKET
- ICE_EEP1_AC97_MAIN_HI
- ICE_EEP1_AC97_MAIN_LO
- ICE_EEP1_AC97_PCM_HI
- ICE_EEP1_AC97_PCM_LO
- ICE_EEP1_AC97_RECSRC
- ICE_EEP1_AC97_REC_HI
- ICE_EEP1_AC97_REC_LO
- ICE_EEP1_ACLINK
- ICE_EEP1_ADC_ID
- ICE_EEP1_ADC_ID1
- ICE_EEP1_ADC_ID2
- ICE_EEP1_ADC_ID3
- ICE_EEP1_CODEC
- ICE_EEP1_DAC_ID
- ICE_EEP1_DAC_ID1
- ICE_EEP1_DAC_ID2
- ICE_EEP1_DAC_ID3
- ICE_EEP1_GPIO_DIR
- ICE_EEP1_GPIO_MASK
- ICE_EEP1_GPIO_STATE
- ICE_EEP1_I2SID
- ICE_EEP1_SPDIF
- ICE_EEP2_ACLINK
- ICE_EEP2_GPIO_DIR
- ICE_EEP2_GPIO_DIR1
- ICE_EEP2_GPIO_DIR2
- ICE_EEP2_GPIO_MASK
- ICE_EEP2_GPIO_MASK1
- ICE_EEP2_GPIO_MASK2
- ICE_EEP2_GPIO_STATE
- ICE_EEP2_GPIO_STATE1
- ICE_EEP2_GPIO_STATE2
- ICE_EEP2_I2S
- ICE_EEP2_SPDIF
- ICE_EEP2_SYSCONF
- ICE_ERR_ALREADY_EXISTS
- ICE_ERR_AQ_EMPTY
- ICE_ERR_AQ_ERROR
- ICE_ERR_AQ_FULL
- ICE_ERR_AQ_NO_WORK
- ICE_ERR_AQ_TIMEOUT
- ICE_ERR_BAD_PTR
- ICE_ERR_BUF_TOO_SHORT
- ICE_ERR_CFG
- ICE_ERR_DEVICE_NOT_SUPPORTED
- ICE_ERR_DOES_NOT_EXIST
- ICE_ERR_FW_API_VER
- ICE_ERR_INVAL_SIZE
- ICE_ERR_IN_USE
- ICE_ERR_MAX_LIMIT
- ICE_ERR_NOT_IMPL
- ICE_ERR_NOT_READY
- ICE_ERR_NOT_SUPPORTED
- ICE_ERR_NO_MEMORY
- ICE_ERR_NVM_BLANK_MODE
- ICE_ERR_NVM_CHECKSUM
- ICE_ERR_OUT_OF_RANGE
- ICE_ERR_PARAM
- ICE_ERR_RESET_FAILED
- ICE_ERR_RESET_ONGOING
- ICE_ETH_DA_OFFSET
- ICE_ETH_ETHTYPE_OFFSET
- ICE_ETH_TEST_EEPROM
- ICE_ETH_TEST_INTR
- ICE_ETH_TEST_LINK
- ICE_ETH_TEST_LOOP
- ICE_ETH_TEST_REG
- ICE_ETH_VLAN_TCI_OFFSET
- ICE_FC_DFLT
- ICE_FC_FULL
- ICE_FC_NONE
- ICE_FC_PFC
- ICE_FC_RX_PAUSE
- ICE_FC_TX_PAUSE
- ICE_FEC_AUTO
- ICE_FEC_BASER
- ICE_FEC_NONE
- ICE_FEC_RS
- ICE_FLAG_ADV_FEATURES
- ICE_FLAG_DCB_CAPABLE
- ICE_FLAG_DCB_ENA
- ICE_FLAG_ETHTOOL_CTXT
- ICE_FLAG_FLTR_SYNC
- ICE_FLAG_FW_LLDP_AGENT
- ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA
- ICE_FLAG_NO_MEDIA
- ICE_FLAG_RSS_ENA
- ICE_FLAG_SRIOV_CAPABLE
- ICE_FLAG_SRIOV_ENA
- ICE_FLG_EVLAN_x8100
- ICE_FLG_EVLAN_x9100
- ICE_FLG_FIN
- ICE_FLG_PKT_DSI
- ICE_FLG_PKT_FRG
- ICE_FLG_RST
- ICE_FLG_RSVD
- ICE_FLG_SYN
- ICE_FLG_TNL0
- ICE_FLG_TNL1
- ICE_FLG_TNL2
- ICE_FLG_TNL_MAC
- ICE_FLG_TNL_VLAN
- ICE_FLG_UDP_GRE
- ICE_FLG_VLAN_x8100
- ICE_FLTR_RX
- ICE_FLTR_TX
- ICE_FLTR_TX_RX
- ICE_FREE_CQ_BUFS
- ICE_FWD_TO_Q
- ICE_FWD_TO_QGRP
- ICE_FWD_TO_VSI
- ICE_FWD_TO_VSI_LIST
- ICE_FW_LOG_DESC_SIZE
- ICE_FW_LOG_DESC_SIZE_MAX
- ICE_FW_LOG_EVNT_ERR
- ICE_FW_LOG_EVNT_FLOW
- ICE_FW_LOG_EVNT_INFO
- ICE_FW_LOG_EVNT_INIT
- ICE_GET_CAP_BUF_COUNT
- ICE_GET_CAP_RETRY_COUNT
- ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE
- ICE_GLINT_DYN_CTL_WB_ON_ITR
- ICE_GLOBAL_CFG_LOCK_RES_ID
- ICE_GLOBAL_CFG_LOCK_TIMEOUT
- ICE_I2C_EEPROM_ADDR
- ICE_IDX_ITR0
- ICE_IDX_ITR1
- ICE_IDX_ITR2
- ICE_IEEE_8021QAZ_OUI
- ICE_IEEE_APP_PRIO_M
- ICE_IEEE_APP_PRIO_S
- ICE_IEEE_APP_SEL_M
- ICE_IEEE_APP_SEL_S
- ICE_IEEE_APP_TLV_LEN
- ICE_IEEE_ETS_CBS_M
- ICE_IEEE_ETS_CBS_S
- ICE_IEEE_ETS_MAXTC_M
- ICE_IEEE_ETS_MAXTC_S
- ICE_IEEE_ETS_PRIO_0_M
- ICE_IEEE_ETS_PRIO_0_S
- ICE_IEEE_ETS_PRIO_1_M
- ICE_IEEE_ETS_PRIO_1_S
- ICE_IEEE_ETS_TLV_LEN
- ICE_IEEE_ETS_WILLING_M
- ICE_IEEE_ETS_WILLING_S
- ICE_IEEE_PFC_CAP_M
- ICE_IEEE_PFC_CAP_S
- ICE_IEEE_PFC_MBC_M
- ICE_IEEE_PFC_MBC_S
- ICE_IEEE_PFC_TLV_LEN
- ICE_IEEE_PFC_WILLING_M
- ICE_IEEE_PFC_WILLING_S
- ICE_IEEE_SUBTYPE_APP_PRI
- ICE_IEEE_SUBTYPE_ETS_CFG
- ICE_IEEE_SUBTYPE_ETS_REC
- ICE_IEEE_SUBTYPE_PFC_CFG
- ICE_IEEE_TLV_ID_APP_PRI
- ICE_IEEE_TLV_ID_ETS_CFG
- ICE_IEEE_TLV_ID_ETS_REC
- ICE_IEEE_TLV_ID_PFC_CFG
- ICE_IEEE_TSA_ETS
- ICE_IEEE_TSA_STRICT
- ICE_INTRL_GRAN_ABOVE_25
- ICE_INTRL_GRAN_MAX_25
- ICE_INT_NAME_STR_LEN
- ICE_INVAL_ACT
- ICE_INVAL_COUNTER_ID
- ICE_INVAL_LG_ACT_INDEX
- ICE_INVAL_Q_HANDLE
- ICE_INVAL_Q_INDEX
- ICE_INVAL_SW_MARKER_ID
- ICE_INVAL_TEID
- ICE_INVAL_VFID
- ICE_IN_WB_ON_ITR_MODE
- ICE_ITR_20K
- ICE_ITR_8K
- ICE_ITR_ADAPTIVE_BULK
- ICE_ITR_ADAPTIVE_LATENCY
- ICE_ITR_ADAPTIVE_MAX_USECS
- ICE_ITR_ADAPTIVE_MIN_INC
- ICE_ITR_ADAPTIVE_MIN_USECS
- ICE_ITR_DYNAMIC
- ICE_ITR_GRAN_ABOVE_25
- ICE_ITR_GRAN_MAX_25
- ICE_ITR_GRAN_S
- ICE_ITR_GRAN_US
- ICE_ITR_MASK
- ICE_ITR_MAX
- ICE_ITR_NONE
- ICE_LAN_TXQ_MAX_QDIS
- ICE_LAN_TXQ_MAX_QGRPS
- ICE_LB_FRAME_SIZE
- ICE_LG_ACT_EGRESS
- ICE_LG_ACT_GENERIC
- ICE_LG_ACT_GENERIC_OFFSET_M
- ICE_LG_ACT_GENERIC_OFFSET_S
- ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX
- ICE_LG_ACT_GENERIC_PRIORITY_M
- ICE_LG_ACT_GENERIC_PRIORITY_S
- ICE_LG_ACT_GENERIC_VALUE_M
- ICE_LG_ACT_GENERIC_VALUE_S
- ICE_LG_ACT_INGRESS
- ICE_LG_ACT_MIRROR_VSI_ID_M
- ICE_LG_ACT_MIRROR_VSI_ID_S
- ICE_LG_ACT_PRUNE
- ICE_LG_ACT_PRUNET
- ICE_LG_ACT_Q_INDEX_M
- ICE_LG_ACT_Q_INDEX_S
- ICE_LG_ACT_Q_PRIORITY_SET
- ICE_LG_ACT_Q_REGION_M
- ICE_LG_ACT_Q_REGION_S
- ICE_LG_ACT_STAT_COUNT
- ICE_LG_ACT_STAT_COUNT_M
- ICE_LG_ACT_STAT_COUNT_S
- ICE_LG_ACT_TO_Q
- ICE_LG_ACT_TYPE_M
- ICE_LG_ACT_TYPE_S
- ICE_LG_ACT_VALID_BIT
- ICE_LG_ACT_VSI_FORWARDING
- ICE_LG_ACT_VSI_ID_M
- ICE_LG_ACT_VSI_ID_S
- ICE_LG_ACT_VSI_LIST
- ICE_LG_ACT_VSI_LIST_ID_M
- ICE_LG_ACT_VSI_LIST_ID_S
- ICE_LG_OTHER_ACT_MIRROR
- ICE_LINK_SPEED_100000MBPS
- ICE_LINK_SPEED_10000MBPS
- ICE_LINK_SPEED_1000MBPS
- ICE_LINK_SPEED_100MBPS
- ICE_LINK_SPEED_10MBPS
- ICE_LINK_SPEED_20000MBPS
- ICE_LINK_SPEED_25000MBPS
- ICE_LINK_SPEED_2500MBPS
- ICE_LINK_SPEED_40000MBPS
- ICE_LINK_SPEED_50000MBPS
- ICE_LINK_SPEED_5000MBPS
- ICE_LINK_SPEED_UNKNOWN
- ICE_LLDPDU_SIZE
- ICE_LLDP_TLV_LEN_M
- ICE_LLDP_TLV_LEN_S
- ICE_LLDP_TLV_OUI_M
- ICE_LLDP_TLV_OUI_S
- ICE_LLDP_TLV_SUBTYPE_M
- ICE_LLDP_TLV_SUBTYPE_S
- ICE_LLDP_TLV_TYPE_M
- ICE_LLDP_TLV_TYPE_S
- ICE_LPORT_MASK
- ICE_M
- ICE_MAC_GENERIC
- ICE_MAC_UNKNOWN
- ICE_MAIN_VSI_HANDLE
- ICE_MASK
- ICE_MAX_AGG_BW_100G
- ICE_MAX_AGG_BW_200G
- ICE_MAX_AGG_BW_25G
- ICE_MAX_AGG_BW_50G
- ICE_MAX_BASE_QS_PER_VF
- ICE_MAX_BST_TCAMS_IN_BUF
- ICE_MAX_BUF_TXD
- ICE_MAX_CHAINED_RX_BUFS
- ICE_MAX_DATA_PER_TXD
- ICE_MAX_DATA_PER_TXD_ALIGNED
- ICE_MAX_ENTRIES_IN_BUF
- ICE_MAX_FUNCS
- ICE_MAX_FV_WORDS
- ICE_MAX_INTRL
- ICE_MAX_INTR_PER_VF
- ICE_MAX_LABELS_IN_BUF
- ICE_MAX_LG_ACT
- ICE_MAX_LG_RSS_QS
- ICE_MAX_MACADDR_PER_VF
- ICE_MAX_MTU
- ICE_MAX_NUM_DESC
- ICE_MAX_NUM_RECIPES
- ICE_MAX_POLICY_INTR_PER_VF
- ICE_MAX_PTGS
- ICE_MAX_QS_PER_VF
- ICE_MAX_READ_REQ_SIZE
- ICE_MAX_RESET_WAIT
- ICE_MAX_SCATTER_QS_PER_VF
- ICE_MAX_SCATTER_RXQS
- ICE_MAX_SCATTER_TXQS
- ICE_MAX_SMALL_RSS_QS
- ICE_MAX_S_COUNT
- ICE_MAX_S_DATA_END
- ICE_MAX_S_OFF
- ICE_MAX_S_SZ
- ICE_MAX_TRAFFIC_CLASS
- ICE_MAX_TXQ_PER_TXQG
- ICE_MAX_USER_PRIORITY
- ICE_MAX_VF_COUNT
- ICE_MAX_VLANID
- ICE_MAX_VLAN_ID
- ICE_MAX_VLAN_PER_VF
- ICE_MAX_VSI
- ICE_MAX_VSIGS
- ICE_MBXQ_MAX_BUF_LEN
- ICE_MBXRQ_LEN
- ICE_MBXSQ_LEN
- ICE_MCAST_PROMISC_BITS
- ICE_MCAST_VLAN_PROMISC_BITS
- ICE_MDD_EVENTS_THRESHOLD
- ICE_MEDIA_BACKPLANE
- ICE_MEDIA_BASET
- ICE_MEDIA_DA
- ICE_MEDIA_FIBER
- ICE_MEDIA_UNKNOWN
- ICE_METADATA_BUF
- ICE_MIN_INTR_PER_VF
- ICE_MIN_LAN_VECS
- ICE_MIN_MSIX
- ICE_MIN_NUM_DESC
- ICE_MIN_QS_PER_VF
- ICE_MIN_S_COUNT
- ICE_MIN_S_DATA_END
- ICE_MIN_S_OFF
- ICE_MIN_S_SZ
- ICE_MIN_TX_LEN
- ICE_MODULE_TYPE_TOTAL_BYTE
- ICE_NONQ_VECS_VF
- ICE_NO_RESET
- ICE_NO_VSI
- ICE_NVM_RES_ID
- ICE_NVM_TIMEOUT
- ICE_NVM_VER_HI_MASK
- ICE_NVM_VER_HI_SHIFT
- ICE_NVM_VER_LEN
- ICE_NVM_VER_LO_MASK
- ICE_NVM_VER_LO_SHIFT
- ICE_OEM_VER_BUILD_MASK
- ICE_OEM_VER_BUILD_SHIFT
- ICE_OEM_VER_MASK
- ICE_OEM_VER_PATCH_MASK
- ICE_OEM_VER_PATCH_SHIFT
- ICE_OEM_VER_SHIFT
- ICE_PCI_CIAD_WAIT_COUNT
- ICE_PCI_CIAD_WAIT_DELAY_US
- ICE_PFC_STATS_LEN
- ICE_PF_FLAGS_NBITS
- ICE_PF_NUM_M
- ICE_PF_NUM_S
- ICE_PF_RESET_WAIT_COUNT
- ICE_PF_STAT
- ICE_PF_STATS_LEN
- ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4
- ICE_PHY_TYPE_HIGH_100G_AUI2
- ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC
- ICE_PHY_TYPE_HIGH_100G_CAUI2
- ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC
- ICE_PHY_TYPE_HIGH_MAX_INDEX
- ICE_PHY_TYPE_LOW_1000BASE_KX
- ICE_PHY_TYPE_LOW_1000BASE_LX
- ICE_PHY_TYPE_LOW_1000BASE_SX
- ICE_PHY_TYPE_LOW_1000BASE_T
- ICE_PHY_TYPE_LOW_100BASE_TX
- ICE_PHY_TYPE_LOW_100GBASE_CP2
- ICE_PHY_TYPE_LOW_100GBASE_CR4
- ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4
- ICE_PHY_TYPE_LOW_100GBASE_DR
- ICE_PHY_TYPE_LOW_100GBASE_KR4
- ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4
- ICE_PHY_TYPE_LOW_100GBASE_LR4
- ICE_PHY_TYPE_LOW_100GBASE_SR2
- ICE_PHY_TYPE_LOW_100GBASE_SR4
- ICE_PHY_TYPE_LOW_100G_AUI4
- ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC
- ICE_PHY_TYPE_LOW_100G_CAUI4
- ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC
- ICE_PHY_TYPE_LOW_100M_SGMII
- ICE_PHY_TYPE_LOW_10GBASE_KR_CR1
- ICE_PHY_TYPE_LOW_10GBASE_LR
- ICE_PHY_TYPE_LOW_10GBASE_SR
- ICE_PHY_TYPE_LOW_10GBASE_T
- ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC
- ICE_PHY_TYPE_LOW_10G_SFI_C2C
- ICE_PHY_TYPE_LOW_10G_SFI_DA
- ICE_PHY_TYPE_LOW_1G_SGMII
- ICE_PHY_TYPE_LOW_2500BASE_KX
- ICE_PHY_TYPE_LOW_2500BASE_T
- ICE_PHY_TYPE_LOW_2500BASE_X
- ICE_PHY_TYPE_LOW_25GBASE_CR
- ICE_PHY_TYPE_LOW_25GBASE_CR1
- ICE_PHY_TYPE_LOW_25GBASE_CR_S
- ICE_PHY_TYPE_LOW_25GBASE_KR
- ICE_PHY_TYPE_LOW_25GBASE_KR1
- ICE_PHY_TYPE_LOW_25GBASE_KR_S
- ICE_PHY_TYPE_LOW_25GBASE_LR
- ICE_PHY_TYPE_LOW_25GBASE_SR
- ICE_PHY_TYPE_LOW_25GBASE_T
- ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC
- ICE_PHY_TYPE_LOW_25G_AUI_C2C
- ICE_PHY_TYPE_LOW_40GBASE_CR4
- ICE_PHY_TYPE_LOW_40GBASE_KR4
- ICE_PHY_TYPE_LOW_40GBASE_LR4
- ICE_PHY_TYPE_LOW_40GBASE_SR4
- ICE_PHY_TYPE_LOW_40G_XLAUI
- ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC
- ICE_PHY_TYPE_LOW_50GBASE_CP
- ICE_PHY_TYPE_LOW_50GBASE_CR2
- ICE_PHY_TYPE_LOW_50GBASE_FR
- ICE_PHY_TYPE_LOW_50GBASE_KR2
- ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4
- ICE_PHY_TYPE_LOW_50GBASE_LR
- ICE_PHY_TYPE_LOW_50GBASE_LR2
- ICE_PHY_TYPE_LOW_50GBASE_SR
- ICE_PHY_TYPE_LOW_50GBASE_SR2
- ICE_PHY_TYPE_LOW_50G_AUI1
- ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC
- ICE_PHY_TYPE_LOW_50G_AUI2
- ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC
- ICE_PHY_TYPE_LOW_50G_LAUI2
- ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC
- ICE_PHY_TYPE_LOW_5GBASE_KR
- ICE_PHY_TYPE_LOW_5GBASE_T
- ICE_PHY_TYPE_LOW_MAX_INDEX
- ICE_PKG_BUF_SIZE
- ICE_PKG_CNT
- ICE_PKG_FLAG_COUNT
- ICE_PKG_FMT_VER_DFT
- ICE_PKG_FMT_VER_MAJ
- ICE_PKG_FMT_VER_MNR
- ICE_PKG_FMT_VER_UPD
- ICE_PKG_LABEL_SIZE
- ICE_PKG_NAME_SIZE
- ICE_PKG_SUPP_VER_MAJ
- ICE_PKG_SUPP_VER_MNR
- ICE_PRIORITY_M
- ICE_PRIV_FLAG
- ICE_PRIV_FLAG_ARRAY_SIZE
- ICE_PROG_FLEX_ENTRY
- ICE_PROG_FLG_ENTRY
- ICE_PROMISC_BCAST_RX
- ICE_PROMISC_BCAST_TX
- ICE_PROMISC_MCAST_RX
- ICE_PROMISC_MCAST_TX
- ICE_PROMISC_UCAST_RX
- ICE_PROMISC_UCAST_TX
- ICE_PROMISC_VLAN_RX
- ICE_PROMISC_VLAN_TX
- ICE_PTT
- ICE_PTT_UNUSED_ENTRY
- ICE_QGRP_LAYER_OFFSET
- ICE_Q_WAIT_MAX_RETRY
- ICE_Q_WAIT_RETRY_LIMIT
- ICE_REQ_DESC_MULTIPLE
- ICE_RESET_CORER
- ICE_RESET_DONE_MASK
- ICE_RESET_EMPR
- ICE_RESET_GLOBR
- ICE_RESET_INVAL
- ICE_RESET_PFR
- ICE_RESET_POR
- ICE_RES_MISC_VEC_ID
- ICE_RES_POLLING_DELAY_MS
- ICE_RES_READ
- ICE_RES_VALID_BIT
- ICE_RES_WRITE
- ICE_RLAN_BASE_S
- ICE_RLAN_CTX_DBUF_S
- ICE_RLAN_CTX_HBUF_S
- ICE_RLAN_RX_HSPLIT_0_NO_SPLIT
- ICE_RLAN_RX_HSPLIT_0_SPLIT_IP
- ICE_RLAN_RX_HSPLIT_0_SPLIT_L2
- ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP
- ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP
- ICE_RLAN_RX_HSPLIT_1_NO_SPLIT
- ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS
- ICE_RLAN_RX_HSPLIT_1_SPLIT_L2
- ICE_RXBUF_2048
- ICE_RXDID_FLEX_NIC
- ICE_RXDID_FLEX_NIC_2
- ICE_RXDID_HW
- ICE_RXDID_LAST
- ICE_RXDID_LEGACY_0
- ICE_RXDID_LEGACY_1
- ICE_RXD_EOF
- ICE_RXQ_CTX_SIZE_DWORDS
- ICE_RXQ_CTX_SZ
- ICE_RX_BUF_WRITE
- ICE_RX_CONTAINER
- ICE_RX_DESC
- ICE_RX_DMA_ATTR
- ICE_RX_DTYPE_HEADER_SPLIT
- ICE_RX_DTYPE_NO_SPLIT
- ICE_RX_DTYPE_SPLIT_ALWAYS
- ICE_RX_FLEX_DESC_PTYPE_M
- ICE_RX_FLEX_DESC_STATUS0_CRCP_S
- ICE_RX_FLEX_DESC_STATUS0_DD_S
- ICE_RX_FLEX_DESC_STATUS0_EOF_S
- ICE_RX_FLEX_DESC_STATUS0_HBO_S
- ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S
- ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S
- ICE_RX_FLEX_DESC_STATUS0_L3L4P_S
- ICE_RX_FLEX_DESC_STATUS0_LAST
- ICE_RX_FLEX_DESC_STATUS0_LPBK_S
- ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S
- ICE_RX_FLEX_DESC_STATUS0_RXE_S
- ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S
- ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S
- ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S
- ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S
- ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S
- ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S
- ICE_RX_FLX_DESC_PKT_LEN_M
- ICE_RX_HDR_SIZE
- ICE_RX_ITR
- ICE_RX_MDID_FLOW_ID_HIGH
- ICE_RX_MDID_FLOW_ID_LOWER
- ICE_RX_MDID_HASH_HIGH
- ICE_RX_MDID_HASH_LOW
- ICE_RX_MDID_SRC_VSI
- ICE_RX_OPC_MDID
- ICE_RX_PTYPE_FRAG
- ICE_RX_PTYPE_INNER_PROT_ICMP
- ICE_RX_PTYPE_INNER_PROT_NONE
- ICE_RX_PTYPE_INNER_PROT_SCTP
- ICE_RX_PTYPE_INNER_PROT_TCP
- ICE_RX_PTYPE_INNER_PROT_TIMESYNC
- ICE_RX_PTYPE_INNER_PROT_UDP
- ICE_RX_PTYPE_NOF
- ICE_RX_PTYPE_NOT_FRAG
- ICE_RX_PTYPE_OUTER_IP
- ICE_RX_PTYPE_OUTER_IPV4
- ICE_RX_PTYPE_OUTER_IPV6
- ICE_RX_PTYPE_OUTER_L2
- ICE_RX_PTYPE_OUTER_NONE
- ICE_RX_PTYPE_PAYLOAD_LAYER_NONE
- ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2
- ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3
- ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4
- ICE_RX_PTYPE_TUNNEL_END_IPV4
- ICE_RX_PTYPE_TUNNEL_END_IPV6
- ICE_RX_PTYPE_TUNNEL_END_NONE
- ICE_RX_PTYPE_TUNNEL_IP_GRENAT
- ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC
- ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN
- ICE_RX_PTYPE_TUNNEL_IP_IP
- ICE_RX_PTYPE_TUNNEL_NONE
- ICE_SCHED_DFLT_BW_WT
- ICE_SCHED_DFLT_RL_PROF_ID
- ICE_SCHED_NODE_OWNER_LAN
- ICE_SCHED_PORT_STATE_INIT
- ICE_SCHED_PORT_STATE_READY
- ICE_SET_FC_AQ_FAIL_GET
- ICE_SET_FC_AQ_FAIL_NONE
- ICE_SET_FC_AQ_FAIL_SET
- ICE_SET_FC_AQ_FAIL_UPDATE
- ICE_SID_ES_OFF
- ICE_SID_FLD_VEC_ACL
- ICE_SID_FLD_VEC_FD
- ICE_SID_FLD_VEC_PE
- ICE_SID_FLD_VEC_RSS
- ICE_SID_FLD_VEC_SW
- ICE_SID_LBL_FIRST
- ICE_SID_LBL_LAST
- ICE_SID_LBL_RXPARSER_TMEM
- ICE_SID_OFF_COUNT
- ICE_SID_PROFID_REDIR_ACL
- ICE_SID_PROFID_REDIR_FD
- ICE_SID_PROFID_REDIR_PE
- ICE_SID_PROFID_REDIR_RSS
- ICE_SID_PROFID_REDIR_SW
- ICE_SID_PROFID_TCAM_ACL
- ICE_SID_PROFID_TCAM_FD
- ICE_SID_PROFID_TCAM_PE
- ICE_SID_PROFID_TCAM_RSS
- ICE_SID_PROFID_TCAM_SW
- ICE_SID_PR_OFF
- ICE_SID_PR_REDIR_OFF
- ICE_SID_RXPARSER_BOOST_TCAM
- ICE_SID_XLT1_ACL
- ICE_SID_XLT1_FD
- ICE_SID_XLT1_OFF
- ICE_SID_XLT1_PE
- ICE_SID_XLT1_RSS
- ICE_SID_XLT1_SW
- ICE_SID_XLT2_ACL
- ICE_SID_XLT2_FD
- ICE_SID_XLT2_OFF
- ICE_SID_XLT2_PE
- ICE_SID_XLT2_RSS
- ICE_SID_XLT2_SW
- ICE_SINGLE_ACT_DROP
- ICE_SINGLE_ACT_EGRESS
- ICE_SINGLE_ACT_INGRESS
- ICE_SINGLE_ACT_LAN_ENABLE
- ICE_SINGLE_ACT_LB_ENABLE
- ICE_SINGLE_ACT_MIRROR_VSI_ID_M
- ICE_SINGLE_ACT_MIRROR_VSI_ID_S
- ICE_SINGLE_ACT_OTHER_ACTS
- ICE_SINGLE_ACT_PRUNE
- ICE_SINGLE_ACT_PRUNET
- ICE_SINGLE_ACT_PTR
- ICE_SINGLE_ACT_PTR_BIT
- ICE_SINGLE_ACT_PTR_VAL_M
- ICE_SINGLE_ACT_PTR_VAL_S
- ICE_SINGLE_ACT_Q_INDEX_M
- ICE_SINGLE_ACT_Q_INDEX_S
- ICE_SINGLE_ACT_Q_PRIORITY
- ICE_SINGLE_ACT_Q_REGION_M
- ICE_SINGLE_ACT_Q_REGION_S
- ICE_SINGLE_ACT_STAT_COUNT_INDEX_M
- ICE_SINGLE_ACT_STAT_COUNT_INDEX_S
- ICE_SINGLE_ACT_TO_Q
- ICE_SINGLE_ACT_TYPE_M
- ICE_SINGLE_ACT_TYPE_S
- ICE_SINGLE_ACT_VALID_BIT
- ICE_SINGLE_ACT_VSI_FORWARDING
- ICE_SINGLE_ACT_VSI_ID_M
- ICE_SINGLE_ACT_VSI_ID_S
- ICE_SINGLE_ACT_VSI_LIST
- ICE_SINGLE_ACT_VSI_LIST_ID_M
- ICE_SINGLE_ACT_VSI_LIST_ID_S
- ICE_SINGLE_OTHER_ACT_IDENTIFIER_M
- ICE_SINGLE_OTHER_ACT_IDENTIFIER_S
- ICE_SINGLE_OTHER_ACT_MIRROR
- ICE_SINGLE_OTHER_ACT_STAT_COUNT
- ICE_SPD_RES_ID
- ICE_SRC_ID_LPORT
- ICE_SRC_ID_QUEUE
- ICE_SRC_ID_UNKNOWN
- ICE_SRC_ID_VSI
- ICE_SR_NVM_DEV_STARTER_VER
- ICE_SR_NVM_EETRACK_HI
- ICE_SR_NVM_EETRACK_LO
- ICE_SR_SECTOR_SIZE_IN_WORDS
- ICE_SR_WORDS_IN_1KB
- ICE_STAT
- ICE_SUCCESS
- ICE_SW_BLK_IDX
- ICE_SW_BLK_INP_MASK_H
- ICE_SW_BLK_INP_MASK_L
- ICE_SW_CFG_MAX_BUF_LEN
- ICE_SW_LKUP_DFLT
- ICE_SW_LKUP_ETHERTYPE
- ICE_SW_LKUP_ETHERTYPE_MAC
- ICE_SW_LKUP_LAST
- ICE_SW_LKUP_MAC
- ICE_SW_LKUP_MAC_VLAN
- ICE_SW_LKUP_PROMISC
- ICE_SW_LKUP_PROMISC_VLAN
- ICE_SW_LKUP_VLAN
- ICE_SW_RECIPE_LOGICAL_PORT_FWD
- ICE_SW_RULE_LG_ACT_SIZE
- ICE_SW_RULE_RX_TX_ETH_HDR_SIZE
- ICE_SW_RULE_RX_TX_NO_HDR_SIZE
- ICE_SW_RULE_VSI_LIST_SIZE
- ICE_TCAM_KEY_SZ
- ICE_TCAM_KEY_VAL_SZ
- ICE_TC_MAX_BW
- ICE_TC_NODE_PRIO_S
- ICE_TEST_LEN
- ICE_TLAN_CTX_BASE_S
- ICE_TLAN_CTX_VMVF_TYPE_PF
- ICE_TLAN_CTX_VMVF_TYPE_VF
- ICE_TLAN_CTX_VMVF_TYPE_VMQ
- ICE_TLV_ID_END_OF_LLDPPDU
- ICE_TLV_ID_START
- ICE_TLV_STATUS_ERR
- ICE_TLV_STATUS_OPER
- ICE_TLV_STATUS_SYNC
- ICE_TLV_TYPE_END
- ICE_TLV_TYPE_ORG
- ICE_TXD_CTX_QW1_CMD_M
- ICE_TXD_CTX_QW1_CMD_S
- ICE_TXD_CTX_QW1_MSS_S
- ICE_TXD_CTX_QW1_TSO_LEN_M
- ICE_TXD_CTX_QW1_TSO_LEN_S
- ICE_TXD_IPLEN_MAX
- ICE_TXD_L4LEN_MAX
- ICE_TXD_MACLEN_MAX
- ICE_TXD_QW1_CMD_M
- ICE_TXD_QW1_CMD_S
- ICE_TXD_QW1_IPLEN_M
- ICE_TXD_QW1_L2TAG1_S
- ICE_TXD_QW1_L4LEN_M
- ICE_TXD_QW1_MACLEN_M
- ICE_TXD_QW1_OFFSET_M
- ICE_TXD_QW1_OFFSET_S
- ICE_TXD_QW1_TX_BUF_SZ_S
- ICE_TXSCHED_GET_NODE_TEID
- ICE_TXSCHED_MAX_BRANCHES
- ICE_TX_ADVANCED
- ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS
- ICE_TX_CONTAINER
- ICE_TX_CTX_DESC
- ICE_TX_CTX_DESC_IL2TAG2
- ICE_TX_CTX_DESC_IL2TAG2_IL2H
- ICE_TX_CTX_DESC_RESERVED
- ICE_TX_CTX_DESC_SWTCH_LOCAL
- ICE_TX_CTX_DESC_SWTCH_NOTAG
- ICE_TX_CTX_DESC_SWTCH_UPLINK
- ICE_TX_CTX_DESC_SWTCH_VSI
- ICE_TX_CTX_DESC_TSO
- ICE_TX_CTX_DESC_TSYN
- ICE_TX_DESC
- ICE_TX_DESC_CMD_EOP
- ICE_TX_DESC_CMD_IIPT_IPV4
- ICE_TX_DESC_CMD_IIPT_IPV4_CSUM
- ICE_TX_DESC_CMD_IIPT_IPV6
- ICE_TX_DESC_CMD_IL2TAG1
- ICE_TX_DESC_CMD_L4T_EOFT_SCTP
- ICE_TX_DESC_CMD_L4T_EOFT_TCP
- ICE_TX_DESC_CMD_L4T_EOFT_UDP
- ICE_TX_DESC_CMD_RS
- ICE_TX_DESC_DTYPE_CTX
- ICE_TX_DESC_DTYPE_DATA
- ICE_TX_DESC_DTYPE_DESC_DONE
- ICE_TX_DESC_LEN_IPLEN_S
- ICE_TX_DESC_LEN_L4_LEN_S
- ICE_TX_DESC_LEN_MACLEN_S
- ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS
- ICE_TX_FLAGS_HW_VLAN
- ICE_TX_FLAGS_SW_VLAN
- ICE_TX_FLAGS_TSO
- ICE_TX_FLAGS_VLAN_M
- ICE_TX_FLAGS_VLAN_PR_M
- ICE_TX_FLAGS_VLAN_PR_S
- ICE_TX_FLAGS_VLAN_S
- ICE_TX_ITR
- ICE_TX_LEGACY
- ICE_UCAST_PROMISC_BITS
- ICE_UCAST_VLAN_PROMISC_BITS
- ICE_UP_TABLE_TRANSLATE
- ICE_VF_RESET
- ICE_VF_STATES_NBITS
- ICE_VF_STATE_ACTIVE
- ICE_VF_STATE_DIS
- ICE_VF_STATE_INIT
- ICE_VF_STATE_MC_PROMISC
- ICE_VF_STATE_QS_ENA
- ICE_VF_STATE_UC_PROMISC
- ICE_VIRTCHNL_VF_CAP_L2
- ICE_VIRTCHNL_VF_CAP_PRIVILEGE
- ICE_VLAN_M
- ICE_VLAN_PRIORITY_S
- ICE_VM_RESET
- ICE_VSIG_IDX_M
- ICE_VSIG_VALUE
- ICE_VSIQF_HKEY_ARRAY_SIZE
- ICE_VSIQF_HLUT_ARRAY_SIZE
- ICE_VSI_FLAG_MMAC_FLTR_CHANGED
- ICE_VSI_FLAG_NBITS
- ICE_VSI_FLAG_PROMISC_CHANGED
- ICE_VSI_FLAG_UMAC_FLTR_CHANGED
- ICE_VSI_FLAG_VLAN_FLTR_CHANGED
- ICE_VSI_INVAL_ID
- ICE_VSI_LAYER_OFFSET
- ICE_VSI_LB
- ICE_VSI_MAP_CONTIG
- ICE_VSI_MAP_SCATTER
- ICE_VSI_PF
- ICE_VSI_STAT
- ICE_VSI_STATS_LEN
- ICE_VSI_VF
- ICE_WB_ON_ITR_USECS
- ICE_XLT1_CNT
- ICE_XLT2_CNT
- ICE_noinline
- ICFBSCR
- ICFG_DEV_BIT
- ICFG_DRD_AFE
- ICFG_DRD_P0CTL
- ICFG_FSM_CTRL
- ICFG_MISC_STAT
- ICFG_OFF_MODE
- ICFG_STRAP_CTRL
- ICFP
- ICFR
- ICF_ATTACHED_TO_RQUEUE
- ICF_CONTIG_MEMORY
- ICF_GOT_DATACK_SNACK
- ICF_GOT_LAST_DATAOUT
- ICF_NON_IMMEDIATE_UNSOLICITED_DATA
- ICF_OOO_CMDSN
- ICF_SENDTARGETS_ALL
- ICF_SENDTARGETS_SINGLE
- ICF_SENT_LAST_R2T
- ICF_WITHIN_COMMAND_RECOVERY
- ICH4_ACPI_EN
- ICH4_GPIOBASE
- ICH4_GPIO_CNTL
- ICH4_GPIO_EN
- ICH5R_PCI_2ND_STAT
- ICH5R_PCI_BRIDGE_CTL
- ICH5R_PCI_STAT
- ICH5_PCS
- ICH5_PMR
- ICH6_ACPI_EN
- ICH6_GPIOBASE
- ICH6_GPIO_CNTL
- ICH6_GPIO_EN
- ICH6_NUM_CAPTURE
- ICH6_NUM_PLAYBACK
- ICH7_GPIO_SIZE
- ICHD_LAST
- ICHD_MDMIN
- ICHD_MDMLAST
- ICHD_MDMOUT
- ICHD_MIC
- ICHD_MIC2
- ICHD_PCM2IN
- ICHD_PCMIN
- ICHD_PCMOUT
- ICHD_SPBAR
- ICHP
- ICHP_IRQ
- ICHP_VAL_IRQ
- ICHREG
- ICHX_READ
- ICHX_WRITE
- ICH_AC97COLD
- ICH_AC97WARM
- ICH_ACLINK
- ICH_ACPI_CNTL
- ICH_AD3
- ICH_ALI_IF_AC97SP
- ICH_ALI_IF_AC97_OUT
- ICH_ALI_IF_LINE_SRC
- ICH_ALI_IF_MC
- ICH_ALI_IF_MC2
- ICH_ALI_IF_MIC_SRC
- ICH_ALI_IF_PI
- ICH_ALI_IF_PI2
- ICH_ALI_IF_PO
- ICH_ALI_IF_PO_SPDF
- ICH_ALI_IF_SPDF_SRC
- ICH_ALI_SC_6CH_CFG
- ICH_ALI_SC_AC97_DBL
- ICH_ALI_SC_CODEC_SPDF
- ICH_ALI_SC_IN_BITS
- ICH_ALI_SC_OUT_BITS
- ICH_ALI_SC_PCM_246_MASK
- ICH_ALI_SC_PCM_4
- ICH_ALI_SC_PCM_6
- ICH_ALI_SC_RESET
- ICH_ALI_SS_PRI_ID
- ICH_ALI_SS_SEC_ID
- ICH_AP0R0
- ICH_AP0R1
- ICH_AP0R2
- ICH_AP0R3
- ICH_AP1R0
- ICH_AP1R1
- ICH_AP1R2
- ICH_AP1R3
- ICH_BCIS
- ICH_BCS
- ICH_BIT1
- ICH_BIT2
- ICH_BIT3
- ICH_CAS
- ICH_CELV
- ICH_CYCLE_ERASE
- ICH_CYCLE_READ
- ICH_CYCLE_RESERVED
- ICH_CYCLE_WRITE
- ICH_DCH
- ICH_DI1L_MASK
- ICH_DI1L_SHIFT
- ICH_DI2L_MASK
- ICH_DI2L_SHIFT
- ICH_EISR
- ICH_ELRSR
- ICH_FEIE
- ICH_FIFOE
- ICH_FLASH_COMMAND_TIMEOUT
- ICH_FLASH_CYCLE_REPEAT_COUNT
- ICH_FLASH_ERASE_COMMAND_TIMEOUT
- ICH_FLASH_ERASE_TIMEOUT
- ICH_FLASH_FADDR
- ICH_FLASH_FDATA0
- ICH_FLASH_FPR0
- ICH_FLASH_FPR1
- ICH_FLASH_FRACC
- ICH_FLASH_FREG0
- ICH_FLASH_FREG1
- ICH_FLASH_FREG2
- ICH_FLASH_FREG3
- ICH_FLASH_GFPREG
- ICH_FLASH_HSFCTL
- ICH_FLASH_HSFSTS
- ICH_FLASH_LINEAR_ADDR_MASK
- ICH_FLASH_OPMENU
- ICH_FLASH_OPTYPE
- ICH_FLASH_PR0
- ICH_FLASH_PREOP
- ICH_FLASH_READ_COMMAND_TIMEOUT
- ICH_FLASH_REG_MAPSIZE
- ICH_FLASH_SECTOR_SIZE
- ICH_FLASH_SEG_SIZE_256
- ICH_FLASH_SEG_SIZE_4K
- ICH_FLASH_SEG_SIZE_64K
- ICH_FLASH_SEG_SIZE_8K
- ICH_FLASH_SSFCTL
- ICH_FLASH_SSFSTS
- ICH_FLASH_WRITE_COMMAND_TIMEOUT
- ICH_FORCE_HPET_RESUME
- ICH_GFPREG_BASE_MASK
- ICH_GIE
- ICH_GSCI
- ICH_HCR
- ICH_HCR_EN
- ICH_HCR_EOIcount_MASK
- ICH_HCR_EOIcount_SHIFT
- ICH_HCR_NPIE
- ICH_HCR_TALL0
- ICH_HCR_TALL1
- ICH_HCR_TC
- ICH_HCR_UIE
- ICH_I3100_GPIO
- ICH_IOCE
- ICH_LDI_MASK
- ICH_LR0
- ICH_LR1
- ICH_LR10
- ICH_LR11
- ICH_LR12
- ICH_LR13
- ICH_LR14
- ICH_LR15
- ICH_LR2
- ICH_LR3
- ICH_LR4
- ICH_LR5
- ICH_LR6
- ICH_LR7
- ICH_LR8
- ICH_LR9
- ICH_LRC0
- ICH_LRC1
- ICH_LRC10
- ICH_LRC11
- ICH_LRC12
- ICH_LRC13
- ICH_LRC14
- ICH_LRC15
- ICH_LRC2
- ICH_LRC3
- ICH_LRC4
- ICH_LRC5
- ICH_LRC6
- ICH_LRC7
- ICH_LRC8
- ICH_LRC9
- ICH_LR_ACTIVE_BIT
- ICH_LR_EOI
- ICH_LR_GROUP
- ICH_LR_HW
- ICH_LR_PENDING_BIT
- ICH_LR_PHYS_ID_MASK
- ICH_LR_PHYS_ID_SHIFT
- ICH_LR_PRIORITY_MASK
- ICH_LR_PRIORITY_SHIFT
- ICH_LR_STATE
- ICH_LR_VIRTUAL_ID_MASK
- ICH_LVBCI
- ICH_LVBIE
- ICH_M2INT
- ICH_MAP
- ICH_MAX_FRAGS
- ICH_MCINT
- ICH_MD3
- ICH_MIINT
- ICH_MISR
- ICH_MISR_EOI
- ICH_MISR_U
- ICH_MOINT
- ICH_MULTICHAN_CAP
- ICH_NVSPINT
- ICH_P2INT
- ICH_PCM_2
- ICH_PCM_20BIT
- ICH_PCM_246_MASK
- ICH_PCM_4
- ICH_PCM_6
- ICH_PCM_8
- ICH_PCM_SPDIF_1011
- ICH_PCM_SPDIF_69
- ICH_PCM_SPDIF_78
- ICH_PCM_SPDIF_MASK
- ICH_PCM_SPDIF_NONE
- ICH_PCR
- ICH_PIINT
- ICH_PMBASE
- ICH_POINT
- ICH_PRI
- ICH_PRIE
- ICH_RCS
- ICH_REG_
- ICH_REG_ACC_SEMA
- ICH_REG_ALI_CAS
- ICH_REG_ALI_CPR
- ICH_REG_ALI_CPR_ADDR
- ICH_REG_ALI_CSPSR
- ICH_REG_ALI_DMACR
- ICH_REG_ALI_FIFOCR1
- ICH_REG_ALI_FIFOCR2
- ICH_REG_ALI_FIFOCR3
- ICH_REG_ALI_HWVOL
- ICH_REG_ALI_I2SCR
- ICH_REG_ALI_INTERFACECR
- ICH_REG_ALI_INTERRUPTCR
- ICH_REG_ALI_INTERRUPTSR
- ICH_REG_ALI_RTSR
- ICH_REG_ALI_SCR
- ICH_REG_ALI_SPDIFCSR
- ICH_REG_ALI_SPDIFICS
- ICH_REG_ALI_SPR
- ICH_REG_ALI_SPR_ADDR
- ICH_REG_ALI_SSR
- ICH_REG_ALI_TTSR
- ICH_REG_GLOB_CNT
- ICH_REG_GLOB_STA
- ICH_REG_LVI_MASK
- ICH_REG_PIV_MASK
- ICH_REG_SDM
- ICH_RESETREGS
- ICH_RES_GPE0
- ICH_RES_GPIO
- ICH_RES_IO_SMI
- ICH_RES_IO_TCO
- ICH_RES_MEM_GCS_PMC
- ICH_RES_MEM_OFF
- ICH_SAMPLE_16_20
- ICH_SAMPLE_CAP
- ICH_SCR
- ICH_SE
- ICH_SIS_PCM_2
- ICH_SIS_PCM_246_MASK
- ICH_SIS_PCM_4
- ICH_SIS_PCM_6
- ICH_SIS_TCR
- ICH_SIS_TRI
- ICH_SPINT
- ICH_SRI
- ICH_SRIE
- ICH_STARTBM
- ICH_TCR
- ICH_TRI
- ICH_TRIE
- ICH_V10CONS_GPIO
- ICH_V10CORP_GPIO
- ICH_V5_GPIO
- ICH_V6_GPIO
- ICH_V7_GPIO
- ICH_V9_GPIO
- ICH_VMCR
- ICH_VMCR_ACK_CTL_MASK
- ICH_VMCR_ACK_CTL_SHIFT
- ICH_VMCR_BPR0_MASK
- ICH_VMCR_BPR0_SHIFT
- ICH_VMCR_BPR1_MASK
- ICH_VMCR_BPR1_SHIFT
- ICH_VMCR_CBPR_MASK
- ICH_VMCR_CBPR_SHIFT
- ICH_VMCR_ENG0_MASK
- ICH_VMCR_ENG0_SHIFT
- ICH_VMCR_ENG1_MASK
- ICH_VMCR_ENG1_SHIFT
- ICH_VMCR_EOIM_MASK
- ICH_VMCR_EOIM_SHIFT
- ICH_VMCR_FIQ_EN_MASK
- ICH_VMCR_FIQ_EN_SHIFT
- ICH_VMCR_PMR_MASK
- ICH_VMCR_PMR_SHIFT
- ICH_VSEIR
- ICH_VTR
- ICH_VTR_A3V_MASK
- ICH_VTR_A3V_SHIFT
- ICH_VTR_ID_BITS_MASK
- ICH_VTR_ID_BITS_SHIFT
- ICH_VTR_PRI_BITS_MASK
- ICH_VTR_PRI_BITS_SHIFT
- ICH_VTR_SEIS_MASK
- ICH_VTR_SEIS_SHIFT
- ICIALLU
- ICIALLUIS
- ICIC
- ICIC_ALE
- ICIC_DTEE
- ICIC_ICCHB8
- ICIC_ICCLB8
- ICIC_RDMAE
- ICIC_TACKE
- ICIC_TDMAE
- ICIC_WAITE
- ICIER_NAKIE
- ICIER_RIE
- ICIER_SPIE
- ICIER_TEIE
- ICIER_TIE
- ICIMVAU
- ICINTSTAT_ICRX
- ICINTSTAT_ICTX
- ICINTSTAT_ICTX0
- ICINTSTAT_ICTX1
- ICIORD_MARK
- ICIOWRAH_MARK
- ICIP
- ICLK
- ICLK_MASK
- ICLR
- ICLR_FIQ
- ICLR_IDLE
- ICLR_IRQ
- ICLR_PENDING
- ICLR_RXOEC1
- ICLR_RXOEC2
- ICLR_RXOEC3
- ICLR_RXOEC4
- ICLR_RXTOFEC1
- ICLR_RXTOFEC2
- ICLR_RXTOFEC3
- ICLR_RXTOFEC4
- ICLR_TRANSMIT
- ICLR_TXUEC1
- ICLR_TXUEC2
- ICLR_TXUEC3
- ICLR_TXUEC4
- ICLR_WISC
- ICL_AUX_ANAOVRD1
- ICL_AUX_ANAOVRD1_ENABLE
- ICL_AUX_ANAOVRD1_LDO_BYPASS
- ICL_AUX_A_IO_POWER_DOMAINS
- ICL_AUX_B_IO_POWER_DOMAINS
- ICL_AUX_CHANNEL_E
- ICL_AUX_C_IO_POWER_DOMAINS
- ICL_AUX_D_IO_POWER_DOMAINS
- ICL_AUX_E_IO_POWER_DOMAINS
- ICL_AUX_F_IO_POWER_DOMAINS
- ICL_AUX_PW_TO_CH
- ICL_AUX_PW_TO_PHY
- ICL_AUX_TBT1_IO_POWER_DOMAINS
- ICL_AUX_TBT2_IO_POWER_DOMAINS
- ICL_AUX_TBT3_IO_POWER_DOMAINS
- ICL_AUX_TBT4_IO_POWER_DOMAINS
- ICL_BYTE_CLK_PER_ESC_CLK_MASK
- ICL_BYTE_CLK_PER_ESC_CLK_SHIFT
- ICL_CDCLK_CD2X_PIPE_NONE
- ICL_CLK_ZERO_CNT_MAX
- ICL_COMMUNITY
- ICL_CSC_ENABLE
- ICL_CSR_MAX_FW_SIZE
- ICL_CSR_PATH
- ICL_CSR_VERSION_REQUIRED
- ICL_DDC_BUS_DDI_A
- ICL_DDC_BUS_DDI_B
- ICL_DDC_BUS_PORT_1
- ICL_DDC_BUS_PORT_2
- ICL_DDC_BUS_PORT_3
- ICL_DDC_BUS_PORT_4
- ICL_DDI_IO_A_POWER_DOMAINS
- ICL_DDI_IO_B_POWER_DOMAINS
- ICL_DDI_IO_C_POWER_DOMAINS
- ICL_DDI_IO_D_POWER_DOMAINS
- ICL_DDI_IO_E_POWER_DOMAINS
- ICL_DDI_IO_F_POWER_DOMAINS
- ICL_DISPLAY_DC_OFF_POWER_DOMAINS
- ICL_DPCLKA_CFGCR0
- ICL_DPCLKA_CFGCR0_DDI_CLK_OFF
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK
- ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT
- ICL_DPCLKA_CFGCR0_TC_CLK_OFF
- ICL_DPHY_CHKN
- ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP
- ICL_DPHY_ESC_CLK_DIV
- ICL_DPLL_CFGCR0
- ICL_DPLL_CFGCR1
- ICL_DSC0_PICTURE_PARAMETER_SET_0
- ICL_DSC0_PICTURE_PARAMETER_SET_1
- ICL_DSC0_PICTURE_PARAMETER_SET_10
- ICL_DSC0_PICTURE_PARAMETER_SET_11
- ICL_DSC0_PICTURE_PARAMETER_SET_12
- ICL_DSC0_PICTURE_PARAMETER_SET_13
- ICL_DSC0_PICTURE_PARAMETER_SET_14
- ICL_DSC0_PICTURE_PARAMETER_SET_15
- ICL_DSC0_PICTURE_PARAMETER_SET_16
- ICL_DSC0_PICTURE_PARAMETER_SET_2
- ICL_DSC0_PICTURE_PARAMETER_SET_3
- ICL_DSC0_PICTURE_PARAMETER_SET_4
- ICL_DSC0_PICTURE_PARAMETER_SET_5
- ICL_DSC0_PICTURE_PARAMETER_SET_6
- ICL_DSC0_PICTURE_PARAMETER_SET_7
- ICL_DSC0_PICTURE_PARAMETER_SET_8
- ICL_DSC0_PICTURE_PARAMETER_SET_9
- ICL_DSC0_RC_BUF_THRESH_0
- ICL_DSC0_RC_BUF_THRESH_0_UDW
- ICL_DSC0_RC_BUF_THRESH_1
- ICL_DSC0_RC_BUF_THRESH_1_UDW
- ICL_DSC0_RC_RANGE_PARAMETERS_0
- ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW
- ICL_DSC0_RC_RANGE_PARAMETERS_1
- ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW
- ICL_DSC0_RC_RANGE_PARAMETERS_2
- ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW
- ICL_DSC0_RC_RANGE_PARAMETERS_3
- ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW
- ICL_DSC1_PICTURE_PARAMETER_SET_0
- ICL_DSC1_PICTURE_PARAMETER_SET_1
- ICL_DSC1_PICTURE_PARAMETER_SET_10
- ICL_DSC1_PICTURE_PARAMETER_SET_11
- ICL_DSC1_PICTURE_PARAMETER_SET_12
- ICL_DSC1_PICTURE_PARAMETER_SET_13
- ICL_DSC1_PICTURE_PARAMETER_SET_14
- ICL_DSC1_PICTURE_PARAMETER_SET_15
- ICL_DSC1_PICTURE_PARAMETER_SET_16
- ICL_DSC1_PICTURE_PARAMETER_SET_2
- ICL_DSC1_PICTURE_PARAMETER_SET_3
- ICL_DSC1_PICTURE_PARAMETER_SET_4
- ICL_DSC1_PICTURE_PARAMETER_SET_5
- ICL_DSC1_PICTURE_PARAMETER_SET_6
- ICL_DSC1_PICTURE_PARAMETER_SET_7
- ICL_DSC1_PICTURE_PARAMETER_SET_8
- ICL_DSC1_PICTURE_PARAMETER_SET_9
- ICL_DSC1_RC_BUF_THRESH_0
- ICL_DSC1_RC_BUF_THRESH_0_UDW
- ICL_DSC1_RC_BUF_THRESH_1
- ICL_DSC1_RC_BUF_THRESH_1_UDW
- ICL_DSC1_RC_RANGE_PARAMETERS_0
- ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW
- ICL_DSC1_RC_RANGE_PARAMETERS_1
- ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW
- ICL_DSC1_RC_RANGE_PARAMETERS_2
- ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW
- ICL_DSC1_RC_RANGE_PARAMETERS_3
- ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW
- ICL_DSI_ESC_CLK_DIV
- ICL_DSI_IO_MODECTL
- ICL_DSI_T_INIT_MASTER
- ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz
- ICL_DSSM_CDCLK_PLL_REFCLK_24MHz
- ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz
- ICL_DSSM_CDCLK_PLL_REFCLK_MASK
- ICL_ESC_CLK_DIV_MASK
- ICL_ESC_CLK_DIV_SHIFT
- ICL_EVENTSEL_ADAPTIVE
- ICL_EXIT_ZERO_CNT_MAX
- ICL_FIXED_0_ADAPTIVE
- ICL_GPIO_DDPA_CTRLCLK_1
- ICL_GPIO_DDPA_CTRLCLK_2
- ICL_GPIO_DDPA_CTRLDATA_1
- ICL_GPIO_DDPA_CTRLDATA_2
- ICL_GPIO_DDSP_HPD_A
- ICL_GPIO_DDSP_HPD_B
- ICL_GPIO_L_BKLTEN_1
- ICL_GPIO_L_BKLTEN_2
- ICL_GPIO_L_VDDEN_1
- ICL_GPIO_L_VDDEN_2
- ICL_GPI_IE
- ICL_GPI_IS
- ICL_GPP
- ICL_HDC_MODE
- ICL_HOSTSW_OWN
- ICL_HS_ZERO_CNT_MAX
- ICL_LANE_ENABLE_AUX
- ICL_LC_GO2SX
- ICL_LC_GO2SX_NO_WAKE
- ICL_LC_MAILBOX_TIMEOUT
- ICL_LC_PREPARE_FOR_RESET
- ICL_MAX_DST_H
- ICL_MAX_DST_W
- ICL_MAX_SRC_H
- ICL_MAX_SRC_W
- ICL_MOBILE_DEVICE_ID
- ICL_NO_GPIO
- ICL_NUM_IP_IGN_ALLOWED
- ICL_OUTPUT_CSC_ENABLE
- ICL_PADCFGLOCK
- ICL_PAD_OWN
- ICL_PCODE_MEM_SS_READ_GLOBAL_INFO
- ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO
- ICL_PCODE_MEM_SUBSYSYSTEM_INFO
- ICL_PG3
- ICL_PG4
- ICL_PHY_MISC
- ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN
- ICL_PHY_MISC_MUX_DDID
- ICL_PIPE_DSS_CTL1
- ICL_PIPE_DSS_CTL2
- ICL_PLANE_CTL_FORMAT_MASK
- ICL_PMC_LTR_WIGIG
- ICL_PORT_CL_DW10
- ICL_PORT_CL_DW12
- ICL_PORT_CL_DW5
- ICL_PORT_COMP_DW0
- ICL_PORT_COMP_DW1
- ICL_PORT_COMP_DW10
- ICL_PORT_COMP_DW3
- ICL_PORT_COMP_DW8
- ICL_PORT_COMP_DW9
- ICL_PORT_DPLL_COUNT
- ICL_PORT_DPLL_DEFAULT
- ICL_PORT_DPLL_MG_PHY
- ICL_PORT_PCS_DW1_AUX
- ICL_PORT_PCS_DW1_GRP
- ICL_PORT_PCS_DW1_LN0
- ICL_PORT_TX_DW2_AUX
- ICL_PORT_TX_DW2_GRP
- ICL_PORT_TX_DW2_LN0
- ICL_PORT_TX_DW4_AUX
- ICL_PORT_TX_DW4_GRP
- ICL_PORT_TX_DW4_LN
- ICL_PORT_TX_DW4_LN0
- ICL_PORT_TX_DW5_AUX
- ICL_PORT_TX_DW5_GRP
- ICL_PORT_TX_DW5_LN0
- ICL_PORT_TX_DW7_AUX
- ICL_PORT_TX_DW7_GRP
- ICL_PORT_TX_DW7_LN
- ICL_PORT_TX_DW7_LN0
- ICL_PPFEAR_NUM_ENTRIES
- ICL_PREPARE_CNT_MAX
- ICL_PWR_WELL_CTL_AUX1
- ICL_PWR_WELL_CTL_AUX2
- ICL_PWR_WELL_CTL_AUX4
- ICL_PWR_WELL_CTL_DDI1
- ICL_PWR_WELL_CTL_DDI2
- ICL_PWR_WELL_CTL_DDI4
- ICL_PW_2_POWER_DOMAINS
- ICL_PW_3_POWER_DOMAINS
- ICL_PW_4_POWER_DOMAINS
- ICL_PW_CTL_IDX_AUX_A
- ICL_PW_CTL_IDX_AUX_B
- ICL_PW_CTL_IDX_AUX_C
- ICL_PW_CTL_IDX_AUX_D
- ICL_PW_CTL_IDX_AUX_E
- ICL_PW_CTL_IDX_AUX_F
- ICL_PW_CTL_IDX_AUX_TBT1
- ICL_PW_CTL_IDX_AUX_TBT2
- ICL_PW_CTL_IDX_AUX_TBT3
- ICL_PW_CTL_IDX_AUX_TBT4
- ICL_PW_CTL_IDX_DDI_A
- ICL_PW_CTL_IDX_DDI_B
- ICL_PW_CTL_IDX_DDI_C
- ICL_PW_CTL_IDX_DDI_D
- ICL_PW_CTL_IDX_DDI_E
- ICL_PW_CTL_IDX_DDI_F
- ICL_PW_CTL_IDX_PW_1
- ICL_PW_CTL_IDX_PW_2
- ICL_PW_CTL_IDX_PW_3
- ICL_PW_CTL_IDX_PW_4
- ICL_PW_CTL_IDX_TO_PG
- ICL_REVID_A0
- ICL_REVID_A2
- ICL_REVID_B0
- ICL_REVID_B2
- ICL_REVID_C0
- ICL_SSP_COUNT
- ICL_TBT_AUX_PW_TO_CH
- ICL_TCLK_POST_CNT_MAX
- ICL_TCLK_PRE_CNT_MAX
- ICL_TRAIL_CNT_MAX
- ICL_UNC_CBO_0_PER_CTR0
- ICL_UNC_CBO_CONFIG
- ICL_UNC_CBO_MSR_OFFSET
- ICL_UNC_NUM_CBO_MASK
- ICL_VIDEO_DIP_PPS_DATA
- ICL_VIDEO_DIP_PPS_ECC
- ICMAR
- ICMCR
- ICMDQUE_WR
- ICMD_COMP
- ICMIER
- ICMP6MSGIN_INC_STATS
- ICMP6MSGOUT_INC_STATS
- ICMP6MSG_MIB_MAX
- ICMP6_INC_STATS
- ICMP6_MIB_CSUMERRORS
- ICMP6_MIB_INERRORS
- ICMP6_MIB_INMSGS
- ICMP6_MIB_MAX
- ICMP6_MIB_NUM
- ICMP6_MIB_OUTERRORS
- ICMP6_MIB_OUTMSGS
- ICMPMSGIN_INC_STATS
- ICMPMSGOUT_INC_STATS
- ICMPMSG_MIB_MAX
- ICMPV6_ADDR_UNREACH
- ICMPV6_ADM_PROHIBITED
- ICMPV6_DEST_UNREACH
- ICMPV6_DHAAD_REPLY
- ICMPV6_DHAAD_REQUEST
- ICMPV6_ECHO_REPLY
- ICMPV6_ECHO_REQUEST
- ICMPV6_ERRMSG_MAX
- ICMPV6_EXC_FRAGTIME
- ICMPV6_EXC_HOPLIMIT
- ICMPV6_FILTER
- ICMPV6_FILTER_BLOCK
- ICMPV6_FILTER_BLOCKOTHERS
- ICMPV6_FILTER_PASS
- ICMPV6_FILTER_PASSONLY
- ICMPV6_HDRLEN
- ICMPV6_HDR_FIELD
- ICMPV6_INFOMSG_MASK
- ICMPV6_MCAST_MAC
- ICMPV6_MGM_QUERY
- ICMPV6_MGM_REDUCTION
- ICMPV6_MGM_REPORT
- ICMPV6_MLD2_REPORT
- ICMPV6_MOBILE_PREFIX_ADV
- ICMPV6_MOBILE_PREFIX_SOL
- ICMPV6_MRDISC_ADV
- ICMPV6_MSG_MAX
- ICMPV6_NI_QUERY
- ICMPV6_NI_REPLY
- ICMPV6_NOROUTE
- ICMPV6_NOT_NEIGHBOUR
- ICMPV6_PARAMPROB
- ICMPV6_PKT_TOOBIG
- ICMPV6_POLICY_FAIL
- ICMPV6_PORT_UNREACH
- ICMPV6_REJECT_ROUTE
- ICMPV6_ROUTER_PREF_HIGH
- ICMPV6_ROUTER_PREF_INVALID
- ICMPV6_ROUTER_PREF_LOW
- ICMPV6_ROUTER_PREF_MEDIUM
- ICMPV6_TIME_EXCEED
- ICMPV6_UNK_NEXTHDR
- ICMPV6_UNK_OPTION
- ICMP_ADDRESS
- ICMP_ADDRESSREPLY
- ICMP_CODE_OFFSET_FIRST_DW
- ICMP_DEST_UNREACH
- ICMP_ECHO
- ICMP_ECHOREPLY
- ICMP_ECHO_LEN
- ICMP_EXC_FRAGTIME
- ICMP_EXC_TTL
- ICMP_FILTER
- ICMP_FRAG_NEEDED
- ICMP_HEADER_DATA_OFFSET_SECOND_DW
- ICMP_HOST_ANO
- ICMP_HOST_ISOLATED
- ICMP_HOST_UNKNOWN
- ICMP_HOST_UNREACH
- ICMP_HOST_UNR_TOS
- ICMP_INC_STATS
- ICMP_INFO_REPLY
- ICMP_INFO_REQUEST
- ICMP_MIB_CSUMERRORS
- ICMP_MIB_INADDRMASKREPS
- ICMP_MIB_INADDRMASKS
- ICMP_MIB_INDESTUNREACHS
- ICMP_MIB_INECHOREPS
- ICMP_MIB_INECHOS
- ICMP_MIB_INERRORS
- ICMP_MIB_INMSGS
- ICMP_MIB_INPARMPROBS
- ICMP_MIB_INREDIRECTS
- ICMP_MIB_INSRCQUENCHS
- ICMP_MIB_INTIMEEXCDS
- ICMP_MIB_INTIMESTAMPREPS
- ICMP_MIB_INTIMESTAMPS
- ICMP_MIB_MAX
- ICMP_MIB_NUM
- ICMP_MIB_OUTADDRMASKREPS
- ICMP_MIB_OUTADDRMASKS
- ICMP_MIB_OUTDESTUNREACHS
- ICMP_MIB_OUTECHOREPS
- ICMP_MIB_OUTECHOS
- ICMP_MIB_OUTERRORS
- ICMP_MIB_OUTMSGS
- ICMP_MIB_OUTPARMPROBS
- ICMP_MIB_OUTREDIRECTS
- ICMP_MIB_OUTSRCQUENCHS
- ICMP_MIB_OUTTIMEEXCDS
- ICMP_MIB_OUTTIMESTAMPREPS
- ICMP_MIB_OUTTIMESTAMPS
- ICMP_NET_ANO
- ICMP_NET_UNKNOWN
- ICMP_NET_UNREACH
- ICMP_NET_UNR_TOS
- ICMP_PARAMETERPROB
- ICMP_PKT_FILTERED
- ICMP_PORT_UNREACH
- ICMP_PREC_CUTOFF
- ICMP_PREC_VIOLATION
- ICMP_PROT_UNREACH
- ICMP_REDIRECT
- ICMP_REDIR_HOST
- ICMP_REDIR_HOSTTOS
- ICMP_REDIR_NET
- ICMP_REDIR_NETTOS
- ICMP_SOURCE_QUENCH
- ICMP_SR_FAILED
- ICMP_TIMESTAMP
- ICMP_TIMESTAMPREPLY
- ICMP_TIME_EXCEEDED
- ICMP_TOOBIG_PAYLOAD_SIZE
- ICMP_TOOBIG_SIZE
- ICMP_TYPE_OFFSET_FIRST_DW
- ICMR
- ICMR1_BCWP
- ICMR1_CKS
- ICMR1_CKS_MASK
- ICMR3_ACKBT
- ICMR3_ACKWP
- ICMR3_RDRFS
- ICMSGHDRFLAG_REQUEST
- ICMSGHDRFLAG_RESPONSE
- ICMSGHDRFLAG_TRANSACTION
- ICMSGTYPE_HEARTBEAT
- ICMSGTYPE_KVPEXCHANGE
- ICMSGTYPE_NEGOTIATE
- ICMSGTYPE_SHUTDOWN
- ICMSGTYPE_TIMESYNC
- ICMSGTYPE_VSS
- ICMSR
- ICM_ADD_DEVICE_KEY
- ICM_APPROVE_DEVICE
- ICM_APPROVE_TIMEOUT
- ICM_APPROVE_XDOMAIN
- ICM_AR_FLAGS_RTD3
- ICM_AR_INFO_BOOT_ACL_MASK
- ICM_AR_INFO_BOOT_ACL_SHIFT
- ICM_AR_INFO_BOOT_ACL_SUPPORTED
- ICM_AR_INFO_SLEVEL_MASK
- ICM_AR_PREBOOT_ACL_ENTRIES
- ICM_CFG_mskBSAV
- ICM_CFG_mskILCK
- ICM_CFG_mskILMB
- ICM_CFG_mskISET
- ICM_CFG_mskISZ
- ICM_CFG_mskIWAY
- ICM_CFG_offBSAV
- ICM_CFG_offILCK
- ICM_CFG_offILMB
- ICM_CFG_offISET
- ICM_CFG_offISZ
- ICM_CFG_offIWAY
- ICM_CHALLENGE_DEVICE
- ICM_CONFIG0_REG_0
- ICM_CONFIG0_REG_0_ADDR
- ICM_CONFIG2_REG_0
- ICM_CONFIG2_REG_0_ADDR
- ICM_DISCONNECT_XDOMAIN
- ICM_DRIVER_READY
- ICM_DROP_COUNT
- ICM_ECM_DROP_COUNT_REG0_ADDR
- ICM_ECM_DROP_COUNT_REG1_ADDR
- ICM_EVENT_DEVICE_CONNECTED
- ICM_EVENT_DEVICE_DISCONNECTED
- ICM_EVENT_RTD3_VETO
- ICM_EVENT_XDOMAIN_CONNECTED
- ICM_EVENT_XDOMAIN_DISCONNECTED
- ICM_FLAGS_ERROR
- ICM_FLAGS_NO_KEY
- ICM_FLAGS_SLEVEL_MASK
- ICM_FLAGS_SLEVEL_SHIFT
- ICM_FLAGS_WRITE
- ICM_FR_SLEVEL_MASK
- ICM_GET_ROUTE
- ICM_GET_TOPOLOGY
- ICM_GET_TOPOLOGY_PACKETS
- ICM_LINK_INFO_APPROVED
- ICM_LINK_INFO_BOOT
- ICM_LINK_INFO_DEPTH_MASK
- ICM_LINK_INFO_DEPTH_SHIFT
- ICM_LINK_INFO_LINK_MASK
- ICM_LINK_INFO_REJECTED
- ICM_MAX_LINK
- ICM_PORT_INDEX_MASK
- ICM_PORT_INDEX_SHIFT
- ICM_PORT_TYPE_MASK
- ICM_PREBOOT_ACL
- ICM_SWITCH_UPSTREAM_PORT_MASK
- ICM_SWITCH_UPSTREAM_PORT_SHIFT
- ICM_SWITCH_USED
- ICM_TIMEOUT
- ICM_TR_FLAGS_RTD3
- ICM_TR_INFO_BOOT_ACL_MASK
- ICM_TR_INFO_BOOT_ACL_SHIFT
- ICM_TR_INFO_SLEVEL_MASK
- ICN8318_EVENT_END
- ICN8318_EVENT_NO_DATA
- ICN8318_EVENT_UPDATE1
- ICN8318_EVENT_UPDATE2
- ICN8318_MAX_TOUCHES
- ICN8318_POWER_ACTIVE
- ICN8318_POWER_HIBERNATE
- ICN8318_POWER_MONITOR
- ICN8318_REG_POWER
- ICN8318_REG_TOUCHDATA
- ICN8505_EVENT_END
- ICN8505_EVENT_NO_DATA
- ICN8505_EVENT_UPDATE1
- ICN8505_EVENT_UPDATE2
- ICN8505_MAX_TOUCHES
- ICN8505_POWER_ACTIVE
- ICN8505_POWER_DIS_CHARGER_MODE
- ICN8505_POWER_ENA_CHARGER_MODE
- ICN8505_POWER_HIBERNATE
- ICN8505_POWER_MONITOR
- ICN8505_PROG_I2C_ADDR
- ICN8505_PROG_REG_ADDR_WIDTH
- ICN8505_REG_ADDR_WIDTH
- ICN8505_REG_CONFIGDATA
- ICN8505_REG_POWER
- ICN8505_REG_TOUCHDATA
- ICODE_FPGA_EMULATION
- ICODE_FUNCTIONAL_SIMULATOR
- ICODE_RTL_SILICON
- ICODE_RTL_VCS_SIMULATION
- ICOLL
- ICOLL_NUM_IRQS
- ICOM_ACFG_1STOP_BIT
- ICOM_ACFG_2STOP_BIT
- ICOM_ACFG_5BPC
- ICOM_ACFG_6BPC
- ICOM_ACFG_7BPC
- ICOM_ACFG_8BPC
- ICOM_ACFG_DRIVE1
- ICOM_ACFG_NO_PARITY
- ICOM_ACFG_PARITY_ENAB
- ICOM_ACFG_PARITY_ODD
- ICOM_CABLE_ID_MASK
- ICOM_CABLE_ID_VALID
- ICOM_CONSOLE
- ICOM_CONTROL_START_A
- ICOM_CONTROL_START_B
- ICOM_CONTROL_START_C
- ICOM_CONTROL_START_D
- ICOM_CONTROL_STOP_A
- ICOM_CONTROL_STOP_B
- ICOM_CONTROL_STOP_C
- ICOM_CONTROL_STOP_D
- ICOM_CTS
- ICOM_DCD
- ICOM_DCE_IRAM_OFFSET
- ICOM_DISABLE
- ICOM_DRIVER_NAME
- ICOM_DSR
- ICOM_DTR
- ICOM_HDW_ACTIVE
- ICOM_ID_1_PID
- ICOM_ID_RP2C1_PID
- ICOM_ID_RP2C2_PID
- ICOM_ID_RP2D_PID
- ICOM_ID_RP2KVR_PID
- ICOM_ID_RP2KVT_PID
- ICOM_ID_RP2VR_PID
- ICOM_ID_RP2VT_PID
- ICOM_ID_RP4KVR_PID
- ICOM_ID_RP4KVT_PID
- ICOM_IMBED_MODEM
- ICOM_INT_MASK_PRC_A
- ICOM_INT_MASK_PRC_B
- ICOM_INT_MASK_PRC_C
- ICOM_INT_MASK_PRC_D
- ICOM_IRAM_OFFSET
- ICOM_IRAM_SIZE
- ICOM_MAJOR
- ICOM_MINOR_START
- ICOM_OPC_U_UC_PID
- ICOM_PORT
- ICOM_PORT_ACTIVE
- ICOM_PORT_OFF
- ICOM_RI
- ICOM_RTS
- ICOM_RVX
- ICOM_UNKNOWN
- ICOM_VERSION_STR
- ICOM_VID
- ICON2_CLR0
- ICON2_CLR1
- ICON2_HORZ_VERT_OFF
- ICON2_HORZ_VERT_POSN
- ICON2_OFFSET
- ICONTROL_MCP251x_nCS1
- ICONTROL_MCP251x_nCS2
- ICONTROL_MCP251x_nCS3
- ICONTROL_MCP251x_nCS4
- ICONTROL_MCP251x_nIRQ1
- ICONTROL_MCP251x_nIRQ2
- ICONTROL_MCP251x_nIRQ3
- ICONTROL_MCP251x_nIRQ4
- ICONTROL_STATUSNAK
- ICON_CLR0
- ICON_CLR1
- ICON_DEGAMMA_MODE
- ICON_ENABLE
- ICON_HORZ_VERT_OFF
- ICON_HORZ_VERT_POSN
- ICON_OFFSET
- ICOUNT_MASK
- ICPC0
- ICPC0_MASK
- ICPC0_SHIFT
- ICPC1
- ICPC1_MASK
- ICPC1_SHIFT
- ICPC2
- ICPC2_MASK
- ICPC2_SHIFT
- ICPC3
- ICPC3_MASK
- ICPC3_SHIFT
- ICPC4
- ICPC4_MASK
- ICPC4_SHIFT
- ICPC5
- ICPC5_MASK
- ICPC5_SHIFT
- ICPC6
- ICPC6_MASK
- ICPC6_SHIFT
- ICPC7
- ICPC7_MASK
- ICPC7_SHIFT
- ICPC_MASK
- ICPC_ROTATE
- ICPDAS_I7560U_PID
- ICPDAS_I7561U_PID
- ICPDAS_I7563U_PID
- ICPDAS_VID
- ICPR
- ICPT_EXTINT
- ICPT_EXTREQ
- ICPT_INST
- ICPT_INSTPROGI
- ICPT_IOINST
- ICPT_IOREQ
- ICPT_KSS
- ICPT_OPEREXC
- ICPT_PARTEXEC
- ICPT_PROGI
- ICPT_STOP
- ICPT_VALIDITY
- ICPT_WAIT
- ICPU
- ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL
- ICPU_CFG_CPU_SYSTEM_CTRL_RESET
- ICPU_CFG_INTR_DST_INTR_IDENT
- ICPU_CFG_INTR_INTR_ENA
- ICPU_CFG_INTR_INTR_ENA_CLR
- ICPU_CFG_INTR_INTR_ENA_SET
- ICPU_CFG_INTR_INTR_STICKY
- ICPU_CFG_INTR_INTR_TRIGGER
- ICPU_HWP
- ICP_DDIA_HPD_ENABLE
- ICP_DDIA_HPD_LONG_DETECT
- ICP_DDIA_HPD_NO_DETECT
- ICP_DDIA_HPD_OP_DRIVE_1
- ICP_DDIA_HPD_SHORT_DETECT
- ICP_DDIA_HPD_SHORT_LONG_DETECT
- ICP_DDIA_HPD_STATUS_MASK
- ICP_DDIB_HPD_ENABLE
- ICP_DDIB_HPD_LONG_DETECT
- ICP_DDIB_HPD_NO_DETECT
- ICP_DDIB_HPD_SHORT_DETECT
- ICP_DDIB_HPD_SHORT_LONG_DETECT
- ICP_DDIB_HPD_STATUS_MASK
- ICP_DDI_HPD_ENABLE_MASK
- ICP_DH895XCC_PESRAM_BAR_SIZE
- ICP_DR_ABS
- ICP_DR_RD_ABS
- ICP_DR_RD_REL
- ICP_DR_REL
- ICP_DR_WR_ABS
- ICP_DR_WR_REL
- ICP_GLOBAL_CLK_ENABLE
- ICP_GPA_ABS
- ICP_GPA_REL
- ICP_GPB_ABS
- ICP_GPB_REL
- ICP_LEVEL1
- ICP_LEVEL2
- ICP_LEVEL3
- ICP_LEVEL4
- ICP_LMEM
- ICP_LMEM0
- ICP_LMEM1
- ICP_MULTI_ADC_CSR
- ICP_MULTI_ADC_CSR_BI
- ICP_MULTI_ADC_CSR_BSY
- ICP_MULTI_ADC_CSR_DI
- ICP_MULTI_ADC_CSR_DI_CHAN
- ICP_MULTI_ADC_CSR_RA
- ICP_MULTI_ADC_CSR_SE_CHAN
- ICP_MULTI_ADC_CSR_ST
- ICP_MULTI_AI
- ICP_MULTI_AO
- ICP_MULTI_CNTR0
- ICP_MULTI_CNTR1
- ICP_MULTI_CNTR2
- ICP_MULTI_CNTR3
- ICP_MULTI_DAC_CSR
- ICP_MULTI_DAC_CSR_BI
- ICP_MULTI_DAC_CSR_BSY
- ICP_MULTI_DAC_CSR_CHAN
- ICP_MULTI_DAC_CSR_RA
- ICP_MULTI_DAC_CSR_ST
- ICP_MULTI_DI
- ICP_MULTI_DO
- ICP_MULTI_INT_ADC_RDY
- ICP_MULTI_INT_CIE0
- ICP_MULTI_INT_CIE1
- ICP_MULTI_INT_CIE2
- ICP_MULTI_INT_CIE3
- ICP_MULTI_INT_DAC_RDY
- ICP_MULTI_INT_DIN_STAT
- ICP_MULTI_INT_DOUT_ERR
- ICP_MULTI_INT_EN
- ICP_MULTI_INT_MASK
- ICP_MULTI_INT_STAT
- ICP_NEIGH_REL
- ICP_NO_DEST
- ICP_PP_CONTROL
- ICP_QAT_AC_895XCC_DEV_TYPE
- ICP_QAT_AC_C3XXX_DEV_TYPE
- ICP_QAT_AC_C62X_DEV_TYPE
- ICP_QAT_AE_IMG_OFFSET
- ICP_QAT_AE_OFFSET
- ICP_QAT_CAP_OFFSET
- ICP_QAT_CSS_AE_IMG_LEN
- ICP_QAT_CSS_AE_SIMG_LEN
- ICP_QAT_CSS_FWSK_EXPONENT_LEN
- ICP_QAT_CSS_FWSK_MODULUS_LEN
- ICP_QAT_CSS_FWSK_PAD_LEN
- ICP_QAT_CSS_FWSK_PUB_LEN
- ICP_QAT_CSS_MAX_IMAGE_LEN
- ICP_QAT_CSS_SIGNATURE_LEN
- ICP_QAT_CTX_MODE
- ICP_QAT_EP_OFFSET
- ICP_QAT_FW_AUTH_CURR_ID_GET
- ICP_QAT_FW_AUTH_CURR_ID_SET
- ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED
- ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED
- ICP_QAT_FW_AUTH_NEXT_ID_GET
- ICP_QAT_FW_AUTH_NEXT_ID_SET
- ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX
- ICP_QAT_FW_CIPHER_CURR_ID_GET
- ICP_QAT_FW_CIPHER_CURR_ID_SET
- ICP_QAT_FW_CIPHER_NEXT_ID_GET
- ICP_QAT_FW_CIPHER_NEXT_ID_SET
- ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET
- ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP
- ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP
- ICP_QAT_FW_CIPH_IV_16BYTE_DATA
- ICP_QAT_FW_CIPH_IV_64BIT_PTR
- ICP_QAT_FW_COMN_CD_FLD_TYPE_GET
- ICP_QAT_FW_COMN_CD_FLD_TYPE_SET
- ICP_QAT_FW_COMN_CURR_ID_BITPOS
- ICP_QAT_FW_COMN_CURR_ID_GET
- ICP_QAT_FW_COMN_CURR_ID_MASK
- ICP_QAT_FW_COMN_CURR_ID_SET
- ICP_QAT_FW_COMN_FLAGS_BUILD
- ICP_QAT_FW_COMN_HDR_FLAGS_BUILD
- ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET
- ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK
- ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET
- ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET
- ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED
- ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS
- ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET
- ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK
- ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET
- ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET
- ICP_QAT_FW_COMN_HEARTBEAT_OK
- ICP_QAT_FW_COMN_NEXT_ID_BITPOS
- ICP_QAT_FW_COMN_NEXT_ID_GET
- ICP_QAT_FW_COMN_NEXT_ID_MASK
- ICP_QAT_FW_COMN_NEXT_ID_SET
- ICP_QAT_FW_COMN_ONE_BYTE_SHIFT
- ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET
- ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET
- ICP_QAT_FW_COMN_OV_SRV_TYPE_GET
- ICP_QAT_FW_COMN_OV_SRV_TYPE_SET
- ICP_QAT_FW_COMN_PTR_TYPE_GET
- ICP_QAT_FW_COMN_PTR_TYPE_SET
- ICP_QAT_FW_COMN_REQ_CPM_FW_COMP
- ICP_QAT_FW_COMN_REQ_CPM_FW_DMA
- ICP_QAT_FW_COMN_REQ_CPM_FW_LA
- ICP_QAT_FW_COMN_REQ_CPM_FW_PKE
- ICP_QAT_FW_COMN_REQ_DELIMITER
- ICP_QAT_FW_COMN_REQ_FLAG_CLR
- ICP_QAT_FW_COMN_REQ_FLAG_SET
- ICP_QAT_FW_COMN_REQ_NULL
- ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET
- ICP_QAT_FW_COMN_RESP_CMP_STAT_GET
- ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET
- ICP_QAT_FW_COMN_RESP_SERV_CPM_FW
- ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
- ICP_QAT_FW_COMN_RESP_SERV_NULL
- ICP_QAT_FW_COMN_RESP_STATUS_BUILD
- ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET
- ICP_QAT_FW_COMN_SINGLE_BYTE_MASK
- ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR
- ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET
- ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
- ICP_QAT_FW_COMN_STATUS_FLAG_OK
- ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK
- ICP_QAT_FW_COMN_VALID_FLAG_BITPOS
- ICP_QAT_FW_COMN_VALID_FLAG_GET
- ICP_QAT_FW_COMN_VALID_FLAG_MASK
- ICP_QAT_FW_COMN_VALID_FLAG_SET
- ICP_QAT_FW_CONSTANTS_CFG
- ICP_QAT_FW_COUNTERS_GET
- ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET
- ICP_QAT_FW_HEARTBEAT_GET
- ICP_QAT_FW_HEARTBEAT_SYNC
- ICP_QAT_FW_INIT_ME
- ICP_QAT_FW_INIT_RESP_STATUS_FAIL
- ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS
- ICP_QAT_FW_LA_CCM_PROTO
- ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET
- ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET
- ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET
- ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET
- ICP_QAT_FW_LA_CMD_AUTH
- ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP
- ICP_QAT_FW_LA_CMD_CIPHER
- ICP_QAT_FW_LA_CMD_CIPHER_HASH
- ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP
- ICP_QAT_FW_LA_CMD_DELIMITER
- ICP_QAT_FW_LA_CMD_HASH_CIPHER
- ICP_QAT_FW_LA_CMD_MGF1
- ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE
- ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE
- ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE
- ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM
- ICP_QAT_FW_LA_CMD_TRNG_TEST
- ICP_QAT_FW_LA_CMP_AUTH_GET
- ICP_QAT_FW_LA_CMP_AUTH_RES
- ICP_QAT_FW_LA_CMP_AUTH_SET
- ICP_QAT_FW_LA_DIGEST_IN_BUFFER
- ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET
- ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET
- ICP_QAT_FW_LA_FLAGS_BUILD
- ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS
- ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET
- ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET
- ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS
- ICP_QAT_FW_LA_GCM_PROTO
- ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL
- ICP_QAT_FW_LA_ICV_VER_STATUS_PASS
- ICP_QAT_FW_LA_NO_CMP_AUTH_RES
- ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER
- ICP_QAT_FW_LA_NO_PROTO
- ICP_QAT_FW_LA_NO_RET_AUTH_RES
- ICP_QAT_FW_LA_NO_UPDATE_STATE
- ICP_QAT_FW_LA_PARTIAL_END
- ICP_QAT_FW_LA_PARTIAL_GET
- ICP_QAT_FW_LA_PARTIAL_MID
- ICP_QAT_FW_LA_PARTIAL_NONE
- ICP_QAT_FW_LA_PARTIAL_SET
- ICP_QAT_FW_LA_PARTIAL_START
- ICP_QAT_FW_LA_PROTO_GET
- ICP_QAT_FW_LA_PROTO_SET
- ICP_QAT_FW_LA_RET_AUTH_GET
- ICP_QAT_FW_LA_RET_AUTH_RES
- ICP_QAT_FW_LA_RET_AUTH_SET
- ICP_QAT_FW_LA_SNOW_3G_PROTO
- ICP_QAT_FW_LA_TRNG_STATUS_FAIL
- ICP_QAT_FW_LA_TRNG_STATUS_PASS
- ICP_QAT_FW_LA_UPDATE_STATE
- ICP_QAT_FW_LA_UPDATE_STATE_GET
- ICP_QAT_FW_LA_UPDATE_STATE_SET
- ICP_QAT_FW_LA_ZUC_3G_PROTO
- ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET
- ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET
- ICP_QAT_FW_LOOPBACK
- ICP_QAT_FW_NULL_REQ_SERV_ID
- ICP_QAT_FW_NUM_LONGWORDS_1
- ICP_QAT_FW_NUM_LONGWORDS_10
- ICP_QAT_FW_NUM_LONGWORDS_13
- ICP_QAT_FW_NUM_LONGWORDS_2
- ICP_QAT_FW_NUM_LONGWORDS_3
- ICP_QAT_FW_NUM_LONGWORDS_4
- ICP_QAT_FW_NUM_LONGWORDS_5
- ICP_QAT_FW_NUM_LONGWORDS_6
- ICP_QAT_FW_NUM_LONGWORDS_7
- ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS
- ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK
- ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET
- ICP_QAT_FW_PKE_RESP_PKE_STAT_GET
- ICP_QAT_FW_REQ_DEFAULT_SZ
- ICP_QAT_FW_RESP_DEFAULT_SZ
- ICP_QAT_FW_SLICE_AUTH
- ICP_QAT_FW_SLICE_CIPHER
- ICP_QAT_FW_SLICE_COMP
- ICP_QAT_FW_SLICE_DELIMITER
- ICP_QAT_FW_SLICE_DRAM_RD
- ICP_QAT_FW_SLICE_DRAM_WR
- ICP_QAT_FW_SLICE_NULL
- ICP_QAT_FW_SLICE_XLAT
- ICP_QAT_FW_STATUS_GET
- ICP_QAT_FW_TRNG_DISABLE
- ICP_QAT_FW_TRNG_ENABLE
- ICP_QAT_HW_3DES_BLK_SZ
- ICP_QAT_HW_3DES_KEY_SZ
- ICP_QAT_HW_AES_128_F8_KEY_SZ
- ICP_QAT_HW_AES_128_KEY_SZ
- ICP_QAT_HW_AES_128_XTS_KEY_SZ
- ICP_QAT_HW_AES_192_F8_KEY_SZ
- ICP_QAT_HW_AES_192_KEY_SZ
- ICP_QAT_HW_AES_256_F8_KEY_SZ
- ICP_QAT_HW_AES_256_KEY_SZ
- ICP_QAT_HW_AES_256_XTS_KEY_SZ
- ICP_QAT_HW_AES_BLK_SZ
- ICP_QAT_HW_AES_CBC_MAC_KEY_SZ
- ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ
- ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ
- ICP_QAT_HW_AES_F9_STATE1_SZ
- ICP_QAT_HW_AES_F9_STATE2_SZ
- ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ
- ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ
- ICP_QAT_HW_AE_0
- ICP_QAT_HW_AE_1
- ICP_QAT_HW_AE_10
- ICP_QAT_HW_AE_11
- ICP_QAT_HW_AE_2
- ICP_QAT_HW_AE_3
- ICP_QAT_HW_AE_4
- ICP_QAT_HW_AE_5
- ICP_QAT_HW_AE_6
- ICP_QAT_HW_AE_7
- ICP_QAT_HW_AE_8
- ICP_QAT_HW_AE_9
- ICP_QAT_HW_AE_DELIMITER
- ICP_QAT_HW_ARC4_KEY_SZ
- ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC
- ICP_QAT_HW_AUTH_ALGO_AES_F9
- ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
- ICP_QAT_HW_AUTH_ALGO_DELIMITER
- ICP_QAT_HW_AUTH_ALGO_GALOIS_128
- ICP_QAT_HW_AUTH_ALGO_GALOIS_64
- ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
- ICP_QAT_HW_AUTH_ALGO_MD5
- ICP_QAT_HW_AUTH_ALGO_NULL
- ICP_QAT_HW_AUTH_ALGO_SHA1
- ICP_QAT_HW_AUTH_ALGO_SHA224
- ICP_QAT_HW_AUTH_ALGO_SHA256
- ICP_QAT_HW_AUTH_ALGO_SHA384
- ICP_QAT_HW_AUTH_ALGO_SHA3_256
- ICP_QAT_HW_AUTH_ALGO_SHA3_512
- ICP_QAT_HW_AUTH_ALGO_SHA512
- ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
- ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3
- ICP_QAT_HW_AUTH_CONFIG_BUILD
- ICP_QAT_HW_AUTH_COUNT_BUILD
- ICP_QAT_HW_AUTH_MODE0
- ICP_QAT_HW_AUTH_MODE1
- ICP_QAT_HW_AUTH_MODE2
- ICP_QAT_HW_AUTH_MODE_DELIMITER
- ICP_QAT_HW_AUTH_RESERVED_1
- ICP_QAT_HW_AUTH_RESERVED_2
- ICP_QAT_HW_AUTH_RESERVED_3
- ICP_QAT_HW_CIPHER_ALGO_3DES
- ICP_QAT_HW_CIPHER_ALGO_AES128
- ICP_QAT_HW_CIPHER_ALGO_AES192
- ICP_QAT_HW_CIPHER_ALGO_AES256
- ICP_QAT_HW_CIPHER_ALGO_ARC4
- ICP_QAT_HW_CIPHER_ALGO_DES
- ICP_QAT_HW_CIPHER_ALGO_KASUMI
- ICP_QAT_HW_CIPHER_ALGO_NULL
- ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2
- ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3
- ICP_QAT_HW_CIPHER_CBC_MODE
- ICP_QAT_HW_CIPHER_CONFIG_BUILD
- ICP_QAT_HW_CIPHER_CTR_MODE
- ICP_QAT_HW_CIPHER_DECRYPT
- ICP_QAT_HW_CIPHER_DELIMITER
- ICP_QAT_HW_CIPHER_ECB_MODE
- ICP_QAT_HW_CIPHER_ENCRYPT
- ICP_QAT_HW_CIPHER_F8_MODE
- ICP_QAT_HW_CIPHER_KEY_CONVERT
- ICP_QAT_HW_CIPHER_MODE_DELIMITER
- ICP_QAT_HW_CIPHER_NO_CONVERT
- ICP_QAT_HW_CIPHER_XTS_MODE
- ICP_QAT_HW_DES_BLK_SZ
- ICP_QAT_HW_DES_KEY_SZ
- ICP_QAT_HW_F9_FK_SZ
- ICP_QAT_HW_F9_IK_SZ
- ICP_QAT_HW_GALOIS_128_STATE1_SZ
- ICP_QAT_HW_GALOIS_E_CTR0_SZ
- ICP_QAT_HW_GALOIS_H_SZ
- ICP_QAT_HW_GALOIS_LEN_A_BITPOS
- ICP_QAT_HW_GALOIS_LEN_A_MASK
- ICP_QAT_HW_GALOIS_LEN_A_SZ
- ICP_QAT_HW_KASUMI_BLK_SZ
- ICP_QAT_HW_KASUMI_F8_KEY_SZ
- ICP_QAT_HW_KASUMI_F9_STATE1_SZ
- ICP_QAT_HW_KASUMI_F9_STATE2_SZ
- ICP_QAT_HW_KASUMI_KEY_SZ
- ICP_QAT_HW_MD5_STATE1_SZ
- ICP_QAT_HW_MD5_STATE2_SZ
- ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR
- ICP_QAT_HW_NULL_BLK_SZ
- ICP_QAT_HW_NULL_KEY_SZ
- ICP_QAT_HW_NULL_STATE1_SZ
- ICP_QAT_HW_NULL_STATE2_SZ
- ICP_QAT_HW_QAT_0
- ICP_QAT_HW_QAT_1
- ICP_QAT_HW_QAT_2
- ICP_QAT_HW_QAT_3
- ICP_QAT_HW_QAT_4
- ICP_QAT_HW_QAT_5
- ICP_QAT_HW_QAT_DELIMITER
- ICP_QAT_HW_SHA1_STATE1_SZ
- ICP_QAT_HW_SHA1_STATE2_SZ
- ICP_QAT_HW_SHA224_STATE1_SZ
- ICP_QAT_HW_SHA224_STATE2_SZ
- ICP_QAT_HW_SHA256_STATE1_SZ
- ICP_QAT_HW_SHA256_STATE2_SZ
- ICP_QAT_HW_SHA384_STATE1_SZ
- ICP_QAT_HW_SHA384_STATE2_SZ
- ICP_QAT_HW_SHA3_224_STATE1_SZ
- ICP_QAT_HW_SHA3_224_STATE2_SZ
- ICP_QAT_HW_SHA3_256_STATE1_SZ
- ICP_QAT_HW_SHA3_256_STATE2_SZ
- ICP_QAT_HW_SHA3_384_STATE1_SZ
- ICP_QAT_HW_SHA3_384_STATE2_SZ
- ICP_QAT_HW_SHA3_512_STATE1_SZ
- ICP_QAT_HW_SHA3_512_STATE2_SZ
- ICP_QAT_HW_SHA512_STATE1_SZ
- ICP_QAT_HW_SHA512_STATE2_SZ
- ICP_QAT_HW_SNOW_3G_BLK_SZ
- ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ
- ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ
- ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ
- ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ
- ICP_QAT_HW_ZUC_3G_BLK_SZ
- ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ
- ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ
- ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ
- ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ
- ICP_QAT_LOC_MEM0_MODE
- ICP_QAT_LOC_MEM1_MODE
- ICP_QAT_NN_MODE
- ICP_QAT_SHARED_USTORE_MODE
- ICP_QAT_SIMG_AE_INIT_SEQ_LEN
- ICP_QAT_SIMG_AE_INSTS_LEN
- ICP_QAT_SUOF_FID
- ICP_QAT_SUOF_MAJVER
- ICP_QAT_SUOF_MINVER
- ICP_QAT_SUOF_OBJ_ID_LEN
- ICP_QAT_UCLO_AE_ALL_CTX
- ICP_QAT_UCLO_MAX_AE
- ICP_QAT_UCLO_MAX_CTX
- ICP_QAT_UCLO_MAX_GPR_REG
- ICP_QAT_UCLO_MAX_LMEM_REG
- ICP_QAT_UCLO_MAX_UIMAGE
- ICP_QAT_UCLO_MAX_USTORE
- ICP_QAT_UCLO_MAX_XFER_REG
- ICP_QAT_UOF_FID
- ICP_QAT_UOF_IMAG
- ICP_QAT_UOF_IMEM
- ICP_QAT_UOF_INIT_EXPR
- ICP_QAT_UOF_INIT_EXPR_ENDIAN_SWAP
- ICP_QAT_UOF_INIT_REG
- ICP_QAT_UOF_INIT_REG_CTX
- ICP_QAT_UOF_LMEM_REGION
- ICP_QAT_UOF_LOCAL_SCOPE
- ICP_QAT_UOF_MAJVER
- ICP_QAT_UOF_MINVER
- ICP_QAT_UOF_OBJID_LEN
- ICP_QAT_UOF_OBJS
- ICP_QAT_UOF_SRAM_REGION
- ICP_QAT_UOF_STRT
- ICP_QAT_UOF_UMEM_REGION
- ICP_RAWCLK_NUM
- ICP_RESEND_MAP_SIZE
- ICP_RESET
- ICP_SR_ABS
- ICP_SR_RD_ABS
- ICP_SR_RD_REL
- ICP_SR_REL
- ICP_SR_WR_ABS
- ICP_SR_WR_REL
- ICP_TC_HPD_ENABLE
- ICP_TC_HPD_ENABLE_MASK
- ICP_TC_HPD_LONG_DETECT
- ICP_TC_HPD_SHORT_DETECT
- ICQ_DESTROYED
- ICQ_EXITED
- ICR
- ICR0
- ICR0_NMIE
- ICR0_NMIF
- ICR0_NMIL
- ICR1
- ICR1_IRQS
- ICR1_IRQS_EDGE_BOTH
- ICR1_IRQS_EDGE_FALLING
- ICR1_IRQS_EDGE_RISING
- ICR1_IRQS_LEVEL_LOW
- ICR1_IRQS_MASK
- ICRAM1
- ICRBN_A_CERR_SHFT
- ICRBN_A_ERR_MASK
- ICRBP_A_CERR_SHFT
- ICRBP_A_ERR_MASK
- ICRC_LENGTH
- ICRNL
- ICRXTX
- ICRX_EN_RISC_INT
- ICR_ACKNAK
- ICR_ADDR
- ICR_ADRR
- ICR_ALDIE
- ICR_ALL
- ICR_ARBITRATION_LOST
- ICR_ARBITRATION_PROGRESS
- ICR_ASSERT_ACK
- ICR_ASSERT_ATN
- ICR_ASSERT_BSY
- ICR_ASSERT_DATA
- ICR_ASSERT_RST
- ICR_ASSERT_SEL
- ICR_BASE
- ICR_BEIE
- ICR_BUSMODE_FM
- ICR_BUSMODE_HS
- ICR_DIFF_ENABLE
- ICR_EN_INT
- ICR_EN_RISC
- ICR_ET1
- ICR_ET2
- ICR_ET3
- ICR_ET6
- ICR_FM
- ICR_GCD
- ICR_GPIOEN
- ICR_HF0
- ICR_HF1
- ICR_HS
- ICR_IRFIE
- ICR_ITEIE
- ICR_ITEM
- ICR_IUE
- ICR_MA
- ICR_MASK
- ICR_MII_CH
- ICR_POL1
- ICR_POL2
- ICR_POL3
- ICR_POL5
- ICR_POL6
- ICR_RF_OVERFLOW
- ICR_RF_UNDERFLOW
- ICR_RREQ
- ICR_RXBUF
- ICR_RXERR
- ICR_SADIE
- ICR_SCLE
- ICR_SPITAS
- ICR_SSDIE
- ICR_START
- ICR_STOP
- ICR_TB
- ICR_TF_OVERFLOW
- ICR_TREQ
- ICR_TRI_STATE
- ICR_TXBUF_H
- ICR_TXBUF_L
- ICR_TXEND_H
- ICR_TXEND_L
- ICR_TXERR_H
- ICR_TXERR_L
- ICR_TX_UDR
- ICR_UR
- ICS
- ICS43432_FORMATS
- ICS43432_RATE_MAX
- ICS43432_RATE_MIN
- ICS91719
- ICS91720
- ICS932S401_CFG1_SPREAD
- ICS932S401_CPU_ALT
- ICS932S401_CPU_DIVISOR_SHIFT
- ICS932S401_DEVICE
- ICS932S401_FS_MASK
- ICS932S401_MN_ENABLED
- ICS932S401_M_MASK
- ICS932S401_PCI_DIVISOR_SHIFT
- ICS932S401_REG_CFG2
- ICS932S401_REG_CFG7
- ICS932S401_REG_CPU_DIVISOR
- ICS932S401_REG_CPU_M_CTRL
- ICS932S401_REG_CPU_N_CTRL
- ICS932S401_REG_CPU_SPREAD1
- ICS932S401_REG_CPU_SPREAD2
- ICS932S401_REG_CTRL
- ICS932S401_REG_DEVICE
- ICS932S401_REG_PCISRC_DIVISOR
- ICS932S401_REG_SRC_M_CTRL
- ICS932S401_REG_SRC_N_CTRL
- ICS932S401_REG_SRC_SPREAD1
- ICS932S401_REG_SRC_SPREAD2
- ICS932S401_REG_VENDOR_REV
- ICS932S401_REV
- ICS932S401_REV_SHIFT
- ICS932S401_SPREAD_MASK
- ICS932S401_SRC_ALT
- ICS932S401_SRC_DIVISOR_MASK
- ICS932S401_VENDOR
- ICS932S401_VENDOR_MASK
- ICSAR
- ICSCR
- ICSIER
- ICSK_ACK_NOW
- ICSK_ACK_PUSHED
- ICSK_ACK_PUSHED2
- ICSK_ACK_SCHED
- ICSK_ACK_TIMER
- ICSK_CA_PRIV_SIZE
- ICSK_TIME_DACK
- ICSK_TIME_EARLY_RETRANS
- ICSK_TIME_LOSS_PROBE
- ICSK_TIME_PROBE0
- ICSK_TIME_REO_TIMEOUT
- ICSK_TIME_RETRANS
- ICSPI_FRM_ERR
- ICSPI_PAR_ERROR_F
- ICSPI_PAR_ERROR_S
- ICSPI_PAR_ERROR_V
- ICSR
- ICSR2_NACKF
- ICSR_AL
- ICSR_BUSY
- ICSR_DTE
- ICSR_SCLM
- ICSR_SDAM
- ICSR_TACK
- ICSR_WAIT
- ICSSR
- ICST307_VCO_MAX
- ICST307_VCO_MIN
- ICST525_VCO_MAX_3V
- ICST525_VCO_MAX_5V
- ICST525_VCO_MIN
- ICSTART
- ICSTART_ICSTART
- ICST_H
- ICST_INTEGRATOR_AP_CM
- ICST_INTEGRATOR_AP_PCI
- ICST_INTEGRATOR_AP_SYS
- ICST_INTEGRATOR_CP_CM_CORE
- ICST_INTEGRATOR_CP_CM_MEM
- ICST_VERSATILE
- ICSWX_BUSY
- ICSWX_INITIATED
- ICSWX_REJECTED
- ICSWX_XERS0
- ICS_ARCIN_V5_IDEALTOFFSET
- ICS_ARCIN_V5_IDEOFFSET
- ICS_ARCIN_V5_IDESTEPPING
- ICS_ARCIN_V5_INTROFFSET
- ICS_ARCIN_V5_INTRSTAT
- ICS_ARCIN_V6_IDEALTOFFSET_1
- ICS_ARCIN_V6_IDEALTOFFSET_2
- ICS_ARCIN_V6_IDEOFFSET_1
- ICS_ARCIN_V6_IDEOFFSET_2
- ICS_ARCIN_V6_IDESTEPPING
- ICS_ARCIN_V6_INTROFFSET_1
- ICS_ARCIN_V6_INTROFFSET_2
- ICS_ARCIN_V6_INTRSTAT_1
- ICS_ARCIN_V6_INTRSTAT_2
- ICS_DOUBLE
- ICS_IDENT_OFFSET
- ICS_TYPE_A3IN
- ICS_TYPE_A3USER
- ICS_TYPE_NOTYPE
- ICS_TYPE_V5
- ICS_TYPE_V6
- ICTIMESYNCFLAG_PROBE
- ICTIMESYNCFLAG_SAMPLE
- ICTIMESYNCFLAG_SYNC
- ICTLR_COP_IEP_CLASS
- ICTLR_COP_IER
- ICTLR_COP_IER_CLR
- ICTLR_COP_IER_SET
- ICTLR_CPU_IEP_CLASS
- ICTLR_CPU_IEP_FIR
- ICTLR_CPU_IEP_FIR_CLR
- ICTLR_CPU_IEP_FIR_SET
- ICTLR_CPU_IEP_VFIQ
- ICTLR_CPU_IER
- ICTLR_CPU_IER_CLR
- ICTLR_CPU_IER_SET
- ICTL_ARB
- ICTL_FIFO
- ICTL_FIFO_MASK
- ICTL_ISKE
- ICTL_LPSW
- ICTL_OPEREXC
- ICTL_PINT
- ICTL_REQ
- ICTL_RRBE
- ICTL_SEL
- ICTL_SSKE
- ICTL_STCTL
- ICTL_TPROT
- ICTRL
- ICTRL0_AUTOINC
- ICTRL0_BYTEGRAN
- ICTRL0_COMMON
- ICTRL_EDC
- ICTRL_EICE
- ICTRL_EICP
- ICTRL_MASK
- ICT_COUNT
- ICT_SHIFT
- ICT_SIZE
- ICU1_SIZE
- ICU1_TYPE1_BASE
- ICU1_TYPE2_BASE
- ICU2_REG
- ICU2_SIZE
- ICU2_TYPE1_BASE
- ICU2_TYPE2_BASE
- ICU2_VIRT_BASE
- ICU_AP_FIQ_SEL_INT_NUM
- ICU_AP_GBL_IRQ_MSK
- ICU_AP_IRQ_SEL_INT_NUM
- ICU_CLRSPI_NSR_AH
- ICU_CLRSPI_NSR_AL
- ICU_CLR_SEI_AH
- ICU_CLR_SEI_AL
- ICU_DEFEATURE
- ICU_GROUP_SHIFT
- ICU_GRP_NSR
- ICU_GRP_REI
- ICU_GRP_SEI
- ICU_GRP_SR
- ICU_INT_CFG
- ICU_INT_CONF
- ICU_INT_CONF_AP_INT
- ICU_INT_CONF_CP_INT
- ICU_INT_CONF_IRQ
- ICU_INT_CONF_MASK
- ICU_INT_ENABLE
- ICU_INT_ROUTE_PJ4_FIQ
- ICU_INT_ROUTE_PJ4_IRQ
- ICU_INT_ROUTE_SP_IRQ
- ICU_INT_STATUS_0
- ICU_INT_STATUS_1
- ICU_IS_EDGE
- ICU_MAX_IRQS
- ICU_REG
- ICU_SATA0_ICU_ID
- ICU_SATA1_ICU_ID
- ICU_SETSPI_NSR_AH
- ICU_SETSPI_NSR_AL
- ICU_SET_SEI_AH
- ICU_SET_SEI_AL
- ICU_VIRT_BASE
- ICV
- ICV_10
- ICV_12
- ICV_13
- ICV_14
- ICV_15
- ICV_16
- ICV_4
- ICV_6
- ICV_8
- ICV_CMP_SIZE
- ICV_IS_512
- ICV_IS_512_SHIFT
- ICV_SIZE
- ICV_SIZE_SHIFT
- IC_ADC14B_12
- IC_ADC_GAIN_MASK
- IC_ADC_LEFT_GAIN_SHIFT
- IC_ADC_RIGHT_GAIN_SHIFT
- IC_ALM
- IC_ASSIGNCLR
- IC_ASSIGNRD
- IC_ASSIGNSET
- IC_BOOTP
- IC_CFG0CLR
- IC_CFG0RD
- IC_CFG0SET
- IC_CFG1CLR
- IC_CFG1RD
- IC_CFG1SET
- IC_CFG2CLR
- IC_CFG2RD
- IC_CFG2SET
- IC_CLR_INTR
- IC_CLR_STOP_DET
- IC_CLR_TX_ABRT
- IC_CMBP_1
- IC_CMBP_2
- IC_CODEC_CLK_EN
- IC_COMP_PARAM_1
- IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX
- IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH
- IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX
- IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH
- IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX
- IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH
- IC_CON
- IC_CONF
- IC_CONF_CSI_MEM_WR_EN
- IC_CONF_IC_GLB_LOC_A
- IC_CONF_KEY_COLOR_EN
- IC_CONF_PP_CMB
- IC_CONF_PP_CSC1
- IC_CONF_PP_CSC2
- IC_CONF_PP_EN
- IC_CONF_PP_ROT_EN
- IC_CONF_PRPENC_CSC1
- IC_CONF_PRPENC_EN
- IC_CONF_PRPENC_ROT_EN
- IC_CONF_PRPVF_CMB
- IC_CONF_PRPVF_CSC1
- IC_CONF_PRPVF_CSC2
- IC_CONF_PRPVF_EN
- IC_CONF_PRPVF_ROT_EN
- IC_CONF_RWS_EN
- IC_CON_MASTER_MODE_INDEX
- IC_CON_MASTER_MODE_WIDTH
- IC_CON_RESTART_EN_INDEX
- IC_CON_RESTART_EN_WIDTH
- IC_CON_RX_FIFO_FULL_HOLD_INDEX
- IC_CON_RX_FIFO_FULL_HOLD_WIDTH
- IC_CON_SLAVE_DISABLE_INDEX
- IC_CON_SLAVE_DISABLE_WIDTH
- IC_CON_SPEED_INDEX
- IC_CON_SPEED_WIDTH
- IC_CPEN
- IC_CPFREQ
- IC_CTRL_DIS
- IC_DATA_CMD
- IC_DATA_CMD_CMD_INDEX
- IC_DATA_CMD_CMD_WIDTH
- IC_DATA_CMD_STOP_INDEX
- IC_DATA_CMD_STOP_WIDTH
- IC_DIGMICEN
- IC_DIGMICFREQ
- IC_DM
- IC_DMA
- IC_DMA0
- IC_DMA1
- IC_DMA2
- IC_DMA3
- IC_DMA4
- IC_DMA5
- IC_DP
- IC_ENABLE
- IC_ENABLE_ABORT_INDEX
- IC_ENABLE_ABORT_WIDTH
- IC_ENABLE_EN_INDEX
- IC_ENABLE_EN_WIDTH
- IC_ENABLE_STATUS
- IC_ENABLE_STATUS_EN_INDEX
- IC_ENABLE_STATUS_EN_WIDTH
- IC_FALLINGCLR
- IC_FALLINGRD
- IC_FIRDAC_HSL_EN
- IC_FIRDAC_HSR_EN
- IC_FIRDAC_LOUT_EN
- IC_FLAG_CLEAR_LO
- IC_FLAG_CLEAR_XLO
- IC_GPIO
- IC_GPIO0
- IC_GPIO1
- IC_GPIO10
- IC_GPIO11_27
- IC_GPIO2
- IC_GPIO3
- IC_GPIO4
- IC_GPIO5
- IC_GPIO6
- IC_GPIO7
- IC_GPIO8
- IC_GPIO9
- IC_GROUP0_MASK
- IC_GROUP0_PEND
- IC_GROUP_OFFSET
- IC_HEADER_BYTES
- IC_HIT
- IC_HPLSELL
- IC_HPLSELR
- IC_HPRSELL
- IC_HPRSELR
- IC_HP_3DB_BOOST
- IC_HSINVEN
- IC_HSLEN
- IC_HSREN
- IC_ICEN
- IC_ICFT_MASK
- IC_ICFT_SHIFT
- IC_ICTT_MASK
- IC_IDMAC_1
- IC_IDMAC_1_CB0_BURST_16
- IC_IDMAC_1_CB1_BURST_16
- IC_IDMAC_1_CB2_BURST_16
- IC_IDMAC_1_CB3_BURST_16
- IC_IDMAC_1_CB4_BURST_16
- IC_IDMAC_1_CB5_BURST_16
- IC_IDMAC_1_CB6_BURST_16
- IC_IDMAC_1_CB7_BURST_16
- IC_IDMAC_1_PP_FLIP_RS
- IC_IDMAC_1_PP_ROT_MASK
- IC_IDMAC_1_PP_ROT_OFFSET
- IC_IDMAC_1_PRPENC_FLIP_RS
- IC_IDMAC_1_PRPENC_ROT_MASK
- IC_IDMAC_1_PRPENC_ROT_OFFSET
- IC_IDMAC_1_PRPVF_FLIP_RS
- IC_IDMAC_1_PRPVF_ROT_MASK
- IC_IDMAC_1_PRPVF_ROT_OFFSET
- IC_IDMAC_2
- IC_IDMAC_2_PP_HEIGHT_MASK
- IC_IDMAC_2_PP_HEIGHT_OFFSET
- IC_IDMAC_2_PRPENC_HEIGHT_MASK
- IC_IDMAC_2_PRPENC_HEIGHT_OFFSET
- IC_IDMAC_2_PRPVF_HEIGHT_MASK
- IC_IDMAC_2_PRPVF_HEIGHT_OFFSET
- IC_IDMAC_3
- IC_IDMAC_3_PP_WIDTH_MASK
- IC_IDMAC_3_PP_WIDTH_OFFSET
- IC_IDMAC_3_PRPENC_WIDTH_MASK
- IC_IDMAC_3_PRPENC_WIDTH_OFFSET
- IC_IDMAC_3_PRPVF_WIDTH_MASK
- IC_IDMAC_3_PRPVF_WIDTH_OFFSET
- IC_IDMAC_4
- IC_INFERIORITY_A
- IC_INFERIORITY_B
- IC_INFO
- IC_INT0ENABLE_LO
- IC_INT0ENABLE_XLO
- IC_INT0STATUS_LO
- IC_INT0STATUS_XLO
- IC_INTR_MASK
- IC_INTR_MASK_TX_EMPTY_INDEX
- IC_INTR_MASK_TX_EMPTY_WIDTH
- IC_INTR_STAT
- IC_LADCEN
- IC_LCD
- IC_LDACEN
- IC_LIF_STATISTICS_LIF_NUMBER_CPU
- IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0
- IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1
- IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0
- IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1
- IC_LINEIN1SEL
- IC_LINEIN2SEL
- IC_LOG_DATA_LOG_ID_DCX_LOG
- IC_LOG_DATA_LOG_ID_DEBUG_LOG
- IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG
- IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG
- IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG
- IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG
- IC_LOG_DATA_LOG_ID_LEARN_LOG
- IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG
- IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG
- IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG
- IC_MACPHY_MODE
- IC_MASKCLR
- IC_MASKRD
- IC_MASKSET
- IC_MATCH_FL_HCIBUS
- IC_MATCH_FL_HCIREV
- IC_MATCH_FL_HCIVER
- IC_MATCH_FL_LMPSUBV
- IC_MICDIFSEL
- IC_MICIN1SEL
- IC_MICIN2SEL
- IC_MICINLEN
- IC_MICINREN
- IC_MIC_MAX_GAIN
- IC_MONOL
- IC_MONOR
- IC_NUM_OPS
- IC_NUM_TASKS
- IC_ODIE
- IC_OPUS
- IC_OST
- IC_OST0
- IC_OST1
- IC_OST2
- IC_OST3
- IC_PIC1
- IC_PIC2
- IC_PLL
- IC_PLL_MAX_OFFSET
- IC_PLL_SECTION
- IC_POR
- IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0
- IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1
- IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0
- IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1
- IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0
- IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1
- IC_POS
- IC_PP_RSC
- IC_PROTO
- IC_PRP_ENC_RSC
- IC_PRP_VF_RSC
- IC_QUEUE_BYTES
- IC_RADCEN
- IC_RARP
- IC_RAW_INTR_STAT
- IC_RAW_INTR_STAT_RX_FULL_INDEX
- IC_RAW_INTR_STAT_RX_FULL_WIDTH
- IC_RAW_INTR_STAT_STOP_DET_INDEX
- IC_RAW_INTR_STAT_STOP_DET_WIDTH
- IC_RAW_INTR_STAT_TX_ABRT_INDEX
- IC_RAW_INTR_STAT_TX_ABRT_WIDTH
- IC_RAW_INTR_STAT_TX_EMPTY_INDEX
- IC_RAW_INTR_STAT_TX_EMPTY_WIDTH
- IC_RDACEN
- IC_REF
- IC_REQ0INT
- IC_REQ1INT
- IC_RISINGCLR
- IC_RISINGRD
- IC_RTC1Hz
- IC_RTCAlrm
- IC_RXFLR
- IC_RXOSRSEL
- IC_RXPGAL
- IC_RXPGAL_MASK
- IC_RXPGAL_SHIFT
- IC_RXPGAR
- IC_RXPGAR_MASK
- IC_RXPGAR_SHIFT
- IC_RX_ENABLE_MONO
- IC_RX_ENABLE_STEREO
- IC_SPEN
- IC_SPSELL
- IC_SPSELR
- IC_SRCCLR
- IC_SRCRD
- IC_SRCSET
- IC_Ser0UDC
- IC_Ser1SDLC
- IC_Ser1UART
- IC_Ser2ICP
- IC_Ser3UART
- IC_Ser4MCP
- IC_Ser4SSP
- IC_TAR
- IC_TASK_ENCODER
- IC_TASK_POST_PROCESSOR
- IC_TASK_PRP
- IC_TASK_VIEWFINDER
- IC_TESTBIT
- IC_TXFLR
- IC_TX_ABRT_7B_ADDR_NOACK
- IC_TX_ABRT_ARB_LOST
- IC_TX_ABRT_SOURCE
- IC_TX_ENABLE
- IC_TYPE_MASK
- IC_USE_DHCP
- IC_VER
- IC_VERRSION
- IC_VERSION_MASK
- IC_VER_A
- IC_VER_AB
- IC_VER_B
- IC_VER_C
- IC_VER_D
- IC_VersionCut_C
- IC_VersionCut_D
- IC_VersionCut_E
- IC_WAKECLR
- IC_WAKERD
- IC_WAKESET
- ID
- ID0
- ID01
- ID0_ATOSNS
- ID0_CTTW
- ID0_EXIDS
- ID0_NTS
- ID0_NUMIRPT
- ID0_NUMSIDB
- ID0_NUMSMRG
- ID0_PTFS_NO_AARCH32
- ID0_PTFS_NO_AARCH32S
- ID0_S1TS
- ID0_S2TS
- ID0_SMS
- ID1
- ID10
- ID11
- ID12
- ID13
- ID14
- ID15
- ID16
- ID1_CHIPID_M
- ID1_CHIPID_S
- ID1_NUMCB
- ID1_NUMPAGENDXB
- ID1_NUMS2CB
- ID1_PAGESIZE
- ID1_REVISION_M
- ID1_REVISION_S
- ID1_START_SW
- ID2
- ID2C
- ID2_IAS
- ID2_OAS
- ID2_PTFS_16K
- ID2_PTFS_4K
- ID2_PTFS_64K
- ID2_UBS
- ID2_VMID16
- ID3
- ID4
- ID5
- ID6
- ID7
- ID7_MAJOR
- ID7_MINOR
- ID8
- ID9
- IDAC_CURRENT_SINKING_BIT_MASK
- IDAC_CURRENT_SINKING_ENABLE
- IDAC_MANUAL_CONTROL
- IDAC_MANUAL_CONTROL_BIT_MASK
- IDATA
- IDATASIZE
- IDA_BITMAP_BITS
- IDA_BITMAP_LONGS
- IDA_BLOCK_SIZE
- IDA_BUG_ON
- IDA_CHUNK_SHIFT
- IDA_CHUNK_SIZE
- IDA_INDEX_BITS
- IDA_INIT
- IDA_INIT_FLAGS
- IDA_MAX_PATH
- IDA_PRELOAD_SIZE
- IDA_SIZE_LOG
- IDBEN_MASK
- IDBEN_SHIFT
- IDBL
- IDB_QSIZE
- IDB_QUEUE
- IDCCOMP
- IDCNTL
- IDCODE_ID_MASK
- IDCODE_ID_SHIFT
- IDCODE_MFG_MASK
- IDCODE_MFG_SHIFT
- IDCODE_PUB
- IDCODE_REV_MASK
- IDCODE_REV_SHIFT
- IDCODE_VER_MASK
- IDCODE_VER_SHIFT
- IDCY_MASK
- IDC_AUDIT_COMPLETION
- IDC_AUDIT_TIMESTAMP
- IDC_CERR1
- IDC_CERR2
- IDC_CERR3
- IDC_COMP_TOV
- IDC_DEVICE_STATE_CHANGE
- IDC_DISABLE
- IDC_ENABLE
- IDC_ENABLED
- IDC_EXTEND_TOV
- IDC_HEARTBEAT_FAILURE
- IDC_INVALL
- IDC_LDLCK
- IDC_LOCK_RECOVERY_OWNER_MASK
- IDC_LOCK_RECOVERY_STAGE1
- IDC_LOCK_RECOVERY_STAGE2
- IDC_LOCK_RECOVERY_STATE_MASK
- IDC_LOCK_RECOVERY_STATE_SHIFT_BITS
- IDC_LOCK_TIMEOUT
- IDC_NIC_FW_REPORTED_FAILURE
- IDC_PEG_HALT_STATUS_CHANGE
- IDC_UNALL
- IDC_UNLINE
- IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK
- IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT
- IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK
- IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT
- IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK
- IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT
- IDDQ_BIAS
- IDDQ_GLOBAL_PWR
- IDE
- IDE0_MAJOR
- IDE1
- IDE1_MAJOR
- IDE1_PRIMARY_BASE
- IDE1_SECONDARY_BASE
- IDE2
- IDE2_MAJOR
- IDE2_PRIMARY_BASE
- IDE2_SECONDARY_BASE
- IDE3_MAJOR
- IDE4_MAJOR
- IDE5_MAJOR
- IDE6_MAJOR
- IDE7_MAJOR
- IDE8_MAJOR
- IDE9_MAJOR
- IDEA0_MARK
- IDEA1_MARK
- IDEA2_MARK
- IDEAL_RATIO_DECIMAL_DEPTH
- IDEAL_RATIO_RATE
- IDEAPAD_BASE
- IDEAPAD_EC_TIMEOUT
- IDEAPAD_RFKILL_DEV_NUM
- IDECD_DEBUG_LOG
- IDECD_VERSION
- IDECFG
- IDECFG_IDEEN
- IDECFG_MDMA
- IDECFG_MODE_MASK
- IDECFG_MODE_SHIFT
- IDECFG_PIO
- IDECFG_UDMA
- IDECFG_WST_MASK
- IDECFG_WST_SHIFT
- IDECS0_MARK
- IDECS1_MARK
- IDECTRL
- IDECTRL_ADDR_ALTSTATUS
- IDECTRL_ADDR_CMD
- IDECTRL_ADDR_COMMAND
- IDECTRL_ADDR_CTL
- IDECTRL_ADDR_DATA
- IDECTRL_ADDR_DEVICE
- IDECTRL_ADDR_ERROR
- IDECTRL_ADDR_FEATURE
- IDECTRL_ADDR_LBAH
- IDECTRL_ADDR_LBAL
- IDECTRL_ADDR_LBAM
- IDECTRL_ADDR_NSECT
- IDECTRL_ADDR_STATUS
- IDECTRL_CS0N
- IDECTRL_CS1N
- IDECTRL_DIORN
- IDECTRL_DIOWN
- IDECTRL_INTRQ
- IDECTRL_IORDY
- IDED0_MARK
- IDED10_MARK
- IDED11_MARK
- IDED12_MARK
- IDED13_MARK
- IDED14_MARK
- IDED15_MARK
- IDED1_MARK
- IDED2_MARK
- IDED3_MARK
- IDED4_MARK
- IDED5_MARK
- IDED6_MARK
- IDED7_MARK
- IDED8_MARK
- IDED9_MARK
- IDEDATAIN
- IDEDATAOUT
- IDEFLOPPY_CAPABILITIES_PAGE
- IDEFLOPPY_FLEXIBLE_DISK_PAGE
- IDEFLOPPY_IOCTL_FORMAT_GET_CAPACITY
- IDEFLOPPY_IOCTL_FORMAT_GET_PROGRESS
- IDEFLOPPY_IOCTL_FORMAT_START
- IDEFLOPPY_IOCTL_FORMAT_SUPPORTED
- IDEFLOPPY_MAX_PC_RETRIES
- IDEFLOPPY_PC_DELAY
- IDEINT_MARK
- IDEIORDY_MARK
- IDEIORD_MARK
- IDEIOWR_MARK
- IDEMDMADATAIN
- IDEMDMADATAOUT
- IDEMDMAOP
- IDENT
- IDENTIFIERFLAG
- IDENTIFY
- IDENTIFY_BASE
- IDENTITY_FRAME
- IDENTITY_FRAME_BIT
- IDENTITY_NR
- IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
- IDENTITY_RATIO
- IDENTMAP_ALL
- IDENTMAP_AZALIA
- IDENTMAP_GFX
- IDENT_ADDR
- IDERST_MARK
- IDETAPE_BLOCK_DESCRIPTOR
- IDETAPE_CAPABILITIES_PAGE
- IDETAPE_DEBUG_LOG
- IDETAPE_DIR_NONE
- IDETAPE_DIR_READ
- IDETAPE_DIR_WRITE
- IDETAPE_DSC_MA_FAST
- IDETAPE_DSC_MA_SLOW
- IDETAPE_DSC_MA_THRESHOLD
- IDETAPE_DSC_MA_TIMEOUT
- IDETAPE_DSC_RW_MAX
- IDETAPE_DSC_RW_MIN
- IDETAPE_DSC_RW_TIMEOUT
- IDETAPE_FIFO_THRESHOLD
- IDETAPE_LU_EOT_MASK
- IDETAPE_LU_LOAD_MASK
- IDETAPE_LU_RETENSION_MASK
- IDETAPE_MAJOR
- IDETAPE_MAX_PC_RETRIES
- IDETAPE_SPACE_OVER_FILEMARK
- IDETAPE_SPACE_TO_EOD
- IDETAPE_VERSION
- IDETIM
- IDEUDMADATAIN
- IDEUDMADATAOUT
- IDEUDMADEBUG
- IDEUDMAOP
- IDEUDMAOP_RWOP
- IDEUDMAOP_UEN
- IDEUDMASTS
- IDEUDMASTS_DMAIDE
- IDEUDMASTS_INTIDE
- IDEUDMASTS_N4X
- IDEUDMASTS_NDI
- IDEUDMASTS_NDO
- IDEUDMASTS_SBUSY
- IDEV_ABORT_PATH_ACTIVE
- IDEV_ABORT_PATH_RESUME_PENDING
- IDEV_ALLOCATED
- IDEV_GONE
- IDEV_IO_NCQERROR
- IDEV_IO_READY
- IDEV_RNC_LLHANG_ENABLED
- IDEV_START_PENDING
- IDEV_STOP_PENDING
- IDE_0
- IDE_A0_MARK
- IDE_A1_MARK
- IDE_A2_MARK
- IDE_ACKCHANGE
- IDE_AFLAG_ADDRESS_VALID
- IDE_AFLAG_BUSY
- IDE_AFLAG_CLIK_DRIVE
- IDE_AFLAG_DETECT_BS
- IDE_AFLAG_DOOR_LOCKED
- IDE_AFLAG_DRQ_INTERRUPT
- IDE_AFLAG_FILEMARK
- IDE_AFLAG_FULL_CAPS_PAGE
- IDE_AFLAG_IGNORE_DSC
- IDE_AFLAG_LE_SPEED_FIELDS
- IDE_AFLAG_MEDIUM_PRESENT
- IDE_AFLAG_NO_AUTOCLOSE
- IDE_AFLAG_NO_EJECT
- IDE_AFLAG_NO_SPEED_SELECT
- IDE_AFLAG_PLAY_AUDIO_OK
- IDE_AFLAG_PRE_ATAPI12
- IDE_AFLAG_SANYO_3CD
- IDE_AFLAG_SRFP
- IDE_AFLAG_TOCADDR_AS_BCD
- IDE_AFLAG_TOCTRACKS_AS_BCD
- IDE_AFLAG_TOC_VALID
- IDE_AFLAG_VERTOS_300_SSD
- IDE_AFLAG_VERTOS_600_ESD
- IDE_AFLAG_ZIP_DRIVE
- IDE_ALT_START
- IDE_AU1XXX_BURSTMODE
- IDE_BASE
- IDE_BUSY
- IDE_CAP
- IDE_CAST
- IDE_CAST_CMD_MASK
- IDE_CAST_CMD_SHIFT
- IDE_CAST_D0_SHIFT
- IDE_CAST_D1_SHIFT
- IDE_CAST_DRV_MASK
- IDE_CD_CAPABILITIES
- IDE_CFG
- IDE_CFG_CABLE
- IDE_CFG_CHANEN
- IDE_CONFIG
- IDE_CONTROL
- IDE_CS
- IDE_CS0_MARK
- IDE_CS1_MARK
- IDE_D0_MARK
- IDE_D0_SHIFT
- IDE_D10_MARK
- IDE_D11_MARK
- IDE_D12_MARK
- IDE_D13_MARK
- IDE_D14_MARK
- IDE_D15_MARK
- IDE_D1_MARK
- IDE_D1_SHIFT
- IDE_D2_MARK
- IDE_D3_MARK
- IDE_D4_MARK
- IDE_D5_MARK
- IDE_D6_MARK
- IDE_D7_MARK
- IDE_D8_MARK
- IDE_D9_MARK
- IDE_DBG_FUNC
- IDE_DBG_PC
- IDE_DBG_PROBE
- IDE_DBG_RQ
- IDE_DBG_SENSE
- IDE_DEFAULT_MAX_FAILURES
- IDE_DEVSET
- IDE_DFLAG_ATTACH
- IDE_DFLAG_BLOCKED
- IDE_DFLAG_DMA_PIO_RETRY
- IDE_DFLAG_DOORLOCKING
- IDE_DFLAG_DSC_OVERLAP
- IDE_DFLAG_FORCED_GEOM
- IDE_DFLAG_FORMAT_IN_PROGRESS
- IDE_DFLAG_ID_READ
- IDE_DFLAG_KEEP_SETTINGS
- IDE_DFLAG_LBA
- IDE_DFLAG_LBA48
- IDE_DFLAG_MEDIA_CHANGED
- IDE_DFLAG_NICE1
- IDE_DFLAG_NIEN_QUIRK
- IDE_DFLAG_NODMA
- IDE_DFLAG_NOFLUSH
- IDE_DFLAG_NOHPA
- IDE_DFLAG_NOPROBE
- IDE_DFLAG_NOWERR
- IDE_DFLAG_NO_IO_32BIT
- IDE_DFLAG_NO_UNLOAD
- IDE_DFLAG_NO_UNMASK
- IDE_DFLAG_PARKED
- IDE_DFLAG_POST_RESET
- IDE_DFLAG_PRESENT
- IDE_DFLAG_REMOVABLE
- IDE_DFLAG_SLEEPING
- IDE_DFLAG_UDMA33_WARNED
- IDE_DFLAG_UNMASK
- IDE_DFLAG_USING_DMA
- IDE_DFLAG_WCACHE
- IDE_DFLAG_WP
- IDE_DIAG
- IDE_DIRECTION_MARK
- IDE_DISK_MINORS
- IDE_DOORLOCK
- IDE_DOORUNLOCK
- IDE_DRIVE_TASK_IN
- IDE_DRIVE_TASK_INVALID
- IDE_DRIVE_TASK_NO_DATA
- IDE_DRIVE_TASK_OUT
- IDE_DRIVE_TASK_RAW_WRITE
- IDE_DRIVE_TASK_SET_XFER
- IDE_DRQ
- IDE_DRV_ERROR_EOD
- IDE_DRV_ERROR_FILEMARK
- IDE_DRV_ERROR_GENERAL
- IDE_DRV_MASK
- IDE_DTC
- IDE_EJECT
- IDE_ERR
- IDE_ERROR
- IDE_ETC
- IDE_ETC_UDMA_MASK
- IDE_EXBUF_ENB_MARK
- IDE_FTFLAG_FLAGGED
- IDE_FTFLAG_IN_DATA
- IDE_FTFLAG_OUT_DATA
- IDE_FTFLAG_SET_IN_FLAGS
- IDE_GD_DEBUG_LOG
- IDE_GD_VERSION
- IDE_GUID
- IDE_HFLAGS_AMD
- IDE_HFLAGS_HPT3XX
- IDE_HFLAGS_PDC202XX
- IDE_HFLAG_4DRIVES
- IDE_HFLAG_ABUSE_DMA_MODES
- IDE_HFLAG_ABUSE_FAST_DEVSEL
- IDE_HFLAG_ABUSE_PREFETCH
- IDE_HFLAG_BROKEN_ALTSTATUS
- IDE_HFLAG_CLEAR_SIMPLEX
- IDE_HFLAG_CS5520
- IDE_HFLAG_DTC2278
- IDE_HFLAG_ERROR_STOPS_FIFO
- IDE_HFLAG_IO_32BIT
- IDE_HFLAG_ISA_PORTS
- IDE_HFLAG_MMIO
- IDE_HFLAG_NON_BOOTABLE
- IDE_HFLAG_NO_ATAPI_DMA
- IDE_HFLAG_NO_AUTODMA
- IDE_HFLAG_NO_DMA
- IDE_HFLAG_NO_DSC
- IDE_HFLAG_NO_IO_32BIT
- IDE_HFLAG_NO_LBA48
- IDE_HFLAG_NO_LBA48_DMA
- IDE_HFLAG_NO_SET_MODE
- IDE_HFLAG_NO_UNMASK_IRQS
- IDE_HFLAG_OFF_BOARD
- IDE_HFLAG_PIO_NO_BLACKLIST
- IDE_HFLAG_POST_SET_MODE
- IDE_HFLAG_QD_2ND_PORT
- IDE_HFLAG_SERIALIZE
- IDE_HFLAG_SERIALIZE_DMA
- IDE_HFLAG_SET_PIO_MODE_KEEP_DMA
- IDE_HFLAG_SINGLE
- IDE_HFLAG_TRM290
- IDE_HFLAG_TRUST_BIOS_FOR_DMA
- IDE_HFLAG_UNMASK_IRQS
- IDE_HOB_STD_IN_FLAGS
- IDE_HOB_STD_OUT_FLAGS
- IDE_HOST_BUSY
- IDE_IDENTIFY
- IDE_IFR
- IDE_IMPLY
- IDE_IN
- IDE_INIT_DEV_PARMS
- IDE_INTERNAL_PM
- IDE_INTERRUPT
- IDE_INTR_DEVICE
- IDE_INTR_DMA
- IDE_INT_MARK
- IDE_IODACK_MARK
- IDE_IODREQ_MARK
- IDE_IORDY_MARK
- IDE_IORD_MARK
- IDE_IOWR_MARK
- IDE_IO_BAR
- IDE_IRQ
- IDE_IRQ_EDGE
- IDE_KAUAI_PIO_CONFIG
- IDE_KAUAI_POLL_CONFIG
- IDE_KAUAI_ULTRA_CONFIG
- IDE_MSR_REG
- IDE_NICE_0
- IDE_NICE_1
- IDE_NICE_2
- IDE_NICE_ATAPI_OVERLAP
- IDE_NICE_DSC_OVERLAP
- IDE_NR_PORTS
- IDE_OFFSET
- IDE_PADS_ENABLE
- IDE_PALM_ATA_PRI_CTL_OFFSET
- IDE_PALM_ATA_PRI_REG_OFFSET
- IDE_PFLAG_PROBING
- IDE_PHYS
- IDE_PM
- IDE_PMAC_DEBUG
- IDE_PM_COMPLETED
- IDE_PM_FLUSH_CACHE
- IDE_PM_IDLE
- IDE_PM_RESTORE_DMA
- IDE_PM_RESTORE_PIO
- IDE_PM_STANDBY
- IDE_PM_START_RESUME
- IDE_PM_START_SUSPEND
- IDE_PROC_DEVSET
- IDE_READ
- IDE_READY
- IDE_READ_VRFY
- IDE_REGS_ADDR
- IDE_REGS_CNT
- IDE_REG_SHIFT
- IDE_RST_MARK
- IDE_SEG_NUM
- IDE_SFLAG_RECALIBRATE
- IDE_SFLAG_SET_GEOMETRY
- IDE_SFLAG_SET_MULTMODE
- IDE_SMI
- IDE_STANDBY
- IDE_STAT
- IDE_SYSCLK_66_NS
- IDE_SYSCLK_NS
- IDE_TASKFILE_STD_IN_FLAGS
- IDE_TASKFILE_STD_OUT_FLAGS
- IDE_TFLAG_CUSTOM_HANDLER
- IDE_TFLAG_DMA_PIO_FALLBACK
- IDE_TFLAG_DYN
- IDE_TFLAG_FS
- IDE_TFLAG_IO_16BIT
- IDE_TFLAG_LBA48
- IDE_TFLAG_MULTI_PIO
- IDE_TFLAG_SET_XFER
- IDE_TFLAG_WRITE
- IDE_TIMING_8BIT
- IDE_TIMING_ACT8B
- IDE_TIMING_ACTIVE
- IDE_TIMING_ALL
- IDE_TIMING_CONFIG
- IDE_TIMING_CYC8B
- IDE_TIMING_CYCLE
- IDE_TIMING_REC8B
- IDE_TIMING_RECOVER
- IDE_TIMING_SETUP
- IDE_TIMING_UDMA
- IDE_VALID_DEVICE
- IDE_VALID_ERROR
- IDE_VALID_FEATURE
- IDE_VALID_IN_HOB
- IDE_VALID_IN_TF
- IDE_VALID_LBA
- IDE_VALID_LBAH
- IDE_VALID_LBAL
- IDE_VALID_LBAM
- IDE_VALID_NSECT
- IDE_VALID_OUT_HOB
- IDE_VALID_OUT_TF
- IDE_WAKEUP_DELAY
- IDE_WAKEUP_DELAY_MS
- IDE_WRITE
- IDF_MAX
- IDF_MIN
- IDF_RECV
- IDF_SEND
- IDF_STOP
- IDH_CLR_MSG_BUF
- IDH_EVENT_MAX
- IDH_FAIL
- IDH_FLR_NOTIFICATION
- IDH_FLR_NOTIFICATION_CMPL
- IDH_IRQ_FORCE_DPM_LEVEL
- IDH_IRQ_GET_PP_MCLK
- IDH_IRQ_GET_PP_SCLK
- IDH_LOG_VF_ERROR
- IDH_PTYPE_ACABLE
- IDH_PTYPE_AMA
- IDH_PTYPE_HUB
- IDH_PTYPE_PCABLE
- IDH_PTYPE_PERIPH
- IDH_PTYPE_UNDEF
- IDH_QUERY_ALIVE
- IDH_READY_TO_ACCESS_GPU
- IDH_REL_GPU_FINI_ACCESS
- IDH_REL_GPU_INIT_ACCESS
- IDH_REQ_GPU_FINI_ACCESS
- IDH_REQ_GPU_INIT_ACCESS
- IDH_REQ_GPU_RESET_ACCESS
- IDH_SUCCESS
- IDI48_NGPIO
- IDIAG_BARACC_ACC_MOD_INDX
- IDIAG_BARACC_BAR_0
- IDIAG_BARACC_BAR_1
- IDIAG_BARACC_BAR_2
- IDIAG_BARACC_BAR_NUM_INDX
- IDIAG_BARACC_BAR_SZE_INDX
- IDIAG_BARACC_OFF_SET_INDX
- IDIAG_BARACC_REG_VAL_INDX
- IDIAG_CTLACC_REGID_INDX
- IDIAG_CTLACC_VALUE_INDX
- IDIAG_DRBACC_REGID_INDX
- IDIAG_DRBACC_VALUE_INDX
- IDIAG_EXTACC_EXMAP_INDX
- IDIAG_MBXACC_DPCNT_INDX
- IDIAG_MBXACC_DPMAP_INDX
- IDIAG_MBXACC_MBCMD_INDX
- IDIAG_MBXACC_WDCNT_INDX
- IDIAG_PCICFG_COUNT_INDX
- IDIAG_PCICFG_VALUE_INDX
- IDIAG_PCICFG_WHERE_INDX
- IDIAG_QUEACC_COUNT_INDX
- IDIAG_QUEACC_INDEX_INDX
- IDIAG_QUEACC_OFFST_INDX
- IDIAG_QUEACC_QUEID_INDX
- IDIAG_QUEACC_QUETP_INDX
- IDIAG_QUEACC_VALUE_INDX
- IDIHASHMSK
- IDIN_MARK
- IDIO_16_EXTENT
- IDIO_16_NGPIO
- IDIO_24_NGPIO
- IDIRECTORY
- IDIROC
- IDIR_INT_OUT0
- IDIR_INT_OUT1
- IDIR_INT_OUT2
- IDIR_INT_OUT3
- IDISP_CODEC_MASK
- IDISP_DAI_COUNT
- IDISP_INTEL_VENDOR_ID
- IDISP_ROUTE_COUNT
- IDISP_VID_INTEL
- IDI_48_EXTENT
- IDL
- IDLAPI_ARM_SHIFT
- IDLD
- IDLE
- IDLEHEADHI
- IDLEHEADLO
- IDLEMODE_ALT_MARK_SPACE
- IDLEMODE_ALT_ONE_ZERO
- IDLEMODE_FLAGS
- IDLEMODE_MARK
- IDLEMODE_MASK
- IDLEMODE_ONE
- IDLEMODE_SPACE
- IDLEMODE_ZERO
- IDLEOK
- IDLEREQ
- IDLESTATE_DESC
- IDLESTATE_DISABLE
- IDLESTATE_LATENCY
- IDLESTATE_NAME
- IDLESTATE_POWER
- IDLESTATE_TIME
- IDLESTATE_USAGE
- IDLE_CALC_LIMIT
- IDLE_CHANNELS_MASK
- IDLE_CHK
- IDLE_CHK_MAX_ENTRIES_SIZE
- IDLE_CHK_RESULT_HDR_DWORDS
- IDLE_CHK_RESULT_REG_HDR_DWORDS
- IDLE_CHK_RULE_SIZE_DWORDS
- IDLE_CHK_SEVERITY_ERROR
- IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC
- IDLE_CHK_SEVERITY_WARNING
- IDLE_CLEAR_BIT
- IDLE_CMD_ABORT
- IDLE_CMD_COMPLETED
- IDLE_CMD_DEVICE_RESET
- IDLE_CMD_SCSIREQ
- IDLE_CMD_SCSI_RESET_END
- IDLE_CMD_SCSI_RESET_START
- IDLE_CMD_SEND_INT
- IDLE_CMD_STATUS_FAILURE
- IDLE_CMD_STATUS_SUCCESS
- IDLE_CMD_STOP_CHIP
- IDLE_CMD_STOP_CHIP_SEND_INT
- IDLE_CRU
- IDLE_CYCLE_MASK
- IDLE_CYCLE_VALUE
- IDLE_EMIFS_REQUEST
- IDLE_EN
- IDLE_EN_BIT
- IDLE_FORCE_MWAIT
- IDLE_HALT
- IDLE_INTERVAL
- IDLE_IRQ_BIT
- IDLE_LEAKY_MAX
- IDLE_MAX_COUNT
- IDLE_MSG_TYPE_MASK
- IDLE_MSG_TYPE_SHIFT
- IDLE_NOMWAIT
- IDLE_NO_OVERRIDE
- IDLE_OFF_MASK
- IDLE_OFF_VALUE
- IDLE_ON_MASK
- IDLE_ON_VALUE
- IDLE_PAYLOAD_MASK
- IDLE_PAYLOAD_SHIFT
- IDLE_PHYSICAL_LINK_MGMT
- IDLE_POLL
- IDLE_POLL_COUNT
- IDLE_POLL_COUNT_MASK
- IDLE_POWERSAVE_OFF
- IDLE_POWER_MGMT
- IDLE_RATE_TYPE
- IDLE_REGS_COUNT
- IDLE_SETUP_STAGE
- IDLE_SHORT_TIMEOUT
- IDLE_SLOPE
- IDLE_SLOPE_1
- IDLE_SLOPE_2
- IDLE_SLOPE_MASK
- IDLE_SMA
- IDLE_STATE
- IDLE_STATE_ENTER_SEQ_NORET
- IDLE_STATUS_CALIBERR_MASK
- IDLE_STATUS_CALIBERR_SHIFT
- IDLE_STATUS_CALIB_DONE
- IDLE_STATUS_CALIB_RES_MASK
- IDLE_STATUS_CALIB_RES_SHIFT
- IDLE_STATUS_CMB
- IDLE_STATUS_DMAR
- IDLE_STATUS_DMAW
- IDLE_STATUS_MASK
- IDLE_STATUS_RXMAC
- IDLE_STATUS_RXMAC_BUSY
- IDLE_STATUS_RXQ
- IDLE_STATUS_RXQ_BUSY
- IDLE_STATUS_SFORCE_MASK
- IDLE_STATUS_SFORCE_SHIFT
- IDLE_STATUS_SMB
- IDLE_STATUS_TXMAC
- IDLE_STATUS_TXMAC_BUSY
- IDLE_STATUS_TXQ
- IDLE_STATUS_TXQ_BUSY
- IDLE_TIMEOUT
- IDLE_TIME_MASK
- IDLE_TO_EXECUTE
- IDLE_TO_EXECUTEOK
- IDLE_VGPU_IDR
- IDLE_WAIT_CYCLES
- IDLE_WORKER_TIMEOUT
- IDLE_WRITEBACK
- IDLIF_ARM_SHIFT
- IDLLB_ARM_SHIFT
- IDLPER_ARM_SHIFT
- IDLTIM_ARM_SHIFT
- IDLWDT_ARM_SHIFT
- IDLXORP_ARM_SHIFT
- IDLY_CODE
- IDLY_CODE_VAL
- IDL_CLKOUT_ARM_SHIFT
- IDMA32C_CFGH_DST_PER
- IDMA32C_CFGH_DST_PER_EXT
- IDMA32C_CFGH_RD_ISSUE_THD
- IDMA32C_CFGH_RW_ISSUE_THD
- IDMA32C_CFGH_SRC_PER
- IDMA32C_CFGH_SRC_PER_EXT
- IDMA32C_CFGL_CH_DRAIN
- IDMA32C_CFGL_DST_BURST_ALIGN
- IDMA32C_CFGL_DST_OPT_BL
- IDMA32C_CFGL_SRC_BURST_ALIGN
- IDMA32C_CFGL_SRC_OPT_BL
- IDMA32C_CTLH_BLOCK_TS
- IDMA32C_CTLH_BLOCK_TS_MASK
- IDMA32C_CTLH_DONE
- IDMA32C_FP_PSIZE_CH0
- IDMA32C_FP_PSIZE_CH1
- IDMA32C_FP_UPDATE
- IDMA32_MSIZE_1
- IDMA32_MSIZE_16
- IDMA32_MSIZE_2
- IDMA32_MSIZE_32
- IDMA32_MSIZE_4
- IDMA32_MSIZE_8
- IDMA64C_CFGH_DST_PER
- IDMA64C_CFGH_RD_ISSUE_THD
- IDMA64C_CFGH_SRC_PER
- IDMA64C_CFGH_WR_ISSUE_THD
- IDMA64C_CFGL_CH_DRAIN
- IDMA64C_CFGL_CH_SUSP
- IDMA64C_CFGL_DST_BURST_ALIGN
- IDMA64C_CFGL_DST_OPT_BL
- IDMA64C_CFGL_FIFO_EMPTY
- IDMA64C_CFGL_SRC_BURST_ALIGN
- IDMA64C_CFGL_SRC_OPT_BL
- IDMA64C_CTLH_BLOCK_TS
- IDMA64C_CTLH_BLOCK_TS_MASK
- IDMA64C_CTLH_DONE
- IDMA64C_CTLL_DST_FIX
- IDMA64C_CTLL_DST_INC
- IDMA64C_CTLL_DST_MSIZE
- IDMA64C_CTLL_DST_WIDTH
- IDMA64C_CTLL_FC_M2P
- IDMA64C_CTLL_FC_P2M
- IDMA64C_CTLL_INT_EN
- IDMA64C_CTLL_LLP_D_EN
- IDMA64C_CTLL_LLP_S_EN
- IDMA64C_CTLL_SRC_FIX
- IDMA64C_CTLL_SRC_INC
- IDMA64C_CTLL_SRC_MSIZE
- IDMA64C_CTLL_SRC_WIDTH
- IDMA64_BUSWIDTHS
- IDMA64_CFG
- IDMA64_CFG_DMA_EN
- IDMA64_CH_CFG_HI
- IDMA64_CH_CFG_LO
- IDMA64_CH_CTL_HI
- IDMA64_CH_CTL_LO
- IDMA64_CH_DAR
- IDMA64_CH_DSR
- IDMA64_CH_DSTAT
- IDMA64_CH_DSTATAR
- IDMA64_CH_EN
- IDMA64_CH_LENGTH
- IDMA64_CH_LLP
- IDMA64_CH_SAR
- IDMA64_CH_SGR
- IDMA64_CH_SSTAT
- IDMA64_CH_SSTATAR
- IDMA64_CLEAR
- IDMA64_INT_BLOCK
- IDMA64_INT_DST_TRAN
- IDMA64_INT_ERROR
- IDMA64_INT_SRC_TRAN
- IDMA64_INT_XFER
- IDMA64_MASK
- IDMA64_NR_CHAN
- IDMA64_RAW
- IDMA64_STATUS
- IDMA64_STATUS_INT
- IDMAC_64ADDR_SET_BUFFER1_SIZE
- IDMAC_ADC_0
- IDMAC_ADC_1
- IDMAC_ADC_2
- IDMAC_ADC_3
- IDMAC_ADC_4
- IDMAC_ADC_5
- IDMAC_ADC_6
- IDMAC_ADC_7
- IDMAC_ALT_SEP_ALPHA
- IDMAC_BAND_EN
- IDMAC_CHA_BUSY
- IDMAC_CHA_EN
- IDMAC_CHA_PRI
- IDMAC_CH_LOCK_EN_1
- IDMAC_CH_LOCK_EN_2
- IDMAC_CONF
- IDMAC_DES0_CES
- IDMAC_DES0_CH
- IDMAC_DES0_DIC
- IDMAC_DES0_ER
- IDMAC_DES0_FD
- IDMAC_DES0_LD
- IDMAC_DES0_OWN
- IDMAC_IC_0
- IDMAC_IC_1
- IDMAC_IC_10
- IDMAC_IC_11
- IDMAC_IC_12
- IDMAC_IC_13
- IDMAC_IC_2
- IDMAC_IC_3
- IDMAC_IC_4
- IDMAC_IC_5
- IDMAC_IC_6
- IDMAC_IC_7
- IDMAC_IC_8
- IDMAC_IC_9
- IDMAC_INT_CLR
- IDMAC_OWN_CLR64
- IDMAC_PF_0
- IDMAC_PF_1
- IDMAC_PF_2
- IDMAC_PF_3
- IDMAC_PF_4
- IDMAC_PF_5
- IDMAC_PF_6
- IDMAC_PF_7
- IDMAC_SDC_0
- IDMAC_SDC_1
- IDMAC_SDC_2
- IDMAC_SDC_3
- IDMAC_SEP_ALPHA
- IDMAC_SET_BUFFER1_SIZE
- IDMAC_SUB_ADDR_0
- IDMAC_SUB_ADDR_1
- IDMAC_SUB_ADDR_2
- IDMAC_WM_EN
- IDMAP_CONV_IDTONAME
- IDMAP_CONV_NAMETOID
- IDMAP_DIR_SIZE
- IDMAP_INVALID_ADDR
- IDMAP_NAMESZ
- IDMAP_PGTABLE_LEVELS
- IDMAP_STATUS_AGAIN
- IDMAP_STATUS_INVALIDMSG
- IDMAP_STATUS_LOOKUPFAIL
- IDMAP_STATUS_SUCCESS
- IDMAP_TEXT
- IDMAP_TYPE_GROUP
- IDMAP_TYPE_USER
- IDMA_ADC_SYS1_CMD
- IDMA_ADC_SYS1_RD
- IDMA_ADC_SYS1_WR
- IDMA_ADC_SYS2_CMD
- IDMA_ADC_SYS2_RD
- IDMA_ADC_SYS2_WR
- IDMA_BD_CM
- IDMA_BD_DBO_BE
- IDMA_BD_DBO_LE
- IDMA_BD_DDN
- IDMA_BD_DDTB
- IDMA_BD_DGBL
- IDMA_BD_I
- IDMA_BD_L
- IDMA_BD_SBO_BE
- IDMA_BD_SBO_LE
- IDMA_BD_SDN
- IDMA_BD_SDTB
- IDMA_BD_SGBL
- IDMA_BD_V
- IDMA_BD_W
- IDMA_CHAN_INVALID
- IDMA_CONFB
- IDMA_CPB_TBL_SIZE
- IDMA_CTL_ATA_NIEN
- IDMA_CTL_GO
- IDMA_CTL_RST_ATA
- IDMA_CTL_RST_IDMA
- IDMA_DCM_DINC
- IDMA_DCM_DMA_WRAP_1024
- IDMA_DCM_DMA_WRAP_128
- IDMA_DCM_DMA_WRAP_2048
- IDMA_DCM_DMA_WRAP_256
- IDMA_DCM_DMA_WRAP_512
- IDMA_DCM_DMA_WRAP_64
- IDMA_DCM_DMA_WRAP_MASK
- IDMA_DCM_DT
- IDMA_DCM_ERM
- IDMA_DCM_FB
- IDMA_DCM_LP
- IDMA_DCM_SD_MASK
- IDMA_DCM_SD_MEM2MEM
- IDMA_DCM_SD_MEM2PER
- IDMA_DCM_SD_PER2MEM
- IDMA_DCM_SINC
- IDMA_DCM_TC2
- IDMA_EVENT_BC
- IDMA_EVENT_EDN
- IDMA_EVENT_OB
- IDMA_EVENT_SC
- IDMA_IC_0
- IDMA_IC_1
- IDMA_IC_10
- IDMA_IC_11
- IDMA_IC_12
- IDMA_IC_13
- IDMA_IC_2
- IDMA_IC_3
- IDMA_IC_4
- IDMA_IC_5
- IDMA_IC_6
- IDMA_IC_7
- IDMA_IC_8
- IDMA_IC_9
- IDMA_PF_BSP
- IDMA_PF_QP
- IDMA_PF_U_IN
- IDMA_PF_U_OUT
- IDMA_PF_V_IN
- IDMA_PF_V_OUT
- IDMA_PF_Y_IN
- IDMA_PF_Y_OUT
- IDMA_SDC_BG
- IDMA_SDC_FG
- IDMA_SDC_MASK
- IDMA_SDC_PARTIAL
- IDMA_STAT_CPBERR
- IDMA_STAT_DONE
- IDMA_STAT_ERR
- IDMA_STAT_LGCY
- IDMA_STAT_PERR
- IDMA_STAT_PSD
- IDMA_STAT_STPD
- IDMA_STAT_UIRQ
- IDMON
- IDM_CTRL_DIRECT_OFFSET
- IDM_RST_BIT
- IDNAME_PARTITION
- IDNAME_RIGIDDISK
- IDON
- IDONM
- IDO_STRT
- IDPDH
- IDPDL
- IDPROM_ADDRESS
- IDP_ALT_FLASH_PHYS
- IDP_BUSY_LED
- IDP_COREVOLT_PHYS
- IDP_COREVOLT_SIZE
- IDP_COREVOLT_VIRT
- IDP_CPLD_FLASH_WE
- IDP_CPLD_GPIOH_DIR
- IDP_CPLD_GPIOH_VALUE
- IDP_CPLD_GPIOL_DIR
- IDP_CPLD_GPIOL_VALUE
- IDP_CPLD_KB_COL_HIGH
- IDP_CPLD_KB_COL_LOW
- IDP_CPLD_KB_ROW
- IDP_CPLD_LCD
- IDP_CPLD_LED_CONTROL
- IDP_CPLD_MISC_CTRL
- IDP_CPLD_MISC_STATUS
- IDP_CPLD_PCCARD0_STATUS
- IDP_CPLD_PCCARD1_STATUS
- IDP_CPLD_PCCARD_EN
- IDP_CPLD_PCCARD_PWR
- IDP_CPLD_PERIPH_PWR
- IDP_CPLD_PHYS
- IDP_CPLD_REV
- IDP_CPLD_SIZE
- IDP_CPLD_VIRT
- IDP_ETH_PHYS
- IDP_FLASH_PHYS
- IDP_HB_LED
- IDP_IDE_PHYS
- IDP_LEDS_MASK
- IDP_MEDIAQ_PHYS
- IDR
- IDR0
- IDR0_8723B
- IDR0_ASID16
- IDR0_ATS
- IDR0_CD2L
- IDR0_COHACC
- IDR0_DATA_PORT
- IDR0_HYP
- IDR0_MSI
- IDR0_PRI
- IDR0_S1P
- IDR0_S2P
- IDR0_SEV
- IDR0_STALL_MODEL
- IDR0_STALL_MODEL_FORCE
- IDR0_STALL_MODEL_STALL
- IDR0_ST_LVL
- IDR0_ST_LVL_2LVL
- IDR0_TTENDIAN
- IDR0_TTENDIAN_BE
- IDR0_TTENDIAN_LE
- IDR0_TTENDIAN_MIXED
- IDR0_TTF
- IDR0_TTF_AARCH32_64
- IDR0_TTF_AARCH64
- IDR0_VMID16
- IDR1_CMDQS
- IDR1_CRAM_POINTER
- IDR1_EVTQS
- IDR1_PRIQS
- IDR1_QUEUES_PRESET
- IDR1_REL
- IDR1_SIDSIZE
- IDR1_SSIDSIZE
- IDR1_TABLES_PRESET
- IDR2_CRAM_DATA
- IDR3_WAVE_DATA
- IDR4
- IDR4_8723B
- IDR4_WAVE_PTR_LOW
- IDR5_GRAN16K
- IDR5_GRAN4K
- IDR5_GRAN64K
- IDR5_OAS
- IDR5_OAS_32_BIT
- IDR5_OAS_36_BIT
- IDR5_OAS_40_BIT
- IDR5_OAS_42_BIT
- IDR5_OAS_44_BIT
- IDR5_OAS_48_BIT
- IDR5_OAS_52_BIT
- IDR5_STALL_MAX
- IDR5_VAX
- IDR5_VAX_52_BIT
- IDR5_WAVE_PTR_HI
- IDR6_TIMER_CTRL
- IDR7_WAVE_ROMRAM
- IDREG
- IDR_CI
- IDR_CI0_SHIFT
- IDR_CI1_SHIFT
- IDR_EEPROM
- IDR_EP
- IDR_EP_MASK
- IDR_EP_SHIFT
- IDR_FREE
- IDR_INDEX_BITS
- IDR_INIT
- IDR_INIT_BASE
- IDR_MAJOR
- IDR_MAX_PATH
- IDR_MINOR
- IDR_P0_SHIFT
- IDR_P1_SHIFT
- IDR_PRELOAD_SIZE
- IDR_RT_MARKER
- IDR_W5300
- IDSETR1
- IDSR_CLEAR
- IDS_ARBLOST
- IDS_DONE
- IDS_NACK
- IDT434_REG_BASE
- IDT4_CMD_READ
- IDT4_CMD_SEARCH144
- IDT4_CMD_WRITE
- IDT4_DATARY_BASE_ADR0
- IDT4_GMR_BASE0
- IDT4_GMR_BASE1
- IDT4_GMR_BASE2
- IDT4_MSKARY_BASE_ADR0
- IDT4_SCR_ADR0
- IDT75N43102
- IDT75P52100
- IDT77105_CTRHI
- IDT77105_CTRLO
- IDT77105_CTRSEL
- IDT77105_CTRSEL_RCC
- IDT77105_CTRSEL_RHEC
- IDT77105_CTRSEL_SEC
- IDT77105_CTRSEL_TCC
- IDT77105_DIAG
- IDT77105_DIAG_FTD
- IDT77105_DIAG_ITHE
- IDT77105_DIAG_ITPE
- IDT77105_DIAG_LCMASK
- IDT77105_DIAG_LC_LINE_LOOPBACK
- IDT77105_DIAG_LC_NORMAL
- IDT77105_DIAG_LC_PHY_LOOPBACK
- IDT77105_DIAG_MPCS
- IDT77105_DIAG_RFLUSH
- IDT77105_DIAG_ROS
- IDT77105_DIAG_UMODE
- IDT77105_GETSTAT
- IDT77105_GETSTATZ
- IDT77105_ISTAT
- IDT77105_ISTAT_GOODSIG
- IDT77105_ISTAT_HECERR
- IDT77105_ISTAT_RFO
- IDT77105_ISTAT_RSCC
- IDT77105_ISTAT_RSE
- IDT77105_ISTAT_SCR
- IDT77105_ISTAT_TPE
- IDT77105_LEDHEC
- IDT77105_LEDHEC_DRHC
- IDT77105_LEDHEC_DTHC
- IDT77105_LEDHEC_RLS
- IDT77105_LEDHEC_RPWMASK
- IDT77105_LEDHEC_RPW_1
- IDT77105_LEDHEC_RPW_2
- IDT77105_LEDHEC_RPW_4
- IDT77105_LEDHEC_RPW_8
- IDT77105_LEDHEC_TFS
- IDT77105_LEDHEC_TLS
- IDT77105_MCR
- IDT77105_MCR_DREC
- IDT77105_MCR_DRIC
- IDT77105_MCR_ECEIO
- IDT77105_MCR_EIP
- IDT77105_MCR_HALTTX
- IDT77105_MCR_TDPC
- IDT77105_MCR_UMODE
- IDT77105_MCR_UPLO
- IDT77105_RESTART_TIMER_PERIOD
- IDT77105_STATS_TIMER_PERIOD
- IDT77252_BIT_INIT
- IDT77252_BIT_INTERRUPT
- IDT77252_PRV_PADDR
- IDT77252_PRV_POOL
- IDT77252_PRV_TBD
- IDTCPS_RIO_DOMAIN
- IDTECH_IDT1221U_PID
- IDTECH_VID
- IDTE_GLOBAL
- IDTE_GUEST_ASCE
- IDTE_LOCAL
- IDTE_NODAT
- IDTE_PTOA
- IDT_89HPESX_DESC
- IDT_89HPESX_VER
- IDT_AUX_ERR_REPORT_EN
- IDT_AUX_PORT_ERR_CAP_EN
- IDT_AUX_PORT_ERR_LOG_I2C
- IDT_AUX_PORT_ERR_LOG_JTAG
- IDT_BARSETUP_ATRAN_DIR
- IDT_BARSETUP_ATRAN_FLD
- IDT_BARSETUP_ATRAN_LUT12
- IDT_BARSETUP_ATRAN_LUT24
- IDT_BARSETUP_ATRAN_MASK
- IDT_BARSETUP_EN
- IDT_BARSETUP_MODE_CFG
- IDT_BARSETUP_PREF
- IDT_BARSETUP_SIZE_CFG
- IDT_BARSETUP_SIZE_FLD
- IDT_BARSETUP_SIZE_MASK
- IDT_BARSETUP_TPART_FLD
- IDT_BARSETUP_TPART_MASK
- IDT_BARSETUP_TYPE_32
- IDT_BARSETUP_TYPE_64
- IDT_BARSETUP_TYPE_FLD
- IDT_BARSETUP_TYPE_MASK
- IDT_BAR_CNT
- IDT_CFGBLK_ERR_CAPTURE_EN
- IDT_CFGBLK_ERR_REPORT
- IDT_CFGBLK_ERR_REPORT_GENPW
- IDT_CLOCK_MULT
- IDT_CMD_LEARN
- IDT_CMD_READ
- IDT_CMD_SEARCH
- IDT_CMD_WRITE
- IDT_DATARY_BASE_ADR0
- IDT_DBELL_MASK
- IDT_DEFAULT_ROUTE
- IDT_DEV_CTRL_1
- IDT_DEV_CTRL_1_GENPW
- IDT_DEV_CTRL_1_PRSTBEH
- IDT_DIR_SIZE_ALIGN
- IDT_DSTQID_LEN
- IDT_DSTQID_POS
- IDT_ENTRIES
- IDT_ERR_CAP
- IDT_ERR_CAP_LOG_OVERWR
- IDT_ERR_RD
- IDT_FPSEL1_LEN
- IDT_FPSEL1_POS
- IDT_FPSEL_LEN
- IDT_FPSEL_POS
- IDT_GMR_BASE_ADR0
- IDT_I2C_MCTRL
- IDT_I2C_MCTRL_GENPW
- IDT_INMSG_MASK
- IDT_ISLTL_ADDRESS_CAP
- IDT_JTAG_CTRL
- IDT_JTAG_CTRL_GENPW
- IDT_LANE_CTRL
- IDT_LANE_CTRL_BC
- IDT_LANE_CTRL_GENPW
- IDT_LANE_DFE_1_BC
- IDT_LANE_DFE_2_BC
- IDT_LANE_ERR_REPORT_EN
- IDT_LANE_ERR_REPORT_EN_BC
- IDT_LAR_ADR0
- IDT_LAR_MODE144
- IDT_LT_ERR_REPORT_EN
- IDT_LUTOFFSET_BAR_FLD
- IDT_LUTOFFSET_BAR_MASK
- IDT_LUTOFFSET_INDEX_FLD
- IDT_LUTOFFSET_INDEX_MASK
- IDT_LUTUDATA_PART_FLD
- IDT_LUTUDATA_PART_MASK
- IDT_LUTUDATA_VALID
- IDT_MANID
- IDT_MAX_NR_MWS
- IDT_MAX_NR_PARTS
- IDT_MAX_NR_PEERS
- IDT_MAX_NR_PORTS
- IDT_MSG_CNT
- IDT_MSG_MASK
- IDT_MSKARY_BASE_ADR0
- IDT_MTBL_ENTRY_CNT
- IDT_MW_DIR
- IDT_MW_LUT12
- IDT_MW_LUT24
- IDT_NAME
- IDT_NFPSEL1_LEN
- IDT_NFPSEL1_POS
- IDT_NFPSEL_LEN
- IDT_NFPSEL_POS
- IDT_NO_ROUTE
- IDT_NTCTL_ATP
- IDT_NTCTL_CPEN
- IDT_NTCTL_IDPROTDIS
- IDT_NTCTL_RNS
- IDT_NTGSIGNAL_SET
- IDT_NTINTMSK_ALL
- IDT_NTINTMSK_DBELL
- IDT_NTINTMSK_MSG
- IDT_NTINTMSK_SEVENT
- IDT_NTINTMSK_TMPSENSOR
- IDT_NTINTSTS_DBELL
- IDT_NTINTSTS_MSG
- IDT_NTINTSTS_SEVENT
- IDT_NTINTSTS_TMPSENSOR
- IDT_NTMTBLDATA_ATP_TRANS
- IDT_NTMTBLDATA_CNS_INV
- IDT_NTMTBLDATA_PART_FLD
- IDT_NTMTBLDATA_PART_MASK
- IDT_NTMTBLDATA_REQID_FLD
- IDT_NTMTBLDATA_REQID_MASK
- IDT_NTMTBLDATA_RNS_INV
- IDT_NTMTBLDATA_VALID
- IDT_NT_BARLIMIT0
- IDT_NT_BARLIMIT1
- IDT_NT_BARLIMIT2
- IDT_NT_BARLIMIT3
- IDT_NT_BARLIMIT4
- IDT_NT_BARLIMIT5
- IDT_NT_BARLTBASE0
- IDT_NT_BARLTBASE1
- IDT_NT_BARLTBASE2
- IDT_NT_BARLTBASE3
- IDT_NT_BARLTBASE4
- IDT_NT_BARLTBASE5
- IDT_NT_BARSETUP0
- IDT_NT_BARSETUP1
- IDT_NT_BARSETUP2
- IDT_NT_BARSETUP3
- IDT_NT_BARSETUP4
- IDT_NT_BARSETUP5
- IDT_NT_BARUTBASE0
- IDT_NT_BARUTBASE1
- IDT_NT_BARUTBASE2
- IDT_NT_BARUTBASE3
- IDT_NT_BARUTBASE4
- IDT_NT_BARUTBASE5
- IDT_NT_GASAADDR
- IDT_NT_GASADATA
- IDT_NT_INDBELLMSK
- IDT_NT_INDBELLSTS
- IDT_NT_INMSG0
- IDT_NT_INMSG1
- IDT_NT_INMSG2
- IDT_NT_INMSG3
- IDT_NT_INMSGSRC0
- IDT_NT_INMSGSRC1
- IDT_NT_INMSGSRC2
- IDT_NT_INMSGSRC3
- IDT_NT_LUTLDATA
- IDT_NT_LUTMDATA
- IDT_NT_LUTOFFSET
- IDT_NT_LUTUDATA
- IDT_NT_MSGSTS
- IDT_NT_MSGSTSMSK
- IDT_NT_NTCEEM
- IDT_NT_NTCTL
- IDT_NT_NTGSIGNAL
- IDT_NT_NTIERRORMSK0
- IDT_NT_NTIERRORMSK1
- IDT_NT_NTINTMSK
- IDT_NT_NTINTSTS
- IDT_NT_NTMTBLADDR
- IDT_NT_NTMTBLDATA
- IDT_NT_NTMTBLSTS
- IDT_NT_NTSDATA
- IDT_NT_NTUEEM
- IDT_NT_OUTDBELLSET
- IDT_NT_OUTMSG0
- IDT_NT_OUTMSG1
- IDT_NT_OUTMSG2
- IDT_NT_OUTMSG3
- IDT_NT_PCICMDSTS
- IDT_NT_PCIEDCAP
- IDT_NT_PCIEDCAP2
- IDT_NT_PCIEDCTL2
- IDT_NT_PCIEDCTLSTS
- IDT_NT_PCIELCAP
- IDT_NT_PCIELCTLSTS
- IDT_NT_PMCSR
- IDT_NT_REQIDCAP
- IDT_OUTMSG_MASK
- IDT_PCICMDSTS_BME
- IDT_PCICMDSTS_IOAE
- IDT_PCICMDSTS_MAE
- IDT_PCIEDCAP_MPAYLOAD_FLD
- IDT_PCIEDCAP_MPAYLOAD_MASK
- IDT_PCIEDCAP_MPAYLOAD_S1024
- IDT_PCIEDCAP_MPAYLOAD_S128
- IDT_PCIEDCAP_MPAYLOAD_S2048
- IDT_PCIEDCAP_MPAYLOAD_S256
- IDT_PCIEDCAP_MPAYLOAD_S512
- IDT_PCIEDCTLSTS_MPS_FLD
- IDT_PCIEDCTLSTS_MPS_MASK
- IDT_PCIEDCTLSTS_MPS_S1024
- IDT_PCIEDCTLSTS_MPS_S128
- IDT_PCIEDCTLSTS_MPS_S2048
- IDT_PCIEDCTLSTS_MPS_S256
- IDT_PCIEDCTLSTS_MPS_S4096
- IDT_PCIEDCTLSTS_MPS_S512
- IDT_PCIELCAP_PORTNUM_FLD
- IDT_PCIELCAP_PORTNUM_MASK
- IDT_PCIELCTLSTS_CLS_FLD
- IDT_PCIELCTLSTS_CLS_MASK
- IDT_PCIELCTLSTS_NLW_FLD
- IDT_PCIELCTLSTS_NLW_MASK
- IDT_PCIELCTLSTS_SCLK_COM
- IDT_PCIE_REGSIZE
- IDT_PCI_DEVICE_IDS
- IDT_PORT_ERR_REPORT_EN
- IDT_PORT_ERR_REPORT_EN_BC
- IDT_PORT_INIT_TX_ACQUIRED
- IDT_PORT_ISERR_DET
- IDT_PORT_ISERR_REPORT_EN
- IDT_PORT_ISERR_REPORT_EN_BC
- IDT_PORT_OPS
- IDT_PORT_OPS_BC
- IDT_PORT_OPS_GENPW
- IDT_PORT_OPS_LL_ELOG
- IDT_PORT_OPS_LT_ELOG
- IDT_PORT_OPS_PL_ELOG
- IDT_PW_INFO_CSR
- IDT_REG_ALIGN
- IDT_REG_PCI_MAX
- IDT_REG_SW_MAX
- IDT_REQIDCAP_REQID_FLD
- IDT_REQIDCAP_REQID_MASK
- IDT_RIO_DOMAIN
- IDT_RIO_DOMAIN_MASK
- IDT_SCR_ADR0
- IDT_SEMSK_GSIGNAL
- IDT_SEMSK_LINKDN
- IDT_SEMSK_LINKUP
- IDT_SOFT_RESET
- IDT_SOFT_RESET_REQ
- IDT_SSR0_ADR0
- IDT_SSR1_ADR0
- IDT_SWPARTxSTS_DMA
- IDT_SWPARTxSTS_NT
- IDT_SWPARTxSTS_SCC
- IDT_SWPARTxSTS_SCI
- IDT_SWPARTxSTS_STATE_ACT
- IDT_SWPARTxSTS_STATE_DIS
- IDT_SWPARTxSTS_STATE_FLD
- IDT_SWPARTxSTS_STATE_MASK
- IDT_SWPARTxSTS_STATE_RES
- IDT_SWPARTxSTS_US
- IDT_SWPARTxSTS_USID_FLD
- IDT_SWPARTxSTS_USID_MASK
- IDT_SWPORTxSTS_DEVNUM_FLD
- IDT_SWPORTxSTS_DEVNUM_MASK
- IDT_SWPORTxSTS_DS
- IDT_SWPORTxSTS_LINKUP
- IDT_SWPORTxSTS_MODE_DIS
- IDT_SWPORTxSTS_MODE_DS
- IDT_SWPORTxSTS_MODE_FLD
- IDT_SWPORTxSTS_MODE_MASK
- IDT_SWPORTxSTS_MODE_NT
- IDT_SWPORTxSTS_MODE_NTDMA
- IDT_SWPORTxSTS_MODE_UNAT
- IDT_SWPORTxSTS_MODE_US
- IDT_SWPORTxSTS_MODE_USDMA
- IDT_SWPORTxSTS_MODE_USNT
- IDT_SWPORTxSTS_MODE_USNTDMA
- IDT_SWPORTxSTS_OMCC
- IDT_SWPORTxSTS_OMCI
- IDT_SWPORTxSTS_SWPART_FLD
- IDT_SWPORTxSTS_SWPART_MASK
- IDT_SWPxMSGCTL_PART_FLD
- IDT_SWPxMSGCTL_PART_MASK
- IDT_SWPxMSGCTL_REG_FLD
- IDT_SWPxMSGCTL_REG_MASK
- IDT_SW_BCVSTS
- IDT_SW_CTL
- IDT_SW_EEPROMINTF
- IDT_SW_GDBELLSTS
- IDT_SW_GPECTL
- IDT_SW_GPESTS
- IDT_SW_IOEXPADDR0
- IDT_SW_IOEXPADDR1
- IDT_SW_IOEXPADDR2
- IDT_SW_IOEXPADDR3
- IDT_SW_IOEXPADDR4
- IDT_SW_IOEXPADDR5
- IDT_SW_NTP0_BARLIMIT0
- IDT_SW_NTP0_BARLIMIT1
- IDT_SW_NTP0_BARLIMIT2
- IDT_SW_NTP0_BARLIMIT3
- IDT_SW_NTP0_BARLIMIT4
- IDT_SW_NTP0_BARLIMIT5
- IDT_SW_NTP0_BARLTBASE0
- IDT_SW_NTP0_BARLTBASE1
- IDT_SW_NTP0_BARLTBASE2
- IDT_SW_NTP0_BARLTBASE3
- IDT_SW_NTP0_BARLTBASE4
- IDT_SW_NTP0_BARLTBASE5
- IDT_SW_NTP0_BARSETUP0
- IDT_SW_NTP0_BARSETUP1
- IDT_SW_NTP0_BARSETUP2
- IDT_SW_NTP0_BARSETUP3
- IDT_SW_NTP0_BARSETUP4
- IDT_SW_NTP0_BARSETUP5
- IDT_SW_NTP0_BARUTBASE0
- IDT_SW_NTP0_BARUTBASE1
- IDT_SW_NTP0_BARUTBASE2
- IDT_SW_NTP0_BARUTBASE3
- IDT_SW_NTP0_BARUTBASE4
- IDT_SW_NTP0_BARUTBASE5
- IDT_SW_NTP0_NTCTL
- IDT_SW_NTP0_PCIECMDSTS
- IDT_SW_NTP0_PCIELCTLSTS
- IDT_SW_NTP12_BARLIMIT0
- IDT_SW_NTP12_BARLIMIT1
- IDT_SW_NTP12_BARLIMIT2
- IDT_SW_NTP12_BARLIMIT3
- IDT_SW_NTP12_BARLIMIT4
- IDT_SW_NTP12_BARLIMIT5
- IDT_SW_NTP12_BARLTBASE0
- IDT_SW_NTP12_BARLTBASE1
- IDT_SW_NTP12_BARLTBASE2
- IDT_SW_NTP12_BARLTBASE3
- IDT_SW_NTP12_BARLTBASE4
- IDT_SW_NTP12_BARLTBASE5
- IDT_SW_NTP12_BARSETUP0
- IDT_SW_NTP12_BARSETUP1
- IDT_SW_NTP12_BARSETUP2
- IDT_SW_NTP12_BARSETUP3
- IDT_SW_NTP12_BARSETUP4
- IDT_SW_NTP12_BARSETUP5
- IDT_SW_NTP12_BARUTBASE0
- IDT_SW_NTP12_BARUTBASE1
- IDT_SW_NTP12_BARUTBASE2
- IDT_SW_NTP12_BARUTBASE3
- IDT_SW_NTP12_BARUTBASE4
- IDT_SW_NTP12_BARUTBASE5
- IDT_SW_NTP12_NTCTL
- IDT_SW_NTP12_PCIECMDSTS
- IDT_SW_NTP12_PCIELCTLSTS
- IDT_SW_NTP16_BARLIMIT0
- IDT_SW_NTP16_BARLIMIT1
- IDT_SW_NTP16_BARLIMIT2
- IDT_SW_NTP16_BARLIMIT3
- IDT_SW_NTP16_BARLIMIT4
- IDT_SW_NTP16_BARLIMIT5
- IDT_SW_NTP16_BARLTBASE0
- IDT_SW_NTP16_BARLTBASE1
- IDT_SW_NTP16_BARLTBASE2
- IDT_SW_NTP16_BARLTBASE3
- IDT_SW_NTP16_BARLTBASE4
- IDT_SW_NTP16_BARLTBASE5
- IDT_SW_NTP16_BARSETUP0
- IDT_SW_NTP16_BARSETUP1
- IDT_SW_NTP16_BARSETUP2
- IDT_SW_NTP16_BARSETUP3
- IDT_SW_NTP16_BARSETUP4
- IDT_SW_NTP16_BARSETUP5
- IDT_SW_NTP16_BARUTBASE0
- IDT_SW_NTP16_BARUTBASE1
- IDT_SW_NTP16_BARUTBASE2
- IDT_SW_NTP16_BARUTBASE3
- IDT_SW_NTP16_BARUTBASE4
- IDT_SW_NTP16_BARUTBASE5
- IDT_SW_NTP16_NTCTL
- IDT_SW_NTP16_PCIECMDSTS
- IDT_SW_NTP16_PCIELCTLSTS
- IDT_SW_NTP20_BARLIMIT0
- IDT_SW_NTP20_BARLIMIT1
- IDT_SW_NTP20_BARLIMIT2
- IDT_SW_NTP20_BARLIMIT3
- IDT_SW_NTP20_BARLIMIT4
- IDT_SW_NTP20_BARLIMIT5
- IDT_SW_NTP20_BARLTBASE0
- IDT_SW_NTP20_BARLTBASE1
- IDT_SW_NTP20_BARLTBASE2
- IDT_SW_NTP20_BARLTBASE3
- IDT_SW_NTP20_BARLTBASE4
- IDT_SW_NTP20_BARLTBASE5
- IDT_SW_NTP20_BARSETUP0
- IDT_SW_NTP20_BARSETUP1
- IDT_SW_NTP20_BARSETUP2
- IDT_SW_NTP20_BARSETUP3
- IDT_SW_NTP20_BARSETUP4
- IDT_SW_NTP20_BARSETUP5
- IDT_SW_NTP20_BARUTBASE0
- IDT_SW_NTP20_BARUTBASE1
- IDT_SW_NTP20_BARUTBASE2
- IDT_SW_NTP20_BARUTBASE3
- IDT_SW_NTP20_BARUTBASE4
- IDT_SW_NTP20_BARUTBASE5
- IDT_SW_NTP20_NTCTL
- IDT_SW_NTP20_PCIECMDSTS
- IDT_SW_NTP20_PCIELCTLSTS
- IDT_SW_NTP2_BARLIMIT0
- IDT_SW_NTP2_BARLIMIT1
- IDT_SW_NTP2_BARLIMIT2
- IDT_SW_NTP2_BARLIMIT3
- IDT_SW_NTP2_BARLIMIT4
- IDT_SW_NTP2_BARLIMIT5
- IDT_SW_NTP2_BARLTBASE0
- IDT_SW_NTP2_BARLTBASE1
- IDT_SW_NTP2_BARLTBASE2
- IDT_SW_NTP2_BARLTBASE3
- IDT_SW_NTP2_BARLTBASE4
- IDT_SW_NTP2_BARLTBASE5
- IDT_SW_NTP2_BARSETUP0
- IDT_SW_NTP2_BARSETUP1
- IDT_SW_NTP2_BARSETUP2
- IDT_SW_NTP2_BARSETUP3
- IDT_SW_NTP2_BARSETUP4
- IDT_SW_NTP2_BARSETUP5
- IDT_SW_NTP2_BARUTBASE0
- IDT_SW_NTP2_BARUTBASE1
- IDT_SW_NTP2_BARUTBASE2
- IDT_SW_NTP2_BARUTBASE3
- IDT_SW_NTP2_BARUTBASE4
- IDT_SW_NTP2_BARUTBASE5
- IDT_SW_NTP2_NTCTL
- IDT_SW_NTP2_PCIECMDSTS
- IDT_SW_NTP2_PCIELCTLSTS
- IDT_SW_NTP4_BARLIMIT0
- IDT_SW_NTP4_BARLIMIT1
- IDT_SW_NTP4_BARLIMIT2
- IDT_SW_NTP4_BARLIMIT3
- IDT_SW_NTP4_BARLIMIT4
- IDT_SW_NTP4_BARLIMIT5
- IDT_SW_NTP4_BARLTBASE0
- IDT_SW_NTP4_BARLTBASE1
- IDT_SW_NTP4_BARLTBASE2
- IDT_SW_NTP4_BARLTBASE3
- IDT_SW_NTP4_BARLTBASE4
- IDT_SW_NTP4_BARLTBASE5
- IDT_SW_NTP4_BARSETUP0
- IDT_SW_NTP4_BARSETUP1
- IDT_SW_NTP4_BARSETUP2
- IDT_SW_NTP4_BARSETUP3
- IDT_SW_NTP4_BARSETUP4
- IDT_SW_NTP4_BARSETUP5
- IDT_SW_NTP4_BARUTBASE0
- IDT_SW_NTP4_BARUTBASE1
- IDT_SW_NTP4_BARUTBASE2
- IDT_SW_NTP4_BARUTBASE3
- IDT_SW_NTP4_BARUTBASE4
- IDT_SW_NTP4_BARUTBASE5
- IDT_SW_NTP4_NTCTL
- IDT_SW_NTP4_PCIECMDSTS
- IDT_SW_NTP4_PCIELCTLSTS
- IDT_SW_NTP6_BARLIMIT0
- IDT_SW_NTP6_BARLIMIT1
- IDT_SW_NTP6_BARLIMIT2
- IDT_SW_NTP6_BARLIMIT3
- IDT_SW_NTP6_BARLIMIT4
- IDT_SW_NTP6_BARLIMIT5
- IDT_SW_NTP6_BARLTBASE0
- IDT_SW_NTP6_BARLTBASE1
- IDT_SW_NTP6_BARLTBASE2
- IDT_SW_NTP6_BARLTBASE3
- IDT_SW_NTP6_BARLTBASE4
- IDT_SW_NTP6_BARLTBASE5
- IDT_SW_NTP6_BARSETUP0
- IDT_SW_NTP6_BARSETUP1
- IDT_SW_NTP6_BARSETUP2
- IDT_SW_NTP6_BARSETUP3
- IDT_SW_NTP6_BARSETUP4
- IDT_SW_NTP6_BARSETUP5
- IDT_SW_NTP6_BARUTBASE0
- IDT_SW_NTP6_BARUTBASE1
- IDT_SW_NTP6_BARUTBASE2
- IDT_SW_NTP6_BARUTBASE3
- IDT_SW_NTP6_BARUTBASE4
- IDT_SW_NTP6_BARUTBASE5
- IDT_SW_NTP6_NTCTL
- IDT_SW_NTP6_PCIECMDSTS
- IDT_SW_NTP6_PCIELCTLSTS
- IDT_SW_NTP8_BARLIMIT0
- IDT_SW_NTP8_BARLIMIT1
- IDT_SW_NTP8_BARLIMIT2
- IDT_SW_NTP8_BARLIMIT3
- IDT_SW_NTP8_BARLIMIT4
- IDT_SW_NTP8_BARLIMIT5
- IDT_SW_NTP8_BARLTBASE0
- IDT_SW_NTP8_BARLTBASE1
- IDT_SW_NTP8_BARLTBASE2
- IDT_SW_NTP8_BARLTBASE3
- IDT_SW_NTP8_BARLTBASE4
- IDT_SW_NTP8_BARLTBASE5
- IDT_SW_NTP8_BARSETUP0
- IDT_SW_NTP8_BARSETUP1
- IDT_SW_NTP8_BARSETUP2
- IDT_SW_NTP8_BARSETUP3
- IDT_SW_NTP8_BARSETUP4
- IDT_SW_NTP8_BARSETUP5
- IDT_SW_NTP8_BARUTBASE0
- IDT_SW_NTP8_BARUTBASE1
- IDT_SW_NTP8_BARUTBASE2
- IDT_SW_NTP8_BARUTBASE3
- IDT_SW_NTP8_BARUTBASE4
- IDT_SW_NTP8_BARUTBASE5
- IDT_SW_NTP8_NTCTL
- IDT_SW_NTP8_PCIECMDSTS
- IDT_SW_NTP8_PCIELCTLSTS
- IDT_SW_PCLKMODE
- IDT_SW_POMCDELAY
- IDT_SW_RDRAINDELAY
- IDT_SW_SEDELAY
- IDT_SW_SEFOVRMSK
- IDT_SW_SEFRSTMSK
- IDT_SW_SEFRSTSTS
- IDT_SW_SEGSIGMSK
- IDT_SW_SEGSIGSTS
- IDT_SW_SEHRSTMSK
- IDT_SW_SEHRSTSTS
- IDT_SW_SELINKDNMSK
- IDT_SW_SELINKDNSTS
- IDT_SW_SELINKUPMSK
- IDT_SW_SELINKUPSTS
- IDT_SW_SEMSK
- IDT_SW_SEPMSK
- IDT_SW_SESTS
- IDT_SW_SMBUSCBHL
- IDT_SW_SMBUSCTL
- IDT_SW_SMBUSSTS
- IDT_SW_SSBRDELAY
- IDT_SW_SWP0MSGCTL0
- IDT_SW_SWP0MSGCTL1
- IDT_SW_SWP0MSGCTL2
- IDT_SW_SWP0MSGCTL3
- IDT_SW_SWP1MSGCTL0
- IDT_SW_SWP1MSGCTL1
- IDT_SW_SWP1MSGCTL2
- IDT_SW_SWP1MSGCTL3
- IDT_SW_SWP2MSGCTL0
- IDT_SW_SWP2MSGCTL1
- IDT_SW_SWP2MSGCTL2
- IDT_SW_SWP2MSGCTL3
- IDT_SW_SWP3MSGCTL0
- IDT_SW_SWP3MSGCTL1
- IDT_SW_SWP3MSGCTL2
- IDT_SW_SWP3MSGCTL3
- IDT_SW_SWP4MSGCTL0
- IDT_SW_SWP4MSGCTL1
- IDT_SW_SWP4MSGCTL2
- IDT_SW_SWP4MSGCTL3
- IDT_SW_SWP5MSGCTL0
- IDT_SW_SWP5MSGCTL1
- IDT_SW_SWP5MSGCTL2
- IDT_SW_SWP5MSGCTL3
- IDT_SW_SWP6MSGCTL0
- IDT_SW_SWP6MSGCTL1
- IDT_SW_SWP6MSGCTL2
- IDT_SW_SWP6MSGCTL3
- IDT_SW_SWP7MSGCTL0
- IDT_SW_SWP7MSGCTL1
- IDT_SW_SWP7MSGCTL2
- IDT_SW_SWP7MSGCTL3
- IDT_SW_SWPART0CTL
- IDT_SW_SWPART0FCTL
- IDT_SW_SWPART0STS
- IDT_SW_SWPART1CTL
- IDT_SW_SWPART1FCTL
- IDT_SW_SWPART1STS
- IDT_SW_SWPART2CTL
- IDT_SW_SWPART2FCTL
- IDT_SW_SWPART2STS
- IDT_SW_SWPART3CTL
- IDT_SW_SWPART3FCTL
- IDT_SW_SWPART3STS
- IDT_SW_SWPART4CTL
- IDT_SW_SWPART4FCTL
- IDT_SW_SWPART4STS
- IDT_SW_SWPART5CTL
- IDT_SW_SWPART5FCTL
- IDT_SW_SWPART5STS
- IDT_SW_SWPART6CTL
- IDT_SW_SWPART6FCTL
- IDT_SW_SWPART6STS
- IDT_SW_SWPART7CTL
- IDT_SW_SWPART7FCTL
- IDT_SW_SWPART7STS
- IDT_SW_SWPORT0CTL
- IDT_SW_SWPORT0FCTL
- IDT_SW_SWPORT0STS
- IDT_SW_SWPORT12CTL
- IDT_SW_SWPORT12FCTL
- IDT_SW_SWPORT12STS
- IDT_SW_SWPORT16CTL
- IDT_SW_SWPORT16FCTL
- IDT_SW_SWPORT16STS
- IDT_SW_SWPORT20CTL
- IDT_SW_SWPORT20FCTL
- IDT_SW_SWPORT20STS
- IDT_SW_SWPORT2CTL
- IDT_SW_SWPORT2FCTL
- IDT_SW_SWPORT2STS
- IDT_SW_SWPORT4CTL
- IDT_SW_SWPORT4FCTL
- IDT_SW_SWPORT4STS
- IDT_SW_SWPORT6CTL
- IDT_SW_SWPORT6FCTL
- IDT_SW_SWPORT6STS
- IDT_SW_SWPORT8CTL
- IDT_SW_SWPORT8FCTL
- IDT_SW_SWPORT8STS
- IDT_SW_TMPADJ
- IDT_SW_TMPALARM
- IDT_SW_TMPCTL
- IDT_SW_TMPSTS
- IDT_SW_TSSLOPE
- IDT_TABLE_SIZE_BMSK
- IDT_TABLE_SIZE_SHFT
- IDT_TEMP_CUR
- IDT_TEMP_HIGH
- IDT_TEMP_LOW
- IDT_TEMP_MAX_MDEG
- IDT_TEMP_MAX_OFFSET
- IDT_TEMP_MIN_MDEG
- IDT_TEMP_MIN_OFFSET
- IDT_TEMP_OFFSET
- IDT_TMPADJ_OFFSET_FLD
- IDT_TMPADJ_OFFSET_MASK
- IDT_TMPALARM_HTEMP_FLD
- IDT_TMPALARM_HTEMP_MASK
- IDT_TMPALARM_IRQ_MASK
- IDT_TMPALARM_LTEMP_FLD
- IDT_TMPALARM_LTEMP_MASK
- IDT_TMPCTL_HTH_FLD
- IDT_TMPCTL_HTH_MASK
- IDT_TMPCTL_LTH_FLD
- IDT_TMPCTL_LTH_MASK
- IDT_TMPCTL_MTH_FLD
- IDT_TMPCTL_MTH_MASK
- IDT_TMPCTL_PDOWN
- IDT_TMPSTS_HTEMP_FLD
- IDT_TMPSTS_HTEMP_MASK
- IDT_TMPSTS_LTEMP_FLD
- IDT_TMPSTS_LTEMP_MASK
- IDT_TMPSTS_TEMP_FLD
- IDT_TMPSTS_TEMP_MASK
- IDT_TRANS_ALIGN
- IDT_VC5_5P49V5923
- IDT_VC5_5P49V5925
- IDT_VC5_5P49V5933
- IDT_VC5_5P49V5935
- IDT_VC6_5P49V6901
- IDT_VECTORING_ERROR_CODE
- IDT_VECTORING_INFO_FIELD
- IDT_VENDOR_ID
- IDT_VIDDID_CSR
- IDT_VID_MASK
- IDU_M_DISTRI_DEST
- IDU_M_DISTRI_RR
- IDU_M_TRIG_EDGE
- IDU_M_TRIG_LEVEL
- IDVAL3_CLASS_CODE_MASK
- IDVAL3_CLASS_SHIFT
- IDVAL3_SUBCLASS_SHIFT
- IDVENH
- IDVENL
- IDX
- IDX_0xC14
- IDX_0xC1C
- IDX_0xC4C
- IDX_0xC78
- IDX_0xC80
- IDX_0xC88
- IDX_0xC94
- IDX_0xC9C
- IDX_0xCA0
- IDX_ACTIVATE_SIZE
- IDX_ADC_CFG
- IDX_ALS_BLUE
- IDX_ALS_CLEAR
- IDX_ALS_GREEN
- IDX_ALS_RED
- IDX_BEEP_CFG
- IDX_BLUE
- IDX_CLEAR
- IDX_COUNT
- IDX_CSIS
- IDX_DAC_CFG
- IDX_DIR_DOWN
- IDX_DIR_LEFT
- IDX_DIR_RIGHT
- IDX_DIR_UP
- IDX_FAN1_INPUT
- IDX_FAN1_MAX
- IDX_FAN1_MIN
- IDX_FIMC
- IDX_FLITE
- IDX_GAME_AXES_CONFIG
- IDX_GAME_AXIS_VALUE
- IDX_GAME_HWCONFIG
- IDX_GAME_LEGACY_COMPATIBLE
- IDX_GREEN
- IDX_INVALID
- IDX_IO_66H
- IDX_IO_6AH
- IDX_IO_6CH
- IDX_IO_6EH
- IDX_IO_CODEC_DMA_CURROFS
- IDX_IO_CODEC_DMA_CURRPOS
- IDX_IO_CODEC_DMA_FLAGS
- IDX_IO_CODEC_DMA_LENGTHS
- IDX_IO_CODEC_DMA_START_1
- IDX_IO_CODEC_DMA_START_2
- IDX_IO_CODEC_IRQTYPE
- IDX_IO_CODEC_SOUNDFORMAT
- IDX_IO_IRQSTATUS
- IDX_IO_SOME_VALUE
- IDX_IO_TIMER_VALUE
- IDX_IPCP
- IDX_IPV6CP
- IDX_IRQ_S0_BVD1_STSCHG
- IDX_IRQ_S0_CD_VALID
- IDX_IRQ_S0_READY_NINT
- IDX_IRQ_S1_BVD1_STSCHG
- IDX_IRQ_S1_CD_VALID
- IDX_IRQ_S1_READY_NINT
- IDX_IS_ISP
- IDX_LCP
- IDX_MAX
- IDX_MIN
- IDX_MIXER_ADVCTL1
- IDX_MIXER_ADVCTL2
- IDX_MIXER_AUX
- IDX_MIXER_BASSTREBLE
- IDX_MIXER_CDAUDIO
- IDX_MIXER_FMSYNTH
- IDX_MIXER_LINEIN
- IDX_MIXER_MIC
- IDX_MIXER_MODEMIN
- IDX_MIXER_MODEMOUT
- IDX_MIXER_PCBEEP
- IDX_MIXER_PLAY_MASTER
- IDX_MIXER_REC_SELECT
- IDX_MIXER_REC_VOLUME
- IDX_MIXER_RESET
- IDX_MIXER_SOMETHING30H
- IDX_MIXER_VIDEO
- IDX_MIXER_WAVEOUT
- IDX_NS_W
- IDX_OFFSET
- IDX_PER_GROUP
- IDX_RED
- IDX_SENSOR
- IDX_SPDIF_CTL
- IDX_SPDIF_STAT
- IDX_STOP
- IDX_TEMP1_CRIT
- IDX_TEMP1_INPUT
- IDX_TEMP1_MAX
- IDX_TEMP1_MIN
- IDX_TEMP2_CRIT
- IDX_TEMP2_INPUT
- IDX_TEMP2_MAX
- IDX_TEMP2_MIN
- IDX_TO_SEQ
- IDX_TO_VOLT_INP_CMD
- IDX_TO_VOLT_MAX_CMD
- IDX_TO_VOLT_MIN_CMD
- ID_0_7
- ID_4DWAVE_DX
- ID_4DWAVE_NX
- ID_8_F
- ID_9005_GENERIC_IROC_MASK
- ID_9005_GENERIC_MASK
- ID_9005_SISL_ID
- ID_9005_SISL_MASK
- ID_AA64DFR0_BRPS_SHIFT
- ID_AA64DFR0_CTX_CMPS_SHIFT
- ID_AA64DFR0_DEBUGVER_SHIFT
- ID_AA64DFR0_PMSVER_SHIFT
- ID_AA64DFR0_PMUVER_SHIFT
- ID_AA64DFR0_TRACEVER_SHIFT
- ID_AA64DFR0_WRPS_SHIFT
- ID_AA64ISAR0_AES_SHIFT
- ID_AA64ISAR0_ATOMICS_SHIFT
- ID_AA64ISAR0_CRC32_SHIFT
- ID_AA64ISAR0_DP_SHIFT
- ID_AA64ISAR0_FHM_SHIFT
- ID_AA64ISAR0_RDM_SHIFT
- ID_AA64ISAR0_SHA1_SHIFT
- ID_AA64ISAR0_SHA2_SHIFT
- ID_AA64ISAR0_SHA3_SHIFT
- ID_AA64ISAR0_SM3_SHIFT
- ID_AA64ISAR0_SM4_SHIFT
- ID_AA64ISAR0_TS_SHIFT
- ID_AA64ISAR1_APA_ARCHITECTED
- ID_AA64ISAR1_APA_NI
- ID_AA64ISAR1_APA_SHIFT
- ID_AA64ISAR1_API_IMP_DEF
- ID_AA64ISAR1_API_NI
- ID_AA64ISAR1_API_SHIFT
- ID_AA64ISAR1_DPB_SHIFT
- ID_AA64ISAR1_FCMA_SHIFT
- ID_AA64ISAR1_FRINTTS_SHIFT
- ID_AA64ISAR1_GPA_ARCHITECTED
- ID_AA64ISAR1_GPA_NI
- ID_AA64ISAR1_GPA_SHIFT
- ID_AA64ISAR1_GPI_IMP_DEF
- ID_AA64ISAR1_GPI_NI
- ID_AA64ISAR1_GPI_SHIFT
- ID_AA64ISAR1_JSCVT_SHIFT
- ID_AA64ISAR1_LRCPC_SHIFT
- ID_AA64ISAR1_SB_SHIFT
- ID_AA64MMFR0_ASID_SHIFT
- ID_AA64MMFR0_BIGENDEL0_SHIFT
- ID_AA64MMFR0_BIGENDEL_SHIFT
- ID_AA64MMFR0_PARANGE_48
- ID_AA64MMFR0_PARANGE_52
- ID_AA64MMFR0_PARANGE_MAX
- ID_AA64MMFR0_PARANGE_SHIFT
- ID_AA64MMFR0_SNSMEM_SHIFT
- ID_AA64MMFR0_TGRAN16_NI
- ID_AA64MMFR0_TGRAN16_SHIFT
- ID_AA64MMFR0_TGRAN16_SUPPORTED
- ID_AA64MMFR0_TGRAN4_NI
- ID_AA64MMFR0_TGRAN4_SHIFT
- ID_AA64MMFR0_TGRAN4_SUPPORTED
- ID_AA64MMFR0_TGRAN64_NI
- ID_AA64MMFR0_TGRAN64_SHIFT
- ID_AA64MMFR0_TGRAN64_SUPPORTED
- ID_AA64MMFR0_TGRAN_SHIFT
- ID_AA64MMFR0_TGRAN_SUPPORTED
- ID_AA64MMFR1_HADBS_SHIFT
- ID_AA64MMFR1_HPD_SHIFT
- ID_AA64MMFR1_LOR_SHIFT
- ID_AA64MMFR1_PAN_SHIFT
- ID_AA64MMFR1_VHE_SHIFT
- ID_AA64MMFR1_VMIDBITS_16
- ID_AA64MMFR1_VMIDBITS_8
- ID_AA64MMFR1_VMIDBITS_SHIFT
- ID_AA64MMFR2_AT_SHIFT
- ID_AA64MMFR2_CNP_SHIFT
- ID_AA64MMFR2_FWB_SHIFT
- ID_AA64MMFR2_IESB_SHIFT
- ID_AA64MMFR2_LSM_SHIFT
- ID_AA64MMFR2_LVA_SHIFT
- ID_AA64MMFR2_UAO_SHIFT
- ID_AA64PFR0_ASIMD_NI
- ID_AA64PFR0_ASIMD_SHIFT
- ID_AA64PFR0_ASIMD_SUPPORTED
- ID_AA64PFR0_CSV2_SHIFT
- ID_AA64PFR0_CSV3_SHIFT
- ID_AA64PFR0_DIT_SHIFT
- ID_AA64PFR0_EL0_32BIT_64BIT
- ID_AA64PFR0_EL0_64BIT_ONLY
- ID_AA64PFR0_EL0_SHIFT
- ID_AA64PFR0_EL1_64BIT_ONLY
- ID_AA64PFR0_EL1_SHIFT
- ID_AA64PFR0_EL2_SHIFT
- ID_AA64PFR0_EL3_SHIFT
- ID_AA64PFR0_FP_NI
- ID_AA64PFR0_FP_SHIFT
- ID_AA64PFR0_FP_SUPPORTED
- ID_AA64PFR0_GIC_SHIFT
- ID_AA64PFR0_RAS_SHIFT
- ID_AA64PFR0_RAS_V1
- ID_AA64PFR0_SVE
- ID_AA64PFR0_SVE_SHIFT
- ID_AA64PFR1_SSBS_PSTATE_INSNS
- ID_AA64PFR1_SSBS_PSTATE_NI
- ID_AA64PFR1_SSBS_PSTATE_ONLY
- ID_AA64PFR1_SSBS_SHIFT
- ID_AA64ZFR0_AES
- ID_AA64ZFR0_AES_PMULL
- ID_AA64ZFR0_AES_SHIFT
- ID_AA64ZFR0_BITPERM
- ID_AA64ZFR0_BITPERM_SHIFT
- ID_AA64ZFR0_SHA3
- ID_AA64ZFR0_SHA3_SHIFT
- ID_AA64ZFR0_SM4
- ID_AA64ZFR0_SM4_SHIFT
- ID_AA64ZFR0_SVEVER_SHIFT
- ID_AA64ZFR0_SVEVER_SVE2
- ID_AAA_131U2
- ID_AD5024
- ID_AD5025
- ID_AD5044
- ID_AD5045
- ID_AD5064
- ID_AD5064_1
- ID_AD5065
- ID_AD5300
- ID_AD5310
- ID_AD5310R
- ID_AD5311R
- ID_AD5320
- ID_AD5360
- ID_AD5361
- ID_AD5362
- ID_AD5363
- ID_AD5370
- ID_AD5371
- ID_AD5372
- ID_AD5373
- ID_AD5380_3
- ID_AD5380_5
- ID_AD5381_3
- ID_AD5381_5
- ID_AD5382_3
- ID_AD5382_5
- ID_AD5383_3
- ID_AD5383_5
- ID_AD5390_3
- ID_AD5390_5
- ID_AD5391_3
- ID_AD5391_5
- ID_AD5392_3
- ID_AD5392_5
- ID_AD5426
- ID_AD5429
- ID_AD5432
- ID_AD5439
- ID_AD5443
- ID_AD5444
- ID_AD5446
- ID_AD5449
- ID_AD5450
- ID_AD5451
- ID_AD5501
- ID_AD5504
- ID_AD5512A
- ID_AD5541A
- ID_AD5553
- ID_AD5600
- ID_AD5601
- ID_AD5602
- ID_AD5611
- ID_AD5612
- ID_AD5620_1250
- ID_AD5620_2500
- ID_AD5621
- ID_AD5622
- ID_AD5624R3
- ID_AD5624R5
- ID_AD5625
- ID_AD5625R_1V25
- ID_AD5625R_2V5
- ID_AD5627
- ID_AD5627R_1V25
- ID_AD5627R_2V5
- ID_AD5628_1
- ID_AD5628_2
- ID_AD5629_1
- ID_AD5629_2
- ID_AD5640_1250
- ID_AD5640_2500
- ID_AD5641
- ID_AD5644R3
- ID_AD5644R5
- ID_AD5645R_1V25
- ID_AD5645R_2V5
- ID_AD5647R_1V25
- ID_AD5647R_2V5
- ID_AD5648_1
- ID_AD5648_2
- ID_AD5660_1250
- ID_AD5660_2500
- ID_AD5662
- ID_AD5664R3
- ID_AD5664R5
- ID_AD5665
- ID_AD5665R_1V25
- ID_AD5665R_2V5
- ID_AD5666_1
- ID_AD5666_2
- ID_AD5667
- ID_AD5667R_1V25
- ID_AD5667R_2V5
- ID_AD5668_1
- ID_AD5668_2
- ID_AD5669_1
- ID_AD5669_2
- ID_AD5671R
- ID_AD5672R
- ID_AD5674R
- ID_AD5675R
- ID_AD5676
- ID_AD5676R
- ID_AD5679R
- ID_AD5681R
- ID_AD5682R
- ID_AD5683
- ID_AD5683R
- ID_AD5684
- ID_AD5684R
- ID_AD5685R
- ID_AD5686
- ID_AD5686R
- ID_AD5691R
- ID_AD5692R
- ID_AD5693
- ID_AD5693R
- ID_AD5694
- ID_AD5694R
- ID_AD5695R
- ID_AD5696
- ID_AD5696R
- ID_AD5721
- ID_AD5721R
- ID_AD5735
- ID_AD5737
- ID_AD5744
- ID_AD5744R
- ID_AD5755
- ID_AD5757
- ID_AD5760
- ID_AD5761
- ID_AD5761R
- ID_AD5764
- ID_AD5764R
- ID_AD5780
- ID_AD5781
- ID_AD5791
- ID_AD7091R
- ID_AD7124_4
- ID_AD7124_8
- ID_AD7170
- ID_AD7171
- ID_AD7190
- ID_AD7192
- ID_AD7193
- ID_AD7195
- ID_AD7276
- ID_AD7277
- ID_AD7278
- ID_AD7466
- ID_AD7467
- ID_AD7468
- ID_AD7495
- ID_AD7605_4
- ID_AD7606B
- ID_AD7606_4
- ID_AD7606_6
- ID_AD7606_8
- ID_AD7616
- ID_AD7682
- ID_AD7689
- ID_AD7766
- ID_AD7766_1
- ID_AD7766_2
- ID_AD7780
- ID_AD7781
- ID_AD7785
- ID_AD7792
- ID_AD7793
- ID_AD7794
- ID_AD7795
- ID_AD7796
- ID_AD7797
- ID_AD7798
- ID_AD7799
- ID_AD7816
- ID_AD7817
- ID_AD7818
- ID_AD7887
- ID_AD7940
- ID_AD7949
- ID_AD8366
- ID_AD8801
- ID_AD8803
- ID_AD9833
- ID_AD9834
- ID_AD9837
- ID_AD9838
- ID_ADA4961
- ID_ADC081S
- ID_ADC101S
- ID_ADC121S
- ID_ADD
- ID_ADDRESS
- ID_ADIS16080
- ID_ADIS16100
- ID_ADIS16133
- ID_ADIS16135
- ID_ADIS16136
- ID_ADIS16137
- ID_ADL5240
- ID_ADP5501
- ID_ADP5520
- ID_ADP8860
- ID_ADP8870
- ID_ADS7866
- ID_ADS7867
- ID_ADS7868
- ID_ADS8684
- ID_ADS8688
- ID_ADT7316
- ID_ADT7317
- ID_ADT7318
- ID_ADT73XX
- ID_ADT7516
- ID_ADT7517
- ID_ADT7519
- ID_ADT75XX
- ID_ADXL345
- ID_ADXL346
- ID_ADXRS450
- ID_ADXRS453
- ID_AHA_1480A
- ID_AHA_19160B
- ID_AHA_274x
- ID_AHA_284x
- ID_AHA_284xB
- ID_AHA_2902_04_10_15_20C_30C
- ID_AHA_2915_30LP
- ID_AHA_29160
- ID_AHA_29160B
- ID_AHA_29160C
- ID_AHA_29160N
- ID_AHA_29160_CPQ
- ID_AHA_2930CU
- ID_AHA_2930C_VAR
- ID_AHA_2930U
- ID_AHA_2930U2
- ID_AHA_29320
- ID_AHA_29320A
- ID_AHA_29320ALP
- ID_AHA_29320B
- ID_AHA_29320LP
- ID_AHA_29320LPE
- ID_AHA_2940
- ID_AHA_2940AU_0
- ID_AHA_2940AU_1
- ID_AHA_2940AU_CN
- ID_AHA_2940U
- ID_AHA_2940U2
- ID_AHA_2940U2B
- ID_AHA_2940U2_OEM
- ID_AHA_2940UB
- ID_AHA_2940U_CN
- ID_AHA_2940U_DUAL
- ID_AHA_2940U_PRO
- ID_AHA_2944
- ID_AHA_2944U
- ID_AHA_2950U2B
- ID_AHA_39320
- ID_AHA_39320A
- ID_AHA_39320D
- ID_AHA_39320D_B
- ID_AHA_39320D_B_HP
- ID_AHA_39320D_HP
- ID_AHA_39320_B
- ID_AHA_39320_B_DELL
- ID_AHA_3940
- ID_AHA_3940AU
- ID_AHA_3940U
- ID_AHA_3944
- ID_AHA_3944AU
- ID_AHA_3944U
- ID_AHA_3950U2B_0
- ID_AHA_3950U2B_1
- ID_AHA_3950U2D_0
- ID_AHA_3950U2D_1
- ID_AHA_3960D
- ID_AHA_3960D_CPQ
- ID_AHA_398X
- ID_AHA_398XU
- ID_AHA_4944
- ID_AHA_4944U
- ID_AIC7770
- ID_AIC7810
- ID_AIC7815
- ID_AIC7850
- ID_AIC7855
- ID_AIC7859
- ID_AIC7860
- ID_AIC7860C
- ID_AIC7870
- ID_AIC7880
- ID_AIC7880_B
- ID_AIC7890
- ID_AIC7890_ARO
- ID_AIC7892
- ID_AIC7892_ARO
- ID_AIC7895
- ID_AIC7895_ARO
- ID_AIC7895_ARO_MASK
- ID_AIC7896
- ID_AIC7896_ARO
- ID_AIC7899
- ID_AIC7899_ARO
- ID_AIC7901
- ID_AIC7901A
- ID_AIC7902
- ID_AIC7902_B
- ID_AIC7902_PCI_REV_A4
- ID_AIC7902_PCI_REV_B0
- ID_ALL_IROC_MASK
- ID_ALL_MASK
- ID_ARBLOST
- ID_ASSIGNED
- ID_BESS
- ID_BITS
- ID_BIT_AUDIO
- ID_BUS
- ID_BYTE0
- ID_C
- ID_CE6230
- ID_CE6231
- ID_CHERRY
- ID_CHK_REQ
- ID_CHK_RES
- ID_CH_MASK
- ID_CLOCK
- ID_CS
- ID_CYBERPRO_2000
- ID_CYBERPRO_2010
- ID_CYBERPRO_5000
- ID_DAC5311
- ID_DAC6311
- ID_DAC7311
- ID_DEBOUNCE
- ID_DENIED
- ID_DEV_VENDOR_MASK
- ID_DIN
- ID_DM9601
- ID_DM9620
- ID_DOFFSET
- ID_DONE
- ID_DOUT
- ID_DS4422
- ID_DS4424
- ID_ECP3_17
- ID_ECP3_35
- ID_FAMILY_MASK
- ID_FIRST_MSG
- ID_FLG
- ID_GRE
- ID_HIDDEN
- ID_HWDEVICE
- ID_HWGENERAL
- ID_HWHOST
- ID_HWRXBUF
- ID_HWTXBUF
- ID_ID
- ID_IDMOUSE
- ID_IGA_1682
- ID_IN_SYNC
- ID_IRQ_EN
- ID_IRQ_FLG
- ID_ISAR5_AES_SHIFT
- ID_ISAR5_CRC32_SHIFT
- ID_ISAR5_RDM_SHIFT
- ID_ISAR5_SEVL_SHIFT
- ID_ISAR5_SHA1_SHIFT
- ID_ISAR5_SHA2_SHIFT
- ID_IS_CAPTURE
- ID_JZ4725B
- ID_JZ4740
- ID_JZ4760
- ID_JZ4760B
- ID_JZ4770
- ID_JZ4780
- ID_L2TPV3
- ID_LAST_MSG
- ID_LED_DEF1_DEF2
- ID_LED_DEF1_OFF2
- ID_LED_DEF1_ON2
- ID_LED_DEFAULT
- ID_LED_DEFAULT_82573
- ID_LED_DEFAULT_82575_SERDES
- ID_LED_DEFAULT_I210
- ID_LED_DEFAULT_I210_SERDES
- ID_LED_DEFAULT_ICH8LAN
- ID_LED_OFF1_DEF2
- ID_LED_OFF1_OFF2
- ID_LED_OFF1_ON2
- ID_LED_ON1_DEF2
- ID_LED_ON1_OFF2
- ID_LED_ON1_ON2
- ID_LED_RESERVED_0000
- ID_LED_RESERVED_F746
- ID_LED_RESERVED_FFFF
- ID_LEN
- ID_LTC1660
- ID_LTC1665
- ID_LTC2606
- ID_LTC2607
- ID_LTC2609
- ID_LTC2616
- ID_LTC2617
- ID_LTC2619
- ID_LTC2626
- ID_LTC2627
- ID_LTC2629
- ID_LTC2631_H10
- ID_LTC2631_H12
- ID_LTC2631_H8
- ID_LTC2631_L10
- ID_LTC2631_L12
- ID_LTC2631_L8
- ID_LTC2632H10
- ID_LTC2632H12
- ID_LTC2632H8
- ID_LTC2632L10
- ID_LTC2632L12
- ID_LTC2632L8
- ID_LTC2633_H10
- ID_LTC2633_H12
- ID_LTC2633_H8
- ID_LTC2633_L10
- ID_LTC2633_L12
- ID_LTC2633_L8
- ID_LTC2635_H10
- ID_LTC2635_H12
- ID_LTC2635_H8
- ID_LTC2635_L10
- ID_LTC2635_L12
- ID_LTC2635_L8
- ID_MANUFACTURER_NAME
- ID_MANUFACTURER_NAME_END
- ID_MAP_SIZE
- ID_MASK
- ID_MATCHED
- ID_MAX
- ID_MAX517
- ID_MAX518
- ID_MAX519
- ID_MAX520
- ID_MAX521
- ID_MAX5821
- ID_MCP4902
- ID_MCP4912
- ID_MCP4922
- ID_MI1320
- ID_MI2020
- ID_MICROSOFT
- ID_MODEL
- ID_MODE_DIS
- ID_MSG_STRT
- ID_MT312
- ID_MT352
- ID_MT7530
- ID_MT7621
- ID_NACK
- ID_OFFSET
- ID_OLV_274x
- ID_OLV_274xD
- ID_OUT_OF_SYNC
- ID_OV2640
- ID_OV9655
- ID_OVERRIDE
- ID_OVERRIDE_FLOATING
- ID_OVERRIDE_GROUNDED
- ID_PORT_DIR
- ID_PORT_TYPE
- ID_PRODUCT
- ID_P_MASK
- ID_P_NO_RXDMA
- ID_P_PM_BLOCKED
- ID_P_REP_AFTER_RD
- ID_REG
- ID_REMOVE
- ID_REQUEST
- ID_RES_102K
- ID_RES_200K
- ID_RES_440K
- ID_RES_FLOAT
- ID_RES_GND
- ID_REV
- ID_REV_CHIP_ID_
- ID_REV_CHIP_ID_7800_
- ID_REV_CHIP_ID_7801_
- ID_REV_CHIP_ID_7850_
- ID_REV_CHIP_ID_89530_
- ID_REV_CHIP_ID_9500A_
- ID_REV_CHIP_ID_9500_
- ID_REV_CHIP_ID_9512_
- ID_REV_CHIP_ID_9530_
- ID_REV_CHIP_ID_9730_
- ID_REV_CHIP_ID_MASK_
- ID_REV_CHIP_REV_A0_
- ID_REV_CHIP_REV_B0_
- ID_REV_CHIP_REV_MASK_
- ID_REV_ID_LAN7430_
- ID_REV_ID_LAN7431_
- ID_REV_ID_MASK_
- ID_REV_IS_VALID_CHIP_ID_
- ID_REV_REV_ID_
- ID_SANITISED
- ID_SBUSCFG
- ID_SEL_BEGIN
- ID_SERIAL_NUMBER
- ID_SHIFT
- ID_SIEMENS
- ID_STATUS
- ID_STREAM_DISABLE_ACKED
- ID_STREAM_DISABLE_NO_ACK
- ID_STRING_LENGTH
- ID_STR_LENGTH
- ID_SUR40
- ID_SYNCER
- ID_TO_HPI_ENABLE
- ID_TO_TIMER
- ID_UNALLOCATED
- ID_UNASSIGNED
- ID_UNKNOWN
- ID_UNLOCK
- ID_UNUSED
- ID_VENDOR
- ID_VERIFY
- ID_VERSION
- ID_VOODOO1
- ID_VOODOO2
- ID_VP310
- ID_WREN
- ID_X1000
- ID_X1000E
- ID_X1500
- ID_ZL10039
- ID_ZL10313
- ID_ZL10353
- ID_boot
- ID_kernel
- ID_null
- IE
- IE0
- IE0_CDCD
- IE0_RXINTA
- IE0_RXINTB
- IE0_RXRDY
- IE0_TXINT
- IE0_TXRDY
- IE0_UDRN
- IE1
- IE1_ABTD
- IE1_CCTS
- IE1_CDCD
- IE1_CLMD
- IE1_IDL
- IE1_IDLD
- IE1_SYNCD
- IE1_UDRN
- IE2
- IE2_ABT
- IE2_CRCE
- IE2_EOM
- IE2_OVRN
- IE2_RBIT
- IE2_SHRT
- IE31200
- IE31200_C0ECCERRLOG
- IE31200_C0ECCERRLOG_SKL
- IE31200_C1ECCERRLOG
- IE31200_C1ECCERRLOG_SKL
- IE31200_CAPID0
- IE31200_CAPID0_DDPCD
- IE31200_CAPID0_ECC
- IE31200_CAPID0_PDCD
- IE31200_CHANNELS
- IE31200_DIMMS
- IE31200_DIMMS_PER_CHANNEL
- IE31200_ECCERRLOG_CE
- IE31200_ECCERRLOG_RANK_BITS
- IE31200_ECCERRLOG_RANK_SHIFT
- IE31200_ECCERRLOG_SYNDROME
- IE31200_ECCERRLOG_SYNDROME_BITS
- IE31200_ECCERRLOG_SYNDROME_SHIFT
- IE31200_ECCERRLOG_UE
- IE31200_ERRSTS
- IE31200_ERRSTS_BITS
- IE31200_ERRSTS_CE
- IE31200_ERRSTS_UE
- IE31200_MAD_DIMM_0_OFFSET
- IE31200_MAD_DIMM_0_OFFSET_SKL
- IE31200_MAD_DIMM_A_RANK
- IE31200_MAD_DIMM_A_RANK_SHIFT
- IE31200_MAD_DIMM_A_RANK_SKL
- IE31200_MAD_DIMM_A_RANK_SKL_SHIFT
- IE31200_MAD_DIMM_A_WIDTH
- IE31200_MAD_DIMM_A_WIDTH_SHIFT
- IE31200_MAD_DIMM_A_WIDTH_SKL
- IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT
- IE31200_MAD_DIMM_SIZE
- IE31200_MCHBAR_HIGH
- IE31200_MCHBAR_LOW
- IE31200_MCHBAR_MASK
- IE31200_MMR_WINDOW_SIZE
- IE31200_PAGES
- IE31200_RANKS
- IE31200_RANKS_PER_CHANNEL
- IE4
- IE4_CFT
- IE4_CGPI
- IE4_OCLM
- IE4_RDCR
- IE4_RDNR
- IE4_TDCR
- IE4_TDNR
- IEBC
- IEBI
- IEBUS
- IEC61937_FRM_PAU_AAC
- IEC61937_FRM_PAU_AC3
- IEC61937_FRM_PAU_DTS1
- IEC61937_FRM_PAU_DTS2
- IEC61937_FRM_PAU_DTS3
- IEC61937_FRM_PAU_MP3
- IEC61937_FRM_PAU_MPA
- IEC61937_FRM_STR_AAC
- IEC61937_FRM_STR_AC3
- IEC61937_FRM_STR_DTS1
- IEC61937_FRM_STR_DTS2
- IEC61937_FRM_STR_DTS3
- IEC61937_FRM_STR_MP3
- IEC61937_FRM_STR_MPA
- IEC61937_HEADER_SIGN
- IEC61937_PC
- IEC61937_PC_AAC
- IEC61937_PC_AC3
- IEC61937_PC_DTS1
- IEC61937_PC_DTS2
- IEC61937_PC_DTS3
- IEC61937_PC_MP3
- IEC61937_PC_MPA
- IEC61937_PC_PAUSE
- IEC958
- IEC958_AES0_CON_EMPHASIS
- IEC958_AES0_CON_EMPHASIS_5015
- IEC958_AES0_CON_EMPHASIS_NONE
- IEC958_AES0_CON_MODE
- IEC958_AES0_CON_NOT_COPYRIGHT
- IEC958_AES0_NONAUDIO
- IEC958_AES0_PROFESSIONAL
- IEC958_AES0_PRO_EMPHASIS
- IEC958_AES0_PRO_EMPHASIS_5015
- IEC958_AES0_PRO_EMPHASIS_CCITT
- IEC958_AES0_PRO_EMPHASIS_NONE
- IEC958_AES0_PRO_EMPHASIS_NOTID
- IEC958_AES0_PRO_FREQ_UNLOCKED
- IEC958_AES0_PRO_FS
- IEC958_AES0_PRO_FS_32000
- IEC958_AES0_PRO_FS_44100
- IEC958_AES0_PRO_FS_48000
- IEC958_AES0_PRO_FS_NOTID
- IEC958_AES1_CON_ADC
- IEC958_AES1_CON_ADC_COPYRIGHT
- IEC958_AES1_CON_ADC_COPYRIGHT_ID
- IEC958_AES1_CON_ADC_COPYRIGHT_MASK
- IEC958_AES1_CON_ADC_COPYRIGHT_OTHER
- IEC958_AES1_CON_ADC_ID
- IEC958_AES1_CON_ADC_MASK
- IEC958_AES1_CON_ADC_OTHER
- IEC958_AES1_CON_BROADCAST1_ID
- IEC958_AES1_CON_BROADCAST1_MASK
- IEC958_AES1_CON_BROADCAST1_OTHER
- IEC958_AES1_CON_BROADCAST2_ID
- IEC958_AES1_CON_BROADCAST2_MASK
- IEC958_AES1_CON_CATEGORY
- IEC958_AES1_CON_DAB_EUROPE
- IEC958_AES1_CON_DAB_JAPAN
- IEC958_AES1_CON_DAB_USA
- IEC958_AES1_CON_DAT
- IEC958_AES1_CON_DCC
- IEC958_AES1_CON_DIGDIGCONV_ID
- IEC958_AES1_CON_DIGDIGCONV_MASK
- IEC958_AES1_CON_DIGDIGCONV_OTHER
- IEC958_AES1_CON_DSP
- IEC958_AES1_CON_DVD
- IEC958_AES1_CON_EXPERIMENTAL
- IEC958_AES1_CON_GENERAL
- IEC958_AES1_CON_IEC62105
- IEC958_AES1_CON_IEC908_CD
- IEC958_AES1_CON_LASEROPT_ID
- IEC958_AES1_CON_LASEROPT_MASK
- IEC958_AES1_CON_LASTEROPT_OTHER
- IEC958_AES1_CON_MAGNETIC_DISC
- IEC958_AES1_CON_MAGNETIC_ID
- IEC958_AES1_CON_MAGNETIC_MASK
- IEC958_AES1_CON_MAGNETIC_OTHER
- IEC958_AES1_CON_MICROPHONE
- IEC958_AES1_CON_MINI_DISC
- IEC958_AES1_CON_MIXER
- IEC958_AES1_CON_MUSICAL_ID
- IEC958_AES1_CON_MUSICAL_MASK
- IEC958_AES1_CON_MUSICAL_OTHER
- IEC958_AES1_CON_NON_IEC908_CD
- IEC958_AES1_CON_ORIGINAL
- IEC958_AES1_CON_PCM_CODER
- IEC958_AES1_CON_RATE_CONVERTER
- IEC958_AES1_CON_SAMPLER
- IEC958_AES1_CON_SOFTWARE
- IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER
- IEC958_AES1_CON_SOLIDMEM_ID
- IEC958_AES1_CON_SOLIDMEM_MASK
- IEC958_AES1_CON_SOLIDMEM_OTHER
- IEC958_AES1_CON_SYNTHESIZER
- IEC958_AES1_CON_VCR
- IEC958_AES1_PRO_MODE
- IEC958_AES1_PRO_MODE_BYTE3
- IEC958_AES1_PRO_MODE_NOTID
- IEC958_AES1_PRO_MODE_PRIMARY
- IEC958_AES1_PRO_MODE_SINGLE
- IEC958_AES1_PRO_MODE_STEREOPHONIC
- IEC958_AES1_PRO_MODE_TWO
- IEC958_AES1_PRO_USERBITS
- IEC958_AES1_PRO_USERBITS_192
- IEC958_AES1_PRO_USERBITS_NOTID
- IEC958_AES1_PRO_USERBITS_UDEF
- IEC958_AES2_CON_CHANNEL
- IEC958_AES2_CON_CHANNEL_UNSPEC
- IEC958_AES2_CON_SOURCE
- IEC958_AES2_CON_SOURCE_UNSPEC
- IEC958_AES2_PRO_SBITS
- IEC958_AES2_PRO_SBITS_20
- IEC958_AES2_PRO_SBITS_24
- IEC958_AES2_PRO_SBITS_UDEF
- IEC958_AES2_PRO_WORDLEN
- IEC958_AES2_PRO_WORDLEN_20_16
- IEC958_AES2_PRO_WORDLEN_22_18
- IEC958_AES2_PRO_WORDLEN_23_19
- IEC958_AES2_PRO_WORDLEN_24_20
- IEC958_AES2_PRO_WORDLEN_NOTID
- IEC958_AES3_CON_CLOCK
- IEC958_AES3_CON_CLOCK_1000PPM
- IEC958_AES3_CON_CLOCK_50PPM
- IEC958_AES3_CON_CLOCK_VARIABLE
- IEC958_AES3_CON_FS
- IEC958_AES3_CON_FS_176400
- IEC958_AES3_CON_FS_192000
- IEC958_AES3_CON_FS_22050
- IEC958_AES3_CON_FS_24000
- IEC958_AES3_CON_FS_32000
- IEC958_AES3_CON_FS_44100
- IEC958_AES3_CON_FS_48000
- IEC958_AES3_CON_FS_768000
- IEC958_AES3_CON_FS_88200
- IEC958_AES3_CON_FS_96000
- IEC958_AES3_CON_FS_NOTID
- IEC958_AES4_CON_MAX_WORDLEN_24
- IEC958_AES4_CON_ORIGFS
- IEC958_AES4_CON_ORIGFS_11025
- IEC958_AES4_CON_ORIGFS_12000
- IEC958_AES4_CON_ORIGFS_16000
- IEC958_AES4_CON_ORIGFS_176400
- IEC958_AES4_CON_ORIGFS_192000
- IEC958_AES4_CON_ORIGFS_22050
- IEC958_AES4_CON_ORIGFS_24000
- IEC958_AES4_CON_ORIGFS_32000
- IEC958_AES4_CON_ORIGFS_44100
- IEC958_AES4_CON_ORIGFS_48000
- IEC958_AES4_CON_ORIGFS_8000
- IEC958_AES4_CON_ORIGFS_88200
- IEC958_AES4_CON_ORIGFS_96000
- IEC958_AES4_CON_ORIGFS_NOTID
- IEC958_AES4_CON_WORDLEN
- IEC958_AES4_CON_WORDLEN_20_16
- IEC958_AES4_CON_WORDLEN_21_17
- IEC958_AES4_CON_WORDLEN_22_18
- IEC958_AES4_CON_WORDLEN_23_19
- IEC958_AES4_CON_WORDLEN_24_20
- IEC958_AES4_CON_WORDLEN_NOTID
- IEC958_AES5_CON_CGMSA
- IEC958_AES5_CON_CGMSA_COPYFREELY
- IEC958_AES5_CON_CGMSA_COPYNEVER
- IEC958_AES5_CON_CGMSA_COPYNOMORE
- IEC958_AES5_CON_CGMSA_COPYONCE
- IEC958_DEFAULT_CON
- IECLK_A_MARK
- IECLK_B_MARK
- IECLK_C_MARK
- IECLK_MARK
- IECLR_BTE0
- IECLR_BTE1
- IECLR_CRAZY
- IECLR_PRB_0
- IECLR_PRB_8
- IECLR_PRB_9
- IECLR_PRB_A
- IECLR_PRB_B
- IECLR_PRB_C
- IECLR_PRB_D
- IECLR_PRB_E
- IECLR_PRB_F
- IECSR_CLEAR
- IEEE1284_ADDR
- IEEE1284_DATA
- IEEE1284_DEVICEID
- IEEE1284_EXT_LINK
- IEEE1284_MODE_BECP
- IEEE1284_MODE_BYTE
- IEEE1284_MODE_COMPAT
- IEEE1284_MODE_ECP
- IEEE1284_MODE_ECPRLE
- IEEE1284_MODE_ECPSWE
- IEEE1284_MODE_EPP
- IEEE1284_MODE_EPPSL
- IEEE1284_MODE_EPPSWE
- IEEE1284_MODE_NIBBLE
- IEEE1284_PH_ECP_DIR_UNKNOWN
- IEEE1284_PH_ECP_FWD_TO_REV
- IEEE1284_PH_ECP_REV_TO_FWD
- IEEE1284_PH_ECP_SETUP
- IEEE1284_PH_FWD_DATA
- IEEE1284_PH_FWD_IDLE
- IEEE1284_PH_HBUSY_DAVAIL
- IEEE1284_PH_HBUSY_DNA
- IEEE1284_PH_NEGOTIATION
- IEEE1284_PH_REV_DATA
- IEEE1284_PH_REV_IDLE
- IEEE1284_PH_TERMINATE
- IEEE1394_ALL_NODES
- IEEE1394_BROADCAST_CHANNEL
- IEEE1394_GASP_HDR_SIZE
- IEEE1394_MATCH_MODEL_ID
- IEEE1394_MATCH_SPECIFIER_ID
- IEEE1394_MATCH_VENDOR_ID
- IEEE1394_MATCH_VERSION
- IEEE1394_MAX_PAYLOAD_S100
- IEEE1588_IRQ
- IEEE754_CEQ
- IEEE754_CGT
- IEEE754_CLASS_DNORM
- IEEE754_CLASS_INF
- IEEE754_CLASS_NORM
- IEEE754_CLASS_QNAN
- IEEE754_CLASS_SNAN
- IEEE754_CLASS_ZERO
- IEEE754_CLT
- IEEE754_CUN
- IEEE754_INEXACT
- IEEE754_INVALID_OPERATION
- IEEE754_OVERFLOW
- IEEE754_RT_DI
- IEEE754_RT_DP
- IEEE754_RT_SI
- IEEE754_RT_SP
- IEEE754_RT_XP
- IEEE754_SPCVAL_INDEF_2008
- IEEE754_SPCVAL_INDEF_LEG
- IEEE754_SPCVAL_NINFINITY
- IEEE754_SPCVAL_NMAX
- IEEE754_SPCVAL_NMIN
- IEEE754_SPCVAL_NMIND
- IEEE754_SPCVAL_NONE
- IEEE754_SPCVAL_NTEN
- IEEE754_SPCVAL_NZERO
- IEEE754_SPCVAL_P1E31
- IEEE754_SPCVAL_P1E63
- IEEE754_SPCVAL_PINFINITY
- IEEE754_SPCVAL_PMAX
- IEEE754_SPCVAL_PMIN
- IEEE754_SPCVAL_PMIND
- IEEE754_SPCVAL_PONE
- IEEE754_SPCVAL_PTEN
- IEEE754_SPCVAL_PZERO
- IEEE754_UNDERFLOW
- IEEE754_ZERO_DIVIDE
- IEEE80211A
- IEEE80211G
- IEEE80211S_H
- IEEE80211_1ADDR_LEN
- IEEE80211_24GHZ_BAND
- IEEE80211_24GHZ_CHANNELS
- IEEE80211_24GHZ_MAX_CHANNEL
- IEEE80211_24GHZ_MIN_CHANNEL
- IEEE80211_2ADDR_LEN
- IEEE80211_3ADDR_LEN
- IEEE80211_4ADDR_LEN
- IEEE80211_52GHZ_BAND
- IEEE80211_52GHZ_CHANNELS
- IEEE80211_52GHZ_MAX_CHANNEL
- IEEE80211_52GHZ_MIN_CHANNEL
- IEEE80211_AC_BE
- IEEE80211_AC_BK
- IEEE80211_AC_VI
- IEEE80211_AC_VO
- IEEE80211_ADDBA_EXT_FRAG_LEVEL_MASK
- IEEE80211_ADDBA_EXT_FRAG_LEVEL_SHIFT
- IEEE80211_ADDBA_EXT_NO_FRAG
- IEEE80211_ADDBA_PARAM_AMSDU_MASK
- IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
- IEEE80211_ADDBA_PARAM_POLICY_MASK
- IEEE80211_ADDBA_PARAM_TID_MASK
- IEEE80211_ADDR_LEN
- IEEE80211_AMPDU_RX_START
- IEEE80211_AMPDU_RX_STOP
- IEEE80211_AMPDU_TX_OPERATIONAL
- IEEE80211_AMPDU_TX_START
- IEEE80211_AMPDU_TX_STOP_CONT
- IEEE80211_AMPDU_TX_STOP_FLUSH
- IEEE80211_AMPDU_TX_STOP_FLUSH_CONT
- IEEE80211_ASSOCIATING
- IEEE80211_ASSOCIATING_AUTHENTICATED
- IEEE80211_ASSOCIATING_AUTHENTICATING
- IEEE80211_ASSOCIATING_RETRY
- IEEE80211_ASSOC_MAX_TRIES
- IEEE80211_ASSOC_TIMEOUT
- IEEE80211_ASSOC_TIMEOUT_LONG
- IEEE80211_ASSOC_TIMEOUT_SHORT
- IEEE80211_ATF_OVERHEAD
- IEEE80211_ATF_OVERHEAD_IFS
- IEEE80211_AUTH_MAX_TRIES
- IEEE80211_AUTH_TIMEOUT
- IEEE80211_AUTH_TIMEOUT_LONG
- IEEE80211_AUTH_TIMEOUT_SAE
- IEEE80211_AUTH_TIMEOUT_SHORT
- IEEE80211_AUTH_WAIT_ASSOC
- IEEE80211_BANDID_2G
- IEEE80211_BANDID_3G
- IEEE80211_BANDID_5G
- IEEE80211_BANDID_60G
- IEEE80211_BANDID_SUB1
- IEEE80211_BANDID_TV_WS
- IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL
- IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA
- IEEE80211_BAR_CTRL_MULTI_TID
- IEEE80211_BAR_CTRL_TID_INFO_MASK
- IEEE80211_BAR_CTRL_TID_INFO_SHIFT
- IEEE80211_BASIC_MAP_BSS
- IEEE80211_BASIC_MAP_OFDM
- IEEE80211_BASIC_MAP_RADAR
- IEEE80211_BASIC_MAP_UNIDENTIFIED
- IEEE80211_BASIC_MAP_UNMEASURED
- IEEE80211_BASIC_RATE_MASK
- IEEE80211_BSS_ARP_ADDR_LIST_LEN
- IEEE80211_BSS_CORRUPT_BEACON
- IEEE80211_BSS_CORRUPT_PROBE_RESP
- IEEE80211_BSS_TYPE_ANY
- IEEE80211_BSS_TYPE_ESS
- IEEE80211_BSS_TYPE_IBSS
- IEEE80211_BSS_TYPE_MBSS
- IEEE80211_BSS_TYPE_PBSS
- IEEE80211_BSS_VALID_ERP
- IEEE80211_BSS_VALID_RATES
- IEEE80211_BSS_VALID_WMM
- IEEE80211_CCK_BASIC_RATES_MASK
- IEEE80211_CCK_DEFAULT_RATES_MASK
- IEEE80211_CCK_MODULATION
- IEEE80211_CCK_RATES_MASK
- IEEE80211_CCK_RATE_11MB
- IEEE80211_CCK_RATE_11MB_MASK
- IEEE80211_CCK_RATE_1MB
- IEEE80211_CCK_RATE_1MB_MASK
- IEEE80211_CCK_RATE_2MB
- IEEE80211_CCK_RATE_2MB_MASK
- IEEE80211_CCK_RATE_5MB
- IEEE80211_CCK_RATE_5MB_MASK
- IEEE80211_CCK_RATE_LEN
- IEEE80211_CCMP_256_HDR_LEN
- IEEE80211_CCMP_256_MIC_LEN
- IEEE80211_CCMP_256_PN_LEN
- IEEE80211_CCMP_HDR_LEN
- IEEE80211_CCMP_MIC_LEN
- IEEE80211_CCMP_PN_LEN
- IEEE80211_CHANCTX_CHANGE_CHANNEL
- IEEE80211_CHANCTX_CHANGE_MIN_WIDTH
- IEEE80211_CHANCTX_CHANGE_RADAR
- IEEE80211_CHANCTX_CHANGE_RX_CHAINS
- IEEE80211_CHANCTX_CHANGE_WIDTH
- IEEE80211_CHANCTX_EXCLUSIVE
- IEEE80211_CHANCTX_REPLACES_OTHER
- IEEE80211_CHANCTX_REPLACE_NONE
- IEEE80211_CHANCTX_SHARED
- IEEE80211_CHANCTX_WILL_BE_REPLACED
- IEEE80211_CHANNEL_TIME
- IEEE80211_CHAN_2GHZ
- IEEE80211_CHAN_5GHZ
- IEEE80211_CHAN_CCK
- IEEE80211_CHAN_DISABLED
- IEEE80211_CHAN_DYN
- IEEE80211_CHAN_HALF
- IEEE80211_CHAN_INDOOR_ONLY
- IEEE80211_CHAN_IR_CONCURRENT
- IEEE80211_CHAN_NO_10MHZ
- IEEE80211_CHAN_NO_160MHZ
- IEEE80211_CHAN_NO_20MHZ
- IEEE80211_CHAN_NO_80MHZ
- IEEE80211_CHAN_NO_HT40
- IEEE80211_CHAN_NO_HT40MINUS
- IEEE80211_CHAN_NO_HT40PLUS
- IEEE80211_CHAN_NO_IBSS
- IEEE80211_CHAN_NO_IR
- IEEE80211_CHAN_NO_OFDM
- IEEE80211_CHAN_OFDM
- IEEE80211_CHAN_PASSIVE_SCAN
- IEEE80211_CHAN_QUARTER
- IEEE80211_CHAN_RADAR
- IEEE80211_CMAC_PN_LEN
- IEEE80211_CONF_CHANGE_CHANNEL
- IEEE80211_CONF_CHANGE_IDLE
- IEEE80211_CONF_CHANGE_LISTEN_INTERVAL
- IEEE80211_CONF_CHANGE_MONITOR
- IEEE80211_CONF_CHANGE_POWER
- IEEE80211_CONF_CHANGE_PS
- IEEE80211_CONF_CHANGE_RETRY_LIMITS
- IEEE80211_CONF_CHANGE_SMPS
- IEEE80211_CONF_IDLE
- IEEE80211_CONF_MONITOR
- IEEE80211_CONF_OFFCHANNEL
- IEEE80211_CONF_PS
- IEEE80211_CONNECTION_IDLE_TIME
- IEEE80211_COUNTRY_EXTENSION_ID
- IEEE80211_COUNTRY_IE_MIN_LEN
- IEEE80211_COUNTRY_STRING_LEN
- IEEE80211_CRYPTO_TKIP_COUNTERMEASURES
- IEEE80211_CRYPT_H
- IEEE80211_CTL_EXT_DMG_CTS
- IEEE80211_CTL_EXT_DMG_DTS
- IEEE80211_CTL_EXT_GRANT
- IEEE80211_CTL_EXT_POLL
- IEEE80211_CTL_EXT_SPR
- IEEE80211_CTL_EXT_SSW
- IEEE80211_CTL_EXT_SSW_ACK
- IEEE80211_CTL_EXT_SSW_FBACK
- IEEE80211_CTL_FRAME
- IEEE80211_DATA_HDR3_LEN
- IEEE80211_DATA_HDR4_LEN
- IEEE80211_DATA_LEN
- IEEE80211_DEAUTH_FRAME_LEN
- IEEE80211_DEBUG
- IEEE80211_DEBUG_DATA
- IEEE80211_DEBUG_DROP
- IEEE80211_DEBUG_EAP
- IEEE80211_DEBUG_FRAG
- IEEE80211_DEBUG_INFO
- IEEE80211_DEBUG_MGMT
- IEEE80211_DEBUG_QOS
- IEEE80211_DEBUG_RX
- IEEE80211_DEBUG_SCAN
- IEEE80211_DEBUG_STATE
- IEEE80211_DEBUG_TX
- IEEE80211_DEBUG_WX
- IEEE80211_DEFAULT_AIRTIME_WEIGHT
- IEEE80211_DEFAULT_BASIC_RATE
- IEEE80211_DEFAULT_MAX_SP_LEN
- IEEE80211_DEFAULT_RATES_MASK
- IEEE80211_DEFAULT_TX_ESSID
- IEEE80211_DEFAULT_UAPSD_QUEUES
- IEEE80211_DELBA_PARAM_INITIATOR_MASK
- IEEE80211_DELBA_PARAM_TID_MASK
- IEEE80211_DEV_TO_SUB_IF
- IEEE80211_DFS_MIN_CAC_TIME_MS
- IEEE80211_DFS_MIN_NOP_TIME_MS
- IEEE80211_DL_BA
- IEEE80211_DL_DATA
- IEEE80211_DL_DROP
- IEEE80211_DL_EAP
- IEEE80211_DL_ERR
- IEEE80211_DL_FRAG
- IEEE80211_DL_HT
- IEEE80211_DL_INFO
- IEEE80211_DL_IOT
- IEEE80211_DL_IPS
- IEEE80211_DL_MGMT
- IEEE80211_DL_QOS
- IEEE80211_DL_REORDER
- IEEE80211_DL_RX
- IEEE80211_DL_SCAN
- IEEE80211_DL_STATE
- IEEE80211_DL_TRACE
- IEEE80211_DL_TS
- IEEE80211_DL_TX
- IEEE80211_DL_WX
- IEEE80211_DTIM_INVALID
- IEEE80211_DTIM_MBCAST
- IEEE80211_DTIM_UCAST
- IEEE80211_DTIM_VALID
- IEEE80211_DUR_DS_FAST_ACK
- IEEE80211_DUR_DS_FAST_CTS
- IEEE80211_DUR_DS_FAST_PLCPHDR
- IEEE80211_DUR_DS_LONG_PREAMBLE
- IEEE80211_DUR_DS_SHORT_PREAMBLE
- IEEE80211_DUR_DS_SIFS
- IEEE80211_DUR_DS_SLOT
- IEEE80211_DUR_DS_SLOW_ACK
- IEEE80211_DUR_DS_SLOW_CTS
- IEEE80211_DUR_DS_SLOW_PLCPHDR
- IEEE80211_EDMG_BW_CONFIG_10
- IEEE80211_EDMG_BW_CONFIG_11
- IEEE80211_EDMG_BW_CONFIG_12
- IEEE80211_EDMG_BW_CONFIG_13
- IEEE80211_EDMG_BW_CONFIG_14
- IEEE80211_EDMG_BW_CONFIG_15
- IEEE80211_EDMG_BW_CONFIG_4
- IEEE80211_EDMG_BW_CONFIG_5
- IEEE80211_EDMG_BW_CONFIG_6
- IEEE80211_EDMG_BW_CONFIG_7
- IEEE80211_EDMG_BW_CONFIG_8
- IEEE80211_EDMG_BW_CONFIG_9
- IEEE80211_ENCRYPT_HEADROOM
- IEEE80211_ENCRYPT_TAILROOM
- IEEE80211_ERROR
- IEEE80211_FAST_XMIT_MAX_IV
- IEEE80211_FC0_SUBTYPE_MASK
- IEEE80211_FC0_SUBTYPE_QOS
- IEEE80211_FC0_TYPE_DATA
- IEEE80211_FC0_TYPE_MASK
- IEEE80211_FCS_LEN
- IEEE80211_FCTL_CTL_EXT
- IEEE80211_FCTL_DSTODS
- IEEE80211_FCTL_FRAMETYPE
- IEEE80211_FCTL_FROMDS
- IEEE80211_FCTL_FTYPE
- IEEE80211_FCTL_MOREDATA
- IEEE80211_FCTL_MOREFRAGS
- IEEE80211_FCTL_ORDER
- IEEE80211_FCTL_PM
- IEEE80211_FCTL_PROTECTED
- IEEE80211_FCTL_RETRY
- IEEE80211_FCTL_STYPE
- IEEE80211_FCTL_TODS
- IEEE80211_FCTL_VERS
- IEEE80211_FCTL_WEP
- IEEE80211_FC_DSTODS
- IEEE80211_FC_FROMDS
- IEEE80211_FC_FROMDS_MASK
- IEEE80211_FC_NODS
- IEEE80211_FC_SUBTYPE_MASK
- IEEE80211_FC_TODS
- IEEE80211_FC_TODS_MASK
- IEEE80211_FC_TOFROMDS_MASK
- IEEE80211_FC_TYPE_CTL
- IEEE80211_FC_TYPE_DATA
- IEEE80211_FC_TYPE_MASK
- IEEE80211_FC_TYPE_MGT
- IEEE80211_FC_VERSION_MASK
- IEEE80211_FIRST_TSPEC_TSID
- IEEE80211_FRAGMENT_MAX
- IEEE80211_FRAG_CACHE_LEN
- IEEE80211_FRAME_LEN
- IEEE80211_FRAME_RELEASE_PSPOLL
- IEEE80211_FRAME_RELEASE_UAPSD
- IEEE80211_FTYPE_CTL
- IEEE80211_FTYPE_DATA
- IEEE80211_FTYPE_EXT
- IEEE80211_FTYPE_MGMT
- IEEE80211_GCMP_HDR_LEN
- IEEE80211_GCMP_MIC_LEN
- IEEE80211_GCMP_PN_LEN
- IEEE80211_GMAC_PN_LEN
- IEEE80211_H
- IEEE80211_HEADER
- IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_LEVEL_1
- IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_LEVEL_2
- IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_LEVEL_3
- IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_MASK
- IEEE80211_HE_MAC_CAP0_DYNAMIC_FRAG_NOT_SUPP
- IEEE80211_HE_MAC_CAP0_HTC_HE
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_1
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_16
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_2
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_32
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_4
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_64
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_8
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_MASK
- IEEE80211_HE_MAC_CAP0_MAX_NUM_FRAG_MSDU_UNLIMITED
- IEEE80211_HE_MAC_CAP0_TWT_REQ
- IEEE80211_HE_MAC_CAP0_TWT_RES
- IEEE80211_HE_MAC_CAP1_LINK_ADAPTATION
- IEEE80211_HE_MAC_CAP1_MIN_FRAG_SIZE_128
- IEEE80211_HE_MAC_CAP1_MIN_FRAG_SIZE_256
- IEEE80211_HE_MAC_CAP1_MIN_FRAG_SIZE_512
- IEEE80211_HE_MAC_CAP1_MIN_FRAG_SIZE_MASK
- IEEE80211_HE_MAC_CAP1_MIN_FRAG_SIZE_UNLIMITED
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_1
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_2
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_3
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_4
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_5
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_6
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_7
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8
- IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_MASK
- IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_0US
- IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US
- IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_8US
- IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK
- IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP
- IEEE80211_HE_MAC_CAP2_ACK_EN
- IEEE80211_HE_MAC_CAP2_ALL_ACK
- IEEE80211_HE_MAC_CAP2_BCAST_TWT
- IEEE80211_HE_MAC_CAP2_BSR
- IEEE80211_HE_MAC_CAP2_LINK_ADAPTATION
- IEEE80211_HE_MAC_CAP2_MU_CASCADING
- IEEE80211_HE_MAC_CAP2_TRS
- IEEE80211_HE_MAC_CAP3_AMSDU_FRAG
- IEEE80211_HE_MAC_CAP3_FLEX_TWT_SCHED
- IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK
- IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_RESERVED
- IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_USE_VHT
- IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_1
- IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_VHT_2
- IEEE80211_HE_MAC_CAP3_OFDMA_RA
- IEEE80211_HE_MAC_CAP3_OMI_CONTROL
- IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS
- IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU
- IEEE80211_HE_MAC_CAP4_BQR
- IEEE80211_HE_MAC_CAP4_BSRP_BQRP_A_MPDU_AGG
- IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39
- IEEE80211_HE_MAC_CAP4_NDP_FB_REP
- IEEE80211_HE_MAC_CAP4_OPS
- IEEE80211_HE_MAC_CAP4_QTP
- IEEE80211_HE_MAC_CAP4_SRP_RESP
- IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS
- IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX
- IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40
- IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41
- IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX
- IEEE80211_HE_MAC_CAP5_PUNCTURED_SOUNDING
- IEEE80211_HE_MAC_CAP5_SUBCHAN_SELECVITE_TRANSMISSION
- IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU
- IEEE80211_HE_MCS_NOT_SUPPORTED
- IEEE80211_HE_MCS_SUPPORT_0_11
- IEEE80211_HE_MCS_SUPPORT_0_7
- IEEE80211_HE_MCS_SUPPORT_0_9
- IEEE80211_HE_OPERATION_6GHZ_OP_INFO
- IEEE80211_HE_OPERATION_BSS_COLOR_DISABLED
- IEEE80211_HE_OPERATION_BSS_COLOR_MASK
- IEEE80211_HE_OPERATION_BSS_COLOR_OFFSET
- IEEE80211_HE_OPERATION_CO_HOSTED_BSS
- IEEE80211_HE_OPERATION_DFLT_PE_DURATION_MASK
- IEEE80211_HE_OPERATION_ER_SU_DISABLE
- IEEE80211_HE_OPERATION_PARTIAL_BSS_COLOR
- IEEE80211_HE_OPERATION_RTS_THRESHOLD_MASK
- IEEE80211_HE_OPERATION_RTS_THRESHOLD_OFFSET
- IEEE80211_HE_OPERATION_TWT_REQUIRED
- IEEE80211_HE_OPERATION_VHT_OPER_INFO
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G
- IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G
- IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A
- IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US
- IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD
- IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS
- IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_160MHZ_ONLY_SECOND_20MHZ
- IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_160MHZ_ONLY_SECOND_40MHZ
- IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_80MHZ_ONLY_SECOND_20MHZ
- IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_80MHZ_ONLY_SECOND_40MHZ
- IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK
- IEEE80211_HE_PHY_CAP2_DOPPLER_RX
- IEEE80211_HE_PHY_CAP2_DOPPLER_TX
- IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS
- IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US
- IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ
- IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ
- IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO
- IEEE80211_HE_PHY_CAP2_UL_MU_PARTIAL_MU_MIMO
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_MASK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_NO_DCM
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_MASK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_NO_DCM
- IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK
- IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1
- IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_2
- IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1
- IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2
- IEEE80211_HE_PHY_CAP3_RX_HE_MU_PPDU_FROM_NON_AP_STA
- IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_6
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_7
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_MASK
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_6
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_7
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8
- IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_MASK
- IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER
- IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_1
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_3
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_4
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_5
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_6
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_7
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_8
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_1
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_3
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_4
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_5
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_6
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_7
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_8
- IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK
- IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK
- IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK
- IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU
- IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU
- IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO
- IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE
- IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT
- IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB
- IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMER_FB
- IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMER_FB
- IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI
- IEEE80211_HE_PHY_CAP7_MAX_NC_1
- IEEE80211_HE_PHY_CAP7_MAX_NC_2
- IEEE80211_HE_PHY_CAP7_MAX_NC_3
- IEEE80211_HE_PHY_CAP7_MAX_NC_4
- IEEE80211_HE_PHY_CAP7_MAX_NC_5
- IEEE80211_HE_PHY_CAP7_MAX_NC_6
- IEEE80211_HE_PHY_CAP7_MAX_NC_7
- IEEE80211_HE_PHY_CAP7_MAX_NC_MASK
- IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR
- IEEE80211_HE_PHY_CAP7_SRP_BASED_SR
- IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ
- IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ
- IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU
- IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G
- IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU
- IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242
- IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_2x996
- IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484
- IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996
- IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_MASK
- IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI
- IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI
- IEEE80211_HE_PHY_CAP8_MIDAMBLE_RX_TX_2X_AND_1XLTF
- IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM
- IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_0US
- IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_16US
- IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_8US
- IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_MASK
- IEEE80211_HE_PHY_CAP9_NOMIMAL_PKT_PADDING_RESERVED
- IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK
- IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU
- IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB
- IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB
- IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU
- IEEE80211_HE_PPE_THRES_MAX_LEN
- IEEE80211_HE_SPR_NON_SRG_OFFSET_PRESENT
- IEEE80211_HE_SPR_SRG_INFORMATION_PRESENT
- IEEE80211_HLEN
- IEEE80211_HT_AMPDU_PARM_DENSITY
- IEEE80211_HT_AMPDU_PARM_DENSITY_SHIFT
- IEEE80211_HT_AMPDU_PARM_FACTOR
- IEEE80211_HT_CAP_40MHZ_INTOLERANT
- IEEE80211_HT_CAP_AMPDU_DENSITY
- IEEE80211_HT_CAP_AMPDU_FACTOR
- IEEE80211_HT_CAP_DELAY_BA
- IEEE80211_HT_CAP_DSSSCCK40
- IEEE80211_HT_CAP_GRN_FLD
- IEEE80211_HT_CAP_LDPC_CODING
- IEEE80211_HT_CAP_LSIG_TXOP_PROT
- IEEE80211_HT_CAP_MAX_AMSDU
- IEEE80211_HT_CAP_MAX_STREAMS
- IEEE80211_HT_CAP_MCS_TX_DEFINED
- IEEE80211_HT_CAP_MCS_TX_RX_DIFF
- IEEE80211_HT_CAP_MCS_TX_STREAMS
- IEEE80211_HT_CAP_MCS_TX_UEQM
- IEEE80211_HT_CAP_RESERVED
- IEEE80211_HT_CAP_RX_STBC
- IEEE80211_HT_CAP_RX_STBC_1R
- IEEE80211_HT_CAP_RX_STBC_2R
- IEEE80211_HT_CAP_RX_STBC_3R
- IEEE80211_HT_CAP_RX_STBC_SHIFT
- IEEE80211_HT_CAP_SGI_20
- IEEE80211_HT_CAP_SGI_40
- IEEE80211_HT_CAP_SM_PS
- IEEE80211_HT_CAP_SM_PS_SHIFT
- IEEE80211_HT_CAP_SUP_WIDTH
- IEEE80211_HT_CAP_SUP_WIDTH_20_40
- IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP
- IEEE80211_HT_CAP_TXBF_RX_NDP
- IEEE80211_HT_CAP_TXBF_TX_NDP
- IEEE80211_HT_CAP_TX_STBC
- IEEE80211_HT_CHANWIDTH_20MHZ
- IEEE80211_HT_CHANWIDTH_ANY
- IEEE80211_HT_CTL_LEN
- IEEE80211_HT_EXT_CAP_HTC_SUP
- IEEE80211_HT_EXT_CAP_MCS_FB
- IEEE80211_HT_EXT_CAP_MCS_FB_SHIFT
- IEEE80211_HT_EXT_CAP_PCO
- IEEE80211_HT_EXT_CAP_PCO_TIME
- IEEE80211_HT_EXT_CAP_PCO_TIME_SHIFT
- IEEE80211_HT_EXT_CAP_RD_RESPONDER
- IEEE80211_HT_IE_CHA_SEC_ABOVE
- IEEE80211_HT_IE_CHA_SEC_BELOW
- IEEE80211_HT_IE_CHA_SEC_NONE
- IEEE80211_HT_IE_CHA_SEC_OFFSET
- IEEE80211_HT_IE_CHA_WIDTH
- IEEE80211_HT_IE_HT_PROTECTION
- IEEE80211_HT_IE_NON_GF_STA_PRSNT
- IEEE80211_HT_IE_NON_HT_STA_PRSNT
- IEEE80211_HT_MAX_AMPDU_16K
- IEEE80211_HT_MAX_AMPDU_32K
- IEEE80211_HT_MAX_AMPDU_64K
- IEEE80211_HT_MAX_AMPDU_8K
- IEEE80211_HT_MAX_AMPDU_FACTOR
- IEEE80211_HT_MCS_MASK_LEN
- IEEE80211_HT_MCS_RX_HIGHEST_MASK
- IEEE80211_HT_MCS_TX_DEFINED
- IEEE80211_HT_MCS_TX_MAX_STREAMS
- IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK
- IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT
- IEEE80211_HT_MCS_TX_RX_DIFF
- IEEE80211_HT_MCS_TX_UNEQUAL_MODULATION
- IEEE80211_HT_MCS_UNEQUAL_MODULATION_START
- IEEE80211_HT_MCS_UNEQUAL_MODULATION_START_BYTE
- IEEE80211_HT_MPDU_DENSITY_0_25
- IEEE80211_HT_MPDU_DENSITY_0_5
- IEEE80211_HT_MPDU_DENSITY_1
- IEEE80211_HT_MPDU_DENSITY_16
- IEEE80211_HT_MPDU_DENSITY_2
- IEEE80211_HT_MPDU_DENSITY_4
- IEEE80211_HT_MPDU_DENSITY_8
- IEEE80211_HT_MPDU_DENSITY_NONE
- IEEE80211_HT_OP_MODE_CCFS2_MASK
- IEEE80211_HT_OP_MODE_CCFS2_SHIFT
- IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT
- IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT
- IEEE80211_HT_OP_MODE_PROTECTION
- IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
- IEEE80211_HT_OP_MODE_PROTECTION_NONE
- IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED
- IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER
- IEEE80211_HT_PARAM_CHAN_WIDTH_ANY
- IEEE80211_HT_PARAM_CHA_SEC_ABOVE
- IEEE80211_HT_PARAM_CHA_SEC_BELOW
- IEEE80211_HT_PARAM_CHA_SEC_NONE
- IEEE80211_HT_PARAM_CHA_SEC_OFFSET
- IEEE80211_HT_PARAM_RIFS_MODE
- IEEE80211_HT_STBC_PARAM_DUAL_BEACON
- IEEE80211_HT_STBC_PARAM_DUAL_CTS_PROT
- IEEE80211_HT_STBC_PARAM_LSIG_TXOP_FULLPROT
- IEEE80211_HT_STBC_PARAM_PCO_ACTIVE
- IEEE80211_HT_STBC_PARAM_PCO_PHASE
- IEEE80211_HT_STBC_PARAM_STBC_BEACON
- IEEE80211_HW_AMPDU_AGGREGATION
- IEEE80211_HW_AMPDU_KEYBORDER_SUPPORT
- IEEE80211_HW_AP_LINK_PS
- IEEE80211_HW_BEACON_TX_STATUS
- IEEE80211_HW_BUFF_MMPDU_TXQ
- IEEE80211_HW_CHANCTX_STA_CSA
- IEEE80211_HW_CONNECTION_MONITOR
- IEEE80211_HW_DEAUTH_NEED_MGD_TX_PREP
- IEEE80211_HW_DOESNT_SUPPORT_QOS_NDP
- IEEE80211_HW_HAS_RATE_CONTROL
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
- IEEE80211_HW_MFP_CAPABLE
- IEEE80211_HW_NEEDS_UNIQUE_STA_ADDR
- IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC
- IEEE80211_HW_NO_AUTO_VIF
- IEEE80211_HW_P2P_DEV_ADDR_FOR_INTF
- IEEE80211_HW_PS_NULLFUNC_STACK
- IEEE80211_HW_QUEUE_CONTROL
- IEEE80211_HW_REPORTS_LOW_ACK
- IEEE80211_HW_REPORTS_TX_ACK_STATUS
- IEEE80211_HW_RX_INCLUDES_FCS
- IEEE80211_HW_SIGNAL_DBM
- IEEE80211_HW_SIGNAL_UNSPEC
- IEEE80211_HW_SINGLE_SCAN_ON_ALL_BANDS
- IEEE80211_HW_SPECTRUM_MGMT
- IEEE80211_HW_STA_MMPDU_TXQ
- IEEE80211_HW_SUPPORTS_AMSDU_IN_AMPDU
- IEEE80211_HW_SUPPORTS_CLONED_SKBS
- IEEE80211_HW_SUPPORTS_DYNAMIC_PS
- IEEE80211_HW_SUPPORTS_HT_CCK_RATES
- IEEE80211_HW_SUPPORTS_MULTI_BSSID
- IEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID
- IEEE80211_HW_SUPPORTS_PER_STA_GTK
- IEEE80211_HW_SUPPORTS_PS
- IEEE80211_HW_SUPPORTS_RC_TABLE
- IEEE80211_HW_SUPPORTS_REORDERING_BUFFER
- IEEE80211_HW_SUPPORTS_TDLS_BUFFER_STA
- IEEE80211_HW_SUPPORTS_TX_FRAG
- IEEE80211_HW_SUPPORTS_VHT_EXT_NSS_BW
- IEEE80211_HW_SUPPORT_FAST_XMIT
- IEEE80211_HW_SW_CRYPTO_CONTROL
- IEEE80211_HW_TDLS_WIDER_BW
- IEEE80211_HW_TIMING_BEACON_ONLY
- IEEE80211_HW_TX_AMPDU_SETUP_IN_HW
- IEEE80211_HW_TX_AMSDU
- IEEE80211_HW_TX_FRAG_LIST
- IEEE80211_HW_TX_STATUS_NO_AMPDU_LEN
- IEEE80211_HW_USES_RSS
- IEEE80211_HW_WANT_MONITOR_VIF
- IEEE80211_IBSS_INACTIVITY_LIMIT
- IEEE80211_IBSS_JOIN_TIMEOUT
- IEEE80211_IBSS_MAX_STA_ENTRIES
- IEEE80211_IBSS_MERGE_INTERVAL
- IEEE80211_IBSS_MLME_JOINED
- IEEE80211_IBSS_MLME_SEARCH
- IEEE80211_IBSS_RSN_INACTIVITY_LIMIT
- IEEE80211_IFACE_ITER_ACTIVE
- IEEE80211_IFACE_ITER_NORMAL
- IEEE80211_IFACE_ITER_RESUME_ALL
- IEEE80211_IFSTA_MESH_CTR_INC
- IEEE80211_IF_FILE
- IEEE80211_IF_FILE_R
- IEEE80211_IF_FILE_RW
- IEEE80211_IF_FILE_W
- IEEE80211_IF_FMT
- IEEE80211_IF_FMT_ATOMIC
- IEEE80211_IF_FMT_DEC
- IEEE80211_IF_FMT_HEX
- IEEE80211_IF_FMT_HEXARRAY
- IEEE80211_IF_FMT_JIFFIES_TO_MS
- IEEE80211_IF_FMT_LHEX
- IEEE80211_IF_FMT_MAC
- IEEE80211_IF_FMT_SIZE
- IEEE80211_INVAL_HW_QUEUE
- IEEE80211_IRQSAFE_QUEUE_LIMIT
- IEEE80211_I_H
- IEEE80211_KEY_CONF
- IEEE80211_KEY_FLAG_GENERATE_IV
- IEEE80211_KEY_FLAG_GENERATE_IV_MGMT
- IEEE80211_KEY_FLAG_GENERATE_MMIC
- IEEE80211_KEY_FLAG_GENERATE_MMIE
- IEEE80211_KEY_FLAG_NO_AUTO_TX
- IEEE80211_KEY_FLAG_PAIRWISE
- IEEE80211_KEY_FLAG_PUT_IV_SPACE
- IEEE80211_KEY_FLAG_PUT_MIC_SPACE
- IEEE80211_KEY_FLAG_RESERVE_TAILROOM
- IEEE80211_KEY_FLAG_RX_MGMT
- IEEE80211_KEY_FLAG_SW_MGMT_TX
- IEEE80211_KEY_H
- IEEE80211_LINKED
- IEEE80211_LINKED_SCANNING
- IEEE80211_MAX_AID
- IEEE80211_MAX_AMPDU_BUF
- IEEE80211_MAX_AMPDU_BUF_HT
- IEEE80211_MAX_CHAINS
- IEEE80211_MAX_CSA_COUNTERS_NUM
- IEEE80211_MAX_DATA_LEN
- IEEE80211_MAX_DATA_LEN_DMG
- IEEE80211_MAX_FRAG_THRESHOLD
- IEEE80211_MAX_FRAME_LEN
- IEEE80211_MAX_MESH_ID_LEN
- IEEE80211_MAX_MESH_PEERINGS
- IEEE80211_MAX_MPDU_LEN
- IEEE80211_MAX_MPDU_LEN_HT_3839
- IEEE80211_MAX_MPDU_LEN_HT_7935
- IEEE80211_MAX_MPDU_LEN_HT_BA
- IEEE80211_MAX_MPDU_LEN_VHT_11454
- IEEE80211_MAX_MPDU_LEN_VHT_3895
- IEEE80211_MAX_MPDU_LEN_VHT_7991
- IEEE80211_MAX_NAN_INSTANCE_ID
- IEEE80211_MAX_PN_LEN
- IEEE80211_MAX_QUEUES
- IEEE80211_MAX_QUEUE_MAP
- IEEE80211_MAX_RTS_THRESHOLD
- IEEE80211_MAX_SN
- IEEE80211_MAX_SSID_LEN
- IEEE80211_MAX_SUPP_RATES
- IEEE80211_MAX_TIM_LEN
- IEEE80211_MAX_TX_RETRY
- IEEE80211_MEASUREMENT_ENABLE
- IEEE80211_MEASUREMENT_REPORT
- IEEE80211_MEASUREMENT_REQUEST
- IEEE80211_MESHCONF_CAPAB_ACCEPT_PLINKS
- IEEE80211_MESHCONF_CAPAB_FORWARDING
- IEEE80211_MESHCONF_CAPAB_POWER_SAVE_LEVEL
- IEEE80211_MESHCONF_CAPAB_TBTT_ADJUSTING
- IEEE80211_MESHCONF_FORM_CONNECTED_TO_GATE
- IEEE80211_MESH_CSA_ROLE_INIT
- IEEE80211_MESH_CSA_ROLE_NONE
- IEEE80211_MESH_CSA_ROLE_REPEATER
- IEEE80211_MESH_HOUSEKEEPING_INTERVAL
- IEEE80211_MESH_SEC_AUTHED
- IEEE80211_MESH_SEC_NONE
- IEEE80211_MESH_SEC_SECURED
- IEEE80211_MFP_DISABLED
- IEEE80211_MFP_OPTIONAL
- IEEE80211_MFP_REQUIRED
- IEEE80211_MGMT_FRAME
- IEEE80211_MGMT_HDR_LEN
- IEEE80211_MIN_ACTION_SIZE
- IEEE80211_MIN_AMPDU_BUF
- IEEE80211_MS_TO_TU
- IEEE80211_NOLINK
- IEEE80211_NONQOS_TID
- IEEE80211_NUM_ACS
- IEEE80211_NUM_CCK_RATES
- IEEE80211_NUM_OFDM_RATES
- IEEE80211_NUM_OFDM_RATESLEN
- IEEE80211_NUM_TIDS
- IEEE80211_NUM_UPS
- IEEE80211_OCB_HOUSEKEEPING_INTERVAL
- IEEE80211_OCB_MAX_STA_ENTRIES
- IEEE80211_OCB_PEER_INACTIVITY_LIMIT
- IEEE80211_OFDM_BASIC_RATES_MASK
- IEEE80211_OFDM_DEFAULT_RATES_MASK
- IEEE80211_OFDM_MODULATION
- IEEE80211_OFDM_RATES_MASK
- IEEE80211_OFDM_RATE_12MB
- IEEE80211_OFDM_RATE_12MB_MASK
- IEEE80211_OFDM_RATE_18MB
- IEEE80211_OFDM_RATE_18MB_MASK
- IEEE80211_OFDM_RATE_24MB
- IEEE80211_OFDM_RATE_24MB_MASK
- IEEE80211_OFDM_RATE_36MB
- IEEE80211_OFDM_RATE_36MB_MASK
- IEEE80211_OFDM_RATE_48MB
- IEEE80211_OFDM_RATE_48MB_MASK
- IEEE80211_OFDM_RATE_54MB
- IEEE80211_OFDM_RATE_54MB_MASK
- IEEE80211_OFDM_RATE_6MB
- IEEE80211_OFDM_RATE_6MB_MASK
- IEEE80211_OFDM_RATE_9MB
- IEEE80211_OFDM_RATE_9MB_MASK
- IEEE80211_OFDM_RATE_LEN
- IEEE80211_OFDM_SHIFT_MASK_A
- IEEE80211_OPMODE_NOTIF_CHANWIDTH_160MHZ
- IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ
- IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ
- IEEE80211_OPMODE_NOTIF_CHANWIDTH_80MHZ
- IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK
- IEEE80211_OPMODE_NOTIF_RX_NSS_MASK
- IEEE80211_OPMODE_NOTIF_RX_NSS_SHIFT
- IEEE80211_OPMODE_NOTIF_RX_NSS_TYPE_BF
- IEEE80211_P2P_ATTR_ABSENCE_NOTICE
- IEEE80211_P2P_ATTR_CAPABILITY
- IEEE80211_P2P_ATTR_CHANNEL_LIST
- IEEE80211_P2P_ATTR_DEVICE_ID
- IEEE80211_P2P_ATTR_DEVICE_INFO
- IEEE80211_P2P_ATTR_EXT_LISTEN_TIMING
- IEEE80211_P2P_ATTR_GO_CONFIG_TIMEOUT
- IEEE80211_P2P_ATTR_GO_INTENT
- IEEE80211_P2P_ATTR_GROUP_BSSID
- IEEE80211_P2P_ATTR_GROUP_ID
- IEEE80211_P2P_ATTR_GROUP_INFO
- IEEE80211_P2P_ATTR_INTENDED_IFACE_ADDR
- IEEE80211_P2P_ATTR_INTERFACE
- IEEE80211_P2P_ATTR_INVITE_FLAGS
- IEEE80211_P2P_ATTR_LISTEN_CHANNEL
- IEEE80211_P2P_ATTR_MANAGABILITY
- IEEE80211_P2P_ATTR_MAX
- IEEE80211_P2P_ATTR_MINOR_REASON
- IEEE80211_P2P_ATTR_OPER_CHANNEL
- IEEE80211_P2P_ATTR_STATUS
- IEEE80211_P2P_ATTR_VENDOR_SPECIFIC
- IEEE80211_P2P_NOA_DESC_MAX
- IEEE80211_P2P_OPPPS_CTWINDOW_MASK
- IEEE80211_P2P_OPPPS_ENABLE_BIT
- IEEE80211_PASSIVE_CHANNEL_TIME
- IEEE80211_PATH_METRIC_AIRTIME
- IEEE80211_PATH_METRIC_VENDOR
- IEEE80211_PATH_PROTOCOL_HWMP
- IEEE80211_PATH_PROTOCOL_VENDOR
- IEEE80211_PPE_THRES_INFO_PPET_SIZE
- IEEE80211_PPE_THRES_NSS_MASK
- IEEE80211_PPE_THRES_NSS_POS
- IEEE80211_PPE_THRES_NSS_SUPPORT_2NSS
- IEEE80211_PPE_THRES_RU_INDEX_BITMASK_2x966_AND_966_RU
- IEEE80211_PPE_THRES_RU_INDEX_BITMASK_MASK
- IEEE80211_PPE_THRES_RU_INDEX_BITMASK_POS
- IEEE80211_PREQ_PROACTIVE_PREP_FLAG
- IEEE80211_PREQ_TO_FLAG
- IEEE80211_PREQ_USN_FLAG
- IEEE80211_PRIVACY
- IEEE80211_PRIVACY_ANY
- IEEE80211_PRIVACY_OFF
- IEEE80211_PRIVACY_ON
- IEEE80211_PROACTIVE_PREQ_NO_PREP
- IEEE80211_PROACTIVE_PREQ_WITH_PREP
- IEEE80211_PROACTIVE_RANN
- IEEE80211_PROBE_DELAY
- IEEE80211_PROBE_FLAG_DIRECTED
- IEEE80211_PROBE_FLAG_MIN_CONTENT
- IEEE80211_PROBE_FLAG_RANDOM_SN
- IEEE80211_PS_DISABLED
- IEEE80211_PS_MBCAST
- IEEE80211_PS_UNICAST
- IEEE80211_QCTL_TID
- IEEE80211_QOS_CTL_ACK_POLICY_BLOCKACK
- IEEE80211_QOS_CTL_ACK_POLICY_MASK
- IEEE80211_QOS_CTL_ACK_POLICY_NOACK
- IEEE80211_QOS_CTL_ACK_POLICY_NORMAL
- IEEE80211_QOS_CTL_ACK_POLICY_NO_EXPL
- IEEE80211_QOS_CTL_A_MSDU_PRESENT
- IEEE80211_QOS_CTL_EOSP
- IEEE80211_QOS_CTL_LEN
- IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT
- IEEE80211_QOS_CTL_MESH_PS_LEVEL
- IEEE80211_QOS_CTL_RSPI
- IEEE80211_QOS_CTL_TAG1D_MASK
- IEEE80211_QOS_CTL_TID_MASK
- IEEE80211_QOS_DATAGRP
- IEEE80211_QOS_HAS_SEQ
- IEEE80211_QOS_MAP_LEN_MAX
- IEEE80211_QOS_MAP_LEN_MIN
- IEEE80211_QOS_MAP_MAX_EX
- IEEE80211_QOS_TID
- IEEE80211_QUEUE_LIMIT
- IEEE80211_QUEUE_STOP_REASONS
- IEEE80211_QUEUE_STOP_REASON_AGGREGATION
- IEEE80211_QUEUE_STOP_REASON_CSA
- IEEE80211_QUEUE_STOP_REASON_DRIVER
- IEEE80211_QUEUE_STOP_REASON_FLUSH
- IEEE80211_QUEUE_STOP_REASON_OFFCHANNEL
- IEEE80211_QUEUE_STOP_REASON_PS
- IEEE80211_QUEUE_STOP_REASON_RESERVE_TID
- IEEE80211_QUEUE_STOP_REASON_SKB_ADD
- IEEE80211_QUEUE_STOP_REASON_SUSPEND
- IEEE80211_QUEUE_STOP_REASON_TDLS_TEARDOWN
- IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR
- IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN
- IEEE80211_RADIOTAP_AMPDU_EOF
- IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN
- IEEE80211_RADIOTAP_AMPDU_IS_LAST
- IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN
- IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN
- IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN
- IEEE80211_RADIOTAP_AMPDU_STATUS
- IEEE80211_RADIOTAP_ANTENNA
- IEEE80211_RADIOTAP_CHANNEL
- IEEE80211_RADIOTAP_CODING_LDPC_USER0
- IEEE80211_RADIOTAP_CODING_LDPC_USER1
- IEEE80211_RADIOTAP_CODING_LDPC_USER2
- IEEE80211_RADIOTAP_CODING_LDPC_USER3
- IEEE80211_RADIOTAP_DATA_RETRIES
- IEEE80211_RADIOTAP_DBM_ANTNOISE
- IEEE80211_RADIOTAP_DBM_ANTSIGNAL
- IEEE80211_RADIOTAP_DBM_TX_POWER
- IEEE80211_RADIOTAP_DB_ANTNOISE
- IEEE80211_RADIOTAP_DB_ANTSIGNAL
- IEEE80211_RADIOTAP_DB_TX_ATTENUATION
- IEEE80211_RADIOTAP_EXT
- IEEE80211_RADIOTAP_FHSS
- IEEE80211_RADIOTAP_FLAGS
- IEEE80211_RADIOTAP_F_BADFCS
- IEEE80211_RADIOTAP_F_CFP
- IEEE80211_RADIOTAP_F_DATAPAD
- IEEE80211_RADIOTAP_F_FCS
- IEEE80211_RADIOTAP_F_FRAG
- IEEE80211_RADIOTAP_F_RX_BADPLCP
- IEEE80211_RADIOTAP_F_SHORTPRE
- IEEE80211_RADIOTAP_F_TX_CTS
- IEEE80211_RADIOTAP_F_TX_FAIL
- IEEE80211_RADIOTAP_F_TX_NOACK
- IEEE80211_RADIOTAP_F_TX_RTS
- IEEE80211_RADIOTAP_F_WEP
- IEEE80211_RADIOTAP_HE
- IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU
- IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK
- IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU
- IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU
- IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG
- IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN
- IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC
- IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET
- IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN
- IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN
- IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE
- IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR
- IEEE80211_RADIOTAP_HE_DATA3_CODING
- IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM
- IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS
- IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG
- IEEE80211_RADIOTAP_HE_DATA3_STBC
- IEEE80211_RADIOTAP_HE_DATA3_UL_DL
- IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID
- IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE
- IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1
- IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2
- IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3
- IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ
- IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T
- IEEE80211_RADIOTAP_HE_DATA5_GI
- IEEE80211_RADIOTAP_HE_DATA5_GI_0_8
- IEEE80211_RADIOTAP_HE_DATA5_GI_1_6
- IEEE80211_RADIOTAP_HE_DATA5_GI_3_2
- IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE
- IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X
- IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X
- IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X
- IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN
- IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS
- IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG
- IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD
- IEEE80211_RADIOTAP_HE_DATA5_TXBF
- IEEE80211_RADIOTAP_HE_DATA6_DOPPLER
- IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY
- IEEE80211_RADIOTAP_HE_DATA6_NSTS
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ
- IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN
- IEEE80211_RADIOTAP_HE_DATA6_TXOP
- IEEE80211_RADIOTAP_HE_MU
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP
- IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS
- IEEE80211_RADIOTAP_LOCK_QUALITY
- IEEE80211_RADIOTAP_LSIG
- IEEE80211_RADIOTAP_LSIG_DATA1_LENGTH_KNOWN
- IEEE80211_RADIOTAP_LSIG_DATA1_RATE_KNOWN
- IEEE80211_RADIOTAP_LSIG_DATA2_LENGTH
- IEEE80211_RADIOTAP_LSIG_DATA2_RATE
- IEEE80211_RADIOTAP_MCS
- IEEE80211_RADIOTAP_MCS_BW_20
- IEEE80211_RADIOTAP_MCS_BW_20L
- IEEE80211_RADIOTAP_MCS_BW_20U
- IEEE80211_RADIOTAP_MCS_BW_40
- IEEE80211_RADIOTAP_MCS_BW_MASK
- IEEE80211_RADIOTAP_MCS_FEC_LDPC
- IEEE80211_RADIOTAP_MCS_FMT_GF
- IEEE80211_RADIOTAP_MCS_HAVE_BW
- IEEE80211_RADIOTAP_MCS_HAVE_FEC
- IEEE80211_RADIOTAP_MCS_HAVE_FMT
- IEEE80211_RADIOTAP_MCS_HAVE_GI
- IEEE80211_RADIOTAP_MCS_HAVE_MCS
- IEEE80211_RADIOTAP_MCS_HAVE_STBC
- IEEE80211_RADIOTAP_MCS_SGI
- IEEE80211_RADIOTAP_MCS_STBC_1
- IEEE80211_RADIOTAP_MCS_STBC_2
- IEEE80211_RADIOTAP_MCS_STBC_3
- IEEE80211_RADIOTAP_MCS_STBC_MASK
- IEEE80211_RADIOTAP_MCS_STBC_SHIFT
- IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE
- IEEE80211_RADIOTAP_RATE
- IEEE80211_RADIOTAP_RTS_RETRIES
- IEEE80211_RADIOTAP_RX_FLAGS
- IEEE80211_RADIOTAP_TIMESTAMP
- IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT
- IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT
- IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ
- IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN
- IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK
- IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS
- IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS
- IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US
- IEEE80211_RADIOTAP_TSFT
- IEEE80211_RADIOTAP_TX_ATTENUATION
- IEEE80211_RADIOTAP_TX_FLAGS
- IEEE80211_RADIOTAP_VENDOR_NAMESPACE
- IEEE80211_RADIOTAP_VHT
- IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED
- IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM
- IEEE80211_RADIOTAP_VHT_FLAG_SGI
- IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9
- IEEE80211_RADIOTAP_VHT_FLAG_STBC
- IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA
- IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH
- IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED
- IEEE80211_RADIOTAP_VHT_KNOWN_GI
- IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID
- IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM
- IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID
- IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS
- IEEE80211_RADIOTAP_VHT_KNOWN_STBC
- IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA
- IEEE80211_RADIOTAP_ZERO_LEN_PSDU
- IEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED
- IEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING
- IEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR
- IEEE80211_RATE_ERP_G
- IEEE80211_RATE_H
- IEEE80211_RATE_MANDATORY_A
- IEEE80211_RATE_MANDATORY_B
- IEEE80211_RATE_MANDATORY_G
- IEEE80211_RATE_SHORT_PREAMBLE
- IEEE80211_RATE_SUPPORTS_10MHZ
- IEEE80211_RATE_SUPPORTS_5MHZ
- IEEE80211_RC_BW_CHANGED
- IEEE80211_RC_NSS_CHANGED
- IEEE80211_RC_SMPS_CHANGED
- IEEE80211_RC_SUPP_RATES_CHANGED
- IEEE80211_RECONFIG_TYPE_RESTART
- IEEE80211_RECONFIG_TYPE_SUSPEND
- IEEE80211_REPORT_BASIC
- IEEE80211_REPORT_CCA
- IEEE80211_REPORT_RPI
- IEEE80211_ROC_TYPE_MGMT_TX
- IEEE80211_ROC_TYPE_NORMAL
- IEEE80211_ROOTMODE_NO_ROOT
- IEEE80211_ROOTMODE_ROOT
- IEEE80211_RX_AMSDU
- IEEE80211_RX_BEACON_REPORTED
- IEEE80211_RX_CMNTR
- IEEE80211_RX_DEFERRED_RELEASE
- IEEE80211_RX_MALFORMED_ACTION_FRM
- IEEE80211_RX_MSG
- IEEE80211_SCAN_INTERVAL
- IEEE80211_SCAN_RESULT_EXPIRE
- IEEE80211_SCTL_FRAG
- IEEE80211_SCTL_SEQ
- IEEE80211_SDATA_ALLMULTI
- IEEE80211_SDATA_DISCONNECT_RESUME
- IEEE80211_SDATA_DONT_BRIDGE_PACKETS
- IEEE80211_SDATA_IN_DRIVER
- IEEE80211_SDATA_OPERATING_GMODE
- IEEE80211_SEQ_MAX
- IEEE80211_SEQ_SEQ_SHIFT
- IEEE80211_SEQ_TO_SN
- IEEE80211_SIGNAL_AVE_MIN_COUNT
- IEEE80211_SKB_CB
- IEEE80211_SKB_RXCB
- IEEE80211_SMPS_AUTOMATIC
- IEEE80211_SMPS_DYNAMIC
- IEEE80211_SMPS_NUM_MODES
- IEEE80211_SMPS_OFF
- IEEE80211_SMPS_STATIC
- IEEE80211_SN_MASK
- IEEE80211_SN_MODULO
- IEEE80211_SN_TO_SEQ
- IEEE80211_SOFTMAC_ASSOC_RETRY_TIME
- IEEE80211_SOFTMAC_SCAN_TIME
- IEEE80211_SPCT_MSR_RPRT_MODE_INCAPABLE
- IEEE80211_SPCT_MSR_RPRT_MODE_LATE
- IEEE80211_SPCT_MSR_RPRT_MODE_REFUSED
- IEEE80211_SPCT_MSR_RPRT_TYPE_BASIC
- IEEE80211_SPCT_MSR_RPRT_TYPE_CCA
- IEEE80211_SPCT_MSR_RPRT_TYPE_CIVIC
- IEEE80211_SPCT_MSR_RPRT_TYPE_LCI
- IEEE80211_SPCT_MSR_RPRT_TYPE_RPI
- IEEE80211_STATMASK_NOISE
- IEEE80211_STATMASK_RATE
- IEEE80211_STATMASK_RSSI
- IEEE80211_STATMASK_SIGNAL
- IEEE80211_STATMASK_WEMASK
- IEEE80211_STA_ASSOC
- IEEE80211_STA_AUTH
- IEEE80211_STA_AUTHORIZED
- IEEE80211_STA_CONNECTION_POLL
- IEEE80211_STA_CONTROL_PORT
- IEEE80211_STA_DISABLE_160MHZ
- IEEE80211_STA_DISABLE_40MHZ
- IEEE80211_STA_DISABLE_80P80MHZ
- IEEE80211_STA_DISABLE_HE
- IEEE80211_STA_DISABLE_HT
- IEEE80211_STA_DISABLE_VHT
- IEEE80211_STA_DISABLE_WMM
- IEEE80211_STA_ENABLE_RRM
- IEEE80211_STA_MFP_ENABLED
- IEEE80211_STA_NONE
- IEEE80211_STA_NOTEXIST
- IEEE80211_STA_NULLFUNC_ACKED
- IEEE80211_STA_RESET_SIGNAL_AVE
- IEEE80211_STA_RX_BW_160
- IEEE80211_STA_RX_BW_20
- IEEE80211_STA_RX_BW_40
- IEEE80211_STA_RX_BW_80
- IEEE80211_STA_UAPSD_ENABLED
- IEEE80211_STYPE_ACK
- IEEE80211_STYPE_ACTION
- IEEE80211_STYPE_ASSOC_REQ
- IEEE80211_STYPE_ASSOC_RESP
- IEEE80211_STYPE_ATIM
- IEEE80211_STYPE_AUTH
- IEEE80211_STYPE_BACK
- IEEE80211_STYPE_BACK_REQ
- IEEE80211_STYPE_BEACON
- IEEE80211_STYPE_BLOCKACK
- IEEE80211_STYPE_CFACK
- IEEE80211_STYPE_CFACKPOLL
- IEEE80211_STYPE_CFEND
- IEEE80211_STYPE_CFENDACK
- IEEE80211_STYPE_CFPOLL
- IEEE80211_STYPE_CTL_EXT
- IEEE80211_STYPE_CTS
- IEEE80211_STYPE_DATA
- IEEE80211_STYPE_DATA_CFACK
- IEEE80211_STYPE_DATA_CFACKPOLL
- IEEE80211_STYPE_DATA_CFPOLL
- IEEE80211_STYPE_DEAUTH
- IEEE80211_STYPE_DISASSOC
- IEEE80211_STYPE_DMG_BEACON
- IEEE80211_STYPE_MANAGE_ACT
- IEEE80211_STYPE_NULLFUNC
- IEEE80211_STYPE_PROBE_REQ
- IEEE80211_STYPE_PROBE_RESP
- IEEE80211_STYPE_PSPOLL
- IEEE80211_STYPE_QOS_CFACK
- IEEE80211_STYPE_QOS_CFACKPOLL
- IEEE80211_STYPE_QOS_CFPOLL
- IEEE80211_STYPE_QOS_DATA
- IEEE80211_STYPE_QOS_DATA_CFACK
- IEEE80211_STYPE_QOS_DATA_CFACKPOLL
- IEEE80211_STYPE_QOS_DATA_CFPOLL
- IEEE80211_STYPE_QOS_NULL
- IEEE80211_STYPE_QOS_NULLFUNC
- IEEE80211_STYPE_REASSOC_REQ
- IEEE80211_STYPE_REASSOC_RESP
- IEEE80211_STYPE_RTS
- IEEE80211_SUPP_MCS_SET_LEN
- IEEE80211_SUPP_MCS_SET_UEQM
- IEEE80211_SYNC_METHOD_NEIGHBOR_OFFSET
- IEEE80211_SYNC_METHOD_VENDOR
- IEEE80211_TID_UNRESERVED
- IEEE80211_TKIP_ICV_LEN
- IEEE80211_TKIP_IV_LEN
- IEEE80211_TPT_LEDTRIG_FL_CONNECTED
- IEEE80211_TPT_LEDTRIG_FL_RADIO
- IEEE80211_TPT_LEDTRIG_FL_WORK
- IEEE80211_TSPEC_STATUS_ADDTS_INVAL_PARAMS
- IEEE80211_TSPEC_STATUS_ADMISS_ACCEPTED
- IEEE80211_TXQ_AMPDU
- IEEE80211_TXQ_NO_AMSDU
- IEEE80211_TXQ_STOP
- IEEE80211_TXQ_STOP_NETIF_TX
- IEEE80211_TX_CTL_AMPDU
- IEEE80211_TX_CTL_ASSIGN_SEQ
- IEEE80211_TX_CTL_CLEAR_PS_FILT
- IEEE80211_TX_CTL_DONTFRAG
- IEEE80211_TX_CTL_FIRST_FRAGMENT
- IEEE80211_TX_CTL_INJECTED
- IEEE80211_TX_CTL_LDPC
- IEEE80211_TX_CTL_MORE_FRAMES
- IEEE80211_TX_CTL_NO_ACK
- IEEE80211_TX_CTL_NO_CCK_RATE
- IEEE80211_TX_CTL_NO_PS_BUFFER
- IEEE80211_TX_CTL_RATE_CTRL_PROBE
- IEEE80211_TX_CTL_REQ_TX_STATUS
- IEEE80211_TX_CTL_SEND_AFTER_DTIM
- IEEE80211_TX_CTL_STBC
- IEEE80211_TX_CTL_STBC_SHIFT
- IEEE80211_TX_CTL_TX_OFFCHAN
- IEEE80211_TX_CTL_USE_MINRATE
- IEEE80211_TX_CTRL_AMSDU
- IEEE80211_TX_CTRL_FAST_XMIT
- IEEE80211_TX_CTRL_PORT_CTRL_PROTO
- IEEE80211_TX_CTRL_PS_RESPONSE
- IEEE80211_TX_CTRL_RATE_INJECT
- IEEE80211_TX_CTRL_SKIP_MPATH_LOOKUP
- IEEE80211_TX_INFO_DRIVER_DATA_SIZE
- IEEE80211_TX_INFO_RATE_DRIVER_DATA_SIZE
- IEEE80211_TX_INTFL_DONT_ENCRYPT
- IEEE80211_TX_INTFL_MLME_CONN_TX
- IEEE80211_TX_INTFL_NEED_TXPROCESSING
- IEEE80211_TX_INTFL_NL80211_FRAME_TX
- IEEE80211_TX_INTFL_OFFCHAN_TX_OK
- IEEE80211_TX_INTFL_RETRANSMISSION
- IEEE80211_TX_INTFL_RETRIED
- IEEE80211_TX_INTFL_TKIP_MIC_FAILURE
- IEEE80211_TX_MAX_RATES
- IEEE80211_TX_NO_SEQNO
- IEEE80211_TX_PS_BUFFERED
- IEEE80211_TX_RATE_TABLE_SIZE
- IEEE80211_TX_RC_160_MHZ_WIDTH
- IEEE80211_TX_RC_40_MHZ_WIDTH
- IEEE80211_TX_RC_80_MHZ_WIDTH
- IEEE80211_TX_RC_DUP_DATA
- IEEE80211_TX_RC_GREEN_FIELD
- IEEE80211_TX_RC_MCS
- IEEE80211_TX_RC_SHORT_GI
- IEEE80211_TX_RC_USE_CTS_PROTECT
- IEEE80211_TX_RC_USE_RTS_CTS
- IEEE80211_TX_RC_USE_SHORT_PREAMBLE
- IEEE80211_TX_RC_VHT_MCS
- IEEE80211_TX_RX_MCS_NSS_DESC_MAX_LEN
- IEEE80211_TX_RX_MCS_NSS_SUPP_HIGHEST_MCS_POS
- IEEE80211_TX_RX_MCS_NSS_SUPP_RX_BITMAP_MASK
- IEEE80211_TX_RX_MCS_NSS_SUPP_RX_BITMAP_POS
- IEEE80211_TX_RX_MCS_NSS_SUPP_TX_BITMAP_MASK
- IEEE80211_TX_RX_MCS_NSS_SUPP_TX_BITMAP_POS
- IEEE80211_TX_STATUS_EOSP
- IEEE80211_TX_STATUS_HEADROOM
- IEEE80211_TX_STATUS_MSG
- IEEE80211_TX_STAT_ACK
- IEEE80211_TX_STAT_AMPDU
- IEEE80211_TX_STAT_AMPDU_NO_BACK
- IEEE80211_TX_STAT_NOACK_TRANSMITTED
- IEEE80211_TX_STAT_TX_FILTERED
- IEEE80211_TX_TEMPORARY_FLAGS
- IEEE80211_TX_UNICAST
- IEEE80211_UNSET_POWER_LEVEL
- IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK
- IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT
- IEEE80211_VHT_CAP_EXT_NSS_BW_MASK
- IEEE80211_VHT_CAP_EXT_NSS_BW_SHIFT
- IEEE80211_VHT_CAP_HTC_VHT
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK
- IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895
- IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991
- IEEE80211_VHT_CAP_MAX_MPDU_MASK
- IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE
- IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE
- IEEE80211_VHT_CAP_RXLDPC
- IEEE80211_VHT_CAP_RXSTBC_1
- IEEE80211_VHT_CAP_RXSTBC_2
- IEEE80211_VHT_CAP_RXSTBC_3
- IEEE80211_VHT_CAP_RXSTBC_4
- IEEE80211_VHT_CAP_RXSTBC_MASK
- IEEE80211_VHT_CAP_RXSTBC_SHIFT
- IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN
- IEEE80211_VHT_CAP_SHORT_GI_160
- IEEE80211_VHT_CAP_SHORT_GI_80
- IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK
- IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT
- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ
- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ
- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK
- IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_SHIFT
- IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE
- IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE
- IEEE80211_VHT_CAP_TXSTBC
- IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN
- IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB
- IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_UNSOL_MFB
- IEEE80211_VHT_CAP_VHT_TXOP_PS
- IEEE80211_VHT_CHANWIDTH_160MHZ
- IEEE80211_VHT_CHANWIDTH_80MHZ
- IEEE80211_VHT_CHANWIDTH_80P80MHZ
- IEEE80211_VHT_CHANWIDTH_USE_HT
- IEEE80211_VHT_EXT_NSS_BW_CAPABLE
- IEEE80211_VHT_MAX_AMPDU_1024K
- IEEE80211_VHT_MAX_AMPDU_128K
- IEEE80211_VHT_MAX_AMPDU_16K
- IEEE80211_VHT_MAX_AMPDU_256K
- IEEE80211_VHT_MAX_AMPDU_32K
- IEEE80211_VHT_MAX_AMPDU_512K
- IEEE80211_VHT_MAX_AMPDU_64K
- IEEE80211_VHT_MAX_AMPDU_8K
- IEEE80211_VHT_MAX_NSTS_TOTAL_MASK
- IEEE80211_VHT_MAX_NSTS_TOTAL_SHIFT
- IEEE80211_VHT_MCS_NOT_SUPPORTED
- IEEE80211_VHT_MCS_SUPPORT_0_7
- IEEE80211_VHT_MCS_SUPPORT_0_8
- IEEE80211_VHT_MCS_SUPPORT_0_9
- IEEE80211_VIF_BEACON_FILTER
- IEEE80211_VIF_GET_NOA_UPDATE
- IEEE80211_VIF_SUPPORTS_CQM_RSSI
- IEEE80211_VIF_SUPPORTS_UAPSD
- IEEE80211_WARNING
- IEEE80211_WATCH_DOG_TIME
- IEEE80211_WDEV_TO_SUB_IF
- IEEE80211_WEP_CRCLEN
- IEEE80211_WEP_ICV_LEN
- IEEE80211_WEP_IVLEN
- IEEE80211_WEP_IV_LEN
- IEEE80211_WEP_KIDLEN
- IEEE80211_WEP_NKID
- IEEE80211_WMM_IE_AP_QOSINFO_PARAM_SET_CNT_MASK
- IEEE80211_WMM_IE_AP_QOSINFO_UAPSD
- IEEE80211_WMM_IE_STA_QOSINFO_AC_BE
- IEEE80211_WMM_IE_STA_QOSINFO_AC_BK
- IEEE80211_WMM_IE_STA_QOSINFO_AC_MASK
- IEEE80211_WMM_IE_STA_QOSINFO_AC_VI
- IEEE80211_WMM_IE_STA_QOSINFO_AC_VO
- IEEE80211_WMM_IE_STA_QOSINFO_SP_2
- IEEE80211_WMM_IE_STA_QOSINFO_SP_4
- IEEE80211_WMM_IE_STA_QOSINFO_SP_6
- IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL
- IEEE80211_WMM_IE_STA_QOSINFO_SP_MASK
- IEEE80211_WMM_IE_STA_QOSINFO_SP_SHIFT
- IEEE80211_WMM_IE_TSPEC_TID_MASK
- IEEE80211_WMM_IE_TSPEC_TID_SHIFT
- IEEE802154_ACK_PSDU_LEN
- IEEE802154_ADDR_BROADCAST
- IEEE802154_ADDR_LEN
- IEEE802154_ADDR_LONG
- IEEE802154_ADDR_NONE
- IEEE802154_ADDR_SHORT
- IEEE802154_ADDR_SHORT_BROADCAST
- IEEE802154_ADDR_SHORT_UNSPEC
- IEEE802154_ADDR_UNDEF
- IEEE802154_ADD_IFACE
- IEEE802154_AFILT_IEEEADDR_CHANGED
- IEEE802154_AFILT_PANC_CHANGED
- IEEE802154_AFILT_PANID_CHANGED
- IEEE802154_AFILT_SADDR_CHANGED
- IEEE802154_ASSOCIATE_CONF
- IEEE802154_ASSOCIATE_INDIC
- IEEE802154_ASSOCIATE_REQ
- IEEE802154_ASSOCIATE_RESP
- IEEE802154_ATTR_BAT_EXT
- IEEE802154_ATTR_BCN_ORD
- IEEE802154_ATTR_CAPABILITY
- IEEE802154_ATTR_CCA_ED_LEVEL
- IEEE802154_ATTR_CCA_MODE
- IEEE802154_ATTR_CHANNEL
- IEEE802154_ATTR_CHANNELS
- IEEE802154_ATTR_CHANNEL_PAGE_LIST
- IEEE802154_ATTR_COORD_HW_ADDR
- IEEE802154_ATTR_COORD_PAN_ID
- IEEE802154_ATTR_COORD_REALIGN
- IEEE802154_ATTR_COORD_SHORT_ADDR
- IEEE802154_ATTR_CSMA_MAX_BE
- IEEE802154_ATTR_CSMA_MIN_BE
- IEEE802154_ATTR_CSMA_RETRIES
- IEEE802154_ATTR_DEST_HW_ADDR
- IEEE802154_ATTR_DEST_PAN_ID
- IEEE802154_ATTR_DEST_SHORT_ADDR
- IEEE802154_ATTR_DEV_INDEX
- IEEE802154_ATTR_DEV_NAME
- IEEE802154_ATTR_DEV_TYPE
- IEEE802154_ATTR_DURATION
- IEEE802154_ATTR_ED_LIST
- IEEE802154_ATTR_FRAME_RETRIES
- IEEE802154_ATTR_HW_ADDR
- IEEE802154_ATTR_LBT_ENABLED
- IEEE802154_ATTR_LLSEC_CMD_FRAME_ID
- IEEE802154_ATTR_LLSEC_DEV_KEY_MODE
- IEEE802154_ATTR_LLSEC_DEV_OVERRIDE
- IEEE802154_ATTR_LLSEC_ENABLED
- IEEE802154_ATTR_LLSEC_FRAME_COUNTER
- IEEE802154_ATTR_LLSEC_FRAME_TYPE
- IEEE802154_ATTR_LLSEC_KEY_BYTES
- IEEE802154_ATTR_LLSEC_KEY_ID
- IEEE802154_ATTR_LLSEC_KEY_MODE
- IEEE802154_ATTR_LLSEC_KEY_SOURCE_EXTENDED
- IEEE802154_ATTR_LLSEC_KEY_SOURCE_SHORT
- IEEE802154_ATTR_LLSEC_KEY_USAGE_COMMANDS
- IEEE802154_ATTR_LLSEC_KEY_USAGE_FRAME_TYPES
- IEEE802154_ATTR_LLSEC_SECLEVEL
- IEEE802154_ATTR_LLSEC_SECLEVELS
- IEEE802154_ATTR_MAX
- IEEE802154_ATTR_PAD
- IEEE802154_ATTR_PAGE
- IEEE802154_ATTR_PAN_COORD
- IEEE802154_ATTR_PAN_ID
- IEEE802154_ATTR_PHY_NAME
- IEEE802154_ATTR_REASON
- IEEE802154_ATTR_SCAN_TYPE
- IEEE802154_ATTR_SEC
- IEEE802154_ATTR_SF_ORD
- IEEE802154_ATTR_SHORT_ADDR
- IEEE802154_ATTR_SRC_HW_ADDR
- IEEE802154_ATTR_SRC_PAN_ID
- IEEE802154_ATTR_SRC_SHORT_ADDR
- IEEE802154_ATTR_STATUS
- IEEE802154_ATTR_TXPOWER
- IEEE802154_BEACON_LOSS
- IEEE802154_BEACON_MCGRP
- IEEE802154_BEACON_NOTIFY_INDIC
- IEEE802154_CHNL_ACCESS_FAIL
- IEEE802154_CMD_ASSOCIATION_REQ
- IEEE802154_CMD_ASSOCIATION_RESP
- IEEE802154_CMD_BEACON_REQ
- IEEE802154_CMD_COORD_REALIGN_NOTIFY
- IEEE802154_CMD_DATA_REQ
- IEEE802154_CMD_DISASSOCIATION_NOTIFY
- IEEE802154_CMD_GTS_REQ
- IEEE802154_CMD_MAX
- IEEE802154_CMD_ORPHAN_NOTIFY
- IEEE802154_CMD_PANID_CONFLICT_NOTIFY
- IEEE802154_COMM_STATUS_INDIC
- IEEE802154_COORD_MCGRP
- IEEE802154_DEL_IFACE
- IEEE802154_DENINED
- IEEE802154_DEV_MONITOR
- IEEE802154_DEV_TO_SUB_IF
- IEEE802154_DEV_WPAN
- IEEE802154_DISABLE_TRX_FAIL
- IEEE802154_DISASSOCIATE_CONF
- IEEE802154_DISASSOCIATE_INDIC
- IEEE802154_DISASSOCIATE_REQ
- IEEE802154_DUMP
- IEEE802154_EXTENDED_ADDR_LEN
- IEEE802154_FAILED_SECURITY_CHECK
- IEEE802154_FCS_LEN
- IEEE802154_FCTL_ACKREQ
- IEEE802154_FCTL_ADDR_NONE
- IEEE802154_FCTL_DADDR
- IEEE802154_FCTL_DADDR_EXTENDED
- IEEE802154_FCTL_DADDR_SHORT
- IEEE802154_FCTL_FTYPE
- IEEE802154_FCTL_INTRA_PAN
- IEEE802154_FCTL_SADDR
- IEEE802154_FCTL_SADDR_EXTENDED
- IEEE802154_FCTL_SADDR_SHORT
- IEEE802154_FCTL_SECEN
- IEEE802154_FC_ACK_REQ
- IEEE802154_FC_ACK_REQ_SHIFT
- IEEE802154_FC_DAMODE
- IEEE802154_FC_DAMODE_MASK
- IEEE802154_FC_DAMODE_SHIFT
- IEEE802154_FC_FRPEND
- IEEE802154_FC_FRPEND_SHIFT
- IEEE802154_FC_INTRA_PAN
- IEEE802154_FC_INTRA_PAN_SHIFT
- IEEE802154_FC_LEN
- IEEE802154_FC_SAMODE
- IEEE802154_FC_SAMODE_MASK
- IEEE802154_FC_SAMODE_SHIFT
- IEEE802154_FC_SECEN
- IEEE802154_FC_SECEN_SHIFT
- IEEE802154_FC_SET_TYPE
- IEEE802154_FC_TYPE
- IEEE802154_FC_TYPE_ACK
- IEEE802154_FC_TYPE_BEACON
- IEEE802154_FC_TYPE_DATA
- IEEE802154_FC_TYPE_MAC_CMD
- IEEE802154_FC_TYPE_MASK
- IEEE802154_FC_TYPE_SHIFT
- IEEE802154_FC_VERSION
- IEEE802154_FC_VERSION_MASK
- IEEE802154_FC_VERSION_SHIFT
- IEEE802154_FRAME_TOO_LONG
- IEEE802154_FTYPE_DATA
- IEEE802154_GET_CONF
- IEEE802154_GET_REQ
- IEEE802154_GTS_CONF
- IEEE802154_GTS_INDIC
- IEEE802154_GTS_REQ
- IEEE802154_HW_AFILT
- IEEE802154_HW_CSMA_PARAMS
- IEEE802154_HW_FRAME_RETRIES
- IEEE802154_HW_LBT
- IEEE802154_HW_OMIT_CKSUM
- IEEE802154_HW_PROMISCUOUS
- IEEE802154_HW_RX_DROP_BAD_CKSUM
- IEEE802154_HW_RX_OMIT_CKSUM
- IEEE802154_HW_TX_OMIT_CKSUM
- IEEE802154_INVALID_GTS
- IEEE802154_INVALID_HANDLE
- IEEE802154_INVALID_PARAMETER
- IEEE802154_LIFS_PERIOD
- IEEE802154_LIST_IFACE
- IEEE802154_LIST_PHY
- IEEE802154_LLSEC_ADD_DEV
- IEEE802154_LLSEC_ADD_DEVKEY
- IEEE802154_LLSEC_ADD_KEY
- IEEE802154_LLSEC_ADD_SECLEVEL
- IEEE802154_LLSEC_DEL_DEV
- IEEE802154_LLSEC_DEL_DEVKEY
- IEEE802154_LLSEC_DEL_KEY
- IEEE802154_LLSEC_DEL_SECLEVEL
- IEEE802154_LLSEC_DEVKEY_IGNORE
- IEEE802154_LLSEC_DEVKEY_RECORD
- IEEE802154_LLSEC_DEVKEY_RESTRICT
- IEEE802154_LLSEC_GETPARAMS
- IEEE802154_LLSEC_KEY_SIZE
- IEEE802154_LLSEC_LIST_DEV
- IEEE802154_LLSEC_LIST_DEVKEY
- IEEE802154_LLSEC_LIST_KEY
- IEEE802154_LLSEC_LIST_SECLEVEL
- IEEE802154_LLSEC_PARAM_COORD_HWADDR
- IEEE802154_LLSEC_PARAM_COORD_SHORTADDR
- IEEE802154_LLSEC_PARAM_ENABLED
- IEEE802154_LLSEC_PARAM_FRAME_COUNTER
- IEEE802154_LLSEC_PARAM_HWADDR
- IEEE802154_LLSEC_PARAM_KEY_SOURCE
- IEEE802154_LLSEC_PARAM_OUT_KEY
- IEEE802154_LLSEC_PARAM_OUT_LEVEL
- IEEE802154_LLSEC_PARAM_PAN_ID
- IEEE802154_LLSEC_SETPARAMS
- IEEE802154_MAC_SCAN_ACTIVE
- IEEE802154_MAC_SCAN_ED
- IEEE802154_MAC_SCAN_ORPHAN
- IEEE802154_MAC_SCAN_PASSIVE
- IEEE802154_MAX_AUTH_TAG_LEN
- IEEE802154_MAX_CHANNEL
- IEEE802154_MAX_HEADER_LEN
- IEEE802154_MAX_PAGE
- IEEE802154_MAX_SIFS_FRAME_SIZE
- IEEE802154_MCAST_BEACON_NAME
- IEEE802154_MCAST_COORD_NAME
- IEEE802154_MFR_SIZE
- IEEE802154_MIN_HEADER_LEN
- IEEE802154_MIN_PSDU_LEN
- IEEE802154_MTU
- IEEE802154_NETDEVICE_H
- IEEE802154_NL_NAME
- IEEE802154_NO_ACK
- IEEE802154_NO_BEACON
- IEEE802154_NO_DATA
- IEEE802154_NO_SHORT_ADDRESS
- IEEE802154_OP
- IEEE802154_ORPHAN_INDIC
- IEEE802154_ORPHAN_RESP
- IEEE802154_OUT_OF_CAP
- IEEE802154_PANID_BROADCAST
- IEEE802154_PANID_CONFLICT
- IEEE802154_PAN_ID_BROADCAST
- IEEE802154_PAN_ID_LEN
- IEEE802154_POLL_CONF
- IEEE802154_POLL_REQ
- IEEE802154_REALIGMENT
- IEEE802154_RESET_CONF
- IEEE802154_RESET_REQ
- IEEE802154_RX_ENABLE_CONF
- IEEE802154_RX_ENABLE_REQ
- IEEE802154_RX_MSG
- IEEE802154_SCAN_CONF
- IEEE802154_SCAN_IN_PROGRESS
- IEEE802154_SCAN_REQ
- IEEE802154_SCF_KEY_HW_INDEX
- IEEE802154_SCF_KEY_ID_MODE
- IEEE802154_SCF_KEY_ID_MODE_MASK
- IEEE802154_SCF_KEY_ID_MODE_SHIFT
- IEEE802154_SCF_KEY_IMPLICIT
- IEEE802154_SCF_KEY_INDEX
- IEEE802154_SCF_KEY_SHORT_INDEX
- IEEE802154_SCF_SECLEVEL
- IEEE802154_SCF_SECLEVEL_ENC
- IEEE802154_SCF_SECLEVEL_ENC_MIC128
- IEEE802154_SCF_SECLEVEL_ENC_MIC32
- IEEE802154_SCF_SECLEVEL_ENC_MIC64
- IEEE802154_SCF_SECLEVEL_MASK
- IEEE802154_SCF_SECLEVEL_MIC128
- IEEE802154_SCF_SECLEVEL_MIC32
- IEEE802154_SCF_SECLEVEL_MIC64
- IEEE802154_SCF_SECLEVEL_NONE
- IEEE802154_SCF_SECLEVEL_SHIFT
- IEEE802154_SEQ_LEN
- IEEE802154_SET_CONF
- IEEE802154_SET_MACPARAMS
- IEEE802154_SET_REQ
- IEEE802154_SHORT_ADDR_LEN
- IEEE802154_SIFS_PERIOD
- IEEE802154_START_CONF
- IEEE802154_START_REQ
- IEEE802154_SUCCESS
- IEEE802154_SYNC_LOSS_INDIC
- IEEE802154_SYNC_REQ
- IEEE802154_TRANSACTION_EXPIRED
- IEEE802154_TRANSACTION_OVERFLOW
- IEEE802154_TX_ACTIVE
- IEEE802154_UNAVAILABLE_KEY
- IEEE802154_UNSUPPORTED_ATTR
- IEEE802154_WPAN_DEV_TO_SUB_IF
- IEEE8023_FRAMETAG
- IEEE802_1X_TYPE_EAPOL_ENCAPSULATED_ASF_ALERT
- IEEE802_1X_TYPE_EAPOL_KEY
- IEEE802_1X_TYPE_EAPOL_LOGOFF
- IEEE802_1X_TYPE_EAPOL_START
- IEEE802_1X_TYPE_EAP_PACKET
- IEEE802_3_SZ
- IEEE_802154_LOCAL_H
- IEEE_8021QAZ_APP_SEL_ANY
- IEEE_8021QAZ_APP_SEL_DGRAM
- IEEE_8021QAZ_APP_SEL_DSCP
- IEEE_8021QAZ_APP_SEL_ETHERTYPE
- IEEE_8021QAZ_APP_SEL_STREAM
- IEEE_8021QAZ_MAX_TCS
- IEEE_8021QAZ_TSA_CB_SHAPER
- IEEE_8021QAZ_TSA_ETS
- IEEE_8021QAZ_TSA_STRICT
- IEEE_8021QAZ_TSA_VENDOR
- IEEE_8021Q_INFO
- IEEE_8021Q_MAX_PRIORITIES
- IEEE_A
- IEEE_B
- IEEE_CMD_MLME
- IEEE_CMD_SET_ENCRYPTION
- IEEE_CMD_SET_WPA_IE
- IEEE_CMD_SET_WPA_PARAM
- IEEE_CRYPT_ALG_NAME_LEN
- IEEE_CRYPT_ERR_CARD_CONF_FAILED
- IEEE_CRYPT_ERR_CRYPT_INIT_FAILED
- IEEE_CRYPT_ERR_KEY_SET_FAILED
- IEEE_CRYPT_ERR_TX_KEY_SET_FAILED
- IEEE_CRYPT_ERR_UNKNOWN_ADDR
- IEEE_CRYPT_ERR_UNKNOWN_ALG
- IEEE_CURRENT_RM_MASK
- IEEE_CURRENT_RM_SHIFT
- IEEE_ESR_1000T_FD_CAPS
- IEEE_ESR_1000T_HD_CAPS
- IEEE_ESR_1000X_FD_CAPS
- IEEE_ESR_1000X_HD_CAPS
- IEEE_FAUX_SYNC
- IEEE_G
- IEEE_IBSS_MAC_HASH_SIZE
- IEEE_INHERIT
- IEEE_KEY_MGMT_IEEE8021X
- IEEE_KEY_MGMT_PSK
- IEEE_MAP_DMZ
- IEEE_MAP_MASK
- IEEE_MAP_UMZ
- IEEE_MAX_IE_SIZE
- IEEE_MLME_STA_DEAUTH
- IEEE_MLME_STA_DISASSOC
- IEEE_MODE_MASK
- IEEE_N_24G
- IEEE_N_5G
- IEEE_PACKET_RETRY_TIME
- IEEE_PARAM_AUTH_ALGS
- IEEE_PARAM_DROP_UNENCRYPTED
- IEEE_PARAM_IEEE_802_1X
- IEEE_PARAM_PRIVACY_INVOKED
- IEEE_PARAM_TKIP_COUNTERMEASURES
- IEEE_PARAM_WPAX_SELECT
- IEEE_PARAM_WPA_ENABLED
- IEEE_PROTO_RSN
- IEEE_PROTO_WPA
- IEEE_R_ALIGN
- IEEE_R_CRC
- IEEE_R_DROP
- IEEE_R_FDXFC
- IEEE_R_FRAME_OK
- IEEE_R_MACERR
- IEEE_R_OCTETS_OK
- IEEE_SGE_FLAGS_ADDR_MASK
- IEEE_SGE_FLAGS_CHAIN_ELEMENT
- IEEE_SGE_FLAGS_END_OF_LIST
- IEEE_SGE_FLAGS_FORMAT_IEEE
- IEEE_SGE_FLAGS_FORMAT_MASK
- IEEE_SGE_FLAGS_FORMAT_NVME
- IEEE_SGE_FLAGS_IOCDDR_ADDR
- IEEE_SGE_FLAGS_IOCPLBNTA_ADDR
- IEEE_SGE_FLAGS_IOCPLB_ADDR
- IEEE_SGE_FLAGS_SYSTEM_ADDR
- IEEE_SOFTMAC_ASSOCIATE
- IEEE_SOFTMAC_BEACONS
- IEEE_SOFTMAC_PROBERQ
- IEEE_SOFTMAC_PROBERS
- IEEE_SOFTMAC_SCAN
- IEEE_SOFTMAC_SINGLE_QUEUE
- IEEE_SOFTMAC_TX_QUEUE
- IEEE_STATUS_DNO
- IEEE_STATUS_DZE
- IEEE_STATUS_INE
- IEEE_STATUS_INV
- IEEE_STATUS_MASK
- IEEE_STATUS_OVF
- IEEE_STATUS_TO_EXCSUM_SHIFT
- IEEE_STATUS_UNF
- IEEE_SW_MASK
- IEEE_TRAP_ENABLE_DNO
- IEEE_TRAP_ENABLE_DZE
- IEEE_TRAP_ENABLE_INE
- IEEE_TRAP_ENABLE_INV
- IEEE_TRAP_ENABLE_MASK
- IEEE_TRAP_ENABLE_OVF
- IEEE_TRAP_ENABLE_UNF
- IEEE_T_1COL
- IEEE_T_CSERR
- IEEE_T_DEF
- IEEE_T_DROP
- IEEE_T_EXCOL
- IEEE_T_FDXFC
- IEEE_T_FRAME_OK
- IEEE_T_LCOL
- IEEE_T_MACERR
- IEEE_T_MCOL
- IEEE_T_OCTETS_OK
- IEEE_T_SQE
- IEEE_WPAX_CCMP
- IEEE_WPAX_TKIP
- IEEE_WPAX_USEGROUP
- IEEE_WPAX_WEP104
- IEEE_WPAX_WEP40
- IEEE_WPAX_WRAP
- IEFT_MPA_KEY_REP
- IEFT_MPA_KEY_REQ
- IEMSK
- IEOB_ATTEN
- IEOB_BUSERR
- IEOB_ENABLE
- IEOB_IENAB
- IEOB_INT
- IEOB_NORSET
- IEOB_ONAIR
- IEOB_XCVRL2
- IEOB_XXXXX
- IEOC
- IEOC_ENABLE
- IEOS_ENABLE
- IEQ_CREATED
- IER
- IER0
- IER0_OFFSET
- IER1
- IER2
- IERXD_MARK
- IERX_A_MARK
- IERX_B_MARK
- IERX_C_MARK
- IERX_MARK
- IER_CLR
- IER_CLR_BIT
- IER_CMD_DONE
- IER_CTS
- IER_DMAE
- IER_ECC_ERR
- IER_ELSI
- IER_EMSC
- IER_EMSI
- IER_ENABLE_ALL
- IER_ERDAI
- IER_ERLS
- IER_ERR_TRIG_VAL
- IER_ERXRDY
- IER_ETHREI
- IER_ETXRDY
- IER_FCIE
- IER_FIFO_INT_EN_MASK
- IER_FUIE
- IER_GIE
- IER_I2C_INT_EN_MASK
- IER_LIE
- IER_LINK_DOWN
- IER_LINK_UP
- IER_LSR
- IER_MASK
- IER_MDM
- IER_MIE
- IER_MSR
- IER_NOACK_EN_MASK
- IER_NRZE
- IER_OFFSET
- IER_OVR
- IER_RAVIE
- IER_RDIE
- IER_RDMAE
- IER_RDREQE
- IER_READ_COMPLETE_INT_MASK
- IER_REOFE
- IER_RFFULE
- IER_RFOVFE
- IER_RFSERRE
- IER_RFUDFE
- IER_RLSE
- IER_RRIE
- IER_RTIOE
- IER_RTS
- IER_RX
- IER_RXENABLED
- IER_RXS
- IER_SET
- IER_SET_BIT
- IER_SLEEP
- IER_TCIE
- IER_TDIE
- IER_TDMAE
- IER_TDREQE
- IER_TEOFE
- IER_TERRIE
- IER_TFEMPE
- IER_TFOVFE
- IER_TFSERRE
- IER_TFUDFE
- IER_TIE
- IER_TX
- IER_TXENABLED
- IER_UND
- IER_UUE
- IER_XOFF
- IESPI_FRM_ERR
- IESPI_PAR_ERROR_F
- IESPI_PAR_ERROR_S
- IESPI_PAR_ERROR_V
- IETF_FLPDU_ZERO_LEN
- IETF_MAX_PRIV_DATA_LEN
- IETF_MPA_FLAGS_CRC
- IETF_MPA_FLAGS_MARKERS
- IETF_MPA_FLAGS_REJECT
- IETF_MPA_FRAME_SIZE
- IETF_MPA_KEY_SIZE
- IETF_MPA_V1
- IETF_MPA_V2
- IETF_MPA_V2_FLAG
- IETF_MPA_VERSION
- IETF_NO_IRD_ORD
- IETF_PEER_TO_PEER
- IETF_RDMA0_READ
- IETF_RDMA0_WRITE
- IETF_RTR_MSG_SIZE
- IETH_PRN
- IETXD_MARK
- IETX_A_MARK
- IETX_B_MARK
- IETX_C_MARK
- IETX_MARK
- IEVENT_BABR
- IEVENT_BABT
- IEVENT_BSY
- IEVENT_CRL
- IEVENT_DPE
- IEVENT_EBERR
- IEVENT_ERR_MASK
- IEVENT_FGPI
- IEVENT_FIQ
- IEVENT_FIR
- IEVENT_GRSC
- IEVENT_GTSC
- IEVENT_INIT_CLEAR
- IEVENT_LC
- IEVENT_MAG
- IEVENT_MSRO
- IEVENT_PERR
- IEVENT_RTX_MASK
- IEVENT_RXB0
- IEVENT_RXC
- IEVENT_RXF0
- IEVENT_RX_MASK
- IEVENT_TXB
- IEVENT_TXC
- IEVENT_TXE
- IEVENT_TXF
- IEVENT_TX_MASK
- IEVENT_XFUN
- IEXTEN
- IE_ALL
- IE_CISCO_FLAG_POSITION
- IE_EEOB
- IE_EOB
- IE_FEC
- IE_IRQ
- IE_IRQ0
- IE_IRQ1
- IE_IRQ2
- IE_IRQ3
- IE_IRQ4
- IE_IRQ5
- IE_MASK
- IE_MAX_LEN
- IE_M_ALL_INTERRUPT_MASK
- IE_M_ALL_INTERRUPT_SHIFT
- IE_M_RX_FIFO_FULL_SHIFT
- IE_M_RX_THLD_SHIFT
- IE_M_START_BUSY_SHIFT
- IE_M_TX_UNDERRUN_SHIFT
- IE_OBIO
- IE_OFFSET
- IE_ON_CMD_COMPLETE
- IE_ON_FATAL_ERR
- IE_ON_PHYRDY_CHG
- IE_ON_SIGNATURE_UPDATE
- IE_ON_SINGL_DEVICE_ERR
- IE_ON_SNOTIFY_UPDATE
- IE_OR
- IE_ORIE
- IE_PATTERN_DETECTION
- IE_QPSK_H
- IE_QPSK_L
- IE_QPSK_M
- IE_RX
- IE_RXIE
- IE_RXTIE
- IE_RXTO
- IE_RXTOFE
- IE_RXTOIE
- IE_SHIFT
- IE_SW0
- IE_SW1
- IE_S_ALL_INTERRUPT_MASK
- IE_S_ALL_INTERRUPT_SHIFT
- IE_S_RD_EVENT_SHIFT
- IE_S_RX_EVENT_SHIFT
- IE_S_RX_FIFO_FULL_SHIFT
- IE_S_RX_THLD_SHIFT
- IE_S_START_BUSY_SHIFT
- IE_S_TX_UNDERRUN_SHIFT
- IE_TX
- IE_TXC
- IE_TXCIE
- IE_TXIE
- IE_UR
- IE_URIE
- IF
- IF2
- IF2DT
- IFACE
- IFACEQ_CMD_IDX
- IFACEQ_DBG_IDX
- IFACEQ_DFLT_QHDR
- IFACEQ_GET_QHDR_START_ADDR
- IFACEQ_MAX_BUF_COUNT
- IFACEQ_MAX_PARALLEL_CLNTS
- IFACEQ_MAX_PKT_SIZE
- IFACEQ_MED_PKT_SIZE
- IFACEQ_MIN_PKT_SIZE
- IFACEQ_MSG_IDX
- IFACEQ_NUM
- IFACEQ_QUEUE_SIZE
- IFACEQ_TABLE_SIZE
- IFACEQ_VAR_HUGE_PKT_SIZE
- IFACEQ_VAR_LARGE_PKT_SIZE
- IFACEQ_VAR_SMALL_PKT_SIZE
- IFACE_AUDIO_DATA_LEN
- IFACE_BCLK_INVERT
- IFACE_DAC_LR_POLARITY
- IFACE_DAC_LR_SWAP
- IFACE_ENABLE_MASTER
- IFACE_FUNC_CTRL_OFFSET
- IFACE_GENERIC_INT_TYPE_OFFSET
- IFACE_IFACE_FORMAT
- IFACE_INT_MASK_OFFSET
- IFACE_INT_STATUS_OFFSET
- IFACE_LOCKOUT_HOST_OFFSET
- IFACE_LOCKOUT_MAC_OFFSET
- IFACE_MAC_STAT_OFFSET
- IFACE_NAME_TEMPLATE
- IFACE_ON_COMMAND
- IFACE_PORT0
- IFACE_PORT1
- IFADC_CTRL
- IFALIASZ
- IFAL_ADDRESS
- IFAL_LABEL
- IFAL_MAX
- IFAR
- IFATN
- IFATN_ATTENUATION
- IFATN_ATTENUATION_MASK
- IFATN_FILTERCUTOFF
- IFATN_FILTERCUTOFF_MASK
- IFA_ADDRESS
- IFA_ANYCAST
- IFA_BROADCAST
- IFA_CACHEINFO
- IFA_FLAGS
- IFA_F_DADFAILED
- IFA_F_DEPRECATED
- IFA_F_HOMEADDRESS
- IFA_F_MANAGETEMPADDR
- IFA_F_MCAUTOJOIN
- IFA_F_NODAD
- IFA_F_NOPREFIXROUTE
- IFA_F_OPTIMISTIC
- IFA_F_PERMANENT
- IFA_F_SECONDARY
- IFA_F_STABLE_PRIVACY
- IFA_F_TEMPORARY
- IFA_F_TENTATIVE
- IFA_HOST
- IFA_LABEL
- IFA_LINK
- IFA_LOCAL
- IFA_MAX
- IFA_MULTICAST
- IFA_PAYLOAD
- IFA_RTA
- IFA_RT_PRIORITY
- IFA_SITE
- IFA_TARGET_NETNSID
- IFA_UNSPEC
- IFBIG
- IFB_FEATURES
- IFCB_VER_MAX
- IFCB_VER_MIN
- IFC_ACT_NEG
- IFC_AMASK
- IFC_AMASK_MASK
- IFC_AMASK_SHIFT
- IFC_CCR_CLK_DIV
- IFC_CCR_CLK_DIV_MASK
- IFC_CCR_CLK_DIV_SHIFT
- IFC_CCR_CLK_DLY
- IFC_CCR_CLK_DLY_MASK
- IFC_CCR_CLK_DLY_SHIFT
- IFC_CCR_FB_IFC_CLK_SEL
- IFC_CCR_INV_CLK_EN
- IFC_CCR_MASK
- IFC_CM_ERATTR0_ERAID
- IFC_CM_ERATTR0_ERAID_SHIFT
- IFC_CM_ERATTR0_ERTYP_READ
- IFC_CM_ERATTR0_ESRCID
- IFC_CM_ERATTR0_ESRCID_SHIFT
- IFC_CM_EVTER_EN_CSEREN
- IFC_CM_EVTER_INTR_EN_CSERIREN
- IFC_CM_EVTER_STAT_CSER
- IFC_CSR_CLK_STAT_STABLE
- IFC_FIR_OP_BTRD
- IFC_FIR_OP_CA0
- IFC_FIR_OP_CA1
- IFC_FIR_OP_CA2
- IFC_FIR_OP_CA3
- IFC_FIR_OP_CMD0
- IFC_FIR_OP_CMD1
- IFC_FIR_OP_CMD2
- IFC_FIR_OP_CMD3
- IFC_FIR_OP_CMD4
- IFC_FIR_OP_CMD5
- IFC_FIR_OP_CMD6
- IFC_FIR_OP_CMD7
- IFC_FIR_OP_CW0
- IFC_FIR_OP_CW1
- IFC_FIR_OP_CW2
- IFC_FIR_OP_CW3
- IFC_FIR_OP_CW4
- IFC_FIR_OP_CW5
- IFC_FIR_OP_CW6
- IFC_FIR_OP_CW7
- IFC_FIR_OP_NOP
- IFC_FIR_OP_NWAIT
- IFC_FIR_OP_RA0
- IFC_FIR_OP_RA1
- IFC_FIR_OP_RA2
- IFC_FIR_OP_RA3
- IFC_FIR_OP_RB
- IFC_FIR_OP_RBCD
- IFC_FIR_OP_RDSTAT
- IFC_FIR_OP_SBRD
- IFC_FIR_OP_UA
- IFC_FIR_OP_WBCD
- IFC_FIR_OP_WFR
- IFC_GCR_MASK
- IFC_GCR_SOFT_RST_ALL
- IFC_GCR_TBCTL_TRN_TIME
- IFC_GCR_TBCTL_TRN_TIME_SHIFT
- IFC_GPCM_EEIER_PERIR_EN
- IFC_GPCM_EEIER_TOERIR_EN
- IFC_GPCM_ERATTR0_ERAID
- IFC_GPCM_ERATTR0_ERCS_CS0
- IFC_GPCM_ERATTR0_ERCS_CS1
- IFC_GPCM_ERATTR0_ERCS_CS2
- IFC_GPCM_ERATTR0_ERCS_CS3
- IFC_GPCM_ERATTR0_ERSRCID
- IFC_GPCM_ERATTR0_ERTYPE_READ
- IFC_GPCM_ERATTR2_PERR_BEAT
- IFC_GPCM_ERATTR2_PERR_BYTE
- IFC_GPCM_ERATTR2_PERR_DATA_PHASE
- IFC_GPCM_EVTER_EN_PER_EN
- IFC_GPCM_EVTER_EN_TOER_EN
- IFC_GPCM_EVTER_STAT_PER
- IFC_GPCM_EVTER_STAT_TOER
- IFC_GPCM_STAT_BSY
- IFC_INIT_DEFAULT
- IFC_INP_FILTER
- IFC_NAND_AUTOBOOT_TRGR_BOOT_LD
- IFC_NAND_AUTOBOOT_TRGR_RCW_LD
- IFC_NAND_BC
- IFC_NAND_COL_CA_MASK
- IFC_NAND_COL_MS
- IFC_NAND_CSEL
- IFC_NAND_CSEL_CS0
- IFC_NAND_CSEL_CS1
- IFC_NAND_CSEL_CS2
- IFC_NAND_CSEL_CS3
- IFC_NAND_CSEL_SHIFT
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK
- IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK
- IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK
- IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK
- IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT
- IFC_NAND_ERATTR0_ERCS_CS0
- IFC_NAND_ERATTR0_ERCS_CS1
- IFC_NAND_ERATTR0_ERCS_CS2
- IFC_NAND_ERATTR0_ERCS_CS3
- IFC_NAND_ERATTR0_ERTTYPE_READ
- IFC_NAND_ERATTR0_MASK
- IFC_NAND_EVTER_EN_ECCER_EN
- IFC_NAND_EVTER_EN_FTOER_EN
- IFC_NAND_EVTER_EN_OPC_EN
- IFC_NAND_EVTER_EN_PGRDCMPL_EN
- IFC_NAND_EVTER_EN_WPER_EN
- IFC_NAND_EVTER_INTR_ECCERIR_EN
- IFC_NAND_EVTER_INTR_FTOERIR_EN
- IFC_NAND_EVTER_INTR_OPCIR_EN
- IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN
- IFC_NAND_EVTER_INTR_WPERIR_EN
- IFC_NAND_EVTER_STAT_BBI_SRCH_SE
- IFC_NAND_EVTER_STAT_BOOT_DN
- IFC_NAND_EVTER_STAT_ECCER
- IFC_NAND_EVTER_STAT_FTOER
- IFC_NAND_EVTER_STAT_OPC
- IFC_NAND_EVTER_STAT_RCW_DN
- IFC_NAND_EVTER_STAT_WPER
- IFC_NAND_FCR0_CMD0
- IFC_NAND_FCR0_CMD0_SHIFT
- IFC_NAND_FCR0_CMD1
- IFC_NAND_FCR0_CMD1_SHIFT
- IFC_NAND_FCR0_CMD2
- IFC_NAND_FCR0_CMD2_SHIFT
- IFC_NAND_FCR0_CMD3
- IFC_NAND_FCR0_CMD3_SHIFT
- IFC_NAND_FCR1_CMD4
- IFC_NAND_FCR1_CMD4_SHIFT
- IFC_NAND_FCR1_CMD5
- IFC_NAND_FCR1_CMD5_SHIFT
- IFC_NAND_FCR1_CMD6
- IFC_NAND_FCR1_CMD6_SHIFT
- IFC_NAND_FCR1_CMD7
- IFC_NAND_FCR1_CMD7_SHIFT
- IFC_NAND_FIR0_OP0
- IFC_NAND_FIR0_OP0_SHIFT
- IFC_NAND_FIR0_OP1
- IFC_NAND_FIR0_OP1_SHIFT
- IFC_NAND_FIR0_OP2
- IFC_NAND_FIR0_OP2_SHIFT
- IFC_NAND_FIR0_OP3
- IFC_NAND_FIR0_OP3_SHIFT
- IFC_NAND_FIR0_OP4
- IFC_NAND_FIR0_OP4_SHIFT
- IFC_NAND_FIR1_OP5
- IFC_NAND_FIR1_OP5_SHIFT
- IFC_NAND_FIR1_OP6
- IFC_NAND_FIR1_OP6_SHIFT
- IFC_NAND_FIR1_OP7
- IFC_NAND_FIR1_OP7_SHIFT
- IFC_NAND_FIR1_OP8
- IFC_NAND_FIR1_OP8_SHIFT
- IFC_NAND_FIR1_OP9
- IFC_NAND_FIR1_OP9_SHIFT
- IFC_NAND_FIR2_OP10
- IFC_NAND_FIR2_OP10_SHIFT
- IFC_NAND_FIR2_OP11
- IFC_NAND_FIR2_OP11_SHIFT
- IFC_NAND_FIR2_OP12
- IFC_NAND_FIR2_OP12_SHIFT
- IFC_NAND_FIR2_OP13
- IFC_NAND_FIR2_OP13_SHIFT
- IFC_NAND_FIR2_OP14
- IFC_NAND_FIR2_OP14_SHIFT
- IFC_NAND_MDR_RDATA0
- IFC_NAND_MDR_RDATA1
- IFC_NAND_NCFGR_ADDR_MODE_RC0
- IFC_NAND_NCFGR_ADDR_MODE_RC1
- IFC_NAND_NCFGR_BOOT
- IFC_NAND_NCFGR_NUM_LOOP
- IFC_NAND_NCFGR_NUM_LOOP_MASK
- IFC_NAND_NCFGR_NUM_LOOP_SHIFT
- IFC_NAND_NCFGR_NUM_WAIT_MASK
- IFC_NAND_NCFGR_NUM_WAIT_SHIFT
- IFC_NAND_NCFGR_SRAM_INIT_EN
- IFC_NAND_NCR_FTOCNT
- IFC_NAND_NCR_FTOCNT_MASK
- IFC_NAND_NCR_FTOCNT_SHIFT
- IFC_NAND_NFSR_RS0
- IFC_NAND_NFSR_RS1
- IFC_NAND_SEQ_STRT_AUTO_CPB
- IFC_NAND_SEQ_STRT_AUTO_ERS
- IFC_NAND_SEQ_STRT_AUTO_PGM
- IFC_NAND_SEQ_STRT_AUTO_RD
- IFC_NAND_SEQ_STRT_AUTO_STAT_RD
- IFC_NAND_SEQ_STRT_FIR_STRT
- IFC_NORCR_MASK
- IFC_NORCR_NUM_PHASE
- IFC_NORCR_NUM_PHASE_MASK
- IFC_NORCR_NUM_PHASE_SHIFT
- IFC_NORCR_STOCNT
- IFC_NORCR_STOCNT_MASK
- IFC_NORCR_STOCNT_SHIFT
- IFC_NOR_ERATTR0_ERAID
- IFC_NOR_ERATTR0_ERCS_CS0
- IFC_NOR_ERATTR0_ERCS_CS1
- IFC_NOR_ERATTR0_ERCS_CS2
- IFC_NOR_ERATTR0_ERCS_CS3
- IFC_NOR_ERATTR0_ERSRCID
- IFC_NOR_ERATTR0_ERTYPE_READ
- IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP
- IFC_NOR_ERATTR2_ER_NUM_PHASE_PER
- IFC_NOR_EVTER_EN_OPCEN_NOR
- IFC_NOR_EVTER_EN_STOEREN
- IFC_NOR_EVTER_EN_WPEREN
- IFC_NOR_EVTER_INTR_OPCEN_NOR
- IFC_NOR_EVTER_INTR_STOEREN
- IFC_NOR_EVTER_INTR_WPEREN
- IFC_NOR_EVTER_STAT_OPC_NOR
- IFC_NOR_EVTER_STAT_STOER
- IFC_NOR_EVTER_STAT_WPER
- IFC_RB_STAT_READY_CS0
- IFC_RB_STAT_READY_CS1
- IFC_RB_STAT_READY_CS2
- IFC_RB_STAT_READY_CS3
- IFC_RD_NO_EEPROM
- IFC_REG_LOCK
- IFC_REG_UNLOCK
- IFC_SLEW_RATE
- IFC_TIMEOUT_MSECS
- IFC_WR_EN_FILTER
- IFDEF_ZONE_DMA
- IFDEF_ZONE_DMA32
- IFDEF_ZONE_HIGHMEM
- IFEI
- IFEM_EXT_CCUT
- IFER
- IFETCH_ALIGN_BYTES
- IFETCH_ALIGN_SHIFT
- IFE_0_GDSC
- IFE_1_GDSC
- IFE_C_E_PHY_ID
- IFE_DECODE
- IFE_ENCODE
- IFE_E_PHY_ID
- IFE_METAHDRLEN
- IFE_META_HASHID
- IFE_META_MAX
- IFE_META_PRIO
- IFE_META_QMAP
- IFE_META_SKBMARK
- IFE_META_TCINDEX
- IFE_PESC_100BTX_POWER_DOWN
- IFE_PESC_10BTX_POWER_DOWN
- IFE_PESC_DUPLEX
- IFE_PESC_PHY_ADDR_MASK
- IFE_PESC_POLARITY_REVERSED
- IFE_PESC_POLARITY_REVERSED_SHIFT
- IFE_PESC_REDUCED_POWER_DOWN_DISABLE
- IFE_PESC_SPEED
- IFE_PHC_ABILITY_CHECK
- IFE_PHC_DISTANCE_MASK
- IFE_PHC_HIGHZ
- IFE_PHC_HWI_ENABLE
- IFE_PHC_LOWZ
- IFE_PHC_LOW_HIGH_Z_MASK
- IFE_PHC_MDIX_RESET_ALL_MASK
- IFE_PHC_RESET_ALL_MASK
- IFE_PHC_TEST_EXEC
- IFE_PHY_EQUALIZER
- IFE_PHY_EXTENDED_STATUS_CONTROL
- IFE_PHY_HWI_CONTROL
- IFE_PHY_MDIX_CONTROL
- IFE_PHY_PREM_EOF_ERR
- IFE_PHY_RCV_DISCONNECT
- IFE_PHY_RCV_EOF_ERR
- IFE_PHY_RCV_ERROT_FRAME
- IFE_PHY_RCV_FALSE_CARRIER
- IFE_PHY_RCV_SYMBOL_ERR
- IFE_PHY_SPECIAL_CONTROL
- IFE_PHY_SPECIAL_CONTROL_LED
- IFE_PHY_TX_JABBER_DETECT
- IFE_PLUS_E_PHY_ID
- IFE_PMC_AUTO_MDIX
- IFE_PMC_AUTO_MDIX_COMPLETE
- IFE_PMC_FORCE_MDIX
- IFE_PMC_MDIX_MODE_SHIFT
- IFE_PMC_MDIX_STATUS
- IFE_PSCL_PROBE_LEDS_OFF
- IFE_PSCL_PROBE_LEDS_ON
- IFE_PSCL_PROBE_MODE
- IFE_PSC_AUTO_POLARITY_DISABLE
- IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT
- IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN
- IFE_PSC_FORCE_POLARITY
- IFE_PSC_FORCE_POLARITY_SHIFT
- IFE_PSC_JABBER_FUNC_DISABLE
- IFFALSE
- IFFILTER_DISCRETE
- IFFILTER_SAW
- IFF_802_1Q_VLAN
- IFF_ALLMULTI
- IFF_ATTACH_QUEUE
- IFF_AUTOMEDIA
- IFF_BONDING
- IFF_BRIDGE_PORT
- IFF_BROADCAST
- IFF_DEBUG
- IFF_DETACH_QUEUE
- IFF_DISABLE_NETPOLL
- IFF_DONT_BRIDGE
- IFF_DORMANT
- IFF_DYNAMIC
- IFF_EBRIDGE
- IFF_ECHO
- IFF_FAILOVER
- IFF_FAILOVER_SLAVE
- IFF_ISATAP
- IFF_L3MDEV_MASTER
- IFF_L3MDEV_RX_HANDLER
- IFF_L3MDEV_SLAVE
- IFF_LIVE_ADDR_CHANGE
- IFF_LIVE_RENAME_OK
- IFF_LOOPBACK
- IFF_LOWER_UP
- IFF_MACSEC
- IFF_MACVLAN
- IFF_MACVLAN_PORT
- IFF_MASTER
- IFF_MULTICAST
- IFF_MULTI_QUEUE
- IFF_NAPI
- IFF_NAPI_FRAGS
- IFF_NOARP
- IFF_NOFILTER
- IFF_NOTRAILERS
- IFF_NO_PI
- IFF_NO_QUEUE
- IFF_NO_RX_HANDLER
- IFF_ONE_QUEUE
- IFF_OPENVSWITCH
- IFF_OVS_DATAPATH
- IFF_PERSIST
- IFF_PHONY_HEADROOM
- IFF_POINTOPOINT
- IFF_PORTSEL
- IFF_PROMISC
- IFF_RUNNING
- IFF_RXFH_CONFIGURED
- IFF_SLAVE
- IFF_SUPP_NOFCS
- IFF_TAP
- IFF_TEAM
- IFF_TEAM_PORT
- IFF_TUN
- IFF_TUN_EXCL
- IFF_TX_SKB_SHARING
- IFF_UNICAST_FLT
- IFF_UP
- IFF_VNET_HDR
- IFF_VOLATILE
- IFF_WAN_HDLC
- IFF_XMIT_DST_RELEASE
- IFF_XMIT_DST_RELEASE_PERM
- IFG
- IFHWADDRLEN
- IFH_EXTRACT_BITFIELD64
- IFH_INJ_BYPASS
- IFH_INJ_POP_CNT_DISABLE
- IFH_LEN
- IFH_REW_OP_DSCP
- IFH_REW_OP_NOOP
- IFH_REW_OP_ONE_STEP_PTP
- IFH_REW_OP_ORIGIN_PTP
- IFH_REW_OP_TWO_STEP_PTP
- IFH_TAG_TYPE_C
- IFH_TAG_TYPE_S
- IFIRST
- IFIS
- IFI_CANFD_CANCLOCK
- IFI_CANFD_ERRCNT
- IFI_CANFD_ERROR
- IFI_CANFD_ERROR_CTR
- IFI_CANFD_ERROR_CTR_ACK_ERROR_ALL
- IFI_CANFD_ERROR_CTR_ACK_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_BIT0_ERROR_ALL
- IFI_CANFD_ERROR_CTR_BIT0_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_BIT1_ERROR_ALL
- IFI_CANFD_ERROR_CTR_BIT1_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_BITPOSITION_MASK
- IFI_CANFD_ERROR_CTR_BITPOSITION_OFFSET
- IFI_CANFD_ERROR_CTR_CRC_ERROR_ALL
- IFI_CANFD_ERROR_CTR_CRC_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_ER_ENABLE
- IFI_CANFD_ERROR_CTR_ER_RESET
- IFI_CANFD_ERROR_CTR_FORM_ERROR_ALL
- IFI_CANFD_ERROR_CTR_FORM_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_OVERLOAD_ALL
- IFI_CANFD_ERROR_CTR_OVERLOAD_FIRST
- IFI_CANFD_ERROR_CTR_STUFF_ERROR_ALL
- IFI_CANFD_ERROR_CTR_STUFF_ERROR_FIRST
- IFI_CANFD_ERROR_CTR_UNLOCK_MAGIC
- IFI_CANFD_ERROR_RX_MASK
- IFI_CANFD_ERROR_RX_OFFSET
- IFI_CANFD_ERROR_TX_MASK
- IFI_CANFD_ERROR_TX_OFFSET
- IFI_CANFD_FILTER_IDENT
- IFI_CANFD_FILTER_IDENT_CANFD
- IFI_CANFD_FILTER_IDENT_IDE
- IFI_CANFD_FILTER_IDENT_VALID
- IFI_CANFD_FILTER_MASK
- IFI_CANFD_FILTER_MASK_EDL
- IFI_CANFD_FILTER_MASK_EXT
- IFI_CANFD_FILTER_MASK_VALID
- IFI_CANFD_FTIME
- IFI_CANFD_INTERRUPT
- IFI_CANFD_INTERRUPT_ERROR_BUSOFF
- IFI_CANFD_INTERRUPT_ERROR_COUNTER
- IFI_CANFD_INTERRUPT_ERROR_REC_TEC_INC
- IFI_CANFD_INTERRUPT_ERROR_STATE_CHG
- IFI_CANFD_INTERRUPT_ERROR_WARNING
- IFI_CANFD_INTERRUPT_RXFIFO_NEMPTY
- IFI_CANFD_INTERRUPT_RXFIFO_NEMPTY_PER
- IFI_CANFD_INTERRUPT_SET_IRQ
- IFI_CANFD_INTERRUPT_TXFIFO_EMPTY
- IFI_CANFD_INTERRUPT_TXFIFO_REMOVE
- IFI_CANFD_IP_ID
- IFI_CANFD_IP_ID_VALUE
- IFI_CANFD_IRQMASK
- IFI_CANFD_IRQMASK_ERROR_BUSOFF
- IFI_CANFD_IRQMASK_ERROR_REC_TEC_INC
- IFI_CANFD_IRQMASK_ERROR_STATE_CHG
- IFI_CANFD_IRQMASK_ERROR_WARNING
- IFI_CANFD_IRQMASK_RXFIFO_NEMPTY
- IFI_CANFD_IRQMASK_SET_ERR
- IFI_CANFD_IRQMASK_SET_RX
- IFI_CANFD_IRQMASK_SET_TS
- IFI_CANFD_IRQMASK_SET_TX
- IFI_CANFD_IRQMASK_TXFIFO_EMPTY
- IFI_CANFD_PAR
- IFI_CANFD_REPEAT
- IFI_CANFD_RES1
- IFI_CANFD_RXFIFO_DATA
- IFI_CANFD_RXFIFO_DLC
- IFI_CANFD_RXFIFO_DLC_BRS
- IFI_CANFD_RXFIFO_DLC_DLC_MASK
- IFI_CANFD_RXFIFO_DLC_DLC_OFFSET
- IFI_CANFD_RXFIFO_DLC_EDL
- IFI_CANFD_RXFIFO_DLC_ESI
- IFI_CANFD_RXFIFO_DLC_FNR_MASK
- IFI_CANFD_RXFIFO_DLC_FNR_OFFSET
- IFI_CANFD_RXFIFO_DLC_OBJ_MASK
- IFI_CANFD_RXFIFO_DLC_OBJ_OFFSET
- IFI_CANFD_RXFIFO_DLC_RTR
- IFI_CANFD_RXFIFO_ID
- IFI_CANFD_RXFIFO_ID_IDE
- IFI_CANFD_RXFIFO_ID_ID_OFFSET
- IFI_CANFD_RXFIFO_ID_ID_STD_MASK
- IFI_CANFD_RXFIFO_ID_ID_STD_OFFSET
- IFI_CANFD_RXFIFO_ID_ID_STD_WIDTH
- IFI_CANFD_RXFIFO_ID_ID_XTD_MASK
- IFI_CANFD_RXFIFO_ID_ID_XTD_OFFSET
- IFI_CANFD_RXFIFO_ID_ID_XTD_WIDTH
- IFI_CANFD_RXFIFO_TS_31_0
- IFI_CANFD_RXFIFO_TS_63_32
- IFI_CANFD_RXSTCMD
- IFI_CANFD_RXSTCMD_EMPTY
- IFI_CANFD_RXSTCMD_OVERFLOW
- IFI_CANFD_RXSTCMD_REMOVE_MSG
- IFI_CANFD_RXSTCMD_RESET
- IFI_CANFD_STCMD
- IFI_CANFD_STCMD_BUSMONITOR
- IFI_CANFD_STCMD_BUSOFF
- IFI_CANFD_STCMD_DISABLE_CANFD
- IFI_CANFD_STCMD_ENABLE
- IFI_CANFD_STCMD_ENABLE_7_9_8_8_TIMING
- IFI_CANFD_STCMD_ENABLE_ISO
- IFI_CANFD_STCMD_ERROR_ACTIVE
- IFI_CANFD_STCMD_ERROR_PASSIVE
- IFI_CANFD_STCMD_ERROR_WARNING
- IFI_CANFD_STCMD_HARDRESET
- IFI_CANFD_STCMD_LOOPBACK
- IFI_CANFD_STCMD_NORMAL_MODE
- IFI_CANFD_SUSPEND
- IFI_CANFD_SYSCLOCK
- IFI_CANFD_TDELAY
- IFI_CANFD_TDELAY_ABS
- IFI_CANFD_TDELAY_DEFAULT
- IFI_CANFD_TDELAY_EN
- IFI_CANFD_TDELAY_MASK
- IFI_CANFD_TEST
- IFI_CANFD_TIME
- IFI_CANFD_TIME_PRESCALE_OFF
- IFI_CANFD_TIME_SET_PRESC_4_12_6_6
- IFI_CANFD_TIME_SET_SJW_4_12_6_6
- IFI_CANFD_TIME_SET_TIMEA_4_12_6_6
- IFI_CANFD_TIME_SET_TIMEB_4_12_6_6
- IFI_CANFD_TIME_SJW_OFF_4_12_6_6
- IFI_CANFD_TIME_SJW_OFF_7_9_8_8
- IFI_CANFD_TIME_TIMEA_OFF
- IFI_CANFD_TIME_TIMEB_OFF
- IFI_CANFD_TRAFFIC
- IFI_CANFD_TSC
- IFI_CANFD_TSCONTROL
- IFI_CANFD_TST
- IFI_CANFD_TXFIFO_DATA
- IFI_CANFD_TXFIFO_DLC
- IFI_CANFD_TXFIFO_DLC_BRS
- IFI_CANFD_TXFIFO_DLC_DLC_MASK
- IFI_CANFD_TXFIFO_DLC_DLC_OFFSET
- IFI_CANFD_TXFIFO_DLC_EDL
- IFI_CANFD_TXFIFO_DLC_FNR_MASK
- IFI_CANFD_TXFIFO_DLC_FNR_OFFSET
- IFI_CANFD_TXFIFO_DLC_RTR
- IFI_CANFD_TXFIFO_ID
- IFI_CANFD_TXFIFO_ID_IDE
- IFI_CANFD_TXFIFO_ID_ID_OFFSET
- IFI_CANFD_TXFIFO_ID_ID_STD_MASK
- IFI_CANFD_TXFIFO_ID_ID_STD_OFFSET
- IFI_CANFD_TXFIFO_ID_ID_STD_WIDTH
- IFI_CANFD_TXFIFO_ID_ID_XTD_MASK
- IFI_CANFD_TXFIFO_ID_ID_XTD_OFFSET
- IFI_CANFD_TXFIFO_ID_ID_XTD_WIDTH
- IFI_CANFD_TXFIFO_REPEATCOUNT
- IFI_CANFD_TXFIFO_SUSPEND_US
- IFI_CANFD_TXSTCMD
- IFI_CANFD_TXSTCMD_ADD_MSG
- IFI_CANFD_TXSTCMD_EMPTY
- IFI_CANFD_TXSTCMD_FULL
- IFI_CANFD_TXSTCMD_HIGH_PRIO
- IFI_CANFD_TXSTCMD_OVERFLOW
- IFI_CANFD_TXSTCMD_RESET
- IFI_CANFD_VER
- IFI_CANFD_VER_REV_MASK
- IFI_CANFD_VER_REV_MIN_SUPPORTED
- IFJOURNAL
- IFL
- IFLAGS
- IFLA_ADDRESS
- IFLA_AF_SPEC
- IFLA_BOND_ACTIVE_SLAVE
- IFLA_BOND_AD_ACTOR_SYSTEM
- IFLA_BOND_AD_ACTOR_SYS_PRIO
- IFLA_BOND_AD_INFO
- IFLA_BOND_AD_INFO_ACTOR_KEY
- IFLA_BOND_AD_INFO_AGGREGATOR
- IFLA_BOND_AD_INFO_MAX
- IFLA_BOND_AD_INFO_NUM_PORTS
- IFLA_BOND_AD_INFO_PARTNER_KEY
- IFLA_BOND_AD_INFO_PARTNER_MAC
- IFLA_BOND_AD_INFO_UNSPEC
- IFLA_BOND_AD_LACP_RATE
- IFLA_BOND_AD_SELECT
- IFLA_BOND_AD_USER_PORT_KEY
- IFLA_BOND_ALL_SLAVES_ACTIVE
- IFLA_BOND_ARP_ALL_TARGETS
- IFLA_BOND_ARP_INTERVAL
- IFLA_BOND_ARP_IP_TARGET
- IFLA_BOND_ARP_VALIDATE
- IFLA_BOND_DOWNDELAY
- IFLA_BOND_FAIL_OVER_MAC
- IFLA_BOND_LP_INTERVAL
- IFLA_BOND_MAX
- IFLA_BOND_MIIMON
- IFLA_BOND_MIN_LINKS
- IFLA_BOND_MODE
- IFLA_BOND_NUM_PEER_NOTIF
- IFLA_BOND_PACKETS_PER_SLAVE
- IFLA_BOND_PEER_NOTIF_DELAY
- IFLA_BOND_PRIMARY
- IFLA_BOND_PRIMARY_RESELECT
- IFLA_BOND_RESEND_IGMP
- IFLA_BOND_SLAVE_AD_ACTOR_OPER_PORT_STATE
- IFLA_BOND_SLAVE_AD_AGGREGATOR_ID
- IFLA_BOND_SLAVE_AD_PARTNER_OPER_PORT_STATE
- IFLA_BOND_SLAVE_LINK_FAILURE_COUNT
- IFLA_BOND_SLAVE_MAX
- IFLA_BOND_SLAVE_MII_STATUS
- IFLA_BOND_SLAVE_PERM_HWADDR
- IFLA_BOND_SLAVE_QUEUE_ID
- IFLA_BOND_SLAVE_STATE
- IFLA_BOND_SLAVE_UNSPEC
- IFLA_BOND_TLB_DYNAMIC_LB
- IFLA_BOND_UNSPEC
- IFLA_BOND_UPDELAY
- IFLA_BOND_USE_CARRIER
- IFLA_BOND_XMIT_HASH_POLICY
- IFLA_BRIDGE_FLAGS
- IFLA_BRIDGE_MAX
- IFLA_BRIDGE_MODE
- IFLA_BRIDGE_VLAN_INFO
- IFLA_BRIDGE_VLAN_TUNNEL_FLAGS
- IFLA_BRIDGE_VLAN_TUNNEL_ID
- IFLA_BRIDGE_VLAN_TUNNEL_INFO
- IFLA_BRIDGE_VLAN_TUNNEL_MAX
- IFLA_BRIDGE_VLAN_TUNNEL_UNSPEC
- IFLA_BRIDGE_VLAN_TUNNEL_VID
- IFLA_BROADCAST
- IFLA_BRPORT_BACKUP_PORT
- IFLA_BRPORT_BCAST_FLOOD
- IFLA_BRPORT_BRIDGE_ID
- IFLA_BRPORT_CONFIG_PENDING
- IFLA_BRPORT_COST
- IFLA_BRPORT_DESIGNATED_COST
- IFLA_BRPORT_DESIGNATED_PORT
- IFLA_BRPORT_FAST_LEAVE
- IFLA_BRPORT_FLUSH
- IFLA_BRPORT_FORWARD_DELAY_TIMER
- IFLA_BRPORT_GROUP_FWD_MASK
- IFLA_BRPORT_GUARD
- IFLA_BRPORT_HOLD_TIMER
- IFLA_BRPORT_ID
- IFLA_BRPORT_ISOLATED
- IFLA_BRPORT_LEARNING
- IFLA_BRPORT_LEARNING_SYNC
- IFLA_BRPORT_MAX
- IFLA_BRPORT_MCAST_FLOOD
- IFLA_BRPORT_MCAST_TO_UCAST
- IFLA_BRPORT_MESSAGE_AGE_TIMER
- IFLA_BRPORT_MODE
- IFLA_BRPORT_MULTICAST_ROUTER
- IFLA_BRPORT_NEIGH_SUPPRESS
- IFLA_BRPORT_NO
- IFLA_BRPORT_PAD
- IFLA_BRPORT_PRIORITY
- IFLA_BRPORT_PROTECT
- IFLA_BRPORT_PROXYARP
- IFLA_BRPORT_PROXYARP_WIFI
- IFLA_BRPORT_ROOT_ID
- IFLA_BRPORT_STATE
- IFLA_BRPORT_TOPOLOGY_CHANGE_ACK
- IFLA_BRPORT_UNICAST_FLOOD
- IFLA_BRPORT_UNSPEC
- IFLA_BRPORT_VLAN_TUNNEL
- IFLA_BR_AGEING_TIME
- IFLA_BR_BRIDGE_ID
- IFLA_BR_FDB_FLUSH
- IFLA_BR_FORWARD_DELAY
- IFLA_BR_GC_TIMER
- IFLA_BR_GROUP_ADDR
- IFLA_BR_GROUP_FWD_MASK
- IFLA_BR_HELLO_TIME
- IFLA_BR_HELLO_TIMER
- IFLA_BR_MAX
- IFLA_BR_MAX_AGE
- IFLA_BR_MCAST_HASH_ELASTICITY
- IFLA_BR_MCAST_HASH_MAX
- IFLA_BR_MCAST_IGMP_VERSION
- IFLA_BR_MCAST_LAST_MEMBER_CNT
- IFLA_BR_MCAST_LAST_MEMBER_INTVL
- IFLA_BR_MCAST_MEMBERSHIP_INTVL
- IFLA_BR_MCAST_MLD_VERSION
- IFLA_BR_MCAST_QUERIER
- IFLA_BR_MCAST_QUERIER_INTVL
- IFLA_BR_MCAST_QUERY_INTVL
- IFLA_BR_MCAST_QUERY_RESPONSE_INTVL
- IFLA_BR_MCAST_QUERY_USE_IFADDR
- IFLA_BR_MCAST_ROUTER
- IFLA_BR_MCAST_SNOOPING
- IFLA_BR_MCAST_STARTUP_QUERY_CNT
- IFLA_BR_MCAST_STARTUP_QUERY_INTVL
- IFLA_BR_MCAST_STATS_ENABLED
- IFLA_BR_MULTI_BOOLOPT
- IFLA_BR_NF_CALL_ARPTABLES
- IFLA_BR_NF_CALL_IP6TABLES
- IFLA_BR_NF_CALL_IPTABLES
- IFLA_BR_PAD
- IFLA_BR_PRIORITY
- IFLA_BR_ROOT_ID
- IFLA_BR_ROOT_PATH_COST
- IFLA_BR_ROOT_PORT
- IFLA_BR_STP_STATE
- IFLA_BR_TCN_TIMER
- IFLA_BR_TOPOLOGY_CHANGE
- IFLA_BR_TOPOLOGY_CHANGE_DETECTED
- IFLA_BR_TOPOLOGY_CHANGE_TIMER
- IFLA_BR_UNSPEC
- IFLA_BR_VLAN_DEFAULT_PVID
- IFLA_BR_VLAN_FILTERING
- IFLA_BR_VLAN_PROTOCOL
- IFLA_BR_VLAN_STATS_ENABLED
- IFLA_BR_VLAN_STATS_PER_PORT
- IFLA_CAIF_IPV4_CONNID
- IFLA_CAIF_IPV6_CONNID
- IFLA_CAIF_LOOPBACK
- IFLA_CAIF_MAX
- IFLA_CAN_BERR_COUNTER
- IFLA_CAN_BITRATE_CONST
- IFLA_CAN_BITRATE_MAX
- IFLA_CAN_BITTIMING
- IFLA_CAN_BITTIMING_CONST
- IFLA_CAN_CLOCK
- IFLA_CAN_CTRLMODE
- IFLA_CAN_DATA_BITRATE_CONST
- IFLA_CAN_DATA_BITTIMING
- IFLA_CAN_DATA_BITTIMING_CONST
- IFLA_CAN_MAX
- IFLA_CAN_RESTART
- IFLA_CAN_RESTART_MS
- IFLA_CAN_STATE
- IFLA_CAN_TERMINATION
- IFLA_CAN_TERMINATION_CONST
- IFLA_CAN_UNSPEC
- IFLA_CARRIER
- IFLA_CARRIER_CHANGES
- IFLA_CARRIER_DOWN_COUNT
- IFLA_CARRIER_UP_COUNT
- IFLA_COST
- IFLA_EVENT
- IFLA_EVENT_BONDING_FAILOVER
- IFLA_EVENT_BONDING_OPTIONS
- IFLA_EVENT_FEATURES
- IFLA_EVENT_IGMP_RESEND
- IFLA_EVENT_NONE
- IFLA_EVENT_NOTIFY_PEERS
- IFLA_EVENT_REBOOT
- IFLA_EXT_MASK
- IFLA_GENEVE_COLLECT_METADATA
- IFLA_GENEVE_DF
- IFLA_GENEVE_ID
- IFLA_GENEVE_LABEL
- IFLA_GENEVE_MAX
- IFLA_GENEVE_PORT
- IFLA_GENEVE_REMOTE
- IFLA_GENEVE_REMOTE6
- IFLA_GENEVE_TOS
- IFLA_GENEVE_TTL
- IFLA_GENEVE_TTL_INHERIT
- IFLA_GENEVE_UDP_CSUM
- IFLA_GENEVE_UDP_ZERO_CSUM6_RX
- IFLA_GENEVE_UDP_ZERO_CSUM6_TX
- IFLA_GENEVE_UNSPEC
- IFLA_GRE_COLLECT_METADATA
- IFLA_GRE_ENCAP_DPORT
- IFLA_GRE_ENCAP_FLAGS
- IFLA_GRE_ENCAP_LIMIT
- IFLA_GRE_ENCAP_SPORT
- IFLA_GRE_ENCAP_TYPE
- IFLA_GRE_ERSPAN_DIR
- IFLA_GRE_ERSPAN_HWID
- IFLA_GRE_ERSPAN_INDEX
- IFLA_GRE_ERSPAN_VER
- IFLA_GRE_FLAGS
- IFLA_GRE_FLOWINFO
- IFLA_GRE_FWMARK
- IFLA_GRE_IFLAGS
- IFLA_GRE_IGNORE_DF
- IFLA_GRE_IKEY
- IFLA_GRE_LINK
- IFLA_GRE_LOCAL
- IFLA_GRE_MAX
- IFLA_GRE_OFLAGS
- IFLA_GRE_OKEY
- IFLA_GRE_PMTUDISC
- IFLA_GRE_REMOTE
- IFLA_GRE_TOS
- IFLA_GRE_TTL
- IFLA_GRE_UNSPEC
- IFLA_GROUP
- IFLA_GSO_MAX_SEGS
- IFLA_GSO_MAX_SIZE
- IFLA_GTP_FD0
- IFLA_GTP_FD1
- IFLA_GTP_MAX
- IFLA_GTP_PDP_HASHSIZE
- IFLA_GTP_ROLE
- IFLA_GTP_UNSPEC
- IFLA_HSR_MAX
- IFLA_HSR_MULTICAST_SPEC
- IFLA_HSR_SEQ_NR
- IFLA_HSR_SLAVE1
- IFLA_HSR_SLAVE2
- IFLA_HSR_SUPERVISION_ADDR
- IFLA_HSR_UNSPEC
- IFLA_HSR_VERSION
- IFLA_IFALIAS
- IFLA_IFNAME
- IFLA_IF_NETNSID
- IFLA_INET6_ADDR_GEN_MODE
- IFLA_INET6_CACHEINFO
- IFLA_INET6_CONF
- IFLA_INET6_FLAGS
- IFLA_INET6_ICMP6STATS
- IFLA_INET6_MAX
- IFLA_INET6_MCAST
- IFLA_INET6_STATS
- IFLA_INET6_TOKEN
- IFLA_INET6_UNSPEC
- IFLA_INET_CONF
- IFLA_INET_MAX
- IFLA_INET_UNSPEC
- IFLA_INFO_DATA
- IFLA_INFO_KIND
- IFLA_INFO_MAX
- IFLA_INFO_SLAVE_DATA
- IFLA_INFO_SLAVE_KIND
- IFLA_INFO_UNSPEC
- IFLA_INFO_XSTATS
- IFLA_IPOIB_MAX
- IFLA_IPOIB_MODE
- IFLA_IPOIB_PKEY
- IFLA_IPOIB_UMCAST
- IFLA_IPOIB_UNSPEC
- IFLA_IPTUN_6RD_PREFIX
- IFLA_IPTUN_6RD_PREFIXLEN
- IFLA_IPTUN_6RD_RELAY_PREFIX
- IFLA_IPTUN_6RD_RELAY_PREFIXLEN
- IFLA_IPTUN_COLLECT_METADATA
- IFLA_IPTUN_ENCAP_DPORT
- IFLA_IPTUN_ENCAP_FLAGS
- IFLA_IPTUN_ENCAP_LIMIT
- IFLA_IPTUN_ENCAP_SPORT
- IFLA_IPTUN_ENCAP_TYPE
- IFLA_IPTUN_FLAGS
- IFLA_IPTUN_FLOWINFO
- IFLA_IPTUN_FWMARK
- IFLA_IPTUN_LINK
- IFLA_IPTUN_LOCAL
- IFLA_IPTUN_MAX
- IFLA_IPTUN_PMTUDISC
- IFLA_IPTUN_PROTO
- IFLA_IPTUN_REMOTE
- IFLA_IPTUN_TOS
- IFLA_IPTUN_TTL
- IFLA_IPTUN_UNSPEC
- IFLA_IPVLAN_FLAGS
- IFLA_IPVLAN_MAX
- IFLA_IPVLAN_MODE
- IFLA_IPVLAN_UNSPEC
- IFLA_LINK
- IFLA_LINKINFO
- IFLA_LINKMODE
- IFLA_LINK_NETNSID
- IFLA_MACSEC_CIPHER_SUITE
- IFLA_MACSEC_ENCODING_SA
- IFLA_MACSEC_ENCRYPT
- IFLA_MACSEC_ES
- IFLA_MACSEC_ICV_LEN
- IFLA_MACSEC_INC_SCI
- IFLA_MACSEC_MAX
- IFLA_MACSEC_PAD
- IFLA_MACSEC_PORT
- IFLA_MACSEC_PROTECT
- IFLA_MACSEC_REPLAY_PROTECT
- IFLA_MACSEC_SCB
- IFLA_MACSEC_SCI
- IFLA_MACSEC_UNSPEC
- IFLA_MACSEC_VALIDATION
- IFLA_MACSEC_WINDOW
- IFLA_MACVLAN_FLAGS
- IFLA_MACVLAN_MACADDR
- IFLA_MACVLAN_MACADDR_COUNT
- IFLA_MACVLAN_MACADDR_DATA
- IFLA_MACVLAN_MACADDR_MODE
- IFLA_MACVLAN_MAX
- IFLA_MACVLAN_MODE
- IFLA_MACVLAN_UNSPEC
- IFLA_MAP
- IFLA_MASTER
- IFLA_MAX
- IFLA_MAX_MTU
- IFLA_MIN_MTU
- IFLA_MTU
- IFLA_NET_NS_FD
- IFLA_NET_NS_PID
- IFLA_NEW_IFINDEX
- IFLA_NEW_NETNSID
- IFLA_NUM_RX_QUEUES
- IFLA_NUM_TX_QUEUES
- IFLA_NUM_VF
- IFLA_OFFLOAD_XSTATS_CPU_HIT
- IFLA_OFFLOAD_XSTATS_FIRST
- IFLA_OFFLOAD_XSTATS_MAX
- IFLA_OFFLOAD_XSTATS_UNSPEC
- IFLA_OPERSTATE
- IFLA_PAD
- IFLA_PAYLOAD
- IFLA_PHYS_PORT_ID
- IFLA_PHYS_PORT_NAME
- IFLA_PHYS_SWITCH_ID
- IFLA_PORT_HOST_UUID
- IFLA_PORT_INSTANCE_UUID
- IFLA_PORT_MAX
- IFLA_PORT_PROFILE
- IFLA_PORT_REQUEST
- IFLA_PORT_RESPONSE
- IFLA_PORT_SELF
- IFLA_PORT_UNSPEC
- IFLA_PORT_VF
- IFLA_PORT_VSI_TYPE
- IFLA_PPP_DEV_FD
- IFLA_PPP_MAX
- IFLA_PPP_UNSPEC
- IFLA_PRIORITY
- IFLA_PROMISCUITY
- IFLA_PROTINFO
- IFLA_PROTO_DOWN
- IFLA_QDISC
- IFLA_RMNET_FLAGS
- IFLA_RMNET_MAX
- IFLA_RMNET_MUX_ID
- IFLA_RMNET_UNSPEC
- IFLA_RTA
- IFLA_STATS
- IFLA_STATS64
- IFLA_STATS_AF_SPEC
- IFLA_STATS_FILTER_BIT
- IFLA_STATS_LINK_64
- IFLA_STATS_LINK_OFFLOAD_XSTATS
- IFLA_STATS_LINK_XSTATS
- IFLA_STATS_LINK_XSTATS_SLAVE
- IFLA_STATS_MAX
- IFLA_STATS_UNSPEC
- IFLA_TARGET_NETNSID
- IFLA_TUN_GROUP
- IFLA_TUN_MAX
- IFLA_TUN_MULTI_QUEUE
- IFLA_TUN_NUM_DISABLED_QUEUES
- IFLA_TUN_NUM_QUEUES
- IFLA_TUN_OWNER
- IFLA_TUN_PERSIST
- IFLA_TUN_PI
- IFLA_TUN_TYPE
- IFLA_TUN_UNSPEC
- IFLA_TUN_VNET_HDR
- IFLA_TXQLEN
- IFLA_UNSPEC
- IFLA_VFINFO_LIST
- IFLA_VF_BROADCAST
- IFLA_VF_IB_NODE_GUID
- IFLA_VF_IB_PORT_GUID
- IFLA_VF_INFO
- IFLA_VF_INFO_MAX
- IFLA_VF_INFO_UNSPEC
- IFLA_VF_LINK_STATE
- IFLA_VF_LINK_STATE_AUTO
- IFLA_VF_LINK_STATE_DISABLE
- IFLA_VF_LINK_STATE_ENABLE
- IFLA_VF_MAC
- IFLA_VF_MAX
- IFLA_VF_PORT
- IFLA_VF_PORTS
- IFLA_VF_PORT_MAX
- IFLA_VF_PORT_UNSPEC
- IFLA_VF_RATE
- IFLA_VF_RSS_QUERY_EN
- IFLA_VF_SPOOFCHK
- IFLA_VF_STATS
- IFLA_VF_STATS_BROADCAST
- IFLA_VF_STATS_MAX
- IFLA_VF_STATS_MULTICAST
- IFLA_VF_STATS_PAD
- IFLA_VF_STATS_RX_BYTES
- IFLA_VF_STATS_RX_DROPPED
- IFLA_VF_STATS_RX_PACKETS
- IFLA_VF_STATS_TX_BYTES
- IFLA_VF_STATS_TX_DROPPED
- IFLA_VF_STATS_TX_PACKETS
- IFLA_VF_TRUST
- IFLA_VF_TX_RATE
- IFLA_VF_UNSPEC
- IFLA_VF_VLAN
- IFLA_VF_VLAN_INFO
- IFLA_VF_VLAN_INFO_MAX
- IFLA_VF_VLAN_INFO_UNSPEC
- IFLA_VF_VLAN_LIST
- IFLA_VLAN_EGRESS_QOS
- IFLA_VLAN_FLAGS
- IFLA_VLAN_ID
- IFLA_VLAN_INGRESS_QOS
- IFLA_VLAN_MAX
- IFLA_VLAN_PROTOCOL
- IFLA_VLAN_QOS_MAPPING
- IFLA_VLAN_QOS_MAX
- IFLA_VLAN_QOS_UNSPEC
- IFLA_VLAN_UNSPEC
- IFLA_VRF_MAX
- IFLA_VRF_PORT_MAX
- IFLA_VRF_PORT_TABLE
- IFLA_VRF_PORT_UNSPEC
- IFLA_VRF_TABLE
- IFLA_VRF_UNSPEC
- IFLA_VTI_FWMARK
- IFLA_VTI_IKEY
- IFLA_VTI_LINK
- IFLA_VTI_LOCAL
- IFLA_VTI_MAX
- IFLA_VTI_OKEY
- IFLA_VTI_REMOTE
- IFLA_VTI_UNSPEC
- IFLA_VXLAN_AGEING
- IFLA_VXLAN_COLLECT_METADATA
- IFLA_VXLAN_DF
- IFLA_VXLAN_GBP
- IFLA_VXLAN_GPE
- IFLA_VXLAN_GROUP
- IFLA_VXLAN_GROUP6
- IFLA_VXLAN_ID
- IFLA_VXLAN_L2MISS
- IFLA_VXLAN_L3MISS
- IFLA_VXLAN_LABEL
- IFLA_VXLAN_LEARNING
- IFLA_VXLAN_LIMIT
- IFLA_VXLAN_LINK
- IFLA_VXLAN_LOCAL
- IFLA_VXLAN_LOCAL6
- IFLA_VXLAN_MAX
- IFLA_VXLAN_PORT
- IFLA_VXLAN_PORT_RANGE
- IFLA_VXLAN_PROXY
- IFLA_VXLAN_REMCSUM_NOPARTIAL
- IFLA_VXLAN_REMCSUM_RX
- IFLA_VXLAN_REMCSUM_TX
- IFLA_VXLAN_RSC
- IFLA_VXLAN_TOS
- IFLA_VXLAN_TTL
- IFLA_VXLAN_TTL_INHERIT
- IFLA_VXLAN_UDP_CSUM
- IFLA_VXLAN_UDP_ZERO_CSUM6_RX
- IFLA_VXLAN_UDP_ZERO_CSUM6_TX
- IFLA_VXLAN_UNSPEC
- IFLA_WEIGHT
- IFLA_WIRELESS
- IFLA_XDP
- IFLA_XDP_ATTACHED
- IFLA_XDP_DRV_PROG_ID
- IFLA_XDP_FD
- IFLA_XDP_FLAGS
- IFLA_XDP_HW_PROG_ID
- IFLA_XDP_MAX
- IFLA_XDP_PROG_ID
- IFLA_XDP_SKB_PROG_ID
- IFLA_XDP_UNSPEC
- IFLA_XFRM_IF_ID
- IFLA_XFRM_LINK
- IFLA_XFRM_MAX
- IFLA_XFRM_UNSPEC
- IFLISTSZ
- IFLITTLE
- IFMARKER
- IFMARKINT
- IFMI
- IFMR
- IFNAMSIZ
- IFORCE_EFFECTS_MAX
- IFORCE_MAX_LENGTH
- IFORCE_XMIT_AGAIN
- IFORCE_XMIT_RUNNING
- IFR
- IFREGCTL_DONE
- IFREGCTL_IFRF
- IFREGCTL_REGW
- IFRFbWriteEmbedded
- IFS
- IFS1
- IFS1_DELTA
- IFSELECT
- IFSEL_C
- IFSEL_S
- IFSET
- IFSR
- IFSR32_EL2
- IFSTAT_EXCESS_DEFER
- IFS_BACKOFF
- IFS_CTL1_EDCRS
- IFS_CTL1_EDCRS_20L
- IFS_CTL1_EDCRS_40
- IFS_MAX
- IFS_MIN
- IFS_NEW_BACKOFF
- IFS_NONE
- IFS_RATIO
- IFS_SIFS
- IFS_STEP
- IFS_USEEDCF
- IFS_VALUE_DEFAULT
- IFS_VALUE_DIFS_SH
- IFS_VALUE_EIFS_SH
- IFS_VALUE_SIFS_SH
- IFTHEN
- IFTOCDT
- IFTRUE
- IFTYPE_HDMI
- IFU_BRUB_RESERVE
- IFX_MDM_RST_PMU
- IFX_MODEM_6160
- IFX_MODEM_6260
- IFX_RESET_TIMEOUT
- IFX_SPI_CTS
- IFX_SPI_CTS_BIT
- IFX_SPI_DCD
- IFX_SPI_DSR
- IFX_SPI_DTR
- IFX_SPI_FIFO_SIZE
- IFX_SPI_GPIO0
- IFX_SPI_GPIO_TARGET
- IFX_SPI_HEADER_0
- IFX_SPI_HEADER_F
- IFX_SPI_HEADER_OVERHEAD
- IFX_SPI_IRQ_TYPE
- IFX_SPI_MAX_MINORS
- IFX_SPI_MODE
- IFX_SPI_MORE_BIT
- IFX_SPI_MORE_MASK
- IFX_SPI_PAYLOAD_SIZE
- IFX_SPI_POWER_DATA_PENDING
- IFX_SPI_POWER_SRDY
- IFX_SPI_RI
- IFX_SPI_RTS
- IFX_SPI_RX_FC
- IFX_SPI_STATE_IO_AVAILABLE
- IFX_SPI_STATE_IO_IN_PROGRESS
- IFX_SPI_STATE_IO_READY
- IFX_SPI_STATE_PRESENT
- IFX_SPI_STATE_TIMER_PENDING
- IFX_SPI_STATUS_TIMEOUT
- IFX_SPI_TIMEOUT_SEC
- IFX_SPI_TRANSFER_SIZE
- IFX_SPI_TTY_ID
- IFX_SPI_TX_FC
- IFX_SPI_UPDATE
- IFXcvrIO
- IF_ABR
- IF_ACT_FILTER
- IF_ACT_NONE
- IF_ACT_START
- IF_ACT_STOP
- IF_ARB_MSGVAL
- IF_ARB_MSGXTD
- IF_ARB_TRANSMIT
- IF_ASSIGN
- IF_AUD0
- IF_AUD1
- IF_AUD2
- IF_AUD3
- IF_BLIT
- IF_CAIF_H_
- IF_CAPS_FLAGS_VALID_SHIFT
- IF_CBR
- IF_CLR
- IF_COMB_AP
- IF_COMM_ARB
- IF_COMM_CLR_INT_PND
- IF_COMM_CLR_NEWDAT
- IF_COMM_CONTROL
- IF_COMM_DATAA
- IF_COMM_DATAB
- IF_COMM_INVAL
- IF_COMM_MASK
- IF_COMM_RCV_HIGH
- IF_COMM_RCV_LOW
- IF_COMM_RCV_SETUP
- IF_COMM_TX
- IF_COMM_TXRQST
- IF_COMM_WR
- IF_COMR_BUSY
- IF_COPER
- IF_COPY
- IF_COPY_OVER
- IF_COUNT_GET
- IF_CS_BIT_COMMAND
- IF_CS_BIT_EVENT
- IF_CS_BIT_MASK
- IF_CS_BIT_RESP
- IF_CS_BIT_RX
- IF_CS_BIT_TX
- IF_CS_CARD_INT_CAUSE
- IF_CS_CARD_STATUS
- IF_CS_CARD_STATUS_MASK
- IF_CS_CF8305_B1_REV
- IF_CS_CF8381_B3_REV
- IF_CS_CF8385_B1_REV
- IF_CS_CMD
- IF_CS_CMD_LEN
- IF_CS_HOST_INT_CAUSE
- IF_CS_HOST_INT_MASK
- IF_CS_HOST_STATUS
- IF_CS_PRODUCT_ID
- IF_CS_READ
- IF_CS_READ_LEN
- IF_CS_RESP
- IF_CS_RESP_LEN
- IF_CS_SCRATCH
- IF_CS_SCRATCH_BOOT_OK
- IF_CS_SCRATCH_HELPER_OK
- IF_CS_SQ_HELPER_OK
- IF_CS_SQ_READ_LOW
- IF_CS_WRITE
- IF_CS_WRITE_LEN
- IF_DIS_INTR
- IF_DIVVAL
- IF_DSKBLK
- IF_DSKSYN
- IF_EN
- IF_ENUM_REG_LEN
- IF_EN_INTR
- IF_ERR
- IF_EVENT
- IF_EXTER
- IF_FREQUENCYx6
- IF_FREQ_36000000HZ
- IF_FREQ_36125000HZ
- IF_FREQ_36166667HZ
- IF_FREQ_3point3_MHZ
- IF_FREQ_3point5_MHZ
- IF_FREQ_44000000HZ
- IF_FREQ_4570000HZ
- IF_FREQ_4571429HZ
- IF_FREQ_4_MHZ
- IF_FREQ_5380000HZ
- IF_FREQ_6_MHZ
- IF_GET_IFACE
- IF_GET_PROTO
- IF_HANG
- IF_HAVE_PG_HWPOISON
- IF_HAVE_PG_IDLE
- IF_HAVE_PG_MLOCK
- IF_HAVE_PG_UNCACHED
- IF_HAVE_VM_SOFTDIRTY
- IF_I2C_CLK
- IF_I2C_DATA
- IF_I2C_DATA_DIR
- IF_IADBG
- IF_IADBG_ABR
- IF_IADBG_CBR
- IF_IADBG_DESC
- IF_IADBG_DIS_INTR
- IF_IADBG_EN_INTR
- IF_IADBG_ERR
- IF_IADBG_EVENT
- IF_IADBG_INIT_ADAPTER
- IF_IADBG_INTR
- IF_IADBG_LOUD
- IF_IADBG_QUERY_INFO
- IF_IADBG_RESET
- IF_IADBG_RX
- IF_IADBG_RXPKT
- IF_IADBG_SHUTDOWN
- IF_IADBG_SUNI_STAT
- IF_IADBG_TX
- IF_IADBG_TXPKT
- IF_IADBG_UBR
- IF_IADBG_VERY_LOUD
- IF_ID_DEBUG
- IF_ID_ISL36356A
- IF_ID_ISL37700_UAP
- IF_ID_ISL37704C
- IF_ID_ISL39000
- IF_ID_ISL39000_UAP
- IF_ID_ISL39300A
- IF_ID_LMAC
- IF_ID_MVC
- IF_ID_OEM
- IF_ID_PCI3877
- IF_ID_PRODUCT
- IF_IFACE_E1
- IF_IFACE_SYNC_SERIAL
- IF_IFACE_T1
- IF_IFACE_V24
- IF_IFACE_V35
- IF_IFACE_X21
- IF_IFACE_X21D
- IF_IFSEL
- IF_INIT
- IF_INIT_ADAPTER
- IF_INTEN
- IF_INTR
- IF_ISSET
- IF_IS_INT_TABLE_ADDR
- IF_IS_PRAM_ADDR
- IF_LINK_MODE_DEFAULT
- IF_LINK_MODE_DORMANT
- IF_LOUD
- IF_LP_EN
- IF_MCONT_DLC_MASK
- IF_MCONT_EOB
- IF_MCONT_INTPND
- IF_MCONT_MSGLST
- IF_MCONT_NEWDAT
- IF_MCONT_RCV
- IF_MCONT_RCV_EOB
- IF_MCONT_RMTEN
- IF_MCONT_RXIE
- IF_MCONT_TX
- IF_MCONT_TXIE
- IF_MCONT_TXRQST
- IF_MCONT_UMASK
- IF_MODE_10G
- IF_MODE_GMII
- IF_MODE_HD
- IF_MODE_MASK
- IF_MODE_RGMII
- IF_MODE_RGMII_10
- IF_MODE_RGMII_100
- IF_MODE_RGMII_1000
- IF_MODE_RGMII_AUTO
- IF_MODE_RGMII_FD
- IF_MODE_RGMII_SP_MASK
- IF_MODE_SGMII_DUPLEX_HALF
- IF_MODE_SGMII_EN
- IF_MODE_SGMII_SPEED_100M
- IF_MODE_SGMII_SPEED_1G
- IF_MODE_USE_SGMII_AN
- IF_OFFSET
- IF_OPER_DORMANT
- IF_OPER_DOWN
- IF_OPER_LOWERLAYERDOWN
- IF_OPER_NOTPRESENT
- IF_OPER_TESTING
- IF_OPER_UNKNOWN
- IF_OPER_UP
- IF_PORTS
- IF_PORT_100BASEFX
- IF_PORT_100BASET
- IF_PORT_100BASETX
- IF_PORT_10BASE2
- IF_PORT_10BASET
- IF_PORT_AUI
- IF_PORT_UNKNOWN
- IF_PREFIX_AUTOCONF
- IF_PREFIX_ONLINK
- IF_PROTO_CISCO
- IF_PROTO_FR
- IF_PROTO_FR_ADD_ETH_PVC
- IF_PROTO_FR_ADD_PVC
- IF_PROTO_FR_DEL_ETH_PVC
- IF_PROTO_FR_DEL_PVC
- IF_PROTO_FR_ETH_PVC
- IF_PROTO_FR_PVC
- IF_PROTO_HDLC
- IF_PROTO_HDLC_ETH
- IF_PROTO_PPP
- IF_PROTO_RAW
- IF_PROTO_X25
- IF_PVC_CHKPKT
- IF_QUERY_INFO
- IF_RA_MANAGED
- IF_RA_OTHERCONF
- IF_RA_RCVD
- IF_RBF
- IF_RD_SWAPPER_FB
- IF_READY
- IF_REGSEL
- IF_RS_SENT
- IF_RX
- IF_RXPKT
- IF_SDIO_BLOCK_SIZE
- IF_SDIO_CIS_RDY
- IF_SDIO_C_INT_MASK
- IF_SDIO_C_INT_RSR
- IF_SDIO_C_INT_STATUS
- IF_SDIO_DL_RDY
- IF_SDIO_EVENT
- IF_SDIO_FIRMWARE_OK
- IF_SDIO_FW_STATUS
- IF_SDIO_H_INT_DNLD
- IF_SDIO_H_INT_MASK
- IF_SDIO_H_INT_OFLOW
- IF_SDIO_H_INT_RSR
- IF_SDIO_H_INT_STATUS
- IF_SDIO_H_INT_STATUS2
- IF_SDIO_H_INT_UFLOW
- IF_SDIO_H_INT_UPLD
- IF_SDIO_IOPORT
- IF_SDIO_IO_RDY
- IF_SDIO_RD_BASE
- IF_SDIO_RX_LEN
- IF_SDIO_RX_UNIT
- IF_SDIO_SCRATCH
- IF_SDIO_SCRATCH_OLD
- IF_SDIO_STATUS
- IF_SDIO_UL_RDY
- IF_SEL_DBL
- IF_SET
- IF_SETCLR
- IF_SETSIZE
- IF_SHUTDOWN
- IF_SI_OWNER_MASK
- IF_SI_OWNER_OFFSET
- IF_SI_OWNER_SIBM
- IF_SI_OWNER_SIMC
- IF_SI_OWNER_SISL
- IF_SOFT
- IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA
- IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA
- IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA
- IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA
- IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK
- IF_SPI_BUS_MODE_DELAY_METHOD_TIMED
- IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING
- IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING
- IF_SPI_CARD_INT_CAUSE_REG
- IF_SPI_CARD_INT_EVENT_MASK_REG
- IF_SPI_CARD_INT_RESET_SELECT_REG
- IF_SPI_CARD_INT_STATUS_MASK_REG
- IF_SPI_CARD_INT_STATUS_REG
- IF_SPI_CIC_CMD_DOWNLOAD_OVER
- IF_SPI_CIC_CMD_UPLOAD_OVER
- IF_SPI_CIC_HOST_EVENT
- IF_SPI_CIC_POWER_DOWN
- IF_SPI_CIC_RX_UPLOAD_OVER
- IF_SPI_CIC_TX_DOWNLOAD_OVER
- IF_SPI_CIS_CMD_DOWNLOAD_OVER
- IF_SPI_CIS_CMD_UPLOAD_OVER
- IF_SPI_CIS_HOST_EVENT
- IF_SPI_CIS_POWER_DOWN
- IF_SPI_CIS_RX_UPLOAD_OVER
- IF_SPI_CIS_TX_DOWNLOAD_OVER
- IF_SPI_CMD_BUF_SIZE
- IF_SPI_CMD_RDWRPORT_REG
- IF_SPI_CMD_READBASE_REG
- IF_SPI_CMD_WRITEBASE_REG
- IF_SPI_DATA_RDWRPORT_REG
- IF_SPI_DATA_READBASE_REG
- IF_SPI_DATA_WRITEBASE_REG
- IF_SPI_DELAY_READ_REG
- IF_SPI_DEVICEID_CTRL_REG
- IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID
- IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV
- IF_SPI_FW_NAME_MAX
- IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO
- IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO
- IF_SPI_HICT_RX_UPLOAD_OVER_AUTO
- IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO
- IF_SPI_HICT_WAKE_UP
- IF_SPI_HICT_WLAN_READY
- IF_SPI_HICU_CARD_EVENT
- IF_SPI_HICU_CMD_DOWNLOAD_RDY
- IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW
- IF_SPI_HICU_CMD_UPLOAD_RDY
- IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW
- IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW
- IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW
- IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW
- IF_SPI_HICU_IO_WR_FIFO_OVERFLOW
- IF_SPI_HICU_RX_UPLOAD_RDY
- IF_SPI_HICU_TX_DOWNLOAD_RDY
- IF_SPI_HISM_CARDEVENT
- IF_SPI_HISM_CMD_DOWNLOAD_RDY
- IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW
- IF_SPI_HISM_CMD_UPLOAD_RDY
- IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW
- IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW
- IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW
- IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW
- IF_SPI_HISM_IO_WR_FIFO_OVERFLOW
- IF_SPI_HISM_RX_UPLOAD_RDY
- IF_SPI_HISM_TX_DOWNLOAD_RDY
- IF_SPI_HIST_CARD_EVENT
- IF_SPI_HIST_CMD_DOWNLOAD_RDY
- IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW
- IF_SPI_HIST_CMD_UPLOAD_RDY
- IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW
- IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW
- IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW
- IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW
- IF_SPI_HIST_IO_WR_FIFO_OVERFLOW
- IF_SPI_HIST_RX_UPLOAD_RDY
- IF_SPI_HIST_TX_DOWNLOAD_RDY
- IF_SPI_HOST_INT_CAUSE_REG
- IF_SPI_HOST_INT_CTRL_REG
- IF_SPI_HOST_INT_EVENT_MASK_REG
- IF_SPI_HOST_INT_RESET_SELECT_REG
- IF_SPI_HOST_INT_STATUS_MASK_REG
- IF_SPI_HOST_INT_STATUS_REG
- IF_SPI_IO_RDWRPORT_REG
- IF_SPI_IO_READBASE_REG
- IF_SPI_IO_WRITEBASE_REG
- IF_SPI_READ_OPERATION_MASK
- IF_SPI_SCRATCH_1_REG
- IF_SPI_SCRATCH_2_REG
- IF_SPI_SCRATCH_3_REG
- IF_SPI_SCRATCH_4_REG
- IF_SPI_SPU_BUS_MODE_REG
- IF_SPI_TX_FRAME_SEQ_NUM_REG
- IF_SPI_TX_FRAME_STATUS_REG
- IF_SPI_WRITE_OPERATION_MASK
- IF_SRC_CTL
- IF_SRC_FILE
- IF_SRC_FILEADDR
- IF_SRC_KERNEL
- IF_SRC_KERNELADDR
- IF_STATE_ACTION
- IF_STATE_END
- IF_STATE_SOURCE
- IF_STATUS
- IF_SUNI_STAT
- IF_TBE
- IF_TE_EN
- IF_TX
- IF_TXDEBUG
- IF_TXPKT
- IF_TYPE_16BIT
- IF_TYPE_DIO
- IF_TYPE_DUAL
- IF_TYPE_QIO
- IF_TYPE_QUAD
- IF_TYPE_STD
- IF_UBR
- IF_UNTERM_PKT_ERR
- IF_UP
- IF_VC
- IF_VCHAN_ID
- IF_VCO_BIAS
- IF_VERTB
- IF_VERY_LOUD
- IF_VID_DEC_PAD_IF_INPUT
- IF_VID_DEC_PAD_NUM_PADS
- IF_VID_DEC_PAD_OUT
- IF_VID_MODE
- IF_VID_SELECT
- IF_VID_SELECT_MASK
- IF_WRITEBUF
- IF_ZERO
- IGA1
- IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
- IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
- IGA1_FETCH_COUNT_ALIGN_BYTE
- IGA1_FETCH_COUNT_FORMULA
- IGA1_FETCH_COUNT_PATCH_VALUE
- IGA1_FETCH_COUNT_REG_NUM
- IGA1_FIFO_DEPTH_SELECT_FORMULA
- IGA1_FIFO_DEPTH_SELECT_REG_NUM
- IGA1_FIFO_HIGH_THRESHOLD_FORMULA
- IGA1_FIFO_HIGH_THRESHOLD_REG_NUM
- IGA1_FIFO_THRESHOLD_FORMULA
- IGA1_FIFO_THRESHOLD_REG_NUM
- IGA1_STARTING_ADDR_REG_NUM
- IGA2
- IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
- IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
- IGA2_FETCH_COUNT_ALIGN_BYTE
- IGA2_FETCH_COUNT_FORMULA
- IGA2_FETCH_COUNT_PATCH_VALUE
- IGA2_FETCH_COUNT_REG_NUM
- IGA2_FIFO_DEPTH_SELECT_FORMULA
- IGA2_FIFO_DEPTH_SELECT_REG_NUM
- IGA2_FIFO_HIGH_THRESHOLD_FORMULA
- IGA2_FIFO_HIGH_THRESHOLD_REG_NUM
- IGA2_FIFO_THRESHOLD_FORMULA
- IGA2_FIFO_THRESHOLD_REG_NUM
- IGA2_HOR_BLANK_END_SHADOW_FORMULA
- IGA2_HOR_TOTAL_SHADOW_FORMULA
- IGA2_SHADOW_HOR_BLANK_END_REG_NUM
- IGA2_SHADOW_HOR_TOTAL_REG_NUM
- IGA2_SHADOW_VER_ADDR_REG_NUM
- IGA2_SHADOW_VER_BLANK_END_REG_NUM
- IGA2_SHADOW_VER_BLANK_START_REG_NUM
- IGA2_SHADOW_VER_SYNC_END_REG_NUM
- IGA2_SHADOW_VER_SYNC_START_REG_NUM
- IGA2_SHADOW_VER_TOTAL_REG_NUM
- IGA2_STARTING_ADDR_REG_NUM
- IGA2_VER_ADDR_SHADOW_FORMULA
- IGA2_VER_BLANK_END_SHADOW_FORMULA
- IGA2_VER_BLANK_START_SHADOW_FORMULA
- IGA2_VER_SYNC_END_SHADOW_FORMULA
- IGA2_VER_SYNC_START_SHADOW_FORMULA
- IGA2_VER_TOTAL_SHADOW_FORMULA
- IGBVF_20K_ITR
- IGBVF_4K_ITR
- IGBVF_70K_ITR
- IGBVF_DEFAULT_RXD
- IGBVF_DEFAULT_TXD
- IGBVF_EEPROM_APME
- IGBVF_FC_PAUSE_TIME
- IGBVF_FLAG_RX_CSUM_DISABLED
- IGBVF_FLAG_RX_LB_VLAN_BSWAP
- IGBVF_GLOBAL_STATS_LEN
- IGBVF_GSO_PARTIAL_FEATURES
- IGBVF_INT_MODE_LEGACY
- IGBVF_INT_MODE_MSI
- IGBVF_INT_MODE_MSIX
- IGBVF_MAX_DATA_PER_TXD
- IGBVF_MAX_ITR_USECS
- IGBVF_MAX_MAC_FILTERS
- IGBVF_MAX_MAC_HDR_LEN
- IGBVF_MAX_NETWORK_HDR_LEN
- IGBVF_MAX_RXD
- IGBVF_MAX_TXD
- IGBVF_MAX_TXD_PWR
- IGBVF_MIN_ITR_USECS
- IGBVF_MIN_RXD
- IGBVF_MIN_TXD
- IGBVF_MNG_VLAN_NONE
- IGBVF_NO_QUEUE
- IGBVF_REGS_LEN
- IGBVF_RX_BUFFER_WRITE
- IGBVF_RX_DESC_ADV
- IGBVF_RX_HTHRESH
- IGBVF_RX_PTHRESH
- IGBVF_RX_WTHRESH
- IGBVF_START_ITR
- IGBVF_STAT
- IGBVF_TEST_LEN
- IGBVF_TX_CTXTDESC_ADV
- IGBVF_TX_DESC_ADV
- IGBVF_TX_FLAGS_CSUM
- IGBVF_TX_FLAGS_IPV4
- IGBVF_TX_FLAGS_TSO
- IGBVF_TX_FLAGS_VLAN
- IGBVF_TX_FLAGS_VLAN_MASK
- IGBVF_TX_FLAGS_VLAN_SHIFT
- IGBVF_TX_QUEUE_WAKE
- IGB_20K_ITR
- IGB_4K_ITR
- IGB_70K_ITR
- IGB_82576_TSYNC_SHIFT
- IGB_82576_VF_DEV_ID
- IGB_BUILD_MASK
- IGB_COMB_VER_MASK
- IGB_COMB_VER_SHFT
- IGB_DEFAULT_ITR
- IGB_DEFAULT_RXD
- IGB_DEFAULT_TXD
- IGB_DEFAULT_TX_WORK
- IGB_DMCTLX_DCFLUSH_DIS
- IGB_EEPROM_APME
- IGB_ETQF_FILTER_1588
- IGB_ETRACK_SHIFT
- IGB_FILTER_FLAG_DST_MAC_ADDR
- IGB_FILTER_FLAG_ETHER_TYPE
- IGB_FILTER_FLAG_SRC_MAC_ADDR
- IGB_FILTER_FLAG_VLAN_TCI
- IGB_FLAG_DCA_ENABLED
- IGB_FLAG_DMAC
- IGB_FLAG_EEE
- IGB_FLAG_FQTSS
- IGB_FLAG_HAS_MSI
- IGB_FLAG_HAS_MSIX
- IGB_FLAG_MAS_CAPABLE
- IGB_FLAG_MAS_ENABLE
- IGB_FLAG_MEDIA_RESET
- IGB_FLAG_NEED_LINK_UPDATE
- IGB_FLAG_QUAD_PORT_A
- IGB_FLAG_QUEUE_PAIRS
- IGB_FLAG_RSS_FIELD_IPV4_UDP
- IGB_FLAG_RSS_FIELD_IPV6_UDP
- IGB_FLAG_RX_LEGACY
- IGB_FLAG_VLAN_PROMISC
- IGB_FLAG_WOL_SUPPORTED
- IGB_GLOBAL_STATS_LEN
- IGB_GSO_PARTIAL_FEATURES
- IGB_HWMON_TYPE_CAUTION
- IGB_HWMON_TYPE_LOC
- IGB_HWMON_TYPE_MAX
- IGB_HWMON_TYPE_TEMP
- IGB_I210_RX_LATENCY_10
- IGB_I210_RX_LATENCY_100
- IGB_I210_RX_LATENCY_1000
- IGB_I210_TX_LATENCY_10
- IGB_I210_TX_LATENCY_100
- IGB_I210_TX_LATENCY_1000
- IGB_I350_VF_DEV_ID
- IGB_LAST_OFFSET
- IGB_LED_ON
- IGB_MAC_STATE_DEFAULT
- IGB_MAC_STATE_IN_USE
- IGB_MAC_STATE_QUEUE_STEERING
- IGB_MAC_STATE_SRC_ADDR
- IGB_MAJOR_MASK
- IGB_MAJOR_SHIFT
- IGB_MASTER_SLAVE
- IGB_MAS_ENABLE_0
- IGB_MAS_ENABLE_1
- IGB_MAS_ENABLE_2
- IGB_MAS_ENABLE_3
- IGB_MAX_DATA_PER_TXD
- IGB_MAX_FRAME_BUILD_SKB
- IGB_MAX_ITR_USECS
- IGB_MAX_MAC_HDR_LEN
- IGB_MAX_NETWORK_HDR_LEN
- IGB_MAX_RXD
- IGB_MAX_RXNFC_FILTERS
- IGB_MAX_RX_QUEUES
- IGB_MAX_RX_QUEUES_82575
- IGB_MAX_RX_QUEUES_I211
- IGB_MAX_TXD
- IGB_MAX_TXD_PWR
- IGB_MAX_TX_QUEUES
- IGB_MAX_VFTA_ENTRIES
- IGB_MAX_VF_FUNCTIONS
- IGB_MAX_VF_MC_ENTRIES
- IGB_MINOR_MASK
- IGB_MINOR_SHIFT
- IGB_MIN_ITR_USECS
- IGB_MIN_RXD
- IGB_MIN_TXD
- IGB_MIN_TXPBSIZE
- IGB_MNG_VLAN_NONE
- IGB_N0_QUEUE
- IGB_NBITS_82580
- IGB_NETDEV_STAT
- IGB_NETDEV_STATS_LEN
- IGB_NVM_VER_INVALID
- IGB_N_EXTTS
- IGB_N_PEROUT
- IGB_N_SDP
- IGB_PF_MAC_FILTERS_RESERVED
- IGB_PRIV_FLAGS_LEGACY_RX
- IGB_PRIV_FLAGS_STR_LEN
- IGB_PTP_ENABLED
- IGB_PTP_OVERFLOW_CHECK
- IGB_PTP_TX_TIMEOUT
- IGB_QUEUE_STATS_LEN
- IGB_REGS_LEN
- IGB_RETA_SIZE
- IGB_RING_FLAG_RX_3K_BUFFER
- IGB_RING_FLAG_RX_BUILD_SKB_ENABLED
- IGB_RING_FLAG_RX_LB_VLAN_BSWAP
- IGB_RING_FLAG_RX_SCTP_CSUM
- IGB_RING_FLAG_TX_CTX_IDX
- IGB_RING_FLAG_TX_DETECT_HANG
- IGB_RXBUFFER_2048
- IGB_RXBUFFER_256
- IGB_RXBUFFER_3072
- IGB_RX_BUFFER_WRITE
- IGB_RX_DESC
- IGB_RX_DMA_ATTR
- IGB_RX_HDR_LEN
- IGB_RX_HTHRESH
- IGB_RX_PTHRESH
- IGB_RX_QUEUE_STATS_LEN
- IGB_RX_WTHRESH
- IGB_SET_FLAG
- IGB_SFF_8472_COMP
- IGB_SFF_8472_SWAP
- IGB_SFF_8472_UNSUP
- IGB_SFF_ADDRESSING_MODE
- IGB_SKB_PAD
- IGB_STAGGERED_QUEUE_OFFSET
- IGB_START_ITR
- IGB_STAT
- IGB_STATS_LEN
- IGB_SYSTIM_OVERFLOW_PERIOD
- IGB_TEST_LEN
- IGB_TS_HDR_LEN
- IGB_TXD_DCMD
- IGB_TX_BUF_4096
- IGB_TX_CTXTDESC
- IGB_TX_DESC
- IGB_TX_FLAGS_CSUM
- IGB_TX_FLAGS_IPV4
- IGB_TX_FLAGS_TSO
- IGB_TX_FLAGS_TSTAMP
- IGB_TX_FLAGS_VLAN
- IGB_TX_FLAGS_VLAN_MASK
- IGB_TX_FLAGS_VLAN_SHIFT
- IGB_TX_HTHRESH
- IGB_TX_PTHRESH
- IGB_TX_QUEUE_STATS_LEN
- IGB_TX_WTHRESH
- IGB_VF_FLAG_CTS
- IGB_VF_FLAG_MULTI_PROMISC
- IGB_VF_FLAG_PF_SET_MAC
- IGB_VF_FLAG_UNI_PROMISC
- IGCSR
- IGC_20K_ITR
- IGC_4K_ITR
- IGC_70K_ITR
- IGC_ADVTXD_DCMD_DEXT
- IGC_ADVTXD_DCMD_EOP
- IGC_ADVTXD_DCMD_IFCS
- IGC_ADVTXD_DCMD_RS
- IGC_ADVTXD_DCMD_TSE
- IGC_ADVTXD_DCMD_VLE
- IGC_ADVTXD_DTYP_CTXT
- IGC_ADVTXD_DTYP_DATA
- IGC_ADVTXD_MACLEN_SHIFT
- IGC_ADVTXD_MAC_TSTAMP
- IGC_ADVTXD_PAYLEN_SHIFT
- IGC_ADVTXD_TUCMD_IPV4
- IGC_ADVTXD_TUCMD_L4T_SCTP
- IGC_ADVTXD_TUCMD_L4T_TCP
- IGC_ALGNERRC
- IGC_ALL_SPEED_DUPLEX_2500
- IGC_BPRC
- IGC_BPTC
- IGC_CBRMPC
- IGC_CBTMPC
- IGC_CEXTERR
- IGC_COLC
- IGC_COLD_SHIFT
- IGC_COLLISION_DISTANCE
- IGC_COLLISION_THRESHOLD
- IGC_CONNSW
- IGC_CONNSW_AUTOSENSE_EN
- IGC_CRCERRS
- IGC_CTRL
- IGC_CTRL_DEV_RST
- IGC_CTRL_EXT
- IGC_CTRL_EXT_DRV_LOAD
- IGC_CTRL_EXT_LINK_MODE_MASK
- IGC_CTRL_FRCDPX
- IGC_CTRL_FRCSPD
- IGC_CTRL_GIO_MASTER_DISABLE
- IGC_CTRL_PHY_RST
- IGC_CTRL_RFCE
- IGC_CTRL_SLU
- IGC_CTRL_TFCE
- IGC_CT_SHIFT
- IGC_DC
- IGC_DEFAULT_ITR
- IGC_DEFAULT_RXD
- IGC_DEFAULT_TXD
- IGC_DEFAULT_TX_WORK
- IGC_DEV_ID_I220_V
- IGC_DEV_ID_I225_I
- IGC_DEV_ID_I225_K
- IGC_DEV_ID_I225_LM
- IGC_DEV_ID_I225_V
- IGC_DMA
- IGC_DSPP
- IGC_ECOL
- IGC_EECD
- IGC_EECD_ADDR_BITS
- IGC_EECD_AUTO_RD
- IGC_EECD_FLASH_DETECTED_I225
- IGC_EECD_FLUDONE_I225
- IGC_EECD_FLUPD_I225
- IGC_EECD_GNT
- IGC_EECD_REQ
- IGC_EECD_SIZE_EX_MASK
- IGC_EECD_SIZE_EX_SHIFT
- IGC_EERD
- IGC_EERD_EEWR_MAX_COUNT
- IGC_EEWR
- IGC_EIAC
- IGC_EIAM
- IGC_EICS
- IGC_EIMC
- IGC_EIMS
- IGC_EITR
- IGC_EITR_CNT_IGNR
- IGC_ERR_BLK_PHY_RESET
- IGC_ERR_CONFIG
- IGC_ERR_MAC_INIT
- IGC_ERR_MASTER_REQUESTS_PENDING
- IGC_ERR_NVM
- IGC_ERR_PARAM
- IGC_ERR_PHY
- IGC_ERR_RESET
- IGC_ERR_SWFW_SYNC
- IGC_ETQF
- IGC_ETQF_ETYPE_MASK
- IGC_ETQF_FILTER_ENABLE
- IGC_ETQF_QUEUE_ENABLE
- IGC_ETQF_QUEUE_MASK
- IGC_ETQF_QUEUE_SHIFT
- IGC_FACTPS
- IGC_FACTPS_MNGCG
- IGC_FCAH
- IGC_FCAL
- IGC_FCRTH
- IGC_FCRTL
- IGC_FCRTL_XONE
- IGC_FCRTV
- IGC_FCRUC
- IGC_FCSTS
- IGC_FCT
- IGC_FCTTV
- IGC_FILTER_FLAG_DST_MAC_ADDR
- IGC_FILTER_FLAG_ETHER_TYPE
- IGC_FILTER_FLAG_SRC_MAC_ADDR
- IGC_FILTER_FLAG_VLAN_TCI
- IGC_FLAG_DMAC
- IGC_FLAG_HAS_MSI
- IGC_FLAG_HAS_MSIX
- IGC_FLAG_MAS_ENABLE
- IGC_FLAG_MEDIA_RESET
- IGC_FLAG_NEED_LINK_UPDATE
- IGC_FLAG_QUEUE_PAIRS
- IGC_FLAG_RSS_FIELD_IPV4_UDP
- IGC_FLAG_RSS_FIELD_IPV6_UDP
- IGC_FLAG_RX_LEGACY
- IGC_FLAG_VLAN_PROMISC
- IGC_FLUDONE_ATTEMPTS
- IGC_FUNC_0
- IGC_FWSM
- IGC_FWSM_MODE_MASK
- IGC_FWSM_MODE_SHIFT
- IGC_GCR
- IGC_GEN_POLL_TIMEOUT
- IGC_GLOBAL_STATS_LEN
- IGC_GORCH
- IGC_GORCL
- IGC_GOTCH
- IGC_GOTCL
- IGC_GPIE
- IGC_GPIE_EIAME
- IGC_GPIE_MSIX_MODE
- IGC_GPIE_NSICR
- IGC_GPIE_PBA
- IGC_GPRC
- IGC_GPTC
- IGC_HGORCH
- IGC_HGORCL
- IGC_HGOTCH
- IGC_HGOTCL
- IGC_HGPTC
- IGC_HRMPC
- IGC_HTCBDPC
- IGC_HTDPMC
- IGC_IAC
- IGC_IAM
- IGC_ICR
- IGC_ICRXATC
- IGC_ICRXDMTC
- IGC_ICRXOC
- IGC_ICRXPTC
- IGC_ICR_DOUTSYNC
- IGC_ICR_DRSTA
- IGC_ICR_INT_ASSERTED
- IGC_ICR_LSC
- IGC_ICR_RXDMT0
- IGC_ICR_RXO
- IGC_ICR_RXSEQ
- IGC_ICR_RXT0
- IGC_ICR_TXDW
- IGC_ICR_TXQE
- IGC_ICS
- IGC_ICS_DRSTA
- IGC_ICS_LSC
- IGC_ICS_RXDMT0
- IGC_ICS_RXT0
- IGC_ICTXATC
- IGC_ICTXPTC
- IGC_ICTXQEC
- IGC_ICTXQMTC
- IGC_IMC
- IGC_IMS
- IGC_IMS_DOUTSYNC
- IGC_IMS_DRSTA
- IGC_IMS_LSC
- IGC_IMS_RXDMT0
- IGC_IMS_RXSEQ
- IGC_IMS_RXT0
- IGC_IMS_TXDW
- IGC_ITR_VAL_MASK
- IGC_IVAR0
- IGC_IVAR_MISC
- IGC_IVAR_VALID
- IGC_LAST_OFFSET
- IGC_LATECOL
- IGC_LENERRS
- IGC_MAC_STATE_DEFAULT
- IGC_MAC_STATE_IN_USE
- IGC_MAC_STATE_QUEUE_STEERING
- IGC_MAC_STATE_SRC_ADDR
- IGC_MANC
- IGC_MANC_ASF_EN
- IGC_MANC_BLK_PHY_RST_ON_IDE
- IGC_MANC_RCV_TCO_EN
- IGC_MANC_SMBUS_EN
- IGC_MAX_DATA_PER_TXD
- IGC_MAX_FRAME_BUILD_SKB
- IGC_MAX_ITR_USECS
- IGC_MAX_MAC_HDR_LEN
- IGC_MAX_NETWORK_HDR_LEN
- IGC_MAX_RXD
- IGC_MAX_RXNFC_FILTERS
- IGC_MAX_RX_QUEUES
- IGC_MAX_TXD
- IGC_MAX_TXD_PWR
- IGC_MAX_TX_QUEUES
- IGC_MCC
- IGC_MDIC
- IGC_MDICNFG
- IGC_MDIC_DATA_MASK
- IGC_MDIC_DEST
- IGC_MDIC_ERROR
- IGC_MDIC_INT_EN
- IGC_MDIC_OP_READ
- IGC_MDIC_OP_WRITE
- IGC_MDIC_PHY_MASK
- IGC_MDIC_PHY_SHIFT
- IGC_MDIC_READY
- IGC_MDIC_REG_MASK
- IGC_MDIC_REG_SHIFT
- IGC_MGTPDC
- IGC_MGTPRC
- IGC_MGTPTC
- IGC_MIN_ITR_USECS
- IGC_MIN_RXD
- IGC_MIN_TXD
- IGC_MMDAAD
- IGC_MMDAC
- IGC_MMDAC_FUNC_DATA
- IGC_MPC
- IGC_MPRC
- IGC_MPTC
- IGC_MRQC
- IGC_MRQC_ENABLE_RSS_MQ
- IGC_MRQC_RSS_FIELD_IPV4
- IGC_MRQC_RSS_FIELD_IPV4_TCP
- IGC_MRQC_RSS_FIELD_IPV4_UDP
- IGC_MRQC_RSS_FIELD_IPV6
- IGC_MRQC_RSS_FIELD_IPV6_TCP
- IGC_MRQC_RSS_FIELD_IPV6_TCP_EX
- IGC_MRQC_RSS_FIELD_IPV6_UDP
- IGC_MTA
- IGC_N0_QUEUE
- IGC_NETDEV_STAT
- IGC_NETDEV_STATS_LEN
- IGC_NVM_GRANT_ATTEMPTS
- IGC_NVM_POLL_READ
- IGC_NVM_RW_ADDR_SHIFT
- IGC_NVM_RW_REG_DATA
- IGC_NVM_RW_REG_DONE
- IGC_NVM_RW_REG_START
- IGC_PBACL
- IGC_PBA_34K
- IGC_PQGPTC
- IGC_PRC1023
- IGC_PRC127
- IGC_PRC1522
- IGC_PRC255
- IGC_PRC511
- IGC_PRC64
- IGC_PRIV_FLAGS_LEGACY_RX
- IGC_PRIV_FLAGS_STR_LEN
- IGC_PSRTYPE
- IGC_PTC1023
- IGC_PTC127
- IGC_PTC1522
- IGC_PTC255
- IGC_PTC511
- IGC_PTC64
- IGC_QUEUE_STATS_LEN
- IGC_QVECTOR_MASK
- IGC_RAH
- IGC_RAH_AV
- IGC_RAH_MAC_ADDR_LEN
- IGC_RAH_POOL_1
- IGC_RAL
- IGC_RAL_MAC_ADDR_LEN
- IGC_RAR_ENTRIES
- IGC_RCTL
- IGC_RCTL_BAM
- IGC_RCTL_CFIEN
- IGC_RCTL_DPF
- IGC_RCTL_EN
- IGC_RCTL_LBM_MAC
- IGC_RCTL_LBM_TCVR
- IGC_RCTL_LPE
- IGC_RCTL_MO_SHIFT
- IGC_RCTL_MPE
- IGC_RCTL_PMCF
- IGC_RCTL_RDMTS_HALF
- IGC_RCTL_RST
- IGC_RCTL_SBP
- IGC_RCTL_SECRC
- IGC_RCTL_SZ_256
- IGC_RCTL_UPE
- IGC_RDBAH
- IGC_RDBAL
- IGC_RDH
- IGC_RDLEN
- IGC_RDT
- IGC_REGS_LEN
- IGC_REMOVED
- IGC_RETA
- IGC_RETA_SIZE
- IGC_RFC
- IGC_RFCTL
- IGC_RFCTL_IPV6_EX_DIS
- IGC_RFCTL_LEF
- IGC_RGB
- IGC_RING_FLAG_RX_3K_BUFFER
- IGC_RING_FLAG_RX_BUILD_SKB_ENABLED
- IGC_RING_FLAG_RX_LB_VLAN_BSWAP
- IGC_RING_FLAG_RX_SCTP_CSUM
- IGC_RING_FLAG_TX_CTX_IDX
- IGC_RING_FLAG_TX_DETECT_HANG
- IGC_RJC
- IGC_RLEC
- IGC_RLPML
- IGC_RNBC
- IGC_ROC
- IGC_RPTHC
- IGC_RQDPC
- IGC_RSSRK
- IGC_RUC
- IGC_RXBUFFER_2048
- IGC_RXBUFFER_256
- IGC_RXBUFFER_3072
- IGC_RXCSUM
- IGC_RXCSUM_CRCOFL
- IGC_RXCSUM_PCSD
- IGC_RXDCTL
- IGC_RXDCTL_QUEUE_ENABLE
- IGC_RXDEXT_ERR_FRAME_ERR_MASK
- IGC_RXDEXT_STATERR_CE
- IGC_RXDEXT_STATERR_CXE
- IGC_RXDEXT_STATERR_IPE
- IGC_RXDEXT_STATERR_RXE
- IGC_RXDEXT_STATERR_SE
- IGC_RXDEXT_STATERR_SEQ
- IGC_RXDEXT_STATERR_TCPE
- IGC_RXDMTC
- IGC_RXD_STAT_EOP
- IGC_RXERRC
- IGC_RXPBS
- IGC_RX_BUFFER_WRITE
- IGC_RX_DESC
- IGC_RX_DMA_ATTR
- IGC_RX_HDR_LEN
- IGC_RX_HTHRESH
- IGC_RX_PTHRESH
- IGC_RX_QUEUE_STATS_LEN
- IGC_RX_WTHRESH
- IGC_SCC
- IGC_SEC
- IGC_SKB_PAD
- IGC_SRRCTL
- IGC_SRRCTL_BSIZEHDRSIZE_SHIFT
- IGC_SRRCTL_BSIZEPKT_SHIFT
- IGC_SRRCTL_DESCTYPE_ADV_ONEBUF
- IGC_SRWR
- IGC_START_ITR
- IGC_STAT
- IGC_STATS_LEN
- IGC_STATUS
- IGC_STATUS_FD
- IGC_STATUS_FUNC_1
- IGC_STATUS_FUNC_MASK
- IGC_STATUS_FUNC_SHIFT
- IGC_STATUS_GIO_MASTER_ENABLE
- IGC_STATUS_LU
- IGC_STATUS_SPEED_100
- IGC_STATUS_SPEED_1000
- IGC_STATUS_SPEED_2500
- IGC_STATUS_TXOFF
- IGC_SUCCESS
- IGC_SWFW_EEP_SM
- IGC_SWFW_PHY0_SM
- IGC_SWSM
- IGC_SWSM_SMBI
- IGC_SWSM_SWESMBI
- IGC_SW_FW_SYNC
- IGC_SYMERRS
- IGC_TCTL
- IGC_TCTL_COLD
- IGC_TCTL_CT
- IGC_TCTL_EN
- IGC_TCTL_MULR
- IGC_TCTL_PSP
- IGC_TCTL_RTLC
- IGC_TDBAH
- IGC_TDBAL
- IGC_TDH
- IGC_TDLEN
- IGC_TDT
- IGC_TEST_LEN
- IGC_TIPG
- IGC_TNCRS
- IGC_TORH
- IGC_TORL
- IGC_TOTH
- IGC_TOTL
- IGC_TPR
- IGC_TPT
- IGC_TSCTC
- IGC_TSCTFC
- IGC_TS_HDR_LEN
- IGC_TXDCTL
- IGC_TXDCTL_QUEUE_ENABLE
- IGC_TXD_CMD_DEXT
- IGC_TXD_CMD_EOP
- IGC_TXD_CMD_IC
- IGC_TXD_CMD_IDE
- IGC_TXD_CMD_IFCS
- IGC_TXD_CMD_IP
- IGC_TXD_CMD_RPS
- IGC_TXD_CMD_RS
- IGC_TXD_CMD_TCP
- IGC_TXD_CMD_TSE
- IGC_TXD_CMD_VLE
- IGC_TXD_DCMD
- IGC_TXD_DTYP_C
- IGC_TXD_DTYP_D
- IGC_TXD_EXTCMD_TSTAMP
- IGC_TXD_POPTS_IXSM
- IGC_TXD_POPTS_TXSM
- IGC_TXD_STAT_DD
- IGC_TXD_STAT_EC
- IGC_TXD_STAT_LC
- IGC_TXD_STAT_TC
- IGC_TXD_STAT_TU
- IGC_TXPBS
- IGC_TX_CTXTDESC
- IGC_TX_DESC
- IGC_TX_FLAGS_CSUM
- IGC_TX_FLAGS_IPV4
- IGC_TX_FLAGS_TSO
- IGC_TX_FLAGS_TSTAMP
- IGC_TX_FLAGS_VLAN
- IGC_TX_FLAGS_VLAN_MASK
- IGC_TX_HTHRESH
- IGC_TX_PTHRESH
- IGC_TX_QUEUE_STATS_LEN
- IGC_TX_WTHRESH
- IGC_UTA
- IGC_VIG
- IGC_VLAPQF
- IGC_VLAPQF_P_VALID
- IGC_VLAPQF_QUEUE_MASK
- IGC_VLAPQF_QUEUE_SEL
- IGC_XOFFRXC
- IGC_XOFFTXC
- IGC_XONRXC
- IGC_XONTXC
- IGD_OPERATION_TIMEOUT
- IGEN_MESSAGE
- IGMPMSG_NOCACHE
- IGMPMSG_WHOLEPKT
- IGMPMSG_WRONGVIF
- IGMPMSG_WRVIFWHOLE
- IGMPV2_HOST_MEMBERSHIP_REPORT
- IGMPV3_ALLOW_NEW_SOURCES
- IGMPV3_ALL_MCR
- IGMPV3_BLOCK_OLD_SOURCES
- IGMPV3_CHANGE_TO_EXCLUDE
- IGMPV3_CHANGE_TO_INCLUDE
- IGMPV3_EXP
- IGMPV3_HOST_MEMBERSHIP_REPORT
- IGMPV3_MASK
- IGMPV3_MODE_IS_EXCLUDE
- IGMPV3_MODE_IS_INCLUDE
- IGMPV3_MRC
- IGMPV3_QQIC
- IGMP_AGE_THRESHOLD
- IGMP_ALL_HOSTS
- IGMP_ALL_ROUTER
- IGMP_AWAKENING_MEMBER
- IGMP_DELAYING_MEMBER
- IGMP_DVMRP
- IGMP_HOST_LEAVE_MESSAGE
- IGMP_HOST_MEMBERSHIP_QUERY
- IGMP_HOST_MEMBERSHIP_REPORT
- IGMP_IDLE_MEMBER
- IGMP_INITIAL_REPORT_DELAY
- IGMP_LAZY_MEMBER
- IGMP_LOCAL_GROUP
- IGMP_LOCAL_GROUP_MASK
- IGMP_MAX_HOST_REPORT_DELAY
- IGMP_MINLEN
- IGMP_MRDISC_ADV
- IGMP_MTRACE
- IGMP_MTRACE_RESP
- IGMP_PIM
- IGMP_QUERY_INTERVAL
- IGMP_QUERY_RESPONSE_INTERVAL
- IGMP_SIZE
- IGMP_SLEEPING_MEMBER
- IGMP_TIMER_SCALE
- IGMP_TRACE
- IGMP_V1_SEEN
- IGMP_V2_SEEN
- IGMP_V2_UNSOLICITED_REPORT_INTERVAL
- IGMP_V3_UNSOLICITED_REPORT_INTERVAL
- IGN
- IGN1_EN
- IGN2_EN
- IGNBRK
- IGNCR
- IGNLABEL
- IGNORED_IRQS
- IGNORE_2STEP
- IGNORE_ADD_NACK
- IGNORE_ALL
- IGNORE_ARGS
- IGNORE_BREAK
- IGNORE_BULK_OUT
- IGNORE_B_SCAN
- IGNORE_CASE
- IGNORE_CASE_BOOL
- IGNORE_CCR
- IGNORE_DEV
- IGNORE_DEVICE
- IGNORE_ECC_DONE
- IGNORE_ECC_DONE__FLAG
- IGNORE_FIFO_AVAILABILITY
- IGNORE_GPR
- IGNORE_INTR
- IGNORE_INTS
- IGNORE_IOCTL
- IGNORE_IRQ
- IGNORE_JOB
- IGNORE_NEXT_INT
- IGNORE_PCI_BOOT_CONFIG_DSM
- IGNORE_PFN0
- IGNORE_PS_FAIL_DURING_SCAN
- IGNORE_SEQ_ASSOC
- IGNORE_TDO
- IGNORE_TIMEOUT
- IGNORE_UNUSED_VPI_VCI_BITS_SET
- IGNORE_VISIBILITY
- IGNORE_W1C_MASK
- IGNORE_WIDE_RESIDUE
- IGNORE_XER
- IGNPAR
- IGN_RAW_FL
- IGP01E1000_AGC_LENGTH_SHIFT
- IGP01E1000_AGC_LENGTH_TABLE_SIZE
- IGP01E1000_AGC_RANGE
- IGP01E1000_ANALOG_FUSE_BYPASS
- IGP01E1000_ANALOG_FUSE_COARSE_10
- IGP01E1000_ANALOG_FUSE_COARSE_MASK
- IGP01E1000_ANALOG_FUSE_COARSE_THRESH
- IGP01E1000_ANALOG_FUSE_CONTROL
- IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL
- IGP01E1000_ANALOG_FUSE_FINE_1
- IGP01E1000_ANALOG_FUSE_FINE_10
- IGP01E1000_ANALOG_FUSE_FINE_MASK
- IGP01E1000_ANALOG_FUSE_POLY_MASK
- IGP01E1000_ANALOG_FUSE_STATUS
- IGP01E1000_ANALOG_REGS_PAGE
- IGP01E1000_ANALOG_SPARE_FUSE_ENABLED
- IGP01E1000_ANALOG_SPARE_FUSE_STATUS
- IGP01E1000_GMII_FIFO
- IGP01E1000_GMII_FLEX_SPD
- IGP01E1000_GMII_SPD
- IGP01E1000_IEEE_FORCE_GIGA
- IGP01E1000_IEEE_REGS_PAGE
- IGP01E1000_IEEE_RESTART_AUTONEG
- IGP01E1000_I_PHY_ID
- IGP01E1000_MSE_CHANNEL_A
- IGP01E1000_MSE_CHANNEL_B
- IGP01E1000_MSE_CHANNEL_C
- IGP01E1000_MSE_CHANNEL_D
- IGP01E1000_PHY_AGC_A
- IGP01E1000_PHY_AGC_B
- IGP01E1000_PHY_AGC_C
- IGP01E1000_PHY_AGC_D
- IGP01E1000_PHY_AGC_PARAM_A
- IGP01E1000_PHY_AGC_PARAM_B
- IGP01E1000_PHY_AGC_PARAM_C
- IGP01E1000_PHY_AGC_PARAM_D
- IGP01E1000_PHY_ANALOG_CLASS_A
- IGP01E1000_PHY_ANALOG_TX_STATE
- IGP01E1000_PHY_CHANNEL_NUM
- IGP01E1000_PHY_CHANNEL_QUALITY
- IGP01E1000_PHY_DSP_FFE
- IGP01E1000_PHY_DSP_FFE_CM_CP
- IGP01E1000_PHY_DSP_FFE_DEFAULT
- IGP01E1000_PHY_DSP_RESET
- IGP01E1000_PHY_DSP_SET
- IGP01E1000_PHY_EDAC_MU_INDEX
- IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS
- IGP01E1000_PHY_FORCE_ANALOG_ENABLE
- IGP01E1000_PHY_LINK_HEALTH
- IGP01E1000_PHY_PAGE_SELECT
- IGP01E1000_PHY_PCS_CTRL_REG
- IGP01E1000_PHY_PCS_INIT_REG
- IGP01E1000_PHY_POLARITY_MASK
- IGP01E1000_PHY_PORT_CONFIG
- IGP01E1000_PHY_PORT_CTRL
- IGP01E1000_PHY_PORT_STATUS
- IGP01E1000_PLHR_AUTONEG_ACTIVE
- IGP01E1000_PLHR_AUTONEG_FAULT
- IGP01E1000_PLHR_DATA_ERR_0
- IGP01E1000_PLHR_DATA_ERR_1
- IGP01E1000_PLHR_GIG_REM_RCVR_NOK
- IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR
- IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW
- IGP01E1000_PLHR_MASTER_FAULT
- IGP01E1000_PLHR_MASTER_RESOLUTION
- IGP01E1000_PLHR_SS_DOWNGRADE
- IGP01E1000_PLHR_VALID_CHANNEL_A
- IGP01E1000_PLHR_VALID_CHANNEL_B
- IGP01E1000_PLHR_VALID_CHANNEL_C
- IGP01E1000_PLHR_VALID_CHANNEL_D
- IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT
- IGP01E1000_PSCFR_DISABLE_JABBER
- IGP01E1000_PSCFR_DISABLE_TPLOOPBACK
- IGP01E1000_PSCFR_DISABLE_TRANSMIT
- IGP01E1000_PSCFR_PRE_EN
- IGP01E1000_PSCFR_SMART_SPEED
- IGP01E1000_PSCR_AUTO_MDIX
- IGP01E1000_PSCR_CORRECT_NC_SCMBLR
- IGP01E1000_PSCR_FLIP_CHIP
- IGP01E1000_PSCR_FORCE_MDI_MDIX
- IGP01E1000_PSCR_TEN_CRS_SELECT
- IGP01E1000_PSCR_TP_LOOPBACK
- IGP01E1000_PSSR_AUTONEG_FAILED
- IGP01E1000_PSSR_CABLE_LENGTH
- IGP01E1000_PSSR_CABLE_LENGTH_SHIFT
- IGP01E1000_PSSR_FULL_DUPLEX
- IGP01E1000_PSSR_LINK_UP
- IGP01E1000_PSSR_MDIX
- IGP01E1000_PSSR_MDIX_SHIFT
- IGP01E1000_PSSR_POLARITY_REVERSED
- IGP01E1000_PSSR_SPEED_1000MBPS
- IGP01E1000_PSSR_SPEED_100MBPS
- IGP01E1000_PSSR_SPEED_10MBPS
- IGP01E1000_PSSR_SPEED_MASK
- IGP02E1000_AGC_LENGTH_MASK
- IGP02E1000_AGC_LENGTH_SHIFT
- IGP02E1000_AGC_LENGTH_TABLE_SIZE
- IGP02E1000_AGC_RANGE
- IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- IGP02E1000_PHY_AGC_A
- IGP02E1000_PHY_AGC_B
- IGP02E1000_PHY_AGC_C
- IGP02E1000_PHY_AGC_D
- IGP02E1000_PHY_CHANNEL_NUM
- IGP02E1000_PHY_POWER_MGMT
- IGP02E1000_PM_D0_LPLU
- IGP02E1000_PM_D3_LPLU
- IGP02E1000_PM_SPD
- IGP03E1000_E_PHY_ID
- IGP3E1000_PHY_MISC_CTRL
- IGP3_CAPABILITY
- IGP3_CAP_8021PQ
- IGP3_CAP_AMT_CB
- IGP3_CAP_ASF
- IGP3_CAP_DC_AUTO_SPEED
- IGP3_CAP_INITIATE_TEAM
- IGP3_CAP_LPLU
- IGP3_CAP_MULT_QUEUE
- IGP3_CAP_RSS
- IGP3_CAP_SPD
- IGP3_CAP_WFM
- IGP3_KMRN_ACK_TIMEOUT
- IGP3_KMRN_DIAG
- IGP3_KMRN_DIAG_PCS_LOCK_LOSS
- IGP3_KMRN_EC_DIS_INBAND
- IGP3_KMRN_EXT_CTRL
- IGP3_KMRN_FIFO_CTRL_STATS
- IGP3_KMRN_INBAND_CTRL
- IGP3_KMRN_PMC_EE_IDLE_LINK_DIS
- IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK
- IGP3_KMRN_PMC_K0S_MODE1_EN_100
- IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA
- IGP3_KMRN_POWER_MNG_CTRL
- IGP3_PHY_MISC_DUPLEX_MANUAL_SET
- IGP3_PHY_PORT_CTRL
- IGP3_PHY_RATE_ADAPT_CTRL
- IGP3_PPC_JORDAN_EN
- IGP3_PPC_JORDAN_GIGA_SPEED
- IGP3_VR_CTRL
- IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
- IGP3_VR_CTRL_MODE_MASK
- IGP3_VR_CTRL_MODE_SHUT
- IGP3_VR_CTRL_MODE_SHUTDOWN
- IGP_ACTIVITY_LED_ENABLE
- IGP_ACTIVITY_LED_MASK
- IGP_CAP_FLAG_AC_CARD
- IGP_CAP_FLAG_DYNAMIC_CLOCK_EN
- IGP_CAP_FLAG_POSTDIV_BY_2_MODE
- IGP_CAP_FLAG_SDVO_CARD
- IGP_DDI_SLOT_ATTRIBUTE_MASK
- IGP_DDI_SLOT_CONFIG_REVERSED
- IGP_DDI_SLOT_CONNECTOR_TYPE_MASK
- IGP_DDI_SLOT_LANE_CONFIG_MASK
- IGP_LED3_MODE
- IGP_PAGE_SHIFT
- IGT21A_MSVLD
- IGTK_PN_LEN
- IGT_ATOMIC_H
- IGT_FLUSH_TEST_H
- IGT_IDLE_TIMEOUT
- IGT_LIVE_TEST_H
- IGT_TIMEOUT
- IGU_ACK_REGISTER_INTERRUPT_MODE
- IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT
- IGU_ACK_REGISTER_RESERVED
- IGU_ACK_REGISTER_RESERVED_SHIFT
- IGU_ACK_REGISTER_STATUS_BLOCK_ID
- IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT
- IGU_ACK_REGISTER_STORM_ID
- IGU_ACK_REGISTER_STORM_ID_SHIFT
- IGU_ACK_REGISTER_UPDATE_INDEX
- IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT
- IGU_ADDR_ATTN_BITS_CLR
- IGU_ADDR_ATTN_BITS_SET
- IGU_ADDR_ATTN_BITS_UPD
- IGU_ADDR_COALESCE_NOW
- IGU_ADDR_INT_ACK
- IGU_ADDR_MSIX
- IGU_ADDR_MSI_ADDR_HI
- IGU_ADDR_MSI_ADDR_LO
- IGU_ADDR_MSI_CTL
- IGU_ADDR_MSI_DATA
- IGU_ADDR_PROD_UPD
- IGU_ADDR_SIMD_MASK
- IGU_ADDR_SIMD_NOMASK
- IGU_ADDR_TYPE_MSIX_MEM
- IGU_ADDR_TYPE_READ_INT
- IGU_ADDR_TYPE_RESERVED
- IGU_ADDR_TYPE_WRITE_ATTN_BITS
- IGU_ADDR_TYPE_WRITE_INT_ACK
- IGU_ADDR_TYPE_WRITE_PBA
- IGU_ADDR_TYPE_WRITE_PROD_UPDATE
- IGU_BACKWARD_COMPATIBLE_BUPDATE
- IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT
- IGU_BACKWARD_COMPATIBLE_ENABLE_INT
- IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT
- IGU_BACKWARD_COMPATIBLE_RESERVED_0
- IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT
- IGU_BACKWARD_COMPATIBLE_SB_INDEX
- IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT
- IGU_BACKWARD_COMPATIBLE_SB_SELECT
- IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT
- IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS
- IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT
- IGU_BC_BASE_DSB_PROD
- IGU_BC_DSB_NUM_SEGS
- IGU_BC_NDSB_NUM_SEGS
- IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
- IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
- IGU_CLEANUP_CLEANUP_SET_MASK
- IGU_CLEANUP_CLEANUP_SET_SHIFT
- IGU_CLEANUP_CLEANUP_TYPE_MASK
- IGU_CLEANUP_CLEANUP_TYPE_SHIFT
- IGU_CLEANUP_COMMAND_TYPE_MASK
- IGU_CLEANUP_COMMAND_TYPE_SHIFT
- IGU_CLEANUP_RESERVED0_MASK
- IGU_CLEANUP_RESERVED0_SHIFT
- IGU_CLEANUP_SLEEP_LENGTH
- IGU_CMD_ATTN_BIT_CLR_UPPER
- IGU_CMD_ATTN_BIT_SET_UPPER
- IGU_CMD_ATTN_BIT_UPD_UPPER
- IGU_CMD_BACKWARD_COMP_PROD_UPD
- IGU_CMD_E2_PROD_UPD_BASE
- IGU_CMD_E2_PROD_UPD_RESERVED_UPPER
- IGU_CMD_E2_PROD_UPD_UPPER
- IGU_CMD_INT_ACK_BASE
- IGU_CMD_INT_ACK_RESERVED_UPPER
- IGU_CMD_INT_ACK_UPPER
- IGU_CMD_PROD_UPD_BASE
- IGU_CMD_PROD_UPD_RESERVED_UPPER
- IGU_CMD_PROD_UPD_UPPER
- IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK
- IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT
- IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK
- IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT
- IGU_COMMAND_REG_CTRL_RESERVED_MASK
- IGU_COMMAND_REG_CTRL_RESERVED_SHIFT
- IGU_COMMAND_TYPE_NOP
- IGU_COMMAND_TYPE_SET
- IGU_CTRL_CMD_TYPE_RD
- IGU_CTRL_CMD_TYPE_WR
- IGU_CTRL_REG_ADDRESS
- IGU_CTRL_REG_ADDRESS_SHIFT
- IGU_CTRL_REG_FID
- IGU_CTRL_REG_FID_MASK
- IGU_CTRL_REG_FID_SHIFT
- IGU_CTRL_REG_PXP_ADDR_MASK
- IGU_CTRL_REG_PXP_ADDR_SHIFT
- IGU_CTRL_REG_RESERVED
- IGU_CTRL_REG_RESERVED_MASK
- IGU_CTRL_REG_RESERVED_SHIFT
- IGU_CTRL_REG_TYPE
- IGU_CTRL_REG_TYPE_MASK
- IGU_CTRL_REG_TYPE_SHIFT
- IGU_CTRL_REG_UNUSED
- IGU_CTRL_REG_UNUSED_SHIFT
- IGU_ENTRY_SIZE
- IGU_FID
- IGU_FID_ENCODE_IS_PF
- IGU_FID_ENCODE_IS_PF_SHIFT
- IGU_FID_PF_NUM_MASK
- IGU_FID_VF_NUM_MASK
- IGU_FIFO
- IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_MASK
- IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_SHIFT
- IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_MASK
- IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_SHIFT
- IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_MASK
- IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_SHIFT
- IGU_FIFO_CLEANUP_WR_DATA_RESERVED_MASK
- IGU_FIFO_CLEANUP_WR_DATA_RESERVED_SHIFT
- IGU_FIFO_DEPTH_DWORDS
- IGU_FIFO_DEPTH_ELEMENTS
- IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_MASK
- IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_SHIFT
- IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_MASK
- IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_SHIFT
- IGU_FIFO_ELEMENT_DWORD0_FID_MASK
- IGU_FIFO_ELEMENT_DWORD0_FID_SHIFT
- IGU_FIFO_ELEMENT_DWORD0_IS_PF_MASK
- IGU_FIFO_ELEMENT_DWORD0_IS_PF_SHIFT
- IGU_FIFO_ELEMENT_DWORD0_SOURCE_MASK
- IGU_FIFO_ELEMENT_DWORD0_SOURCE_SHIFT
- IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_MASK
- IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_SHIFT
- IGU_FIFO_ELEMENT_DWORD12_WR_DATA_MASK
- IGU_FIFO_ELEMENT_DWORD12_WR_DATA_SHIFT
- IGU_FIFO_ELEMENT_DWORDS
- IGU_FIFO_WR_DATA_CMD_TYPE_MASK
- IGU_FIFO_WR_DATA_CMD_TYPE_SHIFT
- IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_MASK
- IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_SHIFT
- IGU_FIFO_WR_DATA_PROD_CONS_MASK
- IGU_FIFO_WR_DATA_PROD_CONS_SHIFT
- IGU_FIFO_WR_DATA_SEGMENT_MASK
- IGU_FIFO_WR_DATA_SEGMENT_SHIFT
- IGU_FIFO_WR_DATA_TIMER_MASK_MASK
- IGU_FIFO_WR_DATA_TIMER_MASK_SHIFT
- IGU_FIFO_WR_DATA_UPDATE_FLAG_MASK
- IGU_FIFO_WR_DATA_UPDATE_FLAG_SHIFT
- IGU_FUNC_BASE
- IGU_INT_DISABLE
- IGU_INT_ENABLE
- IGU_INT_NOP
- IGU_INT_NOP2
- IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK
- IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT
- IGU_MAPPING_LINE_IPS_GROUP_MASK
- IGU_MAPPING_LINE_IPS_GROUP_SHIFT
- IGU_MAPPING_LINE_PF_VALID_MASK
- IGU_MAPPING_LINE_PF_VALID_SHIFT
- IGU_MAPPING_LINE_RESERVED_MASK
- IGU_MAPPING_LINE_RESERVED_SHIFT
- IGU_MAPPING_LINE_VALID_MASK
- IGU_MAPPING_LINE_VALID_SHIFT
- IGU_MAPPING_LINE_VECTOR_NUMBER_MASK
- IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT
- IGU_MEM_BASE
- IGU_MEM_MSIX_BASE
- IGU_MEM_MSIX_RESERVED_UPPER
- IGU_MEM_MSIX_UPPER
- IGU_MEM_PBA_MSIX_BASE
- IGU_MEM_PBA_MSIX_RESERVED_UPPER
- IGU_MEM_PBA_MSIX_UPPER
- IGU_MSIX_VECTOR_MASK_BIT_MASK
- IGU_MSIX_VECTOR_MASK_BIT_SHIFT
- IGU_MSIX_VECTOR_RESERVED0_MASK
- IGU_MSIX_VECTOR_RESERVED0_SHIFT
- IGU_MSIX_VECTOR_RESERVED1_MASK
- IGU_MSIX_VECTOR_RESERVED1_SHIFT
- IGU_MSIX_VECTOR_STEERING_TAG_MASK
- IGU_MSIX_VECTOR_STEERING_TAG_SHIFT
- IGU_NORM_BASE_DSB_PROD
- IGU_NORM_DSB_NUM_SEGS
- IGU_NORM_NDSB_NUM_SEGS
- IGU_PF_CONF_ATTN_BIT_EN
- IGU_PF_CONF_FUNC_EN
- IGU_PF_CONF_INT_LINE_EN
- IGU_PF_CONF_MSI_MSIX_EN
- IGU_PF_CONF_SIMD_MODE
- IGU_PF_CONF_SINGLE_ISR_EN
- IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK
- IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT
- IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK
- IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT
- IGU_PROD_CONS_UPDATE_RESERVED0_MASK
- IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT
- IGU_PROD_CONS_UPDATE_SB_INDEX_MASK
- IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT
- IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK
- IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT
- IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK
- IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT
- IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK
- IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT
- IGU_REGULAR_BCLEANUP
- IGU_REGULAR_BCLEANUP_SHIFT
- IGU_REGULAR_BUPDATE
- IGU_REGULAR_BUPDATE_SHIFT
- IGU_REGULAR_CLEANUP_SET
- IGU_REGULAR_CLEANUP_SET_SHIFT
- IGU_REGULAR_CLEANUP_TYPE
- IGU_REGULAR_CLEANUP_TYPE_SHIFT
- IGU_REGULAR_ENABLE_INT
- IGU_REGULAR_ENABLE_INT_SHIFT
- IGU_REGULAR_RESERVED0
- IGU_REGULAR_RESERVED0_SHIFT
- IGU_REGULAR_RESERVED_1
- IGU_REGULAR_RESERVED_1_SHIFT
- IGU_REGULAR_SB_INDEX
- IGU_REGULAR_SB_INDEX_SHIFT
- IGU_REGULAR_SEGMENT_ACCESS
- IGU_REGULAR_SEGMENT_ACCESS_SHIFT
- IGU_REG_ATTENTION_ACK_BITS
- IGU_REG_ATTENTION_ENABLE
- IGU_REG_ATTN_FSM
- IGU_REG_ATTN_MSG_ADDR_H
- IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET
- IGU_REG_ATTN_MSG_ADDR_L
- IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET
- IGU_REG_ATTN_WRITE_DONE_PENDING
- IGU_REG_BLOCK_CONFIGURATION
- IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN
- IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN
- IGU_REG_CLEANUP_STATUS_0
- IGU_REG_CLEANUP_STATUS_1
- IGU_REG_CLEANUP_STATUS_2
- IGU_REG_CLEANUP_STATUS_3
- IGU_REG_CLEANUP_STATUS_4
- IGU_REG_COMMAND_REG_32LSB_DATA
- IGU_REG_COMMAND_REG_CTRL
- IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
- IGU_REG_CTRL_FSM
- IGU_REG_DBG_DWORD_ENABLE
- IGU_REG_DBG_FORCE_FRAME
- IGU_REG_DBG_FORCE_VALID
- IGU_REG_DBG_SELECT
- IGU_REG_DBG_SHIFT
- IGU_REG_ERROR_HANDLING_DATA_VALID
- IGU_REG_ERROR_HANDLING_MEMORY
- IGU_REG_IGU_PRTY_MASK
- IGU_REG_IGU_PRTY_STS
- IGU_REG_IGU_PRTY_STS_CLR
- IGU_REG_INT_HANDLE_FSM
- IGU_REG_LEADING_EDGE_LATCH
- IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET
- IGU_REG_MAPPING_MEMORY
- IGU_REG_MAPPING_MEMORY_FID_MASK
- IGU_REG_MAPPING_MEMORY_FID_SHIFT
- IGU_REG_MAPPING_MEMORY_SIZE
- IGU_REG_MAPPING_MEMORY_VALID
- IGU_REG_MAPPING_MEMORY_VECTOR_MASK
- IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT
- IGU_REG_PBA_STATUS_LSB
- IGU_REG_PBA_STATUS_MSB
- IGU_REG_PCI_PF_MSIX_EN
- IGU_REG_PCI_PF_MSIX_FUNC_MASK
- IGU_REG_PCI_PF_MSI_EN
- IGU_REG_PENDING_BITS_STATUS
- IGU_REG_PF_CONFIGURATION
- IGU_REG_PF_CONFIGURATION_RT_OFFSET
- IGU_REG_PROD_CONS_MEMORY
- IGU_REG_PXP_ARB_FSM
- IGU_REG_RESERVED_UPPER
- IGU_REG_RESET_MEMORIES
- IGU_REG_SB_CTRL_FSM
- IGU_REG_SB_INT_BEFORE_MASK_LSB
- IGU_REG_SB_INT_BEFORE_MASK_MSB
- IGU_REG_SB_MASK_LSB
- IGU_REG_SB_MASK_MSB
- IGU_REG_SILENT_DROP
- IGU_REG_SISR_MDPC_WMASK_LSB_UPPER
- IGU_REG_SISR_MDPC_WMASK_MSB_UPPER
- IGU_REG_SISR_MDPC_WMASK_UPPER
- IGU_REG_SISR_MDPC_WOMASK_UPPER
- IGU_REG_STATISTIC_NUM_MESSAGE_SENT
- IGU_REG_STATISTIC_NUM_VF_MSG_SENT
- IGU_REG_TIMER_MASKING_VALUE
- IGU_REG_TRAILING_EDGE_LATCH
- IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET
- IGU_REG_VF_CONFIGURATION
- IGU_REG_VF_CONFIGURATION_RT_OFFSET
- IGU_REG_WRITE_DONE_PENDING
- IGU_SEG_ACCESS_ATTN
- IGU_SEG_ACCESS_DEF
- IGU_SEG_ACCESS_NORM
- IGU_SEG_ACCESS_REG
- IGU_SRC_ATTN
- IGU_SRC_CAU
- IGU_SRC_GRC
- IGU_SRC_PXP0
- IGU_SRC_PXP1
- IGU_SRC_PXP2
- IGU_SRC_PXP3
- IGU_SRC_PXP4
- IGU_SRC_PXP5
- IGU_SRC_PXP6
- IGU_SRC_PXP7
- IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
- IGU_USE_REGISTER_cstorm_type_1_sb_cleanup
- IGU_USE_REGISTER_ustorm_type_0_sb_cleanup
- IGU_USE_REGISTER_ustorm_type_1_sb_cleanup
- IGU_VEC
- IGU_VF_CONF_FUNC_EN
- IGU_VF_CONF_MSI_MSIX_EN
- IGU_VF_CONF_PARENT_MASK
- IGU_VF_CONF_PARENT_SHIFT
- IGU_VF_CONF_SINGLE_ISR_EN
- IG_Backup
- IG_Max
- IG_Restore
- IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK
- IG_VLAN_REWRITE_MODE_PASS_THRU
- IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN
- IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN
- IH
- IH2_BASE
- IHANDLE_VALID
- IHC_AA_DONE
- IHC_FRAME_DONE
- IHC_GET_SENSOR_NUM
- IHC_INTERRUPT_LINE_STATUS
- IHC_NOT_READY
- IHC_SET_FACE_MARK
- IHC_SET_SHOT_MARK
- IHDR
- IHIDDEN
- IHOST_IRQ_ENABLED
- IHOST_START_PENDING
- IHOST_STOP_PENDING
- IHR
- IH_ACTIVE_FCN_ID__PF_VF_MASK
- IH_ACTIVE_FCN_ID__PF_VF__SHIFT
- IH_ACTIVE_FCN_ID__RESERVED_MASK
- IH_ACTIVE_FCN_ID__RESERVED__SHIFT
- IH_ACTIVE_FCN_ID__VF_ID_MASK
- IH_ACTIVE_FCN_ID__VF_ID__SHIFT
- IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED_MASK
- IH_ADVFAULT_CNTL__NUM_FAULTS_DROPPED__SHIFT
- IH_ADVFAULT_CNTL__WAIT_TIMER_MASK
- IH_ADVFAULT_CNTL__WAIT_TIMER__SHIFT
- IH_ADVFAULT_CNTL__WATERMARK_ENABLE_MASK
- IH_ADVFAULT_CNTL__WATERMARK_ENABLE__SHIFT
- IH_ADVFAULT_CNTL__WATERMARK_MASK
- IH_ADVFAULT_CNTL__WATERMARK_REACHED_MASK
- IH_ADVFAULT_CNTL__WATERMARK_REACHED__SHIFT
- IH_ADVFAULT_CNTL__WATERMARK__SHIFT
- IH_BUSY
- IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK
- IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT
- IH_CHICKEN__CROSS_TRIGGER_ENABLE_MASK
- IH_CHICKEN__CROSS_TRIGGER_ENABLE__SHIFT
- IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK
- IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT
- IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK
- IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT
- IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK
- IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT
- IH_CHICKEN__REG_FIREWALL_ENABLE_MASK
- IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT
- IH_CID_REMAP_DATA__CLIENT_ID_MASK
- IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK
- IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT
- IH_CID_REMAP_DATA__CLIENT_ID__SHIFT
- IH_CID_REMAP_DATA__INITIATOR_ID_MASK
- IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT
- IH_CID_REMAP_INDEX__INDEX_MASK
- IH_CID_REMAP_INDEX__INDEX__SHIFT
- IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK
- IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT
- IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK
- IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT
- IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK
- IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT
- IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK
- IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT
- IH_CLIENT_CFG_DATA__RING_ID_MASK
- IH_CLIENT_CFG_DATA__RING_ID__SHIFT
- IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK
- IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT
- IH_CLIENT_CFG_INDEX__INDEX_MASK
- IH_CLIENT_CFG_INDEX__INDEX__SHIFT
- IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK
- IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLEAR_MASK
- IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT
- IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK
- IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT
- IH_CLIENT_ID
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ACP__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ATC__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__BIF__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ISP__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__RLC__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__ROM__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SAMMSP__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA1__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH1__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH2__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH3__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SH__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SRBM__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__UVD__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE0__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VCE1__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__VMC__SHIFT
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA_MASK
- IH_CLIENT_MAY_SEND_INCOMPLETE_INT__XDMA__SHIFT
- IH_CLIENT_TYPE
- IH_CLIENT_TYPE_RESERVED
- IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT
- IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT
- IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT
- IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT
- IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT
- IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK
- IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT
- IH_CNTL
- IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK
- IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT
- IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK
- IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT
- IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK
- IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT
- IH_CNTL__ENABLE_INTR_MASK
- IH_CNTL__ENABLE_INTR__SHIFT
- IH_CNTL__IH_FIFO_HIGHWATER_MASK
- IH_CNTL__IH_FIFO_HIGHWATER__SHIFT
- IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK
- IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT
- IH_CNTL__MC_FIFO_HIGHWATER_MASK
- IH_CNTL__MC_FIFO_HIGHWATER__SHIFT
- IH_CNTL__MC_SWAP_MASK
- IH_CNTL__MC_SWAP__SHIFT
- IH_CNTL__MC_TRAN_MASK
- IH_CNTL__MC_TRAN__SHIFT
- IH_CNTL__MC_VMID_MASK
- IH_CNTL__MC_VMID__SHIFT
- IH_CNTL__MC_WRREQ_CREDIT_MASK
- IH_CNTL__MC_WRREQ_CREDIT__SHIFT
- IH_CNTL__MC_WR_CLEAN_CNT_MASK
- IH_CNTL__MC_WR_CLEAN_CNT__SHIFT
- IH_CNTL__RPTR_REARM_MASK
- IH_CNTL__RPTR_REARM__SHIFT
- IH_CNTL__WPTR_WRITEBACK_TIMER_MASK
- IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT
- IH_COOKIE_0__CLIENT_ID_MASK
- IH_COOKIE_0__CLIENT_ID__SHIFT
- IH_COOKIE_0__RESERVED_MASK
- IH_COOKIE_0__RESERVED__SHIFT
- IH_COOKIE_0__RING_ID_MASK
- IH_COOKIE_0__RING_ID__SHIFT
- IH_COOKIE_0__SOURCE_ID_MASK
- IH_COOKIE_0__SOURCE_ID__SHIFT
- IH_COOKIE_0__VMID_TYPE_MASK
- IH_COOKIE_0__VMID_TYPE__SHIFT
- IH_COOKIE_0__VM_ID_MASK
- IH_COOKIE_0__VM_ID__SHIFT
- IH_COOKIE_1__TIMESTAMP_31_0_MASK
- IH_COOKIE_1__TIMESTAMP_31_0__SHIFT
- IH_COOKIE_2__RESERVED_MASK
- IH_COOKIE_2__RESERVED__SHIFT
- IH_COOKIE_2__TIMESTAMP_47_32_MASK
- IH_COOKIE_2__TIMESTAMP_47_32__SHIFT
- IH_COOKIE_2__TIMESTAMP_SRC_MASK
- IH_COOKIE_2__TIMESTAMP_SRC__SHIFT
- IH_COOKIE_3__PASID_SRC_MASK
- IH_COOKIE_3__PASID_SRC__SHIFT
- IH_COOKIE_3__PAS_ID_MASK
- IH_COOKIE_3__PAS_ID__SHIFT
- IH_COOKIE_3__RESERVED_MASK
- IH_COOKIE_3__RESERVED__SHIFT
- IH_COOKIE_4__CONTEXT_ID_31_0_MASK
- IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT
- IH_COOKIE_5__CONTEXT_ID_63_32_MASK
- IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT
- IH_COOKIE_6__CONTEXT_ID_95_64_MASK
- IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT
- IH_COOKIE_7__CONTEXT_ID_128_96_MASK
- IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT
- IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK
- IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT
- IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK
- IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT
- IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK
- IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT
- IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT
- IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK
- IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT
- IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE_MASK
- IH_DEBUG__MC_WR_FIFO_BLOCK_ENABLE__SHIFT
- IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK
- IH_DEBUG__RB_FULL_DRAIN_ENABLE__SHIFT
- IH_DEBUG__WPTR_OVERFLOW_ENABLE_MASK
- IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT
- IH_DOORBELL_RPTR_RING1__ENABLE_MASK
- IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT
- IH_DOORBELL_RPTR_RING1__OFFSET_MASK
- IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT
- IH_DOORBELL_RPTR_RING2__ENABLE_MASK
- IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT
- IH_DOORBELL_RPTR_RING2__OFFSET_MASK
- IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT
- IH_DOORBELL_RPTR__CAPTURED_MASK
- IH_DOORBELL_RPTR__CAPTURED__SHIFT
- IH_DOORBELL_RPTR__ENABLE_MASK
- IH_DOORBELL_RPTR__ENABLE__SHIFT
- IH_DOORBELL_RPTR__OFFSET_MASK
- IH_DOORBELL_RPTR__OFFSET__SHIFT
- IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK
- IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT
- IH_DSM_MATCH_FCN_ID__PF_VF_MASK
- IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT
- IH_DSM_MATCH_FCN_ID__VF_ID_MASK
- IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT
- IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK
- IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT
- IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK
- IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT
- IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK
- IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT
- IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK
- IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT
- IH_DUMMY_RD_EN
- IH_DUMMY_RD_OVERRIDE
- IH_GFX_VMID_CLIENT
- IH_GPIO_BASE
- IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK
- IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK
- IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK
- IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK
- IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK
- IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK
- IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__VF_MASK
- IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT
- IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK
- IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT
- IH_IB_SIZE
- IH_INTERFACE_TYPE
- IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK
- IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT
- IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK
- IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT
- IH_INT_DROP_CNTL__INT_DROPPED_MASK
- IH_INT_DROP_CNTL__INT_DROPPED__SHIFT
- IH_INT_DROP_CNTL__INT_DROP_EN_MASK
- IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT
- IH_INT_DROP_CNTL__INT_DROP_MODE_MASK
- IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT
- IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK
- IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT
- IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK
- IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT
- IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK
- IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT
- IH_INT_DROP_CNTL__VF_MATCH_EN_MASK
- IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT
- IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK
- IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT
- IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT
- IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT
- IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT
- IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT
- IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT
- IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK
- IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT
- IH_INT_FLAGS__CLIENT_0_FLAG_MASK
- IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_10_FLAG_MASK
- IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_11_FLAG_MASK
- IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_12_FLAG_MASK
- IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_13_FLAG_MASK
- IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_14_FLAG_MASK
- IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_15_FLAG_MASK
- IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_16_FLAG_MASK
- IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_17_FLAG_MASK
- IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_18_FLAG_MASK
- IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_19_FLAG_MASK
- IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_1_FLAG_MASK
- IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_20_FLAG_MASK
- IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_21_FLAG_MASK
- IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_22_FLAG_MASK
- IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_23_FLAG_MASK
- IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_24_FLAG_MASK
- IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_25_FLAG_MASK
- IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_26_FLAG_MASK
- IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_27_FLAG_MASK
- IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_28_FLAG_MASK
- IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_29_FLAG_MASK
- IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_2_FLAG_MASK
- IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_30_FLAG_MASK
- IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_31_FLAG_MASK
- IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_3_FLAG_MASK
- IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_4_FLAG_MASK
- IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_5_FLAG_MASK
- IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_6_FLAG_MASK
- IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_7_FLAG_MASK
- IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_8_FLAG_MASK
- IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT
- IH_INT_FLAGS__CLIENT_9_FLAG_MASK
- IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT
- IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK
- IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT
- IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK
- IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT
- IH_INT_FLOOD_CNTL__HIGHWATER_MASK
- IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK
- IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT
- IH_INT_FLOOD_STATUS__INT_DROPPED_MASK
- IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT
- IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK
- IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT
- IH_LAST_INT_INFO0__CLIENT_ID_MASK
- IH_LAST_INT_INFO0__CLIENT_ID__SHIFT
- IH_LAST_INT_INFO0__RING_ID_MASK
- IH_LAST_INT_INFO0__RING_ID__SHIFT
- IH_LAST_INT_INFO0__SOURCE_ID_MASK
- IH_LAST_INT_INFO0__SOURCE_ID__SHIFT
- IH_LAST_INT_INFO0__VMID_TYPE_MASK
- IH_LAST_INT_INFO0__VMID_TYPE__SHIFT
- IH_LAST_INT_INFO0__VM_ID_MASK
- IH_LAST_INT_INFO0__VM_ID__SHIFT
- IH_LAST_INT_INFO1__CONTEXT_ID_MASK
- IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT
- IH_LAST_INT_INFO2__PAS_ID_MASK
- IH_LAST_INT_INFO2__PAS_ID__SHIFT
- IH_LAST_INT_INFO2__VF_ID_MASK
- IH_LAST_INT_INFO2__VF_ID__SHIFT
- IH_LAST_INT_INFO2__VF_MASK
- IH_LAST_INT_INFO2__VF__SHIFT
- IH_LEGACY_INTERFACE
- IH_LEVEL_INTR_MASK__MASK_MASK
- IH_LEVEL_INTR_MASK__MASK__SHIFT
- IH_LEVEL_STATUS__BIF_STATUS_MASK
- IH_LEVEL_STATUS__BIF_STATUS__SHIFT
- IH_LEVEL_STATUS__DC_STATUS_MASK
- IH_LEVEL_STATUS__DC_STATUS__SHIFT
- IH_LEVEL_STATUS__ROM_STATUS_MASK
- IH_LEVEL_STATUS__ROM_STATUS__SHIFT
- IH_LEVEL_STATUS__SRBM_STATUS_MASK
- IH_LEVEL_STATUS__SRBM_STATUS__SHIFT
- IH_LEVEL_STATUS__XDMA_STATUS_MASK
- IH_LEVEL_STATUS__XDMA_STATUS__SHIFT
- IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK
- IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT
- IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK
- IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT
- IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK
- IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT
- IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK
- IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT
- IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK
- IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT
- IH_MC_SWAP
- IH_MC_SWAP_16BIT
- IH_MC_SWAP_32BIT
- IH_MC_SWAP_64BIT
- IH_MC_SWAP_NONE
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK
- IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT
- IH_MENELAUS_IRQS
- IH_MMHUB_CNTL__IV_TLVL_MASK
- IH_MMHUB_CNTL__IV_TLVL__SHIFT
- IH_MMHUB_CNTL__UNITID_MASK
- IH_MMHUB_CNTL__UNITID__SHIFT
- IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK
- IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT
- IH_MMHUB_ERROR__IH_BRESP_01_MASK
- IH_MMHUB_ERROR__IH_BRESP_01__SHIFT
- IH_MMHUB_ERROR__IH_BRESP_10_MASK
- IH_MMHUB_ERROR__IH_BRESP_10__SHIFT
- IH_MMHUB_ERROR__IH_BRESP_11_MASK
- IH_MMHUB_ERROR__IH_BRESP_11__SHIFT
- IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK
- IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT
- IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK
- IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT
- IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK
- IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT
- IH_MM_VMID_CLIENT
- IH_MPUIO_BASE
- IH_MULTI_VMID_CLIENT
- IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK
- IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT
- IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK
- IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT
- IH_PERFMON_CNTL__CLEAR0_MASK
- IH_PERFMON_CNTL__CLEAR0__SHIFT
- IH_PERFMON_CNTL__CLEAR1_MASK
- IH_PERFMON_CNTL__CLEAR1__SHIFT
- IH_PERFMON_CNTL__ENABLE0_MASK
- IH_PERFMON_CNTL__ENABLE0__SHIFT
- IH_PERFMON_CNTL__ENABLE1_MASK
- IH_PERFMON_CNTL__ENABLE1__SHIFT
- IH_PERFMON_CNTL__PERF_SEL0_MASK
- IH_PERFMON_CNTL__PERF_SEL0__SHIFT
- IH_PERFMON_CNTL__PERF_SEL1_MASK
- IH_PERFMON_CNTL__PERF_SEL1__SHIFT
- IH_PERF_SEL
- IH_PERF_SEL_BIF_FALLING
- IH_PERF_SEL_BIF_FALLING_VF0
- IH_PERF_SEL_BIF_FALLING_VF1
- IH_PERF_SEL_BIF_FALLING_VF10
- IH_PERF_SEL_BIF_FALLING_VF11
- IH_PERF_SEL_BIF_FALLING_VF12
- IH_PERF_SEL_BIF_FALLING_VF13
- IH_PERF_SEL_BIF_FALLING_VF14
- IH_PERF_SEL_BIF_FALLING_VF15
- IH_PERF_SEL_BIF_FALLING_VF2
- IH_PERF_SEL_BIF_FALLING_VF3
- IH_PERF_SEL_BIF_FALLING_VF4
- IH_PERF_SEL_BIF_FALLING_VF5
- IH_PERF_SEL_BIF_FALLING_VF6
- IH_PERF_SEL_BIF_FALLING_VF7
- IH_PERF_SEL_BIF_FALLING_VF8
- IH_PERF_SEL_BIF_FALLING_VF9
- IH_PERF_SEL_BIF_LINE0_FALLING
- IH_PERF_SEL_BIF_LINE0_FALLING_VF0
- IH_PERF_SEL_BIF_LINE0_FALLING_VF1
- IH_PERF_SEL_BIF_LINE0_FALLING_VF10
- IH_PERF_SEL_BIF_LINE0_FALLING_VF11
- IH_PERF_SEL_BIF_LINE0_FALLING_VF12
- IH_PERF_SEL_BIF_LINE0_FALLING_VF13
- IH_PERF_SEL_BIF_LINE0_FALLING_VF14
- IH_PERF_SEL_BIF_LINE0_FALLING_VF15
- IH_PERF_SEL_BIF_LINE0_FALLING_VF16
- IH_PERF_SEL_BIF_LINE0_FALLING_VF17
- IH_PERF_SEL_BIF_LINE0_FALLING_VF18
- IH_PERF_SEL_BIF_LINE0_FALLING_VF19
- IH_PERF_SEL_BIF_LINE0_FALLING_VF2
- IH_PERF_SEL_BIF_LINE0_FALLING_VF20
- IH_PERF_SEL_BIF_LINE0_FALLING_VF21
- IH_PERF_SEL_BIF_LINE0_FALLING_VF22
- IH_PERF_SEL_BIF_LINE0_FALLING_VF23
- IH_PERF_SEL_BIF_LINE0_FALLING_VF24
- IH_PERF_SEL_BIF_LINE0_FALLING_VF25
- IH_PERF_SEL_BIF_LINE0_FALLING_VF26
- IH_PERF_SEL_BIF_LINE0_FALLING_VF27
- IH_PERF_SEL_BIF_LINE0_FALLING_VF28
- IH_PERF_SEL_BIF_LINE0_FALLING_VF29
- IH_PERF_SEL_BIF_LINE0_FALLING_VF3
- IH_PERF_SEL_BIF_LINE0_FALLING_VF30
- IH_PERF_SEL_BIF_LINE0_FALLING_VF4
- IH_PERF_SEL_BIF_LINE0_FALLING_VF5
- IH_PERF_SEL_BIF_LINE0_FALLING_VF6
- IH_PERF_SEL_BIF_LINE0_FALLING_VF7
- IH_PERF_SEL_BIF_LINE0_FALLING_VF8
- IH_PERF_SEL_BIF_LINE0_FALLING_VF9
- IH_PERF_SEL_BIF_LINE0_RISING
- IH_PERF_SEL_BIF_LINE0_RISING_VF0
- IH_PERF_SEL_BIF_LINE0_RISING_VF1
- IH_PERF_SEL_BIF_LINE0_RISING_VF10
- IH_PERF_SEL_BIF_LINE0_RISING_VF11
- IH_PERF_SEL_BIF_LINE0_RISING_VF12
- IH_PERF_SEL_BIF_LINE0_RISING_VF13
- IH_PERF_SEL_BIF_LINE0_RISING_VF14
- IH_PERF_SEL_BIF_LINE0_RISING_VF15
- IH_PERF_SEL_BIF_LINE0_RISING_VF16
- IH_PERF_SEL_BIF_LINE0_RISING_VF17
- IH_PERF_SEL_BIF_LINE0_RISING_VF18
- IH_PERF_SEL_BIF_LINE0_RISING_VF19
- IH_PERF_SEL_BIF_LINE0_RISING_VF2
- IH_PERF_SEL_BIF_LINE0_RISING_VF20
- IH_PERF_SEL_BIF_LINE0_RISING_VF21
- IH_PERF_SEL_BIF_LINE0_RISING_VF22
- IH_PERF_SEL_BIF_LINE0_RISING_VF23
- IH_PERF_SEL_BIF_LINE0_RISING_VF24
- IH_PERF_SEL_BIF_LINE0_RISING_VF25
- IH_PERF_SEL_BIF_LINE0_RISING_VF26
- IH_PERF_SEL_BIF_LINE0_RISING_VF27
- IH_PERF_SEL_BIF_LINE0_RISING_VF28
- IH_PERF_SEL_BIF_LINE0_RISING_VF29
- IH_PERF_SEL_BIF_LINE0_RISING_VF3
- IH_PERF_SEL_BIF_LINE0_RISING_VF30
- IH_PERF_SEL_BIF_LINE0_RISING_VF4
- IH_PERF_SEL_BIF_LINE0_RISING_VF5
- IH_PERF_SEL_BIF_LINE0_RISING_VF6
- IH_PERF_SEL_BIF_LINE0_RISING_VF7
- IH_PERF_SEL_BIF_LINE0_RISING_VF8
- IH_PERF_SEL_BIF_LINE0_RISING_VF9
- IH_PERF_SEL_BIF_RISING
- IH_PERF_SEL_BIF_RISING_VF0
- IH_PERF_SEL_BIF_RISING_VF1
- IH_PERF_SEL_BIF_RISING_VF10
- IH_PERF_SEL_BIF_RISING_VF11
- IH_PERF_SEL_BIF_RISING_VF12
- IH_PERF_SEL_BIF_RISING_VF13
- IH_PERF_SEL_BIF_RISING_VF14
- IH_PERF_SEL_BIF_RISING_VF15
- IH_PERF_SEL_BIF_RISING_VF2
- IH_PERF_SEL_BIF_RISING_VF3
- IH_PERF_SEL_BIF_RISING_VF4
- IH_PERF_SEL_BIF_RISING_VF5
- IH_PERF_SEL_BIF_RISING_VF6
- IH_PERF_SEL_BIF_RISING_VF7
- IH_PERF_SEL_BIF_RISING_VF8
- IH_PERF_SEL_BIF_RISING_VF9
- IH_PERF_SEL_BUFFER_FIFO_FULL
- IH_PERF_SEL_BUFFER_IDLE
- IH_PERF_SEL_CLIENT0_IH_STALL
- IH_PERF_SEL_CLIENT0_INT
- IH_PERF_SEL_CLIENT10_IH_STALL
- IH_PERF_SEL_CLIENT10_INT
- IH_PERF_SEL_CLIENT11_IH_STALL
- IH_PERF_SEL_CLIENT11_INT
- IH_PERF_SEL_CLIENT12_IH_STALL
- IH_PERF_SEL_CLIENT12_INT
- IH_PERF_SEL_CLIENT13_IH_STALL
- IH_PERF_SEL_CLIENT13_INT
- IH_PERF_SEL_CLIENT14_IH_STALL
- IH_PERF_SEL_CLIENT14_INT
- IH_PERF_SEL_CLIENT15_IH_STALL
- IH_PERF_SEL_CLIENT15_INT
- IH_PERF_SEL_CLIENT16_IH_STALL
- IH_PERF_SEL_CLIENT16_INT
- IH_PERF_SEL_CLIENT17_IH_STALL
- IH_PERF_SEL_CLIENT17_INT
- IH_PERF_SEL_CLIENT18_IH_STALL
- IH_PERF_SEL_CLIENT18_INT
- IH_PERF_SEL_CLIENT19_IH_STALL
- IH_PERF_SEL_CLIENT19_INT
- IH_PERF_SEL_CLIENT1_IH_STALL
- IH_PERF_SEL_CLIENT1_INT
- IH_PERF_SEL_CLIENT20_IH_STALL
- IH_PERF_SEL_CLIENT20_INT
- IH_PERF_SEL_CLIENT21_IH_STALL
- IH_PERF_SEL_CLIENT21_INT
- IH_PERF_SEL_CLIENT22_IH_STALL
- IH_PERF_SEL_CLIENT22_INT
- IH_PERF_SEL_CLIENT23_IH_STALL
- IH_PERF_SEL_CLIENT23_INT
- IH_PERF_SEL_CLIENT24_INT
- IH_PERF_SEL_CLIENT25_INT
- IH_PERF_SEL_CLIENT26_INT
- IH_PERF_SEL_CLIENT27_INT
- IH_PERF_SEL_CLIENT28_INT
- IH_PERF_SEL_CLIENT29_INT
- IH_PERF_SEL_CLIENT2_IH_STALL
- IH_PERF_SEL_CLIENT2_INT
- IH_PERF_SEL_CLIENT30_INT
- IH_PERF_SEL_CLIENT31_INT
- IH_PERF_SEL_CLIENT3_IH_STALL
- IH_PERF_SEL_CLIENT3_INT
- IH_PERF_SEL_CLIENT4_IH_STALL
- IH_PERF_SEL_CLIENT4_INT
- IH_PERF_SEL_CLIENT5_IH_STALL
- IH_PERF_SEL_CLIENT5_INT
- IH_PERF_SEL_CLIENT6_IH_STALL
- IH_PERF_SEL_CLIENT6_INT
- IH_PERF_SEL_CLIENT7_IH_STALL
- IH_PERF_SEL_CLIENT7_INT
- IH_PERF_SEL_CLIENT8_IH_STALL
- IH_PERF_SEL_CLIENT8_INT
- IH_PERF_SEL_CLIENT9_IH_STALL
- IH_PERF_SEL_CLIENT9_INT
- IH_PERF_SEL_CLIENT_CREDIT_ERROR
- IH_PERF_SEL_COOKIE_REC_ERROR
- IH_PERF_SEL_CYCLE
- IH_PERF_SEL_IDLE
- IH_PERF_SEL_INPUT_IDLE
- IH_PERF_SEL_MC_WR_CLEAN_PENDING
- IH_PERF_SEL_MC_WR_CLEAN_STALL
- IH_PERF_SEL_MC_WR_COUNT
- IH_PERF_SEL_MC_WR_IDLE
- IH_PERF_SEL_MC_WR_STALL
- IH_PERF_SEL_RB0_FULL
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8
- IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9
- IH_PERF_SEL_RB0_FULL_VF0
- IH_PERF_SEL_RB0_FULL_VF1
- IH_PERF_SEL_RB0_FULL_VF10
- IH_PERF_SEL_RB0_FULL_VF11
- IH_PERF_SEL_RB0_FULL_VF12
- IH_PERF_SEL_RB0_FULL_VF13
- IH_PERF_SEL_RB0_FULL_VF14
- IH_PERF_SEL_RB0_FULL_VF15
- IH_PERF_SEL_RB0_FULL_VF16
- IH_PERF_SEL_RB0_FULL_VF17
- IH_PERF_SEL_RB0_FULL_VF18
- IH_PERF_SEL_RB0_FULL_VF19
- IH_PERF_SEL_RB0_FULL_VF2
- IH_PERF_SEL_RB0_FULL_VF20
- IH_PERF_SEL_RB0_FULL_VF21
- IH_PERF_SEL_RB0_FULL_VF22
- IH_PERF_SEL_RB0_FULL_VF23
- IH_PERF_SEL_RB0_FULL_VF24
- IH_PERF_SEL_RB0_FULL_VF25
- IH_PERF_SEL_RB0_FULL_VF26
- IH_PERF_SEL_RB0_FULL_VF27
- IH_PERF_SEL_RB0_FULL_VF28
- IH_PERF_SEL_RB0_FULL_VF29
- IH_PERF_SEL_RB0_FULL_VF3
- IH_PERF_SEL_RB0_FULL_VF30
- IH_PERF_SEL_RB0_FULL_VF4
- IH_PERF_SEL_RB0_FULL_VF5
- IH_PERF_SEL_RB0_FULL_VF6
- IH_PERF_SEL_RB0_FULL_VF7
- IH_PERF_SEL_RB0_FULL_VF8
- IH_PERF_SEL_RB0_FULL_VF9
- IH_PERF_SEL_RB0_LOAD_RPTR
- IH_PERF_SEL_RB0_LOAD_RPTR_VF0
- IH_PERF_SEL_RB0_LOAD_RPTR_VF1
- IH_PERF_SEL_RB0_LOAD_RPTR_VF10
- IH_PERF_SEL_RB0_LOAD_RPTR_VF11
- IH_PERF_SEL_RB0_LOAD_RPTR_VF12
- IH_PERF_SEL_RB0_LOAD_RPTR_VF13
- IH_PERF_SEL_RB0_LOAD_RPTR_VF14
- IH_PERF_SEL_RB0_LOAD_RPTR_VF15
- IH_PERF_SEL_RB0_LOAD_RPTR_VF16
- IH_PERF_SEL_RB0_LOAD_RPTR_VF17
- IH_PERF_SEL_RB0_LOAD_RPTR_VF18
- IH_PERF_SEL_RB0_LOAD_RPTR_VF19
- IH_PERF_SEL_RB0_LOAD_RPTR_VF2
- IH_PERF_SEL_RB0_LOAD_RPTR_VF20
- IH_PERF_SEL_RB0_LOAD_RPTR_VF21
- IH_PERF_SEL_RB0_LOAD_RPTR_VF22
- IH_PERF_SEL_RB0_LOAD_RPTR_VF23
- IH_PERF_SEL_RB0_LOAD_RPTR_VF24
- IH_PERF_SEL_RB0_LOAD_RPTR_VF25
- IH_PERF_SEL_RB0_LOAD_RPTR_VF26
- IH_PERF_SEL_RB0_LOAD_RPTR_VF27
- IH_PERF_SEL_RB0_LOAD_RPTR_VF28
- IH_PERF_SEL_RB0_LOAD_RPTR_VF29
- IH_PERF_SEL_RB0_LOAD_RPTR_VF3
- IH_PERF_SEL_RB0_LOAD_RPTR_VF30
- IH_PERF_SEL_RB0_LOAD_RPTR_VF4
- IH_PERF_SEL_RB0_LOAD_RPTR_VF5
- IH_PERF_SEL_RB0_LOAD_RPTR_VF6
- IH_PERF_SEL_RB0_LOAD_RPTR_VF7
- IH_PERF_SEL_RB0_LOAD_RPTR_VF8
- IH_PERF_SEL_RB0_LOAD_RPTR_VF9
- IH_PERF_SEL_RB0_OVERFLOW
- IH_PERF_SEL_RB0_OVERFLOW_VF0
- IH_PERF_SEL_RB0_OVERFLOW_VF1
- IH_PERF_SEL_RB0_OVERFLOW_VF10
- IH_PERF_SEL_RB0_OVERFLOW_VF11
- IH_PERF_SEL_RB0_OVERFLOW_VF12
- IH_PERF_SEL_RB0_OVERFLOW_VF13
- IH_PERF_SEL_RB0_OVERFLOW_VF14
- IH_PERF_SEL_RB0_OVERFLOW_VF15
- IH_PERF_SEL_RB0_OVERFLOW_VF16
- IH_PERF_SEL_RB0_OVERFLOW_VF17
- IH_PERF_SEL_RB0_OVERFLOW_VF18
- IH_PERF_SEL_RB0_OVERFLOW_VF19
- IH_PERF_SEL_RB0_OVERFLOW_VF2
- IH_PERF_SEL_RB0_OVERFLOW_VF20
- IH_PERF_SEL_RB0_OVERFLOW_VF21
- IH_PERF_SEL_RB0_OVERFLOW_VF22
- IH_PERF_SEL_RB0_OVERFLOW_VF23
- IH_PERF_SEL_RB0_OVERFLOW_VF24
- IH_PERF_SEL_RB0_OVERFLOW_VF25
- IH_PERF_SEL_RB0_OVERFLOW_VF26
- IH_PERF_SEL_RB0_OVERFLOW_VF27
- IH_PERF_SEL_RB0_OVERFLOW_VF28
- IH_PERF_SEL_RB0_OVERFLOW_VF29
- IH_PERF_SEL_RB0_OVERFLOW_VF3
- IH_PERF_SEL_RB0_OVERFLOW_VF30
- IH_PERF_SEL_RB0_OVERFLOW_VF4
- IH_PERF_SEL_RB0_OVERFLOW_VF5
- IH_PERF_SEL_RB0_OVERFLOW_VF6
- IH_PERF_SEL_RB0_OVERFLOW_VF7
- IH_PERF_SEL_RB0_OVERFLOW_VF8
- IH_PERF_SEL_RB0_OVERFLOW_VF9
- IH_PERF_SEL_RB0_RPTR_WRAP
- IH_PERF_SEL_RB0_RPTR_WRAP_VF0
- IH_PERF_SEL_RB0_RPTR_WRAP_VF1
- IH_PERF_SEL_RB0_RPTR_WRAP_VF10
- IH_PERF_SEL_RB0_RPTR_WRAP_VF11
- IH_PERF_SEL_RB0_RPTR_WRAP_VF12
- IH_PERF_SEL_RB0_RPTR_WRAP_VF13
- IH_PERF_SEL_RB0_RPTR_WRAP_VF14
- IH_PERF_SEL_RB0_RPTR_WRAP_VF15
- IH_PERF_SEL_RB0_RPTR_WRAP_VF16
- IH_PERF_SEL_RB0_RPTR_WRAP_VF17
- IH_PERF_SEL_RB0_RPTR_WRAP_VF18
- IH_PERF_SEL_RB0_RPTR_WRAP_VF19
- IH_PERF_SEL_RB0_RPTR_WRAP_VF2
- IH_PERF_SEL_RB0_RPTR_WRAP_VF20
- IH_PERF_SEL_RB0_RPTR_WRAP_VF21
- IH_PERF_SEL_RB0_RPTR_WRAP_VF22
- IH_PERF_SEL_RB0_RPTR_WRAP_VF23
- IH_PERF_SEL_RB0_RPTR_WRAP_VF24
- IH_PERF_SEL_RB0_RPTR_WRAP_VF25
- IH_PERF_SEL_RB0_RPTR_WRAP_VF26
- IH_PERF_SEL_RB0_RPTR_WRAP_VF27
- IH_PERF_SEL_RB0_RPTR_WRAP_VF28
- IH_PERF_SEL_RB0_RPTR_WRAP_VF29
- IH_PERF_SEL_RB0_RPTR_WRAP_VF3
- IH_PERF_SEL_RB0_RPTR_WRAP_VF30
- IH_PERF_SEL_RB0_RPTR_WRAP_VF4
- IH_PERF_SEL_RB0_RPTR_WRAP_VF5
- IH_PERF_SEL_RB0_RPTR_WRAP_VF6
- IH_PERF_SEL_RB0_RPTR_WRAP_VF7
- IH_PERF_SEL_RB0_RPTR_WRAP_VF8
- IH_PERF_SEL_RB0_RPTR_WRAP_VF9
- IH_PERF_SEL_RB0_WPTR_WRAP
- IH_PERF_SEL_RB0_WPTR_WRAP_VF0
- IH_PERF_SEL_RB0_WPTR_WRAP_VF1
- IH_PERF_SEL_RB0_WPTR_WRAP_VF10
- IH_PERF_SEL_RB0_WPTR_WRAP_VF11
- IH_PERF_SEL_RB0_WPTR_WRAP_VF12
- IH_PERF_SEL_RB0_WPTR_WRAP_VF13
- IH_PERF_SEL_RB0_WPTR_WRAP_VF14
- IH_PERF_SEL_RB0_WPTR_WRAP_VF15
- IH_PERF_SEL_RB0_WPTR_WRAP_VF16
- IH_PERF_SEL_RB0_WPTR_WRAP_VF17
- IH_PERF_SEL_RB0_WPTR_WRAP_VF18
- IH_PERF_SEL_RB0_WPTR_WRAP_VF19
- IH_PERF_SEL_RB0_WPTR_WRAP_VF2
- IH_PERF_SEL_RB0_WPTR_WRAP_VF20
- IH_PERF_SEL_RB0_WPTR_WRAP_VF21
- IH_PERF_SEL_RB0_WPTR_WRAP_VF22
- IH_PERF_SEL_RB0_WPTR_WRAP_VF23
- IH_PERF_SEL_RB0_WPTR_WRAP_VF24
- IH_PERF_SEL_RB0_WPTR_WRAP_VF25
- IH_PERF_SEL_RB0_WPTR_WRAP_VF26
- IH_PERF_SEL_RB0_WPTR_WRAP_VF27
- IH_PERF_SEL_RB0_WPTR_WRAP_VF28
- IH_PERF_SEL_RB0_WPTR_WRAP_VF29
- IH_PERF_SEL_RB0_WPTR_WRAP_VF3
- IH_PERF_SEL_RB0_WPTR_WRAP_VF30
- IH_PERF_SEL_RB0_WPTR_WRAP_VF4
- IH_PERF_SEL_RB0_WPTR_WRAP_VF5
- IH_PERF_SEL_RB0_WPTR_WRAP_VF6
- IH_PERF_SEL_RB0_WPTR_WRAP_VF7
- IH_PERF_SEL_RB0_WPTR_WRAP_VF8
- IH_PERF_SEL_RB0_WPTR_WRAP_VF9
- IH_PERF_SEL_RB0_WPTR_WRITEBACK
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8
- IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9
- IH_PERF_SEL_RB1_FULL
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8
- IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9
- IH_PERF_SEL_RB1_FULL_VF0
- IH_PERF_SEL_RB1_FULL_VF1
- IH_PERF_SEL_RB1_FULL_VF10
- IH_PERF_SEL_RB1_FULL_VF11
- IH_PERF_SEL_RB1_FULL_VF12
- IH_PERF_SEL_RB1_FULL_VF13
- IH_PERF_SEL_RB1_FULL_VF14
- IH_PERF_SEL_RB1_FULL_VF15
- IH_PERF_SEL_RB1_FULL_VF16
- IH_PERF_SEL_RB1_FULL_VF17
- IH_PERF_SEL_RB1_FULL_VF18
- IH_PERF_SEL_RB1_FULL_VF19
- IH_PERF_SEL_RB1_FULL_VF2
- IH_PERF_SEL_RB1_FULL_VF20
- IH_PERF_SEL_RB1_FULL_VF21
- IH_PERF_SEL_RB1_FULL_VF22
- IH_PERF_SEL_RB1_FULL_VF23
- IH_PERF_SEL_RB1_FULL_VF24
- IH_PERF_SEL_RB1_FULL_VF25
- IH_PERF_SEL_RB1_FULL_VF26
- IH_PERF_SEL_RB1_FULL_VF27
- IH_PERF_SEL_RB1_FULL_VF28
- IH_PERF_SEL_RB1_FULL_VF29
- IH_PERF_SEL_RB1_FULL_VF3
- IH_PERF_SEL_RB1_FULL_VF30
- IH_PERF_SEL_RB1_FULL_VF4
- IH_PERF_SEL_RB1_FULL_VF5
- IH_PERF_SEL_RB1_FULL_VF6
- IH_PERF_SEL_RB1_FULL_VF7
- IH_PERF_SEL_RB1_FULL_VF8
- IH_PERF_SEL_RB1_FULL_VF9
- IH_PERF_SEL_RB1_LOAD_RPTR
- IH_PERF_SEL_RB1_LOAD_RPTR_VF0
- IH_PERF_SEL_RB1_LOAD_RPTR_VF1
- IH_PERF_SEL_RB1_LOAD_RPTR_VF10
- IH_PERF_SEL_RB1_LOAD_RPTR_VF11
- IH_PERF_SEL_RB1_LOAD_RPTR_VF12
- IH_PERF_SEL_RB1_LOAD_RPTR_VF13
- IH_PERF_SEL_RB1_LOAD_RPTR_VF14
- IH_PERF_SEL_RB1_LOAD_RPTR_VF15
- IH_PERF_SEL_RB1_LOAD_RPTR_VF16
- IH_PERF_SEL_RB1_LOAD_RPTR_VF17
- IH_PERF_SEL_RB1_LOAD_RPTR_VF18
- IH_PERF_SEL_RB1_LOAD_RPTR_VF19
- IH_PERF_SEL_RB1_LOAD_RPTR_VF2
- IH_PERF_SEL_RB1_LOAD_RPTR_VF20
- IH_PERF_SEL_RB1_LOAD_RPTR_VF21
- IH_PERF_SEL_RB1_LOAD_RPTR_VF22
- IH_PERF_SEL_RB1_LOAD_RPTR_VF23
- IH_PERF_SEL_RB1_LOAD_RPTR_VF24
- IH_PERF_SEL_RB1_LOAD_RPTR_VF25
- IH_PERF_SEL_RB1_LOAD_RPTR_VF26
- IH_PERF_SEL_RB1_LOAD_RPTR_VF27
- IH_PERF_SEL_RB1_LOAD_RPTR_VF28
- IH_PERF_SEL_RB1_LOAD_RPTR_VF29
- IH_PERF_SEL_RB1_LOAD_RPTR_VF3
- IH_PERF_SEL_RB1_LOAD_RPTR_VF30
- IH_PERF_SEL_RB1_LOAD_RPTR_VF4
- IH_PERF_SEL_RB1_LOAD_RPTR_VF5
- IH_PERF_SEL_RB1_LOAD_RPTR_VF6
- IH_PERF_SEL_RB1_LOAD_RPTR_VF7
- IH_PERF_SEL_RB1_LOAD_RPTR_VF8
- IH_PERF_SEL_RB1_LOAD_RPTR_VF9
- IH_PERF_SEL_RB1_OVERFLOW
- IH_PERF_SEL_RB1_OVERFLOW_VF0
- IH_PERF_SEL_RB1_OVERFLOW_VF1
- IH_PERF_SEL_RB1_OVERFLOW_VF10
- IH_PERF_SEL_RB1_OVERFLOW_VF11
- IH_PERF_SEL_RB1_OVERFLOW_VF12
- IH_PERF_SEL_RB1_OVERFLOW_VF13
- IH_PERF_SEL_RB1_OVERFLOW_VF14
- IH_PERF_SEL_RB1_OVERFLOW_VF15
- IH_PERF_SEL_RB1_OVERFLOW_VF16
- IH_PERF_SEL_RB1_OVERFLOW_VF17
- IH_PERF_SEL_RB1_OVERFLOW_VF18
- IH_PERF_SEL_RB1_OVERFLOW_VF19
- IH_PERF_SEL_RB1_OVERFLOW_VF2
- IH_PERF_SEL_RB1_OVERFLOW_VF20
- IH_PERF_SEL_RB1_OVERFLOW_VF21
- IH_PERF_SEL_RB1_OVERFLOW_VF22
- IH_PERF_SEL_RB1_OVERFLOW_VF23
- IH_PERF_SEL_RB1_OVERFLOW_VF24
- IH_PERF_SEL_RB1_OVERFLOW_VF25
- IH_PERF_SEL_RB1_OVERFLOW_VF26
- IH_PERF_SEL_RB1_OVERFLOW_VF27
- IH_PERF_SEL_RB1_OVERFLOW_VF28
- IH_PERF_SEL_RB1_OVERFLOW_VF29
- IH_PERF_SEL_RB1_OVERFLOW_VF3
- IH_PERF_SEL_RB1_OVERFLOW_VF30
- IH_PERF_SEL_RB1_OVERFLOW_VF4
- IH_PERF_SEL_RB1_OVERFLOW_VF5
- IH_PERF_SEL_RB1_OVERFLOW_VF6
- IH_PERF_SEL_RB1_OVERFLOW_VF7
- IH_PERF_SEL_RB1_OVERFLOW_VF8
- IH_PERF_SEL_RB1_OVERFLOW_VF9
- IH_PERF_SEL_RB1_RPTR_WRAP
- IH_PERF_SEL_RB1_RPTR_WRAP_VF0
- IH_PERF_SEL_RB1_RPTR_WRAP_VF1
- IH_PERF_SEL_RB1_RPTR_WRAP_VF10
- IH_PERF_SEL_RB1_RPTR_WRAP_VF11
- IH_PERF_SEL_RB1_RPTR_WRAP_VF12
- IH_PERF_SEL_RB1_RPTR_WRAP_VF13
- IH_PERF_SEL_RB1_RPTR_WRAP_VF14
- IH_PERF_SEL_RB1_RPTR_WRAP_VF15
- IH_PERF_SEL_RB1_RPTR_WRAP_VF16
- IH_PERF_SEL_RB1_RPTR_WRAP_VF17
- IH_PERF_SEL_RB1_RPTR_WRAP_VF18
- IH_PERF_SEL_RB1_RPTR_WRAP_VF19
- IH_PERF_SEL_RB1_RPTR_WRAP_VF2
- IH_PERF_SEL_RB1_RPTR_WRAP_VF20
- IH_PERF_SEL_RB1_RPTR_WRAP_VF21
- IH_PERF_SEL_RB1_RPTR_WRAP_VF22
- IH_PERF_SEL_RB1_RPTR_WRAP_VF23
- IH_PERF_SEL_RB1_RPTR_WRAP_VF24
- IH_PERF_SEL_RB1_RPTR_WRAP_VF25
- IH_PERF_SEL_RB1_RPTR_WRAP_VF26
- IH_PERF_SEL_RB1_RPTR_WRAP_VF27
- IH_PERF_SEL_RB1_RPTR_WRAP_VF28
- IH_PERF_SEL_RB1_RPTR_WRAP_VF29
- IH_PERF_SEL_RB1_RPTR_WRAP_VF3
- IH_PERF_SEL_RB1_RPTR_WRAP_VF30
- IH_PERF_SEL_RB1_RPTR_WRAP_VF4
- IH_PERF_SEL_RB1_RPTR_WRAP_VF5
- IH_PERF_SEL_RB1_RPTR_WRAP_VF6
- IH_PERF_SEL_RB1_RPTR_WRAP_VF7
- IH_PERF_SEL_RB1_RPTR_WRAP_VF8
- IH_PERF_SEL_RB1_RPTR_WRAP_VF9
- IH_PERF_SEL_RB1_WPTR_WRAP
- IH_PERF_SEL_RB1_WPTR_WRAP_VF0
- IH_PERF_SEL_RB1_WPTR_WRAP_VF1
- IH_PERF_SEL_RB1_WPTR_WRAP_VF10
- IH_PERF_SEL_RB1_WPTR_WRAP_VF11
- IH_PERF_SEL_RB1_WPTR_WRAP_VF12
- IH_PERF_SEL_RB1_WPTR_WRAP_VF13
- IH_PERF_SEL_RB1_WPTR_WRAP_VF14
- IH_PERF_SEL_RB1_WPTR_WRAP_VF15
- IH_PERF_SEL_RB1_WPTR_WRAP_VF16
- IH_PERF_SEL_RB1_WPTR_WRAP_VF17
- IH_PERF_SEL_RB1_WPTR_WRAP_VF18
- IH_PERF_SEL_RB1_WPTR_WRAP_VF19
- IH_PERF_SEL_RB1_WPTR_WRAP_VF2
- IH_PERF_SEL_RB1_WPTR_WRAP_VF20
- IH_PERF_SEL_RB1_WPTR_WRAP_VF21
- IH_PERF_SEL_RB1_WPTR_WRAP_VF22
- IH_PERF_SEL_RB1_WPTR_WRAP_VF23
- IH_PERF_SEL_RB1_WPTR_WRAP_VF24
- IH_PERF_SEL_RB1_WPTR_WRAP_VF25
- IH_PERF_SEL_RB1_WPTR_WRAP_VF26
- IH_PERF_SEL_RB1_WPTR_WRAP_VF27
- IH_PERF_SEL_RB1_WPTR_WRAP_VF28
- IH_PERF_SEL_RB1_WPTR_WRAP_VF29
- IH_PERF_SEL_RB1_WPTR_WRAP_VF3
- IH_PERF_SEL_RB1_WPTR_WRAP_VF30
- IH_PERF_SEL_RB1_WPTR_WRAP_VF4
- IH_PERF_SEL_RB1_WPTR_WRAP_VF5
- IH_PERF_SEL_RB1_WPTR_WRAP_VF6
- IH_PERF_SEL_RB1_WPTR_WRAP_VF7
- IH_PERF_SEL_RB1_WPTR_WRAP_VF8
- IH_PERF_SEL_RB1_WPTR_WRAP_VF9
- IH_PERF_SEL_RB2_FULL
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8
- IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9
- IH_PERF_SEL_RB2_FULL_VF0
- IH_PERF_SEL_RB2_FULL_VF1
- IH_PERF_SEL_RB2_FULL_VF10
- IH_PERF_SEL_RB2_FULL_VF11
- IH_PERF_SEL_RB2_FULL_VF12
- IH_PERF_SEL_RB2_FULL_VF13
- IH_PERF_SEL_RB2_FULL_VF14
- IH_PERF_SEL_RB2_FULL_VF15
- IH_PERF_SEL_RB2_FULL_VF16
- IH_PERF_SEL_RB2_FULL_VF17
- IH_PERF_SEL_RB2_FULL_VF18
- IH_PERF_SEL_RB2_FULL_VF19
- IH_PERF_SEL_RB2_FULL_VF2
- IH_PERF_SEL_RB2_FULL_VF20
- IH_PERF_SEL_RB2_FULL_VF21
- IH_PERF_SEL_RB2_FULL_VF22
- IH_PERF_SEL_RB2_FULL_VF23
- IH_PERF_SEL_RB2_FULL_VF24
- IH_PERF_SEL_RB2_FULL_VF25
- IH_PERF_SEL_RB2_FULL_VF26
- IH_PERF_SEL_RB2_FULL_VF27
- IH_PERF_SEL_RB2_FULL_VF28
- IH_PERF_SEL_RB2_FULL_VF29
- IH_PERF_SEL_RB2_FULL_VF3
- IH_PERF_SEL_RB2_FULL_VF30
- IH_PERF_SEL_RB2_FULL_VF4
- IH_PERF_SEL_RB2_FULL_VF5
- IH_PERF_SEL_RB2_FULL_VF6
- IH_PERF_SEL_RB2_FULL_VF7
- IH_PERF_SEL_RB2_FULL_VF8
- IH_PERF_SEL_RB2_FULL_VF9
- IH_PERF_SEL_RB2_LOAD_RPTR
- IH_PERF_SEL_RB2_LOAD_RPTR_VF0
- IH_PERF_SEL_RB2_LOAD_RPTR_VF1
- IH_PERF_SEL_RB2_LOAD_RPTR_VF10
- IH_PERF_SEL_RB2_LOAD_RPTR_VF11
- IH_PERF_SEL_RB2_LOAD_RPTR_VF12
- IH_PERF_SEL_RB2_LOAD_RPTR_VF13
- IH_PERF_SEL_RB2_LOAD_RPTR_VF14
- IH_PERF_SEL_RB2_LOAD_RPTR_VF15
- IH_PERF_SEL_RB2_LOAD_RPTR_VF16
- IH_PERF_SEL_RB2_LOAD_RPTR_VF17
- IH_PERF_SEL_RB2_LOAD_RPTR_VF18
- IH_PERF_SEL_RB2_LOAD_RPTR_VF19
- IH_PERF_SEL_RB2_LOAD_RPTR_VF2
- IH_PERF_SEL_RB2_LOAD_RPTR_VF20
- IH_PERF_SEL_RB2_LOAD_RPTR_VF21
- IH_PERF_SEL_RB2_LOAD_RPTR_VF22
- IH_PERF_SEL_RB2_LOAD_RPTR_VF23
- IH_PERF_SEL_RB2_LOAD_RPTR_VF24
- IH_PERF_SEL_RB2_LOAD_RPTR_VF25
- IH_PERF_SEL_RB2_LOAD_RPTR_VF26
- IH_PERF_SEL_RB2_LOAD_RPTR_VF27
- IH_PERF_SEL_RB2_LOAD_RPTR_VF28
- IH_PERF_SEL_RB2_LOAD_RPTR_VF29
- IH_PERF_SEL_RB2_LOAD_RPTR_VF3
- IH_PERF_SEL_RB2_LOAD_RPTR_VF30
- IH_PERF_SEL_RB2_LOAD_RPTR_VF4
- IH_PERF_SEL_RB2_LOAD_RPTR_VF5
- IH_PERF_SEL_RB2_LOAD_RPTR_VF6
- IH_PERF_SEL_RB2_LOAD_RPTR_VF7
- IH_PERF_SEL_RB2_LOAD_RPTR_VF8
- IH_PERF_SEL_RB2_LOAD_RPTR_VF9
- IH_PERF_SEL_RB2_OVERFLOW
- IH_PERF_SEL_RB2_OVERFLOW_VF0
- IH_PERF_SEL_RB2_OVERFLOW_VF1
- IH_PERF_SEL_RB2_OVERFLOW_VF10
- IH_PERF_SEL_RB2_OVERFLOW_VF11
- IH_PERF_SEL_RB2_OVERFLOW_VF12
- IH_PERF_SEL_RB2_OVERFLOW_VF13
- IH_PERF_SEL_RB2_OVERFLOW_VF14
- IH_PERF_SEL_RB2_OVERFLOW_VF15
- IH_PERF_SEL_RB2_OVERFLOW_VF16
- IH_PERF_SEL_RB2_OVERFLOW_VF17
- IH_PERF_SEL_RB2_OVERFLOW_VF18
- IH_PERF_SEL_RB2_OVERFLOW_VF19
- IH_PERF_SEL_RB2_OVERFLOW_VF2
- IH_PERF_SEL_RB2_OVERFLOW_VF20
- IH_PERF_SEL_RB2_OVERFLOW_VF21
- IH_PERF_SEL_RB2_OVERFLOW_VF22
- IH_PERF_SEL_RB2_OVERFLOW_VF23
- IH_PERF_SEL_RB2_OVERFLOW_VF24
- IH_PERF_SEL_RB2_OVERFLOW_VF25
- IH_PERF_SEL_RB2_OVERFLOW_VF26
- IH_PERF_SEL_RB2_OVERFLOW_VF27
- IH_PERF_SEL_RB2_OVERFLOW_VF28
- IH_PERF_SEL_RB2_OVERFLOW_VF29
- IH_PERF_SEL_RB2_OVERFLOW_VF3
- IH_PERF_SEL_RB2_OVERFLOW_VF30
- IH_PERF_SEL_RB2_OVERFLOW_VF4
- IH_PERF_SEL_RB2_OVERFLOW_VF5
- IH_PERF_SEL_RB2_OVERFLOW_VF6
- IH_PERF_SEL_RB2_OVERFLOW_VF7
- IH_PERF_SEL_RB2_OVERFLOW_VF8
- IH_PERF_SEL_RB2_OVERFLOW_VF9
- IH_PERF_SEL_RB2_RPTR_WRAP
- IH_PERF_SEL_RB2_RPTR_WRAP_VF0
- IH_PERF_SEL_RB2_RPTR_WRAP_VF1
- IH_PERF_SEL_RB2_RPTR_WRAP_VF10
- IH_PERF_SEL_RB2_RPTR_WRAP_VF11
- IH_PERF_SEL_RB2_RPTR_WRAP_VF12
- IH_PERF_SEL_RB2_RPTR_WRAP_VF13
- IH_PERF_SEL_RB2_RPTR_WRAP_VF14
- IH_PERF_SEL_RB2_RPTR_WRAP_VF15
- IH_PERF_SEL_RB2_RPTR_WRAP_VF16
- IH_PERF_SEL_RB2_RPTR_WRAP_VF17
- IH_PERF_SEL_RB2_RPTR_WRAP_VF18
- IH_PERF_SEL_RB2_RPTR_WRAP_VF19
- IH_PERF_SEL_RB2_RPTR_WRAP_VF2
- IH_PERF_SEL_RB2_RPTR_WRAP_VF20
- IH_PERF_SEL_RB2_RPTR_WRAP_VF21
- IH_PERF_SEL_RB2_RPTR_WRAP_VF22
- IH_PERF_SEL_RB2_RPTR_WRAP_VF23
- IH_PERF_SEL_RB2_RPTR_WRAP_VF24
- IH_PERF_SEL_RB2_RPTR_WRAP_VF25
- IH_PERF_SEL_RB2_RPTR_WRAP_VF26
- IH_PERF_SEL_RB2_RPTR_WRAP_VF27
- IH_PERF_SEL_RB2_RPTR_WRAP_VF28
- IH_PERF_SEL_RB2_RPTR_WRAP_VF29
- IH_PERF_SEL_RB2_RPTR_WRAP_VF3
- IH_PERF_SEL_RB2_RPTR_WRAP_VF30
- IH_PERF_SEL_RB2_RPTR_WRAP_VF4
- IH_PERF_SEL_RB2_RPTR_WRAP_VF5
- IH_PERF_SEL_RB2_RPTR_WRAP_VF6
- IH_PERF_SEL_RB2_RPTR_WRAP_VF7
- IH_PERF_SEL_RB2_RPTR_WRAP_VF8
- IH_PERF_SEL_RB2_RPTR_WRAP_VF9
- IH_PERF_SEL_RB2_WPTR_WRAP
- IH_PERF_SEL_RB2_WPTR_WRAP_VF0
- IH_PERF_SEL_RB2_WPTR_WRAP_VF1
- IH_PERF_SEL_RB2_WPTR_WRAP_VF10
- IH_PERF_SEL_RB2_WPTR_WRAP_VF11
- IH_PERF_SEL_RB2_WPTR_WRAP_VF12
- IH_PERF_SEL_RB2_WPTR_WRAP_VF13
- IH_PERF_SEL_RB2_WPTR_WRAP_VF14
- IH_PERF_SEL_RB2_WPTR_WRAP_VF15
- IH_PERF_SEL_RB2_WPTR_WRAP_VF16
- IH_PERF_SEL_RB2_WPTR_WRAP_VF17
- IH_PERF_SEL_RB2_WPTR_WRAP_VF18
- IH_PERF_SEL_RB2_WPTR_WRAP_VF19
- IH_PERF_SEL_RB2_WPTR_WRAP_VF2
- IH_PERF_SEL_RB2_WPTR_WRAP_VF20
- IH_PERF_SEL_RB2_WPTR_WRAP_VF21
- IH_PERF_SEL_RB2_WPTR_WRAP_VF22
- IH_PERF_SEL_RB2_WPTR_WRAP_VF23
- IH_PERF_SEL_RB2_WPTR_WRAP_VF24
- IH_PERF_SEL_RB2_WPTR_WRAP_VF25
- IH_PERF_SEL_RB2_WPTR_WRAP_VF26
- IH_PERF_SEL_RB2_WPTR_WRAP_VF27
- IH_PERF_SEL_RB2_WPTR_WRAP_VF28
- IH_PERF_SEL_RB2_WPTR_WRAP_VF29
- IH_PERF_SEL_RB2_WPTR_WRAP_VF3
- IH_PERF_SEL_RB2_WPTR_WRAP_VF30
- IH_PERF_SEL_RB2_WPTR_WRAP_VF4
- IH_PERF_SEL_RB2_WPTR_WRAP_VF5
- IH_PERF_SEL_RB2_WPTR_WRAP_VF6
- IH_PERF_SEL_RB2_WPTR_WRAP_VF7
- IH_PERF_SEL_RB2_WPTR_WRAP_VF8
- IH_PERF_SEL_RB2_WPTR_WRAP_VF9
- IH_PERF_SEL_RB_FULL
- IH_PERF_SEL_RB_FULL_VF0
- IH_PERF_SEL_RB_FULL_VF1
- IH_PERF_SEL_RB_FULL_VF10
- IH_PERF_SEL_RB_FULL_VF11
- IH_PERF_SEL_RB_FULL_VF12
- IH_PERF_SEL_RB_FULL_VF13
- IH_PERF_SEL_RB_FULL_VF14
- IH_PERF_SEL_RB_FULL_VF15
- IH_PERF_SEL_RB_FULL_VF2
- IH_PERF_SEL_RB_FULL_VF3
- IH_PERF_SEL_RB_FULL_VF4
- IH_PERF_SEL_RB_FULL_VF5
- IH_PERF_SEL_RB_FULL_VF6
- IH_PERF_SEL_RB_FULL_VF7
- IH_PERF_SEL_RB_FULL_VF8
- IH_PERF_SEL_RB_FULL_VF9
- IH_PERF_SEL_RB_IDLE
- IH_PERF_SEL_RB_OVERFLOW
- IH_PERF_SEL_RB_OVERFLOW_VF0
- IH_PERF_SEL_RB_OVERFLOW_VF1
- IH_PERF_SEL_RB_OVERFLOW_VF10
- IH_PERF_SEL_RB_OVERFLOW_VF11
- IH_PERF_SEL_RB_OVERFLOW_VF12
- IH_PERF_SEL_RB_OVERFLOW_VF13
- IH_PERF_SEL_RB_OVERFLOW_VF14
- IH_PERF_SEL_RB_OVERFLOW_VF15
- IH_PERF_SEL_RB_OVERFLOW_VF2
- IH_PERF_SEL_RB_OVERFLOW_VF3
- IH_PERF_SEL_RB_OVERFLOW_VF4
- IH_PERF_SEL_RB_OVERFLOW_VF5
- IH_PERF_SEL_RB_OVERFLOW_VF6
- IH_PERF_SEL_RB_OVERFLOW_VF7
- IH_PERF_SEL_RB_OVERFLOW_VF8
- IH_PERF_SEL_RB_OVERFLOW_VF9
- IH_PERF_SEL_RB_RPTR_WRAP
- IH_PERF_SEL_RB_RPTR_WRAP_VF0
- IH_PERF_SEL_RB_RPTR_WRAP_VF1
- IH_PERF_SEL_RB_RPTR_WRAP_VF10
- IH_PERF_SEL_RB_RPTR_WRAP_VF11
- IH_PERF_SEL_RB_RPTR_WRAP_VF12
- IH_PERF_SEL_RB_RPTR_WRAP_VF13
- IH_PERF_SEL_RB_RPTR_WRAP_VF14
- IH_PERF_SEL_RB_RPTR_WRAP_VF15
- IH_PERF_SEL_RB_RPTR_WRAP_VF2
- IH_PERF_SEL_RB_RPTR_WRAP_VF3
- IH_PERF_SEL_RB_RPTR_WRAP_VF4
- IH_PERF_SEL_RB_RPTR_WRAP_VF5
- IH_PERF_SEL_RB_RPTR_WRAP_VF6
- IH_PERF_SEL_RB_RPTR_WRAP_VF7
- IH_PERF_SEL_RB_RPTR_WRAP_VF8
- IH_PERF_SEL_RB_RPTR_WRAP_VF9
- IH_PERF_SEL_RB_WPTR_WRAP
- IH_PERF_SEL_RB_WPTR_WRAP_VF0
- IH_PERF_SEL_RB_WPTR_WRAP_VF1
- IH_PERF_SEL_RB_WPTR_WRAP_VF10
- IH_PERF_SEL_RB_WPTR_WRAP_VF11
- IH_PERF_SEL_RB_WPTR_WRAP_VF12
- IH_PERF_SEL_RB_WPTR_WRAP_VF13
- IH_PERF_SEL_RB_WPTR_WRAP_VF14
- IH_PERF_SEL_RB_WPTR_WRAP_VF15
- IH_PERF_SEL_RB_WPTR_WRAP_VF2
- IH_PERF_SEL_RB_WPTR_WRAP_VF3
- IH_PERF_SEL_RB_WPTR_WRAP_VF4
- IH_PERF_SEL_RB_WPTR_WRAP_VF5
- IH_PERF_SEL_RB_WPTR_WRAP_VF6
- IH_PERF_SEL_RB_WPTR_WRAP_VF7
- IH_PERF_SEL_RB_WPTR_WRAP_VF8
- IH_PERF_SEL_RB_WPTR_WRAP_VF9
- IH_PERF_SEL_RB_WPTR_WRITEBACK
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF0
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF1
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF10
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF11
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF12
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF13
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF14
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF15
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF2
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF3
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF4
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF5
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF6
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF7
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF8
- IH_PERF_SEL_RB_WPTR_WRITEBACK_VF9
- IH_PERF_SEL_SELF_IV_VALID
- IH_PERF_SEL_STORM_CLIENT_INT_DROP
- IH_RB
- IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK
- IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK
- IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT
- IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT
- IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK
- IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK
- IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT
- IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT
- IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK
- IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK
- IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT
- IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT
- IH_RB_BASE
- IH_RB_BASE_HI_RING1__ADDR_MASK
- IH_RB_BASE_HI_RING1__ADDR__SHIFT
- IH_RB_BASE_HI_RING2__ADDR_MASK
- IH_RB_BASE_HI_RING2__ADDR__SHIFT
- IH_RB_BASE_HI__ADDR_MASK
- IH_RB_BASE_HI__ADDR__SHIFT
- IH_RB_BASE_RING1__ADDR_MASK
- IH_RB_BASE_RING1__ADDR__SHIFT
- IH_RB_BASE_RING2__ADDR_MASK
- IH_RB_BASE_RING2__ADDR__SHIFT
- IH_RB_BASE__ADDR_MASK
- IH_RB_BASE__ADDR__SHIFT
- IH_RB_CNTL
- IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK
- IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT
- IH_RB_CNTL_RING1__MC_RO_MASK
- IH_RB_CNTL_RING1__MC_RO__SHIFT
- IH_RB_CNTL_RING1__MC_SNOOP_MASK
- IH_RB_CNTL_RING1__MC_SNOOP__SHIFT
- IH_RB_CNTL_RING1__MC_SPACE_MASK
- IH_RB_CNTL_RING1__MC_SPACE__SHIFT
- IH_RB_CNTL_RING1__MC_SWAP_MASK
- IH_RB_CNTL_RING1__MC_SWAP__SHIFT
- IH_RB_CNTL_RING1__MC_VMID_MASK
- IH_RB_CNTL_RING1__MC_VMID__SHIFT
- IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK
- IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT
- IH_RB_CNTL_RING1__RB_ENABLE_MASK
- IH_RB_CNTL_RING1__RB_ENABLE__SHIFT
- IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK
- IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT
- IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK
- IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT
- IH_RB_CNTL_RING1__RB_SIZE_MASK
- IH_RB_CNTL_RING1__RB_SIZE__SHIFT
- IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK
- IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT
- IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK
- IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT
- IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK
- IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT
- IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK
- IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT
- IH_RB_CNTL_RING2__MC_RO_MASK
- IH_RB_CNTL_RING2__MC_RO__SHIFT
- IH_RB_CNTL_RING2__MC_SNOOP_MASK
- IH_RB_CNTL_RING2__MC_SNOOP__SHIFT
- IH_RB_CNTL_RING2__MC_SPACE_MASK
- IH_RB_CNTL_RING2__MC_SPACE__SHIFT
- IH_RB_CNTL_RING2__MC_SWAP_MASK
- IH_RB_CNTL_RING2__MC_SWAP__SHIFT
- IH_RB_CNTL_RING2__MC_VMID_MASK
- IH_RB_CNTL_RING2__MC_VMID__SHIFT
- IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK
- IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT
- IH_RB_CNTL_RING2__RB_ENABLE_MASK
- IH_RB_CNTL_RING2__RB_ENABLE__SHIFT
- IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK
- IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT
- IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK
- IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT
- IH_RB_CNTL_RING2__RB_SIZE_MASK
- IH_RB_CNTL_RING2__RB_SIZE__SHIFT
- IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK
- IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT
- IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK
- IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT
- IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK
- IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT
- IH_RB_CNTL__ENABLE_INTR_MASK
- IH_RB_CNTL__ENABLE_INTR__SHIFT
- IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK
- IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT
- IH_RB_CNTL__MC_RO_MASK
- IH_RB_CNTL__MC_RO__SHIFT
- IH_RB_CNTL__MC_SNOOP_MASK
- IH_RB_CNTL__MC_SNOOP__SHIFT
- IH_RB_CNTL__MC_SPACE_MASK
- IH_RB_CNTL__MC_SPACE__SHIFT
- IH_RB_CNTL__MC_SWAP_MASK
- IH_RB_CNTL__MC_SWAP__SHIFT
- IH_RB_CNTL__MC_VMID_MASK
- IH_RB_CNTL__MC_VMID__SHIFT
- IH_RB_CNTL__PAGE_RB_CLEAR_MASK
- IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT
- IH_RB_CNTL__RB_ENABLE_MASK
- IH_RB_CNTL__RB_ENABLE__SHIFT
- IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK
- IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT
- IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK
- IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT
- IH_RB_CNTL__RB_SIZE_MASK
- IH_RB_CNTL__RB_SIZE__SHIFT
- IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK
- IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT
- IH_RB_CNTL__RPTR_REARM_MASK
- IH_RB_CNTL__RPTR_REARM__SHIFT
- IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
- IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT
- IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK
- IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT
- IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK
- IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT
- IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK
- IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT
- IH_RB_ENABLE
- IH_RB_FULL_DRAIN_ENABLE
- IH_RB_RNG1
- IH_RB_RNG2
- IH_RB_RPTR
- IH_RB_RPTR_RING1__OFFSET_MASK
- IH_RB_RPTR_RING1__OFFSET__SHIFT
- IH_RB_RPTR_RING2__OFFSET_MASK
- IH_RB_RPTR_RING2__OFFSET__SHIFT
- IH_RB_RPTR__OFFSET_MASK
- IH_RB_RPTR__OFFSET__SHIFT
- IH_RB_SIZE
- IH_RB_WPTR
- IH_RB_WPTR_ADDR_HI
- IH_RB_WPTR_ADDR_HI__ADDR_MASK
- IH_RB_WPTR_ADDR_HI__ADDR__SHIFT
- IH_RB_WPTR_ADDR_LO
- IH_RB_WPTR_ADDR_LO__ADDR_MASK
- IH_RB_WPTR_ADDR_LO__ADDR__SHIFT
- IH_RB_WPTR_RING1__OFFSET_MASK
- IH_RB_WPTR_RING1__OFFSET__SHIFT
- IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK
- IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT
- IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK
- IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT
- IH_RB_WPTR_RING1__RB_OVERFLOW_MASK
- IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT
- IH_RB_WPTR_RING2__OFFSET_MASK
- IH_RB_WPTR_RING2__OFFSET__SHIFT
- IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK
- IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT
- IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK
- IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT
- IH_RB_WPTR_RING2__RB_OVERFLOW_MASK
- IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT
- IH_RB_WPTR__OFFSET_MASK
- IH_RB_WPTR__OFFSET__SHIFT
- IH_RB_WPTR__RB_LEFT_NONE_MASK
- IH_RB_WPTR__RB_LEFT_NONE__SHIFT
- IH_RB_WPTR__RB_MAY_OVERFLOW_MASK
- IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT
- IH_RB_WPTR__RB_OVERFLOW_MASK
- IH_RB_WPTR__RB_OVERFLOW__SHIFT
- IH_REGISTER_LAST_PART0__RESERVED_MASK
- IH_REGISTER_LAST_PART0__RESERVED__SHIFT
- IH_REGISTER_LAST_PART1__RESERVED_MASK
- IH_REGISTER_LAST_PART1__RESERVED__SHIFT
- IH_REGISTER_LAST_PART2__RESERVED_MASK
- IH_REGISTER_LAST_PART2__RESERVED__SHIFT
- IH_REGISTER_WRITE_INTERFACE
- IH_REPLY_DONE
- IH_REPLY_NOT_DONE
- IH_REQ_NONSNOOP_EN
- IH_RESET_INCOMPLETE_INT_CNTL__ACP_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__ACP__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__ATC_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__ATC__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__BIF_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__BIF__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__CG__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__DC_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__INCOMPLETE_CNT__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__ISP_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__ISP__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__RESET_ENABLE__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__RLC_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__RLC__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__ROM_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__ROM__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SAMMSP__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SDMA0_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SDMA1_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SDMA1__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SH1_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SH1__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SH2_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SH2__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SH3_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SH3__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SH_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SH__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__SRBM_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__SRBM__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__UVD_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__UVD__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__VCE0_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__VCE0__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__VCE1_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__VCE1__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__VMC_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__VMC__SHIFT
- IH_RESET_INCOMPLETE_INT_CNTL__XDMA_MASK
- IH_RESET_INCOMPLETE_INT_CNTL__XDMA__SHIFT
- IH_RING_ID
- IH_RING_ID_INTERRUPT
- IH_RING_ID_REQUEST
- IH_RING_ID_RESERVED
- IH_RING_ID_TRANSLATION
- IH_SCRATCH__DATA_MASK
- IH_SCRATCH__DATA__SHIFT
- IH_SIZE
- IH_STATUS__BIF_INTERRUPT_LINE_MASK
- IH_STATUS__BIF_INTERRUPT_LINE__SHIFT
- IH_STATUS__BUFFER_IDLE_MASK
- IH_STATUS__BUFFER_IDLE__SHIFT
- IH_STATUS__IDLE_MASK
- IH_STATUS__IDLE__SHIFT
- IH_STATUS__INPUT_IDLE_MASK
- IH_STATUS__INPUT_IDLE__SHIFT
- IH_STATUS__MC_WR_CLEAN_PENDING_MASK
- IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT
- IH_STATUS__MC_WR_CLEAN_STALL_MASK
- IH_STATUS__MC_WR_CLEAN_STALL__SHIFT
- IH_STATUS__MC_WR_IDLE_MASK
- IH_STATUS__MC_WR_IDLE__SHIFT
- IH_STATUS__MC_WR_STALL_MASK
- IH_STATUS__MC_WR_STALL__SHIFT
- IH_STATUS__RB1_FULL_DRAIN_MASK
- IH_STATUS__RB1_FULL_DRAIN__SHIFT
- IH_STATUS__RB1_FULL_MASK
- IH_STATUS__RB1_FULL__SHIFT
- IH_STATUS__RB1_OVERFLOW_MASK
- IH_STATUS__RB1_OVERFLOW__SHIFT
- IH_STATUS__RB2_FULL_DRAIN_MASK
- IH_STATUS__RB2_FULL_DRAIN__SHIFT
- IH_STATUS__RB2_FULL_MASK
- IH_STATUS__RB2_FULL__SHIFT
- IH_STATUS__RB2_OVERFLOW_MASK
- IH_STATUS__RB2_OVERFLOW__SHIFT
- IH_STATUS__RB_FULL_DRAIN_MASK
- IH_STATUS__RB_FULL_DRAIN__SHIFT
- IH_STATUS__RB_FULL_MASK
- IH_STATUS__RB_FULL__SHIFT
- IH_STATUS__RB_IDLE_MASK
- IH_STATUS__RB_IDLE__SHIFT
- IH_STATUS__RB_OVERFLOW_MASK
- IH_STATUS__RB_OVERFLOW__SHIFT
- IH_STATUS__SELF_INT_GEN_IDLE_MASK
- IH_STATUS__SELF_INT_GEN_IDLE__SHIFT
- IH_STATUS__SWITCH_READY_MASK
- IH_STATUS__SWITCH_READY__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT
- IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK
- IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT
- IH_VERSION__MAJVER_MASK
- IH_VERSION__MAJVER__SHIFT
- IH_VERSION__MINVER_MASK
- IH_VERSION__MINVER__SHIFT
- IH_VERSION__REV_MASK
- IH_VERSION__REV__SHIFT
- IH_VERSION__VALUE_MASK
- IH_VERSION__VALUE__SHIFT
- IH_VF_ENABLE__VALUE_MASK
- IH_VF_ENABLE__VALUE__SHIFT
- IH_VF_RB1_STATUS2__RB_FULL_VF_MASK
- IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT
- IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK
- IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT
- IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK
- IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT
- IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK
- IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT
- IH_VF_RB2_STATUS2__RB_FULL_VF_MASK
- IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT
- IH_VF_RB2_STATUS3__RB_OVERFLOW_VF_MASK
- IH_VF_RB2_STATUS3__RB_OVERFLOW_VF__SHIFT
- IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK
- IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT
- IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK
- IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT
- IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF_MASK
- IH_VF_RB_BIF_STATUS__BIF_INTERRUPT_LINE_VF__SHIFT
- IH_VF_RB_BIF_STATUS__RB_FULL_VF_MASK
- IH_VF_RB_BIF_STATUS__RB_FULL_VF__SHIFT
- IH_VF_RB_SELECT
- IH_VF_RB_SELECT_CLIENT_FCN_ID
- IH_VF_RB_SELECT_IH_FCN_ID
- IH_VF_RB_SELECT_PF
- IH_VF_RB_SELECT_RESERVED
- IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK
- IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT
- IH_VF_RB_STATUS2__RB_FULL_VF_MASK
- IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT
- IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK
- IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT
- IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK
- IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT
- IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK
- IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT
- IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK
- IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT
- IH_VIRT_RESET_REQ__PF_MASK
- IH_VIRT_RESET_REQ__PF__SHIFT
- IH_VIRT_RESET_REQ__VF_MASK
- IH_VIRT_RESET_REQ__VF__SHIFT
- IH_VMID_0_LUT
- IH_VMID_0_LUT_MM__PASID_MASK
- IH_VMID_0_LUT_MM__PASID__SHIFT
- IH_VMID_0_LUT__PASID_MASK
- IH_VMID_0_LUT__PASID__SHIFT
- IH_VMID_10_LUT_MM__PASID_MASK
- IH_VMID_10_LUT_MM__PASID__SHIFT
- IH_VMID_10_LUT__PASID_MASK
- IH_VMID_10_LUT__PASID__SHIFT
- IH_VMID_11_LUT_MM__PASID_MASK
- IH_VMID_11_LUT_MM__PASID__SHIFT
- IH_VMID_11_LUT__PASID_MASK
- IH_VMID_11_LUT__PASID__SHIFT
- IH_VMID_12_LUT_MM__PASID_MASK
- IH_VMID_12_LUT_MM__PASID__SHIFT
- IH_VMID_12_LUT__PASID_MASK
- IH_VMID_12_LUT__PASID__SHIFT
- IH_VMID_13_LUT_MM__PASID_MASK
- IH_VMID_13_LUT_MM__PASID__SHIFT
- IH_VMID_13_LUT__PASID_MASK
- IH_VMID_13_LUT__PASID__SHIFT
- IH_VMID_14_LUT_MM__PASID_MASK
- IH_VMID_14_LUT_MM__PASID__SHIFT
- IH_VMID_14_LUT__PASID_MASK
- IH_VMID_14_LUT__PASID__SHIFT
- IH_VMID_15_LUT_MM__PASID_MASK
- IH_VMID_15_LUT_MM__PASID__SHIFT
- IH_VMID_15_LUT__PASID_MASK
- IH_VMID_15_LUT__PASID__SHIFT
- IH_VMID_1_LUT_MM__PASID_MASK
- IH_VMID_1_LUT_MM__PASID__SHIFT
- IH_VMID_1_LUT__PASID_MASK
- IH_VMID_1_LUT__PASID__SHIFT
- IH_VMID_2_LUT_MM__PASID_MASK
- IH_VMID_2_LUT_MM__PASID__SHIFT
- IH_VMID_2_LUT__PASID_MASK
- IH_VMID_2_LUT__PASID__SHIFT
- IH_VMID_3_LUT_MM__PASID_MASK
- IH_VMID_3_LUT_MM__PASID__SHIFT
- IH_VMID_3_LUT__PASID_MASK
- IH_VMID_3_LUT__PASID__SHIFT
- IH_VMID_4_LUT_MM__PASID_MASK
- IH_VMID_4_LUT_MM__PASID__SHIFT
- IH_VMID_4_LUT__PASID_MASK
- IH_VMID_4_LUT__PASID__SHIFT
- IH_VMID_5_LUT_MM__PASID_MASK
- IH_VMID_5_LUT_MM__PASID__SHIFT
- IH_VMID_5_LUT__PASID_MASK
- IH_VMID_5_LUT__PASID__SHIFT
- IH_VMID_6_LUT_MM__PASID_MASK
- IH_VMID_6_LUT_MM__PASID__SHIFT
- IH_VMID_6_LUT__PASID_MASK
- IH_VMID_6_LUT__PASID__SHIFT
- IH_VMID_7_LUT_MM__PASID_MASK
- IH_VMID_7_LUT_MM__PASID__SHIFT
- IH_VMID_7_LUT__PASID_MASK
- IH_VMID_7_LUT__PASID__SHIFT
- IH_VMID_8_LUT_MM__PASID_MASK
- IH_VMID_8_LUT_MM__PASID__SHIFT
- IH_VMID_8_LUT__PASID_MASK
- IH_VMID_8_LUT__PASID__SHIFT
- IH_VMID_9_LUT_MM__PASID_MASK
- IH_VMID_9_LUT_MM__PASID__SHIFT
- IH_VMID_9_LUT__PASID_MASK
- IH_VMID_9_LUT__PASID__SHIFT
- IH_WPTR_OVERFLOW_CLEAR
- IH_WPTR_OVERFLOW_ENABLE
- IH_WPTR_WRITEBACK_ENABLE
- IH_WPTR_WRITEBACK_TIMER
- II
- II20K_AI_16BIT_DATA_REG
- II20K_AI_CHANLIST_CHAN
- II20K_AI_CHANLIST_GAIN
- II20K_AI_CHANLIST_LEN
- II20K_AI_CHANLIST_MUX_ENA
- II20K_AI_CHANLIST_ONBOARD_ONLY
- II20K_AI_CHANLIST_REG
- II20K_AI_CHAN_ADV_REG
- II20K_AI_CHAN_RESET_REG
- II20K_AI_CONF_ENA
- II20K_AI_CONF_REG
- II20K_AI_COUNT_RESET_REG
- II20K_AI_CUR_ADDR_REG
- II20K_AI_DELAY_LSB_REG
- II20K_AI_DELAY_MSB_REG
- II20K_AI_LAST_CHAN_ADDR_REG
- II20K_AI_LSB_REG
- II20K_AI_MSB_REG
- II20K_AI_OPT_BURST_MODE
- II20K_AI_OPT_REG
- II20K_AI_OPT_TIMEBASE
- II20K_AI_OPT_TRIG_ENA
- II20K_AI_OPT_TRIG_INV
- II20K_AI_PACER_RESET_REG
- II20K_AI_SET_TIME_REG
- II20K_AI_START_TRIG_REG
- II20K_AI_STATUS_CMD_BUSY
- II20K_AI_STATUS_CMD_EXT_START
- II20K_AI_STATUS_CMD_HW_ENA
- II20K_AI_STATUS_CMD_REG
- II20K_AI_STATUS_DATA_ERR
- II20K_AI_STATUS_INT
- II20K_AI_STATUS_PACER_ERR
- II20K_AI_STATUS_REG
- II20K_AI_STATUS_SET_TIME_ERR
- II20K_AI_STATUS_TRIG
- II20K_AI_STATUS_TRIG_ENA
- II20K_AO_LSB_REG
- II20K_AO_MSB_REG
- II20K_AO_STRB_BOTH_REG
- II20K_AO_STRB_REG
- II20K_BUF_DISAB_DIO0
- II20K_BUF_DISAB_DIO1
- II20K_BUF_DISAB_DIO2
- II20K_BUF_DISAB_DIO3
- II20K_CTRL01_DIO0_IN
- II20K_CTRL01_DIO1_IN
- II20K_CTRL01_REG
- II20K_CTRL01_SET
- II20K_CTRL23_DIO2_IN
- II20K_CTRL23_DIO3_IN
- II20K_CTRL23_REG
- II20K_CTRL23_SET
- II20K_DIO0_REG
- II20K_DIO1_REG
- II20K_DIO2_REG
- II20K_DIO3_REG
- II20K_DIR_DIO0_OUT
- II20K_DIR_DIO1_OUT
- II20K_DIR_DIO2_OUT
- II20K_DIR_DIO3_OUT
- II20K_DIR_ENA_REG
- II20K_ID_MASK
- II20K_ID_MOD1_EMPTY
- II20K_ID_MOD2_EMPTY
- II20K_ID_MOD3_EMPTY
- II20K_ID_PCI20001C_1A
- II20K_ID_PCI20001C_2A
- II20K_ID_PCI20006M_1
- II20K_ID_PCI20006M_2
- II20K_ID_PCI20341M_1
- II20K_ID_REG
- II20K_MOD_OFFSET
- II20K_MOD_STATUS_IRQ_MOD1
- II20K_MOD_STATUS_IRQ_MOD2
- II20K_MOD_STATUS_IRQ_MOD3
- II20K_MOD_STATUS_REG
- II20K_SIZE
- IIC
- IIC0
- IIC0_0
- IIC0_1
- IIC0_2
- IIC0_3
- IIC0_RSTCTRL
- IIC0_SCL_B_MARK
- IIC0_SCL_C_MARK
- IIC0_SCL_D_MARK
- IIC0_SCL_MARK
- IIC0_SDA_B_MARK
- IIC0_SDA_C_MARK
- IIC0_SDA_D_MARK
- IIC0_SDA_MARK
- IIC1
- IIC1_0
- IIC1_1
- IIC1_2
- IIC1_3
- IIC1_RSTCTRL
- IIC1_SCL_B_MARK
- IIC1_SCL_C_MARK
- IIC1_SCL_MARK
- IIC1_SDA_B_MARK
- IIC1_SDA_C_MARK
- IIC1_SDA_MARK
- IIC2_0
- IIC2_1
- IIC2_2
- IIC2_3
- IIC2_SCL_B_MARK
- IIC2_SCL_C_MARK
- IIC2_SCL_D_MARK
- IIC2_SCL_E_MARK
- IIC2_SCL_MARK
- IIC2_SDA_B_MARK
- IIC2_SDA_C_MARK
- IIC2_SDA_D_MARK
- IIC2_SDA_E_MARK
- IIC2_SDA_MARK
- IIC3
- IIC30
- IIC31
- IIC32
- IIC33
- IIC3_0
- IIC3_1
- IIC3_2
- IIC3_3
- IIC3_SCL_MARK
- IIC3_SDA_MARK
- IIC4_0
- IIC4_1
- IIC4_2
- IIC4_3
- IIC5_0
- IIC5_1
- IIC5_2
- IIC5_3
- IIC6_0
- IIC6_1
- IIC6_2
- IIC6_3
- IIC7_0
- IIC7_1
- IIC7_2
- IIC7_3
- IIC8_0
- IIC8_1
- IIC8_2
- IIC8_3
- IIC9_0
- IIC9_1
- IIC9_2
- IIC9_3
- IICCC
- IICE
- IICSTA
- IICTFR
- IIC_24C01_addr
- IIC_CLK
- IIC_CLK_DUR
- IIC_CSR1
- IIC_CSR2
- IIC_DATA
- IIC_E
- IIC_EA
- IIC_EF
- IIC_EL
- IIC_ER
- IIC_EW
- IIC_FLAG_HAS_ICIC67
- IIC_INT_REG_ACK_ERR
- IIC_INT_REG_BIT_FSM_ERR
- IIC_INT_REG_BUS_FSM_ERR
- IIC_INT_REG_CYCLE_FSM_ERR
- IIC_INT_REG_REQ_FSM_ERR
- IIC_IRQ_CLASS_0
- IIC_IRQ_CLASS_1
- IIC_IRQ_CLASS_2
- IIC_IRQ_CLASS_SHIFT
- IIC_IRQ_EXT_IOIF0
- IIC_IRQ_EXT_IOIF1
- IIC_IRQ_INVALID
- IIC_IRQ_IOEX_ATI
- IIC_IRQ_IOEX_ELDI
- IIC_IRQ_IOEX_MATBFI
- IIC_IRQ_IOEX_PMI
- IIC_IRQ_IOEX_TMI
- IIC_IRQ_MAX
- IIC_IRQ_NODE_MASK
- IIC_IRQ_NODE_SHIFT
- IIC_IRQ_TYPE_IOEXC
- IIC_IRQ_TYPE_IPI
- IIC_IRQ_TYPE_MASK
- IIC_IRQ_TYPE_NORMAL
- IIC_ISR_EDGE_MASK
- IIC_NODE_COUNT
- IIC_READ
- IIC_RX_FIFO_DEPTH
- IIC_S
- IIC_SCL_MARK
- IIC_SDA_MARK
- IIC_SMB_WITHOUT_DATA_LEN
- IIC_SMB_WITH_DATA_LEN
- IIC_SOURCE_COUNT
- IIC_STATE_IDLE
- IIC_STATE_READ
- IIC_STATE_START
- IIC_STATE_STOP
- IIC_STATE_WRITE
- IIC_TX_FIFO_DEPTH
- IIC_UNIT_IIC
- IIC_UNIT_IOC_0
- IIC_UNIT_IOC_1
- IIC_UNIT_SPU_0
- IIC_UNIT_SPU_1
- IIC_UNIT_SPU_2
- IIC_UNIT_SPU_3
- IIC_UNIT_SPU_4
- IIC_UNIT_SPU_5
- IIC_UNIT_SPU_6
- IIC_UNIT_SPU_7
- IIC_UNIT_THREAD_0
- IIC_UNIT_THREAD_1
- IIC_WRITE
- IID
- IIEN
- IIF_ALL
- IIF_BGRACE
- IIF_FLAGS
- IIF_IGRACE
- IILIMIT_100
- IILIMIT_150
- IILIMIT_1500
- IILIMIT_2000
- IILIMIT_500
- IILIMIT_900
- IILIMIT_EXT
- IILIMIT_NONE
- IIM
- IIM_BANK_BASE
- IIM_SREV
- IIOC_SCSI_DATA
- IIO_ACCEL
- IIO_ACTIVITY
- IIO_ADC_AD7280_H_
- IIO_ADC_AD7606_H_
- IIO_ADC_AD7887_H_
- IIO_ALIGN
- IIO_ALTVOLTAGE
- IIO_ANGL
- IIO_ANGL_VEL
- IIO_ATTR
- IIO_ATTR_RO
- IIO_ATTR_RW
- IIO_ATTR_WO
- IIO_AVAIL_LIST
- IIO_AVAIL_RANGE
- IIO_BASE
- IIO_BASE_BTE0
- IIO_BASE_BTE1
- IIO_BASE_PERF
- IIO_BE
- IIO_BLOCK_STATE_ACTIVE
- IIO_BLOCK_STATE_DEAD
- IIO_BLOCK_STATE_DEQUEUED
- IIO_BLOCK_STATE_DONE
- IIO_BLOCK_STATE_QUEUED
- IIO_BTE_CRB_CNT
- IIO_BTE_CTRL_0
- IIO_BTE_DEST_0
- IIO_BTE_INT_0
- IIO_BTE_NOTIFY_0
- IIO_BTE_OFF_0
- IIO_BTE_OFF_1
- IIO_BTE_SRC_0
- IIO_BTE_STAT_0
- IIO_BUSY_BIT_POS
- IIO_CAPACITANCE
- IIO_CCT
- IIO_CDC_AD7746_H_
- IIO_CHANNEL_NUM
- IIO_CHAN_INFO_AVERAGE_RAW
- IIO_CHAN_INFO_CALIBBIAS
- IIO_CHAN_INFO_CALIBEMISSIVITY
- IIO_CHAN_INFO_CALIBHEIGHT
- IIO_CHAN_INFO_CALIBSCALE
- IIO_CHAN_INFO_CALIBWEIGHT
- IIO_CHAN_INFO_DEBOUNCE_COUNT
- IIO_CHAN_INFO_DEBOUNCE_TIME
- IIO_CHAN_INFO_ENABLE
- IIO_CHAN_INFO_FREQUENCY
- IIO_CHAN_INFO_HARDWAREGAIN
- IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY
- IIO_CHAN_INFO_HYSTERESIS
- IIO_CHAN_INFO_INT_TIME
- IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY
- IIO_CHAN_INFO_OFFSET
- IIO_CHAN_INFO_OVERSAMPLING_RATIO
- IIO_CHAN_INFO_PEAK
- IIO_CHAN_INFO_PEAK_SCALE
- IIO_CHAN_INFO_PHASE
- IIO_CHAN_INFO_PROCESSED
- IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW
- IIO_CHAN_INFO_RAW
- IIO_CHAN_INFO_SAMP_FREQ
- IIO_CHAN_INFO_SCALE
- IIO_CHAN_SOFT_TIMESTAMP
- IIO_CHAN_SOFT_TIMESTAMP_ASSIGN
- IIO_CONCENTRATION
- IIO_CONST_ATTR
- IIO_CONST_ATTR_FREQ_SCALE
- IIO_CONST_ATTR_INT_TIME_AVAIL
- IIO_CONST_ATTR_NAMED
- IIO_CONST_ATTR_OUT_WAVETYPES_AVAILABLE
- IIO_CONST_ATTR_PHASE_SCALE
- IIO_CONST_ATTR_SAMP_FREQ_AVAIL
- IIO_CONST_ATTR_TEMP_OFFSET
- IIO_CONST_ATTR_TEMP_SCALE
- IIO_COUNT
- IIO_CPU
- IIO_CURRENT
- IIO_DAC_MAX517_H_
- IIO_DAC_MCP4725_H_
- IIO_DDS_AD9832_H_
- IIO_DDS_AD9834_H_
- IIO_DDS_H_
- IIO_DEGREE_TO_RAD
- IIO_DEVICE_ATTR
- IIO_DEVICE_ATTR_NAMED
- IIO_DEVICE_ATTR_RO
- IIO_DEVICE_ATTR_RW
- IIO_DEVICE_ATTR_WO
- IIO_DEV_ATTR_AAPOS
- IIO_DEV_ATTR_ACTIVE_POWER_A_GAIN
- IIO_DEV_ATTR_ACTIVE_POWER_A_OFFSET
- IIO_DEV_ATTR_ACTIVE_POWER_B_GAIN
- IIO_DEV_ATTR_ACTIVE_POWER_B_OFFSET
- IIO_DEV_ATTR_ACTIVE_POWER_C_GAIN
- IIO_DEV_ATTR_ACTIVE_POWER_C_OFFSET
- IIO_DEV_ATTR_ACTIVE_POWER_GAIN
- IIO_DEV_ATTR_AENERGY
- IIO_DEV_ATTR_AFWATTHR
- IIO_DEV_ATTR_AIGAIN
- IIO_DEV_ATTR_AIRMS
- IIO_DEV_ATTR_AIRMSOS
- IIO_DEV_ATTR_ANGLE0
- IIO_DEV_ATTR_ANGLE1
- IIO_DEV_ATTR_ANGLE2
- IIO_DEV_ATTR_APHCAL
- IIO_DEV_ATTR_APOS
- IIO_DEV_ATTR_APPARENT_POWER_A_GAIN
- IIO_DEV_ATTR_APPARENT_POWER_B_GAIN
- IIO_DEV_ATTR_APPARENT_POWER_C_GAIN
- IIO_DEV_ATTR_AVAHR
- IIO_DEV_ATTR_AVARHR
- IIO_DEV_ATTR_AVGAIN
- IIO_DEV_ATTR_AVRMS
- IIO_DEV_ATTR_AVRMSGAIN
- IIO_DEV_ATTR_AVRMSOS
- IIO_DEV_ATTR_AWATTHR
- IIO_DEV_ATTR_BAPOS
- IIO_DEV_ATTR_BFWATTHR
- IIO_DEV_ATTR_BIGAIN
- IIO_DEV_ATTR_BIRMS
- IIO_DEV_ATTR_BIRMSOS
- IIO_DEV_ATTR_BPHCAL
- IIO_DEV_ATTR_BVAHR
- IIO_DEV_ATTR_BVARHR
- IIO_DEV_ATTR_BVGAIN
- IIO_DEV_ATTR_BVRMS
- IIO_DEV_ATTR_BVRMSGAIN
- IIO_DEV_ATTR_BVRMSOS
- IIO_DEV_ATTR_BWATTHR
- IIO_DEV_ATTR_CAPOS
- IIO_DEV_ATTR_CF1DEN
- IIO_DEV_ATTR_CF2DEN
- IIO_DEV_ATTR_CF3DEN
- IIO_DEV_ATTR_CFCYC
- IIO_DEV_ATTR_CFDEN
- IIO_DEV_ATTR_CFNUM
- IIO_DEV_ATTR_CFWATTHR
- IIO_DEV_ATTR_CHKSUM
- IIO_DEV_ATTR_CIGAIN
- IIO_DEV_ATTR_CIRMS
- IIO_DEV_ATTR_CIRMSOS
- IIO_DEV_ATTR_CPHCAL
- IIO_DEV_ATTR_CURRENT_A
- IIO_DEV_ATTR_CURRENT_A_GAIN
- IIO_DEV_ATTR_CURRENT_A_OFFSET
- IIO_DEV_ATTR_CURRENT_B
- IIO_DEV_ATTR_CURRENT_B_GAIN
- IIO_DEV_ATTR_CURRENT_B_OFFSET
- IIO_DEV_ATTR_CURRENT_C
- IIO_DEV_ATTR_CURRENT_C_GAIN
- IIO_DEV_ATTR_CURRENT_C_OFFSET
- IIO_DEV_ATTR_CVAHR
- IIO_DEV_ATTR_CVARHR
- IIO_DEV_ATTR_CVGAIN
- IIO_DEV_ATTR_CVRMS
- IIO_DEV_ATTR_CVRMSGAIN
- IIO_DEV_ATTR_CVRMSOS
- IIO_DEV_ATTR_CWATTHR
- IIO_DEV_ATTR_FREQ
- IIO_DEV_ATTR_FREQSYMBOL
- IIO_DEV_ATTR_INT_TIME_AVAIL
- IIO_DEV_ATTR_IOS
- IIO_DEV_ATTR_IPEAK
- IIO_DEV_ATTR_IPKLVL
- IIO_DEV_ATTR_IRMS
- IIO_DEV_ATTR_IRMSOS
- IIO_DEV_ATTR_LAENERGY
- IIO_DEV_ATTR_LENERGY
- IIO_DEV_ATTR_LINECYC
- IIO_DEV_ATTR_LVAENERGY
- IIO_DEV_ATTR_LVARENERGY
- IIO_DEV_ATTR_NIGAIN
- IIO_DEV_ATTR_NIRMS
- IIO_DEV_ATTR_OUTY_ENABLE
- IIO_DEV_ATTR_OUT_ENABLE
- IIO_DEV_ATTR_OUT_WAVETYPE
- IIO_DEV_ATTR_PEAKCYC
- IIO_DEV_ATTR_PGA_GAIN
- IIO_DEV_ATTR_PHASE
- IIO_DEV_ATTR_PHASESYMBOL
- IIO_DEV_ATTR_PHCAL
- IIO_DEV_ATTR_PINCONTROL_EN
- IIO_DEV_ATTR_PINCONTROL_FREQ_EN
- IIO_DEV_ATTR_PINCONTROL_PHASE_EN
- IIO_DEV_ATTR_RAENERGY
- IIO_DEV_ATTR_REACTIVE_POWER_A_GAIN
- IIO_DEV_ATTR_REACTIVE_POWER_A_OFFSET
- IIO_DEV_ATTR_REACTIVE_POWER_B_GAIN
- IIO_DEV_ATTR_REACTIVE_POWER_B_OFFSET
- IIO_DEV_ATTR_REACTIVE_POWER_C_GAIN
- IIO_DEV_ATTR_REACTIVE_POWER_C_OFFSET
- IIO_DEV_ATTR_RIPEAK
- IIO_DEV_ATTR_RVAENERGY
- IIO_DEV_ATTR_RVPEAK
- IIO_DEV_ATTR_SAGCYC
- IIO_DEV_ATTR_SAGLVL
- IIO_DEV_ATTR_SAMP_FREQ
- IIO_DEV_ATTR_SAMP_FREQ_AVAIL
- IIO_DEV_ATTR_TEMP_RAW
- IIO_DEV_ATTR_VADIV
- IIO_DEV_ATTR_VAENERGY
- IIO_DEV_ATTR_VAGAIN
- IIO_DEV_ATTR_VOLT_A
- IIO_DEV_ATTR_VOLT_A_OFFSET
- IIO_DEV_ATTR_VOLT_B
- IIO_DEV_ATTR_VOLT_B_OFFSET
- IIO_DEV_ATTR_VOLT_C
- IIO_DEV_ATTR_VOLT_C_OFFSET
- IIO_DEV_ATTR_VOS
- IIO_DEV_ATTR_VPEAK
- IIO_DEV_ATTR_VPERIOD
- IIO_DEV_ATTR_VPKLVL
- IIO_DEV_ATTR_VRMS
- IIO_DEV_ATTR_VRMSOS
- IIO_DEV_ATTR_WDIV
- IIO_DEV_ATTR_WGAIN
- IIO_DEV_MAX
- IIO_DISTANCE
- IIO_ELECTRICALCONDUCTIVITY
- IIO_ENERGY
- IIO_ENUM
- IIO_ENUM_AVAILABLE
- IIO_EVENTGEN_NO
- IIO_EVENT_ATTR_AENERGY_HALF_FULL
- IIO_EVENT_ATTR_AENERGY_OVERFLOW
- IIO_EVENT_ATTR_CYCEND
- IIO_EVENT_ATTR_IPKLVL_EXC
- IIO_EVENT_ATTR_LINE_VOLT_SAG
- IIO_EVENT_ATTR_PNEG
- IIO_EVENT_ATTR_PPOS
- IIO_EVENT_ATTR_VAENERGY_HALF_FULL
- IIO_EVENT_ATTR_VAENERGY_OVERFLOW
- IIO_EVENT_ATTR_VPKLVL_EXC
- IIO_EVENT_ATTR_ZERO_CROSS
- IIO_EVENT_CODE
- IIO_EVENT_CODE_AD7816_OTI
- IIO_EVENT_CODE_EXTRACT_CHAN
- IIO_EVENT_CODE_EXTRACT_CHAN2
- IIO_EVENT_CODE_EXTRACT_CHAN_TYPE
- IIO_EVENT_CODE_EXTRACT_DIFF
- IIO_EVENT_CODE_EXTRACT_DIR
- IIO_EVENT_CODE_EXTRACT_MODIFIER
- IIO_EVENT_CODE_EXTRACT_TYPE
- IIO_EV_DIR_EITHER
- IIO_EV_DIR_FALLING
- IIO_EV_DIR_NONE
- IIO_EV_DIR_RISING
- IIO_EV_INFO_ENABLE
- IIO_EV_INFO_HIGH_PASS_FILTER_3DB
- IIO_EV_INFO_HYSTERESIS
- IIO_EV_INFO_LOW_PASS_FILTER_3DB
- IIO_EV_INFO_PERIOD
- IIO_EV_INFO_VALUE
- IIO_EV_TYPE_CHANGE
- IIO_EV_TYPE_MAG
- IIO_EV_TYPE_MAG_ADAPTIVE
- IIO_EV_TYPE_ROC
- IIO_EV_TYPE_THRESH
- IIO_EV_TYPE_THRESH_ADAPTIVE
- IIO_FREQUENCY_AD9523_H_
- IIO_GET_EVENT_FD_IOCTL
- IIO_GRAVITY
- IIO_G_TO_M_S_2
- IIO_HUMIDITYRELATIVE
- IIO_IBCN
- IIO_IBCT_0
- IIO_IBCT_1
- IIO_IBDA_0
- IIO_IBDA_1
- IIO_IBIA_0
- IIO_IBIA_1
- IIO_IBLS_0
- IIO_IBLS_1
- IIO_IBNA_0
- IIO_IBNA_1
- IIO_IBNR_0
- IIO_IBNR_1
- IIO_IBSA_0
- IIO_IBSA_1
- IIO_ICCR
- IIO_ICCR_CMD_EJECT
- IIO_ICCR_CMD_FLUSH
- IIO_ICCR_CMD_MASK
- IIO_ICCR_CMD_NOP
- IIO_ICCR_CMD_SHFT
- IIO_ICCR_CMD_TIMEOUT
- IIO_ICCR_CMD_WAKE
- IIO_ICCR_PENDING
- IIO_ICDR
- IIO_ICDR_PND
- IIO_ICMR
- IIO_ICMR_CLR_RPPD
- IIO_ICMR_CLR_RQPD
- IIO_ICMR_CRB_VLD_MASK
- IIO_ICMR_CRB_VLD_SHFT
- IIO_ICMR_C_CNT_MASK
- IIO_ICMR_C_CNT_SHFT
- IIO_ICMR_FC_CNT_MASK
- IIO_ICMR_FC_CNT_SHFT
- IIO_ICMR_PC_VLD_MASK
- IIO_ICMR_PC_VLD_SHFT
- IIO_ICMR_PRECISE
- IIO_ICMR_P_CNT_MASK
- IIO_ICMR_P_CNT_SHFT
- IIO_ICRB_0
- IIO_ICRB_A
- IIO_ICRB_ADDR_SHFT
- IIO_ICRB_B
- IIO_ICRB_C
- IIO_ICRB_D
- IIO_ICRB_ECODE_AERR
- IIO_ICRB_ECODE_DERR
- IIO_ICRB_ECODE_PERR
- IIO_ICRB_ECODE_PRERR
- IIO_ICRB_ECODE_PWERR
- IIO_ICRB_ECODE_TOUT
- IIO_ICRB_ECODE_WERR
- IIO_ICRB_ECODE_XTERR
- IIO_ICRB_GB_REQ
- IIO_ICRB_IMSGT_BTE
- IIO_ICRB_IMSGT_CRB
- IIO_ICRB_IMSGT_SN0NET
- IIO_ICRB_IMSGT_XTALK
- IIO_ICRB_INIT_BTE0
- IIO_ICRB_INIT_BTE1
- IIO_ICRB_INIT_CRB
- IIO_ICRB_INIT_SN0NET
- IIO_ICRB_INIT_XTALK
- IIO_ICRB_IO_REQ
- IIO_ICRB_OFFSET
- IIO_ICRB_PROC0
- IIO_ICRB_PROC1
- IIO_ICRB_REQ_BLKRD
- IIO_ICRB_REQ_BWINV
- IIO_ICRB_REQ_DEX
- IIO_ICRB_REQ_DWRD
- IIO_ICRB_REQ_PIORD
- IIO_ICRB_REQ_PIOWR
- IIO_ICRB_REQ_PRDM
- IIO_ICRB_REQ_PTPWR
- IIO_ICRB_REQ_PWRM
- IIO_ICRB_REQ_QCLRD
- IIO_ICRB_REQ_RDEX
- IIO_ICRB_REQ_REXU
- IIO_ICRB_REQ_RSHU
- IIO_ICRB_REQ_WB
- IIO_ICRB_REQ_WINC
- IIO_ICRB_XTSIZE_128
- IIO_ICRB_XTSIZE_32
- IIO_ICRB_XTSIZE_DW
- IIO_ICTO
- IIO_ICTP
- IIO_IECLR
- IIO_IFDR
- IIO_IGFX_0
- IIO_IGFX_1
- IIO_IGFX_INIT
- IIO_IGFX_N_NUM_BITS
- IIO_IGFX_N_NUM_MASK
- IIO_IGFX_N_NUM_SHIFT
- IIO_IGFX_P_NUM_BITS
- IIO_IGFX_P_NUM_MASK
- IIO_IGFX_P_NUM_SHIFT
- IIO_IGFX_VLD_BITS
- IIO_IGFX_VLD_MASK
- IIO_IGFX_VLD_SHIFT
- IIO_IGFX_W_NUM_BITS
- IIO_IGFX_W_NUM_MASK
- IIO_IGFX_W_NUM_SHIFT
- IIO_IIAP
- IIO_IIBUSERR
- IIO_IIDEM
- IIO_IIDSR
- IIO_IIDSR_ENB_MASK
- IIO_IIDSR_ENB_SHIFT
- IIO_IIDSR_LVL_MASK
- IIO_IIDSR_LVL_SHIFT
- IIO_IIDSR_NODE_MASK
- IIO_IIDSR_NODE_SHIFT
- IIO_IIDSR_SENT_MASK
- IIO_IIDSR_SENT_SHIFT
- IIO_IIWA
- IIO_ILAPO
- IIO_ILAPR
- IIO_ILCSR
- IIO_ILLR
- IIO_IMEM
- IIO_IMEM_B0ESD
- IIO_IMEM_B1ESD
- IIO_IMEM_W0ESD
- IIO_IMMR
- IIO_INCLI
- IIO_INDEV_ERR_MASK
- IIO_INDEX
- IIO_INTENSITY
- IIO_INWIDGET_ACCESS
- IIO_IOPRB
- IIO_IOPRB_0
- IIO_IOPRB_8
- IIO_IOPRB_9
- IIO_IOPRB_A
- IIO_IOPRB_B
- IIO_IOPRB_C
- IIO_IOPRB_D
- IIO_IOPRB_E
- IIO_IOPRB_F
- IIO_IOWA
- IIO_IO_ERR_CLR
- IIO_IPCA
- IIO_IPCR
- IIO_IPDR
- IIO_IPDR_PND
- IIO_IPPR
- IIO_ITTE
- IIO_ITTE_BASE
- IIO_ITTE_DISABLE
- IIO_ITTE_GET
- IIO_ITTE_INVALID_WIDGET
- IIO_ITTE_IOSP
- IIO_ITTE_IOSP_MASK
- IIO_ITTE_IOSP_SHIFT
- IIO_ITTE_OFFSET_BITS
- IIO_ITTE_OFFSET_MASK
- IIO_ITTE_OFFSET_SHIFT
- IIO_ITTE_PUT
- IIO_ITTE_WIDGET_BITS
- IIO_ITTE_WIDGET_MASK
- IIO_ITTE_WIDGET_SHIFT
- IIO_IXCC
- IIO_IXTCC
- IIO_IXTT
- IIO_LE
- IIO_LIGHT
- IIO_LLP_CB_MAX
- IIO_LLP_CSR
- IIO_LLP_CSR_IS_UP
- IIO_LLP_CSR_LLP_STAT_MASK
- IIO_LLP_CSR_LLP_STAT_SHFT
- IIO_LLP_LOG
- IIO_LLP_SN_MAX
- IIO_MAGN
- IIO_MAP
- IIO_MASSCONCENTRATION
- IIO_MAX_GROUPS
- IIO_MAX_NAME_LENGTH
- IIO_MOD_CO2
- IIO_MOD_ETHANOL
- IIO_MOD_EVENT_CODE
- IIO_MOD_H2
- IIO_MOD_I
- IIO_MOD_JOGGING
- IIO_MOD_LIGHT_BLUE
- IIO_MOD_LIGHT_BOTH
- IIO_MOD_LIGHT_CLEAR
- IIO_MOD_LIGHT_DUV
- IIO_MOD_LIGHT_GREEN
- IIO_MOD_LIGHT_IR
- IIO_MOD_LIGHT_RED
- IIO_MOD_LIGHT_UV
- IIO_MOD_NORTH_MAGN
- IIO_MOD_NORTH_MAGN_TILT_COMP
- IIO_MOD_NORTH_TRUE
- IIO_MOD_NORTH_TRUE_TILT_COMP
- IIO_MOD_PM1
- IIO_MOD_PM10
- IIO_MOD_PM2P5
- IIO_MOD_PM4
- IIO_MOD_Q
- IIO_MOD_QUATERNION
- IIO_MOD_ROOT_SUM_SQUARED_X_Y
- IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z
- IIO_MOD_RUNNING
- IIO_MOD_STILL
- IIO_MOD_SUM_SQUARED_X_Y_Z
- IIO_MOD_TEMP_AMBIENT
- IIO_MOD_TEMP_OBJECT
- IIO_MOD_VOC
- IIO_MOD_WALKING
- IIO_MOD_X
- IIO_MOD_X_AND_Y
- IIO_MOD_X_AND_Y_AND_Z
- IIO_MOD_X_AND_Z
- IIO_MOD_X_OR_Y
- IIO_MOD_X_OR_Y_OR_Z
- IIO_MOD_X_OR_Z
- IIO_MOD_Y
- IIO_MOD_Y_AND_Z
- IIO_MOD_Y_OR_Z
- IIO_MOD_Z
- IIO_MOUNT_MATRIX
- IIO_M_S_2_TO_G
- IIO_NO_MOD
- IIO_NUM_CRBS
- IIO_NUM_IPRBS
- IIO_NUM_ITTES
- IIO_NUM_NORMAL_CRBS
- IIO_NUM_PC_CRBS
- IIO_NUM_PRTES
- IIO_OUTWIDGET_ACCESS
- IIO_PERF_CNT
- IIO_PH
- IIO_PHASE
- IIO_PLL_ADF4350_H_
- IIO_POSITIONRELATIVE
- IIO_POWER
- IIO_PRESSURE
- IIO_PROTECT
- IIO_PROTECT_OVRRD
- IIO_PROTECT_OVRRD_KEY
- IIO_PROXIMITY
- IIO_PRTE
- IIO_PRTE_0
- IIO_RAD_TO_DEGREE
- IIO_RESISTANCE
- IIO_ROT
- IIO_SCRATCH_BIT0_0
- IIO_SCRATCH_BIT0_1
- IIO_SCRATCH_BIT0_2
- IIO_SCRATCH_BIT0_3
- IIO_SCRATCH_BIT0_4
- IIO_SCRATCH_BIT0_5
- IIO_SCRATCH_BIT0_6
- IIO_SCRATCH_BIT0_7
- IIO_SCRATCH_BIT0_8
- IIO_SCRATCH_BIT0_9
- IIO_SCRATCH_BIT0_R
- IIO_SCRATCH_MASK
- IIO_SCRATCH_REG0
- IIO_SCRATCH_REG1
- IIO_SEPARATE
- IIO_SHARED_BY_ALL
- IIO_SHARED_BY_DIR
- IIO_SHARED_BY_TYPE
- IIO_STEPS
- IIO_TEMP
- IIO_TIMESTAMP
- IIO_UNMOD_EVENT_CODE
- IIO_UVINDEX
- IIO_VAL_FRACTIONAL
- IIO_VAL_FRACTIONAL_LOG2
- IIO_VAL_INT
- IIO_VAL_INT_MULTIPLE
- IIO_VAL_INT_PLUS_MICRO
- IIO_VAL_INT_PLUS_MICRO_DB
- IIO_VAL_INT_PLUS_NANO
- IIO_VELOCITY
- IIO_VOLTAGE
- IIO_WCR
- IIO_WCR_WID_GET
- IIO_WID
- IIO_WIDGET
- IIO_WIDGET_CTRL
- IIO_WIDGET_FLUSH
- IIO_WIDGET_STAT
- IIO_WIDGET_TOUT
- IIO_WIDPRTE
- IIO_WSTAT
- IIO_WSTAT_ECRAZY
- IIO_WSTAT_TXRETRY
- IIO_WSTAT_TXRETRY_CNT
- IIO_WSTAT_TXRETRY_MASK
- IIO_WSTAT_TXRETRY_SHFT
- IIO_WST_ERROR_MASK
- IIO_XTALKCC_TOUT
- IIO_XTALKTT_TOUT
- IIP
- IIR
- IIR1
- IIR2
- IIRQ
- IIRQ_REG
- IIR_FIFO
- IIR_FIFOES0
- IIR_FIFOES1
- IIR_IIB0
- IIR_IIB1
- IIR_IIB2
- IIR_IID1
- IIR_IID2
- IIR_IP
- IIR_LSR
- IIR_MASK
- IIR_MAX
- IIR_MSR
- IIR_NOPEND
- IIR_RX
- IIR_TIMEOUT
- IIR_TOD
- IIR_TX
- IIS
- IIS_INPUT_ENABLE
- IITV
- II_CLOCKTIME
- II_CMD_GET_ACK
- II_CMD_GET_NOACK
- II_CMD_RESTART
- II_CMD_SEND_ACK
- II_CMD_START
- II_CMD_STATUS_ABORT
- II_CMD_STATUS_ACK_BAD
- II_CMD_STATUS_ACK_GOOD
- II_CMD_STATUS_NORMAL
- II_CMD_STOP
- II_COMMAND
- II_COMMAND_COMPLETION_STATUS
- II_COMMAND_GO
- II_CONTROL
- II_CONTROL_LOCAL_RESET
- II_DATA
- II_GEN
- II_INTENABLE
- II_INTFLAG_CLEAR
- II_IO
- II_MEM
- II_MSG
- II_RESV
- IJPEG_AHB_CLK
- IJPEG_AHB_RESET
- IJPEG_AXI_CLK
- IJPEG_AXI_RESET
- IJPEG_CLK
- IJPEG_RESET
- IJPEG_SRC
- IKE_IOC_OFFSET
- IKE_MERCED_PORT
- IL3945_BROADCAST_ID
- IL3945_EEPROM_IMG_SIZE
- IL3945_EXT_BEACON_TIME_POS
- IL3945_FW_PRE
- IL3945_MAX_PROBE_REQUEST
- IL3945_MODULE_FIRMWARE
- IL3945_STATION_COUNT
- IL3945_UCODE_API_MAX
- IL3945_UCODE_API_MIN
- IL3945_UCODE_GET
- IL39_CMD_QUEUE_NUM
- IL39_LAST_OFDM_RATE
- IL39_MAX_BSM_SIZE
- IL39_MAX_DATA_SIZE
- IL39_MAX_INST_SIZE
- IL39_MAX_UCODE_BEACON_INTERVAL
- IL39_NUM_QUEUES
- IL39_RATE_HIGH_TH
- IL39_RSSI_OFFSET
- IL39_RTC_DATA_LOWER_BOUND
- IL39_RTC_DATA_SIZE
- IL39_RTC_DATA_UPPER_BOUND
- IL39_RTC_INST_LOWER_BOUND
- IL39_RTC_INST_SIZE
- IL39_RTC_INST_UPPER_BOUND
- IL39_RX_FRAME_SIZE
- IL39_SCAN_PROBE_MASK
- IL4965_BROADCAST_ID
- IL4965_CAL_NUM_BEACONS
- IL4965_DEFAULT_TX_RETRY
- IL4965_EEPROM_IMG_SIZE
- IL4965_EXT_BEACON_TIME_POS
- IL4965_FIRST_AMPDU_QUEUE
- IL4965_FW_PRE
- IL4965_MAX_RATE
- IL4965_MODULE_FIRMWARE
- IL4965_RSSI_OFFSET
- IL4965_RS_NAME
- IL4965_RTC_INST_LOWER_BOUND
- IL4965_STATION_COUNT
- IL4965_UCODE_API_MAX
- IL4965_UCODE_API_MIN
- IL49_AGC_DB_MASK
- IL49_AGC_DB_POS
- IL49_CMD_FIFO_NUM
- IL49_FIRST_AMPDU_QUEUE
- IL49_MAX_BSM_SIZE
- IL49_MAX_DATA_SIZE
- IL49_MAX_INST_SIZE
- IL49_NUM_AMPDU_QUEUES
- IL49_NUM_FIFOS
- IL49_NUM_QUEUES
- IL49_RTC_DATA_LOWER_BOUND
- IL49_RTC_DATA_SIZE
- IL49_RTC_DATA_UPPER_BOUND
- IL49_RTC_INST_LOWER_BOUND
- IL49_RTC_INST_SIZE
- IL49_RTC_INST_UPPER_BOUND
- IL49_RX_PHY_FLAGS_ANTENNAE_MASK
- IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET
- IL49_RX_RES_PHY_CNT
- IL49_SCD_CONTEXT_DATA_OFFSET
- IL49_SCD_CONTEXT_QUEUE_OFFSET
- IL49_SCD_DRAM_BASE_ADDR
- IL49_SCD_EMPTY_BITS
- IL49_SCD_INTERRUPT_MASK
- IL49_SCD_QUEUECHAIN_SEL
- IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK
- IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS
- IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
- IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
- IL49_SCD_QUEUE_RDPTR
- IL49_SCD_QUEUE_STATUS_BITS
- IL49_SCD_QUEUE_STTS_REG_MSK
- IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE
- IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK
- IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN
- IL49_SCD_QUEUE_STTS_REG_POS_TXF
- IL49_SCD_QUEUE_STTS_REG_POS_WSL
- IL49_SCD_QUEUE_WRPTR
- IL49_SCD_SRAM_BASE_ADDR
- IL49_SCD_START_OFFSET
- IL49_SCD_TRANSLATE_TBL_OFFSET
- IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE
- IL49_SCD_TXFACT
- IL49_SCD_TX_STTS_BITMAP_OFFSET
- ILAR
- ILA_ATTR_CSUM_MODE
- ILA_ATTR_DIR
- ILA_ATTR_HOOK_TYPE
- ILA_ATTR_IDENTIFIER
- ILA_ATTR_IDENT_TYPE
- ILA_ATTR_IFINDEX
- ILA_ATTR_LOCATOR
- ILA_ATTR_LOCATOR_MATCH
- ILA_ATTR_MAX
- ILA_ATTR_PAD
- ILA_ATTR_UNSPEC
- ILA_ATYPE_IID
- ILA_ATYPE_LUID
- ILA_ATYPE_NONLOCAL_ADDR
- ILA_ATYPE_RSVD_1
- ILA_ATYPE_RSVD_2
- ILA_ATYPE_USE_FORMAT
- ILA_ATYPE_VIRT_MULTI_V6
- ILA_ATYPE_VIRT_UNI_V6
- ILA_ATYPE_VIRT_V4
- ILA_CMD_ADD
- ILA_CMD_DEL
- ILA_CMD_FLUSH
- ILA_CMD_GET
- ILA_CMD_MAX
- ILA_CMD_UNSPEC
- ILA_CSUM_ADJUST_TRANSPORT
- ILA_CSUM_NEUTRAL_MAP
- ILA_CSUM_NEUTRAL_MAP_AUTO
- ILA_CSUM_NO_ACTION
- ILA_DIR_IN
- ILA_DIR_OUT
- ILA_GENL_NAME
- ILA_GENL_VERSION
- ILA_HASH_TABLE_SIZE
- ILA_HOOK_ROUTE_INPUT
- ILA_HOOK_ROUTE_OUTPUT
- ILB_REMAP_SIZE
- ILCR_FLV_MASK
- ILCR_FLV_SHIFT
- ILCR_HLVH_MASK
- ILCR_HLVH_SHIFT
- ILCR_HLVL_MASK
- ILCR_HLVL_SHIFT
- ILCR_SLV_MASK
- ILCR_SLV_SHIFT
- ILCSR_WARM_RESET
- ILE_EINT0
- ILE_EINT1
- ILF
- ILF1
- ILGAL_REQ
- ILGL_INST_DETECTED
- ILGL_INST_INT
- ILI
- ILI210X_TOUCHES
- ILI251X_TOUCHES
- ILI9225_BLANK_PERIOD_CONTROL_1
- ILI9225_DISPLAY_CONTROL_1
- ILI9225_DRIVER_OUTPUT_CONTROL
- ILI9225_DRIVER_READ_CODE
- ILI9225_ENTRY_MODE
- ILI9225_FRAME_CYCLE_CONTROL
- ILI9225_GAMMA_CONTROL_1
- ILI9225_GAMMA_CONTROL_10
- ILI9225_GAMMA_CONTROL_2
- ILI9225_GAMMA_CONTROL_3
- ILI9225_GAMMA_CONTROL_4
- ILI9225_GAMMA_CONTROL_5
- ILI9225_GAMMA_CONTROL_6
- ILI9225_GAMMA_CONTROL_7
- ILI9225_GAMMA_CONTROL_8
- ILI9225_GAMMA_CONTROL_9
- ILI9225_GATE_SCAN_CONTROL
- ILI9225_HORIZ_WINDOW_ADDR_1
- ILI9225_HORIZ_WINDOW_ADDR_2
- ILI9225_INTERFACE_CONTROL
- ILI9225_LCD_AC_DRIVING_CONTROL
- ILI9225_OSCILLATION_CONTROL
- ILI9225_PARTIAL_DRIVING_POS_1
- ILI9225_PARTIAL_DRIVING_POS_2
- ILI9225_POWER_CONTROL_1
- ILI9225_POWER_CONTROL_2
- ILI9225_POWER_CONTROL_3
- ILI9225_POWER_CONTROL_4
- ILI9225_POWER_CONTROL_5
- ILI9225_RAM_ADDRESS_SET_1
- ILI9225_RAM_ADDRESS_SET_2
- ILI9225_SOFTWARE_RESET
- ILI9225_VCI_RECYCLING
- ILI9225_VERTICAL_SCROLL_1
- ILI9225_VERTICAL_SCROLL_2
- ILI9225_VERTICAL_SCROLL_3
- ILI9225_VERT_WINDOW_ADDR_1
- ILI9225_VERT_WINDOW_ADDR_2
- ILI9225_WRITE_DATA_TO_GRAM
- ILI9320_BASEIMAGE_NDL
- ILI9320_BASEIMAGE_REV
- ILI9320_BASEIMAGE_VLE
- ILI9320_BASE_IMAGE
- ILI9320_DISPLAY1
- ILI9320_DISPLAY1_BASEE
- ILI9320_DISPLAY1_CL
- ILI9320_DISPLAY1_D
- ILI9320_DISPLAY1_DTE
- ILI9320_DISPLAY1_GON
- ILI9320_DISPLAY1_PTDE
- ILI9320_DISPLAY2
- ILI9320_DISPLAY2_BP
- ILI9320_DISPLAY2_FP
- ILI9320_DISPLAY3
- ILI9320_DISPLAY4
- ILI9320_DRIVER
- ILI9320_DRIVER2
- ILI9320_DRIVER2_GS
- ILI9320_DRIVER2_NL
- ILI9320_DRIVER2_SCNL
- ILI9320_DRIVER_SM
- ILI9320_DRIVER_SS
- ILI9320_DRIVEWAVE
- ILI9320_DRIVEWAVE_BC
- ILI9320_DRIVEWAVE_EOR
- ILI9320_DRIVEWAVE_MUSTSET
- ILI9320_ENTRYMODE
- ILI9320_ENTRYMODE_AM
- ILI9320_ENTRYMODE_BGR
- ILI9320_ENTRYMODE_DFM
- ILI9320_ENTRYMODE_HWM
- ILI9320_ENTRYMODE_ID
- ILI9320_ENTRYMODE_ORG
- ILI9320_ENTRYMODE_TRI
- ILI9320_FRAMEMAKER
- ILI9320_FRAME_RATE_COLOUR
- ILI9320_GAMMA1
- ILI9320_GAMMA10
- ILI9320_GAMMA2
- ILI9320_GAMMA3
- ILI9320_GAMMA4
- ILI9320_GAMMA5
- ILI9320_GAMMA6
- ILI9320_GAMMA7
- ILI9320_GAMMA8
- ILI9320_GAMMA9
- ILI9320_GRAM_HORIZ_ADDR
- ILI9320_GRAM_VERT_ADD
- ILI9320_HORIZ_END
- ILI9320_HORIZ_START
- ILI9320_INDEX
- ILI9320_INTERFACE1
- ILI9320_INTERFACE2
- ILI9320_INTERFACE3
- ILI9320_INTERFACE4
- ILI9320_INTERFACE4_DIVE
- ILI9320_INTERFACE4_RTNE
- ILI9320_INTERFACE5
- ILI9320_INTERFACE6
- ILI9320_OSCILATION
- ILI9320_OSCILATION_OSC
- ILI9320_PARTIAL1_END
- ILI9320_PARTIAL1_POSITION
- ILI9320_PARTIAL1_START
- ILI9320_PARTIAL2_END
- ILI9320_PARTIAL2_POSITION
- ILI9320_PARTIAL2_START
- ILI9320_POWER1
- ILI9320_POWER1_AP
- ILI9320_POWER1_APE
- ILI9320_POWER1_BT
- ILI9320_POWER1_DSTB
- ILI9320_POWER1_SAP
- ILI9320_POWER1_SLP
- ILI9320_POWER2
- ILI9320_POWER2_DC0
- ILI9320_POWER2_DC1
- ILI9320_POWER2_VC
- ILI9320_POWER3
- ILI9320_POWER3_PON
- ILI9320_POWER3_VCMR
- ILI9320_POWER3_VRH
- ILI9320_POWER4
- ILI9320_POWER4_VREOUT
- ILI9320_POWER7
- ILI9320_REG
- ILI9320_RESIZING
- ILI9320_RESIZING_RCH
- ILI9320_RESIZING_RCV
- ILI9320_RESIZING_RSZ
- ILI9320_RGBIF1_CLK_INT
- ILI9320_RGBIF1_CLK_RGBIF
- ILI9320_RGBIF1_CLK_VSYNC
- ILI9320_RGBIF1_ENC_FRAMES
- ILI9320_RGBIF1_RIM_RGB16
- ILI9320_RGBIF1_RIM_RGB18
- ILI9320_RGBIF1_RIM_RGB6
- ILI9320_RGBIF1_RM
- ILI9320_RGBIF2_DPL
- ILI9320_RGBIF2_EPL
- ILI9320_RGBIF2_HSPL
- ILI9320_RGBIF2_VSPL
- ILI9320_RGB_IF1
- ILI9320_RGB_IF2
- ILI9320_SPI_DATA
- ILI9320_SPI_ID
- ILI9320_SPI_IDCODE
- ILI9320_SPI_INDEX
- ILI9320_SPI_READ
- ILI9320_SPI_WRITE
- ILI9320_SUSPEND_DEEP
- ILI9320_SUSPEND_OFF
- ILI9320_VERT_END
- ILI9320_VERT_SCROLL
- ILI9320_VERT_START
- ILI9322_CHIP_ID
- ILI9322_CHIP_ID_MAGIC
- ILI9322_ENTRY
- ILI9322_ENTRY_AUTODETECT
- ILI9322_ENTRY_DISABLE_1
- ILI9322_ENTRY_DISABLE_2
- ILI9322_ENTRY_HDIR
- ILI9322_ENTRY_ITU_R_BT_656_640X320
- ILI9322_ENTRY_ITU_R_BT_656_720X360
- ILI9322_ENTRY_NTSC
- ILI9322_ENTRY_PAL
- ILI9322_ENTRY_PARALLEL_RGB_ALIGNED
- ILI9322_ENTRY_PARALLEL_RGB_THROUGH
- ILI9322_ENTRY_SERIAL_RGB_ALIGNED
- ILI9322_ENTRY_SERIAL_RGB_DUMMY_320X240
- ILI9322_ENTRY_SERIAL_RGB_DUMMY_360X240
- ILI9322_ENTRY_SERIAL_RGB_THROUGH
- ILI9322_ENTRY_VDIR
- ILI9322_ENTRY_YUV_640Y_320CBCR_25_54_MHZ
- ILI9322_ENTRY_YUV_720Y_360CBCR_27_MHZ
- ILI9322_GAMMA_1
- ILI9322_GAMMA_2
- ILI9322_GAMMA_3
- ILI9322_GAMMA_4
- ILI9322_GAMMA_5
- ILI9322_GAMMA_6
- ILI9322_GAMMA_7
- ILI9322_GAMMA_8
- ILI9322_GLOBAL_RESET
- ILI9322_GLOBAL_RESET_ASSERT
- ILI9322_HBP
- ILI9322_IF_CTRL
- ILI9322_IF_CTRL_DE_ONLY
- ILI9322_IF_CTRL_HSYNC_VSYNC
- ILI9322_IF_CTRL_HSYNC_VSYNC_DE
- ILI9322_IF_CTRL_LINE_INVERSION
- ILI9322_IF_CTRL_SYNC_DISABLED
- ILI9322_INPUT_DISABLED_1
- ILI9322_INPUT_DISABLED_2
- ILI9322_INPUT_ITU_R_BT656_640X320_YCBCR
- ILI9322_INPUT_ITU_R_BT656_720X360_YCBCR
- ILI9322_INPUT_PRGB_ALIGNED
- ILI9322_INPUT_PRGB_THROUGH
- ILI9322_INPUT_SRGB_ALIGNED
- ILI9322_INPUT_SRGB_DUMMY_320X240
- ILI9322_INPUT_SRGB_DUMMY_360X240
- ILI9322_INPUT_SRGB_THROUGH
- ILI9322_INPUT_UNKNOWN
- ILI9322_INPUT_YUV_640X320_YCBCR
- ILI9322_INPUT_YUV_720X360_YCBCR
- ILI9322_POL
- ILI9322_POL_DCLK
- ILI9322_POL_DE
- ILI9322_POL_FORMULA
- ILI9322_POL_HSYNC
- ILI9322_POL_REV
- ILI9322_POL_VSYNC
- ILI9322_POL_YCBCR_MODE
- ILI9322_POW_CTRL
- ILI9322_POW_CTRL_AUTO
- ILI9322_POW_CTRL_DDVDH
- ILI9322_POW_CTRL_DEFAULT
- ILI9322_POW_CTRL_STANDBY
- ILI9322_POW_CTRL_STB
- ILI9322_POW_CTRL_VCL
- ILI9322_POW_CTRL_VCOM
- ILI9322_POW_CTRL_VGH
- ILI9322_POW_CTRL_VGL
- ILI9322_VBP
- ILI9322_VCOM_AMP
- ILI9322_VCOM_HIGH
- ILI9322_VREG1_VOLTAGE
- ILI9340_MADCTL_MV
- ILI9340_MADCTL_MX
- ILI9340_MADCTL_MY
- ILI9341_DISCTRL
- ILI9341_DTCTRLA
- ILI9341_DTCTRLB
- ILI9341_EN3GAM
- ILI9341_ETMOD
- ILI9341_FRMCTR1
- ILI9341_MADCTL_BGR
- ILI9341_MADCTL_MV
- ILI9341_MADCTL_MX
- ILI9341_MADCTL_MY
- ILI9341_NGAMCTRL
- ILI9341_PGAMCTRL
- ILI9341_PUMPCTRL
- ILI9341_PWCTRL1
- ILI9341_PWCTRL2
- ILI9341_PWCTRLA
- ILI9341_PWCTRLB
- ILI9341_PWRSEQ
- ILI9341_VMCTRL1
- ILI9341_VMCTRL2
- ILI9881C_COMMAND
- ILI9881C_COMMAND_INSTR
- ILI9881C_SWITCH_PAGE
- ILI9881C_SWITCH_PAGE_INSTR
- ILITEK_DEVICE_ID
- ILITEK_DEVICE_ID_MASK
- ILITEK_MAX_FREQ_REG
- ILK_BSD_USER_INTERRUPT
- ILK_COLORS
- ILK_CSC_COEFF_1_0
- ILK_CSC_COEFF_FP
- ILK_CSC_COEFF_LIMITED_RANGE
- ILK_CSC_POSTOFF_LIMITED_RANGE
- ILK_DESKTOP
- ILK_DISPLAY_CHICKEN1
- ILK_DISPLAY_CHICKEN2
- ILK_DISPLAY_DEBUG_DISABLE
- ILK_DPARBUNIT_CLOCK_GATE_ENABLE
- ILK_DPARB_GATE
- ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
- ILK_DPFCUNIT_CLOCK_GATE_DISABLE
- ILK_DPFC_CB_BASE
- ILK_DPFC_CHICKEN
- ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL
- ILK_DPFC_COMP_SEG_MASK
- ILK_DPFC_CONTROL
- ILK_DPFC_DISABLE_DUMMY0
- ILK_DPFC_FENCE_YOFF
- ILK_DPFC_NUKE_ON_ANY_MODIFICATION
- ILK_DPFC_RECOMP_CTL
- ILK_DPFC_STATUS
- ILK_DPFDUNIT_CLOCK_GATE_ENABLE
- ILK_DSPCLK_GATE_D
- ILK_ELPIN_409_SELECT
- ILK_FBCQ_DIS
- ILK_FBC_RT_BASE
- ILK_FBC_RT_VALID
- ILK_GDSR
- ILK_GRDOM_FULL
- ILK_GRDOM_MASK
- ILK_GRDOM_MEDIA
- ILK_GRDOM_RENDER
- ILK_GRDOM_RESET_ENABLE
- ILK_HDCP_DISABLE
- ILK_INTERNAL_DISPLAY_DISABLE
- ILK_INTERNAL_GRAPHICS_DISABLE
- ILK_PABSTRETCH_DIS
- ILK_SRLT_MASK
- ILK_TIMESTAMP_HI
- ILK_VRHUNIT_CLOCK_GATE_DISABLE
- ILK_VSDPFD_FULL
- ILK_eDP_A_DISABLE
- ILLEGAL_ACCESS_MASK
- ILLEGAL_BASE
- ILLEGAL_BYTE_ENABLES
- ILLEGAL_CHAR_MARK
- ILLEGAL_INSTR
- ILLEGAL_JTAG_STATE
- ILLEGAL_KEY_GROUP
- ILLEGAL_MSR_REG
- ILLEGAL_PATH_ELEMENT_OFFSET
- ILLEGAL_PHASE
- ILLEGAL_REQUEST
- ILLEGAL_STATE
- ILLEGAL_STATUS_BYTE
- ILLEGAL_VL
- ILLEGAL_XY
- ILLRDBEINT_F
- ILLRDBEINT_S
- ILLRDBEINT_V
- ILLRDINT_F
- ILLRDINT_S
- ILLRDINT_V
- ILLTRANSINT_F
- ILLTRANSINT_S
- ILLTRANSINT_V
- ILLUMINANCE_ATTR_RO
- ILLUMINANCE_ATTR_RW
- ILLUMINATORS_1_DEF
- ILLUMINATORS_2_DEF
- ILLWRBEINT_F
- ILLWRBEINT_S
- ILLWRBEINT_V
- ILLWRINT_F
- ILLWRINT_S
- ILLWRINT_V
- ILL_ACC_ID_M
- ILL_ACC_ID_S
- ILL_ACC_LEN_M
- ILL_ACC_OFF_M
- ILL_ACC_OFF_S
- ILL_ACC_WRITE
- ILL_BADIADDR
- ILL_BADSTK
- ILL_COPROC
- ILL_ILLADR
- ILL_ILLOPC
- ILL_ILLOPN
- ILL_ILLTRP
- ILL_INT_STATUS
- ILL_PRVOPC
- ILL_PRVREG
- ILMB_mskIBPA
- ILMB_mskIEN
- ILMB_mskILMSZ
- ILMB_offIBPA
- ILMB_offIEN
- ILMB_offILMSZ
- ILOG2
- ILOG2_256MB
- ILOG2_4MB
- ILOHW_CCB_SZ
- ILOSW_CCB_SZ
- ILOS_SHIFT
- ILO_CACHE_SZ
- ILO_NAME
- ILO_START_ALIGN
- ILP_CALC_DUR
- ILP_CLOCK
- ILP_DIV_1MHZ
- ILP_DIV_5MHZ
- ILQ_CREATED
- ILR_INTTGT_CINT
- ILR_INTTGT_INT
- ILR_INTTGT_MASK
- ILR_INTTGT_MCP
- ILSEL_BASE
- ILSEL_EX1
- ILSEL_EX2
- ILSEL_EX3
- ILSEL_EX4
- ILSEL_EX5
- ILSEL_EX6
- ILSEL_EX7
- ILSEL_EX8
- ILSEL_FPGA0
- ILSEL_FPGA1
- ILSEL_FPGA2
- ILSEL_FPGA3
- ILSEL_KEY
- ILSEL_LAN
- ILSEL_LEVELS
- ILSEL_NONE
- ILSEL_RTC
- ILSEL_USBH_I
- ILSEL_USBH_S
- ILSEL_USBH_V
- ILSEL_USBP_I
- ILSEL_USBP_S
- ILSEL_USBP_V
- ILS_ALL_INT0
- ILS_ALL_INT1
- ILT_ADDR1
- ILT_ADDR2
- ILT_CFG_REG
- ILT_CLIENT_CDU
- ILT_CLIENT_QM
- ILT_CLIENT_SKIP_INIT
- ILT_CLIENT_SKIP_MEM
- ILT_CLIENT_SRC
- ILT_CLIENT_TM
- ILT_CLI_CDUC
- ILT_CLI_CDUT
- ILT_CLI_MAX
- ILT_CLI_PF_BLOCKS
- ILT_CLI_QM
- ILT_CLI_SRC
- ILT_CLI_TM
- ILT_CLI_TSDM
- ILT_CLI_VF_BLOCKS
- ILT_DEFAULT_HW_P_SIZE
- ILT_ENTRY_IN_REGS
- ILT_ENTRY_PHY_ADDR_MASK
- ILT_ENTRY_PHY_ADDR_SHIFT
- ILT_ENTRY_VALID_MASK
- ILT_ENTRY_VALID_SHIFT
- ILT_MAX_L2_LINES
- ILT_MAX_LINES
- ILT_MEMOP_ALLOC
- ILT_MEMOP_FREE
- ILT_NUM_PAGE_ENTRIES
- ILT_PAGE_CIDS
- ILT_PAGE_IN_BYTES
- ILT_PAGE_SIZE_TCFC
- ILT_PER_FUNC
- ILT_RANGE
- ILT_REG_SIZE_IN_BYTES
- IL_ACTION_LIMIT
- IL_ACTIVE_DWELL_FACTOR_24GHZ
- IL_ACTIVE_DWELL_FACTOR_52GHZ
- IL_ACTIVE_DWELL_TIME_24
- IL_ACTIVE_DWELL_TIME_52
- IL_ACTIVE_QUIET_TIME
- IL_AGG_ALL_TID
- IL_AGG_LOAD_THRESHOLD
- IL_AGG_OFF
- IL_AGG_ON
- IL_AGG_TPT_THREHOLD
- IL_AGG_TX_QUEUE_MSK
- IL_ANONYMOUS
- IL_ANTENNA_AUX
- IL_ANTENNA_DIVERSITY
- IL_ANTENNA_MAIN
- IL_AP_ID
- IL_AVERAGE_PACKETS
- IL_BASIC_RATES_MASK
- IL_CAL_NUM_BEACONS
- IL_CCK_BASIC_RATES_MASK
- IL_CCK_FROM_OFDM_IDX_DIFF
- IL_CCK_FROM_OFDM_POWER_DIFF
- IL_CCK_RATES
- IL_CCK_RATES_MASK
- IL_CHAIN_NOISE_ACCUMULATE
- IL_CHAIN_NOISE_ALIVE
- IL_CHAIN_NOISE_CALIBRATED
- IL_CHAIN_NOISE_DONE
- IL_CHANNEL_TUNE_TIME
- IL_CMD
- IL_CMD_FAILED_MSK
- IL_CN_MAX
- IL_CONN_MAX_LISTEN_INTERVAL
- IL_DBG
- IL_DECLARE_RATE_INFO
- IL_DEFAULT_CMD_QUEUE_NUM
- IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE
- IL_DEFAULT_TX_RETRY
- IL_DEF_LED_INTRVL
- IL_DEF_WD_TIMEOUT
- IL_DELAY_NEXT_FORCE_FW_RELOAD
- IL_DELAY_NEXT_SCAN_AFTER_ASSOC
- IL_DELEGATE
- IL_DL_11H
- IL_DL_AP
- IL_DL_ASSOC
- IL_DL_CALIB
- IL_DL_DROP
- IL_DL_EEPROM
- IL_DL_FW
- IL_DL_FW_ERRORS
- IL_DL_HCMD
- IL_DL_HCMD_DUMP
- IL_DL_HT
- IL_DL_INFO
- IL_DL_ISR
- IL_DL_LED
- IL_DL_MAC80211
- IL_DL_MACDUMP
- IL_DL_NOTIF
- IL_DL_POWER
- IL_DL_QOS
- IL_DL_RADIO
- IL_DL_RATE
- IL_DL_RF_KILL
- IL_DL_RX
- IL_DL_SCAN
- IL_DL_STATE
- IL_DL_STATS
- IL_DL_TEMP
- IL_DL_TX
- IL_DL_TXPOWER
- IL_DL_TX_REPLY
- IL_DL_WEP
- IL_DROP_ALL
- IL_DROP_SELECTED
- IL_DROP_SINGLE
- IL_EEPROM_ACCESS_TIMEOUT
- IL_EEPROM_SEM_RETRY_LIMIT
- IL_EEPROM_SEM_TIMEOUT
- IL_EMPTYING_HW_QUEUE_ADDBA
- IL_EMPTYING_HW_QUEUE_DELBA
- IL_ERR
- IL_EVT_DISABLE
- IL_EVT_DISABLE_SIZE
- IL_FA_GOOD_RANGE
- IL_FA_TOO_FEW
- IL_FA_TOO_MANY
- IL_FIRST_CCK_RATE
- IL_FIRST_OFDM_RATE
- IL_GOOD_CRC_TH_DEFAULT
- IL_GOOD_CRC_TH_DISABLED
- IL_GOOD_CRC_TH_NEVER
- IL_HOST_INT_CALIB_TIMEOUT_DEF
- IL_HOST_INT_CALIB_TIMEOUT_MAX
- IL_HOST_INT_CALIB_TIMEOUT_MIN
- IL_HOST_INT_TIMEOUT_DEF
- IL_HOST_INT_TIMEOUT_MAX
- IL_HOST_INT_TIMEOUT_MIN
- IL_HT_NUMBER_TRY
- IL_IBSS_MANAGER
- IL_IDENTIFICATION
- IL_IMPERSONATION
- IL_INFO
- IL_INVALID_RATE
- IL_INVALID_STATION
- IL_INVALID_VALUE
- IL_KW_SIZE
- IL_LAST_CCK_RATE
- IL_LAST_OFDM_RATE
- IL_LED_ACTIVITY
- IL_LED_BLINK
- IL_LED_DEFAULT
- IL_LED_LINK
- IL_LED_RF_STATE
- IL_LED_SOLID
- IL_LEGACY_FAILURE_LIMIT
- IL_LEGACY_PM_OPS
- IL_LEGACY_SUCCESS_LIMIT
- IL_LEGACY_SWITCH_ANTENNA1
- IL_LEGACY_SWITCH_ANTENNA2
- IL_LEGACY_SWITCH_MIMO2_AB
- IL_LEGACY_SWITCH_MIMO2_AC
- IL_LEGACY_SWITCH_MIMO2_BC
- IL_LEGACY_SWITCH_SISO
- IL_LEGACY_TBL_COUNT
- IL_LONG_WD_TIMEOUT
- IL_MASK
- IL_MAX_CMD_SIZE
- IL_MAX_GAIN_ENTRIES
- IL_MAX_HW_QUEUES
- IL_MAX_MCS_DISPLAY_SIZE
- IL_MAX_PHY_CALIBRATE_TBL_SIZE
- IL_MAX_RATES
- IL_MAX_RSSI_VAL
- IL_MAX_SCAN_SIZE
- IL_MAX_SEARCH
- IL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE
- IL_MAX_UCODE_BEACON_INTERVAL
- IL_MAX_WD_TIMEOUT
- IL_MEASUREMENT_CONCURRENT
- IL_MEASUREMENT_CSA_CONFLICT
- IL_MEASUREMENT_OK
- IL_MEASUREMENT_PERIODIC_FAILED
- IL_MEASUREMENT_START
- IL_MEASUREMENT_STOP
- IL_MEASUREMENT_STOPPED
- IL_MEASUREMENT_TGH_CONFLICT
- IL_MEASUREMENT_TIMEOUT
- IL_MEASURE_BASIC
- IL_MEASURE_CHANNEL_LOAD
- IL_MEASURE_FRAME
- IL_MEASURE_HISTOGRAM_NOISE
- IL_MEASURE_HISTOGRAM_RPI
- IL_MEASURE_IDLE
- IL_MIMO2_SWITCH_ANTENNA1
- IL_MIMO2_SWITCH_ANTENNA2
- IL_MIMO2_SWITCH_GI
- IL_MIMO2_SWITCH_SISO_A
- IL_MIMO2_SWITCH_SISO_B
- IL_MIMO2_SWITCH_SISO_C
- IL_MIN_NUM_QUEUES
- IL_MIN_RSSI_VAL
- IL_MISSED_BEACON_THRESHOLD_DEF
- IL_MISSED_BEACON_THRESHOLD_MAX
- IL_MISSED_BEACON_THRESHOLD_MIN
- IL_MISSED_RATE_MAX
- IL_NOISE_MEAS_NOT_AVAILABLE
- IL_NONE_LEGACY_FAILURE_LIMIT
- IL_NONE_LEGACY_SUCCESS_LIMIT
- IL_NONE_LEGACY_TBL_COUNT
- IL_NOT_IBSS_MANAGER
- IL_NUMBER_TRY
- IL_NUM_IDLE_CHAINS_DUAL
- IL_NUM_IDLE_CHAINS_SINGLE
- IL_NUM_OF_TBS
- IL_NUM_RX_CHAINS_MULTIPLE
- IL_NUM_RX_CHAINS_SINGLE
- IL_NUM_SCAN_RATES
- IL_NUM_TX_CALIB_GROUPS
- IL_OFDM_BASIC_RATES_MASK
- IL_OFDM_RATES
- IL_OFDM_RATES_MASK
- IL_OPERATION_MODE_20MHZ
- IL_OPERATION_MODE_AUTO
- IL_OPERATION_MODE_HT_ONLY
- IL_OPERATION_MODE_MIXED
- IL_PASSIVE_DWELL_BASE
- IL_PASSIVE_DWELL_TIME_24
- IL_PASSIVE_DWELL_TIME_52
- IL_PCI_DEVICE
- IL_PHY_CALIBRATE_DIFF_GAIN_CMD
- IL_PLCP_QUIET_THRESH
- IL_PM_NO_SLEEP
- IL_PM_NUM_OF_MODES
- IL_PM_SLP_FULL_MAC_CARD_STATE
- IL_PM_SLP_FULL_MAC_UNASSOCIATE
- IL_PM_SLP_MAC
- IL_PM_SLP_PHY
- IL_PM_SLP_REPENT
- IL_PM_WAKEUP_BY_DRIVER
- IL_PM_WAKEUP_BY_RFKILL
- IL_PM_WAKEUP_BY_TIMER
- IL_POWER_DRIVER_ALLOW_SLEEP_MSK
- IL_POWER_PCI_PM_MSK
- IL_POWER_SLEEP_OVER_DTIM_MSK
- IL_POWER_VEC_SIZE
- IL_PROBE_STATUS_FAIL_BT
- IL_PROBE_STATUS_FAIL_TTL
- IL_PROBE_STATUS_OK
- IL_PROBE_STATUS_TX_FAILED
- IL_PWR_CCK_ENTRIES
- IL_PWR_NUM_HT_OFDM_ENTRIES
- IL_RS_GOOD_RATIO
- IL_RX_BUF_SIZE_3K
- IL_RX_BUF_SIZE_4K
- IL_RX_BUF_SIZE_8K
- IL_RX_DATA
- IL_RX_END
- IL_RX_FRAME_SIZE_MSK
- IL_RX_HDR
- IL_RX_STATS
- IL_SCAN_CHECK_WATCHDOG
- IL_SCAN_PROBE_MASK
- IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK
- IL_SCD_TXFIFO_POS_RA
- IL_SCD_TXFIFO_POS_TID
- IL_SHIFT
- IL_SISO_SWITCH_ANTENNA1
- IL_SISO_SWITCH_ANTENNA2
- IL_SISO_SWITCH_GI
- IL_SISO_SWITCH_MIMO2_AB
- IL_SISO_SWITCH_MIMO2_AC
- IL_SISO_SWITCH_MIMO2_BC
- IL_SKU_A
- IL_SKU_G
- IL_SKU_N
- IL_STATION_COUNT
- IL_STATS_CONF_CLEAR_STATS
- IL_STATS_CONF_DISABLE_NOTIF
- IL_STA_BCAST
- IL_STA_DRIVER_ACTIVE
- IL_STA_ID
- IL_STA_LOCAL
- IL_STA_UCODE_ACTIVE
- IL_STA_UCODE_INPROGRESS
- IL_STOP_REASON_PASSIVE
- IL_SUCCESS_DOWN_TH
- IL_SUCCESS_UP_TH
- IL_SUPPORTED_RATES_IE_LEN
- IL_TEMPERATURE_LIMIT_TIMER
- IL_TEMPERATURE_THRESHOLD
- IL_TEMP_CONVERT
- IL_TRAFFIC_ENTRIES
- IL_TRAFFIC_ENTRY_SIZE
- IL_TX_CRC_SIZE
- IL_TX_DELIMITER_SIZE
- IL_TX_DMA_MASK
- IL_TX_FIFO_AC0
- IL_TX_FIFO_AC1
- IL_TX_FIFO_AC2
- IL_TX_FIFO_AC3
- IL_TX_FIFO_BE
- IL_TX_FIFO_BE_MSK
- IL_TX_FIFO_BK
- IL_TX_FIFO_BK_MSK
- IL_TX_FIFO_HCCA_1
- IL_TX_FIFO_HCCA_2
- IL_TX_FIFO_NONE
- IL_TX_FIFO_UNUSED
- IL_TX_FIFO_VI
- IL_TX_FIFO_VI_MSK
- IL_TX_FIFO_VO
- IL_TX_FIFO_VO_MSK
- IL_TX_POWER_CCK_COMPENSATION_B_STEP
- IL_TX_POWER_CCK_COMPENSATION_C_STEP
- IL_TX_POWER_DEFAULT_REGULATORY_24
- IL_TX_POWER_DEFAULT_REGULATORY_52
- IL_TX_POWER_DEFAULT_SATURATION_24
- IL_TX_POWER_DEFAULT_SATURATION_52
- IL_TX_POWER_MIMO_REGULATORY_COMPENSATION
- IL_TX_POWER_REGULATORY_MAX
- IL_TX_POWER_REGULATORY_MIN
- IL_TX_POWER_SATURATION_MAX
- IL_TX_POWER_SATURATION_MIN
- IL_TX_POWER_TEMPERATURE_MAX
- IL_TX_POWER_TEMPERATURE_MIN
- IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE
- IL_TX_QUEUE_MSK
- IL_UCODE_API
- IL_UCODE_MAJOR
- IL_UCODE_MINOR
- IL_UCODE_SERIAL
- IL_WARN
- IL_WARN_ONCE
- IL_WD_TICK
- IM
- IM14
- IM5_2
- IM5_3
- IM7
- IM7_MASK
- IMA
- IMADDTIMER
- IMAGE975
- IMAGE985
- IMAGES_H
- IMAGETAG_CRC_START
- IMAGE_1280
- IMAGE_1600
- IMAGE_640
- IMAGE_800
- IMAGE_BOOT_CODE
- IMAGE_CONVERT_IN
- IMAGE_CONVERT_OUT
- IMAGE_DEBUG_TYPE_CODEVIEW
- IMAGE_DESCRIPTORS_BUFSIZE
- IMAGE_DLLCHARACTERISTICS_NO_BIND
- IMAGE_DLLCHARACTERISTICS_NO_ISOLATION
- IMAGE_DLLCHARACTERISTICS_NO_SEH
- IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE
- IMAGE_DLLCHARACTERISTICS_WDM_DRIVER
- IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE
- IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY
- IMAGE_DLL_CHARACTERISTICS_NX_COMPAT
- IMAGE_FILE_16BIT_MACHINE
- IMAGE_FILE_32BIT_MACHINE
- IMAGE_FILE_AGGRESSIVE_WS_TRIM
- IMAGE_FILE_BYTES_REVERSED_HI
- IMAGE_FILE_BYTES_REVERSED_LO
- IMAGE_FILE_DEBUG_STRIPPED
- IMAGE_FILE_DLL
- IMAGE_FILE_EXECUTABLE_IMAGE
- IMAGE_FILE_LARGE_ADDRESS_AWARE
- IMAGE_FILE_LINE_NUMS_STRIPPED
- IMAGE_FILE_LOCAL_SYMS_STRIPPED
- IMAGE_FILE_MACHINE_AM33
- IMAGE_FILE_MACHINE_AMD64
- IMAGE_FILE_MACHINE_ARM
- IMAGE_FILE_MACHINE_ARM64
- IMAGE_FILE_MACHINE_ARMV7
- IMAGE_FILE_MACHINE_EBC
- IMAGE_FILE_MACHINE_I386
- IMAGE_FILE_MACHINE_IA64
- IMAGE_FILE_MACHINE_M32R
- IMAGE_FILE_MACHINE_MIPS16
- IMAGE_FILE_MACHINE_MIPSFPU
- IMAGE_FILE_MACHINE_MIPSFPU16
- IMAGE_FILE_MACHINE_POWERPC
- IMAGE_FILE_MACHINE_POWERPCFP
- IMAGE_FILE_MACHINE_R4000
- IMAGE_FILE_MACHINE_SH3
- IMAGE_FILE_MACHINE_SH3DSP
- IMAGE_FILE_MACHINE_SH3E
- IMAGE_FILE_MACHINE_SH4
- IMAGE_FILE_MACHINE_SH5
- IMAGE_FILE_MACHINE_THUMB
- IMAGE_FILE_MACHINE_UNKNOWN
- IMAGE_FILE_MACHINE_WCEMIPSV2
- IMAGE_FILE_NET_RUN_FROM_SWAP
- IMAGE_FILE_OPT_PE32_MAGIC
- IMAGE_FILE_OPT_PE32_PLUS_MAGIC
- IMAGE_FILE_OPT_ROM_MAGIC
- IMAGE_FILE_RELOCS_STRIPPED
- IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP
- IMAGE_FILE_SYSTEM
- IMAGE_FILE_UP_SYSTEM_ONLY
- IMAGE_FIRMWARE_BACKUP_FCOE
- IMAGE_FIRMWARE_BACKUP_ISCSI
- IMAGE_FIRMWARE_FCOE
- IMAGE_FIRMWARE_ISCSI
- IMAGE_FIRMWARE_PHY
- IMAGE_FLAG_ADDR0
- IMAGE_FLAG_ADDR1
- IMAGE_FLASHISM_JUMPVECTOR
- IMAGE_HEADER_VERSION_10
- IMAGE_INVALID
- IMAGE_LEN
- IMAGE_LOADING
- IMAGE_MAX_HEIGHT
- IMAGE_MAX_HEIGHT_LEGACY
- IMAGE_MAX_WIDTH
- IMAGE_MAX_WIDTH_LEGACY
- IMAGE_MODE
- IMAGE_MODE_HREF_VSYNC
- IMAGE_MODE_JPEG_EN
- IMAGE_MODE_LBYTE_FIRST
- IMAGE_MODE_RAW10
- IMAGE_MODE_RGB565
- IMAGE_MODE_Y8_DVP_EN
- IMAGE_MODE_YUV422
- IMAGE_NCSI
- IMAGE_OPTION_ROM_FCOE
- IMAGE_OPTION_ROM_ISCSI
- IMAGE_OPTION_ROM_PXE
- IMAGE_ORIENTATION
- IMAGE_READY
- IMAGE_REDBOOT_CONFIG
- IMAGE_REDBOOT_DIR
- IMAGE_REL_AMD64_ABSOLUTE
- IMAGE_REL_AMD64_ADDR32
- IMAGE_REL_AMD64_ADDR32N
- IMAGE_REL_AMD64_ADDR64
- IMAGE_REL_AMD64_PAIR
- IMAGE_REL_AMD64_REL32
- IMAGE_REL_AMD64_REL32_1
- IMAGE_REL_AMD64_REL32_2
- IMAGE_REL_AMD64_REL32_3
- IMAGE_REL_AMD64_REL32_4
- IMAGE_REL_AMD64_REL32_5
- IMAGE_REL_AMD64_SECREL
- IMAGE_REL_AMD64_SECREL7
- IMAGE_REL_AMD64_SECTION
- IMAGE_REL_AMD64_SREL32
- IMAGE_REL_AMD64_SSPAN32
- IMAGE_REL_AMD64_TOKEN
- IMAGE_REL_ARM_ABSOLUTE
- IMAGE_REL_ARM_ADDR32
- IMAGE_REL_ARM_ADDR32N
- IMAGE_REL_ARM_BRANCH1
- IMAGE_REL_ARM_BRANCH2
- IMAGE_REL_ARM_SECREL
- IMAGE_REL_ARM_SECTION
- IMAGE_REL_I386_ABSOLUTE
- IMAGE_REL_I386_DIR16
- IMAGE_REL_I386_DIR32
- IMAGE_REL_I386_DIR32NB
- IMAGE_REL_I386_REL16
- IMAGE_REL_I386_REL32
- IMAGE_REL_I386_SECREL
- IMAGE_REL_I386_SECREL7
- IMAGE_REL_I386_SECTION
- IMAGE_REL_I386_SEG12
- IMAGE_REL_I386_TOKEN
- IMAGE_REL_IA64_ABSOLUTE
- IMAGE_REL_IA64_ADDEND
- IMAGE_REL_IA64_DIR32
- IMAGE_REL_IA64_DIR32NB
- IMAGE_REL_IA64_DIR64
- IMAGE_REL_IA64_GPREL22
- IMAGE_REL_IA64_GPREL32
- IMAGE_REL_IA64_IMM14
- IMAGE_REL_IA64_IMM22
- IMAGE_REL_IA64_IMM64
- IMAGE_REL_IA64_IMMGPREL6
- IMAGE_REL_IA64_LTOFF22
- IMAGE_REL_IA64_PCREL21B
- IMAGE_REL_IA64_PCREL21F
- IMAGE_REL_IA64_PCREL21M
- IMAGE_REL_IA64_PCREL60B
- IMAGE_REL_IA64_PCREL60F
- IMAGE_REL_IA64_PCREL60I
- IMAGE_REL_IA64_PCREL60M
- IMAGE_REL_IA64_PCREL60X
- IMAGE_REL_IA64_SECREL22
- IMAGE_REL_IA64_SECREL32
- IMAGE_REL_IA64_SECREL64I
- IMAGE_REL_IA64_SECTION
- IMAGE_REL_IA64_SREL14
- IMAGE_REL_IA64_SREL22
- IMAGE_REL_IA64_SREL32
- IMAGE_REL_IA64_TOKEN
- IMAGE_REL_IA64_UREL32
- IMAGE_REL_PPC_ABSOLUTE
- IMAGE_REL_PPC_ADDR14
- IMAGE_REL_PPC_ADDR16
- IMAGE_REL_PPC_ADDR24
- IMAGE_REL_PPC_ADDR32
- IMAGE_REL_PPC_ADDR32N
- IMAGE_REL_PPC_ADDR64
- IMAGE_REL_PPC_GPREL
- IMAGE_REL_PPC_PAIR
- IMAGE_REL_PPC_REFHI
- IMAGE_REL_PPC_REFLO
- IMAGE_REL_PPC_REL14
- IMAGE_REL_PPC_REL24
- IMAGE_REL_PPC_SECREL
- IMAGE_REL_PPC_SECREL16
- IMAGE_REL_PPC_SECRELLO
- IMAGE_REL_PPC_SECTION
- IMAGE_REL_PPC_TOKEN
- IMAGE_REL_SH3_ABSOLUTE
- IMAGE_REL_SH3_DIRECT16
- IMAGE_REL_SH3_DIRECT32
- IMAGE_REL_SH3_DIRECT32_NB
- IMAGE_REL_SH3_DIRECT4
- IMAGE_REL_SH3_DIRECT4_LONG
- IMAGE_REL_SH3_DIRECT4_WORD
- IMAGE_REL_SH3_DIRECT8
- IMAGE_REL_SH3_DIRECT8_LONG
- IMAGE_REL_SH3_DIRECT8_WORD
- IMAGE_REL_SH3_GPREL4_LONG
- IMAGE_REL_SH3_PCREL12_WORD
- IMAGE_REL_SH3_PCREL8_LONG
- IMAGE_REL_SH3_PCREL8_WORD
- IMAGE_REL_SH3_SECREL
- IMAGE_REL_SH3_SECTION
- IMAGE_REL_SH3_SIZEOF_SECTION
- IMAGE_REL_SH3_STARTOF_SECTION
- IMAGE_REL_SH3_TOKEN
- IMAGE_REL_SHM_NOMODE
- IMAGE_REL_SHM_PAIR
- IMAGE_REL_SHM_PCRELPT
- IMAGE_REL_SHM_REFHALF
- IMAGE_REL_SHM_REFLO
- IMAGE_REL_SHM_RELHALF
- IMAGE_REL_SHM_RELLO
- IMAGE_SCN_16BIT
- IMAGE_SCN_ALIGN_1024BYTES
- IMAGE_SCN_ALIGN_128BYTES
- IMAGE_SCN_ALIGN_16BYTES
- IMAGE_SCN_ALIGN_1BYTES
- IMAGE_SCN_ALIGN_2048BYTES
- IMAGE_SCN_ALIGN_256BYTES
- IMAGE_SCN_ALIGN_2BYTES
- IMAGE_SCN_ALIGN_32BYTES
- IMAGE_SCN_ALIGN_4096BYTES
- IMAGE_SCN_ALIGN_4BYTES
- IMAGE_SCN_ALIGN_512BYTES
- IMAGE_SCN_ALIGN_64BYTES
- IMAGE_SCN_ALIGN_8192BYTES
- IMAGE_SCN_ALIGN_8BYTES
- IMAGE_SCN_CNT_CODE
- IMAGE_SCN_CNT_INITIALIZED_DATA
- IMAGE_SCN_CNT_UNINITIALIZED_DATA
- IMAGE_SCN_GPREL
- IMAGE_SCN_LNK_COMDAT
- IMAGE_SCN_LNK_INFO
- IMAGE_SCN_LNK_NRELOC_OVFL
- IMAGE_SCN_LNK_OTHER
- IMAGE_SCN_LNK_REMOVE
- IMAGE_SCN_LOCKED
- IMAGE_SCN_MEM_DISCARDABLE
- IMAGE_SCN_MEM_EXECUTE
- IMAGE_SCN_MEM_NOT_CACHED
- IMAGE_SCN_MEM_NOT_PAGED
- IMAGE_SCN_MEM_PURGEABLE
- IMAGE_SCN_MEM_READ
- IMAGE_SCN_MEM_SHARED
- IMAGE_SCN_MEM_WRITE
- IMAGE_SCN_PRELOAD
- IMAGE_SCN_RESERVED_0
- IMAGE_SCN_RESERVED_1
- IMAGE_SCN_RESERVED_2
- IMAGE_SCN_RESERVED_3
- IMAGE_SCN_RESERVED_4
- IMAGE_SCN_RESERVED_5
- IMAGE_SCN_RESERVED_6
- IMAGE_SCN_TYPE_NO_PAD
- IMAGE_SEQUENCE_LEN
- IMAGE_SIZE
- IMAGE_START
- IMAGE_START_MAGIC
- IMAGE_SUBSYSTEM_EFI_APPLICATION
- IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER
- IMAGE_SUBSYSTEM_EFI_ROM_IMAGE
- IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER
- IMAGE_SUBSYSTEM_NATIVE
- IMAGE_SUBSYSTEM_POSIX_CUI
- IMAGE_SUBSYSTEM_UNKNOWN
- IMAGE_SUBSYSTEM_WINDOWS_CE_GUI
- IMAGE_SUBSYSTEM_WINDOWS_CUI
- IMAGE_SUBSYSTEM_WINDOWS_GUI
- IMAGE_SUBSYSTEM_XBOX
- IMAGE_TEXT_TYPE
- IMAGE_TEXT_TYPE_16
- IMAGE_TEXT_TYPE_8
- IMAGE_TRAIL_MAGIC
- IMAGE_UFI_DIR
- IMAN_IE
- IMAN_IP
- IMAPBLKNO
- IMAP_ADDR
- IMAP_AID_SAFARI
- IMAP_AID_SHIFT
- IMAP_IGN
- IMAP_INO
- IMAP_INR
- IMAP_NID_SAFARI
- IMAP_NID_SHIFT
- IMAP_TID_JBUS
- IMAP_TID_SHIFT
- IMAP_TID_UPA
- IMAP_VALID
- IMAP_VALID_SHIFT
- IMASK6
- IMASK_BABR
- IMASK_BABT
- IMASK_BSY
- IMASK_CRL
- IMASK_DEF
- IMASK_DEFAULT
- IMASK_DPE
- IMASK_EBERR
- IMASK_FAST
- IMASK_FGPI
- IMASK_FIQ
- IMASK_FIR
- IMASK_GLOBAL
- IMASK_GRSC
- IMASK_GTSC
- IMASK_INIT_CLEAR
- IMASK_LC
- IMASK_MAG
- IMASK_MSRO
- IMASK_PERR
- IMASK_PMA
- IMASK_PRIORITY
- IMASK_RXB0
- IMASK_RXC
- IMASK_RXFEN0
- IMASK_RX_DEFAULT
- IMASK_RX_DISABLED
- IMASK_SLOW
- IMASK_TXBEN
- IMASK_TXC
- IMASK_TXEEN
- IMASK_TXFEN
- IMASK_TX_DEFAULT
- IMASK_TX_DISABLED
- IMASK_XFUN
- IMAXBEL
- IMAX_CDB
- IMA_ACTION_FLAGS
- IMA_APPRAISE
- IMA_APPRAISED
- IMA_APPRAISED_SUBMASK
- IMA_APPRAISE_ENFORCE
- IMA_APPRAISE_FIRMWARE
- IMA_APPRAISE_FIX
- IMA_APPRAISE_KEXEC
- IMA_APPRAISE_LOG
- IMA_APPRAISE_MODULES
- IMA_APPRAISE_POLICY
- IMA_APPRAISE_SUBMASK
- IMA_AUDIT
- IMA_AUDITED
- IMA_BPRM_APPRAISE
- IMA_BPRM_APPRAISED
- IMA_CB_DELAY
- IMA_CHANGE_ATTR
- IMA_CHANGE_XATTR
- IMA_COLLECTED
- IMA_CREDS_APPRAISE
- IMA_CREDS_APPRAISED
- IMA_CUSTOM_POLICY
- IMA_DEFAULT_POLICY
- IMA_DIGEST_SIZE
- IMA_DIGSIG
- IMA_DIGSIG_REQUIRED
- IMA_DONE_MASK
- IMA_DO_MASK
- IMA_EUID
- IMA_EVENT_NAME_LEN_MAX
- IMA_FAIL_UNVERIFIABLE_SIGS
- IMA_FILE_APPRAISE
- IMA_FILE_APPRAISED
- IMA_FOWNER
- IMA_FSMAGIC
- IMA_FSNAME
- IMA_FSUUID
- IMA_FS_BUSY
- IMA_FUNC
- IMA_HASH
- IMA_HASHED
- IMA_HASH_BITS
- IMA_INMASK
- IMA_INTERRUPT
- IMA_MAPPED
- IMA_MASK
- IMA_MAX_DIGEST_SIZE
- IMA_MEASURE
- IMA_MEASURED
- IMA_MEASURE_HTABLE_SIZE
- IMA_MMAP_APPRAISE
- IMA_MMAP_APPRAISED
- IMA_MODSIG_ALLOWED
- IMA_MUST_MEASURE
- IMA_NEW_FILE
- IMA_PCR
- IMA_PERMIT_DIRECTIO
- IMA_READ_APPRAISE
- IMA_READ_APPRAISED
- IMA_SHOW_ASCII
- IMA_SHOW_BINARY
- IMA_SHOW_BINARY_NO_FIELD_LEN
- IMA_SHOW_BINARY_OLD_STRING_FMT
- IMA_TEMPLATE_FIELD_ID_MAX_LEN
- IMA_TEMPLATE_IMA_FMT
- IMA_TEMPLATE_IMA_NAME
- IMA_TEMPLATE_NUM_FIELDS_MAX
- IMA_UID
- IMA_UNMAPPED
- IMA_UPDATE_XATTR
- IMA_XATTR_DIGEST
- IMA_XATTR_DIGEST_NG
- IMA_XATTR_LAST
- IMBUSCR
- IMBUSCR_BUSSEL_CCI
- IMBUSCR_BUSSEL_CCI_IMCAAR
- IMBUSCR_BUSSEL_IMCAAR
- IMBUSCR_BUSSEL_MASK
- IMBUSCR_BUSSEL_SYS
- IMBUSCR_DVM
- IMC0
- IMC1
- IMCAAR
- IMCLEAR_L2
- IMCR_CCFG
- IMCR_L1DCC
- IMCR_L1DCFG
- IMCR_L1DIBAR
- IMCR_L1DINV
- IMCR_L1DIWC
- IMCR_L1DMPFAR
- IMCR_L1DMPFCR
- IMCR_L1DMPFSR
- IMCR_L1DMPLK0
- IMCR_L1DMPLK1
- IMCR_L1DMPLK2
- IMCR_L1DMPLK3
- IMCR_L1DMPLKCMD
- IMCR_L1DMPLKSTAT
- IMCR_L1DMPPA_BASE
- IMCR_L1DWB
- IMCR_L1DWBAR
- IMCR_L1DWBINV
- IMCR_L1DWIBAR
- IMCR_L1DWIWC
- IMCR_L1DWWC
- IMCR_L1PCC
- IMCR_L1PCFG
- IMCR_L1PIBAR
- IMCR_L1PINV
- IMCR_L1PIWC
- IMCR_L1PMPFAR
- IMCR_L1PMPFCR
- IMCR_L1PMPFSR
- IMCR_L1PMPLK0
- IMCR_L1PMPLK1
- IMCR_L1PMPLK2
- IMCR_L1PMPLK3
- IMCR_L1PMPLKCMD
- IMCR_L1PMPLKSTAT
- IMCR_L1PMPPA_BASE
- IMCR_L2ALLOC0
- IMCR_L2ALLOC1
- IMCR_L2ALLOC2
- IMCR_L2ALLOC3
- IMCR_L2IBAR
- IMCR_L2INV
- IMCR_L2IWC
- IMCR_L2MPFAR
- IMCR_L2MPFCR
- IMCR_L2MPFSR
- IMCR_L2MPLK0
- IMCR_L2MPLK1
- IMCR_L2MPLK2
- IMCR_L2MPLK3
- IMCR_L2MPLKCMD
- IMCR_L2MPLKSTAT
- IMCR_L2MPPA_BASE
- IMCR_L2PDSLEEP0
- IMCR_L2PDSLEEP1
- IMCR_L2PDSTAT0
- IMCR_L2PDSTAT1
- IMCR_L2PDWAKE0
- IMCR_L2PDWAKE1
- IMCR_L2WB
- IMCR_L2WBAR
- IMCR_L2WBINV
- IMCR_L2WIBAR
- IMCR_L2WIWC
- IMCR_L2WWC
- IMCR_MAR128_191
- IMCR_MAR224_239
- IMCR_MAR96_111
- IMCR_MAR_BASE
- IMCTR
- IMCTRLREQ
- IMCTR_AFE
- IMCTR_FLUSH
- IMCTR_INTEN
- IMCTR_MMUEN
- IMCTR_RTSEL_MASK
- IMCTR_RTSEL_SHIFT
- IMCTR_TRE
- IMCTR_TREN
- IMC_CNTL_BLK_CMD_OFFSET
- IMC_CNTL_BLK_MODE_OFFSET
- IMC_CNTL_BLK_OFFSET
- IMC_CPUMASK_ATTR
- IMC_DEV
- IMC_DOMAIN_CORE
- IMC_DOMAIN_NEST
- IMC_DOMAIN_THREAD
- IMC_DOMAIN_TRACE
- IMC_DTB_COMPAT
- IMC_DTB_UNIT_COMPAT
- IMC_EVENT_ATTR
- IMC_EVENT_OFFSET_MASK
- IMC_FORMAT_ATTR
- IMC_NULL_ATTR
- IMC_TRACE_RECORD_TB1_MASK
- IMC_TYPE_CHIP
- IMC_TYPE_CORE
- IMC_TYPE_THREAD
- IMC_TYPE_TRACE
- IMDELTIMER
- IMD_CMD0
- IMD_CMD0_DEV_ADDR
- IMD_CMD0_PL_LEN
- IMD_CMD0_RNW
- IMD_CMD1
- IMD_CMD1_CCC
- IMD_DATA
- IMELAR
- IMEM
- IMEM0_A_CLK
- IMEM0_RESET
- IMEMC_PHYS
- IMEMC_SIZE
- IMEMC_VIRT
- IMEM_BLOCK_SIZE
- IMEM_CHK_RPT
- IMEM_CODE_DONE
- IMEM_DMA_ADR
- IMEM_DMA_COUNT
- IMEM_DMA_CTRL
- IMEM_NR_CLK
- IMEM_OFFSET
- IMEM_RDY
- IMEUAR
- IMFILLRNG1_TAG_HI_SHIFT
- IMFILLRNG1_TAG_LO_SHIFT
- IMFILLRNG1_TAG_MASK
- IMGBLK
- IMGETCOUNT
- IMGETDEVINFO
- IMGETVERSION
- IMGP_UVP_MASK
- IMGP_UVP_SHFT
- IMGP_YP_MASK
- IMGP_YP_SHFT
- IMGSIZE
- IMGSZ_H_MASK
- IMGSZ_V_MASK
- IMGSZ_V_SHIFT
- IMGU_ABI_ACC_OPTYPE_PROCESS_LINES
- IMGU_ABI_ACC_OPTYPE_TRANSFER_DATA
- IMGU_ABI_ACC_OP_END_OF_ACK
- IMGU_ABI_ACC_OP_END_OF_OPS
- IMGU_ABI_ACC_OP_IDLE
- IMGU_ABI_ACC_OP_NO_OPS
- IMGU_ABI_AF_MAX_CELLS_PER_SET
- IMGU_ABI_AF_MAX_OPERATIONS
- IMGU_ABI_AF_MAX_PROCESS_LINES
- IMGU_ABI_AF_MAX_TRANSFERS
- IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET
- IMGU_ABI_AWB_FR_MAX_OPERATIONS
- IMGU_ABI_AWB_FR_MAX_PROCESS_LINES
- IMGU_ABI_AWB_FR_MAX_TRANSFERS
- IMGU_ABI_AWB_MAX_CELLS_PER_SET
- IMGU_ABI_AWB_MAX_OPERATIONS
- IMGU_ABI_AWB_MAX_PROCESS_LINES
- IMGU_ABI_AWB_MAX_TRANSFERS
- IMGU_ABI_BAYER_ORDER_BGGR
- IMGU_ABI_BAYER_ORDER_GBRG
- IMGU_ABI_BAYER_ORDER_GRBG
- IMGU_ABI_BAYER_ORDER_RGGB
- IMGU_ABI_BDS_PHASE_COEFFS_ARRAY_SIZE
- IMGU_ABI_BDS_SAMPLE_PATTERN_ARRAY_SIZE
- IMGU_ABI_BINARY_INPUT_SOURCE_MEMORY
- IMGU_ABI_BINARY_INPUT_SOURCE_SENSOR
- IMGU_ABI_BINARY_INPUT_SOURCE_VARIABLE
- IMGU_ABI_BINARY_MAX_OUTPUT_PORTS
- IMGU_ABI_BL_DMACMD_TYPE_SP_PMEM
- IMGU_ABI_BL_SWSTATE_BUSY
- IMGU_ABI_BL_SWSTATE_ERR
- IMGU_ABI_BL_SWSTATE_OK
- IMGU_ABI_BUFFER_TYPE_3A_STATISTICS
- IMGU_ABI_BUFFER_TYPE_CUSTOM_INPUT
- IMGU_ABI_BUFFER_TYPE_CUSTOM_OUTPUT
- IMGU_ABI_BUFFER_TYPE_DIS_STATISTICS
- IMGU_ABI_BUFFER_TYPE_INPUT_FRAME
- IMGU_ABI_BUFFER_TYPE_INVALID
- IMGU_ABI_BUFFER_TYPE_LACE_STATISTICS
- IMGU_ABI_BUFFER_TYPE_METADATA
- IMGU_ABI_BUFFER_TYPE_OUTPUT_FRAME
- IMGU_ABI_BUFFER_TYPE_PARAMETER_SET
- IMGU_ABI_BUFFER_TYPE_PER_FRAME_PARAMETER_SET
- IMGU_ABI_BUFFER_TYPE_RAW_OUTPUT_FRAME
- IMGU_ABI_BUFFER_TYPE_SEC_OUTPUT_FRAME
- IMGU_ABI_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME
- IMGU_ABI_BUFFER_TYPE_VF_OUTPUT_FRAME
- IMGU_ABI_BUF_SETS_TNR
- IMGU_ABI_DVS_STAT_LEVELS
- IMGU_ABI_DVS_STAT_MAX_OPERATIONS
- IMGU_ABI_DVS_STAT_MAX_PROCESS_LINES
- IMGU_ABI_DVS_STAT_MAX_TRANSFERS
- IMGU_ABI_EVENT_BUFFER_DEQUEUED
- IMGU_ABI_EVENT_BUFFER_ENQUEUED
- IMGU_ABI_EVENT_EVENT_DEQUEUED
- IMGU_ABI_EVENT_MIPI_BUFFERS_READY
- IMGU_ABI_EVENT_STAGE_ENABLE_DISABLE
- IMGU_ABI_EVENT_START_STREAM
- IMGU_ABI_EVENT_STOP_STREAM
- IMGU_ABI_EVENT_UNLOCK_RAW_BUFFER
- IMGU_ABI_EVTTYPE_2ND_OUT_FRAME_DONE
- IMGU_ABI_EVTTYPE_2ND_VF_OUT_FRAME_DONE
- IMGU_ABI_EVTTYPE_3A_STATS_DONE
- IMGU_ABI_EVTTYPE_ACC_STAGE_COMPLETE
- IMGU_ABI_EVTTYPE_DIS_STATS_DONE
- IMGU_ABI_EVTTYPE_EVENT_MASK
- IMGU_ABI_EVTTYPE_EVENT_SHIFT
- IMGU_ABI_EVTTYPE_FRAME_TAGGED
- IMGU_ABI_EVTTYPE_FW_ASSERT
- IMGU_ABI_EVTTYPE_FW_WARNING
- IMGU_ABI_EVTTYPE_INPUT_FRAME_DONE
- IMGU_ABI_EVTTYPE_LACE_STATS_DONE
- IMGU_ABI_EVTTYPE_LINENO_MASK
- IMGU_ABI_EVTTYPE_LINENO_SHIFT
- IMGU_ABI_EVTTYPE_METADATA_DONE
- IMGU_ABI_EVTTYPE_MODULEID_MASK
- IMGU_ABI_EVTTYPE_MODULEID_SHIFT
- IMGU_ABI_EVTTYPE_OUT_FRAME_DONE
- IMGU_ABI_EVTTYPE_PIPEID_MASK
- IMGU_ABI_EVTTYPE_PIPEID_SHIFT
- IMGU_ABI_EVTTYPE_PIPELINE_DONE
- IMGU_ABI_EVTTYPE_PIPE_MASK
- IMGU_ABI_EVTTYPE_PIPE_SHIFT
- IMGU_ABI_EVTTYPE_PORT_EOF
- IMGU_ABI_EVTTYPE_TIMER
- IMGU_ABI_EVTTYPE_VF_OUT_FRAME_DONE
- IMGU_ABI_FRAMES_REF
- IMGU_ABI_FRAMES_TNR
- IMGU_ABI_FRAME_FORMAT_BINARY_8
- IMGU_ABI_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8
- IMGU_ABI_FRAME_FORMAT_CSI_MIPI_YUV420_10
- IMGU_ABI_FRAME_FORMAT_CSI_MIPI_YUV420_8
- IMGU_ABI_FRAME_FORMAT_MIPI
- IMGU_ABI_FRAME_FORMAT_NUM
- IMGU_ABI_FRAME_FORMAT_NV11
- IMGU_ABI_FRAME_FORMAT_NV12
- IMGU_ABI_FRAME_FORMAT_NV12_16
- IMGU_ABI_FRAME_FORMAT_NV12_TILEY
- IMGU_ABI_FRAME_FORMAT_NV16
- IMGU_ABI_FRAME_FORMAT_NV21
- IMGU_ABI_FRAME_FORMAT_NV61
- IMGU_ABI_FRAME_FORMAT_PLANAR_RGB888
- IMGU_ABI_FRAME_FORMAT_QPLANE6
- IMGU_ABI_FRAME_FORMAT_RAW
- IMGU_ABI_FRAME_FORMAT_RAW_PACKED
- IMGU_ABI_FRAME_FORMAT_RGB565
- IMGU_ABI_FRAME_FORMAT_RGBA888
- IMGU_ABI_FRAME_FORMAT_UYVY
- IMGU_ABI_FRAME_FORMAT_YCGCO444_16
- IMGU_ABI_FRAME_FORMAT_YUV420
- IMGU_ABI_FRAME_FORMAT_YUV420_16
- IMGU_ABI_FRAME_FORMAT_YUV422
- IMGU_ABI_FRAME_FORMAT_YUV422_16
- IMGU_ABI_FRAME_FORMAT_YUV444
- IMGU_ABI_FRAME_FORMAT_YUV_LINE
- IMGU_ABI_FRAME_FORMAT_YUYV
- IMGU_ABI_FRAME_FORMAT_YV12
- IMGU_ABI_FRAME_FORMAT_YV16
- IMGU_ABI_GDC_FRAC_BITS
- IMGU_ABI_HOST2SP_BUFQ_SIZE
- IMGU_ABI_HOST2SP_EVTQ_SIZE
- IMGU_ABI_ISP_DDR_WORD_BITS
- IMGU_ABI_ISP_DDR_WORD_BYTES
- IMGU_ABI_MAX_BINARY_NAME
- IMGU_ABI_MAX_IF_CONFIGS
- IMGU_ABI_MAX_SP_THREADS
- IMGU_ABI_MAX_STAGES
- IMGU_ABI_MEM_DDR
- IMGU_ABI_MEM_ISP_DMEM0
- IMGU_ABI_MEM_ISP_HMEM0
- IMGU_ABI_MEM_ISP_PMEM0
- IMGU_ABI_MEM_ISP_VAMEM0
- IMGU_ABI_MEM_ISP_VAMEM1
- IMGU_ABI_MEM_ISP_VAMEM2
- IMGU_ABI_MEM_ISP_VMEM0
- IMGU_ABI_MEM_SP0_DMEM0
- IMGU_ABI_MEM_SP1_DMEM0
- IMGU_ABI_NUM_BUFFER_TYPE
- IMGU_ABI_NUM_CONTINUOUS_FRAMES
- IMGU_ABI_NUM_DYNAMIC_BUFFER_TYPE
- IMGU_ABI_NUM_MEMORIES
- IMGU_ABI_OSYS_FORMAT_BGRA
- IMGU_ABI_OSYS_FORMAT_NV12
- IMGU_ABI_OSYS_FORMAT_NV16
- IMGU_ABI_OSYS_FORMAT_NV21
- IMGU_ABI_OSYS_FORMAT_RGBA
- IMGU_ABI_OSYS_FORMAT_YUV420
- IMGU_ABI_OSYS_FORMAT_YUV_LINE
- IMGU_ABI_OSYS_FORMAT_YUY2
- IMGU_ABI_OSYS_FORMAT_YV12
- IMGU_ABI_OSYS_PINS
- IMGU_ABI_OSYS_PIN_OUT
- IMGU_ABI_OSYS_PIN_VF
- IMGU_ABI_OSYS_PROCMODE_BYPASS
- IMGU_ABI_OSYS_PROCMODE_DOWNSCALE
- IMGU_ABI_OSYS_PROCMODE_UPSCALE
- IMGU_ABI_OSYS_TILING_NONE
- IMGU_ABI_OSYS_TILING_Y
- IMGU_ABI_OSYS_TILING_YF
- IMGU_ABI_PARAM_CLASS_CONFIG
- IMGU_ABI_PARAM_CLASS_NUM
- IMGU_ABI_PARAM_CLASS_PARAM
- IMGU_ABI_PARAM_CLASS_STATE
- IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP
- IMGU_ABI_PORT_CONFIG_TYPE_INPUT_HOST
- IMGU_ABI_PORT_CONFIG_TYPE_OUTPUT_HOST
- IMGU_ABI_QUEUE_A_ID
- IMGU_ABI_QUEUE_B_ID
- IMGU_ABI_QUEUE_C_ID
- IMGU_ABI_QUEUE_D_ID
- IMGU_ABI_QUEUE_EVENT_ID
- IMGU_ABI_QUEUE_E_ID
- IMGU_ABI_QUEUE_F_ID
- IMGU_ABI_QUEUE_G_ID
- IMGU_ABI_QUEUE_H_ID
- IMGU_ABI_QUEUE_NUM
- IMGU_ABI_RAW_TYPE_BAYER
- IMGU_ABI_RAW_TYPE_IR_ON_GB
- IMGU_ABI_RAW_TYPE_IR_ON_GR
- IMGU_ABI_SHD_MAX_CELLS_PER_SET
- IMGU_ABI_SHD_MAX_CFG_SETS
- IMGU_ABI_SHD_MAX_OPERATIONS
- IMGU_ABI_SHD_MAX_PROCESS_LINES
- IMGU_ABI_SHD_MAX_TRANSFERS
- IMGU_ABI_SP2HOST_BUFQ_SIZE
- IMGU_ABI_SP2HOST_EVTQ_SIZE
- IMGU_ABI_SP_COMM_COMMAND
- IMGU_ABI_SP_COMM_COMMAND_DUMMY
- IMGU_ABI_SP_COMM_COMMAND_READY
- IMGU_ABI_SP_COMM_COMMAND_START_FLASH
- IMGU_ABI_SP_COMM_COMMAND_TERMINATE
- IMGU_ABI_SP_COMM_EVENT_IRQ_MASK
- IMGU_ABI_SP_COMM_EVENT_IRQ_MASK_AND_SHIFT
- IMGU_ABI_SP_COMM_EVENT_IRQ_MASK_OR_SHIFT
- IMGU_ABI_SP_SWSTATE_CONNECTED
- IMGU_ABI_SP_SWSTATE_INITIALIZED
- IMGU_ABI_SP_SWSTATE_RUNNING
- IMGU_ABI_SP_SWSTATE_TERMINATED
- IMGU_ABI_STAGE_TYPE_ISP
- IMGU_ABI_STAGE_TYPE_SP
- IMGU_ABI_YUVP2_YTM_LUT_ENTRIES
- IMGU_BDS_CONFIG_LEN
- IMGU_BDS_GRANULARITY
- IMGU_BDS_MAX_CLIP_VAL
- IMGU_BDS_MIN_CLIP_VAL
- IMGU_BDS_MIN_SF_INV
- IMGU_BYTES_PER_WORD
- IMGU_CIO_GATE_BURST_MASK
- IMGU_CNTX_BPP
- IMGU_CNTX_STRIDE_UV
- IMGU_CTRL_BREAK
- IMGU_CTRL_BROKEN
- IMGU_CTRL_ICACHE_INV
- IMGU_CTRL_IDLE
- IMGU_CTRL_IPREFETCH_EN
- IMGU_CTRL_IRQ_CLEAR
- IMGU_CTRL_IRQ_READY
- IMGU_CTRL_IRQ_SLEEPING
- IMGU_CTRL_RST
- IMGU_CTRL_RUN
- IMGU_CTRL_SLEEPING
- IMGU_CTRL_STALLING
- IMGU_CTRL_START
- IMGU_DMA_MASK
- IMGU_DVS_BLOCK_H
- IMGU_DVS_BLOCK_W
- IMGU_FIFO_ADDR_FMT_TO_SCALER
- IMGU_FIFO_ADDR_FMT_TO_SP
- IMGU_FIFO_ADDR_SCALER_TO_FMT
- IMGU_FIFO_ADDR_SCALER_TO_SP
- IMGU_FW_ACC_FIRMWARE
- IMGU_FW_ACC_NONE
- IMGU_FW_ACC_OUTPUT
- IMGU_FW_ACC_STANDALONE
- IMGU_FW_ACC_VIEWFINDER
- IMGU_FW_BOOTLOADER_FIRMWARE
- IMGU_FW_ISP_FIRMWARE
- IMGU_FW_NAME
- IMGU_FW_SP1_FIRMWARE
- IMGU_FW_SP_FIRMWARE
- IMGU_GDC_BUF_X
- IMGU_GDC_BUF_Y
- IMGU_GDC_LUT_LEN
- IMGU_GDC_LUT_MASK
- IMGU_GDC_LUT_UNIT
- IMGU_GP_STRMON_STAT_ACCS2SP1_MON_PORT_ACC
- IMGU_GP_STRMON_STAT_ACCS2SP2_MON_PORT_ACC
- IMGU_GP_STRMON_STAT_ACCS_PORT_ACC
- IMGU_GP_STRMON_STAT_ISP_PORT_DMA2ISP
- IMGU_GP_STRMON_STAT_ISP_PORT_ISP2DMA
- IMGU_GP_STRMON_STAT_ISP_PORT_ISP2SP1
- IMGU_GP_STRMON_STAT_ISP_PORT_SP12ISP
- IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2DECOMP
- IMGU_GP_STRMON_STAT_MOD_PORT_CELLS2GDC
- IMGU_GP_STRMON_STAT_MOD_PORT_DECOMP2CELLS
- IMGU_GP_STRMON_STAT_MOD_PORT_DMA2ISP
- IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP1
- IMGU_GP_STRMON_STAT_MOD_PORT_DMA2SP2
- IMGU_GP_STRMON_STAT_MOD_PORT_GDC2CELLS
- IMGU_GP_STRMON_STAT_MOD_PORT_ISP2DMA
- IMGU_GP_STRMON_STAT_MOD_PORT_S2V
- IMGU_GP_STRMON_STAT_MOD_PORT_SP12DMA
- IMGU_GP_STRMON_STAT_MOD_PORT_SP22DMA
- IMGU_GP_STRMON_STAT_SP1_PORT_DMA2SP1
- IMGU_GP_STRMON_STAT_SP1_PORT_ISP2SP1
- IMGU_GP_STRMON_STAT_SP1_PORT_SP12DMA
- IMGU_GP_STRMON_STAT_SP1_PORT_SP12ISP
- IMGU_GP_STRMON_STAT_SP1_PORT_SP12SP2
- IMGU_GP_STRMON_STAT_SP1_PORT_SP22SP1
- IMGU_GP_STRMON_STAT_SP2_PORT_DMA2SP2
- IMGU_GP_STRMON_STAT_SP2_PORT_SP12SP2
- IMGU_GP_STRMON_STAT_SP2_PORT_SP22DMA
- IMGU_GP_STRMON_STAT_SP2_PORT_SP22SP1
- IMGU_HIVE_OF_SYS_OF_SYSTEM_NWAYS
- IMGU_HIVE_OF_SYS_OF_TO_FA_OFFSET
- IMGU_HIVE_OF_SYS_SCALER_TO_FA_OFFSET
- IMGU_HOR_CNTX_WORDS
- IMGU_INPUT_BLOCK_WIDTH
- IMGU_IRQCTRL_IRQ_ACCS_SCRATCH_MEM_ERROR
- IMGU_IRQCTRL_IRQ_ACCS_SP1_STREAM_MON
- IMGU_IRQCTRL_IRQ_ACCS_SP2_STREAM_MON
- IMGU_IRQCTRL_IRQ_ACCS_STREAM_MON
- IMGU_IRQCTRL_IRQ_ACC_SYS
- IMGU_IRQCTRL_IRQ_DMA
- IMGU_IRQCTRL_IRQ_GP_TIMER
- IMGU_IRQCTRL_IRQ_ISP
- IMGU_IRQCTRL_IRQ_ISP_BAMEM_ERROR
- IMGU_IRQCTRL_IRQ_ISP_DMEM_ERROR
- IMGU_IRQCTRL_IRQ_ISP_PMEM_ERROR
- IMGU_IRQCTRL_IRQ_ISP_STREAM_MON
- IMGU_IRQCTRL_IRQ_ISP_VMEM_ERROR
- IMGU_IRQCTRL_IRQ_MASK
- IMGU_IRQCTRL_IRQ_MOD_ISP_STREAM_MON
- IMGU_IRQCTRL_IRQ_MOD_STREAM_MON
- IMGU_IRQCTRL_IRQ_OUT_FORM_IRQ_CTRL
- IMGU_IRQCTRL_IRQ_SP1
- IMGU_IRQCTRL_IRQ_SP1_DMEM_ERROR
- IMGU_IRQCTRL_IRQ_SP1_ICACHE_MEM_ERROR
- IMGU_IRQCTRL_IRQ_SP1_IRQ_CTRL
- IMGU_IRQCTRL_IRQ_SP1_STREAM_MON
- IMGU_IRQCTRL_IRQ_SP2
- IMGU_IRQCTRL_IRQ_SP2_DMEM_ERROR
- IMGU_IRQCTRL_IRQ_SP2_ICACHE_MEM_ERROR
- IMGU_IRQCTRL_IRQ_SP2_IRQ_CTRL
- IMGU_IRQCTRL_IRQ_SP2_STREAM_MON
- IMGU_IRQCTRL_IRQ_SW_PIN
- IMGU_IRQCTRL_MAIN
- IMGU_IRQCTRL_NUM
- IMGU_IRQCTRL_SP0
- IMGU_IRQCTRL_SP1
- IMGU_ISP_VEC_NELEMS
- IMGU_ISP_VMEM_ALIGN
- IMGU_LUMA_TO_CHROMA_RATIO
- IMGU_MAX_BQ_GRID_HEIGHT
- IMGU_MAX_BQ_GRID_WIDTH
- IMGU_MAX_FRAME_WIDTH
- IMGU_MAX_INPUT_BLOCK_HEIGHT
- IMGU_MAX_OUTPUT_BLOCK_WIDTH
- IMGU_MAX_PIPELINE_NUM
- IMGU_MAX_PIPE_NUM
- IMGU_MAX_QUEUE_DEPTH
- IMGU_NAME
- IMGU_NODE_IN
- IMGU_NODE_NUM
- IMGU_NODE_OUT
- IMGU_NODE_PARAMS
- IMGU_NODE_STAT_3A
- IMGU_NODE_VF
- IMGU_NUM_SP
- IMGU_OBGRID_TILE_SIZE
- IMGU_OF_TO_ACK_FA_ADDR
- IMGU_OSYS_BLOCK_HEIGHT
- IMGU_OSYS_BLOCK_WIDTH
- IMGU_OSYS_DMA_CROP_H_LIMIT
- IMGU_OSYS_DMA_CROP_W_LIMIT
- IMGU_OSYS_FILTER_TAPS
- IMGU_OSYS_FIR_PHASES
- IMGU_OSYS_NUM_INPUT_BUFFERS
- IMGU_OSYS_NUM_INTERM_BUFFERS
- IMGU_OSYS_NUM_OUTPUT_BUFFERS
- IMGU_OSYS_PHASES
- IMGU_OSYS_PHASE_COUNTER_PREC_REF
- IMGU_OSYS_TAPS_UV
- IMGU_OSYS_TAPS_Y
- IMGU_OUTFORMACC_MS_TO_SCALER_SL_ADDR
- IMGU_PCI_BAR
- IMGU_PCI_ID
- IMGU_PIXELS_PER_WORD
- IMGU_PM_CTRL_CFG_DONE
- IMGU_PM_CTRL_CSS_PWRDN
- IMGU_PM_CTRL_FORCE_HALT
- IMGU_PM_CTRL_FORCE_PWRDN
- IMGU_PM_CTRL_FORCE_RESET
- IMGU_PM_CTRL_FORCE_UNHALT
- IMGU_PM_CTRL_NACK_ALL
- IMGU_PM_CTRL_RACE_TO_HALT
- IMGU_PM_CTRL_RST_AT_EOF
- IMGU_PM_CTRL_START
- IMGU_PS_SNR_PRESERVE_BITS
- IMGU_QUEUE_FIRST_INPUT
- IMGU_QUEUE_MASTER
- IMGU_REG_BASE
- IMGU_REG_CIO_GATE_BURST_STATE
- IMGU_REG_GDC_BASE
- IMGU_REG_GDC_LUT_BASE
- IMGU_REG_GP_BUSY
- IMGU_REG_GP_HALT
- IMGU_REG_GP_IRQ
- IMGU_REG_GP_ISP_STRMON_STAT
- IMGU_REG_GP_MOD_STRMON_STAT
- IMGU_REG_GP_SP1_STRMON_STAT
- IMGU_REG_GP_SP2_STRMON_STAT
- IMGU_REG_GP_STARVING
- IMGU_REG_GP_TIMER
- IMGU_REG_GP_WORKLOAD
- IMGU_REG_INT_CSS_IRQ
- IMGU_REG_INT_ENABLE
- IMGU_REG_INT_STATUS
- IMGU_REG_IRQCTRL_BASE
- IMGU_REG_IRQCTRL_CLEAR
- IMGU_REG_IRQCTRL_EDGE
- IMGU_REG_IRQCTRL_EDGE_NOT_PULSE
- IMGU_REG_IRQCTRL_ENABLE
- IMGU_REG_IRQCTRL_MASK
- IMGU_REG_IRQCTRL_STATUS
- IMGU_REG_IRQCTRL_STR_OUT_ENABLE
- IMGU_REG_ISP_CTRL
- IMGU_REG_ISP_DMEM_BASE
- IMGU_REG_ISP_ICACHE_ADDR
- IMGU_REG_ISP_PC
- IMGU_REG_ISP_START_ADDR
- IMGU_REG_L1_PHYS
- IMGU_REG_PM_CTRL
- IMGU_REG_PM_STS
- IMGU_REG_SP_CTRL
- IMGU_REG_SP_CTRL_SINK
- IMGU_REG_SP_DMEM_BASE
- IMGU_REG_SP_ICACHE_ADDR
- IMGU_REG_SP_PC
- IMGU_REG_SP_START_ADDR
- IMGU_REG_STATE
- IMGU_REG_SYSTEM_REQ
- IMGU_REG_TLB_INVALIDATE
- IMGU_SCALER_COEFF_BITS
- IMGU_SCALER_DOWNSCALE_2TAPS_LEN
- IMGU_SCALER_DOWNSCALE_4TAPS_LEN
- IMGU_SCALER_ELEMS_PER_VEC
- IMGU_SCALER_FILTER_TAPS
- IMGU_SCALER_FILTER_TAPS_UV
- IMGU_SCALER_FILTER_TAPS_Y
- IMGU_SCALER_FIR_PHASES
- IMGU_SCALER_FP
- IMGU_SCALER_INTR_BPP
- IMGU_SCALER_MAX_EXPONENT_SHIFT
- IMGU_SCALER_MS_TO_OUTFORMACC_SL_ADDR
- IMGU_SCALER_OUT_BPP
- IMGU_SCALER_PHASES
- IMGU_SCALER_PHASE_COUNTER_PREC_REF
- IMGU_SCALER_TAPS_UV
- IMGU_SCALER_TAPS_Y
- IMGU_SCALER_TO_OF_ACK_FA_ADDR
- IMGU_SHD_SETS
- IMGU_SP_PMEM_BASE
- IMGU_STATE_CSS_BUSY_MASK
- IMGU_STATE_HALT_STS
- IMGU_STATE_IDLE_STS
- IMGU_STATE_PM_FSM_MASK
- IMGU_STATE_POWER_DOWN
- IMGU_STATE_POWER_UP
- IMGU_STATE_PWRDNM_FSM_MASK
- IMGU_STRIDE_Y
- IMGU_STRIPE_FIXED_HALF_OVERLAP
- IMGU_SYSTEM_REQ_FREQ_DIVIDER
- IMGU_SYSTEM_REQ_FREQ_MASK
- IMGU_TLB_INVALIDATE
- IMGU_VER_CNTX_WORDS
- IMGU_VMEM1_BUF_SIZE
- IMGU_VMEM1_ELEMS_PER_VEC
- IMGU_VMEM1_HST_BUF_ADDR
- IMGU_VMEM1_HST_BUF_NLINES
- IMGU_VMEM1_HST_BUF_STRIDE
- IMGU_VMEM1_INP_BUF_ADDR
- IMGU_VMEM1_INT_BUF_ADDR
- IMGU_VMEM1_OUT_BUF_ADDR
- IMGU_VMEM1_UV_SIZE
- IMGU_VMEM1_UV_STRIDE
- IMGU_VMEM1_U_OFFSET
- IMGU_VMEM1_V_OFFSET
- IMGU_VMEM1_Y_SIZE
- IMGU_VMEM1_Y_STRIDE
- IMGU_VMEM2_BUF_SIZE
- IMGU_VMEM2_BUF_UV_STRIDE
- IMGU_VMEM2_BUF_U_ADDR
- IMGU_VMEM2_BUF_V_ADDR
- IMGU_VMEM2_BUF_Y_ADDR
- IMGU_VMEM2_BUF_Y_STRIDE
- IMGU_VMEM2_ELEMS_PER_VEC
- IMGU_VMEM2_LINES_PER_BLOCK
- IMGU_VMEM2_VECS_PER_LINE
- IMGU_VMEM3_ELEMS_PER_VEC
- IMGU_VMEM3_HOR_U_ADDR
- IMGU_VMEM3_HOR_U_SIZE
- IMGU_VMEM3_HOR_V_ADDR
- IMGU_VMEM3_HOR_Y_ADDR
- IMGU_VMEM3_HOR_Y_SIZE
- IMGU_VMEM3_VER_U_ADDR
- IMGU_VMEM3_VER_U_EXTRA
- IMGU_VMEM3_VER_U_SIZE
- IMGU_VMEM3_VER_V_ADDR
- IMGU_VMEM3_VER_V_SIZE
- IMGU_VMEM3_VER_Y_ADDR
- IMGU_VMEM3_VER_Y_EXTRA
- IMGU_VMEM3_VER_Y_SIZE
- IMGU_XNR3_VMEM_LUT_LEN
- IMG_CRC_LEN
- IMG_DATA_FORMAT
- IMG_DATA_FORMAT_1
- IMG_DATA_FORMAT_10_10_10_2
- IMG_DATA_FORMAT_10_11_11
- IMG_DATA_FORMAT_11_11_10
- IMG_DATA_FORMAT_16
- IMG_DATA_FORMAT_16_16
- IMG_DATA_FORMAT_16_16_16_16
- IMG_DATA_FORMAT_16_AS_16_16_16_16
- IMG_DATA_FORMAT_16_AS_32_32
- IMG_DATA_FORMAT_16_AS_32_32_32_32
- IMG_DATA_FORMAT_1_5_5_5
- IMG_DATA_FORMAT_1_REVERSED
- IMG_DATA_FORMAT_24_8
- IMG_DATA_FORMAT_2_10_10_10
- IMG_DATA_FORMAT_32
- IMG_DATA_FORMAT_32_32
- IMG_DATA_FORMAT_32_32_32
- IMG_DATA_FORMAT_32_32_32_32
- IMG_DATA_FORMAT_32_AS_32_32_32_32
- IMG_DATA_FORMAT_32_AS_8
- IMG_DATA_FORMAT_32_AS_8_8
- IMG_DATA_FORMAT_4_4
- IMG_DATA_FORMAT_4_4_4_4
- IMG_DATA_FORMAT_5_5_5_1
- IMG_DATA_FORMAT_5_6_5
- IMG_DATA_FORMAT_5_9_9_9
- IMG_DATA_FORMAT_6E4
- IMG_DATA_FORMAT_6_5_5
- IMG_DATA_FORMAT_8
- IMG_DATA_FORMAT_8_24
- IMG_DATA_FORMAT_8_8
- IMG_DATA_FORMAT_8_8_8_8
- IMG_DATA_FORMAT_8_AS_32
- IMG_DATA_FORMAT_8_AS_32_32
- IMG_DATA_FORMAT_8_AS_8_8_8_8
- IMG_DATA_FORMAT_ASTC_2D_HDR
- IMG_DATA_FORMAT_ASTC_2D_LDR
- IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB
- IMG_DATA_FORMAT_ASTC_3D_HDR
- IMG_DATA_FORMAT_ASTC_3D_LDR
- IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB
- IMG_DATA_FORMAT_BC1
- IMG_DATA_FORMAT_BC2
- IMG_DATA_FORMAT_BC3
- IMG_DATA_FORMAT_BC4
- IMG_DATA_FORMAT_BC5
- IMG_DATA_FORMAT_BC6
- IMG_DATA_FORMAT_BC7
- IMG_DATA_FORMAT_BG_RG
- IMG_DATA_FORMAT_ETC2_R
- IMG_DATA_FORMAT_ETC2_RG
- IMG_DATA_FORMAT_ETC2_RGB
- IMG_DATA_FORMAT_ETC2_RGBA
- IMG_DATA_FORMAT_ETC2_RGBA1
- IMG_DATA_FORMAT_FMASK
- IMG_DATA_FORMAT_FMASK16_S16_F1
- IMG_DATA_FORMAT_FMASK16_S8_F2
- IMG_DATA_FORMAT_FMASK32_S16_F2
- IMG_DATA_FORMAT_FMASK32_S8_F4
- IMG_DATA_FORMAT_FMASK32_S8_F8
- IMG_DATA_FORMAT_FMASK64_S16_F4
- IMG_DATA_FORMAT_FMASK64_S16_F8
- IMG_DATA_FORMAT_FMASK8_S2_F1
- IMG_DATA_FORMAT_FMASK8_S2_F2
- IMG_DATA_FORMAT_FMASK8_S4_F1
- IMG_DATA_FORMAT_FMASK8_S4_F2
- IMG_DATA_FORMAT_FMASK8_S4_F4
- IMG_DATA_FORMAT_FMASK8_S8_F1
- IMG_DATA_FORMAT_GB_GR
- IMG_DATA_FORMAT_INVALID
- IMG_DATA_FORMAT_MM_10_11_11
- IMG_DATA_FORMAT_MM_10_IN_16
- IMG_DATA_FORMAT_MM_10_IN_16_16
- IMG_DATA_FORMAT_MM_10_IN_16_16_16_16
- IMG_DATA_FORMAT_MM_16_16_16_16
- IMG_DATA_FORMAT_MM_2_10_10_10
- IMG_DATA_FORMAT_MM_8
- IMG_DATA_FORMAT_MM_8_8
- IMG_DATA_FORMAT_MM_8_8_8_8
- IMG_DATA_FORMAT_MM_VYUY8
- IMG_DATA_FORMAT_N_IN_16
- IMG_DATA_FORMAT_N_IN_16_16
- IMG_DATA_FORMAT_N_IN_16_16_16_16
- IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16
- IMG_DATA_FORMAT_RESERVED_100
- IMG_DATA_FORMAT_RESERVED_101
- IMG_DATA_FORMAT_RESERVED_102
- IMG_DATA_FORMAT_RESERVED_103
- IMG_DATA_FORMAT_RESERVED_104
- IMG_DATA_FORMAT_RESERVED_105
- IMG_DATA_FORMAT_RESERVED_106
- IMG_DATA_FORMAT_RESERVED_107
- IMG_DATA_FORMAT_RESERVED_108
- IMG_DATA_FORMAT_RESERVED_109
- IMG_DATA_FORMAT_RESERVED_110
- IMG_DATA_FORMAT_RESERVED_111
- IMG_DATA_FORMAT_RESERVED_112
- IMG_DATA_FORMAT_RESERVED_113
- IMG_DATA_FORMAT_RESERVED_114
- IMG_DATA_FORMAT_RESERVED_115
- IMG_DATA_FORMAT_RESERVED_116
- IMG_DATA_FORMAT_RESERVED_117
- IMG_DATA_FORMAT_RESERVED_118
- IMG_DATA_FORMAT_RESERVED_119
- IMG_DATA_FORMAT_RESERVED_120
- IMG_DATA_FORMAT_RESERVED_121
- IMG_DATA_FORMAT_RESERVED_122
- IMG_DATA_FORMAT_RESERVED_123
- IMG_DATA_FORMAT_RESERVED_124
- IMG_DATA_FORMAT_RESERVED_125
- IMG_DATA_FORMAT_RESERVED_126
- IMG_DATA_FORMAT_RESERVED_127
- IMG_DATA_FORMAT_RESERVED_15
- IMG_DATA_FORMAT_RESERVED_23
- IMG_DATA_FORMAT_RESERVED_24
- IMG_DATA_FORMAT_RESERVED_25
- IMG_DATA_FORMAT_RESERVED_26
- IMG_DATA_FORMAT_RESERVED_27
- IMG_DATA_FORMAT_RESERVED_28
- IMG_DATA_FORMAT_RESERVED_29
- IMG_DATA_FORMAT_RESERVED_30
- IMG_DATA_FORMAT_RESERVED_31
- IMG_DATA_FORMAT_RESERVED_42
- IMG_DATA_FORMAT_RESERVED_43
- IMG_DATA_FORMAT_RESERVED_56
- IMG_DATA_FORMAT_RESERVED_59
- IMG_DATA_FORMAT_RESERVED_60
- IMG_DATA_FORMAT_RESERVED_61
- IMG_DATA_FORMAT_RESERVED_62
- IMG_DATA_FORMAT_RESERVED_75
- IMG_DATA_FORMAT_RESERVED_86
- IMG_DATA_FORMAT_RESERVED_87
- IMG_DATA_FORMAT_RESERVED_88
- IMG_DATA_FORMAT_RESERVED_89
- IMG_DATA_FORMAT_RESERVED_90
- IMG_DATA_FORMAT_RESERVED_91
- IMG_DATA_FORMAT_RESERVED_92
- IMG_DATA_FORMAT_RESERVED_93
- IMG_DATA_FORMAT_RESERVED_94
- IMG_DATA_FORMAT_RESERVED_95
- IMG_DATA_FORMAT_RESERVED_96
- IMG_DATA_FORMAT_RESERVED_97
- IMG_DATA_FORMAT_RESERVED_98
- IMG_DATA_FORMAT_RESERVED_99
- IMG_DATA_FORMAT_X24_8_32
- IMG_FMT
- IMG_FMT_10_10_10_2_SINT
- IMG_FMT_10_10_10_2_SNORM
- IMG_FMT_10_10_10_2_SSCALED
- IMG_FMT_10_10_10_2_UINT
- IMG_FMT_10_10_10_2_UNORM
- IMG_FMT_10_10_10_2_USCALED
- IMG_FMT_10_11_11_FLOAT
- IMG_FMT_10_11_11_SINT
- IMG_FMT_10_11_11_SNORM
- IMG_FMT_10_11_11_SSCALED
- IMG_FMT_10_11_11_UINT
- IMG_FMT_10_11_11_UNORM
- IMG_FMT_10_11_11_USCALED
- IMG_FMT_11_11_10_FLOAT
- IMG_FMT_11_11_10_SINT
- IMG_FMT_11_11_10_SNORM
- IMG_FMT_11_11_10_SSCALED
- IMG_FMT_11_11_10_UINT
- IMG_FMT_11_11_10_UNORM
- IMG_FMT_11_11_10_USCALED
- IMG_FMT_16_16_16_16_FLOAT
- IMG_FMT_16_16_16_16_SINT
- IMG_FMT_16_16_16_16_SNORM
- IMG_FMT_16_16_16_16_SSCALED
- IMG_FMT_16_16_16_16_UINT
- IMG_FMT_16_16_16_16_UNORM
- IMG_FMT_16_16_16_16_USCALED
- IMG_FMT_16_16_FLOAT
- IMG_FMT_16_16_SINT
- IMG_FMT_16_16_SNORM
- IMG_FMT_16_16_SSCALED
- IMG_FMT_16_16_UINT
- IMG_FMT_16_16_UNORM
- IMG_FMT_16_16_USCALED
- IMG_FMT_16_FLOAT
- IMG_FMT_16_SINT
- IMG_FMT_16_SNORM
- IMG_FMT_16_SSCALED
- IMG_FMT_16_UINT
- IMG_FMT_16_UNORM
- IMG_FMT_16_USCALED
- IMG_FMT_1_5_5_5_UNORM
- IMG_FMT_1_REVERSED_UNORM
- IMG_FMT_1_UNORM
- IMG_FMT_24_8_UINT
- IMG_FMT_24_8_UNORM
- IMG_FMT_2_10_10_10_SINT
- IMG_FMT_2_10_10_10_SNORM
- IMG_FMT_2_10_10_10_SSCALED
- IMG_FMT_2_10_10_10_UINT
- IMG_FMT_2_10_10_10_UNORM
- IMG_FMT_2_10_10_10_USCALED
- IMG_FMT_32_32_32_32_FLOAT
- IMG_FMT_32_32_32_32_SINT
- IMG_FMT_32_32_32_32_UINT
- IMG_FMT_32_32_32_FLOAT
- IMG_FMT_32_32_32_SINT
- IMG_FMT_32_32_32_UINT
- IMG_FMT_32_32_FLOAT
- IMG_FMT_32_32_SINT
- IMG_FMT_32_32_UINT
- IMG_FMT_32_FLOAT
- IMG_FMT_32_FLOAT_CLAMP
- IMG_FMT_32_SINT
- IMG_FMT_32_UINT
- IMG_FMT_4_4_4_4_UNORM
- IMG_FMT_4_4_UNORM
- IMG_FMT_5_5_5_1_UNORM
- IMG_FMT_5_6_5_UNORM
- IMG_FMT_5_9_9_9_FLOAT
- IMG_FMT_6E4_FLOAT
- IMG_FMT_8_24_UINT
- IMG_FMT_8_24_UNORM
- IMG_FMT_8_8_8_8_SINT
- IMG_FMT_8_8_8_8_SNORM
- IMG_FMT_8_8_8_8_SRGB
- IMG_FMT_8_8_8_8_SSCALED
- IMG_FMT_8_8_8_8_UINT
- IMG_FMT_8_8_8_8_UNORM
- IMG_FMT_8_8_8_8_USCALED
- IMG_FMT_8_8_SINT
- IMG_FMT_8_8_SNORM
- IMG_FMT_8_8_SRGB
- IMG_FMT_8_8_SSCALED
- IMG_FMT_8_8_UINT
- IMG_FMT_8_8_UNORM
- IMG_FMT_8_8_USCALED
- IMG_FMT_8_SINT
- IMG_FMT_8_SNORM
- IMG_FMT_8_SRGB
- IMG_FMT_8_SSCALED
- IMG_FMT_8_UINT
- IMG_FMT_8_UNORM
- IMG_FMT_8_USCALED
- IMG_FMT_BC1_SRGB
- IMG_FMT_BC1_UNORM
- IMG_FMT_BC2_SRGB
- IMG_FMT_BC2_UNORM
- IMG_FMT_BC3_SRGB
- IMG_FMT_BC3_UNORM
- IMG_FMT_BC4_SNORM
- IMG_FMT_BC4_UNORM
- IMG_FMT_BC5_SNORM
- IMG_FMT_BC5_UNORM
- IMG_FMT_BC6_SFLOAT
- IMG_FMT_BC6_UFLOAT
- IMG_FMT_BC7_SRGB
- IMG_FMT_BC7_UNORM
- IMG_FMT_BG_RG_SNORM
- IMG_FMT_BG_RG_SRGB
- IMG_FMT_BG_RG_UINT
- IMG_FMT_BG_RG_UNORM
- IMG_FMT_CBYCRY422
- IMG_FMT_CRYCBY422
- IMG_FMT_FMASK16_S16_F1
- IMG_FMT_FMASK16_S8_F2
- IMG_FMT_FMASK32_S16_F2
- IMG_FMT_FMASK32_S8_F4
- IMG_FMT_FMASK32_S8_F8
- IMG_FMT_FMASK64_S16_F4
- IMG_FMT_FMASK64_S16_F8
- IMG_FMT_FMASK8_S2_F1
- IMG_FMT_FMASK8_S2_F2
- IMG_FMT_FMASK8_S4_F1
- IMG_FMT_FMASK8_S4_F2
- IMG_FMT_FMASK8_S4_F4
- IMG_FMT_FMASK8_S8_F1
- IMG_FMT_GB_GR_SNORM
- IMG_FMT_GB_GR_SRGB
- IMG_FMT_GB_GR_UINT
- IMG_FMT_GB_GR_UNORM
- IMG_FMT_INVALID
- IMG_FMT_MM_10_11_11_UINT
- IMG_FMT_MM_10_11_11_UNORM
- IMG_FMT_MM_10_IN_16_16_16_16_UINT
- IMG_FMT_MM_10_IN_16_16_16_16_UNORM
- IMG_FMT_MM_10_IN_16_16_UINT
- IMG_FMT_MM_10_IN_16_16_UNORM
- IMG_FMT_MM_10_IN_16_UINT
- IMG_FMT_MM_10_IN_16_UNORM
- IMG_FMT_MM_16_16_16_16_UINT
- IMG_FMT_MM_16_16_16_16_UNORM
- IMG_FMT_MM_2_10_10_10_UINT
- IMG_FMT_MM_2_10_10_10_UNORM
- IMG_FMT_MM_8_8_8_8_UINT
- IMG_FMT_MM_8_8_8_8_UNORM
- IMG_FMT_MM_8_8_UINT
- IMG_FMT_MM_8_8_UNORM
- IMG_FMT_MM_8_UINT
- IMG_FMT_MM_8_UNORM
- IMG_FMT_MM_VYUY8_UINT
- IMG_FMT_MM_VYUY8_UNORM
- IMG_FMT_RESERVED_100
- IMG_FMT_RESERVED_101
- IMG_FMT_RESERVED_102
- IMG_FMT_RESERVED_103
- IMG_FMT_RESERVED_104
- IMG_FMT_RESERVED_105
- IMG_FMT_RESERVED_106
- IMG_FMT_RESERVED_107
- IMG_FMT_RESERVED_108
- IMG_FMT_RESERVED_109
- IMG_FMT_RESERVED_110
- IMG_FMT_RESERVED_111
- IMG_FMT_RESERVED_112
- IMG_FMT_RESERVED_113
- IMG_FMT_RESERVED_114
- IMG_FMT_RESERVED_115
- IMG_FMT_RESERVED_116
- IMG_FMT_RESERVED_117
- IMG_FMT_RESERVED_118
- IMG_FMT_RESERVED_119
- IMG_FMT_RESERVED_120
- IMG_FMT_RESERVED_121
- IMG_FMT_RESERVED_122
- IMG_FMT_RESERVED_123
- IMG_FMT_RESERVED_124
- IMG_FMT_RESERVED_125
- IMG_FMT_RESERVED_126
- IMG_FMT_RESERVED_127
- IMG_FMT_RESERVED_155
- IMG_FMT_RESERVED_285
- IMG_FMT_RESERVED_286
- IMG_FMT_RESERVED_287
- IMG_FMT_RESERVED_288
- IMG_FMT_RESERVED_289
- IMG_FMT_RESERVED_290
- IMG_FMT_RESERVED_291
- IMG_FMT_RESERVED_292
- IMG_FMT_RESERVED_293
- IMG_FMT_RESERVED_294
- IMG_FMT_RESERVED_295
- IMG_FMT_RESERVED_296
- IMG_FMT_RESERVED_297
- IMG_FMT_RESERVED_298
- IMG_FMT_RESERVED_299
- IMG_FMT_RESERVED_300
- IMG_FMT_RESERVED_301
- IMG_FMT_RESERVED_302
- IMG_FMT_RESERVED_303
- IMG_FMT_RESERVED_304
- IMG_FMT_RESERVED_305
- IMG_FMT_RESERVED_306
- IMG_FMT_RESERVED_307
- IMG_FMT_RESERVED_308
- IMG_FMT_RESERVED_309
- IMG_FMT_RESERVED_310
- IMG_FMT_RESERVED_311
- IMG_FMT_RESERVED_312
- IMG_FMT_RESERVED_313
- IMG_FMT_RESERVED_314
- IMG_FMT_RESERVED_315
- IMG_FMT_RESERVED_316
- IMG_FMT_RESERVED_317
- IMG_FMT_RESERVED_318
- IMG_FMT_RESERVED_319
- IMG_FMT_RESERVED_320
- IMG_FMT_RESERVED_321
- IMG_FMT_RESERVED_322
- IMG_FMT_RESERVED_323
- IMG_FMT_RESERVED_324
- IMG_FMT_RESERVED_325
- IMG_FMT_RESERVED_326
- IMG_FMT_RESERVED_327
- IMG_FMT_RESERVED_328
- IMG_FMT_RESERVED_329
- IMG_FMT_RESERVED_330
- IMG_FMT_RESERVED_331
- IMG_FMT_RESERVED_332
- IMG_FMT_RESERVED_333
- IMG_FMT_RESERVED_334
- IMG_FMT_RESERVED_335
- IMG_FMT_RESERVED_336
- IMG_FMT_RESERVED_337
- IMG_FMT_RESERVED_338
- IMG_FMT_RESERVED_339
- IMG_FMT_RESERVED_340
- IMG_FMT_RESERVED_341
- IMG_FMT_RESERVED_342
- IMG_FMT_RESERVED_343
- IMG_FMT_RESERVED_344
- IMG_FMT_RESERVED_345
- IMG_FMT_RESERVED_346
- IMG_FMT_RESERVED_347
- IMG_FMT_RESERVED_348
- IMG_FMT_RESERVED_349
- IMG_FMT_RESERVED_350
- IMG_FMT_RESERVED_351
- IMG_FMT_RESERVED_352
- IMG_FMT_RESERVED_353
- IMG_FMT_RESERVED_354
- IMG_FMT_RESERVED_355
- IMG_FMT_RESERVED_356
- IMG_FMT_RESERVED_357
- IMG_FMT_RESERVED_358
- IMG_FMT_RESERVED_359
- IMG_FMT_RESERVED_360
- IMG_FMT_RESERVED_361
- IMG_FMT_RESERVED_362
- IMG_FMT_RESERVED_363
- IMG_FMT_RESERVED_364
- IMG_FMT_RESERVED_365
- IMG_FMT_RESERVED_366
- IMG_FMT_RESERVED_367
- IMG_FMT_RESERVED_368
- IMG_FMT_RESERVED_369
- IMG_FMT_RESERVED_370
- IMG_FMT_RESERVED_371
- IMG_FMT_RESERVED_372
- IMG_FMT_RESERVED_373
- IMG_FMT_RESERVED_374
- IMG_FMT_RESERVED_375
- IMG_FMT_RESERVED_376
- IMG_FMT_RESERVED_377
- IMG_FMT_RESERVED_378
- IMG_FMT_RESERVED_379
- IMG_FMT_RESERVED_380
- IMG_FMT_RESERVED_381
- IMG_FMT_RESERVED_382
- IMG_FMT_RESERVED_383
- IMG_FMT_RESERVED_384
- IMG_FMT_RESERVED_385
- IMG_FMT_RESERVED_386
- IMG_FMT_RESERVED_387
- IMG_FMT_RESERVED_388
- IMG_FMT_RESERVED_389
- IMG_FMT_RESERVED_390
- IMG_FMT_RESERVED_391
- IMG_FMT_RESERVED_392
- IMG_FMT_RESERVED_393
- IMG_FMT_RESERVED_394
- IMG_FMT_RESERVED_395
- IMG_FMT_RESERVED_396
- IMG_FMT_RESERVED_397
- IMG_FMT_RESERVED_398
- IMG_FMT_RESERVED_399
- IMG_FMT_RESERVED_400
- IMG_FMT_RESERVED_401
- IMG_FMT_RESERVED_402
- IMG_FMT_RESERVED_403
- IMG_FMT_RESERVED_404
- IMG_FMT_RESERVED_405
- IMG_FMT_RESERVED_406
- IMG_FMT_RESERVED_407
- IMG_FMT_RESERVED_408
- IMG_FMT_RESERVED_409
- IMG_FMT_RESERVED_410
- IMG_FMT_RESERVED_411
- IMG_FMT_RESERVED_412
- IMG_FMT_RESERVED_413
- IMG_FMT_RESERVED_414
- IMG_FMT_RESERVED_415
- IMG_FMT_RESERVED_416
- IMG_FMT_RESERVED_417
- IMG_FMT_RESERVED_418
- IMG_FMT_RESERVED_419
- IMG_FMT_RESERVED_420
- IMG_FMT_RESERVED_421
- IMG_FMT_RESERVED_422
- IMG_FMT_RESERVED_423
- IMG_FMT_RESERVED_424
- IMG_FMT_RESERVED_425
- IMG_FMT_RESERVED_426
- IMG_FMT_RESERVED_427
- IMG_FMT_RESERVED_428
- IMG_FMT_RESERVED_429
- IMG_FMT_RESERVED_430
- IMG_FMT_RESERVED_431
- IMG_FMT_RESERVED_432
- IMG_FMT_RESERVED_433
- IMG_FMT_RESERVED_434
- IMG_FMT_RESERVED_435
- IMG_FMT_RESERVED_436
- IMG_FMT_RESERVED_437
- IMG_FMT_RESERVED_438
- IMG_FMT_RESERVED_439
- IMG_FMT_RESERVED_440
- IMG_FMT_RESERVED_441
- IMG_FMT_RESERVED_442
- IMG_FMT_RESERVED_443
- IMG_FMT_RESERVED_444
- IMG_FMT_RESERVED_445
- IMG_FMT_RESERVED_446
- IMG_FMT_RESERVED_447
- IMG_FMT_RESERVED_448
- IMG_FMT_RESERVED_449
- IMG_FMT_RESERVED_450
- IMG_FMT_RESERVED_451
- IMG_FMT_RESERVED_452
- IMG_FMT_RESERVED_453
- IMG_FMT_RESERVED_454
- IMG_FMT_RESERVED_455
- IMG_FMT_RESERVED_456
- IMG_FMT_RESERVED_457
- IMG_FMT_RESERVED_458
- IMG_FMT_RESERVED_459
- IMG_FMT_RESERVED_460
- IMG_FMT_RESERVED_461
- IMG_FMT_RESERVED_462
- IMG_FMT_RESERVED_463
- IMG_FMT_RESERVED_464
- IMG_FMT_RESERVED_465
- IMG_FMT_RESERVED_466
- IMG_FMT_RESERVED_467
- IMG_FMT_RESERVED_468
- IMG_FMT_RESERVED_469
- IMG_FMT_RESERVED_470
- IMG_FMT_RESERVED_471
- IMG_FMT_RESERVED_472
- IMG_FMT_RESERVED_473
- IMG_FMT_RESERVED_474
- IMG_FMT_RESERVED_475
- IMG_FMT_RESERVED_476
- IMG_FMT_RESERVED_477
- IMG_FMT_RESERVED_478
- IMG_FMT_RESERVED_479
- IMG_FMT_RESERVED_480
- IMG_FMT_RESERVED_481
- IMG_FMT_RESERVED_482
- IMG_FMT_RESERVED_483
- IMG_FMT_RESERVED_484
- IMG_FMT_RESERVED_485
- IMG_FMT_RESERVED_486
- IMG_FMT_RESERVED_487
- IMG_FMT_RESERVED_488
- IMG_FMT_RESERVED_489
- IMG_FMT_RESERVED_490
- IMG_FMT_RESERVED_491
- IMG_FMT_RESERVED_492
- IMG_FMT_RESERVED_493
- IMG_FMT_RESERVED_494
- IMG_FMT_RESERVED_495
- IMG_FMT_RESERVED_496
- IMG_FMT_RESERVED_497
- IMG_FMT_RESERVED_498
- IMG_FMT_RESERVED_499
- IMG_FMT_RESERVED_500
- IMG_FMT_RESERVED_501
- IMG_FMT_RESERVED_502
- IMG_FMT_RESERVED_503
- IMG_FMT_RESERVED_504
- IMG_FMT_RESERVED_505
- IMG_FMT_RESERVED_506
- IMG_FMT_RESERVED_507
- IMG_FMT_RESERVED_508
- IMG_FMT_RESERVED_509
- IMG_FMT_RESERVED_510
- IMG_FMT_RESERVED_511
- IMG_FMT_RESERVED_78
- IMG_FMT_RESERVED_79
- IMG_FMT_RESERVED_80
- IMG_FMT_RESERVED_81
- IMG_FMT_RESERVED_82
- IMG_FMT_RESERVED_83
- IMG_FMT_RESERVED_84
- IMG_FMT_RESERVED_85
- IMG_FMT_RESERVED_86
- IMG_FMT_RESERVED_87
- IMG_FMT_RESERVED_88
- IMG_FMT_RESERVED_89
- IMG_FMT_RESERVED_90
- IMG_FMT_RESERVED_91
- IMG_FMT_RESERVED_92
- IMG_FMT_RESERVED_93
- IMG_FMT_RESERVED_94
- IMG_FMT_RESERVED_95
- IMG_FMT_RESERVED_96
- IMG_FMT_RESERVED_97
- IMG_FMT_RESERVED_98
- IMG_FMT_RESERVED_99
- IMG_FMT_RGB565
- IMG_FMT_RGB666
- IMG_FMT_X24_8_32_FLOAT
- IMG_FMT_X24_8_32_UINT
- IMG_FMT_XRGB8888
- IMG_FMT_YCBCR420
- IMG_FMT_YCBCR422P
- IMG_FMT_YCBYCR422
- IMG_FMT_YCRCB420
- IMG_FMT_YCRYCB422
- IMG_H
- IMG_HASH_BYTE_ORDER
- IMG_HASH_DMA_BURST
- IMG_HASH_DMA_THRESHOLD
- IMG_HASH_QUEUE_LENGTH
- IMG_I2C_PM_TIMEOUT
- IMG_I2C_TIMEOUT
- IMG_I2S_IN_CH_CTL
- IMG_I2S_IN_CH_CTL_16PACK_MASK
- IMG_I2S_IN_CH_CTL_BLKP_MASK
- IMG_I2S_IN_CH_CTL_CCDEL_MASK
- IMG_I2S_IN_CH_CTL_CCDEL_SHIFT
- IMG_I2S_IN_CH_CTL_CLK_TRANS_MASK
- IMG_I2S_IN_CH_CTL_FEN_MASK
- IMG_I2S_IN_CH_CTL_FIFO_FLUSH_MASK
- IMG_I2S_IN_CH_CTL_FMODE_MASK
- IMG_I2S_IN_CH_CTL_FW_MASK
- IMG_I2S_IN_CH_CTL_JUST_MASK
- IMG_I2S_IN_CH_CTL_LRD_MASK
- IMG_I2S_IN_CH_CTL_ME_MASK
- IMG_I2S_IN_CH_CTL_PACKH_MASK
- IMG_I2S_IN_CH_CTL_SW_MASK
- IMG_I2S_IN_CH_STRIDE
- IMG_I2S_IN_CTL
- IMG_I2S_IN_CTL_16PACK_MASK
- IMG_I2S_IN_CTL_ACTIVE_CHAN_MASK
- IMG_I2S_IN_CTL_ACTIVE_CH_SHIFT
- IMG_I2S_IN_CTL_ME_MASK
- IMG_I2S_IN_RX_FIFO
- IMG_I2S_OUT_CHAN_CTL_CH_MASK
- IMG_I2S_OUT_CHAN_CTL_CLKT_MASK
- IMG_I2S_OUT_CHAN_CTL_FMT_MASK
- IMG_I2S_OUT_CHAN_CTL_FMT_SHIFT
- IMG_I2S_OUT_CHAN_CTL_JUST_MASK
- IMG_I2S_OUT_CHAN_CTL_LT_MASK
- IMG_I2S_OUT_CHAN_CTL_ME_MASK
- IMG_I2S_OUT_CH_CTL
- IMG_I2S_OUT_CH_STRIDE
- IMG_I2S_OUT_CTL
- IMG_I2S_OUT_CTL_ACTIVE_CHAN_MASK
- IMG_I2S_OUT_CTL_ACTIVE_CHAN_SHIFT
- IMG_I2S_OUT_CTL_BCLK_POL_MASK
- IMG_I2S_OUT_CTL_CLK_EN_MASK
- IMG_I2S_OUT_CTL_CLK_MASK
- IMG_I2S_OUT_CTL_DATA_EN_MASK
- IMG_I2S_OUT_CTL_FRM_CLK_POL_MASK
- IMG_I2S_OUT_CTL_FRM_SIZE_MASK
- IMG_I2S_OUT_CTL_MASTER_MASK
- IMG_I2S_OUT_CTL_ME_MASK
- IMG_I2S_OUT_TX_FIFO
- IMG_IR_BITINV
- IMG_IR_BITINVD2
- IMG_IR_BITORIEN
- IMG_IR_BITORIEND2
- IMG_IR_CODETYPE
- IMG_IR_CODETYPE_2BITPULSEPOS
- IMG_IR_CODETYPE_BIPHASE
- IMG_IR_CODETYPE_PULSEDIST
- IMG_IR_CODETYPE_PULSELEN
- IMG_IR_CODETYPE_SHIFT
- IMG_IR_CONTROL
- IMG_IR_CORE_CONFIG
- IMG_IR_CORE_CONFIG_SHIFT
- IMG_IR_CORE_DES1
- IMG_IR_CORE_DES2
- IMG_IR_CORE_ID
- IMG_IR_CORE_ID_SHIFT
- IMG_IR_CORE_REV
- IMG_IR_D1VALIDSEL
- IMG_IR_DATA_LW
- IMG_IR_DATA_UP
- IMG_IR_DECODEN
- IMG_IR_DECODEND2
- IMG_IR_DECODINPOL
- IMG_IR_DESIGNER
- IMG_IR_DESIGNER_SHIFT
- IMG_IR_FREE_SYMB_TIMING
- IMG_IR_FT_MIN
- IMG_IR_FT_MIN_SHIFT
- IMG_IR_F_FILTER
- IMG_IR_F_WAKE
- IMG_IR_HDRTOG
- IMG_IR_IRCORE_ID
- IMG_IR_IRQ_ACT_LEVEL
- IMG_IR_IRQ_ALL
- IMG_IR_IRQ_CLEAR
- IMG_IR_IRQ_DATA2_VALID
- IMG_IR_IRQ_DATA_MATCH
- IMG_IR_IRQ_DATA_VALID
- IMG_IR_IRQ_DEC2_ERR
- IMG_IR_IRQ_DEC_ERR
- IMG_IR_IRQ_EDGE
- IMG_IR_IRQ_ENABLE
- IMG_IR_IRQ_FALL_EDGE
- IMG_IR_IRQ_MSG_DATA_LW
- IMG_IR_IRQ_MSG_DATA_UP
- IMG_IR_IRQ_MSG_MASK_LW
- IMG_IR_IRQ_MSG_MASK_UP
- IMG_IR_IRQ_RISE_EDGE
- IMG_IR_IRQ_STATUS
- IMG_IR_IRRXD
- IMG_IR_LDRDEC
- IMG_IR_LEAD_SYMB_TIMING
- IMG_IR_MAINT_REV
- IMG_IR_MAINT_REV_SHIFT
- IMG_IR_MAJOR_REV
- IMG_IR_MAJOR_REV_SHIFT
- IMG_IR_MAXLEN
- IMG_IR_MAXLEN_SHIFT
- IMG_IR_MINLEN
- IMG_IR_MINLEN_SHIFT
- IMG_IR_MINOR_REV
- IMG_IR_MINOR_REV_SHIFT
- IMG_IR_M_NORMAL
- IMG_IR_M_REPEATING
- IMG_IR_M_WAKE
- IMG_IR_PD_MAX
- IMG_IR_PD_MAX_SHIFT
- IMG_IR_PD_MIN
- IMG_IR_PD_MIN_SHIFT
- IMG_IR_PERIOD_DUTY
- IMG_IR_PERIOD_DUTY_SHIFT
- IMG_IR_PERIOD_LEN
- IMG_IR_PERIOD_LEN_SHIFT
- IMG_IR_POWER_MOD_EN
- IMG_IR_POWER_OUT_EN
- IMG_IR_POW_MOD_ENABLE
- IMG_IR_POW_MOD_PARAMS
- IMG_IR_QUIRK_CODE_BROKEN
- IMG_IR_QUIRK_CODE_IRQ
- IMG_IR_QUIRK_CODE_LEN_INCR
- IMG_IR_REPEATCODE
- IMG_IR_RXDLEN
- IMG_IR_RXDLEN_SHIFT
- IMG_IR_RXDVAL
- IMG_IR_RXDVALD2
- IMG_IR_S00_SYMB_TIMING
- IMG_IR_S01_SYMB_TIMING
- IMG_IR_S10_SYMB_TIMING
- IMG_IR_S11_SYMB_TIMING
- IMG_IR_SCANCODE
- IMG_IR_STABLE_START
- IMG_IR_STABLE_START_SHIFT
- IMG_IR_STABLE_STOP
- IMG_IR_STABLE_STOP_SHIFT
- IMG_IR_STATUS
- IMG_IR_TOGSTATE
- IMG_IR_W_MAX
- IMG_IR_W_MAX_SHIFT
- IMG_IR_W_MIN
- IMG_IR_W_MIN_SHIFT
- IMG_MASK
- IMG_NUM_FORMAT
- IMG_NUM_FORMAT_ASTC_2D
- IMG_NUM_FORMAT_ASTC_2D_10x10
- IMG_NUM_FORMAT_ASTC_2D_10x5
- IMG_NUM_FORMAT_ASTC_2D_10x6
- IMG_NUM_FORMAT_ASTC_2D_10x8
- IMG_NUM_FORMAT_ASTC_2D_12x10
- IMG_NUM_FORMAT_ASTC_2D_12x12
- IMG_NUM_FORMAT_ASTC_2D_4x4
- IMG_NUM_FORMAT_ASTC_2D_5x4
- IMG_NUM_FORMAT_ASTC_2D_5x5
- IMG_NUM_FORMAT_ASTC_2D_6x5
- IMG_NUM_FORMAT_ASTC_2D_6x6
- IMG_NUM_FORMAT_ASTC_2D_8x5
- IMG_NUM_FORMAT_ASTC_2D_8x6
- IMG_NUM_FORMAT_ASTC_2D_8x8
- IMG_NUM_FORMAT_ASTC_2D_RESERVED_14
- IMG_NUM_FORMAT_ASTC_2D_RESERVED_15
- IMG_NUM_FORMAT_ASTC_3D
- IMG_NUM_FORMAT_ASTC_3D_3x3x3
- IMG_NUM_FORMAT_ASTC_3D_4x3x3
- IMG_NUM_FORMAT_ASTC_3D_4x4x3
- IMG_NUM_FORMAT_ASTC_3D_4x4x4
- IMG_NUM_FORMAT_ASTC_3D_5x4x4
- IMG_NUM_FORMAT_ASTC_3D_5x5x4
- IMG_NUM_FORMAT_ASTC_3D_5x5x5
- IMG_NUM_FORMAT_ASTC_3D_6x5x5
- IMG_NUM_FORMAT_ASTC_3D_6x6x5
- IMG_NUM_FORMAT_ASTC_3D_6x6x6
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_10
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_11
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_12
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_13
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_14
- IMG_NUM_FORMAT_ASTC_3D_RESERVED_15
- IMG_NUM_FORMAT_FLOAT
- IMG_NUM_FORMAT_FMASK
- IMG_NUM_FORMAT_FMASK_16_16_1
- IMG_NUM_FORMAT_FMASK_16_8_2
- IMG_NUM_FORMAT_FMASK_32_16_2
- IMG_NUM_FORMAT_FMASK_32_8_4
- IMG_NUM_FORMAT_FMASK_32_8_8
- IMG_NUM_FORMAT_FMASK_64_16_4
- IMG_NUM_FORMAT_FMASK_64_16_8
- IMG_NUM_FORMAT_FMASK_8_2_1
- IMG_NUM_FORMAT_FMASK_8_2_2
- IMG_NUM_FORMAT_FMASK_8_4_1
- IMG_NUM_FORMAT_FMASK_8_4_2
- IMG_NUM_FORMAT_FMASK_8_4_4
- IMG_NUM_FORMAT_FMASK_8_8_1
- IMG_NUM_FORMAT_FMASK_RESERVED_13
- IMG_NUM_FORMAT_FMASK_RESERVED_14
- IMG_NUM_FORMAT_FMASK_RESERVED_15
- IMG_NUM_FORMAT_N_IN_16
- IMG_NUM_FORMAT_N_IN_16_RESERVED_0
- IMG_NUM_FORMAT_N_IN_16_RESERVED_10
- IMG_NUM_FORMAT_N_IN_16_RESERVED_11
- IMG_NUM_FORMAT_N_IN_16_RESERVED_12
- IMG_NUM_FORMAT_N_IN_16_RESERVED_13
- IMG_NUM_FORMAT_N_IN_16_RESERVED_14
- IMG_NUM_FORMAT_N_IN_16_RESERVED_15
- IMG_NUM_FORMAT_N_IN_16_RESERVED_3
- IMG_NUM_FORMAT_N_IN_16_RESERVED_6
- IMG_NUM_FORMAT_N_IN_16_RESERVED_9
- IMG_NUM_FORMAT_N_IN_16_UINT_10
- IMG_NUM_FORMAT_N_IN_16_UINT_9
- IMG_NUM_FORMAT_N_IN_16_UNORM_10
- IMG_NUM_FORMAT_N_IN_16_UNORM_9
- IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10
- IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9
- IMG_NUM_FORMAT_RESERVED_10
- IMG_NUM_FORMAT_RESERVED_11
- IMG_NUM_FORMAT_RESERVED_12
- IMG_NUM_FORMAT_RESERVED_13
- IMG_NUM_FORMAT_RESERVED_14
- IMG_NUM_FORMAT_RESERVED_15
- IMG_NUM_FORMAT_RESERVED_6
- IMG_NUM_FORMAT_RESERVED_8
- IMG_NUM_FORMAT_SINT
- IMG_NUM_FORMAT_SNORM
- IMG_NUM_FORMAT_SNORM_NZ
- IMG_NUM_FORMAT_SNORM_OGL
- IMG_NUM_FORMAT_SRGB
- IMG_NUM_FORMAT_SSCALED
- IMG_NUM_FORMAT_UBINT
- IMG_NUM_FORMAT_UBNORM
- IMG_NUM_FORMAT_UBNORM_NZ
- IMG_NUM_FORMAT_UBNORM_OGL
- IMG_NUM_FORMAT_UBSCALED
- IMG_NUM_FORMAT_UINT
- IMG_NUM_FORMAT_UNORM
- IMG_NUM_FORMAT_UNORM_UINT
- IMG_NUM_FORMAT_USCALED
- IMG_PRL_OUT_CTL
- IMG_PRL_OUT_CTL_CH_MASK
- IMG_PRL_OUT_CTL_EDGE_MASK
- IMG_PRL_OUT_CTL_ME_MASK
- IMG_PRL_OUT_CTL_PACKH_MASK
- IMG_PRL_OUT_CTL_SRST_MASK
- IMG_PRL_OUT_TX_FIFO
- IMG_PWM_NPWM
- IMG_PWM_PM_TIMEOUT
- IMG_REQ_CHILD
- IMG_REQ_LAYERED
- IMG_SPDIF_IN_ACLKGEN_HLD_MASK
- IMG_SPDIF_IN_ACLKGEN_HLD_SHIFT
- IMG_SPDIF_IN_ACLKGEN_NOM_MASK
- IMG_SPDIF_IN_ACLKGEN_NOM_SHIFT
- IMG_SPDIF_IN_ACLKGEN_START
- IMG_SPDIF_IN_ACLKGEN_TRK_MASK
- IMG_SPDIF_IN_ACLKGEN_TRK_SHIFT
- IMG_SPDIF_IN_CLKGEN
- IMG_SPDIF_IN_CLKGEN_HLD_MASK
- IMG_SPDIF_IN_CLKGEN_HLD_SHIFT
- IMG_SPDIF_IN_CLKGEN_NOM_MASK
- IMG_SPDIF_IN_CLKGEN_NOM_SHIFT
- IMG_SPDIF_IN_CSH
- IMG_SPDIF_IN_CSH_MASK
- IMG_SPDIF_IN_CSH_SHIFT
- IMG_SPDIF_IN_CSL
- IMG_SPDIF_IN_CTL
- IMG_SPDIF_IN_CTL_LOCKHI_MASK
- IMG_SPDIF_IN_CTL_LOCKHI_SHIFT
- IMG_SPDIF_IN_CTL_LOCKLO_MASK
- IMG_SPDIF_IN_CTL_LOCKLO_SHIFT
- IMG_SPDIF_IN_CTL_SRD_MASK
- IMG_SPDIF_IN_CTL_SRD_SHIFT
- IMG_SPDIF_IN_CTL_SRT_MASK
- IMG_SPDIF_IN_CTL_TRK_MASK
- IMG_SPDIF_IN_CTL_TRK_SHIFT
- IMG_SPDIF_IN_NUM_ACLKGEN
- IMG_SPDIF_IN_RX_FIFO_OFFSET
- IMG_SPDIF_IN_SOFT_RESET
- IMG_SPDIF_IN_SOFT_RESET_MASK
- IMG_SPDIF_IN_STATUS
- IMG_SPDIF_IN_STATUS_LOCK_MASK
- IMG_SPDIF_IN_STATUS_LOCK_SHIFT
- IMG_SPDIF_IN_STATUS_SAM_MASK
- IMG_SPDIF_IN_STATUS_SAM_SHIFT
- IMG_SPDIF_OUT_CSH_UV
- IMG_SPDIF_OUT_CSH_UV_CSH_MASK
- IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT
- IMG_SPDIF_OUT_CSL
- IMG_SPDIF_OUT_CTL
- IMG_SPDIF_OUT_CTL_CLK_MASK
- IMG_SPDIF_OUT_CTL_FS_MASK
- IMG_SPDIF_OUT_CTL_SRT_MASK
- IMG_SPDIF_OUT_TX_FIFO
- IMHOLD_L1
- IMISS
- IMM
- IMM12_MASK
- IMM20
- IMM3U
- IMM5_0
- IMM5_9
- IMM8
- IMMAIR0
- IMMAIR1
- IMMAIR_ATTR_DEVICE
- IMMAIR_ATTR_IDX_DEV
- IMMAIR_ATTR_IDX_NC
- IMMAIR_ATTR_IDX_WBRWA
- IMMAIR_ATTR_MASK
- IMMAIR_ATTR_NC
- IMMAIR_ATTR_SHIFT
- IMMAIR_ATTR_WBRWA
- IMMDT_CHNG
- IMMED
- IMMEDIATE
- IMMEDIATEDATA
- IMMEDIATE_ATTR
- IMMEDIATE_BLOCK_ACK
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK
- IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID
- IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID
- IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK
- IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT
- IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK
- IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT
- IMMEDIATE_DATA_CANNOT_RECOVER
- IMMEDIATE_DATA_ERL1_CRC_FAILURE
- IMMEDIATE_DATA_NORMAL_OPERATION
- IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK
- IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT
- IMMED_NOTIFY_TYPE
- IMMED_PKT_SIZE
- IMMED_SHIFT_0B
- IMMED_SHIFT_1B
- IMMED_SHIFT_2B
- IMMED_WIDTH_ALL
- IMMED_WIDTH_BYTE
- IMMED_WIDTH_WORD
- IMMRBAR_BASE
- IMMR_RCW_OFFSET
- IMMR_SIZE
- IMMR_SPI_CS_OFFSET
- IMMR_SYSCR_OFFSET
- IMMT_DATA_MASK
- IMMT_DATA_SHIFT
- IMMT_TYPE
- IMM_4
- IMM_4BY2
- IMM_4BY4
- IMM_8
- IMM_8BY2
- IMM_8BY4
- IMM_AUTODETECT
- IMM_BIT
- IMM_BURST_SIZE
- IMM_DATA_MASK
- IMM_DATA_SHIFT
- IMM_DEBUG
- IMM_EPP_16
- IMM_EPP_32
- IMM_EPP_8
- IMM_H
- IMM_HA
- IMM_L
- IMM_MASK
- IMM_NIBBLE
- IMM_NTFY_ABORT_TASK
- IMM_NTFY_ELS
- IMM_NTFY_GLBL_LOGO
- IMM_NTFY_GLBL_TPRLO
- IMM_NTFY_IOCB_OVERFLOW
- IMM_NTFY_LIP_LINK_REINIT
- IMM_NTFY_LIP_RESET
- IMM_NTFY_MSG_RX
- IMM_NTFY_PORT_CONFIG
- IMM_NTFY_PORT_LOGOUT
- IMM_NTFY_RESOURCE
- IMM_NTFY_SRR
- IMM_NTFY_TASK_MGMT_SHIFT
- IMM_PRN
- IMM_PROBE_ECR
- IMM_PROBE_EPP17
- IMM_PROBE_EPP19
- IMM_PROBE_PS2
- IMM_PROBE_SPP
- IMM_PS2
- IMM_SELECT_TMO
- IMM_SH
- IMM_SHIFT
- IMM_SPIN_TMO
- IMM_TYPE
- IMM_UNKNOWN
- IMM_VERSION
- IMM_WRITE
- IMONDO_DATA0
- IMONDO_DATA0_DATA
- IMONDO_DATA1
- IMONDO_DATA1_DATA
- IMON_BITS
- IMON_CHKBITS
- IMON_CLOCK_ENABLE_PACKETS
- IMON_DISPLAY_TYPE_AUTO
- IMON_DISPLAY_TYPE_LCD
- IMON_DISPLAY_TYPE_NONE
- IMON_DISPLAY_TYPE_VFD
- IMON_DISPLAY_TYPE_VGA
- IMON_KEY_IMON
- IMON_KEY_MCE
- IMON_KEY_PANEL
- IMON_NEED_20MS_PKT_DELAY
- IMON_NO_FLAGS
- IMON_UNIT
- IMPCAL_VTH_DIV
- IMPCTL_RESET_IND__IMP_SW_RESET_MASK
- IMPCTL_RESET_IND__IMP_SW_RESET__SHIFT
- IMPCTL_RESET__IMP_SW_RESET_MASK
- IMPCTL_RESET__IMP_SW_RESET__SHIFT
- IMPCTR
- IMPD1_CTRL
- IMPD1_CTRL_DISP_ENABLE
- IMPD1_CTRL_DISP_LCD
- IMPD1_CTRL_DISP_LCD1
- IMPD1_CTRL_DISP_MASK
- IMPD1_CTRL_DISP_VGA
- IMPD1_INT
- IMPD1_LEDS
- IMPD1_LOCK
- IMPD1_OSC1
- IMPD1_OSC2
- IMPD1_SW
- IMPD1_VALID_IRQS
- IMPEAR
- IMPERF_PA_OFFSET
- IMPL3ERR_ADDR_OFF
- IMPLEMENTER_ARM
- IMPLEMENT_GETSET
- IMPLICITLY_UPGRADED_DISK
- IMPLICITLY_UPGRADED_PDSK
- IMPLVER_EV4
- IMPLVER_EV5
- IMPLVER_EV6
- IMPL_LOGO_ADISC_ACC
- IMPL_LOGO_ADISC_CNFLT
- IMPL_LOGO_ADISC_RJT
- IMPL_NAME_LIMIT
- IMPMBA
- IMPMBD
- IMPORT_MODE_MANUAL
- IMPROMOEN
- IMPSTR
- IMPULSE_COSINE_ALPHA_0_3
- IMPULSE_COSINE_ALPHA_0_5
- IMPULSE_COSINE_ALPHA_RO_0_5
- IMP_CAL_FS_HS_DLY_0
- IMP_CAL_FS_HS_DLY_1
- IMP_CAL_FS_HS_DLY_2
- IMP_CAL_FS_HS_DLY_3
- IMP_RES_OFFSET_MASK
- IMP_RES_OFFSET_SHIFT
- IMR
- IMR0
- IMR0_ATIMEND
- IMR0_BCNDERR0
- IMR0_BCNDMAINT0
- IMR0_BCNDMAINT_E
- IMR0_BEDOK
- IMR0_BKDOK
- IMR0_C2HCMD
- IMR0_CPWM
- IMR0_CPWM2
- IMR0_GTINT3
- IMR0_GTINT4
- IMR0_HIGHDOK
- IMR0_HISR1_IND_INT
- IMR0_HSISR_IND_ON_INT
- IMR0_MGNTDOK
- IMR0_PSTIMEOUT
- IMR0_RDU
- IMR0_ROK
- IMR0_TBDER
- IMR0_TBDOK
- IMR0_TSF_BIT32_TOGGLE
- IMR0_TXCCK
- IMR0_VIDOK
- IMR0_VODOK
- IMR1
- IMR1_ATIMEND_E
- IMR1_BCNDERR1
- IMR1_BCNDERR2
- IMR1_BCNDERR3
- IMR1_BCNDERR4
- IMR1_BCNDERR5
- IMR1_BCNDERR6
- IMR1_BCNDERR7
- IMR1_BCNDMAINT1
- IMR1_BCNDMAINT2
- IMR1_BCNDMAINT3
- IMR1_BCNDMAINT4
- IMR1_BCNDMAINT5
- IMR1_BCNDMAINT6
- IMR1_BCNDMAINT7
- IMR1_RXERR
- IMR1_RXFOVW
- IMR1_TXERR
- IMR1_TXFOVW
- IMR8190_DISABLED
- IMR_AC0DMA
- IMR_ACCESS_NONE
- IMR_ADDR
- IMR_AIM
- IMR_ALIGN
- IMR_ANM
- IMR_ATIMEND
- IMR_ATIMEND_8723B
- IMR_ATIMEND_88E
- IMR_ATIMEND_E
- IMR_ATIMEND_E_8723B
- IMR_ATIMEND_E_88E
- IMR_ATIMINT
- IMR_ATM
- IMR_BCNDERR0_8723B
- IMR_BCNDERR0_88E
- IMR_BCNDERR1_88E
- IMR_BCNDERR2_88E
- IMR_BCNDERR3_88E
- IMR_BCNDERR4_88E
- IMR_BCNDERR5_88E
- IMR_BCNDERR6_88E
- IMR_BCNDERR7_88E
- IMR_BCNDMAINT
- IMR_BCNDMAINT0
- IMR_BCNDMAINT0_8723B
- IMR_BCNDMAINT0_88E
- IMR_BCNDMAINT1
- IMR_BCNDMAINT1_8723B
- IMR_BCNDMAINT1_88E
- IMR_BCNDMAINT2
- IMR_BCNDMAINT2_8723B
- IMR_BCNDMAINT2_88E
- IMR_BCNDMAINT3
- IMR_BCNDMAINT3_8723B
- IMR_BCNDMAINT3_88E
- IMR_BCNDMAINT4
- IMR_BCNDMAINT4_8723B
- IMR_BCNDMAINT4_88E
- IMR_BCNDMAINT5
- IMR_BCNDMAINT5_8723B
- IMR_BCNDMAINT5_88E
- IMR_BCNDMAINT6
- IMR_BCNDMAINT6_8723B
- IMR_BCNDMAINT6_88E
- IMR_BCNDMAINT7
- IMR_BCNDMAINT7_8723B
- IMR_BCNDMAINT7_88E
- IMR_BCNDMAINT8
- IMR_BCNDMAINT_E
- IMR_BCNDMAINT_E_8723B
- IMR_BCNDMAINT_E_88E
- IMR_BCNDOK0
- IMR_BCNDOK1
- IMR_BCNDOK1_8723B
- IMR_BCNDOK1_88E
- IMR_BCNDOK2
- IMR_BCNDOK2_8723B
- IMR_BCNDOK2_88E
- IMR_BCNDOK3
- IMR_BCNDOK3_8723B
- IMR_BCNDOK3_88E
- IMR_BCNDOK4
- IMR_BCNDOK4_8723B
- IMR_BCNDOK4_88E
- IMR_BCNDOK5
- IMR_BCNDOK5_8723B
- IMR_BCNDOK5_88E
- IMR_BCNDOK6
- IMR_BCNDOK6_8723B
- IMR_BCNDOK6_88E
- IMR_BCNDOK7
- IMR_BCNDOK7_8723B
- IMR_BCNDOK7_88E
- IMR_BCNDOK8
- IMR_BCNINT
- IMR_BDOK
- IMR_BEDOK
- IMR_BEDOK_8723B
- IMR_BEDOK_88E
- IMR_BKDOK
- IMR_BKDOK_8723B
- IMR_BKDOK_88E
- IMR_BNTX
- IMR_BTON_STS_UPDATE
- IMR_BcnInt
- IMR_BcnInt_E
- IMR_C2HCMD
- IMR_C2HCMD_8723B
- IMR_C2HCMD_88E
- IMR_COMDOK
- IMR_COUNTER_READY
- IMR_CPU
- IMR_CPUERR
- IMR_CPUMGQ_TX_TIMER
- IMR_CPU_0
- IMR_CPU_MGQ_TXDONE
- IMR_CPU_SNOOP
- IMR_CPWM
- IMR_CPWM2
- IMR_CPWM2_8723B
- IMR_CPWM2_88E
- IMR_CPWM_8723B
- IMR_CPWM_88E
- IMR_DEBUG_MASK
- IMR_DELTA_BREAK_A
- IMR_DELTA_BREAK_B
- IMR_DISABLED
- IMR_DISABLED_8723B
- IMR_DISABLED_88E
- IMR_DOT11HINT
- IMR_ENABLE_ALL
- IMR_ERM
- IMR_ESRAM_FLUSH
- IMR_ETM
- IMR_FBM
- IMR_FDM
- IMR_FETALERR
- IMR_FLONIM
- IMR_FOVW
- IMR_GPIO
- IMR_GPM
- IMR_GTINT3
- IMR_GTINT3_8723B
- IMR_GTINT3_88E
- IMR_GTINT4
- IMR_GTINT4_8723B
- IMR_GTINT4_88E
- IMR_H2CDOK
- IMR_HCCADOK
- IMR_HIGHDOK
- IMR_HIGHDOK_8723B
- IMR_HIGHDOK_88E
- IMR_HISR1_IND_INT
- IMR_HISR1_IND_INT_88E
- IMR_HSISR_IND_ON_INT
- IMR_HSISR_IND_ON_INT_8723B
- IMR_HSISR_IND_ON_INT_88E
- IMR_INPROG
- IMR_INPUT_PORT_CHANGE
- IMR_IP2_VAL
- IMR_IP3_VAL
- IMR_IP4_VAL
- IMR_IP5_VAL
- IMR_IP6_VAL
- IMR_LFM
- IMR_LNKCHNG
- IMR_LOCK
- IMR_LPM
- IMR_LSTEIM
- IMR_LSTPEIM
- IMR_MASK
- IMR_MASK_VALUE
- IMR_MCUERR
- IMR_MEASUREEND
- IMR_MEASURESTART
- IMR_MEMIQ
- IMR_MGNTDOK
- IMR_MGNTDOK_8723B
- IMR_MGNTDOK_88E
- IMR_MIBFIM
- IMR_MIBNEARFULL
- IMR_MINT0
- IMR_MINT1
- IMR_MINT2
- IMR_MINT3
- IMR_MINT4
- IMR_MINT5
- IMR_MINT6
- IMR_MINT7
- IMR_MIRQ1
- IMR_MIRQ2
- IMR_MIRQ3
- IMR_MIRQ5
- IMR_MIRQ6
- IMR_MIRQ7
- IMR_MKB
- IMR_MPEN
- IMR_MPWM
- IMR_MRTC
- IMR_MSAM
- IMR_MSPI
- IMR_MSPIM
- IMR_MSPIS
- IMR_MTMR
- IMR_MTMR1
- IMR_MTMR2
- IMR_MUART
- IMR_MWDT
- IMR_NIM
- IMR_NORMAL_MASK
- IMR_NORXTX_MASK
- IMR_NUM
- IMR_NUM_REGS
- IMR_OCPINT
- IMR_OVFIM
- IMR_PAR
- IMR_PHYIM
- IMR_PPRXIM
- IMR_PPTXIM
- IMR_PRM
- IMR_PRXIM
- IMR_PSTIMEOUT
- IMR_PSTIMEOUT_8723B
- IMR_PSTIMEOUT_88E
- IMR_PS_TIMER_A
- IMR_PS_TIMER_B
- IMR_PS_TIMER_C
- IMR_PTM
- IMR_PTX0IM
- IMR_PTX1IM
- IMR_PTX2IM
- IMR_PTX3IM
- IMR_PTXIM
- IMR_PWEIM
- IMR_QUIETSTART
- IMR_RACEIM
- IMR_RADARDETECT
- IMR_RDU
- IMR_RDU_8723B
- IMR_RDU_88E
- IMR_READ_ACCESS_ALL
- IMR_REGISTER_SPACING
- IMR_REGISTER_SPACING_SHIFT
- IMR_RER
- IMR_RIM
- IMR_RMU
- IMR_ROK
- IMR_ROK_8723B
- IMR_ROK_88E
- IMR_ROM
- IMR_ROOM
- IMR_RQOSOK
- IMR_RSM
- IMR_RUM
- IMR_RWM
- IMR_RXCMDOK
- IMR_RXDMA0
- IMR_RXDMA1
- IMR_RXERR
- IMR_RXERR_8723B
- IMR_RXERR_88E
- IMR_RXFOVW
- IMR_RXFOVW_8723B
- IMR_RXFOVW_88E
- IMR_RXNOBUF
- IMR_RXRDY
- IMR_RxRDY_FFULL_A
- IMR_RxRDY_FFULL_B
- IMR_SCSI_INTR_ENABLE
- IMR_SEM
- IMR_SHDNIM
- IMR_SHIFT
- IMR_SOFTINT
- IMR_SOFTTIMER
- IMR_SOFTTIMER1
- IMR_SRCIM
- IMR_TBDER
- IMR_TBDER_88E
- IMR_TBDOK
- IMR_TBDOK_88E
- IMR_TBEDER
- IMR_TBEDOK
- IMR_TBKDER
- IMR_TBKDOK
- IMR_TBTT
- IMR_THPDER
- IMR_THPDOK
- IMR_TIM
- IMR_TIMEOUT0
- IMR_TIMEOUT1
- IMR_TIMEOUT2
- IMR_TIMEOUT3
- IMR_TIMER1
- IMR_TIMER1_8723B
- IMR_TIMER2
- IMR_TIMER2_8723B
- IMR_TJM
- IMR_TMGDOK
- IMR_TMM
- IMR_TMR0IM
- IMR_TMR1IM
- IMR_TRIAL
- IMR_TSF_BIT32_TOGGLE
- IMR_TSF_BIT32_TOGGLE_8723B
- IMR_TSF_BIT32_TOGGLE_88E
- IMR_TSM
- IMR_TUM
- IMR_TVIDER
- IMR_TVIDOK
- IMR_TVODER
- IMR_TVODOK
- IMR_TXBCN0ERR_8723B
- IMR_TXBCN0OK_8723B
- IMR_TXCCK
- IMR_TXCCK_88E
- IMR_TXDMA0
- IMR_TXERR
- IMR_TXERR_8723B
- IMR_TXERR_88E
- IMR_TXFIFO_TH_INT
- IMR_TXFOVW
- IMR_TXFOVW_8723B
- IMR_TXFOVW_88E
- IMR_TXRDY
- IMR_TXSTLM
- IMR_TXWB0IM
- IMR_TXWB1IM
- IMR_TxRDY_A
- IMR_TxRDY_B
- IMR_UDPIM
- IMR_UNDERRUN
- IMR_UNM
- IMR_VC0_SAI_ID0
- IMR_VC0_SAI_ID1
- IMR_VC0_SAI_ID2
- IMR_VC0_SAI_ID3
- IMR_VC1_SAI_ID0
- IMR_VC1_SAI_ID1
- IMR_VC1_SAI_ID2
- IMR_VC1_SAI_ID3
- IMR_VIDOK
- IMR_VIDOK_8723B
- IMR_VIDOK_88E
- IMR_VODOK
- IMR_VODOK_8723B
- IMR_VODOK_88E
- IMR_WAKEINT
- IMR_WATCHDOG
- IMR_WLANOFF
- IMR_WRITE_ACCESS_ALL
- IMS332_REG_COLOR_PALETTE
- IMS332_REG_CURSOR_COLOR_PALETTE
- IMS332_REG_CURSOR_RAM
- IMSCR_IN
- IMSCR_OUT
- IMSETDEVNAME
- IMSK
- IMSR_CLEAR
- IMSTR
- IMSTR_ABORT
- IMSTR_ERRCODE_ACCESS_PERM
- IMSTR_ERRCODE_MASK
- IMSTR_ERRCODE_SECURE_ACCESS
- IMSTR_ERRCODE_TLB_FORMAT
- IMSTR_ERRLVL_MASK
- IMSTR_ERRLVL_SHIFT
- IMSTR_MHIT
- IMSTR_PF
- IMSTR_TF
- IMS_ENABLE_MASK
- IMS_OTHER_MASK
- IMS_PCU_APPLICATION_MODE
- IMS_PCU_ATTR
- IMS_PCU_BL_CMD_ERASE_APP
- IMS_PCU_BL_CMD_LAUNCH_APP
- IMS_PCU_BL_CMD_PROGRAM_COMPLETE
- IMS_PCU_BL_CMD_PROGRAM_DEVICE
- IMS_PCU_BL_CMD_QUERY_DEVICE
- IMS_PCU_BL_CMD_READ_APP
- IMS_PCU_BL_CMD_RESET_DEVICE
- IMS_PCU_BL_CMD_UNLOCK_CONFIG
- IMS_PCU_BL_DATA_OFFSET
- IMS_PCU_BL_RESET_REASON_LEN
- IMS_PCU_BL_RSP_ERASE_APP
- IMS_PCU_BL_RSP_LAUNCH_APP
- IMS_PCU_BL_RSP_PROGRAM_COMPLETE
- IMS_PCU_BL_RSP_PROGRAM_DEVICE
- IMS_PCU_BL_RSP_QUERY_DEVICE
- IMS_PCU_BL_RSP_READ_APP
- IMS_PCU_BL_RSP_RESET_DEVICE
- IMS_PCU_BL_RSP_UNLOCK_CONFIG
- IMS_PCU_BL_VERSION_LEN
- IMS_PCU_BOOTLOADER_MODE
- IMS_PCU_BUF_SIZE
- IMS_PCU_CMD_BOOTLOADER
- IMS_PCU_CMD_EEPROM
- IMS_PCU_CMD_GET_BL_VERSION
- IMS_PCU_CMD_GET_BRIGHTNESS
- IMS_PCU_CMD_GET_DEVICE_ID
- IMS_PCU_CMD_GET_FW_VERSION
- IMS_PCU_CMD_GET_INFO
- IMS_PCU_CMD_JUMP_TO_BTLDR
- IMS_PCU_CMD_OFN_GET_CONFIG
- IMS_PCU_CMD_OFN_SET_CONFIG
- IMS_PCU_CMD_PCU_RESET
- IMS_PCU_CMD_RESET_REASON
- IMS_PCU_CMD_RESPONSE_TIMEOUT
- IMS_PCU_CMD_SEND_BUTTONS
- IMS_PCU_CMD_SET_BRIGHTNESS
- IMS_PCU_CMD_SET_INFO
- IMS_PCU_CMD_SPECIAL_INFO
- IMS_PCU_CMD_STATUS
- IMS_PCU_CMD_WRITE_TIMEOUT
- IMS_PCU_DATA_OFFSET
- IMS_PCU_DEVINFO
- IMS_PCU_DOM_LEN
- IMS_PCU_FIRMWARE_NAME
- IMS_PCU_FW_VERSION_LEN
- IMS_PCU_GAMEPAD_MASK
- IMS_PCU_INFO_DOM_OFFSET
- IMS_PCU_INFO_PART_OFFSET
- IMS_PCU_INFO_SERIAL_OFFSET
- IMS_PCU_KEYMAP_LEN
- IMS_PCU_MAX_BRIGHTNESS
- IMS_PCU_MIN_PACKET_LEN
- IMS_PCU_OFN_BIT_ATTR
- IMS_PCU_PART_NUMBER_LEN
- IMS_PCU_PCU_B_DEVICE_ID
- IMS_PCU_PROTOCOL_DLE
- IMS_PCU_PROTOCOL_ETX
- IMS_PCU_PROTOCOL_STX
- IMS_PCU_RO_ATTR
- IMS_PCU_RSP_BOOTLOADER
- IMS_PCU_RSP_CMD_INVALID
- IMS_PCU_RSP_EEPROM
- IMS_PCU_RSP_EVNT_BUTTONS
- IMS_PCU_RSP_GET_BL_VERSION
- IMS_PCU_RSP_GET_BRIGHTNESS
- IMS_PCU_RSP_GET_DEVICE_ID
- IMS_PCU_RSP_GET_FW_VERSION
- IMS_PCU_RSP_GET_INFO
- IMS_PCU_RSP_JUMP_TO_BTLDR
- IMS_PCU_RSP_OFN_GET_CONFIG
- IMS_PCU_RSP_OFN_SET_CONFIG
- IMS_PCU_RSP_PCU_RESET
- IMS_PCU_RSP_RESET_REASON
- IMS_PCU_RSP_SEND_BUTTONS
- IMS_PCU_RSP_SET_BRIGHTNESS
- IMS_PCU_RSP_SET_INFO
- IMS_PCU_RSP_SPECIAL_INFO
- IMS_PCU_RSP_STATUS
- IMS_PCU_RW_ATTR
- IMS_PCU_SERIAL_NUMBER_LEN
- IMS_PCU_SET_INFO_SIZE
- IMTTBCR
- IMTTBCR_EAE
- IMTTBCR_IRGN0_MASK
- IMTTBCR_IRGN0_NC
- IMTTBCR_IRGN0_WB
- IMTTBCR_IRGN0_WB_WA
- IMTTBCR_IRGN0_WT
- IMTTBCR_IRGN1_MASK
- IMTTBCR_IRGN1_NC
- IMTTBCR_IRGN1_WB
- IMTTBCR_IRGN1_WB_WA
- IMTTBCR_IRGN1_WT
- IMTTBCR_ORGN0_MASK
- IMTTBCR_ORGN0_NC
- IMTTBCR_ORGN0_WB
- IMTTBCR_ORGN0_WB_WA
- IMTTBCR_ORGN0_WT
- IMTTBCR_ORGN1_MASK
- IMTTBCR_ORGN1_NC
- IMTTBCR_ORGN1_WB
- IMTTBCR_ORGN1_WB_WA
- IMTTBCR_ORGN1_WT
- IMTTBCR_PMB
- IMTTBCR_SH0_INNER_SHAREABLE
- IMTTBCR_SH0_MASK
- IMTTBCR_SH0_NON_SHAREABLE
- IMTTBCR_SH0_OUTER_SHAREABLE
- IMTTBCR_SH1_INNER_SHAREABLE
- IMTTBCR_SH1_MASK
- IMTTBCR_SH1_NON_SHAREABLE
- IMTTBCR_SH1_OUTER_SHAREABLE
- IMTTBCR_SL0_LVL_1
- IMTTBCR_SL0_LVL_2
- IMTTBCR_SL0_TWOBIT_LVL_1
- IMTTBCR_SL0_TWOBIT_LVL_2
- IMTTBCR_SL0_TWOBIT_LVL_3
- IMTTBCR_TSZ0_MASK
- IMTTBCR_TSZ0_SHIFT
- IMTTBCR_TSZ1_MASK
- IMTTBCR_TSZ1_SHIFT
- IMTTLBR0
- IMTTLBR1
- IMTTUBR0
- IMTTUBR1
- IMUASID
- IMUASID0
- IMUASID32
- IMUASID_ASID0_MASK
- IMUASID_ASID0_SHIFT
- IMUASID_ASID8_MASK
- IMUASID_ASID8_SHIFT
- IMUCTR
- IMUCTR0
- IMUCTR32
- IMUCTR_FIXADDEN
- IMUCTR_FIXADD_MASK
- IMUCTR_FIXADD_SHIFT
- IMUCTR_FLUSH
- IMUCTR_MMUEN
- IMUCTR_TTSEL_MASK
- IMUCTR_TTSEL_MMU
- IMUCTR_TTSEL_PMB
- IMVR
- IMX074_HEIGHT
- IMX074_WIDTH
- IMX1_CLK_BROM_GATE
- IMX1_CLK_CLK16M
- IMX1_CLK_CLK16M_EXT
- IMX1_CLK_CLK32
- IMX1_CLK_CLK32_PREMULT
- IMX1_CLK_CLK48M
- IMX1_CLK_CLKO
- IMX1_CLK_CSI_GATE
- IMX1_CLK_DMA_GATE
- IMX1_CLK_DUMMY
- IMX1_CLK_FCLK
- IMX1_CLK_HCLK
- IMX1_CLK_MAX
- IMX1_CLK_MCU
- IMX1_CLK_MMA_GATE
- IMX1_CLK_MPLL
- IMX1_CLK_MPLL_GATE
- IMX1_CLK_PER1
- IMX1_CLK_PER2
- IMX1_CLK_PER3
- IMX1_CLK_PREM
- IMX1_CLK_SPLL
- IMX1_CLK_SPLL_GATE
- IMX1_CLK_SSI2_GATE
- IMX1_CLK_UART3_GATE
- IMX1_CLK_USBD_GATE
- IMX1_CSPI
- IMX1_DMA
- IMX1_FB
- IMX1_GPIO
- IMX1_I2C
- IMX1_RTC
- IMX1_UART
- IMX1_UART1_BASE_ADDR
- IMX1_UART2_BASE_ADDR
- IMX1_UART_BASE
- IMX1_UART_BASE_ADDR
- IMX1_UCR1_UARTCLKEN
- IMX1_UTS
- IMX214_DEFAULT_CLK_FREQ
- IMX214_DEFAULT_LINK_FREQ
- IMX214_DEFAULT_PIXEL_RATE
- IMX214_FPS
- IMX214_MAX_RETRIES
- IMX214_MBUS_CODE
- IMX214_NUM_SUPPLIES
- IMX214_TABLE_END
- IMX214_TABLE_WAIT_MS
- IMX214_WAIT_MS
- IMX21_AUDMUX
- IMX21_CLK_BMI_GATE
- IMX21_CLK_BROM_GATE
- IMX21_CLK_CKIH
- IMX21_CLK_CKIH_DIV1P5
- IMX21_CLK_CKIH_GATE
- IMX21_CLK_CKIL
- IMX21_CLK_CSI_HCLK_GATE
- IMX21_CLK_CSPI1_IPG_GATE
- IMX21_CLK_CSPI2_IPG_GATE
- IMX21_CLK_CSPI3_IPG_GATE
- IMX21_CLK_DMA_GATE
- IMX21_CLK_DMA_HCLK_GATE
- IMX21_CLK_DUMMY
- IMX21_CLK_EMMA_GATE
- IMX21_CLK_EMMA_HCLK_GATE
- IMX21_CLK_FCLK
- IMX21_CLK_FPM
- IMX21_CLK_FPM_GATE
- IMX21_CLK_GPIO_GATE
- IMX21_CLK_GPT1_IPG_GATE
- IMX21_CLK_GPT2_IPG_GATE
- IMX21_CLK_GPT3_IPG_GATE
- IMX21_CLK_HCLK
- IMX21_CLK_I2C_GATE
- IMX21_CLK_IPG
- IMX21_CLK_KPP_GATE
- IMX21_CLK_LCDC_HCLK_GATE
- IMX21_CLK_LCDC_IPG_GATE
- IMX21_CLK_MAX
- IMX21_CLK_MPLL
- IMX21_CLK_MPLL_GATE
- IMX21_CLK_MPLL_OSC_SEL
- IMX21_CLK_MPLL_SEL
- IMX21_CLK_NFC_DIV
- IMX21_CLK_NFC_GATE
- IMX21_CLK_OWIRE_GATE
- IMX21_CLK_PER1
- IMX21_CLK_PER2
- IMX21_CLK_PER3
- IMX21_CLK_PER4
- IMX21_CLK_PER4_GATE
- IMX21_CLK_PWM_IPG_GATE
- IMX21_CLK_RTC_GATE
- IMX21_CLK_SDHC1_IPG_GATE
- IMX21_CLK_SDHC2_IPG_GATE
- IMX21_CLK_SLCDC_GATE
- IMX21_CLK_SLCDC_HCLK_GATE
- IMX21_CLK_SPLL
- IMX21_CLK_SPLL_GATE
- IMX21_CLK_SPLL_SEL
- IMX21_CLK_SSI1_BAUD_GATE
- IMX21_CLK_SSI1_DIV
- IMX21_CLK_SSI1_GATE
- IMX21_CLK_SSI1_SEL
- IMX21_CLK_SSI2_BAUD_GATE
- IMX21_CLK_SSI2_DIV
- IMX21_CLK_SSI2_GATE
- IMX21_CLK_SSI2_SEL
- IMX21_CLK_UART1_IPG_GATE
- IMX21_CLK_UART2_IPG_GATE
- IMX21_CLK_UART3_IPG_GATE
- IMX21_CLK_UART4_IPG_GATE
- IMX21_CLK_USB_DIV
- IMX21_CLK_USB_GATE
- IMX21_CLK_USB_HCLK_GATE
- IMX21_CLK_WDOG_GATE
- IMX21_CSPI
- IMX21_DMA
- IMX21_FB
- IMX21_GPIO
- IMX21_I2C
- IMX21_MMC
- IMX21_ONEMS
- IMX21_RTC
- IMX21_UART
- IMX21_UART1_BASE_ADDR
- IMX21_UART2_BASE_ADDR
- IMX21_UART3_BASE_ADDR
- IMX21_UART4_BASE_ADDR
- IMX21_UART_BASE
- IMX21_UART_BASE_ADDR
- IMX21_UCR3_RXDMUXSEL
- IMX21_UTS
- IMX23_AUART
- IMX23_DMA
- IMX23_GPIO
- IMX23_LRADC
- IMX23_SSP
- IMX258_ANA_GAIN_DEFAULT
- IMX258_ANA_GAIN_MAX
- IMX258_ANA_GAIN_MIN
- IMX258_ANA_GAIN_STEP
- IMX258_CHIP_ID
- IMX258_DGTL_GAIN_DEFAULT
- IMX258_DGTL_GAIN_MAX
- IMX258_DGTL_GAIN_MIN
- IMX258_DGTL_GAIN_STEP
- IMX258_EXPOSURE_DEFAULT
- IMX258_EXPOSURE_MAX
- IMX258_EXPOSURE_MIN
- IMX258_EXPOSURE_STEP
- IMX258_FLL_DEFAULT
- IMX258_FLL_MAX
- IMX258_FLL_MIN
- IMX258_FLL_STEP
- IMX258_LINK_FREQ_1267MBPS
- IMX258_LINK_FREQ_320MHZ
- IMX258_LINK_FREQ_634MHZ
- IMX258_LINK_FREQ_640MBPS
- IMX258_MODE_STANDBY
- IMX258_MODE_STREAMING
- IMX258_PPL_DEFAULT
- IMX258_REG_ANALOG_GAIN
- IMX258_REG_B_DIGITAL_GAIN
- IMX258_REG_CHIP_ID
- IMX258_REG_EXPOSURE
- IMX258_REG_GB_DIGITAL_GAIN
- IMX258_REG_GR_DIGITAL_GAIN
- IMX258_REG_MODE_SELECT
- IMX258_REG_R_DIGITAL_GAIN
- IMX258_REG_TEST_PATTERN
- IMX258_REG_VALUE_08BIT
- IMX258_REG_VALUE_16BIT
- IMX258_VTS_30FPS
- IMX258_VTS_30FPS_2K
- IMX258_VTS_30FPS_VGA
- IMX258_VTS_MAX
- IMX25_FEC
- IMX25_UART1_BASE_ADDR
- IMX25_UART2_BASE_ADDR
- IMX25_UART3_BASE_ADDR
- IMX25_UART4_BASE_ADDR
- IMX25_UART5_BASE_ADDR
- IMX25_UART_BASE
- IMX25_UART_BASE_ADDR
- IMX274_ANALOG_GAIN_ADDR_LSB
- IMX274_ANALOG_GAIN_ADDR_MSB
- IMX274_BINNING_2_1
- IMX274_BINNING_3_1
- IMX274_BINNING_OFF
- IMX274_DEFAULT_BINNING
- IMX274_DEFAULT_FRAME_LENGTH
- IMX274_DEF_FRAME_RATE
- IMX274_DEF_GAIN
- IMX274_DIGITAL_GAIN_REG
- IMX274_GAIN_CONST
- IMX274_GAIN_REG_MAX
- IMX274_GAIN_SHIFT
- IMX274_GAIN_SHIFT_MASK
- IMX274_HMAX_REG_LSB
- IMX274_HMAX_REG_MSB
- IMX274_HTRIM_END_REG_LSB
- IMX274_HTRIM_END_REG_MSB
- IMX274_HTRIM_EN_REG
- IMX274_HTRIM_START_REG_LSB
- IMX274_HTRIM_START_REG_MSB
- IMX274_MASK_LSB_2_BITS
- IMX274_MASK_LSB_3_BITS
- IMX274_MASK_LSB_4_BITS
- IMX274_MASK_LSB_8_BITS
- IMX274_MAX_ANALOG_GAIN
- IMX274_MAX_DIGITAL_GAIN
- IMX274_MAX_FRAME_LENGTH
- IMX274_MAX_FRAME_RATE
- IMX274_MAX_HEIGHT
- IMX274_MAX_WIDTH
- IMX274_MIN_EXPOSURE_TIME
- IMX274_MIN_FRAME_RATE
- IMX274_MIN_GAIN
- IMX274_PIXCLK_CONST1
- IMX274_PIXCLK_CONST2
- IMX274_RESET_DELAY1
- IMX274_RESET_DELAY2
- IMX274_ROUND
- IMX274_SHIFT_16_BITS
- IMX274_SHIFT_8_BITS
- IMX274_SHR_LIMIT_CONST
- IMX274_SHR_REG_LSB
- IMX274_SHR_REG_MSB
- IMX274_STANDBY_REG
- IMX274_SVR_REG_LSB
- IMX274_SVR_REG_MSB
- IMX274_TABLE_END
- IMX274_TABLE_WAIT_MS
- IMX274_TEST_PATTERN_REG
- IMX274_VFLIP_REG
- IMX274_VMAX_REG_1
- IMX274_VMAX_REG_2
- IMX274_VMAX_REG_3
- IMX274_VWIDCUTEN_REG
- IMX274_VWIDCUT_REG_LSB
- IMX274_VWIDCUT_REG_MSB
- IMX274_VWINPOS_REG_LSB
- IMX274_VWINPOS_REG_MSB
- IMX274_WRITE_VSIZE_REG_LSB
- IMX274_WRITE_VSIZE_REG_MSB
- IMX274_Y_OUT_SIZE_REG_LSB
- IMX274_Y_OUT_SIZE_REG_MSB
- IMX27_CLK_AHB
- IMX27_CLK_ATA_AHB_GATE
- IMX27_CLK_BROM_AHB_GATE
- IMX27_CLK_CKIH
- IMX27_CLK_CKIH_DIV1P5
- IMX27_CLK_CKIH_GATE
- IMX27_CLK_CKIL
- IMX27_CLK_CLKO_DIV
- IMX27_CLK_CLKO_EN
- IMX27_CLK_CLKO_SEL
- IMX27_CLK_CPU_DIV
- IMX27_CLK_CPU_SEL
- IMX27_CLK_CSI_AHB_GATE
- IMX27_CLK_CSPI1_IPG_GATE
- IMX27_CLK_CSPI2_IPG_GATE
- IMX27_CLK_CSPI3_IPG_GATE
- IMX27_CLK_DMA_AHB_GATE
- IMX27_CLK_DMA_IPG_GATE
- IMX27_CLK_DUMMY
- IMX27_CLK_EMI_AHB_GATE
- IMX27_CLK_EMMA_AHB_GATE
- IMX27_CLK_EMMA_IPG_GATE
- IMX27_CLK_FEC_AHB_GATE
- IMX27_CLK_FEC_IPG_GATE
- IMX27_CLK_FPM
- IMX27_CLK_GPIO_IPG_GATE
- IMX27_CLK_GPT1_IPG_GATE
- IMX27_CLK_GPT2_IPG_GATE
- IMX27_CLK_GPT3_IPG_GATE
- IMX27_CLK_GPT4_IPG_GATE
- IMX27_CLK_GPT5_IPG_GATE
- IMX27_CLK_GPT6_IPG_GATE
- IMX27_CLK_I2C1_IPG_GATE
- IMX27_CLK_I2C2_IPG_GATE
- IMX27_CLK_IIM_IPG_GATE
- IMX27_CLK_IPG
- IMX27_CLK_KPP_IPG_GATE
- IMX27_CLK_LCDC_AHB_GATE
- IMX27_CLK_LCDC_IPG_GATE
- IMX27_CLK_MAX
- IMX27_CLK_MPLL
- IMX27_CLK_MPLL_MAIN2
- IMX27_CLK_MPLL_OSC_SEL
- IMX27_CLK_MPLL_SEL
- IMX27_CLK_MSHC_BAUD_GATE
- IMX27_CLK_MSHC_DIV
- IMX27_CLK_MSHC_IPG_GATE
- IMX27_CLK_NFC_BAUD_GATE
- IMX27_CLK_NFC_DIV
- IMX27_CLK_OWIRE_IPG_GATE
- IMX27_CLK_PER1_DIV
- IMX27_CLK_PER1_GATE
- IMX27_CLK_PER2_DIV
- IMX27_CLK_PER2_GATE
- IMX27_CLK_PER3_DIV
- IMX27_CLK_PER3_GATE
- IMX27_CLK_PER4_DIV
- IMX27_CLK_PER4_GATE
- IMX27_CLK_PWM_IPG_GATE
- IMX27_CLK_RTC_IPG_GATE
- IMX27_CLK_RTIC_AHB_GATE
- IMX27_CLK_RTIC_IPG_GATE
- IMX27_CLK_SAHARA_AHB_GATE
- IMX27_CLK_SAHARA_IPG_GATE
- IMX27_CLK_SCC_IPG_GATE
- IMX27_CLK_SDHC1_IPG_GATE
- IMX27_CLK_SDHC2_IPG_GATE
- IMX27_CLK_SDHC3_IPG_GATE
- IMX27_CLK_SLCDC_AHB_GATE
- IMX27_CLK_SLCDC_IPG_GATE
- IMX27_CLK_SPLL
- IMX27_CLK_SPLL_GATE
- IMX27_CLK_SSI1_BAUD_GATE
- IMX27_CLK_SSI1_DIV
- IMX27_CLK_SSI1_IPG_GATE
- IMX27_CLK_SSI1_SEL
- IMX27_CLK_SSI2_BAUD_GATE
- IMX27_CLK_SSI2_DIV
- IMX27_CLK_SSI2_IPG_GATE
- IMX27_CLK_SSI2_SEL
- IMX27_CLK_UART1_IPG_GATE
- IMX27_CLK_UART2_IPG_GATE
- IMX27_CLK_UART3_IPG_GATE
- IMX27_CLK_UART4_IPG_GATE
- IMX27_CLK_UART5_IPG_GATE
- IMX27_CLK_UART6_IPG_GATE
- IMX27_CLK_USB_AHB_GATE
- IMX27_CLK_USB_DIV
- IMX27_CLK_USB_IPG_GATE
- IMX27_CLK_VPU_AHB_GATE
- IMX27_CLK_VPU_BAUD_GATE
- IMX27_CLK_VPU_DIV
- IMX27_CLK_VPU_SEL
- IMX27_CLK_WDOG_IPG_GATE
- IMX27_CSPI
- IMX27_DMA
- IMX27_FEC
- IMX28_AUART
- IMX28_DMA
- IMX28_FEC
- IMX28_GPIO
- IMX28_LRADC
- IMX28_SSP
- IMX2_WDT_DEFAULT_TIME
- IMX2_WDT_MAX_TIME
- IMX2_WDT_SEQ1
- IMX2_WDT_SEQ2
- IMX2_WDT_WCR
- IMX2_WDT_WCR_SRS
- IMX2_WDT_WCR_WDA
- IMX2_WDT_WCR_WDE
- IMX2_WDT_WCR_WDZST
- IMX2_WDT_WCR_WRE
- IMX2_WDT_WCR_WT
- IMX2_WDT_WICR
- IMX2_WDT_WICR_WICT
- IMX2_WDT_WICR_WIE
- IMX2_WDT_WICR_WTIS
- IMX2_WDT_WMCR
- IMX2_WDT_WRSR
- IMX2_WDT_WRSR_TOUT
- IMX2_WDT_WSR
- IMX319_ANA_GAIN_DEFAULT
- IMX319_ANA_GAIN_MAX
- IMX319_ANA_GAIN_MIN
- IMX319_ANA_GAIN_STEP
- IMX319_CHIP_ID
- IMX319_DGTL_GAIN_DEFAULT
- IMX319_DGTL_GAIN_MAX
- IMX319_DGTL_GAIN_MIN
- IMX319_DGTL_GAIN_STEP
- IMX319_EXPOSURE_DEFAULT
- IMX319_EXPOSURE_MIN
- IMX319_EXPOSURE_STEP
- IMX319_EXT_CLK
- IMX319_FLL_MAX
- IMX319_LINK_FREQ_DEFAULT
- IMX319_LINK_FREQ_INDEX
- IMX319_MODE_STANDBY
- IMX319_MODE_STREAMING
- IMX319_REG_ANALOG_GAIN
- IMX319_REG_CHIP_ID
- IMX319_REG_DIG_GAIN_GLOBAL
- IMX319_REG_DPGA_USE_GLOBAL_GAIN
- IMX319_REG_EXPOSURE
- IMX319_REG_FLL
- IMX319_REG_MODE_SELECT
- IMX319_REG_ORIENTATION
- IMX319_REG_TEST_PATTERN
- IMX319_TEST_PATTERN_COLOR_BARS
- IMX319_TEST_PATTERN_DISABLED
- IMX319_TEST_PATTERN_GRAY_COLOR_BARS
- IMX319_TEST_PATTERN_PN9
- IMX319_TEST_PATTERN_SOLID_COLOR
- IMX31_AUDMUX
- IMX31_CSPI
- IMX31_GPIO
- IMX31_MMC
- IMX31_UART1_BASE_ADDR
- IMX31_UART2_BASE_ADDR
- IMX31_UART3_BASE_ADDR
- IMX31_UART4_BASE_ADDR
- IMX31_UART5_BASE_ADDR
- IMX31_UART_BASE
- IMX31_UART_BASE_ADDR
- IMX355_ANA_GAIN_DEFAULT
- IMX355_ANA_GAIN_MAX
- IMX355_ANA_GAIN_MIN
- IMX355_ANA_GAIN_STEP
- IMX355_CHIP_ID
- IMX355_DGTL_GAIN_DEFAULT
- IMX355_DGTL_GAIN_MAX
- IMX355_DGTL_GAIN_MIN
- IMX355_DGTL_GAIN_STEP
- IMX355_EXPOSURE_DEFAULT
- IMX355_EXPOSURE_MIN
- IMX355_EXPOSURE_STEP
- IMX355_EXT_CLK
- IMX355_FLL_MAX
- IMX355_LINK_FREQ_DEFAULT
- IMX355_LINK_FREQ_INDEX
- IMX355_MODE_STANDBY
- IMX355_MODE_STREAMING
- IMX355_REG_ANALOG_GAIN
- IMX355_REG_CHIP_ID
- IMX355_REG_DIG_GAIN_GLOBAL
- IMX355_REG_DPGA_USE_GLOBAL_GAIN
- IMX355_REG_EXPOSURE
- IMX355_REG_FLL
- IMX355_REG_MODE_SELECT
- IMX355_REG_ORIENTATION
- IMX355_REG_TEST_PATTERN
- IMX355_TEST_PATTERN_COLOR_BARS
- IMX355_TEST_PATTERN_DISABLED
- IMX355_TEST_PATTERN_GRAY_COLOR_BARS
- IMX355_TEST_PATTERN_PN9
- IMX355_TEST_PATTERN_SOLID_COLOR
- IMX35_CSPI
- IMX35_GPIO
- IMX35_UART1_BASE_ADDR
- IMX35_UART2_BASE_ADDR
- IMX35_UART3_BASE_ADDR
- IMX35_UART_BASE
- IMX35_UART_BASE_ADDR
- IMX50_UART1_BASE_ADDR
- IMX50_UART2_BASE_ADDR
- IMX50_UART3_BASE_ADDR
- IMX50_UART4_BASE_ADDR
- IMX50_UART5_BASE_ADDR
- IMX50_UART_BASE
- IMX50_UART_BASE_ADDR
- IMX51_ECSPI
- IMX51_UART1_BASE_ADDR
- IMX51_UART2_BASE_ADDR
- IMX51_UART3_BASE_ADDR
- IMX51_UART_BASE
- IMX51_UART_BASE_ADDR
- IMX53_ECSPI
- IMX53_UART
- IMX53_UART1_BASE_ADDR
- IMX53_UART2_BASE_ADDR
- IMX53_UART3_BASE_ADDR
- IMX53_UART4_BASE_ADDR
- IMX53_UART5_BASE_ADDR
- IMX53_UART_BASE
- IMX53_UART_BASE_ADDR
- IMX5_CLK_AHB
- IMX5_CLK_AHB_MAX
- IMX5_CLK_AIPS_TZ1
- IMX5_CLK_AIPS_TZ2
- IMX5_CLK_ARM
- IMX5_CLK_AXI_A
- IMX5_CLK_AXI_B
- IMX5_CLK_CAN1_IPG_GATE
- IMX5_CLK_CAN1_SERIAL_GATE
- IMX5_CLK_CAN2_IPG_GATE
- IMX5_CLK_CAN2_SERIAL_GATE
- IMX5_CLK_CAN_SEL
- IMX5_CLK_CKIH1
- IMX5_CLK_CKIH2
- IMX5_CLK_CKIL
- IMX5_CLK_CKO1
- IMX5_CLK_CKO1_PODF
- IMX5_CLK_CKO1_SEL
- IMX5_CLK_CKO2
- IMX5_CLK_CKO2_PODF
- IMX5_CLK_CKO2_SEL
- IMX5_CLK_CPU_PODF
- IMX5_CLK_CPU_PODF_SEL
- IMX5_CLK_CSI0_MCLK1_GATE
- IMX5_CLK_CSI0_MCLK1_PODF
- IMX5_CLK_CSI0_MCLK1_PRED
- IMX5_CLK_CSI0_MCLK1_SEL
- IMX5_CLK_CSPI_IPG_GATE
- IMX5_CLK_DI_PLL4_PODF
- IMX5_CLK_DI_PRED
- IMX5_CLK_DUMMY
- IMX5_CLK_ECSPI1_IPG_GATE
- IMX5_CLK_ECSPI1_PER_GATE
- IMX5_CLK_ECSPI2_IPG_GATE
- IMX5_CLK_ECSPI2_PER_GATE
- IMX5_CLK_ECSPI_PODF
- IMX5_CLK_ECSPI_PRED
- IMX5_CLK_ECSPI_SEL
- IMX5_CLK_EMI_FAST_GATE
- IMX5_CLK_EMI_SEL
- IMX5_CLK_EMI_SLOW_GATE
- IMX5_CLK_EMI_SLOW_PODF
- IMX5_CLK_END
- IMX5_CLK_EPIT1_HF_GATE
- IMX5_CLK_EPIT1_IPG_GATE
- IMX5_CLK_EPIT2_HF_GATE
- IMX5_CLK_EPIT2_IPG_GATE
- IMX5_CLK_ESDHC1_IPG_GATE
- IMX5_CLK_ESDHC1_PER_GATE
- IMX5_CLK_ESDHC2_IPG_GATE
- IMX5_CLK_ESDHC2_PER_GATE
- IMX5_CLK_ESDHC3_IPG_GATE
- IMX5_CLK_ESDHC3_PER_GATE
- IMX5_CLK_ESDHC4_IPG_GATE
- IMX5_CLK_ESDHC4_PER_GATE
- IMX5_CLK_ESDHC_A_PODF
- IMX5_CLK_ESDHC_A_PRED
- IMX5_CLK_ESDHC_A_SEL
- IMX5_CLK_ESDHC_B_PODF
- IMX5_CLK_ESDHC_B_PRED
- IMX5_CLK_ESDHC_B_SEL
- IMX5_CLK_ESDHC_C_SEL
- IMX5_CLK_ESDHC_D_SEL
- IMX5_CLK_FEC_GATE
- IMX5_CLK_FIRI_IPG_GATE
- IMX5_CLK_FIRI_PODF
- IMX5_CLK_FIRI_PRED
- IMX5_CLK_FIRI_SEL
- IMX5_CLK_FIRI_SERIAL_GATE
- IMX5_CLK_GARB_GATE
- IMX5_CLK_GPC_DVFS
- IMX5_CLK_GPT_HF_GATE
- IMX5_CLK_GPT_IPG_GATE
- IMX5_CLK_GPU2D_GATE
- IMX5_CLK_GPU2D_SEL
- IMX5_CLK_GPU3D_GATE
- IMX5_CLK_GPU3D_SEL
- IMX5_CLK_HSI2C_GATE
- IMX5_CLK_I2C1_GATE
- IMX5_CLK_I2C2_GATE
- IMX5_CLK_I2C3_GATE
- IMX5_CLK_IEEE1588_GATE
- IMX5_CLK_IEEE1588_PODF
- IMX5_CLK_IEEE1588_PRED
- IMX5_CLK_IEEE1588_SEL
- IMX5_CLK_IIM_GATE
- IMX5_CLK_IPG
- IMX5_CLK_IPU_DI0_GATE
- IMX5_CLK_IPU_DI0_SEL
- IMX5_CLK_IPU_DI1_GATE
- IMX5_CLK_IPU_DI1_SEL
- IMX5_CLK_IPU_GATE
- IMX5_CLK_IPU_SEL
- IMX5_CLK_LDB_DI0_DIV
- IMX5_CLK_LDB_DI0_DIV_3_5
- IMX5_CLK_LDB_DI0_GATE
- IMX5_CLK_LDB_DI0_SEL
- IMX5_CLK_LDB_DI1_DIV
- IMX5_CLK_LDB_DI1_DIV_3_5
- IMX5_CLK_LDB_DI1_GATE
- IMX5_CLK_LDB_DI1_SEL
- IMX5_CLK_LP_APM
- IMX5_CLK_MAIN_BUS
- IMX5_CLK_MIPI_ESC_GATE
- IMX5_CLK_MIPI_HSC1_GATE
- IMX5_CLK_MIPI_HSC2_GATE
- IMX5_CLK_MIPI_HSP_GATE
- IMX5_CLK_MX51_MIPI
- IMX5_CLK_NFC_GATE
- IMX5_CLK_NFC_PODF
- IMX5_CLK_OCRAM
- IMX5_CLK_OSC
- IMX5_CLK_OWIRE_GATE
- IMX5_CLK_PATA_GATE
- IMX5_CLK_PERIPH_APM
- IMX5_CLK_PER_LP_APM
- IMX5_CLK_PER_PODF
- IMX5_CLK_PER_PRED1
- IMX5_CLK_PER_PRED2
- IMX5_CLK_PER_ROOT
- IMX5_CLK_PLL1_SW
- IMX5_CLK_PLL2_SW
- IMX5_CLK_PLL3_SW
- IMX5_CLK_PLL4_SW
- IMX5_CLK_PWM1_HF_GATE
- IMX5_CLK_PWM1_IPG_GATE
- IMX5_CLK_PWM2_HF_GATE
- IMX5_CLK_PWM2_IPG_GATE
- IMX5_CLK_SAHARA_IPG_GATE
- IMX5_CLK_SATA_GATE
- IMX5_CLK_SATA_REF
- IMX5_CLK_SCC2_IPG_GATE
- IMX5_CLK_SDMA_GATE
- IMX5_CLK_SPBA
- IMX5_CLK_SPDIF0_COM_SEL
- IMX5_CLK_SPDIF0_GATE
- IMX5_CLK_SPDIF0_PODF
- IMX5_CLK_SPDIF0_PRED
- IMX5_CLK_SPDIF0_SEL
- IMX5_CLK_SPDIF1_COM_SEL
- IMX5_CLK_SPDIF1_GATE
- IMX5_CLK_SPDIF1_PODF
- IMX5_CLK_SPDIF1_PRED
- IMX5_CLK_SPDIF1_SEL
- IMX5_CLK_SPDIF_IPG_GATE
- IMX5_CLK_SPDIF_XTAL_SEL
- IMX5_CLK_SRTC_GATE
- IMX5_CLK_SSI1_IPG_GATE
- IMX5_CLK_SSI1_ROOT_GATE
- IMX5_CLK_SSI1_ROOT_PODF
- IMX5_CLK_SSI1_ROOT_PRED
- IMX5_CLK_SSI1_ROOT_SEL
- IMX5_CLK_SSI2_IPG_GATE
- IMX5_CLK_SSI2_ROOT_GATE
- IMX5_CLK_SSI2_ROOT_PODF
- IMX5_CLK_SSI2_ROOT_PRED
- IMX5_CLK_SSI2_ROOT_SEL
- IMX5_CLK_SSI3_IPG_GATE
- IMX5_CLK_SSI3_ROOT_GATE
- IMX5_CLK_SSI3_ROOT_SEL
- IMX5_CLK_SSI_APM
- IMX5_CLK_SSI_EXT1_COM_SEL
- IMX5_CLK_SSI_EXT1_GATE
- IMX5_CLK_SSI_EXT1_PODF
- IMX5_CLK_SSI_EXT1_PRED
- IMX5_CLK_SSI_EXT1_SEL
- IMX5_CLK_SSI_EXT2_COM_SEL
- IMX5_CLK_SSI_EXT2_GATE
- IMX5_CLK_SSI_EXT2_PODF
- IMX5_CLK_SSI_EXT2_PRED
- IMX5_CLK_SSI_EXT2_SEL
- IMX5_CLK_STEP_SEL
- IMX5_CLK_TMAX1
- IMX5_CLK_TMAX2
- IMX5_CLK_TMAX3
- IMX5_CLK_TVE_EXT_SEL
- IMX5_CLK_TVE_GATE
- IMX5_CLK_TVE_PRED
- IMX5_CLK_TVE_SEL
- IMX5_CLK_UART1_IPG_GATE
- IMX5_CLK_UART1_PER_GATE
- IMX5_CLK_UART2_IPG_GATE
- IMX5_CLK_UART2_PER_GATE
- IMX5_CLK_UART3_IPG_GATE
- IMX5_CLK_UART3_PER_GATE
- IMX5_CLK_UART4_IPG_GATE
- IMX5_CLK_UART4_PER_GATE
- IMX5_CLK_UART5_IPG_GATE
- IMX5_CLK_UART5_PER_GATE
- IMX5_CLK_UART_PRED
- IMX5_CLK_UART_ROOT
- IMX5_CLK_UART_SEL
- IMX5_CLK_USBOH3_GATE
- IMX5_CLK_USBOH3_PER_GATE
- IMX5_CLK_USBOH3_PODF
- IMX5_CLK_USBOH3_PRED
- IMX5_CLK_USBOH3_SEL
- IMX5_CLK_USB_PHY1_GATE
- IMX5_CLK_USB_PHY2_GATE
- IMX5_CLK_USB_PHY_GATE
- IMX5_CLK_USB_PHY_PODF
- IMX5_CLK_USB_PHY_PRED
- IMX5_CLK_USB_PHY_SEL
- IMX5_CLK_VPU_GATE
- IMX5_CLK_VPU_REFERENCE_GATE
- IMX5_CLK_VPU_SEL
- IMX5_DEFAULT_CPU_IDLE_STATE
- IMX6DL_CLK_I2C4
- IMX6Q
- IMX6QDL_CLK_AHB
- IMX6QDL_CLK_ANACLK1
- IMX6QDL_CLK_ANACLK2
- IMX6QDL_CLK_APBH_DMA
- IMX6QDL_CLK_ARM
- IMX6QDL_CLK_ASRC
- IMX6QDL_CLK_ASRC_IPG
- IMX6QDL_CLK_ASRC_MEM
- IMX6QDL_CLK_ASRC_PODF
- IMX6QDL_CLK_ASRC_PRED
- IMX6QDL_CLK_ASRC_SEL
- IMX6QDL_CLK_AXI
- IMX6QDL_CLK_AXI_SEL
- IMX6QDL_CLK_CAAM_ACLK
- IMX6QDL_CLK_CAAM_IPG
- IMX6QDL_CLK_CAAM_MEM
- IMX6QDL_CLK_CAN1_IPG
- IMX6QDL_CLK_CAN1_SERIAL
- IMX6QDL_CLK_CAN2_IPG
- IMX6QDL_CLK_CAN2_SERIAL
- IMX6QDL_CLK_CAN_ROOT
- IMX6QDL_CLK_CAN_SEL
- IMX6QDL_CLK_CKIH
- IMX6QDL_CLK_CKIL
- IMX6QDL_CLK_CKO
- IMX6QDL_CLK_CKO1
- IMX6QDL_CLK_CKO1_PODF
- IMX6QDL_CLK_CKO1_SEL
- IMX6QDL_CLK_CKO2
- IMX6QDL_CLK_CKO2_PODF
- IMX6QDL_CLK_CKO2_SEL
- IMX6QDL_CLK_DCIC1
- IMX6QDL_CLK_DCIC2
- IMX6QDL_CLK_DUMMY
- IMX6QDL_CLK_ECSPI1
- IMX6QDL_CLK_ECSPI2
- IMX6QDL_CLK_ECSPI3
- IMX6QDL_CLK_ECSPI4
- IMX6QDL_CLK_ECSPI_ROOT
- IMX6QDL_CLK_ECSPI_SEL
- IMX6QDL_CLK_EIM_PODF
- IMX6QDL_CLK_EIM_SEL
- IMX6QDL_CLK_EIM_SLOW
- IMX6QDL_CLK_EIM_SLOW_PODF
- IMX6QDL_CLK_EIM_SLOW_SEL
- IMX6QDL_CLK_END
- IMX6QDL_CLK_ENET
- IMX6QDL_CLK_ENET_REF
- IMX6QDL_CLK_ENFC
- IMX6QDL_CLK_ENFC_PODF
- IMX6QDL_CLK_ENFC_PRED
- IMX6QDL_CLK_ENFC_SEL
- IMX6QDL_CLK_EPIT1
- IMX6QDL_CLK_EPIT2
- IMX6QDL_CLK_ESAI_EXTAL
- IMX6QDL_CLK_ESAI_IPG
- IMX6QDL_CLK_ESAI_MEM
- IMX6QDL_CLK_ESAI_PODF
- IMX6QDL_CLK_ESAI_PRED
- IMX6QDL_CLK_ESAI_SEL
- IMX6QDL_CLK_GPMI_APB
- IMX6QDL_CLK_GPMI_BCH
- IMX6QDL_CLK_GPMI_BCH_APB
- IMX6QDL_CLK_GPMI_IO
- IMX6QDL_CLK_GPT_3M
- IMX6QDL_CLK_GPT_IPG
- IMX6QDL_CLK_GPT_IPG_PER
- IMX6QDL_CLK_GPU2D_AXI
- IMX6QDL_CLK_GPU2D_CORE
- IMX6QDL_CLK_GPU2D_CORE_PODF
- IMX6QDL_CLK_GPU2D_CORE_SEL
- IMX6QDL_CLK_GPU3D_AXI
- IMX6QDL_CLK_GPU3D_CORE
- IMX6QDL_CLK_GPU3D_CORE_PODF
- IMX6QDL_CLK_GPU3D_CORE_SEL
- IMX6QDL_CLK_GPU3D_SHADER
- IMX6QDL_CLK_GPU3D_SHADER_SEL
- IMX6QDL_CLK_HDMI_IAHB
- IMX6QDL_CLK_HDMI_ISFR
- IMX6QDL_CLK_HSI_TX
- IMX6QDL_CLK_HSI_TX_PODF
- IMX6QDL_CLK_HSI_TX_SEL
- IMX6QDL_CLK_I2C1
- IMX6QDL_CLK_I2C2
- IMX6QDL_CLK_I2C3
- IMX6QDL_CLK_IIM
- IMX6QDL_CLK_IPG
- IMX6QDL_CLK_IPG_PER
- IMX6QDL_CLK_IPG_PER_SEL
- IMX6QDL_CLK_IPU1
- IMX6QDL_CLK_IPU1_DI0
- IMX6QDL_CLK_IPU1_DI0_PRE
- IMX6QDL_CLK_IPU1_DI0_PRE_SEL
- IMX6QDL_CLK_IPU1_DI0_SEL
- IMX6QDL_CLK_IPU1_DI1
- IMX6QDL_CLK_IPU1_DI1_PRE
- IMX6QDL_CLK_IPU1_DI1_PRE_SEL
- IMX6QDL_CLK_IPU1_DI1_SEL
- IMX6QDL_CLK_IPU1_PODF
- IMX6QDL_CLK_IPU1_SEL
- IMX6QDL_CLK_IPU2
- IMX6QDL_CLK_IPU2_DI0
- IMX6QDL_CLK_IPU2_DI0_PRE
- IMX6QDL_CLK_IPU2_DI0_PRE_SEL
- IMX6QDL_CLK_IPU2_DI0_SEL
- IMX6QDL_CLK_IPU2_DI1
- IMX6QDL_CLK_IPU2_DI1_PRE
- IMX6QDL_CLK_IPU2_DI1_PRE_SEL
- IMX6QDL_CLK_IPU2_DI1_SEL
- IMX6QDL_CLK_IPU2_PODF
- IMX6QDL_CLK_IPU2_SEL
- IMX6QDL_CLK_LDB_DI0
- IMX6QDL_CLK_LDB_DI0_DIV_3_5
- IMX6QDL_CLK_LDB_DI0_PODF
- IMX6QDL_CLK_LDB_DI0_SEL
- IMX6QDL_CLK_LDB_DI1
- IMX6QDL_CLK_LDB_DI1_DIV_3_5
- IMX6QDL_CLK_LDB_DI1_PODF
- IMX6QDL_CLK_LDB_DI1_SEL
- IMX6QDL_CLK_LVDS1_GATE
- IMX6QDL_CLK_LVDS1_IN
- IMX6QDL_CLK_LVDS1_SEL
- IMX6QDL_CLK_LVDS2_GATE
- IMX6QDL_CLK_LVDS2_IN
- IMX6QDL_CLK_LVDS2_SEL
- IMX6QDL_CLK_MIPI_CORE_CFG
- IMX6QDL_CLK_MIPI_IPG
- IMX6QDL_CLK_MLB
- IMX6QDL_CLK_MLB_PODF
- IMX6QDL_CLK_MLB_SEL
- IMX6QDL_CLK_MMDC_CH0_AXI
- IMX6QDL_CLK_MMDC_CH0_AXI_PODF
- IMX6QDL_CLK_MMDC_CH1_AXI
- IMX6QDL_CLK_MMDC_CH1_AXI_CG
- IMX6QDL_CLK_MMDC_CH1_AXI_PODF
- IMX6QDL_CLK_MMDC_P0_IPG
- IMX6QDL_CLK_OCRAM
- IMX6QDL_CLK_OPENVG_AXI
- IMX6QDL_CLK_OSC
- IMX6QDL_CLK_PCIE_AXI
- IMX6QDL_CLK_PCIE_AXI_SEL
- IMX6QDL_CLK_PCIE_REF
- IMX6QDL_CLK_PCIE_REF_125M
- IMX6QDL_CLK_PER1_BCH
- IMX6QDL_CLK_PERIPH
- IMX6QDL_CLK_PERIPH2
- IMX6QDL_CLK_PERIPH2_CLK2
- IMX6QDL_CLK_PERIPH2_CLK2_SEL
- IMX6QDL_CLK_PERIPH2_PRE
- IMX6QDL_CLK_PERIPH_CLK2
- IMX6QDL_CLK_PERIPH_CLK2_SEL
- IMX6QDL_CLK_PERIPH_PRE
- IMX6QDL_CLK_PLL1
- IMX6QDL_CLK_PLL1_SW
- IMX6QDL_CLK_PLL1_SYS
- IMX6QDL_CLK_PLL2
- IMX6QDL_CLK_PLL2_198M
- IMX6QDL_CLK_PLL2_BUS
- IMX6QDL_CLK_PLL2_PFD0_352M
- IMX6QDL_CLK_PLL2_PFD1_594M
- IMX6QDL_CLK_PLL2_PFD2_396M
- IMX6QDL_CLK_PLL3
- IMX6QDL_CLK_PLL3_120M
- IMX6QDL_CLK_PLL3_60M
- IMX6QDL_CLK_PLL3_80M
- IMX6QDL_CLK_PLL3_PFD0_720M
- IMX6QDL_CLK_PLL3_PFD1_540M
- IMX6QDL_CLK_PLL3_PFD2_508M
- IMX6QDL_CLK_PLL3_PFD3_454M
- IMX6QDL_CLK_PLL3_USB_OTG
- IMX6QDL_CLK_PLL4
- IMX6QDL_CLK_PLL4_AUDIO
- IMX6QDL_CLK_PLL4_AUDIO_DIV
- IMX6QDL_CLK_PLL4_POST_DIV
- IMX6QDL_CLK_PLL5
- IMX6QDL_CLK_PLL5_POST_DIV
- IMX6QDL_CLK_PLL5_VIDEO
- IMX6QDL_CLK_PLL5_VIDEO_DIV
- IMX6QDL_CLK_PLL6
- IMX6QDL_CLK_PLL6_ENET
- IMX6QDL_CLK_PLL7
- IMX6QDL_CLK_PLL7_USB_HOST
- IMX6QDL_CLK_PLL8_MLB
- IMX6QDL_CLK_PRE0
- IMX6QDL_CLK_PRE1
- IMX6QDL_CLK_PRE2
- IMX6QDL_CLK_PRE3
- IMX6QDL_CLK_PRE_AXI
- IMX6QDL_CLK_PRG0_APB
- IMX6QDL_CLK_PRG0_AXI
- IMX6QDL_CLK_PRG1_APB
- IMX6QDL_CLK_PRG1_AXI
- IMX6QDL_CLK_PWM1
- IMX6QDL_CLK_PWM2
- IMX6QDL_CLK_PWM3
- IMX6QDL_CLK_PWM4
- IMX6QDL_CLK_ROM
- IMX6QDL_CLK_SATA
- IMX6QDL_CLK_SATA_REF
- IMX6QDL_CLK_SATA_REF_100M
- IMX6QDL_CLK_SDMA
- IMX6QDL_CLK_SPBA
- IMX6QDL_CLK_SPDIF
- IMX6QDL_CLK_SPDIF_GCLK
- IMX6QDL_CLK_SPDIF_PODF
- IMX6QDL_CLK_SPDIF_PRED
- IMX6QDL_CLK_SPDIF_SEL
- IMX6QDL_CLK_SSI1
- IMX6QDL_CLK_SSI1_IPG
- IMX6QDL_CLK_SSI1_PODF
- IMX6QDL_CLK_SSI1_PRED
- IMX6QDL_CLK_SSI1_SEL
- IMX6QDL_CLK_SSI2
- IMX6QDL_CLK_SSI2_IPG
- IMX6QDL_CLK_SSI2_PODF
- IMX6QDL_CLK_SSI2_PRED
- IMX6QDL_CLK_SSI2_SEL
- IMX6QDL_CLK_SSI3
- IMX6QDL_CLK_SSI3_IPG
- IMX6QDL_CLK_SSI3_PODF
- IMX6QDL_CLK_SSI3_PRED
- IMX6QDL_CLK_SSI3_SEL
- IMX6QDL_CLK_STEP
- IMX6QDL_CLK_TWD
- IMX6QDL_CLK_UART_IPG
- IMX6QDL_CLK_UART_SEL
- IMX6QDL_CLK_UART_SERIAL
- IMX6QDL_CLK_UART_SERIAL_PODF
- IMX6QDL_CLK_USBOH3
- IMX6QDL_CLK_USBPHY1
- IMX6QDL_CLK_USBPHY1_GATE
- IMX6QDL_CLK_USBPHY2
- IMX6QDL_CLK_USBPHY2_GATE
- IMX6QDL_CLK_USDHC1
- IMX6QDL_CLK_USDHC1_PODF
- IMX6QDL_CLK_USDHC1_SEL
- IMX6QDL_CLK_USDHC2
- IMX6QDL_CLK_USDHC2_PODF
- IMX6QDL_CLK_USDHC2_SEL
- IMX6QDL_CLK_USDHC3
- IMX6QDL_CLK_USDHC3_PODF
- IMX6QDL_CLK_USDHC3_SEL
- IMX6QDL_CLK_USDHC4
- IMX6QDL_CLK_USDHC4_PODF
- IMX6QDL_CLK_USDHC4_SEL
- IMX6QDL_CLK_VDOA
- IMX6QDL_CLK_VDO_AXI
- IMX6QDL_CLK_VDO_AXI_SEL
- IMX6QDL_CLK_VIDEO_27M
- IMX6QDL_CLK_VPU_AXI
- IMX6QDL_CLK_VPU_AXI_PODF
- IMX6QDL_CLK_VPU_AXI_SEL
- IMX6QDL_PLL1_BYPASS
- IMX6QDL_PLL1_BYPASS_SRC
- IMX6QDL_PLL2_BYPASS
- IMX6QDL_PLL2_BYPASS_SRC
- IMX6QDL_PLL3_BYPASS
- IMX6QDL_PLL3_BYPASS_SRC
- IMX6QDL_PLL4_BYPASS
- IMX6QDL_PLL4_BYPASS_SRC
- IMX6QDL_PLL5_BYPASS
- IMX6QDL_PLL5_BYPASS_SRC
- IMX6QDL_PLL6_BYPASS
- IMX6QDL_PLL6_BYPASS_SRC
- IMX6QDL_PLL7_BYPASS
- IMX6QDL_PLL7_BYPASS_SRC
- IMX6QP
- IMX6Q_CLK_ECSPI5
- IMX6Q_CPUFREQ_CLK_NUM
- IMX6Q_FEC
- IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR
- IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR
- IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED
- IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1
- IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED
- IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK
- IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK
- IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2
- IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED
- IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK
- IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK
- IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7
- IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED
- IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK
- IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK
- IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7
- IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED
- IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK
- IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK
- IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1
- IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED
- IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK
- IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK
- IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2
- IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED
- IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK
- IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK
- IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7
- IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED
- IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK
- IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK
- IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK
- IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX
- IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1
- IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1
- IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3
- IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1
- IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2
- IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2
- IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1
- IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4
- IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1
- IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4
- IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2
- IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI
- IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3
- IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX
- IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK
- IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF
- IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1
- IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2
- IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3
- IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK
- IMX6Q_GPR10_DBG_CLK_EN
- IMX6Q_GPR10_DBG_EN
- IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0
- IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1
- IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0
- IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1
- IMX6Q_GPR10_DCIC1_MUX_CTL_MASK
- IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0
- IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1
- IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0
- IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1
- IMX6Q_GPR10_DCIC2_MUX_CTL_MASK
- IMX6Q_GPR10_LOCK_DBG_CLK_EN
- IMX6Q_GPR10_LOCK_DBG_EN
- IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK
- IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK
- IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR
- IMX6Q_GPR10_LOCK_OCRAM_TZ_EN
- IMX6Q_GPR10_LOCK_SEC_ERR_RESP
- IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK
- IMX6Q_GPR10_OCRAM_TZ_EN_MASK
- IMX6Q_GPR10_SEC_ERR_RESP_MASK
- IMX6Q_GPR10_SEC_ERR_RESP_OKEY
- IMX6Q_GPR10_SEC_ERR_RESP_SLVE
- IMX6Q_GPR12_ARMP_AHB_CLK_EN
- IMX6Q_GPR12_ARMP_APB_CLK_EN
- IMX6Q_GPR12_ARMP_ATB_CLK_EN
- IMX6Q_GPR12_ARMP_IPG_CLK_EN
- IMX6Q_GPR12_DEVICE_TYPE
- IMX6Q_GPR12_LOS_LEVEL
- IMX6Q_GPR12_PCIE_CTL_2
- IMX6Q_GPR13_CAN1_STOP_REQ
- IMX6Q_GPR13_CAN2_STOP_REQ
- IMX6Q_GPR13_ENET_STOP_REQ
- IMX6Q_GPR13_SATA_MPLL_CLK_EN
- IMX6Q_GPR13_SATA_MPLL_SS_EN
- IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F
- IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F
- IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F
- IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
- IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
- IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB
- IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
- IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
- IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X
- IMX6Q_GPR13_SATA_SPD_MODE_1P5G
- IMX6Q_GPR13_SATA_SPD_MODE_3P0G
- IMX6Q_GPR13_SATA_SPD_MODE_MASK
- IMX6Q_GPR13_SATA_TX_ATTEN_10_16
- IMX6Q_GPR13_SATA_TX_ATTEN_12_16
- IMX6Q_GPR13_SATA_TX_ATTEN_14_16
- IMX6Q_GPR13_SATA_TX_ATTEN_16_16
- IMX6Q_GPR13_SATA_TX_ATTEN_8_16
- IMX6Q_GPR13_SATA_TX_ATTEN_9_16
- IMX6Q_GPR13_SATA_TX_ATTEN_MASK
- IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB
- IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB
- IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB
- IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB
- IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB
- IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB
- IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB
- IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB
- IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB
- IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
- IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB
- IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB
- IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB
- IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB
- IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB
- IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB
- IMX6Q_GPR13_SATA_TX_BOOST_MASK
- IMX6Q_GPR13_SATA_TX_EDGE_RATE
- IMX6Q_GPR13_SATA_TX_LVL_0_937_V
- IMX6Q_GPR13_SATA_TX_LVL_0_947_V
- IMX6Q_GPR13_SATA_TX_LVL_0_957_V
- IMX6Q_GPR13_SATA_TX_LVL_0_966_V
- IMX6Q_GPR13_SATA_TX_LVL_0_976_V
- IMX6Q_GPR13_SATA_TX_LVL_0_986_V
- IMX6Q_GPR13_SATA_TX_LVL_0_996_V
- IMX6Q_GPR13_SATA_TX_LVL_1_005_V
- IMX6Q_GPR13_SATA_TX_LVL_1_015_V
- IMX6Q_GPR13_SATA_TX_LVL_1_025_V
- IMX6Q_GPR13_SATA_TX_LVL_1_035_V
- IMX6Q_GPR13_SATA_TX_LVL_1_045_V
- IMX6Q_GPR13_SATA_TX_LVL_1_054_V
- IMX6Q_GPR13_SATA_TX_LVL_1_064_V
- IMX6Q_GPR13_SATA_TX_LVL_1_074_V
- IMX6Q_GPR13_SATA_TX_LVL_1_084_V
- IMX6Q_GPR13_SATA_TX_LVL_1_094_V
- IMX6Q_GPR13_SATA_TX_LVL_1_104_V
- IMX6Q_GPR13_SATA_TX_LVL_1_113_V
- IMX6Q_GPR13_SATA_TX_LVL_1_123_V
- IMX6Q_GPR13_SATA_TX_LVL_1_133_V
- IMX6Q_GPR13_SATA_TX_LVL_1_143_V
- IMX6Q_GPR13_SATA_TX_LVL_1_152_V
- IMX6Q_GPR13_SATA_TX_LVL_1_162_V
- IMX6Q_GPR13_SATA_TX_LVL_1_172_V
- IMX6Q_GPR13_SATA_TX_LVL_1_182_V
- IMX6Q_GPR13_SATA_TX_LVL_1_191_V
- IMX6Q_GPR13_SATA_TX_LVL_1_201_V
- IMX6Q_GPR13_SATA_TX_LVL_1_211_V
- IMX6Q_GPR13_SATA_TX_LVL_1_221_V
- IMX6Q_GPR13_SATA_TX_LVL_1_230_V
- IMX6Q_GPR13_SATA_TX_LVL_1_240_V
- IMX6Q_GPR13_SATA_TX_LVL_MASK
- IMX6Q_GPR13_SDMA_STOP_REQ
- IMX6Q_GPR1_ACT_CS0
- IMX6Q_GPR1_ACT_CS1
- IMX6Q_GPR1_ACT_CS2
- IMX6Q_GPR1_ACT_CS3
- IMX6Q_GPR1_ADDRS0_MASK
- IMX6Q_GPR1_ADDRS1_MASK
- IMX6Q_GPR1_ADDRS2_MASK
- IMX6Q_GPR1_ADDRS3_128MB
- IMX6Q_GPR1_ADDRS3_32MB
- IMX6Q_GPR1_ADDRS3_64MB
- IMX6Q_GPR1_ADDRS3_MASK
- IMX6Q_GPR1_DPI_OFF
- IMX6Q_GPR1_ENET_CLK_SEL_ANATOP
- IMX6Q_GPR1_ENET_CLK_SEL_MASK
- IMX6Q_GPR1_ENET_CLK_SEL_PAD
- IMX6Q_GPR1_EXC_MON_MASK
- IMX6Q_GPR1_EXC_MON_OKAY
- IMX6Q_GPR1_EXC_MON_SLVE
- IMX6Q_GPR1_GINT
- IMX6Q_GPR1_IPU_VPU_MUX_IPU1
- IMX6Q_GPR1_IPU_VPU_MUX_IPU2
- IMX6Q_GPR1_IPU_VPU_MUX_MASK
- IMX6Q_GPR1_MIPI_COLOR_SW
- IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET
- IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX
- IMX6Q_GPR1_MIPI_IPU1_MUX_MASK
- IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET
- IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX
- IMX6Q_GPR1_MIPI_IPU2_MUX_MASK
- IMX6Q_GPR1_PCIE_ENTER_L1
- IMX6Q_GPR1_PCIE_EXIT_L1
- IMX6Q_GPR1_PCIE_INT
- IMX6Q_GPR1_PCIE_RDY_L23
- IMX6Q_GPR1_PCIE_REF_CLK_EN
- IMX6Q_GPR1_PCIE_REQ_MASK
- IMX6Q_GPR1_PCIE_SW_RST
- IMX6Q_GPR1_PCIE_TEST_PD
- IMX6Q_GPR1_USB_EXP_MODE
- IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER
- IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1
- IMX6Q_GPR1_USB_OTG_ID_SEL_MASK
- IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR
- IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR
- IMX6Q_GPR2_BGREF_RRMODE_MASK
- IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA
- IMX6Q_GPR2_BIT_MAPPING_CH0_MASK
- IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG
- IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA
- IMX6Q_GPR2_BIT_MAPPING_CH1_MASK
- IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG
- IMX6Q_GPR2_CH0_MODE_DISABLE
- IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0
- IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1
- IMX6Q_GPR2_CH0_MODE_MASK
- IMX6Q_GPR2_CH1_MODE_DISABLE
- IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0
- IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1
- IMX6Q_GPR2_CH1_MODE_MASK
- IMX6Q_GPR2_COUNTER_RESET_VAL_3
- IMX6Q_GPR2_COUNTER_RESET_VAL_4
- IMX6Q_GPR2_COUNTER_RESET_VAL_5
- IMX6Q_GPR2_COUNTER_RESET_VAL_6
- IMX6Q_GPR2_COUNTER_RESET_VAL_MASK
- IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT
- IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT
- IMX6Q_GPR2_DATA_WIDTH_CH0_MASK
- IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT
- IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT
- IMX6Q_GPR2_DATA_WIDTH_CH1_MASK
- IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H
- IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L
- IMX6Q_GPR2_DI0_VS_POLARITY_MASK
- IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H
- IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L
- IMX6Q_GPR2_DI1_VS_POLARITY_MASK
- IMX6Q_GPR2_LVDS_CLK_SHIFT_0
- IMX6Q_GPR2_LVDS_CLK_SHIFT_1
- IMX6Q_GPR2_LVDS_CLK_SHIFT_2
- IMX6Q_GPR2_LVDS_CLK_SHIFT_3
- IMX6Q_GPR2_LVDS_CLK_SHIFT_4
- IMX6Q_GPR2_LVDS_CLK_SHIFT_5
- IMX6Q_GPR2_LVDS_CLK_SHIFT_6
- IMX6Q_GPR2_LVDS_CLK_SHIFT_7
- IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK
- IMX6Q_GPR2_SPLIT_MODE_EN
- IMX6Q_GPR3_BCH_RD_CACHE_CTL
- IMX6Q_GPR3_BCH_WR_CACHE_CTL
- IMX6Q_GPR3_CORE0_DBG_ACK_EN
- IMX6Q_GPR3_CORE1_DBG_ACK_EN
- IMX6Q_GPR3_CORE2_DBG_ACK_EN
- IMX6Q_GPR3_CORE3_DBG_ACK_EN
- IMX6Q_GPR3_GPU_DBG_GPU2D
- IMX6Q_GPR3_GPU_DBG_GPU3D
- IMX6Q_GPR3_GPU_DBG_MASK
- IMX6Q_GPR3_GPU_DBG_OPENVG
- IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0
- IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1
- IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0
- IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1
- IMX6Q_GPR3_HDMI_MUX_CTL_MASK
- IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT
- IMX6Q_GPR3_IPU_DIAG_MASK
- IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0
- IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1
- IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0
- IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1
- IMX6Q_GPR3_LVDS0_MUX_CTL_MASK
- IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0
- IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1
- IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0
- IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1
- IMX6Q_GPR3_LVDS1_MUX_CTL_MASK
- IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0
- IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1
- IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0
- IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1
- IMX6Q_GPR3_MIPI_MUX_CTL_MASK
- IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT
- IMX6Q_GPR3_OCRAM_CTL_MASK
- IMX6Q_GPR3_OCRAM_STATUS_MASK
- IMX6Q_GPR3_TZASC1_BOOT_LOCK
- IMX6Q_GPR3_TZASC2_BOOT_LOCK
- IMX6Q_GPR3_USDHCX_RD_CACHE_CTL
- IMX6Q_GPR3_USDHCX_WR_CACHE_CTL
- IMX6Q_GPR4_CAN1_STOP_ACK
- IMX6Q_GPR4_CAN2_STOP_ACK
- IMX6Q_GPR4_ENET_STOP_ACK
- IMX6Q_GPR4_IPU_RD_CACHE_CTL
- IMX6Q_GPR4_IPU_WR_CACHE_CTL
- IMX6Q_GPR4_PCIE_RD_CACHE_SEL
- IMX6Q_GPR4_PCIE_RD_CACHE_VAL
- IMX6Q_GPR4_PCIE_WR_CACHE_SEL
- IMX6Q_GPR4_PCIE_WR_CACHE_VAL
- IMX6Q_GPR4_SDMA_STOP_ACK
- IMX6Q_GPR4_SOC_VERSION_MASK
- IMX6Q_GPR4_SOC_VERSION_OFF
- IMX6Q_GPR4_VDOA_RD_CACHE_SEL
- IMX6Q_GPR4_VDOA_RD_CACHE_VAL
- IMX6Q_GPR4_VDOA_WR_CACHE_SEL
- IMX6Q_GPR4_VDOA_WR_CACHE_VAL
- IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK
- IMX6Q_GPR4_VPU_P_WR_CACHE_VAL
- IMX6Q_GPR4_VPU_RD_CACHE_SEL
- IMX6Q_GPR4_VPU_WR_CACHE_SEL
- IMX6Q_GPR5_L2_CLK_STOP
- IMX6Q_GPR5_SATA_SW_PD
- IMX6Q_GPR5_SATA_SW_RST
- IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK
- IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK
- IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK
- IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK
- IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK
- IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK
- IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK
- IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK
- IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK
- IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK
- IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK
- IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK
- IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK
- IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK
- IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK
- IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK
- IMX6Q_GPR8_TX_DEEMPH_GEN1
- IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB
- IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB
- IMX6Q_GPR8_TX_SWING_FULL
- IMX6Q_GPR8_TX_SWING_LOW
- IMX6Q_GPR9_TZASC1_BYP
- IMX6Q_GPR9_TZASC2_BYP
- IMX6Q_SNVS_HPLR
- IMX6Q_SNVS_LPGPR
- IMX6Q_SNVS_LPLR
- IMX6Q_UART
- IMX6Q_UART1_BASE_ADDR
- IMX6Q_UART2_BASE_ADDR
- IMX6Q_UART3_BASE_ADDR
- IMX6Q_UART4_BASE_ADDR
- IMX6Q_UART5_BASE_ADDR
- IMX6Q_UART_BASE
- IMX6Q_UART_BASE_ADDR
- IMX6SLL_CLK_AHB
- IMX6SLL_CLK_AIPSTZ1
- IMX6SLL_CLK_AIPSTZ2
- IMX6SLL_CLK_ARM
- IMX6SLL_CLK_AXI_ALT_SEL
- IMX6SLL_CLK_AXI_PODF
- IMX6SLL_CLK_AXI_SEL
- IMX6SLL_CLK_CKIL
- IMX6SLL_CLK_CSI
- IMX6SLL_CLK_DCP
- IMX6SLL_CLK_DUMMY
- IMX6SLL_CLK_ECSPI1
- IMX6SLL_CLK_ECSPI2
- IMX6SLL_CLK_ECSPI3
- IMX6SLL_CLK_ECSPI4
- IMX6SLL_CLK_ECSPI_PODF
- IMX6SLL_CLK_ECSPI_SEL
- IMX6SLL_CLK_END
- IMX6SLL_CLK_EPDC_AXI
- IMX6SLL_CLK_EPDC_PIX
- IMX6SLL_CLK_EPDC_PODF
- IMX6SLL_CLK_EPDC_PRE_SEL
- IMX6SLL_CLK_EPDC_SEL
- IMX6SLL_CLK_EPIT1
- IMX6SLL_CLK_EPIT2
- IMX6SLL_CLK_EXTERN_AUDIO
- IMX6SLL_CLK_EXTERN_AUDIO_PODF
- IMX6SLL_CLK_EXTERN_AUDIO_PRED
- IMX6SLL_CLK_EXTERN_AUDIO_SEL
- IMX6SLL_CLK_GPIO1
- IMX6SLL_CLK_GPIO2
- IMX6SLL_CLK_GPIO3
- IMX6SLL_CLK_GPIO4
- IMX6SLL_CLK_GPIO5
- IMX6SLL_CLK_GPIO6
- IMX6SLL_CLK_GPT_BUS
- IMX6SLL_CLK_GPT_SERIAL
- IMX6SLL_CLK_I2C1
- IMX6SLL_CLK_I2C2
- IMX6SLL_CLK_I2C3
- IMX6SLL_CLK_IPG
- IMX6SLL_CLK_IPP_DI0
- IMX6SLL_CLK_IPP_DI1
- IMX6SLL_CLK_KPP
- IMX6SLL_CLK_LCDIF_APB
- IMX6SLL_CLK_LCDIF_PIX
- IMX6SLL_CLK_LCDIF_PODF
- IMX6SLL_CLK_LCDIF_PRED
- IMX6SLL_CLK_LCDIF_PRE_SEL
- IMX6SLL_CLK_LCDIF_SEL
- IMX6SLL_CLK_LDB_DI0
- IMX6SLL_CLK_LDB_DI0_DIV_3_5
- IMX6SLL_CLK_LDB_DI0_DIV_7
- IMX6SLL_CLK_LDB_DI0_DIV_SEL
- IMX6SLL_CLK_LDB_DI0_SEL
- IMX6SLL_CLK_LDB_DI1
- IMX6SLL_CLK_LDB_DI1_DIV_3_5
- IMX6SLL_CLK_LDB_DI1_DIV_7
- IMX6SLL_CLK_LDB_DI1_DIV_SEL
- IMX6SLL_CLK_LDB_DI1_SEL
- IMX6SLL_CLK_MMDC_P0_FAST
- IMX6SLL_CLK_MMDC_P0_IPG
- IMX6SLL_CLK_MMDC_P1_IPG
- IMX6SLL_CLK_MMDC_PODF
- IMX6SLL_CLK_OCOTP
- IMX6SLL_CLK_OCRAM
- IMX6SLL_CLK_OSC
- IMX6SLL_CLK_PERCLK
- IMX6SLL_CLK_PERCLK_SEL
- IMX6SLL_CLK_PERIPH
- IMX6SLL_CLK_PERIPH2
- IMX6SLL_CLK_PERIPH2_CLK2
- IMX6SLL_CLK_PERIPH2_CLK2_SEL
- IMX6SLL_CLK_PERIPH2_PRE
- IMX6SLL_CLK_PERIPH_CLK2
- IMX6SLL_CLK_PERIPH_CLK2_SEL
- IMX6SLL_CLK_PERIPH_PRE
- IMX6SLL_CLK_PLL1
- IMX6SLL_CLK_PLL1_SW
- IMX6SLL_CLK_PLL1_SYS
- IMX6SLL_CLK_PLL2
- IMX6SLL_CLK_PLL2_198M
- IMX6SLL_CLK_PLL2_BUS
- IMX6SLL_CLK_PLL2_PFD0
- IMX6SLL_CLK_PLL2_PFD1
- IMX6SLL_CLK_PLL2_PFD2
- IMX6SLL_CLK_PLL2_PFD3
- IMX6SLL_CLK_PLL3
- IMX6SLL_CLK_PLL3_120M
- IMX6SLL_CLK_PLL3_60M
- IMX6SLL_CLK_PLL3_80M
- IMX6SLL_CLK_PLL3_PFD0
- IMX6SLL_CLK_PLL3_PFD1
- IMX6SLL_CLK_PLL3_PFD2
- IMX6SLL_CLK_PLL3_PFD3
- IMX6SLL_CLK_PLL3_USB_OTG
- IMX6SLL_CLK_PLL4
- IMX6SLL_CLK_PLL4_AUDIO
- IMX6SLL_CLK_PLL4_AUDIO_DIV
- IMX6SLL_CLK_PLL4_POST_DIV
- IMX6SLL_CLK_PLL5
- IMX6SLL_CLK_PLL5_POST_DIV
- IMX6SLL_CLK_PLL5_VIDEO
- IMX6SLL_CLK_PLL5_VIDEO_DIV
- IMX6SLL_CLK_PLL6
- IMX6SLL_CLK_PLL6_ENET
- IMX6SLL_CLK_PLL7
- IMX6SLL_CLK_PLL7_USB_HOST
- IMX6SLL_CLK_PWM1
- IMX6SLL_CLK_PWM2
- IMX6SLL_CLK_PWM3
- IMX6SLL_CLK_PWM4
- IMX6SLL_CLK_PXP
- IMX6SLL_CLK_PXP_PODF
- IMX6SLL_CLK_PXP_SEL
- IMX6SLL_CLK_ROM
- IMX6SLL_CLK_SDMA
- IMX6SLL_CLK_SPBA
- IMX6SLL_CLK_SPDIF
- IMX6SLL_CLK_SPDIF_GCLK
- IMX6SLL_CLK_SPDIF_PODF
- IMX6SLL_CLK_SPDIF_PRED
- IMX6SLL_CLK_SPDIF_SEL
- IMX6SLL_CLK_SSI1
- IMX6SLL_CLK_SSI1_IPG
- IMX6SLL_CLK_SSI1_PODF
- IMX6SLL_CLK_SSI1_PRED
- IMX6SLL_CLK_SSI1_SEL
- IMX6SLL_CLK_SSI2
- IMX6SLL_CLK_SSI2_IPG
- IMX6SLL_CLK_SSI2_PODF
- IMX6SLL_CLK_SSI2_PRED
- IMX6SLL_CLK_SSI2_SEL
- IMX6SLL_CLK_SSI3
- IMX6SLL_CLK_SSI3_IPG
- IMX6SLL_CLK_SSI3_PODF
- IMX6SLL_CLK_SSI3_PRED
- IMX6SLL_CLK_SSI3_SEL
- IMX6SLL_CLK_STEP
- IMX6SLL_CLK_UART1_IPG
- IMX6SLL_CLK_UART1_SERIAL
- IMX6SLL_CLK_UART2_IPG
- IMX6SLL_CLK_UART2_SERIAL
- IMX6SLL_CLK_UART3_IPG
- IMX6SLL_CLK_UART3_SERIAL
- IMX6SLL_CLK_UART4_IPG
- IMX6SLL_CLK_UART4_SERIAL
- IMX6SLL_CLK_UART5_IPG
- IMX6SLL_CLK_UART5_SERIAL
- IMX6SLL_CLK_UART_PODF
- IMX6SLL_CLK_UART_SEL
- IMX6SLL_CLK_USBOH3
- IMX6SLL_CLK_USBPHY1
- IMX6SLL_CLK_USBPHY1_GATE
- IMX6SLL_CLK_USBPHY2
- IMX6SLL_CLK_USBPHY2_GATE
- IMX6SLL_CLK_USDHC1
- IMX6SLL_CLK_USDHC1_PODF
- IMX6SLL_CLK_USDHC1_SEL
- IMX6SLL_CLK_USDHC2
- IMX6SLL_CLK_USDHC2_PODF
- IMX6SLL_CLK_USDHC2_SEL
- IMX6SLL_CLK_USDHC3
- IMX6SLL_CLK_USDHC3_PODF
- IMX6SLL_CLK_USDHC3_SEL
- IMX6SLL_CLK_WDOG1
- IMX6SLL_CLK_WDOG2
- IMX6SLL_GPR5_AFCG_X_BYPASS_MASK
- IMX6SLL_PLL1_BYPASS
- IMX6SLL_PLL1_BYPASS_SRC
- IMX6SLL_PLL2_BYPASS
- IMX6SLL_PLL2_BYPASS_SRC
- IMX6SLL_PLL3_BYPASS
- IMX6SLL_PLL3_BYPASS_SRC
- IMX6SLL_PLL4_BYPASS
- IMX6SLL_PLL4_BYPASS_SRC
- IMX6SLL_PLL5_BYPASS
- IMX6SLL_PLL5_BYPASS_SRC
- IMX6SLL_PLL6_BYPASS
- IMX6SLL_PLL6_BYPASS_SRC
- IMX6SLL_PLL7_BYPASS
- IMX6SLL_PLL7_BYPASS_SRC
- IMX6SL_CLK_AHB
- IMX6SL_CLK_ANACLK1
- IMX6SL_CLK_ARM
- IMX6SL_CLK_CKIL
- IMX6SL_CLK_CSI
- IMX6SL_CLK_CSI_PODF
- IMX6SL_CLK_CSI_SEL
- IMX6SL_CLK_DUMMY
- IMX6SL_CLK_ECSPI1
- IMX6SL_CLK_ECSPI2
- IMX6SL_CLK_ECSPI3
- IMX6SL_CLK_ECSPI4
- IMX6SL_CLK_ECSPI_ROOT
- IMX6SL_CLK_ECSPI_SEL
- IMX6SL_CLK_END
- IMX6SL_CLK_ENET
- IMX6SL_CLK_ENET_REF
- IMX6SL_CLK_EPDC_AXI
- IMX6SL_CLK_EPDC_AXI_PODF
- IMX6SL_CLK_EPDC_AXI_SEL
- IMX6SL_CLK_EPDC_PIX
- IMX6SL_CLK_EPDC_PIX_PODF
- IMX6SL_CLK_EPDC_PIX_PRED
- IMX6SL_CLK_EPDC_PIX_SEL
- IMX6SL_CLK_EPIT1
- IMX6SL_CLK_EPIT2
- IMX6SL_CLK_EXTERN_AUDIO
- IMX6SL_CLK_EXTERN_AUDIO_PODF
- IMX6SL_CLK_EXTERN_AUDIO_PRED
- IMX6SL_CLK_EXTERN_AUDIO_SEL
- IMX6SL_CLK_GPT
- IMX6SL_CLK_GPT_SERIAL
- IMX6SL_CLK_GPU2D_OVG
- IMX6SL_CLK_GPU2D_OVG_PODF
- IMX6SL_CLK_GPU2D_OVG_SEL
- IMX6SL_CLK_GPU2D_PODF
- IMX6SL_CLK_GPU2D_SEL
- IMX6SL_CLK_I2C1
- IMX6SL_CLK_I2C2
- IMX6SL_CLK_I2C3
- IMX6SL_CLK_IPG
- IMX6SL_CLK_LCDIF_AXI
- IMX6SL_CLK_LCDIF_AXI_PODF
- IMX6SL_CLK_LCDIF_AXI_SEL
- IMX6SL_CLK_LCDIF_PIX
- IMX6SL_CLK_LCDIF_PIX_PODF
- IMX6SL_CLK_LCDIF_PIX_PRED
- IMX6SL_CLK_LCDIF_PIX_SEL
- IMX6SL_CLK_LVDS1_IN
- IMX6SL_CLK_LVDS1_OUT
- IMX6SL_CLK_LVDS1_SEL
- IMX6SL_CLK_MMDC_P0_IPG
- IMX6SL_CLK_MMDC_P1_IPG
- IMX6SL_CLK_MMDC_ROOT
- IMX6SL_CLK_OCOTP
- IMX6SL_CLK_OCRAM
- IMX6SL_CLK_OCRAM_ALT_SEL
- IMX6SL_CLK_OCRAM_PODF
- IMX6SL_CLK_OCRAM_SEL
- IMX6SL_CLK_OSC
- IMX6SL_CLK_PERCLK
- IMX6SL_CLK_PERCLK_SEL
- IMX6SL_CLK_PERIPH
- IMX6SL_CLK_PERIPH2
- IMX6SL_CLK_PERIPH2_CLK2_PODF
- IMX6SL_CLK_PERIPH2_CLK2_SEL
- IMX6SL_CLK_PERIPH_CLK2_PODF
- IMX6SL_CLK_PERIPH_CLK2_SEL
- IMX6SL_CLK_PLL1
- IMX6SL_CLK_PLL1_SW
- IMX6SL_CLK_PLL1_SYS
- IMX6SL_CLK_PLL2
- IMX6SL_CLK_PLL2_198M
- IMX6SL_CLK_PLL2_BUS
- IMX6SL_CLK_PLL2_PFD0
- IMX6SL_CLK_PLL2_PFD1
- IMX6SL_CLK_PLL2_PFD2
- IMX6SL_CLK_PLL3
- IMX6SL_CLK_PLL3_120M
- IMX6SL_CLK_PLL3_60M
- IMX6SL_CLK_PLL3_80M
- IMX6SL_CLK_PLL3_PFD0
- IMX6SL_CLK_PLL3_PFD1
- IMX6SL_CLK_PLL3_PFD2
- IMX6SL_CLK_PLL3_PFD3
- IMX6SL_CLK_PLL3_USB_OTG
- IMX6SL_CLK_PLL4
- IMX6SL_CLK_PLL4_AUDIO
- IMX6SL_CLK_PLL4_AUDIO_DIV
- IMX6SL_CLK_PLL4_POST_DIV
- IMX6SL_CLK_PLL5
- IMX6SL_CLK_PLL5_POST_DIV
- IMX6SL_CLK_PLL5_VIDEO
- IMX6SL_CLK_PLL5_VIDEO_DIV
- IMX6SL_CLK_PLL6
- IMX6SL_CLK_PLL6_ENET
- IMX6SL_CLK_PLL7
- IMX6SL_CLK_PLL7_USB_HOST
- IMX6SL_CLK_PRE_PERIPH2_SEL
- IMX6SL_CLK_PRE_PERIPH_SEL
- IMX6SL_CLK_PWM1
- IMX6SL_CLK_PWM2
- IMX6SL_CLK_PWM3
- IMX6SL_CLK_PWM4
- IMX6SL_CLK_PXP_AXI
- IMX6SL_CLK_PXP_AXI_PODF
- IMX6SL_CLK_PXP_AXI_SEL
- IMX6SL_CLK_SDMA
- IMX6SL_CLK_SPBA
- IMX6SL_CLK_SPDIF
- IMX6SL_CLK_SPDIF0_PODF
- IMX6SL_CLK_SPDIF0_PRED
- IMX6SL_CLK_SPDIF0_SEL
- IMX6SL_CLK_SPDIF1_PODF
- IMX6SL_CLK_SPDIF1_PRED
- IMX6SL_CLK_SPDIF1_SEL
- IMX6SL_CLK_SPDIF_GCLK
- IMX6SL_CLK_SSI1
- IMX6SL_CLK_SSI1_IPG
- IMX6SL_CLK_SSI1_PODF
- IMX6SL_CLK_SSI1_PRED
- IMX6SL_CLK_SSI1_SEL
- IMX6SL_CLK_SSI2
- IMX6SL_CLK_SSI2_IPG
- IMX6SL_CLK_SSI2_PODF
- IMX6SL_CLK_SSI2_PRED
- IMX6SL_CLK_SSI2_SEL
- IMX6SL_CLK_SSI3
- IMX6SL_CLK_SSI3_IPG
- IMX6SL_CLK_SSI3_PODF
- IMX6SL_CLK_SSI3_PRED
- IMX6SL_CLK_SSI3_SEL
- IMX6SL_CLK_STEP
- IMX6SL_CLK_UART
- IMX6SL_CLK_UART_ROOT
- IMX6SL_CLK_UART_SEL
- IMX6SL_CLK_UART_SERIAL
- IMX6SL_CLK_USBOH3
- IMX6SL_CLK_USBPHY1
- IMX6SL_CLK_USBPHY1_GATE
- IMX6SL_CLK_USBPHY2
- IMX6SL_CLK_USBPHY2_GATE
- IMX6SL_CLK_USDHC1
- IMX6SL_CLK_USDHC1_PODF
- IMX6SL_CLK_USDHC1_SEL
- IMX6SL_CLK_USDHC2
- IMX6SL_CLK_USDHC2_PODF
- IMX6SL_CLK_USDHC2_SEL
- IMX6SL_CLK_USDHC3
- IMX6SL_CLK_USDHC3_PODF
- IMX6SL_CLK_USDHC3_SEL
- IMX6SL_CLK_USDHC4
- IMX6SL_CLK_USDHC4_PODF
- IMX6SL_CLK_USDHC4_SEL
- IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK
- IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK
- IMX6SL_PLL1_BYPASS
- IMX6SL_PLL1_BYPASS_SRC
- IMX6SL_PLL2_BYPASS
- IMX6SL_PLL2_BYPASS_SRC
- IMX6SL_PLL3_BYPASS
- IMX6SL_PLL3_BYPASS_SRC
- IMX6SL_PLL4_BYPASS
- IMX6SL_PLL4_BYPASS_SRC
- IMX6SL_PLL5_BYPASS
- IMX6SL_PLL5_BYPASS_SRC
- IMX6SL_PLL6_BYPASS
- IMX6SL_PLL6_BYPASS_SRC
- IMX6SL_PLL7_BYPASS
- IMX6SL_PLL7_BYPASS_SRC
- IMX6SL_UART1_BASE_ADDR
- IMX6SL_UART2_BASE_ADDR
- IMX6SL_UART3_BASE_ADDR
- IMX6SL_UART4_BASE_ADDR
- IMX6SL_UART5_BASE_ADDR
- IMX6SL_UART_BASE
- IMX6SL_UART_BASE_ADDR
- IMX6SX
- IMX6SX_CLK_AHB
- IMX6SX_CLK_AIPS_TZ1
- IMX6SX_CLK_AIPS_TZ2
- IMX6SX_CLK_AIPS_TZ3
- IMX6SX_CLK_ANACLK1
- IMX6SX_CLK_ANACLK2
- IMX6SX_CLK_APBH_DMA
- IMX6SX_CLK_ARM
- IMX6SX_CLK_ASRC_GATE
- IMX6SX_CLK_ASRC_IPG
- IMX6SX_CLK_ASRC_MEM
- IMX6SX_CLK_AUDIO
- IMX6SX_CLK_AUDIO_PODF
- IMX6SX_CLK_AUDIO_PRED
- IMX6SX_CLK_AUDIO_SEL
- IMX6SX_CLK_AXI
- IMX6SX_CLK_CAAM_ACLK
- IMX6SX_CLK_CAAM_IPG
- IMX6SX_CLK_CAAM_MEM
- IMX6SX_CLK_CAN1_IPG
- IMX6SX_CLK_CAN1_SERIAL
- IMX6SX_CLK_CAN2_IPG
- IMX6SX_CLK_CAN2_SERIAL
- IMX6SX_CLK_CANFD
- IMX6SX_CLK_CAN_PODF
- IMX6SX_CLK_CAN_SEL
- IMX6SX_CLK_CKIH
- IMX6SX_CLK_CKIL
- IMX6SX_CLK_CKO
- IMX6SX_CLK_CKO1
- IMX6SX_CLK_CKO1_PODF
- IMX6SX_CLK_CKO1_SEL
- IMX6SX_CLK_CKO2
- IMX6SX_CLK_CKO2_PODF
- IMX6SX_CLK_CKO2_SEL
- IMX6SX_CLK_CLK_END
- IMX6SX_CLK_CPU_DEBUG
- IMX6SX_CLK_CSI
- IMX6SX_CLK_CSI_PODF
- IMX6SX_CLK_CSI_SEL
- IMX6SX_CLK_DCIC1
- IMX6SX_CLK_DCIC2
- IMX6SX_CLK_DISPLAY_AXI
- IMX6SX_CLK_DISPLAY_PODF
- IMX6SX_CLK_DISPLAY_SEL
- IMX6SX_CLK_DUMMY
- IMX6SX_CLK_ECSPI1
- IMX6SX_CLK_ECSPI2
- IMX6SX_CLK_ECSPI3
- IMX6SX_CLK_ECSPI4
- IMX6SX_CLK_ECSPI5
- IMX6SX_CLK_ECSPI_PODF
- IMX6SX_CLK_ECSPI_SEL
- IMX6SX_CLK_EIM_SLOW
- IMX6SX_CLK_EIM_SLOW_PODF
- IMX6SX_CLK_EIM_SLOW_SEL
- IMX6SX_CLK_ENET
- IMX6SX_CLK_ENET2_REF
- IMX6SX_CLK_ENET2_REF_125M
- IMX6SX_CLK_ENET_AHB
- IMX6SX_CLK_ENET_PODF
- IMX6SX_CLK_ENET_PRE_SEL
- IMX6SX_CLK_ENET_PTP
- IMX6SX_CLK_ENET_PTP_REF
- IMX6SX_CLK_ENET_REF
- IMX6SX_CLK_ENET_SEL
- IMX6SX_CLK_EPIT1
- IMX6SX_CLK_EPIT2
- IMX6SX_CLK_ESAI_EXTAL
- IMX6SX_CLK_ESAI_IPG
- IMX6SX_CLK_ESAI_MEM
- IMX6SX_CLK_ESAI_PODF
- IMX6SX_CLK_ESAI_PRED
- IMX6SX_CLK_ESAI_SEL
- IMX6SX_CLK_GIS
- IMX6SX_CLK_GPMI_APB
- IMX6SX_CLK_GPMI_BCH
- IMX6SX_CLK_GPMI_BCH_APB
- IMX6SX_CLK_GPMI_IO
- IMX6SX_CLK_GPT_3M
- IMX6SX_CLK_GPT_BUS
- IMX6SX_CLK_GPT_SERIAL
- IMX6SX_CLK_GPU
- IMX6SX_CLK_GPU_AXI_PODF
- IMX6SX_CLK_GPU_AXI_SEL
- IMX6SX_CLK_GPU_CORE_PODF
- IMX6SX_CLK_GPU_CORE_SEL
- IMX6SX_CLK_I2C1
- IMX6SX_CLK_I2C2
- IMX6SX_CLK_I2C3
- IMX6SX_CLK_I2C4
- IMX6SX_CLK_IOMUXC
- IMX6SX_CLK_IPG
- IMX6SX_CLK_IPMUX1
- IMX6SX_CLK_IPMUX2
- IMX6SX_CLK_IPMUX3
- IMX6SX_CLK_IPP_DI0
- IMX6SX_CLK_IPP_DI1
- IMX6SX_CLK_LCDIF1_PIX
- IMX6SX_CLK_LCDIF1_PODF
- IMX6SX_CLK_LCDIF1_PRED
- IMX6SX_CLK_LCDIF1_PRE_SEL
- IMX6SX_CLK_LCDIF1_SEL
- IMX6SX_CLK_LCDIF2_PIX
- IMX6SX_CLK_LCDIF2_PODF
- IMX6SX_CLK_LCDIF2_PRED
- IMX6SX_CLK_LCDIF2_PRE_SEL
- IMX6SX_CLK_LCDIF2_SEL
- IMX6SX_CLK_LCDIF_APB
- IMX6SX_CLK_LDB_DI0
- IMX6SX_CLK_LDB_DI0_DIV_3_5
- IMX6SX_CLK_LDB_DI0_DIV_7
- IMX6SX_CLK_LDB_DI0_DIV_SEL
- IMX6SX_CLK_LDB_DI0_SEL
- IMX6SX_CLK_LDB_DI1_DIV_3_5
- IMX6SX_CLK_LDB_DI1_DIV_7
- IMX6SX_CLK_LDB_DI1_DIV_SEL
- IMX6SX_CLK_LDB_DI1_SEL
- IMX6SX_CLK_LVDS1_IN
- IMX6SX_CLK_LVDS1_OUT
- IMX6SX_CLK_LVDS1_SEL
- IMX6SX_CLK_LVDS2_IN
- IMX6SX_CLK_LVDS2_OUT
- IMX6SX_CLK_LVDS2_SEL
- IMX6SX_CLK_M4
- IMX6SX_CLK_M4_PODF
- IMX6SX_CLK_M4_PRE_SEL
- IMX6SX_CLK_M4_SEL
- IMX6SX_CLK_MLB
- IMX6SX_CLK_MMDC_P0_FAST
- IMX6SX_CLK_MMDC_P0_IPG
- IMX6SX_CLK_MMDC_P1_IPG
- IMX6SX_CLK_MMDC_PODF
- IMX6SX_CLK_OCOTP
- IMX6SX_CLK_OCRAM
- IMX6SX_CLK_OCRAM_PODF
- IMX6SX_CLK_OCRAM_S
- IMX6SX_CLK_OCRAM_SEL
- IMX6SX_CLK_OSC
- IMX6SX_CLK_PCIE_AXI
- IMX6SX_CLK_PCIE_AXI_SEL
- IMX6SX_CLK_PCIE_REF
- IMX6SX_CLK_PCIE_REF_125M
- IMX6SX_CLK_PER1_BCH
- IMX6SX_CLK_PER2_MAIN
- IMX6SX_CLK_PERCLK
- IMX6SX_CLK_PERCLK_SEL
- IMX6SX_CLK_PERIPH
- IMX6SX_CLK_PERIPH2
- IMX6SX_CLK_PERIPH2_CLK2
- IMX6SX_CLK_PERIPH2_CLK2_SEL
- IMX6SX_CLK_PERIPH2_PRE
- IMX6SX_CLK_PERIPH_CLK2
- IMX6SX_CLK_PERIPH_CLK2_SEL
- IMX6SX_CLK_PERIPH_PRE
- IMX6SX_CLK_PLL1
- IMX6SX_CLK_PLL1_SW
- IMX6SX_CLK_PLL1_SYS
- IMX6SX_CLK_PLL2
- IMX6SX_CLK_PLL2_198M
- IMX6SX_CLK_PLL2_BUS
- IMX6SX_CLK_PLL2_PFD0
- IMX6SX_CLK_PLL2_PFD1
- IMX6SX_CLK_PLL2_PFD2
- IMX6SX_CLK_PLL2_PFD3
- IMX6SX_CLK_PLL3
- IMX6SX_CLK_PLL3_120M
- IMX6SX_CLK_PLL3_60M
- IMX6SX_CLK_PLL3_80M
- IMX6SX_CLK_PLL3_PFD0
- IMX6SX_CLK_PLL3_PFD1
- IMX6SX_CLK_PLL3_PFD2
- IMX6SX_CLK_PLL3_PFD3
- IMX6SX_CLK_PLL3_USB_OTG
- IMX6SX_CLK_PLL4
- IMX6SX_CLK_PLL4_AUDIO
- IMX6SX_CLK_PLL4_AUDIO_DIV
- IMX6SX_CLK_PLL4_POST_DIV
- IMX6SX_CLK_PLL5
- IMX6SX_CLK_PLL5_POST_DIV
- IMX6SX_CLK_PLL5_VIDEO
- IMX6SX_CLK_PLL5_VIDEO_DIV
- IMX6SX_CLK_PLL6
- IMX6SX_CLK_PLL6_ENET
- IMX6SX_CLK_PLL7
- IMX6SX_CLK_PLL7_USB_HOST
- IMX6SX_CLK_PWM1
- IMX6SX_CLK_PWM2
- IMX6SX_CLK_PWM3
- IMX6SX_CLK_PWM4
- IMX6SX_CLK_PWM5
- IMX6SX_CLK_PWM6
- IMX6SX_CLK_PWM7
- IMX6SX_CLK_PWM8
- IMX6SX_CLK_PXP_AXI
- IMX6SX_CLK_QSPI1
- IMX6SX_CLK_QSPI1_PODF
- IMX6SX_CLK_QSPI1_SEL
- IMX6SX_CLK_QSPI2
- IMX6SX_CLK_QSPI2_PODF
- IMX6SX_CLK_QSPI2_PRED
- IMX6SX_CLK_QSPI2_SEL
- IMX6SX_CLK_ROM
- IMX6SX_CLK_SAI1
- IMX6SX_CLK_SAI1_IPG
- IMX6SX_CLK_SAI2
- IMX6SX_CLK_SAI2_IPG
- IMX6SX_CLK_SDMA
- IMX6SX_CLK_SPBA
- IMX6SX_CLK_SPDIF
- IMX6SX_CLK_SPDIF_GCLK
- IMX6SX_CLK_SPDIF_PODF
- IMX6SX_CLK_SPDIF_PRED
- IMX6SX_CLK_SPDIF_SEL
- IMX6SX_CLK_SSI1
- IMX6SX_CLK_SSI1_IPG
- IMX6SX_CLK_SSI1_PODF
- IMX6SX_CLK_SSI1_PRED
- IMX6SX_CLK_SSI1_SEL
- IMX6SX_CLK_SSI2
- IMX6SX_CLK_SSI2_IPG
- IMX6SX_CLK_SSI2_PODF
- IMX6SX_CLK_SSI2_PRED
- IMX6SX_CLK_SSI2_SEL
- IMX6SX_CLK_SSI3
- IMX6SX_CLK_SSI3_IPG
- IMX6SX_CLK_SSI3_PODF
- IMX6SX_CLK_SSI3_PRED
- IMX6SX_CLK_SSI3_SEL
- IMX6SX_CLK_STEP
- IMX6SX_CLK_TWD
- IMX6SX_CLK_TZASC1
- IMX6SX_CLK_UART_IPG
- IMX6SX_CLK_UART_PODF
- IMX6SX_CLK_UART_SEL
- IMX6SX_CLK_UART_SERIAL
- IMX6SX_CLK_USBOH3
- IMX6SX_CLK_USBPHY1
- IMX6SX_CLK_USBPHY1_GATE
- IMX6SX_CLK_USBPHY2
- IMX6SX_CLK_USBPHY2_GATE
- IMX6SX_CLK_USDHC1
- IMX6SX_CLK_USDHC1_PODF
- IMX6SX_CLK_USDHC1_SEL
- IMX6SX_CLK_USDHC2
- IMX6SX_CLK_USDHC2_PODF
- IMX6SX_CLK_USDHC2_SEL
- IMX6SX_CLK_USDHC3
- IMX6SX_CLK_USDHC3_PODF
- IMX6SX_CLK_USDHC3_SEL
- IMX6SX_CLK_USDHC4
- IMX6SX_CLK_USDHC4_PODF
- IMX6SX_CLK_USDHC4_SEL
- IMX6SX_CLK_VADC
- IMX6SX_CLK_VID_PODF
- IMX6SX_CLK_VID_SEL
- IMX6SX_CLK_WAKEUP
- IMX6SX_ENABLE_M4
- IMX6SX_FEC
- IMX6SX_GPR12_PCIE_PM_TURN_OFF
- IMX6SX_GPR12_PCIE_RX_EQ_2
- IMX6SX_GPR12_PCIE_RX_EQ_MASK
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN
- IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT
- IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK
- IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK
- IMX6SX_GPR1_VADC_SW_RST_MASK
- IMX6SX_GPR1_VADC_SW_RST_RELEASE
- IMX6SX_GPR1_VADC_SW_RST_RESET
- IMX6SX_GPR1_VDEC_SW_RST_MASK
- IMX6SX_GPR1_VDEC_SW_RST_RELEASE
- IMX6SX_GPR1_VDEC_SW_RST_RESET
- IMX6SX_GPR2_MQS_CLK_DIV_MASK
- IMX6SX_GPR2_MQS_CLK_DIV_SHIFT
- IMX6SX_GPR2_MQS_EN_MASK
- IMX6SX_GPR2_MQS_EN_SHIFT
- IMX6SX_GPR2_MQS_OVERSAMPLE_MASK
- IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT
- IMX6SX_GPR2_MQS_SW_RST_MASK
- IMX6SX_GPR2_MQS_SW_RST_SHIFT
- IMX6SX_GPR4_FEC_ENET1_STOP_REQ
- IMX6SX_GPR4_FEC_ENET2_STOP_REQ
- IMX6SX_GPR5_CSI1_MUX_CTRL_CVD
- IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN
- IMX6SX_GPR5_CSI1_MUX_CTRL_GND
- IMX6SX_GPR5_CSI1_MUX_CTRL_MASK
- IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI
- IMX6SX_GPR5_CSI2_MUX_CTRL_CVD
- IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN
- IMX6SX_GPR5_CSI2_MUX_CTRL_GND
- IMX6SX_GPR5_CSI2_MUX_CTRL_MASK
- IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI
- IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1
- IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS
- IMX6SX_GPR5_DISP_MUX_DCIC1_MASK
- IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2
- IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS
- IMX6SX_GPR5_DISP_MUX_DCIC2_MASK
- IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1
- IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2
- IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK
- IMX6SX_GPR5_PCIE_BTNRST_RESET
- IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE
- IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE
- IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK
- IMX6SX_M4_RST_MASK
- IMX6SX_M4_START
- IMX6SX_M4_STOP
- IMX6SX_PLL1_BYPASS
- IMX6SX_PLL1_BYPASS_SRC
- IMX6SX_PLL2_BYPASS
- IMX6SX_PLL2_BYPASS_SRC
- IMX6SX_PLL3_BYPASS
- IMX6SX_PLL3_BYPASS_SRC
- IMX6SX_PLL4_BYPASS
- IMX6SX_PLL4_BYPASS_SRC
- IMX6SX_PLL5_BYPASS
- IMX6SX_PLL5_BYPASS_SRC
- IMX6SX_PLL6_BYPASS
- IMX6SX_PLL6_BYPASS_SRC
- IMX6SX_PLL7_BYPASS
- IMX6SX_PLL7_BYPASS_SRC
- IMX6SX_SRC_SCR
- IMX6SX_SW_M4C_NON_SCLR_RST
- IMX6SX_SW_M4C_RST
- IMX6SX_SW_M4P_RST
- IMX6SX_UART1_BASE_ADDR
- IMX6SX_UART2_BASE_ADDR
- IMX6SX_UART3_BASE_ADDR
- IMX6SX_UART4_BASE_ADDR
- IMX6SX_UART5_BASE_ADDR
- IMX6SX_UART6_BASE_ADDR
- IMX6SX_UART_BASE
- IMX6SX_UART_BASE_ADDR
- IMX6ULL_CLK_DCP_CLK
- IMX6ULL_CLK_EPDC_ACLK
- IMX6ULL_CLK_EPDC_PIX
- IMX6ULL_CLK_EPDC_PODF
- IMX6ULL_CLK_EPDC_PRE_SEL
- IMX6ULL_CLK_EPDC_SEL
- IMX6ULL_CLK_ESAI_EXTAL
- IMX6ULL_CLK_ESAI_IPG
- IMX6ULL_CLK_ESAI_MEM
- IMX6ULL_CLK_ESAI_PODF
- IMX6ULL_CLK_ESAI_PRED
- IMX6ULL_CLK_ESAI_SEL
- IMX6UL_CA7_SECONDARY_SEL
- IMX6UL_CLK_ADC1
- IMX6UL_CLK_ADC2
- IMX6UL_CLK_AHB
- IMX6UL_CLK_AIPSTZ1
- IMX6UL_CLK_AIPSTZ2
- IMX6UL_CLK_AIPSTZ3
- IMX6UL_CLK_APBHDMA
- IMX6UL_CLK_ARM
- IMX6UL_CLK_ASRC_IPG
- IMX6UL_CLK_ASRC_MEM
- IMX6UL_CLK_AXI
- IMX6UL_CLK_AXI_ALT_SEL
- IMX6UL_CLK_AXI_PODF
- IMX6UL_CLK_AXI_SEL
- IMX6UL_CLK_BCH_PODF
- IMX6UL_CLK_BCH_SEL
- IMX6UL_CLK_CAAM_ACLK
- IMX6UL_CLK_CAAM_IPG
- IMX6UL_CLK_CAAM_MEM
- IMX6UL_CLK_CAN1_IPG
- IMX6UL_CLK_CAN1_SERIAL
- IMX6UL_CLK_CAN2_IPG
- IMX6UL_CLK_CAN2_SERIAL
- IMX6UL_CLK_CAN_PODF
- IMX6UL_CLK_CAN_SEL
- IMX6UL_CLK_CKIH
- IMX6UL_CLK_CKIL
- IMX6UL_CLK_CKO
- IMX6UL_CLK_CKO1
- IMX6UL_CLK_CKO1_PODF
- IMX6UL_CLK_CKO1_SEL
- IMX6UL_CLK_CKO2
- IMX6UL_CLK_CKO2_PODF
- IMX6UL_CLK_CKO2_SEL
- IMX6UL_CLK_CSI
- IMX6UL_CLK_CSI_PODF
- IMX6UL_CLK_CSI_SEL
- IMX6UL_CLK_DUMMY
- IMX6UL_CLK_ECSPI1
- IMX6UL_CLK_ECSPI2
- IMX6UL_CLK_ECSPI3
- IMX6UL_CLK_ECSPI4
- IMX6UL_CLK_ECSPI_PODF
- IMX6UL_CLK_ECSPI_SEL
- IMX6UL_CLK_EIM
- IMX6UL_CLK_EIM_SLOW_PODF
- IMX6UL_CLK_EIM_SLOW_SEL
- IMX6UL_CLK_END
- IMX6UL_CLK_ENET
- IMX6UL_CLK_ENET2_REF
- IMX6UL_CLK_ENET2_REF_125M
- IMX6UL_CLK_ENET_AHB
- IMX6UL_CLK_ENET_PTP
- IMX6UL_CLK_ENET_PTP_REF
- IMX6UL_CLK_ENET_REF
- IMX6UL_CLK_ENFC_PODF
- IMX6UL_CLK_ENFC_PRED
- IMX6UL_CLK_ENFC_SEL
- IMX6UL_CLK_EPIT1
- IMX6UL_CLK_EPIT2
- IMX6UL_CLK_GPIO1
- IMX6UL_CLK_GPIO2
- IMX6UL_CLK_GPIO3
- IMX6UL_CLK_GPIO4
- IMX6UL_CLK_GPIO5
- IMX6UL_CLK_GPMI_APB
- IMX6UL_CLK_GPMI_BCH
- IMX6UL_CLK_GPMI_BCH_APB
- IMX6UL_CLK_GPMI_IO
- IMX6UL_CLK_GPMI_PODF
- IMX6UL_CLK_GPMI_SEL
- IMX6UL_CLK_GPT1_BUS
- IMX6UL_CLK_GPT1_SERIAL
- IMX6UL_CLK_GPT2_BUS
- IMX6UL_CLK_GPT2_SERIAL
- IMX6UL_CLK_GPT_3M
- IMX6UL_CLK_I2C1
- IMX6UL_CLK_I2C2
- IMX6UL_CLK_I2C3
- IMX6UL_CLK_I2C4
- IMX6UL_CLK_IOMUXC
- IMX6UL_CLK_IPG
- IMX6UL_CLK_IPP_DI0
- IMX6UL_CLK_IPP_DI1
- IMX6UL_CLK_KPP
- IMX6UL_CLK_LCDIF_APB
- IMX6UL_CLK_LCDIF_PIX
- IMX6UL_CLK_LCDIF_PODF
- IMX6UL_CLK_LCDIF_PRED
- IMX6UL_CLK_LCDIF_PRE_SEL
- IMX6UL_CLK_LCDIF_SEL
- IMX6UL_CLK_LDB_DI0
- IMX6UL_CLK_LDB_DI0_DIV_3_5
- IMX6UL_CLK_LDB_DI0_DIV_7
- IMX6UL_CLK_LDB_DI0_DIV_SEL
- IMX6UL_CLK_LDB_DI0_SEL
- IMX6UL_CLK_LDB_DI1_DIV_3_5
- IMX6UL_CLK_LDB_DI1_DIV_7
- IMX6UL_CLK_LDB_DI1_DIV_SEL
- IMX6UL_CLK_LDB_DI1_SEL
- IMX6UL_CLK_MMDC_P0_FAST
- IMX6UL_CLK_MMDC_P0_IPG
- IMX6UL_CLK_MMDC_P1_IPG
- IMX6UL_CLK_MMDC_PODF
- IMX6UL_CLK_OCOTP
- IMX6UL_CLK_OCRAM
- IMX6UL_CLK_OSC
- IMX6UL_CLK_PERCLK
- IMX6UL_CLK_PERCLK_SEL
- IMX6UL_CLK_PERIPH
- IMX6UL_CLK_PERIPH2
- IMX6UL_CLK_PERIPH2_CLK2
- IMX6UL_CLK_PERIPH2_CLK2_SEL
- IMX6UL_CLK_PERIPH2_PRE
- IMX6UL_CLK_PERIPH_CLK2
- IMX6UL_CLK_PERIPH_CLK2_SEL
- IMX6UL_CLK_PERIPH_PRE
- IMX6UL_CLK_PER_BCH
- IMX6UL_CLK_PLL1
- IMX6UL_CLK_PLL1_SW
- IMX6UL_CLK_PLL1_SYS
- IMX6UL_CLK_PLL2
- IMX6UL_CLK_PLL2_198M
- IMX6UL_CLK_PLL2_BUS
- IMX6UL_CLK_PLL2_PFD0
- IMX6UL_CLK_PLL2_PFD1
- IMX6UL_CLK_PLL2_PFD2
- IMX6UL_CLK_PLL2_PFD3
- IMX6UL_CLK_PLL3
- IMX6UL_CLK_PLL3_120M
- IMX6UL_CLK_PLL3_60M
- IMX6UL_CLK_PLL3_80M
- IMX6UL_CLK_PLL3_PFD0
- IMX6UL_CLK_PLL3_PFD1
- IMX6UL_CLK_PLL3_PFD2
- IMX6UL_CLK_PLL3_PFD3
- IMX6UL_CLK_PLL3_USB_OTG
- IMX6UL_CLK_PLL4
- IMX6UL_CLK_PLL4_AUDIO
- IMX6UL_CLK_PLL4_AUDIO_DIV
- IMX6UL_CLK_PLL4_POST_DIV
- IMX6UL_CLK_PLL5
- IMX6UL_CLK_PLL5_POST_DIV
- IMX6UL_CLK_PLL5_VIDEO
- IMX6UL_CLK_PLL5_VIDEO_DIV
- IMX6UL_CLK_PLL6
- IMX6UL_CLK_PLL6_ENET
- IMX6UL_CLK_PLL7
- IMX6UL_CLK_PLL7_USB_HOST
- IMX6UL_CLK_PWM1
- IMX6UL_CLK_PWM2
- IMX6UL_CLK_PWM3
- IMX6UL_CLK_PWM4
- IMX6UL_CLK_PWM5
- IMX6UL_CLK_PWM6
- IMX6UL_CLK_PWM7
- IMX6UL_CLK_PWM8
- IMX6UL_CLK_PXP
- IMX6UL_CLK_QSPI
- IMX6UL_CLK_QSPI1_PDOF
- IMX6UL_CLK_QSPI1_SEL
- IMX6UL_CLK_ROM
- IMX6UL_CLK_SAI1
- IMX6UL_CLK_SAI1_IPG
- IMX6UL_CLK_SAI1_PODF
- IMX6UL_CLK_SAI1_PRED
- IMX6UL_CLK_SAI1_SEL
- IMX6UL_CLK_SAI2
- IMX6UL_CLK_SAI2_IPG
- IMX6UL_CLK_SAI2_PODF
- IMX6UL_CLK_SAI2_PRED
- IMX6UL_CLK_SAI2_SEL
- IMX6UL_CLK_SAI3
- IMX6UL_CLK_SAI3_IPG
- IMX6UL_CLK_SAI3_PODF
- IMX6UL_CLK_SAI3_PRED
- IMX6UL_CLK_SAI3_SEL
- IMX6UL_CLK_SDMA
- IMX6UL_CLK_SIM
- IMX6UL_CLK_SIM1
- IMX6UL_CLK_SIM2
- IMX6UL_CLK_SIM_PODF
- IMX6UL_CLK_SIM_PRE_SEL
- IMX6UL_CLK_SIM_S
- IMX6UL_CLK_SIM_SEL
- IMX6UL_CLK_SPBA
- IMX6UL_CLK_SPDIF
- IMX6UL_CLK_SPDIF_GCLK
- IMX6UL_CLK_SPDIF_PODF
- IMX6UL_CLK_SPDIF_PRED
- IMX6UL_CLK_SPDIF_SEL
- IMX6UL_CLK_STEP
- IMX6UL_CLK_UART1_IPG
- IMX6UL_CLK_UART1_SERIAL
- IMX6UL_CLK_UART2_IPG
- IMX6UL_CLK_UART2_SERIAL
- IMX6UL_CLK_UART3_IPG
- IMX6UL_CLK_UART3_SERIAL
- IMX6UL_CLK_UART4_IPG
- IMX6UL_CLK_UART4_SERIAL
- IMX6UL_CLK_UART5_IPG
- IMX6UL_CLK_UART5_SERIAL
- IMX6UL_CLK_UART6_IPG
- IMX6UL_CLK_UART6_SERIAL
- IMX6UL_CLK_UART7_IPG
- IMX6UL_CLK_UART7_SERIAL
- IMX6UL_CLK_UART8_IPG
- IMX6UL_CLK_UART8_SERIAL
- IMX6UL_CLK_UART_PODF
- IMX6UL_CLK_UART_SEL
- IMX6UL_CLK_USBOH3
- IMX6UL_CLK_USBPHY1
- IMX6UL_CLK_USBPHY1_GATE
- IMX6UL_CLK_USBPHY2
- IMX6UL_CLK_USBPHY2_GATE
- IMX6UL_CLK_USDHC1
- IMX6UL_CLK_USDHC1_PODF
- IMX6UL_CLK_USDHC1_SEL
- IMX6UL_CLK_USDHC2
- IMX6UL_CLK_USDHC2_PODF
- IMX6UL_CLK_USDHC2_SEL
- IMX6UL_CLK_WDOG1
- IMX6UL_CLK_WDOG2
- IMX6UL_CLK_WDOG3
- IMX6UL_CPUFREQ_CLK_NUM
- IMX6UL_FEC
- IMX6UL_GPR1_ENET1_CLK_DIR
- IMX6UL_GPR1_ENET1_CLK_OUTPUT
- IMX6UL_GPR1_ENET2_CLK_DIR
- IMX6UL_GPR1_ENET2_CLK_OUTPUT
- IMX6UL_GPR1_ENET_CLK_DIR
- IMX6UL_GPR1_ENET_CLK_OUTPUT
- IMX6UL_GPR1_SAI1_MCLK_DIR
- IMX6UL_GPR1_SAI2_MCLK_DIR
- IMX6UL_GPR1_SAI3_MCLK_DIR
- IMX6UL_GPR1_SAI_MCLK_MASK
- IMX6UL_PLL1_BYPASS
- IMX6UL_PLL1_BYPASS_SRC
- IMX6UL_PLL2_BYPASS
- IMX6UL_PLL2_BYPASS_SRC
- IMX6UL_PLL3_BYPASS
- IMX6UL_PLL3_BYPASS_SRC
- IMX6UL_PLL4_BYPASS
- IMX6UL_PLL4_BYPASS_SRC
- IMX6UL_PLL5_BYPASS
- IMX6UL_PLL5_BYPASS_SRC
- IMX6UL_PLL6_BYPASS
- IMX6UL_PLL6_BYPASS_SRC
- IMX6UL_PLL7_BYPASS
- IMX6UL_PLL7_BYPASS_SRC
- IMX6UL_UART1_BASE_ADDR
- IMX6UL_UART2_BASE_ADDR
- IMX6UL_UART3_BASE_ADDR
- IMX6UL_UART4_BASE_ADDR
- IMX6UL_UART5_BASE_ADDR
- IMX6UL_UART6_BASE_ADDR
- IMX6UL_UART7_BASE_ADDR
- IMX6UL_UART8_BASE_ADDR
- IMX6UL_UART_BASE
- IMX6UL_UART_BASE_ADDR
- IMX6_CPUFREQ_CLKS
- IMX6_MISC0
- IMX6_MISC0_REFTOP_SELBIASOFF
- IMX6_MISC1
- IMX6_MISC1_IRQ_TEMPHIGH
- IMX6_MISC1_IRQ_TEMPLOW
- IMX6_MISC1_IRQ_TEMPPANIC
- IMX6_PCIE_FLAG_IMX6_PHY
- IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE
- IMX6_PCIE_FLAG_SUPPORTS_SUSPEND
- IMX6_TEMPSENSE0
- IMX6_TEMPSENSE0_ALARM_VALUE_MASK
- IMX6_TEMPSENSE0_ALARM_VALUE_SHIFT
- IMX6_TEMPSENSE0_FINISHED
- IMX6_TEMPSENSE0_MEASURE_TEMP
- IMX6_TEMPSENSE0_POWER_DOWN
- IMX6_TEMPSENSE0_TEMP_CNT_MASK
- IMX6_TEMPSENSE0_TEMP_CNT_SHIFT
- IMX6_TEMPSENSE1
- IMX6_TEMPSENSE1_MEASURE_FREQ
- IMX6_TEMPSENSE1_MEASURE_FREQ_SHIFT
- IMX6_TEMPSENSE2
- IMX6_TEMPSENSE2_LOW_VALUE_MASK
- IMX6_TEMPSENSE2_LOW_VALUE_SHIFT
- IMX6_TEMPSENSE2_PANIC_VALUE_MASK
- IMX6_TEMPSENSE2_PANIC_VALUE_SHIFT
- IMX7D
- IMX7D_ADC_ANALOGUE_CLK_CONFIG
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_128
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_16
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_32
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_4
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_64
- IMX7D_ADC_ANALOG_CLK_PRE_DIV_8
- IMX7D_ADC_AVERAGE_NUM_16
- IMX7D_ADC_AVERAGE_NUM_32
- IMX7D_ADC_AVERAGE_NUM_4
- IMX7D_ADC_AVERAGE_NUM_8
- IMX7D_ADC_CHAN
- IMX7D_ADC_INPUT_CLK
- IMX7D_ADC_ROOT_CLK
- IMX7D_ADC_TIMEOUT
- IMX7D_AHB_CHANNEL_ROOT_CG
- IMX7D_AHB_CHANNEL_ROOT_CLK
- IMX7D_AHB_CHANNEL_ROOT_DIV
- IMX7D_AHB_CHANNEL_ROOT_PRE_DIV
- IMX7D_AHB_CHANNEL_ROOT_SRC
- IMX7D_ARM_A7_ROOT_CG
- IMX7D_ARM_A7_ROOT_CLK
- IMX7D_ARM_A7_ROOT_DIV
- IMX7D_ARM_A7_ROOT_SRC
- IMX7D_ARM_M0_ROOT_CG
- IMX7D_ARM_M0_ROOT_CLK
- IMX7D_ARM_M0_ROOT_DIV
- IMX7D_ARM_M0_ROOT_SRC
- IMX7D_ARM_M4_ROOT_CG
- IMX7D_ARM_M4_ROOT_CLK
- IMX7D_ARM_M4_ROOT_DIV
- IMX7D_ARM_M4_ROOT_SRC
- IMX7D_AUDIO_MCLK_ROOT_CG
- IMX7D_AUDIO_MCLK_ROOT_CLK
- IMX7D_AUDIO_MCLK_ROOT_DIV
- IMX7D_AUDIO_MCLK_ROOT_PRE_DIV
- IMX7D_AUDIO_MCLK_ROOT_SRC
- IMX7D_CAAM_CLK
- IMX7D_CAN1_ROOT_CG
- IMX7D_CAN1_ROOT_CLK
- IMX7D_CAN1_ROOT_DIV
- IMX7D_CAN1_ROOT_PRE_DIV
- IMX7D_CAN1_ROOT_SRC
- IMX7D_CAN2_ROOT_CG
- IMX7D_CAN2_ROOT_CLK
- IMX7D_CAN2_ROOT_DIV
- IMX7D_CAN2_ROOT_PRE_DIV
- IMX7D_CAN2_ROOT_SRC
- IMX7D_CKIL
- IMX7D_CLKO1_ROOT_CG
- IMX7D_CLKO1_ROOT_DIV
- IMX7D_CLKO1_ROOT_PRE_DIV
- IMX7D_CLKO1_ROOT_SRC
- IMX7D_CLKO2_ROOT_CG
- IMX7D_CLKO2_ROOT_DIV
- IMX7D_CLKO2_ROOT_PRE_DIV
- IMX7D_CLKO2_ROOT_SRC
- IMX7D_CLK_ARM
- IMX7D_CLK_DUMMY
- IMX7D_CLK_END
- IMX7D_CSI_MCLK_ROOT_CG
- IMX7D_CSI_MCLK_ROOT_CLK
- IMX7D_CSI_MCLK_ROOT_DIV
- IMX7D_CSI_MCLK_ROOT_PRE_DIV
- IMX7D_CSI_MCLK_ROOT_SRC
- IMX7D_DISP_AXI_ROOT_CG
- IMX7D_DISP_AXI_ROOT_CLK
- IMX7D_DISP_AXI_ROOT_DIV
- IMX7D_DISP_AXI_ROOT_PRE_DIV
- IMX7D_DISP_AXI_ROOT_SRC
- IMX7D_DRAM_ALT_ROOT_CG
- IMX7D_DRAM_ALT_ROOT_CLK
- IMX7D_DRAM_ALT_ROOT_DIV
- IMX7D_DRAM_ALT_ROOT_PRE_DIV
- IMX7D_DRAM_ALT_ROOT_SRC
- IMX7D_DRAM_PHYM_ALT_ROOT_CG
- IMX7D_DRAM_PHYM_ALT_ROOT_CLK
- IMX7D_DRAM_PHYM_ALT_ROOT_DIV
- IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV
- IMX7D_DRAM_PHYM_ALT_ROOT_SRC
- IMX7D_DRAM_PHYM_ROOT_CG
- IMX7D_DRAM_PHYM_ROOT_CLK
- IMX7D_DRAM_PHYM_ROOT_DIV
- IMX7D_DRAM_PHYM_ROOT_SRC
- IMX7D_DRAM_ROOT_CG
- IMX7D_DRAM_ROOT_CLK
- IMX7D_DRAM_ROOT_DIV
- IMX7D_DRAM_ROOT_SRC
- IMX7D_EACH_CHANNEL_REG_OFFSET
- IMX7D_ECSPI1_ROOT_CG
- IMX7D_ECSPI1_ROOT_CLK
- IMX7D_ECSPI1_ROOT_DIV
- IMX7D_ECSPI1_ROOT_PRE_DIV
- IMX7D_ECSPI1_ROOT_SRC
- IMX7D_ECSPI2_ROOT_CG
- IMX7D_ECSPI2_ROOT_CLK
- IMX7D_ECSPI2_ROOT_DIV
- IMX7D_ECSPI2_ROOT_PRE_DIV
- IMX7D_ECSPI2_ROOT_SRC
- IMX7D_ECSPI3_ROOT_CG
- IMX7D_ECSPI3_ROOT_CLK
- IMX7D_ECSPI3_ROOT_DIV
- IMX7D_ECSPI3_ROOT_PRE_DIV
- IMX7D_ECSPI3_ROOT_SRC
- IMX7D_ECSPI4_ROOT_CG
- IMX7D_ECSPI4_ROOT_CLK
- IMX7D_ECSPI4_ROOT_DIV
- IMX7D_ECSPI4_ROOT_PRE_DIV
- IMX7D_ECSPI4_ROOT_SRC
- IMX7D_EIM_ROOT_CG
- IMX7D_EIM_ROOT_CLK
- IMX7D_EIM_ROOT_DIV
- IMX7D_EIM_ROOT_PRE_DIV
- IMX7D_EIM_ROOT_SRC
- IMX7D_ENABLE_M4
- IMX7D_ENET1_IPG_ROOT_CLK
- IMX7D_ENET1_REF_ROOT_CG
- IMX7D_ENET1_REF_ROOT_DIV
- IMX7D_ENET1_REF_ROOT_PRE_DIV
- IMX7D_ENET1_REF_ROOT_SRC
- IMX7D_ENET1_TIME_ROOT_CG
- IMX7D_ENET1_TIME_ROOT_CLK
- IMX7D_ENET1_TIME_ROOT_DIV
- IMX7D_ENET1_TIME_ROOT_PRE_DIV
- IMX7D_ENET1_TIME_ROOT_SRC
- IMX7D_ENET2_IPG_ROOT_CLK
- IMX7D_ENET2_REF_ROOT_CG
- IMX7D_ENET2_REF_ROOT_DIV
- IMX7D_ENET2_REF_ROOT_PRE_DIV
- IMX7D_ENET2_REF_ROOT_SRC
- IMX7D_ENET2_TIME_ROOT_CG
- IMX7D_ENET2_TIME_ROOT_CLK
- IMX7D_ENET2_TIME_ROOT_DIV
- IMX7D_ENET2_TIME_ROOT_PRE_DIV
- IMX7D_ENET2_TIME_ROOT_SRC
- IMX7D_ENET_AXI_ROOT_CG
- IMX7D_ENET_AXI_ROOT_CLK
- IMX7D_ENET_AXI_ROOT_DIV
- IMX7D_ENET_AXI_ROOT_PRE_DIV
- IMX7D_ENET_AXI_ROOT_SRC
- IMX7D_ENET_PHY_REF_ROOT_CG
- IMX7D_ENET_PHY_REF_ROOT_CLK
- IMX7D_ENET_PHY_REF_ROOT_DIV
- IMX7D_ENET_PHY_REF_ROOT_PRE_DIV
- IMX7D_ENET_PHY_REF_ROOT_SRC
- IMX7D_EPDC_PIXEL_ROOT_CG
- IMX7D_EPDC_PIXEL_ROOT_CLK
- IMX7D_EPDC_PIXEL_ROOT_DIV
- IMX7D_EPDC_PIXEL_ROOT_PRE_DIV
- IMX7D_EPDC_PIXEL_ROOT_SRC
- IMX7D_FLEXTIMER1_ROOT_CG
- IMX7D_FLEXTIMER1_ROOT_CLK
- IMX7D_FLEXTIMER1_ROOT_DIV
- IMX7D_FLEXTIMER1_ROOT_PRE_DIV
- IMX7D_FLEXTIMER1_ROOT_SRC
- IMX7D_FLEXTIMER2_ROOT_CG
- IMX7D_FLEXTIMER2_ROOT_CLK
- IMX7D_FLEXTIMER2_ROOT_DIV
- IMX7D_FLEXTIMER2_ROOT_PRE_DIV
- IMX7D_FLEXTIMER2_ROOT_SRC
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL
- IMX7D_GPR1_ENET1_CLK_DIR_MASK
- IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK
- IMX7D_GPR1_ENET2_CLK_DIR_MASK
- IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK
- IMX7D_GPR1_ENET_CLK_DIR_MASK
- IMX7D_GPR1_ENET_TX_CLK_SEL_MASK
- IMX7D_GPR1_IRQ_MASK
- IMX7D_GPR22_PCIE_PHY_PLL_LOCKED
- IMX7D_GPR5_CSI_MUX_CONTROL_MIPI
- IMX7D_GPT1_ROOT_CG
- IMX7D_GPT1_ROOT_CLK
- IMX7D_GPT1_ROOT_DIV
- IMX7D_GPT1_ROOT_PRE_DIV
- IMX7D_GPT1_ROOT_SRC
- IMX7D_GPT2_ROOT_CG
- IMX7D_GPT2_ROOT_CLK
- IMX7D_GPT2_ROOT_DIV
- IMX7D_GPT2_ROOT_PRE_DIV
- IMX7D_GPT2_ROOT_SRC
- IMX7D_GPT3_ROOT_CG
- IMX7D_GPT3_ROOT_CLK
- IMX7D_GPT3_ROOT_DIV
- IMX7D_GPT3_ROOT_PRE_DIV
- IMX7D_GPT3_ROOT_SRC
- IMX7D_GPT4_ROOT_CG
- IMX7D_GPT4_ROOT_CLK
- IMX7D_GPT4_ROOT_DIV
- IMX7D_GPT4_ROOT_PRE_DIV
- IMX7D_GPT4_ROOT_SRC
- IMX7D_GPT_3M_CLK
- IMX7D_I2C1_ROOT_CG
- IMX7D_I2C1_ROOT_CLK
- IMX7D_I2C1_ROOT_DIV
- IMX7D_I2C1_ROOT_PRE_DIV
- IMX7D_I2C1_ROOT_SRC
- IMX7D_I2C2_ROOT_CG
- IMX7D_I2C2_ROOT_CLK
- IMX7D_I2C2_ROOT_DIV
- IMX7D_I2C2_ROOT_PRE_DIV
- IMX7D_I2C2_ROOT_SRC
- IMX7D_I2C3_ROOT_CG
- IMX7D_I2C3_ROOT_CLK
- IMX7D_I2C3_ROOT_DIV
- IMX7D_I2C3_ROOT_PRE_DIV
- IMX7D_I2C3_ROOT_SRC
- IMX7D_I2C4_ROOT_CG
- IMX7D_I2C4_ROOT_CLK
- IMX7D_I2C4_ROOT_DIV
- IMX7D_I2C4_ROOT_PRE_DIV
- IMX7D_I2C4_ROOT_SRC
- IMX7D_IPG_ROOT_CLK
- IMX7D_KPP_ROOT_CLK
- IMX7D_LCDIF_PIXEL_ROOT_CG
- IMX7D_LCDIF_PIXEL_ROOT_CLK
- IMX7D_LCDIF_PIXEL_ROOT_DIV
- IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV
- IMX7D_LCDIF_PIXEL_ROOT_SRC
- IMX7D_LVDS1_IN_CLK
- IMX7D_LVDS1_OUT_CLK
- IMX7D_LVDS1_OUT_SEL
- IMX7D_M4_RST_MASK
- IMX7D_M4_START
- IMX7D_M4_STOP
- IMX7D_MAIN_AXI_ROOT_CG
- IMX7D_MAIN_AXI_ROOT_CLK
- IMX7D_MAIN_AXI_ROOT_DIV
- IMX7D_MAIN_AXI_ROOT_PRE_DIV
- IMX7D_MAIN_AXI_ROOT_SRC
- IMX7D_MIPI_CSI_ROOT_CG
- IMX7D_MIPI_CSI_ROOT_CLK
- IMX7D_MIPI_CSI_ROOT_DIV
- IMX7D_MIPI_CSI_ROOT_PRE_DIV
- IMX7D_MIPI_CSI_ROOT_SRC
- IMX7D_MIPI_DPHY_ROOT_CG
- IMX7D_MIPI_DPHY_ROOT_CLK
- IMX7D_MIPI_DPHY_ROOT_DIV
- IMX7D_MIPI_DPHY_ROOT_PRE_DIV
- IMX7D_MIPI_DPHY_ROOT_SRC
- IMX7D_MIPI_DSI_ROOT_CG
- IMX7D_MIPI_DSI_ROOT_CLK
- IMX7D_MIPI_DSI_ROOT_DIV
- IMX7D_MIPI_DSI_ROOT_PRE_DIV
- IMX7D_MIPI_DSI_ROOT_SRC
- IMX7D_MU_ROOT_CLK
- IMX7D_NAND_RAWNAND_CLK
- IMX7D_NAND_ROOT_CG
- IMX7D_NAND_ROOT_CLK
- IMX7D_NAND_ROOT_DIV
- IMX7D_NAND_ROOT_PRE_DIV
- IMX7D_NAND_ROOT_SRC
- IMX7D_NAND_USDHC_BUS_RAWNAND_CLK
- IMX7D_NAND_USDHC_BUS_ROOT_CG
- IMX7D_NAND_USDHC_BUS_ROOT_CLK
- IMX7D_NAND_USDHC_BUS_ROOT_DIV
- IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV
- IMX7D_NAND_USDHC_BUS_ROOT_SRC
- IMX7D_OCOTP_CLK
- IMX7D_OCRAM_CLK
- IMX7D_OCRAM_S_CLK
- IMX7D_OSC_24M_CLK
- IMX7D_PCIE_CTRL_ROOT_CG
- IMX7D_PCIE_CTRL_ROOT_CLK
- IMX7D_PCIE_CTRL_ROOT_DIV
- IMX7D_PCIE_CTRL_ROOT_PRE_DIV
- IMX7D_PCIE_CTRL_ROOT_SRC
- IMX7D_PCIE_PHY_ROOT_CG
- IMX7D_PCIE_PHY_ROOT_CLK
- IMX7D_PCIE_PHY_ROOT_DIV
- IMX7D_PCIE_PHY_ROOT_PRE_DIV
- IMX7D_PCIE_PHY_ROOT_SRC
- IMX7D_PLL_ARM_MAIN
- IMX7D_PLL_ARM_MAIN_BYPASS
- IMX7D_PLL_ARM_MAIN_CLK
- IMX7D_PLL_ARM_MAIN_SRC
- IMX7D_PLL_AUDIO_MAIN
- IMX7D_PLL_AUDIO_MAIN_BYPASS
- IMX7D_PLL_AUDIO_MAIN_CLK
- IMX7D_PLL_AUDIO_MAIN_SRC
- IMX7D_PLL_AUDIO_POST_DIV
- IMX7D_PLL_AUDIO_TEST_DIV
- IMX7D_PLL_DRAM_MAIN
- IMX7D_PLL_DRAM_MAIN_533M
- IMX7D_PLL_DRAM_MAIN_533M_CLK
- IMX7D_PLL_DRAM_MAIN_BYPASS
- IMX7D_PLL_DRAM_MAIN_CLK
- IMX7D_PLL_DRAM_MAIN_SRC
- IMX7D_PLL_DRAM_TEST_DIV
- IMX7D_PLL_ENET_MAIN
- IMX7D_PLL_ENET_MAIN_100M
- IMX7D_PLL_ENET_MAIN_100M_CLK
- IMX7D_PLL_ENET_MAIN_125M
- IMX7D_PLL_ENET_MAIN_125M_CLK
- IMX7D_PLL_ENET_MAIN_250M
- IMX7D_PLL_ENET_MAIN_250M_CLK
- IMX7D_PLL_ENET_MAIN_25M
- IMX7D_PLL_ENET_MAIN_25M_CLK
- IMX7D_PLL_ENET_MAIN_40M
- IMX7D_PLL_ENET_MAIN_40M_CLK
- IMX7D_PLL_ENET_MAIN_500M
- IMX7D_PLL_ENET_MAIN_500M_CLK
- IMX7D_PLL_ENET_MAIN_50M
- IMX7D_PLL_ENET_MAIN_50M_CLK
- IMX7D_PLL_ENET_MAIN_BYPASS
- IMX7D_PLL_ENET_MAIN_CLK
- IMX7D_PLL_ENET_MAIN_SRC
- IMX7D_PLL_SYS_MAIN
- IMX7D_PLL_SYS_MAIN_120M
- IMX7D_PLL_SYS_MAIN_120M_CLK
- IMX7D_PLL_SYS_MAIN_240M
- IMX7D_PLL_SYS_MAIN_240M_CLK
- IMX7D_PLL_SYS_MAIN_480M
- IMX7D_PLL_SYS_MAIN_480M_CLK
- IMX7D_PLL_SYS_MAIN_BYPASS
- IMX7D_PLL_SYS_MAIN_CLK
- IMX7D_PLL_SYS_MAIN_SRC
- IMX7D_PLL_SYS_PFD0_196M
- IMX7D_PLL_SYS_PFD0_196M_CLK
- IMX7D_PLL_SYS_PFD0_392M_CLK
- IMX7D_PLL_SYS_PFD1_166M
- IMX7D_PLL_SYS_PFD1_166M_CLK
- IMX7D_PLL_SYS_PFD1_332M_CLK
- IMX7D_PLL_SYS_PFD2_135M
- IMX7D_PLL_SYS_PFD2_135M_CLK
- IMX7D_PLL_SYS_PFD2_270M_CLK
- IMX7D_PLL_SYS_PFD3_CLK
- IMX7D_PLL_SYS_PFD4_CLK
- IMX7D_PLL_SYS_PFD5_CLK
- IMX7D_PLL_SYS_PFD6_CLK
- IMX7D_PLL_SYS_PFD7_CLK
- IMX7D_PLL_VIDEO_MAIN
- IMX7D_PLL_VIDEO_MAIN_BYPASS
- IMX7D_PLL_VIDEO_MAIN_CLK
- IMX7D_PLL_VIDEO_MAIN_SRC
- IMX7D_PLL_VIDEO_POST_DIV
- IMX7D_PLL_VIDEO_TEST_DIV
- IMX7D_PWM1_ROOT_CG
- IMX7D_PWM1_ROOT_CLK
- IMX7D_PWM1_ROOT_DIV
- IMX7D_PWM1_ROOT_PRE_DIV
- IMX7D_PWM1_ROOT_SRC
- IMX7D_PWM2_ROOT_CG
- IMX7D_PWM2_ROOT_CLK
- IMX7D_PWM2_ROOT_DIV
- IMX7D_PWM2_ROOT_PRE_DIV
- IMX7D_PWM2_ROOT_SRC
- IMX7D_PWM3_ROOT_CG
- IMX7D_PWM3_ROOT_CLK
- IMX7D_PWM3_ROOT_DIV
- IMX7D_PWM3_ROOT_PRE_DIV
- IMX7D_PWM3_ROOT_SRC
- IMX7D_PWM4_ROOT_CG
- IMX7D_PWM4_ROOT_CLK
- IMX7D_PWM4_ROOT_DIV
- IMX7D_PWM4_ROOT_PRE_DIV
- IMX7D_PWM4_ROOT_SRC
- IMX7D_QSPI_ROOT_CG
- IMX7D_QSPI_ROOT_CLK
- IMX7D_QSPI_ROOT_DIV
- IMX7D_QSPI_ROOT_PRE_DIV
- IMX7D_QSPI_ROOT_SRC
- IMX7D_REG_ADC_ADC_CFG
- IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN
- IMX7D_REG_ADC_ADC_CFG_ADC_EN
- IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN
- IMX7D_REG_ADC_CHANNEL_CFG2_BASE
- IMX7D_REG_ADC_CHA_B_CNV_RSLT
- IMX7D_REG_ADC_CHC_D_CNV_RSLT
- IMX7D_REG_ADC_CH_A_CFG1
- IMX7D_REG_ADC_CH_A_CFG2
- IMX7D_REG_ADC_CH_B_CFG1
- IMX7D_REG_ADC_CH_B_CFG2
- IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN
- IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN
- IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL
- IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE
- IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16
- IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32
- IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4
- IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8
- IMX7D_REG_ADC_CH_C_CFG1
- IMX7D_REG_ADC_CH_C_CFG2
- IMX7D_REG_ADC_CH_D_CFG1
- IMX7D_REG_ADC_CH_D_CFG2
- IMX7D_REG_ADC_CH_SW_CFG
- IMX7D_REG_ADC_CH_SW_CNV_RSLT
- IMX7D_REG_ADC_DMA_FIFO
- IMX7D_REG_ADC_DMA_FIFO_DAT
- IMX7D_REG_ADC_FIFO_STATUS
- IMX7D_REG_ADC_INT_CHANNEL_INT_EN
- IMX7D_REG_ADC_INT_CHA_COV_INT_EN
- IMX7D_REG_ADC_INT_CHB_COV_INT_EN
- IMX7D_REG_ADC_INT_CHC_COV_INT_EN
- IMX7D_REG_ADC_INT_CHD_COV_INT_EN
- IMX7D_REG_ADC_INT_EN
- IMX7D_REG_ADC_INT_SIG_EN
- IMX7D_REG_ADC_INT_STATUS
- IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT
- IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS
- IMX7D_REG_ADC_TIMER_UNIT
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64
- IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8
- IMX7D_RPROC_MEM_MAX
- IMX7D_SAI1_IPG_CLK
- IMX7D_SAI1_ROOT_CG
- IMX7D_SAI1_ROOT_CLK
- IMX7D_SAI1_ROOT_DIV
- IMX7D_SAI1_ROOT_PRE_DIV
- IMX7D_SAI1_ROOT_SRC
- IMX7D_SAI2_IPG_CLK
- IMX7D_SAI2_ROOT_CG
- IMX7D_SAI2_ROOT_CLK
- IMX7D_SAI2_ROOT_DIV
- IMX7D_SAI2_ROOT_PRE_DIV
- IMX7D_SAI2_ROOT_SRC
- IMX7D_SAI3_IPG_CLK
- IMX7D_SAI3_ROOT_CG
- IMX7D_SAI3_ROOT_CLK
- IMX7D_SAI3_ROOT_DIV
- IMX7D_SAI3_ROOT_PRE_DIV
- IMX7D_SAI3_ROOT_SRC
- IMX7D_SDMA_CORE_CLK
- IMX7D_SEMA4_HS_ROOT_CLK
- IMX7D_SIM1_ROOT_CG
- IMX7D_SIM1_ROOT_CLK
- IMX7D_SIM1_ROOT_DIV
- IMX7D_SIM1_ROOT_PRE_DIV
- IMX7D_SIM1_ROOT_SRC
- IMX7D_SIM2_ROOT_CG
- IMX7D_SIM2_ROOT_CLK
- IMX7D_SIM2_ROOT_DIV
- IMX7D_SIM2_ROOT_PRE_DIV
- IMX7D_SIM2_ROOT_SRC
- IMX7D_SNVS_CLK
- IMX7D_SNVS_HPLR
- IMX7D_SNVS_LPGPR
- IMX7D_SNVS_LPLR
- IMX7D_SPDIF_ROOT_CG
- IMX7D_SPDIF_ROOT_CLK
- IMX7D_SPDIF_ROOT_DIV
- IMX7D_SPDIF_ROOT_PRE_DIV
- IMX7D_SPDIF_ROOT_SRC
- IMX7D_SRC_SCR
- IMX7D_SW_M4C_NON_SCLR_RST
- IMX7D_SW_M4C_RST
- IMX7D_SW_M4P_RST
- IMX7D_TRACE_ROOT_CG
- IMX7D_TRACE_ROOT_CLK
- IMX7D_TRACE_ROOT_DIV
- IMX7D_TRACE_ROOT_PRE_DIV
- IMX7D_TRACE_ROOT_SRC
- IMX7D_UART1_BASE_ADDR
- IMX7D_UART1_ROOT_CG
- IMX7D_UART1_ROOT_CLK
- IMX7D_UART1_ROOT_DIV
- IMX7D_UART1_ROOT_PRE_DIV
- IMX7D_UART1_ROOT_SRC
- IMX7D_UART2_BASE_ADDR
- IMX7D_UART2_ROOT_CG
- IMX7D_UART2_ROOT_CLK
- IMX7D_UART2_ROOT_DIV
- IMX7D_UART2_ROOT_PRE_DIV
- IMX7D_UART2_ROOT_SRC
- IMX7D_UART3_BASE_ADDR
- IMX7D_UART3_ROOT_CG
- IMX7D_UART3_ROOT_CLK
- IMX7D_UART3_ROOT_DIV
- IMX7D_UART3_ROOT_PRE_DIV
- IMX7D_UART3_ROOT_SRC
- IMX7D_UART4_BASE_ADDR
- IMX7D_UART4_ROOT_CG
- IMX7D_UART4_ROOT_CLK
- IMX7D_UART4_ROOT_DIV
- IMX7D_UART4_ROOT_PRE_DIV
- IMX7D_UART4_ROOT_SRC
- IMX7D_UART5_BASE_ADDR
- IMX7D_UART5_ROOT_CG
- IMX7D_UART5_ROOT_CLK
- IMX7D_UART5_ROOT_DIV
- IMX7D_UART5_ROOT_PRE_DIV
- IMX7D_UART5_ROOT_SRC
- IMX7D_UART6_BASE_ADDR
- IMX7D_UART6_ROOT_CG
- IMX7D_UART6_ROOT_CLK
- IMX7D_UART6_ROOT_DIV
- IMX7D_UART6_ROOT_PRE_DIV
- IMX7D_UART6_ROOT_SRC
- IMX7D_UART7_BASE_ADDR
- IMX7D_UART7_ROOT_CG
- IMX7D_UART7_ROOT_CLK
- IMX7D_UART7_ROOT_DIV
- IMX7D_UART7_ROOT_PRE_DIV
- IMX7D_UART7_ROOT_SRC
- IMX7D_UART_BASE
- IMX7D_UART_BASE_ADDR
- IMX7D_USB1_MAIN_480M_CLK
- IMX7D_USB_CTRL_CLK
- IMX7D_USB_HSIC_ROOT_CG
- IMX7D_USB_HSIC_ROOT_CLK
- IMX7D_USB_HSIC_ROOT_DIV
- IMX7D_USB_HSIC_ROOT_PRE_DIV
- IMX7D_USB_HSIC_ROOT_SRC
- IMX7D_USB_MAIN_480M_CLK
- IMX7D_USB_PHY1_CLK
- IMX7D_USB_PHY2_CLK
- IMX7D_USDHC1_ROOT_CG
- IMX7D_USDHC1_ROOT_CLK
- IMX7D_USDHC1_ROOT_DIV
- IMX7D_USDHC1_ROOT_PRE_DIV
- IMX7D_USDHC1_ROOT_SRC
- IMX7D_USDHC2_ROOT_CG
- IMX7D_USDHC2_ROOT_CLK
- IMX7D_USDHC2_ROOT_DIV
- IMX7D_USDHC2_ROOT_PRE_DIV
- IMX7D_USDHC2_ROOT_SRC
- IMX7D_USDHC3_ROOT_CG
- IMX7D_USDHC3_ROOT_CLK
- IMX7D_USDHC3_ROOT_DIV
- IMX7D_USDHC3_ROOT_PRE_DIV
- IMX7D_USDHC3_ROOT_SRC
- IMX7D_WDOG1_ROOT_CLK
- IMX7D_WDOG2_ROOT_CLK
- IMX7D_WDOG3_ROOT_CLK
- IMX7D_WDOG4_ROOT_CLK
- IMX7D_WDOG_ROOT_CG
- IMX7D_WDOG_ROOT_DIV
- IMX7D_WDOG_ROOT_PRE_DIV
- IMX7D_WDOG_ROOT_SRC
- IMX7D_WRCLK_ROOT_CG
- IMX7D_WRCLK_ROOT_CLK
- IMX7D_WRCLK_ROOT_DIV
- IMX7D_WRCLK_ROOT_PRE_DIV
- IMX7D_WRCLK_ROOT_SRC
- IMX7ULP_CCR
- IMX7ULP_CFGR0
- IMX7ULP_CFGR1
- IMX7ULP_CLK_APLL
- IMX7ULP_CLK_APLL_PFD0
- IMX7ULP_CLK_APLL_PFD1
- IMX7ULP_CLK_APLL_PFD2
- IMX7ULP_CLK_APLL_PFD3
- IMX7ULP_CLK_APLL_PFD_SEL
- IMX7ULP_CLK_APLL_POST_DIV1
- IMX7ULP_CLK_APLL_POST_DIV2
- IMX7ULP_CLK_APLL_PRE_DIV
- IMX7ULP_CLK_APLL_PRE_SEL
- IMX7ULP_CLK_APLL_SEL
- IMX7ULP_CLK_ARM
- IMX7ULP_CLK_BUS_DIV
- IMX7ULP_CLK_CAAM
- IMX7ULP_CLK_CORE_DIV
- IMX7ULP_CLK_DDR_DIV
- IMX7ULP_CLK_DDR_SEL
- IMX7ULP_CLK_DMA1
- IMX7ULP_CLK_DMA_MUX1
- IMX7ULP_CLK_DSI
- IMX7ULP_CLK_DUMMY
- IMX7ULP_CLK_FIRC
- IMX7ULP_CLK_FIRC_BUS_CLK
- IMX7ULP_CLK_FLEXBUS
- IMX7ULP_CLK_FLEXIO1
- IMX7ULP_CLK_GPU2D
- IMX7ULP_CLK_GPU3D
- IMX7ULP_CLK_GPU_DIV
- IMX7ULP_CLK_HSRUN_CORE_DIV
- IMX7ULP_CLK_HSRUN_SYS_SEL
- IMX7ULP_CLK_LCDIF
- IMX7ULP_CLK_LPI2C4
- IMX7ULP_CLK_LPI2C5
- IMX7ULP_CLK_LPI2C6
- IMX7ULP_CLK_LPI2C7
- IMX7ULP_CLK_LPIT1
- IMX7ULP_CLK_LPSPI2
- IMX7ULP_CLK_LPSPI3
- IMX7ULP_CLK_LPTPM4
- IMX7ULP_CLK_LPTPM5
- IMX7ULP_CLK_LPTPM6
- IMX7ULP_CLK_LPTPM7
- IMX7ULP_CLK_LPUART4
- IMX7ULP_CLK_LPUART5
- IMX7ULP_CLK_LPUART6
- IMX7ULP_CLK_LPUART7
- IMX7ULP_CLK_MIPI_PLL
- IMX7ULP_CLK_MMDC
- IMX7ULP_CLK_NIC0_DIV
- IMX7ULP_CLK_NIC1_BUS_DIV
- IMX7ULP_CLK_NIC1_DIV
- IMX7ULP_CLK_NIC1_EXT_DIV
- IMX7ULP_CLK_NIC_SEL
- IMX7ULP_CLK_PCC2_END
- IMX7ULP_CLK_PCC3_END
- IMX7ULP_CLK_PCTLC
- IMX7ULP_CLK_PCTLD
- IMX7ULP_CLK_PCTLE
- IMX7ULP_CLK_PCTLF
- IMX7ULP_CLK_PLAT_DIV
- IMX7ULP_CLK_RGPIO2P1
- IMX7ULP_CLK_ROSC
- IMX7ULP_CLK_SCG1_END
- IMX7ULP_CLK_SEMA42_1
- IMX7ULP_CLK_SIRC
- IMX7ULP_CLK_SMC1_END
- IMX7ULP_CLK_SOSC
- IMX7ULP_CLK_SOSC_BUS_CLK
- IMX7ULP_CLK_SPLL
- IMX7ULP_CLK_SPLL_BUS_CLK
- IMX7ULP_CLK_SPLL_PFD0
- IMX7ULP_CLK_SPLL_PFD1
- IMX7ULP_CLK_SPLL_PFD2
- IMX7ULP_CLK_SPLL_PFD3
- IMX7ULP_CLK_SPLL_PFD_SEL
- IMX7ULP_CLK_SPLL_POST_DIV1
- IMX7ULP_CLK_SPLL_POST_DIV2
- IMX7ULP_CLK_SPLL_PRE_DIV
- IMX7ULP_CLK_SPLL_PRE_SEL
- IMX7ULP_CLK_SPLL_SEL
- IMX7ULP_CLK_SYS_SEL
- IMX7ULP_CLK_UPLL
- IMX7ULP_CLK_USB0
- IMX7ULP_CLK_USB1
- IMX7ULP_CLK_USB_PHY
- IMX7ULP_CLK_USB_PL301
- IMX7ULP_CLK_USDHC0
- IMX7ULP_CLK_USDHC1
- IMX7ULP_CLK_VIU
- IMX7ULP_CLK_WDG1
- IMX7ULP_CLK_WDG2
- IMX7ULP_CR
- IMX7ULP_DER
- IMX7ULP_DMR0
- IMX7ULP_DMR1
- IMX7ULP_FCR
- IMX7ULP_FSR
- IMX7ULP_IER
- IMX7ULP_LPUART
- IMX7ULP_PAD_PTC0
- IMX7ULP_PAD_PTC0__FB_AD0
- IMX7ULP_PAD_PTC0__LPI2C4_SCL
- IMX7ULP_PAD_PTC0__LPUART4_CTS_B
- IMX7ULP_PAD_PTC0__PTC0
- IMX7ULP_PAD_PTC0__TPM4_CLKIN
- IMX7ULP_PAD_PTC0__TRACE_D15
- IMX7ULP_PAD_PTC1
- IMX7ULP_PAD_PTC10
- IMX7ULP_PAD_PTC10__FB_AD10
- IMX7ULP_PAD_PTC10__FXIO1_D6
- IMX7ULP_PAD_PTC10__LPI2C6_HREQ
- IMX7ULP_PAD_PTC10__LPSPI2_SCK
- IMX7ULP_PAD_PTC10__LPUART6_TX
- IMX7ULP_PAD_PTC10__PTC10
- IMX7ULP_PAD_PTC10__TPM7_CH3
- IMX7ULP_PAD_PTC10__TRACE_D5
- IMX7ULP_PAD_PTC11
- IMX7ULP_PAD_PTC11__FB_AD11
- IMX7ULP_PAD_PTC11__FXIO1_D7
- IMX7ULP_PAD_PTC11__LPSPI2_PCS0
- IMX7ULP_PAD_PTC11__LPUART6_RX
- IMX7ULP_PAD_PTC11__PTC11
- IMX7ULP_PAD_PTC11__TPM7_CH4
- IMX7ULP_PAD_PTC11__TRACE_D4
- IMX7ULP_PAD_PTC12
- IMX7ULP_PAD_PTC12__FB_AD12
- IMX7ULP_PAD_PTC12__FXIO1_D8
- IMX7ULP_PAD_PTC12__LPI2C7_SCL
- IMX7ULP_PAD_PTC12__LPSPI3_PCS1
- IMX7ULP_PAD_PTC12__LPUART7_CTS_B
- IMX7ULP_PAD_PTC12__PTC12
- IMX7ULP_PAD_PTC12__TPM7_CH5
- IMX7ULP_PAD_PTC12__TRACE_D3
- IMX7ULP_PAD_PTC13
- IMX7ULP_PAD_PTC13__FB_AD13
- IMX7ULP_PAD_PTC13__FXIO1_D9
- IMX7ULP_PAD_PTC13__LPI2C7_SDA
- IMX7ULP_PAD_PTC13__LPSPI3_PCS2
- IMX7ULP_PAD_PTC13__LPUART7_RTS_B
- IMX7ULP_PAD_PTC13__PTC13
- IMX7ULP_PAD_PTC13__TPM7_CLKIN
- IMX7ULP_PAD_PTC13__TRACE_D2
- IMX7ULP_PAD_PTC13__USB0_ID
- IMX7ULP_PAD_PTC14
- IMX7ULP_PAD_PTC14__FB_AD14
- IMX7ULP_PAD_PTC14__FXIO1_D10
- IMX7ULP_PAD_PTC14__LPI2C7_HREQ
- IMX7ULP_PAD_PTC14__LPSPI3_PCS3
- IMX7ULP_PAD_PTC14__LPUART7_TX
- IMX7ULP_PAD_PTC14__PTC14
- IMX7ULP_PAD_PTC14__TPM7_CH0
- IMX7ULP_PAD_PTC14__TRACE_D1
- IMX7ULP_PAD_PTC15
- IMX7ULP_PAD_PTC15__FB_AD15
- IMX7ULP_PAD_PTC15__FXIO1_D11
- IMX7ULP_PAD_PTC15__LPUART7_RX
- IMX7ULP_PAD_PTC15__PTC15
- IMX7ULP_PAD_PTC15__TPM7_CH1
- IMX7ULP_PAD_PTC15__TRACE_D0
- IMX7ULP_PAD_PTC16
- IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B
- IMX7ULP_PAD_PTC16__FXIO1_D12
- IMX7ULP_PAD_PTC16__LPSPI3_SIN
- IMX7ULP_PAD_PTC16__PTC16
- IMX7ULP_PAD_PTC16__TPM7_CH2
- IMX7ULP_PAD_PTC16__TRACE_CLKOUT
- IMX7ULP_PAD_PTC16__USB1_OC2
- IMX7ULP_PAD_PTC17
- IMX7ULP_PAD_PTC17__FB_CS0_B
- IMX7ULP_PAD_PTC17__FXIO1_D13
- IMX7ULP_PAD_PTC17__LPSPI3_SOUT
- IMX7ULP_PAD_PTC17__PTC17
- IMX7ULP_PAD_PTC17__TPM6_CLKIN
- IMX7ULP_PAD_PTC18
- IMX7ULP_PAD_PTC18__FB_OE_B
- IMX7ULP_PAD_PTC18__FXIO1_D14
- IMX7ULP_PAD_PTC18__LPSPI3_SCK
- IMX7ULP_PAD_PTC18__PTC18
- IMX7ULP_PAD_PTC18__TPM6_CH0
- IMX7ULP_PAD_PTC18__USB0_ID
- IMX7ULP_PAD_PTC18__VIU_DE
- IMX7ULP_PAD_PTC19
- IMX7ULP_PAD_PTC19__FB_A16
- IMX7ULP_PAD_PTC19__FXIO1_D15
- IMX7ULP_PAD_PTC19__LPSPI3_PCS0
- IMX7ULP_PAD_PTC19__PTC19
- IMX7ULP_PAD_PTC19__TPM6_CH1
- IMX7ULP_PAD_PTC19__USB0_ID
- IMX7ULP_PAD_PTC19__USB1_PWR2
- IMX7ULP_PAD_PTC19__VIU_DE
- IMX7ULP_PAD_PTC1__FB_AD1
- IMX7ULP_PAD_PTC1__LPI2C4_SDA
- IMX7ULP_PAD_PTC1__LPUART4_RTS_B
- IMX7ULP_PAD_PTC1__PTC1
- IMX7ULP_PAD_PTC1__TPM4_CH0
- IMX7ULP_PAD_PTC1__TRACE_D14
- IMX7ULP_PAD_PTC2
- IMX7ULP_PAD_PTC2__FB_AD2
- IMX7ULP_PAD_PTC2__LPI2C4_HREQ
- IMX7ULP_PAD_PTC2__LPUART4_TX
- IMX7ULP_PAD_PTC2__PTC2
- IMX7ULP_PAD_PTC2__TPM4_CH1
- IMX7ULP_PAD_PTC2__TRACE_D13
- IMX7ULP_PAD_PTC3
- IMX7ULP_PAD_PTC3__FB_AD3
- IMX7ULP_PAD_PTC3__LPUART4_RX
- IMX7ULP_PAD_PTC3__PTC3
- IMX7ULP_PAD_PTC3__TPM4_CH2
- IMX7ULP_PAD_PTC3__TRACE_D12
- IMX7ULP_PAD_PTC4
- IMX7ULP_PAD_PTC4__FB_AD4
- IMX7ULP_PAD_PTC4__FXIO1_D0
- IMX7ULP_PAD_PTC4__LPI2C5_SCL
- IMX7ULP_PAD_PTC4__LPSPI2_PCS1
- IMX7ULP_PAD_PTC4__LPUART5_CTS_B
- IMX7ULP_PAD_PTC4__PTC4
- IMX7ULP_PAD_PTC4__TPM4_CH3
- IMX7ULP_PAD_PTC4__TRACE_D11
- IMX7ULP_PAD_PTC5
- IMX7ULP_PAD_PTC5__FB_AD5
- IMX7ULP_PAD_PTC5__FXIO1_D1
- IMX7ULP_PAD_PTC5__LPI2C5_SDA
- IMX7ULP_PAD_PTC5__LPSPI2_PCS2
- IMX7ULP_PAD_PTC5__LPUART5_RTS_B
- IMX7ULP_PAD_PTC5__PTC5
- IMX7ULP_PAD_PTC5__TPM4_CH4
- IMX7ULP_PAD_PTC5__TRACE_D10
- IMX7ULP_PAD_PTC6
- IMX7ULP_PAD_PTC6__FB_AD6
- IMX7ULP_PAD_PTC6__FXIO1_D2
- IMX7ULP_PAD_PTC6__LPI2C5_HREQ
- IMX7ULP_PAD_PTC6__LPSPI2_PCS3
- IMX7ULP_PAD_PTC6__LPUART5_TX
- IMX7ULP_PAD_PTC6__PTC6
- IMX7ULP_PAD_PTC6__TPM4_CH5
- IMX7ULP_PAD_PTC6__TRACE_D9
- IMX7ULP_PAD_PTC7
- IMX7ULP_PAD_PTC7__FB_AD7
- IMX7ULP_PAD_PTC7__FXIO1_D3
- IMX7ULP_PAD_PTC7__LPUART5_RX
- IMX7ULP_PAD_PTC7__PTC7
- IMX7ULP_PAD_PTC7__TPM5_CH1
- IMX7ULP_PAD_PTC7__TRACE_D8
- IMX7ULP_PAD_PTC8
- IMX7ULP_PAD_PTC8__FB_AD8
- IMX7ULP_PAD_PTC8__FXIO1_D4
- IMX7ULP_PAD_PTC8__LPI2C6_SCL
- IMX7ULP_PAD_PTC8__LPSPI2_SIN
- IMX7ULP_PAD_PTC8__LPUART6_CTS_B
- IMX7ULP_PAD_PTC8__PTC8
- IMX7ULP_PAD_PTC8__TPM5_CLKIN
- IMX7ULP_PAD_PTC8__TRACE_D7
- IMX7ULP_PAD_PTC9
- IMX7ULP_PAD_PTC9__FB_AD9
- IMX7ULP_PAD_PTC9__FXIO1_D5
- IMX7ULP_PAD_PTC9__LPI2C6_SDA
- IMX7ULP_PAD_PTC9__LPSPI2_SOUT
- IMX7ULP_PAD_PTC9__LPUART6_RTS_B
- IMX7ULP_PAD_PTC9__PTC9
- IMX7ULP_PAD_PTC9__TPM5_CH0
- IMX7ULP_PAD_PTC9__TRACE_D6
- IMX7ULP_PAD_PTD0
- IMX7ULP_PAD_PTD0__PTD0
- IMX7ULP_PAD_PTD0__SDHC0_RESET_B
- IMX7ULP_PAD_PTD1
- IMX7ULP_PAD_PTD10
- IMX7ULP_PAD_PTD10__PTD10
- IMX7ULP_PAD_PTD10__SDHC0_D0
- IMX7ULP_PAD_PTD10__TPM4_CH1
- IMX7ULP_PAD_PTD11
- IMX7ULP_PAD_PTD11__PTD11
- IMX7ULP_PAD_PTD11__SDHC0_DQS
- IMX7ULP_PAD_PTD11__TPM4_CH2
- IMX7ULP_PAD_PTD1__PTD1
- IMX7ULP_PAD_PTD1__SDHC0_CMD
- IMX7ULP_PAD_PTD2
- IMX7ULP_PAD_PTD2__PTD2
- IMX7ULP_PAD_PTD2__SDHC0_CLK
- IMX7ULP_PAD_PTD3
- IMX7ULP_PAD_PTD3__PTD3
- IMX7ULP_PAD_PTD3__SDHC0_D7
- IMX7ULP_PAD_PTD4
- IMX7ULP_PAD_PTD4__PTD4
- IMX7ULP_PAD_PTD4__SDHC0_D6
- IMX7ULP_PAD_PTD5
- IMX7ULP_PAD_PTD5__PTD5
- IMX7ULP_PAD_PTD5__SDHC0_D5
- IMX7ULP_PAD_PTD6
- IMX7ULP_PAD_PTD6__PTD6
- IMX7ULP_PAD_PTD6__SDHC0_D4
- IMX7ULP_PAD_PTD7
- IMX7ULP_PAD_PTD7__PTD7
- IMX7ULP_PAD_PTD7__SDHC0_D3
- IMX7ULP_PAD_PTD8
- IMX7ULP_PAD_PTD8__PTD8
- IMX7ULP_PAD_PTD8__SDHC0_D2
- IMX7ULP_PAD_PTD8__TPM4_CLKIN
- IMX7ULP_PAD_PTD9
- IMX7ULP_PAD_PTD9__PTD9
- IMX7ULP_PAD_PTD9__SDHC0_D1
- IMX7ULP_PAD_PTD9__TPM4_CH0
- IMX7ULP_PAD_PTE0
- IMX7ULP_PAD_PTE0__FB_A25
- IMX7ULP_PAD_PTE0__FXIO1_D31
- IMX7ULP_PAD_PTE0__LPI2C4_SCL
- IMX7ULP_PAD_PTE0__LPSPI2_PCS1
- IMX7ULP_PAD_PTE0__LPUART4_CTS_B
- IMX7ULP_PAD_PTE0__PTE0
- IMX7ULP_PAD_PTE0__SDHC1_D1
- IMX7ULP_PAD_PTE1
- IMX7ULP_PAD_PTE10
- IMX7ULP_PAD_PTE10__FB_A19
- IMX7ULP_PAD_PTE10__FXIO1_D21
- IMX7ULP_PAD_PTE10__LPI2C6_HREQ
- IMX7ULP_PAD_PTE10__LPSPI3_PCS3
- IMX7ULP_PAD_PTE10__LPUART6_TX
- IMX7ULP_PAD_PTE10__PTE10
- IMX7ULP_PAD_PTE10__SDHC1_DQS
- IMX7ULP_PAD_PTE10__SDHC1_VS
- IMX7ULP_PAD_PTE10__TPM7_CH0
- IMX7ULP_PAD_PTE10__TRACE_D4
- IMX7ULP_PAD_PTE10__VIU_D18
- IMX7ULP_PAD_PTE11
- IMX7ULP_PAD_PTE11__FB_A20
- IMX7ULP_PAD_PTE11__FXIO1_D20
- IMX7ULP_PAD_PTE11__LPUART6_RX
- IMX7ULP_PAD_PTE11__PTE11
- IMX7ULP_PAD_PTE11__SDHC1_RESET_B
- IMX7ULP_PAD_PTE11__TPM7_CH1
- IMX7ULP_PAD_PTE11__TRACE_D3
- IMX7ULP_PAD_PTE11__VIU_D19
- IMX7ULP_PAD_PTE12
- IMX7ULP_PAD_PTE12__FB_A21
- IMX7ULP_PAD_PTE12__FXIO1_D19
- IMX7ULP_PAD_PTE12__LPI2C7_SCL
- IMX7ULP_PAD_PTE12__LPSPI3_SIN
- IMX7ULP_PAD_PTE12__LPUART7_CTS_B
- IMX7ULP_PAD_PTE12__PTE12
- IMX7ULP_PAD_PTE12__SDHC1_WP
- IMX7ULP_PAD_PTE12__TPM7_CH2
- IMX7ULP_PAD_PTE12__TRACE_D2
- IMX7ULP_PAD_PTE12__USB1_OC2
- IMX7ULP_PAD_PTE12__VIU_D20
- IMX7ULP_PAD_PTE13
- IMX7ULP_PAD_PTE13__FB_A22
- IMX7ULP_PAD_PTE13__FXIO1_D18
- IMX7ULP_PAD_PTE13__LPI2C7_SDA
- IMX7ULP_PAD_PTE13__LPSPI3_SOUT
- IMX7ULP_PAD_PTE13__LPUART7_RTS_B
- IMX7ULP_PAD_PTE13__PTE13
- IMX7ULP_PAD_PTE13__SDHC1_CD
- IMX7ULP_PAD_PTE13__TPM6_CLKIN
- IMX7ULP_PAD_PTE13__TRACE_D1
- IMX7ULP_PAD_PTE13__USB1_PWR2
- IMX7ULP_PAD_PTE13__VIU_D21
- IMX7ULP_PAD_PTE14
- IMX7ULP_PAD_PTE14__FB_A23
- IMX7ULP_PAD_PTE14__FXIO1_D17
- IMX7ULP_PAD_PTE14__LPI2C7_HREQ
- IMX7ULP_PAD_PTE14__LPSPI3_SCK
- IMX7ULP_PAD_PTE14__LPUART7_TX
- IMX7ULP_PAD_PTE14__PTE14
- IMX7ULP_PAD_PTE14__SDHC1_VS
- IMX7ULP_PAD_PTE14__TPM6_CH0
- IMX7ULP_PAD_PTE14__TRACE_D0
- IMX7ULP_PAD_PTE14__USB0_OC
- IMX7ULP_PAD_PTE14__VIU_D22
- IMX7ULP_PAD_PTE15
- IMX7ULP_PAD_PTE15__FB_A24
- IMX7ULP_PAD_PTE15__FXIO1_D16
- IMX7ULP_PAD_PTE15__LPSPI3_PCS0
- IMX7ULP_PAD_PTE15__LPUART7_RX
- IMX7ULP_PAD_PTE15__PTE15
- IMX7ULP_PAD_PTE15__TPM6_CH1
- IMX7ULP_PAD_PTE15__TRACE_CLKOUT
- IMX7ULP_PAD_PTE15__USB0_PWR
- IMX7ULP_PAD_PTE15__VIU_D23
- IMX7ULP_PAD_PTE1__FB_A26
- IMX7ULP_PAD_PTE1__FXIO1_D30
- IMX7ULP_PAD_PTE1__LPI2C4_SDA
- IMX7ULP_PAD_PTE1__LPSPI2_PCS2
- IMX7ULP_PAD_PTE1__LPUART4_RTS_B
- IMX7ULP_PAD_PTE1__PTE1
- IMX7ULP_PAD_PTE1__SDHC1_D0
- IMX7ULP_PAD_PTE2
- IMX7ULP_PAD_PTE2__FXIO1_D29
- IMX7ULP_PAD_PTE2__LPI2C4_HREQ
- IMX7ULP_PAD_PTE2__LPSPI2_PCS3
- IMX7ULP_PAD_PTE2__LPUART4_TX
- IMX7ULP_PAD_PTE2__PTE2
- IMX7ULP_PAD_PTE2__SDHC1_CLK
- IMX7ULP_PAD_PTE3
- IMX7ULP_PAD_PTE3__FXIO1_D28
- IMX7ULP_PAD_PTE3__LPUART4_RX
- IMX7ULP_PAD_PTE3__PTE3
- IMX7ULP_PAD_PTE3__SDHC1_CMD
- IMX7ULP_PAD_PTE3__TPM5_CH1
- IMX7ULP_PAD_PTE4
- IMX7ULP_PAD_PTE4__FXIO1_D27
- IMX7ULP_PAD_PTE4__LPI2C5_SCL
- IMX7ULP_PAD_PTE4__LPSPI2_SIN
- IMX7ULP_PAD_PTE4__LPUART5_CTS_B
- IMX7ULP_PAD_PTE4__PTE4
- IMX7ULP_PAD_PTE4__SDHC1_D3
- IMX7ULP_PAD_PTE4__TPM5_CLKIN
- IMX7ULP_PAD_PTE5
- IMX7ULP_PAD_PTE5__FXIO1_D26
- IMX7ULP_PAD_PTE5__LPI2C5_SDA
- IMX7ULP_PAD_PTE5__LPSPI2_SOUT
- IMX7ULP_PAD_PTE5__LPUART5_RTS_B
- IMX7ULP_PAD_PTE5__PTE5
- IMX7ULP_PAD_PTE5__SDHC1_D2
- IMX7ULP_PAD_PTE5__TPM5_CH0
- IMX7ULP_PAD_PTE5__VIU_DE
- IMX7ULP_PAD_PTE6
- IMX7ULP_PAD_PTE6__FB_A17
- IMX7ULP_PAD_PTE6__FXIO1_D25
- IMX7ULP_PAD_PTE6__LPI2C5_HREQ
- IMX7ULP_PAD_PTE6__LPSPI2_SCK
- IMX7ULP_PAD_PTE6__LPUART5_TX
- IMX7ULP_PAD_PTE6__PTE6
- IMX7ULP_PAD_PTE6__SDHC1_D4
- IMX7ULP_PAD_PTE6__TPM7_CH3
- IMX7ULP_PAD_PTE6__USB0_OC
- IMX7ULP_PAD_PTE7
- IMX7ULP_PAD_PTE7__FB_A18
- IMX7ULP_PAD_PTE7__FXIO1_D24
- IMX7ULP_PAD_PTE7__LPSPI2_PCS0
- IMX7ULP_PAD_PTE7__LPUART5_RX
- IMX7ULP_PAD_PTE7__PTE7
- IMX7ULP_PAD_PTE7__SDHC1_D5
- IMX7ULP_PAD_PTE7__TPM7_CH4
- IMX7ULP_PAD_PTE7__TRACE_D7
- IMX7ULP_PAD_PTE7__USB0_PWR
- IMX7ULP_PAD_PTE7__VIU_FID
- IMX7ULP_PAD_PTE8
- IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B
- IMX7ULP_PAD_PTE8__FXIO1_D23
- IMX7ULP_PAD_PTE8__LPI2C6_SCL
- IMX7ULP_PAD_PTE8__LPSPI3_PCS1
- IMX7ULP_PAD_PTE8__LPUART6_CTS_B
- IMX7ULP_PAD_PTE8__PTE8
- IMX7ULP_PAD_PTE8__SDHC1_D6
- IMX7ULP_PAD_PTE8__SDHC1_WP
- IMX7ULP_PAD_PTE8__TPM7_CH5
- IMX7ULP_PAD_PTE8__TRACE_D6
- IMX7ULP_PAD_PTE8__VIU_D16
- IMX7ULP_PAD_PTE9
- IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B
- IMX7ULP_PAD_PTE9__FXIO1_D22
- IMX7ULP_PAD_PTE9__LPI2C6_SDA
- IMX7ULP_PAD_PTE9__LPSPI3_PCS2
- IMX7ULP_PAD_PTE9__LPUART6_RTS_B
- IMX7ULP_PAD_PTE9__PTE9
- IMX7ULP_PAD_PTE9__SDHC1_CD
- IMX7ULP_PAD_PTE9__SDHC1_D7
- IMX7ULP_PAD_PTE9__TPM7_CLKIN
- IMX7ULP_PAD_PTE9__TRACE_D5
- IMX7ULP_PAD_PTE9__VIU_D17
- IMX7ULP_PAD_PTF0
- IMX7ULP_PAD_PTF0__FB_RW_B
- IMX7ULP_PAD_PTF0__LPI2C4_SCL
- IMX7ULP_PAD_PTF0__LPUART4_CTS_B
- IMX7ULP_PAD_PTF0__PTF0
- IMX7ULP_PAD_PTF0__TPM4_CLKIN
- IMX7ULP_PAD_PTF0__VIU_DE
- IMX7ULP_PAD_PTF1
- IMX7ULP_PAD_PTF10
- IMX7ULP_PAD_PTF10__FB_AD23
- IMX7ULP_PAD_PTF10__FXIO1_D6
- IMX7ULP_PAD_PTF10__LPI2C6_HREQ
- IMX7ULP_PAD_PTF10__LPSPI2_SCK
- IMX7ULP_PAD_PTF10__LPUART6_TX
- IMX7ULP_PAD_PTF10__PTF10
- IMX7ULP_PAD_PTF10__TPM7_CH3
- IMX7ULP_PAD_PTF10__USB1_ULPI_STP
- IMX7ULP_PAD_PTF10__VIU_D6
- IMX7ULP_PAD_PTF11
- IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B
- IMX7ULP_PAD_PTF11__FXIO1_D7
- IMX7ULP_PAD_PTF11__LPSPI2_PCS0
- IMX7ULP_PAD_PTF11__LPUART6_RX
- IMX7ULP_PAD_PTF11__PTF11
- IMX7ULP_PAD_PTF11__TPM7_CH4
- IMX7ULP_PAD_PTF11__USB1_ULPI_DIR
- IMX7ULP_PAD_PTF11__VIU_D7
- IMX7ULP_PAD_PTF12
- IMX7ULP_PAD_PTF12__FB_AD24
- IMX7ULP_PAD_PTF12__FXIO1_D8
- IMX7ULP_PAD_PTF12__LPI2C7_SCL
- IMX7ULP_PAD_PTF12__LPSPI3_PCS1
- IMX7ULP_PAD_PTF12__LPUART7_CTS_B
- IMX7ULP_PAD_PTF12__PTF12
- IMX7ULP_PAD_PTF12__TPM7_CH5
- IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0
- IMX7ULP_PAD_PTF12__VIU_D8
- IMX7ULP_PAD_PTF13
- IMX7ULP_PAD_PTF13__FB_AD25
- IMX7ULP_PAD_PTF13__FXIO1_D9
- IMX7ULP_PAD_PTF13__LPI2C7_SDA
- IMX7ULP_PAD_PTF13__LPSPI3_PCS2
- IMX7ULP_PAD_PTF13__LPUART7_RTS_B
- IMX7ULP_PAD_PTF13__PTF13
- IMX7ULP_PAD_PTF13__TPM7_CLKIN
- IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1
- IMX7ULP_PAD_PTF13__VIU_D9
- IMX7ULP_PAD_PTF14
- IMX7ULP_PAD_PTF14__FB_AD26
- IMX7ULP_PAD_PTF14__FXIO1_D10
- IMX7ULP_PAD_PTF14__LPI2C7_HREQ
- IMX7ULP_PAD_PTF14__LPSPI3_PCS3
- IMX7ULP_PAD_PTF14__LPUART7_TX
- IMX7ULP_PAD_PTF14__PTF14
- IMX7ULP_PAD_PTF14__TPM7_CH0
- IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2
- IMX7ULP_PAD_PTF14__VIU_D10
- IMX7ULP_PAD_PTF15
- IMX7ULP_PAD_PTF15__FB_AD27
- IMX7ULP_PAD_PTF15__FXIO1_D11
- IMX7ULP_PAD_PTF15__LPUART7_RX
- IMX7ULP_PAD_PTF15__PTF15
- IMX7ULP_PAD_PTF15__TPM7_CH1
- IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3
- IMX7ULP_PAD_PTF15__VIU_D11
- IMX7ULP_PAD_PTF16
- IMX7ULP_PAD_PTF16__FB_AD28
- IMX7ULP_PAD_PTF16__FXIO1_D12
- IMX7ULP_PAD_PTF16__LPSPI3_SIN
- IMX7ULP_PAD_PTF16__PTF16
- IMX7ULP_PAD_PTF16__TPM7_CH2
- IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4
- IMX7ULP_PAD_PTF16__VIU_D12
- IMX7ULP_PAD_PTF17
- IMX7ULP_PAD_PTF17__FB_AD29
- IMX7ULP_PAD_PTF17__FXIO1_D13
- IMX7ULP_PAD_PTF17__LPSPI3_SOUT
- IMX7ULP_PAD_PTF17__PTF17
- IMX7ULP_PAD_PTF17__TPM6_CLKIN
- IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5
- IMX7ULP_PAD_PTF17__VIU_D13
- IMX7ULP_PAD_PTF18
- IMX7ULP_PAD_PTF18__FB_AD30
- IMX7ULP_PAD_PTF18__FXIO1_D14
- IMX7ULP_PAD_PTF18__LPSPI3_SCK
- IMX7ULP_PAD_PTF18__PTF18
- IMX7ULP_PAD_PTF18__TPM6_CH0
- IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6
- IMX7ULP_PAD_PTF18__VIU_D14
- IMX7ULP_PAD_PTF19
- IMX7ULP_PAD_PTF19__FB_AD31
- IMX7ULP_PAD_PTF19__FXIO1_D15
- IMX7ULP_PAD_PTF19__LPSPI3_PCS0
- IMX7ULP_PAD_PTF19__PTF19
- IMX7ULP_PAD_PTF19__TPM6_CH1
- IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7
- IMX7ULP_PAD_PTF19__VIU_D15
- IMX7ULP_PAD_PTF1__CLKOUT
- IMX7ULP_PAD_PTF1__LPI2C4_SDA
- IMX7ULP_PAD_PTF1__LPUART4_RTS_B
- IMX7ULP_PAD_PTF1__PTF1
- IMX7ULP_PAD_PTF1__TPM4_CH0
- IMX7ULP_PAD_PTF1__VIU_HSYNC
- IMX7ULP_PAD_PTF2
- IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B
- IMX7ULP_PAD_PTF2__LPI2C4_HREQ
- IMX7ULP_PAD_PTF2__LPUART4_TX
- IMX7ULP_PAD_PTF2__PTF2
- IMX7ULP_PAD_PTF2__TPM4_CH1
- IMX7ULP_PAD_PTF2__VIU_VSYNC
- IMX7ULP_PAD_PTF3
- IMX7ULP_PAD_PTF3__FB_AD16
- IMX7ULP_PAD_PTF3__LPUART4_RX
- IMX7ULP_PAD_PTF3__PTF3
- IMX7ULP_PAD_PTF3__TPM4_CH2
- IMX7ULP_PAD_PTF3__VIU_PCLK
- IMX7ULP_PAD_PTF4
- IMX7ULP_PAD_PTF4__FB_AD17
- IMX7ULP_PAD_PTF4__FXIO1_D0
- IMX7ULP_PAD_PTF4__LPI2C5_SCL
- IMX7ULP_PAD_PTF4__LPSPI2_PCS1
- IMX7ULP_PAD_PTF4__LPUART5_CTS_B
- IMX7ULP_PAD_PTF4__PTF4
- IMX7ULP_PAD_PTF4__TPM4_CH3
- IMX7ULP_PAD_PTF4__VIU_D0
- IMX7ULP_PAD_PTF5
- IMX7ULP_PAD_PTF5__FB_AD18
- IMX7ULP_PAD_PTF5__FXIO1_D1
- IMX7ULP_PAD_PTF5__LPI2C5_SDA
- IMX7ULP_PAD_PTF5__LPSPI2_PCS2
- IMX7ULP_PAD_PTF5__LPUART5_RTS_B
- IMX7ULP_PAD_PTF5__PTF5
- IMX7ULP_PAD_PTF5__TPM4_CH4
- IMX7ULP_PAD_PTF5__VIU_D1
- IMX7ULP_PAD_PTF6
- IMX7ULP_PAD_PTF6__FB_AD19
- IMX7ULP_PAD_PTF6__FXIO1_D2
- IMX7ULP_PAD_PTF6__LPI2C5_HREQ
- IMX7ULP_PAD_PTF6__LPSPI2_PCS3
- IMX7ULP_PAD_PTF6__LPUART5_TX
- IMX7ULP_PAD_PTF6__PTF6
- IMX7ULP_PAD_PTF6__TPM4_CH5
- IMX7ULP_PAD_PTF6__VIU_D2
- IMX7ULP_PAD_PTF7
- IMX7ULP_PAD_PTF7__FB_AD20
- IMX7ULP_PAD_PTF7__FXIO1_D3
- IMX7ULP_PAD_PTF7__LPUART5_RX
- IMX7ULP_PAD_PTF7__PTF7
- IMX7ULP_PAD_PTF7__TPM5_CH1
- IMX7ULP_PAD_PTF7__VIU_D3
- IMX7ULP_PAD_PTF8
- IMX7ULP_PAD_PTF8__FB_AD21
- IMX7ULP_PAD_PTF8__FXIO1_D4
- IMX7ULP_PAD_PTF8__LPI2C6_SCL
- IMX7ULP_PAD_PTF8__LPSPI2_SIN
- IMX7ULP_PAD_PTF8__LPUART6_CTS_B
- IMX7ULP_PAD_PTF8__PTF8
- IMX7ULP_PAD_PTF8__TPM5_CLKIN
- IMX7ULP_PAD_PTF8__USB1_ULPI_CLK
- IMX7ULP_PAD_PTF8__VIU_D4
- IMX7ULP_PAD_PTF9
- IMX7ULP_PAD_PTF9__FB_AD22
- IMX7ULP_PAD_PTF9__FXIO1_D5
- IMX7ULP_PAD_PTF9__LPI2C6_SDA
- IMX7ULP_PAD_PTF9__LPSPI2_SOUT
- IMX7ULP_PAD_PTF9__LPUART6_RTS_B
- IMX7ULP_PAD_PTF9__PTF9
- IMX7ULP_PAD_PTF9__TPM5_CH0
- IMX7ULP_PAD_PTF9__USB1_ULPI_NXT
- IMX7ULP_PAD_PTF9__VIU_D5
- IMX7ULP_PAD_RESERVE0
- IMX7ULP_PAD_RESERVE1
- IMX7ULP_PAD_RESERVE10
- IMX7ULP_PAD_RESERVE11
- IMX7ULP_PAD_RESERVE12
- IMX7ULP_PAD_RESERVE13
- IMX7ULP_PAD_RESERVE14
- IMX7ULP_PAD_RESERVE15
- IMX7ULP_PAD_RESERVE16
- IMX7ULP_PAD_RESERVE17
- IMX7ULP_PAD_RESERVE18
- IMX7ULP_PAD_RESERVE19
- IMX7ULP_PAD_RESERVE2
- IMX7ULP_PAD_RESERVE20
- IMX7ULP_PAD_RESERVE21
- IMX7ULP_PAD_RESERVE22
- IMX7ULP_PAD_RESERVE23
- IMX7ULP_PAD_RESERVE24
- IMX7ULP_PAD_RESERVE25
- IMX7ULP_PAD_RESERVE26
- IMX7ULP_PAD_RESERVE27
- IMX7ULP_PAD_RESERVE28
- IMX7ULP_PAD_RESERVE29
- IMX7ULP_PAD_RESERVE3
- IMX7ULP_PAD_RESERVE30
- IMX7ULP_PAD_RESERVE31
- IMX7ULP_PAD_RESERVE32
- IMX7ULP_PAD_RESERVE33
- IMX7ULP_PAD_RESERVE34
- IMX7ULP_PAD_RESERVE35
- IMX7ULP_PAD_RESERVE36
- IMX7ULP_PAD_RESERVE37
- IMX7ULP_PAD_RESERVE38
- IMX7ULP_PAD_RESERVE39
- IMX7ULP_PAD_RESERVE4
- IMX7ULP_PAD_RESERVE40
- IMX7ULP_PAD_RESERVE41
- IMX7ULP_PAD_RESERVE42
- IMX7ULP_PAD_RESERVE43
- IMX7ULP_PAD_RESERVE44
- IMX7ULP_PAD_RESERVE45
- IMX7ULP_PAD_RESERVE46
- IMX7ULP_PAD_RESERVE47
- IMX7ULP_PAD_RESERVE5
- IMX7ULP_PAD_RESERVE6
- IMX7ULP_PAD_RESERVE7
- IMX7ULP_PAD_RESERVE8
- IMX7ULP_PAD_RESERVE9
- IMX7ULP_PARAM
- IMX7ULP_RDR
- IMX7ULP_RSR
- IMX7ULP_SR
- IMX7ULP_TCR
- IMX7ULP_TDR
- IMX7ULP_VERID
- IMX7_ANADIG_DIGPROG
- IMX7_CSI_PADS_NUM
- IMX7_CSI_PAD_SINK
- IMX7_CSI_PAD_SRC
- IMX7_DDR_PLL_POWER
- IMX7_ENET_PLL_POWER
- IMX7_MIPI_PHY_A_CORE_DOMAIN
- IMX7_MIPI_PHY_SW_Pxx_REQ
- IMX7_PCIE_PHY_A_CORE_DOMAIN
- IMX7_PCIE_PHY_SW_Pxx_REQ
- IMX7_PGC_MIPI
- IMX7_PGC_PCIE
- IMX7_PGC_USB_HSIC
- IMX7_POWER_DOMAIN_MIPI_PHY
- IMX7_POWER_DOMAIN_PCIE_PHY
- IMX7_POWER_DOMAIN_USB_HSIC_PHY
- IMX7_RESET_A7_CORE_POR_RESET0
- IMX7_RESET_A7_CORE_POR_RESET1
- IMX7_RESET_A7_CORE_RESET0
- IMX7_RESET_A7_CORE_RESET1
- IMX7_RESET_A7_DBG_RESET0
- IMX7_RESET_A7_DBG_RESET1
- IMX7_RESET_A7_ETM_RESET0
- IMX7_RESET_A7_ETM_RESET1
- IMX7_RESET_A7_L2RESET
- IMX7_RESET_A7_SOC_DBG_RESET
- IMX7_RESET_DDRC_CORE_RST
- IMX7_RESET_DDRC_PRST
- IMX7_RESET_EIM_RST
- IMX7_RESET_HSICPHY_PORT_RST
- IMX7_RESET_MIPI_PHY_MRST
- IMX7_RESET_MIPI_PHY_SRST
- IMX7_RESET_NUM
- IMX7_RESET_PCIEPHY
- IMX7_RESET_PCIEPHY_PERST
- IMX7_RESET_PCIE_CTRL_APPS_EN
- IMX7_RESET_PCIE_CTRL_APPS_TURNOFF
- IMX7_RESET_SW_M4C_RST
- IMX7_RESET_SW_M4P_RST
- IMX7_RESET_USBPHY1_POR
- IMX7_RESET_USBPHY1_PORT_RST
- IMX7_RESET_USBPHY2_POR
- IMX7_RESET_USBPHY2_PORT_RST
- IMX7_TEMPSENSE0
- IMX7_TEMPSENSE0_HIGH_ALARM_MASK
- IMX7_TEMPSENSE0_HIGH_ALARM_SHIFT
- IMX7_TEMPSENSE0_LOW_ALARM_MASK
- IMX7_TEMPSENSE0_LOW_ALARM_SHIFT
- IMX7_TEMPSENSE0_PANIC_ALARM_MASK
- IMX7_TEMPSENSE0_PANIC_ALARM_SHIFT
- IMX7_TEMPSENSE1
- IMX7_TEMPSENSE1_FINISHED
- IMX7_TEMPSENSE1_MEASURE_FREQ_MASK
- IMX7_TEMPSENSE1_MEASURE_FREQ_SHIFT
- IMX7_TEMPSENSE1_MEASURE_TEMP
- IMX7_TEMPSENSE1_POWER_DOWN
- IMX7_TEMPSENSE1_TEMP_VALUE_MASK
- IMX7_TEMPSENSE1_TEMP_VALUE_SHIFT
- IMX7_USB_HSIC_PHY_A_CORE_DOMAIN
- IMX7_USB_HSIC_PHY_SW_Pxx_REQ
- IMX7_USB_OTG1_PHY_A_CORE_DOMAIN
- IMX7_USB_OTG1_PHY_SW_Pxx_REQ
- IMX7_USB_OTG2_PHY_A_CORE_DOMAIN
- IMX7_USB_OTG2_PHY_SW_Pxx_REQ
- IMX8MM_ARM_PLL
- IMX8MM_ARM_PLL_BYPASS
- IMX8MM_ARM_PLL_OUT
- IMX8MM_ARM_PLL_REF_SEL
- IMX8MM_AUDIO_PLL1
- IMX8MM_AUDIO_PLL1_BYPASS
- IMX8MM_AUDIO_PLL1_OUT
- IMX8MM_AUDIO_PLL1_REF_SEL
- IMX8MM_AUDIO_PLL2
- IMX8MM_AUDIO_PLL2_BYPASS
- IMX8MM_AUDIO_PLL2_OUT
- IMX8MM_AUDIO_PLL2_REF_SEL
- IMX8MM_CLK_24M
- IMX8MM_CLK_32K
- IMX8MM_CLK_A53_CG
- IMX8MM_CLK_A53_DIV
- IMX8MM_CLK_A53_SRC
- IMX8MM_CLK_AHB
- IMX8MM_CLK_ARM
- IMX8MM_CLK_AUDIO_AHB
- IMX8MM_CLK_CLKO1
- IMX8MM_CLK_CSI1_CORE
- IMX8MM_CLK_CSI1_ESC
- IMX8MM_CLK_CSI1_PHY_REF
- IMX8MM_CLK_CSI1_ROOT
- IMX8MM_CLK_CSI2_CORE
- IMX8MM_CLK_CSI2_ESC
- IMX8MM_CLK_CSI2_PHY_REF
- IMX8MM_CLK_DC_PIXEL
- IMX8MM_CLK_DISP_APB
- IMX8MM_CLK_DISP_APB_ROOT
- IMX8MM_CLK_DISP_AXI
- IMX8MM_CLK_DISP_AXI_ROOT
- IMX8MM_CLK_DISP_DC8000
- IMX8MM_CLK_DISP_DTRC
- IMX8MM_CLK_DISP_ROOT
- IMX8MM_CLK_DISP_RTRM
- IMX8MM_CLK_DISP_RTRM_ROOT
- IMX8MM_CLK_DRAM_ALT
- IMX8MM_CLK_DRAM_ALT_ROOT
- IMX8MM_CLK_DRAM_APB
- IMX8MM_CLK_DRAM_CORE
- IMX8MM_CLK_DSI_CORE
- IMX8MM_CLK_DSI_DBI
- IMX8MM_CLK_DSI_PHY_REF
- IMX8MM_CLK_DUMMY
- IMX8MM_CLK_ECSPI1
- IMX8MM_CLK_ECSPI1_ROOT
- IMX8MM_CLK_ECSPI2
- IMX8MM_CLK_ECSPI2_ROOT
- IMX8MM_CLK_ECSPI3
- IMX8MM_CLK_ECSPI3_ROOT
- IMX8MM_CLK_END
- IMX8MM_CLK_ENET1_ROOT
- IMX8MM_CLK_ENET_AXI
- IMX8MM_CLK_ENET_PHY_REF
- IMX8MM_CLK_ENET_REF
- IMX8MM_CLK_ENET_TIMER
- IMX8MM_CLK_EXT1
- IMX8MM_CLK_EXT2
- IMX8MM_CLK_EXT3
- IMX8MM_CLK_EXT4
- IMX8MM_CLK_GIC
- IMX8MM_CLK_GPIO1_ROOT
- IMX8MM_CLK_GPIO2_ROOT
- IMX8MM_CLK_GPIO3_ROOT
- IMX8MM_CLK_GPIO4_ROOT
- IMX8MM_CLK_GPIO5_ROOT
- IMX8MM_CLK_GPT1
- IMX8MM_CLK_GPT1_ROOT
- IMX8MM_CLK_GPT_3M
- IMX8MM_CLK_GPU2D_CG
- IMX8MM_CLK_GPU2D_DIV
- IMX8MM_CLK_GPU2D_ROOT
- IMX8MM_CLK_GPU2D_SRC
- IMX8MM_CLK_GPU3D_CG
- IMX8MM_CLK_GPU3D_DIV
- IMX8MM_CLK_GPU3D_ROOT
- IMX8MM_CLK_GPU3D_SRC
- IMX8MM_CLK_GPU_AHB
- IMX8MM_CLK_GPU_AXI
- IMX8MM_CLK_GPU_BUS_ROOT
- IMX8MM_CLK_I2C1
- IMX8MM_CLK_I2C1_ROOT
- IMX8MM_CLK_I2C2
- IMX8MM_CLK_I2C2_ROOT
- IMX8MM_CLK_I2C3
- IMX8MM_CLK_I2C3_ROOT
- IMX8MM_CLK_I2C4
- IMX8MM_CLK_I2C4_ROOT
- IMX8MM_CLK_IPG_AUDIO_ROOT
- IMX8MM_CLK_IPG_ROOT
- IMX8MM_CLK_LCDIF_PIXEL
- IMX8MM_CLK_M4_CG
- IMX8MM_CLK_M4_DIV
- IMX8MM_CLK_M4_SRC
- IMX8MM_CLK_MAIN_AXI
- IMX8MM_CLK_MU_ROOT
- IMX8MM_CLK_NAND
- IMX8MM_CLK_NAND_ROOT
- IMX8MM_CLK_NAND_USDHC_BUS
- IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK
- IMX8MM_CLK_NOC
- IMX8MM_CLK_NOC_APB
- IMX8MM_CLK_OCOTP_ROOT
- IMX8MM_CLK_PCIE1_AUX
- IMX8MM_CLK_PCIE1_CTRL
- IMX8MM_CLK_PCIE1_PHY
- IMX8MM_CLK_PCIE1_ROOT
- IMX8MM_CLK_PCIE2_AUX
- IMX8MM_CLK_PCIE2_CTRL
- IMX8MM_CLK_PCIE2_PHY
- IMX8MM_CLK_PDM
- IMX8MM_CLK_PDM_IPG
- IMX8MM_CLK_PDM_ROOT
- IMX8MM_CLK_PWM1
- IMX8MM_CLK_PWM1_ROOT
- IMX8MM_CLK_PWM2
- IMX8MM_CLK_PWM2_ROOT
- IMX8MM_CLK_PWM3
- IMX8MM_CLK_PWM3_ROOT
- IMX8MM_CLK_PWM4
- IMX8MM_CLK_PWM4_ROOT
- IMX8MM_CLK_QSPI
- IMX8MM_CLK_QSPI_ROOT
- IMX8MM_CLK_SAI1
- IMX8MM_CLK_SAI1_IPG
- IMX8MM_CLK_SAI1_ROOT
- IMX8MM_CLK_SAI2
- IMX8MM_CLK_SAI2_IPG
- IMX8MM_CLK_SAI2_ROOT
- IMX8MM_CLK_SAI3
- IMX8MM_CLK_SAI3_IPG
- IMX8MM_CLK_SAI3_ROOT
- IMX8MM_CLK_SAI4
- IMX8MM_CLK_SAI4_IPG
- IMX8MM_CLK_SAI4_ROOT
- IMX8MM_CLK_SAI5
- IMX8MM_CLK_SAI5_IPG
- IMX8MM_CLK_SAI5_ROOT
- IMX8MM_CLK_SAI6
- IMX8MM_CLK_SAI6_IPG
- IMX8MM_CLK_SAI6_ROOT
- IMX8MM_CLK_SDMA1_ROOT
- IMX8MM_CLK_SDMA2_ROOT
- IMX8MM_CLK_SDMA3_ROOT
- IMX8MM_CLK_SNVS_ROOT
- IMX8MM_CLK_SPDIF1
- IMX8MM_CLK_SPDIF2
- IMX8MM_CLK_TMU_ROOT
- IMX8MM_CLK_UART1
- IMX8MM_CLK_UART1_ROOT
- IMX8MM_CLK_UART2
- IMX8MM_CLK_UART2_ROOT
- IMX8MM_CLK_UART3
- IMX8MM_CLK_UART3_ROOT
- IMX8MM_CLK_UART4
- IMX8MM_CLK_UART4_ROOT
- IMX8MM_CLK_USB1_CTRL_ROOT
- IMX8MM_CLK_USB_BUS
- IMX8MM_CLK_USB_CORE_REF
- IMX8MM_CLK_USB_PHY_REF
- IMX8MM_CLK_USDHC1
- IMX8MM_CLK_USDHC1_ROOT
- IMX8MM_CLK_USDHC2
- IMX8MM_CLK_USDHC2_ROOT
- IMX8MM_CLK_USDHC3
- IMX8MM_CLK_USDHC3_ROOT
- IMX8MM_CLK_VPU_BUS
- IMX8MM_CLK_VPU_CG
- IMX8MM_CLK_VPU_DEC_ROOT
- IMX8MM_CLK_VPU_DIV
- IMX8MM_CLK_VPU_G1
- IMX8MM_CLK_VPU_G1_ROOT
- IMX8MM_CLK_VPU_G2
- IMX8MM_CLK_VPU_G2_ROOT
- IMX8MM_CLK_VPU_H1
- IMX8MM_CLK_VPU_H1_ROOT
- IMX8MM_CLK_VPU_SRC
- IMX8MM_CLK_WDOG
- IMX8MM_CLK_WDOG1_ROOT
- IMX8MM_CLK_WDOG2_ROOT
- IMX8MM_CLK_WDOG3_ROOT
- IMX8MM_CLK_WRCLK
- IMX8MM_DRAM_PLL
- IMX8MM_DRAM_PLL_BYPASS
- IMX8MM_DRAM_PLL_OUT
- IMX8MM_DRAM_PLL_REF_SEL
- IMX8MM_GPU_PLL
- IMX8MM_GPU_PLL_BYPASS
- IMX8MM_GPU_PLL_OUT
- IMX8MM_GPU_PLL_REF_SEL
- IMX8MM_OSC_HDMI_CLK
- IMX8MM_SYS_PLL1
- IMX8MM_SYS_PLL1_100M
- IMX8MM_SYS_PLL1_133M
- IMX8MM_SYS_PLL1_160M
- IMX8MM_SYS_PLL1_200M
- IMX8MM_SYS_PLL1_266M
- IMX8MM_SYS_PLL1_400M
- IMX8MM_SYS_PLL1_40M
- IMX8MM_SYS_PLL1_800M
- IMX8MM_SYS_PLL1_80M
- IMX8MM_SYS_PLL1_BYPASS
- IMX8MM_SYS_PLL1_OUT
- IMX8MM_SYS_PLL1_REF_SEL
- IMX8MM_SYS_PLL2
- IMX8MM_SYS_PLL2_1000M
- IMX8MM_SYS_PLL2_100M
- IMX8MM_SYS_PLL2_125M
- IMX8MM_SYS_PLL2_166M
- IMX8MM_SYS_PLL2_200M
- IMX8MM_SYS_PLL2_250M
- IMX8MM_SYS_PLL2_333M
- IMX8MM_SYS_PLL2_500M
- IMX8MM_SYS_PLL2_50M
- IMX8MM_SYS_PLL2_BYPASS
- IMX8MM_SYS_PLL2_OUT
- IMX8MM_SYS_PLL2_REF_SEL
- IMX8MM_SYS_PLL3
- IMX8MM_SYS_PLL3_BYPASS
- IMX8MM_SYS_PLL3_OUT
- IMX8MM_SYS_PLL3_REF_SEL
- IMX8MM_VIDEO_PLL1
- IMX8MM_VIDEO_PLL1_BYPASS
- IMX8MM_VIDEO_PLL1_OUT
- IMX8MM_VIDEO_PLL1_REF_SEL
- IMX8MM_VPU_PLL
- IMX8MM_VPU_PLL_BYPASS
- IMX8MM_VPU_PLL_OUT
- IMX8MM_VPU_PLL_REF_SEL
- IMX8MN_ARM_PLL
- IMX8MN_ARM_PLL_BYPASS
- IMX8MN_ARM_PLL_OUT
- IMX8MN_ARM_PLL_REF_SEL
- IMX8MN_AUDIO_PLL1
- IMX8MN_AUDIO_PLL1_BYPASS
- IMX8MN_AUDIO_PLL1_OUT
- IMX8MN_AUDIO_PLL1_REF_SEL
- IMX8MN_AUDIO_PLL2
- IMX8MN_AUDIO_PLL2_BYPASS
- IMX8MN_AUDIO_PLL2_OUT
- IMX8MN_AUDIO_PLL2_REF_SEL
- IMX8MN_CLK_24M
- IMX8MN_CLK_32K
- IMX8MN_CLK_A53_CG
- IMX8MN_CLK_A53_DIV
- IMX8MN_CLK_A53_SRC
- IMX8MN_CLK_AHB
- IMX8MN_CLK_ARM
- IMX8MN_CLK_ASRC_ROOT
- IMX8MN_CLK_AUDIO_AHB
- IMX8MN_CLK_CAMERA_PIXEL
- IMX8MN_CLK_CAMERA_PIXEL_ROOT
- IMX8MN_CLK_CLKO1
- IMX8MN_CLK_CLKO2
- IMX8MN_CLK_CSI1_PHY_REF
- IMX8MN_CLK_CSI2_ESC
- IMX8MN_CLK_CSI2_PHY_REF
- IMX8MN_CLK_DISP_APB
- IMX8MN_CLK_DISP_APB_ROOT
- IMX8MN_CLK_DISP_AXI
- IMX8MN_CLK_DISP_AXI_ROOT
- IMX8MN_CLK_DISP_PIXEL
- IMX8MN_CLK_DISP_PIXEL_ROOT
- IMX8MN_CLK_DRAM_ALT
- IMX8MN_CLK_DRAM_ALT_ROOT
- IMX8MN_CLK_DRAM_APB
- IMX8MN_CLK_DRAM_CORE
- IMX8MN_CLK_DSI_CORE
- IMX8MN_CLK_DSI_DBI
- IMX8MN_CLK_DSI_PHY_REF
- IMX8MN_CLK_DUMMY
- IMX8MN_CLK_ECSPI1
- IMX8MN_CLK_ECSPI1_ROOT
- IMX8MN_CLK_ECSPI2
- IMX8MN_CLK_ECSPI2_ROOT
- IMX8MN_CLK_ECSPI3
- IMX8MN_CLK_ECSPI3_ROOT
- IMX8MN_CLK_END
- IMX8MN_CLK_ENET1_ROOT
- IMX8MN_CLK_ENET_AXI
- IMX8MN_CLK_ENET_PHY_REF
- IMX8MN_CLK_ENET_REF
- IMX8MN_CLK_ENET_TIMER
- IMX8MN_CLK_EXT1
- IMX8MN_CLK_EXT2
- IMX8MN_CLK_EXT3
- IMX8MN_CLK_EXT4
- IMX8MN_CLK_GIC
- IMX8MN_CLK_GPIO1_ROOT
- IMX8MN_CLK_GPIO2_ROOT
- IMX8MN_CLK_GPIO3_ROOT
- IMX8MN_CLK_GPIO4_ROOT
- IMX8MN_CLK_GPIO5_ROOT
- IMX8MN_CLK_GPU3D_ROOT
- IMX8MN_CLK_GPU_AHB
- IMX8MN_CLK_GPU_AXI
- IMX8MN_CLK_GPU_BUS_ROOT
- IMX8MN_CLK_GPU_CORE_CG
- IMX8MN_CLK_GPU_CORE_DIV
- IMX8MN_CLK_GPU_CORE_ROOT
- IMX8MN_CLK_GPU_CORE_SRC
- IMX8MN_CLK_GPU_SHADER_CG
- IMX8MN_CLK_GPU_SHADER_DIV
- IMX8MN_CLK_GPU_SHADER_SRC
- IMX8MN_CLK_I2C1
- IMX8MN_CLK_I2C1_ROOT
- IMX8MN_CLK_I2C2
- IMX8MN_CLK_I2C2_ROOT
- IMX8MN_CLK_I2C3
- IMX8MN_CLK_I2C3_ROOT
- IMX8MN_CLK_I2C4
- IMX8MN_CLK_I2C4_ROOT
- IMX8MN_CLK_IPG_AUDIO_ROOT
- IMX8MN_CLK_IPG_ROOT
- IMX8MN_CLK_MAIN_AXI
- IMX8MN_CLK_MU_ROOT
- IMX8MN_CLK_NAND
- IMX8MN_CLK_NAND_ROOT
- IMX8MN_CLK_NAND_USDHC_BUS
- IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK
- IMX8MN_CLK_NOC
- IMX8MN_CLK_OCOTP_ROOT
- IMX8MN_CLK_PDM
- IMX8MN_CLK_PDM_IPG
- IMX8MN_CLK_PDM_ROOT
- IMX8MN_CLK_PWM1
- IMX8MN_CLK_PWM1_ROOT
- IMX8MN_CLK_PWM2
- IMX8MN_CLK_PWM2_ROOT
- IMX8MN_CLK_PWM3
- IMX8MN_CLK_PWM3_ROOT
- IMX8MN_CLK_PWM4
- IMX8MN_CLK_PWM4_ROOT
- IMX8MN_CLK_QSPI
- IMX8MN_CLK_QSPI_ROOT
- IMX8MN_CLK_SAI2
- IMX8MN_CLK_SAI2_IPG
- IMX8MN_CLK_SAI2_ROOT
- IMX8MN_CLK_SAI3
- IMX8MN_CLK_SAI3_IPG
- IMX8MN_CLK_SAI3_ROOT
- IMX8MN_CLK_SAI5
- IMX8MN_CLK_SAI5_IPG
- IMX8MN_CLK_SAI5_ROOT
- IMX8MN_CLK_SAI6
- IMX8MN_CLK_SAI6_IPG
- IMX8MN_CLK_SAI6_ROOT
- IMX8MN_CLK_SAI7
- IMX8MN_CLK_SAI7_IPG
- IMX8MN_CLK_SAI7_ROOT
- IMX8MN_CLK_SDMA1_ROOT
- IMX8MN_CLK_SDMA2_ROOT
- IMX8MN_CLK_SDMA3_ROOT
- IMX8MN_CLK_SPDIF1
- IMX8MN_CLK_TMU_ROOT
- IMX8MN_CLK_UART1
- IMX8MN_CLK_UART1_ROOT
- IMX8MN_CLK_UART2
- IMX8MN_CLK_UART2_ROOT
- IMX8MN_CLK_UART3
- IMX8MN_CLK_UART3_ROOT
- IMX8MN_CLK_UART4
- IMX8MN_CLK_UART4_ROOT
- IMX8MN_CLK_USB1_CTRL_ROOT
- IMX8MN_CLK_USB_BUS
- IMX8MN_CLK_USB_CORE_REF
- IMX8MN_CLK_USB_PHY_REF
- IMX8MN_CLK_USDHC1
- IMX8MN_CLK_USDHC1_ROOT
- IMX8MN_CLK_USDHC2
- IMX8MN_CLK_USDHC2_ROOT
- IMX8MN_CLK_USDHC3
- IMX8MN_CLK_USDHC3_ROOT
- IMX8MN_CLK_WDOG
- IMX8MN_CLK_WDOG1_ROOT
- IMX8MN_CLK_WDOG2_ROOT
- IMX8MN_CLK_WDOG3_ROOT
- IMX8MN_CLK_WRCLK
- IMX8MN_DRAM_PLL
- IMX8MN_DRAM_PLL_BYPASS
- IMX8MN_DRAM_PLL_OUT
- IMX8MN_DRAM_PLL_REF_SEL
- IMX8MN_GPU_PLL
- IMX8MN_GPU_PLL_BYPASS
- IMX8MN_GPU_PLL_OUT
- IMX8MN_GPU_PLL_REF_SEL
- IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK
- IMX8MN_OSC_HDMI_CLK
- IMX8MN_SYS_PLL1
- IMX8MN_SYS_PLL1_100M
- IMX8MN_SYS_PLL1_133M
- IMX8MN_SYS_PLL1_160M
- IMX8MN_SYS_PLL1_200M
- IMX8MN_SYS_PLL1_266M
- IMX8MN_SYS_PLL1_400M
- IMX8MN_SYS_PLL1_40M
- IMX8MN_SYS_PLL1_800M
- IMX8MN_SYS_PLL1_80M
- IMX8MN_SYS_PLL1_BYPASS
- IMX8MN_SYS_PLL1_OUT
- IMX8MN_SYS_PLL1_REF_SEL
- IMX8MN_SYS_PLL2
- IMX8MN_SYS_PLL2_1000M
- IMX8MN_SYS_PLL2_100M
- IMX8MN_SYS_PLL2_125M
- IMX8MN_SYS_PLL2_166M
- IMX8MN_SYS_PLL2_200M
- IMX8MN_SYS_PLL2_250M
- IMX8MN_SYS_PLL2_333M
- IMX8MN_SYS_PLL2_500M
- IMX8MN_SYS_PLL2_50M
- IMX8MN_SYS_PLL2_BYPASS
- IMX8MN_SYS_PLL2_OUT
- IMX8MN_SYS_PLL2_REF_SEL
- IMX8MN_SYS_PLL3
- IMX8MN_SYS_PLL3_BYPASS
- IMX8MN_SYS_PLL3_OUT
- IMX8MN_SYS_PLL3_REF_SEL
- IMX8MN_VIDEO_PLL1
- IMX8MN_VIDEO_PLL1_BYPASS
- IMX8MN_VIDEO_PLL1_OUT
- IMX8MN_VIDEO_PLL1_REF_SEL
- IMX8MN_VPU_PLL
- IMX8MN_VPU_PLL_BYPASS
- IMX8MN_VPU_PLL_OUT
- IMX8MN_VPU_PLL_REF_SEL
- IMX8MQ
- IMX8MQ_ARM_PLL
- IMX8MQ_ARM_PLL_BYPASS
- IMX8MQ_ARM_PLL_OUT
- IMX8MQ_ARM_PLL_REF_DIV
- IMX8MQ_ARM_PLL_REF_SEL
- IMX8MQ_AUDIO_PLL1
- IMX8MQ_AUDIO_PLL1_BYPASS
- IMX8MQ_AUDIO_PLL1_OUT
- IMX8MQ_AUDIO_PLL1_REF_DIV
- IMX8MQ_AUDIO_PLL1_REF_SEL
- IMX8MQ_AUDIO_PLL2
- IMX8MQ_AUDIO_PLL2_BYPASS
- IMX8MQ_AUDIO_PLL2_OUT
- IMX8MQ_AUDIO_PLL2_REF_DIV
- IMX8MQ_AUDIO_PLL2_REF_SEL
- IMX8MQ_CLK_25M
- IMX8MQ_CLK_27M
- IMX8MQ_CLK_32K
- IMX8MQ_CLK_A53_CG
- IMX8MQ_CLK_A53_DIV
- IMX8MQ_CLK_A53_ROOT
- IMX8MQ_CLK_A53_SRC
- IMX8MQ_CLK_AHB
- IMX8MQ_CLK_ARM
- IMX8MQ_CLK_AUDIO_AHB
- IMX8MQ_CLK_AVC_ROOT
- IMX8MQ_CLK_CLKO1
- IMX8MQ_CLK_CLKO2
- IMX8MQ_CLK_CSI1_CORE
- IMX8MQ_CLK_CSI1_ESC
- IMX8MQ_CLK_CSI1_PHY_REF
- IMX8MQ_CLK_CSI1_ROOT
- IMX8MQ_CLK_CSI2_CORE
- IMX8MQ_CLK_CSI2_ESC
- IMX8MQ_CLK_CSI2_PHY_REF
- IMX8MQ_CLK_CSI2_ROOT
- IMX8MQ_CLK_DC_PIXEL
- IMX8MQ_CLK_DISP_APB
- IMX8MQ_CLK_DISP_APB_ROOT
- IMX8MQ_CLK_DISP_AXI
- IMX8MQ_CLK_DISP_AXI_ROOT
- IMX8MQ_CLK_DISP_DC8000
- IMX8MQ_CLK_DISP_DTRC
- IMX8MQ_CLK_DISP_ROOT
- IMX8MQ_CLK_DISP_RTRM
- IMX8MQ_CLK_DISP_RTRM_ROOT
- IMX8MQ_CLK_DRAM_ALT
- IMX8MQ_CLK_DRAM_ALT_ROOT
- IMX8MQ_CLK_DRAM_APB
- IMX8MQ_CLK_DRAM_CORE
- IMX8MQ_CLK_DRAM_ROOT
- IMX8MQ_CLK_DSI_AHB
- IMX8MQ_CLK_DSI_CORE
- IMX8MQ_CLK_DSI_DBI
- IMX8MQ_CLK_DSI_ESC
- IMX8MQ_CLK_DSI_IPG_DIV
- IMX8MQ_CLK_DSI_PHY_REF
- IMX8MQ_CLK_DUMMY
- IMX8MQ_CLK_ECSPI1
- IMX8MQ_CLK_ECSPI1_ROOT
- IMX8MQ_CLK_ECSPI2
- IMX8MQ_CLK_ECSPI2_ROOT
- IMX8MQ_CLK_ECSPI3
- IMX8MQ_CLK_ECSPI3_ROOT
- IMX8MQ_CLK_END
- IMX8MQ_CLK_ENET1_ROOT
- IMX8MQ_CLK_ENET_AXI
- IMX8MQ_CLK_ENET_PHY_REF
- IMX8MQ_CLK_ENET_REF
- IMX8MQ_CLK_ENET_TIMER
- IMX8MQ_CLK_EXT1
- IMX8MQ_CLK_EXT2
- IMX8MQ_CLK_EXT3
- IMX8MQ_CLK_EXT4
- IMX8MQ_CLK_GIC
- IMX8MQ_CLK_GPIO1_ROOT
- IMX8MQ_CLK_GPIO2_ROOT
- IMX8MQ_CLK_GPIO3_ROOT
- IMX8MQ_CLK_GPIO4_ROOT
- IMX8MQ_CLK_GPIO5_ROOT
- IMX8MQ_CLK_GPT1
- IMX8MQ_CLK_GPT1_ROOT
- IMX8MQ_CLK_GPU_AHB
- IMX8MQ_CLK_GPU_AXI
- IMX8MQ_CLK_GPU_CORE_CG
- IMX8MQ_CLK_GPU_CORE_DIV
- IMX8MQ_CLK_GPU_CORE_SRC
- IMX8MQ_CLK_GPU_ROOT
- IMX8MQ_CLK_GPU_SHADER_CG
- IMX8MQ_CLK_GPU_SHADER_DIV
- IMX8MQ_CLK_GPU_SHADER_SRC
- IMX8MQ_CLK_HDMI_PHY_ROOT
- IMX8MQ_CLK_HDMI_ROOT
- IMX8MQ_CLK_HEVC_INTER_ROOT
- IMX8MQ_CLK_HEVC_ROOT
- IMX8MQ_CLK_I2C1
- IMX8MQ_CLK_I2C1_ROOT
- IMX8MQ_CLK_I2C2
- IMX8MQ_CLK_I2C2_ROOT
- IMX8MQ_CLK_I2C3
- IMX8MQ_CLK_I2C3_ROOT
- IMX8MQ_CLK_I2C4
- IMX8MQ_CLK_I2C4_ROOT
- IMX8MQ_CLK_IPG_AUDIO_ROOT
- IMX8MQ_CLK_IPG_ROOT
- IMX8MQ_CLK_LCDIF_PIXEL
- IMX8MQ_CLK_M4_CG
- IMX8MQ_CLK_M4_DIV
- IMX8MQ_CLK_M4_ROOT
- IMX8MQ_CLK_M4_SRC
- IMX8MQ_CLK_MAIN_AXI
- IMX8MQ_CLK_MU_ROOT
- IMX8MQ_CLK_NAND
- IMX8MQ_CLK_NAND_USDHC_BUS
- IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK
- IMX8MQ_CLK_NOC
- IMX8MQ_CLK_NOC_APB
- IMX8MQ_CLK_OCOTP_ROOT
- IMX8MQ_CLK_PCIE1_AUX
- IMX8MQ_CLK_PCIE1_CTRL
- IMX8MQ_CLK_PCIE1_PHY
- IMX8MQ_CLK_PCIE1_ROOT
- IMX8MQ_CLK_PCIE2_AUX
- IMX8MQ_CLK_PCIE2_CTRL
- IMX8MQ_CLK_PCIE2_PHY
- IMX8MQ_CLK_PCIE2_ROOT
- IMX8MQ_CLK_PWM1
- IMX8MQ_CLK_PWM1_ROOT
- IMX8MQ_CLK_PWM2
- IMX8MQ_CLK_PWM2_ROOT
- IMX8MQ_CLK_PWM3
- IMX8MQ_CLK_PWM3_ROOT
- IMX8MQ_CLK_PWM4
- IMX8MQ_CLK_PWM4_ROOT
- IMX8MQ_CLK_QSPI
- IMX8MQ_CLK_QSPI_ROOT
- IMX8MQ_CLK_RAWNAND_ROOT
- IMX8MQ_CLK_SAI1
- IMX8MQ_CLK_SAI1_IPG
- IMX8MQ_CLK_SAI1_ROOT
- IMX8MQ_CLK_SAI2
- IMX8MQ_CLK_SAI2_IPG
- IMX8MQ_CLK_SAI2_ROOT
- IMX8MQ_CLK_SAI3
- IMX8MQ_CLK_SAI3_IPG
- IMX8MQ_CLK_SAI3_ROOT
- IMX8MQ_CLK_SAI4
- IMX8MQ_CLK_SAI4_IPG
- IMX8MQ_CLK_SAI4_ROOT
- IMX8MQ_CLK_SAI5
- IMX8MQ_CLK_SAI5_IPG
- IMX8MQ_CLK_SAI5_ROOT
- IMX8MQ_CLK_SAI6
- IMX8MQ_CLK_SAI6_IPG
- IMX8MQ_CLK_SAI6_ROOT
- IMX8MQ_CLK_SDMA1_ROOT
- IMX8MQ_CLK_SDMA2_ROOT
- IMX8MQ_CLK_SNVS_ROOT
- IMX8MQ_CLK_SPDIF1
- IMX8MQ_CLK_SPDIF2
- IMX8MQ_CLK_TMU_ROOT
- IMX8MQ_CLK_UART1
- IMX8MQ_CLK_UART1_ROOT
- IMX8MQ_CLK_UART2
- IMX8MQ_CLK_UART2_ROOT
- IMX8MQ_CLK_UART3
- IMX8MQ_CLK_UART3_ROOT
- IMX8MQ_CLK_UART4
- IMX8MQ_CLK_UART4_ROOT
- IMX8MQ_CLK_USB1_CTRL_ROOT
- IMX8MQ_CLK_USB1_PHY_ROOT
- IMX8MQ_CLK_USB2_CTRL_ROOT
- IMX8MQ_CLK_USB2_PHY_ROOT
- IMX8MQ_CLK_USB_BUS
- IMX8MQ_CLK_USB_CORE_REF
- IMX8MQ_CLK_USB_PHY_REF
- IMX8MQ_CLK_USDHC1
- IMX8MQ_CLK_USDHC1_ROOT
- IMX8MQ_CLK_USDHC2
- IMX8MQ_CLK_USDHC2_ROOT
- IMX8MQ_CLK_VP9_ROOT
- IMX8MQ_CLK_VPU_BUS
- IMX8MQ_CLK_VPU_CG
- IMX8MQ_CLK_VPU_DEC_ROOT
- IMX8MQ_CLK_VPU_DIV
- IMX8MQ_CLK_VPU_G1
- IMX8MQ_CLK_VPU_G1_ROOT
- IMX8MQ_CLK_VPU_G2
- IMX8MQ_CLK_VPU_G2_ROOT
- IMX8MQ_CLK_VPU_SRC
- IMX8MQ_CLK_WDOG
- IMX8MQ_CLK_WDOG1_ROOT
- IMX8MQ_CLK_WDOG2_ROOT
- IMX8MQ_CLK_WDOG3_ROOT
- IMX8MQ_CLK_WRCLK
- IMX8MQ_DRAM_PLL1
- IMX8MQ_DRAM_PLL1_OUT
- IMX8MQ_DRAM_PLL1_OUT_DIV
- IMX8MQ_DRAM_PLL1_REF_DIV
- IMX8MQ_DRAM_PLL1_REF_SEL
- IMX8MQ_DRAM_PLL2
- IMX8MQ_DRAM_PLL2_DIV
- IMX8MQ_DRAM_PLL2_OUT
- IMX8MQ_DRAM_PLL_OUT
- IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE
- IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN
- IMX8MQ_GPR_PCIE_REF_USE_PAD
- IMX8MQ_GPT_3M_CLK
- IMX8MQ_GPU_PLL
- IMX8MQ_GPU_PLL_BYPASS
- IMX8MQ_GPU_PLL_OUT
- IMX8MQ_GPU_PLL_REF_DIV
- IMX8MQ_GPU_PLL_REF_SEL
- IMX8MQ_PCIE2_BASE_ADDR
- IMX8MQ_RESET_A53_CORE_POR_RESET0
- IMX8MQ_RESET_A53_CORE_POR_RESET1
- IMX8MQ_RESET_A53_CORE_POR_RESET2
- IMX8MQ_RESET_A53_CORE_POR_RESET3
- IMX8MQ_RESET_A53_CORE_RESET0
- IMX8MQ_RESET_A53_CORE_RESET1
- IMX8MQ_RESET_A53_CORE_RESET2
- IMX8MQ_RESET_A53_CORE_RESET3
- IMX8MQ_RESET_A53_DBG_RESET0
- IMX8MQ_RESET_A53_DBG_RESET1
- IMX8MQ_RESET_A53_DBG_RESET2
- IMX8MQ_RESET_A53_DBG_RESET3
- IMX8MQ_RESET_A53_ETM_RESET0
- IMX8MQ_RESET_A53_ETM_RESET1
- IMX8MQ_RESET_A53_ETM_RESET2
- IMX8MQ_RESET_A53_ETM_RESET3
- IMX8MQ_RESET_A53_L2RESET
- IMX8MQ_RESET_A53_SOC_DBG_RESET
- IMX8MQ_RESET_DDRC1_CORE_RESET
- IMX8MQ_RESET_DDRC1_PHY_RESET
- IMX8MQ_RESET_DDRC1_PRST
- IMX8MQ_RESET_DDRC2_CORE_RESET
- IMX8MQ_RESET_DDRC2_PHY_RESET
- IMX8MQ_RESET_DDRC2_PRST
- IMX8MQ_RESET_DISP_RESET
- IMX8MQ_RESET_GPU_RESET
- IMX8MQ_RESET_HDMI_PHY_APB_RESET
- IMX8MQ_RESET_MIPI_CSI1_CORE_RESET
- IMX8MQ_RESET_MIPI_CSI1_ESC_RESET
- IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET
- IMX8MQ_RESET_MIPI_CSI2_CORE_RESET
- IMX8MQ_RESET_MIPI_CSI2_ESC_RESET
- IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET
- IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N
- IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N
- IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N
- IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N
- IMX8MQ_RESET_MIPI_DSI_RESET_N
- IMX8MQ_RESET_NUM
- IMX8MQ_RESET_OTG1_PHY_RESET
- IMX8MQ_RESET_OTG2_PHY_RESET
- IMX8MQ_RESET_PCIE2_CTRL_APPS_EN
- IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF
- IMX8MQ_RESET_PCIEPHY
- IMX8MQ_RESET_PCIEPHY2
- IMX8MQ_RESET_PCIEPHY2_PERST
- IMX8MQ_RESET_PCIEPHY_PERST
- IMX8MQ_RESET_PCIE_CTRL_APPS_EN
- IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF
- IMX8MQ_RESET_SW_NON_SCLR_M4C_RST
- IMX8MQ_RESET_VPU_RESET
- IMX8MQ_SW_INFO_B1
- IMX8MQ_SW_MAGIC_B1
- IMX8MQ_SYS1_PLL1
- IMX8MQ_SYS1_PLL1_OUT
- IMX8MQ_SYS1_PLL1_OUT_DIV
- IMX8MQ_SYS1_PLL1_REF_DIV
- IMX8MQ_SYS1_PLL1_REF_SEL
- IMX8MQ_SYS1_PLL2
- IMX8MQ_SYS1_PLL2_DIV
- IMX8MQ_SYS1_PLL2_OUT
- IMX8MQ_SYS1_PLL_100M
- IMX8MQ_SYS1_PLL_133M
- IMX8MQ_SYS1_PLL_160M
- IMX8MQ_SYS1_PLL_200M
- IMX8MQ_SYS1_PLL_266M
- IMX8MQ_SYS1_PLL_400M
- IMX8MQ_SYS1_PLL_40M
- IMX8MQ_SYS1_PLL_800M
- IMX8MQ_SYS1_PLL_80M
- IMX8MQ_SYS1_PLL_OUT
- IMX8MQ_SYS2_PLL1
- IMX8MQ_SYS2_PLL1_OUT
- IMX8MQ_SYS2_PLL1_OUT_DIV
- IMX8MQ_SYS2_PLL1_REF_DIV
- IMX8MQ_SYS2_PLL1_REF_SEL
- IMX8MQ_SYS2_PLL2
- IMX8MQ_SYS2_PLL2_DIV
- IMX8MQ_SYS2_PLL2_OUT
- IMX8MQ_SYS2_PLL_1000M
- IMX8MQ_SYS2_PLL_100M
- IMX8MQ_SYS2_PLL_125M
- IMX8MQ_SYS2_PLL_166M
- IMX8MQ_SYS2_PLL_200M
- IMX8MQ_SYS2_PLL_250M
- IMX8MQ_SYS2_PLL_333M
- IMX8MQ_SYS2_PLL_500M
- IMX8MQ_SYS2_PLL_50M
- IMX8MQ_SYS2_PLL_OUT
- IMX8MQ_SYS3_PLL1
- IMX8MQ_SYS3_PLL1_OUT
- IMX8MQ_SYS3_PLL1_OUT_DIV
- IMX8MQ_SYS3_PLL1_REF_DIV
- IMX8MQ_SYS3_PLL1_REF_SEL
- IMX8MQ_SYS3_PLL2
- IMX8MQ_SYS3_PLL2_DIV
- IMX8MQ_SYS3_PLL2_OUT
- IMX8MQ_SYS3_PLL_OUT
- IMX8MQ_VIDEO2_PLL_OUT
- IMX8MQ_VIDEO_PLL1
- IMX8MQ_VIDEO_PLL1_BYPASS
- IMX8MQ_VIDEO_PLL1_OUT
- IMX8MQ_VIDEO_PLL1_REF_DIV
- IMX8MQ_VIDEO_PLL1_REF_SEL
- IMX8MQ_VPU_PLL
- IMX8MQ_VPU_PLL_BYPASS
- IMX8MQ_VPU_PLL_OUT
- IMX8MQ_VPU_PLL_REF_DIV
- IMX8MQ_VPU_PLL_REF_SEL
- IMX8M_DDR1_A53_DOMAIN
- IMX8M_DDR1_SW_Pxx_REQ
- IMX8M_DDR2_A53_DOMAIN
- IMX8M_DDR2_SW_Pxx_REQ
- IMX8M_DISP_A53_DOMAIN
- IMX8M_DISP_HSK_PWRDNREQN
- IMX8M_DISP_SW_Pxx_REQ
- IMX8M_GPU_A53_DOMAIN
- IMX8M_GPU_HSK_PWRDNREQN
- IMX8M_GPU_SW_Pxx_REQ
- IMX8M_HDMI_A53_DOMAIN
- IMX8M_HDMI_SW_Pxx_REQ
- IMX8M_MIPI_A53_DOMAIN
- IMX8M_MIPI_CSI1_A53_DOMAIN
- IMX8M_MIPI_CSI1_SW_Pxx_REQ
- IMX8M_MIPI_CSI2_A53_DOMAIN
- IMX8M_MIPI_CSI2_SW_Pxx_REQ
- IMX8M_MIPI_SW_Pxx_REQ
- IMX8M_OTG1_A53_DOMAIN
- IMX8M_OTG1_SW_Pxx_REQ
- IMX8M_OTG2_A53_DOMAIN
- IMX8M_OTG2_SW_Pxx_REQ
- IMX8M_PCIE1_A53_DOMAIN
- IMX8M_PCIE1_SW_Pxx_REQ
- IMX8M_PCIE2_A53_DOMAIN
- IMX8M_PCIE2_SW_Pxx_REQ
- IMX8M_PGC_DDR1
- IMX8M_PGC_DISP
- IMX8M_PGC_GPU
- IMX8M_PGC_MIPI
- IMX8M_PGC_MIPI_CSI1
- IMX8M_PGC_MIPI_CSI2
- IMX8M_PGC_OTG1
- IMX8M_PGC_OTG2
- IMX8M_PGC_PCIE1
- IMX8M_PGC_PCIE2
- IMX8M_PGC_VPU
- IMX8M_POWER_DOMAIN_DDR1
- IMX8M_POWER_DOMAIN_DISP
- IMX8M_POWER_DOMAIN_GPU
- IMX8M_POWER_DOMAIN_MIPI
- IMX8M_POWER_DOMAIN_MIPI_CSI1
- IMX8M_POWER_DOMAIN_MIPI_CSI2
- IMX8M_POWER_DOMAIN_PCIE1
- IMX8M_POWER_DOMAIN_PCIE2
- IMX8M_POWER_DOMAIN_USB_OTG1
- IMX8M_POWER_DOMAIN_USB_OTG2
- IMX8M_POWER_DOMAIN_VPU
- IMX8M_VPU_A53_DOMAIN
- IMX8M_VPU_HSK_PWRDNREQN
- IMX8M_VPU_SW_Pxx_REQ
- IMX8QM
- IMX8QM_ADC_IN0
- IMX8QM_ADC_IN0_DMA_ADC0_IN0
- IMX8QM_ADC_IN0_LSIO_GPIO3_IO18
- IMX8QM_ADC_IN0_LSIO_KPP0_COL0
- IMX8QM_ADC_IN1
- IMX8QM_ADC_IN1_DMA_ADC0_IN1
- IMX8QM_ADC_IN1_LSIO_GPIO3_IO19
- IMX8QM_ADC_IN1_LSIO_KPP0_COL1
- IMX8QM_ADC_IN2
- IMX8QM_ADC_IN2_DMA_ADC0_IN2
- IMX8QM_ADC_IN2_LSIO_GPIO3_IO20
- IMX8QM_ADC_IN2_LSIO_KPP0_COL2
- IMX8QM_ADC_IN3
- IMX8QM_ADC_IN3_DMA_ADC0_IN3
- IMX8QM_ADC_IN3_DMA_SPI1_SCK
- IMX8QM_ADC_IN3_LSIO_GPIO3_IO21
- IMX8QM_ADC_IN3_LSIO_KPP0_COL3
- IMX8QM_ADC_IN4
- IMX8QM_ADC_IN4_DMA_ADC1_IN0
- IMX8QM_ADC_IN4_DMA_SPI1_SDO
- IMX8QM_ADC_IN4_LSIO_GPIO3_IO22
- IMX8QM_ADC_IN4_LSIO_KPP0_ROW0
- IMX8QM_ADC_IN5
- IMX8QM_ADC_IN5_DMA_ADC1_IN1
- IMX8QM_ADC_IN5_DMA_SPI1_SDI
- IMX8QM_ADC_IN5_LSIO_GPIO3_IO23
- IMX8QM_ADC_IN5_LSIO_KPP0_ROW1
- IMX8QM_ADC_IN6
- IMX8QM_ADC_IN6_DMA_ADC1_IN2
- IMX8QM_ADC_IN6_DMA_SPI1_CS0
- IMX8QM_ADC_IN6_LSIO_GPIO3_IO24
- IMX8QM_ADC_IN6_LSIO_KPP0_ROW2
- IMX8QM_ADC_IN7
- IMX8QM_ADC_IN7_DMA_ADC1_IN3
- IMX8QM_ADC_IN7_DMA_SPI1_CS1
- IMX8QM_ADC_IN7_LSIO_GPIO3_IO25
- IMX8QM_ADC_IN7_LSIO_KPP0_ROW3
- IMX8QM_CALIBRATION_0_HSIC
- IMX8QM_CALIBRATION_1_HSIC
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3
- IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP
- IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO
- IMX8QM_COMP_CTL_GPIO_3V3_USB3IO
- IMX8QM_CSR_MISC_OFFSET
- IMX8QM_CSR_PCIEA_OFFSET
- IMX8QM_CSR_PCIEB_OFFSET
- IMX8QM_CSR_PCIE_CTRL2_OFFSET
- IMX8QM_CSR_PHYX1_OFFSET
- IMX8QM_CSR_PHYX2_OFFSET
- IMX8QM_CSR_PHYX_STTS0_OFFSET
- IMX8QM_CSR_SATA_OFFSET
- IMX8QM_CTL_NAND_DQS_P_N
- IMX8QM_CTL_NAND_RE_P_N
- IMX8QM_CTRL_BUTTON_RST_N
- IMX8QM_CTRL_LTSSM_ENABLE
- IMX8QM_CTRL_POWER_UP_RST_N
- IMX8QM_EMMC0_CLK
- IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK
- IMX8QM_EMMC0_CLK_CONN_NAND_READY_B
- IMX8QM_EMMC0_CMD
- IMX8QM_EMMC0_CMD_AUD_MQS_R
- IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD
- IMX8QM_EMMC0_CMD_CONN_NAND_DQS
- IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03
- IMX8QM_EMMC0_DATA0
- IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0
- IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00
- IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04
- IMX8QM_EMMC0_DATA1
- IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1
- IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01
- IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05
- IMX8QM_EMMC0_DATA2
- IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2
- IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02
- IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06
- IMX8QM_EMMC0_DATA3
- IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3
- IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03
- IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07
- IMX8QM_EMMC0_DATA4
- IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4
- IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04
- IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08
- IMX8QM_EMMC0_DATA5
- IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5
- IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05
- IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09
- IMX8QM_EMMC0_DATA6
- IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6
- IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06
- IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10
- IMX8QM_EMMC0_DATA7
- IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7
- IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07
- IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11
- IMX8QM_EMMC0_RESET_B
- IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B
- IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B
- IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT
- IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13
- IMX8QM_EMMC0_STROBE
- IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE
- IMX8QM_EMMC0_STROBE_CONN_NAND_CLE
- IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12
- IMX8QM_ENET0_MDC
- IMX8QM_ENET0_MDC_CONN_ENET0_MDC
- IMX8QM_ENET0_MDC_DMA_I2C4_SCL
- IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14
- IMX8QM_ENET0_MDIO
- IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO
- IMX8QM_ENET0_MDIO_DMA_I2C4_SDA
- IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13
- IMX8QM_ENET0_REFCLK_125M_25M
- IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS
- IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M
- IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15
- IMX8QM_ENET0_RGMII_RXC
- IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
- IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B
- IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04
- IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA
- IMX8QM_ENET0_RGMII_RXD0
- IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
- IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06
- IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC
- IMX8QM_ENET0_RGMII_RXD1
- IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
- IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07
- IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA
- IMX8QM_ENET0_RGMII_RXD2
- IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
- IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER
- IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08
- IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK
- IMX8QM_ENET0_RGMII_RXD3
- IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
- IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX
- IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09
- IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK
- IMX8QM_ENET0_RGMII_RX_CTL
- IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
- IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05
- IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID
- IMX8QM_ENET0_RGMII_TXC
- IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN
- IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT
- IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
- IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30
- IMX8QM_ENET0_RGMII_TXD0
- IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
- IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00
- IMX8QM_ENET0_RGMII_TXD1
- IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
- IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01
- IMX8QM_ENET0_RGMII_TXD2
- IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
- IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX
- IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02
- IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID
- IMX8QM_ENET0_RGMII_TXD3
- IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
- IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B
- IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03
- IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC
- IMX8QM_ENET0_RGMII_TX_CTL
- IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
- IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31
- IMX8QM_ENET1_MDC
- IMX8QM_ENET1_MDC_CONN_ENET1_MDC
- IMX8QM_ENET1_MDC_DMA_I2C4_SCL
- IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18
- IMX8QM_ENET1_MDIO
- IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO
- IMX8QM_ENET1_MDIO_DMA_I2C4_SDA
- IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17
- IMX8QM_ENET1_REFCLK_125M_25M
- IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS
- IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M
- IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16
- IMX8QM_ENET1_RGMII_RXC
- IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC
- IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B
- IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16
- IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA
- IMX8QM_ENET1_RGMII_RXD0
- IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0
- IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18
- IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC
- IMX8QM_ENET1_RGMII_RXD1
- IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1
- IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19
- IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA
- IMX8QM_ENET1_RGMII_RXD2
- IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2
- IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER
- IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20
- IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK
- IMX8QM_ENET1_RGMII_RXD3
- IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3
- IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX
- IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21
- IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK
- IMX8QM_ENET1_RGMII_RX_CTL
- IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL
- IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17
- IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID
- IMX8QM_ENET1_RGMII_TXC
- IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN
- IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT
- IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC
- IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10
- IMX8QM_ENET1_RGMII_TXD0
- IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0
- IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12
- IMX8QM_ENET1_RGMII_TXD1
- IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1
- IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13
- IMX8QM_ENET1_RGMII_TXD2
- IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2
- IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX
- IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14
- IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID
- IMX8QM_ENET1_RGMII_TXD3
- IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3
- IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B
- IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15
- IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC
- IMX8QM_ENET1_RGMII_TX_CTL
- IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL
- IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11
- IMX8QM_ESAI0_FSR
- IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR
- IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22
- IMX8QM_ESAI0_FST
- IMX8QM_ESAI0_FST_AUD_ESAI0_FST
- IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23
- IMX8QM_ESAI0_SCKR
- IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR
- IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24
- IMX8QM_ESAI0_SCKT
- IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT
- IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25
- IMX8QM_ESAI0_TX0
- IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0
- IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26
- IMX8QM_ESAI0_TX1
- IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1
- IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27
- IMX8QM_ESAI0_TX2_RX3
- IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3
- IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28
- IMX8QM_ESAI0_TX3_RX2
- IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2
- IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29
- IMX8QM_ESAI0_TX4_RX1
- IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1
- IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30
- IMX8QM_ESAI0_TX5_RX0
- IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0
- IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31
- IMX8QM_ESAI1_FSR
- IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR
- IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04
- IMX8QM_ESAI1_FST
- IMX8QM_ESAI1_FST_AUD_ESAI1_FST
- IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK
- IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05
- IMX8QM_ESAI1_SCKR
- IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR
- IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06
- IMX8QM_ESAI1_SCKT
- IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT
- IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC
- IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK
- IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07
- IMX8QM_ESAI1_TX0
- IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0
- IMX8QM_ESAI1_TX0_AUD_SAI2_RXD
- IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX
- IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08
- IMX8QM_ESAI1_TX1
- IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1
- IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS
- IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX
- IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09
- IMX8QM_ESAI1_TX2_RX3
- IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3
- IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX
- IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10
- IMX8QM_ESAI1_TX3_RX2
- IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2
- IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX
- IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11
- IMX8QM_ESAI1_TX4_RX1
- IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1
- IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12
- IMX8QM_ESAI1_TX5_RX0
- IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0
- IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13
- IMX8QM_FLEXCAN0_RX
- IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX
- IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29
- IMX8QM_FLEXCAN0_TX
- IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX
- IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30
- IMX8QM_FLEXCAN1_RX
- IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX
- IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31
- IMX8QM_FLEXCAN1_TX
- IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX
- IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00
- IMX8QM_FLEXCAN2_RX
- IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX
- IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01
- IMX8QM_FLEXCAN2_TX
- IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX
- IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02
- IMX8QM_GPT0_CAPTURE
- IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA
- IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15
- IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE
- IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5
- IMX8QM_GPT0_CLK
- IMX8QM_GPT0_CLK_DMA_I2C1_SCL
- IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14
- IMX8QM_GPT0_CLK_LSIO_GPT0_CLK
- IMX8QM_GPT0_CLK_LSIO_KPP0_COL4
- IMX8QM_GPT0_COMPARE
- IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16
- IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE
- IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6
- IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT
- IMX8QM_GPT1_CAPTURE
- IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA
- IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18
- IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE
- IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4
- IMX8QM_GPT1_CLK
- IMX8QM_GPT1_CLK_DMA_I2C2_SCL
- IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17
- IMX8QM_GPT1_CLK_LSIO_GPT1_CLK
- IMX8QM_GPT1_CLK_LSIO_KPP0_COL7
- IMX8QM_GPT1_COMPARE
- IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19
- IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE
- IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5
- IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT
- IMX8QM_HDMI_TX0_TS_SCL
- IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL
- IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL
- IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02
- IMX8QM_HDMI_TX0_TS_SDA
- IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA
- IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA
- IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03
- IMX8QM_LPCG_PHYX2_OFFSET
- IMX8QM_LPCG_PHYX2_PCLK0_MASK
- IMX8QM_LPCG_PHYX2_PCLK1_MASK
- IMX8QM_LVDS0_GPIO00
- IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04
- IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00
- IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT
- IMX8QM_LVDS0_GPIO01
- IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05
- IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01
- IMX8QM_LVDS0_I2C0_SCL
- IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06
- IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02
- IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL
- IMX8QM_LVDS0_I2C0_SDA
- IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07
- IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03
- IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA
- IMX8QM_LVDS0_I2C1_SCL
- IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX
- IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08
- IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL
- IMX8QM_LVDS0_I2C1_SDA
- IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX
- IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09
- IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA
- IMX8QM_LVDS1_GPIO00
- IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10
- IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00
- IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT
- IMX8QM_LVDS1_GPIO01
- IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11
- IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01
- IMX8QM_LVDS1_I2C0_SCL
- IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12
- IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02
- IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL
- IMX8QM_LVDS1_I2C0_SDA
- IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13
- IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03
- IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA
- IMX8QM_LVDS1_I2C1_SCL
- IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX
- IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14
- IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL
- IMX8QM_LVDS1_I2C1_SDA
- IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX
- IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15
- IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA
- IMX8QM_M40_GPIO0_00
- IMX8QM_M40_GPIO0_00_DMA_UART4_RX
- IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08
- IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00
- IMX8QM_M40_GPIO0_00_M40_TPM0_CH0
- IMX8QM_M40_GPIO0_01
- IMX8QM_M40_GPIO0_01_DMA_UART4_TX
- IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09
- IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01
- IMX8QM_M40_GPIO0_01_M40_TPM0_CH1
- IMX8QM_M40_I2C0_SCL
- IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06
- IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02
- IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL
- IMX8QM_M40_I2C0_SCL_M40_UART0_RX
- IMX8QM_M40_I2C0_SDA
- IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07
- IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03
- IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA
- IMX8QM_M40_I2C0_SDA_M40_UART0_TX
- IMX8QM_M41_GPIO0_00
- IMX8QM_M41_GPIO0_00_DMA_UART3_RX
- IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12
- IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00
- IMX8QM_M41_GPIO0_00_M41_TPM0_CH0
- IMX8QM_M41_GPIO0_01
- IMX8QM_M41_GPIO0_01_DMA_UART3_TX
- IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13
- IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01
- IMX8QM_M41_GPIO0_01_M41_TPM0_CH1
- IMX8QM_M41_I2C0_SCL
- IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10
- IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02
- IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL
- IMX8QM_M41_I2C0_SCL_M41_UART0_RX
- IMX8QM_M41_I2C0_SDA
- IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11
- IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03
- IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA
- IMX8QM_M41_I2C0_SDA_M41_UART0_TX
- IMX8QM_MCLK_IN0
- IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0
- IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK
- IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK
- IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00
- IMX8QM_MCLK_OUT0
- IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0
- IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK
- IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK
- IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01
- IMX8QM_MIPI_CSI0_GPIO0_00
- IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL
- IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27
- IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00
- IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL
- IMX8QM_MIPI_CSI0_GPIO0_01
- IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA
- IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28
- IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01
- IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA
- IMX8QM_MIPI_CSI0_I2C0_SCL
- IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25
- IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL
- IMX8QM_MIPI_CSI0_I2C0_SDA
- IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26
- IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA
- IMX8QM_MIPI_CSI0_MCLK_OUT
- IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24
- IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT
- IMX8QM_MIPI_CSI1_GPIO0_00
- IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX
- IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30
- IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00
- IMX8QM_MIPI_CSI1_GPIO0_01
- IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX
- IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31
- IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01
- IMX8QM_MIPI_CSI1_I2C0_SCL
- IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00
- IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL
- IMX8QM_MIPI_CSI1_I2C0_SDA
- IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01
- IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA
- IMX8QM_MIPI_CSI1_MCLK_OUT
- IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29
- IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT
- IMX8QM_MIPI_DSI0_GPIO0_00
- IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18
- IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00
- IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT
- IMX8QM_MIPI_DSI0_GPIO0_01
- IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19
- IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01
- IMX8QM_MIPI_DSI0_I2C0_SCL
- IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16
- IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL
- IMX8QM_MIPI_DSI0_I2C0_SDA
- IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17
- IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA
- IMX8QM_MIPI_DSI1_GPIO0_00
- IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22
- IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00
- IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT
- IMX8QM_MIPI_DSI1_GPIO0_01
- IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23
- IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01
- IMX8QM_MIPI_DSI1_I2C0_SCL
- IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20
- IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL
- IMX8QM_MIPI_DSI1_I2C0_SDA
- IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21
- IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA
- IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0
- IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1
- IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0
- IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1
- IMX8QM_MISC_IOB_RXENA
- IMX8QM_MISC_IOB_TXENA
- IMX8QM_MISC_PHYX1_EPCS_SEL
- IMX8QM_MLB_CLK
- IMX8QM_MLB_CLK_AUD_SAI3_RXFS
- IMX8QM_MLB_CLK_CONN_MLB_CLK
- IMX8QM_MLB_CLK_LSIO_GPIO3_IO27
- IMX8QM_MLB_DATA
- IMX8QM_MLB_DATA_AUD_SAI3_RXD
- IMX8QM_MLB_DATA_CONN_MLB_DATA
- IMX8QM_MLB_DATA_LSIO_GPIO3_IO28
- IMX8QM_MLB_SIG
- IMX8QM_MLB_SIG_AUD_SAI3_RXC
- IMX8QM_MLB_SIG_CONN_MLB_SIG
- IMX8QM_MLB_SIG_LSIO_GPIO3_IO26
- IMX8QM_PCIE_CTRL0_CLKREQ_B
- IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B
- IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27
- IMX8QM_PCIE_CTRL0_PERST_B
- IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
- IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29
- IMX8QM_PCIE_CTRL0_WAKE_B
- IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B
- IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28
- IMX8QM_PCIE_CTRL1_CLKREQ_B
- IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC
- IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA
- IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B
- IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30
- IMX8QM_PCIE_CTRL1_PERST_B
- IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR
- IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL
- IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B
- IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00
- IMX8QM_PCIE_CTRL1_WAKE_B
- IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR
- IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL
- IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B
- IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31
- IMX8QM_PHY_APB_RSTN_0
- IMX8QM_PHY_MODE_MASK
- IMX8QM_PHY_MODE_SATA
- IMX8QM_PHY_PIPE_RSTN_0
- IMX8QM_PHY_PIPE_RSTN_1
- IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0
- IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1
- IMX8QM_PMIC_EARLY_WARNING
- IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING
- IMX8QM_PMIC_I2C_SCL
- IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL
- IMX8QM_PMIC_I2C_SDA
- IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA
- IMX8QM_PMIC_INT_B
- IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B
- IMX8QM_QSPI0A_DATA0
- IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0
- IMX8QM_QSPI0A_DATA1
- IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1
- IMX8QM_QSPI0A_DATA2
- IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2
- IMX8QM_QSPI0A_DATA3
- IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3
- IMX8QM_QSPI0A_DQS
- IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS
- IMX8QM_QSPI0A_SCLK
- IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK
- IMX8QM_QSPI0A_SS0_B
- IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B
- IMX8QM_QSPI0A_SS1_B
- IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2
- IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B
- IMX8QM_QSPI0B_DATA0
- IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0
- IMX8QM_QSPI0B_DATA1
- IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1
- IMX8QM_QSPI0B_DATA2
- IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2
- IMX8QM_QSPI0B_DATA3
- IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3
- IMX8QM_QSPI0B_DQS
- IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS
- IMX8QM_QSPI0B_SCLK
- IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK
- IMX8QM_QSPI0B_SS0_B
- IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B
- IMX8QM_QSPI0B_SS1_B
- IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2
- IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B
- IMX8QM_QSPI1A_DATA0
- IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26
- IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0
- IMX8QM_QSPI1A_DATA1
- IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC
- IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA
- IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25
- IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1
- IMX8QM_QSPI1A_DATA2
- IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR
- IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL
- IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24
- IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2
- IMX8QM_QSPI1A_DATA3
- IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC
- IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA
- IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23
- IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3
- IMX8QM_QSPI1A_DQS
- IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22
- IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS
- IMX8QM_QSPI1A_SCLK
- IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21
- IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK
- IMX8QM_QSPI1A_SS0_B
- IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19
- IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B
- IMX8QM_QSPI1A_SS1_B
- IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20
- IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2
- IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B
- IMX8QM_SAI1_RXC
- IMX8QM_SAI1_RXC_AUD_SAI0_TXD
- IMX8QM_SAI1_RXC_AUD_SAI1_RXC
- IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12
- IMX8QM_SAI1_RXD
- IMX8QM_SAI1_RXD_AUD_SAI0_TXFS
- IMX8QM_SAI1_RXD_AUD_SAI1_RXD
- IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13
- IMX8QM_SAI1_RXFS
- IMX8QM_SAI1_RXFS_AUD_SAI0_RXD
- IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS
- IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14
- IMX8QM_SAI1_TXC
- IMX8QM_SAI1_TXC_AUD_SAI0_TXC
- IMX8QM_SAI1_TXC_AUD_SAI1_TXC
- IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15
- IMX8QM_SAI1_TXD
- IMX8QM_SAI1_TXD_AUD_SAI1_RXC
- IMX8QM_SAI1_TXD_AUD_SAI1_TXD
- IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16
- IMX8QM_SAI1_TXFS
- IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS
- IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS
- IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17
- IMX8QM_SATA_CTRL_EPCS_PHYRESET_N
- IMX8QM_SATA_CTRL_RESET_N
- IMX8QM_SATA_PHY_IMPED_RATIO_85OHM
- IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET
- IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET
- IMX8QM_SCU_BOOT_MODE0
- IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0
- IMX8QM_SCU_BOOT_MODE1
- IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1
- IMX8QM_SCU_BOOT_MODE2
- IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2
- IMX8QM_SCU_BOOT_MODE3
- IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3
- IMX8QM_SCU_BOOT_MODE4
- IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4
- IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL
- IMX8QM_SCU_BOOT_MODE5
- IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5
- IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA
- IMX8QM_SCU_GPIO0_00
- IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28
- IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00
- IMX8QM_SCU_GPIO0_00_SCU_UART0_RX
- IMX8QM_SCU_GPIO0_01
- IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29
- IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01
- IMX8QM_SCU_GPIO0_01_SCU_UART0_TX
- IMX8QM_SCU_GPIO0_02
- IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30
- IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02
- IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON
- IMX8QM_SCU_GPIO0_03
- IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31
- IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03
- IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON
- IMX8QM_SCU_GPIO0_04
- IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00
- IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04
- IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON
- IMX8QM_SCU_GPIO0_05
- IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01
- IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05
- IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON
- IMX8QM_SCU_GPIO0_06
- IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02
- IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06
- IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0
- IMX8QM_SCU_GPIO0_07
- IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03
- IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K
- IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07
- IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1
- IMX8QM_SCU_PMIC_MEMC_ON
- IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON
- IMX8QM_SCU_WDOG_OUT
- IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT
- IMX8QM_SIM0_CLK
- IMX8QM_SIM0_CLK_DMA_SIM0_CLK
- IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00
- IMX8QM_SIM0_GPIO0_00
- IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN
- IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05
- IMX8QM_SIM0_IO
- IMX8QM_SIM0_IO_DMA_SIM0_IO
- IMX8QM_SIM0_IO_LSIO_GPIO0_IO02
- IMX8QM_SIM0_PD
- IMX8QM_SIM0_PD_DMA_I2C3_SCL
- IMX8QM_SIM0_PD_DMA_SIM0_PD
- IMX8QM_SIM0_PD_LSIO_GPIO0_IO03
- IMX8QM_SIM0_POWER_EN
- IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA
- IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN
- IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04
- IMX8QM_SIM0_RST
- IMX8QM_SIM0_RST_DMA_SIM0_RST
- IMX8QM_SIM0_RST_LSIO_GPIO0_IO01
- IMX8QM_SPDIF0_EXT_CLK
- IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK
- IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0
- IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16
- IMX8QM_SPDIF0_RX
- IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1
- IMX8QM_SPDIF0_RX_AUD_MQS_R
- IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX
- IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14
- IMX8QM_SPDIF0_TX
- IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1
- IMX8QM_SPDIF0_TX_AUD_MQS_L
- IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX
- IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15
- IMX8QM_SPI0_CS0
- IMX8QM_SPI0_CS0_AUD_SAI0_RXFS
- IMX8QM_SPI0_CS0_DMA_SPI0_CS0
- IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05
- IMX8QM_SPI0_CS1
- IMX8QM_SPI0_CS1_AUD_SAI0_TXC
- IMX8QM_SPI0_CS1_DMA_SPI0_CS1
- IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06
- IMX8QM_SPI0_SCK
- IMX8QM_SPI0_SCK_AUD_SAI0_RXC
- IMX8QM_SPI0_SCK_DMA_SPI0_SCK
- IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02
- IMX8QM_SPI0_SDI
- IMX8QM_SPI0_SDI_AUD_SAI0_RXD
- IMX8QM_SPI0_SDI_DMA_SPI0_SDI
- IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04
- IMX8QM_SPI0_SDO
- IMX8QM_SPI0_SDO_AUD_SAI0_TXD
- IMX8QM_SPI0_SDO_DMA_SPI0_SDO
- IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03
- IMX8QM_SPI2_CS0
- IMX8QM_SPI2_CS0_DMA_SPI2_CS0
- IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10
- IMX8QM_SPI2_CS1
- IMX8QM_SPI2_CS1_AUD_SAI0_TXFS
- IMX8QM_SPI2_CS1_DMA_SPI2_CS1
- IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11
- IMX8QM_SPI2_SCK
- IMX8QM_SPI2_SCK_DMA_SPI2_SCK
- IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07
- IMX8QM_SPI2_SDI
- IMX8QM_SPI2_SDI_DMA_SPI2_SDI
- IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09
- IMX8QM_SPI2_SDO
- IMX8QM_SPI2_SDO_DMA_SPI2_SDO
- IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08
- IMX8QM_SPI3_CS0
- IMX8QM_SPI3_CS0_DMA_FTM_CH2
- IMX8QM_SPI3_CS0_DMA_SPI3_CS0
- IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20
- IMX8QM_SPI3_CS1
- IMX8QM_SPI3_CS1_DMA_SPI3_CS1
- IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21
- IMX8QM_SPI3_SCK
- IMX8QM_SPI3_SCK_DMA_SPI3_SCK
- IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17
- IMX8QM_SPI3_SDI
- IMX8QM_SPI3_SDI_DMA_FTM_CH1
- IMX8QM_SPI3_SDI_DMA_SPI3_SDI
- IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19
- IMX8QM_SPI3_SDO
- IMX8QM_SPI3_SDO_DMA_FTM_CH0
- IMX8QM_SPI3_SDO_DMA_SPI3_SDO
- IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18
- IMX8QM_STTS0_LANE0_TX_PLL_LOCK
- IMX8QM_UART0_CTS_B
- IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B
- IMX8QM_UART0_CTS_B_DMA_UART2_TX
- IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23
- IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT
- IMX8QM_UART0_RTS_B
- IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B
- IMX8QM_UART0_RTS_B_DMA_UART2_RX
- IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22
- IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT
- IMX8QM_UART0_RX
- IMX8QM_UART0_RX_DMA_UART0_RX
- IMX8QM_UART0_RX_LSIO_GPIO0_IO20
- IMX8QM_UART0_RX_SCU_UART0_RX
- IMX8QM_UART0_TX
- IMX8QM_UART0_TX_DMA_UART0_TX
- IMX8QM_UART0_TX_LSIO_GPIO0_IO21
- IMX8QM_UART0_TX_SCU_UART0_TX
- IMX8QM_UART1_CTS_B
- IMX8QM_UART1_CTS_B_DMA_SPI3_CS0
- IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B
- IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B
- IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27
- IMX8QM_UART1_RTS_B
- IMX8QM_UART1_RTS_B_DMA_SPI3_SDI
- IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B
- IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B
- IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26
- IMX8QM_UART1_RX
- IMX8QM_UART1_RX_DMA_SPI3_SDO
- IMX8QM_UART1_RX_DMA_UART1_RX
- IMX8QM_UART1_RX_LSIO_GPIO0_IO25
- IMX8QM_UART1_TX
- IMX8QM_UART1_TX_DMA_SPI3_SCK
- IMX8QM_UART1_TX_DMA_UART1_TX
- IMX8QM_UART1_TX_LSIO_GPIO0_IO24
- IMX8QM_USB_HSIC0_DATA
- IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA
- IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA
- IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01
- IMX8QM_USB_HSIC0_STROBE
- IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE
- IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL
- IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02
- IMX8QM_USB_SS3_TC0
- IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR
- IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL
- IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03
- IMX8QM_USB_SS3_TC1
- IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR
- IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL
- IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04
- IMX8QM_USB_SS3_TC2
- IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC
- IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA
- IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05
- IMX8QM_USB_SS3_TC3
- IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC
- IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA
- IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06
- IMX8QM_USDHC1_CLK
- IMX8QM_USDHC1_CLK_AUD_MQS_R
- IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK
- IMX8QM_USDHC1_CMD
- IMX8QM_USDHC1_CMD_AUD_MQS_L
- IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD
- IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14
- IMX8QM_USDHC1_DATA0
- IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N
- IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0
- IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15
- IMX8QM_USDHC1_DATA1
- IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P
- IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1
- IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16
- IMX8QM_USDHC1_DATA2
- IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N
- IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2
- IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17
- IMX8QM_USDHC1_DATA3
- IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P
- IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3
- IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18
- IMX8QM_USDHC1_DATA4
- IMX8QM_USDHC1_DATA4_AUD_MQS_R
- IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B
- IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4
- IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19
- IMX8QM_USDHC1_DATA5
- IMX8QM_USDHC1_DATA5_AUD_MQS_L
- IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B
- IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5
- IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20
- IMX8QM_USDHC1_DATA6
- IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B
- IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6
- IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP
- IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21
- IMX8QM_USDHC1_DATA7
- IMX8QM_USDHC1_DATA7_CONN_NAND_ALE
- IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B
- IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7
- IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22
- IMX8QM_USDHC1_RESET_B
- IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B
- IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07
- IMX8QM_USDHC1_STROBE
- IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B
- IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B
- IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE
- IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23
- IMX8QM_USDHC1_VSELECT
- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT
- IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08
- IMX8QM_USDHC2_CD_B
- IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B
- IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12
- IMX8QM_USDHC2_CLK
- IMX8QM_USDHC2_CLK_AUD_MQS_R
- IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK
- IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24
- IMX8QM_USDHC2_CMD
- IMX8QM_USDHC2_CMD_AUD_MQS_L
- IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD
- IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25
- IMX8QM_USDHC2_DATA0
- IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0
- IMX8QM_USDHC2_DATA0_DMA_UART4_RX
- IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26
- IMX8QM_USDHC2_DATA1
- IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1
- IMX8QM_USDHC2_DATA1_DMA_UART4_TX
- IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27
- IMX8QM_USDHC2_DATA2
- IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2
- IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B
- IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28
- IMX8QM_USDHC2_DATA3
- IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3
- IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B
- IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29
- IMX8QM_USDHC2_RESET_B
- IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B
- IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09
- IMX8QM_USDHC2_VSELECT
- IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT
- IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10
- IMX8QM_USDHC2_WP
- IMX8QM_USDHC2_WP_CONN_USDHC2_WP
- IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11
- IMX8QXP
- IMX8QXP_ADC_IN0
- IMX8QXP_ADC_IN0_ADMA_ADC_IN0
- IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10
- IMX8QXP_ADC_IN0_M40_GPIO0_IO00
- IMX8QXP_ADC_IN0_M40_I2C0_SCL
- IMX8QXP_ADC_IN1
- IMX8QXP_ADC_IN1_ADMA_ADC_IN1
- IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09
- IMX8QXP_ADC_IN1_M40_GPIO0_IO01
- IMX8QXP_ADC_IN1_M40_I2C0_SDA
- IMX8QXP_ADC_IN2
- IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0
- IMX8QXP_ADC_IN2_ADMA_ADC_IN2
- IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12
- IMX8QXP_ADC_IN2_M40_GPIO0_IO02
- IMX8QXP_ADC_IN2_M40_UART0_RX
- IMX8QXP_ADC_IN3
- IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0
- IMX8QXP_ADC_IN3_ADMA_ADC_IN3
- IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11
- IMX8QXP_ADC_IN3_M40_GPIO0_IO03
- IMX8QXP_ADC_IN3_M40_UART0_TX
- IMX8QXP_ADC_IN4
- IMX8QXP_ADC_IN4_ADMA_ADC_IN4
- IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14
- IMX8QXP_ADC_IN4_M40_GPIO0_IO04
- IMX8QXP_ADC_IN4_M40_TPM0_CH0
- IMX8QXP_ADC_IN5
- IMX8QXP_ADC_IN5_ADMA_ADC_IN5
- IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13
- IMX8QXP_ADC_IN5_M40_GPIO0_IO05
- IMX8QXP_ADC_IN5_M40_TPM0_CH1
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3
- IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP
- IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO
- IMX8QXP_CSI_D00
- IMX8QXP_CSI_D00_ADMA_SAI0_RXC
- IMX8QXP_CSI_D00_CI_PI_D02
- IMX8QXP_CSI_D01
- IMX8QXP_CSI_D01_ADMA_SAI0_RXD
- IMX8QXP_CSI_D01_CI_PI_D03
- IMX8QXP_CSI_D02
- IMX8QXP_CSI_D02_ADMA_SAI0_RXFS
- IMX8QXP_CSI_D02_CI_PI_D04
- IMX8QXP_CSI_D03
- IMX8QXP_CSI_D03_ADMA_SAI2_RXC
- IMX8QXP_CSI_D03_CI_PI_D05
- IMX8QXP_CSI_D04
- IMX8QXP_CSI_D04_ADMA_SAI2_RXD
- IMX8QXP_CSI_D04_CI_PI_D06
- IMX8QXP_CSI_D05
- IMX8QXP_CSI_D05_ADMA_SAI2_RXFS
- IMX8QXP_CSI_D05_CI_PI_D07
- IMX8QXP_CSI_D06
- IMX8QXP_CSI_D06_ADMA_SAI3_RXC
- IMX8QXP_CSI_D06_CI_PI_D08
- IMX8QXP_CSI_D07
- IMX8QXP_CSI_D07_ADMA_SAI3_RXD
- IMX8QXP_CSI_D07_CI_PI_D09
- IMX8QXP_CSI_EN
- IMX8QXP_CSI_EN_ADMA_I2C3_SCL
- IMX8QXP_CSI_EN_ADMA_SPI1_SDI
- IMX8QXP_CSI_EN_CI_PI_EN
- IMX8QXP_CSI_EN_CI_PI_I2C_SCL
- IMX8QXP_CSI_EN_LSIO_GPIO3_IO02
- IMX8QXP_CSI_HSYNC
- IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS
- IMX8QXP_CSI_HSYNC_CI_PI_D00
- IMX8QXP_CSI_HSYNC_CI_PI_HSYNC
- IMX8QXP_CSI_MCLK
- IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO
- IMX8QXP_CSI_MCLK_CI_PI_MCLK
- IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01
- IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA
- IMX8QXP_CSI_PCLK
- IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK
- IMX8QXP_CSI_PCLK_CI_PI_PCLK
- IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00
- IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL
- IMX8QXP_CSI_RESET
- IMX8QXP_CSI_RESET_ADMA_I2C3_SDA
- IMX8QXP_CSI_RESET_ADMA_SPI1_CS0
- IMX8QXP_CSI_RESET_CI_PI_I2C_SDA
- IMX8QXP_CSI_RESET_CI_PI_RESET
- IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03
- IMX8QXP_CSI_VSYNC
- IMX8QXP_CSI_VSYNC_CI_PI_D01
- IMX8QXP_CSI_VSYNC_CI_PI_VSYNC
- IMX8QXP_CTL_NAND_DQS_P_N
- IMX8QXP_CTL_NAND_RE_P_N
- IMX8QXP_EMMC0_CLK
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK
- IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B
- IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07
- IMX8QXP_EMMC0_CMD
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD
- IMX8QXP_EMMC0_CMD_CONN_NAND_DQS
- IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08
- IMX8QXP_EMMC0_DATA0
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0
- IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00
- IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09
- IMX8QXP_EMMC0_DATA1
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1
- IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01
- IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10
- IMX8QXP_EMMC0_DATA2
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2
- IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02
- IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11
- IMX8QXP_EMMC0_DATA3
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3
- IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03
- IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12
- IMX8QXP_EMMC0_DATA4
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP
- IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04
- IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13
- IMX8QXP_EMMC0_DATA5
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT
- IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05
- IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14
- IMX8QXP_EMMC0_DATA6
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6
- IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK
- IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06
- IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15
- IMX8QXP_EMMC0_DATA7
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7
- IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG
- IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07
- IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16
- IMX8QXP_EMMC0_RESET_B
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B
- IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B
- IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18
- IMX8QXP_EMMC0_STROBE
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE
- IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA
- IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE
- IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17
- IMX8QXP_ENET0_MDC
- IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL
- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC
- IMX8QXP_ENET0_MDC_CONN_ENET1_MDC
- IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11
- IMX8QXP_ENET0_MDIO
- IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA
- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO
- IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO
- IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10
- IMX8QXP_ENET0_REFCLK_125M_25M
- IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS
- IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M
- IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS
- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09
- IMX8QXP_ENET0_RGMII_RXC
- IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
- IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA
- IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B
- IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK
- IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03
- IMX8QXP_ENET0_RGMII_RXD0
- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
- IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0
- IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05
- IMX8QXP_ENET0_RGMII_RXD1
- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
- IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1
- IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06
- IMX8QXP_ENET0_RGMII_RXD2
- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER
- IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2
- IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07
- IMX8QXP_ENET0_RGMII_RXD3
- IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
- IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE
- IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3
- IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08
- IMX8QXP_ENET0_RGMII_RX_CTL
- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD
- IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04
- IMX8QXP_ENET0_RGMII_TXC
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
- IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B
- IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29
- IMX8QXP_ENET0_RGMII_TXD0
- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
- IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT
- IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31
- IMX8QXP_ENET0_RGMII_TXD1
- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
- IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP
- IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00
- IMX8QXP_ENET0_RGMII_TXD2
- IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
- IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK
- IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B
- IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B
- IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01
- IMX8QXP_ENET0_RGMII_TXD3
- IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
- IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG
- IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B
- IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02
- IMX8QXP_ENET0_RGMII_TX_CTL
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B
- IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30
- IMX8QXP_ESAI0_FSR
- IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR
- IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00
- IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN
- IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT
- IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC
- IMX8QXP_ESAI0_FST
- IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST
- IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01
- IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2
- IMX8QXP_ESAI0_FST_CONN_MLB_CLK
- IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01
- IMX8QXP_ESAI0_SCKR
- IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR
- IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02
- IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL
- IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02
- IMX8QXP_ESAI0_SCKT
- IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT
- IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03
- IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3
- IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG
- IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03
- IMX8QXP_ESAI0_TX0
- IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0
- IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04
- IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC
- IMX8QXP_ESAI0_TX0_CONN_MLB_DATA
- IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04
- IMX8QXP_ESAI0_TX1
- IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1
- IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05
- IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3
- IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05
- IMX8QXP_ESAI0_TX2_RX3
- IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3
- IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06
- IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2
- IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER
- IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06
- IMX8QXP_ESAI0_TX3_RX2
- IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2
- IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07
- IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1
- IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07
- IMX8QXP_ESAI0_TX4_RX1
- IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1
- IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08
- IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0
- IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08
- IMX8QXP_ESAI0_TX5_RX0
- IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0
- IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09
- IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1
- IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09
- IMX8QXP_FLEXCAN0_RX
- IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX
- IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC
- IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC
- IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B
- IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15
- IMX8QXP_FLEXCAN0_TX
- IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX
- IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS
- IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD
- IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B
- IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16
- IMX8QXP_FLEXCAN1_RX
- IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX
- IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2
- IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD
- IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS
- IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17
- IMX8QXP_FLEXCAN1_TX
- IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0
- IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX
- IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD
- IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC
- IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18
- IMX8QXP_FLEXCAN2_RX
- IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX
- IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS
- IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD
- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX
- IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19
- IMX8QXP_FLEXCAN2_TX
- IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX
- IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC
- IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS
- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX
- IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20
- IMX8QXP_JTAG_TRST_B
- IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B
- IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT
- IMX8QXP_LPUART
- IMX8QXP_MCLK_IN0
- IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0
- IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK
- IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC
- IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI
- IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19
- IMX8QXP_MCLK_IN1
- IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1
- IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA
- IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17
- IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN
- IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK
- IMX8QXP_MCLK_OUT0
- IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0
- IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK
- IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK
- IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO
- IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20
- IMX8QXP_MIPI_CSI0_GPIO0_00
- IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL
- IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08
- IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00
- IMX8QXP_MIPI_CSI0_GPIO0_01
- IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA
- IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07
- IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01
- IMX8QXP_MIPI_CSI0_I2C0_SCL
- IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05
- IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02
- IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL
- IMX8QXP_MIPI_CSI0_I2C0_SDA
- IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06
- IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03
- IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA
- IMX8QXP_MIPI_CSI0_MCLK_OUT
- IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04
- IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT
- IMX8QXP_MIPI_DSI0_GPIO0_00
- IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL
- IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27
- IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00
- IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT
- IMX8QXP_MIPI_DSI0_GPIO0_01
- IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA
- IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28
- IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01
- IMX8QXP_MIPI_DSI0_I2C0_SCL
- IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25
- IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL
- IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02
- IMX8QXP_MIPI_DSI0_I2C0_SDA
- IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26
- IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA
- IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03
- IMX8QXP_MIPI_DSI1_GPIO0_00
- IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL
- IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31
- IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00
- IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT
- IMX8QXP_MIPI_DSI1_GPIO0_01
- IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA
- IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00
- IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01
- IMX8QXP_MIPI_DSI1_I2C0_SCL
- IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29
- IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02
- IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL
- IMX8QXP_MIPI_DSI1_I2C0_SDA
- IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30
- IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03
- IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA
- IMX8QXP_PCIE_CTRL0_CLKREQ_B
- IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B
- IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01
- IMX8QXP_PCIE_CTRL0_PERST_B
- IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
- IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00
- IMX8QXP_PCIE_CTRL0_WAKE_B
- IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B
- IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02
- IMX8QXP_PMIC_I2C_SCL
- IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01
- IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON
- IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL
- IMX8QXP_PMIC_I2C_SDA
- IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02
- IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON
- IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA
- IMX8QXP_PMIC_INT_B
- IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B
- IMX8QXP_QSPI0A_DATA0
- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09
- IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0
- IMX8QXP_QSPI0A_DATA1
- IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10
- IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1
- IMX8QXP_QSPI0A_DATA2
- IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11
- IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2
- IMX8QXP_QSPI0A_DATA3
- IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12
- IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3
- IMX8QXP_QSPI0A_DQS
- IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13
- IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS
- IMX8QXP_QSPI0A_SCLK
- IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16
- IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK
- IMX8QXP_QSPI0A_SS0_B
- IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14
- IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B
- IMX8QXP_QSPI0A_SS1_B
- IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15
- IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B
- IMX8QXP_QSPI0B_DATA0
- IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18
- IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1
- IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0
- IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0
- IMX8QXP_QSPI0B_DATA1
- IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19
- IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2
- IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1
- IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1
- IMX8QXP_QSPI0B_DATA2
- IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20
- IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3
- IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2
- IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2
- IMX8QXP_QSPI0B_DATA3
- IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21
- IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0
- IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3
- IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3
- IMX8QXP_QSPI0B_DQS
- IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22
- IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1
- IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS
- IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS
- IMX8QXP_QSPI0B_SCLK
- IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17
- IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0
- IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK
- IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK
- IMX8QXP_QSPI0B_SS0_B
- IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23
- IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2
- IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B
- IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B
- IMX8QXP_QSPI0B_SS1_B
- IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24
- IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3
- IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B
- IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B
- IMX8QXP_SAI0_RXD
- IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20
- IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD
- IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS
- IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0
- IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27
- IMX8QXP_SAI0_TXC
- IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19
- IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC
- IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD
- IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI
- IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26
- IMX8QXP_SAI0_TXD
- IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18
- IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD
- IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC
- IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO
- IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25
- IMX8QXP_SAI0_TXFS
- IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS
- IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK
- IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1
- IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28
- IMX8QXP_SAI1_RXC
- IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22
- IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC
- IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC
- IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30
- IMX8QXP_SAI1_RXD
- IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21
- IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS
- IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD
- IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1
- IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29
- IMX8QXP_SAI1_RXFS
- IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23
- IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS
- IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS
- IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31
- IMX8QXP_SCU_BOOT_MODE0
- IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0
- IMX8QXP_SCU_BOOT_MODE1
- IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1
- IMX8QXP_SCU_BOOT_MODE2
- IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2
- IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA
- IMX8QXP_SCU_BOOT_MODE3
- IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3
- IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K
- IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL
- IMX8QXP_SCU_GPIO0_00
- IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX
- IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03
- IMX8QXP_SCU_GPIO0_00_M40_UART0_RX
- IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00
- IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX
- IMX8QXP_SCU_GPIO0_01
- IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX
- IMX8QXP_SCU_GPIO0_01_M40_UART0_TX
- IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01
- IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX
- IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT
- IMX8QXP_SCU_PMIC_STANDBY
- IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY
- IMX8QXP_SPDIF0_EXT_CLK
- IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12
- IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK
- IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M
- IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12
- IMX8QXP_SPDIF0_RX
- IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10
- IMX8QXP_SPDIF0_RX_ADMA_MQS_R
- IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX
- IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0
- IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10
- IMX8QXP_SPDIF0_TX
- IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11
- IMX8QXP_SPDIF0_TX_ADMA_MQS_L
- IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX
- IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL
- IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11
- IMX8QXP_SPI0_CS0
- IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD
- IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0
- IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08
- IMX8QXP_SPI0_CS0_M40_GPIO0_IO03
- IMX8QXP_SPI0_CS0_M40_TPM0_CH1
- IMX8QXP_SPI0_CS1
- IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT
- IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC
- IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD
- IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1
- IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07
- IMX8QXP_SPI0_SCK
- IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC
- IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK
- IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04
- IMX8QXP_SPI0_SCK_M40_GPIO0_IO00
- IMX8QXP_SPI0_SCK_M40_I2C0_SCL
- IMX8QXP_SPI0_SDI
- IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD
- IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI
- IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05
- IMX8QXP_SPI0_SDI_M40_GPIO0_IO02
- IMX8QXP_SPI0_SDI_M40_TPM0_CH0
- IMX8QXP_SPI0_SDO
- IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS
- IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO
- IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06
- IMX8QXP_SPI0_SDO_M40_GPIO0_IO01
- IMX8QXP_SPI0_SDO_M40_I2C0_SDA
- IMX8QXP_SPI2_CS0
- IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0
- IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00
- IMX8QXP_SPI2_SCK
- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK
- IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03
- IMX8QXP_SPI2_SDI
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI
- IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02
- IMX8QXP_SPI2_SDO
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO
- IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01
- IMX8QXP_SPI3_CS0
- IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1
- IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC
- IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0
- IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16
- IMX8QXP_SPI3_CS1
- IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL
- IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16
- IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET
- IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0
- IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1
- IMX8QXP_SPI3_SCK
- IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13
- IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK
- IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13
- IMX8QXP_SPI3_SDI
- IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15
- IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI
- IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15
- IMX8QXP_SPI3_SDO
- IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14
- IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO
- IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14
- IMX8QXP_UART0_RX
- IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX
- IMX8QXP_UART0_RX_ADMA_MQS_R
- IMX8QXP_UART0_RX_ADMA_UART0_RX
- IMX8QXP_UART0_RX_LSIO_GPIO1_IO21
- IMX8QXP_UART0_TX
- IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX
- IMX8QXP_UART0_TX_ADMA_MQS_L
- IMX8QXP_UART0_TX_ADMA_UART0_TX
- IMX8QXP_UART0_TX_LSIO_GPIO1_IO22
- IMX8QXP_UART1_CTS_B
- IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17
- IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B
- IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24
- IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE
- IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT
- IMX8QXP_UART1_RTS_B
- IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16
- IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B
- IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK
- IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE
- IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT
- IMX8QXP_UART1_RX
- IMX8QXP_UART1_RX_ADMA_UART1_RX
- IMX8QXP_UART1_RX_LSIO_GPIO0_IO22
- IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE
- IMX8QXP_UART1_RX_LSIO_GPT1_CLK
- IMX8QXP_UART1_RX_LSIO_PWM1_OUT
- IMX8QXP_UART1_TX
- IMX8QXP_UART1_TX_ADMA_UART1_TX
- IMX8QXP_UART1_TX_LSIO_GPIO0_IO21
- IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE
- IMX8QXP_UART1_TX_LSIO_PWM0_OUT
- IMX8QXP_UART2_RX
- IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX
- IMX8QXP_UART2_RX_ADMA_FTM_CH0
- IMX8QXP_UART2_RX_ADMA_UART2_RX
- IMX8QXP_UART2_RX_LSIO_GPIO1_IO24
- IMX8QXP_UART2_TX
- IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX
- IMX8QXP_UART2_TX_ADMA_FTM_CH1
- IMX8QXP_UART2_TX_ADMA_UART2_TX
- IMX8QXP_UART2_TX_LSIO_GPIO1_IO23
- IMX8QXP_USB_SS3_TC0
- IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL
- IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR
- IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR
- IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03
- IMX8QXP_USB_SS3_TC1
- IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL
- IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR
- IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04
- IMX8QXP_USB_SS3_TC2
- IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA
- IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC
- IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC
- IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05
- IMX8QXP_USB_SS3_TC3
- IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA
- IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC
- IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06
- IMX8QXP_USDHC1_CD_B
- IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0
- IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS
- IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P
- IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B
- IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22
- IMX8QXP_USDHC1_CLK
- IMX8QXP_USDHC1_CLK_ADMA_UART3_RX
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK
- IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23
- IMX8QXP_USDHC1_CMD
- IMX8QXP_USDHC1_CMD_ADMA_MQS_R
- IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD
- IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24
- IMX8QXP_USDHC1_DATA0
- IMX8QXP_USDHC1_DATA0_ADMA_MQS_L
- IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0
- IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25
- IMX8QXP_USDHC1_DATA1
- IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX
- IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1
- IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26
- IMX8QXP_USDHC1_DATA2
- IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B
- IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2
- IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27
- IMX8QXP_USDHC1_DATA3
- IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B
- IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3
- IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28
- IMX8QXP_USDHC1_RESET_B
- IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK
- IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N
- IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B
- IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19
- IMX8QXP_USDHC1_VSELECT
- IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO
- IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B
- IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT
- IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20
- IMX8QXP_USDHC1_WP
- IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI
- IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N
- IMX8QXP_USDHC1_WP_CONN_USDHC1_WP
- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21
- IMX8_DDR_PMU_EVENT_ATTR
- IMXDMA_DESC_CYCLIC
- IMXDMA_DESC_INTERLEAVED
- IMXDMA_DESC_MEMCPY
- IMXDMA_DESC_SLAVE_SG
- IMXDMA_MAX_CHAN_DESCRIPTORS
- IMXFB_LSCR1_DEFAULT
- IMXUART_HAVE_RTSCTS
- IMX_A35_CLK
- IMX_ADMA_ADC0_CLK
- IMX_ADMA_CAN0_CLK
- IMX_ADMA_CAN1_CLK
- IMX_ADMA_CAN2_CLK
- IMX_ADMA_FTM0_CLK
- IMX_ADMA_FTM1_CLK
- IMX_ADMA_I2C0_CLK
- IMX_ADMA_I2C1_CLK
- IMX_ADMA_I2C2_CLK
- IMX_ADMA_I2C3_CLK
- IMX_ADMA_IPG_CLK_ROOT
- IMX_ADMA_LCD_CLK
- IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK
- IMX_ADMA_LPCG_CAN0_IPG_CLK
- IMX_ADMA_LPCG_CAN0_IPG_PE_CLK
- IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK
- IMX_ADMA_LPCG_CAN1_IPG_CLK
- IMX_ADMA_LPCG_CAN1_IPG_PE_CLK
- IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK
- IMX_ADMA_LPCG_CAN2_IPG_CLK
- IMX_ADMA_LPCG_CAN2_IPG_PE_CLK
- IMX_ADMA_LPCG_CLK_END
- IMX_ADMA_LPCG_DSP_ADB_CLK
- IMX_ADMA_LPCG_DSP_CORE_CLK
- IMX_ADMA_LPCG_DSP_IPG_CLK
- IMX_ADMA_LPCG_FTM0_CLK
- IMX_ADMA_LPCG_FTM0_IPG_CLK
- IMX_ADMA_LPCG_FTM1_CLK
- IMX_ADMA_LPCG_FTM1_IPG_CLK
- IMX_ADMA_LPCG_I2C0_CLK
- IMX_ADMA_LPCG_I2C0_IPG_CLK
- IMX_ADMA_LPCG_I2C1_CLK
- IMX_ADMA_LPCG_I2C1_IPG_CLK
- IMX_ADMA_LPCG_I2C2_CLK
- IMX_ADMA_LPCG_I2C2_IPG_CLK
- IMX_ADMA_LPCG_I2C3_CLK
- IMX_ADMA_LPCG_I2C3_IPG_CLK
- IMX_ADMA_LPCG_LCD_APB_CLK
- IMX_ADMA_LPCG_LCD_PIX_CLK
- IMX_ADMA_LPCG_OCRAM_IPG_CLK
- IMX_ADMA_LPCG_PWM_HI_CLK
- IMX_ADMA_LPCG_PWM_IPG_CLK
- IMX_ADMA_LPCG_SPI0_CLK
- IMX_ADMA_LPCG_SPI0_IPG_CLK
- IMX_ADMA_LPCG_SPI1_CLK
- IMX_ADMA_LPCG_SPI1_IPG_CLK
- IMX_ADMA_LPCG_SPI2_CLK
- IMX_ADMA_LPCG_SPI2_IPG_CLK
- IMX_ADMA_LPCG_SPI3_CLK
- IMX_ADMA_LPCG_SPI3_IPG_CLK
- IMX_ADMA_LPCG_UART0_BAUD_CLK
- IMX_ADMA_LPCG_UART0_IPG_CLK
- IMX_ADMA_LPCG_UART1_BAUD_CLK
- IMX_ADMA_LPCG_UART1_IPG_CLK
- IMX_ADMA_LPCG_UART2_BAUD_CLK
- IMX_ADMA_LPCG_UART2_IPG_CLK
- IMX_ADMA_LPCG_UART3_BAUD_CLK
- IMX_ADMA_LPCG_UART3_IPG_CLK
- IMX_ADMA_PWM_CLK
- IMX_ADMA_SPI0_CLK
- IMX_ADMA_SPI1_CLK
- IMX_ADMA_SPI2_CLK
- IMX_ADMA_SPI3_CLK
- IMX_ADMA_UART0_CLK
- IMX_ADMA_UART1_CLK
- IMX_ADMA_UART2_CLK
- IMX_ADMA_UART3_CLK
- IMX_AUDMUX_RXCLK
- IMX_AUDMUX_RXFS
- IMX_AUDMUX_V1_PCR_INMEN
- IMX_AUDMUX_V1_PCR_INMMASK
- IMX_AUDMUX_V1_PCR_RCLKDIR
- IMX_AUDMUX_V1_PCR_RFCSEL
- IMX_AUDMUX_V1_PCR_RFSDIR
- IMX_AUDMUX_V1_PCR_RXDSEL
- IMX_AUDMUX_V1_PCR_SYN
- IMX_AUDMUX_V1_PCR_TCLKDIR
- IMX_AUDMUX_V1_PCR_TFCSEL
- IMX_AUDMUX_V1_PCR_TFSDIR
- IMX_AUDMUX_V1_PCR_TXRXEN
- IMX_AUDMUX_V2_PDCR
- IMX_AUDMUX_V2_PDCR_INMMASK
- IMX_AUDMUX_V2_PDCR_MODE
- IMX_AUDMUX_V2_PDCR_RXDSEL
- IMX_AUDMUX_V2_PDCR_TXRXEN
- IMX_AUDMUX_V2_PTCR
- IMX_AUDMUX_V2_PTCR_RCLKDIR
- IMX_AUDMUX_V2_PTCR_RCSEL
- IMX_AUDMUX_V2_PTCR_RFSDIR
- IMX_AUDMUX_V2_PTCR_RFSEL
- IMX_AUDMUX_V2_PTCR_SYN
- IMX_AUDMUX_V2_PTCR_TCLKDIR
- IMX_AUDMUX_V2_PTCR_TCSEL
- IMX_AUDMUX_V2_PTCR_TFSDIR
- IMX_AUDMUX_V2_PTCR_TFSEL
- IMX_CAPTURE_NAME
- IMX_CFG_PARAMS_DECODE
- IMX_CFG_PARAMS_DECODE_INVERT
- IMX_CHIP_REVISION_1_0
- IMX_CHIP_REVISION_1_1
- IMX_CHIP_REVISION_1_2
- IMX_CHIP_REVISION_1_3
- IMX_CHIP_REVISION_1_4
- IMX_CHIP_REVISION_1_5
- IMX_CHIP_REVISION_2_0
- IMX_CHIP_REVISION_2_1
- IMX_CHIP_REVISION_2_2
- IMX_CHIP_REVISION_2_3
- IMX_CHIP_REVISION_3_0
- IMX_CHIP_REVISION_3_1
- IMX_CHIP_REVISION_3_2
- IMX_CHIP_REVISION_3_3
- IMX_CHIP_REVISION_UNKNOWN
- IMX_CLK_DUMMY
- IMX_CLOCK_RESET
- IMX_CLOCK_RESET_RESET
- IMX_CONN_AHB_CLK_ROOT
- IMX_CONN_AXI_CLK_ROOT
- IMX_CONN_ENET0_BYPASS_CLK
- IMX_CONN_ENET0_RGMII_CLK
- IMX_CONN_ENET0_ROOT_CLK
- IMX_CONN_ENET1_BYPASS_CLK
- IMX_CONN_ENET1_RGMII_CLK
- IMX_CONN_ENET1_ROOT_CLK
- IMX_CONN_GPMI_BCH_CLK
- IMX_CONN_GPMI_BCH_IO_CLK
- IMX_CONN_IPG_CLK_ROOT
- IMX_CONN_LPCG_APBHDMA_CLK
- IMX_CONN_LPCG_CLK_END
- IMX_CONN_LPCG_ENET0_AHB_CLK
- IMX_CONN_LPCG_ENET0_IPG_CLK
- IMX_CONN_LPCG_ENET0_IPG_S_CLK
- IMX_CONN_LPCG_ENET0_ROOT_CLK
- IMX_CONN_LPCG_ENET0_TX_CLK
- IMX_CONN_LPCG_ENET1_AHB_CLK
- IMX_CONN_LPCG_ENET1_IPG_CLK
- IMX_CONN_LPCG_ENET1_IPG_S_CLK
- IMX_CONN_LPCG_ENET1_ROOT_CLK
- IMX_CONN_LPCG_ENET1_TX_CLK
- IMX_CONN_LPCG_GPMI_APB_CLK
- IMX_CONN_LPCG_GPMI_BCH_APB_CLK
- IMX_CONN_LPCG_GPMI_BCH_CLK
- IMX_CONN_LPCG_GPMI_BCH_IO_CLK
- IMX_CONN_LPCG_SDHC0_HCLK
- IMX_CONN_LPCG_SDHC0_IPG_CLK
- IMX_CONN_LPCG_SDHC0_PER_CLK
- IMX_CONN_LPCG_SDHC1_HCLK
- IMX_CONN_LPCG_SDHC1_IPG_CLK
- IMX_CONN_LPCG_SDHC1_PER_CLK
- IMX_CONN_LPCG_SDHC2_HCLK
- IMX_CONN_LPCG_SDHC2_IPG_CLK
- IMX_CONN_LPCG_SDHC2_PER_CLK
- IMX_CONN_SDHC0_CLK
- IMX_CONN_SDHC1_CLK
- IMX_CONN_SDHC2_CLK
- IMX_CONN_USB2_ACLK
- IMX_CONN_USB2_BUS_CLK
- IMX_CONN_USB2_LPM_CLK
- IMX_CONSOLE
- IMX_CSI0_CORE_CLK
- IMX_CSI0_ESC_CLK
- IMX_CSI0_I2C0_CLK
- IMX_CSI0_PWM0_CLK
- IMX_DC0_DISP0_CLK
- IMX_DC0_DISP1_CLK
- IMX_DC0_PLL0_CLK
- IMX_DC0_PLL1_CLK
- IMX_DC_AXI_EXT_CLK
- IMX_DC_AXI_INT_CLK
- IMX_DC_CFG_CLK
- IMX_DDR_TYPE_LPDDR2
- IMX_DEBUG_UART_BASE
- IMX_DEFAULT_DMABUF_SIZE
- IMX_DMATYPE_ASRC
- IMX_DMATYPE_ASRC_SP
- IMX_DMATYPE_ATA
- IMX_DMATYPE_CCM
- IMX_DMATYPE_CSPI
- IMX_DMATYPE_CSPI_SP
- IMX_DMATYPE_DSP
- IMX_DMATYPE_ESAI
- IMX_DMATYPE_EXT
- IMX_DMATYPE_FIFO_MEMORY
- IMX_DMATYPE_FIRI
- IMX_DMATYPE_IPU_MEMORY
- IMX_DMATYPE_MEMORY
- IMX_DMATYPE_MMC
- IMX_DMATYPE_MSHC
- IMX_DMATYPE_MSHC_SP
- IMX_DMATYPE_SAI
- IMX_DMATYPE_SDHC
- IMX_DMATYPE_SIM
- IMX_DMATYPE_SPDIF
- IMX_DMATYPE_SSI
- IMX_DMATYPE_SSI_DUAL
- IMX_DMATYPE_SSI_SP
- IMX_DMATYPE_UART
- IMX_DMATYPE_UART_SP
- IMX_DMA_2D_SLOTS
- IMX_DMA_2D_SLOT_A
- IMX_DMA_2D_SLOT_B
- IMX_DMA_CHANNELS
- IMX_DMA_ERR_BUFFER
- IMX_DMA_ERR_BURST
- IMX_DMA_ERR_REQUEST
- IMX_DMA_ERR_TIMEOUT
- IMX_DMA_ERR_TRANSFER
- IMX_DMA_LENGTH_LOOP
- IMX_DMA_MEMSIZE_16
- IMX_DMA_MEMSIZE_32
- IMX_DMA_MEMSIZE_8
- IMX_DMA_SG_LOOP
- IMX_DMA_TYPE_2D
- IMX_DMA_TYPE_FIFO
- IMX_DMA_TYPE_LINEAR
- IMX_ESAI_DMABUF_SIZE
- IMX_FMT_BULK
- IMX_FMT_CTRL
- IMX_FMT_INT
- IMX_FMT_ISO
- IMX_GPIO_NR
- IMX_GPR_HL
- IMX_GPR_SL
- IMX_GPU0_CORE_CLK
- IMX_GPU0_SHADER_CLK
- IMX_HSIO_AXI_CLK
- IMX_HSIO_PER_CLK
- IMX_I2C_BIT_RATE
- IMX_I2C_I2CR
- IMX_I2C_I2DR
- IMX_I2C_I2SR
- IMX_I2C_IADR
- IMX_I2C_IFDR
- IMX_I2C_REGSHIFT
- IMX_IMG_AXI_CLK
- IMX_IMG_IPG_CLK
- IMX_IMG_PXL_CLK
- IMX_IO_ADDRESS
- IMX_IO_P2V
- IMX_IO_P2V_MODULE
- IMX_KEYPAD_SCANS_FOR_STABILITY
- IMX_LANE0_OUT_STAT
- IMX_LANE0_OUT_STAT_RX_PLL_STATE
- IMX_LSIO_BUS_CLK
- IMX_LSIO_FSPI0_CLK
- IMX_LSIO_FSPI1_CLK
- IMX_LSIO_GPT0_CLK
- IMX_LSIO_GPT1_CLK
- IMX_LSIO_GPT2_CLK
- IMX_LSIO_GPT3_CLK
- IMX_LSIO_GPT4_CLK
- IMX_LSIO_LPCG_CLK_END
- IMX_LSIO_LPCG_FSPI0_HCLK
- IMX_LSIO_LPCG_FSPI0_IPG_CLK
- IMX_LSIO_LPCG_FSPI0_IPG_SFCK
- IMX_LSIO_LPCG_FSPI0_IPG_S_CLK
- IMX_LSIO_LPCG_FSPI1_HCLK
- IMX_LSIO_LPCG_FSPI1_IPG_CLK
- IMX_LSIO_LPCG_FSPI1_IPG_SFCK
- IMX_LSIO_LPCG_FSPI1_IPG_S_CLK
- IMX_LSIO_LPCG_GPT0_IPG_CLK
- IMX_LSIO_LPCG_GPT0_IPG_HF_CLK
- IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK
- IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK
- IMX_LSIO_LPCG_GPT0_IPG_S_CLK
- IMX_LSIO_LPCG_GPT1_IPG_CLK
- IMX_LSIO_LPCG_GPT1_IPG_HF_CLK
- IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK
- IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK
- IMX_LSIO_LPCG_GPT1_IPG_S_CLK
- IMX_LSIO_LPCG_GPT2_IPG_CLK
- IMX_LSIO_LPCG_GPT2_IPG_HF_CLK
- IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK
- IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK
- IMX_LSIO_LPCG_GPT2_IPG_S_CLK
- IMX_LSIO_LPCG_GPT3_IPG_CLK
- IMX_LSIO_LPCG_GPT3_IPG_HF_CLK
- IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK
- IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK
- IMX_LSIO_LPCG_GPT3_IPG_S_CLK
- IMX_LSIO_LPCG_GPT4_IPG_CLK
- IMX_LSIO_LPCG_GPT4_IPG_HF_CLK
- IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK
- IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK
- IMX_LSIO_LPCG_GPT4_IPG_S_CLK
- IMX_LSIO_LPCG_PWM0_IPG_CLK
- IMX_LSIO_LPCG_PWM0_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM0_IPG_S_CLK
- IMX_LSIO_LPCG_PWM1_IPG_CLK
- IMX_LSIO_LPCG_PWM1_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM1_IPG_S_CLK
- IMX_LSIO_LPCG_PWM2_IPG_CLK
- IMX_LSIO_LPCG_PWM2_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM2_IPG_S_CLK
- IMX_LSIO_LPCG_PWM3_IPG_CLK
- IMX_LSIO_LPCG_PWM3_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM3_IPG_S_CLK
- IMX_LSIO_LPCG_PWM4_IPG_CLK
- IMX_LSIO_LPCG_PWM4_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM4_IPG_S_CLK
- IMX_LSIO_LPCG_PWM5_IPG_CLK
- IMX_LSIO_LPCG_PWM5_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM5_IPG_S_CLK
- IMX_LSIO_LPCG_PWM6_IPG_CLK
- IMX_LSIO_LPCG_PWM6_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM6_IPG_S_CLK
- IMX_LSIO_LPCG_PWM7_IPG_CLK
- IMX_LSIO_LPCG_PWM7_IPG_HF_CLK
- IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK
- IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK
- IMX_LSIO_LPCG_PWM7_IPG_S_CLK
- IMX_LSIO_MEM_CLK
- IMX_LSIO_PWM0_CLK
- IMX_LSIO_PWM1_CLK
- IMX_LSIO_PWM2_CLK
- IMX_LSIO_PWM3_CLK
- IMX_LSIO_PWM4_CLK
- IMX_LSIO_PWM5_CLK
- IMX_LSIO_PWM6_CLK
- IMX_LSIO_PWM7_CLK
- IMX_MEDIA_EOF_TIMEOUT
- IMX_MEDIA_GRP_ID_CSI
- IMX_MEDIA_GRP_ID_CSI2
- IMX_MEDIA_GRP_ID_IPU_CSI
- IMX_MEDIA_GRP_ID_IPU_CSI0
- IMX_MEDIA_GRP_ID_IPU_CSI1
- IMX_MEDIA_GRP_ID_IPU_CSI_BIT
- IMX_MEDIA_GRP_ID_IPU_IC_PRP
- IMX_MEDIA_GRP_ID_IPU_IC_PRPENC
- IMX_MEDIA_GRP_ID_IPU_IC_PRPVF
- IMX_MEDIA_GRP_ID_IPU_VDIC
- IMX_MIPI0_BYPASS_CLK
- IMX_MIPI0_I2C0_CLK
- IMX_MIPI0_I2C1_CLK
- IMX_MIPI0_LVDS_BYPASS_CLK
- IMX_MIPI0_LVDS_PHY_CLK
- IMX_MIPI0_LVDS_PIXEL_CLK
- IMX_MIPI0_PIXEL_CLK
- IMX_MIPI0_PWM0_CLK
- IMX_MIPI1_BYPASS_CLK
- IMX_MIPI1_I2C0_CLK
- IMX_MIPI1_I2C1_CLK
- IMX_MIPI1_LVDS_BYPASS_CLK
- IMX_MIPI1_LVDS_PHY_CLK
- IMX_MIPI1_LVDS_PIXEL_CLK
- IMX_MIPI1_PIXEL_CLK
- IMX_MIPI1_PWM0_CLK
- IMX_MIPI_IPG_CLK
- IMX_MUX_MASK
- IMX_MU_CHANS
- IMX_MU_CHAN_NAME_SIZE
- IMX_MU_TYPE_RX
- IMX_MU_TYPE_RXDB
- IMX_MU_TYPE_TX
- IMX_MU_TYPE_TXDB
- IMX_MU_xCR
- IMX_MU_xCR_GIEn
- IMX_MU_xCR_GIRn
- IMX_MU_xCR_RIEn
- IMX_MU_xCR_TIEn
- IMX_MU_xRRn
- IMX_MU_xSR
- IMX_MU_xSR_BRDIP
- IMX_MU_xSR_GIPn
- IMX_MU_xSR_RFn
- IMX_MU_xSR_TEn
- IMX_MU_xTRn
- IMX_NAME
- IMX_NO_PAD_CTL
- IMX_OCOTP_ADDR_CTRL
- IMX_OCOTP_ADDR_CTRL_CLR
- IMX_OCOTP_ADDR_CTRL_SET
- IMX_OCOTP_ADDR_DATA0
- IMX_OCOTP_ADDR_DATA1
- IMX_OCOTP_ADDR_DATA2
- IMX_OCOTP_ADDR_DATA3
- IMX_OCOTP_ADDR_TIMING
- IMX_OCOTP_BM_CTRL_ADDR
- IMX_OCOTP_BM_CTRL_BUSY
- IMX_OCOTP_BM_CTRL_ERROR
- IMX_OCOTP_BM_CTRL_REL_SHADOWS
- IMX_OCOTP_OFFSET_B0W0
- IMX_OCOTP_OFFSET_PER_WORD
- IMX_OCOTP_READ_LOCKED_VAL
- IMX_OCOTP_WR_UNLOCK
- IMX_P0PHYCR
- IMX_P0PHYCR_CR_CAP_ADDR
- IMX_P0PHYCR_CR_CAP_DATA
- IMX_P0PHYCR_CR_READ
- IMX_P0PHYCR_CR_WRITE
- IMX_P0PHYCR_TEST_PDDQ
- IMX_P0PHYSR
- IMX_P0PHYSR_CR_ACK
- IMX_P0PHYSR_CR_DATA_OUT
- IMX_PAD_SION
- IMX_PARALLEL_CSI_DPLL_CLK
- IMX_PARALLEL_CSI_MCLK_CLK
- IMX_PARALLEL_CSI_PIXEL_CLK
- IMX_PASSIVE_DELAY
- IMX_PINCTRL_PIN
- IMX_PLLV1_IMX1
- IMX_PLLV1_IMX21
- IMX_PLLV1_IMX25
- IMX_PLLV1_IMX27
- IMX_PLLV1_IMX31
- IMX_PLLV1_IMX35
- IMX_PLLV3_AV
- IMX_PLLV3_AV_IMX7
- IMX_PLLV3_DDR_IMX7
- IMX_PLLV3_ENET
- IMX_PLLV3_ENET_IMX7
- IMX_PLLV3_GENERIC
- IMX_PLLV3_SYS
- IMX_PLLV3_SYS_VF610
- IMX_PLLV3_USB
- IMX_PLLV3_USB_VF610
- IMX_POLLING_DELAY
- IMX_REG_OFF
- IMX_SAI_DMABUF_SIZE
- IMX_SCU_CLK_END
- IMX_SCU_PD_NAME_SIZE
- IMX_SCU_SOC_DRIVER_NAME
- IMX_SC_C_CLKDIV
- IMX_SC_C_DISABLE_125
- IMX_SC_C_DISABLE_50
- IMX_SC_C_DPI_RESET
- IMX_SC_C_DUAL_MODE
- IMX_SC_C_ID
- IMX_SC_C_KACHUNK_CNT
- IMX_SC_C_KACHUNK_SEL
- IMX_SC_C_LAST
- IMX_SC_C_LINESTATE
- IMX_SC_C_MIPI_RESET
- IMX_SC_C_MODE
- IMX_SC_C_OFS_AUDIO
- IMX_SC_C_OFS_IRQ
- IMX_SC_C_OFS_PERIPH
- IMX_SC_C_OFS_SEL
- IMX_SC_C_PANIC
- IMX_SC_C_PCIE_BUTTON_RST
- IMX_SC_C_PCIE_G_RST
- IMX_SC_C_PCIE_PERST
- IMX_SC_C_PHY_RESET
- IMX_SC_C_PRIORITY_GROUP
- IMX_SC_C_PXL_CLK_POLARITY
- IMX_SC_C_PXL_LINK_MST1_ADDR
- IMX_SC_C_PXL_LINK_MST1_ENB
- IMX_SC_C_PXL_LINK_MST1_VLD
- IMX_SC_C_PXL_LINK_MST2_ADDR
- IMX_SC_C_PXL_LINK_MST2_ENB
- IMX_SC_C_PXL_LINK_MST2_VLD
- IMX_SC_C_PXL_LINK_MST_ENB
- IMX_SC_C_PXL_LINK_MST_VLD
- IMX_SC_C_PXL_LINK_RATE_CORRECTION
- IMX_SC_C_PXL_LINK_SEL
- IMX_SC_C_PXL_LINK_SLV1_ADDR
- IMX_SC_C_PXL_LINK_SLV2_ADDR
- IMX_SC_C_RST0
- IMX_SC_C_RST1
- IMX_SC_C_SEL0
- IMX_SC_C_SEL_125
- IMX_SC_C_SINGLE_MODE
- IMX_SC_C_SYNC_CTRL0
- IMX_SC_C_SYNC_CTRL1
- IMX_SC_C_TEMP
- IMX_SC_C_TEMP_HI
- IMX_SC_C_TEMP_LOW
- IMX_SC_C_TXCLK
- IMX_SC_C_VOLTAGE
- IMX_SC_ERR_BUSY
- IMX_SC_ERR_CONFIG
- IMX_SC_ERR_FAIL
- IMX_SC_ERR_IPC
- IMX_SC_ERR_LAST
- IMX_SC_ERR_LOCKED
- IMX_SC_ERR_NOACCESS
- IMX_SC_ERR_NONE
- IMX_SC_ERR_NOPOWER
- IMX_SC_ERR_NOTFOUND
- IMX_SC_ERR_PARM
- IMX_SC_ERR_UNAVAILABLE
- IMX_SC_ERR_VERSION
- IMX_SC_IRQ_FUNC_ENABLE
- IMX_SC_IRQ_FUNC_STATUS
- IMX_SC_IRQ_NUM_GROUP
- IMX_SC_MISC_FUNC_BOOT_DONE
- IMX_SC_MISC_FUNC_BOOT_STATUS
- IMX_SC_MISC_FUNC_BUILD_INFO
- IMX_SC_MISC_FUNC_DEBUG_OUT
- IMX_SC_MISC_FUNC_GET_BOOT_DEV
- IMX_SC_MISC_FUNC_GET_BUTTON_STATUS
- IMX_SC_MISC_FUNC_GET_CONTROL
- IMX_SC_MISC_FUNC_GET_TEMP
- IMX_SC_MISC_FUNC_OTP_FUSE_READ
- IMX_SC_MISC_FUNC_OTP_FUSE_WRITE
- IMX_SC_MISC_FUNC_SECO_AUTHENTICATE
- IMX_SC_MISC_FUNC_SECO_IMAGE_LOAD
- IMX_SC_MISC_FUNC_SET_ARI
- IMX_SC_MISC_FUNC_SET_CONTROL
- IMX_SC_MISC_FUNC_SET_DMA_GROUP
- IMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP
- IMX_SC_MISC_FUNC_SET_TEMP
- IMX_SC_MISC_FUNC_UNIQUE_ID
- IMX_SC_MISC_FUNC_UNKNOWN
- IMX_SC_MISC_FUNC_WAVEFORM_CAPTURE
- IMX_SC_PAD_FUNC_GET
- IMX_SC_PAD_FUNC_SET
- IMX_SC_PM_CLK_ALL
- IMX_SC_PM_CLK_BYPASS
- IMX_SC_PM_CLK_CPU
- IMX_SC_PM_CLK_MISC
- IMX_SC_PM_CLK_MISC0
- IMX_SC_PM_CLK_MISC1
- IMX_SC_PM_CLK_MISC2
- IMX_SC_PM_CLK_MISC3
- IMX_SC_PM_CLK_MISC4
- IMX_SC_PM_CLK_MST_BUS
- IMX_SC_PM_CLK_PER
- IMX_SC_PM_CLK_PHY
- IMX_SC_PM_CLK_PLL
- IMX_SC_PM_CLK_SLV_BUS
- IMX_SC_PM_FUNC_BOOT
- IMX_SC_PM_FUNC_CLOCK_ENABLE
- IMX_SC_PM_FUNC_CPU_START
- IMX_SC_PM_FUNC_GET_CLOCK_PARENT
- IMX_SC_PM_FUNC_GET_CLOCK_RATE
- IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE
- IMX_SC_PM_FUNC_GET_SYS_POWER_MODE
- IMX_SC_PM_FUNC_REBOOT
- IMX_SC_PM_FUNC_REBOOT_PARTITION
- IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE
- IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE
- IMX_SC_PM_FUNC_RESET
- IMX_SC_PM_FUNC_RESET_REASON
- IMX_SC_PM_FUNC_SET_CLOCK_PARENT
- IMX_SC_PM_FUNC_SET_CLOCK_RATE
- IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR
- IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE
- IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE
- IMX_SC_PM_FUNC_SET_SYS_POWER_MODE
- IMX_SC_PM_FUNC_UNKNOWN
- IMX_SC_PM_PARENT_BYPS
- IMX_SC_PM_PARENT_PLL0
- IMX_SC_PM_PARENT_PLL1
- IMX_SC_PM_PARENT_PLL2
- IMX_SC_PM_PARENT_XTAL
- IMX_SC_PM_PW_MODE_LP
- IMX_SC_PM_PW_MODE_OFF
- IMX_SC_PM_PW_MODE_ON
- IMX_SC_PM_PW_MODE_STBY
- IMX_SC_RPC_MAX_MSG
- IMX_SC_RPC_SVC_ABORT
- IMX_SC_RPC_SVC_IRQ
- IMX_SC_RPC_SVC_MISC
- IMX_SC_RPC_SVC_PAD
- IMX_SC_RPC_SVC_PM
- IMX_SC_RPC_SVC_RETURN
- IMX_SC_RPC_SVC_RM
- IMX_SC_RPC_SVC_TIMER
- IMX_SC_RPC_SVC_UNKNOWN
- IMX_SC_RPC_VERSION
- IMX_SC_R_A35
- IMX_SC_R_A35_0
- IMX_SC_R_A35_1
- IMX_SC_R_A35_2
- IMX_SC_R_A35_3
- IMX_SC_R_A53
- IMX_SC_R_A53_0
- IMX_SC_R_A53_1
- IMX_SC_R_A53_2
- IMX_SC_R_A53_3
- IMX_SC_R_A72
- IMX_SC_R_A72_0
- IMX_SC_R_A72_1
- IMX_SC_R_A72_2
- IMX_SC_R_A72_3
- IMX_SC_R_ADC_0
- IMX_SC_R_ADC_1
- IMX_SC_R_AMIX
- IMX_SC_R_ASRC_0
- IMX_SC_R_ASRC_1
- IMX_SC_R_ATTESTATION
- IMX_SC_R_AUDIO_CLK_0
- IMX_SC_R_AUDIO_CLK_1
- IMX_SC_R_AUDIO_PLL_0
- IMX_SC_R_AUDIO_PLL_1
- IMX_SC_R_BOARD_R0
- IMX_SC_R_BOARD_R1
- IMX_SC_R_BOARD_R2
- IMX_SC_R_BOARD_R3
- IMX_SC_R_BOARD_R4
- IMX_SC_R_BOARD_R5
- IMX_SC_R_BOARD_R6
- IMX_SC_R_BOARD_R7
- IMX_SC_R_CAAM_JR0
- IMX_SC_R_CAAM_JR0_OUT
- IMX_SC_R_CAAM_JR1
- IMX_SC_R_CAAM_JR1_OUT
- IMX_SC_R_CAAM_JR2
- IMX_SC_R_CAAM_JR2_OUT
- IMX_SC_R_CAAM_JR3
- IMX_SC_R_CAAM_JR3_OUT
- IMX_SC_R_CAN_0
- IMX_SC_R_CAN_1
- IMX_SC_R_CAN_2
- IMX_SC_R_CCI
- IMX_SC_R_CSI_0
- IMX_SC_R_CSI_0_I2C_0
- IMX_SC_R_CSI_0_PWM_0
- IMX_SC_R_CSI_1
- IMX_SC_R_CSI_1_I2C_0
- IMX_SC_R_CSI_1_PWM_0
- IMX_SC_R_DB
- IMX_SC_R_DBLOGIC
- IMX_SC_R_DC_0
- IMX_SC_R_DC_0_BLIT0
- IMX_SC_R_DC_0_BLIT1
- IMX_SC_R_DC_0_BLIT2
- IMX_SC_R_DC_0_BLIT_OUT
- IMX_SC_R_DC_0_FRAC0
- IMX_SC_R_DC_0_PLL_0
- IMX_SC_R_DC_0_PLL_1
- IMX_SC_R_DC_0_VIDEO0
- IMX_SC_R_DC_0_VIDEO1
- IMX_SC_R_DC_0_WARP
- IMX_SC_R_DC_1
- IMX_SC_R_DC_1_BLIT0
- IMX_SC_R_DC_1_BLIT1
- IMX_SC_R_DC_1_BLIT2
- IMX_SC_R_DC_1_BLIT_OUT
- IMX_SC_R_DC_1_FRAC0
- IMX_SC_R_DC_1_PLL_0
- IMX_SC_R_DC_1_PLL_1
- IMX_SC_R_DC_1_VIDEO0
- IMX_SC_R_DC_1_VIDEO1
- IMX_SC_R_DC_1_WARP
- IMX_SC_R_DEBUG
- IMX_SC_R_DMA_0_CH0
- IMX_SC_R_DMA_0_CH1
- IMX_SC_R_DMA_0_CH10
- IMX_SC_R_DMA_0_CH11
- IMX_SC_R_DMA_0_CH12
- IMX_SC_R_DMA_0_CH13
- IMX_SC_R_DMA_0_CH14
- IMX_SC_R_DMA_0_CH15
- IMX_SC_R_DMA_0_CH16
- IMX_SC_R_DMA_0_CH17
- IMX_SC_R_DMA_0_CH18
- IMX_SC_R_DMA_0_CH19
- IMX_SC_R_DMA_0_CH2
- IMX_SC_R_DMA_0_CH20
- IMX_SC_R_DMA_0_CH21
- IMX_SC_R_DMA_0_CH22
- IMX_SC_R_DMA_0_CH23
- IMX_SC_R_DMA_0_CH24
- IMX_SC_R_DMA_0_CH25
- IMX_SC_R_DMA_0_CH26
- IMX_SC_R_DMA_0_CH27
- IMX_SC_R_DMA_0_CH28
- IMX_SC_R_DMA_0_CH29
- IMX_SC_R_DMA_0_CH3
- IMX_SC_R_DMA_0_CH30
- IMX_SC_R_DMA_0_CH31
- IMX_SC_R_DMA_0_CH4
- IMX_SC_R_DMA_0_CH5
- IMX_SC_R_DMA_0_CH6
- IMX_SC_R_DMA_0_CH7
- IMX_SC_R_DMA_0_CH8
- IMX_SC_R_DMA_0_CH9
- IMX_SC_R_DMA_1_CH0
- IMX_SC_R_DMA_1_CH1
- IMX_SC_R_DMA_1_CH10
- IMX_SC_R_DMA_1_CH11
- IMX_SC_R_DMA_1_CH12
- IMX_SC_R_DMA_1_CH13
- IMX_SC_R_DMA_1_CH14
- IMX_SC_R_DMA_1_CH15
- IMX_SC_R_DMA_1_CH16
- IMX_SC_R_DMA_1_CH17
- IMX_SC_R_DMA_1_CH18
- IMX_SC_R_DMA_1_CH19
- IMX_SC_R_DMA_1_CH2
- IMX_SC_R_DMA_1_CH20
- IMX_SC_R_DMA_1_CH21
- IMX_SC_R_DMA_1_CH22
- IMX_SC_R_DMA_1_CH23
- IMX_SC_R_DMA_1_CH24
- IMX_SC_R_DMA_1_CH25
- IMX_SC_R_DMA_1_CH26
- IMX_SC_R_DMA_1_CH27
- IMX_SC_R_DMA_1_CH28
- IMX_SC_R_DMA_1_CH29
- IMX_SC_R_DMA_1_CH3
- IMX_SC_R_DMA_1_CH30
- IMX_SC_R_DMA_1_CH31
- IMX_SC_R_DMA_1_CH4
- IMX_SC_R_DMA_1_CH5
- IMX_SC_R_DMA_1_CH6
- IMX_SC_R_DMA_1_CH7
- IMX_SC_R_DMA_1_CH8
- IMX_SC_R_DMA_1_CH9
- IMX_SC_R_DMA_2_CH0
- IMX_SC_R_DMA_2_CH1
- IMX_SC_R_DMA_2_CH10
- IMX_SC_R_DMA_2_CH11
- IMX_SC_R_DMA_2_CH12
- IMX_SC_R_DMA_2_CH13
- IMX_SC_R_DMA_2_CH14
- IMX_SC_R_DMA_2_CH15
- IMX_SC_R_DMA_2_CH16
- IMX_SC_R_DMA_2_CH17
- IMX_SC_R_DMA_2_CH18
- IMX_SC_R_DMA_2_CH19
- IMX_SC_R_DMA_2_CH2
- IMX_SC_R_DMA_2_CH20
- IMX_SC_R_DMA_2_CH21
- IMX_SC_R_DMA_2_CH22
- IMX_SC_R_DMA_2_CH23
- IMX_SC_R_DMA_2_CH24
- IMX_SC_R_DMA_2_CH25
- IMX_SC_R_DMA_2_CH26
- IMX_SC_R_DMA_2_CH27
- IMX_SC_R_DMA_2_CH28
- IMX_SC_R_DMA_2_CH29
- IMX_SC_R_DMA_2_CH3
- IMX_SC_R_DMA_2_CH30
- IMX_SC_R_DMA_2_CH31
- IMX_SC_R_DMA_2_CH4
- IMX_SC_R_DMA_2_CH5
- IMX_SC_R_DMA_2_CH6
- IMX_SC_R_DMA_2_CH7
- IMX_SC_R_DMA_2_CH8
- IMX_SC_R_DMA_2_CH9
- IMX_SC_R_DMA_3_CH0
- IMX_SC_R_DMA_3_CH1
- IMX_SC_R_DMA_3_CH10
- IMX_SC_R_DMA_3_CH11
- IMX_SC_R_DMA_3_CH12
- IMX_SC_R_DMA_3_CH13
- IMX_SC_R_DMA_3_CH14
- IMX_SC_R_DMA_3_CH15
- IMX_SC_R_DMA_3_CH16
- IMX_SC_R_DMA_3_CH17
- IMX_SC_R_DMA_3_CH18
- IMX_SC_R_DMA_3_CH19
- IMX_SC_R_DMA_3_CH2
- IMX_SC_R_DMA_3_CH20
- IMX_SC_R_DMA_3_CH21
- IMX_SC_R_DMA_3_CH22
- IMX_SC_R_DMA_3_CH23
- IMX_SC_R_DMA_3_CH24
- IMX_SC_R_DMA_3_CH25
- IMX_SC_R_DMA_3_CH26
- IMX_SC_R_DMA_3_CH27
- IMX_SC_R_DMA_3_CH28
- IMX_SC_R_DMA_3_CH29
- IMX_SC_R_DMA_3_CH3
- IMX_SC_R_DMA_3_CH30
- IMX_SC_R_DMA_3_CH31
- IMX_SC_R_DMA_3_CH4
- IMX_SC_R_DMA_3_CH5
- IMX_SC_R_DMA_3_CH6
- IMX_SC_R_DMA_3_CH7
- IMX_SC_R_DMA_3_CH8
- IMX_SC_R_DMA_3_CH9
- IMX_SC_R_DMA_4_CH0
- IMX_SC_R_DMA_4_CH1
- IMX_SC_R_DMA_4_CH2
- IMX_SC_R_DMA_4_CH3
- IMX_SC_R_DMA_4_CH4
- IMX_SC_R_DMA_5_CH0
- IMX_SC_R_DMA_5_CH1
- IMX_SC_R_DMA_5_CH2
- IMX_SC_R_DMA_5_CH3
- IMX_SC_R_DRC_0
- IMX_SC_R_DRC_1
- IMX_SC_R_DSP
- IMX_SC_R_DSP_RAM
- IMX_SC_R_DTCP
- IMX_SC_R_ELCDIF_PLL
- IMX_SC_R_EMVSIM_0
- IMX_SC_R_EMVSIM_1
- IMX_SC_R_ENET_0
- IMX_SC_R_ENET_1
- IMX_SC_R_ESAI_0
- IMX_SC_R_ESAI_1
- IMX_SC_R_FSPI_0
- IMX_SC_R_FSPI_1
- IMX_SC_R_FTM_0
- IMX_SC_R_FTM_1
- IMX_SC_R_GIC
- IMX_SC_R_GIC_SMMU
- IMX_SC_R_GPIO_0
- IMX_SC_R_GPIO_1
- IMX_SC_R_GPIO_2
- IMX_SC_R_GPIO_3
- IMX_SC_R_GPIO_4
- IMX_SC_R_GPIO_5
- IMX_SC_R_GPIO_6
- IMX_SC_R_GPIO_7
- IMX_SC_R_GPT_0
- IMX_SC_R_GPT_1
- IMX_SC_R_GPT_10
- IMX_SC_R_GPT_2
- IMX_SC_R_GPT_3
- IMX_SC_R_GPT_4
- IMX_SC_R_GPT_5
- IMX_SC_R_GPT_6
- IMX_SC_R_GPT_7
- IMX_SC_R_GPT_8
- IMX_SC_R_GPT_9
- IMX_SC_R_GPU_0_PID0
- IMX_SC_R_GPU_0_PID1
- IMX_SC_R_GPU_0_PID2
- IMX_SC_R_GPU_0_PID3
- IMX_SC_R_GPU_1_PID0
- IMX_SC_R_GPU_1_PID1
- IMX_SC_R_GPU_1_PID2
- IMX_SC_R_GPU_1_PID3
- IMX_SC_R_GPU_2_PID0
- IMX_SC_R_HDMI
- IMX_SC_R_HDMI_I2C_0
- IMX_SC_R_HDMI_I2S
- IMX_SC_R_HDMI_PLL_0
- IMX_SC_R_HDMI_PLL_1
- IMX_SC_R_HDMI_RX
- IMX_SC_R_HDMI_RX_BYPASS
- IMX_SC_R_HDMI_RX_I2C_0
- IMX_SC_R_HDMI_RX_PWM_0
- IMX_SC_R_HSIO_GPIO
- IMX_SC_R_I2C_0
- IMX_SC_R_I2C_1
- IMX_SC_R_I2C_2
- IMX_SC_R_I2C_3
- IMX_SC_R_I2C_4
- IMX_SC_R_IEE
- IMX_SC_R_IEE_R0
- IMX_SC_R_IEE_R1
- IMX_SC_R_IEE_R2
- IMX_SC_R_IEE_R3
- IMX_SC_R_IEE_R4
- IMX_SC_R_IEE_R5
- IMX_SC_R_IEE_R6
- IMX_SC_R_IEE_R7
- IMX_SC_R_IRQSTR_DSP
- IMX_SC_R_IRQSTR_M4_0
- IMX_SC_R_IRQSTR_M4_1
- IMX_SC_R_IRQSTR_SCU2
- IMX_SC_R_ISI_CH0
- IMX_SC_R_ISI_CH1
- IMX_SC_R_ISI_CH2
- IMX_SC_R_ISI_CH3
- IMX_SC_R_ISI_CH4
- IMX_SC_R_ISI_CH5
- IMX_SC_R_ISI_CH6
- IMX_SC_R_ISI_CH7
- IMX_SC_R_KPP
- IMX_SC_R_LAST
- IMX_SC_R_LCD_0
- IMX_SC_R_LCD_0_I2C_0
- IMX_SC_R_LCD_0_I2C_1
- IMX_SC_R_LCD_0_PWM_0
- IMX_SC_R_LVDS_0
- IMX_SC_R_LVDS_0_I2C_0
- IMX_SC_R_LVDS_0_I2C_1
- IMX_SC_R_LVDS_0_PWM_0
- IMX_SC_R_LVDS_1
- IMX_SC_R_LVDS_1_I2C_0
- IMX_SC_R_LVDS_1_I2C_1
- IMX_SC_R_LVDS_1_PWM_0
- IMX_SC_R_LVDS_2
- IMX_SC_R_LVDS_2_I2C_0
- IMX_SC_R_LVDS_2_I2C_1
- IMX_SC_R_LVDS_2_PWM_0
- IMX_SC_R_M4_0_I2C
- IMX_SC_R_M4_0_INTMUX
- IMX_SC_R_M4_0_MU_0A0
- IMX_SC_R_M4_0_MU_0A1
- IMX_SC_R_M4_0_MU_0A2
- IMX_SC_R_M4_0_MU_0A3
- IMX_SC_R_M4_0_MU_0B
- IMX_SC_R_M4_0_MU_1A
- IMX_SC_R_M4_0_PID0
- IMX_SC_R_M4_0_PID1
- IMX_SC_R_M4_0_PID2
- IMX_SC_R_M4_0_PID3
- IMX_SC_R_M4_0_PID4
- IMX_SC_R_M4_0_PIT
- IMX_SC_R_M4_0_RGPIO
- IMX_SC_R_M4_0_SEMA42
- IMX_SC_R_M4_0_TPM
- IMX_SC_R_M4_0_UART
- IMX_SC_R_M4_1_I2C
- IMX_SC_R_M4_1_INTMUX
- IMX_SC_R_M4_1_MU_0A0
- IMX_SC_R_M4_1_MU_0A1
- IMX_SC_R_M4_1_MU_0A2
- IMX_SC_R_M4_1_MU_0A3
- IMX_SC_R_M4_1_MU_0B
- IMX_SC_R_M4_1_MU_1A
- IMX_SC_R_M4_1_PID0
- IMX_SC_R_M4_1_PID1
- IMX_SC_R_M4_1_PID2
- IMX_SC_R_M4_1_PID3
- IMX_SC_R_M4_1_PID4
- IMX_SC_R_M4_1_PIT
- IMX_SC_R_M4_1_RGPIO
- IMX_SC_R_M4_1_SEMA42
- IMX_SC_R_M4_1_TPM
- IMX_SC_R_M4_1_UART
- IMX_SC_R_MATCH_0
- IMX_SC_R_MATCH_1
- IMX_SC_R_MATCH_10
- IMX_SC_R_MATCH_11
- IMX_SC_R_MATCH_12
- IMX_SC_R_MATCH_13
- IMX_SC_R_MATCH_14
- IMX_SC_R_MATCH_15
- IMX_SC_R_MATCH_16
- IMX_SC_R_MATCH_17
- IMX_SC_R_MATCH_18
- IMX_SC_R_MATCH_19
- IMX_SC_R_MATCH_2
- IMX_SC_R_MATCH_20
- IMX_SC_R_MATCH_21
- IMX_SC_R_MATCH_22
- IMX_SC_R_MATCH_23
- IMX_SC_R_MATCH_24
- IMX_SC_R_MATCH_25
- IMX_SC_R_MATCH_26
- IMX_SC_R_MATCH_27
- IMX_SC_R_MATCH_28
- IMX_SC_R_MATCH_3
- IMX_SC_R_MATCH_4
- IMX_SC_R_MATCH_5
- IMX_SC_R_MATCH_6
- IMX_SC_R_MATCH_7
- IMX_SC_R_MATCH_8
- IMX_SC_R_MATCH_9
- IMX_SC_R_MCLK_OUT_0
- IMX_SC_R_MCLK_OUT_1
- IMX_SC_R_MIPI_0
- IMX_SC_R_MIPI_0_I2C_0
- IMX_SC_R_MIPI_0_I2C_1
- IMX_SC_R_MIPI_0_PWM_0
- IMX_SC_R_MIPI_1
- IMX_SC_R_MIPI_1_I2C_0
- IMX_SC_R_MIPI_1_I2C_1
- IMX_SC_R_MIPI_1_PWM_0
- IMX_SC_R_MJPEG_DEC_MP
- IMX_SC_R_MJPEG_DEC_S0
- IMX_SC_R_MJPEG_DEC_S1
- IMX_SC_R_MJPEG_DEC_S2
- IMX_SC_R_MJPEG_DEC_S3
- IMX_SC_R_MJPEG_ENC_MP
- IMX_SC_R_MJPEG_ENC_S0
- IMX_SC_R_MJPEG_ENC_S1
- IMX_SC_R_MJPEG_ENC_S2
- IMX_SC_R_MJPEG_ENC_S3
- IMX_SC_R_MLB_0
- IMX_SC_R_MQS_0
- IMX_SC_R_MU_0A
- IMX_SC_R_MU_10A
- IMX_SC_R_MU_10B
- IMX_SC_R_MU_11A
- IMX_SC_R_MU_11B
- IMX_SC_R_MU_12A
- IMX_SC_R_MU_12B
- IMX_SC_R_MU_13A
- IMX_SC_R_MU_13B
- IMX_SC_R_MU_1A
- IMX_SC_R_MU_2A
- IMX_SC_R_MU_3A
- IMX_SC_R_MU_4A
- IMX_SC_R_MU_5A
- IMX_SC_R_MU_5B
- IMX_SC_R_MU_6A
- IMX_SC_R_MU_6B
- IMX_SC_R_MU_7A
- IMX_SC_R_MU_7B
- IMX_SC_R_MU_8A
- IMX_SC_R_MU_8B
- IMX_SC_R_MU_9A
- IMX_SC_R_MU_9B
- IMX_SC_R_NAND
- IMX_SC_R_OCRAM
- IMX_SC_R_OTP
- IMX_SC_R_PCIE_A
- IMX_SC_R_PCIE_B
- IMX_SC_R_PERF
- IMX_SC_R_PI_0
- IMX_SC_R_PI_0_I2C_0
- IMX_SC_R_PI_0_PLL
- IMX_SC_R_PI_0_PWM_0
- IMX_SC_R_PI_0_PWM_1
- IMX_SC_R_PI_1
- IMX_SC_R_PI_1_I2C_0
- IMX_SC_R_PI_1_PLL
- IMX_SC_R_PI_1_PWM_0
- IMX_SC_R_PI_1_PWM_1
- IMX_SC_R_PMIC_0
- IMX_SC_R_PMIC_1
- IMX_SC_R_PMIC_2
- IMX_SC_R_PWM_0
- IMX_SC_R_PWM_1
- IMX_SC_R_PWM_2
- IMX_SC_R_PWM_3
- IMX_SC_R_PWM_4
- IMX_SC_R_PWM_5
- IMX_SC_R_PWM_6
- IMX_SC_R_PWM_7
- IMX_SC_R_ROM_0
- IMX_SC_R_SAI_0
- IMX_SC_R_SAI_1
- IMX_SC_R_SAI_2
- IMX_SC_R_SAI_3
- IMX_SC_R_SAI_4
- IMX_SC_R_SAI_5
- IMX_SC_R_SAI_6
- IMX_SC_R_SAI_7
- IMX_SC_R_SATA_0
- IMX_SC_R_SC_I2C
- IMX_SC_R_SC_MU_0A0
- IMX_SC_R_SC_MU_0A1
- IMX_SC_R_SC_MU_0A2
- IMX_SC_R_SC_MU_0A3
- IMX_SC_R_SC_MU_0B
- IMX_SC_R_SC_MU_1A
- IMX_SC_R_SC_PID0
- IMX_SC_R_SC_PID1
- IMX_SC_R_SC_PID2
- IMX_SC_R_SC_PID3
- IMX_SC_R_SC_PID4
- IMX_SC_R_SC_PIT
- IMX_SC_R_SC_SEMA42
- IMX_SC_R_SC_TPM
- IMX_SC_R_SC_UART
- IMX_SC_R_SDHC_0
- IMX_SC_R_SDHC_1
- IMX_SC_R_SDHC_2
- IMX_SC_R_SECO
- IMX_SC_R_SECO_MU_2
- IMX_SC_R_SECO_MU_3
- IMX_SC_R_SECO_MU_4
- IMX_SC_R_SERDES_0
- IMX_SC_R_SERDES_1
- IMX_SC_R_SMMU
- IMX_SC_R_SNVS
- IMX_SC_R_SPDIF_0
- IMX_SC_R_SPDIF_1
- IMX_SC_R_SPI_0
- IMX_SC_R_SPI_1
- IMX_SC_R_SPI_2
- IMX_SC_R_SPI_3
- IMX_SC_R_SYSCNT_CMP
- IMX_SC_R_SYSCNT_RD
- IMX_SC_R_SYSTEM
- IMX_SC_R_UART_0
- IMX_SC_R_UART_1
- IMX_SC_R_UART_2
- IMX_SC_R_UART_3
- IMX_SC_R_UART_4
- IMX_SC_R_UNUSED1
- IMX_SC_R_UNUSED2
- IMX_SC_R_UNUSED3
- IMX_SC_R_UNUSED4
- IMX_SC_R_USB_0
- IMX_SC_R_USB_0_PHY
- IMX_SC_R_USB_1
- IMX_SC_R_USB_2
- IMX_SC_R_USB_2_PHY
- IMX_SC_R_VPU
- IMX_SC_R_VPUCORE
- IMX_SC_R_VPUCORE_0
- IMX_SC_R_VPUCORE_1
- IMX_SC_R_VPUCORE_2
- IMX_SC_R_VPUCORE_3
- IMX_SC_R_VPU_DEC_0
- IMX_SC_R_VPU_ENC_0
- IMX_SC_R_VPU_ENC_1
- IMX_SC_R_VPU_MU_0
- IMX_SC_R_VPU_MU_1
- IMX_SC_R_VPU_MU_2
- IMX_SC_R_VPU_MU_3
- IMX_SC_R_VPU_PID0
- IMX_SC_R_VPU_PID1
- IMX_SC_R_VPU_PID2
- IMX_SC_R_VPU_PID3
- IMX_SC_R_VPU_PID4
- IMX_SC_R_VPU_PID5
- IMX_SC_R_VPU_PID6
- IMX_SC_R_VPU_PID7
- IMX_SC_R_VPU_TS_0
- IMX_SC_R_VPU_UART
- IMX_SC_TIMER_FUNC_GET_RTC_SEC1970
- IMX_SC_TIMER_FUNC_SET_RTC_ALARM
- IMX_SC_TIMER_FUNC_SET_RTC_TIME
- IMX_SIP_CPUFREQ
- IMX_SIP_SET_CPUFREQ
- IMX_SIP_SRTC
- IMX_SIP_SRTC_SET_TIME
- IMX_SIP_TIMER
- IMX_SIP_TIMER_GET_WDOG_STAT
- IMX_SIP_TIMER_PING_WDOG
- IMX_SIP_TIMER_SET_PRETIME_WDOG
- IMX_SIP_TIMER_SET_TIMEOUT_WDOG
- IMX_SIP_TIMER_SET_WDOG_ACT
- IMX_SIP_TIMER_START_WDOG
- IMX_SIP_TIMER_STOP_WDOG
- IMX_SPDIF_DMABUF_SIZE
- IMX_SSI_DMA
- IMX_SSI_DMABUF_SIZE
- IMX_SSI_NET
- IMX_SSI_RX_DIV_2
- IMX_SSI_RX_DIV_PM
- IMX_SSI_RX_DIV_PSR
- IMX_SSI_SYN
- IMX_SSI_TX_DIV_2
- IMX_SSI_TX_DIV_PM
- IMX_SSI_TX_DIV_PSR
- IMX_SSI_USE_AC97
- IMX_SSI_USE_I2S_SLAVE
- IMX_SSP_SYS_CLK
- IMX_TIMER1MS
- IMX_TRIP_CRITICAL
- IMX_TRIP_NUM
- IMX_TRIP_PASSIVE
- IMX_TVE_DAC_VOLTAGE
- IMX_USE_SCU
- IMX_VDOA_H
- IMX_VPU_DEC_CLK
- IMX_VPU_ENC_CLK
- IM_ALLOC_INT
- IM_CTL
- IM_CTX_SIZE
- IM_EPH_INT
- IM_ERCV_INT
- IM_FID
- IM_MDINT
- IM_NS_ALIAS_OFFSET
- IM_R1
- IM_RCV_INT
- IM_REG
- IM_RX_OVRN_INT
- IM_SAP
- IM_SEQ
- IM_TX_EMPTY_INT
- IM_TX_INT
- IN
- IN00
- IN01
- IN1
- IN10
- IN11
- IN12_MON12
- IN12_MON34
- IN12_SEL
- IN2
- IN3
- IN32
- IN34_MON12
- IN34_MON34
- IN34_SEL
- IN4
- IN4500
- IN4_ADDR_HSIZE
- IN4_ADDR_HSIZE_SHIFT
- IN6ADDR_ANY_INIT
- IN6ADDR_INTERFACELOCAL_ALLNODES_INIT
- IN6ADDR_INTERFACELOCAL_ALLROUTERS_INIT
- IN6ADDR_LINKLOCAL_ALLNODES_INIT
- IN6ADDR_LINKLOCAL_ALLROUTERS_INIT
- IN6ADDR_LOOPBACK_INIT
- IN6ADDR_SITELOCAL_ALLROUTERS_INIT
- IN6PTON_COLON_1
- IN6PTON_COLON_1_2
- IN6PTON_COLON_2
- IN6PTON_COLON_MASK
- IN6PTON_DELIM
- IN6PTON_DIGIT
- IN6PTON_DOT
- IN6PTON_NULL
- IN6PTON_UNKNOWN
- IN6PTON_XDIGIT
- IN6_ADDR_GEN_MODE_EUI64
- IN6_ADDR_GEN_MODE_NONE
- IN6_ADDR_GEN_MODE_RANDOM
- IN6_ADDR_GEN_MODE_STABLE_PRIVACY
- IN6_ADDR_HSIZE
- IN6_ADDR_HSIZE_SHIFT
- IN6_ADDR_INITIALIZER
- INA209_BUS_VOLTAGE
- INA209_BUS_VOLTAGE_MAX_PEAK
- INA209_BUS_VOLTAGE_MIN_PEAK
- INA209_BUS_VOLTAGE_OVER_LIMIT
- INA209_BUS_VOLTAGE_OVER_WARN
- INA209_BUS_VOLTAGE_UNDER_LIMIT
- INA209_BUS_VOLTAGE_UNDER_WARN
- INA209_CALIBRATION
- INA209_CONFIGURATION
- INA209_CONFIG_DEFAULT
- INA209_CRITICAL_DAC_NEG
- INA209_CRITICAL_DAC_POS
- INA209_CURRENT
- INA209_POWER
- INA209_POWER_OVER_LIMIT
- INA209_POWER_PEAK
- INA209_POWER_WARN
- INA209_REGISTERS
- INA209_SHUNT_DEFAULT
- INA209_SHUNT_VOLTAGE
- INA209_SHUNT_VOLTAGE_NEG_PEAK
- INA209_SHUNT_VOLTAGE_NEG_WARN
- INA209_SHUNT_VOLTAGE_POS_PEAK
- INA209_SHUNT_VOLTAGE_POS_WARN
- INA209_STATUS
- INA209_STATUS_MASK
- INA219_BRNG_MASK
- INA219_BUS_VOLTAGE_SHIFT
- INA219_CHAN
- INA219_CHAN_VOLTAGE
- INA219_CNVR
- INA219_CONFIG_DEFAULT
- INA219_DEFAULT_BRNG
- INA219_DEFAULT_IT
- INA219_DEFAULT_PGA
- INA219_ITB_MASK
- INA219_ITS_MASK
- INA219_OVF
- INA219_PGA_MASK
- INA219_REGISTERS
- INA219_SHIFT_BRNG
- INA219_SHIFT_ITB
- INA219_SHIFT_ITS
- INA219_SHIFT_PGA
- INA226_ALERT_LIMIT
- INA226_AVG_MASK
- INA226_AVG_RD_MASK
- INA226_CHAN
- INA226_CHAN_VOLTAGE
- INA226_CONFIG_DEFAULT
- INA226_CVRF
- INA226_DEFAULT_AVG
- INA226_DEFAULT_IT
- INA226_DIE_ID
- INA226_ITB_MASK
- INA226_ITS_MASK
- INA226_MASK_ENABLE
- INA226_READ_AVG
- INA226_REGISTERS
- INA226_SHIFT_AVG
- INA226_SHIFT_ITB
- INA226_SHIFT_ITS
- INA226_TOTAL_CONV_TIME_DEFAULT
- INA2XX_BUS_VOLTAGE
- INA2XX_CALIBRATION
- INA2XX_CONFIG
- INA2XX_CONVERSION_RATE
- INA2XX_CURRENT
- INA2XX_MAX_ATTRIBUTE_GROUPS
- INA2XX_MAX_DELAY
- INA2XX_MAX_REGISTERS
- INA2XX_MODE_MASK
- INA2XX_POWER
- INA2XX_RSHUNT_DEFAULT
- INA2XX_SHUNT_VOLTAGE
- INA3221_BUS1
- INA3221_BUS2
- INA3221_BUS3
- INA3221_CHANNEL1
- INA3221_CHANNEL2
- INA3221_CHANNEL3
- INA3221_CONFIG
- INA3221_CONFIG_AVG
- INA3221_CONFIG_AVG_MASK
- INA3221_CONFIG_AVG_SHIFT
- INA3221_CONFIG_CHs_EN_MASK
- INA3221_CONFIG_CHx_EN
- INA3221_CONFIG_DEFAULT
- INA3221_CONFIG_MODE_BUS
- INA3221_CONFIG_MODE_CONTINUOUS
- INA3221_CONFIG_MODE_MASK
- INA3221_CONFIG_MODE_POWERDOWN
- INA3221_CONFIG_MODE_SHUNT
- INA3221_CONFIG_VBUS_CT
- INA3221_CONFIG_VBUS_CT_MASK
- INA3221_CONFIG_VBUS_CT_SHIFT
- INA3221_CONFIG_VSH_CT
- INA3221_CONFIG_VSH_CT_MASK
- INA3221_CONFIG_VSH_CT_SHIFT
- INA3221_CRIT1
- INA3221_CRIT2
- INA3221_CRIT3
- INA3221_DRIVER_NAME
- INA3221_HWMON_CURR_CONFIG
- INA3221_MASK_ENABLE
- INA3221_NUM_CHANNELS
- INA3221_RSHUNT_DEFAULT
- INA3221_SHUNT1
- INA3221_SHUNT2
- INA3221_SHUNT3
- INA3221_WARN1
- INA3221_WARN2
- INA3221_WARN3
- INACK_BUFLEN
- INACTIVE
- INACTIVE_CUS_MASK
- INACTIVE_CUS_SHIFT
- INACTIVE_MODE
- INACTIVE_QD_PIPES
- INACTIVE_QD_PIPES_MASK
- INACTIVE_QD_PIPES_SHIFT
- INACTIVE_RESET_AUDIO
- INACTIVE_SIMDS
- INACTIVE_SIMDS_MASK
- INACTIVE_SIMDS_SHIFT
- INACTIVE_STA_EVENT_ID
- INACTIVITY
- INACTIVITY_TIMEOUT
- INACTIV_TMRS_EXST
- INACTIV_TMR_BASE_MASK
- INACTIV_TMR_BASE_SHIFT
- INACT_ACDC
- INACT_X_EN
- INACT_Y_EN
- INACT_Z_EN
- INADDR_ALLHOSTS_GROUP
- INADDR_ALLRTRS_GROUP
- INADDR_ALLSNOOPERS_GROUP
- INADDR_ANY
- INADDR_BROADCAST
- INADDR_LOOPBACK
- INADDR_MAX_LOCAL_GROUP
- INADDR_NONE
- INADDR_UNSPEC_GROUP
- INAK_BI
- INAK_BO
- INAK_CI
- INAK_CO
- INAK_II
- INAK_IO
- INAND_CMD38_ARG_ERASE
- INAND_CMD38_ARG_EXT_CSD
- INAND_CMD38_ARG_SECERASE
- INAND_CMD38_ARG_SECTRIM1
- INAND_CMD38_ARG_SECTRIM2
- INAND_CMD38_ARG_TRIM
- INAT_ESC_BITS
- INAT_ESC_MASK
- INAT_ESC_MAX
- INAT_ESC_OFFS
- INAT_EVEXONLY
- INAT_FLAG_OFFS
- INAT_FORCE64
- INAT_GROUP_TABLE_SIZE
- INAT_GRP_BITS
- INAT_GRP_MASK
- INAT_GRP_MAX
- INAT_GRP_OFFS
- INAT_IMM_BITS
- INAT_IMM_BYTE
- INAT_IMM_DWORD
- INAT_IMM_MASK
- INAT_IMM_OFFS
- INAT_IMM_PTR
- INAT_IMM_QWORD
- INAT_IMM_VWORD
- INAT_IMM_VWORD32
- INAT_IMM_WORD
- INAT_LGCPFX_MAX
- INAT_LSTPFX_MAX
- INAT_MAKE_ESCAPE
- INAT_MAKE_GROUP
- INAT_MAKE_IMM
- INAT_MAKE_PREFIX
- INAT_MODRM
- INAT_MOFFSET
- INAT_OPCODE_TABLE_SIZE
- INAT_PFX_ADDRSZ
- INAT_PFX_BITS
- INAT_PFX_CS
- INAT_PFX_DS
- INAT_PFX_ES
- INAT_PFX_EVEX
- INAT_PFX_FS
- INAT_PFX_GS
- INAT_PFX_LOCK
- INAT_PFX_MASK
- INAT_PFX_MAX
- INAT_PFX_OFFS
- INAT_PFX_OPNDSZ
- INAT_PFX_REPE
- INAT_PFX_REPNE
- INAT_PFX_REX
- INAT_PFX_SS
- INAT_PFX_VEX2
- INAT_PFX_VEX3
- INAT_SCNDIMM
- INAT_SEG_REG_CS
- INAT_SEG_REG_DEFAULT
- INAT_SEG_REG_DS
- INAT_SEG_REG_ES
- INAT_SEG_REG_FS
- INAT_SEG_REG_GS
- INAT_SEG_REG_IGNORE
- INAT_SEG_REG_SS
- INAT_VARIANT
- INAT_VEXOK
- INAT_VEXONLY
- INB
- INBAND_ERROR
- INBAND_P
- INBAND_PACKET_MAX_LEN
- INBAND_POWER_THRSHLD_REG
- INBAND_S
- INBOUNDDOORBELL_0
- INBOUNDDOORBELL_1
- INBOUNDDOORBELL_2
- INBOUNDDOORBELL_3
- INBOUNDDOORBELL_4
- INBOUNDDOORBELL_5
- INBOUNDDOORBELL_6
- INBOUND_COMING_UP
- INBOUND_DOORBELL_REGISTER_CPU_SIDE
- INBOUND_DOORBELL_REGISTER_PCI_SIDE
- INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE
- INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE
- INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE
- INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE
- INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE
- INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE
- INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE
- INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE
- INBOUND_MESSAGE_REGISTER0_CPU_SIDE
- INBOUND_MESSAGE_REGISTER0_PCI_SIDE
- INBOUND_MESSAGE_REGISTER1_CPU_SIDE
- INBOUND_MESSAGE_REGISTER1_PCI_SIDE
- INBOUND_NOT_COMING_UP
- INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE
- INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE
- INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE
- INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE
- INBOUND_QUEUE_PORT
- INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE
- INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE
- INBOX_MASK
- INBUFM
- INB_OFF
- INC
- INCCRC
- INCLI_3D_CHANNEL_MAX
- INCLK_ASRCK1_CLK
- INCLK_ESAI_RX
- INCLK_ESAI_TX
- INCLK_MLB_CLK
- INCLK_NONE
- INCLK_PAD
- INCLK_SPDIF_RX
- INCLK_SPDIF_TX
- INCLK_SSI1_RX
- INCLK_SSI1_TX
- INCLK_SSI2_RX
- INCLK_SSI2_TX
- INCLK_SSI3_RX
- INCLK_SSI3_TX
- INCLUDE_ALLOW_MODULE
- INCLUDE_ALLOW_USERLEVEL
- INCLUDE_ALLOW_VMCORE
- INCLUDE_COMMENT
- INCLUDE_MMU_GENERAL_H_
- INCLUDE_MMU_V1_0_H_
- INCLUDE_MULTI_FUNC_BT
- INCLUDE_MULTI_FUNC_GPS
- INCLUDE_PCI_GENERAL_H_
- INCLUDE_XEN_OPS_H
- INCLUDE_XILINX_PCI
- INCLUDE__ARM_SPE_PKT_DECODER_H__
- INCLUDE__CS_ETM_DECODER_H__
- INCLUDE__INTEL_PT_DECODER_H__
- INCLUDE__INTEL_PT_INSN_DECODER_H__
- INCLUDE__INTEL_PT_LOG_H__
- INCLUDE__INTEL_PT_PKT_DECODER_H__
- INCLUDE__PERF_ARM_SPE_H__
- INCLUDE__PERF_CS_ETM_H__
- INCLUDE__PERF_INTEL_BTS_H__
- INCLUDE__PERF_INTEL_PT_H__
- INCLUDE__PERF_S390_CPUMSF_H
- INCLUDE__UTIL_PERF_CS_ETM_H__
- INCOMPAT_FEATURE_ON
- INCORRECT
- INCORRECTMIC
- INCORRECT_BASE_ADDR_LOW_BYTE
- INCPERIOD_24MHZ
- INCPERIOD_25MHZ
- INCPERIOD_38400KHZ
- INCPERIOD_82576
- INCPERIOD_96MHZ
- INCPERIOD_SHIFT_96MHZ
- INCR
- INCR16_EN
- INCR4_EN
- INCR8_EN
- INCREASED_MAX
- INCREMENT
- INCREMENTER_DENUMERATOR_RELOAD_OFFSET
- INCREMENTER_NUMERATOR_OFFSET
- INCREMENT_ARG_LIST
- INCRX_BURST_MODE
- INCRX_UNDEF_LENGTH_BURST_MODE
- INCR_INSTRQUEUE_PKT_COUNT
- INCR_LBRT_MSK
- INCR_LBRT_OFF
- INCVALUE_24MHZ
- INCVALUE_25MHZ
- INCVALUE_38400KHZ
- INCVALUE_82576
- INCVALUE_82576_MASK
- INCVALUE_96MHZ
- INCVALUE_MASK
- INCVALUE_SHIFT_24MHZ
- INCVALUE_SHIFT_25MHZ
- INCVALUE_SHIFT_38400KHZ
- INCVALUE_SHIFT_96MHZ
- INC_ACTIVATION
- INC_BIT
- INC_BITS
- INC_CACHE_INFO
- INC_DEC_CMD_ADDR
- INC_DIR_INODE_NLINK
- INC_IDX_ROUND
- INC_IVERSION
- INC_ORPHAN_COUNT
- INC_PERF_COUNTER
- INC_PROF
- INC_PTR
- INC_RETURN_FAMILY_TEST
- INC_STAT
- INC_VIF
- INC_X
- INC_Y
- INDADDR
- INDAT49W_BUFLEN
- INDCMD
- INDCMD_STATUS
- INDENT
- INDEX
- INDEX10
- INDEX12
- INDEX4
- INDEX4_SIZE_16_BIT
- INDEX4_SIZE_32_BIT
- INDEX4_SIZE_8_BIT
- INDEXER_NULL
- INDEXREG
- INDEX_0
- INDEX_16_COUNT
- INDEX_32_COUNT
- INDEX_64_COUNT
- INDEX_8
- INDEX_ACCESS_RANGE_BEGIN
- INDEX_ACCESS_RANGE_END
- INDEX_ADDRESS
- INDEX_ALLOCATION
- INDEX_AUDIO
- INDEX_BASE
- INDEX_BDADDR
- INDEX_BLOCK
- INDEX_BUSPOWER_ANALOG_ONLY
- INDEX_BUSPOWER_DIF_ONLY
- INDEX_BUSPOWER_DIGITAL_ANALOG
- INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL
- INDEX_BUSPOWER_DIGITAL_DIF
- INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL
- INDEX_BUSPOWER_DIGITAL_ONLY
- INDEX_BUSPOWER_EXTERNAL_ANALOG
- INDEX_BUSPOWER_EXTERNAL_DIF
- INDEX_BUSPOWER_EXTERNAL_DIGITAL
- INDEX_BUSPOWER_EXTERNAL_ONLY
- INDEX_CACHE_SIZE
- INDEX_CHANNEL
- INDEX_CSUM_XOR
- INDEX_DEBUG
- INDEX_DIMM
- INDEX_ENTRY
- INDEX_ENTRY_END
- INDEX_ENTRY_FLAGS
- INDEX_ENTRY_HEADER
- INDEX_ENTRY_NODE
- INDEX_ENTRY_SPACE_FILLER
- INDEX_ERROR
- INDEX_FIVE
- INDEX_FOUR
- INDEX_HANC
- INDEX_HEADER
- INDEX_HEADER_FLAGS
- INDEX_HIGH
- INDEX_INTERFACE_INFO
- INDEX_INTERRUPT
- INDEX_IR
- INDEX_LOW
- INDEX_MAC
- INDEX_MAPPING_NUM
- INDEX_MASK
- INDEX_MAX
- INDEX_MEMCTRL
- INDEX_NODE
- INDEX_NOT_CHECKED
- INDEX_NOT_FOUND
- INDEX_OK
- INDEX_ONE
- INDEX_PATH
- INDEX_PCB_CONFIG
- INDEX_PORT
- INDEX_REG
- INDEX_ROOT
- INDEX_SELFPOWER_ANALOG_ONLY
- INDEX_SELFPOWER_COMPRESSOR
- INDEX_SELFPOWER_DIGITAL_ONLY
- INDEX_SELFPOWER_DUAL
- INDEX_SELFPOWER_DUAL_DIGITAL
- INDEX_SELFPOWER_TRIPLE
- INDEX_SHIFT
- INDEX_SIZE_16_BIT
- INDEX_SIZE_32_BIT
- INDEX_SIZE_8_BIT
- INDEX_SIZE_IGN
- INDEX_SIZE_INVALID
- INDEX_SOCKET
- INDEX_THREE
- INDEX_TO_SEQ
- INDEX_TS1
- INDEX_TS2
- INDEX_TWO
- INDEX_VANC
- INDEX_VIDEO
- INDEX_ZERO
- INDICATOR_ALT_BLINK
- INDICATOR_ALT_BLINK_OFF
- INDICATOR_AMBER_BLINK
- INDICATOR_AMBER_BLINK_OFF
- INDICATOR_AUTO
- INDICATOR_CYCLE
- INDICATOR_GREEN_BLINK
- INDICATOR_GREEN_BLINK_OFF
- INDICATOR_INTENSITY
- INDICATOR_LAST
- INDICATOR_NOOP
- INDIC_N_BLANK_0
- INDIC_N_BLANK_1
- INDIC_N_BLANK_10
- INDIC_N_BLANK_11
- INDIC_N_BLANK_12
- INDIC_N_BLANK_13
- INDIC_N_BLANK_14
- INDIC_N_BLANK_15
- INDIC_N_BLANK_2
- INDIC_N_BLANK_3
- INDIC_N_BLANK_4
- INDIC_N_BLANK_5
- INDIC_N_BLANK_6
- INDIC_N_BLANK_7
- INDIC_N_BLANK_8
- INDIC_N_BLANK_9
- INDIC_PATTERN_SIZE
- INDIC_PERIOD_0
- INDIC_PERIOD_1
- INDIC_PERIOD_2
- INDIC_PERIOD_3
- INDIC_PERIOD_4
- INDIC_PERIOD_5
- INDIC_PERIOD_6
- INDIC_PERIOD_7
- INDIGO
- INDIGO_DJ
- INDIGO_DJX
- INDIGO_EXPRESS_32000
- INDIGO_EXPRESS_44100
- INDIGO_EXPRESS_48000
- INDIGO_EXPRESS_CLOCK_MASK
- INDIGO_EXPRESS_DOUBLE_SPEED
- INDIGO_EXPRESS_QUAD_SPEED
- INDIGO_FAMILY
- INDIGO_IO
- INDIGO_IOX
- INDIO_ALL_BUFFER_MODES
- INDIO_ALL_TRIGGERED_MODES
- INDIO_BUFFER_FLAG_FIXED_WATERMARK
- INDIO_BUFFER_HARDWARE
- INDIO_BUFFER_SOFTWARE
- INDIO_BUFFER_TRIGGERED
- INDIO_DIRECT_MODE
- INDIO_EVENT_TRIGGERED
- INDIO_HARDWARE_TRIGGERED
- INDIO_MAX_RAW_ELEMENTS
- INDIRCOUNT
- INDIRECT
- INDIRECT_ADDR
- INDIRECT_ADDRESS
- INDIRECT_ASSIGN
- INDIRECT_BUFFER_CACHE_POLICY
- INDIRECT_BUFFER_PRE_ENB
- INDIRECT_BUFFER_PRE_RESUME
- INDIRECT_BUFFER_TCL2_VOLATILE
- INDIRECT_BUFFER_VALID
- INDIRECT_CALIBRATION
- INDIRECT_CALLABLE_DECLARE
- INDIRECT_CALLABLE_SCOPE
- INDIRECT_CALL_1
- INDIRECT_CALL_2
- INDIRECT_CALL_INET
- INDIRECT_CALL_L4
- INDIRECT_CALL_OPCODE
- INDIRECT_CLEARBIT
- INDIRECT_CTX_ADDR_MASK
- INDIRECT_CTX_SIZE_MASK
- INDIRECT_GENERAL
- INDIRECT_GREFS
- INDIRECT_HOST
- INDIRECT_IO_ACCESS
- INDIRECT_IO_MC
- INDIRECT_IO_MC_READ
- INDIRECT_IO_MC_WRITE
- INDIRECT_IO_MM
- INDIRECT_IO_NBMISC
- INDIRECT_IO_NBMISC_READ
- INDIRECT_IO_NBMISC_WRITE
- INDIRECT_IO_PCIE
- INDIRECT_IO_PCIEP
- INDIRECT_IO_PCIEP_READ
- INDIRECT_IO_PCIEP_WRITE
- INDIRECT_IO_PCIE_READ
- INDIRECT_IO_PCIE_WRITE
- INDIRECT_IO_PLL
- INDIRECT_IO_PLL_READ
- INDIRECT_IO_PLL_WRITE
- INDIRECT_IO_SMU
- INDIRECT_IO_SMU_READ
- INDIRECT_IO_SMU_WRITE
- INDIRECT_LM_ADDR_0_BYTE_INDEX
- INDIRECT_LM_ADDR_1_BYTE_INDEX
- INDIRECT_OTHERS
- INDIRECT_PAGES
- INDIRECT_PROCESS_ADJST
- INDIRECT_READ
- INDIRECT_REGULATORY
- INDIRECT_SETBIT
- INDIRECT_THUNK
- INDIRECT_TXP_LIMIT
- INDIRECT_TXP_LIMIT_SIZE
- INDIRECT_TYPE_BIG_ENDIAN
- INDIRECT_TYPE_BROKEN_MRM
- INDIRECT_TYPE_EXT_REG
- INDIRECT_TYPE_MSK
- INDIRECT_TYPE_NO_PCIE_LINK
- INDIRECT_TYPE_SET_CFG_TYPE
- INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
- INDIRECT_WRITE
- INDIR_SPACE_MAP_SHIFT
- INDT
- INDUCTOR_I_LIMIT_MASK
- INDUCTOR_I_LIMIT_SHIFT
- IND_AB_UPDATED
- IND_ACC_TABLE
- IND_AP_ABITS
- IND_AP_ACTION
- IND_AP_LOCK
- IND_AX_EVNT
- IND_AX_FBCTRL
- IND_AX_IN
- IND_AX_MIN
- IND_AX_MOUT
- IND_AX_OUT
- IND_DESTINATION
- IND_DESTINATION_BIT
- IND_DONE
- IND_DONE_BIT
- IND_FLAGS
- IND_INDIRECTION
- IND_INDIRECTION_BIT
- IND_REG
- IND_SIS_AGP_IO_PAD
- IND_SIS_CMDQUEUE_SET
- IND_SIS_CMDQUEUE_THRESHOLD
- IND_SIS_COLOR_MODE
- IND_SIS_DRAM_SIZE
- IND_SIS_MODULE_ENABLE
- IND_SIS_PASSWORD
- IND_SIS_PCI_ADDRESS_SET
- IND_SIS_POWER_ON_TRAP
- IND_SIS_POWER_ON_TRAP2
- IND_SIS_RAMDAC_CONTROL
- IND_SIS_TURBOQUEUE_ADR
- IND_SIS_TURBOQUEUE_SET
- IND_SOURCE
- IND_SOURCE_BIT
- INEA
- INET6_ADDRSTRLEN
- INET6_IFADDR_STATE_DAD
- INET6_IFADDR_STATE_DEAD
- INET6_IFADDR_STATE_ERRDAD
- INET6_IFADDR_STATE_POSTDAD
- INET6_IFADDR_STATE_PREDAD
- INET6_MATCH
- INET6_PROTO_FINAL
- INET6_PROTO_GSO_EXTHDR
- INET6_PROTO_NOPOLICY
- INETPEER_MAXKEYSZ
- INETPEER_METRICS_NEW
- INETSW_ARRAY_LEN
- INET_ADDRSTRLEN
- INET_ADDR_COOKIE
- INET_COMBINED_PORTS
- INET_CSK_CLEAR_TIMERS
- INET_DIAG_BBRINFO
- INET_DIAG_BC_AUTO
- INET_DIAG_BC_DEV_COND
- INET_DIAG_BC_D_COND
- INET_DIAG_BC_D_EQ
- INET_DIAG_BC_D_GE
- INET_DIAG_BC_D_LE
- INET_DIAG_BC_JMP
- INET_DIAG_BC_MARK_COND
- INET_DIAG_BC_NOP
- INET_DIAG_BC_S_COND
- INET_DIAG_BC_S_EQ
- INET_DIAG_BC_S_GE
- INET_DIAG_BC_S_LE
- INET_DIAG_CLASS_ID
- INET_DIAG_CONG
- INET_DIAG_DCTCPINFO
- INET_DIAG_GETSOCK_MAX
- INET_DIAG_INFO
- INET_DIAG_LOCALS
- INET_DIAG_MARK
- INET_DIAG_MAX
- INET_DIAG_MD5SIG
- INET_DIAG_MEMINFO
- INET_DIAG_NOCOOKIE
- INET_DIAG_NONE
- INET_DIAG_PAD
- INET_DIAG_PEERS
- INET_DIAG_PROTOCOL
- INET_DIAG_REQ_BYTECODE
- INET_DIAG_REQ_MAX
- INET_DIAG_REQ_NONE
- INET_DIAG_SHUTDOWN
- INET_DIAG_SKMEMINFO
- INET_DIAG_SKV6ONLY
- INET_DIAG_TCLASS
- INET_DIAG_TOS
- INET_DIAG_ULP_INFO
- INET_DIAG_VEGASINFO
- INET_ECN_CE
- INET_ECN_ECT_0
- INET_ECN_ECT_1
- INET_ECN_MASK
- INET_ECN_NOT_ECT
- INET_ECN_decapsulate
- INET_ECN_dontxmit
- INET_ECN_encapsulate
- INET_ECN_is_capable
- INET_ECN_is_ce
- INET_ECN_is_not_ect
- INET_ECN_set_ce
- INET_ECN_set_ect1
- INET_ECN_xmit
- INET_FRAG_COMPLETE
- INET_FRAG_FIRST_IN
- INET_FRAG_HASH_DEAD
- INET_FRAG_LAST_IN
- INET_LHTABLE_SIZE
- INET_MATCH
- INET_NTOP_BUF
- INET_PROTOSW_ICSK
- INET_PROTOSW_PERMANENT
- INET_PROTOSW_REUSE
- INET_ULP_INFO_MAX
- INET_ULP_INFO_NAME
- INET_ULP_INFO_TLS
- INET_ULP_INFO_UNSPEC
- INEWNAME
- INEXACTEXCEPTION
- INEXACT_PREFIXLEN_IPV4
- INEXACT_PREFIXLEN_IPV6
- INEXIO_FORMAT_LENGTH
- INEXIO_FORMAT_TOUCH_BIT
- INEXIO_GET_TOUCHED
- INEXIO_GET_XC
- INEXIO_GET_YC
- INEXIO_MAX_LENGTH
- INEXIO_MAX_XC
- INEXIO_MAX_YC
- INEXIO_MIN_XC
- INEXIO_MIN_YC
- INEXIO_RESPONSE_BEGIN_BYTE
- INEXT
- INF
- INFBOUND
- INFINEON
- INFINEON_REV
- INFINEON_TRIBOARD_TC1798_PID
- INFINEON_TRIBOARD_TC2X7_PID
- INFINEON_VID
- INFINIBAND_ALEN
- INFINITE_CONS_TRANS
- INFINITY_LIFE_TIME
- INFLATE_H
- INFO
- INFO0
- INFO1
- INFO1_CLEAR
- INFO1_DTRANEND0
- INFO1_DTRANEND1
- INFO1_MASK_CLEAR
- INFO2
- INFO2_DTRANERR0
- INFO2_DTRANERR1
- INFO2_MASK_CLEAR
- INFO3_P10
- INFO3_P8
- INFO4_P10
- INFO4_P8
- INFO6
- INFOBIT
- INFOFRAME_AAI
- INFOFRAME_AVI
- INFOFRAME_CTRL_CHECKSUM_ENABLE
- INFOFRAME_CTRL_ENABLE
- INFOFRAME_CTRL_OTHER
- INFOFRAME_CTRL_SINGLE
- INFOFRAME_HEADER_LEN
- INFOFRAME_HEADER_TYPE
- INFOFRAME_HEADER_VERSION
- INFOFRAME_STATUS_DONE
- INFOFRAME_VSI
- INFOLEAF_SIZE
- INFOR
- INFORM
- INFO_BLOCK_BLK_CNT
- INFO_BLOCK_OFFSET
- INFO_BLOCK_REV
- INFO_BLOCK_RX_CHAN
- INFO_BLOCK_SIZE
- INFO_BLOCK_TX_CHAN
- INFO_BLOCK_TYPE
- INFO_COMMAND
- INFO_DBG
- INFO_ERR_STRUCT_TYPE_BUS
- INFO_ERR_STRUCT_TYPE_CACHE
- INFO_ERR_STRUCT_TYPE_MS
- INFO_ERR_STRUCT_TYPE_TLB
- INFO_FL_ALWAYS_COPY
- INFO_FL_CLEAR
- INFO_FL_CLEAR_MASK
- INFO_FL_CTRL
- INFO_FL_PRIO
- INFO_FL_QUEUE
- INFO_IS_TX
- INFO_LEAD
- INFO_OFFSET_BEBOB_VERSION
- INFO_OFFSET_GUID
- INFO_OFFSET_HW_MODEL_ID
- INFO_OFFSET_HW_MODEL_REVISION
- INFO_OFFSET_SW_DATE
- INFO_OUT_LEN
- INFO_PACKET_PACKET_INVALID
- INFO_PACKET_PACKET_RESET
- INFO_PACKET_PACKET_UPDATE_SCAN_TYPE
- INFO_PACKET_PACKET_VALID
- INFO_PACK_STATUS
- INFO_PORT
- INFO_QUERY_REG0
- INFO_QUERY_REG1
- INFO_QUERY_REG2
- INFO_QUERY_REG3
- INFO_STRING_LEN
- INFO_TYPE_APP
- INFO_TYPE_FB
- INFO_TYPE_MAX_PAGE_CNT
- INFO_VALID_CHECK_INFO
- INFO_VALID_IP
- INFO_VALID_REQUESTOR_ID
- INFO_VALID_RESPONDER_ID
- INFO_VALID_TARGET_ID
- INFO_VERSION
- INFO_XP70_FW_INITQUEUES
- INFO_XP70_FW_PROCESSING
- INFO_XP70_FW_READY
- INFO_ZONE
- INFO_bm_xfer_stats
- INFRA
- INFRASTRUCTURE_MODE
- INFRA_MISC2
- INFRA_NETWORK
- INFRA_RST0_SET_OFFSET
- INFRA_TIM_BASE
- INFRA_TOPAXI_PROTECTEN
- INFRA_TOPAXI_PROTECTEN_CLR
- INFRA_TOPAXI_PROTECTEN_SET
- INFRA_TOPAXI_PROTECTSTA1
- INFTLMediaHeader
- INFTLPartition
- INFTL_BBT_RESERVED_BLOCKS
- INFTL_BDTL
- INFTL_BINARY
- INFTL_LAST
- INFTL_MAJOR
- INFTL_PARTN_BITS
- INFTL_deleteblock
- INFTL_dumpVUchains
- INFTL_dumptables
- INFTL_findfreeblock
- INFTL_findwriteunit
- INFTL_foldchain
- INFTL_formatblock
- INFTL_makefreeblock
- INFTL_mount
- INFTL_trydeletechain
- INFTLrecord
- INFTREES_H
- INF_AUX_DIV_SHIFT
- INF_BURST_EN
- INF_DIVA20
- INF_DIVA201
- INF_DIVA202
- INF_DIVA20U
- INF_GAZEL_R685
- INF_GAZEL_R753
- INF_MAIN_DIV_SHIFT
- INF_MSG
- INF_NICCY
- INF_NONE
- INF_QS1000
- INF_QS3000
- INF_SAPHIR3
- INF_SCT_1
- INF_SCT_2
- INF_SCT_3
- INF_SCT_4
- INF_SPEEDWIN
- INF_UNIT_LEVEL_CLKGATE
- INGAMMA_MODE_BYPASS
- INGAMMA_MODE_FIX
- INGAMMA_MODE_FLOAT
- INGENIC_ADC_AUX
- INGENIC_ADC_BATTERY
- INGENIC_PIN_GROUP
- INGENIC_UART0_BASE_ADDR
- INGPACKBOUNDARY_16B_X
- INGPACKBOUNDARY_64B_X
- INGPACKBOUNDARY_G
- INGPACKBOUNDARY_M
- INGPACKBOUNDARY_S
- INGPACKBOUNDARY_SHIFT_X
- INGPACKBOUNDARY_V
- INGPADBOUNDARY_32B_X
- INGPADBOUNDARY_G
- INGPADBOUNDARY_M
- INGPADBOUNDARY_S
- INGPADBOUNDARY_SHIFT_X
- INGPADBOUNDARY_V
- INGPCIEBOUNDARY_32B_X
- INGPCIEBOUNDARY_S
- INGPCIEBOUNDARY_SHIFT_X
- INGPCIEBOUNDARY_V
- INGQ_EXTRAS
- INGRESSQID_S
- INGRESSQID_V
- INGRESS_CHECKSUM
- INGRESS_CHECKSUM_COMPUTE
- INGRESS_CRC
- INGRESS_FIFO_OVERRUN
- INGRESS_INVALID
- INGRESS_LINUM_IDX
- INGRESS_LISTEN_IDX
- INGRESS_PKT_LEN
- INGRESS_PKT_UNDER
- INGRESS_PURGE_RCVD
- INGRESS_REFRESHING
- INGRESS_RESOLVED
- INGRESS_RESOLVING
- INGRESS_SIZE_ERR_F
- INGRESS_SIZE_ERR_S
- INGRESS_SIZE_ERR_V
- INGRESS_TRUNC_FRAME
- INHERITED_ACE
- INHERIT_ONLY_ACE
- INHIBIT_UL_CHECK
- INIC_DMA_BOUNDARY
- INIMCS_SEL
- INIRTSMCS_SEL
- INIT
- INIT1
- INITBITS
- INITBLOCK_SLEEP
- INITCODEFILE
- INITCONTEXTLEN
- INITCTRL_NUM
- INITERR
- INITERROR
- INITFLAGS_DRIVER_SUPPORTS_HBA_MODE
- INITFLAGS_DRIVER_SUPPORTS_PM
- INITFLAGS_DRIVER_USES_UTC_TIME
- INITFLAGS_FAST_JBOD_SUPPORTED
- INITFLAGS_NEW_COMM_SUPPORTED
- INITFLAGS_NEW_COMM_TYPE1_SUPPORTED
- INITFLAGS_NEW_COMM_TYPE2_SUPPORTED
- INITIALISED
- INITIALIZATION_VALUE
- INITIALIZE
- INITIALIZE_CRYPT
- INITIALIZE_ELEMENT_STATUS
- INITIALIZE_KEY
- INITIALIZE_MGMT_STATUS
- INITIALIZE_PATH
- INITIALIZE_SUBTYPE
- INITIALR2T
- INITIAL_ADDRESS
- INITIAL_AGC_BW
- INITIAL_AUTHMETHOD
- INITIAL_AUTOLOAD_STATE
- INITIAL_BASER_VALUE
- INITIAL_BLOCKS_AVX
- INITIAL_BLOCKS_AVX2
- INITIAL_BLOCKS_ENC_DEC
- INITIAL_CHAIN_KEY
- INITIAL_CHECK_INTERVAL
- INITIAL_CRC
- INITIAL_CREDIT_PACKETS
- INITIAL_DATADIGEST
- INITIAL_DATAPDUINORDER
- INITIAL_DATASEQUENCEINORDER
- INITIAL_DEFAULTTIME2RETAIN
- INITIAL_DEFAULTTIME2WAIT
- INITIAL_DELAY
- INITIAL_ERRORRECOVERYLEVEL
- INITIAL_FIRSTBURSTLENGTH
- INITIAL_FREQ
- INITIAL_HEADERDIGEST
- INITIAL_IFMARKER
- INITIAL_IFMARKINT
- INITIAL_IMMEDIATEDATA
- INITIAL_INITIALR2T
- INITIAL_INITIATORALIAS
- INITIAL_INITIATORNAME
- INITIAL_INITIATORRECVDATASEGMENTLENGTH
- INITIAL_JIFFIES
- INITIAL_MAXBURSTLENGTH
- INITIAL_MAXCONNECTIONS
- INITIAL_MAXOUTSTANDINGR2T
- INITIAL_MAXRECVDATASEGMENTLENGTH
- INITIAL_MAXXMITDATASEGMENTLENGTH
- INITIAL_MAX_GAIN
- INITIAL_NET_GEN_PTRS
- INITIAL_OFMARKER
- INITIAL_OFMARKINT
- INITIAL_PENDBASER_VALUE
- INITIAL_PIPES_CAPACITY
- INITIAL_PRIO
- INITIAL_PROPBASER_VALUE
- INITIAL_RDMAEXTENSIONS
- INITIAL_SENDTARGETS
- INITIAL_SESSIONTYPE
- INITIAL_SRP_LIMIT
- INITIAL_STATE
- INITIAL_TARGETADDRESS
- INITIAL_TARGETALIAS
- INITIAL_TARGETNAME
- INITIAL_TARGETPORTALGROUPTAG
- INITIAL_TARGETRECVDATASEGMENTLENGTH
- INITIAL_TRAM_POS
- INITIAL_TRAM_SHIFT
- INITIAL_TX_RATE_REG
- INITIAL_VERSION_IOB
- INITIAL_VERSION_LB
- INITIAL_VERSION_LRB
- INITIATE_ATAPI_TASK
- INITIATE_ATA_TASK
- INITIATE_BIDIR_SSP_TASK
- INITIATE_DDB_ADM_TASK
- INITIATE_LINK_ADM_TASK
- INITIATE_LONG_SSP_TASK
- INITIATE_OCR
- INITIATE_RECOVERY
- INITIATE_SEQ_ADM_TASK
- INITIATE_SMP_TASK
- INITIATE_SSP_TASK
- INITIATE_SSP_TMF
- INITIATOR
- INITIATORALIAS
- INITIATORNAME
- INITIATORRECVDATASEGMENTLENGTH
- INITIATOR_BIT
- INITIATOR_COMMAND_REG
- INITIATOR_ERROR
- INITIATOR_WILDCARD
- INITOP_CLEAR
- INITOP_INIT
- INITOP_SET
- INITQFNAMES
- INITRD_MINOR
- INITRD_SIZE
- INITRD_SIZE_OFFSET
- INITRD_START
- INITRD_START_OFFSET
- INITREF_DIS_MASK
- INITREF_DIS_SHIFT
- INITSECTION
- INITSRTT_G
- INITSRTT_M
- INITSRTT_S
- INITTABSPTS
- INITVAL
- INITVALS_9003_2P2_H
- INITVALS_9003_BUFFALO_H
- INITVALS_9330_1P1_H
- INITVALS_9330_1P2_H
- INITVALS_9340_H
- INITVALS_9462_2P0_H
- INITVALS_9462_2P1_H
- INITVALS_9485_H
- INITVALS_953X_H
- INITVALS_955X_1P0_H
- INITVALS_9565_1P0_H
- INITVALS_9565_1P1_H
- INITVALS_956X_H
- INITVALS_9580_1P0_H
- INIT_8BIT
- INIT_ACTIVE_REQUEST
- INIT_ADAPTER
- INIT_ADDR4
- INIT_ADDR6
- INIT_AIFS
- INIT_ALLOC_SIZE
- INIT_ARCH_ELF_STATE
- INIT_ARCH_THREAD
- INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK
- INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT
- INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK
- INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT
- INIT_ARRAY_PATTERN_HDR_TYPE_MASK
- INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT
- INIT_ARRAY_RAW_HDR_PARAMS_MASK
- INIT_ARRAY_RAW_HDR_PARAMS_SHIFT
- INIT_ARRAY_RAW_HDR_TYPE_MASK
- INIT_ARRAY_RAW_HDR_TYPE_SHIFT
- INIT_ARRAY_SPEC
- INIT_ARRAY_STANDARD_HDR_SIZE_MASK
- INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT
- INIT_ARRAY_STANDARD_HDR_TYPE_MASK
- INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT
- INIT_ARRAY_ZIPPED_HDR_TYPE_MASK
- INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT
- INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK
- INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT
- INIT_ARR_PATTERN
- INIT_ARR_STANDARD
- INIT_ARR_ZIPPED
- INIT_ASPECT_RATIO
- INIT_BATCHCMD
- INIT_BAUD_RATE
- INIT_BCON_CNTRL_REG
- INIT_BIO
- INIT_BLOCK_RX_COMP
- INIT_BLOCK_RX_DESC
- INIT_BLOCK_RX_RING_SIZE
- INIT_BLOCK_TX
- INIT_BLOCK_TX_RING_SIZE
- INIT_BPP
- INIT_BRIGHT
- INIT_BUF
- INIT_BUFFER_SIZE
- INIT_BW
- INIT_CAL
- INIT_CALLBACK_OP_OP_MASK
- INIT_CALLBACK_OP_OP_SHIFT
- INIT_CALLBACK_OP_RESERVED_MASK
- INIT_CALLBACK_OP_RESERVED_SHIFT
- INIT_CALLS
- INIT_CALLS_LEVEL
- INIT_CAPS_ARRAY_SIZE
- INIT_CCENABLE_VALUE
- INIT_CDEX
- INIT_CIDR
- INIT_CK
- INIT_CLASS_FUNC
- INIT_CLKREG
- INIT_CLONE_SCALAR
- INIT_CLONE_STRING
- INIT_CLONE_STRUCT
- INIT_CMD
- INIT_CMD_COMPLETE
- INIT_CODE
- INIT_COMMAND_NO_RESPONSE
- INIT_COMMAND_WITH_RESPONSE
- INIT_COMPACT_PRIORITY
- INIT_COMPLETE_MSG
- INIT_COMPLETE_NOTIF
- INIT_CONFIG_STATUS
- INIT_CONG_COUNTER
- INIT_CONN_TAG
- INIT_COUNT_REG
- INIT_CPLT
- INIT_CPUMASK
- INIT_CPUTIME_ATOMIC
- INIT_CPU_DAI
- INIT_CPU_TIMERBASE
- INIT_CPU_TIMERBASES
- INIT_CPU_TIMERS
- INIT_CQR_ERROR
- INIT_CQR_OK
- INIT_CQR_UNFORMATTED
- INIT_CREDIT
- INIT_CRQ_CMD
- INIT_CRQ_COMP_CMD
- INIT_CRQ_COMP_RES
- INIT_CRQ_RES
- INIT_CSEM_INT_TABLE_DATA
- INIT_CSEM_PRAM_DATA
- INIT_CTX_ARB_VALUE
- INIT_CTX_ENABLE_VALUE
- INIT_CWMAX
- INIT_CWMIN
- INIT_CWMIN_11B
- INIT_C_CC
- INIT_DATA
- INIT_DATA_SECTION
- INIT_DBG
- INIT_DEFERRABLE_WORK
- INIT_DEFERRABLE_WORK_ONSTACK
- INIT_DELAYED_WORK
- INIT_DELAYED_WORK_ONSTACK
- INIT_DELAYED_WORK_RSL
- INIT_DELAY_OP_OP_MASK
- INIT_DELAY_OP_OP_SHIFT
- INIT_DELAY_OP_RESERVED_MASK
- INIT_DELAY_OP_RESERVED_SHIFT
- INIT_DEVCON0
- INIT_DEVCON1
- INIT_DIR_SIZE
- INIT_DISP_HORIZONTAL_SIZE
- INIT_DISP_VERTICAL_SIZE
- INIT_DMAE_C
- INIT_DONE
- INIT_EEPROM
- INIT_EFI_OP
- INIT_ENB
- INIT_END
- INIT_ERR
- INIT_EXTENDED_CFG_CMD
- INIT_EXT_PPCNT_COUNTER
- INIT_FAIL
- INIT_FAILURE
- INIT_FAN_CTRL
- INIT_FCS
- INIT_FEATURE_FLAGS
- INIT_FILELEN_MAX
- INIT_FPROP_LOCAL_SINGLE
- INIT_FRAME_RATE
- INIT_GLOBAL
- INIT_GPIO_DESC_MUXED
- INIT_HAL_MSG
- INIT_HAL_PTT_MSG
- INIT_HCA_ALTC_BASE_OFFSET
- INIT_HCA_AUXC_BASE_OFFSET
- INIT_HCA_CACHELINE_SZ_OFFSET
- INIT_HCA_CMPT_BASE_OFFSET
- INIT_HCA_CQC_BASE_OFFSET
- INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN
- INIT_HCA_DMPT_BASE_OFFSET
- INIT_HCA_DRIVER_VERSION_OFFSET
- INIT_HCA_DRIVER_VERSION_SZ
- INIT_HCA_EEC_BASE_OFFSET
- INIT_HCA_EEEC_BASE_OFFSET
- INIT_HCA_EQC_BASE_OFFSET
- INIT_HCA_EQE_CQE_OFFSETS
- INIT_HCA_EQE_CQE_STRIDE_OFFSET
- INIT_HCA_EQPC_BASE_OFFSET
- INIT_HCA_FLAGS1_OFFSET
- INIT_HCA_FLAGS2_OFFSET
- INIT_HCA_FLAGS_OFFSET
- INIT_HCA_FS_A0_OFFSET
- INIT_HCA_FS_BASE_OFFSET
- INIT_HCA_FS_ETH_BITS_OFFSET
- INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET
- INIT_HCA_FS_IB_BITS_OFFSET
- INIT_HCA_FS_IB_NUM_ADDRS_OFFSET
- INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET
- INIT_HCA_FS_LOG_TABLE_SZ_OFFSET
- INIT_HCA_FS_PARAM_OFFSET
- INIT_HCA_IN_SIZE
- INIT_HCA_LOG_CQ_OFFSET
- INIT_HCA_LOG_EEC_OFFSET
- INIT_HCA_LOG_EQ_OFFSET
- INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
- INIT_HCA_LOG_MC_HASH_SZ_OFFSET
- INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
- INIT_HCA_LOG_MPT_SZ_OFFSET
- INIT_HCA_LOG_QP_OFFSET
- INIT_HCA_LOG_RD_OFFSET
- INIT_HCA_LOG_SRQ_OFFSET
- INIT_HCA_LOG_UAR_SZ_OFFSET
- INIT_HCA_MCAST_OFFSET
- INIT_HCA_MC_BASE_OFFSET
- INIT_HCA_MC_HASH_SZ_OFFSET
- INIT_HCA_MPT_BASE_OFFSET
- INIT_HCA_MTT_BASE_OFFSET
- INIT_HCA_MTT_SEG_SZ_OFFSET
- INIT_HCA_NUM_SYS_EQS_OFFSET
- INIT_HCA_QPC_BASE_OFFSET
- INIT_HCA_QPC_OFFSET
- INIT_HCA_RDB_BASE_OFFSET
- INIT_HCA_RDMARC_BASE_OFFSET
- INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET
- INIT_HCA_SRQC_BASE_OFFSET
- INIT_HCA_TPT_MW_ENABLE
- INIT_HCA_TPT_MW_OFFSET
- INIT_HCA_TPT_OFFSET
- INIT_HCA_UARC_SZ_OFFSET
- INIT_HCA_UAR_BASE_OFFSET
- INIT_HCA_UAR_CTX_BASE_OFFSET
- INIT_HCA_UAR_OFFSET
- INIT_HCA_UAR_PAGE_SZ_OFFSET
- INIT_HCA_UAR_SCATCH_BASE_OFFSET
- INIT_HCA_UC_STEERING_OFFSET
- INIT_HCA_UDAV_LKEY_OFFSET
- INIT_HCA_UDAV_OFFSET
- INIT_HCA_UDAV_PD_OFFSET
- INIT_HCA_VERSION
- INIT_HCA_VERSION_OFFSET
- INIT_HCA_VXLAN_OFFSET
- INIT_HEADER
- INIT_HLIST_BL_HEAD
- INIT_HLIST_BL_NODE
- INIT_HLIST_HEAD
- INIT_HLIST_NODE
- INIT_HLIST_NULLS_HEAD
- INIT_HORIZONTAL_SIZE
- INIT_HVC
- INIT_HWRPB
- INIT_IB_EVENT_HANDLER
- INIT_IB_FLAGS_OFFSET
- INIT_IB_FLAG_G0
- INIT_IB_FLAG_NG
- INIT_IB_FLAG_SIG
- INIT_IB_GUID0_OFFSET
- INIT_IB_IN_SIZE
- INIT_IB_MAX_GID_OFFSET
- INIT_IB_MAX_PKEY_OFFSET
- INIT_IB_MTU_SHIFT
- INIT_IB_NODE_GUID_OFFSET
- INIT_IB_PORT_WIDTH_SHIFT
- INIT_IB_SI_GUID_OFFSET
- INIT_IB_VL_SHIFT
- INIT_IF_MODE_OP_CMD_OFFSET_MASK
- INIT_IF_MODE_OP_CMD_OFFSET_SHIFT
- INIT_IF_MODE_OP_OP_MASK
- INIT_IF_MODE_OP_OP_SHIFT
- INIT_IF_MODE_OP_RESERVED1_MASK
- INIT_IF_MODE_OP_RESERVED1_SHIFT
- INIT_IF_PHASE_OP_CMD_OFFSET_MASK
- INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT
- INIT_IF_PHASE_OP_DMAE_ENABLE_MASK
- INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT
- INIT_IF_PHASE_OP_OP_MASK
- INIT_IF_PHASE_OP_OP_SHIFT
- INIT_IF_PHASE_OP_PHASE_ID_MASK
- INIT_IF_PHASE_OP_PHASE_ID_SHIFT
- INIT_IF_PHASE_OP_PHASE_MASK
- INIT_IF_PHASE_OP_PHASE_SHIFT
- INIT_IF_PHASE_OP_RESERVED1_MASK
- INIT_IF_PHASE_OP_RESERVED1_SHIFT
- INIT_IF_PHASE_OP_RESERVED2_MASK
- INIT_IF_PHASE_OP_RESERVED2_SHIFT
- INIT_INFO
- INIT_INI_ARRAY
- INIT_INPUT_ACPI
- INIT_INPUT_WMI_0
- INIT_INPUT_WMI_2
- INIT_IQK
- INIT_JMP_CALLBACK
- INIT_JMP_HALT
- INIT_JMP_NEW_THREAD
- INIT_JMP_REBOOT
- INIT_KBD_LED
- INIT_KEY
- INIT_KEYS_EACH_TIME
- INIT_KEYS_SLEEP_MS
- INIT_KFIFO
- INIT_LG_RETRY
- INIT_LINK_VAR
- INIT_LIST_HEAD
- INIT_LIST_HEAD_RCU
- INIT_LOG_COUNT
- INIT_LOOP
- INIT_LOOP_DELAY
- INIT_MEMBLOCK_REGIONS
- INIT_MEMBLOCK_RESERVED_REGIONS
- INIT_MMAP
- INIT_MM_CONTEXT
- INIT_MODE_FLAGS
- INIT_MODE_FLIPPED
- INIT_MODE_OP_AND
- INIT_MODE_OP_NOT
- INIT_MODE_OP_OR
- INIT_MODE_ROTATED
- INIT_MSG
- INIT_MSG_INIT
- INIT_MT7530_DUMMY_POLL
- INIT_MX_RETRIES
- INIT_NDP16_OPTS
- INIT_NDP32_OPTS
- INIT_NETDEV_GROUP
- INIT_NOTFOUND
- INIT_OFFSET_MASK
- INIT_OPS
- INIT_OPS_HASH
- INIT_OPS_OFFSETS
- INIT_OP_CALLBACK
- INIT_OP_DELAY
- INIT_OP_IF_MODE
- INIT_OP_IF_PHASE
- INIT_OP_READ
- INIT_OP_WRITE
- INIT_PC_VALUE
- INIT_PER_CPU
- INIT_PER_CPU_VAR
- INIT_PGD
- INIT_PGD_PAGE_COUNT
- INIT_PGT_BUF_SIZE
- INIT_PH
- INIT_PHYSMEM_REGIONS
- INIT_POLL_AND
- INIT_POLL_DELAY
- INIT_POLL_EQ
- INIT_POLL_NONE
- INIT_POLL_OR
- INIT_POLL_TIMEOUT
- INIT_PORT_DCB_CMD
- INIT_PORT_DCB_READ_LOCAL_CMD
- INIT_PORT_DCB_READ_PEER_CMD
- INIT_PORT_DCB_READ_SYNC_CMD
- INIT_PORT_DCB_WRITE_CMD
- INIT_PORT_FLAGS_OFFSET
- INIT_PORT_FLAG_G0
- INIT_PORT_FLAG_NG
- INIT_PORT_FLAG_SIG
- INIT_PORT_GUID0_OFFSET
- INIT_PORT_IN_SIZE
- INIT_PORT_MAX_GID_OFFSET
- INIT_PORT_MAX_PKEY_OFFSET
- INIT_PORT_MTU_OFFSET
- INIT_PORT_NODE_GUID_OFFSET
- INIT_PORT_PORT_WIDTH_SHIFT
- INIT_PORT_SI_GUID_OFFSET
- INIT_PORT_VL_SHIFT
- INIT_PREEMPT_COUNT
- INIT_PREV_CPUTIME
- INIT_QC_COMMON
- INIT_QUOTA_MODULE_NAMES
- INIT_Q_COUNTER
- INIT_RADIX_TREE
- INIT_RAM_FS
- INIT_RAW_OP_OP_MASK
- INIT_RAW_OP_OP_SHIFT
- INIT_RAW_OP_PARAM1_MASK
- INIT_RAW_OP_PARAM1_SHIFT
- INIT_RCU_WORK
- INIT_RCU_WORK_ONSTACK
- INIT_RDMA_OBJ_SIZE
- INIT_READY
- INIT_READ_OP_ADDRESS_MASK
- INIT_READ_OP_ADDRESS_SHIFT
- INIT_READ_OP_OP_MASK
- INIT_READ_OP_OP_SHIFT
- INIT_READ_OP_POLL_TYPE_MASK
- INIT_READ_OP_POLL_TYPE_SHIFT
- INIT_READ_OP_RESERVED_MASK
- INIT_READ_OP_RESERVED_SHIFT
- INIT_REGALLOC
- INIT_REGMAP_IRQ
- INIT_REGULATOR_REGISTER
- INIT_RESOURCE_LENGTH
- INIT_RESOURCE_TYPE
- INIT_RETRIES
- INIT_RF
- INIT_RHT_NULLS_HEAD
- INIT_RING_BEFORE_START
- INIT_RLIMITS
- INIT_RSSI_THR
- INIT_SAS_EVENT
- INIT_SAS_WORK
- INIT_SBICDMA
- INIT_SCALAR_none
- INIT_SCALAR_zero
- INIT_SCSI_NL_HDR
- INIT_SC_PER_VL
- INIT_SECTIONS
- INIT_SELTD
- INIT_SETUP
- INIT_SHORTNAME_INFO
- INIT_SHRAM_CONSTANTS_TABLE_SZ
- INIT_SH_RETRY
- INIT_SIG_EVENTS_VALUE
- INIT_SIZE
- INIT_SLG_RETRY
- INIT_SOCKS
- INIT_SP
- INIT_SPARSE_KEYMAP
- INIT_SP_LIMIT
- INIT_SRC_ARRAY
- INIT_SRC_INLINE
- INIT_SRC_RUNTIME
- INIT_SRC_ZEROS
- INIT_SSH_RETRY
- INIT_SSP_REGS
- INIT_STACK
- INIT_STAT
- INIT_STATE
- INIT_STATE_AFU
- INIT_STATE_CDEV
- INIT_STATE_NONE
- INIT_STATE_PCI
- INIT_STATE_SCSI
- INIT_STATUS
- INIT_STREAM
- INIT_STREAM_CMD
- INIT_STRING_none
- INIT_STRING_zero
- INIT_STRUCT_BASE_ADDRESS
- INIT_STRUCT_STAT64_PADDING
- INIT_STRUCT_STAT_PADDING
- INIT_STRUCT_dynamic_all
- INIT_STRUCT_dynamic_partial
- INIT_STRUCT_none
- INIT_STRUCT_runtime_all
- INIT_STRUCT_runtime_partial
- INIT_STRUCT_static_all
- INIT_STRUCT_static_partial
- INIT_STRUCT_zero
- INIT_SUM
- INIT_TABLE_LENGTH
- INIT_TASK_COMM
- INIT_TASK_DATA
- INIT_TASK_DATA_SECTION
- INIT_TEXT
- INIT_TEXT_SECTION
- INIT_THREAD
- INIT_THREAD_INFO
- INIT_THREAD_PM
- INIT_THRESHOLD
- INIT_TIMEOUT
- INIT_TIMEOUT_MS
- INIT_TIMEOUT_MSECS
- INIT_TIMEOUT_SECS
- INIT_TIMER_AFTER_SUSPEND
- INIT_TIMER_RAND_STATE
- INIT_TPAD_LED
- INIT_TP_WR
- INIT_TP_WR_CPL
- INIT_TRACE_IRQFLAGS
- INIT_TREE_NODE_ARRAY_SIZE
- INIT_TSEM_INT_TABLE_DATA
- INIT_TSEM_PRAM_DATA
- INIT_TXPOWER
- INIT_ULPTX_WR
- INIT_UNCHECKED
- INIT_USEM_INT_TABLE_DATA
- INIT_USEM_PRAM_DATA
- INIT_USER
- INIT_VERTICAL_SIZE
- INIT_VOL
- INIT_WAIT_MS
- INIT_WAIT_MSECS
- INIT_WAKEUP_EVENTS_VALUE
- INIT_WORK
- INIT_WORK_ONSTACK
- INIT_WORK_RSL
- INIT_WRITE_OP_ADDRESS_MASK
- INIT_WRITE_OP_ADDRESS_SHIFT
- INIT_WRITE_OP_OP_MASK
- INIT_WRITE_OP_OP_SHIFT
- INIT_WRITE_OP_RESERVED_MASK
- INIT_WRITE_OP_RESERVED_SHIFT
- INIT_WRITE_OP_SOURCE_MASK
- INIT_WRITE_OP_SOURCE_SHIFT
- INIT_WRITE_OP_WIDE_BUS_MASK
- INIT_WRITE_OP_WIDE_BUS_SHIFT
- INIT_XBUS_CYCLE
- INIT_XBUS_STROBE
- INIT_XRES
- INIT_XSEM_INT_TABLE_DATA
- INIT_XSEM_PRAM_DATA
- INIT_YRES
- INIT_ZONE
- INI_IO_ABORTED
- INI_IO_ACTIVE
- INI_IO_COMPLETED
- INI_IO_START
- INI_NOPOUT_CMD
- INI_QUEUE_FULL
- INI_RA
- INI_RD_CMD
- INI_SIGNATURE
- INI_TMF_CMD
- INI_WR_CMD
- INJECT
- INJECT_ADDR_PARITY
- INJECT_ASM_REG
- INJECT_ASM_REG_P
- INJECT_DST
- INJECT_ECC
- INJECT_ERROR_MASK
- INJECT_NONE
- INJECT_SRC
- INL
- INLCR
- INLINE
- INLINEEA
- INLINE_COMMENT
- INLINE_COPY_FROM_USER
- INLINE_COPY_TO_USER
- INLINE_DENTRY_BITMAP_SIZE
- INLINE_EXTENT_BUFFER_PAGES
- INLINE_RESERVED_SIZE
- INLINE_RESULT_H
- INLOOP
- INL_CONFIG_FRAMETRAP
- INL_CONFIG_MANUALRUN
- INL_CONFIG_NOTHING
- INL_CONFIG_RXANNEX
- INL_CONFIG_TXANNEX
- INL_CONFIG_WDS
- INL_HDR_START_SZ
- INL_MODE_AP
- INL_MODE_CLIENT
- INL_MODE_NONE
- INL_MODE_PROMISCUOUS
- INL_MODE_SNIFFER
- INL_OFF
- INL_PHYCAP_2400MHZ
- INL_PHYCAP_5000MHZ
- INL_PHYCAP_FAA
- INMC
- INMEM
- INMEM_DROP
- INMEM_INVALIDATE
- INMEM_PAGES
- INMEM_REVOKE
- INNER_CLSS_DISABLED
- INNER_CLSS_USE_VLAN
- INNER_CLSS_USE_VNI
- INNER_DST_IP
- INNER_DST_MAC
- INNER_DST_PORT
- INNER_ETH_TYPE
- INNER_IP_PROTO
- INNER_IP_TOS
- INNER_L2_RSV
- INNER_L3_RSV
- INNER_L4_RSV
- INNER_LOOP_BACK_MODE_MASK
- INNER_LOOP_BACK_MODE_MASK_SFT
- INNER_LOOP_BACK_MODE_SFT
- INNER_LRU_HASH_PREALLOC
- INNER_PROVIDER_VLAN
- INNER_SRC_IP
- INNER_SRC_MAC
- INNER_SRC_PORT
- INNER_VLAN
- INNER_VLAN_TAG_FST
- INNER_VLAN_TAG_SEC
- INNOVATOR1610_ETHR_START
- INNOVATOR_FPGA_CAM_USB_CONTROL
- INNOVATOR_FPGA_EXP_CONTROL
- INNOVATOR_FPGA_HID_SPI
- INNOVATOR_FPGA_IMR2
- INNOVATOR_FPGA_INFO
- INNOVATOR_FPGA_ISR2
- INNOVATOR_FPGA_LCD_BRIGHT_HI
- INNOVATOR_FPGA_LCD_BRIGHT_LO
- INNOVATOR_FPGA_LED_GRN_HI
- INNOVATOR_FPGA_LED_GRN_LO
- INNOVATOR_FPGA_LED_RED_HI
- INNOVATOR_FPGA_LED_RED_LO
- INNO_HP_GAIN_0DB
- INNO_HP_GAIN_N39DB
- INNO_HP_GAIN_SHIFT
- INNO_PHY_PORT_NUM
- INNO_R00
- INNO_R00_CDCR_RESET
- INNO_R00_CDCR_WORK
- INNO_R00_CSR_RESET
- INNO_R00_CSR_WORK
- INNO_R00_PRB_DISABLE
- INNO_R00_PRB_ENABLE
- INNO_R01
- INNO_R01_I2SMODE_MASTER
- INNO_R01_I2SMODE_MSK
- INNO_R01_I2SMODE_SLAVE
- INNO_R01_PINDIR_IN_SLAVE
- INNO_R01_PINDIR_MSK
- INNO_R01_PINDIR_OUT_MASTER
- INNO_R02
- INNO_R02_DACM_I2S
- INNO_R02_DACM_LJM
- INNO_R02_DACM_MSK
- INNO_R02_DACM_PCM
- INNO_R02_DACM_RJM
- INNO_R02_LRCP_MSK
- INNO_R02_LRCP_NORMAL
- INNO_R02_LRCP_REVERSAL
- INNO_R02_LRS_MSK
- INNO_R02_LRS_NORMAL
- INNO_R02_LRS_SWAP
- INNO_R02_VWL_16BIT
- INNO_R02_VWL_20BIT
- INNO_R02_VWL_24BIT
- INNO_R02_VWL_32BIT
- INNO_R02_VWL_MSK
- INNO_R03
- INNO_R03_BCP_MSK
- INNO_R03_BCP_NORMAL
- INNO_R03_BCP_REVERSAL
- INNO_R03_DACR_MSK
- INNO_R03_DACR_RESET
- INNO_R03_DACR_WORK
- INNO_R03_FWL_16BIT
- INNO_R03_FWL_20BIT
- INNO_R03_FWL_24BIT
- INNO_R03_FWL_32BIT
- INNO_R03_FWL_MSK
- INNO_R04
- INNO_R04_DACL_CLK_SHIFT
- INNO_R04_DACL_SW_SHIFT
- INNO_R04_DACL_VREF_SHIFT
- INNO_R04_DACR_CLK_SHIFT
- INNO_R04_DACR_SW_SHIFT
- INNO_R04_DACR_VREF_SHIFT
- INNO_R05
- INNO_R05_HPL_EN_SHIFT
- INNO_R05_HPL_WORK_SHIFT
- INNO_R05_HPR_EN_SHIFT
- INNO_R05_HPR_WORK_SHIFT
- INNO_R06
- INNO_R06_DACL_HILO_VREF_SHIFT
- INNO_R06_DACR_HILO_VREF_SHIFT
- INNO_R06_DAC_DISCHARGE
- INNO_R06_DAC_EN_SHIFT
- INNO_R06_DAC_PRECHARGE
- INNO_R06_VOUTL_CZ_SHIFT
- INNO_R06_VOUTR_CZ_SHIFT
- INNO_R07
- INNO_R08
- INNO_R09
- INNO_R09_DACL_SWITCH_SHIFT
- INNO_R09_DACR_SWITCH_SHIFT
- INNO_R09_HPL_ANITPOP_SHIFT
- INNO_R09_HPL_MUTE_SHIFT
- INNO_R09_HPR_ANITPOP_SHIFT
- INNO_R09_HPR_MUTE_SHIFT
- INNO_R09_HP_ANTIPOP_MSK
- INNO_R09_HP_ANTIPOP_OFF
- INNO_R09_HP_ANTIPOP_ON
- INNO_R10
- INNO_R10_CHARGE_SEL_CUR_027I_NO
- INNO_R10_CHARGE_SEL_CUR_027I_YES
- INNO_R10_CHARGE_SEL_CUR_050I_NO
- INNO_R10_CHARGE_SEL_CUR_050I_YES
- INNO_R10_CHARGE_SEL_CUR_100I_NO
- INNO_R10_CHARGE_SEL_CUR_100I_YES
- INNO_R10_CHARGE_SEL_CUR_130I_NO
- INNO_R10_CHARGE_SEL_CUR_130I_YES
- INNO_R10_CHARGE_SEL_CUR_260I_NO
- INNO_R10_CHARGE_SEL_CUR_260I_YES
- INNO_R10_CHARGE_SEL_CUR_400I_NO
- INNO_R10_CHARGE_SEL_CUR_400I_YES
- INNO_R10_MAX_CUR
- INOCACHE_HASHSIZE_MAX
- INOCACHE_HASHSIZE_MIN
- INODESLOTSIZE
- INODES_PER_BITMAP
- INODE_ALLOC_SYSTEM_INODE
- INODE_BITMAP
- INODE_CACHE
- INODE_COST
- INODE_EXTENT_SIZE
- INODE_INFO
- INODE_ITEM
- INODE_JOURNAL
- INODE_OFFSET
- INODE_PKEY
- INODE_TABLE
- INODE_VERSION
- INOHINT
- INOPBLK
- INORDER
- INOSPEREXT
- INOSPERIAG
- INOSPERPAGE
- INOTIFY_E
- INOTIFY_IOC_SETNEXTWD
- INOTIFY_MAX_QUEUED_EVENTS
- INOTIFY_MAX_USER_INSTANCES
- INOTIFY_MAX_USER_WATCHES
- INOTOIAG
- INOUTEPMPSR_MPS
- INOUTEPMPSR_RESET_TSEQ
- INOUTEPMPSR_STL_EP
- INOUTSEL
- INOUT_C
- INOUT_C_MASK
- INOUT_C_SHIFT
- INOVIA_SEW858
- INOVIA_VENDOR_ID
- INO_ENTRIES
- INO_FLAGS_IS_DIR
- INO_FLAGS_XATTR_CHECKED
- INO_STATE_CHECKEDABSENT
- INO_STATE_CHECKING
- INO_STATE_CLEARING
- INO_STATE_GC
- INO_STATE_PRESENT
- INO_STATE_READING
- INO_STATE_UNCHECKED
- INP
- INPACK
- INPCK
- INPH_IA_DEV
- INPH_IA_VCC
- INPINE
- INPLL
- INPORT_BASE
- INPORT_CONTROL_PORT
- INPORT_DATA_PORT
- INPORT_EXTENT
- INPORT_IRQ
- INPORT_MODE_BASE
- INPORT_MODE_HOLD
- INPORT_MODE_IRQ
- INPORT_NAME
- INPORT_REG_BTNS
- INPORT_REG_MODE
- INPORT_REG_X
- INPORT_REG_Y
- INPORT_RESET
- INPORT_SIGNATURE_PORT
- INPORT_SPEED_100HZ
- INPORT_SPEED_200HZ
- INPORT_SPEED_30HZ
- INPORT_SPEED_50HZ
- INPORT_VENDOR
- INPUT
- INPUT1
- INPUT2
- INPUTACTION_KEY_DOWN
- INPUTACTION_KEY_DOWN_UP
- INPUTACTION_KEY_UP
- INPUTACTION_MOUSE_BUTTON_CLICK
- INPUTACTION_MOUSE_BUTTON_DCLICK
- INPUTACTION_MOUSE_BUTTON_DOWN
- INPUTACTION_MOUSE_BUTTON_UP
- INPUTACTION_SET_LOCKING_KEY_STATE
- INPUTACTION_WHEEL_ROTATE_AWAY
- INPUTACTION_WHEEL_ROTATE_TOWARD
- INPUTACTION_XY_MOTION
- INPUTBOX_HEIGTH_MIN
- INPUTBOX_WIDTH_MIN
- INPUTCSC_MODE_A
- INPUTCSC_MODE_B
- INPUTCSC_MODE_BYPASS
- INPUTCSC_MODE_UNITY
- INPUTCSC_ROUND
- INPUTCSC_TRUNCATE
- INPUTCSC_TYPE_10_2
- INPUTCSC_TYPE_12_0
- INPUTCSC_TYPE_8_4
- INPUTGAIN_RANGE_SHIFT
- INPUTSTATOFFSET
- INPUTVSC_RECV_RING_BUFFER_SIZE
- INPUTVSC_SEND_RING_BUFFER_SIZE
- INPUT_ADC_LEVEL
- INPUT_ADD_HOTPLUG_BM_VAR
- INPUT_ADD_HOTPLUG_MODALIAS_VAR
- INPUT_ADD_HOTPLUG_VAR
- INPUT_AVAIL
- INPUT_B0
- INPUT_B1
- INPUT_B2
- INPUT_B3
- INPUT_B4
- INPUT_B5
- INPUT_B6
- INPUT_B7
- INPUT_BOX
- INPUT_CLEANSE_BITMASK
- INPUT_CLK_BOOT
- INPUT_CLK_MAX
- INPUT_CLK_MONO
- INPUT_CLK_REAL
- INPUT_COVERAGE
- INPUT_CSC_BYPASS
- INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A_MASK
- INPUT_CSC_C11_C12_A__INPUT_CSC_C11_A__SHIFT
- INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A_MASK
- INPUT_CSC_C11_C12_A__INPUT_CSC_C12_A__SHIFT
- INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B_MASK
- INPUT_CSC_C11_C12_B__INPUT_CSC_C11_B__SHIFT
- INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B_MASK
- INPUT_CSC_C11_C12_B__INPUT_CSC_C12_B__SHIFT
- INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK
- INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT
- INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK
- INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT
- INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A_MASK
- INPUT_CSC_C13_C14_A__INPUT_CSC_C13_A__SHIFT
- INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A_MASK
- INPUT_CSC_C13_C14_A__INPUT_CSC_C14_A__SHIFT
- INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B_MASK
- INPUT_CSC_C13_C14_B__INPUT_CSC_C13_B__SHIFT
- INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B_MASK
- INPUT_CSC_C13_C14_B__INPUT_CSC_C14_B__SHIFT
- INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK
- INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT
- INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK
- INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT
- INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A_MASK
- INPUT_CSC_C21_C22_A__INPUT_CSC_C21_A__SHIFT
- INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A_MASK
- INPUT_CSC_C21_C22_A__INPUT_CSC_C22_A__SHIFT
- INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B_MASK
- INPUT_CSC_C21_C22_B__INPUT_CSC_C21_B__SHIFT
- INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B_MASK
- INPUT_CSC_C21_C22_B__INPUT_CSC_C22_B__SHIFT
- INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK
- INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT
- INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK
- INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT
- INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A_MASK
- INPUT_CSC_C23_C24_A__INPUT_CSC_C23_A__SHIFT
- INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A_MASK
- INPUT_CSC_C23_C24_A__INPUT_CSC_C24_A__SHIFT
- INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B_MASK
- INPUT_CSC_C23_C24_B__INPUT_CSC_C23_B__SHIFT
- INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B_MASK
- INPUT_CSC_C23_C24_B__INPUT_CSC_C24_B__SHIFT
- INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK
- INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT
- INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK
- INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT
- INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A_MASK
- INPUT_CSC_C31_C32_A__INPUT_CSC_C31_A__SHIFT
- INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A_MASK
- INPUT_CSC_C31_C32_A__INPUT_CSC_C32_A__SHIFT
- INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B_MASK
- INPUT_CSC_C31_C32_B__INPUT_CSC_C31_B__SHIFT
- INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B_MASK
- INPUT_CSC_C31_C32_B__INPUT_CSC_C32_B__SHIFT
- INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK
- INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT
- INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK
- INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT
- INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A_MASK
- INPUT_CSC_C33_C34_A__INPUT_CSC_C33_A__SHIFT
- INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A_MASK
- INPUT_CSC_C33_C34_A__INPUT_CSC_C34_A__SHIFT
- INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B_MASK
- INPUT_CSC_C33_C34_B__INPUT_CSC_C33_B__SHIFT
- INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B_MASK
- INPUT_CSC_C33_C34_B__INPUT_CSC_C34_B__SHIFT
- INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK
- INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT
- INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK
- INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT
- INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK
- INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
- INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK
- INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT
- INPUT_CSC_PROG_COEFF
- INPUT_CSC_PROG_SHARED_MATRIXA
- INPUT_CSC_SELECT_BYPASS
- INPUT_CSC_SELECT_COMA
- INPUT_CSC_SELECT_ICSC
- INPUT_CVBS_VI1A
- INPUT_CVBS_VI1B
- INPUT_CVBS_VI1C
- INPUT_CVBS_VI2A
- INPUT_CVBS_VI2B
- INPUT_CVBS_VI2C
- INPUT_CVBS_VI3A
- INPUT_CVBS_VI3B
- INPUT_CVBS_VI3C
- INPUT_CVBS_VI4A
- INPUT_DATA_REG
- INPUT_DE
- INPUT_DEPTH_COVERAGE
- INPUT_DEVICE_ID_ABS_MAX
- INPUT_DEVICE_ID_EV_MAX
- INPUT_DEVICE_ID_FF_MAX
- INPUT_DEVICE_ID_KEY_MAX
- INPUT_DEVICE_ID_KEY_MIN_INTERESTING
- INPUT_DEVICE_ID_LED_MAX
- INPUT_DEVICE_ID_MATCH_ABSBIT
- INPUT_DEVICE_ID_MATCH_BUS
- INPUT_DEVICE_ID_MATCH_DEVICE
- INPUT_DEVICE_ID_MATCH_DEVICE_AND_VERSION
- INPUT_DEVICE_ID_MATCH_EVBIT
- INPUT_DEVICE_ID_MATCH_FFBIT
- INPUT_DEVICE_ID_MATCH_KEYBIT
- INPUT_DEVICE_ID_MATCH_LEDBIT
- INPUT_DEVICE_ID_MATCH_MSCIT
- INPUT_DEVICE_ID_MATCH_PRODUCT
- INPUT_DEVICE_ID_MATCH_PROPBIT
- INPUT_DEVICE_ID_MATCH_RELBIT
- INPUT_DEVICE_ID_MATCH_SNDBIT
- INPUT_DEVICE_ID_MATCH_SWBIT
- INPUT_DEVICE_ID_MATCH_VENDOR
- INPUT_DEVICE_ID_MATCH_VERSION
- INPUT_DEVICE_ID_MSC_MAX
- INPUT_DEVICE_ID_PROP_MAX
- INPUT_DEVICE_ID_REL_MAX
- INPUT_DEVICE_ID_SND_MAX
- INPUT_DEVICE_ID_SW_MAX
- INPUT_DEV_CAP_ATTR
- INPUT_DEV_ID_ATTR
- INPUT_DEV_STRING_ATTR_SHOW
- INPUT_DISABLE
- INPUT_DIVIDER
- INPUT_DO_TOGGLE
- INPUT_EN
- INPUT_FIELD
- INPUT_FIRST_DYNAMIC_DEV
- INPUT_FLUSH
- INPUT_FREQ_0
- INPUT_FREQ_1
- INPUT_G0
- INPUT_G1
- INPUT_G2
- INPUT_G3
- INPUT_G4
- INPUT_G5
- INPUT_G6
- INPUT_G7
- INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B_MASK
- INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_BLACK_OFFSET_B__SHIFT
- INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B_MASK
- INPUT_GAMMA_BW_OFFSETS_B__INPUT_GAMMA_WHITE_OFFSET_B__SHIFT
- INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G_MASK
- INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_BLACK_OFFSET_G__SHIFT
- INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G_MASK
- INPUT_GAMMA_BW_OFFSETS_G__INPUT_GAMMA_WHITE_OFFSET_G__SHIFT
- INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R_MASK
- INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_BLACK_OFFSET_R__SHIFT
- INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R_MASK
- INPUT_GAMMA_BW_OFFSETS_R__INPUT_GAMMA_WHITE_OFFSET_R__SHIFT
- INPUT_GAMMA_BYPASS
- INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK
- INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
- INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK
- INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE_MASK
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_BLUE__SHIFT
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN_MASK
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_GREEN__SHIFT
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED_MASK
- INPUT_GAMMA_LUT_30_COLOR__INPUT_GAMMA_LUT_COLOR_10_RED__SHIFT
- INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE_MASK
- INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_DONE__SHIFT
- INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL_MASK
- INPUT_GAMMA_LUT_AUTOFILL__INPUT_GAMMA_LUT_AUTOFILL__SHIFT
- INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE_MASK
- INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_BASE__SHIFT
- INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA_MASK
- INPUT_GAMMA_LUT_PWL_DATA__INPUT_GAMMA_LUT_DELTA__SHIFT
- INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX_MASK
- INPUT_GAMMA_LUT_RW_INDEX__INPUT_GAMMA_LUT_RW_INDEX__SHIFT
- INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR_MASK
- INPUT_GAMMA_LUT_SEQ_COLOR__INPUT_GAMMA_LUT_SEQ_COLOR__SHIFT
- INPUT_GAMMA_SRGB_24
- INPUT_GAMMA_USE_LUT
- INPUT_GAMMA_XVYCC_222
- INPUT_GENERATE_ABS_ACCESSORS
- INPUT_HEADING
- INPUT_HSYNC
- INPUT_IGNORE_EVENT
- INPUT_INNER_COVERAGE
- INPUT_INVALID
- INPUT_KEYMAP_BY_INDEX
- INPUT_LAST
- INPUT_MAJOR
- INPUT_MAX
- INPUT_MAX_CHAR_DEVICES
- INPUT_MODE_CVBS_0
- INPUT_MODE_DIVERSITY
- INPUT_MODE_MASK
- INPUT_MODE_MPEG
- INPUT_MODE_OFF
- INPUT_MODE_YC2_2
- INPUT_MODE_YC_1
- INPUT_MODE_YUV_3
- INPUT_MORE
- INPUT_MT_DIRECT
- INPUT_MT_DROP_UNUSED
- INPUT_MT_POINTER
- INPUT_MT_SEMI_MT
- INPUT_MT_TRACK
- INPUT_MUX
- INPUT_NOPULL
- INPUT_ONLY
- INPUT_PASS_TO_ALL
- INPUT_PASS_TO_DEVICE
- INPUT_PASS_TO_HANDLERS
- INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK
- INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT
- INPUT_PIN_ATTR_DOCK
- INPUT_PIN_ATTR_FRONT
- INPUT_PIN_ATTR_INT
- INPUT_PIN_ATTR_LAST
- INPUT_PIN_ATTR_NORMAL
- INPUT_PIN_ATTR_REAR
- INPUT_PIN_ATTR_UNUSED
- INPUT_POLL_TIME
- INPUT_POOL_SHIFT
- INPUT_POOL_WORDS
- INPUT_PROP_ACCELEROMETER
- INPUT_PROP_BUTTONPAD
- INPUT_PROP_CNT
- INPUT_PROP_DIRECT
- INPUT_PROP_MAX
- INPUT_PROP_POINTER
- INPUT_PROP_POINTING_STICK
- INPUT_PROP_SEMI_MT
- INPUT_PROP_TOPBUTTONPAD
- INPUT_PULLDOWN
- INPUT_PULLUP
- INPUT_R0
- INPUT_R1
- INPUT_R2
- INPUT_R3
- INPUT_R4
- INPUT_R5
- INPUT_R6
- INPUT_R7
- INPUT_RANGE_BYPASS
- INPUT_RANGE_FULL
- INPUT_RANGE_LIMITED
- INPUT_REG_OFFSET
- INPUT_REPORT_ID
- INPUT_SCALER_HBYPASS
- INPUT_SCALER_USE422
- INPUT_SCALER_VBYPASS
- INPUT_SCHMITT
- INPUT_SCHMITT_MASK
- INPUT_SCHMITT_SHIFT
- INPUT_SEL_B
- INPUT_SEL_MASK
- INPUT_SEL_OUT_MODE
- INPUT_SEL_RST_FMT
- INPUT_SEL_RST_VDP
- INPUT_SLOT
- INPUT_SOURCE_ENUM
- INPUT_STATUS
- INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK
- INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT
- INPUT_STRING_LEN
- INPUT_ST_FALLING
- INPUT_ST_HIGH
- INPUT_ST_LOW
- INPUT_ST_RISING
- INPUT_SVIDEO_VI2A_VI1A
- INPUT_SVIDEO_VI2A_VI3A
- INPUT_SVIDEO_VI2B_VI1B
- INPUT_SVIDEO_VI2B_VI3B
- INPUT_SVIDEO_VI2C_VI1C
- INPUT_SVIDEO_VI2C_VI3C
- INPUT_SVIDEO_VI4A_VI1A
- INPUT_SVIDEO_VI4A_VI1B
- INPUT_SVIDEO_VI4A_VI1C
- INPUT_SVIDEO_VI4A_VI3A
- INPUT_SVIDEO_VI4A_VI3B
- INPUT_SVIDEO_VI4A_VI3C
- INPUT_TERMINAL_ID
- INPUT_TEXT
- INPUT_TYPE_DUAL
- INPUT_TYPE_KBD
- INPUT_TYPE_KEYBOARD
- INPUT_TYPE_MOUSE
- INPUT_TYPE_NONTOUCH
- INPUT_TYPE_OFFSET
- INPUT_TYPE_PALM
- INPUT_TYPE_PROXIMITY
- INPUT_TYPE_SINGLE
- INPUT_TYPE_STD
- INPUT_URBS
- INPUT_VAL
- INPUT_VALUE
- INPUT_VOLUME
- INPUT_VSYNC
- INPUT_YEALINK_H
- INP_ACK
- INQD_PDT_CHNGR
- INQD_PDT_COMM
- INQD_PDT_DA
- INQD_PDT_DMASK
- INQD_PDT_NOLUN
- INQD_PDT_NOLUN2
- INQD_PDT_PROC
- INQD_PDT_QMASK
- INQUIRY
- INQUIRYDATABUFFERSIZE
- INQUIRY_CACHE_AGE_MAX
- INQUIRY_DATA_SIZE
- INQUIRY_ENTRY_AGE_MAX
- INQUIRY_EVPD
- INQUIRY_EXTENDED
- INQUIRY_LEN
- INQUIRY_MODEL_LEN
- INQUIRY_REVISION_LEN
- INQUIRY_STATUS
- INQUIRY_STRING_LEN
- INQUIRY_TERMINATION
- INQUIRY_VENDOR_LEN
- INQUIRY_VPD_DEVICE_IDENTIFIER_LEN
- INQUIRY_VPD_SERIAL_LEN
- INQ_STD_NBYTES
- INRANGE
- INRANGEERR_DISCARD
- INREG
- INREG16
- INREG8
- INR_OPEN_CUR
- INR_OPEN_MAX
- INS
- INSANEDEBUG
- INSERTS_PER_STEP
- INSERT_CAL
- INSERT_ICV
- INSERT_ICV_SHIFT
- INSERT_IMMED_GPRA_CONST
- INSERT_IMMED_GPRB_CONST
- INSERT_STRING
- INSEXT_FROM_REG
- INSIDE_ACCESSO
- INSIZE
- INSN_BITS
- INSN_BLE_SR2_R0
- INSN_BUG
- INSN_B_1F
- INSN_CACHE_MODE
- INSN_CALL
- INSN_CALLSYS
- INSN_CALL_DYNAMIC
- INSN_CLAC
- INSN_CLD
- INSN_CODE_SEG_ADDR_SZ
- INSN_CODE_SEG_OPND_SZ
- INSN_CODE_SEG_PARAMS
- INSN_CONFIG
- INSN_CONFIG_8254_READ_STATUS
- INSN_CONFIG_8254_SET_MODE
- INSN_CONFIG_ALT_SOURCE
- INSN_CONFIG_ANALOG_TRIG
- INSN_CONFIG_ARM
- INSN_CONFIG_BIDIRECTIONAL_DATA
- INSN_CONFIG_BLOCK_SIZE
- INSN_CONFIG_CHANGE_NOTIFY
- INSN_CONFIG_DIGITAL_TRIG
- INSN_CONFIG_DIO_INPUT
- INSN_CONFIG_DIO_OPENDRAIN
- INSN_CONFIG_DIO_OUTPUT
- INSN_CONFIG_DIO_QUERY
- INSN_CONFIG_DISARM
- INSN_CONFIG_FILTER
- INSN_CONFIG_GET_CLOCK_SRC
- INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS
- INSN_CONFIG_GET_COUNTER_STATUS
- INSN_CONFIG_GET_GATE_SRC
- INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE
- INSN_CONFIG_GET_PWM_OUTPUT
- INSN_CONFIG_GET_PWM_STATUS
- INSN_CONFIG_GET_ROUTING
- INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR
- INSN_CONFIG_GPCT_QUADRATURE_ENCODER
- INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR
- INSN_CONFIG_PWM_GET_H_BRIDGE
- INSN_CONFIG_PWM_GET_PERIOD
- INSN_CONFIG_PWM_OUTPUT
- INSN_CONFIG_PWM_SET_H_BRIDGE
- INSN_CONFIG_PWM_SET_PERIOD
- INSN_CONFIG_RESET
- INSN_CONFIG_SERIAL_CLOCK
- INSN_CONFIG_SET_CLOCK_SRC
- INSN_CONFIG_SET_COUNTER_MODE
- INSN_CONFIG_SET_GATE_SRC
- INSN_CONFIG_SET_OTHER_SRC
- INSN_CONFIG_SET_ROUTING
- INSN_CONFIG_TIMER_1
- INSN_CONTEXT_SWITCH
- INSN_DECODE
- INSN_DECODE_IPA0
- INSN_DELETED_P
- INSN_DEPRECATED
- INSN_DEVICE_CONFIG
- INSN_DEVICE_CONFIG_CONNECT_ROUTE
- INSN_DEVICE_CONFIG_DISCONNECT_ROUTE
- INSN_DEVICE_CONFIG_GET_ROUTES
- INSN_DEVICE_CONFIG_TEST_ROUTE
- INSN_DFLTCC
- INSN_DIE_HORRIBLY
- INSN_EMULATE
- INSN_GOOD
- INSN_GOOD_NO_SLOT
- INSN_GTOD
- INSN_H
- INSN_HW
- INSN_INTTRIG
- INSN_JAL
- INSN_JUMP_CONDITIONAL
- INSN_JUMP_DYNAMIC
- INSN_JUMP_DYNAMIC_CONDITIONAL
- INSN_JUMP_UNCONDITIONAL
- INSN_LDI_R0
- INSN_LDI_R20
- INSN_LDI_R25_0
- INSN_LDI_R25_1
- INSN_LOCATION
- INSN_LWA
- INSN_MASK_READ
- INSN_MASK_SPECIAL
- INSN_MASK_WRITE
- INSN_MOV_R30_R16
- INSN_NEW_BITS
- INSN_NOP
- INSN_OBSOLETE
- INSN_OP0
- INSN_OP1
- INSN_OTHER
- INSN_PxTLB
- INSN_READ
- INSN_REJECTED
- INSN_RETURN
- INSN_SAMEAS16_BITS
- INSN_SIZE
- INSN_SORTL
- INSN_STAC
- INSN_STACK
- INSN_STD
- INSN_SWA
- INSN_T
- INSN_UD0
- INSN_UD2
- INSN_UNDEF
- INSN_WAIT
- INSN_WRITE
- INSTALL_ENUM_PROPERTY
- INSTALL_NOTIFY_HANDLER
- INSTALL_PACKAGE_TIMEOUT
- INSTALL_PROPERTY
- INSTALL_RANGE_PROPERTY
- INSTANCE_ATTR
- INSTANCE_BROADCAST_WRITES
- INSTANCE_BUCKETS
- INSTANCE_INDEX
- INSTANTIATE
- INSTAT_BUFLEN
- INSTAT_ERROR
- INSTDONE
- INSTPM
- INSTPM_AGPBUSY_INT_EN
- INSTPM_FORCE_ORDERING
- INSTPM_SELF_EN
- INSTPM_SYNC_FLUSH
- INSTPM_TLB_INVALIDATE
- INSTPNT
- INSTPS
- INSTR
- INSTRUCTION_BIT_MODIFY
- INSTRUCTION_LOAD_TXB
- INSTRUCTION_READ
- INSTRUCTION_READ_RXB
- INSTRUCTION_RESET
- INSTRUCTION_RTS
- INSTRUCTION_STORAGE_EXCEPTION
- INSTRUCTION_WRITE
- INSTR_26_TO_24_MASK
- INSTR_26_TO_24_SHIFT
- INSTR_BC_CLIENT
- INSTR_CLIENT_SHIFT
- INSTR_CNT
- INSTR_CNT_D1
- INSTR_LEN_SANITY_CHECK
- INSTR_MEDIA_SUBCLIENT
- INSTR_MI_CLIENT
- INSTR_RC_CLIENT
- INSTR_RD_FIFO
- INSTR_RESET_MBOX
- INSTR_SHIFT
- INSTR_SUBCLIENT_MASK
- INSTR_SUBCLIENT_SHIFT
- INSTR_TYPE_MASK
- INSTR_WR_REG_BYTE
- INSTR_WR_REG_SHORT
- INST_16BIT_BM
- INST_BUSRESET
- INST_BUSSERVICE
- INST_CPNUM
- INST_CPRT
- INST_CPRTDO
- INST_CPRT_L
- INST_CPRT_OP
- INST_CPRT_Rd
- INST_DISCONNECT
- INST_FLAG_BOOSTABLE
- INST_FLAG_BREAK_INST
- INST_FLAG_FIX_BRANCH_REG
- INST_FLAG_FIX_RELATIVE_IP_ADDR
- INST_FLUSH_MAP_CACHE
- INST_FUNCDONE
- INST_GENERIC
- INST_ID_ECC_INTERRUPT_MSG
- INST_ID_HOST_REG_TRAP_MSG
- INST_ID_HW_TRAP
- INST_ID_KILL_SEQ
- INST_ID_PRIV_START
- INST_ID_SPI_WREXEC
- INST_ID_TTRACE_NEW_PC_MSG
- INST_ILLEGALCMD
- INST_INIT
- INST_LDH
- INST_LDHU
- INST_LDW
- INST_LOAD_RESOURCES
- INST_MODE_BM
- INST_OP_FLUSH
- INST_PARSER_CLIENT
- INST_PARSER_ERROR
- INST_READ_BM
- INST_RELEASE_RESOURCES
- INST_RESELECTED
- INST_SC
- INST_SELATN
- INST_SELWOATN
- INST_START
- INST_STH
- INST_STOP
- INST_STW
- INST_SZ
- INST_UNINIT
- INST_VA_TO_PA
- INSUFF_RES_ASC
- INSUFF_RES_ASCQ
- INS_CACHE
- INS_CURR_TIMEOUT
- INS_DCBZ
- INS_DLE_char
- INS_DLE_command
- INS_FROM_REG
- INS_HALT
- INS_HALTINT
- INS_REM_EVENT
- INS_REM_INT_DISABLE
- INS_RFLAG_WTM
- INS_SINT
- INS_TO_REG
- INS_TO_USBDEV
- INS_TW
- INS_VLAN
- INS_byte_stuff
- INS_command
- INS_flag_hunt
- INS_have_data
- INT
- INT0
- INT0_BITS
- INT0_BLK_TRAN_DONE_INT_EN
- INT0_CD_INT_EN
- INT0_DI_INT_EN
- INT0_IRQ
- INT0_IRQ_NUM
- INT0_MBLK_TRAN_DONE_INT_EN
- INT1
- INT16
- INT1R
- INT1_CMD_RES_TOUT_INT_EN
- INT1_CMD_RES_TRAN_DONE_INT_EN
- INT1_DATA_TOUT_INT_EN
- INT1_DCD_TIMEOUT_MASK
- INT1_ENABLED_AND_ACTIVE
- INT1_IRQ
- INT1_IRQ_NUM
- INT1_MASK
- INT1_MBLK_AUTO_STOP_INT_EN
- INT1_RCRC_ERR_INT_EN
- INT1_RESCRC_ERR_INT_EN
- INT1_WCRC_ERR_INT_EN
- INT2
- INT2CLR_REG
- INT2DISTCR0
- INT2DISTCR1
- INT2DISTCR2
- INT2DISTCR3
- INT2NTSR0
- INT2NTSR1
- INT2PRI0
- INT2PRI1
- INT2PRI10
- INT2PRI11
- INT2PRI12
- INT2PRI13
- INT2PRI14
- INT2PRI15
- INT2PRI16
- INT2PRI17
- INT2PRI18
- INT2PRI19
- INT2PRI2
- INT2PRI20
- INT2PRI21
- INT2PRI22
- INT2PRI23
- INT2PRI24
- INT2PRI25
- INT2PRI26
- INT2PRI27
- INT2PRI28
- INT2PRI29
- INT2PRI3
- INT2PRI30
- INT2PRI31
- INT2PRI32
- INT2PRI33
- INT2PRI34
- INT2PRI35
- INT2PRI36
- INT2PRI37
- INT2PRI38
- INT2PRI39
- INT2PRI4
- INT2PRI40
- INT2PRI41
- INT2PRI42
- INT2PRI43
- INT2PRI44
- INT2PRI45
- INT2PRI46
- INT2PRI47
- INT2PRI5
- INT2PRI6
- INT2PRI7
- INT2PRI8
- INT2PRI9
- INT2R
- INT2SMSKCR0
- INT2SMSKCR1
- INT2SMSKCR2
- INT2SMSKCR3
- INT2SMSKCR4
- INT2_IRQ
- INT2_IRQ_NUM
- INT2_MASK
- INT32
- INT32K_EN
- INT32K_EN_SHT
- INT32_MAX
- INT33FE_NODE_DISPLAYPORT
- INT33FE_NODE_FUSB302
- INT33FE_NODE_MAX
- INT33FE_NODE_MAX17047
- INT33FE_NODE_PI3USB30532
- INT33FE_NODE_USB_CONNECTOR
- INT3400_THERMAL_ACTIVE
- INT3400_THERMAL_ADAPTIVE_PERFORMANCE
- INT3400_THERMAL_COOLING_MODE
- INT3400_THERMAL_CRITICAL
- INT3400_THERMAL_EMERGENCY_CALL_MODE
- INT3400_THERMAL_HARDWARE_DUTY_CYCLING
- INT3400_THERMAL_MAXIMUM_UUID
- INT3400_THERMAL_PASSIVE_1
- INT3400_THERMAL_PASSIVE_2
- INT3400_THERMAL_POWER_BOSS
- INT3400_THERMAL_TABLE_CHANGED
- INT3400_THERMAL_VIRTUAL_SENSOR
- INT3401_DEVICE
- INT3402_PERF_CHANGED_EVENT
- INT3402_THERMAL_EVENT
- INT3403_PERF_CHANGED_EVENT
- INT3403_PERF_TRIP_POINT_CHANGED
- INT3403_THERMAL_EVENT
- INT3403_TYPE_BATTERY
- INT3403_TYPE_CHARGER
- INT3403_TYPE_SENSOR
- INT3406_BRIGHTNESS_LIMITS_CHANGED
- INT340X_THERMAL_MAX_ACT_TRIP_COUNT
- INT3496_GPIO_USB_ID
- INT3496_GPIO_USB_MUX
- INT3496_GPIO_VBUS_EN
- INT3R
- INT3_INSN_SIZE
- INT3_IRQ
- INT3_IRQ_NUM
- INT3_SIZE
- INT48_MIN
- INT4R
- INT4_IRQ
- INT4_IRQ_NUM
- INT51X1_HEADER_SIZE
- INT51X1_PRODUCT_ID
- INT51X1_VENDOR_ID
- INT5_IRQ_NUM
- INT68HIGH
- INT6_IRQ_NUM
- INT7_IRQ_NUM
- INT8
- INT80_CLOBBERS
- INTA
- INTA0
- INTA1
- INTA2
- INTAB
- INTAB_LD
- INTACK
- INTACKCLR
- INTACSET
- INTAMR
- INTASR
- INTASSIGN0
- INTASSIGN1
- INTASSIGN2
- INTASSIGN3
- INTASSIGN_MASK
- INTASSIGN_MAX
- INTA_ASSERTED
- INTA_DRVR_ADDR
- INTA_ENABLED_FLAG
- INTA_FLAG
- INTA_MARK
- INTA_MASK
- INTA_PRIORITY
- INTA_STATE
- INTB
- INTBMR
- INTBSR
- INTBUFFERSIZE
- INTBUFSIZE
- INTB_DISABLE
- INTB_MARK
- INTB_PRIORITY
- INTC
- INTCEND
- INTCG_CICFGR
- INTCG_CIDSTR
- INTCG_ICTLR
- INTCG_SIZE
- INTCHID
- INTCHIM
- INTCLK
- INTCLOSE_REG
- INTCLR
- INTCL_CACR
- INTCL_CENR
- INTCL_CFGR
- INTCL_PICTLR
- INTCL_RDYIR
- INTCL_SENR
- INTCL_SIGR
- INTCL_SIZE
- INTCNTSTAREG
- INTCODE_MASK
- INTCOFFSET
- INTCONTLGLOBALREG_END
- INTCONTLGLOBALREG_START
- INTCPS_NR_ILR_REGS
- INTCPS_NR_MIR_REGS
- INTCP_FLASHPROG_OFFSET
- INTCR
- INTCR0_INTCD
- INTCR0_INTGC
- INTCR1_INTCC
- INTCR2_INTCC
- INTCSIZE
- INTCSR
- INTCSR_9052
- INTCSR_9054
- INTCSR_ADDON_INTENABLE_M
- INTCSR_ADINT_ENABLE
- INTCSR_ADINT_STATUS
- INTCSR_CTR4INT_ENABLE
- INTCSR_CTR4INT_STATUS
- INTCSR_INBOX_BYTE
- INTCSR_INBOX_FULL_INT
- INTCSR_INBOX_INTR_STATUS
- INTCSR_INBOX_SELECT
- INTCSR_INTR_ASSERTED
- INTCSR_OUTBOX_BYTE
- INTCSR_OUTBOX_EMPTY_INT
- INTCSR_OUTBOX_SELECT
- INTCSR_PCIINT_ENABLE
- INTCTLB_IPFDC
- INTCTLB_IPPCI
- INTCTLB_IPTI
- INTCTLF_IPFDC
- INTCTLF_IPPCI
- INTCTLF_IPTI
- INTCTLSTAT
- INTCTLSTAT_ENINT_MASK
- INTCTL_G
- INTCTRL
- INTC_BASE
- INTC_BLOCK_OFFSET
- INTC_CONTROL
- INTC_EN0_N_MARK
- INTC_EN1_N_MARK
- INTC_GROUP
- INTC_HW_DESC
- INTC_ICCR
- INTC_ICFP
- INTC_ICIP
- INTC_ICLR
- INTC_ICMR
- INTC_ICPR
- INTC_ICR
- INTC_ICR0
- INTC_ICR1
- INTC_ICR1_IRQLVL
- INTC_ICR2
- INTC_ICR_CLEAR
- INTC_ICR_IRLM
- INTC_ICR_SET
- INTC_IDLE
- INTC_IDLE_FUNCIDLE
- INTC_IDLE_TURBO
- INTC_ILR0
- INTC_INT2MSKCR
- INTC_INT2MSKCR1
- INTC_INT2PRI7
- INTC_INTDSB_0
- INTC_INTDSB_1
- INTC_INTENB_0
- INTC_INTENB_1
- INTC_INTER
- INTC_INTMSK0
- INTC_INTMSK1
- INTC_INTMSK2
- INTC_INTMSKCLR0
- INTC_INTMSKCLR1
- INTC_INTMSKCLR2
- INTC_INTPRI_0
- INTC_INTPRI_PPREG
- INTC_INTPRI_PREGS
- INTC_INTREQ_0
- INTC_INTREQ_1
- INTC_INTSRC_0
- INTC_INTSRC_1
- INTC_INT_GLOBAL
- INTC_IPR01
- INTC_IPRC
- INTC_IPRD
- INTC_IPRE
- INTC_IRQ
- INTC_IRQ0_MARK
- INTC_IRQ0_N_MARK
- INTC_IRQ1_MARK
- INTC_IRQ1_N_MARK
- INTC_IRQ2_MARK
- INTC_IRQ2_N_MARK
- INTC_IRQ3_MARK
- INTC_IRQ3_N_MARK
- INTC_IRQ4_MARK
- INTC_IRQ4_N_MARK
- INTC_IRQ5_MARK
- INTC_IRQ6_MARK
- INTC_IRQ7_MARK
- INTC_IRQPIN_MAX
- INTC_IRQPIN_REG_CLEAR
- INTC_IRQPIN_REG_IRLM
- INTC_IRQPIN_REG_MASK
- INTC_IRQPIN_REG_NR
- INTC_IRQPIN_REG_NR_MANDATORY
- INTC_IRQPIN_REG_PRIO
- INTC_IRQPIN_REG_SENSE
- INTC_IRQPIN_REG_SOURCE
- INTC_IRQS
- INTC_IRQ_SENSE
- INTC_IRQ_SENSE_VALID
- INTC_IRR0
- INTC_IRR1
- INTC_IRR2
- INTC_MARK
- INTC_MIR0
- INTC_MIR_CLEAR0
- INTC_MIR_SET0
- INTC_NR_IRQS
- INTC_PENDING_IRQ0
- INTC_PENDING_IRQ1
- INTC_PENDING_IRQ2
- INTC_PENDING_IRQ3
- INTC_PEND_REG
- INTC_PRIORITY
- INTC_PROTECTION
- INTC_PROTECTION_ENABLE
- INTC_REG
- INTC_REG_DISABLE
- INTC_REG_ENABLE
- INTC_REG_RAW_STATUS
- INTC_REG_STATUS0
- INTC_REG_STATUS1
- INTC_REG_TYPE
- INTC_REVISION
- INTC_SIR
- INTC_SMP
- INTC_SMP_BALANCING
- INTC_SYSCONFIG
- INTC_SYSSTATUS
- INTC_TAG_VIRQ_NEEDS_ALLOC
- INTC_THRESHOLD
- INTC_USERIMASK
- INTC_VECT
- INTD
- INTDEF
- INTDELAY
- INTDISABLE
- INTDISTCR0
- INTDISTCR1
- INTDT
- INTD_MARK
- INTD_PRIORITY
- INTE
- INTE0
- INTE2
- INTE2_CAPTURE_CH_0_HALF_LOOP
- INTE2_CAPTURE_CH_0_LOOP
- INTE2_PLAYBACK_CH_0_HALF_LOOP
- INTE2_PLAYBACK_CH_0_LOOP
- INTE2_PLAYBACK_CH_1_HALF_LOOP
- INTE2_PLAYBACK_CH_1_LOOP
- INTE2_PLAYBACK_CH_2_HALF_LOOP
- INTE2_PLAYBACK_CH_2_LOOP
- INTE2_PLAYBACK_CH_3_HALF_LOOP
- INTE2_PLAYBACK_CH_3_LOOP
- INTE3
- INTEG0_BASE_ADDR
- INTEGER_BITS
- INTEGRATED_LVDS
- INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION
- INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE
- INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND
- INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN
- INTEGRATED_SYSTEM_INFO__AMD_CPU__K8
- INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE
- INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI
- INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH
- INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT
- INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT
- INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT
- INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT
- INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU
- INTEGRATED_TMDS
- INTEGRATOR_AP_CM_BITS
- INTEGRATOR_AP_FLASHPROT
- INTEGRATOR_AP_GPIO_BASE
- INTEGRATOR_AP_PCI_25_33_MHZ
- INTEGRATOR_AP_SYS_BITS
- INTEGRATOR_BOOT_ROM_BASE
- INTEGRATOR_BOOT_ROM_HI
- INTEGRATOR_BOOT_ROM_LO
- INTEGRATOR_BOOT_ROM_SIZE
- INTEGRATOR_CLCD_CM
- INTEGRATOR_CLCD_LCD0_EN
- INTEGRATOR_CLCD_LCD1_EN
- INTEGRATOR_CLCD_LCDBIASDN
- INTEGRATOR_CLCD_LCDBIASEN
- INTEGRATOR_CLCD_LCDBIASUP
- INTEGRATOR_CLCD_LCDMUX_LCD24
- INTEGRATOR_CLCD_LCDMUX_SHARP
- INTEGRATOR_CLCD_LCDMUX_VGA24
- INTEGRATOR_CLCD_LCDMUX_VGA555
- INTEGRATOR_CLCD_LCD_N24BITEN
- INTEGRATOR_CLCD_LCD_STATIC
- INTEGRATOR_CLCD_LCD_STATIC1
- INTEGRATOR_CLCD_LCD_STATIC2
- INTEGRATOR_CLCD_MASK
- INTEGRATOR_CM_CTRL_RESET
- INTEGRATOR_CP_AACI_BASE
- INTEGRATOR_CP_CM_CORE_BITS
- INTEGRATOR_CP_CM_MEM_BITS
- INTEGRATOR_CP_CTL_BASE
- INTEGRATOR_CP_ETH_BASE
- INTEGRATOR_CP_FLASHPROT
- INTEGRATOR_CP_GPIO_BASE
- INTEGRATOR_CP_MMC_BASE
- INTEGRATOR_CP_SIC_BASE
- INTEGRATOR_CSR_BASE
- INTEGRATOR_CSR_SIZE
- INTEGRATOR_CT_BASE
- INTEGRATOR_DBG_ALPHA
- INTEGRATOR_DBG_ALPHA_OFFSET
- INTEGRATOR_DBG_BASE
- INTEGRATOR_DBG_LEDS
- INTEGRATOR_DBG_LEDS_OFFSET
- INTEGRATOR_DBG_SWITCH
- INTEGRATOR_DBG_SWITCH_OFFSET
- INTEGRATOR_EBI_16_BIT
- INTEGRATOR_EBI_32_BIT
- INTEGRATOR_EBI_8_BIT
- INTEGRATOR_EBI_BASE
- INTEGRATOR_EBI_CSR0
- INTEGRATOR_EBI_CSR0_OFFSET
- INTEGRATOR_EBI_CSR1
- INTEGRATOR_EBI_CSR1_OFFSET
- INTEGRATOR_EBI_CSR2
- INTEGRATOR_EBI_CSR2_OFFSET
- INTEGRATOR_EBI_CSR3
- INTEGRATOR_EBI_CSR3_OFFSET
- INTEGRATOR_EBI_LOCK
- INTEGRATOR_EBI_LOCK_OFFSET
- INTEGRATOR_EBI_LOCK_VAL
- INTEGRATOR_EBI_SYNC
- INTEGRATOR_EBI_WRITE_ENABLE
- INTEGRATOR_EBI_WS_10
- INTEGRATOR_EBI_WS_11
- INTEGRATOR_EBI_WS_12
- INTEGRATOR_EBI_WS_13
- INTEGRATOR_EBI_WS_14
- INTEGRATOR_EBI_WS_15
- INTEGRATOR_EBI_WS_16
- INTEGRATOR_EBI_WS_17
- INTEGRATOR_EBI_WS_2
- INTEGRATOR_EBI_WS_3
- INTEGRATOR_EBI_WS_4
- INTEGRATOR_EBI_WS_5
- INTEGRATOR_EBI_WS_6
- INTEGRATOR_EBI_WS_7
- INTEGRATOR_EBI_WS_8
- INTEGRATOR_EBI_WS_9
- INTEGRATOR_FLASH_BASE
- INTEGRATOR_FLASH_SIZE
- INTEGRATOR_HARDWARE_H
- INTEGRATOR_HDR0_SDRAM_BASE
- INTEGRATOR_HDR1_SDRAM_BASE
- INTEGRATOR_HDR2_SDRAM_BASE
- INTEGRATOR_HDR3_SDRAM_BASE
- INTEGRATOR_HDR_BASE
- INTEGRATOR_HDR_CTRL
- INTEGRATOR_HDR_CTRL_BIG_ENDIAN
- INTEGRATOR_HDR_CTRL_FASTBUS
- INTEGRATOR_HDR_CTRL_HIGHVECTORS
- INTEGRATOR_HDR_CTRL_LED
- INTEGRATOR_HDR_CTRL_MBRD_DETECH
- INTEGRATOR_HDR_CTRL_OFFSET
- INTEGRATOR_HDR_CTRL_REMAP
- INTEGRATOR_HDR_CTRL_RESET
- INTEGRATOR_HDR_CTRL_SYNC
- INTEGRATOR_HDR_IC
- INTEGRATOR_HDR_IC_OFFSET
- INTEGRATOR_HDR_ID
- INTEGRATOR_HDR_ID_OFFSET
- INTEGRATOR_HDR_INIT
- INTEGRATOR_HDR_INIT_OFFSET
- INTEGRATOR_HDR_LOCK
- INTEGRATOR_HDR_LOCK_OFFSET
- INTEGRATOR_HDR_OSC
- INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00
- INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0
- INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0
- INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6
- INTEGRATOR_HDR_OSC_BUS_MODE_MASK
- INTEGRATOR_HDR_OSC_CORE_100MHz
- INTEGRATOR_HDR_OSC_CORE_105MHz
- INTEGRATOR_HDR_OSC_CORE_10MHz
- INTEGRATOR_HDR_OSC_CORE_110MHz
- INTEGRATOR_HDR_OSC_CORE_115MHz
- INTEGRATOR_HDR_OSC_CORE_120MHz
- INTEGRATOR_HDR_OSC_CORE_125MHz
- INTEGRATOR_HDR_OSC_CORE_130MHz
- INTEGRATOR_HDR_OSC_CORE_135MHz
- INTEGRATOR_HDR_OSC_CORE_140MHz
- INTEGRATOR_HDR_OSC_CORE_145MHz
- INTEGRATOR_HDR_OSC_CORE_150MHz
- INTEGRATOR_HDR_OSC_CORE_155MHz
- INTEGRATOR_HDR_OSC_CORE_15MHz
- INTEGRATOR_HDR_OSC_CORE_160MHz
- INTEGRATOR_HDR_OSC_CORE_20MHz
- INTEGRATOR_HDR_OSC_CORE_25MHz
- INTEGRATOR_HDR_OSC_CORE_30MHz
- INTEGRATOR_HDR_OSC_CORE_35MHz
- INTEGRATOR_HDR_OSC_CORE_40MHz
- INTEGRATOR_HDR_OSC_CORE_45MHz
- INTEGRATOR_HDR_OSC_CORE_50MHz
- INTEGRATOR_HDR_OSC_CORE_55MHz
- INTEGRATOR_HDR_OSC_CORE_60MHz
- INTEGRATOR_HDR_OSC_CORE_65MHz
- INTEGRATOR_HDR_OSC_CORE_70MHz
- INTEGRATOR_HDR_OSC_CORE_75MHz
- INTEGRATOR_HDR_OSC_CORE_80MHz
- INTEGRATOR_HDR_OSC_CORE_85MHz
- INTEGRATOR_HDR_OSC_CORE_90MHz
- INTEGRATOR_HDR_OSC_CORE_95MHz
- INTEGRATOR_HDR_OSC_CORE_MASK
- INTEGRATOR_HDR_OSC_MEM_10MHz
- INTEGRATOR_HDR_OSC_MEM_15MHz
- INTEGRATOR_HDR_OSC_MEM_20MHz
- INTEGRATOR_HDR_OSC_MEM_25MHz
- INTEGRATOR_HDR_OSC_MEM_30MHz
- INTEGRATOR_HDR_OSC_MEM_33MHz
- INTEGRATOR_HDR_OSC_MEM_40MHz
- INTEGRATOR_HDR_OSC_MEM_50MHz
- INTEGRATOR_HDR_OSC_MEM_60MHz
- INTEGRATOR_HDR_OSC_MEM_66MHz
- INTEGRATOR_HDR_OSC_MEM_MASK
- INTEGRATOR_HDR_OSC_OFFSET
- INTEGRATOR_HDR_PROC
- INTEGRATOR_HDR_PROC_OFFSET
- INTEGRATOR_HDR_SDRAM
- INTEGRATOR_HDR_SDRAM_OFFSET
- INTEGRATOR_HDR_SDRAM_SPD_OK
- INTEGRATOR_HDR_SPDBASE
- INTEGRATOR_HDR_SPDBASE_OFFSET
- INTEGRATOR_HDR_SPDTOP
- INTEGRATOR_HDR_SPDTOP_OFFSET
- INTEGRATOR_HDR_STAT
- INTEGRATOR_HDR_STAT_OFFSET
- INTEGRATOR_IC_BASE
- INTEGRATOR_KBD_BASE
- INTEGRATOR_LOGIC_MODULE0_BASE
- INTEGRATOR_LOGIC_MODULE1_BASE
- INTEGRATOR_LOGIC_MODULE2_BASE
- INTEGRATOR_LOGIC_MODULE3_BASE
- INTEGRATOR_LOGIC_MODULES_BASE
- INTEGRATOR_MBRD_SSRAM_BASE
- INTEGRATOR_MBRD_SSRAM_SIZE
- INTEGRATOR_MOUSE_BASE
- INTEGRATOR_REBOOT_CM
- INTEGRATOR_RTC_BASE
- INTEGRATOR_SC_ARB
- INTEGRATOR_SC_ARB_OFFSET
- INTEGRATOR_SC_BASE
- INTEGRATOR_SC_CTRLC
- INTEGRATOR_SC_CTRLC_OFFSET
- INTEGRATOR_SC_CTRLS
- INTEGRATOR_SC_CTRLS_OFFSET
- INTEGRATOR_SC_CTRL_FLVPPEN
- INTEGRATOR_SC_CTRL_FLWP
- INTEGRATOR_SC_CTRL_SOFTRST
- INTEGRATOR_SC_CTRL_UDTR0
- INTEGRATOR_SC_CTRL_UDTR1
- INTEGRATOR_SC_CTRL_URTS0
- INTEGRATOR_SC_CTRL_URTS1
- INTEGRATOR_SC_CTRL_nFLVPPEN
- INTEGRATOR_SC_CTRL_nFLWP
- INTEGRATOR_SC_DEC
- INTEGRATOR_SC_DEC_OFFSET
- INTEGRATOR_SC_ID
- INTEGRATOR_SC_ID_OFFSET
- INTEGRATOR_SC_LBFADDR_OFFSET
- INTEGRATOR_SC_LBFCODE_OFFSET
- INTEGRATOR_SC_LOCK
- INTEGRATOR_SC_LOCK_OFFSET
- INTEGRATOR_SC_OSC
- INTEGRATOR_SC_OSC_OFFSET
- INTEGRATOR_SC_OSC_PCI_25MHz
- INTEGRATOR_SC_OSC_PCI_33MHz
- INTEGRATOR_SC_OSC_PCI_MASK
- INTEGRATOR_SC_OSC_SYS_10MHz
- INTEGRATOR_SC_OSC_SYS_15MHz
- INTEGRATOR_SC_OSC_SYS_20MHz
- INTEGRATOR_SC_OSC_SYS_25MHz
- INTEGRATOR_SC_OSC_SYS_33MHz
- INTEGRATOR_SC_OSC_SYS_MASK
- INTEGRATOR_SC_PCIENABLE
- INTEGRATOR_SC_PCI_ENABLE
- INTEGRATOR_SC_PCI_INTCLR
- INTEGRATOR_SC_PCI_OFFSET
- INTEGRATOR_SDRAM_ALIAS_BASE
- INTEGRATOR_SDRAM_BASE
- INTEGRATOR_SSRAM_ALIAS_BASE
- INTEGRATOR_SSRAM_BASE
- INTEGRATOR_SSRAM_SIZE
- INTEGRATOR_TIMER0_BASE
- INTEGRATOR_TIMER1_BASE
- INTEGRATOR_TIMER2_BASE
- INTEGRATOR_UART0_BASE
- INTEGRATOR_UART1_BASE
- INTEGRITY_FAIL
- INTEGRITY_KEYRING_EVM
- INTEGRITY_KEYRING_IMA
- INTEGRITY_KEYRING_MAX
- INTEGRITY_KEYRING_PLATFORM
- INTEGRITY_NOLABEL
- INTEGRITY_NOXATTRS
- INTEGRITY_PASS
- INTEGRITY_PASS_IMMUTABLE
- INTEGRITY_UNKNOWN
- INTEG_CFG
- INTEL8X0M_PM_OPS
- INTEL8X0_PM_OPS
- INTEL8X0_TESTBUF_SIZE
- INTELFB_CLASS_MASK
- INTELFB_CONN_LIMIT
- INTELFB_DVO_CHIP_LVDS
- INTELFB_DVO_CHIP_NONE
- INTELFB_DVO_CHIP_TMDS
- INTELFB_DVO_CHIP_TVOUT
- INTELFB_FB_ACQUIRED
- INTELFB_MMIO_ACQUIRED
- INTELFB_MODULE_NAME
- INTELFB_OUTPUT_ANALOG
- INTELFB_OUTPUT_DVO
- INTELFB_OUTPUT_LVDS
- INTELFB_OUTPUT_PIPE_A
- INTELFB_OUTPUT_PIPE_B
- INTELFB_OUTPUT_PIPE_NC
- INTELFB_OUTPUT_SDVO
- INTELFB_OUTPUT_TVOUT
- INTELFB_OUTPUT_UNUSED
- INTELFB_VERSION
- INTELPllInvalid
- INTEL_6300_DISABLE_BOOT_IRQ
- INTEL_6300_IOAPIC_ABAR
- INTEL_815_APCONT
- INTEL_815_ATTBASE_MASK
- INTEL_8255X_ETHERNET_DEVICE
- INTEL_830M
- INTEL_830_GMCH_GMS_DISABLED
- INTEL_830_GMCH_GMS_LOCAL
- INTEL_830_GMCH_GMS_MASK
- INTEL_830_GMCH_GMS_STOLEN_1024
- INTEL_830_GMCH_GMS_STOLEN_512
- INTEL_830_GMCH_GMS_STOLEN_8192
- INTEL_845G
- INTEL_852GM
- INTEL_852GME
- INTEL_854
- INTEL_855GM
- INTEL_855GME
- INTEL_855_GMCH_GMS_DISABLED
- INTEL_855_GMCH_GMS_MASK
- INTEL_855_GMCH_GMS_STOLEN_16M
- INTEL_855_GMCH_GMS_STOLEN_1M
- INTEL_855_GMCH_GMS_STOLEN_32M
- INTEL_855_GMCH_GMS_STOLEN_4M
- INTEL_855_GMCH_GMS_STOLEN_8M
- INTEL_85XGM
- INTEL_85X_CAPID
- INTEL_85X_VARIANT_MASK
- INTEL_85X_VARIANT_SHIFT
- INTEL_865G
- INTEL_915G
- INTEL_915GM
- INTEL_915G_GMCH_GMS_STOLEN_48M
- INTEL_915G_GMCH_GMS_STOLEN_64M
- INTEL_945G
- INTEL_945GM
- INTEL_945GME
- INTEL_965G
- INTEL_965GM
- INTEL_ADVANCED_AD_CONTEXT
- INTEL_ADVANCED_CONTEXT
- INTEL_AGPCTRL
- INTEL_ALL_EVENT_CONSTRAINT
- INTEL_AML_CFL_GT2_IDS
- INTEL_AML_KBL_GT2_IDS
- INTEL_AMT_WATCHDOG_ID
- INTEL_ANALOG_CLONE_BIT
- INTEL_APSIZE
- INTEL_ARCH_EVENT_MASK
- INTEL_ATTBASE
- INTEL_AUDIO_DEVBLC
- INTEL_AUDIO_DEVCL
- INTEL_AUDIO_DEVCTG
- INTEL_BACKLIGHT_DISPLAY_DDI
- INTEL_BACKLIGHT_DSI_DCS
- INTEL_BACKLIGHT_LPSS
- INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE
- INTEL_BACKLIGHT_PMIC
- INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE
- INTEL_BASED_IOP
- INTEL_BDW_GT1_IDS
- INTEL_BDW_GT2_IDS
- INTEL_BDW_GT3_IDS
- INTEL_BDW_IDS
- INTEL_BDW_RSVD_IDS
- INTEL_BDW_ULT_GT1_IDS
- INTEL_BDW_ULT_GT2_IDS
- INTEL_BDW_ULT_GT3_IDS
- INTEL_BDW_ULT_RSVD_IDS
- INTEL_BDW_ULX_GT1_IDS
- INTEL_BDW_ULX_GT2_IDS
- INTEL_BDW_ULX_GT3_IDS
- INTEL_BDW_ULX_RSVD_IDS
- INTEL_BROADCAST_RGB_AUTO
- INTEL_BROADCAST_RGB_FULL
- INTEL_BROADCAST_RGB_LIMITED
- INTEL_BROADWELL
- INTEL_BROXTON
- INTEL_BSM
- INTEL_BSM_MASK
- INTEL_BSPR_REG
- INTEL_BSPR_REG_BPNPD
- INTEL_BSPR_REG_BPPD
- INTEL_BTS_AUXTRACE_PRIV_MAX
- INTEL_BTS_AUXTRACE_PRIV_SIZE
- INTEL_BTS_CAP_USER_TIME_ZERO
- INTEL_BTS_ERR_LOST
- INTEL_BTS_ERR_NOINSN
- INTEL_BTS_PMU_NAME
- INTEL_BTS_PMU_TYPE
- INTEL_BTS_SNAPSHOT_MODE
- INTEL_BTS_TIME_MULT
- INTEL_BTS_TIME_SHIFT
- INTEL_BTS_TIME_ZERO
- INTEL_BUSWIDTH
- INTEL_BXT_IDS
- INTEL_CANNONLAKE
- INTEL_CE4100
- INTEL_CE_GBE_MDIC_GO
- INTEL_CE_GBE_MDIC_OP_READ
- INTEL_CE_GBE_MDIC_OP_WRITE
- INTEL_CE_GBE_MDIC_READ_ERROR
- INTEL_CE_GBE_MDIO_RCOMP_BASE
- INTEL_CFG_MBOX_DEVID_0
- INTEL_CFL_H_GT1_IDS
- INTEL_CFL_H_GT2_IDS
- INTEL_CFL_IDS
- INTEL_CFL_S_GT1_IDS
- INTEL_CFL_S_GT2_IDS
- INTEL_CFL_U_GT2_IDS
- INTEL_CFL_U_GT3_IDS
- INTEL_CHERRYVIEW
- INTEL_CHV_IDS
- INTEL_CIPINTRC_CFG_OFFSET
- INTEL_CIPINTRC_DIS_INTX_ICH
- INTEL_CML_GT1_IDS
- INTEL_CML_GT2_IDS
- INTEL_CNL_IDS
- INTEL_CNL_PORT_F_IDS
- INTEL_COFFEELAKE
- INTEL_CONTEXT_SCHEDULE_IN
- INTEL_CONTEXT_SCHEDULE_OUT
- INTEL_CONTEXT_SCHEDULE_PREEMPTED
- INTEL_CPUFREQ_TRANSITION_DELAY
- INTEL_CPUFREQ_TRANSITION_LATENCY
- INTEL_CPU_DESC
- INTEL_CPU_FAM6
- INTEL_CPU_FAM_ANY
- INTEL_CRTC_FUNCS
- INTEL_DDB_PART_1_2
- INTEL_DDB_PART_5_6
- INTEL_DEVID
- INTEL_DPLL_ALWAYS_ON
- INTEL_DP_B_CLONE_BIT
- INTEL_DP_C_CLONE_BIT
- INTEL_DP_D_CLONE_BIT
- INTEL_DP_RESOLUTION_FAILSAFE
- INTEL_DP_RESOLUTION_PREFERRED
- INTEL_DP_RESOLUTION_SHIFT_MASK
- INTEL_DP_RESOLUTION_STANDARD
- INTEL_DRAM_DDR3
- INTEL_DRAM_DDR4
- INTEL_DRAM_LPDDR3
- INTEL_DRAM_LPDDR4
- INTEL_DRAM_UNKNOWN
- INTEL_DSI_COMMAND_MODE
- INTEL_DSI_VIDEO_MODE
- INTEL_DSM_D3_RETUNE
- INTEL_DSM_DRV_STRENGTH
- INTEL_DSM_FNS
- INTEL_DSM_FN_PLATFORM_MUX_INFO
- INTEL_DSM_HS_CAPS
- INTEL_DSM_HS_CAPS_DDR50
- INTEL_DSM_HS_CAPS_SDR104
- INTEL_DSM_HS_CAPS_SDR25
- INTEL_DSM_HS_CAPS_SDR50
- INTEL_DSM_REVISION_ID
- INTEL_DSM_V18_SWITCH
- INTEL_DSM_V33_SWITCH
- INTEL_DVO_CHIP_LVDS
- INTEL_DVO_CHIP_NONE
- INTEL_DVO_CHIP_TMDS
- INTEL_DVO_CHIP_TVOUT
- INTEL_DVO_LVDS_CLONE_BIT
- INTEL_DVO_TMDS_CLONE_BIT
- INTEL_E1000_ETHERNET_DEVICE
- INTEL_EDP_CLONE_BIT
- INTEL_EG20T_PCH
- INTEL_EHL_IDS
- INTEL_ELKHARTLAKE
- INTEL_ENGINE_CS_MAX_NAME
- INTEL_ENGINE_PM_H
- INTEL_ENGINE_POOL_H
- INTEL_ENGINE_POOL_TYPES_H
- INTEL_ENGINE_USER_H
- INTEL_EN_ALL_PIN_CVTS
- INTEL_EN_DP12
- INTEL_ERRSTS
- INTEL_EVENT_CONSTRAINT
- INTEL_EVENT_CONSTRAINT_RANGE
- INTEL_EVENT_EXTRA_REG
- INTEL_EXCLEVT_CONSTRAINT
- INTEL_EXCLUEVT_CONSTRAINT
- INTEL_EXCL_EXCLUSIVE
- INTEL_EXCL_SHARED
- INTEL_EXCL_UNUSED
- INTEL_FAM6_ATOM_AIRMONT
- INTEL_FAM6_ATOM_AIRMONT_MID
- INTEL_FAM6_ATOM_AIRMONT_NP
- INTEL_FAM6_ATOM_BONNELL
- INTEL_FAM6_ATOM_BONNELL_MID
- INTEL_FAM6_ATOM_GOLDMONT
- INTEL_FAM6_ATOM_GOLDMONT_D
- INTEL_FAM6_ATOM_GOLDMONT_PLUS
- INTEL_FAM6_ATOM_SALTWELL
- INTEL_FAM6_ATOM_SALTWELL_MID
- INTEL_FAM6_ATOM_SALTWELL_TABLET
- INTEL_FAM6_ATOM_SILVERMONT
- INTEL_FAM6_ATOM_SILVERMONT_D
- INTEL_FAM6_ATOM_SILVERMONT_MID
- INTEL_FAM6_ATOM_TREMONT
- INTEL_FAM6_ATOM_TREMONT_D
- INTEL_FAM6_BROADWELL
- INTEL_FAM6_BROADWELL_D
- INTEL_FAM6_BROADWELL_G
- INTEL_FAM6_BROADWELL_X
- INTEL_FAM6_CANNONLAKE_L
- INTEL_FAM6_COMETLAKE
- INTEL_FAM6_COMETLAKE_L
- INTEL_FAM6_CORE2_DUNNINGTON
- INTEL_FAM6_CORE2_MEROM
- INTEL_FAM6_CORE2_MEROM_L
- INTEL_FAM6_CORE2_PENRYN
- INTEL_FAM6_CORE_YONAH
- INTEL_FAM6_HASWELL
- INTEL_FAM6_HASWELL_G
- INTEL_FAM6_HASWELL_L
- INTEL_FAM6_HASWELL_X
- INTEL_FAM6_ICELAKE
- INTEL_FAM6_ICELAKE_D
- INTEL_FAM6_ICELAKE_L
- INTEL_FAM6_ICELAKE_NNPI
- INTEL_FAM6_ICELAKE_X
- INTEL_FAM6_IVYBRIDGE
- INTEL_FAM6_IVYBRIDGE_X
- INTEL_FAM6_KABYLAKE
- INTEL_FAM6_KABYLAKE_L
- INTEL_FAM6_NEHALEM
- INTEL_FAM6_NEHALEM_EP
- INTEL_FAM6_NEHALEM_EX
- INTEL_FAM6_NEHALEM_G
- INTEL_FAM6_SANDYBRIDGE
- INTEL_FAM6_SANDYBRIDGE_X
- INTEL_FAM6_SKYLAKE
- INTEL_FAM6_SKYLAKE_L
- INTEL_FAM6_SKYLAKE_X
- INTEL_FAM6_TIGERLAKE
- INTEL_FAM6_TIGERLAKE_L
- INTEL_FAM6_WESTMERE
- INTEL_FAM6_WESTMERE_EP
- INTEL_FAM6_WESTMERE_EX
- INTEL_FAM6_XEON_PHI_KNL
- INTEL_FAM6_XEON_PHI_KNM
- INTEL_FLAGS_EVENT_CONSTRAINT
- INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD
- INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE
- INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST
- INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD
- INTEL_FLAGS_EVENT_CONSTRAINT_RANGE
- INTEL_FLAGS_UEVENT_CONSTRAINT
- INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD
- INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA
- INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST
- INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD
- INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST
- INTEL_FRONTBUFFER
- INTEL_FRONTBUFFER_ALL_MASK
- INTEL_FRONTBUFFER_BITS_PER_PIPE
- INTEL_FRONTBUFFER_OVERLAY
- INTEL_FWH_ADDR
- INTEL_FWH_ADDR_LEN
- INTEL_FWH_DEVICE_CODE_4M
- INTEL_FWH_DEVICE_CODE_8M
- INTEL_FWH_DEVICE_CODE_ADDRESS
- INTEL_FWH_MANUFACTURER_CODE
- INTEL_FWH_MANUFACTURER_CODE_ADDRESS
- INTEL_FWH_READ_ID_CMD
- INTEL_FWH_RESET_CMD
- INTEL_FW_FAKE_VERSION
- INTEL_FW_FIS_VERSION
- INTEL_FW_MAX_SEND_LEN
- INTEL_FW_QUERY_INTERVAL
- INTEL_FW_QUERY_MAX_TIME
- INTEL_FW_STORAGE_SIZE
- INTEL_G33
- INTEL_G33_IDS
- INTEL_G45
- INTEL_G45_IDS
- INTEL_GEMINILAKE
- INTEL_GEN
- INTEL_GEN11_BSM_DW0
- INTEL_GEN11_BSM_DW1
- INTEL_GEN_MASK
- INTEL_GET_VENDOR_VERB
- INTEL_GLK_IDS
- INTEL_GM45
- INTEL_GM45_IDS
- INTEL_GMBUS_BURST_READ_MAX_LEN
- INTEL_GMCH_CTRL
- INTEL_GMCH_ENABLED
- INTEL_GMCH_GMS_STOLEN_160M
- INTEL_GMCH_GMS_STOLEN_224M
- INTEL_GMCH_GMS_STOLEN_352M
- INTEL_GMCH_GMS_STOLEN_96M
- INTEL_GMCH_MEM_128M
- INTEL_GMCH_MEM_64M
- INTEL_GMCH_MEM_MASK
- INTEL_GMCH_VGA_DISABLE
- INTEL_GTT_GEN
- INTEL_GT_IRQ_H
- INTEL_GT_PARK
- INTEL_GT_PM_H
- INTEL_GT_PM_IRQ_H
- INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA
- INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA
- INTEL_GT_SCRATCH_FIELD_DEFAULT
- INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH
- INTEL_GT_UNPARK
- INTEL_GUC_ACTION_ALLOCATE_DOORBELL
- INTEL_GUC_ACTION_AUTHENTICATE_HUC
- INTEL_GUC_ACTION_DEALLOCATE_DOORBELL
- INTEL_GUC_ACTION_DEFAULT
- INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER
- INTEL_GUC_ACTION_ENTER_S_STATE
- INTEL_GUC_ACTION_EXIT_S_STATE
- INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH
- INTEL_GUC_ACTION_LIMIT
- INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
- INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER
- INTEL_GUC_ACTION_REQUEST_ENGINE_RESET
- INTEL_GUC_ACTION_REQUEST_PREEMPTION
- INTEL_GUC_ACTION_SAMPLE_FORCEWAKE
- INTEL_GUC_ACTION_SLPC_REQUEST
- INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING
- INTEL_GUC_CT_BUFFER_TYPE_RECV
- INTEL_GUC_CT_BUFFER_TYPE_SEND
- INTEL_GUC_MSG_CODE_MASK
- INTEL_GUC_MSG_CODE_SHIFT
- INTEL_GUC_MSG_DATA_MASK
- INTEL_GUC_MSG_DATA_SHIFT
- INTEL_GUC_MSG_IS_REQUEST
- INTEL_GUC_MSG_IS_RESPONSE
- INTEL_GUC_MSG_IS_RESPONSE_SUCCESS
- INTEL_GUC_MSG_TO_CODE
- INTEL_GUC_MSG_TO_DATA
- INTEL_GUC_MSG_TO_TYPE
- INTEL_GUC_MSG_TYPE_MASK
- INTEL_GUC_MSG_TYPE_REQUEST
- INTEL_GUC_MSG_TYPE_RESPONSE
- INTEL_GUC_MSG_TYPE_SHIFT
- INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q
- INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q
- INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED
- INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER
- INTEL_GUC_REPORT_STATUS_ACKED
- INTEL_GUC_REPORT_STATUS_COMPLETE
- INTEL_GUC_REPORT_STATUS_ERROR
- INTEL_GUC_REPORT_STATUS_UNKNOWN
- INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL
- INTEL_GUC_RESPONSE_STATUS_SUCCESS
- INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED
- INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED
- INTEL_GUC_SLEEP_STATE_SUCCESS
- INTEL_GVT_EVENT_MAX
- INTEL_GVT_EVENT_RESERVED
- INTEL_GVT_HYPERVISOR_KVM
- INTEL_GVT_HYPERVISOR_XEN
- INTEL_GVT_INVALID_ADDR
- INTEL_GVT_IRQ_BITWIDTH
- INTEL_GVT_IRQ_INFO_AUD
- INTEL_GVT_IRQ_INFO_DE_MISC
- INTEL_GVT_IRQ_INFO_DE_PIPE_A
- INTEL_GVT_IRQ_INFO_DE_PIPE_B
- INTEL_GVT_IRQ_INFO_DE_PIPE_C
- INTEL_GVT_IRQ_INFO_DE_PORT
- INTEL_GVT_IRQ_INFO_DPY
- INTEL_GVT_IRQ_INFO_GT
- INTEL_GVT_IRQ_INFO_GT0
- INTEL_GVT_IRQ_INFO_GT1
- INTEL_GVT_IRQ_INFO_GT2
- INTEL_GVT_IRQ_INFO_GT3
- INTEL_GVT_IRQ_INFO_MASTER
- INTEL_GVT_IRQ_INFO_MAX
- INTEL_GVT_IRQ_INFO_PCH
- INTEL_GVT_IRQ_INFO_PCU
- INTEL_GVT_IRQ_INFO_PM
- INTEL_GVT_MAX_BAR_NUM
- INTEL_GVT_MAX_NUM_FENCES
- INTEL_GVT_MAX_UEVENT_VARS
- INTEL_GVT_MMIO_HASH_BITS
- INTEL_GVT_MM_GGTT
- INTEL_GVT_MM_PPGTT
- INTEL_GVT_OPREGION_CLID
- INTEL_GVT_OPREGION_PAGES
- INTEL_GVT_OPREGION_PARM
- INTEL_GVT_OPREGION_SCIC
- INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS
- INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA
- INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS
- INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS
- INTEL_GVT_OPREGION_SIZE
- INTEL_GVT_OPREGION_VBT_OFFSET
- INTEL_GVT_OPREGION_VBT_SIZE
- INTEL_GVT_PCI_BAR_APERTURE
- INTEL_GVT_PCI_BAR_GTTMMIO
- INTEL_GVT_PCI_BAR_MAX
- INTEL_GVT_PCI_BAR_PIO
- INTEL_GVT_PCI_CLASS_VGA_OTHER
- INTEL_GVT_PCI_GMCH_CONTROL
- INTEL_GVT_PCI_OPREGION
- INTEL_GVT_PCI_SWSCI
- INTEL_GVT_REQUEST_EMULATE_VBLANK
- INTEL_GVT_REQUEST_EVENT_SCHED
- INTEL_GVT_REQUEST_SCHED
- INTEL_HAD
- INTEL_HASWELL
- INTEL_HDA_CGCTL
- INTEL_HDA_CGCTL_MISCBDCGE
- INTEL_HDMIB_CLONE_BIT
- INTEL_HDMIC_CLONE_BIT
- INTEL_HDMID_CLONE_BIT
- INTEL_HDMIE_CLONE_BIT
- INTEL_HDMIF_CLONE_BIT
- INTEL_HID_DSM_BTNE_FN
- INTEL_HID_DSM_BTNL_FN
- INTEL_HID_DSM_BTNS_FN
- INTEL_HID_DSM_FN_INVALID
- INTEL_HID_DSM_FN_MAX
- INTEL_HID_DSM_HDEM_FN
- INTEL_HID_DSM_HDMM_FN
- INTEL_HID_DSM_HDSM_FN
- INTEL_HID_DSM_HEBC_V1_FN
- INTEL_HID_DSM_HEBC_V2_FN
- INTEL_HID_DSM_VGBS_FN
- INTEL_HOTPLUG_CHANGED
- INTEL_HOTPLUG_RETRY
- INTEL_HOTPLUG_UNCHANGED
- INTEL_HS400_ES_BIT
- INTEL_HS400_ES_REG
- INTEL_HSW_GT1_IDS
- INTEL_HSW_GT2_IDS
- INTEL_HSW_GT3_IDS
- INTEL_HSW_IDS
- INTEL_HSW_ULT_GT1_IDS
- INTEL_HSW_ULT_GT2_IDS
- INTEL_HSW_ULT_GT3_IDS
- INTEL_HSW_ULX_GT1_IDS
- INTEL_HSW_ULX_GT2_IDS
- INTEL_I460_AGPSIZ
- INTEL_I460_ATTBASE
- INTEL_I460_BAPBASE
- INTEL_I460_GATT_COHERENT
- INTEL_I460_GATT_VALID
- INTEL_I460_GXBCTL
- INTEL_I7505_AGPCTRL
- INTEL_I7505_APSIZE
- INTEL_I7505_ATTBASE
- INTEL_I7505_ERRSTS
- INTEL_I7505_MCHCFG
- INTEL_I7505_NCAPID
- INTEL_I7505_NISTAT
- INTEL_I810_IDS
- INTEL_I815_IDS
- INTEL_I820_ERRSTS
- INTEL_I820_RDCR
- INTEL_I830
- INTEL_I830_ERRSTS
- INTEL_I830_IDS
- INTEL_I840_ERRSTS
- INTEL_I840_MCHCFG
- INTEL_I845G
- INTEL_I845G_IDS
- INTEL_I845_AGPM
- INTEL_I845_ERRSTS
- INTEL_I850_ERRSTS
- INTEL_I850_MCHCFG
- INTEL_I85X
- INTEL_I85X_IDS
- INTEL_I860_ERRSTS
- INTEL_I860_MCHCFG
- INTEL_I865G
- INTEL_I865G_IDS
- INTEL_I915G
- INTEL_I915GM
- INTEL_I915GM_IDS
- INTEL_I915G_IDS
- INTEL_I945G
- INTEL_I945GM
- INTEL_I945GM_IDS
- INTEL_I945G_IDS
- INTEL_I965G
- INTEL_I965GM
- INTEL_I965GM_IDS
- INTEL_I965G_IDS
- INTEL_ICELAKE
- INTEL_ICL_11_IDS
- INTEL_ICL_PORT_F_IDS
- INTEL_IDLE_VERSION
- INTEL_INFO
- INTEL_IOMMU_PGSIZES
- INTEL_IRONLAKE
- INTEL_IRONLAKE_D_IDS
- INTEL_IRONLAKE_M_IDS
- INTEL_IRQ_REROUTE_VARIANT
- INTEL_IVB_D_GT1_IDS
- INTEL_IVB_D_GT2_IDS
- INTEL_IVB_D_IDS
- INTEL_IVB_M_GT1_IDS
- INTEL_IVB_M_GT2_IDS
- INTEL_IVB_M_IDS
- INTEL_IVB_Q_IDS
- INTEL_IVYBRIDGE
- INTEL_KABYLAKE
- INTEL_KBL_GT1_IDS
- INTEL_KBL_GT2_IDS
- INTEL_KBL_GT3_IDS
- INTEL_KBL_GT4_IDS
- INTEL_KBL_IDS
- INTEL_KBL_ULT_GT1_IDS
- INTEL_KBL_ULT_GT2_IDS
- INTEL_KBL_ULT_GT3_IDS
- INTEL_KBL_ULX_GT1_IDS
- INTEL_KBL_ULX_GT2_IDS
- INTEL_LEGACY_32B_CONTEXT
- INTEL_LEGACY_64B_CONTEXT
- INTEL_LEGACY_BLK_BASE_ADDR
- INTEL_LIMIT_I9XX_LVDS
- INTEL_LIMIT_I9XX_SDVO_DAC
- INTEL_LPC_RCBA_ENABLE
- INTEL_LPC_RCBA_MASK
- INTEL_LPC_RCBA_REG
- INTEL_LPSS_PM_OPS
- INTEL_LPSS_RUNTIME_PM_OPS
- INTEL_LPSS_SLEEP_PM_OPS
- INTEL_LVDS_CLONE_BIT
- INTEL_MAX_PLATFORMS
- INTEL_MID_CPU_CHIP_CLOVERVIEW
- INTEL_MID_CPU_CHIP_PENWELL
- INTEL_MID_CPU_CHIP_TANGIER
- INTEL_MID_IRQ_OFFSET
- INTEL_MID_IRQ_TYPE_EDGE
- INTEL_MID_IRQ_TYPE_LEVEL
- INTEL_MID_PWR_LSS_OFFSET
- INTEL_MID_PWR_LSS_TYPE
- INTEL_MID_STD_CFG
- INTEL_MID_TIMER_APBT_ONLY
- INTEL_MID_TIMER_DEFAULT
- INTEL_MID_TIMER_LAPIC_APBT
- INTEL_MID_UART_DIV
- INTEL_MID_UART_FISR
- INTEL_MID_UART_MUL
- INTEL_MID_UART_PS
- INTEL_MOCS_H
- INTEL_MODE_PIXEL_MULTIPLIER_MASK
- INTEL_MODE_PIXEL_MULTIPLIER_SHIFT
- INTEL_MPC_REG
- INTEL_MPC_REG_IRBNCE
- INTEL_MRFLD_EMMC_0
- INTEL_MRFLD_EMMC_1
- INTEL_MRFLD_SD
- INTEL_MRFLD_SDIO
- INTEL_MRFLD_SD_CD_GPIO
- INTEL_MRST
- INTEL_MSIC_ACCDET
- INTEL_MSIC_ACCDETMASK
- INTEL_MSIC_ADC1ADDR0
- INTEL_MSIC_ADC1ADDR1
- INTEL_MSIC_ADC1ADDR10
- INTEL_MSIC_ADC1ADDR11
- INTEL_MSIC_ADC1ADDR12
- INTEL_MSIC_ADC1ADDR13
- INTEL_MSIC_ADC1ADDR14
- INTEL_MSIC_ADC1ADDR2
- INTEL_MSIC_ADC1ADDR3
- INTEL_MSIC_ADC1ADDR4
- INTEL_MSIC_ADC1ADDR5
- INTEL_MSIC_ADC1ADDR6
- INTEL_MSIC_ADC1ADDR7
- INTEL_MSIC_ADC1ADDR8
- INTEL_MSIC_ADC1ADDR9
- INTEL_MSIC_ADC1BI0H
- INTEL_MSIC_ADC1BI0L
- INTEL_MSIC_ADC1BI1H
- INTEL_MSIC_ADC1BI1L
- INTEL_MSIC_ADC1BI2H
- INTEL_MSIC_ADC1BI2L
- INTEL_MSIC_ADC1BI3H
- INTEL_MSIC_ADC1BI3L
- INTEL_MSIC_ADC1BV0H
- INTEL_MSIC_ADC1BV0L
- INTEL_MSIC_ADC1BV1H
- INTEL_MSIC_ADC1BV1L
- INTEL_MSIC_ADC1BV2H
- INTEL_MSIC_ADC1BV2L
- INTEL_MSIC_ADC1BV3H
- INTEL_MSIC_ADC1BV3L
- INTEL_MSIC_ADC1CNTL1
- INTEL_MSIC_ADC1CNTL2
- INTEL_MSIC_ADC1CNTL3
- INTEL_MSIC_ADC1INT
- INTEL_MSIC_ADC1OFFSETH
- INTEL_MSIC_ADC1OFFSETL
- INTEL_MSIC_ADC1SNS0H
- INTEL_MSIC_ADC1SNS0L
- INTEL_MSIC_ADC1SNS10H
- INTEL_MSIC_ADC1SNS10L
- INTEL_MSIC_ADC1SNS11H
- INTEL_MSIC_ADC1SNS11L
- INTEL_MSIC_ADC1SNS12H
- INTEL_MSIC_ADC1SNS12L
- INTEL_MSIC_ADC1SNS13H
- INTEL_MSIC_ADC1SNS13L
- INTEL_MSIC_ADC1SNS14H
- INTEL_MSIC_ADC1SNS14L
- INTEL_MSIC_ADC1SNS1H
- INTEL_MSIC_ADC1SNS1L
- INTEL_MSIC_ADC1SNS2H
- INTEL_MSIC_ADC1SNS2L
- INTEL_MSIC_ADC1SNS3H
- INTEL_MSIC_ADC1SNS3L
- INTEL_MSIC_ADC1SNS4H
- INTEL_MSIC_ADC1SNS4L
- INTEL_MSIC_ADC1SNS5H
- INTEL_MSIC_ADC1SNS5L
- INTEL_MSIC_ADC1SNS6H
- INTEL_MSIC_ADC1SNS6L
- INTEL_MSIC_ADC1SNS7H
- INTEL_MSIC_ADC1SNS7L
- INTEL_MSIC_ADC1SNS8H
- INTEL_MSIC_ADC1SNS8L
- INTEL_MSIC_ADC1SNS9H
- INTEL_MSIC_ADC1SNS9L
- INTEL_MSIC_ADCCONFIG
- INTEL_MSIC_ADPDETDBDM
- INTEL_MSIC_ADPHVDET
- INTEL_MSIC_ADPLVDET
- INTEL_MSIC_AUDIOMUX12
- INTEL_MSIC_AUDIOMUX34
- INTEL_MSIC_AUDIOSINC
- INTEL_MSIC_AUDIOTXEN
- INTEL_MSIC_AUDPLLCTRL
- INTEL_MSIC_BATCURRENTLIMIT12
- INTEL_MSIC_BATTIMEDB
- INTEL_MSIC_BATTIMELIMIT12
- INTEL_MSIC_BATTIMELIMIT3
- INTEL_MSIC_BATTRMV
- INTEL_MSIC_BDTIMER
- INTEL_MSIC_BLOCK_ADC
- INTEL_MSIC_BLOCK_AUDIO
- INTEL_MSIC_BLOCK_BATTERY
- INTEL_MSIC_BLOCK_GPIO
- INTEL_MSIC_BLOCK_HDMI
- INTEL_MSIC_BLOCK_LAST
- INTEL_MSIC_BLOCK_OCD
- INTEL_MSIC_BLOCK_POWER_BTN
- INTEL_MSIC_BLOCK_THERMAL
- INTEL_MSIC_BLOCK_TOUCH
- INTEL_MSIC_BRSTCONFIGACTIONS
- INTEL_MSIC_BRSTCONFIGOUTPUTS
- INTEL_MSIC_BTNCTRL1
- INTEL_MSIC_BTNCTRL2
- INTEL_MSIC_BURSTCONTROLSTATUS
- INTEL_MSIC_CCADCHA
- INTEL_MSIC_CCADCLA
- INTEL_MSIC_CCCNTL
- INTEL_MSIC_CCINT
- INTEL_MSIC_CCOFFSETH
- INTEL_MSIC_CCOFFSETL
- INTEL_MSIC_CHIPCNTRL
- INTEL_MSIC_CHRCCURRENT
- INTEL_MSIC_CHRCTRL
- INTEL_MSIC_CHRCTRL1
- INTEL_MSIC_CHRCVOLTAGE
- INTEL_MSIC_CHRINT
- INTEL_MSIC_CHRINT1
- INTEL_MSIC_CHRLEDCTRL
- INTEL_MSIC_CHRLEDPWM
- INTEL_MSIC_CHRSAFELMT
- INTEL_MSIC_CHRSTWDT
- INTEL_MSIC_CHRTTIME
- INTEL_MSIC_DACCONFIG
- INTEL_MSIC_DMICBUF0123
- INTEL_MSIC_DMICBUF45
- INTEL_MSIC_DMICCLK
- INTEL_MSIC_DMICGPO
- INTEL_MSIC_DMICMUX
- INTEL_MSIC_DRIVEREN
- INTEL_MSIC_ERCONFIG
- INTEL_MSIC_GPIO0HV0CTLI
- INTEL_MSIC_GPIO0HV0CTLO
- INTEL_MSIC_GPIO0HV1CTLI
- INTEL_MSIC_GPIO0HV1CTLO
- INTEL_MSIC_GPIO0HV2CTLI
- INTEL_MSIC_GPIO0HV2CTLO
- INTEL_MSIC_GPIO0HV3CTLI
- INTEL_MSIC_GPIO0HV3CTLO
- INTEL_MSIC_GPIO0LV0CTLI
- INTEL_MSIC_GPIO0LV0CTLO
- INTEL_MSIC_GPIO0LV1CTLI
- INTEL_MSIC_GPIO0LV1CTLO
- INTEL_MSIC_GPIO0LV2CTLI
- INTEL_MSIC_GPIO0LV2CTLO
- INTEL_MSIC_GPIO0LV3CTLI
- INTEL_MSIC_GPIO0LV3CTLO
- INTEL_MSIC_GPIO0LV4CTLI
- INTEL_MSIC_GPIO0LV4CTLO
- INTEL_MSIC_GPIO0LV5CTLI
- INTEL_MSIC_GPIO0LV5CTLO
- INTEL_MSIC_GPIO0LV6CTLI
- INTEL_MSIC_GPIO0LV6CTLO
- INTEL_MSIC_GPIO0LV7CTLI
- INTEL_MSIC_GPIO0LV7CTLO
- INTEL_MSIC_GPIO0LVIRQ
- INTEL_MSIC_GPIO0LVIRQMASK
- INTEL_MSIC_GPIO1HV0CTLI
- INTEL_MSIC_GPIO1HV0CTLO
- INTEL_MSIC_GPIO1HV1CTLI
- INTEL_MSIC_GPIO1HV1CTLO
- INTEL_MSIC_GPIO1HV2CTLI
- INTEL_MSIC_GPIO1HV2CTLO
- INTEL_MSIC_GPIO1HV3CTLI
- INTEL_MSIC_GPIO1HV3CTLO
- INTEL_MSIC_GPIO1LV0CTLI
- INTEL_MSIC_GPIO1LV0CTLO
- INTEL_MSIC_GPIO1LV1CTLI
- INTEL_MSIC_GPIO1LV1CTLO
- INTEL_MSIC_GPIO1LV2CTLI
- INTEL_MSIC_GPIO1LV2CTLO
- INTEL_MSIC_GPIO1LV3CTLI
- INTEL_MSIC_GPIO1LV3CTLO
- INTEL_MSIC_GPIO1LV4CTLI
- INTEL_MSIC_GPIO1LV4CTLO
- INTEL_MSIC_GPIO1LV5CTLI
- INTEL_MSIC_GPIO1LV5CTLO
- INTEL_MSIC_GPIO1LV6CTLI
- INTEL_MSIC_GPIO1LV6CTLO
- INTEL_MSIC_GPIO1LV7CTLIS
- INTEL_MSIC_GPIO1LV7CTLOS
- INTEL_MSIC_GPIO1LVIRQ
- INTEL_MSIC_GPIO1LVIRQMASK
- INTEL_MSIC_GPIOHVIRQ
- INTEL_MSIC_GPIOHVIRQMASK
- INTEL_MSIC_HDMIPUEN
- INTEL_MSIC_HDMISTATUS
- INTEL_MSIC_HSEPRXCTRL
- INTEL_MSIC_HSLVOLCTRL
- INTEL_MSIC_HSMIXER
- INTEL_MSIC_HSRVOLCTRL
- INTEL_MSIC_ID0
- INTEL_MSIC_ID1
- INTEL_MSIC_IHFLVOLCTRL
- INTEL_MSIC_IHFRVOLCTRL
- INTEL_MSIC_IHFRXCTRL
- INTEL_MSIC_IRQLVL1
- INTEL_MSIC_IRQLVL1MSK
- INTEL_MSIC_IRQ_PHYS_BASE
- INTEL_MSIC_LDORAMP1
- INTEL_MSIC_LDORAMP2
- INTEL_MSIC_LINEOUTCTRL
- INTEL_MSIC_LOWBATTDET
- INTEL_MSIC_MADC1INT
- INTEL_MSIC_MCCINT
- INTEL_MSIC_MCHRINT
- INTEL_MSIC_MCHRINT1
- INTEL_MSIC_MICAMP1
- INTEL_MSIC_MICAMP2
- INTEL_MSIC_MICBIAS
- INTEL_MSIC_MPWRSRCINT
- INTEL_MSIC_MPWRSRCINT1
- INTEL_MSIC_MUSICSHARVOL
- INTEL_MSIC_NOISEMUX
- INTEL_MSIC_OCAUDIO
- INTEL_MSIC_OCAUDIOMASK
- INTEL_MSIC_PBCONFIG
- INTEL_MSIC_PBSTATUS
- INTEL_MSIC_PCM1CTRL1
- INTEL_MSIC_PCM1CTRL2
- INTEL_MSIC_PCM1CTRL3
- INTEL_MSIC_PCM1RXSLOT0123
- INTEL_MSIC_PCM1RXSLOT045
- INTEL_MSIC_PCM1TXSLOT01
- INTEL_MSIC_PCM1TXSLOT23
- INTEL_MSIC_PCM1TXSLOT45
- INTEL_MSIC_PCM2CTRL1
- INTEL_MSIC_PCM2CTRL2
- INTEL_MSIC_PCM2RXSLOT01
- INTEL_MSIC_PCM2RXSLOT23
- INTEL_MSIC_PCM2RXSLOT45
- INTEL_MSIC_PCM2TXSLOT01
- INTEL_MSIC_PCM2TXSLOT23
- INTEL_MSIC_PCM2TXSLOT45
- INTEL_MSIC_PWM0CLKDIV0
- INTEL_MSIC_PWM0CLKDIV1
- INTEL_MSIC_PWM0DUTYCYCLE
- INTEL_MSIC_PWM1CLKDIV0
- INTEL_MSIC_PWM1CLKDIV1
- INTEL_MSIC_PWM1DUTYCYCLE
- INTEL_MSIC_PWM2CLKDIV0
- INTEL_MSIC_PWM2CLKDIV1
- INTEL_MSIC_PWM2DUTYCYCLE
- INTEL_MSIC_PWRSRCINT
- INTEL_MSIC_PWRSRCINT1
- INTEL_MSIC_PWRSRCLMT
- INTEL_MSIC_RESETIRQ1
- INTEL_MSIC_RESETIRQ1MASK
- INTEL_MSIC_RESETIRQ2
- INTEL_MSIC_RESETIRQ2MASK
- INTEL_MSIC_RTCAB1
- INTEL_MSIC_RTCAB2
- INTEL_MSIC_RTCAB3
- INTEL_MSIC_RTCAB4
- INTEL_MSIC_RTCB1
- INTEL_MSIC_RTCB2
- INTEL_MSIC_RTCB3
- INTEL_MSIC_RTCB4
- INTEL_MSIC_RTCCONFIG1
- INTEL_MSIC_RTCCONFIG2
- INTEL_MSIC_RTCIRQ
- INTEL_MSIC_RTCIRQMASK
- INTEL_MSIC_RTCOB1
- INTEL_MSIC_RTCOB2
- INTEL_MSIC_RTCOB3
- INTEL_MSIC_RTCOB4
- INTEL_MSIC_RTCSC1
- INTEL_MSIC_RTCSC2
- INTEL_MSIC_RTCSC3
- INTEL_MSIC_RTCSC4
- INTEL_MSIC_RTCSTATUS
- INTEL_MSIC_RTCWAB1
- INTEL_MSIC_RTCWAB2
- INTEL_MSIC_RTCWAB3
- INTEL_MSIC_RTCWAB4
- INTEL_MSIC_SIDETONEVOL
- INTEL_MSIC_SMPSRAMP
- INTEL_MSIC_SOFTMUTE
- INTEL_MSIC_SPCHARGER
- INTEL_MSIC_SPWRSRCINT
- INTEL_MSIC_SPWRSRCINT1
- INTEL_MSIC_SVIDCTRL0
- INTEL_MSIC_SVIDCTRL1
- INTEL_MSIC_SVIDCTRL2
- INTEL_MSIC_SVIDPKTOUTBYTE0
- INTEL_MSIC_SVIDPKTOUTBYTE1
- INTEL_MSIC_SVIDPKTOUTBYTE2
- INTEL_MSIC_SVIDPKTOUTBYTE3
- INTEL_MSIC_SVIDRXCHKSTATUS0
- INTEL_MSIC_SVIDRXCHKSTATUS1
- INTEL_MSIC_SVIDRXCHKSTATUS2
- INTEL_MSIC_SVIDRXCHKSTATUS3
- INTEL_MSIC_SVIDRXLASTPKT0
- INTEL_MSIC_SVIDRXLASTPKT1
- INTEL_MSIC_SVIDRXLASTPKT2
- INTEL_MSIC_SVIDRXLASTPKT3
- INTEL_MSIC_SVIDRXVPDEBUG0
- INTEL_MSIC_SVIDRXVPDEBUG1
- INTEL_MSIC_SVIDTXLASTPKT0
- INTEL_MSIC_SVIDTXLASTPKT1
- INTEL_MSIC_SVIDTXLASTPKT2
- INTEL_MSIC_SVIDTXLASTPKT3
- INTEL_MSIC_V180AONCNT
- INTEL_MSIC_V1P35CNT
- INTEL_MSIC_V330AONCNT
- INTEL_MSIC_V500CNT
- INTEL_MSIC_VAUDACNT
- INTEL_MSIC_VBUSDET
- INTEL_MSIC_VBUSDET1
- INTEL_MSIC_VCC108AONCNT
- INTEL_MSIC_VCC108ASCNT
- INTEL_MSIC_VCC108CNT
- INTEL_MSIC_VCC122AONCNT
- INTEL_MSIC_VCC180AONCNT
- INTEL_MSIC_VCC180CNT
- INTEL_MSIC_VCC330CNT
- INTEL_MSIC_VCCA100ASCNT
- INTEL_MSIC_VCCA100CNT
- INTEL_MSIC_VCCCNT
- INTEL_MSIC_VCCLATCH
- INTEL_MSIC_VCCSDIOCNT
- INTEL_MSIC_VEMMC1CNT
- INTEL_MSIC_VEMMC2CNT
- INTEL_MSIC_VEMMCSCNT
- INTEL_MSIC_VHDMICNT
- INTEL_MSIC_VHSNCNT
- INTEL_MSIC_VHSPCNT
- INTEL_MSIC_VIB1CTRL1
- INTEL_MSIC_VIB1CTRL2
- INTEL_MSIC_VIB1CTRL3
- INTEL_MSIC_VIB1CTRL5
- INTEL_MSIC_VIB1SPIPCM_1
- INTEL_MSIC_VIB1SPIPCM_2
- INTEL_MSIC_VIB2CTRL1
- INTEL_MSIC_VIB2CTRL2
- INTEL_MSIC_VIB2CTRL3
- INTEL_MSIC_VIB2CTRL5
- INTEL_MSIC_VIB2SPIPCM_1
- INTEL_MSIC_VIB2SPIPCM_2
- INTEL_MSIC_VIHFCNT
- INTEL_MSIC_VNNAONCNT
- INTEL_MSIC_VNNCNT
- INTEL_MSIC_VNNLATCH
- INTEL_MSIC_VOICETXCTRL
- INTEL_MSIC_VOICETXVOL
- INTEL_MSIC_VOTGCNT
- INTEL_MSIC_VPROG1CNT
- INTEL_MSIC_VPROG2CNT
- INTEL_MSIC_VRINT
- INTEL_MSIC_VRINTMASK
- INTEL_MSIC_VUSB330CNT
- INTEL_MSIC_WDTWRITE
- INTEL_MSR_RANGE
- INTEL_NBXCFG
- INTEL_OUI_1
- INTEL_OUI_2
- INTEL_OUI_3
- INTEL_OUTPUT_ANALOG
- INTEL_OUTPUT_DDI
- INTEL_OUTPUT_DISPLAYPORT
- INTEL_OUTPUT_DP
- INTEL_OUTPUT_DP_MST
- INTEL_OUTPUT_DSI
- INTEL_OUTPUT_DVO
- INTEL_OUTPUT_EDP
- INTEL_OUTPUT_FORMAT_INVALID
- INTEL_OUTPUT_FORMAT_RGB
- INTEL_OUTPUT_FORMAT_YCBCR420
- INTEL_OUTPUT_FORMAT_YCBCR444
- INTEL_OUTPUT_HDMI
- INTEL_OUTPUT_LVDS
- INTEL_OUTPUT_MIPI
- INTEL_OUTPUT_MIPI2
- INTEL_OUTPUT_SDVO
- INTEL_OUTPUT_TVOUT
- INTEL_OUTPUT_UNUSED
- INTEL_PCH_CMP2_DEVICE_ID_TYPE
- INTEL_PCH_CMP_DEVICE_ID_TYPE
- INTEL_PCH_CNP_DEVICE_ID_TYPE
- INTEL_PCH_CNP_LP_DEVICE_ID_TYPE
- INTEL_PCH_CPT_DEVICE_ID_TYPE
- INTEL_PCH_DEVICE_ID_MASK
- INTEL_PCH_IBX_DEVICE_ID_TYPE
- INTEL_PCH_ICP_DEVICE_ID_TYPE
- INTEL_PCH_ID
- INTEL_PCH_KBP_DEVICE_ID_TYPE
- INTEL_PCH_LPT_DEVICE_ID_TYPE
- INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
- INTEL_PCH_MCC2_DEVICE_ID_TYPE
- INTEL_PCH_MCC_DEVICE_ID_TYPE
- INTEL_PCH_P2X_DEVICE_ID_TYPE
- INTEL_PCH_P3X_DEVICE_ID_TYPE
- INTEL_PCH_PPT_DEVICE_ID_TYPE
- INTEL_PCH_QEMU_DEVICE_ID_TYPE
- INTEL_PCH_SPT_DEVICE_ID_TYPE
- INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
- INTEL_PCH_TGP_DEVICE_ID_TYPE
- INTEL_PCH_TYPE
- INTEL_PCH_WPT_DEVICE_ID_TYPE
- INTEL_PCH_WPT_LP_DEVICE_ID_TYPE
- INTEL_PDI_BD
- INTEL_PDI_IN
- INTEL_PDI_OUT
- INTEL_PERF_CTL_MASK
- INTEL_PINCTRL_PM_OPS
- INTEL_PINEVIEW
- INTEL_PINEVIEW_G_IDS
- INTEL_PINEVIEW_M_IDS
- INTEL_PIPE_CRC_ENTRIES_NR
- INTEL_PIPE_CRC_SOURCE_AUTO
- INTEL_PIPE_CRC_SOURCE_DP_B
- INTEL_PIPE_CRC_SOURCE_DP_C
- INTEL_PIPE_CRC_SOURCE_DP_D
- INTEL_PIPE_CRC_SOURCE_MAX
- INTEL_PIPE_CRC_SOURCE_NONE
- INTEL_PIPE_CRC_SOURCE_PIPE
- INTEL_PIPE_CRC_SOURCE_PLANE1
- INTEL_PIPE_CRC_SOURCE_PLANE2
- INTEL_PIPE_CRC_SOURCE_PLANE3
- INTEL_PIPE_CRC_SOURCE_PLANE4
- INTEL_PIPE_CRC_SOURCE_PLANE5
- INTEL_PIPE_CRC_SOURCE_PLANE6
- INTEL_PIPE_CRC_SOURCE_PLANE7
- INTEL_PIPE_CRC_SOURCE_TV
- INTEL_PLATFORM_UNINITIALIZED
- INTEL_PLD_CONSTRAINT
- INTEL_PMC_IDX_FIXED
- INTEL_PMC_IDX_FIXED_BTS
- INTEL_PMC_IDX_FIXED_CPU_CYCLES
- INTEL_PMC_IDX_FIXED_INSTRUCTIONS
- INTEL_PMC_IDX_FIXED_REF_CYCLES
- INTEL_PMC_MAX_FIXED
- INTEL_PMC_MAX_GENERIC
- INTEL_PMC_MSK_FIXED_REF_CYCLES
- INTEL_PMC_TYPE_SHIFT
- INTEL_PPGTT
- INTEL_PPGTT_ALIASING
- INTEL_PPGTT_FULL
- INTEL_PPGTT_NONE
- INTEL_PSTATE_HWP_BROADWELL
- INTEL_PSTATE_SAMPLING_INTERVAL
- INTEL_PSTATE_TRACE_FAST_SWITCH
- INTEL_PSTATE_TRACE_TARGET
- INTEL_PST_CONSTRAINT
- INTEL_PT_ABORT_TX
- INTEL_PT_ASYNC
- INTEL_PT_AUXTRACE_PRIV_MAX
- INTEL_PT_BAD
- INTEL_PT_BAD_PACKET
- INTEL_PT_BBP
- INTEL_PT_BEP
- INTEL_PT_BEP_IP
- INTEL_PT_BIP
- INTEL_PT_BLK_4_CTX
- INTEL_PT_BLK_8_CTX
- INTEL_PT_BLK_ITEMS
- INTEL_PT_BLK_ITEM_ID_CNT
- INTEL_PT_BLK_SIZE
- INTEL_PT_BLK_TYPE_CNT
- INTEL_PT_BLK_TYPE_MAX
- INTEL_PT_BRANCH
- INTEL_PT_BR_CONDITIONAL
- INTEL_PT_BR_INDIRECT
- INTEL_PT_BR_NO_BRANCH
- INTEL_PT_BR_UNCONDITIONAL
- INTEL_PT_CAP_USER_TIME_ZERO
- INTEL_PT_CBR
- INTEL_PT_CBR_CHG
- INTEL_PT_CYC
- INTEL_PT_CYC_BIT
- INTEL_PT_ERR_BADPKT
- INTEL_PT_ERR_INTERN
- INTEL_PT_ERR_LOST
- INTEL_PT_ERR_MAX
- INTEL_PT_ERR_MISMAT
- INTEL_PT_ERR_NELOOP
- INTEL_PT_ERR_NODATA
- INTEL_PT_ERR_NOINSN
- INTEL_PT_ERR_NOMEM
- INTEL_PT_ERR_OVR
- INTEL_PT_ERR_UNK
- INTEL_PT_EXSTOP
- INTEL_PT_EXSTOP_IP
- INTEL_PT_EX_STOP
- INTEL_PT_FILTER_STR_LEN
- INTEL_PT_FUP
- INTEL_PT_FUP_IP
- INTEL_PT_FUP_WITH_NLIP
- INTEL_PT_GP_REGS
- INTEL_PT_GP_REGS_POS
- INTEL_PT_HAVE_SCHED_SWITCH
- INTEL_PT_INSN_BUF_SZ
- INTEL_PT_INSN_DESC_MAX
- INTEL_PT_INSTRUCTION
- INTEL_PT_IN_TX
- INTEL_PT_LBR_0
- INTEL_PT_LBR_0_POS
- INTEL_PT_LBR_1
- INTEL_PT_LBR_1_POS
- INTEL_PT_LBR_2
- INTEL_PT_LBR_2_POS
- INTEL_PT_MAX_LOOPS
- INTEL_PT_MAX_NONTURBO_RATIO
- INTEL_PT_MNT
- INTEL_PT_MODE_EXEC
- INTEL_PT_MODE_TSX
- INTEL_PT_MTC
- INTEL_PT_MTC_BIT
- INTEL_PT_MTC_FREQ_BITS
- INTEL_PT_MWAIT
- INTEL_PT_MWAIT_OP
- INTEL_PT_NEED_MORE_BYTES
- INTEL_PT_NORETCOMP_BIT
- INTEL_PT_NO_CTX
- INTEL_PT_OP_CALL
- INTEL_PT_OP_INT
- INTEL_PT_OP_IRET
- INTEL_PT_OP_JCC
- INTEL_PT_OP_JMP
- INTEL_PT_OP_LOOP
- INTEL_PT_OP_OTHER
- INTEL_PT_OP_RET
- INTEL_PT_OP_SYSCALL
- INTEL_PT_OP_SYSRET
- INTEL_PT_OVF
- INTEL_PT_PAD
- INTEL_PT_PEBS_BASIC
- INTEL_PT_PEBS_BASIC_POS
- INTEL_PT_PEBS_MEM
- INTEL_PT_PEBS_MEM_POS
- INTEL_PT_PERIOD_INSTRUCTIONS
- INTEL_PT_PERIOD_MTC
- INTEL_PT_PERIOD_NONE
- INTEL_PT_PERIOD_TICKS
- INTEL_PT_PER_CPU_MMAPS
- INTEL_PT_PIP
- INTEL_PT_PKT_DESC_MAX
- INTEL_PT_PKT_MAX_SZ
- INTEL_PT_PMU_NAME
- INTEL_PT_PMU_TYPE
- INTEL_PT_PSB
- INTEL_PT_PSBEND
- INTEL_PT_PSB_LEN
- INTEL_PT_PSB_PERIOD_NEAR
- INTEL_PT_PSB_STR
- INTEL_PT_PTW
- INTEL_PT_PTWRITE
- INTEL_PT_PTWRITE_IP
- INTEL_PT_PWRE
- INTEL_PT_PWRX
- INTEL_PT_PWR_ENTRY
- INTEL_PT_PWR_EVT
- INTEL_PT_PWR_EXIT
- INTEL_PT_RETURN
- INTEL_PT_SNAPSHOT_MODE
- INTEL_PT_SS_EXPECTING_SWITCH_EVENT
- INTEL_PT_SS_EXPECTING_SWITCH_IP
- INTEL_PT_SS_NOT_TRACING
- INTEL_PT_SS_TRACING
- INTEL_PT_SS_UNKNOWN
- INTEL_PT_STATE_ERR1
- INTEL_PT_STATE_ERR2
- INTEL_PT_STATE_ERR3
- INTEL_PT_STATE_ERR4
- INTEL_PT_STATE_ERR_RESYNC
- INTEL_PT_STATE_FUP
- INTEL_PT_STATE_FUP_NO_TIP
- INTEL_PT_STATE_IN_SYNC
- INTEL_PT_STATE_NO_IP
- INTEL_PT_STATE_NO_PSB
- INTEL_PT_STATE_TIP
- INTEL_PT_STATE_TIP_PGD
- INTEL_PT_STATE_TNT
- INTEL_PT_STATE_TNT_CONT
- INTEL_PT_TIME_MULT
- INTEL_PT_TIME_SHIFT
- INTEL_PT_TIME_ZERO
- INTEL_PT_TIP
- INTEL_PT_TIP_PGD
- INTEL_PT_TIP_PGE
- INTEL_PT_TMA
- INTEL_PT_TNT
- INTEL_PT_TRACESTOP
- INTEL_PT_TRACE_BEGIN
- INTEL_PT_TRACE_END
- INTEL_PT_TRANSACTION
- INTEL_PT_TSC
- INTEL_PT_TSC_BIT
- INTEL_PT_TSC_CTC_D
- INTEL_PT_TSC_CTC_N
- INTEL_PT_VMCS
- INTEL_PT_XMM
- INTEL_PT_XMM_POS
- INTEL_QUANTA_VGA_DEVICE
- INTEL_QUARK_GPIO_NPORTS
- INTEL_QUARK_I2C_CLK_HZ
- INTEL_QUARK_I2C_CONTROLLER_CLK
- INTEL_QUARK_IORES_IRQ
- INTEL_QUARK_IORES_MEM
- INTEL_QUARK_MFD_GPIO_BASE
- INTEL_QUARK_MFD_NGPIO
- INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD
- INTEL_RAPL_PRIO_DEVID_0
- INTEL_RECV_LPM
- INTEL_REG_SIZE
- INTEL_REVID
- INTEL_RNG_ADDR
- INTEL_RNG_ADDR_LEN
- INTEL_RNG_DATA
- INTEL_RNG_DATA_PRESENT
- INTEL_RNG_ENABLED
- INTEL_RNG_HW_STATUS
- INTEL_RNG_PRESENT
- INTEL_RNG_STATUS
- INTEL_RPM_RAW_WAKEREF_MASK
- INTEL_RPM_WAKELOCK_BIAS
- INTEL_RPM_WAKELOCK_SHIFT
- INTEL_SANDYBRIDGE
- INTEL_SCH_HDA_DEVC
- INTEL_SCH_HDA_DEVC_NOSNOOP
- INTEL_SDVO_LVDS_CLONE_BIT
- INTEL_SDVO_NON_TV_CLONE_BIT
- INTEL_SDVO_TV_CLONE_BIT
- INTEL_SET_VENDOR_VERB
- INTEL_SIP_SMC_ECC_DBE
- INTEL_SIP_SMC_FAST_CALL_VAL
- INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
- INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
- INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
- INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
- INTEL_SIP_SMC_FPGA_CONFIG_START
- INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY
- INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR
- INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED
- INTEL_SIP_SMC_FPGA_CONFIG_WRITE
- INTEL_SIP_SMC_FUNCID_ECC_DBE
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START
- INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE
- INTEL_SIP_SMC_FUNCID_REG_READ
- INTEL_SIP_SMC_FUNCID_REG_UPDATE
- INTEL_SIP_SMC_FUNCID_REG_WRITE
- INTEL_SIP_SMC_FUNCID_RSU_NOTIFY
- INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER
- INTEL_SIP_SMC_FUNCID_RSU_STATUS
- INTEL_SIP_SMC_FUNCID_RSU_UPDATE
- INTEL_SIP_SMC_REG_ERROR
- INTEL_SIP_SMC_REG_READ
- INTEL_SIP_SMC_REG_UPDATE
- INTEL_SIP_SMC_REG_WRITE
- INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
- INTEL_SIP_SMC_RSU_ERROR
- INTEL_SIP_SMC_RSU_NOTIFY
- INTEL_SIP_SMC_RSU_RETRY_COUNTER
- INTEL_SIP_SMC_RSU_STATUS
- INTEL_SIP_SMC_RSU_UPDATE
- INTEL_SIP_SMC_STATUS_OK
- INTEL_SIP_SMC_STD_CALL_VAL
- INTEL_SKL_GT1_IDS
- INTEL_SKL_GT2_IDS
- INTEL_SKL_GT3_IDS
- INTEL_SKL_GT4_IDS
- INTEL_SKL_IDS
- INTEL_SKL_ULT_GT1_IDS
- INTEL_SKL_ULT_GT2_IDS
- INTEL_SKL_ULT_GT3_IDS
- INTEL_SKL_ULX_GT1_IDS
- INTEL_SKL_ULX_GT2_IDS
- INTEL_SKYLAKE
- INTEL_SNB_D_GT1_IDS
- INTEL_SNB_D_GT2_IDS
- INTEL_SNB_D_IDS
- INTEL_SNB_M_GT1_IDS
- INTEL_SNB_M_GT2_IDS
- INTEL_SNB_M_IDS
- INTEL_SOC_DTS_INTERRUPT_APIC
- INTEL_SOC_DTS_INTERRUPT_MSI
- INTEL_SOC_DTS_INTERRUPT_NONE
- INTEL_SOC_DTS_INTERRUPT_SCI
- INTEL_SOC_DTS_INTERRUPT_SMI
- INTEL_SPI_BXT
- INTEL_SPI_BYT
- INTEL_SPI_FIFO_SZ
- INTEL_SPI_H
- INTEL_SPI_LPT
- INTEL_SPI_PDATA_H
- INTEL_SPI_TIMEOUT
- INTEL_SPT_ACS_CTRL
- INTEL_SUBPLATFORM_BITS
- INTEL_SUBPLATFORM_PORTF
- INTEL_SUBPLATFORM_ULT
- INTEL_SUBPLATFORM_ULX
- INTEL_TELEMETRY_H
- INTEL_TGL_12_IDS
- INTEL_TH_CAP
- INTEL_TH_OUTPUT
- INTEL_TH_SOURCE
- INTEL_TH_SWITCH
- INTEL_TIGERLAKE
- INTEL_TV_CLONE_BIT
- INTEL_UBIT_EVENT_CONSTRAINT
- INTEL_UC_FIRMWARE_AVAILABLE
- INTEL_UC_FIRMWARE_DEFS
- INTEL_UC_FIRMWARE_DISABLED
- INTEL_UC_FIRMWARE_ERROR
- INTEL_UC_FIRMWARE_FAIL
- INTEL_UC_FIRMWARE_MISSING
- INTEL_UC_FIRMWARE_NOT_SUPPORTED
- INTEL_UC_FIRMWARE_RUNNING
- INTEL_UC_FIRMWARE_SELECTED
- INTEL_UC_FIRMWARE_TRANSFERRED
- INTEL_UC_FIRMWARE_UNINITIALIZED
- INTEL_UC_FIRMWARE_URL
- INTEL_UC_FW_NUM_TYPES
- INTEL_UC_FW_TYPE_GUC
- INTEL_UC_FW_TYPE_HUC
- INTEL_UC_MODULE_FW
- INTEL_UEVENT_CONSTRAINT
- INTEL_UEVENT_EXTRA_REG
- INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG
- INTEL_UNCORE_EVENT_DESC
- INTEL_UPDCR_REG
- INTEL_UPDCR_REG_MASK
- INTEL_USB_ID_FLOAT
- INTEL_USB_ID_GND
- INTEL_USB_ID_OTG
- INTEL_USB_RID_A
- INTEL_USB_RID_B
- INTEL_USB_RID_C
- INTEL_VALLEYVIEW
- INTEL_VAR_852GM
- INTEL_VAR_852GME
- INTEL_VAR_855GM
- INTEL_VAR_855GME
- INTEL_VENDOR_ID
- INTEL_VENDOR_NID_0x2
- INTEL_VENDOR_NID_0x8
- INTEL_VENDOR_NID_0xb
- INTEL_VGA_DEVICE
- INTEL_VGPU_EXECLIST_SUBMISSION
- INTEL_VGPU_GUC_SUBMISSION
- INTEL_VLV_IDS
- INTEL_VSS_FLAGS_RTD3
- INTEL_WAKEREF_BUG_ON
- INTEL_WAKEREF_H
- INTEL_WAKEREF_PUT_ASYNC
- INTEL_WHL_U_GT1_IDS
- INTEL_WHL_U_GT2_IDS
- INTEL_WHL_U_GT3_IDS
- INTEL_WMI_THUNDERBOLT_GUID
- INTEN
- INTEN0
- INTEN0_BITS
- INTEN0_CLEAR
- INTENB0
- INTENB1
- INTENB2
- INTENT_TO_RECOVER
- INTEN_INT_AFIFO_OF
- INTEN_INT_ERRSOTHS
- INTEN_INT_ERRSOTSYNCHS
- INTEN_REG
- INTER0_IN
- INTER0_OUT
- INTER1_IN
- INTER1_OUT
- INTER2_IN
- INTER2_OUT
- INTER3_IN
- INTER3_OUT
- INTER4_IN
- INTER4_OUT
- INTERACE_SCAN_CFG
- INTERACT_MAX_LENGTH
- INTERACT_MAX_START
- INTERACT_MAX_STROBE
- INTERACT_TYPE_HHFX
- INTERACT_TYPE_PP8D
- INTERBIOMETRICS_IOBOARD_PID
- INTERBIOMETRICS_MINI_IOBOARD_PID
- INTERBIOMETRICS_VID
- INTERCEPT_CLGI
- INTERCEPT_CPUID
- INTERCEPT_CR0_READ
- INTERCEPT_CR0_WRITE
- INTERCEPT_CR3_READ
- INTERCEPT_CR3_WRITE
- INTERCEPT_CR4_READ
- INTERCEPT_CR4_WRITE
- INTERCEPT_CR8_READ
- INTERCEPT_CR8_WRITE
- INTERCEPT_DR0_READ
- INTERCEPT_DR0_WRITE
- INTERCEPT_DR1_READ
- INTERCEPT_DR1_WRITE
- INTERCEPT_DR2_READ
- INTERCEPT_DR2_WRITE
- INTERCEPT_DR3_READ
- INTERCEPT_DR3_WRITE
- INTERCEPT_DR4_READ
- INTERCEPT_DR4_WRITE
- INTERCEPT_DR5_READ
- INTERCEPT_DR5_WRITE
- INTERCEPT_DR6_READ
- INTERCEPT_DR6_WRITE
- INTERCEPT_DR7_READ
- INTERCEPT_DR7_WRITE
- INTERCEPT_FERR_FREEZE
- INTERCEPT_HLT
- INTERCEPT_ICEBP
- INTERCEPT_INIT
- INTERCEPT_INTR
- INTERCEPT_INTn
- INTERCEPT_INVD
- INTERCEPT_INVLPG
- INTERCEPT_INVLPGA
- INTERCEPT_IOIO_PROT
- INTERCEPT_IRET
- INTERCEPT_LOAD_GDTR
- INTERCEPT_LOAD_IDTR
- INTERCEPT_LOAD_LDTR
- INTERCEPT_LOAD_TR
- INTERCEPT_MONITOR
- INTERCEPT_MSR_PROT
- INTERCEPT_MWAIT
- INTERCEPT_MWAIT_COND
- INTERCEPT_NMI
- INTERCEPT_PAUSE
- INTERCEPT_POPF
- INTERCEPT_PUSHF
- INTERCEPT_RDPMC
- INTERCEPT_RDPRU
- INTERCEPT_RDTSC
- INTERCEPT_RDTSCP
- INTERCEPT_RSM
- INTERCEPT_SELECTIVE_CR0
- INTERCEPT_SHUTDOWN
- INTERCEPT_SKINIT
- INTERCEPT_SMI
- INTERCEPT_STGI
- INTERCEPT_STORE_GDTR
- INTERCEPT_STORE_IDTR
- INTERCEPT_STORE_LDTR
- INTERCEPT_STORE_TR
- INTERCEPT_TASK_SWITCH
- INTERCEPT_VINTR
- INTERCEPT_VMLOAD
- INTERCEPT_VMMCALL
- INTERCEPT_VMRUN
- INTERCEPT_VMSAVE
- INTERCEPT_WBINVD
- INTERCEPT_XSETBV
- INTERCOMMAND_DELAY
- INTERCONNECT_DESC_PARAM_LEN
- INTERCONNECT_DESC_PARAM_MPHY_VER
- INTERCONNECT_DESC_PARAM_TYPE
- INTERCONNECT_DESC_PARAM_UNIPRO_VER
- INTERESTING_INTERRUPTS
- INTERFACE
- INTERFACE_A
- INTERFACE_ANALOG_RGB
- INTERFACE_B
- INTERFACE_BNC
- INTERFACE_C
- INTERFACE_CONTROL
- INTERFACE_CONTROL_ADDR
- INTERFACE_D
- INTERFACE_DATA
- INTERFACE_DFP
- INTERFACE_DFP_HIGH
- INTERFACE_DFP_LOW
- INTERFACE_DVP0
- INTERFACE_DVP1
- INTERFACE_ERROR
- INTERFACE_FLAGS
- INTERFACE_INFO
- INTERFACE_LVDS0
- INTERFACE_LVDS0LVDS1
- INTERFACE_LVDS1
- INTERFACE_MASK
- INTERFACE_MODE_10G_KR
- INTERFACE_MODE_40G_KR4
- INTERFACE_MODE_AGL
- INTERFACE_MODE_DISABLED
- INTERFACE_MODE_GMII
- INTERFACE_MODE_ILK
- INTERFACE_MODE_LOOP
- INTERFACE_MODE_MIXED
- INTERFACE_MODE_NPI
- INTERFACE_MODE_PCIE
- INTERFACE_MODE_PICMG
- INTERFACE_MODE_QSGMII
- INTERFACE_MODE_RGMII
- INTERFACE_MODE_RXAUI
- INTERFACE_MODE_SATA_1P5
- INTERFACE_MODE_SATA_3P0
- INTERFACE_MODE_SGMII
- INTERFACE_MODE_SPI
- INTERFACE_MODE_SRIO
- INTERFACE_MODE_USBSS
- INTERFACE_MODE_XAUI
- INTERFACE_MODE_XFI
- INTERFACE_MODE_XLAUI
- INTERFACE_NONE
- INTERFACE_RJ48C
- INTERFACE_SHIFT
- INTERFACE_TMDS
- INTERFERENCE_DATA_AVAILABLE
- INTERLACE
- INTERLACED
- INTERLACE_AUTO
- INTERLACE_BIT
- INTERLACE_CNTL
- INTERLACE_DISABLE
- INTERLACE_DTCT_WIN
- INTERLACE_ENABLE
- INTERLACE_FMT_DET
- INTERLACE_OFF
- INTERLACE_ON
- INTERLACE_SOURCE_INTERLEAVE
- INTERLACE_SOURCE_PROGRESSIVE
- INTERLACE_SOURCE_STACK
- INTERLACE_START
- INTERLACE_STATUS
- INTERLAN_8390_BASE
- INTERLAN_8390_MEM
- INTERLEAVED_RGB_FMT
- INTERLEAVED_RGB_FMT_TILED
- INTERLEAVED_YUV_FMT
- INTERLEAVE_BOTH
- INTERLEAVE_DIS
- INTERLEAVE_EN
- INTERLEAVE_INTERNAL
- INTERLEAVE_NONE
- INTERLEAVE_SAME
- INTERLEAVING_240
- INTERLEAVING_720
- INTERLEAVING_AUTO
- INTERLEAVING_NONE
- INTERLOCK
- INTERLOCK_OPEN
- INTERM0_IN
- INTERM0_OUT
- INTERM1_IN
- INTERM1_OUT
- INTERM2_IN
- INTERM2_OUT
- INTERM3_IN
- INTERM3_OUT
- INTERM4_IN
- INTERM4_OUT
- INTERM5_IN
- INTERM5_OUT
- INTERM6_IN
- INTERM6_OUT
- INTERMEDIATE_C_GOOD
- INTERMEDIATE_GOOD
- INTERM_CCM_XFR
- INTERNAL
- INTERNAL_ABORT_TIMEOUT
- INTERNAL_ARB_ENABLE_BIT
- INTERNAL_CHIP_DM
- INTERNAL_CHIP_EF
- INTERNAL_CHIP_FI
- INTERNAL_CHIP_FR
- INTERNAL_CHIP_FT
- INTERNAL_CHIP_FW
- INTERNAL_CHIP_RAP_ERM
- INTERNAL_CHIP_RAP_ERMx
- INTERNAL_CHIP_RAP_MASK
- INTERNAL_CHIP_RAP_NRM
- INTERNAL_CHIP_RAP_RR
- INTERNAL_CHIP_SD
- INTERNAL_CHIP_WE
- INTERNAL_CLOCK_4020_BITS
- INTERNAL_CMD
- INTERNAL_CMDS_COUNT
- INTERNAL_CMND
- INTERNAL_DATAPATH_16
- INTERNAL_DATAPATH_32
- INTERNAL_DATAPATH_8
- INTERNAL_DATAPATH_SIZE
- INTERNAL_DEBMSG
- INTERNAL_DRIVE
- INTERNAL_EPHY_ID
- INTERNAL_ERRMSG
- INTERNAL_ERROR
- INTERNAL_INFMSG
- INTERNAL_INSERT_TO_L
- INTERNAL_INSERT_TO_R
- INTERNAL_INSERT_TO_S
- INTERNAL_LOOPBACK
- INTERNAL_LOOPBACK_MASK
- INTERNAL_LOOP_BACK
- INTERNAL_MEM_RX_OFFSET
- INTERNAL_MEM_SIZE
- INTERNAL_MGMT_PKT
- INTERNAL_NODE
- INTERNAL_POISON_MASK__IntPoisonMask_MASK
- INTERNAL_POISON_MASK__IntPoisonMask__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_0_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_0__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_1_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_1__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_2_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_2__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_3_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_3__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_4_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_4__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_5_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_5__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_6_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_6__SHIFT
- INTERNAL_POISON_STATUS__IntPoisonStatus_7_MASK
- INTERNAL_POISON_STATUS__IntPoisonStatus_7__SHIFT
- INTERNAL_QUARTZ
- INTERNAL_RAM
- INTERNAL_READY
- INTERNAL_REGS_MASK
- INTERNAL_REG_CURRENT
- INTERNAL_REV_RAVEN_A0
- INTERNAL_RST
- INTERNAL_SCSIIO_CMDS_COUNT
- INTERNAL_SHIFT_FROM_L_TO_S
- INTERNAL_SHIFT_FROM_R_TO_S
- INTERNAL_SHIFT_FROM_S_TO_L
- INTERNAL_SHIFT_FROM_S_TO_R
- INTERNAL_WAIT_STATES
- INTERNAL_WRNMSG
- INTERNATIONAL_MODE
- INTERNETWORK
- INTERNETWORKV6
- INTERNODE_CACHE_BYTES
- INTERNODE_CACHE_SHIFT
- INTERN_H
- INTERN_WAIT
- INTERP
- INTERPOLATOR_CLOCK_GATE_DISABLE
- INTERP_EAR
- INTERP_HPHL
- INTERP_HPHR
- INTERP_LO1
- INTERP_LO2
- INTERP_LO3
- INTERP_LO4
- INTERP_ONE_PRIM_PER_ROW
- INTERP_SPKR1
- INTERP_SPKR2
- INTERRSTATE_REG
- INTERRUPT
- INTERRUPTS
- INTERRUPTS_ENABLED
- INTERRUPT_0
- INTERRUPT_1
- INTERRUPT_2
- INTERRUPT_3
- INTERRUPT_4
- INTERRUPT_5
- INTERRUPT_ACK
- INTERRUPT_AFE
- INTERRUPT_AFTER_TERMINAL_COUNT
- INTERRUPT_AND_WINDOW_STATUS
- INTERRUPT_AUDIO
- INTERRUPT_BASE
- INTERRUPT_BIT_DISCONNECT
- INTERRUPT_BIT_RX
- INTERRUPT_BIT_TX
- INTERRUPT_BUFSIZE
- INTERRUPT_CAUSE_EXTERNAL
- INTERRUPT_CAUSE_SOFTWARE
- INTERRUPT_CAUSE_TIMER
- INTERRUPT_CNTL
- INTERRUPT_CNTL2
- INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR_MASK
- INTERRUPT_CNTL2_IND__IH_DUMMY_RD_ADDR__SHIFT
- INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK
- INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK
- INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT
- INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN_MASK
- INTERRUPT_CNTL_IND__BIF_RB_REQ_NONSNOOP_EN__SHIFT
- INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN_MASK
- INTERRUPT_CNTL_IND__GEN_GPIO_INT_EN__SHIFT
- INTERRUPT_CNTL_IND__GEN_IH_INT_EN_MASK
- INTERRUPT_CNTL_IND__GEN_IH_INT_EN__SHIFT
- INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN_MASK
- INTERRUPT_CNTL_IND__IH_DUMMY_RD_EN__SHIFT
- INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE_MASK
- INTERRUPT_CNTL_IND__IH_DUMMY_RD_OVERRIDE__SHIFT
- INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR_MASK
- INTERRUPT_CNTL_IND__IH_INTR_DLY_CNTR__SHIFT
- INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN_MASK
- INTERRUPT_CNTL_IND__IH_REQ_NONSNOOP_EN__SHIFT
- INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT_MASK
- INTERRUPT_CNTL_IND__SELECT_INT_GPIO_OUTPUT__SHIFT
- INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK
- INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT
- INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK
- INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK
- INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT
- INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK
- INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT
- INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK
- INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT
- INTERRUPT_CNTL__GEN_GPIO_INT_EN_MASK
- INTERRUPT_CNTL__GEN_GPIO_INT_EN__SHIFT
- INTERRUPT_CNTL__GEN_IH_INT_EN_MASK
- INTERRUPT_CNTL__GEN_IH_INT_EN__MASK
- INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT
- INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK
- INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK
- INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT
- INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK
- INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK
- INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT
- INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK
- INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK
- INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT
- INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK
- INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK
- INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT
- INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT_MASK
- INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT
- INTERRUPT_COALESCE_NUMBER_MAX
- INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS
- INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS
- INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX
- INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN
- INTERRUPT_COALESCE_TIMEOUT_MAX_US
- INTERRUPT_CONTEXT_NUMBER
- INTERRUPT_CONTROL
- INTERRUPT_CONTROL_REG
- INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK
- INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT
- INTERRUPT_DDC
- INTERRUPT_DONE
- INTERRUPT_EDGE_LEVEL_REG
- INTERRUPT_ENABLE
- INTERRUPT_ENABLE_MASK
- INTERRUPT_ENABLE_OFF
- INTERRUPT_ENABLE_REGISTER
- INTERRUPT_EN_0
- INTERRUPT_EN_1
- INTERRUPT_EN_2
- INTERRUPT_EN_3
- INTERRUPT_EN_REG
- INTERRUPT_EVENT_CLEAR
- INTERRUPT_EVENT_SET
- INTERRUPT_HDCP
- INTERRUPT_HIGH_IRQ_CONTEXT
- INTERRUPT_ID_BITS_ITS
- INTERRUPT_ID_BITS_SPIS
- INTERRUPT_INFO
- INTERRUPT_INTERVAL
- INTERRUPT_LINE
- INTERRUPT_LINE_ASSERTED
- INTERRUPT_LINE_NOT_ASSERTED
- INTERRUPT_LINE__INTERRUPT_LINE_MASK
- INTERRUPT_LINE__INTERRUPT_LINE__MASK
- INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- INTERRUPT_LOW_IRQ_CONTEXT
- INTERRUPT_MASK
- INTERRUPT_MASK_ALL_VER_10
- INTERRUPT_MASK_ALL_VER_11
- INTERRUPT_MASK_ALL_VER_21
- INTERRUPT_MASK_CLEAR
- INTERRUPT_MASK_DISCONNECT
- INTERRUPT_MASK_OFF
- INTERRUPT_MASK_RW_VER_10
- INTERRUPT_MASK_RX
- INTERRUPT_MASK_SET
- INTERRUPT_MASK_TX
- INTERRUPT_MODE
- INTERRUPT_MSG_FORMAT_LEN
- INTERRUPT_NEXT_BUFFER
- INTERRUPT_PIN
- INTERRUPT_PIN__INTERRUPT_PIN_MASK
- INTERRUPT_PIN__INTERRUPT_PIN__MASK
- INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- INTERRUPT_POLARITY_BOTH
- INTERRUPT_POLARITY_DEFAULT
- INTERRUPT_POLARITY_HIGH
- INTERRUPT_POLARITY_LOW
- INTERRUPT_POLARITY_REG
- INTERRUPT_QUEUE_HDR_ADDR
- INTERRUPT_RATE
- INTERRUPT_REG
- INTERRUPT_REGISTER_ACCESSES
- INTERRUPT_RETURN
- INTERRUPT_SEL
- INTERRUPT_SEL_2
- INTERRUPT_SERVICE_GEN_SW_INT
- INTERRUPT_SERVICE_GET_STATUS
- INTERRUPT_SERVICE_PARAMETER_V2
- INTERRUPT_SOURCE
- INTERRUPT_STATUS
- INTERRUPT_STATUS_REG
- INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__HPD_HIGH
- INTERRUPT_STATUS__INT_TRIGGER
- INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK
- INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT
- INTERRUPT_STS_OFF
- INTERRUPT_SUS
- INTERRUPT_THRES
- INTERRUPT_TO_KERNEL
- INTERRUPT_TRAMPOLINE
- INTERRUPT_TRANSFER
- INTERRUPT_UNKNOWN
- INTERSECT_WINDOW_A_B
- INTERSECT_WINDOW_A_NOT_B
- INTERSECT_WINDOW_NOT_A_B
- INTERSECT_WINDOW_NOT_A_NOT_B
- INTERSIL_12H_MODE
- INTERSIL_24H_MODE
- INTERSIL_FREQ_1M
- INTERSIL_FREQ_2M
- INTERSIL_FREQ_32K
- INTERSIL_FREQ_4M
- INTERSIL_HZ_100_MASK
- INTERSIL_INT_DISABLE
- INTERSIL_INT_ENABLE
- INTERSIL_MODE_NORMAL
- INTERSIL_MODE_TEST
- INTERSIL_RF
- INTERSIL_RUN
- INTERSIL_STOP
- INTERVAL
- INTERVALS
- INTERVAL_0_833_TO_US
- INTERVAL_0_833_US
- INTERVAL_1_28_TO_US
- INTERVAL_1_28_US
- INTERVAL_1_33_TO_US
- INTERVAL_1_33_US
- INTERVAL_COUNT_REG
- INTERVAL_HIGH
- INTERVAL_LOW
- INTERVAL_SHIFT
- INTERVAL_STROBE_REG
- INTERVAL_TIME
- INTERVAL_TIME_DEFAULT
- INTERVAL_TREE_DEFINE
- INTERWAVE_DRIVER
- INTERWAVE_PNP_DRIVER
- INTER_PACKET
- INTEVT
- INTE_ADCBUFENABLE
- INTE_ADLIBENABLE
- INTE_AI
- INTE_A_MIDIRXENABLE2
- INTE_A_MIDITXENABLE2
- INTE_CAP_0_HALF_LOOP
- INTE_CAP_0_LOOP
- INTE_CDSPDIFENABLE
- INTE_CH_0_HALF_LOOP
- INTE_CH_0_LOOP
- INTE_EFXBUFENABLE
- INTE_FORCEINT
- INTE_FXDSPENABLE
- INTE_GPI
- INTE_GPSPDIFENABLE
- INTE_I2C_DAC
- INTE_I2C_EEPROM
- INTE_INTERVALTIMERENB
- INTE_MASTERDMAENABLE
- INTE_MASTERPICENABLE
- INTE_MICBUFENABLE
- INTE_MIDIRXENABLE
- INTE_MIDITXENABLE
- INTE_MIDI_RX_A
- INTE_MIDI_RX_B
- INTE_MIDI_TX_A
- INTE_MIDI_TX_B
- INTE_MPUENABLE
- INTE_MRHANDENABLE
- INTE_MUTEENABLE
- INTE_PCI
- INTE_PCIERRORENABLE
- INTE_SAMPLERATETRACKER
- INTE_SCU_IPC_REGISTER_READ
- INTE_SCU_IPC_REGISTER_UPDATE
- INTE_SCU_IPC_REGISTER_WRITE
- INTE_SLAVEDMAENABLE
- INTE_SLAVEPICENABLE
- INTE_SPDIF_IN_USER
- INTE_SPDIF_OUT_FRAME
- INTE_SPDIF_OUT_USER
- INTE_SPDIF_STATUS
- INTE_SPI
- INTE_SRC_LOCKED
- INTE_TIMER1
- INTE_TIMER2
- INTE_VIRTUALMPU_300
- INTE_VIRTUALMPU_310
- INTE_VIRTUALMPU_320
- INTE_VIRTUALMPU_330
- INTE_VIRTUALMPU_MASK
- INTE_VIRTUALSB_220
- INTE_VIRTUALSB_240
- INTE_VIRTUALSB_260
- INTE_VIRTUALSB_280
- INTE_VIRTUALSB_MASK
- INTE_VOLDECRENABLE
- INTE_VOLINCRENABLE
- INTE_VSBENABLE
- INTEl_WIDI_WK_CID
- INTF
- INTF0
- INTF1
- INTF2
- INTF3
- INTFBPADDR
- INTFBVADDR
- INTFC_CACHE_VALID
- INTFC_CTLR_READY
- INTFC_ERASED
- INTFC_FLASH_READY
- INTFC_FLASH_STATUS
- INTFC_OOB_VALID
- INTFLAG
- INTF_0
- INTF_1
- INTF_2
- INTF_3
- INTF_4
- INTF_5
- INTF_6
- INTF_ACTIVE_HCTL
- INTF_ACTIVE_V_END_F0
- INTF_ACTIVE_V_END_F1
- INTF_ACTIVE_V_START_F0
- INTF_ACTIVE_V_START_F1
- INTF_BLK
- INTF_BORDER_COLOR
- INTF_CAPTURE
- INTF_CFG
- INTF_CONFIG
- INTF_COUNT
- INTF_DEFLICKER_CONFIG
- INTF_DEFLICKER_STRNG_COEFF
- INTF_DEFLICKER_WEAK_COEFF
- INTF_DISABLED
- INTF_DISPLAY_HCTL
- INTF_DISPLAY_V_END_F0
- INTF_DISPLAY_V_END_F1
- INTF_DISPLAY_V_START_F0
- INTF_DISPLAY_V_START_F1
- INTF_DP
- INTF_DSI
- INTF_DSI_CMD
- INTF_DSI_CMD_MODE_TRIGGER_EN
- INTF_DSI_VIDEO
- INTF_EBI2_TV
- INTF_EDP
- INTF_FRAME_COUNT
- INTF_FRAME_LINE_COUNT_EN
- INTF_HDMI
- INTF_HDR_ALIGN
- INTF_HEADER_LEN
- INTF_HSYNC_CTL
- INTF_HSYNC_SKEW
- INTF_IE_STAT
- INTF_INIT
- INTF_INREQUEST
- INTF_INTR_CLEAR
- INTF_INTR_EN
- INTF_INTR_STATUS
- INTF_INT_CLR
- INTF_INT_EN
- INTF_INT_STAT
- INTF_LCDC
- INTF_LCDC_DTV
- INTF_LINE_COUNT
- INTF_MAX
- INTF_MIDI
- INTF_MODE
- INTF_MODE_CMD
- INTF_MODE_LEN
- INTF_MODE_MAX
- INTF_MODE_NONE
- INTF_MODE_POS
- INTF_MODE_RGMII_1000
- INTF_MODE_RGMII_10_100
- INTF_MODE_VIDEO
- INTF_MODE_WB_BLOCK
- INTF_MODE_WB_LINE
- INTF_NONE
- INTF_NOTIFY
- INTF_PANEL_FORMAT
- INTF_PCI
- INTF_PCIE
- INTF_PLAYBACK
- INTF_POLARITY_CTL
- INTF_PROG_FETCH_START
- INTF_PROG_ROT_START
- INTF_REQUEST
- INTF_SDIO
- INTF_SEL0_PCIE
- INTF_SEL1_MINICARD
- INTF_SEL2_RSV
- INTF_SEL3_RSV
- INTF_STAT
- INTF_SW_RESET_MASK
- INTF_TEST_CTL
- INTF_TIMING_ENGINE_EN
- INTF_TPG_BLK_WHITE_PATTERN_FRAMES
- INTF_TPG_COMPONENT_LIMITS
- INTF_TPG_ENABLE
- INTF_TPG_INITIAL_VALUE
- INTF_TPG_MAIN_CONTROL
- INTF_TPG_RECTANGLE
- INTF_TPG_RGB_MAPPING
- INTF_TPG_VIDEO_CONFIG
- INTF_TP_COLOR0
- INTF_TP_COLOR1
- INTF_TYPE_MAX
- INTF_UNDERFLOW_COLOR
- INTF_USB
- INTF_VE_STAT
- INTF_VIRTUAL
- INTF_VSYNC_PERIOD_F0
- INTF_VSYNC_PERIOD_F1
- INTF_VSYNC_PULSE_WIDTH_F0
- INTF_VSYNC_PULSE_WIDTH_F1
- INTF_WB
- INTF_eDP
- INTG
- INTGR0_INTGC
- INTGR0_INTGD
- INTGR1_INTGC
- INTH_R5F_CLEAR_OFFSET
- INTH_R5F_MASK_CLEAR_OFFSET
- INTH_R5F_MASK_SET_OFFSET
- INTH_R5F_STATUS_OFFSET
- INTICI0
- INTICI1
- INTICI2
- INTICI3
- INTICI4
- INTICI5
- INTICI6
- INTICI7
- INTIE
- INTL
- INTLEVEL
- INTLEVEL2_VECTOR_VADDR
- INTLEVEL3_VECTOR_VADDR
- INTLEVEL4_VECTOR_VADDR
- INTLEVEL5_VECTOR_VADDR
- INTLEVEL6_VECTOR_VADDR
- INTLEVEL7_VECTOR_VADDR
- INTLINE
- INTLINEREG
- INTLOG10X100
- INTLV_IN_DEPTH
- INTLV_NATIVE
- INTLV_UNKNOWN
- INTL_EN
- INTL_HBAR_CTRL
- INTL_STAND
- INTM
- INTMAK_ALLMASK
- INTMAK_HIRQM
- INTMAK_IRM
- INTMAK_NONEMASK
- INTMAK_TSIRQM
- INTMAP_ECCDED_INDEX
- INTMAP_ECCSEC_INDEX
- INTMASK
- INTMASK1_ADC1K_MASK
- INTMASK1_ADC1K_SHIFT
- INTMASK1_ADCERR_MASK
- INTMASK1_ADCERR_SHIFT
- INTMASK1_ADCLOW_MASK
- INTMASK1_ADCLOW_SHIFT
- INTMASK1_ADC_MASK
- INTMASK1_ADC_SHIFT
- INTMASK2_CHGDETRUN_MASK
- INTMASK2_CHGDETRUN_SHIFT
- INTMASK2_CHGTYP_MASK
- INTMASK2_CHGTYP_SHIFT
- INTMASK2_DCDTMR_MASK
- INTMASK2_DCDTMR_SHIFT
- INTMASK2_DXOVP_MASK
- INTMASK2_DXOVP_SHIFT
- INTMASK2_VBVOLT_MASK
- INTMASK2_VBVOLT_SHIFT
- INTMASK2_VIDRM_MASK
- INTMASK2_VIDRM_SHIFT
- INTMR0_INTMC
- INTMR0_INTMD
- INTMR1_INTMC
- INTMR2_INTMCIS
- INTMSK
- INTMSK0
- INTMSK1
- INTMSK2
- INTMSKCLR2
- INTMSR
- INTMSR0_GET_INTMSC
- INTMSR0_GET_INTMSD
- INTMS_OVERFLOW
- INTMS_SYMBRCV
- INTMS_TIMEOUT
- INTMTU
- INTMUX
- INTN
- INTPENDJUNK_CLRBIT
- INTPINREG
- INTPLT_ON_OFF
- INTPL_CUR_10
- INTPL_CUR_20
- INTPL_CUR_30
- INTPL_CUR_40
- INTPND_RES
- INTPND_SET
- INTPND_UNC
- INTPRI
- INTPRINTK
- INTR
- INTR1_MASK
- INTR1_MONITOR_DETECT
- INTR1_STAT
- INTR2_CLEAR
- INTR2_EN
- INTR2_STATUS
- INTRA_REFRESH_MBS_MAX
- INTRBID
- INTRBIM
- INTREG
- INTREN
- INTREPID_NEOVI_PID
- INTREPID_VALUECAN_PID
- INTREPID_VID
- INTRFLAGS
- INTRL2_0_BELOW_HYST_THRESH
- INTRL2_0_BRCM_MATCH_TAG
- INTRL2_0_DESC_ALLOC_ERR
- INTRL2_0_FREE_LIST_EMPTY
- INTRL2_0_GISB_ERR
- INTRL2_0_MPD
- INTRL2_0_OVER_MAX_THRESH
- INTRL2_0_RBUF_OVFLOW
- INTRL2_0_RDMA_MBDONE
- INTRL2_0_TBUF_UNDFLOW
- INTRL2_0_TDMA_MBDONE_MASK
- INTRL2_0_TDMA_MBDONE_SHIFT
- INTRL2_0_TX_RING_FULL
- INTRL2_0_UNEXP_PKTSIZE_ACK
- INTRL2_CPU_CLEAR
- INTRL2_CPU_MASK_CLEAR
- INTRL2_CPU_MASK_SET
- INTRL2_CPU_MASK_STATUS
- INTRL2_CPU_SET
- INTRL2_CPU_STAT
- INTRL2_CPU_STATUS
- INTRL_ENA
- INTRL_REG_TO_USEC
- INTRL_USEC_TO_REG
- INTRMASK
- INTRMSK_EIHE
- INTRMSK_EIIC
- INTRMSK_EIMTC
- INTRMSK_EIRC
- INTRMSK_EIRS
- INTRMSK_EITA
- INTRMSK_EIWC
- INTRMSK_EIWS
- INTRNAMSIZ
- INTRN_MASK_CLEAR_ALL
- INTRN_MASK_RX_EN
- INTRQ_CPU_MONDO_HEAD
- INTRQ_CPU_MONDO_TAIL
- INTRQ_DEVICE_MONDO_HEAD
- INTRQ_DEVICE_MONDO_TAIL
- INTRQ_NONRESUM_MONDO_HEAD
- INTRQ_NONRESUM_MONDO_TAIL
- INTRQ_RESUM_MONDO_HEAD
- INTRQ_RESUM_MONDO_TAIL
- INTRS_ALLOW_MSIX_VECTOR0
- INTRS_CRITICAL_OP_IN_PROGRESS
- INTRS_HRRQ_VALID
- INTRS_IOARCB_TRANSFER_FAILED
- INTRS_IOARRIN_LOST
- INTRS_IOA_PROCESSOR_ERROR
- INTRS_IOA_UNIT_CHECK
- INTRS_IO_DEBUG_ACK
- INTRS_NO_HRRQ_FOR_CMD_RESPONSE
- INTRS_OPERATIONAL_STATUS
- INTRS_SYSTEM_BUS_MMIO_ERROR
- INTRS_TRANSITION_TO_OPERATIONAL
- INTRUSION_ALARM_BASE
- INTRVL_CNTR
- INTR_AHB_DONE_EN
- INTR_ALL
- INTR_ALWAYS
- INTR_ASYNC_EVENT
- INTR_ATIO_QUE_UPDATE
- INTR_ATIO_QUE_UPDATE_27XX
- INTR_ATIO_RSP_QUE_UPDATE
- INTR_AUTO
- INTR_AUTO_C
- INTR_AUTO_P
- INTR_AUTO_PI
- INTR_BASE_BIT_SHIFT
- INTR_BDIS_ACON
- INTR_BIT
- INTR_BSPI_LR_FULLNESS_REACHED_MASK
- INTR_BSPI_LR_IMPATIENT_MASK
- INTR_BSPI_LR_OVERREAD_MASK
- INTR_BSPI_LR_SESSION_ABORTED_MASK
- INTR_BSPI_LR_SESSION_DONE_MASK
- INTR_BUSOWNER_UPDATE_STAT
- INTR_BUS_SERV
- INTR_CCC_UPDATED_STAT
- INTR_CHAR
- INTR_CLEAR
- INTR_CLR_OFS
- INTR_CLR_SHIFT
- INTR_CMD_QUEUE_READY_STAT
- INTR_COAL
- INTR_COAL_COUNT_BITS
- INTR_COAL_COUNT_MASK
- INTR_COAL_COUNT_SHIFT
- INTR_COAL_LATENCY_MASK
- INTR_COAL_LATENCY_UNITS_NS
- INTR_CONTROL_REGISTER
- INTR_COUNT
- INTR_CR_INT
- INTR_DBG
- INTR_DEFSLV_STAT
- INTR_DISABLE
- INTR_DISCONNECT
- INTR_DM_HI
- INTR_DONE
- INTR_DP_HI
- INTR_DYN_ADDR_ASSGN_STAT
- INTR_EN
- INTR_ENABLE
- INTR_ENABLE_MASK
- INTR_ENABLE_REG
- INTR_EN_EI
- INTR_EN_EN
- INTR_EN_IHD
- INTR_EN_IHD_MASK
- INTR_EN_INTR_MASK
- INTR_EN_MAC0
- INTR_EN_MAC1
- INTR_EN_MAC2
- INTR_EN_MAC3
- INTR_EN_MAC4
- INTR_EN_MAC5
- INTR_EN_MAC6
- INTR_EN_MAC7
- INTR_EN_MAC8
- INTR_EN_MAC9
- INTR_EN_PAGE_MASK
- INTR_EN_PCI
- INTR_EN_QMI
- INTR_EN_REG
- INTR_EN_REV0
- INTR_EN_REV1
- INTR_EN_REV2
- INTR_EN_REV3
- INTR_EN_TMR
- INTR_EN_TYPE_DISABLE
- INTR_EN_TYPE_ENABLE
- INTR_EN_TYPE_MASK
- INTR_EN_TYPE_READ
- INTR_ERROR_MASK
- INTR_FLAG_IRQ_REQUESTED
- INTR_FLAG_MSIX_ENABLED
- INTR_FLAG_MSI_ENABLED
- INTR_FORCE
- INTR_FOR_CAPTURE
- INTR_FOR_PLAYBACK
- INTR_IBI_THLD_STAT
- INTR_IBI_UPDATED_STAT
- INTR_IDLE
- INTR_IDX_CTL_START
- INTR_IDX_MAX
- INTR_IDX_PINGPONG
- INTR_IDX_RDPTR
- INTR_IDX_UNDERRUN
- INTR_IDX_VSYNC
- INTR_ID_FLOAT
- INTR_ID_GND
- INTR_IFCLR
- INTR_IFSET
- INTR_ILL_CMD
- INTR_INDEX_NOT_ASSIGNED
- INTR_INFO_DELIVER_CODE_MASK
- INTR_INFO_INTR_TYPE_MASK
- INTR_INFO_RESVD_BITS_MASK
- INTR_INFO_UNBLOCK_NMI
- INTR_INFO_VALID_MASK
- INTR_INFO_VECTOR_MASK
- INTR_IN_BUFFER_SIZE
- INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK
- INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK
- INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT
- INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK
- INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT
- INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK
- INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK
- INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT
- INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK
- INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT
- INTR_LINK
- INTR_LINKCH
- INTR_LOC
- INTR_MAC_CTRL_STATUS
- INTR_MAGICRCV
- INTR_MASK
- INTR_MASK_HL0
- INTR_MASK_HL1
- INTR_MASK_LH0
- INTR_MASK_LH1
- INTR_MASK_LINK_IRQS
- INTR_MASK_LSC
- INTR_MASK_MC
- INTR_MASK_PI
- INTR_MASK_REG
- INTR_MASK_SE
- INTR_MASTER_MASK
- INTR_MBOX_SIZE
- INTR_MB_FAILED
- INTR_MB_SUCCESS
- INTR_MIF_STATUS
- INTR_MODE
- INTR_MODE_LEGACY
- INTR_MODE_MSI
- INTR_MODE_MSIX
- INTR_MSIX_TYPE
- INTR_MSPI_DONE_MASK
- INTR_MSPI_HALTED_MASK
- INTR_NAME_MAX_SZ
- INTR_NEVER
- INTR_NEXT_COMMAND
- INTR_OFF
- INTR_OFFSET
- INTR_ON
- INTR_PAUSERCV
- INTR_PCCRX0
- INTR_PCCRX0TO
- INTR_PCCRX1
- INTR_PCCRX1TO
- INTR_PCCRX2
- INTR_PCCRX2TO
- INTR_PCCRX3
- INTR_PCCRX3TO
- INTR_PCCTX
- INTR_PCCTXTO
- INTR_PCI_ERROR_STATUS
- INTR_PCS_STATUS
- INTR_PENDING
- INTR_PORT
- INTR_PROCESSING
- INTR_READ_REQ_RECV_STAT
- INTR_REMAP
- INTR_REMAP_PAGE_ORDER
- INTR_REMAP_TABLE_ENTRIES
- INTR_REMAP_TABLE_REG_SIZE
- INTR_REMAP_TABLE_REG_SIZE_MASK
- INTR_RESELECTED
- INTR_RESET
- INTR_RESET_REG
- INTR_RESP_READY_STAT
- INTR_ROM_MB_FAILED
- INTR_ROM_MB_SUCCESS
- INTR_RSP_QUE_UPDATE
- INTR_RSP_QUE_UPDATE_83XX
- INTR_RX0
- INTR_RX0EMP
- INTR_RX1
- INTR_RX1EMP
- INTR_RX2
- INTR_RX2EMP
- INTR_RX3
- INTR_RX3EMP
- INTR_RX_BUF_AE
- INTR_RX_BUF_AE_1
- INTR_RX_BUF_UNAVAIL
- INTR_RX_BUF_UNAVAIL_1
- INTR_RX_COMP_AF
- INTR_RX_COMP_AF_ALT
- INTR_RX_COMP_FULL
- INTR_RX_COMP_FULL_ALT
- INTR_RX_DONE
- INTR_RX_DONE_ALT
- INTR_RX_LEN_MISMATCH
- INTR_RX_MAC_STATUS
- INTR_RX_TAG_ERROR
- INTR_RX_THLD_STAT
- INTR_SCHEME_PERPORT
- INTR_SELECT
- INTR_SEL_ATN
- INTR_SESS_VLD
- INTR_SET_OFS
- INTR_SIGNAL_EN
- INTR_SPREAD_BLOCKING_DURATION
- INTR_SPREAD_BLOCKING_DURATION_KFC
- INTR_SPREAD_EN
- INTR_SPREAD_ENABLE_KFC
- INTR_SPREAD_USE_STANDBYWFI
- INTR_SPREAD_USE_STANDBYWFI_KFC
- INTR_STATES_SEG_NUM
- INTR_STATUS
- INTR_STATUS_ALT_INTX_EN
- INTR_STATUS_EN
- INTR_STATUS_FUNC1
- INTR_STATUS_FUNC2
- INTR_STATUS_PAGE_VALID
- INTR_STATUS_REG
- INTR_STATUS_REGISTER
- INTR_STAT_OFS
- INTR_STAT_REG
- INTR_SUMMARY
- INTR_SWAP
- INTR_SWINTR
- INTR_SYSRTC_CN
- INTR_TMINTR
- INTR_TRANSFER_ABORT_STAT
- INTR_TRANSFER_ERR_STAT
- INTR_TRIG_CMD
- INTR_TRIG_DEBUG_ACK
- INTR_TRIG_EVENT_ACK
- INTR_TRIG_RX_PROC0
- INTR_TRIG_RX_PROC1
- INTR_TRIG_STATE_CHANGED
- INTR_TRIG_TX_PROC0
- INTR_TRIG_TX_PROC1
- INTR_TX0
- INTR_TX1
- INTR_TX2
- INTR_TX3
- INTR_TX4
- INTR_TX5
- INTR_TX6
- INTR_TX7
- INTR_TX_ALL
- INTR_TX_COMP_3_MASK
- INTR_TX_COMP_3_SHIFT
- INTR_TX_DONE
- INTR_TX_INTME
- INTR_TX_MAC_STATUS
- INTR_TX_TAG_ERROR
- INTR_TX_THLD_STAT
- INTR_TYPE_EXT_INTR
- INTR_TYPE_HARD_EXCEPTION
- INTR_TYPE_NMI_INTR
- INTR_TYPE_OTHER_EVENT
- INTR_TYPE_PRIV_SW_EXCEPTION
- INTR_TYPE_RESERVED
- INTR_TYPE_SOFT_EXCEPTION
- INTR_TYPE_SOFT_INTR
- INTR_VALID
- INTR_VBUS_VLD
- INTR_WAKE
- INTR_WAKERCV
- INTR_WORK
- INTR__DMA_CMD_COMP
- INTR__ECC_ERR
- INTR__ECC_TRANSACTION_DONE
- INTR__ECC_UNCOR_ERR
- INTR__ERASED_PAGE
- INTR__ERASE_COMP
- INTR__ERASE_FAIL
- INTR__INT_ACT
- INTR__LOAD_COMP
- INTR__LOCKED_BLK
- INTR__PAGE_XFER_INC
- INTR__PIPE_CMD_ERR
- INTR__PIPE_CPYBCK_CMD_COMP
- INTR__PROGRAM_COMP
- INTR__PROGRAM_FAIL
- INTR__RST_COMP
- INTR__TIME_OUT
- INTR__UNSUP_CMD
- INTSCR_INT1_ENABLE
- INTSCR_INT1_STATUS
- INTSEL
- INTSR0_GET_INTSC
- INTSR0_GET_INTSD
- INTSRC_ANEG_COMPLETE
- INTSRC_ANEG_LP_ACK
- INTSRC_ANEG_PR
- INTSRC_FLAG
- INTSRC_LINK_DOWN
- INTSRC_MASK
- INTSRC_PARALLEL_FAULT
- INTSRC_REMOTE_FAULT
- INTSTAT
- INTSTAT0
- INTSTAT1
- INTSTAT2
- INTSTAT3
- INTSTATE_INT_ULPS_END
- INTSTATE_INT_ULPS_START
- INTSTATE_REG
- INTSTATUS
- INTSTATUSMASK
- INTSTRLEN
- INTSTS0
- INTSTS0_MAGIC
- INTSTS1
- INTSTS1_MAGIC
- INTSTS2
- INTSTS_G
- INTSTS_HIRQ
- INTSTS_IR
- INTSTS_TSIRQ
- INTSYSSTATUS
- INTS_CASE
- INTS_CASE_COMMON
- INTS_DATA
- INTS_DISABLE
- INTS_ERR_CASE
- INTS_RESTORE_HARD
- INTTESTR
- INTTOEXT_BASE
- INTTOEXT_BASE_ILK
- INTTOEXT_MAP0_MASK
- INTTOEXT_MAP0_SHIFT
- INTTOEXT_MAP1_MASK
- INTTOEXT_MAP1_SHIFT
- INTTOEXT_MAP2_MASK
- INTTOEXT_MAP2_SHIFT
- INTTOEXT_MAP3_MASK
- INTTOEXT_MAP3_SHIFT
- INTT_MASK
- INTUOS
- INTUOS3
- INTUOS3L
- INTUOS3S
- INTUOS4
- INTUOS4L
- INTUOS4S
- INTUOS4WL
- INTUOS5
- INTUOS5L
- INTUOS5S
- INTUOSHT
- INTUOSHT2
- INTUOSHT3_BT
- INTUOSP2S_BT
- INTUOSP2_BT
- INTUOSPL
- INTUOSPM
- INTUOSPS
- INTVAL
- INTVR
- INTXCLRPERR_F
- INTXCLRPERR_S
- INTXCLRPERR_V
- INTX_CONFIG_SET
- INTX_MASK
- INTX_SHIFT
- INT_0
- INT_1
- INT_1510_COM_SPI_RO
- INT_1510_DSP_MAILBOX1
- INT_1510_DSP_MAILBOX2
- INT_1510_DSP_MMU
- INT_1510_IH2_IRQ
- INT_1510_LB_MMU
- INT_1510_LOCAL_BUS
- INT_1510_RES12
- INT_1510_RES18
- INT_1510_RES2
- INT_1510_SPI_RX
- INT_1510_SPI_TX
- INT_1610_CF
- INT_1610_DMA_CH10
- INT_1610_DMA_CH11
- INT_1610_DMA_CH12
- INT_1610_DMA_CH13
- INT_1610_DMA_CH14
- INT_1610_DMA_CH15
- INT_1610_DMA_CH6
- INT_1610_DMA_CH7
- INT_1610_DMA_CH8
- INT_1610_DMA_CH9
- INT_1610_DSP_MAILBOX1
- INT_1610_DSP_MAILBOX2
- INT_1610_DSP_MMU
- INT_1610_FAC
- INT_1610_GPIO_BANK2
- INT_1610_GPIO_BANK3
- INT_1610_GPIO_BANK4
- INT_1610_GPTIMER1
- INT_1610_GPTIMER2
- INT_1610_GPTIMER3
- INT_1610_GPTIMER4
- INT_1610_GPTIMER5
- INT_1610_GPTIMER6
- INT_1610_GPTIMER7
- INT_1610_GPTIMER8
- INT_1610_IH2_FIQ
- INT_1610_IH2_IRQ
- INT_1610_LCD_LINE
- INT_1610_MMC2
- INT_1610_McBSP2RX_OF
- INT_1610_McBSP2_RX
- INT_1610_McBSP2_TX
- INT_1610_NAND
- INT_1610_SHA1MD5
- INT_1610_SPI
- INT_1610_SSR_FIFO_0
- INT_1610_STI
- INT_1610_STI_WAKEUP
- INT_1610_SoSSI
- INT_1610_SoSSI_MATCH
- INT_1610_USB_HHC_2
- INT_1610_USB_OTG
- INT_1610_WAKE_UP_REQ
- INT_1WIRE
- INT_2
- INT_3
- INT_4
- INT_5
- INT_7XX_CAMERA_IF
- INT_7XX_CFCD
- INT_7XX_CFIREQ
- INT_7XX_DBB_RF_EN
- INT_7XX_DMA_CH10
- INT_7XX_DMA_CH11
- INT_7XX_DMA_CH12
- INT_7XX_DMA_CH13
- INT_7XX_DMA_CH14
- INT_7XX_DMA_CH15
- INT_7XX_DMA_CH6
- INT_7XX_DMA_CH7
- INT_7XX_DMA_CH8
- INT_7XX_DMA_CH9
- INT_7XX_DUAL_MODE_TIMER
- INT_7XX_EAC
- INT_7XX_GPIO_BANK1
- INT_7XX_GPIO_BANK2
- INT_7XX_GPIO_BANK3
- INT_7XX_GPIO_BANK4
- INT_7XX_GPIO_BANK5
- INT_7XX_GPIO_BANK6
- INT_7XX_GSM_PROTECT
- INT_7XX_HDQ_1WIRE
- INT_7XX_HW_ERRORS
- INT_7XX_I2C
- INT_7XX_ICR
- INT_7XX_IH2_FIQ
- INT_7XX_IH2_IRQ
- INT_7XX_LCD_LINE
- INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF
- INT_7XX_LLPC_OE_FALLING
- INT_7XX_LLPC_OE_RISING
- INT_7XX_LLPC_VSYNC
- INT_7XX_MCSI
- INT_7XX_MMC_SDIO
- INT_7XX_MPUIO
- INT_7XX_MPUIO_KEYPAD
- INT_7XX_MPU_EXT_NIRQ
- INT_7XX_McBSP1RX
- INT_7XX_McBSP1RX_OF
- INT_7XX_McBSP1TX
- INT_7XX_McBSP2RX
- INT_7XX_McBSP2RX_OVF
- INT_7XX_McBSP2TX
- INT_7XX_NAND
- INT_7XX_NFIQ_PWR_FAIL
- INT_7XX_PCC
- INT_7XX_RNG
- INT_7XX_RNG_IDLE
- INT_7XX_SHA1_MD5
- INT_7XX_SMC_CD
- INT_7XX_SMC_IREQ
- INT_7XX_SPGIO_WR
- INT_7XX_SPI_100K_1
- INT_7XX_SPI_100K_2
- INT_7XX_SYREN_SPI
- INT_7XX_TIMER3
- INT_7XX_TIMER32K
- INT_7XX_UART_MODEM_1
- INT_7XX_UART_MODEM_IRDA_2
- INT_7XX_UPLD
- INT_7XX_USB_GENI
- INT_7XX_USB_HHC_1
- INT_7XX_USB_HHC_2
- INT_7XX_USB_ISO
- INT_7XX_USB_NON_ISO
- INT_7XX_USB_OTG
- INT_7XX_VLYNQ
- INT_7XX_WAKE_UP_REQ
- INT_7XX_uWireRX
- INT_7XX_uWireTX
- INT_A1IE
- INT_A2IE
- INT_AAL0
- INT_AAL0_STR
- INT_ABORT
- INT_ACK
- INT_ACK_MASK
- INT_ACT
- INT_ACTIVE_HIGH
- INT_ACTIVE_LOW
- INT_ADD
- INT_ADDI
- INT_ADDIU
- INT_ADDR_ACK_ERR
- INT_ADDU
- INT_AGGR_COUNTER_AND_TIMER_RESET
- INT_AGGR_COUNTER_THLD_VAL
- INT_AGGR_COUNTER_THRESHOLD_MASK
- INT_AGGR_DEF_TO
- INT_AGGR_ENABLE
- INT_AGGR_PARAM_WRITE
- INT_AGGR_STATUS_BIT
- INT_AGGR_TIMEOUT_VAL
- INT_AGGR_TIMEOUT_VAL_MASK
- INT_ALL
- INT_ALL_Rx
- INT_ALL_STATUS
- INT_ANCHOR
- INT_ASSERTED
- INT_ATTACH
- INT_BABBLE
- INT_BDIS_ACON
- INT_BITS
- INT_BIT_1588_
- INT_BIT_ALL_OTHER_
- INT_BIT_ALL_RX_
- INT_BIT_ALL_TX_
- INT_BIT_DMA_RX_
- INT_BIT_DMA_TX_
- INT_BIT_ERR
- INT_BIT_MAS_
- INT_BIT_SW_GP_
- INT_BLK_MQ_DEBUGFS_H
- INT_BLK_MQ_H
- INT_BLK_MQ_TAG_H
- INT_BLOCK_HC
- INT_BLOCK_IGU
- INT_BLOCK_MODE_BW_COMP
- INT_BLOCK_MODE_NORMAL
- INT_BRIDGE_PRIV
- INT_BRIDGE_PUB
- INT_BSIE
- INT_BT_MCSI1RX
- INT_BT_MCSI1TX
- INT_BUFRE
- INT_BUFREN
- INT_BUFVIO
- INT_BUFWEN
- INT_BUF_FILL
- INT_BUF_READ_EN
- INT_BUF_WRITE_EN
- INT_BULK_SEL
- INT_BUSSERVICE
- INT_BUS_ABORT
- INT_BUS_ABORT_EN
- INT_BUS_INACTIVE
- INT_BUTTON_CANCEL
- INT_BUTTON_IGNORE
- INT_BUTTON_PRESS
- INT_BUTTON_RELEASE
- INT_CABLE_PULL
- INT_CAMERA
- INT_CANCEL
- INT_CAPS
- INT_CARD_INSERTION_EN
- INT_CARD_INSERTION_WKP_EN
- INT_CARD_REMOVAL_EN
- INT_CARD_REMOVAL_WKP_EN
- INT_CAUSE
- INT_CAUSE_EXT
- INT_CBR0
- INT_CCS
- INT_CCSDE
- INT_CCSRCV
- INT_CCSTO
- INT_CC_EN
- INT_CFG
- INT_CFG_INT_DEAS_
- INT_CFG_INT_DEAS_CLR_
- INT_CFG_INT_DEAS_MASK
- INT_CFG_INT_DEAS_STS_
- INT_CFG_IRQ_EN_
- INT_CFG_IRQ_INT_
- INT_CFG_IRQ_POL_
- INT_CFG_IRQ_TYPE_
- INT_CFG_NEXT_BCN
- INT_CFG_NEXT_BCN_EN
- INT_CHECKSUM
- INT_CLASS_CRIT
- INT_CLASS_DBG
- INT_CLASS_MC
- INT_CLASS_NONCRIT
- INT_CLEAR
- INT_CLEAR_A
- INT_CLEAR_B
- INT_CLEAR_C
- INT_CLEAR_D
- INT_CLEAR_MASK_R1
- INT_CLEAR_MASK_R2
- INT_CLEAR_MASK_R3
- INT_CLEAR_MASK_R4
- INT_CLEAR_R1
- INT_CLEAR_R2
- INT_CLEAR_R3
- INT_CLEAR_R4
- INT_CLK
- INT_CLK_MULT_ENABLE
- INT_CLK_MULT_RESET
- INT_CLK_SELECT
- INT_CLK_SRC_NOT_PCI
- INT_CLR_OVERFLOW
- INT_CLR_RCV
- INT_CLR_RCVTIMEOUT
- INT_CLR_TIMEOUT
- INT_CLS
- INT_CMD12CRE
- INT_CMD12DRE
- INT_CMD12RBE
- INT_CMDDONE
- INT_CMDVIO
- INT_CMD_COMPL
- INT_CMD_COMPLETE
- INT_CMD_ERR
- INT_CNEW
- INT_CNT
- INT_COAL_EN
- INT_COAL_MULT
- INT_CODEC_SCRATCH0
- INT_CODEC_SCRATCH1
- INT_COL_CNT
- INT_COMMON
- INT_COMPLETION
- INT_CP_REQUEST
- INT_CRCSTO
- INT_CRC_ERR
- INT_CRERR_CNT
- INT_CRSPE
- INT_CR_INT
- INT_CSR
- INT_CTL
- INT_CTLR_DTS
- INT_CTLR_DTSE
- INT_CTLR_PERR
- INT_CTLR_SERR
- INT_CTL_GPT_INT_EN_
- INT_CTL_MBERR_INT_EN_
- INT_CTL_PHY_INT_EN_
- INT_CTL_SBERR_INT_EN_
- INT_CTL_SW_INT_EN_
- INT_CTL_WAKE_INT_EN_
- INT_CTRL1
- INT_CTRL_FLAG
- INT_CTRL_PKT_DONE
- INT_DAT0_EN
- INT_DBG_LATCH_R1
- INT_DBG_LATCH_R2
- INT_DBG_LATCH_R3
- INT_DBG_LATCH_R4
- INT_DCDC1
- INT_DCDC2
- INT_DCDC3
- INT_DEAS_TIME
- INT_DEBOUNCE_MSEC
- INT_DEFERRED_FIQ
- INT_DEF_LB_ECHO_CMD
- INT_DEF_LB_LOOPBACK_CMD
- INT_DEF_MASK
- INT_DETACH
- INT_DEVWIDE
- INT_DIS
- INT_DISABLE
- INT_DISABLED
- INT_DISABLE_ALL
- INT_DISC
- INT_DISCONNECT
- INT_DMASHUT
- INT_DMA_CH0_6
- INT_DMA_CH1_7
- INT_DMA_CH2_8
- INT_DMA_CH3
- INT_DMA_CH4
- INT_DMA_CH5
- INT_DMA_END_EN
- INT_DMA_END_STATUS
- INT_DMA_FINISH
- INT_DMA_LCD
- INT_DM_HI
- INT_DONE
- INT_DOWN
- INT_DPLL_LOCKED
- INT_DP_HI
- INT_DSP_MMU_ABORT
- INT_DTIM_NOTIFY
- INT_DTIM_NOTIFY_EN
- INT_DTRANE
- INT_ECC_EN
- INT_ECC_ERR
- INT_EMPTY_QUEUE
- INT_EN
- INT_ENABLE
- INT_ENABLED
- INT_ENABLE_2
- INT_ENABLE_ADDR
- INT_ENABLE_FW_MB
- INT_ENABLE_MASK_ATOMIC
- INT_ENABLE_MASK_AUTOMATIC
- INT_ENABLE_MASK_INACTIVE
- INT_ENABLE_MASK_RAW
- INT_ENABLE_MASK_WAITSTOP
- INT_ENABLE_REG
- INT_ENABLE_REG_OFF
- INT_ENA_ABS_MSK
- INT_ENA_F20_MSK
- INT_ENA_REL_MSK
- INT_ENA_REQ_MSK
- INT_ENDPOINT0
- INT_END_CMD_RES_EN
- INT_ENP_DP_INT
- INT_ENP_EEE_RX_LPI_INT
- INT_ENP_EEE_START_TX_LPI_INT
- INT_ENP_EEE_STOP_TX_LPI_INT
- INT_ENP_MAC_ERR_INT
- INT_ENP_MAC_RTO_
- INT_ENP_PHY_INT
- INT_ENP_PHY_INT_
- INT_ENP_RDFO_INT
- INT_ENP_RXDF_
- INT_ENP_RX_DIS_INT
- INT_ENP_RX_FIFO_DATA_INT
- INT_ENP_RX_STOP_
- INT_ENP_TDFO_
- INT_ENP_TDFO_INT
- INT_ENP_TDFU_
- INT_ENP_TDFU_INT
- INT_ENP_TXE_
- INT_ENP_TXE_INT
- INT_ENP_TX_DIS_INT
- INT_ENP_TX_STOP_
- INT_ENP_UTX_FP_INT
- INT_EN_CLR
- INT_EN_CMD
- INT_EN_GPIO0_INT_
- INT_EN_GPIO1_INT_
- INT_EN_GPIO2_INT_
- INT_EN_GPT_INT_EN_
- INT_EN_MASK
- INT_EN_PHY_INT_EN_
- INT_EN_PME_INT_EN_
- INT_EN_POS
- INT_EN_RDFL_EN_
- INT_EN_RDFO_EN_
- INT_EN_REG_MASK
- INT_EN_RSFF_EN_
- INT_EN_RSFL_EN_
- INT_EN_RWT_EN_
- INT_EN_RXDFH_INT_EN_
- INT_EN_RXDF_EN_
- INT_EN_RXD_INT_EN_
- INT_EN_RXE_EN_
- INT_EN_RXSTOP_INT_EN_
- INT_EN_SET
- INT_EN_SW_INT_EN_
- INT_EN_TDFA_EN_
- INT_EN_TDFO_EN_
- INT_EN_TDFU_EN_
- INT_EN_TIOC_INT_EN_
- INT_EN_TSFF_EN_
- INT_EN_TSFL_EN_
- INT_EN_TXE_EN_
- INT_EN_TXSO_EN_
- INT_EN_TXSTOP_INT_EN_
- INT_EP0
- INT_EP1DATASET
- INT_EP1NAK
- INT_EP2DATASET
- INT_EP2NAK
- INT_EP3DATASET
- INT_EP3NAK
- INT_EPHY
- INT_EP_CTL
- INT_EP_CTL_GPIOS_
- INT_EP_CTL_GPIOX_EN
- INT_EP_CTL_INTEP_
- INT_EP_CTL_INTEP_ON
- INT_EP_CTL_MACROTO_EN
- INT_EP_CTL_MAC_ERR_EN
- INT_EP_CTL_MAC_RTO_
- INT_EP_CTL_PHY_EN_
- INT_EP_CTL_PHY_INT_
- INT_EP_CTL_RDFO_EN
- INT_EP_CTL_RXDF_
- INT_EP_CTL_RX_DIS_EN
- INT_EP_CTL_RX_FIFO_
- INT_EP_CTL_RX_FIFO_EN
- INT_EP_CTL_RX_STOP_
- INT_EP_CTL_TDFO_
- INT_EP_CTL_TDFO_EN
- INT_EP_CTL_TDFU_
- INT_EP_CTL_TDFU_EN
- INT_EP_CTL_TXE_
- INT_EP_CTL_TXE_EN
- INT_EP_CTL_TX_DIS_EN
- INT_EP_CTL_TX_STOP_
- INT_EP_DP
- INT_EP_DP_INT_EN_
- INT_EP_EEE_RX_LPI
- INT_EP_EEE_TX_LPI_START
- INT_EP_EEE_TX_LPI_STOP
- INT_EP_GPIO_0
- INT_EP_GPIO_1
- INT_EP_GPIO_10
- INT_EP_GPIO_11
- INT_EP_GPIO_2
- INT_EP_GPIO_3
- INT_EP_GPIO_4
- INT_EP_GPIO_5
- INT_EP_GPIO_6
- INT_EP_GPIO_7
- INT_EP_GPIO_8
- INT_EP_GPIO_9
- INT_EP_GPIO_EN_MASK_
- INT_EP_INTEP
- INT_EP_INTEP_ON_
- INT_EP_MAC_ERR
- INT_EP_MAC_ERR_EN_
- INT_EP_MAC_RESET_TIMEOUT
- INT_EP_OTP_WR_DONE
- INT_EP_PHY
- INT_EP_PHY_INT_EN_
- INT_EP_RDFO
- INT_EP_RDFO_EN_
- INT_EP_RX_DIS
- INT_EP_RX_DIS_EN_
- INT_EP_TDFO
- INT_EP_TDFO_EN_
- INT_EP_TDFU
- INT_EP_TDFU_EN_
- INT_EP_TXE
- INT_EP_TXE_EN_
- INT_EP_TX_DIS
- INT_EP_TX_DIS_EN_
- INT_EP_USB_STATUS
- INT_EP_UTX
- INT_EP_UTX_FP_EN_
- INT_EPnNAK
- INT_EPxDATASET
- INT_ERR
- INT_ERR1
- INT_ERR1_MASK
- INT_ERR1_RAW
- INT_ERR2
- INT_ERR2_MASK
- INT_ERR2_RAW
- INT_ERROR
- INT_ERROR_EN
- INT_ERROR_STATUS
- INT_ERR_ACK_OFFSET
- INT_ERR_MASK_OFFSET
- INT_ERR_Rx
- INT_ERR_STAT_OFFSET
- INT_ERR_STS
- INT_EVERY_N_CELLS
- INT_EXACT
- INT_EXCEPTION
- INT_EXT
- INT_EXT_LINK_PHY
- INT_EXT_STATUS
- INT_EXT_TX
- INT_FATAL_ERROR
- INT_FATAL_ERRORS
- INT_FBUS
- INT_FDSR
- INT_FIELD_EN
- INT_FIELD_STATUS
- INT_FIFO
- INT_FIFO_EMPTY
- INT_FIFO_EMPTYING
- INT_FIFO_FILLING
- INT_FIFO_FULL
- INT_FIFO_FULL_FILLING
- INT_FIFO_O
- INT_FIFO_SIZE
- INT_FIFO_U
- INT_FIQ
- INT_FIXPT
- INT_FLAGS
- INT_FLAGS_2_EDID_BLK_RD
- INT_FTRGT
- INT_FW_UPGRADE
- INT_GAUGE_32K
- INT_GCR_A
- INT_GCR_B
- INT_GEN_CNT
- INT_GLOBAL_EN
- INT_GP0_LCNT
- INT_GP1_LCNT
- INT_GPHY
- INT_GPIN
- INT_GPIO_BANK1
- INT_GPIO_H
- INT_GPIO_LC
- INT_HANDLER
- INT_HDCP
- INT_HEADER
- INT_HOST
- INT_HPD
- INT_HSYNC_EN
- INT_HSYNC_STATUS
- INT_H_SIZE
- INT_I2C
- INT_IDLE_DETECT
- INT_ID_FLOAT
- INT_ID_GND
- INT_IFM_ERR
- INT_ILP
- INT_INACTIVITY
- INT_INCOMINGCMV
- INT_INDEP_MASK
- INT_INDEX_ADDR
- INT_INF_DONE
- INT_INPUT_CLEAR
- INT_INST_INT
- INT_INVALID
- INT_INVERT
- INT_INV_BIT
- INT_IN_EP
- INT_KEYBOARD
- INT_KEYPAD
- INT_KVM_HANDLER
- INT_L
- INT_LBASIZE_ALIGNMENT
- INT_LCD
- INT_LCD_CTRL
- INT_LDO1
- INT_LDO2
- INT_LED
- INT_LEVEL
- INT_LIMIT
- INT_LNR_SUSP
- INT_LOADSWAPPAGE
- INT_LOCD
- INT_LOCK
- INT_LOSS_LOCK
- INT_LRD_DIS
- INT_LSS_POWER_ERR
- INT_LS_BF_VS
- INT_LWR_DIS
- INT_MADIM
- INT_MAP
- INT_MASK
- INT_MASK_A
- INT_MASK_ADDR
- INT_MASK_ALL
- INT_MASK_ALL_DISABLED
- INT_MASK_ALL_ENABLED
- INT_MASK_B
- INT_MASK_BUSY
- INT_MASK_C
- INT_MASK_CRT_VSYNC
- INT_MASK_CSR
- INT_MASK_CSR_AC0_DMA_DONE
- INT_MASK_CSR_AC1_DMA_DONE
- INT_MASK_CSR_AC2_DMA_DONE
- INT_MASK_CSR_AC3_DMA_DONE
- INT_MASK_CSR_AUTO_WAKEUP
- INT_MASK_CSR_BEACON_DONE
- INT_MASK_CSR_ENABLE_MITIGATION
- INT_MASK_CSR_GPTIMER
- INT_MASK_CSR_HCCA_DMA_DONE
- INT_MASK_CSR_MCU_COMMAND
- INT_MASK_CSR_MGMT_DMA_DONE
- INT_MASK_CSR_MITIGATION_PERIOD
- INT_MASK_CSR_PRE_TBTT
- INT_MASK_CSR_RXDELAYINT
- INT_MASK_CSR_RXDONE
- INT_MASK_CSR_RXTX_COHERENT
- INT_MASK_CSR_RX_COHERENT
- INT_MASK_CSR_RX_DONE
- INT_MASK_CSR_TBTT
- INT_MASK_CSR_TXDELAYINT
- INT_MASK_CSR_TXDONE
- INT_MASK_CSR_TX_ABORT_DONE
- INT_MASK_CSR_TX_COHERENT
- INT_MASK_CSR_TX_FIFO_STATUS
- INT_MASK_D
- INT_MASK_DE
- INT_MASK_DEF
- INT_MASK_DISABLE
- INT_MASK_DMA
- INT_MASK_DMA1
- INT_MASK_ENABLE
- INT_MASK_ENABLE_NO_FLOW
- INT_MASK_EXT
- INT_MASK_FW_MB
- INT_MASK_GPIO25
- INT_MASK_GPIO26
- INT_MASK_GPIO27
- INT_MASK_GPIO28
- INT_MASK_GPIO29
- INT_MASK_GPIO30
- INT_MASK_GPIO31
- INT_MASK_I2C
- INT_MASK_INITAIAL_VAL
- INT_MASK_OFFSET
- INT_MASK_P
- INT_MASK_PANEL_VSYNC
- INT_MASK_PCI
- INT_MASK_PM
- INT_MASK_PWM
- INT_MASK_R1
- INT_MASK_R2
- INT_MASK_R3
- INT_MASK_R4
- INT_MASK_RX
- INT_MASK_RXC
- INT_MASK_RXE
- INT_MASK_RXF
- INT_MASK_SET
- INT_MASK_SSP0
- INT_MASK_SSP1
- INT_MASK_TX
- INT_MASK_TXC
- INT_MASK_TXE
- INT_MASK_TXF
- INT_MASK_VGA_VSYNC
- INT_MASK_ZVPORT0_VSYNC
- INT_MASK_ZVPORT1_VSYNC
- INT_MASK_mskDSSIM
- INT_MASK_mskH0IM
- INT_MASK_mskH1IM
- INT_MASK_mskH2IM
- INT_MASK_mskH3IM
- INT_MASK_mskH4IM
- INT_MASK_mskH5IM
- INT_MASK_mskIDIVZE
- INT_MASK_mskSIM
- INT_MASK_offDSSIM
- INT_MASK_offH0IM
- INT_MASK_offH1IM
- INT_MASK_offH2IM
- INT_MASK_offH3IM
- INT_MASK_offH4IM
- INT_MASK_offH5IM
- INT_MASK_offIDIVZE
- INT_MASK_offSIM
- INT_MASTER_HALTED
- INT_MAX
- INT_MDI
- INT_MEM_DATA
- INT_MEM_DATA_M
- INT_MEM_STICK
- INT_MEM_WRITE_EN
- INT_MERGED_MASK
- INT_MIN
- INT_MISMATCH
- INT_MMC
- INT_MODE
- INT_MODULE_PARM
- INT_MOD_CFG0
- INT_MOD_CFG1
- INT_MOD_CFG2
- INT_MOD_CFG3
- INT_MOD_CFG4
- INT_MOD_CFG5
- INT_MOD_CFG6
- INT_MOD_CFG7
- INT_MOD_DEFAULT_CNT
- INT_MOD_MAP0
- INT_MOD_MAP1
- INT_MOD_MAP2
- INT_MOD_MAX_CNT
- INT_MOD_MIN_CNT
- INT_MON_CYCCNT
- INT_MON_CYCCNT__VALUE
- INT_MPUIO
- INT_MSK2_GPIO0_F_IT_MSK_MASK
- INT_MSK2_GPIO0_F_IT_MSK_SHIFT
- INT_MSK2_GPIO0_R_IT_MSK_MASK
- INT_MSK2_GPIO0_R_IT_MSK_SHIFT
- INT_MSK2_GPIO1_F_IT_MSK_MASK
- INT_MSK2_GPIO1_F_IT_MSK_SHIFT
- INT_MSK2_GPIO1_R_IT_MSK_MASK
- INT_MSK2_GPIO1_R_IT_MSK_SHIFT
- INT_MSK2_GPIO2_F_IT_MSK_MASK
- INT_MSK2_GPIO2_F_IT_MSK_SHIFT
- INT_MSK2_GPIO2_R_IT_MSK_MASK
- INT_MSK2_GPIO2_R_IT_MSK_SHIFT
- INT_MSK2_GPIO3_F_IT_MSK_MASK
- INT_MSK2_GPIO3_F_IT_MSK_SHIFT
- INT_MSK2_GPIO3_R_IT_MSK_MASK
- INT_MSK2_GPIO3_R_IT_MSK_SHIFT
- INT_MSK3_GPIO4_F_IT_MSK_MASK
- INT_MSK3_GPIO4_F_IT_MSK_SHIFT
- INT_MSK3_GPIO4_R_IT_MSK_MASK
- INT_MSK3_GPIO4_R_IT_MSK_SHIFT
- INT_MSK3_GPIO5_F_IT_MSK_MASK
- INT_MSK3_GPIO5_F_IT_MSK_SHIFT
- INT_MSK3_GPIO5_R_IT_MSK_MASK
- INT_MSK3_GPIO5_R_IT_MSK_SHIFT
- INT_MSK3_PWRDN_IT_MSK_MASK
- INT_MSK3_PWRDN_IT_MSK_SHIFT
- INT_MSK3_VMBCH2_H_IT_MSK_MASK
- INT_MSK3_VMBCH2_H_IT_MSK_SHIFT
- INT_MSK3_VMBCH2_L_IT_MSK_MASK
- INT_MSK3_VMBCH2_L_IT_MSK_SHIFT
- INT_MSK3_WTCHDG_IT_MSK_MASK
- INT_MSK3_WTCHDG_IT_MSK_SHIFT
- INT_MSK_HOTDIE_IT_MSK_MASK
- INT_MSK_HOTDIE_IT_MSK_SHIFT
- INT_MSK_PWRHOLD_F_IT_MSK_MASK
- INT_MSK_PWRHOLD_F_IT_MSK_SHIFT
- INT_MSK_PWRHOLD_R_IT_MSK_MASK
- INT_MSK_PWRHOLD_R_IT_MSK_SHIFT
- INT_MSK_PWRON_IT_MSK_MASK
- INT_MSK_PWRON_IT_MSK_SHIFT
- INT_MSK_PWRON_LP_IT_MSK_MASK
- INT_MSK_PWRON_LP_IT_MSK_SHIFT
- INT_MSK_RTC_ALARM_IT_MSK_MASK
- INT_MSK_RTC_ALARM_IT_MSK_SHIFT
- INT_MSK_RTC_PERIOD_IT_MSK_MASK
- INT_MSK_RTC_PERIOD_IT_MSK_SHIFT
- INT_MSK_VMBHI_IT_MSK_MASK
- INT_MSK_VMBHI_IT_MSK_SHIFT
- INT_MSR
- INT_MST
- INT_MSTRDEND
- INT_MSTWREND
- INT_MSTWRSET
- INT_MSTWRTMOUT
- INT_MUTEX
- INT_McBSP1RX
- INT_McBSP1TX
- INT_McBSP3RX
- INT_McBSP3TX
- INT_NCTS_DONE
- INT_NOINIT
- INT_NONE
- INT_NO_C6
- INT_NO_MASK
- INT_NUM_EXTRA_START
- INT_NUM_IM0_IRL0
- INT_NUM_IM1_IRL0
- INT_NUM_IM2_IRL0
- INT_NUM_IM3_IRL0
- INT_NUM_IM4_IRL0
- INT_NUM_IM_OFFSET
- INT_NUM_IRQ0
- INT_OCERR
- INT_OFLOW
- INT_OIE
- INT_ON_CMD_COMPLETE
- INT_ON_DATA_LENGTH_MISMATCH
- INT_ON_ERROR
- INT_ON_FATAL_ERR
- INT_ON_PHYRDY_CHG
- INT_ON_SIGNATURE_UPDATE
- INT_ON_SINGL_DEVICE_ERR
- INT_ON_SNOTIFY_UPDATE
- INT_OS_TIMER
- INT_OUT_COUNT
- INT_OUT_COUNT_TO_US
- INT_OUT_DIAG
- INT_OUT_EP
- INT_OUT_INT_OUT
- INT_OUT_MAX_TICKS
- INT_OUT_MIN_TICKS
- INT_OUT_MODE
- INT_OUT_MODE_0
- INT_OUT_MODE_1
- INT_OUT_MODE_1PULSE
- INT_OUT_MODE_PULSES
- INT_OUT_MODE_SQW
- INT_OUT_NS_PER_TICK
- INT_OUT_TICKS_PER_PULSE
- INT_OUT_US_TO_COUNT
- INT_PABORT
- INT_PAGE_MAP
- INT_PARAM_ADDR
- INT_PARERR
- INT_PCIPARITY
- INT_PCI_MSI_NR
- INT_PEND0_BASELVL
- INT_PEND1_BASELVL
- INT_PENDING_MSK
- INT_PENDING_R1
- INT_PENDING_R2
- INT_PENDING_R3
- INT_PENDING_R4
- INT_PENDING_REG
- INT_PEND_mskCIPL
- INT_PEND_mskH0I
- INT_PEND_mskH1I
- INT_PEND_mskH2I
- INT_PEND_mskH3I
- INT_PEND_mskH4I
- INT_PEND_mskH5I
- INT_PEND_mskSWI
- INT_PEND_offCIPL
- INT_PEND_offH0I
- INT_PEND_offH1I
- INT_PEND_offH2I
- INT_PEND_offH3I
- INT_PEND_offH4I
- INT_PEND_offH5I
- INT_PEND_offSWI
- INT_PHY
- INT_PHY_ADDR
- INT_PI
- INT_PIE
- INT_PING
- INT_PIN_ENABLE_OFFSET
- INT_PME
- INT_POL0
- INT_POL1
- INT_PORT_1
- INT_PORT_2
- INT_PORT_3
- INT_PORT_4
- INT_PORT_5
- INT_PORT_ALL
- INT_POWER_FAULT
- INT_POWER_FAULT_CLEAR
- INT_PPERR
- INT_PRESENCE_OFF
- INT_PRESENCE_ON
- INT_PROC_ENBL
- INT_PTD_OFFSET
- INT_PULSE
- INT_PWM1
- INT_PWM2
- INT_PWM3
- INT_PWRDETECT
- INT_QRX_FUL
- INT_QRX_OV
- INT_QUEUE
- INT_QUEUE_STOPPED
- INT_Q_AVAILABLE
- INT_Q_OVERFLOW
- INT_RBSYE
- INT_RBSYTO
- INT_RCV_COMPLETED
- INT_RCV_DISABLED
- INT_RCV_XMIT_SHUTDOWN
- INT_RDATERR
- INT_RDATTO
- INT_RDY_PIN
- INT_RDY_SR
- INT_RD_CLR_EN
- INT_READ_INDEX
- INT_READ_OP_EN
- INT_READ_SIZE
- INT_READ_STATUS
- INT_REG
- INT_REGS_MASK
- INT_REG_BREQ
- INT_REG_CED
- INT_REG_CMDNK
- INT_REG_ERR
- INT_REG_VAL
- INT_REL
- INT_REQ
- INT_REQ_STAT_REG
- INT_RESELECTED
- INT_RESERVED
- INT_RESPONSE
- INT_RETRIG_TIMER_MASK
- INT_RETRY_FAIL
- INT_RETRY_FAIL_EN
- INT_RETRY_TIME
- INT_RF_FULL
- INT_RF_OVERFLOW
- INT_RF_UNDERFLOW
- INT_RIDXERR
- INT_RIPERR
- INT_RISCI
- INT_RISCS_SHIFT
- INT_RISC_EN
- INT_ROTATOR
- INT_RSPERR
- INT_RSPTO
- INT_RSR
- INT_RTC_ALARM
- INT_RTC_TIMER
- INT_RTDX
- INT_RX
- INT_RXFIFO_FUL
- INT_RXFIFO_RESYNC
- INT_RXFIFO_UNOV
- INT_RXLOST_CNT
- INT_RX_0
- INT_RX_BUS_ERR
- INT_RX_COMPLETE
- INT_RX_COMPLETE_EN
- INT_RX_MASK
- INT_RX_NOT_EMPTY
- INT_RX_NOT_FULL
- INT_RX_OVERFLOW
- INT_RX_PKT
- INT_S
- INT_S0iX_MSG_ERR
- INT_SAS_SATA
- INT_SAVE_SRR_AND_JUMP
- INT_SCAM
- INT_SCERR
- INT_SCLK_LOW_TIMEOUT
- INT_SCRATCH
- INT_SCSIRESET
- INT_SC_SERDES_READ_REG
- INT_SC_SERDES_WRITE_REG
- INT_SDAT_LOW_TIMEOUT
- INT_SDIO_INT_WKP_EN
- INT_SDIO_IRQ_EN
- INT_SDMA_INT
- INT_SEGSHUT
- INT_SEL
- INT_SELECT
- INT_SELTIMEOUT
- INT_SERVICE
- INT_SESS_VLD
- INT_SET
- INT_SETUP
- INT_SET_MASK_R1
- INT_SET_MASK_R2
- INT_SET_MASK_R3
- INT_SET_MASK_R4
- INT_SIGNAL_CHANGE
- INT_SIGNAL_ENABLE
- INT_SIG_EN
- INT_SIZE
- INT_SLAVE_EVENT
- INT_SLL
- INT_SLLV
- INT_SLV
- INT_SLV_TMOMASK
- INT_SOF
- INT_SOFT_CLEAR
- INT_SOFT_SET
- INT_SOOL
- INT_SOSSI_MATCH
- INT_SOURCE
- INT_SOURCE_CSR
- INT_SOURCE_CSR_AC0_DMA_DONE
- INT_SOURCE_CSR_AC1_DMA_DONE
- INT_SOURCE_CSR_AC2_DMA_DONE
- INT_SOURCE_CSR_AC3_DMA_DONE
- INT_SOURCE_CSR_AUTO_WAKEUP
- INT_SOURCE_CSR_BEACON_DONE
- INT_SOURCE_CSR_GPTIMER
- INT_SOURCE_CSR_HCCA_DMA_DONE
- INT_SOURCE_CSR_MCU_COMMAND
- INT_SOURCE_CSR_MGMT_DMA_DONE
- INT_SOURCE_CSR_PRE_TBTT
- INT_SOURCE_CSR_RXDELAYINT
- INT_SOURCE_CSR_RXDONE
- INT_SOURCE_CSR_RXTX_COHERENT
- INT_SOURCE_CSR_RX_COHERENT
- INT_SOURCE_CSR_RX_DONE
- INT_SOURCE_CSR_TBTT
- INT_SOURCE_CSR_TXDELAYINT
- INT_SOURCE_CSR_TXDONE
- INT_SOURCE_CSR_TX_ABORT_DONE
- INT_SOURCE_CSR_TX_COHERENT
- INT_SOURCE_CSR_TX_FIFO_STATUS
- INT_SOURCE_REG_OFF
- INT_SPACE_MSK
- INT_SR
- INT_SRA
- INT_SRAV
- INT_SRC_R1
- INT_SRC_R2
- INT_SRC_R3
- INT_SRC_R4
- INT_SRL
- INT_SRLV
- INT_ST
- INT_STA
- INT_STAT
- INT_STATS
- INT_STATUS
- INT_STATUSNAK
- INT_STATUS_1
- INT_STATUS_2
- INT_STATUS_ADDR
- INT_STATUS_ALL
- INT_STATUS_ANY_ERR
- INT_STATUS_CRC_ERR
- INT_STATUS_CRT_VSYNC
- INT_STATUS_DE
- INT_STATUS_DMA0
- INT_STATUS_DMA1
- INT_STATUS_DMA_BOUNDARY
- INT_STATUS_DMA_TOUT
- INT_STATUS_ENABLE
- INT_STATUS_ENABLE_ADDRESS
- INT_STATUS_ENABLE_COUNTER
- INT_STATUS_ENABLE_COUNTER_LSB
- INT_STATUS_ENABLE_COUNTER_MASK
- INT_STATUS_ENABLE_COUNTER_S
- INT_STATUS_ENABLE_CPU
- INT_STATUS_ENABLE_CPU_LSB
- INT_STATUS_ENABLE_CPU_MASK
- INT_STATUS_ENABLE_CPU_S
- INT_STATUS_ENABLE_ERROR
- INT_STATUS_ENABLE_ERROR_LSB
- INT_STATUS_ENABLE_ERROR_MASK
- INT_STATUS_ENABLE_ERROR_S
- INT_STATUS_ENABLE_INT
- INT_STATUS_ENABLE_INT_S
- INT_STATUS_ENABLE_MBOX_DATA
- INT_STATUS_ENABLE_MBOX_DATA_LSB
- INT_STATUS_ENABLE_MBOX_DATA_MASK
- INT_STATUS_ENABLE_MBOX_DATA_S
- INT_STATUS_EOTPC
- INT_STATUS_EOTRAN
- INT_STATUS_FIFO_RRDY
- INT_STATUS_FIFO_WRDY
- INT_STATUS_GPIO25
- INT_STATUS_GPIO26
- INT_STATUS_GPIO27
- INT_STATUS_GPIO28
- INT_STATUS_GPIO29
- INT_STATUS_GPIO30
- INT_STATUS_GPIO31
- INT_STATUS_HSK_TO
- INT_STATUS_I2C
- INT_STATUS_MASK
- INT_STATUS_MEDIA_IN
- INT_STATUS_MEDIA_OUT
- INT_STATUS_NUM
- INT_STATUS_PANEL_VSYNC
- INT_STATUS_PCI
- INT_STATUS_PWM
- INT_STATUS_SSP0
- INT_STATUS_SSP1
- INT_STATUS_TIMER_TO
- INT_STATUS_TPC_ERR
- INT_STATUS_VGA_VSYNC
- INT_STATUS_ZVPORT0_VSYNC
- INT_STATUS_ZVPORT1_VSYNC
- INT_STAT_CAD_INT
- INT_STAT_DMAC_INT_
- INT_STAT_GPI_INT
- INT_STAT_GPT_INT_
- INT_STAT_K_INT
- INT_STAT_K_LCK_INT
- INT_STAT_MASK
- INT_STAT_MBERR_INT_
- INT_STAT_OVR_FLOW_INT
- INT_STAT_PHY_INT_
- INT_STAT_SBERR_INT_
- INT_STAT_SW_INT_
- INT_STAT_WAKE_INT_
- INT_STA_MASK
- INT_STOP_DETECTED
- INT_STROB
- INT_STS
- INT_STS2_GPIO0_F_IT_MASK
- INT_STS2_GPIO0_F_IT_SHIFT
- INT_STS2_GPIO0_R_IT_MASK
- INT_STS2_GPIO0_R_IT_SHIFT
- INT_STS2_GPIO1_F_IT_MASK
- INT_STS2_GPIO1_F_IT_SHIFT
- INT_STS2_GPIO1_R_IT_MASK
- INT_STS2_GPIO1_R_IT_SHIFT
- INT_STS2_GPIO2_F_IT_MASK
- INT_STS2_GPIO2_F_IT_SHIFT
- INT_STS2_GPIO2_R_IT_MASK
- INT_STS2_GPIO2_R_IT_SHIFT
- INT_STS2_GPIO3_F_IT_MASK
- INT_STS2_GPIO3_F_IT_SHIFT
- INT_STS2_GPIO3_R_IT_MASK
- INT_STS2_GPIO3_R_IT_SHIFT
- INT_STS3_GPIO4_F_IT_MASK
- INT_STS3_GPIO4_F_IT_SHIFT
- INT_STS3_GPIO4_R_IT_MASK
- INT_STS3_GPIO4_R_IT_SHIFT
- INT_STS3_GPIO5_F_IT_MASK
- INT_STS3_GPIO5_F_IT_SHIFT
- INT_STS3_GPIO5_R_IT_MASK
- INT_STS3_GPIO5_R_IT_SHIFT
- INT_STS3_PWRDN_IT_MASK
- INT_STS3_PWRDN_IT_SHIFT
- INT_STS3_VMBCH2_H_IT_MASK
- INT_STS3_VMBCH2_H_IT_SHIFT
- INT_STS3_VMBCH2_L_IT_MASK
- INT_STS3_VMBCH2_L_IT_SHIFT
- INT_STS3_WTCHDG_IT_MASK
- INT_STS3_WTCHDG_IT_SHIFT
- INT_STS_ALL
- INT_STS_CLEAR_ALL
- INT_STS_CLEAR_ALL_
- INT_STS_DP_INT_
- INT_STS_EEE_RX_LPI_
- INT_STS_EEE_RX_LPI_EN_
- INT_STS_EEE_TX_LPI_STOP_
- INT_STS_EEE_TX_LPI_STOP_EN_
- INT_STS_EEE_TX_LPI_STRT_
- INT_STS_EEE_TX_LPI_STRT_EN_
- INT_STS_EN
- INT_STS_GPIO0_
- INT_STS_GPIO0_INT_
- INT_STS_GPIO10_
- INT_STS_GPIO11_
- INT_STS_GPIO1_
- INT_STS_GPIO1_INT_
- INT_STS_GPIO2_
- INT_STS_GPIO2_INT_
- INT_STS_GPIO3_
- INT_STS_GPIO4_
- INT_STS_GPIO5_
- INT_STS_GPIO6_
- INT_STS_GPIO7_
- INT_STS_GPIO8_
- INT_STS_GPIO9_
- INT_STS_GPIOS
- INT_STS_GPIOS_
- INT_STS_GPIO_MASK_
- INT_STS_GPT_INT_
- INT_STS_HOTDIE_IT_MASK
- INT_STS_HOTDIE_IT_SHIFT
- INT_STS_MACRTO_INT
- INT_STS_MAC_ERR_
- INT_STS_MAC_ERR_INT
- INT_STS_MAC_RTO_
- INT_STS_OFFSET
- INT_STS_PENDING
- INT_STS_PHY_INT_
- INT_STS_PME_INT_
- INT_STS_PWRHOLD_F_IT_MASK
- INT_STS_PWRHOLD_F_IT_SHIFT
- INT_STS_PWRHOLD_R_IT_MASK
- INT_STS_PWRHOLD_R_IT_SHIFT
- INT_STS_PWRON_IT_MASK
- INT_STS_PWRON_IT_SHIFT
- INT_STS_PWRON_LP_IT_MASK
- INT_STS_PWRON_LP_IT_SHIFT
- INT_STS_R2C
- INT_STS_RDFL_
- INT_STS_RDFO_
- INT_STS_RDFO_INT
- INT_STS_RSFF_
- INT_STS_RSFL_
- INT_STS_RTC_ALARM_IT_MASK
- INT_STS_RTC_ALARM_IT_SHIFT
- INT_STS_RTC_PERIOD_IT_MASK
- INT_STS_RTC_PERIOD_IT_SHIFT
- INT_STS_RWT_
- INT_STS_RXDFH_INT_
- INT_STS_RXDF_
- INT_STS_RXDF_INT_
- INT_STS_RXD_INT_
- INT_STS_RXE_
- INT_STS_RXSTOP_INT_
- INT_STS_RX_DIS_
- INT_STS_RX_DIS_INT
- INT_STS_RX_STOP_
- INT_STS_SW_INT_
- INT_STS_TDFA_
- INT_STS_TDFO
- INT_STS_TDFO_
- INT_STS_TDFU
- INT_STS_TDFU_
- INT_STS_TSFF_
- INT_STS_TSFL_
- INT_STS_TXE_
- INT_STS_TXE_INT
- INT_STS_TXSO_
- INT_STS_TXSTOP_INT_
- INT_STS_TX_DIS_
- INT_STS_TX_DIS_INT
- INT_STS_TX_IOC_
- INT_STS_TX_STOP_
- INT_STS_UFX_FP_
- INT_STS_VMBHI_IT_MASK
- INT_STS_VMBHI_IT_SHIFT
- INT_SUB
- INT_SUBU
- INT_SUSPEND
- INT_SWITCH_CLOSE
- INT_SWITCH_OPEN
- INT_SYM_ERR
- INT_SYSERR
- INT_SYSERROR
- INT_TABORTBM
- INT_TABORTSENT
- INT_TC1
- INT_TC1_MASK
- INT_TC1_RAW
- INT_TC2
- INT_TC2_MASK
- INT_TC2_RAW
- INT_TEMP_HOT
- INT_TEMP_WARM
- INT_TEST
- INT_TF_EMPTY
- INT_TF_OVERFLOW
- INT_THRESH_HI
- INT_TICKS
- INT_TIMEOUTBM
- INT_TIMER1
- INT_TIMER2
- INT_TIMER3
- INT_TIMER_CFG
- INT_TIMER_CFG_GP_TIMER
- INT_TIMER_CFG_PRE_TBTT_TIMER
- INT_TIMER_EN
- INT_TIMER_EN_GP_TIMER
- INT_TIMER_EN_PRE_TBTT_TIMER
- INT_TIMING
- INT_TO
- INT_TO_FIXPT
- INT_TO_FP
- INT_TO_IRQ
- INT_TO_Q52
- INT_TRANSACTION_DONE
- INT_TRIGGER_ERR
- INT_TSR
- INT_TSRIE
- INT_TXFIFO_RESYNC
- INT_TXFIFO_UNOV
- INT_TXOK_CNT
- INT_TX_BUS_ERR
- INT_TX_COMPLETE
- INT_TX_COMPLETE_EN
- INT_TX_EM
- INT_TX_EMPTY
- INT_TX_END
- INT_TX_END_0
- INT_TX_FIFO_READY
- INT_TX_FIFO_READY_EN
- INT_TX_MASK
- INT_TX_NOT_FULL
- INT_TX_PKT
- INT_TX_UNDERRUN
- INT_TYPE
- INT_TYPEDEFS_H
- INT_TYPE_APIC
- INT_UART
- INT_UART1
- INT_UART2
- INT_UART3
- INT_UART_EN
- INT_UNDERFLOW_EN
- INT_UNDERFLOW_STA
- INT_UNDERRUN
- INT_UNDRUN
- INT_UNEXPECTED_START
- INT_UP
- INT_UQ_ERR
- INT_UQ_SYNC
- INT_URX_FUL
- INT_URX_OV
- INT_USBRESET
- INT_USB_ALARM
- INT_USB_HHC_1
- INT_USB_IRQ_GEN
- INT_USB_IRQ_HGEN
- INT_USB_IRQ_ISO
- INT_USB_IRQ_NISO
- INT_USB_IRQ_OTG
- INT_USB_W2FC
- INT_USB_WARN
- INT_VAL_NOGOOD
- INT_VBUS
- INT_VBUS_VLD
- INT_VDE_EN
- INT_VDE_STA
- INT_VEC_EN_
- INT_VEC_EN_AUTO_CLR
- INT_VEC_EN_CLR
- INT_VEC_EN_SET
- INT_VEC_MAP0
- INT_VEC_MAP0_RX_VEC_
- INT_VEC_MAP1
- INT_VEC_MAP1_TX_VEC_
- INT_VEC_MAP2
- INT_VIRT_SAVE_SRR_AND_JUMP
- INT_VSTART_EN
- INT_VSTART_STATUS
- INT_VSYNC
- INT_VSYNC_EN
- INT_VSYNC_STA
- INT_VSYNC_STATUS
- INT_VSYNC_WB
- INT_WAKE
- INT_WAKEUP
- INT_WAKEUP_EN
- INT_WAKE_EVENT
- INT_WAKSR
- INT_WATCHDOG
- INT_WB_CLR
- INT_WDATERR
- INT_WDATTO
- INT_WDIE
- INT_WD_TIMER
- INT_WORKS_DEF
- INT_WORKS_MAX
- INT_WORKS_MIN
- INT_WRITE_ACK_ERR
- INT_WRITE_INDEX
- INT_WRITE_OP_DONE_EN
- INT_WRITE_SIZE
- INT_WRITE_STATUS
- INT_W_CLEAR
- INT_XMIT_COMPLETED
- INT_XMIT_DISABLED
- INT_XOR
- INT_data
- INT_uWireRX
- INT_uWireTX
- INTbit
- INTn_1_MIX_INP_SEL_DEC0
- INTn_1_MIX_INP_SEL_DEC1
- INTn_1_MIX_INP_SEL_IIR0
- INTn_1_MIX_INP_SEL_IIR1
- INTn_1_MIX_INP_SEL_RX0
- INTn_1_MIX_INP_SEL_RX1
- INTn_1_MIX_INP_SEL_RX2
- INTn_1_MIX_INP_SEL_RX3
- INTn_1_MIX_INP_SEL_RX4
- INTn_1_MIX_INP_SEL_RX5
- INTn_1_MIX_INP_SEL_RX6
- INTn_1_MIX_INP_SEL_RX7
- INTn_1_MIX_INP_SEL_ZERO
- INTn_2_INP_SEL_PROXIMITY
- INTn_2_INP_SEL_RX0
- INTn_2_INP_SEL_RX1
- INTn_2_INP_SEL_RX2
- INTn_2_INP_SEL_RX3
- INTn_2_INP_SEL_RX4
- INTn_2_INP_SEL_RX5
- INTn_2_INP_SEL_RX6
- INTn_2_INP_SEL_RX7
- INTn_2_INP_SEL_ZERO
- INTx
- INTx_EN
- INUM_WARN_WATERMARK
- INUM_WATERMARK
- INUSE_MARGIN_PCT
- INV
- INVACT_LPCMD_TIME
- INVADER_SERIES
- INVALID
- INVALID1
- INVALID2
- INVALIDATE
- INVALIDATE_ADJACENT_PAGES_CPU15
- INVALIDATE_ALL_L1_TLBS
- INVALIDATE_CACHED_RANGE
- INVALIDATE_CACHE_MODE
- INVALIDATE_CACHE_UDELAY
- INVALIDATE_CMD_RESP_EL
- INVALIDATE_L2_CACHE
- INVALIDATE_ONLY_PDE_CACHES
- INVALIDATE_ONLY_PTE_CACHES
- INVALIDATE_PTE_AND_PDE_CACHES
- INVALIDEXCEPTION
- INVALIDFID
- INVALIDIOBA
- INVALIDLENGTH
- INVALIDSTATE
- INVALID_00
- INVALID_ACPI_HANDLE
- INVALID_ACPI_IRQ
- INVALID_ADDR
- INVALID_ARG
- INVALID_BACKLIGHT
- INVALID_BAND
- INVALID_BBRF_VALUE
- INVALID_BEARER_ID
- INVALID_BUFFER
- INVALID_CHANNEL
- INVALID_CHIP_ADDRESS
- INVALID_CID_ADDR
- INVALID_CMD
- INVALID_CNODEID
- INVALID_COMMAND
- INVALID_CONNECTOR_INDEX
- INVALID_COOKIE
- INVALID_COORD
- INVALID_COPP_ID
- INVALID_CTX_ID
- INVALID_DDI_CHANNEL_MAPPING
- INVALID_DEVICE_ID
- INVALID_DMA_ADDRESS
- INVALID_DMA_CHANNEL
- INVALID_EE
- INVALID_END_CHAR
- INVALID_ENTRY
- INVALID_EVTCHN
- INVALID_EVTCHN_IRQ
- INVALID_FID_MASK
- INVALID_FIELD_IN_CDB
- INVALID_FIELD_IN_PARAM_LIST
- INVALID_FORMAT
- INVALID_FW
- INVALID_GENERATE_ADE
- INVALID_GID
- INVALID_GRANT_HANDLE
- INVALID_GRANT_REF
- INVALID_HARTID
- INVALID_HWID
- INVALID_HWIRQ
- INVALID_HW_RING_ID
- INVALID_IDX
- INVALID_INDEX
- INVALID_INST_B
- INVALID_IOQ_NO
- INVALID_IO_BITMAP_OFFSET
- INVALID_IRPTNDX
- INVALID_IRQ
- INVALID_KEY
- INVALID_LINK
- INVALID_LOGIN_ID
- INVALID_MAC
- INVALID_MMIO_REG
- INVALID_MODULE
- INVALID_MUX_GATE_BIT
- INVALID_NASID
- INVALID_NODE_SIG
- INVALID_OMR
- INVALID_OP
- INVALID_OPCODE
- INVALID_P2M_ENTRY
- INVALID_PAGE
- INVALID_PARAM
- INVALID_PARAMETER
- INVALID_PARTID
- INVALID_PAYLOAD
- INVALID_PCR
- INVALID_PENDING_IDX
- INVALID_PENDING_RING_IDX
- INVALID_PHYS_ADDR
- INVALID_PIPE
- INVALID_PLUGIN_LIST_OPTION
- INVALID_PNODEID
- INVALID_POINT
- INVALID_PORT_ID
- INVALID_PROFILE
- INVALID_PROJID
- INVALID_PTK_KEYIDX
- INVALID_QUEUE
- INVALID_RATE_INDEX
- INVALID_RCU_FLAVOR
- INVALID_REGION_ID
- INVALID_REG_ACCESS_TYPE
- INVALID_REG_ADDR
- INVALID_RELID
- INVALID_RESOLUTION_DELAY
- INVALID_RESOLUTION_RETRIES
- INVALID_RESP
- INVALID_RETRY_COUNTER
- INVALID_RPTE_HIDX
- INVALID_SCI
- INVALID_SMENDX
- INVALID_SPEED_MODE
- INVALID_STATE
- INVALID_STATS_CTX_ID
- INVALID_STREAM_HW_ID
- INVALID_STREAM_NUM
- INVALID_STYLE
- INVALID_SYNC_FIELD
- INVALID_TAIL
- INVALID_TAIL_PTR
- INVALID_TARGET
- INVALID_THREAD_HWID
- INVALID_TIME_BIT
- INVALID_TRAFFIC_TYPE_PRIORITY
- INVALID_TRIP
- INVALID_TUNING_PHASE
- INVALID_TUNNEL_HANDLE
- INVALID_TYPE
- INVALID_UID
- INVALID_VID_MASK
- INVALID_VMCI_GUEST_MEM_ID
- INVALID_VNIC_ID
- INVALID_WRITESET_ROOT
- INVALL_VPE
- INVAL_CACHE_AND_WAIT
- INVBLOCK
- INVCHANNEL
- INVCHANSPEC
- INVDCMD
- INVERSE
- INVERSE_F
- INVERSION_AUTO
- INVERSION_OFF
- INVERSION_ON
- INVERT
- INVERTCLK
- INVERTER
- INVERTER_MASK
- INVERT_A
- INVERT_ACK
- INVERT_B
- INVERT_BCLK1
- INVERT_BCLK2
- INVERT_CLOCK
- INVERT_DOCK_STATE_BIT
- INVERT_ENABLE
- INVERT_EXT_PHY_CRS
- INVERT_LED_PWR
- INVERT_MASK
- INVERT_MATCH
- INVERT_MII_PWR
- INVERT_PCS_RX_CLK
- INVERT_PWM_WAVEFORM
- INVERT_REQ
- INVERT_ROP
- INVERT_SERIAL
- INVERT_SIGNAL_DETECT
- INVERT_START
- INVERT_STOP_TRIG
- INVERT_TABLET_MODE_BIT
- INVERT_VOL
- INVGART
- INVLD_UWORD
- INVM_DWORD_TO_RECORD_TYPE
- INVM_DWORD_TO_WORD_ADDRESS
- INVM_DWORD_TO_WORD_DATA
- INVOKE_CB
- INVPCID_TYPE_ALL_INCL_GLOBAL
- INVPCID_TYPE_ALL_NON_GLOBAL
- INVPCID_TYPE_INDIV_ADDR
- INVPCID_TYPE_SINGLE_CTXT
- INV_CLK_INTERNAL
- INV_CLK_PLL
- INV_CNT_ADDR
- INV_ICM20602
- INV_ICM20602_BIT_I2C_IF_DIS
- INV_ICM20602_BYTES_PER_TEMP_SENSOR
- INV_ICM20602_REG_I2C_IF
- INV_ICM20602_SCAN_ACCL_X
- INV_ICM20602_SCAN_ACCL_Y
- INV_ICM20602_SCAN_ACCL_Z
- INV_ICM20602_SCAN_GYRO_X
- INV_ICM20602_SCAN_GYRO_Y
- INV_ICM20602_SCAN_GYRO_Z
- INV_ICM20602_SCAN_TEMP
- INV_ICM20602_SCAN_TIMESTAMP
- INV_ICM20602_WHOAMI_VALUE
- INV_ICM20608
- INV_ICM20608_TEMP_OFFSET
- INV_ICM20608_TEMP_SCALE
- INV_ICM20608_WHOAMI_VALUE
- INV_L2
- INV_LRCK_MASK
- INV_LRCK_MASK_SFT
- INV_LRCK_SFT
- INV_MISMASK
- INV_MPU6000
- INV_MPU6000_WHOAMI_VALUE
- INV_MPU6050
- INV_MPU6050_ACCL_CONFIG_FSR_SHIFT
- INV_MPU6050_ACTIVE_HIGH
- INV_MPU6050_ACTIVE_LOW
- INV_MPU6050_BITS_GYRO_OUT
- INV_MPU6050_BIT_ACCEL_OUT
- INV_MPU6050_BIT_BYPASS_EN
- INV_MPU6050_BIT_CLK_MASK
- INV_MPU6050_BIT_DATA_RDY_EN
- INV_MPU6050_BIT_DMP_EN
- INV_MPU6050_BIT_DMP_INT_EN
- INV_MPU6050_BIT_DMP_RST
- INV_MPU6050_BIT_FIFO_EN
- INV_MPU6050_BIT_FIFO_OVERFLOW_INT
- INV_MPU6050_BIT_FIFO_RST
- INV_MPU6050_BIT_H_RESET
- INV_MPU6050_BIT_I2C_IF_DIS
- INV_MPU6050_BIT_I2C_MST_EN
- INV_MPU6050_BIT_PWR_ACCL_STBY
- INV_MPU6050_BIT_PWR_GYRO_STBY
- INV_MPU6050_BIT_RAW_DATA_RDY_INT
- INV_MPU6050_BIT_SLEEP
- INV_MPU6050_BYTES_PER_3AXIS_SENSOR
- INV_MPU6050_CHAN
- INV_MPU6050_DIVIDER_TO_FIFO_RATE
- INV_MPU6050_FIFO_COUNT_BYTE
- INV_MPU6050_FIFO_RATE_TO_DIVIDER
- INV_MPU6050_FILTER_10HZ
- INV_MPU6050_FILTER_188HZ
- INV_MPU6050_FILTER_20HZ
- INV_MPU6050_FILTER_2100HZ_NOLPF
- INV_MPU6050_FILTER_256HZ_NOLPF2
- INV_MPU6050_FILTER_42HZ
- INV_MPU6050_FILTER_5HZ
- INV_MPU6050_FILTER_98HZ
- INV_MPU6050_FREQ_DIVIDER
- INV_MPU6050_FSR_1000DPS
- INV_MPU6050_FSR_2000DPS
- INV_MPU6050_FSR_250DPS
- INV_MPU6050_FSR_500DPS
- INV_MPU6050_FS_02G
- INV_MPU6050_FS_04G
- INV_MPU6050_FS_08G
- INV_MPU6050_FS_16G
- INV_MPU6050_GYRO_CONFIG_FSR_SHIFT
- INV_MPU6050_IIO_ATTR_ADDR
- INV_MPU6050_INIT_FIFO_RATE
- INV_MPU6050_INTERNAL_FREQ_HZ
- INV_MPU6050_LATCH_INT_EN
- INV_MPU6050_MAX_ACCL_FS_PARAM
- INV_MPU6050_MAX_FIFO_RATE
- INV_MPU6050_MAX_GYRO_FS_PARAM
- INV_MPU6050_MIN_FIFO_RATE
- INV_MPU6050_OUTPUT_DATA_SIZE
- INV_MPU6050_POWER_UP_TIME
- INV_MPU6050_REG_ACCEL_CONFIG
- INV_MPU6050_REG_ACCEL_OFFSET
- INV_MPU6050_REG_CONFIG
- INV_MPU6050_REG_FIFO_COUNT_H
- INV_MPU6050_REG_FIFO_EN
- INV_MPU6050_REG_FIFO_R_W
- INV_MPU6050_REG_GYRO_CONFIG
- INV_MPU6050_REG_GYRO_OFFSET
- INV_MPU6050_REG_INT_ENABLE
- INV_MPU6050_REG_INT_PIN_CFG
- INV_MPU6050_REG_INT_STATUS
- INV_MPU6050_REG_PWR_MGMT_1
- INV_MPU6050_REG_PWR_MGMT_2
- INV_MPU6050_REG_RAW_ACCEL
- INV_MPU6050_REG_RAW_GYRO
- INV_MPU6050_REG_SAMPLE_RATE_DIV
- INV_MPU6050_REG_TEMPERATURE
- INV_MPU6050_REG_UP_TIME_MAX
- INV_MPU6050_REG_UP_TIME_MIN
- INV_MPU6050_REG_USER_CTRL
- INV_MPU6050_REG_WHOAMI
- INV_MPU6050_SCAN_ACCL_X
- INV_MPU6050_SCAN_ACCL_Y
- INV_MPU6050_SCAN_ACCL_Z
- INV_MPU6050_SCAN_GYRO_X
- INV_MPU6050_SCAN_GYRO_Y
- INV_MPU6050_SCAN_GYRO_Z
- INV_MPU6050_SCAN_TIMESTAMP
- INV_MPU6050_SENSOR_UP_TIME
- INV_MPU6050_TEMP_OFFSET
- INV_MPU6050_TEMP_SCALE
- INV_MPU6050_TEMP_UP_TIME
- INV_MPU6050_THREE_AXIS
- INV_MPU6050_TS_PERIOD_JITTER
- INV_MPU6050_WHOAMI_VALUE
- INV_MPU6500
- INV_MPU6500_REG_ACCEL_CONFIG_2
- INV_MPU6500_REG_ACCEL_OFFSET
- INV_MPU6500_TEMP_OFFSET
- INV_MPU6500_TEMP_SCALE
- INV_MPU6500_WHOAMI_VALUE
- INV_MPU6515
- INV_MPU6515_WHOAMI_VALUE
- INV_MPU9150
- INV_MPU9150_WHOAMI_VALUE
- INV_MPU9250
- INV_MPU9250_WHOAMI_VALUE
- INV_MPU9255
- INV_MPU9255_WHOAMI_VALUE
- INV_MPU_ASUS_T100TA
- INV_MPU_NOT_MATCHED
- INV_NUM_PARTS
- INV_PAD_CTRL_MASK
- INV_PAD_CTRL_MASK_SFT
- INV_PAD_CTRL_SFT
- INV_RF_DATA
- INV_TR_SW0
- INV_X
- INV_Y
- INW
- INW_OFF
- IN_4WAY_TIMEOUT_TIME
- IN_82c54_TIMER
- IN_ABORT
- IN_ACCESS
- IN_ALL_EVENTS
- IN_ARCH_STRING_C
- IN_ATTRIB
- IN_BADCLASS
- IN_BAND_FILTER
- IN_BLOCK_READ_REQ
- IN_BPC_10_BITS
- IN_BPC_12_BITS
- IN_BPC_6_BITS
- IN_BPC_8_BITS
- IN_BPC_MASK
- IN_BPC_SHIFT
- IN_BUFLEN
- IN_CD1_VS1H
- IN_CD1_VS2H
- IN_CD2_VS1H
- IN_CD2_VS2H
- IN_CLAMP
- IN_CLASSA
- IN_CLASSA_HOST
- IN_CLASSA_MAX
- IN_CLASSA_NET
- IN_CLASSA_NSHIFT
- IN_CLASSB
- IN_CLASSB_HOST
- IN_CLASSB_MAX
- IN_CLASSB_NET
- IN_CLASSB_NSHIFT
- IN_CLASSC
- IN_CLASSC_HOST
- IN_CLASSC_NET
- IN_CLASSC_NSHIFT
- IN_CLASSD
- IN_CLASSE
- IN_CLASSE_NET
- IN_CLASSE_NSHIFT
- IN_CLK_12MHZ_SELECT
- IN_CLOEXEC
- IN_CLOSE
- IN_CLOSE_NOWRITE
- IN_CLOSE_WRITE
- IN_COLOR_F_MASK
- IN_COLOR_F_RGB
- IN_COLOR_F_SHIFT
- IN_COLOR_F_YCBCR422
- IN_COLOR_F_YCBCR444
- IN_CONST_PREFETCH
- IN_CREATE
- IN_DATA_EMPTY_COUNT
- IN_DATA_STAGE
- IN_DATA_TOKEN
- IN_DELETE
- IN_DELETE_SELF
- IN_DEV_ACCEPT_LOCAL
- IN_DEV_ANDCONF
- IN_DEV_ARPFILTER
- IN_DEV_ARP_ACCEPT
- IN_DEV_ARP_ANNOUNCE
- IN_DEV_ARP_IGNORE
- IN_DEV_ARP_NOTIFY
- IN_DEV_BFORWARD
- IN_DEV_BOOTP_RELAY
- IN_DEV_CONF_GET
- IN_DEV_CONF_SET
- IN_DEV_FORWARD
- IN_DEV_IDTAG
- IN_DEV_IGNORE_ROUTES_WITH_LINKDOWN
- IN_DEV_LOG_MARTIANS
- IN_DEV_MAXCONF
- IN_DEV_MEDIUM_ID
- IN_DEV_MFORWARD
- IN_DEV_NET_ORCONF
- IN_DEV_NET_ROUTE_LOCALNET
- IN_DEV_ORCONF
- IN_DEV_PROMOTE_SECONDARIES
- IN_DEV_PROXY_ARP
- IN_DEV_PROXY_ARP_PVLAN
- IN_DEV_ROUTE_LOCALNET
- IN_DEV_RPFILTER
- IN_DEV_RX_REDIRECTS
- IN_DEV_SEC_REDIRECTS
- IN_DEV_SHARED_MEDIA
- IN_DEV_SOURCE_ROUTE
- IN_DEV_SRC_VMARK
- IN_DEV_TX_REDIRECTS
- IN_DISABLE_0_REG_CLR
- IN_DISABLE_0_REG_SET
- IN_DISABLE_1_REG_CLR
- IN_DISABLE_1_REG_SET
- IN_DISABLE_VAL_0_REG_CLR
- IN_DISABLE_VAL_0_REG_SET
- IN_DISABLE_VAL_1_REG_CLR
- IN_DISABLE_VAL_1_REG_SET
- IN_DONT_FOLLOW
- IN_DOORBELL_OFFSET
- IN_D_RANGE_CEA
- IN_D_RANGE_MASK
- IN_D_RANGE_SHIFT
- IN_D_RANGE_VESA
- IN_EFFECTS_COUNT
- IN_EFFECT_END_NID
- IN_EFFECT_START_NID
- IN_ENDPOINT_ENABLE
- IN_ENDPOINT_TYPE
- IN_EP
- IN_EPP_MODE
- IN_EP_DOORBELL
- IN_EXCL_UNLINK
- IN_EXPERIMENTAL
- IN_EXPR_Y
- IN_FIFO_BASE_ADDRESS
- IN_FIFO_SIZE
- IN_FROM_REG
- IN_FUNC_C1RX
- IN_FUNC_C2RX
- IN_FUNC_IC1
- IN_FUNC_IC2
- IN_FUNC_IC3
- IN_FUNC_IC4
- IN_FUNC_IC5
- IN_FUNC_IC6
- IN_FUNC_IC7
- IN_FUNC_IC8
- IN_FUNC_IC9
- IN_FUNC_INT1
- IN_FUNC_INT2
- IN_FUNC_INT3
- IN_FUNC_INT4
- IN_FUNC_OCFA
- IN_FUNC_REFCLKI1
- IN_FUNC_REFCLKI3
- IN_FUNC_REFCLKI4
- IN_FUNC_SDI1
- IN_FUNC_SDI2
- IN_FUNC_SDI3
- IN_FUNC_SDI4
- IN_FUNC_SDI5
- IN_FUNC_SDI6
- IN_FUNC_SS1
- IN_FUNC_SS2
- IN_FUNC_SS3
- IN_FUNC_SS4
- IN_FUNC_SS5
- IN_FUNC_SS6
- IN_FUNC_T2CK
- IN_FUNC_T3CK
- IN_FUNC_T4CK
- IN_FUNC_T5CK
- IN_FUNC_T6CK
- IN_FUNC_T7CK
- IN_FUNC_T8CK
- IN_FUNC_T9CK
- IN_FUNC_U1CTS
- IN_FUNC_U1RX
- IN_FUNC_U2CTS
- IN_FUNC_U2RX
- IN_FUNC_U3CTS
- IN_FUNC_U3RX
- IN_FUNC_U4CTS
- IN_FUNC_U4RX
- IN_FUNC_U5CTS
- IN_FUNC_U5RX
- IN_FUNC_U6CTS
- IN_FUNC_U6RX
- IN_GUEST_MODE
- IN_I2S_0_CFG_OFFSET
- IN_I2S_0_STREAM_CFG_OFFSET
- IN_I2S_1_CFG_OFFSET
- IN_I2S_1_STREAM_CFG_OFFSET
- IN_I2S_2_CFG_OFFSET
- IN_I2S_2_STREAM_CFG_OFFSET
- IN_IB_PREFETCH_END
- IN_IGNORED
- IN_INCR_UPDT_CONST
- IN_INCR_UPDT_INSTR
- IN_INCR_UPDT_STATE
- IN_INSTR_MATCH
- IN_INSTR_PREFETCH
- IN_INT
- IN_ISDIR
- IN_KERNEL
- IN_KERNEL_RECOV
- IN_LAZYCOMMIT
- IN_LOCK_BH
- IN_LOCK_IRQ
- IN_LOOKUP_SHIFT
- IN_LOOPBACK
- IN_LOOPBACKNET
- IN_LOW
- IN_LSB_IDX
- IN_LSB_REG
- IN_LSB_SHIFT
- IN_LVL_BIT
- IN_MASK_ADD
- IN_MASK_CREATE
- IN_MAX
- IN_MB_INT
- IN_MIRROR_DIV_MASK
- IN_MODIFY
- IN_MOVE
- IN_MOVED_FROM
- IN_MOVED_TO
- IN_MOVE_SELF
- IN_MSG_ACK_CHANGE_SVC
- IN_MSG_ACK_FREE_ITEM
- IN_MSG_CTL_MONIT
- IN_MSG_DATA
- IN_MSG_DEBUG_BUF
- IN_MSG_EC_RESPONSE_PREAMBLE
- IN_MSG_END_BRIDGE_APB_RW
- IN_MSG_END_BRIDGE_I2C_RW
- IN_MSG_END_OF_SCAN
- IN_MSG_ERROR
- IN_MSG_EVENT
- IN_MSG_FE_FW_DL_DONE
- IN_MSG_FRAME_INFO
- IN_MSG_HBM_PROF
- IN_MSG_MONIT_DEMOD
- IN_MSG_MPE_MONITOR
- IN_MSG_RAWTS_MONITOR
- IN_MSG_VERSION
- IN_MULTICAST
- IN_MULTICAST_NET
- IN_NOMINAL
- IN_NONBLOCK
- IN_N_CHANNELS
- IN_ONESHOT
- IN_ONLYDIR
- IN_OPEN
- IN_ORDER_MODE
- IN_PID
- IN_PIPE
- IN_PLACE
- IN_PROGRESS_BITS
- IN_PU
- IN_QUEUE_TH
- IN_Q_OVERFLOW
- IN_RANGE
- IN_RB_SWAP
- IN_READ
- IN_RESET
- IN_RPA14
- IN_RPA15
- IN_RPB0
- IN_RPB1
- IN_RPB10
- IN_RPB14
- IN_RPB15
- IN_RPB2
- IN_RPB3
- IN_RPB5
- IN_RPB6
- IN_RPB7
- IN_RPB8
- IN_RPB9
- IN_RPC1
- IN_RPC13
- IN_RPC14
- IN_RPC2
- IN_RPC3
- IN_RPC4
- IN_RPD0
- IN_RPD1
- IN_RPD10
- IN_RPD11
- IN_RPD12
- IN_RPD14
- IN_RPD15
- IN_RPD2
- IN_RPD3
- IN_RPD4
- IN_RPD5
- IN_RPD6
- IN_RPD7
- IN_RPD9
- IN_RPE3
- IN_RPE5
- IN_RPE8
- IN_RPE9
- IN_RPF0
- IN_RPF1
- IN_RPF12
- IN_RPF13
- IN_RPF2
- IN_RPF3
- IN_RPF4
- IN_RPF5
- IN_RPF8
- IN_RPG0
- IN_RPG1
- IN_RPG6
- IN_RPG7
- IN_RPG8
- IN_RPG9
- IN_SEL_REFCLK
- IN_SRC_NUM_OF_INPUTS
- IN_STATUS_STAGE
- IN_SUBBLK_PREFETCH
- IN_TOKEN_FRAME
- IN_TO_REG
- IN_TX
- IN_UNIT_ATTRS
- IN_UNMOUNT
- IN_USER
- IN_VENDOR_REQ
- IN_VS1
- IN_VS2
- IN_YC_COEFFI_ITU601
- IN_YC_COEFFI_ITU709
- IN_YC_COEFFI_MASK
- IN_YC_COEFFI_SHIFT
- IO
- IO2_B_MARK
- IO2_DATA_IN
- IO2_MARK
- IO3_B_MARK
- IO3_MARK
- IO6DPROM_BASE
- IO6DPROM_SIZE
- IO6PROM_BASE
- IO6PROM_BASE_MAPPED
- IO6PROM_SIZE
- IO6PROM_STACK_SHFT
- IO6PROM_STACK_SIZE
- IO6_GDA_COUNT
- IO6_GDA_OFFSET
- IO6_GDA_SIZE
- IO6_GDA_STRIDE
- IO7_AGP_PORT
- IO7_CONF_KERN
- IO7_CONF_PHYS
- IO7_CSRS_KERN
- IO7_CSRS_PHYS
- IO7_CSR_KERN
- IO7_CSR_PHYS
- IO7_DAC_OFFSET
- IO7_HOSE
- IO7_IID
- IO7_IO_KERN
- IO7_IO_PHYS
- IO7_IO_SPACE
- IO7_IPE
- IO7_IPORT
- IO7_KERN_ADDR
- IO7_MEM_KERN
- IO7_MEM_PHYS
- IO7_MEM_SPACE
- IO7_NUM_PORTS
- IO7_PLL_RNGA
- IO7_PLL_RNGB
- IO7_PORT7_CSRS_KERN
- IO7_PORT7_CSRS_PHYS
- IO7_PORT_MASK
- IO7_POx_WBASE
- IO7__ERR_CYC__CYCLE__M
- IO7__ERR_CYC__CYCLE__S
- IO7__ERR_CYC__EVN_FLT
- IO7__ERR_CYC__LOC
- IO7__ERR_CYC__ODD_FLT
- IO7__ERR_CYC__PACKET__M
- IO7__ERR_CYC__PACKET__S
- IO7__PO7_CRRCT_SYM__ERR_CYC__M
- IO7__PO7_CRRCT_SYM__ERR_CYC__S
- IO7__PO7_CRRCT_SYM__SYN__M
- IO7__PO7_CRRCT_SYM__SYN__S
- IO7__PO7_ERRSUM__BH_BAD_CMD
- IO7__PO7_ERRSUM__BH_CDT_TO
- IO7__PO7_ERRSUM__BH_CLK_HDR
- IO7__PO7_ERRSUM__BH_DBE_HDR
- IO7__PO7_ERRSUM__BH_GBG_HDR
- IO7__PO7_ERRSUM__BH_SUM
- IO7__PO7_ERRSUM__CRD_INT
- IO7__PO7_ERRSUM__CR_CLK_DERR
- IO7__PO7_ERRSUM__CR_CSR_NXM
- IO7__PO7_ERRSUM__CR_DAT_DBE
- IO7__PO7_ERRSUM__CR_DAT_GRBG
- IO7__PO7_ERRSUM__CR_ERR_RESP
- IO7__PO7_ERRSUM__CR_PIO_WBYTE
- IO7__PO7_ERRSUM__CR_RPID_ACV
- IO7__PO7_ERRSUM__CR_RSP_NXM
- IO7__PO7_ERRSUM__CR_SBE
- IO7__PO7_ERRSUM__CR_SBE2
- IO7__PO7_ERRSUM__ERR_LST
- IO7__PO7_ERRSUM__ERR_MASK
- IO7__PO7_ERRSUM__ERR_VALID
- IO7__PO7_ERRSUM__HLT_INT
- IO7__PO7_ERRSUM__HP_INT
- IO7__PO7_ERRSUM__HRD_INT
- IO7__PO7_ERRSUM__MAF_TO
- IO7__PO7_ERRSUM__STV_INT
- IO7__PO7_ERRSUM__UGBGE
- IO7__PO7_ERRSUM__UN_CDT_OVF
- IO7__PO7_ERRSUM__UN_DEALLOC
- IO7__PO7_ERRSUM__UN_MAF_LOST
- IO7__PO7_ERRSUM__UN_PKT_OVF
- IO7__PO7_UGBGE_SYM__UPH_DEST_PID__M
- IO7__PO7_UGBGE_SYM__UPH_DEST_PID__S
- IO7__PO7_UGBGE_SYM__UPH_OPCODE__M
- IO7__PO7_UGBGE_SYM__UPH_OPCODE__S
- IO7__PO7_UGBGE_SYM__UPH_PKT_OFF__M
- IO7__PO7_UGBGE_SYM__UPH_PKT_OFF__S
- IO7__PO7_UGBGE_SYM__UPH_SRC_PORT__M
- IO7__PO7_UGBGE_SYM__UPH_SRC_PORT__S
- IO7__PO7_UGBGE_SYM__VALID
- IO7__PO7_UNCRR_SYM__CDT_OVF_TO__BLK
- IO7__PO7_UNCRR_SYM__CDT_OVF_TO__NBK
- IO7__PO7_UNCRR_SYM__CDT_OVF_TO__REQ
- IO7__PO7_UNCRR_SYM__CDT_OVF_TO__RIO
- IO7__PO7_UNCRR_SYM__CDT_OVF_TO__WIO
- IO7__PO7_UNCRR_SYM__CLK__M
- IO7__PO7_UNCRR_SYM__CLK__S
- IO7__PO7_UNCRR_SYM__DETECT_SP__M
- IO7__PO7_UNCRR_SYM__DETECT_SP__S
- IO7__PO7_UNCRR_SYM__ERR_CYC__M
- IO7__PO7_UNCRR_SYM__ERR_CYC__S
- IO7__PO7_UNCRR_SYM__OVF__FWD
- IO7__PO7_UNCRR_SYM__OVF__READIO
- IO7__PO7_UNCRR_SYM__OVF__WRITEIO
- IO7__PO7_UNCRR_SYM__STRV_VTR__M
- IO7__PO7_UNCRR_SYM__STRV_VTR__S
- IO7__PO7_UNCRR_SYM__SYN__M
- IO7__PO7_UNCRR_SYM__SYN__S
- IO7__PO7_UNCRR_SYM__VICTIM_SP__M
- IO7__PO7_UNCRR_SYM__VICTIM_SP__S
- IO7__POX_ERRSUM__ADDRERR_STB
- IO7__POX_ERRSUM__AGP_REQQ_OVFL
- IO7__POX_ERRSUM__AGP_SYNC_ERR
- IO7__POX_ERRSUM__ALL_MABORTS
- IO7__POX_ERRSUM__CSR_NXM_RD
- IO7__POX_ERRSUM__CSR_NXM_WR
- IO7__POX_ERRSUM__DATAERR_STB_NIOW
- IO7__POX_ERRSUM__DETECTED_PERR
- IO7__POX_ERRSUM__DETECTED_SERR
- IO7__POX_ERRSUM__DMA_RD_TO
- IO7__POX_ERRSUM__DMA_TO
- IO7__POX_ERRSUM__ERR_VALID
- IO7__POX_ERRSUM__HUNG_BUS
- IO7__POX_ERRSUM__MABORT
- IO7__POX_ERRSUM__MABORT_MASK
- IO7__POX_ERRSUM__MRETRY_TO
- IO7__POX_ERRSUM__PCIX_DISCARD_SPL
- IO7__POX_ERRSUM__PCIX_SPLIT_TO
- IO7__POX_ERRSUM__PCIX_UX_SPL
- IO7__POX_ERRSUM__PERR
- IO7__POX_ERRSUM__PM_PERR
- IO7__POX_ERRSUM__PM_TABORT
- IO7__POX_ERRSUM__PT_SCERROR
- IO7__POX_ERRSUM__PT_TABORT
- IO7__POX_ERRSUM__SERR
- IO7__POX_ERRSUM__TABORT_MASK
- IO7__POX_ERRSUM__TLB_ERR
- IO7__POX_ERRSUM__TRANS_SUM__MASK
- IO7__POX_ERRSUM__UPE_ERROR
- IO7__POX_ERRSUM__UPE_ERROR__M
- IO7__POX_ERRSUM__UPE_ERROR__S
- IO7__POX_SPLCMPLT__MESSAGE__M
- IO7__POX_SPLCMPLT__MESSAGE__S
- IO7__POX_SPLCMPLT__MSG_CLASSINDEX__M
- IO7__POX_SPLCMPLT__MSG_CLASSINDEX__S
- IO7__POX_SPLCMPLT__MSG_CLASS__M
- IO7__POX_SPLCMPLT__MSG_CLASS__S
- IO7__POX_SPLCMPLT__MSG_INDEX__M
- IO7__POX_SPLCMPLT__MSG_INDEX__S
- IO7__POX_SPLCMPLT__REM_BYTE_COUNT__M
- IO7__POX_SPLCMPLT__REM_BYTE_COUNT__S
- IO7__POX_SPLCMPLT__REM_LOWER_ADDR__M
- IO7__POX_SPLCMPLT__REM_LOWER_ADDR__S
- IO7__POX_SPLCMPLT__SOURCE_BUS__M
- IO7__POX_SPLCMPLT__SOURCE_BUS__S
- IO7__POX_SPLCMPLT__SOURCE_DEV__M
- IO7__POX_SPLCMPLT__SOURCE_DEV__S
- IO7__POX_SPLCMPLT__SOURCE_FUNC__M
- IO7__POX_SPLCMPLT__SOURCE_FUNC__S
- IO7__POX_TLBERR__ERRCODE__M
- IO7__POX_TLBERR__ERRCODE__S
- IO7__POX_TLBERR__ERR_TLB_PTR__M
- IO7__POX_TLBERR__ERR_TLB_PTR__S
- IO7__POX_TLBERR__ERR_VALID
- IO7__POX_TLBERR__FADDR__M
- IO7__POX_TLBERR__FADDR__S
- IO7__POX_TRANSUM__DAC
- IO7__POX_TRANSUM__ERR_VALID
- IO7__POX_TRANSUM__PCIX_CMD__M
- IO7__POX_TRANSUM__PCIX_CMD__S
- IO7__POX_TRANSUM__PCIX_MASTER_SLOT__M
- IO7__POX_TRANSUM__PCIX_MASTER_SLOT__S
- IO7__POX_TRANSUM__PCI_ADDR__M
- IO7__POX_TRANSUM__PCI_ADDR__S
- IO7__STRV_VTR__IS_MSI
- IO7__STRV_VTR__LSI__BUS__M
- IO7__STRV_VTR__LSI__BUS__S
- IO7__STRV_VTR__LSI__INTX__M
- IO7__STRV_VTR__LSI__INTX__S
- IO7__STRV_VTR__LSI__SLOT__M
- IO7__STRV_VTR__LSI__SLOT__S
- IO7__STRV_VTR__MSI__INTNUM__M
- IO7__STRV_VTR__MSI__INTNUM__S
- IOACCEL1_BUSADDR_CMDTYPE
- IOACCEL1_COMMANDLIST_ALIGNMENT
- IOACCEL1_CONTROL_ACA
- IOACCEL1_CONTROL_DATA_IN
- IOACCEL1_CONTROL_DATA_OUT
- IOACCEL1_CONTROL_HEADOFQUEUE
- IOACCEL1_CONTROL_NODATAXFER
- IOACCEL1_CONTROL_ORDEREDQUEUE
- IOACCEL1_CONTROL_SIMPLEQUEUE
- IOACCEL1_CONTROL_TASKPRIO_MASK
- IOACCEL1_CONTROL_TASKPRIO_SHIFT
- IOACCEL1_FUNCTION_SCSIIO
- IOACCEL1_HCFLAGS_CISS_FORMAT
- IOACCEL1_IOFLAGS_CDBLEN_MASK
- IOACCEL1_IOFLAGS_CDBLEN_MAX
- IOACCEL1_IOFLAGS_IO_REQ
- IOACCEL1_MAXSGENTRIES
- IOACCEL1_SGLOFFSET
- IOACCEL2_ATTR_MASK
- IOACCEL2_CHAIN
- IOACCEL2_COMMANDLIST_ALIGNMENT
- IOACCEL2_DIRECTION_ENCRYPT_MASK
- IOACCEL2_DIRECTION_MASK
- IOACCEL2_DIRECTION_MEMTYPE_MASK
- IOACCEL2_DIR_DATA_IN
- IOACCEL2_DIR_DATA_OUT
- IOACCEL2_DIR_NO_DATA
- IOACCEL2_INBOUND_POSTQ_32
- IOACCEL2_INBOUND_POSTQ_64_HI
- IOACCEL2_INBOUND_POSTQ_64_LOW
- IOACCEL2_IU_TMF_TYPE
- IOACCEL2_IU_TYPE
- IOACCEL2_IU_TYPE_SRF
- IOACCEL2_LAST_SG
- IOACCEL2_MAXSGENTRIES
- IOACCEL2_NO_DATAPRESENT
- IOACCEL2_PRIORITY_MASK
- IOACCEL2_RESERVED
- IOACCEL2_RESPONSE_DATAPRESENT
- IOACCEL2_SENSE_DATA_PRESENT
- IOACCEL2_SERV_RESPONSE_COMPLETE
- IOACCEL2_SERV_RESPONSE_FAILURE
- IOACCEL2_SERV_RESPONSE_TMF_COMPLETE
- IOACCEL2_SERV_RESPONSE_TMF_REJECTED
- IOACCEL2_SERV_RESPONSE_TMF_SUCCESS
- IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN
- IOACCEL2_STATUS_SR_INVALID_DEVICE
- IOACCEL2_STATUS_SR_IOACCEL_DISABLED
- IOACCEL2_STATUS_SR_IO_ABORTED
- IOACCEL2_STATUS_SR_IO_ERROR
- IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE
- IOACCEL2_STATUS_SR_OVERRUN
- IOACCEL2_STATUS_SR_TASK_COMP_ABORTED
- IOACCEL2_STATUS_SR_TASK_COMP_BUSY
- IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND
- IOACCEL2_STATUS_SR_TASK_COMP_GOOD
- IOACCEL2_STATUS_SR_TASK_COMP_RES_CON
- IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL
- IOACCEL2_STATUS_SR_UNDERRUN
- IOACCEL2_TMF
- IOACCEL2_TMF_ABORT
- IOACCEL_MODE1_CONSUMER_INDEX
- IOACCEL_MODE1_PRODUCER_INDEX
- IOACCEL_MODE1_REPLY_QUEUE_INDEX
- IOACCEL_MODE1_REPLY_UNUSED
- IOACCEL_MODE_1
- IOACCEL_STATUS_BYTE
- IOADDR
- IOADL_FLAGS_CHAINED
- IOADL_FLAGS_LAST_DESC
- IOADL_FLAGS_READ_LAST
- IOADL_FLAGS_WRITE_LAST
- IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK
- IOAGR_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT
- IOAGR_HWID
- IOAGR_PERF_CNTL__EVENT0_SEL_MASK
- IOAGR_PERF_CNTL__EVENT0_SEL__SHIFT
- IOAGR_PERF_CNTL__EVENT1_SEL_MASK
- IOAGR_PERF_CNTL__EVENT1_SEL__SHIFT
- IOAGR_PERF_CNTL__EVENT2_SEL_MASK
- IOAGR_PERF_CNTL__EVENT2_SEL__SHIFT
- IOAGR_PERF_CNTL__EVENT3_SEL_MASK
- IOAGR_PERF_CNTL__EVENT3_SEL__SHIFT
- IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK
- IOAGR_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT
- IOAGR_PERF_COUNT0__COUNTER0_MASK
- IOAGR_PERF_COUNT0__COUNTER0__SHIFT
- IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK
- IOAGR_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT
- IOAGR_PERF_COUNT1__COUNTER1_MASK
- IOAGR_PERF_COUNT1__COUNTER1__SHIFT
- IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK
- IOAGR_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT
- IOAGR_PERF_COUNT2__COUNTER2_MASK
- IOAGR_PERF_COUNT2__COUNTER2__SHIFT
- IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK
- IOAGR_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT
- IOAGR_PERF_COUNT3__COUNTER3_MASK
- IOAGR_PERF_COUNT3__COUNTER3__SHIFT
- IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK
- IOAGR_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT
- IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK
- IOAGR_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT
- IOAGR_PGMST_CNTL__CFG_PG_EN_MASK
- IOAGR_PGMST_CNTL__CFG_PG_EN__SHIFT
- IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK
- IOAGR_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT
- IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK
- IOAGR_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK
- IOAGR_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK
- IOAGR_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT
- IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK
- IOAGR_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT
- IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK
- IOAGR_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT
- IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK
- IOAGR_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT
- IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__IOAGR_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__IOAGR_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__IOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK
- IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK
- IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold_MASK
- IOAGR_SION_LiveLock_WatchDog_Threshold__IOAGR_SION_LiveLock_WatchDog_Threshold__SHIFT
- IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__IOAGR_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__IOAGR_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__IOAGR_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__IOAGR_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__IOAGR_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__IOAGR_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__IOAGR_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__IOAGR_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__IOAGR_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__IOAGR_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__IOAGR_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__IOAGR_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__IOAGR_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__IOAGR_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__IOAGR_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__IOAGR_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__IOAGR_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__IOAGR_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__IOAGR_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__IOAGR_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__IOAGR_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__IOAGR_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__IOAGR_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__IOAGR_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__IOAGR_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__IOAGR_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__IOAGR_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__IOAGR_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__IOAGR_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__IOAGR_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__IOAGR_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__IOAGR_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT
- IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK
- IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT
- IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK
- IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT
- IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK
- IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT
- IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK
- IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT
- IOAGR_USERBIT_BYPASS__Userbit_Bypass_MASK
- IOAGR_USERBIT_BYPASS__Userbit_Bypass__SHIFT
- IOAPICMIO_DATA__IOAPICMIO_DATA_MASK
- IOAPICMIO_DATA__IOAPICMIO_DATA__SHIFT
- IOAPICMIO_INDEX__IOAPICMIO_INDEX_data_MASK
- IOAPICMIO_INDEX__IOAPICMIO_INDEX_data__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0__PBr0_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1__PBr1_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2__PBr2_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3__PBr3_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4__PBr4_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5__PBr5_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6__PBr6_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7__PBr7_DevFnMap__SHIFT
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap_MASK
- IOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8__PBr8_DevFnMap__SHIFT
- IOAPIC_ARBITRATION_REGISTER__Arbitration_ID_MASK
- IOAPIC_ARBITRATION_REGISTER__Arbitration_ID__SHIFT
- IOAPIC_AUTO
- IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI_MASK
- IOAPIC_BASE_ADDR_HI__IOAPIC_BASE_ADDR_HI__SHIFT
- IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO_MASK
- IOAPIC_BASE_ADDR_LO__IOAPIC_BASE_ADDR_LO__SHIFT
- IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN_MASK
- IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_EN__SHIFT
- IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK_MASK
- IOAPIC_BASE_ADDR_LO__IOAPIC_MMIO_LOCK__SHIFT
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp_MASK
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_grp__SHIFT
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz_MASK
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_ext_Intr_swz__SHIFT
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map_MASK
- IOAPIC_BR0_INTERRUPT_ROUTING__Br0_int_Intr_map__SHIFT
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp_MASK
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_grp__SHIFT
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz_MASK
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_ext_Intr_swz__SHIFT
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map_MASK
- IOAPIC_BR1_INTERRUPT_ROUTING__Br1_int_Intr_map__SHIFT
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp_MASK
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_grp__SHIFT
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz_MASK
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_ext_Intr_swz__SHIFT
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map_MASK
- IOAPIC_BR2_INTERRUPT_ROUTING__Br2_int_Intr_map__SHIFT
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp_MASK
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_grp__SHIFT
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz_MASK
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_ext_Intr_swz__SHIFT
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map_MASK
- IOAPIC_BR3_INTERRUPT_ROUTING__Br3_int_Intr_map__SHIFT
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp_MASK
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_grp__SHIFT
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz_MASK
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_ext_Intr_swz__SHIFT
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map_MASK
- IOAPIC_BR4_INTERRUPT_ROUTING__Br4_int_Intr_map__SHIFT
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp_MASK
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_grp__SHIFT
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz_MASK
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_ext_Intr_swz__SHIFT
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map_MASK
- IOAPIC_BR5_INTERRUPT_ROUTING__Br5_int_Intr_map__SHIFT
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp_MASK
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_grp__SHIFT
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz_MASK
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_ext_Intr_swz__SHIFT
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map_MASK
- IOAPIC_BR6_INTERRUPT_ROUTING__Br6_int_Intr_map__SHIFT
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp_MASK
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_grp__SHIFT
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz_MASK
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_ext_Intr_swz__SHIFT
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map_MASK
- IOAPIC_BR7_INTERRUPT_ROUTING__Br7_int_Intr_map__SHIFT
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp_MASK
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_grp__SHIFT
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz_MASK
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_ext_Intr_swz__SHIFT
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map_MASK
- IOAPIC_BR8_INTERRUPT_ROUTING__Br8_int_Intr_map__SHIFT
- IOAPIC_DEFAULT_BASE_ADDRESS
- IOAPIC_DEST_MODE_LOGICAL
- IOAPIC_DEST_MODE_PHYSICAL
- IOAPIC_DOMAIN_DYNAMIC
- IOAPIC_DOMAIN_INVALID
- IOAPIC_DOMAIN_LEGACY
- IOAPIC_DOMAIN_STRICT
- IOAPIC_EDGE
- IOAPIC_EDGE_TRIG
- IOAPIC_EXTINT
- IOAPIC_FIXED
- IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK
- IOAPIC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT
- IOAPIC_HWID
- IOAPIC_ID_REGISTER__DEV_ID_MASK
- IOAPIC_ID_REGISTER__DEV_ID__SHIFT
- IOAPIC_ID_REGISTER__EXTEND_ID_MASK
- IOAPIC_ID_REGISTER__EXTEND_ID__SHIFT
- IOAPIC_INIT
- IOAPIC_LEVEL
- IOAPIC_LEVEL_TRIG
- IOAPIC_LOWEST_PRIORITY
- IOAPIC_MAP_ALLOC
- IOAPIC_MAP_CHECK
- IOAPIC_MASKED
- IOAPIC_MEM_LENGTH
- IOAPIC_MIO_DATA__IOAPIC_MIO_DATA_MASK
- IOAPIC_MIO_DATA__IOAPIC_MIO_DATA__SHIFT
- IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data_MASK
- IOAPIC_MIO_INDEX__IOAPIC_MIO_INDEX_data__SHIFT
- IOAPIC_NMI
- IOAPIC_NUM_PINS
- IOAPIC_PERF_CNTL__EVENT0_SEL_MASK
- IOAPIC_PERF_CNTL__EVENT0_SEL__SHIFT
- IOAPIC_PERF_CNTL__EVENT1_SEL_MASK
- IOAPIC_PERF_CNTL__EVENT1_SEL__SHIFT
- IOAPIC_PERF_CNTL__EVENT2_SEL_MASK
- IOAPIC_PERF_CNTL__EVENT2_SEL__SHIFT
- IOAPIC_PERF_CNTL__EVENT3_SEL_MASK
- IOAPIC_PERF_CNTL__EVENT3_SEL__SHIFT
- IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK
- IOAPIC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT
- IOAPIC_PERF_COUNT0__COUNTER0_MASK
- IOAPIC_PERF_COUNT0__COUNTER0__SHIFT
- IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK
- IOAPIC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT
- IOAPIC_PERF_COUNT1__COUNTER1_MASK
- IOAPIC_PERF_COUNT1__COUNTER1__SHIFT
- IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK
- IOAPIC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT
- IOAPIC_PERF_COUNT2__COUNTER2_MASK
- IOAPIC_PERF_COUNT2__COUNTER2__SHIFT
- IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK
- IOAPIC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT
- IOAPIC_PERF_COUNT3__COUNTER3_MASK
- IOAPIC_PERF_COUNT3__COUNTER3__SHIFT
- IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis_MASK
- IOAPIC_PGSLV_CONTROL__PGSLV_Hysteresis__SHIFT
- IOAPIC_PMI
- IOAPIC_POL_HIGH
- IOAPIC_POL_LOW
- IOAPIC_RANGE_END
- IOAPIC_RANGE_START
- IOAPIC_REG_APIC_ID
- IOAPIC_REG_ARB_ID
- IOAPIC_REG_SELECT
- IOAPIC_REG_VERSION
- IOAPIC_REG_WINDOW
- IOAPIC_REMAPPING_ENTRY
- IOAPIC_RESOURCE_NAME_SIZE
- IOAPIC_ROUTING_ENTRY
- IOAPIC_SB_DEVID
- IOAPIC_SCRATCH_0__Scratch_0_MASK
- IOAPIC_SCRATCH_0__Scratch_0__SHIFT
- IOAPIC_SCRATCH_1__Scratch_1_MASK
- IOAPIC_SCRATCH_1__Scratch_1__SHIFT
- IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK
- IOAPIC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT
- IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts_MASK
- IOAPIC_SERIAL_IRQ_STATUS__Internal_irq_sts__SHIFT
- IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT
- IOAPIC_UNMASKED
- IOAPIC_VERSION_ID
- IOAPIC_VERSION_REGISTER__Max_Redirection_Entries_MASK
- IOAPIC_VERSION_REGISTER__Max_Redirection_Entries__SHIFT
- IOAPIC_VERSION_REGISTER__PRQ_MASK
- IOAPIC_VERSION_REGISTER__PRQ__SHIFT
- IOAPIC_VERSION_REGISTER__Version_MASK
- IOAPIC_VERSION_REGISTER__Version__SHIFT
- IOASC_LOG_LEVEL_HARD
- IOASC_LOG_LEVEL_MUST
- IOASC_LOG_LEVEL_NONE
- IOASIC
- IOASIC_ACC_BUS
- IOASIC_CHKSYN
- IOASIC_ERRADDR
- IOASIC_ESAR
- IOASIC_FDC_DMA
- IOASIC_FLOPPY
- IOASIC_IOCTL
- IOASIC_ISDN
- IOASIC_LANCE
- IOASIC_MCR
- IOASIC_RES_15
- IOASIC_SCC0
- IOASIC_SCC1
- IOASIC_SCSI
- IOASIC_SCSI_DMA
- IOASIC_SLOT_SIZE
- IOASIC_SYS_ROM
- IOASIC_TOY
- IOASIC_VDAC_HI
- IOASIC_VDAC_LO
- IOAT1_CHAINADDR_OFFSET
- IOAT1_CHAINADDR_OFFSET_HIGH
- IOAT1_CHAINADDR_OFFSET_LOW
- IOAT1_CHANCMD_OFFSET
- IOAT2_CHAINADDR_OFFSET
- IOAT2_CHAINADDR_OFFSET_HIGH
- IOAT2_CHAINADDR_OFFSET_LOW
- IOAT2_CHANCMD_OFFSET
- IOAT3_APICID_TAG_MAP_OFFSET
- IOAT3_APICID_TAG_MAP_OFFSET_HIGH
- IOAT3_APICID_TAG_MAP_OFFSET_LOW
- IOAT3_CHANCTRL_COMPL_DCA_EN
- IOAT3_CSI_CAPABILITY_OFFSET
- IOAT3_CSI_CAPABILITY_PREFETCH
- IOAT3_CSI_CONTROL_OFFSET
- IOAT3_CSI_CONTROL_PREFETCH
- IOAT3_DCA_GREQID_OFFSET
- IOAT3_DCA_MAX_REQ
- IOAT3_PCI_CAPABILITY_MEMWR
- IOAT3_PCI_CAPABILITY_OFFSET
- IOAT3_PCI_CONTROL_MEMWR
- IOAT3_PCI_CONTROL_OFFSET
- IOATA
- IOATDMA_H
- IOAT_APICID_TAG_CB2_VALID
- IOAT_APICID_TAG_MAP_OFFSET
- IOAT_APICID_TAG_MAP_TAG0
- IOAT_APICID_TAG_MAP_TAG0_SHIFT
- IOAT_APICID_TAG_MAP_TAG1
- IOAT_APICID_TAG_MAP_TAG1_SHIFT
- IOAT_APICID_TAG_MAP_TAG2
- IOAT_APICID_TAG_MAP_TAG2_SHIFT
- IOAT_APICID_TAG_MAP_TAG3
- IOAT_APICID_TAG_MAP_TAG3_SHIFT
- IOAT_APICID_TAG_MAP_TAG4
- IOAT_APICID_TAG_MAP_TAG4_SHIFT
- IOAT_ATTNSTATUS_OFFSET
- IOAT_CAP_APIC
- IOAT_CAP_CRC
- IOAT_CAP_CRC_MOVE
- IOAT_CAP_DCA
- IOAT_CAP_DPS
- IOAT_CAP_DWBES
- IOAT_CAP_FILL_BLOCK
- IOAT_CAP_PAGE_BREAK
- IOAT_CAP_PQ
- IOAT_CAP_RAID16SS
- IOAT_CAP_SKIP_MARKER
- IOAT_CAP_XOR
- IOAT_CDAR_OFFSET
- IOAT_CDAR_OFFSET_HIGH
- IOAT_CDAR_OFFSET_LOW
- IOAT_CHAINADDR_OFFSET
- IOAT_CHAINADDR_OFFSET_HIGH
- IOAT_CHAINADDR_OFFSET_LOW
- IOAT_CHANCMD_ABORT
- IOAT_CHANCMD_APPEND
- IOAT_CHANCMD_OFFSET
- IOAT_CHANCMD_RESET
- IOAT_CHANCMD_RESUME
- IOAT_CHANCMD_START
- IOAT_CHANCMD_SUSPEND
- IOAT_CHANCMP_OFFSET
- IOAT_CHANCMP_OFFSET_HIGH
- IOAT_CHANCMP_OFFSET_LOW
- IOAT_CHANCNT_OFFSET
- IOAT_CHANCTRL_ANY_ERR_ABORT_EN
- IOAT_CHANCTRL_CHANNEL_IN_USE
- IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK
- IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL
- IOAT_CHANCTRL_ERR_COMPLETION_EN
- IOAT_CHANCTRL_ERR_INT_EN
- IOAT_CHANCTRL_INT_REARM
- IOAT_CHANCTRL_OFFSET
- IOAT_CHANCTRL_RUN
- IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR
- IOAT_CHANERR_CHANCMD_ERR
- IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR
- IOAT_CHANERR_COMPLETION_ADDR_ERR
- IOAT_CHANERR_CONTROL_ERR
- IOAT_CHANERR_DESCRIPTOR_COUNT_ERR
- IOAT_CHANERR_DEST_ADDR_ERR
- IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR
- IOAT_CHANERR_HANDLE_MASK
- IOAT_CHANERR_INT_CONFIGURATION_ERR
- IOAT_CHANERR_LENGTH_ERR
- IOAT_CHANERR_MASK_OFFSET
- IOAT_CHANERR_NEXT_ADDR_ERR
- IOAT_CHANERR_NEXT_DESC_ALIGN_ERR
- IOAT_CHANERR_OFFSET
- IOAT_CHANERR_READ_DATA_ERR
- IOAT_CHANERR_RECOVER_MASK
- IOAT_CHANERR_SOFT_ERR
- IOAT_CHANERR_SRC_ADDR_ERR
- IOAT_CHANERR_UNAFFILIATED_ERR
- IOAT_CHANERR_WRITE_DATA_ERR
- IOAT_CHANERR_XOR_P_OR_CRC_ERR
- IOAT_CHANERR_XOR_Q_ERR
- IOAT_CHANNEL_MMIO_SIZE
- IOAT_CHANSTS_ACTIVE
- IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR
- IOAT_CHANSTS_DONE
- IOAT_CHANSTS_HALTED
- IOAT_CHANSTS_OFFSET
- IOAT_CHANSTS_SOFT_ERR
- IOAT_CHANSTS_STATUS
- IOAT_CHANSTS_SUSPENDED
- IOAT_CHANSTS_UNAFFILIATED_ERR
- IOAT_CHAN_ACTIVE
- IOAT_CHAN_DMACOUNT_OFFSET
- IOAT_CHAN_DOWN
- IOAT_CHAN_DRSCTL_OFFSET
- IOAT_CHAN_DRSZ_2MB
- IOAT_CHAN_DRSZ_4KB
- IOAT_CHAN_DRSZ_8KB
- IOAT_CHAN_DRS_AUTOWRAP
- IOAT_CHAN_DRS_EN
- IOAT_CHAN_LTR_ACTIVE_OFFSET
- IOAT_CHAN_LTR_ACTIVE_SNLATSCALE
- IOAT_CHAN_LTR_ACTIVE_SNREQMNT
- IOAT_CHAN_LTR_ACTIVE_SNVAL
- IOAT_CHAN_LTR_IDLE_OFFSET
- IOAT_CHAN_LTR_IDLE_SNLATSCALE
- IOAT_CHAN_LTR_IDLE_SNREQMNT
- IOAT_CHAN_LTR_IDLE_SNVAL
- IOAT_CHAN_LTR_SWSEL_ACTIVE
- IOAT_CHAN_LTR_SWSEL_IDLE
- IOAT_CHAN_LTR_SWSEL_OFFSET
- IOAT_COMPLETION_ACK
- IOAT_DCACTRL_CMPL_WRITE_ENABLE
- IOAT_DCACTRL_OFFSET
- IOAT_DCACTRL_TARGET_CPU_MASK
- IOAT_DCAOFFSET_OFFSET
- IOAT_DCA_COMP_OFFSET
- IOAT_DCA_COMP_V1
- IOAT_DCA_GREQID_IGNOREFUN
- IOAT_DCA_GREQID_LASTID
- IOAT_DCA_GREQID_MASK
- IOAT_DCA_GREQID_OFFSET
- IOAT_DCA_GREQID_SIZE
- IOAT_DCA_GREQID_VALID
- IOAT_DCA_MAX_REQ
- IOAT_DCA_VER_MAJOR_MASK
- IOAT_DCA_VER_MINOR_MASK
- IOAT_DCA_VER_OFFSET
- IOAT_DESCS_PER_2M
- IOAT_DESC_SZ
- IOAT_DEVCTRL_OFFSET
- IOAT_DEVCTRL_ROE
- IOAT_DEVICE_ADDRESS_REMAPPING
- IOAT_DEVICE_MEMORY_BYPASS
- IOAT_DEVICE_MMIO_RESTRICTED
- IOAT_DEVICE_STATUS_DEGRADED_MODE
- IOAT_DEVICE_STATUS_OFFSET
- IOAT_DMA_CAP_OFFSET
- IOAT_DMA_COMP_OFFSET
- IOAT_DMA_COMP_V1
- IOAT_DMA_COMP_V2
- IOAT_DMA_DCA_ANY_CPU
- IOAT_DMA_VERSION
- IOAT_FSB_CAPABILITY_OFFSET
- IOAT_FSB_CAPABILITY_PREFETCH
- IOAT_FSB_CAP_ENABLE_OFFSET
- IOAT_FSB_CAP_ENABLE_PREFETCH
- IOAT_GENCTRL_DEBUG_EN
- IOAT_GENCTRL_OFFSET
- IOAT_INTRCTRL_INT
- IOAT_INTRCTRL_INT_STATUS
- IOAT_INTRCTRL_MASTER_INT_EN
- IOAT_INTRCTRL_MSIX_VECTOR_CONTROL
- IOAT_INTRCTRL_OFFSET
- IOAT_INTRDELAY_COALESE_SUPPORT
- IOAT_INTRDELAY_MASK
- IOAT_INTRDELAY_OFFSET
- IOAT_INTX
- IOAT_KOBJ_INIT_FAIL
- IOAT_MAX_CHANS
- IOAT_MAX_DESCS
- IOAT_MAX_ORDER
- IOAT_MMIO_BAR
- IOAT_MSI
- IOAT_MSIX
- IOAT_NOIRQ
- IOAT_NUM_SRC_TEST
- IOAT_OP_COPY
- IOAT_OP_PQ
- IOAT_OP_PQ_16S
- IOAT_OP_PQ_UP
- IOAT_OP_PQ_VAL
- IOAT_OP_PQ_VAL_16S
- IOAT_OP_XOR
- IOAT_OP_XOR_VAL
- IOAT_PCI_CAPABILITY_MEMWR
- IOAT_PCI_CAPABILITY_OFFSET
- IOAT_PCI_CAP_ENABLE_MEMWR
- IOAT_PCI_CAP_ENABLE_OFFSET
- IOAT_PCI_CHANERRMASK_INT_OFFSET
- IOAT_PCI_CHANERR_INT_OFFSET
- IOAT_PCI_DEVICE_ID_OFFSET
- IOAT_PCI_DMACTRL_DMA_EN
- IOAT_PCI_DMACTRL_MSI_EN
- IOAT_PCI_DMACTRL_OFFSET
- IOAT_PCI_DMAUNCERRSTS_OFFSET
- IOAT_PERPORTOFFSET_OFFSET
- IOAT_PREFETCH_LIMIT_OFFSET
- IOAT_RESET_PENDING
- IOAT_RUN
- IOAT_TAG_MAP_LEN
- IOAT_TEST_SIZE
- IOAT_VER_1_2
- IOAT_VER_2_0
- IOAT_VER_3_0
- IOAT_VER_3_2
- IOAT_VER_3_3
- IOAT_VER_3_4
- IOAT_VER_MAJOR_MASK
- IOAT_VER_MINOR_MASK
- IOAT_VER_OFFSET
- IOAT_XFERCAP_16KB
- IOAT_XFERCAP_32GB
- IOAT_XFERCAP_32KB
- IOAT_XFERCAP_4KB
- IOAT_XFERCAP_8KB
- IOAT_XFERCAP_OFFSET
- IOA_NORMAL_MODE
- IOA_STATE_DEAD
- IOA_STATE_IN_BRINGDOWN
- IOA_STATE_IN_BRINGUP
- IOA_STATE_IN_HARD_RESET
- IOA_STATE_IN_RESET_ALERT
- IOA_STATE_IN_SOFT_RESET
- IOA_STATE_OPERATIONAL
- IOA_STATE_UNKNOWN
- IOBAR
- IOBASE
- IOBASE2
- IOBASE_ADDR
- IOBASE_BRIDGE_NUMBER
- IOBASE_DENSE_IO
- IOBASE_DENSE_MEM
- IOBASE_END
- IOBASE_FROM_HOSE
- IOBASE_HOSE
- IOBASE_IO
- IOBASE_ISA_IO
- IOBASE_ISA_MEM
- IOBASE_MEMORY
- IOBASE_ROOT_BUS
- IOBASE_SPARSE_IO
- IOBASE_SPARSE_MEM
- IOBASE_VADDR
- IOBAXIS0TRANSERRINTMSK
- IOBAXIS0TRANSERRINTSTS
- IOBAXIS0TRANSERRREQINFOH
- IOBAXIS0TRANSERRREQINFOL
- IOBAXIS0_ILLEGAL_ACCESS_MASK
- IOBAXIS0_M_ILLEGAL_ACCESS_MASK
- IOBAXIS1TRANSERRINTMSK
- IOBAXIS1TRANSERRINTSTS
- IOBAXIS1TRANSERRREQINFOH
- IOBAXIS1TRANSERRREQINFOL
- IOBBATRANSERRCSWREQID
- IOBBATRANSERRINTSTS
- IOBBATRANSERRREQINFOH
- IOBBATRANSERRREQINFOL
- IOBCAP_REG
- IOBCOM_ATEN
- IOBCOM_REG
- IOBMAP_L1E_BIG_CACHED
- IOBMAP_L1E_BIG_PRIORITY
- IOBMAP_L1E_V
- IOBMAP_L1E_V_B
- IOBMAP_L2E_V
- IOBMAP_L2E_V_CACHED
- IOBMAP_PAGE_MASK
- IOBMAP_PAGE_SHIFT
- IOBMAP_PAGE_SIZE
- IOBPATRANSERRINTSTS
- IOBPA_M_RDATA_CORRUPT_MASK
- IOBPA_M_REQIDRAM_CORRUPT_MASK
- IOBPA_M_TRANS_CORRUPT_MASK
- IOBPA_M_WDATA_CORRUPT_MASK
- IOBPA_RDATA_CORRUPT_MASK
- IOBPA_REQIDRAM_CORRUPT_MASK
- IOBPA_TRANS_CORRUPT_MASK
- IOBPA_WDATA_CORRUPT_MASK
- IOBRIDGE
- IOBUF_SIZE
- IOB_AD_MPSEL_B38
- IOB_AD_MPSEL_B40
- IOB_AD_MPSEL_B42
- IOB_AD_MPSEL_MASK
- IOB_AD_REG
- IOB_AD_TRNG_128G
- IOB_AD_TRNG_256M
- IOB_AD_TRNG_2G
- IOB_AD_TRNG_MASK
- IOB_AD_VGAEN
- IOB_AD_VGPRT
- IOB_AT_INVAL_TLB_REG
- IOB_BASE
- IOB_BA_ERR_MASK
- IOB_PA_ERR_MASK
- IOB_RB_ERR_MASK
- IOB_SIZE
- IOB_TABLEBASE_REG
- IOB_XGIC_ERR_MASK
- IOB_XLT_L1_REGBASE
- IOC3_BYTEBUS_DEV0
- IOC3_BYTEBUS_DEV1
- IOC3_BYTEBUS_DEV2
- IOC3_BYTEBUS_DEV3
- IOC3_CLASS_BASE_IP27
- IOC3_CLASS_BASE_IP30
- IOC3_CLASS_CADDUO
- IOC3_CLASS_MENET_123
- IOC3_CLASS_MENET_4
- IOC3_CLASS_NONE
- IOC3_CLASS_SERIAL
- IOC3_CLK
- IOC3_DMA_XFER_LEN
- IOC3_FLAGS
- IOC3_MAX_SUBMODULES
- IOC3_NAME
- IOC3_SIO_BASE
- IOC3_SIO_KBDCG
- IOC3_SIO_PP_BASE
- IOC3_SIO_RTC_BASE
- IOC3_SIO_UARTC
- IOC3_SIO_UA_BASE
- IOC3_SIO_UB_BASE
- IOC3_SIZE
- IOC3_SSRAM
- IOC3_SSRAM_DM
- IOC3_SSRAM_LEN
- IOC3_SSRAM_PM
- IOC3_VERSION
- IOC3_W_IEC
- IOC3_W_IES
- IOCB_APPEND
- IOCB_BUSY
- IOCB_CMD_FDSYNC
- IOCB_CMD_FSYNC
- IOCB_CMD_NOOP
- IOCB_CMD_POLL
- IOCB_CMD_PREAD
- IOCB_CMD_PREADV
- IOCB_CMD_PWRITE
- IOCB_CMD_PWRITEV
- IOCB_DIRECT
- IOCB_DSYNC
- IOCB_ERROR
- IOCB_EVENTFD
- IOCB_FLAG_IOPRIO
- IOCB_FLAG_RESFD
- IOCB_HIPRI
- IOCB_HIWAT_CUSHION
- IOCB_MAX_CDB_LEN
- IOCB_MAX_EXT_SENSEDATA_LEN
- IOCB_MAX_SENSEDATA_LEN
- IOCB_NOWAIT
- IOCB_SIZE
- IOCB_SUCCESS
- IOCB_SYNC
- IOCB_TIMEDOUT
- IOCB_TOV_MARGIN
- IOCB_WORD_SZ
- IOCB_WRITE
- IOCB_t
- IOCETH_E_DISABLE
- IOCETH_E_ENABLE
- IOCETH_E_ENET_ATTR_RESP
- IOCETH_E_ENET_STOPPED
- IOCETH_E_IOC_DISABLED
- IOCETH_E_IOC_FAILED
- IOCETH_E_IOC_READY
- IOCETH_E_IOC_RESET
- IOCFC_E_CFG_DONE
- IOCFC_E_DCONF_DONE
- IOCFC_E_DISABLE
- IOCFC_E_ENABLE
- IOCFC_E_INIT
- IOCFC_E_IOC_DISABLED
- IOCFC_E_IOC_ENABLED
- IOCFC_E_IOC_FAILED
- IOCFC_E_START
- IOCFC_E_STOP
- IOCFG_BALLCFG
- IOCFG_IG
- IOCFactsReply_t
- IOCFacts_t
- IOCHAN_DESC
- IOCHAN_FROM_IOPART
- IOCHAN_RAW_DESC
- IOCHAN_TO_IOPART
- IOCInitReply_t
- IOCInit_t
- IOCMD_ADAPTER_CFG_MODE
- IOCMD_BB_READ_IDX
- IOCMD_BB_WRITE_IDX
- IOCMD_BOOT_CFG
- IOCMD_BOOT_QUERY
- IOCMD_CEE_GET_ATTR
- IOCMD_CEE_GET_STATS
- IOCMD_CEE_RESET_STATS
- IOCMD_CLASS_BB_RF
- IOCMD_CTRL_REG
- IOCMD_DATA_REG
- IOCMD_DEBUG_FW_CORE
- IOCMD_DEBUG_FW_STATE_CLR
- IOCMD_DEBUG_PORTLOG
- IOCMD_DEBUG_PORTLOG_CLR
- IOCMD_DEBUG_PORTLOG_CTL
- IOCMD_DEBUG_START_DTRC
- IOCMD_DEBUG_STOP_DTRC
- IOCMD_DIAG_BEACON_LPORT
- IOCMD_DIAG_DPORT_DISABLE
- IOCMD_DIAG_DPORT_ENABLE
- IOCMD_DIAG_DPORT_SHOW
- IOCMD_DIAG_DPORT_START
- IOCMD_DIAG_FWPING
- IOCMD_DIAG_LB_STAT
- IOCMD_DIAG_LED
- IOCMD_DIAG_LOOPBACK
- IOCMD_DIAG_MEMTEST
- IOCMD_DIAG_QUEUETEST
- IOCMD_DIAG_SFP
- IOCMD_DIAG_TEMP
- IOCMD_ETHBOOT_CFG
- IOCMD_ETHBOOT_QUERY
- IOCMD_FAA_QUERY
- IOCMD_FABRIC_GET_LPORTS
- IOCMD_FCPIM_DEL_ITN_STATS
- IOCMD_FCPIM_FAILOVER
- IOCMD_FCPIM_LUNMASK_ADD
- IOCMD_FCPIM_LUNMASK_CLEAR
- IOCMD_FCPIM_LUNMASK_DELETE
- IOCMD_FCPIM_LUNMASK_DISABLE
- IOCMD_FCPIM_LUNMASK_ENABLE
- IOCMD_FCPIM_LUNMASK_QUERY
- IOCMD_FCPIM_MODSTATS
- IOCMD_FCPIM_MODSTATSCLR
- IOCMD_FCPIM_PROFILE_OFF
- IOCMD_FCPIM_PROFILE_ON
- IOCMD_FCPIM_THROTTLE_QUERY
- IOCMD_FCPIM_THROTTLE_SET
- IOCMD_FCPORT_DISABLE
- IOCMD_FCPORT_ENABLE
- IOCMD_FCPORT_GET_STATS
- IOCMD_FCPORT_RESET_STATS
- IOCMD_FLASH_DISABLE_OPTROM
- IOCMD_FLASH_ENABLE_OPTROM
- IOCMD_FLASH_ERASE_PART
- IOCMD_FLASH_GET_ATTR
- IOCMD_FLASH_READ_PART
- IOCMD_FLASH_UPDATE_PART
- IOCMD_FRUVPD_GET_MAX_SIZE
- IOCMD_FRUVPD_READ
- IOCMD_FRUVPD_UPDATE
- IOCMD_GET_THERMAL_METER
- IOCMD_IOCFC_GET_ATTR
- IOCMD_IOCFC_SET_INTR
- IOCMD_IOC_DISABLE
- IOCMD_IOC_ENABLE
- IOCMD_IOC_FW_SIG_INV
- IOCMD_IOC_GET_ATTR
- IOCMD_IOC_GET_FWSTATS
- IOCMD_IOC_GET_INFO
- IOCMD_IOC_GET_STATS
- IOCMD_IOC_PCIFN_CFG
- IOCMD_IOC_RESET_FWSTATS
- IOCMD_IOC_RESET_STATS
- IOCMD_IOC_SET_ADAPTER_NAME
- IOCMD_IOC_SET_PORT_NAME
- IOCMD_ITNIM_GET_ATTR
- IOCMD_ITNIM_GET_IOPROFILE
- IOCMD_ITNIM_GET_IOSTATS
- IOCMD_ITNIM_GET_ITNSTATS
- IOCMD_ITNIM_RESET_STATS
- IOCMD_LPORT_GET_ATTR
- IOCMD_LPORT_GET_IOSTATS
- IOCMD_LPORT_GET_RPORTS
- IOCMD_LPORT_GET_STATS
- IOCMD_LPORT_RESET_STATS
- IOCMD_PCIFN_BW
- IOCMD_PCIFN_CREATE
- IOCMD_PCIFN_DELETE
- IOCMD_PHY_GET_ATTR
- IOCMD_PHY_GET_STATS
- IOCMD_PHY_READ_FW
- IOCMD_PHY_UPDATE_FW
- IOCMD_PORT_BBCR_DISABLE
- IOCMD_PORT_BBCR_ENABLE
- IOCMD_PORT_BBCR_GET_ATTR
- IOCMD_PORT_CFG_ALPA
- IOCMD_PORT_CFG_MAXFRSZ
- IOCMD_PORT_CFG_MODE
- IOCMD_PORT_CFG_SPEED
- IOCMD_PORT_CFG_TOPO
- IOCMD_PORT_CLR_ALPA
- IOCMD_PORT_DISABLE
- IOCMD_PORT_ENABLE
- IOCMD_PORT_GET_ATTR
- IOCMD_PORT_GET_STATS
- IOCMD_PORT_RESET_STATS
- IOCMD_PREBOOT_QUERY
- IOCMD_QOS_DISABLE
- IOCMD_QOS_ENABLE
- IOCMD_QOS_GET_ATTR
- IOCMD_QOS_GET_STATS
- IOCMD_QOS_GET_VC_ATTR
- IOCMD_QOS_RESET_STATS
- IOCMD_QOS_SET_BW
- IOCMD_RATELIM_DEF_SPEED
- IOCMD_RATELIM_DISABLE
- IOCMD_RATELIM_ENABLE
- IOCMD_RF_READ_IDX
- IOCMD_RF_WRIT_IDX
- IOCMD_RPORT_GET_ADDR
- IOCMD_RPORT_GET_ATTR
- IOCMD_RPORT_GET_STATS
- IOCMD_RPORT_RESET_STATS
- IOCMD_RPORT_SET_SPEED
- IOCMD_SFP_MEDIA
- IOCMD_SFP_SPEED
- IOCMD_STRUCT
- IOCMD_TFRU_READ
- IOCMD_TFRU_WRITE
- IOCMD_TRUNK_DISABLE
- IOCMD_TRUNK_ENABLE
- IOCMD_TRUNK_GET_ATTR
- IOCMD_VF_GET_STATS
- IOCMD_VF_RESET_STATS
- IOCMD_VHBA_QUERY
- IOCMD_VPORT_GET_ATTR
- IOCMD_VPORT_GET_STATS
- IOCMD_VPORT_RESET_STATS
- IOCNR_GET_BUS_ADDRESS
- IOCNR_GET_DEVICE_ID
- IOCNR_GET_PROTOCOLS
- IOCNR_GET_VID_PID
- IOCNR_HP_SET_CHANNEL
- IOCNR_SET_PROTOCOL
- IOCNR_SOFT_RESET
- IOCONTEXT_H
- IOCON_HAEN
- IOCON_INTCC
- IOCON_INTPOL
- IOCON_MIRROR
- IOCON_ODR
- IOCON_SEQOP
- IOCPF_E_DISABLE
- IOCPF_E_ENABLE
- IOCPF_E_FAIL
- IOCPF_E_FWREADY
- IOCPF_E_FWRSP_DISABLE
- IOCPF_E_FWRSP_ENABLE
- IOCPF_E_GETATTRFAIL
- IOCPF_E_INITFAIL
- IOCPF_E_SEMLOCKED
- IOCPF_E_SEM_ERROR
- IOCPF_E_STOP
- IOCPF_E_TIMEOUT
- IOCPage0_t
- IOCPage1_t
- IOCPage2_t
- IOCPage3_t
- IOCPage4_t
- IOCPage5_t
- IOCPage6_t
- IOCR
- IOCR_INPUTS_OFFSET
- IOCR_OUTPUTS_OFFSET
- IOCSIZE_MASK
- IOCSIZE_SHIFT
- IOCTL32_Command_struct
- IOCTL_ABORT
- IOCTL_BAD_CHANNEL
- IOCTL_BAD_FLASH_IMGTYPE
- IOCTL_BUF_SIZE
- IOCTL_CMD
- IOCTL_CONFIG_SYS_RESOURCE_PARAMETERS
- IOCTL_Command_struct
- IOCTL_ERR_INVCMD
- IOCTL_EVTCHN_BIND_INTERDOMAIN
- IOCTL_EVTCHN_BIND_UNBOUND_PORT
- IOCTL_EVTCHN_BIND_VIRQ
- IOCTL_EVTCHN_NOTIFY
- IOCTL_EVTCHN_RESET
- IOCTL_EVTCHN_RESTRICT_DOMID
- IOCTL_EVTCHN_UNBIND
- IOCTL_FLAGS_ISSUE_GLOBAL_EVENT
- IOCTL_FLAGS_NO_PARAMS
- IOCTL_GENERAL_ERROR
- IOCTL_GET_DRV_VERSION
- IOCTL_GET_HARD_VERSION
- IOCTL_GET_NUM_DEVICES
- IOCTL_GET_PLL_FRAC_DATA
- IOCTL_GET_PLL_FRAC_MODE
- IOCTL_GNTALLOC_ALLOC_GREF
- IOCTL_GNTALLOC_DEALLOC_GREF
- IOCTL_GNTALLOC_SET_UNMAP_NOTIFY
- IOCTL_GNTDEV_DMABUF_EXP_FROM_REFS
- IOCTL_GNTDEV_DMABUF_EXP_WAIT_RELEASED
- IOCTL_GNTDEV_DMABUF_IMP_RELEASE
- IOCTL_GNTDEV_DMABUF_IMP_TO_REFS
- IOCTL_GNTDEV_GET_OFFSET_FOR_VADDR
- IOCTL_GNTDEV_GRANT_COPY
- IOCTL_GNTDEV_MAP_GRANT_REF
- IOCTL_GNTDEV_SET_MAX_GRANTS
- IOCTL_GNTDEV_SET_UNMAP_NOTIFY
- IOCTL_GNTDEV_UNMAP_GRANT_REF
- IOCTL_IN
- IOCTL_INFO
- IOCTL_INIT_FAILED
- IOCTL_INVALID_PARAM
- IOCTL_IOSB_TYPE_FX00
- IOCTL_ISSUE
- IOCTL_MAX_DATALEN
- IOCTL_MEI_CONNECT_CLIENT
- IOCTL_MEI_NOTIFY_GET
- IOCTL_MEI_NOTIFY_SET
- IOCTL_MW_DSP_ABILITIES
- IOCTL_MW_GET_IPC
- IOCTL_MW_READCLEAR_DATA
- IOCTL_MW_READ_DATA
- IOCTL_MW_READ_INST
- IOCTL_MW_REGISTER_IPC
- IOCTL_MW_RESET
- IOCTL_MW_RUN
- IOCTL_MW_TRACE
- IOCTL_MW_UNREGISTER_IPC
- IOCTL_MW_WRITE_DATA
- IOCTL_MW_WRITE_INST
- IOCTL_NORMAL_TIMEOUT
- IOCTL_NOT_IMPLEMENTED
- IOCTL_OUT
- IOCTL_OUT_OF_RESOURCES
- IOCTL_PRI
- IOCTL_PRIVCMD_DM_OP
- IOCTL_PRIVCMD_HYPERCALL
- IOCTL_PRIVCMD_MMAP
- IOCTL_PRIVCMD_MMAPBATCH
- IOCTL_PRIVCMD_MMAPBATCH_V2
- IOCTL_PRIVCMD_MMAP_RESOURCE
- IOCTL_PRIVCMD_RESTRICT
- IOCTL_RAW_TRACK
- IOCTL_RESP_TIMEOUT
- IOCTL_RETRIES
- IOCTL_SET_PLL_FRAC_DATA
- IOCTL_SET_PLL_FRAC_MODE
- IOCTL_START_ACCEL_DEV
- IOCTL_STATUS_ACCEL_DEV
- IOCTL_STOP_ACCEL_DEV
- IOCTL_SUCCESS
- IOCTL_TARGET_NOT_ENABLED
- IOCTL_TARGET_OVERRUN
- IOCTL_TIMEOUT
- IOCTL_VMCI_CTX_ADD_NOTIFICATION
- IOCTL_VMCI_CTX_GET_CPT_STATE
- IOCTL_VMCI_CTX_REMOVE_NOTIFICATION
- IOCTL_VMCI_CTX_SET_CPT_STATE
- IOCTL_VMCI_DATAGRAM_RECEIVE
- IOCTL_VMCI_DATAGRAM_SEND
- IOCTL_VMCI_GET_CONTEXT_ID
- IOCTL_VMCI_INIT_CONTEXT
- IOCTL_VMCI_NOTIFICATIONS_RECEIVE
- IOCTL_VMCI_NOTIFY_RESOURCE
- IOCTL_VMCI_QUEUEPAIR_ALLOC
- IOCTL_VMCI_QUEUEPAIR_DETACH
- IOCTL_VMCI_QUEUEPAIR_SETPAGEFILE
- IOCTL_VMCI_QUEUEPAIR_SETVA
- IOCTL_VMCI_SET_NOTIFY
- IOCTL_VMCI_SOCKETS_GET_AF_VALUE
- IOCTL_VMCI_SOCKETS_GET_LOCAL_CID
- IOCTL_VMCI_SOCKETS_VERSION
- IOCTL_VMCI_VERSION
- IOCTL_VMCI_VERSION2
- IOCTL_VM_SOCKETS_GET_LOCAL_CID
- IOCTL_WDM_MAX_COMMAND
- IOCTL_XENBUS_BACKEND_EVTCHN
- IOCTL_XENBUS_BACKEND_SETUP
- IOCTL_XMIT_PACKET
- IOCTRL_TYPE_AON
- IOCTRL_TYPE_CDRU
- IOCTRL_TYPE_INVALID
- IOC_3_PHYS_DISK
- IOC_4_SEP
- IOC_5_HOT_SPARE
- IOC_AND_NETDEV_NAMES_s_s
- IOC_BASE
- IOC_CMD
- IOC_CMD_SHIFT
- IOC_CODE
- IOC_CODE_SHIFT
- IOC_CONTROL
- IOC_CTRL
- IOC_CTRL_CE
- IOC_CTRL_D4
- IOC_CTRL_DD
- IOC_CTRL_DE
- IOC_CTRL_NC
- IOC_CTRL_RM
- IOC_CTRL_TC
- IOC_DISGPU_PWR_DOWN_EN
- IOC_ERR
- IOC_E_DETACH
- IOC_E_DISABLE
- IOC_E_DISABLED
- IOC_E_ENABLE
- IOC_E_ENABLED
- IOC_E_FWRSP_GETATTR
- IOC_E_HBFAIL
- IOC_E_HWERROR
- IOC_E_HWFAILED
- IOC_E_PFFAILED
- IOC_E_RESET
- IOC_E_TIMEOUT
- IOC_FCLASS
- IOC_FIQMASK
- IOC_FIQREQ
- IOC_FIQSTAT
- IOC_FUNC_ID
- IOC_IBASE
- IOC_IDLE
- IOC_IMASK
- IOC_IN
- IOC_INIT_FRAME_SIZE
- IOC_INOUT
- IOC_IOCmd_Cfg
- IOC_IOCmd_Cfg_TE
- IOC_IOCmd_Offset
- IOC_IOPT_CacheInvd
- IOC_IOPT_CacheInvd_Busy
- IOC_IOPT_CacheInvd_IOPTE_Mask
- IOC_IOPT_CacheInvd_NE_Mask
- IOC_IOST_Origin
- IOC_IOST_Origin_E
- IOC_IOST_Origin_HL
- IOC_IOST_Origin_HW
- IOC_IO_ExcpMask
- IOC_IO_ExcpMask_PFE
- IOC_IO_ExcpMask_SFE
- IOC_IO_ExcpStat
- IOC_IO_ExcpStat_ADDR_Mask
- IOC_IO_ExcpStat_IOID_Mask
- IOC_IO_ExcpStat_RW_Mask
- IOC_IO_ExcpStat_SPF_Mask
- IOC_IO_ExcpStat_SPF_P
- IOC_IO_ExcpStat_SPF_S
- IOC_IO_ExcpStat_V
- IOC_IRQCLRA
- IOC_IRQMASKA
- IOC_IRQMASKB
- IOC_IRQREQA
- IOC_IRQREQB
- IOC_IRQSTATA
- IOC_IRQSTATB
- IOC_KARTRX
- IOC_KARTTX
- IOC_LOGINFO_CODE_MASK
- IOC_LOGINFO_CODE_SHIFT
- IOC_LOGINFO_ORIGINATOR_IOP
- IOC_LOGINFO_ORIGINATOR_IR
- IOC_LOGINFO_ORIGINATOR_MASK
- IOC_LOGINFO_ORIGINATOR_PL
- IOC_LOGINFO_PREFIX_IOP
- IOC_LOGINFO_PREFIX_IR
- IOC_LOGINFO_PREFIX_PL
- IOC_LOST
- IOC_NVRAM_GET_OFFSET
- IOC_NVRAM_SYNC
- IOC_OPAL_ACTIVATE_LSP
- IOC_OPAL_ACTIVATE_USR
- IOC_OPAL_ADD_USR_TO_LR
- IOC_OPAL_ENABLE_DISABLE_MBR
- IOC_OPAL_ERASE_LR
- IOC_OPAL_LOCK_UNLOCK
- IOC_OPAL_LR_SETUP
- IOC_OPAL_MBR_DONE
- IOC_OPAL_PSID_REVERT_TPR
- IOC_OPAL_REVERT_TPR
- IOC_OPAL_SAVE
- IOC_OPAL_SECURE_ERASE_LR
- IOC_OPAL_SET_PW
- IOC_OPAL_TAKE_OWNERSHIP
- IOC_OPAL_WRITE_SHADOW_MBR
- IOC_OPERATIONAL_WAIT_COUNT
- IOC_OUT
- IOC_PAGE_SHIFT
- IOC_PAGE_SIZE
- IOC_PCOM
- IOC_PDIR_BASE
- IOC_PR_CLEAR
- IOC_PR_PREEMPT
- IOC_PR_PREEMPT_ABORT
- IOC_PR_REGISTER
- IOC_PR_RELEASE
- IOC_PR_RESERVE
- IOC_P_NBR
- IOC_ROPE0_CFG
- IOC_ROPE_AO
- IOC_RUNNING
- IOC_Reg_Size
- IOC_SCAN_CHAN_NODEV
- IOC_SCAN_CHAN_OFFSET
- IOC_SECT_TO_PAGE_SHIFT
- IOC_STOP
- IOC_T0CNTH
- IOC_T0CNTL
- IOC_T0GO
- IOC_T0LATCH
- IOC_T0LTCHH
- IOC_T0LTCHL
- IOC_T1CNTH
- IOC_T1CNTL
- IOC_T1GO
- IOC_T1LATCH
- IOC_T1LTCHH
- IOC_T1LTCHL
- IOC_T2CNTH
- IOC_T2CNTL
- IOC_T2GO
- IOC_T2LATCH
- IOC_T2LTCHH
- IOC_T2LTCHL
- IOC_T3CNTH
- IOC_T3CNTL
- IOC_T3GO
- IOC_T3LATCH
- IOC_T3LTCHH
- IOC_T3LTCHL
- IOC_TCNFG
- IOD
- IODACK_MARK
- IODATA
- IODATA_PRODUCT_ID
- IODATA_PRODUCT_ID_RSAQ5
- IODATA_VENDOR_ID
- IODA_INVALID_M64
- IODA_INVALID_PE
- IODCR
- IODESC_ENT
- IODEV_CPUIF
- IODEV_DIST
- IODEV_ITS
- IODEV_NO
- IODEV_REDIST
- IODR
- IODREQ_MARK
- IODRIVEA
- IODRR
- IODWR
- IOD_subpacket
- IOER
- IOESR
- IOE_DIRECT0
- IOE_DIRECT0_IDX
- IOE_DIRECT1
- IOE_DIRECT1_IDX
- IOE_EREAD0
- IOE_EREAD0_IDX
- IOE_EREAD1
- IOE_EREAD1_IDX
- IOE_EWRITE0
- IOE_EWRITE0_IDX
- IOE_EWRITE1
- IOE_EWRITE1_IDX
- IOE_RAC
- IOE_RAC_IDX
- IOE_RAD
- IOE_RAD_IDX
- IOE_RAI
- IOE_RAI_IDX
- IOE_RAS
- IOE_RAS_IDX
- IOE_READ
- IOE_READ_IDX
- IOE_STAT
- IOE_WRITE
- IOE_WRITE_IDX
- IOFMSTRWAUX
- IOFUNC_IND
- IOFUNC_IO
- IOFUNC_MEMIO
- IOHC0_BASE__INST0_SEG0
- IOHC0_BASE__INST0_SEG1
- IOHC0_BASE__INST0_SEG2
- IOHC0_BASE__INST0_SEG3
- IOHC0_BASE__INST0_SEG4
- IOHC0_BASE__INST1_SEG0
- IOHC0_BASE__INST1_SEG1
- IOHC0_BASE__INST1_SEG2
- IOHC0_BASE__INST1_SEG3
- IOHC0_BASE__INST1_SEG4
- IOHC0_BASE__INST2_SEG0
- IOHC0_BASE__INST2_SEG1
- IOHC0_BASE__INST2_SEG2
- IOHC0_BASE__INST2_SEG3
- IOHC0_BASE__INST2_SEG4
- IOHC0_BASE__INST3_SEG0
- IOHC0_BASE__INST3_SEG1
- IOHC0_BASE__INST3_SEG2
- IOHC0_BASE__INST3_SEG3
- IOHC0_BASE__INST3_SEG4
- IOHC0_BASE__INST4_SEG0
- IOHC0_BASE__INST4_SEG1
- IOHC0_BASE__INST4_SEG2
- IOHC0_BASE__INST4_SEG3
- IOHC0_BASE__INST4_SEG4
- IOHC0_BASE__INST5_SEG0
- IOHC0_BASE__INST5_SEG1
- IOHC0_BASE__INST5_SEG2
- IOHC0_BASE__INST5_SEG3
- IOHC0_BASE__INST5_SEG4
- IOHC0_BASE__INST6_SEG0
- IOHC0_BASE__INST6_SEG1
- IOHC0_BASE__INST6_SEG2
- IOHC0_BASE__INST6_SEG3
- IOHC0_BASE__INST6_SEG4
- IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN_MASK
- IOHC_AER_CNTL__CFG_IOHC_AER_COMPLIANCE_EN__SHIFT
- IOHC_BASE__INST0_SEG0
- IOHC_BASE__INST0_SEG1
- IOHC_BASE__INST0_SEG2
- IOHC_BASE__INST0_SEG3
- IOHC_BASE__INST0_SEG4
- IOHC_BASE__INST1_SEG0
- IOHC_BASE__INST1_SEG1
- IOHC_BASE__INST1_SEG2
- IOHC_BASE__INST1_SEG3
- IOHC_BASE__INST1_SEG4
- IOHC_BASE__INST2_SEG0
- IOHC_BASE__INST2_SEG1
- IOHC_BASE__INST2_SEG2
- IOHC_BASE__INST2_SEG3
- IOHC_BASE__INST2_SEG4
- IOHC_BASE__INST3_SEG0
- IOHC_BASE__INST3_SEG1
- IOHC_BASE__INST3_SEG2
- IOHC_BASE__INST3_SEG3
- IOHC_BASE__INST3_SEG4
- IOHC_BASE__INST4_SEG0
- IOHC_BASE__INST4_SEG1
- IOHC_BASE__INST4_SEG2
- IOHC_BASE__INST4_SEG3
- IOHC_BASE__INST4_SEG4
- IOHC_FEATURE_CNTL2__CrsStatus_MASK
- IOHC_FEATURE_CNTL2__CrsStatus__SHIFT
- IOHC_FEATURE_CNTL2__NMI_status_MASK
- IOHC_FEATURE_CNTL2__NMI_status__SHIFT
- IOHC_FEATURE_CNTL2__NP_DMA_DROPPED_MASK
- IOHC_FEATURE_CNTL2__NP_DMA_DROPPED__SHIFT
- IOHC_FEATURE_CNTL2__P_DMA_DROPPED_MASK
- IOHC_FEATURE_CNTL2__P_DMA_DROPPED__SHIFT
- IOHC_FEATURE_CNTL2__SErr_status_MASK
- IOHC_FEATURE_CNTL2__SErr_status__SHIFT
- IOHC_FEATURE_CNTL__HpPmpme_DevID_En_MASK
- IOHC_FEATURE_CNTL__HpPmpme_DevID_En__SHIFT
- IOHC_FEATURE_CNTL__IOHC_ARCH_MODE_MASK
- IOHC_FEATURE_CNTL__IOHC_ARCH_MODE__SHIFT
- IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED_MASK
- IOHC_FEATURE_CNTL__IOHC_ARI_SUPPORTED__SHIFT
- IOHC_FEATURE_CNTL__IOHC_dGPU_MODE_MASK
- IOHC_FEATURE_CNTL__IOHC_dGPU_MODE__SHIFT
- IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL_MASK
- IOHC_FEATURE_CNTL__MISC_FEATURE_CNTL__SHIFT
- IOHC_FEATURE_CNTL__P2P_mode_MASK
- IOHC_FEATURE_CNTL__P2P_mode__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__CG_OFF_HYSTERESIS__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK0__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK1__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK2__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK3__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK4__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK5__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK6__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK7__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK8__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9_MASK
- IOHC_GLUE_CG_LCLK_CTRL_0__SOFT_OVERRIDE_CLK9__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK0__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK1__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK2__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK3__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK4__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK5__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK6__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK7__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK8__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9_MASK
- IOHC_GLUE_CG_LCLK_CTRL_1__SOFT_OVERRIDE_CLK9__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK0__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK1__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK2__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK3__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK4__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK5__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK6__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK7__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK8__SHIFT
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9_MASK
- IOHC_GLUE_CG_LCLK_CTRL_2__SOFT_OVERRIDE_CLK9__SHIFT
- IOHC_HWID
- IOHC_INTERRUPT_EOI__NMI_EOI_MASK
- IOHC_INTERRUPT_EOI__NMI_EOI__SHIFT
- IOHC_INTERRUPT_EOI__SCI_EOI_MASK
- IOHC_INTERRUPT_EOI__SCI_EOI__SHIFT
- IOHC_INTERRUPT_EOI__SMI_EOI_MASK
- IOHC_INTERRUPT_EOI__SMI_EOI__SHIFT
- IOHC_INTR_CNTL__NMI_DEST_ctrl_MASK
- IOHC_INTR_CNTL__NMI_DEST_ctrl__SHIFT
- IOHC_P2P_CNTL__DLDownResetEn_MASK
- IOHC_P2P_CNTL__DLDownResetEn__SHIFT
- IOHC_PCIE_CRS_Count__CrsDelayCount_MASK
- IOHC_PCIE_CRS_Count__CrsDelayCount__SHIFT
- IOHC_PCIE_CRS_Count__CrsLimitCount_MASK
- IOHC_PCIE_CRS_Count__CrsLimitCount__SHIFT
- IOHC_PERF_CNTL__EVENT0_SEL_MASK
- IOHC_PERF_CNTL__EVENT0_SEL__SHIFT
- IOHC_PERF_CNTL__EVENT1_SEL_MASK
- IOHC_PERF_CNTL__EVENT1_SEL__SHIFT
- IOHC_PERF_CNTL__EVENT2_SEL_MASK
- IOHC_PERF_CNTL__EVENT2_SEL__SHIFT
- IOHC_PERF_CNTL__EVENT3_SEL_MASK
- IOHC_PERF_CNTL__EVENT3_SEL__SHIFT
- IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER_MASK
- IOHC_PERF_COUNT0_UPPER__COUNTER0_UPPER__SHIFT
- IOHC_PERF_COUNT0__COUNTER0_MASK
- IOHC_PERF_COUNT0__COUNTER0__SHIFT
- IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER_MASK
- IOHC_PERF_COUNT1_UPPER__COUNTER1_UPPER__SHIFT
- IOHC_PERF_COUNT1__COUNTER1_MASK
- IOHC_PERF_COUNT1__COUNTER1__SHIFT
- IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER_MASK
- IOHC_PERF_COUNT2_UPPER__COUNTER2_UPPER__SHIFT
- IOHC_PERF_COUNT2__COUNTER2_MASK
- IOHC_PERF_COUNT2__COUNTER2__SHIFT
- IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER_MASK
- IOHC_PERF_COUNT3_UPPER__COUNTER3_UPPER__SHIFT
- IOHC_PERF_COUNT3__COUNTER3_MASK
- IOHC_PERF_COUNT3__COUNTER3__SHIFT
- IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN_MASK
- IOHC_PGMST_CNTL__CFG_FW_PG_EXIT_EN__SHIFT
- IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK
- IOHC_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT
- IOHC_PGMST_CNTL__CFG_PG_EN_MASK
- IOHC_PGMST_CNTL__CFG_PG_EN__SHIFT
- IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK
- IOHC_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT
- IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK
- IOHC_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT
- IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE_MASK
- IOHC_PIN_CNTL__NMI_SYNCFLOOD_PIN_MODE__SHIFT
- IOHC_QOS_CONTROL__VC0QoSPriority_MASK
- IOHC_QOS_CONTROL__VC0QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC1QoSPriority_MASK
- IOHC_QOS_CONTROL__VC1QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC2QoSPriority_MASK
- IOHC_QOS_CONTROL__VC2QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC3QoSPriority_MASK
- IOHC_QOS_CONTROL__VC3QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC4QoSPriority_MASK
- IOHC_QOS_CONTROL__VC4QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC5QoSPriority_MASK
- IOHC_QOS_CONTROL__VC5QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC6QoSPriority_MASK
- IOHC_QOS_CONTROL__VC6QoSPriority__SHIFT
- IOHC_QOS_CONTROL__VC7QoSPriority_MASK
- IOHC_QOS_CONTROL__VC7QoSPriority__SHIFT
- IOHC_REFCLK_MODE__MODE_100MHZ_MASK
- IOHC_REFCLK_MODE__MODE_100MHZ__SHIFT
- IOHC_REFCLK_MODE__MODE_25MHZ_MASK
- IOHC_REFCLK_MODE__MODE_25MHZ__SHIFT
- IOHC_REFCLK_MODE__MODE_27MHZ_MASK
- IOHC_REFCLK_MODE__MODE_27MHZ__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client0__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client1__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client2__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client3__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client4__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client5__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client6__SHIFT
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7_MASK
- IOHC_REQDECODE_OVERRIDE__ReqDecodeOverride_Client7__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client0__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client1__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client2__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client3__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client4__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client5__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client6__SHIFT
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7_MASK
- IOHC_RSPDECODE_OVERRIDE__RspDecodeOverride_Client7__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client0__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client1__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client2__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client3__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client4__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client5__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client6__SHIFT
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7_MASK
- IOHC_RSPPASSPW_OVERRIDE__RspPassPWOverride_Client7__SHIFT
- IOHC_SDP_PARITY_CONTROL__SDP_ParityDis_MASK
- IOHC_SDP_PARITY_CONTROL__SDP_ParityDis__SHIFT
- IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq_MASK
- IOHC_SDP_PORT_CONTROL__DMAEnableEarlyClkReq__SHIFT
- IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq_MASK
- IOHC_SDP_PORT_CONTROL__HostEnableEarlyClkReq__SHIFT
- IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis_MASK
- IOHC_SDP_PORT_CONTROL__Port_Disconnect_Hysteresis__SHIFT
- IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis_MASK
- IOHC_SDP_PORT_CONTROL__SDF_Port_Disconnect_Real_Time_Hysteresis__SHIFT
- IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__IOHC_SION_Client0_DataPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__IOHC_SION_Client0_DataPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client0_ReqPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client0_ReqPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__IOHC_SION_Client1_DataPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__IOHC_SION_Client1_DataPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client1_ReqPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client1_ReqPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__IOHC_SION_Client2_DataPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__IOHC_SION_Client2_DataPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client2_ReqPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client2_ReqPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__IOHC_SION_Client3_DataPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__IOHC_SION_Client3_DataPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client3_ReqPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client3_ReqPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__IOHC_SION_Client4_DataPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__IOHC_SION_Client4_DataPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__IOHC_SION_Client4_ReqPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__IOHC_SION_Client4_ReqPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_MASK
- IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower__SHIFT
- IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_MASK
- IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__IOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper__SHIFT
- IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold_MASK
- IOHC_SION_LiveLock_WatchDog_Threshold__IOHC_SION_LiveLock_WatchDog_Threshold__SHIFT
- IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client0_Req_BurstTarget_Lower__IOHC_SION_S0_Client0_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client0_Req_BurstTarget_Upper__IOHC_SION_S0_Client0_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client0_Req_TimeSlot_Lower__IOHC_SION_S0_Client0_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client0_Req_TimeSlot_Upper__IOHC_SION_S0_Client0_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client1_Req_BurstTarget_Lower__IOHC_SION_S0_Client1_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client1_Req_BurstTarget_Upper__IOHC_SION_S0_Client1_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client1_Req_TimeSlot_Lower__IOHC_SION_S0_Client1_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client1_Req_TimeSlot_Upper__IOHC_SION_S0_Client1_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client2_Req_BurstTarget_Lower__IOHC_SION_S0_Client2_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client2_Req_BurstTarget_Upper__IOHC_SION_S0_Client2_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client2_Req_TimeSlot_Lower__IOHC_SION_S0_Client2_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client2_Req_TimeSlot_Upper__IOHC_SION_S0_Client2_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client3_Req_BurstTarget_Lower__IOHC_SION_S0_Client3_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client3_Req_BurstTarget_Upper__IOHC_SION_S0_Client3_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client3_Req_TimeSlot_Lower__IOHC_SION_S0_Client3_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client3_Req_TimeSlot_Upper__IOHC_SION_S0_Client3_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client4_Req_BurstTarget_Lower__IOHC_SION_S0_Client4_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client4_Req_BurstTarget_Upper__IOHC_SION_S0_Client4_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client4_Req_TimeSlot_Lower__IOHC_SION_S0_Client4_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client4_Req_TimeSlot_Upper__IOHC_SION_S0_Client4_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client0_Req_BurstTarget_Lower__IOHC_SION_S1_Client0_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client0_Req_BurstTarget_Upper__IOHC_SION_S1_Client0_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client0_Req_TimeSlot_Lower__IOHC_SION_S1_Client0_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client0_Req_TimeSlot_Upper__IOHC_SION_S1_Client0_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client1_Req_BurstTarget_Lower__IOHC_SION_S1_Client1_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client1_Req_BurstTarget_Upper__IOHC_SION_S1_Client1_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client1_Req_TimeSlot_Lower__IOHC_SION_S1_Client1_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client1_Req_TimeSlot_Upper__IOHC_SION_S1_Client1_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client2_Req_BurstTarget_Lower__IOHC_SION_S1_Client2_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client2_Req_BurstTarget_Upper__IOHC_SION_S1_Client2_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client2_Req_TimeSlot_Lower__IOHC_SION_S1_Client2_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client2_Req_TimeSlot_Upper__IOHC_SION_S1_Client2_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client3_Req_BurstTarget_Lower__IOHC_SION_S1_Client3_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client3_Req_BurstTarget_Upper__IOHC_SION_S1_Client3_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client3_Req_TimeSlot_Lower__IOHC_SION_S1_Client3_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client3_Req_TimeSlot_Upper__IOHC_SION_S1_Client3_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client4_Req_BurstTarget_Lower__IOHC_SION_S1_Client4_Req_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client4_Req_BurstTarget_Upper__IOHC_SION_S1_Client4_Req_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client4_Req_TimeSlot_Lower__IOHC_SION_S1_Client4_Req_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client4_Req_TimeSlot_Upper__IOHC_SION_S1_Client4_Req_TimeSlot_Upper__SHIFT
- IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_MASK
- IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower__SHIFT
- IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_MASK
- IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__IOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper__SHIFT
- IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_MASK
- IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower__SHIFT
- IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_MASK
- IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__IOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper__SHIFT
- IOHC_SMN_MASTER_CNTL__SmnErrRspMap_MASK
- IOHC_SMN_MASTER_CNTL__SmnErrRspMap__SHIFT
- IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus_MASK
- IOHC_SMN_MASTER_STATUS__SmnPoisonErrStatus__SHIFT
- IOHC_USERBIT_BYPASS__Userbit_Bypass_MASK
- IOHC_USERBIT_BYPASS__Userbit_Bypass__SHIFT
- IOH_EDGE_BOTH
- IOH_EDGE_FALLING
- IOH_EDGE_RISING
- IOH_IM_MASK
- IOH_IRQ_BASE
- IOH_LEVEL_H
- IOH_LEVEL_L
- IOIER
- IOIIDATA_IOII
- IOIIDATA_MINT5EN
- IOIIDATA_PACKEN
- IOIIDATA_PREFETCHEN
- IOIIDATA_SMINT5L
- IOINTSEL
- IOIR
- IOIS16
- IOIS16_MARK
- IOLARGE_MASK
- IOLARGE_SHIFT
- IOLARGE_SIZE
- IOLIMH
- IOLIML
- IOMAP
- IOMAP_DELALLOC
- IOMAP_DIO_COW
- IOMAP_DIO_DIRTY
- IOMAP_DIO_NEED_SYNC
- IOMAP_DIO_UNWRITTEN
- IOMAP_DIO_WRITE
- IOMAP_DIO_WRITE_FUA
- IOMAP_DIRECT
- IOMAP_FAULT
- IOMAP_FULL_CACHING
- IOMAP_F_BUFFER_HEAD
- IOMAP_F_DIRTY
- IOMAP_F_GFS2_BOUNDARY
- IOMAP_F_MERGED
- IOMAP_F_NEW
- IOMAP_F_PRIVATE
- IOMAP_F_SHARED
- IOMAP_F_SIZE_CHANGED
- IOMAP_HOLE
- IOMAP_INLINE
- IOMAP_MAPPED
- IOMAP_MAX_ORDER
- IOMAP_NOCACHE_NONSER
- IOMAP_NOCACHE_SER
- IOMAP_NOWAIT
- IOMAP_NO_COPYBACK
- IOMAP_NULL_ADDR
- IOMAP_REPORT
- IOMAP_UNWRITTEN
- IOMAP_WRITE
- IOMAP_WRITETHROUGH
- IOMAP_ZERO
- IOMAPflag
- IOMASK
- IOMB_SIZE_SPC
- IOMB_SIZE_SPCV
- IOMD_BASE
- IOMD_CONTROL
- IOMD_CURSCUR
- IOMD_CURSINIT
- IOMD_DMAEXT
- IOMD_DMAMASK
- IOMD_DMAREQ
- IOMD_DMASTAT
- IOMD_DMATCR
- IOMD_DMA_BOUNDARY
- IOMD_DRAMCR
- IOMD_ECTCR
- IOMD_FIQMASK
- IOMD_FIQREQ
- IOMD_FIQSTAT
- IOMD_FSIZE
- IOMD_ID0
- IOMD_ID1
- IOMD_IO0CR
- IOMD_IO0CURA
- IOMD_IO0CURB
- IOMD_IO0ENDA
- IOMD_IO0ENDB
- IOMD_IO0ST
- IOMD_IO1CR
- IOMD_IO1CURA
- IOMD_IO1CURB
- IOMD_IO1ENDA
- IOMD_IO1ENDB
- IOMD_IO1ST
- IOMD_IO2CR
- IOMD_IO2CURA
- IOMD_IO2CURB
- IOMD_IO2ENDA
- IOMD_IO2ENDB
- IOMD_IO2ST
- IOMD_IO3CR
- IOMD_IO3CURA
- IOMD_IO3CURB
- IOMD_IO3ENDA
- IOMD_IO3ENDB
- IOMD_IO3ST
- IOMD_IOTCR
- IOMD_IRQCLRA
- IOMD_IRQMASKA
- IOMD_IRQMASKB
- IOMD_IRQREQA
- IOMD_IRQREQB
- IOMD_IRQSTATA
- IOMD_IRQSTATB
- IOMD_KARTRX
- IOMD_KARTTX
- IOMD_KCTRL
- IOMD_MOUSEX
- IOMD_MOUSEY
- IOMD_REFCR
- IOMD_ROMCR0
- IOMD_ROMCR1
- IOMD_SD0CR
- IOMD_SD0CURA
- IOMD_SD0CURB
- IOMD_SD0ENDA
- IOMD_SD0ENDB
- IOMD_SD0ST
- IOMD_SD1CR
- IOMD_SD1CURA
- IOMD_SD1CURB
- IOMD_SD1ENDA
- IOMD_SD1ENDB
- IOMD_SD1ST
- IOMD_T0CNTH
- IOMD_T0CNTL
- IOMD_T0GO
- IOMD_T0LATCH
- IOMD_T0LTCHH
- IOMD_T0LTCHL
- IOMD_T1CNTH
- IOMD_T1CNTL
- IOMD_T1GO
- IOMD_T1LATCH
- IOMD_T1LTCHH
- IOMD_T1LTCHL
- IOMD_VERSION
- IOMD_VIDCR
- IOMD_VIDCUR
- IOMD_VIDEND
- IOMD_VIDINIT
- IOMD_VIDSTART
- IOMEM
- IOMEMBASE
- IOMEMSIZE
- IOMEM_ERR_PTR
- IOMEM_RESOURCE_END
- IOMEM_RESOURCE_START
- IOMGRCOLD_RESET
- IOMMU_ACPI_FINISHED
- IOMMU_ADDR_MASK
- IOMMU_AFSR_BE
- IOMMU_AFSR_ERR
- IOMMU_AFSR_FAV
- IOMMU_AFSR_LE
- IOMMU_AFSR_ME
- IOMMU_AFSR_RD
- IOMMU_AFSR_RESV
- IOMMU_AFSR_S
- IOMMU_AFSR_SIZE
- IOMMU_AFSR_TO
- IOMMU_CACHE
- IOMMU_CACHE_INHIBIT
- IOMMU_CAP_CACHE_COHERENCY
- IOMMU_CAP_EFR
- IOMMU_CAP_INTR_REMAP
- IOMMU_CAP_IOTLB
- IOMMU_CAP_NOEXEC
- IOMMU_CAP_NPCACHE
- IOMMU_CMDLINE_DISABLED
- IOMMU_CMD_LINE_DMA_API
- IOMMU_CONTROL
- IOMMU_CTRL_ENAB
- IOMMU_CTRL_IMPL
- IOMMU_CTRL_RNGE
- IOMMU_CTRL_VERS
- IOMMU_DETECTED
- IOMMU_DEV_FEAT_AUX
- IOMMU_DEV_FEAT_SVA
- IOMMU_DMA_IOVA_COOKIE
- IOMMU_DMA_MSI_COOKIE
- IOMMU_DMA_OPS
- IOMMU_DOMAIN_BLOCKED
- IOMMU_DOMAIN_DMA
- IOMMU_DOMAIN_IDENTITY
- IOMMU_DOMAIN_UNMANAGED
- IOMMU_DRAMDIAG
- IOMMU_DRAM_VALID
- IOMMU_DT_BAD
- IOMMU_DT_INVALID
- IOMMU_DT_MASK
- IOMMU_DT_VALID
- IOMMU_EFR_GASUP_SHIFT
- IOMMU_EFR_MSICAPMMIOSUP_SHIFT
- IOMMU_EFR_XTSUP_SHIFT
- IOMMU_ENABLED
- IOMMU_ENTRIES
- IOMMU_ERROR_CODE
- IOMMU_FAULT_DMA_UNRECOV
- IOMMU_FAULT_PAGE_REQ
- IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE
- IOMMU_FAULT_PAGE_REQUEST_PASID_VALID
- IOMMU_FAULT_PAGE_REQUEST_PRIV_DATA
- IOMMU_FAULT_PERM_EXEC
- IOMMU_FAULT_PERM_PRIV
- IOMMU_FAULT_PERM_READ
- IOMMU_FAULT_PERM_WRITE
- IOMMU_FAULT_READ
- IOMMU_FAULT_REASON_ACCESS
- IOMMU_FAULT_REASON_BAD_PASID_ENTRY
- IOMMU_FAULT_REASON_OOR_ADDRESS
- IOMMU_FAULT_REASON_PASID_FETCH
- IOMMU_FAULT_REASON_PASID_INVALID
- IOMMU_FAULT_REASON_PERMISSION
- IOMMU_FAULT_REASON_PTE_FETCH
- IOMMU_FAULT_REASON_UNKNOWN
- IOMMU_FAULT_REASON_WALK_EABT
- IOMMU_FAULT_UNRECOV_ADDR_VALID
- IOMMU_FAULT_UNRECOV_FETCH_ADDR_VALID
- IOMMU_FAULT_UNRECOV_PASID_VALID
- IOMMU_FAULT_WRITE
- IOMMU_FEAT_GASUP_SHIFT
- IOMMU_FINISH_IF_DETECTED
- IOMMU_FLUSH
- IOMMU_FULL_BLOCK
- IOMMU_FWSPEC_PCI_RC_ATS
- IOMMU_GROUP_ATTR
- IOMMU_GROUP_NOTIFY_ADD_DEVICE
- IOMMU_GROUP_NOTIFY_BIND_DRIVER
- IOMMU_GROUP_NOTIFY_BOUND_DRIVER
- IOMMU_GROUP_NOTIFY_DEL_DEVICE
- IOMMU_GROUP_NOTIFY_UNBIND_DRIVER
- IOMMU_GROUP_NOTIFY_UNBOUND_DRIVER
- IOMMU_HAS_LARGE_POOL
- IOMMU_INIT
- IOMMU_INITIALIZED
- IOMMU_INIT_ERROR
- IOMMU_INIT_FINISH
- IOMMU_INIT_POST
- IOMMU_INIT_POST_FINISH
- IOMMU_INTERRUPTS_EN
- IOMMU_INVALID_PTE
- IOMMU_IVRS_DETECTED
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDO__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPDV__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0__Reserved__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1__Reserved__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT
- IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved_MASK
- IOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL__Reserved__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0__CPD_REQADDR_LO__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1__CPD_REQADDR_HI__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDO__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPDV__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__CPD_REQSTREAM_ID__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0__Reserved__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1__Reserved__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__CPD_SUP__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL__Reserved__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__AbortPreTrans__SHIFT
- IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved_MASK
- IOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL__Reserved__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK
- IOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT
- IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK
- IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT
- IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK
- IOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT
- IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK
- IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT
- IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK
- IOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK
- IOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT
- IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK
- IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT
- IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK
- IOMMU_L1_IOAGR_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT
- IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0_MASK
- IOMMU_L1_IOAGR_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT
- IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved_MASK
- IOMMU_L1_IOAGR_L1_CLKCNTRL_0__reserved__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIR_only__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__CacheIW_only__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__Fragment_dis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1Banks__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1Entries__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__L2Credits__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__RESERVED__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved0__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__Reserved1__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_0__Unfilter_dis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__CacheByPass__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheInvAllEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1CacheParityEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1DTEDis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1Order_en__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1ParityEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__RESERVED__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__Select_timeout_pulse__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__Snd_filter_dis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_1__WQ_EntryDis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__CPD_RESP_MODE__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1Disable__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1SDPParityEn__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_2__RESERVED__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_4__RESERVED__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT
- IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED_MASK
- IOMMU_L1_IOAGR_L1_CNTRL_5__RESERVED__SHIFT
- IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO_MASK
- IOMMU_L1_IOAGR_L1_ECO_CNTRL__L1_ECO__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_CNTRL__Reserved__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved_MASK
- IOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL__reserved__SHIFT
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved_MASK
- IOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL__reserved__SHIFT
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK
- IOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1_MASK
- IOMMU_L1_IOAGR_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK
- IOMMU_L1_IOAGR_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK
- IOMMU_L1_IOAGR_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK
- IOMMU_L1_IOAGR_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT
- IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK
- IOMMU_L1_IOAGR_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK
- IOMMU_L1_IOAGR_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core_MASK
- IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Core__SHIFT
- IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port_MASK
- IOMMU_L1_IOAGR_L1_SB_LOCATION__SBlocated_Port__SHIFT
- IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK
- IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT
- IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK
- IOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK
- IOMMU_L1_IOAGR_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus0__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus1__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus2__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus3__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus4__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus5__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus6__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus7__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus8__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_0__EntryStatus9__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus10__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus11__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus12__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus13__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus14__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus15__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus16__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus17__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus18__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_1__EntryStatus19__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus20__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus21__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus22__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus23__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus24__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus25__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus26__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus27__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus28__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_2__EntryStatus29__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus30__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__EntryStatus31__SHIFT
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status_MASK
- IOMMU_L1_IOAGR_L1_WQ_STATUS_3__Invalidation_status__SHIFT
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn_MASK
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallHRT1RspEn__SHIFT
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn_MASK
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallNPRspEn__SHIFT
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn_MASK
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallPRspEn__SHIFT
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn_MASK
- IOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control__StallUpWrRspEn__SHIFT
- IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn_MASK
- IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallNPRspEn__SHIFT
- IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn_MASK
- IOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control__StallPRspEn__SHIFT
- IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS_MASK
- IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT
- IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS_MASK
- IOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL__L1_PG_STATUS__SHIFT
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer_MASK
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_allow_timer__SHIFT
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer_MASK
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATS_Resp_delay_timer__SHIFT
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en_MASK
- IOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0__L1_ATSdely_on_PPRAutoResp_en__SHIFT
- IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0_MASK
- IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_0__SHIFT
- IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1_MASK
- IOMMU_L1_PCIE0_L1_BANK_DISABLE_0__L1CacheLineDis_1__SHIFT
- IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0_MASK
- IOMMU_L1_PCIE0_L1_BANK_SEL_0__L1CacheBankSel_0__SHIFT
- IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CACHE_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CLKGATE_HYSTERESIS__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_CPSLV_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMARSP_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_DMA_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTREQ_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_HOSTRSP_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_L2_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_MEMORY_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_PERF_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__L1_REG_CLKGATE_EN__SHIFT
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved_MASK
- IOMMU_L1_PCIE0_L1_CLKCNTRL_0__reserved__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIR_only__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__CacheIW_only__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__Fragment_dis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1Banks__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1Entries__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1ErrEventDetectDis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1ForceHostRspPassPWHigh__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L1InterruptHalfDwDis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__L2Credits__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__RESERVED__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved0__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__Reserved1__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_0__Unfilter_dis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__CacheByPass__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheInvAllEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1CacheParityEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1DTEDis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1DmaUseChainAll_En__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1Order_en__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1ParityEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1StrictVCOrder_En__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_interleave__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__L1_cache_sel_reqid__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__Pretrans_noVA_filterEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__RESERVED__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__Select_timeout_pulse__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__Snd_filter_dis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__UnTrans_2M_filterEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_1__WQ_EntryDis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__CPD_RESP_MODE__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_IntInv__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__FlushVC_HRT1_Inv__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1ATSDataErrorSignalEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1ConsumedDataErrorSignalEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1Disable__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1NonConsumedDataErrorSignalEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1SDPParityEn__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__L1_abrt_ats_dis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__MSI_to_HT_remap_dis__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_2__RESERVED__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_3__ATS_tlbinv_pulse_width__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_4__ATS_multiple_resp_en__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_4__AtsRsp_send_mem_type_en__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_4__IntGfx_UnitID_Val__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_4__RESERVED__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_4__Timeout_pulse_ext_En__SHIFT
- IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED_MASK
- IOMMU_L1_PCIE0_L1_CNTRL_5__RESERVED__SHIFT
- IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO_MASK
- IOMMU_L1_PCIE0_L1_ECO_CNTRL__L1_ECO__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Debug_sticky_bits__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_CNTRL__Reserved__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_DTE_seg_W__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_EFR_SUP__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_GT_SUP_W__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__L1_PPR_SUP__SHIFT
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved_MASK
- IOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL__reserved__SHIFT
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN_MASK
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_CANONICAL_ERR_EN__SHIFT
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK_MASK
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__L1_GUEST_ADDR_MSK__SHIFT
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved_MASK
- IOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL__reserved__SHIFT
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn_MASK
- IOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control__StallUpWrReqEn__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_2__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_COUNT_HI_3__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT2__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL_B__L1_PERF_EVENT3__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_0__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_COUNT_HI_1__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT0__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1_MASK
- IOMMU_L1_PCIE0_L1_PERF_CNTL__L1_PERF_EVENT1__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0_MASK
- IOMMU_L1_PCIE0_L1_PERF_COUNT_0__L1_PERF_COUNT_0__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1_MASK
- IOMMU_L1_PCIE0_L1_PERF_COUNT_1__L1_PERF_COUNT_1__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2_MASK
- IOMMU_L1_PCIE0_L1_PERF_COUNT_B0__L1_PERF_COUNT_2__SHIFT
- IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3_MASK
- IOMMU_L1_PCIE0_L1_PERF_COUNT_B1__L1_PERF_COUNT_3__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_10__L1_SD_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_DS_EN__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_IP_PGMEM_SEL__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_LS_EN__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_1__L1_SD_EN__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_2__L1_LS_thres__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_3__L1_DS_thres__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_4__L1_SD_thres__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_5__L1_LS_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_6__L1_LS_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_7__L1_DS_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_8__L1_DS_Exit_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt_MASK
- IOMMU_L1_PCIE0_L1_PGMEM_CTRL_9__L1_SD_Req_Maintain_Cnt__SHIFT
- IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core_MASK
- IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Core__SHIFT
- IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port_MASK
- IOMMU_L1_PCIE0_L1_SB_LOCATION__SBlocated_Port__SHIFT
- IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA_MASK
- IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_DMA__SHIFT
- IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST_MASK
- IOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL__HW_PG_WAKEUP_EN_HOST__SHIFT
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED_MASK
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_FLUSHRSP_MAXCRED__SHIFT
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED_MASK
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTRDRSP_MAXCRED__SHIFT
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED_MASK
- IOMMU_L1_PCIE0_L1_SDP_MAXCRED_0__L1_HOSTWRRSP_MAXCRED__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus0__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus1__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus2__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus3__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus4__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus5__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus6__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus7__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus8__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_0__EntryStatus9__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus10__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus11__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus12__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus13__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus14__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus15__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus16__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus17__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus18__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_1__EntryStatus19__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus20__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus21__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus22__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus23__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus24__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus25__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus26__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus27__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus28__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_2__EntryStatus29__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus30__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__EntryStatus31__SHIFT
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status_MASK
- IOMMU_L1_PCIE0_L1_WQ_STATUS_3__Invalidation_status__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__ISOC__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0__TLPT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__DSFXSup__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__DSSX_status__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__EVENTF__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAF__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GATS__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GA_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__GT_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HATS__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__HE_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__IA_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__NX_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PC_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPRF__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_0__XT_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__DTE_seg__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HA_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__HD_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MARCnum__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__US_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA__Reserved__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_INT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved0__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0__Reserved1__SHIFT
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0_MASK
- IOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1__Reserved0__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDID_0__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiDV_0__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0__SmiFLock_0__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDID_1__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiDV_1__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0__SmiFLock_1__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDID_2__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiDV_2__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0__SmiFLock_2__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__Reserved__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDID_3__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiDV_3__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0__SmiFLock_3__SHIFT
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved_MASK
- IOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1__Reserved__SHIFT
- IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK
- IOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT
- IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK
- IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT
- IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK
- IOMMU_L2_0_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT
- IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK
- IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
- IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
- IOMMU_L2_0_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
- IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK
- IOMMU_L2_0_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT
- IOMMU_L2_0_IOMMU_BIST__BIST_CAP_MASK
- IOMMU_L2_0_IOMMU_BIST__BIST_CAP__SHIFT
- IOMMU_L2_0_IOMMU_BIST__BIST_COMP_MASK
- IOMMU_L2_0_IOMMU_BIST__BIST_COMP__SHIFT
- IOMMU_L2_0_IOMMU_BIST__BIST_STRT_MASK
- IOMMU_L2_0_IOMMU_BIST__BIST_STRT__SHIFT
- IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK
- IOMMU_L2_0_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK
- IOMMU_L2_0_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT
- IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK
- IOMMU_L2_0_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved_MASK
- IOMMU_L2_0_IOMMU_CAP_BASE_LO__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved_MASK
- IOMMU_L2_0_IOMMU_CAP_HEADER__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1_MASK
- IOMMU_L2_0_IOMMU_CAP_MISC__Reserved1__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT
- IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved_MASK
- IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN_MASK
- IOMMU_L2_0_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS_MASK
- IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN_MASK
- IOMMU_L2_0_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN_MASK
- IOMMU_L2_0_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN_MASK
- IOMMU_L2_0_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__Reserved0_MASK
- IOMMU_L2_0_IOMMU_COMMAND__Reserved0__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__Reserved1_MASK
- IOMMU_L2_0_IOMMU_COMMAND__Reserved1__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__Reserved2_MASK
- IOMMU_L2_0_IOMMU_COMMAND__Reserved2__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__Reserved_MASK
- IOMMU_L2_0_IOMMU_COMMAND__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_COMMAND__SERR_EN_MASK
- IOMMU_L2_0_IOMMU_COMMAND__SERR_EN__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT
- IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK
- IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT
- IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID_MASK
- IOMMU_L2_0_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT
- IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK
- IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT
- IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved_MASK
- IOMMU_L2_0_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup_MASK
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK
- IOMMU_L2_0_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT
- IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK
- IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT
- IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved_MASK
- IOMMU_L2_0_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE_MASK
- IOMMU_L2_0_IOMMU_HEADER__HEADER_TYPE__SHIFT
- IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- IOMMU_L2_0_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- IOMMU_L2_0_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- IOMMU_L2_0_IOMMU_LATENCY__LATENCY_MASK
- IOMMU_L2_0_IOMMU_LATENCY__LATENCY__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK
- IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT
- IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK
- IOMMU_L2_0_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT
- IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK
- IOMMU_L2_0_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT
- IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved_MASK
- IOMMU_L2_0_IOMMU_MSI_ADDR_LO__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_64_EN__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_EN__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT
- IOMMU_L2_0_IOMMU_MSI_CAP__Reserved_MASK
- IOMMU_L2_0_IOMMU_MSI_CAP__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA_MASK
- IOMMU_L2_0_IOMMU_MSI_DATA__MSI_DATA__SHIFT
- IOMMU_L2_0_IOMMU_MSI_DATA__Reserved_MASK
- IOMMU_L2_0_IOMMU_MSI_DATA__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK
- IOMMU_L2_0_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT
- IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W_MASK
- IOMMU_L2_0_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT
- IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK
- IOMMU_L2_0_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT
- IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W_MASK
- IOMMU_L2_0_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT
- IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W_MASK
- IOMMU_L2_0_IOMMU_RANGE_W__RNG_VALID_W__SHIFT
- IOMMU_L2_0_IOMMU_RANGE_W__Reserved_MASK
- IOMMU_L2_0_IOMMU_RANGE_W__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK
- IOMMU_L2_0_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT
- IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK
- IOMMU_L2_0_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT
- IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID_MASK
- IOMMU_L2_0_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__CAP_LIST_MASK
- IOMMU_L2_0_IOMMU_STATUS__CAP_LIST__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__INT_Status_MASK
- IOMMU_L2_0_IOMMU_STATUS__INT_Status__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR_MASK
- IOMMU_L2_0_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK
- IOMMU_L2_0_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK
- IOMMU_L2_0_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK
- IOMMU_L2_0_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__Reserved1_MASK
- IOMMU_L2_0_IOMMU_STATUS__Reserved1__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__Reserved2_MASK
- IOMMU_L2_0_IOMMU_STATUS__Reserved2__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__Reserved_MASK
- IOMMU_L2_0_IOMMU_STATUS__Reserved__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- IOMMU_L2_0_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK
- IOMMU_L2_0_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK
- IOMMU_L2_0_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT
- IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID_MASK
- IOMMU_L2_0_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT
- IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK
- IOMMU_L2_0_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W_MASK
- IOMMU_L2_0_SMMU_AIDR_W__ArchMajorRev_W__SHIFT
- IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W_MASK
- IOMMU_L2_0_SMMU_AIDR_W__ArchMinorRev_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__MSI_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__PRI_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__RAS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__S1P_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__S2P_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__SEV_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__TTF_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR0_W__VMW_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__REL_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR3_W__HAD_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__OAS_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Revision_W__SHIFT
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W_MASK
- IOMMU_L2_0_SMMU_MMIO_IIDR_W__Variant_W__SHIFT
- IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK
- IOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT
- IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK
- IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT
- IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK
- IOMMU_L2_1_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT
- IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK
- IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
- IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
- IOMMU_L2_1_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
- IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK
- IOMMU_L2_1_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT
- IOMMU_L2_1_IOMMU_BIST__BIST_CAP_MASK
- IOMMU_L2_1_IOMMU_BIST__BIST_CAP__SHIFT
- IOMMU_L2_1_IOMMU_BIST__BIST_COMP_MASK
- IOMMU_L2_1_IOMMU_BIST__BIST_COMP__SHIFT
- IOMMU_L2_1_IOMMU_BIST__BIST_STRT_MASK
- IOMMU_L2_1_IOMMU_BIST__BIST_STRT__SHIFT
- IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK
- IOMMU_L2_1_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK
- IOMMU_L2_1_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT
- IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK
- IOMMU_L2_1_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved_MASK
- IOMMU_L2_1_IOMMU_CAP_BASE_LO__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved_MASK
- IOMMU_L2_1_IOMMU_CAP_HEADER__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1_MASK
- IOMMU_L2_1_IOMMU_CAP_MISC__Reserved1__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT
- IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved_MASK
- IOMMU_L2_1_IOMMU_CAP_RANGE__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN_MASK
- IOMMU_L2_1_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS_MASK
- IOMMU_L2_1_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN_MASK
- IOMMU_L2_1_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN_MASK
- IOMMU_L2_1_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN_MASK
- IOMMU_L2_1_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__Reserved0_MASK
- IOMMU_L2_1_IOMMU_COMMAND__Reserved0__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__Reserved1_MASK
- IOMMU_L2_1_IOMMU_COMMAND__Reserved1__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__Reserved2_MASK
- IOMMU_L2_1_IOMMU_COMMAND__Reserved2__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__Reserved_MASK
- IOMMU_L2_1_IOMMU_COMMAND__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_COMMAND__SERR_EN_MASK
- IOMMU_L2_1_IOMMU_COMMAND__SERR_EN__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT
- IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK
- IOMMU_L2_1_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT
- IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID_MASK
- IOMMU_L2_1_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT
- IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK
- IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT
- IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved_MASK
- IOMMU_L2_1_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup_MASK
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK
- IOMMU_L2_1_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT
- IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK
- IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT
- IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved_MASK
- IOMMU_L2_1_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE_MASK
- IOMMU_L2_1_IOMMU_HEADER__HEADER_TYPE__SHIFT
- IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- IOMMU_L2_1_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- IOMMU_L2_1_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- IOMMU_L2_1_IOMMU_LATENCY__LATENCY_MASK
- IOMMU_L2_1_IOMMU_LATENCY__LATENCY__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK
- IOMMU_L2_1_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT
- IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK
- IOMMU_L2_1_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT
- IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK
- IOMMU_L2_1_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT
- IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved_MASK
- IOMMU_L2_1_IOMMU_MSI_ADDR_LO__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_64_EN__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_EN__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT
- IOMMU_L2_1_IOMMU_MSI_CAP__Reserved_MASK
- IOMMU_L2_1_IOMMU_MSI_CAP__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA_MASK
- IOMMU_L2_1_IOMMU_MSI_DATA__MSI_DATA__SHIFT
- IOMMU_L2_1_IOMMU_MSI_DATA__Reserved_MASK
- IOMMU_L2_1_IOMMU_MSI_DATA__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK
- IOMMU_L2_1_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT
- IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W_MASK
- IOMMU_L2_1_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT
- IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK
- IOMMU_L2_1_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT
- IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W_MASK
- IOMMU_L2_1_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT
- IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W_MASK
- IOMMU_L2_1_IOMMU_RANGE_W__RNG_VALID_W__SHIFT
- IOMMU_L2_1_IOMMU_RANGE_W__Reserved_MASK
- IOMMU_L2_1_IOMMU_RANGE_W__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK
- IOMMU_L2_1_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT
- IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK
- IOMMU_L2_1_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT
- IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID_MASK
- IOMMU_L2_1_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__CAP_LIST_MASK
- IOMMU_L2_1_IOMMU_STATUS__CAP_LIST__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__INT_Status_MASK
- IOMMU_L2_1_IOMMU_STATUS__INT_Status__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR_MASK
- IOMMU_L2_1_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK
- IOMMU_L2_1_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK
- IOMMU_L2_1_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK
- IOMMU_L2_1_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__Reserved1_MASK
- IOMMU_L2_1_IOMMU_STATUS__Reserved1__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__Reserved2_MASK
- IOMMU_L2_1_IOMMU_STATUS__Reserved2__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__Reserved_MASK
- IOMMU_L2_1_IOMMU_STATUS__Reserved__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- IOMMU_L2_1_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK
- IOMMU_L2_1_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK
- IOMMU_L2_1_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT
- IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID_MASK
- IOMMU_L2_1_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT
- IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK
- IOMMU_L2_1_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W_MASK
- IOMMU_L2_1_SMMU_AIDR_W__ArchMajorRev_W__SHIFT
- IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W_MASK
- IOMMU_L2_1_SMMU_AIDR_W__ArchMinorRev_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ATS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__BTM_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__MSI_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__PRI_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__RAS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__S1P_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__S2P_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__SEV_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__TTF_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR0_W__VMW_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__REL_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR3_W__HAD_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__OAS_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Revision_W__SHIFT
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W_MASK
- IOMMU_L2_1_SMMU_MMIO_IIDR_W__Variant_W__SHIFT
- IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn_MASK
- IOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control__StallUpRdRspEn__SHIFT
- IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W_MASK
- IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_ID_W__SHIFT
- IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W_MASK
- IOMMU_L2_2_IOMMU_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_W__SHIFT
- IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID_MASK
- IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_ID__SHIFT
- IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK
- IOMMU_L2_2_IOMMU_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT
- IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE_MASK
- IOMMU_L2_2_IOMMU_BASE_CODE__BASE_CLASS_CODE__SHIFT
- IOMMU_L2_2_IOMMU_BIST__BIST_CAP_MASK
- IOMMU_L2_2_IOMMU_BIST__BIST_CAP__SHIFT
- IOMMU_L2_2_IOMMU_BIST__BIST_COMP_MASK
- IOMMU_L2_2_IOMMU_BIST__BIST_COMP__SHIFT
- IOMMU_L2_2_IOMMU_BIST__BIST_STRT_MASK
- IOMMU_L2_2_IOMMU_BIST__BIST_STRT__SHIFT
- IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE_MASK
- IOMMU_L2_2_IOMMU_CACHE_LINE__CACHE_LINE_SIZE__SHIFT
- IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR_MASK
- IOMMU_L2_2_IOMMU_CAPABILITIES_PTR__CAP_PTR__SHIFT
- IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI_MASK
- IOMMU_L2_2_IOMMU_CAP_BASE_HI__IOMMU_BASE_ADDR_HI__SHIFT
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO_MASK
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_BASE_ADDR_LO__SHIFT
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE_MASK
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__IOMMU_ENABLE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved_MASK
- IOMMU_L2_2_IOMMU_CAP_BASE_LO__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_EXT__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_ID__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_PTR__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_REV__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_CAP_TYPE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_EFR_SUP__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_HT_TUNNEL_SUP__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_IO_TLBSUP__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__IOMMU_NP_CACHE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved_MASK
- IOMMU_L2_2_IOMMU_CAP_HEADER__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC_1__DVM_MODE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_EN__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC_1__SMMUMMIO_LOCK__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_HT_ATS_RESV__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_MSI_NUM__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_PA_SIZE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__IOMMU_VA_SIZE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1_MASK
- IOMMU_L2_2_IOMMU_CAP_MISC__Reserved1__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_BUS_NUMBER__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_FIRST_DEVICE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_LAST_DEVICE__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_RNG_VALID__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__IOMMU_UNIT_ID__SHIFT
- IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved_MASK
- IOMMU_L2_2_IOMMU_CAP_RANGE__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN_MASK
- IOMMU_L2_2_IOMMU_COMMAND__BUS_MASTER_EN__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS_MASK
- IOMMU_L2_2_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN_MASK
- IOMMU_L2_2_IOMMU_COMMAND__IO_ACCESS_EN__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN_MASK
- IOMMU_L2_2_IOMMU_COMMAND__MEM_ACCESS_EN__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN_MASK
- IOMMU_L2_2_IOMMU_COMMAND__PARITY_ERROR_EN__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__Reserved0_MASK
- IOMMU_L2_2_IOMMU_COMMAND__Reserved0__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__Reserved1_MASK
- IOMMU_L2_2_IOMMU_COMMAND__Reserved1__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__Reserved2_MASK
- IOMMU_L2_2_IOMMU_COMMAND__Reserved2__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__Reserved_MASK
- IOMMU_L2_2_IOMMU_COMMAND__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_COMMAND__SERR_EN_MASK
- IOMMU_L2_2_IOMMU_COMMAND__SERR_EN__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__EFR_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__INTERRUPT_PIN_W__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__IOMMU_CAP_EXT_W__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__IO_TLBSUP_W__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__MINOR_REV_ID_W__SHIFT
- IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W_MASK
- IOMMU_L2_2_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT
- IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID_MASK
- IOMMU_L2_2_IOMMU_DEVICE_ID__DEVICE_ID__SHIFT
- IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set_MASK
- IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__DSCX_CNTRL_set__SHIFT
- IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved_MASK
- IOMMU_L2_2_IOMMU_DSCX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup_MASK
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__DSFXSup__SHIFT
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR_MASK
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MAJOR__SHIFT
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR_MASK
- IOMMU_L2_2_IOMMU_DSFX_CONTROL__REVISION_MINOR__SHIFT
- IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set_MASK
- IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__DSSX_status_set__SHIFT
- IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved_MASK
- IOMMU_L2_2_IOMMU_DSSX_DUMMY_0__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE_MASK
- IOMMU_L2_2_IOMMU_HEADER__HEADER_TYPE__SHIFT
- IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE_MASK
- IOMMU_L2_2_IOMMU_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT
- IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN_MASK
- IOMMU_L2_2_IOMMU_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT
- IOMMU_L2_2_IOMMU_LATENCY__LATENCY_MASK
- IOMMU_L2_2_IOMMU_LATENCY__LATENCY__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__EVENTF_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GAM_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GA_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GLX_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__GT_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__HE_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__IA_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__NX_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PC_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPRF_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PPR_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__PREF_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved3__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved5__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__Reserved6__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL0_W__US_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__ATTRFW_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__DTE_seg_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__EPH_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__GIo_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HA_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__HD_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__InvIotlbTypeSup_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__MARCnum_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PAS_MAX_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_AUTORESP_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__PPR_OVERFLOW_EARLY_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved1__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__SNOOP_ATTRS_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W_MASK
- IOMMU_L2_2_IOMMU_MMIO_CONTROL1_W__V2_HD_DIS_SUP_W__SHIFT
- IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI_MASK
- IOMMU_L2_2_IOMMU_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT
- IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO_MASK
- IOMMU_L2_2_IOMMU_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT
- IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved_MASK
- IOMMU_L2_2_IOMMU_MSI_ADDR_LO__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_64_EN__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_ID__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_CAP_PTR__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_EN__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__MSI_MULT_MESS_EN__SHIFT
- IOMMU_L2_2_IOMMU_MSI_CAP__Reserved_MASK
- IOMMU_L2_2_IOMMU_MSI_CAP__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA_MASK
- IOMMU_L2_2_IOMMU_MSI_DATA__MSI_DATA__SHIFT
- IOMMU_L2_2_IOMMU_MSI_DATA__Reserved_MASK
- IOMMU_L2_2_IOMMU_MSI_DATA__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK
- IOMMU_L2_2_IOMMU_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT
- IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W_MASK
- IOMMU_L2_2_IOMMU_RANGE_W__BUS_NUMBER_W__SHIFT
- IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W_MASK
- IOMMU_L2_2_IOMMU_RANGE_W__FIRST_DEVICE_W__SHIFT
- IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W_MASK
- IOMMU_L2_2_IOMMU_RANGE_W__LAST_DEVICE_W__SHIFT
- IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W_MASK
- IOMMU_L2_2_IOMMU_RANGE_W__RNG_VALID_W__SHIFT
- IOMMU_L2_2_IOMMU_RANGE_W__Reserved_MASK
- IOMMU_L2_2_IOMMU_RANGE_W__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF_MASK
- IOMMU_L2_2_IOMMU_REGPROG_INF__REG_LEVEL_PROG_INF__SHIFT
- IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID_MASK
- IOMMU_L2_2_IOMMU_REVISION_ID__MAJOR_REV_ID__SHIFT
- IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID_MASK
- IOMMU_L2_2_IOMMU_REVISION_ID__MINOR_REV_ID__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__CAP_LIST_MASK
- IOMMU_L2_2_IOMMU_STATUS__CAP_LIST__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__INT_Status_MASK
- IOMMU_L2_2_IOMMU_STATUS__INT_Status__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR_MASK
- IOMMU_L2_2_IOMMU_STATUS__MASTER_DATA_ERROR__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED_MASK
- IOMMU_L2_2_IOMMU_STATUS__PARITY_ERROR_DETECTED__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT_MASK
- IOMMU_L2_2_IOMMU_STATUS__RECEIVED_MASTER_ABORT__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT_MASK
- IOMMU_L2_2_IOMMU_STATUS__RECEIVED_TARGET_ABORT__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__Reserved1_MASK
- IOMMU_L2_2_IOMMU_STATUS__Reserved1__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__Reserved2_MASK
- IOMMU_L2_2_IOMMU_STATUS__Reserved2__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__Reserved_MASK
- IOMMU_L2_2_IOMMU_STATUS__Reserved__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR_MASK
- IOMMU_L2_2_IOMMU_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT
- IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT_MASK
- IOMMU_L2_2_IOMMU_STATUS__SIGNAL_TARGET_ABORT__SHIFT
- IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF_MASK
- IOMMU_L2_2_IOMMU_SUB_CLASS__SUB_CLASS_INF__SHIFT
- IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID_MASK
- IOMMU_L2_2_IOMMU_VENDOR_ID__VENDOR_ID__SHIFT
- IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE_MASK
- IOMMU_L2_2_L2B_POISON_DVM_CNTRL__DVM_POISON_RESP_MODE__SHIFT
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn_MASK
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallHRT1ReqEn__SHIFT
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn_MASK
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallMemReqEn__SHIFT
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn_MASK
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallNPReqEn__SHIFT
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn_MASK
- IOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control__StallPReqEn__SHIFT
- IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W_MASK
- IOMMU_L2_2_SMMU_AIDR_W__ArchMajorRev_W__SHIFT
- IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W_MASK
- IOMMU_L2_2_SMMU_AIDR_W__ArchMinorRev_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ASID16_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATOS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ATS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__BTM_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__CD2L_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__COHACC_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__DORMHINT_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__HTTU_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__Hyp_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__MSI_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__PERFCTRS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__PRI_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__RAS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__S1P_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__S2P_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__SEV_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__STALL_MODEL_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__ST_LEVEL_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TERM_MODEL_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTENDIAN_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__TTF_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VATOS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMID16_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR0_W__VMW_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_PERMS_OVR_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__ATTR_TYPES_OVR_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__CMDQS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__EVENTQS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__PRIQS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__QUEUES_PRESET_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__REL_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__SIDSIZE_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__SSIDSIZE_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR1_W__TABLES_PRESET_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR2_W__BA_VATOS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR3_W__HAD_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN4K_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__GRAN64K_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__OAS_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IDR5_W__STALL_MAX_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Implementer_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__ProductID_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Revision_W__SHIFT
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W_MASK
- IOMMU_L2_2_SMMU_MMIO_IIDR_W__Variant_W__SHIFT
- IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK_MASK
- IOMMU_L2_GUEST_ADDR_CNTRL__IOMMU_L2_GUEST_ADDR_MASK__SHIFT
- IOMMU_L2_GUEST_ADDR_CNTRL__Reserved_MASK
- IOMMU_L2_GUEST_ADDR_CNTRL__Reserved__SHIFT
- IOMMU_LRUDIAG
- IOMMU_MAP_STATS
- IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0_MASK
- IOMMU_MARC_BASE_HI_0__MARCBaseAddr_H_0__SHIFT
- IOMMU_MARC_BASE_HI_0__Reserved_MASK
- IOMMU_MARC_BASE_HI_0__Reserved__SHIFT
- IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1_MASK
- IOMMU_MARC_BASE_HI_1__MARCBaseAddr_H_1__SHIFT
- IOMMU_MARC_BASE_HI_1__Reserved_MASK
- IOMMU_MARC_BASE_HI_1__Reserved__SHIFT
- IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2_MASK
- IOMMU_MARC_BASE_HI_2__MARCBaseAddr_H_2__SHIFT
- IOMMU_MARC_BASE_HI_2__Reserved_MASK
- IOMMU_MARC_BASE_HI_2__Reserved__SHIFT
- IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3_MASK
- IOMMU_MARC_BASE_HI_3__MARCBaseAddr_H_3__SHIFT
- IOMMU_MARC_BASE_HI_3__Reserved_MASK
- IOMMU_MARC_BASE_HI_3__Reserved__SHIFT
- IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0_MASK
- IOMMU_MARC_BASE_LO_0__MARCBaseAddr_L_0__SHIFT
- IOMMU_MARC_BASE_LO_0__Reserved_MASK
- IOMMU_MARC_BASE_LO_0__Reserved__SHIFT
- IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1_MASK
- IOMMU_MARC_BASE_LO_1__MARCBaseAddr_L_1__SHIFT
- IOMMU_MARC_BASE_LO_1__Reserved_MASK
- IOMMU_MARC_BASE_LO_1__Reserved__SHIFT
- IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2_MASK
- IOMMU_MARC_BASE_LO_2__MARCBaseAddr_L_2__SHIFT
- IOMMU_MARC_BASE_LO_2__Reserved_MASK
- IOMMU_MARC_BASE_LO_2__Reserved__SHIFT
- IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3_MASK
- IOMMU_MARC_BASE_LO_3__MARCBaseAddr_L_3__SHIFT
- IOMMU_MARC_BASE_LO_3__Reserved_MASK
- IOMMU_MARC_BASE_LO_3__Reserved__SHIFT
- IOMMU_MARC_LEN_HI_0__MARCLen_H_0_MASK
- IOMMU_MARC_LEN_HI_0__MARCLen_H_0__SHIFT
- IOMMU_MARC_LEN_HI_0__Reserved_MASK
- IOMMU_MARC_LEN_HI_0__Reserved__SHIFT
- IOMMU_MARC_LEN_HI_1__MARCLen_H_1_MASK
- IOMMU_MARC_LEN_HI_1__MARCLen_H_1__SHIFT
- IOMMU_MARC_LEN_HI_1__Reserved_MASK
- IOMMU_MARC_LEN_HI_1__Reserved__SHIFT
- IOMMU_MARC_LEN_HI_2__MARCLen_H_2_MASK
- IOMMU_MARC_LEN_HI_2__MARCLen_H_2__SHIFT
- IOMMU_MARC_LEN_HI_2__Reserved_MASK
- IOMMU_MARC_LEN_HI_2__Reserved__SHIFT
- IOMMU_MARC_LEN_HI_3__MARCLen_H_3_MASK
- IOMMU_MARC_LEN_HI_3__MARCLen_H_3__SHIFT
- IOMMU_MARC_LEN_HI_3__Reserved_MASK
- IOMMU_MARC_LEN_HI_3__Reserved__SHIFT
- IOMMU_MARC_LEN_LO_0__MARCLen_L_0_MASK
- IOMMU_MARC_LEN_LO_0__MARCLen_L_0__SHIFT
- IOMMU_MARC_LEN_LO_0__Reserved_MASK
- IOMMU_MARC_LEN_LO_0__Reserved__SHIFT
- IOMMU_MARC_LEN_LO_1__MARCLen_L_1_MASK
- IOMMU_MARC_LEN_LO_1__MARCLen_L_1__SHIFT
- IOMMU_MARC_LEN_LO_1__Reserved_MASK
- IOMMU_MARC_LEN_LO_1__Reserved__SHIFT
- IOMMU_MARC_LEN_LO_2__MARCLen_L_2_MASK
- IOMMU_MARC_LEN_LO_2__MARCLen_L_2__SHIFT
- IOMMU_MARC_LEN_LO_2__Reserved_MASK
- IOMMU_MARC_LEN_LO_2__Reserved__SHIFT
- IOMMU_MARC_LEN_LO_3__MARCLen_L_3_MASK
- IOMMU_MARC_LEN_LO_3__MARCLen_L_3__SHIFT
- IOMMU_MARC_LEN_LO_3__Reserved_MASK
- IOMMU_MARC_LEN_LO_3__Reserved__SHIFT
- IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0_MASK
- IOMMU_MARC_RELOC_HI_0__MARCRelocAddr_H_0__SHIFT
- IOMMU_MARC_RELOC_HI_0__Reserved_MASK
- IOMMU_MARC_RELOC_HI_0__Reserved__SHIFT
- IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1_MASK
- IOMMU_MARC_RELOC_HI_1__MARCRelocAddr_H_1__SHIFT
- IOMMU_MARC_RELOC_HI_1__Reserved_MASK
- IOMMU_MARC_RELOC_HI_1__Reserved__SHIFT
- IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2_MASK
- IOMMU_MARC_RELOC_HI_2__MARCRelocAddr_H_2__SHIFT
- IOMMU_MARC_RELOC_HI_2__Reserved_MASK
- IOMMU_MARC_RELOC_HI_2__Reserved__SHIFT
- IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3_MASK
- IOMMU_MARC_RELOC_HI_3__MARCRelocAddr_H_3__SHIFT
- IOMMU_MARC_RELOC_HI_3__Reserved_MASK
- IOMMU_MARC_RELOC_HI_3__Reserved__SHIFT
- IOMMU_MARC_RELOC_LO_0__MARCEnable_0_MASK
- IOMMU_MARC_RELOC_LO_0__MARCEnable_0__SHIFT
- IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0_MASK
- IOMMU_MARC_RELOC_LO_0__MARCReadOnly_0__SHIFT
- IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0_MASK
- IOMMU_MARC_RELOC_LO_0__MARCRelocAddr_L_0__SHIFT
- IOMMU_MARC_RELOC_LO_0__Reserved_MASK
- IOMMU_MARC_RELOC_LO_0__Reserved__SHIFT
- IOMMU_MARC_RELOC_LO_1__MARCEnable_1_MASK
- IOMMU_MARC_RELOC_LO_1__MARCEnable_1__SHIFT
- IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1_MASK
- IOMMU_MARC_RELOC_LO_1__MARCReadOnly_1__SHIFT
- IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1_MASK
- IOMMU_MARC_RELOC_LO_1__MARCRelocAddr_L_1__SHIFT
- IOMMU_MARC_RELOC_LO_1__Reserved_MASK
- IOMMU_MARC_RELOC_LO_1__Reserved__SHIFT
- IOMMU_MARC_RELOC_LO_2__MARCEnable_2_MASK
- IOMMU_MARC_RELOC_LO_2__MARCEnable_2__SHIFT
- IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2_MASK
- IOMMU_MARC_RELOC_LO_2__MARCReadOnly_2__SHIFT
- IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2_MASK
- IOMMU_MARC_RELOC_LO_2__MARCRelocAddr_L_2__SHIFT
- IOMMU_MARC_RELOC_LO_2__Reserved_MASK
- IOMMU_MARC_RELOC_LO_2__Reserved__SHIFT
- IOMMU_MARC_RELOC_LO_3__MARCEnable_3_MASK
- IOMMU_MARC_RELOC_LO_3__MARCEnable_3__SHIFT
- IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3_MASK
- IOMMU_MARC_RELOC_LO_3__MARCReadOnly_3__SHIFT
- IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3_MASK
- IOMMU_MARC_RELOC_LO_3__MARCRelocAddr_L_3__SHIFT
- IOMMU_MARC_RELOC_LO_3__Reserved_MASK
- IOMMU_MARC_RELOC_LO_3__Reserved__SHIFT
- IOMMU_MAX_CBS
- IOMMU_MFSR_BM
- IOMMU_MFSR_C
- IOMMU_MFSR_CPU
- IOMMU_MFSR_ERR
- IOMMU_MFSR_ME
- IOMMU_MFSR_PERR
- IOMMU_MFSR_RTYP
- IOMMU_MFSR_S
- IOMMU_MID_MID
- IOMMU_MID_SB0
- IOMMU_MID_SB1
- IOMMU_MID_SB2
- IOMMU_MID_SB3
- IOMMU_MID_SBAE
- IOMMU_MID_SE
- IOMMU_MMIO
- IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA_MASK
- IOMMU_MMIO_CAP_MISC_1__IOMMU_MSI_NUM_GA__SHIFT
- IOMMU_MMIO_CAP_MISC_1__Reserved_MASK
- IOMMU_MMIO_CAP_MISC_1__Reserved__SHIFT
- IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_MASK
- IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR_MASK
- IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM_PPR__SHIFT
- IOMMU_MMIO_CAP_MISC__IOMMU_MSI_NUM__SHIFT
- IOMMU_MMIO_CAP_MISC__Reserved1_MASK
- IOMMU_MMIO_CAP_MISC__Reserved1__SHIFT
- IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO_MASK
- IOMMU_MMIO_CMD_BASE_0__COM_BASE_LO__SHIFT
- IOMMU_MMIO_CMD_BASE_0__Reserved1_MASK
- IOMMU_MMIO_CMD_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI_MASK
- IOMMU_MMIO_CMD_BASE_1__COM_BASE_HI__SHIFT
- IOMMU_MMIO_CMD_BASE_1__COM_LEN_MASK
- IOMMU_MMIO_CMD_BASE_1__COM_LEN__SHIFT
- IOMMU_MMIO_CMD_BASE_1__Reserved0_MASK
- IOMMU_MMIO_CMD_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_CMD_BASE_1__Reserved1_MASK
- IOMMU_MMIO_CMD_BASE_1__Reserved1__SHIFT
- IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR_MASK
- IOMMU_MMIO_CMD_BUF_HDPTR_0__CMD_HDPTR__SHIFT
- IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_CMD_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_CMD_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR_MASK
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__CMD_TAILPTR__SHIFT
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_CMD_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_CMD_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_CNTRL_0__CMD_BUF_EN_MASK
- IOMMU_MMIO_CNTRL_0__CMD_BUF_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__COHERENT_MASK
- IOMMU_MMIO_CNTRL_0__COHERENT__SHIFT
- IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN_MASK
- IOMMU_MMIO_CNTRL_0__COM_WAIT_INTEN__SHIFT
- IOMMU_MMIO_CNTRL_0__EVENT_INT_EN_MASK
- IOMMU_MMIO_CNTRL_0__EVENT_INT_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN_MASK
- IOMMU_MMIO_CNTRL_0__EVENT_LOG_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__GAM_EN_MASK
- IOMMU_MMIO_CNTRL_0__GAM_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__GA_EN_MASK
- IOMMU_MMIO_CNTRL_0__GA_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__GA_INT_EN_MASK
- IOMMU_MMIO_CNTRL_0__GA_INT_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__GA_LOG_EN_MASK
- IOMMU_MMIO_CNTRL_0__GA_LOG_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__GT_EN_MASK
- IOMMU_MMIO_CNTRL_0__GT_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__HT_TUN_EN_MASK
- IOMMU_MMIO_CNTRL_0__HT_TUN_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__INV_TIMEOUT_MASK
- IOMMU_MMIO_CNTRL_0__INV_TIMEOUT__SHIFT
- IOMMU_MMIO_CNTRL_0__IOMMU_EN_MASK
- IOMMU_MMIO_CNTRL_0__IOMMU_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__ISOC_MASK
- IOMMU_MMIO_CNTRL_0__ISOC__SHIFT
- IOMMU_MMIO_CNTRL_0__PASS_PW_MASK
- IOMMU_MMIO_CNTRL_0__PASS_PW__SHIFT
- IOMMU_MMIO_CNTRL_0__PPRQ_MASK
- IOMMU_MMIO_CNTRL_0__PPRQ__SHIFT
- IOMMU_MMIO_CNTRL_0__PPR_EN_MASK
- IOMMU_MMIO_CNTRL_0__PPR_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__PPR_INT_EN_MASK
- IOMMU_MMIO_CNTRL_0__PPR_INT_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__PPR_LOG_EN_MASK
- IOMMU_MMIO_CNTRL_0__PPR_LOG_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__RES_PASS_PW_MASK
- IOMMU_MMIO_CNTRL_0__RES_PASS_PW__SHIFT
- IOMMU_MMIO_CNTRL_0__SMIF_EN_MASK
- IOMMU_MMIO_CNTRL_0__SMIF_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN_MASK
- IOMMU_MMIO_CNTRL_0__SMIF_LOG_EN__SHIFT
- IOMMU_MMIO_CNTRL_0__TLPT_MASK
- IOMMU_MMIO_CNTRL_0__TLPT__SHIFT
- IOMMU_MMIO_CNTRL_1__Block_StopMark_En_MASK
- IOMMU_MMIO_CNTRL_1__Block_StopMark_En__SHIFT
- IOMMU_MMIO_CNTRL_1__DTE_SEG_EN_MASK
- IOMMU_MMIO_CNTRL_1__DTE_SEG_EN__SHIFT
- IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE_MASK
- IOMMU_MMIO_CNTRL_1__DVM_DOMAIN_PNE__SHIFT
- IOMMU_MMIO_CNTRL_1__DVM_ERR_EN_MASK
- IOMMU_MMIO_CNTRL_1__DVM_ERR_EN__SHIFT
- IOMMU_MMIO_CNTRL_1__EPH_EN_MASK
- IOMMU_MMIO_CNTRL_1__EPH_EN__SHIFT
- IOMMU_MMIO_CNTRL_1__EVENTQ_MASK
- IOMMU_MMIO_CNTRL_1__EVENTQ__SHIFT
- IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD_MASK
- IOMMU_MMIO_CNTRL_1__HW_Prefetch_AD__SHIFT
- IOMMU_MMIO_CNTRL_1__MARC_en_MASK
- IOMMU_MMIO_CNTRL_1__MARC_en__SHIFT
- IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON_MASK
- IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_AON__SHIFT
- IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en_MASK
- IOMMU_MMIO_CNTRL_1__PPR_Auto_resp_en__SHIFT
- IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN_MASK
- IOMMU_MMIO_CNTRL_1__PRIV_ABORT_EN__SHIFT
- IOMMU_MMIO_CNTRL_1__Reserved0_MASK
- IOMMU_MMIO_CNTRL_1__Reserved0__SHIFT
- IOMMU_MMIO_CNTRL_1__Reserved1_MASK
- IOMMU_MMIO_CNTRL_1__Reserved1__SHIFT
- IOMMU_MMIO_CNTRL_1__V2_HD_Dis_MASK
- IOMMU_MMIO_CNTRL_1__V2_HD_Dis__SHIFT
- IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS_MASK
- IOMMU_MMIO_CONTROL_W__GMC_IOMMU_BYPASS__SHIFT
- IOMMU_MMIO_CONTROL_W__Reserved0_MASK
- IOMMU_MMIO_CONTROL_W__Reserved0__SHIFT
- IOMMU_MMIO_CONTROL_W__Reserved1_MASK
- IOMMU_MMIO_CONTROL_W__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0__ICOUNTER_0_0_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__ICOUNTER_0_0_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0__ICOUNTER_0_1_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__ICOUNTER_0_1_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0__ICOUNTER_0_2_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__ICOUNTER_0_2_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0__ICOUNTER_0_3_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__ICOUNTER_0_3_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0__ICOUNTER_1_0_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__ICOUNTER_1_0_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0__ICOUNTER_1_1_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__ICOUNTER_1_1_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0__ICOUNTER_1_2_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__ICOUNTER_1_2_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0__ICOUNTER_1_3_LO__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__ICOUNTER_1_3_HI__SHIFT
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved_MASK
- IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1__Reserved__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS_MASK
- IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_BANKS__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER_MASK
- IOMMU_MMIO_COUNTER_CONFIG_0__N_COUNTER__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0_MASK
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2_MASK
- IOMMU_MMIO_COUNTER_CONFIG_0__Reserved2__SHIFT
- IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_CONFIG_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO_MASK
- IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0__DEVID_LOCK_LO__SHIFT
- IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI_MASK
- IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1__DEVID_LOCK_HI__SHIFT
- IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO_MASK
- IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0__DOMAIN_LOCK_LO__SHIFT
- IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI_MASK
- IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1__DOMAIN_LOCK_HI__SHIFT
- IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO_MASK
- IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0__PASID_LOCK_LO__SHIFT
- IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI_MASK
- IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1__PASID_LOCK_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0__EVENT_NOTE_0_0_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__CERE_0_0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__EVENT_NOTE_0_0_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0__EVENT_NOTE_0_1_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__CERE_0_1__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__EVENT_NOTE_0_1_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0__EVENT_NOTE_0_2_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__CERE_0_2__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__EVENT_NOTE_0_2_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0__EVENT_NOTE_0_3_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__CERE_0_3__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__EVENT_NOTE_0_3_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0__EVENT_NOTE_1_0_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__CERE_1_0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__EVENT_NOTE_1_0_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0__EVENT_NOTE_1_1_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__CERE_1_1__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__EVENT_NOTE_1_1_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0__EVENT_NOTE_1_2_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__CERE_1_2__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__EVENT_NOTE_1_2_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0__EVENT_NOTE_1_3_LO__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__CERE_1_3__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__EVENT_NOTE_1_3_HI__SHIFT
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CAC_0_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__COUNT_UNITS_0_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__CSOURCE_0_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CAC_0_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__COUNT_UNITS_0_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__CSOURCE_0_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CAC_0_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__COUNT_UNITS_0_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__CSOURCE_0_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CAC_0_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__COUNT_UNITS_0_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__CSOURCE_0_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CAC_1_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__COUNT_UNITS_1_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__CSOURCE_1_0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CAC_1_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__COUNT_UNITS_1_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__CSOURCE_1_1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CAC_1_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__COUNT_UNITS_1_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__CSOURCE_1_2__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CAC_1_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__COUNT_UNITS_1_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__CSOURCE_1_3__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DEVICEID_MATCH_0_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__DIDMEN_0_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__DEVICEID_MASK_0_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DEVICEID_MATCH_0_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__DIDMEN_0_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__DEVICEID_MASK_0_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DEVICEID_MATCH_0_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__DIDMEN_0_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__DEVICEID_MASK_0_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DEVICEID_MATCH_0_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__DIDMEN_0_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__DEVICEID_MASK_0_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DEVICEID_MATCH_1_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__DIDMEN_1_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__DEVICEID_MASK_1_0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DEVICEID_MATCH_1_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__DIDMEN_1_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__DEVICEID_MASK_1_1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DEVICEID_MATCH_1_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__DIDMEN_1_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__DEVICEID_MASK_1_2__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DEVICEID_MATCH_1_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__DIDMEN_1_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__DEVICEID_MASK_1_3__SHIFT
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE_MASK
- IOMMU_MMIO_DEVTBL_1_BASE_0__DEV_TBL_1_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_1_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_1_BASE_1__DEV_TBL_1_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_1_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE_MASK
- IOMMU_MMIO_DEVTBL_2_BASE_0__DEV_TBL_2_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_2_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_2_BASE_1__DEV_TBL_2_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_2_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE_MASK
- IOMMU_MMIO_DEVTBL_3_BASE_0__DEV_TBL_3_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_3_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_3_BASE_1__DEV_TBL_3_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_3_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE_MASK
- IOMMU_MMIO_DEVTBL_4_BASE_0__DEV_TBL_4_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_4_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_4_BASE_1__DEV_TBL_4_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_4_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE_MASK
- IOMMU_MMIO_DEVTBL_5_BASE_0__DEV_TBL_5_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_5_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_5_BASE_1__DEV_TBL_5_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_5_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE_MASK
- IOMMU_MMIO_DEVTBL_6_BASE_0__DEV_TBL_6_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_6_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_6_BASE_1__DEV_TBL_6_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_6_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE_MASK
- IOMMU_MMIO_DEVTBL_7_BASE_0__DEV_TBL_7_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_7_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_7_BASE_1__DEV_TBL_7_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_7_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO_MASK
- IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_BASE_LO__SHIFT
- IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE_MASK
- IOMMU_MMIO_DEVTBL_BASE_0__DEV_TBL_SIZE__SHIFT
- IOMMU_MMIO_DEVTBL_BASE_0__Reserved1_MASK
- IOMMU_MMIO_DEVTBL_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI_MASK
- IOMMU_MMIO_DEVTBL_BASE_1__DEV_TBL_BASE_HI__SHIFT
- IOMMU_MMIO_DEVTBL_BASE_1__Reserved0_MASK
- IOMMU_MMIO_DEVTBL_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMAIN_MATCH_0_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__DOMMEN_0_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__DOMAIN_MASK_0_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMAIN_MATCH_0_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__DOMMEN_0_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__DOMAIN_MASK_0_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMAIN_MATCH_0_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__DOMMEN_0_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__DOMAIN_MASK_0_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMAIN_MATCH_0_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__DOMMEN_0_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__DOMAIN_MASK_0_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMAIN_MATCH_1_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__DOMMEN_1_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__DOMAIN_MASK_1_0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMAIN_MATCH_1_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__DOMMEN_1_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__DOMAIN_MASK_1_1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMAIN_MATCH_1_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__DOMMEN_1_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__DOMAIN_MASK_1_2__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMAIN_MATCH_1_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__DOMMEN_1_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__DOMAIN_MASK_1_3__SHIFT
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_DSCX__DSCX_CNTRL_MASK
- IOMMU_MMIO_DSCX__DSCX_CNTRL__SHIFT
- IOMMU_MMIO_DSCX__REVISION_MAJOR_MASK
- IOMMU_MMIO_DSCX__REVISION_MAJOR__SHIFT
- IOMMU_MMIO_DSCX__REVISION_MINOR_MASK
- IOMMU_MMIO_DSCX__REVISION_MINOR__SHIFT
- IOMMU_MMIO_DSFX__DSFXSup_MASK
- IOMMU_MMIO_DSFX__DSFXSup__SHIFT
- IOMMU_MMIO_DSFX__REVISION_MAJOR_MASK
- IOMMU_MMIO_DSFX__REVISION_MAJOR__SHIFT
- IOMMU_MMIO_DSFX__REVISION_MINOR_MASK
- IOMMU_MMIO_DSFX__REVISION_MINOR__SHIFT
- IOMMU_MMIO_DSSX__DSSX_status_MASK
- IOMMU_MMIO_DSSX__DSSX_status__SHIFT
- IOMMU_MMIO_DSSX__REVISION_MAJOR_MASK
- IOMMU_MMIO_DSSX__REVISION_MAJOR__SHIFT
- IOMMU_MMIO_DSSX__REVISION_MINOR_MASK
- IOMMU_MMIO_DSSX__REVISION_MINOR__SHIFT
- IOMMU_MMIO_EFR_0__DVM_ERR_SUP_MASK
- IOMMU_MMIO_EFR_0__DVM_ERR_SUP__SHIFT
- IOMMU_MMIO_EFR_0__EVENTF_MASK
- IOMMU_MMIO_EFR_0__EVENTF__SHIFT
- IOMMU_MMIO_EFR_0__GAF_MASK
- IOMMU_MMIO_EFR_0__GAF__SHIFT
- IOMMU_MMIO_EFR_0__GAM_SUP_MASK
- IOMMU_MMIO_EFR_0__GAM_SUP__SHIFT
- IOMMU_MMIO_EFR_0__GATS_MASK
- IOMMU_MMIO_EFR_0__GATS__SHIFT
- IOMMU_MMIO_EFR_0__GA_SUP_MASK
- IOMMU_MMIO_EFR_0__GA_SUP__SHIFT
- IOMMU_MMIO_EFR_0__GLX_SUP_MASK
- IOMMU_MMIO_EFR_0__GLX_SUP__SHIFT
- IOMMU_MMIO_EFR_0__GT_SUP_MASK
- IOMMU_MMIO_EFR_0__GT_SUP__SHIFT
- IOMMU_MMIO_EFR_0__HATS_MASK
- IOMMU_MMIO_EFR_0__HATS__SHIFT
- IOMMU_MMIO_EFR_0__HE_SUP_MASK
- IOMMU_MMIO_EFR_0__HE_SUP__SHIFT
- IOMMU_MMIO_EFR_0__IA_SUP_MASK
- IOMMU_MMIO_EFR_0__IA_SUP__SHIFT
- IOMMU_MMIO_EFR_0__NX_SUP_MASK
- IOMMU_MMIO_EFR_0__NX_SUP__SHIFT
- IOMMU_MMIO_EFR_0__PC_SUP_MASK
- IOMMU_MMIO_EFR_0__PC_SUP__SHIFT
- IOMMU_MMIO_EFR_0__PPRF_MASK
- IOMMU_MMIO_EFR_0__PPRF__SHIFT
- IOMMU_MMIO_EFR_0__PPR_SUP_MASK
- IOMMU_MMIO_EFR_0__PPR_SUP__SHIFT
- IOMMU_MMIO_EFR_0__PREF_SUP_MASK
- IOMMU_MMIO_EFR_0__PREF_SUP__SHIFT
- IOMMU_MMIO_EFR_0__Reserved1_MASK
- IOMMU_MMIO_EFR_0__Reserved1__SHIFT
- IOMMU_MMIO_EFR_0__Reserved_MASK
- IOMMU_MMIO_EFR_0__Reserved__SHIFT
- IOMMU_MMIO_EFR_0__SMIF_RC_MASK
- IOMMU_MMIO_EFR_0__SMIF_RC__SHIFT
- IOMMU_MMIO_EFR_0__SMIF_SUP_MASK
- IOMMU_MMIO_EFR_0__SMIF_SUP__SHIFT
- IOMMU_MMIO_EFR_0__XT_SUP_MASK
- IOMMU_MMIO_EFR_0__XT_SUP__SHIFT
- IOMMU_MMIO_EFR_1__ATTRFW_SUP_MASK
- IOMMU_MMIO_EFR_1__ATTRFW_SUP__SHIFT
- IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP_MASK
- IOMMU_MMIO_EFR_1__BLOCK_STOPMARK_SUP__SHIFT
- IOMMU_MMIO_EFR_1__DTE_seg_MASK
- IOMMU_MMIO_EFR_1__DTE_seg__SHIFT
- IOMMU_MMIO_EFR_1__EPH_SUP_MASK
- IOMMU_MMIO_EFR_1__EPH_SUP__SHIFT
- IOMMU_MMIO_EFR_1__GIo_SUP_MASK
- IOMMU_MMIO_EFR_1__GIo_SUP__SHIFT
- IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP_MASK
- IOMMU_MMIO_EFR_1__GMC_IOMMU_BYPASS_SUP__SHIFT
- IOMMU_MMIO_EFR_1__HA_SUP_MASK
- IOMMU_MMIO_EFR_1__HA_SUP__SHIFT
- IOMMU_MMIO_EFR_1__HD_SUP_MASK
- IOMMU_MMIO_EFR_1__HD_SUP__SHIFT
- IOMMU_MMIO_EFR_1__InvIotlbTypeSup_MASK
- IOMMU_MMIO_EFR_1__InvIotlbTypeSup__SHIFT
- IOMMU_MMIO_EFR_1__MARCnum_MASK
- IOMMU_MMIO_EFR_1__MARCnum__SHIFT
- IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP_MASK
- IOMMU_MMIO_EFR_1__MMIO_MSI_CAP_SUP__SHIFT
- IOMMU_MMIO_EFR_1__PAS_MAX_MASK
- IOMMU_MMIO_EFR_1__PAS_MAX__SHIFT
- IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP_MASK
- IOMMU_MMIO_EFR_1__PPR_AUTORESP_SUP__SHIFT
- IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP_MASK
- IOMMU_MMIO_EFR_1__PPR_OVERFLOW_EARLY_SUP__SHIFT
- IOMMU_MMIO_EFR_1__Reserved0_MASK
- IOMMU_MMIO_EFR_1__Reserved0__SHIFT
- IOMMU_MMIO_EFR_1__Reserved1_MASK
- IOMMU_MMIO_EFR_1__Reserved1__SHIFT
- IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP_MASK
- IOMMU_MMIO_EFR_1__SNOOP_ATTRS_SUP__SHIFT
- IOMMU_MMIO_EFR_1__US_SUP_MASK
- IOMMU_MMIO_EFR_1__US_SUP__SHIFT
- IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP_MASK
- IOMMU_MMIO_EFR_1__V2_HD_DIS_SUP__SHIFT
- IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO_MASK
- IOMMU_MMIO_EVENT_BASE_0__EVENT_BASE_LO__SHIFT
- IOMMU_MMIO_EVENT_BASE_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI_MASK
- IOMMU_MMIO_EVENT_BASE_1__EVENT_BASE_HI__SHIFT
- IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN_MASK
- IOMMU_MMIO_EVENT_BASE_1__EVENT_LEN__SHIFT
- IOMMU_MMIO_EVENT_BASE_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_BASE_1__Reserved1_MASK
- IOMMU_MMIO_EVENT_BASE_1__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR_MASK
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__EVENT_HDPTR__SHIFT
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR_MASK
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__EVENT_TAILPTR__SHIFT
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO_MASK
- IOMMU_MMIO_EVENT_B_BASE_0__EVENT_B_BASE_LO__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_B_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI_MASK
- IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_BASE_HI__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN_MASK
- IOMMU_MMIO_EVENT_B_BASE_1__EVENT_B_LEN__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_B_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_B_BASE_1__Reserved1_MASK
- IOMMU_MMIO_EVENT_B_BASE_1__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR_MASK
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__EVENT_B_HDPTR__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_B_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR_MASK
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__EVENT_B_TAILPTR__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO_MASK
- IOMMU_MMIO_EXCL_BASE_0__EXCL_BASE_LO__SHIFT
- IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW_MASK
- IOMMU_MMIO_EXCL_BASE_0__EX_ALLOW__SHIFT
- IOMMU_MMIO_EXCL_BASE_0__EX_EN_MASK
- IOMMU_MMIO_EXCL_BASE_0__EX_EN__SHIFT
- IOMMU_MMIO_EXCL_BASE_0__Reserved0_MASK
- IOMMU_MMIO_EXCL_BASE_0__Reserved0__SHIFT
- IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI_MASK
- IOMMU_MMIO_EXCL_BASE_1__EXCL_BASE_HI__SHIFT
- IOMMU_MMIO_EXCL_BASE_1__Reserved0_MASK
- IOMMU_MMIO_EXCL_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO_MASK
- IOMMU_MMIO_EXCL_LIM_0__EXCL_LIMIT_LO__SHIFT
- IOMMU_MMIO_EXCL_LIM_0__Reserved0_MASK
- IOMMU_MMIO_EXCL_LIM_0__Reserved0__SHIFT
- IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI_MASK
- IOMMU_MMIO_EXCL_LIM_1__EXCL_LIMIT_HI__SHIFT
- IOMMU_MMIO_EXCL_LIM_1__Reserved0_MASK
- IOMMU_MMIO_EXCL_LIM_1__Reserved0__SHIFT
- IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR_MASK
- IOMMU_MMIO_GA_BUF_HDPTR_0__GA_HDPTR__SHIFT
- IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_GA_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_GA_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR_MASK
- IOMMU_MMIO_GA_BUF_TAILPTR_0__GA_TAILPTR__SHIFT
- IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_GA_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_GA_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO_MASK
- IOMMU_MMIO_GA_LOG_BASE_0__GA_LOG_BASE_LO__SHIFT
- IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI_MASK
- IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_BASE_HI__SHIFT
- IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN_MASK
- IOMMU_MMIO_GA_LOG_BASE_1__GA_LOG_LEN__SHIFT
- IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO_MASK
- IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0__GA_LOG_TAILPTR_ADDR_LO__SHIFT
- IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI_MASK
- IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1__GA_LOG_TAILPTR_ADDR_HI__SHIFT
- IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO_MASK
- IOMMU_MMIO_HW_ERR_LOWER_0__SECOND_EV_CODE_LO__SHIFT
- IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI_MASK
- IOMMU_MMIO_HW_ERR_LOWER_1__SECOND_EV_CODE_HI__SHIFT
- IOMMU_MMIO_HW_ERR_STATUS_0__HEO_MASK
- IOMMU_MMIO_HW_ERR_STATUS_0__HEO__SHIFT
- IOMMU_MMIO_HW_ERR_STATUS_0__HEV_MASK
- IOMMU_MMIO_HW_ERR_STATUS_0__HEV__SHIFT
- IOMMU_MMIO_HW_ERR_STATUS_0__Reserved_MASK
- IOMMU_MMIO_HW_ERR_STATUS_0__Reserved__SHIFT
- IOMMU_MMIO_HW_ERR_STATUS_1__Reserved_MASK
- IOMMU_MMIO_HW_ERR_STATUS_1__Reserved__SHIFT
- IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO_MASK
- IOMMU_MMIO_HW_ERR_UPPER_0__FIRST_EV_CODE_LO__SHIFT
- IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE_MASK
- IOMMU_MMIO_HW_ERR_UPPER_1__EV_CODE__SHIFT
- IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI_MASK
- IOMMU_MMIO_HW_ERR_UPPER_1__FIRST_EV_CODE_HI__SHIFT
- IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI_MASK
- IOMMU_MMIO_MSI_ADDR_HI__MSI_ADDR_HI__SHIFT
- IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO_MASK
- IOMMU_MMIO_MSI_ADDR_LO__MSI_ADDR_LO__SHIFT
- IOMMU_MMIO_MSI_ADDR_LO__Reserved_MASK
- IOMMU_MMIO_MSI_ADDR_LO__Reserved__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_64_EN_MASK
- IOMMU_MMIO_MSI_CAP__MSI_64_EN__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_CAP_ID_MASK
- IOMMU_MMIO_MSI_CAP__MSI_CAP_ID__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR_MASK
- IOMMU_MMIO_MSI_CAP__MSI_CAP_PTR__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_EN_MASK
- IOMMU_MMIO_MSI_CAP__MSI_EN__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP_MASK
- IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_CAP__SHIFT
- IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN_MASK
- IOMMU_MMIO_MSI_CAP__MSI_MULT_MESS_EN__SHIFT
- IOMMU_MMIO_MSI_CAP__Reserved_MASK
- IOMMU_MMIO_MSI_CAP__Reserved__SHIFT
- IOMMU_MMIO_MSI_DATA__MSI_DATA_MASK
- IOMMU_MMIO_MSI_DATA__MSI_DATA__SHIFT
- IOMMU_MMIO_MSI_DATA__Reserved_MASK
- IOMMU_MMIO_MSI_DATA__Reserved__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_ID__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_PTR__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_CAP_TYPE__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_EN__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_FIXD__SHIFT
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV_MASK
- IOMMU_MMIO_MSI_MAPPING_CAP__MSI_MAP_RSV__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASID_MATCH_0_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__PASMEN_0_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__PASID_MASK_0_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASID_MATCH_0_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__PASMEN_0_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__PASID_MASK_0_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASID_MATCH_0_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__PASMEN_0_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__PASID_MASK_0_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASID_MATCH_0_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__PASMEN_0_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__PASID_MASK_0_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASID_MATCH_1_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__PASMEN_1_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__PASID_MASK_1_0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASID_MATCH_1_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__PASMEN_1_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__PASID_MASK_1_1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASID_MATCH_1_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__PASMEN_1_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__PASID_MASK_1_2__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1__Reserved0__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASID_MATCH_1_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__PASMEN_1_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0__Reserved1__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__PASID_MASK_1_3__SHIFT
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0_MASK
- IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code_MASK
- IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_code__SHIFT
- IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn_MASK
- IOMMU_MMIO_PPR_AUTORESP_0__PPR_Auto_resp_mask_gn__SHIFT
- IOMMU_MMIO_PPR_AUTORESP_0__Reserved0_MASK
- IOMMU_MMIO_PPR_AUTORESP_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO_MASK
- IOMMU_MMIO_PPR_BASE_0__PPR_BASE_LO__SHIFT
- IOMMU_MMIO_PPR_BASE_0__Reserved1_MASK
- IOMMU_MMIO_PPR_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI_MASK
- IOMMU_MMIO_PPR_BASE_1__PPR_BASE_HI__SHIFT
- IOMMU_MMIO_PPR_BASE_1__PPR_LEN_MASK
- IOMMU_MMIO_PPR_BASE_1__PPR_LEN__SHIFT
- IOMMU_MMIO_PPR_BASE_1__Reserved0_MASK
- IOMMU_MMIO_PPR_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_BASE_1__Reserved1_MASK
- IOMMU_MMIO_PPR_BASE_1__Reserved1__SHIFT
- IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR_MASK
- IOMMU_MMIO_PPR_BUF_HDPTR_0__PPR_HDPTR__SHIFT
- IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_PPR_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_PPR_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR_MASK
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__PPR_TAILPTR__SHIFT
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_PPR_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_PPR_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO_MASK
- IOMMU_MMIO_PPR_B_BASE_0__PPR_B_BASE_LO__SHIFT
- IOMMU_MMIO_PPR_B_BASE_0__Reserved1_MASK
- IOMMU_MMIO_PPR_B_BASE_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI_MASK
- IOMMU_MMIO_PPR_B_BASE_1__PPR_B_BASE_HI__SHIFT
- IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN_MASK
- IOMMU_MMIO_PPR_B_BASE_1__PPR_B_LEN__SHIFT
- IOMMU_MMIO_PPR_B_BASE_1__Reserved0_MASK
- IOMMU_MMIO_PPR_B_BASE_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_BASE_1__Reserved1_MASK
- IOMMU_MMIO_PPR_B_BASE_1__Reserved1__SHIFT
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR_MASK
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__PPR_B_HDPTR__SHIFT
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0_MASK
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1_MASK
- IOMMU_MMIO_PPR_B_BUF_HDPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0_MASK
- IOMMU_MMIO_PPR_B_BUF_HDPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR_MASK
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__PPR_B_TAILPTR__SHIFT
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0_MASK
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1_MASK
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_0__Reserved1__SHIFT
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0_MASK
- IOMMU_MMIO_PPR_B_BUF_TAILPTR_1__Reserved0__SHIFT
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en_MASK
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_en__SHIFT
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en_MASK
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_int_en__SHIFT
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold_MASK
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__PPR_B_Overflow_early_threshold__SHIFT
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0_MASK
- IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0__Reserved0__SHIFT
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en_MASK
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_en__SHIFT
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en_MASK
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_int_en__SHIFT
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold_MASK
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__PPR_Overflow_early_threshold__SHIFT
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0_MASK
- IOMMU_MMIO_PPR_OVERFLOW_EARLY_0__Reserved0__SHIFT
- IOMMU_MMIO_STATUS_0__CMD_BUFRUN_MASK
- IOMMU_MMIO_STATUS_0__CMD_BUFRUN__SHIFT
- IOMMU_MMIO_STATUS_0__COMWAIT_INT_MASK
- IOMMU_MMIO_STATUS_0__COMWAIT_INT__SHIFT
- IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE_MASK
- IOMMU_MMIO_STATUS_0__EVENT_BUF_ACTIVE__SHIFT
- IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW_MASK
- IOMMU_MMIO_STATUS_0__EVENT_B_OVERFLOW__SHIFT
- IOMMU_MMIO_STATUS_0__EVENT_LOGINT_MASK
- IOMMU_MMIO_STATUS_0__EVENT_LOGINT__SHIFT
- IOMMU_MMIO_STATUS_0__EVENT_LOGRUN_MASK
- IOMMU_MMIO_STATUS_0__EVENT_LOGRUN__SHIFT
- IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW_MASK
- IOMMU_MMIO_STATUS_0__EVENT_OVERFLOW__SHIFT
- IOMMU_MMIO_STATUS_0__GA_INT_MASK
- IOMMU_MMIO_STATUS_0__GA_INT__SHIFT
- IOMMU_MMIO_STATUS_0__GA_OVERFLOW_MASK
- IOMMU_MMIO_STATUS_0__GA_OVERFLOW__SHIFT
- IOMMU_MMIO_STATUS_0__GA_RUN_MASK
- IOMMU_MMIO_STATUS_0__GA_RUN__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE_MASK
- IOMMU_MMIO_STATUS_0__PPR_BUF_ACTIVE__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY_MASK
- IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_EARLY__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW_MASK
- IOMMU_MMIO_STATUS_0__PPR_B_OVERFLOW__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_INT_MASK
- IOMMU_MMIO_STATUS_0__PPR_INT__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY_MASK
- IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_EARLY__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_OVERFLOW_MASK
- IOMMU_MMIO_STATUS_0__PPR_OVERFLOW__SHIFT
- IOMMU_MMIO_STATUS_0__PPR_RUN_MASK
- IOMMU_MMIO_STATUS_0__PPR_RUN__SHIFT
- IOMMU_MMIO_STATUS_0__Reserved0_MASK
- IOMMU_MMIO_STATUS_0__Reserved0__SHIFT
- IOMMU_MMIO_STATUS_0__Reserved1_MASK
- IOMMU_MMIO_STATUS_0__Reserved1__SHIFT
- IOMMU_MMIO_STATUS_1__Reserved0_MASK
- IOMMU_MMIO_STATUS_1__Reserved0__SHIFT
- IOMMU_MODIFIED
- IOMMU_NAME_SIZE
- IOMMU_NEED_FLUSH
- IOMMU_NOEXEC
- IOMMU_NOT_FOUND
- IOMMU_NO_SPAN_BOUND
- IOMMU_NPTES
- IOMMU_NR_POOLS
- IOMMU_NUM_CTXS
- IOMMU_ORDER
- IOMMU_PAGE_ALIGN
- IOMMU_PAGE_ALIGN_4K
- IOMMU_PAGE_MASK
- IOMMU_PAGE_MASK_4K
- IOMMU_PAGE_RESP_FAILURE
- IOMMU_PAGE_RESP_INVALID
- IOMMU_PAGE_RESP_PASID_VALID
- IOMMU_PAGE_RESP_SUCCESS
- IOMMU_PAGE_RESP_VERSION_1
- IOMMU_PAGE_SHIFT
- IOMMU_PAGE_SHIFT_4K
- IOMMU_PAGE_SIZE
- IOMMU_PAGE_SIZE_4K
- IOMMU_PASID_INVALID
- IOMMU_PCI_INIT
- IOMMU_PC_COUNTER_REG
- IOMMU_PC_COUNTER_REPORT_REG
- IOMMU_PC_COUNTER_SRC_REG
- IOMMU_PC_DEVID_MATCH_REG
- IOMMU_PC_DOMID_MATCH_REG
- IOMMU_PC_PASID_MATCH_REG
- IOMMU_POOL_HASHBITS
- IOMMU_PRIV
- IOMMU_PROT_IR
- IOMMU_PROT_IW
- IOMMU_PROT_MASK
- IOMMU_PTE_FC
- IOMMU_PTE_IR
- IOMMU_PTE_IW
- IOMMU_PTE_MODE
- IOMMU_PTE_PAGE
- IOMMU_PTE_PR
- IOMMU_PTE_PRESENT
- IOMMU_PTE_U
- IOMMU_QCOM_SYS_CACHE
- IOMMU_READ
- IOMMU_REGSET_ENTRY
- IOMMU_RESERVED_PTE
- IOMMU_RESV_DIRECT
- IOMMU_RESV_DIRECT_RELAXABLE
- IOMMU_RESV_MSI
- IOMMU_RESV_RESERVED
- IOMMU_RESV_SW_MSI
- IOMMU_RNGE
- IOMMU_RNGE_128MB
- IOMMU_RNGE_16MB
- IOMMU_RNGE_1GB
- IOMMU_RNGE_256MB
- IOMMU_RNGE_2GB
- IOMMU_RNGE_32MB
- IOMMU_RNGE_512MB
- IOMMU_RNGE_64MB
- IOMMU_SBCFG_BA16
- IOMMU_SBCFG_BA8
- IOMMU_SBCFG_BYPASS
- IOMMU_SBCFG_SAB30
- IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0_MASK
- IOMMU_SMN_DATA_0__IOMMU_SMN_DATA_0__SHIFT
- IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1_MASK
- IOMMU_SMN_DATA_1__IOMMU_SMN_DATA_1__SHIFT
- IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0_MASK
- IOMMU_SMN_INDEX_0__IOMMU_SMN_INDEX_0__SHIFT
- IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1_MASK
- IOMMU_SMN_INDEX_1__IOMMU_SMN_INDEX_1__SHIFT
- IOMMU_START
- IOMMU_START_STATE
- IOMMU_TABLE_GROUP_MAX_TABLES
- IOMMU_TABLE_USERSPACE_ENTRY
- IOMMU_TABLE_USERSPACE_ENTRY_RO
- IOMMU_TAGCMP
- IOMMU_TAGDIAG
- IOMMU_TOTAL_ENTRIES
- IOMMU_TSBBASE
- IOMMU_UNITY_MAP_FLAG_EXCL_RANGE
- IOMMU_USED
- IOMMU_VADIAG
- IOMMU_WAIT_OP
- IOMMU_WINSIZE
- IOMMU_WRITE
- IOMMU_WRITE_PROTECT
- IOMODE_ANY
- IOMODE_READ
- IOMODE_RW
- IOMUXC_CONFIG_SION
- IOMUXC_GPR0
- IOMUXC_GPR1
- IOMUXC_GPR10
- IOMUXC_GPR11
- IOMUXC_GPR12
- IOMUXC_GPR13
- IOMUXC_GPR14
- IOMUXC_GPR15
- IOMUXC_GPR16
- IOMUXC_GPR17
- IOMUXC_GPR18
- IOMUXC_GPR19
- IOMUXC_GPR2
- IOMUXC_GPR20
- IOMUXC_GPR21
- IOMUXC_GPR22
- IOMUXC_GPR3
- IOMUXC_GPR4
- IOMUXC_GPR5
- IOMUXC_GPR6
- IOMUXC_GPR7
- IOMUXC_GPR8
- IOMUXC_GPR9
- IOMUXGPR
- IOMUXINT_OBS1
- IOMUXINT_OBS2
- IOMUXSW_MUX_CTL
- IOMUXSW_PAD_CTL
- IOMUX_BASE
- IOMUX_CONFIG_ALT1
- IOMUX_CONFIG_ALT2
- IOMUX_CONFIG_FUNC
- IOMUX_CONFIG_GPIO
- IOMUX_CONFIG_SION
- IOMUX_ENABLE_MASK
- IOMUX_ENABLE_SHIFT
- IOMUX_GPIONUM_MASK
- IOMUX_GPIONUM_SHIFT
- IOMUX_GPIO_ONLY
- IOMUX_ICONFIG_ALT1
- IOMUX_ICONFIG_ALT2
- IOMUX_ICONFIG_FUNC
- IOMUX_ICONFIG_GPIO
- IOMUX_ICONFIG_NONE
- IOMUX_MODE
- IOMUX_MODE_MASK
- IOMUX_MODE_SHIFT
- IOMUX_OCONFIG_ALT1
- IOMUX_OCONFIG_ALT2
- IOMUX_OCONFIG_ALT3
- IOMUX_OCONFIG_ALT4
- IOMUX_OCONFIG_ALT5
- IOMUX_OCONFIG_ALT6
- IOMUX_OCONFIG_FUNC
- IOMUX_OCONFIG_GPIO
- IOMUX_PAD
- IOMUX_PADNUM_MASK
- IOMUX_PIN
- IOMUX_PRESENT
- IOMUX_REG_MASK
- IOMUX_SOURCE_PMU
- IOMUX_TO_GPIO
- IOMUX_UNROUTED
- IOMUX_WIDTH_3BIT
- IOMUX_WIDTH_4BIT
- IOM_CTRL_ALAW
- IOM_CTRL_ENA
- IOM_CTRL_NOPCM
- IOM_CTRL_RCV
- IOM_CTRL_ULAW
- IOM_P1_TXD
- IONICS_PLUGCOMPUTER_PID
- IONICS_VID
- IONIC_ADDR_LEN
- IONIC_ADDR_MASK
- IONIC_ADMINQ_LENGTH
- IONIC_ASIC_TYPE_CAPRI
- IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET
- IONIC_BAR0_DEV_CMD_REGS_OFFSET
- IONIC_BAR0_DEV_INFO_REGS_OFFSET
- IONIC_BAR0_INTR_CTRL_OFFSET
- IONIC_BAR0_INTR_STATUS_OFFSET
- IONIC_BAR0_SIZE
- IONIC_BARS_MAX
- IONIC_CMD_FW_CONTROL
- IONIC_CMD_FW_DOWNLOAD
- IONIC_CMD_GETATTR
- IONIC_CMD_IDENTIFY
- IONIC_CMD_INIT
- IONIC_CMD_LIF_GETATTR
- IONIC_CMD_LIF_IDENTIFY
- IONIC_CMD_LIF_INIT
- IONIC_CMD_LIF_RESET
- IONIC_CMD_LIF_SETATTR
- IONIC_CMD_NOP
- IONIC_CMD_PORT_GETATTR
- IONIC_CMD_PORT_IDENTIFY
- IONIC_CMD_PORT_INIT
- IONIC_CMD_PORT_RESET
- IONIC_CMD_PORT_SETATTR
- IONIC_CMD_QOS_CLASS_IDENTIFY
- IONIC_CMD_QOS_CLASS_INIT
- IONIC_CMD_QOS_CLASS_RESET
- IONIC_CMD_Q_CONTROL
- IONIC_CMD_Q_INIT
- IONIC_CMD_RDMA_CREATE_ADMINQ
- IONIC_CMD_RDMA_CREATE_CQ
- IONIC_CMD_RDMA_CREATE_EQ
- IONIC_CMD_RDMA_RESET_LIF
- IONIC_CMD_RESET
- IONIC_CMD_RX_FILTER_ADD
- IONIC_CMD_RX_FILTER_DEL
- IONIC_CMD_RX_MODE_SET
- IONIC_CMD_SETATTR
- IONIC_COMP_COLOR_MASK
- IONIC_CQ_STAT_DESC
- IONIC_DBELL_INDEX_MASK
- IONIC_DBELL_QID
- IONIC_DBELL_QID_MASK
- IONIC_DBELL_QID_SHIFT
- IONIC_DBELL_RING
- IONIC_DBELL_RING_0
- IONIC_DBELL_RING_1
- IONIC_DBELL_RING_2
- IONIC_DBELL_RING_3
- IONIC_DBELL_RING_MASK
- IONIC_DBELL_RING_SHIFT
- IONIC_DEF_TXRX_DESC
- IONIC_DEVINFO_FWVERS_BUFLEN
- IONIC_DEVINFO_SERIAL_BUFLEN
- IONIC_DEV_ATTR_FEATURES
- IONIC_DEV_ATTR_NAME
- IONIC_DEV_ATTR_STATE
- IONIC_DEV_CMD_DONE
- IONIC_DEV_CMD_REG_COUNT
- IONIC_DEV_CMD_REG_VERSION
- IONIC_DEV_DISABLE
- IONIC_DEV_ENABLE
- IONIC_DEV_HANG_RESET
- IONIC_DEV_INFO_REG_COUNT
- IONIC_DEV_INFO_SIGNATURE
- IONIC_DEV_INFO_VERSION
- IONIC_DRV_DESCRIPTION
- IONIC_DRV_NAME
- IONIC_DRV_VERSION
- IONIC_DW_TYPE_LIF_RESET
- IONIC_DW_TYPE_LINK_STATUS
- IONIC_DW_TYPE_RX_ADDR_ADD
- IONIC_DW_TYPE_RX_ADDR_DEL
- IONIC_DW_TYPE_RX_MODE
- IONIC_ETH_HW_RX_CSUM
- IONIC_ETH_HW_RX_HASH
- IONIC_ETH_HW_RX_SG
- IONIC_ETH_HW_TSO
- IONIC_ETH_HW_TSO_ECN
- IONIC_ETH_HW_TSO_GRE
- IONIC_ETH_HW_TSO_GRE_CSUM
- IONIC_ETH_HW_TSO_IPV6
- IONIC_ETH_HW_TSO_IPXIP4
- IONIC_ETH_HW_TSO_IPXIP6
- IONIC_ETH_HW_TSO_UDP
- IONIC_ETH_HW_TSO_UDP_CSUM
- IONIC_ETH_HW_TX_CSUM
- IONIC_ETH_HW_TX_SG
- IONIC_ETH_HW_VLAN_RX_FILTER
- IONIC_ETH_HW_VLAN_RX_STRIP
- IONIC_ETH_HW_VLAN_TX_TAG
- IONIC_EVENT_HEARTBEAT
- IONIC_EVENT_LINK_CHANGE
- IONIC_EVENT_LOG
- IONIC_EVENT_RESET
- IONIC_FW_ACTIVATE
- IONIC_FW_INSTALL
- IONIC_FW_RESET
- IONIC_IDENTITY_VERSION_1
- IONIC_IFNAMSIZ
- IONIC_INTR_CRED_COUNT
- IONIC_INTR_CRED_COUNT_SIGNED
- IONIC_INTR_CRED_REARM
- IONIC_INTR_CRED_RESET_COALESCE
- IONIC_INTR_CRED_UNMASK
- IONIC_INTR_CTRL_COAL_MAX
- IONIC_INTR_CTRL_REGS_MAX
- IONIC_INTR_MASK_CLEAR
- IONIC_INTR_MASK_SET
- IONIC_INTR_STAT_DESC
- IONIC_ITR_COAL_USEC_DEFAULT
- IONIC_LIFS_MAX
- IONIC_LIF_ATTR_FEATURES
- IONIC_LIF_ATTR_MAC
- IONIC_LIF_ATTR_MTU
- IONIC_LIF_ATTR_NAME
- IONIC_LIF_ATTR_RSS
- IONIC_LIF_ATTR_STATE
- IONIC_LIF_ATTR_STATS_CTRL
- IONIC_LIF_CAP_ETH
- IONIC_LIF_CAP_RDMA
- IONIC_LIF_DISABLE
- IONIC_LIF_ENABLE
- IONIC_LIF_HANG_RESET
- IONIC_LIF_INITED
- IONIC_LIF_LINK_CHECK_REQUESTED
- IONIC_LIF_NAME_MAX_SZ
- IONIC_LIF_QUEUE_RESET
- IONIC_LIF_STATE_SIZE
- IONIC_LIF_STAT_DESC
- IONIC_LIF_SW_DEBUG_STATS
- IONIC_LIF_TYPE_CLASSIC
- IONIC_LIF_TYPE_MACVLAN
- IONIC_LIF_TYPE_NETQUEUE
- IONIC_LIF_UP
- IONIC_MAX_MTU
- IONIC_MAX_NUM_NAPI_CNTR
- IONIC_MAX_NUM_SG_CNTR
- IONIC_MAX_TXRX_DESC
- IONIC_MIN_MTU
- IONIC_MIN_TXRX_DESC
- IONIC_NAPI_STAT_DESC
- IONIC_NOTIFYQ_LENGTH
- IONIC_NUM_DBG_CQ_STATS
- IONIC_NUM_DBG_INTR_STATS
- IONIC_NUM_DBG_NAPI_STATS
- IONIC_NUM_LIF_STATS
- IONIC_NUM_RX_STATS
- IONIC_NUM_TX_Q_STATS
- IONIC_NUM_TX_STATS
- IONIC_OS_TYPE_DPDK
- IONIC_OS_TYPE_ESXI
- IONIC_OS_TYPE_FREEBSD
- IONIC_OS_TYPE_IPXE
- IONIC_OS_TYPE_LINUX
- IONIC_OS_TYPE_WIN
- IONIC_PAUSE_FLAGS_MASK
- IONIC_PAUSE_F_RX
- IONIC_PAUSE_F_TX
- IONIC_PAUSE_TYPE_MASK
- IONIC_PCI_BAR_DBELL
- IONIC_PHY_TYPE_COPPER
- IONIC_PHY_TYPE_FIBER
- IONIC_PHY_TYPE_NONE
- IONIC_PKT_TYPE_IPV4
- IONIC_PKT_TYPE_IPV4_TCP
- IONIC_PKT_TYPE_IPV4_UDP
- IONIC_PKT_TYPE_IPV6
- IONIC_PKT_TYPE_IPV6_TCP
- IONIC_PKT_TYPE_IPV6_UDP
- IONIC_PKT_TYPE_NON_IP
- IONIC_PORT_ADMIN_STATE_DOWN
- IONIC_PORT_ADMIN_STATE_NONE
- IONIC_PORT_ADMIN_STATE_UP
- IONIC_PORT_ATTR_AUTONEG
- IONIC_PORT_ATTR_FEC
- IONIC_PORT_ATTR_LOOPBACK
- IONIC_PORT_ATTR_MTU
- IONIC_PORT_ATTR_PAUSE
- IONIC_PORT_ATTR_SPEED
- IONIC_PORT_ATTR_STATE
- IONIC_PORT_ATTR_STATS_CTRL
- IONIC_PORT_FEC_TYPE_FC
- IONIC_PORT_FEC_TYPE_NONE
- IONIC_PORT_FEC_TYPE_RS
- IONIC_PORT_LOOPBACK_MODE_MAC
- IONIC_PORT_LOOPBACK_MODE_NONE
- IONIC_PORT_LOOPBACK_MODE_PHY
- IONIC_PORT_OPER_STATUS_DOWN
- IONIC_PORT_OPER_STATUS_NONE
- IONIC_PORT_OPER_STATUS_UP
- IONIC_PORT_PAUSE_TYPE_LINK
- IONIC_PORT_PAUSE_TYPE_NONE
- IONIC_PORT_PAUSE_TYPE_PFC
- IONIC_PORT_TYPE_ETH
- IONIC_PORT_TYPE_MGMT
- IONIC_PORT_TYPE_NONE
- IONIC_QCQ_F_INITED
- IONIC_QCQ_F_INTR
- IONIC_QCQ_F_NOTIFYQ
- IONIC_QCQ_F_RX_STATS
- IONIC_QCQ_F_SG
- IONIC_QCQ_F_TX_STATS
- IONIC_QINIT_F_DEBUG
- IONIC_QINIT_F_ENA
- IONIC_QINIT_F_EQ
- IONIC_QINIT_F_IRQ
- IONIC_QINIT_F_SG
- IONIC_QOS_CLASS_DEFAULT
- IONIC_QOS_CLASS_MAX
- IONIC_QOS_CLASS_NAME_SZ
- IONIC_QOS_CLASS_TYPE_DSCP
- IONIC_QOS_CLASS_TYPE_NONE
- IONIC_QOS_CLASS_TYPE_PCP
- IONIC_QOS_CLASS_USER_DEFINED_1
- IONIC_QOS_CLASS_USER_DEFINED_2
- IONIC_QOS_CLASS_USER_DEFINED_3
- IONIC_QOS_CLASS_USER_DEFINED_4
- IONIC_QOS_CLASS_USER_DEFINED_5
- IONIC_QOS_CLASS_USER_DEFINED_6
- IONIC_QOS_CONFIG_F_DROP
- IONIC_QOS_CONFIG_F_ENABLE
- IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP
- IONIC_QOS_CONFIG_F_RW_IP_DSCP
- IONIC_QOS_DSCP_MAX_VALUES
- IONIC_QOS_SCHED_TYPE_DWRR
- IONIC_QOS_SCHED_TYPE_STRICT
- IONIC_QTYPE_ADMINQ
- IONIC_QTYPE_EQ
- IONIC_QTYPE_MAX
- IONIC_QTYPE_NOTIFYQ
- IONIC_QTYPE_RXQ
- IONIC_QTYPE_TXQ
- IONIC_Q_DISABLE
- IONIC_Q_ENABLE
- IONIC_Q_HANG_RESET
- IONIC_RC_BAD_ADDR
- IONIC_RC_DEV_CMD
- IONIC_RC_EAGAIN
- IONIC_RC_EBUSY
- IONIC_RC_EEXIST
- IONIC_RC_EFAULT
- IONIC_RC_EINTR
- IONIC_RC_EINVAL
- IONIC_RC_EIO
- IONIC_RC_ENOENT
- IONIC_RC_ENOMEM
- IONIC_RC_ENOSPC
- IONIC_RC_ENOSUPP
- IONIC_RC_EOPCODE
- IONIC_RC_EPERM
- IONIC_RC_EQID
- IONIC_RC_EQTYPE
- IONIC_RC_ERANGE
- IONIC_RC_ERDMA
- IONIC_RC_ERROR
- IONIC_RC_EVERSION
- IONIC_RC_SUCCESS
- IONIC_READ_STAT64
- IONIC_REGS_H
- IONIC_RSS_HASH_KEY_SIZE
- IONIC_RSS_TYPE_IPV4
- IONIC_RSS_TYPE_IPV4_TCP
- IONIC_RSS_TYPE_IPV4_UDP
- IONIC_RSS_TYPE_IPV6
- IONIC_RSS_TYPE_IPV6_TCP
- IONIC_RSS_TYPE_IPV6_UDP
- IONIC_RXQ_COMP_CSUM_F_CALC
- IONIC_RXQ_COMP_CSUM_F_IP_BAD
- IONIC_RXQ_COMP_CSUM_F_IP_OK
- IONIC_RXQ_COMP_CSUM_F_TCP_BAD
- IONIC_RXQ_COMP_CSUM_F_TCP_OK
- IONIC_RXQ_COMP_CSUM_F_UDP_BAD
- IONIC_RXQ_COMP_CSUM_F_UDP_OK
- IONIC_RXQ_COMP_CSUM_F_VLAN
- IONIC_RXQ_COMP_PKT_TYPE_MASK
- IONIC_RXQ_DESC_OPCODE_SG
- IONIC_RXQ_DESC_OPCODE_SIMPLE
- IONIC_RXQ_INDEX_ANY
- IONIC_RX_COPYBREAK_DEFAULT
- IONIC_RX_FILTER_HASH_BITS
- IONIC_RX_FILTER_HLISTS
- IONIC_RX_FILTER_HLISTS_MASK
- IONIC_RX_FILTER_MATCH_MAC
- IONIC_RX_FILTER_MATCH_MAC_VLAN
- IONIC_RX_FILTER_MATCH_VLAN
- IONIC_RX_MAX_SG_ELEMS
- IONIC_RX_MODE_F_ALLMULTI
- IONIC_RX_MODE_F_BROADCAST
- IONIC_RX_MODE_F_MULTICAST
- IONIC_RX_MODE_F_PROMISC
- IONIC_RX_MODE_F_UNICAST
- IONIC_RX_RING_DOORBELL_STRIDE
- IONIC_RX_STAT_DESC
- IONIC_SPEED_100G
- IONIC_SPEED_10G
- IONIC_SPEED_1G
- IONIC_SPEED_25G
- IONIC_SPEED_40G
- IONIC_SPEED_50G
- IONIC_STATS_CTL_RESET
- IONIC_STAT_DESC
- IONIC_STAT_TO_OFFSET
- IONIC_SUBDEV_ID_NAPLES_100_4
- IONIC_SUBDEV_ID_NAPLES_100_8
- IONIC_SUBDEV_ID_NAPLES_25
- IONIC_TXQ_DESC_ADDR_MASK
- IONIC_TXQ_DESC_ADDR_SHIFT
- IONIC_TXQ_DESC_FLAGS_MASK
- IONIC_TXQ_DESC_FLAGS_SHIFT
- IONIC_TXQ_DESC_FLAG_CSUM_L3
- IONIC_TXQ_DESC_FLAG_CSUM_L4
- IONIC_TXQ_DESC_FLAG_ENCAP
- IONIC_TXQ_DESC_FLAG_TSO_EOT
- IONIC_TXQ_DESC_FLAG_TSO_SOT
- IONIC_TXQ_DESC_FLAG_VLAN
- IONIC_TXQ_DESC_NSGE_MASK
- IONIC_TXQ_DESC_NSGE_SHIFT
- IONIC_TXQ_DESC_OPCODE_CSUM_HW
- IONIC_TXQ_DESC_OPCODE_CSUM_NONE
- IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL
- IONIC_TXQ_DESC_OPCODE_MASK
- IONIC_TXQ_DESC_OPCODE_SHIFT
- IONIC_TXQ_DESC_OPCODE_TSO
- IONIC_TX_MAX_SG_ELEMS
- IONIC_TX_Q_STAT_DESC
- IONIC_TX_STAT_DESC
- IONIC_XCVR_PID_QSFP_100G_ACC
- IONIC_XCVR_PID_QSFP_100G_AOC
- IONIC_XCVR_PID_QSFP_100G_CR4
- IONIC_XCVR_PID_QSFP_100G_CWDM4
- IONIC_XCVR_PID_QSFP_100G_ER4
- IONIC_XCVR_PID_QSFP_100G_LR4
- IONIC_XCVR_PID_QSFP_100G_PSM4
- IONIC_XCVR_PID_QSFP_100G_SR4
- IONIC_XCVR_PID_QSFP_40GBASE_AOC
- IONIC_XCVR_PID_QSFP_40GBASE_CR4
- IONIC_XCVR_PID_QSFP_40GBASE_ER4
- IONIC_XCVR_PID_QSFP_40GBASE_LR4
- IONIC_XCVR_PID_QSFP_40GBASE_SR4
- IONIC_XCVR_PID_SFP_10GBASE_AOC
- IONIC_XCVR_PID_SFP_10GBASE_CU
- IONIC_XCVR_PID_SFP_10GBASE_ER
- IONIC_XCVR_PID_SFP_10GBASE_LR
- IONIC_XCVR_PID_SFP_10GBASE_LRM
- IONIC_XCVR_PID_SFP_10GBASE_SR
- IONIC_XCVR_PID_SFP_25GBASE_AOC
- IONIC_XCVR_PID_SFP_25GBASE_CR_L
- IONIC_XCVR_PID_SFP_25GBASE_CR_N
- IONIC_XCVR_PID_SFP_25GBASE_CR_S
- IONIC_XCVR_PID_SFP_25GBASE_ER
- IONIC_XCVR_PID_SFP_25GBASE_LR
- IONIC_XCVR_PID_SFP_25GBASE_SR
- IONIC_XCVR_PID_UNKNOWN
- IONIC_XCVR_STATE_INSERTED
- IONIC_XCVR_STATE_PENDING
- IONIC_XCVR_STATE_REMOVED
- IONIC_XCVR_STATE_SPROM_READ
- IONIC_XCVR_STATE_SPROM_READ_ERR
- ION_BUFFER_LEN
- ION_DEVICE
- ION_DEVICE_ID_80251_NETCHIP
- ION_DEVICE_ID_EDGEPORT_1
- ION_DEVICE_ID_EDGEPORT_16_DUAL_CPU
- ION_DEVICE_ID_EDGEPORT_2
- ION_DEVICE_ID_EDGEPORT_21
- ION_DEVICE_ID_EDGEPORT_21C
- ION_DEVICE_ID_EDGEPORT_221C
- ION_DEVICE_ID_EDGEPORT_22C
- ION_DEVICE_ID_EDGEPORT_22I
- ION_DEVICE_ID_EDGEPORT_2C
- ION_DEVICE_ID_EDGEPORT_2I
- ION_DEVICE_ID_EDGEPORT_2_DIN
- ION_DEVICE_ID_EDGEPORT_4
- ION_DEVICE_ID_EDGEPORT_412_4
- ION_DEVICE_ID_EDGEPORT_412_8
- ION_DEVICE_ID_EDGEPORT_42
- ION_DEVICE_ID_EDGEPORT_421
- ION_DEVICE_ID_EDGEPORT_4I
- ION_DEVICE_ID_EDGEPORT_4S
- ION_DEVICE_ID_EDGEPORT_4T
- ION_DEVICE_ID_EDGEPORT_4_DIN
- ION_DEVICE_ID_EDGEPORT_8
- ION_DEVICE_ID_EDGEPORT_8I
- ION_DEVICE_ID_EDGEPORT_8R
- ION_DEVICE_ID_EDGEPORT_8RR
- ION_DEVICE_ID_EDGEPORT_8S
- ION_DEVICE_ID_EDGEPORT_8_DUAL_CPU
- ION_DEVICE_ID_EDGEPORT_COMPATIBLE
- ION_DEVICE_ID_EDGEPORT_E
- ION_DEVICE_ID_EDGEPORT_PARALLEL_PORT
- ION_DEVICE_ID_EPOS44
- ION_DEVICE_ID_GENERATION_1
- ION_DEVICE_ID_GENERATION_2
- ION_DEVICE_ID_GENERATION_3
- ION_DEVICE_ID_GENERATION_4
- ION_DEVICE_ID_HUB_MASK
- ION_DEVICE_ID_MT4X56USB
- ION_DEVICE_ID_PLUS_PWR_HP4C
- ION_DEVICE_ID_PLUS_PWR_HP4CD
- ION_DEVICE_ID_PLUS_PWR_PCI
- ION_DEVICE_ID_RAPIDPORT_4
- ION_DEVICE_ID_TI3410_EDGEPORT_1
- ION_DEVICE_ID_TI3410_EDGEPORT_1I
- ION_DEVICE_ID_TI_EDGEPORT_1
- ION_DEVICE_ID_TI_EDGEPORT_2
- ION_DEVICE_ID_TI_EDGEPORT_21
- ION_DEVICE_ID_TI_EDGEPORT_21C
- ION_DEVICE_ID_TI_EDGEPORT_221C
- ION_DEVICE_ID_TI_EDGEPORT_22C
- ION_DEVICE_ID_TI_EDGEPORT_22I
- ION_DEVICE_ID_TI_EDGEPORT_2C
- ION_DEVICE_ID_TI_EDGEPORT_2I
- ION_DEVICE_ID_TI_EDGEPORT_4
- ION_DEVICE_ID_TI_EDGEPORT_416
- ION_DEVICE_ID_TI_EDGEPORT_416B
- ION_DEVICE_ID_TI_EDGEPORT_42
- ION_DEVICE_ID_TI_EDGEPORT_421
- ION_DEVICE_ID_TI_EDGEPORT_4I
- ION_DEVICE_ID_TI_EDGEPORT_4S
- ION_DEVICE_ID_TI_EDGEPORT_8
- ION_DEVICE_ID_TI_EDGEPORT_8S
- ION_DEVICE_ID_TI_TI3410_EDGEPORT_1
- ION_DEVICE_ID_TI_TI3410_EDGEPORT_1I
- ION_DEVICE_ID_UNCONFIGURED_EDGE_DEVICE
- ION_DEVICE_ID_WP_ACCELERATION
- ION_DEVICE_ID_WP_DISTANCE
- ION_DEVICE_ID_WP_HUMIDITY
- ION_DEVICE_ID_WP_LIGHT
- ION_DEVICE_ID_WP_MOISTURE
- ION_DEVICE_ID_WP_MOTION
- ION_DEVICE_ID_WP_POWER
- ION_DEVICE_ID_WP_PROXIMITY
- ION_DEVICE_ID_WP_PROX_DIST
- ION_DEVICE_ID_WP_RADIATION
- ION_DEVICE_ID_WP_TEMPERATURE
- ION_DEVICE_ID_WP_UNSERIALIZED
- ION_FLAG_CACHED
- ION_GENERATION_MASK
- ION_HEAP_FLAG_DEFER_FREE
- ION_HEAP_TYPE_CARVEOUT
- ION_HEAP_TYPE_CHUNK
- ION_HEAP_TYPE_CUSTOM
- ION_HEAP_TYPE_DMA
- ION_HEAP_TYPE_SYSTEM
- ION_HEAP_TYPE_SYSTEM_CONTIG
- ION_IOC_ALLOC
- ION_IOC_HEAP_QUERY
- ION_IOC_MAGIC
- ION_NUM_HEAP_IDS
- ION_OEM_ID_AGILENT
- ION_OEM_ID_GENERIC
- ION_OEM_ID_ION
- ION_OEM_ID_MAC
- ION_OEM_ID_MEGAWOLF
- ION_OEM_ID_MULTITECH
- ION_OEM_ID_NLYNX
- ION_PRIV_FLAG_SHRINKER_FREE
- IOP
- IOP32X_MAX_RAM_SIZE
- IOP3XX_AAU_PHYS_BASE
- IOP3XX_AAU_UPPER_PA
- IOP3XX_APMCR
- IOP3XX_APMCSR
- IOP3XX_ASIR
- IOP3XX_ASVIR
- IOP3XX_ATUBIST
- IOP3XX_ATUCCR
- IOP3XX_ATUCLSR
- IOP3XX_ATUCMD
- IOP3XX_ATUCR
- IOP3XX_ATUCR_OUT_EN
- IOP3XX_ATUDID
- IOP3XX_ATUHTR
- IOP3XX_ATUILR
- IOP3XX_ATUIMR
- IOP3XX_ATUIPR
- IOP3XX_ATUISR
- IOP3XX_ATULT
- IOP3XX_ATUMGNT
- IOP3XX_ATUMLAT
- IOP3XX_ATURID
- IOP3XX_ATUSR
- IOP3XX_ATUVID
- IOP3XX_DMA_PHYS_BASE
- IOP3XX_DMA_UPPER_PA
- IOP3XX_EMISR
- IOP3XX_ERBAR
- IOP3XX_ERLR
- IOP3XX_ERTVR
- IOP3XX_ESR
- IOP3XX_GPID
- IOP3XX_GPIO_LINE
- IOP3XX_GPOD
- IOP3XX_GPOD_I2C0
- IOP3XX_GPOD_I2C1
- IOP3XX_GPOE
- IOP3XX_GTMR
- IOP3XX_GTSR
- IOP3XX_I2C_IO_SIZE
- IOP3XX_IABAR0
- IOP3XX_IABAR1
- IOP3XX_IABAR2
- IOP3XX_IABAR3
- IOP3XX_IALR0
- IOP3XX_IALR1
- IOP3XX_IALR2
- IOP3XX_IALR3
- IOP3XX_IAR
- IOP3XX_IATVR0
- IOP3XX_IATVR2
- IOP3XX_IATVR3
- IOP3XX_IAUBAR0
- IOP3XX_IAUBAR1
- IOP3XX_IAUBAR2
- IOP3XX_IAUBAR3
- IOP3XX_IBMR0
- IOP3XX_IBMR1
- IOP3XX_IBMR_SCL
- IOP3XX_IBMR_SDA
- IOP3XX_ICR0
- IOP3XX_ICR1
- IOP3XX_ICR_ALD_IE
- IOP3XX_ICR_BERR_IE
- IOP3XX_ICR_FAST_MODE
- IOP3XX_ICR_GCD
- IOP3XX_ICR_MABORT
- IOP3XX_ICR_MSTART
- IOP3XX_ICR_MSTOP
- IOP3XX_ICR_NACK
- IOP3XX_ICR_RXFULL_IE
- IOP3XX_ICR_SAD_IE
- IOP3XX_ICR_SCLEN
- IOP3XX_ICR_SSD_IE
- IOP3XX_ICR_TBYTE
- IOP3XX_ICR_TXEMPTY_IE
- IOP3XX_ICR_UE
- IOP3XX_ICR_UNIT_RESET
- IOP3XX_IDBR0
- IOP3XX_IDBR1
- IOP3XX_IDBR_MASK
- IOP3XX_IDR
- IOP3XX_IFHPR
- IOP3XX_IFTPR
- IOP3XX_IIMR
- IOP3XX_IISR
- IOP3XX_IMR0
- IOP3XX_IMR1
- IOP3XX_INIT_ATU_DEFAULT
- IOP3XX_INIT_ATU_DISABLE
- IOP3XX_INIT_ATU_ENABLE
- IOP3XX_IPHPR
- IOP3XX_IPTPR
- IOP3XX_ISAR0
- IOP3XX_ISAR1
- IOP3XX_ISAR_SAMASK
- IOP3XX_ISR0
- IOP3XX_ISR1
- IOP3XX_ISR_ALD
- IOP3XX_ISR_BBUSY
- IOP3XX_ISR_BERRD
- IOP3XX_ISR_CLEARBITS
- IOP3XX_ISR_GCAD
- IOP3XX_ISR_NACK
- IOP3XX_ISR_RXFULL
- IOP3XX_ISR_RXREAD
- IOP3XX_ISR_SAD
- IOP3XX_ISR_SSD
- IOP3XX_ISR_TXEMPTY
- IOP3XX_ISR_UNITBUSY
- IOP3XX_MAX_RAM_SIZE
- IOP3XX_MUCR
- IOP3XX_OCCAR
- IOP3XX_OCCDR
- IOP3XX_ODR
- IOP3XX_OFHPR
- IOP3XX_OFTPR
- IOP3XX_OIMR
- IOP3XX_OIOWTVR
- IOP3XX_OISR
- IOP3XX_OMR0
- IOP3XX_OMR1
- IOP3XX_OMWTVR0
- IOP3XX_OMWTVR1
- IOP3XX_OPHPR
- IOP3XX_OPTPR
- IOP3XX_OUDWTVR
- IOP3XX_OUMWTVR0
- IOP3XX_OUMWTVR1
- IOP3XX_PBBAR0
- IOP3XX_PBBAR1
- IOP3XX_PBBAR2
- IOP3XX_PBBAR3
- IOP3XX_PBBAR4
- IOP3XX_PBBAR5
- IOP3XX_PBCR
- IOP3XX_PBISR
- IOP3XX_PBLR0
- IOP3XX_PBLR1
- IOP3XX_PBLR2
- IOP3XX_PBLR3
- IOP3XX_PBLR4
- IOP3XX_PBLR5
- IOP3XX_PCIIRSR
- IOP3XX_PCIXCAPID
- IOP3XX_PCIXCMD
- IOP3XX_PCIXNEXT
- IOP3XX_PCIXSR
- IOP3XX_PCI_LOWER_IO_BA
- IOP3XX_PCI_LOWER_IO_PA
- IOP3XX_PCI_LOWER_MEM_BA
- IOP3XX_PCI_LOWER_MEM_PA
- IOP3XX_PCI_MEM_WINDOW_SIZE
- IOP3XX_PCSR
- IOP3XX_PCSR_IN_Q_BUSY
- IOP3XX_PCSR_OUT_Q_BUSY
- IOP3XX_PDSCR
- IOP3XX_PERCR0
- IOP3XX_PERIPHERAL_PHYS_BASE
- IOP3XX_PERIPHERAL_SIZE
- IOP3XX_PERIPHERAL_UPPER_PA
- IOP3XX_PERIPHERAL_UPPER_VA
- IOP3XX_PERIPHERAL_VIRT_BASE
- IOP3XX_PMBR0
- IOP3XX_PMBR1
- IOP3XX_PMBR2
- IOP3XX_PMCAPID
- IOP3XX_PMMR_PHYS_TO_VIRT
- IOP3XX_PMNEXT
- IOP3XX_QBAR
- IOP3XX_REG_ADDR
- IOP3XX_TIMER_REG
- IOP3XX_TU_TCR0
- IOP3XX_TU_TCR1
- IOP3XX_TU_TISR
- IOP3XX_TU_TMR0
- IOP3XX_TU_TMR1
- IOP3XX_TU_TRR0
- IOP3XX_TU_TRR1
- IOP3XX_TU_WDTCR
- IOPA
- IOPAD
- IOPAD_DUMB12
- IOPAD_DUMB16GPIO
- IOPAD_DUMB16SPI
- IOPAD_DUMB16_DUMB16
- IOPAD_DUMB16_SMART8GPIO
- IOPAD_DUMB16_SMART8SPI
- IOPAD_DUMB18GPIO
- IOPAD_DUMB18SPI
- IOPAD_DUMB18_SMART8
- IOPAD_DUMB24
- IOPAD_SMART16SPI
- IOPAD_SMART18SPI
- IOPAD_SMART8BOTH
- IOPAD_SMART8_SMART8
- IOPAGE_MASK
- IOPB_ACC_GRP
- IOPB_BYTE_LEFT_TO_XFER
- IOPB_BYTE_TO_XFER_0
- IOPB_BYTE_TO_XFER_1
- IOPB_BYTE_TO_XFER_2
- IOPB_BYTE_TO_XFER_3
- IOPB_CHIP_ID_1
- IOPB_CHIP_TYPE_REV
- IOPB_DEV_ID
- IOPB_DMA_CFG0
- IOPB_DMA_CFG1
- IOPB_DMA_REG_WR
- IOPB_FLAG_REG
- IOPB_FLASH_DATA
- IOPB_FLASH_PAGE
- IOPB_GPIO_CNTL
- IOPB_GPIO_DATA
- IOPB_HOST_BYTE_CNT
- IOPB_INTR_ENABLES
- IOPB_INTR_STATUS_REG
- IOPB_MEM_CFG
- IOPB_PCI_INT_CFG
- IOPB_PLL_TEST
- IOPB_RAM_BIST
- IOPB_RAM_DATA
- IOPB_RES_ADDR_11
- IOPB_RES_ADDR_13
- IOPB_RES_ADDR_15
- IOPB_RES_ADDR_17
- IOPB_RES_ADDR_19
- IOPB_RES_ADDR_1A
- IOPB_RES_ADDR_1B
- IOPB_RES_ADDR_1C
- IOPB_RES_ADDR_1D
- IOPB_RES_ADDR_1E
- IOPB_RES_ADDR_1F
- IOPB_RES_ADDR_2D
- IOPB_RES_ADDR_2F
- IOPB_RES_ADDR_31
- IOPB_RES_ADDR_32
- IOPB_RES_ADDR_35
- IOPB_RES_ADDR_36
- IOPB_RES_ADDR_37
- IOPB_RES_ADDR_3B
- IOPB_RES_ADDR_3D
- IOPB_RES_ADDR_3E
- IOPB_RES_ADDR_3F
- IOPB_RES_ADDR_4
- IOPB_RES_ADDR_5
- IOPB_RES_ADDR_7
- IOPB_RES_ADDR_9
- IOPB_RES_ADDR_B
- IOPB_RES_ADDR_C
- IOPB_RES_ADDR_D
- IOPB_RES_ADDR_F
- IOPB_RFIFO_CNT
- IOPB_RISC_CSR
- IOPB_SCSI_BYTE_CNT
- IOPB_SCSI_CTRL
- IOPB_SCSI_DATA
- IOPB_SCSI_DATA_HSHK
- IOPB_SDMA_STATUS
- IOPB_SOFT_OVER_WR
- IOPB_TICKLE
- IOPD
- IOPDIR_VALID
- IOPDW_COMMA
- IOPDW_COMMB
- IOPDW_RAM_DATA
- IOPDW_RDMA_ADDR0
- IOPDW_RDMA_ADDR1
- IOPDW_RDMA_COUNT
- IOPDW_RDMA_ERROR
- IOPDW_RES_ADDR_0
- IOPDW_RES_ADDR_10
- IOPDW_RES_ADDR_1C
- IOPDW_RES_ADDR_8
- IOPDW_RES_ADDR_C
- IOPDW_SDMA_ADDR0
- IOPDW_SDMA_ADDR1
- IOPDW_SDMA_COUNT
- IOPDW_SDMA_ERROR
- IOPERM
- IOPFNSHIFT
- IOPG
- IOPGD_MASK
- IOPGD_SECTION
- IOPGD_SHIFT
- IOPGD_SIZE
- IOPGD_SUPER
- IOPGD_TABLE
- IOPGD_TABLE_SIZE
- IOPGOFF
- IOPGSIZE
- IOPIN_UPDATE
- IOPI_IOCLOGINFO_H_INCLUDED
- IOPLL
- IOPLL_HALF
- IOPLL_INT
- IOPLL_INT_MUX
- IOPLL_POST_SRC
- IOPLL_PRE_SRC
- IOPLL_TO_FPD
- IOPMU_INBOUND_INT_DOORBELL
- IOPMU_INBOUND_INT_ERROR
- IOPMU_INBOUND_INT_MSG0
- IOPMU_INBOUND_INT_MSG1
- IOPMU_INBOUND_INT_POSTQUEUE
- IOPMU_INBOUND_MSG0_FLUSH
- IOPMU_INBOUND_MSG0_MAX
- IOPMU_INBOUND_MSG0_NOP
- IOPMU_INBOUND_MSG0_RESET
- IOPMU_INBOUND_MSG0_RESET_COMM
- IOPMU_INBOUND_MSG0_SHUTDOWN
- IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK
- IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK
- IOPMU_OUTBOUND_INT_DOORBELL
- IOPMU_OUTBOUND_INT_MSG0
- IOPMU_OUTBOUND_INT_MSG1
- IOPMU_OUTBOUND_INT_PCI
- IOPMU_OUTBOUND_INT_POSTQUEUE
- IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0
- IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX
- IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0
- IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX
- IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0
- IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX
- IOPMU_QUEUE_ADDR_HOST_BIT
- IOPMU_QUEUE_EMPTY
- IOPMU_QUEUE_MASK_HOST_BITS
- IOPMU_QUEUE_REQUEST_RESULT_BIT
- IOPMU_QUEUE_REQUEST_SIZE_BIT
- IOPM_ALLOC_ORDER
- IOPORT
- IOPORT_MAP_BASE
- IOPORT_RESOURCE_END
- IOPORT_RESOURCE_START
- IOPORT_SIZE
- IOPRIO_BE_NR
- IOPRIO_CLASS_BE
- IOPRIO_CLASS_IDLE
- IOPRIO_CLASS_NONE
- IOPRIO_CLASS_RT
- IOPRIO_CLASS_SHIFT
- IOPRIO_H
- IOPRIO_NORM
- IOPRIO_PRIO_CLASS
- IOPRIO_PRIO_DATA
- IOPRIO_PRIO_MASK
- IOPRIO_PRIO_VALUE
- IOPRIO_WHO_PGRP
- IOPRIO_WHO_PROCESS
- IOPRIO_WHO_USER
- IOPTE_64K
- IOPTE_CACHE
- IOPTE_CONSISTENT
- IOPTE_CONTEXT
- IOPTE_INTRA
- IOPTE_IS_DUMMY
- IOPTE_LARGE
- IOPTE_MASK
- IOPTE_PAGE
- IOPTE_SHIFT
- IOPTE_SIZE
- IOPTE_SMALL
- IOPTE_STBUF
- IOPTE_STREAMING
- IOPTE_TABLE_SIZE
- IOPTE_VALID
- IOPTE_WAZ
- IOPTE_WRITE
- IOPU_CTRL1
- IOPU_CTRL2
- IOPW_CHIP_ID_0
- IOPW_CTRL_REG
- IOPW_EE_CMD
- IOPW_EE_DATA
- IOPW_FLASH_ADDR
- IOPW_HSHK_CFG
- IOPW_IX
- IOPW_PC
- IOPW_QP
- IOPW_Q_BASE
- IOPW_RAM_ADDR
- IOPW_RAM_DATA
- IOPW_RES_ADDR_08
- IOPW_RES_ADDR_10
- IOPW_RES_ADDR_14
- IOPW_RES_ADDR_18
- IOPW_RES_ADDR_20
- IOPW_RES_ADDR_2C
- IOPW_RES_ADDR_2E
- IOPW_RES_ADDR_3C
- IOPW_RFIFO_DATA
- IOPW_RISC_CSR
- IOPW_SCSI_CFG0
- IOPW_SCSI_CFG1
- IOPW_SCSI_CTRL
- IOPW_SCSI_DATA
- IOPW_SCSI_DATA_HSHK
- IOPW_SEL_MASK
- IOPW_SFIFO_CNT
- IOPW_SP
- IOPW_SXFR_CNTH
- IOPW_SXFR_CNTL
- IOPW_SXFR_STATUS
- IOP_ADDR_ALIVE
- IOP_ADDR_MAX_RECV_CHAN
- IOP_ADDR_MAX_SEND_CHAN
- IOP_ADDR_PATCH_CTRL
- IOP_ADDR_RECV_MSG
- IOP_ADDR_RECV_STATE
- IOP_ADDR_SEND_MSG
- IOP_ADDR_SEND_STATE
- IOP_ADMA_H
- IOP_ADMA_MAX_BYTE_COUNT
- IOP_ADMA_NUM_SRC_TEST
- IOP_ADMA_SLOT_SIZE
- IOP_ADMA_STATUS_BUSY
- IOP_ADMA_TEST_SIZE
- IOP_ADMA_THRESHOLD
- IOP_ADMA_XOR_MAX_BYTE_COUNT
- IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT
- IOP_AUTOINC
- IOP_BLOCK_COMMAND_FLUSH
- IOP_BLOCK_COMMAND_READ
- IOP_BLOCK_COMMAND_SHUTDOWN
- IOP_BLOCK_COMMAND_VERIFY
- IOP_BLOCK_COMMAND_WRITE
- IOP_BYPASS
- IOP_CONFIG_HIGH
- IOP_CONFIG_LOW
- IOP_CTRL
- IOP_DEFAULT_READLINK
- IOP_DMAINACTIVE
- IOP_DMA_SPEED
- IOP_EEP_CMD
- IOP_EEP_DATA
- IOP_EXTRA_CONTROL
- IOP_FASTPERM
- IOP_FIFO_H
- IOP_FIFO_L
- IOP_HWINT
- IOP_HWSOFT_RESET
- IOP_INT0
- IOP_INT1
- IOP_INT_ACK
- IOP_IRQ
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_DEFAULT
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_DNM
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_FORM
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_PERSIST
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_PN
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_PT
- IOP_LOGINFO_CODE_CONFIG_INVALID_PAGE_RT
- IOP_LOGINFO_CODE_DIAG_MSG_ERROR
- IOP_LOGINFO_CODE_ENCL_MGMT_INVALID_BUS_ID_ERR0R
- IOP_LOGINFO_CODE_ENCL_MGMT_READ_ACTION_ERR0R
- IOP_LOGINFO_CODE_FWUPLOAD_DMA_FAILURE
- IOP_LOGINFO_CODE_FWUPLOAD_ENTIRE_FLASH_UPLOAD_FAILED
- IOP_LOGINFO_CODE_FWUPLOAD_NO_FLASH_AVAILABLE
- IOP_LOGINFO_CODE_FWUPLOAD_REGION_UPLOAD_FAILED
- IOP_LOGINFO_CODE_FWUPLOAD_UNKNOWN_IMAGE_TYPE
- IOP_LOGINFO_CODE_FWUPLOAD_WRONG_IMAGE_SIZE
- IOP_LOGINFO_CODE_INVALID_SAS_ADDRESS
- IOP_LOGINFO_CODE_LOG_TIMESTAMP_EVENT
- IOP_LOGINFO_CODE_TARGET_ASSIST_TERMINATED
- IOP_LOGINFO_CODE_TARGET_MODE_ABORT_ALL_IO
- IOP_LOGINFO_CODE_TARGET_MODE_ABORT_EXACT_IO
- IOP_LOGINFO_CODE_TARGET_MODE_ABORT_EXACT_IO_REQ
- IOP_LOGINFO_CODE_TARGET_STATUS_SEND_TERMINATED
- IOP_LOGINFO_CODE_TASK_TERMINATED
- IOP_LOGINFO_CODE_UNUSED2
- IOP_LOOKUP
- IOP_MIN_RANGE
- IOP_MSGSTATUS_COMPLETE
- IOP_MSGSTATUS_SENT
- IOP_MSGSTATUS_UNSOL
- IOP_MSGSTATUS_UNUSED
- IOP_MSGSTATUS_WAITING
- IOP_MSG_COMPLETE
- IOP_MSG_IDLE
- IOP_MSG_LEN
- IOP_MSG_NEW
- IOP_MSG_RCVD
- IOP_NOFOLLOW
- IOP_NUM_ISM
- IOP_NUM_SCC
- IOP_PARANOIA
- IOP_PLL_0_ACTIVE_MDIV_Ch0_OFFSET
- IOP_PLL_0_ACTIVE_MDIV_Ch1_OFFSET
- IOP_PLL_0_ACTIVE_MDIV_Ch2_OFFSET
- IOP_PLL_0_ACTIVE_NDIV_FRAC
- IOP_PLL_0_ACTIVE_NDIV_OFFSET
- IOP_PLL_0_CONTROL_OFFSET
- IOP_PLL_0_MACRO_OFFSET
- IOP_PLL_0_MDIV_Ch0_OFFSET
- IOP_PLL_0_MDIV_Ch1_OFFSET
- IOP_PLL_0_MDIV_Ch2_OFFSET
- IOP_PLL_0_RESET_OFFSET
- IOP_PLL_0_USER_NDIV_FRAC
- IOP_PLL_0_USER_NDIV_OFFSET
- IOP_RAM_ADDR
- IOP_RAM_DATA
- IOP_RCSR_WDT
- IOP_RDUMP
- IOP_REG_AX
- IOP_REG_DA0
- IOP_REG_DA1
- IOP_REG_DC0
- IOP_REG_DC1
- IOP_REG_FLAG
- IOP_REG_ID
- IOP_REG_IFC
- IOP_REG_IH
- IOP_REG_IX
- IOP_REG_PC
- IOP_REG_QP
- IOP_REG_SB
- IOP_REG_SC
- IOP_REQUEST_FLAG_ADDR_BITS
- IOP_REQUEST_FLAG_BIST_REQUEST
- IOP_REQUEST_FLAG_OUTPUT_CONTEXT
- IOP_REQUEST_FLAG_REMAPPED
- IOP_REQUEST_FLAG_SYNC_REQUEST
- IOP_REQUEST_TYPE_BLOCK_COMMAND
- IOP_REQUEST_TYPE_GET_CONFIG
- IOP_REQUEST_TYPE_IOCTL_COMMAND
- IOP_REQUEST_TYPE_MAX
- IOP_REQUEST_TYPE_SCSI_COMMAND
- IOP_REQUEST_TYPE_SET_CONFIG
- IOP_RESET
- IOP_RESET_ALWAYS
- IOP_RESET_FW_FIB_DUMP
- IOP_RESULT_BAD_TARGET
- IOP_RESULT_BUSY
- IOP_RESULT_CHECK_CONDITION
- IOP_RESULT_FAIL
- IOP_RESULT_INVALID_REQUEST
- IOP_RESULT_PENDING
- IOP_RESULT_RESET
- IOP_RESULT_SUCCESS
- IOP_RUN
- IOP_SIG_BYTE
- IOP_SIG_WORD
- IOP_SRC_RESET_MASK
- IOP_STATUS
- IOP_SW_INIT_LOGIC
- IOP_SYN_OFFSET
- IOP_TMR_EN
- IOP_TMR_PRIVILEGED
- IOP_TMR_RATIO_1_1
- IOP_TMR_RELOAD
- IOP_VERSION
- IOP_WDTCR_DIS
- IOP_WDTCR_DIS_ARM
- IOP_WDTCR_EN
- IOP_WDTCR_EN_ARM
- IOP_XATTR
- IORDY
- IOREGION_ALIGNMENT
- IOREGION_LENGTH
- IOREGION_OFFSET
- IOREMAP_BASE
- IOREMAP_END
- IOREMAP_MAX_ORDER
- IOREMAP_START
- IOREMAP_TOP
- IOREN_CTRL1
- IOREN_CTRL2
- IORESOURCE_AUTO
- IORESOURCE_BITS
- IORESOURCE_BUS
- IORESOURCE_BUSY
- IORESOURCE_CACHEABLE
- IORESOURCE_DISABLED
- IORESOURCE_DMA
- IORESOURCE_DMA_16BIT
- IORESOURCE_DMA_8AND16BIT
- IORESOURCE_DMA_8BIT
- IORESOURCE_DMA_BYTE
- IORESOURCE_DMA_COMPATIBLE
- IORESOURCE_DMA_MASTER
- IORESOURCE_DMA_SPEED_MASK
- IORESOURCE_DMA_TYPEA
- IORESOURCE_DMA_TYPEB
- IORESOURCE_DMA_TYPEF
- IORESOURCE_DMA_TYPE_MASK
- IORESOURCE_DMA_WORD
- IORESOURCE_EXCLUSIVE
- IORESOURCE_EXT_TYPE_BITS
- IORESOURCE_IO
- IORESOURCE_IO_16BIT_ADDR
- IORESOURCE_IO_FIXED
- IORESOURCE_IO_SPARSE
- IORESOURCE_IRQ
- IORESOURCE_IRQ_HIGHEDGE
- IORESOURCE_IRQ_HIGHLEVEL
- IORESOURCE_IRQ_LOWEDGE
- IORESOURCE_IRQ_LOWLEVEL
- IORESOURCE_IRQ_OPTIONAL
- IORESOURCE_IRQ_SHAREABLE
- IORESOURCE_MEM
- IORESOURCE_MEM_16BIT
- IORESOURCE_MEM_32BIT
- IORESOURCE_MEM_64
- IORESOURCE_MEM_8AND16BIT
- IORESOURCE_MEM_8BIT
- IORESOURCE_MEM_CACHEABLE
- IORESOURCE_MEM_EXPANSIONROM
- IORESOURCE_MEM_RANGELENGTH
- IORESOURCE_MEM_SHADOWABLE
- IORESOURCE_MEM_TYPE_MASK
- IORESOURCE_MEM_WRITEABLE
- IORESOURCE_MUXED
- IORESOURCE_PCI_EA_BEI
- IORESOURCE_PCI_FIXED
- IORESOURCE_PREFETCH
- IORESOURCE_RANGELENGTH
- IORESOURCE_READONLY
- IORESOURCE_REG
- IORESOURCE_ROM_ENABLE
- IORESOURCE_ROM_SHADOW
- IORESOURCE_SHADOWABLE
- IORESOURCE_SIZEALIGN
- IORESOURCE_STARTALIGN
- IORESOURCE_SYSRAM
- IORESOURCE_SYSTEM_RAM
- IORESOURCE_TYPE_BITS
- IORESOURCE_UNSET
- IORESOURCE_WINDOW
- IORES_DESC_ACPI_NV_STORAGE
- IORES_DESC_ACPI_TABLES
- IORES_DESC_CRASH_KERNEL
- IORES_DESC_DEVICE_PRIVATE_MEMORY
- IORES_DESC_NONE
- IORES_DESC_PERSISTENT_MEMORY
- IORES_DESC_PERSISTENT_MEMORY_LEGACY
- IORES_DESC_RESERVED
- IORES_MAP_ENCRYPTED
- IORES_MAP_SYSTEM_RAM
- IORING_ENTER_GETEVENTS
- IORING_ENTER_SQ_WAKEUP
- IORING_FEAT_SINGLE_MMAP
- IORING_FSYNC_DATASYNC
- IORING_MAX_ENTRIES
- IORING_MAX_FIXED_FILES
- IORING_OFF_CQ_RING
- IORING_OFF_SQES
- IORING_OFF_SQ_RING
- IORING_OP_FSYNC
- IORING_OP_NOP
- IORING_OP_POLL_ADD
- IORING_OP_POLL_REMOVE
- IORING_OP_READV
- IORING_OP_READ_FIXED
- IORING_OP_RECVMSG
- IORING_OP_SENDMSG
- IORING_OP_SYNC_FILE_RANGE
- IORING_OP_TIMEOUT
- IORING_OP_WRITEV
- IORING_OP_WRITE_FIXED
- IORING_REGISTER_BUFFERS
- IORING_REGISTER_EVENTFD
- IORING_REGISTER_FILES
- IORING_SETUP_IOPOLL
- IORING_SETUP_SQPOLL
- IORING_SETUP_SQ_AFF
- IORING_SQ_NEED_WAKEUP
- IORING_UNREGISTER_BUFFERS
- IORING_UNREGISTER_EVENTFD
- IORING_UNREGISTER_FILES
- IORR_BASE0
- IORR_MASK0
- IORS_PER_SET
- IORT_IOMMU_TYPE
- IORT_IRQ_MASK
- IORT_IRQ_TRIGGER_MASK
- IORT_MSI_TYPE
- IORT_SMMU_V3_PMCG_GENERIC
- IORT_SMMU_V3_PMCG_HISI_HIP08
- IORT_TYPE_MASK
- IORXR
- IOR_DBG
- IOR_MSG
- IOR_SET_OFFSET
- IOR_WARN
- IOSAPIC_DELIVERY_SHIFT
- IOSAPIC_DEST_SHIFT
- IOSAPIC_EDGE
- IOSAPIC_EOI
- IOSAPIC_EXTINT
- IOSAPIC_FIXED
- IOSAPIC_INIT
- IOSAPIC_IRDT_ENABLE
- IOSAPIC_IRDT_ENTRY
- IOSAPIC_IRDT_ENTRY_HI
- IOSAPIC_IRDT_ID_EID_SHIFT
- IOSAPIC_IRDT_LEVEL_TRIG
- IOSAPIC_IRDT_MAX_ENTRY
- IOSAPIC_IRDT_MODE_LPRI
- IOSAPIC_IRDT_PO_LOW
- IOSAPIC_LEVEL
- IOSAPIC_LOWEST_PRIORITY
- IOSAPIC_MASK
- IOSAPIC_MASK_SHIFT
- IOSAPIC_MAX_ENTRY_MASK
- IOSAPIC_MAX_ENTRY_SHIFT
- IOSAPIC_NMI
- IOSAPIC_PMI
- IOSAPIC_POLARITY_SHIFT
- IOSAPIC_POL_HIGH
- IOSAPIC_POL_LOW
- IOSAPIC_REG_EOI
- IOSAPIC_REG_SELECT
- IOSAPIC_REG_VERSION
- IOSAPIC_REG_WINDOW
- IOSAPIC_RTE_HIGH
- IOSAPIC_RTE_LOW
- IOSAPIC_TRIGGER_SHIFT
- IOSAPIC_VECTOR_MASK
- IOSAPIC_VERSION
- IOSAPIC_VERSION_MASK
- IOSAPIC_WINDOW
- IOSECTION_MASK
- IOSECTION_SHIFT
- IOSECTION_SIZE
- IOSF_BAR_SHIFT
- IOSF_BYTE_ENABLES_SHIFT
- IOSF_CPU_POWER_BUDGET_CTL_BYT
- IOSF_CPU_POWER_BUDGET_CTL_TNG
- IOSF_DEVFN_SHIFT
- IOSF_MBI_SYMS_H
- IOSF_NC_FB_GFX_FMAX_FUSE_HI
- IOSF_NC_FB_GFX_FMAX_FUSE_LO
- IOSF_NC_FB_GFX_FREQ_FUSE
- IOSF_OPCODE_SHIFT
- IOSF_PORT_BUNIT
- IOSF_PORT_CCK
- IOSF_PORT_CCU
- IOSF_PORT_DPIO
- IOSF_PORT_DPIO_2
- IOSF_PORT_FLISDSI
- IOSF_PORT_GPIO_NC
- IOSF_PORT_GPIO_SC
- IOSF_PORT_GPIO_SUS
- IOSF_PORT_NC
- IOSF_PORT_PUNIT
- IOSF_PORT_SHIFT
- IOSF_SB_BUSY
- IOSPA
- IOSPACE
- IOSP_BUILD_CMD_HDR1
- IOSP_BUILD_DATA_HDR1
- IOSP_BUILD_DATA_HDR2
- IOSP_CMD_CHASE_PORT
- IOSP_CMD_CLEAR_BREAK
- IOSP_CMD_CLOSE_PORT
- IOSP_CMD_HDR_SIZE
- IOSP_CMD_OPEN_PORT
- IOSP_CMD_RX_CHECK_REQ
- IOSP_CMD_SET_BREAK
- IOSP_CMD_SET_RX_FLOW
- IOSP_CMD_SET_TX_FLOW
- IOSP_CMD_SET_XOFF_CHAR
- IOSP_CMD_SET_XON_CHAR
- IOSP_CMD_STAT_BIT
- IOSP_DATA_HDR_SIZE
- IOSP_EXT4_STATUS
- IOSP_EXT_CMD
- IOSP_EXT_STATUS
- IOSP_EXT_STATUS_CHASE_FAIL
- IOSP_EXT_STATUS_CHASE_PASS
- IOSP_EXT_STATUS_CHASE_RSP
- IOSP_EXT_STATUS_RX_CHECK_RSP
- IOSP_GET_HDR_DATA_LEN
- IOSP_GET_HDR_PORT
- IOSP_GET_STATUS_CODE
- IOSP_GET_STATUS_LEN
- IOSP_MAX_DATA_LENGTH
- IOSP_PORT_MASK
- IOSP_RX_FLOW_DSR_SENSITIVITY
- IOSP_RX_FLOW_DTR
- IOSP_RX_FLOW_RTS
- IOSP_RX_FLOW_XON_XOFF
- IOSP_STATUS_IS_2BYTE
- IOSP_STATUS_IS_3BYTE
- IOSP_STATUS_IS_4BYTE
- IOSP_STATUS_LSR
- IOSP_STATUS_LSR_DATA
- IOSP_STATUS_MSR
- IOSP_STATUS_OPEN_RSP
- IOSP_TX_FLOW_CTS
- IOSP_TX_FLOW_DCD
- IOSP_TX_FLOW_DSR
- IOSP_TX_FLOW_XOFF_CONTINUE
- IOSP_TX_FLOW_XON_XOFF
- IOSP_TX_TOGGLE_RTS
- IOSP_WRITE_UART_REG
- IOSQE_FIXED_FILE
- IOSQE_IO_DRAIN
- IOSQE_IO_LINK
- IOSR
- IOSS_TELEM_EVENT_CTL_READ
- IOSS_TELEM_EVENT_CTL_WRITE
- IOSS_TELEM_EVENT_READ
- IOSS_TELEM_EVENT_WRITE
- IOSS_TELEM_EVT_CTRL_WRITE_SIZE
- IOSS_TELEM_EVT_WRITE_SIZE
- IOSS_TELEM_INFO_READ
- IOSS_TELEM_READ_WORD
- IOSS_TELEM_TRACE_CTL_READ
- IOSS_TELEM_TRACE_CTL_WRITE
- IOSS_TELEM_WRITE_FOURBYTES
- IOSTATUS_FE
- IOSTATUS_RY
- IOSTE_H
- IOSTE_NPPT_Mask
- IOSTE_PS_16M
- IOSTE_PS_1M
- IOSTE_PS_4K
- IOSTE_PS_64K
- IOSTE_PS_Mask
- IOSTE_PT_Base_RPN_Mask
- IOSTE_V
- IOST_BASE_ADDR_HI
- IOST_BASE_ADDR_LO
- IOSUPER_MASK
- IOSUPER_SHIFT
- IOSUPER_SIZE
- IOSYNC
- IOS_DIRECT_BASE
- IOS_DIRECT_MASK
- IOS_DIRECT_ROUTE
- IOS_DIST_BASE
- IOS_DIST_MASK
- IOS_DIST_ROUTE
- IOS_ERROR_THRESHOLD
- IOT2040_UART1_MASK
- IOT2040_UART2_SHIFT
- IOT2040_UARTS_DEFAULT_MODE
- IOT2040_UARTS_ENABLE
- IOT2040_UARTS_GPIO_HI_MODE
- IOT2040_UARTS_GPIO_LO_MODE
- IOT2040_UART_MODE_RS232
- IOT2040_UART_MODE_RS422
- IOT2040_UART_MODE_RS485
- IOT2040_UART_TERMINATE_BUS
- IOTAC_IODC_10_BIT
- IOTAC_IODC_12_BIT
- IOTAC_IODC_16_BIT
- IOTAC_IODC_MASK
- IOTAC_MSK_MASK
- IOTAC_MSK_SHIFT
- IOTAC_RE
- IOTAC_RSPI
- IOTAC_SA_MASK
- IOTAC_SA_SHIFT
- IOTAC_WE
- IOTAC_WSE
- IOTAC_WSPI
- IOTCR_DDP
- IOTCR_DFI
- IOTCR_DTI
- IOTCR_HRV
- IOTCR_ITD
- IOTCR_JTE
- IOTCR_PPE
- IOTCR_SRV
- IOTFIFO_BA_MASK
- IOTFIFO_BA_SHIFT
- IOTFIFO_OF
- IOTFIFO_SPIOF
- IOTFIFO_S_MASK
- IOTFIFO_S_SHIFT
- IOTFP_CA_MASK
- IOTFP_CA_SHIFT
- IOTFP_PA_MASK
- IOTFP_PA_SHIFT
- IOTFR_ALL
- IOTFR_A_MASK
- IOTFR_A_SHIFT
- IOTFR_D_MASK
- IOTFR_D_SHIFT
- IOTFR_R_MASK
- IOTFR_R_SHIFT
- IOTFR_VL
- IOTRRD_D_MASK
- IOTRRD_D_SHIFT
- IOTRRD_RDV
- IOTXR
- IOTYPE
- IOTYPE_POLL
- IOTYPE_READ
- IOTYPE_RX
- IOTYPE_SYNC
- IOTYPE_TX
- IOTYPE_WRITE
- IOUNIT_BMAP1_END
- IOUNIT_BMAP1_START
- IOUNIT_BMAP2_END
- IOUNIT_BMAP2_START
- IOUNIT_BMAPM_END
- IOUNIT_BMAPM_START
- IOUNIT_DMA_BASE
- IOUNIT_DMA_SIZE
- IOUNIT_DVMA_SIZE
- IOUPTE_CACHE
- IOUPTE_INTRA
- IOUPTE_PAGE
- IOUPTE_PARITY
- IOUPTE_STREAM
- IOUPTE_VALID
- IOUPTE_WRITE
- IOU_SWITCH
- IOUnitPage0_t
- IOUnitPage1_t
- IOUnitPage2_t
- IOUnitPage3_t
- IOUnitPage4_t
- IOVA_ANCHOR
- IOVA_FQ_SIZE
- IOVA_FQ_TIMEOUT
- IOVA_MAG_SIZE
- IOVA_PFN
- IOVA_RANGE_CACHE_MAX_SIZE
- IOVA_START_ADDR
- IOVA_START_PFN
- IOVP_MASK
- IOVP_SHIFT
- IOVP_SIZE
- IOVR
- IOV_111
- IOV_111_OFFSET
- IOV_1V8
- IOV_3V0
- IOV_3V3
- IOV_BCN_LI_BCN
- IOV_MPC
- IOV_QTXPOWER
- IOV_RTSTHRESH
- IOWAIT_BOOST_MIN
- IOWAIT_IB_SE
- IOWAIT_PENDING_IB
- IOWAIT_PENDING_TID
- IOWAIT_PRIORITY_STARVE_SHIFT
- IOWAIT_SES
- IOWAIT_TID_SE
- IOWARRIOR_MINOR_BASE
- IOWA_MAX_BUS
- IOW_GETINFO
- IOW_READ
- IOW_WRITE
- IO_4I4O
- IO_4P4O
- IO_68_RANDOM_TOGGLE1
- IO_68_RANDOM_TOGGLE2
- IO_6A_PAUSE_PLAYBACK_BIT8
- IO_6A_PAUSE_PLAYBACK_BIT9
- IO_6A_SOMETHING1_GAMEPORT
- IO_6A_SOMETHING2_GAMEPORT
- IO_8I
- IO_8O
- IO_8P
- IO_ABORTED
- IO_ABORT_DELAYED
- IO_ABORT_IN_PROGRESS
- IO_ABORT_RESET
- IO_ACCEL_INELIGIBLE
- IO_ACCESS_ENB
- IO_ADDR1
- IO_ADDR2
- IO_ADDRESS
- IO_ADDR_SELECT
- IO_ADRESS_ALIAS
- IO_APB_PHYS
- IO_APB_SIZE
- IO_APB_VIRT
- IO_APIC_DEFAULT_PHYS_BASE
- IO_APIC_IRQ
- IO_APIC_REDIR_DEST_LOGICAL
- IO_APIC_REDIR_DEST_PHYSICAL
- IO_APIC_REDIR_LEVEL_TRIGGER
- IO_APIC_REDIR_MASKED
- IO_APIC_REDIR_REMOTE_IRR
- IO_APIC_REDIR_SEND_PENDING
- IO_APIC_REDIR_VECTOR_MASK
- IO_APIC_SLOT_SIZE
- IO_APIC_VECTOR_LIMIT
- IO_APIC_get_PCI_irq_vector
- IO_APIC_reg_00
- IO_APIC_reg_01
- IO_APIC_reg_02
- IO_APIC_reg_03
- IO_APIC_route_entry
- IO_APP_COMMON_CONFIG
- IO_APP_DEBUG_REG_01
- IO_APP_DEBUG_REG_02
- IO_APP_DEBUG_REG_03
- IO_APP_DEBUG_REG_04
- IO_APP_DEBUG_REG_05
- IO_APP_DEBUG_REG_06
- IO_APP_DEBUG_REG_07
- IO_APP_DEBUG_REG_08
- IO_APP_DEBUG_REG_09
- IO_APP_DEBUG_REG_10
- IO_APP_DEBUG_REG_11
- IO_APP_DEBUG_REG_12
- IO_APP_DEBUG_REG_13
- IO_APP_DEBUG_REG_14
- IO_APP_DEBUG_REG_15
- IO_APP_DEBUG_REG_16
- IO_APP_DEBUG_REG_17
- IO_APP_DEBUG_REG_18
- IO_APP_ERR_ACT_MASK
- IO_APP_ERR_ATTN_MASK
- IO_APP_EXTENDED_ERR_PTR
- IO_APP_FEC
- IO_APP_FIR
- IO_APP_FIRX0_ACT_MASK
- IO_APP_FIRX1_ACT_MASK
- IO_APP_FIR_CLR
- IO_APP_SEC_LEM_DEBUG_OVR
- IO_APP_UNITCFG
- IO_BASE
- IO_BASE_HI_INDEX
- IO_BASE_IO_DECODE
- IO_BASE_IO_DECODE_BIT8
- IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK
- IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK
- IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT
- IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK
- IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK
- IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT
- IO_BASE_LIMIT__IO_BASE_MASK
- IO_BASE_LIMIT__IO_BASE_TYPE_MASK
- IO_BASE_LIMIT__IO_BASE_TYPE__MASK
- IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT
- IO_BASE_LIMIT__IO_BASE__MASK
- IO_BASE_LIMIT__IO_BASE__SHIFT
- IO_BASE_LIMIT__IO_LIMIT_MASK
- IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK
- IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK
- IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT
- IO_BASE_LIMIT__IO_LIMIT__MASK
- IO_BASE_LIMIT__IO_LIMIT__SHIFT
- IO_BASE_LO_INDEX
- IO_BIAS_MASK
- IO_BITMAP_A
- IO_BITMAP_A_HIGH
- IO_BITMAP_B
- IO_BITMAP_BITS
- IO_BITMAP_BYTES
- IO_BITMAP_B_HIGH
- IO_BITMAP_LONGS
- IO_BITMAP_OFFSET
- IO_BLOCKED
- IO_BROKEN_MSG_ADDR_HI
- IO_BROKEN_MSG_ADDR_LO
- IO_BUFFER_LENGTH
- IO_CFG_SDEST_MASK
- IO_CG_BACKBIAS_EN
- IO_CG_VOLTAGE_DROP
- IO_CHANNEL
- IO_CHANNEL_READY_ON
- IO_CHECK_ALIGN
- IO_CMD_CLEAN_QUEUE_CTXT
- IO_CMD_MODIFY_QUEUE_CTXT
- IO_CMD_PAUSE_BAND0_DM_BY_SCAN
- IO_CMD_PAUSE_BAND1_DM_BY_SCAN
- IO_CMD_PAUSE_DM_BY_SCAN
- IO_CMD_RESUME_DM_BY_SCAN
- IO_CMD_TIM
- IO_CNTL_CSR
- IO_CNTL_CSR_RF_PS
- IO_COHERENCE_DEFAULT
- IO_COHERENCE_DISABLED
- IO_COHERENCE_ENABLED
- IO_CONCAT
- IO_COND
- IO_CONFIG_SWAP_DIS
- IO_CONTROL
- IO_CPU_PHYS
- IO_CPU_SIZE
- IO_CPU_VIRT
- IO_CTNL
- IO_CTRL
- IO_CTRL_1_CLEAR_MASK
- IO_CTRL_1_LPC_ERR
- IO_CTRL_1_NMIONERR
- IO_CTRL_1_PW2LPC
- IO_CTRL_OUT_BOTH
- IO_CTRL_OUT_LOCAL
- IO_CTRL_OUT_MUTE
- IO_CTRL_OUT_REMOTE
- IO_CURRENT
- IO_CURRENT_VAL
- IO_DATA_PATH_WIDTH
- IO_DATA_PATH_WIDTH_16
- IO_DATA_PATH_WIDTH_8
- IO_DATA_PATH_WIDTH_AUTO
- IO_DATA_PORT
- IO_DATA_REG_OFFSET
- IO_DCOUNT_REG_OFFSET
- IO_DEBUG
- IO_DEFAULT
- IO_DELAY_TYPE_0X80
- IO_DELAY_TYPE_0XED
- IO_DELAY_TYPE_NONE
- IO_DELAY_TYPE_UDELAY
- IO_DIR
- IO_DISABLE
- IO_DIVIDER
- IO_DMA1_BASE
- IO_DMA2_BASE
- IO_DONE
- IO_DONE_BIT
- IO_DPD2_REQ
- IO_DPD2_STATUS
- IO_DPD_REQ
- IO_DPD_REQ_CODE_IDLE
- IO_DPD_REQ_CODE_MASK
- IO_DPD_REQ_CODE_OFF
- IO_DPD_REQ_CODE_ON
- IO_DPD_STATUS
- IO_DRIVE_REGISTER_SPACING
- IO_DS_INVALID
- IO_DS_IN_ERROR
- IO_DS_IN_RECOVERY
- IO_DS_NON_OPERATIONAL
- IO_EDC_IN_ERROR
- IO_EDC_OUT_ERROR
- IO_EN
- IO_ENABLE
- IO_ERROR
- IO_ERROR_HW_TIMEOUT
- IO_ERROR_INJECT_SELECTOR
- IO_ERROR_INTERNAL_SMP_RESOURCE
- IO_ERROR_INTR
- IO_ERROR_SHIFT
- IO_ERROR_UNKNOWN_GENERIC
- IO_ERR_PTR
- IO_EXTENDED_DIAG_MAP
- IO_EXTENDED_DIAG_READ_MBX
- IO_EXTENDED_DIAG_SELECTOR
- IO_EXTENDED_ERROR_POINTER
- IO_EXTENT
- IO_EXT_CFG_COUNT
- IO_EXT_REGISTER_SPACING
- IO_FAILED
- IO_FIQ_BASE
- IO_FRAME
- IO_GOT_PACKET
- IO_HOLD_TIM
- IO_HSU_COMMON_CONFIG
- IO_HSU_ERR_ACT_MASK
- IO_HSU_ERR_ATTN_MASK
- IO_HSU_ERR_BEHAVIOR
- IO_HSU_EXTENDED_ERR_PTR
- IO_HSU_FEC
- IO_HSU_FIR
- IO_HSU_FIRX0_ACT_MASK
- IO_HSU_FIRX1_ACT_MASK
- IO_HSU_FIR_CLR
- IO_HSU_SEC_LEM_DEBUG_OVR
- IO_HSU_UNITCFG
- IO_IDE1_BASE
- IO_IDE1_MISC
- IO_IDE2_BASE
- IO_IDE2_MISC
- IO_IDE_EXTENT
- IO_ILLEGAL_PARAMETER
- IO_ILLEGAL_VALUE
- IO_IN
- IO_INDEX_PORT
- IO_INR_AB_RXDMA
- IO_INR_AB_RXERR
- IO_INR_AB_TXDMA
- IO_INR_AB_TXERR
- IO_INR_ASC_DMA
- IO_INR_ASC_ERR
- IO_INR_ASC_MERR
- IO_INR_DMA
- IO_INR_FLOPPY_ERR
- IO_INR_ISDN_ERR
- IO_INR_ISDN_RXDMA
- IO_INR_ISDN_TXDMA
- IO_INR_LANCE_MERR
- IO_INR_RES_20
- IO_INR_RES_21
- IO_INR_RES_22
- IO_INR_RES_23
- IO_INR_SCC0A_RXDMA
- IO_INR_SCC0A_RXERR
- IO_INR_SCC0A_TXDMA
- IO_INR_SCC0A_TXERR
- IO_INR_SCC1A_RXDMA
- IO_INR_SCC1A_RXERR
- IO_INR_SCC1A_TXDMA
- IO_INR_SCC1A_TXERR
- IO_INTERRUPT
- IO_INTR_ACK
- IO_INTR_MSK
- IO_INTR_STS
- IO_INVALID_LENGTH
- IO_INVERT_SEL
- IO_IN_IT_ID
- IO_IOPOLL_BATCH
- IO_IO_HIGH
- IO_IO_LOW
- IO_IRAM_PHYS
- IO_IRAM_SIZE
- IO_IRAM_VIRT
- IO_IRQ_ALL
- IO_IRQ_BASE
- IO_IRQ_DMA
- IO_IRQ_DMA_INFO
- IO_IRQ_LINES
- IO_IRQ_MASK
- IO_IRQ_NR
- IO_ISP1161_BASE
- IO_ISP1161_EXTENT
- IO_ISP1161_PHYS
- IO_KILLED
- IO_LAN91C111_BASE
- IO_LAN91C111_EXTENT
- IO_LAN91C111_PHYS
- IO_LENGTH
- IO_LINK_FAILURE
- IO_LITE
- IO_MADE_GOOD
- IO_MAP_SIZE
- IO_MASK
- IO_MATCH
- IO_MATCH_BEGIN
- IO_MAX_MAPS
- IO_MAX_PRIOTY
- IO_MEM_BAR
- IO_MEM_RESOURCE_END
- IO_MEM_RESOURCE_START
- IO_MMAP
- IO_MODE
- IO_MODE_FAST
- IO_MODE_IRQ
- IO_MODE_TIMING_100NS
- IO_MODE_TIMING_120NS
- IO_MODE_TIMING_250NS
- IO_MODE_TIMING_80NS
- IO_MODE_TIMING_MASK
- IO_MODULE_DC_ADATA
- IO_MODULE_EIM
- IO_MODULE_II_CDATA
- IO_MODULE_IO_COMMAND
- IO_MODULE_IO_STATUS
- IO_NAND_CTL
- IO_NAND_DATA
- IO_NAND_ECC_COL
- IO_NAND_ECC_CTL
- IO_NAND_ECC_LSB
- IO_NAND_ECC_MSB
- IO_NAND_IO
- IO_NAND_LAC
- IO_NAND_STS
- IO_NONE
- IO_NOT_VALID
- IO_NO_DEVICE
- IO_NUM_REG_CONFIG_SRC
- IO_NUM_REG_CONT
- IO_NUM_REG_CUER
- IO_NUM_REG_GENCLK
- IO_NUM_REG_IN_ANA_LEVEL
- IO_NUM_REG_MUTE_OUT
- IO_NUM_REG_OUT_ANA_LEVEL
- IO_NUM_REG_STATUS
- IO_NUM_SPEED_RATIO
- IO_NUM_UER_CHIP_REG
- IO_OFFSET
- IO_OK
- IO_OPEN_CNX_ERROR_BAD_DESTINATION
- IO_OPEN_CNX_ERROR_BREAK
- IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED
- IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY
- IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT
- IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS
- IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST
- IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE
- IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO
- IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED
- IO_OPEN_CNX_ERROR_OPEN_PREEMPTED
- IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED
- IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY
- IO_OPEN_CNX_ERROR_UNKNOWN_ERROR
- IO_OPEN_CNX_ERROR_WRONG_DESTINATION
- IO_OPEN_CNX_ERROR_ZONE_VIOLATION
- IO_OUT
- IO_OUT_OT_ID
- IO_OVERFLOW
- IO_PAGENO_BITS
- IO_PAGE_ALIGN
- IO_PAGE_MASK
- IO_PAGE_SHIFT
- IO_PAGE_SIZE
- IO_PATH_ERROR
- IO_PERF_SETS
- IO_PF_SLC_JOBPEND
- IO_PF_SLC_VIRTUAL_REGION
- IO_PF_SLC_VIRTUAL_WINDOW
- IO_PGTABLE_NUM_FMTS
- IO_PGTABLE_QUIRK_ARM_MTK_EXT
- IO_PGTABLE_QUIRK_ARM_NS
- IO_PGTABLE_QUIRK_NON_STRICT
- IO_PGTABLE_QUIRK_NO_PERMS
- IO_PGTABLE_QUIRK_TLBI_ON_MAP
- IO_PHYS
- IO_PIN
- IO_PIN_SHUTDOWN_LIMIT
- IO_PLUG_THRESHOLD
- IO_PORT_BASE
- IO_PORT_IN_RESET
- IO_PORT_RESOURCE_END
- IO_PORT_RESOURCE_START
- IO_PPSB_PHYS
- IO_PPSB_SIZE
- IO_PPSB_VIRT
- IO_PRIORITY_SEL
- IO_PROG_ERROR
- IO_RANGE
- IO_RAW_STATUS
- IO_RD16
- IO_RD16_ASYNC
- IO_RD32
- IO_RD32_ASYNC
- IO_RD8
- IO_RD8_ASYNC
- IO_RD_BURST
- IO_READ
- IO_READY
- IO_READ_OR_WRITE
- IO_REGION_ID
- IO_REG_AB_R_DMA_P
- IO_REG_AB_SLOT
- IO_REG_AB_T_DMA_P
- IO_REG_DATA_0
- IO_REG_DATA_1
- IO_REG_DATA_2
- IO_REG_DATA_3
- IO_REG_FCTR
- IO_REG_FLOPPY_DMA_P
- IO_REG_FLOPPY_SLOT
- IO_REG_ISDN_R_DATA
- IO_REG_ISDN_R_DMA_BP
- IO_REG_ISDN_R_DMA_P
- IO_REG_ISDN_T_DATA
- IO_REG_ISDN_T_DMA_BP
- IO_REG_ISDN_T_DMA_P
- IO_REG_LANCE_DMA_P
- IO_REG_LANCE_SLOT
- IO_REG_RES_31
- IO_REG_SAR
- IO_REG_SCC0A_R_DMA_P
- IO_REG_SCC0A_SLOT
- IO_REG_SCC0A_T_DMA_P
- IO_REG_SCC1A_R_DMA_P
- IO_REG_SCC1A_SLOT
- IO_REG_SCC1A_T_DMA_P
- IO_REG_SCSI_DMA_BP
- IO_REG_SCSI_DMA_P
- IO_REG_SCSI_SCR
- IO_REG_SCSI_SDR0
- IO_REG_SCSI_SDR1
- IO_REG_SCSI_SLOT
- IO_REG_SIMR
- IO_REG_SIR
- IO_REG_SSR
- IO_REJECTED
- IO_REPARSE_APPXSTREAM
- IO_REPARSE_TAG_AF_UNIX
- IO_REPARSE_TAG_AZ_FILE_SYNC
- IO_REPARSE_TAG_DEDUP
- IO_REPARSE_TAG_DFS
- IO_REPARSE_TAG_DFSR
- IO_REPARSE_TAG_DRIVER_EXTENDER
- IO_REPARSE_TAG_FILTER_MANAGER
- IO_REPARSE_TAG_HSM
- IO_REPARSE_TAG_HSM2
- IO_REPARSE_TAG_IS_ALIAS
- IO_REPARSE_TAG_IS_HIGH_LATENCY
- IO_REPARSE_TAG_IS_MICROSOFT
- IO_REPARSE_TAG_LX_BLK
- IO_REPARSE_TAG_LX_CHR
- IO_REPARSE_TAG_LX_FIFO
- IO_REPARSE_TAG_LX_SYMLINK
- IO_REPARSE_TAG_MOUNT_POINT
- IO_REPARSE_TAG_NFS
- IO_REPARSE_TAG_NSS
- IO_REPARSE_TAG_NSS_RECOVER
- IO_REPARSE_TAG_RESERVED_ONE
- IO_REPARSE_TAG_RESERVED_RANGE
- IO_REPARSE_TAG_RESERVED_ZERO
- IO_REPARSE_TAG_SIS
- IO_REPARSE_TAG_SYMBOLIC_LINK
- IO_REPARSE_TAG_SYMLINK
- IO_REPARSE_TAG_VALID_VALUES
- IO_REQUEST_INFO
- IO_RESET
- IO_RETRY
- IO_RSRC_PRINTK_SIZE
- IO_RUNNING
- IO_RW_DIRECT
- IO_SATA_BROKEN_MSG_ADDR_HI
- IO_SATA_BROKEN_MSG_ADDR_LO
- IO_SCH_ATTACH
- IO_SCH_DISC
- IO_SCH_ISC
- IO_SCH_NOP
- IO_SCH_ORPH_ATTACH
- IO_SCH_ORPH_UNREG
- IO_SCH_REPROBE
- IO_SCH_UNREG
- IO_SCH_UNREG_ATTACH
- IO_SCH_VERIFY
- IO_SEGMENT_SHIFT
- IO_SEND_OP_COND
- IO_SERIAL1_BASE
- IO_SERIAL2_BASE
- IO_SERIAL_EXTENT
- IO_SETUP_TIM
- IO_SIZE
- IO_SLC2_FLS_MASTER_TRAP
- IO_SLC2_QUEUE_MANAGER_TRAP
- IO_SLC2_SQB_TRAP
- IO_SLC_APPJOB_TIMEOUT
- IO_SLC_CFGREG_GFIR
- IO_SLC_CFGREG_SOFTRESET
- IO_SLC_FREE_RUNNING_TIMER
- IO_SLC_JOBPEND
- IO_SLC_MISC_DEBUG
- IO_SLC_MISC_DEBUG_CLR
- IO_SLC_MISC_DEBUG_SET
- IO_SLC_QUEUE_CONFIG
- IO_SLC_QUEUE_ERRCNTS
- IO_SLC_QUEUE_INITSQN
- IO_SLC_QUEUE_LRW
- IO_SLC_QUEUE_OFFSET
- IO_SLC_QUEUE_SEGMENT
- IO_SLC_QUEUE_STATUS
- IO_SLC_QUEUE_WRAP
- IO_SLC_QUEUE_WTIME
- IO_SLC_VF_APPJOB_TIMEOUT
- IO_SLC_VF_FREE_RUNNING_TIMER
- IO_SLC_VF_QUEUE_CONFIG
- IO_SLC_VF_QUEUE_ERRCNTS
- IO_SLC_VF_QUEUE_INITSQN
- IO_SLC_VF_QUEUE_LRW
- IO_SLC_VF_QUEUE_OFFSET
- IO_SLC_VF_QUEUE_SEGMENT
- IO_SLC_VF_QUEUE_STATUS
- IO_SLC_VF_QUEUE_WRAP
- IO_SLC_VF_QUEUE_WTIME
- IO_SLOT_CHANGE
- IO_SLU_BITSTREAM
- IO_SLU_COMMON_CONFIG
- IO_SLU_ERR_ACT_MASK
- IO_SLU_ERR_ATTN_MASK
- IO_SLU_EXTENDED_ERR_PTR
- IO_SLU_FEC
- IO_SLU_FIR
- IO_SLU_FIRX0_ACT_MASK
- IO_SLU_FIRX1_ACT_MASK
- IO_SLU_FIR_CLR
- IO_SLU_FLASH_CMDINTF
- IO_SLU_FLASH_DIRECTACCESS
- IO_SLU_FLASH_DIRECTACCESS2
- IO_SLU_FLASH_FEC
- IO_SLU_FLASH_FIR
- IO_SLU_LEDCONTROL
- IO_SLU_RIU_TRAP
- IO_SLU_SEC_LEM_DEBUG_OVR
- IO_SLU_SLC_DISP_TRAP
- IO_SLU_SLC_FEC
- IO_SLU_SLC_FIR
- IO_SLU_SLC_PARSE_TRAP
- IO_SLU_TEMPERATURE_CONFIG
- IO_SLU_TEMPERATURE_SENSOR
- IO_SLU_UNITCFG
- IO_SLU_UNITCFG_TYPE_MASK
- IO_SLU_VOLTAGE_CONTROL
- IO_SLU_VOLTAGE_DOWN5
- IO_SLU_VOLTAGE_NOMINAL
- IO_SLU_VOLTAGE_UP5
- IO_SMUIO_PINSTRAP__AUD_MASK
- IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK
- IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT
- IO_SMUIO_PINSTRAP__AUD__SHIFT
- IO_SMUIO_PINSTRAP__BOARD_CONFIG_MASK
- IO_SMUIO_PINSTRAP__BOARD_CONFIG__SHIFT
- IO_SMUIO_PINSTRAP__SMBUS_ADDR_MASK
- IO_SMUIO_PINSTRAP__SMBUS_ADDR__SHIFT
- IO_SPACE
- IO_SPACE_BASE
- IO_SPACE_BITS
- IO_SPACE_LIMIT
- IO_SPACE_NR
- IO_SPACE_PORT
- IO_SPACE_SIZE
- IO_SPACE_SPARSE_ENCODING
- IO_SRAM_ENABLE
- IO_SSP_EXT_IU_ZERO_LEN_ERROR
- IO_SSR_AB_RX_DMA_EN
- IO_SSR_AB_TX_DMA_EN
- IO_SSR_FLOPPY_DMA_DIR
- IO_SSR_FLOPPY_DMA_EN
- IO_SSR_ISDN_RX_DMA_EN
- IO_SSR_ISDN_TX_DMA_EN
- IO_SSR_LANCE_DMA_EN
- IO_SSR_RES_19
- IO_SSR_RES_20
- IO_SSR_RES_21
- IO_SSR_RES_22
- IO_SSR_RES_23
- IO_SSR_RES_24
- IO_SSR_RES_25
- IO_SSR_RES_26
- IO_SSR_RES_27
- IO_SSR_SCC0A_RX_DMA_EN
- IO_SSR_SCC0A_TX_DMA_EN
- IO_SSR_SCC1A_RX_DMA_EN
- IO_SSR_SCC1A_TX_DMA_EN
- IO_SSR_SCSI_DMA_DIR
- IO_SSR_SCSI_DMA_EN
- IO_START
- IO_STATUS
- IO_STATUS_ERROR
- IO_STATUS_IN_LOCAL
- IO_STATUS_IN_REMOTE
- IO_STATUS_TIMEOUT
- IO_STICKY_SEL
- IO_STOPPED
- IO_SUCCESS
- IO_SUPERIO_BASE
- IO_SUPERIO_EXTENT
- IO_SUPERIO_PHYS
- IO_SYNC_BARRIER_CTL_OFFSET
- IO_THRESHOLD
- IO_TIMER1
- IO_TIMER2
- IO_TLB_DEFAULT_SIZE
- IO_TLB_MIN_SLABS
- IO_TLB_SEGSIZE
- IO_TLB_SHIFT
- IO_TM_TAG_NOT_FOUND
- IO_TO_VIRT
- IO_TO_VIRT_BETWEEN
- IO_TO_VIRT_XLATE
- IO_TRAPPED_MAGIC
- IO_TREE_FS_INFO_FREED_EXTENTS0
- IO_TREE_FS_INFO_FREED_EXTENTS1
- IO_TREE_INODE_IO
- IO_TREE_INODE_IO_FAILURE
- IO_TREE_RELOC_BLOCKS
- IO_TREE_ROOT_DIRTY_LOG_PAGES
- IO_TREE_SELFTEST
- IO_TREE_TRANS_DIRTY_PAGES
- IO_TSB_ENTRIES
- IO_TSB_SIZE
- IO_UNDERFLOW
- IO_UNIT_IO_END
- IO_UNIT_IO_START
- IO_UNIT_RUNNING
- IO_UNIT_STRIPE_END
- IO_UNKNOWN
- IO_VIEW
- IO_VIRT
- IO_WAKEUP_ENABLE
- IO_WATCHDOG_DELAY
- IO_WATCHDOG_OFF
- IO_WINDOW_TYPE
- IO_WIN_CNT
- IO_WIN_CNT_MASK
- IO_WIN_DATA_16BIT
- IO_WIN_DATA_AUTOSZ
- IO_WIN_EA
- IO_WIN_EN
- IO_WIN_OAH
- IO_WIN_OAL
- IO_WIN_SA
- IO_WR16
- IO_WR16_ASYNC
- IO_WR32
- IO_WR32_ASYNC
- IO_WR8
- IO_WR8_ASYNC
- IO_WR_BURST
- IO_XFER
- IO_XFER_CMD_FRAME_ISSUED
- IO_XFER_DMA_ACTIVATE_TIMEOUT
- IO_XFER_ERROR_ABORTED_DUE_TO_SRST
- IO_XFER_ERROR_ABORTED_NCQ_MODE
- IO_XFER_ERROR_ACK_NAK_TIMEOUT
- IO_XFER_ERROR_BREAK
- IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT
- IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK
- IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK
- IO_XFER_ERROR_CREDIT_TIMEOUT
- IO_XFER_ERROR_DMA
- IO_XFER_ERROR_INTERNAL_CRC_ERROR
- IO_XFER_ERROR_INVALID_SSP_RSP_FRAME
- IO_XFER_ERROR_NAK_RECEIVED
- IO_XFER_ERROR_OFFSET_MISMATCH
- IO_XFER_ERROR_PEER_ABORTED
- IO_XFER_ERROR_PHY_NOT_READY
- IO_XFER_ERROR_REJECTED_NCQ_MODE
- IO_XFER_ERROR_RX_FRAME
- IO_XFER_ERROR_SATA
- IO_XFER_ERROR_SATA_LINK_TIMEOUT
- IO_XFER_ERROR_UNEXPECTED_PHASE
- IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED
- IO_XFER_ERROR_XFER_RDY_OVERRUN
- IO_XFER_ERROR_XFER_ZERO_DATA_LEN
- IO_XFER_ERR_EOB_DATA_OVERRUN
- IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR
- IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED
- IO_XFER_OPEN_RETRY_TIMEOUT
- IO_XFER_PIO_SETUP_ERROR
- IO_XFER_SMP_RESP_CONNECTION_ERROR
- IO_XFR_ERROR_CIPHER_MODE_INVALID
- IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS0x2046
- IO_XFR_ERROR_DEK_IV_MISMATCH
- IO_XFR_ERROR_DEK_KEY_CACHE_MISS
- IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH
- IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR
- IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH
- IO_XFR_ERROR_DIF_CRC_MISMATCH
- IO_XFR_ERROR_DIF_MISMATCH
- IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH
- IO_XFR_ERROR_INTERNAL_RAM
- IP
- IP0_11_8
- IP0_15_12
- IP0_19_16
- IP0_23_20
- IP0_27_24
- IP0_31_28
- IP0_3_0
- IP0_7_4
- IP1001_APS_ON
- IP1001_RXPHASE_SEL
- IP1001_SPEC_CTRL_STATUS_2
- IP1001_TXPHASE_SEL
- IP101A_G_APS_ON
- IP101A_G_IRQ_ALL_MASK
- IP101A_G_IRQ_CONF_STATUS
- IP101A_G_IRQ_DUPLEX_CHANGE
- IP101A_G_IRQ_LINK_CHANGE
- IP101A_G_IRQ_PIN_USED
- IP101A_G_IRQ_SPEED_CHANGE
- IP101GR_SEL_INTR32_INTR
- IP101GR_SEL_INTR32_KEEP
- IP101GR_SEL_INTR32_RXER
- IP101G_DIGITAL_IO_SPEC_CTRL
- IP101G_DIGITAL_IO_SPEC_CTRL_SEL_INTR32
- IP10XX_SPEC_CTRL_STATUS
- IP10_11_8
- IP10_15_12
- IP10_19_16
- IP10_23_20
- IP10_27_24
- IP10_31_28
- IP10_3_0
- IP10_7_4
- IP11_11_8
- IP11_15_12
- IP11_19_16
- IP11_23_20
- IP11_27_24
- IP11_31_28
- IP11_3_0
- IP11_7_4
- IP12_11_8
- IP12_15_12
- IP12_19_16
- IP12_23_20
- IP12_27_24
- IP12_31_28
- IP12_3_0
- IP12_7_4
- IP13_11_8
- IP13_15_12
- IP13_19_16
- IP13_23_20
- IP13_27_24
- IP13_31_28
- IP13_3_0
- IP13_7_4
- IP14_11_8
- IP14_15_12
- IP14_19_16
- IP14_23_20
- IP14_27_24
- IP14_31_28
- IP14_3_0
- IP14_7_4
- IP1588_EN
- IP1588_EN_MASK
- IP1588_EN_SHIFT
- IP15_11_8
- IP15_15_12
- IP15_19_16
- IP15_23_20
- IP15_27_24
- IP15_31_28
- IP15_3_0
- IP15_7_4
- IP16_11_8
- IP16_15_12
- IP16_19_16
- IP16_23_20
- IP16_27_24
- IP16_31_28
- IP16_3_0
- IP16_7_4
- IP17_11_8
- IP17_15_12
- IP17_19_16
- IP17_23_20
- IP17_27_24
- IP17_31_28
- IP17_3_0
- IP17_7_4
- IP18_3_0
- IP18_7_4
- IP1_11_8
- IP1_15_12
- IP1_19_16
- IP1_23_20
- IP1_27_24
- IP1_31_28
- IP1_3_0
- IP1_7_4
- IP22ZILOG_FLAG_IS_CHANNEL_A
- IP22ZILOG_FLAG_IS_CONS
- IP22ZILOG_FLAG_IS_KGDB
- IP22ZILOG_FLAG_MODEM_STATUS
- IP22ZILOG_FLAG_REGS_HELD
- IP22ZILOG_FLAG_RESET_DONE
- IP22ZILOG_FLAG_TX_ACTIVE
- IP22ZILOG_FLAG_TX_STOPPED
- IP22ZILOG_GET_CURR_REG
- IP22ZILOG_SET_CURR_REG
- IP22_EISA_MAX_SLOTS
- IP27PROM_BASE
- IP27PROM_BASE_MAPPED
- IP27PROM_CONSOLE
- IP27PROM_CONSOLE_SIZE
- IP27PROM_CORP
- IP27PROM_CORP_MAX
- IP27PROM_CORP_SIZE
- IP27PROM_CORP_STK
- IP27PROM_CORP_STKSIZE
- IP27PROM_DECOMP_BUF
- IP27PROM_DECOMP_SIZE
- IP27PROM_ELSC_BASE_A
- IP27PROM_ELSC_BASE_B
- IP27PROM_ELSC_SHFT
- IP27PROM_ELSC_SIZE
- IP27PROM_ENTRY
- IP27PROM_ERRDMP
- IP27PROM_ERRDMP_SIZE
- IP27PROM_FLASHLEDS
- IP27PROM_FLASH_DATA
- IP27PROM_FLASH_HDR
- IP27PROM_INIT_END
- IP27PROM_INIT_START
- IP27PROM_INT_LAUNCH
- IP27PROM_INT_NETUART
- IP27PROM_IOC3UARTPOD
- IP27PROM_LAUNCHSLAVE
- IP27PROM_NETUART
- IP27PROM_NETUART_SIZE
- IP27PROM_PCFG
- IP27PROM_PCFG_SIZE
- IP27PROM_PODMODE
- IP27PROM_POLLSLAVE
- IP27PROM_REPOD
- IP27PROM_RESTART
- IP27PROM_SIZE_MAX
- IP27PROM_SLAVELOOP
- IP27PROM_STACK_A
- IP27PROM_STACK_B
- IP27PROM_STACK_SHFT
- IP27PROM_STACK_SIZE
- IP27PROM_UNUSED1
- IP27PROM_UNUSED1_SIZE
- IP27PROM_WAITSLAVE
- IP27_CPU0_INDEX
- IP27_CPU1_INDEX
- IP27_FREEMEM_COUNT
- IP27_FREEMEM_OFFSET
- IP27_FREEMEM_SIZE
- IP27_FREEMEM_STRIDE
- IP27_HUB_INDEX
- IP27_HUB_IRQ_BASE
- IP27_HUB_IRQ_COUNT
- IP27_HUB_PEND0_IRQ
- IP27_HUB_PEND1_IRQ
- IP27_INTR_0
- IP27_INTR_1
- IP27_INTR_2
- IP27_INTR_3
- IP27_INTR_4
- IP27_INTR_5
- IP27_INTR_6
- IP27_INTR_7
- IP27_KLCONFIG_COUNT
- IP27_KLCONFIG_OFFSET
- IP27_KLCONFIG_SIZE
- IP27_KLCONFIG_STRIDE
- IP27_LAUNCH_COUNT
- IP27_LAUNCH_OFFSET
- IP27_LAUNCH_SIZE
- IP27_LAUNCH_STRIDE
- IP27_MEM_INDEX
- IP27_NMI_COUNT
- IP27_NMI_EFRAME_OFFSET
- IP27_NMI_EFRAME_SIZE
- IP27_NMI_KREGS_CPU_SIZE
- IP27_NMI_KREGS_OFFSET
- IP27_NMI_OFFSET
- IP27_NMI_SIZE
- IP27_NMI_STRIDE
- IP27_PI_ERROR_COUNT
- IP27_PI_ERROR_OFFSET
- IP27_PI_ERROR_SIZE
- IP27_PI_ERROR_STRIDE
- IP27_RT_TIMER_IRQ
- IP27_SYMMON_STK_COUNT
- IP27_SYMMON_STK_OFFSET
- IP27_SYMMON_STK_SIZE
- IP27_SYMMON_STK_STRIDE
- IP2_11_8
- IP2_15_12
- IP2_19_16
- IP2_23_20
- IP2_27_24
- IP2_31_28
- IP2_3_0
- IP2_7_4
- IP32_IRQ_MAX
- IP3_11_8
- IP3_15_12
- IP3_19_16
- IP3_23_20
- IP3_27_24
- IP3_31_28
- IP3_3_0
- IP3_7_4
- IP4FOURTUPEN_F
- IP4FOURTUPEN_S
- IP4FOURTUPEN_V
- IP4INSEGS
- IP4OUTRSTS
- IP4OUTSEGS
- IP4RETRANSSEGS
- IP4TWOTUPEN_F
- IP4TWOTUPEN_S
- IP4TWOTUPEN_V
- IP4_11_8
- IP4_15_12
- IP4_19_16
- IP4_23_20
- IP4_27_24
- IP4_31_28
- IP4_3_0
- IP4_7_4
- IP4_ADDR_FULL_MASK
- IP4_DST
- IP4_HLEN
- IP4_MF
- IP4_REPLY_MARK
- IP4_SRC
- IP5_11_8
- IP5_15_12
- IP5_19_16
- IP5_23_20
- IP5_27_24
- IP5_31_28
- IP5_3_0
- IP5_7_4
- IP6CB
- IP6CBMTU
- IP6FOURTUPEN_F
- IP6FOURTUPEN_S
- IP6FOURTUPEN_V
- IP6INSEGS
- IP6MRA_CREPORT_DST_ADDR
- IP6MRA_CREPORT_MAX
- IP6MRA_CREPORT_MIF_ID
- IP6MRA_CREPORT_MSGTYPE
- IP6MRA_CREPORT_PKT
- IP6MRA_CREPORT_SRC_ADDR
- IP6MRA_CREPORT_UNSPEC
- IP6OUTRSTS
- IP6OUTSEGS
- IP6RETRANSSEGS
- IP6SKB_FORWARDED
- IP6SKB_FRAGMENTED
- IP6SKB_HOPBYHOP
- IP6SKB_JUMBOGRAM
- IP6SKB_L3SLAVE
- IP6SKB_REROUTED
- IP6SKB_ROUTERALERT
- IP6SKB_XFRM_TRANSFORMED
- IP6TUNNEL_ERR_TIMEO
- IP6TWOTUPEN_F
- IP6TWOTUPEN_S
- IP6TWOTUPEN_V
- IP6T_AH_INV_LEN
- IP6T_AH_INV_MASK
- IP6T_AH_INV_SPI
- IP6T_AH_LEN
- IP6T_AH_RES
- IP6T_AH_SPI
- IP6T_BASE_CTL
- IP6T_CONTINUE
- IP6T_ENTRY_INIT
- IP6T_ENTRY_ITERATE
- IP6T_ERROR_INIT
- IP6T_ERROR_TARGET
- IP6T_FRAG_FST
- IP6T_FRAG_IDS
- IP6T_FRAG_INV_IDS
- IP6T_FRAG_INV_LEN
- IP6T_FRAG_INV_MASK
- IP6T_FRAG_LEN
- IP6T_FRAG_MF
- IP6T_FRAG_NMF
- IP6T_FRAG_RES
- IP6T_FUNCTION_MAXNAMELEN
- IP6T_F_GOTO
- IP6T_F_MASK
- IP6T_F_PROTO
- IP6T_F_TOS
- IP6T_HL_DEC
- IP6T_HL_EQ
- IP6T_HL_GT
- IP6T_HL_INC
- IP6T_HL_LT
- IP6T_HL_MAXMODE
- IP6T_HL_NE
- IP6T_HL_SET
- IP6T_ICMP6_ADDR_UNREACH
- IP6T_ICMP6_ADM_PROHIBITED
- IP6T_ICMP6_ECHOREPLY
- IP6T_ICMP6_NOT_NEIGHBOUR
- IP6T_ICMP6_NO_ROUTE
- IP6T_ICMP6_POLICY_FAIL
- IP6T_ICMP6_PORT_UNREACH
- IP6T_ICMP6_REJECT_ROUTE
- IP6T_ICMP_INV
- IP6T_INV_DSTIP
- IP6T_INV_FRAG
- IP6T_INV_MASK
- IP6T_INV_PROTO
- IP6T_INV_SRCIP
- IP6T_INV_TOS
- IP6T_INV_VIA_IN
- IP6T_INV_VIA_OUT
- IP6T_LOG_IPOPT
- IP6T_LOG_MACDECODE
- IP6T_LOG_MASK
- IP6T_LOG_NFLOG
- IP6T_LOG_TCPOPT
- IP6T_LOG_TCPSEQ
- IP6T_LOG_UID
- IP6T_MATCH_ITERATE
- IP6T_MH_INV_MASK
- IP6T_MH_INV_TYPE
- IP6T_OPTS_INV_LEN
- IP6T_OPTS_INV_MASK
- IP6T_OPTS_LEN
- IP6T_OPTS_NSTRICT
- IP6T_OPTS_OPTS
- IP6T_OPTS_OPTSNR
- IP6T_RETURN
- IP6T_RT_FST
- IP6T_RT_FST_MASK
- IP6T_RT_FST_NSTRICT
- IP6T_RT_HOPS
- IP6T_RT_INV_LEN
- IP6T_RT_INV_MASK
- IP6T_RT_INV_SGS
- IP6T_RT_INV_TYP
- IP6T_RT_LEN
- IP6T_RT_RES
- IP6T_RT_SGS
- IP6T_RT_TYP
- IP6T_SO_GET_ENTRIES
- IP6T_SO_GET_INFO
- IP6T_SO_GET_MAX
- IP6T_SO_GET_REVISION_MATCH
- IP6T_SO_GET_REVISION_TARGET
- IP6T_SO_ORIGINAL_DST
- IP6T_SO_SET_ADD_COUNTERS
- IP6T_SO_SET_MAX
- IP6T_SO_SET_REPLACE
- IP6T_SRH_INV_LAST_EQ
- IP6T_SRH_INV_LAST_GT
- IP6T_SRH_INV_LAST_LT
- IP6T_SRH_INV_LEN_EQ
- IP6T_SRH_INV_LEN_GT
- IP6T_SRH_INV_LEN_LT
- IP6T_SRH_INV_LSID
- IP6T_SRH_INV_MASK
- IP6T_SRH_INV_NEXTHDR
- IP6T_SRH_INV_NSID
- IP6T_SRH_INV_PSID
- IP6T_SRH_INV_SEGS_EQ
- IP6T_SRH_INV_SEGS_GT
- IP6T_SRH_INV_SEGS_LT
- IP6T_SRH_INV_TAG
- IP6T_SRH_LAST_EQ
- IP6T_SRH_LAST_GT
- IP6T_SRH_LAST_LT
- IP6T_SRH_LEN_EQ
- IP6T_SRH_LEN_GT
- IP6T_SRH_LEN_LT
- IP6T_SRH_LSID
- IP6T_SRH_MASK
- IP6T_SRH_NEXTHDR
- IP6T_SRH_NSID
- IP6T_SRH_PSID
- IP6T_SRH_SEGS_EQ
- IP6T_SRH_SEGS_GT
- IP6T_SRH_SEGS_LT
- IP6T_SRH_TAG
- IP6T_STANDARD_INIT
- IP6T_STANDARD_TARGET
- IP6T_TABLE_MAXNAMELEN
- IP6T_TCP_INV_DSTPT
- IP6T_TCP_INV_FLAGS
- IP6T_TCP_INV_MASK
- IP6T_TCP_INV_OPTION
- IP6T_TCP_INV_SRCPT
- IP6T_TCP_RESET
- IP6T_UDP_INV_DSTPT
- IP6T_UDP_INV_MASK
- IP6T_UDP_INV_SRCPT
- IP6_11_8
- IP6_15_12
- IP6_19_16
- IP6_23_20
- IP6_27_24
- IP6_31_28
- IP6_3_0
- IP6_7_4
- IP6_ADD_STATS
- IP6_AUTO_FLOW_LABEL_FORCED
- IP6_AUTO_FLOW_LABEL_MAX
- IP6_AUTO_FLOW_LABEL_OFF
- IP6_AUTO_FLOW_LABEL_OPTIN
- IP6_AUTO_FLOW_LABEL_OPTOUT
- IP6_DEFAULT_AUTO_FLOW_LABELS
- IP6_DEFAULT_MAX_DST_OPTS_CNT
- IP6_DEFAULT_MAX_DST_OPTS_LEN
- IP6_DEFAULT_MAX_HBH_OPTS_CNT
- IP6_DEFAULT_MAX_HBH_OPTS_LEN
- IP6_DEFRAG_CONNTRACK_BRIDGE_IN
- IP6_DEFRAG_CONNTRACK_IN
- IP6_DEFRAG_CONNTRACK_OUT
- IP6_DEFRAG_LOCAL_DELIVER
- IP6_DST_127_96
- IP6_DST_31_0
- IP6_DST_63_32
- IP6_DST_95_64
- IP6_ECN_decapsulate
- IP6_ECN_flow_init
- IP6_ECN_flow_xmit
- IP6_ECN_set_ce
- IP6_ECN_set_ect1
- IP6_FH_F_AUTH
- IP6_FH_F_FRAG
- IP6_FH_F_SKIP_RH
- IP6_GRE_HASH_SIZE
- IP6_GRE_HASH_SIZE_SHIFT
- IP6_HLEN
- IP6_INC_STATS
- IP6_MAX_MTU
- IP6_MF
- IP6_MH_TYPE_BACK
- IP6_MH_TYPE_BERROR
- IP6_MH_TYPE_BRR
- IP6_MH_TYPE_BU
- IP6_MH_TYPE_COT
- IP6_MH_TYPE_COTI
- IP6_MH_TYPE_HOT
- IP6_MH_TYPE_HOTI
- IP6_MH_TYPE_MAX
- IP6_OFFSET
- IP6_REPLY_MARK
- IP6_RT_PRIO_ADDRCONF
- IP6_RT_PRIO_USER
- IP6_SFBLOCK
- IP6_SFLSIZE
- IP6_SIT_HASH_SIZE
- IP6_SRC_127_96
- IP6_SRC_31_0
- IP6_SRC_63_32
- IP6_SRC_95_64
- IP6_TNL_F_ALLOW_LOCAL_REMOTE
- IP6_TNL_F_CAP_PER_PACKET
- IP6_TNL_F_CAP_RCV
- IP6_TNL_F_CAP_XMIT
- IP6_TNL_F_IGN_ENCAP_LIMIT
- IP6_TNL_F_MIP6_DEV
- IP6_TNL_F_RCV_DSCP_COPY
- IP6_TNL_F_USE_ORIG_FLOWLABEL
- IP6_TNL_F_USE_ORIG_FWMARK
- IP6_TNL_F_USE_ORIG_TCLASS
- IP6_TUNNEL_HASH_SIZE
- IP6_TUNNEL_HASH_SIZE_SHIFT
- IP6_UPD_PO_STATS
- IP6_VTI_HASH_SIZE
- IP6_VTI_HASH_SIZE_SHIFT
- IP7_11_8
- IP7_15_12
- IP7_19_16
- IP7_23_20
- IP7_27_24
- IP7_31_28
- IP7_3_0
- IP7_7_4
- IP8_11_8
- IP8_15_12
- IP8_19_16
- IP8_23_20
- IP8_27_24
- IP8_31_28
- IP8_3_0
- IP8_7_4
- IP9_11_8
- IP9_15_12
- IP9_19_16
- IP9_23_20
- IP9_27_24
- IP9_31_28
- IP9_3_0
- IP9_7_4
- IPACK1_DEVICE_ID_SBS_OCTAL_232
- IPACK1_DEVICE_ID_SBS_OCTAL_422
- IPACK1_DEVICE_ID_SBS_OCTAL_485
- IPACK1_VENDOR_ID_RESERVED1
- IPACK1_VENDOR_ID_RESERVED2
- IPACK1_VENDOR_ID_SBS
- IPACK1_VENDOR_ID_UNREGISTRED01
- IPACK1_VENDOR_ID_UNREGISTRED02
- IPACK1_VENDOR_ID_UNREGISTRED03
- IPACK1_VENDOR_ID_UNREGISTRED04
- IPACK1_VENDOR_ID_UNREGISTRED05
- IPACK1_VENDOR_ID_UNREGISTRED06
- IPACK1_VENDOR_ID_UNREGISTRED07
- IPACK1_VENDOR_ID_UNREGISTRED08
- IPACK1_VENDOR_ID_UNREGISTRED09
- IPACK1_VENDOR_ID_UNREGISTRED10
- IPACK1_VENDOR_ID_UNREGISTRED11
- IPACK1_VENDOR_ID_UNREGISTRED12
- IPACK1_VENDOR_ID_UNREGISTRED13
- IPACK1_VENDOR_ID_UNREGISTRED14
- IPACK1_VENDOR_ID_UNREGISTRED15
- IPACKS
- IPACK_ANY_FORMAT
- IPACK_ANY_ID
- IPACK_DEVICE
- IPACK_IDPROM_OFFSET_A
- IPACK_IDPROM_OFFSET_C
- IPACK_IDPROM_OFFSET_CRC
- IPACK_IDPROM_OFFSET_DRIVER_ID_H
- IPACK_IDPROM_OFFSET_DRIVER_ID_L
- IPACK_IDPROM_OFFSET_I
- IPACK_IDPROM_OFFSET_MANUFACTURER_ID
- IPACK_IDPROM_OFFSET_MODEL
- IPACK_IDPROM_OFFSET_NUM_BYTES
- IPACK_IDPROM_OFFSET_P
- IPACK_IDPROM_OFFSET_RESERVED
- IPACK_IDPROM_OFFSET_REVISION
- IPACK_ID_SPACE
- IPACK_ID_VERSION_1
- IPACK_ID_VERSION_2
- IPACK_ID_VERSION_INVALID
- IPACK_INT_SPACE
- IPACK_IO_SPACE
- IPACK_MEM16_SPACE
- IPACK_MEM8_SPACE
- IPACK_SPACE_COUNT
- IPACX_B_ON
- IPACX_B_RFO
- IPACX_B_RME
- IPACX_B_RPF
- IPACX_B_XDU
- IPACX_B_XPR
- IPACX_CMDRB
- IPACX_EXMB
- IPACX_ISTAB
- IPACX_MASKB
- IPACX_MODEB
- IPACX_OFF_ICA
- IPACX_OFF_ICB
- IPACX_RAH1
- IPACX_RAH2
- IPACX_RAL1
- IPACX_RAL2
- IPACX_RBCHB
- IPACX_RBCLB
- IPACX_RFIFOB
- IPACX_RSTAB
- IPACX_STARB
- IPACX_TMB
- IPACX_XFIFOB
- IPACX__ICA
- IPACX__ICB
- IPACX__ON
- IPAC_ACFG
- IPAC_AOE
- IPAC_ARX
- IPAC_ATX
- IPAC_B_ON
- IPAC_B_RFO
- IPAC_B_RFS
- IPAC_B_RME
- IPAC_B_RPF
- IPAC_B_XDU
- IPAC_B_XMR
- IPAC_B_XPR
- IPAC_CCR1
- IPAC_CCR2
- IPAC_CMDRB
- IPAC_CONF
- IPAC_D_TIN2
- IPAC_EXIRB
- IPAC_ID
- IPAC_ISTA
- IPAC_ISTAB
- IPAC_MASK
- IPAC_MASKB
- IPAC_MODEB
- IPAC_PCFG
- IPAC_PITA1
- IPAC_PITA2
- IPAC_POTA1
- IPAC_POTA2
- IPAC_RAH1
- IPAC_RAH2
- IPAC_RAL1
- IPAC_RAL2
- IPAC_RBCHB
- IPAC_RBCLB
- IPAC_RCCR
- IPAC_RHCRB
- IPAC_RLCR
- IPAC_RSTAB
- IPAC_SCFG
- IPAC_STARB
- IPAC_TIMR2
- IPAC_TSAR
- IPAC_TSAX
- IPAC_TYPE_HSCX
- IPAC_TYPE_IPAC
- IPAC_TYPE_IPACX
- IPAC_TYPE_ISAC
- IPAC_TYPE_ISACX
- IPAC_XBCH
- IPAC_XBCL
- IPAC_XCCR
- IPAC__EXA
- IPAC__EXB
- IPAC__EXD
- IPAC__ICA
- IPAC__ICB
- IPAC__ICD
- IPAC__INT0
- IPAC__INT1
- IPAC__ON
- IPADDR
- IPAD_CTRL1
- IPAD_CTRL2
- IPAD_DATA
- IPAD_STS
- IPAQ_LED_MAX_DUTY
- IPA_ADDR_CHANGE_CODE_MACADDR
- IPA_ADDR_CHANGE_CODE_REMOVAL
- IPA_ADDR_CHANGE_CODE_VLANID
- IPA_ARP_PROCESSING
- IPA_CMD_ADDRESS_CHANGE_NOTIF
- IPA_CMD_ASS_ARP_ADD_ENTRY
- IPA_CMD_ASS_ARP_FLUSH_CACHE
- IPA_CMD_ASS_ARP_QUERY_CACHE
- IPA_CMD_ASS_ARP_QUERY_INFO
- IPA_CMD_ASS_ARP_QUERY_STATS
- IPA_CMD_ASS_ARP_REMOVE_ENTRY
- IPA_CMD_ASS_ARP_SET_NO_ENTRIES
- IPA_CMD_ASS_CONFIGURE
- IPA_CMD_ASS_ENABLE
- IPA_CMD_ASS_START
- IPA_CMD_ASS_STOP
- IPA_CMD_CREATE_ADDR
- IPA_CMD_DELCCID
- IPA_CMD_DELGMAC
- IPA_CMD_DELIP
- IPA_CMD_DELIPM
- IPA_CMD_DELVLAN
- IPA_CMD_DELVMAC
- IPA_CMD_DESTROY_ADDR
- IPA_CMD_INITIATOR_HOST
- IPA_CMD_INITIATOR_HOST_REPLY
- IPA_CMD_INITIATOR_OSA
- IPA_CMD_INITIATOR_OSA_REPLY
- IPA_CMD_MODCCID
- IPA_CMD_PRIM_VERSION_NO
- IPA_CMD_QIPASSIST
- IPA_CMD_REGISTER_LOCAL_ADDR
- IPA_CMD_SETADAPTERPARMS
- IPA_CMD_SETASSPARMS
- IPA_CMD_SETBRIDGEPORT_IQD
- IPA_CMD_SETBRIDGEPORT_OSA
- IPA_CMD_SETCCID
- IPA_CMD_SETGMAC
- IPA_CMD_SETIP
- IPA_CMD_SETIPM
- IPA_CMD_SETRTG
- IPA_CMD_SETVLAN
- IPA_CMD_SETVMAC
- IPA_CMD_SET_DIAG_ASS
- IPA_CMD_STARTLAN
- IPA_CMD_STOPLAN
- IPA_CMD_UNKNOWN
- IPA_CMD_UNREGISTER_LOCAL_ADDR
- IPA_CMD_VNICC
- IPA_DATA_SIZEOF
- IPA_FILTERING
- IPA_FLUSH_ARP_SUPPORT
- IPA_FULL_VLAN
- IPA_INBOUND_CHECKSUM
- IPA_INBOUND_CHECKSUM_V6
- IPA_INBOUND_PASSTHRU
- IPA_INBOUND_TSO
- IPA_IPV6
- IPA_IP_REASSEMBLY
- IPA_MULTICASTING
- IPA_OSA_MC_ROUTER
- IPA_OUTBOUND_CHECKSUM
- IPA_OUTBOUND_CHECKSUM_V6
- IPA_OUTBOUND_TSO
- IPA_PASSTHRU
- IPA_PDU_HEADER_SIZE
- IPA_QUERY_ARP_ADDR_INFO
- IPA_QUERY_ARP_ASSIST
- IPA_QUERY_ARP_COUNTERS
- IPA_RC_ARP_ASSIST_NO_ENABLE
- IPA_RC_DATA_MISMATCH
- IPA_RC_DUPLICATE_IP_ADDRESS
- IPA_RC_DUP_IPV6_HOME
- IPA_RC_DUP_IPV6_REMOTE
- IPA_RC_FFFF
- IPA_RC_HARDWARE_AUTH_ERROR
- IPA_RC_ID_NOT_FOUND
- IPA_RC_INVALID_FORMAT
- IPA_RC_INVALID_IP_VERSION
- IPA_RC_INVALID_IP_VERSION2
- IPA_RC_INVALID_LANNUM
- IPA_RC_INVALID_LANTYPE
- IPA_RC_INVALID_MTU_SIZE
- IPA_RC_INVALID_SETRTG_INDICATOR
- IPA_RC_INVALID_SUBCMD
- IPA_RC_IP_ADDR_ALREADY_USED
- IPA_RC_IP_ADDR_TABLE_FULL
- IPA_RC_IP_TABLE_FULL
- IPA_RC_L2_ADDR_TABLE_FULL
- IPA_RC_L2_DUP_LAYER3_MAC
- IPA_RC_L2_DUP_MAC
- IPA_RC_L2_DUP_VLAN_ID
- IPA_RC_L2_GMAC_NOT_FOUND
- IPA_RC_L2_INVALID_VLAN_ID
- IPA_RC_L2_MAC_NOT_AUTH_BY_ADP
- IPA_RC_L2_MAC_NOT_AUTH_BY_HYP
- IPA_RC_L2_MAC_NOT_FOUND
- IPA_RC_L2_UNSUPPORTED_CMD
- IPA_RC_L2_VLAN_ID_NOT_ALLOWED
- IPA_RC_L2_VLAN_ID_NOT_FOUND
- IPA_RC_LAN_FRAME_MISMATCH
- IPA_RC_LAN_OFFLINE
- IPA_RC_LAN_PORT_STATE_ERROR
- IPA_RC_MC_ADDR_ALREADY_DEFINED
- IPA_RC_MC_ADDR_NOT_FOUND
- IPA_RC_NOTSUPP
- IPA_RC_NO_ID_AVAILABLE
- IPA_RC_PRIMARY_ALREADY_DEFINED
- IPA_RC_SBP_IQD_ANO_DEV_PRIMARY
- IPA_RC_SBP_IQD_CURRENT_PRIMARY
- IPA_RC_SBP_IQD_CURRENT_SECOND
- IPA_RC_SBP_IQD_LIMIT_SECOND
- IPA_RC_SBP_IQD_NOT_AUTHD_BY_ZMAN
- IPA_RC_SBP_IQD_NOT_CONFIGURED
- IPA_RC_SBP_IQD_NO_QDIO_QUEUES
- IPA_RC_SBP_IQD_OS_MISMATCH
- IPA_RC_SBP_OSA_ANO_DEV_PRIMARY
- IPA_RC_SBP_OSA_CURRENT_PRIMARY
- IPA_RC_SBP_OSA_CURRENT_SECOND
- IPA_RC_SBP_OSA_LIMIT_SECOND
- IPA_RC_SBP_OSA_NOT_AUTHD_BY_ZMAN
- IPA_RC_SBP_OSA_NOT_CONFIGURED
- IPA_RC_SBP_OSA_NO_QDIO_QUEUES
- IPA_RC_SBP_OSA_OS_MISMATCH
- IPA_RC_SECOND_ALREADY_DEFINED
- IPA_RC_SETIP_ALREADY_RECEIVED
- IPA_RC_SETIP_INVALID_VERSION
- IPA_RC_SETIP_NO_STARTLAN
- IPA_RC_SUCCESS
- IPA_RC_TRACE_ALREADY_ACTIVE
- IPA_RC_UNKNOWN_ERROR
- IPA_RC_UNREGISTERED_ADDR
- IPA_RC_UNSUPPORTED_COMMAND
- IPA_RC_UNSUPPORTED_SUBCMD
- IPA_RC_VEPA_TO_VEB_TRANSITION
- IPA_RC_VNICC_OOSEQ
- IPA_RC_VNICC_VNICBP
- IPA_SBP_BRIDGE_PORT_STATE_CHANGE
- IPA_SBP_QUERY_BRIDGE_PORTS
- IPA_SBP_QUERY_COMMANDS_SUPPORTED
- IPA_SBP_RESET_BRIDGE_PORT_ROLE
- IPA_SBP_SET_PRIMARY_BRIDGE_PORT
- IPA_SBP_SET_SECONDARY_BRIDGE_PORT
- IPA_SETADAPTERPARMS
- IPA_SETADP_ADD_DELETE_FUNCTIONAL_ADDR
- IPA_SETADP_ADD_DELETE_GROUP_ADDRESS
- IPA_SETADP_ALTER_MAC_ADDRESS
- IPA_SETADP_QUERY_CARD_INFO
- IPA_SETADP_QUERY_COMMANDS_SUPPORTED
- IPA_SETADP_QUERY_OAT
- IPA_SETADP_QUERY_SWITCH_ATTRIBUTES
- IPA_SETADP_SEND_OSA_MESSAGE
- IPA_SETADP_SET_ACCESS_CONTROL
- IPA_SETADP_SET_ADDRESSING_MODE
- IPA_SETADP_SET_BROADCAST_MODE
- IPA_SETADP_SET_CONFIG_PARMS
- IPA_SETADP_SET_CONFIG_PARMS_EXTENDED
- IPA_SETADP_SET_DIAG_ASSIST
- IPA_SETADP_SET_PROMISC_MODE
- IPA_SETADP_SET_SNMP_CONTROL
- IPA_SOURCE_MAC
- IPA_VLAN_PRIO
- IPA_VNICC_DISABLE
- IPA_VNICC_ENABLE
- IPA_VNICC_GET_TIMEOUT
- IPA_VNICC_QUERY_CHARS
- IPA_VNICC_QUERY_CMDS
- IPA_VNICC_SET_TIMEOUT
- IPC
- IPCB
- IPCC
- IPCCALL
- IPCC_HWCFGR
- IPCC_IRQ_NUM
- IPCC_IRQ_RX
- IPCC_IRQ_TX
- IPCC_PROC_OFFST
- IPCC_VER
- IPCC_XCR
- IPCC_XMR
- IPCC_XSCR
- IPCC_XTOYSR
- IPCFGR_CHAN_MASK
- IPCLK
- IPCMMIS
- IPCMNI
- IPCMNI_EXTEND
- IPCMNI_EXTEND_MIN_CYCLE
- IPCMNI_EXTEND_SHIFT
- IPCMNI_IDX_MASK
- IPCMNI_SHIFT
- IPCMRIS
- IPCMSG_BATTERY
- IPCMSG_COLD_BOOT
- IPCMSG_COLD_OFF
- IPCMSG_COLD_RESET
- IPCMSG_FW_REVISION
- IPCMSG_FW_UPDATE
- IPCMSG_INDIRECT_READ
- IPCMSG_INDIRECT_WRITE
- IPCMSG_PCNTRL
- IPCMSG_SOFT_RESET
- IPCMSG_VRTC
- IPCMSG_WARM_RESET
- IPCMSG_WATCHDOG_TIMER
- IPCMxDCLEAR
- IPCMxDR
- IPCMxDSET
- IPCMxDSTATUS
- IPCMxMCLEAR
- IPCMxMODE
- IPCMxMSET
- IPCMxMSTATUS
- IPCMxSEND
- IPCMxSOURCE
- IPCOMP_SCRATCH_SIZE
- IPCONFIG_BOOTP
- IPCONFIG_DHCP
- IPCONFIG_DYNAMIC
- IPCONFIG_RARP
- IPCORK_ALLFRAG
- IPCORK_OPT
- IPCS
- IPCTNL_MSG_CT_DELETE
- IPCTNL_MSG_CT_GET
- IPCTNL_MSG_CT_GET_CTRZERO
- IPCTNL_MSG_CT_GET_DYING
- IPCTNL_MSG_CT_GET_STATS
- IPCTNL_MSG_CT_GET_STATS_CPU
- IPCTNL_MSG_CT_GET_UNCONFIRMED
- IPCTNL_MSG_CT_NEW
- IPCTNL_MSG_EXP_DELETE
- IPCTNL_MSG_EXP_GET
- IPCTNL_MSG_EXP_GET_STATS_CPU
- IPCTNL_MSG_EXP_MAX
- IPCTNL_MSG_EXP_NEW
- IPCTNL_MSG_MAX
- IPCTNL_MSG_TIMEOUT_DEFAULT_GET
- IPCTNL_MSG_TIMEOUT_DEFAULT_SET
- IPCTNL_MSG_TIMEOUT_DELETE
- IPCTNL_MSG_TIMEOUT_GET
- IPCTNL_MSG_TIMEOUT_MAX
- IPCTNL_MSG_TIMEOUT_NEW
- IPCT_ASSURED
- IPCT_DESTROY
- IPCT_HELPER
- IPCT_LABEL
- IPCT_MARK
- IPCT_NATSEQADJ
- IPCT_NEW
- IPCT_PROTOINFO
- IPCT_RELATED
- IPCT_REPLY
- IPCT_SECMARK
- IPCT_SEQADJ
- IPCT_SYNPROXY
- IPCV2_MAX_NODES
- IPC_64
- IPC_ACK_FAILURE
- IPC_ACK_SUCCESS
- IPC_BASE_ADDR
- IPC_BOOT_MSECS
- IPC_BUILD_HEADER
- IPC_BUILD_MNG_MSG
- IPC_CALLBACK_PRI
- IPC_CLEAR_HOST_BUSY_READING
- IPC_CLEAR_HOST_ILUP
- IPC_CLEAR_HOST_READY
- IPC_CMD
- IPC_CMD_DS0
- IPC_CMD_IDLE
- IPC_CMD_MSI
- IPC_CMD_PCNTRL_M
- IPC_CMD_PCNTRL_R
- IPC_CMD_PCNTRL_W
- IPC_CMD_RESET
- IPC_CMD_SIZE
- IPC_CMD_STANDBY
- IPC_CMD_SUBCMD
- IPC_CMD_VRTC_SETALARM
- IPC_CMD_VRTC_SETTIME
- IPC_CORE_ID
- IPC_CORE_ID_MASK
- IPC_CORE_ID_SHIFT
- IPC_CREAT
- IPC_D0IX_STREAMING
- IPC_D0IX_STREAMING_MASK
- IPC_D0IX_STREAMING_SHIFT
- IPC_D0IX_WAKE
- IPC_D0IX_WAKE_MASK
- IPC_D0IX_WAKE_SHIFT
- IPC_DATA_BUFFER_SIZE
- IPC_DATA_OFFSET_SZ
- IPC_DATA_OFFSET_SZ_CLEAR
- IPC_DATA_OFFSET_SZ_MASK
- IPC_DATA_OFFSET_SZ_SHIFT
- IPC_DEBUG_DISABLE_LOG
- IPC_DEBUG_ENABLE_LOG
- IPC_DEBUG_MAX_DEBUG_LOG
- IPC_DEBUG_NOTIFY_LOG_DUMP
- IPC_DEBUG_REQUEST_LOG_DUMP
- IPC_DEV
- IPC_DIPC
- IPC_DMA_ID
- IPC_DMA_ID_MASK
- IPC_DMA_ID_SHIFT
- IPC_DOMAIN
- IPC_DOMAIN_MASK
- IPC_DOMAIN_SHIFT
- IPC_DPTR
- IPC_DRBL_BUSY_BIT
- IPC_DRBL_BUSY_OFFS
- IPC_DST_MOD_ID
- IPC_DST_MOD_ID_SHIFT
- IPC_DST_MOD_INSTANCE_ID
- IPC_DST_MOD_INSTANCE_ID_SHIFT
- IPC_DST_QUEUE
- IPC_DST_QUEUE_MASK
- IPC_DST_QUEUE_SHIFT
- IPC_EFFECTS_CREATE
- IPC_EFFECTS_DESTROY
- IPC_EMPTY_LIST_SIZE
- IPC_ERR_CMD_FAILED
- IPC_ERR_CMD_INVALID
- IPC_ERR_CMD_NOT_SERVICED
- IPC_ERR_CMD_NOT_SUPPORTED
- IPC_ERR_EMSECURITY
- IPC_ERR_NONE
- IPC_ERR_UNABLE_TO_SERVICE
- IPC_ERR_UNSIGNEDKERNEL
- IPC_EXCL
- IPC_FINAL_BLOCK
- IPC_FINAL_BLOCK_MASK
- IPC_FINAL_BLOCK_SHIFT
- IPC_FLOOD_TEST_RESULT_LEN
- IPC_FRAGMENT_DATA_PREAMBLE
- IPC_FULL_MSG_SIZE
- IPC_FWSTS_DMA0
- IPC_FWSTS_DMA1
- IPC_FWSTS_DMA2
- IPC_FWSTS_DMA3
- IPC_FWSTS_ILUP
- IPC_FWSTS_ISHTP_UP
- IPC_FW_GEN_MSG
- IPC_FW_READY
- IPC_GET_ISH_FWSTS
- IPC_GET_PARAMS
- IPC_GLB_ALLOCATE_STREAM
- IPC_GLB_CREATE_PPL
- IPC_GLB_DEBUG_LOG_MESSAGE
- IPC_GLB_DELETE_PPL
- IPC_GLB_ENTER_DX_STATE
- IPC_GLB_FREE_STREAM
- IPC_GLB_GET_DEVICE_FORMATS
- IPC_GLB_GET_FW_CAPABILITIES
- IPC_GLB_GET_FW_VERSION
- IPC_GLB_GET_MIXER_STREAM_INFO
- IPC_GLB_GET_PPL_CONTEXT_SIZE
- IPC_GLB_GET_PPL_STATE
- IPC_GLB_LOAD_LIBRARY
- IPC_GLB_LOAD_MULTIPLE_MODS
- IPC_GLB_MAX_IPC_MESSAGE_TYPE
- IPC_GLB_MAX_IPC_MSG_NUMBER
- IPC_GLB_MODULE_OPERATION
- IPC_GLB_NOTIFY
- IPC_GLB_NOTIFY_END_STREAM
- IPC_GLB_NOTIFY_FW_READY
- IPC_GLB_NOTIFY_GLITCH
- IPC_GLB_NOTIFY_LOG_BUFFER_STATUS
- IPC_GLB_NOTIFY_MSG_TYPE
- IPC_GLB_NOTIFY_MSG_TYPE_MASK
- IPC_GLB_NOTIFY_MSG_TYPE_SHIFT
- IPC_GLB_NOTIFY_OVERRUN
- IPC_GLB_NOTIFY_PHRASE_DETECTED
- IPC_GLB_NOTIFY_RESOURCE_EVENT
- IPC_GLB_NOTIFY_RSP_MASK
- IPC_GLB_NOTIFY_RSP_SHIFT
- IPC_GLB_NOTIFY_RSP_TYPE
- IPC_GLB_NOTIFY_TIMESTAMP_CAPTURED
- IPC_GLB_NOTIFY_TYPE
- IPC_GLB_NOTIFY_TYPE_MASK
- IPC_GLB_NOTIFY_TYPE_SHIFT
- IPC_GLB_NOTIFY_UNDERRUN
- IPC_GLB_PERFORMANCE_MONITOR
- IPC_GLB_REPLY_BUSY
- IPC_GLB_REPLY_ERROR_INVALID_PARAM
- IPC_GLB_REPLY_FAILURE
- IPC_GLB_REPLY_GATEWAY_NOT_EXIST
- IPC_GLB_REPLY_GATEWAY_NOT_INITIALIZED
- IPC_GLB_REPLY_INVALID_CONFIG_DATA_LEN
- IPC_GLB_REPLY_INVALID_CONFIG_PARAM_ID
- IPC_GLB_REPLY_INVALID_REQUEST
- IPC_GLB_REPLY_INVALID_RESOURCE_ID
- IPC_GLB_REPLY_INVALID_RESOURCE_STATE
- IPC_GLB_REPLY_MASK
- IPC_GLB_REPLY_MCLK_ALREADY_RUNNING
- IPC_GLB_REPLY_MOD_LOAD_CL_FAILED
- IPC_GLB_REPLY_MOD_LOAD_INVALID_HASH
- IPC_GLB_REPLY_MOD_MGMT_ERROR
- IPC_GLB_REPLY_MOD_NOT_INITIALIZED
- IPC_GLB_REPLY_MOD_UNLOAD_INST_EXIST
- IPC_GLB_REPLY_NOT_FOUND
- IPC_GLB_REPLY_OUT_OF_MEMORY
- IPC_GLB_REPLY_OUT_OF_MIPS
- IPC_GLB_REPLY_OUT_OF_RESOURCES
- IPC_GLB_REPLY_PENDING
- IPC_GLB_REPLY_PPL_NOT_EXIST
- IPC_GLB_REPLY_PPL_NOT_INITIALIZED
- IPC_GLB_REPLY_PPL_RESTORE_FAILED
- IPC_GLB_REPLY_PPL_SAVE_FAILED
- IPC_GLB_REPLY_SCLK_ALREADY_RUNNING
- IPC_GLB_REPLY_SHIFT
- IPC_GLB_REPLY_SOURCE_NOT_STARTED
- IPC_GLB_REPLY_STAGE_UNINITIALIZED
- IPC_GLB_REPLY_STATUS
- IPC_GLB_REPLY_STATUS_MASK
- IPC_GLB_REPLY_STATUS_SHIFT
- IPC_GLB_REPLY_SUCCESS
- IPC_GLB_REPLY_TYPE
- IPC_GLB_REPLY_TYPE_MASK
- IPC_GLB_REPLY_TYPE_SHIFT
- IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE
- IPC_GLB_REPLY_UNKNOWN_MSG_TYPE
- IPC_GLB_REQUEST_DUMP
- IPC_GLB_REQUEST_TRANSFER
- IPC_GLB_RESTORE_CONTEXT
- IPC_GLB_RESTORE_PPL
- IPC_GLB_SAVE_PPL
- IPC_GLB_SET_DEVICE_FORMATS
- IPC_GLB_SET_PPL_STATE
- IPC_GLB_SHORT_REPLY
- IPC_GLB_STREAM_MESSAGE
- IPC_GLB_TYPE
- IPC_GLB_TYPE_MASK
- IPC_GLB_TYPE_SHIFT
- IPC_GLB_UNLOAD_MULTIPLE_MODS
- IPC_GLITCH_DECODER_ERROR
- IPC_GLITCH_DOUBLED_WRITE_POS
- IPC_GLITCH_MAX
- IPC_GLITCH_UNDERRUN
- IPC_HEADER_DATA
- IPC_HEADER_DATA_MASK
- IPC_HEADER_DATA_SHIFT
- IPC_HEADER_GET_LENGTH
- IPC_HEADER_GET_MNG_CMD
- IPC_HEADER_GET_PROTOCOL
- IPC_HEADER_LARGE
- IPC_HEADER_LARGE_SHIFT
- IPC_HEADER_LENGTH_MASK
- IPC_HEADER_LENGTH_OFFSET
- IPC_HEADER_MNG_CMD_MASK
- IPC_HEADER_MNG_CMD_OFFSET
- IPC_HEADER_MSG_ID
- IPC_HEADER_MSG_ID_MASK
- IPC_HEADER_PROTOCOL_MASK
- IPC_HEADER_PROTOCOL_OFFSET
- IPC_HEADER_STR_ID
- IPC_HEADER_STR_ID_MASK
- IPC_HEADER_STR_ID_SHIFT
- IPC_HHIER_BRIDGE
- IPC_HHIER_MSK
- IPC_HHIER_SEC
- IPC_HHIMR_BRIDGE
- IPC_HHIMR_SEC
- IPC_HOST2ISH_BUSYCLEAR_MASK_BIT
- IPC_HOST2ISH_BUSYCLEAR_MASK_OFFS_BXT
- IPC_HOSTCOMM_INT_EN_BIT_CHV_AB
- IPC_HOSTCOMM_INT_EN_OFFS_CHV_AB
- IPC_HOSTCOMM_READY_BIT
- IPC_HOSTCOMM_READY_OFFS
- IPC_HOST_BUSY_READING_BIT
- IPC_HOST_BUSY_READING_OFFS
- IPC_HOST_OWNS_MSG_BIT
- IPC_HOST_OWNS_MSG_OFFS
- IPC_I2C_CNTRL_ADDR
- IPC_I2C_READ
- IPC_I2C_WRITE
- IPC_IA_ALG_PARAMS
- IPC_IA_ALLOC_STREAM
- IPC_IA_ALLOC_STREAM_MRFLD
- IPC_IA_BUF_UNDER_RUN_MRFLD
- IPC_IA_CONTROL_ROUTING
- IPC_IA_DBG_LOG_ENABLE
- IPC_IA_DBG_LOOP_BACK
- IPC_IA_DBG_MEM_READ
- IPC_IA_DBG_MEM_WRITE
- IPC_IA_DBG_SET_PROBE_PARAMS
- IPC_IA_DRAIN_STREAM
- IPC_IA_DRAIN_STREAM_MRFLD
- IPC_IA_DROP_STREAM
- IPC_IA_DROP_STREAM_MRFLD
- IPC_IA_FREE_STREAM
- IPC_IA_FREE_STREAM_MRFLD
- IPC_IA_FW_ASYNC_ERR_MRFLD
- IPC_IA_FW_INIT_CMPLT
- IPC_IA_FW_INIT_CMPLT_MRFLD
- IPC_IA_GET_CODEC_PARAMS
- IPC_IA_GET_FW_BUILD_INF
- IPC_IA_GET_FW_CTXT
- IPC_IA_GET_FW_INFO
- IPC_IA_GET_FW_VERSION
- IPC_IA_GET_PARAMS
- IPC_IA_GET_PPP_PARAMS
- IPC_IA_GET_STREAM_PARAMS
- IPC_IA_LIB_DNLD_CMPLT
- IPC_IA_MEM_ALLOC_FAIL
- IPC_IA_PAUSE_STREAM
- IPC_IA_PAUSE_STREAM_MRFLD
- IPC_IA_PREPARE_SHUTDOWN
- IPC_IA_PREP_LIB_DNLD
- IPC_IA_PRINT_STRING
- IPC_IA_PROC_ERR
- IPC_IA_RESUME_STREAM
- IPC_IA_RESUME_STREAM_MRFLD
- IPC_IA_SET_CODEC_PARAMS
- IPC_IA_SET_FW_CTXT
- IPC_IA_SET_GAIN_MRFLD
- IPC_IA_SET_PARAMS
- IPC_IA_SET_PPP_PARAMS
- IPC_IA_SET_RUNTIME_PARAMS
- IPC_IA_SET_STREAM_PARAMS
- IPC_IA_SET_STREAM_PARAMS_MRFLD
- IPC_IA_START_STREAM
- IPC_IA_START_STREAM_MRFLD
- IPC_IA_TUNING_PARAMS
- IPC_IA_VTSV_DETECTED
- IPC_IA_VTSV_UPDATE_MODULES
- IPC_ILUP_BIT
- IPC_ILUP_OFFS
- IPC_INFO
- IPC_INITIAL_BLOCK
- IPC_INITIAL_BLOCK_CLEAR
- IPC_INITIAL_BLOCK_MASK
- IPC_INITIAL_BLOCK_SHIFT
- IPC_INSTANCE_ID
- IPC_INSTANCE_ID_MASK
- IPC_INSTANCE_ID_SHIFT
- IPC_INT_FROM_ISH_TO_HOST_BXT
- IPC_INT_FROM_ISH_TO_HOST_CHV_AB
- IPC_INT_HOST2ISH_BIT
- IPC_INT_ISH2HOST_BIT_BXT
- IPC_INT_ISH2HOST_BIT_CHV_AB
- IPC_INT_ISH2HOST_CLR_BIT
- IPC_INT_ISH2HOST_CLR_MASK_BIT
- IPC_INT_ISH2HOST_CLR_OFFS
- IPC_INVALID
- IPC_IOC
- IPC_ISH_FWSTS_MASK
- IPC_ISH_FWSTS_SHIFT
- IPC_ISH_IN_DMA
- IPC_ISH_ISHTP_READY_BIT
- IPC_ISH_ISHTP_READY_OFFS
- IPC_IS_BUSY
- IPC_IS_ISH_ILUP
- IPC_IS_ISH_ISHTP_READY
- IPC_IXC_STATUS_BITS
- IPC_LARGE_PARAM_ID
- IPC_LARGE_PARAM_ID_MASK
- IPC_LARGE_PARAM_ID_SHIFT
- IPC_LOAD_MODULE_CNT
- IPC_LOAD_MODULE_MASK
- IPC_LOAD_MODULE_SHIFT
- IPC_LOG_ID
- IPC_LOG_ID_MASK
- IPC_LOG_ID_SHIFT
- IPC_LOG_OP_MASK
- IPC_LOG_OP_SHIFT
- IPC_LOG_OP_TYPE
- IPC_LOOP_CNT
- IPC_MAX_MAILBOX_BYTES
- IPC_MAX_SEC
- IPC_MAX_STATUS
- IPC_MAX_STREAMS
- IPC_MODULE_DISABLE
- IPC_MODULE_ENABLE
- IPC_MODULE_GET_INFO
- IPC_MODULE_GET_PARAMETER
- IPC_MODULE_ID
- IPC_MODULE_ID_MASK
- IPC_MODULE_ID_SHIFT
- IPC_MODULE_MAX_MESSAGE
- IPC_MODULE_NOTIFICATION
- IPC_MODULE_OPERATION
- IPC_MODULE_OPERATION_MASK
- IPC_MODULE_OPERATION_SHIFT
- IPC_MODULE_SET_PARAMETER
- IPC_MOD_BIND
- IPC_MOD_CONFIG_GET
- IPC_MOD_CONFIG_SET
- IPC_MOD_ID
- IPC_MOD_ID_MASK
- IPC_MOD_ID_SHIFT
- IPC_MOD_INIT_INSTANCE
- IPC_MOD_INSTANCE_ID
- IPC_MOD_INSTANCE_ID_MASK
- IPC_MOD_INSTANCE_ID_SHIFT
- IPC_MOD_LARGE_CONFIG_GET
- IPC_MOD_LARGE_CONFIG_SET
- IPC_MOD_MSG
- IPC_MOD_SET_D0IX
- IPC_MOD_SET_DX
- IPC_MOD_UNBIND
- IPC_MSG_DIR
- IPC_MSG_DIR_MASK
- IPC_MSG_DIR_SHIFT
- IPC_MSG_IDS
- IPC_MSG_MAX_SIZE
- IPC_MSG_NOWAIT
- IPC_MSG_REPLY
- IPC_MSG_REQUEST
- IPC_MSG_TARGET
- IPC_MSG_TARGET_MASK
- IPC_MSG_TARGET_SHIFT
- IPC_MSG_WAIT
- IPC_NOTIFICATION
- IPC_NOWAIT
- IPC_NS_INDEX
- IPC_OLD
- IPC_OWN
- IPC_PARAM_BLOCK_SIZE
- IPC_PARAM_BLOCK_SIZE_MASK
- IPC_PARAM_BLOCK_SIZE_SHIFT
- IPC_PAYLOAD_SIZE
- IPC_PIMR_INT_EN_BIT_BXT
- IPC_PIMR_INT_EN_OFFS_BXT
- IPC_POSITION_CHANGED
- IPC_PPL_INSTANCE_ID
- IPC_PPL_INSTANCE_ID_MASK
- IPC_PPL_INSTANCE_ID_SHIFT
- IPC_PPL_LP_MODE
- IPC_PPL_LP_MODE_MASK
- IPC_PPL_LP_MODE_SHIFT
- IPC_PPL_MEM_SIZE
- IPC_PPL_MEM_SIZE_MASK
- IPC_PPL_MEM_SIZE_SHIFT
- IPC_PPL_STATE
- IPC_PPL_STATE_MASK
- IPC_PPL_STATE_SHIFT
- IPC_PPL_TYPE
- IPC_PPL_TYPE_MASK
- IPC_PPL_TYPE_SHIFT
- IPC_PREP_D3
- IPC_PRIVATE
- IPC_PROTOCOL_ISHTP
- IPC_PROTOCOL_MNG
- IPC_PUNIT_BIOS_CMD_BASE
- IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH
- IPC_PUNIT_BIOS_READ_MODULE_TEMP
- IPC_PUNIT_BIOS_READ_PCS
- IPC_PUNIT_BIOS_READ_PCU_CONFIG
- IPC_PUNIT_BIOS_READ_PL1_SETTING
- IPC_PUNIT_BIOS_READ_RATIO_OVER
- IPC_PUNIT_BIOS_READ_TELE_EVENT
- IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL
- IPC_PUNIT_BIOS_READ_TELE_INFO
- IPC_PUNIT_BIOS_READ_TELE_TRACE
- IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL
- IPC_PUNIT_BIOS_READ_VF_GL_CTRL
- IPC_PUNIT_BIOS_READ_VOLTAGE_OVER
- IPC_PUNIT_BIOS_RESERVED
- IPC_PUNIT_BIOS_TRIGGER_VDD_RAM
- IPC_PUNIT_BIOS_VR_INTERFACE
- IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH
- IPC_PUNIT_BIOS_WRITE_PCS
- IPC_PUNIT_BIOS_WRITE_PCU_CONFIG
- IPC_PUNIT_BIOS_WRITE_PL1_SETTING
- IPC_PUNIT_BIOS_WRITE_RATIO_OVER
- IPC_PUNIT_BIOS_WRITE_TELE_EVENT
- IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL
- IPC_PUNIT_BIOS_WRITE_TELE_TRACE
- IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL
- IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL
- IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER
- IPC_PUNIT_BIOS_ZERO
- IPC_PUNIT_CMD_TYPE_MASK
- IPC_PUNIT_ERR_CMD_LOCKED
- IPC_PUNIT_ERR_CMD_TIMEOUT
- IPC_PUNIT_ERR_INVALID_CMD
- IPC_PUNIT_ERR_INVALID_PARAMETER
- IPC_PUNIT_ERR_INVALID_VR_ID
- IPC_PUNIT_ERR_SUCCESS
- IPC_PUNIT_ERR_VR_ERR
- IPC_PUNIT_GTD_CMD_BASE
- IPC_PUNIT_GTD_CONFIG
- IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST
- IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL
- IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING
- IPC_PUNIT_GTD_GET_WM_VAL
- IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL
- IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE
- IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ
- IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL
- IPC_PUNIT_GTD_ZERO
- IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS
- IPC_PUNIT_ISPD_CMD_BASE
- IPC_PUNIT_ISPD_CONFIG
- IPC_PUNIT_ISPD_GET_ISP_LTR_VAL
- IPC_PUNIT_ISPD_READ_CDYN_LEVEL
- IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL
- IPC_PUNIT_ISPD_ZERO
- IPC_READ_BUFFER
- IPC_REG_BASE
- IPC_REG_HOST2ISH_DRBL
- IPC_REG_HOST2ISH_MSG
- IPC_REG_HOST_COMM
- IPC_REG_ISH2HOST_DRBL
- IPC_REG_ISH2HOST_MSG
- IPC_REG_ISH_HOST_FWSTS
- IPC_REG_ISH_RMP2
- IPC_REG_ISH_RST
- IPC_REG_MAX
- IPC_REG_PIMR_BXT
- IPC_REG_PIMR_CHV_AB
- IPC_REG_PISR_BXT
- IPC_REG_PISR_CHV_AB
- IPC_RMID
- IPC_RMP2_DMA_ENABLED
- IPC_RWBUF_SIZE
- IPC_RX_MBOX
- IPC_SANITY_TAG
- IPC_SC_DDR_LINK_DOWN
- IPC_SC_DDR_LINK_UP
- IPC_SC_SET_LPECLK_REQ
- IPC_SC_SSP_BIT_BANG
- IPC_SEM_IDS
- IPC_SET
- IPC_SET_HOST_BUSY_READING
- IPC_SET_HOST_ILUP
- IPC_SET_HOST_READY
- IPC_SET_PARAMS
- IPC_SET_WATCHDOG_TIMER
- IPC_SHARED_PAYLOAD_REG
- IPC_SHM_IDS
- IPC_SPTR
- IPC_SRC_QUEUE
- IPC_SRC_QUEUE_MASK
- IPC_SRC_QUEUE_SHIFT
- IPC_SST_BUF_OVER_RUN
- IPC_SST_BUF_UNDER_RUN
- IPC_SST_CHNGE_SSP_PARAMS
- IPC_SST_DRAIN_END
- IPC_SST_ERROR_EVENT
- IPC_SST_FRAGMENT_ELPASED
- IPC_SST_PERIOD_ELAPSED
- IPC_SST_PERIOD_ELAPSED_MRFLD
- IPC_SST_STREAM_PROCESS_FATAL_ERR
- IPC_STAT
- IPC_STATUS
- IPC_STATUS_BUSY
- IPC_STATUS_ERR
- IPC_STATUS_IRQ
- IPC_STATUS_MASK
- IPC_STG_GET_VOLUME
- IPC_STG_GLITCH
- IPC_STG_ID
- IPC_STG_ID_MASK
- IPC_STG_ID_SHIFT
- IPC_STG_MAX_MESSAGE
- IPC_STG_MAX_NOTIFY
- IPC_STG_MUTE_LOOPBACK
- IPC_STG_REPLY_MASK
- IPC_STG_REPLY_SHIFT
- IPC_STG_SET_FX_DISABLE
- IPC_STG_SET_FX_ENABLE
- IPC_STG_SET_FX_GET_INFO
- IPC_STG_SET_FX_GET_PARAM
- IPC_STG_SET_FX_SET_PARAM
- IPC_STG_SET_VOLUME
- IPC_STG_SET_WRITE_POSITION
- IPC_STG_TYPE
- IPC_STG_TYPE_MASK
- IPC_STG_TYPE_SHIFT
- IPC_STR_ID
- IPC_STR_ID_MASK
- IPC_STR_ID_SHIFT
- IPC_STR_MAX_MESSAGE
- IPC_STR_NOTIFICATION
- IPC_STR_PAUSE
- IPC_STR_REPLY_MASK
- IPC_STR_REPLY_SHIFT
- IPC_STR_RESET
- IPC_STR_RESUME
- IPC_STR_STAGE_MESSAGE
- IPC_STR_TYPE
- IPC_STR_TYPE_MASK
- IPC_STR_TYPE_SHIFT
- IPC_TIMEOUT
- IPC_TIMEOUT_MSECS
- IPC_TRIGGER_MODE_IRQ
- IPC_TX_FIFO_SIZE
- IPC_TX_MBOX
- IPC_TYPE
- IPC_TYPE_OFFSET
- IPC_WATCHDOG
- IPC_WRITE_BUFFER
- IPC_WWBUF_SIZE
- IPCheckSumErrors
- IPChecksumEnable
- IPChksumErr
- IPChksumValid
- IPDDP_DECAP
- IPDDP_ENCAP
- IPDEFTTL
- IPDetected
- IPEHR
- IPEHR_I965
- IPEIR
- IPEIR_I965
- IPEND
- IPEXP_DESTROY
- IPEXP_NEW
- IPE_0_GDSC
- IPE_1_GDSC
- IPE_FRAME_CNT_MASK
- IPError
- IPF
- IPFIELD_ALIGN_OFFSET
- IPFRAG_DUP
- IPFRAG_ECN_CE
- IPFRAG_ECN_ECT_0
- IPFRAG_ECN_ECT_1
- IPFRAG_ECN_NOT_ECT
- IPFRAG_OK
- IPFRAG_OVERLAP
- IPFS_EN_FPCI
- IPFS_IP_INT_MASK
- IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0
- IPFS_XUSB_HOST_CONFIGURATION_0
- IPFS_XUSB_HOST_INTR_MASK_0
- IPFail
- IPG
- IPG1
- IPG2
- IPGIFG_BACK_TO_BACK_IFG_MAX
- IPGIFG_BACK_TO_BACK_IFG_SHIFT
- IPGIFG_BACK_TO_BACK_IPG
- IPGIFG_BTB_IPG_MASK
- IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX
- IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
- IPGIFG_MIN_IFG_ENFORCEMENT
- IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT
- IPGIFG_MIN_IFG_MASK
- IPGIFG_NBTB_CS_IPG_MASK
- IPGIFG_NBTB_IPG_MASK
- IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
- IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
- IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
- IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
- IPGIFG_NON_BACK_TO_BACK_IPG_1
- IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT
- IPGIFG_NON_BACK_TO_BACK_IPG_2
- IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT
- IPGR
- IPGR1
- IPGR2
- IPGT
- IPG_12_15_XGMII
- IPG_12_MII_GMII
- IPG_13_MII_GMII
- IPG_14_MII_GMII
- IPG_15_MII_GMII
- IPG_16_19_XGMII
- IPG_16_MII_GMII
- IPG_20_23_XGMII
- IPG_AC_LED_MODE
- IPG_AC_LED_MODE_BIT_1
- IPG_AC_LED_SPEED
- IPG_CONFIG_RX_MASK
- IPG_CONFIG_RX_SHIFT
- IPG_CONVERGE_JIFFIES
- IPG_DATA_DEF
- IPG_DATA_DEF_1000
- IPG_DATA_DEF_10_100
- IPG_DATA_VAL
- IPG_STABLE_TIME
- IPG_STEP
- IPHASE5575_BUS_CONTROL_REG
- IPHASE5575_BUS_CONTROL_REG_BASE
- IPHASE5575_BUS_STATUS_REG
- IPHASE5575_CELL_FIFO_CELLS_AVL
- IPHASE5575_CELL_FIFO_MARK_STATE
- IPHASE5575_CELL_FIFO_QUEUE_SZ
- IPHASE5575_CELL_FIFO_READ_PTR
- IPHASE5575_CELL_FIFO_WRITE_PTR
- IPHASE5575_DMA_CONTROL_REG_BASE
- IPHASE5575_EEPROM_ACCESS
- IPHASE5575_EXT_RESET
- IPHASE5575_FRAG_CONTROL_RAM_BASE
- IPHASE5575_FRAG_CONTROL_REG_BASE
- IPHASE5575_FRONT_END_REG_BASE
- IPHASE5575_INT_RESET
- IPHASE5575_MAC1
- IPHASE5575_MAC2
- IPHASE5575_PCI_ADDR_PAGE
- IPHASE5575_PCI_CONFIG_REG_BASE
- IPHASE5575_REASS_CONTROL_RAM_BASE
- IPHASE5575_REASS_CONTROL_REG_BASE
- IPHASE5575_REV
- IPHASE5575_RX_COUNTER
- IPHASE5575_RX_LIST_ADDR
- IPHASE5575_TX_COUNTER
- IPHASE5575_TX_LIST_ADDR
- IPHASE_H
- IPHDR_DSTPORT_OFFSET
- IPHDR_LEN
- IPHDR_POS
- IPHDR_SRCPORT_OFFSET
- IPHETH_ALT_INTFNUM
- IPHETH_BUF_SIZE
- IPHETH_CARRIER_CHECK_TIMEOUT
- IPHETH_CARRIER_ON
- IPHETH_CMD_CARRIER_CHECK
- IPHETH_CMD_GET_MACADDR
- IPHETH_CTRL_BUF_SIZE
- IPHETH_CTRL_ENDP
- IPHETH_CTRL_TIMEOUT
- IPHETH_INTFNUM
- IPHETH_IP_ALIGN
- IPHETH_TX_TIMEOUT
- IPHETH_USBINTF_CLASS
- IPHETH_USBINTF_PROTO
- IPHETH_USBINTF_SUBCLASS
- IPI
- IPI0_IRQ
- IPI1_IRQ
- IPIC_DISABLE_MCP_OUT
- IPIC_INT_GRP_A
- IPIC_INT_GRP_D
- IPIC_IRQ0_MCP
- IPIC_IRQ_EXT0
- IPIC_IRQ_EXT1
- IPIC_IRQ_EXT7
- IPIC_MCP_IRQ0
- IPIC_MCP_MU
- IPIC_MCP_PCI1
- IPIC_MCP_PCI2
- IPIC_MCP_SBA
- IPIC_MCP_WDT
- IPIC_MIX_GRP_A
- IPIC_MIX_GRP_B
- IPIC_PRIORITY_DEFAULT
- IPIC_SCVCR
- IPIC_SECNR
- IPIC_SEFCR
- IPIC_SEMSR
- IPIC_SEPNR
- IPIC_SERCR
- IPIC_SERFR
- IPIC_SERMR
- IPIC_SERSR
- IPIC_SICFR
- IPIC_SICNR
- IPIC_SIFCR_H
- IPIC_SIFCR_L
- IPIC_SIMSR_H
- IPIC_SIMSR_L
- IPIC_SIPNR_H
- IPIC_SIPNR_L
- IPIC_SIPRR_A
- IPIC_SIPRR_B
- IPIC_SIPRR_C
- IPIC_SIPRR_D
- IPIC_SIVCR
- IPIC_SIVCR_VECTOR_MASK
- IPIC_SMPRR_A
- IPIC_SMPRR_B
- IPIC_SMVCR
- IPIC_SPREADMODE_GRP_A
- IPIC_SPREADMODE_GRP_B
- IPIC_SPREADMODE_GRP_C
- IPIC_SPREADMODE_GRP_D
- IPIC_SPREADMODE_MIX_A
- IPIC_SPREADMODE_MIX_B
- IPINADDRERRORS
- IPINDELIVERS
- IPINDISCARDS
- IPINHDRERRORS
- IPINRECEIVES
- IPINUNKNOWNPROTOS
- IPIPEIF_CFG1
- IPIPEIF_CFG1_INPSRC1_ISIF_DARKFM
- IPIPEIF_CFG1_INPSRC1_MASK
- IPIPEIF_CFG1_INPSRC1_SDRAM_RAW
- IPIPEIF_CFG1_INPSRC1_SDRAM_YUV
- IPIPEIF_CFG1_INPSRC1_VPORT_RAW
- IPIPEIF_CFG1_INPSRC2_ISIF
- IPIPEIF_CFG1_INPSRC2_ISIF_DARKFM
- IPIPEIF_CFG1_INPSRC2_MASK
- IPIPEIF_CFG1_INPSRC2_SDRAM_RAW
- IPIPEIF_CFG1_INPSRC2_SDRAM_YUV
- IPIPEIF_CFG2
- IPIPEIF_CFG2_HDPOL
- IPIPEIF_CFG2_INTSW
- IPIPEIF_CFG2_VDPOL
- IPIPEIF_CFG2_YUV16
- IPIPEIF_CFG2_YUV8
- IPIPEIF_CFG2_YUV8P
- IPIPEIF_CLKDIV
- IPIPEIF_DRV_SUBCLK_MASK
- IPIPEIF_ENABLE
- IPIPEIF_INPUT_CSI2A
- IPIPEIF_INPUT_CSI2B
- IPIPEIF_INPUT_NONE
- IPIPEIF_OUTPUT_MEMORY
- IPIPEIF_OUTPUT_VP
- IPIPEIF_PADS_NUM
- IPIPEIF_PAD_SINK
- IPIPEIF_PAD_SOURCE_ISIF_SF
- IPIPEIF_PAD_SOURCE_VP
- IPIPEIF_PRINT_REGISTER
- IPIPE_BOX_EN
- IPIPE_BOX_MODE
- IPIPE_BOX_SDR_SAD_H
- IPIPE_BOX_SDR_SAD_L
- IPIPE_BOX_SHF
- IPIPE_BOX_TYP
- IPIPE_BSC_COL_HNU
- IPIPE_BSC_COL_HPO
- IPIPE_BSC_COL_HSKIP
- IPIPE_BSC_COL_SHF
- IPIPE_BSC_COL_VCT
- IPIPE_BSC_COL_VNU
- IPIPE_BSC_COL_VPO
- IPIPE_BSC_COL_VSKIP
- IPIPE_BSC_EN
- IPIPE_BSC_MODE
- IPIPE_BSC_ROW_HNU
- IPIPE_BSC_ROW_HPO
- IPIPE_BSC_ROW_HSKIP
- IPIPE_BSC_ROW_SHF
- IPIPE_BSC_ROW_VCT
- IPIPE_BSC_ROW_VNU
- IPIPE_BSC_ROW_VPO
- IPIPE_BSC_ROW_VSKIP
- IPIPE_BSC_TYP
- IPIPE_CAR_EN
- IPIPE_CAR_GN1_GAN
- IPIPE_CAR_GN1_MIN
- IPIPE_CAR_GN1_SHF
- IPIPE_CAR_GN2_GAN
- IPIPE_CAR_GN2_MIN
- IPIPE_CAR_GN2_SHF
- IPIPE_CAR_HPF_SHF
- IPIPE_CAR_HPF_THR
- IPIPE_CAR_HPF_TYP
- IPIPE_CAR_SW
- IPIPE_CAR_TYP
- IPIPE_CFA_2DIR_DIR_SLP
- IPIPE_CFA_2DIR_DIR_TRH
- IPIPE_CFA_2DIR_HPF_SLP
- IPIPE_CFA_2DIR_HPF_THR
- IPIPE_CFA_2DIR_MIX_SLP
- IPIPE_CFA_2DIR_MIX_THR
- IPIPE_CFA_2DIR_NDWT
- IPIPE_CFA_MODE
- IPIPE_CFA_MONO_EDG_THR
- IPIPE_CFA_MONO_HUE_FRA
- IPIPE_CFA_MONO_LPWT
- IPIPE_CFA_MONO_SLP_MIN
- IPIPE_CFA_MONO_SLP_SLP
- IPIPE_CFA_MONO_THR_MIN
- IPIPE_CFA_MONO_THR_SLP
- IPIPE_CGS_EN
- IPIPE_CGS_GN1_H_GAIN
- IPIPE_CGS_GN1_H_MIN
- IPIPE_CGS_GN1_H_SHF
- IPIPE_CGS_GN1_H_THR
- IPIPE_CGS_GN1_L_GAIN
- IPIPE_CGS_GN1_L_MIN
- IPIPE_CGS_GN1_L_SHF
- IPIPE_CGS_GN1_L_THR
- IPIPE_CGS_GN2_L_GAIN
- IPIPE_CGS_GN2_L_MIN
- IPIPE_CGS_GN2_L_SHF
- IPIPE_CGS_GN2_L_THR
- IPIPE_D2F_1ST_EDG_MAX
- IPIPE_D2F_1ST_EDG_MIN
- IPIPE_D2F_1ST_EN
- IPIPE_D2F_1ST_SPR_00
- IPIPE_D2F_1ST_SPR_01
- IPIPE_D2F_1ST_SPR_02
- IPIPE_D2F_1ST_SPR_03
- IPIPE_D2F_1ST_SPR_04
- IPIPE_D2F_1ST_SPR_05
- IPIPE_D2F_1ST_SPR_06
- IPIPE_D2F_1ST_SPR_07
- IPIPE_D2F_1ST_STR_00
- IPIPE_D2F_1ST_STR_01
- IPIPE_D2F_1ST_STR_02
- IPIPE_D2F_1ST_STR_03
- IPIPE_D2F_1ST_STR_04
- IPIPE_D2F_1ST_STR_05
- IPIPE_D2F_1ST_STR_06
- IPIPE_D2F_1ST_STR_07
- IPIPE_D2F_1ST_THR_00
- IPIPE_D2F_1ST_THR_01
- IPIPE_D2F_1ST_THR_02
- IPIPE_D2F_1ST_THR_03
- IPIPE_D2F_1ST_THR_04
- IPIPE_D2F_1ST_THR_05
- IPIPE_D2F_1ST_THR_06
- IPIPE_D2F_1ST_THR_07
- IPIPE_D2F_1ST_TYP
- IPIPE_D2F_2ND_EDG_MAX
- IPIPE_D2F_2ND_EDG_MIN
- IPIPE_D2F_2ND_EN
- IPIPE_D2F_2ND_SPR_00
- IPIPE_D2F_2ND_SPR_01
- IPIPE_D2F_2ND_SPR_02
- IPIPE_D2F_2ND_SPR_03
- IPIPE_D2F_2ND_SPR_04
- IPIPE_D2F_2ND_SPR_05
- IPIPE_D2F_2ND_SPR_06
- IPIPE_D2F_2ND_SPR_07
- IPIPE_D2F_2ND_STR_00
- IPIPE_D2F_2ND_STR_01
- IPIPE_D2F_2ND_STR_02
- IPIPE_D2F_2ND_STR_03
- IPIPE_D2F_2ND_STR_04
- IPIPE_D2F_2ND_STR_05
- IPIPE_D2F_2ND_STR_06
- IPIPE_D2F_2ND_STR_07
- IPIPE_D2F_2ND_THR00
- IPIPE_D2F_2ND_THR01
- IPIPE_D2F_2ND_THR02
- IPIPE_D2F_2ND_THR03
- IPIPE_D2F_2ND_THR04
- IPIPE_D2F_2ND_THR05
- IPIPE_D2F_2ND_THR06
- IPIPE_D2F_2ND_THR07
- IPIPE_D2F_2ND_TYP
- IPIPE_DPC_LUT_ADR
- IPIPE_DPC_LUT_EN
- IPIPE_DPC_LUT_SEL
- IPIPE_DPC_LUT_SIZ
- IPIPE_DPC_OTF_2_C_THR_B
- IPIPE_DPC_OTF_2_C_THR_GB
- IPIPE_DPC_OTF_2_C_THR_GR
- IPIPE_DPC_OTF_2_C_THR_R
- IPIPE_DPC_OTF_2_D_THR_B
- IPIPE_DPC_OTF_2_D_THR_GB
- IPIPE_DPC_OTF_2_D_THR_GR
- IPIPE_DPC_OTF_2_D_THR_R
- IPIPE_DPC_OTF_3_C_MAX
- IPIPE_DPC_OTF_3_C_MIN
- IPIPE_DPC_OTF_3_C_SLP
- IPIPE_DPC_OTF_3_C_THR
- IPIPE_DPC_OTF_3_D_MAX
- IPIPE_DPC_OTF_3_D_MIN
- IPIPE_DPC_OTF_3_D_SPL
- IPIPE_DPC_OTF_3_D_THR
- IPIPE_DPC_OTF_3_SHF
- IPIPE_DPC_OTF_EN
- IPIPE_DPC_OTF_TYP
- IPIPE_GCK_MMR
- IPIPE_GCK_MMR_REG
- IPIPE_GCK_PIX
- IPIPE_GCK_PIX_G0
- IPIPE_GCK_PIX_G1
- IPIPE_GCK_PIX_G2
- IPIPE_GCK_PIX_G3
- IPIPE_GIC_EN
- IPIPE_GIC_GAN
- IPIPE_GIC_NFGAIN
- IPIPE_GIC_SLP
- IPIPE_GIC_THR
- IPIPE_GIC_TYP
- IPIPE_GMM_CFG
- IPIPE_HST_0_HPS
- IPIPE_HST_0_HSZ
- IPIPE_HST_0_VPS
- IPIPE_HST_0_VSZ
- IPIPE_HST_1_HPS
- IPIPE_HST_1_HSZ
- IPIPE_HST_1_VPS
- IPIPE_HST_1_VSZ
- IPIPE_HST_2_HPS
- IPIPE_HST_2_HSZ
- IPIPE_HST_2_VPS
- IPIPE_HST_2_VSZ
- IPIPE_HST_3_HPS
- IPIPE_HST_3_HSZ
- IPIPE_HST_3_VPS
- IPIPE_HST_3_VSZ
- IPIPE_HST_EN
- IPIPE_HST_MODE
- IPIPE_HST_MUL_B
- IPIPE_HST_MUL_GB
- IPIPE_HST_MUL_GR
- IPIPE_HST_MUL_R
- IPIPE_HST_PARA
- IPIPE_HST_SEL
- IPIPE_HST_TBL
- IPIPE_INPUT_IPIPEIF
- IPIPE_INPUT_NONE
- IPIPE_LSC_GAN_B
- IPIPE_LSC_GAN_GB
- IPIPE_LSC_GAN_GR
- IPIPE_LSC_GAN_R
- IPIPE_LSC_HA1
- IPIPE_LSC_HA2
- IPIPE_LSC_HOFT
- IPIPE_LSC_HS
- IPIPE_LSC_MAX
- IPIPE_LSC_OFT_B
- IPIPE_LSC_OFT_GB
- IPIPE_LSC_OFT_GR
- IPIPE_LSC_OFT_R
- IPIPE_LSC_SHF
- IPIPE_LSC_VA1
- IPIPE_LSC_VA2
- IPIPE_LSC_VOFT
- IPIPE_LSC_VS
- IPIPE_OUTPUT_VP
- IPIPE_PADS_NUM
- IPIPE_PAD_SINK
- IPIPE_PAD_SOURCE_VP
- IPIPE_PRINT_REGISTER
- IPIPE_RGB1_MUL_BB
- IPIPE_RGB1_MUL_BG
- IPIPE_RGB1_MUL_BR
- IPIPE_RGB1_MUL_GB
- IPIPE_RGB1_MUL_GG
- IPIPE_RGB1_MUL_GR
- IPIPE_RGB1_MUL_RB
- IPIPE_RGB1_MUL_RG
- IPIPE_RGB1_MUL_RR
- IPIPE_RGB1_OFT_OB
- IPIPE_RGB1_OFT_OG
- IPIPE_RGB1_OFT_OR
- IPIPE_RGB2_MUL_BB
- IPIPE_RGB2_MUL_BG
- IPIPE_RGB2_MUL_BR
- IPIPE_RGB2_MUL_GB
- IPIPE_RGB2_MUL_GG
- IPIPE_RGB2_MUL_GR
- IPIPE_RGB2_MUL_RB
- IPIPE_RGB2_MUL_RG
- IPIPE_RGB2_MUL_RR
- IPIPE_RGB2_OFT_OB
- IPIPE_RGB2_OFT_OG
- IPIPE_RGB2_OFT_OR
- IPIPE_SEL_SBU
- IPIPE_SRC_COL
- IPIPE_SRC_COL_EE_B
- IPIPE_SRC_COL_EE_GB
- IPIPE_SRC_COL_EE_GR
- IPIPE_SRC_COL_EE_R
- IPIPE_SRC_COL_EO_B
- IPIPE_SRC_COL_EO_GB
- IPIPE_SRC_COL_EO_GR
- IPIPE_SRC_COL_EO_R
- IPIPE_SRC_COL_OE_B
- IPIPE_SRC_COL_OE_GB
- IPIPE_SRC_COL_OE_GR
- IPIPE_SRC_COL_OE_R
- IPIPE_SRC_COL_OO_B
- IPIPE_SRC_COL_OO_GB
- IPIPE_SRC_COL_OO_GR
- IPIPE_SRC_COL_OO_R
- IPIPE_SRC_EN
- IPIPE_SRC_EN_EN
- IPIPE_SRC_FMT
- IPIPE_SRC_FMT_RAW2RAW
- IPIPE_SRC_FMT_RAW2STATS
- IPIPE_SRC_FMT_RAW2YUV
- IPIPE_SRC_FMT_YUV2YUV
- IPIPE_SRC_HPS
- IPIPE_SRC_HPS_MASK
- IPIPE_SRC_HSZ
- IPIPE_SRC_HSZ_MASK
- IPIPE_SRC_MODE
- IPIPE_SRC_MODE_OST
- IPIPE_SRC_MODE_WRT
- IPIPE_SRC_STA
- IPIPE_SRC_VPS
- IPIPE_SRC_VPS_MASK
- IPIPE_SRC_VSZ
- IPIPE_SRC_VSZ_MASK
- IPIPE_WB2_OFT_B
- IPIPE_WB2_OFT_GB
- IPIPE_WB2_OFT_GR
- IPIPE_WB2_OFT_R
- IPIPE_WB2_WGN_B
- IPIPE_WB2_WGN_GB
- IPIPE_WB2_WGN_GR
- IPIPE_WB2_WGN_R
- IPIPE_YEE_EN
- IPIPE_YEE_E_GAN
- IPIPE_YEE_E_THR_1
- IPIPE_YEE_E_THR_2
- IPIPE_YEE_G_GAN
- IPIPE_YEE_G_OFT
- IPIPE_YEE_MUL_00
- IPIPE_YEE_MUL_01
- IPIPE_YEE_MUL_02
- IPIPE_YEE_MUL_10
- IPIPE_YEE_MUL_11
- IPIPE_YEE_MUL_12
- IPIPE_YEE_MUL_20
- IPIPE_YEE_MUL_21
- IPIPE_YEE_MUL_22
- IPIPE_YEE_SHF
- IPIPE_YEE_THR
- IPIPE_YEE_TYP
- IPIPE_YUV_ADJ
- IPIPE_YUV_MUL_BCB
- IPIPE_YUV_MUL_BCR
- IPIPE_YUV_MUL_BY
- IPIPE_YUV_MUL_GCB
- IPIPE_YUV_MUL_GCR
- IPIPE_YUV_MUL_GY
- IPIPE_YUV_MUL_RCB
- IPIPE_YUV_MUL_RCR
- IPIPE_YUV_MUL_RY
- IPIPE_YUV_OFT_CB
- IPIPE_YUV_OFT_CR
- IPIPE_YUV_OFT_Y
- IPIPE_YUV_PHS
- IPIPE_YUV_PHS_LPF
- IPIPE_YUV_PHS_POS
- IPIP_FEATURES
- IPI_CALL_FUNC
- IPI_CALL_FUNC_SINGLE
- IPI_COMPLETION
- IPI_CPU_BACKTRACE
- IPI_CPU_CRASH_STOP
- IPI_CPU_START
- IPI_CPU_STOP
- IPI_CPU_TEST
- IPI_DOORBELL_END
- IPI_DOORBELL_MASK
- IPI_DOORBELL_START
- IPI_EMPTY
- IPI_ID_ANY
- IPI_IRQ
- IPI_IRQ_OFFSET
- IPI_IRQ_WORK
- IPI_KDUMP_CPU_STOP
- IPI_MAX
- IPI_MB_CHNL_RX
- IPI_MB_CHNL_TX
- IPI_MB_STATUS_IDLE
- IPI_MB_STATUS_RECV_PENDING
- IPI_MB_STATUS_SEND_PENDING
- IPI_MDP
- IPI_MESSAGE
- IPI_NOP
- IPI_PRIORITY
- IPI_RESCHEDULE
- IPI_RESET_LIMIT
- IPI_SMC_ACK_EIRQ_MASK
- IPI_SMC_ENQUIRY_DIRQ_MASK
- IPI_TIMEOUT
- IPI_TIMEOUT_MS
- IPI_TIMER
- IPI_VDEC_H264
- IPI_VDEC_VP8
- IPI_VDEC_VP9
- IPI_VENC_H264
- IPI_VENC_VP8
- IPI_VPU_INIT
- IPI_WAKEUP
- IPL
- IPLL_CON0
- IPLL_LOCK
- IPL_ATTR_CCW_STORE_FN
- IPL_ATTR_SHOW_FN
- IPL_BP0_CCW_LEN
- IPL_BP0_FCP_LEN
- IPL_BP_CCW_LEN
- IPL_BP_FCP_LEN
- IPL_BS
- IPL_CCW_STR
- IPL_DEV0
- IPL_DEV1
- IPL_DEVICE
- IPL_DEVICE_OFFSET
- IPL_FCP_DUMP_STR
- IPL_FCP_STR
- IPL_MAX
- IPL_MAX_SUPPORTED_VERSION
- IPL_MCHECK
- IPL_MIN
- IPL_NSS_STR
- IPL_PARM_BLOCK_VERSION
- IPL_PARTITION_DATA
- IPL_PB0_CCW_VM_FLAG_NSS
- IPL_PB0_CCW_VM_FLAG_VP
- IPL_PB0_FCP_OPT_DUMP
- IPL_PB0_FCP_OPT_IPL
- IPL_PB0_FLAG_LOADPARM
- IPL_PBT_CCW
- IPL_PBT_FCP
- IPL_PBT_SCP_DATA
- IPL_PERF
- IPL_PL_FLAG_IPLPS
- IPL_PL_FLAG_IPLSR
- IPL_PL_FLAG_SIPL
- IPL_POWERFAIL
- IPL_RBT_CERTIFICATES
- IPL_RBT_COMPONENTS
- IPL_RB_CERT_UNKNOWN
- IPL_RB_COMPONENT_FLAG_SIGNED
- IPL_RB_COMPONENT_FLAG_VERIFIED
- IPL_SW0
- IPL_SW1
- IPL_TIMER
- IPL_TYPE_CCW
- IPL_TYPE_FCP
- IPL_TYPE_FCP_DUMP
- IPL_TYPE_NSS
- IPL_TYPE_UNKNOWN
- IPL_UNKNOWN_STR
- IPMB_MSG_LEN_IDX
- IPMB_MSG_PAYLOAD_LEN_MAX
- IPMB_REQUEST_LEN_MIN
- IPMICTL_GET_MAINTENANCE_MODE_CMD
- IPMICTL_GET_MY_ADDRESS_CMD
- IPMICTL_GET_MY_CHANNEL_ADDRESS_CMD
- IPMICTL_GET_MY_CHANNEL_LUN_CMD
- IPMICTL_GET_MY_LUN_CMD
- IPMICTL_GET_TIMING_PARMS_CMD
- IPMICTL_RECEIVE_MSG
- IPMICTL_RECEIVE_MSG_TRUNC
- IPMICTL_REGISTER_FOR_CMD
- IPMICTL_REGISTER_FOR_CMD_CHANS
- IPMICTL_SEND_COMMAND
- IPMICTL_SEND_COMMAND_SETTIME
- IPMICTL_SET_GETS_EVENTS_CMD
- IPMICTL_SET_MAINTENANCE_MODE_CMD
- IPMICTL_SET_MY_ADDRESS_CMD
- IPMICTL_SET_MY_CHANNEL_ADDRESS_CMD
- IPMICTL_SET_MY_CHANNEL_LUN_CMD
- IPMICTL_SET_MY_LUN_CMD
- IPMICTL_SET_TIMING_PARMS_CMD
- IPMICTL_UNREGISTER_FOR_CMD
- IPMICTL_UNREGISTER_FOR_CMD_CHANS
- IPMI_ADD_SEL_ENTRY_CMD
- IPMI_ASYNC_EVENT_RECV_TYPE
- IPMI_ATCA_GET_ADDR_INFO_CMD
- IPMI_ATCA_PPS_GRACEFUL_RESTART
- IPMI_ATCA_PPS_IANA
- IPMI_ATCA_SET_POWER_CMD
- IPMI_BMC_CHANNEL
- IPMI_BMC_EVT_MSG_BUFF
- IPMI_BMC_EVT_MSG_INTR
- IPMI_BMC_IOCTL_CLEAR_SMS_ATN
- IPMI_BMC_IOCTL_FORCE_ABORT
- IPMI_BMC_IOCTL_SET_SMS_ATN
- IPMI_BMC_RCV_MSG_INTR
- IPMI_BMC_SLAVE_ADDR
- IPMI_BMC_SYS_LOG
- IPMI_BT_INTMASK_CLEAR_IRQ_BIT
- IPMI_BT_INTMASK_ENABLE_IRQ_BIT
- IPMI_BT_INTMASK_REG
- IPMI_BUS_ERR
- IPMI_CC_NO_ERROR
- IPMI_CHANNEL_MEDIUM_8023LAN
- IPMI_CHANNEL_MEDIUM_ASYNC
- IPMI_CHANNEL_MEDIUM_ICMB09
- IPMI_CHANNEL_MEDIUM_ICMB10
- IPMI_CHANNEL_MEDIUM_IPMB
- IPMI_CHANNEL_MEDIUM_OEM_MAX
- IPMI_CHANNEL_MEDIUM_OEM_MIN
- IPMI_CHANNEL_MEDIUM_OTHER_LAN
- IPMI_CHANNEL_MEDIUM_PCI_SMBUS
- IPMI_CHANNEL_MEDIUM_SMBUS1
- IPMI_CHANNEL_MEDIUM_SMBUS2
- IPMI_CHANNEL_MEDIUM_SYSINTF
- IPMI_CHANNEL_MEDIUM_USB1
- IPMI_CHANNEL_MEDIUM_USB2
- IPMI_CHANNEL_PROTOCOL_BT10
- IPMI_CHANNEL_PROTOCOL_BT15
- IPMI_CHANNEL_PROTOCOL_ICMB
- IPMI_CHANNEL_PROTOCOL_IPMB
- IPMI_CHANNEL_PROTOCOL_KCS
- IPMI_CHANNEL_PROTOCOL_SMBUS
- IPMI_CHANNEL_PROTOCOL_SMIC
- IPMI_CHANNEL_PROTOCOL_TMODE
- IPMI_CHAN_ALL
- IPMI_CHASSIS_CONTROL_CMD
- IPMI_CHASSIS_POWER_CYCLE
- IPMI_CHASSIS_POWER_DOWN
- IPMI_CLEAR_MSG_FLAGS_CMD
- IPMI_CMD_GET_EVENT_RECEIVER
- IPMI_CMD_RECV_TYPE
- IPMI_COLD_RESET_CMD
- IPMI_CPI1_MANUFACTURER_ID
- IPMI_CPI1_PRODUCT_ID
- IPMI_DMI_TYPE_BT
- IPMI_DMI_TYPE_KCS
- IPMI_DMI_TYPE_SMIC
- IPMI_DMI_TYPE_SSIF
- IPMI_DRIVER_VERSION
- IPMI_DYN_DEV_ID_EXPIRY
- IPMI_ERR_MSG_TRUNCATED
- IPMI_ERR_UNSPECIFIED
- IPMI_GET_BMC_GLOBAL_ENABLES_CMD
- IPMI_GET_CHANNEL_INFO_CMD
- IPMI_GET_DEVICE_GUID_CMD
- IPMI_GET_DEVICE_ID_CMD
- IPMI_GET_EVENT_RECEIVER_CMD
- IPMI_GET_MSG_CMD
- IPMI_GET_MSG_FLAGS_CMD
- IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_CMD
- IPMI_INVALID_CMD_COMPLETION_CODE
- IPMI_INVALID_COMMAND_ERR
- IPMI_IOC_MAGIC
- IPMI_IO_ADDR_SPACE
- IPMI_IPMB_ADDR_TYPE
- IPMI_IPMB_BROADCAST_ADDR_TYPE
- IPMI_IPMB_NUM_SEQ
- IPMI_LAN_ADDR_TYPE
- IPMI_LOST_ARBITRATION_ERR
- IPMI_MAINTENANCE_MODE_AUTO
- IPMI_MAINTENANCE_MODE_OFF
- IPMI_MAINTENANCE_MODE_ON
- IPMI_MAX_ADDR_SIZE
- IPMI_MAX_CHANNELS
- IPMI_MAX_INTFS
- IPMI_MAX_MSG_LENGTH
- IPMI_MEM_ADDR_SPACE
- IPMI_MOTOROLA_MANUFACTURER_ID
- IPMI_MOTOROLA_PPS_IPMC_PRODUCT_ID
- IPMI_NAK_ON_WRITE_ERR
- IPMI_NETFN_APP_REQUEST
- IPMI_NETFN_APP_RESPONSE
- IPMI_NETFN_ATCA
- IPMI_NETFN_CHASSIS_REQUEST
- IPMI_NETFN_FIRMWARE_REQUEST
- IPMI_NETFN_FIRMWARE_RESPONSE
- IPMI_NETFN_OEM
- IPMI_NETFN_OEM_1
- IPMI_NETFN_OEM_8
- IPMI_NETFN_SENSOR_EVENT_REQUEST
- IPMI_NETFN_SENSOR_EVENT_RESPONSE
- IPMI_NETFN_SENSOR_EVT
- IPMI_NETFN_STORAGE_REQUEST
- IPMI_NETFN_STORAGE_RESPONSE
- IPMI_NODE_BUSY_ERR
- IPMI_NOT_IN_MY_STATE_ERR
- IPMI_NUM_CHANNELS
- IPMI_NUM_STATS
- IPMI_OEM_RECV_TYPE
- IPMI_OP_RGN_CMD
- IPMI_OP_RGN_NETFN
- IPMI_PANIC_DEFAULT
- IPMI_PICMG_ID
- IPMI_PLAT_IF_SI
- IPMI_PLAT_IF_SSIF
- IPMI_READ_EVENT_MSG_BUFFER_CMD
- IPMI_REQUEST_EV_TIME
- IPMI_REQ_LEN_EXCEEDED_ERR
- IPMI_REQ_LEN_INVALID_ERR
- IPMI_RESPONSE_RECV_TYPE
- IPMI_RESPONSE_RESPONSE_TYPE
- IPMI_SEND_MSG_CMD
- IPMI_SEND_PANIC_EVENT
- IPMI_SEND_PANIC_EVENT_NONE
- IPMI_SEND_PANIC_EVENT_STRING
- IPMI_SET_BMC_GLOBAL_ENABLES_CMD
- IPMI_SET_TIMEOUT_FORCE_HB
- IPMI_SET_TIMEOUT_HB_IF_NECESSARY
- IPMI_SET_TIMEOUT_NO_HB
- IPMI_SI_ATTR
- IPMI_SSIF_ATTR
- IPMI_STAT_dropped_rexmit_ipmb_commands
- IPMI_STAT_dropped_rexmit_lan_commands
- IPMI_STAT_events
- IPMI_STAT_handled_commands
- IPMI_STAT_handled_ipmb_responses
- IPMI_STAT_handled_lan_responses
- IPMI_STAT_handled_local_responses
- IPMI_STAT_invalid_commands
- IPMI_STAT_invalid_events
- IPMI_STAT_invalid_ipmb_responses
- IPMI_STAT_invalid_lan_responses
- IPMI_STAT_retransmitted_ipmb_commands
- IPMI_STAT_retransmitted_lan_commands
- IPMI_STAT_sent_invalid_commands
- IPMI_STAT_sent_ipmb_command_errs
- IPMI_STAT_sent_ipmb_commands
- IPMI_STAT_sent_ipmb_responses
- IPMI_STAT_sent_lan_command_errs
- IPMI_STAT_sent_lan_commands
- IPMI_STAT_sent_lan_responses
- IPMI_STAT_sent_local_commands
- IPMI_STAT_timed_out_ipmb_broadcasts
- IPMI_STAT_timed_out_ipmb_commands
- IPMI_STAT_timed_out_lan_commands
- IPMI_STAT_unhandled_commands
- IPMI_STAT_unhandled_ipmb_responses
- IPMI_STAT_unhandled_lan_responses
- IPMI_STAT_unhandled_local_responses
- IPMI_SYSTEM_INTERFACE_ADDR_TYPE
- IPMI_TIMEOUT
- IPMI_TIMEOUT_COMPLETION_CODE
- IPMI_TIMEOUT_ERR
- IPMI_TIMEOUT_JIFFIES
- IPMI_TIMEOUT_TIME
- IPMI_UNKNOWN_ERR_COMPLETION_CODE
- IPMI_WARM_RESET_CMD
- IPMI_WATCH_MASK_CHECK_COMMANDS
- IPMI_WATCH_MASK_CHECK_MESSAGES
- IPMI_WATCH_MASK_CHECK_WATCHDOG
- IPMI_WDOG_GET_TIMER
- IPMI_WDOG_RESET_TIMER
- IPMI_WDOG_SET_TIMER
- IPMI_WDOG_TIMER_NOT_INIT_RESP
- IPMMU_CTX_INVALID
- IPMMU_CTX_MAX
- IPMMU_UTLB_MAX
- IPMRA_CREPORT_DST_ADDR
- IPMRA_CREPORT_MAX
- IPMRA_CREPORT_MSGTYPE
- IPMRA_CREPORT_PKT
- IPMRA_CREPORT_SRC_ADDR
- IPMRA_CREPORT_UNSPEC
- IPMRA_CREPORT_VIF_ID
- IPMRA_TABLE_CACHE_RES_QUEUE_LEN
- IPMRA_TABLE_ID
- IPMRA_TABLE_MAX
- IPMRA_TABLE_MROUTE_DO_ASSERT
- IPMRA_TABLE_MROUTE_DO_PIM
- IPMRA_TABLE_MROUTE_DO_WRVIFWHOLE
- IPMRA_TABLE_MROUTE_REG_VIF_NUM
- IPMRA_TABLE_UNSPEC
- IPMRA_TABLE_VIFS
- IPMRA_VIF
- IPMRA_VIFA_BYTES_IN
- IPMRA_VIFA_BYTES_OUT
- IPMRA_VIFA_FLAGS
- IPMRA_VIFA_IFINDEX
- IPMRA_VIFA_LOCAL_ADDR
- IPMRA_VIFA_MAX
- IPMRA_VIFA_PACKETS_IN
- IPMRA_VIFA_PACKETS_OUT
- IPMRA_VIFA_PAD
- IPMRA_VIFA_REMOTE_ADDR
- IPMRA_VIFA_UNSPEC
- IPMRA_VIFA_VIF_ID
- IPMRA_VIF_MAX
- IPMRA_VIF_UNSPEC
- IPM_BIT_OFFSET
- IPMode
- IPOCTAL_MAX_BOARDS
- IPOIB_CM_BUF_SIZE
- IPOIB_CM_COPYBREAK
- IPOIB_CM_HEAD_SIZE
- IPOIB_CM_IETF_ID
- IPOIB_CM_MAX_CONN_QP
- IPOIB_CM_MTU
- IPOIB_CM_RX_DELAY
- IPOIB_CM_RX_DRAIN_WRID
- IPOIB_CM_RX_ERROR
- IPOIB_CM_RX_FLUSH
- IPOIB_CM_RX_LIVE
- IPOIB_CM_RX_RESERVE
- IPOIB_CM_RX_SG
- IPOIB_CM_RX_TIMEOUT
- IPOIB_CM_RX_UPDATE_MASK
- IPOIB_CM_RX_UPDATE_TIME
- IPOIB_CM_SUPPORTED
- IPOIB_ENCAP_LEN
- IPOIB_FLAGS_RC
- IPOIB_FLAGS_UC
- IPOIB_FLAG_ADMIN_CM
- IPOIB_FLAG_ADMIN_UP
- IPOIB_FLAG_DEV_ADDR_CTRL
- IPOIB_FLAG_DEV_ADDR_SET
- IPOIB_FLAG_INITIALIZED
- IPOIB_FLAG_OPER_UP
- IPOIB_FLAG_SUBINTERFACE
- IPOIB_FLAG_UMCAST
- IPOIB_FLUSH_HEAVY
- IPOIB_FLUSH_LIGHT
- IPOIB_FLUSH_NORMAL
- IPOIB_GLOBAL_STATS_LEN
- IPOIB_HARD_LEN
- IPOIB_LEGACY_CHILD
- IPOIB_MAX_BACKOFF_SECONDS
- IPOIB_MAX_MCAST_QUEUE
- IPOIB_MAX_PATH_REC_QUEUE
- IPOIB_MAX_QUEUE_SIZE
- IPOIB_MCAST_FLAG_ATTACHED
- IPOIB_MCAST_FLAG_BUSY
- IPOIB_MCAST_FLAG_FOUND
- IPOIB_MCAST_FLAG_SENDONLY
- IPOIB_MIN_QUEUE_SIZE
- IPOIB_MODE_CONNECTED
- IPOIB_MODE_DATAGRAM
- IPOIB_NEIGH_TBL_FLUSH
- IPOIB_NETDEV_STAT
- IPOIB_NON_CHILD
- IPOIB_NUM_WC
- IPOIB_OP_CM
- IPOIB_OP_RECV
- IPOIB_PKEY_ASSIGNED
- IPOIB_PSEUDO_LEN
- IPOIB_QPN
- IPOIB_QPN_MASK
- IPOIB_RTNL_CHILD
- IPOIB_RX_RING_SIZE
- IPOIB_STOP_REAPER
- IPOIB_TX_RING_SIZE
- IPOIB_UD_BUF_SIZE
- IPOIB_UD_HEAD_SIZE
- IPOIB_UD_MTU
- IPOIB_UD_RX_SG
- IPON
- IPOPT_ALT_CID_EN
- IPOPT_ARP_REDIRECT_EN
- IPOPT_CIPSO
- IPOPT_CLASS
- IPOPT_CLASS_MASK
- IPOPT_CONTROL
- IPOPT_COPIED
- IPOPT_COPY
- IPOPT_END
- IPOPT_EOL
- IPOPT_FRAGMENTATION_DISABLE
- IPOPT_FRAGMENT_DISABLE
- IPOPT_GRAT_ARP_EN
- IPOPT_IN_FORWARD_EN
- IPOPT_IPV4_PROTOCOL_ENABLE
- IPOPT_IPV4_TOS_EN
- IPOPT_LEARN_IQN_EN
- IPOPT_LSRR
- IPOPT_MEASUREMENT
- IPOPT_MINOFF
- IPOPT_NOOP
- IPOPT_NOP
- IPOPT_NUMBER
- IPOPT_NUMBER_MASK
- IPOPT_OFFSET
- IPOPT_OLEN
- IPOPT_OPTVAL
- IPOPT_RA
- IPOPT_REQ_VID_EN
- IPOPT_RESERVED1
- IPOPT_RESERVED2
- IPOPT_RR
- IPOPT_SEC
- IPOPT_SID
- IPOPT_SSRR
- IPOPT_TIMESTAMP
- IPOPT_TS
- IPOPT_TS_PRESPEC
- IPOPT_TS_TSANDADDR
- IPOPT_TS_TSONLY
- IPOPT_USE_VID_EN
- IPOPT_VLAN_TAGGING_ENABLE
- IPORTMXACLKSEL0EX
- IPORTMXACLKSEL0EX_ACLKSEL0EX_EXTERNAL
- IPORTMXACLKSEL0EX_ACLKSEL0EX_INTERNAL
- IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK
- IPORTMXCNTCTR
- IPORTMXCNTMONI
- IPORTMXCOUNTER
- IPORTMXCTR1
- IPORTMXCTR1_CHSEL_ALL
- IPORTMXCTR1_CHSEL_D0
- IPORTMXCTR1_CHSEL_D0_D2
- IPORTMXCTR1_CHSEL_D1
- IPORTMXCTR1_CHSEL_D2
- IPORTMXCTR1_CHSEL_DMIX
- IPORTMXCTR1_CHSEL_MASK
- IPORTMXCTR1_FSSEL_11_025
- IPORTMXCTR1_FSSEL_12
- IPORTMXCTR1_FSSEL_16
- IPORTMXCTR1_FSSEL_176_4
- IPORTMXCTR1_FSSEL_192
- IPORTMXCTR1_FSSEL_22_05
- IPORTMXCTR1_FSSEL_24
- IPORTMXCTR1_FSSEL_32
- IPORTMXCTR1_FSSEL_44_1
- IPORTMXCTR1_FSSEL_48
- IPORTMXCTR1_FSSEL_8
- IPORTMXCTR1_FSSEL_88_2
- IPORTMXCTR1_FSSEL_96
- IPORTMXCTR1_FSSEL_MASK
- IPORTMXCTR1_LRSEL_I2S
- IPORTMXCTR1_LRSEL_LEFT
- IPORTMXCTR1_LRSEL_MASK
- IPORTMXCTR1_LRSEL_RIGHT
- IPORTMXCTR1_OUTBITSEL_16
- IPORTMXCTR1_OUTBITSEL_20
- IPORTMXCTR1_OUTBITSEL_24
- IPORTMXCTR1_OUTBITSEL_32
- IPORTMXCTR1_OUTBITSEL_MASK
- IPORTMXCTR2
- IPORTMXCTR2_ACLKSEL_A1
- IPORTMXCTR2_ACLKSEL_A2
- IPORTMXCTR2_ACLKSEL_A2PLL
- IPORTMXCTR2_ACLKSEL_F1
- IPORTMXCTR2_ACLKSEL_F2
- IPORTMXCTR2_ACLKSEL_MASK
- IPORTMXCTR2_ACLKSEL_RX1
- IPORTMXCTR2_ACLKSEL_RX2
- IPORTMXCTR2_DACCKSEL_1_1
- IPORTMXCTR2_DACCKSEL_1_2
- IPORTMXCTR2_DACCKSEL_1_3
- IPORTMXCTR2_DACCKSEL_2_3
- IPORTMXCTR2_DACCKSEL_MASK
- IPORTMXCTR2_EXTLSIFSSEL_24
- IPORTMXCTR2_EXTLSIFSSEL_36
- IPORTMXCTR2_EXTLSIFSSEL_MASK
- IPORTMXCTR2_MSSEL_MASK
- IPORTMXCTR2_MSSEL_MASTER
- IPORTMXCTR2_MSSEL_SLAVE
- IPORTMXCTR2_REQEN_DISABLE
- IPORTMXCTR2_REQEN_ENABLE
- IPORTMXCTR2_REQEN_MASK
- IPORTMXEXNOE
- IPORTMXEXNOE_PCMINOE_INPUT
- IPORTMXEXNOE_PCMINOE_MASK
- IPORTMXEXNOE_PCMINOE_OUTPUT
- IPORTMXMASK
- IPORTMXMASK_IUXCKMSK_MASK
- IPORTMXMASK_IUXCKMSK_OFF
- IPORTMXMASK_IUXCKMSK_ON
- IPORTMXMASK_XCKMSK_MASK
- IPORTMXMASK_XCKMSK_OFF
- IPORTMXMASK_XCKMSK_ON
- IPORTMXRSTCTR
- IPORTMXRSTCTR_RSTPI_MASK
- IPORTMXRSTCTR_RSTPI_RELEASE
- IPORTMXRSTCTR_RSTPI_RESET
- IPORT_BITWIDTH
- IPORT_RESET_PENDING
- IPOUTDISCARDS
- IPOUTNOROUTES
- IPOUTREQUESTS
- IPO_IATTR_CONNECT_DATA
- IPO_IATTR_CONNECT_SQE
- IPPOD_SIZE
- IPPROTO_AH
- IPPROTO_BEETPH
- IPPROTO_COMP
- IPPROTO_DCCP
- IPPROTO_DSTOPTS
- IPPROTO_EGP
- IPPROTO_ENCAP
- IPPROTO_ESP
- IPPROTO_FRAGMENT
- IPPROTO_GRE
- IPPROTO_HOPOPTS
- IPPROTO_ICMP
- IPPROTO_ICMPV6
- IPPROTO_IDP
- IPPROTO_IGMP
- IPPROTO_IP
- IPPROTO_IPIP
- IPPROTO_IPV6
- IPPROTO_L2TP
- IPPROTO_MASK
- IPPROTO_MAX
- IPPROTO_MH
- IPPROTO_MPLS
- IPPROTO_MTP
- IPPROTO_NONE
- IPPROTO_PIM
- IPPROTO_PUP
- IPPROTO_RAW
- IPPROTO_ROUTING
- IPPROTO_RSVP
- IPPROTO_SCTP
- IPPROTO_SHIFT
- IPPROTO_TCP
- IPPROTO_TP
- IPPROTO_UDP
- IPPROTO_UDPLITE
- IPP_BAD_CS_CNT
- IPP_BAD_CS_CNT_COUNT
- IPP_CFIG
- IPP_CFIG_CKSUM_EN
- IPP_CFIG_DEBUG_BUS_OUT_EN
- IPP_CFIG_DFIFO_ECC_EN
- IPP_CFIG_DFIFO_PIO_W
- IPP_CFIG_DROP_BAD_CRC
- IPP_CFIG_FFLP_CS_PIO_W
- IPP_CFIG_IPP_ENABLE
- IPP_CFIG_IP_MAX_PKT
- IPP_CFIG_IP_MAX_PKT_SHIFT
- IPP_CFIG_PFIFO_PIO_W
- IPP_CFIG_SOFT_RST
- IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE
- IPP_COMMON_REG_LIST_DCE_BASE
- IPP_CS_STAT
- IPP_CS_STAT_BAD_NUM
- IPP_CS_STAT_BCYC_CNT
- IPP_CS_STAT_CS_FAIL
- IPP_CS_STAT_CS_STATE
- IPP_CS_STAT_IP_LEN
- IPP_CS_STAT_TERM
- IPP_DBG_SEL
- IPP_DBG_SEL_SEL
- IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE
- IPP_DCE100_REG_LIST_DCE_BASE
- IPP_DCE110_REG_LIST_DCE_BASE
- IPP_DCE120_MASK_SH_LIST_SOC_BASE
- IPP_DCN10_REG_FIELD_LIST
- IPP_DEGAMMA_MODE_BYPASS
- IPP_DEGAMMA_MODE_HW_sRGB
- IPP_DEGAMMA_MODE_HW_xvYCC
- IPP_DEGAMMA_MODE_USER_PWL
- IPP_DFIFO_ECC_SYND
- IPP_DFIFO_ECC_SYND_SYND
- IPP_DFIFO_EOP_RD_PTR
- IPP_DFIFO_EOP_RD_PTR_PTR
- IPP_DFIFO_RD0
- IPP_DFIFO_RD0_DATA
- IPP_DFIFO_RD1
- IPP_DFIFO_RD1_DATA
- IPP_DFIFO_RD2
- IPP_DFIFO_RD2_DATA
- IPP_DFIFO_RD3
- IPP_DFIFO_RD3_DATA
- IPP_DFIFO_RD4
- IPP_DFIFO_RD4_DATA
- IPP_DFIFO_RD_PTR
- IPP_DFIFO_RD_PTR_PTR
- IPP_DFIFO_WR0
- IPP_DFIFO_WR0_DATA
- IPP_DFIFO_WR1
- IPP_DFIFO_WR1_DATA
- IPP_DFIFO_WR2
- IPP_DFIFO_WR2_DATA
- IPP_DFIFO_WR3
- IPP_DFIFO_WR3_DATA
- IPP_DFIFO_WR4
- IPP_DFIFO_WR4_DATA
- IPP_DFIFO_WR_PTR
- IPP_DFIFO_WR_PTR_PTR
- IPP_ECC
- IPP_ECC_COUNT
- IPP_ECC_CTL
- IPP_ECC_CTL_COR_1
- IPP_ECC_CTL_COR_ALL
- IPP_ECC_CTL_COR_DBL
- IPP_ECC_CTL_COR_FSR
- IPP_ECC_CTL_COR_LST
- IPP_ECC_CTL_COR_SND
- IPP_ECC_CTL_COR_SNG
- IPP_ECC_CTL_DIS_DBL
- IPP_FFLP_CS_INFO
- IPP_FFLP_CS_INFO_L2_OP
- IPP_FFLP_CS_INFO_L3_VER
- IPP_FFLP_CS_INFO_L4_PROTO
- IPP_FFLP_CS_INFO_PKT_ID
- IPP_FFLP_CS_INFO_V4_HD_LEN
- IPP_INT_STAT
- IPP_INT_STAT_ALL
- IPP_INT_STAT_BAD_CS_MX
- IPP_INT_STAT_DFIFO_CE
- IPP_INT_STAT_DFIFO_ECC
- IPP_INT_STAT_DFIFO_ECC_IDX
- IPP_INT_STAT_DFIFO_UE
- IPP_INT_STAT_ECC_ERR_MAX
- IPP_INT_STAT_EOP_MISS
- IPP_INT_STAT_PFIFO_ERR_IDX
- IPP_INT_STAT_PFIFO_OVER
- IPP_INT_STAT_PFIFO_PERR
- IPP_INT_STAT_PFIFO_UND
- IPP_INT_STAT_PKT_DIS_MX
- IPP_INT_STAT_SOP_MISS
- IPP_LIMIT_AREA
- IPP_LIMIT_BUFFER
- IPP_LIMIT_MAX
- IPP_LIMIT_ROTATED
- IPP_MASK_SH_LIST_DCN
- IPP_MASK_SH_LIST_DCN10
- IPP_MASK_SH_LIST_DCN20
- IPP_MSK
- IPP_MSK_ALL
- IPP_MSK_BAD_CS
- IPP_MSK_DFIFO_EOP_SOP
- IPP_MSK_DFIFO_UC
- IPP_MSK_ECC_ERR_MX
- IPP_MSK_PFIFO_OVER
- IPP_MSK_PFIFO_PAR
- IPP_MSK_PFIFO_UND
- IPP_MSK_PKT_DIS_CNT
- IPP_OUTPUT_FORMAT_12_BIT_FIX
- IPP_OUTPUT_FORMAT_16_BIT_BYPASS
- IPP_OUTPUT_FORMAT_FLOAT
- IPP_PFIFO_RD0
- IPP_PFIFO_RD0_DATA
- IPP_PFIFO_RD1
- IPP_PFIFO_RD1_DATA
- IPP_PFIFO_RD2
- IPP_PFIFO_RD2_DATA
- IPP_PFIFO_RD3
- IPP_PFIFO_RD3_DATA
- IPP_PFIFO_RD4
- IPP_PFIFO_RD4_DATA
- IPP_PFIFO_RD_PTR
- IPP_PFIFO_RD_PTR_PTR
- IPP_PFIFO_WR0
- IPP_PFIFO_WR0_DATA
- IPP_PFIFO_WR1
- IPP_PFIFO_WR1_DATA
- IPP_PFIFO_WR2
- IPP_PFIFO_WR2_DATA
- IPP_PFIFO_WR3
- IPP_PFIFO_WR3_DATA
- IPP_PFIFO_WR4
- IPP_PFIFO_WR4_DATA
- IPP_PFIFO_WR_PTR
- IPP_PFIFO_WR_PTR_PTR
- IPP_PKT_DIS
- IPP_PKT_DIS_COUNT
- IPP_PRESCALE_MODE_BYPASS
- IPP_PRESCALE_MODE_FIXED_SIGNED
- IPP_PRESCALE_MODE_FIXED_UNSIGNED
- IPP_PRESCALE_MODE_FLOAT_SIGNED
- IPP_PRESCALE_MODE_FLOAT_UNSIGNED
- IPP_REG_FIELD_LIST
- IPP_REG_LIST_DCN
- IPP_REG_LIST_DCN10
- IPP_REG_LIST_DCN20
- IPP_SCALE_LIMIT
- IPP_SF
- IPP_SIZE_LIMIT
- IPP_SM
- IPP_SM_SM
- IPP_SRCDST_FORMAT
- IPP_SRCDST_MFORMAT
- IPP_SRCDST_TILE_FORMAT
- IPQ806X_LPAIF_I2S_PORT_CODEC_MIC
- IPQ806X_LPAIF_I2S_PORT_CODEC_SPK
- IPQ806X_LPAIF_I2S_PORT_MI2S
- IPQ806X_LPAIF_I2S_PORT_SEC_MIC
- IPQ806X_LPAIF_I2S_PORT_SEC_SPK
- IPQ806X_LPAIF_RDMA_CHAN_MI2S
- IPQ806X_LPAIF_RDMA_CHAN_PCM0
- IPQ806X_LPAIF_RDMA_CHAN_PCM1
- IPQ_MUX_NA
- IPQ_MUX_audio_pcm
- IPQ_MUX_gpio
- IPQ_MUX_gsbi1
- IPQ_MUX_gsbi2
- IPQ_MUX_gsbi4
- IPQ_MUX_gsbi5
- IPQ_MUX_gsbi5_spi_cs1
- IPQ_MUX_gsbi5_spi_cs2
- IPQ_MUX_gsbi5_spi_cs3
- IPQ_MUX_gsbi6
- IPQ_MUX_gsbi7
- IPQ_MUX_mdio
- IPQ_MUX_mi2s
- IPQ_MUX_nand
- IPQ_MUX_nss_spi
- IPQ_MUX_pcie1_clk_req
- IPQ_MUX_pcie1_prsnt
- IPQ_MUX_pcie1_pwren
- IPQ_MUX_pcie1_pwren_n
- IPQ_MUX_pcie1_pwrflt
- IPQ_MUX_pcie1_rst
- IPQ_MUX_pcie2_clk_req
- IPQ_MUX_pcie2_prsnt
- IPQ_MUX_pcie2_pwren
- IPQ_MUX_pcie2_pwren_n
- IPQ_MUX_pcie2_pwrflt
- IPQ_MUX_pcie2_rst
- IPQ_MUX_pcie3_clk_req
- IPQ_MUX_pcie3_prsnt
- IPQ_MUX_pcie3_pwren
- IPQ_MUX_pcie3_pwren_n
- IPQ_MUX_pcie3_pwrflt
- IPQ_MUX_pcie3_rst
- IPQ_MUX_pdm
- IPQ_MUX_ps_hold
- IPQ_MUX_rgmii2
- IPQ_MUX_sata
- IPQ_MUX_sdc1
- IPQ_MUX_spdif
- IPQ_MUX_spmi
- IPQ_MUX_ssbi
- IPQ_MUX_tsif1
- IPQ_MUX_tsif2
- IPQ_MUX_usb2_hsic
- IPQ_MUX_usb_fs
- IPQ_MUX_usb_fs_n
- IPR
- IPR2
- IPR2_CAPTURE_CH_0_HALF_LOOP
- IPR2_CAPTURE_CH_0_LOOP
- IPR2_PLAYBACK_CH_0_HALF_LOOP
- IPR2_PLAYBACK_CH_0_LOOP
- IPR3
- IPRA
- IPRANGE_DST
- IPRANGE_DST_INV
- IPRANGE_SRC
- IPRANGE_SRC_INV
- IPRB_MODE_COLLECT_A
- IPRB_MODE_NORMAL
- IPRB_MODE_SERVICE_A
- IPRB_MODE_SERVICE_B
- IPREASMFAILS
- IPREASMOKS
- IPREASMREQDS
- IPREASMTIMEOUT
- IPRETRYPERR_F
- IPRETRYPERR_S
- IPRETRYPERR_V
- IPRINTK
- IPROC_ADC_AUXDATA_RDY_INTR
- IPROC_ADC_AUXIN_SCAN_ENA
- IPROC_ADC_CHANNEL
- IPROC_ADC_CHANNEL_DATA
- IPROC_ADC_CHANNEL_DATA_LOST
- IPROC_ADC_CHANNEL_DATA_LOST_MASK
- IPROC_ADC_CHANNEL_EMPTY_INTR
- IPROC_ADC_CHANNEL_EMPTY_INTR_MASK
- IPROC_ADC_CHANNEL_ENABLE
- IPROC_ADC_CHANNEL_ENABLE_MASK
- IPROC_ADC_CHANNEL_FULL_INTR
- IPROC_ADC_CHANNEL_FULL_INTR_MASK
- IPROC_ADC_CHANNEL_INTERRUPT_MASK
- IPROC_ADC_CHANNEL_INTERRUPT_STATUS
- IPROC_ADC_CHANNEL_MODE
- IPROC_ADC_CHANNEL_MODE_MASK
- IPROC_ADC_CHANNEL_MODE_SNAPSHOT
- IPROC_ADC_CHANNEL_MODE_TDM
- IPROC_ADC_CHANNEL_OFFSET
- IPROC_ADC_CHANNEL_REGCTL1
- IPROC_ADC_CHANNEL_REGCTL2
- IPROC_ADC_CHANNEL_ROUNDS
- IPROC_ADC_CHANNEL_ROUNDS_MASK
- IPROC_ADC_CHANNEL_SEL
- IPROC_ADC_CHANNEL_SEL_MASK
- IPROC_ADC_CHANNEL_STATUS
- IPROC_ADC_CHANNEL_TOTAL_ENTERIES
- IPROC_ADC_CHANNEL_TOTAL_ENTERIES_MASK
- IPROC_ADC_CHANNEL_VALID_ENTERIES
- IPROC_ADC_CHANNEL_VALID_ENTERIES_MASK
- IPROC_ADC_CHANNEL_WATERMARK
- IPROC_ADC_CHANNEL_WATERMARK_MASK
- IPROC_ADC_CHANNEL_WTRMRK_INTR
- IPROC_ADC_CHANNEL_WTRMRK_INTR_MASK
- IPROC_ADC_CONTROLLER_EN
- IPROC_ADC_INTMASK_RETRY_ATTEMPTS
- IPROC_ADC_INTR
- IPROC_ADC_INTR_MASK
- IPROC_ADC_PWR_ADC
- IPROC_ADC_PWR_BG
- IPROC_ADC_PWR_LDO
- IPROC_ADC_READ_TIMEOUT
- IPROC_ADC_WATER_MARK_INTR_ENABLE
- IPROC_ADC_WATER_MARK_LEVEL
- IPROC_ANALOG_CONTROL
- IPROC_AUX_DATA
- IPROC_CLK_AON
- IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK
- IPROC_CLK_ARM_DIV_OFFSET
- IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT
- IPROC_CLK_EMBED_PWRCTRL
- IPROC_CLK_INVALID_OFFSET
- IPROC_CLK_MAX_FREQ_POLICY
- IPROC_CLK_MCLK_DIV_BY_2
- IPROC_CLK_NAME_LEN
- IPROC_CLK_NEEDS_READ_BACK
- IPROC_CLK_PLLARMA_LOCK_SHIFT
- IPROC_CLK_PLLARMA_NDIV_INT_MASK
- IPROC_CLK_PLLARMA_NDIV_INT_SHIFT
- IPROC_CLK_PLLARMA_OFFSET
- IPROC_CLK_PLLARMA_PDIV_MASK
- IPROC_CLK_PLLARMA_PDIV_SHIFT
- IPROC_CLK_PLLARMB_NDIV_FRAC_MASK
- IPROC_CLK_PLLARMB_OFFSET
- IPROC_CLK_PLLARMCTL5_H_MDIV_MASK
- IPROC_CLK_PLLARMCTL5_OFFSET
- IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT
- IPROC_CLK_PLLARMC_MDIV_MASK
- IPROC_CLK_PLLARMC_OFFSET
- IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK
- IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK
- IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT
- IPROC_CLK_PLLARM_OFFSET_OFFSET
- IPROC_CLK_PLLARM_SW_CTL_SHIFT
- IPROC_CLK_PLL_ASIU
- IPROC_CLK_PLL_CALC_PARAM
- IPROC_CLK_PLL_HAS_NDIV_FRAC
- IPROC_CLK_PLL_NEEDS_SW_CFG
- IPROC_CLK_PLL_RESET_ACTIVE_LOW
- IPROC_CLK_PLL_SPLIT_STAT_CTRL
- IPROC_CLK_PLL_USER_MODE_ON
- IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK
- IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT
- IPROC_CLK_POLICY_DBG_OFFSET
- IPROC_CLK_POLICY_FREQ_OFFSET
- IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK
- IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT
- IPROC_CONTROLLER_STATUS
- IPROC_GPHY_MDCDIV
- IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET
- IPROC_GPIO_DATA_IN_OFFSET
- IPROC_GPIO_DATA_OUT_OFFSET
- IPROC_GPIO_DRV_CTRL_OFFSET
- IPROC_GPIO_INT_CLR_OFFSET
- IPROC_GPIO_INT_DE_OFFSET
- IPROC_GPIO_INT_EDGE_OFFSET
- IPROC_GPIO_INT_MSK_OFFSET
- IPROC_GPIO_INT_MSTAT_OFFSET
- IPROC_GPIO_INT_STAT_OFFSET
- IPROC_GPIO_INT_TYPE_OFFSET
- IPROC_GPIO_OUT_EN_OFFSET
- IPROC_GPIO_PAD_RES_OFFSET
- IPROC_GPIO_PULL_DN_OFFSET
- IPROC_GPIO_PULL_UP_OFFSET
- IPROC_GPIO_REG
- IPROC_GPIO_RES_EN_OFFSET
- IPROC_GPIO_SHIFT
- IPROC_I2C
- IPROC_I2C_NIC
- IPROC_INTERRUPT_MASK
- IPROC_INTERRUPT_STATUS
- IPROC_INTERRUPT_THRES
- IPROC_MSI_CTRL
- IPROC_MSI_EQ_EN
- IPROC_MSI_EQ_EN_SHIFT
- IPROC_MSI_EQ_HEAD
- IPROC_MSI_EQ_MASK
- IPROC_MSI_EQ_PAGE
- IPROC_MSI_EQ_PAGE_UPPER
- IPROC_MSI_EQ_TAIL
- IPROC_MSI_INTR_EN
- IPROC_MSI_INTR_EN_SHIFT
- IPROC_MSI_INTS_EN
- IPROC_MSI_INT_N_EVENT
- IPROC_MSI_INT_N_EVENT_SHIFT
- IPROC_MSI_PAGE
- IPROC_MSI_PAGE_UPPER
- IPROC_MSI_REG_SIZE
- IPROC_NAND_APB_LE_MODE
- IPROC_NAND_CTLR_READY
- IPROC_NAND_CTLR_READY_OFFSET
- IPROC_NAND_INT_CTRL_READ_ENABLE
- IPROC_NAND_IO_CTRL_OFFSET
- IPROC_PCIE_APB_ERR_EN
- IPROC_PCIE_CFG_ADDR
- IPROC_PCIE_CFG_DATA
- IPROC_PCIE_CFG_IND_ADDR
- IPROC_PCIE_CFG_IND_DATA
- IPROC_PCIE_CFG_RD_STATUS
- IPROC_PCIE_CLK_CTRL
- IPROC_PCIE_IARR0
- IPROC_PCIE_IARR1
- IPROC_PCIE_IARR2
- IPROC_PCIE_IARR3
- IPROC_PCIE_IARR4
- IPROC_PCIE_IB_MAP_INVALID
- IPROC_PCIE_IB_MAP_IO
- IPROC_PCIE_IB_MAP_MEM
- IPROC_PCIE_IMAP0
- IPROC_PCIE_IMAP1
- IPROC_PCIE_IMAP2
- IPROC_PCIE_IMAP3
- IPROC_PCIE_IMAP4
- IPROC_PCIE_INTX_EN
- IPROC_PCIE_LINK_STATUS
- IPROC_PCIE_MAX_NUM_REG
- IPROC_PCIE_MSI_ADDR_HI
- IPROC_PCIE_MSI_ADDR_LO
- IPROC_PCIE_MSI_BASE_ADDR
- IPROC_PCIE_MSI_EN_CFG
- IPROC_PCIE_MSI_GIC_MODE
- IPROC_PCIE_MSI_WINDOW_SIZE
- IPROC_PCIE_OARR0
- IPROC_PCIE_OARR1
- IPROC_PCIE_OARR2
- IPROC_PCIE_OARR3
- IPROC_PCIE_OMAP0
- IPROC_PCIE_OMAP1
- IPROC_PCIE_OMAP2
- IPROC_PCIE_OMAP3
- IPROC_PCIE_PAXB
- IPROC_PCIE_PAXB_BCMA
- IPROC_PCIE_PAXB_V2
- IPROC_PCIE_PAXC
- IPROC_PCIE_PAXC_V2
- IPROC_PCIE_REG_INVALID
- IPROC_PCI_EXP_CAP
- IPROC_PCI_PM_CAP
- IPROC_PCI_PM_CAP_MASK
- IPROC_PINCONF_BIAS_DISABLE
- IPROC_PINCONF_BIAS_PULL_DOWN
- IPROC_PINCONF_BIAS_PULL_UP
- IPROC_PINCONF_DRIVE_STRENGTH
- IPROC_PINCON_MAX
- IPROC_PWM_CTRL_EN_SHIFT
- IPROC_PWM_CTRL_OFFSET
- IPROC_PWM_CTRL_POLARITY_SHIFT
- IPROC_PWM_CTRL_TYPE_SHIFT
- IPROC_PWM_DUTY_CYCLE_MAX
- IPROC_PWM_DUTY_CYCLE_MIN
- IPROC_PWM_DUTY_CYCLE_OFFSET
- IPROC_PWM_PERIOD_MAX
- IPROC_PWM_PERIOD_MIN
- IPROC_PWM_PERIOD_OFFSET
- IPROC_PWM_PRESCALE_BITS
- IPROC_PWM_PRESCALE_MASK
- IPROC_PWM_PRESCALE_MAX
- IPROC_PWM_PRESCALE_MIN
- IPROC_PWM_PRESCALE_OFFSET
- IPROC_PWM_PRESCALE_SHIFT
- IPROC_REGCTL1
- IPROC_REGCTL2
- IPROC_SOFT_BYPASS_CONTROL
- IPROC_SOFT_BYPASS_DATA
- IPROC_TS_NAME
- IPRTE_ADDRSHFT
- IPRXDATAGRPPERR_F
- IPRXDATAGRPPERR_S
- IPRXDATAGRPPERR_V
- IPRXHDRGRPPERR_F
- IPRXHDRGRPPERR_S
- IPRXHDRGRPPERR_V
- IPR_80MBs_SCSI_RATE
- IPR_ABBREV_SHUTDOWN_TIMEOUT
- IPR_ABORT_TASK_TIMEOUT
- IPR_ADCBUFFULL
- IPR_ADCBUFHALFFULL
- IPR_ADDITIONAL_STATUS_FMT
- IPR_ADDR
- IPR_AI
- IPR_ARRAY_VIRTUAL_BUS
- IPR_ATA_DEVICE_WAS_RESET
- IPR_ATA_FLAG_PACKET_CMD
- IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION
- IPR_ATA_FLAG_XFER_TYPE_DMA
- IPR_ATA_PHY_RESET
- IPR_AUTOSENSE_VALID
- IPR_A_MIDIRECVBUFEMPTY2
- IPR_A_MIDITRANSBUFEMPTY2
- IPR_BUS_RESET
- IPR_CANCEL_64BIT_IOARCB
- IPR_CANCEL_ALL_REQUESTS
- IPR_CANCEL_ALL_TIMEOUT
- IPR_CANCEL_REQUEST
- IPR_CANCEL_TIMEOUT
- IPR_CAP_0_HALF_LOOP
- IPR_CAP_0_LOOP
- IPR_CAP_DUAL_IOA_RAID
- IPR_CAP_SYNC_CACHE
- IPR_CDROMSTATUSCHANGE
- IPR_CFG_TBL_START
- IPR_CHANNELLOOP
- IPR_CHANNELNUMBERMASK
- IPR_CHECK_FOR_RESET_TIMEOUT
- IPR_CH_0_HALF_LOOP
- IPR_CH_0_LOOP
- IPR_CMD_LABEL
- IPR_DBG_CMD
- IPR_DEBUG_LOG_LEVEL
- IPR_DEFAULT_BUS_WIDTH
- IPR_DEFAULT_LOG_LEVEL
- IPR_DEFAULT_MAX_ERROR_DUMP
- IPR_DEFAULT_SIS64_DEVS
- IPR_DESCRIPTOR_MASK
- IPR_DESCRIPTOR_SIS64
- IPR_DEVICE_RESET_TIMEOUT
- IPR_DOORBELL
- IPR_DRIVER_DATE
- IPR_DRIVER_ILID
- IPR_DRIVER_VERSION
- IPR_DUAL_IOA_ABBR_SHUTDOWN_TO
- IPR_DUMP_DATA_TYPE_ASCII
- IPR_DUMP_DATA_TYPE_BINARY
- IPR_DUMP_DELAY_SECONDS
- IPR_DUMP_DELAY_TIMEOUT
- IPR_DUMP_DRIVER_NAME
- IPR_DUMP_DRIVER_TYPE_ID
- IPR_DUMP_DRIVER_VERSION_ID
- IPR_DUMP_EYE_CATCHER
- IPR_DUMP_IOA_CTRL_BLK
- IPR_DUMP_IOA_DUMP_ID
- IPR_DUMP_LOCATION_ID
- IPR_DUMP_OS_LINUX
- IPR_DUMP_PEND_OPS
- IPR_DUMP_STATUS_FAILED
- IPR_DUMP_STATUS_QUAL_SUCCESS
- IPR_DUMP_STATUS_SUCCESS
- IPR_DUMP_TRACE_ID
- IPR_EFXBUFFULL
- IPR_EFXBUFHALFFULL
- IPR_EMIQ
- IPR_ENABLE_DUAL_IOA_AF
- IPR_ENDIAN_SWAP_KEY
- IPR_EXTENDED_RESET_DELAY
- IPR_EYECATCHER
- IPR_FIELD_POINTER_MASK
- IPR_FIELD_POINTER_VALID
- IPR_FIRST_DRIVER_IOASC
- IPR_FLAGS_HI_NO_LINK_DESC
- IPR_FLAGS_HI_NO_ULEN_CHK
- IPR_FLAGS_HI_SYNC_COMPLETE
- IPR_FLAGS_HI_SYNC_OVERRIDE
- IPR_FLAGS_HI_WRITE_NOT_READ
- IPR_FLAGS_LO_ACA_TASK
- IPR_FLAGS_LO_ALIGNED_BFR
- IPR_FLAGS_LO_DELAY_AFTER_RST
- IPR_FLAGS_LO_HEAD_OF_Q_TASK
- IPR_FLAGS_LO_ORDERED_TASK
- IPR_FLAGS_LO_SIMPLE_TASK
- IPR_FLAGS_LO_UNTAGGED_TASK
- IPR_FMT2_MAX_IOA_DUMP_SIZE
- IPR_FMT2_MAX_NUM_DUMP_PAGES
- IPR_FMT2_MBX_ADDR_MASK
- IPR_FMT2_MBX_BAR_SEL_MASK
- IPR_FMT2_MKR_BAR_SEL_SHIFT
- IPR_FMT2_NUM_SDT_ENTRIES
- IPR_FMT2_SDT_READY_TO_USE
- IPR_FMT3_MAX_IOA_DUMP_SIZE
- IPR_FMT3_MAX_NUM_DUMP_PAGES
- IPR_FMT3_NUM_SDT_ENTRIES
- IPR_FMT3_SDT_READY_TO_USE
- IPR_FORCEINT
- IPR_FXDSP
- IPR_GET_FMT2_BAR_SEL
- IPR_GET_MODE_PAGE_CODE
- IPR_GET_PHYS_LOC
- IPR_GET_RES_PHYS_LOC
- IPR_GPI
- IPR_GPIOMSG
- IPR_GPSPDIFSTATUSCHANGE
- IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE
- IPR_HCAM_CDB_OP_CODE_LOG_DATA
- IPR_HCAM_LABEL
- IPR_HOSTRCB_ERR_RESP_SENT
- IPR_HOSTRCB_INTERNAL_OPER
- IPR_HOST_CONTROLLED_ASYNC
- IPR_HOST_RCB_NOTIFICATIONS_LOST
- IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY
- IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED
- IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY
- IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY
- IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY
- IPR_HOST_RCB_NO_NOTIFICATIONS_LOST
- IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE
- IPR_HOST_RCB_OP_CODE_LOG_DATA
- IPR_HOST_RCB_OVERLAY_ID_1
- IPR_HOST_RCB_OVERLAY_ID_12
- IPR_HOST_RCB_OVERLAY_ID_13
- IPR_HOST_RCB_OVERLAY_ID_14
- IPR_HOST_RCB_OVERLAY_ID_16
- IPR_HOST_RCB_OVERLAY_ID_17
- IPR_HOST_RCB_OVERLAY_ID_2
- IPR_HOST_RCB_OVERLAY_ID_20
- IPR_HOST_RCB_OVERLAY_ID_21
- IPR_HOST_RCB_OVERLAY_ID_23
- IPR_HOST_RCB_OVERLAY_ID_24
- IPR_HOST_RCB_OVERLAY_ID_26
- IPR_HOST_RCB_OVERLAY_ID_3
- IPR_HOST_RCB_OVERLAY_ID_30
- IPR_HOST_RCB_OVERLAY_ID_4
- IPR_HOST_RCB_OVERLAY_ID_41
- IPR_HOST_RCB_OVERLAY_ID_6
- IPR_HOST_RCB_OVERLAY_ID_7
- IPR_HOST_RCB_OVERLAY_ID_DEFAULT
- IPR_HRRQ_REQ_RESP_HANDLE_MASK
- IPR_HRRQ_REQ_RESP_HANDLE_SHIFT
- IPR_HRRQ_RESP_BIT_SET
- IPR_HRRQ_TOGGLE_BIT
- IPR_I2C_DAC
- IPR_I2C_EEPROM
- IPR_ID_HOST_RR_Q
- IPR_ID_HRRQ_SELE_ENABLE
- IPR_INIT_HRRQ
- IPR_INQUIRY_PAGE0_ENTRIES
- IPR_INT0
- IPR_INT1
- IPR_INT2
- IPR_INT3
- IPR_INT4
- IPR_INT5
- IPR_INT6
- IPR_INT7
- IPR_INTERNAL_TIMEOUT
- IPR_INTERVALTIMER
- IPR_INVALID_ARRAY_DEV_NUM
- IPR_INVALID_RES_HANDLE
- IPR_IOADL_DATA_LEN_MASK
- IPR_IOADL_FLAGS_LAST
- IPR_IOADL_FLAGS_MASK
- IPR_IOADL_FLAGS_READ
- IPR_IOADL_FLAGS_READ_LAST
- IPR_IOADL_FLAGS_WRITE
- IPR_IOADL_FLAGS_WRITE_LAST
- IPR_IOADL_GET_DATA_LEN
- IPR_IOADL_GET_FLAGS
- IPR_IOAFP_VIRTUAL_BUS
- IPR_IOASA_IR_DUAL_IOA_DISABLED
- IPR_IOASC_ABORTED_CMD_TERM_BY_HOST
- IPR_IOASC_BUS_WAS_RESET
- IPR_IOASC_BUS_WAS_RESET_BY_OTHER
- IPR_IOASC_HW_CMD_FAILED
- IPR_IOASC_HW_DEV_BUS_STATUS
- IPR_IOASC_HW_SEL_TIMEOUT
- IPR_IOASC_IOASC_MASK
- IPR_IOASC_IOA_WAS_RESET
- IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT
- IPR_IOASC_IR_NON_OPTIMIZED
- IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA
- IPR_IOASC_IR_RESOURCE_HANDLE
- IPR_IOASC_MED_DO_NOT_REALLOC
- IPR_IOASC_NR_INIT_CMD_REQUIRED
- IPR_IOASC_NR_IOA_RESET_REQUIRED
- IPR_IOASC_PCI_ACCESS_ERROR
- IPR_IOASC_SCSI_STATUS_MASK
- IPR_IOASC_SENSE_CODE
- IPR_IOASC_SENSE_KEY
- IPR_IOASC_SENSE_QUAL
- IPR_IOASC_SENSE_STATUS
- IPR_IOASC_SPECIFIC_MASK
- IPR_IOASC_SYNC_REQUIRED
- IPR_IOA_BUS
- IPR_IOA_LUN
- IPR_IOA_MAX_SECTORS
- IPR_IOA_RES_ADDR
- IPR_IOA_RES_HANDLE
- IPR_IOA_SA_CHANGE_CACHE_PARAMS
- IPR_IOA_SERVICE_ACTION
- IPR_IOA_SHUTDOWN
- IPR_IOA_TARGET
- IPR_IPL_INIT_DEFAULT_STAGE_TIME
- IPR_IPL_INIT_MIN_STAGE_TIME
- IPR_IPL_INIT_STAGE_MASK
- IPR_IPL_INIT_STAGE_TIME_MASK
- IPR_IPL_INIT_STAGE_TRANSOP
- IPR_IPL_INIT_STAGE_UNKNOWN
- IPR_IRQ1
- IPR_IRQ2
- IPR_IRQ3
- IPR_IRQ5
- IPR_IRQ6
- IPR_IRQ7
- IPR_IS_DASD_DEVICE
- IPR_IS_IOA_RESOURCE
- IPR_IS_SES_DEVICE
- IPR_KB
- IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC
- IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC
- IPR_LONG_OPERATIONAL_TIMEOUT
- IPR_LUN_RESET
- IPR_MAX_CDB_LEN
- IPR_MAX_CMD_PER_ATA_LUN
- IPR_MAX_CMD_PER_LUN
- IPR_MAX_COMMANDS
- IPR_MAX_HCAMS
- IPR_MAX_HRRQ_NUM
- IPR_MAX_HRRQ_RETRIES
- IPR_MAX_LOG_LEVEL
- IPR_MAX_MSIX_VECTORS
- IPR_MAX_NUM_BUSES
- IPR_MAX_NUM_LUNS_PER_TARGET
- IPR_MAX_NUM_TARGETS_PER_BUS
- IPR_MAX_PHYSICAL_DEVS
- IPR_MAX_RES_PATH_LENGTH
- IPR_MAX_SCSI_RATE
- IPR_MAX_SGLIST
- IPR_MAX_SIS64_BUSES
- IPR_MAX_SIS64_DEVS
- IPR_MAX_SIS64_LUNS_PER_TARGET
- IPR_MAX_SIS64_TARGETS_PER_BUS
- IPR_MICBUFFULL
- IPR_MICBUFHALFFULL
- IPR_MIDIRECVBUFEMPTY
- IPR_MIDITRANSBUFEMPTY
- IPR_MIDI_RX_A
- IPR_MIDI_RX_B
- IPR_MIDI_TX_A
- IPR_MIDI_TX_B
- IPR_MMIO
- IPR_MODE_PAGE_PS
- IPR_MUTE
- IPR_NAME
- IPR_NO_ILID
- IPR_NUM_BASE_CMD_BLKS
- IPR_NUM_CFG_CHG_HCAMS
- IPR_NUM_CMD_BLKS
- IPR_NUM_HCAMS
- IPR_NUM_HCAM_QUEUE
- IPR_NUM_INTERNAL_CMD_BLKS
- IPR_NUM_IOADL_ENTRIES
- IPR_NUM_LOG_HCAMS
- IPR_NUM_RESET_RELOAD_RETRIES
- IPR_NUM_TRACE_ENTRIES
- IPR_NUM_TRACE_INDEX_BITS
- IPR_OPERATIONAL_TIMEOUT
- IPR_P16V
- IPR_PATH_ACTIVE
- IPR_PATH_ACTIVE_MASK
- IPR_PATH_CFG_DEGRADED
- IPR_PATH_CFG_DEVICE_LUN
- IPR_PATH_CFG_DEVICE_PORT
- IPR_PATH_CFG_EXP_PORT
- IPR_PATH_CFG_FAILED
- IPR_PATH_CFG_IOA_PORT
- IPR_PATH_CFG_NOT_EXIST
- IPR_PATH_CFG_NO_PROB
- IPR_PATH_CFG_STATUS_MASK
- IPR_PATH_CFG_SUSPECT
- IPR_PATH_CFG_TYPE_MASK
- IPR_PATH_DEGRADED
- IPR_PATH_FAILED
- IPR_PATH_HEALTHY
- IPR_PATH_INCORRECT_CONN
- IPR_PATH_NOT_ACTIVE
- IPR_PATH_NOT_DETECTED
- IPR_PATH_NO_INFO
- IPR_PATH_STATE_MASK
- IPR_PATH_STATE_NO_INFO
- IPR_PCI
- IPR_PCIERROR
- IPR_PCII_CORE_ISSUED_RST_REQ
- IPR_PCII_CRITICAL_OPERATION
- IPR_PCII_ERROR_INTERRUPTS
- IPR_PCII_HRRQ_UPDATED
- IPR_PCII_IOARCB_XFER_FAILED
- IPR_PCII_IOARRIN_LOST
- IPR_PCII_IOA_TRANS_TO_OPER
- IPR_PCII_IOA_UNIT_CHECKED
- IPR_PCII_IO_DEBUG_ACKNOWLEDGE
- IPR_PCII_IPL_STAGE_CHANGE
- IPR_PCII_MAILBOX_STABLE
- IPR_PCII_MMIO_ERROR
- IPR_PCII_NO_HOST_RRQ
- IPR_PCII_OPER_INTERRUPTS
- IPR_PCII_PROC_ERR_STATE
- IPR_PCI_CFG
- IPR_PCI_ERROR_RECOVERY_TIMEOUT
- IPR_PCI_RESET_TIMEOUT
- IPR_PEN
- IPR_PHY_LINK_RATE_MASK
- IPR_PROD_ID_LEN
- IPR_PROTO_SAS_STP
- IPR_PROTO_SAS_STP_ATAPI
- IPR_PROTO_SATA
- IPR_PROTO_SATA_ATAPI
- IPR_PWM
- IPR_QUERY_IOA_CONFIG
- IPR_QUERY_RSRC_STATE
- IPR_QUEUEING_MODEL
- IPR_QUEUEING_MODEL64
- IPR_QUEUE_FROZEN_MODEL
- IPR_QUEUE_NACA_MODEL
- IPR_RC_JOB_CONTINUE
- IPR_RC_JOB_RETURN
- IPR_REQUEST_SENSE_TIMEOUT
- IPR_RESET_DEVICE
- IPR_RESET_TYPE_SELECT
- IPR_RES_TABLE_LABEL
- IPR_RES_TYPE_AF_DASD
- IPR_RES_TYPE_ARRAY
- IPR_RES_TYPE_GENERIC_ATA
- IPR_RES_TYPE_GENERIC_SCSI
- IPR_RES_TYPE_IOAFP
- IPR_RES_TYPE_REMOTE_AF_DASD
- IPR_RES_TYPE_VOLUME_SET
- IPR_RQTYPE_ATA_PASSTHRU
- IPR_RQTYPE_HCAM
- IPR_RQTYPE_IOACMD
- IPR_RQTYPE_PIPE
- IPR_RQTYPE_SCSICDB
- IPR_RTC
- IPR_RUNTIME_RESET
- IPR_SAM
- IPR_SAMPLERATETRACKER
- IPR_SCSI_ATTR_DISABLE_QAS
- IPR_SCSI_ATTR_ENABLE_QAS
- IPR_SCSI_ATTR_ENABLE_TM
- IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED
- IPR_SCSI_ATTR_NO_TERM_PWR
- IPR_SCSI_ATTR_QAS_MASK
- IPR_SCSI_ATTR_TM_SUPPORTED
- IPR_SDT_ENDIAN
- IPR_SDT_FMT2_BAR0_SEL
- IPR_SDT_FMT2_BAR1_SEL
- IPR_SDT_FMT2_BAR2_SEL
- IPR_SDT_FMT2_BAR3_SEL
- IPR_SDT_FMT2_BAR4_SEL
- IPR_SDT_FMT2_BAR5_SEL
- IPR_SDT_FMT2_EXP_ROM_SEL
- IPR_SDT_VALID_ENTRY
- IPR_SERIAL_NUM_LEN
- IPR_SET_ALL_SUPPORTED_DEVICES
- IPR_SET_SUPPORTED_DEVICES
- IPR_SET_SUP_DEVICE_TIMEOUT
- IPR_SHUTDOWN_ABBREV
- IPR_SHUTDOWN_NONE
- IPR_SHUTDOWN_NORMAL
- IPR_SHUTDOWN_PREPARE_FOR_NORMAL
- IPR_SHUTDOWN_QUIESCE
- IPR_SHUTDOWN_TIMEOUT
- IPR_SIS32
- IPR_SIS32_DUMP_TIMEOUT
- IPR_SIS64
- IPR_SIS64_DUMP_TIMEOUT
- IPR_SPDIFBUFFULL
- IPR_SPDIFBUFHALFFULL
- IPR_SPDIF_IN_USER
- IPR_SPDIF_OUT_FRAME
- IPR_SPDIF_OUT_USER
- IPR_SPDIF_STATUS
- IPR_SPI
- IPR_SPIM
- IPR_SPIS
- IPR_SRC_LOCKED
- IPR_STD_INQ_PERI_DEV_TYPE
- IPR_STD_INQ_PERI_QUAL
- IPR_STD_INQ_REMOVEABLE_MEDIUM
- IPR_SUBS_DEV_ID_2780
- IPR_SUBS_DEV_ID_2CCA
- IPR_SUBS_DEV_ID_2CCD
- IPR_SUBS_DEV_ID_2CD2
- IPR_SUBS_DEV_ID_5702
- IPR_SUBS_DEV_ID_5703
- IPR_SUBS_DEV_ID_571A
- IPR_SUBS_DEV_ID_571B
- IPR_SUBS_DEV_ID_571E
- IPR_SUBS_DEV_ID_571F
- IPR_SUBS_DEV_ID_572A
- IPR_SUBS_DEV_ID_572B
- IPR_SUBS_DEV_ID_572E
- IPR_SUBS_DEV_ID_572F
- IPR_SUBS_DEV_ID_573D
- IPR_SUBS_DEV_ID_573E
- IPR_SUBS_DEV_ID_574D
- IPR_SUBS_DEV_ID_574E
- IPR_SUBS_DEV_ID_575B
- IPR_SUBS_DEV_ID_575C
- IPR_SUBS_DEV_ID_57B1
- IPR_SUBS_DEV_ID_57B2
- IPR_SUBS_DEV_ID_57B3
- IPR_SUBS_DEV_ID_57B4
- IPR_SUBS_DEV_ID_57B5
- IPR_SUBS_DEV_ID_57B7
- IPR_SUBS_DEV_ID_57B8
- IPR_SUBS_DEV_ID_57C0
- IPR_SUBS_DEV_ID_57C3
- IPR_SUBS_DEV_ID_57C4
- IPR_SUBS_DEV_ID_57C6
- IPR_SUBS_DEV_ID_57C8
- IPR_SUBS_DEV_ID_57CC
- IPR_SUBS_DEV_ID_57CE
- IPR_SUBS_DEV_ID_57D5
- IPR_SUBS_DEV_ID_57D6
- IPR_SUBS_DEV_ID_57D7
- IPR_SUBS_DEV_ID_57D8
- IPR_SUBS_DEV_ID_57D9
- IPR_SUBS_DEV_ID_57DA
- IPR_SUBS_DEV_ID_57EB
- IPR_SUBS_DEV_ID_57EC
- IPR_SUBS_DEV_ID_57ED
- IPR_SUBS_DEV_ID_57EE
- IPR_SUBS_DEV_ID_57EF
- IPR_SUBS_DEV_ID_57F0
- IPR_SUBS_DEV_ID_580A
- IPR_SUBS_DEV_ID_580B
- IPR_TARGET_RESET
- IPR_TIMER1
- IPR_TIMER2
- IPR_TMR
- IPR_TMR1
- IPR_TMR2
- IPR_TRACE_FINISH
- IPR_TRACE_INDEX_MASK
- IPR_TRACE_SIZE
- IPR_TRACE_START
- IPR_TRACE_START_LABEL
- IPR_U160_SCSI_RATE
- IPR_U320_SCSI_RATE
- IPR_UART
- IPR_UCODE_DOWNLOAD_REQ
- IPR_UPROCI_IO_DEBUG_ALERT
- IPR_UPROCI_RESET_ALERT
- IPR_UPROCI_SIS64_START_BIST
- IPR_USE_LONG_TRANSOP_TIMEOUT
- IPR_USE_PCI_WARM_RESET
- IPR_VALID
- IPR_VENDOR_ID_LEN
- IPR_VOLDECR
- IPR_VOLINCR
- IPR_VSET_BUS
- IPR_VSET_MAX_SECTORS
- IPR_VSET_RW_TIMEOUT
- IPR_VSET_VIRTUAL_BUS
- IPR_WAIT_FOR_BIST_TIMEOUT
- IPR_WAIT_FOR_MAILBOX
- IPR_WAIT_FOR_RESET_TIMEOUT
- IPR_WDT
- IPR_WRITE_BUFFER_TIMEOUT
- IPR_WR_BUF_DOWNLOAD_AND_SAVE
- IPSEC
- IPSEC_CONFIG_PRESENT
- IPSEC_DIR_ANY
- IPSEC_DIR_FWD
- IPSEC_DIR_INBOUND
- IPSEC_DIR_INVALID
- IPSEC_DIR_MAX
- IPSEC_DIR_OUTBOUND
- IPSEC_ENCAP_DECO_DPOVRD_USE
- IPSEC_LEVEL_DEFAULT
- IPSEC_LEVEL_REQUIRE
- IPSEC_LEVEL_UNIQUE
- IPSEC_LEVEL_USE
- IPSEC_MANUAL_REQID_MAX
- IPSEC_MODE_ANY
- IPSEC_MODE_BEET
- IPSEC_MODE_TRANSPORT
- IPSEC_MODE_TUNNEL
- IPSEC_PKTINFO
- IPSEC_POLICY_BYPASS
- IPSEC_POLICY_DISCARD
- IPSEC_POLICY_ENTRUST
- IPSEC_POLICY_IPSEC
- IPSEC_POLICY_NONE
- IPSEC_PORT_ANY
- IPSEC_PROTO_ANY
- IPSEC_REPLAYWSIZE
- IPSEC_TRUNCATED_ICV_SIZE
- IPSEC_ULPROTO_ANY
- IPSEL
- IPSET_ADD
- IPSET_ADD_FAILED
- IPSET_ADD_START_STORED_TIMEOUT
- IPSET_ADD_STORE_PLAIN_TIMEOUT
- IPSET_ADT_MAX
- IPSET_ATTR_ADT
- IPSET_ATTR_ADT_MAX
- IPSET_ATTR_BYTES
- IPSET_ATTR_CADT_FLAGS
- IPSET_ATTR_CADT_LINENO
- IPSET_ATTR_CADT_MAX
- IPSET_ATTR_CIDR
- IPSET_ATTR_CIDR2
- IPSET_ATTR_CMD_MAX
- IPSET_ATTR_COMMENT
- IPSET_ATTR_CREATE_MAX
- IPSET_ATTR_DATA
- IPSET_ATTR_ELEMENTS
- IPSET_ATTR_ETHER
- IPSET_ATTR_FAMILY
- IPSET_ATTR_FLAGS
- IPSET_ATTR_GC
- IPSET_ATTR_HASHSIZE
- IPSET_ATTR_IFACE
- IPSET_ATTR_INDEX
- IPSET_ATTR_IP
- IPSET_ATTR_IP2
- IPSET_ATTR_IP2_TO
- IPSET_ATTR_IPADDR_IPV4
- IPSET_ATTR_IPADDR_IPV6
- IPSET_ATTR_IPADDR_MAX
- IPSET_ATTR_IP_FROM
- IPSET_ATTR_IP_TO
- IPSET_ATTR_LINENO
- IPSET_ATTR_MARK
- IPSET_ATTR_MARKMASK
- IPSET_ATTR_MAXELEM
- IPSET_ATTR_MEMSIZE
- IPSET_ATTR_NAME
- IPSET_ATTR_NAMEREF
- IPSET_ATTR_NETMASK
- IPSET_ATTR_PACKETS
- IPSET_ATTR_PAD
- IPSET_ATTR_PORT
- IPSET_ATTR_PORT_FROM
- IPSET_ATTR_PORT_TO
- IPSET_ATTR_PROBES
- IPSET_ATTR_PROTO
- IPSET_ATTR_PROTOCOL
- IPSET_ATTR_PROTOCOL_MIN
- IPSET_ATTR_REFERENCES
- IPSET_ATTR_RESIZE
- IPSET_ATTR_REVISION
- IPSET_ATTR_REVISION_MIN
- IPSET_ATTR_SETNAME
- IPSET_ATTR_SETNAME2
- IPSET_ATTR_SIZE
- IPSET_ATTR_SKBMARK
- IPSET_ATTR_SKBPRIO
- IPSET_ATTR_SKBQUEUE
- IPSET_ATTR_TIMEOUT
- IPSET_ATTR_TYPENAME
- IPSET_ATTR_UNSPEC
- IPSET_BITMAP_MAX_RANGE
- IPSET_BIT_RETURN_NOMATCH
- IPSET_CADT_MAX
- IPSET_CB_ARG0
- IPSET_CB_DUMP
- IPSET_CB_INDEX
- IPSET_CB_NET
- IPSET_CB_PRIVATE
- IPSET_CB_PROTO
- IPSET_CMD_ADD
- IPSET_CMD_COMMIT
- IPSET_CMD_CREATE
- IPSET_CMD_DEL
- IPSET_CMD_DESTROY
- IPSET_CMD_FLUSH
- IPSET_CMD_GET_BYINDEX
- IPSET_CMD_GET_BYNAME
- IPSET_CMD_HEADER
- IPSET_CMD_HELP
- IPSET_CMD_LIST
- IPSET_CMD_MAX
- IPSET_CMD_NONE
- IPSET_CMD_PROTOCOL
- IPSET_CMD_QUIT
- IPSET_CMD_RENAME
- IPSET_CMD_RESTORE
- IPSET_CMD_SAVE
- IPSET_CMD_SWAP
- IPSET_CMD_TEST
- IPSET_CMD_TYPE
- IPSET_CMD_VERSION
- IPSET_CONCAT
- IPSET_COUNTER_EQ
- IPSET_COUNTER_GT
- IPSET_COUNTER_LT
- IPSET_COUNTER_NE
- IPSET_COUNTER_NONE
- IPSET_CREATE
- IPSET_CREATE_FLAG_BIT_FORCEADD
- IPSET_CREATE_FLAG_BIT_MAX
- IPSET_CREATE_FLAG_FORCEADD
- IPSET_DEFAULT_HASHSIZE
- IPSET_DEFAULT_MAXELEM
- IPSET_DEFAULT_PROBES
- IPSET_DEFAULT_RESIZE
- IPSET_DEL
- IPSET_DIM_MAX
- IPSET_DIM_ONE
- IPSET_DIM_ONE_SRC
- IPSET_DIM_THREE
- IPSET_DIM_THREE_SRC
- IPSET_DIM_TWO
- IPSET_DIM_TWO_SRC
- IPSET_DIM_ZERO
- IPSET_DST
- IPSET_DUMP_LAST
- IPSET_DUMP_LAST_FLAG
- IPSET_ELEM_PERMANENT
- IPSET_ERR_BEFORE
- IPSET_ERR_BITMAP_RANGE
- IPSET_ERR_BITMAP_RANGE_SIZE
- IPSET_ERR_BUSY
- IPSET_ERR_COMMENT
- IPSET_ERR_COUNTER
- IPSET_ERR_EXIST
- IPSET_ERR_EXIST_SETNAME2
- IPSET_ERR_FIND_TYPE
- IPSET_ERR_HASH_ELEM
- IPSET_ERR_HASH_FULL
- IPSET_ERR_HASH_RANGE
- IPSET_ERR_HASH_RANGE_UNSUPPORTED
- IPSET_ERR_INVALID_CIDR
- IPSET_ERR_INVALID_FAMILY
- IPSET_ERR_INVALID_MARKMASK
- IPSET_ERR_INVALID_NETMASK
- IPSET_ERR_INVALID_PROTO
- IPSET_ERR_IPADDR_IPV4
- IPSET_ERR_IPADDR_IPV6
- IPSET_ERR_LIST_FULL
- IPSET_ERR_LOOP
- IPSET_ERR_MAX_SETS
- IPSET_ERR_MISSING_PROTO
- IPSET_ERR_NAME
- IPSET_ERR_NAMEREF
- IPSET_ERR_PRIVATE
- IPSET_ERR_PROTOCOL
- IPSET_ERR_REFERENCED
- IPSET_ERR_REF_EXIST
- IPSET_ERR_SKBINFO
- IPSET_ERR_TIMEOUT
- IPSET_ERR_TYPE_MISMATCH
- IPSET_ERR_TYPE_SPECIFIC
- IPSET_EXT_BIT_COMMENT
- IPSET_EXT_BIT_COUNTER
- IPSET_EXT_BIT_DESTROY
- IPSET_EXT_BIT_SKBINFO
- IPSET_EXT_BIT_TIMEOUT
- IPSET_EXT_COMMENT
- IPSET_EXT_COUNTER
- IPSET_EXT_DESTROY
- IPSET_EXT_ID_COMMENT
- IPSET_EXT_ID_COUNTER
- IPSET_EXT_ID_MAX
- IPSET_EXT_ID_SKBINFO
- IPSET_EXT_ID_TIMEOUT
- IPSET_EXT_SKBINFO
- IPSET_EXT_TIMEOUT
- IPSET_FLAG_BEFORE
- IPSET_FLAG_BIT_BEFORE
- IPSET_FLAG_BIT_EXIST
- IPSET_FLAG_BIT_LIST_HEADER
- IPSET_FLAG_BIT_LIST_SETNAME
- IPSET_FLAG_BIT_MAP_SKBMARK
- IPSET_FLAG_BIT_MAP_SKBPRIO
- IPSET_FLAG_BIT_MAP_SKBQUEUE
- IPSET_FLAG_BIT_MATCH_COUNTERS
- IPSET_FLAG_BIT_NOMATCH
- IPSET_FLAG_BIT_PHYSDEV
- IPSET_FLAG_BIT_RETURN_NOMATCH
- IPSET_FLAG_BIT_SKIP_COUNTER_UPDATE
- IPSET_FLAG_BIT_SKIP_SUBCOUNTER_UPDATE
- IPSET_FLAG_BIT_WITH_COMMENT
- IPSET_FLAG_BIT_WITH_COUNTERS
- IPSET_FLAG_BIT_WITH_FORCEADD
- IPSET_FLAG_BIT_WITH_SKBINFO
- IPSET_FLAG_CADT_MAX
- IPSET_FLAG_CMD_MAX
- IPSET_FLAG_EXIST
- IPSET_FLAG_LIST_HEADER
- IPSET_FLAG_LIST_SETNAME
- IPSET_FLAG_MAP_SKBMARK
- IPSET_FLAG_MAP_SKBPRIO
- IPSET_FLAG_MAP_SKBQUEUE
- IPSET_FLAG_MATCH_COUNTERS
- IPSET_FLAG_NOMATCH
- IPSET_FLAG_PHYSDEV
- IPSET_FLAG_RETURN_NOMATCH
- IPSET_FLAG_SKIP_COUNTER_UPDATE
- IPSET_FLAG_SKIP_SUBCOUNTER_UPDATE
- IPSET_FLAG_WITH_COMMENT
- IPSET_FLAG_WITH_COUNTERS
- IPSET_FLAG_WITH_FORCEADD
- IPSET_FLAG_WITH_SKBINFO
- IPSET_GC_PERIOD
- IPSET_GC_TIME
- IPSET_INVALID_ID
- IPSET_INV_MATCH
- IPSET_MATCH_INV
- IPSET_MAXNAMELEN
- IPSET_MAX_COMMENT_SIZE
- IPSET_MAX_TIMEOUT
- IPSET_MIMINAL_HASHSIZE
- IPSET_MSG_MAX
- IPSET_NET_COUNT
- IPSET_NO_TIMEOUT
- IPSET_PROTOCOL
- IPSET_PROTOCOL_MIN
- IPSET_RETURN_NOMATCH
- IPSET_SRC
- IPSET_TEST
- IPSET_TOKEN
- IPSET_TYPE_IFACE
- IPSET_TYPE_IFACE_FLAG
- IPSET_TYPE_IP
- IPSET_TYPE_IP2
- IPSET_TYPE_IP2_FLAG
- IPSET_TYPE_IP_FLAG
- IPSET_TYPE_MAC
- IPSET_TYPE_MAC_FLAG
- IPSET_TYPE_MARK
- IPSET_TYPE_MARK_FLAG
- IPSET_TYPE_NAME
- IPSET_TYPE_NAME_FLAG
- IPSET_TYPE_NOMATCH
- IPSET_TYPE_NOMATCH_FLAG
- IPSET_TYPE_PORT
- IPSET_TYPE_PORT_FLAG
- IPSET_TYPE_REV_MAX
- IPSET_TYPE_REV_MIN
- IPSKB_DOREDIRECT
- IPSKB_FORWARDED
- IPSKB_FRAG_COMPLETE
- IPSKB_FRAG_PMTU
- IPSKB_L3SLAVE
- IPSKB_REROUTED
- IPSKB_XFRM_TRANSFORMED
- IPSKB_XFRM_TUNNEL_SIZE
- IPSOTPERR_F
- IPSOTPERR_S
- IPSOTPERR_V
- IPSPS_REG_FW_VERSION
- IPSPS_REG_HW_VERSION
- IPSPS_REG_MODE
- IPSPS_REG_MODEL
- IPSPS_REG_PN
- IPSPS_REG_SN
- IPSPS_REG_VENDOR_ID
- IPSRST2_OFFSET
- IPSRST3_OFFSET
- IPSR_MASK
- IPSTATS_MIB_CEPKTS
- IPSTATS_MIB_CSUMERRORS
- IPSTATS_MIB_ECT0PKTS
- IPSTATS_MIB_ECT1PKTS
- IPSTATS_MIB_FRAGCREATES
- IPSTATS_MIB_FRAGFAILS
- IPSTATS_MIB_FRAGOKS
- IPSTATS_MIB_INADDRERRORS
- IPSTATS_MIB_INBCASTOCTETS
- IPSTATS_MIB_INBCASTPKTS
- IPSTATS_MIB_INDELIVERS
- IPSTATS_MIB_INDISCARDS
- IPSTATS_MIB_INHDRERRORS
- IPSTATS_MIB_INMCASTOCTETS
- IPSTATS_MIB_INMCASTPKTS
- IPSTATS_MIB_INNOROUTES
- IPSTATS_MIB_INOCTETS
- IPSTATS_MIB_INPKTS
- IPSTATS_MIB_INTOOBIGERRORS
- IPSTATS_MIB_INTRUNCATEDPKTS
- IPSTATS_MIB_INUNKNOWNPROTOS
- IPSTATS_MIB_MAX
- IPSTATS_MIB_NOECTPKTS
- IPSTATS_MIB_NUM
- IPSTATS_MIB_OUTBCASTOCTETS
- IPSTATS_MIB_OUTBCASTPKTS
- IPSTATS_MIB_OUTDISCARDS
- IPSTATS_MIB_OUTFORWDATAGRAMS
- IPSTATS_MIB_OUTMCASTOCTETS
- IPSTATS_MIB_OUTMCASTPKTS
- IPSTATS_MIB_OUTNOROUTES
- IPSTATS_MIB_OUTOCTETS
- IPSTATS_MIB_OUTPKTS
- IPSTATS_MIB_REASMFAILS
- IPSTATS_MIB_REASMOKS
- IPSTATS_MIB_REASMREQDS
- IPSTATS_MIB_REASMTIMEOUT
- IPSTATS_MIB_REASM_OVERLAPS
- IPSTS_CTS
- IPSTS_DCD
- IPSTS_DSR
- IPSTS_INDICATE
- IPSTS_RI
- IPSTS_TMI
- IPS_ADAPTECCOPYRIGHT_STRING
- IPS_ADAPTER
- IPS_ADAPTER_ID
- IPS_ADTYPE_KIOWA
- IPS_ADTYPE_NAVAJO
- IPS_ADTYPE_SERVERAID
- IPS_ADTYPE_SERVERAID2
- IPS_ADTYPE_SERVERAID3
- IPS_ADTYPE_SERVERAID3L
- IPS_ADTYPE_SERVERAID4H
- IPS_ADTYPE_SERVERAID4L
- IPS_ADTYPE_SERVERAID4LX
- IPS_ADTYPE_SERVERAID4M
- IPS_ADTYPE_SERVERAID4MX
- IPS_ADTYPE_SERVERAID5I1
- IPS_ADTYPE_SERVERAID5I2
- IPS_ADTYPE_SERVERAID6I
- IPS_ADTYPE_SERVERAID6M
- IPS_ADTYPE_SERVERAID7M
- IPS_ADTYPE_SERVERAID7k
- IPS_ADTYPE_SERVERAID7t
- IPS_ASSURED
- IPS_ASSURED_BIT
- IPS_BASIC_STATUS_MASK
- IPS_BIOS_HEADER
- IPS_BIOS_IMAGE
- IPS_BIT_EBM
- IPS_BIT_EI
- IPS_BIT_GHI
- IPS_BIT_I2O_OPQI
- IPS_BIT_I960_MSG0I
- IPS_BIT_I960_MSG1I
- IPS_BIT_ILE
- IPS_BIT_OP
- IPS_BIT_RST
- IPS_BIT_SCE
- IPS_BIT_SEM
- IPS_BIT_SQO
- IPS_BIT_START_CMD
- IPS_BIT_START_STOP
- IPS_BLKSIZE
- IPS_BUILD_IDENT
- IPS_BUSY
- IPS_CALLBACK_FUNCION
- IPS_CALLBACK_JOIN_REQUEST
- IPS_CALLBACK_MGNT_LINK_REQUEST
- IPS_CALLBACK_NONE
- IPS_CHUNK
- IPS_CMD_CMPLT_WERROR
- IPS_CMD_CONFIG_SYNC
- IPS_CMD_DCDB
- IPS_CMD_DCDB_SG
- IPS_CMD_DOWNLOAD
- IPS_CMD_ENQUIRY
- IPS_CMD_ERROR_TABLE
- IPS_CMD_EXTENDED_DCDB
- IPS_CMD_EXTENDED_DCDB_SG
- IPS_CMD_FFDC
- IPS_CMD_FLUSH
- IPS_CMD_GET_LD_INFO
- IPS_CMD_GET_SUBSYS
- IPS_CMD_GET_VERSION_INFO
- IPS_CMD_READ
- IPS_CMD_READ_CONF
- IPS_CMD_READ_SG
- IPS_CMD_RECOVERED_ERROR
- IPS_CMD_RESET_CHANNEL
- IPS_CMD_RW_BIOSFW
- IPS_CMD_RW_NVRAM_PAGE
- IPS_CMD_SUCCESS
- IPS_CMD_TIMEOUT
- IPS_CMD_WRITE
- IPS_CMD_WRITE_SG
- IPS_COMMAND_ID
- IPS_COMPAT_BIOS
- IPS_COMPAT_CURRENT
- IPS_COMPAT_ID_LENGTH
- IPS_COMPAT_KEYWEST
- IPS_COMPAT_KIOWA
- IPS_COMPAT_MARCO
- IPS_COMPAT_MAX_ADAPTER_TYPE
- IPS_COMPAT_NAVAJO
- IPS_COMPAT_SARASOTA
- IPS_COMPAT_SEBRING
- IPS_COMPAT_SERVERAID1
- IPS_COMPAT_SERVERAID2
- IPS_COMPAT_SERVERAID3H
- IPS_COMPAT_SERVERAID3L
- IPS_COMPAT_SERVERAID4H
- IPS_COMPAT_SERVERAID4L
- IPS_COMPAT_SERVERAID4Lx
- IPS_COMPAT_SERVERAID4M
- IPS_COMPAT_SERVERAID4Mx
- IPS_COMPAT_TAMPA
- IPS_COMPAT_UNKNOWN
- IPS_COMP_HEADS
- IPS_COMP_SECTORS
- IPS_CONF
- IPS_CONFIRMED
- IPS_CONFIRMED_BIT
- IPS_COPPIOCCMD
- IPS_COPPUSRCMD
- IPS_CSL
- IPS_CS_CMD
- IPS_CTL
- IPS_CTRLINFO
- IPS_CTRL_CHD420
- IPS_CTRL_CHD422
- IPS_CTRL_CLAMP
- IPS_CTRL_DITH
- IPS_CTRL_FT
- IPS_CTRL_LPF
- IPS_CTRL_RGB
- IPS_CTRL_SBS
- IPS_CTRL_YUV
- IPS_DATA_IN
- IPS_DATA_NONE
- IPS_DATA_OUT
- IPS_DATA_UNK
- IPS_DCDB_CMD
- IPS_DCDB_TABLE
- IPS_DCDB_TABLE_TAPE
- IPS_DEFINE_COMPAT_TABLE
- IPS_DELLCOPYRIGHT_STRING
- IPS_DEPTH
- IPS_DEPTH_MARK
- IPS_DEVICEID_COPPERHEAD
- IPS_DEVICEID_MARCO
- IPS_DEVICEID_MORPHEUS
- IPS_DEVSTATE
- IPS_DISCONNECT_ALLOWED
- IPS_DMA_DIR
- IPS_DRIVE_INFO
- IPS_DST_NAT
- IPS_DST_NAT_BIT
- IPS_DST_NAT_DONE
- IPS_DST_NAT_DONE_BIT
- IPS_DYING
- IPS_DYING_BIT
- IPS_ENABLE
- IPS_ENH_SG_LIST
- IPS_ENQ
- IPS_ERASE_BIOS
- IPS_ERR_CKCOND
- IPS_ERR_DEV_RESET
- IPS_ERR_HOST_RESET
- IPS_ERR_OU_RUN
- IPS_ERR_RECOVERY
- IPS_ERR_SEL_TO
- IPS_EXPECTED
- IPS_EXPECTED_BIT
- IPS_FAILURE
- IPS_FC_CMD
- IPS_FFDC
- IPS_FFDC_CMD
- IPS_FIXED_TIMEOUT
- IPS_FIXED_TIMEOUT_BIT
- IPS_FLASHBIOS_CMD
- IPS_FLASHFW_CMD
- IPS_FW_IMAGE
- IPS_GET_VERSION_SUPPORT
- IPS_GOOD_POST_STATUS
- IPS_GSC_STATUS_MASK
- IPS_HA
- IPS_HARDWARE
- IPS_HAS_ENH_SGLIST
- IPS_HA_ENH_SG
- IPS_HELPER
- IPS_HELPER_BIT
- IPS_HOST_COMMAND
- IPS_IMAGE_SIZE
- IPS_INFO_CHD420
- IPS_INTR_IORL
- IPS_INTR_ON
- IPS_INVAL_CMD_BLK
- IPS_INVAL_OPCO
- IPS_INVAL_PARM_BLK
- IPS_IOCTL_CMD
- IPS_IOCTL_COMMAND
- IPS_IOCTL_SIZE
- IPS_IO_CMD
- IPS_IS_CLARINET
- IPS_IS_MARCO
- IPS_IS_MORPHEUS
- IPS_IS_TROMBONE
- IPS_LD
- IPS_LD_CMD
- IPS_LD_CRS
- IPS_LD_ERROR
- IPS_LD_FREE
- IPS_LD_INFO
- IPS_LD_OFFLINE
- IPS_LD_OKAY
- IPS_LD_SYS
- IPS_LEGALCOPYRIGHT_STRING
- IPS_LEVEL_2
- IPS_MAX_ADAPTERS
- IPS_MAX_ADAPTER_TYPES
- IPS_MAX_CHANNELS
- IPS_MAX_CHUNKS
- IPS_MAX_CMDS
- IPS_MAX_CONFIG_BYTES
- IPS_MAX_IOCTL
- IPS_MAX_IOCTL_QUEUE
- IPS_MAX_LD
- IPS_MAX_POST_BYTES
- IPS_MAX_QUEUE
- IPS_MAX_SG
- IPS_MAX_TARGETS
- IPS_MAX_XFER
- IPS_MEMMAP_SIZE
- IPS_NAT_DONE_MASK
- IPS_NAT_MASK
- IPS_NONE
- IPS_NORMAL
- IPS_NORM_HEADS
- IPS_NORM_SECTORS
- IPS_NORM_STATE
- IPS_NOTIMEOUT
- IPS_NO_AUTO_REQSEN
- IPS_NO_DISCONNECT
- IPS_NT_LEGALCOPYRIGHT_STRING
- IPS_NUM
- IPS_NUMCTRLS
- IPS_NUM_INPUT_IDS
- IPS_NUM_OUTPUT_IDS
- IPS_NVRAM_CMD
- IPS_NVRAM_P5
- IPS_NVRAM_P5_SIG
- IPS_OFFLOAD
- IPS_OFFLOAD_BIT
- IPS_ONE_MSEC
- IPS_ONE_SEC
- IPS_OPTION
- IPS_OS_FREEBSD
- IPS_OS_LINUX
- IPS_OS_NETWARE
- IPS_OS_OPENSERVER
- IPS_OS_OS2
- IPS_OS_SOLARIS
- IPS_OS_UNIXWARE
- IPS_OS_WINDOWS_NT
- IPS_PCODE_CONTROL
- IPS_PHYS_DRV_ERROR
- IPS_POCL
- IPS_PRINTK
- IPS_PROTO_VERSION
- IPS_REG_CBSP
- IPS_REG_CCCR
- IPS_REG_CCSAR
- IPS_REG_FLAP
- IPS_REG_FLDP
- IPS_REG_HISR
- IPS_REG_I2O_HIR
- IPS_REG_I2O_INMSGQ
- IPS_REG_I2O_OUTMSGQ
- IPS_REG_I960_IDR
- IPS_REG_I960_MSG0
- IPS_REG_I960_MSG1
- IPS_REG_I960_OIMR
- IPS_REG_ISPR
- IPS_REG_NDAE
- IPS_REG_SCPR
- IPS_REG_SQER
- IPS_REG_SQHR
- IPS_REG_SQSR
- IPS_REG_SQTR
- IPS_RELEASE_ID
- IPS_RESET_CMD
- IPS_REVID_CLARINETP1
- IPS_REVID_CLARINETP2
- IPS_REVID_CLARINETP3
- IPS_REVID_NAVAJO
- IPS_REVID_SERVERAID
- IPS_REVID_SERVERAID2
- IPS_REVID_TROMBONE32
- IPS_REVID_TROMBONE64
- IPS_RGB_RGB_COEFF0
- IPS_RGB_YUV_COEFF0
- IPS_SAMPLE_COUNT
- IPS_SCB_MAP_SG
- IPS_SCB_MAP_SINGLE
- IPS_SCSI_CAPACITY
- IPS_SCSI_INQ_Address16
- IPS_SCSI_INQ_Address32
- IPS_SCSI_INQ_CmdQue
- IPS_SCSI_INQ_DATA
- IPS_SCSI_INQ_EncServ
- IPS_SCSI_INQ_LU_CONNECTED
- IPS_SCSI_INQ_Linked
- IPS_SCSI_INQ_MedChanger
- IPS_SCSI_INQ_MultiPort
- IPS_SCSI_INQ_RD_REV2
- IPS_SCSI_INQ_REV2
- IPS_SCSI_INQ_REV3
- IPS_SCSI_INQ_RelAdr
- IPS_SCSI_INQ_SoftReset
- IPS_SCSI_INQ_Sync
- IPS_SCSI_INQ_TYPE_DASD
- IPS_SCSI_INQ_TYPE_PROCESSOR
- IPS_SCSI_INQ_WBus16
- IPS_SCSI_INQ_WBus32
- IPS_SCSI_MODE_PAGE3
- IPS_SCSI_MODE_PAGE4
- IPS_SCSI_MODE_PAGE8
- IPS_SCSI_MODE_PAGE_BLKDESC
- IPS_SCSI_MODE_PAGE_DATA
- IPS_SCSI_MODE_PAGE_HEADER
- IPS_SCSI_MP3_AllocateSurface
- IPS_SCSI_MP3_HardSector
- IPS_SCSI_MP3_Removeable
- IPS_SCSI_MP3_SoftSector
- IPS_SCSI_REQSEN
- IPS_SCSI_REQSEN_CURRENT_ERR
- IPS_SCSI_REQSEN_NO_SENSE
- IPS_SCSI_REQSEN_VALID
- IPS_SECS_8HOURS
- IPS_SEEN_REPLY
- IPS_SEEN_REPLY_BIT
- IPS_SEM_TIMEOUT
- IPS_SEQ_ADJUST
- IPS_SEQ_ADJUST_BIT
- IPS_SGLIST_SIZE
- IPS_SG_LIST
- IPS_SRC_NAT
- IPS_SRC_NAT_BIT
- IPS_SRC_NAT_DONE
- IPS_SRC_NAT_DONE_BIT
- IPS_STATUS
- IPS_STATUS_CMD
- IPS_STATUS_Q_SIZE
- IPS_STATUS_SIZE
- IPS_STD_SG_LIST
- IPS_SUBDEVICEID_4L
- IPS_SUBDEVICEID_4LX
- IPS_SUBDEVICEID_4M
- IPS_SUBDEVICEID_4MX
- IPS_SUBDEVICEID_5I1
- IPS_SUBDEVICEID_5I2
- IPS_SUBDEVICEID_6I
- IPS_SUBDEVICEID_6M
- IPS_SUBDEVICEID_7M
- IPS_SUBDEVICEID_7k
- IPS_SUBSYS
- IPS_SUCCESS
- IPS_SUCCESS_IMM
- IPS_TEMPLATE
- IPS_TEMPLATE_BIT
- IPS_TIMEOUT10
- IPS_TIMEOUT20M
- IPS_TIMEOUT60
- IPS_TRANSFER64K
- IPS_UNCHANGEABLE_MASK
- IPS_UNTRACKED
- IPS_UNTRACKED_BIT
- IPS_USE_ENH_SGLIST
- IPS_USE_I2O_DELIVER
- IPS_USE_MEMIO
- IPS_US_CMD
- IPS_VENDORID_ADAPTEC
- IPS_VENDORID_IBM
- IPS_VERSION_DATA
- IPS_VERSION_HIGH
- IPS_VERSION_INFO
- IPS_VERSION_LOW
- IPS_VER_BUILD
- IPS_VER_BUILD_STRING
- IPS_VER_KEYWEST
- IPS_VER_MAJOR
- IPS_VER_MAJOR_STRING
- IPS_VER_MARCO
- IPS_VER_MINOR
- IPS_VER_MINOR_STRING
- IPS_VER_NAVAJO
- IPS_VER_SARASOTA
- IPS_VER_SEBRING
- IPS_VER_SERVERAID1
- IPS_VER_SERVERAID2
- IPS_VER_SERVERAID3
- IPS_VER_SERVERAID4H
- IPS_VER_SERVERAID4MLx
- IPS_VER_STRING
- IPS_WRITE_BIOS
- IPS_WRITE_FW
- IPTE_GLOBAL
- IPTE_GUEST_ASCE
- IPTE_LOCAL
- IPTE_NODAT
- IPTOS_LOWDELAY
- IPTOS_MASK
- IPTOS_MINCOST
- IPTOS_OFFSET
- IPTOS_PREC
- IPTOS_PREC_CRITIC_ECP
- IPTOS_PREC_FLASH
- IPTOS_PREC_FLASHOVERRIDE
- IPTOS_PREC_IMMEDIATE
- IPTOS_PREC_INTERNETCONTROL
- IPTOS_PREC_MASK
- IPTOS_PREC_NETCONTROL
- IPTOS_PREC_PRIORITY
- IPTOS_PREC_ROUTINE
- IPTOS_RELIABILITY
- IPTOS_RT_MASK
- IPTOS_SHIFT
- IPTOS_THROUGHPUT
- IPTOS_TOS
- IPTOS_TOS_MASK
- IPTUNNEL_ERR_TIMEO
- IPT_AH_INV_MASK
- IPT_AH_INV_SPI
- IPT_BASE_CTL
- IPT_CONTINUE
- IPT_ECN_IP_MASK
- IPT_ECN_OP_MASK
- IPT_ECN_OP_MATCH_CWR
- IPT_ECN_OP_MATCH_ECE
- IPT_ECN_OP_MATCH_IP
- IPT_ECN_OP_MATCH_MASK
- IPT_ECN_OP_SET_CWR
- IPT_ECN_OP_SET_ECE
- IPT_ECN_OP_SET_IP
- IPT_ENTRY_INIT
- IPT_ENTRY_ITERATE
- IPT_ERROR_INIT
- IPT_ERROR_TARGET
- IPT_FUNCTION_MAXNAMELEN
- IPT_F_FRAG
- IPT_F_GOTO
- IPT_F_MASK
- IPT_ICMP_ADMIN_PROHIBITED
- IPT_ICMP_ECHOREPLY
- IPT_ICMP_HOST_PROHIBITED
- IPT_ICMP_HOST_UNREACHABLE
- IPT_ICMP_INV
- IPT_ICMP_NET_PROHIBITED
- IPT_ICMP_NET_UNREACHABLE
- IPT_ICMP_PORT_UNREACHABLE
- IPT_ICMP_PROT_UNREACHABLE
- IPT_INV_DSTIP
- IPT_INV_FRAG
- IPT_INV_MASK
- IPT_INV_PROTO
- IPT_INV_SRCIP
- IPT_INV_TOS
- IPT_INV_VIA_IN
- IPT_INV_VIA_OUT
- IPT_LOG_IPOPT
- IPT_LOG_MACDECODE
- IPT_LOG_MASK
- IPT_LOG_NFLOG
- IPT_LOG_TCPOPT
- IPT_LOG_TCPSEQ
- IPT_LOG_UID
- IPT_MATCH_ITERATE
- IPT_RETURN
- IPT_SO_GET_ENTRIES
- IPT_SO_GET_INFO
- IPT_SO_GET_MAX
- IPT_SO_GET_REVISION_MATCH
- IPT_SO_GET_REVISION_TARGET
- IPT_SO_SET_ADD_COUNTERS
- IPT_SO_SET_MAX
- IPT_SO_SET_REPLACE
- IPT_STANDARD_INIT
- IPT_STANDARD_TARGET
- IPT_TABLE_MAXNAMELEN
- IPT_TCP_INV_DSTPT
- IPT_TCP_INV_FLAGS
- IPT_TCP_INV_MASK
- IPT_TCP_INV_OPTION
- IPT_TCP_INV_SRCPT
- IPT_TCP_RESET
- IPT_TTL_DEC
- IPT_TTL_EQ
- IPT_TTL_GT
- IPT_TTL_INC
- IPT_TTL_LT
- IPT_TTL_MAXMODE
- IPT_TTL_NE
- IPT_TTL_SET
- IPT_UDP_INV_DSTPT
- IPT_UDP_INV_MASK
- IPT_UDP_INV_SRCPT
- IPU
- IPU3_ADDR2PTE
- IPU3_CSS_AUX_FRAMES
- IPU3_CSS_AUX_FRAME_REF
- IPU3_CSS_AUX_FRAME_TNR
- IPU3_CSS_AUX_FRAME_TYPES
- IPU3_CSS_BUFFER_DONE
- IPU3_CSS_BUFFER_FAILED
- IPU3_CSS_BUFFER_NEW
- IPU3_CSS_BUFFER_QUEUED
- IPU3_CSS_DEFAULT_BINARY
- IPU3_CSS_FORMAT_BPP_DEN
- IPU3_CSS_FORMAT_FL_IN
- IPU3_CSS_FORMAT_FL_OUT
- IPU3_CSS_FORMAT_FL_VF
- IPU3_CSS_MAX_H
- IPU3_CSS_MAX_W
- IPU3_CSS_MIN_RES
- IPU3_CSS_PIPE_ID_ACC
- IPU3_CSS_PIPE_ID_CAPTURE
- IPU3_CSS_PIPE_ID_COPY
- IPU3_CSS_PIPE_ID_NUM
- IPU3_CSS_PIPE_ID_PREVIEW
- IPU3_CSS_PIPE_ID_VIDEO
- IPU3_CSS_PIPE_ID_YUVPP
- IPU3_CSS_POOL_SIZE
- IPU3_CSS_QUEUES
- IPU3_CSS_QUEUE_IN
- IPU3_CSS_QUEUE_OUT
- IPU3_CSS_QUEUE_PARAMS
- IPU3_CSS_QUEUE_STAT_3A
- IPU3_CSS_QUEUE_TO_FLAGS
- IPU3_CSS_QUEUE_VF
- IPU3_CSS_RECTS
- IPU3_CSS_RECT_BDS
- IPU3_CSS_RECT_EFFECTIVE
- IPU3_CSS_RECT_ENVELOPE
- IPU3_CSS_RECT_GDC
- IPU3_INPUT_MAX_HEIGHT
- IPU3_INPUT_MAX_WIDTH
- IPU3_INPUT_MIN_HEIGHT
- IPU3_INPUT_MIN_WIDTH
- IPU3_L1PT_MASK
- IPU3_L1PT_SHIFT
- IPU3_L2PT_MASK
- IPU3_L2PT_SHIFT
- IPU3_MMU_ADDRESS_BITS
- IPU3_OUTPUT_MAX_HEIGHT
- IPU3_OUTPUT_MAX_WIDTH
- IPU3_OUTPUT_MIN_HEIGHT
- IPU3_OUTPUT_MIN_WIDTH
- IPU3_PAGE_SHIFT
- IPU3_PAGE_SIZE
- IPU3_PTE2ADDR
- IPU3_PT_BITS
- IPU3_PT_ORDER
- IPU3_PT_PTES
- IPU3_PT_SIZE
- IPU3_RUNNING_MODE_STILL
- IPU3_RUNNING_MODE_VIDEO
- IPU3_UAPI_AE_BINS
- IPU3_UAPI_AE_COLORS
- IPU3_UAPI_AE_WEIGHTS
- IPU3_UAPI_AF_MAX_SETS
- IPU3_UAPI_AF_MD_ITEM_SIZE
- IPU3_UAPI_AF_SPARE_FOR_BUBBLES
- IPU3_UAPI_AF_Y_TABLE_MAX_SIZE
- IPU3_UAPI_AF_Y_TABLE_SET_SIZE
- IPU3_UAPI_ANR_LUT_SIZE
- IPU3_UAPI_ANR_MAX_RESET
- IPU3_UAPI_ANR_MIN_RESET
- IPU3_UAPI_ANR_PYRAMID_SIZE
- IPU3_UAPI_AWB_FR_BAYER_TABLE_MAX_SIZE
- IPU3_UAPI_AWB_FR_BAYER_TBL_SIZE
- IPU3_UAPI_AWB_FR_MAX_SETS
- IPU3_UAPI_AWB_FR_MD_ITEM_SIZE
- IPU3_UAPI_AWB_FR_SPARE_FOR_BUBBLES
- IPU3_UAPI_AWB_MAX_BUFFER_SIZE
- IPU3_UAPI_AWB_MAX_SETS
- IPU3_UAPI_AWB_MD_ITEM_SIZE
- IPU3_UAPI_AWB_RGBS_THR_B_EN
- IPU3_UAPI_AWB_RGBS_THR_B_INCL_SAT
- IPU3_UAPI_AWB_SET_SIZE
- IPU3_UAPI_AWB_SPARE_FOR_BUBBLES
- IPU3_UAPI_BNR_LUT_SIZE
- IPU3_UAPI_GAMMA_CORR_LUT_ENTRIES
- IPU3_UAPI_GRID_START_MASK
- IPU3_UAPI_GRID_Y_START_EN
- IPU3_UAPI_ISP_TNR3_VMEM_LEN
- IPU3_UAPI_ISP_VEC_ELEMS
- IPU3_UAPI_LIN_LUT_SIZE
- IPU3_UAPI_MAX_BUBBLE_SIZE
- IPU3_UAPI_MAX_STRIPES
- IPU3_UAPI_SHD_BLGR_NF_MASK
- IPU3_UAPI_SHD_BLGR_NF_SHIFT
- IPU3_UAPI_SHD_MAX_CELLS_PER_SET
- IPU3_UAPI_SHD_MAX_CFG_SETS
- IPU3_UAPI_YUVP2_TCC_GAIN_PCWL_LUT_ELEMENTS
- IPU3_UAPI_YUVP2_TCC_INV_Y_LUT_ELEMENTS
- IPU3_UAPI_YUVP2_TCC_MACC_TABLE_ELEMENTS
- IPU3_UAPI_YUVP2_TCC_R_SQR_LUT_ELEMENTS
- IPUV3EX
- IPUV3H
- IPUV3M
- IPUV3_CHANNEL_CSI0
- IPUV3_CHANNEL_CSI1
- IPUV3_CHANNEL_CSI2
- IPUV3_CHANNEL_CSI3
- IPUV3_CHANNEL_CSI_DIRECT
- IPUV3_CHANNEL_CSI_VDI_PREV
- IPUV3_CHANNEL_DC_MEM_READ
- IPUV3_CHANNEL_G_MEM_IC_PP
- IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA
- IPUV3_CHANNEL_G_MEM_IC_PRP_VF
- IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA
- IPUV3_CHANNEL_IC_PP_MEM
- IPUV3_CHANNEL_IC_PRP_ENC_MEM
- IPUV3_CHANNEL_IC_PRP_VF_MEM
- IPUV3_CHANNEL_MEM_BG_ASYNC
- IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA
- IPUV3_CHANNEL_MEM_BG_SYNC
- IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA
- IPUV3_CHANNEL_MEM_DC_ASYNC
- IPUV3_CHANNEL_MEM_DC_COMMAND
- IPUV3_CHANNEL_MEM_DC_COMMAND2
- IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK
- IPUV3_CHANNEL_MEM_DC_SYNC
- IPUV3_CHANNEL_MEM_FG_ASYNC
- IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA
- IPUV3_CHANNEL_MEM_FG_SYNC
- IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA
- IPUV3_CHANNEL_MEM_IC_PP
- IPUV3_CHANNEL_MEM_IC_PRP_VF
- IPUV3_CHANNEL_MEM_ROT_ENC
- IPUV3_CHANNEL_MEM_ROT_PP
- IPUV3_CHANNEL_MEM_ROT_VF
- IPUV3_CHANNEL_MEM_VDI_CUR
- IPUV3_CHANNEL_MEM_VDI_NEXT
- IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB
- IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA
- IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB
- IPUV3_CHANNEL_MEM_VDI_PREV
- IPUV3_CHANNEL_ROT_ENC_MEM
- IPUV3_CHANNEL_ROT_PP_MEM
- IPUV3_CHANNEL_ROT_VF_MEM
- IPUV3_CHANNEL_VDI_MEM_IC_VF
- IPUV3_CHANNEL_VDI_MEM_RECENT
- IPUV3_COLORSPACE_RGB
- IPUV3_COLORSPACE_UNKNOWN
- IPUV3_COLORSPACE_YUV
- IPUV3_NUM_CHANNELS
- IPUV3_NUM_FLOWS
- IPU_ALT_CHA_BUF0_RDY
- IPU_ALT_CHA_BUF1_RDY
- IPU_ALT_CHA_DB_MODE_SEL
- IPU_ALT_CUR_BUF0
- IPU_ALT_CUR_BUF1
- IPU_BRK_CTRL_1
- IPU_BRK_CTRL_2
- IPU_BRK_STAT
- IPU_CHANNELS_NUM
- IPU_CHANNEL_ENABLED
- IPU_CHANNEL_FREE
- IPU_CHANNEL_INITIALIZED
- IPU_CHANNEL_READY
- IPU_CHA_BUF0_RDY
- IPU_CHA_BUF1_RDY
- IPU_CHA_BUF2_RDY
- IPU_CHA_CUR_BUF
- IPU_CHA_DB_MODE_SEL
- IPU_CM_CSI0_REG_OFS
- IPU_CM_CSI1_REG_OFS
- IPU_CM_DC_REG_OFS
- IPU_CM_DMFC_REG_OFS
- IPU_CM_IC_REG_OFS
- IPU_CM_IDMAC_REG_OFS
- IPU_CM_IRT_REG_OFS
- IPU_CM_REG
- IPU_CM_SMFC_REG_OFS
- IPU_COLORSPACE_RGB
- IPU_COLORSPACE_YCBCR
- IPU_COLORSPACE_YUV
- IPU_CONF
- IPU_CONF_ADC_EN
- IPU_CONF_CSI0_DATA_SOURCE
- IPU_CONF_CSI0_EN
- IPU_CONF_CSI1_DATA_SOURCE
- IPU_CONF_CSI1_EN
- IPU_CONF_CSI_EN
- IPU_CONF_CSI_SEL
- IPU_CONF_DC_EN
- IPU_CONF_DI0_EN
- IPU_CONF_DI1_EN
- IPU_CONF_DI_EN
- IPU_CONF_DMFC_EN
- IPU_CONF_DP_EN
- IPU_CONF_DU_EN
- IPU_CONF_IC_DMFC_SEL
- IPU_CONF_IC_DMFC_SYNC
- IPU_CONF_IC_EN
- IPU_CONF_IC_INPUT
- IPU_CONF_IDMAC_DIS
- IPU_CONF_ISP_EN
- IPU_CONF_PF_EN
- IPU_CONF_PXL_ENDIAN
- IPU_CONF_ROT_EN
- IPU_CONF_SDC_EN
- IPU_CONF_SMFC_EN
- IPU_CONF_VDI_DMFC_SYNC
- IPU_CONF_VDI_EN
- IPU_CPMEM_WORD
- IPU_CSI0
- IPU_CSI1
- IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR
- IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR
- IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR
- IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR
- IPU_CSI_CLK_MODE_CCIR656_INTERLACED
- IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE
- IPU_CSI_CLK_MODE_GATED_CLK
- IPU_CSI_CLK_MODE_NONGATED_CLK
- IPU_CSI_DATA_WIDTH_10
- IPU_CSI_DATA_WIDTH_12
- IPU_CSI_DATA_WIDTH_16
- IPU_CSI_DATA_WIDTH_4
- IPU_CSI_DATA_WIDTH_8
- IPU_CSI_DEST_IC
- IPU_CSI_DEST_IDMAC
- IPU_CSI_DEST_VDIC
- IPU_DC_MAP_BGR24
- IPU_DC_MAP_BGR666
- IPU_DC_MAP_GBR24
- IPU_DC_MAP_LVDS666
- IPU_DC_MAP_RGB24
- IPU_DC_MAP_RGB565
- IPU_DC_NUM_CHANNELS
- IPU_DI0_COUNTER_RELEASE
- IPU_DI1_COUNTER_RELEASE
- IPU_DIAGB_CTRL
- IPU_DISP_ALT1
- IPU_DISP_ALT2
- IPU_DISP_ALT3
- IPU_DISP_ALT4
- IPU_DISP_ALT_CONF
- IPU_DISP_DATA_MAPPING_RGB565
- IPU_DISP_DATA_MAPPING_RGB666
- IPU_DISP_DATA_MAPPING_RGB888
- IPU_DISP_GEN
- IPU_DISP_TASK_STAT
- IPU_DI_CLKMODE_EXT
- IPU_DI_CLKMODE_SYNC
- IPU_DP_FLOW_ASYNC0_BG
- IPU_DP_FLOW_ASYNC0_FG
- IPU_DP_FLOW_ASYNC1_BG
- IPU_DP_FLOW_ASYNC1_FG
- IPU_DP_FLOW_SYNC_BG
- IPU_DP_FLOW_SYNC_FG
- IPU_FIELD_ALBM
- IPU_FIELD_ALU
- IPU_FIELD_BM
- IPU_FIELD_BNDM
- IPU_FIELD_BPP
- IPU_FIELD_CAE
- IPU_FIELD_CAP
- IPU_FIELD_CF
- IPU_FIELD_CRE
- IPU_FIELD_DEC_SEL
- IPU_FIELD_DEC_SEL2
- IPU_FIELD_DIM
- IPU_FIELD_EBA0
- IPU_FIELD_EBA1
- IPU_FIELD_FH
- IPU_FIELD_FW
- IPU_FIELD_HF
- IPU_FIELD_ID
- IPU_FIELD_ILO
- IPU_FIELD_IOX
- IPU_FIELD_NPB
- IPU_FIELD_NS
- IPU_FIELD_NSB_B
- IPU_FIELD_OFS0
- IPU_FIELD_OFS1
- IPU_FIELD_OFS2
- IPU_FIELD_OFS3
- IPU_FIELD_PFS
- IPU_FIELD_RDRW
- IPU_FIELD_ROT
- IPU_FIELD_ROT_HF_VF
- IPU_FIELD_SCC
- IPU_FIELD_SCE
- IPU_FIELD_SDRX
- IPU_FIELD_SDRY
- IPU_FIELD_SDX
- IPU_FIELD_SDY
- IPU_FIELD_SL
- IPU_FIELD_SLUV
- IPU_FIELD_SLY
- IPU_FIELD_SM
- IPU_FIELD_SO
- IPU_FIELD_SX
- IPU_FIELD_SXYS
- IPU_FIELD_SY
- IPU_FIELD_TH
- IPU_FIELD_THE
- IPU_FIELD_UBO
- IPU_FIELD_VBO
- IPU_FIELD_VF
- IPU_FIELD_WID0
- IPU_FIELD_WID1
- IPU_FIELD_WID2
- IPU_FIELD_WID3
- IPU_FIELD_XB
- IPU_FIELD_XV
- IPU_FIELD_YB
- IPU_FIELD_YV
- IPU_FS_DISP_FLOW
- IPU_FS_DISP_FLOW1
- IPU_FS_DISP_FLOW2
- IPU_FS_PROC_FLOW
- IPU_FS_PROC_FLOW1
- IPU_FS_PROC_FLOW2
- IPU_FS_PROC_FLOW3
- IPU_GPR
- IPU_IC_PRP
- IPU_IC_PRPENC
- IPU_IC_PRPVF
- IPU_IDMAC_REG
- IPU_IMA_ADDR
- IPU_IMA_DATA
- IPU_INT_CTRL
- IPU_INT_CTRL_1
- IPU_INT_CTRL_2
- IPU_INT_CTRL_3
- IPU_INT_CTRL_4
- IPU_INT_CTRL_5
- IPU_INT_STAT
- IPU_INT_STAT_1
- IPU_INT_STAT_2
- IPU_INT_STAT_3
- IPU_INT_STAT_4
- IPU_INT_STAT_5
- IPU_IRQ_BG_SF_END
- IPU_IRQ_DC_FC_0
- IPU_IRQ_DC_FC_1
- IPU_IRQ_DC_FC_2
- IPU_IRQ_DC_FC_3
- IPU_IRQ_DC_FC_4
- IPU_IRQ_DC_FC_6
- IPU_IRQ_DP_SF_END
- IPU_IRQ_DP_SF_START
- IPU_IRQ_EOF
- IPU_IRQ_EOS
- IPU_IRQ_NFACK
- IPU_IRQ_NFB4EOF
- IPU_IRQ_NR_BANKS
- IPU_IRQ_NR_ERR_BANKS
- IPU_IRQ_NR_FN_BANKS
- IPU_IRQ_VSYNC_PRE_0
- IPU_IRQ_VSYNC_PRE_1
- IPU_MCU_T_DEFAULT
- IPU_MEM_RST
- IPU_NUM_IRQS
- IPU_PANEL_SHARP_TFT
- IPU_PANEL_TFT
- IPU_PIX_FMT_ABGR32
- IPU_PIX_FMT_BGR24
- IPU_PIX_FMT_BGR32
- IPU_PIX_FMT_BGR666
- IPU_PIX_FMT_BGRA32
- IPU_PIX_FMT_GBR24
- IPU_PIX_FMT_GENERIC
- IPU_PIX_FMT_GENERIC_32
- IPU_PIX_FMT_RGB24
- IPU_PIX_FMT_RGB32
- IPU_PIX_FMT_RGB332
- IPU_PIX_FMT_RGB565
- IPU_PIX_FMT_RGB666
- IPU_PIX_FMT_RGBA32
- IPU_PIX_FMT_UYVY
- IPU_PIX_FMT_YUV420P
- IPU_PIX_FMT_YUV420P2
- IPU_PIX_FMT_YUV422P
- IPU_PIX_FMT_YUYV
- IPU_PIX_FMT_YVU422P
- IPU_PM
- IPU_PRE_CTRL
- IPU_PRE_CTRL_BLOCK_16
- IPU_PRE_CTRL_BLOCK_EN
- IPU_PRE_CTRL_CLKGATE
- IPU_PRE_CTRL_ENABLE
- IPU_PRE_CTRL_EN_REPEAT
- IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN
- IPU_PRE_CTRL_HANDSHAKE_EN
- IPU_PRE_CTRL_HANDSHAKE_LINE_NUM
- IPU_PRE_CTRL_INTERLACED_FIELD
- IPU_PRE_CTRL_SDW_UPDATE
- IPU_PRE_CTRL_SET
- IPU_PRE_CTRL_SFTRST
- IPU_PRE_CTRL_SO
- IPU_PRE_CTRL_TPR_REST_SEL
- IPU_PRE_CTRL_VFLIP
- IPU_PRE_CUR_BUF
- IPU_PRE_MAX_WIDTH
- IPU_PRE_NEXT_BUF
- IPU_PRE_NUM_SCANLINES
- IPU_PRE_PREFETCH_ENG_CTRL
- IPU_PRE_PREFETCH_ENG_INPUT_SIZE
- IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT
- IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH
- IPU_PRE_PREFETCH_ENG_PITCH
- IPU_PRE_PREFETCH_ENG_PITCH_UV
- IPU_PRE_PREFETCH_ENG_PITCH_Y
- IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE
- IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP
- IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT
- IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP
- IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN
- IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES
- IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS
- IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN
- IPU_PRE_STORE_ENG_ADDR
- IPU_PRE_STORE_ENG_CTRL
- IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP
- IPU_PRE_STORE_ENG_CTRL_STORE_EN
- IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES
- IPU_PRE_STORE_ENG_PITCH
- IPU_PRE_STORE_ENG_PITCH_OUT_PITCH
- IPU_PRE_STORE_ENG_SIZE
- IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT
- IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH
- IPU_PRE_STORE_ENG_STATUS
- IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK
- IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT
- IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK
- IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT
- IPU_PRE_STORE_ENG_STATUS_STORE_FIELD
- IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL
- IPU_PRE_TPR_CTRL
- IPU_PRE_TPR_CTRL_TILE_FORMAT
- IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT
- IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK
- IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF
- IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF
- IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED
- IPU_PRG_BADDR
- IPU_PRG_CROP_LINE
- IPU_PRG_CTL
- IPU_PRG_CTL_BLOCK_MODE
- IPU_PRG_CTL_BYPASS
- IPU_PRG_CTL_CNT_LOAD_EN
- IPU_PRG_CTL_SHADOW_EN
- IPU_PRG_CTL_SO
- IPU_PRG_CTL_SOFTRST
- IPU_PRG_CTL_SOFT_ARID
- IPU_PRG_CTL_SOFT_ARID_MASK
- IPU_PRG_CTL_SOFT_ARID_SHIFT
- IPU_PRG_CTL_VFLIP
- IPU_PRG_HEIGHT
- IPU_PRG_HEIGHT_IPU_HEIGHT_MASK
- IPU_PRG_HEIGHT_IPU_HEIGHT_SHIFT
- IPU_PRG_HEIGHT_PRE_HEIGHT_MASK
- IPU_PRG_HEIGHT_PRE_HEIGHT_SHIFT
- IPU_PRG_ILO
- IPU_PRG_OFFSET
- IPU_PRG_QOS
- IPU_PRG_QOS_ARID_MASK
- IPU_PRG_QOS_ARID_SHIFT
- IPU_PRG_REG_UPDATE
- IPU_PRG_REG_UPDATE_REG_UPDATE
- IPU_PRG_STATUS
- IPU_PRG_STATUS_BUFFER0_READY
- IPU_PRG_STATUS_BUFFER1_READY
- IPU_PRG_STRIDE
- IPU_PRG_STRIDE_STRIDE_MASK
- IPU_PRG_THD
- IPU_PROC_TASK_STAT
- IPU_ROTATE_180
- IPU_ROTATE_90_LEFT
- IPU_ROTATE_90_RIGHT
- IPU_ROTATE_90_RIGHT_HFLIP
- IPU_ROTATE_90_RIGHT_VFLIP
- IPU_ROTATE_HORIZ_FLIP
- IPU_ROTATE_NONE
- IPU_ROTATE_VERT_FLIP
- IPU_ROT_BIT_90
- IPU_ROT_BIT_HFLIP
- IPU_ROT_BIT_VFLIP
- IPU_SKIP
- IPU_SNOOP
- IPU_SRM_PRI1
- IPU_SRM_PRI2
- IPU_SRM_STAT
- IPU_TASKS_STAT
- IPU_VDIC
- IPV4_ADDRX
- IPV4_ADDR_SIZE
- IPV4_BEET_PHMAXLEN
- IPV4_CS
- IPV4_DEVCONF
- IPV4_DEVCONF_ACCEPT_LOCAL
- IPV4_DEVCONF_ACCEPT_REDIRECTS
- IPV4_DEVCONF_ACCEPT_SOURCE_ROUTE
- IPV4_DEVCONF_ALL
- IPV4_DEVCONF_ARPFILTER
- IPV4_DEVCONF_ARP_ACCEPT
- IPV4_DEVCONF_ARP_ANNOUNCE
- IPV4_DEVCONF_ARP_IGNORE
- IPV4_DEVCONF_ARP_NOTIFY
- IPV4_DEVCONF_BC_FORWARDING
- IPV4_DEVCONF_BOOTP_RELAY
- IPV4_DEVCONF_DFLT
- IPV4_DEVCONF_DROP_GRATUITOUS_ARP
- IPV4_DEVCONF_DROP_UNICAST_IN_L2_MULTICAST
- IPV4_DEVCONF_FORCE_IGMP_VERSION
- IPV4_DEVCONF_FORWARDING
- IPV4_DEVCONF_IGMPV2_UNSOLICITED_REPORT_INTERVAL
- IPV4_DEVCONF_IGMPV3_UNSOLICITED_REPORT_INTERVAL
- IPV4_DEVCONF_IGNORE_ROUTES_WITH_LINKDOWN
- IPV4_DEVCONF_LOG_MARTIANS
- IPV4_DEVCONF_MAX
- IPV4_DEVCONF_MC_FORWARDING
- IPV4_DEVCONF_MEDIUM_ID
- IPV4_DEVCONF_NOPOLICY
- IPV4_DEVCONF_NOXFRM
- IPV4_DEVCONF_PROMOTE_SECONDARIES
- IPV4_DEVCONF_PROXY_ARP
- IPV4_DEVCONF_PROXY_ARP_PVLAN
- IPV4_DEVCONF_ROUTE_LOCALNET
- IPV4_DEVCONF_RP_FILTER
- IPV4_DEVCONF_SECURE_REDIRECTS
- IPV4_DEVCONF_SEND_REDIRECTS
- IPV4_DEVCONF_SHARED_MEDIA
- IPV4_DEVCONF_SRC_VMARK
- IPV4_DEVCONF_TAG
- IPV4_FLOW
- IPV4_HASH_TYPE
- IPV4_HDR_LEN
- IPV4_HDR_LEN_NO_OPT
- IPV4_HLEN
- IPV4_INDEX
- IPV4_LEN
- IPV4_MAX_PMTU
- IPV4_MIN_MTU
- IPV4_PKT_NO_CHKSUM_OFFLOAD
- IPV4_PKT_WITH_CHKSUM_OFFLOAD
- IPV4_PLUS_ICMP_HDR
- IPV4_PROT
- IPV4_PROT_DEF
- IPV4_UDP_MOD
- IPV4_USER_FLOW
- IPV6
- IPV6FR
- IPV6HDR_BASELEN
- IPV6ONLY_FLAGS
- IPV6OP
- IPV6_2292DSTOPTS
- IPV6_2292HOPLIMIT
- IPV6_2292HOPOPTS
- IPV6_2292PKTINFO
- IPV6_2292PKTOPTIONS
- IPV6_2292RTHDR
- IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR
- IPV6_ADDOPT_IGNORE_ICMP_ECHO_REQ
- IPV6_ADDOPT_MLD_EN
- IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE
- IPV6_ADDRFORM
- IPV6_ADDRX
- IPV6_ADDR_ANY
- IPV6_ADDR_COMPATv4
- IPV6_ADDR_ENTRY
- IPV6_ADDR_LABEL_DEFAULT
- IPV6_ADDR_LINKLOCAL
- IPV6_ADDR_LOOPBACK
- IPV6_ADDR_MAPPED
- IPV6_ADDR_MC_FLAG_PREFIX
- IPV6_ADDR_MC_FLAG_RENDEZVOUS
- IPV6_ADDR_MC_FLAG_TRANSIENT
- IPV6_ADDR_MC_SCOPE
- IPV6_ADDR_MULTICAST
- IPV6_ADDR_PREFERENCES
- IPV6_ADDR_SCOPE_GLOBAL
- IPV6_ADDR_SCOPE_LINKLOCAL
- IPV6_ADDR_SCOPE_MASK
- IPV6_ADDR_SCOPE_NODELOCAL
- IPV6_ADDR_SCOPE_ORGLOCAL
- IPV6_ADDR_SCOPE_SITELOCAL
- IPV6_ADDR_SCOPE_TYPE
- IPV6_ADDR_SITELOCAL
- IPV6_ADDR_SIZE
- IPV6_ADDR_UNICAST
- IPV6_ADD_MEMBERSHIP
- IPV6_AUTHHDR
- IPV6_AUTOFLOWLABEL
- IPV6_CHECKSUM
- IPV6_CHKSUM_CTRL_EN
- IPV6_CS
- IPV6_DECODE_PREF
- IPV6_DEFAULT_DDB_ENTRY
- IPV6_DEFAULT_HOPLIMIT
- IPV6_DEFAULT_MCASTHOPS
- IPV6_DEFAULT_TNL_ENCAP_LIMIT
- IPV6_DONTFRAG
- IPV6_DROP_MEMBERSHIP
- IPV6_DSTOPTS
- IPV6_EH_NOT_SUPPORTED
- IPV6_EH_SUPPORTED
- IPV6_EH_SUPPORTED_LIM
- IPV6_EXTRACT_PREF
- IPV6_FLOW
- IPV6_FLOWINFO
- IPV6_FLOWINFO_FLOWLABEL
- IPV6_FLOWINFO_MASK
- IPV6_FLOWINFO_PRIORITY
- IPV6_FLOWINFO_SEND
- IPV6_FLOWLABEL_MASK
- IPV6_FLOWLABEL_MGR
- IPV6_FLOWLABEL_STATELESS_FLAG
- IPV6_FLOW_LABEL_MASK
- IPV6_FL_A_GET
- IPV6_FL_A_PUT
- IPV6_FL_A_RENEW
- IPV6_FL_F_CREATE
- IPV6_FL_F_EXCL
- IPV6_FL_F_REFLECT
- IPV6_FL_F_REMOTE
- IPV6_FL_S_ANY
- IPV6_FL_S_EXCL
- IPV6_FL_S_NONE
- IPV6_FL_S_PROCESS
- IPV6_FL_S_USER
- IPV6_FRAG_HIGH_THRESH
- IPV6_FRAG_LOW_THRESH
- IPV6_FRAG_TIMEOUT
- IPV6_FREEBIND
- IPV6_HASH_TYPE
- IPV6_HDRINCL
- IPV6_HDR_LEN
- IPV6_HOPLIMIT
- IPV6_HOPOPTS
- IPV6_IPSEC_POLICY
- IPV6_JOIN_ANYCAST
- IPV6_LEAVE_ANYCAST
- IPV6_LEN
- IPV6_MAXPLEN
- IPV6_MAX_ADDRESSES
- IPV6_MAX_INDEX
- IPV6_MAX_STRLEN
- IPV6_MINHOPCOUNT
- IPV6_MIN_MTU
- IPV6_MLD_MAX_MSF
- IPV6_MLD_SNOOP_ENABLE
- IPV6_MLD_SNOOP_OPTION
- IPV6_MTU
- IPV6_MTU_DISCOVER
- IPV6_MULTICAST_ALL
- IPV6_MULTICAST_HOPS
- IPV6_MULTICAST_IF
- IPV6_MULTICAST_LOOP
- IPV6_NEXTHOP
- IPV6_OPT_GRAT_NEIGHBOR_ADV_EN
- IPV6_OPT_IPV6_PROTOCOL_ENABLE
- IPV6_OPT_REDIRECT_EN
- IPV6_OPT_ROUTERALERT_MLD
- IPV6_OPT_VLAN_TAGGING_ENABLE
- IPV6_ORIGDSTADDR
- IPV6_PATHMTU
- IPV6_PKT
- IPV6_PKTINFO
- IPV6_PLUS_ICMP_HDR
- IPV6_PMTUDISC_DO
- IPV6_PMTUDISC_DONT
- IPV6_PMTUDISC_INTERFACE
- IPV6_PMTUDISC_OMIT
- IPV6_PMTUDISC_PROBE
- IPV6_PMTUDISC_WANT
- IPV6_PREFER_SRC_CGA
- IPV6_PREFER_SRC_COA
- IPV6_PREFER_SRC_HOME
- IPV6_PREFER_SRC_NONCGA
- IPV6_PREFER_SRC_PUBLIC
- IPV6_PREFER_SRC_PUBTMP_DEFAULT
- IPV6_PREFER_SRC_TMP
- IPV6_PRIORITY_10
- IPV6_PRIORITY_11
- IPV6_PRIORITY_12
- IPV6_PRIORITY_13
- IPV6_PRIORITY_14
- IPV6_PRIORITY_15
- IPV6_PRIORITY_8
- IPV6_PRIORITY_9
- IPV6_PRIORITY_BULK
- IPV6_PRIORITY_CONTROL
- IPV6_PRIORITY_FILLER
- IPV6_PRIORITY_INTERACTIVE
- IPV6_PRIORITY_RESERVED1
- IPV6_PRIORITY_RESERVED2
- IPV6_PRIORITY_UNATTENDED
- IPV6_PRIORITY_UNCHARACTERIZED
- IPV6_PROT
- IPV6_PROT_DEF
- IPV6_RECVDSTOPTS
- IPV6_RECVERR
- IPV6_RECVFRAGSIZE
- IPV6_RECVHOPLIMIT
- IPV6_RECVHOPOPTS
- IPV6_RECVORIGDSTADDR
- IPV6_RECVPATHMTU
- IPV6_RECVPKTINFO
- IPV6_RECVRTHDR
- IPV6_RECVTCLASS
- IPV6_ROUTER_ALERT
- IPV6_ROUTER_ALERT_ISOLATE
- IPV6_RTHDR
- IPV6_RTHDRDSTOPTS
- IPV6_RTRSTATE_ADVERTISED
- IPV6_RTRSTATE_MANUAL
- IPV6_RTRSTATE_STALE
- IPV6_RTRSTATE_UNKNOWN
- IPV6_SADDR_RULE_HOA
- IPV6_SADDR_RULE_INIT
- IPV6_SADDR_RULE_LABEL
- IPV6_SADDR_RULE_LOCAL
- IPV6_SADDR_RULE_MAX
- IPV6_SADDR_RULE_NOT_OPTIMISTIC
- IPV6_SADDR_RULE_OIF
- IPV6_SADDR_RULE_ORCHID
- IPV6_SADDR_RULE_PREFERRED
- IPV6_SADDR_RULE_PREFIX
- IPV6_SADDR_RULE_PRIVACY
- IPV6_SADDR_RULE_SCOPE
- IPV6_SCOPE_DELIMITER
- IPV6_SCOPE_ID_LEN
- IPV6_SEQ_DGRAM_HEADER
- IPV6_SIZE
- IPV6_SRCRT_STRICT
- IPV6_SRCRT_TYPE_0
- IPV6_SRCRT_TYPE_2
- IPV6_SRCRT_TYPE_4
- IPV6_TCLASS
- IPV6_TCLASS_MASK
- IPV6_TCLASS_SHIFT
- IPV6_TCPOPT_DELAYED_ACK_DISABLE
- IPV6_TCPOPT_NAGLE_ALGO_DISABLE
- IPV6_TCPOPT_TIMER_SCALE
- IPV6_TCPOPT_TIMESTAMP_EN
- IPV6_TCPOPT_WINDOW_SCALE_DISABLE
- IPV6_TLV_CALIPSO
- IPV6_TLV_HAO
- IPV6_TLV_JUMBO
- IPV6_TLV_PAD1
- IPV6_TLV_PADN
- IPV6_TLV_ROUTERALERT
- IPV6_TLV_TNL_ENCAP_LIMIT
- IPV6_TRANSPARENT
- IPV6_UNICAST_HOPS
- IPV6_UNICAST_IF
- IPV6_USER_FLOW
- IPV6_USE_MIN_MTU
- IPV6_V6ONLY
- IPV6_XFRM_POLICY
- IPVERSION
- IPVLAN_DRV
- IPVLAN_FEATURES
- IPVLAN_F_PRIVATE
- IPVLAN_F_VEPA
- IPVLAN_HASH_MASK
- IPVLAN_HASH_SIZE
- IPVLAN_MAC_FILTER_BITS
- IPVLAN_MAC_FILTER_MASK
- IPVLAN_MAC_FILTER_SIZE
- IPVLAN_MODE_L2
- IPVLAN_MODE_L3
- IPVLAN_MODE_L3S
- IPVLAN_MODE_MAX
- IPVLAN_QBACKLOG_LIMIT
- IPVLAN_STATE_MASK
- IPVL_ARP
- IPVL_ICMPV6
- IPVL_IPV4
- IPVL_IPV6
- IPVL_SKB_CB
- IPVS_CMD_ATTR_DAEMON
- IPVS_CMD_ATTR_DEST
- IPVS_CMD_ATTR_MAX
- IPVS_CMD_ATTR_SERVICE
- IPVS_CMD_ATTR_TIMEOUT_TCP
- IPVS_CMD_ATTR_TIMEOUT_TCP_FIN
- IPVS_CMD_ATTR_TIMEOUT_UDP
- IPVS_CMD_ATTR_UNSPEC
- IPVS_CMD_DEL_DAEMON
- IPVS_CMD_DEL_DEST
- IPVS_CMD_DEL_SERVICE
- IPVS_CMD_FLUSH
- IPVS_CMD_GET_CONFIG
- IPVS_CMD_GET_DAEMON
- IPVS_CMD_GET_DEST
- IPVS_CMD_GET_INFO
- IPVS_CMD_GET_SERVICE
- IPVS_CMD_MAX
- IPVS_CMD_NEW_DAEMON
- IPVS_CMD_NEW_DEST
- IPVS_CMD_NEW_SERVICE
- IPVS_CMD_SET_CONFIG
- IPVS_CMD_SET_DEST
- IPVS_CMD_SET_INFO
- IPVS_CMD_SET_SERVICE
- IPVS_CMD_UNSPEC
- IPVS_CMD_ZERO
- IPVS_DAEMON_ATTR_MAX
- IPVS_DAEMON_ATTR_MCAST_GROUP
- IPVS_DAEMON_ATTR_MCAST_GROUP6
- IPVS_DAEMON_ATTR_MCAST_IFN
- IPVS_DAEMON_ATTR_MCAST_PORT
- IPVS_DAEMON_ATTR_MCAST_TTL
- IPVS_DAEMON_ATTR_STATE
- IPVS_DAEMON_ATTR_SYNC_ID
- IPVS_DAEMON_ATTR_SYNC_MAXLEN
- IPVS_DAEMON_ATTR_UNSPEC
- IPVS_DEST_ATTR_ACTIVE_CONNS
- IPVS_DEST_ATTR_ADDR
- IPVS_DEST_ATTR_ADDR_FAMILY
- IPVS_DEST_ATTR_FWD_METHOD
- IPVS_DEST_ATTR_INACT_CONNS
- IPVS_DEST_ATTR_L_THRESH
- IPVS_DEST_ATTR_MAX
- IPVS_DEST_ATTR_PERSIST_CONNS
- IPVS_DEST_ATTR_PORT
- IPVS_DEST_ATTR_STATS
- IPVS_DEST_ATTR_STATS64
- IPVS_DEST_ATTR_TUN_FLAGS
- IPVS_DEST_ATTR_TUN_PORT
- IPVS_DEST_ATTR_TUN_TYPE
- IPVS_DEST_ATTR_UNSPEC
- IPVS_DEST_ATTR_U_THRESH
- IPVS_DEST_ATTR_WEIGHT
- IPVS_GENL_NAME
- IPVS_GENL_VERSION
- IPVS_INFO_ATTR_CONN_TAB_SIZE
- IPVS_INFO_ATTR_MAX
- IPVS_INFO_ATTR_UNSPEC
- IPVS_INFO_ATTR_VERSION
- IPVS_OPT_F_PARAM
- IPVS_OPT_F_PE_DATA
- IPVS_OPT_F_PE_NAME
- IPVS_OPT_F_SEQ_DATA
- IPVS_OPT_PARAM
- IPVS_OPT_PE_DATA
- IPVS_OPT_PE_NAME
- IPVS_OPT_SEQ_DATA
- IPVS_STATS_ATTR_CONNS
- IPVS_STATS_ATTR_CPS
- IPVS_STATS_ATTR_INBPS
- IPVS_STATS_ATTR_INBYTES
- IPVS_STATS_ATTR_INPKTS
- IPVS_STATS_ATTR_INPPS
- IPVS_STATS_ATTR_MAX
- IPVS_STATS_ATTR_OUTBPS
- IPVS_STATS_ATTR_OUTBYTES
- IPVS_STATS_ATTR_OUTPKTS
- IPVS_STATS_ATTR_OUTPPS
- IPVS_STATS_ATTR_PAD
- IPVS_STATS_ATTR_UNSPEC
- IPVS_SVC_ATTR_ADDR
- IPVS_SVC_ATTR_AF
- IPVS_SVC_ATTR_FLAGS
- IPVS_SVC_ATTR_FWMARK
- IPVS_SVC_ATTR_MAX
- IPVS_SVC_ATTR_NETMASK
- IPVS_SVC_ATTR_PE_NAME
- IPVS_SVC_ATTR_PORT
- IPVS_SVC_ATTR_PROTOCOL
- IPVS_SVC_ATTR_SCHED_NAME
- IPVS_SVC_ATTR_STATS
- IPVS_SVC_ATTR_STATS64
- IPVS_SVC_ATTR_TIMEOUT
- IPVS_SVC_ATTR_UNSPEC
- IPVS_SYNC_CHECK_PERIOD
- IPVS_SYNC_FLUSH_TIME
- IPVS_SYNC_PORTS_MAX
- IPVS_SYNC_QLEN_MAX
- IPVS_SYNC_SEND_DELAY
- IPVS_SYNC_WAKEUP_RATE
- IPV_DRV_VER
- IPW2100_COMMAND
- IPW2100_COMMAND_PHY_OFF
- IPW2100_COMMAND_PHY_ON
- IPW2100_CONTROL_PHY_OFF
- IPW2100_CONTROL_REG
- IPW2100_DEV_ID
- IPW2100_ERROR_QUEUE
- IPW2100_ERR_C3_CORRUPTION
- IPW2100_ERR_FW_LOAD
- IPW2100_ERR_MSG_TIMEOUT
- IPW2100_FW_MAJOR
- IPW2100_FW_MAJOR_VERSION
- IPW2100_FW_MINOR
- IPW2100_FW_MINOR_VERSION
- IPW2100_FW_NAME
- IPW2100_FW_PREFIX
- IPW2100_FW_VERSION
- IPW2100_HANDLER
- IPW2100_INTA_BEACON_PERIOD_EXPIRED
- IPW2100_INTA_EVENT_INTERRUPT
- IPW2100_INTA_FATAL_ERROR
- IPW2100_INTA_FW_CALIBRATION_CALC
- IPW2100_INTA_FW_INIT_DONE
- IPW2100_INTA_PARITY_ERROR
- IPW2100_INTA_RX_TRANSFER
- IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE
- IPW2100_INTA_STATUS_CHANGE
- IPW2100_INTA_TX_COMPLETE
- IPW2100_INTA_TX_TRANSFER
- IPW2100_NIC
- IPW2100_ORD
- IPW2100_PM_DISABLED
- IPW2100_PRIV_GET_CRC_CHECK
- IPW2100_PRIV_GET_LONGPREAMBLE
- IPW2100_PRIV_GET_POWER
- IPW2100_PRIV_RESET
- IPW2100_PRIV_SET_CRC_CHECK
- IPW2100_PRIV_SET_LONGPREAMBLE
- IPW2100_PRIV_SET_MONITOR
- IPW2100_PRIV_SET_POWER
- IPW2100_REG
- IPW2100_RSSI_TO_DBM
- IPW2100_RX_DEBUG
- IPW2100_VERSION
- IPW2100_WEP_DROP_CLEAR
- IPW2100_WEP_ENABLE
- IPW2200_VERSION
- IPWIRELESS_PCCARD_NAME
- IPWIRELESS_PCMCIA_AUTHOR
- IPWIRELESS_PCMCIA_MINORS
- IPWIRELESS_PCMCIA_MINOR_RANGE
- IPWIRELESS_PCMCIA_START
- IPWIRELESS_PCMCIA_VERSION
- IPWIRELESS_RX_QUEUE_SIZE
- IPWIRELESS_STATE_DEBUG
- IPWIRELESS_TX_QUEUE_SIZE
- IPWSR_CLEAR
- IPW_2200BG
- IPW_2915ABG
- IPW_802_11_FCS_LENGTH
- IPW_802_11_PAYLOAD_OFFSET
- IPW_ACTIVITY_LED
- IPW_ARC_KESHET_CONFIG
- IPW_ASSOCIATED_LED
- IPW_ATIM_SENT
- IPW_AUTH_LEAP
- IPW_AUTH_LEAP_CISCO_ID
- IPW_AUTH_OPEN
- IPW_AUTH_SHARED
- IPW_AUTOINC_ADDR
- IPW_AUTOINC_DATA
- IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG
- IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE
- IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE
- IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY
- IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK
- IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY
- IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK
- IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE
- IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE
- IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI
- IPW_AUX_HOST_RESET_REG_FORCE_NMI
- IPW_AUX_HOST_RESET_REG_MASTER_DISABLED
- IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI
- IPW_AUX_HOST_RESET_REG_PRINCETON_RESET
- IPW_AUX_HOST_RESET_REG_STOP_MASTER
- IPW_AUX_HOST_RESET_REG_SW_RESET
- IPW_A_MODE
- IPW_BASEBAND_CONTROL_STATUS
- IPW_BASEBAND_CONTROL_STORE
- IPW_BASEBAND_POWER_DOWN
- IPW_BASEBAND_RX_FIFO_READ
- IPW_BASEBAND_TX_FIFO_WRITE
- IPW_BD_ALIGNMENT
- IPW_BD_QUEUE_LENGTH
- IPW_BD_QUEUE_W_R_MIN_SPARE
- IPW_BD_STATUS_TX_FRAME_802_11
- IPW_BD_STATUS_TX_FRAME_802_3
- IPW_BD_STATUS_TX_FRAME_COMMAND
- IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT
- IPW_BD_STATUS_TX_INTERRUPT_ENABLE
- IPW_BIT_GPIO_GPIO1_ENABLE
- IPW_BIT_GPIO_GPIO1_MASK
- IPW_BIT_GPIO_GPIO3_MASK
- IPW_BIT_GPIO_LED_OFF
- IPW_BIT_GPIO_RF_KILL
- IPW_BIT_HALT_RESET_OFF
- IPW_BIT_HALT_RESET_ON
- IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER
- IPW_BSS
- IPW_BYTES_FLOWINIT
- IPW_B_MODE
- IPW_CACHE_LINE_LENGTH_DEFAULT
- IPW_CARD_DISABLE_COMPLETE_WAIT
- IPW_CARD_DISABLE_PHY_OFF_COMPLETE_WAIT
- IPW_CCMP_CIPHER
- IPW_CFG_802_1x_ENABLE
- IPW_CFG_ANSWER_BCSSID_PROBE
- IPW_CFG_BSS_MASK
- IPW_CFG_BT_SIDEBAND_SIGNAL
- IPW_CFG_IBSS_AUTO_START
- IPW_CFG_IBSS_MASK
- IPW_CFG_LOOPBACK
- IPW_CFG_MONITOR
- IPW_CFG_PREAMBLE_AUTO
- IPW_CHANNEL_CONSOLE
- IPW_CHANNEL_DIALLER
- IPW_CHANNEL_RAS
- IPW_CKIP_CIPHER
- IPW_CMD
- IPW_CMD_ADAPTER_ADDRESS
- IPW_CMD_AIRONET_INFO
- IPW_CMD_AP_TX_POWER
- IPW_CMD_ASSOCIATE
- IPW_CMD_CARD_DISABLE
- IPW_CMD_CCKM_INFO
- IPW_CMD_CCX_VER_INFO
- IPW_CMD_COUNTRY_INFO
- IPW_CMD_DINO_CONFIG
- IPW_CMD_EXT_SUPPORTED_RATES
- IPW_CMD_FRAG_THRESHOLD
- IPW_CMD_HOST_COMPLETE
- IPW_CMD_IPW_PRE_POWER_DOWN
- IPW_CMD_LINKSYS_EOU_INFO
- IPW_CMD_MEASUREMENT
- IPW_CMD_MULTICAST_ADDRESS
- IPW_CMD_PORT_TYPE
- IPW_CMD_POWER_CAPABILITY
- IPW_CMD_POWER_DOWN
- IPW_CMD_POWER_MODE
- IPW_CMD_PRODUCTION_COMMAND
- IPW_CMD_QOS_PARAMETERS
- IPW_CMD_RETRY_LIMIT
- IPW_CMD_RSN_CAPABILITIES
- IPW_CMD_RTS_THRESHOLD
- IPW_CMD_RX_KEY
- IPW_CMD_SCAN_ABORT
- IPW_CMD_SCAN_REQUEST
- IPW_CMD_SCAN_REQUEST_EXT
- IPW_CMD_SEED_NUMBER
- IPW_CMD_SENSITIVITY_CALIB
- IPW_CMD_SET_CALIBRATION
- IPW_CMD_SSID
- IPW_CMD_SUPPORTED_CHANNELS
- IPW_CMD_SUPPORTED_RATES
- IPW_CMD_SYSTEM_CONFIG
- IPW_CMD_TGI_TX_KEY
- IPW_CMD_TPC_REPORT
- IPW_CMD_TX_FLUSH
- IPW_CMD_TX_POWER
- IPW_CMD_VAP_BEACON_TEMPLATE
- IPW_CMD_VAP_CELL_PWR_LIMIT
- IPW_CMD_VAP_CF_PARAM_SET
- IPW_CMD_VAP_CHANNEL_SWITCH
- IPW_CMD_VAP_DTIM_PERIOD
- IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT
- IPW_CMD_VAP_MANDATORY_CHANNELS
- IPW_CMD_VAP_QUIET_INTERVALS
- IPW_CMD_VAP_SET_BEACONING_STATE
- IPW_CMD_WEP_KEY
- IPW_CMD_WME_INFO
- IPW_COMMAND_POOL_SIZE
- IPW_CONTROL_LINE_CTS
- IPW_CONTROL_LINE_DCD
- IPW_CONTROL_LINE_DSR
- IPW_CONTROL_LINE_DTR
- IPW_CONTROL_LINE_RI
- IPW_CONTROL_LINE_RTS
- IPW_CSR_CIS_UPPER_BOUND
- IPW_CTS
- IPW_DATA_DOA_DEBUG_VALUE
- IPW_DEBUG
- IPW_DEBUG_ASSOC
- IPW_DEBUG_DROP
- IPW_DEBUG_ERROR
- IPW_DEBUG_FRAG
- IPW_DEBUG_FW
- IPW_DEBUG_FW_INFO
- IPW_DEBUG_HC
- IPW_DEBUG_INFO
- IPW_DEBUG_IO
- IPW_DEBUG_IOCTL
- IPW_DEBUG_ISR
- IPW_DEBUG_LED
- IPW_DEBUG_MANAGEMENT
- IPW_DEBUG_MERGE
- IPW_DEBUG_NOTIF
- IPW_DEBUG_ORD
- IPW_DEBUG_QOS
- IPW_DEBUG_RF_KILL
- IPW_DEBUG_RX
- IPW_DEBUG_SCAN
- IPW_DEBUG_STATE
- IPW_DEBUG_STATS
- IPW_DEBUG_TRACE
- IPW_DEBUG_TX
- IPW_DEBUG_WARNING
- IPW_DEBUG_WEP
- IPW_DEBUG_WX
- IPW_DL_ALL
- IPW_DL_ASSOC
- IPW_DL_DROP
- IPW_DL_ERROR
- IPW_DL_FRAG
- IPW_DL_FW
- IPW_DL_FW_ERRORS
- IPW_DL_FW_INFO
- IPW_DL_HC
- IPW_DL_HOST_COMMAND
- IPW_DL_INFO
- IPW_DL_IO
- IPW_DL_IOCTL
- IPW_DL_ISR
- IPW_DL_LED
- IPW_DL_MANAGE
- IPW_DL_MERGE
- IPW_DL_NONE
- IPW_DL_NOTIF
- IPW_DL_ORD
- IPW_DL_QOS
- IPW_DL_RF_KILL
- IPW_DL_RX
- IPW_DL_SCAN
- IPW_DL_STATE
- IPW_DL_STATS
- IPW_DL_TRACE
- IPW_DL_TX
- IPW_DL_UNINIT
- IPW_DL_WARNING
- IPW_DL_WEP
- IPW_DL_WX
- IPW_DMA_I_CB_BASE
- IPW_DMA_I_CURRENT_CB
- IPW_DMA_I_DMA_CONTROL
- IPW_DMA_O_CURRENT_CB
- IPW_DOMAIN_0_END
- IPW_DSR
- IPW_DURING_ATIM_WINDOW
- IPW_EEPROM_DATA
- IPW_EEPROM_DATA_SRAM_ADDRESS
- IPW_EEPROM_DATA_SRAM_SIZE
- IPW_EEPROM_IMAGE_SIZE
- IPW_EEPROM_LOAD_DISABLE
- IPW_EEPROM_UPPER_ADDRESS
- IPW_ERROR
- IPW_ERROR_ADDR
- IPW_ERROR_CODE
- IPW_ERROR_LOG
- IPW_EVENT_LOG
- IPW_EVENT_REG
- IPW_FILLER_40
- IPW_FILLER_41
- IPW_FILLER_42
- IPW_FILLER_43
- IPW_FILL_1
- IPW_FIRST_VARIABLE_LENGTH_ORDINAL
- IPW_FW_ERROR_ALLOC_FAIL
- IPW_FW_ERROR_BAD_CHECKSUM
- IPW_FW_ERROR_BAD_DATABASE
- IPW_FW_ERROR_BAD_PARAM
- IPW_FW_ERROR_DINO_ERROR
- IPW_FW_ERROR_DMA_STATUS
- IPW_FW_ERROR_DMA_UNDERRUN
- IPW_FW_ERROR_EEPROM_ERROR
- IPW_FW_ERROR_FAIL
- IPW_FW_ERROR_FATAL_ERROR
- IPW_FW_ERROR_MEMORY_OVERFLOW
- IPW_FW_ERROR_MEMORY_UNDERFLOW
- IPW_FW_ERROR_NMI_INTERRUPT
- IPW_FW_ERROR_OK
- IPW_FW_ERROR_SYSASSERT
- IPW_GATE_ADMA
- IPW_GATE_IDMA
- IPW_GATE_ODMA
- IPW_GET_PACKET_STYPE
- IPW_GP_CNTRL_BIT_CLOCK_READY
- IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY
- IPW_GP_CNTRL_BIT_INIT_DONE
- IPW_GP_CNTRL_RW
- IPW_G_MODE
- IPW_HEADER_802_11_SIZE
- IPW_HOST_EEPROM_DATA_SRAM_SIZE
- IPW_HOST_FW_INTERRUPT_AREA
- IPW_HOST_FW_INTERRUPT_AREA_END
- IPW_HOST_FW_SHARED_AREA0
- IPW_HOST_FW_SHARED_AREA0_END
- IPW_HOST_FW_SHARED_AREA1
- IPW_HOST_FW_SHARED_AREA1_END
- IPW_HOST_FW_SHARED_AREA2
- IPW_HOST_FW_SHARED_AREA2_END
- IPW_HOST_FW_SHARED_AREA3
- IPW_HOST_FW_SHARED_AREA3_END
- IPW_HW_STATE_DISABLED
- IPW_HW_STATE_ENABLED
- IPW_IBSS
- IPW_IBSS_11B_DEFAULT_MASK
- IPW_IBSS_MAC_HASH_SIZE
- IPW_INDIRECT_ADDR
- IPW_INDIRECT_ADDR_MASK
- IPW_INDIRECT_DATA
- IPW_INTA_BIT_BEACON_PERIOD_EXPIRED
- IPW_INTA_BIT_FATAL_ERROR
- IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE
- IPW_INTA_BIT_FW_INITIALIZATION_DONE
- IPW_INTA_BIT_PARITY_ERROR
- IPW_INTA_BIT_POWER_DOWN
- IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN
- IPW_INTA_BIT_RF_KILL_DONE
- IPW_INTA_BIT_RX_TRANSFER
- IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE
- IPW_INTA_BIT_STATUS_CHANGE
- IPW_INTA_BIT_TX_CMD_QUEUE
- IPW_INTA_BIT_TX_QUEUE_1
- IPW_INTA_BIT_TX_QUEUE_2
- IPW_INTA_BIT_TX_QUEUE_3
- IPW_INTA_BIT_TX_QUEUE_4
- IPW_INTA_MASK_ALL
- IPW_INTA_MASK_R
- IPW_INTA_NONE
- IPW_INTA_RW
- IPW_INTERNAL_CMD_EVENT
- IPW_INTERNAL_REGISTER_HALT_AND_RESET
- IPW_INTERRUPT_AREA_LOWER_BOUND
- IPW_INTERRUPT_MASK
- IPW_INVALID_STATION
- IPW_LAST_VARIABLE_LENGTH_ORDINAL
- IPW_LL_DEBUG
- IPW_MAX_80211_PAYLOAD_SIZE
- IPW_MAX_802_11_PAYLOAD_LENGTH
- IPW_MAX_ACCEPTABLE_RX_FRAME_LENGTH
- IPW_MAX_ACCEPTABLE_TX_FRAME_LENGTH
- IPW_MAX_BDS
- IPW_MAX_CONFIG_RETRIES
- IPW_MAX_RATES
- IPW_MAX_VAR_IE_LEN
- IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT
- IPW_MB_ROAMING_THRESHOLD_DEFAULT
- IPW_MB_ROAMING_THRESHOLD_MAX
- IPW_MB_ROAMING_THRESHOLD_MIN
- IPW_MB_SCAN_CANCEL_THRESHOLD
- IPW_MEM_FIXED_OVERRIDE
- IPW_MEM_HALT_AND_RESET
- IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1
- IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2
- IPW_MEM_HOST_SHARED_RX_BD_BASE
- IPW_MEM_HOST_SHARED_RX_BD_SIZE
- IPW_MEM_HOST_SHARED_RX_READ_INDEX
- IPW_MEM_HOST_SHARED_RX_STATUS_BASE
- IPW_MEM_HOST_SHARED_RX_WRITE_INDEX
- IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE
- IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE
- IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX
- IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX
- IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND
- IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND
- IPW_MIN_ACCEPTABLE_RX_FRAME_LENGTH
- IPW_MONITOR
- IPW_NIC_FATAL_ERROR
- IPW_NIC_SRAM_LOWER_BOUND
- IPW_NIC_SRAM_UPPER_BOUND
- IPW_NONE_CIPHER
- IPW_OFDM_LED
- IPW_ORDINALS_TABLE_0
- IPW_ORDINALS_TABLE_1
- IPW_ORDINALS_TABLE_2
- IPW_ORDINALS_TABLE_LOWER
- IPW_ORD_ANTENNA_DIVERSITY
- IPW_ORD_AP_HIGHEST_RATE
- IPW_ORD_AP_LIST_PTR
- IPW_ORD_ASSOCIATED_AP_PTR
- IPW_ORD_ATIM_WINDOW
- IPW_ORD_AUTH_TYPE
- IPW_ORD_AVAILABLE_AP_CNT
- IPW_ORD_BASIC_RATES
- IPW_ORD_BEACON_INTERVAL
- IPW_ORD_CAPABILITIES
- IPW_ORD_CARD_DISABLED
- IPW_ORD_CCA_RSSI
- IPW_ORD_COUNTRY_CHANNELS
- IPW_ORD_COUNTRY_CODE
- IPW_ORD_CURRENT_TX_RATE
- IPW_ORD_CURR_BSSID
- IPW_ORD_CURR_FREQ
- IPW_ORD_CURR_SSID
- IPW_ORD_DTIM_PERIOD
- IPW_ORD_EEPROM_IBSS_11B_CHANNELS
- IPW_ORD_EEPROM_SKU_CAPABILITY
- IPW_ORD_EEPROM_SRAM_DB_BLOCK_SIZE
- IPW_ORD_EEPROM_SRAM_DB_BLOCK_START_ADDRESS
- IPW_ORD_FRAGMENTATION_THRESHOLD
- IPW_ORD_HW_RF_SWITCH_STATE
- IPW_ORD_INT_MODE
- IPW_ORD_LAST_ASSN_TIME
- IPW_ORD_MAC_REVISION
- IPW_ORD_MAC_VERSION
- IPW_ORD_NIC_HIGHEST_RATE
- IPW_ORD_NIC_MANF_DATE_TIME
- IPW_ORD_OUR_FREQ
- IPW_ORD_PERS_DB_ADDR
- IPW_ORD_PERS_DB_LOCK
- IPW_ORD_PERS_DB_SIZE
- IPW_ORD_PORT_TYPE
- IPW_ORD_POWER_MGMT_INDEX
- IPW_ORD_POWER_MGMT_MODE
- IPW_ORD_PRINCETON_VERSION
- IPW_ORD_RADIO_TYPE
- IPW_ORD_RADIO_VERSION
- IPW_ORD_RESET_CNT
- IPW_ORD_RSSI_AT_ASSN
- IPW_ORD_RSSI_AVG_CURR
- IPW_ORD_RTC_TIME
- IPW_ORD_RTS_THRESHOLD
- IPW_ORD_SECURITY_NGOTIATION_RESULT
- IPW_ORD_SELF_TEST_STATUS
- IPW_ORD_STATION_TABLE
- IPW_ORD_STATION_TABLE_CNT
- IPW_ORD_STAT_ADAPTER_MAC
- IPW_ORD_STAT_AP_ASSNS
- IPW_ORD_STAT_ASSN_AP_BSSID
- IPW_ORD_STAT_ASSN_CAUSE1
- IPW_ORD_STAT_ASSN_CAUSE2
- IPW_ORD_STAT_ASSN_CAUSE3
- IPW_ORD_STAT_ASSN_CAUSE4
- IPW_ORD_STAT_ASSN_CAUSE5
- IPW_ORD_STAT_ASSN_CAUSE6
- IPW_ORD_STAT_ASSN_FAIL
- IPW_ORD_STAT_ASSN_RESP_FAIL
- IPW_ORD_STAT_ASSN_SSID
- IPW_ORD_STAT_AUTH_FAIL
- IPW_ORD_STAT_AUTH_RESP_FAIL
- IPW_ORD_STAT_AVAILABLE_AP_COUNT
- IPW_ORD_STAT_BASE
- IPW_ORD_STAT_COUNTRY_TEXT
- IPW_ORD_STAT_CURR_RSSI_DBM
- IPW_ORD_STAT_CURR_RSSI_RAW
- IPW_ORD_STAT_DEBUG
- IPW_ORD_STAT_EEPROM_UPDATE
- IPW_ORD_STAT_FIFO
- IPW_ORD_STAT_FRAG_TRESHOLD
- IPW_ORD_STAT_FULL_SCANS
- IPW_ORD_STAT_FW_DATE
- IPW_ORD_STAT_FW_VERSION
- IPW_ORD_STAT_FW_VER_NUM
- IPW_ORD_STAT_LINK_DOWN
- IPW_ORD_STAT_LINK_UP
- IPW_ORD_STAT_MANDATORY_BSSID
- IPW_ORD_STAT_MISSED_BEACONS
- IPW_ORD_STAT_NIC_BPA_NUM
- IPW_ORD_STAT_NULL_DATA
- IPW_ORD_STAT_PARTIAL_SCANS
- IPW_ORD_STAT_PERCENT_LINK_QUALITY
- IPW_ORD_STAT_PERCENT_MISSED_BCNS
- IPW_ORD_STAT_PERCENT_MISSED_BEACONS
- IPW_ORD_STAT_PERCENT_RETRIES
- IPW_ORD_STAT_PERCENT_TX_RETRIES
- IPW_ORD_STAT_PREFERRED_BSSID
- IPW_ORD_STAT_PSP_BCN_TIMEOUT
- IPW_ORD_STAT_PSP_NONDIR_TIMEOUT
- IPW_ORD_STAT_PSP_POLL_TIMEOUT
- IPW_ORD_STAT_PSP_RX_DTIMS
- IPW_ORD_STAT_PSP_RX_TIMS
- IPW_ORD_STAT_PSP_STATION_ID
- IPW_ORD_STAT_PSP_SUSPENSION
- IPW_ORD_STAT_RATE_LOG
- IPW_ORD_STAT_ROAM
- IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE
- IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX
- IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY
- IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS
- IPW_ORD_STAT_ROAM_CAUSE_RSSI
- IPW_ORD_STAT_ROAM_CAUSE_UNASSOC
- IPW_ORD_STAT_ROAM_INHIBIT
- IPW_ORD_STAT_ROAM_LOG
- IPW_ORD_STAT_RTC
- IPW_ORD_STAT_RTS_THRESHOLD
- IPW_ORD_STAT_RX_ABORT_AT_HOP
- IPW_ORD_STAT_RX_ABORT_LATE_DMA
- IPW_ORD_STAT_RX_ACK
- IPW_ORD_STAT_RX_ASSN
- IPW_ORD_STAT_RX_ASSN_RESP
- IPW_ORD_STAT_RX_ATIM
- IPW_ORD_STAT_RX_AUTH
- IPW_ORD_STAT_RX_BAD_SSID
- IPW_ORD_STAT_RX_BEACON
- IPW_ORD_STAT_RX_CFEND
- IPW_ORD_STAT_RX_CFEND_ACK
- IPW_ORD_STAT_RX_CTS
- IPW_ORD_STAT_RX_DEAUTH
- IPW_ORD_STAT_RX_DIR_DATA
- IPW_ORD_STAT_RX_DIR_DATA1
- IPW_ORD_STAT_RX_DIR_DATA11
- IPW_ORD_STAT_RX_DIR_DATA2
- IPW_ORD_STAT_RX_DIR_DATA22
- IPW_ORD_STAT_RX_DIR_DATA5_5
- IPW_ORD_STAT_RX_DISASSN
- IPW_ORD_STAT_RX_DUPLICATE
- IPW_ORD_STAT_RX_DUPLICATE1
- IPW_ORD_STAT_RX_DUPLICATE11
- IPW_ORD_STAT_RX_DUPLICATE2
- IPW_ORD_STAT_RX_DUPLICATE5_5
- IPW_ORD_STAT_RX_ERR_CRC
- IPW_ORD_STAT_RX_ERR_CRC1
- IPW_ORD_STAT_RX_ERR_CRC11
- IPW_ORD_STAT_RX_ERR_CRC2
- IPW_ORD_STAT_RX_ERR_CRC5_5
- IPW_ORD_STAT_RX_ERR_ICV
- IPW_ORD_STAT_RX_FRAG_AGEOUT
- IPW_ORD_STAT_RX_HOST
- IPW_ORD_STAT_RX_ICV_ERRORS
- IPW_ORD_STAT_RX_INVALID_PROTOCOL
- IPW_ORD_STAT_RX_MISSING_FRAG
- IPW_ORD_STAT_RX_NODIR_DATA
- IPW_ORD_STAT_RX_NODIR_DATA1
- IPW_ORD_STAT_RX_NODIR_DATA11
- IPW_ORD_STAT_RX_NODIR_DATA2
- IPW_ORD_STAT_RX_NODIR_DATA5_5
- IPW_ORD_STAT_RX_NO_BUFFER
- IPW_ORD_STAT_RX_NULL_DATA
- IPW_ORD_STAT_RX_ORPHAN_FRAG
- IPW_ORD_STAT_RX_ORPHAN_FRAME
- IPW_ORD_STAT_RX_POLL
- IPW_ORD_STAT_RX_PROBE
- IPW_ORD_STAT_RX_PROBE_RESP
- IPW_ORD_STAT_RX_REASSN
- IPW_ORD_STAT_RX_REASSN_RESP
- IPW_ORD_STAT_RX_RTS
- IPW_ORD_STAT_RX_TOTAL_BYTES
- IPW_ORD_STAT_SWEEP_TABLE
- IPW_ORD_STAT_TGH_ABORTED_SCANS
- IPW_ORD_STAT_TX_ABORT_AT_HOP
- IPW_ORD_STAT_TX_ABORT_LATE_DMA
- IPW_ORD_STAT_TX_ABORT_STX
- IPW_ORD_STAT_TX_ACK
- IPW_ORD_STAT_TX_ASSN
- IPW_ORD_STAT_TX_ASSN_RESP
- IPW_ORD_STAT_TX_ATIM
- IPW_ORD_STAT_TX_AUTH
- IPW_ORD_STAT_TX_BEACON
- IPW_ORD_STAT_TX_BPDU
- IPW_ORD_STAT_TX_CTS
- IPW_ORD_STAT_TX_CURR_RATE
- IPW_ORD_STAT_TX_DEAUTH
- IPW_ORD_STAT_TX_DIR_DATA
- IPW_ORD_STAT_TX_DIR_DATA1
- IPW_ORD_STAT_TX_DIR_DATA11
- IPW_ORD_STAT_TX_DIR_DATA2
- IPW_ORD_STAT_TX_DIR_DATA22
- IPW_ORD_STAT_TX_DIR_DATA5_5
- IPW_ORD_STAT_TX_DIR_DATA_B_1
- IPW_ORD_STAT_TX_DIR_DATA_B_11
- IPW_ORD_STAT_TX_DIR_DATA_B_2
- IPW_ORD_STAT_TX_DIR_DATA_B_5_5
- IPW_ORD_STAT_TX_DIR_DATA_G_1
- IPW_ORD_STAT_TX_DIR_DATA_G_11
- IPW_ORD_STAT_TX_DIR_DATA_G_12
- IPW_ORD_STAT_TX_DIR_DATA_G_18
- IPW_ORD_STAT_TX_DIR_DATA_G_2
- IPW_ORD_STAT_TX_DIR_DATA_G_24
- IPW_ORD_STAT_TX_DIR_DATA_G_36
- IPW_ORD_STAT_TX_DIR_DATA_G_48
- IPW_ORD_STAT_TX_DIR_DATA_G_54
- IPW_ORD_STAT_TX_DIR_DATA_G_5_5
- IPW_ORD_STAT_TX_DIR_DATA_G_6
- IPW_ORD_STAT_TX_DIR_DATA_G_9
- IPW_ORD_STAT_TX_DISASSN
- IPW_ORD_STAT_TX_DISASSN_FAIL
- IPW_ORD_STAT_TX_ERR_ACK
- IPW_ORD_STAT_TX_ERR_CTS
- IPW_ORD_STAT_TX_FAILURE
- IPW_ORD_STAT_TX_FAILURES
- IPW_ORD_STAT_TX_HOST_COMPLETE
- IPW_ORD_STAT_TX_HOST_REQUESTS
- IPW_ORD_STAT_TX_MAX_TRIES_IN_HOP
- IPW_ORD_STAT_TX_NODIR_DATA1
- IPW_ORD_STAT_TX_NODIR_DATA11
- IPW_ORD_STAT_TX_NODIR_DATA2
- IPW_ORD_STAT_TX_NODIR_DATA5_5
- IPW_ORD_STAT_TX_NON_DIR_DATA
- IPW_ORD_STAT_TX_NON_DIR_DATA_B_1
- IPW_ORD_STAT_TX_NON_DIR_DATA_B_11
- IPW_ORD_STAT_TX_NON_DIR_DATA_B_2
- IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_1
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_11
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_12
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_18
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_2
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_24
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_36
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_48
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_54
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_6
- IPW_ORD_STAT_TX_NON_DIR_DATA_G_9
- IPW_ORD_STAT_TX_PACKET
- IPW_ORD_STAT_TX_PACKET_ABORTED
- IPW_ORD_STAT_TX_PACKET_FAILURE
- IPW_ORD_STAT_TX_PACKET_SUCCESS
- IPW_ORD_STAT_TX_PROBE
- IPW_ORD_STAT_TX_PROBE_RESP
- IPW_ORD_STAT_TX_REASSN
- IPW_ORD_STAT_TX_REASSN_RESP
- IPW_ORD_STAT_TX_RETRIES
- IPW_ORD_STAT_TX_RETRY
- IPW_ORD_STAT_TX_RETRY1
- IPW_ORD_STAT_TX_RETRY11
- IPW_ORD_STAT_TX_RETRY2
- IPW_ORD_STAT_TX_RETRY5_5
- IPW_ORD_STAT_TX_RTS
- IPW_ORD_STAT_TX_TOTAL_BYTES
- IPW_ORD_STAT_UCODE_DATE
- IPW_ORD_STAT_UCODE_VERSION
- IPW_ORD_STEST_RESULTS_CUM
- IPW_ORD_STEST_RESULTS_CURR
- IPW_ORD_SUPPORTED_RATES
- IPW_ORD_SYS_BOOT_TIME
- IPW_ORD_TABLE_0_LAST
- IPW_ORD_TABLE_0_MASK
- IPW_ORD_TABLE_1_LAST
- IPW_ORD_TABLE_1_MASK
- IPW_ORD_TABLE_2_LAST
- IPW_ORD_TABLE_2_MASK
- IPW_ORD_TABLE_3_LAST
- IPW_ORD_TABLE_3_MASK
- IPW_ORD_TABLE_4_LAST
- IPW_ORD_TABLE_4_MASK
- IPW_ORD_TABLE_5_LAST
- IPW_ORD_TABLE_5_MASK
- IPW_ORD_TABLE_6_LAST
- IPW_ORD_TABLE_6_MASK
- IPW_ORD_TABLE_7_LAST
- IPW_ORD_TABLE_7_MASK
- IPW_ORD_TABLE_ID_MASK
- IPW_ORD_TABLE_VALUE_MASK
- IPW_ORD_TAB_1_ENTRY_SIZE
- IPW_ORD_UCODE_VERSION
- IPW_PACKET_RETRY_TIME
- IPW_PID
- IPW_PIN_CLRDTR
- IPW_PIN_CLRRTS
- IPW_PIN_SETDTR
- IPW_PIN_SETRTS
- IPW_POWER_AC
- IPW_POWER_AUTO
- IPW_POWER_BATTERY
- IPW_POWER_ENABLED
- IPW_POWER_INDEX_1
- IPW_POWER_INDEX_2
- IPW_POWER_INDEX_3
- IPW_POWER_INDEX_4
- IPW_POWER_INDEX_5
- IPW_POWER_LEVEL
- IPW_POWER_LIMIT
- IPW_POWER_MASK
- IPW_POWER_MODE_CAM
- IPW_PREPARE_POWER_DOWN_COMPLETE_WAIT
- IPW_PRIVACY_CAPABLE
- IPW_PRIV_GET_MODE
- IPW_PRIV_GET_POWER
- IPW_PRIV_GET_PREAMBLE
- IPW_PRIV_RESET
- IPW_PRIV_SET_MODE
- IPW_PRIV_SET_MONITOR
- IPW_PRIV_SET_POWER
- IPW_PRIV_SET_PREAMBLE
- IPW_PRIV_SW_RESET
- IPW_PROM_ALL_HEADER_ONLY
- IPW_PROM_CTL_HEADER_ONLY
- IPW_PROM_DATA_HEADER_ONLY
- IPW_PROM_MGMT_HEADER_ONLY
- IPW_PROM_NO_CTL
- IPW_PROM_NO_DATA
- IPW_PROM_NO_MGMT
- IPW_PROM_NO_RX
- IPW_PROM_NO_TX
- IPW_QUIET
- IPW_RATE_CAPABILITIES
- IPW_RATE_CONNECT
- IPW_READ_INT_REGISTER
- IPW_REAL_RATE_RX_PACKET_THRESHOLD
- IPW_REGISTER_DOMAIN1_END
- IPW_REG_AUTOINCREMENT_ADDRESS
- IPW_REG_AUTOINCREMENT_DATA
- IPW_REG_DOA_DEBUG_AREA_END
- IPW_REG_DOA_DEBUG_AREA_START
- IPW_REG_DOMAIN_0_OFFSET
- IPW_REG_DOMAIN_1_OFFSET
- IPW_REG_FW_COMPATIBILITY_VERSION
- IPW_REG_FW_TYPE
- IPW_REG_FW_VERSION
- IPW_REG_GPIO
- IPW_REG_GP_CNTRL
- IPW_REG_INDIRECT_ACCESS_ADDRESS
- IPW_REG_INDIRECT_ACCESS_DATA
- IPW_REG_INDIRECT_ADDR_MASK
- IPW_REG_INTA
- IPW_REG_INTA_MASK
- IPW_REG_RESET_REG
- IPW_REQUEST_ATIM
- IPW_RESET_REG
- IPW_RESET_REG_MASTER_DISABLED
- IPW_RESET_REG_STOP_MASTER
- IPW_RESET_REG_SW_RESET
- IPW_RFDS_TABLE_LOWER
- IPW_ROAMING
- IPW_RSSI_TO_DBM
- IPW_RXBULK_OFF
- IPW_RXBULK_ON
- IPW_RX_BD_BASE
- IPW_RX_BD_SIZE
- IPW_RX_BUF_SIZE
- IPW_RX_FRAME_SIZE
- IPW_RX_NIC_BUFFER_LENGTH
- IPW_RX_NOTIFICATION_SIZE
- IPW_RX_READ_INDEX
- IPW_RX_WRITE_INDEX
- IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN
- IPW_SCAN_ACTIVE_BROADCAST_SCAN
- IPW_SCAN_ACTIVE_DIRECT_SCAN
- IPW_SCAN_CHANNELS
- IPW_SCAN_CHECK_WATCHDOG
- IPW_SCAN_MIXED_CELL
- IPW_SCAN_NOASSOCIATE
- IPW_SCAN_PASSIVE
- IPW_SCAN_PASSIVE_FULL_DWELL_SCAN
- IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN
- IPW_SCAN_TYPES
- IPW_SHARED_LOWER_BOUND
- IPW_SHARED_SRAM_DMA_CONTROL
- IPW_SHARED_SRAM_SIZE
- IPW_SIO_HANDFLOW
- IPW_SIO_INIT
- IPW_SIO_POLL
- IPW_SIO_PURGE
- IPW_SIO_RXCTL
- IPW_SIO_SETCHARS
- IPW_SIO_SET_BAUD
- IPW_SIO_SET_LINE
- IPW_SIO_SET_PIN
- IPW_SRAM_READ_INT_REGISTER
- IPW_START_ORD_TAB_1
- IPW_START_ORD_TAB_2
- IPW_START_STANDBY
- IPW_STATE_ASSN_CHANGED
- IPW_STATE_ASSN_LOST
- IPW_STATE_ASSOCIATED
- IPW_STATE_COUNTRY_FOUND
- IPW_STATE_DISABLED
- IPW_STATE_ENTERED_PSP
- IPW_STATE_INITIALIZED
- IPW_STATE_LEFT_PSP
- IPW_STATE_POWER_DOWN
- IPW_STATE_RF_KILL
- IPW_STATE_SCANNING
- IPW_STATE_SCAN_COMPLETE
- IPW_STATION_TABLE_LOWER
- IPW_STATION_TABLE_UPPER
- IPW_STATS_INTERVAL
- IPW_STATUS_FLAG_CRC_ERROR
- IPW_STATUS_FLAG_DECRYPTED
- IPW_STATUS_FLAG_WEP_ENCRYPTED
- IPW_TKIP_CIPHER
- IPW_TTY_MAJOR
- IPW_TTY_MINORS
- IPW_TX_CMD_QUEUE_BD_BASE
- IPW_TX_CMD_QUEUE_BD_SIZE
- IPW_TX_CMD_QUEUE_READ_INDEX
- IPW_TX_CMD_QUEUE_WRITE_INDEX
- IPW_TX_POWER_AUTO
- IPW_TX_POWER_DEFAULT
- IPW_TX_POWER_ENHANCED
- IPW_TX_POWER_MAX
- IPW_TX_POWER_MAX_DBM
- IPW_TX_POWER_MIN
- IPW_TX_POWER_MIN_DBM
- IPW_TX_QUEUE_0_BD_BASE
- IPW_TX_QUEUE_0_BD_SIZE
- IPW_TX_QUEUE_0_READ_INDEX
- IPW_TX_QUEUE_0_WRITE_INDEX
- IPW_TX_QUEUE_1
- IPW_TX_QUEUE_1_BD_BASE
- IPW_TX_QUEUE_1_BD_SIZE
- IPW_TX_QUEUE_1_READ_INDEX
- IPW_TX_QUEUE_1_WRITE_INDEX
- IPW_TX_QUEUE_2
- IPW_TX_QUEUE_2_BD_BASE
- IPW_TX_QUEUE_2_BD_SIZE
- IPW_TX_QUEUE_2_READ_INDEX
- IPW_TX_QUEUE_2_WRITE_INDEX
- IPW_TX_QUEUE_3
- IPW_TX_QUEUE_3_BD_BASE
- IPW_TX_QUEUE_3_BD_SIZE
- IPW_TX_QUEUE_3_READ_INDEX
- IPW_TX_QUEUE_3_WRITE_INDEX
- IPW_TX_QUEUE_4
- IPW_TX_RATE_11MB
- IPW_TX_RATE_12MB
- IPW_TX_RATE_18MB
- IPW_TX_RATE_1MB
- IPW_TX_RATE_24MB
- IPW_TX_RATE_2MB
- IPW_TX_RATE_36MB
- IPW_TX_RATE_48MB
- IPW_TX_RATE_54MB
- IPW_TX_RATE_5MB
- IPW_TX_RATE_6MB
- IPW_TX_RATE_9MB
- IPW_VID
- IPW_WAIT
- IPW_WAIT_CLOCK_STABILIZATION_DELAY
- IPW_WAIT_RESET_ARC_COMPLETE_DELAY
- IPW_WAIT_RESET_MASTER_ASSERT_COMPLETE_DELAY
- IPW_WANTS_TO_SEND
- IPW_WARNING
- IPW_WEP104_CIPHER
- IPW_WEP40_CIPHER
- IPW_WHO_IS_AWAKE
- IPW_WPA_AP_ADDRESS
- IPW_WPA_CAPABILITIES
- IPW_WPA_LISTENINTERVAL
- IPXIPX_FEATURES
- IPX_CRTITF
- IPX_DLTITF
- IPX_FRAME_8022
- IPX_FRAME_8023
- IPX_FRAME_ETHERII
- IPX_FRAME_NONE
- IPX_FRAME_SNAP
- IPX_FRAME_TR_8022
- IPX_INTERNAL
- IPX_MAX_EPHEMERAL_SOCKET
- IPX_MAX_PPROP_HOPS
- IPX_MIN_EPHEMERAL_SOCKET
- IPX_MTU
- IPX_NODE_LEN
- IPX_NO_CHECKSUM
- IPX_PRIMARY
- IPX_ROUTE_NO_ROUTER
- IPX_RT_8022
- IPX_RT_BLUEBOOK
- IPX_RT_ROUTED
- IPX_RT_SNAP
- IPX_SKB_CB
- IPX_SPECIAL_NONE
- IPX_TYPE
- IPX_TYPE_NCP
- IPX_TYPE_PPROP
- IPX_TYPE_RIP
- IPX_TYPE_SAP
- IPX_TYPE_SPX
- IPX_TYPE_UNKNOWN
- IP_ACTION_ADD
- IP_ACTION_DEL
- IP_ADDRSTATE_ACQUIRING
- IP_ADDRSTATE_DEPRICATED
- IP_ADDRSTATE_DISABLING
- IP_ADDRSTATE_INVALID
- IP_ADDRSTATE_PREFERRED
- IP_ADDRSTATE_TENTATIVE
- IP_ADDRSTATE_UNCONFIGURED
- IP_ADDR_COUNT
- IP_ADDR_INDEX_REG_6
- IP_ADDR_INDEX_REG_E
- IP_ADDR_INDEX_REG_FUNC_0_PRI
- IP_ADDR_INDEX_REG_FUNC_0_SEC
- IP_ADDR_INDEX_REG_FUNC_1_PRI
- IP_ADDR_INDEX_REG_FUNC_1_SEC
- IP_ADDR_INDEX_REG_FUNC_2_PRI
- IP_ADDR_INDEX_REG_FUNC_2_SEC
- IP_ADDR_INDEX_REG_FUNC_3_PRI
- IP_ADDR_INDEX_REG_FUNC_3_SEC
- IP_ADDR_INDEX_REG_MASK
- IP_ADDR_INDEX_REG_OFFSET_MASK
- IP_ADDR_LEN
- IP_ADDR_REGISTERED
- IP_ADD_MEMBERSHIP
- IP_ADD_SOURCE_MEMBERSHIP
- IP_ADD_STATS
- IP_ALIG_DEF
- IP_ARG
- IP_BASE
- IP_BASE_INSTANCE
- IP_BIND_ADDRESS_NO_PORT
- IP_BLOCK_SOURCE
- IP_CE
- IP_CHECKSUM
- IP_CMSG_CHECKSUM
- IP_CMSG_ORIGDSTADDR
- IP_CMSG_PASSSEC
- IP_CMSG_PKTINFO
- IP_CMSG_RECVFRAGSIZE
- IP_CMSG_RECVOPTS
- IP_CMSG_RETOPTS
- IP_CMSG_TOS
- IP_CMSG_TTL
- IP_CONF
- IP_CONFIG_TOV
- IP_CSUM_OFF
- IP_CT_DIR_MAX
- IP_CT_DIR_ORIGINAL
- IP_CT_DIR_REPLY
- IP_CT_ESTABLISHED
- IP_CT_ESTABLISHED_REPLY
- IP_CT_EXP_CHALLENGE_ACK
- IP_CT_IS_REPLY
- IP_CT_NEW
- IP_CT_NEW_REPLY
- IP_CT_NUMBER
- IP_CT_RELATED
- IP_CT_RELATED_REPLY
- IP_CT_TCP_FLAG_BE_LIBERAL
- IP_CT_TCP_FLAG_CLOSE_INIT
- IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED
- IP_CT_TCP_FLAG_MAXACK_SET
- IP_CT_TCP_FLAG_SACK_PERM
- IP_CT_TCP_FLAG_WINDOW_SCALE
- IP_CT_TCP_SIMULTANEOUS_OPEN
- IP_CT_UNTRACKED
- IP_DEFAULT_MULTICAST_LOOP
- IP_DEFAULT_MULTICAST_TTL
- IP_DEFRAG_AF_PACKET
- IP_DEFRAG_CALL_RA_CHAIN
- IP_DEFRAG_CONNTRACK_BRIDGE_IN
- IP_DEFRAG_CONNTRACK_IN
- IP_DEFRAG_CONNTRACK_OUT
- IP_DEFRAG_LOCAL_DELIVER
- IP_DEFRAG_MACVLAN
- IP_DEFRAG_VS_FWD
- IP_DEFRAG_VS_IN
- IP_DEFRAG_VS_OUT
- IP_DF
- IP_DISCOVERY
- IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK
- IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT
- IP_DROP_MEMBERSHIP
- IP_DROP_SOURCE_MEMBERSHIP
- IP_DST_OFF
- IP_ECN_clear
- IP_ECN_decapsulate
- IP_ECN_set_ce
- IP_ECN_set_ect1
- IP_ETHERTYPE
- IP_FMT
- IP_FRAG
- IP_FRAGEMENT
- IP_FRAG_SHIFT
- IP_FRAG_TIME
- IP_FREEBIND
- IP_HASHBITS
- IP_HASHMAX
- IP_HDRINCL
- IP_HDR_ALIGN
- IP_HDR_LEN
- IP_HDR_LEN_G
- IP_HDR_LEN_M
- IP_HDR_LEN_S
- IP_HDR_LEN_V
- IP_HDR_OFFSET
- IP_HEADER_ALIGNMENT_PADDING
- IP_HEADER_OFFSET
- IP_IDENTS_SZ
- IP_INC_STATS
- IP_IPSEC_POLICY
- IP_KEY_LEN
- IP_MASK
- IP_MAX_MTU
- IP_MC
- IP_MCAST_MAC
- IP_MF
- IP_MINTTL
- IP_MSFILTER
- IP_MSFILTER_SIZE
- IP_MSGSIZE
- IP_MTU
- IP_MTU_DISCOVER
- IP_MULTICAST_ALL
- IP_MULTICAST_IF
- IP_MULTICAST_LOOP
- IP_MULTICAST_TTL
- IP_NAME_SZ
- IP_NLPID
- IP_NODEFRAG
- IP_OCTAL_ID_SPACE_VECTOR
- IP_OCTAL_NB_BLOCKS
- IP_OFFSET
- IP_OPTIONS
- IP_OP_SP
- IP_ORIGDSTADDR
- IP_PASSSEC
- IP_PEND0_6_63
- IP_PKTINFO
- IP_PKTOPTIONS
- IP_PMTUDISC_DO
- IP_PMTUDISC_DONT
- IP_PMTUDISC_INTERFACE
- IP_PMTUDISC_OMIT
- IP_PMTUDISC_PROBE
- IP_PMTUDISC_WANT
- IP_PROTOCOL_TCP
- IP_PROTOCOL_UDP
- IP_PROTO_FULL_MASK
- IP_PROTO_OFF
- IP_RECVERR
- IP_RECVFRAGSIZE
- IP_RECVOPTS
- IP_RECVORIGDSTADDR
- IP_RECVRETOPTS
- IP_RECVTOS
- IP_RECVTTL
- IP_RELATIVE_BRANCH_OPCODE
- IP_RELATIVE_CALL_OPCODE
- IP_RELATIVE_PREDICT_OPCODE
- IP_REPLY_ARG_NOSRCCHECK
- IP_RETOPTS
- IP_ROUTER_ALERT
- IP_RST_USB3OTG
- IP_RST_USB3OTGPHY_POR
- IP_SEL_MIX_PAD_REG
- IP_SEL_PAD_0_9_REG
- IP_SEL_PAD_10_19_REG
- IP_SEL_PAD_20_29_REG
- IP_SEL_PAD_30_39_REG
- IP_SEL_PAD_40_49_REG
- IP_SEL_PAD_50_59_REG
- IP_SEL_PAD_60_69_REG
- IP_SEL_PAD_70_79_REG
- IP_SEL_PAD_80_89_REG
- IP_SEL_PAD_90_99_REG
- IP_SET_BITMAP_STORED_TIMEOUT
- IP_SET_EMIT_CREATE
- IP_SET_HASH_WITH_MARKMASK
- IP_SET_HASH_WITH_MULTI
- IP_SET_HASH_WITH_NET0
- IP_SET_HASH_WITH_NETMASK
- IP_SET_HASH_WITH_NETS
- IP_SET_HASH_WITH_NETS_PACKED
- IP_SET_HASH_WITH_PROTO
- IP_SET_INC
- IP_SET_INIT_KEXT
- IP_SET_INIT_UEXT
- IP_SET_LIST_DEFAULT_SIZE
- IP_SET_LIST_MAX_SIZE
- IP_SET_LIST_MIN_SIZE
- IP_SET_MODULE_DESC
- IP_SET_OP_GET_BYINDEX
- IP_SET_OP_GET_BYNAME
- IP_SET_OP_GET_FNAME
- IP_SET_OP_VERSION
- IP_SET_PROTO_UNDEF
- IP_SFBLOCK
- IP_SFLSIZE
- IP_SR
- IP_SRC_OFF
- IP_STATE_MASK
- IP_STATE_SHIFT
- IP_TG_CONFIG
- IP_TNL_HASH_BITS
- IP_TNL_HASH_SIZE
- IP_TOS
- IP_TO_CP
- IP_TRANSPARENT
- IP_TRUNK_VERS
- IP_TTL
- IP_TUNNEL_INFO_BRIDGE
- IP_TUNNEL_INFO_IPV6
- IP_TUNNEL_INFO_TX
- IP_TUNNEL_KEY_IPV4_PAD
- IP_TUNNEL_KEY_IPV4_PAD_LEN
- IP_TUNNEL_KEY_SIZE
- IP_TUNNEL_OPTS_MAX
- IP_UNBLOCK_SOURCE
- IP_UNICAST_IF
- IP_UNITY
- IP_UPD_PO_STATS
- IP_USB_PD_REVISION_ID
- IP_USER_FLOW
- IP_V4
- IP_V4_LEN
- IP_V6
- IP_V6_LEN
- IP_VERSION_4
- IP_VERSION_6
- IP_VERSION_IPV4
- IP_VERSION_IPV6
- IP_VS_ADDRSTRLEN
- IP_VS_APP_MAX_PORTS
- IP_VS_APP_TYPE_FTP
- IP_VS_BASE_CTL
- IP_VS_BUG
- IP_VS_CONN_F_BACKUP_MASK
- IP_VS_CONN_F_BACKUP_UPD_MASK
- IP_VS_CONN_F_BYPASS
- IP_VS_CONN_F_DEST_MASK
- IP_VS_CONN_F_DROUTE
- IP_VS_CONN_F_FWD_MASK
- IP_VS_CONN_F_HASHED
- IP_VS_CONN_F_INACTIVE
- IP_VS_CONN_F_IN_SEQ
- IP_VS_CONN_F_LOCALNODE
- IP_VS_CONN_F_MASQ
- IP_VS_CONN_F_NFCT
- IP_VS_CONN_F_NOOUTPUT
- IP_VS_CONN_F_NO_CPORT
- IP_VS_CONN_F_ONE_PACKET
- IP_VS_CONN_F_OUT_SEQ
- IP_VS_CONN_F_SEQ_MASK
- IP_VS_CONN_F_SYNC
- IP_VS_CONN_F_TEMPLATE
- IP_VS_CONN_F_TUNNEL
- IP_VS_CONN_F_TUNNEL_TYPE_GRE
- IP_VS_CONN_F_TUNNEL_TYPE_GUE
- IP_VS_CONN_F_TUNNEL_TYPE_IPIP
- IP_VS_CONN_F_TUNNEL_TYPE_MAX
- IP_VS_CTPL_S_ASSURED
- IP_VS_CTPL_S_LAST
- IP_VS_CTPL_S_NONE
- IP_VS_DBG
- IP_VS_DBG_ADDR
- IP_VS_DBG_BUF
- IP_VS_DBG_PKT
- IP_VS_DBG_RL
- IP_VS_DBG_RL_PKT
- IP_VS_DEBUG_CALLID
- IP_VS_DEST_F_AVAILABLE
- IP_VS_DEST_F_OVERLOAD
- IP_VS_DEST_TRASH_PERIOD
- IP_VS_DFWD_METHOD
- IP_VS_DH_TAB_BITS
- IP_VS_DH_TAB_MASK
- IP_VS_DH_TAB_SIZE
- IP_VS_DIR_INPUT
- IP_VS_DIR_INPUT_ONLY
- IP_VS_DIR_LAST
- IP_VS_DIR_OUTPUT
- IP_VS_ERR_BUF
- IP_VS_ERR_RL
- IP_VS_FTP_ACTIVE
- IP_VS_FTP_EPRT
- IP_VS_FTP_EPSV
- IP_VS_FTP_PASV
- IP_VS_FTP_PORT
- IP_VS_FWD_METHOD
- IP_VS_HDR_ICMP
- IP_VS_HDR_INVERSE
- IP_VS_ICMP_S_LAST
- IP_VS_ICMP_S_NORMAL
- IP_VS_IFNAME_MAXLEN
- IP_VS_INIT_HASH_TABLE
- IP_VS_LBLCR_TAB_BITS
- IP_VS_LBLCR_TAB_MASK
- IP_VS_LBLCR_TAB_SIZE
- IP_VS_LBLC_TAB_BITS
- IP_VS_LBLC_TAB_MASK
- IP_VS_LBLC_TAB_SIZE
- IP_VS_MH_TAB_BITS
- IP_VS_MH_TAB_INDEX
- IP_VS_MH_TAB_SIZE
- IP_VS_PEDATA_MAXLEN
- IP_VS_PENAME_MAXLEN
- IP_VS_PROTO_HASH
- IP_VS_PROTO_TAB_SIZE
- IP_VS_RTAB_BITS
- IP_VS_RTAB_MASK
- IP_VS_RTAB_SIZE
- IP_VS_RT_MODE_CONNECT
- IP_VS_RT_MODE_KNOWN_NH
- IP_VS_RT_MODE_LOCAL
- IP_VS_RT_MODE_NON_LOCAL
- IP_VS_RT_MODE_RDR
- IP_VS_RT_MODE_TUNNEL
- IP_VS_SCHEDNAME_MAXLEN
- IP_VS_SCTP_ABORT
- IP_VS_SCTP_COOKIE_ACK
- IP_VS_SCTP_COOKIE_ECHO
- IP_VS_SCTP_DATA
- IP_VS_SCTP_ERROR
- IP_VS_SCTP_EVENT_LAST
- IP_VS_SCTP_INIT
- IP_VS_SCTP_INIT_ACK
- IP_VS_SCTP_MAX_RTO
- IP_VS_SCTP_SHUTDOWN
- IP_VS_SCTP_SHUTDOWN_ACK
- IP_VS_SCTP_SHUTDOWN_COMPLETE
- IP_VS_SCTP_S_CLOSED
- IP_VS_SCTP_S_COOKIE
- IP_VS_SCTP_S_COOKIE_ECHOED
- IP_VS_SCTP_S_COOKIE_REPLIED
- IP_VS_SCTP_S_COOKIE_SENT
- IP_VS_SCTP_S_COOKIE_WAIT
- IP_VS_SCTP_S_ESTABLISHED
- IP_VS_SCTP_S_INIT
- IP_VS_SCTP_S_INIT1
- IP_VS_SCTP_S_LAST
- IP_VS_SCTP_S_NONE
- IP_VS_SCTP_S_REJECTED
- IP_VS_SCTP_S_SHUTDOWN_ACK_SENT
- IP_VS_SCTP_S_SHUTDOWN_RECEIVED
- IP_VS_SCTP_S_SHUTDOWN_SENT
- IP_VS_SHOW_STATS_COUNTER
- IP_VS_SH_TAB_BITS
- IP_VS_SH_TAB_MASK
- IP_VS_SH_TAB_SIZE
- IP_VS_SO_GET_DAEMON
- IP_VS_SO_GET_DEST
- IP_VS_SO_GET_DESTS
- IP_VS_SO_GET_INFO
- IP_VS_SO_GET_MAX
- IP_VS_SO_GET_SERVICE
- IP_VS_SO_GET_SERVICES
- IP_VS_SO_GET_TIMEOUT
- IP_VS_SO_GET_VERSION
- IP_VS_SO_SET_ADD
- IP_VS_SO_SET_ADDDEST
- IP_VS_SO_SET_DEL
- IP_VS_SO_SET_DELDEST
- IP_VS_SO_SET_EDIT
- IP_VS_SO_SET_EDITDEST
- IP_VS_SO_SET_FLUSH
- IP_VS_SO_SET_INSERT
- IP_VS_SO_SET_LIST
- IP_VS_SO_SET_MAX
- IP_VS_SO_SET_NONE
- IP_VS_SO_SET_RESTORE
- IP_VS_SO_SET_SAVE
- IP_VS_SO_SET_STARTDAEMON
- IP_VS_SO_SET_STOPDAEMON
- IP_VS_SO_SET_TIMEOUT
- IP_VS_SO_SET_ZERO
- IP_VS_STATE_BACKUP
- IP_VS_STATE_MASTER
- IP_VS_STATE_NONE
- IP_VS_SVC_F_HASHED
- IP_VS_SVC_F_ONEPACKET
- IP_VS_SVC_F_PERSISTENT
- IP_VS_SVC_F_SCHED1
- IP_VS_SVC_F_SCHED2
- IP_VS_SVC_F_SCHED3
- IP_VS_SVC_F_SCHED_MH_FALLBACK
- IP_VS_SVC_F_SCHED_MH_PORT
- IP_VS_SVC_F_SCHED_SH_FALLBACK
- IP_VS_SVC_F_SCHED_SH_PORT
- IP_VS_SVC_TAB_BITS
- IP_VS_SVC_TAB_MASK
- IP_VS_SVC_TAB_SIZE
- IP_VS_SYNC_GROUP
- IP_VS_SYNC_PORT
- IP_VS_TCP_S_CLOSE
- IP_VS_TCP_S_CLOSE_WAIT
- IP_VS_TCP_S_ESTABLISHED
- IP_VS_TCP_S_FIN_WAIT
- IP_VS_TCP_S_LAST
- IP_VS_TCP_S_LAST_ACK
- IP_VS_TCP_S_LISTEN
- IP_VS_TCP_S_NONE
- IP_VS_TCP_S_SYNACK
- IP_VS_TCP_S_SYN_RECV
- IP_VS_TCP_S_SYN_SENT
- IP_VS_TCP_S_TIME_WAIT
- IP_VS_TUNNEL_ENCAP_FLAG_CSUM
- IP_VS_TUNNEL_ENCAP_FLAG_NOCSUM
- IP_VS_TUNNEL_ENCAP_FLAG_REMCSUM
- IP_VS_UDP_S_LAST
- IP_VS_UDP_S_NORMAL
- IP_VS_VERSION_CODE
- IP_VS_ZERO_STATS_COUNTER
- IP_XFRM_POLICY
- IPos
- IPv6_ADDR_LEN
- IQ31244_7SEG_0
- IQ31244_7SEG_1
- IQ31244_BATT_STAT
- IQ31244_ROTARY_SW
- IQ31244_UART
- IQ80321_7SEG_0
- IQ80321_7SEG_1
- IQ80321_BATT_STAT
- IQ80321_ROTARY_SW
- IQ80321_UART
- IQCONST
- IQFRM_DES
- IQINV
- IQI_CONFIG_DFLT
- IQI_CON_BRI_DFLT
- IQI_PXF_CONF_DFLT
- IQI_SAT_GAIN_DFLT
- IQK_ADDA_REG_NUM
- IQK_BB_REG_NUM
- IQK_BB_REG_NUM_92C
- IQK_BB_REG_NUM_92D
- IQK_BB_REG_NUM_MAX
- IQK_BB_REG_NUM_test
- IQK_DEFERRED_TIME_8723B
- IQK_DELAY_TIME
- IQK_DELAY_TIME_8723B
- IQK_DELAY_TIME_88E
- IQK_MAC_REG_NUM
- IQK_MATRIX_REGS_SETTING
- IQK_MATRIX_REG_NUM
- IQK_MATRIX_SETTINGS_NUM
- IQK_Matrix_REG_NUM
- IQK_Matrix_Settings_NUM
- IQK_Matrix_Settings_NUM_92D
- IQK_SET_CLEAR
- IQK_SET_SEGMENT_IQK
- IQK_THRESHOLD
- IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED
- IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED
- IQM_AF_ADC_CONF_ADC_SIGN__B
- IQM_AF_ADC_CONF_ADC_SIGN__M
- IQM_AF_ADC_CONF_ADC_SIGN__PRE
- IQM_AF_ADC_CONF_ADC_SIGN__W
- IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED
- IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL
- IQM_AF_ADC_CONF_BITREVERSE_ADC__B
- IQM_AF_ADC_CONF_BITREVERSE_ADC__M
- IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE
- IQM_AF_ADC_CONF_BITREVERSE_ADC__W
- IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED
- IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL
- IQM_AF_ADC_CONF_BITREVERSE_NSSI__B
- IQM_AF_ADC_CONF_BITREVERSE_NSSI__M
- IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE
- IQM_AF_ADC_CONF_BITREVERSE_NSSI__W
- IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED
- IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL
- IQM_AF_ADC_CONF_BITREVERSE_NSSR__B
- IQM_AF_ADC_CONF_BITREVERSE_NSSR__M
- IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE
- IQM_AF_ADC_CONF_BITREVERSE_NSSR__W
- IQM_AF_ADC_CONF__A
- IQM_AF_ADC_CONF__M
- IQM_AF_ADC_CONF__PRE
- IQM_AF_ADC_CONF__W
- IQM_AF_AGC_IF__A
- IQM_AF_AGC_IF__M
- IQM_AF_AGC_IF__PRE
- IQM_AF_AGC_IF__W
- IQM_AF_AGC_RF__A
- IQM_AF_AGC_RF__M
- IQM_AF_AGC_RF__PRE
- IQM_AF_AGC_RF__W
- IQM_AF_AMUX_SIGNAL2ADC
- IQM_AF_AMUX__A
- IQM_AF_AMUX__M
- IQM_AF_AMUX__PRE
- IQM_AF_AMUX__W
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG
- IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS
- IQM_AF_CLKNEG_CLKNEGDATA__B
- IQM_AF_CLKNEG_CLKNEGDATA__M
- IQM_AF_CLKNEG_CLKNEGDATA__PRE
- IQM_AF_CLKNEG_CLKNEGDATA__W
- IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG
- IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS
- IQM_AF_CLKNEG_CLKNEGPEAK__B
- IQM_AF_CLKNEG_CLKNEGPEAK__M
- IQM_AF_CLKNEG_CLKNEGPEAK__PRE
- IQM_AF_CLKNEG_CLKNEGPEAK__W
- IQM_AF_CLKNEG__A
- IQM_AF_CLKNEG__M
- IQM_AF_CLKNEG__PRE
- IQM_AF_CLKNEG__W
- IQM_AF_CLP_CLIP__A
- IQM_AF_CLP_CLIP__M
- IQM_AF_CLP_CLIP__PRE
- IQM_AF_CLP_CLIP__W
- IQM_AF_CLP_LEN_ATV
- IQM_AF_CLP_LEN_QAM_B_256
- IQM_AF_CLP_LEN_QAM_B_64
- IQM_AF_CLP_LEN__A
- IQM_AF_CLP_LEN__M
- IQM_AF_CLP_LEN__PRE
- IQM_AF_CLP_LEN__W
- IQM_AF_CLP_TH_ATV
- IQM_AF_CLP_TH_QAM_B_256
- IQM_AF_CLP_TH_QAM_B_64
- IQM_AF_CLP_TH__A
- IQM_AF_CLP_TH__M
- IQM_AF_CLP_TH__PRE
- IQM_AF_CLP_TH__W
- IQM_AF_COMM_EXEC_ACTIVE
- IQM_AF_COMM_EXEC_HOLD
- IQM_AF_COMM_EXEC_STOP
- IQM_AF_COMM_EXEC__A
- IQM_AF_COMM_EXEC__M
- IQM_AF_COMM_EXEC__PRE
- IQM_AF_COMM_EXEC__W
- IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B
- IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M
- IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE
- IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W
- IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B
- IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M
- IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE
- IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W
- IQM_AF_COMM_INT_MSK__A
- IQM_AF_COMM_INT_MSK__M
- IQM_AF_COMM_INT_MSK__PRE
- IQM_AF_COMM_INT_MSK__W
- IQM_AF_COMM_INT_REQ__A
- IQM_AF_COMM_INT_REQ__M
- IQM_AF_COMM_INT_REQ__PRE
- IQM_AF_COMM_INT_REQ__W
- IQM_AF_COMM_INT_STA_CLP_INT_STA__B
- IQM_AF_COMM_INT_STA_CLP_INT_STA__M
- IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE
- IQM_AF_COMM_INT_STA_CLP_INT_STA__W
- IQM_AF_COMM_INT_STA_SNS_INT_STA__B
- IQM_AF_COMM_INT_STA_SNS_INT_STA__M
- IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE
- IQM_AF_COMM_INT_STA_SNS_INT_STA__W
- IQM_AF_COMM_INT_STA__A
- IQM_AF_COMM_INT_STA__M
- IQM_AF_COMM_INT_STA__PRE
- IQM_AF_COMM_INT_STA__W
- IQM_AF_COMM_INT_STM_CLP_INT_STA__B
- IQM_AF_COMM_INT_STM_CLP_INT_STA__M
- IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE
- IQM_AF_COMM_INT_STM_CLP_INT_STA__W
- IQM_AF_COMM_INT_STM_SNS_INT_STA__B
- IQM_AF_COMM_INT_STM_SNS_INT_STA__M
- IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE
- IQM_AF_COMM_INT_STM_SNS_INT_STA__W
- IQM_AF_COMM_INT_STM__A
- IQM_AF_COMM_INT_STM__M
- IQM_AF_COMM_INT_STM__PRE
- IQM_AF_COMM_INT_STM__W
- IQM_AF_COMM_MB_CTL_CTL_OFF
- IQM_AF_COMM_MB_CTL_CTL_ON
- IQM_AF_COMM_MB_CTL__B
- IQM_AF_COMM_MB_CTL__M
- IQM_AF_COMM_MB_CTL__PRE
- IQM_AF_COMM_MB_CTL__W
- IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT
- IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT
- IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT
- IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT
- IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT
- IQM_AF_COMM_MB_MUX_CTRL__B
- IQM_AF_COMM_MB_MUX_CTRL__M
- IQM_AF_COMM_MB_MUX_CTRL__PRE
- IQM_AF_COMM_MB_MUX_CTRL__W
- IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT
- IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT
- IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT
- IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT
- IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT
- IQM_AF_COMM_MB_MUX_OBS__B
- IQM_AF_COMM_MB_MUX_OBS__M
- IQM_AF_COMM_MB_MUX_OBS__PRE
- IQM_AF_COMM_MB_MUX_OBS__W
- IQM_AF_COMM_MB_OBS_OBS_OFF
- IQM_AF_COMM_MB_OBS_OBS_ON
- IQM_AF_COMM_MB_OBS__B
- IQM_AF_COMM_MB_OBS__M
- IQM_AF_COMM_MB_OBS__PRE
- IQM_AF_COMM_MB_OBS__W
- IQM_AF_COMM_MB__A
- IQM_AF_COMM_MB__M
- IQM_AF_COMM_MB__PRE
- IQM_AF_COMM_MB__W
- IQM_AF_DCF_BYPASS_ACTIVE
- IQM_AF_DCF_BYPASS_BYPASS
- IQM_AF_DCF_BYPASS__A
- IQM_AF_DCF_BYPASS__M
- IQM_AF_DCF_BYPASS__PRE
- IQM_AF_DCF_BYPASS__W
- IQM_AF_FDB_SEL__A
- IQM_AF_FDB_SEL__M
- IQM_AF_FDB_SEL__PRE
- IQM_AF_FDB_SEL__W
- IQM_AF_INC_BYPASS__A
- IQM_AF_INC_LCT__A
- IQM_AF_INVEXT__A
- IQM_AF_INVEXT__M
- IQM_AF_INVEXT__PRE
- IQM_AF_INVEXT__W
- IQM_AF_MON_IN0__A
- IQM_AF_MON_IN0__M
- IQM_AF_MON_IN0__PRE
- IQM_AF_MON_IN0__W
- IQM_AF_MON_IN1__A
- IQM_AF_MON_IN1__M
- IQM_AF_MON_IN1__PRE
- IQM_AF_MON_IN1__W
- IQM_AF_MON_IN2__A
- IQM_AF_MON_IN2__M
- IQM_AF_MON_IN2__PRE
- IQM_AF_MON_IN2__W
- IQM_AF_MON_IN3__A
- IQM_AF_MON_IN3__M
- IQM_AF_MON_IN3__PRE
- IQM_AF_MON_IN3__W
- IQM_AF_MON_IN4__A
- IQM_AF_MON_IN4__M
- IQM_AF_MON_IN4__PRE
- IQM_AF_MON_IN4__W
- IQM_AF_MON_IN5__A
- IQM_AF_MON_IN5__M
- IQM_AF_MON_IN5__PRE
- IQM_AF_MON_IN5__W
- IQM_AF_MON_IN_MUX__A
- IQM_AF_MON_IN_MUX__M
- IQM_AF_MON_IN_MUX__PRE
- IQM_AF_MON_IN_MUX__W
- IQM_AF_MON_IN_VAL__A
- IQM_AF_MON_IN_VAL__M
- IQM_AF_MON_IN_VAL__PRE
- IQM_AF_MON_IN_VAL__W
- IQM_AF_PDREF_ATV
- IQM_AF_PDREF_QAM_B_256
- IQM_AF_PDREF_QAM_B_64
- IQM_AF_PDREF__A
- IQM_AF_PDREF__M
- IQM_AF_PDREF__PRE
- IQM_AF_PDREF__W
- IQM_AF_PGA_GAIN__A
- IQM_AF_PGA_GAIN__M
- IQM_AF_PGA_GAIN__PRE
- IQM_AF_PGA_GAIN__W
- IQM_AF_PHASE0__A
- IQM_AF_PHASE0__M
- IQM_AF_PHASE0__PRE
- IQM_AF_PHASE0__W
- IQM_AF_PHASE1__A
- IQM_AF_PHASE1__M
- IQM_AF_PHASE1__PRE
- IQM_AF_PHASE1__W
- IQM_AF_PHASE2__A
- IQM_AF_PHASE2__M
- IQM_AF_PHASE2__PRE
- IQM_AF_PHASE2__W
- IQM_AF_SCU_PHASE__A
- IQM_AF_SCU_PHASE__M
- IQM_AF_SCU_PHASE__PRE
- IQM_AF_SCU_PHASE__W
- IQM_AF_SNS_LEN_ATV
- IQM_AF_SNS_LEN_QAM_B_256
- IQM_AF_SNS_LEN_QAM_B_64
- IQM_AF_SNS_LEN__A
- IQM_AF_SNS_LEN__M
- IQM_AF_SNS_LEN__PRE
- IQM_AF_SNS_LEN__W
- IQM_AF_SNS_SENSE__A
- IQM_AF_SNS_SENSE__M
- IQM_AF_SNS_SENSE__PRE
- IQM_AF_SNS_SENSE__W
- IQM_AF_START_LOCK__A
- IQM_AF_START_LOCK__M
- IQM_AF_START_LOCK__PRE
- IQM_AF_START_LOCK__W
- IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE
- IQM_AF_STDBY_STDBY_ADC_A1_STANDBY
- IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE
- IQM_AF_STDBY_STDBY_ADC_A2_STANDBY
- IQM_AF_STDBY_STDBY_ADC_STANDBY
- IQM_AF_STDBY_STDBY_ADC__B
- IQM_AF_STDBY_STDBY_ADC__M
- IQM_AF_STDBY_STDBY_ADC__PRE
- IQM_AF_STDBY_STDBY_ADC__W
- IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE
- IQM_AF_STDBY_STDBY_AMP_A1_STANDBY
- IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE
- IQM_AF_STDBY_STDBY_AMP_A2_STANDBY
- IQM_AF_STDBY_STDBY_AMP_STANDBY
- IQM_AF_STDBY_STDBY_AMP__B
- IQM_AF_STDBY_STDBY_AMP__M
- IQM_AF_STDBY_STDBY_AMP__PRE
- IQM_AF_STDBY_STDBY_AMP__W
- IQM_AF_STDBY_STDBY_BIAS_ACTIVE
- IQM_AF_STDBY_STDBY_BIAS_STANDBY
- IQM_AF_STDBY_STDBY_BIAS__B
- IQM_AF_STDBY_STDBY_BIAS__M
- IQM_AF_STDBY_STDBY_BIAS__PRE
- IQM_AF_STDBY_STDBY_BIAS__W
- IQM_AF_STDBY_STDBY_PD_A1_ACTIVE
- IQM_AF_STDBY_STDBY_PD_A1_STANDBY
- IQM_AF_STDBY_STDBY_PD_A2_ACTIVE
- IQM_AF_STDBY_STDBY_PD_A2_STANDBY
- IQM_AF_STDBY_STDBY_PD_STANDBY
- IQM_AF_STDBY_STDBY_PD__B
- IQM_AF_STDBY_STDBY_PD__M
- IQM_AF_STDBY_STDBY_PD__PRE
- IQM_AF_STDBY_STDBY_PD__W
- IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE
- IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE
- IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_IF__B
- IQM_AF_STDBY_STDBY_TAGC_IF__M
- IQM_AF_STDBY_STDBY_TAGC_IF__PRE
- IQM_AF_STDBY_STDBY_TAGC_IF__W
- IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE
- IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE
- IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY
- IQM_AF_STDBY_STDBY_TAGC_RF__B
- IQM_AF_STDBY_STDBY_TAGC_RF__M
- IQM_AF_STDBY_STDBY_TAGC_RF__PRE
- IQM_AF_STDBY_STDBY_TAGC_RF__W
- IQM_AF_STDBY__A
- IQM_AF_STDBY__M
- IQM_AF_STDBY__PRE
- IQM_AF_STDBY__W
- IQM_AF_SYNC_SEL__A
- IQM_AF_SYNC_SEL__M
- IQM_AF_SYNC_SEL__PRE
- IQM_AF_SYNC_SEL__W
- IQM_AF_TST_AFEMAIN__A
- IQM_AF_TST_AFEMAIN__M
- IQM_AF_TST_AFEMAIN__PRE
- IQM_AF_TST_AFEMAIN__W
- IQM_AF_UPD_SEL__A
- IQM_CF_ADJ_SEL__A
- IQM_CF_ADJ_SEL__M
- IQM_CF_ADJ_SEL__PRE
- IQM_CF_ADJ_SEL__W
- IQM_CF_AMP__A
- IQM_CF_AMP__M
- IQM_CF_AMP__PRE
- IQM_CF_AMP__W
- IQM_CF_BYPASSDET__A
- IQM_CF_CLP_VAL__A
- IQM_CF_COMM_EXEC_ACTIVE
- IQM_CF_COMM_EXEC_HOLD
- IQM_CF_COMM_EXEC_STOP
- IQM_CF_COMM_EXEC__A
- IQM_CF_COMM_EXEC__M
- IQM_CF_COMM_EXEC__PRE
- IQM_CF_COMM_EXEC__W
- IQM_CF_COMM_INT_MSK_PM__B
- IQM_CF_COMM_INT_MSK_PM__M
- IQM_CF_COMM_INT_MSK_PM__PRE
- IQM_CF_COMM_INT_MSK_PM__W
- IQM_CF_COMM_INT_MSK__A
- IQM_CF_COMM_INT_MSK__M
- IQM_CF_COMM_INT_MSK__PRE
- IQM_CF_COMM_INT_MSK__W
- IQM_CF_COMM_INT_REQ__A
- IQM_CF_COMM_INT_REQ__M
- IQM_CF_COMM_INT_REQ__PRE
- IQM_CF_COMM_INT_REQ__W
- IQM_CF_COMM_INT_STA_PM__B
- IQM_CF_COMM_INT_STA_PM__M
- IQM_CF_COMM_INT_STA_PM__PRE
- IQM_CF_COMM_INT_STA_PM__W
- IQM_CF_COMM_INT_STA__A
- IQM_CF_COMM_INT_STA__M
- IQM_CF_COMM_INT_STA__PRE
- IQM_CF_COMM_INT_STA__W
- IQM_CF_COMM_INT_STM_PM__B
- IQM_CF_COMM_INT_STM_PM__M
- IQM_CF_COMM_INT_STM_PM__PRE
- IQM_CF_COMM_INT_STM_PM__W
- IQM_CF_COMM_INT_STM__A
- IQM_CF_COMM_INT_STM__M
- IQM_CF_COMM_INT_STM__PRE
- IQM_CF_COMM_INT_STM__W
- IQM_CF_COMM_MB_CTL_CTL_OFF
- IQM_CF_COMM_MB_CTL_CTL_ON
- IQM_CF_COMM_MB_CTL__B
- IQM_CF_COMM_MB_CTL__M
- IQM_CF_COMM_MB_CTL__PRE
- IQM_CF_COMM_MB_CTL__W
- IQM_CF_COMM_MB_OBS_OBS_OFF
- IQM_CF_COMM_MB_OBS_OBS_ON
- IQM_CF_COMM_MB_OBS__B
- IQM_CF_COMM_MB_OBS__M
- IQM_CF_COMM_MB_OBS__PRE
- IQM_CF_COMM_MB_OBS__W
- IQM_CF_COMM_MB__A
- IQM_CF_COMM_MB__M
- IQM_CF_COMM_MB__PRE
- IQM_CF_COMM_MB__W
- IQM_CF_DATATH__A
- IQM_CF_DET_LCT__A
- IQM_CF_DS_ENA__A
- IQM_CF_MIDTAP_IM__B
- IQM_CF_MIDTAP_IM__M
- IQM_CF_MIDTAP_IM__PRE
- IQM_CF_MIDTAP_IM__W
- IQM_CF_MIDTAP_RE__B
- IQM_CF_MIDTAP_RE__M
- IQM_CF_MIDTAP_RE__PRE
- IQM_CF_MIDTAP_RE__W
- IQM_CF_MIDTAP__A
- IQM_CF_MIDTAP__M
- IQM_CF_MIDTAP__PRE
- IQM_CF_MIDTAP__W
- IQM_CF_OUT_ENA_ATV__B
- IQM_CF_OUT_ENA_ATV__M
- IQM_CF_OUT_ENA_ATV__PRE
- IQM_CF_OUT_ENA_ATV__W
- IQM_CF_OUT_ENA_OFDM__M
- IQM_CF_OUT_ENA_QAM__B
- IQM_CF_OUT_ENA_QAM__M
- IQM_CF_OUT_ENA_QAM__PRE
- IQM_CF_OUT_ENA_QAM__W
- IQM_CF_OUT_ENA_VSB__B
- IQM_CF_OUT_ENA_VSB__M
- IQM_CF_OUT_ENA_VSB__PRE
- IQM_CF_OUT_ENA_VSB__W
- IQM_CF_OUT_ENA__A
- IQM_CF_OUT_ENA__M
- IQM_CF_OUT_ENA__PRE
- IQM_CF_OUT_ENA__W
- IQM_CF_PKDTH__A
- IQM_CF_POW_MEAS_LEN_QAM_B_256
- IQM_CF_POW_MEAS_LEN_QAM_B_64
- IQM_CF_POW_MEAS_LEN__A
- IQM_CF_POW_MEAS_LEN__M
- IQM_CF_POW_MEAS_LEN__PRE
- IQM_CF_POW_MEAS_LEN__W
- IQM_CF_POW__A
- IQM_CF_POW__M
- IQM_CF_POW__PRE
- IQM_CF_POW__W
- IQM_CF_SCALE_SH__A
- IQM_CF_SCALE_SH__M
- IQM_CF_SCALE_SH__PRE
- IQM_CF_SCALE_SH__W
- IQM_CF_SCALE__A
- IQM_CF_SCALE__M
- IQM_CF_SCALE__PRE
- IQM_CF_SCALE__W
- IQM_CF_SYMMETRIC_IM__B
- IQM_CF_SYMMETRIC_IM__M
- IQM_CF_SYMMETRIC_IM__PRE
- IQM_CF_SYMMETRIC_IM__W
- IQM_CF_SYMMETRIC_RE__B
- IQM_CF_SYMMETRIC_RE__M
- IQM_CF_SYMMETRIC_RE__PRE
- IQM_CF_SYMMETRIC_RE__W
- IQM_CF_SYMMETRIC__A
- IQM_CF_SYMMETRIC__M
- IQM_CF_SYMMETRIC__PRE
- IQM_CF_SYMMETRIC__W
- IQM_CF_TAP_IM0__A
- IQM_CF_TAP_IM0__M
- IQM_CF_TAP_IM0__PRE
- IQM_CF_TAP_IM0__W
- IQM_CF_TAP_IM10__A
- IQM_CF_TAP_IM10__M
- IQM_CF_TAP_IM10__PRE
- IQM_CF_TAP_IM10__W
- IQM_CF_TAP_IM11__A
- IQM_CF_TAP_IM11__M
- IQM_CF_TAP_IM11__PRE
- IQM_CF_TAP_IM11__W
- IQM_CF_TAP_IM12__A
- IQM_CF_TAP_IM12__M
- IQM_CF_TAP_IM12__PRE
- IQM_CF_TAP_IM12__W
- IQM_CF_TAP_IM13__A
- IQM_CF_TAP_IM13__M
- IQM_CF_TAP_IM13__PRE
- IQM_CF_TAP_IM13__W
- IQM_CF_TAP_IM14__A
- IQM_CF_TAP_IM14__M
- IQM_CF_TAP_IM14__PRE
- IQM_CF_TAP_IM14__W
- IQM_CF_TAP_IM15__A
- IQM_CF_TAP_IM15__M
- IQM_CF_TAP_IM15__PRE
- IQM_CF_TAP_IM15__W
- IQM_CF_TAP_IM16__A
- IQM_CF_TAP_IM16__M
- IQM_CF_TAP_IM16__PRE
- IQM_CF_TAP_IM16__W
- IQM_CF_TAP_IM17__A
- IQM_CF_TAP_IM17__M
- IQM_CF_TAP_IM17__PRE
- IQM_CF_TAP_IM17__W
- IQM_CF_TAP_IM18__A
- IQM_CF_TAP_IM18__M
- IQM_CF_TAP_IM18__PRE
- IQM_CF_TAP_IM18__W
- IQM_CF_TAP_IM19__A
- IQM_CF_TAP_IM19__M
- IQM_CF_TAP_IM19__PRE
- IQM_CF_TAP_IM19__W
- IQM_CF_TAP_IM1__A
- IQM_CF_TAP_IM1__M
- IQM_CF_TAP_IM1__PRE
- IQM_CF_TAP_IM1__W
- IQM_CF_TAP_IM20__A
- IQM_CF_TAP_IM20__M
- IQM_CF_TAP_IM20__PRE
- IQM_CF_TAP_IM20__W
- IQM_CF_TAP_IM21__A
- IQM_CF_TAP_IM21__M
- IQM_CF_TAP_IM21__PRE
- IQM_CF_TAP_IM21__W
- IQM_CF_TAP_IM22__A
- IQM_CF_TAP_IM22__M
- IQM_CF_TAP_IM22__PRE
- IQM_CF_TAP_IM22__W
- IQM_CF_TAP_IM23__A
- IQM_CF_TAP_IM23__M
- IQM_CF_TAP_IM23__PRE
- IQM_CF_TAP_IM23__W
- IQM_CF_TAP_IM24__A
- IQM_CF_TAP_IM24__M
- IQM_CF_TAP_IM24__PRE
- IQM_CF_TAP_IM24__W
- IQM_CF_TAP_IM25__A
- IQM_CF_TAP_IM25__M
- IQM_CF_TAP_IM25__PRE
- IQM_CF_TAP_IM25__W
- IQM_CF_TAP_IM26__A
- IQM_CF_TAP_IM26__M
- IQM_CF_TAP_IM26__PRE
- IQM_CF_TAP_IM26__W
- IQM_CF_TAP_IM27__A
- IQM_CF_TAP_IM27__M
- IQM_CF_TAP_IM27__PRE
- IQM_CF_TAP_IM27__W
- IQM_CF_TAP_IM2__A
- IQM_CF_TAP_IM2__M
- IQM_CF_TAP_IM2__PRE
- IQM_CF_TAP_IM2__W
- IQM_CF_TAP_IM3__A
- IQM_CF_TAP_IM3__M
- IQM_CF_TAP_IM3__PRE
- IQM_CF_TAP_IM3__W
- IQM_CF_TAP_IM4__A
- IQM_CF_TAP_IM4__M
- IQM_CF_TAP_IM4__PRE
- IQM_CF_TAP_IM4__W
- IQM_CF_TAP_IM5__A
- IQM_CF_TAP_IM5__M
- IQM_CF_TAP_IM5__PRE
- IQM_CF_TAP_IM5__W
- IQM_CF_TAP_IM6__A
- IQM_CF_TAP_IM6__M
- IQM_CF_TAP_IM6__PRE
- IQM_CF_TAP_IM6__W
- IQM_CF_TAP_IM7__A
- IQM_CF_TAP_IM7__M
- IQM_CF_TAP_IM7__PRE
- IQM_CF_TAP_IM7__W
- IQM_CF_TAP_IM8__A
- IQM_CF_TAP_IM8__M
- IQM_CF_TAP_IM8__PRE
- IQM_CF_TAP_IM8__W
- IQM_CF_TAP_IM9__A
- IQM_CF_TAP_IM9__M
- IQM_CF_TAP_IM9__PRE
- IQM_CF_TAP_IM9__W
- IQM_CF_TAP_RE0__A
- IQM_CF_TAP_RE0__M
- IQM_CF_TAP_RE0__PRE
- IQM_CF_TAP_RE0__W
- IQM_CF_TAP_RE10__A
- IQM_CF_TAP_RE10__M
- IQM_CF_TAP_RE10__PRE
- IQM_CF_TAP_RE10__W
- IQM_CF_TAP_RE11__A
- IQM_CF_TAP_RE11__M
- IQM_CF_TAP_RE11__PRE
- IQM_CF_TAP_RE11__W
- IQM_CF_TAP_RE12__A
- IQM_CF_TAP_RE12__M
- IQM_CF_TAP_RE12__PRE
- IQM_CF_TAP_RE12__W
- IQM_CF_TAP_RE13__A
- IQM_CF_TAP_RE13__M
- IQM_CF_TAP_RE13__PRE
- IQM_CF_TAP_RE13__W
- IQM_CF_TAP_RE14__A
- IQM_CF_TAP_RE14__M
- IQM_CF_TAP_RE14__PRE
- IQM_CF_TAP_RE14__W
- IQM_CF_TAP_RE15__A
- IQM_CF_TAP_RE15__M
- IQM_CF_TAP_RE15__PRE
- IQM_CF_TAP_RE15__W
- IQM_CF_TAP_RE16__A
- IQM_CF_TAP_RE16__M
- IQM_CF_TAP_RE16__PRE
- IQM_CF_TAP_RE16__W
- IQM_CF_TAP_RE17__A
- IQM_CF_TAP_RE17__M
- IQM_CF_TAP_RE17__PRE
- IQM_CF_TAP_RE17__W
- IQM_CF_TAP_RE18__A
- IQM_CF_TAP_RE18__M
- IQM_CF_TAP_RE18__PRE
- IQM_CF_TAP_RE18__W
- IQM_CF_TAP_RE19__A
- IQM_CF_TAP_RE19__M
- IQM_CF_TAP_RE19__PRE
- IQM_CF_TAP_RE19__W
- IQM_CF_TAP_RE1__A
- IQM_CF_TAP_RE1__M
- IQM_CF_TAP_RE1__PRE
- IQM_CF_TAP_RE1__W
- IQM_CF_TAP_RE20__A
- IQM_CF_TAP_RE20__M
- IQM_CF_TAP_RE20__PRE
- IQM_CF_TAP_RE20__W
- IQM_CF_TAP_RE21__A
- IQM_CF_TAP_RE21__M
- IQM_CF_TAP_RE21__PRE
- IQM_CF_TAP_RE21__W
- IQM_CF_TAP_RE22__A
- IQM_CF_TAP_RE22__M
- IQM_CF_TAP_RE22__PRE
- IQM_CF_TAP_RE22__W
- IQM_CF_TAP_RE23__A
- IQM_CF_TAP_RE23__M
- IQM_CF_TAP_RE23__PRE
- IQM_CF_TAP_RE23__W
- IQM_CF_TAP_RE24__A
- IQM_CF_TAP_RE24__M
- IQM_CF_TAP_RE24__PRE
- IQM_CF_TAP_RE24__W
- IQM_CF_TAP_RE25__A
- IQM_CF_TAP_RE25__M
- IQM_CF_TAP_RE25__PRE
- IQM_CF_TAP_RE25__W
- IQM_CF_TAP_RE26__A
- IQM_CF_TAP_RE26__M
- IQM_CF_TAP_RE26__PRE
- IQM_CF_TAP_RE26__W
- IQM_CF_TAP_RE27__A
- IQM_CF_TAP_RE27__M
- IQM_CF_TAP_RE27__PRE
- IQM_CF_TAP_RE27__W
- IQM_CF_TAP_RE2__A
- IQM_CF_TAP_RE2__M
- IQM_CF_TAP_RE2__PRE
- IQM_CF_TAP_RE2__W
- IQM_CF_TAP_RE3__A
- IQM_CF_TAP_RE3__M
- IQM_CF_TAP_RE3__PRE
- IQM_CF_TAP_RE3__W
- IQM_CF_TAP_RE4__A
- IQM_CF_TAP_RE4__M
- IQM_CF_TAP_RE4__PRE
- IQM_CF_TAP_RE4__W
- IQM_CF_TAP_RE5__A
- IQM_CF_TAP_RE5__M
- IQM_CF_TAP_RE5__PRE
- IQM_CF_TAP_RE5__W
- IQM_CF_TAP_RE6__A
- IQM_CF_TAP_RE6__M
- IQM_CF_TAP_RE6__PRE
- IQM_CF_TAP_RE6__W
- IQM_CF_TAP_RE7__A
- IQM_CF_TAP_RE7__M
- IQM_CF_TAP_RE7__PRE
- IQM_CF_TAP_RE7__W
- IQM_CF_TAP_RE8__A
- IQM_CF_TAP_RE8__M
- IQM_CF_TAP_RE8__PRE
- IQM_CF_TAP_RE8__W
- IQM_CF_TAP_RE9__A
- IQM_CF_TAP_RE9__M
- IQM_CF_TAP_RE9__PRE
- IQM_CF_TAP_RE9__W
- IQM_CF_WND_LEN__A
- IQM_COMM_EXEC_ACTIVE
- IQM_COMM_EXEC_B_ACTIVE
- IQM_COMM_EXEC_B_STOP
- IQM_COMM_EXEC_HOLD
- IQM_COMM_EXEC_STOP
- IQM_COMM_EXEC__A
- IQM_COMM_EXEC__M
- IQM_COMM_EXEC__PRE
- IQM_COMM_EXEC__W
- IQM_COMM_INT_MSK__A
- IQM_COMM_INT_MSK__M
- IQM_COMM_INT_MSK__PRE
- IQM_COMM_INT_MSK__W
- IQM_COMM_INT_REQ_AF_REQ__B
- IQM_COMM_INT_REQ_AF_REQ__M
- IQM_COMM_INT_REQ_AF_REQ__PRE
- IQM_COMM_INT_REQ_AF_REQ__W
- IQM_COMM_INT_REQ_CF_REQ__B
- IQM_COMM_INT_REQ_CF_REQ__M
- IQM_COMM_INT_REQ_CF_REQ__PRE
- IQM_COMM_INT_REQ_CF_REQ__W
- IQM_COMM_INT_REQ__A
- IQM_COMM_INT_REQ__M
- IQM_COMM_INT_REQ__PRE
- IQM_COMM_INT_REQ__W
- IQM_COMM_INT_STA__A
- IQM_COMM_INT_STA__M
- IQM_COMM_INT_STA__PRE
- IQM_COMM_INT_STA__W
- IQM_COMM_INT_STM__A
- IQM_COMM_INT_STM__M
- IQM_COMM_INT_STM__PRE
- IQM_COMM_INT_STM__W
- IQM_COMM_MB__A
- IQM_COMM_MB__M
- IQM_COMM_MB__PRE
- IQM_COMM_MB__W
- IQM_FD_COMM_EXEC_ACTIVE
- IQM_FD_COMM_EXEC_HOLD
- IQM_FD_COMM_EXEC_STOP
- IQM_FD_COMM_EXEC__A
- IQM_FD_COMM_EXEC__M
- IQM_FD_COMM_EXEC__PRE
- IQM_FD_COMM_EXEC__W
- IQM_FD_COMM_MB_CTL_CTL_OFF
- IQM_FD_COMM_MB_CTL_CTL_ON
- IQM_FD_COMM_MB_CTL__B
- IQM_FD_COMM_MB_CTL__M
- IQM_FD_COMM_MB_CTL__PRE
- IQM_FD_COMM_MB_CTL__W
- IQM_FD_COMM_MB_OBS_OBS_OFF
- IQM_FD_COMM_MB_OBS_OBS_ON
- IQM_FD_COMM_MB_OBS__B
- IQM_FD_COMM_MB_OBS__M
- IQM_FD_COMM_MB_OBS__PRE
- IQM_FD_COMM_MB_OBS__W
- IQM_FD_COMM_MB__A
- IQM_FD_COMM_MB__M
- IQM_FD_COMM_MB__PRE
- IQM_FD_COMM_MB__W
- IQM_FD_RATESEL__A
- IQM_FS_ADJ_SEL_B_OFF
- IQM_FS_ADJ_SEL_B_QAM
- IQM_FS_ADJ_SEL_B_VSB
- IQM_FS_ADJ_SEL_OFF
- IQM_FS_ADJ_SEL_QAM
- IQM_FS_ADJ_SEL_VSB
- IQM_FS_ADJ_SEL__A
- IQM_FS_ADJ_SEL__M
- IQM_FS_ADJ_SEL__PRE
- IQM_FS_ADJ_SEL__W
- IQM_FS_COMM_EXEC_ACTIVE
- IQM_FS_COMM_EXEC_HOLD
- IQM_FS_COMM_EXEC_STOP
- IQM_FS_COMM_EXEC__A
- IQM_FS_COMM_EXEC__M
- IQM_FS_COMM_EXEC__PRE
- IQM_FS_COMM_EXEC__W
- IQM_FS_COMM_MB_CTL_CTL_OFF
- IQM_FS_COMM_MB_CTL_CTL_ON
- IQM_FS_COMM_MB_CTL__B
- IQM_FS_COMM_MB_CTL__M
- IQM_FS_COMM_MB_CTL__PRE
- IQM_FS_COMM_MB_CTL__W
- IQM_FS_COMM_MB_OBS_OBS_OFF
- IQM_FS_COMM_MB_OBS_OBS_ON
- IQM_FS_COMM_MB_OBS__B
- IQM_FS_COMM_MB_OBS__M
- IQM_FS_COMM_MB_OBS__PRE
- IQM_FS_COMM_MB_OBS__W
- IQM_FS_COMM_MB__A
- IQM_FS_COMM_MB__M
- IQM_FS_COMM_MB__PRE
- IQM_FS_COMM_MB__W
- IQM_FS_RATE_HI__A
- IQM_FS_RATE_HI__M
- IQM_FS_RATE_HI__PRE
- IQM_FS_RATE_HI__W
- IQM_FS_RATE_LO__A
- IQM_FS_RATE_LO__M
- IQM_FS_RATE_LO__PRE
- IQM_FS_RATE_LO__W
- IQM_FS_RATE_OFS_HI__A
- IQM_FS_RATE_OFS_HI__M
- IQM_FS_RATE_OFS_HI__PRE
- IQM_FS_RATE_OFS_HI__W
- IQM_FS_RATE_OFS_LO__A
- IQM_FS_RATE_OFS_LO__M
- IQM_FS_RATE_OFS_LO__PRE
- IQM_FS_RATE_OFS_LO__W
- IQM_RC_ADJ_SEL_B_OFF
- IQM_RC_ADJ_SEL_B_QAM
- IQM_RC_ADJ_SEL_B_VSB
- IQM_RC_ADJ_SEL_OFF
- IQM_RC_ADJ_SEL_QAM
- IQM_RC_ADJ_SEL_VSB
- IQM_RC_ADJ_SEL__A
- IQM_RC_ADJ_SEL__M
- IQM_RC_ADJ_SEL__PRE
- IQM_RC_ADJ_SEL__W
- IQM_RC_COMM_EXEC_ACTIVE
- IQM_RC_COMM_EXEC_HOLD
- IQM_RC_COMM_EXEC_STOP
- IQM_RC_COMM_EXEC__A
- IQM_RC_COMM_EXEC__M
- IQM_RC_COMM_EXEC__PRE
- IQM_RC_COMM_EXEC__W
- IQM_RC_COMM_MB_CTL_CTL_OFF
- IQM_RC_COMM_MB_CTL_CTL_ON
- IQM_RC_COMM_MB_CTL__B
- IQM_RC_COMM_MB_CTL__M
- IQM_RC_COMM_MB_CTL__PRE
- IQM_RC_COMM_MB_CTL__W
- IQM_RC_COMM_MB_OBS_OBS_OFF
- IQM_RC_COMM_MB_OBS_OBS_ON
- IQM_RC_COMM_MB_OBS__B
- IQM_RC_COMM_MB_OBS__M
- IQM_RC_COMM_MB_OBS__PRE
- IQM_RC_COMM_MB_OBS__W
- IQM_RC_COMM_MB__A
- IQM_RC_COMM_MB__M
- IQM_RC_COMM_MB__PRE
- IQM_RC_COMM_MB__W
- IQM_RC_CROUT_ENA_ENA__B
- IQM_RC_CROUT_ENA_ENA__M
- IQM_RC_CROUT_ENA_ENA__PRE
- IQM_RC_CROUT_ENA_ENA__W
- IQM_RC_CROUT_ENA__A
- IQM_RC_CROUT_ENA__M
- IQM_RC_CROUT_ENA__PRE
- IQM_RC_CROUT_ENA__W
- IQM_RC_RATE_HI__A
- IQM_RC_RATE_HI__M
- IQM_RC_RATE_HI__PRE
- IQM_RC_RATE_HI__W
- IQM_RC_RATE_LO__A
- IQM_RC_RATE_LO__M
- IQM_RC_RATE_LO__PRE
- IQM_RC_RATE_LO__W
- IQM_RC_RATE_OFS_HI__A
- IQM_RC_RATE_OFS_HI__M
- IQM_RC_RATE_OFS_HI__PRE
- IQM_RC_RATE_OFS_HI__W
- IQM_RC_RATE_OFS_LO__A
- IQM_RC_RATE_OFS_LO__M
- IQM_RC_RATE_OFS_LO__PRE
- IQM_RC_RATE_OFS_LO__W
- IQM_RC_STRETCH_ATV
- IQM_RC_STRETCH_QAM_B_256
- IQM_RC_STRETCH_QAM_B_64
- IQM_RC_STRETCH__A
- IQM_RC_STRETCH__M
- IQM_RC_STRETCH__PRE
- IQM_RC_STRETCH__W
- IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF
- IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON
- IQM_RT_ACTIVE_ACTIVE_CR__B
- IQM_RT_ACTIVE_ACTIVE_CR__M
- IQM_RT_ACTIVE_ACTIVE_CR__PRE
- IQM_RT_ACTIVE_ACTIVE_CR__W
- IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF
- IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON
- IQM_RT_ACTIVE_ACTIVE_RT__B
- IQM_RT_ACTIVE_ACTIVE_RT__M
- IQM_RT_ACTIVE_ACTIVE_RT__PRE
- IQM_RT_ACTIVE_ACTIVE_RT__W
- IQM_RT_ACTIVE__A
- IQM_RT_ACTIVE__M
- IQM_RT_ACTIVE__PRE
- IQM_RT_ACTIVE__W
- IQM_RT_COMM_EXEC_ACTIVE
- IQM_RT_COMM_EXEC_HOLD
- IQM_RT_COMM_EXEC_STOP
- IQM_RT_COMM_EXEC__A
- IQM_RT_COMM_EXEC__M
- IQM_RT_COMM_EXEC__PRE
- IQM_RT_COMM_EXEC__W
- IQM_RT_COMM_MB_CTL_CTL_OFF
- IQM_RT_COMM_MB_CTL_CTL_ON
- IQM_RT_COMM_MB_CTL__B
- IQM_RT_COMM_MB_CTL__M
- IQM_RT_COMM_MB_CTL__PRE
- IQM_RT_COMM_MB_CTL__W
- IQM_RT_COMM_MB_OBS_OBS_OFF
- IQM_RT_COMM_MB_OBS_OBS_ON
- IQM_RT_COMM_MB_OBS__B
- IQM_RT_COMM_MB_OBS__M
- IQM_RT_COMM_MB_OBS__PRE
- IQM_RT_COMM_MB_OBS__W
- IQM_RT_COMM_MB__A
- IQM_RT_COMM_MB__M
- IQM_RT_COMM_MB__PRE
- IQM_RT_COMM_MB__W
- IQM_RT_DELAY__A
- IQM_RT_DELAY__M
- IQM_RT_DELAY__PRE
- IQM_RT_DELAY__W
- IQM_RT_LO_INCR_FM
- IQM_RT_LO_INCR_MN
- IQM_RT_LO_INCR__A
- IQM_RT_LO_INCR__M
- IQM_RT_LO_INCR__PRE
- IQM_RT_LO_INCR__W
- IQM_RT_LP_BP__A
- IQM_RT_LP_BP__M
- IQM_RT_LP_BP__PRE
- IQM_RT_LP_BP__W
- IQM_RT_RAM_DLY__B
- IQM_RT_RAM_DLY__M
- IQM_RT_RAM_DLY__PRE
- IQM_RT_RAM_DLY__W
- IQM_RT_RAM__A
- IQM_RT_ROT_BP_ROT_BPF__B
- IQM_RT_ROT_BP_ROT_BPF__M
- IQM_RT_ROT_BP_ROT_BPF__PRE
- IQM_RT_ROT_BP_ROT_BPF__W
- IQM_RT_ROT_BP_ROT_OFF_ACTIVE
- IQM_RT_ROT_BP_ROT_OFF_OFF
- IQM_RT_ROT_BP_ROT_OFF__B
- IQM_RT_ROT_BP_ROT_OFF__M
- IQM_RT_ROT_BP_ROT_OFF__PRE
- IQM_RT_ROT_BP_ROT_OFF__W
- IQM_RT_ROT_BP__A
- IQM_RT_ROT_BP__M
- IQM_RT_ROT_BP__PRE
- IQM_RT_ROT_BP__W
- IQPOWER_THRESHOLD
- IQS5XX_ABS_X
- IQS5XX_ABS_Y
- IQS5XX_APP
- IQS5XX_APP_LEN
- IQS5XX_BL_ADDR_MASK
- IQS5XX_BL_ATTEMPTS
- IQS5XX_BL_BLK_LEN_MAX
- IQS5XX_BL_CMD_CRC
- IQS5XX_BL_CMD_EXEC
- IQS5XX_BL_CMD_READ
- IQS5XX_BL_CMD_VER
- IQS5XX_BL_CRC_FAIL
- IQS5XX_BL_CRC_PASS
- IQS5XX_BL_ID
- IQS5XX_BL_STATUS_AVAIL
- IQS5XX_BL_STATUS_NONE
- IQS5XX_BL_STATUS_RESET
- IQS5XX_CHKSM
- IQS5XX_CHKSM_LEN
- IQS5XX_CSTM
- IQS5XX_CSTM_LEN
- IQS5XX_END_COMM
- IQS5XX_EVENT_MODE
- IQS5XX_FLIP_X
- IQS5XX_FLIP_Y
- IQS5XX_FW_FILE_LEN
- IQS5XX_MAJOR_VER_MIN
- IQS5XX_NUM_CONTACTS
- IQS5XX_NUM_POINTS
- IQS5XX_NUM_RETRIES
- IQS5XX_PMAP_END
- IQS5XX_PMAP_LEN
- IQS5XX_PROD_NUM
- IQS5XX_PROD_NUM_IQS525
- IQS5XX_PROD_NUM_IQS550
- IQS5XX_PROD_NUM_IQS572
- IQS5XX_PROJ_NUM_A000
- IQS5XX_PROJ_NUM_B000
- IQS5XX_REC_HDR_LEN
- IQS5XX_REC_LEN_MAX
- IQS5XX_REC_TYPE_DATA
- IQS5XX_REC_TYPE_EOF
- IQS5XX_RESUME
- IQS5XX_SETUP_COMPLETE
- IQS5XX_SUSPEND
- IQS5XX_SWITCH_XY_AXIS
- IQS5XX_SW_INPUT_EVENT
- IQS5XX_SYS_CFG0
- IQS5XX_SYS_CFG1
- IQS5XX_SYS_CTRL0
- IQS5XX_SYS_CTRL1
- IQS5XX_TOTAL_RX
- IQS5XX_TOTAL_TX
- IQS5XX_TP_EVENT
- IQS5XX_WR_BYTES_MAX
- IQS5XX_XY_CFG0
- IQS5XX_X_RES
- IQS5XX_Y_RES
- IQWRF_GEN_SHIFT
- IQWRF_LEN_GET
- IQWRF_NEWBUF
- IQWRF_TYPE_GET
- IQ_ADDR
- IQ_DEQUEUE_RETRY
- IQ_IDX
- IQ_INSTR_MODE_32B
- IQ_INSTR_MODE_64B
- IQ_INTR_TYPE_IB
- IQ_INTR_TYPE_MQD
- IQ_INTR_TYPE_PQ
- IQ_MAP
- IQ_MISMATCH_CAL
- IQ_OFFLOAD_RETRY
- IQ_QUEUE_SLEEP
- IQ_SCH_WAVE_MSG
- IQ_SEM_REARM
- IQ_SEND_FAILED
- IQ_SEND_OK
- IQ_SEND_STOP
- IQ_STATUS_RUNNING
- IQ_SWAP_OFF
- IQ_SWAP_ON
- IR
- IR0
- IR0_DMAREQ
- IR0_DMIA
- IR0_DMIB
- IR0_DMIC
- IR0_DRX
- IR0_DTX
- IR0_EFT
- IR0_M
- IR0_RXINTA
- IR0_RXINTB
- IR0_RXRDY
- IR0_TXINT
- IR0_TXRDY
- IR1
- IR2
- IR2MSK
- IR2_PD_INFO
- IR2_STATE_CHANGED
- IR3
- IR35221_MFR_IOUT_PEAK
- IR35221_MFR_IOUT_VALLEY
- IR35221_MFR_TEMP_PEAK
- IR35221_MFR_TEMP_VALLEY
- IR35221_MFR_VIN_PEAK
- IR35221_MFR_VIN_VALLEY
- IR35221_MFR_VOUT_PEAK
- IR35221_MFR_VOUT_VALLEY
- IR3MSKL
- IRACR
- IRAMTOP
- IRAM_IADD_AIE
- IRAM_OFFSET
- IRAM_READY
- IRAM_RESERVE_AREA_END_V2
- IRAM_RESERVE_AREA_END_V2_2
- IRAM_RESERVE_AREA_START_V2
- IRAM_RESERVE_AREA_START_V2_2
- IRAM_SIZE
- IRASH
- IRBAR
- IRB_AREA_SIZE
- IRB_CLOCK_SEL
- IRB_CLOCK_SEL_STATUS
- IRB_FIFO_NOT_EMPTY
- IRB_MAX_SYM_PERIOD
- IRB_OVERFLOW
- IRB_RX_EN
- IRB_RX_INTS
- IRB_RX_INT_CLEAR
- IRB_RX_INT_EN
- IRB_RX_INT_STATUS
- IRB_RX_NOISE_SUPPR
- IRB_RX_ON
- IRB_RX_OVERRUN_INT
- IRB_RX_POLARITY_INV
- IRB_RX_STATUS
- IRB_RX_SYS
- IRB_SAMPLE_FREQ
- IRB_SAMPLE_RATE_COMM
- IRB_TIMEOUT
- IRC
- IRCAPTURE
- IRCR_P2V
- IRCR_V2P
- IRCR_writew
- IRC_PORT
- IRDA
- IRDACLKCR
- IRDA_FIRSEL
- IRDA_FIRSEL_MARK
- IRDA_IN
- IRDA_IN_MARK
- IRDA_IO_BASE
- IRDA_IRDAI
- IRDA_MODE
- IRDA_OUT
- IRDA_OUT_MARK
- IRDA_SD
- IRDA_TX_1_5MBPS
- IRDA_TX_4MBPS
- IRDY_HSYNC_MARK
- IRDY_RST
- IRD_LIMIT_TO_IRRQ_SLOTS
- IREADONLY
- IREAD_LOCK
- IREAD_UNLOCK
- IREF0RC_OFFSET_MASK
- IREF0RC_OFFSET_SHIFT
- IREF1RC_OFFSET_MASK
- IREF1RC_OFFSET_SHIFT
- IREFGEN
- IREG_ACTIVATE
- IREG_EECONTROL
- IREG_FAN0
- IREG_FAN1
- IREG_FAN2
- IREG_FAN3
- IREG_FAN4
- IREG_FAN5
- IREG_FAN_STAT
- IREG_FIRE_TEMP
- IREG_FRONT_TEMP
- IREG_IO0_BASEHI
- IREG_IO0_BASELO
- IREG_IO1_BASEHI
- IREG_IO1_BASELO
- IREG_IRQ_NUMBER
- IREG_IRQ_TYPE
- IREG_LCL_TEMP
- IREG_LM95221_TEMP
- IREG_LOGDEVICE
- IREG_LSI1064_TEMP
- IREG_MEMBASEHI
- IREG_MEMBASELO
- IREG_MEMCONTROL
- IREG_MEMRANGEHI
- IREG_MEMRANGELO
- IREG_NUM_ELEM
- IREG_PSU_TEMP
- IREG_RMT1_TEMP
- IREG_RMT2_TEMP
- IREG_RMT3_TEMP
- IREG_VCORE0
- IREG_VCORE1
- IREG_VMEM0
- IREG_VMEM1
- IREQ_ABORT_PATH_ACTIVE
- IREQ_ACTIVE
- IREQ_CACHE_FLUSH
- IREQ_COMPLETE_IN_TARGET
- IREQ_INT
- IREQ_NO_AUTO_FREE_TAG
- IREQ_PENDING_ABORT
- IREQ_TC_ABORT_POSTED
- IREQ_TERMINATED
- IREQ_TMF
- IRER
- IRET
- IRET_FRAME
- IRET_FRAME_OFFSET
- IRET_FRAME_SIZE
- IREXIT1
- IREXIT2
- IRE_FRAME_CNT_MASK
- IRG_FLAGS_OFFSET
- IRING
- IRING_PAD
- IRIS_GIO_BASE
- IRIS_GIO_INPUT
- IRIS_GIO_NODEV
- IRIS_GIO_OUTPUT
- IRIS_GIO_PULSE
- IRIS_GIO_REST
- IRL
- IRL0
- IRL0MSKR_OFS
- IRL0SR_OFS
- IRL0_HHHL
- IRL0_HHLH
- IRL0_HHLL
- IRL0_HLHH
- IRL0_HLHL
- IRL0_HLLH
- IRL0_HLLL
- IRL0_IRQ
- IRL0_LHHH
- IRL0_LHHL
- IRL0_LHLH
- IRL0_LHLL
- IRL0_LLHH
- IRL0_LLHL
- IRL0_LLLH
- IRL0_LLLL
- IRL0_MARK
- IRL0_PRIORITY
- IRL1
- IRL1MSKR_OFS
- IRL1SR_OFS
- IRL1_IRQ
- IRL1_MARK
- IRL1_PRIORITY
- IRL2
- IRL2MSKR_OFS
- IRL2SR_OFS
- IRL2_IRQ
- IRL2_MARK
- IRL2_PRIORITY
- IRL3
- IRL3MSKR_OFS
- IRL3SR_OFS
- IRL3_IRQ
- IRL3_MARK
- IRL3_PRIORITY
- IRL4_HHHL
- IRL4_HHLH
- IRL4_HHLL
- IRL4_HLHH
- IRL4_HLHL
- IRL4_HLLH
- IRL4_HLLL
- IRL4_LHHH
- IRL4_LHHL
- IRL4_LHLH
- IRL4_LHLL
- IRL4_LLHH
- IRL4_LLHL
- IRL4_LLLH
- IRL4_LLLL
- IRL4_MARK
- IRL5_MARK
- IRL6_MARK
- IRL7_MARK
- IRLCNTR1
- IRLEN_COARSE_2K
- IRLEN_COARSE_8K
- IRLEN_FINE_2K
- IRLEN_FINE_8K
- IRL_FC_MASK
- IRL_FC_SHIFT
- IRL_HHHL
- IRL_HHLH
- IRL_HHLL
- IRL_HLHH
- IRL_HLHL
- IRL_HLLH
- IRL_HLLL
- IRL_LHHH
- IRL_LHHL
- IRL_LHLH
- IRL_LHLL
- IRL_LLHH
- IRL_LLHL
- IRL_LLLH
- IRL_LLLL
- IRL_TO_MASK
- IRM
- IRMSEL
- IRMSEL_HP
- IRMSEL_SHARP
- IRMSEL_TEMIC
- IRNET_MINOR
- IRO
- IRONGATE0
- IRONGATE1
- IRONGATE_3GB
- IRONGATE_BIAS
- IRONGATE_CONF
- IRONGATE_DEFAULT_MEM_BASE
- IRONGATE_HAE_ADDRESS
- IRONGATE_IACK_SC
- IRONGATE_IO
- IRONGATE_MEM
- IROUT_MARK
- IRPAUSE
- IRPS5401_LDO_FUNC
- IRPS5401_SW_FUNC
- IRPTNDX
- IRPTNDX_MASK
- IRPTNDX_SHIFT
- IRQ
- IRQ0
- IRQ01_BASE_ADDR
- IRQ01_MASK_REG
- IRQ01_MODE_REG
- IRQ01_STS_REG
- IRQ0ENABLE_CCDC_ERR_IRQ
- IRQ0ENABLE_CCDC_LSC_DONE_IRQ
- IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ
- IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ
- IRQ0ENABLE_CCDC_VD0_IRQ
- IRQ0ENABLE_CCDC_VD1_IRQ
- IRQ0ENABLE_CCDC_VD2_IRQ
- IRQ0ENABLE_CCP2_LC0_IRQ
- IRQ0ENABLE_CCP2_LC1_IRQ
- IRQ0ENABLE_CCP2_LC2_IRQ
- IRQ0ENABLE_CCP2_LC3_IRQ
- IRQ0ENABLE_CCP2_LCM_IRQ
- IRQ0ENABLE_CSIA_IRQ
- IRQ0ENABLE_CSIB_IRQ
- IRQ0ENABLE_CSIC_IRQ
- IRQ0ENABLE_H3A_AF_DONE_IRQ
- IRQ0ENABLE_H3A_AWB_DONE_IRQ
- IRQ0ENABLE_HIST_DONE_IRQ
- IRQ0ENABLE_HS_VS_IRQ
- IRQ0ENABLE_MMU_ERR_IRQ
- IRQ0ENABLE_OCP_ERR_IRQ
- IRQ0ENABLE_OVF_IRQ
- IRQ0ENABLE_PING_IRQ
- IRQ0ENABLE_PONG_IRQ
- IRQ0ENABLE_PRV_DONE_IRQ
- IRQ0ENABLE_RSZ_DONE_IRQ
- IRQ0ENABLE_SEC_ERR_IRQ
- IRQ0STATUS_CCDC_ERR_IRQ
- IRQ0STATUS_CCDC_LSC_DONE_IRQ
- IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ
- IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ
- IRQ0STATUS_CCDC_VD0_IRQ
- IRQ0STATUS_CCDC_VD1_IRQ
- IRQ0STATUS_CCDC_VD2_IRQ
- IRQ0STATUS_CCP2_LC0_IRQ
- IRQ0STATUS_CCP2_LCM_IRQ
- IRQ0STATUS_CSI2C_IRQ
- IRQ0STATUS_CSIA_IRQ
- IRQ0STATUS_CSIB_IRQ
- IRQ0STATUS_CSIB_LC1_IRQ
- IRQ0STATUS_CSIB_LC2_IRQ
- IRQ0STATUS_CSIB_LC3_IRQ
- IRQ0STATUS_H3A_AF_DONE_IRQ
- IRQ0STATUS_H3A_AWB_DONE_IRQ
- IRQ0STATUS_HIST_DONE_IRQ
- IRQ0STATUS_HS_VS_IRQ
- IRQ0STATUS_MMU_ERR_IRQ
- IRQ0STATUS_OCP_ERR_IRQ
- IRQ0STATUS_OVF_IRQ
- IRQ0STATUS_PING_IRQ
- IRQ0STATUS_PONG_IRQ
- IRQ0STATUS_PRV_DONE_IRQ
- IRQ0STATUS_RSZ_DONE_IRQ
- IRQ0STATUS_SEC_ERR_IRQ
- IRQ0_A_MARK
- IRQ0_BASE
- IRQ0_B_MARK
- IRQ0_CNTL
- IRQ0_CTL_BASE
- IRQ0_DATA
- IRQ0_END
- IRQ0_HEAD
- IRQ0_IRL0_MARK
- IRQ0_IRQ
- IRQ0_KEY
- IRQ0_MARK
- IRQ0_MASK
- IRQ0_MCU_CLR_MASK
- IRQ0_MCU_CLR_MASK_SFT
- IRQ0_MCU_CLR_SFT
- IRQ0_MCU_MISS_CLR_MASK
- IRQ0_MCU_MISS_CLR_MASK_SFT
- IRQ0_MCU_MISS_CLR_SFT
- IRQ0_MCU_MODE_MASK
- IRQ0_MCU_MODE_MASK_SFT
- IRQ0_MCU_MODE_SFT
- IRQ0_MCU_ON_MASK
- IRQ0_MCU_ON_MASK_SFT
- IRQ0_MCU_ON_SFT
- IRQ0_MR
- IRQ0_PB_MARK
- IRQ0_PC_MARK
- IRQ0_PD_MARK
- IRQ0_PE_MARK
- IRQ0_PG_MARK
- IRQ0_PJ_MARK
- IRQ0_PORT13_MARK
- IRQ0_PORT2_MARK
- IRQ0_RMII
- IRQ0_SMC
- IRQ0_SR
- IRQ1
- IRQ10
- IRQ10_MARK
- IRQ10_MCU_CLR_MASK
- IRQ10_MCU_CLR_MASK_SFT
- IRQ10_MCU_CLR_SFT
- IRQ10_MCU_MISS_CLR_MASK
- IRQ10_MCU_MISS_CLR_MASK_SFT
- IRQ10_MCU_MISS_CLR_SFT
- IRQ10_MCU_ON_MASK
- IRQ10_MCU_ON_MASK_SFT
- IRQ10_MCU_ON_SFT
- IRQ11
- IRQ11_MARK
- IRQ11_MCU_CLR_MASK
- IRQ11_MCU_CLR_MASK_SFT
- IRQ11_MCU_CLR_SFT
- IRQ11_MCU_MISS_CNT_CLR_MASK
- IRQ11_MCU_MISS_CNT_CLR_MASK_SFT
- IRQ11_MCU_MISS_CNT_CLR_SFT
- IRQ11_MCU_MODE_MASK
- IRQ11_MCU_MODE_MASK_SFT
- IRQ11_MCU_MODE_SFT
- IRQ11_MCU_ON_MASK
- IRQ11_MCU_ON_MASK_SFT
- IRQ11_MCU_ON_SFT
- IRQ12
- IRQ12_MARK
- IRQ12_MCU_CLR_MASK
- IRQ12_MCU_CLR_MASK_SFT
- IRQ12_MCU_CLR_SFT
- IRQ12_MCU_MISS_CNT_CLR_MASK
- IRQ12_MCU_MISS_CNT_CLR_MASK_SFT
- IRQ12_MCU_MISS_CNT_CLR_SFT
- IRQ12_MCU_MODE_MASK
- IRQ12_MCU_MODE_MASK_SFT
- IRQ12_MCU_MODE_SFT
- IRQ12_MCU_ON_MASK
- IRQ12_MCU_ON_MASK_SFT
- IRQ12_MCU_ON_SFT
- IRQ12_PORT42_MARK
- IRQ12_PORT97_MARK
- IRQ13
- IRQ13_MARK
- IRQ13_PORT64_MARK
- IRQ13_PORT98_MARK
- IRQ14
- IRQ14_MARK
- IRQ14_PORT63_MARK
- IRQ14_PORT99_MARK
- IRQ15
- IRQ15_MARK
- IRQ15_PORT100_MARK
- IRQ15_PORT62_MARK
- IRQ16_PORT211_MARK
- IRQ16_PORT68_MARK
- IRQ17_MARK
- IRQ18_MARK
- IRQ19_MARK
- IRQ1_A_MARK
- IRQ1_BASE
- IRQ1_B_MARK
- IRQ1_CNTL
- IRQ1_CTL_BASE
- IRQ1_DATA
- IRQ1_END
- IRQ1_HEAD
- IRQ1_IRL1_MARK
- IRQ1_IRQ
- IRQ1_IRQ_NUM
- IRQ1_LEVEL2
- IRQ1_MARK
- IRQ1_MASK
- IRQ1_MCU_CLR_MASK
- IRQ1_MCU_CLR_MASK_SFT
- IRQ1_MCU_CLR_SFT
- IRQ1_MCU_MISS_CLR_MASK
- IRQ1_MCU_MISS_CLR_MASK_SFT
- IRQ1_MCU_MISS_CLR_SFT
- IRQ1_MCU_MODE_MASK
- IRQ1_MCU_MODE_MASK_SFT
- IRQ1_MCU_MODE_SFT
- IRQ1_MCU_ON_MASK
- IRQ1_MCU_ON_MASK_SFT
- IRQ1_MCU_ON_SFT
- IRQ1_MR
- IRQ1_PB_MARK
- IRQ1_PC_MARK
- IRQ1_PD_MARK
- IRQ1_PE_MARK
- IRQ1_PG_MARK
- IRQ1_PJ_MARK
- IRQ1_SR
- IRQ1_TS
- IRQ2
- IRQ20_MARK
- IRQ21_MARK
- IRQ22_MARK
- IRQ23_MARK
- IRQ24_MARK
- IRQ25_MARK
- IRQ26_MODE
- IRQ26_PORT58_MARK
- IRQ26_PORT81_MARK
- IRQ27_PORT168_MARK
- IRQ27_PORT57_MARK
- IRQ28_PORT169_MARK
- IRQ28_PORT56_MARK
- IRQ29_PORT170_MARK
- IRQ29_PORT50_MARK
- IRQ2SLOT
- IRQ2_A_MARK
- IRQ2_BASE
- IRQ2_B_MARK
- IRQ2_CNTL
- IRQ2_CTL_BASE
- IRQ2_C_MARK
- IRQ2_DATA
- IRQ2_END
- IRQ2_HEAD
- IRQ2_IRL2_MARK
- IRQ2_IRQ
- IRQ2_IRQ_NUM
- IRQ2_MARK
- IRQ2_MASK
- IRQ2_MCU_CLR_MASK
- IRQ2_MCU_CLR_MASK_SFT
- IRQ2_MCU_CLR_SFT
- IRQ2_MCU_MISS_CLR_MASK
- IRQ2_MCU_MISS_CLR_MASK_SFT
- IRQ2_MCU_MISS_CLR_SFT
- IRQ2_MCU_MODE_MASK
- IRQ2_MCU_MODE_MASK_SFT
- IRQ2_MCU_MODE_SFT
- IRQ2_MCU_ON_MASK
- IRQ2_MCU_ON_MASK_SFT
- IRQ2_MCU_ON_SFT
- IRQ2_MR
- IRQ2_PB_MARK
- IRQ2_PD_MARK
- IRQ2_PE_MARK
- IRQ2_PG_MARK
- IRQ2_PJ_MARK
- IRQ2_PORT11_MARK
- IRQ2_PORT12_MARK
- IRQ2_SDHID2
- IRQ2_SR
- IRQ2_USB0
- IRQ2_USB1
- IRQ3
- IRQ30_PORT171_MARK
- IRQ30_PORT49_MARK
- IRQ31_PORT167_MARK
- IRQ31_PORT41_MARK
- IRQ3_A_MARK
- IRQ3_BASE
- IRQ3_B_MARK
- IRQ3_CNTL
- IRQ3_DATA
- IRQ3_HEAD
- IRQ3_IRL3_MARK
- IRQ3_IRQ
- IRQ3_IRQ_NUM
- IRQ3_LEVEL6
- IRQ3_MARK
- IRQ3_MCU_CLR_MASK
- IRQ3_MCU_CLR_MASK_SFT
- IRQ3_MCU_CLR_SFT
- IRQ3_MCU_MISS_CLR_MASK
- IRQ3_MCU_MISS_CLR_MASK_SFT
- IRQ3_MCU_MISS_CLR_SFT
- IRQ3_MCU_MODE_MASK
- IRQ3_MCU_MODE_MASK_SFT
- IRQ3_MCU_MODE_SFT
- IRQ3_MCU_ON_MASK
- IRQ3_MCU_ON_MASK_SFT
- IRQ3_MCU_ON_SFT
- IRQ3_PB_MARK
- IRQ3_PD_MARK
- IRQ3_PE_MARK
- IRQ3_PG_MARK
- IRQ3_PJ_MARK
- IRQ3_PORT10_MARK
- IRQ3_PORT14_MARK
- IRQ4
- IRQ4_BS
- IRQ4_IRQ
- IRQ4_MARK
- IRQ4_MCU_CLR_MASK
- IRQ4_MCU_CLR_MASK_SFT
- IRQ4_MCU_CLR_SFT
- IRQ4_MCU_MISS_CLR_MASK
- IRQ4_MCU_MISS_CLR_MASK_SFT
- IRQ4_MCU_MISS_CLR_SFT
- IRQ4_MCU_MODE_MASK
- IRQ4_MCU_MODE_MASK_SFT
- IRQ4_MCU_MODE_SFT
- IRQ4_MCU_ON_MASK
- IRQ4_MCU_ON_MASK_SFT
- IRQ4_MCU_ON_SFT
- IRQ4_PB_MARK
- IRQ4_PC_MARK
- IRQ4_PD_MARK
- IRQ4_PE_MARK
- IRQ4_PF_MARK
- IRQ4_PG_MARK
- IRQ4_PORT15_MARK
- IRQ4_PORT172_MARK
- IRQ5
- IRQ5_IRQ
- IRQ5_IRQ_NUM
- IRQ5_LEVEL4
- IRQ5_MARK
- IRQ5_MCU_CLR_MASK
- IRQ5_MCU_CLR_MASK_SFT
- IRQ5_MCU_CLR_SFT
- IRQ5_MCU_MISS_CLR_MASK
- IRQ5_MCU_MISS_CLR_MASK_SFT
- IRQ5_MCU_MISS_CLR_SFT
- IRQ5_MCU_MODE_MASK
- IRQ5_MCU_MODE_MASK_SFT
- IRQ5_MCU_MODE_SFT
- IRQ5_MCU_ON_MASK
- IRQ5_MCU_ON_MASK_SFT
- IRQ5_MCU_ON_SFT
- IRQ5_PB_MARK
- IRQ5_PC_MARK
- IRQ5_PD_MARK
- IRQ5_PE_MARK
- IRQ5_PF_MARK
- IRQ5_PG_MARK
- IRQ5_PORT0_MARK
- IRQ5_PORT1_MARK
- IRQ6
- IRQ6_IRQ_NUM
- IRQ6_MARK
- IRQ6_MCU_CLR_MASK
- IRQ6_MCU_CLR_MASK_SFT
- IRQ6_MCU_CLR_SFT
- IRQ6_MCU_MISS_CLR_MASK
- IRQ6_MCU_MISS_CLR_MASK_SFT
- IRQ6_MCU_MISS_CLR_SFT
- IRQ6_MCU_MODE_MASK
- IRQ6_MCU_MODE_MASK_SFT
- IRQ6_MCU_MODE_SFT
- IRQ6_MCU_ON_MASK
- IRQ6_MCU_ON_MASK_SFT
- IRQ6_MCU_ON_SFT
- IRQ6_PB_MARK
- IRQ6_PC_MARK
- IRQ6_PD_MARK
- IRQ6_PE_MARK
- IRQ6_PF_MARK
- IRQ6_PG_MARK
- IRQ6_PORT121_MARK
- IRQ6_PORT173_MARK
- IRQ7
- IRQ7_IRQ_NUM
- IRQ7_MARK
- IRQ7_MCU_CLR_MASK
- IRQ7_MCU_CLR_MASK_SFT
- IRQ7_MCU_CLR_SFT
- IRQ7_MCU_MISS_CLR_MASK
- IRQ7_MCU_MISS_CLR_MASK_SFT
- IRQ7_MCU_MISS_CLR_SFT
- IRQ7_MCU_MODE_MASK
- IRQ7_MCU_MODE_MASK_SFT
- IRQ7_MCU_MODE_SFT
- IRQ7_MCU_ON_MASK
- IRQ7_MCU_ON_MASK_SFT
- IRQ7_MCU_ON_SFT
- IRQ7_PB_MARK
- IRQ7_PC_MARK
- IRQ7_PD_MARK
- IRQ7_PE_MARK
- IRQ7_PF_MARK
- IRQ7_PG_MARK
- IRQ7_PORT120_MARK
- IRQ7_PORT209_MARK
- IRQ8
- IRQ8_MARK
- IRQ8_MCU_CLR_MASK
- IRQ8_MCU_CLR_MASK_SFT
- IRQ8_MCU_CLR_SFT
- IRQ8_MCU_MISS_CLR_MASK
- IRQ8_MCU_MISS_CLR_MASK_SFT
- IRQ8_MCU_MISS_CLR_SFT
- IRQ8_MCU_ON_MASK
- IRQ8_MCU_ON_MASK_SFT
- IRQ8_MCU_ON_SFT
- IRQ9
- IRQ9_MARK
- IRQ9_MCP_INT_MARK
- IRQ9_MCU_CLR_MASK
- IRQ9_MCU_CLR_MASK_SFT
- IRQ9_MCU_CLR_SFT
- IRQ9_MCU_MISS_CLR_MASK
- IRQ9_MCU_MISS_CLR_MASK_SFT
- IRQ9_MCU_MISS_CLR_SFT
- IRQ9_MCU_ON_MASK
- IRQ9_MCU_ON_MASK_SFT
- IRQ9_MCU_ON_SFT
- IRQ9_MEM_INT_MARK
- IRQ9_PORT118_MARK
- IRQ9_PORT210_MARK
- IRQBIT
- IRQBITS
- IRQBYPASS_H
- IRQCHIP_ACPI_DECLARE
- IRQCHIP_DECLARE
- IRQCHIP_EOI_IF_HANDLED
- IRQCHIP_EOI_THREADED
- IRQCHIP_FWNODE_NAMED
- IRQCHIP_FWNODE_NAMED_ID
- IRQCHIP_FWNODE_REAL
- IRQCHIP_MADERA_H
- IRQCHIP_MASK_ON_SUSPEND
- IRQCHIP_OF_MATCH_TABLE
- IRQCHIP_ONESHOT_SAFE
- IRQCHIP_ONOFFLINE_ENABLED
- IRQCHIP_SET_TYPE_MASKED
- IRQCHIP_SKIP_SET_WAKE
- IRQCHIP_STATE_ACTIVE
- IRQCHIP_STATE_LINE_LEVEL
- IRQCHIP_STATE_MASKED
- IRQCHIP_STATE_PENDING
- IRQCHIP_SUPPORTS_LEVEL_MSI
- IRQCHIP_SUPPORTS_NMI
- IRQCONTROL
- IRQCONTROL_ALLCLEAR
- IRQCONTROL_ALLMASK
- IRQCONTROL_FIFO_CLEAR
- IRQCONTROL_IRQDISABLE
- IRQCONTROL_PHASE_CHANGE_CLEAR
- IRQCONTROL_RESELECT_CLEAR
- IRQCONTROL_TIMER_CLEAR
- IRQCS_ACTIVE_PCIDB
- IRQCS_ENABLE_PCIDB
- IRQCS_ENABLE_PCIIRQ
- IRQC_BASE
- IRQC_CONFIG
- IRQC_EN_SET
- IRQC_EN_STS
- IRQC_INT_CPU_BASE
- IRQC_IRQ_MAX
- IRQC_IS_HARDIRQ
- IRQC_IS_NESTED
- IRQC_MONITOR
- IRQC_NUM_IRQ
- IRQC_PINS_MUX
- IRQC_PIN_MUX
- IRQC_REQ_STS
- IRQD
- IRQD_ACTIVATED
- IRQD_AFFINITY_MANAGED
- IRQD_AFFINITY_SET
- IRQD_CAN_RESERVE
- IRQD_DEFAULT_TRIGGER_SET
- IRQD_FORWARDED_TO_VCPU
- IRQD_IRQ_DISABLED
- IRQD_IRQ_INPROGRESS
- IRQD_IRQ_MASKED
- IRQD_IRQ_STARTED
- IRQD_LEVEL
- IRQD_MANAGED_SHUTDOWN
- IRQD_MOVE_PCNTXT
- IRQD_MSI_NOMASK_QUIRK
- IRQD_NO_BALANCING
- IRQD_PER_CPU
- IRQD_SETAFFINITY_PENDING
- IRQD_SINGLE_TARGET
- IRQD_TRIGGER_MASK
- IRQD_WAKEUP_ARMED
- IRQD_WAKEUP_STATE
- IRQEN
- IRQEN0
- IRQEN1
- IRQENABLE_CLR
- IRQENABLE_L0
- IRQENABLE_L1
- IRQENABLE_L2
- IRQENABLE_L3
- IRQENABLE_MCUACCUMINT
- IRQENABLE_MCUBOUNDSINT
- IRQENABLE_MCUDISABLEACKINT
- IRQENABLE_MCUVALIDINT
- IRQENABLE_SET
- IRQENB0
- IRQENB1
- IRQENB_EOS
- IRQENB_FIFO0OVRRUN
- IRQENB_FIFO0THRES
- IRQENB_FIFO0UNDRFLW
- IRQENB_FIFO1OVRRUN
- IRQENB_FIFO1THRES
- IRQENB_FIFO1UNDRFLW
- IRQENB_HW_PEN
- IRQENB_PENUP
- IRQENTRY_TEXT
- IRQEN_GPIOINTEN_DISABLED
- IRQEN_GPIOINTEN_ENABLED
- IRQEN_MSK
- IRQEN_ROE
- IRQEN_RSE
- IRQEN_RTE
- IRQEN_TSE
- IRQEXT_CLK
- IRQEXT_CMC
- IRQEXT_CMS
- IRQEXT_DSD
- IRQEXT_EMS
- IRQEXT_EXC
- IRQEXT_FTP
- IRQEXT_IUC
- IRQEXT_PFL
- IRQEXT_SCP
- IRQEXT_TLA
- IRQEXT_TMR
- IRQEXT_VRT
- IRQF_COND_SUSPEND
- IRQF_EARLY_RESUME
- IRQF_FORCE_RESUME
- IRQF_IRQPOLL
- IRQF_MODIFY_MASK
- IRQF_NOBALANCING
- IRQF_NO_SUSPEND
- IRQF_NO_THREAD
- IRQF_ONESHOT
- IRQF_PERCPU
- IRQF_PROBE_SHARED
- IRQF_SHARED
- IRQF_TIMER
- IRQF_TRIGGER_FALLING
- IRQF_TRIGGER_HIGH
- IRQF_TRIGGER_LOW
- IRQF_TRIGGER_MASK
- IRQF_TRIGGER_NONE
- IRQF_TRIGGER_PROBE
- IRQF_TRIGGER_RISING
- IRQIO_ADM
- IRQIO_APB
- IRQIO_C15
- IRQIO_C70
- IRQIO_CIO
- IRQIO_CSC
- IRQIO_CTC
- IRQIO_DAS
- IRQIO_GAL
- IRQIO_LCS
- IRQIO_MSI
- IRQIO_PCD
- IRQIO_PCF
- IRQIO_QAI
- IRQIO_TAP
- IRQIO_VAI
- IRQIO_VIR
- IRQIO_VMR
- IRQLine
- IRQM
- IRQMASK_GPIOM_MASKED
- IRQMASK_GPIOM_NOT_MASKED
- IRQMASK_I_BIT
- IRQMASK_REG_NAME_R
- IRQMASK_REG_NAME_W
- IRQMASK_SOME_STATUS_1
- IRQMASK_SOME_STATUS_2
- IRQMASK_UNMODIFIABLE
- IRQM_ADC_ABOUT_CNT
- IRQM_ADC_DELAY_CNT
- IRQM_ADC_FIFO_WRITE
- IRQM_ADC_SAMPLE_CNT
- IRQM_CGT_PAUSE
- IRQM_CGT_RESET
- IRQM_DAC1_UCNT
- IRQM_DAC2_UCNT
- IRQM_DIGITAL_IT
- IRQM_ETRIG_FALLING
- IRQM_ETRIG_RISING
- IRQM_EXTERNAL_IT
- IRQM_UTC1
- IRQM_UTC1_INV
- IRQM_UTC2
- IRQNAME
- IRQOUT_MARK
- IRQOUT_REFOUT_MARK
- IRQPHASESENCE
- IRQPIN_EXTINT1
- IRQPIN_EXTINT2
- IRQPIN_EXTINT3
- IRQPIN_EXTINT4
- IRQPIN_PCC0
- IRQPIN_PCC2
- IRQPIN_PCCPW
- IRQPIN_SM501
- IRQPIN_SMC91CX
- IRQPM_EN
- IRQPOS_EXTINT1
- IRQPOS_EXTINT2
- IRQPOS_EXTINT3
- IRQPOS_EXTINT4
- IRQPOS_PCCPW
- IRQPOS_SM501
- IRQPOS_SMC91CX
- IRQRR
- IRQSELECT_AUTO_SCSI_SEQ_IRQ
- IRQSELECT_BMCNTERR_IRQ
- IRQSELECT_FIFO_SHLD_IRQ
- IRQSELECT_MASTER_ABORT_IRQ
- IRQSELECT_PERR_IRQ
- IRQSELECT_PHASE_CHANGE_IRQ
- IRQSELECT_RESELECT_IRQ
- IRQSELECT_SCSIRESET_IRQ
- IRQSELECT_SERR_IRQ
- IRQSELECT_TARGET_ABORT_IRQ
- IRQSELECT_TIMER_IRQ
- IRQSTAT
- IRQSTAT0
- IRQSTAT1
- IRQSTATUS
- IRQSTATUS_ANY_IRQ
- IRQSTATUS_AUTOSCSI_IRQ
- IRQSTATUS_BMCNTERR_IRQ
- IRQSTATUS_FIFO
- IRQSTATUS_FIFO_SHLD_IRQ
- IRQSTATUS_L0
- IRQSTATUS_L1
- IRQSTATUS_L2
- IRQSTATUS_L3
- IRQSTATUS_LATCHED_BUS_FREE
- IRQSTATUS_LATCHED_CD
- IRQSTATUS_LATCHED_IO
- IRQSTATUS_LATCHED_MSG
- IRQSTATUS_MASK
- IRQSTATUS_MCBOUNDSINT
- IRQSTATUS_MCUACCUMINT
- IRQSTATUS_MCUDISABLEACKINT
- IRQSTATUS_MCVALIDINT
- IRQSTATUS_PCI_IRQ
- IRQSTATUS_PHASE_CHANGE_IRQ
- IRQSTATUS_RAW
- IRQSTATUS_RESELECT_OCCUER
- IRQSTATUS_SCSI
- IRQSTATUS_SCSIRESET_IRQ
- IRQSTATUS_TIMER
- IRQSTATUS_TIMER_IRQ
- IRQSTAT_A
- IRQSTAT_C
- IRQSTAT_C_TAPER_IRQ
- IRQSTAT_C_TERMINATION_IRQ
- IRQSTAT_C_TERMINATION_STAT
- IRQSTAT_D
- IRQSTAT_D_CHARGE_TIMEOUT_IRQ
- IRQSTAT_D_CHARGE_TIMEOUT_STAT
- IRQSTAT_E
- IRQSTAT_E_DCIN_UV_IRQ
- IRQSTAT_E_DCIN_UV_STAT
- IRQSTAT_E_USBIN_UV_IRQ
- IRQSTAT_E_USBIN_UV_STAT
- IRQSTAT_F
- IRQSTAT_GPIOINT_INTERRUPTED
- IRQSTAT_GPIOINT_NOT_INTERRUPTED
- IRQS_ALL_DISABLED
- IRQS_AUTODETECT
- IRQS_DISABLED
- IRQS_ENABLED
- IRQS_NMI
- IRQS_ONESHOT
- IRQS_PENDING
- IRQS_PER_BANK
- IRQS_PER_IDX
- IRQS_PER_MBIGEN_NODE
- IRQS_PER_MSI_REG
- IRQS_PER_WORD
- IRQS_PMI_DISABLED
- IRQS_POLL_INPROGRESS
- IRQS_REPLAY
- IRQS_SPURIOUS_DISABLED
- IRQS_SUSPENDED
- IRQS_TIMINGS
- IRQS_WAITING
- IRQTF_AFFINITY
- IRQTF_FORCED_THREAD
- IRQTF_RUNTHREAD
- IRQTF_WARNED
- IRQTYPE_EDGE
- IRQTYPE_HIGH
- IRQTYPE_LEVEL
- IRQTYPE_LOW
- IRQT_EVTCHN
- IRQT_IPI
- IRQT_PIRQ
- IRQT_UNBOUND
- IRQT_VIRQ
- IRQVEC
- IRQWKUP_ENB
- IRQ_1WIRE
- IRQ_2D
- IRQ_79C973
- IRQ_A
- IRQ_AA_EOC
- IRQ_AA_EOT
- IRQ_AA_ERR
- IRQ_AC97
- IRQ_ACIPC0
- IRQ_ACIPC1
- IRQ_ACIPC2
- IRQ_ACTIVE_HIGH
- IRQ_ACTIVE_LOW
- IRQ_ADC
- IRQ_ADCPARENT
- IRQ_ADDRESS_VALID
- IRQ_ADDRSEL
- IRQ_AEMIFINT
- IRQ_AFFINITY_MAX_SETS
- IRQ_ALI
- IRQ_ALIGNMENT
- IRQ_ALL
- IRQ_ALLSENT
- IRQ_ALL_ACK_MASK
- IRQ_ALL_EN_MASK
- IRQ_ALL_ERRORS
- IRQ_AMI
- IRQ_AMIGA_AUD0
- IRQ_AMIGA_AUD1
- IRQ_AMIGA_AUD2
- IRQ_AMIGA_AUD3
- IRQ_AMIGA_BLIT
- IRQ_AMIGA_CIAA
- IRQ_AMIGA_CIAA_ALRM
- IRQ_AMIGA_CIAA_FLG
- IRQ_AMIGA_CIAA_SP
- IRQ_AMIGA_CIAA_TA
- IRQ_AMIGA_CIAA_TB
- IRQ_AMIGA_CIAB
- IRQ_AMIGA_CIAB_ALRM
- IRQ_AMIGA_CIAB_FLG
- IRQ_AMIGA_CIAB_SP
- IRQ_AMIGA_CIAB_TA
- IRQ_AMIGA_CIAB_TB
- IRQ_AMIGA_COPPER
- IRQ_AMIGA_DSKBLK
- IRQ_AMIGA_DSKSYN
- IRQ_AMIGA_EXTER
- IRQ_AMIGA_PORTS
- IRQ_AMIGA_RBF
- IRQ_AMIGA_SOFT
- IRQ_AMIGA_TBE
- IRQ_AMIGA_VERTB
- IRQ_ANGELX
- IRQ_APOLLO
- IRQ_APU_TO_CPU
- IRQ_APU_TO_CPU_ACK
- IRQ_APU_TO_EPU
- IRQ_APU_TO_EPU_ACK
- IRQ_APU_TO_HPU
- IRQ_APU_TO_HPU_ACK
- IRQ_APU_TO_PPU
- IRQ_APU_TO_PPU_ACK
- IRQ_ARB
- IRQ_ARM_DMA
- IRQ_ARM_DMAERR
- IRQ_ARM_DMAS
- IRQ_ASQINT
- IRQ_ASSP
- IRQ_ATA
- IRQ_ATI
- IRQ_ATM
- IRQ_ATTR_RO
- IRQ_AUTO
- IRQ_AUTO_1
- IRQ_AUTO_2
- IRQ_AUTO_3
- IRQ_AUTO_4
- IRQ_AUTO_5
- IRQ_AUTO_6
- IRQ_AUTO_7
- IRQ_AX88796
- IRQ_B
- IRQ_BABOON_0
- IRQ_BABOON_1
- IRQ_BABOON_2
- IRQ_BABOON_3
- IRQ_BANK
- IRQ_BAP
- IRQ_BASE
- IRQ_BATF
- IRQ_BATLOW
- IRQ_BATT_FLT
- IRQ_BAT_LOW
- IRQ_BEI
- IRQ_BIT
- IRQ_BITMAP_BITS
- IRQ_BOARD_END
- IRQ_BOARD_START
- IRQ_BREAK_ON
- IRQ_BRI
- IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK
- IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT
- IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK
- IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT
- IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK
- IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK
- IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT
- IRQ_BRIDGE_CNTL__ISA_EN_MASK
- IRQ_BRIDGE_CNTL__ISA_EN__MASK
- IRQ_BRIDGE_CNTL__ISA_EN__SHIFT
- IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK
- IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK
- IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT
- IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK
- IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK
- IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT
- IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK
- IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT
- IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK
- IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK
- IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT
- IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK
- IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT
- IRQ_BRIDGE_CNTL__SERR_EN_MASK
- IRQ_BRIDGE_CNTL__SERR_EN__MASK
- IRQ_BRIDGE_CNTL__SERR_EN__SHIFT
- IRQ_BRIDGE_CNTL__VGA_DEC_MASK
- IRQ_BRIDGE_CNTL__VGA_DEC__MASK
- IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT
- IRQ_BRIDGE_CNTL__VGA_EN_MASK
- IRQ_BRIDGE_CNTL__VGA_EN__MASK
- IRQ_BRIDGE_CNTL__VGA_EN__SHIFT
- IRQ_BTUART
- IRQ_BUTTON
- IRQ_CAM
- IRQ_CAMERA
- IRQ_CAMIF_C
- IRQ_CAMIF_MC
- IRQ_CAMIF_P
- IRQ_CAMIF_WE_C
- IRQ_CAPTURE
- IRQ_CAUSE_ERR_OFF
- IRQ_CAUSE_HIGH_OFF
- IRQ_CAUSE_LOW_OFF
- IRQ_CCA_COMPLETE
- IRQ_CCA_ED
- IRQ_CCERRINT
- IRQ_CCINT0
- IRQ_CF
- IRQ_CF0
- IRQ_CF1
- IRQ_CFCARD
- IRQ_CFCON
- IRQ_CFG_IRQ_BITS
- IRQ_CFG_IRQ_MASK
- IRQ_CFG_IRQ_PER_REG
- IRQ_CFG_REG
- IRQ_CF_CD
- IRQ_CF_IDE
- IRQ_CHIP
- IRQ_CIR
- IRQ_CLEAR
- IRQ_CNS3XXX_ARM11
- IRQ_CNS3XXX_CIM
- IRQ_CNS3XXX_CRYPTO
- IRQ_CNS3XXX_DMAC0
- IRQ_CNS3XXX_DMAC1
- IRQ_CNS3XXX_DMAC10
- IRQ_CNS3XXX_DMAC11
- IRQ_CNS3XXX_DMAC12
- IRQ_CNS3XXX_DMAC13
- IRQ_CNS3XXX_DMAC14
- IRQ_CNS3XXX_DMAC15
- IRQ_CNS3XXX_DMAC16
- IRQ_CNS3XXX_DMAC17
- IRQ_CNS3XXX_DMAC2
- IRQ_CNS3XXX_DMAC3
- IRQ_CNS3XXX_DMAC4
- IRQ_CNS3XXX_DMAC5
- IRQ_CNS3XXX_DMAC6
- IRQ_CNS3XXX_DMAC7
- IRQ_CNS3XXX_DMAC8
- IRQ_CNS3XXX_DMAC9
- IRQ_CNS3XXX_DMAC_ABORT
- IRQ_CNS3XXX_EXTERNAL_PIN0
- IRQ_CNS3XXX_EXTERNAL_PIN1
- IRQ_CNS3XXX_EXTERNAL_PIN2
- IRQ_CNS3XXX_GPIOA
- IRQ_CNS3XXX_GPIOB
- IRQ_CNS3XXX_GPU
- IRQ_CNS3XXX_HCIE
- IRQ_CNS3XXX_I2C
- IRQ_CNS3XXX_I2S
- IRQ_CNS3XXX_L2CC
- IRQ_CNS3XXX_LCD
- IRQ_CNS3XXX_PCIE0_DEVICE
- IRQ_CNS3XXX_PCIE0_RC
- IRQ_CNS3XXX_PCIE1_DEVICE
- IRQ_CNS3XXX_PCIE1_RC
- IRQ_CNS3XXX_PCM
- IRQ_CNS3XXX_PMU
- IRQ_CNS3XXX_RAID
- IRQ_CNS3XXX_RTC
- IRQ_CNS3XXX_SATA
- IRQ_CNS3XXX_SDIO
- IRQ_CNS3XXX_SMC
- IRQ_CNS3XXX_SPI
- IRQ_CNS3XXX_SW_PPE
- IRQ_CNS3XXX_SW_R0QE
- IRQ_CNS3XXX_SW_R0QF
- IRQ_CNS3XXX_SW_R0RXC
- IRQ_CNS3XXX_SW_R0TXC
- IRQ_CNS3XXX_SW_R1QE
- IRQ_CNS3XXX_SW_R1QF
- IRQ_CNS3XXX_SW_R1RXC
- IRQ_CNS3XXX_SW_R1TXC
- IRQ_CNS3XXX_SW_STATUS
- IRQ_CNS3XXX_TIMER0
- IRQ_CNS3XXX_TIMER1
- IRQ_CNS3XXX_TIMER2
- IRQ_CNS3XXX_UART0
- IRQ_CNS3XXX_UART1
- IRQ_CNS3XXX_UART2
- IRQ_CNS3XXX_USB_EHCI
- IRQ_CNS3XXX_USB_OHCI
- IRQ_CNS3XXX_USB_OTG
- IRQ_COAL
- IRQ_COAL_CAUSE
- IRQ_COAL_IO_THRESHOLD
- IRQ_COAL_TIME_THRESHOLD
- IRQ_COMMRX
- IRQ_COMMTX
- IRQ_COMM_WDT
- IRQ_CONNECT_STREAM_END
- IRQ_CONNECT_STREAM_NEXT
- IRQ_CONRX
- IRQ_CONTROL
- IRQ_CONTROL_ALL_IRQ_MASK
- IRQ_CONTROL_REG_OFFSET
- IRQ_CONTX
- IRQ_COUNT
- IRQ_COYOTE_IDE
- IRQ_CPU_TO_APU
- IRQ_CPU_TO_APU_ACK
- IRQ_CPU_TO_EPU
- IRQ_CPU_TO_EPU_ACK
- IRQ_CPU_TO_HPU
- IRQ_CPU_TO_HPU_ACK
- IRQ_CPU_TO_PPU
- IRQ_CPU_TO_PPU_ACK
- IRQ_CRC_ERR
- IRQ_CROSS_CALL
- IRQ_CSMA_CA
- IRQ_CTL_HI
- IRQ_CTRL_EVTQ_IRQEN
- IRQ_CTRL_GERROR_IRQEN
- IRQ_CTRL_IRQ_BITS
- IRQ_CTRL_IRQ_MASK
- IRQ_CTRL_IRQ_PER_REG
- IRQ_CTRL_PRIQ_IRQEN
- IRQ_CTRL_REG
- IRQ_CTS
- IRQ_CUI
- IRQ_DA830_BOOTCFGERR
- IRQ_DA830_EHRPWM2
- IRQ_DA830_EHRPWM2TZ
- IRQ_DA830_EQEP0
- IRQ_DA830_EQEP1
- IRQ_DA830_IOPUERR
- IRQ_DA830_MPUERR
- IRQ_DA830_T12CMPINT0_0
- IRQ_DA830_T12CMPINT0_1
- IRQ_DA830_T12CMPINT1_0
- IRQ_DA830_T12CMPINT1_1
- IRQ_DA830_T12CMPINT2_0
- IRQ_DA830_T12CMPINT2_1
- IRQ_DA830_T12CMPINT3_0
- IRQ_DA830_T12CMPINT3_1
- IRQ_DA830_T12CMPINT4_0
- IRQ_DA830_T12CMPINT4_1
- IRQ_DA830_T12CMPINT5_0
- IRQ_DA830_T12CMPINT5_1
- IRQ_DA830_T12CMPINT6_0
- IRQ_DA830_T12CMPINT6_1
- IRQ_DA830_T12CMPINT7_0
- IRQ_DA830_T12CMPINT7_1
- IRQ_DA850_BOOTCFG_ADDR_ERR
- IRQ_DA850_BOOTCFG_PROT_ERR
- IRQ_DA850_CCERRINT1
- IRQ_DA850_CCINT1
- IRQ_DA850_IOPUADDRERR0
- IRQ_DA850_IOPUADDRERR1
- IRQ_DA850_IOPUADDRERR2
- IRQ_DA850_IOPUADDRERR3
- IRQ_DA850_IOPUADDRERR4
- IRQ_DA850_IOPUADDRERR5
- IRQ_DA850_IOPUPROTERR0
- IRQ_DA850_IOPUPROTERR1
- IRQ_DA850_IOPUPROTERR2
- IRQ_DA850_IOPUPROTERR3
- IRQ_DA850_IOPUPROTERR4
- IRQ_DA850_IOPUPROTERR5
- IRQ_DA850_MCBSP0RINT
- IRQ_DA850_MCBSP0XINT
- IRQ_DA850_MCBSP1RINT
- IRQ_DA850_MCBSP1XINT
- IRQ_DA850_MIOPU_BOOTCFG_ERR
- IRQ_DA850_MMCSDINT0_1
- IRQ_DA850_MMCSDINT1_1
- IRQ_DA850_MPUADDRERR0
- IRQ_DA850_MPUADDRERR1
- IRQ_DA850_MPUPROTERR0
- IRQ_DA850_MPUPROTERR1
- IRQ_DA850_RPIINT
- IRQ_DA850_SATAINT
- IRQ_DA850_T12CMPINT0_2
- IRQ_DA850_T12CMPINT0_3
- IRQ_DA850_T12CMPINT1_2
- IRQ_DA850_T12CMPINT1_3
- IRQ_DA850_T12CMPINT2_2
- IRQ_DA850_T12CMPINT2_3
- IRQ_DA850_T12CMPINT3_2
- IRQ_DA850_T12CMPINT3_3
- IRQ_DA850_T12CMPINT4_2
- IRQ_DA850_T12CMPINT4_3
- IRQ_DA850_T12CMPINT5_2
- IRQ_DA850_T12CMPINT5_3
- IRQ_DA850_T12CMPINT6_2
- IRQ_DA850_T12CMPINT6_3
- IRQ_DA850_T12CMPINT7_2
- IRQ_DA850_T12CMPINT7_3
- IRQ_DA850_TCERRINT2
- IRQ_DA850_TINT12_2
- IRQ_DA850_TINT12_3
- IRQ_DA850_TINT34_2
- IRQ_DA850_TINT34_3
- IRQ_DA850_TINTALL_2
- IRQ_DA850_TINTALL_3
- IRQ_DA850_VPIFINT
- IRQ_DA8XX_AEMIFINT
- IRQ_DA8XX_ALLINT0
- IRQ_DA8XX_ALLINT1
- IRQ_DA8XX_ARMCLKSTOPREQ
- IRQ_DA8XX_C0_MISC_PULSE
- IRQ_DA8XX_C0_RX_PULSE
- IRQ_DA8XX_C0_RX_THRESH_PULSE
- IRQ_DA8XX_C0_TX_PULSE
- IRQ_DA8XX_C1_MISC_PULSE
- IRQ_DA8XX_C1_RX_PULSE
- IRQ_DA8XX_C1_RX_THRESH_PULSE
- IRQ_DA8XX_C1_TX_PULSE
- IRQ_DA8XX_CCERRINT
- IRQ_DA8XX_CCINT0
- IRQ_DA8XX_CHIPINT0
- IRQ_DA8XX_CHIPINT1
- IRQ_DA8XX_CHIPINT2
- IRQ_DA8XX_CHIPINT3
- IRQ_DA8XX_COMMRX
- IRQ_DA8XX_COMMTX
- IRQ_DA8XX_DFTSSINT
- IRQ_DA8XX_ECAP0
- IRQ_DA8XX_ECAP1
- IRQ_DA8XX_ECAP2
- IRQ_DA8XX_EHRPWM0
- IRQ_DA8XX_EHRPWM0TZ
- IRQ_DA8XX_EHRPWM1
- IRQ_DA8XX_EHRPWM1TZ
- IRQ_DA8XX_EVTOUT0
- IRQ_DA8XX_EVTOUT1
- IRQ_DA8XX_EVTOUT2
- IRQ_DA8XX_EVTOUT3
- IRQ_DA8XX_EVTOUT4
- IRQ_DA8XX_EVTOUT5
- IRQ_DA8XX_EVTOUT6
- IRQ_DA8XX_EVTOUT7
- IRQ_DA8XX_GPIO0
- IRQ_DA8XX_GPIO1
- IRQ_DA8XX_GPIO2
- IRQ_DA8XX_GPIO3
- IRQ_DA8XX_GPIO4
- IRQ_DA8XX_GPIO5
- IRQ_DA8XX_GPIO6
- IRQ_DA8XX_GPIO7
- IRQ_DA8XX_GPIO8
- IRQ_DA8XX_I2CINT0
- IRQ_DA8XX_I2CINT1
- IRQ_DA8XX_IRQN
- IRQ_DA8XX_KEYMGRINT
- IRQ_DA8XX_LCDINT
- IRQ_DA8XX_MCASPINT
- IRQ_DA8XX_MEMERR
- IRQ_DA8XX_MMCSDINT0
- IRQ_DA8XX_MMCSDINT1
- IRQ_DA8XX_NINT
- IRQ_DA8XX_RTC
- IRQ_DA8XX_RWAKEUP
- IRQ_DA8XX_SECINT
- IRQ_DA8XX_SECKEYERR
- IRQ_DA8XX_SPINT0
- IRQ_DA8XX_SPINT1
- IRQ_DA8XX_TCERRINT0
- IRQ_DA8XX_TCERRINT1
- IRQ_DA8XX_TINT12_0
- IRQ_DA8XX_TINT12_1
- IRQ_DA8XX_TINT34_0
- IRQ_DA8XX_TINT34_1
- IRQ_DA8XX_UARTINT0
- IRQ_DA8XX_UARTINT1
- IRQ_DA8XX_UARTINT2
- IRQ_DA8XX_UHPI_INT1
- IRQ_DA8XX_USB_INT
- IRQ_DAERR
- IRQ_DAS
- IRQ_DATAOVERRUN
- IRQ_DCD
- IRQ_DDR
- IRQ_DDRINT
- IRQ_DEBOUNCE_REG
- IRQ_DEBUG
- IRQ_DEDI
- IRQ_DEFAULT_INIT_FLAGS
- IRQ_DEF_ERRORS
- IRQ_DESC_ERR
- IRQ_DESC_TIMEOUT
- IRQ_DEVICE_NAME_MAX
- IRQ_DISABLE
- IRQ_DISABLE_UNLAZY
- IRQ_DISCARD_TIMER
- IRQ_DLY
- IRQ_DM355_CCDC_VDINT0
- IRQ_DM355_CCDC_VDINT1
- IRQ_DM355_CCDC_VDINT2
- IRQ_DM355_GPIO0
- IRQ_DM355_GPIO1
- IRQ_DM355_GPIO2
- IRQ_DM355_GPIO3
- IRQ_DM355_GPIO4
- IRQ_DM355_GPIO5
- IRQ_DM355_GPIO6
- IRQ_DM355_GPIO7
- IRQ_DM355_GPIO8
- IRQ_DM355_GPIO9
- IRQ_DM355_GPIOBNK0
- IRQ_DM355_GPIOBNK1
- IRQ_DM355_GPIOBNK2
- IRQ_DM355_GPIOBNK3
- IRQ_DM355_GPIOBNK4
- IRQ_DM355_GPIOBNK5
- IRQ_DM355_GPIOBNK6
- IRQ_DM355_H3AINT
- IRQ_DM355_IMCOPINT
- IRQ_DM355_IPIPEIFINT
- IRQ_DM355_IPIPE_HST
- IRQ_DM355_IPIPE_SDR
- IRQ_DM355_MMCINT0
- IRQ_DM355_MMCINT1
- IRQ_DM355_MSINT
- IRQ_DM355_OSDINT
- IRQ_DM355_PWMINT3
- IRQ_DM355_RTOINT
- IRQ_DM355_SDIOINT0
- IRQ_DM355_SDIOINT1
- IRQ_DM355_SPINT0_0
- IRQ_DM355_SPINT0_1
- IRQ_DM355_SPINT1_0
- IRQ_DM355_SPINT1_1
- IRQ_DM355_SPINT2_0
- IRQ_DM355_SPINT2_1
- IRQ_DM355_TINT2_TINT12
- IRQ_DM355_TINT2_TINT34
- IRQ_DM355_TINT3_TINT12
- IRQ_DM355_TINT3_TINT34
- IRQ_DM355_TINT4
- IRQ_DM355_TINT5
- IRQ_DM355_TINT6
- IRQ_DM355_TINT7
- IRQ_DM355_UARTINT2
- IRQ_DM355_VENCINT
- IRQ_DM365_ADCINT
- IRQ_DM365_EMAC_MISCPULSE
- IRQ_DM365_EMAC_RXPULSE
- IRQ_DM365_EMAC_RXTHRESH
- IRQ_DM365_EMAC_TXPULSE
- IRQ_DM365_EMUINT
- IRQ_DM365_GPIO0
- IRQ_DM365_GPIO1
- IRQ_DM365_GPIO12
- IRQ_DM365_GPIO13
- IRQ_DM365_GPIO14
- IRQ_DM365_GPIO15
- IRQ_DM365_GPIO2
- IRQ_DM365_GPIO3
- IRQ_DM365_GPIO4
- IRQ_DM365_GPIO5
- IRQ_DM365_GPIO6
- IRQ_DM365_GPIO7
- IRQ_DM365_IMCOPINT
- IRQ_DM365_IMXINT0
- IRQ_DM365_IMXINT1
- IRQ_DM365_INSFINT
- IRQ_DM365_KEYINT
- IRQ_DM365_KLD_ARMINT
- IRQ_DM365_MMCINT1
- IRQ_DM365_PWMINT3
- IRQ_DM365_RTCINT
- IRQ_DM365_RTOINT
- IRQ_DM365_SDIOINT0
- IRQ_DM365_SDIOINT1
- IRQ_DM365_SPIINT0_0
- IRQ_DM365_SPIINT3_0
- IRQ_DM365_SPINT2_1
- IRQ_DM365_TCERRINT2
- IRQ_DM365_TCERRINT3
- IRQ_DM365_TINT5
- IRQ_DM365_TINT6
- IRQ_DM365_TINT7
- IRQ_DM646X_AEMIFINT
- IRQ_DM646X_CRGENINT0
- IRQ_DM646X_CRGENINT1
- IRQ_DM646X_DDRINT
- IRQ_DM646X_DSP2ARMINT
- IRQ_DM646X_EMACMISCINT
- IRQ_DM646X_EMACRXINT
- IRQ_DM646X_EMACRXTHINT
- IRQ_DM646X_EMACTXINT
- IRQ_DM646X_GPIO0
- IRQ_DM646X_GPIO1
- IRQ_DM646X_GPIO2
- IRQ_DM646X_GPIO3
- IRQ_DM646X_GPIO4
- IRQ_DM646X_GPIO5
- IRQ_DM646X_GPIO6
- IRQ_DM646X_GPIO7
- IRQ_DM646X_GPIOBNK0
- IRQ_DM646X_GPIOBNK1
- IRQ_DM646X_GPIOBNK2
- IRQ_DM646X_HPIINT
- IRQ_DM646X_IDE
- IRQ_DM646X_MCASP0RXINT
- IRQ_DM646X_MCASP0TXINT
- IRQ_DM646X_MCASP1TXINT
- IRQ_DM646X_PCIINT
- IRQ_DM646X_PSCINT
- IRQ_DM646X_RESERVED_1
- IRQ_DM646X_RESERVED_2
- IRQ_DM646X_RESERVED_3
- IRQ_DM646X_RESERVED_4
- IRQ_DM646X_SPINT0
- IRQ_DM646X_SPINT1
- IRQ_DM646X_TCERRINT2
- IRQ_DM646X_TCERRINT3
- IRQ_DM646X_TSIFINT0
- IRQ_DM646X_TSIFINT1
- IRQ_DM646X_UARTINT2
- IRQ_DM646X_USBDMAINT
- IRQ_DM646X_USBINT
- IRQ_DM646X_VDCEINT
- IRQ_DM646X_VLQINT
- IRQ_DM646X_VP_ERRINT
- IRQ_DM646X_VP_VERTINT0
- IRQ_DM646X_VP_VERTINT1
- IRQ_DM646X_VP_VERTINT2
- IRQ_DM646X_VP_VERTINT3
- IRQ_DM646X_WDINT
- IRQ_DMA
- IRQ_DMA0
- IRQ_DMA0_EOC
- IRQ_DMA0_EOT
- IRQ_DMA0_ERR
- IRQ_DMA1
- IRQ_DMA1_EOC
- IRQ_DMA1_EOT
- IRQ_DMA1_ERR
- IRQ_DMA2
- IRQ_DMA3
- IRQ_DMA4
- IRQ_DMA5
- IRQ_DMAERR
- IRQ_DMAS0
- IRQ_DMAS1
- IRQ_DMA_CNTRL_REG
- IRQ_DMA_WD_CNT_MASK
- IRQ_DMEMC
- IRQ_DMTE0
- IRQ_DMTE1
- IRQ_DMTE2
- IRQ_DMTE3
- IRQ_DOI
- IRQ_DOMAIN_FLAG_HIERARCHY
- IRQ_DOMAIN_FLAG_IPI_PER_CPU
- IRQ_DOMAIN_FLAG_IPI_SINGLE
- IRQ_DOMAIN_FLAG_MSI
- IRQ_DOMAIN_FLAG_MSI_REMAP
- IRQ_DOMAIN_FLAG_NONCORE
- IRQ_DOMAIN_IRQ_SPEC_PARAMS
- IRQ_DOMAIN_MSI_NOMASK_QUIRK
- IRQ_DOMAIN_NAME_ALLOCATED
- IRQ_DONT_CARE_BITS
- IRQ_DOORBELLHOST
- IRQ_DOVE_AC97
- IRQ_DOVE_BRIDGE
- IRQ_DOVE_C2H
- IRQ_DOVE_CAM
- IRQ_DOVE_CRYPTO
- IRQ_DOVE_CRYPTO_ERR
- IRQ_DOVE_GE00_ERR
- IRQ_DOVE_GE00_MISC
- IRQ_DOVE_GE00_RX
- IRQ_DOVE_GE00_SUM
- IRQ_DOVE_GE00_TX
- IRQ_DOVE_GPIO_0_7
- IRQ_DOVE_GPIO_16_23
- IRQ_DOVE_GPIO_24_31
- IRQ_DOVE_GPIO_8_15
- IRQ_DOVE_GPIO_START
- IRQ_DOVE_GPU
- IRQ_DOVE_H2C
- IRQ_DOVE_HIGH_GPIO
- IRQ_DOVE_I2C
- IRQ_DOVE_I2S0
- IRQ_DOVE_I2S0_ERR
- IRQ_DOVE_I2S1
- IRQ_DOVE_I2S1_ERR
- IRQ_DOVE_LCD0
- IRQ_DOVE_LCD1
- IRQ_DOVE_LCD_DCON
- IRQ_DOVE_MC_L2_ERR
- IRQ_DOVE_NAND
- IRQ_DOVE_PCIE0
- IRQ_DOVE_PCIE0_ERR
- IRQ_DOVE_PCIE1
- IRQ_DOVE_PCIE1_ERR
- IRQ_DOVE_PDMA
- IRQ_DOVE_PERFORM_MNTR
- IRQ_DOVE_PMU
- IRQ_DOVE_PMU_START
- IRQ_DOVE_RTC
- IRQ_DOVE_SATA
- IRQ_DOVE_SDIO0
- IRQ_DOVE_SDIO0_WAKEUP
- IRQ_DOVE_SDIO1
- IRQ_DOVE_SDIO1_WAKEUP
- IRQ_DOVE_SPI0
- IRQ_DOVE_SPI1
- IRQ_DOVE_SSP
- IRQ_DOVE_SSP_TIMER
- IRQ_DOVE_UART_0
- IRQ_DOVE_UART_1
- IRQ_DOVE_UART_2
- IRQ_DOVE_UART_3
- IRQ_DOVE_USB0
- IRQ_DOVE_USB1
- IRQ_DOVE_USB_ERR
- IRQ_DOVE_VPRO_DMA1
- IRQ_DOVE_XOR0_ERR
- IRQ_DOVE_XOR1_ERR
- IRQ_DOVE_XOR_00
- IRQ_DOVE_XOR_01
- IRQ_DOVE_XOR_10
- IRQ_DOVE_XOR_11
- IRQ_DPE
- IRQ_DPED
- IRQ_DSL
- IRQ_DSP2ARM0
- IRQ_DSP2ARM1
- IRQ_DSR
- IRQ_EBSA110_COM1
- IRQ_EBSA110_COM2
- IRQ_EBSA110_ETHERNET
- IRQ_EBSA110_IMMEDIATE
- IRQ_EBSA110_PCMCIA
- IRQ_EBSA110_PRINTER
- IRQ_EBSA110_TIMER0
- IRQ_EBSA110_TIMER1
- IRQ_EDGE_BOTH
- IRQ_EDGE_FALLING
- IRQ_EDGE_HIGH
- IRQ_EDGE_RISING
- IRQ_EDI
- IRQ_EHCI0
- IRQ_EI
- IRQ_EINT
- IRQ_EINT0
- IRQ_EINT0_2412
- IRQ_EINT0_3
- IRQ_EINT1
- IRQ_EINT10
- IRQ_EINT11
- IRQ_EINT12
- IRQ_EINT12_19
- IRQ_EINT13
- IRQ_EINT14
- IRQ_EINT15
- IRQ_EINT16
- IRQ_EINT17
- IRQ_EINT18
- IRQ_EINT19
- IRQ_EINT1_2412
- IRQ_EINT2
- IRQ_EINT20
- IRQ_EINT20_27
- IRQ_EINT21
- IRQ_EINT22
- IRQ_EINT23
- IRQ_EINT2_2412
- IRQ_EINT3
- IRQ_EINT3_2412
- IRQ_EINT4
- IRQ_EINT4_11
- IRQ_EINT4t7
- IRQ_EINT5
- IRQ_EINT6
- IRQ_EINT7
- IRQ_EINT8
- IRQ_EINT8t23
- IRQ_EINT9
- IRQ_EINT_BIT
- IRQ_EINT_GROUP
- IRQ_EINT_GROUP1_BASE
- IRQ_EINT_GROUP1_NR
- IRQ_EINT_GROUP2_BASE
- IRQ_EINT_GROUP2_NR
- IRQ_EINT_GROUP3_BASE
- IRQ_EINT_GROUP3_NR
- IRQ_EINT_GROUP4_BASE
- IRQ_EINT_GROUP4_NR
- IRQ_EINT_GROUP5_BASE
- IRQ_EINT_GROUP5_NR
- IRQ_EINT_GROUP6_BASE
- IRQ_EINT_GROUP6_NR
- IRQ_EINT_GROUP7_BASE
- IRQ_EINT_GROUP7_NR
- IRQ_EINT_GROUP8_BASE
- IRQ_EINT_GROUP8_NR
- IRQ_EINT_GROUP9_BASE
- IRQ_EINT_GROUP9_NR
- IRQ_EINT_GROUP_BASE
- IRQ_EMACINT
- IRQ_EMUINT
- IRQ_EN
- IRQ_ENABLE
- IRQ_ENABLES_MASK
- IRQ_ENABLES_SHIFT
- IRQ_ENABLE_BANK
- IRQ_ENABLE_CLEAR
- IRQ_ENABLE_SET
- IRQ_ENA_ALL
- IRQ_ENA_PORT0
- IRQ_ENA_PORT0_MASK
- IRQ_END_CONNECTION
- IRQ_END_OF_CHAIN
- IRQ_ENET0
- IRQ_ENET0_RXDMA
- IRQ_ENET0_TXDMA
- IRQ_ENET1
- IRQ_ENET1_RXDMA
- IRQ_ENET1_TXDMA
- IRQ_ENETSW_RXDMA0
- IRQ_ENETSW_RXDMA1
- IRQ_ENETSW_RXDMA2
- IRQ_ENETSW_RXDMA3
- IRQ_ENETSW_TXDMA0
- IRQ_ENETSW_TXDMA1
- IRQ_ENETSW_TXDMA2
- IRQ_ENETSW_TXDMA3
- IRQ_ENET_PHY
- IRQ_ENHROT
- IRQ_ENTER
- IRQ_ENTRY
- IRQ_EN_ADDR
- IRQ_EN_CLR
- IRQ_EN_MASK
- IRQ_EN_SET
- IRQ_EOF0
- IRQ_EOF1
- IRQ_EOF2
- IRQ_EOI
- IRQ_EP93XX_1HZ
- IRQ_EP93XX_64HZ
- IRQ_EP93XX_AACINTR
- IRQ_EP93XX_COMMRX
- IRQ_EP93XX_COMMTX
- IRQ_EP93XX_DMAM2M0
- IRQ_EP93XX_DMAM2M1
- IRQ_EP93XX_DMAM2P0
- IRQ_EP93XX_DMAM2P1
- IRQ_EP93XX_DMAM2P2
- IRQ_EP93XX_DMAM2P3
- IRQ_EP93XX_DMAM2P4
- IRQ_EP93XX_DMAM2P5
- IRQ_EP93XX_DMAM2P6
- IRQ_EP93XX_DMAM2P7
- IRQ_EP93XX_DMAM2P8
- IRQ_EP93XX_DMAM2P9
- IRQ_EP93XX_DSP
- IRQ_EP93XX_ETHERNET
- IRQ_EP93XX_ETHERNET_PME
- IRQ_EP93XX_EXT0
- IRQ_EP93XX_EXT1
- IRQ_EP93XX_EXT2
- IRQ_EP93XX_EXT3
- IRQ_EP93XX_GPIO0MUX
- IRQ_EP93XX_GPIO1MUX
- IRQ_EP93XX_GPIO2MUX
- IRQ_EP93XX_GPIO3MUX
- IRQ_EP93XX_GPIO4MUX
- IRQ_EP93XX_GPIO5MUX
- IRQ_EP93XX_GPIO6MUX
- IRQ_EP93XX_GPIO7MUX
- IRQ_EP93XX_GPIO_AB
- IRQ_EP93XX_IRDA
- IRQ_EP93XX_KEY
- IRQ_EP93XX_PROG
- IRQ_EP93XX_RTC
- IRQ_EP93XX_SAI
- IRQ_EP93XX_SSP
- IRQ_EP93XX_SSP1RX
- IRQ_EP93XX_SSP1TX
- IRQ_EP93XX_TIMER1
- IRQ_EP93XX_TIMER2
- IRQ_EP93XX_TIMER3
- IRQ_EP93XX_TOUCH
- IRQ_EP93XX_UART1
- IRQ_EP93XX_UART1RX
- IRQ_EP93XX_UART1TX
- IRQ_EP93XX_UART2
- IRQ_EP93XX_UART2RX
- IRQ_EP93XX_UART2TX
- IRQ_EP93XX_UART3
- IRQ_EP93XX_UART3RX
- IRQ_EP93XX_UART3TX
- IRQ_EP93XX_USB
- IRQ_EP93XX_VIDEO_FIFO
- IRQ_EP93XX_VSYNC
- IRQ_EP93XX_WATCHDOG
- IRQ_EPI
- IRQ_EPU_TO_APU
- IRQ_EPU_TO_APU_ACK
- IRQ_EPU_TO_CPU
- IRQ_EPU_TO_CPU_ACK
- IRQ_EPU_TO_HPU
- IRQ_EPU_TO_HPU_ACK
- IRQ_EPU_TO_PPU
- IRQ_EPU_TO_PPU_ACK
- IRQ_ERI
- IRQ_ERR
- IRQ_ERR_MASK
- IRQ_ETH0
- IRQ_ETH1
- IRQ_ETHERNET
- IRQ_EVENT_ID_MASK
- IRQ_EVENT_ID_SHIFT
- IRQ_EXIT
- IRQ_EXITHUNT
- IRQ_EXPANSIONCARD
- IRQ_EXPCARDFIQ
- IRQ_EXT
- IRQ_EXT0
- IRQ_EXT1
- IRQ_EXT2
- IRQ_EXT3
- IRQ_EXT4
- IRQ_EXT5
- IRQ_EXT6
- IRQ_EXT7
- IRQ_EXTERNAL_BASE
- IRQ_EXT_0
- IRQ_EXT_1
- IRQ_EXT_2
- IRQ_EXT_3
- IRQ_EXT_REG
- IRQ_FATA
- IRQ_FATAL
- IRQ_FAULT
- IRQ_FFUART
- IRQ_FIFO
- IRQ_FINISHED_DMABUF_1
- IRQ_FINISHED_DMABUF_2
- IRQ_FLOPPYDISK
- IRQ_FLOPPYINDEX
- IRQ_FMN
- IRQ_FORCED
- IRQ_FRAME_VALID
- IRQ_FREE
- IRQ_GAMEPORT
- IRQ_GCU
- IRQ_GC_BE_IO
- IRQ_GC_INIT_MASK_CACHE
- IRQ_GC_INIT_NESTED_LOCK
- IRQ_GC_MASK_CACHE_PER_TYPE
- IRQ_GC_NO_MASK
- IRQ_GENERAL
- IRQ_GET_DESC_CHECK_GLOBAL
- IRQ_GET_DESC_CHECK_PERCPU
- IRQ_GIC_END
- IRQ_GLOBAL_CLEAR
- IRQ_GMR_REG_OFFSET
- IRQ_GPAIN0
- IRQ_GPAIN1
- IRQ_GPAIN2
- IRQ_GPAIN3
- IRQ_GPBIN0
- IRQ_GPBIN1
- IRQ_GPBIN2
- IRQ_GPBIN3
- IRQ_GPBIN4
- IRQ_GPBIN5
- IRQ_GPCIN0
- IRQ_GPCIN1
- IRQ_GPCIN2
- IRQ_GPCIN3
- IRQ_GPCIN4
- IRQ_GPCIN5
- IRQ_GPCIN6
- IRQ_GPCIN7
- IRQ_GPIO0
- IRQ_GPIO0_SC
- IRQ_GPIO1
- IRQ_GPIO10
- IRQ_GPIO10_SC
- IRQ_GPIO11
- IRQ_GPIO11_27
- IRQ_GPIO12
- IRQ_GPIO13
- IRQ_GPIO14
- IRQ_GPIO15
- IRQ_GPIO16
- IRQ_GPIO17
- IRQ_GPIO18
- IRQ_GPIO19
- IRQ_GPIO1_SC
- IRQ_GPIO2
- IRQ_GPIO20
- IRQ_GPIO21
- IRQ_GPIO22
- IRQ_GPIO23
- IRQ_GPIO24
- IRQ_GPIO25
- IRQ_GPIO26
- IRQ_GPIO27
- IRQ_GPIO2_SC
- IRQ_GPIO3
- IRQ_GPIO3_SC
- IRQ_GPIO4
- IRQ_GPIO4_SC
- IRQ_GPIO5
- IRQ_GPIO5_SC
- IRQ_GPIO6
- IRQ_GPIO6_SC
- IRQ_GPIO7
- IRQ_GPIO7_SC
- IRQ_GPIO8
- IRQ_GPIO8_SC
- IRQ_GPIO9
- IRQ_GPIO9_SC
- IRQ_GPIOBNK0
- IRQ_GPIOBNK1
- IRQ_GPIOBNK2
- IRQ_GPIOBNK3
- IRQ_GPIOBNK4
- IRQ_GPIOHIGH
- IRQ_GPIOLOW0
- IRQ_GPIOLOW1
- IRQ_GPIOLOW2
- IRQ_GPIOLOW3
- IRQ_GPIOLOW4
- IRQ_GPIOLOW5
- IRQ_GPIOLOW6
- IRQ_GPIOLOW7
- IRQ_GPIO_2_x
- IRQ_GPIO_ETH0_IRQ
- IRQ_GPIO_PALMLD_GPIO_RESET
- IRQ_GPIO_PALMLD_IDE_IRQ
- IRQ_GPIO_PALMLD_SD_DETECT_N
- IRQ_GPIO_PALMLD_WM9712_IRQ
- IRQ_GPIO_PALMT5_GPIO_RESET
- IRQ_GPIO_PALMT5_SD_DETECT_N
- IRQ_GPIO_PALMT5_USB_DETECT
- IRQ_GPIO_PALMT5_WM9712_IRQ
- IRQ_GPIO_PALMTC_SD_DETECT_N
- IRQ_GPIO_PALMTC_WLAN_READY
- IRQ_GPIO_PALMTX_GPIO_RESET
- IRQ_GPIO_PALMTX_SD_DETECT_N
- IRQ_GPIO_PALMTX_USB_DETECT
- IRQ_GPIO_PALMTX_WM9712_IRQ
- IRQ_GPIO_PIN
- IRQ_GPIO_POWER_BUTTON
- IRQ_GPIO_SMARD_CARD
- IRQ_GPIO_START
- IRQ_GPIO_UCB1300_IRQ
- IRQ_GRU
- IRQ_H3AINT
- IRQ_HALF
- IRQ_HANDLE
- IRQ_HANDLED
- IRQ_HANDLE_BYTE
- IRQ_HANDLE_NIBBLE
- IRQ_HARDDISK
- IRQ_HCIBUFFACC
- IRQ_HCIM
- IRQ_HCIRMTWKP
- IRQ_HEAD
- IRQ_HISTINT
- IRQ_HOSTIF
- IRQ_HPIINT
- IRQ_HPU_TO_APU
- IRQ_HPU_TO_APU_ACK
- IRQ_HPU_TO_CPU
- IRQ_HPU_TO_CPU_ACK
- IRQ_HPU_TO_EPU
- IRQ_HPU_TO_EPU_ACK
- IRQ_HPU_TO_PPU
- IRQ_HPU_TO_PPU_ACK
- IRQ_HSIrx
- IRQ_HSItx
- IRQ_HSMMC0
- IRQ_HSMMC1
- IRQ_HSMMC2
- IRQ_HSSPI
- IRQ_HWUART
- IRQ_I2C
- IRQ_I2C_READY
- IRQ_I2OINPOST
- IRQ_I2S
- IRQ_I2S0
- IRQ_I2S_OUT
- IRQ_I8259_CASCADE
- IRQ_ICP
- IRQ_ID
- IRQ_IDE
- IRQ_IDE0
- IRQ_IDX
- IRQ_ID_SIZE
- IRQ_IFCP_1
- IRQ_IFCP_2
- IRQ_IFCP_3
- IRQ_IFCP_4
- IRQ_IIC
- IRQ_IIC1
- IRQ_ILR0_REG_OFFSET
- IRQ_IMMEDIATE
- IRQ_IMXINT
- IRQ_IN0
- IRQ_IN1
- IRQ_IN2
- IRQ_IN3
- IRQ_INDEX
- IRQ_INFO2_VALID
- IRQ_INPROGRESS
- IRQ_INTA
- IRQ_INTA_ASSERT
- IRQ_INTB
- IRQ_INTB_ASSERT
- IRQ_INTC
- IRQ_INTC_ASSERT
- IRQ_INTD
- IRQ_INTD_ASSERT
- IRQ_INTERNAL_BASE
- IRQ_INTERVAL
- IRQ_INTX
- IRQ_INT_A
- IRQ_INT_B
- IRQ_INT_C
- IRQ_INT_D
- IRQ_INT_MULTI_RXRDY
- IRQ_INT_RX_RDY
- IRQ_INT_TX_FIFO_EMPTY
- IRQ_INT_TX_PER_PACKET
- IRQ_IN_COMBINER
- IRQ_IOP32X_AA_EOC
- IRQ_IOP32X_AA_EOT
- IRQ_IOP32X_AA_ERR
- IRQ_IOP32X_ATU_BIST
- IRQ_IOP32X_ATU_ERR
- IRQ_IOP32X_BIU_ERR
- IRQ_IOP32X_CORE_PMON
- IRQ_IOP32X_CORE_PMU
- IRQ_IOP32X_DMA0_EOC
- IRQ_IOP32X_DMA0_EOT
- IRQ_IOP32X_DMA0_ERR
- IRQ_IOP32X_DMA1_EOC
- IRQ_IOP32X_DMA1_EOT
- IRQ_IOP32X_DMA1_ERR
- IRQ_IOP32X_HPI
- IRQ_IOP32X_I2C_0
- IRQ_IOP32X_I2C_1
- IRQ_IOP32X_MCU_ERR
- IRQ_IOP32X_MESSAGING
- IRQ_IOP32X_MSG_ERR
- IRQ_IOP32X_PERFMON
- IRQ_IOP32X_SSP
- IRQ_IOP32X_TIMER0
- IRQ_IOP32X_TIMER1
- IRQ_IOP32X_XINT0
- IRQ_IOP32X_XINT1
- IRQ_IOP32X_XINT2
- IRQ_IOP32X_XINT3
- IRQ_IPI_MASK
- IRQ_IPI_RESCHED
- IRQ_IPI_SINGLE
- IRQ_IPI_SMP_FUNCTION
- IRQ_IPI_SMP_RESCHEDULE
- IRQ_IRDA
- IRQ_IRL0
- IRQ_IRL1
- IRQ_IRL2
- IRQ_IRL3
- IRQ_ISA_2
- IRQ_ISA_CASCADE
- IRQ_ISA_FLOPPY
- IRQ_ISA_HARDDISK1
- IRQ_ISA_HARDDISK2
- IRQ_ISA_KEYBOARD
- IRQ_ISA_PRINTER
- IRQ_ISA_PS2MOUSE
- IRQ_ISA_RTC_ALARM
- IRQ_ISA_TIMER
- IRQ_ISA_UART
- IRQ_ISA_UART2
- IRQ_ISR_REG_OFFSET
- IRQ_IS_POLLED
- IRQ_ITI
- IRQ_ITR_REG_OFFSET
- IRQ_IXP4XX_AHB_PMU
- IRQ_IXP4XX_BASE
- IRQ_IXP4XX_EAU_DONE
- IRQ_IXP4XX_EXP_PE
- IRQ_IXP4XX_GPIO0
- IRQ_IXP4XX_GPIO1
- IRQ_IXP4XX_GPIO10
- IRQ_IXP4XX_GPIO11
- IRQ_IXP4XX_GPIO12
- IRQ_IXP4XX_GPIO2
- IRQ_IXP4XX_GPIO3
- IRQ_IXP4XX_GPIO4
- IRQ_IXP4XX_GPIO5
- IRQ_IXP4XX_GPIO6
- IRQ_IXP4XX_GPIO7
- IRQ_IXP4XX_GPIO8
- IRQ_IXP4XX_GPIO9
- IRQ_IXP4XX_I2C
- IRQ_IXP4XX_MCU_ECC
- IRQ_IXP4XX_NPEA
- IRQ_IXP4XX_NPEB
- IRQ_IXP4XX_NPEC
- IRQ_IXP4XX_PCI_DMA1
- IRQ_IXP4XX_PCI_DMA2
- IRQ_IXP4XX_PCI_INT
- IRQ_IXP4XX_QM1
- IRQ_IXP4XX_QM2
- IRQ_IXP4XX_QM_PE
- IRQ_IXP4XX_SHA_DONE
- IRQ_IXP4XX_SSP
- IRQ_IXP4XX_SWCP_PE
- IRQ_IXP4XX_SW_INT1
- IRQ_IXP4XX_SW_INT2
- IRQ_IXP4XX_TIMER1
- IRQ_IXP4XX_TIMER2
- IRQ_IXP4XX_TIMESTAMP
- IRQ_IXP4XX_TSYNC
- IRQ_IXP4XX_UART1
- IRQ_IXP4XX_UART2
- IRQ_IXP4XX_USB
- IRQ_IXP4XX_USB_HOST
- IRQ_IXP4XX_WDOG
- IRQ_IXP4XX_XSCALE_PMU
- IRQ_JPEG
- IRQ_KEY
- IRQ_KEYBOARD
- IRQ_KEYBOARDRX
- IRQ_KEYBOARDTX
- IRQ_KEYPAD
- IRQ_LCD
- IRQ_LCD_FIFO
- IRQ_LCD_FRAME
- IRQ_LCD_SYSTEM
- IRQ_LCD_VSYNC
- IRQ_LCI
- IRQ_LDI
- IRQ_LEVEL
- IRQ_LEVEL2
- IRQ_LEVEL_HIGH
- IRQ_LEVEL_LOW
- IRQ_LINE0
- IRQ_LINE1
- IRQ_LINES
- IRQ_LINK_CHANGE
- IRQ_LOCALTIMER
- IRQ_LOCOMO_GPIO
- IRQ_LOCOMO_KEY
- IRQ_LOCOMO_LT
- IRQ_LOCOMO_SPI
- IRQ_LVL_BITS
- IRQ_MAC_ADB
- IRQ_MAC_ADB_CL
- IRQ_MAC_ADB_SD
- IRQ_MAC_ADB_SR
- IRQ_MAC_MACE
- IRQ_MAC_MACE_DMA
- IRQ_MAC_NUBUS
- IRQ_MAC_SCC
- IRQ_MAC_SCC_A
- IRQ_MAC_SCC_B
- IRQ_MAC_SCSI
- IRQ_MAC_SCSIDRQ
- IRQ_MAC_TIMER_1
- IRQ_MAC_TIMER_2
- IRQ_MAC_VBL
- IRQ_MAGICIAN_BT
- IRQ_MAGICIAN_EP
- IRQ_MAGICIAN_SD
- IRQ_MAGICIAN_VBUS
- IRQ_MAP_EEPROM_DATA
- IRQ_MAP_LEN
- IRQ_MASK
- IRQ_MASK_BASE
- IRQ_MASK_BIT
- IRQ_MASK_DISCARD_TIMER
- IRQ_MASK_DMA1
- IRQ_MASK_DMA2
- IRQ_MASK_DOORBELLHOST
- IRQ_MASK_ERR_OFF
- IRQ_MASK_FEC_LOCK
- IRQ_MASK_HIGH
- IRQ_MASK_HIGH_OFF
- IRQ_MASK_I2OINPOST
- IRQ_MASK_IN0
- IRQ_MASK_IN1
- IRQ_MASK_IN2
- IRQ_MASK_IN3
- IRQ_MASK_LOW
- IRQ_MASK_LOW_OFF
- IRQ_MASK_PCI
- IRQ_MASK_PCI_ABORT
- IRQ_MASK_PCI_DPERR
- IRQ_MASK_PCI_PERR
- IRQ_MASK_PCI_SERR
- IRQ_MASK_REG
- IRQ_MASK_SDRAMPARITY
- IRQ_MASK_TIMER1
- IRQ_MASK_TIMER2
- IRQ_MASK_TIMER3
- IRQ_MASK_UART_RX
- IRQ_MASK_UART_TX
- IRQ_MASTER
- IRQ_MATRIX_BITS
- IRQ_MATRIX_SIZE
- IRQ_MAX
- IRQ_MBRINT
- IRQ_MBXINT
- IRQ_MCLR
- IRQ_MEMSTK
- IRQ_MEM_SIZE
- IRQ_MESSAGE
- IRQ_MESS_READ_END
- IRQ_MESS_READ_NEXT
- IRQ_MESS_WRITE_END
- IRQ_MESS_WRITE_NEXT
- IRQ_MFC
- IRQ_MFP_ACIA
- IRQ_MFP_ACSI
- IRQ_MFP_BUSY
- IRQ_MFP_CTS
- IRQ_MFP_DCD
- IRQ_MFP_FDC
- IRQ_MFP_FSCSI
- IRQ_MFP_GPU
- IRQ_MFP_IDE
- IRQ_MFP_MMD
- IRQ_MFP_RECERR
- IRQ_MFP_RECFULL
- IRQ_MFP_RI
- IRQ_MFP_SEREMPT
- IRQ_MFP_SERERR
- IRQ_MFP_TIMA
- IRQ_MFP_TIMB
- IRQ_MFP_TIMC
- IRQ_MFP_TIMD
- IRQ_MFP_TIMER1
- IRQ_MFP_TIMER2
- IRQ_MFP_TIMER3
- IRQ_MFP_TIMER4
- IRQ_MFP_TIMER5
- IRQ_MFP_TIMER6
- IRQ_MFP_TIMER7
- IRQ_MFP_TIMER8
- IRQ_MIDI
- IRQ_MIN
- IRQ_MIR_REG_OFFSET
- IRQ_MMC
- IRQ_MMC2
- IRQ_MMC3
- IRQ_MMCINT
- IRQ_MME
- IRQ_MMP2_CHARGER
- IRQ_MMP2_CI
- IRQ_MMP2_CI2
- IRQ_MMP2_COMMRX
- IRQ_MMP2_COMMTX
- IRQ_MMP2_CORESIGHT
- IRQ_MMP2_DDR
- IRQ_MMP2_DMA_FIQ
- IRQ_MMP2_DMA_RIQ
- IRQ_MMP2_FAB0_TIMEOUT
- IRQ_MMP2_FAB1_TIMEOUT
- IRQ_MMP2_FAB2_TIMEOUT
- IRQ_MMP2_GPIO
- IRQ_MMP2_GPU
- IRQ_MMP2_HDMI
- IRQ_MMP2_HSI0_CAWAKE
- IRQ_MMP2_HSI1_CAWAKE
- IRQ_MMP2_IRE
- IRQ_MMP2_KEYPAD_BASE
- IRQ_MMP2_KEYPAD_MUX
- IRQ_MMP2_KPC
- IRQ_MMP2_L2_ECC
- IRQ_MMP2_L2_PA_ECC
- IRQ_MMP2_L2_UECC
- IRQ_MMP2_LCD
- IRQ_MMP2_MAIN_PMU
- IRQ_MMP2_MIPI_DSI
- IRQ_MMP2_MIPI_HSI0_BASE
- IRQ_MMP2_MIPI_HSI0_MUX
- IRQ_MMP2_MIPI_HSI1_BASE
- IRQ_MMP2_MIPI_HSI1_MUX
- IRQ_MMP2_MIPI_HSI_INT0
- IRQ_MMP2_MIPI_HSI_INT1
- IRQ_MMP2_MIPI_SLIM
- IRQ_MMP2_MIPI_SLIM_DMA
- IRQ_MMP2_MISC_BASE
- IRQ_MMP2_MISC_MUX
- IRQ_MMP2_MMC
- IRQ_MMP2_MMC2
- IRQ_MMP2_MMC3
- IRQ_MMP2_MMC4
- IRQ_MMP2_MSP
- IRQ_MMP2_MUX_BASE
- IRQ_MMP2_MUX_END
- IRQ_MMP2_NAND
- IRQ_MMP2_NAND_DMA
- IRQ_MMP2_NONE
- IRQ_MMP2_ONEWIRE
- IRQ_MMP2_PERF
- IRQ_MMP2_PJ4_FREQ_CHG
- IRQ_MMP2_PMIC
- IRQ_MMP2_PMIC_BASE
- IRQ_MMP2_PMIC_MUX
- IRQ_MMP2_PMU_TIMER1
- IRQ_MMP2_PMU_TIMER2
- IRQ_MMP2_PMU_TIMER3
- IRQ_MMP2_RIPC
- IRQ_MMP2_ROTARY
- IRQ_MMP2_ROTORY
- IRQ_MMP2_RTC
- IRQ_MMP2_RTC_ALARM
- IRQ_MMP2_RTC_BASE
- IRQ_MMP2_RTC_MUX
- IRQ_MMP2_SM
- IRQ_MMP2_SSP1
- IRQ_MMP2_SSP2
- IRQ_MMP2_SSP3
- IRQ_MMP2_SSP4
- IRQ_MMP2_SSPA1
- IRQ_MMP2_SSPA2
- IRQ_MMP2_TBALL
- IRQ_MMP2_THERMAL
- IRQ_MMP2_TIMER1
- IRQ_MMP2_TIMER2
- IRQ_MMP2_TIMER3
- IRQ_MMP2_TRACKBALL
- IRQ_MMP2_TWSI1
- IRQ_MMP2_TWSI2
- IRQ_MMP2_TWSI3
- IRQ_MMP2_TWSI4
- IRQ_MMP2_TWSI5
- IRQ_MMP2_TWSI6
- IRQ_MMP2_TWSI_BASE
- IRQ_MMP2_TWSI_MUX
- IRQ_MMP2_UART1
- IRQ_MMP2_UART2
- IRQ_MMP2_UART3
- IRQ_MMP2_UART4
- IRQ_MMP2_USB_FS
- IRQ_MMP2_USB_HS1
- IRQ_MMP2_USB_HS2
- IRQ_MMP2_USB_OTG
- IRQ_MMP2_USIM
- IRQ_MMP2_WDT1
- IRQ_MMP2_WDT2
- IRQ_MMP2_WTM
- IRQ_MODE
- IRQ_MODEM
- IRQ_MODERATOR2_EN
- IRQ_MODERATOR2_INIT_BMSK
- IRQ_MODERATOR2_INIT_SHFT
- IRQ_MODERATOR_EN
- IRQ_MODERATOR_INIT_BMSK
- IRQ_MODERATOR_INIT_SHFT
- IRQ_MODE_INTX
- IRQ_MODE_IRL3210
- IRQ_MODE_IRL3210_MASK
- IRQ_MODE_IRL7654
- IRQ_MODE_IRL7654_MASK
- IRQ_MODE_IRQ
- IRQ_MODE_IRQ3210
- IRQ_MODE_IRQ7654
- IRQ_MODE_MASK
- IRQ_MODE_MSIX
- IRQ_MODE_NONE
- IRQ_MODRT_RX_TIMER_SHIFT
- IRQ_MODRT_TIMER_MASK
- IRQ_MODRT_TX_TIMER_SHIFT
- IRQ_MOVE_CLEANUP_VECTOR
- IRQ_MOVE_PCNTXT
- IRQ_MPU401
- IRQ_MSET
- IRQ_MSI
- IRQ_MSINT
- IRQ_MSIX
- IRQ_MSI_ENABLE
- IRQ_MSK
- IRQ_MSL
- IRQ_MSM
- IRQ_MSRXINT
- IRQ_MSSTOPERRINT
- IRQ_MSTXINT
- IRQ_MST_ERR
- IRQ_MV78XX0_CRYPTO
- IRQ_MV78XX0_DB_IN
- IRQ_MV78XX0_DB_OUT
- IRQ_MV78XX0_ERR
- IRQ_MV78XX0_GE00_MISC
- IRQ_MV78XX0_GE00_RX
- IRQ_MV78XX0_GE00_SUM
- IRQ_MV78XX0_GE00_TX
- IRQ_MV78XX0_GE01_MISC
- IRQ_MV78XX0_GE01_RX
- IRQ_MV78XX0_GE01_SUM
- IRQ_MV78XX0_GE01_TX
- IRQ_MV78XX0_GE10_MISC
- IRQ_MV78XX0_GE10_RX
- IRQ_MV78XX0_GE10_SUM
- IRQ_MV78XX0_GE10_TX
- IRQ_MV78XX0_GE11_MISC
- IRQ_MV78XX0_GE11_RX
- IRQ_MV78XX0_GE11_SUM
- IRQ_MV78XX0_GE11_TX
- IRQ_MV78XX0_GE_ERR
- IRQ_MV78XX0_GPIO_0_7
- IRQ_MV78XX0_GPIO_16_23
- IRQ_MV78XX0_GPIO_24_31
- IRQ_MV78XX0_GPIO_8_15
- IRQ_MV78XX0_GPIO_START
- IRQ_MV78XX0_I2C_0
- IRQ_MV78XX0_I2C_1
- IRQ_MV78XX0_I2S_0
- IRQ_MV78XX0_I2S_1
- IRQ_MV78XX0_IDMA_0
- IRQ_MV78XX0_IDMA_1
- IRQ_MV78XX0_IDMA_2
- IRQ_MV78XX0_IDMA_3
- IRQ_MV78XX0_PCIE_00
- IRQ_MV78XX0_PCIE_01
- IRQ_MV78XX0_PCIE_02
- IRQ_MV78XX0_PCIE_03
- IRQ_MV78XX0_PCIE_10
- IRQ_MV78XX0_PCIE_11
- IRQ_MV78XX0_PCIE_12
- IRQ_MV78XX0_PCIE_13
- IRQ_MV78XX0_SATA
- IRQ_MV78XX0_SDIO_0
- IRQ_MV78XX0_SDIO_1
- IRQ_MV78XX0_SPI
- IRQ_MV78XX0_TDMI
- IRQ_MV78XX0_TIMER_0
- IRQ_MV78XX0_TIMER_1
- IRQ_MV78XX0_TIMER_2
- IRQ_MV78XX0_TIMER_3
- IRQ_MV78XX0_UART_0
- IRQ_MV78XX0_UART_1
- IRQ_MV78XX0_UART_2
- IRQ_MV78XX0_UART_3
- IRQ_MV78XX0_USB_0
- IRQ_MV78XX0_USB_1
- IRQ_MV78XX0_USB_2
- IRQ_MV78XX0_XOR_0
- IRQ_MV78XX0_XOR_1
- IRQ_M_EXT
- IRQ_M_SOFT
- IRQ_M_TIMER
- IRQ_NAMESZ
- IRQ_NAME_OFF
- IRQ_NAME_SIZE
- IRQ_NAND
- IRQ_NESTED_THREAD
- IRQ_NETWINDER_BUTTON
- IRQ_NETWINDER_ETHER10
- IRQ_NETWINDER_ETHER100
- IRQ_NETWINDER_IR
- IRQ_NETWINDER_PS2MOUSE
- IRQ_NETWINDER_SOUND
- IRQ_NETWINDER_VGA
- IRQ_NETWINDER_VIDCOMP
- IRQ_NFC
- IRQ_NFCON
- IRQ_NHCIMFCIR
- IRQ_NOAUTOEN
- IRQ_NONE
- IRQ_NOPROBE
- IRQ_NOREQUEST
- IRQ_NORESEND
- IRQ_NOTCONNECTED
- IRQ_NOTHREAD
- IRQ_NOTMINE
- IRQ_NO_BALANCING
- IRQ_NO_BALANCING_MASK
- IRQ_NSSP
- IRQ_NUBUS_9
- IRQ_NUBUS_A
- IRQ_NUBUS_B
- IRQ_NUBUS_C
- IRQ_NUBUS_D
- IRQ_NUBUS_E
- IRQ_NUBUS_F
- IRQ_NUM
- IRQ_NUM_STATS
- IRQ_OFF
- IRQ_OFFSET
- IRQ_OHCI0
- IRQ_ON
- IRQ_ONENAND
- IRQ_ONENAND0
- IRQ_ONENAND1
- IRQ_ON_REQ
- IRQ_ORION5X_BRIDGE
- IRQ_ORION5X_CESA
- IRQ_ORION5X_DEV_BUS_ERR
- IRQ_ORION5X_DOORBELL_C2H
- IRQ_ORION5X_DOORBELL_H2C
- IRQ_ORION5X_ETH_ERR
- IRQ_ORION5X_ETH_MISC
- IRQ_ORION5X_ETH_RX
- IRQ_ORION5X_ETH_SUM
- IRQ_ORION5X_ETH_TX
- IRQ_ORION5X_GPIO_0_7
- IRQ_ORION5X_GPIO_16_23
- IRQ_ORION5X_GPIO_24_31
- IRQ_ORION5X_GPIO_8_15
- IRQ_ORION5X_GPIO_START
- IRQ_ORION5X_I2C
- IRQ_ORION5X_IDMA_0
- IRQ_ORION5X_IDMA_1
- IRQ_ORION5X_IDMA_2
- IRQ_ORION5X_IDMA_3
- IRQ_ORION5X_IDMA_ERR
- IRQ_ORION5X_PCIE0_ERR
- IRQ_ORION5X_PCIE0_INT
- IRQ_ORION5X_PCI_ERR
- IRQ_ORION5X_SATA
- IRQ_ORION5X_UART0
- IRQ_ORION5X_UART1
- IRQ_ORION5X_USB0_CTRL
- IRQ_ORION5X_USB1_CTRL
- IRQ_ORION5X_USB_BR_ERR
- IRQ_ORION5X_XOR0
- IRQ_ORION5X_XOR1
- IRQ_OST0
- IRQ_OST1
- IRQ_OST2
- IRQ_OST3
- IRQ_OST_4_11
- IRQ_OTG
- IRQ_OTHER
- IRQ_OVERFLOW
- IRQ_OVERRUN
- IRQ_P2INTA
- IRQ_P2INTB
- IRQ_P2INTC
- IRQ_P2INTD
- IRQ_PACKET_SIZE
- IRQ_PARITY
- IRQ_PAUSE_START_CONNECT
- IRQ_PCI
- IRQ_PCIINTA
- IRQ_PCIINTB
- IRQ_PCIINTC
- IRQ_PCIINTD
- IRQ_PCI_A
- IRQ_PCI_ABORT
- IRQ_PCI_B
- IRQ_PCI_BRIDGE
- IRQ_PCI_C
- IRQ_PCI_DPERR
- IRQ_PCI_INTA
- IRQ_PCI_INTAD_BASE
- IRQ_PCI_INTB
- IRQ_PCI_INTC
- IRQ_PCI_INTD
- IRQ_PCI_PERR
- IRQ_PCI_SERR
- IRQ_PCM0
- IRQ_PCM1
- IRQ_PCMCIA
- IRQ_PCMOUT
- IRQ_PENDING
- IRQ_PENDN
- IRQ_PEND_COUNT
- IRQ_PEND_EXT_CLOCK_COMP
- IRQ_PEND_EXT_CPU_TIMER
- IRQ_PEND_EXT_EMERGENCY
- IRQ_PEND_EXT_EXTERNAL
- IRQ_PEND_EXT_HOST
- IRQ_PEND_EXT_IRQ_KEY
- IRQ_PEND_EXT_MALFUNC
- IRQ_PEND_EXT_MASK
- IRQ_PEND_EXT_SERVICE
- IRQ_PEND_EXT_TIMING
- IRQ_PEND_IO_ISC_0
- IRQ_PEND_IO_ISC_1
- IRQ_PEND_IO_ISC_2
- IRQ_PEND_IO_ISC_3
- IRQ_PEND_IO_ISC_4
- IRQ_PEND_IO_ISC_5
- IRQ_PEND_IO_ISC_6
- IRQ_PEND_IO_ISC_7
- IRQ_PEND_IO_MASK
- IRQ_PEND_MCHK_EX
- IRQ_PEND_MCHK_MASK
- IRQ_PEND_MCHK_REP
- IRQ_PEND_PFAULT_DONE
- IRQ_PEND_PFAULT_INIT
- IRQ_PEND_PROG
- IRQ_PEND_RESTART
- IRQ_PEND_SET_PREFIX
- IRQ_PEND_SIGP_STOP
- IRQ_PEND_SVC
- IRQ_PEND_VIRTIO
- IRQ_PENRELEASE
- IRQ_PENTOUCH_TOUCHCONVDONE
- IRQ_PER_BANK
- IRQ_PER_CPU
- IRQ_PER_CPU_DEVID
- IRQ_PIN_ASSERTION_REGISTER__Input_IRQ_MASK
- IRQ_PIN_ASSERTION_REGISTER__Input_IRQ__SHIFT
- IRQ_PIPE
- IRQ_PLAYBACK
- IRQ_PLL_LOCK
- IRQ_PLL_UNL
- IRQ_PMU
- IRQ_POL
- IRQ_POLL_F_DISABLE
- IRQ_POLL_F_SCHED
- IRQ_POLL_H
- IRQ_POLL_SOFTIRQ
- IRQ_POL_MSK
- IRQ_POST0
- IRQ_POSTING
- IRQ_POSTING_CAP
- IRQ_POWER
- IRQ_POWERON
- IRQ_PPU_TO_APU
- IRQ_PPU_TO_APU_ACK
- IRQ_PPU_TO_CPU
- IRQ_PPU_TO_CPU_ACK
- IRQ_PPU_TO_EPU
- IRQ_PPU_TO_EPU_ACK
- IRQ_PPU_TO_HPU
- IRQ_PPU_TO_HPU_ACK
- IRQ_PRCMU_ABB
- IRQ_PRCMU_ABB_FIFO
- IRQ_PRCMU_ARM
- IRQ_PRCMU_CA_SLEEP
- IRQ_PRCMU_CA_WAKE
- IRQ_PRCMU_GPIO0
- IRQ_PRCMU_GPIO1
- IRQ_PRCMU_GPIO2
- IRQ_PRCMU_GPIO3
- IRQ_PRCMU_GPIO4
- IRQ_PRCMU_GPIO5
- IRQ_PRCMU_GPIO6
- IRQ_PRCMU_GPIO7
- IRQ_PRCMU_GPIO8
- IRQ_PRCMU_HOTMON_HIGH
- IRQ_PRCMU_HOTMON_LOW
- IRQ_PRCMU_HSI0
- IRQ_PRCMU_HSI1
- IRQ_PRCMU_MODEM_SW_RESET_REQ
- IRQ_PRCMU_RTC
- IRQ_PRCMU_RTT0
- IRQ_PRCMU_RTT1
- IRQ_PRCMU_USB
- IRQ_PRI
- IRQ_PRINTER
- IRQ_PRVUINT
- IRQ_PS2_AUX
- IRQ_PS2_KBD
- IRQ_PSC3_0
- IRQ_PSC3_1
- IRQ_PSC3_2
- IRQ_PSC3_3
- IRQ_PSC4_0
- IRQ_PSC4_1
- IRQ_PSC4_2
- IRQ_PSC4_3
- IRQ_PSC5_0
- IRQ_PSC5_1
- IRQ_PSC5_2
- IRQ_PSC5_3
- IRQ_PSC6_0
- IRQ_PSC6_1
- IRQ_PSC6_2
- IRQ_PSC6_3
- IRQ_PSCIN
- IRQ_PSW
- IRQ_PWMINT0
- IRQ_PWMINT1
- IRQ_PWMINT2
- IRQ_PWR0
- IRQ_PWR1
- IRQ_PWR2
- IRQ_PWR3
- IRQ_PWRI2C
- IRQ_PWRON
- IRQ_PWRON_L
- IRQ_PWRON_S
- IRQ_PXA168_AC97
- IRQ_PXA168_AP_PMU
- IRQ_PXA168_CF
- IRQ_PXA168_CF_WAKEUP
- IRQ_PXA168_CI
- IRQ_PXA168_CMU
- IRQ_PXA168_DDR_INT
- IRQ_PXA168_DMA_INT0
- IRQ_PXA168_DMA_INT1
- IRQ_PXA168_FRQ_CHANGE
- IRQ_PXA168_GPIOX
- IRQ_PXA168_GPU
- IRQ_PXA168_HIFI_DMA
- IRQ_PXA168_KEYPAD
- IRQ_PXA168_LCD
- IRQ_PXA168_MAIN_PMU
- IRQ_PXA168_MFU
- IRQ_PXA168_MSP
- IRQ_PXA168_MSP_WAKEUP
- IRQ_PXA168_NAND
- IRQ_PXA168_NONE
- IRQ_PXA168_ONEWIRE
- IRQ_PXA168_PMIC_INT
- IRQ_PXA168_RTC_ALARM
- IRQ_PXA168_RTC_INT
- IRQ_PXA168_SDH1
- IRQ_PXA168_SDH2
- IRQ_PXA168_SM_INT
- IRQ_PXA168_SSP1
- IRQ_PXA168_SSP2
- IRQ_PXA168_SSP3
- IRQ_PXA168_SSP4
- IRQ_PXA168_SSP5
- IRQ_PXA168_TIMER1
- IRQ_PXA168_TIMER2
- IRQ_PXA168_TIMER3
- IRQ_PXA168_TWSI0
- IRQ_PXA168_TWSI1
- IRQ_PXA168_UART1
- IRQ_PXA168_UART2
- IRQ_PXA168_UART3
- IRQ_PXA168_USB1
- IRQ_PXA168_USB2
- IRQ_PXA168_WDT
- IRQ_PXA168_XD
- IRQ_PXA168_XD_WAKEUP
- IRQ_PXA910_AEU
- IRQ_PXA910_AIRQ
- IRQ_PXA910_AP1_TIMER1
- IRQ_PXA910_AP1_TIMER2
- IRQ_PXA910_AP1_TIMER3
- IRQ_PXA910_AP2_TIMER1
- IRQ_PXA910_AP2_TIMER2
- IRQ_PXA910_AP2_TIMER3
- IRQ_PXA910_AP_FREQ_CHG
- IRQ_PXA910_AP_GPIO
- IRQ_PXA910_AP_PMU
- IRQ_PXA910_CCIC
- IRQ_PXA910_CP2_TIMER1
- IRQ_PXA910_CP2_TIMER2
- IRQ_PXA910_CP2_TIMER3
- IRQ_PXA910_CP2_WDT
- IRQ_PXA910_CP_FREQ_CHG
- IRQ_PXA910_CP_GPIO
- IRQ_PXA910_DMA_INT0
- IRQ_PXA910_DMA_INT1
- IRQ_PXA910_GPU
- IRQ_PXA910_GSSP
- IRQ_PXA910_HIFI_DMA
- IRQ_PXA910_IPC_AP0
- IRQ_PXA910_IPC_AP1
- IRQ_PXA910_IPC_AP2
- IRQ_PXA910_IPC_AP3
- IRQ_PXA910_IPC_AP4
- IRQ_PXA910_IPC_CP0
- IRQ_PXA910_IPC_CP1
- IRQ_PXA910_IPC_CP2
- IRQ_PXA910_IPC_CP3
- IRQ_PXA910_IPC_CP4
- IRQ_PXA910_IRE
- IRQ_PXA910_KEYPAD
- IRQ_PXA910_L2_DDR
- IRQ_PXA910_LCD
- IRQ_PXA910_MAIN_PMU
- IRQ_PXA910_MMC
- IRQ_PXA910_NAND
- IRQ_PXA910_NONE
- IRQ_PXA910_ONEWIRE
- IRQ_PXA910_PMIC_INT
- IRQ_PXA910_ROTARY
- IRQ_PXA910_RTC_ALARM
- IRQ_PXA910_RTC_INT
- IRQ_PXA910_SM_INT
- IRQ_PXA910_SSP1
- IRQ_PXA910_SSP2
- IRQ_PXA910_SSP3
- IRQ_PXA910_TRACKBALL
- IRQ_PXA910_TWSI0
- IRQ_PXA910_TWSI1
- IRQ_PXA910_UART1
- IRQ_PXA910_UART2
- IRQ_PXA910_UART3
- IRQ_PXA910_USB1
- IRQ_PXA910_USB2
- IRQ_PXA935_MMC0
- IRQ_PXA935_MMC1
- IRQ_PXA935_MMC2
- IRQ_R1_B
- IRQ_R1_C
- IRQ_R1_F
- IRQ_R1_P
- IRQ_R2_B
- IRQ_R2_C
- IRQ_R2_F
- IRQ_R2_P
- IRQ_RATE_LIMIT
- IRQ_RAWSTAT
- IRQ_RAW_STATUS
- IRQ_RCVCTXT
- IRQ_READ
- IRQ_RECORDING
- IRQ_REG
- IRQ_REG_ENTRY
- IRQ_REG_MASK
- IRQ_REMAPPING
- IRQ_REMAP_X2APIC_MODE
- IRQ_REMAP_XAPIC_MODE
- IRQ_REQ
- IRQ_REQ_POOL_SIZE
- IRQ_RESEND
- IRQ_RESERVED
- IRQ_RESERVED24
- IRQ_RESERVED6
- IRQ_RESET_CHK
- IRQ_RESOURCE_APIC
- IRQ_RESOURCE_GPIO
- IRQ_RESOURCE_NONE
- IRQ_RESOURCE_TYPE
- IRQ_RESP_ERR
- IRQ_RESP_STATUS
- IRQ_RESP_TIMEOUT
- IRQ_RETRY_MASK
- IRQ_RETVAL
- IRQ_RI
- IRQ_RIO_BELL
- IRQ_RIO_PW
- IRQ_RIO_RX
- IRQ_RIO_TX
- IRQ_RMA
- IRQ_ROTATOR
- IRQ_RST
- IRQ_RSVD
- IRQ_RSZINT
- IRQ_RTA
- IRQ_RTC
- IRQ_RTC1Hz
- IRQ_RTCAlarm
- IRQ_RTCAlrm
- IRQ_RTC_A
- IRQ_RTC_ALARM
- IRQ_RTC_T
- IRQ_RTC_TIC
- IRQ_RTM
- IRQ_RX
- IRQ_RXBREAK
- IRQ_RXDATA
- IRQ_RXD_ERR_MASK
- IRQ_RXEOM
- IRQ_RXFIFO
- IRQ_RXI
- IRQ_RXIDLE
- IRQ_RXMPDI
- IRQ_RXOI
- IRQ_RXOVER
- IRQ_RXPSI
- IRQ_RXTIME
- IRQ_RXWFDI
- IRQ_RX_ERROR
- IRQ_RX_OVERRUN
- IRQ_RX_PKT_RCVD
- IRQ_RX_START
- IRQ_RX_STOPPED
- IRQ_S0_BVD1_STSCHG
- IRQ_S0_CD_VALID
- IRQ_S0_READY_NINT
- IRQ_S1_BVD1_STSCHG
- IRQ_S1_CD_VALID
- IRQ_S1_READY_NINT
- IRQ_S32416_AC97
- IRQ_S32416_WDT
- IRQ_S3C2412_CF
- IRQ_S3C2412_CFSDI
- IRQ_S3C2412_SDI
- IRQ_S3C2416_2D
- IRQ_S3C2416_DMA
- IRQ_S3C2416_DMA0
- IRQ_S3C2416_DMA1
- IRQ_S3C2416_DMA2
- IRQ_S3C2416_DMA3
- IRQ_S3C2416_DMA4
- IRQ_S3C2416_DMA5
- IRQ_S3C2416_EINT8t15
- IRQ_S3C2416_HSMMC0
- IRQ_S3C2416_I2S0
- IRQ_S3C2416_I2S1
- IRQ_S3C2416_IIC1
- IRQ_S3C2416_LCD2
- IRQ_S3C2416_LCD3
- IRQ_S3C2416_LCD4
- IRQ_S3C2416_PCM0
- IRQ_S3C2416_PCM1
- IRQ_S3C2416_RESERVED2
- IRQ_S3C2416_RESERVED3
- IRQ_S3C2416_SDI0
- IRQ_S3C2416_SDI1
- IRQ_S3C2416_UART3
- IRQ_S3C2440_AC97
- IRQ_S3C2440_CAM_C
- IRQ_S3C2440_CAM_P
- IRQ_S3C2440_WDT
- IRQ_S3C2443_AC97
- IRQ_S3C2443_CFCON
- IRQ_S3C2443_DMA
- IRQ_S3C2443_DMA0
- IRQ_S3C2443_DMA1
- IRQ_S3C2443_DMA2
- IRQ_S3C2443_DMA3
- IRQ_S3C2443_DMA4
- IRQ_S3C2443_DMA5
- IRQ_S3C2443_ERR3
- IRQ_S3C2443_HSMMC
- IRQ_S3C2443_LCD1
- IRQ_S3C2443_LCD2
- IRQ_S3C2443_LCD3
- IRQ_S3C2443_LCD4
- IRQ_S3C2443_NAND
- IRQ_S3C2443_RX3
- IRQ_S3C2443_TX3
- IRQ_S3C2443_UART3
- IRQ_S3C2443_WDT
- IRQ_S3C244X_AC97
- IRQ_S3C6400_CAMIF_MP
- IRQ_S3C6400_CAMIF_WE_P
- IRQ_S3C6410_G3D
- IRQ_S3C6410_IIC1
- IRQ_S3C6410_IIS
- IRQ_S3CUART_ERR0
- IRQ_S3CUART_ERR1
- IRQ_S3CUART_ERR2
- IRQ_S3CUART_ERR3
- IRQ_S3CUART_RX0
- IRQ_S3CUART_RX1
- IRQ_S3CUART_RX2
- IRQ_S3CUART_RX3
- IRQ_S3CUART_TX0
- IRQ_S3CUART_TX1
- IRQ_S3CUART_TX2
- IRQ_S3CUART_TX3
- IRQ_SATA
- IRQ_SCALER
- IRQ_SCCA_RX
- IRQ_SCCA_SPCOND
- IRQ_SCCA_STAT
- IRQ_SCCA_TX
- IRQ_SCCB_RX
- IRQ_SCCB_SPCOND
- IRQ_SCCB_STAT
- IRQ_SCCB_TX
- IRQ_SCIF0
- IRQ_SCIF1
- IRQ_SDC
- IRQ_SDCARD
- IRQ_SDI
- IRQ_SDIO
- IRQ_SDIOINT
- IRQ_SDMA
- IRQ_SDMA0
- IRQ_SDMA1
- IRQ_SDRAMPARITY
- IRQ_SD_CD
- IRQ_SEC
- IRQ_SEL
- IRQ_SELECT
- IRQ_SELECT_INDEX
- IRQ_SERIALPORT
- IRQ_SERR
- IRQ_SET_BIT
- IRQ_SET_MASK_OK
- IRQ_SET_MASK_OK_DONE
- IRQ_SET_MASK_OK_NOCOPY
- IRQ_SFD_RX
- IRQ_SFD_TX
- IRQ_SHARE
- IRQ_SIGNAL_HOLD
- IRQ_SIGNAL_THROUGH
- IRQ_SIR_CODE_L2
- IRQ_SIR_FIQ_REG_OFFSET
- IRQ_SIR_IRQ
- IRQ_SIR_IRQ_REG_OFFSET
- IRQ_SIZE
- IRQ_SKIP
- IRQ_SMBUS
- IRQ_SOF0
- IRQ_SOF1
- IRQ_SOF2
- IRQ_SOFT_CLR
- IRQ_SOFT_SET
- IRQ_SOMETHING
- IRQ_SOURCE_TO_VECTOR
- IRQ_SPDUP
- IRQ_SPI
- IRQ_SPI0
- IRQ_SPI1
- IRQ_SPIBEI
- IRQ_SPINT0
- IRQ_SPINT1
- IRQ_SPURIOUS
- IRQ_SRC
- IRQ_SSE
- IRQ_SSP
- IRQ_SSP2
- IRQ_SSP3
- IRQ_SSP4
- IRQ_STA
- IRQ_STACK_ORDER
- IRQ_STACK_SIZE
- IRQ_STACK_START
- IRQ_STARTUP_ABORT
- IRQ_STARTUP_MANAGED
- IRQ_STARTUP_NORMAL
- IRQ_START_COND
- IRQ_START_FORCE
- IRQ_STAT
- IRQ_STATE
- IRQ_STATE_EXT
- IRQ_STATUS
- IRQ_STATUS_BASE
- IRQ_STATUS_IRQ_BITS
- IRQ_STATUS_IRQ_MASK
- IRQ_STATUS_IRQ_PER_REG
- IRQ_STATUS_REG
- IRQ_STAT_4PORTS
- IRQ_STAT_CTRL
- IRQ_STBY_REQ
- IRQ_STNIC
- IRQ_STS
- IRQ_STUART
- IRQ_SUBCLASS_MEASUREMENT_ALERT
- IRQ_SUBCLASS_SERVICE_SIGNAL
- IRQ_SW
- IRQ_SWRST
- IRQ_SYSTEM_RESET
- IRQ_S_EXT
- IRQ_S_SOFT
- IRQ_S_TIMER
- IRQ_Ser0UDC
- IRQ_Ser1SDLC
- IRQ_Ser1UART
- IRQ_Ser2ICP
- IRQ_Ser3UART
- IRQ_Ser4MCP
- IRQ_Ser4SSP
- IRQ_T7L66XB_MMC
- IRQ_T7L66XB_NAND
- IRQ_TABLE
- IRQ_TABLE_ALIGNMENT
- IRQ_TAIL
- IRQ_TC
- IRQ_TC11MP_GIC_START
- IRQ_TC6393_FB
- IRQ_TC6393_MMC
- IRQ_TC6393_NAND
- IRQ_TC6393_OHCI
- IRQ_TCERRINT
- IRQ_TCERRINT0
- IRQ_TEMP1
- IRQ_TEMP2
- IRQ_TEMP3
- IRQ_TEMPD1
- IRQ_TEMPD2
- IRQ_TEMPD3
- IRQ_THRESH
- IRQ_TH_ALERT
- IRQ_TI
- IRQ_TICK
- IRQ_TICPI2
- IRQ_TIMBERDALE_ADV7180
- IRQ_TIMBERDALE_DMA
- IRQ_TIMBERDALE_ETHSW_IF
- IRQ_TIMBERDALE_GPIO
- IRQ_TIMBERDALE_I2C
- IRQ_TIMBERDALE_I2S
- IRQ_TIMBERDALE_INIC
- IRQ_TIMBERDALE_MLB
- IRQ_TIMBERDALE_MLCORE
- IRQ_TIMBERDALE_MLCORE_BUF
- IRQ_TIMBERDALE_RDS
- IRQ_TIMBERDALE_SDHC
- IRQ_TIMBERDALE_SPI
- IRQ_TIMBERDALE_TSC_INT
- IRQ_TIMBERDALE_UART
- IRQ_TIMBERDALE_UARTLITE
- IRQ_TIMEOUT
- IRQ_TIMEOUTS
- IRQ_TIMER
- IRQ_TIMER0
- IRQ_TIMER0_VIC
- IRQ_TIMER1
- IRQ_TIMER1_VIC
- IRQ_TIMER2
- IRQ_TIMER2_VIC
- IRQ_TIMER3
- IRQ_TIMER3_VIC
- IRQ_TIMER4
- IRQ_TIMER4_VIC
- IRQ_TIMINGS_MASK
- IRQ_TIMINGS_SHIFT
- IRQ_TIMINGS_SIZE
- IRQ_TINT0_TINT12
- IRQ_TINT0_TINT34
- IRQ_TINT1_TINT12
- IRQ_TINT1_TINT34
- IRQ_TMIO
- IRQ_TO_ISA
- IRQ_TP
- IRQ_TPM
- IRQ_TPRXINT
- IRQ_TPSTOPERRINT
- IRQ_TPTXINT
- IRQ_TRIGGER_EDGE
- IRQ_TRIGGER_EDGE_FALLING
- IRQ_TRIGGER_EDGE_RISING
- IRQ_TRIGGER_LEVEL
- IRQ_TRKBALL
- IRQ_TRX_END
- IRQ_TRX_UR
- IRQ_TSI
- IRQ_TSI108_DBELL0
- IRQ_TSI108_DBELL1
- IRQ_TSI108_DBELL2
- IRQ_TSI108_DBELL3
- IRQ_TSI108_DMA0
- IRQ_TSI108_DMA1
- IRQ_TSI108_DMA2
- IRQ_TSI108_DMA3
- IRQ_TSI108_EXT_INT0
- IRQ_TSI108_EXT_INT1
- IRQ_TSI108_EXT_INT2
- IRQ_TSI108_EXT_INT3
- IRQ_TSI108_GIGE0
- IRQ_TSI108_GIGE1
- IRQ_TSI108_GPIO
- IRQ_TSI108_HLP
- IRQ_TSI108_I2C
- IRQ_TSI108_MBOX0
- IRQ_TSI108_MBOX1
- IRQ_TSI108_MBOX2
- IRQ_TSI108_MBOX3
- IRQ_TSI108_PCI
- IRQ_TSI108_PROC_IF
- IRQ_TSI108_RESERVED0
- IRQ_TSI108_RESERVED1
- IRQ_TSI108_RESERVED2
- IRQ_TSI108_RESERVED3
- IRQ_TSI108_RESERVED4
- IRQ_TSI108_RESERVED5
- IRQ_TSI108_SDRAM
- IRQ_TSI108_TAB_SIZE
- IRQ_TSI108_TIMER0
- IRQ_TSI108_TIMER1
- IRQ_TSI108_TIMER2
- IRQ_TSI108_TIMER3
- IRQ_TSI108_UART0
- IRQ_TSI108_UART1
- IRQ_TT_MFP_DRVRDY
- IRQ_TT_MFP_IO0
- IRQ_TT_MFP_IO1
- IRQ_TT_MFP_RECERR
- IRQ_TT_MFP_RECFULL
- IRQ_TT_MFP_RI
- IRQ_TT_MFP_RTC
- IRQ_TT_MFP_SCC
- IRQ_TT_MFP_SCSI
- IRQ_TT_MFP_SCSIDMA
- IRQ_TT_MFP_SEREMPT
- IRQ_TT_MFP_SERERR
- IRQ_TT_MFP_TIMA
- IRQ_TT_MFP_TIMB
- IRQ_TT_MFP_TIMC
- IRQ_TT_MFP_TIMD
- IRQ_TUNI0
- IRQ_TUNI1
- IRQ_TUNI2
- IRQ_TVENC
- IRQ_TWSIE
- IRQ_TWSIR
- IRQ_TWSIW
- IRQ_TX
- IRQ_TXDATA
- IRQ_TXD_ERR
- IRQ_TXFIFO
- IRQ_TXI
- IRQ_TXIDLE
- IRQ_TXPSI
- IRQ_TXREPEAT
- IRQ_TXSAI
- IRQ_TXUNDER
- IRQ_TX_PKT_SENT
- IRQ_TX_STOPPED
- IRQ_TYPE_ADDR
- IRQ_TYPE_DEFAULT
- IRQ_TYPE_EDGE_BOTH
- IRQ_TYPE_EDGE_FALLING
- IRQ_TYPE_EDGE_RISING
- IRQ_TYPE_FSLINT
- IRQ_TYPE_FSLSPECIAL
- IRQ_TYPE_LEGACY
- IRQ_TYPE_LEVEL_HIGH
- IRQ_TYPE_LEVEL_LOW
- IRQ_TYPE_LEVEL_MASK
- IRQ_TYPE_LINE
- IRQ_TYPE_MPIC_DIRECT
- IRQ_TYPE_MSI
- IRQ_TYPE_MSIX
- IRQ_TYPE_NONE
- IRQ_TYPE_NORMAL
- IRQ_TYPE_PFLIP
- IRQ_TYPE_PROBE
- IRQ_TYPE_SENSE_MASK
- IRQ_TYPE_UNDEFINED
- IRQ_TYPE_VBLANK
- IRQ_TYPE_VUPDATE
- IRQ_U2H
- IRQ_U2O
- IRQ_U2P
- IRQ_UART0
- IRQ_UART1
- IRQ_UART1_CTS
- IRQ_UART1_DCD
- IRQ_UART1_DSR
- IRQ_UART2
- IRQ_UART3
- IRQ_UART3_CTS
- IRQ_UART3_DCD
- IRQ_UART3_DSR
- IRQ_UARTINT0
- IRQ_UARTINT1
- IRQ_UARTINT2
- IRQ_UMAL
- IRQ_UNDERRUN
- IRQ_UNIGFX
- IRQ_UNKNOWN2
- IRQ_UNKNOWN3
- IRQ_UNMAPPED
- IRQ_UNUSED
- IRQ_USB
- IRQ_USB2
- IRQ_USBD
- IRQ_USBD_RXDMA0
- IRQ_USBD_RXDMA1
- IRQ_USBD_RXDMA2
- IRQ_USBD_TXDMA0
- IRQ_USBD_TXDMA1
- IRQ_USBD_TXDMA2
- IRQ_USBH
- IRQ_USBH1
- IRQ_USBH2
- IRQ_USBINT
- IRQ_USBPWR
- IRQ_USB_ATX
- IRQ_USB_DEVDMA
- IRQ_USB_HP
- IRQ_USB_LP
- IRQ_USB_PORT_RESUME
- IRQ_USED
- IRQ_USER
- IRQ_USIM
- IRQ_USIM2
- IRQ_U_EXT
- IRQ_U_SOFT
- IRQ_U_TIMER
- IRQ_VDINT0
- IRQ_VDINT1
- IRQ_VDINT2
- IRQ_VECTOR_TO_SOURCE
- IRQ_VECTOR_UNASSIGNED
- IRQ_VENCINT
- IRQ_VFOCINT
- IRQ_VIA1_0
- IRQ_VIA1_1
- IRQ_VIA1_2
- IRQ_VIA1_3
- IRQ_VIA1_4
- IRQ_VIA1_5
- IRQ_VIA1_6
- IRQ_VIA1_7
- IRQ_VIA2_0
- IRQ_VIA2_1
- IRQ_VIA2_2
- IRQ_VIA2_3
- IRQ_VIA2_4
- IRQ_VIA2_5
- IRQ_VIA2_6
- IRQ_VIA2_7
- IRQ_VIC0_BASE
- IRQ_VIC0_RESUME
- IRQ_VIC1_BASE
- IRQ_VIC1_RESUME
- IRQ_VIC_END
- IRQ_VIRT_BASE
- IRQ_VLCDINT
- IRQ_VLQINT
- IRQ_VOYAGER
- IRQ_VSYNCPULSE
- IRQ_WAKEUP0
- IRQ_WAKEUP1
- IRQ_WAKE_THREAD
- IRQ_WDOG
- IRQ_WDT
- IRQ_WKUP
- IRQ_WORK_BUSY
- IRQ_WORK_CLAIMED
- IRQ_WORK_LAZY
- IRQ_WORK_PENDING
- IRQ_WORK_VECTOR
- IRQ_WRITE
- IRQ_WUI
- IRQ_XA_B
- IRQ_XA_C
- IRQ_XA_F
- IRQ_XS_B
- IRQ_XS_C
- IRQ_XS_F
- IRQ_XTM
- IRQ_XTM_DMA0
- IRQ_check
- IRQ_get_next
- IRQ_i_CFG
- IRQ_local_pipe
- IRQ_resetbit
- IRQ_setbit
- IRQindex
- IRQpending
- IRQtable
- IRR
- IRRELEVANT
- IRRQ_SLOTS_TO_IRD_LIMIT
- IRR_ETHERNET
- IRR_SA1111
- IRR_USAR
- IRSELECT
- IRSHIFT
- IRSR
- IRST
- IRTE_ALLOCATED
- IRTE_DEST
- IRT_ACTIVE_HI
- IRT_ACTIVE_LO
- IRT_DEV_MASK
- IRT_DEV_SHIFT
- IRT_EDGE_TRIG
- IRT_EL_MASK
- IRT_EL_SHIFT
- IRT_IOSAPIC_LENGTH
- IRT_IOSAPIC_TYPE
- IRT_IRQ_DEVNO_MASK
- IRT_IRQ_MASK
- IRT_LEVEL_TRIG
- IRT_MASK
- IRT_PO_MASK
- IRT_SHIFT
- IRT_VECTORED_INTR
- IRUPDATE
- IRUSESEL
- IR_ACKE
- IR_ALL
- IR_ALL_INT
- IR_ANIMAX
- IR_ARA
- IR_BE
- IR_BEC
- IR_BEU
- IR_BO
- IR_BUSY
- IR_CDUTY_REG
- IR_CFG_FORMAT_MASK
- IR_CFG_FORMAT_SHIFT
- IR_CFG_FREQ_MASK
- IR_CFG_FREQ_SHIFT
- IR_CFG_INT_LEVEL_MASK
- IR_CFG_INT_LEVEL_SHIFT
- IR_CFG_INT_THRESHOLD
- IR_CFG_MODE_RAW
- IR_CFG_SYMBOL_FMT
- IR_CFG_SYMBOL_MAXWIDTH
- IR_CFG_WIDTH_MASK
- IR_CFG_WIDTH_SHIFT
- IR_CLK
- IR_CLK_ENABLE
- IR_CLK_RESET
- IR_CNTRL_REG
- IR_CONFIG
- IR_CONTEXT_BUFFER_FILL
- IR_CONTEXT_CYCLE_MATCH_ENABLE
- IR_CONTEXT_DUAL_BUFFER_MODE
- IR_CONTEXT_ISOCH_HEADER
- IR_CONTEXT_MULTI_CHANNEL_MODE
- IR_CONTROL_REG_BASE
- IR_CRCE
- IR_CTRL
- IR_CTX_HEADER_SIZE_CIP
- IR_CTX_HEADER_SIZE_NO_CIP
- IR_DATAH
- IR_DATAL
- IR_DATA_BUFFER_BASE
- IR_DEC_BIT_0
- IR_DEC_FRAME
- IR_DEC_LDR_ACTIVE
- IR_DEC_LDR_IDLE
- IR_DEC_LDR_REPEAT
- IR_DEC_REG0
- IR_DEC_REG1
- IR_DEC_REG2
- IR_DEC_STATUS
- IR_DEFAULT_TIMEOUT
- IR_DEVICE_ANY
- IR_DISABLE
- IR_DRX
- IR_Data_Cnt
- IR_ELO
- IR_ENABLE
- IR_EP
- IR_ERR_ALL_30X
- IR_ERR_ALL_31X
- IR_ERR_BUS_30X
- IR_ERR_BUS_31X
- IR_ERR_LEC_30X
- IR_ERR_LEC_31X
- IR_ERR_STATE
- IR_ERR_TOL_CTRL
- IR_ERR_TOL_LEN
- IR_EW
- IR_EXTRA
- IR_FIFO_REG
- IR_FILTR_REG
- IR_FIRMODE
- IR_FOE
- IR_GLITCH_LEN
- IR_GPIO
- IR_HIX5HD2_NAME
- IR_HOMEBREW
- IR_HPM
- IR_IDLE_LEN0
- IR_IDLE_LEN1
- IR_IGOR
- IR_IN
- IR_INT
- IR_INTC
- IR_INTM
- IR_INTS
- IR_IO_APIC_route_entry
- IR_IRDEO
- IR_IRDEO_REMOTE
- IR_IRQEN_REG
- IR_Idle_Cnt_High
- IR_Idle_Cnt_Low
- IR_Init_Reg
- IR_KBD_GET_KEY_AVERMEDIA_CARDBUS
- IR_KBD_GET_KEY_CUSTOM
- IR_KBD_GET_KEY_FUSIONHDTV
- IR_KBD_GET_KEY_HAUP
- IR_KBD_GET_KEY_HAUP_XVR
- IR_KBD_GET_KEY_KNC1
- IR_KBD_GET_KEY_PIXELVIEW
- IR_LNKCHG0
- IR_LNKCHG0_ofst
- IR_LNKCHG1
- IR_LOGINFO_CODE_UNUSED2
- IR_LOGINFO_COMPAT_ERROR_DEVICE_NOT_512_BYTE_BLOCK
- IR_LOGINFO_COMPAT_ERROR_DISK_TOO_SMALL
- IR_LOGINFO_COMPAT_ERROR_IME_VOL_NOT_CURRENTLY_SUPPORTED
- IR_LOGINFO_COMPAT_ERROR_INQUIRY_FAILED
- IR_LOGINFO_COMPAT_ERROR_MEMBERSHIP_COUNT
- IR_LOGINFO_COMPAT_ERROR_NEED_SCSI_2_OR_HIGHER
- IR_LOGINFO_COMPAT_ERROR_NON_64K_STRIPE_SIZE
- IR_LOGINFO_COMPAT_ERROR_NOT_DIRECT_ACCESS
- IR_LOGINFO_COMPAT_ERROR_PHYS_DISK_NOT_FOUND
- IR_LOGINFO_COMPAT_ERROR_RAID_DISABLED
- IR_LOGINFO_COMPAT_ERROR_REMOVABLE_FOUND
- IR_LOGINFO_COMPAT_ERROR_SATA_48BIT_LBA_NOT_SUPPORTED
- IR_LOGINFO_COMPAT_ERROR_UNSUPPORTED_VOLUME_TYPE
- IR_LOGINFO_COMPAT_ERROR_VOLUME_TYPE_CHECK_FAILED
- IR_LOGINFO_DEV_FW_UPDATE_ERR_ALLOC_CFG_PAGE
- IR_LOGINFO_DEV_FW_UPDATE_ERR_DEVICE_IN_INVALID_STATE
- IR_LOGINFO_DEV_FW_UPDATE_ERR_DFU_IN_PROGRESS
- IR_LOGINFO_DEV_FW_UPDATE_ERR_INVALID_TIMEOUT
- IR_LOGINFO_DEV_FW_UPDATE_ERR_NO_TIMERS
- IR_LOGINFO_DEV_FW_UPDATE_ERR_PORT_IO_TIMEOUTS_REQUIRED
- IR_LOGINFO_DEV_FW_UPDATE_ERR_READING_CFG_PAGE
- IR_LOGINFO_PHYSDISK_CREATE_BUS_TID_INVALID
- IR_LOGINFO_PHYSDISK_CREATE_CONFIG_PAGE_ERROR
- IR_LOGINFO_PHYSDISK_CREATE_DMA_ERROR
- IR_LOGINFO_PHYSDISK_CREATE_INVALID_LENGTH
- IR_LOGINFO_PHYSDISK_CREATE_TOO_MANY_DISKS
- IR_LOGINFO_RAID_ACTION_ERROR
- IR_LOGINFO_VOLUME_ACTIVATE_VOLUME_FAILED
- IR_LOGINFO_VOLUME_ACTIVATING_AN_ACTIVE_VOLUME
- IR_LOGINFO_VOLUME_ACTIVATING_IMPORT_VOLUME_FAILED
- IR_LOGINFO_VOLUME_ACTIVATING_INVALID_VOLUME_TYPE
- IR_LOGINFO_VOLUME_ACTIVATING_TOO_MANY_PHYS_DISKS
- IR_LOGINFO_VOLUME_ACTIVATING_TOO_MANY_VOLUMES
- IR_LOGINFO_VOLUME_ACTIVATING_VOLUME_ID_IN_USE
- IR_LOGINFO_VOLUME_CREATE_DMA_ERROR
- IR_LOGINFO_VOLUME_CREATE_DUPLICATE
- IR_LOGINFO_VOLUME_CREATE_INVALID_LENGTH
- IR_LOGINFO_VOLUME_CREATE_INVALID_VOLUME_TYPE
- IR_LOGINFO_VOLUME_CREATE_NO_SLOTS
- IR_LOGINFO_VOLUME_INTERNAL_CONFIG_STRUCTURE_ERROR
- IR_LOGINFO_VOLUME_MFG_PAGE4_ERROR
- IR_MASK_CTRL
- IR_MASK_DATA
- IR_MAX_DURATION
- IR_MAX_DURATION0
- IR_MAX_DURATION1
- IR_MAX_H_TOL_LEN
- IR_MAX_L_TOL_LEN
- IR_MEASURE
- IR_MRAF
- IR_NEC_CTRL
- IR_NEC_DATA
- IR_OFF
- IR_PCIE_LINK
- IR_PCIE_TOUT
- IR_PEA
- IR_PED
- IR_PERCENT_TOLERANCE
- IR_PROTOCOL_NEC
- IR_PROTOCOL_RC5
- IR_PROTOCOL_RC6
- IR_PSE
- IR_RC5
- IR_RC5_CLK_DIV
- IR_RC5_DATA
- IR_RC5_EXT
- IR_RCMM
- IR_RES_MASK_ADDR
- IR_RES_MASK_T_LEN
- IR_RF0F
- IR_RF0L
- IR_RF0N
- IR_RF0W
- IR_RF1F
- IR_RF1L
- IR_RF1N
- IR_RF1W
- IR_RFRSH
- IR_RSVD
- IR_RUN
- IR_RXCLK_REG
- IR_RXINTR
- IR_RX_BC
- IR_RX_BUF
- IR_RX_BUF_CTRL
- IR_RX_BUF_DATA
- IR_RX_CFG
- IR_RX_CLK
- IR_RX_CTRL
- IR_RX_C_COUNT_H
- IR_RX_C_COUNT_L
- IR_RX_DESC_0
- IR_RX_DESC_1
- IR_RX_DESC_2
- IR_RX_DESC_3
- IR_RX_FREE_0
- IR_RX_FREE_1
- IR_RX_FREE_2
- IR_RX_FREE_3
- IR_RX_IE
- IR_RX_IF
- IR_RxFL
- IR_S0
- IR_SDPERR
- IR_SIRMODE
- IR_SPI_DEFAULT_FREQUENCY
- IR_SPI_DRIVER_NAME
- IR_SPI_MAX_BUFSIZE
- IR_START
- IR_STAT_REG
- IR_STE
- IR_ST_NAME
- IR_SUSPEND_CTRL
- IR_SWI
- IR_TAB_MAX_SIZE
- IR_TAB_MIN_SIZE
- IR_TC
- IR_TCF
- IR_TEFF
- IR_TEFL
- IR_TEFN
- IR_TEFW
- IR_TFE
- IR_TMR0
- IR_TMR1
- IR_TMR2
- IR_TMR3
- IR_TOO
- IR_TR
- IR_TSW
- IR_TXCLK_REG
- IR_TXINTR
- IR_TX_FREE_0
- IR_TX_FREE_1
- IR_TX_FREE_2
- IR_TX_FREE_3
- IR_UNIT_LEN
- IR_Unit_Cnt_High
- IR_Unit_Cnt_Low
- IR_VNT
- IR_WDI
- IR_X2APIC_MODE
- IR_X_INT
- IR_i2c
- IR_i2c_init_data
- IS1_R
- IS2_ACTION_TYPE_NORMAL
- IS2_ACTION_TYPE_SMAC_SIP
- IS2_ACT_MASK_MODE_FILTER
- IS2_ACT_MASK_MODE_NONE
- IS2_ACT_MASK_MODE_POLICY
- IS2_ACT_MASK_MODE_REDIR
- IS2_ACT_REW_OP_NONE
- IS2_ACT_REW_OP_PTP_ONE
- IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY
- IS2_ACT_REW_OP_PTP_ONE_ADD_SUB
- IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1
- IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2
- IS2_ACT_REW_OP_PTP_ORG
- IS2_ACT_REW_OP_PTP_TWO
- IS2_ACT_REW_OP_SPECIAL
- IS2_AL_ACL_ID
- IS2_AL_CPU_COPY_ENA
- IS2_AL_CPU_QU_NUM
- IS2_AL_HIT_ME_ONCE
- IS2_AL_ISDX_ENA
- IS2_AL_LM_CNT_DIS
- IS2_AL_LRN_DIS
- IS2_AL_MASK_MODE
- IS2_AL_MIRROR_ENA
- IS2_AL_POLICE_ENA
- IS2_AL_POLICE_IDX
- IS2_AL_POLICE_VCAP_ONLY
- IS2_AL_PORT_MASK
- IS2_AL_REW_OP
- IS2_AL_SMAC_SIP_CPU_COPY_ENA
- IS2_AL_SMAC_SIP_CPU_QU_NUM
- IS2_AL_SMAC_SIP_FWD_KILL_ENA
- IS2_AL_SMAC_SIP_HOST_MATCH
- IS2_AO_ACL_ID
- IS2_AO_CPU_COPY_ENA
- IS2_AO_CPU_QU_NUM
- IS2_AO_HIT_ME_ONCE
- IS2_AO_ISDX_ENA
- IS2_AO_LM_CNT_DIS
- IS2_AO_LRN_DIS
- IS2_AO_MASK_MODE
- IS2_AO_MIRROR_ENA
- IS2_AO_POLICE_ENA
- IS2_AO_POLICE_IDX
- IS2_AO_POLICE_VCAP_ONLY
- IS2_AO_PORT_MASK
- IS2_AO_REW_OP
- IS2_AO_SMAC_SIP_CPU_COPY_ENA
- IS2_AO_SMAC_SIP_CPU_QU_NUM
- IS2_AO_SMAC_SIP_FWD_KILL_ENA
- IS2_AO_SMAC_SIP_HOST_MATCH
- IS2_FKL_CUSTOM_CUSTOM
- IS2_FKL_CUSTOM_CUSTOM_TYPE
- IS2_FKL_DEI
- IS2_FKL_DIP_EQ_SIP
- IS2_FKL_FIRST
- IS2_FKL_HOST_MATCH
- IS2_FKL_IGR_PORT_MASK
- IS2_FKL_IP6_OTHER_L3_PAYLOAD
- IS2_FKL_IP6_OTHER_L3_PROTO
- IS2_FKL_IP6_TCP_UDP_L4_1588_DOM
- IS2_FKL_IP6_TCP_UDP_L4_1588_VER
- IS2_FKL_IP6_TCP_UDP_L4_ACK
- IS2_FKL_IP6_TCP_UDP_L4_DPORT
- IS2_FKL_IP6_TCP_UDP_L4_FIN
- IS2_FKL_IP6_TCP_UDP_L4_PSH
- IS2_FKL_IP6_TCP_UDP_L4_RNG
- IS2_FKL_IP6_TCP_UDP_L4_RST
- IS2_FKL_IP6_TCP_UDP_L4_SPORT
- IS2_FKL_IP6_TCP_UDP_L4_SYN
- IS2_FKL_IP6_TCP_UDP_L4_URG
- IS2_FKL_IP6_TCP_UDP_SEQUENCE_EQ0
- IS2_FKL_IP6_TCP_UDP_SPORT_EQ_DPORT
- IS2_FKL_IP6_TCP_UDP_TCP
- IS2_FKL_L2_BC
- IS2_FKL_L2_MC
- IS2_FKL_L3_IP6_DIP
- IS2_FKL_L3_IP6_SIP
- IS2_FKL_L3_TOS
- IS2_FKL_L3_TTL_GT0
- IS2_FKL_PAG
- IS2_FKL_PCP
- IS2_FKL_SERVICE_FRM
- IS2_FKL_TYPE
- IS2_FKL_VID
- IS2_FKL_VLAN_TAGGED
- IS2_FKO_CUSTOM_CUSTOM
- IS2_FKO_CUSTOM_CUSTOM_TYPE
- IS2_FKO_DEI
- IS2_FKO_DIP_EQ_SIP
- IS2_FKO_FIRST
- IS2_FKO_HOST_MATCH
- IS2_FKO_IGR_PORT_MASK
- IS2_FKO_IP6_OTHER_L3_PAYLOAD
- IS2_FKO_IP6_OTHER_L3_PROTO
- IS2_FKO_IP6_TCP_UDP_L4_1588_DOM
- IS2_FKO_IP6_TCP_UDP_L4_1588_VER
- IS2_FKO_IP6_TCP_UDP_L4_ACK
- IS2_FKO_IP6_TCP_UDP_L4_DPORT
- IS2_FKO_IP6_TCP_UDP_L4_FIN
- IS2_FKO_IP6_TCP_UDP_L4_PSH
- IS2_FKO_IP6_TCP_UDP_L4_RNG
- IS2_FKO_IP6_TCP_UDP_L4_RST
- IS2_FKO_IP6_TCP_UDP_L4_SPORT
- IS2_FKO_IP6_TCP_UDP_L4_SYN
- IS2_FKO_IP6_TCP_UDP_L4_URG
- IS2_FKO_IP6_TCP_UDP_SEQUENCE_EQ0
- IS2_FKO_IP6_TCP_UDP_SPORT_EQ_DPORT
- IS2_FKO_IP6_TCP_UDP_TCP
- IS2_FKO_L2_BC
- IS2_FKO_L2_MC
- IS2_FKO_L3_IP6_DIP
- IS2_FKO_L3_IP6_SIP
- IS2_FKO_L3_TOS
- IS2_FKO_L3_TTL_GT0
- IS2_FKO_PAG
- IS2_FKO_PCP
- IS2_FKO_SERVICE_FRM
- IS2_FKO_TYPE
- IS2_FKO_VID
- IS2_FKO_VLAN_TAGGED
- IS2_HKL_DEI
- IS2_HKL_DIP_EQ_SIP
- IS2_HKL_FIRST
- IS2_HKL_HOST_MATCH
- IS2_HKL_IGR_PORT_MASK
- IS2_HKL_IP4
- IS2_HKL_IP4_OTHER_L3_PAYLOAD
- IS2_HKL_IP4_OTHER_L3_PROTO
- IS2_HKL_IP4_TCP_UDP_L4_1588_DOM
- IS2_HKL_IP4_TCP_UDP_L4_1588_VER
- IS2_HKL_IP4_TCP_UDP_L4_ACK
- IS2_HKL_IP4_TCP_UDP_L4_DPORT
- IS2_HKL_IP4_TCP_UDP_L4_FIN
- IS2_HKL_IP4_TCP_UDP_L4_PSH
- IS2_HKL_IP4_TCP_UDP_L4_RNG
- IS2_HKL_IP4_TCP_UDP_L4_RST
- IS2_HKL_IP4_TCP_UDP_L4_SPORT
- IS2_HKL_IP4_TCP_UDP_L4_SYN
- IS2_HKL_IP4_TCP_UDP_L4_URG
- IS2_HKL_IP4_TCP_UDP_SEQUENCE_EQ0
- IS2_HKL_IP4_TCP_UDP_SPORT_EQ_DPORT
- IS2_HKL_IP4_TCP_UDP_TCP
- IS2_HKL_IP6_STD_L3_IP6_SIP
- IS2_HKL_IP6_STD_L3_PROTO
- IS2_HKL_IP6_STD_L3_TTL_GT0
- IS2_HKL_L2_BC
- IS2_HKL_L2_DMAC
- IS2_HKL_L2_MC
- IS2_HKL_L2_SMAC
- IS2_HKL_L3_FRAGMENT
- IS2_HKL_L3_FRAG_OFS_GT0
- IS2_HKL_L3_IP4_DIP
- IS2_HKL_L3_IP4_SIP
- IS2_HKL_L3_OPTIONS
- IS2_HKL_L3_TOS
- IS2_HKL_L3_TTL_GT0
- IS2_HKL_MAC_ARP_ARP_ADDR_SPACE_OK
- IS2_HKL_MAC_ARP_ARP_LEN_OK
- IS2_HKL_MAC_ARP_ARP_OPCODE
- IS2_HKL_MAC_ARP_ARP_OPCODE_UNKNOWN
- IS2_HKL_MAC_ARP_ARP_PROTO_SPACE_OK
- IS2_HKL_MAC_ARP_ARP_SENDER_MATCH
- IS2_HKL_MAC_ARP_ARP_TGT_MATCH
- IS2_HKL_MAC_ARP_DIP_EQ_SIP
- IS2_HKL_MAC_ARP_L2_SMAC
- IS2_HKL_MAC_ARP_L3_IP4_DIP
- IS2_HKL_MAC_ARP_L3_IP4_SIP
- IS2_HKL_MAC_ETYPE_ETYPE
- IS2_HKL_MAC_ETYPE_L2_PAYLOAD
- IS2_HKL_MAC_LLC_L2_LLC
- IS2_HKL_MAC_SNAP_L2_SNAP
- IS2_HKL_OAM_OAM_CCM_CNTS_EQ0
- IS2_HKL_OAM_OAM_FLAGS
- IS2_HKL_OAM_OAM_MEL_FLAGS
- IS2_HKL_OAM_OAM_MEPID
- IS2_HKL_OAM_OAM_OPCODE
- IS2_HKL_OAM_OAM_VER
- IS2_HKL_PAG
- IS2_HKL_PCP
- IS2_HKL_SERVICE_FRM
- IS2_HKL_SMAC_SIP6_IGR_PORT
- IS2_HKL_SMAC_SIP6_L2_SMAC
- IS2_HKL_SMAC_SIP6_L3_IP6_SIP
- IS2_HKL_TYPE
- IS2_HKL_VID
- IS2_HKL_VLAN_TAGGED
- IS2_HKO_DEI
- IS2_HKO_DIP_EQ_SIP
- IS2_HKO_FIRST
- IS2_HKO_HOST_MATCH
- IS2_HKO_IGR_PORT_MASK
- IS2_HKO_IP4
- IS2_HKO_IP4_OTHER_L3_PAYLOAD
- IS2_HKO_IP4_OTHER_L3_PROTO
- IS2_HKO_IP4_TCP_UDP_L4_1588_DOM
- IS2_HKO_IP4_TCP_UDP_L4_1588_VER
- IS2_HKO_IP4_TCP_UDP_L4_ACK
- IS2_HKO_IP4_TCP_UDP_L4_DPORT
- IS2_HKO_IP4_TCP_UDP_L4_FIN
- IS2_HKO_IP4_TCP_UDP_L4_PSH
- IS2_HKO_IP4_TCP_UDP_L4_RNG
- IS2_HKO_IP4_TCP_UDP_L4_RST
- IS2_HKO_IP4_TCP_UDP_L4_SPORT
- IS2_HKO_IP4_TCP_UDP_L4_SYN
- IS2_HKO_IP4_TCP_UDP_L4_URG
- IS2_HKO_IP4_TCP_UDP_SEQUENCE_EQ0
- IS2_HKO_IP4_TCP_UDP_SPORT_EQ_DPORT
- IS2_HKO_IP4_TCP_UDP_TCP
- IS2_HKO_IP6_STD_L3_IP6_SIP
- IS2_HKO_IP6_STD_L3_PROTO
- IS2_HKO_IP6_STD_L3_TTL_GT0
- IS2_HKO_L2_BC
- IS2_HKO_L2_DMAC
- IS2_HKO_L2_MC
- IS2_HKO_L2_SMAC
- IS2_HKO_L3_FRAGMENT
- IS2_HKO_L3_FRAG_OFS_GT0
- IS2_HKO_L3_IP4_DIP
- IS2_HKO_L3_IP4_SIP
- IS2_HKO_L3_OPTIONS
- IS2_HKO_L3_TOS
- IS2_HKO_L3_TTL_GT0
- IS2_HKO_MAC_ARP_ARP_ADDR_SPACE_OK
- IS2_HKO_MAC_ARP_ARP_LEN_OK
- IS2_HKO_MAC_ARP_ARP_OPCODE
- IS2_HKO_MAC_ARP_ARP_OPCODE_UNKNOWN
- IS2_HKO_MAC_ARP_ARP_PROTO_SPACE_OK
- IS2_HKO_MAC_ARP_ARP_SENDER_MATCH
- IS2_HKO_MAC_ARP_ARP_TGT_MATCH
- IS2_HKO_MAC_ARP_DIP_EQ_SIP
- IS2_HKO_MAC_ARP_L2_SMAC
- IS2_HKO_MAC_ARP_L3_IP4_DIP
- IS2_HKO_MAC_ARP_L3_IP4_SIP
- IS2_HKO_MAC_ETYPE_ETYPE
- IS2_HKO_MAC_ETYPE_L2_PAYLOAD
- IS2_HKO_MAC_LLC_L2_LLC
- IS2_HKO_MAC_SNAP_L2_SNAP
- IS2_HKO_OAM_OAM_CCM_CNTS_EQ0
- IS2_HKO_OAM_OAM_FLAGS
- IS2_HKO_OAM_OAM_MEL_FLAGS
- IS2_HKO_OAM_OAM_MEPID
- IS2_HKO_OAM_OAM_OPCODE
- IS2_HKO_OAM_OAM_VER
- IS2_HKO_PAG
- IS2_HKO_PCP
- IS2_HKO_SERVICE_FRM
- IS2_HKO_SMAC_SIP6_IGR_PORT
- IS2_HKO_SMAC_SIP6_L2_SMAC
- IS2_HKO_SMAC_SIP6_L3_IP6_SIP
- IS2_HKO_TYPE
- IS2_HKO_VID
- IS2_HKO_VLAN_TAGGED
- IS2_QKL_IGR_PORT
- IS2_QKL_L2_SMAC
- IS2_QKL_L3_IP4_SIP
- IS2_QKO_IGR_PORT
- IS2_QKO_L2_SMAC
- IS2_QKO_L3_IP4_SIP
- IS2_TYPE_ANY
- IS2_TYPE_ARP
- IS2_TYPE_ETYPE
- IS2_TYPE_IPV6
- IS2_TYPE_IP_OTHER
- IS2_TYPE_IP_UDP_TCP
- IS2_TYPE_LLC
- IS2_TYPE_MASK_IP_ANY
- IS2_TYPE_OAM
- IS2_TYPE_SMAC_SIP6
- IS2_TYPE_SNAP
- IS31FL319X_AUDIO_GAIN_DB_MAX
- IS31FL319X_AUDIO_GAIN_DB_STEP
- IS31FL319X_BREATH_MASK
- IS31FL319X_CONFIG1
- IS31FL319X_CONFIG2
- IS31FL319X_CONFIG2_CS_MASK
- IS31FL319X_CONFIG2_CS_SHIFT
- IS31FL319X_CONFIG2_CS_STEP_REF
- IS31FL319X_CTRL1
- IS31FL319X_CTRL2
- IS31FL319X_CURRENT_DEFAULT
- IS31FL319X_CURRENT_MAX
- IS31FL319X_CURRENT_MIN
- IS31FL319X_CURRENT_STEP
- IS31FL319X_DATA_UPDATE
- IS31FL319X_MAX_LEDS
- IS31FL319X_PWM
- IS31FL319X_RAMP_MODE
- IS31FL319X_REG_CNT
- IS31FL319X_RESET
- IS31FL319X_SHUTDOWN
- IS31FL319X_T0
- IS31FL319X_T123_1
- IS31FL319X_T123_2
- IS31FL319X_T123_3
- IS31FL319X_T4
- IS31FL319X_TIME_UPDATE
- IS31FL3216_CHANNEL_CONFIG_REG
- IS31FL3216_CONFIG_REG
- IS31FL3216_CONFIG_SSD_DISABLE
- IS31FL3216_CONFIG_SSD_ENABLE
- IS31FL3216_LIGHTING_EFFECT_REG
- IS31FL32XX_REG_NONE
- IS31FL32XX_SHUTDOWN_SSD_DISABLE
- IS31FL32XX_SHUTDOWN_SSD_ENABLE
- ISA
- ISA16
- ISA207_ADD_FIELDS
- ISA207_SIER_DATA_SRC_MASK
- ISA207_SIER_DATA_SRC_SHIFT
- ISA207_SIER_LDST_MASK
- ISA207_SIER_LDST_SHIFT
- ISA207_SIER_TYPE_MASK
- ISA207_SIER_TYPE_SHIFT
- ISA207_TEST_ADDER
- ISABELLE_ABIAS_CFG_REG
- ISABELLE_ACCDET_STATUS_REG
- ISABELLE_AIF_FMT_MASK
- ISABELLE_AIF_LENGTH_20
- ISABELLE_AIF_LENGTH_32
- ISABELLE_AIF_LENGTH_MASK
- ISABELLE_AIF_MS
- ISABELLE_ALU_RX_EN_REG
- ISABELLE_ALU_TX_EN_REG
- ISABELLE_AMIC_CFG_REG
- ISABELLE_APGA_CFG_REG
- ISABELLE_APGA_GAIN_REG
- ISABELLE_ATX1_DPGA_REG
- ISABELLE_ATX2_DPGA_REG
- ISABELLE_ATX_STPGA1_CFG_REG
- ISABELLE_ATX_STPGA2_CFG_REG
- ISABELLE_AUDIO_HPF_CFG_REG
- ISABELLE_BUTTON_ID_REG
- ISABELLE_CHIP_EN
- ISABELLE_DAC1_SOFTRAMP_REG
- ISABELLE_DAC2_SOFTRAMP_REG
- ISABELLE_DAC3_SOFTRAMP_REG
- ISABELLE_DAC_CFG_REG
- ISABELLE_DBIAS_CFG_REG
- ISABELLE_DL12_INTF_CFG_REG
- ISABELLE_DL34_INTF_CFG_REG
- ISABELLE_DL56_INTF_CFG_REG
- ISABELLE_DMIC_CFG_REG
- ISABELLE_DPGA1LR_IN_SEL_REG
- ISABELLE_DPGA1L_GAIN_REG
- ISABELLE_DPGA1R_GAIN_REG
- ISABELLE_DPGA2L_GAIN_REG
- ISABELLE_DPGA2L_IN_SEL_REG
- ISABELLE_DPGA2R_GAIN_REG
- ISABELLE_DPGA2R_IN_SEL_REG
- ISABELLE_DPGA3LR_IN_SEL_REG
- ISABELLE_DPGA3L_GAIN_REG
- ISABELLE_DPGA3R_GAIN_REG
- ISABELLE_EARDRV_CFG1_REG
- ISABELLE_EARDRV_CFG2_REG
- ISABELLE_FORMATS
- ISABELLE_FS_RATE_11
- ISABELLE_FS_RATE_12
- ISABELLE_FS_RATE_16
- ISABELLE_FS_RATE_22
- ISABELLE_FS_RATE_24
- ISABELLE_FS_RATE_32
- ISABELLE_FS_RATE_44
- ISABELLE_FS_RATE_48
- ISABELLE_FS_RATE_8
- ISABELLE_FS_RATE_CFG_REG
- ISABELLE_FS_RATE_MASK
- ISABELLE_HFDRV_CFG_REG
- ISABELLE_HFLPGA_CFG_REG
- ISABELLE_HFL_LIM_CTRL_1_REG
- ISABELLE_HFL_LIM_CTRL_2_REG
- ISABELLE_HFL_SFTVOL_CTRL_REG
- ISABELLE_HFL_VOL_CTRL_REG
- ISABELLE_HFRPGA_CFG_REG
- ISABELLE_HFR_LIM_CTRL_1_REG
- ISABELLE_HFR_LIM_CTRL_2_REG
- ISABELLE_HFR_SFTVOL_CTRL_REG
- ISABELLE_HFR_VOL_CTRL_REG
- ISABELLE_HF_MODE_REG
- ISABELLE_HF_NG_CFG1_REG
- ISABELLE_HF_NG_CFG2_REG
- ISABELLE_HKCTL1_REG
- ISABELLE_HKCTL2_REG
- ISABELLE_HKCTL3_REG
- ISABELLE_HSDRV_CFG1_REG
- ISABELLE_HSDRV_CFG2_REG
- ISABELLE_HSDRV_GAIN_REG
- ISABELLE_HS_NG_CFG1_REG
- ISABELLE_HS_NG_CFG2_REG
- ISABELLE_I2S_MODE
- ISABELLE_IIR_RESYNC_REG
- ISABELLE_INT1_MASK_REG
- ISABELLE_INT1_STATUS_REG
- ISABELLE_INT2_MASK_REG
- ISABELLE_INT2_STATUS_REG
- ISABELLE_INTF_CFG_REG
- ISABELLE_INTF_EN_REG
- ISABELLE_LEFT_J_MODE
- ISABELLE_LINEAMP_CFG_REG
- ISABELLE_LINEAMP_GAIN_REG
- ISABELLE_MAX_REGISTER
- ISABELLE_MIC1_GAIN_REG
- ISABELLE_MIC2_GAIN_REG
- ISABELLE_PDMOUT_CFG1_REG
- ISABELLE_PDMOUT_CFG2_REG
- ISABELLE_PDMOUT_L_WM_REG
- ISABELLE_PDMOUT_R_WM_REG
- ISABELLE_PDM_MODE
- ISABELLE_PLL_CFG_REG
- ISABELLE_PLL_EN_REG
- ISABELLE_PS_EN1_REG
- ISABELLE_PWR_CFG_REG
- ISABELLE_PWR_EN_REG
- ISABELLE_RATES
- ISABELLE_RX1_DPGA_REG
- ISABELLE_RX2_DPGA_REG
- ISABELLE_RX3_DPGA_REG
- ISABELLE_RX4_DPGA_REG
- ISABELLE_RX5_DPGA_REG
- ISABELLE_RX6_DPGA_REG
- ISABELLE_RX_GAIN_DLY_REG
- ISABELLE_RX_INPUT_CFG2_REG
- ISABELLE_RX_INPUT_CFG_REG
- ISABELLE_RX_PWR_CTRL_REG
- ISABELLE_TX_GAIN_DLY_REG
- ISABELLE_TX_INPUT_CFG_REG
- ISABELLE_ULATX12_INTF_CFG_REG
- ISABELLE_VOICE_HPF_CFG_REG
- ISABELLE_VTX1_DPGA_REG
- ISABELLE_VTX2_DPGA_REG
- ISABELLE_VTX2_STPGA2_CFG_REG
- ISABELLE_VTX_STPGA1_CFG_REG
- ISACSR0
- ISACSR1
- ISACSR2
- ISACSR4
- ISACSR5
- ISACSR6
- ISACSR7
- ISACX_ACFG1
- ISACX_ACFG2
- ISACX_AOE
- ISACX_ARX
- ISACX_ASTI
- ISACX_ATX
- ISACX_AUXI
- ISACX_AUXM
- ISACX_BCHA_CR
- ISACX_BCHA_TSDP_BC1
- ISACX_BCHA_TSDP_BC2
- ISACX_BCHB_CR
- ISACX_BCHB_TSDP_BC1
- ISACX_BCHB_TSDP_BC2
- ISACX_CDA10
- ISACX_CDA11
- ISACX_CDA1_CR
- ISACX_CDA20
- ISACX_CDA21
- ISACX_CDA2_CR
- ISACX_CDA_TSDP10
- ISACX_CDA_TSDP11
- ISACX_CDA_TSDP20
- ISACX_CDA_TSDP21
- ISACX_CIR0
- ISACX_CIR0_BAS
- ISACX_CIR0_CIC0
- ISACX_CIR0_CIC1
- ISACX_CIR0_SG
- ISACX_CIR1
- ISACX_CIX0
- ISACX_CIX1
- ISACX_CMDRD
- ISACX_CMDRD_RMC
- ISACX_CMDRD_RRES
- ISACX_CMDRD_STI
- ISACX_CMDRD_XME
- ISACX_CMDRD_XRES
- ISACX_CMDRD_XTF
- ISACX_DCIC_CR
- ISACX_DCI_CR
- ISACX_D_RFO
- ISACX_D_RME
- ISACX_D_RPF
- ISACX_D_XDU
- ISACX_D_XMR
- ISACX_D_XPR
- ISACX_EXMD1
- ISACX_ID
- ISACX_IOM_CR
- ISACX_ISTA
- ISACX_ISTAD
- ISACX_ISTATR
- ISACX_MASK
- ISACX_MASKD
- ISACX_MASKTR
- ISACX_MCDA
- ISACX_MCONF
- ISACX_MOCR
- ISACX_MODE1
- ISACX_MODE2
- ISACX_MODED
- ISACX_MON_CR
- ISACX_MOR
- ISACX_MOSR
- ISACX_MOX
- ISACX_MSTA
- ISACX_MSTI
- ISACX_RBCHD
- ISACX_RBCLD
- ISACX_RFIFOD
- ISACX_RSTAD
- ISACX_RSTAD_CR
- ISACX_RSTAD_CRC
- ISACX_RSTAD_RAB
- ISACX_RSTAD_RDO
- ISACX_RSTAD_SA0
- ISACX_RSTAD_SA1
- ISACX_RSTAD_TA
- ISACX_RSTAD_VFR
- ISACX_SAP1
- ISACX_SAP2
- ISACX_SDS1_CR
- ISACX_SDS2_CR
- ISACX_SDS_CONF
- ISACX_SQRR1
- ISACX_SQRR2
- ISACX_SQRR3
- ISACX_SQXR1
- ISACX_SQXR2
- ISACX_SQXR3
- ISACX_SRES
- ISACX_STARD
- ISACX_STI
- ISACX_TEI1
- ISACX_TEI2
- ISACX_TIMR1
- ISACX_TIMR2
- ISACX_TMD
- ISACX_TRC_CR
- ISACX_TR_CMD
- ISACX_TR_CONF0
- ISACX_TR_CONF1
- ISACX_TR_CONF2
- ISACX_TR_CR
- ISACX_TR_MODE
- ISACX_TR_STA
- ISACX_TR_TSDP_BC1
- ISACX_TR_TSDP_BC2
- ISACX_XFIFOD
- ISACX__AUX
- ISACX__CIC
- ISACX__ICD
- ISACX__MOS
- ISACX__ST
- ISACX__TRAN
- ISAC_ADF1
- ISAC_ADF2
- ISAC_CIR0
- ISAC_CIR1
- ISAC_CIX0
- ISAC_CIX1
- ISAC_CMDR
- ISAC_CMD_AR10
- ISAC_CMD_AR8
- ISAC_CMD_ARL
- ISAC_CMD_DUI
- ISAC_CMD_RS
- ISAC_CMD_SCZ
- ISAC_CMD_SSZ
- ISAC_CMD_TIM
- ISAC_EXIR
- ISAC_IND_AI10
- ISAC_IND_AI8
- ISAC_IND_ARD
- ISAC_IND_ATI
- ISAC_IND_DID
- ISAC_IND_DIS
- ISAC_IND_DR
- ISAC_IND_DR6
- ISAC_IND_EI
- ISAC_IND_PU
- ISAC_IND_RS
- ISAC_IND_RSY
- ISAC_IND_SD
- ISAC_IND_TI
- ISAC_ISTA
- ISAC_MASK
- ISAC_MOCR
- ISAC_MODE
- ISAC_MOR0
- ISAC_MOR1
- ISAC_MOSR
- ISAC_MOX0
- ISAC_MOX1
- ISAC_RBCH
- ISAC_RBCH_XAC
- ISAC_RBCL
- ISAC_REV
- ISAC_RSTA
- ISAC_SPCR
- ISAC_SQRR
- ISAC_SQXR
- ISAC_STAR
- ISAC_STCR
- ISAC_TIMR
- ISAC_USE_ARCOFI
- ISAIO_BASE
- ISAIO_PHYS
- ISAIO_SIZE
- ISALED0
- ISALED0_LNKST
- ISALIGNED
- ISALLOWED_CHANWIDTH40
- ISALPHA
- ISAMEM_BASE
- ISAMEM_PHYS
- ISAMEM_SIZE
- ISAPNP_ANY_ID
- ISAPNP_CARD_DEVS
- ISAPNP_CARD_END
- ISAPNP_CARD_ID
- ISAPNP_CFG_ACTIVATE
- ISAPNP_CFG_DMA
- ISAPNP_CFG_IRQ
- ISAPNP_CFG_MEM
- ISAPNP_CFG_PORT
- ISAPNP_DEVICE
- ISAPNP_DEVICE_ID
- ISAPNP_DEVICE_SINGLE
- ISAPNP_DEVICE_SINGLE_END
- ISAPNP_FUNCTION
- ISAPNP_MAX_DMA
- ISAPNP_MAX_IRQ
- ISAPNP_MAX_MEM
- ISAPNP_MAX_PORT
- ISAPNP_REGION_OK
- ISAPNP_VENDOR
- ISARVersion
- ISAR_CTRL_H
- ISAR_CTRL_L
- ISAR_CTRL_STST
- ISAR_CTRL_SWVER
- ISAR_DP1_USE
- ISAR_DP2_USE
- ISAR_HIA
- ISAR_HIS
- ISAR_HIS_BSTREQ
- ISAR_HIS_DIAG
- ISAR_HIS_DKEY
- ISAR_HIS_DPS1
- ISAR_HIS_DPS2
- ISAR_HIS_FIRM
- ISAR_HIS_IOM2CFG
- ISAR_HIS_IOM2CTRL
- ISAR_HIS_IOM2REQ
- ISAR_HIS_P0CFG
- ISAR_HIS_P12CFG
- ISAR_HIS_PSTREQ
- ISAR_HIS_PUMPCFG
- ISAR_HIS_PUMPCTRL
- ISAR_HIS_SARTCFG
- ISAR_HIS_SDATA
- ISAR_HIS_STDSP
- ISAR_HIS_VNR
- ISAR_IIA
- ISAR_IIS
- ISAR_IIS_BSTEV
- ISAR_IIS_BSTRSP
- ISAR_IIS_DIAG
- ISAR_IIS_DKEY
- ISAR_IIS_FIRM
- ISAR_IIS_GSTEV
- ISAR_IIS_INVMSG
- ISAR_IIS_IOM2RSP
- ISAR_IIS_MSCMSD
- ISAR_IIS_PSTEV
- ISAR_IIS_PSTRSP
- ISAR_IIS_RDATA
- ISAR_IIS_STDSP
- ISAR_IIS_VNR
- ISAR_IRQBIT
- ISAR_IRQMSK
- ISAR_IRQSTA
- ISAR_MBOX
- ISAR_MSG_HWVER
- ISAR_RADR
- ISAR_RATE_REQ
- ISAR_REV
- ISAR_WADR
- ISA_AUTO_RxDMA
- ISA_CNF_OFFSET
- ISA_COMMAND_TIMEOUT
- ISA_DMA_ADDR
- ISA_DMA_CLRFF
- ISA_DMA_COUNT
- ISA_DMA_MASK
- ISA_DMA_MODE
- ISA_DMA_PGHI
- ISA_DMA_PGLO
- ISA_DMA_SIZE
- ISA_EN
- ISA_END_ADDRESS
- ISA_INIT_STATUS_BITS
- ISA_IO_BASE
- ISA_IO_END
- ISA_IRQ_VECTOR
- ISA_LOCK
- ISA_MODE
- ISA_POOL_SIZE
- ISA_RXDATA_16BIT_1_DATA_MASK
- ISA_RXDATA_16BIT_2_DATA_MASK
- ISA_RXDATA_16BIT_3_DATA_MASK
- ISA_RXDATA_16BIT_4_DATA_MASK
- ISA_RXDATA_32BIT_1_DATA_MASK
- ISA_RxDMA
- ISA_SEX
- ISA_SPACE_IO
- ISA_SPACE_MASK
- ISA_START_ADDRESS
- ISA_TYPE
- ISA_TYPE_AG
- ISA_TYPE_ENEC
- ISA_TYPE_Q40
- ISA_UNLOCK
- ISA_V2
- ISA_V2_07B
- ISA_V3_0B
- ISCI_ABORT_TASK_TIMEOUT_MS
- ISCI_CAN_QUEUE_VAL
- ISCI_COALESCE_BASE
- ISCI_EFI_VAR_NAME
- ISCI_EFI_VENDOR_GUID
- ISCI_FW_NAME
- ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_FRAGMENT
- ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_IP_OPTIONS
- ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_MAX_RTRANS
- ISCI_KCQE_COMPLETION_STATUS_TCP_ERROR_URGENT_FLAG
- ISCI_LU_RESET_TIMEOUT_MS
- ISCI_OEM_SIG
- ISCI_OEM_SIG_SIZE
- ISCI_PEG
- ISCI_PORT_RESET_TIMEOUT
- ISCI_REMOTE_DEVICE_START_TIMEOUT
- ISCI_ROM_SIG
- ISCI_ROM_SIG_SIZE
- ISCI_ROM_VER_1_0
- ISCI_ROM_VER_1_1
- ISCI_ROM_VER_1_3
- ISCI_ROM_VER_LATEST
- ISCI_TAG
- ISCI_TAG_SEQ
- ISCI_TAG_TCI
- ISCI_TERMINATION_TIMEOUT_MSEC
- ISCON
- ISCP_ADDR
- ISCP_BUSY
- ISCP_SIZE
- ISCR_DPDM_PULLUP_EN
- ISCR_FORCE_ID_HIGH
- ISCR_FORCE_ID_LOW
- ISCR_FORCE_ID_MASK
- ISCR_FORCE_VBUS_HIGH
- ISCR_FORCE_VBUS_LOW
- ISCR_FORCE_VBUS_MASK
- ISCR_ID_PULLUP_EN
- ISCSIOPTS_BIDI_CHAP_EN
- ISCSIOPTS_CHAP_AUTH_EN
- ISCSIOPTS_DATA_DIGEST_EN
- ISCSIOPTS_DATA_PDU_INORDER_EN
- ISCSIOPTS_DATA_SEQ_INORDER_EN
- ISCSIOPTS_DISCOVERY_AUTH_EN
- ISCSIOPTS_DISCOVERY_LOGOUT_EN
- ISCSIOPTS_ERL
- ISCSIOPTS_HEADER_DIGEST_EN
- ISCSIOPTS_IMMEDIATE_DATA_EN
- ISCSIOPTS_INITIAL_R2T_EN
- ISCSIOPTS_SNACK_EN
- ISCSIOPTS_STRICT_LOGIN_COMP_EN
- ISCSIOPT_BIDI_CHAP_EN
- ISCSIOPT_CHAP_AUTH_EN
- ISCSIOPT_DATA_DIGEST_EN
- ISCSIOPT_DATA_PDU_IN_ORDER
- ISCSIOPT_DATA_SEQ_IN_ORDER
- ISCSIOPT_DISCOVERY_AUTH_OPTIONAL
- ISCSIOPT_DISCOVERY_LOGOUT_EN
- ISCSIOPT_ERL0
- ISCSIOPT_ERL1
- ISCSIOPT_HEADER_DIGEST_EN
- ISCSIOPT_IMMEDIATE_DATA_EN
- ISCSIOPT_INITIAL_R2T_EN
- ISCSIOPT_SNACK_REQ_EN
- ISCSIT_BITMAP_BITS
- ISCSIT_EXTRA_TAGS
- ISCSIT_MIN_TAGS
- ISCSIT_TCP_BACKLOG
- ISCSIT_TRANSPORT_NAME
- ISCSIT_VERSION
- ISCSI_ADDRESS_BUF_LEN
- ISCSI_AGE_MASK
- ISCSI_AGE_SHIFT
- ISCSI_AHSTYPE_CDB
- ISCSI_AHSTYPE_RLENGTH
- ISCSI_AHS_CNTL_SIZE
- ISCSI_ALIAS_SIZE
- ISCSI_APP_IDX
- ISCSI_ASYNC_MSG_DROPPING_ALL_CONNECTIONS
- ISCSI_ASYNC_MSG_DROPPING_CONNECTION
- ISCSI_ASYNC_MSG_HDR_CONST1_MASK
- ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT
- ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK
- ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_ASYNC_MSG_HDR_RSRV_MASK
- ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT
- ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_ASYNC_MSG_PARAM_NEGOTIATION
- ISCSI_ASYNC_MSG_REQUEST_LOGOUT
- ISCSI_ASYNC_MSG_SCSI_EVENT
- ISCSI_ASYNC_MSG_VENDOR_SPECIFIC
- ISCSI_ATTR
- ISCSI_ATTR_ACA
- ISCSI_ATTR_HEAD_OF_QUEUE
- ISCSI_ATTR_ORDERED
- ISCSI_ATTR_SIMPLE
- ISCSI_ATTR_UNTAGGED
- ISCSI_BD_FIRST_IN_BD_CHAIN
- ISCSI_BD_FIRST_IN_BD_CHAIN_SHIFT
- ISCSI_BD_LAST_IN_BD_CHAIN
- ISCSI_BD_LAST_IN_BD_CHAIN_SHIFT
- ISCSI_BD_RESERVED1
- ISCSI_BD_RESERVED1_SHIFT
- ISCSI_BD_RESERVED2
- ISCSI_BD_RESERVED2_SHIFT
- ISCSI_BOOTPROTO_DHCP
- ISCSI_BOOTPROTO_STATIC
- ISCSI_BOOT_ACPITBL_OEM_ID
- ISCSI_BOOT_ACPITBL_OEM_TABLE_ID
- ISCSI_BOOT_ACPITBL_SIGNATURE
- ISCSI_BOOT_ETH_DHCP
- ISCSI_BOOT_ETH_END_MARKER
- ISCSI_BOOT_ETH_FLAGS
- ISCSI_BOOT_ETH_GATEWAY
- ISCSI_BOOT_ETH_HOSTNAME
- ISCSI_BOOT_ETH_INDEX
- ISCSI_BOOT_ETH_IP_ADDR
- ISCSI_BOOT_ETH_MAC
- ISCSI_BOOT_ETH_ORIGIN
- ISCSI_BOOT_ETH_PREFIX_LEN
- ISCSI_BOOT_ETH_PRIMARY_DNS
- ISCSI_BOOT_ETH_SECONDARY_DNS
- ISCSI_BOOT_ETH_SUBNET_MASK
- ISCSI_BOOT_ETH_VLAN
- ISCSI_BOOT_INI_END_MARKER
- ISCSI_BOOT_INI_FLAGS
- ISCSI_BOOT_INI_INDEX
- ISCSI_BOOT_INI_INITIATOR_NAME
- ISCSI_BOOT_INI_ISNS_SERVER
- ISCSI_BOOT_INI_PRI_RADIUS_SERVER
- ISCSI_BOOT_INI_SEC_RADIUS_SERVER
- ISCSI_BOOT_INI_SLP_SERVER
- ISCSI_BOOT_TGT_CHAP_NAME
- ISCSI_BOOT_TGT_CHAP_SECRET
- ISCSI_BOOT_TGT_CHAP_TYPE
- ISCSI_BOOT_TGT_END_MARKER
- ISCSI_BOOT_TGT_FLAGS
- ISCSI_BOOT_TGT_INDEX
- ISCSI_BOOT_TGT_IP_ADDR
- ISCSI_BOOT_TGT_LUN
- ISCSI_BOOT_TGT_NAME
- ISCSI_BOOT_TGT_NIC_ASSOC
- ISCSI_BOOT_TGT_PORT
- ISCSI_BOOT_TGT_REV_CHAP_NAME
- ISCSI_BOOT_TGT_REV_CHAP_SECRET
- ISCSI_BSG_CLS_MASK
- ISCSI_BSG_HST_MASK
- ISCSI_BSG_HST_VENDOR
- ISCSI_CDB_SIZE
- ISCSI_CDU_TASK_SEG_TYPE
- ISCSI_CHAP_AUTH_NAME_MAX_LEN
- ISCSI_CHAP_AUTH_SECRET_MAX_LEN
- ISCSI_CHAP_PARAM
- ISCSI_CHAP_PARAM_CHAP_TYPE
- ISCSI_CHAP_PARAM_INDEX
- ISCSI_CHAP_PARAM_PASSWORD
- ISCSI_CHAP_PARAM_PASSWORD_LEN
- ISCSI_CHAP_PARAM_USERNAME
- ISCSI_CLASS
- ISCSI_CLASS_ATTR
- ISCSI_CLEANUP_REQUEST_INDEX
- ISCSI_CLEANUP_REQUEST_INDEX_SHIFT
- ISCSI_CLEANUP_REQUEST_TYPE
- ISCSI_CLEANUP_REQUEST_TYPE_SHIFT
- ISCSI_CLEANUP_RESPONSE_INDEX
- ISCSI_CLEANUP_RESPONSE_INDEX_SHIFT
- ISCSI_CLEANUP_RESPONSE_TYPE
- ISCSI_CLEANUP_RESPONSE_TYPE_SHIFT
- ISCSI_CMD_CLEANUP_TIMEOUT
- ISCSI_CMD_HDR_ATTR_MASK
- ISCSI_CMD_HDR_ATTR_SHIFT
- ISCSI_CMD_HDR_DATA_SEG_LEN_MASK
- ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_CMD_HDR_FINAL_MASK
- ISCSI_CMD_HDR_FINAL_SHIFT
- ISCSI_CMD_HDR_IMM_MASK
- ISCSI_CMD_HDR_IMM_SHIFT
- ISCSI_CMD_HDR_OPCODE_MASK
- ISCSI_CMD_HDR_OPCODE_SHIFT
- ISCSI_CMD_HDR_READ_MASK
- ISCSI_CMD_HDR_READ_SHIFT
- ISCSI_CMD_HDR_RSRV1_MASK
- ISCSI_CMD_HDR_RSRV1_SHIFT
- ISCSI_CMD_HDR_RSRV_MASK
- ISCSI_CMD_HDR_RSRV_SHIFT
- ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_CMD_HDR_TYPE_AHS
- ISCSI_CMD_HDR_TYPE_BHS_ONLY
- ISCSI_CMD_HDR_TYPE_BHS_W_AHS
- ISCSI_CMD_HDR_WRITE_MASK
- ISCSI_CMD_HDR_WRITE_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG
- ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT
- ISCSI_CMD_REQUEST_FINAL
- ISCSI_CMD_REQUEST_FINAL_SHIFT
- ISCSI_CMD_REQUEST_INDEX
- ISCSI_CMD_REQUEST_INDEX_SHIFT
- ISCSI_CMD_REQUEST_READ
- ISCSI_CMD_REQUEST_READ_SHIFT
- ISCSI_CMD_REQUEST_RESERVED1
- ISCSI_CMD_REQUEST_RESERVED1_SHIFT
- ISCSI_CMD_REQUEST_TASK_ATTR
- ISCSI_CMD_REQUEST_TASK_ATTR_SHIFT
- ISCSI_CMD_REQUEST_TYPE
- ISCSI_CMD_REQUEST_TYPE_SHIFT
- ISCSI_CMD_REQUEST_WRITE
- ISCSI_CMD_REQUEST_WRITE_SHIFT
- ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW
- ISCSI_CMD_RESPONSE_BR_RESIDUAL_OVERFLOW_SHIFT
- ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW
- ISCSI_CMD_RESPONSE_BR_RESIDUAL_UNDERFLOW_SHIFT
- ISCSI_CMD_RESPONSE_INDEX
- ISCSI_CMD_RESPONSE_INDEX_SHIFT
- ISCSI_CMD_RESPONSE_RESERVED0
- ISCSI_CMD_RESPONSE_RESERVED0_SHIFT
- ISCSI_CMD_RESPONSE_RESERVED1
- ISCSI_CMD_RESPONSE_RESERVED1_SHIFT
- ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW
- ISCSI_CMD_RESPONSE_RESIDUAL_OVERFLOW_SHIFT
- ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW
- ISCSI_CMD_RESPONSE_RESIDUAL_UNDERFLOW_SHIFT
- ISCSI_CMD_RESPONSE_TYPE
- ISCSI_CMD_RESPONSE_TYPE_SHIFT
- ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK
- ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_COMMON_HDR_IMM_MASK
- ISCSI_COMMON_HDR_IMM_SHIFT
- ISCSI_COMMON_HDR_OPCODE_MASK
- ISCSI_COMMON_HDR_OPCODE_SHIFT
- ISCSI_COMMON_HDR_RSRV_MASK
- ISCSI_COMMON_HDR_RSRV_SHIFT
- ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_CONNECTION_TYPE
- ISCSI_CONN_CLEANUP_WAIT
- ISCSI_CONN_ERROR_CMDQ_RING_IS_FULL
- ISCSI_CONN_ERROR_CONNECT_INVALID_TCP_OPTION
- ISCSI_CONN_ERROR_DATA_OVERRUN
- ISCSI_CONN_ERROR_DATA_PLACEMENT_ERROR
- ISCSI_CONN_ERROR_HEADER_DIGEST_ERROR
- ISCSI_CONN_ERROR_HQE_CACHING_FAILED
- ISCSI_CONN_ERROR_INVALID_ITT
- ISCSI_CONN_ERROR_IP_OPTIONS_ERROR
- ISCSI_CONN_ERROR_LOCAL_COMPLETION_ERROR
- ISCSI_CONN_ERROR_OUT_OF_SGES_ERROR
- ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_LEN
- ISCSI_CONN_ERROR_PROTOCOL_ERR_AHS_TYPE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_BUFFER_OFFSET_OOO
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_IN_TTT
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_OUT_ITT
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SEG_LEN_EXCEEDS_PDU_SIZE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SEG_LEN_TOO_BIG
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DATA_SN
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_2
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DIF_TX
- ISCSI_CONN_ERROR_PROTOCOL_ERR_DSL_NOT_ZERO
- ISCSI_CONN_ERROR_PROTOCOL_ERR_EXP_STAT_SN
- ISCSI_CONN_ERROR_PROTOCOL_ERR_F_BIT_ZERO
- ISCSI_CONN_ERROR_PROTOCOL_ERR_F_BIT_ZERO_S_BIT_ONE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_DSL
- ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_OPCODE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_INVALID_OPCODE_BEFORE_UPDATE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_ITT_OUT_OF_RANGE
- ISCSI_CONN_ERROR_PROTOCOL_ERR_LUN
- ISCSI_CONN_ERROR_PROTOCOL_ERR_OUTSTANDING_R2T_COUNT
- ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_BUFFER_OFFSET
- ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_CARRIES_NO_DATA
- ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_SN
- ISCSI_CONN_ERROR_PROTOCOL_ERR_R2T_TTT
- ISCSI_CONN_ERROR_PROTOCOL_ERR_TTT_OUT_OF_RANGE
- ISCSI_CONN_ERROR_PRS_ERRORS
- ISCSI_CONN_ERROR_RQ_RING_IS_FULL
- ISCSI_CONN_ERROR_SENSE_DATA_LENGTH
- ISCSI_CONN_ERROR_TASK_CID_MISMATCH
- ISCSI_CONN_ERROR_TASK_NOT_VALID
- ISCSI_CONN_ERROR_TCP_IP_FRAGMENT_ERROR
- ISCSI_CONN_ERROR_UNVALID_NOPIN_DSL
- ISCSI_CONN_INITIAL_STAGE
- ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK
- ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT
- ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK
- ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT
- ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK
- ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT
- ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK
- ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT
- ISCSI_CONN_STARTED
- ISCSI_CONN_STATE_CLEANUP_WAIT
- ISCSI_CONN_STATE_FREE
- ISCSI_CONN_STATE_IN_LOGIN
- ISCSI_CONN_STATE_IN_LOGOUT
- ISCSI_CONN_STATE_LOGGED_IN
- ISCSI_CONN_STATE_LOGOUT_REQUESTED
- ISCSI_CONN_STATE_XPT_WAIT
- ISCSI_CONN_STOPPED
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_IMM_EN_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_IMM_EN_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_LUN_MAPPER_EN_MASK
- ISCSI_CONN_UPDATE_RAMROD_PARAMS_LUN_MAPPER_EN_SHIFT
- ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN
- ISCSI_CQE_TYPE_DUMMY
- ISCSI_CQE_TYPE_SOLICITED
- ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE
- ISCSI_CQE_TYPE_TASK_CLEANUP
- ISCSI_CQE_TYPE_UNSOLICITED
- ISCSI_CQE_UNSOLICITED_FIRST
- ISCSI_CQE_UNSOLICITED_LAST
- ISCSI_CQE_UNSOLICITED_MIDDLE
- ISCSI_CQE_UNSOLICITED_NONE
- ISCSI_CQE_UNSOLICITED_SINGLE
- ISCSI_CQ_DB_SIZE
- ISCSI_CRC_LEN
- ISCSI_CTRL
- ISCSI_CXGBIT
- ISCSI_DATA_IN_HDR_ACK_MASK
- ISCSI_DATA_IN_HDR_ACK_SHIFT
- ISCSI_DATA_IN_HDR_FINAL_MASK
- ISCSI_DATA_IN_HDR_FINAL_SHIFT
- ISCSI_DATA_IN_HDR_OVERFLOW_MASK
- ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT
- ISCSI_DATA_IN_HDR_RSRV_MASK
- ISCSI_DATA_IN_HDR_RSRV_SHIFT
- ISCSI_DATA_IN_HDR_STATUS_MASK
- ISCSI_DATA_IN_HDR_STATUS_SHIFT
- ISCSI_DATA_IN_HDR_UNDERFLOW_MASK
- ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT
- ISCSI_DATA_OUT_HDR_FINAL_MASK
- ISCSI_DATA_OUT_HDR_FINAL_SHIFT
- ISCSI_DATA_OUT_HDR_RSRV_MASK
- ISCSI_DATA_OUT_HDR_RSRV_SHIFT
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_DBG_CONN
- ISCSI_DBG_EH
- ISCSI_DBG_SESSION
- ISCSI_DBG_TCP
- ISCSI_DBG_TRANS_CONN
- ISCSI_DBG_TRANS_SESSION
- ISCSI_DB_DATA_AGG_CMD_MASK
- ISCSI_DB_DATA_AGG_CMD_SHIFT
- ISCSI_DB_DATA_AGG_VAL_SEL_MASK
- ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT
- ISCSI_DB_DATA_BYPASS_EN_MASK
- ISCSI_DB_DATA_BYPASS_EN_SHIFT
- ISCSI_DB_DATA_DEST_MASK
- ISCSI_DB_DATA_DEST_SHIFT
- ISCSI_DB_DATA_RESERVED_MASK
- ISCSI_DB_DATA_RESERVED_SHIFT
- ISCSI_DDP_F
- ISCSI_DDP_S
- ISCSI_DDP_V
- ISCSI_DEBUG_MODES_ASSERT_IF_DIF_OR_DATA_DIGEST_ERROR_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_DIF_OR_DATA_DIGEST_ERROR_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_HQ_CORRUPT_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_HQ_CORRUPT_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT
- ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK
- ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT
- ISCSI_DEFAULT_BSG_TIMEOUT
- ISCSI_DEFAULT_DATA_DIGEST
- ISCSI_DEFAULT_FIRST_BURST_LENGTH
- ISCSI_DEFAULT_HEADER_DIGEST
- ISCSI_DEFAULT_IMMEDIATE_DATA
- ISCSI_DEFAULT_INITIAL_R2T
- ISCSI_DEFAULT_MAX_BURST_LENGTH
- ISCSI_DEFAULT_MAX_OUTSTANDING_R2T
- ISCSI_DEFAULT_MAX_PDU_LENGTH
- ISCSI_DEFAULT_MTU
- ISCSI_DEF_CMD_PER_LUN
- ISCSI_DEF_FIRST_BURST_LEN
- ISCSI_DEF_MAX_BURST_LEN
- ISCSI_DEF_MAX_RECV_SEG_LEN
- ISCSI_DEF_TIME2WAIT
- ISCSI_DEF_XMIT_CMDS_MAX
- ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK
- ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT
- ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK
- ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT
- ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK
- ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT
- ISCSI_DIGEST_SHIFT
- ISCSI_DIGEST_SIZE
- ISCSI_DISCONTINUITY_TIME
- ISCSI_DISC_PARENT_ISNS
- ISCSI_DISC_PARENT_SENDTGT
- ISCSI_DISC_PARENT_UNKNOWN
- ISCSI_DRAFT20_VERSION
- ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK
- ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT
- ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK
- ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT
- ISCSI_EQE_DATA_RESERVED0_MASK
- ISCSI_EQE_DATA_RESERVED0_SHIFT
- ISCSI_ERROR_UNKNOWN
- ISCSI_ERR_AHSLEN
- ISCSI_ERR_BAD_ITT
- ISCSI_ERR_BAD_OPCODE
- ISCSI_ERR_BASE
- ISCSI_ERR_CONN_FAILED
- ISCSI_ERR_DATALEN
- ISCSI_ERR_DATASN
- ISCSI_ERR_DATA_DGST
- ISCSI_ERR_DATA_OFFSET
- ISCSI_ERR_EXP_CMDSN
- ISCSI_ERR_HDR_DGST
- ISCSI_ERR_INVALID_HOST
- ISCSI_ERR_LUN
- ISCSI_ERR_MAX_CMDSN
- ISCSI_ERR_NOP_TIMEDOUT
- ISCSI_ERR_NO_SCSI_CMD
- ISCSI_ERR_PARAM_NOT_FOUND
- ISCSI_ERR_PROTO
- ISCSI_ERR_R2TSN
- ISCSI_ERR_SCSI_EH_SESSION_RST
- ISCSI_ERR_SESSION_FAILED
- ISCSI_ERR_TCP_CONN_CLOSE
- ISCSI_ERR_XMIT_FAILED
- ISCSI_EVENT_LINKDOWN
- ISCSI_EVENT_LINKUP
- ISCSI_EVENT_MAX
- ISCSI_EVENT_TYPE_ASYN_ABORT_RCVD
- ISCSI_EVENT_TYPE_ASYN_CLOSE_RCVD
- ISCSI_EVENT_TYPE_ASYN_CONNECT_COMPLETE
- ISCSI_EVENT_TYPE_ASYN_FIN_WAIT2
- ISCSI_EVENT_TYPE_ASYN_MAX_KA_PROBES_CNT
- ISCSI_EVENT_TYPE_ASYN_MAX_RT_CNT
- ISCSI_EVENT_TYPE_ASYN_MAX_RT_TIME
- ISCSI_EVENT_TYPE_ASYN_SYN_RCVD
- ISCSI_EVENT_TYPE_ASYN_TERMINATE_DONE
- ISCSI_EVENT_TYPE_CLEAR_SQ
- ISCSI_EVENT_TYPE_COLLECT_STATS_CONN
- ISCSI_EVENT_TYPE_DESTROY_FUNC
- ISCSI_EVENT_TYPE_INIT_FUNC
- ISCSI_EVENT_TYPE_ISCSI_CONN_ERROR
- ISCSI_EVENT_TYPE_MAC_UPDATE_CONN
- ISCSI_EVENT_TYPE_OFFLOAD_CONN
- ISCSI_EVENT_TYPE_START_OF_ERROR_TYPES
- ISCSI_EVENT_TYPE_TCP_CONN_ERROR
- ISCSI_EVENT_TYPE_TERMINATE_CONN
- ISCSI_EVENT_TYPE_UPDATE_CONN
- ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK
- ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK
- ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK
- ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK
- ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_READ_MASK
- ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK
- ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT
- ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK
- ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT
- ISCSI_FLAG_CMD_ATTR_MASK
- ISCSI_FLAG_CMD_BIDI_OVERFLOW
- ISCSI_FLAG_CMD_BIDI_UNDERFLOW
- ISCSI_FLAG_CMD_FINAL
- ISCSI_FLAG_CMD_OVERFLOW
- ISCSI_FLAG_CMD_READ
- ISCSI_FLAG_CMD_UNDERFLOW
- ISCSI_FLAG_CMD_WRITE
- ISCSI_FLAG_DATA_ACK
- ISCSI_FLAG_DATA_OVERFLOW
- ISCSI_FLAG_DATA_STATUS
- ISCSI_FLAG_DATA_UNDERFLOW
- ISCSI_FLAG_LOGIN_CONTINUE
- ISCSI_FLAG_LOGIN_CURRENT_STAGE1
- ISCSI_FLAG_LOGIN_CURRENT_STAGE2
- ISCSI_FLAG_LOGIN_CURRENT_STAGE3
- ISCSI_FLAG_LOGIN_CURRENT_STAGE_MASK
- ISCSI_FLAG_LOGIN_NEXT_STAGE1
- ISCSI_FLAG_LOGIN_NEXT_STAGE2
- ISCSI_FLAG_LOGIN_NEXT_STAGE3
- ISCSI_FLAG_LOGIN_NEXT_STAGE_MASK
- ISCSI_FLAG_LOGIN_TRANSIT
- ISCSI_FLAG_LOGOUT_REASON_MASK
- ISCSI_FLAG_RESIDUAL_OVER
- ISCSI_FLAG_RESIDUAL_UNDER
- ISCSI_FLAG_SNACK_TYPE_DATA
- ISCSI_FLAG_SNACK_TYPE_DATA_ACK
- ISCSI_FLAG_SNACK_TYPE_MASK
- ISCSI_FLAG_SNACK_TYPE_R2T
- ISCSI_FLAG_SNACK_TYPE_RDATA
- ISCSI_FLAG_SNACK_TYPE_STATUS
- ISCSI_FLAG_TEXT_CONTINUE
- ISCSI_FLAG_TM_FUNC_MASK
- ISCSI_FLASHNODE_ALIAS
- ISCSI_FLASHNODE_ATTR
- ISCSI_FLASHNODE_AUTO_SND_TGT_DISABLE
- ISCSI_FLASHNODE_BIDI_CHAP_EN
- ISCSI_FLASHNODE_CHAP_AUTH_EN
- ISCSI_FLASHNODE_CHAP_IN_IDX
- ISCSI_FLASHNODE_CHAP_OUT_IDX
- ISCSI_FLASHNODE_DATASEQ_INORDER
- ISCSI_FLASHNODE_DATA_DGST_EN
- ISCSI_FLASHNODE_DEF_TASKMGMT_TMO
- ISCSI_FLASHNODE_DEF_TIME2RETAIN
- ISCSI_FLASHNODE_DEF_TIME2WAIT
- ISCSI_FLASHNODE_DISCOVERY_AUTH_OPTIONAL
- ISCSI_FLASHNODE_DISCOVERY_LOGOUT_EN
- ISCSI_FLASHNODE_DISCOVERY_PARENT_IDX
- ISCSI_FLASHNODE_DISCOVERY_PARENT_TYPE
- ISCSI_FLASHNODE_DISCOVERY_SESS
- ISCSI_FLASHNODE_ENTRY_EN
- ISCSI_FLASHNODE_ERL
- ISCSI_FLASHNODE_EXP_STATSN
- ISCSI_FLASHNODE_FIRST_BURST
- ISCSI_FLASHNODE_HDR_DGST_EN
- ISCSI_FLASHNODE_IMM_DATA_EN
- ISCSI_FLASHNODE_INITIAL_R2T_EN
- ISCSI_FLASHNODE_IPADDR
- ISCSI_FLASHNODE_IPV4_TOS
- ISCSI_FLASHNODE_IPV6_FLOW_LABEL
- ISCSI_FLASHNODE_IPV6_TC
- ISCSI_FLASHNODE_IP_FRAG_DISABLE
- ISCSI_FLASHNODE_ISID
- ISCSI_FLASHNODE_IS_BOOT_TGT
- ISCSI_FLASHNODE_IS_FW_ASSIGNED_IPV6
- ISCSI_FLASHNODE_KEEPALIVE_TMO
- ISCSI_FLASHNODE_LINK_LOCAL_IPV6
- ISCSI_FLASHNODE_LOCAL_PORT
- ISCSI_FLASHNODE_MAX
- ISCSI_FLASHNODE_MAX_BURST
- ISCSI_FLASHNODE_MAX_R2T
- ISCSI_FLASHNODE_MAX_RECV_DLENGTH
- ISCSI_FLASHNODE_MAX_SEGMENT_SIZE
- ISCSI_FLASHNODE_MAX_XMIT_DLENGTH
- ISCSI_FLASHNODE_NAME
- ISCSI_FLASHNODE_PARAM
- ISCSI_FLASHNODE_PASSWORD
- ISCSI_FLASHNODE_PASSWORD_IN
- ISCSI_FLASHNODE_PDU_INORDER
- ISCSI_FLASHNODE_PORT
- ISCSI_FLASHNODE_PORTAL_TYPE
- ISCSI_FLASHNODE_REDIRECT_IPADDR
- ISCSI_FLASHNODE_SNACK_REQ_EN
- ISCSI_FLASHNODE_STATSN
- ISCSI_FLASHNODE_TCP_NAGLE_DISABLE
- ISCSI_FLASHNODE_TCP_RECV_WSF
- ISCSI_FLASHNODE_TCP_TIMER_SCALE
- ISCSI_FLASHNODE_TCP_TIMESTAMP_EN
- ISCSI_FLASHNODE_TCP_TIMESTAMP_STAT
- ISCSI_FLASHNODE_TCP_WSF_DISABLE
- ISCSI_FLASHNODE_TCP_XMIT_WSF
- ISCSI_FLASHNODE_TPGT
- ISCSI_FLASHNODE_TSID
- ISCSI_FLASHNODE_USERNAME
- ISCSI_FLASHNODE_USERNAME_IN
- ISCSI_FULL_FEATURE_PHASE
- ISCSI_FW_MP_REQUEST_INDEX
- ISCSI_FW_MP_REQUEST_INDEX_SHIFT
- ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION
- ISCSI_FW_MP_REQUEST_LOCAL_COMPLETION_SHIFT
- ISCSI_FW_MP_REQUEST_NUM_RESP_BDS
- ISCSI_FW_MP_REQUEST_NUM_RESP_BDS_SHIFT
- ISCSI_FW_MP_REQUEST_RESERVED1
- ISCSI_FW_MP_REQUEST_RESERVED1_SHIFT
- ISCSI_FW_MP_REQUEST_RESERVED2
- ISCSI_FW_MP_REQUEST_RESERVED2_SHIFT
- ISCSI_FW_MP_REQUEST_RESP_BUFFER_LENGTH
- ISCSI_FW_MP_REQUEST_RESP_BUFFER_LENGTH_SHIFT
- ISCSI_FW_MP_REQUEST_TYPE
- ISCSI_FW_MP_REQUEST_TYPE_SHIFT
- ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN
- ISCSI_FW_MP_REQUEST_UPDATE_EXP_STAT_SN_SHIFT
- ISCSI_FW_RESPONSE_ERR_CODE
- ISCSI_FW_RESPONSE_ERR_CODE_SHIFT
- ISCSI_FW_RESPONSE_RESERVED2
- ISCSI_FW_RESPONSE_RESERVED2_SHIFT
- ISCSI_FW_RESPONSE_RESERVED3
- ISCSI_FW_RESPONSE_RESERVED3_SHIFT
- ISCSI_GET_PDU_TEMPLATE_ADDRESS
- ISCSI_HDR_LEN
- ISCSI_HEADER_SIZE
- ISCSI_HOST_PARAM
- ISCSI_HOST_PARAM_HWADDRESS
- ISCSI_HOST_PARAM_INITIATOR_NAME
- ISCSI_HOST_PARAM_IPADDRESS
- ISCSI_HOST_PARAM_MAX
- ISCSI_HOST_PARAM_NETDEV_NAME
- ISCSI_HOST_PARAM_PORT_SPEED
- ISCSI_HOST_PARAM_PORT_STATE
- ISCSI_HOST_REMOVED
- ISCSI_HOST_SETUP
- ISCSI_HOST_STATS_CUSTOM_DESC_MAX
- ISCSI_HOST_STATS_CUSTOM_MAX
- ISCSI_IBFT_H
- ISCSI_IFACE_ATTR
- ISCSI_IFACE_DISABLE
- ISCSI_IFACE_ENABLE
- ISCSI_IFACE_PARAM
- ISCSI_IFACE_PARAM_BIDI_CHAP_EN
- ISCSI_IFACE_PARAM_CHAP_AUTH_EN
- ISCSI_IFACE_PARAM_DATADGST_EN
- ISCSI_IFACE_PARAM_DATASEQ_INORDER_EN
- ISCSI_IFACE_PARAM_DEF_TASKMGMT_TMO
- ISCSI_IFACE_PARAM_DISCOVERY_AUTH_OPTIONAL
- ISCSI_IFACE_PARAM_DISCOVERY_LOGOUT_EN
- ISCSI_IFACE_PARAM_ERL
- ISCSI_IFACE_PARAM_FIRST_BURST
- ISCSI_IFACE_PARAM_HDRDGST_EN
- ISCSI_IFACE_PARAM_IMM_DATA_EN
- ISCSI_IFACE_PARAM_INITIAL_R2T_EN
- ISCSI_IFACE_PARAM_INITIATOR_NAME
- ISCSI_IFACE_PARAM_MAX_BURST
- ISCSI_IFACE_PARAM_MAX_R2T
- ISCSI_IFACE_PARAM_MAX_RECV_DLENGTH
- ISCSI_IFACE_PARAM_PDU_INORDER_EN
- ISCSI_IFACE_PARAM_STRICT_LOGIN_COMP_EN
- ISCSI_IFACE_TYPE_IPV4
- ISCSI_IFACE_TYPE_IPV6
- ISCSI_IF_H
- ISCSI_INFINIBAND
- ISCSI_INITIAL_LOGIN_STAGE
- ISCSI_INITIAL_SN
- ISCSI_INITIATOR_MODE
- ISCSI_INST_DESCR
- ISCSI_INST_LAST_FAILURE_TYPE
- ISCSI_INST_NUM_NODES
- ISCSI_IOV_DATA_BUFFER
- ISCSI_IPADDR_SIZE
- ISCSI_IPDDRESS_STATE_ACQUIRING
- ISCSI_IPDDRESS_STATE_DEPRECATED
- ISCSI_IPDDRESS_STATE_DISABLING
- ISCSI_IPDDRESS_STATE_INVALID
- ISCSI_IPDDRESS_STATE_TENTATIVE
- ISCSI_IPDDRESS_STATE_UNCONFIGURED
- ISCSI_IPDDRESS_STATE_VALID
- ISCSI_IPV6_AUTOCFG_DHCPV6_ENABLE
- ISCSI_IPV6_AUTOCFG_DISABLE
- ISCSI_IPV6_AUTOCFG_ND_ENABLE
- ISCSI_IPV6_LINKLOCAL_AUTOCFG_DISABLE
- ISCSI_IPV6_LINKLOCAL_AUTOCFG_ENABLE
- ISCSI_IPV6_ROUTER_AUTOCFG_DISABLE
- ISCSI_IPV6_ROUTER_AUTOCFG_ENABLE
- ISCSI_IQN_LEN
- ISCSI_ISER_DEF_SG_TABLESIZE
- ISCSI_ISER_H
- ISCSI_ISER_MAX_CONN
- ISCSI_ISER_MAX_SG_TABLESIZE
- ISCSI_ISER_SG_TABLESIZE
- ISCSI_ITT_ALL_ONES
- ISCSI_ITT_MASK
- ISCSI_IWARP_SCTP
- ISCSI_IWARP_TCP
- ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY
- ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE
- ISCSI_KCQE_COMPLETION_STATUS_CTX_FREE_FAILURE
- ISCSI_KCQE_COMPLETION_STATUS_DATA_DIG_ERR
- ISCSI_KCQE_COMPLETION_STATUS_HDR_DIG_ERR
- ISCSI_KCQE_COMPLETION_STATUS_INVALID_OPCODE
- ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED
- ISCSI_KCQE_COMPLETION_STATUS_LOM_ISCSI_NOT_ENABLED
- ISCSI_KCQE_COMPLETION_STATUS_NIC_ERROR
- ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_AHS_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ASYNC_PDU_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_BUFFER_OFF
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATASN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_IS_ZERO
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_NOT_ZERO
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DATA_SEG_LEN_TOO_BIG
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_0
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_DESIRED_DATA_TRNS_LEN_1
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_EXP_DATASN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_F_BIT_ZERO
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_ITT
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_LUN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_BURST_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_MAX_RCV_PDU_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_NOPIN_PDU_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_OPCODE
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_0
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_1
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_2
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_3
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_4
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_5
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_O_U_6
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_EXCEED
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_PEND_R2T_IN_CLEANUP
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_R2TSN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REJECT_PDU_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_BURST_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_REMAIN_RCV_LEN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_STATSN
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_IS_RSRV
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_TTT_NOT_RSRV
- ISCSI_KCQE_COMPLETION_STATUS_PROTOCOL_ERR_UNEXPECTED_OPCODE
- ISCSI_KCQE_COMPLETION_STATUS_SUCCESS
- ISCSI_KCQE_LAYER_CODE
- ISCSI_KCQE_LAYER_CODE_SHIFT
- ISCSI_KCQE_OPCODE_CQ_EVENT_NOTIFICATION
- ISCSI_KCQE_OPCODE_DESTROY_CONN
- ISCSI_KCQE_OPCODE_FW_CLEAN_TASK
- ISCSI_KCQE_OPCODE_INIT
- ISCSI_KCQE_OPCODE_ISCSI_ERROR
- ISCSI_KCQE_OPCODE_OFFLOAD_CONN
- ISCSI_KCQE_OPCODE_TCP_ERROR
- ISCSI_KCQE_OPCODE_TCP_FIN
- ISCSI_KCQE_OPCODE_TCP_RESET
- ISCSI_KCQE_OPCODE_TCP_SYN
- ISCSI_KCQE_OPCODE_UPDATE_CONN
- ISCSI_KCQE_RESERVED0
- ISCSI_KCQE_RESERVED0_SHIFT
- ISCSI_KCQE_RESERVED1
- ISCSI_KCQE_RESERVED1_SHIFT
- ISCSI_KEVENT_CONN_ERROR
- ISCSI_KEVENT_CONN_LOGIN_STATE
- ISCSI_KEVENT_CREATE_SESSION
- ISCSI_KEVENT_DESTROY_SESSION
- ISCSI_KEVENT_HOST_EVENT
- ISCSI_KEVENT_IF_DOWN
- ISCSI_KEVENT_IF_ERROR
- ISCSI_KEVENT_PATH_REQ
- ISCSI_KEVENT_PING_COMP
- ISCSI_KEVENT_RECV_PDU
- ISCSI_KEVENT_UNBIND_SESSION
- ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST
- ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT
- ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST
- ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT
- ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA
- ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT
- ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T
- ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT
- ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE
- ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT
- ISCSI_KWQE_CONN_UPDATE_RESERVED1
- ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT
- ISCSI_KWQE_HEADER_LAYER_CODE
- ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT
- ISCSI_KWQE_HEADER_RESERVED0
- ISCSI_KWQE_HEADER_RESERVED0_SHIFT
- ISCSI_KWQE_HEADER_RESERVED1
- ISCSI_KWQE_HEADER_RESERVED1_SHIFT
- ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE
- ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT
- ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE
- ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT
- ISCSI_KWQE_INIT1_PAGE_SIZE
- ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT
- ISCSI_KWQE_INIT1_RESERVED1
- ISCSI_KWQE_INIT1_RESERVED1_SHIFT
- ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE
- ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE_SHIFT
- ISCSI_KWQE_LAYER_CODE
- ISCSI_KWQE_OPCODE_DESTROY_CONN
- ISCSI_KWQE_OPCODE_INIT1
- ISCSI_KWQE_OPCODE_INIT2
- ISCSI_KWQE_OPCODE_OFFLOAD_CONN1
- ISCSI_KWQE_OPCODE_OFFLOAD_CONN2
- ISCSI_KWQE_OPCODE_UPDATE_CONN
- ISCSI_LISTEN_PORT
- ISCSI_LOGIN_CURRENT_STAGE
- ISCSI_LOGIN_FAIL_AUTHENTICATE
- ISCSI_LOGIN_FAIL_AUTHORIZE
- ISCSI_LOGIN_FAIL_NEGOTIATE
- ISCSI_LOGIN_FAIL_OTHER
- ISCSI_LOGIN_FAIL_REDIRECT
- ISCSI_LOGIN_NEXT_STAGE
- ISCSI_LOGIN_REQUEST_CONT
- ISCSI_LOGIN_REQUEST_CONT_SHIFT
- ISCSI_LOGIN_REQUEST_CURRENT_STAGE
- ISCSI_LOGIN_REQUEST_CURRENT_STAGE_SHIFT
- ISCSI_LOGIN_REQUEST_INDEX
- ISCSI_LOGIN_REQUEST_INDEX_SHIFT
- ISCSI_LOGIN_REQUEST_NEXT_STAGE
- ISCSI_LOGIN_REQUEST_NEXT_STAGE_SHIFT
- ISCSI_LOGIN_REQUEST_NUM_RESP_BDS
- ISCSI_LOGIN_REQUEST_NUM_RESP_BDS_SHIFT
- ISCSI_LOGIN_REQUEST_RESERVED0
- ISCSI_LOGIN_REQUEST_RESERVED0_SHIFT
- ISCSI_LOGIN_REQUEST_RESERVED5
- ISCSI_LOGIN_REQUEST_RESERVED5_SHIFT
- ISCSI_LOGIN_REQUEST_RESERVED6
- ISCSI_LOGIN_REQUEST_RESERVED6_SHIFT
- ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH
- ISCSI_LOGIN_REQUEST_RESP_BUFFER_LENGTH_SHIFT
- ISCSI_LOGIN_REQUEST_TRANSIT
- ISCSI_LOGIN_REQUEST_TRANSIT_SHIFT
- ISCSI_LOGIN_REQUEST_TYPE
- ISCSI_LOGIN_REQUEST_TYPE_SHIFT
- ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN
- ISCSI_LOGIN_REQUEST_UPDATE_EXP_STAT_SN_SHIFT
- ISCSI_LOGIN_REQ_HDR_CSG_MASK
- ISCSI_LOGIN_REQ_HDR_CSG_SHIFT
- ISCSI_LOGIN_REQ_HDR_C_MASK
- ISCSI_LOGIN_REQ_HDR_C_SHIFT
- ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK
- ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT
- ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT
- ISCSI_LOGIN_REQ_HDR_NSG_MASK
- ISCSI_LOGIN_REQ_HDR_NSG_SHIFT
- ISCSI_LOGIN_REQ_HDR_RSRV_MASK
- ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT
- ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_LOGIN_REQ_HDR_T_MASK
- ISCSI_LOGIN_REQ_HDR_T_SHIFT
- ISCSI_LOGIN_RESPONSE_CONT
- ISCSI_LOGIN_RESPONSE_CONT_SHIFT
- ISCSI_LOGIN_RESPONSE_CURRENT_STAGE
- ISCSI_LOGIN_RESPONSE_CURRENT_STAGE_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK
- ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_C_MASK
- ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK
- ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK
- ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK
- ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_LOGIN_RESPONSE_HDR_T_MASK
- ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT
- ISCSI_LOGIN_RESPONSE_INDEX
- ISCSI_LOGIN_RESPONSE_INDEX_SHIFT
- ISCSI_LOGIN_RESPONSE_NEXT_STAGE
- ISCSI_LOGIN_RESPONSE_NEXT_STAGE_SHIFT
- ISCSI_LOGIN_RESPONSE_RESERVED0
- ISCSI_LOGIN_RESPONSE_RESERVED0_SHIFT
- ISCSI_LOGIN_RESPONSE_TRANSIT
- ISCSI_LOGIN_RESPONSE_TRANSIT_SHIFT
- ISCSI_LOGIN_RESPONSE_TYPE
- ISCSI_LOGIN_RESPONSE_TYPE_SHIFT
- ISCSI_LOGIN_STATUS_ACCEPT
- ISCSI_LOGIN_STATUS_AUTH_FAILED
- ISCSI_LOGIN_STATUS_CONN_ADD_FAILED
- ISCSI_LOGIN_STATUS_INIT_ERR
- ISCSI_LOGIN_STATUS_INVALID_REQUEST
- ISCSI_LOGIN_STATUS_ISID_ERROR
- ISCSI_LOGIN_STATUS_MISSING_FIELDS
- ISCSI_LOGIN_STATUS_NO_RESOURCES
- ISCSI_LOGIN_STATUS_NO_SESSION
- ISCSI_LOGIN_STATUS_NO_SESSION_TYPE
- ISCSI_LOGIN_STATUS_NO_VERSION
- ISCSI_LOGIN_STATUS_SVC_UNAVAILABLE
- ISCSI_LOGIN_STATUS_TARGET_ERROR
- ISCSI_LOGIN_STATUS_TGT_FORBIDDEN
- ISCSI_LOGIN_STATUS_TGT_MOVED_PERM
- ISCSI_LOGIN_STATUS_TGT_MOVED_TEMP
- ISCSI_LOGIN_STATUS_TGT_NOT_FOUND
- ISCSI_LOGIN_STATUS_TGT_REMOVED
- ISCSI_LOGOUT_CID_NOT_FOUND
- ISCSI_LOGOUT_CLEANUP_FAILED
- ISCSI_LOGOUT_REASON_AEN_REQUEST
- ISCSI_LOGOUT_REASON_CLOSE_CONNECTION
- ISCSI_LOGOUT_REASON_CLOSE_SESSION
- ISCSI_LOGOUT_REASON_RECOVERY
- ISCSI_LOGOUT_RECOVERY_UNSUPPORTED
- ISCSI_LOGOUT_REQUEST_ALWAYS_ONE
- ISCSI_LOGOUT_REQUEST_ALWAYS_ONE_SHIFT
- ISCSI_LOGOUT_REQUEST_INDEX
- ISCSI_LOGOUT_REQUEST_INDEX_SHIFT
- ISCSI_LOGOUT_REQUEST_REASON
- ISCSI_LOGOUT_REQUEST_REASON_SHIFT
- ISCSI_LOGOUT_REQUEST_TYPE
- ISCSI_LOGOUT_REQUEST_TYPE_SHIFT
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK
- ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_LOGOUT_RESPONSE_INDEX
- ISCSI_LOGOUT_RESPONSE_INDEX_SHIFT
- ISCSI_LOGOUT_RESPONSE_TYPE
- ISCSI_LOGOUT_RESPONSE_TYPE_SHIFT
- ISCSI_LOGOUT_SUCCESS
- ISCSI_MAX_AHS_SIZE
- ISCSI_MAX_BDS_PER_CMD
- ISCSI_MAX_CMDS_PER_HBA_5708
- ISCSI_MAX_CMDS_PER_HBA_5709
- ISCSI_MAX_CMDS_PER_HBA_57710
- ISCSI_MAX_CMDS_PER_SESS
- ISCSI_MAX_CONNS_PER_HBA
- ISCSI_MAX_DATASN_MISSING_COUNT
- ISCSI_MAX_EPID
- ISCSI_MAX_FIRST_BURST_LEN
- ISCSI_MAX_MAX_BURST_LEN
- ISCSI_MAX_MAX_RECV_SEG_LEN
- ISCSI_MAX_SESS_PER_HBA
- ISCSI_MAX_TARGET
- ISCSI_MAX_VAL_BURST_LENGTH
- ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T
- ISCSI_MAX_VAL_MAX_PDU_LENGTH
- ISCSI_MAX_VLAN_ID
- ISCSI_MAX_VLAN_PRIORITY
- ISCSI_MEM_GLOBAL_HEADER
- ISCSI_MGMT_CMDS_MAX
- ISCSI_MIN_FIRST_BURST_LEN
- ISCSI_MIN_MAX_BURST_LEN
- ISCSI_MIN_MAX_RECV_SEG_LEN
- ISCSI_MIN_VAL_BURST_LENGTH
- ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T
- ISCSI_MIN_VAL_MAX_PDU_LENGTH
- ISCSI_MISC_IOVECS
- ISCSI_MSG_MAX
- ISCSI_NACL_ATTR
- ISCSI_NACL_PARAM
- ISCSI_NAME_LEN
- ISCSI_NAME_SIZE
- ISCSI_NET_PARAM
- ISCSI_NET_PARAM_CACHE_ID
- ISCSI_NET_PARAM_DELAYED_ACK_EN
- ISCSI_NET_PARAM_DISABLE
- ISCSI_NET_PARAM_ENABLE
- ISCSI_NET_PARAM_IFACE_ENABLE
- ISCSI_NET_PARAM_IFACE_NAME
- ISCSI_NET_PARAM_IFACE_TYPE
- ISCSI_NET_PARAM_IPADDR_STATE
- ISCSI_NET_PARAM_IPV4_ADDR
- ISCSI_NET_PARAM_IPV4_BOOTPROTO
- ISCSI_NET_PARAM_IPV4_DHCP_ALT_CLIENT_ID
- ISCSI_NET_PARAM_IPV4_DHCP_ALT_CLIENT_ID_EN
- ISCSI_NET_PARAM_IPV4_DHCP_DNS_ADDR_EN
- ISCSI_NET_PARAM_IPV4_DHCP_LEARN_IQN_EN
- ISCSI_NET_PARAM_IPV4_DHCP_REQ_VENDOR_ID_EN
- ISCSI_NET_PARAM_IPV4_DHCP_SLP_DA_EN
- ISCSI_NET_PARAM_IPV4_DHCP_USE_VENDOR_ID_EN
- ISCSI_NET_PARAM_IPV4_DHCP_VENDOR_ID
- ISCSI_NET_PARAM_IPV4_FRAGMENT_DISABLE
- ISCSI_NET_PARAM_IPV4_GRAT_ARP_EN
- ISCSI_NET_PARAM_IPV4_GW
- ISCSI_NET_PARAM_IPV4_IN_FORWARD_EN
- ISCSI_NET_PARAM_IPV4_SUBNET
- ISCSI_NET_PARAM_IPV4_TOS
- ISCSI_NET_PARAM_IPV4_TOS_EN
- ISCSI_NET_PARAM_IPV4_TTL
- ISCSI_NET_PARAM_IPV6_ADDR
- ISCSI_NET_PARAM_IPV6_ADDR_AUTOCFG
- ISCSI_NET_PARAM_IPV6_DUP_ADDR_DETECT_CNT
- ISCSI_NET_PARAM_IPV6_FLOW_LABEL
- ISCSI_NET_PARAM_IPV6_GRAT_NEIGHBOR_ADV_EN
- ISCSI_NET_PARAM_IPV6_HOP_LIMIT
- ISCSI_NET_PARAM_IPV6_LINKLOCAL
- ISCSI_NET_PARAM_IPV6_LINKLOCAL_AUTOCFG
- ISCSI_NET_PARAM_IPV6_LINKLOCAL_STATE
- ISCSI_NET_PARAM_IPV6_MLD_EN
- ISCSI_NET_PARAM_IPV6_ND_REACHABLE_TMO
- ISCSI_NET_PARAM_IPV6_ND_REXMIT_TIME
- ISCSI_NET_PARAM_IPV6_ND_STALE_TMO
- ISCSI_NET_PARAM_IPV6_ROUTER
- ISCSI_NET_PARAM_IPV6_ROUTER_AUTOCFG
- ISCSI_NET_PARAM_IPV6_ROUTER_STATE
- ISCSI_NET_PARAM_IPV6_RTR_ADV_LINK_MTU
- ISCSI_NET_PARAM_IPV6_TRAFFIC_CLASS
- ISCSI_NET_PARAM_MAC
- ISCSI_NET_PARAM_MTU
- ISCSI_NET_PARAM_PORT
- ISCSI_NET_PARAM_REDIRECT_EN
- ISCSI_NET_PARAM_TCP_NAGLE_DISABLE
- ISCSI_NET_PARAM_TCP_TIMER_SCALE
- ISCSI_NET_PARAM_TCP_TIMESTAMP_EN
- ISCSI_NET_PARAM_TCP_WSF
- ISCSI_NET_PARAM_TCP_WSF_DISABLE
- ISCSI_NET_PARAM_VLAN_ENABLED
- ISCSI_NET_PARAM_VLAN_ID
- ISCSI_NET_PARAM_VLAN_PRIORITY
- ISCSI_NET_PARAM_VLAN_TAG
- ISCSI_NL_GRP_ISCSID
- ISCSI_NL_GRP_UIP
- ISCSI_NODE_INDEX
- ISCSI_NOP_IN_HDR_CONST1_MASK
- ISCSI_NOP_IN_HDR_CONST1_SHIFT
- ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK
- ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_NOP_IN_HDR_RSRV_MASK
- ISCSI_NOP_IN_HDR_RSRV_SHIFT
- ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_NOP_IN_MSG_INDEX
- ISCSI_NOP_IN_MSG_INDEX_SHIFT
- ISCSI_NOP_IN_MSG_TYPE
- ISCSI_NOP_IN_MSG_TYPE_SHIFT
- ISCSI_NOP_OUT_HDR_CONST1_MASK
- ISCSI_NOP_OUT_HDR_CONST1_SHIFT
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_NOP_OUT_HDR_RSRV_MASK
- ISCSI_NOP_OUT_HDR_RSRV_SHIFT
- ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE
- ISCSI_NOP_OUT_REQUEST_ALWAYS_ONE_SHIFT
- ISCSI_NOP_OUT_REQUEST_INDEX
- ISCSI_NOP_OUT_REQUEST_INDEX_SHIFT
- ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION
- ISCSI_NOP_OUT_REQUEST_LOCAL_COMPLETION_SHIFT
- ISCSI_NOP_OUT_REQUEST_NUM_RESP_BDS
- ISCSI_NOP_OUT_REQUEST_NUM_RESP_BDS_SHIFT
- ISCSI_NOP_OUT_REQUEST_RESERVED1
- ISCSI_NOP_OUT_REQUEST_RESERVED1_SHIFT
- ISCSI_NOP_OUT_REQUEST_RESERVED4
- ISCSI_NOP_OUT_REQUEST_RESERVED4_SHIFT
- ISCSI_NOP_OUT_REQUEST_RESP_BUFFER_LENGTH
- ISCSI_NOP_OUT_REQUEST_RESP_BUFFER_LENGTH_SHIFT
- ISCSI_NOP_OUT_REQUEST_TYPE
- ISCSI_NOP_OUT_REQUEST_TYPE_SHIFT
- ISCSI_NOP_OUT_REQUEST_ZERO_FILL
- ISCSI_NOP_OUT_REQUEST_ZERO_FILL_SHIFT
- ISCSI_NP_THREAD_ACTIVE
- ISCSI_NP_THREAD_EXIT
- ISCSI_NP_THREAD_INACTIVE
- ISCSI_NP_THREAD_RESET
- ISCSI_NP_THREAD_SHUTDOWN
- ISCSI_OK
- ISCSI_OPCODE_ASYNC_MSG
- ISCSI_OPCODE_CLEANUP_REQUEST
- ISCSI_OPCODE_CLEANUP_RESPONSE
- ISCSI_OPCODE_DATA_IN
- ISCSI_OPCODE_DATA_OUT
- ISCSI_OPCODE_LOGIN_REQUEST
- ISCSI_OPCODE_LOGIN_RESPONSE
- ISCSI_OPCODE_LOGOUT_REQUEST
- ISCSI_OPCODE_LOGOUT_RESPONSE
- ISCSI_OPCODE_MASK
- ISCSI_OPCODE_NOPOUT_LOCAL_COMPLETION
- ISCSI_OPCODE_NOP_IN
- ISCSI_OPCODE_NOP_OUT
- ISCSI_OPCODE_R2T
- ISCSI_OPCODE_REJECT
- ISCSI_OPCODE_SCSI_CMD
- ISCSI_OPCODE_SCSI_DATA_OUT
- ISCSI_OPCODE_SCSI_RESPONSE
- ISCSI_OPCODE_TEXT_REQUEST
- ISCSI_OPCODE_TEXT_RESPONSE
- ISCSI_OPCODE_TMF_REQUEST
- ISCSI_OPCODE_TMF_RESPONSE
- ISCSI_OPTION_1_OFF_CHIP_TCP
- ISCSI_OPTION_2_ON_CHIP_TCP
- ISCSI_OP_ASYNC_EVENT
- ISCSI_OP_IMMEDIATE
- ISCSI_OP_LOGIN
- ISCSI_OP_LOGIN_RSP
- ISCSI_OP_LOGOUT
- ISCSI_OP_LOGOUT_RSP
- ISCSI_OP_NOOP_IN
- ISCSI_OP_NOOP_OUT
- ISCSI_OP_PARMS_NEGOTIATION_STAGE
- ISCSI_OP_R2T
- ISCSI_OP_REJECT
- ISCSI_OP_RETRY
- ISCSI_OP_SCSI_CMD
- ISCSI_OP_SCSI_CMD_RSP
- ISCSI_OP_SCSI_DATA_IN
- ISCSI_OP_SCSI_DATA_OUT
- ISCSI_OP_SCSI_TMFUNC
- ISCSI_OP_SCSI_TMFUNC_RSP
- ISCSI_OP_SNACK
- ISCSI_OP_TEXT
- ISCSI_OP_TEXT_RSP
- ISCSI_OP_VENDOR1_CMD
- ISCSI_OP_VENDOR2_CMD
- ISCSI_OP_VENDOR3_CMD
- ISCSI_OP_VENDOR4_CMD
- ISCSI_PAD_LEN
- ISCSI_PAGE_SIZE_128K
- ISCSI_PAGE_SIZE_16K
- ISCSI_PAGE_SIZE_1K
- ISCSI_PAGE_SIZE_1M
- ISCSI_PAGE_SIZE_256
- ISCSI_PAGE_SIZE_256K
- ISCSI_PAGE_SIZE_2K
- ISCSI_PAGE_SIZE_2M
- ISCSI_PAGE_SIZE_32K
- ISCSI_PAGE_SIZE_4K
- ISCSI_PAGE_SIZE_4M
- ISCSI_PAGE_SIZE_512
- ISCSI_PAGE_SIZE_512K
- ISCSI_PAGE_SIZE_64K
- ISCSI_PAGE_SIZE_8K
- ISCSI_PAGE_SIZE_8M
- ISCSI_PARAM
- ISCSI_PARAMETERS_H
- ISCSI_PARAM_ABORT_TMO
- ISCSI_PARAM_AUTO_SND_TGT_DISABLE
- ISCSI_PARAM_BIDI_CHAP_EN
- ISCSI_PARAM_BOOT_NIC
- ISCSI_PARAM_BOOT_ROOT
- ISCSI_PARAM_BOOT_TARGET
- ISCSI_PARAM_CHAP_AUTH_EN
- ISCSI_PARAM_CHAP_IN_IDX
- ISCSI_PARAM_CHAP_OUT_IDX
- ISCSI_PARAM_CONN_ADDRESS
- ISCSI_PARAM_CONN_PORT
- ISCSI_PARAM_DATADGST_EN
- ISCSI_PARAM_DATASEQ_INORDER_EN
- ISCSI_PARAM_DEF_TASKMGMT_TMO
- ISCSI_PARAM_DEF_TIME2RETAIN
- ISCSI_PARAM_DEF_TIME2WAIT
- ISCSI_PARAM_DISCOVERY_AUTH_OPTIONAL
- ISCSI_PARAM_DISCOVERY_LOGOUT_EN
- ISCSI_PARAM_DISCOVERY_PARENT_IDX
- ISCSI_PARAM_DISCOVERY_PARENT_TYPE
- ISCSI_PARAM_DISCOVERY_SESS
- ISCSI_PARAM_ERL
- ISCSI_PARAM_EXP_STATSN
- ISCSI_PARAM_FAST_ABORT
- ISCSI_PARAM_FIRST_BURST
- ISCSI_PARAM_HDRDGST_EN
- ISCSI_PARAM_HOST_RESET_TMO
- ISCSI_PARAM_IFACE_NAME
- ISCSI_PARAM_IFMARKER_EN
- ISCSI_PARAM_IMM_DATA_EN
- ISCSI_PARAM_INITIAL_R2T_EN
- ISCSI_PARAM_INITIATOR_NAME
- ISCSI_PARAM_IPV4_TOS
- ISCSI_PARAM_IPV6_FLOW_LABEL
- ISCSI_PARAM_IPV6_TC
- ISCSI_PARAM_IP_FRAGMENT_DISABLE
- ISCSI_PARAM_ISID
- ISCSI_PARAM_IS_FW_ASSIGNED_IPV6
- ISCSI_PARAM_KEEPALIVE_TMO
- ISCSI_PARAM_LOCAL_IPADDR
- ISCSI_PARAM_LOCAL_PORT
- ISCSI_PARAM_LU_RESET_TMO
- ISCSI_PARAM_MAX
- ISCSI_PARAM_MAX_BURST
- ISCSI_PARAM_MAX_R2T
- ISCSI_PARAM_MAX_RECV_DLENGTH
- ISCSI_PARAM_MAX_SEGMENT_SIZE
- ISCSI_PARAM_MAX_XMIT_DLENGTH
- ISCSI_PARAM_OFMARKER_EN
- ISCSI_PARAM_PASSWORD
- ISCSI_PARAM_PASSWORD_IN
- ISCSI_PARAM_PDU_INORDER_EN
- ISCSI_PARAM_PERSISTENT_ADDRESS
- ISCSI_PARAM_PERSISTENT_PORT
- ISCSI_PARAM_PING_TMO
- ISCSI_PARAM_PORTAL_TYPE
- ISCSI_PARAM_RECV_TMO
- ISCSI_PARAM_SESS_RECOVERY_TMO
- ISCSI_PARAM_STATSN
- ISCSI_PARAM_TARGET_ALIAS
- ISCSI_PARAM_TARGET_NAME
- ISCSI_PARAM_TCP_NAGLE_DISABLE
- ISCSI_PARAM_TCP_RECV_WSF
- ISCSI_PARAM_TCP_TIMER_SCALE
- ISCSI_PARAM_TCP_TIMESTAMP_EN
- ISCSI_PARAM_TCP_TIMESTAMP_STAT
- ISCSI_PARAM_TCP_WSF_DISABLE
- ISCSI_PARAM_TCP_XMIT_WSF
- ISCSI_PARAM_TGT_RESET_TMO
- ISCSI_PARAM_TPGT
- ISCSI_PARAM_TSID
- ISCSI_PARAM_USERNAME
- ISCSI_PARAM_USERNAME_IN
- ISCSI_PDU_CRC_FAILED
- ISCSI_PDU_LEN_G
- ISCSI_PDU_LEN_M
- ISCSI_PDU_LEN_S
- ISCSI_PDU_LEN_V
- ISCSI_PDU_NONPAYLOAD_LEN
- ISCSI_PDU_NONPAYLOAD_MAX
- ISCSI_PDU_NOT_RECEIVED
- ISCSI_PDU_READ
- ISCSI_PDU_RECEIVED_OK
- ISCSI_PDU_TIMED_OUT
- ISCSI_PDU_WRITE
- ISCSI_PING_FW_DISABLED
- ISCSI_PING_ICMP_ERROR
- ISCSI_PING_INVALID_DEST_ADDR
- ISCSI_PING_IPADDR_INVALID
- ISCSI_PING_LINKLOCAL_IPV6_ADDR_INVALID
- ISCSI_PING_MAX_REQ_EXCEEDED
- ISCSI_PING_NO_ARP_RECEIVED
- ISCSI_PING_OVERSIZE_PACKET
- ISCSI_PING_SUCCESS
- ISCSI_PING_TIMEOUT
- ISCSI_PORT_SPEED_100MBPS
- ISCSI_PORT_SPEED_10GBPS
- ISCSI_PORT_SPEED_10MBPS
- ISCSI_PORT_SPEED_1GBPS
- ISCSI_PORT_SPEED_25GBPS
- ISCSI_PORT_SPEED_40GBPS
- ISCSI_PORT_SPEED_UNKNOWN
- ISCSI_PORT_STATE_DOWN
- ISCSI_PORT_STATE_UP
- ISCSI_PROTO_H
- ISCSI_RAMROD_CMD_ID_CLEAR_SQ
- ISCSI_RAMROD_CMD_ID_CONN_STATS
- ISCSI_RAMROD_CMD_ID_DESTROY_FUNC
- ISCSI_RAMROD_CMD_ID_INIT
- ISCSI_RAMROD_CMD_ID_INIT_FUNC
- ISCSI_RAMROD_CMD_ID_MAC_UPDATE
- ISCSI_RAMROD_CMD_ID_OFFLOAD_CONN
- ISCSI_RAMROD_CMD_ID_TERMINATION_CONN
- ISCSI_RAMROD_CMD_ID_UNUSED
- ISCSI_RAMROD_CMD_ID_UPDATE_CONN
- ISCSI_REASON_BOOKMARK_INVALID
- ISCSI_REASON_BOOKMARK_NO_RESOURCES
- ISCSI_REASON_CMD_BEFORE_LOGIN
- ISCSI_REASON_CMD_NOT_SUPPORTED
- ISCSI_REASON_DATA_DIGEST_ERROR
- ISCSI_REASON_DATA_SNACK_REJECT
- ISCSI_REASON_IMM_CMD_REJECT
- ISCSI_REASON_INVALID_SNACK
- ISCSI_REASON_NEGOTIATION_RESET
- ISCSI_REASON_PROTOCOL_ERROR
- ISCSI_REASON_TASK_IN_PROGRESS
- ISCSI_REG1_NUM_SGES_MASK
- ISCSI_REG1_NUM_SGES_SHIFT
- ISCSI_REG1_RESERVED1_MASK
- ISCSI_REG1_RESERVED1_SHIFT
- ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK
- ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_RESERVED_TAG
- ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK
- ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_ROUTER_STATE_ADVERTISED
- ISCSI_ROUTER_STATE_MANUAL
- ISCSI_ROUTER_STATE_STALE
- ISCSI_ROUTER_STATE_UNKNOWN
- ISCSI_RQ_DB_SIZE
- ISCSI_RX_DATA
- ISCSI_RX_THREAD_NAME
- ISCSI_RX_THREAD_TCP_TIMEOUT
- ISCSI_SCTP_TCP
- ISCSI_SCTP_UDP
- ISCSI_SECURITY_NEGOTIATION_STAGE
- ISCSI_SEND_MAX_ALLOWED
- ISCSI_SENSE_BUFFER_LEN
- ISCSI_SEQ_AND_PDU_LIST_H
- ISCSI_SESSION_FAILED
- ISCSI_SESSION_FREE
- ISCSI_SESSION_LOGGED_IN
- ISCSI_SESS_ERR_CXN_TIMEOUT
- ISCSI_SESS_ERR_DIGEST
- ISCSI_SESS_ERR_PDU_FORMAT
- ISCSI_SESS_ERR_UNKNOWN
- ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK
- ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT
- ISCSI_SLOW_PATH_HDR_RESERVED0_MASK
- ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT
- ISCSI_SLOW_PATH_HDR_RESERVED1_MASK
- ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT
- ISCSI_SLOW_PATH_LAYER_CODE
- ISCSI_SPE_FUNC_INIT_COUNTERS_EN_MASK
- ISCSI_SPE_FUNC_INIT_COUNTERS_EN_SHIFT
- ISCSI_SPE_FUNC_INIT_RESERVED0_MASK
- ISCSI_SPE_FUNC_INIT_RESERVED0_SHIFT
- ISCSI_SQN_TO_NOTIFY_NOT_VALID
- ISCSI_SQ_DB_SIZE
- ISCSI_STAGE_FULL_FEATURE_PHASE
- ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION
- ISCSI_STAGE_SECURITY_NEGOTIATION
- ISCSI_STATE_FAILED
- ISCSI_STATE_FREE
- ISCSI_STATE_IN_RECOVERY
- ISCSI_STATE_LOGGED_IN
- ISCSI_STATE_LOGGING_OUT
- ISCSI_STATE_RECOVERY_FAILED
- ISCSI_STATE_TERMINATE
- ISCSI_STATS_CUSTOM_DESC_MAX
- ISCSI_STATS_CUSTOM_MAX
- ISCSI_STATS_OPCODE
- ISCSI_STATUS_CLS_INITIATOR_ERR
- ISCSI_STATUS_CLS_REDIRECT
- ISCSI_STATUS_CLS_SUCCESS
- ISCSI_STATUS_CLS_TARGET_ERR
- ISCSI_STATUS_CMD_COMPLETED
- ISCSI_STATUS_NONE
- ISCSI_STATUS_SUBSYS_FAILURE
- ISCSI_STATUS_TARGET_FAILURE
- ISCSI_SUSPEND_BIT
- ISCSI_SW_TCP_DBG
- ISCSI_SW_TCP_H
- ISCSI_TARGET_CORE_H
- ISCSI_TARGET_DATAIN_VALUES_H
- ISCSI_TARGET_DEVICE_H
- ISCSI_TARGET_ERL0_H
- ISCSI_TARGET_ERL1_H
- ISCSI_TARGET_ERL2_H
- ISCSI_TARGET_H
- ISCSI_TARGET_LOGIN_H
- ISCSI_TARGET_MODE
- ISCSI_TARGET_NEGO_H
- ISCSI_TARGET_NODEATTRIB_H
- ISCSI_TARGET_STAT_H
- ISCSI_TARGET_TMR_H
- ISCSI_TARGET_TPG_H
- ISCSI_TARGET_UTIL_H
- ISCSI_TASK_ABRT_SESS_RECOV
- ISCSI_TASK_ABRT_TMF
- ISCSI_TASK_COMPLETED
- ISCSI_TASK_FREE
- ISCSI_TASK_PENDING
- ISCSI_TASK_REQUEUE_SCSIQ
- ISCSI_TASK_RUNNING
- ISCSI_TASK_TYPE_EXCHCLEANUP
- ISCSI_TASK_TYPE_INITIATOR_READ
- ISCSI_TASK_TYPE_INITIATOR_WRITE
- ISCSI_TASK_TYPE_IRRELEVANT
- ISCSI_TASK_TYPE_LOGIN_RESPONSE
- ISCSI_TASK_TYPE_MIDPATH
- ISCSI_TASK_TYPE_MPATH
- ISCSI_TASK_TYPE_READ
- ISCSI_TASK_TYPE_TARGET_IMM_W_DIF
- ISCSI_TASK_TYPE_TARGET_READ
- ISCSI_TASK_TYPE_TARGET_RESPONSE
- ISCSI_TASK_TYPE_TARGET_WRITE
- ISCSI_TASK_TYPE_UNSOLIC
- ISCSI_TASK_TYPE_WRITE
- ISCSI_TCP
- ISCSI_TCP_CONN_ERR
- ISCSI_TCP_SEGMENT_DONE
- ISCSI_TCP_SKB_DONE
- ISCSI_TCP_SUSPENDED
- ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT
- ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT
- ISCSI_TERM_VARS_FIN_RECEIVED_SBIT
- ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT
- ISCSI_TERM_VARS_RSRV
- ISCSI_TERM_VARS_RSRV_SHIFT
- ISCSI_TERM_VARS_TCP_STATE
- ISCSI_TERM_VARS_TCP_STATE_SHIFT
- ISCSI_TERM_VARS_TERM_ON_CHIP
- ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT
- ISCSI_TEXT_REQUEST_CONT
- ISCSI_TEXT_REQUEST_CONT_SHIFT
- ISCSI_TEXT_REQUEST_FINAL
- ISCSI_TEXT_REQUEST_FINAL_SHIFT
- ISCSI_TEXT_REQUEST_HDR_C_MASK
- ISCSI_TEXT_REQUEST_HDR_C_SHIFT
- ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK
- ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_TEXT_REQUEST_HDR_F_MASK
- ISCSI_TEXT_REQUEST_HDR_F_SHIFT
- ISCSI_TEXT_REQUEST_HDR_RSRV_MASK
- ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT
- ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_TEXT_REQUEST_INDEX
- ISCSI_TEXT_REQUEST_INDEX_SHIFT
- ISCSI_TEXT_REQUEST_NUM_RESP_BDS
- ISCSI_TEXT_REQUEST_NUM_RESP_BDS_SHIFT
- ISCSI_TEXT_REQUEST_RESERVED1
- ISCSI_TEXT_REQUEST_RESERVED1_SHIFT
- ISCSI_TEXT_REQUEST_RESP_BUFFER_LENGTH
- ISCSI_TEXT_REQUEST_RESP_BUFFER_LENGTH_SHIFT
- ISCSI_TEXT_REQUEST_TYPE
- ISCSI_TEXT_REQUEST_TYPE_SHIFT
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_TEXT_RESPONSE_CONT
- ISCSI_TEXT_RESPONSE_CONT_SHIFT
- ISCSI_TEXT_RESPONSE_FINAL
- ISCSI_TEXT_RESPONSE_FINAL_SHIFT
- ISCSI_TEXT_RESPONSE_HDR_C_MASK
- ISCSI_TEXT_RESPONSE_HDR_C_SHIFT
- ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK
- ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_TEXT_RESPONSE_HDR_F_MASK
- ISCSI_TEXT_RESPONSE_HDR_F_SHIFT
- ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK
- ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT
- ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_TEXT_RESPONSE_INDEX
- ISCSI_TEXT_RESPONSE_INDEX_SHIFT
- ISCSI_TEXT_RESPONSE_RESERVED1
- ISCSI_TEXT_RESPONSE_RESERVED1_SHIFT
- ISCSI_TEXT_RESPONSE_TYPE
- ISCSI_TEXT_RESPONSE_TYPE_SHIFT
- ISCSI_TF_EXPIRED
- ISCSI_TF_RUNNING
- ISCSI_TF_STOP
- ISCSI_TGT_DSCVR_ISNS
- ISCSI_TGT_DSCVR_SEND_TARGETS
- ISCSI_TGT_DSCVR_SLP
- ISCSI_TMF_REQUEST_ALWAYS_ONE
- ISCSI_TMF_REQUEST_ALWAYS_ONE_SHIFT
- ISCSI_TMF_REQUEST_FUNCTION
- ISCSI_TMF_REQUEST_FUNCTION_SHIFT
- ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK
- ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_TMF_REQUEST_INDEX
- ISCSI_TMF_REQUEST_INDEX_SHIFT
- ISCSI_TMF_REQUEST_TYPE
- ISCSI_TMF_REQUEST_TYPE_SHIFT
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH
- ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT
- ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK
- ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT
- ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK
- ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT
- ISCSI_TMF_RESPONSE_INDEX
- ISCSI_TMF_RESPONSE_INDEX_SHIFT
- ISCSI_TMF_RESPONSE_TYPE
- ISCSI_TMF_RESPONSE_TYPE_SHIFT
- ISCSI_TMF_RSP_AUTH_FAILED
- ISCSI_TMF_RSP_COMPLETE
- ISCSI_TMF_RSP_NOT_SUPPORTED
- ISCSI_TMF_RSP_NO_FAILOVER
- ISCSI_TMF_RSP_NO_LUN
- ISCSI_TMF_RSP_NO_TASK
- ISCSI_TMF_RSP_REJECTED
- ISCSI_TMF_RSP_TASK_ALLEGIANT
- ISCSI_TM_FUNC_ABORT_TASK
- ISCSI_TM_FUNC_ABORT_TASK_SET
- ISCSI_TM_FUNC_CLEAR_ACA
- ISCSI_TM_FUNC_CLEAR_TASK_SET
- ISCSI_TM_FUNC_LOGICAL_UNIT_RESET
- ISCSI_TM_FUNC_TARGET_COLD_RESET
- ISCSI_TM_FUNC_TARGET_WARM_RESET
- ISCSI_TM_FUNC_TASK_REASSIGN
- ISCSI_TM_FUNC_VALUE
- ISCSI_TOTAL_CMDS_MAX
- ISCSI_TOTAL_CMDS_MIN
- ISCSI_TRANSPORT_VERSION
- ISCSI_TTT_ALL_ONES
- ISCSI_TX_CONTROL
- ISCSI_TX_DATA
- ISCSI_TX_DATAIN
- ISCSI_TX_DATAOUT
- ISCSI_TX_SCSI_COMMAND
- ISCSI_TX_THREAD_NAME
- ISCSI_TX_THREAD_TCP_TIMEOUT
- ISCSI_UEVENT_BIND_CONN
- ISCSI_UEVENT_CREATE_BOUND_SESSION
- ISCSI_UEVENT_CREATE_CONN
- ISCSI_UEVENT_CREATE_SESSION
- ISCSI_UEVENT_DELETE_CHAP
- ISCSI_UEVENT_DEL_FLASHNODE
- ISCSI_UEVENT_DESTROY_CONN
- ISCSI_UEVENT_DESTROY_SESSION
- ISCSI_UEVENT_GET_CHAP
- ISCSI_UEVENT_GET_HOST_STATS
- ISCSI_UEVENT_GET_PARAM
- ISCSI_UEVENT_GET_STATS
- ISCSI_UEVENT_LOGIN_FLASHNODE
- ISCSI_UEVENT_LOGOUT_FLASHNODE
- ISCSI_UEVENT_LOGOUT_FLASHNODE_SID
- ISCSI_UEVENT_NEW_FLASHNODE
- ISCSI_UEVENT_PATH_UPDATE
- ISCSI_UEVENT_PING
- ISCSI_UEVENT_SEND_PDU
- ISCSI_UEVENT_SET_CHAP
- ISCSI_UEVENT_SET_FLASHNODE_PARAMS
- ISCSI_UEVENT_SET_HOST_PARAM
- ISCSI_UEVENT_SET_IFACE_PARAMS
- ISCSI_UEVENT_SET_PARAM
- ISCSI_UEVENT_START_CONN
- ISCSI_UEVENT_STOP_CONN
- ISCSI_UEVENT_TGT_DSCVR
- ISCSI_UEVENT_TRANSPORT_EP_CONNECT
- ISCSI_UEVENT_TRANSPORT_EP_CONNECT_THROUGH_HOST
- ISCSI_UEVENT_TRANSPORT_EP_DISCONNECT
- ISCSI_UEVENT_TRANSPORT_EP_POLL
- ISCSI_UEVENT_UNBIND_SESSION
- ISCSI_UEVENT_UNKNOWN
- ISCSI_UHQE_BUFFER_OFFSET_MASK
- ISCSI_UHQE_BUFFER_OFFSET_SHIFT
- ISCSI_UHQE_LOCAL_COMP_MASK
- ISCSI_UHQE_LOCAL_COMP_SHIFT
- ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK
- ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT
- ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK
- ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT
- ISCSI_UHQE_PURE_PAYLOAD_MASK
- ISCSI_UHQE_PURE_PAYLOAD_SHIFT
- ISCSI_UHQE_TASK_ID_HI_MASK
- ISCSI_UHQE_TASK_ID_HI_SHIFT
- ISCSI_UHQE_TASK_ID_LO_MASK
- ISCSI_UHQE_TASK_ID_LO_SHIFT
- ISCSI_UHQE_TOGGLE_BIT_MASK
- ISCSI_UHQE_TOGGLE_BIT_SHIFT
- ISCSI_VLAN_DISABLE
- ISCSI_VLAN_ENABLE
- ISCSI_WQE_CDB_SIZE_MASK
- ISCSI_WQE_CDB_SIZE_SHIFT
- ISCSI_WQE_CONT_LEN_MASK
- ISCSI_WQE_CONT_LEN_SHIFT
- ISCSI_WQE_NUM_SGES_MASK
- ISCSI_WQE_NUM_SGES_SHIFT
- ISCSI_WQE_NUM_SGES_SLOWIO
- ISCSI_WQE_RESPONSE_MASK
- ISCSI_WQE_RESPONSE_SHIFT
- ISCSI_WQE_SET_PTU_INVALIDATE
- ISCSI_WQE_TYPE_FIRST_R2T_CONT
- ISCSI_WQE_TYPE_LOGIN
- ISCSI_WQE_TYPE_MIDDLE_PATH
- ISCSI_WQE_TYPE_NONFIRST_R2T_CONT
- ISCSI_WQE_TYPE_NORMAL
- ISCSI_WQE_TYPE_RESPONSE
- ISCSI_WQE_TYPE_TASK_CLEANUP
- ISCSI_WQE_WQE_TYPE_MASK
- ISCSI_WQE_WQE_TYPE_SHIFT
- ISCSI_XHQE_FINAL_MASK
- ISCSI_XHQE_FINAL_SHIFT
- ISCSI_XHQE_NUM_SGES_MASK
- ISCSI_XHQE_NUM_SGES_SHIFT
- ISCSI_XHQE_RESERVED0_MASK
- ISCSI_XHQE_RESERVED0_SHIFT
- ISCSI_XHQE_STATUS_BIT_MASK
- ISCSI_XHQE_STATUS_BIT_SHIFT
- ISC_BAY_CFG_BGBG
- ISC_BAY_CFG_GBGB
- ISC_BAY_CFG_GRGR
- ISC_BAY_CFG_RGRG
- ISC_CBC_BRIGHT
- ISC_CBC_BRIGHT_MASK
- ISC_CBC_CFG
- ISC_CBC_CONTRAST
- ISC_CBC_CONTRAST_MASK
- ISC_CBC_CTRL
- ISC_CC_BB_OB
- ISC_CC_BR_BG
- ISC_CC_CTRL
- ISC_CC_GB_OG
- ISC_CC_GR_GG
- ISC_CC_RB_OR
- ISC_CC_RR_RG
- ISC_CFA_CFG
- ISC_CFA_CFG_EITPOL
- ISC_CFA_CTRL
- ISC_CLK
- ISC_CLKCFG
- ISC_CLKCFG_DIV_MASK
- ISC_CLKCFG_DIV_SHIFT
- ISC_CLKCFG_SEL_MASK
- ISC_CLKCFG_SEL_SHIFT
- ISC_CLKDIS
- ISC_CLKEN
- ISC_CLKSR
- ISC_CLKSR_SIP
- ISC_CLK_MAX_DIV
- ISC_CSC_CBB_OCB
- ISC_CSC_CBR_CBG
- ISC_CSC_CRB_OCR
- ISC_CSC_CRR_CRG
- ISC_CSC_CTRL
- ISC_CSC_YB_OY
- ISC_CSC_YR_YG
- ISC_CTRLDIS
- ISC_CTRLEN
- ISC_CTRLSR
- ISC_CTRL_CAPTURE
- ISC_CTRL_HISCLR
- ISC_CTRL_HISREQ
- ISC_CTRL_UPPRO
- ISC_DAD0
- ISC_DAD1
- ISC_DAD2
- ISC_DCFG
- ISC_DCFG_CMBSIZE_BEATS16
- ISC_DCFG_CMBSIZE_BEATS4
- ISC_DCFG_CMBSIZE_BEATS8
- ISC_DCFG_CMBSIZE_MASK
- ISC_DCFG_CMBSIZE_SINGLE
- ISC_DCFG_IMODE_MASK
- ISC_DCFG_IMODE_PACKED16
- ISC_DCFG_IMODE_PACKED32
- ISC_DCFG_IMODE_PACKED8
- ISC_DCFG_IMODE_YC420P
- ISC_DCFG_IMODE_YC420SP
- ISC_DCFG_IMODE_YC422P
- ISC_DCFG_IMODE_YC422SP
- ISC_DCFG_YMBSIZE_BEATS16
- ISC_DCFG_YMBSIZE_BEATS4
- ISC_DCFG_YMBSIZE_BEATS8
- ISC_DCFG_YMBSIZE_MASK
- ISC_DCFG_YMBSIZE_SINGLE
- ISC_DCTRL
- ISC_DCTRL_DVIEW_MASK
- ISC_DCTRL_DVIEW_PACKED
- ISC_DCTRL_DVIEW_PLANAR
- ISC_DCTRL_DVIEW_SEMIPLANAR
- ISC_DCTRL_IE_IS
- ISC_DNDA
- ISC_ENABLE
- ISC_ERASE
- ISC_GAM_BENTRY
- ISC_GAM_CTRL
- ISC_GAM_GENTRY
- ISC_GAM_RENTRY
- ISC_HIS_CFG
- ISC_HIS_CFG_BAYSEL_SHIFT
- ISC_HIS_CFG_MODE_B
- ISC_HIS_CFG_MODE_GB
- ISC_HIS_CFG_MODE_GR
- ISC_HIS_CFG_MODE_R
- ISC_HIS_CFG_MODE_RAW
- ISC_HIS_CFG_MODE_Y
- ISC_HIS_CFG_MODE_YCCIR656
- ISC_HIS_CFG_RAR
- ISC_HIS_CTRL
- ISC_HIS_CTRL_DIS
- ISC_HIS_CTRL_EN
- ISC_HIS_ENTRY
- ISC_INTDIS
- ISC_INTEN
- ISC_INTMASK
- ISC_INTSR
- ISC_INT_DDONE
- ISC_INT_HISDONE
- ISC_ISPCK
- ISC_IS_FORMAT_RAW
- ISC_MAX_SUPPORT_HEIGHT
- ISC_MAX_SUPPORT_WIDTH
- ISC_MCK
- ISC_PFE_CFG0
- ISC_PFE_CFG0_BPS_EIGHT
- ISC_PFE_CFG0_BPS_MASK
- ISC_PFE_CFG0_CCIR656
- ISC_PFE_CFG0_CCIR_CRC
- ISC_PFE_CFG0_COLEN
- ISC_PFE_CFG0_HPOL_LOW
- ISC_PFE_CFG0_MODE_MASK
- ISC_PFE_CFG0_MODE_PROGRESSIVE
- ISC_PFE_CFG0_PPOL_LOW
- ISC_PFE_CFG0_ROWEN
- ISC_PFE_CFG0_VPOL_LOW
- ISC_PFE_CFG1
- ISC_PFE_CFG1_COLMAX
- ISC_PFE_CFG1_COLMAX_MASK
- ISC_PFE_CFG1_COLMIN
- ISC_PFE_CFG1_COLMIN_MASK
- ISC_PFE_CFG2
- ISC_PFE_CFG2_ROWMAX
- ISC_PFE_CFG2_ROWMAX_MASK
- ISC_PFE_CFG2_ROWMIN
- ISC_PFE_CFG2_ROWMIN_MASK
- ISC_PFG_CFG0_BPS_ELEVEN
- ISC_PFG_CFG0_BPS_NINE
- ISC_PFG_CFG0_BPS_TEN
- ISC_PFG_CFG0_BPS_TWELVE
- ISC_PIPE_LINE_NODE_NUM
- ISC_PROGRAMDONE
- ISC_RLP_CFG
- ISC_RLP_CFG_MODE_ARGB32
- ISC_RLP_CFG_MODE_ARGB444
- ISC_RLP_CFG_MODE_ARGB555
- ISC_RLP_CFG_MODE_DAT10
- ISC_RLP_CFG_MODE_DAT11
- ISC_RLP_CFG_MODE_DAT12
- ISC_RLP_CFG_MODE_DAT8
- ISC_RLP_CFG_MODE_DAT9
- ISC_RLP_CFG_MODE_DATY10
- ISC_RLP_CFG_MODE_DATY8
- ISC_RLP_CFG_MODE_MASK
- ISC_RLP_CFG_MODE_RGB565
- ISC_RLP_CFG_MODE_YYCC
- ISC_RLP_CFG_MODE_YYCC_LIMITED
- ISC_SUB420_CTRL
- ISC_SUB422_CTRL
- ISC_WB_AUTO
- ISC_WB_CFG
- ISC_WB_CTRL
- ISC_WB_G_BGB
- ISC_WB_G_RGR
- ISC_WB_NONE
- ISC_WB_ONETIME
- ISC_WB_O_BGB
- ISC_WB_O_RGR
- ISC_WB_O_ZERO_VAL
- ISD200_DEFAULT_TIMEOUT
- ISD200_ENUM_BSY_TIMEOUT
- ISD200_ENUM_DETECT_TIMEOUT
- ISD200_ERROR
- ISD200_GOOD
- ISD200_TRANSPORT_ERROR
- ISD200_TRANSPORT_FAILED
- ISD200_TRANSPORT_GOOD
- ISDIRTY
- ISDN_P_BASE
- ISDN_P_B_HDLC
- ISDN_P_B_L2DSP
- ISDN_P_B_L2DSPHDLC
- ISDN_P_B_L2DTMF
- ISDN_P_B_MASK
- ISDN_P_B_MODEM_ASYNC
- ISDN_P_B_RAW
- ISDN_P_B_START
- ISDN_P_B_T30_FAX
- ISDN_P_B_X75SLP
- ISDN_P_LAPD_NT
- ISDN_P_LAPD_TE
- ISDN_P_NONE
- ISDN_P_NT_E1
- ISDN_P_NT_S0
- ISDN_P_NT_UP0
- ISDN_P_TE_E1
- ISDN_P_TE_S0
- ISDN_P_TE_UP0
- ISEL
- ISENABLED_40MHZ_INTOLERANT
- ISENSE_CLK_SRC
- ISERT_MAX_CONN
- ISERT_MAX_CQ
- ISERT_MAX_RX_MISC_PDUS
- ISERT_MAX_TX_MISC_PDUS
- ISERT_MIN_POSTED_RX
- ISERT_QP_MAX_RECV_DTOS
- ISERT_QP_MAX_REQ_DTOS
- ISERT_SEND_W_INV_NOT_USED
- ISERT_ZBVA_NOT_USED
- ISER_CONN_BOUND
- ISER_CONN_DOWN
- ISER_CONN_FULL_FEATURE
- ISER_CONN_INIT
- ISER_CONN_PENDING
- ISER_CONN_STATES_NUM
- ISER_CONN_TERMINATING
- ISER_CONN_UP
- ISER_DEF_CMD_PER_LUN
- ISER_DEF_MAX_SECTORS
- ISER_DEF_XMIT_CMDS_DEFAULT
- ISER_DEF_XMIT_CMDS_MAX
- ISER_DIRS_NUM
- ISER_DIR_IN
- ISER_DIR_OUT
- ISER_GET_MAX_XMIT_CMDS
- ISER_HEADERS_LEN
- ISER_HELLO
- ISER_HELLORPLY
- ISER_INFLIGHT_DATAOUTS
- ISER_MAX_CQ_LEN
- ISER_MAX_REG_WR_PER_CMD
- ISER_MAX_RX_CQ_LEN
- ISER_MAX_RX_LEN
- ISER_MAX_RX_MISC_PDUS
- ISER_MAX_TX_CQ_LEN
- ISER_MAX_TX_LEN
- ISER_MAX_TX_MISC_PDUS
- ISER_MIN_POSTED_RX
- ISER_OBJECT_NAME_SIZE
- ISER_QP_MAX_RECV_DTOS
- ISER_QP_MAX_REQ_DTOS
- ISER_QP_SIG_MAX_REQ_DTOS
- ISER_RECV_DATA_SEG_LEN
- ISER_RSV
- ISER_RX_LOGIN_SIZE
- ISER_RX_PAD_SIZE
- ISER_RX_PAYLOAD_SIZE
- ISER_SEND_W_INV_NOT_SUP
- ISER_SIGNAL_CMD_COUNT
- ISER_TASK_STATUS_COMPLETED
- ISER_TASK_STATUS_INIT
- ISER_TASK_STATUS_STARTED
- ISER_VER
- ISER_WSV
- ISER_ZBVA_NOT_SUP
- ISGN
- ISH
- ISHTP_CLIENTS_MAX
- ISHTP_CLIENT_DMA_ENABLED
- ISHTP_CL_CONNECTED
- ISHTP_CL_CONNECTING
- ISHTP_CL_CONNECT_TIMEOUT
- ISHTP_CL_DISCONNECTED
- ISHTP_CL_DISCONNECTING
- ISHTP_CL_INITIALIZING
- ISHTP_DEV_DISABLED
- ISHTP_DEV_ENABLED
- ISHTP_DEV_INITIALIZING
- ISHTP_DEV_INIT_CLIENTS
- ISHTP_DEV_POWER_DOWN
- ISHTP_DEV_POWER_UP
- ISHTP_DEV_RESETTING
- ISHTP_FC_MESSAGE_RESERVED_LENGTH
- ISHTP_FLOW_CONTROL_CMD
- ISHTP_HBM_CLIENT_PROPERTIES
- ISHTP_HBM_CMD_OP_MSK
- ISHTP_HBM_CMD_RES_MSK
- ISHTP_HBM_ENUM_CLIENTS
- ISHTP_HBM_HOST_CLIENT_ID
- ISHTP_HBM_IDLE
- ISHTP_HBM_START
- ISHTP_HBM_STARTED
- ISHTP_HBM_STOPPED
- ISHTP_HBM_WORKING
- ISHTP_HID__H
- ISHTP_HOST_CLIENT_ID_ANY
- ISHTP_INTEROP_TIMEOUT
- ISHTP_MAX_OPEN_HANDLE_COUNT
- ISHTP_RD_MSG_BUF_SIZE
- ISHTP_SEND_TIMEOUT
- ISHTP_SYSTEM_STATE_CLIENT_ADDR
- ISH_HID_PRODUCT
- ISH_HID_VENDOR
- ISH_HID_VERSION
- ISH_MASK
- ISH_SHIFT
- ISIBITENA
- ISICOM_1SB
- ISICOM_2SB
- ISICOM_CMAJOR
- ISICOM_CS5
- ISICOM_CS6
- ISICOM_CS7
- ISICOM_CS8
- ISICOM_CTSRTS
- ISICOM_EVPAR
- ISICOM_INITIATE_XONXOFF
- ISICOM_KILLRX
- ISICOM_KILLTX
- ISICOM_MAGIC
- ISICOM_NAME
- ISICOM_NMAJOR
- ISICOM_NOPAR
- ISICOM_ODPAR
- ISICOM_RESPOND_XONXOFF
- ISID_SIZE
- ISIENTRY
- ISIF_1BIT_SHIFT
- ISIF_1LINE
- ISIF_1STLINE
- ISIF_2BIT_SHIFT
- ISIF_2LINES
- ISIF_2NDLINE
- ISIF_3BIT_SHIFT
- ISIF_3LINES
- ISIF_3RDLINE
- ISIF_4BIT_SHIFT
- ISIF_4LINES
- ISIF_4THLINE
- ISIF_5BIT_SHIFT
- ISIF_6BIT_SHIFT
- ISIF_ALAW
- ISIF_ALAW_ENABLE
- ISIF_ALAW_GAMMA_WD_MASK
- ISIF_ALAW_GAMMA_WD_SHIFT
- ISIF_BC_MODE_COLOR_SHIFT
- ISIF_BIT_MSB_10
- ISIF_BIT_MSB_11
- ISIF_BIT_MSB_12
- ISIF_BIT_MSB_13
- ISIF_BIT_MSB_14
- ISIF_BIT_MSB_15
- ISIF_BIT_MSB_7
- ISIF_BIT_MSB_8
- ISIF_BIT_MSB_9
- ISIF_BLUE
- ISIF_BW656_ENABLE
- ISIF_CADL
- ISIF_CADL_MASK
- ISIF_CADU
- ISIF_CADU_MASK
- ISIF_CCDCFG
- ISIF_CCDCFG_EXTRG_DISABLE
- ISIF_CCDCFG_FIDMD_LATCH_VSYNC
- ISIF_CCDCFG_TRGSEL_WEN
- ISIF_CCDCFG_WENLOG_AND
- ISIF_CCDCFG_Y8POS
- ISIF_CCOLP
- ISIF_CCOLP_CP0_F0_B
- ISIF_CCOLP_CP0_F0_GB
- ISIF_CCOLP_CP0_F0_GR
- ISIF_CCOLP_CP0_F0_R
- ISIF_CCOLP_CP1_F0_B
- ISIF_CCOLP_CP1_F0_GB
- ISIF_CCOLP_CP1_F0_GR
- ISIF_CCOLP_CP1_F0_R
- ISIF_CCOLP_CP2_F0_B
- ISIF_CCOLP_CP2_F0_GB
- ISIF_CCOLP_CP2_F0_GR
- ISIF_CCOLP_CP2_F0_R
- ISIF_CCOLP_CP3_F0_B
- ISIF_CCOLP_CP3_F0_GB
- ISIF_CCOLP_CP3_F0_GR
- ISIF_CCOLP_CP3_F0_R
- ISIF_CFA_PAT_MOSAIC
- ISIF_CFA_PAT_STRIPE
- ISIF_CGAMMAWD
- ISIF_CGAMMAWD_GWDI
- ISIF_CGAMMAWD_GWDI_MASK
- ISIF_COMBINE
- ISIF_CSCM_MSB_SHIFT
- ISIF_CSC_COEF_DECIMAL_MASK
- ISIF_CSC_COEF_INTEG_MASK
- ISIF_CSC_COEF_INTEG_SHIFT
- ISIF_CSC_NUM_COEFF
- ISIF_DATAPOL_NORMAL
- ISIF_DATAPOL_SHIFT
- ISIF_DATASFT_SHIFT
- ISIF_DATA_H_OFFSET_MASK
- ISIF_DATA_PACK12
- ISIF_DATA_PACK16
- ISIF_DATA_PACK8
- ISIF_DATA_PACK_MASK
- ISIF_DATA_V_OFFSET_MASK
- ISIF_DFCMEMCTL_DFCMARST_SHIFT
- ISIF_DF_CSC_LNH_MASK
- ISIF_DF_CSC_LNV_MASK
- ISIF_DF_CSC_SLV_MASK
- ISIF_DF_CSC_SPH_MASK
- ISIF_DF_NUMLINES
- ISIF_DF_NUMPIX
- ISIF_DPCM
- ISIF_DPCM_EN_SHIFT
- ISIF_DPCM_PRED1
- ISIF_DPCM_PRED2
- ISIF_DPCM_PREDICTOR_SHIFT
- ISIF_EXWEN_DISABLE
- ISIF_EXWEN_SHIFT
- ISIF_FID_POL_SHIFT
- ISIF_FRM_FMT_SHIFT
- ISIF_GAMMAWD_CFA_SHIFT
- ISIF_GREEN_BLUE
- ISIF_GREEN_RED
- ISIF_HD_POL_SHIFT
- ISIF_HORZ_BC_CLAMP_CALC_ENABLED
- ISIF_HORZ_BC_CLAMP_NOT_UPDATED
- ISIF_HORZ_BC_DISABLE
- ISIF_HORZ_BC_MODE_SHIFT
- ISIF_HORZ_BC_PIX_LIMIT_SHIFT
- ISIF_HORZ_BC_SZ_H_16PIXELS
- ISIF_HORZ_BC_SZ_H_2PIXELS
- ISIF_HORZ_BC_SZ_H_4PIXELS
- ISIF_HORZ_BC_SZ_H_8PIXELS
- ISIF_HORZ_BC_SZ_V_128PIXELS
- ISIF_HORZ_BC_SZ_V_256PIXELS
- ISIF_HORZ_BC_SZ_V_32PIXELS
- ISIF_HORZ_BC_SZ_V_64PIXELS
- ISIF_HORZ_BC_WIN_H_SIZE_SHIFT
- ISIF_HORZ_BC_WIN_SEL_SHIFT
- ISIF_HORZ_BC_WIN_V_SIZE_SHIFT
- ISIF_HSIZE
- ISIF_HSIZE_ADCR
- ISIF_HSIZE_FLIP_MASK
- ISIF_HSIZE_FLIP_SHIFT
- ISIF_HSIZE_HSIZE_MASK
- ISIF_INPUT_SHIFT
- ISIF_LATCH_ON_VSYNC_DISABLE
- ISIF_LATCH_ON_VSYNC_ENABLE
- ISIF_LINEAR_TAB_SIZE
- ISIF_LIN_CORRSFT_SHIFT
- ISIF_LIN_SCALE_FACT_INTEG_SHIFT
- ISIF_LNH
- ISIF_LNH_MASK
- ISIF_LNV
- ISIF_LNV_MASK
- ISIF_LPF_MASK
- ISIF_LPF_SHIFT
- ISIF_MODESET
- ISIF_MODESET_CCDMD
- ISIF_MODESET_CCDW_2BIT
- ISIF_MODESET_CCDW_MASK
- ISIF_MODESET_HDPOL
- ISIF_MODESET_INPMOD_MASK
- ISIF_MODESET_INPMOD_RAW
- ISIF_MODESET_INPMOD_YCBCR16
- ISIF_MODESET_INPMOD_YCBCR8
- ISIF_MODESET_SWEN
- ISIF_MODESET_VDPOL
- ISIF_NO_COMPRESSION
- ISIF_NO_SHIFT
- ISIF_PACK_12BIT
- ISIF_PACK_16BIT
- ISIF_PACK_8BIT
- ISIF_PG_EN
- ISIF_PG_HD_POL_SHIFT
- ISIF_PG_VD_POL_SHIFT
- ISIF_PIX_ORDER_SHIFT
- ISIF_PRINT_REGISTER
- ISIF_RAW_INPUT_MODE
- ISIF_RED
- ISIF_SEL_MOST_LEFT_WIN
- ISIF_SEL_MOST_RIGHT_WIN
- ISIF_SEL_PG_SRC
- ISIF_SPH
- ISIF_SPH_MASK
- ISIF_SPLIT
- ISIF_SYNCEN
- ISIF_SYNCEN_DWEN
- ISIF_SYNCEN_SYEN
- ISIF_SYNCEN_VDHDEN_MASK
- ISIF_SYNCEN_WEN_MASK
- ISIF_SYNCEN_WEN_SHIFT
- ISIF_VDFC_CORR_MOD_SHIFT
- ISIF_VDFC_CORR_WHOLE_LN_SHIFT
- ISIF_VDFC_EN_SHIFT
- ISIF_VDFC_HORZ_INTERPOL
- ISIF_VDFC_HORZ_INTERPOL_IF_SAT
- ISIF_VDFC_LEVEL_SHFT_SHIFT
- ISIF_VDFC_NORMAL
- ISIF_VDFC_NO_SHIFT
- ISIF_VDFC_POS_MASK
- ISIF_VDFC_SHIFT_1
- ISIF_VDFC_SHIFT_2
- ISIF_VDFC_SHIFT_3
- ISIF_VDFC_SHIFT_4
- ISIF_VDFC_TABLE_SIZE
- ISIF_VDHDOUT_INPUT
- ISIF_VDINT
- ISIF_VDINT_MASK
- ISIF_VD_POL_SHIFT
- ISIF_VERT_BC_LINE_AVE_COEF_SHIFT
- ISIF_VERT_BC_NO_UPDATE
- ISIF_VERT_BC_RST_VAL_SEL_SHIFT
- ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL
- ISIF_VERT_BC_USE_HORZ_CLAMP_VAL
- ISIF_WIN_NTSC
- ISIF_WIN_VGA
- ISIF_YCINSWP_RAW
- ISIF_YCINSWP_YCBCR
- ISIG
- ISIPHYCTRL
- ISIPHYCTRL_PHYE
- ISIPHYCTRL_PXE
- ISI_CFG1
- ISI_CFG1_CRC_SYNC
- ISI_CFG1_DISCR
- ISI_CFG1_EMB_SYNC
- ISI_CFG1_FRATE_CAPTURE_ALL
- ISI_CFG1_FRATE_DIV_2
- ISI_CFG1_FRATE_DIV_3
- ISI_CFG1_FRATE_DIV_4
- ISI_CFG1_FRATE_DIV_5
- ISI_CFG1_FRATE_DIV_6
- ISI_CFG1_FRATE_DIV_7
- ISI_CFG1_FRATE_DIV_8
- ISI_CFG1_FRATE_DIV_MASK
- ISI_CFG1_FULL_MODE
- ISI_CFG1_HSYNC_POL_ACTIVE_LOW
- ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING
- ISI_CFG1_THMASK_BEATS_16
- ISI_CFG1_THMASK_BEATS_4
- ISI_CFG1_THMASK_BEATS_8
- ISI_CFG1_VSYNC_POL_ACTIVE_LOW
- ISI_CFG2
- ISI_CFG2_COL_SPACE_RGB
- ISI_CFG2_COL_SPACE_YCbCr
- ISI_CFG2_GRAYSCALE
- ISI_CFG2_IM_HSIZE_MASK
- ISI_CFG2_IM_HSIZE_OFFSET
- ISI_CFG2_IM_VSIZE_MASK
- ISI_CFG2_IM_VSIZE_OFFSET
- ISI_CFG2_YCC_SWAP_DEFAULT
- ISI_CFG2_YCC_SWAP_MODE_1
- ISI_CFG2_YCC_SWAP_MODE_2
- ISI_CFG2_YCC_SWAP_MODE_3
- ISI_CFG2_YCC_SWAP_MODE_MASK
- ISI_CTRL
- ISI_CTRL_CDC
- ISI_CTRL_DIS
- ISI_CTRL_EN
- ISI_CTRL_SRST
- ISI_CTS
- ISI_DATAWIDTH_10
- ISI_DATAWIDTH_8
- ISI_DCD
- ISI_DMA_CHDR
- ISI_DMA_CHER
- ISI_DMA_CHSR
- ISI_DMA_CHSR_C_CH
- ISI_DMA_CHSR_P_CH
- ISI_DMA_CTRL_DONE
- ISI_DMA_CTRL_FETCH
- ISI_DMA_CTRL_IEN
- ISI_DMA_CTRL_WB
- ISI_DMA_C_ADDR
- ISI_DMA_C_CTRL
- ISI_DMA_C_DSCR
- ISI_DMA_P_ADDR
- ISI_DMA_P_CTRL
- ISI_DMA_P_DSCR
- ISI_DSR
- ISI_DTR
- ISI_EXITS
- ISI_INTDIS
- ISI_INTEN
- ISI_INTMASK
- ISI_PDECF
- ISI_PDECF_DEC_FACTOR_MASK
- ISI_PDECF_NO_SAMPLING
- ISI_PSIZE
- ISI_PSIZE_PREV_HSIZE_MASK
- ISI_PSIZE_PREV_HSIZE_OFFSET
- ISI_PSIZE_PREV_VSIZE_MASK
- ISI_PSIZE_PREV_VSIZE_OFFSET
- ISI_R2Y_SET0
- ISI_R2Y_SET1
- ISI_R2Y_SET2
- ISI_RI
- ISI_RTS
- ISI_SR_CRC_ERR
- ISI_SR_CXFR_DONE
- ISI_SR_C_OVR
- ISI_SR_FR_OVR
- ISI_SR_PXFR_DONE
- ISI_SR_P_OVR
- ISI_SR_SIP
- ISI_SR_VSYNC
- ISI_STATUS
- ISI_TXOK
- ISI_Y2R_SET0
- ISI_Y2R_SET1
- ISKU_BIN_ATTR_R
- ISKU_BIN_ATTR_RW
- ISKU_BIN_ATTR_W
- ISKU_COMMAND_15
- ISKU_COMMAND_ACTUAL_PROFILE
- ISKU_COMMAND_CONTROL
- ISKU_COMMAND_FIRMWARE_WRITE
- ISKU_COMMAND_FIRMWARE_WRITE_CONTROL
- ISKU_COMMAND_INFO
- ISKU_COMMAND_KEYS_CAPSLOCK
- ISKU_COMMAND_KEYS_EASYZONE
- ISKU_COMMAND_KEYS_FUNCTION
- ISKU_COMMAND_KEYS_MACRO
- ISKU_COMMAND_KEYS_MEDIA
- ISKU_COMMAND_KEYS_THUMBSTER
- ISKU_COMMAND_KEY_MASK
- ISKU_COMMAND_LAST_SET
- ISKU_COMMAND_LIGHT
- ISKU_COMMAND_MACRO
- ISKU_COMMAND_RESET
- ISKU_COMMAND_TALK
- ISKU_COMMAND_TALKFX
- ISKU_PROFILE_NUM
- ISKU_REPORT_BUTTON_EVENT_PROFILE
- ISKU_REPORT_NUMBER_BUTTON
- ISKU_SIZE_CONTROL
- ISKU_SIZE_INFO
- ISKU_SIZE_KEYS_CAPSLOCK
- ISKU_SIZE_KEYS_EASYZONE
- ISKU_SIZE_KEYS_FUNCTION
- ISKU_SIZE_KEYS_MACRO
- ISKU_SIZE_KEYS_MEDIA
- ISKU_SIZE_KEYS_THUMBSTER
- ISKU_SIZE_KEY_MASK
- ISKU_SIZE_LAST_SET
- ISKU_SIZE_LIGHT
- ISKU_SIZE_MACRO
- ISKU_SIZE_RESET
- ISKU_SIZE_TALK
- ISKU_SIZE_TALKFX
- ISKU_SYSFS_R
- ISKU_SYSFS_RW
- ISKU_SYSFS_W
- ISKU_USB_INTERFACE_PROTOCOL
- ISL12022_HR_MIL
- ISL12022_INT_WRTC
- ISL12022_REG_DT
- ISL12022_REG_DW
- ISL12022_REG_HR
- ISL12022_REG_INT
- ISL12022_REG_MN
- ISL12022_REG_MO
- ISL12022_REG_SC
- ISL12022_REG_SR
- ISL12022_REG_YR
- ISL12022_SR_LBAT75
- ISL12022_SR_LBAT85
- ISL12026_EEPROM_ADDR
- ISL12026_NVMEM_WRITE_TIME
- ISL12026_PAGESIZE
- ISL12026_REG_HR
- ISL12026_REG_HR_MIL
- ISL12026_REG_PWR
- ISL12026_REG_PWR_BSW
- ISL12026_REG_PWR_SBIB
- ISL12026_REG_SC
- ISL12026_REG_SR
- ISL12026_REG_SR_MBZ
- ISL12026_REG_SR_OSCF
- ISL12026_REG_SR_RTCF
- ISL12026_REG_SR_RWEL
- ISL12026_REG_SR_WEL
- ISL1208_ALARM_SECTION_LEN
- ISL1208_REG_ATR
- ISL1208_REG_DT
- ISL1208_REG_DTA
- ISL1208_REG_DTR
- ISL1208_REG_DW
- ISL1208_REG_DWA
- ISL1208_REG_HR
- ISL1208_REG_HRA
- ISL1208_REG_HR_MIL
- ISL1208_REG_HR_PM
- ISL1208_REG_INT
- ISL1208_REG_INT_ALME
- ISL1208_REG_INT_IM
- ISL1208_REG_MN
- ISL1208_REG_MNA
- ISL1208_REG_MO
- ISL1208_REG_MOA
- ISL1208_REG_SC
- ISL1208_REG_SCA
- ISL1208_REG_SR
- ISL1208_REG_SR_ALM
- ISL1208_REG_SR_ARST
- ISL1208_REG_SR_BAT
- ISL1208_REG_SR_EVT
- ISL1208_REG_SR_RTCF
- ISL1208_REG_SR_WRTC
- ISL1208_REG_SR_XTOSCB
- ISL1208_REG_USR1
- ISL1208_REG_USR2
- ISL1208_REG_YR
- ISL1208_RTC_SECTION_LEN
- ISL1208_USR_SECTION_LEN
- ISL1219_EVT_SECTION_LEN
- ISL1219_REG_DTT
- ISL1219_REG_EV
- ISL1219_REG_EV_EVEN
- ISL1219_REG_EV_EVIENB
- ISL1219_REG_HRT
- ISL1219_REG_MNT
- ISL1219_REG_MOT
- ISL1219_REG_SCT
- ISL1219_REG_YRT
- ISL29003_ADC_ENABLED
- ISL29003_ADC_PD
- ISL29003_DRV_NAME
- ISL29003_INT_FLG
- ISL29003_INT_PERSISTS_MASK
- ISL29003_INT_PERSISTS_SHIFT
- ISL29003_MODE_MASK
- ISL29003_MODE_SHIFT
- ISL29003_NUM_CACHABLE_REGS
- ISL29003_PM_OPS
- ISL29003_RANGE_MASK
- ISL29003_RANGE_SHIFT
- ISL29003_REG_COMMAND
- ISL29003_REG_CONTROL
- ISL29003_REG_IRQ_THRESH_HI
- ISL29003_REG_IRQ_THRESH_LO
- ISL29003_REG_LSB_SENSOR
- ISL29003_REG_LSB_TIMER
- ISL29003_REG_MSB_SENSOR
- ISL29003_REG_MSB_TIMER
- ISL29003_RES_MASK
- ISL29003_RES_SHIFT
- ISL29003_TIMING_INT
- ISL29018_CMD1_OPMODE_ALS_ONCE
- ISL29018_CMD1_OPMODE_IR_ONCE
- ISL29018_CMD1_OPMODE_MASK
- ISL29018_CMD1_OPMODE_POWER_DOWN
- ISL29018_CMD1_OPMODE_PROX_ONCE
- ISL29018_CMD1_OPMODE_SHIFT
- ISL29018_CMD2_RANGE_MASK
- ISL29018_CMD2_RANGE_SHIFT
- ISL29018_CMD2_RESOLUTION_MASK
- ISL29018_CMD2_RESOLUTION_SHIFT
- ISL29018_CMD2_SCHEME_MASK
- ISL29018_CMD2_SCHEME_SHIFT
- ISL29018_CONV_TIME_MS
- ISL29018_DEV_ATTR
- ISL29018_INT_TIME_12
- ISL29018_INT_TIME_16
- ISL29018_INT_TIME_4
- ISL29018_INT_TIME_8
- ISL29018_IR_CHANNEL
- ISL29018_LIGHT_CHANNEL
- ISL29018_PM_OPS
- ISL29018_PROXIMITY_CHANNEL
- ISL29018_REG_ADD_COMMAND1
- ISL29018_REG_ADD_COMMAND2
- ISL29018_REG_ADD_DATA_LSB
- ISL29018_REG_ADD_DATA_MSB
- ISL29018_REG_TEST
- ISL29018_TEST_MASK
- ISL29018_TEST_SHIFT
- ISL29020_PM_OPS
- ISL29028_CONF_ALS_DIS
- ISL29028_CONF_ALS_EN
- ISL29028_CONF_ALS_EN_MASK
- ISL29028_CONF_ALS_IR_MODE_ALS
- ISL29028_CONF_ALS_IR_MODE_IR
- ISL29028_CONF_ALS_IR_MODE_MASK
- ISL29028_CONF_ALS_RANGE_HIGH_LUX
- ISL29028_CONF_ALS_RANGE_LOW_LUX
- ISL29028_CONF_ALS_RANGE_MASK
- ISL29028_CONF_PROX_EN
- ISL29028_CONF_PROX_EN_MASK
- ISL29028_CONF_PROX_SLP_MASK
- ISL29028_CONF_PROX_SLP_SH
- ISL29028_CONST_ATTR
- ISL29028_CONV_TIME_MS
- ISL29028_MODE_ALS
- ISL29028_MODE_IR
- ISL29028_MODE_NONE
- ISL29028_NUM_REGS
- ISL29028_POWER_OFF_DELAY_MS
- ISL29028_REG_ALSIR_L
- ISL29028_REG_ALSIR_U
- ISL29028_REG_CONFIGURE
- ISL29028_REG_INTERRUPT
- ISL29028_REG_PROX_DATA
- ISL29028_REG_TEST1_MODE
- ISL29028_REG_TEST2_MODE
- ISL29035_BOUT_MASK
- ISL29035_BOUT_SHIFT
- ISL29035_DEVICE_ID
- ISL29035_DEVICE_ID_MASK
- ISL29035_DEVICE_ID_SHIFT
- ISL29035_REG_DEVICE_ID
- ISL29125_BLUE_DATA
- ISL29125_CHANNEL
- ISL29125_CONF1
- ISL29125_CONF2
- ISL29125_CONF3
- ISL29125_DEVICE_ID
- ISL29125_DRV_NAME
- ISL29125_GREEN_DATA
- ISL29125_ID
- ISL29125_MODE_B
- ISL29125_MODE_G
- ISL29125_MODE_MASK
- ISL29125_MODE_PD
- ISL29125_MODE_R
- ISL29125_MODE_RANGE
- ISL29125_MODE_RGB
- ISL29125_RED_DATA
- ISL29125_SENSING_RANGE_0
- ISL29125_SENSING_RANGE_1
- ISL29125_STATUS
- ISL29125_STATUS_CONV
- ISL29501_AMBIANT_COEFF_A
- ISL29501_AMBIANT_COEFF_B
- ISL29501_AMBIENT_LIGHT
- ISL29501_COMMAND_REGISTER
- ISL29501_CROSSTALK_GAIN_LSB
- ISL29501_CROSSTALK_GAIN_MSB
- ISL29501_CROSSTALK_I_EXPONENT
- ISL29501_CROSSTALK_I_LSB
- ISL29501_CROSSTALK_I_MSB
- ISL29501_CROSSTALK_Q_EXPONENT
- ISL29501_CROSSTALK_Q_LSB
- ISL29501_CROSSTALK_Q_MSB
- ISL29501_CURRENT_SCALE_AVAILABLE
- ISL29501_DEVICE_ID
- ISL29501_DIE_TEMPERATURE
- ISL29501_DISTANCE_LSB_DATA
- ISL29501_DISTANCE_MSB_DATA
- ISL29501_DISTANCE_SCAN_INDEX
- ISL29501_DRIVER_RANGE
- ISL29501_EMITTER_DAC
- ISL29501_EMUL_SAMPLE_START_PIN
- ISL29501_GAIN_LSB
- ISL29501_GAIN_MSB
- ISL29501_ID
- ISL29501_INTEGRATION_PERIOD
- ISL29501_INT_TIME_AVAILABLE
- ISL29501_I_RAW_EXPONENT
- ISL29501_I_RAW_LSB
- ISL29501_I_RAW_MSB
- ISL29501_MAGNITUDE_EXPONENT
- ISL29501_MAGNITUDE_LSB
- ISL29501_MAGNITUDE_MSB
- ISL29501_MAGNITUDE_REF_EXP
- ISL29501_MAGNITUDE_REF_LSB
- ISL29501_MAGNITUDE_REF_MSB
- ISL29501_MAX_EXP_VAL
- ISL29501_PHASE_EXPONENT
- ISL29501_PHASE_LSB
- ISL29501_PHASE_MSB
- ISL29501_PHASE_OFFSET_LSB
- ISL29501_PHASE_OFFSET_MSB
- ISL29501_PRECISION_LSB
- ISL29501_PRECISION_MSB
- ISL29501_Q_RAW_EXPONENT
- ISL29501_Q_RAW_LSB
- ISL29501_Q_RAW_MSB
- ISL29501_RESET_ALL_REGISTERS
- ISL29501_RESET_INT_SM
- ISL29501_SAMPLE_PERIOD
- ISL29501_TEMP_COEFF_A
- ISL29501_TEMP_COEFF_B
- ISL29501_TEMP_REFERENCE
- ISL29501_TIMESTAMP_SCAN_INDEX
- ISL3877_IMAGE_FILE
- ISL3886_IMAGE_FILE
- ISL3890_IMAGE_FILE
- ISL38XX_CARDBUS_CIS
- ISL38XX_CB_MGMT_QSIZE
- ISL38XX_CB_QCOUNT
- ISL38XX_CB_RX_DATA_HQ
- ISL38XX_CB_RX_DATA_LQ
- ISL38XX_CB_RX_MGMTQ
- ISL38XX_CB_RX_QSIZE
- ISL38XX_CB_TX_DATA_HQ
- ISL38XX_CB_TX_DATA_LQ
- ISL38XX_CB_TX_MGMTQ
- ISL38XX_CB_TX_QSIZE
- ISL38XX_CTRL_BLK_BASE_REG
- ISL38XX_CTRL_STAT_CLKRUN
- ISL38XX_CTRL_STAT_HOST_OVERRIDE
- ISL38XX_CTRL_STAT_RAMBOOT
- ISL38XX_CTRL_STAT_REG
- ISL38XX_CTRL_STAT_RESET
- ISL38XX_CTRL_STAT_SLEEPMODE
- ISL38XX_CTRL_STAT_STARTHALTED
- ISL38XX_DEV_FIRMWARE_ADDR
- ISL38XX_DEV_FIRMWARE_ADDRES
- ISL38XX_DEV_INT_ABORT
- ISL38XX_DEV_INT_DATA
- ISL38XX_DEV_INT_MGMT
- ISL38XX_DEV_INT_PCIUART_CTS
- ISL38XX_DEV_INT_PCIUART_DR
- ISL38XX_DEV_INT_REG
- ISL38XX_DEV_INT_RESET
- ISL38XX_DEV_INT_SLEEP
- ISL38XX_DEV_INT_UPDATE
- ISL38XX_DEV_INT_WAKEUP
- ISL38XX_DIRECT_MEM_WIN
- ISL38XX_DIR_MEM_BASE_REG
- ISL38XX_DMA_MASTER_CONTROL_TRIGGER
- ISL38XX_DMA_STATUS_DONE
- ISL38XX_DMA_STATUS_READY
- ISL38XX_GEN_PURP_COM_REG_1
- ISL38XX_GEN_PURP_COM_REG_2
- ISL38XX_HARDWARE_REG
- ISL38XX_INT_ACK_REG
- ISL38XX_INT_EN_REG
- ISL38XX_INT_IDENT_INIT
- ISL38XX_INT_IDENT_PCIUART_CTS
- ISL38XX_INT_IDENT_PCIUART_DR
- ISL38XX_INT_IDENT_REG
- ISL38XX_INT_IDENT_SLEEP
- ISL38XX_INT_IDENT_UPDATE
- ISL38XX_INT_IDENT_WAKEUP
- ISL38XX_INT_SOURCES
- ISL38XX_MAX_WAIT_CYCLES
- ISL38XX_MAX_WDS_LINKS
- ISL38XX_MEMORY_WINDOW_SIZE
- ISL38XX_MIN_QTHRESHOLD
- ISL38XX_PCI_MEM_SIZE
- ISL38XX_PCI_POSTING_FLUSH
- ISL38XX_PSM_ACTIVE_STATE
- ISL38XX_PSM_POWERSAVE_STATE
- ISL38XX_RESET_DELAY
- ISL38XX_WAIT_CYCLE
- ISL38XX_WRITEIO_DELAY
- ISL6271A_VOLTAGE_MAX
- ISL6271A_VOLTAGE_MIN
- ISL6271A_VOLTAGE_STEP
- ISL6405_DCL
- ISL6405_EN1
- ISL6405_EN2
- ISL6405_ENT1
- ISL6405_ENT2
- ISL6405_ISEL1
- ISL6405_ISEL2
- ISL6405_LLC1
- ISL6405_LLC2
- ISL6405_OLF1
- ISL6405_OLF2
- ISL6405_OTF
- ISL6405_SR
- ISL6405_VSEL1
- ISL6405_VSEL2
- ISL6421_DCL
- ISL6421_EN1
- ISL6421_ENT1
- ISL6421_ISEL1
- ISL6421_LLC1
- ISL6421_OLF1
- ISL6421_VSEL1
- ISL68137_VOUT_AVS
- ISL9305_DCD1
- ISL9305_DCD1OUT
- ISL9305_DCD1SR_MASK
- ISL9305_DCD1_BLD
- ISL9305_DCD1_EN
- ISL9305_DCD1_MODE
- ISL9305_DCD1_ULTRA
- ISL9305_DCD2
- ISL9305_DCD2OUT
- ISL9305_DCD2SR_MASK
- ISL9305_DCD2_BLD
- ISL9305_DCD2_EN
- ISL9305_DCD2_MODE
- ISL9305_DCD2_ULTRA
- ISL9305_DCDPOR_MASK
- ISL9305_DCD_PARAMETER
- ISL9305_DCD_PHASE
- ISL9305_DCD_SRCTL
- ISL9305_I2C_EN
- ISL9305_LDO1
- ISL9305_LDO1OUT
- ISL9305_LDO1_EN
- ISL9305_LDO2
- ISL9305_LDO2OUT
- ISL9305_LDO2_EN
- ISL9305_MAX_REG
- ISL9305_MAX_REGULATOR
- ISL9305_SYSTEM_PARAMETER
- ISLCNPHY
- ISLOWER
- ISLPCI_TX_TIMEOUT
- ISL_ALS_I2C_ADDR
- ISL_LAST_ID
- ISMT_DESC_ADDR_RW
- ISMT_DESC_BLK
- ISMT_DESC_CLTO
- ISMT_DESC_COL
- ISMT_DESC_CRC
- ISMT_DESC_CWRL
- ISMT_DESC_DLTO
- ISMT_DESC_ENTRIES
- ISMT_DESC_FAIR
- ISMT_DESC_I2C
- ISMT_DESC_INT
- ISMT_DESC_LPR
- ISMT_DESC_NAK
- ISMT_DESC_PEC
- ISMT_DESC_SCS
- ISMT_DESC_SOE
- ISMT_GCTRL_KILL
- ISMT_GCTRL_SRST
- ISMT_GCTRL_TRST
- ISMT_GR_ERRAERMSK
- ISMT_GR_ERRINFO
- ISMT_GR_ERRINTMSK
- ISMT_GR_ERRSTS
- ISMT_GR_GCTRL
- ISMT_GR_SMTICL
- ISMT_MAX_RETRIES
- ISMT_MCTRL_FMHP
- ISMT_MCTRL_MEIE
- ISMT_MCTRL_SS
- ISMT_MDS_MASK
- ISMT_MSICTL_MSIE
- ISMT_MSTR_MCTRL
- ISMT_MSTR_MDBA
- ISMT_MSTR_MDS
- ISMT_MSTR_MSTS
- ISMT_MSTR_RPOLICY
- ISMT_MSTS_HMTP
- ISMT_MSTS_IP
- ISMT_MSTS_MEIS
- ISMT_MSTS_MIS
- ISMT_SPGT
- ISMT_SPGT_SPD_100K
- ISMT_SPGT_SPD_1M
- ISMT_SPGT_SPD_400K
- ISMT_SPGT_SPD_80K
- ISMT_SPGT_SPD_MASK
- ISM_ADD_VLAN_ID
- ISM_CREATE_REQ
- ISM_DEL_VLAN_ID
- ISM_DMB_BIT_OFFSET
- ISM_DMB_WORD_OFFSET
- ISM_ERROR
- ISM_EVENT_CODE_SHUTDOWN
- ISM_EVENT_CODE_TESTLINK
- ISM_EVENT_DMB
- ISM_EVENT_GID
- ISM_EVENT_REQUEST
- ISM_EVENT_REQUEST_IR
- ISM_EVENT_RESPONSE
- ISM_EVENT_SWR
- ISM_IOP_BASE_IIFX
- ISM_IOP_BASE_QUADRA
- ISM_MASK
- ISM_NR_DMBS
- ISM_QUERY_INFO
- ISM_QUERY_RGID
- ISM_READ_GID
- ISM_REG_DMB
- ISM_REG_IEQ
- ISM_REG_SBA
- ISM_RESET_VLAN
- ISM_SET_VLAN
- ISM_SHIFT
- ISM_SIGNAL_IEQ
- ISM_UNREG_DMB
- ISM_UNREG_IEQ
- ISM_UNREG_SBA
- ISNPHY
- ISNS_DEFAULT_SERVER_CONN_ID
- ISNS_DEREG_TOV
- ISNS_DISABLE
- ISNS_ENABLE
- ISNS_EVENT_CONNECTION_FAILED
- ISNS_EVENT_CONNECTION_OPENED
- ISNS_EVENT_DATA_RECEIVED
- ISNT
- ISNUM
- ISO13522_STREAM
- ISO14443A_PROTOCOL_CODE
- ISO14443A_RATS_REQ
- ISO14443B_PROTOCOL_CODE
- ISO15693_CMD_GET_MULTIPLE_BLOCK_SECURITY_STATUS
- ISO15693_CMD_GET_SYSTEM_INFO
- ISO15693_CMD_INVENTORY
- ISO15693_CMD_LOCK_AFI
- ISO15693_CMD_LOCK_BLOCK
- ISO15693_CMD_LOCK_DSFID
- ISO15693_CMD_READ_MULTIPLE_BLOCK
- ISO15693_CMD_READ_SINGLE_BLOCK
- ISO15693_CMD_RESET_TO_READY
- ISO15693_CMD_SELECT
- ISO15693_CMD_WRITE_AFI
- ISO15693_CMD_WRITE_DSFID
- ISO15693_CMD_WRITE_MULTIPLE_BLOCK
- ISO15693_CMD_WRITE_SINGLE_BLOCK
- ISO15693_PROTOCOL_CODE
- ISO15693_REQ_FLAG_ADDRESS
- ISO15693_REQ_FLAG_AFI
- ISO15693_REQ_FLAG_DATA_RATE
- ISO15693_REQ_FLAG_INVENTORY
- ISO15693_REQ_FLAG_NB_SLOTS
- ISO15693_REQ_FLAG_OPTION
- ISO15693_REQ_FLAG_PROTOCOL_EXT
- ISO15693_REQ_FLAG_SELECT
- ISO15693_REQ_FLAG_SPEED_MASK
- ISO15693_REQ_FLAG_SUB_CARRIER
- ISOCHRONOUS_DELAY
- ISOC_COMM_CONTROL_MASK
- ISOC_COMM_CONTROL_OFFSET
- ISOC_DBR_FACTOR
- ISOC_INTERFACE_ALTERNATIVE
- ISOC_IN_EP
- ISOC_MODE_COMPRESS
- ISOC_MODE_YUV420
- ISOC_MODE_YUV422
- ISOC_OUT_EP
- ISOC_PACKETS_B
- ISOC_PACKETS_D
- ISOC_URB_GIVEBACK_ASAP
- ISODCL
- ISODESC_MAX
- ISOFS_BLOCK_BITS
- ISOFS_BLOCK_SIZE
- ISOFS_BUFFER_BITS
- ISOFS_BUFFER_SIZE
- ISOFS_I
- ISOFS_INVALID_MODE
- ISOFS_SB
- ISOFS_SUPER_MAGIC
- ISOLATE
- ISOLATED_BITS
- ISOLATE_ABORT
- ISOLATE_ASYNC_MIGRATE
- ISOLATE_NG
- ISOLATE_NONE
- ISOLATE_OK
- ISOLATE_SUCCESS
- ISOLATE_UNEVICTABLE
- ISOLATE_UNMAPPED
- ISOLATION_MODE_DROP
- ISOLATION_MODE_FWD
- ISOLATION_MODE_NONE
- ISOLATION_STATE
- ISOL_CONFIG_REG
- ISO_BUFFER_SIZE
- ISO_BUF_COUNT
- ISO_BUF_FILL
- ISO_DATA_LENGTH_SHIFT
- ISO_DIOE
- ISO_DIOP
- ISO_DIOR
- ISO_EB2CORE
- ISO_EN
- ISO_ERRS
- ISO_FIFO_SIZE
- ISO_FRAMES_PER_DESC
- ISO_FRAME_SIZE
- ISO_HEADER_SIZE
- ISO_IP2MAC
- ISO_MAX_FRAME_SIZE
- ISO_MAX_INTERVAL
- ISO_MD2PP
- ISO_PA2PCIE
- ISO_PD2CORE
- ISO_PFAULT_DETECTED
- ISO_PFAULT_INTR_MASK
- ISO_PKT_TX
- ISO_PLL2MD
- ISO_PTD_OFFSET
- ISO_PWC_DV2RP
- ISO_PWC_RV2RP
- ISO_RES_ALLOC
- ISO_RES_ALLOC_ONCE
- ISO_RES_DEALLOC
- ISO_RES_DEALLOC_ONCE
- ISO_RES_REALLOC
- ISO_STANDARD_ID
- ISO_UA2USB
- ISO_UD2CORE
- ISO_UPDATE
- ISO_VD_END
- ISO_VD_PRIMARY
- ISO_VD_SUPPLEMENTARY
- ISP116x_ATL_BUFSIZE
- ISP116x_BUF_SIZE
- ISP116x_ITL_BUFSIZE
- ISP116x_WRITE_OFFSET
- ISP1301
- ISP1301_BCD_DEVICE
- ISP1301_I2C_INTERRUPT_FALLING
- ISP1301_I2C_INTERRUPT_LATCH
- ISP1301_I2C_INTERRUPT_RISING
- ISP1301_I2C_INTERRUPT_SOURCE
- ISP1301_I2C_MODE_CONTROL_1
- ISP1301_I2C_MODE_CONTROL_2
- ISP1301_I2C_OTG_CONTROL_1
- ISP1301_I2C_OTG_CONTROL_2
- ISP1301_I2C_REG_CLEAR_ADDR
- ISP1301_INTERRUPT_FALLING
- ISP1301_INTERRUPT_LATCH
- ISP1301_INTERRUPT_RISING
- ISP1301_INTERRUPT_SOURCE
- ISP1301_MODE_CONTROL_1
- ISP1301_MODE_CONTROL_2
- ISP1301_OTG_CONTROL_1
- ISP1301_OTG_STATUS
- ISP1301_PRODUCT_ID
- ISP1301_VENDOR_ID
- ISP1362_ATL_BLKSIZE
- ISP1362_BUF_SIZE
- ISP1362_DEBUG
- ISP1362_INTL_BLKSIZE
- ISP1362_INTL_BUFFERS
- ISP1362_INT_ATL
- ISP1362_INT_CLKRDY
- ISP1362_INT_EOT
- ISP1362_INT_INTL
- ISP1362_INT_ISTL0
- ISP1362_INT_ISTL1
- ISP1362_INT_NAME
- ISP1362_INT_OPR
- ISP1362_INT_OTG
- ISP1362_INT_SOF
- ISP1362_INT_SUSP
- ISP1362_ISTL_BUFSIZE
- ISP1362_REG
- ISP1362_REG_NO
- ISP1362_REG_WRITE_OFFSET
- ISP1704_PWR_CTRL
- ISP1704_PWR_CTRL_BVALID_FALL
- ISP1704_PWR_CTRL_BVALID_RISE
- ISP1704_PWR_CTRL_DET_COMP
- ISP1704_PWR_CTRL_DPVSRC_EN
- ISP1704_PWR_CTRL_DP_WKPU_EN
- ISP1704_PWR_CTRL_HWDETECT
- ISP1704_PWR_CTRL_SWCTRL
- ISP1704_PWR_CTRL_VDAT_DET
- ISP1760_CTRL_DATA_IN
- ISP1760_CTRL_DATA_OUT
- ISP1760_CTRL_SETUP
- ISP1760_CTRL_STATUS
- ISP1760_FLAG_ANALOG_OC
- ISP1760_FLAG_BUS_WIDTH_16
- ISP1760_FLAG_DACK_POL_HIGH
- ISP1760_FLAG_DREQ_POL_HIGH
- ISP1760_FLAG_INTR_EDGE_TRIG
- ISP1760_FLAG_INTR_POL_HIGH
- ISP1760_FLAG_ISP1761
- ISP1760_FLAG_OTG_EN
- ISP1760_VBUS_POLL_INTERVAL
- ISP4XXX_PCI_FN_1
- ISP4XXX_PCI_FN_2
- ISP5_BCR
- ISP5_CCDCMUX
- ISP5_CTRL
- ISP5_CTRL_BL_CLK_ENABLE
- ISP5_CTRL_H3A_CLK_ENABLE
- ISP5_CTRL_IPIPEIF_CLK_ENABLE
- ISP5_CTRL_IPIPE_CLK_ENABLE
- ISP5_CTRL_ISIF_CLK_ENABLE
- ISP5_CTRL_MSTANDBY
- ISP5_CTRL_MSTANDBY_WAIT
- ISP5_CTRL_PSYNC_CLK_SEL
- ISP5_CTRL_RSZ_CLK_ENABLE
- ISP5_CTRL_SYNC_ENABLE
- ISP5_CTRL_VD_PULSE_EXT
- ISP5_EVTSEL
- ISP5_INTSEL1
- ISP5_INTSEL2
- ISP5_INTSEL3
- ISP5_INTSTAT
- ISP5_INTSTAT_OSDINT
- ISP5_INTSTAT_VENCINT
- ISP5_IRQENABLE_CLR
- ISP5_IRQENABLE_SET
- ISP5_IRQSTATUS
- ISP5_IRQ_AEW_INT
- ISP5_IRQ_AF_INT
- ISP5_IRQ_H3A_INT
- ISP5_IRQ_H3A_INT_EOF
- ISP5_IRQ_IPIPEIF_IRQ
- ISP5_IRQ_IPIPE_INT_BSC
- ISP5_IRQ_IPIPE_INT_DMA
- ISP5_IRQ_IPIPE_INT_DPC_INIT
- ISP5_IRQ_IPIPE_INT_DPC_RNEW0
- ISP5_IRQ_IPIPE_INT_DPC_RNEW1
- ISP5_IRQ_IPIPE_INT_EOF
- ISP5_IRQ_IPIPE_INT_HST
- ISP5_IRQ_IPIPE_INT_LAST_PIX
- ISP5_IRQ_IPIPE_INT_REG
- ISP5_IRQ_ISIF_INT
- ISP5_IRQ_OCP_ERR
- ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR
- ISP5_IRQ_RSZ_FIFO_OVF
- ISP5_IRQ_RSZ_INT_CYC_RSZA
- ISP5_IRQ_RSZ_INT_CYC_RSZB
- ISP5_IRQ_RSZ_INT_DMA
- ISP5_IRQ_RSZ_INT_EOF0
- ISP5_IRQ_RSZ_INT_EOF1
- ISP5_IRQ_RSZ_INT_LAST_PIX
- ISP5_IRQ_RSZ_INT_REG
- ISP5_PCCR
- ISP5_PID
- ISP5_PRINT_REGISTER
- ISP5_REVISION
- ISP5_SYSCONFIG
- ISP5_SYSCONFIG_SOFTRESET
- ISP5_SYSCONFIG_STANDBYMODE_FORCE
- ISP5_SYSCONFIG_STANDBYMODE_MASK
- ISP5_SYSCONFIG_STANDBYMODE_NO
- ISP5_SYSCONFIG_STANDBYMODE_SMART
- ISP8044_PEX_DMA_BASE_ADDRESS
- ISP8044_PEX_DMA_CMD_ADDR_HIGH
- ISP8044_PEX_DMA_CMD_ADDR_LOW
- ISP8044_PEX_DMA_CMD_STS_AND_CNTRL
- ISP8044_PEX_DMA_ENGINE_INDEX
- ISP8044_PEX_DMA_MAX_WAIT
- ISP8044_PEX_DMA_NUM_OFFSET
- ISP8044_PEX_DMA_READ_SIZE
- ISPARSE
- ISPCCDC_ALAW
- ISPCCDC_ALAW_CCDTBL
- ISPCCDC_ALAW_GWDI_10_1
- ISPCCDC_ALAW_GWDI_11_2
- ISPCCDC_ALAW_GWDI_12_3
- ISPCCDC_ALAW_GWDI_9_0
- ISPCCDC_BLKCMP
- ISPCCDC_BLKCMP_B_MG_SHIFT
- ISPCCDC_BLKCMP_GB_G_SHIFT
- ISPCCDC_BLKCMP_GR_CY_SHIFT
- ISPCCDC_BLKCMP_R_YE_SHIFT
- ISPCCDC_CFG
- ISPCCDC_CFG_BSWD
- ISPCCDC_CFG_BW656
- ISPCCDC_CFG_FIDMD_SHIFT
- ISPCCDC_CFG_MSBINVI
- ISPCCDC_CFG_VDLC
- ISPCCDC_CFG_WENLOG
- ISPCCDC_CFG_WENLOG_AND
- ISPCCDC_CFG_WENLOG_OR
- ISPCCDC_CFG_Y8POS
- ISPCCDC_CLAMP
- ISPCCDC_CLAMP_CLAMPEN
- ISPCCDC_CLAMP_OBGAIN_SHIFT
- ISPCCDC_CLAMP_OBSLEN_SHIFT
- ISPCCDC_CLAMP_OBSLN_SHIFT
- ISPCCDC_CLAMP_OBST_SHIFT
- ISPCCDC_COLPTN
- ISPCCDC_COLPTN_B_Mg
- ISPCCDC_COLPTN_CP0PLC0_SHIFT
- ISPCCDC_COLPTN_CP0PLC1_SHIFT
- ISPCCDC_COLPTN_CP0PLC2_SHIFT
- ISPCCDC_COLPTN_CP0PLC3_SHIFT
- ISPCCDC_COLPTN_CP1PLC0_SHIFT
- ISPCCDC_COLPTN_CP1PLC1_SHIFT
- ISPCCDC_COLPTN_CP1PLC2_SHIFT
- ISPCCDC_COLPTN_CP1PLC3_SHIFT
- ISPCCDC_COLPTN_CP2PLC0_SHIFT
- ISPCCDC_COLPTN_CP2PLC1_SHIFT
- ISPCCDC_COLPTN_CP2PLC2_SHIFT
- ISPCCDC_COLPTN_CP2PLC3_SHIFT
- ISPCCDC_COLPTN_CP3PLC0_SHIFT
- ISPCCDC_COLPTN_CP3PLC1_SHIFT
- ISPCCDC_COLPTN_CP3PLC2_SHIFT
- ISPCCDC_COLPTN_CP3PLC3_SHIFT
- ISPCCDC_COLPTN_Gb_G
- ISPCCDC_COLPTN_Gr_Cy
- ISPCCDC_COLPTN_R_Ye
- ISPCCDC_CULLING
- ISPCCDC_CULLING_CULHEVN_SHIFT
- ISPCCDC_CULLING_CULHODD_SHIFT
- ISPCCDC_CULLING_CULV_SHIFT
- ISPCCDC_DCSUB
- ISPCCDC_FMTCFG
- ISPCCDC_FMTCFG_FMTEN
- ISPCCDC_FMTCFG_LNALT
- ISPCCDC_FMTCFG_LNUM_SHIFT
- ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT
- ISPCCDC_FMTCFG_PLEN_ODD_SHIFT
- ISPCCDC_FMTCFG_VPEN
- ISPCCDC_FMTCFG_VPIF_FRQ_BY2
- ISPCCDC_FMTCFG_VPIF_FRQ_BY3
- ISPCCDC_FMTCFG_VPIF_FRQ_BY4
- ISPCCDC_FMTCFG_VPIF_FRQ_BY5
- ISPCCDC_FMTCFG_VPIF_FRQ_BY6
- ISPCCDC_FMTCFG_VPIF_FRQ_MASK
- ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT
- ISPCCDC_FMTCFG_VPIN_10_1
- ISPCCDC_FMTCFG_VPIN_11_2
- ISPCCDC_FMTCFG_VPIN_12_3
- ISPCCDC_FMTCFG_VPIN_9_0
- ISPCCDC_FMTCFG_VPIN_MASK
- ISPCCDC_FMT_ADDR0
- ISPCCDC_FMT_ADDR1
- ISPCCDC_FMT_ADDR2
- ISPCCDC_FMT_ADDR3
- ISPCCDC_FMT_ADDR4
- ISPCCDC_FMT_ADDR5
- ISPCCDC_FMT_ADDR6
- ISPCCDC_FMT_ADDR7
- ISPCCDC_FMT_HORZ
- ISPCCDC_FMT_HORZ_FMTLNH_MASK
- ISPCCDC_FMT_HORZ_FMTLNH_SHIFT
- ISPCCDC_FMT_HORZ_FMTSPH_MASK
- ISPCCDC_FMT_HORZ_FMTSPH_SHIFT
- ISPCCDC_FMT_VERT
- ISPCCDC_FMT_VERT_FMTLNV_MASK
- ISPCCDC_FMT_VERT_FMTLNV_SHIFT
- ISPCCDC_FMT_VERT_FMTSLV_MASK
- ISPCCDC_FMT_VERT_FMTSLV_SHIFT
- ISPCCDC_FPC
- ISPCCDC_FPC_ADDR
- ISPCCDC_FPC_FPCEN
- ISPCCDC_FPC_FPERR
- ISPCCDC_FPC_FPNUM_SHIFT
- ISPCCDC_HD_VD_WID
- ISPCCDC_HD_VD_WID_HDW_SHIFT
- ISPCCDC_HD_VD_WID_VDW_SHIFT
- ISPCCDC_HORZ_INFO
- ISPCCDC_HORZ_INFO_NPH_MASK
- ISPCCDC_HORZ_INFO_NPH_SHIFT
- ISPCCDC_HORZ_INFO_SPH_MASK
- ISPCCDC_HORZ_INFO_SPH_SHIFT
- ISPCCDC_HSIZE_OFF
- ISPCCDC_HSIZE_OFF_SHIFT
- ISPCCDC_LSC_AFTER_REFORMATTER_MASK
- ISPCCDC_LSC_BUSY
- ISPCCDC_LSC_CONFIG
- ISPCCDC_LSC_ENABLE
- ISPCCDC_LSC_GAIN_FORMAT_MASK
- ISPCCDC_LSC_GAIN_FORMAT_SHIFT
- ISPCCDC_LSC_GAIN_MODE_M_MASK
- ISPCCDC_LSC_GAIN_MODE_M_SHIFT
- ISPCCDC_LSC_GAIN_MODE_N_MASK
- ISPCCDC_LSC_GAIN_MODE_N_SHIFT
- ISPCCDC_LSC_INITIAL
- ISPCCDC_LSC_INITIAL_X_MASK
- ISPCCDC_LSC_INITIAL_X_SHIFT
- ISPCCDC_LSC_INITIAL_Y_MASK
- ISPCCDC_LSC_INITIAL_Y_SHIFT
- ISPCCDC_LSC_TABLE_BASE
- ISPCCDC_LSC_TABLE_OFFSET
- ISPCCDC_PCR
- ISPCCDC_PCR_BUSY
- ISPCCDC_PCR_EN
- ISPCCDC_PID
- ISPCCDC_PID_CID_SHIFT
- ISPCCDC_PID_PREV_SHIFT
- ISPCCDC_PID_TID_SHIFT
- ISPCCDC_PIX_LINES
- ISPCCDC_PIX_LINES_HLPRF_SHIFT
- ISPCCDC_PIX_LINES_PPLN_SHIFT
- ISPCCDC_PRGEVEN0
- ISPCCDC_PRGEVEN1
- ISPCCDC_PRGODD0
- ISPCCDC_PRGODD1
- ISPCCDC_REC656IF
- ISPCCDC_REC656IF_ECCFVH
- ISPCCDC_REC656IF_R656ON
- ISPCCDC_SDOFST
- ISPCCDC_SDOFST_FIINV
- ISPCCDC_SDOFST_FOFST_MASK
- ISPCCDC_SDOFST_FOFST_SHIFT
- ISPCCDC_SDOFST_LOFST0_SHIFT
- ISPCCDC_SDOFST_LOFST1_SHIFT
- ISPCCDC_SDOFST_LOFST2_SHIFT
- ISPCCDC_SDOFST_LOFST3_SHIFT
- ISPCCDC_SDR_ADDR
- ISPCCDC_SYN_MODE
- ISPCCDC_SYN_MODE_DATAPOL
- ISPCCDC_SYN_MODE_DATSIZ_10
- ISPCCDC_SYN_MODE_DATSIZ_11
- ISPCCDC_SYN_MODE_DATSIZ_12
- ISPCCDC_SYN_MODE_DATSIZ_8
- ISPCCDC_SYN_MODE_DATSIZ_8_16
- ISPCCDC_SYN_MODE_DATSIZ_MASK
- ISPCCDC_SYN_MODE_EXWEN
- ISPCCDC_SYN_MODE_FLDMODE
- ISPCCDC_SYN_MODE_FLDOUT
- ISPCCDC_SYN_MODE_FLDPOL
- ISPCCDC_SYN_MODE_FLDSTAT
- ISPCCDC_SYN_MODE_HDPOL
- ISPCCDC_SYN_MODE_INPMOD_MASK
- ISPCCDC_SYN_MODE_INPMOD_RAW
- ISPCCDC_SYN_MODE_INPMOD_YCBCR16
- ISPCCDC_SYN_MODE_INPMOD_YCBCR8
- ISPCCDC_SYN_MODE_LPF
- ISPCCDC_SYN_MODE_PACK8
- ISPCCDC_SYN_MODE_SDR2RSZ
- ISPCCDC_SYN_MODE_VDHDEN
- ISPCCDC_SYN_MODE_VDHDOUT
- ISPCCDC_SYN_MODE_VDPOL
- ISPCCDC_SYN_MODE_VP2SDR
- ISPCCDC_SYN_MODE_WEN
- ISPCCDC_VDINT
- ISPCCDC_VDINT_0_MASK
- ISPCCDC_VDINT_0_SHIFT
- ISPCCDC_VDINT_1_MASK
- ISPCCDC_VDINT_1_SHIFT
- ISPCCDC_VERT_LINES
- ISPCCDC_VERT_LINES_NLV_MASK
- ISPCCDC_VERT_LINES_NLV_SHIFT
- ISPCCDC_VERT_START
- ISPCCDC_VERT_START_SLV0_MASK
- ISPCCDC_VERT_START_SLV0_SHIFT
- ISPCCDC_VERT_START_SLV1_SHIFT
- ISPCCDC_VP_OUT
- ISPCCDC_VP_OUT_HORZ_NUM_SHIFT
- ISPCCDC_VP_OUT_HORZ_ST_SHIFT
- ISPCCDC_VP_OUT_VERT_NUM_SHIFT
- ISPCCP2_CTRL
- ISPCCP2_CTRL_IF_EN
- ISPCCP2_CTRL_INV
- ISPCCP2_CTRL_INV_MASK
- ISPCCP2_CTRL_INV_SHIFT
- ISPCCP2_CTRL_IO_OUT_SEL
- ISPCCP2_CTRL_IO_OUT_SEL_MASK
- ISPCCP2_CTRL_IO_OUT_SEL_SHIFT
- ISPCCP2_CTRL_MODE
- ISPCCP2_CTRL_PHY_SEL
- ISPCCP2_CTRL_PHY_SEL_CLOCK
- ISPCCP2_CTRL_PHY_SEL_MASK
- ISPCCP2_CTRL_PHY_SEL_SHIFT
- ISPCCP2_CTRL_PHY_SEL_STROBE
- ISPCCP2_CTRL_VPCLK_DIV_MASK
- ISPCCP2_CTRL_VPCLK_DIV_SHIFT
- ISPCCP2_CTRL_VP_CLK_FORCE_ON
- ISPCCP2_CTRL_VP_CLK_POL
- ISPCCP2_CTRL_VP_CLK_POL_MASK
- ISPCCP2_CTRL_VP_CLK_POL_SHIFT
- ISPCCP2_CTRL_VP_ONLY_EN
- ISPCCP2_CTRL_VP_OUT_CTRL_MASK
- ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT
- ISPCCP2_DAT_SIZE_MAX
- ISPCCP2_DAT_SIZE_MIN
- ISPCCP2_DAT_START_MAX
- ISPCCP2_DAT_START_MIN
- ISPCCP2_DBG
- ISPCCP2_GNQ
- ISPCCP2_LC01_IRQENABLE
- ISPCCP2_LC01_IRQSTATUS
- ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ
- ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ
- ISPCCP2_LC23_IRQENABLE
- ISPCCP2_LC23_IRQSTATUS
- ISPCCP2_LCM_CTRL
- ISPCCP2_LCM_CTRL_BURST_SIZE_32X
- ISPCCP2_LCM_CTRL_BURST_SIZE_MASK
- ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT
- ISPCCP2_LCM_CTRL_CHAN_EN
- ISPCCP2_LCM_CTRL_DST_FORMAT_MASK
- ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10
- ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT
- ISPCCP2_LCM_CTRL_DST_PORT
- ISPCCP2_LCM_CTRL_DST_PORT_MEM
- ISPCCP2_LCM_CTRL_DST_PORT_SHIFT
- ISPCCP2_LCM_CTRL_DST_PORT_VP
- ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL
- ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK
- ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT
- ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10
- ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK
- ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT
- ISPCCP2_LCM_CTRL_SRC_DPCM_PRED
- ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK
- ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10
- ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8
- ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT
- ISPCCP2_LCM_CTRL_SRC_PACK
- ISPCCP2_LCM_DST_ADDR
- ISPCCP2_LCM_DST_OFST
- ISPCCP2_LCM_HSIZE
- ISPCCP2_LCM_HSIZE_COUNT_MAX
- ISPCCP2_LCM_HSIZE_COUNT_MIN
- ISPCCP2_LCM_HSIZE_SHIFT
- ISPCCP2_LCM_HSIZE_SKIP_MAX
- ISPCCP2_LCM_HSIZE_SKIP_MIN
- ISPCCP2_LCM_HWORDS_MAX
- ISPCCP2_LCM_HWORDS_MIN
- ISPCCP2_LCM_IRQENABLE
- ISPCCP2_LCM_IRQSTATUS
- ISPCCP2_LCM_IRQSTATUS_EOF_IRQ
- ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ
- ISPCCP2_LCM_PREFETCH
- ISPCCP2_LCM_PREFETCH_SHIFT
- ISPCCP2_LCM_SRC_ADDR
- ISPCCP2_LCM_SRC_OFST
- ISPCCP2_LCM_VSIZE
- ISPCCP2_LCM_VSIZE_MAX
- ISPCCP2_LCM_VSIZE_MIN
- ISPCCP2_LCM_VSIZE_SHIFT
- ISPCCP2_LCx_CODE
- ISPCCP2_LCx_CTRL
- ISPCCP2_LCx_CTRL_CHAN_EN
- ISPCCP2_LCx_CTRL_CRC_EN
- ISPCCP2_LCx_CTRL_CRC_MASK
- ISPCCP2_LCx_CTRL_CRC_SHIFT
- ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0
- ISPCCP2_LCx_CTRL_FORMAT_MASK
- ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0
- ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP
- ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP
- ISPCCP2_LCx_CTRL_FORMAT_SHIFT
- ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0
- ISPCCP2_LCx_CTRL_REGION_EN
- ISPCCP2_LCx_CTRL_REGION_MASK
- ISPCCP2_LCx_CTRL_REGION_SHIFT
- ISPCCP2_LCx_DAT_MASK
- ISPCCP2_LCx_DAT_OFST
- ISPCCP2_LCx_DAT_PING_ADDR
- ISPCCP2_LCx_DAT_PONG_ADDR
- ISPCCP2_LCx_DAT_SHIFT
- ISPCCP2_LCx_DAT_SIZE
- ISPCCP2_LCx_DAT_START
- ISPCCP2_LCx_EOF_ADDR
- ISPCCP2_LCx_SOF_ADDR
- ISPCCP2_LCx_STAT_SIZE
- ISPCCP2_LCx_STAT_START
- ISPCCP2_REVISION
- ISPCCP2_SYSCONFIG
- ISPCCP2_SYSCONFIG_AUTO_IDLE
- ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE
- ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO
- ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT
- ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART
- ISPCCP2_SYSCONFIG_SOFT_RESET
- ISPCCP2_SYSSTATUS
- ISPCCP2_SYSSTATUS_RESET_DONE
- ISPCCP2_VPCLK_FRACDIV
- ISPCSI2_CTRL
- ISPCSI2_CTRL_BURST_SIZE_MASK
- ISPCSI2_CTRL_BURST_SIZE_SHIFT
- ISPCSI2_CTRL_DBG_EN
- ISPCSI2_CTRL_ECC_EN
- ISPCSI2_CTRL_FRAME
- ISPCSI2_CTRL_IF_EN
- ISPCSI2_CTRL_SECURE
- ISPCSI2_CTRL_VP_CLK_EN
- ISPCSI2_CTRL_VP_ONLY_EN
- ISPCSI2_CTRL_VP_OUT_CTRL_MASK
- ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT
- ISPCSI2_CTX_CTRL1
- ISPCSI2_CTX_CTRL1_COUNT_MASK
- ISPCSI2_CTX_CTRL1_COUNT_SHIFT
- ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
- ISPCSI2_CTX_CTRL1_CS_EN
- ISPCSI2_CTX_CTRL1_CTX_EN
- ISPCSI2_CTX_CTRL1_EOF_EN
- ISPCSI2_CTX_CTRL1_EOL_EN
- ISPCSI2_CTX_CTRL1_PING_PONG
- ISPCSI2_CTX_CTRL2
- ISPCSI2_CTX_CTRL2_DPCM_PRED
- ISPCSI2_CTX_CTRL2_FORMAT_MASK
- ISPCSI2_CTX_CTRL2_FORMAT_SHIFT
- ISPCSI2_CTX_CTRL2_FRAME_MASK
- ISPCSI2_CTX_CTRL2_FRAME_SHIFT
- ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK
- ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT
- ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK
- ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT
- ISPCSI2_CTX_CTRL3
- ISPCSI2_CTX_CTRL3_ALPHA_MASK
- ISPCSI2_CTX_CTRL3_ALPHA_SHIFT
- ISPCSI2_CTX_DAT_OFST
- ISPCSI2_CTX_DAT_OFST_OFST_MASK
- ISPCSI2_CTX_DAT_OFST_OFST_SHIFT
- ISPCSI2_CTX_DAT_PING_ADDR
- ISPCSI2_CTX_DAT_PONG_ADDR
- ISPCSI2_CTX_IRQENABLE
- ISPCSI2_CTX_IRQENABLE_CS_IRQ
- ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ
- ISPCSI2_CTX_IRQENABLE_FE_IRQ
- ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ
- ISPCSI2_CTX_IRQENABLE_FS_IRQ
- ISPCSI2_CTX_IRQENABLE_LE_IRQ
- ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ
- ISPCSI2_CTX_IRQENABLE_LS_IRQ
- ISPCSI2_CTX_IRQSTATUS
- ISPCSI2_CTX_IRQSTATUS_CS_IRQ
- ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ
- ISPCSI2_CTX_IRQSTATUS_FE_IRQ
- ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ
- ISPCSI2_CTX_IRQSTATUS_FS_IRQ
- ISPCSI2_CTX_IRQSTATUS_LE_IRQ
- ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ
- ISPCSI2_CTX_IRQSTATUS_LS_IRQ
- ISPCSI2_CTX_TRANSCODEH
- ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK
- ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT
- ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK
- ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT
- ISPCSI2_CTX_TRANSCODEV
- ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK
- ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT
- ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK
- ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT
- ISPCSI2_DBG_H
- ISPCSI2_DBG_P
- ISPCSI2_GNQ
- ISPCSI2_IRQENABLE
- ISPCSI2_IRQSTATUS
- ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ
- ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ
- ISPCSI2_IRQSTATUS_CONTEXT
- ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ
- ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ
- ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ
- ISPCSI2_IRQSTATUS_OCP_ERR_IRQ
- ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ
- ISPCSI2_PHY_CFG
- ISPCSI2_PHY_CFG_CLOCK_POL_MASK
- ISPCSI2_PHY_CFG_CLOCK_POL_NP
- ISPCSI2_PHY_CFG_CLOCK_POL_PN
- ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT
- ISPCSI2_PHY_CFG_CLOCK_POSITION_1
- ISPCSI2_PHY_CFG_CLOCK_POSITION_2
- ISPCSI2_PHY_CFG_CLOCK_POSITION_3
- ISPCSI2_PHY_CFG_CLOCK_POSITION_4
- ISPCSI2_PHY_CFG_CLOCK_POSITION_5
- ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK
- ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT
- ISPCSI2_PHY_CFG_DATA_POL_MASK
- ISPCSI2_PHY_CFG_DATA_POL_NP
- ISPCSI2_PHY_CFG_DATA_POL_PN
- ISPCSI2_PHY_CFG_DATA_POL_SHIFT
- ISPCSI2_PHY_CFG_DATA_POSITION_1
- ISPCSI2_PHY_CFG_DATA_POSITION_2
- ISPCSI2_PHY_CFG_DATA_POSITION_3
- ISPCSI2_PHY_CFG_DATA_POSITION_4
- ISPCSI2_PHY_CFG_DATA_POSITION_5
- ISPCSI2_PHY_CFG_DATA_POSITION_MASK
- ISPCSI2_PHY_CFG_DATA_POSITION_NC
- ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT
- ISPCSI2_PHY_CFG_PWR_AUTO
- ISPCSI2_PHY_CFG_PWR_CMD_MASK
- ISPCSI2_PHY_CFG_PWR_CMD_OFF
- ISPCSI2_PHY_CFG_PWR_CMD_ON
- ISPCSI2_PHY_CFG_PWR_CMD_SHIFT
- ISPCSI2_PHY_CFG_PWR_CMD_ULPW
- ISPCSI2_PHY_CFG_PWR_STATUS_MASK
- ISPCSI2_PHY_CFG_PWR_STATUS_OFF
- ISPCSI2_PHY_CFG_PWR_STATUS_ON
- ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT
- ISPCSI2_PHY_CFG_PWR_STATUS_ULPW
- ISPCSI2_PHY_CFG_RESET_CTRL
- ISPCSI2_PHY_CFG_RESET_DONE
- ISPCSI2_PHY_IRQENABLE
- ISPCSI2_PHY_IRQENABLE_ERRCONTROL1
- ISPCSI2_PHY_IRQENABLE_ERRCONTROL2
- ISPCSI2_PHY_IRQENABLE_ERRCONTROL3
- ISPCSI2_PHY_IRQENABLE_ERRCONTROL4
- ISPCSI2_PHY_IRQENABLE_ERRCONTROL5
- ISPCSI2_PHY_IRQENABLE_ERRESC1
- ISPCSI2_PHY_IRQENABLE_ERRESC2
- ISPCSI2_PHY_IRQENABLE_ERRESC3
- ISPCSI2_PHY_IRQENABLE_ERRESC4
- ISPCSI2_PHY_IRQENABLE_ERRESC5
- ISPCSI2_PHY_IRQENABLE_ERRSOTHS1
- ISPCSI2_PHY_IRQENABLE_ERRSOTHS2
- ISPCSI2_PHY_IRQENABLE_ERRSOTHS3
- ISPCSI2_PHY_IRQENABLE_ERRSOTHS4
- ISPCSI2_PHY_IRQENABLE_ERRSOTHS5
- ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1
- ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2
- ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3
- ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4
- ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5
- ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER
- ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT
- ISPCSI2_PHY_IRQENABLE_STATEULPM1
- ISPCSI2_PHY_IRQENABLE_STATEULPM2
- ISPCSI2_PHY_IRQENABLE_STATEULPM3
- ISPCSI2_PHY_IRQENABLE_STATEULPM4
- ISPCSI2_PHY_IRQENABLE_STATEULPM5
- ISPCSI2_PHY_IRQSTATUS
- ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1
- ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2
- ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3
- ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4
- ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5
- ISPCSI2_PHY_IRQSTATUS_ERRESC1
- ISPCSI2_PHY_IRQSTATUS_ERRESC2
- ISPCSI2_PHY_IRQSTATUS_ERRESC3
- ISPCSI2_PHY_IRQSTATUS_ERRESC4
- ISPCSI2_PHY_IRQSTATUS_ERRESC5
- ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1
- ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2
- ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3
- ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4
- ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5
- ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1
- ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2
- ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3
- ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4
- ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5
- ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER
- ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT
- ISPCSI2_PHY_IRQSTATUS_STATEULPM1
- ISPCSI2_PHY_IRQSTATUS_STATEULPM2
- ISPCSI2_PHY_IRQSTATUS_STATEULPM3
- ISPCSI2_PHY_IRQSTATUS_STATEULPM4
- ISPCSI2_PHY_IRQSTATUS_STATEULPM5
- ISPCSI2_REVISION
- ISPCSI2_SHORT_PACKET
- ISPCSI2_SYSCONFIG
- ISPCSI2_SYSCONFIG_AUTO_IDLE
- ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE
- ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK
- ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO
- ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT
- ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART
- ISPCSI2_SYSCONFIG_SOFT_RESET
- ISPCSI2_SYSSTATUS
- ISPCSI2_SYSSTATUS_RESET_DONE
- ISPCSI2_TIMING
- ISPCSI2_TIMING_FORCE_RX_MODE_IO
- ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK
- ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT
- ISPCSI2_TIMING_STOP_STATE_X16_IO
- ISPCSI2_TIMING_STOP_STATE_X4_IO
- ISPCSIPHY_REG0
- ISPCSIPHY_REG0_THS_SETTLE_MASK
- ISPCSIPHY_REG0_THS_SETTLE_SHIFT
- ISPCSIPHY_REG0_THS_TERM_MASK
- ISPCSIPHY_REG0_THS_TERM_SHIFT
- ISPCSIPHY_REG1
- ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS
- ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK
- ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT
- ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK
- ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT
- ISPCSIPHY_REG1_RESET_DONE_CTRLCLK
- ISPCSIPHY_REG1_TCLK_MISS_MASK
- ISPCSIPHY_REG1_TCLK_MISS_SHIFT
- ISPCSIPHY_REG1_TCLK_SETTLE_MASK
- ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT
- ISPCSIPHY_REG1_TCLK_TERM_MASK
- ISPCSIPHY_REG1_TCLK_TERM_SHIFT
- ISPCSIPHY_REG2
- ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK
- ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK
- ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT
- ISPCTRL00_AWB_EN
- ISPCTRL00_AWB_GAIN_EN
- ISPCTRL_CCDC_CLK_EN
- ISPCTRL_CCDC_FLUSH
- ISPCTRL_CCDC_RAM_EN
- ISPCTRL_CLKS_MASK
- ISPCTRL_H3A_CLK_EN
- ISPCTRL_HIST_CLK_EN
- ISPCTRL_JPEG_FLUSH
- ISPCTRL_PAR_BRIDGE_BENDIAN
- ISPCTRL_PAR_BRIDGE_DISABLE
- ISPCTRL_PAR_BRIDGE_LENDIAN
- ISPCTRL_PAR_BRIDGE_MASK
- ISPCTRL_PAR_BRIDGE_SHIFT
- ISPCTRL_PAR_CLK_POL_INV
- ISPCTRL_PAR_CLK_POL_SHIFT
- ISPCTRL_PAR_SER_CLK_SEL_CSIA
- ISPCTRL_PAR_SER_CLK_SEL_CSIB
- ISPCTRL_PAR_SER_CLK_SEL_CSIC
- ISPCTRL_PAR_SER_CLK_SEL_MASK
- ISPCTRL_PAR_SER_CLK_SEL_PARALLEL
- ISPCTRL_PING_PONG_EN
- ISPCTRL_PREV_CLK_EN
- ISPCTRL_PREV_RAM_EN
- ISPCTRL_RSZ_CLK_EN
- ISPCTRL_SBL_AUTOIDLE
- ISPCTRL_SBL_RD_RAM_EN
- ISPCTRL_SBL_SHARED_RPORTA
- ISPCTRL_SBL_SHARED_RPORTB
- ISPCTRL_SBL_SHARED_WPORTC
- ISPCTRL_SBL_WR0_RAM_EN
- ISPCTRL_SBL_WR1_RAM_EN
- ISPCTRL_SCMP_CLK_EN
- ISPCTRL_SHIFT_0
- ISPCTRL_SHIFT_2
- ISPCTRL_SHIFT_4
- ISPCTRL_SHIFT_MASK
- ISPCTRL_SHIFT_SHIFT
- ISPCTRL_SYNC_DETECT_HSFALL
- ISPCTRL_SYNC_DETECT_HSRISE
- ISPCTRL_SYNC_DETECT_MASK
- ISPCTRL_SYNC_DETECT_SHIFT
- ISPCTRL_SYNC_DETECT_VSFALL
- ISPCTRL_SYNC_DETECT_VSRISE
- ISPDRIVER_IPC
- ISPH3A_AEWBUFST
- ISPH3A_AEWINBLK
- ISPH3A_AEWINBLK_WINH_MASK
- ISPH3A_AEWINBLK_WINH_SHIFT
- ISPH3A_AEWINBLK_WINSV_MASK
- ISPH3A_AEWINBLK_WINSV_SHIFT
- ISPH3A_AEWINSTART
- ISPH3A_AEWINSTART_WINSH_MASK
- ISPH3A_AEWINSTART_WINSH_SHIFT
- ISPH3A_AEWINSTART_WINSV_MASK
- ISPH3A_AEWINSTART_WINSV_SHIFT
- ISPH3A_AEWSUBWIN
- ISPH3A_AEWSUBWIN_AEWINCH_MASK
- ISPH3A_AEWSUBWIN_AEWINCH_SHIFT
- ISPH3A_AEWSUBWIN_AEWINCV_MASK
- ISPH3A_AEWSUBWIN_AEWINCV_SHIFT
- ISPH3A_AEWWIN1
- ISPH3A_AEWWIN1_WINHC_MASK
- ISPH3A_AEWWIN1_WINHC_SHIFT
- ISPH3A_AEWWIN1_WINH_MASK
- ISPH3A_AEWWIN1_WINH_SHIFT
- ISPH3A_AEWWIN1_WINVC_MASK
- ISPH3A_AEWWIN1_WINVC_SHIFT
- ISPH3A_AEWWIN1_WINW_MASK
- ISPH3A_AEWWIN1_WINW_SHIFT
- ISPH3A_AFBUFST
- ISPH3A_AFCOEF0010
- ISPH3A_AFCOEF010
- ISPH3A_AFCOEF032
- ISPH3A_AFCOEF054
- ISPH3A_AFCOEF076
- ISPH3A_AFCOEF098
- ISPH3A_AFCOEF1010
- ISPH3A_AFCOEF110
- ISPH3A_AFCOEF132
- ISPH3A_AFCOEF154
- ISPH3A_AFCOEF176
- ISPH3A_AFCOEF198
- ISPH3A_AFIIRSH
- ISPH3A_AFPAX1
- ISPH3A_AFPAX2
- ISPH3A_AFPAXSTART
- ISPH3A_PCR
- ISPH3A_PCR_AEW_ALAW_EN
- ISPH3A_PCR_AEW_ALAW_EN_SHIFT
- ISPH3A_PCR_AEW_AVE2LMT_MASK
- ISPH3A_PCR_AEW_AVE2LMT_SHIFT
- ISPH3A_PCR_AEW_BUSY
- ISPH3A_PCR_AEW_EN
- ISPH3A_PCR_AEW_MASK
- ISPH3A_PCR_AF_ALAW_EN
- ISPH3A_PCR_AF_BUSY
- ISPH3A_PCR_AF_EN
- ISPH3A_PCR_AF_MED_EN
- ISPH3A_PCR_AF_MED_TH_SHIFT
- ISPH3A_PCR_AF_RGBPOS_SHIFT
- ISPH3A_PCR_BUSYAEAWB
- ISPH3A_PCR_BUSYAF
- ISPH3A_PID
- ISPHIST_ADDR
- ISPHIST_ADDR_MASK
- ISPHIST_ADDR_SHIFT
- ISPHIST_CNT
- ISPHIST_CNT_BINS_MASK
- ISPHIST_CNT_BINS_SHIFT
- ISPHIST_CNT_CFA_MASK
- ISPHIST_CNT_CFA_SHIFT
- ISPHIST_CNT_CLEAR
- ISPHIST_CNT_CLEAR_MASK
- ISPHIST_CNT_CLEAR_SHIFT
- ISPHIST_CNT_DATASIZE_MASK
- ISPHIST_CNT_DATASIZE_SHIFT
- ISPHIST_CNT_SHIFT_MASK
- ISPHIST_CNT_SHIFT_SHIFT
- ISPHIST_CNT_SOURCE_MASK
- ISPHIST_CNT_SOURCE_SHIFT
- ISPHIST_DATA
- ISPHIST_DATA_MASK
- ISPHIST_DATA_SHIFT
- ISPHIST_HV_INFO_HSIZE_MASK
- ISPHIST_HV_INFO_HSIZE_SHIFT
- ISPHIST_HV_INFO_MASK
- ISPHIST_HV_INFO_VSIZE_MASK
- ISPHIST_HV_INFO_VSIZE_SHIFT
- ISPHIST_H_V_INFO
- ISPHIST_IN_BIT_WIDTH_CCDC
- ISPHIST_PCR
- ISPHIST_PCR_BUSY
- ISPHIST_PCR_ENABLE
- ISPHIST_PCR_ENABLE_MASK
- ISPHIST_PCR_ENABLE_SHIFT
- ISPHIST_PID
- ISPHIST_R0_HORZ
- ISPHIST_R0_VERT
- ISPHIST_R1_HORZ
- ISPHIST_R1_VERT
- ISPHIST_R2_HORZ
- ISPHIST_R2_VERT
- ISPHIST_R3_HORZ
- ISPHIST_R3_VERT
- ISPHIST_RADD
- ISPHIST_RADD_MASK
- ISPHIST_RADD_OFF
- ISPHIST_RADD_OFF_MASK
- ISPHIST_RADD_OFF_SHIFT
- ISPHIST_RADD_SHIFT
- ISPHIST_REG_END_MASK
- ISPHIST_REG_END_SHIFT
- ISPHIST_REG_MASK
- ISPHIST_REG_START_END_MASK
- ISPHIST_REG_START_MASK
- ISPHIST_REG_START_SHIFT
- ISPHIST_WB_GAIN
- ISPHIST_WB_GAIN_WG00_MASK
- ISPHIST_WB_GAIN_WG00_SHIFT
- ISPHIST_WB_GAIN_WG01_MASK
- ISPHIST_WB_GAIN_WG01_SHIFT
- ISPHIST_WB_GAIN_WG02_MASK
- ISPHIST_WB_GAIN_WG02_SHIFT
- ISPHIST_WB_GAIN_WG03_MASK
- ISPHIST_WB_GAIN_WG03_SHIFT
- ISPIF_IRQ_GLOBAL_CLEAR_CMD
- ISPIF_RESET_TIMEOUT_MS
- ISPIF_RST_CMD_0
- ISPIF_RST_CMD_0_MISC_LOGIC_RST
- ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST
- ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST
- ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST
- ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST
- ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST
- ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST
- ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST
- ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST
- ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST
- ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST
- ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST
- ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST
- ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST
- ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST
- ISPIF_RST_CMD_0_STROBED_RST_EN
- ISPIF_RST_CMD_0_SW_REG_RST
- ISPIF_TIMEOUT_ALL_US
- ISPIF_TIMEOUT_SLEEP_US
- ISPIF_VFE_m_CTRL_0
- ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN
- ISPIF_VFE_m_INTF_CMD_0
- ISPIF_VFE_m_INTF_CMD_1
- ISPIF_VFE_m_INTF_INPUT_SEL
- ISPIF_VFE_m_IRQ_CLEAR_0
- ISPIF_VFE_m_IRQ_CLEAR_1
- ISPIF_VFE_m_IRQ_CLEAR_2
- ISPIF_VFE_m_IRQ_MASK_0
- ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE
- ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK
- ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE
- ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK
- ISPIF_VFE_m_IRQ_MASK_1
- ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE
- ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK
- ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE
- ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK
- ISPIF_VFE_m_IRQ_MASK_2
- ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE
- ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK
- ISPIF_VFE_m_IRQ_STATUS_0
- ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW
- ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW
- ISPIF_VFE_m_IRQ_STATUS_1
- ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW
- ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW
- ISPIF_VFE_m_IRQ_STATUS_2
- ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW
- ISPIF_VFE_m_PIX_INTF_n_CID_MASK
- ISPIF_VFE_m_PIX_INTF_n_STATUS
- ISPIF_VFE_m_RDI_INTF_n_CID_MASK
- ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0
- ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN
- ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1
- ISPIF_VFE_m_RDI_INTF_n_STATUS
- ISPPRV_AVE
- ISPPRV_AVE_EVENDIST_1
- ISPPRV_AVE_EVENDIST_2
- ISPPRV_AVE_EVENDIST_3
- ISPPRV_AVE_EVENDIST_4
- ISPPRV_AVE_EVENDIST_SHIFT
- ISPPRV_AVE_ODDDIST_1
- ISPPRV_AVE_ODDDIST_2
- ISPPRV_AVE_ODDDIST_3
- ISPPRV_AVE_ODDDIST_4
- ISPPRV_AVE_ODDDIST_SHIFT
- ISPPRV_BLKADJOFF
- ISPPRV_BLKADJOFF_B_SHIFT
- ISPPRV_BLKADJOFF_G_SHIFT
- ISPPRV_BLKADJOFF_R_SHIFT
- ISPPRV_BLUEGAMMA_TABLE_ADDR
- ISPPRV_BRIGHT_DEF
- ISPPRV_BRIGHT_HIGH
- ISPPRV_BRIGHT_LOW
- ISPPRV_BRIGHT_MAX
- ISPPRV_BRIGHT_MIN
- ISPPRV_BRIGHT_STEP
- ISPPRV_BRIGHT_UNITS
- ISPPRV_CDC_THR0
- ISPPRV_CDC_THR1
- ISPPRV_CDC_THR2
- ISPPRV_CDC_THR3
- ISPPRV_CFA
- ISPPRV_CFA_GRADTH_HOR_SHIFT
- ISPPRV_CFA_GRADTH_VER_SHIFT
- ISPPRV_CFA_TABLE_ADDR
- ISPPRV_CNT_BRT
- ISPPRV_CNT_BRT_BRT_SHIFT
- ISPPRV_CNT_BRT_CNT_SHIFT
- ISPPRV_CONTRAST_DEF
- ISPPRV_CONTRAST_HIGH
- ISPPRV_CONTRAST_LOW
- ISPPRV_CONTRAST_MAX
- ISPPRV_CONTRAST_MIN
- ISPPRV_CONTRAST_STEP
- ISPPRV_CONTRAST_UNITS
- ISPPRV_CSC0
- ISPPRV_CSC0_BY_SHIFT
- ISPPRV_CSC0_GY_SHIFT
- ISPPRV_CSC0_RY_SHIFT
- ISPPRV_CSC1
- ISPPRV_CSC1_BCB_SHIFT
- ISPPRV_CSC1_GCB_SHIFT
- ISPPRV_CSC1_RCB_SHIFT
- ISPPRV_CSC2
- ISPPRV_CSC2_BCR_SHIFT
- ISPPRV_CSC2_GCR_SHIFT
- ISPPRV_CSC2_RCR_SHIFT
- ISPPRV_CSC_OFFSET
- ISPPRV_CSC_OFFSET_CB_SHIFT
- ISPPRV_CSC_OFFSET_CR_SHIFT
- ISPPRV_CSC_OFFSET_Y_SHIFT
- ISPPRV_CSUP
- ISPPRV_CSUP_CSUPG_SHIFT
- ISPPRV_CSUP_HPYF_SHIFT
- ISPPRV_CSUP_THRES_SHIFT
- ISPPRV_DRKF_OFFSET
- ISPPRV_DSDR_ADDR
- ISPPRV_GREENGAMMA_TABLE_ADDR
- ISPPRV_HMED
- ISPPRV_HMED_EVENDIST
- ISPPRV_HMED_ODDDIST
- ISPPRV_HMED_THRESHOLD_SHIFT
- ISPPRV_HORZ_INFO
- ISPPRV_HORZ_INFO_EPH_MASK
- ISPPRV_HORZ_INFO_EPH_SHIFT
- ISPPRV_HORZ_INFO_SPH_MASK
- ISPPRV_HORZ_INFO_SPH_SHIFT
- ISPPRV_NF
- ISPPRV_NF_TABLE_ADDR
- ISPPRV_PCR
- ISPPRV_PCR_BUSY
- ISPPRV_PCR_CFAEN
- ISPPRV_PCR_CFAFMT_BAYER
- ISPPRV_PCR_CFAFMT_DNSPL
- ISPPRV_PCR_CFAFMT_HONEYCOMB
- ISPPRV_PCR_CFAFMT_MASK
- ISPPRV_PCR_CFAFMT_RGBFOVEON
- ISPPRV_PCR_CFAFMT_RRGGBBFOVEON
- ISPPRV_PCR_CFAFMT_SHIFT
- ISPPRV_PCR_CFAFMT_SONYVGA
- ISPPRV_PCR_DCCOUP
- ISPPRV_PCR_DCOREN
- ISPPRV_PCR_DRKFCAP
- ISPPRV_PCR_DRKFEN
- ISPPRV_PCR_DRK_FAIL
- ISPPRV_PCR_EN
- ISPPRV_PCR_GAMMA_BYPASS
- ISPPRV_PCR_HMEDEN
- ISPPRV_PCR_INVALAW
- ISPPRV_PCR_NFEN
- ISPPRV_PCR_ONESHOT
- ISPPRV_PCR_RSZPORT
- ISPPRV_PCR_SCOMP_EN
- ISPPRV_PCR_SCOMP_SFT_MASK
- ISPPRV_PCR_SCOMP_SFT_SHIFT
- ISPPRV_PCR_SDRPORT
- ISPPRV_PCR_SOURCE
- ISPPRV_PCR_SUPEN
- ISPPRV_PCR_WIDTH
- ISPPRV_PCR_YCPOS_CbYCrY
- ISPPRV_PCR_YCPOS_CrYCbY
- ISPPRV_PCR_YCPOS_SHIFT
- ISPPRV_PCR_YCPOS_YCbYCr
- ISPPRV_PCR_YCPOS_YCrYCb
- ISPPRV_PCR_YNENHEN
- ISPPRV_RADR_OFFSET
- ISPPRV_REDGAMMA_TABLE_ADDR
- ISPPRV_RGB_MAT1
- ISPPRV_RGB_MAT1_MTX_GR_SHIFT
- ISPPRV_RGB_MAT1_MTX_RR_SHIFT
- ISPPRV_RGB_MAT2
- ISPPRV_RGB_MAT2_MTX_BR_SHIFT
- ISPPRV_RGB_MAT2_MTX_RG_SHIFT
- ISPPRV_RGB_MAT3
- ISPPRV_RGB_MAT3_MTX_BG_SHIFT
- ISPPRV_RGB_MAT3_MTX_GG_SHIFT
- ISPPRV_RGB_MAT4
- ISPPRV_RGB_MAT4_MTX_GB_SHIFT
- ISPPRV_RGB_MAT4_MTX_RB_SHIFT
- ISPPRV_RGB_MAT5
- ISPPRV_RGB_MAT5_MTX_BB_SHIFT
- ISPPRV_RGB_OFF1
- ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT
- ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT
- ISPPRV_RGB_OFF2
- ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT
- ISPPRV_RSDR_ADDR
- ISPPRV_SETUP_YC
- ISPPRV_SETUP_YC_MAXC_SHIFT
- ISPPRV_SETUP_YC_MAXY_SHIFT
- ISPPRV_SETUP_YC_MINC_SHIFT
- ISPPRV_SETUP_YC_MINY_SHIFT
- ISPPRV_SET_TBL_ADDR
- ISPPRV_SET_TBL_DATA
- ISPPRV_VERT_INFO
- ISPPRV_VERT_INFO_ELV_MASK
- ISPPRV_VERT_INFO_ELV_SHIFT
- ISPPRV_VERT_INFO_SLV_MASK
- ISPPRV_VERT_INFO_SLV_SHIFT
- ISPPRV_WADD_OFFSET
- ISPPRV_WBGAIN
- ISPPRV_WBGAIN_COEF0_SHIFT
- ISPPRV_WBGAIN_COEF1_SHIFT
- ISPPRV_WBGAIN_COEF2_SHIFT
- ISPPRV_WBGAIN_COEF3_SHIFT
- ISPPRV_WBSEL
- ISPPRV_WBSEL_COEF0
- ISPPRV_WBSEL_COEF1
- ISPPRV_WBSEL_COEF2
- ISPPRV_WBSEL_COEF3
- ISPPRV_WBSEL_N0_0_SHIFT
- ISPPRV_WBSEL_N0_1_SHIFT
- ISPPRV_WBSEL_N0_2_SHIFT
- ISPPRV_WBSEL_N0_3_SHIFT
- ISPPRV_WBSEL_N1_0_SHIFT
- ISPPRV_WBSEL_N1_1_SHIFT
- ISPPRV_WBSEL_N1_2_SHIFT
- ISPPRV_WBSEL_N1_3_SHIFT
- ISPPRV_WBSEL_N2_0_SHIFT
- ISPPRV_WBSEL_N2_1_SHIFT
- ISPPRV_WBSEL_N2_2_SHIFT
- ISPPRV_WBSEL_N2_3_SHIFT
- ISPPRV_WBSEL_N3_0_SHIFT
- ISPPRV_WBSEL_N3_1_SHIFT
- ISPPRV_WBSEL_N3_2_SHIFT
- ISPPRV_WBSEL_N3_3_SHIFT
- ISPPRV_WB_DGAIN
- ISPPRV_WSDR_ADDR
- ISPPRV_YC_MAX
- ISPPRV_YC_MIN
- ISPPRV_YENH_TABLE_ADDR
- ISPREG
- ISPRINT
- ISPRSZ_CNT
- ISPRSZ_CNT_CBILIN
- ISPRSZ_CNT_HRSZ_MASK
- ISPRSZ_CNT_HRSZ_SHIFT
- ISPRSZ_CNT_HSTPH_MASK
- ISPRSZ_CNT_HSTPH_SHIFT
- ISPRSZ_CNT_INPSRC
- ISPRSZ_CNT_INPTYP
- ISPRSZ_CNT_VRSZ_MASK
- ISPRSZ_CNT_VRSZ_SHIFT
- ISPRSZ_CNT_VSTPH_MASK
- ISPRSZ_CNT_VSTPH_SHIFT
- ISPRSZ_CNT_YCPOS
- ISPRSZ_HFILT10
- ISPRSZ_HFILT1110
- ISPRSZ_HFILT1110_COEF10_MASK
- ISPRSZ_HFILT1110_COEF10_SHIFT
- ISPRSZ_HFILT1110_COEF11_MASK
- ISPRSZ_HFILT1110_COEF11_SHIFT
- ISPRSZ_HFILT1312
- ISPRSZ_HFILT1312_COEFF12_MASK
- ISPRSZ_HFILT1312_COEFF12_SHIFT
- ISPRSZ_HFILT1312_COEFF13_MASK
- ISPRSZ_HFILT1312_COEFF13_SHIFT
- ISPRSZ_HFILT1514
- ISPRSZ_HFILT1514_COEFF14_MASK
- ISPRSZ_HFILT1514_COEFF14_SHIFT
- ISPRSZ_HFILT1514_COEFF15_MASK
- ISPRSZ_HFILT1514_COEFF15_SHIFT
- ISPRSZ_HFILT1716
- ISPRSZ_HFILT1716_COEF16_MASK
- ISPRSZ_HFILT1716_COEF16_SHIFT
- ISPRSZ_HFILT1716_COEF17_MASK
- ISPRSZ_HFILT1716_COEF17_SHIFT
- ISPRSZ_HFILT1918
- ISPRSZ_HFILT1918_COEF18_MASK
- ISPRSZ_HFILT1918_COEF18_SHIFT
- ISPRSZ_HFILT1918_COEF19_MASK
- ISPRSZ_HFILT1918_COEF19_SHIFT
- ISPRSZ_HFILT2120
- ISPRSZ_HFILT2120_COEF20_MASK
- ISPRSZ_HFILT2120_COEF20_SHIFT
- ISPRSZ_HFILT2120_COEF21_MASK
- ISPRSZ_HFILT2120_COEF21_SHIFT
- ISPRSZ_HFILT2322
- ISPRSZ_HFILT2322_COEF22_MASK
- ISPRSZ_HFILT2322_COEF22_SHIFT
- ISPRSZ_HFILT2322_COEF23_MASK
- ISPRSZ_HFILT2322_COEF23_SHIFT
- ISPRSZ_HFILT2524
- ISPRSZ_HFILT2524_COEF24_MASK
- ISPRSZ_HFILT2524_COEF24_SHIFT
- ISPRSZ_HFILT2524_COEF25_MASK
- ISPRSZ_HFILT2524_COEF25_SHIFT
- ISPRSZ_HFILT2726
- ISPRSZ_HFILT2726_COEF26_MASK
- ISPRSZ_HFILT2726_COEF26_SHIFT
- ISPRSZ_HFILT2726_COEF27_MASK
- ISPRSZ_HFILT2726_COEF27_SHIFT
- ISPRSZ_HFILT2928
- ISPRSZ_HFILT2928_COEF28_MASK
- ISPRSZ_HFILT2928_COEF28_SHIFT
- ISPRSZ_HFILT2928_COEF29_MASK
- ISPRSZ_HFILT2928_COEF29_SHIFT
- ISPRSZ_HFILT3130
- ISPRSZ_HFILT3130_COEF30_MASK
- ISPRSZ_HFILT3130_COEF30_SHIFT
- ISPRSZ_HFILT3130_COEF31_MASK
- ISPRSZ_HFILT3130_COEF31_SHIFT
- ISPRSZ_HFILT32
- ISPRSZ_HFILT32_COEF2_MASK
- ISPRSZ_HFILT32_COEF2_SHIFT
- ISPRSZ_HFILT32_COEF3_MASK
- ISPRSZ_HFILT32_COEF3_SHIFT
- ISPRSZ_HFILT54
- ISPRSZ_HFILT54_COEF4_MASK
- ISPRSZ_HFILT54_COEF4_SHIFT
- ISPRSZ_HFILT54_COEF5_MASK
- ISPRSZ_HFILT54_COEF5_SHIFT
- ISPRSZ_HFILT76
- ISPRSZ_HFILT76_COEFF6_MASK
- ISPRSZ_HFILT76_COEFF6_SHIFT
- ISPRSZ_HFILT76_COEFF7_MASK
- ISPRSZ_HFILT76_COEFF7_SHIFT
- ISPRSZ_HFILT98
- ISPRSZ_HFILT98_COEFF8_MASK
- ISPRSZ_HFILT98_COEFF8_SHIFT
- ISPRSZ_HFILT98_COEFF9_MASK
- ISPRSZ_HFILT98_COEFF9_SHIFT
- ISPRSZ_HFILT_COEF0_MASK
- ISPRSZ_HFILT_COEF0_SHIFT
- ISPRSZ_HFILT_COEF1_MASK
- ISPRSZ_HFILT_COEF1_SHIFT
- ISPRSZ_IN_SIZE
- ISPRSZ_IN_SIZE_HORZ_MASK
- ISPRSZ_IN_SIZE_HORZ_SHIFT
- ISPRSZ_IN_SIZE_VERT_MASK
- ISPRSZ_IN_SIZE_VERT_SHIFT
- ISPRSZ_IN_START
- ISPRSZ_IN_START_HORZ_ST_MASK
- ISPRSZ_IN_START_HORZ_ST_SHIFT
- ISPRSZ_IN_START_VERT_ST_MASK
- ISPRSZ_IN_START_VERT_ST_SHIFT
- ISPRSZ_MAX_OUTPUT
- ISPRSZ_MIN_OUTPUT
- ISPRSZ_OUT_SIZE
- ISPRSZ_OUT_SIZE_HORZ_MASK
- ISPRSZ_OUT_SIZE_HORZ_SHIFT
- ISPRSZ_OUT_SIZE_VERT_MASK
- ISPRSZ_OUT_SIZE_VERT_SHIFT
- ISPRSZ_PCR
- ISPRSZ_PCR_BUSY
- ISPRSZ_PCR_ENABLE
- ISPRSZ_PCR_ONESHOT
- ISPRSZ_PID
- ISPRSZ_PID_CID_SHIFT
- ISPRSZ_PID_PREV_SHIFT
- ISPRSZ_PID_TID_SHIFT
- ISPRSZ_SDR_INADD
- ISPRSZ_SDR_INADD_ADDR_MASK
- ISPRSZ_SDR_INADD_ADDR_SHIFT
- ISPRSZ_SDR_INOFF
- ISPRSZ_SDR_INOFF_OFFSET_MASK
- ISPRSZ_SDR_INOFF_OFFSET_SHIFT
- ISPRSZ_SDR_OUTADD
- ISPRSZ_SDR_OUTADD_ADDR_MASK
- ISPRSZ_SDR_OUTADD_ADDR_SHIFT
- ISPRSZ_SDR_OUTOFF
- ISPRSZ_SDR_OUTOFF_OFFSET_MASK
- ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT
- ISPRSZ_VFILT10
- ISPRSZ_VFILT10_COEF0_MASK
- ISPRSZ_VFILT10_COEF0_SHIFT
- ISPRSZ_VFILT10_COEF1_MASK
- ISPRSZ_VFILT10_COEF1_SHIFT
- ISPRSZ_VFILT1110
- ISPRSZ_VFILT1110_COEF10_MASK
- ISPRSZ_VFILT1110_COEF10_SHIFT
- ISPRSZ_VFILT1110_COEF11_MASK
- ISPRSZ_VFILT1110_COEF11_SHIFT
- ISPRSZ_VFILT1312
- ISPRSZ_VFILT1312_COEFF12_MASK
- ISPRSZ_VFILT1312_COEFF12_SHIFT
- ISPRSZ_VFILT1312_COEFF13_MASK
- ISPRSZ_VFILT1312_COEFF13_SHIFT
- ISPRSZ_VFILT1514
- ISPRSZ_VFILT1514_COEFF14_MASK
- ISPRSZ_VFILT1514_COEFF14_SHIFT
- ISPRSZ_VFILT1514_COEFF15_MASK
- ISPRSZ_VFILT1514_COEFF15_SHIFT
- ISPRSZ_VFILT1716
- ISPRSZ_VFILT1716_COEF16_MASK
- ISPRSZ_VFILT1716_COEF16_SHIFT
- ISPRSZ_VFILT1716_COEF17_MASK
- ISPRSZ_VFILT1716_COEF17_SHIFT
- ISPRSZ_VFILT1918
- ISPRSZ_VFILT1918_COEF18_MASK
- ISPRSZ_VFILT1918_COEF18_SHIFT
- ISPRSZ_VFILT1918_COEF19_MASK
- ISPRSZ_VFILT1918_COEF19_SHIFT
- ISPRSZ_VFILT2120
- ISPRSZ_VFILT2120_COEF20_MASK
- ISPRSZ_VFILT2120_COEF20_SHIFT
- ISPRSZ_VFILT2120_COEF21_MASK
- ISPRSZ_VFILT2120_COEF21_SHIFT
- ISPRSZ_VFILT2322
- ISPRSZ_VFILT2322_COEF22_MASK
- ISPRSZ_VFILT2322_COEF22_SHIFT
- ISPRSZ_VFILT2322_COEF23_MASK
- ISPRSZ_VFILT2322_COEF23_SHIFT
- ISPRSZ_VFILT2524
- ISPRSZ_VFILT2524_COEF24_MASK
- ISPRSZ_VFILT2524_COEF24_SHIFT
- ISPRSZ_VFILT2524_COEF25_MASK
- ISPRSZ_VFILT2524_COEF25_SHIFT
- ISPRSZ_VFILT2726
- ISPRSZ_VFILT2726_COEF26_MASK
- ISPRSZ_VFILT2726_COEF26_SHIFT
- ISPRSZ_VFILT2726_COEF27_MASK
- ISPRSZ_VFILT2726_COEF27_SHIFT
- ISPRSZ_VFILT2928
- ISPRSZ_VFILT2928_COEF28_MASK
- ISPRSZ_VFILT2928_COEF28_SHIFT
- ISPRSZ_VFILT2928_COEF29_MASK
- ISPRSZ_VFILT2928_COEF29_SHIFT
- ISPRSZ_VFILT3130
- ISPRSZ_VFILT3130_COEF30_MASK
- ISPRSZ_VFILT3130_COEF30_SHIFT
- ISPRSZ_VFILT3130_COEF31_MASK
- ISPRSZ_VFILT3130_COEF31_SHIFT
- ISPRSZ_VFILT32
- ISPRSZ_VFILT32_COEF2_MASK
- ISPRSZ_VFILT32_COEF2_SHIFT
- ISPRSZ_VFILT32_COEF3_MASK
- ISPRSZ_VFILT32_COEF3_SHIFT
- ISPRSZ_VFILT54
- ISPRSZ_VFILT54_COEF4_MASK
- ISPRSZ_VFILT54_COEF4_SHIFT
- ISPRSZ_VFILT54_COEF5_MASK
- ISPRSZ_VFILT54_COEF5_SHIFT
- ISPRSZ_VFILT76
- ISPRSZ_VFILT76_COEFF6_MASK
- ISPRSZ_VFILT76_COEFF6_SHIFT
- ISPRSZ_VFILT76_COEFF7_MASK
- ISPRSZ_VFILT76_COEFF7_SHIFT
- ISPRSZ_VFILT98
- ISPRSZ_VFILT98_COEFF8_MASK
- ISPRSZ_VFILT98_COEFF8_SHIFT
- ISPRSZ_VFILT98_COEFF9_MASK
- ISPRSZ_VFILT98_COEFF9_SHIFT
- ISPRSZ_VFILT_COEF0_MASK
- ISPRSZ_VFILT_COEF0_SHIFT
- ISPRSZ_VFILT_COEF1_MASK
- ISPRSZ_VFILT_COEF1_SHIFT
- ISPRSZ_YENH
- ISPRSZ_YENH_ALGO_MASK
- ISPRSZ_YENH_ALGO_SHIFT
- ISPRSZ_YENH_CORE_MASK
- ISPRSZ_YENH_CORE_SHIFT
- ISPRSZ_YENH_GAIN_MASK
- ISPRSZ_YENH_GAIN_SHIFT
- ISPRSZ_YENH_SLOP_MASK
- ISPRSZ_YENH_SLOP_SHIFT
- ISPSBL_CCDC_WR_0
- ISPSBL_CCDC_WR_0_DATA_READY
- ISPSBL_CCDC_WR_1
- ISPSBL_CCDC_WR_2
- ISPSBL_CCDC_WR_3
- ISPSBL_PCR
- ISPSBL_PCR_CCDCPRV_2_RSZ_OVF
- ISPSBL_PCR_CCDC_WBL_OVF
- ISPSBL_PCR_CSIA_WBL_OVF
- ISPSBL_PCR_CSIB_WBL_OVF
- ISPSBL_PCR_H3A_AEAWB_WBL_OVF
- ISPSBL_PCR_H3A_AF_WBL_OVF
- ISPSBL_PCR_PRV_WBL_OVF
- ISPSBL_PCR_RSZ1_WBL_OVF
- ISPSBL_PCR_RSZ2_WBL_OVF
- ISPSBL_PCR_RSZ3_WBL_OVF
- ISPSBL_PCR_RSZ4_WBL_OVF
- ISPSBL_SDR_REQ_EXP
- ISPSBL_SDR_REQ_HIST_EXP_MASK
- ISPSBL_SDR_REQ_HIST_EXP_SHIFT
- ISPSBL_SDR_REQ_PRV_EXP_MASK
- ISPSBL_SDR_REQ_PRV_EXP_SHIFT
- ISPSBL_SDR_REQ_RSZ_EXP_MASK
- ISPSBL_SDR_REQ_RSZ_EXP_SHIFT
- ISPSECURE_SECUREMODE
- ISPSSPM0
- ISPSSPM0_ISPSSC_MASK
- ISPSSPM0_ISPSSC_OFFSET
- ISPSSPM0_ISPSSS_MASK
- ISPSSPM0_ISPSSS_OFFSET
- ISPSSPM0_IUNIT_POWER_OFF
- ISPSSPM0_IUNIT_POWER_ON
- ISPSTAT_DISABLED
- ISPSTAT_DISABLING
- ISPSTAT_ENABLED
- ISPSTAT_ENABLING
- ISPSTAT_SUSPENDED
- ISPTCTRL_CTRL_DIVA_MASK
- ISPTCTRL_CTRL_DIVA_SHIFT
- ISPTCTRL_CTRL_DIVB_MASK
- ISPTCTRL_CTRL_DIVB_SHIFT
- ISPTCTRL_CTRL_DIVC_NOCLOCK
- ISPTCTRL_CTRL_DIVC_SHIFT
- ISPTCTRL_CTRL_DIV_BYPASS
- ISPTCTRL_CTRL_DIV_HIGH
- ISPTCTRL_CTRL_DIV_LOW
- ISPTCTRL_CTRL_GRESETDIR
- ISPTCTRL_CTRL_GRESETEn
- ISPTCTRL_CTRL_GRESETPOL
- ISPTCTRL_CTRL_INSEL_CSIA
- ISPTCTRL_CTRL_INSEL_CSIB
- ISPTCTRL_CTRL_INSEL_PARALLEL
- ISPTCTRL_CTRL_INSEL_SHIFT
- ISPTCTRL_CTRL_PSTRBEN
- ISPTCTRL_CTRL_SHUTEN
- ISPTCTRL_CTRL_SHUTPOL
- ISPTCTRL_CTRL_STRBEN
- ISPTCTRL_CTRL_STRBPSTRBPOL
- ISPTCTRL_FRAME_PSTRB_SHIFT
- ISPTCTRL_FRAME_SHUT_SHIFT
- ISPTCTRL_FRAME_STRB_SHIFT
- ISP_AA_COMMAND_START
- ISP_AA_COMMAND_STOP
- ISP_AA_TARGET_AE
- ISP_AA_TARGET_AF
- ISP_AA_TARGET_AWB
- ISP_ADJUST_COMMAND_AUTO
- ISP_ADJUST_COMMAND_MANUAL_ALL
- ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS
- ISP_ADJUST_COMMAND_MANUAL_CONTRAST
- ISP_ADJUST_COMMAND_MANUAL_EXPOSURE
- ISP_ADJUST_COMMAND_MANUAL_HUE
- ISP_ADJUST_COMMAND_MANUAL_SATURATION
- ISP_ADJUST_COMMAND_MANUAL_SHARPNESS
- ISP_ADJUST_ERROR_NONE
- ISP_AFC_COMMAND_AUTO
- ISP_AFC_COMMAND_DISABLE
- ISP_AFC_COMMAND_MANUAL
- ISP_AFC_ERROR_NONE
- ISP_AFC_MANUAL_50HZ
- ISP_AFC_MANUAL_60HZ
- ISP_AF_CONTINUOUS_DISABLE
- ISP_AF_CONTINUOUS_ENABLE
- ISP_AF_ERROR_NONE
- ISP_AF_ERROR_NONE_LOCK_DONE
- ISP_AF_FACE_DISABLE
- ISP_AF_FACE_ENABLE
- ISP_AF_MODE_CONTINUOUS
- ISP_AF_MODE_INIT
- ISP_AF_MODE_MANUAL
- ISP_AF_MODE_SET_CENTER_WINDOW
- ISP_AF_MODE_SET_TOUCH_WINDOW
- ISP_AF_MODE_SINGLE
- ISP_AF_MODE_SLEEP
- ISP_AF_MODE_TOUCH
- ISP_AF_RANGE_MACRO
- ISP_AF_RANGE_NORMAL
- ISP_AF_SLEEP_OFF
- ISP_AF_SLEEP_ON
- ISP_ATIO_Q_IN
- ISP_ATIO_Q_OUT
- ISP_AWB_COMMAND_AUTO
- ISP_AWB_COMMAND_ILLUMINATION
- ISP_AWB_COMMAND_MANUAL
- ISP_AWB_ERROR_NONE
- ISP_AWB_ILLUMINATION_CLOUDY
- ISP_AWB_ILLUMINATION_DAYLIGHT
- ISP_AWB_ILLUMINATION_FLUORESCENT
- ISP_AWB_ILLUMINATION_TUNGSTEN
- ISP_BANK
- ISP_BASE__INST0_SEG0
- ISP_BASE__INST0_SEG1
- ISP_BASE__INST0_SEG2
- ISP_BASE__INST0_SEG3
- ISP_BASE__INST0_SEG4
- ISP_BASE__INST1_SEG0
- ISP_BASE__INST1_SEG1
- ISP_BASE__INST1_SEG2
- ISP_BASE__INST1_SEG3
- ISP_BASE__INST1_SEG4
- ISP_BASE__INST2_SEG0
- ISP_BASE__INST2_SEG1
- ISP_BASE__INST2_SEG2
- ISP_BASE__INST2_SEG3
- ISP_BASE__INST2_SEG4
- ISP_BASE__INST3_SEG0
- ISP_BASE__INST3_SEG1
- ISP_BASE__INST3_SEG2
- ISP_BASE__INST3_SEG3
- ISP_BASE__INST3_SEG4
- ISP_BASE__INST4_SEG0
- ISP_BASE__INST4_SEG1
- ISP_BASE__INST4_SEG2
- ISP_BASE__INST4_SEG3
- ISP_BASE__INST4_SEG4
- ISP_BASE__INST5_SEG0
- ISP_BASE__INST5_SEG1
- ISP_BASE__INST5_SEG2
- ISP_BASE__INST5_SEG3
- ISP_BASE__INST5_SEG4
- ISP_BASE__INST6_SEG0
- ISP_BASE__INST6_SEG1
- ISP_BASE__INST6_SEG2
- ISP_BASE__INST6_SEG3
- ISP_BASE__INST6_SEG4
- ISP_CCP2_MODE_CCP2
- ISP_CCP2_MODE_MIPI
- ISP_CCP2_PHY_DATA_CLOCK
- ISP_CCP2_PHY_DATA_STROBE
- ISP_CFG0_1020
- ISP_CFG0_1020A
- ISP_CFG0_1040
- ISP_CFG0_1040A
- ISP_CFG0_1040B
- ISP_CFG0_1040C
- ISP_CFG0_HWMSK
- ISP_CFG1_BENAB
- ISP_CFG1_F128
- ISP_CFG1_F16
- ISP_CFG1_F32
- ISP_CFG1_F64
- ISP_CFG1_SXP
- ISP_CFG_F
- ISP_CFG_FL
- ISP_CFG_N
- ISP_CFG_NL
- ISP_CLK_CA5
- ISP_CLK_CAM_ICK
- ISP_CLK_CAM_MCLK
- ISP_CLK_CSI2_FCK
- ISP_CLK_FIMC
- ISP_CLK_FIMC_DRC
- ISP_CLK_FIMC_FD
- ISP_CLK_FIMC_SCALERC
- ISP_CLK_FIMC_SCALERP
- ISP_CLK_GIC
- ISP_CLK_I2C0
- ISP_CLK_I2C1
- ISP_CLK_L3_ICK
- ISP_CLK_MCUCTL
- ISP_CLK_MPWM
- ISP_CLK_MTCADC
- ISP_CLK_PWM
- ISP_CLK_SMMU_DRC
- ISP_CLK_SMMU_FD
- ISP_CLK_SMMU_ISP
- ISP_CLK_SMMU_ISPCX
- ISP_CLK_SMMU_SCALERC
- ISP_CLK_SMMU_SCALERP
- ISP_CLK_SPI0
- ISP_CLK_SPI1
- ISP_CLK_UART
- ISP_CLK_WDT
- ISP_CONTROL_BE
- ISP_CONTROL_CI
- ISP_CONTROL_FE
- ISP_CONTROL_FN0_NET
- ISP_CONTROL_FN0_SCSI
- ISP_CONTROL_FN1_NET
- ISP_CONTROL_FN1_SCSI
- ISP_CONTROL_FN_MASK
- ISP_CONTROL_FSR
- ISP_CONTROL_IN
- ISP_CONTROL_LINK_DN_0
- ISP_CONTROL_LINK_DN_1
- ISP_CONTROL_NP_HMCR
- ISP_CONTROL_NP_LRAMCR
- ISP_CONTROL_NP_MASK
- ISP_CONTROL_NP_PCSR
- ISP_CONTROL_NP_PSR
- ISP_CONTROL_PI
- ISP_CONTROL_RI
- ISP_CONTROL_SR
- ISP_CSI2_FRAME_AFTERFEC
- ISP_CSI2_FRAME_IMMEDIATE
- ISP_CSI2_MAX_CTX_NUM
- ISP_CSIPHY1_NUM_DATA_LANES
- ISP_CSIPHY2_NUM_DATA_LANES
- ISP_CTL_REG
- ISP_CTRL
- ISP_DOUT_CA5_ATCLKIN
- ISP_DOUT_CA5_PCLKDBG
- ISP_DOUT_PCLK_ISP_133
- ISP_DOUT_PCLK_ISP_66
- ISP_DOUT_SCLK_MPWM
- ISP_EN_INT
- ISP_EN_RISC
- ISP_FLASH_COMMAND_AUTO
- ISP_FLASH_COMMAND_DISABLE
- ISP_FLASH_COMMAND_MANUAL_ON
- ISP_FLASH_COMMAND_TORCH
- ISP_FLASH_ENABLE
- ISP_FLASH_ERROR_NONE
- ISP_FLASH_REDEYE_DISABLE
- ISP_FLASH_REDEYE_ENABLE
- ISP_FLASH_UPPER
- ISP_HWID
- ISP_IMAGE_EFFECT_DISABLE
- ISP_IMAGE_EFFECT_ERROR_NONE
- ISP_IMAGE_EFFECT_MONOCHROME
- ISP_IMAGE_EFFECT_NEGATIVE_COLOR
- ISP_IMAGE_EFFECT_NEGATIVE_MONO
- ISP_IMAGE_EFFECT_SEPIA
- ISP_IMR_DISABLE_CMPL_INT
- ISP_IMR_DISABLE_PROC_INT
- ISP_IMR_DISABLE_RESET_INT
- ISP_IMR_ENABLE_INT
- ISP_INTERFACE_CCP2B_PHY1
- ISP_INTERFACE_CCP2B_PHY2
- ISP_INTERFACE_CSI2A_PHY2
- ISP_INTERFACE_CSI2C_PHY1
- ISP_INTERFACE_PARALLEL
- ISP_INT_CLR
- ISP_IRIS0_236
- ISP_IRIS0_247
- ISP_IRIS1_234
- ISP_IRIS1_246
- ISP_IRQ0ENABLE
- ISP_IRQ0STATUS
- ISP_IRQ1ENABLE
- ISP_IRQ1STATUS
- ISP_ISO_COMMAND_AUTO
- ISP_ISO_COMMAND_MANUAL
- ISP_ISO_ERROR_NONE
- ISP_MBX_RDY
- ISP_METERING_COMMAND_AVERAGE
- ISP_METERING_COMMAND_CENTER
- ISP_METERING_COMMAND_MATRIX
- ISP_METERING_COMMAND_SPOT
- ISP_METERING_ERROR_NONE
- ISP_MOUT_ISP_266_USER
- ISP_MOUT_ISP_400_USER
- ISP_NR_CLK
- ISP_NVRAM_MASK
- ISP_OF_PHY_CSIPHY1
- ISP_OF_PHY_CSIPHY2
- ISP_OF_PHY_PARALLEL
- ISP_PHY_TYPE_3430
- ISP_PHY_TYPE_3630
- ISP_PING_PONG_ADDR
- ISP_PING_PONG_BUF_SIZE
- ISP_PING_PONG_MEM_RANGE
- ISP_PIPELINE_IDLE_INPUT
- ISP_PIPELINE_IDLE_OUTPUT
- ISP_PIPELINE_QUEUE_INPUT
- ISP_PIPELINE_QUEUE_OUTPUT
- ISP_PIPELINE_STREAM
- ISP_PIPELINE_STREAM_CONTINUOUS
- ISP_PIPELINE_STREAM_INPUT
- ISP_PIPELINE_STREAM_OUTPUT
- ISP_PIPELINE_STREAM_SINGLESHOT
- ISP_PIPELINE_STREAM_STOPPED
- ISP_PLL_CON0
- ISP_PLL_CON1
- ISP_PLL_FREQ_DET
- ISP_PLL_LOCK
- ISP_PRINT_REGISTER
- ISP_QUE_REG
- ISP_REG_DISCONNECT
- ISP_REQ_Q_IN
- ISP_REQ_Q_OUT
- ISP_RESET
- ISP_RESET_CMPL
- ISP_REVISION
- ISP_REVISION_15_0
- ISP_REVISION_1_0
- ISP_REVISION_2_0
- ISP_REVISION_SHIFT
- ISP_RSP_Q_IN
- ISP_RSP_Q_OUT
- ISP_SCENE_AGAINSTLIGHTWLIGHT
- ISP_SCENE_AGAINSTLIGHTWOLIGHT
- ISP_SCENE_BEACHSNOW
- ISP_SCENE_CANDLE
- ISP_SCENE_DAWN
- ISP_SCENE_FALL
- ISP_SCENE_FIRE
- ISP_SCENE_LANDSCAPE
- ISP_SCENE_NIGHT
- ISP_SCENE_NONE
- ISP_SCENE_PARTYINDOOR
- ISP_SCENE_PORTRAIT
- ISP_SCENE_SPORTS
- ISP_SCENE_SUNSET
- ISP_SCENE_TEXT
- ISP_SCLK_SPI0_EXT
- ISP_SCLK_SPI1_EXT
- ISP_SCLK_UART_EXT
- ISP_SECURE
- ISP_SERIAL_PORT_IF_CLK
- ISP_SERIAL_PORT_IF_CS
- ISP_SERIAL_PORT_IF_D0
- ISP_SERIAL_PORT_IF_DI
- ISP_SERIAL_PORT_IF_I2C_MASK
- ISP_SERIAL_PORT_IF_NVR_MASK
- ISP_SERIAL_PORT_IF_SC0
- ISP_SERIAL_PORT_IF_SCE
- ISP_SERIAL_PORT_IF_SCI
- ISP_SERIAL_PORT_IF_SDE
- ISP_SERIAL_PORT_IF_SDI
- ISP_SERIAL_PORT_IF_SDO
- ISP_SERIAL_PORT_IF_WE
- ISP_SHUTTER0_245
- ISP_SHUTTER0_249
- ISP_SHUTTER1_242
- ISP_SHUTTER1_248
- ISP_SOFT_RESET_CMPL
- ISP_SS_PM0
- ISP_STAT_USES_DMAENGINE
- ISP_STOP_TIMEOUT
- ISP_STROBE_124
- ISP_STROBE_250
- ISP_SYSCONFIG
- ISP_SYSCONFIG_AUTOIDLE
- ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY
- ISP_SYSCONFIG_MIDLEMODE_NOSTANBY
- ISP_SYSCONFIG_MIDLEMODE_SHIFT
- ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY
- ISP_SYSCONFIG_SOFTRESET
- ISP_SYSSTATUS
- ISP_SYSSTATUS_RESETDONE
- ISP_TCTRL_CTRL
- ISP_TCTRL_FRAME
- ISP_TCTRL_GRESET_LENGTH
- ISP_TCTRL_PSTRB_DELAY
- ISP_TCTRL_PSTRB_LENGTH
- ISP_TCTRL_PSTRB_REPLAY
- ISP_TCTRL_SHUT_DELAY
- ISP_TCTRL_SHUT_LENGTH
- ISP_TCTRL_STRB_DELAY
- ISP_TCTRL_STRB_LENGTH
- ISP_TOK_TERM
- ISP_VIDEO_DMAQUEUE_QUEUED
- ISP_VIDEO_DMAQUEUE_UNDERRUN
- ISP_VIDEO_DRIVER_NAME
- ISP_VIDEO_DRIVER_VERSION
- ISP_XCLK_A
- ISP_XCLK_B
- ISQ_BUFFER_EVENT
- ISQ_EVENT_MASK
- ISQ_HIST
- ISQ_PORT
- ISQ_RECEIVER_EVENT
- ISQ_RX_MISS_EVENT
- ISQ_TRANSMITTER_EVENT
- ISQ_TX_COL_EVENT
- ISR
- ISR0
- ISR0_AUTONEG
- ISR0_HARDACSCMPLT
- ISR0_OFFSET
- ISR0_RXCMPLT
- ISR0_RXDCMLCK
- ISR0_RXFIFOOVR
- ISR0_RXREJ
- ISR0_TXCMPLT
- ISR1
- ISR1_FORMAT
- ISR2
- ISR2_FORMAT
- ISR3
- ISR4
- ISRAEL
- ISRAEL_HOP_MOD
- ISRAM_SIZE
- ISRAM_START
- ISRC1_EN
- ISRC2_EN
- ISRCTL1_HCRLD
- ISRCTL1_INTPD
- ISRCTL1_PMSK0
- ISRCTL1_PMSK1
- ISRCTL1_RSUPDIS
- ISRCTL1_SCRLD
- ISRCTL1_TSUPDIS
- ISRCTL1_UDPINT
- ISRCTL_HCRLD
- ISRCTL_INTPD
- ISRCTL_PMSK0
- ISRCTL_PMSK1
- ISRCTL_RSUPDIS
- ISRCTL_SCRLD
- ISRCTL_TSUPDIS
- ISRCTL_UDPINT
- ISREG0
- ISRG_RR0
- ISRG_TR0
- ISRX_82XX_RISC_INT
- ISRX_NX_RISC_INT
- ISRX_RISC_INT
- ISR_8723B
- ISR_A
- ISR_AC0DMA
- ISR_ACKNAK
- ISR_ACTX
- ISR_ADDR
- ISR_ALD
- ISR_BCN_TIMER_INTR
- ISR_BED
- ISR_BFP_SC
- ISR_BNTX
- ISR_BUFFER_SIZE
- ISR_BYTE_END
- ISR_CERR_DETECTED
- ISR_CHK
- ISR_CLR_STATUS
- ISR_CMB_RX
- ISR_CMB_TX
- ISR_CMDBUSY_MASK
- ISR_CMD_DONE
- ISR_COMMAND_COMPLETE
- ISR_COMPLETE
- ISR_COMPLETE_M
- ISR_CORRFAIL_ERR
- ISR_COUNTER_READY
- ISR_CRCCO
- ISR_CSQ_NF
- ISR_CSQ_W
- ISR_CTPQ_E
- ISR_DELTA_BREAK_A
- ISR_DELTA_BREAK_B
- ISR_DIS_DMA
- ISR_DIS_INT
- ISR_DIS_SMB
- ISR_DMAR_TO_RST
- ISR_DMAW_TO_RST
- ISR_DPCO
- ISR_DPERR
- ISR_ECC_ERR
- ISR_EMIQ
- ISR_EMPTY
- ISR_ERR
- ISR_ERROR
- ISR_ERR_MASK
- ISR_EXT_INT
- ISR_FATAL
- ISR_FATAL_ERROR
- ISR_FATAL_M
- ISR_FERR_DETECTED
- ISR_FETALERR
- ISR_FIFO_ENABLED
- ISR_FLONI
- ISR_FUIF
- ISR_GCAD
- ISR_GENERIC_IRQ
- ISR_GFC_C0
- ISR_GPHY
- ISR_GPHY_LPW
- ISR_GPIO
- ISR_GPIO0
- ISR_GPIO3
- ISR_HECO
- ISR_HF2
- ISR_HF3
- ISR_HFLD
- ISR_HIBINT
- ISR_HOST_RFD_UNRUN
- ISR_HOST_RRD_OV
- ISR_HOST_RXD_OV
- ISR_HOST_RXF0_OV
- ISR_HOST_RXF1_OV
- ISR_HOST_RXF2_OV
- ISR_HOST_RXF3_OV
- ISR_HOST_TXD_UR
- ISR_HW_RXF_OV
- ISR_IBB
- ISR_IBSS_MERGE
- ISR_INIT
- ISR_INIT_ERR
- ISR_INPUT_PORT_CHANGE
- ISR_INT0
- ISR_INT1
- ISR_INT2
- ISR_INT3
- ISR_INT4
- ISR_INT5
- ISR_INT6
- ISR_INT7
- ISR_INT_BITS_MASK
- ISR_INT_LINE_STATUS
- ISR_INT_MASK
- ISR_INT_MASK_SLOW
- ISR_INT_MDM_STATUS
- ISR_INT_NONE
- ISR_INT_RTS_CTS
- ISR_INT_RXRDY
- ISR_INT_RX_TIMEOUT
- ISR_INT_RX_XOFF
- ISR_INT_STATE_REG
- ISR_INT_TARGET_MASK
- ISR_INT_TARGET_MASK_F1
- ISR_INT_TARGET_MASK_F2
- ISR_INT_TARGET_MASK_F3
- ISR_INT_TARGET_MASK_F4
- ISR_INT_TARGET_MASK_F5
- ISR_INT_TARGET_MASK_F6
- ISR_INT_TARGET_MASK_F7
- ISR_INT_TARGET_STATUS
- ISR_INT_TARGET_STATUS_F1
- ISR_INT_TARGET_STATUS_F2
- ISR_INT_TARGET_STATUS_F3
- ISR_INT_TARGET_STATUS_F4
- ISR_INT_TARGET_STATUS_F5
- ISR_INT_TARGET_STATUS_F6
- ISR_INT_TARGET_STATUS_F7
- ISR_INT_TXRDY
- ISR_INT_VECTOR
- ISR_IRF
- ISR_IRQ1
- ISR_IRQ2
- ISR_IRQ3
- ISR_IRQ5
- ISR_IRQ6
- ISR_IRQ7
- ISR_ISR0
- ISR_ISR1
- ISR_ISR2
- ISR_ISR3
- ISR_IS_LEGACY_INTR_IDLE
- ISR_IS_LEGACY_INTR_TRIGGERED
- ISR_ITE
- ISR_KB
- ISR_LEGACY_INT_TRIGGERED
- ISR_LIF
- ISR_LINK
- ISR_LINK_CHG
- ISR_LINK_DOWN
- ISR_LINK_UP
- ISR_LNKCHNG
- ISR_LPCO
- ISR_LSTEI
- ISR_LSTPEI
- ISR_MAC_RX
- ISR_MAC_TX
- ISR_MANUAL
- ISR_MASK
- ISR_MASK_SLAVE
- ISR_MEASUREEND
- ISR_MEASURESTART
- ISR_MIB
- ISR_MIBFI
- ISR_MIBNEARFULL
- ISR_MISC_FW_ERROR
- ISR_MISC_FW_READY
- ISR_MISC_MBOX_EVT
- ISR_MSI_INT_TRIGGER
- ISR_NACK_ADDR
- ISR_NFERR_DETECTED
- ISR_NOACK_MASK
- ISR_OFFSET
- ISR_OR
- ISR_ORINTR
- ISR_OUT_OF_RANGE
- ISR_OVER
- ISR_OVFI
- ISR_OVR
- ISR_PASS_LIMIT
- ISR_PCI_FTL
- ISR_PEN
- ISR_PHY
- ISR_PHYI
- ISR_PHY_LINKDOWN
- ISR_PME
- ISR_PPRXI
- ISR_PPTXI
- ISR_PRS
- ISR_PRXI
- ISR_PTS
- ISR_PTX0I
- ISR_PTX1I
- ISR_PTX2I
- ISR_PTX3I
- ISR_PTXI
- ISR_PWEI
- ISR_PWM
- ISR_QUIETSTART
- ISR_RACEI
- ISR_RADARDETECT
- ISR_RBRQ0_NF
- ISR_RBRQ0_W
- ISR_RBRQ1_NF
- ISR_RBRQ1_W
- ISR_RBRQ2_NF
- ISR_RBRQ2_W
- ISR_RBRQ3_NF
- ISR_RBRQ3_W
- ISR_READ_COMPLETE_MASK
- ISR_RESERVED_MASK
- ISR_RFD0_UR
- ISR_RFD1_UR
- ISR_RFD2_UR
- ISR_RFD3_UR
- ISR_RFD_UNRUN
- ISR_RISC_INT
- ISR_RMABT
- ISR_ROOS
- ISR_ROS
- ISR_RRD_OV
- ISR_RRIF
- ISR_RS_UPDATE
- ISR_RTABT
- ISR_RTC
- ISR_RWM
- ISR_RX
- ISR_RX0_PAGE_FULL
- ISR_RXDA
- ISR_RXDESC
- ISR_RXDESC0
- ISR_RXDESC1
- ISR_RXDESC2
- ISR_RXDESC3
- ISR_RXDMA0
- ISR_RXDMA1
- ISR_RXDMA_S
- ISR_RXEARLY
- ISR_RXERR
- ISR_RXFO
- ISR_RXF_OV
- ISR_RXIDLE
- ISR_RXINTR
- ISR_RXNOBUF
- ISR_RXOK
- ISR_RXORN
- ISR_RXRCMP
- ISR_RXRDY
- ISR_RXSOVR
- ISR_RXSTLI
- ISR_RXS_OV
- ISR_RXTO
- ISR_RXTOFE
- ISR_RXTOFEINTR
- ISR_RXTOINTR
- ISR_RX_DMA
- ISR_RX_EVENT
- ISR_RX_FULL
- ISR_RX_PKT
- ISR_RX_PKT_0
- ISR_RX_PKT_1
- ISR_RX_PKT_2
- ISR_RX_PKT_3
- ISR_RxCOMPLETE
- ISR_RxFRAMELOST
- ISR_RxOK
- ISR_RxRDY_FFULL_A
- ISR_RxRDY_FFULL_B
- ISR_SAD
- ISR_SAM
- ISR_SCL_TIMEOUT
- ISR_SES_DONE_MASK
- ISR_SHDNI
- ISR_SMB
- ISR_SOFTINT
- ISR_SOFTTIMER
- ISR_SOFTTIMER1
- ISR_SPI
- ISR_SPIM
- ISR_SPIS
- ISR_SRCI
- ISR_SSD
- ISR_SSERR
- ISR_STATUS_M
- ISR_SWI
- ISR_TBRQ_NF
- ISR_TBRQ_W
- ISR_TBTT
- ISR_TERRIF
- ISR_TIMER
- ISR_TMR
- ISR_TMR0I
- ISR_TMR1
- ISR_TMR1I
- ISR_TMR2
- ISR_TS_UPDATE
- ISR_TX
- ISR_TXC
- ISR_TXCINTR
- ISR_TXDESC
- ISR_TXDESC0
- ISR_TXDESC1
- ISR_TXDESC2
- ISR_TXDESC3
- ISR_TXDMA0
- ISR_TXERR
- ISR_TXFE
- ISR_TXFIFOEMPTY_MASK
- ISR_TXFO
- ISR_TXF_UN
- ISR_TXF_UNRUN
- ISR_TXF_UR
- ISR_TXIDLE
- ISR_TXINTR
- ISR_TXOK
- ISR_TXQ_TO_RST
- ISR_TXRCMP
- ISR_TXRDY
- ISR_TXSTLI
- ISR_TXS_OV
- ISR_TXURN
- ISR_TXWB0I
- ISR_TXWB1I
- ISR_TX_BCN_ERR
- ISR_TX_BCN_OK
- ISR_TX_CREDIT
- ISR_TX_DMA
- ISR_TX_EARLY
- ISR_TX_EMPTY
- ISR_TX_EVENT
- ISR_TX_PKT
- ISR_TX_READY
- ISR_TxCOMPLETE
- ISR_TxErr
- ISR_TxOK
- ISR_TxRDY_A
- ISR_TxRDY_B
- ISR_UART
- ISR_UB
- ISR_UDPI
- ISR_UND
- ISR_UNDERRUN
- ISR_UPEC0
- ISR_UR
- ISR_URINTR
- ISR_UR_DETECTED
- ISR_USCEO
- ISR_VPFCO
- ISR_WAITSTOP
- ISR_WATCHDOG
- ISR_WDT
- ISR_WRITE_ALL
- ISR_ZONE
- ISRh_RxErr
- ISS
- ISST_FACT_MAX_BUCKETS
- ISST_IF_API_VERSION
- ISST_IF_CMD_LIMIT
- ISST_IF_DEV_MAX
- ISST_IF_DEV_MBOX
- ISST_IF_DEV_MMIO
- ISST_IF_DRIVER_VERSION
- ISST_IF_GET_PHY_ID
- ISST_IF_GET_PLATFORM_INFO
- ISST_IF_IO_CMD
- ISST_IF_MAGIC
- ISST_IF_MBOX_COMMAND
- ISST_IF_MSR_COMMAND
- ISST_MAX_TDP_LEVELS
- ISST_TRL_MAX_ACTIVE_CORES
- ISSUE_BYTE
- ISSUE_SC
- ISSUPP_11ACENABLED
- ISSUPP_11NENABLED
- ISSUPP_ADHOC_ENABLED
- ISSUPP_BEAMFORMING
- ISSUPP_CHANWIDTH40
- ISSUPP_DRCS_ENABLED
- ISSUPP_FIRMWARE_SUPPLICANT
- ISSUPP_GREENFIELD
- ISSUPP_RANDOM_MAC
- ISSUPP_RXLDPC
- ISSUPP_RXSTBC
- ISSUPP_SDIO_SPA_ENABLED
- ISSUPP_SHORTGI20
- ISSUPP_SHORTGI40
- ISSUPP_TDLS_ENABLED
- ISSUPP_TXSTBC
- ISS_BIT
- ISS_CGIS
- ISS_CLKCTRL
- ISS_CLKCTRL_CCP2
- ISS_CLKCTRL_CSI2_A
- ISS_CLKCTRL_CSI2_B
- ISS_CLKCTRL_ISP
- ISS_CLKCTRL_MASK
- ISS_CLKCTRL_SIMCOP
- ISS_CLKCTRL_VPORT0_CLK
- ISS_CLKCTRL_VPORT1_CLK
- ISS_CLKCTRL_VPORT2_CLK
- ISS_CLKSTAT
- ISS_CLKSTAT_CCP2
- ISS_CLKSTAT_CSI2_A
- ISS_CLKSTAT_CSI2_B
- ISS_CLKSTAT_ISP
- ISS_CLKSTAT_SIMCOP
- ISS_CLKSTAT_VPORT0_CLK
- ISS_CLKSTAT_VPORT1_CLK
- ISS_CLKSTAT_VPORT2_CLK
- ISS_CLKS_MAX
- ISS_CLK_ACLK200
- ISS_CLK_ACLK200_DIV
- ISS_CLK_ACLK400MCUISP
- ISS_CLK_ACLK400MCUISP_DIV
- ISS_CLK_DRC
- ISS_CLK_FD
- ISS_CLK_GICISP
- ISS_CLK_ISP
- ISS_CLK_ISP_DIV0
- ISS_CLK_ISP_DIV1
- ISS_CLK_LITE0
- ISS_CLK_LITE1
- ISS_CLK_MCUCTL_ISP
- ISS_CLK_MCUISP
- ISS_CLK_MCUISP_DIV0
- ISS_CLK_MCUISP_DIV1
- ISS_CLK_MPLL
- ISS_CLK_PPMUISPMX
- ISS_CLK_PPMUISPX
- ISS_CLK_PWM_ISP
- ISS_CLK_UART
- ISS_CSI2_FRAME_AFTERFEC
- ISS_CSI2_FRAME_IMMEDIATE
- ISS_CSI2_MAX_CTX_NUM
- ISS_CSIPHY1_NUM_DATA_LANES
- ISS_CSIPHY2_NUM_DATA_LANES
- ISS_CTRL
- ISS_CTRL_CLK_DIV_MASK
- ISS_CTRL_INPUT_SEL_CSI2A
- ISS_CTRL_INPUT_SEL_CSI2B
- ISS_CTRL_INPUT_SEL_MASK
- ISS_CTRL_SYNC_DETECT_VS_RAISING
- ISS_DPS1
- ISS_DPS10
- ISS_DPS11
- ISS_DPS12
- ISS_DPS13
- ISS_DPS14
- ISS_DPS15
- ISS_DPS2
- ISS_DPS3
- ISS_DPS4
- ISS_DPS5
- ISS_DPS6
- ISS_DPS7
- ISS_DPS8
- ISS_DPS9
- ISS_ES
- ISS_FRS
- ISS_FTS
- ISS_GATE_CLKS_MAX
- ISS_HL_IRQENABLE_CLR
- ISS_HL_IRQENABLE_SET
- ISS_HL_IRQSTATUS
- ISS_HL_IRQSTATUS_RAW
- ISS_HL_IRQ_BTE
- ISS_HL_IRQ_CBUFF
- ISS_HL_IRQ_CCP2
- ISS_HL_IRQ_CSIA
- ISS_HL_IRQ_CSIB
- ISS_HL_IRQ_HS_VS
- ISS_HL_IRQ_ISP
- ISS_HL_IRQ_SIMCOP
- ISS_HL_REVISION
- ISS_HL_SYSCONFIG
- ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE
- ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE
- ISS_HL_SYSCONFIG_IDLEMODE_SHIFT
- ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE
- ISS_HL_SYSCONFIG_SOFTRESET
- ISS_INTERFACE_CSI2A_PHY1
- ISS_INTERFACE_CSI2B_PHY2
- ISS_ISP5_CLKCTRL_MASK
- ISS_MS
- ISS_NET_TIMER_VALUE
- ISS_PIPELINE_IDLE_INPUT
- ISS_PIPELINE_IDLE_OUTPUT
- ISS_PIPELINE_QUEUE_INPUT
- ISS_PIPELINE_QUEUE_OUTPUT
- ISS_PIPELINE_STREAM
- ISS_PIPELINE_STREAM_CONTINUOUS
- ISS_PIPELINE_STREAM_INPUT
- ISS_PIPELINE_STREAM_OUTPUT
- ISS_PIPELINE_STREAM_SINGLESHOT
- ISS_PIPELINE_STREAM_STOPPED
- ISS_PM_STATUS
- ISS_PM_STATUS_BTE_PM_MASK
- ISS_PM_STATUS_CBUFF_PM_MASK
- ISS_PM_STATUS_CCP2_PM_MASK
- ISS_PM_STATUS_CSI2_A_PM_MASK
- ISS_PM_STATUS_CSI2_B_PM_MASK
- ISS_PM_STATUS_ISP_PM_MASK
- ISS_PM_STATUS_SIMCOP_PM_MASK
- ISS_PRINT_REGISTER
- ISS_RFWS
- ISS_TFUS
- ISS_TFWS
- ISS_VIDEO_DMAQUEUE_QUEUED
- ISS_VIDEO_DMAQUEUE_UNDERRUN
- ISS_VIDEO_DRIVER_NAME
- ISS_VIDEO_DRIVER_VERSION
- ISTATE_DEFERRED_CMD
- ISTATE_FREE
- ISTATE_IN_CONNECTION_RECOVERY
- ISTATE_NEW_CMD
- ISTATE_NO_STATE
- ISTATE_RECEIVED_LAST_DATAOUT
- ISTATE_RECEIVED_TASKMGT
- ISTATE_RECEIVE_DATAOUT
- ISTATE_RECEIVE_DATAOUT_RECOVERY
- ISTATE_REMOVE
- ISTATE_SEND_ASYNCMSG
- ISTATE_SEND_DATAIN
- ISTATE_SEND_LAST_DATAIN
- ISTATE_SEND_LAST_R2T
- ISTATE_SEND_LAST_R2T_RECOVERY
- ISTATE_SEND_LOGOUTRSP
- ISTATE_SEND_NOPIN
- ISTATE_SEND_NOPIN_NO_RESPONSE
- ISTATE_SEND_NOPIN_WANT_RESPONSE
- ISTATE_SEND_R2T
- ISTATE_SEND_R2T_RECOVERY
- ISTATE_SEND_REJECT
- ISTATE_SEND_STATUS
- ISTATE_SEND_STATUS_BROKEN_PC
- ISTATE_SEND_STATUS_RECOVERY
- ISTATE_SEND_TASKMGTRSP
- ISTATE_SEND_TEXTRSP
- ISTATE_SENT_ASYNCMSG
- ISTATE_SENT_LAST_DATAIN
- ISTATE_SENT_LAST_R2T
- ISTATE_SENT_LAST_R2T_RECOVERY
- ISTATE_SENT_LOGOUTRSP
- ISTATE_SENT_NOPIN
- ISTATE_SENT_NOPIN_WANT_RESPONSE
- ISTATE_SENT_R2T
- ISTATE_SENT_R2T_RECOVERY
- ISTATE_SENT_REJECT
- ISTATE_SENT_STATUS
- ISTATE_SENT_STATUS_RECOVERY
- ISTATE_SENT_TASKMGTRSP
- ISTATE_SENT_TEXTRSP
- ISTATE_UNSOLICITED_DATA
- ISTATE_WITHIN_DATAOUT_RECOVERY
- ISTAT_DATAE
- ISTAT_DPE
- ISTAT_DSCE
- ISTAT_EMAC
- ISTAT_ERRORS
- ISTAT_LS
- ISTAT_MII_READ
- ISTAT_MII_WRITE
- ISTAT_PME
- ISTAT_RDU
- ISTAT_REG
- ISTAT_RFO
- ISTAT_RX
- ISTAT_TFU
- ISTAT_TO
- ISTAT_TO_SM
- ISTAT_TX
- ISTEMP
- ISTG
- ISTRIP
- ISTR_E_INT
- ISTR_FE_FLG
- ISTR_FF_FLG
- ISTR_INTS
- ISTR_INTX
- ISTR_INT_F
- ISTR_INT_P
- ISTR_OE_INT
- ISTR_UE_INT
- IST_INDEX_DB
- IST_INDEX_DF
- IST_INDEX_MCE
- IST_INDEX_NMI
- ISUPPER
- ISVALID
- ISVOLT
- ISWAPFILE
- ISYMB
- ISYNC_601
- ISYNC_ANY2D_IDLE3D
- ISYNC_ANY3D_IDLE2D
- ISYNC_CNTL
- ISYNC_CPSCRATCH_IDLEGUI
- ISYNC_TRIG2D_IDLE3D
- ISYNC_TRIG3D_IDLE2D
- ISYNC_WAIT_IDLEGUI
- ISYSTEM
- IS_1020
- IS_11N_ENABLED
- IS_11N_MCS_RATE
- IS_11W_ASSOC
- IS_1T1R
- IS_1T2R
- IS_24_DEVICE
- IS_29BIT
- IS_2T2R
- IS_3DES
- IS_7385
- IS_7388
- IS_7395
- IS_7398
- IS_739X
- IS_81XXC
- IS_81XXC_VENDOR_UMC_B_CUT
- IS_8723_SERIES
- IS_8812_SERIES
- IS_8821_SERIES
- IS_888_DEVICE
- IS_92C_1T2R
- IS_92C_SERIAL
- IS_92D
- IS_92D_C_CUT
- IS_92D_D_CUT
- IS_92D_E_CUT
- IS_92D_SINGLEPHY
- IS_9893
- IS_ACCEPTING_CMD
- IS_ADT7468_HFPWM
- IS_ADT7468_OFF64
- IS_AES
- IS_AGA
- IS_AL2230S
- IS_ALIGNED
- IS_ALIVE
- IS_ALL_MSK
- IS_ALOGIO_CAPABLE
- IS_AM_CLASS
- IS_AM_SUBCLASS
- IS_ANT_DETECT_SUPPORT_RSSI
- IS_ANT_DETECT_SUPPORT_SINGLE_TONE
- IS_ANY_T0
- IS_ANY_T1
- IS_APPEND
- IS_AR7010_DEVICE
- IS_ARP
- IS_ASIX
- IS_ASTRO
- IS_ATIO_MSIX_CAPABLE
- IS_ATOMIC_WRITTEN_PAGE
- IS_ATR_PRESENT
- IS_ATR_VALID
- IS_ATTR
- IS_AUTOMOUNT
- IS_AUTOPPS_ACT
- IS_AVAIL1
- IS_AVAIL2
- IS_AVAIL3
- IS_AX88190
- IS_AX88790
- IS_AZALIA
- IS_A_CUT
- IS_A_TT
- IS_BAD_CARD
- IS_BAD_CHIP
- IS_BAD_CSUM
- IS_BAD_LENGTH
- IS_BAD_PKT
- IS_BASTREAM_SETUP
- IS_BB_REG_OFFSET_92S
- IS_BDW_GT3
- IS_BDW_ULT
- IS_BDW_ULX
- IS_BE
- IS_BEIGE
- IS_BIDI_CAPABLE
- IS_BIOS_ENABLED
- IS_BIT
- IS_BITS
- IS_BLOCKED
- IS_BOOMERANG
- IS_BOOTLOADER
- IS_BOTH_COUNTERS_1004K_EVENT
- IS_BOTH_COUNTERS_24K_EVENT
- IS_BOTH_COUNTERS_34K_EVENT
- IS_BOTH_COUNTERS_74K_EVENT
- IS_BOTH_COUNTERS_BMIPS5000_EVENT
- IS_BOTH_COUNTERS_INTERAPTIV_EVENT
- IS_BOTH_COUNTERS_P5600_EVENT
- IS_BOTH_COUNTERS_PROAPTIV_EVENT
- IS_BREAK
- IS_BROADWELL
- IS_BROXTON
- IS_BSR32
- IS_BUFFERED
- IS_BUFFER_POOL
- IS_BUILTIN
- IS_BURST_ONLY4
- IS_BUSY
- IS_BUS_ALIGNED
- IS_BXT
- IS_BXT_REVID
- IS_B_CUT
- IS_CACHED
- IS_CANNONLAKE
- IS_CANONICAL
- IS_CAPTURE_ACTIVE
- IS_CARD_RX_RCVD
- IS_CASEFOLDED
- IS_CBC
- IS_CCK_RATE
- IS_CCM
- IS_CDSA_32
- IS_CDV
- IS_CE1_ADDR
- IS_CFL
- IS_CFL_GT2
- IS_CFL_GT3
- IS_CFL_ULT
- IS_CFL_ULX
- IS_CHAN_2GHZ
- IS_CHAN_5GHZ
- IS_CHAN_A_FAST_CLOCK
- IS_CHAN_HALF_RATE
- IS_CHAN_HT
- IS_CHAN_HT20
- IS_CHAN_HT40
- IS_CHAN_HT40MINUS
- IS_CHAN_HT40PLUS
- IS_CHAN_QUARTER_RATE
- IS_CHAR
- IS_CHECKPOINTED
- IS_CHERRYVIEW
- IS_CHIP_FEATURE
- IS_CHIP_VENDOR_SMIC
- IS_CHIP_VENDOR_TSMC
- IS_CHIP_VENDOR_UMC
- IS_CHIP_VER_B
- IS_CIRRUS
- IS_CLOSE_PG
- IS_CMAC
- IS_CMDAEIRQ
- IS_CMDBEIRQ
- IS_CMDE
- IS_CMDQ_IDLE
- IS_CMD_STAT_HDR
- IS_CMM_ABSENT
- IS_CNA_CAPABLE
- IS_CNL
- IS_CNL_REVID
- IS_CNL_WITH_PORT_F
- IS_COFFEELAKE
- IS_COLD
- IS_COMPLETE
- IS_CONSOLE_IOC3
- IS_COUNT
- IS_COUNTRY_IE_VALID
- IS_CRITICAL_EXC
- IS_CSSA_32
- IS_CT6_SUPPORTED
- IS_CTR
- IS_CURSEC
- IS_CURSEG
- IS_CYCLONE
- IS_C_CUT
- IS_DATAFIRQ
- IS_DATASEG
- IS_DATA_FRAME
- IS_DATA_HDR
- IS_DATBFIRQ
- IS_DATF
- IS_DAVINCI_CPU
- IS_DAX
- IS_DCBX_PFC_PRI_MIX_PAUSE
- IS_DCBX_PFC_PRI_ONLY_NON_PAUSE
- IS_DCBX_PFC_PRI_ONLY_PAUSE
- IS_DCC_BASE
- IS_DC_END
- IS_DC_START
- IS_DEADDIR
- IS_DEBUG_EXC
- IS_DECRYPT
- IS_DEFAULT_HEIGHT
- IS_DEFAULT_WIDTH
- IS_DES
- IS_DESC_64BIT
- IS_DF_HARD_WRITE_PROTECT
- IS_DF_PWR
- IS_DF_SOFT_WRITE_PROTECT
- IS_DIAG_DC
- IS_DIGITAL
- IS_DIMM_PRESENT
- IS_DINODE
- IS_DIRSYNC
- IS_DIRTY
- IS_DISABLED_RUN
- IS_DISCARDING
- IS_DISCONNECTING
- IS_DL10019
- IS_DL10022
- IS_DLERR
- IS_DLREADY
- IS_DMA32
- IS_DMA64
- IS_DMA_DONE
- IS_DMA_ERRATA
- IS_DMA_FINISHED
- IS_DMA_IDLE
- IS_DMA_QM_IDLE
- IS_DMA_USED
- IS_DMA_VALID
- IS_DNODE
- IS_DOT11D_ENABLE
- IS_DPORT_CAPABLE
- IS_DPU_MAJOR_MINOR_SAME
- IS_DRA_CLASS
- IS_DRA_SUBCLASS
- IS_DRA_SUBCLASS_PACKAGE
- IS_DSFORM
- IS_DUAL_DSI
- IS_DUMMY_WRITTEN_PAGE
- IS_DVT
- IS_D_CUT
- IS_E0
- IS_E1
- IS_E1H_OFFSET
- IS_E1H_REG
- IS_E1_REG
- IS_E2_REG
- IS_E3A0_REG
- IS_E3B0_REG
- IS_EARLYPHASE
- IS_ECB
- IS_ECC_ENABLED
- IS_ECS
- IS_EFS
- IS_EFS_MAGIC
- IS_ELKHARTLAKE
- IS_ELROY
- IS_ENABLED
- IS_ENCRYPT
- IS_ENCRYPTED
- IS_EOBIRQ
- IS_EOCIRQ
- IS_EOSIRQ
- IS_EQUAL_CIE_SRC
- IS_ERR
- IS_ERROR_BUSY
- IS_ERROR_DIS_FRAME_END_NOT_DONE
- IS_ERROR_DIS_MSG_FAIL
- IS_ERROR_DIS_PWRDN_FAIL
- IS_ERROR_DRC_ABSENT_INPUT
- IS_ERROR_DRC_ABSENT_OUTPUT
- IS_ERROR_DRC_BITWIDTH_MISMATCH
- IS_ERROR_DRC_FORMAT_MISMATCH
- IS_ERROR_DRC_FRAME_END_NOT_DONE
- IS_ERROR_DRC_FRAME_END_TIME_OUT
- IS_ERROR_DRC_HEIGHT_MISMATCH
- IS_ERROR_DRC_MSG_FAIL
- IS_ERROR_DRC_MULTIPLE_INPUT
- IS_ERROR_DRC_NONADJACENT_INPUT
- IS_ERROR_DRC_NONADJACENT_OUTPUT
- IS_ERROR_DRC_PWRDN_FAIL
- IS_ERROR_DRC_WIDTH_MISMATCH
- IS_ERROR_ENTRY_MSG_THREAD_DOWN
- IS_ERROR_FD_ABSENT_INPUT
- IS_ERROR_FD_MULTIPLE_INPUT
- IS_ERROR_FD_NONADJACENT_INPUT
- IS_ERROR_FD_PWRDN_FAIL
- IS_ERROR_INVALID_COMMAND
- IS_ERROR_INVALID_MAGIC_NUMBER
- IS_ERROR_INVALID_MODE_CHANGE
- IS_ERROR_INVALID_PATH
- IS_ERROR_INVALID_SCENARIO
- IS_ERROR_INVALID_SENSORID
- IS_ERROR_INVALID_SETFILE_HDR
- IS_ERROR_ISP_ABSENT_INPUT
- IS_ERROR_ISP_ABSENT_OUTPUT
- IS_ERROR_ISP_BITWIDTH_MISMATCH
- IS_ERROR_ISP_FORMAT_MISMATCH
- IS_ERROR_ISP_FRAME_END_NOT_DONE
- IS_ERROR_ISP_FRAME_END_TIME_OUT
- IS_ERROR_ISP_HEIGHT_MISMATCH
- IS_ERROR_ISP_MSG_FAIL
- IS_ERROR_ISP_MULTIPLE_INPUT
- IS_ERROR_ISP_NONADJACENT_OUTPUT
- IS_ERROR_ISP_PWRDN_FAIL
- IS_ERROR_ISP_WIDTH_MISMATCH
- IS_ERROR_LHFD_FRAME_END_TIME_OUT
- IS_ERROR_LHFD_INTERNAL_STOP
- IS_ERROR_LHFD_MSG_FAIL
- IS_ERROR_NONE
- IS_ERROR_NO_MSG_IS_RECEIVED
- IS_ERROR_ODC_FRAME_END_NOT_DONE
- IS_ERROR_ODC_MSG_FAIL
- IS_ERROR_ODC_PWRDN_FAIL
- IS_ERROR_OPEN_SENSOR_FAIL
- IS_ERROR_REQUEST_FAIL
- IS_ERROR_SCALERC_FRAME_END_NOT_DONE
- IS_ERROR_SCALERC_MSG_FAIL
- IS_ERROR_SCALERC_PWRDN_FAIL
- IS_ERROR_SCALERP_FRAME_END_NOT_DONE
- IS_ERROR_SCALERP_MSG_FAIL
- IS_ERROR_SCALERP_PWRDN_FAIL
- IS_ERROR_SENSOR_MSG_FAIL
- IS_ERROR_SENSOR_PWRDN_FAIL
- IS_ERROR_SENSOR_STREAM_OFF_FAIL
- IS_ERROR_SENSOR_STREAM_ON_FAIL
- IS_ERROR_SET_PARAMETER
- IS_ERROR_TDNR_FRAME_END_NOT_DONE
- IS_ERROR_TDNR_MSG_FAIL
- IS_ERROR_TDNR_PWRDN_FAIL
- IS_ERROR_TIME_OUT_FLAG
- IS_ERROR_UNKNOWN
- IS_ERROR_VER
- IS_ERROR_WAIT_STREAM_OFF_NOT_DONE
- IS_ERR_MREF
- IS_ERR_MSK
- IS_ERR_OR_NULL
- IS_ERR_VALUE
- IS_ERR_VALUE_U32
- IS_ETH_FP
- IS_EUC_BYTE
- IS_EUC_IBM2JISX0208
- IS_EUC_JISX0201KANA
- IS_EUC_JISX0208
- IS_EUC_UDC_HI
- IS_EUC_UDC_LOW
- IS_EXCHG_OFFLD_CAPABLE
- IS_EXLOGIN_OFFLD_CAPABLE
- IS_EXT2_SB
- IS_EXT3_SB
- IS_EXTENDED
- IS_EXT_REG
- IS_E_CUT
- IS_FAC_REQUIRED
- IS_FALSE_ELSE
- IS_FALSE_MIDDLE
- IS_FALSE_PREFIX
- IS_FALSE_TRAILER
- IS_FAULT_SET
- IS_FAWWN_CAPABLE
- IS_FCOE_FP
- IS_FCOE_IDX
- IS_FD_ARRAY
- IS_FD_HASH
- IS_FD_MAP
- IS_FEC
- IS_FILTER_ENABLED
- IS_FIRST_SOURCE
- IS_FLD_SET
- IS_FLOCK
- IS_FPGA_MAXIMUS_DC
- IS_FREE
- IS_FS155
- IS_FS50
- IS_FSINFO
- IS_FULL
- IS_FWI2_CAPABLE
- IS_FW_81xxC
- IS_FW_HEADER_EXIST
- IS_FW_HEADER_EXIST_8723B
- IS_FW_HEADER_EXIST_8812
- IS_FW_HEADER_EXIST_8821
- IS_G200_SE
- IS_G33
- IS_G45
- IS_G4AGP
- IS_G4DA
- IS_G4X
- IS_GEMINILAKE
- IS_GEN
- IS_GEN9_BC
- IS_GEN9_LP
- IS_GENERAL_ERR_END
- IS_GENERAL_ERR_START
- IS_GEN_I
- IS_GEN_II
- IS_GEN_IIE
- IS_GEN_RANGE
- IS_GERR
- IS_GETLK
- IS_GETLK32
- IS_GETLK64
- IS_GFX_DEVICE
- IS_GIO_DIRECT
- IS_GIO_LOCAL
- IS_GIO_MAPPED
- IS_GLK_REVID
- IS_GM45
- IS_H3A
- IS_H3A_AEWB
- IS_H3A_AF
- IS_HARDWARE_TYPE_8192CE
- IS_HARDWARE_TYPE_8192E
- IS_HARDWARE_TYPE_8192SE
- IS_HARDWARE_TYPE_8723A
- IS_HARDWARE_TYPE_8723B
- IS_HARDWARE_TYPE_8812
- IS_HARDWARE_TYPE_8821
- IS_HARDWARE_TYPE_8822B
- IS_HASWELL
- IS_HDR_BYTE
- IS_HIGHT_PA
- IS_HIGH_SPEED_USB
- IS_HOT
- IS_HSW_EARLY_SDV
- IS_HSW_GT1
- IS_HSW_GT3
- IS_HSW_ULT
- IS_HSW_ULX
- IS_HT_RATE
- IS_HUGE
- IS_HWBLOCKED
- IS_HW_ERR
- IS_I2C_10BIT
- IS_I2C_READY
- IS_I82365A
- IS_I82365B
- IS_I82365DF
- IS_I830
- IS_I845G
- IS_I85X
- IS_I865G
- IS_I915G
- IS_I915GM
- IS_I945G
- IS_I945GM
- IS_I965G
- IS_I965GM
- IS_I9XX
- IS_IALIAS
- IS_IBM
- IS_ICELAKE
- IS_ICL_REVID
- IS_ICL_WITH_PORT_F
- IS_IIDMA_CAPABLE
- IS_IKE
- IS_IMA
- IS_IMAC1
- IS_IMAC2
- IS_IMMEDIATE
- IS_IMMUTABLE
- IS_INDIRECT
- IS_INF
- IS_INITIALIZED
- IS_INODE
- IS_INPUT_APPLICATION
- IS_INTERLINK_SET
- IS_INVREV
- IS_IN_LOW_POWER_STATE
- IS_IN_LOW_POWER_STATE_8821AE
- IS_IN_LOW_POWER_STATE_88E
- IS_IN_LOW_POWER_STATE_92E
- IS_IN_WORK_LIST
- IS_IOMMU_CAP_DOMAIN_IN_CONTAINER
- IS_IP
- IS_IPA
- IS_IPA_REPLY
- IS_IPV4_UNUSABLE_ADDRESS
- IS_IPV6
- IS_IQD
- IS_IRONLAKE
- IS_IRONLAKE_M
- IS_IRQ_MST_ERR
- IS_IRQ_SENSOR
- IS_IRQ_STAT
- IS_IRQ_SW
- IS_IRQ_TIST_OV
- IS_ISA_DEVICE
- IS_ISDN
- IS_ISDN_P_E1
- IS_ISDN_P_NT
- IS_ISDN_P_S0
- IS_ISDN_P_TE
- IS_ISDN_P_UP0
- IS_ISP1040
- IS_ISP1x160
- IS_ISP1x40
- IS_ITDB_VALID
- IS_IVB_GT1
- IS_IVYBRIDGE
- IS_IWARP
- IS_I_CUT
- IS_I_VERSION
- IS_JSRI32
- IS_J_CUT
- IS_KABYLAKE
- IS_KBL_GT2
- IS_KBL_GT3
- IS_KBL_REVID
- IS_KBL_ULT
- IS_KBL_ULX
- IS_KERNEL
- IS_KERNEL_TEXT
- IS_KSEG1
- IS_K_CUT
- IS_LARGE_AREA
- IS_LASAT_200
- IS_LAST_ENTRY
- IS_LAST_SECTOR_IN_CLUSTER
- IS_LAST_SOURCE
- IS_LAYER2
- IS_LAYER3
- IS_LE
- IS_LEAD_HWFN
- IS_LEAF
- IS_LEAP_YEAR
- IS_LEASE
- IS_LED_BLINKING
- IS_LED_WPS_BLINKING
- IS_LEN
- IS_LITTLE_ENDIAN
- IS_LNK_SYNC_M1
- IS_LNK_SYNC_M2
- IS_LOCAL_LIST_TYPE
- IS_LOCAL_TLB_FLUSH
- IS_LOCKSTEP_ENABLED
- IS_LOMBARD
- IS_LOW512
- IS_LOWER_PORT
- IS_LP
- IS_LTSSM_UP
- IS_LVDS
- IS_M1_PAR_ERR
- IS_M2M
- IS_M2_PAR_ERR
- IS_MAC1
- IS_MAC2
- IS_MANAGMEMENT
- IS_MANAGMEMENT_CALLBACK
- IS_MANDLOCK
- IS_MAPPABLE_UNCACHEABLE
- IS_MASK
- IS_MASTER_DSI_LINK
- IS_MCAST
- IS_MCHECK_EXC
- IS_MCTP_CAPABLE
- IS_MERCURY
- IS_METERING_CONFIG_CMD
- IS_METERING_CONFIG_MAX
- IS_METERING_CONFIG_WIN_HEIGHT
- IS_METERING_CONFIG_WIN_POS_X
- IS_METERING_CONFIG_WIN_POS_Y
- IS_METERING_CONFIG_WIN_WIDTH
- IS_MF
- IS_MFC51_PRIV
- IS_MFCV10
- IS_MFCV6_PLUS
- IS_MFCV6_V2
- IS_MFCV7_PLUS
- IS_MFCV8_PLUS
- IS_MFLD
- IS_MF_AFEX
- IS_MF_BD
- IS_MF_FCOE_AFEX
- IS_MF_FCOE_SD
- IS_MF_ISCSI_ONLY
- IS_MF_ISCSI_SD
- IS_MF_ISCSI_SI
- IS_MF_PERCENT_BW
- IS_MF_SD
- IS_MF_SD_STORAGE_PERSONALITY_ONLY
- IS_MF_SI
- IS_MF_SI_STORAGE_PERSONALITY_ONLY
- IS_MF_STORAGE_ONLY
- IS_MF_STORAGE_PERSONALITY_ONLY
- IS_MF_UFP
- IS_MGMT_STATUS_SUCCES
- IS_MINTR1
- IS_MINTR2
- IS_MINTR3
- IS_MIO_IOC3
- IS_MIO_PRESENT
- IS_MIRRORED
- IS_MIRROR_ENABLED
- IS_MME_CMDQ_IDLE
- IS_MME_IDLE
- IS_MME_QM_IDLE
- IS_MNT_LOCKED
- IS_MNT_MARKED
- IS_MNT_NEW
- IS_MNT_SHARED
- IS_MNT_SLAVE
- IS_MNT_UNBINDABLE
- IS_MOBILE
- IS_MOBILITY
- IS_MODULE
- IS_MPC
- IS_MPCDEV
- IS_MPUIRQ
- IS_MQUE_CAPABLE
- IS_MRST
- IS_MSGBYTESENT
- IS_MSIX_NACK_CAPABLE
- IS_MSM8996_TARGET
- IS_MSM8998_TARGET
- IS_MTK_HSDMA_VDESC_FINISHED
- IS_MTMSRD
- IS_MV300
- IS_MX23
- IS_MX28
- IS_MX6Q
- IS_MX6SX
- IS_MX7D
- IS_M_RX_FIFO_FULL_SHIFT
- IS_M_RX_THLD_SHIFT
- IS_M_START_BUSY_SHIFT
- IS_M_TX_UNDERRUN_SHIFT
- IS_NAME_NTH
- IS_NEW_GENERATION_IC
- IS_NOATIME
- IS_NOCACHE_VPD_TYPE
- IS_NOCMTIME
- IS_NODESEG
- IS_NONCONTIG_BUFFER
- IS_NOPOLLING_TYPE
- IS_NOQUOTA
- IS_NORMAL_CHIP
- IS_NORMAL_CHIP92D
- IS_NOSEC
- IS_NOTCOMMAND
- IS_NOT_PRINTABLE
- IS_NO_STAT_M1
- IS_NO_STAT_M2
- IS_NO_TIST_M1
- IS_NO_TIST_M2
- IS_NULL_REG
- IS_NVA3F
- IS_NVAAF
- IS_NVDIMM_PRESENT
- IS_OCS
- IS_OEM_001
- IS_OFDLCK
- IS_OFDM_RATE
- IS_OFFSET
- IS_OMAP_CLASS
- IS_OMAP_SUBCLASS
- IS_OMAP_TYPE
- IS_OPERATIONAL
- IS_OPERATIONAL_ERR
- IS_ORDINAL_TABLE_ONE
- IS_ORDINAL_TABLE_TWO
- IS_OSD
- IS_OSM
- IS_OSN
- IS_OSX
- IS_OUTSIDE
- IS_OUT_OF_BOUNDS
- IS_OVERLAY_ACTIVE
- IS_P2P_SOCIAL_CHANNEL
- IS_P3P_TYPE
- IS_PANCOORD
- IS_PASS_ELSE
- IS_PASS_MIDDLE
- IS_PA_TO_RX1
- IS_PA_TO_RX2
- IS_PA_TO_TX1
- IS_PA_TO_TX2
- IS_PCI32_DIRECT
- IS_PCI32_LOCAL
- IS_PCI32_MAPPED
- IS_PCI64
- IS_PCIE
- IS_PD6710
- IS_PD672X
- IS_PDEV
- IS_PF
- IS_PF_SRIOV
- IS_PF_SRIOV_ALLOC
- IS_PHASE_DECLARATIVE
- IS_PHASE_FFP0
- IS_PHASE_OPERATIONAL
- IS_PHASE_SECURITY
- IS_PHY_IF_MODE_GBIT
- IS_PHY_IF_MODE_RGMII
- IS_PINEVIEW
- IS_PI_DIFB_DIX0_CAPABLE
- IS_PI_IPGUARD_CAPABLE
- IS_PI_SPLIT_DET_CAPABLE
- IS_PI_SPLIT_DET_CAPABLE_HBA
- IS_PI_UNINIT_CAPABLE
- IS_PLANAR
- IS_PLATFORM
- IS_PLINT1
- IS_PLINT2
- IS_PLUTO
- IS_PM34XX_ERRATUM
- IS_PM44XX_ERRATUM
- IS_PM5500
- IS_PM7500
- IS_PORT_1
- IS_PORT_2
- IS_PORT_STAT
- IS_POS
- IS_POSIX
- IS_POSIXACL
- IS_POW2
- IS_POW2PS
- IS_POWER_OF_2
- IS_PREALLOC
- IS_PRIVATE
- IS_PROCBYTE_PRESENT
- IS_PROT_IO
- IS_PSB
- IS_PSEUDO
- IS_PSTATE_ACCEPTOR
- IS_PSTATE_IRRELEVANT
- IS_PSTATE_NEGOTIATE
- IS_PSTATE_PROPOSER
- IS_PSTATE_REJECT
- IS_PSTATE_REPLY_OPTIONAL
- IS_PSTATE_RESPONSE_GOT
- IS_PSTATE_RESPONSE_SENT
- IS_QED_ETH_IF
- IS_QED_FCOE_IF
- IS_QED_MULTI_TC_ROCE
- IS_QED_SRIOV
- IS_QLA2031
- IS_QLA2071
- IS_QLA2081
- IS_QLA2100
- IS_QLA2200
- IS_QLA2261
- IS_QLA2271
- IS_QLA2281
- IS_QLA2300
- IS_QLA2312
- IS_QLA2322
- IS_QLA23XX
- IS_QLA2422
- IS_QLA2432
- IS_QLA24XX
- IS_QLA24XX_TYPE
- IS_QLA2532
- IS_QLA25XX
- IS_QLA27XX
- IS_QLA28XX
- IS_QLA2XXX_MIDTYPE
- IS_QLA5422
- IS_QLA5432
- IS_QLA54XX
- IS_QLA6312
- IS_QLA6322
- IS_QLA8001
- IS_QLA8031
- IS_QLA8044
- IS_QLA81XX
- IS_QLA82XX
- IS_QLA83XX
- IS_QLA8432
- IS_QLA84XX
- IS_QLAFX00
- IS_QLC_83XX_USED
- IS_QME
- IS_QMH
- IS_QM_IDLE
- IS_QOS_QUEUE
- IS_QUICKSILVER
- IS_R1_B
- IS_R1_C
- IS_R1_F
- IS_R1_P
- IS_R1_PAR_ERR
- IS_R2_B
- IS_R2_C
- IS_R2_F
- IS_R2_P
- IS_R2_PAR_ERR
- IS_R300_VARIANT
- IS_RAID_CH
- IS_RAM_RD_PAR
- IS_RAM_WR_PAR
- IS_RANGE_P_1004K_EVENT
- IS_RANGE_P_34K_EVENT
- IS_RANGE_P_INTERAPTIV_EVENT
- IS_RANGE_V_1004K_EVENT
- IS_RANGE_V_34K_EVENT
- IS_RANGE_V_INTERAPTIV_EVENT
- IS_RCVAVAIL_END
- IS_RCVAVAIL_START
- IS_RCVURGENT_END
- IS_RCVURGENT_START
- IS_RC_MSK
- IS_RC_SHIFT
- IS_RDLH_LINK_UP
- IS_RDONLY
- IS_REACHABLE
- IS_READY
- IS_REGISTERED
- IS_REG_2ND_BANK
- IS_REG_IN_PRESET
- IS_REMOTELCK
- IS_RESCHEDULE
- IS_RESERVED_END
- IS_RESERVED_START
- IS_RESPONSE
- IS_RESTORE_INHIBIT
- IS_RETRY_ENABLED
- IS_REVID
- IS_REV_A
- IS_RF5Cx96
- IS_RFI
- IS_RFID
- IS_RIR_VALID
- IS_ROCE
- IS_ROOT
- IS_RUN_COMMAND_ERR
- IS_RV100_VARIANT
- IS_RW_PRIORITY
- IS_RX
- IS_RX_ERROR
- IS_SAMSUNG_CPU
- IS_SBIRQ
- IS_SCOPE_CONNECTION_ONLY
- IS_SCOPE_SESSION_WIDE
- IS_SCRBALGO_ENHANCED
- IS_SCSI_READ_WRITE
- IS_SC_CAPTURE_STILL
- IS_SC_CAPTURE_VIDEO
- IS_SC_MAX
- IS_SC_PREVIEW_STILL
- IS_SC_PREVIEW_VIDEO
- IS_SC_SUB_CS_VTCALL
- IS_SC_SUB_CV_VTCALL
- IS_SC_SUB_DEFAULT
- IS_SC_SUB_PS_VTCALL
- IS_SC_SUB_PV_VTCALL
- IS_SDM670_TARGET
- IS_SDM845_TARGET
- IS_SDM855_TARGET
- IS_SDMAENG_ERR_END
- IS_SDMAENG_ERR_START
- IS_SDMA_END
- IS_SDMA_IDLE_END
- IS_SDMA_IDLE_START
- IS_SDMA_PROGRESS_END
- IS_SDMA_PROGRESS_START
- IS_SDMA_START
- IS_SDVOB
- IS_SECCOMP_EVENT
- IS_SELARB
- IS_SENDCREDIT_END
- IS_SENDCREDIT_START
- IS_SENDCTXT_ERR_END
- IS_SENDCTXT_ERR_START
- IS_SENDER_BOTH
- IS_SENDER_INITIATOR
- IS_SENDER_TARGET
- IS_SENSOR_CTRL_BUS_I2C0
- IS_SENSOR_CTRL_BUS_I2C1
- IS_SETHI
- IS_SETLK
- IS_SETLK32
- IS_SETLK64
- IS_SETLKW
- IS_SETLKW32
- IS_SETLKW64
- IS_SG64_ADDR
- IS_SHA
- IS_SHA1
- IS_SHA1_HMAC
- IS_SHA256
- IS_SHA256_HMAC
- IS_SHADOW_REG_CAPABLE
- IS_SHA_HMAC
- IS_SHIFT
- IS_SHORT_READ
- IS_SIGNIFICANT_DIFF
- IS_SIM
- IS_SINGLE_MODE
- IS_SINK
- IS_SIS330
- IS_SIS550
- IS_SIS550650740
- IS_SIS550650740660
- IS_SIS650
- IS_SIS650740
- IS_SIS650740660
- IS_SIS651
- IS_SIS65x
- IS_SIS660
- IS_SIS661
- IS_SIS661741660760
- IS_SIS740
- IS_SIS741
- IS_SIS760
- IS_SIS761
- IS_SISM650
- IS_SJIS_IBM
- IS_SJIS_JISX0201KANA
- IS_SJIS_JISX0208
- IS_SJIS_LOW_BYTE
- IS_SJIS_NECIBM
- IS_SJIS_UDC_HI
- IS_SJIS_UDC_LOW
- IS_SKL_GT2
- IS_SKL_GT3
- IS_SKL_GT4
- IS_SKL_REVID
- IS_SKL_ULT
- IS_SKL_ULX
- IS_SKYLAKE
- IS_SMC
- IS_SMLH_LINK_UP
- IS_SMP
- IS_SOC
- IS_SOF
- IS_SPCV_12G
- IS_SPROCKETS
- IS_SRC
- IS_SRIOV
- IS_SS4PLUS_DEV
- IS_SS_DISABLED
- IS_SS_ID_2U
- IS_SS_ID_MU
- IS_SS_ID_NU
- IS_SS_ID_VER_14
- IS_SS_ID_XGBE
- IS_STARTED
- IS_START_OF_FRAME
- IS_STA_VALID
- IS_ST_A5_PWR_ON
- IS_ST_BLOCK_CMD_CLEARED
- IS_ST_CHANGE_MODE
- IS_ST_END
- IS_ST_FW_LOADED
- IS_ST_IDLE
- IS_ST_INIT_DONE
- IS_ST_OPEN_SENSOR
- IS_ST_PWR_ON
- IS_ST_PWR_SUBIP_ON
- IS_ST_SETFILE_LOADED
- IS_ST_SET_ZOOM
- IS_ST_STREAM_OFF
- IS_ST_STREAM_ON
- IS_SUBPLATFORM
- IS_SUPPORT_MULTI_BANDS
- IS_SWAPFILE
- IS_SWBLOCKED
- IS_SW_RESV_ADDR
- IS_SYNC
- IS_SYNC_CODE
- IS_SYNC_NEEDED
- IS_S_RD_EVENT_SHIFT
- IS_S_RX_EVENT_SHIFT
- IS_S_RX_FIFO_FULL_SHIFT
- IS_S_RX_THLD_SHIFT
- IS_S_START_BUSY_SHIFT
- IS_S_TX_UNDERRUN_SHIFT
- IS_T10_PI_CAPABLE
- IS_T32
- IS_TD
- IS_TDI
- IS_TEST_CHIP
- IS_TE_ENABLED
- IS_TGT_MODE_CAPABLE
- IS_TIGERLAKE
- IS_TIMER0
- IS_TIMER1
- IS_TIMER_BOT
- IS_TIMER_TOP
- IS_TIMINT
- IS_TI_CLASS
- IS_TI_SUBCLASS
- IS_TMDS
- IS_TMO
- IS_TNODE
- IS_TOKEN
- IS_TORNADO
- IS_TO_PORT1
- IS_TO_PORT2
- IS_TPC_CMDQ_IDLE
- IS_TPC_IDLE
- IS_TPC_QM_IDLE
- IS_TRIE
- IS_TRUE_ELSE
- IS_TRUE_MIDDLE
- IS_TRUE_PREFIX
- IS_TSO_HEADER
- IS_TV
- IS_TV_OR_LVDS
- IS_TW
- IS_TWI
- IS_TWOPORT
- IS_TX
- IS_TX_ERROR
- IS_TYPE
- IS_TYPERANGE_0_TO_2
- IS_TYPERANGE_0_TO_32767
- IS_TYPERANGE_0_TO_3600
- IS_TYPERANGE_0_TO_65535
- IS_TYPERANGE_1_TO_65535
- IS_TYPERANGE_2_TO_3600
- IS_TYPERANGE_512_TO_16777215
- IS_TYPERANGE_AUTH_PARAM
- IS_TYPERANGE_DIGEST_PARAM
- IS_TYPERANGE_SESSIONTYPE
- IS_TYPE_BOOL_AND
- IS_TYPE_BOOL_OR
- IS_TYPE_NUMBER
- IS_TYPE_NUMBER_RANGE
- IS_TYPE_STRING
- IS_TYPE_VALUE_LIST
- IS_UBWC_20_SUPPORTED
- IS_UC
- IS_UDPLITE
- IS_UI
- IS_UNALIGNED
- IS_UNDEFINED
- IS_UNDERLAY_CONTROLLER
- IS_UNICODE
- IS_UNKNOWN
- IS_UNSLIRQ
- IS_UNSUP
- IS_USB_DEVICE
- IS_USB_START
- IS_USB_STOP
- IS_USED_CFG
- IS_USED_RUN
- IS_USE_ALL
- IS_USE_INITIAL_ONLY
- IS_USE_LEADING_ONLY
- IS_UVERBS_COPY_ERR
- IS_V1
- IS_V3
- IS_V4
- IS_VADEM
- IS_VALID_APP
- IS_VALID_BW
- IS_VALID_VLAN
- IS_VALLEYVIEW
- IS_VARIOUS_END
- IS_VARIOUS_START
- IS_VENDOR_8723A_B_CUT
- IS_VENDOR_8723_A_CUT
- IS_VENDOR_8812A_C_CUT
- IS_VENDOR_8812A_MP_CHIP
- IS_VENDOR_8812A_TEST_CHIP
- IS_VENDOR_8821A_B_CUT
- IS_VENDOR_8821A_MP_CHIP
- IS_VENDOR_8821A_TEST_CHIP
- IS_VENDOR_UMC
- IS_VENDOR_UMC_A_CUT
- IS_VERITY
- IS_VF
- IS_VF_FLAG
- IS_VG468
- IS_VG469
- IS_VGA
- IS_VGIC_ADDR_UNDEF
- IS_VG_PWR
- IS_VHT_RATE
- IS_VIA
- IS_VLSI
- IS_VM_NIC
- IS_VOODOO2
- IS_VORTEX
- IS_VT1636
- IS_VT83C469
- IS_WARM
- IS_WC
- IS_WDLM
- IS_WHITEOUT
- IS_WIRELESS_MODE_A
- IS_WIRELESS_MODE_B
- IS_WIRELESS_MODE_G
- IS_WIRELESS_MODE_N_24G
- IS_WIRELESS_MODE_N_5G
- IS_WORD_16
- IS_XA1_B
- IS_XA1_C
- IS_XA1_F
- IS_XA2_B
- IS_XA2_C
- IS_XA2_F
- IS_XATTR_LAST_ENTRY
- IS_XA_B
- IS_XA_C
- IS_XA_F
- IS_XFORM
- IS_XL
- IS_XS1_B
- IS_XS1_C
- IS_XS1_F
- IS_XS2_B
- IS_XS2_C
- IS_XS2_F
- IS_XS_B
- IS_XS_C
- IS_XS_F
- IS_XTS
- IS_ZERO
- IS_ZIO_SUPPORTED
- IT
- IT8152_AUDIO_INT
- IT8152_CDMA_INT
- IT8152_CFGREG_BASE
- IT8152_GPIO_GPDR
- IT8152_H2PMAR
- IT8152_H2PTADR
- IT8152_INTC_INTC_TYPER
- IT8152_INTC_LDCNIMR
- IT8152_INTC_LDCNIRR
- IT8152_INTC_LDNIAR
- IT8152_INTC_LDNITR
- IT8152_INTC_LDPNIMR
- IT8152_INTC_LDPNIRR
- IT8152_INTC_LPCNIMR
- IT8152_INTC_LPCNIRR
- IT8152_INTC_LPNIAR
- IT8152_INTC_LPNITR
- IT8152_INTC_LPPNIMR
- IT8152_INTC_LPPNIRR
- IT8152_INTC_PDCNIMR
- IT8152_INTC_PDCNIRR
- IT8152_INTC_PDNIAR
- IT8152_INTC_PDNITR
- IT8152_INTC_PDPNIMR
- IT8152_INTC_PDPNIRR
- IT8152_IO_BASE
- IT8152_IRQ
- IT8152_LAST_IRQ
- IT8152_LD_IRQ
- IT8152_LD_IRQ_COUNT
- IT8152_LP_IRQ
- IT8152_LP_IRQ_COUNT
- IT8152_PCISERR
- IT8152_PCI_CFG_ADDR
- IT8152_PCI_CFG_DATA
- IT8152_PCI_INTA
- IT8152_PCI_INTB
- IT8152_PCI_INTC
- IT8152_PCI_INTD
- IT8152_PD_IRQ
- IT8152_PD_IRQ_COUNT
- IT8152_USB_INT
- IT85_BRCM
- IT85_C0BDHR
- IT85_C0BDLR
- IT85_C0CFR
- IT85_C0DR
- IT85_C0IER
- IT85_C0IIR
- IT85_C0MSTCR
- IT85_C0RCR
- IT85_C0RFSR
- IT85_C0SCK
- IT85_C0TCR
- IT85_C0TFSR
- IT85_C0WCL
- IT85_C0WCR
- IT85_C0WPS
- IT85_CFQ
- IT85_CIRPOII
- IT85_CIRPOIS
- IT85_CIRPOSIE
- IT85_DLL1P8E
- IT85_DLLOCK
- IT85_DLLTE
- IT85_FIFOCLR
- IT85_FIFOTL
- IT85_FIFOTL_DEFAULT
- IT85_HCFS
- IT85_IEC
- IT85_ILE
- IT85_ILSEL
- IT85_IOREG_LENGTH
- IT85_NIP
- IT85_RCRST
- IT85_RDAI
- IT85_RDAIE
- IT85_RDWOS
- IT85_RESET
- IT85_RFOI
- IT85_RFOIE
- IT85_RXACT
- IT85_RXDCR
- IT85_RXEN
- IT85_RXEND
- IT85_RXFBC
- IT85_RXFTO
- IT85_SCKS
- IT85_TLDLI
- IT85_TLDLIE
- IT85_TXDCKG
- IT85_TXENDF
- IT85_TXFBC
- IT85_TXMPM
- IT85_TXMPM_DEFAULT
- IT85_TXMPW
- IT85_TXMPW_DEFAULT
- IT85_TXRLE
- IT85_WCL
- IT85_WCRST
- IT8603E_DEVID
- IT8607_ID
- IT8613_ID
- IT8620E_DEVID
- IT8620_ID
- IT8622E_DEVID
- IT8622_ID
- IT8623E_DEVID
- IT8625_ID
- IT8628E_DEVID
- IT8628_ID
- IT8655_ID
- IT8665_ID
- IT8686_ID
- IT8702_ID
- IT8705F_DEVID
- IT8705_ID
- IT8708_BANKSEL
- IT8708_C0BDHR
- IT8708_C0BDLR
- IT8708_C0CFR
- IT8708_C0DR
- IT8708_C0IER
- IT8708_C0IIR
- IT8708_C0MSTCR
- IT8708_C0RCR
- IT8708_C0RFSR
- IT8708_C0SCK
- IT8708_C0TCR
- IT8708_C0TFSR
- IT8708_C0WCL
- IT8708_C0WCR
- IT8708_C0WPS
- IT8708_CGPINT
- IT8708_CGPINTR
- IT8708_CSCRR
- IT8708_CSCRR_PM
- IT8708_CSCRR_SCRB
- IT8708_HRAE
- IT8708_IOREG_LENGTH
- IT8709_FIFO
- IT8709_IDLE
- IT8709_IIR
- IT8709_IOREG_LENGTH
- IT8709_MODE
- IT8709_RAM_IDX
- IT8709_RAM_VAL
- IT8709_READ
- IT8709_REG_IDX
- IT8709_REG_VAL
- IT8709_RFSR
- IT8709_WRITE
- IT8712F_DEVID
- IT8712_ID
- IT8716F_DEVID
- IT8716_ID
- IT8718F_DEVID
- IT8718_ID
- IT8720F_DEVID
- IT8720_ID
- IT8721F_DEVID
- IT8721_ID
- IT8726F_DEVID
- IT8726_ID
- IT8728F_DEVID
- IT8728_ID
- IT8732F_DEVID
- IT8732_ID
- IT8761_ID
- IT8771E_DEVID
- IT8772E_DEVID
- IT8772_ID
- IT8781F_DEVID
- IT8782F_DEVID
- IT8783E_DEVID
- IT8783_ID
- IT8786E_DEVID
- IT8786_ID
- IT8790E_DEVID
- IT8792E_DEVID
- IT87_ACT_REG
- IT87_ADDR_REG_OFFSET
- IT87_BASE_REG
- IT87_BDHR
- IT87_BDLR
- IT87_BR
- IT87_CFQ
- IT87_CFQ_SHIFT
- IT87_DATA_REG_OFFSET
- IT87_DR
- IT87_EC_EXTENT
- IT87_EC_OFFSET
- IT87_EXTENT
- IT87_FIFOCLR
- IT87_FIFOTL
- IT87_FIFOTL_DEFAULT
- IT87_HCFS
- IT87_IEC
- IT87_IER
- IT87_II
- IT87_IIR
- IT87_II_NOINT
- IT87_II_RXDS
- IT87_II_RXFO
- IT87_II_TXLDL
- IT87_ILE
- IT87_IOREG_LENGTH
- IT87_IP
- IT87_RCR
- IT87_RDAIE
- IT87_RDWOS
- IT87_REG_ALARM1
- IT87_REG_ALARM2
- IT87_REG_ALARM3
- IT87_REG_AUTO_PWM
- IT87_REG_AUTO_TEMP
- IT87_REG_BEEP_ENABLE
- IT87_REG_CHIPID
- IT87_REG_CONFIG
- IT87_REG_FAN_16BIT
- IT87_REG_FAN_CTL
- IT87_REG_FAN_DIV
- IT87_REG_FAN_MAIN_CTRL
- IT87_REG_TEMP
- IT87_REG_TEMP456_ENABLE
- IT87_REG_TEMP_ENABLE
- IT87_REG_TEMP_EXTRA
- IT87_REG_TEMP_HIGH
- IT87_REG_TEMP_LOW
- IT87_REG_VID
- IT87_REG_VIN_ENABLE
- IT87_REG_VIN_MAX
- IT87_REG_VIN_MIN
- IT87_RESET
- IT87_RFOIE
- IT87_RSR
- IT87_RXACT
- IT87_RXDCR
- IT87_RXEN
- IT87_RXEND
- IT87_RXFBC
- IT87_RXFTO
- IT87_SIO_BEEP_PIN_REG
- IT87_SIO_GPIO1_REG
- IT87_SIO_GPIO2_REG
- IT87_SIO_GPIO3_REG
- IT87_SIO_GPIO4_REG
- IT87_SIO_GPIO5_REG
- IT87_SIO_PINX1_REG
- IT87_SIO_PINX2_REG
- IT87_SIO_SPI_REG
- IT87_SIO_VID_REG
- IT87_TCR1
- IT87_TCR2
- IT87_TLDLIE
- IT87_TSR
- IT87_TXENDF
- IT87_TXFBC
- IT87_TXMPM
- IT87_TXMPM_DEFAULT
- IT87_TXMPW
- IT87_TXMPW_DEFAULT
- IT87_TXRLE
- IT913X_H
- IT913X_ROLE_DUAL_MASTER
- IT913X_ROLE_DUAL_SLAVE
- IT913X_ROLE_SINGLE
- ITA
- ITAB_NUM
- ITAPDLY
- ITAPDLY_EN
- ITAP_DELAY
- ITAR_DISC
- ITBINV
- ITBS16
- ITBS32
- ITCCHEN
- ITCINTEN
- ITCM_CK
- ITCM_OFFSET
- ITCO_WDT_PM_OPS
- ITCR
- ITCT_BASE_ADDR_HI
- ITCT_BASE_ADDR_LO
- ITCT_CLR
- ITCT_CLR_EN_MSK
- ITCT_CLR_EN_OFF
- ITCT_DEV_MSK
- ITCT_DEV_OFF
- ITCT_HDR_AWT_CONTINUE_OFF
- ITCT_HDR_AWT_CONTROL_MSK
- ITCT_HDR_AWT_CONTROL_OFF
- ITCT_HDR_BITLT_MSK
- ITCT_HDR_BITLT_OFF
- ITCT_HDR_BUS_INACTIVE_TL_MSK
- ITCT_HDR_BUS_INACTIVE_TL_OFF
- ITCT_HDR_DEV_TYPE_MSK
- ITCT_HDR_DEV_TYPE_OFF
- ITCT_HDR_INLT_MSK
- ITCT_HDR_INLT_OFF
- ITCT_HDR_IT_NEXUS_LOSS_TL_MSK
- ITCT_HDR_IT_NEXUS_LOSS_TL_OFF
- ITCT_HDR_MAX_CONN_RATE_MSK
- ITCT_HDR_MAX_CONN_RATE_OFF
- ITCT_HDR_MAX_CONN_TL_MSK
- ITCT_HDR_MAX_CONN_TL_OFF
- ITCT_HDR_MAX_SAS_ADDR_MSK
- ITCT_HDR_MAX_SAS_ADDR_OFF
- ITCT_HDR_MCR_MSK
- ITCT_HDR_MCR_OFF
- ITCT_HDR_MCTLT_MSK
- ITCT_HDR_MCTLT_OFF
- ITCT_HDR_PORT_ID_MSK
- ITCT_HDR_PORT_ID_OFF
- ITCT_HDR_REJ_OPEN_TL_MSK
- ITCT_HDR_REJ_OPEN_TL_OFF
- ITCT_HDR_RTOLT_MSK
- ITCT_HDR_RTOLT_OFF
- ITCT_HDR_SMP_TIMEOUT
- ITCT_HDR_SMP_TIMEOUT_8US
- ITCT_HDR_SMP_TIMEOUT_MSK
- ITCT_HDR_SMP_TIMEOUT_OFF
- ITCT_HDR_VALID_LINK_NUM_MSK
- ITCT_HDR_VALID_LINK_NUM_OFF
- ITCT_HDR_VALID_MSK
- ITCT_HDR_VALID_OFF
- ITCT_HDR_VLN_MSK
- ITCT_HDR_VLN_OFF
- ITCW_OP_READ
- ITCW_OP_WRITE
- ITC_D
- ITC_I
- ITC_I_AND_D
- ITD1000_H
- ITD1000_PRIV_H
- ITD_ACTIVE
- ITD_OPT_IOC
- ITD_OPT_SMALL
- ITD_STS_ACTIVE
- ITD_STS_BABBLE
- ITD_STS_DBE
- ITD_STS_INACTIVE
- ITE
- ITEGNO_PRODUCT_ID
- ITEGNO_PRODUCT_ID_2080
- ITEGNO_VENDOR_ID
- ITEMS
- ITEMS_PER_DESC
- ITEM_FOUND
- ITEM_NOT_FOUND
- ITEM_PTRS_SIZE
- ITEM_SIZE
- ITEM_TYPE
- ITER
- ITERATE_ALIGN
- ITERATE_LEN
- ITERATE_LEN_LIST
- ITERATE_MAX_LEN
- ITERATE_RESOURCES
- ITERATIONS
- ITERATIONS_BENCH
- ITERATIONS_LONG
- ITERATIONS_SHORT
- ITER_BVEC
- ITER_DISCARD
- ITER_GET_BVECS_PAGES
- ITER_IOVEC
- ITER_KVEC
- ITER_PIPE
- ITER_STRIDE
- ITE_887x_INTCBAR
- ITE_887x_IOSIZE
- ITE_887x_MISCR
- ITE_887x_POSIO0
- ITE_887x_POSIO_ENABLE
- ITE_887x_POSIO_IOSIZE_32
- ITE_887x_POSIO_IOSIZE_8
- ITE_887x_POSIO_SPEED
- ITE_887x_PS0BAR
- ITE_887x_UARTBAR
- ITE_BAUDRATE_DIVISOR
- ITE_BITS_TO_NS
- ITE_CFQ_400
- ITE_CFQ_450
- ITE_CFQ_480
- ITE_CFQ_500
- ITE_DEFAULT_CARRIER_FREQ
- ITE_DRIVER_NAME
- ITE_HCF_MAX_CARRIER_FREQ
- ITE_HCF_MIN_CARRIER_FREQ
- ITE_IRQ_RX_FIFO
- ITE_IRQ_RX_FIFO_OVERRUN
- ITE_IRQ_TX_FIFO
- ITE_LCF_MAX_CARRIER_FREQ
- ITE_LCF_MIN_CARRIER_FREQ
- ITE_RXDCR_DEFAULT
- ITE_RXDCR_MAX
- ITE_RXDCR_PER_10000_STEP
- ITE_RX_FIFO_LEN
- ITE_TXMPW_A
- ITE_TXMPW_B
- ITE_TXMPW_C
- ITE_TXMPW_D
- ITE_TXMPW_E
- ITE_TX_FIFO_LEN
- ITE_TX_MAX_RLE
- ITE_TX_PULSE
- ITE_TX_RLE_MASK
- ITE_TX_SPACE
- ITG3200_CLK_EXT_19M
- ITG3200_CLK_EXT_32K
- ITG3200_CLK_GYRO_X
- ITG3200_CLK_GYRO_Y
- ITG3200_CLK_GYRO_Z
- ITG3200_CLK_INTERNAL
- ITG3200_DLPF_10_1
- ITG3200_DLPF_188_1
- ITG3200_DLPF_20_1
- ITG3200_DLPF_256_8
- ITG3200_DLPF_42_1
- ITG3200_DLPF_5_1
- ITG3200_DLPF_98_1
- ITG3200_DLPF_CFG_MASK
- ITG3200_DLPF_FS_SEL_2000
- ITG3200_GYRO_CHAN
- ITG3200_IRQ_ACTIVE_HIGH
- ITG3200_IRQ_ACTIVE_LOW
- ITG3200_IRQ_DATA_RDY_ENABLE
- ITG3200_IRQ_DATA_RDY_STATUS
- ITG3200_IRQ_DEVICE_RDY_ENABLE
- ITG3200_IRQ_DEVICE_RDY_STATUS
- ITG3200_IRQ_LATCH_50US_PULSE
- ITG3200_IRQ_LATCH_CLEAR_ANY
- ITG3200_IRQ_LATCH_CLEAR_STATUS
- ITG3200_IRQ_LATCH_UNTIL_CLEARED
- ITG3200_IRQ_OPEN_DRAIN
- ITG3200_IRQ_PUSH_PULL
- ITG3200_REG_ADDRESS
- ITG3200_REG_DLPF
- ITG3200_REG_GYRO_XOUT_H
- ITG3200_REG_GYRO_XOUT_L
- ITG3200_REG_GYRO_YOUT_H
- ITG3200_REG_GYRO_YOUT_L
- ITG3200_REG_GYRO_ZOUT_H
- ITG3200_REG_GYRO_ZOUT_L
- ITG3200_REG_IRQ_CONFIG
- ITG3200_REG_IRQ_STATUS
- ITG3200_REG_POWER_MANAGEMENT
- ITG3200_REG_SAMPLE_RATE_DIV
- ITG3200_REG_TEMP_OUT_H
- ITG3200_REG_TEMP_OUT_L
- ITG3200_RESET
- ITG3200_SCAN_ELEMENTS
- ITG3200_SCAN_GYRO_X
- ITG3200_SCAN_GYRO_Y
- ITG3200_SCAN_GYRO_Z
- ITG3200_SCAN_INDEX
- ITG3200_SCAN_TEMP
- ITG3200_SLEEP
- ITG3200_ST
- ITG3200_STANDBY_GYRO_X
- ITG3200_STANDBY_GYRO_Y
- ITG3200_STANDBY_GYRO_Z
- ITI
- ITICKLE
- ITIME
- ITIMER_PROF
- ITIMER_REAL
- ITIMER_TEST
- ITIMER_VIRTUAL
- ITIP_MASK_RXDMAC
- ITIP_MASK_SSPCLKIN
- ITIP_MASK_SSPFSSIN
- ITIP_MASK_SSPRXD
- ITIP_MASK_SSPTXDIN
- ITIP_MASK_TXDMAC
- ITLB_ARF_WAYS
- ITLB_FIXED
- ITLB_HIT_BIT
- ITLB_LAST_VAR_UNRESTRICTED
- ITLB_LOAD_MISS
- ITLB_MISS_KERNEL
- ITLB_MR_MASK
- ITLB_OFFSET
- ITLB_REAL_MISS_EXITS
- ITLB_SMP_CONVERT_MASK
- ITLB_TR_MASK
- ITLB_UP_CONVERT_MASK
- ITLB_VIRT_MISS_EXITS
- ITMISS
- ITNIM_STATE_FREE
- ITNIM_STATE_NONE
- ITNIM_STATE_OFFLINE
- ITNIM_STATE_OFFLINE_PENDING
- ITNIM_STATE_ONLINE
- ITNIM_STATE_TIMEOUT
- ITNL_TIMEOUT
- ITNL_TIMEOUT_CONST
- ITOA_MAX_LEN
- ITOC
- ITOP_MASK_INTR
- ITOP_MASK_RORINTR
- ITOP_MASK_RTINTR
- ITOP_MASK_RXDMABREQ
- ITOP_MASK_RXDMASREQ
- ITOP_MASK_RXINTR
- ITOP_MASK_SSPCLKOUT
- ITOP_MASK_SSPCTLOEn
- ITOP_MASK_SSPFSSOUT
- ITOP_MASK_SSPOEn
- ITOP_MASK_SSPTXD
- ITOP_MASK_TXDMABREQ
- ITOP_MASK_TXDMASREQ
- ITOP_MASK_TXINTR
- ITOSTOP
- ITRACE_HELP
- ITRAM_ADDR
- ITRAM_DATA
- ITR_COUNTDOWN_START
- ITR_IS_ADAPTIVE
- ITR_IS_BULK
- ITR_IS_DYNAMIC
- ITR_REG_ALIGN
- ITR_TO_REG
- ITSTART
- ITS_CMD_BUFFER_SIZE
- ITS_CMD_OFFSET
- ITS_CMD_QUEUE_NR_ENTRIES
- ITS_CMD_QUEUE_SZ
- ITS_CMD_SIZE
- ITS_FLAGS_CMDQ_NEEDS_FLUSHING
- ITS_FLAGS_SAVE_SUSPEND_STATE
- ITS_FLAGS_WORKAROUND_CAVIUM_22375
- ITS_FLAGS_WORKAROUND_CAVIUM_23144
- ITS_ITT_ALIGN
- ITS_MAX_LPI_NRBITS
- ITS_MAX_VPEID
- ITS_MAX_VPEID_BITS
- ITT_ANTENNA
- ITT_INVALID_SIGNATURE
- ITU601_RGBFULL
- ITU656_ON_OFF
- ITU709_RGBFULL
- ITVC_READ_DIR
- ITVC_WRITE_DIR
- ITV_MCH_TEMP_MASK
- ITV_MCH_TEMP_SHIFT
- ITV_ME_SEQNO_MASK
- ITV_ME_SEQNO_SHIFT
- ITV_PCH_TEMP_MASK
- ITYPE
- ITYPE_ABORT
- ITYPE_GROUP
- ITYPE_HBI
- ITYPE_I2C
- ITYPE_I2S
- ITYPE_INVALID
- ITYPE_LOOPBACK
- ITYPE_MEDIALB_DIM
- ITYPE_MEDIALB_DIM2
- ITYPE_OTHER
- ITYPE_PARITY
- ITYPE_PCIE
- ITYPE_PHY
- ITYPE_RBPL_THRESH
- ITYPE_RBPS_THRESH
- ITYPE_RBRQ_THRESH
- ITYPE_RBRQ_TIMER
- ITYPE_TBRQ_THRESH
- ITYPE_TPD_COMPLETE
- ITYPE_TSI
- ITYPE_TYPE
- ITYPE_USB
- ITYPE_mskCPID
- ITYPE_mskETYPE
- ITYPE_mskINST
- ITYPE_mskSTYPE
- ITYPE_mskSWID
- ITYPE_mskVECTOR
- ITYPE_offCPID
- ITYPE_offETYPE
- ITYPE_offINST
- ITYPE_offSTYPE
- ITYPE_offSWID
- ITYPE_offVECTOR
- IT_ACQUIRE_MEM
- IT_ATOMIC_GDS
- IT_CLEAR_STATE
- IT_COND_EXEC
- IT_COND_WRITE
- IT_CONTEXT_CONTROL
- IT_CONTEXT_CYCLE_MATCH_ENABLE
- IT_COPY_DATA
- IT_COPY_DW
- IT_CURLIM_BUCK1
- IT_CURLIM_BUCK2
- IT_CURLIM_BUCK3
- IT_CURLIM_BUCK4
- IT_CURLIM_LDO1
- IT_CURLIM_LDO2
- IT_CURLIM_LDO3
- IT_CURLIM_LDO4
- IT_CURLIM_LDO5
- IT_CURLIM_LDO6
- IT_DISPATCH_DIRECT
- IT_DISPATCH_INDIRECT
- IT_DMA_DATA
- IT_DRAW_INDEX_2
- IT_DRAW_INDEX_AUTO
- IT_DRAW_INDEX_INDIRECT
- IT_DRAW_INDEX_INDIRECT_MULTI
- IT_DRAW_INDEX_MULTI_AUTO
- IT_DRAW_INDEX_OFFSET_2
- IT_DRAW_INDIRECT
- IT_DRAW_INDIRECT_MULTI
- IT_DRAW_PREAMBLE
- IT_DUMP_CONST_RAM
- IT_EISA
- IT_ERR
- IT_ETH
- IT_EVENT_WRITE
- IT_EVENT_WRITE_EOP
- IT_EVENT_WRITE_EOS
- IT_FRAME
- IT_HEADER_CHANNEL
- IT_HEADER_DATA_LENGTH
- IT_HEADER_SPEED
- IT_HEADER_SY
- IT_HEADER_TAG
- IT_HEADER_TCODE
- IT_ID_NOT_SET
- IT_ID_SET
- IT_INCREMENT_CE_COUNTER
- IT_INCREMENT_DE_COUNTER
- IT_INDEX_BASE
- IT_INDEX_BUFFER_SIZE
- IT_INDEX_TYPE
- IT_INDIRECT_BUFFER
- IT_INDIRECT_BUFFER_CNST
- IT_INDIRECT_BUFFER_PASID
- IT_INT
- IT_INT2
- IT_INTA
- IT_INTB
- IT_INTC
- IT_INTD
- IT_LINE
- IT_LOAD_CONFIG_REG
- IT_LOAD_CONST_RAM
- IT_LOAD_CONTEXT_REG
- IT_LOAD_SH_REG
- IT_LOAD_UCONFIG_REG
- IT_MAP_PROCESS
- IT_MAP_QUEUES
- IT_MASK
- IT_MEM_SEMAPHORE
- IT_NEXUS_TIMEOUT
- IT_NOP
- IT_NUM_INSTANCES
- IT_OCCLUSION_QUERY
- IT_OCP_BOOST
- IT_OCP_OTG
- IT_OCP_SWOUT
- IT_OVP_BOOST
- IT_OVR
- IT_PFP_SYNC_ME
- IT_PKT_HEADER_SIZE_CIP
- IT_PKT_HEADER_SIZE_NO_CIP
- IT_PONKEY_F
- IT_PONKEY_R
- IT_PREAMBLE_CNTL
- IT_PRED_EXEC
- IT_QUERY_STATUS
- IT_REG_RMW
- IT_RELEASE_MEM
- IT_REWIND
- IT_RUN_LIST
- IT_SCRATCH_RAM_READ
- IT_SCRATCH_RAM_WRITE
- IT_SCSI
- IT_SET_BASE
- IT_SET_CONFIG_REG
- IT_SET_CONTEXT_REG
- IT_SET_CONTEXT_REG_INDIRECT
- IT_SET_PREDICATION
- IT_SET_QUEUE_REG
- IT_SET_RESOURCES
- IT_SET_SH_REG
- IT_SET_SH_REG_OFFSET
- IT_SET_UCONFIG_REG
- IT_SHIFT
- IT_SHORT_SWOTG
- IT_SHORT_SWOUT
- IT_STRMOUT_BUFFER_UPDATE
- IT_SURFACE_SYNC
- IT_SWIN_F
- IT_SWIN_R
- IT_SWITCH_BUFFER
- IT_SWOUT_F
- IT_SWOUT_R
- IT_TWARN_F
- IT_TWARN_R
- IT_UNMAP_QUEUES
- IT_VBUS_OTG_F
- IT_VBUS_OTG_R
- IT_VINLOW_F
- IT_VINLOW_R
- IT_VSYNC
- IT_WAIT_ON_CE_COUNTER
- IT_WAIT_ON_DE_COUNTER_DIFF
- IT_WAIT_REG_MEM
- IT_WAKEUP_F
- IT_WAKEUP_R
- IT_WRITE_CONST_RAM
- IT_WRITE_DATA
- IUCLC
- IUCR0_ICBI_ACK
- IUCV_ACCEPT
- IUCV_BOUND
- IUCV_BUFSIZE_DEFAULT
- IUCV_CLOSED
- IUCV_CLOSING
- IUCV_CONNECT
- IUCV_CONNECTED
- IUCV_CONN_IDLE_TIMEOUT
- IUCV_CONN_TIMEOUT
- IUCV_DBF_DATA_LEN
- IUCV_DBF_DATA_LEVEL
- IUCV_DBF_DATA_NAME
- IUCV_DBF_DATA_NR_AREAS
- IUCV_DBF_DATA_PAGES
- IUCV_DBF_HEX
- IUCV_DBF_SETUP_LEN
- IUCV_DBF_SETUP_LEVEL
- IUCV_DBF_SETUP_NAME
- IUCV_DBF_SETUP_NR_AREAS
- IUCV_DBF_SETUP_PAGES
- IUCV_DBF_SPRINTF
- IUCV_DBF_TEXT
- IUCV_DBF_TEXT_
- IUCV_DBF_TRACE_LEN
- IUCV_DBF_TRACE_LEVEL
- IUCV_DBF_TRACE_NAME
- IUCV_DBF_TRACE_NR_AREAS
- IUCV_DBF_TRACE_PAGES
- IUCV_DECLARE_BUFFER
- IUCV_DISCONN
- IUCV_DISCONN_TIMEOUT
- IUCV_HIPER_MSGLIM_DEFAULT
- IUCV_HVC_CON_IDX
- IUCV_IPALL
- IUCV_IPANSLST
- IUCV_IPBUFLST
- IUCV_IPFGMID
- IUCV_IPFGPID
- IUCV_IPLOCAL
- IUCV_IPNORPY
- IUCV_IPPRTY
- IUCV_IPQUSCE
- IUCV_IPRMDATA
- IUCV_IPSRCCLS
- IUCV_IPSYNC
- IUCV_IPTRGCLS
- IUCV_LISTEN
- IUCV_OPEN
- IUCV_PM_FREEZING
- IUCV_PM_INITIAL
- IUCV_PM_RESTORING
- IUCV_PM_THAWING
- IUCV_PURGE
- IUCV_QUERY
- IUCV_QUEUELEN_DEFAULT
- IUCV_QUIESCE
- IUCV_RECEIVE
- IUCV_REJECT
- IUCV_REPLY
- IUCV_RESUME
- IUCV_RETRIEVE_BUFFER
- IUCV_SEND
- IUCV_SETCONTROLMASK
- IUCV_SETMASK
- IUCV_SEVER
- IUCV_SEVERED
- IUCV_SKB_CB
- IUDMA_DMAC_OFFSET
- IUDMA_DMAS_OFFSET
- IUDMA_EP0_RXCHAN
- IUDMA_EP0_TXCHAN
- IUDMA_MAX_FRAGMENT
- IUDMA_RESET_TIMEOUT_US
- IUNKWN
- IUSC_PRE_SL1660
- IUSC_SL1660
- IUSR
- IUTF8
- IUU_AVR_1CLK
- IUU_AVR_DREAD
- IUU_AVR_DREADN
- IUU_AVR_DWRITE
- IUU_AVR_INCN_PC
- IUU_AVR_INC_PC
- IUU_AVR_OFF
- IUU_AVR_ON
- IUU_AVR_PREAD
- IUU_AVR_PREADN
- IUU_AVR_PWRITE
- IUU_AVR_PWRITEN
- IUU_AVR_RESET
- IUU_AVR_RESET_PC
- IUU_BAUD_115200
- IUU_BAUD_19200
- IUU_BAUD_2400
- IUU_BAUD_28800
- IUU_BAUD_38400
- IUU_BAUD_57600
- IUU_BAUD_9600
- IUU_CLK_3579000
- IUU_CLK_3680000
- IUU_CLK_6000000
- IUU_DELAY_MS
- IUU_DEVICE_NOT_FOUND
- IUU_DEV_ERROR
- IUU_EEPROM_BREAD
- IUU_EEPROM_BREADX
- IUU_EEPROM_OFF
- IUU_EEPROM_ON
- IUU_EEPROM_READ
- IUU_EEPROM_READX
- IUU_EEPROM_WRITE
- IUU_EEPROM_WRITE16
- IUU_EEPROM_WRITE8
- IUU_EEPROM_WRITEX
- IUU_EEPROM_WRITEX32
- IUU_EEPROM_WRITEX64
- IUU_FULLCARD_IN
- IUU_GET_FIRMWARE_VERSION
- IUU_GET_LOADER_VERSION
- IUU_GET_PRODUCT_NAME
- IUU_GET_STATE_REGISTER
- IUU_INVALID_HANDLE
- IUU_INVALID_PARAMETER
- IUU_INVALID_REQUEST_LENGTH
- IUU_INVALID_voidERFACE
- IUU_MINICARD_IN
- IUU_NO_OPERATION
- IUU_ONE_STOP_BIT
- IUU_OPERATION_OK
- IUU_PARITY_EVEN
- IUU_PARITY_MARK
- IUU_PARITY_NONE
- IUU_PARITY_ODD
- IUU_PARITY_SPACE
- IUU_PIC_CMD
- IUU_PIC_CMD_LOAD
- IUU_PIC_CMD_READ
- IUU_PIC_DREAD
- IUU_PIC_DWRITE
- IUU_PIC_INCN_PC
- IUU_PIC_INC_PC
- IUU_PIC_OFF
- IUU_PIC_ON
- IUU_PIC_PREAD
- IUU_PIC_PREADN
- IUU_PIC_PWRITE
- IUU_PIC_RESET
- IUU_READ_ERROR
- IUU_RST_CLEAR
- IUU_RST_SET
- IUU_RX_ERROR
- IUU_SC_INSERTED
- IUU_SET_LED
- IUU_SET_VCC
- IUU_SIM_INSERTED
- IUU_TWO_STOP_BITS
- IUU_TX_ERROR
- IUU_UART_CHANGE
- IUU_UART_DISABLE
- IUU_UART_ENABLE
- IUU_UART_ESC
- IUU_UART_NOP
- IUU_UART_NOT_ENABLED
- IUU_UART_RX
- IUU_UART_TRAP
- IUU_UART_TRAP_BREAK
- IUU_UART_TX
- IUU_UART_WRITE_I2C
- IUU_USB_OP_TIMEOUT
- IUU_USB_PRODUCT_ID
- IUU_USB_VENDOR_ID
- IUU_VCC_3V
- IUU_VCC_5V
- IUU_VERIFY_ERROR
- IUU_WAIT_MS
- IUU_WAIT_MUS
- IUU_WRITE_ERROR
- IU_ID_COMMAND
- IU_ID_READ_READY
- IU_ID_RESPONSE
- IU_ID_STATUS
- IU_ID_TASK_MGMT
- IU_ID_WRITE_READY
- IV
- IVA
- IVBEP_CB0_MSR_PMON_BOX_FILTER_C6
- IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC
- IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK
- IVBEP_CB0_MSR_PMON_BOX_FILTER_NC
- IVBEP_CB0_MSR_PMON_BOX_FILTER_NID
- IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC
- IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE
- IVBEP_CB0_MSR_PMON_BOX_FILTER_TID
- IVBEP_CBO_MSR_PMON_RAW_EVENT_MASK
- IVBEP_HA_PCI_PMON_CTL_Q_OCC_RST
- IVBEP_HA_PCI_PMON_RAW_EVENT_MASK
- IVBEP_PCI_UNCORE_HA
- IVBEP_PCI_UNCORE_IMC
- IVBEP_PCI_UNCORE_IRP
- IVBEP_PCI_UNCORE_QPI
- IVBEP_PCI_UNCORE_R2PCIE
- IVBEP_PCI_UNCORE_R3QPI
- IVBEP_PCU_MSR_PMON_RAW_EVENT_MASK
- IVBEP_PMON_BOX_CTL_INT
- IVBEP_PMON_RAW_EVENT_MASK
- IVBEP_QPI_PCI_PMON_RAW_EVENT_MASK
- IVBEP_UNCORE_MSR_OPS_COMMON_INIT
- IVBEP_UNCORE_PCI_COMMON_INIT
- IVBEP_U_MSR_PMON_GLOBAL_CTL
- IVBEP_U_MSR_PMON_RAW_EVENT_MASK
- IVBEP_U_PMON_GLOBAL_FRZ_ALL
- IVBEP_U_PMON_GLOBAL_UNFRZ_ALL
- IVB_BASE
- IVB_CHICKEN3
- IVB_COLORS
- IVB_CURSOR_B_OFFSET
- IVB_CURSOR_C_OFFSET
- IVB_CURSOR_OFFSETS
- IVB_DPFC_CTL_FENCE_EN
- IVB_DPFC_CTL_PLANE
- IVB_D_PLATFORM
- IVB_FBC_COMP_SEG_MASK
- IVB_FBC_RT_BASE
- IVB_FBC_STATUS2
- IVB_M_PLATFORM
- IVB_PIPE_C_DISABLE
- IVB_PIPE_OFFSETS
- IVB_TIMESTAMP_CTR
- IVB_mskESZ
- IVB_mskEVIC
- IVB_mskIVBASE
- IVB_mskIVIC_VER
- IVB_mskNIVIC
- IVB_offESZ
- IVB_offEVIC
- IVB_offIVBASE
- IVB_offIVIC_VER
- IVB_offNIVIC
- IVB_valESZ16
- IVB_valESZ256
- IVB_valESZ4
- IVB_valESZ64
- IVDR_CK_ON
- IVFM_MASK
- IVFM_SHIFT
- IVFWIDTH_G
- IVFWIDTH_M
- IVFWIDTH_S
- IVFWIDTH_V
- IVHD_DEV_ACPI_HID
- IVHD_DEV_ALIAS
- IVHD_DEV_ALIAS_RANGE
- IVHD_DEV_ALL
- IVHD_DEV_EXT_SELECT
- IVHD_DEV_EXT_SELECT_RANGE
- IVHD_DEV_RANGE_END
- IVHD_DEV_SELECT
- IVHD_DEV_SELECT_RANGE_START
- IVHD_DEV_SPECIAL
- IVHD_FLAG_HT_TUN_EN_MASK
- IVHD_FLAG_ISOC_EN_MASK
- IVHD_FLAG_PASSPW_EN_MASK
- IVHD_FLAG_RESPASSPW_EN_MASK
- IVHD_SPECIAL_HPET
- IVHD_SPECIAL_IOAPIC
- IVLAN_BITWIDTH
- IVL_MAC
- IVMD_FLAG_EXCL_RANGE
- IVMD_FLAG_UNITY_MAP
- IVM_D_TH_MASK
- IVM_D_TH_SHIFT
- IVP
- IVPR_ACTIVITY_MASK
- IVPR_ACTIVITY_SHIFT
- IVPR_MASK_MASK
- IVPR_MASK_SHIFT
- IVPR_MODE_MASK
- IVPR_MODE_SHIFT
- IVPR_POLARITY_MASK
- IVPR_POLARITY_SHIFT
- IVPR_PRIORITY
- IVPR_PRIORITY_MASK
- IVPR_SENSE_MASK
- IVPR_SENSE_SHIFT
- IVPR_VECTOR
- IVR
- IVRS_HEADER_LENGTH
- IVR_ADDR
- IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF_MASK
- IVR_TARGETPSMREF_CPU_0__IVR_TARGETPSMREF__SHIFT
- IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF_MASK
- IVR_TARGETPSMREF_CPU_1__IVR_TARGETPSMREF__SHIFT
- IVR_VECTOR_MASK
- IVTVFB_DBGFLG_INFO
- IVTVFB_DBGFLG_WARN
- IVTVFB_DEBUG
- IVTVFB_DEBUG_INFO
- IVTVFB_DEBUG_WARN
- IVTVFB_ERR
- IVTVFB_INFO
- IVTVFB_IOC_DMA_FRAME
- IVTVFB_WARN
- IVTV_ADAPTEC_IR_ADDR
- IVTV_ALGO_BIT_TIMEOUT
- IVTV_ALSA_DBGFLG_INFO
- IVTV_ALSA_DBGFLG_WARN
- IVTV_ALSA_DEBUG
- IVTV_ALSA_DEBUG_INFO
- IVTV_ALSA_DEBUG_WARN
- IVTV_ALSA_ERR
- IVTV_ALSA_INFO
- IVTV_ALSA_WARN
- IVTV_API_STD_TIMEOUT
- IVTV_AVERMEDIA_IR_RX_I2C_ADDR
- IVTV_CAP_DECODER
- IVTV_CAP_ENCODER
- IVTV_CARDS_H
- IVTV_CARD_ASUS_FALCON2
- IVTV_CARD_AVC2010
- IVTV_CARD_AVC2410
- IVTV_CARD_AVERTV_MCE116
- IVTV_CARD_AVER_EZMAKER
- IVTV_CARD_AVER_M104
- IVTV_CARD_AVER_PVR150PLUS
- IVTV_CARD_AVER_ULTRA1500MCE
- IVTV_CARD_BUFFALO_MV5L
- IVTV_CARD_CLUB3D
- IVTV_CARD_CX23416GYC
- IVTV_CARD_CX23416GYC_NOGR
- IVTV_CARD_CX23416GYC_NOGRYCS
- IVTV_CARD_DCTMTVP1
- IVTV_CARD_GOTVIEW_PCI_DVD
- IVTV_CARD_GOTVIEW_PCI_DVD2
- IVTV_CARD_GV_MVPRX
- IVTV_CARD_GV_MVPRX2E
- IVTV_CARD_INPUT_AUD_TUNER
- IVTV_CARD_INPUT_COMPOSITE1
- IVTV_CARD_INPUT_COMPOSITE2
- IVTV_CARD_INPUT_COMPOSITE3
- IVTV_CARD_INPUT_LINE_IN1
- IVTV_CARD_INPUT_LINE_IN2
- IVTV_CARD_INPUT_SVIDEO1
- IVTV_CARD_INPUT_SVIDEO2
- IVTV_CARD_INPUT_VID_TUNER
- IVTV_CARD_KIKYOU
- IVTV_CARD_LAST
- IVTV_CARD_M179
- IVTV_CARD_MAX_AUDIO_INPUTS
- IVTV_CARD_MAX_TUNERS
- IVTV_CARD_MAX_VIDEO_INPUTS
- IVTV_CARD_MPG160
- IVTV_CARD_MPG600
- IVTV_CARD_PG600
- IVTV_CARD_PG600V2
- IVTV_CARD_PVR_150
- IVTV_CARD_PVR_250
- IVTV_CARD_PVR_350
- IVTV_CARD_PVR_350_V1
- IVTV_CARD_TG5000TV
- IVTV_CARD_VA2000MAX_SNT6
- IVTV_CARD_YUAN_MPC622
- IVTV_CMD_AO_STOP
- IVTV_CMD_APU_PING
- IVTV_CMD_HW_BLOCKS_RST
- IVTV_CMD_SDRAM_PRECHARGE_INIT
- IVTV_CMD_SDRAM_REFRESH_INIT
- IVTV_CMD_SPU_STOP
- IVTV_CMD_VDM_STOP
- IVTV_CMD_VPU_STOP15
- IVTV_CMD_VPU_STOP16
- IVTV_CONTROLS_H
- IVTV_CS53L32A_I2C_ADDR
- IVTV_CX25840_I2C_ADDR
- IVTV_DBGFLG_DEC
- IVTV_DBGFLG_DMA
- IVTV_DBGFLG_FILE
- IVTV_DBGFLG_HIGHVOL
- IVTV_DBGFLG_I2C
- IVTV_DBGFLG_INFO
- IVTV_DBGFLG_IOCTL
- IVTV_DBGFLG_IRQ
- IVTV_DBGFLG_MB
- IVTV_DBGFLG_WARN
- IVTV_DBGFLG_YUV
- IVTV_DEBUG
- IVTV_DEBUG_ALSA_INFO
- IVTV_DEBUG_DEC
- IVTV_DEBUG_DMA
- IVTV_DEBUG_FILE
- IVTV_DEBUG_HIGH_VOL
- IVTV_DEBUG_HI_DEC
- IVTV_DEBUG_HI_DMA
- IVTV_DEBUG_HI_FILE
- IVTV_DEBUG_HI_I2C
- IVTV_DEBUG_HI_INFO
- IVTV_DEBUG_HI_IOCTL
- IVTV_DEBUG_HI_IRQ
- IVTV_DEBUG_HI_MB
- IVTV_DEBUG_HI_WARN
- IVTV_DEBUG_HI_YUV
- IVTV_DEBUG_I2C
- IVTV_DEBUG_INFO
- IVTV_DEBUG_IOCTL
- IVTV_DEBUG_IRQ
- IVTV_DEBUG_MB
- IVTV_DEBUG_WARN
- IVTV_DEBUG_YUV
- IVTV_DECODER_OFFSET
- IVTV_DECODER_SIZE
- IVTV_DECODE_INIT_MPEG_FILENAME
- IVTV_DECODE_INIT_MPEG_SIZE
- IVTV_DEC_STREAM_TYPE_MPG
- IVTV_DEC_STREAM_TYPE_VBI
- IVTV_DEC_STREAM_TYPE_VOUT
- IVTV_DEC_STREAM_TYPE_YUV
- IVTV_DEFAULT_DEC_MPG_BUFFERS
- IVTV_DEFAULT_DEC_VBI_BUFFERS
- IVTV_DEFAULT_DEC_YUV_BUFFERS
- IVTV_DEFAULT_ENC_MPG_BUFFERS
- IVTV_DEFAULT_ENC_PCM_BUFFERS
- IVTV_DEFAULT_ENC_VBI_BUFFERS
- IVTV_DEFAULT_ENC_YUV_BUFFERS
- IVTV_DEFAULT_I2C_CLOCK_PERIOD
- IVTV_DMA_SG_OSD_ENT
- IVTV_DMA_UNMAPPED
- IVTV_DRIVER_H
- IVTV_DRIVER_NAME
- IVTV_DUMMY_AUDIO
- IVTV_ENCODER_OFFSET
- IVTV_ENCODER_SIZE
- IVTV_ENC_STREAM_TYPE_MPG
- IVTV_ENC_STREAM_TYPE_PCM
- IVTV_ENC_STREAM_TYPE_RAD
- IVTV_ENC_STREAM_TYPE_VBI
- IVTV_ENC_STREAM_TYPE_YUV
- IVTV_ERR
- IVTV_FILEOPS_H
- IVTV_FIRMWARE_H
- IVTV_FW_DEC_SIZE
- IVTV_FW_ENC_SIZE
- IVTV_F_B_NEED_BUF_SWAP
- IVTV_F_I_DECODING_YUV
- IVTV_F_I_DEC_PAUSED
- IVTV_F_I_DEC_YUV
- IVTV_F_I_DIG_RST
- IVTV_F_I_DMA
- IVTV_F_I_ENC_PAUSED
- IVTV_F_I_EOS
- IVTV_F_I_EV_DEC_STOPPED
- IVTV_F_I_EV_VSYNC
- IVTV_F_I_EV_VSYNC_ENABLED
- IVTV_F_I_EV_VSYNC_FIELD
- IVTV_F_I_FAILED
- IVTV_F_I_HAVE_WORK
- IVTV_F_I_INITED
- IVTV_F_I_PIO
- IVTV_F_I_RADIO_USER
- IVTV_F_I_SPEED_CHANGE
- IVTV_F_I_UDMA
- IVTV_F_I_UDMA_PENDING
- IVTV_F_I_UPDATE_CC
- IVTV_F_I_UPDATE_VPS
- IVTV_F_I_UPDATE_WSS
- IVTV_F_I_VALID_DEC_TIMINGS
- IVTV_F_I_WORK_HANDLER_PCM
- IVTV_F_I_WORK_HANDLER_PIO
- IVTV_F_I_WORK_HANDLER_VBI
- IVTV_F_I_WORK_HANDLER_YUV
- IVTV_F_S_APPL_IO
- IVTV_F_S_CLAIMED
- IVTV_F_S_DMA_HAS_VBI
- IVTV_F_S_DMA_PENDING
- IVTV_F_S_INTERNAL_USE
- IVTV_F_S_NEEDS_DATA
- IVTV_F_S_PASSTHROUGH
- IVTV_F_S_PIO_HAS_VBI
- IVTV_F_S_PIO_PENDING
- IVTV_F_S_STREAMING
- IVTV_F_S_STREAMOFF
- IVTV_GPIO_H
- IVTV_GPIO_LINE_IN
- IVTV_GPIO_TUNER
- IVTV_HAUPPAUGE_I2C_ADDR
- IVTV_HAUP_EXT_IR_RX_I2C_ADDR
- IVTV_HAUP_INT_IR_RX_I2C_ADDR
- IVTV_HW_CS53L32A
- IVTV_HW_CX25840
- IVTV_HW_GPIO
- IVTV_HW_I2C_IR_RX_ADAPTEC
- IVTV_HW_I2C_IR_RX_AVER
- IVTV_HW_I2C_IR_RX_HAUP_EXT
- IVTV_HW_I2C_IR_RX_HAUP_INT
- IVTV_HW_IR_ANY
- IVTV_HW_M52790
- IVTV_HW_MSP34XX
- IVTV_HW_SAA7114
- IVTV_HW_SAA7115
- IVTV_HW_SAA711X
- IVTV_HW_SAA7127
- IVTV_HW_SAA717X
- IVTV_HW_TUNER
- IVTV_HW_TVEEPROM
- IVTV_HW_UPD64031A
- IVTV_HW_UPD6408X
- IVTV_HW_VP27SMPX
- IVTV_HW_WM8739
- IVTV_HW_WM8775
- IVTV_HW_Z8F0811_IR_HAUP
- IVTV_I2C_H
- IVTV_INFO
- IVTV_IOCTL_H
- IVTV_IOC_DMA_FRAME
- IVTV_IOC_PASSTHROUGH_MODE
- IVTV_IRQ_DEC_AUD_MODE_CHG
- IVTV_IRQ_DEC_DATA_REQ
- IVTV_IRQ_DEC_DMA_COMPLETE
- IVTV_IRQ_DEC_VBI_RE_INSERT
- IVTV_IRQ_DEC_VSYNC
- IVTV_IRQ_DMA
- IVTV_IRQ_DMA_ERR
- IVTV_IRQ_DMA_READ
- IVTV_IRQ_DMA_WRITE
- IVTV_IRQ_ENC_DMA_COMPLETE
- IVTV_IRQ_ENC_EOS
- IVTV_IRQ_ENC_PIO_COMPLETE
- IVTV_IRQ_ENC_START_CAP
- IVTV_IRQ_ENC_VBI_CAP
- IVTV_IRQ_ENC_VIM_RST
- IVTV_IRQ_H
- IVTV_IRQ_MASK_CAPTURE
- IVTV_IRQ_MASK_DECODE
- IVTV_IRQ_MASK_INIT
- IVTV_M52790_I2C_ADDR
- IVTV_MAILBOX_H
- IVTV_MASK_SPU_ENABLE
- IVTV_MASK_VPU_ENABLE15
- IVTV_MASK_VPU_ENABLE16
- IVTV_MAX_CARDS
- IVTV_MAX_PGM_INDEX
- IVTV_MAX_STREAMS
- IVTV_MBOX_DMA
- IVTV_MBOX_DMA_END
- IVTV_MBOX_DRIVER_BUSY
- IVTV_MBOX_DRIVER_DONE
- IVTV_MBOX_FIRMWARE_DONE
- IVTV_MBOX_FREE
- IVTV_MSP3400_I2C_ADDR
- IVTV_OSD_BPP_16_444
- IVTV_OSD_BPP_16_555
- IVTV_OSD_BPP_16_565
- IVTV_OSD_BPP_32
- IVTV_OSD_BPP_8
- IVTV_OSD_MAX_HEIGHT
- IVTV_OSD_MAX_WIDTH
- IVTV_PCI_ID_ADAPTEC
- IVTV_PCI_ID_ASUSTEK
- IVTV_PCI_ID_AVERMEDIA
- IVTV_PCI_ID_DIAMONDMM
- IVTV_PCI_ID_GOTVIEW1
- IVTV_PCI_ID_GOTVIEW2
- IVTV_PCI_ID_HAUPPAUGE
- IVTV_PCI_ID_HAUPPAUGE_ALT1
- IVTV_PCI_ID_HAUPPAUGE_ALT2
- IVTV_PCI_ID_IODATA
- IVTV_PCI_ID_MELCO
- IVTV_PCI_ID_SONY
- IVTV_PCI_ID_YUAN1
- IVTV_PCI_ID_YUAN2
- IVTV_PCI_ID_YUAN3
- IVTV_PCI_ID_YUAN4
- IVTV_QUEUE_H
- IVTV_REG_AO
- IVTV_REG_APU
- IVTV_REG_BYTEFLUSH
- IVTV_REG_DECDMAADDR
- IVTV_REG_DEC_LINE_FIELD
- IVTV_REG_DEC_SDRAM_PRECHARGE
- IVTV_REG_DEC_SDRAM_REFRESH
- IVTV_REG_DMACONTROL
- IVTV_REG_DMASTATUS
- IVTV_REG_DMAXFER
- IVTV_REG_ENCDMAADDR
- IVTV_REG_ENC_SDRAM_PRECHARGE
- IVTV_REG_ENC_SDRAM_REFRESH
- IVTV_REG_GPIO_DIR
- IVTV_REG_GPIO_IN
- IVTV_REG_GPIO_OUT
- IVTV_REG_HW_BLOCKS
- IVTV_REG_I2C_GETSCL_OFFSET
- IVTV_REG_I2C_GETSDA_OFFSET
- IVTV_REG_I2C_SETSCL_OFFSET
- IVTV_REG_I2C_SETSDA_OFFSET
- IVTV_REG_IRQMASK
- IVTV_REG_IRQSTATUS
- IVTV_REG_OFFSET
- IVTV_REG_SIZE
- IVTV_REG_SPU
- IVTV_REG_VDM
- IVTV_REG_VPU
- IVTV_ROUTING_H
- IVTV_SAA7115_I2C_ADDR
- IVTV_SAA7127_I2C_ADDR
- IVTV_SAA717X_IN0
- IVTV_SAA717X_IN1
- IVTV_SAA717X_IN2
- IVTV_SAA717X_TUNER_FLAG
- IVTV_SAA717x_I2C_ADDR
- IVTV_SAA71XX_COMPOSITE0
- IVTV_SAA71XX_COMPOSITE1
- IVTV_SAA71XX_COMPOSITE2
- IVTV_SAA71XX_COMPOSITE3
- IVTV_SAA71XX_COMPOSITE4
- IVTV_SAA71XX_COMPOSITE5
- IVTV_SAA71XX_SVIDEO0
- IVTV_SAA71XX_SVIDEO1
- IVTV_SAA71XX_SVIDEO2
- IVTV_SAA71XX_SVIDEO3
- IVTV_SDRAM_SLEEPTIME
- IVTV_SLICED_TYPE_CAPTION_525
- IVTV_SLICED_TYPE_TELETEXT_B
- IVTV_SLICED_TYPE_VPS
- IVTV_SLICED_TYPE_WSS_625
- IVTV_STREAMS_H
- IVTV_TEA5767_I2C_ADDR
- IVTV_UDMA_H
- IVTV_UPD64031A_I2C_ADDR
- IVTV_UPD64083_I2C_ADDR
- IVTV_V4L2_DEC_MPG_OFFSET
- IVTV_V4L2_DEC_VBI_OFFSET
- IVTV_V4L2_DEC_VOUT_OFFSET
- IVTV_V4L2_DEC_YUV_OFFSET
- IVTV_V4L2_ENC_PCM_OFFSET
- IVTV_V4L2_ENC_YUV_OFFSET
- IVTV_VBI_FRAMES
- IVTV_VBI_H
- IVTV_VERSION
- IVTV_VERSION_H
- IVTV_VP27SMPX_I2C_ADDR
- IVTV_WARN
- IVTV_WM8739_I2C_ADDR
- IVTV_WM8775_I2C_ADDR
- IVTV_YUV_BUFFERS
- IVTV_YUV_BUFFER_UV_OFFSET
- IVTV_YUV_H
- IVTV_YUV_HORIZONTAL_FILTER_OFFSET
- IVTV_YUV_MODE_AUTO
- IVTV_YUV_MODE_INTERLACED
- IVTV_YUV_MODE_MASK
- IVTV_YUV_MODE_PROGRESSIVE
- IVTV_YUV_SYNC_EVEN
- IVTV_YUV_SYNC_MASK
- IVTV_YUV_SYNC_ODD
- IVTV_YUV_UPDATE_HORIZONTAL
- IVTV_YUV_UPDATE_INVALID
- IVTV_YUV_UPDATE_VERTICAL
- IVTV_YUV_VERTICAL_FILTER_OFFSET
- IVTV_Z8F0811_IR_RX_I2C_ADDR
- IVTV_Z8F0811_IR_TX_I2C_ADDR
- IVY_BRIDGE
- IV_DSGL
- IV_FROM_CTX
- IV_FROM_DPTR
- IV_IMMEDIATE
- IV_NOP
- IV_OFFSET
- IV_OFFSET_SHIFT
- IV_POSITION
- IW5
- IW6
- IWALK_MAX_INODE_PREFETCH
- IWARP_ACCESS_MASK
- IWARP_ACTIVE_MODE
- IWARP_CONN_ERROR_MPA_ERROR_REJECT
- IWARP_CONN_ERROR_MPA_FIN
- IWARP_CONN_ERROR_MPA_INSUF_IRD
- IWARP_CONN_ERROR_MPA_INVALID_PACKET
- IWARP_CONN_ERROR_MPA_LOCAL_ERROR
- IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER
- IWARP_CONN_ERROR_MPA_RST
- IWARP_CONN_ERROR_MPA_RTR_MISMATCH
- IWARP_CONN_ERROR_MPA_TERMINATE
- IWARP_CONN_ERROR_MPA_TIMEOUT
- IWARP_CONN_ERROR_TCP_CONNECTION_RST
- IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET
- IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT
- IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK
- IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK
- IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK
- IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK
- IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK
- IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK
- IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK
- IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT
- IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK
- IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT
- IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD
- IWARP_EVENT_TYPE_ASYNC_CID_CLEANED
- IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE
- IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW
- IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED
- IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED
- IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE
- IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE
- IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY
- IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT
- IWARP_EVENT_TYPE_CREATE_QP
- IWARP_EVENT_TYPE_DESTROY_QP
- IWARP_EVENT_TYPE_MODIFY_QP
- IWARP_EVENT_TYPE_MPA_OFFLOAD
- IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR
- IWARP_EVENT_TYPE_QUERY_QP
- IWARP_EVENT_TYPE_TCP_OFFLOAD
- IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW
- IWARP_EXCEPTION_DETECTED_IRQ_FULL
- IWARP_EXCEPTION_DETECTED_LLP_CLOSED
- IWARP_EXCEPTION_DETECTED_LLP_RESET
- IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT
- IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR
- IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC
- IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR
- IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR
- IWARP_EXCEPTION_DETECTED_RQ_EMPTY
- IWARP_EXCEPTION_DETECTED_SRQ_EMPTY
- IWARP_EXCEPTION_DETECTED_SRQ_LIMIT
- IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED
- IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE
- IWARP_LL2_ALIGNED_TX_QUEUE
- IWARP_LL2_ERROR
- IWARP_LL2_IN_ORDER_TX_QUEUE
- IWARP_MAX_QPS
- IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT
- IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK
- IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT
- IWARP_MODIFY_QP_STATE_CLOSING
- IWARP_MODIFY_QP_STATE_ERROR
- IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK
- IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT
- IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK
- IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT
- IWARP_PASSIVE_MODE
- IWARP_QP_IN_ERROR_BAD_CLOSE
- IWARP_QP_IN_ERROR_GOOD_CLOSE
- IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK
- IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT
- IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK
- IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT
- IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD
- IWARP_RAMROD_CMD_ID_CREATE_QP
- IWARP_RAMROD_CMD_ID_DESTROY_QP
- IWARP_RAMROD_CMD_ID_MODIFY_QP
- IWARP_RAMROD_CMD_ID_MPA_OFFLOAD
- IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR
- IWARP_RAMROD_CMD_ID_QUERY_QP
- IWARP_RAMROD_CMD_ID_TCP_OFFLOAD
- IWARP_REQ_MAX_INLINE_DATA_SIZE
- IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE
- IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE
- IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET
- IWARP_SHARED_QUEUE_PAGE_SIZE
- IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE
- IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET
- IWCH_NODE_DESC
- IWCH_QP_ATTR_ENABLE_RDMA_BIND
- IWCH_QP_ATTR_ENABLE_RDMA_READ
- IWCH_QP_ATTR_ENABLE_RDMA_WRITE
- IWCH_QP_ATTR_LLP_STREAM_HANDLE
- IWCH_QP_ATTR_MAX_IRD
- IWCH_QP_ATTR_MAX_ORD
- IWCH_QP_ATTR_MPA_ATTR
- IWCH_QP_ATTR_NEXT_STATE
- IWCH_QP_ATTR_QP_CONTEXT_ACTIVATE
- IWCH_QP_ATTR_STREAM_MSG_BUFFER
- IWCH_QP_ATTR_VALID_MODIFY
- IWCH_QP_FLAGS
- IWCH_QP_QUERY_CONTEXT_GET
- IWCH_QP_QUERY_CONTEXT_NONE
- IWCH_QP_QUERY_CONTEXT_QUIESCE
- IWCH_QP_QUERY_CONTEXT_REMOVE
- IWCH_QP_QUERY_CONTEXT_SUSPEND
- IWCH_QP_QUERY_TEST_USERWRITE
- IWCH_QP_STATE_CLOSING
- IWCH_QP_STATE_ERROR
- IWCH_QP_STATE_IDLE
- IWCH_QP_STATE_RTS
- IWCH_QP_STATE_TERMINATE
- IWCH_QP_STATE_TOT
- IWCH_STAG_STATE_INVALID
- IWCH_STAG_STATE_VALID
- IWCH_UVERBS_ABI_VERSION
- IWCM_F_CONNECT_WAIT
- IWCM_F_DROP_EVENTS
- IWCM_H
- IWCR_CNT_MASK
- IWCR_CNT_SHIFT
- IWCR_HS_CNT1_MASK
- IWCR_HS_CNT1_SHIFT
- IWCR_HS_CNT2_MASK
- IWCR_HS_CNT2_SHIFT
- IWDG1
- IWDG2
- IWDG_KR
- IWDG_PR
- IWDG_RLR
- IWDG_SR
- IWDG_WINR
- IWE
- IWEVASSOCREQIE
- IWEVASSOCRESPIE
- IWEVCUSTOM
- IWEVEXPIRED
- IWEVFIRST
- IWEVGENIE
- IWEVMICHAELMICFAILURE
- IWEVPMKIDCAND
- IWEVQUAL
- IWEVREGISTERED
- IWEVTXDROP
- IWL1000_FW_PRE
- IWL1000_MODULE_FIRMWARE
- IWL1000_UCODE_API_MAX
- IWL1000_UCODE_API_MIN
- IWL100_FW_PRE
- IWL100_MODULE_FIRMWARE
- IWL100_UCODE_API_MAX
- IWL100_UCODE_API_MIN
- IWL105_FW_PRE
- IWL105_MODULE_FIRMWARE
- IWL105_UCODE_API_MAX
- IWL105_UCODE_API_MIN
- IWL135_FW_PRE
- IWL135_MODULE_FIRMWARE
- IWL135_UCODE_API_MAX
- IWL135_UCODE_API_MIN
- IWL2000_FW_PRE
- IWL2000_MODULE_FIRMWARE
- IWL2000_UCODE_API_MAX
- IWL2000_UCODE_API_MIN
- IWL2030_FW_PRE
- IWL2030_MODULE_FIRMWARE
- IWL2030_UCODE_API_MAX
- IWL2030_UCODE_API_MIN
- IWL3160_DCCM_LEN
- IWL3160_FW_PRE
- IWL3160_MODULE_FIRMWARE
- IWL3160_NVM_VERSION
- IWL3165_NVM_VERSION
- IWL3168_FW_PRE
- IWL3168_MODULE_FIRMWARE
- IWL3168_NVM_VERSION
- IWL3168_UCODE_API_MAX
- IWL3168_UCODE_API_MIN
- IWL5000_FW_PRE
- IWL5000_MODULE_FIRMWARE
- IWL5000_UCODE_API_MAX
- IWL5000_UCODE_API_MIN
- IWL5150_FW_PRE
- IWL5150_MODULE_FIRMWARE
- IWL5150_UCODE_API_MAX
- IWL5150_UCODE_API_MIN
- IWL6000G2_UCODE_API_MAX
- IWL6000G2_UCODE_API_MIN
- IWL6000_FW_PRE
- IWL6000_MODULE_FIRMWARE
- IWL6000_UCODE_API_MAX
- IWL6000_UCODE_API_MIN
- IWL6005_FW_PRE
- IWL6005_MODULE_FIRMWARE
- IWL6030_FW_PRE
- IWL6030_MODULE_FIRMWARE
- IWL6035_UCODE_API_MAX
- IWL6035_UCODE_API_MIN
- IWL6050_FW_PRE
- IWL6050_MODULE_FIRMWARE
- IWL6050_UCODE_API_MAX
- IWL6050_UCODE_API_MIN
- IWL60_RTC_DATA_LOWER_BOUND
- IWL60_RTC_DATA_SIZE
- IWL60_RTC_DATA_UPPER_BOUND
- IWL60_RTC_INST_LOWER_BOUND
- IWL60_RTC_INST_SIZE
- IWL60_RTC_INST_UPPER_BOUND
- IWL7000_DCCM_OFFSET
- IWL7260_DCCM_LEN
- IWL7260_FW_PRE
- IWL7260_MODULE_FIRMWARE
- IWL7260_NVM_VERSION
- IWL7260_UCODE_API_MAX
- IWL7260_UCODE_API_MIN
- IWL7265D_FW_PRE
- IWL7265D_MODULE_FIRMWARE
- IWL7265D_NVM_VERSION
- IWL7265D_UCODE_API_MAX
- IWL7265D_UCODE_API_MIN
- IWL7265_DCCM_LEN
- IWL7265_FW_PRE
- IWL7265_MODULE_FIRMWARE
- IWL7265_NVM_VERSION
- IWL7265_UCODE_API_MAX
- IWL7265_UCODE_API_MIN
- IWL8000_FW_PRE
- IWL8000_MODULE_FIRMWARE
- IWL8000_NVM_VERSION
- IWL8000_UCODE_API_MAX
- IWL8000_UCODE_API_MIN
- IWL8260_DCCM2_LEN
- IWL8260_DCCM2_OFFSET
- IWL8260_DCCM_LEN
- IWL8260_DCCM_OFFSET
- IWL8260_ICCM_LEN
- IWL8260_ICCM_OFFSET
- IWL8260_SMEM_LEN
- IWL8260_SMEM_OFFSET
- IWL8265_FW_PRE
- IWL8265_MODULE_FIRMWARE
- IWL8265_UCODE_API_MAX
- IWL8265_UCODE_API_MIN
- IWL9000_DCCM2_LEN
- IWL9000_DCCM2_OFFSET
- IWL9000_DCCM_LEN
- IWL9000_DCCM_OFFSET
- IWL9000_FW_PRE
- IWL9000_MODULE_FIRMWARE
- IWL9000_NVM_VERSION
- IWL9000_SMEM_LEN
- IWL9000_SMEM_OFFSET
- IWL9000_UCODE_API_MAX
- IWL9000_UCODE_API_MIN
- IWL9260_FW_PRE
- IWL9260_MODULE_FIRMWARE
- IWLAGN_BAR_DFAULT_RETRY_LIMIT
- IWLAGN_BROADCAST_ID
- IWLAGN_BT3_PRIO_SAMPLE_DEFAULT
- IWLAGN_BT3_T2_DEFAULT
- IWLAGN_BT3_T7_DEFAULT
- IWLAGN_BT_ALL_VALID_MSK
- IWLAGN_BT_DECISION_LUT_SIZE
- IWLAGN_BT_FLAG_CHANNEL_INHIBITION
- IWLAGN_BT_FLAG_COEX_MODE_3W
- IWLAGN_BT_FLAG_COEX_MODE_4W
- IWLAGN_BT_FLAG_COEX_MODE_DISABLED
- IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W
- IWLAGN_BT_FLAG_COEX_MODE_MASK
- IWLAGN_BT_FLAG_COEX_MODE_SHIFT
- IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE
- IWLAGN_BT_FLAG_UCODE_DEFAULT
- IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE
- IWLAGN_BT_KILL_ACK_CTS_MASK_SCO
- IWLAGN_BT_KILL_ACK_MASK_DEFAULT
- IWLAGN_BT_KILL_CTS_MASK_DEFAULT
- IWLAGN_BT_MAX_KILL_DEFAULT
- IWLAGN_BT_PRIO_BOOST_DEFAULT
- IWLAGN_BT_PRIO_BOOST_DEFAULT32
- IWLAGN_BT_PRIO_BOOST_MAX
- IWLAGN_BT_PRIO_BOOST_MIN
- IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD
- IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD
- IWLAGN_BT_REDUCED_TX_PWR
- IWLAGN_BT_SCO_ACTIVE
- IWLAGN_BT_VALID_3W_LUT
- IWLAGN_BT_VALID_3W_TIMERS
- IWLAGN_BT_VALID_BOOST
- IWLAGN_BT_VALID_ENABLE_FLAGS
- IWLAGN_BT_VALID_KILL_ACK_MASK
- IWLAGN_BT_VALID_KILL_CTS_MASK
- IWLAGN_BT_VALID_MAX_KILL
- IWLAGN_BT_VALID_REDUCED_TX_PWR
- IWLAGN_CMD_FIFO_NUM
- IWLAGN_D3_WAKEUP_RFKILL
- IWLAGN_D3_WAKEUP_SYSASSERT
- IWLAGN_DEFAULT_TX_RETRY
- IWLAGN_EEPROM_IMG_SIZE
- IWLAGN_EXT_BEACON_TIME_POS
- IWLAGN_FIRST_AMPDU_QUEUE
- IWLAGN_HW_KEY_DEFAULT
- IWLAGN_KCK_MAX_SIZE
- IWLAGN_KEK_MAX_SIZE
- IWLAGN_LOW_RETRY_LIMIT
- IWLAGN_MGMT_DFAULT_RETRY_LIMIT
- IWLAGN_MIC_KEY_SIZE
- IWLAGN_NUM_QUEUES
- IWLAGN_NUM_RSC
- IWLAGN_NUM_RX_P1K_CACHE
- IWLAGN_OFDM_AGC_BIT_POS
- IWLAGN_OFDM_AGC_MSK
- IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK
- IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK
- IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK
- IWLAGN_OFDM_RSSI_A_BIT_POS
- IWLAGN_OFDM_RSSI_B_BIT_POS
- IWLAGN_OFDM_RSSI_C_BIT_POS
- IWLAGN_OFDM_RSSI_INBAND_A_BITMSK
- IWLAGN_OFDM_RSSI_INBAND_B_BITMSK
- IWLAGN_OFDM_RSSI_INBAND_C_BITMSK
- IWLAGN_P1K_SIZE
- IWLAGN_PAN_BCAST_ID
- IWLAGN_RSSI_OFFSET
- IWLAGN_RTC_DATA_LOWER_BOUND
- IWLAGN_RTC_DATA_SIZE
- IWLAGN_RTC_DATA_UPPER_BOUND
- IWLAGN_RTC_INST_LOWER_BOUND
- IWLAGN_RTC_INST_SIZE
- IWLAGN_RTC_INST_UPPER_BOUND
- IWLAGN_RTS_DFAULT_RETRY_LIMIT
- IWLAGN_RX_RES_AGC_IDX
- IWLAGN_RX_RES_PHY_CNT
- IWLAGN_RX_RES_RSSI_AB_IDX
- IWLAGN_RX_RES_RSSI_C_IDX
- IWLAGN_STATION_COUNT
- IWLAGN_TX_POWER_AUTO
- IWLAGN_TX_POWER_NO_CLOSED
- IWLAGN_TX_POWER_TARGET_POWER_MAX
- IWLAGN_TX_POWER_TARGET_POWER_MIN
- IWLAGN_TX_RES_RA_MSK
- IWLAGN_TX_RES_RA_POS
- IWLAGN_TX_RES_TID_MSK
- IWLAGN_TX_RES_TID_POS
- IWLAGN_WOWLAN_MAX_PATTERNS
- IWLAGN_WOWLAN_MAX_PATTERN_LEN
- IWLAGN_WOWLAN_MIN_PATTERN_LEN
- IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE
- IWLAGN_WOWLAN_WAKEUP_ALWAYS
- IWLAGN_WOWLAN_WAKEUP_BEACON_MISS
- IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ
- IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT
- IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL
- IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE
- IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET
- IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH
- IWLWIFI_VERSION
- IWL_22000_DCCM2_LEN
- IWL_22000_DCCM2_OFFSET
- IWL_22000_DCCM_LEN
- IWL_22000_DCCM_OFFSET
- IWL_22000_HR_A0_FW_PRE
- IWL_22000_HR_A0_QNJ_MODULE_FIRMWARE
- IWL_22000_HR_A_F0_FW_PRE
- IWL_22000_HR_A_F0_QNJ_MODULE_FIRMWARE
- IWL_22000_HR_B_FW_PRE
- IWL_22000_HR_B_QNJ_MODULE_FIRMWARE
- IWL_22000_HR_CDB_FW_PRE
- IWL_22000_HR_FW_PRE
- IWL_22000_HR_MODULE_FIRMWARE
- IWL_22000_JF_FW_PRE
- IWL_22000_JF_MODULE_FIRMWARE
- IWL_22000_NVM_VERSION
- IWL_22000_QU_B_HR_B_FW_PRE
- IWL_22000_QU_B_HR_B_MODULE_FIRMWARE
- IWL_22000_SMEM_LEN
- IWL_22000_SMEM_OFFSET
- IWL_22000_SO_A_GF4_A_FW_PRE
- IWL_22000_SO_A_GF_A_FW_PRE
- IWL_22000_SO_A_GF_A_MODULE_FIRMWARE
- IWL_22000_SO_A_HR_B_FW_PRE
- IWL_22000_SO_A_HR_B_MODULE_FIRMWARE
- IWL_22000_SO_A_JF_B_FW_PRE
- IWL_22000_SO_A_JF_B_MODULE_FIRMWARE
- IWL_22000_TY_A_GF_A_FW_PRE
- IWL_22000_TY_A_GF_A_MODULE_FIRMWARE
- IWL_22000_UCODE_API_MAX
- IWL_22000_UCODE_API_MIN
- IWL_4165_DEVICE_ID
- IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF
- IWL_ABSOLUTE_MAX
- IWL_ABSOLUTE_ZERO
- IWL_ACTION_LIMIT
- IWL_ACTIVE_DWELL_FACTOR_24GHZ
- IWL_ACTIVE_DWELL_FACTOR_52GHZ
- IWL_ACTIVE_DWELL_TIME_24
- IWL_ACTIVE_DWELL_TIME_52
- IWL_ACTIVE_QUIET_TIME
- IWL_ADD_STA_BAID_MASK
- IWL_ADD_STA_BAID_SHIFT
- IWL_ADD_STA_BAID_VALID_MASK
- IWL_ADD_STA_STATUS_MASK
- IWL_AGG_ALL_TID
- IWL_AGG_LOAD_THRESHOLD
- IWL_AGG_OFF
- IWL_AGG_ON
- IWL_AGG_QUEUED
- IWL_AGG_STARTING
- IWL_AGG_TPT_THREHOLD
- IWL_AGG_TX_QUEUE_MSK
- IWL_ALIVE_FLG_RFKILL
- IWL_ALIVE_STATUS_ERR
- IWL_ALIVE_STATUS_OK
- IWL_ALWAYS_LONG_GROUP
- IWL_AMSDU_12K
- IWL_AMSDU_2K
- IWL_AMSDU_4K
- IWL_AMSDU_8K
- IWL_AMSDU_DEF
- IWL_ANT_OK_MULTI
- IWL_ANT_OK_NONE
- IWL_ANT_OK_SINGLE
- IWL_AP_ID
- IWL_AP_ID_PAN
- IWL_AUX_QUEUE
- IWL_BAR_DFAULT_RETRY_LIMIT
- IWL_BAR_FRAME_RELEASE_BAID_MASK
- IWL_BAR_FRAME_RELEASE_NSSN_MASK
- IWL_BAR_FRAME_RELEASE_SN_MASK
- IWL_BAR_FRAME_RELEASE_STA_MASK
- IWL_BAR_FRAME_RELEASE_TID_MASK
- IWL_BA_ENABLE_BEACON_ABORT_DEFAULT
- IWL_BA_ESCAPE_TIMER_D0I3
- IWL_BA_ESCAPE_TIMER_D3
- IWL_BA_ESCAPE_TIMER_DEFAULT
- IWL_BA_ESCAPE_TIMER_MAX
- IWL_BA_ESCAPE_TIMER_MIN
- IWL_BF_CMD_CONFIG
- IWL_BF_CMD_CONFIG_D0I3
- IWL_BF_CMD_CONFIG_DEFAULTS
- IWL_BF_DEBUG_FLAG_D0I3
- IWL_BF_DEBUG_FLAG_DEFAULT
- IWL_BF_ENABLE_BEACON_FILTER_DEFAULT
- IWL_BF_ENERGY_DELTA_D0I3
- IWL_BF_ENERGY_DELTA_DEFAULT
- IWL_BF_ENERGY_DELTA_MAX
- IWL_BF_ENERGY_DELTA_MIN
- IWL_BF_ESCAPE_TIMER_D0I3
- IWL_BF_ESCAPE_TIMER_DEFAULT
- IWL_BF_ESCAPE_TIMER_MAX
- IWL_BF_ESCAPE_TIMER_MIN
- IWL_BF_ROAMING_ENERGY_DELTA_D0I3
- IWL_BF_ROAMING_ENERGY_DELTA_DEFAULT
- IWL_BF_ROAMING_ENERGY_DELTA_MAX
- IWL_BF_ROAMING_ENERGY_DELTA_MIN
- IWL_BF_ROAMING_STATE_D0I3
- IWL_BF_ROAMING_STATE_DEFAULT
- IWL_BF_ROAMING_STATE_MAX
- IWL_BF_ROAMING_STATE_MIN
- IWL_BF_TEMP_FAST_FILTER_D0I3
- IWL_BF_TEMP_FAST_FILTER_DEFAULT
- IWL_BF_TEMP_FAST_FILTER_MAX
- IWL_BF_TEMP_FAST_FILTER_MIN
- IWL_BF_TEMP_SLOW_FILTER_D0I3
- IWL_BF_TEMP_SLOW_FILTER_DEFAULT
- IWL_BF_TEMP_SLOW_FILTER_MAX
- IWL_BF_TEMP_SLOW_FILTER_MIN
- IWL_BF_TEMP_THRESHOLD_D0I3
- IWL_BF_TEMP_THRESHOLD_DEFAULT
- IWL_BF_TEMP_THRESHOLD_MAX
- IWL_BF_TEMP_THRESHOLD_MIN
- IWL_BINDING_CMD_SIZE_V1
- IWL_BT_ANTENNA_COUPLING_THRESHOLD
- IWL_BT_COEX_ENV_CLOSE
- IWL_BT_COEX_ENV_OPEN
- IWL_BT_COEX_PRIO_TBL_PRIO_MASK
- IWL_BT_COEX_PRIO_TBL_PRIO_POS
- IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT
- IWL_BT_COEX_PRIO_TBL_RESERVED_MASK
- IWL_BT_COEX_PRIO_TBL_RESERVED_POS
- IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK
- IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS
- IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS
- IWL_BT_COEX_TRAFFIC_LOAD_HIGH
- IWL_BT_COEX_TRAFFIC_LOAD_LOW
- IWL_BT_COEX_TRAFFIC_LOAD_NONE
- IWL_BT_KILL_DEFAULT
- IWL_BT_KILL_OVERRIDE
- IWL_BT_KILL_REDUCE
- IWL_CALIB_CFG_ABS_IDX
- IWL_CALIB_CFG_AGC_IDX
- IWL_CALIB_CFG_ANT_COUPLING_IDX
- IWL_CALIB_CFG_BB_FILTER_IDX
- IWL_CALIB_CFG_CHAIN_NOISE_IDX
- IWL_CALIB_CFG_CRYSTAL_IDX
- IWL_CALIB_CFG_DAC_IDX
- IWL_CALIB_CFG_DC_IDX
- IWL_CALIB_CFG_DISCONNECTED_ANT_IDX
- IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK
- IWL_CALIB_CFG_LO_IDX
- IWL_CALIB_CFG_LO_LEAKAGE_IDX
- IWL_CALIB_CFG_NOISE_IDX
- IWL_CALIB_CFG_PAPD_IDX
- IWL_CALIB_CFG_RX_BB_IDX
- IWL_CALIB_CFG_RX_IQ_IDX
- IWL_CALIB_CFG_RX_IQ_SKEW_IDX
- IWL_CALIB_CFG_SENSITIVITY_IDX
- IWL_CALIB_CFG_TEMPERATURE_IDX
- IWL_CALIB_CFG_TX_IQ_IDX
- IWL_CALIB_CFG_TX_IQ_SKEW_IDX
- IWL_CALIB_CFG_TX_PWR_IDX
- IWL_CALIB_CFG_VOLTAGE_READ_IDX
- IWL_CALIB_CFG_XTAL_IDX
- IWL_CALIB_DISABLE_ALL
- IWL_CALIB_ENABLE_ALL
- IWL_CALIB_INIT_CFG_ALL
- IWL_CALIB_RT_CFG_ALL
- IWL_CAL_NUM_BEACONS
- IWL_CC_A_FW_PRE
- IWL_CC_A_MODULE_FIRMWARE
- IWL_CHAIN_NOISE_ACCUMULATE
- IWL_CHAIN_NOISE_ALIVE
- IWL_CHAIN_NOISE_CALIBRATED
- IWL_CHAIN_NOISE_CALIB_DISABLED
- IWL_CHAIN_NOISE_DONE
- IWL_CHANNEL_ESTIMATION_COUNTER
- IWL_CHANNEL_ESTIMATION_ENABLE
- IWL_CHANNEL_ESTIMATION_TIMER
- IWL_CHANNEL_FLAG_ACCURATE_EBS
- IWL_CHANNEL_FLAG_EBS
- IWL_CHANNEL_FLAG_EBS_ADD
- IWL_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE
- IWL_CHANNEL_TUNE_TIME
- IWL_CMD
- IWL_CMD_MQ
- IWL_CMD_QUEUE_SIZE
- IWL_CONN_MAX_LISTEN_INTERVAL
- IWL_CRIT
- IWL_CSI_CHUNK_CTL_IDX_MASK_VER_1
- IWL_CSI_CHUNK_CTL_IDX_MASK_VER_2
- IWL_CSI_CHUNK_CTL_NUM_MASK_VER_1
- IWL_CSI_CHUNK_CTL_NUM_MASK_VER_2
- IWL_CSI_MAX_EXPECTED_CHUNKS
- IWL_CSR_TO_DUMP
- IWL_CTXT_INFO_AUTO_FUNC_INIT
- IWL_CTXT_INFO_EARLY_DEBUG
- IWL_CTXT_INFO_ENABLE_CDMP
- IWL_CTXT_INFO_RB_CB_SIZE_POS
- IWL_CTXT_INFO_RB_SIZE_12K
- IWL_CTXT_INFO_RB_SIZE_16K
- IWL_CTXT_INFO_RB_SIZE_1K
- IWL_CTXT_INFO_RB_SIZE_20K
- IWL_CTXT_INFO_RB_SIZE_24K
- IWL_CTXT_INFO_RB_SIZE_28K
- IWL_CTXT_INFO_RB_SIZE_2K
- IWL_CTXT_INFO_RB_SIZE_32K
- IWL_CTXT_INFO_RB_SIZE_4K
- IWL_CTXT_INFO_RB_SIZE_8K
- IWL_CTXT_INFO_RB_SIZE_POS
- IWL_CTXT_INFO_TFD_FORMAT_LONG
- IWL_D3_PROTO_IPV4_VALID
- IWL_D3_PROTO_IPV6_VALID
- IWL_D3_PROTO_OFFLOAD_ARP
- IWL_D3_PROTO_OFFLOAD_NS
- IWL_D3_SLEEP_STATUS_RESUME
- IWL_D3_SLEEP_STATUS_SUSPEND
- IWL_D3_STATUS_ALIVE
- IWL_D3_STATUS_RESET
- IWL_DBG_TLV_TYPE_BUF_ALLOC
- IWL_DBG_TLV_TYPE_DEBUG_INFO
- IWL_DBG_TLV_TYPE_HCMD
- IWL_DBG_TLV_TYPE_NUM
- IWL_DBG_TLV_TYPE_REGION
- IWL_DBG_TLV_TYPE_TRIGGER
- IWL_DEBUG
- IWL_DEBUG_11H
- IWL_DEBUG_ASSOC
- IWL_DEBUG_ASSOC_LIMIT
- IWL_DEBUG_CALIB
- IWL_DEBUG_COEX
- IWL_DEBUG_DEV
- IWL_DEBUG_DEV_RADIO
- IWL_DEBUG_DROP
- IWL_DEBUG_DROP_LIMIT
- IWL_DEBUG_EEPROM
- IWL_DEBUG_EXTERNAL
- IWL_DEBUG_FW
- IWL_DEBUG_FW_INFO
- IWL_DEBUG_HC
- IWL_DEBUG_HT
- IWL_DEBUG_INFO
- IWL_DEBUG_ISR
- IWL_DEBUG_LAR
- IWL_DEBUG_LIMIT
- IWL_DEBUG_MAC80211
- IWL_DEBUG_POWER
- IWL_DEBUG_QUIET_RFKILL
- IWL_DEBUG_QUOTA
- IWL_DEBUG_RADIO
- IWL_DEBUG_RATE
- IWL_DEBUG_RATE_LIMIT
- IWL_DEBUG_RF_KILL
- IWL_DEBUG_RPM
- IWL_DEBUG_RX
- IWL_DEBUG_SCAN
- IWL_DEBUG_STATS
- IWL_DEBUG_STATS_LIMIT
- IWL_DEBUG_TDLS
- IWL_DEBUG_TE
- IWL_DEBUG_TEMP
- IWL_DEBUG_TPT
- IWL_DEBUG_TX
- IWL_DEBUG_TX_QUEUES
- IWL_DEBUG_TX_REPLY
- IWL_DEBUG_WEP
- IWL_DECLARE_MCS_RATE
- IWL_DECLARE_RATE_INFO
- IWL_DEFAULT_CMD_QUEUE_NUM
- IWL_DEFAULT_MAX_PROBE_LENGTH
- IWL_DEFAULT_MAX_TX_POWER
- IWL_DEFAULT_QUEUE_SIZE
- IWL_DEFAULT_SCAN_CHANNELS
- IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE
- IWL_DEFAULT_TX_RETRY
- IWL_DEF_LED_INTRVL
- IWL_DEF_WD_TIMEOUT
- IWL_DELAY_NEXT_FORCE_RF_RESET
- IWL_DENSE_EBS_SCAN_RATIO
- IWL_DEVICE_100
- IWL_DEVICE_1000
- IWL_DEVICE_105
- IWL_DEVICE_135
- IWL_DEVICE_2000
- IWL_DEVICE_2030
- IWL_DEVICE_22000_COMMON
- IWL_DEVICE_22500
- IWL_DEVICE_22560
- IWL_DEVICE_3008
- IWL_DEVICE_5000
- IWL_DEVICE_5150
- IWL_DEVICE_6000i
- IWL_DEVICE_6005
- IWL_DEVICE_6030
- IWL_DEVICE_6035
- IWL_DEVICE_6050
- IWL_DEVICE_6150
- IWL_DEVICE_7000
- IWL_DEVICE_7000_COMMON
- IWL_DEVICE_7005
- IWL_DEVICE_7005D
- IWL_DEVICE_8000
- IWL_DEVICE_8000_COMMON
- IWL_DEVICE_8260
- IWL_DEVICE_8265
- IWL_DEVICE_9000
- IWL_DEVICE_AX210
- IWL_DEVICE_FAMILY_100
- IWL_DEVICE_FAMILY_1000
- IWL_DEVICE_FAMILY_105
- IWL_DEVICE_FAMILY_135
- IWL_DEVICE_FAMILY_2000
- IWL_DEVICE_FAMILY_2030
- IWL_DEVICE_FAMILY_22000
- IWL_DEVICE_FAMILY_22560
- IWL_DEVICE_FAMILY_5000
- IWL_DEVICE_FAMILY_5150
- IWL_DEVICE_FAMILY_6000
- IWL_DEVICE_FAMILY_6000i
- IWL_DEVICE_FAMILY_6005
- IWL_DEVICE_FAMILY_6030
- IWL_DEVICE_FAMILY_6050
- IWL_DEVICE_FAMILY_6150
- IWL_DEVICE_FAMILY_7000
- IWL_DEVICE_FAMILY_8000
- IWL_DEVICE_FAMILY_9000
- IWL_DEVICE_FAMILY_AX210
- IWL_DEVICE_FAMILY_UNDEFINED
- IWL_DEV_MAX_TX_POWER
- IWL_DISABLE_HT_ALL
- IWL_DISABLE_HT_RXAGG
- IWL_DISABLE_HT_TXAGG
- IWL_DISABLE_UAPSD_BSS
- IWL_DISABLE_UAPSD_P2P_CLIENT
- IWL_DL_11H
- IWL_DL_ASSOC
- IWL_DL_CALIB
- IWL_DL_COEX
- IWL_DL_DROP
- IWL_DL_EEPROM
- IWL_DL_EXTERNAL
- IWL_DL_FW
- IWL_DL_HCMD
- IWL_DL_HT
- IWL_DL_INFO
- IWL_DL_ISR
- IWL_DL_LAR
- IWL_DL_MAC80211
- IWL_DL_POWER
- IWL_DL_QUOTA
- IWL_DL_RADIO
- IWL_DL_RATE
- IWL_DL_RF_KILL
- IWL_DL_RPM
- IWL_DL_RX
- IWL_DL_SCAN
- IWL_DL_STATS
- IWL_DL_TDLS
- IWL_DL_TE
- IWL_DL_TEMP
- IWL_DL_TPT
- IWL_DL_TX
- IWL_DL_TX_QUEUES
- IWL_DL_TX_REPLY
- IWL_DL_WEP
- IWL_DROP_ALL
- IWL_DTIM_RANGE_0_MAX
- IWL_DTIM_RANGE_1_MAX
- IWL_EEPROM_ACCESS_TIMEOUT
- IWL_EEPROM_ENH_TXP_FL_40MHZ
- IWL_EEPROM_ENH_TXP_FL_BAND_52G
- IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE
- IWL_EEPROM_ENH_TXP_FL_HT_AP
- IWL_EEPROM_ENH_TXP_FL_OFDM
- IWL_EEPROM_ENH_TXP_FL_RES1
- IWL_EEPROM_ENH_TXP_FL_RES2
- IWL_EEPROM_ENH_TXP_FL_VALID
- IWL_EEPROM_SEM_RETRY_LIMIT
- IWL_EEPROM_SEM_TIMEOUT
- IWL_EMPTYING_HW_QUEUE_ADDBA
- IWL_EMPTYING_HW_QUEUE_DELBA
- IWL_ENABLE_HT_TXAGG
- IWL_ERR
- IWL_ERROR_EVENT_TABLE_LMAC1
- IWL_ERROR_EVENT_TABLE_LMAC2
- IWL_ERROR_EVENT_TABLE_UMAC
- IWL_ERR_DEV
- IWL_EXPORT_SYMBOL
- IWL_FAST_SCHED_SCAN_ITERATIONS
- IWL_FA_GOOD_RANGE
- IWL_FA_TOO_FEW
- IWL_FA_TOO_MANY
- IWL_FIRST_CCK_RATE
- IWL_FIRST_HT_RATE
- IWL_FIRST_OFDM_RATE
- IWL_FIRST_TB_SIZE
- IWL_FIRST_TB_SIZE_ALIGN
- IWL_FIRST_VHT_RATE
- IWL_FLUSH_WAIT_MS
- IWL_FRAME_LIMIT
- IWL_FULL_SCAN_MULTIPLIER
- IWL_FW_CMD_VER_UNKNOWN
- IWL_FW_DBG_CONF_VIF_ANY
- IWL_FW_DBG_CONF_VIF_AP
- IWL_FW_DBG_CONF_VIF_IBSS
- IWL_FW_DBG_CONF_VIF_P2P_CLIENT
- IWL_FW_DBG_CONF_VIF_P2P_DEVICE
- IWL_FW_DBG_CONF_VIF_P2P_GO
- IWL_FW_DBG_CONF_VIF_STATION
- IWL_FW_DBG_FORCE_RESTART
- IWL_FW_DBG_TRIGGER_MONITOR_ONLY
- IWL_FW_DBG_TRIGGER_START
- IWL_FW_DBG_TRIGGER_STOP
- IWL_FW_DVM
- IWL_FW_ERROR_DUMP_BARKER
- IWL_FW_ERROR_DUMP_CSR
- IWL_FW_ERROR_DUMP_D3_DEBUG_DATA
- IWL_FW_ERROR_DUMP_DEV_FW_INFO
- IWL_FW_ERROR_DUMP_ERROR_INFO
- IWL_FW_ERROR_DUMP_EXTERNAL
- IWL_FW_ERROR_DUMP_FAMILY_7
- IWL_FW_ERROR_DUMP_FAMILY_8
- IWL_FW_ERROR_DUMP_FH_REGS
- IWL_FW_ERROR_DUMP_FW_MONITOR
- IWL_FW_ERROR_DUMP_INTERNAL_TXF
- IWL_FW_ERROR_DUMP_MAX
- IWL_FW_ERROR_DUMP_MEM
- IWL_FW_ERROR_DUMP_MEM_CFG
- IWL_FW_ERROR_DUMP_MEM_NAMED_MEM
- IWL_FW_ERROR_DUMP_MEM_SMEM
- IWL_FW_ERROR_DUMP_MEM_SRAM
- IWL_FW_ERROR_DUMP_PAGING
- IWL_FW_ERROR_DUMP_PRPH
- IWL_FW_ERROR_DUMP_RADIO_REG
- IWL_FW_ERROR_DUMP_RB
- IWL_FW_ERROR_DUMP_RXF
- IWL_FW_ERROR_DUMP_TXCMD
- IWL_FW_ERROR_DUMP_TXF
- IWL_FW_INI_ALLOCATION_ID_DBGC1
- IWL_FW_INI_ALLOCATION_ID_DBGC2
- IWL_FW_INI_ALLOCATION_ID_DBGC3
- IWL_FW_INI_ALLOCATION_ID_FW_DUMP
- IWL_FW_INI_ALLOCATION_ID_SDFX
- IWL_FW_INI_ALLOCATION_ID_USER_DEFINED
- IWL_FW_INI_ALLOCATION_INVALID
- IWL_FW_INI_ALLOCATION_NUM
- IWL_FW_INI_DBG_DOMAIN_ALWAYS_ON
- IWL_FW_INI_DBG_DOMAIN_REPORT_PS
- IWL_FW_INI_DEBUG_DBTR_FLOW
- IWL_FW_INI_DEBUG_INVALID
- IWL_FW_INI_DEBUG_TB2DTF_FLOW
- IWL_FW_INI_ERROR_DUMP_BARKER
- IWL_FW_INI_LOCATION_DRAM_PATH
- IWL_FW_INI_LOCATION_INVALID
- IWL_FW_INI_LOCATION_NPK_PATH
- IWL_FW_INI_LOCATION_SRAM_PATH
- IWL_FW_INI_MAX_DBG_CFG_NAME_LEN
- IWL_FW_INI_MAX_IMG_NAME_LEN
- IWL_FW_INI_MAX_NAME
- IWL_FW_INI_MAX_REGION_ID
- IWL_FW_INI_REGION_CSR
- IWL_FW_INI_REGION_DEVICE_MEMORY
- IWL_FW_INI_REGION_DHC
- IWL_FW_INI_REGION_DRAM_BUFFER
- IWL_FW_INI_REGION_DRAM_IMR
- IWL_FW_INI_REGION_INTERNAL_BUFFER
- IWL_FW_INI_REGION_INVALID
- IWL_FW_INI_REGION_LMAC_ERROR_TABLE
- IWL_FW_INI_REGION_NOTIFICATION
- IWL_FW_INI_REGION_NUM
- IWL_FW_INI_REGION_PAGING
- IWL_FW_INI_REGION_PERIPHERY_AUX
- IWL_FW_INI_REGION_PERIPHERY_MAC
- IWL_FW_INI_REGION_PERIPHERY_PHY
- IWL_FW_INI_REGION_RXF
- IWL_FW_INI_REGION_TXF
- IWL_FW_INI_REGION_UMAC_ERROR_TABLE
- IWL_FW_INI_TIME_POINT_AFTER_ALIVE
- IWL_FW_INI_TIME_POINT_ASSOC_FAILED
- IWL_FW_INI_TIME_POINT_DEASSOC
- IWL_FW_INI_TIME_POINT_EAPOL_FAILED
- IWL_FW_INI_TIME_POINT_EARLY
- IWL_FW_INI_TIME_POINT_FAKE_TX
- IWL_FW_INI_TIME_POINT_FW_ASSERT
- IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFOCATION
- IWL_FW_INI_TIME_POINT_FW_HW_ERROR
- IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF
- IWL_FW_INI_TIME_POINT_FW_TFD_Q_HANG
- IWL_FW_INI_TIME_POINT_HANG_OCCURRED
- IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT
- IWL_FW_INI_TIME_POINT_HOST_ASSERT
- IWL_FW_INI_TIME_POINT_HOST_D3_END
- IWL_FW_INI_TIME_POINT_HOST_D3_START
- IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE
- IWL_FW_INI_TIME_POINT_HOST_DEVICE_ENABLE
- IWL_FW_INI_TIME_POINT_INVALID
- IWL_FW_INI_TIME_POINT_MISSED_BEACONS
- IWL_FW_INI_TIME_POINT_NUM
- IWL_FW_INI_TIME_POINT_PERIODIC
- IWL_FW_INI_TIME_POINT_POST_INIT
- IWL_FW_INI_TIME_POINT_TX_FAILED
- IWL_FW_INI_TIME_POINT_TX_LATENCY_THRESHOLD
- IWL_FW_INI_TIME_POINT_TX_WFD_ACTION_FRAME_FAILED
- IWL_FW_INI_TIME_POINT_USER_TRIGGER
- IWL_FW_INI_TIME_POINT_WDG_TIMEOUT
- IWL_FW_MEM_EXTENDED_END
- IWL_FW_MEM_EXTENDED_START
- IWL_FW_MON_DBGFS_STATE_CLOSED
- IWL_FW_MON_DBGFS_STATE_DISABLED
- IWL_FW_MON_DBGFS_STATE_OPEN
- IWL_FW_MVM
- IWL_FW_RUNTIME_DUMP_WK_NUM
- IWL_FW_TRIGGER_ID_FW_ASSERT
- IWL_FW_TRIGGER_ID_FW_DEBUG_HOST_TRIGGER
- IWL_FW_TRIGGER_ID_FW_GENERIC_NOTIFICATION
- IWL_FW_TRIGGER_ID_FW_HW_ERROR
- IWL_FW_TRIGGER_ID_FW_TFD_Q_HANG
- IWL_FW_TRIGGER_ID_HOST_AGG_TX_RESPONSE_STATUS_FAILED
- IWL_FW_TRIGGER_ID_HOST_AUTH_ASSOC_FAILED
- IWL_FW_TRIGGER_ID_HOST_AUTH_ASSOC_FAST_FAILED
- IWL_FW_TRIGGER_ID_HOST_AUTH_REQ_FROM_ASSOC_CLIENT
- IWL_FW_TRIGGER_ID_HOST_BAR_RECEIVED
- IWL_FW_TRIGGER_ID_HOST_BSS_MISSED_BEACONS
- IWL_FW_TRIGGER_ID_HOST_CHANNEL_SWITCH_COMPLETE
- IWL_FW_TRIGGER_ID_HOST_CHECK_FOR_HANG
- IWL_FW_TRIGGER_ID_HOST_D3_END
- IWL_FW_TRIGGER_ID_HOST_D3_START
- IWL_FW_TRIGGER_ID_HOST_EAPOL_TX_RESPONSE_FAILED
- IWL_FW_TRIGGER_ID_HOST_FAKE_TX_RESPONSE_SUSPECTED
- IWL_FW_TRIGGER_ID_HOST_JOIN_GROUP_REQUEST
- IWL_FW_TRIGGER_ID_HOST_NIC_ALIVE
- IWL_FW_TRIGGER_ID_HOST_OS_REQ_DEAUTH_PEER
- IWL_FW_TRIGGER_ID_HOST_P2P_CLIENT_MISSED_BEACONS
- IWL_FW_TRIGGER_ID_HOST_PEER_CLIENT_INACTIVITY
- IWL_FW_TRIGGER_ID_HOST_PEER_CLIENT_TX_FAILURES
- IWL_FW_TRIGGER_ID_HOST_ROAM_COMPLETE
- IWL_FW_TRIGGER_ID_HOST_SCAN_ABORT
- IWL_FW_TRIGGER_ID_HOST_SCAN_COMPLETE
- IWL_FW_TRIGGER_ID_HOST_SCAN_PARAMS
- IWL_FW_TRIGGER_ID_HOST_SCAN_START
- IWL_FW_TRIGGER_ID_HOST_SCAN_SUBMITTED
- IWL_FW_TRIGGER_ID_HOST_START_GO_REQUEST
- IWL_FW_TRIGGER_ID_HOST_STOP_GO_REQUEST
- IWL_FW_TRIGGER_ID_HOST_TX_LATENCY_THRESHOLD_CROSSED
- IWL_FW_TRIGGER_ID_HOST_TX_RESPONSE_STATUS_FAILED
- IWL_FW_TRIGGER_ID_HOST_TX_WFD_ACTION_FRAME_FAILED
- IWL_FW_TRIGGER_ID_INVALID
- IWL_FW_TRIGGER_ID_NUM
- IWL_FW_TRIGGER_ID_PERIODIC_TRIGGER
- IWL_FW_TRIGGER_ID_USER_TRIGGER
- IWL_GEN2_EDCA_TX_FIFO_BE
- IWL_GEN2_EDCA_TX_FIFO_BK
- IWL_GEN2_EDCA_TX_FIFO_VI
- IWL_GEN2_EDCA_TX_FIFO_VO
- IWL_GEN2_TRIG_TX_FIFO_BE
- IWL_GEN2_TRIG_TX_FIFO_BK
- IWL_GEN2_TRIG_TX_FIFO_VI
- IWL_GEN2_TRIG_TX_FIFO_VO
- IWL_GEN2_TX_FIFO_CMD
- IWL_GOOD_CRC_TH_DEFAULT
- IWL_GOOD_CRC_TH_DISABLED
- IWL_GOOD_CRC_TH_NEVER
- IWL_HCMD_DFL_DUP
- IWL_HCMD_DFL_NOCOPY
- IWL_HE_HTC_BQR_SUPP
- IWL_HE_HTC_BSR_SUPP
- IWL_HE_HTC_LINK_ADAP_BOTH
- IWL_HE_HTC_LINK_ADAP_NO_FEEDBACK
- IWL_HE_HTC_LINK_ADAP_POS
- IWL_HE_HTC_LINK_ADAP_UNSOLICITED
- IWL_HE_HTC_OMI_SUPP
- IWL_HE_HTC_SUPPORT
- IWL_HE_HTC_UL_MU_RESP_SCHED
- IWL_HE_PKT_EXT_1024QAM
- IWL_HE_PKT_EXT_16QAM
- IWL_HE_PKT_EXT_256QAM
- IWL_HE_PKT_EXT_64QAM
- IWL_HE_PKT_EXT_BPSK
- IWL_HE_PKT_EXT_NONE
- IWL_HE_PKT_EXT_QPSK
- IWL_HE_PKT_EXT_RESERVED
- IWL_HOST_INT_OPER_MODE
- IWL_HOST_INT_TIMEOUT_DEF
- IWL_HOST_INT_TIMEOUT_MAX
- IWL_HOST_INT_TIMEOUT_MIN
- IWL_HT_NUMBER_TRY
- IWL_IBSS_MANAGER
- IWL_IMAGE_RESP_DEF
- IWL_IMAGE_RESP_FAIL
- IWL_IMAGE_RESP_SUCCESS
- IWL_INFO
- IWL_INITIATOR_AP_FLAGS_ALGO_FFT
- IWL_INITIATOR_AP_FLAGS_ALGO_LR
- IWL_INITIATOR_AP_FLAGS_ASAP
- IWL_INITIATOR_AP_FLAGS_CIVIC_REQUEST
- IWL_INITIATOR_AP_FLAGS_DYN_ACK
- IWL_INITIATOR_AP_FLAGS_LCI_REQUEST
- IWL_INITIATOR_AP_FLAGS_MCSI_REPORT
- IWL_INIT_DEBUG_CFG
- IWL_INIT_NVM
- IWL_INIT_PHY
- IWL_INI_CFG_STATE_CORRUPTED
- IWL_INI_CFG_STATE_LOADED
- IWL_INI_CFG_STATE_NOT_LOADED
- IWL_INI_DUMP_INFO_TYPE
- IWL_INI_DUMP_VER
- IWL_INVALID_MAC80211_QUEUE
- IWL_INVALID_RATE
- IWL_INVALID_STATION
- IWL_INVALID_VALUE
- IWL_IPAN_CMD_QUEUE_NUM
- IWL_IPAN_MCAST_QUEUE
- IWL_KCK_MAX_SIZE
- IWL_KEK_MAX_SIZE
- IWL_KW_SIZE
- IWL_LAST_CCK_RATE
- IWL_LAST_HE_RATE
- IWL_LAST_HT_RATE
- IWL_LAST_NON_HT_RATE
- IWL_LAST_OFDM_RATE
- IWL_LAST_VHT_RATE
- IWL_LCI_CIVIC_IE_MAX_SIZE
- IWL_LDBG_M2S_BUF_BA_MSK
- IWL_LDBG_M2S_BUF_SIZE_MSK
- IWL_LED_ACTIVITY
- IWL_LED_BLINK
- IWL_LED_DEFAULT
- IWL_LED_DISABLE
- IWL_LED_LINK
- IWL_LED_RF_STATE
- IWL_LED_SOLID
- IWL_LEGACY_FAILURE_LIMIT
- IWL_LEGACY_SUCCESS_LIMIT
- IWL_LEGACY_SWITCH_ANTENNA1
- IWL_LEGACY_SWITCH_ANTENNA2
- IWL_LEGACY_SWITCH_MIMO2_AB
- IWL_LEGACY_SWITCH_MIMO2_AC
- IWL_LEGACY_SWITCH_MIMO2_BC
- IWL_LEGACY_SWITCH_MIMO3_ABC
- IWL_LEGACY_SWITCH_SISO
- IWL_LEGACY_TABLE_COUNT
- IWL_LMAC_24G_INDEX
- IWL_LMAC_5G_INDEX
- IWL_LONG_WD_TIMEOUT
- IWL_LOW_RETRY_LIMIT
- IWL_M2S_UNIT_SIZE
- IWL_MAC80211_GET_DVM
- IWL_MAC80211_GET_MVM
- IWL_MAC_BEACON_ANT_A
- IWL_MAC_BEACON_ANT_B
- IWL_MAC_BEACON_ANT_C
- IWL_MAC_BEACON_CCK
- IWL_MASK
- IWL_MAX_11N_MIMO3_SEARCH
- IWL_MAX_BAID
- IWL_MAX_CMD_SIZE
- IWL_MAX_CMD_TBS_PER_TFD
- IWL_MAX_CONTINUE_RELOAD_CNT
- IWL_MAX_CSA_BLOCK_TX
- IWL_MAX_DRAM_ENTRY
- IWL_MAX_DTS_TRIPS
- IWL_MAX_EXT_NVM_SECTION_SIZE
- IWL_MAX_GLOBAL_KEYS
- IWL_MAX_HW_QUEUES
- IWL_MAX_MCS_DISPLAY_SIZE
- IWL_MAX_NVM_SECTION_SIZE
- IWL_MAX_PHY_CALIBRATE_TBL_SIZE
- IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF
- IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF
- IWL_MAX_PLCP_ERR_THRESHOLD_DEF
- IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE
- IWL_MAX_PLCP_ERR_THRESHOLD_MAX
- IWL_MAX_PLCP_ERR_THRESHOLD_MIN
- IWL_MAX_RSSI_VAL
- IWL_MAX_RX_BA_SESSIONS
- IWL_MAX_RX_HW_QUEUES
- IWL_MAX_SCHED_SCAN_PLANS
- IWL_MAX_SEARCH
- IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE
- IWL_MAX_TID_COUNT
- IWL_MAX_TVQM_QUEUES
- IWL_MAX_UCODE_BEACON_INTERVAL
- IWL_MAX_WD_TIMEOUT
- IWL_MEASUREMENT_CONCURRENT
- IWL_MEASUREMENT_CSA_CONFLICT
- IWL_MEASUREMENT_OK
- IWL_MEASUREMENT_PERIODIC_FAILED
- IWL_MEASUREMENT_START
- IWL_MEASUREMENT_STOP
- IWL_MEASUREMENT_STOPPED
- IWL_MEASUREMENT_TGH_CONFLICT
- IWL_MEASUREMENT_TIMEOUT
- IWL_MEASURE_BASIC
- IWL_MEASURE_CHANNEL_LOAD
- IWL_MEASURE_FRAME
- IWL_MEASURE_HISTOGRAM_NOISE
- IWL_MEASURE_HISTOGRAM_RPI
- IWL_MEASURE_IDLE
- IWL_MGMT_DFAULT_RETRY_LIMIT
- IWL_MGMT_QUEUE_SIZE
- IWL_MGMT_TID
- IWL_MIC_KEY_SIZE
- IWL_MIMO2_SWITCH_ANTENNA1
- IWL_MIMO2_SWITCH_ANTENNA2
- IWL_MIMO2_SWITCH_GI
- IWL_MIMO2_SWITCH_MIMO3_ABC
- IWL_MIMO2_SWITCH_SISO_A
- IWL_MIMO2_SWITCH_SISO_B
- IWL_MIMO2_SWITCH_SISO_C
- IWL_MIMO3_SWITCH_ANTENNA1
- IWL_MIMO3_SWITCH_ANTENNA2
- IWL_MIMO3_SWITCH_GI
- IWL_MIMO3_SWITCH_MIMO2_AB
- IWL_MIMO3_SWITCH_MIMO2_AC
- IWL_MIMO3_SWITCH_MIMO2_BC
- IWL_MIMO3_SWITCH_SISO_A
- IWL_MIMO3_SWITCH_SISO_B
- IWL_MIMO3_SWITCH_SISO_C
- IWL_MINIMAL_POWER_THRESHOLD
- IWL_MIN_NUM_QUEUES
- IWL_MIN_RELOAD_DURATION
- IWL_MIN_RSSI_VAL
- IWL_MIN_SLOT_TIME
- IWL_MISSED_BEACON_THRESHOLD_DEF
- IWL_MISSED_BEACON_THRESHOLD_MAX
- IWL_MISSED_BEACON_THRESHOLD_MIN
- IWL_MISSED_RATE_MAX
- IWL_MULTI_QUEUE_SYNC_SENDER_MSK
- IWL_MULTI_QUEUE_SYNC_SENDER_POS
- IWL_MVM_ADWELL_ENABLE
- IWL_MVM_ADWELL_MAX_BUDGET
- IWL_MVM_AMPDU_CONSEC_DROPS_DELBA
- IWL_MVM_BA_RESP_TX_AGG
- IWL_MVM_BA_RESP_TX_AGG_FAIL
- IWL_MVM_BA_RESP_TX_BAR
- IWL_MVM_BA_RESP_TX_BT_KILL
- IWL_MVM_BA_RESP_TX_DSP_TIMEOUT
- IWL_MVM_BA_RESP_TX_UNDERRUN
- IWL_MVM_BT_COEX_ANTENNA_COUPLING_THRS
- IWL_MVM_BT_COEX_DIS_RED_TXP_THRESH
- IWL_MVM_BT_COEX_EN_RED_TXP_THRESH
- IWL_MVM_BT_COEX_MPLUT
- IWL_MVM_BT_COEX_MPLUT_REG0
- IWL_MVM_BT_COEX_MPLUT_REG1
- IWL_MVM_BT_COEX_RRC
- IWL_MVM_BT_COEX_SYNC2SCO
- IWL_MVM_BT_COEX_TTC
- IWL_MVM_CHANNEL_SWITCH_MARGIN
- IWL_MVM_CHANNEL_SWITCH_TIME_CLIENT
- IWL_MVM_CHANNEL_SWITCH_TIME_GO
- IWL_MVM_COMMON_OPS
- IWL_MVM_CS_UNBLOCK_TX_TIMEOUT
- IWL_MVM_D3_DEBUG
- IWL_MVM_DEBUG_SET_TEMPERATURE_DISABLE
- IWL_MVM_DEBUG_SET_TEMPERATURE_MAX
- IWL_MVM_DEBUG_SET_TEMPERATURE_MIN
- IWL_MVM_DEFAULT_PS_RX_DATA_TIMEOUT
- IWL_MVM_DEFAULT_PS_TX_DATA_TIMEOUT
- IWL_MVM_DQA_AP_PROBE_RESP_QUEUE
- IWL_MVM_DQA_AUX_QUEUE
- IWL_MVM_DQA_BSS_CLIENT_QUEUE
- IWL_MVM_DQA_CMD_QUEUE
- IWL_MVM_DQA_GCAST_QUEUE
- IWL_MVM_DQA_INJECT_MONITOR_QUEUE
- IWL_MVM_DQA_MAX_DATA_QUEUE
- IWL_MVM_DQA_MAX_MGMT_QUEUE
- IWL_MVM_DQA_MIN_DATA_QUEUE
- IWL_MVM_DQA_MIN_MGMT_QUEUE
- IWL_MVM_DQA_P2P_DEVICE_QUEUE
- IWL_MVM_DQA_QUEUE_TIMEOUT
- IWL_MVM_ENABLE_EBS
- IWL_MVM_FTM_INITIATOR_ALGO
- IWL_MVM_FTM_INITIATOR_DYNACK
- IWL_MVM_FW_BCAST_FILTER_PASS_ALL
- IWL_MVM_FW_MCAST_FILTER_PASS_ALL
- IWL_MVM_HW_CSUM_DISABLE
- IWL_MVM_INIT_STATUS_LEDS_INIT_COMPLETE
- IWL_MVM_INIT_STATUS_THERMAL_INIT_COMPLETE
- IWL_MVM_INVALID_QUEUE
- IWL_MVM_INVALID_STA
- IWL_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED
- IWL_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL
- IWL_MVM_LMAC_SCAN_FLAG_FRAGMENTED
- IWL_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE
- IWL_MVM_LMAC_SCAN_FLAG_MATCH
- IWL_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS
- IWL_MVM_LMAC_SCAN_FLAG_PASSIVE
- IWL_MVM_LMAC_SCAN_FLAG_PASS_ALL
- IWL_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION
- IWL_MVM_LOWLAT_QUOTA_MIN_PERCENT
- IWL_MVM_MAX_ADDRESSES
- IWL_MVM_MAX_LMAC_SCANS
- IWL_MVM_MAX_QUOTA
- IWL_MVM_MAX_UMAC_SCANS
- IWL_MVM_MISSED_BEACONS_THRESHOLD
- IWL_MVM_MISSED_BEACONS_THRESHOLD_LONG
- IWL_MVM_NON_TRANSMITTING_AP
- IWL_MVM_NUM_CIPHERS
- IWL_MVM_NUM_LAST_FRAMES_UCODE_RATES
- IWL_MVM_OFFCHANNEL_QUEUE
- IWL_MVM_P2P_LOWLATENCY_PS_ENABLE
- IWL_MVM_PARSE_NVM
- IWL_MVM_PM_EVENT_ASLEEP
- IWL_MVM_PM_EVENT_AWAKE
- IWL_MVM_PM_EVENT_PS_POLL
- IWL_MVM_PM_EVENT_UAPSD
- IWL_MVM_PS_HEAVY_RX_THLD_PACKETS
- IWL_MVM_PS_HEAVY_RX_THLD_PERCENT
- IWL_MVM_PS_HEAVY_TX_THLD_PACKETS
- IWL_MVM_PS_HEAVY_TX_THLD_PERCENT
- IWL_MVM_PS_SNOOZE_HEAVY_RX_THLD_PACKETS
- IWL_MVM_PS_SNOOZE_HEAVY_TX_THLD_PACKETS
- IWL_MVM_PS_SNOOZE_INTERVAL
- IWL_MVM_PS_SNOOZE_WINDOW
- IWL_MVM_QUEUE_FREE
- IWL_MVM_QUEUE_READY
- IWL_MVM_QUEUE_RESERVED
- IWL_MVM_QUEUE_SHARED
- IWL_MVM_QUOTA_THRESHOLD
- IWL_MVM_RELEASE_FROM_RSS_SYNC
- IWL_MVM_RELEASE_SEND_RSS_SYNC
- IWL_MVM_ROC_TE_TYPE_MGMT_TX
- IWL_MVM_ROC_TE_TYPE_NORMAL
- IWL_MVM_RS_80_20_FAR_RANGE_TWEAK
- IWL_MVM_RS_AGG_DISABLE_START
- IWL_MVM_RS_AGG_START_THRESHOLD
- IWL_MVM_RS_AGG_TIME_LIMIT
- IWL_MVM_RS_HT_VHT_RETRIES_PER_RATE
- IWL_MVM_RS_HT_VHT_RETRIES_PER_RATE_TW
- IWL_MVM_RS_IDLE_TIMEOUT
- IWL_MVM_RS_INITIAL_LEGACY_NUM_RATES
- IWL_MVM_RS_INITIAL_LEGACY_RETRIES
- IWL_MVM_RS_INITIAL_MIMO_NUM_RATES
- IWL_MVM_RS_INITIAL_SISO_NUM_RATES
- IWL_MVM_RS_LEGACY_FAILURE_LIMIT
- IWL_MVM_RS_LEGACY_SUCCESS_LIMIT
- IWL_MVM_RS_LEGACY_TABLE_COUNT
- IWL_MVM_RS_MISSED_RATE_MAX
- IWL_MVM_RS_NON_LEGACY_FAILURE_LIMIT
- IWL_MVM_RS_NON_LEGACY_SUCCESS_LIMIT
- IWL_MVM_RS_NON_LEGACY_TABLE_COUNT
- IWL_MVM_RS_NUM_TRY_BEFORE_ANT_TOGGLE
- IWL_MVM_RS_RATE_MIN_FAILURE_TH
- IWL_MVM_RS_RATE_MIN_SUCCESS_TH
- IWL_MVM_RS_RSSI_BASED_INIT_RATE
- IWL_MVM_RS_SECONDARY_LEGACY_NUM_RATES
- IWL_MVM_RS_SECONDARY_LEGACY_RETRIES
- IWL_MVM_RS_SECONDARY_SISO_NUM_RATES
- IWL_MVM_RS_SECONDARY_SISO_RETRIES
- IWL_MVM_RS_SR_FORCE_DECREASE
- IWL_MVM_RS_SR_NO_DECREASE
- IWL_MVM_RS_STAY_IN_COLUMN_TIMEOUT
- IWL_MVM_RS_TPC_SR_FORCE_INCREASE
- IWL_MVM_RS_TPC_SR_NO_INCREASE
- IWL_MVM_RS_TPC_TX_POWER_STEP
- IWL_MVM_RXQ_EMPTY
- IWL_MVM_RXQ_NOTIF_DEL_BA
- IWL_MVM_RXQ_NSSN_SYNC
- IWL_MVM_SCAN_MASK
- IWL_MVM_SCAN_NETDETECT
- IWL_MVM_SCAN_NETDETECT_MASK
- IWL_MVM_SCAN_REGULAR
- IWL_MVM_SCAN_REGULAR_MASK
- IWL_MVM_SCAN_SCHED
- IWL_MVM_SCAN_SCHED_MASK
- IWL_MVM_SCAN_STOPPING_MASK
- IWL_MVM_SCAN_STOPPING_NETDETECT
- IWL_MVM_SCAN_STOPPING_REGULAR
- IWL_MVM_SCAN_STOPPING_SCHED
- IWL_MVM_SCAN_STOPPING_SHIFT
- IWL_MVM_SHORT_PS_RX_DATA_TIMEOUT
- IWL_MVM_SHORT_PS_TX_DATA_TIMEOUT
- IWL_MVM_SMPS_REQ_BT_COEX
- IWL_MVM_SMPS_REQ_PROT
- IWL_MVM_SMPS_REQ_TT
- IWL_MVM_STATION_COUNT
- IWL_MVM_STATUS_FIRMWARE_RUNNING
- IWL_MVM_STATUS_HW_CTKILL
- IWL_MVM_STATUS_HW_RESTART_REQUESTED
- IWL_MVM_STATUS_HW_RFKILL
- IWL_MVM_STATUS_IN_HW_RESTART
- IWL_MVM_STATUS_NEED_FLUSH_P2P
- IWL_MVM_STATUS_ROC_AUX_RUNNING
- IWL_MVM_STATUS_ROC_RUNNING
- IWL_MVM_SW_TX_CSUM_OFFLOAD
- IWL_MVM_TCM_LOAD_HIGH_THRESH
- IWL_MVM_TCM_LOAD_MEDIUM_THRESH
- IWL_MVM_TCM_LOWLAT_ENABLE_THRESH
- IWL_MVM_TDLS_FW_TID
- IWL_MVM_TDLS_STA_COUNT
- IWL_MVM_TDLS_SW_ACTIVE
- IWL_MVM_TDLS_SW_IDLE
- IWL_MVM_TDLS_SW_REQ_RCVD
- IWL_MVM_TDLS_SW_REQ_SENT
- IWL_MVM_TDLS_SW_RESP_RCVD
- IWL_MVM_TEMP_NOTIF_WAIT_TIMEOUT
- IWL_MVM_TE_SESSION_PROTECTION_MAX_TIME_MS
- IWL_MVM_TE_SESSION_PROTECTION_MIN_TIME_MS
- IWL_MVM_TM_ATTR_BEACON_FILTER_STATE
- IWL_MVM_TM_ATTR_CMD
- IWL_MVM_TM_ATTR_MAX
- IWL_MVM_TM_ATTR_NOA_DURATION
- IWL_MVM_TM_ATTR_UNSPEC
- IWL_MVM_TM_CMD_SET_BEACON_FILTER
- IWL_MVM_TM_CMD_SET_NOA
- IWL_MVM_TOF_IS_RESPONDER
- IWL_MVM_TOF_MAX_APS
- IWL_MVM_TOF_MAX_TWO_SIDED_APS
- IWL_MVM_TOF_MCSI_BUF_SIZE
- IWL_MVM_TOF_RESPONSE_ASAP
- IWL_MVM_TOF_RESPONSE_COMPLETE
- IWL_MVM_TOF_RESPONSE_TIMEOUT
- IWL_MVM_TRAFFIC_HIGH
- IWL_MVM_TRAFFIC_LOW
- IWL_MVM_TRAFFIC_MEDIUM
- IWL_MVM_TX_FIFO_BE
- IWL_MVM_TX_FIFO_BK
- IWL_MVM_TX_FIFO_CMD
- IWL_MVM_TX_FIFO_MCAST
- IWL_MVM_TX_FIFO_VI
- IWL_MVM_TX_FIFO_VO
- IWL_MVM_TX_RES_GET_RA
- IWL_MVM_TX_RES_GET_TID
- IWL_MVM_UAPSD_NOAGG_BSSIDS_NUM
- IWL_MVM_UAPSD_NOAGG_LIST_LEN
- IWL_MVM_UAPSD_NONAGG_PERIOD
- IWL_MVM_UAPSD_QUEUES
- IWL_MVM_UAPSD_RX_DATA_TIMEOUT
- IWL_MVM_UAPSD_TX_DATA_TIMEOUT
- IWL_MVM_USE_NSSN_SYNC
- IWL_MVM_USE_TWT
- IWL_MVM_WOWLAN_PS_RX_DATA_TIMEOUT
- IWL_MVM_WOWLAN_PS_SNOOZE_WINDOW
- IWL_MVM_WOWLAN_PS_TX_DATA_TIMEOUT
- IWL_NETWORK_TYPE_ANY
- IWL_NETWORK_TYPE_BSS
- IWL_NETWORK_TYPE_IBSS
- IWL_NOISE_MEAS_NOT_AVAILABLE
- IWL_NONE_LEGACY_FAILURE_LIMIT
- IWL_NONE_LEGACY_SUCCESS_LIMIT
- IWL_NONE_LEGACY_TABLE_COUNT
- IWL_NONQOS_SEQ_GET
- IWL_NONQOS_SEQ_SET
- IWL_NOT_IBSS_MANAGER
- IWL_NUMBER_TRY
- IWL_NUM_CHAIN_LIMITS
- IWL_NUM_CHANNELS
- IWL_NUM_CHANNELS_V1
- IWL_NUM_GEO_PROFILES
- IWL_NUM_IDLE_CHAINS_DUAL
- IWL_NUM_IDLE_CHAINS_SINGLE
- IWL_NUM_OF_COMPLETION_RINGS
- IWL_NUM_OF_TBS
- IWL_NUM_OF_TRANSFER_RINGS
- IWL_NUM_RSC
- IWL_NUM_RX_CHAINS_MULTIPLE
- IWL_NUM_RX_CHAINS_SINGLE
- IWL_NUM_RX_P1K_CACHE
- IWL_NUM_SCAN_RATES
- IWL_NUM_SUB_BANDS
- IWL_NVM
- IWL_NVM_DEFAULT_CHUNK_SIZE
- IWL_NVM_EXT
- IWL_NVM_NUM_CHANNELS
- IWL_NVM_NUM_CHANNELS_EXT
- IWL_NVM_NUM_CHANNELS_UHB
- IWL_NVM_READ
- IWL_NVM_SBANDS_FLAGS_LAR
- IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ
- IWL_NVM_SDP
- IWL_NVM_WRITE
- IWL_OPERATION_MODE_20MHZ
- IWL_OPERATION_MODE_AUTO
- IWL_OPERATION_MODE_HT_ONLY
- IWL_OPERATION_MODE_MIXED
- IWL_OP_MODE_GET_DVM
- IWL_OP_MODE_GET_MVM
- IWL_P1K_SIZE
- IWL_P2P_NOA_DESC_COUNT
- IWL_PAN_SCD_BE_MSK
- IWL_PAN_SCD_BK_MSK
- IWL_PAN_SCD_MGMT_MSK
- IWL_PAN_SCD_MULTICAST_MSK
- IWL_PAN_SCD_VI_MSK
- IWL_PAN_SCD_VO_MSK
- IWL_PASSIVE_DWELL_BASE
- IWL_PASSIVE_DWELL_TIME_24
- IWL_PASSIVE_DWELL_TIME_52
- IWL_PCIE_MAX_FRAGS
- IWL_PCI_DEVICE
- IWL_PER_CHAIN_OFFSET_GET_CURRENT_TABLE
- IWL_PER_CHAIN_OFFSET_SET_TABLES
- IWL_PHY_CALIBRATE_BASE_BAND_CMD
- IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD
- IWL_PHY_CALIBRATE_DC_CMD
- IWL_PHY_CALIBRATE_LO_CMD
- IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD
- IWL_PHY_CALIBRATE_TX_IQ_CMD
- IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD
- IWL_PHY_DB_CALIB_CHG_PAPD
- IWL_PHY_DB_CALIB_CHG_TXP
- IWL_PHY_DB_CALIB_NCH
- IWL_PHY_DB_CFG
- IWL_PHY_DB_MAX
- IWL_PHY_DB_UNUSED
- IWL_PLAT_PM_MODE_D3
- IWL_PLAT_PM_MODE_DISABLED
- IWL_PLCP_QUIET_THRESH
- IWL_PM_NO_SLEEP
- IWL_PM_NUM_OF_MODES
- IWL_PM_OPS
- IWL_PM_SLP_FULL_MAC_CARD_STATE
- IWL_PM_SLP_FULL_MAC_UNASSOCIATE
- IWL_PM_SLP_MAC
- IWL_PM_SLP_PHY
- IWL_PM_SLP_REPENT
- IWL_PM_WAKEUP_BY_DRIVER
- IWL_PM_WAKEUP_BY_RFKILL
- IWL_PM_WAKEUP_BY_TIMER
- IWL_POLL_INTERVAL
- IWL_POWER_ADVANCE_PM_ENA_MSK
- IWL_POWER_BEACON_FILTERING
- IWL_POWER_BT_SCO_ENA
- IWL_POWER_CT_KILL_SET
- IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
- IWL_POWER_FAST_PD
- IWL_POWER_INDEX_1
- IWL_POWER_INDEX_2
- IWL_POWER_INDEX_3
- IWL_POWER_INDEX_4
- IWL_POWER_INDEX_5
- IWL_POWER_NUM
- IWL_POWER_PCI_PM_MSK
- IWL_POWER_POWER_MANAGEMENT_ENA_MSK
- IWL_POWER_POWER_SAVE_ENA_MSK
- IWL_POWER_SCHEME_BPS
- IWL_POWER_SCHEME_CAM
- IWL_POWER_SCHEME_LP
- IWL_POWER_SHADOW_REG_ENA
- IWL_POWER_SLEEP_OVER_DTIM_MSK
- IWL_POWER_VEC_SIZE
- IWL_PROBE_RESP_DATA_NO_CSA
- IWL_PROBE_STATUS_FAIL_BT
- IWL_PROBE_STATUS_FAIL_TTL
- IWL_PROBE_STATUS_OK
- IWL_PROBE_STATUS_TX_FAILED
- IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_MAX
- IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_V1
- IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_V2
- IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_V3L
- IWL_PROTO_OFFLOAD_NUM_IPV6_ADDRS_V3S
- IWL_PROTO_OFFLOAD_NUM_NS_CONFIG_V3L
- IWL_PROTO_OFFLOAD_NUM_NS_CONFIG_V3S
- IWL_PRPH_MTR_FORMAT_16B
- IWL_PRPH_MTR_FORMAT_256B
- IWL_PRPH_MTR_FORMAT_32B
- IWL_PRPH_MTR_FORMAT_64B
- IWL_PRPH_SCRATCH_EARLY_DEBUG_EN
- IWL_PRPH_SCRATCH_EDBG_DEST_DRAM
- IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL
- IWL_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER
- IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF
- IWL_PRPH_SCRATCH_MTR_FORMAT
- IWL_PRPH_SCRATCH_MTR_MODE
- IWL_PRPH_SCRATCH_RB_SIZE_4K
- IWL_PWR_CCK_ENTRIES
- IWL_PWR_NUM_HT_OFDM_ENTRIES
- IWL_QNJ_B_JF_B_FW_PRE
- IWL_QNJ_B_JF_B_MODULE_FIRMWARE
- IWL_QUOTA_LOW_LATENCY_NONE
- IWL_QUOTA_LOW_LATENCY_RX
- IWL_QUOTA_LOW_LATENCY_TX
- IWL_QUOTA_LOW_LATENCY_TX_RX
- IWL_QUZ_A_HR_B_FW_PRE
- IWL_QUZ_A_HR_B_MODULE_FIRMWARE
- IWL_QUZ_A_JF_B_FW_PRE
- IWL_QUZ_A_JF_B_MODULE_FIRMWARE
- IWL_QU_B_JF_B_FW_PRE
- IWL_QU_B_JF_B_MODULE_FIRMWARE
- IWL_QU_C_HR_B_FW_PRE
- IWL_QU_C_HR_B_MODULE_FIRMWARE
- IWL_QU_C_JF_B_FW_PRE
- IWL_RADIO_RESET_DWELL_TIME
- IWL_RATES_MASK
- IWL_RATE_11M_IEEE
- IWL_RATE_11M_INDEX
- IWL_RATE_11M_INDEX_TABLE
- IWL_RATE_11M_MASK
- IWL_RATE_11M_PLCP
- IWL_RATE_12M_IEEE
- IWL_RATE_12M_INDEX
- IWL_RATE_12M_INDEX_TABLE
- IWL_RATE_12M_MASK
- IWL_RATE_12M_PLCP
- IWL_RATE_18M_IEEE
- IWL_RATE_18M_INDEX
- IWL_RATE_18M_INDEX_TABLE
- IWL_RATE_18M_MASK
- IWL_RATE_18M_PLCP
- IWL_RATE_1M_IEEE
- IWL_RATE_1M_INDEX
- IWL_RATE_1M_INDEX_TABLE
- IWL_RATE_1M_MASK
- IWL_RATE_1M_PLCP
- IWL_RATE_24M_IEEE
- IWL_RATE_24M_INDEX
- IWL_RATE_24M_INDEX_TABLE
- IWL_RATE_24M_MASK
- IWL_RATE_24M_PLCP
- IWL_RATE_2M_IEEE
- IWL_RATE_2M_INDEX
- IWL_RATE_2M_INDEX_TABLE
- IWL_RATE_2M_MASK
- IWL_RATE_2M_PLCP
- IWL_RATE_36M_IEEE
- IWL_RATE_36M_INDEX
- IWL_RATE_36M_INDEX_TABLE
- IWL_RATE_36M_MASK
- IWL_RATE_36M_PLCP
- IWL_RATE_48M_IEEE
- IWL_RATE_48M_INDEX
- IWL_RATE_48M_INDEX_TABLE
- IWL_RATE_48M_MASK
- IWL_RATE_48M_PLCP
- IWL_RATE_54M_IEEE
- IWL_RATE_54M_INDEX
- IWL_RATE_54M_INDEX_TABLE
- IWL_RATE_54M_MASK
- IWL_RATE_54M_PLCP
- IWL_RATE_5M_IEEE
- IWL_RATE_5M_INDEX
- IWL_RATE_5M_INDEX_TABLE
- IWL_RATE_5M_MASK
- IWL_RATE_5M_PLCP
- IWL_RATE_60M_IEEE
- IWL_RATE_60M_INDEX
- IWL_RATE_60M_MASK
- IWL_RATE_60M_PLCP
- IWL_RATE_6M_IEEE
- IWL_RATE_6M_INDEX
- IWL_RATE_6M_INDEX_TABLE
- IWL_RATE_6M_MASK
- IWL_RATE_6M_PLCP
- IWL_RATE_9M_IEEE
- IWL_RATE_9M_INDEX
- IWL_RATE_9M_INDEX_TABLE
- IWL_RATE_9M_MASK
- IWL_RATE_9M_PLCP
- IWL_RATE_BIT_MSK
- IWL_RATE_COUNT
- IWL_RATE_COUNT_LEGACY
- IWL_RATE_DECREASE_TH
- IWL_RATE_HIGH_TH
- IWL_RATE_HT_MIMO2_MCS_0_PLCP
- IWL_RATE_HT_MIMO2_MCS_1_PLCP
- IWL_RATE_HT_MIMO2_MCS_2_PLCP
- IWL_RATE_HT_MIMO2_MCS_3_PLCP
- IWL_RATE_HT_MIMO2_MCS_4_PLCP
- IWL_RATE_HT_MIMO2_MCS_5_PLCP
- IWL_RATE_HT_MIMO2_MCS_6_PLCP
- IWL_RATE_HT_MIMO2_MCS_7_PLCP
- IWL_RATE_HT_MIMO2_MCS_8_PLCP
- IWL_RATE_HT_MIMO2_MCS_9_PLCP
- IWL_RATE_HT_MIMO2_MCS_INV_PLCP
- IWL_RATE_HT_SISO_MCS_0_PLCP
- IWL_RATE_HT_SISO_MCS_1_PLCP
- IWL_RATE_HT_SISO_MCS_2_PLCP
- IWL_RATE_HT_SISO_MCS_3_PLCP
- IWL_RATE_HT_SISO_MCS_4_PLCP
- IWL_RATE_HT_SISO_MCS_5_PLCP
- IWL_RATE_HT_SISO_MCS_6_PLCP
- IWL_RATE_HT_SISO_MCS_7_PLCP
- IWL_RATE_HT_SISO_MCS_8_PLCP
- IWL_RATE_HT_SISO_MCS_9_PLCP
- IWL_RATE_HT_SISO_MCS_INV_PLCP
- IWL_RATE_INCREASE_TH
- IWL_RATE_INVALID
- IWL_RATE_INVM_INDEX
- IWL_RATE_INVM_INDEX_TABLE
- IWL_RATE_INVM_PLCP
- IWL_RATE_MAX_WINDOW
- IWL_RATE_MCS_0_INDEX
- IWL_RATE_MCS_10_INDEX
- IWL_RATE_MCS_11_INDEX
- IWL_RATE_MCS_1_INDEX
- IWL_RATE_MCS_2_INDEX
- IWL_RATE_MCS_3_INDEX
- IWL_RATE_MCS_4_INDEX
- IWL_RATE_MCS_5_INDEX
- IWL_RATE_MCS_6_INDEX
- IWL_RATE_MCS_7_INDEX
- IWL_RATE_MCS_8_INDEX
- IWL_RATE_MCS_9_INDEX
- IWL_RATE_MIMO2_12M_PLCP
- IWL_RATE_MIMO2_18M_PLCP
- IWL_RATE_MIMO2_24M_PLCP
- IWL_RATE_MIMO2_36M_PLCP
- IWL_RATE_MIMO2_48M_PLCP
- IWL_RATE_MIMO2_54M_PLCP
- IWL_RATE_MIMO2_60M_PLCP
- IWL_RATE_MIMO2_6M_PLCP
- IWL_RATE_MIMO2_INVM_PLCP
- IWL_RATE_MIMO3_12M_PLCP
- IWL_RATE_MIMO3_18M_PLCP
- IWL_RATE_MIMO3_24M_PLCP
- IWL_RATE_MIMO3_36M_PLCP
- IWL_RATE_MIMO3_48M_PLCP
- IWL_RATE_MIMO3_54M_PLCP
- IWL_RATE_MIMO3_60M_PLCP
- IWL_RATE_MIMO3_6M_PLCP
- IWL_RATE_MIMO3_INVM_PLCP
- IWL_RATE_MIN_FAILURE_TH
- IWL_RATE_MIN_SUCCESS_TH
- IWL_RATE_SCALE_FLUSH_INTVL
- IWL_RATE_SCALE_SWITCH
- IWL_RATE_SISO_12M_PLCP
- IWL_RATE_SISO_18M_PLCP
- IWL_RATE_SISO_24M_PLCP
- IWL_RATE_SISO_36M_PLCP
- IWL_RATE_SISO_48M_PLCP
- IWL_RATE_SISO_54M_PLCP
- IWL_RATE_SISO_60M_PLCP
- IWL_RATE_SISO_6M_PLCP
- IWL_RATE_SISO_INVM_PLCP
- IWL_RATE_VHT_MIMO2_MCS_0_PLCP
- IWL_RATE_VHT_MIMO2_MCS_1_PLCP
- IWL_RATE_VHT_MIMO2_MCS_2_PLCP
- IWL_RATE_VHT_MIMO2_MCS_3_PLCP
- IWL_RATE_VHT_MIMO2_MCS_4_PLCP
- IWL_RATE_VHT_MIMO2_MCS_5_PLCP
- IWL_RATE_VHT_MIMO2_MCS_6_PLCP
- IWL_RATE_VHT_MIMO2_MCS_7_PLCP
- IWL_RATE_VHT_MIMO2_MCS_8_PLCP
- IWL_RATE_VHT_MIMO2_MCS_9_PLCP
- IWL_RATE_VHT_MIMO2_MCS_INV_PLCP
- IWL_RATE_VHT_SISO_MCS_0_PLCP
- IWL_RATE_VHT_SISO_MCS_1_PLCP
- IWL_RATE_VHT_SISO_MCS_2_PLCP
- IWL_RATE_VHT_SISO_MCS_3_PLCP
- IWL_RATE_VHT_SISO_MCS_4_PLCP
- IWL_RATE_VHT_SISO_MCS_5_PLCP
- IWL_RATE_VHT_SISO_MCS_6_PLCP
- IWL_RATE_VHT_SISO_MCS_7_PLCP
- IWL_RATE_VHT_SISO_MCS_8_PLCP
- IWL_RATE_VHT_SISO_MCS_9_PLCP
- IWL_RATE_VHT_SISO_MCS_INV_PLCP
- IWL_REDUCED_PERFORMANCE_THRESHOLD_1
- IWL_REDUCED_PERFORMANCE_THRESHOLD_2
- IWL_RSSI_OFFSET
- IWL_RSS_ENABLE
- IWL_RSS_HASH_KEY_CNT
- IWL_RSS_HASH_TYPE_IPV4_PAYLOAD
- IWL_RSS_HASH_TYPE_IPV4_TCP
- IWL_RSS_HASH_TYPE_IPV4_UDP
- IWL_RSS_HASH_TYPE_IPV6_PAYLOAD
- IWL_RSS_HASH_TYPE_IPV6_TCP
- IWL_RSS_HASH_TYPE_IPV6_UDP
- IWL_RSS_INDIRECTION_TABLE_SIZE
- IWL_RS_GOOD_RATIO
- IWL_RS_LOW_RSSI_THRESHOLD
- IWL_RTS_DFAULT_RETRY_LIMIT
- IWL_RXF_UMAC_BIT
- IWL_RXON_CTX_BSS
- IWL_RXON_CTX_PAN
- IWL_RX_CD_FLAGS_FRAGMENTED
- IWL_RX_DESC_SIZE_V1
- IWL_RX_INFO_ENERGY_ANT_ABC_IDX
- IWL_RX_INFO_ENERGY_ANT_A_MSK
- IWL_RX_INFO_ENERGY_ANT_A_POS
- IWL_RX_INFO_ENERGY_ANT_B_MSK
- IWL_RX_INFO_ENERGY_ANT_B_POS
- IWL_RX_INFO_ENERGY_ANT_C_MSK
- IWL_RX_INFO_ENERGY_ANT_C_POS
- IWL_RX_INFO_PHY_CNT
- IWL_RX_L3L4_IP_HDR_CSUM_OK
- IWL_RX_L3L4_L3_PROTO_MASK
- IWL_RX_L3L4_L4_PROTO_MASK
- IWL_RX_L3L4_RSS_HASH_MASK
- IWL_RX_L3L4_TCP_ACK
- IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH
- IWL_RX_L3L4_TCP_UDP_CSUM_OK
- IWL_RX_L3_PROTO_POS
- IWL_RX_L3_TYPE_ARP
- IWL_RX_L3_TYPE_EAPOL
- IWL_RX_L3_TYPE_IPV4
- IWL_RX_L3_TYPE_IPV4_FRAG
- IWL_RX_L3_TYPE_IPV6
- IWL_RX_L3_TYPE_IPV6_FRAG
- IWL_RX_L3_TYPE_IPV6_IN_IPV4
- IWL_RX_L3_TYPE_NONE
- IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK
- IWL_RX_MPDU_AMSDU_LAST_SUBFRAME
- IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK
- IWL_RX_MPDU_HF_A1_HASH_MASK
- IWL_RX_MPDU_HF_FILTER_STATUS_MASK
- IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK
- IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT
- IWL_RX_MPDU_MFLG2_AMSDU
- IWL_RX_MPDU_MFLG2_HDR_LEN_MASK
- IWL_RX_MPDU_MFLG2_PAD
- IWL_RX_MPDU_PHY_AMPDU
- IWL_RX_MPDU_PHY_AMPDU_TOGGLE
- IWL_RX_MPDU_PHY_MAC_INDEX_MASK
- IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY
- IWL_RX_MPDU_PHY_PHY_INDEX_MASK
- IWL_RX_MPDU_PHY_SHORT_PREAMBLE
- IWL_RX_MPDU_PHY_TSF_OVERLOAD
- IWL_RX_MPDU_REORDER_BAID_MASK
- IWL_RX_MPDU_REORDER_BAID_SHIFT
- IWL_RX_MPDU_REORDER_BA_OLD_SN
- IWL_RX_MPDU_REORDER_NSSN_MASK
- IWL_RX_MPDU_REORDER_SN_MASK
- IWL_RX_MPDU_REORDER_SN_SHIFT
- IWL_RX_MPDU_RES_STATUS_TTAK_OK
- IWL_RX_MPDU_SIF_FILTER_STATUS_MASK
- IWL_RX_MPDU_SIF_RRF_ABORT
- IWL_RX_MPDU_SIF_STA_ID_MASK
- IWL_RX_MPDU_STATUS_CRC_OK
- IWL_RX_MPDU_STATUS_DECRYPTED
- IWL_RX_MPDU_STATUS_EXT_IV_MATCH
- IWL_RX_MPDU_STATUS_ICV_OK
- IWL_RX_MPDU_STATUS_KEY_ID_MATCH
- IWL_RX_MPDU_STATUS_KEY_PARAM_OK
- IWL_RX_MPDU_STATUS_KEY_VALID
- IWL_RX_MPDU_STATUS_MIC_OK
- IWL_RX_MPDU_STATUS_OVERRUN_OK
- IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME
- IWL_RX_MPDU_STATUS_SEC_CCM
- IWL_RX_MPDU_STATUS_SEC_EXT_ENC
- IWL_RX_MPDU_STATUS_SEC_GCM
- IWL_RX_MPDU_STATUS_SEC_MASK
- IWL_RX_MPDU_STATUS_SEC_NONE
- IWL_RX_MPDU_STATUS_SEC_TKIP
- IWL_RX_MPDU_STATUS_SEC_UNKNOWN
- IWL_RX_MPDU_STATUS_SEC_WEP
- IWL_RX_MPDU_STATUS_SRC_STA_FOUND
- IWL_RX_MPDU_STATUS_WEP_MATCH
- IWL_RX_PHY_DATA0_HE_BEAM_CHNG
- IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK
- IWL_RX_PHY_DATA0_HE_DELIM_EOF
- IWL_RX_PHY_DATA0_HE_DOPPLER
- IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM
- IWL_RX_PHY_DATA0_HE_PE_DISAMBIG
- IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK
- IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK
- IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK
- IWL_RX_PHY_DATA0_HE_UPLINK
- IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK
- IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK
- IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION
- IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK
- IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80
- IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK
- IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE
- IWL_RX_PHY_DATA1_INFO_TYPE_MASK
- IWL_RX_PHY_DATA1_LSIG_LEN_MASK
- IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0
- IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2
- IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0
- IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2
- IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1
- IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2
- IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3
- IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4
- IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1
- IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3
- IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1
- IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3
- IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK
- IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU
- IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK
- IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU
- IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK
- IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM
- IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK
- IWL_RX_PHY_INFO_TYPE_CCK
- IWL_RX_PHY_INFO_TYPE_HE_MU
- IWL_RX_PHY_INFO_TYPE_HE_MU_EXT
- IWL_RX_PHY_INFO_TYPE_HE_SU
- IWL_RX_PHY_INFO_TYPE_HE_TB
- IWL_RX_PHY_INFO_TYPE_HE_TB_EXT
- IWL_RX_PHY_INFO_TYPE_HT
- IWL_RX_PHY_INFO_TYPE_NONE
- IWL_RX_PHY_INFO_TYPE_OFDM_LGCY
- IWL_RX_PHY_INFO_TYPE_VHT_MU
- IWL_RX_PHY_INFO_TYPE_VHT_SU
- IWL_RX_REORDER_DATA_INVALID_BAID
- IWL_SCAN_ADWELL_DEFAULT_HB_N_APS
- IWL_SCAN_ADWELL_DEFAULT_LB_N_APS
- IWL_SCAN_ADWELL_DEFAULT_N_APS_SOCIAL
- IWL_SCAN_ADWELL_MAX_BUDGET_DIRECTED_SCAN
- IWL_SCAN_ADWELL_MAX_BUDGET_FULL_SCAN
- IWL_SCAN_BAND_2_4
- IWL_SCAN_BAND_5_2
- IWL_SCAN_CHANNEL_FLAG_CACHE_ADD
- IWL_SCAN_CHANNEL_FLAG_EBS
- IWL_SCAN_CHANNEL_FLAG_EBS_ACCURATE
- IWL_SCAN_CHANNEL_FLAG_EBS_FRAG
- IWL_SCAN_CHECK_WATCHDOG
- IWL_SCAN_DWELL_ACTIVE
- IWL_SCAN_DWELL_EXTENDED
- IWL_SCAN_DWELL_FRAGMENTED
- IWL_SCAN_DWELL_PASSIVE
- IWL_SCAN_EBS_CHAN_NOT_FOUND
- IWL_SCAN_EBS_FAILED
- IWL_SCAN_EBS_INACTIVE
- IWL_SCAN_EBS_SUCCESS
- IWL_SCAN_FLAGS_ACTION_FRAME_TX
- IWL_SCAN_LAST_2_4_CHN
- IWL_SCAN_MAX_BLACKLIST_LEN
- IWL_SCAN_MAX_PROFILES
- IWL_SCAN_NORMAL
- IWL_SCAN_NUM_OF_FRAGS
- IWL_SCAN_OFFLOAD_ABORTED
- IWL_SCAN_OFFLOAD_COMPLETED
- IWL_SCAN_OFFLOAD_SELECT_2_4
- IWL_SCAN_OFFLOAD_SELECT_5_2
- IWL_SCAN_OFFLOAD_SELECT_ANY
- IWL_SCAN_PRIORITY_EXT_0_LOWEST
- IWL_SCAN_PRIORITY_EXT_1
- IWL_SCAN_PRIORITY_EXT_2
- IWL_SCAN_PRIORITY_EXT_3
- IWL_SCAN_PRIORITY_EXT_4
- IWL_SCAN_PRIORITY_EXT_5
- IWL_SCAN_PRIORITY_EXT_6
- IWL_SCAN_PRIORITY_EXT_7_HIGHEST
- IWL_SCAN_PRIORITY_HIGH
- IWL_SCAN_PRIORITY_LOW
- IWL_SCAN_PRIORITY_MEDIUM
- IWL_SCAN_PROBE_MASK
- IWL_SCAN_RADIO_RESET
- IWL_SCAN_REQ_UMAC_SIZE_V1
- IWL_SCAN_REQ_UMAC_SIZE_V6
- IWL_SCAN_REQ_UMAC_SIZE_V7
- IWL_SCAN_REQ_UMAC_SIZE_V8
- IWL_SCAN_SHORT_BLACKLIST_LEN
- IWL_SCAN_TYPE_FAST_BALANCE
- IWL_SCAN_TYPE_FRAGMENTED
- IWL_SCAN_TYPE_MILD
- IWL_SCAN_TYPE_NOT_SET
- IWL_SCAN_TYPE_UNASSOC
- IWL_SCAN_TYPE_WILD
- IWL_SCD_BE_MSK
- IWL_SCD_BK_MSK
- IWL_SCD_MGMT_MSK
- IWL_SCD_VI_MSK
- IWL_SCD_VO_MSK
- IWL_SCHED_SCAN_WATCHDOG
- IWL_SENSITIVITY_CALIB_DISABLED
- IWL_SHARED_IRQ_FIRST_RSS
- IWL_SHARED_IRQ_NON_RX
- IWL_SISO_SWITCH_ANTENNA1
- IWL_SISO_SWITCH_ANTENNA2
- IWL_SISO_SWITCH_GI
- IWL_SISO_SWITCH_MIMO2_AB
- IWL_SISO_SWITCH_MIMO2_AC
- IWL_SISO_SWITCH_MIMO2_BC
- IWL_SISO_SWITCH_MIMO3_ABC
- IWL_SPARSE_EBS_SCAN_RATIO
- IWL_STATISTICS_FLG_CLEAR
- IWL_STATISTICS_FLG_DISABLE_NOTIF
- IWL_STATISTICS_REPLY_FLG_CLEAR
- IWL_STATS_CONF_CLEAR_STATS
- IWL_STATS_CONF_DISABLE_NOTIF
- IWL_STA_AUX_ACTIVITY
- IWL_STA_BCAST
- IWL_STA_DRIVER_ACTIVE
- IWL_STA_GENERAL_PURPOSE
- IWL_STA_ID
- IWL_STA_LINK
- IWL_STA_LOCAL
- IWL_STA_MULTICAST
- IWL_STA_TDLS_LINK
- IWL_STA_UCODE_ACTIVE
- IWL_STA_UCODE_INPROGRESS
- IWL_SUPPORTED_RATES_IE_LEN
- IWL_TDLS_CH_SW_FRAME_MAX_SIZE
- IWL_TEMP_CONVERT
- IWL_TFH_NUM_TBS
- IWL_TID_NON_QOS
- IWL_TI_0
- IWL_TI_1
- IWL_TI_2
- IWL_TI_CT_KILL
- IWL_TI_STATE_MAX
- IWL_TLC_HT_BW_160
- IWL_TLC_HT_BW_NONE_160
- IWL_TLC_HT_BW_RATES
- IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK
- IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK
- IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK
- IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK
- IWL_TLC_MNG_CFG_FLAGS_STBC_MSK
- IWL_TLC_MNG_CHAIN_A_MSK
- IWL_TLC_MNG_CHAIN_B_MSK
- IWL_TLC_MNG_CH_WIDTH_160MHZ
- IWL_TLC_MNG_CH_WIDTH_20MHZ
- IWL_TLC_MNG_CH_WIDTH_40MHZ
- IWL_TLC_MNG_CH_WIDTH_80MHZ
- IWL_TLC_MNG_CH_WIDTH_LAST
- IWL_TLC_MNG_HT_RATE_MAX
- IWL_TLC_MNG_HT_RATE_MCS0
- IWL_TLC_MNG_HT_RATE_MCS1
- IWL_TLC_MNG_HT_RATE_MCS10
- IWL_TLC_MNG_HT_RATE_MCS11
- IWL_TLC_MNG_HT_RATE_MCS2
- IWL_TLC_MNG_HT_RATE_MCS3
- IWL_TLC_MNG_HT_RATE_MCS4
- IWL_TLC_MNG_HT_RATE_MCS5
- IWL_TLC_MNG_HT_RATE_MCS6
- IWL_TLC_MNG_HT_RATE_MCS7
- IWL_TLC_MNG_HT_RATE_MCS8
- IWL_TLC_MNG_HT_RATE_MCS9
- IWL_TLC_MNG_MODE_CCK
- IWL_TLC_MNG_MODE_HE
- IWL_TLC_MNG_MODE_HT
- IWL_TLC_MNG_MODE_INVALID
- IWL_TLC_MNG_MODE_NON_HT
- IWL_TLC_MNG_MODE_NUM
- IWL_TLC_MNG_MODE_OFDM_NON_HT
- IWL_TLC_MNG_MODE_VHT
- IWL_TLC_MNG_NSS
- IWL_TLC_NOTIF_FLAG_AMSDU
- IWL_TLC_NOTIF_FLAG_RATE
- IWL_TLC_NSS_1
- IWL_TLC_NSS_2
- IWL_TLC_NSS_MAX
- IWL_TLV_UCODE_MAGIC
- IWL_TOF_ALGO_TYPE_FFT
- IWL_TOF_ALGO_TYPE_INVALID
- IWL_TOF_ALGO_TYPE_LINEAR_REG
- IWL_TOF_ALGO_TYPE_MAX_LIKE
- IWL_TOF_BW_160
- IWL_TOF_BW_20_HT
- IWL_TOF_BW_20_LEGACY
- IWL_TOF_BW_40
- IWL_TOF_BW_80
- IWL_TOF_ENTRY_11MC_PROTOCOL_FAILURE
- IWL_TOF_ENTRY_BAD_REQUEST_ARGS
- IWL_TOF_ENTRY_GENERAL_FAILURE
- IWL_TOF_ENTRY_LOCATION_INVALID_T1_T4_TIME_STAMP
- IWL_TOF_ENTRY_NOT_SCHEDULED
- IWL_TOF_ENTRY_NO_RESPONSE
- IWL_TOF_ENTRY_RANGE_NOT_SUPPORTED
- IWL_TOF_ENTRY_REQUEST_ABORT_UNKNOWN_REASON
- IWL_TOF_ENTRY_REQUEST_CANNOT_SCHED
- IWL_TOF_ENTRY_REQUEST_REJECTED
- IWL_TOF_ENTRY_RESPONDER_CANNOT_COLABORATE
- IWL_TOF_ENTRY_RESPONDER_OVERRIDE_PARAMS
- IWL_TOF_ENTRY_SUCCESS
- IWL_TOF_ENTRY_TARGET_DIFF_CH_CANNOT_CHANGE
- IWL_TOF_ENTRY_TIMING_MEASURE_TIMEOUT
- IWL_TOF_ENTRY_WIFI_NOT_ENABLED
- IWL_TOF_INITIATOR_FLAGS_COMMON_CALIB
- IWL_TOF_INITIATOR_FLAGS_FAST_ALGO_DISABLED
- IWL_TOF_INITIATOR_FLAGS_MACADDR_RANDOM
- IWL_TOF_INITIATOR_FLAGS_NON_ASAP_SUPPORT
- IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_A
- IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_B
- IWL_TOF_INITIATOR_FLAGS_RX_CHAIN_SEL_C
- IWL_TOF_INITIATOR_FLAGS_SPECIFIC_CALIB
- IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_A
- IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_B
- IWL_TOF_INITIATOR_FLAGS_TX_CHAIN_SEL_C
- IWL_TOF_LOC_CIVIC
- IWL_TOF_LOC_LCI
- IWL_TOF_MCSI_DISABLED
- IWL_TOF_MCSI_ENABLED
- IWL_TOF_RANGE_REQUEST_STATUS_BUSY
- IWL_TOF_RANGE_REQUEST_STATUS_SUCCESS
- IWL_TOF_RESPONDER_CMD_VALID_ALGO_TYPE
- IWL_TOF_RESPONDER_CMD_VALID_BSSID
- IWL_TOF_RESPONDER_CMD_VALID_CHAN_INFO
- IWL_TOF_RESPONDER_CMD_VALID_COMMON_CALIB
- IWL_TOF_RESPONDER_CMD_VALID_FAST_ALGO_SUPPORT
- IWL_TOF_RESPONDER_CMD_VALID_MCSI_NOTIF_SUPPORT
- IWL_TOF_RESPONDER_CMD_VALID_NON_ASAP_SUPPORT
- IWL_TOF_RESPONDER_CMD_VALID_RETRY_ON_ALGO_FAIL
- IWL_TOF_RESPONDER_CMD_VALID_SPECIFIC_CALIB
- IWL_TOF_RESPONDER_CMD_VALID_STATISTICS_REPORT_SUPPORT
- IWL_TOF_RESPONDER_CMD_VALID_STA_ID
- IWL_TOF_RESPONDER_CMD_VALID_TOA_OFFSET
- IWL_TOF_RESPONDER_CMD_VALID_TX_ANT
- IWL_TOF_RESPONDER_FLAGS_ALGO_TYPE
- IWL_TOF_RESPONDER_FLAGS_COMMON_CALIB_MODE
- IWL_TOF_RESPONDER_FLAGS_FAST_ALGO_SUPPORT
- IWL_TOF_RESPONDER_FLAGS_FTM_TX_ANT
- IWL_TOF_RESPONDER_FLAGS_NON_ASAP_SUPPORT
- IWL_TOF_RESPONDER_FLAGS_REPORT_MCSI
- IWL_TOF_RESPONDER_FLAGS_REPORT_STATISTICS
- IWL_TOF_RESPONDER_FLAGS_RETRY_ON_ALGO_FAIL
- IWL_TOF_RESPONDER_FLAGS_SPECIFIC_CALIB_MODE
- IWL_TOF_RESPONDER_FLAGS_TOA_OFFSET_MODE
- IWL_TOF_RESPONSE_ABORTED
- IWL_TOF_RESPONSE_FAILED
- IWL_TOF_RESPONSE_SUCCESS
- IWL_TOF_RESPONSE_TIMEOUT
- IWL_TRANS_COMMON_OPS
- IWL_TRANS_FW_ALIVE
- IWL_TRANS_GET_PCIE_TRANS
- IWL_TRANS_NMI_TIMEOUT
- IWL_TRANS_NO_FW
- IWL_TRANS_PM_OPS
- IWL_TT_CT_KILL_MARGIN
- IWL_TT_INCREASE_MARGIN
- IWL_TX_CMD_OFFLD_IP_HDR_MASK
- IWL_TX_CMD_OFFLD_MH_MASK
- IWL_TX_CRC_SIZE
- IWL_TX_CSUM_NETIF_FLAGS
- IWL_TX_DELIMITER_SIZE
- IWL_TX_DMA_MASK
- IWL_TX_FIFO_AUX
- IWL_TX_FIFO_BE
- IWL_TX_FIFO_BE_IPAN
- IWL_TX_FIFO_BK
- IWL_TX_FIFO_BK_IPAN
- IWL_TX_FIFO_UNUSED
- IWL_TX_FIFO_VI
- IWL_TX_FIFO_VI_IPAN
- IWL_TX_FIFO_VO
- IWL_TX_FIFO_VO_IPAN
- IWL_TX_FLAGS_CMD_RATE
- IWL_TX_FLAGS_ENCRYPT_DIS
- IWL_TX_FLAGS_HIGH_PRI
- IWL_TX_POWER_CALIB_DISABLED
- IWL_TX_POWER_MODE_SET_ACK
- IWL_TX_POWER_MODE_SET_CHAINS
- IWL_TX_POWER_MODE_SET_DEVICE
- IWL_TX_POWER_MODE_SET_MAC
- IWL_TX_POWER_MODE_SET_SAR_TIMER
- IWL_TX_POWER_MODE_SET_SAR_TIMER_DEFAULT_TABLE
- IWL_UAPSD_MAX_SP
- IWL_UCODE_API
- IWL_UCODE_INIT
- IWL_UCODE_INI_TLV_GROUP
- IWL_UCODE_MAJOR
- IWL_UCODE_MAX_CS
- IWL_UCODE_MINOR
- IWL_UCODE_REGULAR
- IWL_UCODE_REGULAR_USNIFFER
- IWL_UCODE_SECTION_DATA
- IWL_UCODE_SECTION_INST
- IWL_UCODE_SERIAL
- IWL_UCODE_TLV_API_ADAPTIVE_DWELL
- IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2
- IWL_UCODE_TLV_API_ADWELL_HB_DEF_N_AP
- IWL_UCODE_TLV_API_BEACON_FILTER_V4
- IWL_UCODE_TLV_API_CHANGES_SET
- IWL_UCODE_TLV_API_DEPRECATE_TTAK
- IWL_UCODE_TLV_API_FRAGMENTED_SCAN
- IWL_UCODE_TLV_API_FRAG_EBS
- IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ
- IWL_UCODE_TLV_API_FTM_RTT_ACCURACY
- IWL_UCODE_TLV_API_LQ_SS_PARAMS
- IWL_UCODE_TLV_API_MBSSID_HE
- IWL_UCODE_TLV_API_NAN2_VER2
- IWL_UCODE_TLV_API_NEW_BEACON_TEMPLATE
- IWL_UCODE_TLV_API_NEW_RX_STATS
- IWL_UCODE_TLV_API_NEW_VERSION
- IWL_UCODE_TLV_API_OCE
- IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY
- IWL_UCODE_TLV_API_REDUCED_SCAN_CONFIG
- IWL_UCODE_TLV_API_REDUCE_TX_POWER
- IWL_UCODE_TLV_API_REGULATORY_NVM_INFO
- IWL_UCODE_TLV_API_SAR_TABLE_VER
- IWL_UCODE_TLV_API_SCAN_EXT_CHAN_VER
- IWL_UCODE_TLV_API_SCAN_OFFLOAD_CHANS
- IWL_UCODE_TLV_API_SCAN_TSF_REPORT
- IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF
- IWL_UCODE_TLV_API_STA_TYPE
- IWL_UCODE_TLV_API_TKIP_MIC_KEYS
- IWL_UCODE_TLV_API_WIFI_MCC_UPDATE
- IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL
- IWL_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE
- IWL_UCODE_TLV_BOOT
- IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION
- IWL_UCODE_TLV_CAPA_BEACON_STORING
- IWL_UCODE_TLV_CAPA_BEAMFORMER
- IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT
- IWL_UCODE_TLV_CAPA_BT_COEX_PLCR
- IWL_UCODE_TLV_CAPA_BT_COEX_RRC
- IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT
- IWL_UCODE_TLV_CAPA_CDB_SUPPORT
- IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD
- IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG
- IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2
- IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD
- IWL_UCODE_TLV_CAPA_CSI_REPORTING
- IWL_UCODE_TLV_CAPA_CSUM_SUPPORT
- IWL_UCODE_TLV_CAPA_CS_MODIFY
- IWL_UCODE_TLV_CAPA_CTDP_SUPPORT
- IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW
- IWL_UCODE_TLV_CAPA_D0I3_END_FIRST
- IWL_UCODE_TLV_CAPA_D0I3_SUPPORT
- IWL_UCODE_TLV_CAPA_D3_DEBUG
- IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP
- IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP
- IWL_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT
- IWL_UCODE_TLV_CAPA_DQA_SUPPORT
- IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT
- IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA
- IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE
- IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
- IWL_UCODE_TLV_CAPA_FTM_CALIBRATED
- IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT
- IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT
- IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC
- IWL_UCODE_TLV_CAPA_LAR_SUPPORT
- IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3
- IWL_UCODE_TLV_CAPA_LED_CMD_SUPPORT
- IWL_UCODE_TLV_CAPA_LQM_SUPPORT
- IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT
- IWL_UCODE_TLV_CAPA_MLME_OFFLOAD
- IWL_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT
- IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD
- IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT
- IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS
- IWL_UCODE_TLV_CAPA_SET_LTR_GEN2
- IWL_UCODE_TLV_CAPA_SET_PPAG
- IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS
- IWL_UCODE_TLV_CAPA_STA_PM_NOTIF
- IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH
- IWL_UCODE_TLV_CAPA_TDLS_SUPPORT
- IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT
- IWL_UCODE_TLV_CAPA_TLC_OFFLOAD
- IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT
- IWL_UCODE_TLV_CAPA_TX_POWER_ACK
- IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS
- IWL_UCODE_TLV_CAPA_UMAC_SCAN
- IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED
- IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT
- IWL_UCODE_TLV_CMD_VERSIONS
- IWL_UCODE_TLV_CSCHEME
- IWL_UCODE_TLV_DATA
- IWL_UCODE_TLV_DEBUG_BASE
- IWL_UCODE_TLV_DEBUG_MAX
- IWL_UCODE_TLV_DEF_CALIB
- IWL_UCODE_TLV_ENABLED_CAPABILITIES
- IWL_UCODE_TLV_ENHANCE_SENS_TBL
- IWL_UCODE_TLV_FLAGS
- IWL_UCODE_TLV_FLAGS_BCAST_FILTERING
- IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS
- IWL_UCODE_TLV_FLAGS_EBS_SUPPORT
- IWL_UCODE_TLV_FLAGS_MFP
- IWL_UCODE_TLV_FLAGS_NEWSCAN
- IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE
- IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL
- IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID
- IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD
- IWL_UCODE_TLV_FLAGS_PAN
- IWL_UCODE_TLV_FLAGS_SHORT_BL
- IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT
- IWL_UCODE_TLV_FW_DBG_CONF
- IWL_UCODE_TLV_FW_DBG_DEST
- IWL_UCODE_TLV_FW_DBG_DUMP_LST
- IWL_UCODE_TLV_FW_DBG_TRIGGER
- IWL_UCODE_TLV_FW_FSEQ_VERSION
- IWL_UCODE_TLV_FW_GSCAN_CAPA
- IWL_UCODE_TLV_FW_MEM_SEG
- IWL_UCODE_TLV_FW_RECOVERY_INFO
- IWL_UCODE_TLV_FW_VERSION
- IWL_UCODE_TLV_IML
- IWL_UCODE_TLV_INIT
- IWL_UCODE_TLV_INIT_DATA
- IWL_UCODE_TLV_INIT_ERRLOG_PTR
- IWL_UCODE_TLV_INIT_EVTLOG_PTR
- IWL_UCODE_TLV_INIT_EVTLOG_SIZE
- IWL_UCODE_TLV_INST
- IWL_UCODE_TLV_INVALID
- IWL_UCODE_TLV_LMAC_DEBUG_ADDRS
- IWL_UCODE_TLV_NUM_OF_CPU
- IWL_UCODE_TLV_N_SCAN_CHANNELS
- IWL_UCODE_TLV_PAGING
- IWL_UCODE_TLV_PAN
- IWL_UCODE_TLV_PHY_CALIBRATION_SIZE
- IWL_UCODE_TLV_PHY_SKU
- IWL_UCODE_TLV_PROBE_MAX_LEN
- IWL_UCODE_TLV_RUNT_ERRLOG_PTR
- IWL_UCODE_TLV_RUNT_EVTLOG_PTR
- IWL_UCODE_TLV_RUNT_EVTLOG_SIZE
- IWL_UCODE_TLV_SECURE_SEC_INIT
- IWL_UCODE_TLV_SECURE_SEC_RT
- IWL_UCODE_TLV_SECURE_SEC_WOWLAN
- IWL_UCODE_TLV_SEC_INIT
- IWL_UCODE_TLV_SEC_RT
- IWL_UCODE_TLV_SEC_RT_USNIFFER
- IWL_UCODE_TLV_SEC_WOWLAN
- IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION
- IWL_UCODE_TLV_TYPE_DEBUG_INFO
- IWL_UCODE_TLV_TYPE_HCMD
- IWL_UCODE_TLV_TYPE_REGIONS
- IWL_UCODE_TLV_TYPE_TRIGGERS
- IWL_UCODE_TLV_UMAC_DEBUG_ADDRS
- IWL_UCODE_TLV_WOWLAN_DATA
- IWL_UCODE_TLV_WOWLAN_INST
- IWL_UCODE_TYPE_MAX
- IWL_UCODE_WOWLAN
- IWL_UMAC_SCAN_FLAG_PREEMPTIVE
- IWL_UMAC_SCAN_FLAG_START_NOTIF
- IWL_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER
- IWL_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL
- IWL_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL
- IWL_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL
- IWL_UMAC_SCAN_GEN_FLAGS_FRAGMENTED
- IWL_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE
- IWL_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED
- IWL_UMAC_SCAN_GEN_FLAGS_MATCH
- IWL_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME
- IWL_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID
- IWL_UMAC_SCAN_GEN_FLAGS_OVER_BT
- IWL_UMAC_SCAN_GEN_FLAGS_PASSIVE
- IWL_UMAC_SCAN_GEN_FLAGS_PASS_ALL
- IWL_UMAC_SCAN_GEN_FLAGS_PERIODIC
- IWL_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT
- IWL_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP
- IWL_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE
- IWL_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED
- IWL_UMAC_SCAN_UID_SEQ_OFFSET
- IWL_UMAC_SCAN_UID_TYPE_OFFSET
- IWL_UNIFIED_SCAN_CHANNEL_FULL
- IWL_UNIFIED_SCAN_CHANNEL_PARTIAL
- IWL_WAKEUP_BY_11W_UNPROTECTED_DEAUTH_OR_DISASSOC
- IWL_WAKEUP_BY_PATTERN_IPV4_TCP_SYN
- IWL_WAKEUP_BY_PATTERN_IPV4_TCP_SYN_WILDCARD
- IWL_WAKEUP_BY_PATTERN_IPV6_TCP_SYN
- IWL_WAKEUP_BY_PATTERN_IPV6_TCP_SYN_WILDCARD
- IWL_WAKEUP_D3_CONFIG_FW_ERROR
- IWL_WARN
- IWL_WATCHDOG_DISABLED
- IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF
- IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE
- IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS
- IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET
- IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE
- IWL_WOWLAN_GTK_IDX_MASK
- IWL_WOWLAN_MAX_PATTERNS
- IWL_WOWLAN_MAX_PATTERN_LEN
- IWL_WOWLAN_MIN_PATTERN_LEN
- IWL_WOWLAN_REKEY_POST_REKEY
- IWL_WOWLAN_REKEY_WHILE_REKEY
- IWL_WOWLAN_REMOTE_WAKE_MAX_PACKET_LEN
- IWL_WOWLAN_REMOTE_WAKE_MAX_TOKENS
- IWL_WOWLAN_TCP_MAX_PACKET_LEN
- IWL_WOWLAN_WAKEUP_4WAY_HANDSHAKE
- IWL_WOWLAN_WAKEUP_BCN_FILTERING
- IWL_WOWLAN_WAKEUP_BEACON_MISS
- IWL_WOWLAN_WAKEUP_BY_BEACON_FILTERED_IN
- IWL_WOWLAN_WAKEUP_BY_D3_WAKEUP_HOST_TIMER
- IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_DEAUTH
- IWL_WOWLAN_WAKEUP_BY_DISCONNECTION_ON_MISSED_BEACON
- IWL_WOWLAN_WAKEUP_BY_EAPOL_REQUEST
- IWL_WOWLAN_WAKEUP_BY_FOUR_WAY_HANDSHAKE
- IWL_WOWLAN_WAKEUP_BY_GTK_REKEY_FAILURE
- IWL_WOWLAN_WAKEUP_BY_IOAC_MAGIC_PACKET
- IWL_WOWLAN_WAKEUP_BY_MAGIC_PACKET
- IWL_WOWLAN_WAKEUP_BY_NON_WIRELESS
- IWL_WOWLAN_WAKEUP_BY_PATTERN
- IWL_WOWLAN_WAKEUP_BY_REM_WAKE_LINK_LOSS
- IWL_WOWLAN_WAKEUP_BY_REM_WAKE_SIGNATURE_TABLE
- IWL_WOWLAN_WAKEUP_BY_REM_WAKE_TCP_EXTERNAL
- IWL_WOWLAN_WAKEUP_BY_REM_WAKE_WAKEUP_PACKET
- IWL_WOWLAN_WAKEUP_BY_RFKILL_DEASSERTED
- IWL_WOWLAN_WAKEUP_BY_RXFRAME_FILTERED_IN
- IWL_WOWLAN_WAKEUP_BY_UCODE_ERROR
- IWL_WOWLAN_WAKEUP_EAP_IDENT_REQ
- IWL_WOWLAN_WAKEUP_ENABLE_NET_DETECT
- IWL_WOWLAN_WAKEUP_GTK_REKEY_FAIL
- IWL_WOWLAN_WAKEUP_HOST_TIMER
- IWL_WOWLAN_WAKEUP_IOAC_MAGIC_PACKET
- IWL_WOWLAN_WAKEUP_LINK_CHANGE
- IWL_WOWLAN_WAKEUP_MAGIC_PACKET
- IWL_WOWLAN_WAKEUP_PATTERN_MATCH
- IWL_WOWLAN_WAKEUP_REMOTE_LINK_LOSS
- IWL_WOWLAN_WAKEUP_REMOTE_SIGNATURE_TABLE
- IWL_WOWLAN_WAKEUP_REMOTE_TCP_EXTERNAL
- IWL_WOWLAN_WAKEUP_REMOTE_WAKEUP_PACKET
- IWL_WOWLAN_WAKEUP_RF_KILL_DEASSERT
- IWL_WOWLAN_WAKEUP_RX_FRAME
- IWL_WRITABLE_TRIPS_MSK
- IWMAX_BITRATES
- IWMAX_BSS
- IWMAX_FREQ
- IWMMXT_MAGIC
- IWMMXT_SIZE
- IWMMXT_STORAGE_SIZE
- IWPM_CLIENT_DEV_INFO_ERR
- IWPM_CREATE_MAPPING_ERR
- IWPM_DEVNAME_SIZE
- IWPM_DUPLICATE_MAPPING_ERR
- IWPM_FLAGS_NO_PORT_MAP
- IWPM_IFNAME_SIZE
- IWPM_INVALID_NLMSG_ERR
- IWPM_IPADDR_SIZE
- IWPM_MAPINFO_HASH_MASK
- IWPM_MAPINFO_HASH_SIZE
- IWPM_MAPINFO_SKB_COUNT
- IWPM_MSG_SIZE
- IWPM_NLA_ERR_CODE
- IWPM_NLA_ERR_MAX
- IWPM_NLA_ERR_SEQ
- IWPM_NLA_ERR_UNSPEC
- IWPM_NLA_HELLO_ABI_VERSION
- IWPM_NLA_HELLO_MAX
- IWPM_NLA_HELLO_UNSPEC
- IWPM_NLA_MANAGE_ADDR
- IWPM_NLA_MANAGE_FLAGS
- IWPM_NLA_MANAGE_MAPPED_LOC_ADDR
- IWPM_NLA_MANAGE_MAPPING_MAX
- IWPM_NLA_MANAGE_MAPPING_SEQ
- IWPM_NLA_MANAGE_MAPPING_UNSPEC
- IWPM_NLA_MAPINFO_ACK_NUM
- IWPM_NLA_MAPINFO_FLAGS
- IWPM_NLA_MAPINFO_LOCAL_ADDR
- IWPM_NLA_MAPINFO_MAPPED_ADDR
- IWPM_NLA_MAPINFO_MAX
- IWPM_NLA_MAPINFO_NUM_MAX
- IWPM_NLA_MAPINFO_NUM_UNSPEC
- IWPM_NLA_MAPINFO_REQ_MAX
- IWPM_NLA_MAPINFO_REQ_UNSPEC
- IWPM_NLA_MAPINFO_SEND_MAX
- IWPM_NLA_MAPINFO_SEND_NUM
- IWPM_NLA_MAPINFO_SEQ
- IWPM_NLA_MAPINFO_ULIB_NAME
- IWPM_NLA_MAPINFO_ULIB_VER
- IWPM_NLA_MAPINFO_UNSPEC
- IWPM_NLA_QUERY_FLAGS
- IWPM_NLA_QUERY_LOCAL_ADDR
- IWPM_NLA_QUERY_MAPPING_MAX
- IWPM_NLA_QUERY_MAPPING_SEQ
- IWPM_NLA_QUERY_MAPPING_UNSPEC
- IWPM_NLA_QUERY_REMOTE_ADDR
- IWPM_NLA_REG_IBDEV_NAME
- IWPM_NLA_REG_IF_NAME
- IWPM_NLA_REG_PID_MAX
- IWPM_NLA_REG_PID_SEQ
- IWPM_NLA_REG_PID_UNSPEC
- IWPM_NLA_REG_ULIB_NAME
- IWPM_NLA_REMOVE_MAPPING_MAX
- IWPM_NLA_RMANAGE_ADDR
- IWPM_NLA_RMANAGE_MAPPED_LOC_ADDR
- IWPM_NLA_RMANAGE_MAPPING_ERR
- IWPM_NLA_RMANAGE_MAPPING_MAX
- IWPM_NLA_RMANAGE_MAPPING_SEQ
- IWPM_NLA_RMANAGE_MAPPING_UNSPEC
- IWPM_NLA_RQUERY_LOCAL_ADDR
- IWPM_NLA_RQUERY_MAPPED_LOC_ADDR
- IWPM_NLA_RQUERY_MAPPED_REM_ADDR
- IWPM_NLA_RQUERY_MAPPING_ERR
- IWPM_NLA_RQUERY_MAPPING_MAX
- IWPM_NLA_RQUERY_MAPPING_SEQ
- IWPM_NLA_RQUERY_MAPPING_UNSPEC
- IWPM_NLA_RQUERY_REMOTE_ADDR
- IWPM_NLA_RREG_IBDEV_NAME
- IWPM_NLA_RREG_PID_ERR
- IWPM_NLA_RREG_PID_MAX
- IWPM_NLA_RREG_PID_SEQ
- IWPM_NLA_RREG_PID_UNSPEC
- IWPM_NLA_RREG_ULIB_NAME
- IWPM_NLA_RREG_ULIB_VER
- IWPM_NL_RETRANS
- IWPM_NL_TIMEOUT
- IWPM_PID_UNAVAILABLE
- IWPM_PID_UNDEFINED
- IWPM_REG_INCOMPL
- IWPM_REG_UNDEF
- IWPM_REG_VALID
- IWPM_REMINFO_HASH_MASK
- IWPM_REMINFO_HASH_SIZE
- IWPM_REMOTE_QUERY_REJECT
- IWPM_UABI_VERSION
- IWPM_UABI_VERSION_MIN
- IWPM_ULIBNAME_SIZE
- IWPM_UNKNOWN_MAPPING_ERR
- IWPM_USER_LIB_INFO_ERR
- IWPRIV_ADDR
- IWPRIV_GET
- IWPRIV_SET_ADDR
- IWPRIV_SET_SSID
- IWPRIV_SET_U32
- IWPRIV_SSID
- IWPRIV_U32
- IWR
- IWRITE_LOCK
- IWRITE_UNLOCK
- IWRRD5
- IWRRD6
- IWRRS5
- IWRRS6
- IWRWD5
- IWRWD6
- IWRWS5
- IWRWS6
- IWR_ADDR
- IWR_INT0
- IWR_INT1
- IWR_INT2
- IWR_INT3
- IWR_INT4
- IWR_INT5
- IWR_INT6
- IWR_INT7
- IWR_IRQ1
- IWR_IRQ2
- IWR_IRQ3
- IWR_IRQ6
- IWR_IRQ7
- IWR_KB
- IWR_PEN
- IWR_PWM
- IWR_RTC
- IWR_SPIM
- IWR_SPIS
- IWR_TMR1
- IWR_TMR2
- IWR_UART
- IWR_WDT
- IWW5
- IWW6
- IW_ADD_MCAST
- IW_AEQ_SIZE
- IW_AUTH_80211_AUTH_ALG
- IW_AUTH_ALG_LEAP
- IW_AUTH_ALG_OPEN_SYSTEM
- IW_AUTH_ALG_SHARED_KEY
- IW_AUTH_CIPHER_AES_CMAC
- IW_AUTH_CIPHER_CCMP
- IW_AUTH_CIPHER_GROUP
- IW_AUTH_CIPHER_GROUP_MGMT
- IW_AUTH_CIPHER_NONE
- IW_AUTH_CIPHER_PAIRWISE
- IW_AUTH_CIPHER_TKIP
- IW_AUTH_CIPHER_WEP104
- IW_AUTH_CIPHER_WEP40
- IW_AUTH_DROP_UNENCRYPTED
- IW_AUTH_FLAGS
- IW_AUTH_INDEX
- IW_AUTH_KEY_MGMT
- IW_AUTH_KEY_MGMT_802_1X
- IW_AUTH_KEY_MGMT_PSK
- IW_AUTH_MFP
- IW_AUTH_MFP_DISABLED
- IW_AUTH_MFP_OPTIONAL
- IW_AUTH_MFP_REQUIRED
- IW_AUTH_PRIVACY_INVOKED
- IW_AUTH_ROAMING_CONTROL
- IW_AUTH_ROAMING_DISABLE
- IW_AUTH_ROAMING_ENABLE
- IW_AUTH_RX_UNENCRYPTED_EAPOL
- IW_AUTH_TKIP_COUNTERMEASURES
- IW_AUTH_WPA_ENABLED
- IW_AUTH_WPA_VERSION
- IW_AUTH_WPA_VERSION_DISABLED
- IW_AUTH_WPA_VERSION_WPA
- IW_AUTH_WPA_VERSION_WPA2
- IW_CCQ_SIZE
- IW_CEQ_SIZE
- IW_CFG_FPM_QP_COUNT
- IW_CM_EVENT_CLOSE
- IW_CM_EVENT_CONNECT_REPLY
- IW_CM_EVENT_CONNECT_REQUEST
- IW_CM_EVENT_DISCONNECT
- IW_CM_EVENT_ESTABLISHED
- IW_CM_H
- IW_CM_STATE_CLOSING
- IW_CM_STATE_CONN_RECV
- IW_CM_STATE_CONN_SENT
- IW_CM_STATE_DESTROYING
- IW_CM_STATE_ESTABLISHED
- IW_CM_STATE_IDLE
- IW_CM_STATE_LISTEN
- IW_CQ_COMPL_EVENT
- IW_CQ_COMPL_SOLICITED
- IW_CUSTOM_MAX
- IW_DATA_RATE_MAX_LABELS
- IW_DEL_MCAST
- IW_DESCR_FLAG_DUMP
- IW_DESCR_FLAG_EVENT
- IW_DESCR_FLAG_NOMAX
- IW_DESCR_FLAG_NONE
- IW_DESCR_FLAG_RESTRICT
- IW_DESCR_FLAG_WAIT
- IW_ENCODE_ALG_AES_CMAC
- IW_ENCODE_ALG_CCMP
- IW_ENCODE_ALG_NONE
- IW_ENCODE_ALG_PMK
- IW_ENCODE_ALG_TKIP
- IW_ENCODE_ALG_WEP
- IW_ENCODE_DISABLED
- IW_ENCODE_ENABLED
- IW_ENCODE_EXT_GROUP_KEY
- IW_ENCODE_EXT_RX_SEQ_VALID
- IW_ENCODE_EXT_SET_TX_KEY
- IW_ENCODE_EXT_TX_SEQ_VALID
- IW_ENCODE_FLAGS
- IW_ENCODE_INDEX
- IW_ENCODE_MODE
- IW_ENCODE_NOKEY
- IW_ENCODE_OPEN
- IW_ENCODE_RESTRICTED
- IW_ENCODE_SEQ_MAX_SIZE
- IW_ENCODE_TEMP
- IW_ENCODING_TOKEN_MAX
- IW_ENC_CAPA_4WAY_HANDSHAKE
- IW_ENC_CAPA_CIPHER_CCMP
- IW_ENC_CAPA_CIPHER_TKIP
- IW_ENC_CAPA_WPA
- IW_ENC_CAPA_WPA2
- IW_ESSID_MAX_SIZE
- IW_EVENT_CAPA_BASE
- IW_EVENT_CAPA_INDEX
- IW_EVENT_CAPA_K_0
- IW_EVENT_CAPA_K_1
- IW_EVENT_CAPA_MASK
- IW_EVENT_CAPA_SET
- IW_EVENT_CAPA_SET_KERNEL
- IW_EVENT_IDX
- IW_EV_ADDR_LEN
- IW_EV_ADDR_PK_LEN
- IW_EV_CHAR_LEN
- IW_EV_CHAR_PK_LEN
- IW_EV_COMPAT_ADDR_LEN
- IW_EV_COMPAT_CHAR_LEN
- IW_EV_COMPAT_FREQ_LEN
- IW_EV_COMPAT_LCP_LEN
- IW_EV_COMPAT_PARAM_LEN
- IW_EV_COMPAT_POINT_LEN
- IW_EV_COMPAT_POINT_OFF
- IW_EV_COMPAT_QUAL_LEN
- IW_EV_COMPAT_UINT_LEN
- IW_EV_FREQ_LEN
- IW_EV_FREQ_PK_LEN
- IW_EV_LCP_LEN
- IW_EV_LCP_PK_LEN
- IW_EV_PARAM_LEN
- IW_EV_PARAM_PK_LEN
- IW_EV_POINT_LEN
- IW_EV_POINT_OFF
- IW_EV_POINT_PK_LEN
- IW_EV_QUAL_LEN
- IW_EV_QUAL_PK_LEN
- IW_EV_UINT_LEN
- IW_EV_UINT_PK_LEN
- IW_FIRST_QPN
- IW_FREQ_AUTO
- IW_FREQ_FIXED
- IW_F_NO_PORT_MAP
- IW_GENERIC_IE_MAX
- IW_HANDLER
- IW_HANDLER_VERSION
- IW_HEADER_TYPE_ADDR
- IW_HEADER_TYPE_CHAR
- IW_HEADER_TYPE_FREQ
- IW_HEADER_TYPE_NULL
- IW_HEADER_TYPE_PARAM
- IW_HEADER_TYPE_POINT
- IW_HEADER_TYPE_QUAL
- IW_HEADER_TYPE_UINT
- IW_HMC_OBJ_TYPE_NUM
- IW_IOCTL
- IW_IOCTL_IDX
- IW_IS_GET
- IW_IS_SET
- IW_MAX_AP
- IW_MAX_BITRATES
- IW_MAX_ENCODING_SIZES
- IW_MAX_FREQUENCIES
- IW_MAX_SPY
- IW_MAX_TXPOWER
- IW_MEMREG_TYPE_CQ
- IW_MEMREG_TYPE_MEM
- IW_MEMREG_TYPE_QP
- IW_MGMT_INFO_ELEMENT_CHALLENGE_TEXT
- IW_MGMT_INFO_ELEMENT_CS_PARAMETER_SET
- IW_MGMT_INFO_ELEMENT_CS_TIM
- IW_MGMT_INFO_ELEMENT_DS_PARAMETER_SET
- IW_MGMT_INFO_ELEMENT_FH_PARAMETER_SET
- IW_MGMT_INFO_ELEMENT_IBSS_PARAMETER_SET
- IW_MGMT_INFO_ELEMENT_SSID
- IW_MGMT_INFO_ELEMENT_SUPPORTED_RATES
- IW_MGMT_RATE_LABEL_11MBIT
- IW_MGMT_RATE_LABEL_1MBIT
- IW_MGMT_RATE_LABEL_2MBIT
- IW_MGMT_RATE_LABEL_5_5MBIT
- IW_MGMT_RATE_LABEL_MANDATORY
- IW_MICFAILURE_COUNT
- IW_MICFAILURE_GROUP
- IW_MICFAILURE_KEY_ID
- IW_MICFAILURE_PAIRWISE
- IW_MICFAILURE_STAKEY
- IW_MLME_ASSOC
- IW_MLME_AUTH
- IW_MLME_DEAUTH
- IW_MLME_DISASSOC
- IW_MODE_ADHOC
- IW_MODE_AUTO
- IW_MODE_INFRA
- IW_MODE_MASTER
- IW_MODE_MESH
- IW_MODE_MONITOR
- IW_MODE_REPEAT
- IW_MODE_SECOND
- IW_PMKID_CAND_PREAUTH
- IW_PMKID_LEN
- IW_PMKSA_ADD
- IW_PMKSA_FLUSH
- IW_PMKSA_REMOVE
- IW_POWER_ALL_R
- IW_POWER_FORCE_S
- IW_POWER_MAX
- IW_POWER_MIN
- IW_POWER_MODE
- IW_POWER_MODIFIER
- IW_POWER_MULTICAST_R
- IW_POWER_ON
- IW_POWER_PERIOD
- IW_POWER_RELATIVE
- IW_POWER_REPEATER
- IW_POWER_TIMEOUT
- IW_POWER_TYPE
- IW_POWER_UNICAST_R
- IW_PRIV_SIZE_FIXED
- IW_PRIV_SIZE_MASK
- IW_PRIV_TYPE_ADDR
- IW_PRIV_TYPE_BYTE
- IW_PRIV_TYPE_CHAR
- IW_PRIV_TYPE_FLOAT
- IW_PRIV_TYPE_INT
- IW_PRIV_TYPE_MASK
- IW_PRIV_TYPE_NONE
- IW_QUAL_ALL_INVALID
- IW_QUAL_ALL_UPDATED
- IW_QUAL_DBM
- IW_QUAL_LEVEL_INVALID
- IW_QUAL_LEVEL_UPDATED
- IW_QUAL_NOISE_INVALID
- IW_QUAL_NOISE_UPDATED
- IW_QUAL_QUAL_INVALID
- IW_QUAL_QUAL_UPDATED
- IW_QUAL_RCPI
- IW_REG0_SIZE
- IW_REG_DOMAIN_DOC
- IW_REG_DOMAIN_ETSI
- IW_REG_DOMAIN_FCC
- IW_REG_DOMAIN_FRANCE
- IW_REG_DOMAIN_ISRAEL
- IW_REG_DOMAIN_MKK
- IW_REG_DOMAIN_MKK1
- IW_REG_DOMAIN_SPAIN
- IW_REQUEST_FLAG_COMPAT
- IW_RETRY_LIFETIME
- IW_RETRY_LIMIT
- IW_RETRY_LONG
- IW_RETRY_MAX
- IW_RETRY_MIN
- IW_RETRY_MODIFIER
- IW_RETRY_ON
- IW_RETRY_RELATIVE
- IW_RETRY_SHORT
- IW_RETRY_TYPE
- IW_SCAN_ALL_ESSID
- IW_SCAN_ALL_FREQ
- IW_SCAN_ALL_MODE
- IW_SCAN_ALL_RATE
- IW_SCAN_CAPA_BSSID
- IW_SCAN_CAPA_CHANNEL
- IW_SCAN_CAPA_ESSID
- IW_SCAN_CAPA_MODE
- IW_SCAN_CAPA_NONE
- IW_SCAN_CAPA_RATE
- IW_SCAN_CAPA_TIME
- IW_SCAN_CAPA_TYPE
- IW_SCAN_DEFAULT
- IW_SCAN_MAX_DATA
- IW_SCAN_THIS_ESSID
- IW_SCAN_THIS_FREQ
- IW_SCAN_THIS_MODE
- IW_SCAN_THIS_RATE
- IW_SCAN_TYPE_ACTIVE
- IW_SCAN_TYPE_PASSIVE
- IW_SW_CONTEXT_ALIGN
- IW_TXPOW_DBM
- IW_TXPOW_MWATT
- IW_TXPOW_RANGE
- IW_TXPOW_RELATIVE
- IW_TXPOW_TYPE
- IW_TX_TIMEOUT
- IW_WIRELESS_SPY
- IW_WIRELESS_THRSPY
- IXANY
- IXATTRSIZE
- IXDP425_NAND_ADDR_BYTE
- IXDP425_NAND_CMD_BYTE
- IXDP425_NAND_NCE_PIN
- IXDP425_SCL_PIN
- IXDP425_SDA_PIN
- IXE_STAT
- IXGBEVF_82599_RETA_SIZE
- IXGBEVF_DEFAULT_RXD
- IXGBEVF_DEFAULT_TXD
- IXGBEVF_ESP_FEATURES
- IXGBEVF_FLAGS_LEGACY_RX
- IXGBEVF_GLOBAL_STATS_LEN
- IXGBEVF_GSO_PARTIAL_FEATURES
- IXGBEVF_LAST_OFFSET
- IXGBEVF_MAX_FRAME_BUILD_SKB
- IXGBEVF_MAX_MAC_HDR_LEN
- IXGBEVF_MAX_NETWORK_HDR_LEN
- IXGBEVF_MAX_RSS_QUEUES
- IXGBEVF_MAX_RXD
- IXGBEVF_MAX_RX_DESC_POLL
- IXGBEVF_MAX_TXD
- IXGBEVF_MIN_RXD
- IXGBEVF_MIN_TXD
- IXGBEVF_NETDEV_STAT
- IXGBEVF_PRIV_FLAGS_LEGACY_RX
- IXGBEVF_PRIV_FLAGS_STR_LEN
- IXGBEVF_QUEUE_STATS_LEN
- IXGBEVF_QV_LOCKED
- IXGBEVF_QV_OWNED
- IXGBEVF_QV_STATE_DISABLED
- IXGBEVF_QV_STATE_IDLE
- IXGBEVF_QV_STATE_NAPI
- IXGBEVF_QV_STATE_NAPI_YIELD
- IXGBEVF_QV_STATE_POLL
- IXGBEVF_QV_STATE_POLL_YIELD
- IXGBEVF_QV_USER_PEND
- IXGBEVF_QV_YIELD
- IXGBEVF_RSS_HASH_KEY_SIZE
- IXGBEVF_RXBUFFER_2048
- IXGBEVF_RXBUFFER_256
- IXGBEVF_RXBUFFER_3072
- IXGBEVF_RX_BUFFER_WRITE
- IXGBEVF_RX_DESC
- IXGBEVF_RX_DMA_ATTR
- IXGBEVF_RX_HDR_SIZE
- IXGBEVF_SKB_PAD
- IXGBEVF_STAT
- IXGBEVF_STATS
- IXGBEVF_STATS_LEN
- IXGBEVF_TEST_LEN
- IXGBEVF_TX_CTXTDESC
- IXGBEVF_TX_DESC
- IXGBEVF_VFRSSRK_REGS
- IXGBEVF_X550_VFRETA_SIZE
- IXGBEVF_XCAST_MODE_ALLMULTI
- IXGBEVF_XCAST_MODE_MULTI
- IXGBEVF_XCAST_MODE_NONE
- IXGBEVF_XCAST_MODE_PROMISC
- IXGBEVF_XDP_CONSUMED
- IXGBEVF_XDP_PASS
- IXGBEVF_XDP_TX
- IXGBE_100K_ITR
- IXGBE_12K_ITR
- IXGBE_20K_ITR
- IXGBE_2K_TOO_SMALL_WITH_PADDING
- IXGBE_82598_MAX_RX_QUEUES
- IXGBE_82598_MAX_TX_QUEUES
- IXGBE_82598_MC_TBL_SIZE
- IXGBE_82598_RAR_ENTRIES
- IXGBE_82598_RX_PB_SIZE
- IXGBE_82598_VFT_TBL_SIZE
- IXGBE_82599_MAX_RX_QUEUES
- IXGBE_82599_MAX_TX_QUEUES
- IXGBE_82599_MC_TBL_SIZE
- IXGBE_82599_RAR_ENTRIES
- IXGBE_82599_RX_PB_SIZE
- IXGBE_82599_VFT_TBL_SIZE
- IXGBE_82599_VF_DEVICE_ID
- IXGBE_82599_VMDQ_2Q_MASK
- IXGBE_82599_VMDQ_4Q_MASK
- IXGBE_82599_VMDQ_8Q_MASK
- IXGBE_ADVTXD_CC
- IXGBE_ADVTXD_DCMD_DDTYP_ISCSI
- IXGBE_ADVTXD_DCMD_DEXT
- IXGBE_ADVTXD_DCMD_EOP
- IXGBE_ADVTXD_DCMD_IFCS
- IXGBE_ADVTXD_DCMD_RS
- IXGBE_ADVTXD_DCMD_TSE
- IXGBE_ADVTXD_DCMD_VLE
- IXGBE_ADVTXD_DTALEN_MASK
- IXGBE_ADVTXD_DTYP_CTXT
- IXGBE_ADVTXD_DTYP_DATA
- IXGBE_ADVTXD_DTYP_MASK
- IXGBE_ADVTXD_FCOEF_EOF_A
- IXGBE_ADVTXD_FCOEF_EOF_MASK
- IXGBE_ADVTXD_FCOEF_EOF_N
- IXGBE_ADVTXD_FCOEF_EOF_NI
- IXGBE_ADVTXD_FCOEF_EOF_T
- IXGBE_ADVTXD_FCOEF_ORIE
- IXGBE_ADVTXD_FCOEF_ORIS
- IXGBE_ADVTXD_FCOEF_PARINC
- IXGBE_ADVTXD_FCOEF_SOF
- IXGBE_ADVTXD_IDX_SHIFT
- IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK
- IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK
- IXGBE_ADVTXD_L4LEN_SHIFT
- IXGBE_ADVTXD_MACLEN_SHIFT
- IXGBE_ADVTXD_MAC_LINKSEC
- IXGBE_ADVTXD_MAC_TSTAMP
- IXGBE_ADVTXD_MSS_SHIFT
- IXGBE_ADVTXD_PAYLEN_SHIFT
- IXGBE_ADVTXD_POPTS_IPSEC
- IXGBE_ADVTXD_POPTS_ISCO_1ST
- IXGBE_ADVTXD_POPTS_ISCO_FULL
- IXGBE_ADVTXD_POPTS_ISCO_LAST
- IXGBE_ADVTXD_POPTS_ISCO_MDL
- IXGBE_ADVTXD_POPTS_IXSM
- IXGBE_ADVTXD_POPTS_RSV
- IXGBE_ADVTXD_POPTS_SHIFT
- IXGBE_ADVTXD_POPTS_TXSM
- IXGBE_ADVTXD_STAT_DD
- IXGBE_ADVTXD_STAT_RSV
- IXGBE_ADVTXD_STAT_SN_CRC
- IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN
- IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP
- IXGBE_ADVTXD_TUCMD_IPV4
- IXGBE_ADVTXD_TUCMD_IPV6
- IXGBE_ADVTXD_TUCMD_L4T_RSV
- IXGBE_ADVTXD_TUCMD_L4T_SCTP
- IXGBE_ADVTXD_TUCMD_L4T_TCP
- IXGBE_ADVTXD_TUCMD_L4T_UDP
- IXGBE_ADVTXD_TUCMD_MKRREQ
- IXGBE_ADVTXD_VLAN_SHIFT
- IXGBE_ADVTXT_TUCMD_FCOE
- IXGBE_AIS
- IXGBE_ALL_RAR_ENTRIES
- IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
- IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
- IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
- IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC
- IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET
- IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET
- IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
- IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
- IXGBE_ANLP1
- IXGBE_ANLP1_AN_STATE_MASK
- IXGBE_ANLP1_ASM_PAUSE
- IXGBE_ANLP1_PAUSE
- IXGBE_ANLP1_SYM_PAUSE
- IXGBE_ANLP2
- IXGBE_ANLPNP1
- IXGBE_ANLPNP2
- IXGBE_APAE
- IXGBE_ARD
- IXGBE_ATLAS0_CONFIG_PTR
- IXGBE_ATLAS1_CONFIG_PTR
- IXGBE_ATLASCTL
- IXGBE_ATLASCTL_WRITE_CMD
- IXGBE_ATLAS_PDN_10G
- IXGBE_ATLAS_PDN_1G
- IXGBE_ATLAS_PDN_AN
- IXGBE_ATLAS_PDN_LPBK
- IXGBE_ATLAS_PDN_TX_10G_QL_ALL
- IXGBE_ATLAS_PDN_TX_1G_QL_ALL
- IXGBE_ATLAS_PDN_TX_AN_QL_ALL
- IXGBE_ATLAS_PDN_TX_REG_EN
- IXGBE_ATR_BUCKET_HASH_KEY
- IXGBE_ATR_COMMON_HASH_KEY
- IXGBE_ATR_FLOW_TYPE_IPV4
- IXGBE_ATR_FLOW_TYPE_IPV6
- IXGBE_ATR_FLOW_TYPE_SCTPV4
- IXGBE_ATR_FLOW_TYPE_SCTPV6
- IXGBE_ATR_FLOW_TYPE_TCPV4
- IXGBE_ATR_FLOW_TYPE_TCPV6
- IXGBE_ATR_FLOW_TYPE_UDPV4
- IXGBE_ATR_FLOW_TYPE_UDPV6
- IXGBE_ATR_HASH_MASK
- IXGBE_ATR_L4TYPE_IPV6_MASK
- IXGBE_ATR_L4TYPE_MASK
- IXGBE_ATR_L4TYPE_SCTP
- IXGBE_ATR_L4TYPE_TCP
- IXGBE_ATR_L4TYPE_TUNNEL_MASK
- IXGBE_ATR_L4TYPE_UDP
- IXGBE_ATR_SIGNATURE_HASH_KEY
- IXGBE_AUTOC
- IXGBE_AUTOC2
- IXGBE_AUTOC2_10G_KR
- IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
- IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT
- IXGBE_AUTOC2_10G_SFI
- IXGBE_AUTOC2_10G_XFI
- IXGBE_AUTOC2_LINK_DISABLE_MASK
- IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK
- IXGBE_AUTOC2_UPPER_MASK
- IXGBE_AUTOC3
- IXGBE_AUTOC_10G_CX4
- IXGBE_AUTOC_10G_KX4
- IXGBE_AUTOC_10G_PMA_PMD_MASK
- IXGBE_AUTOC_10G_PMA_PMD_SHIFT
- IXGBE_AUTOC_10G_XAUI
- IXGBE_AUTOC_1G_BX
- IXGBE_AUTOC_1G_KX
- IXGBE_AUTOC_1G_KX_BX
- IXGBE_AUTOC_1G_PMA_PMD_MASK
- IXGBE_AUTOC_1G_PMA_PMD_SHIFT
- IXGBE_AUTOC_1G_SFI
- IXGBE_AUTOC_AN_RESTART
- IXGBE_AUTOC_AN_RX_ALIGN
- IXGBE_AUTOC_AN_RX_DRIFT
- IXGBE_AUTOC_AN_RX_LOOSE
- IXGBE_AUTOC_ASM_PAUSE
- IXGBE_AUTOC_FECA
- IXGBE_AUTOC_FECR
- IXGBE_AUTOC_FLU
- IXGBE_AUTOC_KR_SUPP
- IXGBE_AUTOC_KX4_KX_SUPP_MASK
- IXGBE_AUTOC_KX4_SUPP
- IXGBE_AUTOC_KX_SUPP
- IXGBE_AUTOC_LMS_10G_LINK_NO_AN
- IXGBE_AUTOC_LMS_10G_SERIAL
- IXGBE_AUTOC_LMS_1G_AN
- IXGBE_AUTOC_LMS_1G_LINK_NO_AN
- IXGBE_AUTOC_LMS_ATTACH_TYPE
- IXGBE_AUTOC_LMS_KX4_AN
- IXGBE_AUTOC_LMS_KX4_AN_1G_AN
- IXGBE_AUTOC_LMS_KX4_KX_KR
- IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
- IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
- IXGBE_AUTOC_LMS_MASK
- IXGBE_AUTOC_LMS_SGMII_1G_100M
- IXGBE_AUTOC_LMS_SHIFT
- IXGBE_AUTOC_PAUSE
- IXGBE_AUTOC_PD_TMR
- IXGBE_AUTOC_RF
- IXGBE_AUTOC_SYM_PAUSE
- IXGBE_AUTO_NEG_LP_1000BASE_CAP
- IXGBE_AUTO_NEG_LP_STATUS
- IXGBE_AUTO_NEG_TIME
- IXGBE_AUXSTMPH0
- IXGBE_AUXSTMPH1
- IXGBE_AUXSTMPL0
- IXGBE_AUXSTMPL1
- IXGBE_B2BT
- IXGBE_B2OGPRC
- IXGBE_B2OSPC
- IXGBE_BAD_L2A_QUEUE
- IXGBE_BARCTRL
- IXGBE_BARCTRL_CSRSIZE
- IXGBE_BARCTRL_FLSIZE
- IXGBE_BARCTRL_FLSIZE_SHIFT
- IXGBE_BAR_CTRL_82599
- IXGBE_BMCIP
- IXGBE_BMCIPVAL
- IXGBE_BPRC
- IXGBE_BPTC
- IXGBE_BT2KB
- IXGBE_BUFFCNT_MAX
- IXGBE_BY_MAC
- IXGBE_CABLE_DC
- IXGBE_CABLE_DO
- IXGBE_CAT
- IXGBE_CB
- IXGBE_CDQ_MBR_82599
- IXGBE_CIAA
- IXGBE_CIAA_8259X
- IXGBE_CIAA_X540
- IXGBE_CIAA_X550
- IXGBE_CIAA_X550EM_a
- IXGBE_CIAA_X550EM_x
- IXGBE_CIAD
- IXGBE_CIAD_8259X
- IXGBE_CIAD_X540
- IXGBE_CIAD_X550
- IXGBE_CIAD_X550EM_a
- IXGBE_CIAD_X550EM_x
- IXGBE_CLEAR_VMDQ_ALL
- IXGBE_CLKTIMH
- IXGBE_CLKTIML
- IXGBE_COMPUTE_BKT_HASH_ITERATION
- IXGBE_COMPUTE_SIG_HASH_ITERATION
- IXGBE_CONTROL_EOL_NL
- IXGBE_CONTROL_MASK_NL
- IXGBE_CONTROL_NL
- IXGBE_CONTROL_SHIFT_NL
- IXGBE_CONTROL_SOL_NL
- IXGBE_CORE0_PTR
- IXGBE_CORE1_PTR
- IXGBE_CORECTL
- IXGBE_CORECTL_WRITE_CMD
- IXGBE_CORESPARE
- IXGBE_CRCERRS
- IXGBE_CS4223_SKU_ID
- IXGBE_CS4227
- IXGBE_CS4227_CHECK_DELAY
- IXGBE_CS4227_EDC_MODE_CX1
- IXGBE_CS4227_EDC_MODE_DIAG
- IXGBE_CS4227_EDC_MODE_SR
- IXGBE_CS4227_EEPROM_LOAD_OK
- IXGBE_CS4227_EEPROM_STATUS
- IXGBE_CS4227_EFUSE_PDF_SKU
- IXGBE_CS4227_EFUSE_STATUS
- IXGBE_CS4227_GLOBAL_ID_LSB
- IXGBE_CS4227_GLOBAL_ID_MSB
- IXGBE_CS4227_HOST_SPARE22_MSB
- IXGBE_CS4227_HOST_SPARE24_LSB
- IXGBE_CS4227_LINE_SPARE22_MSB
- IXGBE_CS4227_LINE_SPARE24_LSB
- IXGBE_CS4227_RESET_COMPLETE
- IXGBE_CS4227_RESET_DELAY
- IXGBE_CS4227_RESET_HOLD
- IXGBE_CS4227_RESET_PENDING
- IXGBE_CS4227_RETRIES
- IXGBE_CS4227_SCRATCH
- IXGBE_CS4227_SKU_ID
- IXGBE_CS4227_SPEED_10G
- IXGBE_CS4227_SPEED_1G
- IXGBE_CSR0_CONFIG_PTR
- IXGBE_CSR1_CONFIG_PTR
- IXGBE_CTRL
- IXGBE_CTRL_EXT
- IXGBE_CTRL_EXT_DRV_LOAD
- IXGBE_CTRL_EXT_NS_DIS
- IXGBE_CTRL_EXT_PFRSTD
- IXGBE_CTRL_EXT_RO_DIS
- IXGBE_CTRL_GIO_DIS
- IXGBE_CTRL_LNK_RST
- IXGBE_CTRL_RST
- IXGBE_CTRL_RST_MASK
- IXGBE_DAQF
- IXGBE_DATA_MASK_NL
- IXGBE_DATA_NL
- IXGBE_DCA_CTRL
- IXGBE_DCA_CTRL_DCA_DISABLE
- IXGBE_DCA_CTRL_DCA_ENABLE
- IXGBE_DCA_CTRL_DCA_MODE_CB1
- IXGBE_DCA_CTRL_DCA_MODE_CB2
- IXGBE_DCA_ID
- IXGBE_DCA_MAX_QUEUES_82598
- IXGBE_DCA_RXCTRL
- IXGBE_DCA_RXCTRL_CPUID_MASK
- IXGBE_DCA_RXCTRL_CPUID_MASK_82599
- IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
- IXGBE_DCA_RXCTRL_DATA_DCA_EN
- IXGBE_DCA_RXCTRL_DATA_WRO_EN
- IXGBE_DCA_RXCTRL_DESC_DCA_EN
- IXGBE_DCA_RXCTRL_DESC_RRO_EN
- IXGBE_DCA_RXCTRL_HEAD_DCA_EN
- IXGBE_DCA_RXCTRL_HEAD_WRO_EN
- IXGBE_DCA_TXCTRL
- IXGBE_DCA_TXCTRL_82599
- IXGBE_DCA_TXCTRL_CPUID_MASK
- IXGBE_DCA_TXCTRL_CPUID_MASK_82599
- IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
- IXGBE_DCA_TXCTRL_DATA_RRO_EN
- IXGBE_DCA_TXCTRL_DESC_DCA_EN
- IXGBE_DCA_TXCTRL_DESC_RRO_EN
- IXGBE_DCA_TXCTRL_DESC_WRO_EN
- IXGBE_DCA_TXCTRL_TX_WB_RO_EN
- IXGBE_DCB_8_TC_SUPPORT
- IXGBE_DCB_BCN_SUPPORT
- IXGBE_DCB_GSP_SUPPORT
- IXGBE_DCB_PFC_SUPPORT
- IXGBE_DCB_PG_SUPPORT
- IXGBE_DCB_UP2TC_SUPPORT
- IXGBE_DEFAULT_FCPAUSE
- IXGBE_DEFAULT_RXD
- IXGBE_DEFAULT_TXD
- IXGBE_DEFAULT_TX_WORK
- IXGBE_DELAY_NL
- IXGBE_DEVICE_CAPS
- IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP
- IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
- IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR
- IXGBE_DEVICE_CAPS_WOL_MASK
- IXGBE_DEVICE_CAPS_WOL_PORT0
- IXGBE_DEVICE_CAPS_WOL_PORT0_1
- IXGBE_DEV_ID_82598
- IXGBE_DEV_ID_82598AF_DUAL_PORT
- IXGBE_DEV_ID_82598AF_SINGLE_PORT
- IXGBE_DEV_ID_82598AT
- IXGBE_DEV_ID_82598AT2
- IXGBE_DEV_ID_82598EB_CX4
- IXGBE_DEV_ID_82598EB_SFP_LOM
- IXGBE_DEV_ID_82598EB_XF_LR
- IXGBE_DEV_ID_82598_BX
- IXGBE_DEV_ID_82598_CX4_DUAL_PORT
- IXGBE_DEV_ID_82598_DA_DUAL_PORT
- IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
- IXGBE_DEV_ID_82599EN_SFP
- IXGBE_DEV_ID_82599_BACKPLANE_FCOE
- IXGBE_DEV_ID_82599_COMBO_BACKPLANE
- IXGBE_DEV_ID_82599_CX4
- IXGBE_DEV_ID_82599_KR
- IXGBE_DEV_ID_82599_KX4
- IXGBE_DEV_ID_82599_KX4_MEZZ
- IXGBE_DEV_ID_82599_LS
- IXGBE_DEV_ID_82599_QSFP_SF_QP
- IXGBE_DEV_ID_82599_SFP
- IXGBE_DEV_ID_82599_SFP_EM
- IXGBE_DEV_ID_82599_SFP_FCOE
- IXGBE_DEV_ID_82599_SFP_SF2
- IXGBE_DEV_ID_82599_SFP_SF_QP
- IXGBE_DEV_ID_82599_T3_LOM
- IXGBE_DEV_ID_82599_VF
- IXGBE_DEV_ID_82599_VF_HV
- IXGBE_DEV_ID_82599_XAUI_LOM
- IXGBE_DEV_ID_X540T
- IXGBE_DEV_ID_X540T1
- IXGBE_DEV_ID_X540_VF
- IXGBE_DEV_ID_X540_VF_HV
- IXGBE_DEV_ID_X550EM_A_10G_T
- IXGBE_DEV_ID_X550EM_A_1G_T
- IXGBE_DEV_ID_X550EM_A_1G_T_L
- IXGBE_DEV_ID_X550EM_A_KR
- IXGBE_DEV_ID_X550EM_A_KR_L
- IXGBE_DEV_ID_X550EM_A_SFP
- IXGBE_DEV_ID_X550EM_A_SFP_N
- IXGBE_DEV_ID_X550EM_A_SGMII
- IXGBE_DEV_ID_X550EM_A_SGMII_L
- IXGBE_DEV_ID_X550EM_A_VF
- IXGBE_DEV_ID_X550EM_X_10G_T
- IXGBE_DEV_ID_X550EM_X_1G_T
- IXGBE_DEV_ID_X550EM_X_KR
- IXGBE_DEV_ID_X550EM_X_KX4
- IXGBE_DEV_ID_X550EM_X_SFP
- IXGBE_DEV_ID_X550EM_X_VF
- IXGBE_DEV_ID_X550EM_X_VF_HV
- IXGBE_DEV_ID_X550EM_X_XFI
- IXGBE_DEV_ID_X550T
- IXGBE_DEV_ID_X550T1
- IXGBE_DEV_ID_X550_VF
- IXGBE_DEV_ID_X550_VF_HV
- IXGBE_DMATXCTL
- IXGBE_DMATXCTL_GDV
- IXGBE_DMATXCTL_MBINTEN
- IXGBE_DMATXCTL_MDP_EN
- IXGBE_DMATXCTL_NS
- IXGBE_DMATXCTL_TE
- IXGBE_DMATXCTL_VT_SHIFT
- IXGBE_DPMCS
- IXGBE_DPMCS_ARBDIS
- IXGBE_DPMCS_MTSOS_SHIFT
- IXGBE_DPMCS_TDPAC
- IXGBE_DPMCS_TRM
- IXGBE_DPMCS_TSOEF
- IXGBE_DRECCCTL
- IXGBE_DRECCCTL_DISABLE
- IXGBE_DROPEN
- IXGBE_DTXCTL
- IXGBE_DTXCTL_ENDBUBD
- IXGBE_DTXMXSZRQ
- IXGBE_DTXTCPFLGH
- IXGBE_DTXTCPFLGL
- IXGBE_DV
- IXGBE_DV_X540
- IXGBE_ECC_CTRL_0_82599
- IXGBE_ECC_CTRL_1_82599
- IXGBE_ECC_STATUS_82599
- IXGBE_EEC
- IXGBE_EEC_8259X
- IXGBE_EEC_ADDR_SIZE
- IXGBE_EEC_ARD
- IXGBE_EEC_CS
- IXGBE_EEC_DI
- IXGBE_EEC_DO
- IXGBE_EEC_FLUDONE
- IXGBE_EEC_FLUP
- IXGBE_EEC_FWE_DIS
- IXGBE_EEC_FWE_EN
- IXGBE_EEC_FWE_MASK
- IXGBE_EEC_FWE_SHIFT
- IXGBE_EEC_GNT
- IXGBE_EEC_PRES
- IXGBE_EEC_REQ
- IXGBE_EEC_SEC1VAL
- IXGBE_EEC_SIZE
- IXGBE_EEC_SIZE_SHIFT
- IXGBE_EEC_SK
- IXGBE_EEC_X540
- IXGBE_EEC_X550
- IXGBE_EEC_X550EM_a
- IXGBE_EEC_X550EM_x
- IXGBE_EEMNGCTL
- IXGBE_EEMNGDATA
- IXGBE_EEPROM_A8_OPCODE_SPI
- IXGBE_EEPROM_CCD_BIT
- IXGBE_EEPROM_CHECKSUM
- IXGBE_EEPROM_CTRL_2
- IXGBE_EEPROM_CTRL_4
- IXGBE_EEPROM_ERASE256_OPCODE_SPI
- IXGBE_EEPROM_ERASE4K_OPCODE_SPI
- IXGBE_EEPROM_ERASE64K_OPCODE_SPI
- IXGBE_EEPROM_GRANT_ATTEMPTS
- IXGBE_EEPROM_LAST_WORD
- IXGBE_EEPROM_MAX_RETRY_SPI
- IXGBE_EEPROM_OPCODE_BITS
- IXGBE_EEPROM_PAGE_SIZE_MAX
- IXGBE_EEPROM_RDSR_OPCODE_SPI
- IXGBE_EEPROM_RD_BUFFER_MAX_COUNT
- IXGBE_EEPROM_READ_OPCODE_SPI
- IXGBE_EEPROM_RW_ADDR_SHIFT
- IXGBE_EEPROM_RW_REG_DATA
- IXGBE_EEPROM_RW_REG_DONE
- IXGBE_EEPROM_RW_REG_START
- IXGBE_EEPROM_STATUS_RDY_SPI
- IXGBE_EEPROM_SUM
- IXGBE_EEPROM_WORD_SIZE_SHIFT
- IXGBE_EEPROM_WRDI_OPCODE_SPI
- IXGBE_EEPROM_WREN_OPCODE_SPI
- IXGBE_EEPROM_WRITE_OPCODE_SPI
- IXGBE_EEPROM_WRSR_OPCODE_SPI
- IXGBE_EEPROM_WR_BUFFER_MAX_COUNT
- IXGBE_EERD
- IXGBE_EERD_EEWR_ATTEMPTS
- IXGBE_EERD_MAX_ADDR
- IXGBE_EEWR
- IXGBE_EE_CTRL_4_INST_ID
- IXGBE_EE_CTRL_4_INST_ID_SHIFT
- IXGBE_EIAC
- IXGBE_EIAM
- IXGBE_EIAM_EX
- IXGBE_EICR
- IXGBE_EICR_DHER
- IXGBE_EICR_ECC
- IXGBE_EICR_FLOW_DIR
- IXGBE_EICR_GPI_SDP0
- IXGBE_EICR_GPI_SDP0_8259X
- IXGBE_EICR_GPI_SDP0_X540
- IXGBE_EICR_GPI_SDP0_X550
- IXGBE_EICR_GPI_SDP0_X550EM_a
- IXGBE_EICR_GPI_SDP0_X550EM_x
- IXGBE_EICR_GPI_SDP1
- IXGBE_EICR_GPI_SDP1_8259X
- IXGBE_EICR_GPI_SDP1_X540
- IXGBE_EICR_GPI_SDP1_X550
- IXGBE_EICR_GPI_SDP1_X550EM_a
- IXGBE_EICR_GPI_SDP1_X550EM_x
- IXGBE_EICR_GPI_SDP2
- IXGBE_EICR_GPI_SDP2_8259X
- IXGBE_EICR_GPI_SDP2_X540
- IXGBE_EICR_GPI_SDP2_X550
- IXGBE_EICR_GPI_SDP2_X550EM_a
- IXGBE_EICR_GPI_SDP2_X550EM_x
- IXGBE_EICR_LINKSEC
- IXGBE_EICR_LSC
- IXGBE_EICR_MAILBOX
- IXGBE_EICR_MNG
- IXGBE_EICR_OTHER
- IXGBE_EICR_PBUR
- IXGBE_EICR_PCI
- IXGBE_EICR_RTX_QUEUE
- IXGBE_EICR_RX_MISS
- IXGBE_EICR_TCP_TIMER
- IXGBE_EICR_TIMESYNC
- IXGBE_EICR_TS
- IXGBE_EICS
- IXGBE_EICS_DHER
- IXGBE_EICS_ECC
- IXGBE_EICS_EX
- IXGBE_EICS_FLOW_DIR
- IXGBE_EICS_GPI_SDP0
- IXGBE_EICS_GPI_SDP1
- IXGBE_EICS_GPI_SDP2
- IXGBE_EICS_LSC
- IXGBE_EICS_MAILBOX
- IXGBE_EICS_MNG
- IXGBE_EICS_OTHER
- IXGBE_EICS_PBUR
- IXGBE_EICS_PCI
- IXGBE_EICS_RTX_QUEUE
- IXGBE_EICS_RX_MISS
- IXGBE_EICS_TCP_TIMER
- IXGBE_EICS_TIMESYNC
- IXGBE_EIMC
- IXGBE_EIMC_DHER
- IXGBE_EIMC_ECC
- IXGBE_EIMC_EX
- IXGBE_EIMC_FLOW_DIR
- IXGBE_EIMC_GPI_SDP0
- IXGBE_EIMC_GPI_SDP1
- IXGBE_EIMC_GPI_SDP2
- IXGBE_EIMC_LSC
- IXGBE_EIMC_MAILBOX
- IXGBE_EIMC_MNG
- IXGBE_EIMC_OTHER
- IXGBE_EIMC_PBUR
- IXGBE_EIMC_PCI
- IXGBE_EIMC_RTX_QUEUE
- IXGBE_EIMC_RX_MISS
- IXGBE_EIMC_TCP_TIMER
- IXGBE_EIMC_TIMESYNC
- IXGBE_EIMS
- IXGBE_EIMS_DHER
- IXGBE_EIMS_ECC
- IXGBE_EIMS_ENABLE_MASK
- IXGBE_EIMS_EX
- IXGBE_EIMS_FLOW_DIR
- IXGBE_EIMS_GPI_SDP0
- IXGBE_EIMS_GPI_SDP1
- IXGBE_EIMS_GPI_SDP2
- IXGBE_EIMS_LSC
- IXGBE_EIMS_MAILBOX
- IXGBE_EIMS_MNG
- IXGBE_EIMS_OTHER
- IXGBE_EIMS_PBUR
- IXGBE_EIMS_PCI
- IXGBE_EIMS_RTX_QUEUE
- IXGBE_EIMS_RX_MISS
- IXGBE_EIMS_TCP_TIMER
- IXGBE_EIMS_TIMESYNC
- IXGBE_EIMS_TS
- IXGBE_EITR
- IXGBE_EITRSEL
- IXGBE_EITR_CNT_WDIS
- IXGBE_EITR_ITR_INT_MASK
- IXGBE_EITR_LLI_MOD
- IXGBE_EMC_DIODE1_DATA
- IXGBE_EMC_DIODE1_THERM_LIMIT
- IXGBE_EMC_DIODE2_DATA
- IXGBE_EMC_DIODE2_THERM_LIMIT
- IXGBE_EMC_DIODE3_DATA
- IXGBE_EMC_DIODE3_THERM_LIMIT
- IXGBE_EMC_INTERNAL_DATA
- IXGBE_EMC_INTERNAL_THERM_LIMIT
- IXGBE_EODSDP
- IXGBE_ERETA
- IXGBE_ERRBC
- IXGBE_ERR_ADAPTER_STOPPED
- IXGBE_ERR_AUTONEG_NOT_COMPLETE
- IXGBE_ERR_CONFIG
- IXGBE_ERR_DEVICE_NOT_SUPPORTED
- IXGBE_ERR_EEPROM
- IXGBE_ERR_EEPROM_CHECKSUM
- IXGBE_ERR_EEPROM_VERSION
- IXGBE_ERR_FC_NOT_NEGOTIATED
- IXGBE_ERR_FC_NOT_SUPPORTED
- IXGBE_ERR_FDIR_CMD_INCOMPLETE
- IXGBE_ERR_FDIR_REINIT_FAILED
- IXGBE_ERR_FW_RESP_INVALID
- IXGBE_ERR_HOST_INTERFACE_COMMAND
- IXGBE_ERR_I2C
- IXGBE_ERR_INVALID_ARGUMENT
- IXGBE_ERR_INVALID_LINK_SETTINGS
- IXGBE_ERR_INVALID_MAC_ADDR
- IXGBE_ERR_LINK_SETUP
- IXGBE_ERR_MAC_TYPE
- IXGBE_ERR_MASTER_REQUESTS_PENDING
- IXGBE_ERR_MBX
- IXGBE_ERR_NO_SAN_ADDR_PTR
- IXGBE_ERR_NO_SPACE
- IXGBE_ERR_OVERTEMP
- IXGBE_ERR_PARAM
- IXGBE_ERR_PBA_SECTION
- IXGBE_ERR_PHY
- IXGBE_ERR_PHY_ADDR_INVALID
- IXGBE_ERR_RESET_FAILED
- IXGBE_ERR_SFP_NOT_PRESENT
- IXGBE_ERR_SFP_NOT_SUPPORTED
- IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT
- IXGBE_ERR_SFP_SETUP_NOT_COMPLETE
- IXGBE_ERR_SWFW_SYNC
- IXGBE_ERR_TOKEN_RETRY
- IXGBE_ERR_UNKNOWN_PHY
- IXGBE_ESDP
- IXGBE_ESDP_SDP0
- IXGBE_ESDP_SDP0_DIR
- IXGBE_ESDP_SDP0_NATIVE
- IXGBE_ESDP_SDP1
- IXGBE_ESDP_SDP1_DIR
- IXGBE_ESDP_SDP1_NATIVE
- IXGBE_ESDP_SDP2
- IXGBE_ESDP_SDP3
- IXGBE_ESDP_SDP4
- IXGBE_ESDP_SDP4_DIR
- IXGBE_ESDP_SDP5
- IXGBE_ESDP_SDP5_DIR
- IXGBE_ESDP_SDP6
- IXGBE_ESP_FEATURES
- IXGBE_ETHERNET_IEEE_VLAN_TYPE
- IXGBE_ETH_FRAMING
- IXGBE_ETQF
- IXGBE_ETQF_1588
- IXGBE_ETQF_BCN
- IXGBE_ETQF_FCOE
- IXGBE_ETQF_FILTER_1588
- IXGBE_ETQF_FILTER_EAPOL
- IXGBE_ETQF_FILTER_EN
- IXGBE_ETQF_FILTER_FC
- IXGBE_ETQF_FILTER_FCOE
- IXGBE_ETQF_FILTER_FIP
- IXGBE_ETQF_FILTER_LACP
- IXGBE_ETQF_FILTER_LLDP
- IXGBE_ETQF_POOL_ENABLE
- IXGBE_ETQF_POOL_SHIFT
- IXGBE_ETQF_TX_ANTISPOOF
- IXGBE_ETQS
- IXGBE_ETQS_LLI
- IXGBE_ETQS_QUEUE_EN
- IXGBE_ETQS_RX_QUEUE
- IXGBE_ETQS_RX_QUEUE_SHIFT
- IXGBE_ETS_CFG
- IXGBE_ETS_DATA_HTHRESH_MASK
- IXGBE_ETS_DATA_INDEX_MASK
- IXGBE_ETS_DATA_INDEX_SHIFT
- IXGBE_ETS_DATA_LOC_MASK
- IXGBE_ETS_DATA_LOC_SHIFT
- IXGBE_ETS_LTHRES_DELTA_MASK
- IXGBE_ETS_LTHRES_DELTA_SHIFT
- IXGBE_ETS_NUM_SENSORS_MASK
- IXGBE_ETS_TYPE_EMC
- IXGBE_ETS_TYPE_EMC_SHIFTED
- IXGBE_ETS_TYPE_MASK
- IXGBE_ETS_TYPE_SHIFT
- IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX
- IXGBE_EXVET
- IXGBE_FACTPS
- IXGBE_FACTPS_8259X
- IXGBE_FACTPS_LFS
- IXGBE_FACTPS_MNGCG
- IXGBE_FACTPS_X540
- IXGBE_FACTPS_X550
- IXGBE_FACTPS_X550EM_a
- IXGBE_FACTPS_X550EM_x
- IXGBE_FAILED_READ_CFG_DWORD
- IXGBE_FAILED_READ_CFG_WORD
- IXGBE_FAILED_READ_REG
- IXGBE_FAILED_READ_RETRIES
- IXGBE_FCADBUH
- IXGBE_FCADBUL
- IXGBE_FCAMACH
- IXGBE_FCAMACL
- IXGBE_FCBUFF
- IXGBE_FCBUFF_16KB
- IXGBE_FCBUFF_4KB
- IXGBE_FCBUFF_64KB
- IXGBE_FCBUFF_8KB
- IXGBE_FCBUFF_BUFFCNT
- IXGBE_FCBUFF_BUFFCNT_SHIFT
- IXGBE_FCBUFF_BUFFSIZE
- IXGBE_FCBUFF_BUFFSIZE_SHIFT
- IXGBE_FCBUFF_MAX
- IXGBE_FCBUFF_MIN
- IXGBE_FCBUFF_OFFSET
- IXGBE_FCBUFF_OFFSET_SHIFT
- IXGBE_FCBUFF_VALID
- IXGBE_FCBUFF_WRCONTX
- IXGBE_FCCFG
- IXGBE_FCCFG_TFCE_802_3X
- IXGBE_FCCFG_TFCE_PRIORITY
- IXGBE_FCCRC
- IXGBE_FCDDC
- IXGBE_FCDFC
- IXGBE_FCDFCD
- IXGBE_FCDMARW
- IXGBE_FCDMARW_FCOESEL
- IXGBE_FCDMARW_LASTSIZE
- IXGBE_FCDMARW_LASTSIZE_SHIFT
- IXGBE_FCDMARW_RE
- IXGBE_FCDMARW_WE
- IXGBE_FCERR_BADCRC
- IXGBE_FCFLT
- IXGBE_FCFLTRW
- IXGBE_FCFLTRW_RE
- IXGBE_FCFLTRW_RVALDT
- IXGBE_FCFLTRW_WE
- IXGBE_FCFLT_FIRST
- IXGBE_FCFLT_SEQCNT
- IXGBE_FCFLT_SEQID
- IXGBE_FCFLT_VALID
- IXGBE_FCINVST
- IXGBE_FCINVST0
- IXGBE_FCLAST
- IXGBE_FCOE
- IXGBE_FCOEDWRC
- IXGBE_FCOEDWTC
- IXGBE_FCOEPRC
- IXGBE_FCOEPTC
- IXGBE_FCOERPDC
- IXGBE_FCOE_DDP_MAX
- IXGBE_FCOE_DDP_MAX_X550
- IXGBE_FCOE_DEFTC
- IXGBE_FCOE_IBA_CAPS_BLK_PTR
- IXGBE_FCOE_IBA_CAPS_FCOE
- IXGBE_FCOE_JUMBO_FRAME_SIZE
- IXGBE_FCPARAM
- IXGBE_FCPTRH
- IXGBE_FCPTRL
- IXGBE_FCPTR_ALIGN
- IXGBE_FCPTR_MAX
- IXGBE_FCRECTL
- IXGBE_FCRECTL_ENA
- IXGBE_FCRETA
- IXGBE_FCRETA0
- IXGBE_FCRETA_ENTRY_HIGH_MASK
- IXGBE_FCRETA_ENTRY_HIGH_SHIFT
- IXGBE_FCRETA_ENTRY_MASK
- IXGBE_FCRETA_SIZE
- IXGBE_FCRETA_SIZE_X550
- IXGBE_FCRTH
- IXGBE_FCRTH_82599
- IXGBE_FCRTH_FCEN
- IXGBE_FCRTL
- IXGBE_FCRTL_82599
- IXGBE_FCRTL_XONE
- IXGBE_FCRTV
- IXGBE_FCRXCTRL
- IXGBE_FCRXCTRL_ALLH
- IXGBE_FCRXCTRL_FCCRCBO
- IXGBE_FCRXCTRL_FCOELLI
- IXGBE_FCRXCTRL_FCOEVER
- IXGBE_FCRXCTRL_FCOEVER_SHIFT
- IXGBE_FCRXCTRL_FRSTRDH
- IXGBE_FCRXCTRL_FRSTSEQH
- IXGBE_FCRXCTRL_ICRC
- IXGBE_FCRXCTRL_LASTSEQH
- IXGBE_FCRXCTRL_SAVBAD
- IXGBE_FCTRL
- IXGBE_FCTRL_BAM
- IXGBE_FCTRL_DPF
- IXGBE_FCTRL_MPE
- IXGBE_FCTRL_PMCF
- IXGBE_FCTRL_RFCE
- IXGBE_FCTRL_RPFCE
- IXGBE_FCTRL_SBP
- IXGBE_FCTRL_UPE
- IXGBE_FCTTV
- IXGBE_FDIRCMD
- IXGBE_FDIRCMD_CLEARHT
- IXGBE_FDIRCMD_CMD_ADD_FLOW
- IXGBE_FDIRCMD_CMD_MASK
- IXGBE_FDIRCMD_CMD_POLL
- IXGBE_FDIRCMD_CMD_QUERY_REM_FILT
- IXGBE_FDIRCMD_CMD_REMOVE_FLOW
- IXGBE_FDIRCMD_COLLISION
- IXGBE_FDIRCMD_DROP
- IXGBE_FDIRCMD_FILTER_UPDATE
- IXGBE_FDIRCMD_FILTER_VALID
- IXGBE_FDIRCMD_FLOW_TYPE_SHIFT
- IXGBE_FDIRCMD_INT
- IXGBE_FDIRCMD_IPV6
- IXGBE_FDIRCMD_IPv6DMATCH
- IXGBE_FDIRCMD_L4TYPE_SCTP
- IXGBE_FDIRCMD_L4TYPE_TCP
- IXGBE_FDIRCMD_L4TYPE_UDP
- IXGBE_FDIRCMD_LAST
- IXGBE_FDIRCMD_QUEUE_EN
- IXGBE_FDIRCMD_RX_QUEUE_SHIFT
- IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT
- IXGBE_FDIRCMD_TUNNEL_FILTER
- IXGBE_FDIRCMD_VT_POOL_SHIFT
- IXGBE_FDIRCTRL
- IXGBE_FDIRCTRL_DROP_NO_MATCH
- IXGBE_FDIRCTRL_DROP_Q_SHIFT
- IXGBE_FDIRCTRL_FILTERMODE_CLOUD
- IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
- IXGBE_FDIRCTRL_FILTERMODE_SHIFT
- IXGBE_FDIRCTRL_FLEX_SHIFT
- IXGBE_FDIRCTRL_FULL_THRESH_MASK
- IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
- IXGBE_FDIRCTRL_INIT_DONE
- IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
- IXGBE_FDIRCTRL_PBALLOC_128K
- IXGBE_FDIRCTRL_PBALLOC_256K
- IXGBE_FDIRCTRL_PBALLOC_64K
- IXGBE_FDIRCTRL_PERFECT_MATCH
- IXGBE_FDIRCTRL_REPORT_STATUS
- IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS
- IXGBE_FDIRCTRL_SEARCHLIM
- IXGBE_FDIRDIP4M
- IXGBE_FDIRFREE
- IXGBE_FDIRFREE_COLL_MASK
- IXGBE_FDIRFREE_COLL_SHIFT
- IXGBE_FDIRFREE_FREE_MASK
- IXGBE_FDIRFREE_FREE_SHIFT
- IXGBE_FDIRFSTAT
- IXGBE_FDIRFSTAT_FADD_MASK
- IXGBE_FDIRFSTAT_FADD_SHIFT
- IXGBE_FDIRFSTAT_FREMOVE_MASK
- IXGBE_FDIRFSTAT_FREMOVE_SHIFT
- IXGBE_FDIRHASH
- IXGBE_FDIRHASH_BUCKET_VALID_SHIFT
- IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
- IXGBE_FDIRHKEY
- IXGBE_FDIRIP6M
- IXGBE_FDIRIP6M_DIPM_SHIFT
- IXGBE_FDIRIPDA
- IXGBE_FDIRIPSA
- IXGBE_FDIRLEN
- IXGBE_FDIRLEN_MAXHASH_MASK
- IXGBE_FDIRLEN_MAXHASH_SHIFT
- IXGBE_FDIRLEN_MAXLEN_MASK
- IXGBE_FDIRLEN_MAXLEN_SHIFT
- IXGBE_FDIRM
- IXGBE_FDIRMATCH
- IXGBE_FDIRMISS
- IXGBE_FDIRM_DIPv6
- IXGBE_FDIRM_FLEX
- IXGBE_FDIRM_L4P
- IXGBE_FDIRM_POOL
- IXGBE_FDIRM_VLANID
- IXGBE_FDIRM_VLANP
- IXGBE_FDIRPORT
- IXGBE_FDIRPORT_DESTINATION_SHIFT
- IXGBE_FDIRSCTPM
- IXGBE_FDIRSIP4M
- IXGBE_FDIRSIPv6
- IXGBE_FDIRSKEY
- IXGBE_FDIRTCPM
- IXGBE_FDIRTCPM_DPORTM_SHIFT
- IXGBE_FDIRUDPM
- IXGBE_FDIRUDPM_DPORTM_SHIFT
- IXGBE_FDIRUSTAT
- IXGBE_FDIRUSTAT_ADD_MASK
- IXGBE_FDIRUSTAT_ADD_SHIFT
- IXGBE_FDIRUSTAT_REMOVE_MASK
- IXGBE_FDIRUSTAT_REMOVE_SHIFT
- IXGBE_FDIRVLAN
- IXGBE_FDIRVLAN_FLEX_SHIFT
- IXGBE_FDIR_DROP_QUEUE
- IXGBE_FDIR_INIT_DONE_POLL
- IXGBE_FDIR_PBALLOC_128K
- IXGBE_FDIR_PBALLOC_256K
- IXGBE_FDIR_PBALLOC_64K
- IXGBE_FDIR_PBALLOC_NONE
- IXGBE_FDIR_PBALLOC_SIZE_SHIFT
- IXGBE_FECS1
- IXGBE_FECS2
- IXGBE_FHFT
- IXGBE_FHFT_EXT
- IXGBE_FHFT_LENGTH_MASK
- IXGBE_FHFT_LENGTH_OFFSET
- IXGBE_FLA
- IXGBE_FLAG2_EEE_CAPABLE
- IXGBE_FLAG2_EEE_ENABLED
- IXGBE_FLAG2_FDIR_REQUIRES_REINIT
- IXGBE_FLAG2_IPSEC_ENABLED
- IXGBE_FLAG2_PHY_INTERRUPT
- IXGBE_FLAG2_PTP_PPS_ENABLED
- IXGBE_FLAG2_RSC_CAPABLE
- IXGBE_FLAG2_RSC_ENABLED
- IXGBE_FLAG2_RSS_FIELD_IPV4_UDP
- IXGBE_FLAG2_RSS_FIELD_IPV6_UDP
- IXGBE_FLAG2_RX_LEGACY
- IXGBE_FLAG2_SEARCH_FOR_SFP
- IXGBE_FLAG2_SFP_NEEDS_RESET
- IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
- IXGBE_FLAG2_TEMP_SENSOR_EVENT
- IXGBE_FLAG2_UDP_TUN_REREG_NEEDED
- IXGBE_FLAG2_VF_IPSEC_ENABLED
- IXGBE_FLAG2_VLAN_PROMISC
- IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
- IXGBE_FLAG_DCA_CAPABLE
- IXGBE_FLAG_DCA_ENABLED
- IXGBE_FLAG_DCB_CAPABLE
- IXGBE_FLAG_DCB_ENABLED
- IXGBE_FLAG_FAN_FAIL_CAPABLE
- IXGBE_FLAG_FCOE_CAPABLE
- IXGBE_FLAG_FCOE_ENABLED
- IXGBE_FLAG_FDIR_HASH_CAPABLE
- IXGBE_FLAG_FDIR_PERFECT_CAPABLE
- IXGBE_FLAG_GENEVE_OFFLOAD_CAPABLE
- IXGBE_FLAG_IMIR_ENABLED
- IXGBE_FLAG_MQ_CAPABLE
- IXGBE_FLAG_MSIX_ENABLED
- IXGBE_FLAG_MSI_ENABLED
- IXGBE_FLAG_NEED_LINK_CONFIG
- IXGBE_FLAG_NEED_LINK_UPDATE
- IXGBE_FLAG_RX_1BUF_CAPABLE
- IXGBE_FLAG_RX_HWTSTAMP_ENABLED
- IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER
- IXGBE_FLAG_RX_PS_CAPABLE
- IXGBE_FLAG_RX_PS_ENABLED
- IXGBE_FLAG_SRIOV_CAPABLE
- IXGBE_FLAG_SRIOV_ENABLED
- IXGBE_FLAG_VMDQ_CAPABLE
- IXGBE_FLAG_VMDQ_ENABLED
- IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE
- IXGBE_FLA_8259X
- IXGBE_FLA_X540
- IXGBE_FLA_X550
- IXGBE_FLA_X550EM_a
- IXGBE_FLA_X550EM_x
- IXGBE_FLEXIBLE_FILTER_COUNT_MAX
- IXGBE_FLEXIBLE_FILTER_SIZE_MAX
- IXGBE_FLEX_MNG
- IXGBE_FLMNGCNT
- IXGBE_FLMNGCTL
- IXGBE_FLMNGDATA
- IXGBE_FLOP
- IXGBE_FLUDONE_ATTEMPTS
- IXGBE_FREE_SPACE_PTR
- IXGBE_FREQOUT0
- IXGBE_FREQOUT1
- IXGBE_FRTIMER
- IXGBE_FTFT
- IXGBE_FTQF
- IXGBE_FTQF_5TUPLE_MASK_MASK
- IXGBE_FTQF_5TUPLE_MASK_SHIFT
- IXGBE_FTQF_DEST_ADDR_MASK
- IXGBE_FTQF_DEST_PORT_MASK
- IXGBE_FTQF_POOL_MASK
- IXGBE_FTQF_POOL_MASK_EN
- IXGBE_FTQF_POOL_SHIFT
- IXGBE_FTQF_PRIORITY_MASK
- IXGBE_FTQF_PRIORITY_SHIFT
- IXGBE_FTQF_PROTOCOL_COMP_MASK
- IXGBE_FTQF_PROTOCOL_MASK
- IXGBE_FTQF_PROTOCOL_SCTP
- IXGBE_FTQF_PROTOCOL_TCP
- IXGBE_FTQF_PROTOCOL_UDP
- IXGBE_FTQF_QUEUE_ENABLE
- IXGBE_FTQF_SOURCE_ADDR_MASK
- IXGBE_FTQF_SOURCE_PORT_MASK
- IXGBE_FUNCTAG
- IXGBE_FUSES0_300MHZ
- IXGBE_FUSES0_GROUP
- IXGBE_FUSES0_REV_MASK
- IXGBE_FWSM
- IXGBE_FWSM_8259X
- IXGBE_FWSM_EXT_ERR_IND_MASK
- IXGBE_FWSM_FW_MODE_PT
- IXGBE_FWSM_FW_NVM_RECOVERY_MODE
- IXGBE_FWSM_FW_VAL_BIT
- IXGBE_FWSM_MODE_MASK
- IXGBE_FWSM_TS_ENABLED
- IXGBE_FWSM_X540
- IXGBE_FWSM_X550
- IXGBE_FWSM_X550EM_a
- IXGBE_FWSM_X550EM_x
- IXGBE_FWSTS
- IXGBE_FWSTS_FWRI
- IXGBE_FW_LESM_PARAMETERS_PTR
- IXGBE_FW_LESM_STATE_1
- IXGBE_FW_LESM_STATE_ENABLED
- IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
- IXGBE_FW_PATCH_VERSION_4
- IXGBE_FW_PTR
- IXGBE_GCR
- IXGBE_GCR_CAP_VER2
- IXGBE_GCR_CMPL_TMOUT_10ms
- IXGBE_GCR_CMPL_TMOUT_MASK
- IXGBE_GCR_CMPL_TMOUT_RESEND
- IXGBE_GCR_EXT
- IXGBE_GCR_EXT_BUFFERS_CLEAR
- IXGBE_GCR_EXT_MSIX_EN
- IXGBE_GCR_EXT_SRIOV
- IXGBE_GCR_EXT_VT_MODE_16
- IXGBE_GCR_EXT_VT_MODE_32
- IXGBE_GCR_EXT_VT_MODE_64
- IXGBE_GET_STAT
- IXGBE_GHECCR
- IXGBE_GLOBAL_STATS_LEN
- IXGBE_GLT
- IXGBE_GORCH
- IXGBE_GORCL
- IXGBE_GOTCH
- IXGBE_GOTCL
- IXGBE_GPIE
- IXGBE_GPIE_EIAME
- IXGBE_GPIE_EIMEN
- IXGBE_GPIE_MSIX_MODE
- IXGBE_GPIE_OCD
- IXGBE_GPIE_PBA_SUPPORT
- IXGBE_GPIE_RSC_DELAY_SHIFT
- IXGBE_GPIE_VTMODE_16
- IXGBE_GPIE_VTMODE_32
- IXGBE_GPIE_VTMODE_64
- IXGBE_GPIE_VTMODE_MASK
- IXGBE_GPRC
- IXGBE_GPTC
- IXGBE_GRC
- IXGBE_GRC_8259X
- IXGBE_GRC_APME
- IXGBE_GRC_MNG
- IXGBE_GRC_X540
- IXGBE_GRC_X550
- IXGBE_GRC_X550EM_a
- IXGBE_GRC_X550EM_x
- IXGBE_GSCL_1
- IXGBE_GSCL_2
- IXGBE_GSCL_3
- IXGBE_GSCL_4
- IXGBE_GSCL_5_82599
- IXGBE_GSCL_6_82599
- IXGBE_GSCL_7_82599
- IXGBE_GSCL_8_82599
- IXGBE_GSCN_0
- IXGBE_GSCN_1
- IXGBE_GSCN_2
- IXGBE_GSCN_3
- IXGBE_GSO_PARTIAL_FEATURES
- IXGBE_GSSR
- IXGBE_GSSR_EEP_SM
- IXGBE_GSSR_FLASH_SM
- IXGBE_GSSR_I2C_MASK
- IXGBE_GSSR_MAC_CSR_SM
- IXGBE_GSSR_NVM_PHY_MASK
- IXGBE_GSSR_NVM_UPDATE_SM
- IXGBE_GSSR_PHY0_SM
- IXGBE_GSSR_PHY1_SM
- IXGBE_GSSR_SHARED_I2C_SM
- IXGBE_GSSR_SW_MNG_SM
- IXGBE_GSSR_TOKEN_SM
- IXGBE_GTV
- IXGBE_HD
- IXGBE_HFDR
- IXGBE_HICR
- IXGBE_HICR_C
- IXGBE_HICR_EN
- IXGBE_HICR_FW_RESET
- IXGBE_HICR_FW_RESET_ENABLE
- IXGBE_HICR_SV
- IXGBE_HI_COMMAND_TIMEOUT
- IXGBE_HI_FLASH_APPLY_TIMEOUT
- IXGBE_HI_FLASH_ERASE_TIMEOUT
- IXGBE_HI_FLASH_UPDATE_TIMEOUT
- IXGBE_HI_MAX_BLOCK_BYTE_LENGTH
- IXGBE_HI_MAX_BLOCK_DWORD_LENGTH
- IXGBE_HLREG0
- IXGBE_HLREG0_CONTMDC
- IXGBE_HLREG0_CTRLFLTR
- IXGBE_HLREG0_JUMBOEN
- IXGBE_HLREG0_LPBK
- IXGBE_HLREG0_MDCSPD
- IXGBE_HLREG0_PREPEND
- IXGBE_HLREG0_PRIPAUSEEN
- IXGBE_HLREG0_RXCRCSTRP
- IXGBE_HLREG0_RXLNGTHERREN
- IXGBE_HLREG0_RXPADSTRIPEN
- IXGBE_HLREG0_RXPAUSEEN
- IXGBE_HLREG0_RXPAUSERECDA
- IXGBE_HLREG0_TXCRCEN
- IXGBE_HLREG0_TXPADEN
- IXGBE_HLREG0_TXPAUSEEN
- IXGBE_HLREG1
- IXGBE_HSMC0R
- IXGBE_HSMC1R
- IXGBE_HV_RESET_OFFSET
- IXGBE_HWMON_TYPE_CAUTION
- IXGBE_HWMON_TYPE_LOC
- IXGBE_HWMON_TYPE_MAX
- IXGBE_HWMON_TYPE_TEMP
- IXGBE_HW_READ_REG
- IXGBE_I2CCTL
- IXGBE_I2CCTL_8259X
- IXGBE_I2CCTL_X540
- IXGBE_I2CCTL_X550
- IXGBE_I2CCTL_X550EM_a
- IXGBE_I2CCTL_X550EM_x
- IXGBE_I2C_BB_EN
- IXGBE_I2C_BB_EN_8259X
- IXGBE_I2C_BB_EN_X540
- IXGBE_I2C_BB_EN_X550
- IXGBE_I2C_BB_EN_X550EM_a
- IXGBE_I2C_BB_EN_X550EM_x
- IXGBE_I2C_CLK_IN
- IXGBE_I2C_CLK_IN_8259X
- IXGBE_I2C_CLK_IN_X540
- IXGBE_I2C_CLK_IN_X550
- IXGBE_I2C_CLK_IN_X550EM_a
- IXGBE_I2C_CLK_IN_X550EM_x
- IXGBE_I2C_CLK_OE_N_EN
- IXGBE_I2C_CLK_OE_N_EN_8259X
- IXGBE_I2C_CLK_OE_N_EN_X540
- IXGBE_I2C_CLK_OE_N_EN_X550
- IXGBE_I2C_CLK_OE_N_EN_X550EM_a
- IXGBE_I2C_CLK_OE_N_EN_X550EM_x
- IXGBE_I2C_CLK_OUT
- IXGBE_I2C_CLK_OUT_8259X
- IXGBE_I2C_CLK_OUT_X540
- IXGBE_I2C_CLK_OUT_X550
- IXGBE_I2C_CLK_OUT_X550EM_a
- IXGBE_I2C_CLK_OUT_X550EM_x
- IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT
- IXGBE_I2C_DATA_IN
- IXGBE_I2C_DATA_IN_8259X
- IXGBE_I2C_DATA_IN_X540
- IXGBE_I2C_DATA_IN_X550
- IXGBE_I2C_DATA_IN_X550EM_a
- IXGBE_I2C_DATA_IN_X550EM_x
- IXGBE_I2C_DATA_OE_N_EN
- IXGBE_I2C_DATA_OE_N_EN_8259X
- IXGBE_I2C_DATA_OE_N_EN_X540
- IXGBE_I2C_DATA_OE_N_EN_X550
- IXGBE_I2C_DATA_OE_N_EN_X550EM_a
- IXGBE_I2C_DATA_OE_N_EN_X550EM_x
- IXGBE_I2C_DATA_OUT
- IXGBE_I2C_DATA_OUT_8259X
- IXGBE_I2C_DATA_OUT_X540
- IXGBE_I2C_DATA_OUT_X550
- IXGBE_I2C_DATA_OUT_X550EM_a
- IXGBE_I2C_DATA_OUT_X550EM_x
- IXGBE_I2C_EEPROM_DEV_ADDR
- IXGBE_I2C_EEPROM_DEV_ADDR2
- IXGBE_I2C_EEPROM_READ_MASK
- IXGBE_I2C_EEPROM_STATUS_FAIL
- IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS
- IXGBE_I2C_EEPROM_STATUS_MASK
- IXGBE_I2C_EEPROM_STATUS_NO_OPERATION
- IXGBE_I2C_EEPROM_STATUS_PASS
- IXGBE_I2C_THERMAL_SENSOR_ADDR
- IXGBE_I2C_T_BUF
- IXGBE_I2C_T_FALL
- IXGBE_I2C_T_HD_DATA
- IXGBE_I2C_T_HD_STA
- IXGBE_I2C_T_HIGH
- IXGBE_I2C_T_LOW
- IXGBE_I2C_T_RISE
- IXGBE_I2C_T_SU_DATA
- IXGBE_I2C_T_SU_STA
- IXGBE_I2C_T_SU_STO
- IXGBE_ID
- IXGBE_ID_X540
- IXGBE_ILLERRC
- IXGBE_IMIR
- IXGBE_IMIREXT
- IXGBE_IMIREXT_CTRL_ACK
- IXGBE_IMIREXT_CTRL_BP
- IXGBE_IMIREXT_CTRL_FIN
- IXGBE_IMIREXT_CTRL_PSH
- IXGBE_IMIREXT_CTRL_RST
- IXGBE_IMIREXT_CTRL_SYN
- IXGBE_IMIREXT_CTRL_URG
- IXGBE_IMIREXT_SIZE_BP
- IXGBE_IMIRVP
- IXGBE_IMIRVP_PRIORITY_EN
- IXGBE_IMIRVP_PRIORITY_MASK
- IXGBE_IMIR_CTRL_ACK_82599
- IXGBE_IMIR_CTRL_BP_82599
- IXGBE_IMIR_CTRL_FIN_82599
- IXGBE_IMIR_CTRL_PSH_82599
- IXGBE_IMIR_CTRL_RST_82599
- IXGBE_IMIR_CTRL_SYN_82599
- IXGBE_IMIR_CTRL_URG_82599
- IXGBE_IMIR_LLI_EN_82599
- IXGBE_IMIR_PORT_BP
- IXGBE_IMIR_PORT_IM_EN
- IXGBE_IMIR_RX_QUEUE_MASK_82599
- IXGBE_IMIR_RX_QUEUE_SHIFT_82599
- IXGBE_IMIR_SIZE_BP_82599
- IXGBE_INCPER_SHIFT_82599
- IXGBE_INCVAL_100
- IXGBE_INCVAL_10GB
- IXGBE_INCVAL_1GB
- IXGBE_INCVAL_SHIFT_100
- IXGBE_INCVAL_SHIFT_10GB
- IXGBE_INCVAL_SHIFT_1GB
- IXGBE_INCVAL_SHIFT_82599
- IXGBE_IP4AT
- IXGBE_IP6AT
- IXGBE_IPAV
- IXGBE_IPSEC_AUTH_BITS
- IXGBE_IPSEC_BASE_RX_INDEX
- IXGBE_IPSEC_BASE_TX_INDEX
- IXGBE_IPSEC_KEY_BITS
- IXGBE_IPSEC_MAX_RX_IP_COUNT
- IXGBE_IPSEC_MAX_SA_COUNT
- IXGBE_IPSRXIDX
- IXGBE_IPSRXIPADDR
- IXGBE_IPSRXIPIDX
- IXGBE_IPSRXKEY
- IXGBE_IPSRXMOD
- IXGBE_IPSRXSALT
- IXGBE_IPSRXSPI
- IXGBE_IPSTXIDX
- IXGBE_IPSTXKEY
- IXGBE_IPSTXSALT
- IXGBE_IRQ_CLEAR_MASK
- IXGBE_ISCSI_BOOT_CAPS
- IXGBE_ISCSI_FCOE_BLK_PTR
- IXGBE_ISCSI_FCOE_FLAGS_ENABLE
- IXGBE_ISCSI_FCOE_FLAGS_OFFSET
- IXGBE_ISCSI_SETUP_PORT_0
- IXGBE_ISCSI_SETUP_PORT_1
- IXGBE_ITR_ADAPTIVE_BULK
- IXGBE_ITR_ADAPTIVE_LATENCY
- IXGBE_ITR_ADAPTIVE_MAX_USECS
- IXGBE_ITR_ADAPTIVE_MIN_INC
- IXGBE_ITR_ADAPTIVE_MIN_USECS
- IXGBE_IVAR
- IXGBE_IVAR_ALLOC_VAL
- IXGBE_IVAR_MISC
- IXGBE_IVAR_OTHER_CAUSES_INDEX
- IXGBE_IVAR_REG_NUM
- IXGBE_IVAR_REG_NUM_82599
- IXGBE_IVAR_RX_ENTRY
- IXGBE_IVAR_RX_QUEUE
- IXGBE_IVAR_TCP_TIMER_INDEX
- IXGBE_IVAR_TXRX_ENTRY
- IXGBE_IVAR_TX_ENTRY
- IXGBE_IVAR_TX_QUEUE
- IXGBE_IXGBE_PCIE_GENERAL_SIZE
- IXGBE_JUMBO_FRAME_ENABLE
- IXGBE_KRM_AN_CNTL_1
- IXGBE_KRM_AN_CNTL_1_ASM_PAUSE
- IXGBE_KRM_AN_CNTL_1_SYM_PAUSE
- IXGBE_KRM_AN_CNTL_8
- IXGBE_KRM_AN_CNTL_8_LIMITING
- IXGBE_KRM_AN_CNTL_8_LINEAR
- IXGBE_KRM_DSP_TXFFE_STATE_4
- IXGBE_KRM_DSP_TXFFE_STATE_5
- IXGBE_KRM_DSP_TXFFE_STATE_C0_EN
- IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN
- IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN
- IXGBE_KRM_LINK_CTRL_1
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
- IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN
- IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR
- IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX
- IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G
- IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G
- IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK
- IXGBE_KRM_LINK_S1
- IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE
- IXGBE_KRM_LP_BASE_PAGE_HIGH
- IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE
- IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE
- IXGBE_KRM_PMD_DFX_BURNIN
- IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK
- IXGBE_KRM_PMD_FLX_MASK_ST20
- IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN
- IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN
- IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART
- IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA
- IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR
- IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR
- IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN
- IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK
- IXGBE_KRM_PORT_CAR_GEN_CTRL
- IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B
- IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS
- IXGBE_KRM_RX_ANA_CTL
- IXGBE_KRM_RX_TRN_LINKUP_CTRL
- IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL
- IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS
- IXGBE_KRM_SGMII_CTRL
- IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D
- IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D
- IXGBE_KRM_TX_COEFF_CTRL_1
- IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN
- IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN
- IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN
- IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN
- IXGBE_KRPCSFC
- IXGBE_KRPCSS
- IXGBE_L34T_IMIR
- IXGBE_LAST_OFFSET
- IXGBE_LBDRPEN
- IXGBE_LDPCECH
- IXGBE_LDPCECL
- IXGBE_LEDCTL
- IXGBE_LED_BLINK
- IXGBE_LED_BLINK_BASE
- IXGBE_LED_FILTER
- IXGBE_LED_IVRT
- IXGBE_LED_IVRT_BASE
- IXGBE_LED_LINK_10G
- IXGBE_LED_LINK_1G
- IXGBE_LED_LINK_ACTIVE
- IXGBE_LED_LINK_UP
- IXGBE_LED_MAC
- IXGBE_LED_MODE_MASK
- IXGBE_LED_MODE_MASK_BASE
- IXGBE_LED_MODE_SHIFT
- IXGBE_LED_OFF
- IXGBE_LED_OFFSET
- IXGBE_LED_ON
- IXGBE_LINKS
- IXGBE_LINKS2
- IXGBE_LINKS2_AN_SUPPORTED
- IXGBE_LINKS_10G_ALIGN
- IXGBE_LINKS_10G_LANE_SYNC
- IXGBE_LINKS_1G_AN_EN
- IXGBE_LINKS_1G_SYNC
- IXGBE_LINKS_KX_AN_COMP
- IXGBE_LINKS_KX_AN_IDLE
- IXGBE_LINKS_MODE
- IXGBE_LINKS_PCS_1G_EN
- IXGBE_LINKS_RX_MODE
- IXGBE_LINKS_SGMII_EN
- IXGBE_LINKS_SIGNAL
- IXGBE_LINKS_SPEED
- IXGBE_LINKS_SPEED_100_82599
- IXGBE_LINKS_SPEED_10G_82599
- IXGBE_LINKS_SPEED_10_X550EM_A
- IXGBE_LINKS_SPEED_1G_82599
- IXGBE_LINKS_SPEED_82599
- IXGBE_LINKS_SPEED_NON_STD
- IXGBE_LINKS_TL_FAULT
- IXGBE_LINKS_TX_MODE
- IXGBE_LINKS_UP
- IXGBE_LINKS_XGXS_EN
- IXGBE_LINK_SPEED_100_FULL
- IXGBE_LINK_SPEED_10GB_FULL
- IXGBE_LINK_SPEED_10_FULL
- IXGBE_LINK_SPEED_1GB_FULL
- IXGBE_LINK_SPEED_2_5GB_FULL
- IXGBE_LINK_SPEED_5GB_FULL
- IXGBE_LINK_SPEED_82598_AUTONEG
- IXGBE_LINK_SPEED_82599_AUTONEG
- IXGBE_LINK_SPEED_UNKNOWN
- IXGBE_LINK_UP_TIME
- IXGBE_LLITHRESH
- IXGBE_LOW_DV
- IXGBE_LOW_DV_X540
- IXGBE_LSECRXBAD
- IXGBE_LSECRXCAP
- IXGBE_LSECRXCAP_SUM_MASK
- IXGBE_LSECRXCAP_SUM_SHIFT
- IXGBE_LSECRXCTRL
- IXGBE_LSECRXCTRL_CHECK
- IXGBE_LSECRXCTRL_DISABLE
- IXGBE_LSECRXCTRL_DROP
- IXGBE_LSECRXCTRL_EN_MASK
- IXGBE_LSECRXCTRL_EN_SHIFT
- IXGBE_LSECRXCTRL_PLSH
- IXGBE_LSECRXCTRL_RP
- IXGBE_LSECRXCTRL_RSV_MASK
- IXGBE_LSECRXCTRL_STRICT
- IXGBE_LSECRXDELAY
- IXGBE_LSECRXINV
- IXGBE_LSECRXKEY
- IXGBE_LSECRXLATE
- IXGBE_LSECRXNOSCI
- IXGBE_LSECRXNUSA
- IXGBE_LSECRXNV
- IXGBE_LSECRXOCTD
- IXGBE_LSECRXOCTV
- IXGBE_LSECRXOK
- IXGBE_LSECRXPN
- IXGBE_LSECRXSA
- IXGBE_LSECRXSCH
- IXGBE_LSECRXSCL
- IXGBE_LSECRXUNCH
- IXGBE_LSECRXUNSA
- IXGBE_LSECRXUNSCI
- IXGBE_LSECRXUT
- IXGBE_LSECTXCAP
- IXGBE_LSECTXCAP_SUM_MASK
- IXGBE_LSECTXCAP_SUM_SHIFT
- IXGBE_LSECTXCTRL
- IXGBE_LSECTXCTRL_AISCI
- IXGBE_LSECTXCTRL_AUTH
- IXGBE_LSECTXCTRL_AUTH_ENCRYPT
- IXGBE_LSECTXCTRL_DISABLE
- IXGBE_LSECTXCTRL_EN_MASK
- IXGBE_LSECTXCTRL_PNTHRSH_MASK
- IXGBE_LSECTXCTRL_RSV_MASK
- IXGBE_LSECTXKEY0
- IXGBE_LSECTXKEY1
- IXGBE_LSECTXOCTE
- IXGBE_LSECTXOCTP
- IXGBE_LSECTXPKTE
- IXGBE_LSECTXPKTP
- IXGBE_LSECTXPN0
- IXGBE_LSECTXPN1
- IXGBE_LSECTXSA
- IXGBE_LSECTXSCH
- IXGBE_LSECTXSCL
- IXGBE_LSECTXUT
- IXGBE_LSWFW
- IXGBE_LXOFFRXC
- IXGBE_LXOFFRXCNT
- IXGBE_LXOFFTXC
- IXGBE_LXONRXC
- IXGBE_LXONRXCNT
- IXGBE_LXONTXC
- IXGBE_MAC0_PTR
- IXGBE_MAC1_PTR
- IXGBE_MACA
- IXGBE_MACC
- IXGBE_MACC_FLU
- IXGBE_MACC_FS
- IXGBE_MACC_FSV_10G
- IXGBE_MACS
- IXGBE_MAC_D
- IXGBE_MAC_DC
- IXGBE_MAC_RX2TX_LPBK
- IXGBE_MAC_SGMII_BUSY
- IXGBE_MAC_STATE_DEFAULT
- IXGBE_MAC_STATE_IN_USE
- IXGBE_MAC_STATE_MODIFIED
- IXGBE_MANC
- IXGBE_MANC2H
- IXGBE_MANC_RCV_TCO_EN
- IXGBE_MAVTV
- IXGBE_MAXFRS
- IXGBE_MAX_2K_FRAME_BUILD_SKB
- IXGBE_MAX_DATA_PER_TXD
- IXGBE_MAX_EITR
- IXGBE_MAX_ETQF_FILTERS
- IXGBE_MAX_FCOE_INDICES
- IXGBE_MAX_FCPAUSE
- IXGBE_MAX_FCRTH
- IXGBE_MAX_FCRTL
- IXGBE_MAX_FDIR_INDICES
- IXGBE_MAX_FRAME_SZ
- IXGBE_MAX_FTQF_FILTERS
- IXGBE_MAX_HW_ENTRIES
- IXGBE_MAX_INT_RATE
- IXGBE_MAX_JUMBO_FRAME_SIZE
- IXGBE_MAX_L2A_QUEUES
- IXGBE_MAX_LINK_HANDLE
- IXGBE_MAX_MACVLANS
- IXGBE_MAX_MAC_HDR_LEN
- IXGBE_MAX_MSIX_VECTORS_82598
- IXGBE_MAX_MSIX_VECTORS_82599
- IXGBE_MAX_MTA
- IXGBE_MAX_NETWORK_HDR_LEN
- IXGBE_MAX_PACKET_BUFFERS
- IXGBE_MAX_PB
- IXGBE_MAX_PF_MACVLANS
- IXGBE_MAX_PHY_ADDR
- IXGBE_MAX_RETA_ENTRIES
- IXGBE_MAX_RSS_INDICES
- IXGBE_MAX_RSS_INDICES_X550
- IXGBE_MAX_RXBUFFER
- IXGBE_MAX_RXD
- IXGBE_MAX_RX_DESC_POLL
- IXGBE_MAX_SECRX_POLL
- IXGBE_MAX_SENSORS
- IXGBE_MAX_TXD
- IXGBE_MAX_TXD_PWR
- IXGBE_MAX_VFS_1TC
- IXGBE_MAX_VFS_4TC
- IXGBE_MAX_VFS_8TC
- IXGBE_MAX_VFS_DRV_LIMIT
- IXGBE_MAX_VFTA_ENTRIES
- IXGBE_MAX_VF_FUNCTIONS
- IXGBE_MAX_VF_MC_ENTRIES
- IXGBE_MAX_VMDQ_INDICES
- IXGBE_MBVFICR
- IXGBE_MBVFICR_INDEX
- IXGBE_MBVFICR_VFACK_MASK
- IXGBE_MBVFICR_VFACK_VF1
- IXGBE_MBVFICR_VFREQ_MASK
- IXGBE_MBVFICR_VFREQ_VF1
- IXGBE_MCSTCTRL
- IXGBE_MCSTCTRL_MFE
- IXGBE_MDEF
- IXGBE_MDEF_EXT
- IXGBE_MDFTC1
- IXGBE_MDFTC2
- IXGBE_MDFTFIFO1
- IXGBE_MDFTFIFO2
- IXGBE_MDFTS
- IXGBE_MDIO_AUTO_NEG_EEE_ADVT
- IXGBE_MDIO_AUTO_NEG_LINK_STATUS
- IXGBE_MDIO_AUTO_NEG_VENDOR_STAT
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF
- IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK
- IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM
- IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2
- IXGBE_MDIO_AUTO_NEG_VEN_LSC
- IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK
- IXGBE_MDIO_COMMAND_TIMEOUT
- IXGBE_MDIO_GLOBAL_ALARM_1
- IXGBE_MDIO_GLOBAL_ALARM_1_INT
- IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT
- IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL
- IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
- IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
- IXGBE_MDIO_GLOBAL_FAULT_MSG
- IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP
- IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
- IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG
- IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
- IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN
- IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN
- IXGBE_MDIO_GLOBAL_INT_MASK
- IXGBE_MDIO_GLOBAL_RES_PR_10
- IXGBE_MDIO_GLOBAL_STD_ALM2_INT
- IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
- IXGBE_MDIO_PCS_DEV_TYPE
- IXGBE_MDIO_PHY_LOW_POWER_MODE
- IXGBE_MDIO_PHY_SET_LOW_POWER_MODE
- IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR
- IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA
- IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT
- IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN
- IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
- IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE
- IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR
- IXGBE_MDIO_POWER_UP_STALL
- IXGBE_MDIO_TX_VENDOR_ALARMS_3
- IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
- IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED
- IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED
- IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS
- IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS
- IXGBE_MDIO_XENPAK_LASI_STATUS
- IXGBE_MDIO_ZERO_DEV_TYPE
- IXGBE_METF
- IXGBE_MFLCN
- IXGBE_MFLCN_DPF
- IXGBE_MFLCN_PMCF
- IXGBE_MFLCN_RFCE
- IXGBE_MFLCN_RPFCE
- IXGBE_MFLCN_RPFCE_MASK
- IXGBE_MFLCN_RPFCE_SHIFT
- IXGBE_MFUTP
- IXGBE_MFVAL
- IXGBE_MHADD
- IXGBE_MHADD_MFS_MASK
- IXGBE_MHADD_MFS_SHIFT
- IXGBE_MII_1GBASE_T_ADVERTISE
- IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX
- IXGBE_MII_2_5GBASE_T_ADVERTISE
- IXGBE_MII_5GBASE_T_ADVERTISE
- IXGBE_MII_AUTONEG_LINK_UP
- IXGBE_MII_AUTONEG_REG
- IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
- IXGBE_MII_AUTONEG_XNP_TX_REG
- IXGBE_MII_RESTART
- IXGBE_MIN_EITR
- IXGBE_MIN_FCPAUSE
- IXGBE_MIN_FCRTH
- IXGBE_MIN_FCRTL
- IXGBE_MIN_INT_RATE
- IXGBE_MIN_RSC_ITR
- IXGBE_MIN_RXD
- IXGBE_MIN_TXD
- IXGBE_MIPAF
- IXGBE_MISC_REG_82599
- IXGBE_MLADD
- IXGBE_MLFC
- IXGBE_MMAH
- IXGBE_MMAL
- IXGBE_MMNGC
- IXGBE_MMNGC_MNG_VETO
- IXGBE_MNGPDC
- IXGBE_MNGPRC
- IXGBE_MNGPTC
- IXGBE_MNGTXMAP
- IXGBE_MPC
- IXGBE_MPRC
- IXGBE_MPSAR_HI
- IXGBE_MPSAR_LO
- IXGBE_MPTC
- IXGBE_MPVC
- IXGBE_MRCTL
- IXGBE_MREVID
- IXGBE_MRFC
- IXGBE_MRQC
- IXGBE_MRQC_L3L4TXSWEN
- IXGBE_MRQC_MRQE_MASK
- IXGBE_MRQC_MULTIPLE_RSS
- IXGBE_MRQC_RSSEN
- IXGBE_MRQC_RSS_FIELD_IPV4
- IXGBE_MRQC_RSS_FIELD_IPV4_TCP
- IXGBE_MRQC_RSS_FIELD_IPV4_UDP
- IXGBE_MRQC_RSS_FIELD_IPV6
- IXGBE_MRQC_RSS_FIELD_IPV6_EX
- IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
- IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP
- IXGBE_MRQC_RSS_FIELD_IPV6_TCP
- IXGBE_MRQC_RSS_FIELD_IPV6_UDP
- IXGBE_MRQC_RSS_FIELD_MASK
- IXGBE_MRQC_RT4TCEN
- IXGBE_MRQC_RT8TCEN
- IXGBE_MRQC_RTRSS4TCEN
- IXGBE_MRQC_RTRSS8TCEN
- IXGBE_MRQC_VMDQEN
- IXGBE_MRQC_VMDQRSS32EN
- IXGBE_MRQC_VMDQRSS64EN
- IXGBE_MRQC_VMDQRT4TCEN
- IXGBE_MRQC_VMDQRT8TCEN
- IXGBE_MSCA
- IXGBE_MSCA_ADDR_CYCLE
- IXGBE_MSCA_DEV_TYPE_MASK
- IXGBE_MSCA_DEV_TYPE_SHIFT
- IXGBE_MSCA_MDI_COMMAND
- IXGBE_MSCA_MDI_IN_PROG_EN
- IXGBE_MSCA_NEW_PROTOCOL
- IXGBE_MSCA_NP_ADDR_MASK
- IXGBE_MSCA_NP_ADDR_SHIFT
- IXGBE_MSCA_OLD_PROTOCOL
- IXGBE_MSCA_OP_CODE_MASK
- IXGBE_MSCA_OP_CODE_SHIFT
- IXGBE_MSCA_PHY_ADDR_MASK
- IXGBE_MSCA_PHY_ADDR_SHIFT
- IXGBE_MSCA_READ
- IXGBE_MSCA_READ_AUTOINC
- IXGBE_MSCA_ST_CODE_MASK
- IXGBE_MSCA_ST_CODE_SHIFT
- IXGBE_MSCA_WRITE
- IXGBE_MSIXPBA
- IXGBE_MSIXT
- IXGBE_MSIX_VECTOR
- IXGBE_MSPDC
- IXGBE_MSRWD
- IXGBE_MSRWD_READ_DATA_MASK
- IXGBE_MSRWD_READ_DATA_SHIFT
- IXGBE_MSRWD_WRITE_DATA_MASK
- IXGBE_MSRWD_WRITE_DATA_SHIFT
- IXGBE_MTA
- IXGBE_MTQC
- IXGBE_MTQC_32VF
- IXGBE_MTQC_4TC_4TQ
- IXGBE_MTQC_64Q_1PB
- IXGBE_MTQC_64VF
- IXGBE_MTQC_8TC_8TQ
- IXGBE_MTQC_RT_ENA
- IXGBE_MTQC_VT_ENA
- IXGBE_MVALS_IDX_LIMIT
- IXGBE_MVALS_INIT
- IXGBE_NETDEV_STAT
- IXGBE_NOT_IMPLEMENTED
- IXGBE_NUM_RX_QUEUES
- IXGBE_NVM_POLL_READ
- IXGBE_NVM_POLL_WRITE
- IXGBE_NW_MNG_IF_SEL
- IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
- IXGBE_NW_MNG_IF_SEL_MDIO_ACT
- IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
- IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
- IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M
- IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G
- IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M
- IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G
- IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G
- IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE
- IXGBE_O2BGPTC
- IXGBE_O2BSPC
- IXGBE_OPTION_ROM_PTR
- IXGBE_OVERFLOW_PERIOD
- IXGBE_PAP
- IXGBE_PAP_TXPAUSECNT_MASK
- IXGBE_PBACL
- IXGBE_PBACLR_82599
- IXGBE_PBANUM0_PTR
- IXGBE_PBANUM1_PTR
- IXGBE_PBANUM_LENGTH
- IXGBE_PBANUM_PTR_GUARD
- IXGBE_PBRXECC
- IXGBE_PBTXECC
- IXGBE_PB_STATS_LEN
- IXGBE_PCIDEVCTRL2_16_32ms
- IXGBE_PCIDEVCTRL2_16_32ms_def
- IXGBE_PCIDEVCTRL2_17_34s
- IXGBE_PCIDEVCTRL2_1_2ms
- IXGBE_PCIDEVCTRL2_1_2s
- IXGBE_PCIDEVCTRL2_260_520ms
- IXGBE_PCIDEVCTRL2_4_8s
- IXGBE_PCIDEVCTRL2_50_100us
- IXGBE_PCIDEVCTRL2_65_130ms
- IXGBE_PCIDEVCTRL2_TIMEO_MASK
- IXGBE_PCIEANACTL
- IXGBE_PCIEECCCTL
- IXGBE_PCIEECCCTL0
- IXGBE_PCIEECCCTL1
- IXGBE_PCIESPARE
- IXGBE_PCIE_ANALOG_PTR
- IXGBE_PCIE_ANALOG_PTR_X550
- IXGBE_PCIE_CONFIG0_PTR
- IXGBE_PCIE_CONFIG1_PTR
- IXGBE_PCIE_CONFIG_SIZE
- IXGBE_PCIE_CTRL2
- IXGBE_PCIE_CTRL2_DISABLE_SELECT
- IXGBE_PCIE_CTRL2_DUMMY_ENABLE
- IXGBE_PCIE_CTRL2_LAN_DISABLE
- IXGBE_PCIE_DIAG
- IXGBE_PCIE_GENERAL_PTR
- IXGBE_PCIE_MSIX_82598_CAPS
- IXGBE_PCIE_MSIX_82599_CAPS
- IXGBE_PCIE_MSIX_TBL_SZ_MASK
- IXGBE_PCI_DELAY
- IXGBE_PCI_DEVICE_CONTROL2
- IXGBE_PCI_DEVICE_CONTROL2_16ms
- IXGBE_PCI_DEVICE_STATUS
- IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING
- IXGBE_PCI_HEADER_TYPE_MULTIFUNC
- IXGBE_PCI_HEADER_TYPE_REGISTER
- IXGBE_PCI_LINK_SPEED
- IXGBE_PCI_LINK_SPEED_2500
- IXGBE_PCI_LINK_SPEED_5000
- IXGBE_PCI_LINK_SPEED_8000
- IXGBE_PCI_LINK_STATUS
- IXGBE_PCI_LINK_WIDTH
- IXGBE_PCI_LINK_WIDTH_1
- IXGBE_PCI_LINK_WIDTH_2
- IXGBE_PCI_LINK_WIDTH_4
- IXGBE_PCI_LINK_WIDTH_8
- IXGBE_PCI_MASTER_DISABLE_TIMEOUT
- IXGBE_PCRC8ECH
- IXGBE_PCRC8ECH_MASK
- IXGBE_PCRC8ECL
- IXGBE_PCS1GANA
- IXGBE_PCS1GANA_ASM_PAUSE
- IXGBE_PCS1GANA_SYM_PAUSE
- IXGBE_PCS1GANLP
- IXGBE_PCS1GANLPNP
- IXGBE_PCS1GANNP
- IXGBE_PCS1GCFIG
- IXGBE_PCS1GDBG0
- IXGBE_PCS1GDBG1
- IXGBE_PCS1GLCTL
- IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
- IXGBE_PCS1GLCTL_AN_ENABLE
- IXGBE_PCS1GLCTL_AN_RESTART
- IXGBE_PCS1GLCTL_FLV_LINK_UP
- IXGBE_PCS1GLCTL_FORCE_LINK
- IXGBE_PCS1GLCTL_LOW_LINK_LATCH
- IXGBE_PCS1GLSTA
- IXGBE_PCS1GLSTA_AN_COMPLETE
- IXGBE_PCS1GLSTA_AN_ERROR_RWS
- IXGBE_PCS1GLSTA_AN_PAGE_RX
- IXGBE_PCS1GLSTA_AN_REMOTE_FAULT
- IXGBE_PCS1GLSTA_AN_TIMED_OUT
- IXGBE_PCS1GLSTA_LINK_OK
- IXGBE_PCS1GLSTA_SYNK_OK
- IXGBE_PCSS1
- IXGBE_PCSS2
- IXGBE_PDPMCS
- IXGBE_PDPMCS_ARBDIS
- IXGBE_PDPMCS_TPPAC
- IXGBE_PDPMCS_TRM
- IXGBE_PE
- IXGBE_PE_BIT1
- IXGBE_PE_CONFIG
- IXGBE_PE_OUTPUT
- IXGBE_PFCTOP
- IXGBE_PFC_D
- IXGBE_PFDTXGSWC
- IXGBE_PFDTXGSWC_VT_LBEN
- IXGBE_PFFLPH
- IXGBE_PFFLPL
- IXGBE_PFMAILBOX
- IXGBE_PFMAILBOX_ACK
- IXGBE_PFMAILBOX_PFU
- IXGBE_PFMAILBOX_RVFU
- IXGBE_PFMAILBOX_STS
- IXGBE_PFMAILBOX_VFU
- IXGBE_PFMBICR
- IXGBE_PFMBIMR
- IXGBE_PFMBMEM
- IXGBE_PFVFMRQC
- IXGBE_PFVFRETA
- IXGBE_PFVFRSSRK
- IXGBE_PFVFSPOOF
- IXGBE_PFVFSPOOF_REG_COUNT
- IXGBE_PF_CONTROL_MSG
- IXGBE_PHYADR_82599
- IXGBE_PHYCTL_82599
- IXGBE_PHYDAT_82599
- IXGBE_PHY_D
- IXGBE_PHY_DC
- IXGBE_PHY_INIT_END_NL
- IXGBE_PHY_INIT_OFFSET_NL
- IXGBE_PHY_PTR
- IXGBE_PHY_REVISION_MASK
- IXGBE_PICAUSE
- IXGBE_PIENA
- IXGBE_PRC1023
- IXGBE_PRC127
- IXGBE_PRC1522
- IXGBE_PRC255
- IXGBE_PRC511
- IXGBE_PRC64
- IXGBE_PRIV_FLAGS_LEGACY_RX
- IXGBE_PRIV_FLAGS_STR_LEN
- IXGBE_PRIV_FLAGS_VF_IPSEC_EN
- IXGBE_PSRTYPE
- IXGBE_PSRTYPE_IPV4HDR
- IXGBE_PSRTYPE_IPV6HDR
- IXGBE_PSRTYPE_L2HDR
- IXGBE_PSRTYPE_RQPL_MASK
- IXGBE_PSRTYPE_RQPL_SHIFT
- IXGBE_PSRTYPE_TCPHDR
- IXGBE_PSRTYPE_UDPHDR
- IXGBE_PTC1023
- IXGBE_PTC127
- IXGBE_PTC1522
- IXGBE_PTC255
- IXGBE_PTC511
- IXGBE_PTC64
- IXGBE_PTP_TX_TIMEOUT
- IXGBE_PVFTDH
- IXGBE_PVFTDHN
- IXGBE_PVFTDT
- IXGBE_PVFTDTN
- IXGBE_PVFTDWBAH
- IXGBE_PVFTDWBAHn
- IXGBE_PVFTDWBAL
- IXGBE_PVFTDWBALn
- IXGBE_PVFTXDCTL
- IXGBE_PXOFFRXC
- IXGBE_PXOFFRXCNT
- IXGBE_PXOFFTXC
- IXGBE_PXON2OFFCNT
- IXGBE_PXONRXC
- IXGBE_PXONRXCNT
- IXGBE_PXONTXC
- IXGBE_QBRC
- IXGBE_QBRC_H
- IXGBE_QBRC_L
- IXGBE_QBTC
- IXGBE_QBTC_H
- IXGBE_QBTC_L
- IXGBE_QDE
- IXGBE_QDE_ENABLE
- IXGBE_QDE_HIDE_VLAN
- IXGBE_QDE_IDX_MASK
- IXGBE_QDE_IDX_SHIFT
- IXGBE_QDE_WRITE
- IXGBE_QPRC
- IXGBE_QPRDC
- IXGBE_QPTC
- IXGBE_QUEUE_STATS_LEN
- IXGBE_RAH
- IXGBE_RAH_AV
- IXGBE_RAH_VIND_MASK
- IXGBE_RAH_VIND_SHIFT
- IXGBE_RAL
- IXGBE_RDBAH
- IXGBE_RDBAL
- IXGBE_RDDCC
- IXGBE_RDH
- IXGBE_RDHMPN
- IXGBE_RDHMPN_RDICADDR
- IXGBE_RDHMPN_RDICADDR_SHIFT
- IXGBE_RDHMPN_RDICRDREQ
- IXGBE_RDLEN
- IXGBE_RDMAD
- IXGBE_RDMAM
- IXGBE_RDMAM_DESC_COMP_FIFO
- IXGBE_RDMAM_DESC_COM_FIFO_COUNT
- IXGBE_RDMAM_DESC_COM_FIFO_RANGE
- IXGBE_RDMAM_DFC_CMD_FIFO
- IXGBE_RDMAM_DFC_CMD_FIFO_COUNT
- IXGBE_RDMAM_DFC_CMD_FIFO_RANGE
- IXGBE_RDMAM_DWORD_SHIFT
- IXGBE_RDMAM_MEM_SEL_SHIFT
- IXGBE_RDMAM_QSC_CNT_RAM
- IXGBE_RDMAM_QSC_CNT_RAM_COUNT
- IXGBE_RDMAM_QSC_CNT_RAM_RANGE
- IXGBE_RDMAM_QSC_QUEUE_CNT
- IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT
- IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE
- IXGBE_RDMAM_QSC_QUEUE_RAM
- IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT
- IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE
- IXGBE_RDMAM_TCN_STATUS_RAM
- IXGBE_RDMAM_TCN_STATUS_RAM_COUNT
- IXGBE_RDMAM_TCN_STATUS_RAM_RANGE
- IXGBE_RDMAM_WB_COLL_FIFO
- IXGBE_RDMAM_WB_COLL_FIFO_COUNT
- IXGBE_RDMAM_WB_COLL_FIFO_RANGE
- IXGBE_RDPROBE
- IXGBE_RDRXCTL
- IXGBE_RDRXCTL_AGGDIS
- IXGBE_RDRXCTL_CRCSTRIP
- IXGBE_RDRXCTL_DMAIDONE
- IXGBE_RDRXCTL_FCOE_WRFIX
- IXGBE_RDRXCTL_MBINTEN
- IXGBE_RDRXCTL_MCEN
- IXGBE_RDRXCTL_MDP_EN
- IXGBE_RDRXCTL_MPBEN
- IXGBE_RDRXCTL_MVMEN
- IXGBE_RDRXCTL_PSP
- IXGBE_RDRXCTL_RDMTS_1_2
- IXGBE_RDRXCTL_RSCACKC
- IXGBE_RDRXCTL_RSCFRSTSIZE
- IXGBE_RDRXCTL_RSCLLIDIS
- IXGBE_RDSTAT
- IXGBE_RDSTATCTL
- IXGBE_RDT
- IXGBE_READ_REG
- IXGBE_READ_REG_ARRAY
- IXGBE_REGS_LEN
- IXGBE_REMOVED
- IXGBE_REOFF
- IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE
- IXGBE_REQ_TX_BUFFER_GRANULARITY
- IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE
- IXGBE_RETA
- IXGBE_RFC
- IXGBE_RFCTL
- IXGBE_RFCTL_IPFRSP_DIS
- IXGBE_RFCTL_IPV6_DIS
- IXGBE_RFCTL_IPV6_EX_DIS
- IXGBE_RFCTL_IPV6_XSUM_DIS
- IXGBE_RFCTL_ISCSI_DIS
- IXGBE_RFCTL_ISCSI_DWC_MASK
- IXGBE_RFCTL_ISCSI_DWC_SHIFT
- IXGBE_RFCTL_NEW_IPV6_EXT_DIS
- IXGBE_RFCTL_NFSR_DIS
- IXGBE_RFCTL_NFSW_DIS
- IXGBE_RFCTL_NFS_VER_2
- IXGBE_RFCTL_NFS_VER_3
- IXGBE_RFCTL_NFS_VER_4
- IXGBE_RFCTL_NFS_VER_MASK
- IXGBE_RFCTL_NFS_VER_SHIFT
- IXGBE_RFCTL_RSC_DIS
- IXGBE_RFVAL
- IXGBE_RIC_DW
- IXGBE_RJC
- IXGBE_RLEC
- IXGBE_RMCS
- IXGBE_RMCS_ARBDIS
- IXGBE_RMCS_DFP
- IXGBE_RMCS_RAC
- IXGBE_RMCS_RRM
- IXGBE_RMCS_TFCE_802_3X
- IXGBE_RMCS_TFCE_PRIORITY
- IXGBE_RNBC
- IXGBE_ROC
- IXGBE_RQSMR
- IXGBE_RQTC
- IXGBE_RQTC_SHIFT_TC
- IXGBE_RQTC_TC0_MASK
- IXGBE_RQTC_TC1_MASK
- IXGBE_RQTC_TC2_MASK
- IXGBE_RQTC_TC3_MASK
- IXGBE_RQTC_TC4_MASK
- IXGBE_RQTC_TC5_MASK
- IXGBE_RQTC_TC6_MASK
- IXGBE_RQTC_TC7_MASK
- IXGBE_RSCCTL
- IXGBE_RSCCTL_MAXDESC_1
- IXGBE_RSCCTL_MAXDESC_16
- IXGBE_RSCCTL_MAXDESC_4
- IXGBE_RSCCTL_MAXDESC_8
- IXGBE_RSCCTL_RSCEN
- IXGBE_RSCDBU
- IXGBE_RSCDBU_RSCACKDIS
- IXGBE_RSCDBU_RSCSMALDIS_MASK
- IXGBE_RSOFF
- IXGBE_RSSRK
- IXGBE_RSS_16Q_MASK
- IXGBE_RSS_2Q_MASK
- IXGBE_RSS_4Q_MASK
- IXGBE_RSS_64Q_MASK
- IXGBE_RSS_8Q_MASK
- IXGBE_RSS_DISABLED_MASK
- IXGBE_RSS_KEY_SIZE
- IXGBE_RSS_L4_TYPES_MASK
- IXGBE_RT2CR
- IXGBE_RT2CR_LSP
- IXGBE_RT2CR_MCL_SHIFT
- IXGBE_RT2SR
- IXGBE_RTRPCS
- IXGBE_RTRPCS_ARBDIS
- IXGBE_RTRPCS_RAC
- IXGBE_RTRPCS_RRM
- IXGBE_RTRPT4C
- IXGBE_RTRPT4C_BWG_SHIFT
- IXGBE_RTRPT4C_GSP
- IXGBE_RTRPT4C_LSP
- IXGBE_RTRPT4C_MCL_SHIFT
- IXGBE_RTRPT4S
- IXGBE_RTRUP2TC
- IXGBE_RTRUP2TC_UP_MASK
- IXGBE_RTRUP2TC_UP_SHIFT
- IXGBE_RTTBCNRC
- IXGBE_RTTBCNRC_RF_DEC_MASK
- IXGBE_RTTBCNRC_RF_INT_MASK
- IXGBE_RTTBCNRC_RF_INT_SHIFT
- IXGBE_RTTBCNRC_RS_ENA
- IXGBE_RTTBCNRD
- IXGBE_RTTBCNRM
- IXGBE_RTTDCS
- IXGBE_RTTDCS_ARBDIS
- IXGBE_RTTDCS_BDPM
- IXGBE_RTTDCS_BPBFSM
- IXGBE_RTTDCS_SPEED_CHG
- IXGBE_RTTDCS_TDPAC
- IXGBE_RTTDCS_TDRM
- IXGBE_RTTDCS_VMPAC
- IXGBE_RTTDQSEL
- IXGBE_RTTDT1C
- IXGBE_RTTDT1S
- IXGBE_RTTDT2C
- IXGBE_RTTDT2C_BWG_SHIFT
- IXGBE_RTTDT2C_GSP
- IXGBE_RTTDT2C_LSP
- IXGBE_RTTDT2C_MCL_SHIFT
- IXGBE_RTTDT2S
- IXGBE_RTTDTECC
- IXGBE_RTTDTECC_NO_BCN
- IXGBE_RTTPCS
- IXGBE_RTTPCS_ARBDIS
- IXGBE_RTTPCS_ARBD_DCB
- IXGBE_RTTPCS_ARBD_SHIFT
- IXGBE_RTTPCS_TPPAC
- IXGBE_RTTPCS_TPRM
- IXGBE_RTTPT2C
- IXGBE_RTTPT2C_BWG_SHIFT
- IXGBE_RTTPT2C_GSP
- IXGBE_RTTPT2C_LSP
- IXGBE_RTTPT2C_MCL_SHIFT
- IXGBE_RTTPT2S
- IXGBE_RTTQCNCR
- IXGBE_RTTQCNRM
- IXGBE_RTTQCNRR
- IXGBE_RTTQCNTG
- IXGBE_RTTUP2TC
- IXGBE_RTTUP2TC_UP_SHIFT
- IXGBE_RUC
- IXGBE_RUPPBMR
- IXGBE_RUPPBMR_MQA
- IXGBE_RXBUFCTRL
- IXGBE_RXBUFDATA
- IXGBE_RXBUFFER_1536
- IXGBE_RXBUFFER_256
- IXGBE_RXBUFFER_2K
- IXGBE_RXBUFFER_3K
- IXGBE_RXBUFFER_4K
- IXGBE_RXCSUM
- IXGBE_RXCSUM_IPPCSE
- IXGBE_RXCSUM_PCSD
- IXGBE_RXCTRL
- IXGBE_RXCTRL_DMBYPS
- IXGBE_RXCTRL_RXEN
- IXGBE_RXDADV_ERR_CE
- IXGBE_RXDADV_ERR_FCEOFE
- IXGBE_RXDADV_ERR_FCERR
- IXGBE_RXDADV_ERR_FDIR_COLL
- IXGBE_RXDADV_ERR_FDIR_DROP
- IXGBE_RXDADV_ERR_FDIR_LEN
- IXGBE_RXDADV_ERR_FRAME_ERR_MASK
- IXGBE_RXDADV_ERR_HBO
- IXGBE_RXDADV_ERR_IPE
- IXGBE_RXDADV_ERR_IPSEC_AUTH_FAILED
- IXGBE_RXDADV_ERR_IPSEC_INV_LENGTH
- IXGBE_RXDADV_ERR_IPSEC_INV_PROTOCOL
- IXGBE_RXDADV_ERR_LE
- IXGBE_RXDADV_ERR_MASK
- IXGBE_RXDADV_ERR_OSE
- IXGBE_RXDADV_ERR_OUTERIPER
- IXGBE_RXDADV_ERR_PE
- IXGBE_RXDADV_ERR_SHIFT
- IXGBE_RXDADV_ERR_TCPE
- IXGBE_RXDADV_ERR_USE
- IXGBE_RXDADV_FCSTAT_SHIFT
- IXGBE_RXDADV_HDRBUFLEN_MASK
- IXGBE_RXDADV_HDRBUFLEN_SHIFT
- IXGBE_RXDADV_NEXTP_MASK
- IXGBE_RXDADV_NEXTP_SHIFT
- IXGBE_RXDADV_PKTTYPE_ETQF
- IXGBE_RXDADV_PKTTYPE_ETQF_MASK
- IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT
- IXGBE_RXDADV_PKTTYPE_IPSEC_AH
- IXGBE_RXDADV_PKTTYPE_IPSEC_ESP
- IXGBE_RXDADV_PKTTYPE_IPV4
- IXGBE_RXDADV_PKTTYPE_IPV4_EX
- IXGBE_RXDADV_PKTTYPE_IPV6
- IXGBE_RXDADV_PKTTYPE_IPV6_EX
- IXGBE_RXDADV_PKTTYPE_LINKSEC
- IXGBE_RXDADV_PKTTYPE_MASK
- IXGBE_RXDADV_PKTTYPE_MASK_EX
- IXGBE_RXDADV_PKTTYPE_NFS
- IXGBE_RXDADV_PKTTYPE_NONE
- IXGBE_RXDADV_PKTTYPE_SCTP
- IXGBE_RXDADV_PKTTYPE_TCP
- IXGBE_RXDADV_PKTTYPE_TUNNEL
- IXGBE_RXDADV_PKTTYPE_UDP
- IXGBE_RXDADV_PKTTYPE_VXLAN
- IXGBE_RXDADV_RSCCNT_MASK
- IXGBE_RXDADV_RSCCNT_SHIFT
- IXGBE_RXDADV_RSSTYPE_IPV4
- IXGBE_RXDADV_RSSTYPE_IPV4_TCP
- IXGBE_RXDADV_RSSTYPE_IPV4_UDP
- IXGBE_RXDADV_RSSTYPE_IPV6
- IXGBE_RXDADV_RSSTYPE_IPV6_EX
- IXGBE_RXDADV_RSSTYPE_IPV6_TCP
- IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX
- IXGBE_RXDADV_RSSTYPE_IPV6_UDP
- IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX
- IXGBE_RXDADV_RSSTYPE_MASK
- IXGBE_RXDADV_RSSTYPE_NONE
- IXGBE_RXDADV_SPH
- IXGBE_RXDADV_SPLITHEADER_EN
- IXGBE_RXDADV_STAT_DD
- IXGBE_RXDADV_STAT_EOP
- IXGBE_RXDADV_STAT_FCEOFS
- IXGBE_RXDADV_STAT_FCSTAT
- IXGBE_RXDADV_STAT_FCSTAT_DDP
- IXGBE_RXDADV_STAT_FCSTAT_FCPRSP
- IXGBE_RXDADV_STAT_FCSTAT_NODDP
- IXGBE_RXDADV_STAT_FCSTAT_NOMTCH
- IXGBE_RXDADV_STAT_FLM
- IXGBE_RXDADV_STAT_MASK
- IXGBE_RXDADV_STAT_SECP
- IXGBE_RXDADV_STAT_TS
- IXGBE_RXDADV_STAT_VP
- IXGBE_RXDATARDPTR
- IXGBE_RXDATAWRPTR
- IXGBE_RXDBUECC
- IXGBE_RXDBUEST
- IXGBE_RXDCTL
- IXGBE_RXDCTL_ENABLE
- IXGBE_RXDCTL_RLPMLMASK
- IXGBE_RXDCTL_RLPML_EN
- IXGBE_RXDCTL_SWFLSH
- IXGBE_RXDCTL_VME
- IXGBE_RXDDGBCH
- IXGBE_RXDDGBCL
- IXGBE_RXDDGPC
- IXGBE_RXDESCRDPTR
- IXGBE_RXDESCWRPTR
- IXGBE_RXDGBCH
- IXGBE_RXDGBCL
- IXGBE_RXDGPC
- IXGBE_RXDLPBKGBCH
- IXGBE_RXDLPBKGBCL
- IXGBE_RXDLPBKGPC
- IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK
- IXGBE_RXDPS_HDRSTAT_HDRSP
- IXGBE_RXDSTATCTRL
- IXGBE_RXD_CFI_MASK
- IXGBE_RXD_CFI_SHIFT
- IXGBE_RXD_ERR_CE
- IXGBE_RXD_ERR_FRAME_ERR_MASK
- IXGBE_RXD_ERR_IPE
- IXGBE_RXD_ERR_LE
- IXGBE_RXD_ERR_OSE
- IXGBE_RXD_ERR_PE
- IXGBE_RXD_ERR_TCPE
- IXGBE_RXD_ERR_USE
- IXGBE_RXD_PRI_MASK
- IXGBE_RXD_PRI_SHIFT
- IXGBE_RXD_STAT_ACK
- IXGBE_RXD_STAT_CRCV
- IXGBE_RXD_STAT_DD
- IXGBE_RXD_STAT_DYNINT
- IXGBE_RXD_STAT_EOP
- IXGBE_RXD_STAT_FLM
- IXGBE_RXD_STAT_IPCS
- IXGBE_RXD_STAT_L4CS
- IXGBE_RXD_STAT_LB
- IXGBE_RXD_STAT_LLINT
- IXGBE_RXD_STAT_OUTERIPCS
- IXGBE_RXD_STAT_PIF
- IXGBE_RXD_STAT_SECP
- IXGBE_RXD_STAT_TS
- IXGBE_RXD_STAT_TSIP
- IXGBE_RXD_STAT_UDPCS
- IXGBE_RXD_STAT_UDPV
- IXGBE_RXD_STAT_VEXT
- IXGBE_RXD_STAT_VP
- IXGBE_RXD_VLAN_ID_MASK
- IXGBE_RXFECCERR0
- IXGBE_RXIDX_TBL_SHIFT
- IXGBE_RXLPBKGBCH
- IXGBE_RXLPBKGBCL
- IXGBE_RXLPBKGPC
- IXGBE_RXMEMWRAP
- IXGBE_RXMOD_DECRYPT
- IXGBE_RXMOD_IPV6
- IXGBE_RXMOD_PROTO_ESP
- IXGBE_RXMOD_VALID
- IXGBE_RXMTRL
- IXGBE_RXMTRL_V1_CTRLT_MASK
- IXGBE_RXMTRL_V1_DELAY_REQ_MSG
- IXGBE_RXMTRL_V1_DELAY_RESP_MSG
- IXGBE_RXMTRL_V1_FOLLOWUP_MSG
- IXGBE_RXMTRL_V1_MGMT_MSG
- IXGBE_RXMTRL_V1_SYNC_MSG
- IXGBE_RXMTRL_V2_ANNOUNCE_MSG
- IXGBE_RXMTRL_V2_DELAY_REQ_MSG
- IXGBE_RXMTRL_V2_DELAY_RESP_MSG
- IXGBE_RXMTRL_V2_FOLLOWUP_MSG
- IXGBE_RXMTRL_V2_MGMT_MSG
- IXGBE_RXMTRL_V2_MSGID_MASK
- IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG
- IXGBE_RXMTRL_V2_PDELAY_REQ_MSG
- IXGBE_RXMTRL_V2_PDELAY_RESP_MSG
- IXGBE_RXMTRL_V2_SIGNALING_MSG
- IXGBE_RXMTRL_V2_SYNC_MSG
- IXGBE_RXNFGBCH
- IXGBE_RXNFGBCL
- IXGBE_RXNFGPC
- IXGBE_RXPBSIZE
- IXGBE_RXPBSIZE_128KB
- IXGBE_RXPBSIZE_48KB
- IXGBE_RXPBSIZE_64KB
- IXGBE_RXPBSIZE_80KB
- IXGBE_RXPBSIZE_MAX
- IXGBE_RXPBSIZE_SHIFT
- IXGBE_RXRDPTR
- IXGBE_RXRDWRPTR
- IXGBE_RXSATRH
- IXGBE_RXSATRL
- IXGBE_RXSTMPH
- IXGBE_RXSTMPL
- IXGBE_RXTXIDX_IDX_SHIFT
- IXGBE_RXTXIDX_IPS_EN
- IXGBE_RXTXIDX_READ
- IXGBE_RXTXIDX_WRITE
- IXGBE_RXTXMOD_VF
- IXGBE_RXUSED
- IXGBE_RXWRPTR
- IXGBE_RX_BUFFER_WRITE
- IXGBE_RX_DESC
- IXGBE_RX_DESC_SPECIAL_PRI_MASK
- IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
- IXGBE_RX_DESC_SPECIAL_VLAN_MASK
- IXGBE_RX_DMA_ATTR
- IXGBE_RX_HDR_SIZE
- IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
- IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
- IXGBE_SAN_MAC_ADDR_PTR
- IXGBE_SAQF
- IXGBE_SB_IOSF_CTRL_ADDR_MASK
- IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
- IXGBE_SB_IOSF_CTRL_BUSY
- IXGBE_SB_IOSF_CTRL_BUSY_SHIFT
- IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
- IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
- IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
- IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT
- IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK
- IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
- IXGBE_SB_IOSF_INDIRECT_CTRL
- IXGBE_SB_IOSF_INDIRECT_DATA
- IXGBE_SB_IOSF_TARGET_KR_PHY
- IXGBE_SDP0_GPIEN
- IXGBE_SDP0_GPIEN_8259X
- IXGBE_SDP0_GPIEN_X540
- IXGBE_SDP0_GPIEN_X550
- IXGBE_SDP0_GPIEN_X550EM_a
- IXGBE_SDP0_GPIEN_X550EM_x
- IXGBE_SDP1_GPIEN
- IXGBE_SDP1_GPIEN_8259X
- IXGBE_SDP1_GPIEN_X540
- IXGBE_SDP1_GPIEN_X550
- IXGBE_SDP1_GPIEN_X550EM_a
- IXGBE_SDP1_GPIEN_X550EM_x
- IXGBE_SDP2_GPIEN
- IXGBE_SDP2_GPIEN_8259X
- IXGBE_SDP2_GPIEN_X540
- IXGBE_SDP2_GPIEN_X550
- IXGBE_SDP2_GPIEN_X550EM_a
- IXGBE_SDP2_GPIEN_X550EM_x
- IXGBE_SDPQF
- IXGBE_SECRXCTRL
- IXGBE_SECRXCTRL_RX_DIS
- IXGBE_SECRXCTRL_SECRX_DIS
- IXGBE_SECRXSTAT
- IXGBE_SECRXSTAT_ECC_RXERR
- IXGBE_SECRXSTAT_SECRX_OFF_DIS
- IXGBE_SECRXSTAT_SECRX_RDY
- IXGBE_SECTXBUFFAF
- IXGBE_SECTXCTRL
- IXGBE_SECTXCTRL_SECTX_DIS
- IXGBE_SECTXCTRL_STORE_FORWARD
- IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE
- IXGBE_SECTXCTRL_TX_DIS
- IXGBE_SECTXMINIFG
- IXGBE_SECTXSTAT
- IXGBE_SECTXSTAT_ECC_TXERR
- IXGBE_SECTXSTAT_SECTX_OFF_DIS
- IXGBE_SECTXSTAT_SECTX_RDY
- IXGBE_SECTX_DCB
- IXGBE_SERDESC
- IXGBE_SERIAL_NUMBER_MAC_ADDR
- IXGBE_SET_FLAG
- IXGBE_SFF_10GBASELR_CAPABLE
- IXGBE_SFF_10GBASESR_CAPABLE
- IXGBE_SFF_10GBE_COMP_CODES
- IXGBE_SFF_1GBASELX_CAPABLE
- IXGBE_SFF_1GBASESX_CAPABLE
- IXGBE_SFF_1GBASET_CAPABLE
- IXGBE_SFF_1GBE_COMP_CODES
- IXGBE_SFF_ADDRESSING_MODE
- IXGBE_SFF_CABLE_SPEC_COMP
- IXGBE_SFF_CABLE_TECHNOLOGY
- IXGBE_SFF_DA_ACTIVE_CABLE
- IXGBE_SFF_DA_PASSIVE_CABLE
- IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING
- IXGBE_SFF_DDM_IMPLEMENTED
- IXGBE_SFF_IDENTIFIER
- IXGBE_SFF_IDENTIFIER_QSFP_PLUS
- IXGBE_SFF_IDENTIFIER_SFP
- IXGBE_SFF_QSFP_10GBE_COMP
- IXGBE_SFF_QSFP_1GBE_COMP
- IXGBE_SFF_QSFP_CABLE_LENGTH
- IXGBE_SFF_QSFP_CONNECTOR
- IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE
- IXGBE_SFF_QSFP_DA_ACTIVE_CABLE
- IXGBE_SFF_QSFP_DA_PASSIVE_CABLE
- IXGBE_SFF_QSFP_DEVICE_TECH
- IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL
- IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0
- IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1
- IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2
- IXGBE_SFF_SFF_8472_COMP
- IXGBE_SFF_SFF_8472_ESCB
- IXGBE_SFF_SFF_8472_OSCB
- IXGBE_SFF_SFF_8472_SWAP
- IXGBE_SFF_SFF_8472_UNSUP
- IXGBE_SFF_SOFT_RS_SELECT_10G
- IXGBE_SFF_SOFT_RS_SELECT_1G
- IXGBE_SFF_SOFT_RS_SELECT_MASK
- IXGBE_SFF_VENDOR_OUI_AVAGO
- IXGBE_SFF_VENDOR_OUI_BYTE0
- IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT
- IXGBE_SFF_VENDOR_OUI_BYTE1
- IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT
- IXGBE_SFF_VENDOR_OUI_BYTE2
- IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT
- IXGBE_SFF_VENDOR_OUI_FTL
- IXGBE_SFF_VENDOR_OUI_INTEL
- IXGBE_SFF_VENDOR_OUI_TYCO
- IXGBE_SFP_DETECT_RETRIES
- IXGBE_SFP_POLL_JIFFIES
- IXGBE_SGMIIC
- IXGBE_SHADOW_RAM_SIZE_X550
- IXGBE_SKB_PAD
- IXGBE_SMADARCTL
- IXGBE_SMARTSPEED_MAX_RETRIES
- IXGBE_SPOOF_ETHERTYPEAS
- IXGBE_SPOOF_ETHERTYPEAS_SHIFT
- IXGBE_SPOOF_MACAS_MASK
- IXGBE_SPOOF_VLANAS_MASK
- IXGBE_SPOOF_VLANAS_SHIFT
- IXGBE_SRRCTL
- IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
- IXGBE_SRRCTL_BSIZEHDR_MASK
- IXGBE_SRRCTL_BSIZEPKT_MASK
- IXGBE_SRRCTL_BSIZEPKT_SHIFT
- IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
- IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT
- IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT
- IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
- IXGBE_SRRCTL_DESCTYPE_LEGACY
- IXGBE_SRRCTL_DESCTYPE_MASK
- IXGBE_SRRCTL_DROP_EN
- IXGBE_SRRCTL_RDMTS_MASK
- IXGBE_SRRCTL_RDMTS_SHIFT
- IXGBE_SSVPC
- IXGBE_STARCTRL
- IXGBE_STAT
- IXGBE_STATS
- IXGBE_STATS_LEN
- IXGBE_STATUS
- IXGBE_STATUS_GIO
- IXGBE_STATUS_LAN_ID
- IXGBE_STATUS_LAN_ID_0
- IXGBE_STATUS_LAN_ID_1
- IXGBE_STATUS_LAN_ID_SHIFT
- IXGBE_STORE_AS_BE16
- IXGBE_STORE_AS_BE32
- IXGBE_SUBDEV_ID_82599EN_SFP_OCP1
- IXGBE_SUBDEV_ID_82599_560FLR
- IXGBE_SUBDEV_ID_82599_ECNA_DP
- IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
- IXGBE_SUBDEV_ID_82599_LOM_SNAP6
- IXGBE_SUBDEV_ID_82599_RNDC
- IXGBE_SUBDEV_ID_82599_SFP
- IXGBE_SUBDEV_ID_82599_SFP_1OCP
- IXGBE_SUBDEV_ID_82599_SFP_2OCP
- IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1
- IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2
- IXGBE_SUBDEV_ID_82599_SFP_WOL0
- IXGBE_SUBDEV_ID_82599_SP_560FLR
- IXGBE_SWFW_REGSMP
- IXGBE_SWFW_SYNC
- IXGBE_SWFW_SYNC_8259X
- IXGBE_SWFW_SYNC_X540
- IXGBE_SWFW_SYNC_X550
- IXGBE_SWFW_SYNC_X550EM_a
- IXGBE_SWFW_SYNC_X550EM_x
- IXGBE_SWSM
- IXGBE_SWSM_8259X
- IXGBE_SWSM_SMBI
- IXGBE_SWSM_SWESMBI
- IXGBE_SWSM_WMNG
- IXGBE_SWSM_X540
- IXGBE_SWSM_X550
- IXGBE_SWSM_X550EM_a
- IXGBE_SWSM_X550EM_x
- IXGBE_SWSR
- IXGBE_SYNQF
- IXGBE_SYSTIMH
- IXGBE_SYSTIML
- IXGBE_SYSTIMR
- IXGBE_TAF_ASM_PAUSE
- IXGBE_TAF_SYM_PAUSE
- IXGBE_TCPTIMER
- IXGBE_TCPTIMER_COUNT_ENABLE
- IXGBE_TCPTIMER_COUNT_FINISH
- IXGBE_TCPTIMER_DURATION_MASK
- IXGBE_TCPTIMER_KS
- IXGBE_TCPTIMER_LOOP
- IXGBE_TDBAH
- IXGBE_TDBAL
- IXGBE_TDH
- IXGBE_TDHMPN
- IXGBE_TDHMPN2
- IXGBE_TDHMPN_TDICADDR
- IXGBE_TDHMPN_TDICADDR_SHIFT
- IXGBE_TDHMPN_TDICRDREQ
- IXGBE_TDLEN
- IXGBE_TDPROBE
- IXGBE_TDPT2TCCR
- IXGBE_TDPT2TCCR_BWG_SHIFT
- IXGBE_TDPT2TCCR_GSP
- IXGBE_TDPT2TCCR_LSP
- IXGBE_TDPT2TCCR_MCL_SHIFT
- IXGBE_TDPT2TCSR
- IXGBE_TDSTAT
- IXGBE_TDSTATCTL
- IXGBE_TDT
- IXGBE_TDTQ2TCCR
- IXGBE_TDTQ2TCCR_BWG_SHIFT
- IXGBE_TDTQ2TCCR_GSP
- IXGBE_TDTQ2TCCR_LSP
- IXGBE_TDTQ2TCCR_MCL_SHIFT
- IXGBE_TDTQ2TCSR
- IXGBE_TDWBAH
- IXGBE_TDWBAL
- IXGBE_TDWBAL_HEAD_WB_ENABLE
- IXGBE_TDWBAL_SEQNUM_WB_ENABLE
- IXGBE_TEOFF
- IXGBE_TEST_LEN
- IXGBE_TFCS
- IXGBE_TFCS_TXOFF
- IXGBE_TFCS_TXOFF0
- IXGBE_TFCS_TXOFF1
- IXGBE_TFCS_TXOFF2
- IXGBE_TFCS_TXOFF3
- IXGBE_TFCS_TXOFF4
- IXGBE_TFCS_TXOFF5
- IXGBE_TFCS_TXOFF6
- IXGBE_TFCS_TXOFF7
- IXGBE_TIC_DW
- IXGBE_TIC_DW2
- IXGBE_TIMADJH
- IXGBE_TIMADJL
- IXGBE_TIMINCA
- IXGBE_TIPG
- IXGBE_TIPG_FIBER_DEFAULT
- IXGBE_TN_LASI_STATUS_REG
- IXGBE_TN_LASI_STATUS_TEMP_ALARM
- IXGBE_TORH
- IXGBE_TORL
- IXGBE_TPR
- IXGBE_TPT
- IXGBE_TQSM
- IXGBE_TQSMR
- IXGBE_TREG
- IXGBE_TRGTTIMH0
- IXGBE_TRGTTIMH1
- IXGBE_TRGTTIML0
- IXGBE_TRGTTIML1
- IXGBE_TRY_LINK_TIMEOUT
- IXGBE_TSAUXC
- IXGBE_TSAUXC_DISABLE_SYSTIME
- IXGBE_TSAUXC_DIS_TS_CLEAR
- IXGBE_TSAUXC_EN_CLK
- IXGBE_TSAUXC_EN_TT0
- IXGBE_TSAUXC_EN_TT1
- IXGBE_TSAUXC_SDP0_INT
- IXGBE_TSAUXC_ST0
- IXGBE_TSAUXC_SYNCLK
- IXGBE_TSIM
- IXGBE_TSIM_TXTS
- IXGBE_TSOFF
- IXGBE_TSSDP
- IXGBE_TSSDP_TS_SDP0_CLK0
- IXGBE_TSSDP_TS_SDP0_EN
- IXGBE_TSSDP_TS_SDP0_SEL_MASK
- IXGBE_TSYNCRXCTL
- IXGBE_TSYNCRXCTL_ENABLED
- IXGBE_TSYNCRXCTL_TSIP_UT_EN
- IXGBE_TSYNCRXCTL_TYPE_ALL
- IXGBE_TSYNCRXCTL_TYPE_EVENT_V2
- IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2
- IXGBE_TSYNCRXCTL_TYPE_L2_V2
- IXGBE_TSYNCRXCTL_TYPE_L4_V1
- IXGBE_TSYNCRXCTL_TYPE_MASK
- IXGBE_TSYNCRXCTL_VALID
- IXGBE_TSYNCTXCTL
- IXGBE_TSYNCTXCTL_ENABLED
- IXGBE_TSYNCTXCTL_VALID
- IXGBE_TS_HDR_LEN
- IXGBE_TWINAX_DEV
- IXGBE_TXBUFCTRL
- IXGBE_TXBUFDATA
- IXGBE_TXDATARDPTR
- IXGBE_TXDATAWRPTR
- IXGBE_TXDBUECC
- IXGBE_TXDBUEST
- IXGBE_TXDCTL
- IXGBE_TXDCTL_ENABLE
- IXGBE_TXDCTL_SWFLSH
- IXGBE_TXDCTL_WTHRESH_SHIFT
- IXGBE_TXDESCIC
- IXGBE_TXDESCIC_READY
- IXGBE_TXDESCRDPTR
- IXGBE_TXDESCWRPTR
- IXGBE_TXDGBCH
- IXGBE_TXDGBCL
- IXGBE_TXDGPC
- IXGBE_TXD_CMD
- IXGBE_TXD_CMD_DEXT
- IXGBE_TXD_CMD_EOP
- IXGBE_TXD_CMD_IC
- IXGBE_TXD_CMD_IFCS
- IXGBE_TXD_CMD_RS
- IXGBE_TXD_CMD_VLE
- IXGBE_TXD_POPTS_IXSM
- IXGBE_TXD_POPTS_TXSM
- IXGBE_TXD_STAT_DD
- IXGBE_TXLLQ
- IXGBE_TXPBSIZE
- IXGBE_TXPBSIZE_20KB
- IXGBE_TXPBSIZE_40KB
- IXGBE_TXPBSIZE_MAX
- IXGBE_TXPBSIZE_SHIFT
- IXGBE_TXPBTHRESH
- IXGBE_TXPKT_SIZE_MAX
- IXGBE_TXRDPTR
- IXGBE_TXRDWRPTR
- IXGBE_TXSTMPH
- IXGBE_TXSTMPL
- IXGBE_TXUSED
- IXGBE_TXWRPTR
- IXGBE_TX_CTXTDESC
- IXGBE_TX_DESC
- IXGBE_TX_DESC_SPECIAL_PRI_SHIFT
- IXGBE_TX_FLAGS_CC
- IXGBE_TX_FLAGS_CSUM
- IXGBE_TX_FLAGS_FCOE
- IXGBE_TX_FLAGS_HW_VLAN
- IXGBE_TX_FLAGS_IPSEC
- IXGBE_TX_FLAGS_IPV4
- IXGBE_TX_FLAGS_SW_VLAN
- IXGBE_TX_FLAGS_TSO
- IXGBE_TX_FLAGS_TSTAMP
- IXGBE_TX_FLAGS_VLAN
- IXGBE_TX_FLAGS_VLAN_MASK
- IXGBE_TX_FLAGS_VLAN_PRIO_MASK
- IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT
- IXGBE_TX_FLAGS_VLAN_SHIFT
- IXGBE_TX_PAD_ENABLE
- IXGBE_UTA
- IXGBE_VALIDATE_LINK_READY_TIMEOUT
- IXGBE_VFCTRL
- IXGBE_VFDCA_RXCTRL
- IXGBE_VFDCA_TXCTRL
- IXGBE_VFFRTIMER
- IXGBE_VFGORC_LSB
- IXGBE_VFGORC_MSB
- IXGBE_VFGOTC_LSB
- IXGBE_VFGOTC_MSB
- IXGBE_VFGPRC
- IXGBE_VFGPTC
- IXGBE_VFLINKS
- IXGBE_VFLRE
- IXGBE_VFLREC
- IXGBE_VFMAILBOX
- IXGBE_VFMAILBOX_ACK
- IXGBE_VFMAILBOX_PFACK
- IXGBE_VFMAILBOX_PFSTS
- IXGBE_VFMAILBOX_PFU
- IXGBE_VFMAILBOX_R2C_BITS
- IXGBE_VFMAILBOX_REQ
- IXGBE_VFMAILBOX_RSTD
- IXGBE_VFMAILBOX_RSTI
- IXGBE_VFMAILBOX_SIZE
- IXGBE_VFMAILBOX_VFU
- IXGBE_VFMBMEM
- IXGBE_VFMPRC
- IXGBE_VFMRQC
- IXGBE_VFMRQC_RSSEN
- IXGBE_VFMRQC_RSS_FIELD_IPV4
- IXGBE_VFMRQC_RSS_FIELD_IPV4_TCP
- IXGBE_VFMRQC_RSS_FIELD_IPV6
- IXGBE_VFMRQC_RSS_FIELD_IPV6_TCP
- IXGBE_VFPSRTYPE
- IXGBE_VFRDBAH
- IXGBE_VFRDBAL
- IXGBE_VFRDH
- IXGBE_VFRDLEN
- IXGBE_VFRDT
- IXGBE_VFRE
- IXGBE_VFRETA
- IXGBE_VFRE_ENABLE_ALL
- IXGBE_VFRSCCTL
- IXGBE_VFRSSRK
- IXGBE_VFRXDCTL
- IXGBE_VFRXMEMWRAP
- IXGBE_VFSRRCTL
- IXGBE_VFSTATUS
- IXGBE_VFTA
- IXGBE_VFTAVIND
- IXGBE_VFTDBAH
- IXGBE_VFTDBAL
- IXGBE_VFTDH
- IXGBE_VFTDLEN
- IXGBE_VFTDT
- IXGBE_VFTDWBAH
- IXGBE_VFTDWBAL
- IXGBE_VFTE
- IXGBE_VFTXDCTL
- IXGBE_VF_API_NEGOTIATE
- IXGBE_VF_DEF_QUEUE
- IXGBE_VF_GET_QUEUE
- IXGBE_VF_GET_QUEUES
- IXGBE_VF_GET_RETA
- IXGBE_VF_GET_RSS_KEY
- IXGBE_VF_INIT_TIMEOUT
- IXGBE_VF_IPSEC_ADD
- IXGBE_VF_IPSEC_DEL
- IXGBE_VF_IRQ_CLEAR_MASK
- IXGBE_VF_MAX_RX_QUEUES
- IXGBE_VF_MAX_TRAFFIC_CLASS
- IXGBE_VF_MAX_TX_QUEUES
- IXGBE_VF_MBX_INIT_DELAY
- IXGBE_VF_MBX_INIT_TIMEOUT
- IXGBE_VF_MC_TYPE_WORD
- IXGBE_VF_PERMADDR_MSG_LEN
- IXGBE_VF_RESET
- IXGBE_VF_RX_QUEUES
- IXGBE_VF_SET_LPE
- IXGBE_VF_SET_MACVLAN
- IXGBE_VF_SET_MAC_ADDR
- IXGBE_VF_SET_MULTICAST
- IXGBE_VF_SET_VLAN
- IXGBE_VF_TRANS_VLAN
- IXGBE_VF_TX_QUEUES
- IXGBE_VF_UPDATE_XCAST_MODE
- IXGBE_VLNCTRL
- IXGBE_VLNCTRL_CFI
- IXGBE_VLNCTRL_CFIEN
- IXGBE_VLNCTRL_VET
- IXGBE_VLNCTRL_VFE
- IXGBE_VLNCTRL_VME
- IXGBE_VLVF
- IXGBE_VLVFB
- IXGBE_VLVF_ENTRIES
- IXGBE_VLVF_VIEN
- IXGBE_VLVF_VLANID_MASK
- IXGBE_VMD_CTL
- IXGBE_VMD_CTL_VMDQ_EN
- IXGBE_VMD_CTL_VMDQ_FILTER
- IXGBE_VMECM
- IXGBE_VMOLR
- IXGBE_VMOLR_AUPE
- IXGBE_VMOLR_BAM
- IXGBE_VMOLR_MPE
- IXGBE_VMOLR_ROMPE
- IXGBE_VMOLR_ROPE
- IXGBE_VMOLR_UPE
- IXGBE_VMOLR_VPE
- IXGBE_VMRVLAN
- IXGBE_VMRVM
- IXGBE_VMTXSW
- IXGBE_VMVIR
- IXGBE_VMVIR_VLANA_DEFAULT
- IXGBE_VMVIR_VLANA_NEVER
- IXGBE_VPDDIAG0
- IXGBE_VPDDIAG1
- IXGBE_VTEIAC
- IXGBE_VTEIAM
- IXGBE_VTEICR
- IXGBE_VTEICS
- IXGBE_VTEIMC
- IXGBE_VTEIMS
- IXGBE_VTEITR
- IXGBE_VTIVAR
- IXGBE_VTIVAR_MISC
- IXGBE_VTRSCINT
- IXGBE_VT_CTL
- IXGBE_VT_CTL_DIS_DEFPL
- IXGBE_VT_CTL_POOL_MASK
- IXGBE_VT_CTL_POOL_SHIFT
- IXGBE_VT_CTL_REPLEN
- IXGBE_VT_CTL_VT_ENABLE
- IXGBE_VT_MSGINFO_MASK
- IXGBE_VT_MSGINFO_SHIFT
- IXGBE_VT_MSGTYPE_ACK
- IXGBE_VT_MSGTYPE_CTS
- IXGBE_VT_MSGTYPE_NACK
- IXGBE_VXLANCTRL
- IXGBE_VXLANCTRL_ALL_UDPPORT_MASK
- IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK
- IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT
- IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK
- IXGBE_WQBR_RX
- IXGBE_WQBR_TX
- IXGBE_WRITE_FLUSH
- IXGBE_WRITE_REG
- IXGBE_WRITE_REG64
- IXGBE_WRITE_REG_ARRAY
- IXGBE_WRITE_REG_BE32
- IXGBE_WUC
- IXGBE_WUC_PME_EN
- IXGBE_WUC_PME_STATUS
- IXGBE_WUC_WKEN
- IXGBE_WUFC
- IXGBE_WUFC_ALL_FILTERS
- IXGBE_WUFC_ARP
- IXGBE_WUFC_BC
- IXGBE_WUFC_EX
- IXGBE_WUFC_EXT_FLX_FILTERS
- IXGBE_WUFC_FLX0
- IXGBE_WUFC_FLX1
- IXGBE_WUFC_FLX2
- IXGBE_WUFC_FLX3
- IXGBE_WUFC_FLX4
- IXGBE_WUFC_FLX5
- IXGBE_WUFC_FLX_FILTERS
- IXGBE_WUFC_FLX_OFFSET
- IXGBE_WUFC_IGNORE_TCO
- IXGBE_WUFC_IPV4
- IXGBE_WUFC_IPV6
- IXGBE_WUFC_LNKC
- IXGBE_WUFC_MAG
- IXGBE_WUFC_MC
- IXGBE_WUFC_MNG
- IXGBE_WUPL
- IXGBE_WUPL_LENGTH_MASK
- IXGBE_WUPM
- IXGBE_WUS
- IXGBE_WUS_ARP
- IXGBE_WUS_BC
- IXGBE_WUS_EX
- IXGBE_WUS_FLX0
- IXGBE_WUS_FLX1
- IXGBE_WUS_FLX2
- IXGBE_WUS_FLX3
- IXGBE_WUS_FLX4
- IXGBE_WUS_FLX5
- IXGBE_WUS_FLX_FILTERS
- IXGBE_WUS_IPV4
- IXGBE_WUS_IPV6
- IXGBE_WUS_LNKC
- IXGBE_WUS_MAG
- IXGBE_WUS_MC
- IXGBE_WUS_MNG
- IXGBE_X540_MAX_RX_QUEUES
- IXGBE_X540_MAX_TX_QUEUES
- IXGBE_X540_MC_TBL_SIZE
- IXGBE_X540_RAR_ENTRIES
- IXGBE_X540_RX_PB_SIZE
- IXGBE_X540_VFT_TBL_SIZE
- IXGBE_X540_VF_DEVICE_ID
- IXGBE_X550_BASE_PERIOD
- IXGBE_X557_LED_MANUAL_SET_MASK
- IXGBE_X557_LED_PROVISIONING
- IXGBE_X557_MAX_LED_INDEX
- IXGBE_XAUI_D
- IXGBE_XAUI_DC
- IXGBE_XDP_CONSUMED
- IXGBE_XDP_PASS
- IXGBE_XDP_REDIR
- IXGBE_XDP_TX
- IXGBE_XEC
- IXGBE_XENPAK_LASI_LINK_STATUS_ALARM
- IXGBE_XPCSS
- IXGB_AIS
- IXGB_ALL_RAR_ENTRIES
- IXGB_APAE
- IXGB_ARD
- IXGB_BCM8704_USER_CTRL_REG
- IXGB_BCM8704_USER_CTRL_REG_VAL
- IXGB_BCM8704_USER_DEV3_ADDR
- IXGB_BCM8704_USER_PMD_TX_CTRL_REG
- IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL
- IXGB_BPRCH
- IXGB_BPRCL
- IXGB_BPTCH
- IXGB_BPTCL
- IXGB_CB_LENGTH
- IXGB_CONTEXT_DESC
- IXGB_CONTEXT_DESC_CMD_IDE
- IXGB_CONTEXT_DESC_CMD_IP
- IXGB_CONTEXT_DESC_CMD_RS
- IXGB_CONTEXT_DESC_CMD_TCP
- IXGB_CONTEXT_DESC_CMD_TSE
- IXGB_CONTEXT_DESC_STATUS_DD
- IXGB_CONTEXT_DESC_TYPE
- IXGB_CRCERRS
- IXGB_CTRL0
- IXGB_CTRL0_CMDC
- IXGB_CTRL0_JFE
- IXGB_CTRL0_LRST
- IXGB_CTRL0_MDCS
- IXGB_CTRL0_RPE
- IXGB_CTRL0_RST
- IXGB_CTRL0_SDP0
- IXGB_CTRL0_SDP0_DIR
- IXGB_CTRL0_SDP1
- IXGB_CTRL0_SDP1_DIR
- IXGB_CTRL0_SDP2
- IXGB_CTRL0_SDP2_DIR
- IXGB_CTRL0_SDP3
- IXGB_CTRL0_SDP3_DIR
- IXGB_CTRL0_TPE
- IXGB_CTRL0_VME
- IXGB_CTRL0_XLE
- IXGB_CTRL1
- IXGB_CTRL1_EE_RST
- IXGB_CTRL1_GPI0_EN
- IXGB_CTRL1_GPI1_EN
- IXGB_CTRL1_GPI2_EN
- IXGB_CTRL1_GPI3_EN
- IXGB_CTRL1_PCIXHM_1_2
- IXGB_CTRL1_PCIXHM_3_4
- IXGB_CTRL1_PCIXHM_5_8
- IXGB_CTRL1_PCIXHM_7_8
- IXGB_CTRL1_PCIXHM_MASK
- IXGB_CTRL1_RO_DIS
- IXGB_CTRL1_SDP4
- IXGB_CTRL1_SDP4_DIR
- IXGB_CTRL1_SDP5
- IXGB_CTRL1_SDP5_DIR
- IXGB_CTRL1_SDP6
- IXGB_CTRL1_SDP6_DIR
- IXGB_CTRL1_SDP7
- IXGB_CTRL1_SDP7_DIR
- IXGB_DC
- IXGB_DELAY_AFTER_EE_RESET
- IXGB_DELAY_AFTER_RESET
- IXGB_DELAY_BEFORE_RESET
- IXGB_DELAY_USECS_AFTER_LINK_RESET
- IXGB_DESC_UNUSED
- IXGB_DEVICE_ID_82597EX
- IXGB_DEVICE_ID_82597EX_CX4
- IXGB_DEVICE_ID_82597EX_LR
- IXGB_DEVICE_ID_82597EX_SR
- IXGB_DIAG_PHY_ADDR
- IXGB_ECBC
- IXGB_EECD
- IXGB_EECD_CS
- IXGB_EECD_DI
- IXGB_EECD_DO
- IXGB_EECD_FWE_DIS
- IXGB_EECD_FWE_EN
- IXGB_EECD_FWE_MASK
- IXGB_EECD_SK
- IXGB_EEPROM_SIZE
- IXGB_FCRTH
- IXGB_FCRTL
- IXGB_FCRTL_XONE
- IXGB_FFLT
- IXGB_FFMT
- IXGB_FTVT
- IXGB_GET_DESC
- IXGB_GET_STAT
- IXGB_GORCH
- IXGB_GORCL
- IXGB_GOTCH
- IXGB_GOTCL
- IXGB_GPRCH
- IXGB_GPRCL
- IXGB_GPTCH
- IXGB_GPTCL
- IXGB_IBIC
- IXGB_ICBC
- IXGB_ICR
- IXGB_ICS
- IXGB_IMC
- IXGB_IMS
- IXGB_INT_AUTOSCAN
- IXGB_INT_GPI0
- IXGB_INT_GPI1
- IXGB_INT_GPI2
- IXGB_INT_GPI3
- IXGB_INT_LSC
- IXGB_INT_RXDMT0
- IXGB_INT_RXO
- IXGB_INT_RXSEQ
- IXGB_INT_RXT0
- IXGB_INT_TXDW
- IXGB_INT_TXQE
- IXGB_JPRCH
- IXGB_JPRCL
- IXGB_JPTCH
- IXGB_JPTCL
- IXGB_LFC
- IXGB_MACA
- IXGB_MAX_DATA_PER_TXD
- IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS
- IXGB_MAX_INTR
- IXGB_MAX_JUMBO_FRAME_SIZE
- IXGB_MAX_NIC
- IXGB_MAX_NUM_MULTICAST_ADDRESSES
- IXGB_MAX_PHY_ADDRESS
- IXGB_MAX_PHY_DEV_TYPE
- IXGB_MAX_PHY_REG_ADDRESS
- IXGB_MAX_TXD_PWR
- IXGB_MCFRC
- IXGB_MCFTC
- IXGB_MC_TBL_SIZE
- IXGB_MEMCPY
- IXGB_MEMORY_REGISTER_BASE_ADDRESS
- IXGB_MFS
- IXGB_MFS_SHIFT
- IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS
- IXGB_MPC
- IXGB_MPRCH
- IXGB_MPRCL
- IXGB_MPTCH
- IXGB_MPTCL
- IXGB_MSCA
- IXGB_MSCA_ADDR_CYCLE
- IXGB_MSCA_DEV_TYPE_MASK
- IXGB_MSCA_DEV_TYPE_SHIFT
- IXGB_MSCA_MDI_COMMAND
- IXGB_MSCA_MDI_IN_PROG_EN
- IXGB_MSCA_NEW_PROTOCOL
- IXGB_MSCA_NP_ADDR_MASK
- IXGB_MSCA_NP_ADDR_SHIFT
- IXGB_MSCA_OLD_PROTOCOL
- IXGB_MSCA_OP_CODE_MASK
- IXGB_MSCA_OP_CODE_SHIFT
- IXGB_MSCA_PHY_ADDR_MASK
- IXGB_MSCA_PHY_ADDR_SHIFT
- IXGB_MSCA_READ
- IXGB_MSCA_READ_AUTOINC
- IXGB_MSCA_ST_CODE_MASK
- IXGB_MSCA_ST_CODE_SHIFT
- IXGB_MSCA_WRITE
- IXGB_MSRWD
- IXGB_MSRWD_READ_DATA_MASK
- IXGB_MSRWD_READ_DATA_SHIFT
- IXGB_MSRWD_WRITE_DATA_MASK
- IXGB_MSRWD_WRITE_DATA_SHIFT
- IXGB_MTA
- IXGB_NETDEV_STAT
- IXGB_OPTICAL_PHY_ADDR
- IXGB_PAP
- IXGB_PAP_TXPC_MASK
- IXGB_PAP_TXPV_10G
- IXGB_PAP_TXPV_1G
- IXGB_PAP_TXPV_2G
- IXGB_PAP_TXPV_3G
- IXGB_PAP_TXPV_4G
- IXGB_PAP_TXPV_5G
- IXGB_PAP_TXPV_6G
- IXGB_PAP_TXPV_7G
- IXGB_PAP_TXPV_8G
- IXGB_PAP_TXPV_9G
- IXGB_PAP_TXPV_MASK
- IXGB_PAP_TXPV_WAN
- IXGB_PARAM
- IXGB_PARAM_INIT
- IXGB_PCSC1
- IXGB_PCSC1_LOOPBACK
- IXGB_PCSC2
- IXGB_PCSC2_PCS_TYPE_10GBX
- IXGB_PCSC2_PCS_TYPE_MASK
- IXGB_PCSS1
- IXGB_PCSS1_LOCAL_FAULT
- IXGB_PCSS1_RX_LINK_STATUS
- IXGB_PCSS2
- IXGB_PCSS2_10GBR
- IXGB_PCSS2_10GBW
- IXGB_PCSS2_10GBX
- IXGB_PCSS2_DEV_PRES
- IXGB_PCSS2_DEV_PRES_MASK
- IXGB_PCSS2_RX_LF
- IXGB_PCSS2_TX_LF
- IXGB_PFRC
- IXGB_PFTC
- IXGB_PHY_ADDRESS
- IXGB_PLT64C
- IXGB_RA
- IXGB_RAH
- IXGB_RAH_ASEL_DEST
- IXGB_RAH_ASEL_MASK
- IXGB_RAH_ASEL_SRC
- IXGB_RAH_AV
- IXGB_RAIDC
- IXGB_RAIDC_DELAY_MASK
- IXGB_RAIDC_DELAY_SHIFT
- IXGB_RAIDC_EN
- IXGB_RAIDC_HIGHTHRS_MASK
- IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND
- IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND
- IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND
- IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND
- IXGB_RAIDC_POLL_MASK
- IXGB_RAIDC_POLL_SHIFT
- IXGB_RAIDC_RXT_GATE
- IXGB_RAL
- IXGB_RAR_ENTRIES
- IXGB_RCTL
- IXGB_RCTL_BAM
- IXGB_RCTL_BSIZE_16384
- IXGB_RCTL_BSIZE_2048
- IXGB_RCTL_BSIZE_4096
- IXGB_RCTL_BSIZE_8192
- IXGB_RCTL_BSIZE_MASK
- IXGB_RCTL_CFF
- IXGB_RCTL_CFI
- IXGB_RCTL_CFIEN
- IXGB_RCTL_IDLE_RX_UNIT
- IXGB_RCTL_MC_ONLY
- IXGB_RCTL_MO_43_32
- IXGB_RCTL_MO_45_34
- IXGB_RCTL_MO_46_35
- IXGB_RCTL_MO_47_36
- IXGB_RCTL_MO_MASK
- IXGB_RCTL_MO_SHIFT
- IXGB_RCTL_MPE
- IXGB_RCTL_RDMTS_1_2
- IXGB_RCTL_RDMTS_1_4
- IXGB_RCTL_RDMTS_1_8
- IXGB_RCTL_RDMTS_MASK
- IXGB_RCTL_RPDA_MASK
- IXGB_RCTL_RPDA_MC_MAC
- IXGB_RCTL_RXEN
- IXGB_RCTL_SBP
- IXGB_RCTL_SECRC
- IXGB_RCTL_UPE
- IXGB_RCTL_VFE
- IXGB_RDBAH
- IXGB_RDBAL
- IXGB_RDH
- IXGB_RDLEN
- IXGB_RDT
- IXGB_RDTR
- IXGB_RDT_FPDB
- IXGB_READ_REG
- IXGB_READ_REG_ARRAY
- IXGB_REG_DUMP_LEN
- IXGB_REQ_RX_DESCRIPTOR_MULTIPLE
- IXGB_REQ_TX_DESCRIPTOR_MULTIPLE
- IXGB_RFC
- IXGB_RJC
- IXGB_RLEC
- IXGB_RNBC
- IXGB_ROC
- IXGB_RUC
- IXGB_RXBUFFER_16384
- IXGB_RXBUFFER_2048
- IXGB_RXBUFFER_4096
- IXGB_RXBUFFER_8192
- IXGB_RXCSUM
- IXGB_RXCSUM_IPOFL
- IXGB_RXCSUM_TUOFL
- IXGB_RXDCTL
- IXGB_RXDCTL_HTHRESH_MASK
- IXGB_RXDCTL_HTHRESH_SHIFT
- IXGB_RXDCTL_PTHRESH_MASK
- IXGB_RXDCTL_PTHRESH_SHIFT
- IXGB_RXDCTL_WTHRESH_MASK
- IXGB_RXDCTL_WTHRESH_SHIFT
- IXGB_RX_BUFFER_WRITE
- IXGB_RX_DESC
- IXGB_RX_DESC_ERRORS_CE
- IXGB_RX_DESC_ERRORS_IPE
- IXGB_RX_DESC_ERRORS_P
- IXGB_RX_DESC_ERRORS_RXE
- IXGB_RX_DESC_ERRORS_SE
- IXGB_RX_DESC_ERRORS_TCPE
- IXGB_RX_DESC_SPECIAL_PRI_MASK
- IXGB_RX_DESC_SPECIAL_PRI_SHIFT
- IXGB_RX_DESC_SPECIAL_VLAN_MASK
- IXGB_RX_DESC_STATUS_DD
- IXGB_RX_DESC_STATUS_EOP
- IXGB_RX_DESC_STATUS_IPCS
- IXGB_RX_DESC_STATUS_IXSM
- IXGB_RX_DESC_STATUS_PIF
- IXGB_RX_DESC_STATUS_TCPCS
- IXGB_RX_DESC_STATUS_VP
- IXGB_STAT
- IXGB_STATS
- IXGB_STATS_LEN
- IXGB_STATUS
- IXGB_STATUS_AIP
- IXGB_STATUS_BUS64
- IXGB_STATUS_LU
- IXGB_STATUS_PCIX_MODE
- IXGB_STATUS_PCIX_SPD_100
- IXGB_STATUS_PCIX_SPD_133
- IXGB_STATUS_PCIX_SPD_66
- IXGB_STATUS_PCIX_SPD_MASK
- IXGB_STATUS_PCI_SPD
- IXGB_STATUS_RES
- IXGB_STATUS_REV_ID_MASK
- IXGB_STATUS_REV_ID_SHIFT
- IXGB_STATUS_RIE
- IXGB_STATUS_RIS
- IXGB_STATUS_RLF
- IXGB_STATUS_RRF
- IXGB_STATUS_TXOFF
- IXGB_STATUS_XAUIME
- IXGB_SUBDEVICE_ID_7036
- IXGB_SUBDEVICE_ID_A00C
- IXGB_SUBDEVICE_ID_A01C
- IXGB_SUBDEVICE_ID_A01F
- IXGB_SUBDEVICE_ID_A11F
- IXGB_SUN_PHY_ADDRESS
- IXGB_SUN_PHY_RESET_DELAY
- IXGB_TCTL
- IXGB_TCTL_IDLE_TX_UNIT
- IXGB_TCTL_TCE
- IXGB_TCTL_TPDE
- IXGB_TCTL_TXEN
- IXGB_TDBAH
- IXGB_TDBAL
- IXGB_TDH
- IXGB_TDLEN
- IXGB_TDT
- IXGB_TIDV
- IXGB_TORH
- IXGB_TORL
- IXGB_TOTH
- IXGB_TOTL
- IXGB_TPRH
- IXGB_TPRL
- IXGB_TPTH
- IXGB_TPTL
- IXGB_TSCTC
- IXGB_TSCTFC
- IXGB_TSPMT
- IXGB_TSPMT_TSMT_MASK
- IXGB_TSPMT_TSPBP_MASK
- IXGB_TSPMT_TSPBP_SHIFT
- IXGB_TXDCTL
- IXGB_TXDCTL_HTHRESH_MASK
- IXGB_TXDCTL_HTHRESH_SHIFT
- IXGB_TXDCTL_PTHRESH_MASK
- IXGB_TXDCTL_WTHRESH_MASK
- IXGB_TXDCTL_WTHRESH_SHIFT
- IXGB_TX_DESC
- IXGB_TX_DESC_CMD_EOP
- IXGB_TX_DESC_CMD_IDE
- IXGB_TX_DESC_CMD_MASK
- IXGB_TX_DESC_CMD_RS
- IXGB_TX_DESC_CMD_SHIFT
- IXGB_TX_DESC_CMD_TSE
- IXGB_TX_DESC_CMD_VLE
- IXGB_TX_DESC_LENGTH_MASK
- IXGB_TX_DESC_POPTS_IXSM
- IXGB_TX_DESC_POPTS_TXSM
- IXGB_TX_DESC_SPECIAL_PRI_SHIFT
- IXGB_TX_DESC_STATUS_DD
- IXGB_TX_DESC_TYPE
- IXGB_TX_DESC_TYPE_MASK
- IXGB_TX_DESC_TYPE_SHIFT
- IXGB_TX_FLAGS_CSUM
- IXGB_TX_FLAGS_TSO
- IXGB_TX_FLAGS_VLAN
- IXGB_UCCR
- IXGB_UPRCH
- IXGB_UPRCL
- IXGB_UPTCH
- IXGB_UPTCL
- IXGB_VFTA
- IXGB_VLAN_FILTER_TBL_SIZE
- IXGB_VPRCH
- IXGB_VPRCL
- IXGB_VPTCH
- IXGB_VPTCL
- IXGB_WRITE_FLUSH
- IXGB_WRITE_REG
- IXGB_WRITE_REG_ARRAY
- IXGB_WUFC
- IXGB_WUS
- IXGB_XAUII_PHY_ADDR
- IXGB_XOFFRXC
- IXGB_XOFFTXC
- IXGB_XONRXC
- IXGB_XONTXC
- IXGB_XPCSS
- IXGB_XPCSS_ALIGN_STATUS
- IXGB_XPCSS_LANE_0_SYNC
- IXGB_XPCSS_LANE_1_SYNC
- IXGB_XPCSS_LANE_2_SYNC
- IXGB_XPCSS_LANE_3_SYNC
- IXGB_XPCSS_PATTERN_TEST
- IXGB_XPCSTC
- IXGB_XPCSTC_BERT_PSZ_1028
- IXGB_XPCSTC_BERT_PSZ_68
- IXGB_XPCSTC_BERT_PSZ_INF
- IXGB_XPCSTC_BERT_PSZ_MASK
- IXGB_XPCSTC_BERT_PSZ_SHIFT
- IXGB_XPCSTC_BERT_SST
- IXGB_XPCSTC_BERT_TRIG
- IXM_IXANY
- IXOFF
- IXON
- IXP425_A0
- IXP425_B0
- IXP42X_FEATURE_MASK
- IXP42X_PROCESSOR_ID_MASK
- IXP42X_PROCESSOR_ID_VALUE
- IXP43X_FEATURE_MASK
- IXP43X_PROCESSOR_ID_MASK
- IXP43X_PROCESSOR_ID_VALUE
- IXP465_AD
- IXP46X_FEATURE_MASK
- IXP46X_PROCESSOR_ID_MASK
- IXP46X_PROCESSOR_ID_VALUE
- IXP4XX_ETH_NPEA
- IXP4XX_ETH_NPEB
- IXP4XX_ETH_NPEC
- IXP4XX_EXP_BUS_ADDR_T
- IXP4XX_EXP_BUS_BASE
- IXP4XX_EXP_BUS_BASE_PHYS
- IXP4XX_EXP_BUS_BYTE_EN
- IXP4XX_EXP_BUS_BYTE_RD16
- IXP4XX_EXP_BUS_CS_EN
- IXP4XX_EXP_BUS_CYCLES
- IXP4XX_EXP_BUS_CYCLES_HPI
- IXP4XX_EXP_BUS_CYCLES_INTEL
- IXP4XX_EXP_BUS_CYCLES_MOTOROLA
- IXP4XX_EXP_BUS_END
- IXP4XX_EXP_BUS_HOLD_T
- IXP4XX_EXP_BUS_HRDY_POL
- IXP4XX_EXP_BUS_MUX_EN
- IXP4XX_EXP_BUS_RECOVERY_T
- IXP4XX_EXP_BUS_SETUP_T
- IXP4XX_EXP_BUS_SIZE
- IXP4XX_EXP_BUS_SPLT_EN
- IXP4XX_EXP_BUS_STROBE_T
- IXP4XX_EXP_BUS_WR_EN
- IXP4XX_EXP_CFG0
- IXP4XX_EXP_CFG0_OFFSET
- IXP4XX_EXP_CFG1
- IXP4XX_EXP_CFG1_OFFSET
- IXP4XX_EXP_CFG2
- IXP4XX_EXP_CFG2_OFFSET
- IXP4XX_EXP_CFG3
- IXP4XX_EXP_CFG3_OFFSET
- IXP4XX_EXP_CFG_BASE_PHYS
- IXP4XX_EXP_CFG_BASE_VIRT
- IXP4XX_EXP_CFG_REGION_SIZE
- IXP4XX_EXP_CS0
- IXP4XX_EXP_CS0_OFFSET
- IXP4XX_EXP_CS1
- IXP4XX_EXP_CS1_OFFSET
- IXP4XX_EXP_CS2
- IXP4XX_EXP_CS2_OFFSET
- IXP4XX_EXP_CS3
- IXP4XX_EXP_CS3_OFFSET
- IXP4XX_EXP_CS4
- IXP4XX_EXP_CS4_OFFSET
- IXP4XX_EXP_CS5
- IXP4XX_EXP_CS5_OFFSET
- IXP4XX_EXP_CS6
- IXP4XX_EXP_CS6_OFFSET
- IXP4XX_EXP_CS7
- IXP4XX_EXP_CS7_OFFSET
- IXP4XX_EXP_REG
- IXP4XX_EthA_BASE_PHYS
- IXP4XX_EthA_BASE_VIRT
- IXP4XX_EthB1_BASE_PHYS
- IXP4XX_EthB1_BASE_VIRT
- IXP4XX_EthB2_BASE_PHYS
- IXP4XX_EthB2_BASE_VIRT
- IXP4XX_EthB3_BASE_PHYS
- IXP4XX_EthB3_BASE_VIRT
- IXP4XX_EthB_BASE_PHYS
- IXP4XX_EthB_BASE_VIRT
- IXP4XX_EthC_BASE_PHYS
- IXP4XX_EthC_BASE_VIRT
- IXP4XX_FEATURE_AAL
- IXP4XX_FEATURE_AES
- IXP4XX_FEATURE_DES
- IXP4XX_FEATURE_ECC_TIMESYNC
- IXP4XX_FEATURE_HASH
- IXP4XX_FEATURE_HDLC
- IXP4XX_FEATURE_HSS
- IXP4XX_FEATURE_NPEA_ETH
- IXP4XX_FEATURE_NPEB_ETH0
- IXP4XX_FEATURE_NPEB_ETH_1_TO_3
- IXP4XX_FEATURE_NPEC_ETH
- IXP4XX_FEATURE_PCI
- IXP4XX_FEATURE_RCOMP
- IXP4XX_FEATURE_RESET_NPEA
- IXP4XX_FEATURE_RESET_NPEB
- IXP4XX_FEATURE_RESET_NPEC
- IXP4XX_FEATURE_RSA
- IXP4XX_FEATURE_USB_DEVICE
- IXP4XX_FEATURE_USB_HOST
- IXP4XX_FEATURE_UTOPIA
- IXP4XX_FEATURE_UTOPIA_PHY_LIMIT
- IXP4XX_FEATURE_XSCALE_MAX_FREQ
- IXP4XX_FLASH_DEFAULT
- IXP4XX_FLASH_WRITABLE
- IXP4XX_FLASH_WRITE
- IXP4XX_GPIO_BASE_PHYS
- IXP4XX_GPIO_BASE_VIRT
- IXP4XX_GPIO_CLK_0
- IXP4XX_GPIO_CLK_1
- IXP4XX_GPIO_IRQ
- IXP4XX_GPIO_STYLE_ACTIVE_HIGH
- IXP4XX_GPIO_STYLE_ACTIVE_LOW
- IXP4XX_GPIO_STYLE_FALLING_EDGE
- IXP4XX_GPIO_STYLE_MASK
- IXP4XX_GPIO_STYLE_RISING_EDGE
- IXP4XX_GPIO_STYLE_SIZE
- IXP4XX_GPIO_STYLE_TRANSITIONAL
- IXP4XX_I2C_BASE_PHYS
- IXP4XX_I2C_BASE_VIRT
- IXP4XX_ICEEN
- IXP4XX_ICFH
- IXP4XX_ICFP
- IXP4XX_ICFP2
- IXP4XX_ICHR
- IXP4XX_ICIH
- IXP4XX_ICIP
- IXP4XX_ICIP2
- IXP4XX_ICLR
- IXP4XX_ICLR2
- IXP4XX_ICMR
- IXP4XX_ICMR2
- IXP4XX_ICPR
- IXP4XX_ICPR2
- IXP4XX_INTC_BASE_PHYS
- IXP4XX_INTC_BASE_VIRT
- IXP4XX_NPEA_BASE_PHYS
- IXP4XX_NPEB_BASE_PHYS
- IXP4XX_NPEC_BASE_PHYS
- IXP4XX_OSRT1
- IXP4XX_OSRT1_OFFSET
- IXP4XX_OSRT2
- IXP4XX_OSRT2_OFFSET
- IXP4XX_OSST
- IXP4XX_OSST_OFFSET
- IXP4XX_OSST_TIMER_1_PEND
- IXP4XX_OSST_TIMER_2_PEND
- IXP4XX_OSST_TIMER_TS_PEND
- IXP4XX_OSST_TIMER_WARM_RESET
- IXP4XX_OSST_TIMER_WDOG_PEND
- IXP4XX_OST1
- IXP4XX_OST1_OFFSET
- IXP4XX_OST2
- IXP4XX_OST2_OFFSET
- IXP4XX_OSTS
- IXP4XX_OSTS_OFFSET
- IXP4XX_OST_DISABLED
- IXP4XX_OST_ENABLE
- IXP4XX_OST_ONE_SHOT
- IXP4XX_OST_RELOAD_MASK
- IXP4XX_OSWE
- IXP4XX_OSWE_OFFSET
- IXP4XX_OSWK
- IXP4XX_OSWK_OFFSET
- IXP4XX_OSWT
- IXP4XX_OSWT_OFFSET
- IXP4XX_PCI_CFG_BASE_PHYS
- IXP4XX_PCI_CFG_BASE_VIRT
- IXP4XX_PCI_CFG_REGION_SIZE
- IXP4XX_PCI_CSR
- IXP4XX_PCI_NP_CBE_BESL
- IXP4XX_PERIPHERAL_BASE_PHYS
- IXP4XX_PERIPHERAL_BASE_VIRT
- IXP4XX_PERIPHERAL_BUS_CLOCK
- IXP4XX_PERIPHERAL_REGION_SIZE
- IXP4XX_PMU_BASE_PHYS
- IXP4XX_PMU_BASE_VIRT
- IXP4XX_QMGR_BASE_PHYS
- IXP4XX_QMGR_H
- IXP4XX_REG_GPCLK
- IXP4XX_REG_GPDBSEL
- IXP4XX_REG_GPIN
- IXP4XX_REG_GPIS
- IXP4XX_REG_GPIT1
- IXP4XX_REG_GPIT2
- IXP4XX_REG_GPOE
- IXP4XX_REG_GPOUT
- IXP4XX_SSP_BASE_PHYS
- IXP4XX_SSP_BASE_VIRT
- IXP4XX_TIMER_BASE_PHYS
- IXP4XX_TIMER_BASE_VIRT
- IXP4XX_TIMER_FREQ
- IXP4XX_TIMER_REG
- IXP4XX_TIMESYNC_BASE_PHYS
- IXP4XX_TIMESYNC_BASE_VIRT
- IXP4XX_UART1_BASE_PHYS
- IXP4XX_UART1_BASE_VIRT
- IXP4XX_UART2_BASE_PHYS
- IXP4XX_UART2_BASE_VIRT
- IXP4XX_UART_XTAL
- IXP4XX_USB_BASE_PHYS
- IXP4XX_USB_BASE_VIRT
- IXP4XX_WDT_COUNT_ENABLE
- IXP4XX_WDT_IRQ_ENABLE
- IXP4XX_WDT_KEY
- IXP4XX_WDT_RESET_ENABLE
- IXP_POSTFIX
- IXR_ALL_MASK
- IXR_DMA_DONE_MASK
- IXR_D_P_DONE_MASK
- IXR_ERROR_FLAGS_MASK
- IXR_FPGA_DONE_MASK
- IXR_PCFG_DONE_MASK
- IXSIZE
- IXXAT_PCI_DEVICE_ID
- IXXAT_PCI_SUB_SYS_ID
- IXXAT_PCI_VENDOR_ID
- IX_REG
- IX_REG_READ
- IX_REG_SET_2
- IX_REG_SET_N
- IX_REG_UPDATE_2
- IX_REG_UPDATE_N
- I_0
- I_ADDA_UL_CH1
- I_ADDA_UL_CH2
- I_ADDRESS
- I_BDEV
- I_BRKINT
- I_BUSPWR
- I_CACHEOP_SFT
- I_CACHESEL_SFT
- I_CACHE_SPEC
- I_CACHE_STRIDE_SHIFT
- I_CHIPACTIVE
- I_CLEAR
- I_CLOCK_H
- I_CLOCK_L
- I_CREATING
- I_CUSTOMEROV_SET
- I_CUT_VERSION
- I_DATA_H
- I_DATA_H_ACK0
- I_DATA_H_ACK1
- I_DATA_H_NOP
- I_DATA_H_READ
- I_DATA_L
- I_DATA_L_NOP
- I_DATA_SEM_NORMAL
- I_DATA_SEM_OTHER
- I_DATA_SEM_QUOTA
- I_DE
- I_DEH_N_ENTRY_FILE_NAME_LENGTH
- I_DIO_WAKEUP
- I_DIRTY
- I_DIRTY_ALL
- I_DIRTY_DATASYNC
- I_DIRTY_INODE
- I_DIRTY_PAGES
- I_DIRTY_SYNC
- I_DIRTY_TIME
- I_DIRTY_TIME_EXPIRED
- I_DL1_CH1
- I_DL1_CH2
- I_DL2_CH1
- I_DL2_CH2
- I_DL3_CH1
- I_DL3_CH2
- I_DMA
- I_DRIVER
- I_END
- I_ERRORS
- I_FD_SFT
- I_FFMT_SFT
- I_FMA_FFMT_SFT
- I_FMA_FUNC_SFT
- I_FRAME
- I_FREEING
- I_FR_SFT
- I_FS_SFT
- I_FT_SFT
- I_FUNC_SFT
- I_GAIN1_OUT_CH1
- I_GAIN1_OUT_CH2
- I_GAIN2_OUT_CH1
- I_GAIN2_OUT_CH2
- I_GATE
- I_HMB_FC_CHANGE
- I_HMB_FC_STATE
- I_HMB_FRAME_IND
- I_HMB_HOST_INT
- I_HMB_SW0
- I_HMB_SW1
- I_HMB_SW2
- I_HMB_SW3
- I_HMB_SW_MASK
- I_HMB_SW_SHIFT
- I_I2S0_CH1
- I_I2S0_CH2
- I_I2S2_CH1
- I_I2S2_CH2
- I_ICRNL
- I_IGNBRK
- I_IGNCR
- I_IGNPAR
- I_IMAXBEL
- I_IMM_SFT
- I_INDICATOR
- I_INLCR
- I_INPCK
- I_IOE2
- I_ISTRIP
- I_ISUB_CONTROL
- I_IUCLC
- I_IUTF8
- I_IXANY
- I_IXOFF
- I_IXON
- I_JTARGET_SFT
- I_K_KEY_IN_ITEM
- I_LCOEF_RBPS
- I_LCOEF_RRANDIOPS
- I_LCOEF_RSEQIOPS
- I_LCOEF_WBPS
- I_LCOEF_WRANDIOPS
- I_LCOEF_WSEQIOPS
- I_LINKABLE
- I_MSII_BASE_HI
- I_MSII_BASE_LO
- I_MSII_CAPABILITIES
- I_MSII_CONTROL
- I_MUTEX
- I_MUTEX_CHILD
- I_MUTEX_NONDIR2
- I_MUTEX_NORMAL
- I_MUTEX_PARENT
- I_MUTEX_PARENT2
- I_MUTEX_XATTR
- I_NEED_ONE
- I_NEW
- I_OPCODE_SFT
- I_OPCODE_mskCOP0
- I_OPCODE_mskRa
- I_OPCODE_mskRb
- I_OPCODE_mskRt
- I_OPCODE_mskbit1014
- I_OPCODE_mskbit69
- I_OPCODE_off
- I_OPCODE_offCOP0
- I_OPCODE_offRa
- I_OPCODE_offRb
- I_OPCODE_offRt
- I_OPCODE_offbit1014
- I_OPCODE_offbit69
- I_OVL_INUSE
- I_PAL_NICAM
- I_PAL_NICAM_MONO
- I_PARMRK
- I_PC
- I_PCMCIA_XU
- I_PCM_1_CAP_CH1
- I_PCM_1_CAP_CH2
- I_PCM_2_CAP_CH1
- I_PCM_2_CAP_CH2
- I_PD
- I_PLL_FBDIV_SET
- I_POS_UNFM_SIZE
- I_RD_OOSYNC
- I_RD_SFT
- I_REFERENCED
- I_RESET
- I_RESET_B_SET
- I_RE_SFT
- I_RF_TERM
- I_RI
- I_RO
- I_RS_SFT
- I_RTMUTEX
- I_RT_SFT
- I_RU
- I_RWLOCK
- I_RWSEM
- I_SBINT
- I_SEC
- I_SLEEP
- I_SMB_SW0
- I_SMB_SW1
- I_SMB_SW2
- I_SMB_SW3
- I_SMB_SW_MASK
- I_SMB_SW_SHIFT
- I_SPINLOCK
- I_SRESET
- I_SYNC
- I_T_NEXUS_LOSS_TIME
- I_UNFM_NUM
- I_VERSION_INCREMENT
- I_VERSION_QUERIED
- I_VERSION_QUERIED_SHIFT
- I_WB_SWITCH
- I_WF_TERM
- I_WILL_FREE
- I_WR_OOSYNC
- I_WW
- I_XI
- I_XMTDATA_AVAIL
- I_XU
- I_s3s1s2
- I_u1
- I_u1s2
- I_u1u2
- I_u1u2s3
- I_u1u2u3
- I_u2s3u1
- I_u2u1
- I_u2u1msb32msb3
- I_u2u1msb32u3
- I_u2u1msbdu3
- I_u2u1msbu3
- I_u2u1s3
- I_u2u1u3
- I_u3u1u2
- I_u3u2u1
- Ibit
- IbmVethMcastAddFilter
- IbmVethMcastClearFilterTable
- IbmVethMcastDisableFiltering
- IbmVethMcastDisableRecv
- IbmVethMcastEnableFiltering
- IbmVethMcastEnableRecv
- IbmVethMcastFilterEnableBit
- IbmVethMcastFilterModifyBit
- IbmVethMcastReceptionEnableBit
- IbmVethMcastReceptionModifyBit
- IbmVethMcastRemoveFilter
- Idrop
- Ifalse
- Ifstate
- IgnorePulse
- ImplicitOps
- InBound_SRB
- InByteDsp
- InLen
- InRangeLengthErrors
- InReg
- InWordDsp
- In_sync
- Inb
- InbandPage0_t
- InboundDoorbellReg
- IncSP
- Incoming
- IncorPolarity
- Index_Invalidate_I
- Index_Invalidate_SI
- Index_Load_Data_D
- Index_Load_Data_I
- Index_Load_Data_S
- Index_Load_Tag
- Index_Load_Tag_D
- Index_Load_Tag_I
- Index_Load_Tag_S
- Index_Load_Tag_SD
- Index_Load_Tag_SI
- Index_Load_Tag_T
- Index_Store_Data_D
- Index_Store_Data_I
- Index_Store_Data_S
- Index_Store_Tag
- Index_Store_Tag_D
- Index_Store_Tag_I
- Index_Store_Tag_S
- Index_Store_Tag_SD
- Index_Store_Tag_SI
- Index_Store_Tag_T
- Index_Writeback_Inv
- Index_Writeback_Inv_D
- Index_Writeback_Inv_S
- Index_Writeback_Inv_SD
- Index_Writeback_Inv_V
- IndexedDcd
- Indirect
- Inexactflag
- Inexacttrap
- InfoLeaf
- InfoRequestResponse
- InfoRequestResponse_callSignalAddress
- InitAtomicRead
- InitCC
- InitCE
- InitCP
- InitCal
- InitCommonPointer
- InitEC
- InitEQ
- InitFE
- InitFT
- InitFilt
- InitHI
- InitInterrupt8723BSdio
- InitLLTTable
- InitLed871x
- InitSC
- InitSDRAMRegisters
- InitSysInterrupt8723BSdio
- InitTo300Pointer
- InitTo310Pointer
- InitTunerControls
- InitUsbAggregationSetting
- InitWin
- Init_ODM_ComInfo_8723b
- Init_ODM_ComInfo_88E
- InitialGain819xUsb
- InitialGainOpType
- InitialGainOperateWorkItemCallBack
- Initial_Tx_Rate_Reg
- InitialiseRamdac
- Input
- InquiryData
- InsertNode
- InstrDual
- Instructionfield
- IntAckMasked_Reg
- IntAck_Reg
- IntControlDis_Reg
- IntControlEna_Reg
- IntEnable
- IntLatch
- IntReg
- IntReq
- IntRequested
- IntStatus
- IntStatusAck
- IntStatusMasked_Reg
- IntStatusSetMasked_Reg
- IntStatusSet_Reg
- IntStatus_Reg
- IntStatus_bits
- Int_BLEx
- Int_BLExEn
- Int_DParDEn
- Int_DParErrEn
- Int_DmParErr
- Int_DmParErrEn
- Int_DmParErrStat
- Int_EarNotEn
- Int_FDAEx
- Int_FDAExEn
- Int_IntBLEx
- Int_IntCmp
- Int_IntEarNot
- Int_IntExBD
- Int_IntFDAEx
- Int_IntMacRx
- Int_IntMacTx
- Int_IntNRAbt
- Int_IntPCI
- Int_NRAbtEn
- Int_NRabt
- Int_RMasAbtEn
- Int_RTargAbtEn
- Int_SSysErrEn
- Int_STargAbtEn
- Int_SWInt
- Int_TxCtlCmpEn
- Int_from_dbl_mantissa
- Int_from_sgl_mantissa
- Int_isinexact_to_sgl
- Int_negate
- IntegrationServicesVersion
- IntelCreateAndShare
- IntelEasyPCCamera
- IntelPCCameraPro
- IntelPocketPCCamera
- InterFrameGap
- Intercept
- Interface
- InterfaceModeRS232
- InterfaceModeRS232T
- InterfaceModeRS422
- InterfaceModeRS485
- InterfaceRequest
- InterfaceSel
- InterfaceShutdown
- InterlaceMode
- Interlaced
- InterruptClear
- InterruptEnable
- InterruptStatus
- InterruptTheCard
- Intf_InRequest
- Intf_Request
- IntrAbnormalMask
- IntrAbnormalSummary
- IntrAck
- IntrAll
- IntrBits
- IntrBreak
- IntrClear
- IntrControl
- IntrDMAErr
- IntrDrvRqst
- IntrEOF
- IntrEarlyRx
- IntrEarlyRxQ1
- IntrEarlyRxQ2
- IntrEnable
- IntrEnb
- IntrErr
- IntrFunc
- IntrGeneralTimer
- IntrHiPriTxBadID
- IntrHighBits
- IntrHoldoff
- IntrIntr
- IntrLatencyMask
- IntrLine
- IntrLinkChange
- IntrMACCtrl
- IntrMask
- IntrMask_8125
- IntrMitigate
- IntrNoTxCsum
- IntrNormalMask
- IntrNormalSummary
- IntrOK
- IntrPCI
- IntrPCIErr
- IntrPCIPad
- IntrQuit
- IntrResvd
- IntrRx
- IntrRxComplQ1Low
- IntrRxComplQ2Low
- IntrRxDMADone
- IntrRxDescQ1Low
- IntrRxDescQ2Low
- IntrRxDone
- IntrRxDropped
- IntrRxEarly
- IntrRxEmpty
- IntrRxErr
- IntrRxGFPDead
- IntrRxGfp
- IntrRxIdle
- IntrRxIntr
- IntrRxInvalid
- IntrRxNoBuf
- IntrRxOverflow
- IntrRxOverrun
- IntrRxPCIErr
- IntrRxPCIFault
- IntrRxQ1Done
- IntrRxQ2Done
- IntrRxStart
- IntrRxTrigger
- IntrRxWakeUp
- IntrSoftware
- IntrStatsMax
- IntrStatus
- IntrStatus2
- IntrStatusBits
- IntrStatus_8125
- IntrStatus_bits
- IntrSummary
- IntrTimer
- IntrTimerCtrl
- IntrTx
- IntrTxAborted
- IntrTxBadID
- IntrTxComplQLow
- IntrTxDMADone
- IntrTxDataLow
- IntrTxDescRace
- IntrTxDone
- IntrTxEmpty
- IntrTxErr
- IntrTxErrSummary
- IntrTxError
- IntrTxGfp
- IntrTxIdle
- IntrTxIntr
- IntrTxInvalid
- IntrTxPCIErr
- IntrTxPCIFault
- IntrTxTrigger
- IntrTxUnderrun
- IntrWakeup
- Invalidflag
- Invalidtrap
- Ioc3PhysDisk_t
- Ioc4Sep_t
- Ioc5HotSpare_t
- Ip_0
- Ip_s3s1s2
- Ip_u1
- Ip_u1s2
- Ip_u1u2
- Ip_u1u2s3
- Ip_u1u2u3
- Ip_u2s3u1
- Ip_u2u1
- Ip_u2u1msbu3
- Ip_u2u1s3
- Ip_u2u1u3
- Ip_u3u1u2
- Ip_u3u2u1
- IrDACLKCR
- Irongate0
- Irongate1
- IsAdapterPaused
- IsCommentString
- IsDISC
- IsDM
- IsDataFrame
- IsEnableHWCCK
- IsEnableHWOFDM
- IsFRMR
- IsFrameTypeCtrl
- IsGigabit
- IsHTHalfNmodeAPs
- IsHexDigit
- IsLegacyDataFrame
- IsLegacyOnly
- IsM650
- IsPassiveChannel
- IsQoSDataFrame
- IsREJ
- IsRNR
- IsRR
- IsSABME
- IsSFrame
- IsSpurInBand
- IsSupported24G
- IsSupported5G
- IsSupportedHT
- IsSupportedRxCCK
- IsSupportedRxHT
- IsSupportedRxMCS
- IsSupportedRxOFDM
- IsSupportedTxCCK
- IsSupportedTxMCS
- IsSupportedTxOFDM
- IsSupportedVHT
- IsTextMode
- IsUA
- IsUI
- Is_cbit_set
- Is_dbit21p2
- Is_dbit28p2
- Is_dbit29p2
- Is_dbit2p2
- Is_dbit30p2
- Is_dbit31p2
- Is_dbit3p1
- Is_dbit3p2
- Is_dexthiddenoverflow
- Is_dhidden
- Is_dhiddenoverflow
- Is_dhighp1
- Is_dhighp2
- Is_divisionbyzerotrap_enabled
- Is_dlowp1
- Is_dlowp2
- Is_dsign
- Is_dsignaling
- Is_inexacttrap_enabled
- Is_invalidtrap_enabled
- Is_overflowtrap_enabled
- Is_rounding_mode
- Is_sbit24
- Is_sbit28
- Is_sbit29
- Is_sbit30
- Is_sbit31
- Is_sexthiddenoverflow
- Is_shidden
- Is_shiddenoverflow
- Is_slow
- Is_ssign
- Is_ssignaling
- Is_tbit_set
- Is_underflowtrap_enabled
- Isdnl2_Init
- Isdnl2_cleanup
- Itrue
[..]