[..]
- H
 
- H1
 
- H14_1610_KBR2
 
- H18
 
- H19
 
- H1940_LATCH
 
- H1940_LATCH_AUDIO_POWER
 
- H1940_LATCH_BIT
 
- H1940_LATCH_BLUETOOTH_POWER
 
- H1940_LATCH_GPIO
 
- H1940_LATCH_LCD_P0
 
- H1940_LATCH_LCD_P1
 
- H1940_LATCH_LCD_P2
 
- H1940_LATCH_LCD_P3
 
- H1940_LATCH_LCD_P4
 
- H1940_LATCH_LED_FLASH
 
- H1940_LATCH_LED_GREEN
 
- H1940_LATCH_LED_RED
 
- H1940_LATCH_MAX1698_nSHUTDOWN
 
- H1940_LATCH_SDQ7
 
- H1940_LATCH_SD_POWER
 
- H1940_LATCH_SM803_ENABLE
 
- H1940_LATCH_UDA_POWER
 
- H1940_LATCH_USB_DP
 
- H1940_PA_LATCH
 
- H1940_SUSPEND_CHECK
 
- H1940_SUSPEND_CHECKSUM
 
- H1940_SUSPEND_RESUMEAT
 
- H19_1610_CAM_EXCLK
 
- H19_DESC
 
- H1POLY
 
- H1POLY_INITVAL
 
- H1TPD_CONS_IDX_BMSK
 
- H1TPD_CONS_IDX_SHFT
 
- H1TPD_PROD_IDX_BMSK
 
- H1TPD_PROD_IDX_SHFT
 
- H1_FORCE_QME
 
- H1_FORCE_QMH
 
- H1_FORCE_VAL
 
- H1_JPEG_QUANT_TABLE_COUNT
 
- H1_PCIEPHYADRR
 
- H1_PCIEPHYDOUTR
 
- H1_REG_ADDR_CABAC_TBL
 
- H1_REG_ADDR_IN_PLANE_0
 
- H1_REG_ADDR_IN_PLANE_1
 
- H1_REG_ADDR_IN_PLANE_2
 
- H1_REG_ADDR_MV_OUT
 
- H1_REG_ADDR_NEXT_PIC
 
- H1_REG_ADDR_OUTPUT_CTRL
 
- H1_REG_ADDR_OUTPUT_STREAM
 
- H1_REG_ADDR_REC_CHROMA
 
- H1_REG_ADDR_REC_LUMA
 
- H1_REG_ADDR_REF_CHROMA
 
- H1_REG_ADDR_REF_LUMA
 
- H1_REG_ADDR_VP8_DCT_PART
 
- H1_REG_ADDR_VP8_PROB_CNT
 
- H1_REG_ADDR_VP8_SEG_MAP
 
- H1_REG_AXI_CTRL
 
- H1_REG_AXI_CTRL_BURST_LEN
 
- H1_REG_AXI_CTRL_GATE_BIT
 
- H1_REG_AXI_CTRL_INPUT_SWAP16
 
- H1_REG_AXI_CTRL_INPUT_SWAP32
 
- H1_REG_AXI_CTRL_INPUT_SWAP8
 
- H1_REG_AXI_CTRL_OUTPUT_SWAP16
 
- H1_REG_AXI_CTRL_OUTPUT_SWAP32
 
- H1_REG_AXI_CTRL_OUTPUT_SWAP8
 
- H1_REG_CHECKPOINT
 
- H1_REG_CHECKPOINT_CHECK0
 
- H1_REG_CHECKPOINT_CHECK1
 
- H1_REG_CHECKPOINT_RESULT
 
- H1_REG_CHKPT_DELTA_QP
 
- H1_REG_CHKPT_DELTA_QP_CHK0
 
- H1_REG_CHKPT_DELTA_QP_CHK1
 
- H1_REG_CHKPT_DELTA_QP_CHK2
 
- H1_REG_CHKPT_DELTA_QP_CHK3
 
- H1_REG_CHKPT_DELTA_QP_CHK4
 
- H1_REG_CHKPT_DELTA_QP_CHK5
 
- H1_REG_CHKPT_DELTA_QP_CHK6
 
- H1_REG_CHKPT_WORD_ERR
 
- H1_REG_CHKPT_WORD_ERR_CHK0
 
- H1_REG_CHKPT_WORD_ERR_CHK1
 
- H1_REG_CIR_INTRA_CTRL
 
- H1_REG_DMV_4P_1P_PENALTY
 
- H1_REG_DMV_4P_1P_PENALTY_BIT
 
- H1_REG_DMV_QPEL_PENALTY
 
- H1_REG_DMV_QPEL_PENALTY_BIT
 
- H1_REG_ENC_CTRL
 
- H1_REG_ENC_CTRL0
 
- H1_REG_ENC_CTRL0_CHROMA_QP_OFFSET
 
- H1_REG_ENC_CTRL0_CONSTR_INTRA_PRED
 
- H1_REG_ENC_CTRL0_FILTER_DIS
 
- H1_REG_ENC_CTRL0_IDR_PICID
 
- H1_REG_ENC_CTRL0_INIT_QP
 
- H1_REG_ENC_CTRL0_SLICE_ALPHA
 
- H1_REG_ENC_CTRL0_SLICE_BETA
 
- H1_REG_ENC_CTRL1
 
- H1_REG_ENC_CTRL1_FRAME_NUM
 
- H1_REG_ENC_CTRL1_INTRA_PRED_MODE
 
- H1_REG_ENC_CTRL1_PPS_ID
 
- H1_REG_ENC_CTRL2
 
- H1_REG_ENC_CTRL2_CABAC_INIT_IDC
 
- H1_REG_ENC_CTRL2_DEBLOCKING_FILETER_MODE
 
- H1_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV
 
- H1_REG_ENC_CTRL2_ENTROPY_CODING_MODE
 
- H1_REG_ENC_CTRL2_H264_INTER4X4_MODE
 
- H1_REG_ENC_CTRL2_H264_SLICE_SIZE
 
- H1_REG_ENC_CTRL2_H264_STREAM_MODE
 
- H1_REG_ENC_CTRL2_INTRA16X16_MODE
 
- H1_REG_ENC_CTRL2_TRANS8X8_MODE_EN
 
- H1_REG_ENC_CTRL3
 
- H1_REG_ENC_CTRL3_MUTIMV_EN
 
- H1_REG_ENC_CTRL3_MV_PENALTY_1P
 
- H1_REG_ENC_CTRL3_MV_PENALTY_1_4P
 
- H1_REG_ENC_CTRL3_MV_PENALTY_4P
 
- H1_REG_ENC_CTRL4
 
- H1_REG_ENC_CTRL4_8X4_4X8
 
- H1_REG_ENC_CTRL4_MV_PENALTY_16X8_8X16
 
- H1_REG_ENC_CTRL4_MV_PENALTY_8X8
 
- H1_REG_ENC_CTRL5
 
- H1_REG_ENC_CTRL5_COMPLETE_SLICES
 
- H1_REG_ENC_CTRL5_INTER_MODE
 
- H1_REG_ENC_CTRL5_MACROBLOCK_PENALTY
 
- H1_REG_ENC_CTRL_ENC_MODE_H264
 
- H1_REG_ENC_CTRL_ENC_MODE_JPEG
 
- H1_REG_ENC_CTRL_ENC_MODE_VP8
 
- H1_REG_ENC_CTRL_EN_BIT
 
- H1_REG_ENC_CTRL_HEIGHT
 
- H1_REG_ENC_CTRL_NAL_MODE_BIT
 
- H1_REG_ENC_CTRL_TIMEOUT_EN
 
- H1_REG_ENC_CTRL_WIDTH
 
- H1_REG_ENC_PIC_INTER
 
- H1_REG_ENC_PIC_INTRA
 
- H1_REG_ENC_PIC_MVCINTER
 
- H1_REG_FIRST_ROI_AREA
 
- H1_REG_INTERRUPT
 
- H1_REG_INTERRUPT_BIT
 
- H1_REG_INTERRUPT_DIS_BIT
 
- H1_REG_INTERRUPT_FRAME_RDY
 
- H1_REG_INTRA_AREA_CTRL
 
- H1_REG_INTRA_SLICE_BITMAP
 
- H1_REG_IN_IMG_CTRL
 
- H1_REG_IN_IMG_CTRL_FMT
 
- H1_REG_IN_IMG_CTRL_OVRFLB_D4
 
- H1_REG_IN_IMG_CTRL_OVRFLR_D4
 
- H1_REG_IN_IMG_CTRL_ROW_LEN
 
- H1_REG_JPEG_CHROMA_QUAT
 
- H1_REG_JPEG_LUMA_QUAT
 
- H1_REG_MAD_CTRL
 
- H1_REG_MAD_CTRL_MAD_THREDHOLD
 
- H1_REG_MAD_CTRL_QP_ADJUST
 
- H1_REG_MAD_CTRL_QP_SUM_DIV2
 
- H1_REG_MB_CNT_OUT
 
- H1_REG_MB_CNT_SET
 
- H1_REG_MB_CTRL
 
- H1_REG_MVC_CTRL
 
- H1_REG_MVC_CTRL_MV16X16_FAVOR
 
- H1_REG_QP_VAL
 
- H1_REG_QP_VAL_CHECKPOINT_DISTAN
 
- H1_REG_QP_VAL_LUM
 
- H1_REG_QP_VAL_MAX
 
- H1_REG_QP_VAL_MIN
 
- H1_REG_RGB_MASK_MSB
 
- H1_REG_RGB_YUV_COEFF
 
- H1_REG_RLC_CTRL
 
- H1_REG_RLC_CTRL_RLC_SUM
 
- H1_REG_RLC_CTRL_STR_OFFS_MASK
 
- H1_REG_RLC_CTRL_STR_OFFS_SHIFT
 
- H1_REG_SECOND_ROI_AREA
 
- H1_REG_STABILIZATION_OUTPUT
 
- H1_REG_STR_BUF_LIMIT
 
- H1_REG_STR_HDR_REM_LSB
 
- H1_REG_STR_HDR_REM_MSB
 
- H1_REG_VP8_BIT_COST_GOLDEN
 
- H1_REG_VP8_BOOL_ENC
 
- H1_REG_VP8_CTRL0
 
- H1_REG_VP8_CTRL1
 
- H1_REG_VP8_INTRA_PENALTY
 
- H1_REG_VP8_LOOP_FLT_DELTA
 
- H1_REG_VP8_QP_VAL
 
- H1_REG_VP8_SEG_QP
 
- H2
 
- H20
 
- H21
 
- H21_DESC
 
- H22
 
- H2250LogicalChannelAckParameters
 
- H2250LogicalChannelParameters
 
- H23
 
- H24
 
- H245_TransportAddress
 
- H24x7_DATA_BUFFER_SIZE
 
- H24x7_REQUEST_SIZE
 
- H25
 
- H26
 
- H264_BITSTREAM_OVERSIZE
 
- H264_BS_MODE_FRAME
 
- H264_BS_MODE_PPS
 
- H264_BS_MODE_SPS
 
- H264_BUF_CNT
 
- H264_ENC
 
- H264_ERR_NOT_VALID
 
- H264_FACTOR_BASELINE
 
- H264_FACTOR_HIGH
 
- H264_FILLER_DATA_SIZE
 
- H264_FILLER_MARKER_SIZE
 
- H264_FRAME_SKIPPED
 
- H264_I_PERIOD
 
- H264_MAX_FB_NUM
 
- H264_MAX_SIZE_H
 
- H264_MAX_SIZE_W
 
- H264_MAX_SLICE_NUMBER
 
- H264_MB_DIM
 
- H264_MB_HEIGHT
 
- H264_MB_WIDTH
 
- H264_MV_BUF_SIZE
 
- H264_POC_TYPE
 
- H264_SLICE_LIMIT_SIZE
 
- H264_SLICE_READY
 
- H264_VLC_BUF_SIZE
 
- H2C_8723BE_AOAC_GLOBAL_INFO
 
- H2C_8723BE_AOAC_RSVDPAGE
 
- H2C_8723BE_AP_OFFLOAD
 
- H2C_8723BE_BCN_RSVDPAGE
 
- H2C_8723BE_DISCONNECT_DECISION
 
- H2C_8723BE_INIT_OFFLOAD
 
- H2C_8723BE_JOINBSSRPT
 
- H2C_8723BE_KEEP_ALIVE_CTRL
 
- H2C_8723BE_P2P_PS_CTW_CMD
 
- H2C_8723BE_P2P_PS_MODE
 
- H2C_8723BE_P2P_PS_OFFLOAD
 
- H2C_8723BE_PROBERSP_RSVDPAGE
 
- H2C_8723BE_PSD_RESULT
 
- H2C_8723BE_PS_LPS_PARA
 
- H2C_8723BE_PS_TUNING_PARA
 
- H2C_8723BE_PS_TUNING_PARA2
 
- H2C_8723BE_RA_MASK
 
- H2C_8723BE_REMOTE_WAKE_CTRL
 
- H2C_8723BE_RSSI_REPORT
 
- H2C_8723BE_RSVDPAGE
 
- H2C_8723BE_SCAN
 
- H2C_8723BE_SELECTIVE_SUSPEND_ROF_CMD
 
- H2C_8723BE_SETPWRMODE
 
- H2C_8723BE_WO_WLAN
 
- H2C_8723B_ANT_SEL_RSV
 
- H2C_8723B_AOAC_GLOBAL_INFO
 
- H2C_8723B_AOAC_RSVD_PAGE
 
- H2C_8723B_AOAC_RSVD_PAGE2
 
- H2C_8723B_AP_OFFLOAD
 
- H2C_8723B_AP_REQ_TXRPT
 
- H2C_8723B_AP_WOW_GPIO_CTRL
 
- H2C_8723B_BCN_RSVDPAGE
 
- H2C_8723B_BT_CONTROL
 
- H2C_8723B_BT_FW_PATCH
 
- H2C_8723B_BT_GRANT
 
- H2C_8723B_BT_IGNORE_WLANACT
 
- H2C_8723B_BT_INFO
 
- H2C_8723B_BT_MP_OPER
 
- H2C_8723B_BT_WIFI_CTRL
 
- H2C_8723B_BT_WLAN_CALIBRATION
 
- H2C_8723B_B_TYPE_TDMA
 
- H2C_8723B_CHNL_SWITCH_OFFLOAD
 
- H2C_8723B_D0_SCAN_OFFLOAD_CTRL
 
- H2C_8723B_D0_SCAN_OFFLOAD_INFO
 
- H2C_8723B_DAC_SWING_VALUE
 
- H2C_8723B_DISCONNECT_DECISION
 
- H2C_8723B_DISCON_DECISION
 
- H2C_8723B_FCS_INFO
 
- H2C_8723B_FCS_RSVDPAGE
 
- H2C_8723B_FORCE_BT_TXPWR
 
- H2C_8723B_FWLPS_IN_IPS_
 
- H2C_8723B_INACTIVE_PS_
 
- H2C_8723B_INIT_RATE_COLLECT
 
- H2C_8723B_KEEP_ALIVE
 
- H2C_8723B_KEEP_ALIVE_CTRL
 
- H2C_8723B_MACID_CFG
 
- H2C_8723B_MACID_CFG_RAID
 
- H2C_8723B_MAXID
 
- H2C_8723B_MEDIA_STATUS_RPT
 
- H2C_8723B_MSRRPT
 
- H2C_8723B_P2P_LPS_PARAM
 
- H2C_8723B_P2P_PS_CTW_CMD
 
- H2C_8723B_P2P_PS_OFFLOAD
 
- H2C_8723B_PROBERSP_RSVDPAGE
 
- H2C_8723B_PSD_OFFLOAD
 
- H2C_8723B_PS_LPS_PARA
 
- H2C_8723B_PS_SCAN_ENABLE
 
- H2C_8723B_PS_TUNING_PARA
 
- H2C_8723B_PS_TUNING_PARA2
 
- H2C_8723B_RA_MASK
 
- H2C_8723B_REMOTE_WAKE_CTRL
 
- H2C_8723B_RESET_TSF
 
- H2C_8723B_RSSI_SETTING
 
- H2C_8723B_RSVDPAGE
 
- H2C_8723B_RSVD_PAGE
 
- H2C_8723B_SAP_PS_
 
- H2C_8723B_SCAN
 
- H2C_8723B_SCAN_ENABLE
 
- H2C_8723B_SETPWRMODE
 
- H2C_8723B_SET_PWR_MODE
 
- H2C_8723B_TXBF
 
- H2C_8723B_WL_OPMODE
 
- H2C_8723B_WOWLAN
 
- H2C_8821AE_AOAC_GLOBAL_INFO
 
- H2C_8821AE_AOAC_GLOBAL_INFO_LEN
 
- H2C_8821AE_AOAC_RSVDPAGE
 
- H2C_8821AE_AOAC_RSVDPAGE_LOC_LEN
 
- H2C_8821AE_AP_OFFLOAD
 
- H2C_8821AE_AP_OFFLOAD_LENGTH
 
- H2C_8821AE_BCN_RSVDPAGE
 
- H2C_8821AE_DISCONNECT_DECISION
 
- H2C_8821AE_DISCONNECT_DECISION_CTRL_LEN
 
- H2C_8821AE_INIT_OFFLOAD
 
- H2C_8821AE_JOINBSSRPT_LENGTH
 
- H2C_8821AE_KEEP_ALIVE_CTRL
 
- H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH
 
- H2C_8821AE_MSRRPT
 
- H2C_8821AE_P2P_PS_CTW_CMD
 
- H2C_8821AE_P2P_PS_MODE
 
- H2C_8821AE_P2P_PS_OFFLOAD
 
- H2C_8821AE_PROBERSP_RSVDPAGE
 
- H2C_8821AE_PSD_RESULT
 
- H2C_8821AE_PS_LPS_PARA
 
- H2C_8821AE_PS_TUNING_PARA
 
- H2C_8821AE_PS_TUNING_PARA2
 
- H2C_8821AE_PWEMODE_LENGTH
 
- H2C_8821AE_RA_MASK
 
- H2C_8821AE_REMOTE_WAKE_CTRL
 
- H2C_8821AE_REMOTE_WAKE_CTRL_LEN
 
- H2C_8821AE_RSVDPAGE
 
- H2C_8821AE_RSVDPAGE_LOC_LEN
 
- H2C_8821AE_SCAN
 
- H2C_8821AE_SELECTIVE_SUSPEND_ROF_CMD
 
- H2C_8821AE_SETPWRMODE
 
- H2C_8821AE_WOWLAN_LENGTH
 
- H2C_8821AE_WO_WLAN
 
- H2C_88E_AOAC_GLOBAL_INFO
 
- H2C_88E_AOAC_GLOBAL_INFO_LEN
 
- H2C_88E_AOAC_RSVDPAGE
 
- H2C_88E_AOAC_RSVDPAGE_LOC_LEN
 
- H2C_88E_AP_OFFLOAD
 
- H2C_88E_AP_OFFLOAD_LENGTH
 
- H2C_88E_BCN_RSVDPAGE
 
- H2C_88E_DISCONNECT_DECISION
 
- H2C_88E_INIT_OFFLOAD
 
- H2C_88E_JOINBSSRPT
 
- H2C_88E_JOINBSSRPT_LENGTH
 
- H2C_88E_KEEP_ALIVE_CTRL
 
- H2C_88E_KEEP_ALIVE_CTRL_LENGTH
 
- H2C_88E_P2P_PS_CTW_CMD
 
- H2C_88E_P2P_PS_MODE
 
- H2C_88E_P2P_PS_OFFLOAD
 
- H2C_88E_PROBERSP_RSVDPAGE
 
- H2C_88E_PSD_RESULT
 
- H2C_88E_PS_LPS_PARA
 
- H2C_88E_PS_TUNING_PARA
 
- H2C_88E_PS_TUNING_PARA2
 
- H2C_88E_PWEMODE_LENGTH
 
- H2C_88E_RA_MASK
 
- H2C_88E_REMOTE_WAKE_CTRL
 
- H2C_88E_REMOTE_WAKE_CTRL_LEN
 
- H2C_88E_RSVDPAGE
 
- H2C_88E_RSVDPAGE_LOC_LEN
 
- H2C_88E_SCAN
 
- H2C_88E_SELECTIVE_SUSPEND_ROF_CMD
 
- H2C_88E_SETPWRMODE
 
- H2C_88E_WOWLAN_LENGTH
 
- H2C_88E_WO_WLAN
 
- H2C_92C_KEEP_ALIVE_CTRL
 
- H2C_92E_AOAC_GLOBAL_INFO
 
- H2C_92E_AOAC_GLOBAL_INFO_LEN
 
- H2C_92E_AOAC_RSVDPAGE
 
- H2C_92E_AOAC_RSVDPAGE_LOC_LEN
 
- H2C_92E_AP_OFFLOAD
 
- H2C_92E_AP_OFFLOAD_LENGTH
 
- H2C_92E_BCN_RSVDPAGE
 
- H2C_92E_DISCONNECT_DECISION
 
- H2C_92E_INIT_OFFLOAD
 
- H2C_92E_JOINBSSRPT_LENGTH
 
- H2C_92E_KEEP_ALIVE_CTRL
 
- H2C_92E_KEEP_ALIVE_CTRL_LENGTH
 
- H2C_92E_MSRRPT
 
- H2C_92E_P2P_PS_CTW_CMD
 
- H2C_92E_P2P_PS_MODE
 
- H2C_92E_P2P_PS_OFFLOAD
 
- H2C_92E_PROBERSP_RSVDPAGE
 
- H2C_92E_PSD_RESULT
 
- H2C_92E_PS_LPS_PARA
 
- H2C_92E_PS_TUNING_PARA
 
- H2C_92E_PS_TUNING_PARA2
 
- H2C_92E_PWEMODE_LENGTH
 
- H2C_92E_RA_MASK
 
- H2C_92E_REMOTE_WAKE_CTRL
 
- H2C_92E_REMOTE_WAKE_CTRL_LEN
 
- H2C_92E_RSSI_REPORT
 
- H2C_92E_RSVDPAGE
 
- H2C_92E_RSVDPAGE_LOC_LEN
 
- H2C_92E_SCAN
 
- H2C_92E_SELECTIVE_SUSPEND_ROF_CMD
 
- H2C_92E_SETPWRMODE
 
- H2C_92E_WOWLAN_LENGTH
 
- H2C_92E_WO_WLAN
 
- H2C_ANT_SEL_RSV
 
- H2C_AOAC_GLOBAL_INFO
 
- H2C_AOAC_GLOBAL_INFO_LEN
 
- H2C_AOAC_RSVDPAGE3
 
- H2C_AOAC_RSVDPAGE_LOC_LEN
 
- H2C_AOAC_RSVD_PAGE
 
- H2C_AOAC_RSVD_PAGE2
 
- H2C_AP_OFFLOAD
 
- H2C_AP_OFFLOAD_LEN
 
- H2C_AP_PS_LEN
 
- H2C_AP_REQ_TXRPT
 
- H2C_AP_REQ_TXRPT_LEN
 
- H2C_AP_WOW_GPIO_CTRL
 
- H2C_AP_WOW_GPIO_CTRL_LEN
 
- H2C_BCN_RSVDPAGE
 
- H2C_BCN_RSVDPAGE_LEN
 
- H2C_BTMP_OPER_LEN
 
- H2C_BT_COEX_GPIO_MODE
 
- H2C_BT_COEX_MASK
 
- H2C_BT_CONTROL
 
- H2C_BT_DAC_SWING_VAL
 
- H2C_BT_FW_PATCH
 
- H2C_BT_FW_PATCH_LEN
 
- H2C_BT_IGNORE_WLANACT
 
- H2C_BT_INFO
 
- H2C_BT_MP_OPER
 
- H2C_BT_PORT_ID
 
- H2C_BT_PSD_RST
 
- H2C_BT_WIFI_CTRL
 
- H2C_B_TYPE_TDMA
 
- H2C_CHNL_SWITCH_OFFLOAD
 
- H2C_CMD_BT_WIFI_CONTROL
 
- H2C_CMD_COEX_TDMA_TYPE
 
- H2C_CMD_FORCE_BT_TX_POWER
 
- H2C_CMD_IGNORE_WLAN_ACTION
 
- H2C_CMD_MEDIA_STATUS_RPT
 
- H2C_CMD_OVERFLOW
 
- H2C_CMD_QUERY_BT_INFO
 
- H2C_CMD_QUERY_BT_MP_INFO
 
- H2C_CMD_RA_INFO
 
- H2C_CMD_RSSI_MONITOR
 
- H2C_CMD_RSVD_PAGE
 
- H2C_CMD_SET_PWR_MODE
 
- H2C_CMD_WL_CH_INFO
 
- H2C_COM_AP_OFFLOAD
 
- H2C_COM_BCN_RSVD_PAGE
 
- H2C_COM_DISCNT_DECISION
 
- H2C_COM_INIT_OFFLOAD
 
- H2C_COM_KEEP_ALIVE
 
- H2C_COM_MEDIA_STATUS_RPT
 
- H2C_COM_PROB_RSP_RSVD_PAGE
 
- H2C_COM_REMOTE_WAKE_CTL
 
- H2C_COM_RSVD_PAGE
 
- H2C_COM_SCAN
 
- H2C_CREATEBSS_CMD
 
- H2C_D0_SCAN_OFFLOAD_CTRL
 
- H2C_D0_SCAN_OFFLOAD_INFO
 
- H2C_DAC_SWING_VALUE
 
- H2C_DELASSOCSTA_CMD
 
- H2C_DISCONNECT_CMD
 
- H2C_DISCON_DECISION
 
- H2C_DISCON_DECISION_LEN
 
- H2C_DM_MACID_CFG
 
- H2C_DM_TXBF
 
- H2C_DROPPED
 
- H2C_DUPLICATED
 
- H2C_EXT
 
- H2C_FCS_INFO
 
- H2C_FCS_RSVDPAGE
 
- H2C_FORCE_BT_TXPWR
 
- H2C_FORCE_BT_TXPWR_LEN
 
- H2C_FWLPS_IN_IPS_
 
- H2C_GETBASICRATE_CMD
 
- H2C_GETCCXREPORT_CMD
 
- H2C_GETDATARATE_CMD
 
- H2C_GETDTMREPORT_CMD
 
- H2C_GETPHYINFO_CMD
 
- H2C_GETPHY_CMD
 
- H2C_GETRATABLE_CMD
 
- H2C_GETTXRATESTATICS_CMD
 
- H2C_INACTIVE_PS_
 
- H2C_INIT_RATE_COLLECT
 
- H2C_JOINBSSRPT
 
- H2C_JOINBSSRPT_CMD
 
- H2C_JOINBSS_CMD
 
- H2C_JOIN_BSS_CONNECT
 
- H2C_JOIN_BSS_DISCONNECT
 
- H2C_JOIN_BSS_REPORT
 
- H2C_KEEP_ALIVE
 
- H2C_KEEP_ALIVE_CTRL_LEN
 
- H2C_MACID_CFG
 
- H2C_MACID_CFG_LEN
 
- H2C_MACID_PS_MODE
 
- H2C_MAC_MODE_SEL
 
- H2C_MAXID
 
- H2C_MAX_MBOX
 
- H2C_MEDIA_STATUS_RPT
 
- H2C_MEDIA_STATUS_RPT_LEN
 
- H2C_P2P_LPS_PARAM
 
- H2C_P2P_PS_CTW_CMD
 
- H2C_P2P_PS_OFFLOAD
 
- H2C_PARAMETERS_ERROR
 
- H2C_PKT_CATEGORY
 
- H2C_PKT_CMD_ID
 
- H2C_PKT_GENERAL_INFO
 
- H2C_PKT_HDR_SIZE
 
- H2C_PKT_IQK
 
- H2C_PKT_PHYDM_INFO
 
- H2C_PKT_SIZE
 
- H2C_PROBERSP_RSVDPAGE
 
- H2C_PROBERSP_RSVDPAGE_LEN
 
- H2C_PSD_OFFLOAD
 
- H2C_PSTUNEPARAM_LEN
 
- H2C_PS_LPS_PARA
 
- H2C_PS_P2P_OFFLOAD
 
- H2C_PS_PWR_MODE
 
- H2C_PS_SCAN_ENABLE
 
- H2C_PS_TUNE_PARA
 
- H2C_PS_TUNE_PARA_2
 
- H2C_PS_TUNING_PARA
 
- H2C_PS_TUNING_PARA2
 
- H2C_PWEMODE_LENGTH
 
- H2C_PWRM
 
- H2C_PWRMODE_LEN
 
- H2C_QUEUE
 
- H2C_RA_MASK
 
- H2C_READBB_CMD
 
- H2C_READGAIN_CMD
 
- H2C_READRF_CMD
 
- H2C_READRSSI_CMD
 
- H2C_READ_CAM_CMD
 
- H2C_READ_EEPROM_CMD
 
- H2C_READ_EFUSE_CMD
 
- H2C_READ_MACREG_CMD
 
- H2C_REJECTED
 
- H2C_REMOTE_WAKE_CTRL
 
- H2C_REMOTE_WAKE_CTRL_LEN
 
- H2C_RESERVED
 
- H2C_RESET_TSF
 
- H2C_RSP_OFFSET
 
- H2C_RSSIBE_REPORT
 
- H2C_RSSI_21AE_REPORT
 
- H2C_RSSI_REPORT
 
- H2C_RSSI_SETTING
 
- H2C_RSSI_SETTING_LEN
 
- H2C_RSVDPAGE
 
- H2C_RSVDPAGE_LOC_LEN
 
- H2C_RSVD_PAGE
 
- H2C_SAP_PS_
 
- H2C_SCAN_ENABLE
 
- H2C_SCAN_OFFLOAD_CTRL_LEN
 
- H2C_SETASSOCSTA_CMD
 
- H2C_SETATIM_CMD
 
- H2C_SETAUTH_CMD
 
- H2C_SETBASICRATE_CMD
 
- H2C_SETBCNITV_CMD
 
- H2C_SETDATARATE_CMD
 
- H2C_SETH2CLBK_CMD
 
- H2C_SETKEY_CMD
 
- H2C_SETMBIDCFG_CMD
 
- H2C_SETOPMODE_CMD
 
- H2C_SETPHYINFO_CMD
 
- H2C_SETPHY_CMD
 
- H2C_SETPWRMODE
 
- H2C_SETPWRMODE_CMD
 
- H2C_SETRATABLE_CMD
 
- H2C_SETSTAKEY_CMD
 
- H2C_SETSTAPWRSTATE_CMD
 
- H2C_SETUSBSUSPEND_CMD
 
- H2C_SET_POWER_MODE
 
- H2C_SET_PWR_MODE
 
- H2C_SET_RATE_MASK
 
- H2C_SET_RSSI
 
- H2C_SITESURVEY_CMD
 
- H2C_SUCCESS
 
- H2C_SUCCESS_RSP
 
- H2C_TMP1
 
- H2C_TMP2
 
- H2C_TMP3
 
- H2C_TMP4
 
- H2C_TXBF
 
- H2C_TX_CMD_HDR_LEN
 
- H2C_WL_OPMODE
 
- H2C_WOWLAN
 
- H2C_WOWLAN_FW_OFFLOAD
 
- H2C_WOWLAN_LEN
 
- H2C_WOWLAN_UPDATE_GTK_CMD
 
- H2C_WOWLAN_UPDATE_IV_CMD
 
- H2C_WRITEBB_CMD
 
- H2C_WRITERF_CMD
 
- H2C_WRITE_CAM_CMD
 
- H2C_WRITE_EEPROM_CMD
 
- H2C_WRITE_EFUSE_CMD
 
- H2C_WRITE_MACREG_CMD
 
- H2I_ADC_C1
 
- H2I_ADC_C2
 
- H2I_AESRX_C
 
- H2I_AESTX_C
 
- H2I_AESTX_C_CLKID_M
 
- H2I_AESTX_C_CLKID_SHIFT
 
- H2I_AESTX_C_DATAT_M
 
- H2I_AESTX_C_DATAT_SHIFT
 
- H2I_BRES1_C1
 
- H2I_BRES1_C2
 
- H2I_BRES2_C1
 
- H2I_BRES2_C2
 
- H2I_BRES3_C1
 
- H2I_BRES3_C2
 
- H2I_BRES_C1_M
 
- H2I_BRES_C1_SHIFT
 
- H2I_BRES_C2_INC_M
 
- H2I_BRES_C2_INC_SHIFT
 
- H2I_BRES_C2_MOD_M
 
- H2I_BRES_C2_MOD_SHIFT
 
- H2I_C1_CLKID_M
 
- H2I_C1_CLKID_SHIFT
 
- H2I_C1_DATAT_M
 
- H2I_C1_DATAT_SHIFT
 
- H2I_C1_DMA_M
 
- H2I_C1_DMA_SHIFT
 
- H2I_C2_DO1
 
- H2I_C2_DO2
 
- H2I_C2_L_ATT_M
 
- H2I_C2_L_ATT_SHIFT
 
- H2I_C2_L_GAIN_M
 
- H2I_C2_L_GAIN_SHIFT
 
- H2I_C2_L_SEL
 
- H2I_C2_MUTE
 
- H2I_C2_R_ATT_M
 
- H2I_C2_R_ATT_SHIFT
 
- H2I_C2_R_GAIN_M
 
- H2I_C2_R_GAIN_SHIFT
 
- H2I_C2_R_SEL
 
- H2I_C_NAUDIO
 
- H2I_C_TS_EN
 
- H2I_C_TS_FRMT
 
- H2I_DAC_C1
 
- H2I_DAC_C2
 
- H2I_DMA_DRV
 
- H2I_DMA_END
 
- H2I_DMA_END_AESRX
 
- H2I_DMA_END_AESTX
 
- H2I_DMA_END_CODECR
 
- H2I_DMA_END_CODECTX
 
- H2I_DMA_END_SY_IN
 
- H2I_DMA_PORT_EN
 
- H2I_DMA_PORT_EN_AESRX
 
- H2I_DMA_PORT_EN_AESTX
 
- H2I_DMA_PORT_EN_CODECR
 
- H2I_DMA_PORT_EN_CODECTX
 
- H2I_DMA_PORT_EN_SY_IN
 
- H2I_RELAY_C
 
- H2I_RELAY_C_STATE
 
- H2I_SYNTH_C
 
- H2I_SYNTH_MAP_C
 
- H2I_UTIME
 
- H2I_UTIME_0_LD
 
- H2I_UTIME_1_LD0
 
- H2I_UTIME_1_LD1
 
- H2I_UTIME_2_LD
 
- H2I_UTIME_3_LD
 
- H2M_BBP_AGENT
 
- H2M_INT_SRC
 
- H2M_MAILBOX_CID
 
- H2M_MAILBOX_CID_CMD0
 
- H2M_MAILBOX_CID_CMD1
 
- H2M_MAILBOX_CID_CMD2
 
- H2M_MAILBOX_CID_CMD3
 
- H2M_MAILBOX_CSR
 
- H2M_MAILBOX_CSR_ARG0
 
- H2M_MAILBOX_CSR_ARG1
 
- H2M_MAILBOX_CSR_CMD_TOKEN
 
- H2M_MAILBOX_CSR_OWNER
 
- H2M_MAILBOX_STATUS
 
- H2P2_DBG_FPGA_BASE
 
- H2P2_DBG_FPGA_BOARD_REV
 
- H2P2_DBG_FPGA_ETHR_START
 
- H2P2_DBG_FPGA_FPGA_REV
 
- H2P2_DBG_FPGA_GPIO
 
- H2P2_DBG_FPGA_LAN_RESET
 
- H2P2_DBG_FPGA_LAN_STATUS
 
- H2P2_DBG_FPGA_LEDS
 
- H2P2_DBG_FPGA_LED_AMBER
 
- H2P2_DBG_FPGA_LED_BLUE
 
- H2P2_DBG_FPGA_LED_GREEN
 
- H2P2_DBG_FPGA_LED_RED
 
- H2P2_DBG_FPGA_LOAD_METER
 
- H2P2_DBG_FPGA_LOAD_METER_MASK
 
- H2P2_DBG_FPGA_LOAD_METER_SIZE
 
- H2P2_DBG_FPGA_MISC_INPUTS
 
- H2P2_DBG_FPGA_P2_LED_IDLE
 
- H2P2_DBG_FPGA_P2_LED_TIMER
 
- H2P2_DBG_FPGA_SIZE
 
- H2P2_DBG_FPGA_START
 
- H2POLY
 
- H2POLY_INITVAL
 
- H2TPD_CONS_IDX_BMSK
 
- H2TPD_CONS_IDX_SHFT
 
- H2TPD_PROD_IDX_BMSK
 
- H2TPD_PROD_IDX_SHFT
 
- H2_BLOCK_SIZE
 
- H2_BUF_SIZE
 
- H2_IAR_ACCESS_SELECT
 
- H2_IAR_NUM_M
 
- H2_IAR_PARAM
 
- H2_IAR_RB_INDEX_M
 
- H2_IAR_TYPE_M
 
- H2_INDIRECT_WAIT
 
- H2_ISR_CODEC_RESET_N
 
- H2_ISR_GLOBAL_RESET_N
 
- H2_ISR_QUAD_MODE
 
- H2_ISR_TSTATUS
 
- H2_ISR_USTATUS
 
- H2_MIX_INPUT_GAIN
 
- H2_MIX_OUTPUT_ATT
 
- H2_NAND_RB_GPIO_PIN
 
- H2_PAD_CFG
 
- H2_READ_ADDR
 
- H2_REV_AUDIO_PRESENT
 
- H2_REV_BOARD_M
 
- H2_REV_MAJOR_CHIP_M
 
- H2_REV_MINOR_CHIP_M
 
- H2_TPS_GPIO_BASE
 
- H2_TPS_GPIO_MMC_PWR_EN
 
- H2_WRITE_ADDR
 
- H3
 
- H3100_GPIO_AUD_ON
 
- H3100_GPIO_AUD_PWR_ON
 
- H3100_GPIO_BT_ON
 
- H3100_GPIO_IR_FSEL
 
- H3100_GPIO_IR_ON
 
- H3100_GPIO_LCD_3V_ON
 
- H3100_GPIO_QMUTE
 
- H323_ERROR_BOUND
 
- H323_ERROR_NONE
 
- H323_ERROR_RANGE
 
- H323_ERROR_STOP
 
- H323_RTP_CHANNEL_MAX
 
- H323_TRACE
 
- H323_UU_PDU
 
- H323_UU_PDU_h245Control
 
- H323_UU_PDU_h323_message_body
 
- H323_UserInformation
 
- H32MX_MAX_FREQ
 
- H32_64
 
- H3600_BANK_2_PHYS
 
- H3600_BANK_2_VIRT
 
- H3600_BANK_4_PHYS
 
- H3600_BANK_4_VIRT
 
- H3600_EGPIO_AUD_AMP_ON
 
- H3600_EGPIO_AUD_PWR_ON
 
- H3600_EGPIO_IR_FSEL
 
- H3600_EGPIO_IR_ON
 
- H3600_EGPIO_LCD_5V_ON
 
- H3600_EGPIO_LCD_PCI
 
- H3600_EGPIO_LVDD_ON
 
- H3600_EGPIO_PHYS
 
- H3600_EGPIO_QMUTE
 
- H3600_EGPIO_VIRT
 
- H3600_GPIO_CLK_SET0
 
- H3600_GPIO_CLK_SET1
 
- H3600_GPIO_OPT_DET
 
- H3600_GPIO_OPT_LOCK
 
- H3600_GPIO_SOFT_RESET
 
- H3LIS331DL
 
- H3LIS331DL_ACCEL_DEV_NAME
 
- H3TPD_CONS_IDX_BMSK
 
- H3TPD_CONS_IDX_SHFT
 
- H3TPD_PROD_IDX_BMSK
 
- H3TPD_PROD_IDX_SHFT
 
- H3XXX_EGPIO_BASE
 
- H3XXX_EGPIO_CARD_RESET
 
- H3XXX_EGPIO_CODEC_NRESET
 
- H3XXX_EGPIO_LCD_ON
 
- H3XXX_EGPIO_OPT_NVRAM_ON
 
- H3XXX_EGPIO_OPT_ON
 
- H3XXX_EGPIO_OPT_RESET
 
- H3XXX_EGPIO_RS232_ON
 
- H3XXX_EGPIO_VPP_ON
 
- H3XXX_GPIO_ACTION_BUTTON
 
- H3XXX_GPIO_COM_CTS
 
- H3XXX_GPIO_COM_DCD
 
- H3XXX_GPIO_COM_RTS
 
- H3XXX_GPIO_OPTION
 
- H3XXX_GPIO_PCMCIA_CD0
 
- H3XXX_GPIO_PCMCIA_CD1
 
- H3XXX_GPIO_PCMCIA_IRQ0
 
- H3XXX_GPIO_PCMCIA_IRQ1
 
- H3XXX_GPIO_PWR_BUTTON
 
- H3XXX_GPIO_SYS_CLK
 
- H3_EPHY_ADDR_SHIFT
 
- H3_EPHY_CLK_SEL
 
- H3_EPHY_LED_POL
 
- H3_EPHY_MUX_MASK
 
- H3_EPHY_SELECT
 
- H3_EPHY_SHUTDOWN
 
- H3_NAND_RB_GPIO_PIN
 
- H3_TPS_GPIO_BASE
 
- H3_TPS_GPIO_MMC_PWR_EN
 
- H3_TS_GPIO
 
- H4
 
- H4_RECV_ACL
 
- H4_RECV_EVENT
 
- H4_RECV_SCO
 
- H4_TYPE_SIZE
 
- H5
 
- H5000_GPIO_ACTION_BUTTON
 
- H5000_GPIO_ASIC_INT_N
 
- H5000_GPIO_BACKUP_POWER
 
- H5000_GPIO_BT_2V8_N
 
- H5000_GPIO_BT_CTS
 
- H5000_GPIO_BT_ENV_0
 
- H5000_GPIO_BT_ENV_1
 
- H5000_GPIO_BT_M_RESET
 
- H5000_GPIO_BT_RTS
 
- H5000_GPIO_BT_RXD
 
- H5000_GPIO_BT_TXD
 
- H5000_GPIO_BT_WU
 
- H5000_GPIO_CHG_EN
 
- H5000_GPIO_CIR_RESET
 
- H5000_GPIO_COM_CTS
 
- H5000_GPIO_COM_DCD
 
- H5000_GPIO_COM_DCD_SOMETHING
 
- H5000_GPIO_COM_DSR
 
- H5000_GPIO_COM_DTR
 
- H5000_GPIO_COM_RI
 
- H5000_GPIO_COM_RTS
 
- H5000_GPIO_COM_RXD
 
- H5000_GPIO_COM_TXD
 
- H5000_GPIO_EXT_CHG_RATE
 
- H5000_GPIO_HEADPHONE_DETECT
 
- H5000_GPIO_I2S_BITCLK
 
- H5000_GPIO_I2S_DATAIN
 
- H5000_GPIO_I2S_DATAOUT
 
- H5000_GPIO_I2S_LRCLK
 
- H5000_GPIO_I2S_SYSCLK
 
- H5000_GPIO_IOIS16_N
 
- H5000_GPIO_IRDA_RXD
 
- H5000_GPIO_IRDA_SD
 
- H5000_GPIO_IRDA_TXD
 
- H5000_GPIO_MOTOR_ON_N
 
- H5000_GPIO_OE_RD_NWR
 
- H5000_GPIO_OPT_INT
 
- H5000_GPIO_OPT_NVRAM
 
- H5000_GPIO_OPT_SPI_CLK
 
- H5000_GPIO_OPT_SPI_CS_N
 
- H5000_GPIO_OPT_SPI_DIN
 
- H5000_GPIO_OPT_SPI_DOUT
 
- H5000_GPIO_PCE1_N
 
- H5000_GPIO_PCE2_N
 
- H5000_GPIO_PIOR_N
 
- H5000_GPIO_PIOW_N
 
- H5000_GPIO_POE_N
 
- H5000_GPIO_POWER_ACCEL_N
 
- H5000_GPIO_POWER_BUTTON
 
- H5000_GPIO_POWER_LIGHT_SENSOR_N
 
- H5000_GPIO_POWER_RS232_N
 
- H5000_GPIO_POWER_SD_N
 
- H5000_GPIO_PREG_N
 
- H5000_GPIO_PSKTSEL
 
- H5000_GPIO_PWAIT_N
 
- H5000_GPIO_PWE_N
 
- H5000_GPIO_RESET_BUTTON_AGAIN_N
 
- H5000_GPIO_RESET_BUTTON_N
 
- H5000_GPIO_RSO_N
 
- H5000_GPIO_SD_WP_N
 
- H5000_GPIO_STD_CHG_RATE
 
- H5000_GPIO_USB_CHG_RATE
 
- H5000_GPIO_USB_PULLUP
 
- H5_ACK_TIMEOUT
 
- H5_ACTIVE
 
- H5_AWAKE
 
- H5_HDR_ACK
 
- H5_HDR_CRC
 
- H5_HDR_LEN
 
- H5_HDR_PKT_TYPE
 
- H5_HDR_RELIABLE
 
- H5_HDR_SEQ
 
- H5_INITIALIZED
 
- H5_MAX_LEN
 
- H5_RX_ESC
 
- H5_SLEEPING
 
- H5_SYNC_TIMEOUT
 
- H5_TX_ACK_REQ
 
- H5_TX_WIN_MAX
 
- H5_UNINITIALIZED
 
- H5_WAKING_UP
 
- H620_HIF_DATA_DONE
 
- H620_HIF_DATA_MASK
 
- H620_HIF_GET_DATA
 
- H620_HIF_GET_RESP
 
- H620_HIF_IDLE
 
- H620_HIF_RESET
 
- H620_HIF_SEND_DATA
 
- H620_HIF_UNKNOWN
 
- H620_MAX_ISTREAMS
 
- H620_MAX_OSTREAMS
 
- H6READ
 
- H6WRITE
 
- H8300_GEN_BITOP
 
- H8300_GEN_TEST_BITOP
 
- H8300_REGS_NO
 
- H9632
 
- H9632_DS_CHANNELS
 
- H9632_QS_CHANNELS
 
- H9632_SS_CHANNELS
 
- H9652
 
- H9652_DS_CHANNELS
 
- H9652_SS_CHANNELS
 
- HA2_TYPE
 
- HABANALABSP_H_
 
- HABANALABS_H_
 
- HAC
 
- HAC0
 
- HAC0_BITCLK_MARK
 
- HAC0_SDIN_MARK
 
- HAC0_SDOUT_MARK
 
- HAC0_SYNC_MARK
 
- HAC1
 
- HAC1_BITCLK_MARK
 
- HAC1_SDIN_MARK
 
- HAC1_SDOUT_MARK
 
- HAC1_SYNC_MARK
 
- HACACR
 
- HACC
 
- HACCR
 
- HACCSAR
 
- HACCSDR
 
- HACKED_OVERTEMP
 
- HACMD_FNLOCK_OFF
 
- HACMD_FNLOCK_ON
 
- HACPCML
 
- HACPCMR
 
- HACREG
 
- HACRIER
 
- HACRSR
 
- HACTBL_SIZE
 
- HACTIER
 
- HACTIVE_LO
 
- HACTIVE_MASK
 
- HACTIVE_SHIFT
 
- HACTSR
 
- HACT_LEN
 
- HAC_RES_MARK
 
- HADDAVE
 
- HADDR_1
 
- HADDR_2
 
- HAD_DEFAULT_BUFFER
 
- HAD_FIFO_SIZE
 
- HAD_MAX_BUFFER
 
- HAD_MAX_CHANNEL
 
- HAD_MAX_DIP_WORDS
 
- HAD_MAX_PERIODS
 
- HAD_MAX_PERIOD_BYTES
 
- HAD_MAX_RATE
 
- HAD_MAX_RATE_DP_1_62_MAUD_VAL
 
- HAD_MAX_RATE_DP_2_7_MAUD_VAL
 
- HAD_MIN_CHANNEL
 
- HAD_MIN_PERIODS
 
- HAD_MIN_PERIOD_BYTES
 
- HAD_MIN_RATE
 
- HAD_NUM_OF_RING_BUFS
 
- HAD_REG_WIDTH
 
- HAF
 
- HAFDUP_COLLISION_WINDOW
 
- HAFDUP_EXCESS_DEFER
 
- HAFDUP_RETRANSMISSION_MAX
 
- HAFDUP_RETRANSMISSION_MAX_SHIFT
 
- HAF_MASK
 
- HAF_SHIFT
 
- HAIER_PRODUCT_CE100
 
- HAIER_PRODUCT_CE81B
 
- HAIER_VENDOR_ID
 
- HAIMR_READ
 
- HAIMR_READ_START
 
- HAIMR_TRANS_END
 
- HAIMR_TRANS_START
 
- HAIMR_WRITE
 
- HAIMR_WRITE_START
 
- HAINAN_GB_ADDR_CONFIG_GOLDEN
 
- HAINAN_SMC_UCODE_SIZE
 
- HAINAN_SMC_UCODE_START
 
- HAINT
 
- HAINTMSK
 
- HAL2_PBUS_DMACFG
 
- HAL92C_EN_PKT_LIFE_TIME_BE
 
- HAL92C_EN_PKT_LIFE_TIME_BK
 
- HAL92C_EN_PKT_LIFE_TIME_VI
 
- HAL92C_EN_PKT_LIFE_TIME_VO
 
- HAL92C_MSDU_LIFE_TIME_UNIT
 
- HAL92C_WOL_DEAUTH_EVENT
 
- HAL92C_WOL_DISASSOC_EVENT
 
- HAL92C_WOL_FW_DISCONNECT_EVENT
 
- HAL92C_WOL_GTK_UPDATE_EVENT
 
- HAL92C_WOL_PTK_UPDATE_EVENT
 
- HALCYON_CMDB
 
- HALCYON_CMDBMASK
 
- HALCYON_FIRECMD
 
- HALCYON_FIREMASK
 
- HALCYON_HEADER1
 
- HALCYON_HEADER1MASK
 
- HALCYON_HEADER2
 
- HALCYON_SUB_ADDR0
 
- HALF
 
- HALF10
 
- HALF100
 
- HALFDUP_ALT_BEB
 
- HALFDUP_ALT_BEB_TRUNCATION_MAX
 
- HALFDUP_ALT_BEB_TRUNCATION_SHIFT
 
- HALFDUP_ALT_BEB_TR_MASK
 
- HALFDUP_BACK_PRESSURE_NO_BACKOFF
 
- HALFDUP_COLLISION_WINDOW_MAX
 
- HALFDUP_COLLISION_WINDOW_SHIFT
 
- HALFDUP_COL_WINDOW_MASK
 
- HALFDUP_EXCESSIVE_DEFER
 
- HALFDUP_MAX_RETRANSMISSION_MAX
 
- HALFDUP_MAX_RETRANSMISSION_SHIFT
 
- HALFDUP_NO_BACKOFF
 
- HALFDUP_RETRANS_MASK
 
- HALFLIFE
 
- HALF_BASE_FREQ
 
- HALF_CAM_ENTRY
 
- HALF_DUPLEX
 
- HALF_DUPLEX_SIGNAL_BUG
 
- HALF_DUP_RX
 
- HALF_DUP_TX
 
- HALF_FULL
 
- HALF_LONG_BITS
 
- HALF_QUEUES
 
- HALF_RATE_SHIFT
 
- HALF_SAM
 
- HALF_SLICE_CHICKEN2
 
- HALF_SLICE_CHICKEN3
 
- HALF_US
 
- HALF_VTCLOCK
 
- HALIBUT_ID
 
- HALO_AHBM_CORE_ERR_ADDR_MASK
 
- HALO_AHBM_CORE_ERR_ADDR_SHIFT
 
- HALO_AHBM_FLAGS_ERR_MASK
 
- HALO_AHBM_WINDOW_DEBUG_0
 
- HALO_AHBM_WINDOW_DEBUG_1
 
- HALO_CCM_CORE_CONTROL
 
- HALO_CORE_EN
 
- HALO_CORE_SOFT_RESET
 
- HALO_CORE_SOFT_RESET_MASK
 
- HALO_MPU_LOCK_CONFIG
 
- HALO_MPU_PM_VIO_ADDR
 
- HALO_MPU_PM_VIO_STATUS
 
- HALO_MPU_VIO_ERR_SRC_MASK
 
- HALO_MPU_VIO_ERR_SRC_SHIFT
 
- HALO_MPU_VIO_ERR_WR_MASK
 
- HALO_MPU_VIO_STS_MASK
 
- HALO_MPU_VIO_STS_SHIFT
 
- HALO_MPU_WINDOW_ACCESS_0
 
- HALO_MPU_WINDOW_ACCESS_1
 
- HALO_MPU_WINDOW_ACCESS_2
 
- HALO_MPU_WINDOW_ACCESS_3
 
- HALO_MPU_XMEM_ACCESS_0
 
- HALO_MPU_XMEM_ACCESS_1
 
- HALO_MPU_XMEM_ACCESS_2
 
- HALO_MPU_XMEM_ACCESS_3
 
- HALO_MPU_XM_VIO_ADDR
 
- HALO_MPU_XM_VIO_STATUS
 
- HALO_MPU_XREG_ACCESS_0
 
- HALO_MPU_XREG_ACCESS_1
 
- HALO_MPU_XREG_ACCESS_2
 
- HALO_MPU_XREG_ACCESS_3
 
- HALO_MPU_YMEM_ACCESS_0
 
- HALO_MPU_YMEM_ACCESS_1
 
- HALO_MPU_YMEM_ACCESS_2
 
- HALO_MPU_YMEM_ACCESS_3
 
- HALO_MPU_YM_VIO_ADDR
 
- HALO_MPU_YM_VIO_STATUS
 
- HALO_MPU_YREG_ACCESS_0
 
- HALO_MPU_YREG_ACCESS_1
 
- HALO_MPU_YREG_ACCESS_2
 
- HALO_MPU_YREG_ACCESS_3
 
- HALO_SCRATCH1
 
- HALO_SCRATCH2
 
- HALO_SCRATCH3
 
- HALO_SCRATCH4
 
- HALO_WDT_CONTROL
 
- HALO_WDT_EN_MASK
 
- HALT
 
- HALTCODE_MASK
 
- HALT_ACK_TIMEOUT_MS
 
- HALT_BIT
 
- HALT_CARD_DISABLED
 
- HALT_CHECK_MAX_LOOPS
 
- HALT_INST
 
- HALT_MACH
 
- HALT_NIC
 
- HALT_REALTEK_ALC5505
 
- HALT_STATUS_RECOVERABLE
 
- HALT_STATUS_UNRECOVERABLE
 
- HALT_WAKEUP
 
- HAL_8188E_HW_GPIO_WPS_BIT
 
- HAL_8192C_HW_GPIO_WPS_BIT
 
- HAL_8192EU_HW_GPIO_WPS_BIT
 
- HAL_8192S_HW_GPIO_OFF_BIT
 
- HAL_8192S_HW_GPIO_OFF_MASK
 
- HAL_8192S_HW_GPIO_WPS_BIT
 
- HAL_92C_NAV_UPPER_UNIT
 
- HAL_ATLANTIC_RATE_100M
 
- HAL_ATLANTIC_RATE_10G
 
- HAL_ATLANTIC_RATE_1G
 
- HAL_ATLANTIC_RATE_2GS
 
- HAL_ATLANTIC_RATE_5G
 
- HAL_ATLANTIC_RATE_5GSR
 
- HAL_ATLANTIC_RATE_INVALID
 
- HAL_ATLANTIC_UTILS_CHIP_MIPS
 
- HAL_ATLANTIC_UTILS_CHIP_MPI_AQ
 
- HAL_ATLANTIC_UTILS_CHIP_REVISION_A0
 
- HAL_ATLANTIC_UTILS_CHIP_REVISION_B0
 
- HAL_ATLANTIC_UTILS_CHIP_REVISION_B1
 
- HAL_ATLANTIC_UTILS_CHIP_RPF2
 
- HAL_ATLANTIC_UTILS_CHIP_TPO2
 
- HAL_ATLANTIC_UTILS_FW2X_MSG_WOL
 
- HAL_ATLANTIC_UTILS_FW_MSG_ARP
 
- HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG
 
- HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP
 
- HAL_ATLANTIC_UTILS_FW_MSG_INJECT
 
- HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC
 
- HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD
 
- HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL
 
- HAL_ATLANTIC_UTILS_FW_MSG_PING
 
- HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING
 
- HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD
 
- HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL
 
- HAL_ATLANTIC_UTILS_FW_MSG_WOL_MAG_PKT
 
- HAL_ATLANTIC_UTILS_FW_MSG_WOL_PATTERN
 
- HAL_ATLANTIC_UTILS_FW_MSG_WOL_PRIOR
 
- HAL_ATLANTIC_WOL_FILTERS_COUNT
 
- HAL_ATL_B0_LSO_IPV6_MAX_SEGMENT_SIZE
 
- HAL_ATL_B0_LSO_MAX_SEGMENT_SIZE
 
- HAL_BB_ENABLE
 
- HAL_BTC8723B2ANT_DMA_DURATION_ADJUST
 
- HAL_CHIP_TYPE
 
- HAL_CHIP_TYPE_E
 
- HAL_CUT_VERSION
 
- HAL_CUT_VERSION_E
 
- HAL_DEF_ANT_DETECT
 
- HAL_DEF_CURRENT_ANTENNA
 
- HAL_DEF_DBG_DM_FUNC
 
- HAL_DEF_DBG_DUMP_RXPKT
 
- HAL_DEF_DBG_DUMP_TXPKT
 
- HAL_DEF_DBG_RX_INFO_DUMP
 
- HAL_DEF_DRVINFO_SZ
 
- HAL_DEF_EXPLICIT_BEAMFORMEE
 
- HAL_DEF_EXPLICIT_BEAMFORMER
 
- HAL_DEF_IS_SUPPORT_ANT_DIV
 
- HAL_DEF_MACID_SLEEP
 
- HAL_DEF_MAX_RECVBUF_SZ
 
- HAL_DEF_PCI_AMD_L1_SUPPORT
 
- HAL_DEF_PCI_ASPM_OSC
 
- HAL_DEF_PCI_SUUPORT_L1_BACKDOOR
 
- HAL_DEF_PT_PWR_STATUS
 
- HAL_DEF_RA_DECISION_RATE
 
- HAL_DEF_RA_SGI
 
- HAL_DEF_RX_LDPC
 
- HAL_DEF_RX_PACKET_OFFSET
 
- HAL_DEF_RX_STBC
 
- HAL_DEF_TX_LDPC
 
- HAL_DEF_TX_PAGE_BOUNDARY
 
- HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN
 
- HAL_DEF_TX_PAGE_SIZE
 
- HAL_DEF_TX_STBC
 
- HAL_DEF_UNDERCORATEDSMOOTHEDPWDB
 
- HAL_DEF_VARIABLE
 
- HAL_DEF_WOWLAN
 
- HAL_DM_DIG_DISABLE
 
- HAL_DM_HIPWR_DISABLE
 
- HAL_EFUSE_MEMORY
 
- HAL_FILTER_CMP_TYPE_EQUAL
 
- HAL_FILTER_CMP_TYPE_INVALID
 
- HAL_FILTER_CMP_TYPE_MASK_EQUAL
 
- HAL_FILTER_CMP_TYPE_MAX
 
- HAL_FILTER_CMP_TYPE_NOT_EQUAL
 
- HAL_FILTER_PROTO_TYPE_ARP
 
- HAL_FILTER_PROTO_TYPE_INVALID
 
- HAL_FILTER_PROTO_TYPE_IPV4
 
- HAL_FILTER_PROTO_TYPE_IPV6
 
- HAL_FILTER_PROTO_TYPE_MAC
 
- HAL_FILTER_PROTO_TYPE_MAX
 
- HAL_FILTER_PROTO_TYPE_UDP
 
- HAL_FW_ENABLE
 
- HAL_GLOBAL_CLASS_A_STATS_INFO
 
- HAL_GLOBAL_CLASS_B_STATS_INFO
 
- HAL_GLOBAL_CLASS_C_STATS_INFO
 
- HAL_GLOBAL_CLASS_D_STATS_INFO
 
- HAL_HW_PCI_REVISION_ID_8192PCIE
 
- HAL_HW_PCI_REVISION_ID_8192SE
 
- HAL_IC_TYPE_E
 
- HAL_INIT_PROFILE_TAG
 
- HAL_INTF_PS_FUNC
 
- HAL_IsLegalChannel
 
- HAL_MAC_ENABLE
 
- HAL_MAX_CONCURRENCY_PERSONA
 
- HAL_MAX_ID
 
- HAL_MSG_TIMEOUT
 
- HAL_NAV_UPPER_UNIT
 
- HAL_NAV_UPPER_UNIT_8723B
 
- HAL_NIC_UNPLUG_ISR
 
- HAL_NIC_UNPLUG_PCI_ISR
 
- HAL_ODM_NOISE_MONITOR
 
- HAL_ODM_P2P_STATE
 
- HAL_ODM_STA_INFO
 
- HAL_ODM_VARIABLE
 
- HAL_ODM_WIFI_DISPLAY_STATE
 
- HAL_P2P_CLIENT
 
- HAL_P2P_GO
 
- HAL_PER_STA_STATS_INFO
 
- HAL_PRIME_CHNL_OFFSET_DONT_CARE
 
- HAL_PRIME_CHNL_OFFSET_LOWER
 
- HAL_PRIME_CHNL_OFFSET_UPPER
 
- HAL_PS_TIMER_INT_DELAY
 
- HAL_RCV_FILTER_TYPE_BUFFER_PKT
 
- HAL_RCV_FILTER_TYPE_FILTER_PKT
 
- HAL_RCV_FILTER_TYPE_INVALID
 
- HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
 
- HAL_RF_ENABLE
 
- HAL_RF_TYPE_E
 
- HAL_SAP
 
- HAL_STA
 
- HAL_STATUS
 
- HAL_STATUS_FAILURE
 
- HAL_STATUS_SUCCESS
 
- HAL_STA_SAP
 
- HAL_STOP_TYPE_MAX
 
- HAL_STOP_TYPE_RF_KILL
 
- HAL_STOP_TYPE_SYS_DEEP_SLEEP
 
- HAL_STOP_TYPE_SYS_RESET
 
- HAL_SUMMARY_STATS_INFO
 
- HAL_SYS_MODE_LEARN
 
- HAL_SYS_MODE_MAX
 
- HAL_SYS_MODE_NORMAL
 
- HAL_SYS_MODE_PROMISC
 
- HAL_SYS_MODE_ROAM_SCAN
 
- HAL_SYS_MODE_ROAM_SUSPEND_LINK
 
- HAL_SYS_MODE_SCAN
 
- HAL_SYS_MODE_SUSPEND_LINK
 
- HAL_THERMAL_MITIGATION_LEVEL_0
 
- HAL_THERMAL_MITIGATION_LEVEL_1
 
- HAL_THERMAL_MITIGATION_LEVEL_2
 
- HAL_THERMAL_MITIGATION_LEVEL_3
 
- HAL_THERMAL_MITIGATION_LEVEL_4
 
- HAL_THERMAL_MITIGATION_LEVEL_INVALID
 
- HAL_THERMAL_MITIGATION_LEVEL_MAX
 
- HAL_THERMAL_MITIGATION_MODE_0
 
- HAL_THERMAL_MITIGATION_MODE_1
 
- HAL_THERMAL_MITIGATION_MODE_2
 
- HAL_THERMAL_MITIGATION_MODE_INVALID
 
- HAL_THERMAL_MITIGATION_MODE_MAX
 
- HAL_TX_RATE_HT20
 
- HAL_TX_RATE_HT40
 
- HAL_TX_RATE_LEGACY
 
- HAL_TX_RATE_LGI
 
- HAL_TX_RATE_SGI
 
- HAL_USB_SELECT_SUSPEND
 
- HAL_VENDOR
 
- HAL_VENDOR_E
 
- HAL_VERSION
 
- HAMEG_HO720_PID
 
- HAMEG_HO730_PID
 
- HAMEG_HO820_PID
 
- HAMEG_HO870_PID
 
- HAMMERHEAD_BASE
 
- HAMPSHIRE_FORMAT_LENGTH
 
- HAMPSHIRE_FORMAT_TOUCH_BIT
 
- HAMPSHIRE_GET_TOUCHED
 
- HAMPSHIRE_GET_XC
 
- HAMPSHIRE_GET_YC
 
- HAMPSHIRE_MAX_XC
 
- HAMPSHIRE_MAX_YC
 
- HAMPSHIRE_MIN_XC
 
- HAMPSHIRE_MIN_YC
 
- HAMPSHIRE_RESPONSE_BEGIN_BYTE
 
- HANA_FILENAME
 
- HANDED_OVER_TO_NETWORK
 
- HANDLE
 
- HANDLER_ONCHANGE
 
- HANDLER_ONMATCH
 
- HANDLER_ONMAX
 
- HANDLE_COUNTER
 
- HANDLE_DEATH_LIST
 
- HANDLE_DEATH_PENDING
 
- HANDLE_FLAG
 
- HANDLE_FLAG_MASK
 
- HANDLE_IS_CTIO_COMP
 
- HANDLE_PIN_BIT
 
- HANDLE_STATE_SHIFT
 
- HANDN_BIT
 
- HANDSET_IN_LOCAL
 
- HANDSET_IN_MUTE
 
- HANDSET_IN_REMOTE
 
- HANDSET_OUT_BOTH
 
- HANDSET_OUT_LOCAL
 
- HANDSET_OUT_MUTE
 
- HANDSET_OUT_REMOTE
 
- HANDSHAKE
 
- HANDSHAKE_DONESTATE
 
- HANDSHAKE_READYSTATE
 
- HANDSHAKE_REG
 
- HANDSHAKE_SIGNATURE
 
- HANDSHAKE_TIMEOUT
 
- HANDSPRING_TREO600_ID
 
- HANDSPRING_TREO_ID
 
- HANDSPRING_VENDOR_ID
 
- HANDSPRING_VISOR_ID
 
- HANDYLINK_PID
 
- HANGUL
 
- HANGUL_SYLLABLE
 
- HANTRO_DECODERS
 
- HANTRO_ENCODERS
 
- HANTRO_G1_REGS_H_
 
- HANTRO_H1_REGS_H_
 
- HANTRO_H264_DECODER
 
- HANTRO_H264_DPB_SIZE
 
- HANTRO_HW_H_
 
- HANTRO_H_
 
- HANTRO_JPEG_ENCODER
 
- HANTRO_MODE_H264_DEC
 
- HANTRO_MODE_JPEG_ENC
 
- HANTRO_MODE_MPEG2_DEC
 
- HANTRO_MODE_NONE
 
- HANTRO_MODE_VP8_DEC
 
- HANTRO_MPEG2_DECODER
 
- HANTRO_V4L2_H_
 
- HANTRO_VP8_DECODER
 
- HANWANG_ART_MASTER_HD
 
- HANWANG_ART_MASTER_II
 
- HANWANG_ART_MASTER_III
 
- HANWANG_TABLET_DEVICE
 
- HANWANG_TABLET_INT_CLASS
 
- HANWANG_TABLET_INT_PROTOCOL
 
- HANWANG_TABLET_INT_SUB_CLASS
 
- HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 
- HARDIRQ_BITS
 
- HARDIRQ_DISABLE
 
- HARDIRQ_ENABLE
 
- HARDIRQ_ENTER
 
- HARDIRQ_EXIT
 
- HARDIRQ_MASK
 
- HARDIRQ_OFFSET
 
- HARDIRQ_SHIFT
 
- HARDIRQ_VERBOSE
 
- HARDIRQ_verbose
 
- HARDRESET_EN
 
- HARDRESET_RETRIES
 
- HARDRST
 
- HARDRSTDET
 
- HARDWARE
 
- HARDWARE_ASN_MASK
 
- HARDWARE_EN
 
- HARDWARE_ERR
 
- HARDWARE_ERROR
 
- HARDWARE_TYPE_930
 
- HARDWARE_TYPE_MAX
 
- HARDWARE_TYPE_NUM
 
- HARDWARE_TYPE_RTL8188EE
 
- HARDWARE_TYPE_RTL8188EU
 
- HARDWARE_TYPE_RTL8192CE
 
- HARDWARE_TYPE_RTL8192CU
 
- HARDWARE_TYPE_RTL8192DE
 
- HARDWARE_TYPE_RTL8192DU
 
- HARDWARE_TYPE_RTL8192E
 
- HARDWARE_TYPE_RTL8192EE
 
- HARDWARE_TYPE_RTL8192SE
 
- HARDWARE_TYPE_RTL8192SU
 
- HARDWARE_TYPE_RTL8192U
 
- HARDWARE_TYPE_RTL8723AE
 
- HARDWARE_TYPE_RTL8723BE
 
- HARDWARE_TYPE_RTL8723U
 
- HARDWARE_TYPE_RTL8812AE
 
- HARDWARE_TYPE_RTL8821AE
 
- HARDWARE_TYPE_RTL8822BE
 
- HARDWARE_TYPE_TIUMP
 
- HARDWARE_VOL_CTRL
 
- HARD_ABORT
 
- HARD_ACS_RDY_POLL_NS
 
- HARD_LEBS_LIMIT
 
- HARD_MSGMAX
 
- HARD_MSGSIZEMAX
 
- HARD_PHY_LINKRATE
 
- HARD_RESET
 
- HARD_RESET_DELAY_MS
 
- HARD_RESET_NOW
 
- HARD_RST_CTRL__CORE_RST_EN_MASK
 
- HARD_RST_CTRL__CORE_RST_EN__MASK
 
- HARD_RST_CTRL__CORE_RST_EN__SHIFT
 
- HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK
 
- HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK
 
- HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT
 
- HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK
 
- HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK
 
- HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT
 
- HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK
 
- HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK
 
- HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT
 
- HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK
 
- HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK
 
- HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT
 
- HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK
 
- HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK
 
- HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT
 
- HARD_RST_CTRL__EP_CFG_RST_EN_MASK
 
- HARD_RST_CTRL__EP_CFG_RST_EN__MASK
 
- HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT
 
- HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK
 
- HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK
 
- HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT
 
- HARD_RST_CTRL__EP_PRV_RST_EN_MASK
 
- HARD_RST_CTRL__EP_PRV_RST_EN__MASK
 
- HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT
 
- HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK
 
- HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK
 
- HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT
 
- HARD_RST_CTRL__RELOAD_STRAP_EN_MASK
 
- HARD_RST_CTRL__RELOAD_STRAP_EN__MASK
 
- HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT
 
- HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK
 
- HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK
 
- HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT
 
- HARD_SCORN_SECS
 
- HARD_TX_LOCK
 
- HARD_TX_TRYLOCK
 
- HARD_TX_UNLOCK
 
- HARD_ZERO
 
- HARMONY_CNTL
 
- HARMONY_CNTL_44100
 
- HARMONY_CNTL_8000
 
- HARMONY_CNTL_C
 
- HARMONY_CNTL_ST
 
- HARMONY_CONTROLS
 
- HARMONY_DF_16BIT_LINEAR
 
- HARMONY_DF_8BIT_ALAW
 
- HARMONY_DF_8BIT_ULAW
 
- HARMONY_DIAG
 
- HARMONY_DSTATUS
 
- HARMONY_DSTATUS_ID
 
- HARMONY_DSTATUS_IE
 
- HARMONY_DSTATUS_PN
 
- HARMONY_DSTATUS_RN
 
- HARMONY_GAINCTL
 
- HARMONY_GAIN_DEFAULT
 
- HARMONY_GAIN_HE_MASK
 
- HARMONY_GAIN_HE_SHIFT
 
- HARMONY_GAIN_IN
 
- HARMONY_GAIN_IS_MASK
 
- HARMONY_GAIN_IS_SHIFT
 
- HARMONY_GAIN_LE_MASK
 
- HARMONY_GAIN_LE_SHIFT
 
- HARMONY_GAIN_LI_MASK
 
- HARMONY_GAIN_LI_SHIFT
 
- HARMONY_GAIN_LO_MASK
 
- HARMONY_GAIN_LO_SHIFT
 
- HARMONY_GAIN_MA
 
- HARMONY_GAIN_MA_MASK
 
- HARMONY_GAIN_MA_SHIFT
 
- HARMONY_GAIN_OUT
 
- HARMONY_GAIN_RI_MASK
 
- HARMONY_GAIN_RI_SHIFT
 
- HARMONY_GAIN_RO_MASK
 
- HARMONY_GAIN_RO_SHIFT
 
- HARMONY_GAIN_SE_MASK
 
- HARMONY_GAIN_SE_SHIFT
 
- HARMONY_GAIN_SILENCE
 
- HARMONY_ID
 
- HARMONY_MAX_IN
 
- HARMONY_MAX_MON
 
- HARMONY_MAX_OUT
 
- HARMONY_OV
 
- HARMONY_PCURADD
 
- HARMONY_PIO
 
- HARMONY_PNXTADD
 
- HARMONY_RCURADD
 
- HARMONY_RESET
 
- HARMONY_RNXTADD
 
- HARMONY_SIZE
 
- HARMONY_SR_11KHZ
 
- HARMONY_SR_16KHZ
 
- HARMONY_SR_18KHZ
 
- HARMONY_SR_22KHZ
 
- HARMONY_SR_27KHZ
 
- HARMONY_SR_32KHZ
 
- HARMONY_SR_33KHZ
 
- HARMONY_SR_37KHZ
 
- HARMONY_SR_44KHZ
 
- HARMONY_SR_48KHZ
 
- HARMONY_SR_5KHZ
 
- HARMONY_SR_6KHZ
 
- HARMONY_SR_8KHZ
 
- HARMONY_SR_9KHZ
 
- HARMONY_SS_MONO
 
- HARMONY_SS_STEREO
 
- HARMONY_VOLUME
 
- HARPOON_FAMILY
 
- HARVARD_CACHE
 
- HARVARD_TLB
 
- HARVEST_INFO
 
- HAS
 
- HASH
 
- HASH1
 
- HASH1_R
 
- HASH1_TX_REG_OFFSET
 
- HASH2
 
- HASH2_R
 
- HASHALL_F
 
- HASHALL_S
 
- HASHALL_V
 
- HASHDELAY_G
 
- HASHDELAY_M
 
- HASHDELAY_S
 
- HASHDELAY_V
 
- HASHDIST_DEFAULT
 
- HASHED_PAGE_VIRTUAL
 
- HASHED_SAS_ADDR_SIZE
 
- HASHEN
 
- HASHEN_F
 
- HASHEN_S
 
- HASHEN_V
 
- HASHETH_F
 
- HASHETH_S
 
- HASHETH_V
 
- HASHH
 
- HASHIE
 
- HASHIF
 
- HASHL
 
- HASHLIMIT_MAX_SIZE
 
- HASHLST
 
- HASHMAP_ADD
 
- HASHMAP_APPEND
 
- HASHMAP_INIT
 
- HASHMAP_MIN_CAP_BITS
 
- HASHMAP_SET
 
- HASHMAP_UPDATE
 
- HASHOP
 
- HASHSRAM_F
 
- HASHSRAM_S
 
- HASHSRAM_V
 
- HASHSZ
 
- HASHTAB_MAX_NODES
 
- HASHTIDSIZE_G
 
- HASHTIDSIZE_M
 
- HASHTIDSIZE_S
 
- HASHTOEPLITZ_F
 
- HASHTOEPLITZ_S
 
- HASHTOEPLITZ_V
 
- HASH_ACTION_RDCOFF
 
- HASH_ACTION_RDCOFF_SHIFT
 
- HASH_ACTION_RESV1
 
- HASH_ACTION_RESV2
 
- HASH_ACTION_RESV3
 
- HASH_ACTION_USERINFO
 
- HASH_ACTION_USERINFO_SHIFT
 
- HASH_ACTION_ZFID
 
- HASH_ACTION_ZFID_SHIFT
 
- HASH_ACTION_ZFVALID
 
- HASH_ACTV_HIT_G
 
- HASH_ACTV_HIT_M
 
- HASH_ACTV_HIT_S
 
- HASH_ACTV_HIT_V
 
- HASH_ADD
 
- HASH_ADDR
 
- HASH_ADDR_TABLE_SIZE
 
- HASH_ALG
 
- HASH_ALGO_MD4
 
- HASH_ALGO_MD5
 
- HASH_ALGO_RIPE_MD_128
 
- HASH_ALGO_RIPE_MD_160
 
- HASH_ALGO_RIPE_MD_256
 
- HASH_ALGO_RIPE_MD_320
 
- HASH_ALGO_SHA1
 
- HASH_ALGO_SHA224
 
- HASH_ALGO_SHA256
 
- HASH_ALGO_SHA384
 
- HASH_ALGO_SHA512
 
- HASH_ALGO_SM3_256
 
- HASH_ALGO_STREEBOG_256
 
- HASH_ALGO_STREEBOG_512
 
- HASH_ALGO_TGR_128
 
- HASH_ALGO_TGR_160
 
- HASH_ALGO_TGR_192
 
- HASH_ALGO_WP_256
 
- HASH_ALGO_WP_384
 
- HASH_ALGO_WP_512
 
- HASH_ALGO__LAST
 
- HASH_ALG_AES
 
- HASH_ALG_LAST
 
- HASH_ALG_MD5
 
- HASH_ALG_NONE
 
- HASH_ALG_SHA1
 
- HASH_ALG_SHA224
 
- HASH_ALG_SHA256
 
- HASH_ALG_SHA384
 
- HASH_ALG_SHA3_224
 
- HASH_ALG_SHA3_256
 
- HASH_ALG_SHA3_384
 
- HASH_ALG_SHA3_512
 
- HASH_ALG_SHA512
 
- HASH_ALG_SHIFT
 
- HASH_ALL
 
- HASH_AUTOSUSPEND_DELAY
 
- HASH_BITS
 
- HASH_BLOCK_SIZE
 
- HASH_BUCKETS
 
- HASH_BUCKET_BITS
 
- HASH_BUFLEN
 
- HASH_BYTES_PER_WORD
 
- HASH_CACHE_SIZE
 
- HASH_CARRY_MAX
 
- HASH_CELL_ID0
 
- HASH_CELL_ID1
 
- HASH_CELL_ID2
 
- HASH_CELL_ID3
 
- HASH_CIPHER_DO_PADDING_RESERVE32
 
- HASH_CK
 
- HASH_CLEAR_BITS
 
- HASH_CONFIG1_PADDING_RESERVE32
 
- HASH_CR
 
- HASH_CR_ALGO_MASK
 
- HASH_CR_ALGO_MD5
 
- HASH_CR_ALGO_POS
 
- HASH_CR_ALGO_SHA1
 
- HASH_CR_ALGO_SHA224
 
- HASH_CR_ALGO_SHA256
 
- HASH_CR_DATAFORM_MASK
 
- HASH_CR_DATAFORM_POS
 
- HASH_CR_DATATYPE_POS
 
- HASH_CR_DINF_MASK
 
- HASH_CR_DINF_POS
 
- HASH_CR_DMAA
 
- HASH_CR_DMAE
 
- HASH_CR_DMAE_MASK
 
- HASH_CR_DMAE_POS
 
- HASH_CR_EMPTYMSG_MASK
 
- HASH_CR_EMPTYMSG_POS
 
- HASH_CR_INIT
 
- HASH_CR_INIT_MASK
 
- HASH_CR_INIT_POS
 
- HASH_CR_LKEY
 
- HASH_CR_LKEY_MASK
 
- HASH_CR_LKEY_POS
 
- HASH_CR_MDMAT
 
- HASH_CR_MODE
 
- HASH_CR_MODE_MASK
 
- HASH_CR_MODE_POS
 
- HASH_CR_NBW_MASK
 
- HASH_CR_NBW_POS
 
- HASH_CR_PRIVN_MASK
 
- HASH_CR_PRIVN_POS
 
- HASH_CR_RESUME_MASK
 
- HASH_CR_SECN_MASK
 
- HASH_CR_SECN_POS
 
- HASH_CR_SWITCHON_MASK
 
- HASH_CR_SWITCHON_POS
 
- HASH_CSR
 
- HASH_CSR_COUNT
 
- HASH_CSR_REGISTER_NUMBER
 
- HASH_CTRL_ADDR_MASK
 
- HASH_CTRL_MCAST_EN
 
- HASH_DATA_16_BITS
 
- HASH_DATA_1_BIT
 
- HASH_DATA_32_BITS
 
- HASH_DATA_8_BITS
 
- HASH_DCIE
 
- HASH_DEFAULT_SIZE
 
- HASH_DELETE
 
- HASH_DEVICE_ID_0
 
- HASH_DEVICE_ID_1
 
- HASH_DIGEST_RESULT_LITTLE_ENDIAN
 
- HASH_DIN
 
- HASH_DINIE
 
- HASH_DMA_ALIGN_SIZE
 
- HASH_DMA_FIFO
 
- HASH_DMA_PERFORMANCE_MIN_SIZE
 
- HASH_DMA_THRESHOLD
 
- HASH_EARLY
 
- HASH_ENTRY_RECEIVE_DISCARD
 
- HASH_ENTRY_RECEIVE_DISCARD_BIT
 
- HASH_ENTRY_VALID
 
- HASH_F
 
- HASH_FLAGS_ALGO_MASK
 
- HASH_FLAGS_BUSY
 
- HASH_FLAGS_CPU
 
- HASH_FLAGS_DMA_ACTIVE
 
- HASH_FLAGS_DMA_READY
 
- HASH_FLAGS_ERRORS
 
- HASH_FLAGS_FINAL
 
- HASH_FLAGS_FINUP
 
- HASH_FLAGS_HMAC
 
- HASH_FLAGS_HMAC_FINAL
 
- HASH_FLAGS_HMAC_INIT
 
- HASH_FLAGS_HMAC_KEY
 
- HASH_FLAGS_INIT
 
- HASH_FLAGS_MD5
 
- HASH_FLAGS_OUTPUT_READY
 
- HASH_FLAGS_SGS_ALLOCED
 
- HASH_FLAGS_SGS_COPIED
 
- HASH_FLAGS_SHA1
 
- HASH_FLAGS_SHA224
 
- HASH_FLAGS_SHA256
 
- HASH_FLAG_FINALIZE
 
- HASH_FLAG_HMAC
 
- HASH_FLAG_INIT_CTX
 
- HASH_FLAG_UPDATE
 
- HASH_FLAG_UPDATE_KEY
 
- HASH_FN_MASK
 
- HASH_FN_SHIFT
 
- HASH_FUNCTION
 
- HASH_HEADER_EXT
 
- HASH_HEADER_FMT
 
- HASH_HEADER_L2_DADDR
 
- HASH_HEADER_L2_DADDR_SHIFT
 
- HASH_HEADER_RESVD
 
- HASH_HEADER_VALID
 
- HASH_HEADER_VLAN
 
- HASH_HEADER_VLAN_SHIFT
 
- HASH_HIGH_WORD_MAX_VAL
 
- HASH_HREG
 
- HASH_HWCFGR
 
- HASH_ID
 
- HASH_IMR
 
- HASH_INDEX_MASK
 
- HASH_INITIALIZE
 
- HASH_IP4ADDR_DADDR
 
- HASH_IP4ADDR_DADDR_SHIFT
 
- HASH_IP4ADDR_SADDR
 
- HASH_IP4ADDR_SADDR_SHIFT
 
- HASH_IPV4_CTRL
 
- HASH_IPV6_CTRL
 
- HASH_IPV6_EX_CTRL
 
- HASH_KEY
 
- HASH_KEY_SIZE
 
- HASH_KMALLOC
 
- HASH_LEFT
 
- HASH_LEN_DECLARE
 
- HASH_LEN_SIZE_630
 
- HASH_LEN_SIZE_712
 
- HASH_LONG_KEY
 
- HASH_LOOKUP
 
- HASH_LOOKUP_ERR_LOG1
 
- HASH_LOOKUP_ERR_LOG1_CU
 
- HASH_LOOKUP_ERR_LOG1_ERR
 
- HASH_LOOKUP_ERR_LOG1_MULT_BIT
 
- HASH_LOOKUP_ERR_LOG1_MULT_LK
 
- HASH_LOOKUP_ERR_LOG2
 
- HASH_LOOKUP_ERR_LOG2_H1
 
- HASH_LOOKUP_ERR_LOG2_SUBAREA
 
- HASH_LOOKUP_ERR_LOG2_SYNDROME
 
- HASH_MASK
 
- HASH_MASK_CALC_COMPLETION
 
- HASH_MASK_DATA_INPUT
 
- HASH_MAX_BLOCK_SIZE
 
- HASH_MAX_DESCSIZE
 
- HASH_MAX_DIGESTSIZE
 
- HASH_MAX_KEY_SIZE
 
- HASH_MAX_LEN_SIZE
 
- HASH_MAX_STATESIZE
 
- HASH_MD5_MAX_REG
 
- HASH_MIN_SIZE
 
- HASH_MIX
 
- HASH_MODE
 
- HASH_MODE_CCM
 
- HASH_MODE_CMAC
 
- HASH_MODE_CPU
 
- HASH_MODE_CTXT
 
- HASH_MODE_DMA
 
- HASH_MODE_FHMAC
 
- HASH_MODE_GCM
 
- HASH_MODE_HASH
 
- HASH_MODE_HMAC
 
- HASH_MODE_NONE
 
- HASH_MODE_RABIN
 
- HASH_MODE_SHIFT
 
- HASH_MODE_XCBC
 
- HASH_MSG_LEN
 
- HASH_NBLW_MAX_VAL
 
- HASH_NB_ALWAYS
 
- HASH_NUM_OP
 
- HASH_OPER_MODE_HASH
 
- HASH_OPER_MODE_HMAC
 
- HASH_OPT_HEADER_EXT
 
- HASH_OPT_HEADER_FMT
 
- HASH_OPT_HEADER_HASH2
 
- HASH_OPT_HEADER_HASH2_SHIFT
 
- HASH_OPT_HEADER_RDCOFF
 
- HASH_OPT_HEADER_RDCOFF_SHIFT
 
- HASH_OPT_HEADER_RESVD
 
- HASH_OPT_HEADER_USERINFO
 
- HASH_OPT_HEADER_USERINFO_SHIFT
 
- HASH_OPT_HEADER_VALID
 
- HASH_OP_FINAL
 
- HASH_OP_UPDATE
 
- HASH_ORDER
 
- HASH_O_F
 
- HASH_PADDING_DISABLED
 
- HASH_PADDING_ENABLED
 
- HASH_PERF
 
- HASH_PGD_VAL_BITS
 
- HASH_PMD_VAL_BITS
 
- HASH_PORT_DPORT
 
- HASH_PORT_DPORT_SHIFT
 
- HASH_PORT_PORT_OFF
 
- HASH_PORT_PORT_OFF_SHIFT
 
- HASH_PORT_PORT_RESV
 
- HASH_PORT_PROTO
 
- HASH_PORT_PROTO_SHIFT
 
- HASH_PORT_SPORT
 
- HASH_PORT_SPORT_SHIFT
 
- HASH_PREALLOC
 
- HASH_PTR
 
- HASH_PUD_VAL_BITS
 
- HASH_PUT_BITS
 
- HASH_P_ID0
 
- HASH_P_ID1
 
- HASH_P_ID2
 
- HASH_P_ID3
 
- HASH_QUEUE_LENGTH
 
- HASH_READ_SIZE
 
- HASH_REG_SIZEOF
 
- HASH_RESET_BIT_INDEX_VAL
 
- HASH_RESET_BUFFER_VAL
 
- HASH_RESET_CR_VALUE
 
- HASH_RESET_CSDATAIN_REG_VALUE
 
- HASH_RESET_CSFULL_REG_VALUE
 
- HASH_RESET_CSRX_REG_VALUE
 
- HASH_RESET_INDEX_VAL
 
- HASH_RESET_LEN_HIGH_VAL
 
- HASH_RESET_LEN_LOW_VAL
 
- HASH_RESET_STR_VALUE
 
- HASH_RIGHT
 
- HASH_SET_BITS
 
- HASH_SET_DATA_FORMAT
 
- HASH_SET_DCAL
 
- HASH_SET_DIN
 
- HASH_SET_NBLW
 
- HASH_SHA1_MAX_REG
 
- HASH_SHA256_MAX_REG
 
- HASH_SHIFT
 
- HASH_SIZE
 
- HASH_SMALL
 
- HASH_SPACE_LEFT
 
- HASH_SR
 
- HASH_SR_BUSY
 
- HASH_SR_DATA_INPUT_READY
 
- HASH_SR_DMA_ACTIVE
 
- HASH_SR_OUTPUT_READY
 
- HASH_STR
 
- HASH_STR_DCAL
 
- HASH_STR_DCAL_MASK
 
- HASH_STR_DCAL_POS
 
- HASH_STR_DEFAULT
 
- HASH_STR_NBLW_MASK
 
- HASH_STR_NBLW_POS
 
- HASH_TABLE
 
- HASH_TABLE_BITS
 
- HASH_TABLE_SIZE
 
- HASH_TBL_ADDR
 
- HASH_TBL_ADDR_ADDR
 
- HASH_TBL_ADDR_AUTOINC
 
- HASH_TBL_DATA
 
- HASH_TBL_DATA_DATA
 
- HASH_TBL_DATA_LOG
 
- HASH_TBL_DATA_LOG_ADDR
 
- HASH_TBL_DATA_LOG_ERR
 
- HASH_TBL_DATA_LOG_SYNDROME
 
- HASH_TCP_IPV4_CTRL
 
- HASH_TCP_IPV6_CTRL
 
- HASH_TCP_IPV6_EX_CTRL
 
- HASH_TRANSHDR_SIZE
 
- HASH_TYPE
 
- HASH_TYPE_AES128
 
- HASH_TYPE_AES192
 
- HASH_TYPE_AES256
 
- HASH_TYPE_FIN
 
- HASH_TYPE_FULL
 
- HASH_TYPE_INIT
 
- HASH_TYPE_NONE
 
- HASH_TYPE_SHIFT
 
- HASH_TYPE_UPDT
 
- HASH_UNIT
 
- HASH_VER
 
- HASH_WR_MIN_LEN
 
- HASH_ZERO
 
- HASH_to_DOUT
 
- HASWELL
 
- HASWELL_DDRCRCLKCONTROLS
 
- HASWELL_HASYSDEFEATURE2
 
- HASWELL_TOHM_0
 
- HASWELL_TOHM_1
 
- HASWELL_TOLM
 
- HAS_128_BYTE_Y_TILING
 
- HAS_2D_SCROLL
 
- HAS_64BIT_RELOC
 
- HAS_8023X
 
- HAS_8BIT_TABLES
 
- HAS_ACCELERATION
 
- HAS_ACPI
 
- HAS_ALARM
 
- HAS_ANASWVDD
 
- HAS_ATA
 
- HAS_BOOL
 
- HAS_BROKEN_CS_TLB
 
- HAS_BROKEN_FIRMWARE
 
- HAS_BSR
 
- HAS_CAP
 
- HAS_CAP_TSO
 
- HAS_CB_FNS
 
- HAS_CHANGED
 
- HAS_CHIP_XCVR
 
- HAS_CONFIG_ID
 
- HAS_CSR
 
- HAS_CUR_FBC
 
- HAS_DBDMA
 
- HAS_DDI
 
- HAS_DISPLAY
 
- HAS_DISP_CFG
 
- HAS_DMA
 
- HAS_DP_MST
 
- HAS_EDRAM
 
- HAS_ENGINE
 
- HAS_EXECLISTS
 
- HAS_EXTENDED_IDS
 
- HAS_EXTRA_REQ
 
- HAS_FAN
 
- HAS_FBC
 
- HAS_FONTCACHE
 
- HAS_FPGA_DBG_UNCLAIMED
 
- HAS_FSYNCED_INODE
 
- HAS_FULL_PPGTT
 
- HAS_FWTABLE
 
- HAS_FW_BLC
 
- HAS_GLOBAL_MOCS_REGISTERS
 
- HAS_GMBUS_BURST_READ
 
- HAS_GMBUS_IRQ
 
- HAS_GMCH
 
- HAS_GT_UC
 
- HAS_GUEST_CODE
 
- HAS_HITMS
 
- HAS_HOME_PNA
 
- HAS_HWCKSM
 
- HAS_IBM_MISC
 
- HAS_IF
 
- HAS_IN7
 
- HAS_INTEGRATED_BUTTON
 
- HAS_INTR_MITIGATION
 
- HAS_IOMD
 
- HAS_IPC
 
- HAS_IPS
 
- HAS_L3_DPF
 
- HAS_LAST_FSYNC
 
- HAS_LINK
 
- HAS_LLC
 
- HAS_LNK_CHNG
 
- HAS_LOCK
 
- HAS_LOGICAL_RING_CONTEXTS
 
- HAS_LOGICAL_RING_ELSQ
 
- HAS_LOGICAL_RING_PREEMPTION
 
- HAS_LPE_AUDIO
 
- HAS_LSPCON
 
- HAS_MEDIA_TABLE
 
- HAS_MII
 
- HAS_MII_XCVR
 
- HAS_MISC_REG
 
- HAS_MMC
 
- HAS_MULTI_FING
 
- HAS_NAND
 
- HAS_NONSTANDARD_PDT_MASK
 
- HAS_NOR
 
- HAS_NO_BUTTON
 
- HAS_NVRAM
 
- HAS_NWAY
 
- HAS_OVERLAY
 
- HAS_PAGE_SIZES
 
- HAS_PALM_DETECT
 
- HAS_PCH_CNP
 
- HAS_PCH_CPT
 
- HAS_PCH_IBX
 
- HAS_PCH_ICP
 
- HAS_PCH_LPT
 
- HAS_PCH_LPT_H
 
- HAS_PCH_LPT_LP
 
- HAS_PCH_MCC
 
- HAS_PCH_NOP
 
- HAS_PCH_SPLIT
 
- HAS_PCH_SPT
 
- HAS_PCH_TGP
 
- HAS_PCI_MWI
 
- HAS_PGTBL_EN
 
- HAS_PHYS_PORT_ID
 
- HAS_PHY_IRQ
 
- HAS_PHY_RXTSTAMP
 
- HAS_PHY_TXTSTAMP
 
- HAS_PNICNWAY
 
- HAS_POOLED_EU
 
- HAS_PORTNUM
 
- HAS_POWER
 
- HAS_PPC_PMC_CLASSIC
 
- HAS_PPC_PMC_G4
 
- HAS_PPC_PMC_IBM
 
- HAS_PPC_PMC_PA6T
 
- HAS_PPGTT
 
- HAS_PSR
 
- HAS_PWM
 
- HAS_PWM_MIN
 
- HAS_PWR_CTRL
 
- HAS_RC6
 
- HAS_RC6p
 
- HAS_RC6pp
 
- HAS_RPS
 
- HAS_RUNTIME_PM
 
- HAS_SCROLLER
 
- HAS_SECONDARY_PWM
 
- HAS_SECURE_BATCHES
 
- HAS_SESSION_ENV_PREFIX
 
- HAS_SNOOP
 
- HAS_STATE_ID
 
- HAS_SWAPPED_SEEPROM
 
- HAS_TEMP_OFFSET
 
- HAS_TRANSCODER_EDP
 
- HAS_UNMAPPED_ID
 
- HAS_VBOOSTER
 
- HAS_VID
 
- HAS_VIDC20
 
- HAS_VOLA
 
- HAS_VOLB
 
- HAS_VOLC
 
- HAS_VOLD
 
- HAS_WT
 
- HAS_ZONE3
 
- HAS_ZONE_HYST
 
- HAUPPAUGE_CX_HYBRID_TV
 
- HAVE_ARCH_ALLOC_PAGE
 
- HAVE_ARCH_BUG
 
- HAVE_ARCH_BUG_ON
 
- HAVE_ARCH_CSUM_ADD
 
- HAVE_ARCH_FB_UNMAPPED_AREA
 
- HAVE_ARCH_FREE_PAGE
 
- HAVE_ARCH_HASH_64
 
- HAVE_ARCH_HUGETLB_UNMAPPED_AREA
 
- HAVE_ARCH_KALLSYMS_SYMBOL_VALUE
 
- HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
 
- HAVE_ARCH_PCI_GET_UNMAPPED_AREA
 
- HAVE_ARCH_PICK_MMAP_LAYOUT
 
- HAVE_ARCH_PIO_SIZE
 
- HAVE_ARCH_STRUCT_FLOCK
 
- HAVE_ARCH_UNMAPPED_AREA
 
- HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 
- HAVE_ARCH_WARN_ON
 
- HAVE_ARCH_X86_64_SUPPORT
 
- HAVE_ARCH__HASH_32
 
- HAVE_ATTR_TEST
 
- HAVE_COMPAT_IOCTL
 
- HAVE_COOKED
 
- HAVE_CSUM_COPY_USER
 
- HAVE_DEREFERENCE_FUNCTION_DESCRIPTOR
 
- HAVE_DIE_NMI
 
- HAVE_DISABLE_HLT
 
- HAVE_DMA_RXALIGN
 
- HAVE_DP83640_REGISTERS
 
- HAVE_EEPROM
 
- HAVE_FUNCTION_GRAPH_FP_TEST
 
- HAVE_FUNCTION_GRAPH_RET_ADDR_PTR
 
- HAVE_GETAUXVAL
 
- HAVE_GETREGS
 
- HAVE_HARDWARE
 
- HAVE_HW_TIME_STAMP
 
- HAVE_IP
 
- HAVE_JUMP_LABEL_BATCH
 
- HAVE_LIBATA_MSG
 
- HAVE_LONG_LONG
 
- HAVE_OLDMEM_PFN_IS_RAM
 
- HAVE_OP
 
- HAVE_PAGE_AGP
 
- HAVE_PCI_LEGACY
 
- HAVE_PCI_MMAP
 
- HAVE_PCI_REQ_REGIONS
 
- HAVE_PCI_SET_MWI
 
- HAVE_RBTX4939_IOSWAB
 
- HAVE_REALLY_SLOW_DMA_CONTROLLER
 
- HAVE_REMOTE_RTC
 
- HAVE_RETRIED
 
- HAVE_RST_BAR
 
- HAVE_RT_PUSH_IPI
 
- HAVE_SOFTFP
 
- HAVE_UNLOCKED_IOCTL
 
- HAWAII_GB_ADDR_CONFIG_GOLDEN
 
- HAWAII_IO_MC_REGS_SIZE
 
- HAWAII_MC2_UCODE_SIZE
 
- HAWAII_MC_UCODE_SIZE
 
- HAWAII_MEMORY_CLIENT_ID_MASK
 
- HAWAII_RB_BITMAP_WIDTH_PER_SH
 
- HAWAII_SMC_UCODE_SIZE
 
- HAWAII_SMC_UCODE_START
 
- HAWKBOARD_PHY_ID
 
- HAWK_MPIC_SIZE
 
- HA_CHUNK
 
- HA_DATA_PULSE
 
- HA_ERATT
 
- HA_ER_POS
 
- HA_FNLOCK_BIT
 
- HA_LATT
 
- HA_LE_POS
 
- HA_MBATT
 
- HA_MB_POS
 
- HA_R0ATT
 
- HA_R0CE_RSP
 
- HA_R0RE_REQ
 
- HA_R0_CLR_MSK
 
- HA_R0_POS
 
- HA_R1ATT
 
- HA_R1CE_RSP
 
- HA_R1RE_REQ
 
- HA_R1_CLR_MSK
 
- HA_R1_POS
 
- HA_R2ATT
 
- HA_R2CE_RSP
 
- HA_R2RE_REQ
 
- HA_R2_CLR_MSK
 
- HA_R2_POS
 
- HA_R3ATT
 
- HA_R3CE_RSP
 
- HA_R3RE_REQ
 
- HA_R3_CLR_MSK
 
- HA_R3_POS
 
- HA_REG_OFFSET
 
- HA_RXATT
 
- HA_RXCE_RSP
 
- HA_RXMASK
 
- HA_RXRE_REQ
 
- HB
 
- HBAF_TUNNEL
 
- HBA_AER_ENABLED
 
- HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
 
- HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN
 
- HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT
 
- HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR
 
- HBA_CMD_BYTE1_CRYPTO_ENABLE
 
- HBA_CMD_BYTE1_DATA_DIR_IN
 
- HBA_CMD_BYTE1_DATA_DIR_OUT
 
- HBA_CMD_BYTE1_DATA_TYPE_DDR
 
- HBA_DEFER_FLOGI
 
- HBA_DEVLOSS_TMO
 
- HBA_ERATT_HANDLED
 
- HBA_EVENT_LINK_DOWN
 
- HBA_EVENT_LINK_UP
 
- HBA_EVENT_RSCN
 
- HBA_FCOE_MODE
 
- HBA_FIP_SUPPORT
 
- HBA_FLAGS_BLINKLED_B
 
- HBA_FLAGS_DBG_ERROR_B
 
- HBA_FLAGS_DBG_FLAGS_MASK
 
- HBA_FLAGS_DBG_FUNCTION_ENTRY_B
 
- HBA_FLAGS_DBG_FUNCTION_EXIT_B
 
- HBA_FLAGS_DBG_FW_PRINT_B
 
- HBA_FLAGS_DBG_INIT_B
 
- HBA_FLAGS_DBG_KERNEL_PRINT_B
 
- HBA_FLAGS_DBG_OS_COMMANDS_B
 
- HBA_FLAGS_DBG_SCAN_B
 
- HBA_FLAGS_INSTALLED_B
 
- HBA_FLAGS_INTERNAL_USE
 
- HBA_FLAGS_IN_RESET
 
- HBA_FLAGS_PSCSI_MODE
 
- HBA_FLOGI_ISSUED
 
- HBA_FORCED_LINK_SPEED
 
- HBA_FW_DUMP_OP
 
- HBA_HOSTRESET_FAILED
 
- HBA_INQUIRY_BYTE_COUNT
 
- HBA_IOQ_FLUSH
 
- HBA_IU_TYPE_COALESCED_RESP
 
- HBA_IU_TYPE_INT_COALESCING_CFG_REQ
 
- HBA_IU_TYPE_RESP
 
- HBA_IU_TYPE_SATA_REQ
 
- HBA_IU_TYPE_SCSI_CMD_REQ
 
- HBA_IU_TYPE_SCSI_TM_REQ
 
- HBA_MAX_SG_EMBEDDED
 
- HBA_MAX_SG_SEPARATE
 
- HBA_MENLO_SUPPORT
 
- HBA_NAME_SIZE
 
- HBA_NORMAL_TEMP
 
- HBA_NVMET_CQ_NOTIFY
 
- HBA_NVMET_WQFULL
 
- HBA_ONLINE_TOV
 
- HBA_OVER_TEMP
 
- HBA_PORTSPEED_100GE
 
- HBA_PORTSPEED_10GE
 
- HBA_PORTSPEED_10GFC
 
- HBA_PORTSPEED_128GFC
 
- HBA_PORTSPEED_16GFC
 
- HBA_PORTSPEED_1GFC
 
- HBA_PORTSPEED_20GFC
 
- HBA_PORTSPEED_256GFC
 
- HBA_PORTSPEED_25GE
 
- HBA_PORTSPEED_2GFC
 
- HBA_PORTSPEED_32GFC
 
- HBA_PORTSPEED_400GE
 
- HBA_PORTSPEED_40GE
 
- HBA_PORTSPEED_40GFC
 
- HBA_PORTSPEED_4GFC
 
- HBA_PORTSPEED_50GE
 
- HBA_PORTSPEED_64GFC
 
- HBA_PORTSPEED_8GFC
 
- HBA_PORTSPEED_UNKNOWN
 
- HBA_PORT_BASE
 
- HBA_PORT_SPACE_BITS
 
- HBA_PORT_SPACE_SIZE
 
- HBA_POST_RECEIVE_BUFFER
 
- HBA_RECOVERABLE_UE
 
- HBA_REQUEST_TAG_ERROR_FLAG
 
- HBA_RESP_DATAPRES_NO_DATA
 
- HBA_RESP_DATAPRES_RESPONSE_DATA
 
- HBA_RESP_DATAPRES_SENSE_DATA
 
- HBA_RESP_STAT_HBAMODE_DISABLED
 
- HBA_RESP_STAT_INVALID_DEVICE
 
- HBA_RESP_STAT_IO_ABORTED
 
- HBA_RESP_STAT_IO_ERROR
 
- HBA_RESP_STAT_NO_PATH_TO_DEVICE
 
- HBA_RESP_STAT_OVERRUN
 
- HBA_RESP_STAT_UNDERRUN
 
- HBA_RESP_SVCRES_FAILURE
 
- HBA_RESP_SVCRES_TASK_COMPLETE
 
- HBA_RESP_SVCRES_TMF_COMPLETE
 
- HBA_RESP_SVCRES_TMF_LUN_INVALID
 
- HBA_RESP_SVCRES_TMF_REJECTED
 
- HBA_RESP_SVCRES_TMF_SUCCEEDED
 
- HBA_RRQ_ACTIVE
 
- HBA_RST
 
- HBA_SENSE_DATA_LEN_MAX
 
- HBA_SGL_FLAGS_EXT
 
- HBA_SIGNATURE
 
- HBA_SIGNATURE_471
 
- HBA_SIGNATURE_64BIT
 
- HBA_SIGNATURE_64_BIT
 
- HBA_SP_QUEUE_EVT
 
- HBA_TMF_ABORT_TASK
 
- HBA_TMF_LUN_RESET
 
- HBB
 
- HBE
 
- HBF_LL_READ
 
- HBF_READ_DATA
 
- HBIRD_ESTAR_MODE_ADDR
 
- HBIRD_MEM_CNTL0_ADDR
 
- HBIRD_STICKCMP_ADDR
 
- HBIRD_STICK_ADDR
 
- HBLANK
 
- HBLANKEND_MASK
 
- HBLANKEND_SHIFT
 
- HBLANKH_REG
 
- HBLANKL_REG
 
- HBLANKSTART_MASK
 
- HBLANKSTART_SHIFT
 
- HBLANK_A
 
- HBLANK_B
 
- HBLANK_C
 
- HBLKRM_L_MASK
 
- HBLKRM_PENC_MASK
 
- HBLKRM_SUPPORTED_BLOCK_SIZE
 
- HBLKR_AVPN
 
- HBLKR_CTRL_ERRBUSY
 
- HBLKR_CTRL_ERRNOTFOUND
 
- HBLKR_CTRL_MASK
 
- HBLKR_CTRL_SUCCESS
 
- HBLK_PACKET_OVERHEAD
 
- HBM_DIE_TEMPERATURE_THROTTLING_BIT
 
- HBM_DIE_TEMPERATURE_THROTTLING_MASK
 
- HBM_INT_STATUS
 
- HBM_MAJOR_VERSION
 
- HBM_MAJOR_VERSION_DC
 
- HBM_MAJOR_VERSION_DOT
 
- HBM_MAJOR_VERSION_DR
 
- HBM_MAJOR_VERSION_EV
 
- HBM_MAJOR_VERSION_FA
 
- HBM_MAJOR_VERSION_IE
 
- HBM_MAJOR_VERSION_OS
 
- HBM_MAJOR_VERSION_PGI
 
- HBM_MEMORY_CHANNEL_WIDTH
 
- HBM_MINOR_VERSION
 
- HBM_MINOR_VERSION_DC
 
- HBM_MINOR_VERSION_DOT
 
- HBM_MINOR_VERSION_DR
 
- HBM_MINOR_VERSION_EV
 
- HBM_MINOR_VERSION_FA
 
- HBM_MINOR_VERSION_IE
 
- HBM_MINOR_VERSION_OS
 
- HBM_MINOR_VERSION_PGI
 
- HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT
 
- HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK
 
- HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT
 
- HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK
 
- HBP
 
- HBPR
 
- HBP_LEN
 
- HBP_MASK
 
- HBP_NUM
 
- HBP_OFST
 
- HBP_PACKET_OVERHEAD
 
- HBRN8_POLL_TOUT_MS
 
- HBR_ANDCOND
 
- HBR_AVPN
 
- HBR_CAPABLE
 
- HBR_CHANNEL_COUNT
 
- HBR_END
 
- HBR_REQUEST
 
- HBR_RESPONSE
 
- HBSC_BRIGHT
 
- HBSC_CONTRAST
 
- HBSC_CTRL0
 
- HBSC_CTRL_EN
 
- HBSC_HUE
 
- HBSC_SATURATION
 
- HBSC_THRESHOLD_COL1
 
- HBSC_THRESHOLD_COL2
 
- HBSC_THRESHOLD_COL3
 
- HBSC_VL0_OFFSET
 
- HBSC_VL_OFFSET
 
- HBUFFERLEN
 
- HBUFFER_EVENTS_PENDING
 
- HBUFFER_TIME_HIGH
 
- HBUFFER_TIME_LOW
 
- HBURST_INCR
 
- HBURST_INCR4
 
- HBURST_INCR8
 
- HBURST_SINGLE
 
- HBUS
 
- HBUSREQ_MODE
 
- HBUS_BASE
 
- HBUS_TARG_MBX_C
 
- HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED
 
- HBUS_TARG_MEM_RADDR
 
- HBUS_TARG_MEM_RDAT
 
- HBUS_TARG_MEM_WADDR
 
- HBUS_TARG_MEM_WDAT
 
- HBUS_TARG_PRPH_RADDR
 
- HBUS_TARG_PRPH_RDAT
 
- HBUS_TARG_PRPH_WADDR
 
- HBUS_TARG_PRPH_WDAT
 
- HBUS_TARG_TEST_REG
 
- HBUS_TARG_WRPTR
 
- HB_A9_BCLK_DIV_MASK
 
- HB_A9_BCLK_DIV_SHIFT
 
- HB_A9_PCLK_DIV
 
- HB_CPUFREQ_CHANGE_NOTE
 
- HB_CPUFREQ_IPC_LEN
 
- HB_CPUFREQ_VOLT_RETRIES
 
- HB_DDR_ECC_C_ERR_ADDR
 
- HB_DDR_ECC_C_ERR_DATAH
 
- HB_DDR_ECC_C_ERR_DATAL
 
- HB_DDR_ECC_C_ERR_STAT
 
- HB_DDR_ECC_ERR_BASE
 
- HB_DDR_ECC_INT_ACK
 
- HB_DDR_ECC_INT_BASE
 
- HB_DDR_ECC_INT_STATUS
 
- HB_DDR_ECC_INT_STAT_CE
 
- HB_DDR_ECC_INT_STAT_DOUBLE_CE
 
- HB_DDR_ECC_INT_STAT_DOUBLE_UE
 
- HB_DDR_ECC_INT_STAT_UE
 
- HB_DDR_ECC_OPT
 
- HB_DDR_ECC_OPT_FWC
 
- HB_DDR_ECC_OPT_MODE_MASK
 
- HB_DDR_ECC_OPT_XOR_SHIFT
 
- HB_DDR_ECC_U_ERR_ADDR
 
- HB_DDR_ECC_U_ERR_DATAH
 
- HB_DDR_ECC_U_ERR_DATAL
 
- HB_DDR_ECC_U_ERR_STAT
 
- HB_MAJOR
 
- HB_MAJOR_1
 
- HB_MINOR
 
- HB_PLL_BYPASS
 
- HB_PLL_DIVF_MASK
 
- HB_PLL_DIVF_SHIFT
 
- HB_PLL_DIVQ_MASK
 
- HB_PLL_DIVQ_SHIFT
 
- HB_PLL_DIVR_MASK
 
- HB_PLL_DIVR_SHIFT
 
- HB_PLL_EXT_BYPASS
 
- HB_PLL_EXT_ENA
 
- HB_PLL_LOCK
 
- HB_PLL_LOCK_500
 
- HB_PLL_MAX_FREQ
 
- HB_PLL_MIN_FREQ
 
- HB_PLL_RANGE_MASK
 
- HB_PLL_RANGE_SHIFT
 
- HB_PLL_RESET
 
- HB_PLL_VCO_MIN_FREQ
 
- HB_PWR_HARD_RESET
 
- HB_PWR_SHUTDOWN
 
- HB_PWR_SOFT_RESET
 
- HB_PWR_SUSPEND
 
- HB_SREG_A9_BOOT_DATA
 
- HB_SREG_A9_BOOT_STAT
 
- HB_SREG_A9_PWR_REQ
 
- HB_VERSION
 
- HB_VERSION_1
 
- HB_VER_COUNT
 
- HBorder
 
- HC0_IRQ_PEND
 
- HCALL_BRANCH
 
- HCALL_INST_POSTCALL
 
- HCALL_INST_POSTCALL_NORETS
 
- HCALL_INST_PRECALL
 
- HCALL_ROOT_DIR
 
- HCALL_STAT_ARRAY_SIZE
 
- HCAN20
 
- HCAN21
 
- HCATLBUFLEN
 
- HCATLPORT
 
- HCA_CAP_OPMOD_GET_CUR
 
- HCA_CAP_OPMOD_GET_MAX
 
- HCA_E_BIT
 
- HCB0
 
- HCB0_ENBL
 
- HCB1
 
- HCB1_ENBL
 
- HCBADR
 
- HCBADR_COLKEY
 
- HCBADR_GLALPHA
 
- HCBUFSTAT
 
- HCBUFSTAT_ATL_ACTIVE
 
- HCBUFSTAT_ATL_DONE
 
- HCBUFSTAT_ATL_FULL
 
- HCBUFSTAT_INTL_ACTIVE
 
- HCBUFSTAT_ISTL0_ACTIVE
 
- HCBUFSTAT_ISTL0_DONE
 
- HCBUFSTAT_ISTL0_FULL
 
- HCBUFSTAT_ISTL1_ACTIVE
 
- HCBUFSTAT_ISTL1_DONE
 
- HCBUFSTAT_ISTL1_FULL
 
- HCBUFSTAT_ITL0_DONE
 
- HCBUFSTAT_ITL0_FULL
 
- HCBUFSTAT_ITL1_DONE
 
- HCBUFSTAT_ITL1_FULL
 
- HCBUFSTAT_PAIRED_PTDPP
 
- HCBUFSTAT_RESET_HWPP
 
- HCB_ACK_BIT
 
- HCB_BA
 
- HCB_CD_BIT
 
- HCB_DS_BIT
 
- HCB_RW_BIT
 
- HCB_WUP_BIT
 
- HCC2_CIC
 
- HCC2_CMC
 
- HCC2_CTC
 
- HCC2_ETC
 
- HCC2_FSC
 
- HCC2_LEC
 
- HCC2_U3C
 
- HCCAQDA
 
- HCCA_QID_01
 
- HCCA_QID_02
 
- HCCA_QID_03
 
- HCCA_QID_04
 
- HCCA_QID_05
 
- HCCA_QID_06
 
- HCCA_QID_07
 
- HCCA_QID_08
 
- HCCA_QUEUE
 
- HCCHAR
 
- HCCHAR_CHDIS
 
- HCCHAR_CHENA
 
- HCCHAR_DEVADDR_MASK
 
- HCCHAR_DEVADDR_SHIFT
 
- HCCHAR_EPDIR
 
- HCCHAR_EPNUM_MASK
 
- HCCHAR_EPNUM_SHIFT
 
- HCCHAR_EPTYPE_MASK
 
- HCCHAR_EPTYPE_SHIFT
 
- HCCHAR_LSPDDEV
 
- HCCHAR_MPS_MASK
 
- HCCHAR_MPS_SHIFT
 
- HCCHAR_MULTICNT_MASK
 
- HCCHAR_MULTICNT_SHIFT
 
- HCCHAR_ODDFRM
 
- HCCHIPID
 
- HCCHIPID_MAGIC
 
- HCCHIPID_MASK
 
- HCCKMSK
 
- HCCKMSK_COLKEY_M
 
- HCCMDSTAT
 
- HCCMDSTAT_HCR
 
- HCCMDSTAT_SOC
 
- HCCONTROL
 
- HCCONTROL_HCFS
 
- HCCONTROL_RWC
 
- HCCONTROL_RWE
 
- HCCONTROL_USB_OPER
 
- HCCONTROL_USB_RESET
 
- HCCONTROL_USB_RESUME
 
- HCCONTROL_USB_SUSPEND
 
- HCCPARAMS_LEN
 
- HCCRX_CLR_HOST_INT
 
- HCCRX_CLR_RISC_INT
 
- HCCRX_CLR_RISC_RESET
 
- HCCRX_HOST_INT
 
- HCCRX_NOOP
 
- HCCRX_REL_RISC_PAUSE
 
- HCCRX_RISC_RESET
 
- HCCRX_SET_HOST_INT
 
- HCCRX_SET_RISC_PAUSE
 
- HCCRX_SET_RISC_RESET
 
- HCCR_CLR_HOST_INT
 
- HCCR_CLR_RISC_INT
 
- HCCR_DISABLE_PARITY_PAUSE
 
- HCCR_ENABLE_PARITY
 
- HCCR_HOST_INT
 
- HCCR_PAUSE_RISC
 
- HCCR_RELEASE_RISC
 
- HCCR_RESET_RISC
 
- HCCR_RISC_PAUSE
 
- HCCR_SET_HOST_INT
 
- HCCTRL
 
- HCCTRL_B0ENAB
 
- HCCTRL_B1ENAB
 
- HCCTRL_BKPT
 
- HCCTRL_BLEND_GLOB
 
- HCCTRL_BLEND_INV
 
- HCCTRL_BLEND_M
 
- HCCTRL_BLEND_NONE
 
- HCCTRL_BLEND_PIX
 
- HCCTRL_CBASE_ADR
 
- HCCTRL_CHIRQ
 
- HCCTRL_COLKEYSRC
 
- HCCTRL_COLKEY_EN
 
- HCCTRL_CPIXFMT
 
- HCCTRL_CPIXFMT_ARGB1555
 
- HCCTRL_CPIXFMT_ARGB4444
 
- HCCTRL_CPIXFMT_RGB332
 
- HCCTRL_CRIRQ
 
- HCCTRL_CUR_EN
 
- HCCTRL_EBENAB
 
- HCCTRL_HIRQ
 
- HCCTRL_NOP
 
- HCCTRL_PAUSE
 
- HCCTRL_REL
 
- HCCTRL_RESET
 
- HCCTRL_RPAUSED
 
- HCCTRL_RRIP
 
- HCCTRL_SHIRQ
 
- HCCTRL_STEP
 
- HCCTRL_TMODE
 
- HCC_32FRAME_PERIODIC_LIST
 
- HCC_64BIT_ADDR
 
- HCC_64BYTE_CONTEXT
 
- HCC_ACT_TERM1
 
- HCC_ACT_TERM2
 
- HCC_AUTOTERM
 
- HCC_AUTO_TERM
 
- HCC_BANDWIDTH_NEG
 
- HCC_CANPARK
 
- HCC_CFC
 
- HCC_EN_PAR
 
- HCC_EN_PWR
 
- HCC_EXT_CAPS
 
- HCC_HW_PREFETCH
 
- HCC_ISOC_CACHE
 
- HCC_ISOC_THRES
 
- HCC_LIGHT_RESET
 
- HCC_LOW8TERM
 
- HCC_LPM
 
- HCC_LTC
 
- HCC_MAX_PSA
 
- HCC_NSS
 
- HCC_PARITY
 
- HCC_PER_PORT_CHANGE_EVENT
 
- HCC_PGM_FRAMELISTLEN
 
- HCC_PPC
 
- HCC_SCSI_RESET
 
- HCC_SPC
 
- HCC_UP8TERM
 
- HCC_WIDE_CARD
 
- HCDIRADDR_ADDR
 
- HCDIRADDR_ADDR_MASK
 
- HCDIRADDR_COUNT
 
- HCDIRADDR_COUNT_MASK
 
- HCDMA
 
- HCDMAB
 
- HCDMACFG
 
- HCDMACFG_BUF_ATL
 
- HCDMACFG_BUF_DIRECT
 
- HCDMACFG_BUF_INTL
 
- HCDMACFG_BUF_ISTL0
 
- HCDMACFG_BUF_ISTL1
 
- HCDMACFG_BUF_TYPE
 
- HCDMACFG_BUF_TYPE_MASK
 
- HCDMACFG_BURST_LEN
 
- HCDMACFG_BURST_LEN_1
 
- HCDMACFG_BURST_LEN_4
 
- HCDMACFG_BURST_LEN_8
 
- HCDMACFG_BURST_LEN_MASK
 
- HCDMACFG_CTR_ENABLE
 
- HCDMACFG_CTR_SEL
 
- HCDMACFG_DMA_ENABLE
 
- HCDMACFG_DMA_RW_SELECT
 
- HCDMACFG_ITLATL_SEL
 
- HCDP_TABLE_GUID
 
- HCD_BH
 
- HCD_BUFFER_POOLS
 
- HCD_DEAD
 
- HCD_DMA
 
- HCD_FLAG_DEAD
 
- HCD_FLAG_HW_ACCESSIBLE
 
- HCD_FLAG_INTF_AUTHORIZED
 
- HCD_FLAG_POLL_PENDING
 
- HCD_FLAG_POLL_RH
 
- HCD_FLAG_RH_RUNNING
 
- HCD_FLAG_WAKEUP_PENDING
 
- HCD_HW_ACCESSIBLE
 
- HCD_INTF_AUTHORIZED
 
- HCD_MASK
 
- HCD_MEMORY
 
- HCD_POLL_PENDING
 
- HCD_POLL_RH
 
- HCD_RH_RUNNING
 
- HCD_SHARED
 
- HCD_USB11
 
- HCD_USB2
 
- HCD_USB25
 
- HCD_USB3
 
- HCD_USB31
 
- HCD_USB32
 
- HCD_WAKEUP_PENDING
 
- HCFG
 
- HCFG2
 
- HCFG_8_CHANNEL_CAPTURE
 
- HCFG_8_CHANNEL_PLAY
 
- HCFG_AC3ENABLE_CDSPDIF
 
- HCFG_AC3ENABLE_GPSPDIF
 
- HCFG_AC3ENABLE_MASK
 
- HCFG_AC3ENABLE_ZVIDEO
 
- HCFG_AC97
 
- HCFG_AUDIOENABLE
 
- HCFG_AUTOMUTE
 
- HCFG_AUTOMUTE_ASYNC
 
- HCFG_AUTOMUTE_SPDIF
 
- HCFG_BAUD_RATE
 
- HCFG_CAPTURE_I2S_BYPASS
 
- HCFG_CAPTURE_S32_LE
 
- HCFG_CAPTURE_SPDIF_BYPASS
 
- HCFG_CODECFORMAT_AC97
 
- HCFG_CODECFORMAT_AC97_1
 
- HCFG_CODECFORMAT_AC97_2
 
- HCFG_CODECFORMAT_I2S
 
- HCFG_CODECFORMAT_MASK
 
- HCFG_DESCDMA
 
- HCFG_EMU32_SLAVE
 
- HCFG_ENA32KHZ
 
- HCFG_EXPANDED_MEM
 
- HCFG_FORCE_LOCK
 
- HCFG_FRLISTEN_16
 
- HCFG_FRLISTEN_32
 
- HCFG_FRLISTEN_64
 
- HCFG_FRLISTEN_8
 
- HCFG_FRLISTEN_MASK
 
- HCFG_FRLISTEN_SHIFT
 
- HCFG_FSLSPCLKSEL_30_60_MHZ
 
- HCFG_FSLSPCLKSEL_48_MHZ
 
- HCFG_FSLSPCLKSEL_6_MHZ
 
- HCFG_FSLSPCLKSEL_MASK
 
- HCFG_FSLSPCLKSEL_SHIFT
 
- HCFG_FSLSSUPP
 
- HCFG_GPINPUT0
 
- HCFG_GPINPUT1
 
- HCFG_GPOUT0
 
- HCFG_GPOUT1
 
- HCFG_GPOUT2
 
- HCFG_GPOUTPUT_MASK
 
- HCFG_I2S_ASRC_ENABLE
 
- HCFG_I2S_OUTPUT
 
- HCFG_IOCAPTUREADDR
 
- HCFG_JOYENABLE
 
- HCFG_LEGACYFUNC_AD
 
- HCFG_LEGACYFUNC_MASK
 
- HCFG_LEGACYFUNC_MDMA
 
- HCFG_LEGACYFUNC_MPIC
 
- HCFG_LEGACYFUNC_MPU
 
- HCFG_LEGACYFUNC_SB
 
- HCFG_LEGACYFUNC_SDMA
 
- HCFG_LEGACYFUNC_SPCI
 
- HCFG_LEGACYINT
 
- HCFG_LEGACYWORD
 
- HCFG_LEGACYWRITE
 
- HCFG_LOCKSOUNDCACHE
 
- HCFG_LOCKTANKCACHE
 
- HCFG_LOCKTANKCACHE_MASK
 
- HCFG_LOCK_CAPTURE_CACHE
 
- HCFG_LOCK_PLAYBACK_CACHE
 
- HCFG_MODECHTIMEN
 
- HCFG_MONO
 
- HCFG_MUTEBUTTONENABLE
 
- HCFG_PERSCHEDENA
 
- HCFG_PHASETRACKENABLE
 
- HCFG_PHASE_TRACK_MASK
 
- HCFG_PLAYBACK_ATTENUATION
 
- HCFG_PLAYBACK_DITHER
 
- HCFG_PLAYBACK_I2S_BYPASS
 
- HCFG_PLAYBACK_S32_LE
 
- HCFG_PUSH_BUTTON_ENABLE
 
- HCFG_RESVALID_MASK
 
- HCFG_RESVALID_SHIFT
 
- HCFG_SLOW_RAMP
 
- HCFG_STAC
 
- HCFIFO
 
- HCFMINTVL
 
- HCFMNUM
 
- HCFMREM
 
- HCFPCI_C_I
 
- HCF_EXPECT_DISC
 
- HCF_EXPECT_DONE_DISC
 
- HCF_EXPECT_RESET
 
- HCF_EXPECT_SELECT
 
- HCF_INT_MASK
 
- HCF_LVDS
 
- HCF_PARITY
 
- HCF_SCSI_RESET
 
- HCHWCFG
 
- HCHWCFG_15KRSEL
 
- HCHWCFG_ANALOG_OC
 
- HCHWCFG_CLKNOTSTOP
 
- HCHWCFG_DACK_MODE
 
- HCHWCFG_DACK_POL
 
- HCHWCFG_DBWIDTH
 
- HCHWCFG_DBWIDTH_MASK
 
- HCHWCFG_DISABLE_SUSPEND
 
- HCHWCFG_DREQ_POL
 
- HCHWCFG_EOT_POL
 
- HCHWCFG_GLOBAL_PWRDOWN
 
- HCHWCFG_INT_ENABLE
 
- HCHWCFG_INT_POL
 
- HCHWCFG_INT_TRIGGER
 
- HCHWCFG_ONEDMA
 
- HCHWCFG_ONEINT
 
- HCHWCFG_PULLDOWN_DS1
 
- HCHWCFG_PULLDOWN_DS2
 
- HCIBLOCKADDR
 
- HCIDEVDOWN
 
- HCIDEVRESET
 
- HCIDEVRESTAT
 
- HCIDEVUP
 
- HCIGETAUTHINFO
 
- HCIGETCONNINFO
 
- HCIGETCONNLIST
 
- HCIGETDEVINFO
 
- HCIGETDEVLIST
 
- HCIINQUIRY
 
- HCILL_ASLEEP
 
- HCILL_ASLEEP_TO_AWAKE
 
- HCILL_AWAKE
 
- HCILL_AWAKE_TO_ASLEEP
 
- HCILL_GO_TO_SLEEP_ACK
 
- HCILL_GO_TO_SLEEP_IND
 
- HCILL_WAKE_UP_ACK
 
- HCILL_WAKE_UP_IND
 
- HCINT
 
- HCINTDIS
 
- HCINTENB
 
- HCINTMSK
 
- HCINTMSK_ACK
 
- HCINTMSK_AHBERR
 
- HCINTMSK_BBLERR
 
- HCINTMSK_BNA
 
- HCINTMSK_CHHLTD
 
- HCINTMSK_DATATGLERR
 
- HCINTMSK_FRMOVRUN
 
- HCINTMSK_FRM_LIST_ROLL
 
- HCINTMSK_NAK
 
- HCINTMSK_NYET
 
- HCINTMSK_RESERVED14_31
 
- HCINTMSK_STALL
 
- HCINTMSK_XACTERR
 
- HCINTMSK_XCS_XACT
 
- HCINTMSK_XFERCOMPL
 
- HCINTSTAT
 
- HCINT_FNO
 
- HCINT_MIE
 
- HCINT_OC
 
- HCINT_RD
 
- HCINT_RHSC
 
- HCINT_SF
 
- HCINT_SO
 
- HCINT_UE
 
- HCINT_WDH
 
- HCISETACLMTU
 
- HCISETAUTH
 
- HCISETENCRYPT
 
- HCISETLINKMODE
 
- HCISETLINKPOL
 
- HCISETPTYPE
 
- HCISETRAW
 
- HCISETSCAN
 
- HCISETSCOMTU
 
- HCITLBUFLEN
 
- HCITLPORT
 
- HCIUARTGETDEVICE
 
- HCIUARTGETFLAGS
 
- HCIUARTGETPROTO
 
- HCIUARTSETFLAGS
 
- HCIUARTSETPROTO
 
- HCIUNBLOCKADDR
 
- HCIV
 
- HCI_2DH1
 
- HCI_2DH3
 
- HCI_2DH5
 
- HCI_3DH1
 
- HCI_3DH3
 
- HCI_3DH5
 
- HCI_3WIRE_ACK_PKT
 
- HCI_3WIRE_LINK_PKT
 
- HCI_ACCELEROMETER
 
- HCI_ACCELEROMETER2
 
- HCI_ACCEL_DIRECTION_MASK
 
- HCI_ACCEL_MASK
 
- HCI_ACLDATA_PKT
 
- HCI_ACL_HDR_SIZE
 
- HCI_ACL_TX_TIMEOUT
 
- HCI_ADVERTISING
 
- HCI_ADVERTISING_CONNECTABLE
 
- HCI_ADV_PHY_1M
 
- HCI_ADV_PHY_2M
 
- HCI_ADV_PHY_CODED
 
- HCI_AMP
 
- HCI_AMP_LINK_KEY_SIZE
 
- HCI_AT_DEDICATED_BONDING
 
- HCI_AT_DEDICATED_BONDING_MITM
 
- HCI_AT_GENERAL_BONDING
 
- HCI_AT_GENERAL_BONDING_MITM
 
- HCI_AT_NO_BONDING
 
- HCI_AT_NO_BONDING_MITM
 
- HCI_AUTH
 
- HCI_AUTO_CONN_ALWAYS
 
- HCI_AUTO_CONN_DIRECT
 
- HCI_AUTO_CONN_DISABLED
 
- HCI_AUTO_CONN_EXPLICIT
 
- HCI_AUTO_CONN_LINK_LOSS
 
- HCI_AUTO_CONN_REPORT
 
- HCI_AUTO_OFF
 
- HCI_AUTO_OFF_TIMEOUT
 
- HCI_BONDABLE
 
- HCI_BREDR_ENABLED
 
- HCI_BT_OP_BT_DEV_DISABLE
 
- HCI_BT_OP_BT_DEV_ENABLE
 
- HCI_BT_OP_INQUIRY_FINISH
 
- HCI_BT_OP_INQUIRY_START
 
- HCI_BT_OP_MAX
 
- HCI_BT_OP_NONE
 
- HCI_BT_OP_PAGING_START
 
- HCI_BT_OP_PAGING_SUCCESS
 
- HCI_BT_OP_PAGING_UNSUCCESS
 
- HCI_BT_OP_PAIRING_FINISH
 
- HCI_BT_OP_PAIRING_START
 
- HCI_CB_TYPE_TRANSCEIVE
 
- HCI_CHANNEL_CONTROL
 
- HCI_CHANNEL_LOGGING
 
- HCI_CHANNEL_MONITOR
 
- HCI_CHANNEL_RAW
 
- HCI_CHANNEL_USER
 
- HCI_CHIP_VER_PKT
 
- HCI_CLEAR_ALL_PIPES
 
- HCI_CMDS_HEADROOM
 
- HCI_CMD_PENDING
 
- HCI_CMD_TIMEOUT
 
- HCI_CMSG_DIR
 
- HCI_CMSG_TSTAMP
 
- HCI_CM_ACTIVE
 
- HCI_CM_HOLD
 
- HCI_CM_PARK
 
- HCI_CM_SNIFF
 
- HCI_COMMAND_HDR_SIZE
 
- HCI_COMMAND_PKT
 
- HCI_COMPLETE_FRAME
 
- HCI_CONFIG
 
- HCI_CONNECTABLE
 
- HCI_CONN_AES_CCM
 
- HCI_CONN_AUTH
 
- HCI_CONN_AUTH_FAILURE
 
- HCI_CONN_AUTH_INITIATOR
 
- HCI_CONN_AUTH_PEND
 
- HCI_CONN_DROP
 
- HCI_CONN_ENCRYPT
 
- HCI_CONN_ENCRYPT_PEND
 
- HCI_CONN_FIPS
 
- HCI_CONN_FLUSH_KEY
 
- HCI_CONN_MGMT_CONNECTED
 
- HCI_CONN_MODE_CHANGE_PEND
 
- HCI_CONN_NEW_LINK_KEY
 
- HCI_CONN_PARAM_REMOVAL_PEND
 
- HCI_CONN_POWER_SAVE
 
- HCI_CONN_REAUTH_PEND
 
- HCI_CONN_RSWITCH_PEND
 
- HCI_CONN_SCANNING
 
- HCI_CONN_SCO_SETUP_PEND
 
- HCI_CONN_SC_ENABLED
 
- HCI_CONN_SECURE
 
- HCI_CONN_SETUP_ALLOW_ALL
 
- HCI_CONN_SETUP_ALLOW_BDADDR
 
- HCI_CONN_SETUP_ALLOW_CLASS
 
- HCI_CONN_SETUP_AUTO_OFF
 
- HCI_CONN_SETUP_AUTO_ON
 
- HCI_CONN_SSP_ENABLED
 
- HCI_CONN_STK_ENCRYPT
 
- HCI_COOLING_METHOD
 
- HCI_DATA_DIR
 
- HCI_DEFAULT_ADV_DURATION
 
- HCI_DEFAULT_RPA_TIMEOUT
 
- HCI_DEV_CLOSE
 
- HCI_DEV_DOWN
 
- HCI_DEV_NONE
 
- HCI_DEV_OPEN
 
- HCI_DEV_REG
 
- HCI_DEV_RESUME
 
- HCI_DEV_SETUP
 
- HCI_DEV_SUSPEND
 
- HCI_DEV_UNREG
 
- HCI_DEV_UP
 
- HCI_DH1
 
- HCI_DH3
 
- HCI_DH5
 
- HCI_DIAG_PKT
 
- HCI_DISCONN_TIMEOUT
 
- HCI_DISCOVERABLE
 
- HCI_DM1
 
- HCI_DM3
 
- HCI_DM5
 
- HCI_DM_DIRECT_LOAD
 
- HCI_DM_FIELD_GENERATOR
 
- HCI_DM_FWUPD_END
 
- HCI_DM_FWUPD_START
 
- HCI_DM_GET_DATA
 
- HCI_DM_GET_INFO
 
- HCI_DM_LOAD
 
- HCI_DM_PUT_DATA
 
- HCI_DM_RESET
 
- HCI_DM_UPDATE_AID
 
- HCI_DM_VDC_MEASUREMENT_VALUE
 
- HCI_DM_VDC_VALUE_COMPARISON
 
- HCI_DUT_MODE
 
- HCI_ECO_MODE
 
- HCI_ENCRYPT
 
- HCI_ERROR_ADVERTISING_TIMEOUT
 
- HCI_ERROR_AUTH_FAILURE
 
- HCI_ERROR_CONNECTION_TIMEOUT
 
- HCI_ERROR_INVALID_LL_PARAMS
 
- HCI_ERROR_LOCAL_HOST_TERM
 
- HCI_ERROR_MEMORY_EXCEEDED
 
- HCI_ERROR_PAIRING_NOT_ALLOWED
 
- HCI_ERROR_PIN_OR_KEY_MISSING
 
- HCI_ERROR_REJ_BAD_ADDR
 
- HCI_ERROR_REJ_LIMITED_RESOURCES
 
- HCI_ERROR_REMOTE_LOW_RESOURCES
 
- HCI_ERROR_REMOTE_POWER_OFF
 
- HCI_ERROR_REMOTE_USER_TERM
 
- HCI_ERROR_UNKNOWN_CONN_ID
 
- HCI_ERROR_UNSPECIFIED
 
- HCI_EVENT_HDR_SIZE
 
- HCI_EVENT_PKT
 
- HCI_EV_AUTH_COMPLETE
 
- HCI_EV_CHANGE_LINK_KEY_COMPLETE
 
- HCI_EV_CHANNEL_SELECTED
 
- HCI_EV_CLOCK_OFFSET
 
- HCI_EV_CMD_COMPLETE
 
- HCI_EV_CMD_STATUS
 
- HCI_EV_CONN_COMPLETE
 
- HCI_EV_CONN_REQUEST
 
- HCI_EV_DISCONN_COMPLETE
 
- HCI_EV_DISCONN_LOGICAL_LINK_COMPLETE
 
- HCI_EV_DISCONN_PHY_LINK_COMPLETE
 
- HCI_EV_ENCRYPT_CHANGE
 
- HCI_EV_EXTENDED_INQUIRY_RESULT
 
- HCI_EV_HARDWARE_ERROR
 
- HCI_EV_INQUIRY_COMPLETE
 
- HCI_EV_INQUIRY_RESULT
 
- HCI_EV_INQUIRY_RESULT_WITH_RSSI
 
- HCI_EV_IO_CAPA_REPLY
 
- HCI_EV_IO_CAPA_REQUEST
 
- HCI_EV_KEYPRESS_NOTIFY
 
- HCI_EV_KEY_REFRESH_COMPLETE
 
- HCI_EV_LE_ADVERTISING_REPORT
 
- HCI_EV_LE_CONN_COMPLETE
 
- HCI_EV_LE_CONN_UPDATE_COMPLETE
 
- HCI_EV_LE_DATA_LEN_CHANGE
 
- HCI_EV_LE_DIRECT_ADV_REPORT
 
- HCI_EV_LE_ENHANCED_CONN_COMPLETE
 
- HCI_EV_LE_EXT_ADV_REPORT
 
- HCI_EV_LE_EXT_ADV_SET_TERM
 
- HCI_EV_LE_LTK_REQ
 
- HCI_EV_LE_META
 
- HCI_EV_LE_REMOTE_CONN_PARAM_REQ
 
- HCI_EV_LE_REMOTE_FEAT_COMPLETE
 
- HCI_EV_LINK_KEY_NOTIFY
 
- HCI_EV_LINK_KEY_REQ
 
- HCI_EV_LOGICAL_LINK_COMPLETE
 
- HCI_EV_MODE_CHANGE
 
- HCI_EV_NUM_COMP_BLOCKS
 
- HCI_EV_NUM_COMP_PKTS
 
- HCI_EV_PHY_LINK_COMPLETE
 
- HCI_EV_PIN_CODE_REQ
 
- HCI_EV_PKT_TYPE_CHANGE
 
- HCI_EV_PSCAN_REP_MODE
 
- HCI_EV_QOS_SETUP_COMPLETE
 
- HCI_EV_REMOTE_EXT_FEATURES
 
- HCI_EV_REMOTE_FEATURES
 
- HCI_EV_REMOTE_HOST_FEATURES
 
- HCI_EV_REMOTE_NAME
 
- HCI_EV_REMOTE_OOB_DATA_REQUEST
 
- HCI_EV_REMOTE_VERSION
 
- HCI_EV_ROLE_CHANGE
 
- HCI_EV_SIMPLE_PAIR_COMPLETE
 
- HCI_EV_SI_DEVICE
 
- HCI_EV_SI_SECURITY
 
- HCI_EV_SLAVE_PAGE_RESP_TIMEOUT
 
- HCI_EV_SNIFF_SUBRATE
 
- HCI_EV_STACK_INTERNAL
 
- HCI_EV_SYNC_CONN_CHANGED
 
- HCI_EV_SYNC_CONN_COMPLETE
 
- HCI_EV_SYNC_TRAIN_COMPLETE
 
- HCI_EV_USER_CONFIRM_REQUEST
 
- HCI_EV_USER_PASSKEY_NOTIFY
 
- HCI_EV_USER_PASSKEY_REQUEST
 
- HCI_EV_VENDOR
 
- HCI_EXT_CONFIGURED
 
- HCI_FAN
 
- HCI_FAST_CONNECTABLE
 
- HCI_FILTER
 
- HCI_FLOW_CTL_MODE_BLOCK_BASED
 
- HCI_FLOW_CTL_MODE_PACKET_BASED
 
- HCI_FLT_CLEAR_ALL
 
- HCI_FLT_CONN_SETUP
 
- HCI_FLT_EVENT_BITS
 
- HCI_FLT_INQ_RESULT
 
- HCI_FLT_OCF_BITS
 
- HCI_FLT_OGF_BITS
 
- HCI_FLT_TYPE_BITS
 
- HCI_FORCE_BREDR_SMP
 
- HCI_FORCE_STATIC_ADDR
 
- HCI_FW_REQ_PKT
 
- HCI_GET
 
- HCI_GET_PARAM
 
- HCI_HEADER_LENGTH
 
- HCI_HEADER_SIZE
 
- HCI_HOTKEY_DISABLE
 
- HCI_HOTKEY_ENABLE
 
- HCI_HOTKEY_EVENT
 
- HCI_HOTKEY_SPECIAL_FUNCTIONS
 
- HCI_HS_ENABLED
 
- HCI_HV1
 
- HCI_HV2
 
- HCI_HV3
 
- HCI_I2C
 
- HCI_IBS_RX_ASLEEP
 
- HCI_IBS_RX_AWAKE
 
- HCI_IBS_RX_VOTE_CLOCK_OFF
 
- HCI_IBS_RX_VOTE_CLOCK_ON
 
- HCI_IBS_SLEEP_IND
 
- HCI_IBS_TX_ASLEEP
 
- HCI_IBS_TX_AWAKE
 
- HCI_IBS_TX_VOTE_CLOCK_OFF
 
- HCI_IBS_TX_VOTE_CLOCK_ON
 
- HCI_IBS_TX_WAKING
 
- HCI_IBS_VOTE_STATS_UPDATE
 
- HCI_IBS_WAKE_ACK
 
- HCI_IBS_WAKE_IND
 
- HCI_INIT
 
- HCI_INIT_TIMEOUT
 
- HCI_INQUIRY
 
- HCI_IO_DISPLAY_ONLY
 
- HCI_IO_DISPLAY_YESNO
 
- HCI_IO_DS_2MA
 
- HCI_IO_DS_4MA
 
- HCI_IO_DS_6MA
 
- HCI_IO_DS_8MA
 
- HCI_IO_KEYBOARD_ONLY
 
- HCI_IO_NO_INPUT_OUTPUT
 
- HCI_ISCAN
 
- HCI_KBD_ILLUMINATION
 
- HCI_KEEP_DEBUG_KEYS
 
- HCI_KEYPRESS_CLEARED
 
- HCI_KEYPRESS_COMPLETED
 
- HCI_KEYPRESS_ENTERED
 
- HCI_KEYPRESS_ERASED
 
- HCI_KEYPRESS_STARTED
 
- HCI_LCD_BRIGHTNESS
 
- HCI_LCD_BRIGHTNESS_BITS
 
- HCI_LCD_BRIGHTNESS_LEVELS
 
- HCI_LCD_BRIGHTNESS_SHIFT
 
- HCI_LE_ADV
 
- HCI_LE_AUTOCONN_TIMEOUT
 
- HCI_LE_CHAN_SEL_ALG2
 
- HCI_LE_CONN_PARAM_REQ_PROC
 
- HCI_LE_CONN_TIMEOUT
 
- HCI_LE_DATA_LEN_EXT
 
- HCI_LE_ENABLED
 
- HCI_LE_ENCRYPTION
 
- HCI_LE_EXT_ADV
 
- HCI_LE_EXT_SCAN_POLICY
 
- HCI_LE_PHY_2M
 
- HCI_LE_PHY_CODED
 
- HCI_LE_PING
 
- HCI_LE_SCAN
 
- HCI_LE_SCAN_INTERRUPTED
 
- HCI_LE_SET_PHY_1M
 
- HCI_LE_SET_PHY_2M
 
- HCI_LE_SET_PHY_CODED
 
- HCI_LE_SLAVE_FEATURES
 
- HCI_LE_USE_PEER_ADDR
 
- HCI_LE_USE_WHITELIST
 
- HCI_LIMITED_DISCOVERABLE
 
- HCI_LIMITED_PRIVACY
 
- HCI_LINK_KEY_SIZE
 
- HCI_LINK_SECURITY
 
- HCI_LK_AUTH_COMBINATION_P192
 
- HCI_LK_AUTH_COMBINATION_P256
 
- HCI_LK_CHANGED_COMBINATION
 
- HCI_LK_COMBINATION
 
- HCI_LK_DEBUG_COMBINATION
 
- HCI_LK_LOCAL_UNIT
 
- HCI_LK_REMOTE_UNIT
 
- HCI_LK_UNAUTH_COMBINATION_P192
 
- HCI_LK_UNAUTH_COMBINATION_P256
 
- HCI_LL_RPA_RESOLUTION
 
- HCI_LM_ACCEPT
 
- HCI_LM_AUTH
 
- HCI_LM_ENCRYPT
 
- HCI_LM_FIPS
 
- HCI_LM_MASTER
 
- HCI_LM_RELIABLE
 
- HCI_LM_SECURE
 
- HCI_LM_TRUSTED
 
- HCI_LOOPBACK
 
- HCI_LPM_HDR_SIZE
 
- HCI_LPM_MAX_SIZE
 
- HCI_LPM_PKT
 
- HCI_LPM_WAKE_PKT
 
- HCI_LP_HOLD
 
- HCI_LP_PARK
 
- HCI_LP_RSWITCH
 
- HCI_LP_SNIFF
 
- HCI_MAX_ACL_SIZE
 
- HCI_MAX_ADV_INSTANCES
 
- HCI_MAX_AD_LENGTH
 
- HCI_MAX_AMP_ASSOC_SIZE
 
- HCI_MAX_CSB_DATA_SIZE
 
- HCI_MAX_EIR_LENGTH
 
- HCI_MAX_EVENT_SIZE
 
- HCI_MAX_FRAME_SIZE
 
- HCI_MAX_IBS_SIZE
 
- HCI_MAX_NAME_LENGTH
 
- HCI_MAX_PAGES
 
- HCI_MAX_SCO_SIZE
 
- HCI_MAX_SHORT_NAME_LENGTH
 
- HCI_MGMT
 
- HCI_MGMT_DEV_CLASS_EVENTS
 
- HCI_MGMT_EXT_INDEX_EVENTS
 
- HCI_MGMT_EXT_INFO_EVENTS
 
- HCI_MGMT_INDEX_EVENTS
 
- HCI_MGMT_LOCAL_NAME_EVENTS
 
- HCI_MGMT_NO_HDEV
 
- HCI_MGMT_OOB_DATA_EVENTS
 
- HCI_MGMT_OPTION_EVENTS
 
- HCI_MGMT_SETTING_EVENTS
 
- HCI_MGMT_UNCONFIGURED
 
- HCI_MGMT_UNCONF_INDEX_EVENTS
 
- HCI_MGMT_UNTRUSTED
 
- HCI_MGMT_VAR_LEN
 
- HCI_MIN_ENC_KEY_SIZE
 
- HCI_MISC_SHIFT
 
- HCI_MODE
 
- HCI_MON_ACL_RX_PKT
 
- HCI_MON_ACL_TX_PKT
 
- HCI_MON_CLOSE_INDEX
 
- HCI_MON_COMMAND_PKT
 
- HCI_MON_CTRL_CLOSE
 
- HCI_MON_CTRL_COMMAND
 
- HCI_MON_CTRL_EVENT
 
- HCI_MON_CTRL_OPEN
 
- HCI_MON_DEL_INDEX
 
- HCI_MON_EVENT_PKT
 
- HCI_MON_HDR_SIZE
 
- HCI_MON_INDEX_INFO
 
- HCI_MON_INDEX_INFO_SIZE
 
- HCI_MON_NEW_INDEX
 
- HCI_MON_NEW_INDEX_SIZE
 
- HCI_MON_OPEN_INDEX
 
- HCI_MON_SCO_RX_PKT
 
- HCI_MON_SCO_TX_PKT
 
- HCI_MON_SYSTEM_NOTE
 
- HCI_MON_USER_LOGGING
 
- HCI_MON_VENDOR_DIAG
 
- HCI_MRVL_PKT_SIZE
 
- HCI_NOKIA_ALIVE_HDR_SIZE
 
- HCI_NOKIA_ALIVE_PKT
 
- HCI_NOKIA_MAX_ALIVE_SIZE
 
- HCI_NOKIA_MAX_NEG_SIZE
 
- HCI_NOKIA_MAX_RADIO_SIZE
 
- HCI_NOKIA_NEG_HDR_SIZE
 
- HCI_NOKIA_NEG_PKT
 
- HCI_NOKIA_RADIO_HDR_SIZE
 
- HCI_NOKIA_RADIO_PKT
 
- HCI_NOTIFY_CONN_ADD
 
- HCI_NOTIFY_CONN_DEL
 
- HCI_NOTIFY_VOICE_SETTING
 
- HCI_OP_ACCEPT_CONN_REQ
 
- HCI_OP_ACCEPT_LOGICAL_LINK
 
- HCI_OP_ACCEPT_PHY_LINK
 
- HCI_OP_ACCEPT_SYNC_CONN_REQ
 
- HCI_OP_ADD_SCO
 
- HCI_OP_ATH_SLEEP
 
- HCI_OP_AUTH_REQUESTED
 
- HCI_OP_CHANGE_CONN_LINK_KEY
 
- HCI_OP_CHANGE_CONN_PTYPE
 
- HCI_OP_CREATE_CONN
 
- HCI_OP_CREATE_CONN_CANCEL
 
- HCI_OP_CREATE_LOGICAL_LINK
 
- HCI_OP_CREATE_PHY_LINK
 
- HCI_OP_DELETE_RESERVED_LT_ADDR
 
- HCI_OP_DELETE_STORED_LINK_KEY
 
- HCI_OP_DISCONNECT
 
- HCI_OP_DISCONN_LOGICAL_LINK
 
- HCI_OP_DISCONN_PHY_LINK
 
- HCI_OP_ENABLE_DUT_MODE
 
- HCI_OP_EXIT_PERIODIC_INQ
 
- HCI_OP_EXIT_SNIFF_MODE
 
- HCI_OP_GET_MWS_TRANSPORT_CONFIG
 
- HCI_OP_HOST_BUFFER_SIZE
 
- HCI_OP_INQUIRY
 
- HCI_OP_INQUIRY_CANCEL
 
- HCI_OP_IO_CAPABILITY_NEG_REPLY
 
- HCI_OP_IO_CAPABILITY_REPLY
 
- HCI_OP_LE_ADD_TO_RESOLV_LIST
 
- HCI_OP_LE_ADD_TO_WHITE_LIST
 
- HCI_OP_LE_CLEAR_ADV_SETS
 
- HCI_OP_LE_CLEAR_RESOLV_LIST
 
- HCI_OP_LE_CLEAR_WHITE_LIST
 
- HCI_OP_LE_CONN_PARAM_REQ_NEG_REPLY
 
- HCI_OP_LE_CONN_PARAM_REQ_REPLY
 
- HCI_OP_LE_CONN_UPDATE
 
- HCI_OP_LE_CREATE_CONN
 
- HCI_OP_LE_CREATE_CONN_CANCEL
 
- HCI_OP_LE_DEL_FROM_RESOLV_LIST
 
- HCI_OP_LE_DEL_FROM_WHITE_LIST
 
- HCI_OP_LE_EXT_CREATE_CONN
 
- HCI_OP_LE_LTK_NEG_REPLY
 
- HCI_OP_LE_LTK_REPLY
 
- HCI_OP_LE_READ_ADV_TX_POWER
 
- HCI_OP_LE_READ_BUFFER_SIZE
 
- HCI_OP_LE_READ_DEF_DATA_LEN
 
- HCI_OP_LE_READ_LOCAL_FEATURES
 
- HCI_OP_LE_READ_MAX_DATA_LEN
 
- HCI_OP_LE_READ_NUM_SUPPORTED_ADV_SETS
 
- HCI_OP_LE_READ_REMOTE_FEATURES
 
- HCI_OP_LE_READ_RESOLV_LIST_SIZE
 
- HCI_OP_LE_READ_SUPPORTED_STATES
 
- HCI_OP_LE_READ_WHITE_LIST_SIZE
 
- HCI_OP_LE_SET_ADDR_RESOLV_ENABLE
 
- HCI_OP_LE_SET_ADV_DATA
 
- HCI_OP_LE_SET_ADV_ENABLE
 
- HCI_OP_LE_SET_ADV_PARAM
 
- HCI_OP_LE_SET_ADV_SET_RAND_ADDR
 
- HCI_OP_LE_SET_DATA_LEN
 
- HCI_OP_LE_SET_DEFAULT_PHY
 
- HCI_OP_LE_SET_EVENT_MASK
 
- HCI_OP_LE_SET_EXT_ADV_DATA
 
- HCI_OP_LE_SET_EXT_ADV_ENABLE
 
- HCI_OP_LE_SET_EXT_ADV_PARAMS
 
- HCI_OP_LE_SET_EXT_SCAN_ENABLE
 
- HCI_OP_LE_SET_EXT_SCAN_PARAMS
 
- HCI_OP_LE_SET_EXT_SCAN_RSP_DATA
 
- HCI_OP_LE_SET_RANDOM_ADDR
 
- HCI_OP_LE_SET_SCAN_ENABLE
 
- HCI_OP_LE_SET_SCAN_PARAM
 
- HCI_OP_LE_SET_SCAN_RSP_DATA
 
- HCI_OP_LE_START_ENC
 
- HCI_OP_LE_WRITE_DEF_DATA_LEN
 
- HCI_OP_LINK_KEY_NEG_REPLY
 
- HCI_OP_LINK_KEY_REPLY
 
- HCI_OP_LOGICAL_LINK_CANCEL
 
- HCI_OP_NOP
 
- HCI_OP_PERIODIC_INQ
 
- HCI_OP_PIN_CODE_NEG_REPLY
 
- HCI_OP_PIN_CODE_REPLY
 
- HCI_OP_READ_AUTH_ENABLE
 
- HCI_OP_READ_AUTH_PAYLOAD_TO
 
- HCI_OP_READ_BD_ADDR
 
- HCI_OP_READ_BUFFER_SIZE
 
- HCI_OP_READ_CLASS_OF_DEV
 
- HCI_OP_READ_CLOCK
 
- HCI_OP_READ_CLOCK_OFFSET
 
- HCI_OP_READ_CURRENT_IAC_LAP
 
- HCI_OP_READ_DATA_BLOCK_SIZE
 
- HCI_OP_READ_DEF_LINK_POLICY
 
- HCI_OP_READ_ENCRYPT_MODE
 
- HCI_OP_READ_ENC_KEY_SIZE
 
- HCI_OP_READ_FLOW_CONTROL_MODE
 
- HCI_OP_READ_INQ_RSP_TX_POWER
 
- HCI_OP_READ_LINK_POLICY
 
- HCI_OP_READ_LOCAL_AMP_ASSOC
 
- HCI_OP_READ_LOCAL_AMP_INFO
 
- HCI_OP_READ_LOCAL_CODECS
 
- HCI_OP_READ_LOCAL_COMMANDS
 
- HCI_OP_READ_LOCAL_EXT_FEATURES
 
- HCI_OP_READ_LOCAL_FEATURES
 
- HCI_OP_READ_LOCAL_NAME
 
- HCI_OP_READ_LOCAL_OOB_DATA
 
- HCI_OP_READ_LOCAL_OOB_EXT_DATA
 
- HCI_OP_READ_LOCAL_VERSION
 
- HCI_OP_READ_LOCATION_DATA
 
- HCI_OP_READ_NUM_SUPPORTED_IAC
 
- HCI_OP_READ_PAGE_SCAN_ACTIVITY
 
- HCI_OP_READ_PAGE_SCAN_TYPE
 
- HCI_OP_READ_REMOTE_EXT_FEATURES
 
- HCI_OP_READ_REMOTE_FEATURES
 
- HCI_OP_READ_REMOTE_VERSION
 
- HCI_OP_READ_RSSI
 
- HCI_OP_READ_SC_SUPPORT
 
- HCI_OP_READ_SSP_MODE
 
- HCI_OP_READ_STORED_LINK_KEY
 
- HCI_OP_READ_SYNC_TRAIN_PARAMS
 
- HCI_OP_READ_TX_POWER
 
- HCI_OP_READ_VOICE_SETTING
 
- HCI_OP_REJECT_CONN_REQ
 
- HCI_OP_REJECT_SYNC_CONN_REQ
 
- HCI_OP_REMOTE_NAME_REQ
 
- HCI_OP_REMOTE_NAME_REQ_CANCEL
 
- HCI_OP_REMOTE_OOB_DATA_NEG_REPLY
 
- HCI_OP_REMOTE_OOB_DATA_REPLY
 
- HCI_OP_REMOTE_OOB_EXT_DATA_REPLY
 
- HCI_OP_RESET
 
- HCI_OP_ROLE_DISCOVERY
 
- HCI_OP_SETUP_SYNC_CONN
 
- HCI_OP_SET_CONN_ENCRYPT
 
- HCI_OP_SET_CSB
 
- HCI_OP_SET_CSB_DATA
 
- HCI_OP_SET_EVENT_FLT
 
- HCI_OP_SET_EVENT_MASK
 
- HCI_OP_SET_EVENT_MASK_PAGE_2
 
- HCI_OP_SET_RESERVED_LT_ADDR
 
- HCI_OP_SNIFF_MODE
 
- HCI_OP_SNIFF_SUBRATE
 
- HCI_OP_START_SYNC_TRAIN
 
- HCI_OP_SWITCH_ROLE
 
- HCI_OP_USER_CONFIRM_NEG_REPLY
 
- HCI_OP_USER_CONFIRM_REPLY
 
- HCI_OP_USER_PASSKEY_NEG_REPLY
 
- HCI_OP_USER_PASSKEY_REPLY
 
- HCI_OP_WRITE_AUTH_ENABLE
 
- HCI_OP_WRITE_AUTH_PAYLOAD_TO
 
- HCI_OP_WRITE_CA_TIMEOUT
 
- HCI_OP_WRITE_CLASS_OF_DEV
 
- HCI_OP_WRITE_CURRENT_IAC_LAP
 
- HCI_OP_WRITE_DEF_LINK_POLICY
 
- HCI_OP_WRITE_EIR
 
- HCI_OP_WRITE_ENCRYPT_MODE
 
- HCI_OP_WRITE_INQUIRY_MODE
 
- HCI_OP_WRITE_LE_HOST_SUPPORTED
 
- HCI_OP_WRITE_LINK_POLICY
 
- HCI_OP_WRITE_LOCAL_NAME
 
- HCI_OP_WRITE_PAGE_SCAN_ACTIVITY
 
- HCI_OP_WRITE_PAGE_SCAN_TYPE
 
- HCI_OP_WRITE_PG_TIMEOUT
 
- HCI_OP_WRITE_REMOTE_AMP_ASSOC
 
- HCI_OP_WRITE_SCAN_ENABLE
 
- HCI_OP_WRITE_SC_SUPPORT
 
- HCI_OP_WRITE_SSP_DEBUG_MODE
 
- HCI_OP_WRITE_SSP_MODE
 
- HCI_OP_WRITE_SYNC_TRAIN_PARAMS
 
- HCI_OP_WRITE_VOICE_SETTING
 
- HCI_PAIRING_TIMEOUT
 
- HCI_PCCARD
 
- HCI_PCI
 
- HCI_PERIODIC_INQ
 
- HCI_PHY_HANDLE
 
- HCI_POWER_OFF_TIMEOUT
 
- HCI_PRIMARY
 
- HCI_PRIO_MAX
 
- HCI_PRIVACY
 
- HCI_PROTO_DEFER
 
- HCI_PSCAN
 
- HCI_QUIRK_BROKEN_LOCAL_COMMANDS
 
- HCI_QUIRK_BROKEN_STORED_LINK_KEY
 
- HCI_QUIRK_EXTERNAL_CONFIG
 
- HCI_QUIRK_FIXUP_BUFFER_SIZE
 
- HCI_QUIRK_FIXUP_INQUIRY_MODE
 
- HCI_QUIRK_INVALID_BDADDR
 
- HCI_QUIRK_NON_PERSISTENT_DIAG
 
- HCI_QUIRK_NON_PERSISTENT_SETUP
 
- HCI_QUIRK_RAW_DEVICE
 
- HCI_QUIRK_RESET_ON_CLOSE
 
- HCI_QUIRK_SIMULTANEOUS_DISCOVERY
 
- HCI_QUIRK_STRICT_DUPLICATE_FILTER
 
- HCI_QUIRK_USE_BDADDR_PROPERTY
 
- HCI_RAW
 
- HCI_RECV_CHIP_VER
 
- HCI_RECV_FW_REQ
 
- HCI_RECV_VENDOR
 
- HCI_REQ_CANCELED
 
- HCI_REQ_DONE
 
- HCI_REQ_PEND
 
- HCI_REQ_SKB
 
- HCI_REQ_START
 
- HCI_RESET
 
- HCI_RESUME_PWR_RDY
 
- HCI_RFKILLED
 
- HCI_ROLE_MASTER
 
- HCI_ROLE_SLAVE
 
- HCI_RPA_EXPIRED
 
- HCI_RPA_RESOLVING
 
- HCI_RS232
 
- HCI_RSSI_INVALID
 
- HCI_RUNNING
 
- HCI_RXDMA_EN
 
- HCI_SCODATA_PKT
 
- HCI_SCO_HDR_SIZE
 
- HCI_SC_ENABLED
 
- HCI_SC_ONLY
 
- HCI_SDIO
 
- HCI_SEL
 
- HCI_SERVICE_CACHE
 
- HCI_SET
 
- HCI_SETUP
 
- HCI_SFLT_MAX_OGF
 
- HCI_SMD
 
- HCI_SOCK_TRUSTED
 
- HCI_SPI
 
- HCI_SSP_ENABLED
 
- HCI_SUS_CTRL
 
- HCI_SYSTEM_EVENT
 
- HCI_SYSTEM_INFO
 
- HCI_SYSTEM_TYPE1
 
- HCI_SYSTEM_TYPE2
 
- HCI_TEST_SYSCFG_HWMASK
 
- HCI_TIME_STAMP
 
- HCI_TR_BACKLIGHT
 
- HCI_TXDMA_EN
 
- HCI_TX_POWER_INVALID
 
- HCI_UART
 
- HCI_UART_3WIRE
 
- HCI_UART_AG6XX
 
- HCI_UART_ATH3K
 
- HCI_UART_BCM
 
- HCI_UART_BCSP
 
- HCI_UART_CREATE_AMP
 
- HCI_UART_EXT_CONFIG
 
- HCI_UART_H4
 
- HCI_UART_H4DS
 
- HCI_UART_INIT_PENDING
 
- HCI_UART_INTEL
 
- HCI_UART_LL
 
- HCI_UART_MAX_PROTO
 
- HCI_UART_MRVL
 
- HCI_UART_NOKIA
 
- HCI_UART_PROTO_READY
 
- HCI_UART_PROTO_SET
 
- HCI_UART_QCA
 
- HCI_UART_RAW_DEVICE
 
- HCI_UART_REGISTERED
 
- HCI_UART_RESET_ON_INIT
 
- HCI_UART_SENDING
 
- HCI_UART_TX_WAKEUP
 
- HCI_UART_VND_DETECT
 
- HCI_UNCONFIGURED
 
- HCI_UNREGISTER
 
- HCI_UP
 
- HCI_USB
 
- HCI_USER_CHANNEL
 
- HCI_USE_DEBUG_KEYS
 
- HCI_VENDOR_DIAG
 
- HCI_VENDOR_HDR_SIZE
 
- HCI_VENDOR_PKT
 
- HCI_VIDEO_OUT
 
- HCI_VIDEO_OUT_CRT
 
- HCI_VIDEO_OUT_LCD
 
- HCI_VIDEO_OUT_TV
 
- HCI_VIRTUAL
 
- HCI_VS_UPDATE_UART_HCI_BAUDRATE
 
- HCI_VS_WRITE_BD_ADDR
 
- HCI_WIRELESS
 
- HCI_WIRELESS_STATUS
 
- HCI_WIRELESS_WWAN
 
- HCI_WIRELESS_WWAN_POWER
 
- HCI_WIRELESS_WWAN_STATUS
 
- HCI_WMT_MAX_EVENT_SIZE
 
- HCLGEVF_ADVERTISING
 
- HCLGEVF_CMDQ_INTR_EN_REG
 
- HCLGEVF_CMDQ_INTR_GEN_REG
 
- HCLGEVF_CMDQ_INTR_SRC_REG
 
- HCLGEVF_CMDQ_INTR_STS_REG
 
- HCLGEVF_CMDQ_RX_ADDR_H_REG
 
- HCLGEVF_CMDQ_RX_ADDR_L_REG
 
- HCLGEVF_CMDQ_RX_DEPTH_REG
 
- HCLGEVF_CMDQ_RX_HEAD_REG
 
- HCLGEVF_CMDQ_RX_INVLD_B
 
- HCLGEVF_CMDQ_RX_OUTVLD_B
 
- HCLGEVF_CMDQ_RX_TAIL_REG
 
- HCLGEVF_CMDQ_TX_ADDR_H_REG
 
- HCLGEVF_CMDQ_TX_ADDR_L_REG
 
- HCLGEVF_CMDQ_TX_DEPTH_REG
 
- HCLGEVF_CMDQ_TX_HEAD_REG
 
- HCLGEVF_CMDQ_TX_TAIL_REG
 
- HCLGEVF_CMDQ_TX_TIMEOUT
 
- HCLGEVF_CMD_EXEC_SUCCESS
 
- HCLGEVF_CMD_FLAG_ERR_INTR
 
- HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT
 
- HCLGEVF_CMD_FLAG_IN
 
- HCLGEVF_CMD_FLAG_IN_VALID_SHIFT
 
- HCLGEVF_CMD_FLAG_NEXT
 
- HCLGEVF_CMD_FLAG_NEXT_SHIFT
 
- HCLGEVF_CMD_FLAG_NO_INTR
 
- HCLGEVF_CMD_FLAG_NO_INTR_SHIFT
 
- HCLGEVF_CMD_FLAG_OUT
 
- HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT
 
- HCLGEVF_CMD_FLAG_WR
 
- HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT
 
- HCLGEVF_CMD_HILINK_ERR
 
- HCLGEVF_CMD_INVALID
 
- HCLGEVF_CMD_NEXT_ERR
 
- HCLGEVF_CMD_NOT_SUPPORTED
 
- HCLGEVF_CMD_NO_AUTH
 
- HCLGEVF_CMD_PARA_ERR
 
- HCLGEVF_CMD_QUEUE_FULL
 
- HCLGEVF_CMD_QUEUE_ILLEGAL
 
- HCLGEVF_CMD_RESULT_ERR
 
- HCLGEVF_CMD_TIMEOUT
 
- HCLGEVF_CMD_UNEXE_ERR
 
- HCLGEVF_CORE_RST_ING_BIT
 
- HCLGEVF_DRIVER_NAME
 
- HCLGEVF_D_IP_BIT
 
- HCLGEVF_D_PORT_BIT
 
- HCLGEVF_ERR_CSQ_ERROR
 
- HCLGEVF_ERR_CSQ_FULL
 
- HCLGEVF_ERR_CSQ_TIMEOUT
 
- HCLGEVF_FLR_WAIT_CNT
 
- HCLGEVF_FLR_WAIT_MS
 
- HCLGEVF_FUN_RST_ING_BIT
 
- HCLGEVF_GENERAL_TASK_INTERVAL
 
- HCLGEVF_GLOBAL_RST_ING_BIT
 
- HCLGEVF_GRO_EN_B
 
- HCLGEVF_GRO_EN_REG
 
- HCLGEVF_IMP_RST_ING_BIT
 
- HCLGEVF_INT_EVENT
 
- HCLGEVF_INT_RX
 
- HCLGEVF_INT_TX
 
- HCLGEVF_INT_TYPE_M
 
- HCLGEVF_INT_TYPE_S
 
- HCLGEVF_INVALID_VPORT
 
- HCLGEVF_KEEP_ALIVE_TASK_INTERVAL
 
- HCLGEVF_LINK_STATUS
 
- HCLGEVF_LINK_STS_B
 
- HCLGEVF_MAX_SYNC_COUNT
 
- HCLGEVF_MAX_TC_NUM
 
- HCLGEVF_MAX_TRY_TIMES
 
- HCLGEVF_MAX_VF_VECTOR_NUM
 
- HCLGEVF_MAX_VLAN_ID
 
- HCLGEVF_MISC_VECTOR_NUM
 
- HCLGEVF_MISC_VECTOR_REG_BASE
 
- HCLGEVF_MOD_VERSION
 
- HCLGEVF_MPF_ENBALE
 
- HCLGEVF_MSIX_OFT_ROCEE_M
 
- HCLGEVF_MSIX_OFT_ROCEE_S
 
- HCLGEVF_NAME
 
- HCLGEVF_NIC_CMDQ_INT_SRC_REG
 
- HCLGEVF_NIC_CMQ_DESC_NUM
 
- HCLGEVF_NIC_CMQ_DESC_NUM_S
 
- HCLGEVF_NIC_CRQ_BASEADDR_H_REG
 
- HCLGEVF_NIC_CRQ_BASEADDR_L_REG
 
- HCLGEVF_NIC_CRQ_DEPTH_REG
 
- HCLGEVF_NIC_CRQ_HEAD_REG
 
- HCLGEVF_NIC_CRQ_TAIL_REG
 
- HCLGEVF_NIC_CSQ_BASEADDR_H_REG
 
- HCLGEVF_NIC_CSQ_BASEADDR_L_REG
 
- HCLGEVF_NIC_CSQ_DEPTH_REG
 
- HCLGEVF_NIC_CSQ_HEAD_REG
 
- HCLGEVF_NIC_CSQ_TAIL_REG
 
- HCLGEVF_NIC_SW_RST_RDY
 
- HCLGEVF_NIC_SW_RST_RDY_B
 
- HCLGEVF_OPC_CFG_COM_TQP_QUEUE
 
- HCLGEVF_OPC_GRO_GENERIC_CONFIG
 
- HCLGEVF_OPC_MBX_PF_TO_VF
 
- HCLGEVF_OPC_MBX_VF_TO_PF
 
- HCLGEVF_OPC_QUERY_FW_VER
 
- HCLGEVF_OPC_QUERY_RX_STATUS
 
- HCLGEVF_OPC_QUERY_TX_STATUS
 
- HCLGEVF_OPC_QUERY_VF_RSRC
 
- HCLGEVF_OPC_RSS_GENERIC_CONFIG
 
- HCLGEVF_OPC_RSS_INDIR_TABLE
 
- HCLGEVF_OPC_RSS_INPUT_TUPLE
 
- HCLGEVF_OPC_RSS_TC_MODE
 
- HCLGEVF_RESET_MAX_FAIL_CNT
 
- HCLGEVF_RESET_PENDING
 
- HCLGEVF_RESET_REQUESTED
 
- HCLGEVF_RESET_SYNC_TIME
 
- HCLGEVF_RESET_WAIT_CNT
 
- HCLGEVF_RESET_WAIT_TIMEOUT_US
 
- HCLGEVF_RESET_WAIT_US
 
- HCLGEVF_RING_EN_REG
 
- HCLGEVF_RING_ID_MASK
 
- HCLGEVF_RING_RX_ADDR_H_REG
 
- HCLGEVF_RING_RX_ADDR_L_REG
 
- HCLGEVF_RING_RX_BD_ERR_REG
 
- HCLGEVF_RING_RX_BD_LENGTH_REG
 
- HCLGEVF_RING_RX_BD_NUM_REG
 
- HCLGEVF_RING_RX_FBD_NUM_REG
 
- HCLGEVF_RING_RX_FBD_OFFSET_REG
 
- HCLGEVF_RING_RX_HEAD_REG
 
- HCLGEVF_RING_RX_MERGE_EN_REG
 
- HCLGEVF_RING_RX_OFFSET_REG
 
- HCLGEVF_RING_RX_STASH_REG
 
- HCLGEVF_RING_RX_TAIL_REG
 
- HCLGEVF_RING_TX_ADDR_H_REG
 
- HCLGEVF_RING_TX_ADDR_L_REG
 
- HCLGEVF_RING_TX_BD_ERR_REG
 
- HCLGEVF_RING_TX_BD_NUM_REG
 
- HCLGEVF_RING_TX_EBD_NUM_REG
 
- HCLGEVF_RING_TX_EBD_OFFSET_REG
 
- HCLGEVF_RING_TX_FBD_NUM_REG
 
- HCLGEVF_RING_TX_HEAD_REG
 
- HCLGEVF_RING_TX_MERGE_EN_REG
 
- HCLGEVF_RING_TX_OFFSET_REG
 
- HCLGEVF_RING_TX_PRIORITY_REG
 
- HCLGEVF_RING_TX_TAIL_REG
 
- HCLGEVF_RING_TX_TC_REG
 
- HCLGEVF_RSS_CFG_TBL_NUM
 
- HCLGEVF_RSS_CFG_TBL_SIZE
 
- HCLGEVF_RSS_DEFAULT_OUTPORT_B
 
- HCLGEVF_RSS_HASH_ALGO_MASK
 
- HCLGEVF_RSS_HASH_ALGO_SIMPLE
 
- HCLGEVF_RSS_HASH_ALGO_SYMMETRIC
 
- HCLGEVF_RSS_HASH_ALGO_TOEPLITZ
 
- HCLGEVF_RSS_HASH_KEY_NUM
 
- HCLGEVF_RSS_HASH_KEY_OFFSET_B
 
- HCLGEVF_RSS_IND_TBL_SIZE
 
- HCLGEVF_RSS_INPUT_TUPLE_OTHER
 
- HCLGEVF_RSS_INPUT_TUPLE_SCTP
 
- HCLGEVF_RSS_KEY_SIZE
 
- HCLGEVF_RSS_MBX_RESP_LEN
 
- HCLGEVF_RSS_SET_BITMAP_MSK
 
- HCLGEVF_RSS_TC_OFFSET_M
 
- HCLGEVF_RSS_TC_OFFSET_S
 
- HCLGEVF_RSS_TC_SIZE_M
 
- HCLGEVF_RSS_TC_SIZE_S
 
- HCLGEVF_RSS_TC_VALID_B
 
- HCLGEVF_RST_ING
 
- HCLGEVF_RST_ING_BITS
 
- HCLGEVF_SEND_SYNC
 
- HCLGEVF_SLEEP_USECOND
 
- HCLGEVF_STATE_CMD_DISABLE
 
- HCLGEVF_STATE_DISABLED
 
- HCLGEVF_STATE_DOWN
 
- HCLGEVF_STATE_IRQ_INITED
 
- HCLGEVF_STATE_MBX_HANDLING
 
- HCLGEVF_STATE_MBX_SERVICE_SCHED
 
- HCLGEVF_STATE_NIC_REGISTERED
 
- HCLGEVF_STATE_REMOVING
 
- HCLGEVF_STATE_RST_HANDLING
 
- HCLGEVF_STATE_RST_SERVICE_SCHED
 
- HCLGEVF_STATE_SERVICE_SCHED
 
- HCLGEVF_STATS_TIMER_INTERVAL
 
- HCLGEVF_STATUS_SUCCESS
 
- HCLGEVF_SUPPORTED
 
- HCLGEVF_S_IP_BIT
 
- HCLGEVF_S_PORT_BIT
 
- HCLGEVF_TQPS_DEPTH_INFO_LEN
 
- HCLGEVF_TQPS_RSS_INFO_LEN
 
- HCLGEVF_TQP_ENABLE_B
 
- HCLGEVF_TQP_ID_M
 
- HCLGEVF_TQP_ID_S
 
- HCLGEVF_TQP_INTR_CTRL_REG
 
- HCLGEVF_TQP_INTR_GL0_REG
 
- HCLGEVF_TQP_INTR_GL1_REG
 
- HCLGEVF_TQP_INTR_GL2_REG
 
- HCLGEVF_TQP_INTR_RL_REG
 
- HCLGEVF_TQP_MAP_EN_B
 
- HCLGEVF_TQP_MAP_TYPE_B
 
- HCLGEVF_TQP_MAP_TYPE_PF
 
- HCLGEVF_TQP_MAP_TYPE_VF
 
- HCLGEVF_TQP_REG_OFFSET
 
- HCLGEVF_TQP_REG_SIZE
 
- HCLGEVF_TQP_RESET_TRY_TIMES
 
- HCLGEVF_TYPE_CRQ
 
- HCLGEVF_TYPE_CSQ
 
- HCLGEVF_VECTOR0_CMDQ_SRC_REG
 
- HCLGEVF_VECTOR0_CMDQ_STAT_REG
 
- HCLGEVF_VECTOR0_EVENT_MBX
 
- HCLGEVF_VECTOR0_EVENT_OTHER
 
- HCLGEVF_VECTOR0_EVENT_RST
 
- HCLGEVF_VECTOR0_RST_INT_B
 
- HCLGEVF_VECTOR0_RX_CMDQ_INT_B
 
- HCLGEVF_VECTOR_ELEMENTS_PER_CMD
 
- HCLGEVF_VECTOR_REG_BASE
 
- HCLGEVF_VECTOR_REG_OFFSET
 
- HCLGEVF_VECTOR_VF_OFFSET
 
- HCLGEVF_VEC_NUM_M
 
- HCLGEVF_VEC_NUM_S
 
- HCLGEVF_VF_RST_ING
 
- HCLGEVF_VF_RST_ING_BIT
 
- HCLGEVF_VLAN_MBX_MSG_LEN
 
- HCLGEVF_V_TAG_BIT
 
- HCLGE_32_BIT_DESC_NODATA_LEN
 
- HCLGE_32_BIT_REG_RTN_DATANUM
 
- HCLGE_64_BIT_DESC_NODATA_LEN
 
- HCLGE_64_BIT_REG_RTN_DATANUM
 
- HCLGE_ACCEPT_TAG1_B
 
- HCLGE_ACCEPT_TAG2_B
 
- HCLGE_ACCEPT_UNTAG1_B
 
- HCLGE_ACCEPT_UNTAG2_B
 
- HCLGE_ADD_MC_OVERFLOW
 
- HCLGE_ADD_UC_OVERFLOW
 
- HCLGE_ALLOC_VALID_B
 
- HCLGE_BILLION_NANO_SECONDS
 
- HCLGE_BP_GRP_ID_M
 
- HCLGE_BP_GRP_ID_S
 
- HCLGE_BP_GRP_NUM
 
- HCLGE_BP_SUB_GRP_ID_M
 
- HCLGE_BP_SUB_GRP_ID_S
 
- HCLGE_BROADCAST
 
- HCLGE_BUF_DIV_BY
 
- HCLGE_BUF_MUL_BY
 
- HCLGE_BUF_SIZE_UNIT
 
- HCLGE_BUF_SIZE_UNIT_SHIFT
 
- HCLGE_BUF_SIZE_UPDATE_EN_MSK
 
- HCLGE_BUF_UNIT_S
 
- HCLGE_CFG_DEFAULT_SPEED_M
 
- HCLGE_CFG_DEFAULT_SPEED_S
 
- HCLGE_CFG_DUPLEX_B
 
- HCLGE_CFG_DUPLEX_M
 
- HCLGE_CFG_MAC_ADDR_H_M
 
- HCLGE_CFG_MAC_ADDR_H_S
 
- HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
 
- HCLGE_CFG_MEDIA_TP_M
 
- HCLGE_CFG_MEDIA_TP_S
 
- HCLGE_CFG_NIC_ROCE_SEL_B
 
- HCLGE_CFG_OFFSET_M
 
- HCLGE_CFG_OFFSET_S
 
- HCLGE_CFG_PHY_ADDR_M
 
- HCLGE_CFG_PHY_ADDR_S
 
- HCLGE_CFG_RD_LEN_BYTES
 
- HCLGE_CFG_RD_LEN_M
 
- HCLGE_CFG_RD_LEN_S
 
- HCLGE_CFG_RD_LEN_UNIT
 
- HCLGE_CFG_RESET_FUNC_B
 
- HCLGE_CFG_RESET_MAC_B
 
- HCLGE_CFG_RSS_SIZE_M
 
- HCLGE_CFG_RSS_SIZE_S
 
- HCLGE_CFG_RX_BUF_LEN_M
 
- HCLGE_CFG_RX_BUF_LEN_S
 
- HCLGE_CFG_SPEED_ABILITY_M
 
- HCLGE_CFG_SPEED_ABILITY_S
 
- HCLGE_CFG_SPEED_M
 
- HCLGE_CFG_SPEED_S
 
- HCLGE_CFG_TC_NUM_M
 
- HCLGE_CFG_TC_NUM_S
 
- HCLGE_CFG_TQP_DESC_N_M
 
- HCLGE_CFG_TQP_DESC_N_S
 
- HCLGE_CFG_UMV_TBL_SPACE_M
 
- HCLGE_CFG_UMV_TBL_SPACE_S
 
- HCLGE_CFG_VMDQ_M
 
- HCLGE_CFG_VMDQ_S
 
- HCLGE_CMDQ_INTR_EN_REG
 
- HCLGE_CMDQ_INTR_GEN_REG
 
- HCLGE_CMDQ_INTR_SRC_REG
 
- HCLGE_CMDQ_INTR_STS_REG
 
- HCLGE_CMDQ_NIC_ECC_ERR_INT_EN
 
- HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK
 
- HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN
 
- HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK
 
- HCLGE_CMDQ_RX_ADDR_H_REG
 
- HCLGE_CMDQ_RX_ADDR_L_REG
 
- HCLGE_CMDQ_RX_DEPTH_REG
 
- HCLGE_CMDQ_RX_HEAD_REG
 
- HCLGE_CMDQ_RX_INVLD_B
 
- HCLGE_CMDQ_RX_OUTVLD_B
 
- HCLGE_CMDQ_RX_TAIL_REG
 
- HCLGE_CMDQ_TX_ADDR_H_REG
 
- HCLGE_CMDQ_TX_ADDR_L_REG
 
- HCLGE_CMDQ_TX_DEPTH_REG
 
- HCLGE_CMDQ_TX_HEAD_REG
 
- HCLGE_CMDQ_TX_TAIL_REG
 
- HCLGE_CMDQ_TX_TIMEOUT
 
- HCLGE_CMD_DATA_NUM
 
- HCLGE_CMD_EXEC_SUCCESS
 
- HCLGE_CMD_FLAG_ERR_INTR
 
- HCLGE_CMD_FLAG_IN
 
- HCLGE_CMD_FLAG_NEXT
 
- HCLGE_CMD_FLAG_NO_INTR
 
- HCLGE_CMD_FLAG_OUT
 
- HCLGE_CMD_FLAG_WR
 
- HCLGE_CMD_HILINK_ERR
 
- HCLGE_CMD_INVALID
 
- HCLGE_CMD_NCL_CONFIG_BD_NUM
 
- HCLGE_CMD_NEXT_ERR
 
- HCLGE_CMD_NOT_SUPPORTED
 
- HCLGE_CMD_NO_AUTH
 
- HCLGE_CMD_PARA_ERR
 
- HCLGE_CMD_QUEUE_FULL
 
- HCLGE_CMD_QUEUE_ILLEGAL
 
- HCLGE_CMD_RESULT_ERR
 
- HCLGE_CMD_SERDES_DONE_B
 
- HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B
 
- HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B
 
- HCLGE_CMD_SERDES_SUCCESS_B
 
- HCLGE_CMD_TIMEOUT
 
- HCLGE_CMD_UNEXE_ERR
 
- HCLGE_COMMON_ECC_INT_CFG
 
- HCLGE_CONFIG_ROCEE_RAS_INT_EN
 
- HCLGE_CORE_RESET_BIT
 
- HCLGE_DBG_BUF_LEN
 
- HCLGE_DBG_DFX_BIOS_OFFSET
 
- HCLGE_DBG_DFX_IGU_OFFSET
 
- HCLGE_DBG_DFX_NCSI_OFFSET
 
- HCLGE_DBG_DFX_PPP_OFFSET
 
- HCLGE_DBG_DFX_RCB_OFFSET
 
- HCLGE_DBG_DFX_RPU_0_OFFSET
 
- HCLGE_DBG_DFX_RPU_1_OFFSET
 
- HCLGE_DBG_DFX_RTC_OFFSET
 
- HCLGE_DBG_DFX_SSU_0_OFFSET
 
- HCLGE_DBG_DFX_SSU_1_OFFSET
 
- HCLGE_DBG_DFX_SSU_2_OFFSET
 
- HCLGE_DBG_DFX_TQP_OFFSET
 
- HCLGE_DBG_MAC_REG_TYPE_LEN
 
- HCLGE_DBG_MAX_DFX_MSG_LEN
 
- HCLGE_DBG_MNG_DROP_B
 
- HCLGE_DBG_MNG_ETHER_MASK_B
 
- HCLGE_DBG_MNG_E_TYPE_B
 
- HCLGE_DBG_MNG_MAC_MASK_B
 
- HCLGE_DBG_MNG_PF_ID
 
- HCLGE_DBG_MNG_TBL_MAX
 
- HCLGE_DBG_MNG_VF_ID
 
- HCLGE_DBG_MNG_VLAN_MASK_B
 
- HCLGE_DBG_MNG_VLAN_TAG
 
- HCLGE_DEFAULT_DV
 
- HCLGE_DEFAULT_NON_DCB_DV
 
- HCLGE_DEFAULT_PAUSE_TRANS_GAP
 
- HCLGE_DEFAULT_PAUSE_TRANS_TIME
 
- HCLGE_DEFAULT_TX_BUF
 
- HCLGE_DEFAULT_UMV_SPACE_PER_PF
 
- HCLGE_DEF_VLAN_TYPE
 
- HCLGE_DESC_NO_DATA_LEN
 
- HCLGE_DESC_NUM
 
- HCLGE_DESC_NUMBER
 
- HCLGE_DEV_STATE
 
- HCLGE_DFX_BIOS_BD_OFFSET
 
- HCLGE_DFX_IGU_BD_OFFSET
 
- HCLGE_DFX_NCSI_BD_OFFSET
 
- HCLGE_DFX_PPP_BD_OFFSET
 
- HCLGE_DFX_RCB_BD_OFFSET
 
- HCLGE_DFX_REG_BD_NUM
 
- HCLGE_DFX_RPU_0_BD_OFFSET
 
- HCLGE_DFX_RPU_1_BD_OFFSET
 
- HCLGE_DFX_RTC_BD_OFFSET
 
- HCLGE_DFX_SSU_0_BD_OFFSET
 
- HCLGE_DFX_SSU_1_BD_OFFSET
 
- HCLGE_DFX_SSU_2_BD_OFFSET
 
- HCLGE_DFX_TQP_BD_OFFSET
 
- HCLGE_DRIVER_NAME
 
- HCLGE_D_IP_BIT
 
- HCLGE_D_PORT_BIT
 
- HCLGE_ERR_CSQ_ERROR
 
- HCLGE_ERR_CSQ_FULL
 
- HCLGE_ERR_CSQ_TIMEOUT
 
- HCLGE_ERR_INT_MSIX
 
- HCLGE_ERR_INT_RAS_CE
 
- HCLGE_ERR_INT_RAS_FE
 
- HCLGE_ERR_INT_RAS_NFE
 
- HCLGE_ETHERTYPE_ALREADY_ADD
 
- HCLGE_ETHERTYPE_KEY_CONFLICT
 
- HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW
 
- HCLGE_ETHERTYPE_SUCCESS_ADD
 
- HCLGE_ETHER_MAX_RATE
 
- HCLGE_FC_DEFAULT
 
- HCLGE_FC_FULL
 
- HCLGE_FC_NONE
 
- HCLGE_FC_PFC
 
- HCLGE_FC_RX_PAUSE
 
- HCLGE_FC_TX_PAUSE
 
- HCLGE_FD_ACTION
 
- HCLGE_FD_ACTION_ACCEPT_PACKET
 
- HCLGE_FD_ACTION_DROP_PACKET
 
- HCLGE_FD_ACTIVE_RULE_TYPE
 
- HCLGE_FD_AD_COUNTER_NUM_M
 
- HCLGE_FD_AD_COUNTER_NUM_S
 
- HCLGE_FD_AD_DIRECT_QID_B
 
- HCLGE_FD_AD_DROP_B
 
- HCLGE_FD_AD_NXT_KEY_M
 
- HCLGE_FD_AD_NXT_KEY_S
 
- HCLGE_FD_AD_NXT_STEP_B
 
- HCLGE_FD_AD_QID_M
 
- HCLGE_FD_AD_QID_S
 
- HCLGE_FD_AD_RULE_ID_M
 
- HCLGE_FD_AD_RULE_ID_S
 
- HCLGE_FD_AD_USE_COUNTER_B
 
- HCLGE_FD_AD_WR_RULE_ID_B
 
- HCLGE_FD_ARFS_ACTIVE
 
- HCLGE_FD_ARFS_EXPIRE_TIMER_INTERVAL
 
- HCLGE_FD_EPORT_SW_EN_B
 
- HCLGE_FD_EP_ACTIVE
 
- HCLGE_FD_KEY_BASE_ON_PTYPE
 
- HCLGE_FD_KEY_BASE_ON_TUPLE
 
- HCLGE_FD_KEY_TYPE
 
- HCLGE_FD_META_DATA
 
- HCLGE_FD_MODE
 
- HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2
 
- HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2
 
- HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1
 
- HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1
 
- HCLGE_FD_PACKET_TYPE
 
- HCLGE_FD_RULE_NONE
 
- HCLGE_FD_STAGE
 
- HCLGE_FD_STAGE_1
 
- HCLGE_FD_STAGE_2
 
- HCLGE_FD_TUPLE
 
- HCLGE_FILTER_FE_EGRESS
 
- HCLGE_FILTER_FE_EGRESS_V1_B
 
- HCLGE_FILTER_FE_INGRESS
 
- HCLGE_FILTER_FE_NIC_EGRESS_B
 
- HCLGE_FILTER_FE_NIC_INGRESS_B
 
- HCLGE_FILTER_FE_ROCE_EGRESS_B
 
- HCLGE_FILTER_FE_ROCE_INGRESS_B
 
- HCLGE_FILTER_TYPE_PORT
 
- HCLGE_FILTER_TYPE_VF
 
- HCLGE_FLAG_DCB_CAPABLE
 
- HCLGE_FLAG_DCB_ENABLE
 
- HCLGE_FLAG_MAIN
 
- HCLGE_FLAG_MQPRIO_ENABLE
 
- HCLGE_FLAG_TC_BASE_SCH_MODE
 
- HCLGE_FLAG_VNET_BASE_SCH_MODE
 
- HCLGE_FLR_WAIT_CNT
 
- HCLGE_FLR_WAIT_MS
 
- HCLGE_FUNC_NUMBER_PER_DESC
 
- HCLGE_FUNC_RESET_STS_REG
 
- HCLGE_FUN_RST_ING
 
- HCLGE_FUN_RST_ING_B
 
- HCLGE_GET_DFX_REG_TYPE_CNT
 
- HCLGE_GLOBAL_RESET_BIT
 
- HCLGE_GLOBAL_RESET_REG
 
- HCLGE_GRO_EN_B
 
- HCLGE_GRO_EN_REG
 
- HCLGE_IGU_COMMON_INT_EN
 
- HCLGE_IGU_EGU_TNL_INT_EN
 
- HCLGE_IGU_EGU_TNL_INT_MASK
 
- HCLGE_IGU_ERR_INT_EN
 
- HCLGE_IGU_ERR_INT_EN_MASK
 
- HCLGE_IGU_INT_MASK
 
- HCLGE_IGU_TNL_ERR_INT_EN
 
- HCLGE_IGU_TNL_ERR_INT_EN_MASK
 
- HCLGE_IMP_ITCM4_ECC_ERR_INT_EN
 
- HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK
 
- HCLGE_IMP_RD_POISON_ERR_INT_EN
 
- HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK
 
- HCLGE_IMP_RESET_BIT
 
- HCLGE_IMP_TCM_ECC_ERR_INT_EN
 
- HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK
 
- HCLGE_INT_EVENT
 
- HCLGE_INT_GL_IDX_M
 
- HCLGE_INT_GL_IDX_S
 
- HCLGE_INT_RX
 
- HCLGE_INT_TX
 
- HCLGE_INT_TYPE_M
 
- HCLGE_INT_TYPE_S
 
- HCLGE_INVALID_VPORT
 
- HCLGE_LED_LOCATE_STATE_M
 
- HCLGE_LED_LOCATE_STATE_S
 
- HCLGE_LED_NO_CHANGE
 
- HCLGE_LED_OFF
 
- HCLGE_LED_ON
 
- HCLGE_LF_NORMAL
 
- HCLGE_LF_REF_CLOCK_LOST
 
- HCLGE_LF_XSFP_ABSENT
 
- HCLGE_LF_XSFP_TX_DISABLE
 
- HCLGE_LINK_EVENT_REPORT_EN_B
 
- HCLGE_LINK_STATUS_DOWN
 
- HCLGE_LINK_STATUS_MS
 
- HCLGE_LINK_STATUS_UP
 
- HCLGE_LINK_STATUS_UP_B
 
- HCLGE_LINK_STATUS_UP_M
 
- HCLGE_LOOPBACK_TEST_FLAGS
 
- HCLGE_MAC_1588_RX_B
 
- HCLGE_MAC_1588_TX_B
 
- HCLGE_MAC_ADDR_MC
 
- HCLGE_MAC_ADDR_TYPE
 
- HCLGE_MAC_ADDR_UC
 
- HCLGE_MAC_APP_LP_B
 
- HCLGE_MAC_CFG_AN_EN
 
- HCLGE_MAC_CFG_AN_EN_B
 
- HCLGE_MAC_CFG_AN_INT_CLR_B
 
- HCLGE_MAC_CFG_AN_INT_EN_B
 
- HCLGE_MAC_CFG_AN_INT_MSK_B
 
- HCLGE_MAC_CFG_AN_RST_B
 
- HCLGE_MAC_CFG_FEC_AUTO_EN_B
 
- HCLGE_MAC_CFG_FEC_CLR_DEF_B
 
- HCLGE_MAC_CFG_FEC_MODE_M
 
- HCLGE_MAC_CFG_FEC_MODE_S
 
- HCLGE_MAC_CFG_FEC_SET_DEF_B
 
- HCLGE_MAC_CMD_NUM
 
- HCLGE_MAC_COMMON_ERR_INT_EN
 
- HCLGE_MAC_COMMON_ERR_INT_EN_MASK
 
- HCLGE_MAC_COMMON_INT_EN
 
- HCLGE_MAC_DEFAULT_FRAME
 
- HCLGE_MAC_DUPLEX
 
- HCLGE_MAC_EPORT_PFID_M
 
- HCLGE_MAC_EPORT_PFID_S
 
- HCLGE_MAC_EPORT_SW_EN_B
 
- HCLGE_MAC_EPORT_TYPE_B
 
- HCLGE_MAC_EPORT_VFID_M
 
- HCLGE_MAC_EPORT_VFID_S
 
- HCLGE_MAC_ETHERTYPE_IDX_RD
 
- HCLGE_MAC_FCS_TX_B
 
- HCLGE_MAC_FEC_BASER
 
- HCLGE_MAC_FEC_OFF
 
- HCLGE_MAC_FEC_RS
 
- HCLGE_MAC_FULL
 
- HCLGE_MAC_HALF
 
- HCLGE_MAC_LINE_LP_B
 
- HCLGE_MAC_LINK_STATUS_NUM
 
- HCLGE_MAC_MAX_FRAME
 
- HCLGE_MAC_MGR_MASK_ETHERTYPE_B
 
- HCLGE_MAC_MGR_MASK_MAC_B
 
- HCLGE_MAC_MGR_MASK_VLAN_B
 
- HCLGE_MAC_MIN_FRAME
 
- HCLGE_MAC_MODE
 
- HCLGE_MAC_PAD_RX_B
 
- HCLGE_MAC_PAD_TX_B
 
- HCLGE_MAC_RX_EN_B
 
- HCLGE_MAC_RX_FCS_B
 
- HCLGE_MAC_RX_FCS_STRIP_B
 
- HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
 
- HCLGE_MAC_SPEED
 
- HCLGE_MAC_SPEED_100G
 
- HCLGE_MAC_SPEED_100M
 
- HCLGE_MAC_SPEED_10G
 
- HCLGE_MAC_SPEED_10M
 
- HCLGE_MAC_SPEED_1G
 
- HCLGE_MAC_SPEED_25G
 
- HCLGE_MAC_SPEED_40G
 
- HCLGE_MAC_SPEED_50G
 
- HCLGE_MAC_SPEED_UNKNOWN
 
- HCLGE_MAC_STATS_FIELD_OFF
 
- HCLGE_MAC_TNL_INT_CLR
 
- HCLGE_MAC_TNL_INT_EN
 
- HCLGE_MAC_TNL_INT_EN_MASK
 
- HCLGE_MAC_TNL_LOG_SIZE
 
- HCLGE_MAC_TX_EN_B
 
- HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
 
- HCLGE_MAC_TX_UNDER_MIN_ERR_B
 
- HCLGE_MAC_UPLINK_PORT
 
- HCLGE_MAC_VLAN_ADD
 
- HCLGE_MAC_VLAN_BIT0_EN_B
 
- HCLGE_MAC_VLAN_BIT1_EN_B
 
- HCLGE_MAC_VLAN_LKUP
 
- HCLGE_MAC_VLAN_NIC_SEL
 
- HCLGE_MAC_VLAN_REMOVE
 
- HCLGE_MAC_VLAN_ROCE_SEL
 
- HCLGE_MAC_VLAN_UPDATE
 
- HCLGE_MAX_NCL_CONFIG_LENGTH
 
- HCLGE_MAX_NCL_CONFIG_OFFSET
 
- HCLGE_MAX_PF_NUM
 
- HCLGE_MAX_SYNC_COUNT
 
- HCLGE_MAX_TC_NUM
 
- HCLGE_MAX_VF_BYTES
 
- HCLGE_MBX_API_NEGOTIATE
 
- HCLGE_MBX_ASSERTING_RESET
 
- HCLGE_MBX_BIND_FUNC_QUEUE
 
- HCLGE_MBX_GET_BASE_CONFIG
 
- HCLGE_MBX_GET_BDNUM
 
- HCLGE_MBX_GET_BUFSIZE
 
- HCLGE_MBX_GET_LINK_MODE
 
- HCLGE_MBX_GET_LINK_STATUS
 
- HCLGE_MBX_GET_MAC_ADDR
 
- HCLGE_MBX_GET_MEDIA_TYPE
 
- HCLGE_MBX_GET_PORT_BASE_VLAN_STATE
 
- HCLGE_MBX_GET_QDEPTH
 
- HCLGE_MBX_GET_QID_IN_PF
 
- HCLGE_MBX_GET_QINFO
 
- HCLGE_MBX_GET_RETA
 
- HCLGE_MBX_GET_RSS_KEY
 
- HCLGE_MBX_GET_STREAMID
 
- HCLGE_MBX_GET_TCINFO
 
- HCLGE_MBX_GET_VF_FLR_STATUS
 
- HCLGE_MBX_KEEP_ALIVE
 
- HCLGE_MBX_LINK_STAT_CHANGE
 
- HCLGE_MBX_LINK_STAT_MODE
 
- HCLGE_MBX_MAC_VLAN_MC_ADD
 
- HCLGE_MBX_MAC_VLAN_MC_MODIFY
 
- HCLGE_MBX_MAC_VLAN_MC_REMOVE
 
- HCLGE_MBX_MAC_VLAN_UC_ADD
 
- HCLGE_MBX_MAC_VLAN_UC_MODIFY
 
- HCLGE_MBX_MAC_VLAN_UC_REMOVE
 
- HCLGE_MBX_MAP_RING_TO_VECTOR
 
- HCLGE_MBX_MAX_ARQ_MSG_NUM
 
- HCLGE_MBX_MAX_ARQ_MSG_SIZE
 
- HCLGE_MBX_MAX_MSG_SIZE
 
- HCLGE_MBX_MAX_RESP_DATA_SIZE
 
- HCLGE_MBX_NCSI_ERROR
 
- HCLGE_MBX_NEED_RESP_BIT
 
- HCLGE_MBX_OPCODE
 
- HCLGE_MBX_PF_VF_RESP
 
- HCLGE_MBX_PORT_BASE_VLAN_CFG
 
- HCLGE_MBX_PUSH_LINK_STATUS
 
- HCLGE_MBX_PUSH_VLAN_INFO
 
- HCLGE_MBX_QUEUE_RESET
 
- HCLGE_MBX_RESET
 
- HCLGE_MBX_RING_MAP_BASIC_MSG_NUM
 
- HCLGE_MBX_RING_NODE_VARIABLE_NUM
 
- HCLGE_MBX_SET_AESTART
 
- HCLGE_MBX_SET_ALIVE
 
- HCLGE_MBX_SET_MACVLAN
 
- HCLGE_MBX_SET_MTU
 
- HCLGE_MBX_SET_MULTICAST
 
- HCLGE_MBX_SET_PROMISC_MODE
 
- HCLGE_MBX_SET_TSOSTATS
 
- HCLGE_MBX_SET_UNICAST
 
- HCLGE_MBX_SET_VLAN
 
- HCLGE_MBX_UNMAP_RING_TO_VECTOR
 
- HCLGE_MBX_VF_MSG_DATA_NUM
 
- HCLGE_MBX_VLAN_FILTER
 
- HCLGE_MBX_VLAN_RX_OFF_CFG
 
- HCLGE_MBX_VLAN_TX_OFF_CFG
 
- HCLGE_MDIO_C22_READ
 
- HCLGE_MDIO_C22_WRITE
 
- HCLGE_MDIO_CTRL_OP_M
 
- HCLGE_MDIO_CTRL_OP_S
 
- HCLGE_MDIO_CTRL_START_B
 
- HCLGE_MDIO_CTRL_ST_M
 
- HCLGE_MDIO_CTRL_ST_S
 
- HCLGE_MDIO_PHYID_M
 
- HCLGE_MDIO_PHYID_S
 
- HCLGE_MDIO_PHYREG_M
 
- HCLGE_MDIO_PHYREG_S
 
- HCLGE_MDIO_STA_B
 
- HCLGE_MIN_RX_DESC
 
- HCLGE_MIN_TX_DESC
 
- HCLGE_MISC_RESET_STS_REG
 
- HCLGE_MISC_VECTOR_INT_STS
 
- HCLGE_MISC_VECTOR_REG_BASE
 
- HCLGE_MOD_VERSION
 
- HCLGE_MPF_ENBALE
 
- HCLGE_MPF_MSIX_INT_MIN_BD_NUM
 
- HCLGE_MPF_RAS_INT_MIN_BD_NUM
 
- HCLGE_MSIX_OFT_ROCEE_M
 
- HCLGE_MSIX_OFT_ROCEE_S
 
- HCLGE_MSIX_SRAM_ECC_ERR_INT_EN
 
- HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK
 
- HCLGE_MULTICAST
 
- HCLGE_NAME
 
- HCLGE_NCSI_ECC_INT_MASK
 
- HCLGE_NCSI_ERROR_REPORT_EN_B
 
- HCLGE_NCSI_ERR_INT_EN
 
- HCLGE_NCSI_ERR_INT_TYPE
 
- HCLGE_NCSI_INT_EN
 
- HCLGE_NETWORK_PORT_ID_M
 
- HCLGE_NETWORK_PORT_ID_S
 
- HCLGE_NIC_CMQ_DESC_NUM
 
- HCLGE_NIC_CMQ_DESC_NUM_S
 
- HCLGE_NIC_CRQ_BASEADDR_H_REG
 
- HCLGE_NIC_CRQ_BASEADDR_L_REG
 
- HCLGE_NIC_CRQ_DEPTH_REG
 
- HCLGE_NIC_CRQ_HEAD_REG
 
- HCLGE_NIC_CRQ_TAIL_REG
 
- HCLGE_NIC_CSQ_BASEADDR_H_REG
 
- HCLGE_NIC_CSQ_BASEADDR_L_REG
 
- HCLGE_NIC_CSQ_DEPTH_REG
 
- HCLGE_NIC_CSQ_HEAD_REG
 
- HCLGE_NIC_CSQ_TAIL_REG
 
- HCLGE_NIC_SW_RST_RDY
 
- HCLGE_NIC_SW_RST_RDY_B
 
- HCLGE_NON_DCB_ADDITIONAL_BUF
 
- HCLGE_OPC_ADD_RING_TO_VECTOR
 
- HCLGE_OPC_CFG_COM_TQP_QUEUE
 
- HCLGE_OPC_CFG_MAC_PARA
 
- HCLGE_OPC_CFG_MAC_PAUSE_EN
 
- HCLGE_OPC_CFG_PFC_PARA
 
- HCLGE_OPC_CFG_PFC_PAUSE_EN
 
- HCLGE_OPC_CFG_PROMISC_MODE
 
- HCLGE_OPC_CFG_RST_TRIGGER
 
- HCLGE_OPC_CFG_RX_QUEUE
 
- HCLGE_OPC_CFG_RX_QUEUE_LRO
 
- HCLGE_OPC_CFG_TX_QUEUE
 
- HCLGE_OPC_CLEAR_MAC_TNL_INT
 
- HCLGE_OPC_CONFIG_AN_MODE
 
- HCLGE_OPC_CONFIG_FEC_MODE
 
- HCLGE_OPC_CONFIG_MAC_MODE
 
- HCLGE_OPC_CONFIG_MAX_FRM_SIZE
 
- HCLGE_OPC_CONFIG_SPEED_DUP
 
- HCLGE_OPC_DEL_RING_TO_VECTOR
 
- HCLGE_OPC_DFX_BD_NUM
 
- HCLGE_OPC_DFX_BIOS_COMMON_REG
 
- HCLGE_OPC_DFX_IGU_EGU_REG
 
- HCLGE_OPC_DFX_NCSI_REG
 
- HCLGE_OPC_DFX_PPP_REG
 
- HCLGE_OPC_DFX_QUERY_CHIP_CAP
 
- HCLGE_OPC_DFX_RCB_REG
 
- HCLGE_OPC_DFX_RPU_REG_0
 
- HCLGE_OPC_DFX_RPU_REG_1
 
- HCLGE_OPC_DFX_RTC_REG
 
- HCLGE_OPC_DFX_SSU_REG_0
 
- HCLGE_OPC_DFX_SSU_REG_1
 
- HCLGE_OPC_DFX_SSU_REG_2
 
- HCLGE_OPC_DFX_TQP_REG
 
- HCLGE_OPC_ETS_TC_WEIGHT
 
- HCLGE_OPC_FD_AD_OP
 
- HCLGE_OPC_FD_GET_ALLOCATION
 
- HCLGE_OPC_FD_KEY_CONFIG
 
- HCLGE_OPC_FD_MODE_CTRL
 
- HCLGE_OPC_FD_TCAM_OP
 
- HCLGE_OPC_GBL_RST_STATUS
 
- HCLGE_OPC_GET_CFG_PARAM
 
- HCLGE_OPC_GET_SFP_INFO
 
- HCLGE_OPC_GRO_GENERIC_CONFIG
 
- HCLGE_OPC_LED_STATUS_CFG
 
- HCLGE_OPC_M7_COMPAT_CFG
 
- HCLGE_OPC_M7_STATS_BD
 
- HCLGE_OPC_M7_STATS_INFO
 
- HCLGE_OPC_MAC_ETHTYPE_ADD
 
- HCLGE_OPC_MAC_ETHTYPE_REMOVE
 
- HCLGE_OPC_MAC_TNL_INT_EN
 
- HCLGE_OPC_MAC_VLAN_ADD
 
- HCLGE_OPC_MAC_VLAN_ALLOCATE
 
- HCLGE_OPC_MAC_VLAN_INSERT
 
- HCLGE_OPC_MAC_VLAN_REMOVE
 
- HCLGE_OPC_MAC_VLAN_SWITCH_PARAM
 
- HCLGE_OPC_MAC_VLAN_TYPE_ID
 
- HCLGE_OPC_MDIO_CONFIG
 
- HCLGE_OPC_PF_RST_DONE
 
- HCLGE_OPC_PG_DFX_STS
 
- HCLGE_OPC_PORT_DFX_STS
 
- HCLGE_OPC_PPU_PF_OTHER_INT_DFX
 
- HCLGE_OPC_PRI_DFX_STS
 
- HCLGE_OPC_PRI_TO_TC_MAPPING
 
- HCLGE_OPC_QCN_AJUST_INIT
 
- HCLGE_OPC_QCN_DFX_CNT_STATUS
 
- HCLGE_OPC_QCN_GRP_TMPLT_CFG
 
- HCLGE_OPC_QCN_MOD_CFG
 
- HCLGE_OPC_QCN_QSET_LINK_CFG
 
- HCLGE_OPC_QCN_RP_STATUS_GET
 
- HCLGE_OPC_QCN_SHAPPING_BS_CFG
 
- HCLGE_OPC_QCN_SHAPPING_IR_CFG
 
- HCLGE_OPC_QOS_MAP
 
- HCLGE_OPC_QSET_DFX_STS
 
- HCLGE_OPC_QUERY_32_BIT_REG
 
- HCLGE_OPC_QUERY_64_BIT_REG
 
- HCLGE_OPC_QUERY_FUNC_STATUS
 
- HCLGE_OPC_QUERY_FW_VER
 
- HCLGE_OPC_QUERY_LINK_STATUS
 
- HCLGE_OPC_QUERY_MAC_REG_NUM
 
- HCLGE_OPC_QUERY_MAC_RX_PKT_CNT
 
- HCLGE_OPC_QUERY_MAC_TNL_INT
 
- HCLGE_OPC_QUERY_MAC_TX_PKT_CNT
 
- HCLGE_OPC_QUERY_NCL_CONFIG
 
- HCLGE_OPC_QUERY_PFC_RX_PKT_CNT
 
- HCLGE_OPC_QUERY_PFC_TX_PKT_CNT
 
- HCLGE_OPC_QUERY_PF_RSRC
 
- HCLGE_OPC_QUERY_REG_NUM
 
- HCLGE_OPC_QUERY_RX_POINTER
 
- HCLGE_OPC_QUERY_RX_STATUS
 
- HCLGE_OPC_QUERY_TX_POINTER
 
- HCLGE_OPC_QUERY_TX_STATUS
 
- HCLGE_OPC_QUERY_VF_RSRC
 
- HCLGE_OPC_QUERY_VF_RST_RDY
 
- HCLGE_OPC_RESET_TQP_QUEUE
 
- HCLGE_OPC_RSS_GENERIC_CONFIG
 
- HCLGE_OPC_RSS_INDIR_TABLE
 
- HCLGE_OPC_RSS_INPUT_TUPLE
 
- HCLGE_OPC_RSS_TC_MODE
 
- HCLGE_OPC_RX_COM_THRD_ALLOC
 
- HCLGE_OPC_RX_COM_WL_ALLOC
 
- HCLGE_OPC_RX_GBL_PKT_CNT
 
- HCLGE_OPC_RX_PRIV_BUFF_ALLOC
 
- HCLGE_OPC_RX_PRIV_WL_ALLOC
 
- HCLGE_OPC_SCH_NQ_CNT
 
- HCLGE_OPC_SCH_RQ_CNT
 
- HCLGE_OPC_SERDES_LOOPBACK
 
- HCLGE_OPC_SET_TQP_MAP
 
- HCLGE_OPC_STASH_RX_QUEUE_LRO
 
- HCLGE_OPC_STATS_32_BIT
 
- HCLGE_OPC_STATS_64_BIT
 
- HCLGE_OPC_STATS_MAC
 
- HCLGE_OPC_STATS_MAC_ALL
 
- HCLGE_OPC_TM_BP_TO_QSET_MAPPING
 
- HCLGE_OPC_TM_INTERNAL_CNT
 
- HCLGE_OPC_TM_INTERNAL_STS
 
- HCLGE_OPC_TM_INTERNAL_STS_1
 
- HCLGE_OPC_TM_NQ_TO_QS_LINK
 
- HCLGE_OPC_TM_PG_C_SHAPPING
 
- HCLGE_OPC_TM_PG_P_SHAPPING
 
- HCLGE_OPC_TM_PG_SCH_MODE_CFG
 
- HCLGE_OPC_TM_PG_TO_PRI_LINK
 
- HCLGE_OPC_TM_PG_WEIGHT
 
- HCLGE_OPC_TM_PORT_SHAPPING
 
- HCLGE_OPC_TM_PORT_WEIGHT
 
- HCLGE_OPC_TM_PRI_C_SHAPPING
 
- HCLGE_OPC_TM_PRI_P_SHAPPING
 
- HCLGE_OPC_TM_PRI_SCH_MODE_CFG
 
- HCLGE_OPC_TM_PRI_WEIGHT
 
- HCLGE_OPC_TM_QS_SCH_MODE_CFG
 
- HCLGE_OPC_TM_QS_TO_PRI_LINK
 
- HCLGE_OPC_TM_QS_WEIGHT
 
- HCLGE_OPC_TM_RQ_TO_QS_LINK
 
- HCLGE_OPC_TQP_TX_QUEUE_TC
 
- HCLGE_OPC_TSO_GENERIC_CONFIG
 
- HCLGE_OPC_TX_BUFF_ALLOC
 
- HCLGE_OPC_VLAN_FILTER_CTRL
 
- HCLGE_OPC_VLAN_FILTER_PF_CFG
 
- HCLGE_OPC_VLAN_FILTER_VF_CFG
 
- HCLGE_OPC_VLAN_PORT_RX_CFG
 
- HCLGE_OPC_VLAN_PORT_TX_CFG
 
- HCLGE_PF_CFG_BLOCK_SIZE
 
- HCLGE_PF_CFG_DESC_NUM
 
- HCLGE_PF_ID_M
 
- HCLGE_PF_ID_S
 
- HCLGE_PF_MAC_NUM_MASK
 
- HCLGE_PF_MSIX_INT_MIN_BD_NUM
 
- HCLGE_PF_OTHER_INT_REG
 
- HCLGE_PF_RAS_INT_MIN_BD_NUM
 
- HCLGE_PF_RESET_DONE_BIT
 
- HCLGE_PF_RESET_SYNC_CNT
 
- HCLGE_PF_RESET_SYNC_TIME
 
- HCLGE_PF_RST_ALL_VF_RDY_B
 
- HCLGE_PF_STATE_BOND_B
 
- HCLGE_PF_STATE_DONE
 
- HCLGE_PF_STATE_DONE_B
 
- HCLGE_PF_STATE_MAC_N_B
 
- HCLGE_PF_STATE_MAIN
 
- HCLGE_PF_STATE_MAIN_B
 
- HCLGE_PF_VEC_NUM_M
 
- HCLGE_PF_VEC_NUM_S
 
- HCLGE_PG_NUM
 
- HCLGE_PHY_CSC_REG
 
- HCLGE_PHY_CSS_REG
 
- HCLGE_PHY_LINK_STATUS_NUM
 
- HCLGE_PHY_MDIX_CTRL_M
 
- HCLGE_PHY_MDIX_CTRL_S
 
- HCLGE_PHY_MDIX_STATUS_B
 
- HCLGE_PHY_PAGE_COPPER
 
- HCLGE_PHY_PAGE_MDIX
 
- HCLGE_PHY_PAGE_REG
 
- HCLGE_PHY_SPEED_DUP_RESOLVE_B
 
- HCLGE_PORT_INS_TAG1_EN_B
 
- HCLGE_PORT_INS_TAG2_EN_B
 
- HCLGE_PORT_TYPE_B
 
- HCLGE_PPP_CMD0_INT_CMD
 
- HCLGE_PPP_CMD1_INT_CMD
 
- HCLGE_PPP_MPF_ECC_ERR_INT0_EN
 
- HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK
 
- HCLGE_PPP_MPF_ECC_ERR_INT1_EN
 
- HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK
 
- HCLGE_PPP_MPF_ECC_ERR_INT2_EN
 
- HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK
 
- HCLGE_PPP_MPF_ECC_ERR_INT3_EN
 
- HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK
 
- HCLGE_PPP_MPF_INT_ST3_MASK
 
- HCLGE_PPP_PF_ERR_INT_EN
 
- HCLGE_PPP_PF_ERR_INT_EN_MASK
 
- HCLGE_PPU_MPF_ABNORMAL_INT0_EN
 
- HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK
 
- HCLGE_PPU_MPF_ABNORMAL_INT1_EN
 
- HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK
 
- HCLGE_PPU_MPF_ABNORMAL_INT2_EN
 
- HCLGE_PPU_MPF_ABNORMAL_INT2_EN2
 
- HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK
 
- HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK
 
- HCLGE_PPU_MPF_ABNORMAL_INT3_EN
 
- HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK
 
- HCLGE_PPU_MPF_ECC_INT_CMD
 
- HCLGE_PPU_MPF_INT_ST2_MSIX_MASK
 
- HCLGE_PPU_MPF_INT_ST3_MASK
 
- HCLGE_PPU_MPF_OTHER_INT_CMD
 
- HCLGE_PPU_PF_ABNORMAL_INT_EN
 
- HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK
 
- HCLGE_PPU_PF_INT_MSIX_MASK
 
- HCLGE_PPU_PF_INT_RAS_MASK
 
- HCLGE_PPU_PF_OTHER_INT_CMD
 
- HCLGE_PPU_PF_OVER_8BD_ERR_MASK
 
- HCLGE_PROMISC_EN_ALL
 
- HCLGE_PROMISC_EN_B
 
- HCLGE_PROMISC_EN_BC
 
- HCLGE_PROMISC_EN_MC
 
- HCLGE_PROMISC_EN_UC
 
- HCLGE_PROMISC_RX_EN_B
 
- HCLGE_PROMISC_TX_EN_B
 
- HCLGE_QCN_ECC_INT_MASK
 
- HCLGE_QCN_FIFO_INT_MASK
 
- HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT
 
- HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT
 
- HCLGE_QUERY_CLEAR_MPF_RAS_INT
 
- HCLGE_QUERY_CLEAR_PF_RAS_INT
 
- HCLGE_QUERY_CLEAR_ROCEE_RAS_INT
 
- HCLGE_QUERY_MAX_CNT
 
- HCLGE_QUERY_MSIX_INT_STS_BD_NUM
 
- HCLGE_QUERY_RAS_INT_STS_BD_NUM
 
- HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD
 
- HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD
 
- HCLGE_RAS_OTHER_STS_REG
 
- HCLGE_RAS_PF_OTHER_INT_STS_REG
 
- HCLGE_RAS_REG_NFE_MASK
 
- HCLGE_RAS_REG_ROCEE_ERR_MASK
 
- HCLGE_RCB_INIT_FLAG_EN_B
 
- HCLGE_RCB_INIT_FLAG_FINI_B
 
- HCLGE_RCB_INIT_QUERY_TIMEOUT
 
- HCLGE_RD_FIRST_STATS_NUM
 
- HCLGE_RD_OTHER_STATS_NUM
 
- HCLGE_REM_TAG1_EN_B
 
- HCLGE_REM_TAG2_EN_B
 
- HCLGE_RESET_INTERVAL
 
- HCLGE_RESET_INT_M
 
- HCLGE_RESET_MAX_FAIL_CNT
 
- HCLGE_RESET_SYNC_TIME
 
- HCLGE_RESET_WAIT_CNT
 
- HCLGE_RESET_WATI_MS
 
- HCLGE_RING_EN_REG
 
- HCLGE_RING_ID_MASK
 
- HCLGE_RING_INT_REG_OFFSET
 
- HCLGE_RING_REG_OFFSET
 
- HCLGE_RING_RX_ADDR_H_REG
 
- HCLGE_RING_RX_ADDR_L_REG
 
- HCLGE_RING_RX_BD_ERR_REG
 
- HCLGE_RING_RX_BD_LENGTH_REG
 
- HCLGE_RING_RX_BD_NUM_REG
 
- HCLGE_RING_RX_FBD_NUM_REG
 
- HCLGE_RING_RX_FBD_OFFSET_REG
 
- HCLGE_RING_RX_HEAD_REG
 
- HCLGE_RING_RX_MERGE_EN_REG
 
- HCLGE_RING_RX_OFFSET_REG
 
- HCLGE_RING_RX_STASH_REG
 
- HCLGE_RING_RX_TAIL_REG
 
- HCLGE_RING_TX_ADDR_H_REG
 
- HCLGE_RING_TX_ADDR_L_REG
 
- HCLGE_RING_TX_BD_ERR_REG
 
- HCLGE_RING_TX_BD_NUM_REG
 
- HCLGE_RING_TX_EBD_NUM_REG
 
- HCLGE_RING_TX_EBD_OFFSET_REG
 
- HCLGE_RING_TX_FBD_NUM_REG
 
- HCLGE_RING_TX_HEAD_REG
 
- HCLGE_RING_TX_MERGE_EN_REG
 
- HCLGE_RING_TX_OFFSET_REG
 
- HCLGE_RING_TX_PRIORITY_REG
 
- HCLGE_RING_TX_TAIL_REG
 
- HCLGE_RING_TX_TC_REG
 
- HCLGE_ROCEE_AXI_ERR_INT_MASK
 
- HCLGE_ROCEE_BERR_INT_MASK
 
- HCLGE_ROCEE_ECC_INT_MASK
 
- HCLGE_ROCEE_OVF_ERR_INT_MASK
 
- HCLGE_ROCEE_OVF_ERR_TYPE_MASK
 
- HCLGE_ROCEE_OVF_INT_MASK
 
- HCLGE_ROCEE_PF_RAS_INT_CMD
 
- HCLGE_ROCEE_RAS_CE_INT_EN
 
- HCLGE_ROCEE_RAS_CE_INT_EN_MASK
 
- HCLGE_ROCEE_RAS_NFE_INT_EN
 
- HCLGE_ROCEE_RAS_NFE_INT_EN_MASK
 
- HCLGE_ROCEE_RERR_INT_MASK
 
- HCLGE_RSS_CFG_TBL_NUM
 
- HCLGE_RSS_CFG_TBL_SIZE
 
- HCLGE_RSS_DEFAULT_OUTPORT_B
 
- HCLGE_RSS_HASH_ALGO_MASK
 
- HCLGE_RSS_HASH_ALGO_SIMPLE
 
- HCLGE_RSS_HASH_ALGO_SYMMETRIC
 
- HCLGE_RSS_HASH_ALGO_TOEPLITZ
 
- HCLGE_RSS_HASH_KEY_NUM
 
- HCLGE_RSS_HASH_KEY_OFFSET_B
 
- HCLGE_RSS_IND_TBL_SIZE
 
- HCLGE_RSS_INPUT_TUPLE_OTHER
 
- HCLGE_RSS_INPUT_TUPLE_SCTP
 
- HCLGE_RSS_KEY_SIZE
 
- HCLGE_RSS_MBX_RESP_LEN
 
- HCLGE_RSS_SET_BITMAP_MSK
 
- HCLGE_RSS_TC_OFFSET_M
 
- HCLGE_RSS_TC_OFFSET_S
 
- HCLGE_RSS_TC_SIZE_0
 
- HCLGE_RSS_TC_SIZE_1
 
- HCLGE_RSS_TC_SIZE_2
 
- HCLGE_RSS_TC_SIZE_3
 
- HCLGE_RSS_TC_SIZE_4
 
- HCLGE_RSS_TC_SIZE_5
 
- HCLGE_RSS_TC_SIZE_6
 
- HCLGE_RSS_TC_SIZE_7
 
- HCLGE_RSS_TC_SIZE_M
 
- HCLGE_RSS_TC_SIZE_S
 
- HCLGE_RSS_TC_VALID_B
 
- HCLGE_RX_COM_WL_EN_B
 
- HCLGE_RX_MAC_PAUSE_EN_MSK
 
- HCLGE_RX_PKT_EN_B
 
- HCLGE_RX_PRIV_EN_B
 
- HCLGE_SCH_MODE_DWRR
 
- HCLGE_SCH_MODE_SP
 
- HCLGE_SEND_SYNC
 
- HCLGE_SERDES_RETRY_MS
 
- HCLGE_SERDES_RETRY_NUM
 
- HCLGE_SHAPER_BS_S_DEF
 
- HCLGE_SHAPER_BS_U_DEF
 
- HCLGE_SHAPER_LVL_CNT
 
- HCLGE_SHAPER_LVL_PF
 
- HCLGE_SHAPER_LVL_PG
 
- HCLGE_SHAPER_LVL_PORT
 
- HCLGE_SHAPER_LVL_PRI
 
- HCLGE_SHAPER_LVL_QSET
 
- HCLGE_SHAPER_LVL_VF
 
- HCLGE_SHOW_TAG1_EN_B
 
- HCLGE_SHOW_TAG2_EN_B
 
- HCLGE_SSU_1BIT_ECC_ERR_INT_EN
 
- HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK
 
- HCLGE_SSU_BIT32_ECC_ERR_INT_EN
 
- HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK
 
- HCLGE_SSU_COMMON_ERR_INT_MASK
 
- HCLGE_SSU_COMMON_INT_CMD
 
- HCLGE_SSU_COMMON_INT_EN
 
- HCLGE_SSU_COMMON_INT_EN_MASK
 
- HCLGE_SSU_ECC_INT_CMD
 
- HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN
 
- HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK
 
- HCLGE_SSU_MEM_ECC_ERR
 
- HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN
 
- HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK
 
- HCLGE_SSU_PORT_BASED_ERR_INT_EN
 
- HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK
 
- HCLGE_SSU_PORT_INT_MSIX_MASK
 
- HCLGE_STATE_CMD_DISABLE
 
- HCLGE_STATE_DISABLED
 
- HCLGE_STATE_DOWN
 
- HCLGE_STATE_MAX
 
- HCLGE_STATE_MBX_HANDLING
 
- HCLGE_STATE_MBX_SERVICE_SCHED
 
- HCLGE_STATE_NIC_REGISTERED
 
- HCLGE_STATE_REINITING
 
- HCLGE_STATE_REMOVING
 
- HCLGE_STATE_ROCE_REGISTERED
 
- HCLGE_STATE_RST_HANDLING
 
- HCLGE_STATE_RST_SERVICE_SCHED
 
- HCLGE_STATE_SERVICE_INITED
 
- HCLGE_STATE_SERVICE_SCHED
 
- HCLGE_STATE_STATISTICS_UPDATING
 
- HCLGE_STATS_READ
 
- HCLGE_STATS_TIMER_INTERVAL
 
- HCLGE_STATUS_SUCCESS
 
- HCLGE_SUPPORTED
 
- HCLGE_SUPPORT_100G_BIT
 
- HCLGE_SUPPORT_100M_BIT
 
- HCLGE_SUPPORT_10G_BIT
 
- HCLGE_SUPPORT_10M_BIT
 
- HCLGE_SUPPORT_1G_BIT
 
- HCLGE_SUPPORT_25G_BIT
 
- HCLGE_SUPPORT_40G_BIT
 
- HCLGE_SUPPORT_50G_BIT
 
- HCLGE_SUPPORT_GE
 
- HCLGE_SWITCH_ALW_DST_OVRD_B
 
- HCLGE_SWITCH_ALW_LCL_LPBK_B
 
- HCLGE_SWITCH_ALW_LCL_LPBK_MASK
 
- HCLGE_SWITCH_ALW_LPBK_B
 
- HCLGE_SWITCH_ALW_LPBK_MASK
 
- HCLGE_SWITCH_ANTI_SPOOF_B
 
- HCLGE_SWITCH_ANTI_SPOOF_MASK
 
- HCLGE_SWITCH_LW_DST_OVRD_MASK
 
- HCLGE_SWITCH_NO_MASK
 
- HCLGE_S_IP_BIT
 
- HCLGE_S_PORT_BIT
 
- HCLGE_TC0_PRI_BUF_EN_B
 
- HCLGE_TC_NUM_ONE_DESC
 
- HCLGE_TM_PFC_NUM_GET_PER_CMD
 
- HCLGE_TM_PFC_PKT_GET_CMD_NUM
 
- HCLGE_TM_PORT_BASE_MODE_MSK
 
- HCLGE_TM_QCN_MEM_ERR_INT_EN
 
- HCLGE_TM_QCN_MEM_INT_CFG
 
- HCLGE_TM_QS_PRI_LINK_VLD_MSK
 
- HCLGE_TM_Q_QS_LINK_VLD_MSK
 
- HCLGE_TM_SCH_ECC_ERR_INT_EN
 
- HCLGE_TM_SCH_ECC_INT_EN
 
- HCLGE_TM_SHAP_BS_B_LSH
 
- HCLGE_TM_SHAP_BS_B_MSK
 
- HCLGE_TM_SHAP_BS_S_LSH
 
- HCLGE_TM_SHAP_BS_S_MSK
 
- HCLGE_TM_SHAP_C_BUCKET
 
- HCLGE_TM_SHAP_IR_B_LSH
 
- HCLGE_TM_SHAP_IR_B_MSK
 
- HCLGE_TM_SHAP_IR_S_LSH
 
- HCLGE_TM_SHAP_IR_S_MSK
 
- HCLGE_TM_SHAP_IR_U_LSH
 
- HCLGE_TM_SHAP_IR_U_MSK
 
- HCLGE_TM_SHAP_P_BUCKET
 
- HCLGE_TM_TX_SCHD_DWRR_MSK
 
- HCLGE_TM_TX_SCHD_SP_MSK
 
- HCLGE_TOTAL_PKT_BUF
 
- HCLGE_TQPS_DEPTH_INFO_LEN
 
- HCLGE_TQPS_RSS_INFO_LEN
 
- HCLGE_TQP_ECC_ERR_INT_EN
 
- HCLGE_TQP_ECC_ERR_INT_EN_MASK
 
- HCLGE_TQP_ENABLE_B
 
- HCLGE_TQP_ID_M
 
- HCLGE_TQP_ID_S
 
- HCLGE_TQP_INTR_CTRL_REG
 
- HCLGE_TQP_INTR_GL0_REG
 
- HCLGE_TQP_INTR_GL1_REG
 
- HCLGE_TQP_INTR_GL2_REG
 
- HCLGE_TQP_INTR_RL_REG
 
- HCLGE_TQP_MAP_EN_B
 
- HCLGE_TQP_MAP_TYPE_B
 
- HCLGE_TQP_MAP_TYPE_PF
 
- HCLGE_TQP_MAP_TYPE_VF
 
- HCLGE_TQP_REG_OFFSET
 
- HCLGE_TQP_REG_SIZE
 
- HCLGE_TQP_RESET_B
 
- HCLGE_TQP_RESET_TRY_TIMES
 
- HCLGE_TSO_MSS_MAX
 
- HCLGE_TSO_MSS_MAX_M
 
- HCLGE_TSO_MSS_MAX_S
 
- HCLGE_TSO_MSS_MIN
 
- HCLGE_TSO_MSS_MIN_M
 
- HCLGE_TSO_MSS_MIN_S
 
- HCLGE_TX_MAC_PAUSE_EN_MSK
 
- HCLGE_TYPE_CRQ
 
- HCLGE_TYPE_CSQ
 
- HCLGE_UMV_SPC_ALC_B
 
- HCLGE_UMV_TBL_SIZE
 
- HCLGE_UNICAST
 
- HCLGE_VECTOR0_CMDQ_SRC_REG
 
- HCLGE_VECTOR0_CORERESET_INT_B
 
- HCLGE_VECTOR0_EVENT_ERR
 
- HCLGE_VECTOR0_EVENT_MBX
 
- HCLGE_VECTOR0_EVENT_OTHER
 
- HCLGE_VECTOR0_EVENT_RST
 
- HCLGE_VECTOR0_GLOBALRESET_INT_B
 
- HCLGE_VECTOR0_IMPRESET_INT_B
 
- HCLGE_VECTOR0_IMP_CMDQ_ERR_B
 
- HCLGE_VECTOR0_IMP_RD_POISON_B
 
- HCLGE_VECTOR0_IMP_RESET_INT_B
 
- HCLGE_VECTOR0_OTER_EN_REG
 
- HCLGE_VECTOR0_PF_OTHER_INT_STS_REG
 
- HCLGE_VECTOR0_REG_MSIX_MASK
 
- HCLGE_VECTOR0_RX_CMDQ_INT_B
 
- HCLGE_VECTOR_ELEMENTS_PER_CMD
 
- HCLGE_VECTOR_REG_BASE
 
- HCLGE_VECTOR_REG_OFFSET
 
- HCLGE_VECTOR_VF_OFFSET
 
- HCLGE_VF_ID_M
 
- HCLGE_VF_ID_S
 
- HCLGE_VF_NUM_IN_FIRST_DESC
 
- HCLGE_VF_NUM_PER_BYTE
 
- HCLGE_VF_NUM_PER_CMD
 
- HCLGE_VF_VLAN_DEL_NO_FOUND
 
- HCLGE_VF_VLAN_NO_ENTRY
 
- HCLGE_VPORT_NUM
 
- HCLGE_VPORT_STATE
 
- HCLGE_VPORT_STATE_ALIVE
 
- HCLGE_VPORT_STATE_MAX
 
- HCLGE_V_TAG_BIT
 
- HCLGE_WAIT_RESET_DONE
 
- HCLK
 
- HCLKCON
 
- HCLKX2
 
- HCLK_2D
 
- HCLK_3DSE
 
- HCLK_AHB1TOM
 
- HCLK_AUDIO
 
- HCLK_BUS
 
- HCLK_BUS_PRE
 
- HCLK_CAM
 
- HCLK_CAMIF
 
- HCLK_CFC
 
- HCLK_CIF
 
- HCLK_CIF0
 
- HCLK_CIF1
 
- HCLK_CIF2
 
- HCLK_CIF3
 
- HCLK_CM0S_PMU
 
- HCLK_CPU
 
- HCLK_CRYPTO
 
- HCLK_CRYPTO_MST
 
- HCLK_CRYPTO_SLV
 
- HCLK_DDR0
 
- HCLK_DDR1
 
- HCLK_DHOST
 
- HCLK_DMA0
 
- HCLK_DMA1
 
- HCLK_DMA2
 
- HCLK_DMA3
 
- HCLK_DMA4
 
- HCLK_DMA5
 
- HCLK_DMA6
 
- HCLK_DMA7
 
- HCLK_DRAM
 
- HCLK_EBC
 
- HCLK_EMAC
 
- HCLK_EMMC
 
- HCLK_GATE
 
- HCLK_GMAC
 
- HCLK_GPS
 
- HCLK_H264
 
- HCLK_HALF
 
- HCLK_HDCP
 
- HCLK_HDCP22
 
- HCLK_HDCP_MMU
 
- HCLK_HDCP_NOC
 
- HCLK_HDMI
 
- HCLK_HEVC
 
- HCLK_HOST
 
- HCLK_HOST0
 
- HCLK_HOST0_ARB
 
- HCLK_HOST1
 
- HCLK_HOST1_ARB
 
- HCLK_HOST2
 
- HCLK_HOST_ARB
 
- HCLK_HSADC
 
- HCLK_HSIC
 
- HCLK_HSMMC0
 
- HCLK_HSMMC1
 
- HCLK_HSMMC2
 
- HCLK_I2S
 
- HCLK_I2S0
 
- HCLK_I2S0_2CH
 
- HCLK_I2S0_8CH
 
- HCLK_I2S1
 
- HCLK_I2S1_2CH
 
- HCLK_I2S1_8CH
 
- HCLK_I2S2
 
- HCLK_I2S2_2CH
 
- HCLK_I2S2_8CH
 
- HCLK_I2S3_8CH
 
- HCLK_I2S_2CH
 
- HCLK_I2S_8CH
 
- HCLK_IEP
 
- HCLK_IEP_NOC
 
- HCLK_IHOST
 
- HCLK_INTC
 
- HCLK_IPP
 
- HCLK_IROM
 
- HCLK_ISP
 
- HCLK_ISP0
 
- HCLK_ISP0_NOC
 
- HCLK_ISP0_WRAPPER
 
- HCLK_ISP1
 
- HCLK_ISP1_NOC
 
- HCLK_ISP1_WRAPPER
 
- HCLK_JPEG
 
- HCLK_LCD
 
- HCLK_LCDC
 
- HCLK_LCDC0
 
- HCLK_LCDC1
 
- HCLK_M0_PERILP
 
- HCLK_M0_PERILP_NOC
 
- HCLK_MAC
 
- HCLK_MDP
 
- HCLK_MEM0
 
- HCLK_MEM1
 
- HCLK_MFC
 
- HCLK_MMC_NAND
 
- HCLK_M_CRYPTO
 
- HCLK_M_CRYPTO0
 
- HCLK_M_CRYPTO1
 
- HCLK_NAND
 
- HCLK_NANDC
 
- HCLK_NANDC0
 
- HCLK_NANDC1
 
- HCLK_NOC_PMU
 
- HCLK_OTG
 
- HCLK_OTG0
 
- HCLK_OTG1
 
- HCLK_OTG_PMU
 
- HCLK_PDM
 
- HCLK_PERI
 
- HCLK_PERIHP
 
- HCLK_PERILP0
 
- HCLK_PERILP0_NOC
 
- HCLK_PERILP1
 
- HCLK_PERILP1_NOC
 
- HCLK_PERI_PRE
 
- HCLK_PIDF
 
- HCLK_POST0
 
- HCLK_RATIO_MASK
 
- HCLK_RATIO_SHIFT
 
- HCLK_RGA
 
- HCLK_RGA_NOC
 
- HCLK_RKVDEC
 
- HCLK_RKVDEC_PRE
 
- HCLK_RKVENC
 
- HCLK_ROM
 
- HCLK_ROT
 
- HCLK_SCALER
 
- HCLK_SD
 
- HCLK_SDIO
 
- HCLK_SDIO0
 
- HCLK_SDIO1
 
- HCLK_SDIOAUDIO_NOC
 
- HCLK_SDIO_NOC
 
- HCLK_SDMA0
 
- HCLK_SDMA1
 
- HCLK_SDMMC
 
- HCLK_SDMMC_EXT
 
- HCLK_SDMMC_NOC
 
- HCLK_SDRAM
 
- HCLK_SECUR
 
- HCLK_SFC
 
- HCLK_SPDIF
 
- HCLK_SPDIF8CH
 
- HCLK_SPDIFRX
 
- HCLK_SPDIFTX
 
- HCLK_SPDIF_8CH
 
- HCLK_SSMC
 
- HCLK_S_CRYPTO
 
- HCLK_S_CRYPTO0
 
- HCLK_S_CRYPTO1
 
- HCLK_TSP
 
- HCLK_TV
 
- HCLK_TZIC
 
- HCLK_UHOST
 
- HCLK_USB
 
- HCLK_USBD
 
- HCLK_USBH
 
- HCLK_USBHOST
 
- HCLK_USBHOST0
 
- HCLK_USBHOST1
 
- HCLK_VAD
 
- HCLK_VCODEC
 
- HCLK_VCODEC_NOC
 
- HCLK_VDPU
 
- HCLK_VDU
 
- HCLK_VDU_NOC
 
- HCLK_VEPU
 
- HCLK_VIDEO
 
- HCLK_VIO
 
- HCLK_VIO2_H2P
 
- HCLK_VIO_AHB_ARBI
 
- HCLK_VIO_BUS
 
- HCLK_VIO_H2P
 
- HCLK_VIO_HDCPMMU
 
- HCLK_VIO_NIU
 
- HCLK_VIO_NOC
 
- HCLK_VIO_PRE
 
- HCLK_VIP
 
- HCLK_VI_PRE
 
- HCLK_VOP
 
- HCLK_VOP0
 
- HCLK_VOP0_NOC
 
- HCLK_VOP1
 
- HCLK_VOP1_NOC
 
- HCLK_VOPB
 
- HCLK_VOPL
 
- HCLK_VO_PRE
 
- HCLK_VPU
 
- HCLK_VPU_PRE
 
- HCLK_X2
 
- HCLOCK
 
- HCLSTHRESH
 
- HCMD
 
- HCMD_ARR
 
- HCMD_CHANGE_PHY_STATE
 
- HCMD_INTERFACE_TEST
 
- HCMD_LOAD_CONFIG_DATA
 
- HCMD_MISC
 
- HCMD_MISC_GRANT_LCB_ACCESS
 
- HCMD_MISC_REQUEST_LCB_ACCESS
 
- HCMD_NAME
 
- HCMD_READ_CONFIG_DATA
 
- HCMD_READ_LCB_CSR
 
- HCMD_READ_LCB_IDLE_MSG
 
- HCMD_SEND_LCB_IDLE_MSG
 
- HCMD_SUCCESS
 
- HCMD_WRITE_LCB_CSR
 
- HCMODE
 
- HCNT
 
- HCNTPERR_F
 
- HCNTPERR_S
 
- HCNTPERR_V
 
- HCONTROL
 
- HCONTROL_COPYOUT_STATFIS
 
- HCONTROL_DPATH_PARITY
 
- HCONTROL_FORCE_OFFLINE
 
- HCONTROL_LEGACY
 
- HCONTROL_ONLINE_PHY_RST
 
- HCONTROL_PARITY_PROT_MOD
 
- HCONTROL_PMP_ATTACHED
 
- HCONTROL_SNOOP_ENABLE
 
- HCOP_FC_AES
 
- HCOP_FC_AES_HMAC
 
- HCOP_FC_SHA
 
- HCOUNTER
 
- HCPOS
 
- HCPOS_CURBLINK
 
- HCPOS_SWITCHSRC
 
- HCPOS_XSTART
 
- HCPOS_YSTART
 
- HCPTR
 
- HCPTR_TASE
 
- HCPTR_TCP
 
- HCPTR_TCPAC
 
- HCPTR_TCP_MASK
 
- HCPTR_TTA
 
- HCP_HEADER
 
- HCP_MSG_GET_CMD
 
- HCP_MSG_GET_TYPE
 
- HCR
 
- HCRC
 
- HCRDITL0LEN
 
- HCRDITL1LEN
 
- HCREVISION
 
- HCRHDESCA
 
- HCRHDESCB
 
- HCRHPORT1
 
- HCRHPORT2
 
- HCRHPORT_CLRMASK
 
- HCRHSTATUS
 
- HCRX_SETUP_RAMDAC
 
- HCR_AMO
 
- HCR_API
 
- HCR_APK
 
- HCR_BSU
 
- HCR_BSU_IS
 
- HCR_CD
 
- HCR_DC
 
- HCR_DETECT_HDP
 
- HCR_E2H
 
- HCR_ENABLE_AUDIO
 
- HCR_ENABLE_HDCP
 
- HCR_ENABLE_PIXEL
 
- HCR_ENABLE_TMDS
 
- HCR_E_BIT
 
- HCR_FB
 
- HCR_FMO
 
- HCR_FWB
 
- HCR_GO_BIT
 
- HCR_GUEST_FLAGS
 
- HCR_GUEST_MASK
 
- HCR_HCD
 
- HCR_HOST_NVHE_FLAGS
 
- HCR_HOST_VHE_FLAGS
 
- HCR_H_WAIT_1
 
- HCR_H_WAIT_2
 
- HCR_H_WIDTH
 
- HCR_ID
 
- HCR_IDLE
 
- HCR_IMO
 
- HCR_IN_MODIFIER_OFFSET
 
- HCR_IN_PARAM_OFFSET
 
- HCR_MEM16
 
- HCR_OPMOD_SHIFT
 
- HCR_OUT_PARAM_OFFSET
 
- HCR_PTW
 
- HCR_RUN
 
- HCR_RW
 
- HCR_RW_SHIFT
 
- HCR_STATUS_OFFSET
 
- HCR_SWIO
 
- HCR_TAC
 
- HCR_TDZ
 
- HCR_TEA
 
- HCR_TERR
 
- HCR_TGE
 
- HCR_TID0
 
- HCR_TID1
 
- HCR_TID2
 
- HCR_TID3
 
- HCR_TIDCP
 
- HCR_TLOR
 
- HCR_TOKEN_OFFSET
 
- HCR_TPC
 
- HCR_TPU
 
- HCR_TRVM
 
- HCR_TSC
 
- HCR_TSW
 
- HCR_TTLB
 
- HCR_TVM
 
- HCR_TWE
 
- HCR_TWI
 
- HCR_T_BIT
 
- HCR_VA
 
- HCR_VF
 
- HCR_VI
 
- HCR_VIRT_EXCP_MASK
 
- HCR_VM
 
- HCR_VSE
 
- HCSCRATCH
 
- HCSIZE
 
- HCSIZE_BLEND_CUR
 
- HCSIZE_BLEND_GFX
 
- HCSIZE_BLEND_POS
 
- HCSIZE_BLEND_VID
 
- HCSIZE_CHEIGHT
 
- HCSIZE_CWIDTH
 
- HCSPARAMS_PPC
 
- HCSPLT
 
- HCSPLT_COMPSPLT
 
- HCSPLT_HUBADDR_MASK
 
- HCSPLT_HUBADDR_SHIFT
 
- HCSPLT_PRTADDR_MASK
 
- HCSPLT_PRTADDR_SHIFT
 
- HCSPLT_SPLTENA
 
- HCSPLT_XACTPOS_ALL
 
- HCSPLT_XACTPOS_BEGIN
 
- HCSPLT_XACTPOS_END
 
- HCSPLT_XACTPOS_MASK
 
- HCSPLT_XACTPOS_MID
 
- HCSPLT_XACTPOS_SHIFT
 
- HCSWRES
 
- HCSWRES_MAGIC
 
- HCS_AF_DISABLE_ADPT
 
- HCS_AF_DISABLE_RESET
 
- HCS_AF_IGNORE
 
- HCS_DEBUG_PORT
 
- HCS_ERST_MAX
 
- HCS_INDICATOR
 
- HCS_INTR_CLEAR
 
- HCS_INTR_OFFSET
 
- HCS_IST
 
- HCS_MAX_INTRS
 
- HCS_MAX_PORTS
 
- HCS_MAX_SCRATCHPAD
 
- HCS_MAX_SLOTS
 
- HCS_N_CC
 
- HCS_N_PCC
 
- HCS_N_PORTS
 
- HCS_OFFSET_128K
 
- HCS_PORTROUTED
 
- HCS_PPC
 
- HCS_READ_SERDES
 
- HCS_SLOTS_MASK
 
- HCS_U1_LATENCY
 
- HCS_U2_LATENCY
 
- HCS_WRITE_SERDES
 
- HCTL_EN_BIT
 
- HCTL_FTHD0
 
- HCTL_FTHD1
 
- HCTL_IRQOFF
 
- HCTL_KNOWN_BITS
 
- HCTL_LEDEN
 
- HCTL_PWRDWN
 
- HCTL_RPGSEL
 
- HCTL_SDBP
 
- HCTL_SDVS_18
 
- HCTL_SDVS_30
 
- HCTL_SDVS_33
 
- HCTL_SDVS_MASK
 
- HCTL_SDVS_SHIFT
 
- HCTL_SOFTRST
 
- HCTS0_A_MARK
 
- HCTS0_B_MARK
 
- HCTS0_C_MARK
 
- HCTS0_D_MARK
 
- HCTS0_MARK
 
- HCTS0_N_B_MARK
 
- HCTS0_N_C_MARK
 
- HCTS0_N_D_MARK
 
- HCTS0_N_E_MARK
 
- HCTS0_N_F_MARK
 
- HCTS0_N_MARK
 
- HCTS1_A_MARK
 
- HCTS1_B_MARK
 
- HCTS1_MARK
 
- HCTS1_N_A_MARK
 
- HCTS1_N_B_MARK
 
- HCTS1_N_C_MARK
 
- HCTS1_N_E_MARK
 
- HCTS1_N_MARK
 
- HCTS2_N_B_MARK
 
- HCTS2_N_MARK
 
- HCTSIZ
 
- HCTX_FLAG_NAME
 
- HCTX_MAX_TYPES
 
- HCTX_STATE_NAME
 
- HCTX_TYPE_DEFAULT
 
- HCTX_TYPE_POLL
 
- HCTX_TYPE_READ
 
- HCU_CCSR
 
- HCU_CCSR_AHB_RST
 
- HCU_CCSR_ASF_HALTED
 
- HCU_CCSR_ASF_RESET
 
- HCU_CCSR_ASF_RUNNING
 
- HCU_CCSR_CLR_IRQ_HOST
 
- HCU_CCSR_CPU_CLK_DIVIDE_BASE
 
- HCU_CCSR_CPU_CLK_DIVIDE_MSK
 
- HCU_CCSR_CPU_RST_MODE
 
- HCU_CCSR_CPU_SLEEP
 
- HCU_CCSR_CS_TO
 
- HCU_CCSR_OS_PRSNT
 
- HCU_CCSR_SET_IRQ_HCU
 
- HCU_CCSR_SET_SYNC_CPU
 
- HCU_CCSR_SMBALERT_MONITOR
 
- HCU_CCSR_UC_STATE_BASE
 
- HCU_CCSR_UC_STATE_MSK
 
- HCU_CCSR_WDOG
 
- HCU_HCSR
 
- HCU_HCSR_CLR_IRQ_HCU
 
- HCU_HCSR_SET_IRQ_CPU
 
- HCU_HCSR_SET_IRQ_HOST
 
- HCU_MAP_BASE
 
- HCXFERCTR
 
- HC_ACMD_H1
 
- HC_ACMD_H1IO_MASK
 
- HC_ACMD_H2
 
- HC_ACMD_H2IO1_MASK
 
- HC_ACMD_H2IO1_SHIFT
 
- HC_ACMD_H2IO2_MASK
 
- HC_ACMD_H2IO2_SHIFT
 
- HC_ACMD_H3
 
- HC_ACMD_H3COUNT_MASK
 
- HC_ACMD_H3COUNT_SHIFT
 
- HC_ACMD_H3IO_MASK
 
- HC_ACMD_H4
 
- HC_ACMD_H4COUNT_MASK
 
- HC_ACMD_H4COUNT_SHIFT
 
- HC_ACMD_H4ID_MASK
 
- HC_ACMD_HCmdA
 
- HC_ACMD_HCmdB
 
- HC_ACMD_HCmdC
 
- HC_ACMD_MASK
 
- HC_ACMD_SUB_MASK
 
- HC_ACTION_HOST_CONTROL_POWERCYCLE
 
- HC_ACTION_HOST_CONTROL_POWEROFF
 
- HC_ACTION_NONE
 
- HC_ASSOCIATE
 
- HC_ATL_INT
 
- HC_ATL_IRQ_MASK_AND_REG
 
- HC_ATL_IRQ_MASK_OR_REG
 
- HC_ATL_PTD_DONEMAP_REG
 
- HC_ATL_PTD_LASTPTD_REG
 
- HC_ATL_PTD_SKIPMAP_REG
 
- HC_BUFFER_STATUS_REG
 
- HC_CAPLENGTH
 
- HC_CFG
 
- HC_CFG_BIG_ENDIAN
 
- HC_CFG_CLK_PH_EN
 
- HC_CFG_CLK_POL_INV
 
- HC_CFG_DATA_PASS
 
- HC_CFG_DUAL_SLAVE
 
- HC_CFG_IDLE_SIO_LVL
 
- HC_CFG_IF_CFG
 
- HC_CFG_INDIVIDUAL
 
- HC_CFG_MAN_CS_ASSERT
 
- HC_CFG_MAN_CS_EN
 
- HC_CFG_MAN_START
 
- HC_CFG_MAN_START_EN
 
- HC_CFG_NIO
 
- HC_CFG_SLV_ACT
 
- HC_CFG_TYPE
 
- HC_CFG_TYPE_RAW_NAND
 
- HC_CFG_TYPE_SPI_NAND
 
- HC_CFG_TYPE_SPI_NOR
 
- HC_CFG_TYPE_SPI_RAM
 
- HC_CHIP_ID_REG
 
- HC_CLR_HOST_INT
 
- HC_CLR_RISC_INT
 
- HC_CMD_REG
 
- HC_COAL_IRQ
 
- HC_CONFIGFLAG
 
- HC_CONFIG_0_REG_ATTN_BIT_EN_0
 
- HC_CONFIG_0_REG_BLOCK_DISABLE_0
 
- HC_CONFIG_0_REG_INT_LINE_EN_0
 
- HC_CONFIG_0_REG_MSI_ATTN_EN_0
 
- HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
 
- HC_CONFIG_0_REG_SINGLE_ISR_EN_0
 
- HC_CONFIG_1_REG_BLOCK_DISABLE_1
 
- HC_DEFAULT_SEGMENT
 
- HC_DIAG_REG
 
- HC_DISABLE_BIOS
 
- HC_DISASSOCIATE
 
- HC_DISASSOC_QUIET
 
- HC_DUMMY
 
- HC_EN
 
- HC_EN_BIT
 
- HC_EOT_INT
 
- HC_ERINT_ENA
 
- HC_FRINDEX
 
- HC_FogDenst_MASK
 
- HC_FogEndL_MASK
 
- HC_FogEq_MASK
 
- HC_FogLF_MASK
 
- HC_FogMD_Exponential2Fog
 
- HC_FogMD_ExponentialFog
 
- HC_FogMD_LinearFog
 
- HC_FogMD_LocalFog
 
- HC_FogMD_MASK
 
- HC_H2nd1VT_MASK
 
- HC_HABFM_MASK
 
- HC_HABLAa_0
 
- HC_HABLAa_A_MASK
 
- HC_HABLAa_Adst
 
- HC_HABLAa_Asrc
 
- HC_HABLAa_Fog
 
- HC_HABLAa_HABLRA
 
- HC_HABLAa_InvOPA
 
- HC_HABLAa_MASK
 
- HC_HABLAa_OPA
 
- HC_HABLAa_OPA_MASK
 
- HC_HABLAa_OPAp5
 
- HC_HABLAa_maxAsrcAdst
 
- HC_HABLAa_maxAsrcFog
 
- HC_HABLAa_minAsrcAdst
 
- HC_HABLAa_minAsrcFog
 
- HC_HABLAb_0
 
- HC_HABLAb_Adst
 
- HC_HABLAb_Asrc
 
- HC_HABLAb_Fog
 
- HC_HABLAb_HABLRA
 
- HC_HABLAb_InvOPA
 
- HC_HABLAb_MASK
 
- HC_HABLAb_OPA
 
- HC_HABLAb_OPA_MASK
 
- HC_HABLAb_OPAp5
 
- HC_HABLAb_maxAsrcAdst
 
- HC_HABLAb_maxAsrcFog
 
- HC_HABLAb_minAsrcAdst
 
- HC_HABLAb_minAsrcFog
 
- HC_HABLAbias_A_MASK
 
- HC_HABLAbias_Aaa
 
- HC_HABLAbias_Adst
 
- HC_HABLAbias_Asrc
 
- HC_HABLAbias_Fog
 
- HC_HABLAbias_HABLRAbias
 
- HC_HABLAbias_MASK
 
- HC_HABLAbias_OPA_MASK
 
- HC_HABLAop_MASK
 
- HC_HABLAsat_MASK
 
- HC_HABLAshift_MASK
 
- HC_HABLCa_Adst
 
- HC_HABLCa_Asrc
 
- HC_HABLCa_C_MASK
 
- HC_HABLCa_Cdst
 
- HC_HABLCa_Csrc
 
- HC_HABLCa_Fog
 
- HC_HABLCa_HABLRCa
 
- HC_HABLCa_InvOPC
 
- HC_HABLCa_MASK
 
- HC_HABLCa_OPC
 
- HC_HABLCa_OPC_MASK
 
- HC_HABLCa_OPCp5
 
- HC_HABLCa_maxSrcDst
 
- HC_HABLCa_minSrcDst
 
- HC_HABLCb_Adst
 
- HC_HABLCb_Asrc
 
- HC_HABLCb_C_MASK
 
- HC_HABLCb_Cdst
 
- HC_HABLCb_Csrc
 
- HC_HABLCb_Fog
 
- HC_HABLCb_HABLRCa
 
- HC_HABLCb_InvOPC
 
- HC_HABLCb_MASK
 
- HC_HABLCb_OPC
 
- HC_HABLCb_OPC_MASK
 
- HC_HABLCb_OPCp5
 
- HC_HABLCb_maxSrcDst
 
- HC_HABLCb_minSrcDst
 
- HC_HABLCbias_Adst
 
- HC_HABLCbias_Asrc
 
- HC_HABLCbias_C_MASK
 
- HC_HABLCbias_Cin
 
- HC_HABLCbias_Fog
 
- HC_HABLCbias_HABLRCbias
 
- HC_HABLCbias_MASK
 
- HC_HABLCbias_OPC_MASK
 
- HC_HABLCop_MASK
 
- HC_HABLCsat_MASK
 
- HC_HABLCshift_MASK
 
- HC_HABLFAa_0
 
- HC_HABLFAa_A_MASK
 
- HC_HABLFAa_Adst
 
- HC_HABLFAa_Asrc
 
- HC_HABLFAa_Fog
 
- HC_HABLFAa_HABLFRA
 
- HC_HABLFAa_InvOPA
 
- HC_HABLFAa_MASK
 
- HC_HABLFAa_OPA
 
- HC_HABLFAa_OPA_MASK
 
- HC_HABLFAa_OPAp5
 
- HC_HABLFAa_maxAsrcAdst
 
- HC_HABLFAa_maxAsrcFog
 
- HC_HABLFAa_minAsrcAdst
 
- HC_HABLFAa_minAsrcFog
 
- HC_HABLFAa_minAsrcInvAdst
 
- HC_HABLFAb_0
 
- HC_HABLFAb_Adst
 
- HC_HABLFAb_Asrc
 
- HC_HABLFAb_Fog
 
- HC_HABLFAb_HABLFRA
 
- HC_HABLFAb_InvOPA
 
- HC_HABLFAb_MASK
 
- HC_HABLFAb_OPA
 
- HC_HABLFAb_OPA_MASK
 
- HC_HABLFAb_OPAp5
 
- HC_HABLFAb_maxAsrcAdst
 
- HC_HABLFAb_maxAsrcFog
 
- HC_HABLFAb_minAsrcAdst
 
- HC_HABLFAb_minAsrcFog
 
- HC_HABLFAb_minAsrcInvAdst
 
- HC_HABLFCa_Adst
 
- HC_HABLFCa_Asrc
 
- HC_HABLFCa_C_MASK
 
- HC_HABLFCa_Cdst
 
- HC_HABLFCa_Csrc
 
- HC_HABLFCa_Fog
 
- HC_HABLFCa_HABLRCa
 
- HC_HABLFCa_InvOPC
 
- HC_HABLFCa_MASK
 
- HC_HABLFCa_OPC
 
- HC_HABLFCa_OPC_MASK
 
- HC_HABLFCa_OPCp5
 
- HC_HABLFCa_maxSrcDst
 
- HC_HABLFCa_mimAsrcInvAdst
 
- HC_HABLFCa_minSrcDst
 
- HC_HABLFCb_Adst
 
- HC_HABLFCb_Asrc
 
- HC_HABLFCb_C_MASK
 
- HC_HABLFCb_Cdst
 
- HC_HABLFCb_Csrc
 
- HC_HABLFCb_Fog
 
- HC_HABLFCb_HABLRCb
 
- HC_HABLFCb_InvOPC
 
- HC_HABLFCb_MASK
 
- HC_HABLFCb_OPC
 
- HC_HABLFCb_OPC_MASK
 
- HC_HABLFCb_OPCp5
 
- HC_HABLFCb_maxSrcDst
 
- HC_HABLFCb_mimAsrcInvAdst
 
- HC_HABLFCb_minSrcDst
 
- HC_HABLRAa_MASK
 
- HC_HABLRAa_SHIFT
 
- HC_HABLRAb_MASK
 
- HC_HABLRAb_SHIFT
 
- HC_HABLRAbias_MASK
 
- HC_HABLRFAa_MASK
 
- HC_HABLRFAa_SHIFT
 
- HC_HABLRFAb_MASK
 
- HC_HABLdot_MASK
 
- HC_HABLoc_MASK
 
- HC_HABPit_MASK
 
- HC_HAGPBendH_MASK
 
- HC_HAGPBendH_SHIFT
 
- HC_HAGPBpH_MASK
 
- HC_HAGPBpID_JUMP
 
- HC_HAGPBpID_MASK
 
- HC_HAGPBpID_PAUSE
 
- HC_HAGPBpID_STOP
 
- HC_HAGPBpL_MASK
 
- HC_HAGPBstH_MASK
 
- HC_HAGPBstH_SHIFT
 
- HC_HAGPCMErrC_MASK
 
- HC_HAGPCMErr_MASK
 
- HC_HAGPCMNT_MASK
 
- HC_HATMD_AllPass
 
- HC_HATMD_EQ
 
- HC_HATMD_GE
 
- HC_HATMD_GT
 
- HC_HATMD_LE
 
- HC_HATMD_LT
 
- HC_HATMD_MASK
 
- HC_HATMD_NE
 
- HC_HATMD_NeverPass
 
- HC_HATREF_MASK
 
- HC_HArbWQCM_MASK
 
- HC_HBESt_MASK
 
- HC_HBFace_MASK
 
- HC_HCCPARAMS
 
- HC_HCRSt_MASK
 
- HC_HCSPARAMS
 
- HC_HClipB_MASK
 
- HC_HClipB_SHIFT
 
- HC_HClipL_MASK
 
- HC_HClipL_SHIFT
 
- HC_HClipR_MASK
 
- HC_HClipR_SHIFT
 
- HC_HClipT_MASK
 
- HC_HClipT_SHIFT
 
- HC_HCmdErrClr_MASK
 
- HC_HCmdHeader_MASK
 
- HC_HDASZC_MASK
 
- HC_HDBFM_ABGR0888
 
- HC_HDBFM_ABGR1555
 
- HC_HDBFM_ABGR4444
 
- HC_HDBFM_ABGR8888
 
- HC_HDBFM_ARGB0888
 
- HC_HDBFM_ARGB1555
 
- HC_HDBFM_ARGB4444
 
- HC_HDBFM_ARGB8888
 
- HC_HDBFM_BGR555
 
- HC_HDBFM_BGR565
 
- HC_HDBFM_MASK
 
- HC_HDBFM_RGB555
 
- HC_HDBFM_RGB565
 
- HC_HDBLoc_Local
 
- HC_HDBLoc_MASK
 
- HC_HDBLoc_Sys
 
- HC_HDBPit_MASK
 
- HC_HE2St_MASK
 
- HC_HE3Fire_MASK
 
- HC_HE3St_MASK
 
- HC_HEADER2
 
- HC_HEBEBias_MASK
 
- HC_HEBEBias_SHIFT
 
- HC_HEFlag_MASK
 
- HC_HEFlag_NoAA
 
- HC_HEFlag_ab
 
- HC_HEFlag_bc
 
- HC_HEFlag_ca
 
- HC_HEOF_MASK
 
- HC_HFBBMSKH_MASK
 
- HC_HFBBasH_MASK
 
- HC_HFBDrawFirst_MASK
 
- HC_HFBLock_MASK
 
- HC_HFBQueue_MASK
 
- HC_HFPClipBH_MASK
 
- HC_HFPClipBH_SHIFT
 
- HC_HFPClipLH_MASK
 
- HC_HFPClipLH_SHIFT
 
- HC_HFPClipRH_MASK
 
- HC_HFPClipRH_SHIFT
 
- HC_HFPClipTH_MASK
 
- HC_HFPClipTH_SHIFT
 
- HC_HFPn1_MASK
 
- HC_HFPn1_SHIFT
 
- HC_HFPn2_MASK
 
- HC_HFPn2_SHIFT
 
- HC_HFPn3_MASK
 
- HC_HFPn3_SHIFT
 
- HC_HFPn_MASK
 
- HC_HFthRTXA_MASK
 
- HC_HFthRTXD_MASK
 
- HC_HFthRTXD_SHIFT
 
- HC_HFthRZD_MASK
 
- HC_HFthRZD_SHIFT
 
- HC_HFthWZD_MASK
 
- HC_HGEMITout_MASK
 
- HC_HGEMITout_SHIFT
 
- HC_HLGEMISt_MASK
 
- HC_HLLastP_MASK
 
- HC_HLPrst_MASK
 
- HC_HNPArbZC_MASK
 
- HC_HPESt_MASK
 
- HC_HPLEND_MASK
 
- HC_HPMType_Line
 
- HC_HPMType_MASK
 
- HC_HPMType_Point
 
- HC_HPMType_Tri
 
- HC_HPMType_TriWF
 
- HC_HPMValidN_MASK
 
- HC_HPixGC_MASK
 
- HC_HRATFGMDi_MASK
 
- HC_HRATFGMDo_MASK
 
- HC_HRATFRTXA_MASK
 
- HC_HRATFRTXD_MASK
 
- HC_HRATFRZD_MASK
 
- HC_HRATFWCD_MASK
 
- HC_HRATFWZD_MASK
 
- HC_HRATTXCH_MASK
 
- HC_HRATTXTAG_MASK
 
- HC_HRFIFOATall_MASK
 
- HC_HRFIFOATbusy_MASK
 
- HC_HROP_BLACK
 
- HC_HROP_D
 
- HC_HROP_DPa
 
- HC_HROP_DPan
 
- HC_HROP_DPna
 
- HC_HROP_DPno
 
- HC_HROP_DPo
 
- HC_HROP_DPon
 
- HC_HROP_DPx
 
- HC_HROP_DPxn
 
- HC_HROP_Dn
 
- HC_HROP_MASK
 
- HC_HROP_P
 
- HC_HROP_PDna
 
- HC_HROP_PDno
 
- HC_HROP_Pn
 
- HC_HROP_WHITE
 
- HC_HRTXAempty_MASK
 
- HC_HRTXAfull_MASK
 
- HC_HRTXDempty_MASK
 
- HC_HRTXDfull_MASK
 
- HC_HRZDempty_MASK
 
- HC_HRZDfull_MASK
 
- HC_HSBFM_MASK
 
- HC_HSBLoc_MASK
 
- HC_HSBPit_MASK
 
- HC_HSE0St_MASK
 
- HC_HSE1St_MASK
 
- HC_HSGEMI_MASK
 
- HC_HSPXOS_MASK
 
- HC_HSPXOS_SHIFT
 
- HC_HSPYOS_MASK
 
- HC_HSTBMSK_MASK
 
- HC_HSTMD_AllPass
 
- HC_HSTMD_EQ
 
- HC_HSTMD_GE
 
- HC_HSTMD_GT
 
- HC_HSTMD_LE
 
- HC_HSTMD_LT
 
- HC_HSTMD_MASK
 
- HC_HSTMD_NE
 
- HC_HSTMD_NeverPass
 
- HC_HSTOPMSK_MASK
 
- HC_HSTOPMSK_SHIFT
 
- HC_HSTOPSF_DECR
 
- HC_HSTOPSF_DECRSAT
 
- HC_HSTOPSF_INCR
 
- HC_HSTOPSF_INCRSAT
 
- HC_HSTOPSF_INVERT
 
- HC_HSTOPSF_KEEP
 
- HC_HSTOPSF_MASK
 
- HC_HSTOPSF_REPLACE
 
- HC_HSTOPSF_ZERO
 
- HC_HSTOPSPZF_DECR
 
- HC_HSTOPSPZF_DECRSAT
 
- HC_HSTOPSPZF_INCR
 
- HC_HSTOPSPZF_INCRSAT
 
- HC_HSTOPSPZF_INVERT
 
- HC_HSTOPSPZF_KEEP
 
- HC_HSTOPSPZF_MASK
 
- HC_HSTOPSPZF_REPLACE
 
- HC_HSTOPSPZF_ZERO
 
- HC_HSTOPSPZP_DECR
 
- HC_HSTOPSPZP_DECRSAT
 
- HC_HSTOPSPZP_INCR
 
- HC_HSTOPSPZP_INCRSAT
 
- HC_HSTOPSPZP_INVERT
 
- HC_HSTOPSPZP_KEEP
 
- HC_HSTOPSPZP_MASK
 
- HC_HSTOPSPZP_REPLACE
 
- HC_HSTOPSPZP_ZERO
 
- HC_HSTREF_MASK
 
- HC_HSTREF_SHIFT
 
- HC_HShading_FlatA
 
- HC_HShading_FlatB
 
- HC_HShading_FlatC
 
- HC_HShading_Gouraud
 
- HC_HShading_MASK
 
- HC_HShading_Solid
 
- HC_HSolidCH_MASK
 
- HC_HTArbE2_MASK
 
- HC_HTArbRCM_MASK
 
- HC_HTArbRCW_MASK
 
- HC_HTArbRQCM_MASK
 
- HC_HTArbRTX_MASK
 
- HC_HTArbRZ_MASK
 
- HC_HTArbWZ_MASK
 
- HC_HTPnA_MASK
 
- HC_HTPnB_MASK
 
- HC_HTPnG_MASK
 
- HC_HTPnR_MASK
 
- HC_HTXCHCLR_MASK
 
- HC_HTXNum_MASK
 
- HC_HTXNum_SHIFT
 
- HC_HTXSMD_MASK
 
- HC_HTXTMD_MASK
 
- HC_HTXTRMD_MASK
 
- HC_HTXnCLODd_MASK
 
- HC_HTXnCLODu_MASK
 
- HC_HTXnCLODu_SHIFT
 
- HC_HTXnEnPit_MASK
 
- HC_HTXnFLDs_Ani
 
- HC_HTXnFLDs_AniDither
 
- HC_HTXnFLDs_ConstLOD
 
- HC_HTXnFLDs_Dither
 
- HC_HTXnFLDs_Linear
 
- HC_HTXnFLDs_MASK
 
- HC_HTXnFLDs_Nearest
 
- HC_HTXnFLDs_NonLinear
 
- HC_HTXnFLDs_Tex0
 
- HC_HTXnFLSe_Flat_Gaussian_Cubic
 
- HC_HTXnFLSe_Linear
 
- HC_HTXnFLSe_MASK
 
- HC_HTXnFLSe_Nearest
 
- HC_HTXnFLSe_NonLinear
 
- HC_HTXnFLSe_Sharp
 
- HC_HTXnFLSs_Flat_Gaussian_Cubic
 
- HC_HTXnFLSs_Linear
 
- HC_HTXnFLSs_MASK
 
- HC_HTXnFLSs_Nearest
 
- HC_HTXnFLSs_NonLinear
 
- HC_HTXnFLTe_Flat_Gaussian_Cubic
 
- HC_HTXnFLTe_Linear
 
- HC_HTXnFLTe_MASK
 
- HC_HTXnFLTe_Nearest
 
- HC_HTXnFLTe_NonLinear
 
- HC_HTXnFLTe_Sharp
 
- HC_HTXnFLTs_Flat_Gaussian_Cubic
 
- HC_HTXnFLTs_Linear
 
- HC_HTXnFLTs_MASK
 
- HC_HTXnFLTs_Nearest
 
- HC_HTXnFLTs_NonLinear
 
- HC_HTXnFM_A1
 
- HC_HTXnFM_A2
 
- HC_HTXnFM_A4
 
- HC_HTXnFM_A8
 
- HC_HTXnFM_ABGR0888
 
- HC_HTXnFM_ABGR1555
 
- HC_HTXnFM_ABGR16
 
- HC_HTXnFM_ABGR32
 
- HC_HTXnFM_ABGR4444
 
- HC_HTXnFM_ABGR8888
 
- HC_HTXnFM_AL44
 
- HC_HTXnFM_AL88
 
- HC_HTXnFM_ARGB0888
 
- HC_HTXnFM_ARGB1555
 
- HC_HTXnFM_ARGB16
 
- HC_HTXnFM_ARGB32
 
- HC_HTXnFM_ARGB4444
 
- HC_HTXnFM_ARGB8888
 
- HC_HTXnFM_Alpha
 
- HC_HTXnFM_BGR555
 
- HC_HTXnFM_BGR565
 
- HC_HTXnFM_BGRA16
 
- HC_HTXnFM_BGRA32
 
- HC_HTXnFM_BGRA4444
 
- HC_HTXnFM_BGRA5550
 
- HC_HTXnFM_BGRA5551
 
- HC_HTXnFM_BGRA8880
 
- HC_HTXnFM_BGRA8888
 
- HC_HTXnFM_BUMPMAP
 
- HC_HTXnFM_DX
 
- HC_HTXnFM_DX1
 
- HC_HTXnFM_DX23
 
- HC_HTXnFM_DX45
 
- HC_HTXnFM_INDEX
 
- HC_HTXnFM_Index1
 
- HC_HTXnFM_Index2
 
- HC_HTXnFM_Index4
 
- HC_HTXnFM_Index8
 
- HC_HTXnFM_Intensity
 
- HC_HTXnFM_L1
 
- HC_HTXnFM_L2
 
- HC_HTXnFM_L4
 
- HC_HTXnFM_L8
 
- HC_HTXnFM_LVU655
 
- HC_HTXnFM_LVU888
 
- HC_HTXnFM_Lum
 
- HC_HTXnFM_MASK
 
- HC_HTXnFM_RGB555
 
- HC_HTXnFM_RGB565
 
- HC_HTXnFM_RGBA16
 
- HC_HTXnFM_RGBA32
 
- HC_HTXnFM_RGBA4444
 
- HC_HTXnFM_RGBA5550
 
- HC_HTXnFM_RGBA5551
 
- HC_HTXnFM_RGBA8880
 
- HC_HTXnFM_RGBA8888
 
- HC_HTXnFM_T1
 
- HC_HTXnFM_T2
 
- HC_HTXnFM_T4
 
- HC_HTXnFM_T8
 
- HC_HTXnFM_VU88
 
- HC_HTXnL0BasH_MASK
 
- HC_HTXnL0HE_MASK
 
- HC_HTXnL0OS_MASK
 
- HC_HTXnL0OS_SHIFT
 
- HC_HTXnL0WE_MASK
 
- HC_HTXnL10BasH_MASK
 
- HC_HTXnL10BasH_SHIFT
 
- HC_HTXnL10HE_MASK
 
- HC_HTXnL10HE_SHIFT
 
- HC_HTXnL10WE_MASK
 
- HC_HTXnL10WE_SHIFT
 
- HC_HTXnL11BasH_MASK
 
- HC_HTXnL11BasH_SHIFT
 
- HC_HTXnL11HE_MASK
 
- HC_HTXnL11HE_SHIFT
 
- HC_HTXnL11WE_MASK
 
- HC_HTXnL11WE_SHIFT
 
- HC_HTXnL1BasH_MASK
 
- HC_HTXnL1BasH_SHIFT
 
- HC_HTXnL1HE_MASK
 
- HC_HTXnL1HE_SHIFT
 
- HC_HTXnL1WE_MASK
 
- HC_HTXnL1WE_SHIFT
 
- HC_HTXnL2BasH_MASK
 
- HC_HTXnL2BasH_SHIFT
 
- HC_HTXnL2HE_MASK
 
- HC_HTXnL2HE_SHIFT
 
- HC_HTXnL2WE_MASK
 
- HC_HTXnL2WE_SHIFT
 
- HC_HTXnL3BasH_MASK
 
- HC_HTXnL3HE_MASK
 
- HC_HTXnL3HE_SHIFT
 
- HC_HTXnL3WE_MASK
 
- HC_HTXnL3WE_SHIFT
 
- HC_HTXnL4BasH_MASK
 
- HC_HTXnL4BasH_SHIFT
 
- HC_HTXnL4HE_MASK
 
- HC_HTXnL4HE_SHIFT
 
- HC_HTXnL4WE_MASK
 
- HC_HTXnL4WE_SHIFT
 
- HC_HTXnL5BasH_MASK
 
- HC_HTXnL5BasH_SHIFT
 
- HC_HTXnL5HE_MASK
 
- HC_HTXnL5HE_SHIFT
 
- HC_HTXnL5WE_MASK
 
- HC_HTXnL5WE_SHIFT
 
- HC_HTXnL6BasH_MASK
 
- HC_HTXnL6HE_MASK
 
- HC_HTXnL6WE_MASK
 
- HC_HTXnL7BasH_MASK
 
- HC_HTXnL7BasH_SHIFT
 
- HC_HTXnL7HE_MASK
 
- HC_HTXnL7HE_SHIFT
 
- HC_HTXnL7WE_MASK
 
- HC_HTXnL7WE_SHIFT
 
- HC_HTXnL8BasH_MASK
 
- HC_HTXnL8BasH_SHIFT
 
- HC_HTXnL8HE_MASK
 
- HC_HTXnL8HE_SHIFT
 
- HC_HTXnL8WE_MASK
 
- HC_HTXnL8WE_SHIFT
 
- HC_HTXnL9BasH_MASK
 
- HC_HTXnL9HE_MASK
 
- HC_HTXnL9HE_SHIFT
 
- HC_HTXnL9WE_MASK
 
- HC_HTXnL9WE_SHIFT
 
- HC_HTXnLODDTf_MASK
 
- HC_HTXnLOff_MASK
 
- HC_HTXnLScale_MASK
 
- HC_HTXnLScale_SHIFT
 
- HC_HTXnLVmax_MASK
 
- HC_HTXnLVmax_SHIFT
 
- HC_HTXnLVmin_MASK
 
- HC_HTXnLaBasH_MASK
 
- HC_HTXnLaBasH_SHIFT
 
- HC_HTXnLaHE_MASK
 
- HC_HTXnLaHE_SHIFT
 
- HC_HTXnLaWE_MASK
 
- HC_HTXnLaWE_SHIFT
 
- HC_HTXnLbBasH_MASK
 
- HC_HTXnLbBasH_SHIFT
 
- HC_HTXnLbHE_MASK
 
- HC_HTXnLbHE_SHIFT
 
- HC_HTXnLbWE_MASK
 
- HC_HTXnLbWE_SHIFT
 
- HC_HTXnLcBasH_MASK
 
- HC_HTXnLcHE_MASK
 
- HC_HTXnLcWE_MASK
 
- HC_HTXnLdBasH_MASK
 
- HC_HTXnLdBasH_SHIFT
 
- HC_HTXnLdHE_MASK
 
- HC_HTXnLdHE_SHIFT
 
- HC_HTXnLdWE_MASK
 
- HC_HTXnLdWE_SHIFT
 
- HC_HTXnLeBasH_MASK
 
- HC_HTXnLeBasH_SHIFT
 
- HC_HTXnLeHE_MASK
 
- HC_HTXnLeHE_SHIFT
 
- HC_HTXnLeWE_MASK
 
- HC_HTXnLeWE_SHIFT
 
- HC_HTXnLfBasH_MASK
 
- HC_HTXnLfHE_MASK
 
- HC_HTXnLfHE_SHIFT
 
- HC_HTXnLfWE_MASK
 
- HC_HTXnLfWE_SHIFT
 
- HC_HTXnLnPitE_MASK
 
- HC_HTXnLnPitE_SHIFT
 
- HC_HTXnLnPit_MASK
 
- HC_HTXnLoc_AGP
 
- HC_HTXnLoc_Local
 
- HC_HTXnLoc_MASK
 
- HC_HTXnLoc_Sys
 
- HC_HTXnMPMD_SMASK
 
- HC_HTXnMPMD_Sclamp
 
- HC_HTXnMPMD_Smirror
 
- HC_HTXnMPMD_Srepeat
 
- HC_HTXnMPMD_Ssingle
 
- HC_HTXnMPMD_Swrap
 
- HC_HTXnMPMD_TMASK
 
- HC_HTXnMPMD_Tclamp
 
- HC_HTXnMPMD_Tmirror
 
- HC_HTXnMPMD_Trepeat
 
- HC_HTXnMPMD_Tsingle
 
- HC_HTXnMPMD_Twrap
 
- HC_HTXnTBA_MASK
 
- HC_HTXnTBLAMB_MASK
 
- HC_HTXnTBLAMB_SHIFT
 
- HC_HTXnTBLAa_Acur
 
- HC_HTXnTBLAa_Adif
 
- HC_HTXnTBLAa_Atex
 
- HC_HTXnTBLAa_Atexnext
 
- HC_HTXnTBLAa_Fog
 
- HC_HTXnTBLAa_HTXnTBLRA
 
- HC_HTXnTBLAa_InvTOPA
 
- HC_HTXnTBLAa_MASK
 
- HC_HTXnTBLAa_TOPA
 
- HC_HTXnTBLAa_TOPAp5
 
- HC_HTXnTBLAb_Acur
 
- HC_HTXnTBLAb_Adif
 
- HC_HTXnTBLAb_Atex
 
- HC_HTXnTBLAb_Atexnext
 
- HC_HTXnTBLAb_Fog
 
- HC_HTXnTBLAb_HTXnTBLRA
 
- HC_HTXnTBLAb_InvTOPA
 
- HC_HTXnTBLAb_MASK
 
- HC_HTXnTBLAb_TOPA
 
- HC_HTXnTBLAb_TOPAp5
 
- HC_HTXnTBLAbias_Acur
 
- HC_HTXnTBLAbias_Adif
 
- HC_HTXnTBLAbias_Atex
 
- HC_HTXnTBLAbias_Fog
 
- HC_HTXnTBLAbias_HTXnTBLRAbias
 
- HC_HTXnTBLAbias_Inv
 
- HC_HTXnTBLAbias_MASK
 
- HC_HTXnTBLAc_Acur
 
- HC_HTXnTBLAc_Adif
 
- HC_HTXnTBLAc_Atex
 
- HC_HTXnTBLAc_Atexnext
 
- HC_HTXnTBLAc_Fog
 
- HC_HTXnTBLAc_HTXnTBLRA
 
- HC_HTXnTBLAc_InvTOPA
 
- HC_HTXnTBLAc_MASK
 
- HC_HTXnTBLAc_TOPA
 
- HC_HTXnTBLAc_TOPAp5
 
- HC_HTXnTBLAop_Add
 
- HC_HTXnTBLAop_MASK
 
- HC_HTXnTBLAop_Mask
 
- HC_HTXnTBLAop_Max
 
- HC_HTXnTBLAop_Min
 
- HC_HTXnTBLAop_Sub
 
- HC_HTXnTBLAsat_MASK
 
- HC_HTXnTBLAshift_1
 
- HC_HTXnTBLAshift_2
 
- HC_HTXnTBLAshift_MASK
 
- HC_HTXnTBLAshift_No
 
- HC_HTXnTBLCa_0
 
- HC_HTXnTBLCa_Acur
 
- HC_HTXnTBLCa_Adif
 
- HC_HTXnTBLCa_Atex
 
- HC_HTXnTBLCa_Ctexnext
 
- HC_HTXnTBLCa_Cur
 
- HC_HTXnTBLCa_Dif
 
- HC_HTXnTBLCa_Fog
 
- HC_HTXnTBLCa_HTXnTBLRC
 
- HC_HTXnTBLCa_InvTOPC
 
- HC_HTXnTBLCa_MASK
 
- HC_HTXnTBLCa_Spec
 
- HC_HTXnTBLCa_TOPC
 
- HC_HTXnTBLCa_TOPCp5
 
- HC_HTXnTBLCa_Tex
 
- HC_HTXnTBLCb_0
 
- HC_HTXnTBLCb_Acur
 
- HC_HTXnTBLCb_Adif
 
- HC_HTXnTBLCb_Atex
 
- HC_HTXnTBLCb_Ctexnext
 
- HC_HTXnTBLCb_Cur
 
- HC_HTXnTBLCb_Dif
 
- HC_HTXnTBLCb_Fog
 
- HC_HTXnTBLCb_HTXnTBLRC
 
- HC_HTXnTBLCb_InvTOPC
 
- HC_HTXnTBLCb_MASK
 
- HC_HTXnTBLCb_Spec
 
- HC_HTXnTBLCb_TOPC
 
- HC_HTXnTBLCb_TOPCp5
 
- HC_HTXnTBLCb_Tex
 
- HC_HTXnTBLCbias_0
 
- HC_HTXnTBLCbias_Acur
 
- HC_HTXnTBLCbias_Adif
 
- HC_HTXnTBLCbias_Atex
 
- HC_HTXnTBLCbias_Cbias
 
- HC_HTXnTBLCbias_Cur
 
- HC_HTXnTBLCbias_Dif
 
- HC_HTXnTBLCbias_Fog
 
- HC_HTXnTBLCbias_HTXnTBLRC
 
- HC_HTXnTBLCbias_InvCbias
 
- HC_HTXnTBLCbias_MASK
 
- HC_HTXnTBLCbias_Spec
 
- HC_HTXnTBLCbias_Tex
 
- HC_HTXnTBLCc_0
 
- HC_HTXnTBLCc_Acur
 
- HC_HTXnTBLCc_Adif
 
- HC_HTXnTBLCc_Atex
 
- HC_HTXnTBLCc_Ctexnext
 
- HC_HTXnTBLCc_Cur
 
- HC_HTXnTBLCc_Dif
 
- HC_HTXnTBLCc_Fog
 
- HC_HTXnTBLCc_HTXnTBLRC
 
- HC_HTXnTBLCc_InvTOPC
 
- HC_HTXnTBLCc_MASK
 
- HC_HTXnTBLCc_Spec
 
- HC_HTXnTBLCc_TOPC
 
- HC_HTXnTBLCc_TOPCp5
 
- HC_HTXnTBLCc_Tex
 
- HC_HTXnTBLCop_Add
 
- HC_HTXnTBLCop_MASK
 
- HC_HTXnTBLCop_Mask
 
- HC_HTXnTBLCop_Max
 
- HC_HTXnTBLCop_Min
 
- HC_HTXnTBLCop_Sub
 
- HC_HTXnTBLCsat_MASK
 
- HC_HTXnTBLCshift_1
 
- HC_HTXnTBLCshift_2
 
- HC_HTXnTBLCshift_DotP
 
- HC_HTXnTBLCshift_MASK
 
- HC_HTXnTBLCshift_No
 
- HC_HTXnTBLDOT3
 
- HC_HTXnTBLDOT4
 
- HC_HTXnTBLMPfog_0
 
- HC_HTXnTBLMPfog_Acur
 
- HC_HTXnTBLMPfog_Adif
 
- HC_HTXnTBLMPfog_Atex
 
- HC_HTXnTBLMPfog_Fog
 
- HC_HTXnTBLMPfog_GHTXnTBLRFog
 
- HC_HTXnTBLMPfog_MASK
 
- HC_HTXnTBLRAa_MASK
 
- HC_HTXnTBLRAa_SHIFT
 
- HC_HTXnTBLRAb_MASK
 
- HC_HTXnTBLRAb_SHIFT
 
- HC_HTXnTBLRAbias_MASK
 
- HC_HTXnTBLRAbias_SHIFT
 
- HC_HTXnTBLRAc_MASK
 
- HC_HTXnTBLRAc_SHIFT
 
- HC_HTXnTBLRFog_MASK
 
- HC_HTXnTBLRFog_SHIFT
 
- HC_HTXnTBLdot_MASK
 
- HC_HTXnTB_MASK
 
- HC_HTXnTB_NoTB
 
- HC_HTXnTB_TBC_S
 
- HC_HTXnTB_TBC_T
 
- HC_HTXnTB_TB_S
 
- HC_HTXnTB_TB_T
 
- HC_HTXnTRAH_MASK
 
- HC_HTXnTRAH_SHIFT
 
- HC_HTXnTRAL_MASK
 
- HC_HTXnTRAL_SHIFT
 
- HC_HTXnXY2ST_MASK
 
- HC_HVCycle_AA
 
- HC_HVCycle_AB
 
- HC_HVCycle_AC
 
- HC_HVCycle_AFP
 
- HC_HVCycle_BA
 
- HC_HVCycle_BB
 
- HC_HVCycle_BC
 
- HC_HVCycle_CA
 
- HC_HVCycle_CB
 
- HC_HVCycle_CC
 
- HC_HVCycle_ChgA_MASK
 
- HC_HVCycle_ChgB_MASK
 
- HC_HVCycle_ChgC_MASK
 
- HC_HVCycle_Full
 
- HC_HVCycle_MASK
 
- HC_HVCycle_NewA
 
- HC_HVCycle_NewB
 
- HC_HVCycle_NewC
 
- HC_HVCycle_One
 
- HC_HVCycle_Style_MASK
 
- HC_HVPMSK_Cd
 
- HC_HVPMSK_Cs
 
- HC_HVPMSK_MASK
 
- HC_HVPMSK_S
 
- HC_HVPMSK_T
 
- HC_HVPMSK_W
 
- HC_HVPMSK_X
 
- HC_HVPMSK_Y
 
- HC_HVPMSK_Z
 
- HC_HWCDempty_MASK
 
- HC_HWCDfull_MASK
 
- HC_HWZDempty_MASK
 
- HC_HWZDfull_MASK
 
- HC_HW_MODE_CTRL
 
- HC_HXESt_MASK
 
- HC_HZBiasH_MASK
 
- HC_HZBiasedWB_MASK
 
- HC_HZCYNum_MASK
 
- HC_HZCYNum_SHIFT
 
- HC_HZNF_MASK
 
- HC_HZONEasFF_MASK
 
- HC_HZOONEasFF_MASK
 
- HC_HZWBFM_16
 
- HC_HZWBFM_24
 
- HC_HZWBFM_32
 
- HC_HZWBFM_MASK
 
- HC_HZWBLoc_Local
 
- HC_HZWBLoc_MASK
 
- HC_HZWBLoc_SyS
 
- HC_HZWBPit_MASK
 
- HC_HZWBType_MASK
 
- HC_HZWBend_MASK
 
- HC_HZWBend_SHIFT
 
- HC_HZWCDH_MASK
 
- HC_HZWCDH_SHIFT
 
- HC_HZWCDL_MASK
 
- HC_HZWCQWnumLast_MASK
 
- HC_HZWCQWnumLast_SHIFT
 
- HC_HZWCQWnum_MASK
 
- HC_HZWCQWnum_SHIFT
 
- HC_HZWCTAGnum_MASK
 
- HC_HZWCTAGnum_SHIFT
 
- HC_HZWTMD_AllPass
 
- HC_HZWTMD_EQ
 
- HC_HZWTMD_GE
 
- HC_HZWTMD_GT
 
- HC_HZWTMD_LE
 
- HC_HZWTMD_LT
 
- HC_HZWTMD_MASK
 
- HC_HZWTMD_NE
 
- HC_HZWTMD_NeverPass
 
- HC_HenAA_MASK
 
- HC_HenABL_MASK
 
- HC_HenAT_MASK
 
- HC_HenAW_MASK
 
- HC_HenCMDQ_MASK
 
- HC_HenCPUDAZ_MASK
 
- HC_HenCS_MASK
 
- HC_HenCW_MASK
 
- HC_HenDASZWC_MASK
 
- HC_HenDT_MASK
 
- HC_HenFBASwap_MASK
 
- HC_HenFBCull_MASK
 
- HC_HenFIFOAT_MASK
 
- HC_HenFOG_MASK
 
- HC_HenGEMILock_MASK
 
- HC_HenLP_MASK
 
- HC_HenOT_MASK
 
- HC_HenSP_MASK
 
- HC_HenST_MASK
 
- HC_HenTXCH_MASK
 
- HC_HenTXCTSU_MASK
 
- HC_HenTXEnvMap_MASK
 
- HC_HenTXMP_MASK
 
- HC_HenTXPP_MASK
 
- HC_HenTXTR_MASK
 
- HC_HenVertexCNT_MASK
 
- HC_HenZT_MASK
 
- HC_HenZW_MASK
 
- HC_IBSS_RECONF
 
- HC_IBSS_START
 
- HC_IGU_BC_MODE
 
- HC_IGU_NBC_MODE
 
- HC_INDEX_DATA_DYNAMIC_HC_ENABLED
 
- HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT
 
- HC_INDEX_DATA_HC_ENABLED
 
- HC_INDEX_DATA_HC_ENABLED_SHIFT
 
- HC_INDEX_DATA_RESERVE
 
- HC_INDEX_DATA_RESERVE_SHIFT
 
- HC_INDEX_DATA_SM_ID
 
- HC_INDEX_DATA_SM_ID_SHIFT
 
- HC_INDEX_ETH_FIRST_TX_CQ_CONS
 
- HC_INDEX_ETH_RX_CQ_CONS
 
- HC_INDEX_ETH_TX_CQ_CONS_COS0
 
- HC_INDEX_ETH_TX_CQ_CONS_COS1
 
- HC_INDEX_ETH_TX_CQ_CONS_COS2
 
- HC_INDEX_FCOE_EQ_CONS
 
- HC_INDEX_ISCSI_EQ_CONS
 
- HC_INDEX_OOO_TX_CQ_CONS
 
- HC_INITFF
 
- HC_INITHBI
 
- HC_INITMB
 
- HC_INTERRUPT_ENABLE
 
- HC_INTERRUPT_REG
 
- HC_INTL_INT
 
- HC_INT_IRQ_MASK_AND_REG
 
- HC_INT_IRQ_MASK_OR_REG
 
- HC_INT_MASK_REG
 
- HC_INT_PTD_DONEMAP_REG
 
- HC_INT_PTD_LASTPTD_REG
 
- HC_INT_PTD_SKIPMAP_REG
 
- HC_IRQ_CAUSE
 
- HC_IRQ_COAL_IO_THRESHOLD
 
- HC_IRQ_COAL_TIME_THRESHOLD
 
- HC_ISO_INT
 
- HC_ISO_IRQ_MASK_AND_REG
 
- HC_ISO_IRQ_MASK_OR_REG
 
- HC_ISO_PTD_DONEMAP_REG
 
- HC_ISO_PTD_LASTPTD_REG
 
- HC_ISO_PTD_SKIPMAP_REG
 
- HC_IS_RUNNING
 
- HC_IS_SUSPENDED
 
- HC_LAINT_ENA
 
- HC_LENGTH
 
- HC_LP_CTRL
 
- HC_MAIN_RSVD
 
- HC_MAIN_RSVD_5
 
- HC_MAIN_RSVD_SOC
 
- HC_MBINT_ENA
 
- HC_MEMORY_REG
 
- HC_MODE_EN
 
- HC_PAUSE_RISC
 
- HC_PORT1_CTRL
 
- HC_PORTSC1
 
- HC_ParaAdr_MASK
 
- HC_ParaAdr_SHIFT
 
- HC_ParaN_MASK
 
- HC_ParaOS_MASK
 
- HC_ParaOS_SHIFT
 
- HC_ParaSubType_MASK
 
- HC_ParaSubType_SHIFT
 
- HC_ParaType_Auto
 
- HC_ParaType_CmdVdata
 
- HC_ParaType_MASK
 
- HC_ParaType_NotTex
 
- HC_ParaType_Palette
 
- HC_ParaType_PreCR
 
- HC_ParaType_SHIFT
 
- HC_ParaType_Tex
 
- HC_Para_MASK
 
- HC_QOS_SUPPORT_ASSOC
 
- HC_R0INT_ENA
 
- HC_R1INT_ENA
 
- HC_R2INT_ENA
 
- HC_R3INT_ENA
 
- HC_REASSOCIATE
 
- HC_REGULAR_SEGMENT
 
- HC_REG_AGG_INT_0
 
- HC_REG_AGG_INT_1
 
- HC_REG_ATTN_BIT
 
- HC_REG_ATTN_IDX
 
- HC_REG_ATTN_MSG0_ADDR_L
 
- HC_REG_ATTN_MSG1_ADDR_L
 
- HC_REG_ATTN_NUM_P0
 
- HC_REG_ATTN_NUM_P1
 
- HC_REG_BASE
 
- HC_REG_COMMAND_REG
 
- HC_REG_CONFIG_0
 
- HC_REG_CONFIG_1
 
- HC_REG_FIFOstatus
 
- HC_REG_FUNC_NUM_P0
 
- HC_REG_FUNC_NUM_P1
 
- HC_REG_HC_PRTY_MASK
 
- HC_REG_HC_PRTY_STS
 
- HC_REG_HC_PRTY_STS_CLR
 
- HC_REG_HREngSt
 
- HC_REG_HRErr
 
- HC_REG_HRFIFOempty
 
- HC_REG_HRFIFOfull
 
- HC_REG_Hpara0
 
- HC_REG_HpataAF
 
- HC_REG_INT_MASK
 
- HC_REG_LEADING_EDGE_0
 
- HC_REG_LEADING_EDGE_1
 
- HC_REG_MAIN_MEMORY
 
- HC_REG_MAIN_MEMORY_SIZE
 
- HC_REG_OFFSET
 
- HC_REG_P0_PROD_CONS
 
- HC_REG_P1_PROD_CONS
 
- HC_REG_PBA_COMMAND
 
- HC_REG_PCI_CONFIG_0
 
- HC_REG_PCI_CONFIG_1
 
- HC_REG_STATISTIC_COUNTERS
 
- HC_REG_TRAILING_EDGE_0
 
- HC_REG_TRAILING_EDGE_1
 
- HC_REG_TRANS_SET
 
- HC_REG_TRANS_SPACE
 
- HC_REG_UC_RAM_ADDR_0
 
- HC_REG_UC_RAM_ADDR_1
 
- HC_REG_USTORM_ADDR_FOR_COALESCE
 
- HC_REG_VQID_0
 
- HC_REG_VQID_1
 
- HC_RELEASE_RISC
 
- HC_RESET_REG
 
- HC_RESET_RISC
 
- HC_SB_MAX_DYNAMIC_INDICES
 
- HC_SB_MAX_INDICES_E1X
 
- HC_SB_MAX_INDICES_E2
 
- HC_SB_MAX_SB_E1X
 
- HC_SB_MAX_SB_E2
 
- HC_SB_MAX_SM
 
- HC_SCRATCH_REG
 
- HC_SEG_ACCESS_ATTN
 
- HC_SEG_ACCESS_DEF
 
- HC_SEG_ACCESS_NORM
 
- HC_SET_HOST_INT
 
- HC_SHIFT
 
- HC_SIMA_FIFOstatus
 
- HC_SIMA_FOGTABLE
 
- HC_SIMA_HABBasH
 
- HC_SIMA_HABBasL
 
- HC_SIMA_HABFM
 
- HC_SIMA_HABLAop
 
- HC_SIMA_HABLAsat
 
- HC_SIMA_HABLCop
 
- HC_SIMA_HABLCsat
 
- HC_SIMA_HABLRAa
 
- HC_SIMA_HABLRAb
 
- HC_SIMA_HABLRCa
 
- HC_SIMA_HABLRCb
 
- HC_SIMA_HABLRCbias
 
- HC_SIMA_HABLRFCa
 
- HC_SIMA_HABLRFCb
 
- HC_SIMA_HAGPBendL
 
- HC_SIMA_HAGPBpH
 
- HC_SIMA_HAGPBpL
 
- HC_SIMA_HAGPBstL
 
- HC_SIMA_HAGPCMNT
 
- HC_SIMA_HATMD
 
- HC_SIMA_HClipLR
 
- HC_SIMA_HClipTB
 
- HC_SIMA_HCmdA
 
- HC_SIMA_HCmdB
 
- HC_SIMA_HDBBasH
 
- HC_SIMA_HDBBasL
 
- HC_SIMA_HDBFM
 
- HC_SIMA_HE3Fire
 
- HC_SIMA_HEnable
 
- HC_SIMA_HFBBMSKL
 
- HC_SIMA_HFBBasL
 
- HC_SIMA_HFBDrawFirst
 
- HC_SIMA_HFPClipBL
 
- HC_SIMA_HFPClipLL
 
- HC_SIMA_HFPClipLRH
 
- HC_SIMA_HFPClipRL
 
- HC_SIMA_HFPClipTBH
 
- HC_SIMA_HFPClipTL
 
- HC_SIMA_HFogCH
 
- HC_SIMA_HFogCL
 
- HC_SIMA_HFogDenst
 
- HC_SIMA_HFogEndL
 
- HC_SIMA_HFogLF
 
- HC_SIMA_HFogOOdEF
 
- HC_SIMA_HFogOOdMF
 
- HC_SIMA_HFogStH
 
- HC_SIMA_HFogStL
 
- HC_SIMA_HFthRTXA
 
- HC_SIMA_HFthRTXD
 
- HC_SIMA_HGEMITout
 
- HC_SIMA_HLP
 
- HC_SIMA_HLPRF
 
- HC_SIMA_HPixGC
 
- HC_SIMA_HREngSt
 
- HC_SIMA_HRErr
 
- HC_SIMA_HRFIFOempty
 
- HC_SIMA_HRFIFOfull
 
- HC_SIMA_HROP
 
- HC_SIMA_HSPXYOS
 
- HC_SIMA_HSTMD
 
- HC_SIMA_HSTREF
 
- HC_SIMA_HSolidCL
 
- HC_SIMA_HTArbE2
 
- HC_SIMA_HTArbRCM
 
- HC_SIMA_HTArbRCW
 
- HC_SIMA_HTArbRTX
 
- HC_SIMA_HTArbRZ
 
- HC_SIMA_HTArbWZ
 
- HC_SIMA_HTP0
 
- HC_SIMA_HTP1
 
- HC_SIMA_HTX0BumpM00
 
- HC_SIMA_HTX0BumpM01
 
- HC_SIMA_HTX0BumpM10
 
- HC_SIMA_HTX0BumpM11
 
- HC_SIMA_HTX0CLODu
 
- HC_SIMA_HTX0FM
 
- HC_SIMA_HTX0L012BasH
 
- HC_SIMA_HTX0L0BasL
 
- HC_SIMA_HTX0L0OS
 
- HC_SIMA_HTX0L0Pit
 
- HC_SIMA_HTX0L0_5HE
 
- HC_SIMA_HTX0L0_5WE
 
- HC_SIMA_HTX0L10BasL
 
- HC_SIMA_HTX0L10Pit
 
- HC_SIMA_HTX0L11BasL
 
- HC_SIMA_HTX0L11Pit
 
- HC_SIMA_HTX0L1BasL
 
- HC_SIMA_HTX0L1Pit
 
- HC_SIMA_HTX0L2BasL
 
- HC_SIMA_HTX0L2Pit
 
- HC_SIMA_HTX0L345BasH
 
- HC_SIMA_HTX0L3BasL
 
- HC_SIMA_HTX0L3Pit
 
- HC_SIMA_HTX0L4BasL
 
- HC_SIMA_HTX0L4Pit
 
- HC_SIMA_HTX0L5BasL
 
- HC_SIMA_HTX0L5Pit
 
- HC_SIMA_HTX0L678BasH
 
- HC_SIMA_HTX0L6BasL
 
- HC_SIMA_HTX0L6Pit
 
- HC_SIMA_HTX0L6_bHE
 
- HC_SIMA_HTX0L6_bWE
 
- HC_SIMA_HTX0L7BasL
 
- HC_SIMA_HTX0L7Pit
 
- HC_SIMA_HTX0L8BasL
 
- HC_SIMA_HTX0L8Pit
 
- HC_SIMA_HTX0L9BasL
 
- HC_SIMA_HTX0L9Pit
 
- HC_SIMA_HTX0L9abBasH
 
- HC_SIMA_HTX0LScale
 
- HC_SIMA_HTX0LaBasL
 
- HC_SIMA_HTX0LaPit
 
- HC_SIMA_HTX0LbBasL
 
- HC_SIMA_HTX0LbPit
 
- HC_SIMA_HTX0LcBasL
 
- HC_SIMA_HTX0LcPit
 
- HC_SIMA_HTX0Lc_11HE
 
- HC_SIMA_HTX0Lc_11WE
 
- HC_SIMA_HTX0LcdeBasH
 
- HC_SIMA_HTX0LdBasL
 
- HC_SIMA_HTX0LdPit
 
- HC_SIMA_HTX0LeBasL
 
- HC_SIMA_HTX0LePit
 
- HC_SIMA_HTX0Lf1011BasH
 
- HC_SIMA_HTX0LfBasL
 
- HC_SIMA_HTX0LfPit
 
- HC_SIMA_HTX0MPMD
 
- HC_SIMA_HTX0TB
 
- HC_SIMA_HTX0TBC
 
- HC_SIMA_HTX0TBLAsat
 
- HC_SIMA_HTX0TBLCop
 
- HC_SIMA_HTX0TBLCsat
 
- HC_SIMA_HTX0TBLMPfog
 
- HC_SIMA_HTX0TBLRAa
 
- HC_SIMA_HTX0TBLRCa
 
- HC_SIMA_HTX0TBLRCb
 
- HC_SIMA_HTX0TBLRCbias
 
- HC_SIMA_HTX0TBLRCc
 
- HC_SIMA_HTX0TBLRFog
 
- HC_SIMA_HTX0TRAH
 
- HC_SIMA_HTX0TRCH
 
- HC_SIMA_HTX0TRCL
 
- HC_SIMA_HTX1BumpM00
 
- HC_SIMA_HTX1BumpM01
 
- HC_SIMA_HTX1BumpM10
 
- HC_SIMA_HTX1BumpM11
 
- HC_SIMA_HTX1CLODu
 
- HC_SIMA_HTX1FM
 
- HC_SIMA_HTX1L012BasH
 
- HC_SIMA_HTX1L0BasL
 
- HC_SIMA_HTX1L0OS
 
- HC_SIMA_HTX1L0Pit
 
- HC_SIMA_HTX1L0_5HE
 
- HC_SIMA_HTX1L0_5WE
 
- HC_SIMA_HTX1L10BasL
 
- HC_SIMA_HTX1L10Pit
 
- HC_SIMA_HTX1L11BasL
 
- HC_SIMA_HTX1L11Pit
 
- HC_SIMA_HTX1L1BasL
 
- HC_SIMA_HTX1L1Pit
 
- HC_SIMA_HTX1L2BasL
 
- HC_SIMA_HTX1L2Pit
 
- HC_SIMA_HTX1L345BasH
 
- HC_SIMA_HTX1L3BasL
 
- HC_SIMA_HTX1L3Pit
 
- HC_SIMA_HTX1L4BasL
 
- HC_SIMA_HTX1L4Pit
 
- HC_SIMA_HTX1L5BasL
 
- HC_SIMA_HTX1L5Pit
 
- HC_SIMA_HTX1L678BasH
 
- HC_SIMA_HTX1L6BasL
 
- HC_SIMA_HTX1L6Pit
 
- HC_SIMA_HTX1L6_bHE
 
- HC_SIMA_HTX1L6_bWE
 
- HC_SIMA_HTX1L7BasL
 
- HC_SIMA_HTX1L7Pit
 
- HC_SIMA_HTX1L8BasL
 
- HC_SIMA_HTX1L8Pit
 
- HC_SIMA_HTX1L9BasL
 
- HC_SIMA_HTX1L9Pit
 
- HC_SIMA_HTX1L9abBasH
 
- HC_SIMA_HTX1LScale
 
- HC_SIMA_HTX1LTA
 
- HC_SIMA_HTX1LTC
 
- HC_SIMA_HTX1LaBasL
 
- HC_SIMA_HTX1LaPit
 
- HC_SIMA_HTX1LbBasL
 
- HC_SIMA_HTX1LbPit
 
- HC_SIMA_HTX1LcBasL
 
- HC_SIMA_HTX1LcPit
 
- HC_SIMA_HTX1Lc_11HE
 
- HC_SIMA_HTX1Lc_11WE
 
- HC_SIMA_HTX1LcdeBasH
 
- HC_SIMA_HTX1LdBasL
 
- HC_SIMA_HTX1LdPit
 
- HC_SIMA_HTX1LeBasL
 
- HC_SIMA_HTX1LePit
 
- HC_SIMA_HTX1Lf1011BasH
 
- HC_SIMA_HTX1LfBasL
 
- HC_SIMA_HTX1LfPit
 
- HC_SIMA_HTX1MPMD
 
- HC_SIMA_HTX1TB
 
- HC_SIMA_HTX1TBC
 
- HC_SIMA_HTX1TBLAsat
 
- HC_SIMA_HTX1TBLCop
 
- HC_SIMA_HTX1TBLCsat
 
- HC_SIMA_HTX1TBLMPfog
 
- HC_SIMA_HTX1TBLRAa
 
- HC_SIMA_HTX1TBLRCa
 
- HC_SIMA_HTX1TBLRCb
 
- HC_SIMA_HTX1TBLRCbias
 
- HC_SIMA_HTX1TBLRCc
 
- HC_SIMA_HTX1TBLRFog
 
- HC_SIMA_HTX1TRAH
 
- HC_SIMA_HTX1TRCH
 
- HC_SIMA_HTX1TRCL
 
- HC_SIMA_HTXSMD
 
- HC_SIMA_HZBiasL
 
- HC_SIMA_HZCYNum
 
- HC_SIMA_HZWBBasH
 
- HC_SIMA_HZWBBasL
 
- HC_SIMA_HZWBType
 
- HC_SIMA_HZWBend
 
- HC_SIMA_HZWCDL
 
- HC_SIMA_HZWCFire
 
- HC_SIMA_HZWCTAGnum
 
- HC_SIMA_HZWTMD
 
- HC_SIMA_HenFIFOAT
 
- HC_SIMA_STIPPLE
 
- HC_SIMA_TRANS_SET
 
- HC_SIMA_TX0TX1_OFF
 
- HC_SMITYPE_NONE
 
- HC_SMITYPE_TYPE1
 
- HC_SMITYPE_TYPE2
 
- HC_SMITYPE_TYPE3
 
- HC_SOT_INT
 
- HC_SP_INDEX_EQ_CONS
 
- HC_SP_INDEX_ETH_DEF_CONS
 
- HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
 
- HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
 
- HC_SP_INDEX_ETH_ISCSI_CQ_CONS
 
- HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS
 
- HC_SP_SB_ID
 
- HC_SP_SB_MAX_INDICES
 
- HC_STATE_HALT
 
- HC_STATE_QUIESCING
 
- HC_STATE_RESUMING
 
- HC_STATE_RUNNING
 
- HC_STATE_SUSPENDED
 
- HC_STATUS_REG
 
- HC_SubA_HABBasH
 
- HC_SubA_HABBasL
 
- HC_SubA_HABFM
 
- HC_SubA_HABLAop
 
- HC_SubA_HABLAsat
 
- HC_SubA_HABLCop
 
- HC_SubA_HABLCsat
 
- HC_SubA_HABLRAa
 
- HC_SubA_HABLRAb
 
- HC_SubA_HABLRCa
 
- HC_SubA_HABLRCb
 
- HC_SubA_HABLRCbias
 
- HC_SubA_HABLRFCa
 
- HC_SubA_HABLRFCb
 
- HC_SubA_HAGPBendL
 
- HC_SubA_HAGPBpH
 
- HC_SubA_HAGPBpL
 
- HC_SubA_HAGPBstL
 
- HC_SubA_HAGPCMNT
 
- HC_SubA_HATMD
 
- HC_SubA_HArbRQCM
 
- HC_SubA_HArbWQCM
 
- HC_SubA_HCMDQLen
 
- HC_SubA_HCMDQendL
 
- HC_SubA_HCMDQstL
 
- HC_SubA_HClipLR
 
- HC_SubA_HClipTB
 
- HC_SubA_HDBBasH
 
- HC_SubA_HDBBasL
 
- HC_SubA_HDBFM
 
- HC_SubA_HEnable
 
- HC_SubA_HFBBMSKL
 
- HC_SubA_HFBBasL
 
- HC_SubA_HFBDrawFirst
 
- HC_SubA_HFBDst
 
- HC_SubA_HFPClipBL
 
- HC_SubA_HFPClipLL
 
- HC_SubA_HFPClipLRH
 
- HC_SubA_HFPClipRL
 
- HC_SubA_HFPClipTBH
 
- HC_SubA_HFPClipTL
 
- HC_SubA_HFogCH
 
- HC_SubA_HFogCL
 
- HC_SubA_HFogDenst
 
- HC_SubA_HFogEndL
 
- HC_SubA_HFogLF
 
- HC_SubA_HFogOOdEF
 
- HC_SubA_HFogOOdMF
 
- HC_SubA_HFogStH
 
- HC_SubA_HFogStL
 
- HC_SubA_HFthRTXA
 
- HC_SubA_HFthRTXD
 
- HC_SubA_HGEMITout
 
- HC_SubA_HLP
 
- HC_SubA_HLPRF
 
- HC_SubA_HPixGC
 
- HC_SubA_HROP
 
- HC_SubA_HSPXYOS
 
- HC_SubA_HSTMD
 
- HC_SubA_HSTREF
 
- HC_SubA_HSolidCL
 
- HC_SubA_HTArbE2
 
- HC_SubA_HTArbRCM
 
- HC_SubA_HTArbRCW
 
- HC_SubA_HTArbRTX
 
- HC_SubA_HTArbRZ
 
- HC_SubA_HTArbWZ
 
- HC_SubA_HTXSMD
 
- HC_SubA_HTXnBumpM00
 
- HC_SubA_HTXnBumpM01
 
- HC_SubA_HTXnBumpM10
 
- HC_SubA_HTXnBumpM11
 
- HC_SubA_HTXnCLODu
 
- HC_SubA_HTXnFM
 
- HC_SubA_HTXnL012BasH
 
- HC_SubA_HTXnL0BasL
 
- HC_SubA_HTXnL0OS
 
- HC_SubA_HTXnL0Pit
 
- HC_SubA_HTXnL0_5HE
 
- HC_SubA_HTXnL0_5WE
 
- HC_SubA_HTXnL10BasL
 
- HC_SubA_HTXnL10Pit
 
- HC_SubA_HTXnL11BasL
 
- HC_SubA_HTXnL11Pit
 
- HC_SubA_HTXnL1BasL
 
- HC_SubA_HTXnL1Pit
 
- HC_SubA_HTXnL2BasL
 
- HC_SubA_HTXnL2Pit
 
- HC_SubA_HTXnL345BasH
 
- HC_SubA_HTXnL3BasL
 
- HC_SubA_HTXnL3Pit
 
- HC_SubA_HTXnL4BasL
 
- HC_SubA_HTXnL4Pit
 
- HC_SubA_HTXnL5BasL
 
- HC_SubA_HTXnL5Pit
 
- HC_SubA_HTXnL678BasH
 
- HC_SubA_HTXnL6BasL
 
- HC_SubA_HTXnL6Pit
 
- HC_SubA_HTXnL6_bHE
 
- HC_SubA_HTXnL6_bWE
 
- HC_SubA_HTXnL7BasL
 
- HC_SubA_HTXnL7Pit
 
- HC_SubA_HTXnL8BasL
 
- HC_SubA_HTXnL8Pit
 
- HC_SubA_HTXnL9BasL
 
- HC_SubA_HTXnL9Pit
 
- HC_SubA_HTXnL9abBasH
 
- HC_SubA_HTXnLScale
 
- HC_SubA_HTXnLaBasL
 
- HC_SubA_HTXnLaPit
 
- HC_SubA_HTXnLbBasL
 
- HC_SubA_HTXnLbPit
 
- HC_SubA_HTXnLcBasL
 
- HC_SubA_HTXnLcPit
 
- HC_SubA_HTXnLc_11HE
 
- HC_SubA_HTXnLc_11WE
 
- HC_SubA_HTXnLcdeBasH
 
- HC_SubA_HTXnLdBasL
 
- HC_SubA_HTXnLdPit
 
- HC_SubA_HTXnLeBasL
 
- HC_SubA_HTXnLePit
 
- HC_SubA_HTXnLf1011BasH
 
- HC_SubA_HTXnLfBasL
 
- HC_SubA_HTXnLfPit
 
- HC_SubA_HTXnMPMD
 
- HC_SubA_HTXnTB
 
- HC_SubA_HTXnTBC
 
- HC_SubA_HTXnTBLAsat
 
- HC_SubA_HTXnTBLCop
 
- HC_SubA_HTXnTBLCsat
 
- HC_SubA_HTXnTBLMPfog
 
- HC_SubA_HTXnTBLRAa
 
- HC_SubA_HTXnTBLRCa
 
- HC_SubA_HTXnTBLRCb
 
- HC_SubA_HTXnTBLRCbias
 
- HC_SubA_HTXnTBLRCc
 
- HC_SubA_HTXnTBLRFog
 
- HC_SubA_HTXnTRAH
 
- HC_SubA_HTXnTRCH
 
- HC_SubA_HTXnTRCL
 
- HC_SubA_HVertexCNT
 
- HC_SubA_HZBiasL
 
- HC_SubA_HZCYNum
 
- HC_SubA_HZWBBasH
 
- HC_SubA_HZWBBasL
 
- HC_SubA_HZWBType
 
- HC_SubA_HZWBend
 
- HC_SubA_HZWCDL
 
- HC_SubA_HZWCFire
 
- HC_SubA_HZWCTAGnum
 
- HC_SubA_HZWTMD
 
- HC_SubA_HenFIFOAT
 
- HC_SubA_MASK
 
- HC_SubA_SHIFT
 
- HC_SubType_FogTable
 
- HC_SubType_Stipple
 
- HC_SubType_Tex0
 
- HC_SubType_Tex1
 
- HC_SubType_TexGeneral
 
- HC_SubType_TexPalette0
 
- HC_SubType_TexPalette1
 
- HC_USBCMD
 
- HC_USBSTS
 
- HC_VER
 
- HC_VERSION
 
- HC_XA_0
 
- HC_XA_Adst
 
- HC_XA_Asrc
 
- HC_XA_Fog
 
- HC_XA_HABLFRA
 
- HC_XA_HABLRA
 
- HC_XA_InvOPA
 
- HC_XA_OPA
 
- HC_XA_OPAp5
 
- HC_XA_maxAsrcAdst
 
- HC_XA_maxAsrcFog
 
- HC_XA_minAsrcAdst
 
- HC_XA_minAsrcFog
 
- HC_XA_minAsrcInvAdst
 
- HC_XC_Adst
 
- HC_XC_Asrc
 
- HC_XC_Cdst
 
- HC_XC_Csrc
 
- HC_XC_Fog
 
- HC_XC_HABLRC
 
- HC_XC_InvOPC
 
- HC_XC_OPC
 
- HC_XC_OPCp5
 
- HC_XC_maxSrcDst
 
- HC_XC_mimAsrcInvAdst
 
- HC_XC_minSrcDst
 
- HC_XTA_Acur
 
- HC_XTA_Adif
 
- HC_XTA_Atex
 
- HC_XTA_Atexnext
 
- HC_XTA_Fog
 
- HC_XTA_HTXnTBLRA
 
- HC_XTA_InvTOPA
 
- HC_XTA_TOPA
 
- HC_XTA_TOPAp5
 
- HC_XTC_0
 
- HC_XTC_Acur
 
- HC_XTC_Adif
 
- HC_XTC_Atex
 
- HC_XTC_Cbias
 
- HC_XTC_Ctexnext
 
- HC_XTC_Cur
 
- HC_XTC_Dif
 
- HC_XTC_Fog
 
- HC_XTC_HTXnTBLRC
 
- HC_XTC_InvCbias
 
- HC_XTC_InvTOPC
 
- HC_XTC_Spec
 
- HC_XTC_TOPC
 
- HC_XTC_TOPCp5
 
- HC_XTC_Tex
 
- HC_ZWCFire_MASK
 
- HCuPINT
 
- HCuPINTENB
 
- HCuPINT_AIIEOT
 
- HCuPINT_ATL
 
- HCuPINT_CLKRDY
 
- HCuPINT_EOT
 
- HCuPINT_INTL
 
- HCuPINT_ISTL0
 
- HCuPINT_ISTL1
 
- HCuPINT_OPR
 
- HCuPINT_OTG
 
- HCuPINT_SOF
 
- HCuPINT_SUSP
 
- HD1
 
- HD64461_BBTDHR
 
- HD64461_BBTDSARH
 
- HD64461_BBTDSARL
 
- HD64461_BBTDWR
 
- HD64461_BBTMARH
 
- HD64461_BBTMARL
 
- HD64461_BBTMDR
 
- HD64461_BBTPARH
 
- HD64461_BBTPARL
 
- HD64461_BBTROPR
 
- HD64461_BBTSSARH
 
- HD64461_BBTSSARL
 
- HD64461_CPTRAR
 
- HD64461_CPTRDR
 
- HD64461_CPTWAR
 
- HD64461_CPTWDR
 
- HD64461_GPACR
 
- HD64461_GPADR
 
- HD64461_GPADR_PCMCIA0
 
- HD64461_GPADR_SPEAKER
 
- HD64461_GPAICR
 
- HD64461_GPAISR
 
- HD64461_GPBCR
 
- HD64461_GPBDR
 
- HD64461_GPBDR_LCDOFF
 
- HD64461_GPBDR_LCD_CONTRAST_MASK
 
- HD64461_GPBDR_LED_RED
 
- HD64461_GPBICR
 
- HD64461_GPBISR
 
- HD64461_GPCCR
 
- HD64461_GPCDR
 
- HD64461_GPCICR
 
- HD64461_GPCISR
 
- HD64461_GPDCR
 
- HD64461_GPDDR
 
- HD64461_GPDICR
 
- HD64461_GPDISR
 
- HD64461_GRCFGR
 
- HD64461_GRCFGR_ACCRESET
 
- HD64461_GRCFGR_ACCSTART_BITBLT
 
- HD64461_GRCFGR_ACCSTART_LINE
 
- HD64461_GRCFGR_ACCSTATUS
 
- HD64461_GRCFGR_COLORDEPTH16
 
- HD64461_GRCFGR_COLORDEPTH8
 
- HD64461_GRDOR
 
- HD64461_GRSCR
 
- HD64461_IOBASE
 
- HD64461_IO_OFFSET
 
- HD64461_IRQBASE
 
- HD64461_IRQ_AFE
 
- HD64461_IRQ_GPIO
 
- HD64461_IRQ_IRDA
 
- HD64461_IRQ_NUM
 
- HD64461_IRQ_PCC0
 
- HD64461_IRQ_PCC1
 
- HD64461_IRQ_TMU0
 
- HD64461_IRQ_TMU1
 
- HD64461_IRQ_UART
 
- HD64461_LCDCBAR
 
- HD64461_LCDCCR
 
- HD64461_LCDCCR_EPON
 
- HD64461_LCDCCR_MOFF
 
- HD64461_LCDCCR_REFSEL
 
- HD64461_LCDCCR_SPON
 
- HD64461_LCDCCR_STBACK
 
- HD64461_LCDCCR_STREQ
 
- HD64461_LCDCLOR
 
- HD64461_LDHNCR
 
- HD64461_LDHNSR
 
- HD64461_LDR1
 
- HD64461_LDR1_DINV
 
- HD64461_LDR1_DON
 
- HD64461_LDR2
 
- HD64461_LDR3
 
- HD64461_LDVNDR
 
- HD64461_LDVNTR
 
- HD64461_LDVSPR
 
- HD64461_LNAXLR
 
- HD64461_LNAXR
 
- HD64461_LNDGR
 
- HD64461_LNERTR
 
- HD64461_LNMDR
 
- HD64461_LNSARH
 
- HD64461_LNSARL
 
- HD64461_NIMR
 
- HD64461_NIRR
 
- HD64461_P0OCR
 
- HD64461_P1OCR
 
- HD64461_PCC0CSCIER
 
- HD64461_PCC0CSCR
 
- HD64461_PCC0GCR
 
- HD64461_PCC0ISR
 
- HD64461_PCC0SCR
 
- HD64461_PCC0_ATTR
 
- HD64461_PCC0_BASE
 
- HD64461_PCC0_COMM
 
- HD64461_PCC0_IO
 
- HD64461_PCC1CSCIER
 
- HD64461_PCC1CSCR
 
- HD64461_PCC1GCR
 
- HD64461_PCC1ISR
 
- HD64461_PCC1SCR
 
- HD64461_PCC1_ATTR
 
- HD64461_PCC1_BASE
 
- HD64461_PCC1_COMM
 
- HD64461_PCCCSCIER_BDE
 
- HD64461_PCCCSCIER_BWE
 
- HD64461_PCCCSCIER_CDE
 
- HD64461_PCCCSCIER_CRE
 
- HD64461_PCCCSCIER_IREQE_DISABLED
 
- HD64461_PCCCSCIER_IREQE_FALLING
 
- HD64461_PCCCSCIER_IREQE_LEVEL
 
- HD64461_PCCCSCIER_IREQE_MASK
 
- HD64461_PCCCSCIER_IREQE_RISING
 
- HD64461_PCCCSCIER_RE
 
- HD64461_PCCCSCIER_SCE
 
- HD64461_PCCCSCR_BD
 
- HD64461_PCCCSCR_BW
 
- HD64461_PCCCSCR_CDC
 
- HD64461_PCCCSCR_IREQ
 
- HD64461_PCCCSCR_RC
 
- HD64461_PCCCSCR_SC
 
- HD64461_PCCCSCR_SCDI
 
- HD64461_PCCCSCR_SRV1
 
- HD64461_PCCGCR_DRVE
 
- HD64461_PCCGCR_PA24
 
- HD64461_PCCGCR_PA25
 
- HD64461_PCCGCR_PCCR
 
- HD64461_PCCGCR_PCCT
 
- HD64461_PCCGCR_PMMOD
 
- HD64461_PCCGCR_REG
 
- HD64461_PCCGCR_VCC0
 
- HD64461_PCCISR_BVD1
 
- HD64461_PCCISR_BVD2
 
- HD64461_PCCISR_BVD_BATDEAD1
 
- HD64461_PCCISR_BVD_BATDEAD2
 
- HD64461_PCCISR_BVD_BATGOOD
 
- HD64461_PCCISR_BVD_BATWARN
 
- HD64461_PCCISR_BVD_MASK
 
- HD64461_PCCISR_CD1
 
- HD64461_PCCISR_CD2
 
- HD64461_PCCISR_MWP
 
- HD64461_PCCISR_PCD_MASK
 
- HD64461_PCCISR_READY
 
- HD64461_PCCISR_VS1
 
- HD64461_PCCISR_VS2
 
- HD64461_PCCSCR_SWP
 
- HD64461_PCCSCR_VCC1
 
- HD64461_PCC_WINDOW
 
- HD64461_PGCR
 
- HD64461_SCPUCR
 
- HD64461_STBCR
 
- HD64461_STBCR_CKIO_STBY
 
- HD64461_STBCR_SAFECKE_IST
 
- HD64461_STBCR_SAFECKE_OST
 
- HD64461_STBCR_SAFEST
 
- HD64461_STBCR_SIRST
 
- HD64461_STBCR_SLCDST
 
- HD64461_STBCR_SLCKE_IST
 
- HD64461_STBCR_SLCKE_OST
 
- HD64461_STBCR_SMIAST
 
- HD64461_STBCR_SPC0ST
 
- HD64461_STBCR_SPC1ST
 
- HD64461_STBCR_STM0ST
 
- HD64461_STBCR_STM1ST
 
- HD64461_STBCR_SURTST
 
- HD64461_SYSCR
 
- HDA
 
- HDAC_ALT_ANALOG_DAI_ID
 
- HDAC_ANALOG_DAI_ID
 
- HDAC_DAI_COUNT
 
- HDAC_DIGITAL_DAI_ID
 
- HDAC_EXEC_CMD
 
- HDAC_EXT_STREAM_TYPE_COUPLED
 
- HDAC_EXT_STREAM_TYPE_HOST
 
- HDAC_EXT_STREAM_TYPE_LINK
 
- HDAC_MAX_CAPS
 
- HDAC_MSG_MAX
 
- HDAPS_BOTH_AXES
 
- HDAPS_DMI_MATCH_INVERT
 
- HDAPS_DMI_MATCH_NORMAL
 
- HDAPS_INPUT_FLAT
 
- HDAPS_INPUT_FUZZ
 
- HDAPS_LOW_PORT
 
- HDAPS_NR_PORTS
 
- HDAPS_POLL_INTERVAL
 
- HDAPS_PORT_KMACT
 
- HDAPS_PORT_STATE
 
- HDAPS_PORT_TEMP1
 
- HDAPS_PORT_TEMP2
 
- HDAPS_PORT_UNKNOWN
 
- HDAPS_PORT_XPOS
 
- HDAPS_PORT_XVAR
 
- HDAPS_PORT_YPOS
 
- HDAPS_PORT_YVAR
 
- HDAPS_X_AXIS
 
- HDAPS_Y_AXIS
 
- HDAR_DSP_ADDR_MASK
 
- HDAR_END
 
- HDAR_ERR
 
- HDAR_HOST_ADDR_MASK
 
- HDAR_MEMID_MASK
 
- HDAR_MEMID_OMNI_MEM
 
- HDAR_MEMID_SP_DEBUG
 
- HDAR_MEMID_SP_DMEM0
 
- HDAR_MEMID_SP_DMEM1
 
- HDAR_MEMID_SP_PMEM
 
- HDAT0
 
- HDAT1
 
- HDATA_RATE
 
- HDAT_FADUMP_CORE_INACTIVE
 
- HDAT_FADUMP_CPU_DATA_VER
 
- HDAT_FADUMP_REG_ID_CCR
 
- HDAT_FADUMP_REG_ID_MSR
 
- HDAT_FADUMP_REG_ID_NIP
 
- HDAT_FADUMP_REG_TYPE_GPR
 
- HDAT_FADUMP_REG_TYPE_SPR
 
- HDA_ADSP_ERROR_CODE_SKL
 
- HDA_ADSP_FW_STATUS_SKL
 
- HDA_ADSP_LOADER_BASE
 
- HDA_ADSP_SRAM0_BASE_SKL
 
- HDA_AMP_MUTE
 
- HDA_AMP_UNMUTE
 
- HDA_AMP_VAL_MIN_MUTE
 
- HDA_AMP_VOLMASK
 
- HDA_ANA_ANC_CTRL
 
- HDA_ANA_CFG
 
- HDA_ANA_SCALE_CTRL_CB
 
- HDA_ANA_SCALE_CTRL_CR
 
- HDA_ANA_SCALE_CTRL_Y
 
- HDA_ANA_SRC_C_CFG
 
- HDA_ANA_SRC_C_CFG_4X
 
- HDA_ANA_SRC_C_CFG_ALT_2X
 
- HDA_ANA_SRC_Y_CFG
 
- HDA_ANA_SRC_Y_CFG_4X
 
- HDA_ANA_SRC_Y_CFG_ALT_2X
 
- HDA_BAR0
 
- HDA_BAR0_FINAL_PROGRAM
 
- HDA_BAR0_INIT_PROGRAM
 
- HDA_BASE__INST0_SEG0
 
- HDA_BASE__INST0_SEG1
 
- HDA_BASE__INST0_SEG2
 
- HDA_BASE__INST0_SEG3
 
- HDA_BASE__INST0_SEG4
 
- HDA_BASE__INST1_SEG0
 
- HDA_BASE__INST1_SEG1
 
- HDA_BASE__INST1_SEG2
 
- HDA_BASE__INST1_SEG3
 
- HDA_BASE__INST1_SEG4
 
- HDA_BASE__INST2_SEG0
 
- HDA_BASE__INST2_SEG1
 
- HDA_BASE__INST2_SEG2
 
- HDA_BASE__INST2_SEG3
 
- HDA_BASE__INST2_SEG4
 
- HDA_BASE__INST3_SEG0
 
- HDA_BASE__INST3_SEG1
 
- HDA_BASE__INST3_SEG2
 
- HDA_BASE__INST3_SEG3
 
- HDA_BASE__INST3_SEG4
 
- HDA_BASE__INST4_SEG0
 
- HDA_BASE__INST4_SEG1
 
- HDA_BASE__INST4_SEG2
 
- HDA_BASE__INST4_SEG3
 
- HDA_BASE__INST4_SEG4
 
- HDA_BASE__INST5_SEG0
 
- HDA_BASE__INST5_SEG1
 
- HDA_BASE__INST5_SEG2
 
- HDA_BASE__INST5_SEG3
 
- HDA_BASE__INST5_SEG4
 
- HDA_BASE__INST6_SEG0
 
- HDA_BASE__INST6_SEG1
 
- HDA_BASE__INST6_SEG2
 
- HDA_BASE__INST6_SEG3
 
- HDA_BASE__INST6_SEG4
 
- HDA_BEEP_MODE_OFF
 
- HDA_BEEP_MODE_ON
 
- HDA_CFG_BAR0
 
- HDA_CFG_CMD
 
- HDA_CLFE
 
- HDA_CLK_CYCLES_PER_FRAME
 
- HDA_CODEC_ENTRY
 
- HDA_CODEC_EXT_ENTRY
 
- HDA_CODEC_IDX_CONTROLLER
 
- HDA_CODEC_ID_GENERIC
 
- HDA_CODEC_ID_GENERIC_HDMI
 
- HDA_CODEC_ID_SKIP_PROBE
 
- HDA_CODEC_MUTE
 
- HDA_CODEC_MUTE_BEEP
 
- HDA_CODEC_MUTE_BEEP_MONO
 
- HDA_CODEC_MUTE_BEEP_MONO_IDX
 
- HDA_CODEC_MUTE_IDX
 
- HDA_CODEC_MUTE_MONO
 
- HDA_CODEC_MUTE_MONO_IDX
 
- HDA_CODEC_REV_ENTRY
 
- HDA_CODEC_REV_EXT_ENTRY
 
- HDA_CODEC_VOLUME
 
- HDA_CODEC_VOLUME_IDX
 
- HDA_CODEC_VOLUME_MIN_MUTE
 
- HDA_CODEC_VOLUME_MONO
 
- HDA_CODEC_VOLUME_MONO_IDX
 
- HDA_COEFF_C_PH1_TAP123
 
- HDA_COEFF_C_PH1_TAP456
 
- HDA_COEFF_C_PH2_TAP123
 
- HDA_COEFF_C_PH2_TAP456
 
- HDA_COEFF_C_PH3_TAP123
 
- HDA_COEFF_C_PH3_TAP456
 
- HDA_COEFF_C_PH4_TAP123
 
- HDA_COEFF_C_PH4_TAP456
 
- HDA_COEFF_Y_PH1_TAP123
 
- HDA_COEFF_Y_PH1_TAP456
 
- HDA_COEFF_Y_PH2_TAP123
 
- HDA_COEFF_Y_PH2_TAP456
 
- HDA_COEFF_Y_PH3_TAP123
 
- HDA_COEFF_Y_PH3_TAP456
 
- HDA_COEFF_Y_PH4_TAP123
 
- HDA_COEFF_Y_PH4_TAP456
 
- HDA_COMPOSE_AMP_VAL
 
- HDA_COMPOSE_AMP_VAL_OFS
 
- HDA_CTL_BIND_MUTE
 
- HDA_CTL_WIDGET_MUTE
 
- HDA_CTL_WIDGET_VOL
 
- HDA_C_PA
 
- HDA_DEV_ASOC
 
- HDA_DEV_CORE
 
- HDA_DEV_LEGACY
 
- HDA_DIG_ANALOG_DUP
 
- HDA_DIG_EXCLUSIVE
 
- HDA_DIG_NONE
 
- HDA_DISABLE_INTR
 
- HDA_DSP_ADSPCS_CPA_MASK
 
- HDA_DSP_ADSPCS_CPA_SHIFT
 
- HDA_DSP_ADSPCS_CRST_MASK
 
- HDA_DSP_ADSPCS_CRST_SHIFT
 
- HDA_DSP_ADSPCS_CSTALL_MASK
 
- HDA_DSP_ADSPCS_CSTALL_SHIFT
 
- HDA_DSP_ADSPCS_SPA_MASK
 
- HDA_DSP_ADSPCS_SPA_SHIFT
 
- HDA_DSP_ADSPIC_CL_DMA
 
- HDA_DSP_ADSPIC_IPC
 
- HDA_DSP_ADSPIS_CL_DMA
 
- HDA_DSP_ADSPIS_IPC
 
- HDA_DSP_BAR
 
- HDA_DSP_BASEFW_TIMEOUT_US
 
- HDA_DSP_BDL_SIZE
 
- HDA_DSP_CL_TRIGGER_TIMEOUT
 
- HDA_DSP_CORE_MASK
 
- HDA_DSP_CTRL_RESET_TIMEOUT
 
- HDA_DSP_DRSM_BAR
 
- HDA_DSP_GEN_BASE
 
- HDA_DSP_HDA_BAR
 
- HDA_DSP_INIT_TIMEOUT_US
 
- HDA_DSP_IPC_BASE
 
- HDA_DSP_IPC_PURGE_FW
 
- HDA_DSP_MAX_BDL_ENTRIES
 
- HDA_DSP_MAX_BE_DAI_LINKS
 
- HDA_DSP_MBOX_OFFSET
 
- HDA_DSP_MBOX_UPLINK_OFFSET
 
- HDA_DSP_PANIC_OFFSET
 
- HDA_DSP_PD_TIMEOUT
 
- HDA_DSP_PP_BAR
 
- HDA_DSP_PU_TIMEOUT
 
- HDA_DSP_REG_ADSPCS
 
- HDA_DSP_REG_ADSPIC
 
- HDA_DSP_REG_ADSPIC2
 
- HDA_DSP_REG_ADSPIS
 
- HDA_DSP_REG_ADSPIS2
 
- HDA_DSP_REG_HIPCCTL
 
- HDA_DSP_REG_HIPCCTL_BUSY
 
- HDA_DSP_REG_HIPCCTL_DONE
 
- HDA_DSP_REG_HIPCI
 
- HDA_DSP_REG_HIPCIE
 
- HDA_DSP_REG_HIPCIE_DONE
 
- HDA_DSP_REG_HIPCIE_MSG_MASK
 
- HDA_DSP_REG_HIPCI_BUSY
 
- HDA_DSP_REG_HIPCI_MSG_MASK
 
- HDA_DSP_REG_HIPCT
 
- HDA_DSP_REG_HIPCTE
 
- HDA_DSP_REG_HIPCTE_MSG_MASK
 
- HDA_DSP_REG_HIPCT_BUSY
 
- HDA_DSP_REG_HIPCT_MSG_MASK
 
- HDA_DSP_REG_POLL_INTERVAL_US
 
- HDA_DSP_RESET_TIMEOUT_US
 
- HDA_DSP_ROM_API_PTR_INVALID
 
- HDA_DSP_ROM_BASEFW_INCOMPAT
 
- HDA_DSP_ROM_BASE_FW_NOT_FOUND
 
- HDA_DSP_ROM_CSE_ERROR
 
- HDA_DSP_ROM_CSE_VALIDATION_FAILED
 
- HDA_DSP_ROM_CSE_WRONG_RESPONSE
 
- HDA_DSP_ROM_FW_ENTERED
 
- HDA_DSP_ROM_FW_FW_LOADED
 
- HDA_DSP_ROM_FW_MANIFEST_LOADED
 
- HDA_DSP_ROM_IMR_TO_SMALL
 
- HDA_DSP_ROM_INIT
 
- HDA_DSP_ROM_IPC_FATAL_ERROR
 
- HDA_DSP_ROM_KERNEL_EXCEPTION
 
- HDA_DSP_ROM_L2_CACHE_ERROR
 
- HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL
 
- HDA_DSP_ROM_MEMORY_HOLE_ECC
 
- HDA_DSP_ROM_NULL_FW_ENTRY
 
- HDA_DSP_ROM_RFW_START
 
- HDA_DSP_ROM_STS_MASK
 
- HDA_DSP_ROM_UNEXPECTED_RESET
 
- HDA_DSP_ROM_UNHANDLED_INTERRUPT
 
- HDA_DSP_ROM_USER_EXCEPTION
 
- HDA_DSP_SPIB_BAR
 
- HDA_DSP_SPIB_DISABLE
 
- HDA_DSP_SPIB_ENABLE
 
- HDA_DSP_SRAM_REG_FW_END
 
- HDA_DSP_SRAM_REG_FW_STATUS
 
- HDA_DSP_SRAM_REG_FW_TRACEP
 
- HDA_DSP_SRAM_REG_ROM_ERROR
 
- HDA_DSP_SRAM_REG_ROM_STATUS
 
- HDA_DSP_STACK_DUMP_SIZE
 
- HDA_DSP_STREAM_RESET_TIMEOUT
 
- HDA_DSP_STREAM_RUN_TIMEOUT
 
- HDA_DSP_WAIT_TIMEOUT
 
- HDA_ENABLE_BUS_MASTER
 
- HDA_ENABLE_IO_SPACE
 
- HDA_ENABLE_MEM_SPACE
 
- HDA_ENABLE_SERR
 
- HDA_FIXUP_ACT_BUILD
 
- HDA_FIXUP_ACT_FREE
 
- HDA_FIXUP_ACT_INIT
 
- HDA_FIXUP_ACT_PRE_PROBE
 
- HDA_FIXUP_ACT_PROBE
 
- HDA_FIXUP_FUNC
 
- HDA_FIXUP_ID_NOT_SET
 
- HDA_FIXUP_ID_NO_FIXUP
 
- HDA_FIXUP_INVALID
 
- HDA_FIXUP_PINCTLS
 
- HDA_FIXUP_PINS
 
- HDA_FIXUP_VERBS
 
- HDA_FPCI_BAR0_START
 
- HDA_FRONT
 
- HDA_FW_BOOT_ATTEMPTS
 
- HDA_GEN_PCM_ACT_CLEANUP
 
- HDA_GEN_PCM_ACT_CLOSE
 
- HDA_GEN_PCM_ACT_OPEN
 
- HDA_GEN_PCM_ACT_PREPARE
 
- HDA_GSM_CMD_OFFSET_BITS
 
- HDA_GSM_OFFSET_BITS
 
- HDA_GSM_RSP_OFFSET_BITS
 
- HDA_HINT_STEREO_MIX_AUTO
 
- HDA_HINT_STEREO_MIX_DISABLE
 
- HDA_HINT_STEREO_MIX_ENABLE
 
- HDA_HWDEP_VERSION
 
- HDA_IDISP_CODEC
 
- HDA_INPUT
 
- HDA_IOCTL_GET_WCAP
 
- HDA_IOCTL_PVERSION
 
- HDA_IOCTL_VERB_WRITE
 
- HDA_IPFS_CONFIG
 
- HDA_IPFS_EN_FPCI
 
- HDA_IPFS_EN_INTR
 
- HDA_IPFS_FPCI_BAR0
 
- HDA_IPFS_INTR_MASK
 
- HDA_JACK_NOT_PRESENT
 
- HDA_JACK_PHANTOM
 
- HDA_JACK_PRESENT
 
- HDA_MAX
 
- HDA_MAX_CODECS
 
- HDA_MAX_CODEC_ADDRESS
 
- HDA_MAX_CONNECTIONS
 
- HDA_MAX_CVTS
 
- HDA_MAX_CYCLE_OFFSET
 
- HDA_MAX_CYCLE_READ_RETRY
 
- HDA_MAX_CYCLE_VALUE
 
- HDA_MAX_NUM_INPUTS
 
- HDA_MAX_OUTS
 
- HDA_MAX_PORTS
 
- HDA_MONO
 
- HDA_NID_ITEM_AMP
 
- HDA_OUTPUT
 
- HDA_PCM_NTYPES
 
- HDA_PCM_TYPE_AUDIO
 
- HDA_PCM_TYPE_HDMI
 
- HDA_PCM_TYPE_MODEM
 
- HDA_PCM_TYPE_SPDIF
 
- HDA_PINCFG_HEADPHONE_MIC
 
- HDA_PINCFG_HEADSET_MIC
 
- HDA_PINCFG_NO_HP_FIXUP
 
- HDA_PINCFG_NO_LO_FIXUP
 
- HDA_QUAD
 
- HDA_RATE
 
- HDA_REAR
 
- HDA_REG_NID_SHIFT
 
- HDA_REG_VAL_SHIFT
 
- HDA_REG_VERB_SHIFT
 
- HDA_RW_NO_RESPONSE_FALLBACK
 
- HDA_SEQ_ID_BITS
 
- HDA_SIDE
 
- HDA_SST_CFG_MAX
 
- HDA_STEREO
 
- HDA_SUBDEV_AMP_FLAG
 
- HDA_SUBDEV_NID_FLAG
 
- HDA_SYNC_AWGI
 
- HDA_UNSOL_QUEUE_SIZE
 
- HDA_VERB
 
- HDA_VMUTE_FOLLOW_MASTER
 
- HDA_VMUTE_OFF
 
- HDA_VMUTE_ON
 
- HDA_VS_INTEL_EM2
 
- HDA_VS_INTEL_EM2_L1SEN
 
- HDB
 
- HDC100X_REG_CONFIG
 
- HDC100X_REG_CONFIG_ACQ_MODE
 
- HDC100X_REG_CONFIG_HEATER_EN
 
- HDC100X_REG_HUMIDITY
 
- HDC100X_REG_TEMP
 
- HDCP2_AUTH_DDI
 
- HDCP2_CTL_DDI
 
- HDCP2_LC_RETRY_CNT
 
- HDCP2_STATUS_DDI
 
- HDCP2_TX_IS_KM_STORED_EVENT
 
- HDCP2_TX_STORE_KM_EVENT
 
- HDCP_11
 
- HDCP_2_2_AKE_INIT
 
- HDCP_2_2_AKE_NO_STORED_KM
 
- HDCP_2_2_AKE_SEND_CERT
 
- HDCP_2_2_AKE_SEND_HPRIME
 
- HDCP_2_2_AKE_SEND_PAIRING_INFO
 
- HDCP_2_2_AKE_STORED_KM
 
- HDCP_2_2_CERT_TIMEOUT_MS
 
- HDCP_2_2_DCP_LLC_SIG_LEN
 
- HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN
 
- HDCP_2_2_DEPTH
 
- HDCP_2_2_DEV_COUNT_HI
 
- HDCP_2_2_DEV_COUNT_LO
 
- HDCP_2_2_DP_HDCP_CAPABLE
 
- HDCP_2_2_DP_LPRIME_TIMEOUT_MS
 
- HDCP_2_2_DP_RXSTATUS_H_PRIME
 
- HDCP_2_2_DP_RXSTATUS_LEN
 
- HDCP_2_2_DP_RXSTATUS_LINK_FAILED
 
- HDCP_2_2_DP_RXSTATUS_PAIRING
 
- HDCP_2_2_DP_RXSTATUS_READY
 
- HDCP_2_2_DP_RXSTATUS_REAUTH_REQ
 
- HDCP_2_2_ERRATA_DP_STREAM_TYPE
 
- HDCP_2_2_E_DKEY_KS_LEN
 
- HDCP_2_2_E_KH_KM_LEN
 
- HDCP_2_2_E_KH_KM_M_LEN
 
- HDCP_2_2_E_KPUB_KM_LEN
 
- HDCP_2_2_HDCP1_DEVICE_CONNECTED
 
- HDCP_2_2_HDCP_2_0_REP_CONNECTED
 
- HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS
 
- HDCP_2_2_HDMI_REG_DBG_OFFSET
 
- HDCP_2_2_HDMI_REG_RD_MSG_OFFSET
 
- HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET
 
- HDCP_2_2_HDMI_REG_VER_OFFSET
 
- HDCP_2_2_HDMI_REG_WR_MSG_OFFSET
 
- HDCP_2_2_HDMI_RXSTATUS_LEN
 
- HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI
 
- HDCP_2_2_HDMI_RXSTATUS_READY
 
- HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ
 
- HDCP_2_2_HDMI_SUPPORT_MASK
 
- HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS
 
- HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS
 
- HDCP_2_2_H_PRIME_LEN
 
- HDCP_2_2_K_PUB_RX_EXP_E_LEN
 
- HDCP_2_2_K_PUB_RX_LEN
 
- HDCP_2_2_K_PUB_RX_MOD_N_LEN
 
- HDCP_2_2_LC_INIT
 
- HDCP_2_2_LC_SEND_LPRIME
 
- HDCP_2_2_L_PRIME_LEN
 
- HDCP_2_2_MAX_CASCADE_EXCEEDED
 
- HDCP_2_2_MAX_CONTENT_STREAMS_CNT
 
- HDCP_2_2_MAX_DEVICE_COUNT
 
- HDCP_2_2_MAX_DEVS_EXCEEDED
 
- HDCP_2_2_MPRIME_LEN
 
- HDCP_2_2_NULL_MSG
 
- HDCP_2_2_PAIRING_TIMEOUT_MS
 
- HDCP_2_2_RECEIVER_IDS_MAX_LEN
 
- HDCP_2_2_RECEIVER_ID_LEN
 
- HDCP_2_2_RECVID_LIST_TIMEOUT_MS
 
- HDCP_2_2_REP_SEND_ACK
 
- HDCP_2_2_REP_SEND_RECVID_LIST
 
- HDCP_2_2_REP_STREAM_MANAGE
 
- HDCP_2_2_REP_STREAM_READY
 
- HDCP_2_2_RIV_LEN
 
- HDCP_2_2_RN_LEN
 
- HDCP_2_2_RRX_LEN
 
- HDCP_2_2_RTX_LEN
 
- HDCP_2_2_RXCAPS_LEN
 
- HDCP_2_2_RXINFO_LEN
 
- HDCP_2_2_RX_CAPS_VERSION_VAL
 
- HDCP_2_2_RX_REPEATER
 
- HDCP_2_2_SEQ_NUM_LEN
 
- HDCP_2_2_SEQ_NUM_MAX
 
- HDCP_2_2_SKE_SEND_EKS
 
- HDCP_2_2_STREAM_READY_TIMEOUT_MS
 
- HDCP_2_2_TXCAP_MASK_LEN
 
- HDCP_2_2_V_PRIME_HALF_LEN
 
- HDCP_AKSV_HI
 
- HDCP_AKSV_LO
 
- HDCP_AKSV_SEND_TRIGGER
 
- HDCP_API_VERSION
 
- HDCP_CIPHER_CONFIG
 
- HDCP_CLEAR_KEYS_TRIGGER
 
- HDCP_CONF_AUTH_AND_ENC
 
- HDCP_CONF_CAPTURE_AN
 
- HDCP_CRYPTO_CONFIG
 
- HDCP_DDC_WRITE_MAX_BYTE_NUM
 
- HDCP_DDIA_REP_PRESENT
 
- HDCP_DDIA_SHA1_M0
 
- HDCP_DDIB_REP_PRESENT
 
- HDCP_DDIB_SHA1_M0
 
- HDCP_DDIC_REP_PRESENT
 
- HDCP_DDIC_SHA1_M0
 
- HDCP_DDID_REP_PRESENT
 
- HDCP_DDID_SHA1_M0
 
- HDCP_DDIE_REP_PRESENT
 
- HDCP_DDIE_SHA1_M0
 
- HDCP_DDIF_REP_PRESENT
 
- HDCP_DDIF_SHA1_M0
 
- HDCP_DE_COMP_AND
 
- HDCP_DE_COMP_CH0
 
- HDCP_DE_COMP_CH1
 
- HDCP_DE_COMP_CH2
 
- HDCP_DE_COMP_CH3
 
- HDCP_DE_COMP_MASK
 
- HDCP_DE_COMP_MIXED
 
- HDCP_DE_COMP_OR
 
- HDCP_DE_FILTER_MASK
 
- HDCP_DE_FILTER_SHIFT
 
- HDCP_DE_MODE_MASK
 
- HDCP_DE_MODE_SHIFT
 
- HDCP_DE_REGEN_EN
 
- HDCP_EP_FIL_CTL_MASK
 
- HDCP_EP_FIL_CTL_SHIFT
 
- HDCP_EP_FIL_HS_MASK
 
- HDCP_EP_FIL_HS_SHIFT
 
- HDCP_EP_FIL_VS_MASK
 
- HDCP_EP_FIL_VS_SHIFT
 
- HDCP_FAST
 
- HDCP_FAST_REAUTH
 
- HDCP_FUNC_EN_N
 
- HDCP_FUSE_DONE
 
- HDCP_FUSE_ERROR
 
- HDCP_FUSE_IN_PROGRESS
 
- HDCP_GET_SRM_STATUS
 
- HDCP_HDMI
 
- HDCP_INT
 
- HDCP_INTM
 
- HDCP_INT_STATUS_MASK
 
- HDCP_KEYS_STATE_AKSV_NOT_VALID
 
- HDCP_KEYS_STATE_CHECKING
 
- HDCP_KEYS_STATE_CHKSUM_MISMATCH
 
- HDCP_KEYS_STATE_NOT_CHECKED
 
- HDCP_KEYS_STATE_NO_KEYS
 
- HDCP_KEYS_STATE_PROD_AKSV
 
- HDCP_KEYS_STATE_RESERVED
 
- HDCP_KEYS_STATE_VALID
 
- HDCP_KEY_CONF
 
- HDCP_KEY_LOAD_DONE
 
- HDCP_KEY_LOAD_STATUS
 
- HDCP_KEY_LOAD_TRIGGER
 
- HDCP_KEY_STATUS
 
- HDCP_KH_LEN
 
- HDCP_KSV_LSB
 
- HDCP_KSV_MSB
 
- HDCP_LINK_INTEGRITY_FAILURE
 
- HDCP_LINK_PROTECTED
 
- HDCP_MODE
 
- HDCP_M_LEN
 
- HDCP_PORT_ADDR
 
- HDCP_PORT_TYPE_CPDP
 
- HDCP_PORT_TYPE_INTEGRATED
 
- HDCP_PORT_TYPE_INVALID
 
- HDCP_PORT_TYPE_LSPCON
 
- HDCP_PROTOCOL_DP
 
- HDCP_PROTOCOL_HDMI
 
- HDCP_PROTOCOL_INVALID
 
- HDCP_RDY
 
- HDCP_READY
 
- HDCP_REAUTH_REQUEST
 
- HDCP_REG1
 
- HDCP_REG2
 
- HDCP_REG3
 
- HDCP_REG_DISABLE
 
- HDCP_REG_ENABLE
 
- HDCP_REPEATER
 
- HDCP_REP_CTL
 
- HDCP_REVISION
 
- HDCP_SEND_SRM_FRAGMENT
 
- HDCP_SHA1_BUSY
 
- HDCP_SHA1_COMPLETE
 
- HDCP_SHA1_COMPLETE_HASH
 
- HDCP_SHA1_READY
 
- HDCP_SHA1_TEXT_0
 
- HDCP_SHA1_TEXT_16
 
- HDCP_SHA1_TEXT_24
 
- HDCP_SHA1_TEXT_32
 
- HDCP_SHA1_TEXT_8
 
- HDCP_SHA1_V_MATCH
 
- HDCP_SHA_TEXT
 
- HDCP_SHA_V_PRIME
 
- HDCP_SHA_V_PRIME_H0
 
- HDCP_SHA_V_PRIME_H1
 
- HDCP_SHA_V_PRIME_H2
 
- HDCP_SHA_V_PRIME_H3
 
- HDCP_SHA_V_PRIME_H4
 
- HDCP_STATE_AUTHENTICATED
 
- HDCP_STATE_AUTHENTICATING
 
- HDCP_STATE_AUTH_FAILED
 
- HDCP_STATE_INACTIVE
 
- HDCP_STATE_NO_AKSV
 
- HDCP_STATUS_AN_READY
 
- HDCP_STATUS_AUTH
 
- HDCP_STATUS_CIPHER
 
- HDCP_STATUS_ENC
 
- HDCP_STATUS_FRAME_CNT
 
- HDCP_STATUS_R0_READY
 
- HDCP_STATUS_RI_MATCH
 
- HDCP_STATUS_STREAM_A_ENC
 
- HDCP_STATUS_STREAM_B_ENC
 
- HDCP_STATUS_STREAM_C_ENC
 
- HDCP_STATUS_STREAM_D_ENC
 
- HDCP_STREAM_TYPE0
 
- HDCP_STREAM_TYPE1
 
- HDCP_TOPOLOGY_CHANGE
 
- HDCP_TX_IS_RECEIVER_ID_VALID_EVENT
 
- HDCP_TX_STATUS_EVENT
 
- HDCP_VIDEO_MUTE
 
- HDCR
 
- HDCR_COUNT_MASK
 
- HDCR_COUNT_SHIFT
 
- HDCR_DH
 
- HDCR_DMS_1024_DWORDS
 
- HDCR_DMS_128_DWORDS
 
- HDCR_DMS_16_DWORDS
 
- HDCR_DMS_256_DWORDS
 
- HDCR_DMS_32_DWORDS
 
- HDCR_DMS_512_DWORDS
 
- HDCR_DMS_64_DWORDS
 
- HDCR_DMS_LINEAR
 
- HDCR_DMS_MASK
 
- HDCR_DONE
 
- HDCR_HPME
 
- HDCR_HPMN_MASK
 
- HDCR_OPT
 
- HDCR_SH
 
- HDCR_SMS_1024_DWORDS
 
- HDCR_SMS_128_DWORDS
 
- HDCR_SMS_16_DWORDS
 
- HDCR_SMS_256_DWORDS
 
- HDCR_SMS_32_DWORDS
 
- HDCR_SMS_512_DWORDS
 
- HDCR_SMS_64_DWORDS
 
- HDCR_SMS_LINEAR
 
- HDCR_SMS_MASK
 
- HDCR_TDA
 
- HDCR_TDE
 
- HDCR_TDOSA
 
- HDCR_TDRA
 
- HDCR_TPM
 
- HDCR_TPMCR
 
- HDCR_WBD
 
- HDCR_WBS
 
- HDCS00_CONFIG
 
- HDCS00_CONTROL
 
- HDCS00_SROWEXPH
 
- HDCS00_SROWEXPL
 
- HDCS20_CONFIG
 
- HDCS20_CONTROL
 
- HDCS20_ERROR
 
- HDCS20_HBLANK
 
- HDCS20_ICTRL2
 
- HDCS20_ITMG2
 
- HDCS20_SROWEXP
 
- HDCS20_VBLANK
 
- HDCS_1020_BOTTOM_Y_SKIP
 
- HDCS_1020_DEF_HEIGHT
 
- HDCS_1020_DEF_WIDTH
 
- HDCS_1X00_DEF_HEIGHT
 
- HDCS_1X00_DEF_WIDTH
 
- HDCS_ADCCTRL
 
- HDCS_ADC_START_SIG_DUR
 
- HDCS_BFRAC
 
- HDCS_BRATE
 
- HDCS_CLK_FREQ_MHZ
 
- HDCS_DEFAULT_EXPOSURE
 
- HDCS_DEFAULT_GAIN
 
- HDCS_ERECPGA
 
- HDCS_EROCPGA
 
- HDCS_FWCOL
 
- HDCS_FWROW
 
- HDCS_ICTRL
 
- HDCS_IDENT
 
- HDCS_IMASK
 
- HDCS_ITMG
 
- HDCS_LWCOL
 
- HDCS_LWROW
 
- HDCS_ORECPGA
 
- HDCS_OROCPGA
 
- HDCS_PCTRL
 
- HDCS_PDRV
 
- HDCS_REG_CONFIG
 
- HDCS_REG_CONTROL
 
- HDCS_ROWEXPH
 
- HDCS_ROWEXPL
 
- HDCS_RUN_ENABLE
 
- HDCS_SLEEP_MODE
 
- HDCS_STATE_IDLE
 
- HDCS_STATE_RUN
 
- HDCS_STATE_SLEEP
 
- HDCS_STATUS
 
- HDCS_TCTRL
 
- HDCTBL_SIZE
 
- HDC_BARRIER_PERFORMANCE_DISABLE
 
- HDC_CHICKEN0
 
- HDC_DONOT_FETCH_MEM_WHEN_MASKED
 
- HDC_FENCE_DEST_SLM_DISABLE
 
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
 
- HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
 
- HDC_FORCE_NON_COHERENT
 
- HDE
 
- HDELAY_LO
 
- HDER
 
- HDEXAR_AUX_SET_POTS
 
- HDEXAR_CAL_A_TO_D
 
- HDEXAR_CLEAR_PEAKS
 
- HDEXAR_IN_SET_POTS
 
- HDEXAR_MIC_SET_POTS
 
- HDEXAR_RD_EXT_DSP_BITS
 
- HDEXAR_READ_DAT_IN
 
- HDEXAR_SET_ANA_IN
 
- HDEXAR_SET_DAT_IN
 
- HDEXAR_SET_SYNTH_44
 
- HDEXAR_SET_SYNTH_48
 
- HDEXAR_SET_SYNTH_IN
 
- HDEX_AUX_REQ
 
- HDEX_BASE
 
- HDEX_MIDI_IN_START
 
- HDEX_MIDI_IN_STOP
 
- HDEX_MIDI_OUT_START
 
- HDEX_MIDI_OUT_STOP
 
- HDEX_PLAY_PAUSE
 
- HDEX_PLAY_RESUME
 
- HDEX_PLAY_START
 
- HDEX_PLAY_STOP
 
- HDEX_RECORD_START
 
- HDEX_RECORD_STOP
 
- HDE_ACLK
 
- HDFAR
 
- HDI
 
- HDIO_DRIVE_CMD
 
- HDIO_DRIVE_CMD_AEB
 
- HDIO_DRIVE_CMD_HDR_SIZE
 
- HDIO_DRIVE_HOB_HDR_SIZE
 
- HDIO_DRIVE_RESET
 
- HDIO_DRIVE_TASK
 
- HDIO_DRIVE_TASKFILE
 
- HDIO_DRIVE_TASK_HDR_SIZE
 
- HDIO_GETGEO
 
- HDIO_GET_32BIT
 
- HDIO_GET_ACOUSTIC
 
- HDIO_GET_ADDRESS
 
- HDIO_GET_BUSSTATE
 
- HDIO_GET_DMA
 
- HDIO_GET_IDENTITY
 
- HDIO_GET_KEEPSETTINGS
 
- HDIO_GET_MULTCOUNT
 
- HDIO_GET_NICE
 
- HDIO_GET_NOWERR
 
- HDIO_GET_QDMA
 
- HDIO_GET_UNMASKINTR
 
- HDIO_GET_WCACHE
 
- HDIO_OBSOLETE_IDENTITY
 
- HDIO_SCAN_HWIF
 
- HDIO_SET_32BIT
 
- HDIO_SET_ACOUSTIC
 
- HDIO_SET_ADDRESS
 
- HDIO_SET_BUSSTATE
 
- HDIO_SET_DMA
 
- HDIO_SET_KEEPSETTINGS
 
- HDIO_SET_MULTCOUNT
 
- HDIO_SET_NICE
 
- HDIO_SET_NOWERR
 
- HDIO_SET_PIO_MODE
 
- HDIO_SET_QDMA
 
- HDIO_SET_UNMASKINTR
 
- HDIO_SET_WCACHE
 
- HDIO_SET_XFER
 
- HDIO_TRISTATE_HWIF
 
- HDIO_UNREGISTER_HWIF
 
- HDISPR
 
- HDLCDRVCTL_CALIBRATE
 
- HDLCDRVCTL_DRIVERNAME
 
- HDLCDRVCTL_GETBITS
 
- HDLCDRVCTL_GETCHANNELPAR
 
- HDLCDRVCTL_GETMODE
 
- HDLCDRVCTL_GETMODEMPAR
 
- HDLCDRVCTL_GETSAMPLES
 
- HDLCDRVCTL_GETSTAT
 
- HDLCDRVCTL_MODELIST
 
- HDLCDRVCTL_MODEMPARMASK
 
- HDLCDRVCTL_OLDGETSTAT
 
- HDLCDRVCTL_SETCHANNELPAR
 
- HDLCDRVCTL_SETMODE
 
- HDLCDRVCTL_SETMODEMPAR
 
- HDLCDRV_BITBUFFER
 
- HDLCDRV_DEBUG
 
- HDLCDRV_HDLCBUFFER
 
- HDLCDRV_LOOPBACK
 
- HDLCDRV_MAGIC
 
- HDLCDRV_MAXFLEN
 
- HDLCDRV_PARMASK_DMA
 
- HDLCDRV_PARMASK_DMA2
 
- HDLCDRV_PARMASK_IOBASE
 
- HDLCDRV_PARMASK_IRQ
 
- HDLCDRV_PARMASK_MIDIIOBASE
 
- HDLCDRV_PARMASK_PARIOBASE
 
- HDLCDRV_PARMASK_SERIOBASE
 
- HDLCD_BUS_BURST_1
 
- HDLCD_BUS_BURST_16
 
- HDLCD_BUS_BURST_2
 
- HDLCD_BUS_BURST_4
 
- HDLCD_BUS_BURST_8
 
- HDLCD_BUS_BURST_MASK
 
- HDLCD_BUS_BURST_NONE
 
- HDLCD_BUS_MAX_OUTSTAND
 
- HDLCD_BYTES_PER_PIXEL_MASK
 
- HDLCD_COMMAND_DISABLE
 
- HDLCD_COMMAND_ENABLE
 
- HDLCD_DEBUG_INT_MASK
 
- HDLCD_INTERRUPT_BUS_ERROR
 
- HDLCD_INTERRUPT_DMA_END
 
- HDLCD_INTERRUPT_UNDERRUN
 
- HDLCD_INTERRUPT_VSYNC
 
- HDLCD_MAX_XRES
 
- HDLCD_MAX_YRES
 
- HDLCD_PIXEL_FMT_BIG_ENDIAN
 
- HDLCD_PIXEL_FMT_LITTLE_ENDIAN
 
- HDLCD_POLARITY_DATA
 
- HDLCD_POLARITY_DATAEN
 
- HDLCD_POLARITY_HSYNC
 
- HDLCD_POLARITY_PIXELCLK
 
- HDLCD_POLARITY_VSYNC
 
- HDLCD_PRODUCT_ID
 
- HDLCD_PRODUCT_MASK
 
- HDLCD_REG_BLUE_SELECT
 
- HDLCD_REG_BUS_OPTIONS
 
- HDLCD_REG_COMMAND
 
- HDLCD_REG_FB_BASE
 
- HDLCD_REG_FB_LINE_COUNT
 
- HDLCD_REG_FB_LINE_LENGTH
 
- HDLCD_REG_FB_LINE_PITCH
 
- HDLCD_REG_GREEN_SELECT
 
- HDLCD_REG_H_BACK_PORCH
 
- HDLCD_REG_H_DATA
 
- HDLCD_REG_H_FRONT_PORCH
 
- HDLCD_REG_H_SYNC
 
- HDLCD_REG_INT_CLEAR
 
- HDLCD_REG_INT_MASK
 
- HDLCD_REG_INT_RAWSTAT
 
- HDLCD_REG_INT_STATUS
 
- HDLCD_REG_PIXEL_FORMAT
 
- HDLCD_REG_POLARITIES
 
- HDLCD_REG_RED_SELECT
 
- HDLCD_REG_VERSION
 
- HDLCD_REG_V_BACK_PORCH
 
- HDLCD_REG_V_DATA
 
- HDLCD_REG_V_FRONT_PORCH
 
- HDLCD_REG_V_SYNC
 
- HDLCD_VERSION_MAJOR_MASK
 
- HDLCD_VERSION_MINOR_MASK
 
- HDLC_56KBIT
 
- HDLC_ADDR_ALLSTATIONS
 
- HDLC_BITREVERSE
 
- HDLC_CMD_RRS
 
- HDLC_CMD_XME
 
- HDLC_CMD_XML_MASK
 
- HDLC_CMD_XRS
 
- HDLC_CRC_16_CCITT
 
- HDLC_CRC_32_CCITT
 
- HDLC_CRC_ERROR
 
- HDLC_CRC_MASK
 
- HDLC_CRC_NONE
 
- HDLC_CRC_RETURN_EX
 
- HDLC_CRC_SIZE
 
- HDLC_CTRL_UI
 
- HDLC_DCHANNEL
 
- HDLC_ENCODING_BIPHASE_LEVEL
 
- HDLC_ENCODING_BIPHASE_MARK
 
- HDLC_ENCODING_BIPHASE_SPACE
 
- HDLC_ENCODING_DIFF_BIPHASE_LEVEL
 
- HDLC_ENCODING_NRZ
 
- HDLC_ENCODING_NRZB
 
- HDLC_ENCODING_NRZI
 
- HDLC_ENCODING_NRZI_MARK
 
- HDLC_ENCODING_NRZI_SPACE
 
- HDLC_ERROR
 
- HDLC_ERR_CER
 
- HDLC_ERR_FAD
 
- HDLC_ERR_RER
 
- HDLC_Encode
 
- HDLC_FAST_FLAG
 
- HDLC_FAST_IDLE
 
- HDLC_FED
 
- HDLC_FF_FILL
 
- HDLC_FIFO
 
- HDLC_FIFO_SIZE_128
 
- HDLC_FIFO_SIZE_V1
 
- HDLC_FIFO_SIZE_V2
 
- HDLC_FLAG_AUTO_CTS
 
- HDLC_FLAG_AUTO_DCD
 
- HDLC_FLAG_AUTO_RTS
 
- HDLC_FLAG_DPLL_DIV16
 
- HDLC_FLAG_DPLL_DIV32
 
- HDLC_FLAG_DPLL_DIV8
 
- HDLC_FLAG_HDLC_LOOPMODE
 
- HDLC_FLAG_RXC_BRG
 
- HDLC_FLAG_RXC_DPLL
 
- HDLC_FLAG_RXC_RXCPIN
 
- HDLC_FLAG_RXC_TXCPIN
 
- HDLC_FLAG_SHARE_ZERO
 
- HDLC_FLAG_TXC_BRG
 
- HDLC_FLAG_TXC_DPLL
 
- HDLC_FLAG_TXC_RXCPIN
 
- HDLC_FLAG_TXC_TXCPIN
 
- HDLC_FLAG_UNDERRUN_ABORT15
 
- HDLC_FLAG_UNDERRUN_ABORT7
 
- HDLC_FLAG_UNDERRUN_CRC
 
- HDLC_FLAG_UNDERRUN_FLAG
 
- HDLC_FRAMING_ERROR
 
- HDLC_FSD
 
- HDLC_FST
 
- HDLC_GETFLAG_B1A6
 
- HDLC_GETFLAG_B7
 
- HDLC_GET_DATA
 
- HDLC_GET_FLAG_B0
 
- HDLC_HDW_FLOW
 
- HDLC_HEAD_LEN
 
- HDLC_HEAD_MASK
 
- HDLC_INT_MASK
 
- HDLC_INT_RPR
 
- HDLC_INT_XDU
 
- HDLC_INT_XPR
 
- HDLC_LENGTH_ERROR
 
- HDLC_MAGIC
 
- HDLC_MAX_FRAME_SIZE
 
- HDLC_MAX_MRU
 
- HDLC_MAX_MTU
 
- HDLC_MODE_CCR_16
 
- HDLC_MODE_CCR_7
 
- HDLC_MODE_ITF_FLG
 
- HDLC_MODE_TESTLOOP
 
- HDLC_MODE_TRANS
 
- HDLC_PM_OPS
 
- HDLC_PPP_PURE_ASYNC
 
- HDLC_PREAMBLE_LENGTH_16BITS
 
- HDLC_PREAMBLE_LENGTH_32BITS
 
- HDLC_PREAMBLE_LENGTH_64BITS
 
- HDLC_PREAMBLE_LENGTH_8BITS
 
- HDLC_PREAMBLE_PATTERN_01
 
- HDLC_PREAMBLE_PATTERN_10
 
- HDLC_PREAMBLE_PATTERN_FLAGS
 
- HDLC_PREAMBLE_PATTERN_NONE
 
- HDLC_PREAMBLE_PATTERN_ONES
 
- HDLC_PREAMBLE_PATTERN_ZEROS
 
- HDLC_SENDFLAG_B0
 
- HDLC_SENDFLAG_B1A6
 
- HDLC_SENDFLAG_B7
 
- HDLC_SENDFLAG_ONE
 
- HDLC_SEND_CLOSING_FLAG
 
- HDLC_SEND_CRC1
 
- HDLC_SEND_CRC2
 
- HDLC_SEND_DATA
 
- HDLC_SEND_FAST_FLAG
 
- HDLC_SEND_FAST_IDLE
 
- HDLC_SEND_FIRST_FLAG
 
- HDLC_SEND_IDLE1
 
- HDLC_STATUS
 
- HDLC_STAT_CRCVFR
 
- HDLC_STAT_CRCVFRRAB
 
- HDLC_STAT_RDO
 
- HDLC_STAT_RME
 
- HDLC_STAT_RML_MASK_V1
 
- HDLC_STAT_RML_MASK_V2
 
- HDLC_TXIDLE_ALT_MARK_SPACE
 
- HDLC_TXIDLE_ALT_ZEROS_ONES
 
- HDLC_TXIDLE_CUSTOM_16
 
- HDLC_TXIDLE_CUSTOM_8
 
- HDLC_TXIDLE_FLAGS
 
- HDLC_TXIDLE_MARK
 
- HDLC_TXIDLE_ONES
 
- HDLC_TXIDLE_SPACE
 
- HDLC_TXIDLE_ZEROS
 
- HDLC_irq
 
- HDLC_irq_main
 
- HDLC_irq_xpr
 
- HDMI
 
- HDMI0_60958_0
 
- HDMI0_60958_1
 
- HDMI0_60958_2
 
- HDMI0_60958_CS_A
 
- HDMI0_60958_CS_B
 
- HDMI0_60958_CS_C
 
- HDMI0_60958_CS_CATEGORY_CODE
 
- HDMI0_60958_CS_CHANNEL_NUMBER_2
 
- HDMI0_60958_CS_CHANNEL_NUMBER_3
 
- HDMI0_60958_CS_CHANNEL_NUMBER_4
 
- HDMI0_60958_CS_CHANNEL_NUMBER_5
 
- HDMI0_60958_CS_CHANNEL_NUMBER_6
 
- HDMI0_60958_CS_CHANNEL_NUMBER_7
 
- HDMI0_60958_CS_CHANNEL_NUMBER_L
 
- HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK
 
- HDMI0_60958_CS_CHANNEL_NUMBER_R
 
- HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK
 
- HDMI0_60958_CS_CLOCK_ACCURACY
 
- HDMI0_60958_CS_CLOCK_ACCURACY_MASK
 
- HDMI0_60958_CS_D
 
- HDMI0_60958_CS_MODE
 
- HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY
 
- HDMI0_60958_CS_SAMPLING_FREQUENCY
 
- HDMI0_60958_CS_SOURCE_NUMBER
 
- HDMI0_60958_CS_UPDATE
 
- HDMI0_60958_CS_VALID_L
 
- HDMI0_60958_CS_VALID_R
 
- HDMI0_60958_CS_WORD_LENGTH
 
- HDMI0_ACR_32
 
- HDMI0_ACR_32_0
 
- HDMI0_ACR_32_1
 
- HDMI0_ACR_44
 
- HDMI0_ACR_44_0
 
- HDMI0_ACR_44_1
 
- HDMI0_ACR_48
 
- HDMI0_ACR_48_0
 
- HDMI0_ACR_48_1
 
- HDMI0_ACR_AUTO_SEND
 
- HDMI0_ACR_CONT
 
- HDMI0_ACR_CTS_32
 
- HDMI0_ACR_CTS_32_MASK
 
- HDMI0_ACR_CTS_44
 
- HDMI0_ACR_CTS_44_MASK
 
- HDMI0_ACR_CTS_48
 
- HDMI0_ACR_CTS_48_MASK
 
- HDMI0_ACR_HW
 
- HDMI0_ACR_N_32
 
- HDMI0_ACR_N_32_MASK
 
- HDMI0_ACR_N_44
 
- HDMI0_ACR_N_44_MASK
 
- HDMI0_ACR_N_48
 
- HDMI0_ACR_N_48_MASK
 
- HDMI0_ACR_PACKET_CONTROL
 
- HDMI0_ACR_SELECT
 
- HDMI0_ACR_SEND
 
- HDMI0_ACR_SOURCE
 
- HDMI0_ACR_STATUS_0
 
- HDMI0_ACR_STATUS_1
 
- HDMI0_ACTIVE_AVMUTE
 
- HDMI0_AUDIO_CHANNEL_SWAP
 
- HDMI0_AUDIO_CRC_CONTROL
 
- HDMI0_AUDIO_CRC_EN
 
- HDMI0_AUDIO_DELAY_EN
 
- HDMI0_AUDIO_DELAY_EN_MASK
 
- HDMI0_AUDIO_ENABLE
 
- HDMI0_AUDIO_INFO0
 
- HDMI0_AUDIO_INFO1
 
- HDMI0_AUDIO_INFO_CA
 
- HDMI0_AUDIO_INFO_CC
 
- HDMI0_AUDIO_INFO_CHECKSUM
 
- HDMI0_AUDIO_INFO_CONT
 
- HDMI0_AUDIO_INFO_DM_INH
 
- HDMI0_AUDIO_INFO_DM_INH_LSV
 
- HDMI0_AUDIO_INFO_LINE
 
- HDMI0_AUDIO_INFO_LINE_MASK
 
- HDMI0_AUDIO_INFO_LSV
 
- HDMI0_AUDIO_INFO_SEND
 
- HDMI0_AUDIO_INFO_SOURCE
 
- HDMI0_AUDIO_INFO_UPDATE
 
- HDMI0_AUDIO_PACKETS_PER_LINE
 
- HDMI0_AUDIO_PACKETS_PER_LINE_MASK
 
- HDMI0_AUDIO_PACKET_CONTROL
 
- HDMI0_AUDIO_SAMPLE_SEND
 
- HDMI0_AUDIO_SEND_MAX_PACKETS
 
- HDMI0_AUDIO_TEST_EN
 
- HDMI0_AVI_INFO0
 
- HDMI0_AVI_INFO1
 
- HDMI0_AVI_INFO2
 
- HDMI0_AVI_INFO3
 
- HDMI0_AVI_INFO_A
 
- HDMI0_AVI_INFO_B
 
- HDMI0_AVI_INFO_BOTTOM
 
- HDMI0_AVI_INFO_C
 
- HDMI0_AVI_INFO_CHECKSUM
 
- HDMI0_AVI_INFO_CONT
 
- HDMI0_AVI_INFO_C_M_R
 
- HDMI0_AVI_INFO_ITC_EC_Q_SC
 
- HDMI0_AVI_INFO_LEFT
 
- HDMI0_AVI_INFO_LINE
 
- HDMI0_AVI_INFO_LINE_MASK
 
- HDMI0_AVI_INFO_M
 
- HDMI0_AVI_INFO_PR
 
- HDMI0_AVI_INFO_R
 
- HDMI0_AVI_INFO_RIGHT
 
- HDMI0_AVI_INFO_S
 
- HDMI0_AVI_INFO_SC
 
- HDMI0_AVI_INFO_SEND
 
- HDMI0_AVI_INFO_TOP
 
- HDMI0_AVI_INFO_VERSION
 
- HDMI0_AVI_INFO_VIC
 
- HDMI0_AVI_INFO_Y
 
- HDMI0_AVI_INFO_Y_A_B_S
 
- HDMI0_AVI_INFO_Y_RGB
 
- HDMI0_AVI_INFO_Y_YCBCR422
 
- HDMI0_AVI_INFO_Y_YCBCR444
 
- HDMI0_AZ_FORMAT_WTRIG
 
- HDMI0_AZ_FORMAT_WTRIG_ACK
 
- HDMI0_AZ_FORMAT_WTRIG_INT
 
- HDMI0_AZ_FORMAT_WTRIG_MASK
 
- HDMI0_CONTROL
 
- HDMI0_ENABLE
 
- HDMI0_ERROR_ACK
 
- HDMI0_ERROR_MASK
 
- HDMI0_GC
 
- HDMI0_GC_AVMUTE
 
- HDMI0_GC_CONT
 
- HDMI0_GC_SEND
 
- HDMI0_GENERIC0_0
 
- HDMI0_GENERIC0_1
 
- HDMI0_GENERIC0_2
 
- HDMI0_GENERIC0_3
 
- HDMI0_GENERIC0_4
 
- HDMI0_GENERIC0_5
 
- HDMI0_GENERIC0_6
 
- HDMI0_GENERIC0_CONT
 
- HDMI0_GENERIC0_HDR
 
- HDMI0_GENERIC0_LINE
 
- HDMI0_GENERIC0_LINE_MASK
 
- HDMI0_GENERIC0_SEND
 
- HDMI0_GENERIC0_UPDATE
 
- HDMI0_GENERIC1_0
 
- HDMI0_GENERIC1_1
 
- HDMI0_GENERIC1_2
 
- HDMI0_GENERIC1_3
 
- HDMI0_GENERIC1_4
 
- HDMI0_GENERIC1_5
 
- HDMI0_GENERIC1_6
 
- HDMI0_GENERIC1_CONT
 
- HDMI0_GENERIC1_HDR
 
- HDMI0_GENERIC1_LINE
 
- HDMI0_GENERIC1_LINE_MASK
 
- HDMI0_GENERIC1_SEND
 
- HDMI0_GENERIC_PACKET_CONTROL
 
- HDMI0_INFOFRAME_CONTROL0
 
- HDMI0_INFOFRAME_CONTROL1
 
- HDMI0_MPEG_INFO0
 
- HDMI0_MPEG_INFO1
 
- HDMI0_MPEG_INFO_CHECKSUM
 
- HDMI0_MPEG_INFO_CONT
 
- HDMI0_MPEG_INFO_FR
 
- HDMI0_MPEG_INFO_LINE
 
- HDMI0_MPEG_INFO_MB0
 
- HDMI0_MPEG_INFO_MB1
 
- HDMI0_MPEG_INFO_MB2
 
- HDMI0_MPEG_INFO_MB3
 
- HDMI0_MPEG_INFO_MF
 
- HDMI0_MPEG_INFO_SEND
 
- HDMI0_MPEG_INFO_UPDATE
 
- HDMI0_NULL_SEND
 
- HDMI0_RAMP_CONTROL0
 
- HDMI0_RAMP_CONTROL1
 
- HDMI0_RAMP_CONTROL2
 
- HDMI0_RAMP_CONTROL3
 
- HDMI0_RAMP_DEC_COUNT
 
- HDMI0_RAMP_INC_COUNT
 
- HDMI0_RAMP_MAX_COUNT
 
- HDMI0_RAMP_MIN_COUNT
 
- HDMI0_SEL
 
- HDMI0_STATUS
 
- HDMI0_STREAM
 
- HDMI0_STREAM_DDIA
 
- HDMI0_STREAM_DVOA
 
- HDMI0_STREAM_LVTMA
 
- HDMI0_STREAM_TMDSA
 
- HDMI0_VBI_PACKET_CONTROL
 
- HDMI14_MAX_TMDSCLK
 
- HDMI162
 
- HDMI1_AUDIO_PACKET_CONTROL
 
- HDMI1_CONTROL
 
- HDMI1_SEL
 
- HDMI1_STATUS
 
- HDMI297
 
- HDMI2P0_EN
 
- HDMIB_CONTROL
 
- HDMIB_HDCP_PORT
 
- HDMIB_HOTPLUG_INT_EN
 
- HDMIB_NULL_PACKET
 
- HDMIB_PIPE_B_SELECT
 
- HDMIB_PORT_EN
 
- HDMICEC_CK
 
- HDMICTL4
 
- HDMIC_HOTPLUG_INT_EN
 
- HDMID_HOTPLUG_INT_EN
 
- HDMIPHY
 
- HDMIPHY5433_MODE_SET_DONE
 
- HDMIPHYMISCCTL
 
- HDMIPHY_MODE_SET_DONE
 
- HDMIPHY_POWER
 
- HDMITX_DWC_ADDR_REG
 
- HDMITX_DWC_CTRL_REG
 
- HDMITX_DWC_DATA_REG
 
- HDMITX_TOP_ADDR_REG
 
- HDMITX_TOP_BIST_CNTL
 
- HDMITX_TOP_CLK_CNTL
 
- HDMITX_TOP_CTRL_REG
 
- HDMITX_TOP_DATA_REG
 
- HDMITX_TOP_G12A_OFFSET
 
- HDMITX_TOP_HPD_FILTER
 
- HDMITX_TOP_INTR_CORE
 
- HDMITX_TOP_INTR_HPD_FALL
 
- HDMITX_TOP_INTR_HPD_RISE
 
- HDMITX_TOP_INTR_MASKN
 
- HDMITX_TOP_INTR_RXSENSE_FALL
 
- HDMITX_TOP_INTR_RXSENSE_RISE
 
- HDMITX_TOP_INTR_STAT
 
- HDMITX_TOP_INTR_STAT_CLR
 
- HDMITX_TOP_REVOCMEM_STAT
 
- HDMITX_TOP_SHIFT_PTTN_012
 
- HDMITX_TOP_SHIFT_PTTN_345
 
- HDMITX_TOP_SHIFT_PTTN_67
 
- HDMITX_TOP_STAT0
 
- HDMITX_TOP_SW_RESET
 
- HDMITX_TOP_TMDS_CLK_PTTN_01
 
- HDMITX_TOP_TMDS_CLK_PTTN_23
 
- HDMITX_TOP_TMDS_CLK_PTTN_CNTL
 
- HDMI_24BIT_DEEP_COLOR
 
- HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE
 
- HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B
 
- HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B
 
- HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B
 
- HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET
 
- HDMI_30BIT_DEEP_COLOR
 
- HDMI_36BIT_DEEP_COLOR
 
- HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE
 
- HDMI_3D_STRUCTURE_FRAME_PACKING
 
- HDMI_3D_STRUCTURE_INVALID
 
- HDMI_3D_STRUCTURE_LINE_ALTERNATIVE
 
- HDMI_3D_STRUCTURE_L_DEPTH
 
- HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH
 
- HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL
 
- HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF
 
- HDMI_3D_STRUCTURE_TOP_AND_BOTTOM
 
- HDMI_3D_TX_PHY_CKCALCTRL
 
- HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE
 
- HDMI_3D_TX_PHY_CKSYMTXCTRL
 
- HDMI_3D_TX_PHY_CMPMODECTRL
 
- HDMI_3D_TX_PHY_CMPPWRCTRL
 
- HDMI_3D_TX_PHY_CMPSEQCTRL
 
- HDMI_3D_TX_PHY_CPCE_CTRL
 
- HDMI_3D_TX_PHY_CURRCTRL
 
- HDMI_3D_TX_PHY_D2ACTRL
 
- HDMI_3D_TX_PHY_DIGTXMODE
 
- HDMI_3D_TX_PHY_DRVANACTRL
 
- HDMI_3D_TX_PHY_GMPCTRL
 
- HDMI_3D_TX_PHY_GRP_CTRL
 
- HDMI_3D_TX_PHY_MEASCTRL
 
- HDMI_3D_TX_PHY_MPLLMEASCTRL
 
- HDMI_3D_TX_PHY_MSM_CTRL
 
- HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_CLK_REF_MPLL
 
- HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK
 
- HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_OFF
 
- HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_PCLK
 
- HDMI_3D_TX_PHY_MSM_CTRL_MPLL_PH_SEL_CK
 
- HDMI_3D_TX_PHY_MSM_CTRL_SCOPE_CK_SEL
 
- HDMI_3D_TX_PHY_PATTERNGEN
 
- HDMI_3D_TX_PHY_PLLMEASCTRL
 
- HDMI_3D_TX_PHY_PLLPHBYCTRL
 
- HDMI_3D_TX_PHY_PTRPT_ENBL
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_CKO_WORD_ENB
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_CK_REF_ENB
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_OVERRIDE
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT0
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT1
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_PG_SKIP_BIT2
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_RCAL_ENB
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_REFCLK_ENB
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_TX_CLK_ALIGN_ENB
 
- HDMI_3D_TX_PHY_PTRPT_ENBL_TX_READY
 
- HDMI_3D_TX_PHY_PWRCTRL
 
- HDMI_3D_TX_PHY_SCOPECNT0
 
- HDMI_3D_TX_PHY_SCOPECNT1
 
- HDMI_3D_TX_PHY_SCOPECNT2
 
- HDMI_3D_TX_PHY_SCOPECNTCLK
 
- HDMI_3D_TX_PHY_SCOPECNTMSB01
 
- HDMI_3D_TX_PHY_SCOPECNTMSB2CK
 
- HDMI_3D_TX_PHY_SCOPEMODE
 
- HDMI_3D_TX_PHY_SCOPESAMPLE
 
- HDMI_3D_TX_PHY_SCRPB_STATUS
 
- HDMI_3D_TX_PHY_SDCAP_MODE
 
- HDMI_3D_TX_PHY_SERCKCTRL
 
- HDMI_3D_TX_PHY_SERCKKILLCTRL
 
- HDMI_3D_TX_PHY_SERDIVCTRL
 
- HDMI_3D_TX_PHY_STR_STATUS
 
- HDMI_3D_TX_PHY_TXCLKMEASCTRL
 
- HDMI_3D_TX_PHY_TXMEASCTRL
 
- HDMI_3D_TX_PHY_TXRESCTRL
 
- HDMI_3D_TX_PHY_TXTERM
 
- HDMI_3D_TX_PHY_VLEVCTRL
 
- HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL
 
- HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B
 
- HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK
 
- HDMI_8960_PHY_REG12_PWRDN_B
 
- HDMI_8960_PHY_REG12_SW_RESET
 
- HDMI_8x60_PHY_REG0_DESER_DEL_CTRL
 
- HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK
 
- HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT
 
- HDMI_8x60_PHY_REG12_FORCE_LOCK
 
- HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN
 
- HDMI_8x60_PHY_REG12_RETIMING_EN
 
- HDMI_8x60_PHY_REG1_DTEST_MUX_SEL
 
- HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK
 
- HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT
 
- HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL
 
- HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK
 
- HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT
 
- HDMI_8x60_PHY_REG2_PD_DESER
 
- HDMI_8x60_PHY_REG2_PD_DRIVE_1
 
- HDMI_8x60_PHY_REG2_PD_DRIVE_2
 
- HDMI_8x60_PHY_REG2_PD_DRIVE_3
 
- HDMI_8x60_PHY_REG2_PD_DRIVE_4
 
- HDMI_8x60_PHY_REG2_PD_PLL
 
- HDMI_8x60_PHY_REG2_PD_PWRGEN
 
- HDMI_8x60_PHY_REG2_RCV_SENSE_EN
 
- HDMI_8x60_PHY_REG3_PLL_ENABLE
 
- HDMI_AC97
 
- HDMI_ACP_CON
 
- HDMI_ACP_DATA
 
- HDMI_ACP_TYPE
 
- HDMI_ACR_0_CTS
 
- HDMI_ACR_0_CTS__MASK
 
- HDMI_ACR_0_CTS__SHIFT
 
- HDMI_ACR_0_MULTIPLE_RESERVED
 
- HDMI_ACR_1_MULTIPLE
 
- HDMI_ACR_1_N
 
- HDMI_ACR_1_N__MASK
 
- HDMI_ACR_1_N__SHIFT
 
- HDMI_ACR_2_MULTIPLE
 
- HDMI_ACR_32
 
- HDMI_ACR_32_0
 
- HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK
 
- HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT
 
- HDMI_ACR_32_1
 
- HDMI_ACR_32_1__HDMI_ACR_N_32_MASK
 
- HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT
 
- HDMI_ACR_3_MULTIPLE_RESERVED
 
- HDMI_ACR_44
 
- HDMI_ACR_44_0
 
- HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK
 
- HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
 
- HDMI_ACR_44_1
 
- HDMI_ACR_44_1__HDMI_ACR_N_44_MASK
 
- HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT
 
- HDMI_ACR_48
 
- HDMI_ACR_48_0
 
- HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK
 
- HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
 
- HDMI_ACR_48_1
 
- HDMI_ACR_48_1__HDMI_ACR_N_48_MASK
 
- HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT
 
- HDMI_ACR_4_MULTIPLE
 
- HDMI_ACR_5_MULTIPLE_RESERVED
 
- HDMI_ACR_6_MULTIPLE_RESERVED
 
- HDMI_ACR_7_MULTIPLE_RESERVED
 
- HDMI_ACR_AUDIO_PRIORITY
 
- HDMI_ACR_AUTO_SEND
 
- HDMI_ACR_CON
 
- HDMI_ACR_CONT
 
- HDMI_ACR_CONT_DISABLE
 
- HDMI_ACR_CONT_ENABLE
 
- HDMI_ACR_CTS0
 
- HDMI_ACR_CTS_32
 
- HDMI_ACR_CTS_44
 
- HDMI_ACR_CTS_48
 
- HDMI_ACR_HW
 
- HDMI_ACR_MCTS0
 
- HDMI_ACR_N0
 
- HDMI_ACR_NOT_SEND
 
- HDMI_ACR_N_32
 
- HDMI_ACR_N_44
 
- HDMI_ACR_N_48
 
- HDMI_ACR_N_MULTIPLE
 
- HDMI_ACR_PACKET_CONTROL
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
 
- HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT
 
- HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY
 
- HDMI_ACR_PKT_CTRL_CONT
 
- HDMI_ACR_PKT_CTRL_N_MULTIPLIER
 
- HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK
 
- HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT
 
- HDMI_ACR_PKT_CTRL_SELECT
 
- HDMI_ACR_PKT_CTRL_SELECT__MASK
 
- HDMI_ACR_PKT_CTRL_SELECT__SHIFT
 
- HDMI_ACR_PKT_CTRL_SEND
 
- HDMI_ACR_PKT_CTRL_SOURCE
 
- HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE
 
- HDMI_ACR_PKT_SEND
 
- HDMI_ACR_SELECT
 
- HDMI_ACR_SELECT_32K
 
- HDMI_ACR_SELECT_44K
 
- HDMI_ACR_SELECT_48K
 
- HDMI_ACR_SELECT_HW
 
- HDMI_ACR_SEND
 
- HDMI_ACR_SOURCE
 
- HDMI_ACR_SOURCE_HW
 
- HDMI_ACR_SOURCE_SW
 
- HDMI_ACR_STATUS_0
 
- HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK
 
- HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT
 
- HDMI_ACR_STATUS_1
 
- HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK
 
- HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT
 
- HDMI_ACR_X1
 
- HDMI_ACR_X2
 
- HDMI_ACR_X4
 
- HDMI_ACTIVE_ASPECT_14_9
 
- HDMI_ACTIVE_ASPECT_14_9_TOP
 
- HDMI_ACTIVE_ASPECT_16_9
 
- HDMI_ACTIVE_ASPECT_16_9_CENTER
 
- HDMI_ACTIVE_ASPECT_16_9_SP_14_9
 
- HDMI_ACTIVE_ASPECT_16_9_SP_4_3
 
- HDMI_ACTIVE_ASPECT_16_9_TOP
 
- HDMI_ACTIVE_ASPECT_4_3
 
- HDMI_ACTIVE_ASPECT_4_3_SP_14_9
 
- HDMI_ACTIVE_ASPECT_PICTURE
 
- HDMI_ACTIVE_AVMUTE
 
- HDMI_ACTIVE_HSYNC_END
 
- HDMI_ACTIVE_HSYNC_END__MASK
 
- HDMI_ACTIVE_HSYNC_END__SHIFT
 
- HDMI_ACTIVE_HSYNC_START
 
- HDMI_ACTIVE_HSYNC_START__MASK
 
- HDMI_ACTIVE_HSYNC_START__SHIFT
 
- HDMI_ACTIVE_VID_XMAX
 
- HDMI_ACTIVE_VID_XMIN
 
- HDMI_ACTIVE_VID_YMAX
 
- HDMI_ACTIVE_VID_YMIN
 
- HDMI_ACTIVE_VSYNC_END
 
- HDMI_ACTIVE_VSYNC_END__MASK
 
- HDMI_ACTIVE_VSYNC_END__SHIFT
 
- HDMI_ACTIVE_VSYNC_START
 
- HDMI_ACTIVE_VSYNC_START__MASK
 
- HDMI_ACTIVE_VSYNC_START__SHIFT
 
- HDMI_AHB_DMA_BSTADDR0
 
- HDMI_AHB_DMA_BSTADDR1
 
- HDMI_AHB_DMA_BSTADDR2
 
- HDMI_AHB_DMA_BSTADDR3
 
- HDMI_AHB_DMA_BUFFINT
 
- HDMI_AHB_DMA_BUFFMASK
 
- HDMI_AHB_DMA_BUFFPOL
 
- HDMI_AHB_DMA_BUFFSTAT
 
- HDMI_AHB_DMA_BUFFSTAT_EMPTY
 
- HDMI_AHB_DMA_BUFFSTAT_FULL
 
- HDMI_AHB_DMA_CONF0
 
- HDMI_AHB_DMA_CONF0_BURST_MODE
 
- HDMI_AHB_DMA_CONF0_EN_HLOCK
 
- HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK
 
- HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET
 
- HDMI_AHB_DMA_CONF0_HBR
 
- HDMI_AHB_DMA_CONF0_INCR16
 
- HDMI_AHB_DMA_CONF0_INCR4
 
- HDMI_AHB_DMA_CONF0_INCR8
 
- HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK
 
- HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET
 
- HDMI_AHB_DMA_CONF0_SW_FIFO_RST
 
- HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK
 
- HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET
 
- HDMI_AHB_DMA_CONF1
 
- HDMI_AHB_DMA_DONE
 
- HDMI_AHB_DMA_ERROR
 
- HDMI_AHB_DMA_FIFO_EMPTY
 
- HDMI_AHB_DMA_FIFO_FULL
 
- HDMI_AHB_DMA_FIFO_THREMPTY
 
- HDMI_AHB_DMA_INT
 
- HDMI_AHB_DMA_LOSTOWNERSHIP
 
- HDMI_AHB_DMA_MASK
 
- HDMI_AHB_DMA_MASK_DONE
 
- HDMI_AHB_DMA_MBLENGTH0
 
- HDMI_AHB_DMA_MBLENGTH1
 
- HDMI_AHB_DMA_POL
 
- HDMI_AHB_DMA_RETRY_SPLIT
 
- HDMI_AHB_DMA_START
 
- HDMI_AHB_DMA_START_START
 
- HDMI_AHB_DMA_START_START_MASK
 
- HDMI_AHB_DMA_START_START_OFFSET
 
- HDMI_AHB_DMA_STAT
 
- HDMI_AHB_DMA_STOP
 
- HDMI_AHB_DMA_STOP_STOP
 
- HDMI_AHB_DMA_STOP_STOP_MASK
 
- HDMI_AHB_DMA_STOP_STOP_OFFSET
 
- HDMI_AHB_DMA_STPADDR0
 
- HDMI_AHB_DMA_STPADDR1
 
- HDMI_AHB_DMA_STPADDR2
 
- HDMI_AHB_DMA_STPADDR3
 
- HDMI_AHB_DMA_STRADDR0
 
- HDMI_AHB_DMA_STRADDR1
 
- HDMI_AHB_DMA_STRADDR2
 
- HDMI_AHB_DMA_STRADDR3
 
- HDMI_AHB_DMA_THRSLD
 
- HDMI_AHB_RESET
 
- HDMI_AN_SEED_0
 
- HDMI_AN_SEED_1
 
- HDMI_AN_SEED_2
 
- HDMI_AN_SEED_3
 
- HDMI_AN_SEED_SEL
 
- HDMI_APP_CLK
 
- HDMI_ASP_CHCFG0
 
- HDMI_ASP_CHCFG1
 
- HDMI_ASP_CHCFG2
 
- HDMI_ASP_CHCFG3
 
- HDMI_ASP_CON
 
- HDMI_ASP_DIS
 
- HDMI_ASP_EN
 
- HDMI_ASP_MASK
 
- HDMI_ASP_SP_FLAT
 
- HDMI_AUDIOCLK_FREQ
 
- HDMI_AUDIO_AUTO
 
- HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF
 
- HDMI_AUDIO_BLOCK_SIG_STARTEND_ON
 
- HDMI_AUDIO_BUFFER_DONE
 
- HDMI_AUDIO_CFG
 
- HDMI_AUDIO_CFG_ENGINE_ENABLE
 
- HDMI_AUDIO_CFG_FIFO_WATERMARK
 
- HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK
 
- HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT
 
- HDMI_AUDIO_CHANNEL_STATUS
 
- HDMI_AUDIO_CLKSEL
 
- HDMI_AUDIO_CODING_TYPE_AAC_LC
 
- HDMI_AUDIO_CODING_TYPE_AC3
 
- HDMI_AUDIO_CODING_TYPE_ATRAC
 
- HDMI_AUDIO_CODING_TYPE_CXT
 
- HDMI_AUDIO_CODING_TYPE_DSD
 
- HDMI_AUDIO_CODING_TYPE_DST
 
- HDMI_AUDIO_CODING_TYPE_DTS
 
- HDMI_AUDIO_CODING_TYPE_DTS_HD
 
- HDMI_AUDIO_CODING_TYPE_EAC3
 
- HDMI_AUDIO_CODING_TYPE_EXT_CT
 
- HDMI_AUDIO_CODING_TYPE_EXT_DRA
 
- HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC
 
- HDMI_AUDIO_CODING_TYPE_EXT_HE_AAC_V2
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_AAC_LC_SURROUND
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_SURROUND
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG4_HE_AAC_V2
 
- HDMI_AUDIO_CODING_TYPE_EXT_MPEG_SURROUND
 
- HDMI_AUDIO_CODING_TYPE_MLP
 
- HDMI_AUDIO_CODING_TYPE_MP3
 
- HDMI_AUDIO_CODING_TYPE_MPEG1
 
- HDMI_AUDIO_CODING_TYPE_MPEG2
 
- HDMI_AUDIO_CODING_TYPE_PCM
 
- HDMI_AUDIO_CODING_TYPE_STREAM
 
- HDMI_AUDIO_CODING_TYPE_WMA_PRO
 
- HDMI_AUDIO_CP_LOGIC_RESET
 
- HDMI_AUDIO_CP_LOGIC_RESET_MASK
 
- HDMI_AUDIO_CTRL
 
- HDMI_AUDIO_CTRL1
 
- HDMI_AUDIO_CTRL2
 
- HDMI_AUDIO_CTS_H
 
- HDMI_AUDIO_CTS_L
 
- HDMI_AUDIO_CTS_M
 
- HDMI_AUDIO_CTS_MODE_HW
 
- HDMI_AUDIO_CTS_MODE_SW
 
- HDMI_AUDIO_DELAY_56CLK
 
- HDMI_AUDIO_DELAY_58CLK
 
- HDMI_AUDIO_DELAY_DISABLE
 
- HDMI_AUDIO_DELAY_EN
 
- HDMI_AUDIO_DELAY_RESERVED
 
- HDMI_AUDIO_DISABLE
 
- HDMI_AUDIO_ENABLE
 
- HDMI_AUDIO_EXTERNAL_CTS
 
- HDMI_AUDIO_I2S_CHANNEL_1_2
 
- HDMI_AUDIO_I2S_CHANNEL_3_4
 
- HDMI_AUDIO_I2S_CHANNEL_5_6
 
- HDMI_AUDIO_I2S_CHANNEL_7_8
 
- HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT
 
- HDMI_AUDIO_I2S_FIRST_BIT_SHIFT
 
- HDMI_AUDIO_I2S_FORMAT_STANDARD
 
- HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST
 
- HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST
 
- HDMI_AUDIO_I2S_SCK_EDGE_FALLING
 
- HDMI_AUDIO_I2S_SCK_EDGE_RISING
 
- HDMI_AUDIO_I2S_SD0_EN
 
- HDMI_AUDIO_I2S_SD1_EN
 
- HDMI_AUDIO_I2S_SD2_EN
 
- HDMI_AUDIO_I2S_SD3_EN
 
- HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED
 
- HDMI_AUDIO_I2S_VBIT_FOR_PCM
 
- HDMI_AUDIO_INFO0_CC
 
- HDMI_AUDIO_INFO0_CC__MASK
 
- HDMI_AUDIO_INFO0_CC__SHIFT
 
- HDMI_AUDIO_INFO0_CHECKSUM
 
- HDMI_AUDIO_INFO0_CHECKSUM__MASK
 
- HDMI_AUDIO_INFO0_CHECKSUM__SHIFT
 
- HDMI_AUDIO_INFO1_CA
 
- HDMI_AUDIO_INFO1_CA__MASK
 
- HDMI_AUDIO_INFO1_CA__SHIFT
 
- HDMI_AUDIO_INFO1_DM_INH
 
- HDMI_AUDIO_INFO1_LSV
 
- HDMI_AUDIO_INFO1_LSV__MASK
 
- HDMI_AUDIO_INFO1_LSV__SHIFT
 
- HDMI_AUDIO_INFOFRAME_SIZE
 
- HDMI_AUDIO_INFO_CONT
 
- HDMI_AUDIO_INFO_CONT_DISABLE
 
- HDMI_AUDIO_INFO_CONT_ENABLE
 
- HDMI_AUDIO_INFO_LINE
 
- HDMI_AUDIO_INFO_NOT_SEND
 
- HDMI_AUDIO_INFO_PKT_SEND
 
- HDMI_AUDIO_INFO_SEND
 
- HDMI_AUDIO_INPUT_IIS
 
- HDMI_AUDIO_INPUT_MCLK_ACTIVE
 
- HDMI_AUDIO_INPUT_MCLK_DEACTIVE
 
- HDMI_AUDIO_INPUT_MCLK_RATE_128X
 
- HDMI_AUDIO_INPUT_MCLK_RATE_256X
 
- HDMI_AUDIO_INPUT_MCLK_RATE_384X
 
- HDMI_AUDIO_INPUT_MCLK_RATE_512X
 
- HDMI_AUDIO_INPUT_SPDIF
 
- HDMI_AUDIO_JUSTIFY_LEFT
 
- HDMI_AUDIO_JUSTIFY_RIGHT
 
- HDMI_AUDIO_LAYOUT_2CH
 
- HDMI_AUDIO_LAYOUT_6CH
 
- HDMI_AUDIO_LAYOUT_8CH
 
- HDMI_AUDIO_LR_SWAP_MASK
 
- HDMI_AUDIO_LR_SWAP_SUBPACKET0
 
- HDMI_AUDIO_LR_SWAP_SUBPACKET1
 
- HDMI_AUDIO_LR_SWAP_SUBPACKET2
 
- HDMI_AUDIO_LR_SWAP_SUBPACKET3
 
- HDMI_AUDIO_MCLK_1024FS
 
- HDMI_AUDIO_MCLK_1152FS
 
- HDMI_AUDIO_MCLK_128FS
 
- HDMI_AUDIO_MCLK_192FS
 
- HDMI_AUDIO_MCLK_256FS
 
- HDMI_AUDIO_MCLK_384FS
 
- HDMI_AUDIO_MCLK_512FS
 
- HDMI_AUDIO_MCLK_768FS
 
- HDMI_AUDIO_N_19_16_MASK
 
- HDMI_AUDIO_OFF
 
- HDMI_AUDIO_OFF_DVI
 
- HDMI_AUDIO_ON
 
- HDMI_AUDIO_ONEWORD_ONESAMPLE
 
- HDMI_AUDIO_ONEWORD_TWOSAMPLES
 
- HDMI_AUDIO_PACKETS_PER_LINE
 
- HDMI_AUDIO_PACKET_CONTROL
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK
 
- HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT
 
- HDMI_AUDIO_PACKET_ERROR
 
- HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND
 
- HDMI_AUDIO_PKT_CTRL2_LAYOUT
 
- HDMI_AUDIO_PKT_CTRL2_OVERRIDE
 
- HDMI_AUDIO_SAMPLE_16BITS
 
- HDMI_AUDIO_SAMPLE_24BITS
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_176400
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_192000
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_32000
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_44100
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_48000
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_88200
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_96000
 
- HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM
 
- HDMI_AUDIO_SAMPLE_FRE_176400
 
- HDMI_AUDIO_SAMPLE_FRE_192000
 
- HDMI_AUDIO_SAMPLE_FRE_32000
 
- HDMI_AUDIO_SAMPLE_FRE_44100
 
- HDMI_AUDIO_SAMPLE_FRE_48000
 
- HDMI_AUDIO_SAMPLE_FRE_768000
 
- HDMI_AUDIO_SAMPLE_FRE_88200
 
- HDMI_AUDIO_SAMPLE_FRE_96000
 
- HDMI_AUDIO_SAMPLE_FRE_MASK
 
- HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT
 
- HDMI_AUDIO_SAMPLE_LEFT_FIRST
 
- HDMI_AUDIO_SAMPLE_RIGHT_FIRST
 
- HDMI_AUDIO_SAMPLE_SIZE_16
 
- HDMI_AUDIO_SAMPLE_SIZE_20
 
- HDMI_AUDIO_SAMPLE_SIZE_24
 
- HDMI_AUDIO_SAMPLE_SIZE_STREAM
 
- HDMI_AUDIO_SEND_MAX_PACKETS
 
- HDMI_AUDIO_SRC_NUM_AND_LENGTH
 
- HDMI_AUDIO_STA_BIT_CTRL1
 
- HDMI_AUDIO_STA_BIT_CTRL2
 
- HDMI_AUDIO_STEREO_FOURCHANNELS
 
- HDMI_AUDIO_STEREO_NOCHANNELS
 
- HDMI_AUDIO_STEREO_ONECHANNEL
 
- HDMI_AUDIO_STEREO_THREECHANNELS
 
- HDMI_AUDIO_STEREO_TWOCHANNELS
 
- HDMI_AUDIO_TEST_SEL
 
- HDMI_AUDIO_TRANSF_DMA
 
- HDMI_AUDIO_TRANSF_IRQ
 
- HDMI_AUDIO_TYPE_IEC
 
- HDMI_AUDIO_TYPE_LPCM
 
- HDMI_AUDIO_UNDERRUN
 
- HDMI_AUDN
 
- HDMI_AUD_CFG_8CH
 
- HDMI_AUD_CFG_CH12_VALID
 
- HDMI_AUD_CFG_CH34_VALID
 
- HDMI_AUD_CFG_CH56_VALID
 
- HDMI_AUD_CFG_CH78_VALID
 
- HDMI_AUD_CFG_CTS_CLK_256FS
 
- HDMI_AUD_CFG_DTS_INVALID
 
- HDMI_AUD_CFG_ONE_BIT_INVALID
 
- HDMI_AUD_CFG_SPDIF_CLK_DIV_4
 
- HDMI_AUD_CFG_SPDIF_DIV_2
 
- HDMI_AUD_CFG_SPDIF_DIV_3
 
- HDMI_AUD_CHAN_TYPE_1_0
 
- HDMI_AUD_CHAN_TYPE_1_1
 
- HDMI_AUD_CHAN_TYPE_2_0
 
- HDMI_AUD_CHAN_TYPE_2_1
 
- HDMI_AUD_CHAN_TYPE_3_0
 
- HDMI_AUD_CHAN_TYPE_3_0_LRS
 
- HDMI_AUD_CHAN_TYPE_3_1
 
- HDMI_AUD_CHAN_TYPE_3_1_LRS
 
- HDMI_AUD_CHAN_TYPE_4_0
 
- HDMI_AUD_CHAN_TYPE_4_0_CLRS
 
- HDMI_AUD_CHAN_TYPE_4_1
 
- HDMI_AUD_CHAN_TYPE_4_1_CLRS
 
- HDMI_AUD_CHAN_TYPE_5_0
 
- HDMI_AUD_CHAN_TYPE_5_1
 
- HDMI_AUD_CHAN_TYPE_6_0
 
- HDMI_AUD_CHAN_TYPE_6_0_CH
 
- HDMI_AUD_CHAN_TYPE_6_0_CHR
 
- HDMI_AUD_CHAN_TYPE_6_0_CS
 
- HDMI_AUD_CHAN_TYPE_6_0_OH
 
- HDMI_AUD_CHAN_TYPE_6_1
 
- HDMI_AUD_CHAN_TYPE_6_1_CH
 
- HDMI_AUD_CHAN_TYPE_6_1_CHR
 
- HDMI_AUD_CHAN_TYPE_6_1_CS
 
- HDMI_AUD_CHAN_TYPE_6_1_OH
 
- HDMI_AUD_CHAN_TYPE_7_0
 
- HDMI_AUD_CHAN_TYPE_7_0_CH_CHR
 
- HDMI_AUD_CHAN_TYPE_7_0_CH_OH
 
- HDMI_AUD_CHAN_TYPE_7_0_CS_CH
 
- HDMI_AUD_CHAN_TYPE_7_0_CS_CHR
 
- HDMI_AUD_CHAN_TYPE_7_0_CS_OH
 
- HDMI_AUD_CHAN_TYPE_7_0_LC_RC
 
- HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS
 
- HDMI_AUD_CHAN_TYPE_7_0_LH_RH
 
- HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD
 
- HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR
 
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS
 
- HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR
 
- HDMI_AUD_CHAN_TYPE_7_0_LW_RW
 
- HDMI_AUD_CHAN_TYPE_7_0_OH_CHR
 
- HDMI_AUD_CHAN_TYPE_7_1
 
- HDMI_AUD_CHAN_TYPE_7_1_CH_CHR
 
- HDMI_AUD_CHAN_TYPE_7_1_CH_OH
 
- HDMI_AUD_CHAN_TYPE_7_1_CS_CH
 
- HDMI_AUD_CHAN_TYPE_7_1_CS_CHR
 
- HDMI_AUD_CHAN_TYPE_7_1_CS_OH
 
- HDMI_AUD_CHAN_TYPE_7_1_LC_RC
 
- HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS
 
- HDMI_AUD_CHAN_TYPE_7_1_LH_RH
 
- HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD
 
- HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR
 
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS
 
- HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR
 
- HDMI_AUD_CHAN_TYPE_7_1_LW_RW
 
- HDMI_AUD_CHAN_TYPE_7_1_OH_CHR
 
- HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS
 
- HDMI_AUD_CHAN_TYPE_UNKNOWN
 
- HDMI_AUD_CONF0
 
- HDMI_AUD_CONF0_HBR
 
- HDMI_AUD_CONF0_I2S_EN0
 
- HDMI_AUD_CONF0_I2S_EN1
 
- HDMI_AUD_CONF0_I2S_EN2
 
- HDMI_AUD_CONF0_I2S_EN3
 
- HDMI_AUD_CONF0_I2S_SELECT
 
- HDMI_AUD_CONF0_SW_RESET
 
- HDMI_AUD_CONF1
 
- HDMI_AUD_CONF1_MODE_BURST_1
 
- HDMI_AUD_CONF1_MODE_BURST_2
 
- HDMI_AUD_CONF1_MODE_I2S
 
- HDMI_AUD_CONF1_MODE_LEFT_J
 
- HDMI_AUD_CONF1_MODE_RIGHT_J
 
- HDMI_AUD_CONF1_WIDTH_16
 
- HDMI_AUD_CONF1_WIDTH_24
 
- HDMI_AUD_CONF2
 
- HDMI_AUD_CTS
 
- HDMI_AUD_CTS1
 
- HDMI_AUD_CTS2
 
- HDMI_AUD_CTS3
 
- HDMI_AUD_CTS3_AUDCTS19_16_MASK
 
- HDMI_AUD_CTS3_CTS_MANUAL
 
- HDMI_AUD_CTS3_N_SHIFT_1
 
- HDMI_AUD_CTS3_N_SHIFT_128
 
- HDMI_AUD_CTS3_N_SHIFT_16
 
- HDMI_AUD_CTS3_N_SHIFT_256
 
- HDMI_AUD_CTS3_N_SHIFT_32
 
- HDMI_AUD_CTS3_N_SHIFT_64
 
- HDMI_AUD_CTS3_N_SHIFT_MASK
 
- HDMI_AUD_CTS3_N_SHIFT_OFFSET
 
- HDMI_AUD_HBR_INT
 
- HDMI_AUD_HBR_MASK
 
- HDMI_AUD_HBR_POL
 
- HDMI_AUD_HBR_STATUS
 
- HDMI_AUD_INPUTCLKFS
 
- HDMI_AUD_INPUTCLKFS_128FS
 
- HDMI_AUD_INPUTCLKFS_256FS
 
- HDMI_AUD_INPUTCLKFS_512FS
 
- HDMI_AUD_INPUTCLKFS_64FS
 
- HDMI_AUD_INPUT_I2S
 
- HDMI_AUD_INPUT_SPDIF
 
- HDMI_AUD_INT
 
- HDMI_AUD_INT_AUD_FIFO_URAN_MASK
 
- HDMI_AUD_INT_AUD_FIFO_URUN_INT
 
- HDMI_AUD_INT_AUD_SAM_DROP_INT
 
- HDMI_AUD_INT_AUD_SAM_DROP_MASK
 
- HDMI_AUD_MCLK_1152FS
 
- HDMI_AUD_MCLK_128FS
 
- HDMI_AUD_MCLK_192FS
 
- HDMI_AUD_MCLK_256FS
 
- HDMI_AUD_MCLK_384FS
 
- HDMI_AUD_MCLK_512FS
 
- HDMI_AUD_MCLK_768FS
 
- HDMI_AUD_N1
 
- HDMI_AUD_N2
 
- HDMI_AUD_N3
 
- HDMI_AUD_SPDIFINT
 
- HDMI_AUD_SWAP_LFE_CC
 
- HDMI_AUD_SWAP_LR
 
- HDMI_AUD_SWAP_LR_STATUS
 
- HDMI_AUD_SWAP_LSRS
 
- HDMI_AUD_SWAP_RLS_RRS
 
- HDMI_AUI_BYTE
 
- HDMI_AUI_CHECK_SUM
 
- HDMI_AUI_CON
 
- HDMI_AUI_CON_EVERY_VSYNC
 
- HDMI_AUI_CON_NO_TRAN
 
- HDMI_AUI_HEADER0
 
- HDMI_AUI_HEADER1
 
- HDMI_AUI_HEADER2
 
- HDMI_AUTO_CHECKSUM_OPT
 
- HDMI_AUX_DIV_SHIFT
 
- HDMI_AUX_PNX_DIV_SHIFT
 
- HDMI_AVI_BYTE
 
- HDMI_AVI_CHECK_SUM
 
- HDMI_AVI_CON
 
- HDMI_AVI_CON_DO_NOT_TRANSMIT
 
- HDMI_AVI_CON_EVERY_VSYNC
 
- HDMI_AVI_HEADER0
 
- HDMI_AVI_HEADER1
 
- HDMI_AVI_HEADER2
 
- HDMI_AVI_INFOFRAME_SIZE
 
- HDMI_AVI_INFO_CONT
 
- HDMI_AVI_INFO_CONT_DISABLE
 
- HDMI_AVI_INFO_CONT_ENABLE
 
- HDMI_AVI_INFO_LINE
 
- HDMI_AVI_INFO_LINE_MASK
 
- HDMI_AVI_INFO_NOT_SEND
 
- HDMI_AVI_INFO_PKT_SEND
 
- HDMI_AVI_INFO_SEND
 
- HDMI_AV_CTRL1
 
- HDMI_AV_CTRL2
 
- HDMI_AV_MUTE
 
- HDMI_A_100MSCFG
 
- HDMI_A_2SCFG0
 
- HDMI_A_2SCFG1
 
- HDMI_A_5SCFG0
 
- HDMI_A_5SCFG1
 
- HDMI_A_APIINTCLR
 
- HDMI_A_APIINTMSK
 
- HDMI_A_APIINTSTAT
 
- HDMI_A_HDCPCFG0
 
- HDMI_A_HDCPCFG0_AVMUTE_DISABLE
 
- HDMI_A_HDCPCFG0_AVMUTE_ENABLE
 
- HDMI_A_HDCPCFG0_AVMUTE_MASK
 
- HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE
 
- HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE
 
- HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK
 
- HDMI_A_HDCPCFG0_ELVENA_DISABLE
 
- HDMI_A_HDCPCFG0_ELVENA_ENABLE
 
- HDMI_A_HDCPCFG0_ELVENA_MASK
 
- HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE
 
- HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE
 
- HDMI_A_HDCPCFG0_EN11FEATURE_MASK
 
- HDMI_A_HDCPCFG0_HDMIDVI_DVI
 
- HDMI_A_HDCPCFG0_HDMIDVI_HDMI
 
- HDMI_A_HDCPCFG0_HDMIDVI_MASK
 
- HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE
 
- HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE
 
- HDMI_A_HDCPCFG0_I2CFASTMODE_MASK
 
- HDMI_A_HDCPCFG0_RXDETECT_DISABLE
 
- HDMI_A_HDCPCFG0_RXDETECT_ENABLE
 
- HDMI_A_HDCPCFG0_RXDETECT_MASK
 
- HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE
 
- HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE
 
- HDMI_A_HDCPCFG0_SYNCRICHECK_MASK
 
- HDMI_A_HDCPCFG1
 
- HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE
 
- HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE
 
- HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK
 
- HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE
 
- HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE
 
- HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK
 
- HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE
 
- HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE
 
- HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK
 
- HDMI_A_HDCPCFG1_SWRESET_ASSERT
 
- HDMI_A_HDCPCFG1_SWRESET_MASK
 
- HDMI_A_HDCPOBS0
 
- HDMI_A_HDCPOBS1
 
- HDMI_A_HDCPOBS2
 
- HDMI_A_HDCPOBS3
 
- HDMI_A_I2CHSETUP
 
- HDMI_A_INTSETUP
 
- HDMI_A_OESSWCFG
 
- HDMI_A_PRESETUP
 
- HDMI_A_SFRSETUP
 
- HDMI_A_SRMCTRL
 
- HDMI_A_SRMVERLSB
 
- HDMI_A_SRMVERMSB
 
- HDMI_A_SRM_BASE
 
- HDMI_A_TIMER1SETUP0
 
- HDMI_A_TIMER1SETUP1
 
- HDMI_A_TIMER2SETUP0
 
- HDMI_A_TIMER2SETUP1
 
- HDMI_A_VIDPOLCFG
 
- HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH
 
- HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW
 
- HDMI_A_VIDPOLCFG_DATAENPOL_MASK
 
- HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH
 
- HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW
 
- HDMI_A_VIDPOLCFG_HSYNCPOL_MASK
 
- HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK
 
- HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET
 
- HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH
 
- HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW
 
- HDMI_A_VIDPOLCFG_VSYNCPOL_MASK
 
- HDMI_BIT_WIDTH_16_BIT
 
- HDMI_BIT_WIDTH_32_BIT
 
- HDMI_BLUE_SCREEN_B_0
 
- HDMI_BLUE_SCREEN_B_1
 
- HDMI_BLUE_SCREEN_G_0
 
- HDMI_BLUE_SCREEN_G_1
 
- HDMI_BLUE_SCREEN_R_0
 
- HDMI_BLUE_SCREEN_R_1
 
- HDMI_BLUE_SCR_EN
 
- HDMI_BORDER_ENABLE
 
- HDMI_CEC
 
- HDMI_CEC_ADDR_H
 
- HDMI_CEC_ADDR_L
 
- HDMI_CEC_BUSFREETIME_H
 
- HDMI_CEC_BUSFREETIME_L
 
- HDMI_CEC_CA_15_8
 
- HDMI_CEC_CA_7_0
 
- HDMI_CEC_CLK_H
 
- HDMI_CEC_CLK_L
 
- HDMI_CEC_CTRL
 
- HDMI_CEC_DATA
 
- HDMI_CEC_DBG_3
 
- HDMI_CEC_DEV_ID
 
- HDMI_CEC_INT
 
- HDMI_CEC_INT_ENABLE_0
 
- HDMI_CEC_INT_ENABLE_1
 
- HDMI_CEC_INT_STATUS_0
 
- HDMI_CEC_INT_STATUS_1
 
- HDMI_CEC_LOCK
 
- HDMI_CEC_LOGICADDR
 
- HDMI_CEC_MARK
 
- HDMI_CEC_MASK
 
- HDMI_CEC_POLARITY
 
- HDMI_CEC_RETRANSMIT_CNT_INT_MASK
 
- HDMI_CEC_RX_CMD_HEADER
 
- HDMI_CEC_RX_CNT
 
- HDMI_CEC_RX_COMMAND
 
- HDMI_CEC_RX_CONTROL
 
- HDMI_CEC_RX_COUNT
 
- HDMI_CEC_RX_DATA0
 
- HDMI_CEC_RX_INT
 
- HDMI_CEC_RX_INT_MASK
 
- HDMI_CEC_RX_LENGTH
 
- HDMI_CEC_RX_OFFSET
 
- HDMI_CEC_RX_OPERAND
 
- HDMI_CEC_SETUP
 
- HDMI_CEC_SPEC
 
- HDMI_CEC_STAT
 
- HDMI_CEC_TRANSMIT_DATA
 
- HDMI_CEC_TX_CNT
 
- HDMI_CEC_TX_COMMAND
 
- HDMI_CEC_TX_DATA0
 
- HDMI_CEC_TX_DEST
 
- HDMI_CEC_TX_FIFO_INT_MASK
 
- HDMI_CEC_TX_INIT
 
- HDMI_CEC_TX_INT
 
- HDMI_CEC_TX_INT_MASK
 
- HDMI_CEC_TX_LENGTH
 
- HDMI_CEC_TX_OFFSET
 
- HDMI_CEC_TX_OPERAND
 
- HDMI_CEC_WKUPCTRL
 
- HDMI_CFG
 
- HDMI_CFG_422_EN
 
- HDMI_CFG_DEVICE_EN
 
- HDMI_CFG_ESS_NOT_OESS
 
- HDMI_CFG_FIFO_OVERRUN_CLR
 
- HDMI_CFG_FIFO_UNDERRUN_CLR
 
- HDMI_CFG_HDCP_EN
 
- HDMI_CFG_HDMI_NOT_DVI
 
- HDMI_CFG_H_SYNC_POL_NEG
 
- HDMI_CFG_SW_RST_EN
 
- HDMI_CFG_V_SYNC_POL_NEG
 
- HDMI_CLK_SRC
 
- HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
 
- HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE
 
- HDMI_CLOCK_CHANNEL_RATE
 
- HDMI_CLOCK_CHANNEL_RATE_MORE_340M
 
- HDMI_CMAX
 
- HDMI_CMIN
 
- HDMI_CODEC_CHMAP_IDX_UNKNOWN
 
- HDMI_CODEC_DRV_NAME
 
- HDMI_COLORBAR
 
- HDMI_COLORIMETRY_BT2020_CYCC
 
- HDMI_COLORIMETRY_BT2020_RGB
 
- HDMI_COLORIMETRY_BT2020_YCC
 
- HDMI_COLORIMETRY_BT709_YCC
 
- HDMI_COLORIMETRY_DCI_P3_RGB_D65
 
- HDMI_COLORIMETRY_DCI_P3_RGB_THEATER
 
- HDMI_COLORIMETRY_EXTENDED
 
- HDMI_COLORIMETRY_ITU_601
 
- HDMI_COLORIMETRY_ITU_709
 
- HDMI_COLORIMETRY_NONE
 
- HDMI_COLORIMETRY_NO_DATA
 
- HDMI_COLORIMETRY_OPRGB
 
- HDMI_COLORIMETRY_OPYCC_601
 
- HDMI_COLORIMETRY_SMPTE_170M_YCC
 
- HDMI_COLORIMETRY_SYCC_601
 
- HDMI_COLORIMETRY_XVYCC_601
 
- HDMI_COLORIMETRY_XVYCC_709
 
- HDMI_COLORSPACE_IDO_DEFINED
 
- HDMI_COLORSPACE_RESERVED4
 
- HDMI_COLORSPACE_RESERVED5
 
- HDMI_COLORSPACE_RESERVED6
 
- HDMI_COLORSPACE_RGB
 
- HDMI_COLORSPACE_YUV420
 
- HDMI_COLORSPACE_YUV422
 
- HDMI_COLORSPACE_YUV444
 
- HDMI_COLOR_FORMAT_12bpc
 
- HDMI_COLOR_RANGE_16_235
 
- HDMI_CON0
 
- HDMI_CON1
 
- HDMI_CON2
 
- HDMI_CON3
 
- HDMI_CON4
 
- HDMI_CON5
 
- HDMI_CON6
 
- HDMI_CON7
 
- HDMI_CON8
 
- HDMI_CONFIG0_CEC
 
- HDMI_CONFIG0_I2S
 
- HDMI_CONFIG0_ID
 
- HDMI_CONFIG1_AHB
 
- HDMI_CONFIG1_ID
 
- HDMI_CONFIG2_ID
 
- HDMI_CONFIG3_AHBAUDDMA
 
- HDMI_CONFIG3_GPAUD
 
- HDMI_CONFIG3_ID
 
- HDMI_CONNECTION
 
- HDMI_CONN_CH0
 
- HDMI_CONN_CH1
 
- HDMI_CONN_CH2
 
- HDMI_CONN_CH3
 
- HDMI_CONN_CH4
 
- HDMI_CONN_CH5
 
- HDMI_CONN_CH6
 
- HDMI_CONN_CH7
 
- HDMI_CONTENT_TYPE_CINEMA
 
- HDMI_CONTENT_TYPE_GAME
 
- HDMI_CONTENT_TYPE_GRAPHICS
 
- HDMI_CONTENT_TYPE_PHOTO
 
- HDMI_CONTROL
 
- HDMI_CONTROL_PACKET_ADDR
 
- HDMI_CONTROL_PACKET_BUF_INDEX
 
- HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK
 
- HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT
 
- HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK
 
- HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT
 
- HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
 
- HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
 
- HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
 
- HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT
 
- HDMI_CONTROL__HDMI_ERROR_ACK_MASK
 
- HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT
 
- HDMI_CONTROL__HDMI_ERROR_MASK_MASK
 
- HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT
 
- HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK
 
- HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT
 
- HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK
 
- HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT
 
- HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK
 
- HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT
 
- HDMI_CON_0
 
- HDMI_CON_1
 
- HDMI_CON_2
 
- HDMI_CORECLK_DIV
 
- HDMI_CORE_AUD_CC08
 
- HDMI_CORE_AUD_CONF0
 
- HDMI_CORE_AUD_CONF1
 
- HDMI_CORE_AUD_CTS1
 
- HDMI_CORE_AUD_CTS2
 
- HDMI_CORE_AUD_CTS3
 
- HDMI_CORE_AUD_D010
 
- HDMI_CORE_AUD_GP_CONF0
 
- HDMI_CORE_AUD_GP_CONF1
 
- HDMI_CORE_AUD_GP_CONF2
 
- HDMI_CORE_AUD_GP_INT
 
- HDMI_CORE_AUD_GP_MASK
 
- HDMI_CORE_AUD_GP_POL
 
- HDMI_CORE_AUD_GP_STAT
 
- HDMI_CORE_AUD_INCLKFS
 
- HDMI_CORE_AUD_INT
 
- HDMI_CORE_AUD_N1
 
- HDMI_CORE_AUD_N2
 
- HDMI_CORE_AUD_N3
 
- HDMI_CORE_AV
 
- HDMI_CORE_AV_ACR_CTRL
 
- HDMI_CORE_AV_ASRC
 
- HDMI_CORE_AV_AUDIO_CHSUM
 
- HDMI_CORE_AV_AUDIO_LEN
 
- HDMI_CORE_AV_AUDIO_TYPE
 
- HDMI_CORE_AV_AUDIO_VERS
 
- HDMI_CORE_AV_AUDO_TXSTAT
 
- HDMI_CORE_AV_AUD_DBYTE
 
- HDMI_CORE_AV_AUD_DBYTE_NELEMS
 
- HDMI_CORE_AV_AUD_MODE
 
- HDMI_CORE_AV_AUD_PAR_BUSCLK_1
 
- HDMI_CORE_AV_AUD_PAR_BUSCLK_2
 
- HDMI_CORE_AV_AUD_PAR_BUSCLK_3
 
- HDMI_CORE_AV_AVI_BASE
 
- HDMI_CORE_AV_AVI_CHSUM
 
- HDMI_CORE_AV_AVI_DBYTE
 
- HDMI_CORE_AV_AVI_DBYTE_NELEMS
 
- HDMI_CORE_AV_AVI_LEN
 
- HDMI_CORE_AV_AVI_TYPE
 
- HDMI_CORE_AV_AVI_VERS
 
- HDMI_CORE_AV_CEC_ADDR_ID
 
- HDMI_CORE_AV_CP_BYTE1
 
- HDMI_CORE_AV_CTS_HVAL1
 
- HDMI_CORE_AV_CTS_HVAL2
 
- HDMI_CORE_AV_CTS_HVAL3
 
- HDMI_CORE_AV_CTS_SVAL1
 
- HDMI_CORE_AV_CTS_SVAL2
 
- HDMI_CORE_AV_CTS_SVAL3
 
- HDMI_CORE_AV_DPD
 
- HDMI_CORE_AV_FREQ_SVAL
 
- HDMI_CORE_AV_GEN2_DBYTE
 
- HDMI_CORE_AV_GEN2_DBYTE_ELSIZE
 
- HDMI_CORE_AV_GEN2_DBYTE_NELEMS
 
- HDMI_CORE_AV_GEN_DBYTE
 
- HDMI_CORE_AV_GEN_DBYTE_ELSIZE
 
- HDMI_CORE_AV_GEN_DBYTE_NELEMS
 
- HDMI_CORE_AV_HDMI_CTRL
 
- HDMI_CORE_AV_HW_SPDIF_FS
 
- HDMI_CORE_AV_I2S_CHST0
 
- HDMI_CORE_AV_I2S_CHST1
 
- HDMI_CORE_AV_I2S_CHST2
 
- HDMI_CORE_AV_I2S_CHST4
 
- HDMI_CORE_AV_I2S_CHST5
 
- HDMI_CORE_AV_I2S_IN_CTRL
 
- HDMI_CORE_AV_I2S_IN_LEN
 
- HDMI_CORE_AV_I2S_IN_MAP
 
- HDMI_CORE_AV_MPEG_CHSUM
 
- HDMI_CORE_AV_MPEG_DBYTE
 
- HDMI_CORE_AV_MPEG_DBYTE_ELSIZE
 
- HDMI_CORE_AV_MPEG_DBYTE_NELEMS
 
- HDMI_CORE_AV_MPEG_LEN
 
- HDMI_CORE_AV_MPEG_TYPE
 
- HDMI_CORE_AV_MPEG_VERS
 
- HDMI_CORE_AV_N_SVAL1
 
- HDMI_CORE_AV_N_SVAL2
 
- HDMI_CORE_AV_N_SVAL3
 
- HDMI_CORE_AV_PB_CTRL1
 
- HDMI_CORE_AV_PB_CTRL2
 
- HDMI_CORE_AV_SPDIF_CTRL
 
- HDMI_CORE_AV_SPDIF_ERTH
 
- HDMI_CORE_AV_SPD_CHSUM
 
- HDMI_CORE_AV_SPD_DBYTE
 
- HDMI_CORE_AV_SPD_DBYTE_ELSIZE
 
- HDMI_CORE_AV_SPD_DBYTE_NELEMS
 
- HDMI_CORE_AV_SPD_LEN
 
- HDMI_CORE_AV_SPD_TYPE
 
- HDMI_CORE_AV_SPD_VERS
 
- HDMI_CORE_AV_SWAP_I2S
 
- HDMI_CORE_AV_TEST_TXCTRL
 
- HDMI_CORE_BASE
 
- HDMI_CORE_CEC_MASK
 
- HDMI_CORE_CEC_RETRY
 
- HDMI_CORE_CONFIG0_ID
 
- HDMI_CORE_CONFIG1_ID
 
- HDMI_CORE_CONFIG2_ID
 
- HDMI_CORE_CONFIG3_ID
 
- HDMI_CORE_CSC_CFG
 
- HDMI_CORE_CSC_COEF_A1_LSB
 
- HDMI_CORE_CSC_COEF_A1_MSB
 
- HDMI_CORE_CSC_COEF_A2_LSB
 
- HDMI_CORE_CSC_COEF_A2_MSB
 
- HDMI_CORE_CSC_COEF_A3_LSB
 
- HDMI_CORE_CSC_COEF_A3_MSB
 
- HDMI_CORE_CSC_COEF_A4_LSB
 
- HDMI_CORE_CSC_COEF_A4_MSB
 
- HDMI_CORE_CSC_COEF_B1_LSB
 
- HDMI_CORE_CSC_COEF_B1_MSB
 
- HDMI_CORE_CSC_COEF_B2_LSB
 
- HDMI_CORE_CSC_COEF_B2_MSB
 
- HDMI_CORE_CSC_COEF_B3_LSB
 
- HDMI_CORE_CSC_COEF_B3_MSB
 
- HDMI_CORE_CSC_COEF_B4_LSB
 
- HDMI_CORE_CSC_COEF_B4_MSB
 
- HDMI_CORE_CSC_COEF_C1_LSB
 
- HDMI_CORE_CSC_COEF_C1_MSB
 
- HDMI_CORE_CSC_COEF_C2_LSB
 
- HDMI_CORE_CSC_COEF_C2_MSB
 
- HDMI_CORE_CSC_COEF_C3_LSB
 
- HDMI_CORE_CSC_COEF_C3_MSB
 
- HDMI_CORE_CSC_COEF_C4_LSB
 
- HDMI_CORE_CSC_COEF_C4_MSB
 
- HDMI_CORE_CSC_SCALE
 
- HDMI_CORE_DDC_ADDR
 
- HDMI_CORE_DDC_CMD
 
- HDMI_CORE_DDC_COUNT1
 
- HDMI_CORE_DDC_COUNT2
 
- HDMI_CORE_DDC_DATA
 
- HDMI_CORE_DDC_OFFSET
 
- HDMI_CORE_DDC_SEGM
 
- HDMI_CORE_DDC_STATUS
 
- HDMI_CORE_DESIGN_ID
 
- HDMI_CORE_FC_ACP
 
- HDMI_CORE_FC_ACP0
 
- HDMI_CORE_FC_AUDICONF0
 
- HDMI_CORE_FC_AUDICONF1
 
- HDMI_CORE_FC_AUDICONF2
 
- HDMI_CORE_FC_AUDICONF3
 
- HDMI_CORE_FC_AUDSCHNLS
 
- HDMI_CORE_FC_AUDSCONF
 
- HDMI_CORE_FC_AUDSSTAT
 
- HDMI_CORE_FC_AUDSU
 
- HDMI_CORE_FC_AUDSV
 
- HDMI_CORE_FC_AVICONF0
 
- HDMI_CORE_FC_AVICONF1
 
- HDMI_CORE_FC_AVICONF2
 
- HDMI_CORE_FC_AVICONF3
 
- HDMI_CORE_FC_AVIELB0
 
- HDMI_CORE_FC_AVIELB1
 
- HDMI_CORE_FC_AVIETB0
 
- HDMI_CORE_FC_AVIETB1
 
- HDMI_CORE_FC_AVISBB0
 
- HDMI_CORE_FC_AVISBB1
 
- HDMI_CORE_FC_AVISRB0
 
- HDMI_CORE_FC_AVISRB1
 
- HDMI_CORE_FC_AVIVID
 
- HDMI_CORE_FC_CH0PREAM
 
- HDMI_CORE_FC_CH1PREAM
 
- HDMI_CORE_FC_CH2PREAM
 
- HDMI_CORE_FC_CTRLDUR
 
- HDMI_CORE_FC_CTRLQHIGH
 
- HDMI_CORE_FC_CTRLQLOW
 
- HDMI_CORE_FC_DATAUTO0
 
- HDMI_CORE_FC_DATAUTO1
 
- HDMI_CORE_FC_DATAUTO2
 
- HDMI_CORE_FC_DATAUTO3
 
- HDMI_CORE_FC_DATMAN
 
- HDMI_CORE_FC_DBGAUD0CH0
 
- HDMI_CORE_FC_DBGAUD0CH1
 
- HDMI_CORE_FC_DBGAUD0CH2
 
- HDMI_CORE_FC_DBGAUD0CH3
 
- HDMI_CORE_FC_DBGAUD0CH4
 
- HDMI_CORE_FC_DBGAUD0CH5
 
- HDMI_CORE_FC_DBGAUD0CH6
 
- HDMI_CORE_FC_DBGAUD0CH7
 
- HDMI_CORE_FC_DBGAUD1CH0
 
- HDMI_CORE_FC_DBGAUD1CH1
 
- HDMI_CORE_FC_DBGAUD1CH2
 
- HDMI_CORE_FC_DBGAUD1CH3
 
- HDMI_CORE_FC_DBGAUD1CH4
 
- HDMI_CORE_FC_DBGAUD1CH5
 
- HDMI_CORE_FC_DBGAUD1CH6
 
- HDMI_CORE_FC_DBGAUD1CH7
 
- HDMI_CORE_FC_DBGAUD2CH0
 
- HDMI_CORE_FC_DBGAUD2CH1
 
- HDMI_CORE_FC_DBGAUD2CH2
 
- HDMI_CORE_FC_DBGAUD2CH3
 
- HDMI_CORE_FC_DBGAUD2CH4
 
- HDMI_CORE_FC_DBGAUD2CH5
 
- HDMI_CORE_FC_DBGAUD2CH6
 
- HDMI_CORE_FC_DBGAUD2CH7
 
- HDMI_CORE_FC_DBGFORCE
 
- HDMI_CORE_FC_DBGTMDS0
 
- HDMI_CORE_FC_DBGTMDS1
 
- HDMI_CORE_FC_DBGTMDS2
 
- HDMI_CORE_FC_EXCTRLDUR
 
- HDMI_CORE_FC_EXCTRLSPAC
 
- HDMI_CORE_FC_GCP
 
- HDMI_CORE_FC_GMD_CONF
 
- HDMI_CORE_FC_GMD_EN
 
- HDMI_CORE_FC_GMD_HB
 
- HDMI_CORE_FC_GMD_PB
 
- HDMI_CORE_FC_GMD_STAT
 
- HDMI_CORE_FC_GMD_UP
 
- HDMI_CORE_FC_HSYNCINDELAY0
 
- HDMI_CORE_FC_HSYNCINDELAY1
 
- HDMI_CORE_FC_HSYNCINWIDTH0
 
- HDMI_CORE_FC_HSYNCINWIDTH1
 
- HDMI_CORE_FC_INFREQ0
 
- HDMI_CORE_FC_INFREQ1
 
- HDMI_CORE_FC_INFREQ2
 
- HDMI_CORE_FC_INHACTIV0
 
- HDMI_CORE_FC_INHACTIV1
 
- HDMI_CORE_FC_INHBLANK0
 
- HDMI_CORE_FC_INHBLANK1
 
- HDMI_CORE_FC_INT0
 
- HDMI_CORE_FC_INT1
 
- HDMI_CORE_FC_INT2
 
- HDMI_CORE_FC_INVACTIV0
 
- HDMI_CORE_FC_INVACTIV1
 
- HDMI_CORE_FC_INVBLANK
 
- HDMI_CORE_FC_INVIDCONF
 
- HDMI_CORE_FC_ISCR1
 
- HDMI_CORE_FC_ISCR1_0
 
- HDMI_CORE_FC_ISCR2
 
- HDMI_CORE_FC_MASK0
 
- HDMI_CORE_FC_MASK1
 
- HDMI_CORE_FC_MASK2
 
- HDMI_CORE_FC_POL0
 
- HDMI_CORE_FC_POL1
 
- HDMI_CORE_FC_POL2
 
- HDMI_CORE_FC_PRCONF
 
- HDMI_CORE_FC_RDRB
 
- HDMI_CORE_FC_SPDDEVICEINF
 
- HDMI_CORE_FC_SPDPRODUCTNAME
 
- HDMI_CORE_FC_SPDVENDORNAME
 
- HDMI_CORE_FC_STAT0
 
- HDMI_CORE_FC_STAT1
 
- HDMI_CORE_FC_STAT2
 
- HDMI_CORE_FC_VSDIEEEID0
 
- HDMI_CORE_FC_VSDIEEEID1
 
- HDMI_CORE_FC_VSDIEEEID2
 
- HDMI_CORE_FC_VSDPAYLOAD
 
- HDMI_CORE_FC_VSDSIZE
 
- HDMI_CORE_FC_VSYNCINDELAY
 
- HDMI_CORE_FC_VSYNCINWIDTH
 
- HDMI_CORE_HDCP_MASK
 
- HDMI_CORE_I2CM_ADDRESS
 
- HDMI_CORE_I2CM_CTLINT
 
- HDMI_CORE_I2CM_DATAI
 
- HDMI_CORE_I2CM_DATAO
 
- HDMI_CORE_I2CM_DIV
 
- HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR
 
- HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR
 
- HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR
 
- HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR
 
- HDMI_CORE_I2CM_INT
 
- HDMI_CORE_I2CM_OPERATION
 
- HDMI_CORE_I2CM_SDA_HOLD_ADDR
 
- HDMI_CORE_I2CM_SEGADDR
 
- HDMI_CORE_I2CM_SEGPTR
 
- HDMI_CORE_I2CM_SLAVE
 
- HDMI_CORE_I2CM_SOFTRSTZ
 
- HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR
 
- HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR
 
- HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR
 
- HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR
 
- HDMI_CORE_IH_AS_STAT0
 
- HDMI_CORE_IH_CEC_STAT0
 
- HDMI_CORE_IH_FC_STAT0
 
- HDMI_CORE_IH_FC_STAT1
 
- HDMI_CORE_IH_FC_STAT2
 
- HDMI_CORE_IH_I2CMPHY_STAT0
 
- HDMI_CORE_IH_I2CM_STAT0
 
- HDMI_CORE_IH_MUTE
 
- HDMI_CORE_IH_PHY_STAT0
 
- HDMI_CORE_IH_VP_STAT0
 
- HDMI_CORE_MC_CLKDIS
 
- HDMI_CORE_MC_FLOWCTRL
 
- HDMI_CORE_MC_LOCKONCLOCK
 
- HDMI_CORE_MC_PHYRSTZ
 
- HDMI_CORE_MC_SWRSTZREQ
 
- HDMI_CORE_PHY_I2CM_CTLINT_ADDR
 
- HDMI_CORE_PHY_I2CM_INT_ADDR
 
- HDMI_CORE_PHY_MASK0
 
- HDMI_CORE_PRODUCT_ID0
 
- HDMI_CORE_PRODUCT_ID1
 
- HDMI_CORE_REVISION_ID
 
- HDMI_CORE_RSTOUT
 
- HDMI_CORE_SW_RSTOUT
 
- HDMI_CORE_SYS_B2CB_COEFF_LOW
 
- HDMI_CORE_SYS_B2CB_COEFF_UP
 
- HDMI_CORE_SYS_B2CR_COEFF_LOW
 
- HDMI_CORE_SYS_B2CR_COEFF_UP
 
- HDMI_CORE_SYS_B2Y_COEFF_LOW
 
- HDMI_CORE_SYS_B2Y_COEFF_UP
 
- HDMI_CORE_SYS_CBCR_OFFSET_LOW
 
- HDMI_CORE_SYS_CBCR_OFFSET_UP
 
- HDMI_CORE_SYS_DCTL
 
- HDMI_CORE_SYS_DC_HEADER
 
- HDMI_CORE_SYS_DEV_IDH
 
- HDMI_CORE_SYS_DEV_IDL
 
- HDMI_CORE_SYS_DEV_REV
 
- HDMI_CORE_SYS_DE_CNTH
 
- HDMI_CORE_SYS_DE_CNTL
 
- HDMI_CORE_SYS_DE_CTRL
 
- HDMI_CORE_SYS_DE_DLY
 
- HDMI_CORE_SYS_DE_LINH_1
 
- HDMI_CORE_SYS_DE_LINL
 
- HDMI_CORE_SYS_DE_TOP
 
- HDMI_CORE_SYS_G2CB_COEFF_LOW
 
- HDMI_CORE_SYS_G2CB_COEFF_UP
 
- HDMI_CORE_SYS_G2CR_COEFF_LOW
 
- HDMI_CORE_SYS_G2CR_COEFF_UP
 
- HDMI_CORE_SYS_G2Y_COEFF_LOW
 
- HDMI_CORE_SYS_G2Y_COEFF_UP
 
- HDMI_CORE_SYS_HRES_H
 
- HDMI_CORE_SYS_HRES_L
 
- HDMI_CORE_SYS_HWIDTH1
 
- HDMI_CORE_SYS_HWIDTH2
 
- HDMI_CORE_SYS_IADJUST
 
- HDMI_CORE_SYS_INTR1
 
- HDMI_CORE_SYS_INTR2
 
- HDMI_CORE_SYS_INTR3
 
- HDMI_CORE_SYS_INTR4
 
- HDMI_CORE_SYS_INTR_CTRL
 
- HDMI_CORE_SYS_INTR_STATE
 
- HDMI_CORE_SYS_INTR_UNMASK1
 
- HDMI_CORE_SYS_INTR_UNMASK2
 
- HDMI_CORE_SYS_INTR_UNMASK3
 
- HDMI_CORE_SYS_INTR_UNMASK4
 
- HDMI_CORE_SYS_POLDETECT
 
- HDMI_CORE_SYS_R2CB_COEFF_LOW
 
- HDMI_CORE_SYS_R2CB_COEFF_UP
 
- HDMI_CORE_SYS_R2CR_COEFF_LOW
 
- HDMI_CORE_SYS_R2CR_COEFF_UP
 
- HDMI_CORE_SYS_R2Y_COEFF_LOW
 
- HDMI_CORE_SYS_R2Y_COEFF_UP
 
- HDMI_CORE_SYS_RGB2XVYCC_CT
 
- HDMI_CORE_SYS_RGB_OFFSET_LOW
 
- HDMI_CORE_SYS_RGB_OFFSET_UP
 
- HDMI_CORE_SYS_SRST
 
- HDMI_CORE_SYS_SYS_CTRL1
 
- HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS
 
- HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE
 
- HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC
 
- HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC
 
- HDMI_CORE_SYS_SYS_CTRL3
 
- HDMI_CORE_SYS_SYS_STAT
 
- HDMI_CORE_SYS_TMDS_CTRL
 
- HDMI_CORE_SYS_VID_ACEN
 
- HDMI_CORE_SYS_VID_BLANK1
 
- HDMI_CORE_SYS_VID_BLANK2
 
- HDMI_CORE_SYS_VID_BLANK3
 
- HDMI_CORE_SYS_VID_CTRL
 
- HDMI_CORE_SYS_VID_DITHER
 
- HDMI_CORE_SYS_VID_MODE
 
- HDMI_CORE_SYS_VND_IDL
 
- HDMI_CORE_SYS_VRES_H
 
- HDMI_CORE_SYS_VRES_L
 
- HDMI_CORE_SYS_VWIDTH
 
- HDMI_CORE_SYS_Y_OFFSET_LOW
 
- HDMI_CORE_SYS_Y_OFFSET_UP
 
- HDMI_CORE_TX_BCBDATA0
 
- HDMI_CORE_TX_BCBDATA1
 
- HDMI_CORE_TX_INSTUFFING
 
- HDMI_CORE_TX_INVID0
 
- HDMI_CORE_TX_RCRDATA0
 
- HDMI_CORE_TX_RCRDATA1
 
- HDMI_CORE_TX_RGYDATA0
 
- HDMI_CORE_TX_RGYDATA1
 
- HDMI_CORE_VP_CONF
 
- HDMI_CORE_VP_INT
 
- HDMI_CORE_VP_MASK
 
- HDMI_CORE_VP_POL
 
- HDMI_CORE_VP_PR_CD
 
- HDMI_CORE_VP_REMAP
 
- HDMI_CORE_VP_STAT
 
- HDMI_CORE_VP_STATUS
 
- HDMI_CORE_VP_STUFF
 
- HDMI_CP_AUTO_SEND_CTRL
 
- HDMI_CP_BUF_ACC_HB0
 
- HDMI_CP_BUF_ACC_HB1
 
- HDMI_CP_BUF_ACC_HB2
 
- HDMI_CP_BUF_ACC_PB0
 
- HDMI_CP_BUF_INDEX
 
- HDMI_CP_MANU_SEND_CTRL
 
- HDMI_CSC_CFG
 
- HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1
 
- HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2
 
- HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3
 
- HDMI_CSC_CFG_DECMODE_DISABLE
 
- HDMI_CSC_CFG_DECMODE_MASK
 
- HDMI_CSC_CFG_DECMODE_OFFSET
 
- HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1
 
- HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2
 
- HDMI_CSC_CFG_INTMODE_DISABLE
 
- HDMI_CSC_CFG_INTMODE_MASK
 
- HDMI_CSC_CFG_INTMODE_OFFSET
 
- HDMI_CSC_COEF_A1_LSB
 
- HDMI_CSC_COEF_A1_MSB
 
- HDMI_CSC_COEF_A2_LSB
 
- HDMI_CSC_COEF_A2_MSB
 
- HDMI_CSC_COEF_A3_LSB
 
- HDMI_CSC_COEF_A3_MSB
 
- HDMI_CSC_COEF_A4_LSB
 
- HDMI_CSC_COEF_A4_MSB
 
- HDMI_CSC_COEF_B1_LSB
 
- HDMI_CSC_COEF_B1_MSB
 
- HDMI_CSC_COEF_B2_LSB
 
- HDMI_CSC_COEF_B2_MSB
 
- HDMI_CSC_COEF_B3_LSB
 
- HDMI_CSC_COEF_B3_MSB
 
- HDMI_CSC_COEF_B4_LSB
 
- HDMI_CSC_COEF_B4_MSB
 
- HDMI_CSC_COEF_C1_LSB
 
- HDMI_CSC_COEF_C1_MSB
 
- HDMI_CSC_COEF_C2_LSB
 
- HDMI_CSC_COEF_C2_MSB
 
- HDMI_CSC_COEF_C3_LSB
 
- HDMI_CSC_COEF_C3_MSB
 
- HDMI_CSC_COEF_C4_LSB
 
- HDMI_CSC_COEF_C4_MSB
 
- HDMI_CSC_SCALE
 
- HDMI_CSC_SCALE_CSCSCALE_MASK
 
- HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP
 
- HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP
 
- HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP
 
- HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP
 
- HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK
 
- HDMI_CTRL_BASE
 
- HDMI_CTRL_ENABLE
 
- HDMI_CTRL_ENCRYPTED
 
- HDMI_CTRL_HDCP_AUTO
 
- HDMI_CTRL_HDCP_EESS
 
- HDMI_CTRL_HDCP_MASK
 
- HDMI_CTRL_HDCP_OESS
 
- HDMI_CTRL_HDCP_SHIFT
 
- HDMI_CTRL_HDMI
 
- HDMI_CTRL_MAX_AC_PACKET
 
- HDMI_CTRL_MUTE_AUTO
 
- HDMI_CTRL_MUTE_MASK
 
- HDMI_CTRL_MUTE_OFF
 
- HDMI_CTRL_MUTE_ON
 
- HDMI_CTRL_MUTE_SHIFT
 
- HDMI_CTRL_REKEY
 
- HDMI_CTS_EXT1
 
- HDMI_CTS_EXT2
 
- HDMI_CTS_EXT3
 
- HDMI_CTS_INT1
 
- HDMI_CTS_INT2
 
- HDMI_CTXSW
 
- HDMI_DATA_SCRAMBLE_DISABLE
 
- HDMI_DATA_SCRAMBLE_EN
 
- HDMI_DATA_SCRAMBLE_ENABLE
 
- HDMI_DC_CONTROL
 
- HDMI_DDC_ARBITRATION_HW_ARBITRATION
 
- HDMI_DDC_BUS_CTRL
 
- HDMI_DDC_BUS_FREQ_H
 
- HDMI_DDC_BUS_FREQ_L
 
- HDMI_DDC_CLK_H
 
- HDMI_DDC_CLK_L
 
- HDMI_DDC_CTRL_GO
 
- HDMI_DDC_CTRL_SEND_RESET
 
- HDMI_DDC_CTRL_SOFT_RESET
 
- HDMI_DDC_CTRL_SW_STATUS_RESET
 
- HDMI_DDC_CTRL_TRANSACTION_CNT
 
- HDMI_DDC_CTRL_TRANSACTION_CNT__MASK
 
- HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT
 
- HDMI_DDC_DATA_DATA
 
- HDMI_DDC_DATA_DATA_RW
 
- HDMI_DDC_DATA_DATA_RW__MASK
 
- HDMI_DDC_DATA_DATA_RW__SHIFT
 
- HDMI_DDC_DATA_DATA__MASK
 
- HDMI_DDC_DATA_DATA__SHIFT
 
- HDMI_DDC_DATA_INDEX
 
- HDMI_DDC_DATA_INDEX_WRITE
 
- HDMI_DDC_DATA_INDEX__MASK
 
- HDMI_DDC_DATA_INDEX__SHIFT
 
- HDMI_DDC_HW_STATUS_DONE
 
- HDMI_DDC_I2C_CTRL
 
- HDMI_DDC_I2C_LEN
 
- HDMI_DDC_I2C_OFFSET
 
- HDMI_DDC_I2C_READ_BUF0
 
- HDMI_DDC_I2C_READ_BUF1
 
- HDMI_DDC_I2C_READ_BUF2
 
- HDMI_DDC_I2C_READ_BUF3
 
- HDMI_DDC_I2C_WRITE_BUF0
 
- HDMI_DDC_I2C_WRITE_BUF1
 
- HDMI_DDC_I2C_WRITE_BUF2
 
- HDMI_DDC_I2C_WRITE_BUF3
 
- HDMI_DDC_I2C_WRITE_BUF4
 
- HDMI_DDC_I2C_WRITE_BUF5
 
- HDMI_DDC_I2C_WRITE_BUF6
 
- HDMI_DDC_INT_CTRL_SW_DONE_ACK
 
- HDMI_DDC_INT_CTRL_SW_DONE_INT
 
- HDMI_DDC_INT_CTRL_SW_DONE_MASK
 
- HDMI_DDC_READ_FIFO_ADDR
 
- HDMI_DDC_REF_REFTIMER
 
- HDMI_DDC_REF_REFTIMER_ENABLE
 
- HDMI_DDC_REF_REFTIMER__MASK
 
- HDMI_DDC_REF_REFTIMER__SHIFT
 
- HDMI_DDC_SETUP_TIMEOUT
 
- HDMI_DDC_SETUP_TIMEOUT__MASK
 
- HDMI_DDC_SETUP_TIMEOUT__SHIFT
 
- HDMI_DDC_SPEED_PRESCALE
 
- HDMI_DDC_SPEED_PRESCALE__MASK
 
- HDMI_DDC_SPEED_PRESCALE__SHIFT
 
- HDMI_DDC_SPEED_THRESHOLD
 
- HDMI_DDC_SPEED_THRESHOLD__MASK
 
- HDMI_DDC_SPEED_THRESHOLD__SHIFT
 
- HDMI_DDC_SW_STATUS_NACK0
 
- HDMI_DDC_SW_STATUS_NACK1
 
- HDMI_DDC_SW_STATUS_NACK2
 
- HDMI_DDC_SW_STATUS_NACK3
 
- HDMI_DEEPCOLORPACKECTDISABLE
 
- HDMI_DEEPCOLORPACKECTENABLE
 
- HDMI_DEEP_COLOR_DEPTH
 
- HDMI_DEEP_COLOR_DEPTH_24BPP
 
- HDMI_DEEP_COLOR_DEPTH_30BPP
 
- HDMI_DEEP_COLOR_DEPTH_36BPP
 
- HDMI_DEEP_COLOR_DEPTH_48BPP
 
- HDMI_DEEP_COLOR_DEPTH_MASK
 
- HDMI_DEEP_COLOR_DEPTH_RESERVED
 
- HDMI_DEEP_COLOR_ENABLE
 
- HDMI_DEEP_COLOR_MODE
 
- HDMI_DEFAULT_INT
 
- HDMI_DEFAULT_PAHSE
 
- HDMI_DEFAULT_PHASE_IS_0
 
- HDMI_DEFAULT_PHASE_IS_1
 
- HDMI_DEFAULT_REF_CLOCK
 
- HDMI_DELAY
 
- HDMI_DESIGN_ID
 
- HDMI_DET
 
- HDMI_DETECT_HDP
 
- HDMI_DFLT_CHL0_DAT
 
- HDMI_DFLT_CHL1_DAT
 
- HDMI_DFLT_CHL2_DAT
 
- HDMI_DIG_FREQ_BIT_CLK_THRESHOLD
 
- HDMI_DIV_CLK
 
- HDMI_DP_CORE_SELECT
 
- HDMI_DRM_INFOFRAME_SIZE
 
- HDMI_DSP_A
 
- HDMI_DSP_B
 
- HDMI_DVI
 
- HDMI_EDID_FIFO_ADDR
 
- HDMI_EDID_FIFO_OFFSET
 
- HDMI_EDID_LEN
 
- HDMI_EDID_SEGMENT_POINTER
 
- HDMI_EDID_WORD_ADDR
 
- HDMI_ELD_BUFFER_SIZE
 
- HDMI_EN
 
- HDMI_ENABLE
 
- HDMI_ENABLE_AUDIO
 
- HDMI_ENC_EN
 
- HDMI_EOTF_BT_2100_HLG
 
- HDMI_EOTF_SMPTE_ST2084
 
- HDMI_EOTF_TRADITIONAL_GAMMA_HDR
 
- HDMI_EOTF_TRADITIONAL_GAMMA_SDR
 
- HDMI_ERROR_ACK
 
- HDMI_ERROR_ACK_INT
 
- HDMI_ERROR_MASK
 
- HDMI_ERROR_MASK_INT
 
- HDMI_ERROR_NOT_ACK
 
- HDMI_ERROR_NOT_MASK
 
- HDMI_EXTENDED_COLORIMETRY_BT2020
 
- HDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM
 
- HDMI_EXTENDED_COLORIMETRY_OPRGB
 
- HDMI_EXTENDED_COLORIMETRY_OPYCC_601
 
- HDMI_EXTENDED_COLORIMETRY_RESERVED
 
- HDMI_EXTENDED_COLORIMETRY_S_YCC_601
 
- HDMI_EXTENDED_COLORIMETRY_XV_YCC_601
 
- HDMI_EXTENDED_COLORIMETRY_XV_YCC_709
 
- HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE
 
- HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE
 
- HDMI_EXT_HBLANK_H
 
- HDMI_EXT_HBLANK_L
 
- HDMI_EXT_HDELAY_H
 
- HDMI_EXT_HDELAY_L
 
- HDMI_EXT_HDURATION_H
 
- HDMI_EXT_HDURATION_L
 
- HDMI_EXT_HTOTAL_H
 
- HDMI_EXT_HTOTAL_L
 
- HDMI_EXT_VBLANK_H
 
- HDMI_EXT_VBLANK_L
 
- HDMI_EXT_VDELAY
 
- HDMI_EXT_VDURATION
 
- HDMI_EXT_VIDEO_PARA
 
- HDMI_EXT_VIDEO_SET_EN
 
- HDMI_EXT_VTOTAL_H
 
- HDMI_EXT_VTOTAL_L
 
- HDMI_FC_ACP0
 
- HDMI_FC_ACP1
 
- HDMI_FC_ACP10
 
- HDMI_FC_ACP11
 
- HDMI_FC_ACP12
 
- HDMI_FC_ACP13
 
- HDMI_FC_ACP14
 
- HDMI_FC_ACP15
 
- HDMI_FC_ACP16
 
- HDMI_FC_ACP17
 
- HDMI_FC_ACP18
 
- HDMI_FC_ACP19
 
- HDMI_FC_ACP2
 
- HDMI_FC_ACP20
 
- HDMI_FC_ACP21
 
- HDMI_FC_ACP22
 
- HDMI_FC_ACP23
 
- HDMI_FC_ACP24
 
- HDMI_FC_ACP25
 
- HDMI_FC_ACP26
 
- HDMI_FC_ACP27
 
- HDMI_FC_ACP28
 
- HDMI_FC_ACP3
 
- HDMI_FC_ACP4
 
- HDMI_FC_ACP5
 
- HDMI_FC_ACP6
 
- HDMI_FC_ACP7
 
- HDMI_FC_ACP8
 
- HDMI_FC_ACP9
 
- HDMI_FC_AUDICONF0
 
- HDMI_FC_AUDICONF0_CC_MASK
 
- HDMI_FC_AUDICONF0_CC_OFFSET
 
- HDMI_FC_AUDICONF0_CT_MASK
 
- HDMI_FC_AUDICONF0_CT_OFFSET
 
- HDMI_FC_AUDICONF1
 
- HDMI_FC_AUDICONF1_SF_MASK
 
- HDMI_FC_AUDICONF1_SF_OFFSET
 
- HDMI_FC_AUDICONF1_SS_MASK
 
- HDMI_FC_AUDICONF1_SS_OFFSET
 
- HDMI_FC_AUDICONF2
 
- HDMI_FC_AUDICONF3
 
- HDMI_FC_AUDICONF3_DM_INH_MASK
 
- HDMI_FC_AUDICONF3_DM_INH_OFFSET
 
- HDMI_FC_AUDICONF3_LFEPBL_MASK
 
- HDMI_FC_AUDICONF3_LFEPBL_OFFSET
 
- HDMI_FC_AUDICONF3_LSV_MASK
 
- HDMI_FC_AUDICONF3_LSV_OFFSET
 
- HDMI_FC_AUDSCHNLS0_CGMSA_MASK
 
- HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET
 
- HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK
 
- HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET
 
- HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK
 
- HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET
 
- HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK
 
- HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET
 
- HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK
 
- HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET
 
- HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK
 
- HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET
 
- HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK
 
- HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET
 
- HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK
 
- HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET
 
- HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK
 
- HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET
 
- HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK
 
- HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET
 
- HDMI_FC_AUDSCHNLS7_ACCURACY_MASK
 
- HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET
 
- HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK
 
- HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET
 
- HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK
 
- HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET
 
- HDMI_FC_AUDSCONF
 
- HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0
 
- HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1
 
- HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK
 
- HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET
 
- HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK
 
- HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET
 
- HDMI_FC_AUDSSTAT
 
- HDMI_FC_AVICONF0
 
- HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT
 
- HDMI_FC_AVICONF0_ACTIVE_FMT_MASK
 
- HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO
 
- HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR
 
- HDMI_FC_AVICONF0_BAR_DATA_MASK
 
- HDMI_FC_AVICONF0_BAR_DATA_NO_DATA
 
- HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR
 
- HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR
 
- HDMI_FC_AVICONF0_PIX_FMT_MASK
 
- HDMI_FC_AVICONF0_PIX_FMT_RGB
 
- HDMI_FC_AVICONF0_PIX_FMT_YCBCR422
 
- HDMI_FC_AVICONF0_PIX_FMT_YCBCR444
 
- HDMI_FC_AVICONF0_SCAN_INFO_MASK
 
- HDMI_FC_AVICONF0_SCAN_INFO_NODATA
 
- HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN
 
- HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN
 
- HDMI_FC_AVICONF1
 
- HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9
 
- HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9
 
- HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3
 
- HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK
 
- HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED
 
- HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9
 
- HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3
 
- HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK
 
- HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA
 
- HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO
 
- HDMI_FC_AVICONF1_COLORIMETRY_ITUR
 
- HDMI_FC_AVICONF1_COLORIMETRY_MASK
 
- HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA
 
- HDMI_FC_AVICONF1_COLORIMETRY_SMPTE
 
- HDMI_FC_AVICONF2
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601
 
- HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709
 
- HDMI_FC_AVICONF2_IT_CONTENT_MASK
 
- HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA
 
- HDMI_FC_AVICONF2_IT_CONTENT_VALID
 
- HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT
 
- HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE
 
- HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE
 
- HDMI_FC_AVICONF2_RGB_QUANT_MASK
 
- HDMI_FC_AVICONF2_SCALING_HORIZ
 
- HDMI_FC_AVICONF2_SCALING_HORIZ_VERT
 
- HDMI_FC_AVICONF2_SCALING_MASK
 
- HDMI_FC_AVICONF2_SCALING_NONE
 
- HDMI_FC_AVICONF2_SCALING_VERT
 
- HDMI_FC_AVICONF3
 
- HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA
 
- HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME
 
- HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS
 
- HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK
 
- HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO
 
- HDMI_FC_AVICONF3_QUANT_RANGE_FULL
 
- HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED
 
- HDMI_FC_AVICONF3_QUANT_RANGE_MASK
 
- HDMI_FC_AVIELB0
 
- HDMI_FC_AVIELB1
 
- HDMI_FC_AVIETB0
 
- HDMI_FC_AVIETB1
 
- HDMI_FC_AVISBB0
 
- HDMI_FC_AVISBB1
 
- HDMI_FC_AVISRB0
 
- HDMI_FC_AVISRB1
 
- HDMI_FC_AVIVID
 
- HDMI_FC_CH0PREAM
 
- HDMI_FC_CH1PREAM
 
- HDMI_FC_CH2PREAM
 
- HDMI_FC_CTRLDUR
 
- HDMI_FC_CTRLQHIGH
 
- HDMI_FC_CTRLQLOW
 
- HDMI_FC_DATACH0FILL
 
- HDMI_FC_DATACH1FILL
 
- HDMI_FC_DATACH2FILL
 
- HDMI_FC_DATAUTO0
 
- HDMI_FC_DATAUTO0_VSD_MASK
 
- HDMI_FC_DATAUTO0_VSD_OFFSET
 
- HDMI_FC_DATAUTO1
 
- HDMI_FC_DATAUTO2
 
- HDMI_FC_DATAUTO3
 
- HDMI_FC_DATMAN
 
- HDMI_FC_DBGAUD0CH0
 
- HDMI_FC_DBGAUD0CH1
 
- HDMI_FC_DBGAUD0CH2
 
- HDMI_FC_DBGAUD0CH3
 
- HDMI_FC_DBGAUD0CH4
 
- HDMI_FC_DBGAUD0CH5
 
- HDMI_FC_DBGAUD0CH6
 
- HDMI_FC_DBGAUD0CH7
 
- HDMI_FC_DBGAUD1CH0
 
- HDMI_FC_DBGAUD1CH1
 
- HDMI_FC_DBGAUD1CH2
 
- HDMI_FC_DBGAUD1CH3
 
- HDMI_FC_DBGAUD1CH4
 
- HDMI_FC_DBGAUD1CH5
 
- HDMI_FC_DBGAUD1CH6
 
- HDMI_FC_DBGAUD1CH7
 
- HDMI_FC_DBGAUD2CH0
 
- HDMI_FC_DBGAUD2CH1
 
- HDMI_FC_DBGAUD2CH2
 
- HDMI_FC_DBGAUD2CH3
 
- HDMI_FC_DBGAUD2CH4
 
- HDMI_FC_DBGAUD2CH5
 
- HDMI_FC_DBGAUD2CH6
 
- HDMI_FC_DBGAUD2CH7
 
- HDMI_FC_DBGFORCE
 
- HDMI_FC_DBGFORCE_FORCEAUDIO
 
- HDMI_FC_DBGFORCE_FORCEVIDEO
 
- HDMI_FC_DBGTMDS0
 
- HDMI_FC_DBGTMDS1
 
- HDMI_FC_DBGTMDS2
 
- HDMI_FC_EXCTRLDUR
 
- HDMI_FC_EXCTRLSPAC
 
- HDMI_FC_GCP
 
- HDMI_FC_GMD_CONF
 
- HDMI_FC_GMD_EN
 
- HDMI_FC_GMD_HB
 
- HDMI_FC_GMD_PB0
 
- HDMI_FC_GMD_PB1
 
- HDMI_FC_GMD_PB10
 
- HDMI_FC_GMD_PB11
 
- HDMI_FC_GMD_PB12
 
- HDMI_FC_GMD_PB13
 
- HDMI_FC_GMD_PB14
 
- HDMI_FC_GMD_PB15
 
- HDMI_FC_GMD_PB16
 
- HDMI_FC_GMD_PB17
 
- HDMI_FC_GMD_PB18
 
- HDMI_FC_GMD_PB19
 
- HDMI_FC_GMD_PB2
 
- HDMI_FC_GMD_PB20
 
- HDMI_FC_GMD_PB21
 
- HDMI_FC_GMD_PB22
 
- HDMI_FC_GMD_PB23
 
- HDMI_FC_GMD_PB24
 
- HDMI_FC_GMD_PB25
 
- HDMI_FC_GMD_PB26
 
- HDMI_FC_GMD_PB27
 
- HDMI_FC_GMD_PB3
 
- HDMI_FC_GMD_PB4
 
- HDMI_FC_GMD_PB5
 
- HDMI_FC_GMD_PB6
 
- HDMI_FC_GMD_PB7
 
- HDMI_FC_GMD_PB8
 
- HDMI_FC_GMD_PB9
 
- HDMI_FC_GMD_STAT
 
- HDMI_FC_GMD_UP
 
- HDMI_FC_HSYNCINDELAY0
 
- HDMI_FC_HSYNCINDELAY1
 
- HDMI_FC_HSYNCINWIDTH0
 
- HDMI_FC_HSYNCINWIDTH1
 
- HDMI_FC_INFREQ0
 
- HDMI_FC_INFREQ1
 
- HDMI_FC_INFREQ2
 
- HDMI_FC_INHACTV0
 
- HDMI_FC_INHACTV1
 
- HDMI_FC_INHBLANK0
 
- HDMI_FC_INHBLANK1
 
- HDMI_FC_INT0
 
- HDMI_FC_INT1
 
- HDMI_FC_INT2
 
- HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW
 
- HDMI_FC_INT2_OVERFLOW_MASK
 
- HDMI_FC_INVACTV0
 
- HDMI_FC_INVACTV1
 
- HDMI_FC_INVBLANK
 
- HDMI_FC_INVIDCONF
 
- HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH
 
- HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW
 
- HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK
 
- HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE
 
- HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE
 
- HDMI_FC_INVIDCONF_DVI_MODEZ_MASK
 
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE
 
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE
 
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK
 
- HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH
 
- HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW
 
- HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK
 
- HDMI_FC_INVIDCONF_IN_I_P_INTERLACED
 
- HDMI_FC_INVIDCONF_IN_I_P_MASK
 
- HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE
 
- HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH
 
- HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW
 
- HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK
 
- HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH
 
- HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW
 
- HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK
 
- HDMI_FC_ISCR1_0
 
- HDMI_FC_ISCR1_1
 
- HDMI_FC_ISCR1_10
 
- HDMI_FC_ISCR1_11
 
- HDMI_FC_ISCR1_12
 
- HDMI_FC_ISCR1_13
 
- HDMI_FC_ISCR1_14
 
- HDMI_FC_ISCR1_15
 
- HDMI_FC_ISCR1_16
 
- HDMI_FC_ISCR1_2
 
- HDMI_FC_ISCR1_3
 
- HDMI_FC_ISCR1_4
 
- HDMI_FC_ISCR1_5
 
- HDMI_FC_ISCR1_6
 
- HDMI_FC_ISCR1_7
 
- HDMI_FC_ISCR1_8
 
- HDMI_FC_ISCR1_9
 
- HDMI_FC_ISCR2_0
 
- HDMI_FC_ISCR2_1
 
- HDMI_FC_ISCR2_10
 
- HDMI_FC_ISCR2_11
 
- HDMI_FC_ISCR2_12
 
- HDMI_FC_ISCR2_13
 
- HDMI_FC_ISCR2_14
 
- HDMI_FC_ISCR2_15
 
- HDMI_FC_ISCR2_2
 
- HDMI_FC_ISCR2_3
 
- HDMI_FC_ISCR2_4
 
- HDMI_FC_ISCR2_5
 
- HDMI_FC_ISCR2_6
 
- HDMI_FC_ISCR2_7
 
- HDMI_FC_ISCR2_8
 
- HDMI_FC_ISCR2_9
 
- HDMI_FC_MASK0
 
- HDMI_FC_MASK1
 
- HDMI_FC_MASK2
 
- HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW
 
- HDMI_FC_MASK2_OVERFLOW_MASK
 
- HDMI_FC_POL0
 
- HDMI_FC_POL1
 
- HDMI_FC_POL2
 
- HDMI_FC_PRCONF
 
- HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK
 
- HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET
 
- HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK
 
- HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET
 
- HDMI_FC_RDRB0
 
- HDMI_FC_RDRB1
 
- HDMI_FC_RDRB2
 
- HDMI_FC_RDRB3
 
- HDMI_FC_RDRB4
 
- HDMI_FC_RDRB5
 
- HDMI_FC_RDRB6
 
- HDMI_FC_RDRB7
 
- HDMI_FC_SCRAMBLER_CTRL
 
- HDMI_FC_SDPPRODUCTNAME0
 
- HDMI_FC_SDPPRODUCTNAME1
 
- HDMI_FC_SDPPRODUCTNAME10
 
- HDMI_FC_SDPPRODUCTNAME11
 
- HDMI_FC_SDPPRODUCTNAME12
 
- HDMI_FC_SDPPRODUCTNAME13
 
- HDMI_FC_SDPPRODUCTNAME14
 
- HDMI_FC_SDPPRODUCTNAME2
 
- HDMI_FC_SDPPRODUCTNAME3
 
- HDMI_FC_SDPPRODUCTNAME4
 
- HDMI_FC_SDPPRODUCTNAME5
 
- HDMI_FC_SDPPRODUCTNAME6
 
- HDMI_FC_SDPPRODUCTNAME7
 
- HDMI_FC_SDPPRODUCTNAME8
 
- HDMI_FC_SDPPRODUCTNAME9
 
- HDMI_FC_SPDDEVICEINF
 
- HDMI_FC_SPDPRODUCTNAME15
 
- HDMI_FC_SPDVENDORNAME0
 
- HDMI_FC_SPDVENDORNAME1
 
- HDMI_FC_SPDVENDORNAME2
 
- HDMI_FC_SPDVENDORNAME3
 
- HDMI_FC_SPDVENDORNAME4
 
- HDMI_FC_SPDVENDORNAME5
 
- HDMI_FC_SPDVENDORNAME6
 
- HDMI_FC_SPDVENDORNAME7
 
- HDMI_FC_STAT0
 
- HDMI_FC_STAT1
 
- HDMI_FC_STAT2
 
- HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW
 
- HDMI_FC_STAT2_OVERFLOW_MASK
 
- HDMI_FC_VSDIEEEID0
 
- HDMI_FC_VSDIEEEID1
 
- HDMI_FC_VSDIEEEID2
 
- HDMI_FC_VSDPAYLOAD0
 
- HDMI_FC_VSDPAYLOAD1
 
- HDMI_FC_VSDPAYLOAD10
 
- HDMI_FC_VSDPAYLOAD11
 
- HDMI_FC_VSDPAYLOAD12
 
- HDMI_FC_VSDPAYLOAD13
 
- HDMI_FC_VSDPAYLOAD14
 
- HDMI_FC_VSDPAYLOAD15
 
- HDMI_FC_VSDPAYLOAD16
 
- HDMI_FC_VSDPAYLOAD17
 
- HDMI_FC_VSDPAYLOAD18
 
- HDMI_FC_VSDPAYLOAD19
 
- HDMI_FC_VSDPAYLOAD2
 
- HDMI_FC_VSDPAYLOAD20
 
- HDMI_FC_VSDPAYLOAD21
 
- HDMI_FC_VSDPAYLOAD22
 
- HDMI_FC_VSDPAYLOAD23
 
- HDMI_FC_VSDPAYLOAD3
 
- HDMI_FC_VSDPAYLOAD4
 
- HDMI_FC_VSDPAYLOAD5
 
- HDMI_FC_VSDPAYLOAD6
 
- HDMI_FC_VSDPAYLOAD7
 
- HDMI_FC_VSDPAYLOAD8
 
- HDMI_FC_VSDPAYLOAD9
 
- HDMI_FC_VSDSIZE
 
- HDMI_FC_VSYNCINDELAY
 
- HDMI_FC_VSYNCINWIDTH
 
- HDMI_FIELD_EN
 
- HDMI_FLAGS_AUDIO
 
- HDMI_FLAGS_AUD_FIFO_LOW
 
- HDMI_FLAGS_AUD_FIFO_OF
 
- HDMI_FLAGS_AUD_LAYOUT
 
- HDMI_FLAGS_AVMUTE
 
- HDMI_FLAGS_EESS
 
- HDMI_FLAGS_HDCP
 
- HDMI_FLAGS_HDMI
 
- HDMI_FORUM_IEEE_OUI
 
- HDMI_FPLL05IDCK
 
- HDMI_FPLL10IDCK
 
- HDMI_FPLL20IDCK
 
- HDMI_FPLL40IDCK
 
- HDMI_FRAC_MAX_G12A
 
- HDMI_FRAC_MAX_GXBB
 
- HDMI_FRAC_MAX_GXL
 
- HDMI_FRAME_CTRL_HSYNC_LOW
 
- HDMI_FRAME_CTRL_INTERLACED_EN
 
- HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR
 
- HDMI_FRAME_CTRL_VSYNC_LOW
 
- HDMI_FULL_INT_CLR
 
- HDMI_GAMUT_CON
 
- HDMI_GAMUT_HEADER0
 
- HDMI_GAMUT_HEADER1
 
- HDMI_GAMUT_HEADER2
 
- HDMI_GAMUT_METADATA
 
- HDMI_GC
 
- HDMI_GCP_BYTE1
 
- HDMI_GCP_BYTE2
 
- HDMI_GCP_BYTE3
 
- HDMI_GCP_CON
 
- HDMI_GC_AVMUTE
 
- HDMI_GC_AVMUTE_CONT
 
- HDMI_GC_AVMUTE_CONT_DISABLE
 
- HDMI_GC_AVMUTE_CONT_ENABLE
 
- HDMI_GC_AVMUTE_SET
 
- HDMI_GC_AVMUTE_UNSET
 
- HDMI_GC_CONT
 
- HDMI_GC_CONT_DISABLE
 
- HDMI_GC_CONT_ENABLE
 
- HDMI_GC_MUTE
 
- HDMI_GC_NOT_SEND
 
- HDMI_GC_PKT_SEND
 
- HDMI_GC_SEND
 
- HDMI_GC__HDMI_DEFAULT_PHASE_MASK
 
- HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT
 
- HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK
 
- HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT
 
- HDMI_GC__HDMI_GC_AVMUTE_MASK
 
- HDMI_GC__HDMI_GC_AVMUTE__SHIFT
 
- HDMI_GC__HDMI_PACKING_PHASE_MASK
 
- HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK
 
- HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT
 
- HDMI_GC__HDMI_PACKING_PHASE__SHIFT
 
- HDMI_GENERIC0_CONT
 
- HDMI_GENERIC0_CONT_DISABLE
 
- HDMI_GENERIC0_CONT_ENABLE
 
- HDMI_GENERIC0_LINE
 
- HDMI_GENERIC0_NOT_SEND
 
- HDMI_GENERIC0_PKT_SEND
 
- HDMI_GENERIC0_SEND
 
- HDMI_GENERIC1_CONT
 
- HDMI_GENERIC1_CONT_DISABLE
 
- HDMI_GENERIC1_CONT_ENABLE
 
- HDMI_GENERIC1_LINE
 
- HDMI_GENERIC1_NOT_SEND
 
- HDMI_GENERIC1_PKT_SEND
 
- HDMI_GENERIC1_SEND
 
- HDMI_GENERIC2_CONT
 
- HDMI_GENERIC2_CONT_DISABLE
 
- HDMI_GENERIC2_CONT_ENABLE
 
- HDMI_GENERIC2_NOT_SEND
 
- HDMI_GENERIC2_PKT_SEND
 
- HDMI_GENERIC2_SEND
 
- HDMI_GENERIC3_CONT
 
- HDMI_GENERIC3_CONT_DISABLE
 
- HDMI_GENERIC3_CONT_ENABLE
 
- HDMI_GENERIC3_NOT_SEND
 
- HDMI_GENERIC3_PKT_SEND
 
- HDMI_GENERIC3_SEND
 
- HDMI_GENERIC_CONT
 
- HDMI_GENERIC_CONT_DISABLE
 
- HDMI_GENERIC_CONT_ENABLE
 
- HDMI_GENERIC_NOT_SEND
 
- HDMI_GENERIC_PACKET_CONTROL
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK
 
- HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK
 
- HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT
 
- HDMI_GENERIC_PKT_SEND
 
- HDMI_GENERIC_SEND
 
- HDMI_GEN_PKT_CTRL_GENERIC0_CONT
 
- HDMI_GEN_PKT_CTRL_GENERIC0_LINE
 
- HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK
 
- HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT
 
- HDMI_GEN_PKT_CTRL_GENERIC0_SEND
 
- HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE
 
- HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK
 
- HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT
 
- HDMI_GEN_PKT_CTRL_GENERIC1_CONT
 
- HDMI_GEN_PKT_CTRL_GENERIC1_LINE
 
- HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK
 
- HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT
 
- HDMI_GEN_PKT_CTRL_GENERIC1_SEND
 
- HDMI_GP_CONF0
 
- HDMI_GP_CONF1
 
- HDMI_GP_CONF2
 
- HDMI_GP_INT
 
- HDMI_GP_MASK
 
- HDMI_GP_POL
 
- HDMI_GP_STAT
 
- HDMI_GUARD_BAND_DIS
 
- HDMI_HBLANK_A
 
- HDMI_HCR
 
- HDMI_HDCP_AKSV
 
- HDMI_HDCP_AN
 
- HDMI_HDCP_AN_INT
 
- HDMI_HDCP_BCAPS
 
- HDMI_HDCP_BKSV
 
- HDMI_HDCP_BSTATUS_0
 
- HDMI_HDCP_BSTATUS_1
 
- HDMI_HDCP_CHECK_RESULT
 
- HDMI_HDCP_CTRL
 
- HDMI_HDCP_CTRL1
 
- HDMI_HDCP_CTRL2
 
- HDMI_HDCP_CTRL_ENABLE
 
- HDMI_HDCP_CTRL_ENCRYPTION_ENABLE
 
- HDMI_HDCP_DDC_CTRL_0_DISABLE
 
- HDMI_HDCP_DDC_CTRL_1_FAILED_ACK
 
- HDMI_HDCP_DDC_STATUS_ABORTED
 
- HDMI_HDCP_DDC_STATUS_FAILED
 
- HDMI_HDCP_DDC_STATUS_NACK0
 
- HDMI_HDCP_DDC_STATUS_NACK1
 
- HDMI_HDCP_DDC_STATUS_TIMEOUT
 
- HDMI_HDCP_DDC_STATUS_XFER_DONE
 
- HDMI_HDCP_DDC_STATUS_XFER_REQ
 
- HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER
 
- HDMI_HDCP_FRAME_COUNT
 
- HDMI_HDCP_I2C_INT
 
- HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK
 
- HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK
 
- HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT
 
- HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK
 
- HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK
 
- HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT
 
- HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT
 
- HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK
 
- HDMI_HDCP_KEY_LOAD
 
- HDMI_HDCP_KSV_LIST
 
- HDMI_HDCP_KSV_LIST_CON
 
- HDMI_HDCP_LINK0_STATUS_AN_0_READY
 
- HDMI_HDCP_LINK0_STATUS_AN_1_READY
 
- HDMI_HDCP_LINK0_STATUS_KEY_STATE
 
- HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK
 
- HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT
 
- HDMI_HDCP_LINK0_STATUS_RI_MATCHES
 
- HDMI_HDCP_LINK0_STATUS_V_MATCHES
 
- HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE
 
- HDMI_HDCP_RI_0
 
- HDMI_HDCP_RI_1
 
- HDMI_HDCP_RI_COMPARE_0
 
- HDMI_HDCP_RI_COMPARE_1
 
- HDMI_HDCP_RI_INT
 
- HDMI_HDCP_SHA1
 
- HDMI_HDCP_SHA_DATA_DONE
 
- HDMI_HDCP_SHA_RESULT
 
- HDMI_HDCP_SHA_STATUS_BLOCK_DONE
 
- HDMI_HDCP_SHA_STATUS_COMP_DONE
 
- HDMI_HDCP_WDT_INT
 
- HDMI_HDMI
 
- HDMI_HD_ALIGN_MASK
 
- HDMI_HD_ALIGN_MASK_SFT
 
- HDMI_HD_ALIGN_SFT
 
- HDMI_HD_MASK
 
- HDMI_HD_MASK_SFT
 
- HDMI_HD_SFT
 
- HDMI_HI2CHCR
 
- HDMI_HI2CRDB0
 
- HDMI_HI2CTDR0
 
- HDMI_HI2CTDR1
 
- HDMI_HICR
 
- HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD
 
- HDMI_HISR
 
- HDMI_HPD
 
- HDMI_HPD_CTRL
 
- HDMI_HPD_CTRL_ENABLE
 
- HDMI_HPD_CTRL_TIMEOUT
 
- HDMI_HPD_CTRL_TIMEOUT__MASK
 
- HDMI_HPD_CTRL_TIMEOUT__SHIFT
 
- HDMI_HPD_INT_CTRL_INT_ACK
 
- HDMI_HPD_INT_CTRL_INT_CONNECT
 
- HDMI_HPD_INT_CTRL_INT_EN
 
- HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK
 
- HDMI_HPD_INT_CTRL_RX_INT_ACK
 
- HDMI_HPD_INT_CTRL_RX_INT_EN
 
- HDMI_HPD_INT_STATUS_CABLE_DETECTED
 
- HDMI_HPD_INT_STATUS_INT
 
- HDMI_HPD_MARK
 
- HDMI_HPD_ST
 
- HDMI_HPD_STATUS
 
- HDMI_HPD_TH_X
 
- HDMI_HPG_IN_STATUS_HIGH
 
- HDMI_HPG_MENS_STA
 
- HDMI_HSR
 
- HDMI_HSYNC_ACTIVE_HIGH
 
- HDMI_HSYNC_POL
 
- HDMI_HTPLG
 
- HDMI_HTPLG_INT_32K_CLR
 
- HDMI_HTPLG_INT_32K_EN
 
- HDMI_HTPLG_INT_32K_STATUS
 
- HDMI_HTPLG_INT_32K_STA_MASK
 
- HDMI_HTPLG_INT_CLR
 
- HDMI_HTPLG_INT_EN
 
- HDMI_HTPLG_INT_STA
 
- HDMI_H_BLANK_0
 
- HDMI_H_BLANK_1
 
- HDMI_H_LINE_0
 
- HDMI_H_LINE_1
 
- HDMI_H_SYNC_END_0
 
- HDMI_H_SYNC_END_1
 
- HDMI_H_SYNC_START_0
 
- HDMI_H_SYNC_START_1
 
- HDMI_I2CM_ADDRESS
 
- HDMI_I2CM_CTLINT
 
- HDMI_I2CM_CTLINT_ARB_MASK
 
- HDMI_I2CM_CTLINT_ARB_POL
 
- HDMI_I2CM_CTLINT_NAC_MASK
 
- HDMI_I2CM_CTLINT_NAC_POL
 
- HDMI_I2CM_DATAI
 
- HDMI_I2CM_DATAO
 
- HDMI_I2CM_DIV
 
- HDMI_I2CM_FS_SCL_HCNT_0_ADDR
 
- HDMI_I2CM_FS_SCL_HCNT_1_ADDR
 
- HDMI_I2CM_FS_SCL_LCNT_0_ADDR
 
- HDMI_I2CM_FS_SCL_LCNT_1_ADDR
 
- HDMI_I2CM_INT
 
- HDMI_I2CM_INT_DONE_MASK
 
- HDMI_I2CM_INT_DONE_POL
 
- HDMI_I2CM_OPERATION
 
- HDMI_I2CM_OPERATION_READ
 
- HDMI_I2CM_OPERATION_READ_EXT
 
- HDMI_I2CM_OPERATION_WRITE
 
- HDMI_I2CM_SEGADDR
 
- HDMI_I2CM_SEGPTR
 
- HDMI_I2CM_SLAVE
 
- HDMI_I2CM_SOFTRSTZ
 
- HDMI_I2CM_SS_SCL_HCNT_0_ADDR
 
- HDMI_I2CM_SS_SCL_HCNT_1_ADDR
 
- HDMI_I2CM_SS_SCL_LCNT_0_ADDR
 
- HDMI_I2CM_SS_SCL_LCNT_1_ADDR
 
- HDMI_I2C_TRANSACTION_REG_CNT
 
- HDMI_I2C_TRANSACTION_REG_CNT__MASK
 
- HDMI_I2C_TRANSACTION_REG_CNT__SHIFT
 
- HDMI_I2C_TRANSACTION_REG_RW
 
- HDMI_I2C_TRANSACTION_REG_RW__MASK
 
- HDMI_I2C_TRANSACTION_REG_RW__SHIFT
 
- HDMI_I2C_TRANSACTION_REG_START
 
- HDMI_I2C_TRANSACTION_REG_STOP
 
- HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK
 
- HDMI_I2S
 
- HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
 
- HDMI_I2S_2AUD_CH_WITH_PREEMPH
 
- HDMI_I2S_AUDIO_CTRL
 
- HDMI_I2S_AUD_DSD
 
- HDMI_I2S_AUD_I2S
 
- HDMI_I2S_AUD_SPDIF
 
- HDMI_I2S_BASE
 
- HDMI_I2S_BASIC_FORMAT
 
- HDMI_I2S_BIT_CH_32FS
 
- HDMI_I2S_BIT_CH_48FS
 
- HDMI_I2S_BIT_CH_RESERVED
 
- HDMI_I2S_CD_PLAYER
 
- HDMI_I2S_CH0_EN
 
- HDMI_I2S_CH0_L_EN
 
- HDMI_I2S_CH0_R_EN
 
- HDMI_I2S_CH1_EN
 
- HDMI_I2S_CH1_L_EN
 
- HDMI_I2S_CH1_R_EN
 
- HDMI_I2S_CH2_EN
 
- HDMI_I2S_CH2_L_EN
 
- HDMI_I2S_CH2_R_EN
 
- HDMI_I2S_CH3_EN
 
- HDMI_I2S_CH3_L_EN
 
- HDMI_I2S_CH3_R_EN
 
- HDMI_I2S_CHANNEL_NUM_MASK
 
- HDMI_I2S_CH_ALL_EN
 
- HDMI_I2S_CH_ST
 
- HDMI_I2S_CH_STATUS_MODE_0
 
- HDMI_I2S_CH_STATUS_RELOAD
 
- HDMI_I2S_CH_ST_0_CLR
 
- HDMI_I2S_CH_ST_CON
 
- HDMI_I2S_CH_ST_CON_CLR
 
- HDMI_I2S_CH_ST_MAXNUM
 
- HDMI_I2S_CH_ST_SH_0
 
- HDMI_I2S_CH_ST_SH_1
 
- HDMI_I2S_CH_ST_SH_2
 
- HDMI_I2S_CH_ST_SH_3
 
- HDMI_I2S_CH_ST_SH_4
 
- HDMI_I2S_CLK_ACCUR_LEVEL_1
 
- HDMI_I2S_CLK_ACCUR_LEVEL_2
 
- HDMI_I2S_CLK_ACCUR_LEVEL_3
 
- HDMI_I2S_CLK_CON
 
- HDMI_I2S_CLK_DIS
 
- HDMI_I2S_CLK_EN
 
- HDMI_I2S_CONSUMER_FORMAT
 
- HDMI_I2S_CON_1
 
- HDMI_I2S_CON_2
 
- HDMI_I2S_CON_2_CLR
 
- HDMI_I2S_COPYRIGHT
 
- HDMI_I2S_CUV_I2S_ENABLE
 
- HDMI_I2S_CUV_L_DATA_MASK
 
- HDMI_I2S_CUV_L_EN
 
- HDMI_I2S_CUV_RL_EN
 
- HDMI_I2S_CUV_R_DATA_MASK
 
- HDMI_I2S_CUV_R_EN
 
- HDMI_I2S_CUV_SPDIF_ENABLE
 
- HDMI_I2S_DAT_PLAYER
 
- HDMI_I2S_DCC_PLAYER
 
- HDMI_I2S_DEFAULT_EMPHASIS
 
- HDMI_I2S_DSD_CLK_FA_EDGE
 
- HDMI_I2S_DSD_CLK_RI_EDGE
 
- HDMI_I2S_DSD_CON
 
- HDMI_I2S_DSD_DISABLE
 
- HDMI_I2S_DSD_ENABLE
 
- HDMI_I2S_IN_DISABLE
 
- HDMI_I2S_IN_ENABLE
 
- HDMI_I2S_LINEAR_PCM
 
- HDMI_I2S_LSB_FIRST_MODE
 
- HDMI_I2S_L_CH_HIGH_POL
 
- HDMI_I2S_L_CH_LOW_POL
 
- HDMI_I2S_L_JUST_FORMAT
 
- HDMI_I2S_MINI_DISC_PLAYER
 
- HDMI_I2S_MODE_I2S_16BIT
 
- HDMI_I2S_MODE_I2S_24BIT
 
- HDMI_I2S_MODE_LJT_16BIT
 
- HDMI_I2S_MODE_LJT_24BIT
 
- HDMI_I2S_MODE_RJT_16BIT
 
- HDMI_I2S_MODE_RJT_24BIT
 
- HDMI_I2S_MSB_FIRST_MODE
 
- HDMI_I2S_MUX_CH
 
- HDMI_I2S_MUX_CH_CLR
 
- HDMI_I2S_MUX_CON
 
- HDMI_I2S_MUX_CON_CLR
 
- HDMI_I2S_MUX_CUV
 
- HDMI_I2S_MUX_DISABLE
 
- HDMI_I2S_MUX_ENABLE
 
- HDMI_I2S_NOISE_FILTER_2_STAGE
 
- HDMI_I2S_NOISE_FILTER_3_STAGE
 
- HDMI_I2S_NOISE_FILTER_4_STAGE
 
- HDMI_I2S_NOISE_FILTER_5_STAGE
 
- HDMI_I2S_NOISE_FILTER_ZERO
 
- HDMI_I2S_NO_COPYRIGHT
 
- HDMI_I2S_NO_LINEAR_PCM
 
- HDMI_I2S_ORG_SMP_FREQ_176_4
 
- HDMI_I2S_ORG_SMP_FREQ_22_05
 
- HDMI_I2S_ORG_SMP_FREQ_44_1
 
- HDMI_I2S_ORG_SMP_FREQ_88_2
 
- HDMI_I2S_PIN_SEL_0
 
- HDMI_I2S_PIN_SEL_1
 
- HDMI_I2S_PIN_SEL_2
 
- HDMI_I2S_PIN_SEL_3
 
- HDMI_I2S_PROF_FORMAT
 
- HDMI_I2S_R_JUST_FORMAT
 
- HDMI_I2S_SCLK_FALLING_EDGE
 
- HDMI_I2S_SCLK_RISING_EDGE
 
- HDMI_I2S_SDATA_16BIT
 
- HDMI_I2S_SDATA_20BIT
 
- HDMI_I2S_SDATA_24BIT
 
- HDMI_I2S_SEL_DSD
 
- HDMI_I2S_SEL_LRCK
 
- HDMI_I2S_SEL_SCLK
 
- HDMI_I2S_SEL_SDATA0
 
- HDMI_I2S_SEL_SDATA1
 
- HDMI_I2S_SEL_SDATA2
 
- HDMI_I2S_SEL_SDATA3
 
- HDMI_I2S_SET_BIT_CH
 
- HDMI_I2S_SET_CHANNEL_NUM
 
- HDMI_I2S_SET_SDATA_BIT
 
- HDMI_I2S_SET_SMP_FREQ
 
- HDMI_I2S_SET_SOURCE_NUM
 
- HDMI_I2S_SMP_FREQ_32
 
- HDMI_I2S_SMP_FREQ_44_1
 
- HDMI_I2S_SMP_FREQ_48
 
- HDMI_I2S_SMP_FREQ_96
 
- HDMI_I2S_SOURCE_NUM_MASK
 
- HDMI_I2S_SWAP
 
- HDMI_I2S_WORD_LEN_MAX20_16BITS
 
- HDMI_I2S_WORD_LEN_MAX20_17BITS
 
- HDMI_I2S_WORD_LEN_MAX20_18BITS
 
- HDMI_I2S_WORD_LEN_MAX20_19BITS
 
- HDMI_I2S_WORD_LEN_MAX20_20BITS
 
- HDMI_I2S_WORD_LEN_MAX24_20BITS
 
- HDMI_I2S_WORD_LEN_MAX24_21BITS
 
- HDMI_I2S_WORD_LEN_MAX24_22BITS
 
- HDMI_I2S_WORD_LEN_MAX24_23BITS
 
- HDMI_I2S_WORD_LEN_MAX24_24BITS
 
- HDMI_I2S_WORD_LEN_MAX_20BITS
 
- HDMI_I2S_WORD_LEN_MAX_24BITS
 
- HDMI_I2S_WORD_LEN_NOT_DEFINE
 
- HDMI_ICRH
 
- HDMI_IEEE_OUI
 
- HDMI_IFRAME_CFG_DI_N
 
- HDMI_IFRAME_DISABLED
 
- HDMI_IFRAME_FIELD
 
- HDMI_IFRAME_FRAME
 
- HDMI_IFRAME_MASK
 
- HDMI_IFRAME_SINGLE_SHOT
 
- HDMI_IFRAME_SLOT_AUDIO
 
- HDMI_IFRAME_SLOT_AVI
 
- HDMI_IFRAME_SLOT_VENDOR
 
- HDMI_IH_AHBDMAAUD_STAT0
 
- HDMI_IH_AHBDMAAUD_STAT0_ALL
 
- HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY
 
- HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL
 
- HDMI_IH_AHBDMAAUD_STAT0_DONE
 
- HDMI_IH_AHBDMAAUD_STAT0_ERROR
 
- HDMI_IH_AHBDMAAUD_STAT0_LOST
 
- HDMI_IH_AHBDMAAUD_STAT0_RETRY
 
- HDMI_IH_AS_STAT0
 
- HDMI_IH_CEC_STAT0
 
- HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW
 
- HDMI_IH_FC_INT2_OVERFLOW_MASK
 
- HDMI_IH_FC_STAT0
 
- HDMI_IH_FC_STAT1
 
- HDMI_IH_FC_STAT2
 
- HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW
 
- HDMI_IH_FC_STAT2_OVERFLOW_MASK
 
- HDMI_IH_I2CMPHY_STAT0
 
- HDMI_IH_I2CM_STAT0
 
- HDMI_IH_I2CM_STAT0_DONE
 
- HDMI_IH_I2CM_STAT0_ERROR
 
- HDMI_IH_MUTE
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST
 
- HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY
 
- HDMI_IH_MUTE_AS_STAT0
 
- HDMI_IH_MUTE_CEC_STAT0
 
- HDMI_IH_MUTE_FC_STAT0
 
- HDMI_IH_MUTE_FC_STAT1
 
- HDMI_IH_MUTE_FC_STAT2
 
- HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW
 
- HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW
 
- HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK
 
- HDMI_IH_MUTE_I2CMPHY_STAT0
 
- HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE
 
- HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR
 
- HDMI_IH_MUTE_I2CM_STAT0
 
- HDMI_IH_MUTE_MUTE_ALL_INTERRUPT
 
- HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT
 
- HDMI_IH_MUTE_PHY_STAT0
 
- HDMI_IH_MUTE_VP_STAT0
 
- HDMI_IH_PHY_STAT0
 
- HDMI_IH_PHY_STAT0_HPD
 
- HDMI_IH_PHY_STAT0_RX_SENSE
 
- HDMI_IH_PHY_STAT0_RX_SENSE0
 
- HDMI_IH_PHY_STAT0_RX_SENSE1
 
- HDMI_IH_PHY_STAT0_RX_SENSE2
 
- HDMI_IH_PHY_STAT0_RX_SENSE3
 
- HDMI_IH_PHY_STAT0_TX_PHY_LOCK
 
- HDMI_IH_VP_STAT0
 
- HDMI_INFOFRAME_AAI
 
- HDMI_INFOFRAME_AVI
 
- HDMI_INFOFRAME_CONTROL0
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT
 
- HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT
 
- HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK
 
- HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT
 
- HDMI_INFOFRAME_CONTROL1
 
- HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK
 
- HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
 
- HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK
 
- HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT
 
- HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND
 
- HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE
 
- HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE
 
- HDMI_INFOFRAME_CTRL0_AVI_CONT
 
- HDMI_INFOFRAME_CTRL0_AVI_SEND
 
- HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE
 
- HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK
 
- HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE
 
- HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK
 
- HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE
 
- HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK
 
- HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE
 
- HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK
 
- HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT
 
- HDMI_INFOFRAME_HEADER_LEN
 
- HDMI_INFOFRAME_HEADER_SIZE
 
- HDMI_INFOFRAME_HEADER_TYPE
 
- HDMI_INFOFRAME_HEADER_VERSION
 
- HDMI_INFOFRAME_SIZE
 
- HDMI_INFOFRAME_TYPE_AUDIO
 
- HDMI_INFOFRAME_TYPE_AVI
 
- HDMI_INFOFRAME_TYPE_DRM
 
- HDMI_INFOFRAME_TYPE_SPD
 
- HDMI_INFOFRAME_TYPE_VENDOR
 
- HDMI_INFOFRAME_VSI
 
- HDMI_INFO_FRAME_WORD1
 
- HDMI_INPUT_10BIT
 
- HDMI_INPUT_12BIT
 
- HDMI_INPUT_8BIT
 
- HDMI_INT0
 
- HDMI_INT1
 
- HDMI_INTC_CON
 
- HDMI_INTC_CON_1
 
- HDMI_INTC_EN_GLOBAL
 
- HDMI_INTC_EN_HPD_PLUG
 
- HDMI_INTC_EN_HPD_UNPLUG
 
- HDMI_INTC_FLAG
 
- HDMI_INTC_FLAG_1
 
- HDMI_INTC_FLAG_HPD_PLUG
 
- HDMI_INTC_FLAG_HPD_UNPLUG
 
- HDMI_INTERNAL_CLK_DIVIDER
 
- HDMI_INTERRUPT_MASK1
 
- HDMI_INTERRUPT_MASK2
 
- HDMI_INTERRUPT_STATUS1
 
- HDMI_INTERRUPT_STATUS2
 
- HDMI_INTR_AUDIO_FIFO_FULL
 
- HDMI_INTR_EDID_ERR
 
- HDMI_INTR_EDID_MASK
 
- HDMI_INTR_EDID_READY
 
- HDMI_INTR_HOTPLUG
 
- HDMI_INTR_HPD
 
- HDMI_INTR_I2C_DONE
 
- HDMI_INTR_I2C_ERROR
 
- HDMI_INTR_I2C_FULL
 
- HDMI_INTR_MASK1
 
- HDMI_INTR_MASK2
 
- HDMI_INTR_MASK3
 
- HDMI_INTR_MASK4
 
- HDMI_INTR_MSENS
 
- HDMI_INTR_STATUS1
 
- HDMI_INTR_STATUS2
 
- HDMI_INTR_STATUS3
 
- HDMI_INTR_STATUS4
 
- HDMI_INTR_VSYNC
 
- HDMI_INT_AUDIO_FIFO_XRUN
 
- HDMI_INT_CLR
 
- HDMI_INT_DLL_LCK
 
- HDMI_INT_EN
 
- HDMI_INT_GENCTRL_PKT
 
- HDMI_INT_GLOBAL
 
- HDMI_INT_HOT_PLUG
 
- HDMI_INT_NEW_FRAME
 
- HDMI_INT_PIX_CAP
 
- HDMI_INT_PRO_MODE
 
- HDMI_INT_SINK_TERM_PRESENT
 
- HDMI_INT_STA
 
- HDMI_INT_SW_RST
 
- HDMI_IRQ_AUDIO_FIFO_OVERFLOW
 
- HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ
 
- HDMI_IRQ_AUDIO_FIFO_UNDERFLOW
 
- HDMI_IRQ_CORE
 
- HDMI_IRQ_LINK_CONNECT
 
- HDMI_IRQ_LINK_DISCONNECT
 
- HDMI_IRQ_OCP_TIMEOUT
 
- HDMI_IRQ_PHY_LINE5V_ASSERT
 
- HDMI_IRQ_PLL_LOCK
 
- HDMI_IRQ_PLL_RECAL
 
- HDMI_IRQ_PLL_UNLOCK
 
- HDMI_IRQ_VIDEO_FRAME_DONE
 
- HDMI_IRQ_VIDEO_VSYNC
 
- HDMI_ISRC1_DATA
 
- HDMI_ISRC1_HEADER1
 
- HDMI_ISRC2_DATA
 
- HDMI_ISRC_CON
 
- HDMI_ISRC_CONT
 
- HDMI_ISRC_CONT_DISABLE
 
- HDMI_ISRC_CONT_ENABLE
 
- HDMI_ISRC_NOT_SEND
 
- HDMI_ISRC_PKT_SEND
 
- HDMI_ISRC_SEND
 
- HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC
 
- HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC
 
- HDMI_KEEPOUT_MODE
 
- HDMI_LEFT_J
 
- HDMI_LEVEL_SHIFT_UNKNOWN
 
- HDMI_LR_SWAP_N3
 
- HDMI_MAIN_DIV_SHIFT
 
- HDMI_MAIN_PNX_DIV_SHIFT
 
- HDMI_MAPPED_BASE
 
- HDMI_MAXIMUM_INFO_FRAME_SIZE
 
- HDMI_MAXLEN_MASK
 
- HDMI_MAXLEN_MASK_SFT
 
- HDMI_MAXLEN_SFT
 
- HDMI_MAX_DATA_RATE_165
 
- HDMI_MAX_DATA_RATE_297
 
- HDMI_MAX_DATA_RATE_PLATFORM
 
- HDMI_MAX_ELD_BYTES
 
- HDMI_MAX_NUM_GPIO
 
- HDMI_MC_CLKDIS
 
- HDMI_MC_CLKDIS_AUDCLK_DISABLE
 
- HDMI_MC_CLKDIS_CECCLK_DISABLE
 
- HDMI_MC_CLKDIS_CSCCLK_DISABLE
 
- HDMI_MC_CLKDIS_HDCPCLK_DISABLE
 
- HDMI_MC_CLKDIS_PIXELCLK_DISABLE
 
- HDMI_MC_CLKDIS_PREPCLK_DISABLE
 
- HDMI_MC_CLKDIS_TMDSCLK_DISABLE
 
- HDMI_MC_FLOWCTRL
 
- HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS
 
- HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH
 
- HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK
 
- HDMI_MC_HEACPHY_RST
 
- HDMI_MC_HEACPHY_RST_ASSERT
 
- HDMI_MC_HEACPHY_RST_DEASSERT
 
- HDMI_MC_LOCKONCLOCK
 
- HDMI_MC_OPCTRL
 
- HDMI_MC_PHYRSTZ
 
- HDMI_MC_PHYRSTZ_PHYRSTZ
 
- HDMI_MC_SFRDIV
 
- HDMI_MC_SWRSTZ
 
- HDMI_MC_SWRSTZ_I2SSWRST_REQ
 
- HDMI_MC_SWRSTZ_TMDSSWRST_REQ
 
- HDMI_METADATA_ENABLE
 
- HDMI_METADATA_NOT_SEND
 
- HDMI_METADATA_PKT_SEND
 
- HDMI_MID_FREQ_BIT_CLK_THRESHOLD
 
- HDMI_MINLEN_MASK
 
- HDMI_MINLEN_MASK_SFT
 
- HDMI_MINLEN_SFT
 
- HDMI_MODE_DELAY_0_MS
 
- HDMI_MODE_DELAY_100_MS
 
- HDMI_MODE_DELAY_25_MS
 
- HDMI_MODE_DELAY_50_MS
 
- HDMI_MODE_DVI_EN
 
- HDMI_MODE_HDMI_EN
 
- HDMI_MODE_MASK
 
- HDMI_MODE_OUTPUT
 
- HDMI_MODE_SEL
 
- HDMI_MODE_SELECT_DVI
 
- HDMI_MODE_SELECT_HDMI
 
- HDMI_MPEG_INFO_CONT
 
- HDMI_MPEG_INFO_CONT_DISABLE
 
- HDMI_MPEG_INFO_CONT_ENABLE
 
- HDMI_MPEG_INFO_LINE
 
- HDMI_MPEG_INFO_NOT_SEND
 
- HDMI_MPEG_INFO_PKT_SEND
 
- HDMI_MPEG_INFO_SEND
 
- HDMI_MPG_CHECK_SUM
 
- HDMI_MPG_CON
 
- HDMI_MPG_DATA
 
- HDMI_MSENS_IN_STATUS_HIGH
 
- HDMI_MSM_AUDIO_ARCS
 
- HDMI_M_AHB_CLK
 
- HDMI_N1
 
- HDMI_N2
 
- HDMI_NORMAL_MODE_MASK
 
- HDMI_NORMAL_MODE_MASK_SFT
 
- HDMI_NORMAL_MODE_SFT
 
- HDMI_NOT_SEND_MAX_AUDIO_PACKETS
 
- HDMI_NO_EXTRA_NULL_PACKET_FILLED
 
- HDMI_NULL_NOT_SEND
 
- HDMI_NULL_PACKETS_DURING_VSYNC
 
- HDMI_NULL_PKT_SEND
 
- HDMI_NULL_SEND
 
- HDMI_NUM_TX_CHANNEL
 
- HDMI_NUPS_BOTH
 
- HDMI_NUPS_HORIZONTAL
 
- HDMI_NUPS_UNKNOWN
 
- HDMI_NUPS_VERTICAL
 
- HDMI_NV_PDISP_AUDIO_CNTRL0
 
- HDMI_NV_PDISP_AUDIO_DEBUG0
 
- HDMI_NV_PDISP_AUDIO_DEBUG1
 
- HDMI_NV_PDISP_AUDIO_DEBUG2
 
- HDMI_NV_PDISP_AUDIO_FS
 
- HDMI_NV_PDISP_AUDIO_N
 
- HDMI_NV_PDISP_AUDIO_PULSE_WIDTH
 
- HDMI_NV_PDISP_AUDIO_THRESHOLD
 
- HDMI_NV_PDISP_CRC_CONTROL
 
- HDMI_NV_PDISP_HDCPRIF_ROM_TIMING
 
- HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH
 
- HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW
 
- HDMI_NV_PDISP_HDMI_ACR_CTRL
 
- HDMI_NV_PDISP_HDMI_AUDIO_EMU0
 
- HDMI_NV_PDISP_HDMI_AUDIO_EMU1
 
- HDMI_NV_PDISP_HDMI_AUDIO_EMU2
 
- HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0
 
- HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL
 
- HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER
 
- HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS
 
- HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH
 
- HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH
 
- HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW
 
- HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1
 
- HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2
 
- HDMI_NV_PDISP_HDMI_CTRL
 
- HDMI_NV_PDISP_HDMI_EMU0
 
- HDMI_NV_PDISP_HDMI_EMU1
 
- HDMI_NV_PDISP_HDMI_EMU1_RDATA
 
- HDMI_NV_PDISP_HDMI_GCP_CTRL
 
- HDMI_NV_PDISP_HDMI_GCP_STATUS
 
- HDMI_NV_PDISP_HDMI_GCP_SUBPACK
 
- HDMI_NV_PDISP_HDMI_GENERIC_CTRL
 
- HDMI_NV_PDISP_HDMI_GENERIC_HEADER
 
- HDMI_NV_PDISP_HDMI_GENERIC_STATUS
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH
 
- HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW
 
- HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL
 
- HDMI_NV_PDISP_HDMI_SPARE
 
- HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1
 
- HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2
 
- HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT
 
- HDMI_NV_PDISP_HDMI_VSYNC_WINDOW
 
- HDMI_NV_PDISP_INPUT_CONTROL
 
- HDMI_NV_PDISP_INT_ENABLE
 
- HDMI_NV_PDISP_INT_MASK
 
- HDMI_NV_PDISP_INT_STATUS
 
- HDMI_NV_PDISP_KEY_CTRL
 
- HDMI_NV_PDISP_KEY_DEBUG0
 
- HDMI_NV_PDISP_KEY_DEBUG1
 
- HDMI_NV_PDISP_KEY_DEBUG2
 
- HDMI_NV_PDISP_KEY_HDCP_KEY_0
 
- HDMI_NV_PDISP_KEY_HDCP_KEY_1
 
- HDMI_NV_PDISP_KEY_HDCP_KEY_2
 
- HDMI_NV_PDISP_KEY_HDCP_KEY_3
 
- HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG
 
- HDMI_NV_PDISP_KEY_SKEY_INDEX
 
- HDMI_NV_PDISP_PE_CURRENT
 
- HDMI_NV_PDISP_RG_HDCP_AKSV_LSB
 
- HDMI_NV_PDISP_RG_HDCP_AKSV_MSB
 
- HDMI_NV_PDISP_RG_HDCP_AN_LSB
 
- HDMI_NV_PDISP_RG_HDCP_AN_MSB
 
- HDMI_NV_PDISP_RG_HDCP_BKSV_LSB
 
- HDMI_NV_PDISP_RG_HDCP_BKSV_MSB
 
- HDMI_NV_PDISP_RG_HDCP_CKSV_LSB
 
- HDMI_NV_PDISP_RG_HDCP_CKSV_MSB
 
- HDMI_NV_PDISP_RG_HDCP_CMODE
 
- HDMI_NV_PDISP_RG_HDCP_CN_LSB
 
- HDMI_NV_PDISP_RG_HDCP_CN_MSB
 
- HDMI_NV_PDISP_RG_HDCP_CS_LSB
 
- HDMI_NV_PDISP_RG_HDCP_CS_MSB
 
- HDMI_NV_PDISP_RG_HDCP_CTRL
 
- HDMI_NV_PDISP_RG_HDCP_DKSV_LSB
 
- HDMI_NV_PDISP_RG_HDCP_DKSV_MSB
 
- HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB
 
- HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB
 
- HDMI_NV_PDISP_RG_HDCP_RI
 
- HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1
 
- HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2
 
- HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB
 
- HDMI_NV_PDISP_SCRATCH
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920
 
- HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT
 
- HDMI_NV_PDISP_SOR_AUDIO_CNTRL0
 
- HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0
 
- HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1
 
- HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR
 
- HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE
 
- HDMI_NV_PDISP_SOR_AUDIO_SPARE0
 
- HDMI_NV_PDISP_SOR_BLANK
 
- HDMI_NV_PDISP_SOR_CAP
 
- HDMI_NV_PDISP_SOR_CCRCA0
 
- HDMI_NV_PDISP_SOR_CCRCA1
 
- HDMI_NV_PDISP_SOR_COUNTA0
 
- HDMI_NV_PDISP_SOR_COUNTA1
 
- HDMI_NV_PDISP_SOR_CRCA
 
- HDMI_NV_PDISP_SOR_CRCB
 
- HDMI_NV_PDISP_SOR_CSTM
 
- HDMI_NV_PDISP_SOR_DEBUGA0
 
- HDMI_NV_PDISP_SOR_DEBUGA1
 
- HDMI_NV_PDISP_SOR_EDATAA0
 
- HDMI_NV_PDISP_SOR_EDATAA1
 
- HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT
 
- HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT
 
- HDMI_NV_PDISP_SOR_LVDS
 
- HDMI_NV_PDISP_SOR_MSCHECK
 
- HDMI_NV_PDISP_SOR_PAD_CTLS0
 
- HDMI_NV_PDISP_SOR_PLL0
 
- HDMI_NV_PDISP_SOR_PLL1
 
- HDMI_NV_PDISP_SOR_PLL2
 
- HDMI_NV_PDISP_SOR_PWR
 
- HDMI_NV_PDISP_SOR_REFCLK
 
- HDMI_NV_PDISP_SOR_SEQ_CTL
 
- HDMI_NV_PDISP_SOR_SEQ_INST
 
- HDMI_NV_PDISP_SOR_STATE0
 
- HDMI_NV_PDISP_SOR_STATE1
 
- HDMI_NV_PDISP_SOR_STATE2
 
- HDMI_NV_PDISP_SOR_TEST
 
- HDMI_NV_PDISP_SOR_TRIG
 
- HDMI_NV_PDISP_SOR_VCRCA0
 
- HDMI_NV_PDISP_SOR_VCRCA1
 
- HDMI_OFFSET0
 
- HDMI_OFFSET1
 
- HDMI_ON
 
- HDMI_OSC_CEC
 
- HDMI_OSC_CLK
 
- HDMI_OUTPUTDITHER_10BIT
 
- HDMI_OUTPUTDITHER_12BIT
 
- HDMI_OUTPUTDITHER_8BIT
 
- HDMI_OUTPUTTRUNCATION_10BIT
 
- HDMI_OUTPUTTRUNCATION_12BIT
 
- HDMI_OUTPUTTRUNCATION_8BIT
 
- HDMI_OUT_FIFO_CLK_INV
 
- HDMI_OUT_FIFO_EN
 
- HDMI_O_0_MASK
 
- HDMI_O_0_MASK_SFT
 
- HDMI_O_0_SFT
 
- HDMI_O_1_MASK
 
- HDMI_O_1_MASK_SFT
 
- HDMI_O_1_SFT
 
- HDMI_O_2_MASK
 
- HDMI_O_2_MASK_SFT
 
- HDMI_O_2_SFT
 
- HDMI_O_3_MASK
 
- HDMI_O_3_MASK_SFT
 
- HDMI_O_3_SFT
 
- HDMI_O_4_MASK
 
- HDMI_O_4_MASK_SFT
 
- HDMI_O_4_SFT
 
- HDMI_O_5_MASK
 
- HDMI_O_5_MASK_SFT
 
- HDMI_O_5_SFT
 
- HDMI_O_6_MASK
 
- HDMI_O_6_MASK_SFT
 
- HDMI_O_6_SFT
 
- HDMI_O_7_MASK
 
- HDMI_O_7_MASK_SFT
 
- HDMI_O_7_SFT
 
- HDMI_PACKETDISABLE
 
- HDMI_PACKETENABLE
 
- HDMI_PACKETMODE24BITPERPIXEL
 
- HDMI_PACKETMODE30BITPERPIXEL
 
- HDMI_PACKETMODE36BITPERPIXEL
 
- HDMI_PACKETMODE48BITPERPIXEL
 
- HDMI_PACKETMODERESERVEDVALUE
 
- HDMI_PACKETREPEATOFF
 
- HDMI_PACKETREPEATON
 
- HDMI_PACKET_GEN_VERSION
 
- HDMI_PACKET_GEN_VERSION_NEW
 
- HDMI_PACKET_GEN_VERSION_OLD
 
- HDMI_PACKET_LINE_REFERENCE
 
- HDMI_PACKET_SEND_AUTO
 
- HDMI_PACKET_SEND_MANUAL
 
- HDMI_PACKET_TYPE_ACP
 
- HDMI_PACKET_TYPE_AUDIO_CLOCK_REGEN
 
- HDMI_PACKET_TYPE_AUDIO_SAMPLE
 
- HDMI_PACKET_TYPE_DST_AUDIO
 
- HDMI_PACKET_TYPE_GAMUT_METADATA
 
- HDMI_PACKET_TYPE_GENERAL_CONTROL
 
- HDMI_PACKET_TYPE_HBR_AUDIO_STREAM
 
- HDMI_PACKET_TYPE_ISRC1
 
- HDMI_PACKET_TYPE_ISRC2
 
- HDMI_PACKET_TYPE_NULL
 
- HDMI_PACKET_TYPE_ONE_BIT_AUDIO_SAMPLE
 
- HDMI_PACKING_PHASE_OVERRIDE
 
- HDMI_PACKING_PHASE_SET_BY_HW
 
- HDMI_PACKING_PHASE_SET_BY_SW
 
- HDMI_PACK_10b_RGB_YUV444
 
- HDMI_PACK_20b_YUV422
 
- HDMI_PACK_24b_RGB_YUV444_YUV422
 
- HDMI_PACK_ALREADYPACKED
 
- HDMI_PBUF_SIZE_MASK
 
- HDMI_PBUF_SIZE_MASK_SFT
 
- HDMI_PBUF_SIZE_SFT
 
- HDMI_PCLK_FREE_RUN
 
- HDMI_PCLK_MAX_FREQ
 
- HDMI_PCLK_MIN_FREQ
 
- HDMI_PHYPWRCMD_LDOON
 
- HDMI_PHYPWRCMD_OFF
 
- HDMI_PHYPWRCMD_TXON
 
- HDMI_PHY_CHG_PWR
 
- HDMI_PHY_CMU
 
- HDMI_PHY_CONF0
 
- HDMI_PHY_CONF0_ENTMDS_MASK
 
- HDMI_PHY_CONF0_ENTMDS_OFFSET
 
- HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK
 
- HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET
 
- HDMI_PHY_CONF0_GEN2_PDDQ_MASK
 
- HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET
 
- HDMI_PHY_CONF0_GEN2_TXPWRON_MASK
 
- HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET
 
- HDMI_PHY_CONF0_PDZ_MASK
 
- HDMI_PHY_CONF0_PDZ_OFFSET
 
- HDMI_PHY_CONF0_SELDATAENPOL_MASK
 
- HDMI_PHY_CONF0_SELDATAENPOL_OFFSET
 
- HDMI_PHY_CONF0_SELDIPIF_MASK
 
- HDMI_PHY_CONF0_SELDIPIF_OFFSET
 
- HDMI_PHY_CONF0_SVSRET_MASK
 
- HDMI_PHY_CONF0_SVSRET_OFFSET
 
- HDMI_PHY_CON_0
 
- HDMI_PHY_CTRL_SW_RESET
 
- HDMI_PHY_CTRL_SW_RESET_LOW
 
- HDMI_PHY_CTRL_SW_RESET_PLL
 
- HDMI_PHY_CTRL_SW_RESET_PLL_LOW
 
- HDMI_PHY_DISABLE_MODE_SET
 
- HDMI_PHY_DRIVER
 
- HDMI_PHY_ENABLE_MODE_SET
 
- HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH
 
- HDMI_PHY_FEEDBACK_DIV_RATIO_LOW
 
- HDMI_PHY_HPD
 
- HDMI_PHY_I2CM_ADDRESS_ADDR
 
- HDMI_PHY_I2CM_CTLINT_ADDR
 
- HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK
 
- HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL
 
- HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK
 
- HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL
 
- HDMI_PHY_I2CM_DATAI_0_ADDR
 
- HDMI_PHY_I2CM_DATAI_1_ADDR
 
- HDMI_PHY_I2CM_DATAO_0_ADDR
 
- HDMI_PHY_I2CM_DATAO_1_ADDR
 
- HDMI_PHY_I2CM_DIV_ADDR
 
- HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR
 
- HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR
 
- HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR
 
- HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR
 
- HDMI_PHY_I2CM_INT_ADDR
 
- HDMI_PHY_I2CM_INT_ADDR_DONE_MASK
 
- HDMI_PHY_I2CM_INT_ADDR_DONE_POL
 
- HDMI_PHY_I2CM_OPERATION_ADDR
 
- HDMI_PHY_I2CM_OPERATION_ADDR_READ
 
- HDMI_PHY_I2CM_OPERATION_ADDR_WRITE
 
- HDMI_PHY_I2CM_SLAVE_ADDR
 
- HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY
 
- HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2
 
- HDMI_PHY_I2CM_SOFTRSTZ_ADDR
 
- HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR
 
- HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR
 
- HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR
 
- HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR
 
- HDMI_PHY_INT0
 
- HDMI_PHY_MASK0
 
- HDMI_PHY_OPTION
 
- HDMI_PHY_POL0
 
- HDMI_PHY_POWER_DOWN
 
- HDMI_PHY_POWER_OFF
 
- HDMI_PHY_POWER_OFF_EN
 
- HDMI_PHY_POWER_ON
 
- HDMI_PHY_PRE_DIV_RATIO
 
- HDMI_PHY_PRE_EMPHASIS
 
- HDMI_PHY_RSTOUT
 
- HDMI_PHY_RX_SENSE
 
- HDMI_PHY_RX_SENSE0
 
- HDMI_PHY_RX_SENSE1
 
- HDMI_PHY_RX_SENSE2
 
- HDMI_PHY_RX_SENSE3
 
- HDMI_PHY_STAT0
 
- HDMI_PHY_STATUS
 
- HDMI_PHY_STATUS_0
 
- HDMI_PHY_STATUS_CMU
 
- HDMI_PHY_STATUS_PLL
 
- HDMI_PHY_STATUS_READY
 
- HDMI_PHY_SW_RSTOUT
 
- HDMI_PHY_SYNC
 
- HDMI_PHY_SYS_CTL
 
- HDMI_PHY_TST0
 
- HDMI_PHY_TST0_TSTCLK_MASK
 
- HDMI_PHY_TST0_TSTCLK_OFFSET
 
- HDMI_PHY_TST0_TSTCLR_MASK
 
- HDMI_PHY_TST0_TSTCLR_OFFSET
 
- HDMI_PHY_TST0_TSTEN_MASK
 
- HDMI_PHY_TST0_TSTEN_OFFSET
 
- HDMI_PHY_TST1
 
- HDMI_PHY_TST2
 
- HDMI_PHY_TX_PHY_LOCK
 
- HDMI_PHY_VPLL
 
- HDMI_PICTURE_ASPECT_16_9
 
- HDMI_PICTURE_ASPECT_256_135
 
- HDMI_PICTURE_ASPECT_4_3
 
- HDMI_PICTURE_ASPECT_64_27
 
- HDMI_PICTURE_ASPECT_NONE
 
- HDMI_PICTURE_ASPECT_RESERVED
 
- HDMI_PKT_LINE_REF_OTGSOF
 
- HDMI_PKT_LINE_REF_VSYNC
 
- HDMI_PLLPWRCMD_ALLOFF
 
- HDMI_PLLPWRCMD_BOTHON_ALLCLKS
 
- HDMI_PLLPWRCMD_BOTHON_NOPHYCLK
 
- HDMI_PLLPWRCMD_PLLONLY
 
- HDMI_PLL_CMP_CNT
 
- HDMI_PLL_LOCK
 
- HDMI_PLL_LOCK_G12A
 
- HDMI_PLL_POLL_MAX_READS
 
- HDMI_PLL_POLL_TIMEOUT_US
 
- HDMI_PLL_RESET
 
- HDMI_PLL_RESET_G12A
 
- HDMI_PORD
 
- HDMI_PORD_INT_32K_CLR
 
- HDMI_PORD_INT_32K_EN
 
- HDMI_PORD_INT_32K_STATUS
 
- HDMI_PORD_INT_32K_STA_MASK
 
- HDMI_PORD_INT_CLR
 
- HDMI_PORD_INT_EN
 
- HDMI_PORD_INT_STA
 
- HDMI_PRODUCT_ID0
 
- HDMI_PRODUCT_ID0_HDMI_TX
 
- HDMI_PRODUCT_ID1
 
- HDMI_PRODUCT_ID1_HDCP
 
- HDMI_PRODUCT_ID1_HDMI_RX
 
- HDMI_PRODUCT_ID1_HDMI_TX
 
- HDMI_QUANTIZATION_RANGE_DEFAULT
 
- HDMI_QUANTIZATION_RANGE_FULL
 
- HDMI_QUANTIZATION_RANGE_LIMITED
 
- HDMI_QUANTIZATION_RANGE_RESERVED
 
- HDMI_RATES
 
- HDMI_READ
 
- HDMI_REKEY_DEFAULT
 
- HDMI_RESET
 
- HDMI_REVISION_ID
 
- HDMI_RGB_ROUND_EN
 
- HDMI_RIGHT_J
 
- HDMI_RST
 
- HDMI_RX
 
- HDMI_RX_EQ_DATA0_REG
 
- HDMI_RX_EQ_DATA1_REG
 
- HDMI_RX_EQ_DATA2_REG
 
- HDMI_RX_EQ_DATA3_REG
 
- HDMI_RX_EQ_DATA4_REG
 
- HDMI_RX_PLL_CALREFSEL_REG
 
- HDMI_RX_PLL_VCOCAL_REG
 
- HDMI_RX_TMDS0_CCTRL1_REG
 
- HDMI_RX_TMDS_CH_EN_REG
 
- HDMI_RX_TMDS_CLK_EN_REG
 
- HDMI_RX_TMDS_MODE_CTRL_REG
 
- HDMI_RX_TMDS_ZONE_CTRL_REG
 
- HDMI_SAMPLE_FLAT_ALL
 
- HDMI_SAMPLE_FLAT_MASK
 
- HDMI_SAMPLE_FLAT_NO
 
- HDMI_SAMPLE_FLAT_SP0
 
- HDMI_SAMPLE_FLAT_SP1
 
- HDMI_SAMPLE_FLAT_SP2
 
- HDMI_SAMPLE_FLAT_SP3
 
- HDMI_SAMPLE_RATE_176_4KHZ
 
- HDMI_SAMPLE_RATE_192KHZ
 
- HDMI_SAMPLE_RATE_32KHZ
 
- HDMI_SAMPLE_RATE_44_1KHZ
 
- HDMI_SAMPLE_RATE_48KHZ
 
- HDMI_SAMPLE_RATE_88_2KHZ
 
- HDMI_SAMPLE_RATE_96KHZ
 
- HDMI_SCAN_MODE_NONE
 
- HDMI_SCAN_MODE_OVERSCAN
 
- HDMI_SCAN_MODE_RESERVED
 
- HDMI_SCAN_MODE_UNDERSCAN
 
- HDMI_SCDC_ADDRESS
 
- HDMI_SCDC_CONFIG_0
 
- HDMI_SCDC_ERR_DETECT
 
- HDMI_SCDC_SCRAMBLER_STATUS
 
- HDMI_SCDC_SINK_VERSION
 
- HDMI_SCDC_SOURCE_VERSION
 
- HDMI_SCDC_STATUS_FLAGS
 
- HDMI_SCDC_TEST_CONFIG
 
- HDMI_SCDC_TMDS_CONFIG
 
- HDMI_SCDC_UPDATE_0
 
- HDMI_SCDC_WRITE_UPDATE_0_ARRAY
 
- HDMI_SCL
 
- HDMI_SCL_RATE
 
- HDMI_SDA
 
- HDMI_SEND_MAX_AUDIO_PACKETS
 
- HDMI_SPDIF
 
- HDMI_SPDIF_FIFO_STATUS
 
- HDMI_SPDIF_FS_CTS_INT3
 
- HDMI_SPD_CON
 
- HDMI_SPD_DATA
 
- HDMI_SPD_HEADER0
 
- HDMI_SPD_HEADER1
 
- HDMI_SPD_HEADER2
 
- HDMI_SPD_INFOFRAME_SIZE
 
- HDMI_SPD_SDI_BD
 
- HDMI_SPD_SDI_DSC
 
- HDMI_SPD_SDI_DSTB
 
- HDMI_SPD_SDI_DVC
 
- HDMI_SPD_SDI_DVDP
 
- HDMI_SPD_SDI_DVHS
 
- HDMI_SPD_SDI_GAME
 
- HDMI_SPD_SDI_HDDVD
 
- HDMI_SPD_SDI_HDDVR
 
- HDMI_SPD_SDI_PC
 
- HDMI_SPD_SDI_PMP
 
- HDMI_SPD_SDI_SACD
 
- HDMI_SPD_SDI_UNKNOWN
 
- HDMI_SPD_SDI_VCD
 
- HDMI_SRC_DISPLAYA
 
- HDMI_SRC_DISPLAYB
 
- HDMI_SRZ_CALCODE_EXT
 
- HDMI_SRZ_CFG
 
- HDMI_SRZ_CFG_DISABLE_BYPASS_SINK_CURRENT
 
- HDMI_SRZ_CFG_EN
 
- HDMI_SRZ_CFG_EN_BIASRES_DETECTION
 
- HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION
 
- HDMI_SRZ_CFG_EN_SRC_TERMINATION
 
- HDMI_SRZ_CFG_EXTERNAL_DATA
 
- HDMI_SRZ_CFG_INTERNAL_MASK
 
- HDMI_SRZ_CFG_RBIAS_EXT
 
- HDMI_SRZ_ICNTL
 
- HDMI_SRZ_PLL_CFG
 
- HDMI_STA
 
- HDMI_STATIC_METADATA_TYPE1
 
- HDMI_STATUS
 
- HDMI_STATUS_EN
 
- HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK
 
- HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT
 
- HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK
 
- HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT
 
- HDMI_STATUS__HDMI_ERROR_INT_MASK
 
- HDMI_STATUS__HDMI_ERROR_INT__SHIFT
 
- HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK
 
- HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT
 
- HDMI_STA_DLL_LCK
 
- HDMI_STA_HOT_PLUG
 
- HDMI_STA_SW_RST
 
- HDMI_SW_DI_1_HEAD_WORD
 
- HDMI_SW_DI_1_PKT_WORD0
 
- HDMI_SW_DI_1_PKT_WORD1
 
- HDMI_SW_DI_1_PKT_WORD2
 
- HDMI_SW_DI_1_PKT_WORD3
 
- HDMI_SW_DI_1_PKT_WORD4
 
- HDMI_SW_DI_1_PKT_WORD5
 
- HDMI_SW_DI_1_PKT_WORD6
 
- HDMI_SW_DI_2_HEAD_WORD
 
- HDMI_SW_DI_2_PKT_WORD0
 
- HDMI_SW_DI_2_PKT_WORD1
 
- HDMI_SW_DI_2_PKT_WORD2
 
- HDMI_SW_DI_2_PKT_WORD3
 
- HDMI_SW_DI_2_PKT_WORD4
 
- HDMI_SW_DI_2_PKT_WORD5
 
- HDMI_SW_DI_2_PKT_WORD6
 
- HDMI_SW_DI_3_HEAD_WORD
 
- HDMI_SW_DI_3_PKT_WORD0
 
- HDMI_SW_DI_3_PKT_WORD1
 
- HDMI_SW_DI_3_PKT_WORD2
 
- HDMI_SW_DI_3_PKT_WORD3
 
- HDMI_SW_DI_3_PKT_WORD4
 
- HDMI_SW_DI_3_PKT_WORD5
 
- HDMI_SW_DI_3_PKT_WORD6
 
- HDMI_SW_DI_CFG
 
- HDMI_SW_DI_MAX_WORD
 
- HDMI_SW_DI_N_HEAD_WORD
 
- HDMI_SW_DI_N_PKT_WORD0
 
- HDMI_SW_DI_N_PKT_WORD1
 
- HDMI_SW_DI_N_PKT_WORD2
 
- HDMI_SW_DI_N_PKT_WORD3
 
- HDMI_SW_DI_N_PKT_WORD4
 
- HDMI_SW_DI_N_PKT_WORD5
 
- HDMI_SW_DI_N_PKT_WORD6
 
- HDMI_SYS_CFG1C
 
- HDMI_SYS_CFG20
 
- HDMI_SYS_CTRL
 
- HDMI_SYS_PLLB_RESET
 
- HDMI_SYS_PLL_RESET
 
- HDMI_SYS_PLL_RESET_MASK
 
- HDMI_SYS_POWER_MODE_A
 
- HDMI_SYS_POWER_MODE_B
 
- HDMI_SYS_POWER_MODE_D
 
- HDMI_SYS_POWER_MODE_E
 
- HDMI_SYS_POWER_MODE_MASK
 
- HDMI_SYS_STATUS
 
- HDMI_S_AHB_CLK
 
- HDMI_TG_3D
 
- HDMI_TG_BASE
 
- HDMI_TG_CMD
 
- HDMI_TG_DECON_EN
 
- HDMI_TG_EN
 
- HDMI_TG_FIELD_BOT_HDMI_H
 
- HDMI_TG_FIELD_BOT_HDMI_L
 
- HDMI_TG_FIELD_CHG_H
 
- HDMI_TG_FIELD_CHG_L
 
- HDMI_TG_FIELD_TOP_HDMI_H
 
- HDMI_TG_FIELD_TOP_HDMI_L
 
- HDMI_TG_HACT_ST_H
 
- HDMI_TG_HACT_ST_L
 
- HDMI_TG_HACT_SZ_H
 
- HDMI_TG_HACT_SZ_L
 
- HDMI_TG_H_FSZ_H
 
- HDMI_TG_H_FSZ_L
 
- HDMI_TG_VACT_ST2_H
 
- HDMI_TG_VACT_ST2_L
 
- HDMI_TG_VACT_ST3_H
 
- HDMI_TG_VACT_ST3_L
 
- HDMI_TG_VACT_ST4_H
 
- HDMI_TG_VACT_ST4_L
 
- HDMI_TG_VACT_ST_H
 
- HDMI_TG_VACT_ST_L
 
- HDMI_TG_VACT_SZ_H
 
- HDMI_TG_VACT_SZ_L
 
- HDMI_TG_VSYNC2_H
 
- HDMI_TG_VSYNC2_L
 
- HDMI_TG_VSYNC_BOT_HDMI_H
 
- HDMI_TG_VSYNC_BOT_HDMI_L
 
- HDMI_TG_VSYNC_H
 
- HDMI_TG_VSYNC_L
 
- HDMI_TG_VSYNC_TOP_HDMI_H
 
- HDMI_TG_VSYNC_TOP_HDMI_L
 
- HDMI_TG_V_FSZ_H
 
- HDMI_TG_V_FSZ_L
 
- HDMI_TIMEOUT_PLL_LOCK
 
- HDMI_TIMEOUT_SWRESET
 
- HDMI_TOTAL_H_TOTAL
 
- HDMI_TOTAL_H_TOTAL__MASK
 
- HDMI_TOTAL_H_TOTAL__SHIFT
 
- HDMI_TOTAL_V_TOTAL
 
- HDMI_TOTAL_V_TOTAL__MASK
 
- HDMI_TOTAL_V_TOTAL__SHIFT
 
- HDMI_TST
 
- HDMI_TV_CLK
 
- HDMI_TXPHY_BIST_CONTROL
 
- HDMI_TXPHY_DIGITAL_CTRL
 
- HDMI_TXPHY_PAD_CFG_CTRL
 
- HDMI_TXPHY_POWER_CTRL
 
- HDMI_TXPHY_TX_CTRL
 
- HDMI_TX_BCBDATA0
 
- HDMI_TX_BCBDATA1
 
- HDMI_TX_GYDATA0
 
- HDMI_TX_GYDATA1
 
- HDMI_TX_INSTUFFING
 
- HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE
 
- HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE
 
- HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK
 
- HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE
 
- HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE
 
- HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK
 
- HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE
 
- HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE
 
- HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK
 
- HDMI_TX_INVID0
 
- HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE
 
- HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE
 
- HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK
 
- HDMI_TX_INVID0_VIDEO_MAPPING_MASK
 
- HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET
 
- HDMI_TX_PIXEL_EN
 
- HDMI_TX_PIXEL_SEL_MASK
 
- HDMI_TX_PIXEL_SEL_SHIFT
 
- HDMI_TX_RCRDATA0
 
- HDMI_TX_RCRDATA1
 
- HDMI_TYPE13
 
- HDMI_TYPE14
 
- HDMI_TYPE_COUNT
 
- HDMI_UNIT_EN
 
- HDMI_V13_ACR_CON
 
- HDMI_V13_ACR_CTS0
 
- HDMI_V13_ACR_CTS1
 
- HDMI_V13_ACR_CTS2
 
- HDMI_V13_ACR_MCTS0
 
- HDMI_V13_ACR_MCTS1
 
- HDMI_V13_ACR_MCTS2
 
- HDMI_V13_ACR_N0
 
- HDMI_V13_ACR_N1
 
- HDMI_V13_ACR_N2
 
- HDMI_V13_AUI_CON
 
- HDMI_V13_AVI_BYTE
 
- HDMI_V13_AVI_CON
 
- HDMI_V13_BLUE_SCREEN_0
 
- HDMI_V13_BLUE_SCREEN_1
 
- HDMI_V13_BLUE_SCREEN_2
 
- HDMI_V13_CORE_RSTOUT
 
- HDMI_V13_DC_CONTROL
 
- HDMI_V13_HPD_GEN
 
- HDMI_V13_H_SYNC_GEN_0
 
- HDMI_V13_H_SYNC_GEN_1
 
- HDMI_V13_H_SYNC_GEN_2
 
- HDMI_V13_H_V_LINE_0
 
- HDMI_V13_H_V_LINE_1
 
- HDMI_V13_H_V_LINE_2
 
- HDMI_V13_PHY_CMU
 
- HDMI_V13_PHY_RSTOUT
 
- HDMI_V13_PHY_STATUS
 
- HDMI_V13_PHY_VPLL
 
- HDMI_V13_SPD_CON
 
- HDMI_V13_VIDEO_PATTERN_GEN
 
- HDMI_V13_V_BLANK_0
 
- HDMI_V13_V_BLANK_1
 
- HDMI_V13_V_BLANK_2
 
- HDMI_V13_V_BLANK_F_0
 
- HDMI_V13_V_BLANK_F_1
 
- HDMI_V13_V_BLANK_F_2
 
- HDMI_V13_V_SYNC_GEN_1_0
 
- HDMI_V13_V_SYNC_GEN_1_1
 
- HDMI_V13_V_SYNC_GEN_1_2
 
- HDMI_V13_V_SYNC_GEN_2_0
 
- HDMI_V13_V_SYNC_GEN_2_1
 
- HDMI_V13_V_SYNC_GEN_2_2
 
- HDMI_V13_V_SYNC_GEN_3_0
 
- HDMI_V13_V_SYNC_GEN_3_1
 
- HDMI_V13_V_SYNC_GEN_3_2
 
- HDMI_V14_ACR_CON
 
- HDMI_V14_ACR_CTS0
 
- HDMI_V14_ACR_CTS1
 
- HDMI_V14_ACR_CTS2
 
- HDMI_V14_ACR_MCTS0
 
- HDMI_V14_ACR_MCTS1
 
- HDMI_V14_ACR_MCTS2
 
- HDMI_V14_ACR_N0
 
- HDMI_V14_ACR_N1
 
- HDMI_V14_ACR_N2
 
- HDMI_V14_PHY_RSTOUT
 
- HDMI_V1_BLANK_0
 
- HDMI_V1_BLANK_1
 
- HDMI_V2_BLANK_0
 
- HDMI_V2_BLANK_1
 
- HDMI_VACT_SPACE_1_0
 
- HDMI_VACT_SPACE_1_1
 
- HDMI_VACT_SPACE_2_0
 
- HDMI_VACT_SPACE_2_1
 
- HDMI_VACT_SPACE_3_0
 
- HDMI_VACT_SPACE_3_1
 
- HDMI_VACT_SPACE_4_0
 
- HDMI_VACT_SPACE_4_1
 
- HDMI_VACT_SPACE_5_0
 
- HDMI_VACT_SPACE_5_1
 
- HDMI_VACT_SPACE_6_0
 
- HDMI_VACT_SPACE_6_1
 
- HDMI_VACT_SPACE_B_0
 
- HDMI_VACT_SPACE_B_1
 
- HDMI_VACT_SPACE_G_0
 
- HDMI_VACT_SPACE_G_1
 
- HDMI_VACT_SPACE_R_0
 
- HDMI_VACT_SPACE_R_1
 
- HDMI_VBI_PACKET_CONTROL
 
- HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT
 
- HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT
 
- HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
 
- HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT
 
- HDMI_VBI_PACKET_ERROR
 
- HDMI_VBI_PKT_CTRL_ACP_SEND
 
- HDMI_VBI_PKT_CTRL_ACP_SRC_SW
 
- HDMI_VBI_PKT_CTRL_GC_ENABLE
 
- HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME
 
- HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS
 
- HDMI_VBI_PKT_CTRL_ISRC_SEND
 
- HDMI_VCO_MAX_FREQ
 
- HDMI_VCO_MIN_FREQ
 
- HDMI_VENDOR_INFOFRAME_MAX_SIZE
 
- HDMI_VIDEO_AUDIO_DISABLE_MASK
 
- HDMI_VIDEO_AV_MUTE_MASK
 
- HDMI_VIDEO_CLR_AV_MUTE
 
- HDMI_VIDEO_CONTRL
 
- HDMI_VIDEO_CONTRL1
 
- HDMI_VIDEO_CONTRL2
 
- HDMI_VIDEO_CONTRL3
 
- HDMI_VIDEO_CSC_COEF
 
- HDMI_VIDEO_CTRL1
 
- HDMI_VIDEO_CTRL2
 
- HDMI_VIDEO_DE_MASK
 
- HDMI_VIDEO_DISABLE
 
- HDMI_VIDEO_EXTERNAL_DE
 
- HDMI_VIDEO_EXT_HBLANK_H
 
- HDMI_VIDEO_EXT_HBLANK_L
 
- HDMI_VIDEO_EXT_HDELAY_H
 
- HDMI_VIDEO_EXT_HDELAY_L
 
- HDMI_VIDEO_EXT_HDURATION_H
 
- HDMI_VIDEO_EXT_HDURATION_L
 
- HDMI_VIDEO_EXT_HTOTAL_H
 
- HDMI_VIDEO_EXT_HTOTAL_L
 
- HDMI_VIDEO_EXT_VBLANK
 
- HDMI_VIDEO_EXT_VDELAY
 
- HDMI_VIDEO_EXT_VDURATION
 
- HDMI_VIDEO_EXT_VTOTAL_H
 
- HDMI_VIDEO_EXT_VTOTAL_L
 
- HDMI_VIDEO_HSYNC_ACTIVE_HIGH
 
- HDMI_VIDEO_HSYNC_ACTIVE_LOW
 
- HDMI_VIDEO_INPUT_COLOR_MASK
 
- HDMI_VIDEO_INPUT_COLOR_RGB
 
- HDMI_VIDEO_INPUT_COLOR_YCBCR
 
- HDMI_VIDEO_INPUT_DATA_DEPTH_10BIT
 
- HDMI_VIDEO_INPUT_DATA_DEPTH_12BIT
 
- HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT
 
- HDMI_VIDEO_INPUT_DATA_DEPTH_MASK
 
- HDMI_VIDEO_INPUT_FORMAT_MASK
 
- HDMI_VIDEO_INPUT_RGB_YCBCR444
 
- HDMI_VIDEO_INPUT_YCBCR422
 
- HDMI_VIDEO_INTERNAL_DE
 
- HDMI_VIDEO_MODE_HDMI
 
- HDMI_VIDEO_MODE_INTERLACE
 
- HDMI_VIDEO_MODE_MASK
 
- HDMI_VIDEO_MODE_PROGRESSIVE
 
- HDMI_VIDEO_OUTPUT_FORMAT_MASK
 
- HDMI_VIDEO_OUTPUT_RGB444
 
- HDMI_VIDEO_OUTPUT_YCBCR422
 
- HDMI_VIDEO_OUTPUT_YCBCR444
 
- HDMI_VIDEO_PATTERN_GEN
 
- HDMI_VIDEO_REG
 
- HDMI_VIDEO_SEL
 
- HDMI_VIDEO_SET_AV_MUTE
 
- HDMI_VIDEO_TIMING_CTL
 
- HDMI_VIDEO_VSYNC_ACTIVE_HIGH
 
- HDMI_VIDEO_VSYNC_ACTIVE_LOW
 
- HDMI_VIDEO_VSYNC_OFFSET_SHIFT
 
- HDMI_VID_PREAMBLE_DIS
 
- HDMI_VP_CONF
 
- HDMI_VP_CONF_BYPASS_EN_DISABLE
 
- HDMI_VP_CONF_BYPASS_EN_ENABLE
 
- HDMI_VP_CONF_BYPASS_EN_MASK
 
- HDMI_VP_CONF_BYPASS_SELECT_MASK
 
- HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER
 
- HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER
 
- HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS
 
- HDMI_VP_CONF_OUTPUT_SELECTOR_MASK
 
- HDMI_VP_CONF_OUTPUT_SELECTOR_PP
 
- HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422
 
- HDMI_VP_CONF_PP_EN_DISABLE
 
- HDMI_VP_CONF_PP_EN_ENABLE
 
- HDMI_VP_CONF_PP_EN_ENMASK
 
- HDMI_VP_CONF_PR_EN_DISABLE
 
- HDMI_VP_CONF_PR_EN_ENABLE
 
- HDMI_VP_CONF_PR_EN_MASK
 
- HDMI_VP_CONF_YCC422_EN_DISABLE
 
- HDMI_VP_CONF_YCC422_EN_ENABLE
 
- HDMI_VP_CONF_YCC422_EN_MASK
 
- HDMI_VP_INT
 
- HDMI_VP_MASK
 
- HDMI_VP_POL
 
- HDMI_VP_PR_CD
 
- HDMI_VP_PR_CD_COLOR_DEPTH_MASK
 
- HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET
 
- HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK
 
- HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET
 
- HDMI_VP_REMAP
 
- HDMI_VP_REMAP_MASK
 
- HDMI_VP_REMAP_YCC422_16bit
 
- HDMI_VP_REMAP_YCC422_20bit
 
- HDMI_VP_REMAP_YCC422_24bit
 
- HDMI_VP_STAT
 
- HDMI_VP_STATUS
 
- HDMI_VP_STUFF
 
- HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK
 
- HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET
 
- HDMI_VP_STUFF_IDEFAULT_PHASE_MASK
 
- HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET
 
- HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK
 
- HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET
 
- HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE
 
- HDMI_VP_STUFF_PP_STUFFING_MASK
 
- HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE
 
- HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE
 
- HDMI_VP_STUFF_PR_STUFFING_MASK
 
- HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE
 
- HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE
 
- HDMI_VP_STUFF_YCC422_STUFFING_MASK
 
- HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE
 
- HDMI_VSI_CON
 
- HDMI_VSI_CON_DO_NOT_TRANSMIT
 
- HDMI_VSI_CON_EVERY_VSYNC
 
- HDMI_VSI_DATA
 
- HDMI_VSI_HEADER0
 
- HDMI_VSI_HEADER1
 
- HDMI_VSI_HEADER2
 
- HDMI_VSYNC_ACTIVE_F2_END
 
- HDMI_VSYNC_ACTIVE_F2_END__MASK
 
- HDMI_VSYNC_ACTIVE_F2_END__SHIFT
 
- HDMI_VSYNC_ACTIVE_F2_START
 
- HDMI_VSYNC_ACTIVE_F2_START__MASK
 
- HDMI_VSYNC_ACTIVE_F2_START__SHIFT
 
- HDMI_VSYNC_ACTIVE_HIGH
 
- HDMI_VSYNC_POL
 
- HDMI_VSYNC_TOTAL_F2_V_TOTAL
 
- HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK
 
- HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT
 
- HDMI_V_BLANK_F0_0
 
- HDMI_V_BLANK_F0_1
 
- HDMI_V_BLANK_F1_0
 
- HDMI_V_BLANK_F1_1
 
- HDMI_V_BLANK_F2_0
 
- HDMI_V_BLANK_F2_1
 
- HDMI_V_BLANK_F3_0
 
- HDMI_V_BLANK_F3_1
 
- HDMI_V_BLANK_F4_0
 
- HDMI_V_BLANK_F4_1
 
- HDMI_V_BLANK_F5_0
 
- HDMI_V_BLANK_F5_1
 
- HDMI_V_LINE_0
 
- HDMI_V_LINE_1
 
- HDMI_V_SYNC_LINE_AFT_1_0
 
- HDMI_V_SYNC_LINE_AFT_1_1
 
- HDMI_V_SYNC_LINE_AFT_2_0
 
- HDMI_V_SYNC_LINE_AFT_2_1
 
- HDMI_V_SYNC_LINE_AFT_3_0
 
- HDMI_V_SYNC_LINE_AFT_3_1
 
- HDMI_V_SYNC_LINE_AFT_4_0
 
- HDMI_V_SYNC_LINE_AFT_4_1
 
- HDMI_V_SYNC_LINE_AFT_5_0
 
- HDMI_V_SYNC_LINE_AFT_5_1
 
- HDMI_V_SYNC_LINE_AFT_6_0
 
- HDMI_V_SYNC_LINE_AFT_6_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_1_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_1_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_2_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_2_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_3_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_3_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_4_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_4_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_5_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_5_1
 
- HDMI_V_SYNC_LINE_AFT_PXL_6_0
 
- HDMI_V_SYNC_LINE_AFT_PXL_6_1
 
- HDMI_V_SYNC_LINE_BEF_1_0
 
- HDMI_V_SYNC_LINE_BEF_1_1
 
- HDMI_V_SYNC_LINE_BEF_2_0
 
- HDMI_V_SYNC_LINE_BEF_2_1
 
- HDMI_WORKING_INT
 
- HDMI_WP_AUDIO_CFG
 
- HDMI_WP_AUDIO_CFG2
 
- HDMI_WP_AUDIO_CTRL
 
- HDMI_WP_AUDIO_DATA
 
- HDMI_WP_CLK
 
- HDMI_WP_DEBOUNCE
 
- HDMI_WP_IRQENABLE_CLR
 
- HDMI_WP_IRQENABLE_SET
 
- HDMI_WP_IRQSTATUS
 
- HDMI_WP_IRQSTATUS_RAW
 
- HDMI_WP_IRQWAKEEN
 
- HDMI_WP_PWR_CTRL
 
- HDMI_WP_REVISION
 
- HDMI_WP_SYSCONFIG
 
- HDMI_WP_VIDEO_CFG
 
- HDMI_WP_VIDEO_SIZE
 
- HDMI_WP_VIDEO_TIMING_H
 
- HDMI_WP_VIDEO_TIMING_V
 
- HDMI_WRITE
 
- HDMI_XCLK
 
- HDMI_XML
 
- HDMI_YCC_QUANTIZATION_RANGE_FULL
 
- HDMI_YCC_QUANTIZATION_RANGE_LIMITED
 
- HDMI_YMAX
 
- HDMI_YMIN
 
- HDMI__MEM_PG
 
- HDMI__MEM_PG__0
 
- HDMR_AC_8_16
 
- HDMR_AC_B_L
 
- HDMR_AC_MASK
 
- HDMR_AC_M_S
 
- HDMR_AC_S_U
 
- HDO
 
- HDOUBLESCAN
 
- HDP
 
- HDP1_INTERRUPT_ID
 
- HDP2_INTERRUPT_ID
 
- HDP3_INTERRUPT_ID
 
- HDP4_INTERRUPT_ID
 
- HDP5_INTERRUPT_ID
 
- HDP6_INTERRUPT_ID
 
- HDPVR_50HZ
 
- HDPVR_60HZ
 
- HDPVR_ADVANCED_IDR_GOP
 
- HDPVR_ADVANCED_NOIDR_GOP
 
- HDPVR_AUDIO_INPUTS
 
- HDPVR_COMPONENT
 
- HDPVR_COMPOSITE
 
- HDPVR_CONSTANT
 
- HDPVR_DEF_DV_TIMINGS_IDX
 
- HDPVR_FIRMWARE_VERSION
 
- HDPVR_FIRMWARE_VERSION_0X12
 
- HDPVR_FIRMWARE_VERSION_0X15
 
- HDPVR_FIRMWARE_VERSION_0X1E
 
- HDPVR_FIRMWARE_VERSION_AC3
 
- HDPVR_FLAG_AC3_CAP
 
- HDPVR_I2C_MAX_SIZE
 
- HDPVR_MAX
 
- HDPVR_RCA_BACK
 
- HDPVR_RCA_FRONT
 
- HDPVR_SIMPLE_IDR_GOP
 
- HDPVR_SIMPLE_NOIDR_GOP
 
- HDPVR_SPDIF
 
- HDPVR_SVIDEO
 
- HDPVR_VARIABLE_AVERAGE
 
- HDPVR_VARIABLE_PEAK
 
- HDPVR_VIDEO_INPUTS
 
- HDP_ADDR_CONFIG
 
- HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- HDP_ADDR_CONFIG__NUM_GPUS_MASK
 
- HDP_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- HDP_ADDR_CONFIG__NUM_PIPES_MASK
 
- HDP_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- HDP_ADDR_CONFIG__ROW_SIZE_MASK
 
- HDP_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- HDP_BASE__INST0_SEG0
 
- HDP_BASE__INST0_SEG1
 
- HDP_BASE__INST0_SEG2
 
- HDP_BASE__INST0_SEG3
 
- HDP_BASE__INST0_SEG4
 
- HDP_BASE__INST0_SEG5
 
- HDP_BASE__INST1_SEG0
 
- HDP_BASE__INST1_SEG1
 
- HDP_BASE__INST1_SEG2
 
- HDP_BASE__INST1_SEG3
 
- HDP_BASE__INST1_SEG4
 
- HDP_BASE__INST1_SEG5
 
- HDP_BASE__INST2_SEG0
 
- HDP_BASE__INST2_SEG1
 
- HDP_BASE__INST2_SEG2
 
- HDP_BASE__INST2_SEG3
 
- HDP_BASE__INST2_SEG4
 
- HDP_BASE__INST2_SEG5
 
- HDP_BASE__INST3_SEG0
 
- HDP_BASE__INST3_SEG1
 
- HDP_BASE__INST3_SEG2
 
- HDP_BASE__INST3_SEG3
 
- HDP_BASE__INST3_SEG4
 
- HDP_BASE__INST3_SEG5
 
- HDP_BASE__INST4_SEG0
 
- HDP_BASE__INST4_SEG1
 
- HDP_BASE__INST4_SEG2
 
- HDP_BASE__INST4_SEG3
 
- HDP_BASE__INST4_SEG4
 
- HDP_BASE__INST4_SEG5
 
- HDP_BASE__INST5_SEG0
 
- HDP_BASE__INST5_SEG1
 
- HDP_BASE__INST5_SEG2
 
- HDP_BASE__INST5_SEG3
 
- HDP_BASE__INST5_SEG4
 
- HDP_BASE__INST5_SEG5
 
- HDP_BASE__INST6_SEG0
 
- HDP_BASE__INST6_SEG1
 
- HDP_BASE__INST6_SEG2
 
- HDP_BASE__INST6_SEG3
 
- HDP_BASE__INST6_SEG4
 
- HDP_BASE__INST6_SEG5
 
- HDP_BASE__INST7_SEG0
 
- HDP_BASE__INST7_SEG1
 
- HDP_BASE__INST7_SEG2
 
- HDP_BASE__INST7_SEG3
 
- HDP_BASE__INST7_SEG4
 
- HDP_BASE__INST7_SEG5
 
- HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK
 
- HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT
 
- HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK
 
- HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT
 
- HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK
 
- HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT
 
- HDP_DEBUG
 
- HDP_DEBUG0
 
- HDP_DEBUG0__HDP_DEBUG_MASK
 
- HDP_DEBUG0__HDP_DEBUG__SHIFT
 
- HDP_DEBUG1
 
- HDP_DEBUG1__HDP_DEBUG__SHIFT
 
- HDP_DYN_CNTL
 
- HDP_EDC_CNT__MEM0_SED_COUNT_MASK
 
- HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT
 
- HDP_EDC_CNT__MEM1_SED_COUNT_MASK
 
- HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT
 
- HDP_EDC_CNT__MEM2_SED_COUNT_MASK
 
- HDP_EDC_CNT__MEM2_SED_COUNT__SHIFT
 
- HDP_EDC_CNT__MEM3_SED_COUNT_MASK
 
- HDP_EDC_CNT__MEM3_SED_COUNT__SHIFT
 
- HDP_ENDIAN_8IN16
 
- HDP_ENDIAN_8IN32
 
- HDP_ENDIAN_8IN64
 
- HDP_ENDIAN_NONE
 
- HDP_FB_LOCATION
 
- HDP_FLUSH_INVALIDATE_CACHE
 
- HDP_FORCEON
 
- HDP_HOST_PATH_CNTL
 
- HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK
 
- HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT
 
- HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK
 
- HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT
 
- HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK
 
- HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT
 
- HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK
 
- HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT
 
- HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK
 
- HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT
 
- HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK
 
- HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT
 
- HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN_MASK
 
- HDP_HOST_PATH_CNTL__RD_CPL_BUF_EN__SHIFT
 
- HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK
 
- HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT
 
- HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK
 
- HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT
 
- HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT
 
- HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK
 
- HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT
 
- HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK
 
- HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT
 
- HDP_HWID
 
- HDP_HWIP
 
- HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK
 
- HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT
 
- HDP_LS_ENABLE
 
- HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK
 
- HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK
 
- HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_BE_MASK
 
- HDP_MEMIO_CNTL__MEMIO_BE__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK
 
- HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK
 
- HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_OP_MASK
 
- HDP_MEMIO_CNTL__MEMIO_OP__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK
 
- HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_SEND_MASK
 
- HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_VFID_MASK
 
- HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_VF_MASK
 
- HDP_MEMIO_CNTL__MEMIO_VF__SHIFT
 
- HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK
 
- HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT
 
- HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK
 
- HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT
 
- HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK
 
- HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT
 
- HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK
 
- HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT
 
- HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK
 
- HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT
 
- HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK
 
- HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT
 
- HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK
 
- HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT
 
- HDP_MEM_COHERENCY_FLUSH_CNTL
 
- HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR_MASK
 
- HDP_MEM_COHERENCY_FLUSH_CNTL_IND__HDP_MEM_FLUSH_ADDR__SHIFT
 
- HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK
 
- HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK
 
- HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_IDLE_HYSTERESIS__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY_MASK
 
- HDP_MEM_POWER_CTRL__IPH_MEM_POWER_UP_RECOVER_DELAY__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_IDLE_HYSTERESIS__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_DOWN_LS_ENTER_DELAY__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_DS_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_SD_EN__SHIFT
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY_MASK
 
- HDP_MEM_POWER_CTRL__RC_MEM_POWER_UP_RECOVER_DELAY__SHIFT
 
- HDP_MEM_POWER_LS
 
- HDP_MEM_POWER_LS__LS_ENABLE_MASK
 
- HDP_MEM_POWER_LS__LS_ENABLE__SHIFT
 
- HDP_MEM_POWER_LS__LS_HOLD_MASK
 
- HDP_MEM_POWER_LS__LS_HOLD__SHIFT
 
- HDP_MEM_POWER_LS__LS_SETUP_MASK
 
- HDP_MEM_POWER_LS__LS_SETUP__SHIFT
 
- HDP_MISC_CNTL
 
- HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK
 
- HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT
 
- HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK
 
- HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT
 
- HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK
 
- HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT
 
- HDP_MISC_CNTL__ATOMIC_FED_ENABLE_MASK
 
- HDP_MISC_CNTL__ATOMIC_FED_ENABLE__SHIFT
 
- HDP_MISC_CNTL__FED_ENABLE_MASK
 
- HDP_MISC_CNTL__FED_ENABLE__SHIFT
 
- HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK
 
- HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT
 
- HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK
 
- HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT
 
- HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK
 
- HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT
 
- HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK
 
- HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT
 
- HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE_MASK
 
- HDP_MISC_CNTL__LEGACY_SURFACES_ENABLE__SHIFT
 
- HDP_MISC_CNTL__LEGACY_TILING_ENABLE_MASK
 
- HDP_MISC_CNTL__LEGACY_TILING_ENABLE__SHIFT
 
- HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK
 
- HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT
 
- HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE_MASK
 
- HDP_MISC_CNTL__MMHUB_EARLY_WRACK_ENABLE__SHIFT
 
- HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK
 
- HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT
 
- HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK
 
- HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT
 
- HDP_MISC_CNTL__MULTIPLE_READS_MASK
 
- HDP_MISC_CNTL__MULTIPLE_READS__SHIFT
 
- HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK
 
- HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT
 
- HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK
 
- HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT
 
- HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE_MASK
 
- HDP_MISC_CNTL__RAW_ADDR_CAM_ENABLE__SHIFT
 
- HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK
 
- HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT
 
- HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK
 
- HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT
 
- HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK
 
- HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT
 
- HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK
 
- HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT
 
- HDP_MISC_CNTL__VM_ID_MASK
 
- HDP_MISC_CNTL__VM_ID__SHIFT
 
- HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK
 
- HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT
 
- HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK
 
- HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT
 
- HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK
 
- HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT
 
- HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK
 
- HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT
 
- HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK
 
- HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT
 
- HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK
 
- HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT
 
- HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK
 
- HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT
 
- HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK
 
- HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT
 
- HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK
 
- HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT
 
- HDP_MMHUB_UNITID__HDP_UNITID_MASK
 
- HDP_MMHUB_UNITID__HDP_UNITID__SHIFT
 
- HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK
 
- HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT
 
- HDP_MMHUB_UNITID__XDP_UNITID_MASK
 
- HDP_MMHUB_UNITID__XDP_UNITID__SHIFT
 
- HDP_NONSURFACE_BASE
 
- HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK
 
- HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT
 
- HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK
 
- HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT
 
- HDP_NONSURFACE_BASE__NONSURF_BASE_MASK
 
- HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT
 
- HDP_NONSURFACE_INFO
 
- HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT
 
- HDP_NONSURFACE_INFO__NONSURF_VMID_MASK
 
- HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK
 
- HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT
 
- HDP_NONSURFACE_SIZE
 
- HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK
 
- HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT
 
- HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK
 
- HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT
 
- HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK
 
- HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT
 
- HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK
 
- HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT
 
- HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK
 
- HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT
 
- HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK
 
- HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT
 
- HDP_OUTSTANDING_REQ__READ_REQ_MASK
 
- HDP_OUTSTANDING_REQ__READ_REQ__SHIFT
 
- HDP_OUTSTANDING_REQ__WRITE_REQ_MASK
 
- HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT
 
- HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK
 
- HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT
 
- HDP_REG_COHERENCY_FLUSH_CNTL
 
- HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR_MASK
 
- HDP_REG_COHERENCY_FLUSH_CNTL_IND__HDP_REG_FLUSH_ADDR__SHIFT
 
- HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK
 
- HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK
 
- HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT
 
- HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK
 
- HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT
 
- HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK
 
- HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT
 
- HDP_SOFT_RESET
 
- HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR_MASK
 
- HDP_SURFACE_READ_FLAGS_CLR__SURF0_READ_FLAG_CLR__SHIFT
 
- HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR_MASK
 
- HDP_SURFACE_READ_FLAGS_CLR__SURF1_READ_FLAG_CLR__SHIFT
 
- HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG_MASK
 
- HDP_SURFACE_READ_FLAGS__SURF0_READ_FLAG__SHIFT
 
- HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG_MASK
 
- HDP_SURFACE_READ_FLAGS__SURF1_READ_FLAG__SHIFT
 
- HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR_MASK
 
- HDP_SURFACE_WRITE_FLAGS_CLR__SURF0_WRITE_FLAG_CLR__SHIFT
 
- HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR_MASK
 
- HDP_SURFACE_WRITE_FLAGS_CLR__SURF1_WRITE_FLAG_CLR__SHIFT
 
- HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG_MASK
 
- HDP_SURFACE_WRITE_FLAGS__SURF0_WRITE_FLAG__SHIFT
 
- HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG_MASK
 
- HDP_SURFACE_WRITE_FLAGS__SURF1_WRITE_FLAG__SHIFT
 
- HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK
 
- HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT
 
- HDP_TILING_CONFIG
 
- HDP_TILING_CONFIG__BANK_SWAPS_MASK
 
- HDP_TILING_CONFIG__BANK_SWAPS__SHIFT
 
- HDP_TILING_CONFIG__BANK_TILING_MASK
 
- HDP_TILING_CONFIG__BANK_TILING__SHIFT
 
- HDP_TILING_CONFIG__GROUP_SIZE_MASK
 
- HDP_TILING_CONFIG__GROUP_SIZE__SHIFT
 
- HDP_TILING_CONFIG__PIPE_TILING_MASK
 
- HDP_TILING_CONFIG__PIPE_TILING__SHIFT
 
- HDP_TILING_CONFIG__ROW_TILING_MASK
 
- HDP_TILING_CONFIG__ROW_TILING__SHIFT
 
- HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK
 
- HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT
 
- HDP_VERSION__MAJVER_MASK
 
- HDP_VERSION__MAJVER__SHIFT
 
- HDP_VERSION__MINVER_MASK
 
- HDP_VERSION__MINVER__SHIFT
 
- HDP_VERSION__REV_MASK
 
- HDP_VERSION__REV__SHIFT
 
- HDP_VF_ENABLE__VF_EN_MASK
 
- HDP_VF_ENABLE__VF_EN__SHIFT
 
- HDP_VF_ENABLE__VF_NUM_MASK
 
- HDP_VF_ENABLE__VF_NUM__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT
 
- HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK
 
- HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT
 
- HDP_XDP_BUSY_STS__BUSY_BITS_MASK
 
- HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK
 
- HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT
 
- HDP_XDP_CHKN__CHKN_0_RSVD_MASK
 
- HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT
 
- HDP_XDP_CHKN__CHKN_1_RSVD_MASK
 
- HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT
 
- HDP_XDP_CHKN__CHKN_2_RSVD_MASK
 
- HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT
 
- HDP_XDP_CHKN__CHKN_3_RSVD_MASK
 
- HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK
 
- HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK
 
- HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT
 
- HDP_XDP_D2H_RSVD_10__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_11__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_12__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_13__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_14__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_15__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_16__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_17__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_18__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_19__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_20__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_21__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_22__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_23__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_24__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_25__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_26__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_27__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_28__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_29__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_30__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_31__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_32__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_33__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_34__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_3__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_4__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_5__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_6__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_7__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_8__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT
 
- HDP_XDP_D2H_RSVD_9__RESERVED_MASK
 
- HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT
 
- HDP_XDP_DBG_ADDR__CTRL_MASK
 
- HDP_XDP_DBG_ADDR__CTRL__SHIFT
 
- HDP_XDP_DBG_ADDR__STS_MASK
 
- HDP_XDP_DBG_ADDR__STS__SHIFT
 
- HDP_XDP_DBG_DATA__CTRL_MASK
 
- HDP_XDP_DBG_DATA__CTRL__SHIFT
 
- HDP_XDP_DBG_DATA__STS_MASK
 
- HDP_XDP_DBG_DATA__STS__SHIFT
 
- HDP_XDP_DBG_MASK__CTRL_MASK
 
- HDP_XDP_DBG_MASK__CTRL__SHIFT
 
- HDP_XDP_DBG_MASK__STS_MASK
 
- HDP_XDP_DBG_MASK__STS__SHIFT
 
- HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK
 
- HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT
 
- HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK
 
- HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT
 
- HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK
 
- HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT
 
- HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK
 
- HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK
 
- HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK
 
- HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK
 
- HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK
 
- HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT
 
- HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK
 
- HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT
 
- HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT
 
- HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK
 
- HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK
 
- HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK
 
- HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT
 
- HDP_XDP_P2P_BAR0__ADDR_MASK
 
- HDP_XDP_P2P_BAR0__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR0__FLUSH_MASK
 
- HDP_XDP_P2P_BAR0__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR0__VALID_MASK
 
- HDP_XDP_P2P_BAR0__VALID__SHIFT
 
- HDP_XDP_P2P_BAR1__ADDR_MASK
 
- HDP_XDP_P2P_BAR1__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR1__FLUSH_MASK
 
- HDP_XDP_P2P_BAR1__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR1__VALID_MASK
 
- HDP_XDP_P2P_BAR1__VALID__SHIFT
 
- HDP_XDP_P2P_BAR2__ADDR_MASK
 
- HDP_XDP_P2P_BAR2__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR2__FLUSH_MASK
 
- HDP_XDP_P2P_BAR2__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR2__VALID_MASK
 
- HDP_XDP_P2P_BAR2__VALID__SHIFT
 
- HDP_XDP_P2P_BAR3__ADDR_MASK
 
- HDP_XDP_P2P_BAR3__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR3__FLUSH_MASK
 
- HDP_XDP_P2P_BAR3__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR3__VALID_MASK
 
- HDP_XDP_P2P_BAR3__VALID__SHIFT
 
- HDP_XDP_P2P_BAR4__ADDR_MASK
 
- HDP_XDP_P2P_BAR4__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR4__FLUSH_MASK
 
- HDP_XDP_P2P_BAR4__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR4__VALID_MASK
 
- HDP_XDP_P2P_BAR4__VALID__SHIFT
 
- HDP_XDP_P2P_BAR5__ADDR_MASK
 
- HDP_XDP_P2P_BAR5__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR5__FLUSH_MASK
 
- HDP_XDP_P2P_BAR5__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR5__VALID_MASK
 
- HDP_XDP_P2P_BAR5__VALID__SHIFT
 
- HDP_XDP_P2P_BAR6__ADDR_MASK
 
- HDP_XDP_P2P_BAR6__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR6__FLUSH_MASK
 
- HDP_XDP_P2P_BAR6__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR6__VALID_MASK
 
- HDP_XDP_P2P_BAR6__VALID__SHIFT
 
- HDP_XDP_P2P_BAR7__ADDR_MASK
 
- HDP_XDP_P2P_BAR7__ADDR__SHIFT
 
- HDP_XDP_P2P_BAR7__FLUSH_MASK
 
- HDP_XDP_P2P_BAR7__FLUSH__SHIFT
 
- HDP_XDP_P2P_BAR7__VALID_MASK
 
- HDP_XDP_P2P_BAR7__VALID__SHIFT
 
- HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK
 
- HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT
 
- HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK
 
- HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR0__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR1__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR2__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR3__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR4__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR5__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK
 
- HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT
 
- HDP_XDP_P2P_MBX_ADDR6__VALID_MASK
 
- HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT
 
- HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK
 
- HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT
 
- HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK
 
- HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT
 
- HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK
 
- HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT
 
- HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK
 
- HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK
 
- HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT
 
- HDP_XDP_STICKY__STICKY_STS_MASK
 
- HDP_XDP_STICKY__STICKY_STS__SHIFT
 
- HDP_XDP_STICKY__STICKY_W1C_MASK
 
- HDP_XDP_STICKY__STICKY_W1C__SHIFT
 
- HDQ_CMD_READ
 
- HDQ_CMD_WRITE
 
- HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT
 
- HDQ_CTRL_STATUS_OFFSET
 
- HDR
 
- HDRIVE_BMSK
 
- HDRIVE_SHFT
 
- HDRQ_INCREMENT
 
- HDRQ_SIZE_SHIFT
 
- HDRSTARTFLQ_G
 
- HDRSTARTFLQ_M
 
- HDRSTARTFLQ_S
 
- HDRSZ
 
- HDR_API_VERS
 
- HDR_CLOCK_GPIO_BIT
 
- HDR_CLOCK_GPIO_DADDR
 
- HDR_CLOCK_GPIO_VADDR
 
- HDR_CMD_STAT_AREA
 
- HDR_DATA_GPIO_BIT
 
- HDR_DATA_GPIO_DADDR
 
- HDR_DATA_GPIO_VADDR
 
- HDR_DESCLEN_MASK
 
- HDR_DESCLEN_SHR_MASK
 
- HDR_DIGEST
 
- HDR_DNR
 
- HDR_FW_CONTROL
 
- HDR_FW_OPTIONS
 
- HDR_FW_SIZE
 
- HDR_FW_VERS
 
- HDR_JD_LENGTH_MASK
 
- HDR_JD_SHARE_MASK
 
- HDR_JD_SHARE_SHIFT
 
- HDR_LEN
 
- HDR_LEN_L2_ONLY
 
- HDR_LEN_L2_VLAN
 
- HDR_MAKE_TRUSTED
 
- HDR_NOT_LPAR
 
- HDR_OFFSET
 
- HDR_ONE
 
- HDR_PARSING_BUF_SZ
 
- HDR_PCR
 
- HDR_PERF_UNAV
 
- HDR_PROP_DNR
 
- HDR_REVERSE
 
- HDR_SAVECTX
 
- HDR_SD_LENGTH_MASK
 
- HDR_SD_SHARE_MASK
 
- HDR_SD_SHARE_SHIFT
 
- HDR_SHARED
 
- HDR_SHARE_ALWAYS
 
- HDR_SHARE_DEFER
 
- HDR_SHARE_NEVER
 
- HDR_SHARE_SERIAL
 
- HDR_SHARE_WAIT
 
- HDR_SIZE
 
- HDR_STACK_INCM
 
- HDR_START_IDX_MASK
 
- HDR_START_IDX_SHIFT
 
- HDR_STATIC_METADATA_BLOCK
 
- HDR_STSI_UNAV
 
- HDR_SYS_SIG
 
- HDR_TEMPLATE_DATA
 
- HDR_TEMPLATE_NAME
 
- HDR_TRANS_GPIO_BIT
 
- HDR_TRANS_GPIO_DADDR
 
- HDR_TRANS_GPIO_VADDR
 
- HDR_TRUSTED
 
- HDR_ZRO
 
- HDR__LAST
 
- HDSP2534_ADDR
 
- HDSPM_AB_int
 
- HDSPM_ADDON_TCO
 
- HDSPM_AES32_AUTOSYNC_FROM_AES1
 
- HDSPM_AES32_AUTOSYNC_FROM_AES2
 
- HDSPM_AES32_AUTOSYNC_FROM_AES3
 
- HDSPM_AES32_AUTOSYNC_FROM_AES4
 
- HDSPM_AES32_AUTOSYNC_FROM_AES5
 
- HDSPM_AES32_AUTOSYNC_FROM_AES6
 
- HDSPM_AES32_AUTOSYNC_FROM_AES7
 
- HDSPM_AES32_AUTOSYNC_FROM_AES8
 
- HDSPM_AES32_AUTOSYNC_FROM_NONE
 
- HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN
 
- HDSPM_AES32_AUTOSYNC_FROM_TCO
 
- HDSPM_AES32_AUTOSYNC_FROM_WORD
 
- HDSPM_AES32_syncref_bit
 
- HDSPM_AES32_wcFreq_bit
 
- HDSPM_AES32_wcLock
 
- HDSPM_AES32_wcSync
 
- HDSPM_AIO_REV
 
- HDSPM_AUTOSYNC_FROM_MADI
 
- HDSPM_AUTOSYNC_FROM_NONE
 
- HDSPM_AUTOSYNC_FROM_SYNC_IN
 
- HDSPM_AUTOSYNC_FROM_TCO
 
- HDSPM_AUTOSYNC_FROM_WORD
 
- HDSPM_AUTOSYNC_REF
 
- HDSPM_AUTOSYNC_SAMPLE_RATE
 
- HDSPM_AudioInterruptEnable
 
- HDSPM_AutoInp
 
- HDSPM_BIGENDIAN_MODE
 
- HDSPM_BufferID
 
- HDSPM_BufferPositionMask
 
- HDSPM_CHANNEL_BUFFER_BYTES
 
- HDSPM_CHANNEL_BUFFER_SAMPLES
 
- HDSPM_COAXIAL
 
- HDSPM_CONFIG_MODE_0
 
- HDSPM_CONFIG_MODE_1
 
- HDSPM_CONTROL_TRISTATE
 
- HDSPM_ClockModeMaster
 
- HDSPM_DMA_AREA_BYTES
 
- HDSPM_DMA_AREA_KILOBYTES
 
- HDSPM_DS_DoubleWire
 
- HDSPM_DS_WIRE
 
- HDSPM_Dolby
 
- HDSPM_DoubleSpeed
 
- HDSPM_DoubleSpeedStatus
 
- HDSPM_Emphasis
 
- HDSPM_Frequency0
 
- HDSPM_Frequency1
 
- HDSPM_Frequency128KHz
 
- HDSPM_Frequency176_4KHz
 
- HDSPM_Frequency192KHz
 
- HDSPM_Frequency32KHz
 
- HDSPM_Frequency44_1KHz
 
- HDSPM_Frequency48KHz
 
- HDSPM_Frequency64KHz
 
- HDSPM_Frequency88_2KHz
 
- HDSPM_Frequency96KHz
 
- HDSPM_FrequencyMask
 
- HDSPM_INPUT_SELECT
 
- HDSPM_INTERNAL_CLOCK
 
- HDSPM_InputCoaxial
 
- HDSPM_InputMask
 
- HDSPM_InputOptical
 
- HDSPM_InputSelect0
 
- HDSPM_InputSelect1
 
- HDSPM_JTAG
 
- HDSPM_Latency0
 
- HDSPM_Latency1
 
- HDSPM_Latency2
 
- HDSPM_LatencyMask
 
- HDSPM_LineOut
 
- HDSPM_LockAES
 
- HDSPM_LockAES1
 
- HDSPM_LockAES2
 
- HDSPM_LockAES3
 
- HDSPM_LockAES4
 
- HDSPM_LockAES5
 
- HDSPM_LockAES6
 
- HDSPM_LockAES7
 
- HDSPM_LockAES8
 
- HDSPM_MADIFACE_REV
 
- HDSPM_MADI_INPUT_PEAK
 
- HDSPM_MADI_INPUT_RMS_H
 
- HDSPM_MADI_INPUT_RMS_L
 
- HDSPM_MADI_OUTPUT_PEAK
 
- HDSPM_MADI_OUTPUT_RMS_H
 
- HDSPM_MADI_OUTPUT_RMS_L
 
- HDSPM_MADI_PLAYBACK_PEAK
 
- HDSPM_MADI_PLAYBACK_RMS_H
 
- HDSPM_MADI_PLAYBACK_RMS_L
 
- HDSPM_MADI_SPEEDMODE
 
- HDSPM_MADI_mixerBase
 
- HDSPM_MATRIX_MIXER_SIZE
 
- HDSPM_MAX_CHANNELS
 
- HDSPM_MIXER
 
- HDSPM_MIXER_CHANNELS
 
- HDSPM_Midi0InterruptEnable
 
- HDSPM_Midi1InterruptEnable
 
- HDSPM_Midi2InterruptEnable
 
- HDSPM_Midi3InterruptEnable
 
- HDSPM_OPTICAL
 
- HDSPM_PLAYBACK_MIXER
 
- HDSPM_PREF_SYNC_REF
 
- HDSPM_PROGRAM
 
- HDSPM_PWDN
 
- HDSPM_Professional
 
- HDSPM_QS_DoubleWire
 
- HDSPM_QS_QuadWire
 
- HDSPM_QS_WIRE
 
- HDSPM_QuadSpeed
 
- HDSPM_RAYDAT_REV
 
- HDSPM_RD_MULTIPLE
 
- HDSPM_RD_PLL_FREQ
 
- HDSPM_RD_STATUS_0
 
- HDSPM_RD_STATUS_1
 
- HDSPM_RD_STATUS_2
 
- HDSPM_RD_STATUS_3
 
- HDSPM_RD_TCO
 
- HDSPM_RX_64ch
 
- HDSPM_SMUX
 
- HDSPM_SPEED_DOUBLE
 
- HDSPM_SPEED_QUAD
 
- HDSPM_SPEED_SINGLE
 
- HDSPM_SYNC_CHECK
 
- HDSPM_SYNC_CHECK_LOCK
 
- HDSPM_SYNC_CHECK_NO_LOCK
 
- HDSPM_SYNC_CHECK_SYNC
 
- HDSPM_SYNC_FROM_MADI
 
- HDSPM_SYNC_FROM_SYNC_IN
 
- HDSPM_SYNC_FROM_TCO
 
- HDSPM_SYNC_FROM_WORD
 
- HDSPM_SYSTEM_CLOCK_MODE
 
- HDSPM_SYSTEM_SAMPLE_RATE
 
- HDSPM_SelSyncRef0
 
- HDSPM_SelSyncRef1
 
- HDSPM_SelSyncRef2
 
- HDSPM_SelSyncRefMask
 
- HDSPM_SelSyncRef_MADI
 
- HDSPM_SelSyncRef_NVALID
 
- HDSPM_SelSyncRef_SyncIn
 
- HDSPM_SelSyncRef_TCO
 
- HDSPM_SelSyncRef_WORD
 
- HDSPM_Start
 
- HDSPM_SyncRef0
 
- HDSPM_SyncRef1
 
- HDSPM_SyncRef2
 
- HDSPM_SyncRef3
 
- HDSPM_SyncRefMask
 
- HDSPM_TCK
 
- HDSPM_TCO1_LTC_Format_LSB
 
- HDSPM_TCO1_LTC_Format_MSB
 
- HDSPM_TCO1_LTC_Input_valid
 
- HDSPM_TCO1_TCO_lock
 
- HDSPM_TCO1_Video_Input_Format_NTSC
 
- HDSPM_TCO1_Video_Input_Format_PAL
 
- HDSPM_TCO1_WCK_Input_Range_LSB
 
- HDSPM_TCO1_WCK_Input_Range_MSB
 
- HDSPM_TCO1_WCK_Input_valid
 
- HDSPM_TCO1_set_TC
 
- HDSPM_TCO1_set_drop_frame_flag
 
- HDSPM_TCO2_TC_run
 
- HDSPM_TCO2_WCK_IO_ratio_LSB
 
- HDSPM_TCO2_WCK_IO_ratio_MSB
 
- HDSPM_TCO2_set_01_4
 
- HDSPM_TCO2_set_flywheel
 
- HDSPM_TCO2_set_freq
 
- HDSPM_TCO2_set_freq_from_app
 
- HDSPM_TCO2_set_input_LSB
 
- HDSPM_TCO2_set_input_MSB
 
- HDSPM_TCO2_set_jam_sync
 
- HDSPM_TCO2_set_num_drop_frames_LSB
 
- HDSPM_TCO2_set_num_drop_frames_MSB
 
- HDSPM_TCO2_set_pull_down
 
- HDSPM_TCO2_set_pull_up
 
- HDSPM_TCO2_set_term_75R
 
- HDSPM_TCO_FRAME_RATE
 
- HDSPM_TCO_LOCK_CHECK
 
- HDSPM_TCO_LTC_FRAMES
 
- HDSPM_TCO_PULL
 
- HDSPM_TCO_SAMPLE_RATE
 
- HDSPM_TCO_SYNC_SOURCE
 
- HDSPM_TCO_VIDEO_INPUT_FORMAT
 
- HDSPM_TCO_WCK_CONVERSION
 
- HDSPM_TCO_WORD_TERM
 
- HDSPM_TDI
 
- HDSPM_TMS
 
- HDSPM_TOGGLE_SETTING
 
- HDSPM_TX_64ch
 
- HDSPM_WCK48
 
- HDSPM_WR_SETTINGS
 
- HDSPM_WR_TCO
 
- HDSPM_audioIRQPending
 
- HDSPM_bit2freq
 
- HDSPM_c0Master
 
- HDSPM_c0_AD_GAIN0
 
- HDSPM_c0_AD_GAIN1
 
- HDSPM_c0_AEB1
 
- HDSPM_c0_AEB2
 
- HDSPM_c0_DA_GAIN0
 
- HDSPM_c0_DA_GAIN1
 
- HDSPM_c0_Input0
 
- HDSPM_c0_Input1
 
- HDSPM_c0_LineOut
 
- HDSPM_c0_PH_GAIN0
 
- HDSPM_c0_PH_GAIN1
 
- HDSPM_c0_Pro
 
- HDSPM_c0_Spdif_Opt
 
- HDSPM_c0_Sym6db
 
- HDSPM_c0_SyncRef0
 
- HDSPM_c0_SyncRef1
 
- HDSPM_c0_SyncRef2
 
- HDSPM_c0_SyncRef3
 
- HDSPM_c0_SyncRefMask
 
- HDSPM_c0_Wck48
 
- HDSPM_c0_clr_tms
 
- HDSPM_clr_tms
 
- HDSPM_control2Reg
 
- HDSPM_controlRegister
 
- HDSPM_eeprom_wr
 
- HDSPM_freqReg
 
- HDSPM_inputBufferAddress
 
- HDSPM_inputEnableBase
 
- HDSPM_interruptConfirmation
 
- HDSPM_madiFreq0
 
- HDSPM_madiFreq1
 
- HDSPM_madiFreq128
 
- HDSPM_madiFreq176_4
 
- HDSPM_madiFreq192
 
- HDSPM_madiFreq2
 
- HDSPM_madiFreq3
 
- HDSPM_madiFreq32
 
- HDSPM_madiFreq44_1
 
- HDSPM_madiFreq48
 
- HDSPM_madiFreq64
 
- HDSPM_madiFreq88_2
 
- HDSPM_madiFreq96
 
- HDSPM_madiFreqMask
 
- HDSPM_madiLock
 
- HDSPM_madiSync
 
- HDSPM_midi0IRQPending
 
- HDSPM_midi1IRQPending
 
- HDSPM_midi2IRQPending
 
- HDSPM_midi2IRQPendingAES
 
- HDSPM_midi3IRQPending
 
- HDSPM_midiDataIn0
 
- HDSPM_midiDataIn1
 
- HDSPM_midiDataIn2
 
- HDSPM_midiDataIn3
 
- HDSPM_midiDataOut0
 
- HDSPM_midiDataOut1
 
- HDSPM_midiDataOut2
 
- HDSPM_midiStatusIn0
 
- HDSPM_midiStatusIn1
 
- HDSPM_midiStatusIn2
 
- HDSPM_midiStatusIn3
 
- HDSPM_midiStatusOut0
 
- HDSPM_midiStatusOut1
 
- HDSPM_midiStatusOut2
 
- HDSPM_outputBufferAddress
 
- HDSPM_outputEnableBase
 
- HDSPM_pageAddressBufferIn
 
- HDSPM_pageAddressBufferOut
 
- HDSPM_s2_AEBI_D
 
- HDSPM_s2_AEBO_D
 
- HDSPM_s2_tco_detect
 
- HDSPM_status1_F_0
 
- HDSPM_status1_F_1
 
- HDSPM_status1_F_2
 
- HDSPM_status1_F_3
 
- HDSPM_status1_freqMask
 
- HDSPM_statusRegister
 
- HDSPM_statusRegister2
 
- HDSPM_syncInLock
 
- HDSPM_syncInSync
 
- HDSPM_taxi_reset
 
- HDSPM_tcoLockAes
 
- HDSPM_tcoLockMadi
 
- HDSPM_tcoSync
 
- HDSPM_tco_detect
 
- HDSPM_timecodeRegister
 
- HDSPM_version0
 
- HDSPM_version1
 
- HDSPM_version2
 
- HDSPM_wcFreq128
 
- HDSPM_wcFreq176_4
 
- HDSPM_wcFreq192
 
- HDSPM_wcFreq32
 
- HDSPM_wcFreq44_1
 
- HDSPM_wcFreq48
 
- HDSPM_wcFreq64
 
- HDSPM_wcFreq88_2
 
- HDSPM_wcFreq96
 
- HDSPM_wcFreqMask
 
- HDSPM_wcLock
 
- HDSPM_wcSync
 
- HDSPM_wc_freq0
 
- HDSPM_wc_freq1
 
- HDSPM_wc_freq2
 
- HDSPM_wc_freq3
 
- HDSPM_wc_valid
 
- HDSPM_wclk_sel
 
- HDSP_9632_metersBase
 
- HDSP_9652_ENABLE_MIXER
 
- HDSP_9652_peakBase
 
- HDSP_9652_rmsBase
 
- HDSP_ADATSYNC_SYNC_CHECK
 
- HDSP_ADAT_SYNC_CHECK
 
- HDSP_ADGain0
 
- HDSP_ADGain1
 
- HDSP_ADGainLowGain
 
- HDSP_ADGainMask
 
- HDSP_ADGainMinus10dBV
 
- HDSP_ADGainPlus4dBu
 
- HDSP_AD_GAIN
 
- HDSP_AEBI
 
- HDSP_AEBO
 
- HDSP_AUTOSYNC_FROM_ADAT1
 
- HDSP_AUTOSYNC_FROM_ADAT2
 
- HDSP_AUTOSYNC_FROM_ADAT3
 
- HDSP_AUTOSYNC_FROM_ADAT_SYNC
 
- HDSP_AUTOSYNC_FROM_NONE
 
- HDSP_AUTOSYNC_FROM_SPDIF
 
- HDSP_AUTOSYNC_FROM_WORD
 
- HDSP_AUTOSYNC_REF
 
- HDSP_AUTOSYNC_SAMPLE_RATE
 
- HDSP_AnalogExtensionBoard
 
- HDSP_AudioInterruptEnable
 
- HDSP_BIGENDIAN_MODE
 
- HDSP_BufferID
 
- HDSP_BufferPositionMask
 
- HDSP_CHANNEL_BUFFER_BYTES
 
- HDSP_CHANNEL_BUFFER_SAMPLES
 
- HDSP_CLOCK_SOURCE
 
- HDSP_CLOCK_SOURCE_AUTOSYNC
 
- HDSP_CLOCK_SOURCE_INTERNAL_128KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_192KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_32KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_48KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_64KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ
 
- HDSP_CLOCK_SOURCE_INTERNAL_96KHZ
 
- HDSP_CONFIG_MODE_0
 
- HDSP_CONFIG_MODE_1
 
- HDSP_CYCLIC_MODE
 
- HDSP_ClockModeMaster
 
- HDSP_ConfigError
 
- HDSP_DAGain0
 
- HDSP_DAGain1
 
- HDSP_DAGainHighGain
 
- HDSP_DAGainMask
 
- HDSP_DAGainMinus10dBV
 
- HDSP_DAGainPlus4dBu
 
- HDSP_DA_GAIN
 
- HDSP_DDS_OFFSET
 
- HDSP_DMA_AREA_BYTES
 
- HDSP_DMA_AREA_KILOBYTES
 
- HDSP_DllError
 
- HDSP_DoubleSpeed
 
- HDSP_DoubleSpeedStatus
 
- HDSP_FIRMWARE_SIZE
 
- HDSP_FirmwareCached
 
- HDSP_FirmwareLoaded
 
- HDSP_Frequency0
 
- HDSP_Frequency1
 
- HDSP_Frequency128KHz
 
- HDSP_Frequency176_4KHz
 
- HDSP_Frequency192KHz
 
- HDSP_Frequency32KHz
 
- HDSP_Frequency44_1KHz
 
- HDSP_Frequency48KHz
 
- HDSP_Frequency64KHz
 
- HDSP_Frequency88_2KHz
 
- HDSP_Frequency96KHz
 
- HDSP_FrequencyMask
 
- HDSP_IO_EXTENT
 
- HDSP_IO_Type
 
- HDSP_InitializationComplete
 
- HDSP_JTAG
 
- HDSP_LONG_WAIT
 
- HDSP_Latency0
 
- HDSP_Latency1
 
- HDSP_Latency2
 
- HDSP_LatencyMask
 
- HDSP_LineOut
 
- HDSP_Lock0
 
- HDSP_Lock1
 
- HDSP_Lock2
 
- HDSP_MATRIX_MIXER_SIZE
 
- HDSP_MAX_CHANNELS
 
- HDSP_MAX_DS_CHANNELS
 
- HDSP_MAX_QS_CHANNELS
 
- HDSP_MIXER
 
- HDSP_Midi0InterruptEnable
 
- HDSP_Midi1InterruptEnable
 
- HDSP_PHONE_GAIN
 
- HDSP_PRECISE_POINTER
 
- HDSP_PREF_SYNC_REF
 
- HDSP_PROGRAM
 
- HDSP_PWDN
 
- HDSP_PhoneGain0
 
- HDSP_PhoneGain0dB
 
- HDSP_PhoneGain1
 
- HDSP_PhoneGainMask
 
- HDSP_PhoneGainMinus12dB
 
- HDSP_PhoneGainMinus6dB
 
- HDSP_QuadSpeed
 
- HDSP_RD_MULTIPLE
 
- HDSP_RPM_Bypass
 
- HDSP_RPM_Disconnect
 
- HDSP_RPM_Inp12
 
- HDSP_RPM_Inp12_Line_0dB
 
- HDSP_RPM_Inp12_Line_n6dB
 
- HDSP_RPM_Inp12_Phon_0dB
 
- HDSP_RPM_Inp12_Phon_6dB
 
- HDSP_RPM_Inp12_Phon_n6dB
 
- HDSP_RPM_Inp34
 
- HDSP_RPM_Inp34_Line_0dB
 
- HDSP_RPM_Inp34_Line_n6dB
 
- HDSP_RPM_Inp34_Phon_0dB
 
- HDSP_RPM_Inp34_Phon_6dB
 
- HDSP_RPM_Inp34_Phon_n6dB
 
- HDSP_S200
 
- HDSP_S300
 
- HDSP_SHORT_WAIT
 
- HDSP_SPDIFEmphasis
 
- HDSP_SPDIFErrorFlag
 
- HDSP_SPDIFIN_AES
 
- HDSP_SPDIFIN_COAXIAL
 
- HDSP_SPDIFIN_INTERNAL
 
- HDSP_SPDIFIN_OPTICAL
 
- HDSP_SPDIFInputADAT1
 
- HDSP_SPDIFInputAES
 
- HDSP_SPDIFInputCdrom
 
- HDSP_SPDIFInputCoaxial
 
- HDSP_SPDIFInputMask
 
- HDSP_SPDIFInputSelect0
 
- HDSP_SPDIFInputSelect1
 
- HDSP_SPDIFNonAudio
 
- HDSP_SPDIFOpticalOut
 
- HDSP_SPDIFProfessional
 
- HDSP_SPDIFSync
 
- HDSP_SPDIF_IN
 
- HDSP_SPDIF_SAMPLE_RATE
 
- HDSP_SPDIF_SYNC_CHECK
 
- HDSP_SYNC_CHECK_LOCK
 
- HDSP_SYNC_CHECK_NO_LOCK
 
- HDSP_SYNC_CHECK_SYNC
 
- HDSP_SYNC_FROM_ADAT1
 
- HDSP_SYNC_FROM_ADAT2
 
- HDSP_SYNC_FROM_ADAT3
 
- HDSP_SYNC_FROM_ADAT_SYNC
 
- HDSP_SYNC_FROM_SPDIF
 
- HDSP_SYNC_FROM_WORD
 
- HDSP_SYSTEM_CLOCK_MODE
 
- HDSP_SYSTEM_SAMPLE_RATE
 
- HDSP_S_LOAD
 
- HDSP_S_PROGRAM
 
- HDSP_SelSyncRef0
 
- HDSP_SelSyncRef1
 
- HDSP_SelSyncRef2
 
- HDSP_SelSyncRefMask
 
- HDSP_SelSyncRef_ADAT1
 
- HDSP_SelSyncRef_ADAT2
 
- HDSP_SelSyncRef_ADAT3
 
- HDSP_SelSyncRef_ADAT_SYNC
 
- HDSP_SelSyncRef_SPDIF
 
- HDSP_SelSyncRef_WORD
 
- HDSP_Start
 
- HDSP_Sync0
 
- HDSP_Sync1
 
- HDSP_Sync2
 
- HDSP_SyncRef0
 
- HDSP_SyncRef1
 
- HDSP_SyncRef2
 
- HDSP_SyncRefMask
 
- HDSP_SyncRef_ADAT1
 
- HDSP_SyncRef_ADAT2
 
- HDSP_SyncRef_ADAT3
 
- HDSP_SyncRef_ADAT_SYNC
 
- HDSP_SyncRef_SPDIF
 
- HDSP_SyncRef_WORD
 
- HDSP_TCK
 
- HDSP_TDI
 
- HDSP_TDO
 
- HDSP_TMS
 
- HDSP_TOGGLE_SETTING
 
- HDSP_TimecodeLock
 
- HDSP_TimecodeSync
 
- HDSP_USE_MIDI_TASKLET
 
- HDSP_VERSION_BIT
 
- HDSP_WC_SYNC_CHECK
 
- HDSP_XLRBreakoutCable
 
- HDSP_audioIRQPending
 
- HDSP_control2Reg
 
- HDSP_controlRegister
 
- HDSP_fifoData
 
- HDSP_fifoStatus
 
- HDSP_freqReg
 
- HDSP_inp_freq0
 
- HDSP_inp_freq1
 
- HDSP_inp_freq2
 
- HDSP_inputBufferAddress
 
- HDSP_inputEnable
 
- HDSP_inputPeakLevel
 
- HDSP_inputRmsLevel
 
- HDSP_interruptConfirmation
 
- HDSP_midi0IRQPending
 
- HDSP_midi1IRQPending
 
- HDSP_midiDataIn0
 
- HDSP_midiDataIn1
 
- HDSP_midiDataOut0
 
- HDSP_midiDataOut1
 
- HDSP_midiStatusIn0
 
- HDSP_midiStatusIn1
 
- HDSP_midiStatusOut0
 
- HDSP_midiStatusOut1
 
- HDSP_outputBufferAddress
 
- HDSP_outputEnable
 
- HDSP_outputPeakLevel
 
- HDSP_playbackPeakLevel
 
- HDSP_playbackRmsLevel
 
- HDSP_resetPointer
 
- HDSP_spdifFrequency0
 
- HDSP_spdifFrequency1
 
- HDSP_spdifFrequency128KHz
 
- HDSP_spdifFrequency176_4KHz
 
- HDSP_spdifFrequency192KHz
 
- HDSP_spdifFrequency2
 
- HDSP_spdifFrequency3
 
- HDSP_spdifFrequency32KHz
 
- HDSP_spdifFrequency44_1KHz
 
- HDSP_spdifFrequency48KHz
 
- HDSP_spdifFrequency64KHz
 
- HDSP_spdifFrequency88_2KHz
 
- HDSP_spdifFrequency96KHz
 
- HDSP_spdifFrequencyMask
 
- HDSP_spdifFrequencyMask_9632
 
- HDSP_status2Register
 
- HDSP_statusRegister
 
- HDSP_systemFrequency32
 
- HDSP_systemFrequency44_1
 
- HDSP_systemFrequency48
 
- HDSP_systemFrequency64
 
- HDSP_systemFrequency88_2
 
- HDSP_systemFrequency96
 
- HDSP_systemFrequencyMask
 
- HDSP_timecode
 
- HDSP_version0
 
- HDSP_version1
 
- HDSP_version2
 
- HDSP_wc_lock
 
- HDSP_wc_sync
 
- HDSP_wc_valid
 
- HDSPe_FLOAT_FORMAT
 
- HDSR
 
- HDTV_1080I
 
- HDTV_525P
 
- HDTV_625P
 
- HDTV_720P
 
- HDW
 
- HDWIDTH
 
- HDX_ACTIVE
 
- HD_1080I_INPUT_MODE
 
- HD_720P_INPUT_MODE
 
- HD_ADPT_FLTR_DI
 
- HD_ADPT_FLTR_EN
 
- HD_ADPT_FLTR_MODEA
 
- HD_ADPT_FLTR_MODEB
 
- HD_AUTO_CORR32_X1_TH_ADD_MIN_IDX
 
- HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX
 
- HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX
 
- HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX
 
- HD_AUTO_CORR32_X4_TH_ADD_MIN_IDX
 
- HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX
 
- HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX
 
- HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX
 
- HD_AUTO_CORR40_X4_TH_ADD_MIN_IDX
 
- HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX
 
- HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX
 
- HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX
 
- HD_B1_FLOW_CONTROL
 
- HD_B2_FLOW_CONTROL
 
- HD_BARKER_CORR_TH_ADD_MIN_IDX
 
- HD_BARKER_CORR_TH_ADD_MIN_INDEX
 
- HD_BARKER_CORR_TH_ADD_MIN_MRC_IDX
 
- HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX
 
- HD_BUSY_FLAG
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2
 
- HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX
 
- HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1
 
- HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2
 
- HD_CCK_NON_SQUARE_DET_SLOPE_INDEX
 
- HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1
 
- HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2
 
- HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX
 
- HD_CLEAR
 
- HD_CLOSE_ATCHANNEL
 
- HD_CLOSE_ATCHANNEL_ACK
 
- HD_CLOSE_B1CHANNEL
 
- HD_CLOSE_B1CHANNEL_ACK
 
- HD_CLOSE_B2CHANNEL
 
- HD_CLOSE_B2CHANNEL_ACK
 
- HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1
 
- HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2
 
- HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX
 
- HD_CRSR_SHIFT
 
- HD_CRSR_SHIFT_DISPLAY
 
- HD_CRSR_SHIFT_DISPLAY_RIGHT
 
- HD_DAC_SWAP_DI
 
- HD_DAC_SWAP_EN
 
- HD_DEVICE_INIT_ACK
 
- HD_DEVICE_INIT_OK
 
- HD_DISPCTRL
 
- HD_DISPCTRL_CURSOR_BLINK
 
- HD_DISPCTRL_CURSOR_ON
 
- HD_DISPCTRL_ON
 
- HD_ENTRYMODE
 
- HD_ENTRYMODE_INCREMENT
 
- HD_ENTRYMODE_SHIFT
 
- HD_FC_BKOFF_OK
 
- HD_FC_EN
 
- HD_FUNCSET
 
- HD_FUNCSET_2_LINES
 
- HD_FUNCSET_8BIT
 
- HD_FUNCSET_FONT_5X10
 
- HD_GAMMA_CURVE_A
 
- HD_GAMMA_CURVE_B
 
- HD_GAMMA_DI
 
- HD_GAMMA_EN
 
- HD_HOME
 
- HD_INA_NON_SQUARE_DET_CCK_DATA_V1
 
- HD_INA_NON_SQUARE_DET_CCK_DATA_V2
 
- HD_INA_NON_SQUARE_DET_CCK_INDEX
 
- HD_INA_NON_SQUARE_DET_OFDM_DATA_V1
 
- HD_INA_NON_SQUARE_DET_OFDM_DATA_V2
 
- HD_INA_NON_SQUARE_DET_OFDM_INDEX
 
- HD_MAJOR
 
- HD_MEDIA
 
- HD_MIN_ENERGY_CCK_DET_IDX
 
- HD_MIN_ENERGY_CCK_DET_INDEX
 
- HD_MIN_ENERGY_OFDM_DET_IDX
 
- HD_MIN_ENERGY_OFDM_DET_INDEX
 
- HD_MODE_LEN
 
- HD_MODE_POS
 
- HD_OFDM_ENERGY_TH_IN_IDX
 
- HD_OFDM_ENERGY_TH_IN_INDEX
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2
 
- HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2
 
- HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX
 
- HD_OPEN_ATCHANNEL
 
- HD_OPEN_ATCHANNEL_ACK
 
- HD_OPEN_B1CHANNEL
 
- HD_OPEN_B1CHANNEL_ACK
 
- HD_OPEN_B2CHANNEL
 
- HD_OPEN_B2CHANNEL_ACK
 
- HD_PBPR_SYNC_DI
 
- HD_PBPR_SYNC_EN
 
- HD_PRPB_SYNC_DI
 
- HD_PRPB_SYNC_EN
 
- HD_PVR_PRODUCT_ID
 
- HD_PVR_PRODUCT_ID1
 
- HD_PVR_PRODUCT_ID2
 
- HD_PVR_PRODUCT_ID3
 
- HD_PVR_PRODUCT_ID4
 
- HD_PVR_VENDOR_ID
 
- HD_READ
 
- HD_READY_SEND_ATDATA
 
- HD_READ_ATMESSAGE
 
- HD_RECEIVEATDATA_ACK
 
- HD_RESERVED
 
- HD_RESET_INTERRUPT_PIPE
 
- HD_RESET_INTERRUPT_PIPE_ACK
 
- HD_RGB_INPUT_DI
 
- HD_RGB_INPUT_EN
 
- HD_SET_CGRAM
 
- HD_SET_DDRAM
 
- HD_SUSPEND_END
 
- HD_TABLE_SIZE
 
- HD_TBL_SIZE
 
- HD_WRITE
 
- HD_WRITE_ATMESSAGE
 
- HE155MM
 
- HE155SM
 
- HE622MM
 
- HE622SM
 
- HEAD
 
- HEADER
 
- HEADERDIGEST
 
- HEADERLEN
 
- HEADER_802_2_SIZE
 
- HEADER_ADDRESS
 
- HEADER_AGENT_DISPATCH
 
- HEADER_ARCH
 
- HEADER_AUXTRACE
 
- HEADER_BARRIER
 
- HEADER_BDCOUNT_MASK
 
- HEADER_BDCOUNT_MAX
 
- HEADER_BDCOUNT_SHIFT
 
- HEADER_BOTH
 
- HEADER_BPF_BTF
 
- HEADER_BPF_PROG_INFO
 
- HEADER_BRANCH_STACK
 
- HEADER_BUILD_ID
 
- HEADER_CACHE
 
- HEADER_CLOCKID
 
- HEADER_CMDLINE
 
- HEADER_CNT_EN
 
- HEADER_COMPRESSED
 
- HEADER_CONTROL
 
- HEADER_COPY_SIZE
 
- HEADER_CPUDESC
 
- HEADER_CPUID
 
- HEADER_CPU_TOPOLOGY
 
- HEADER_DATA_LENGTH
 
- HEADER_DESCRIPTOR
 
- HEADER_DESTINATION
 
- HEADER_DESTINATION_IS_BROADCAST
 
- HEADER_DIR_FORMAT
 
- HEADER_ENABLE
 
- HEADER_ENDPKT_MASK
 
- HEADER_ENDPKT_SHIFT
 
- HEADER_ETHERNET_II_802_3_SIZE
 
- HEADER_EVENT_DESC
 
- HEADER_EXTENDED_TCODE
 
- HEADER_FEAT_BITS
 
- HEADER_FIRST_FEATURE
 
- HEADER_FLAGS_MASK
 
- HEADER_FLAGS_SHIFT
 
- HEADER_FMT_16BITS
 
- HEADER_FMT_24BITS
 
- HEADER_FMT_BASE
 
- HEADER_FMT_BASE_FLOAT
 
- HEADER_FMT_BASE_LIN
 
- HEADER_FMT_INTEL
 
- HEADER_FMT_MONO
 
- HEADER_FMT_UPTO11
 
- HEADER_FMT_UPTO32
 
- HEADER_GET_DATA_LENGTH
 
- HEADER_GET_DESTINATION
 
- HEADER_GET_EXTENDED_TCODE
 
- HEADER_GET_OFFSET_HIGH
 
- HEADER_GET_RCODE
 
- HEADER_GET_SOURCE
 
- HEADER_GET_TCODE
 
- HEADER_GET_TLABEL
 
- HEADER_GROUP_DESC
 
- HEADER_HAS_FILTER
 
- HEADER_HOSTNAME
 
- HEADER_ID0
 
- HEADER_ID1
 
- HEADER_IS_ZERO
 
- HEADER_LAST_FEATURE
 
- HEADER_LDR_FORMAT_GZIP
 
- HEADER_LDR_FORMAT_RAW
 
- HEADER_LEN
 
- HEADER_LENGTH
 
- HEADER_LINE_NR
 
- HEADER_LOW
 
- HEADER_MAGIC
 
- HEADER_MAGIC_OFFSET
 
- HEADER_MAGIC_SIZE
 
- HEADER_MAP_OFFSET
 
- HEADER_MEM_TOPOLOGY
 
- HEADER_MODE
 
- HEADER_NRCPUS
 
- HEADER_NUMA_TOPOLOGY
 
- HEADER_OFFSET_HIGH
 
- HEADER_OPAQUE_MASK
 
- HEADER_OPAQUE_SHIFT
 
- HEADER_OSRELEASE
 
- HEADER_PMU_MAPPINGS
 
- HEADER_PRI
 
- HEADER_RCODE
 
- HEADER_REPORT_10_FINGER
 
- HEADER_RESERVED
 
- HEADER_RETRY
 
- HEADER_SAMPLE_TIME
 
- HEADER_SIZE
 
- HEADER_SIZE_MAX
 
- HEADER_SIZE_MIN
 
- HEADER_SNAP_SIZE
 
- HEADER_SOURCE
 
- HEADER_SPAN
 
- HEADER_SPAN_LOW
 
- HEADER_STARTPKT_MASK
 
- HEADER_STARTPKT_SHIFT
 
- HEADER_STAT
 
- HEADER_TCODE
 
- HEADER_TLABEL
 
- HEADER_TOGGLE_MASK
 
- HEADER_TOGGLE_SHIFT
 
- HEADER_TOTAL_MEM
 
- HEADER_TRACING_DATA
 
- HEADER_TSTAMP_MASK
 
- HEADER_TYPE
 
- HEADER_TYPE1
 
- HEADER_TYPE2
 
- HEADER_TYPE3
 
- HEADER_TYPE4
 
- HEADER_VERSION
 
- HEADER_VLAN_SIZE
 
- HEADER__DEVICE_TYPE_MASK
 
- HEADER__DEVICE_TYPE__MASK
 
- HEADER__DEVICE_TYPE__SHIFT
 
- HEADER__HEADER_TYPE_MASK
 
- HEADER__HEADER_TYPE__MASK
 
- HEADER__HEADER_TYPE__SHIFT
 
- HEADLESS
 
- HEADPHONE_OUT
 
- HEADROOM
 
- HEADS
 
- HEADSET_SARADC_THD
 
- HEADSET_STATUS
 
- HEAD_A
 
- HEAD_ADDR
 
- HEAD_B
 
- HEAD_CRC
 
- HEAD_CRT
 
- HEAD_DBG
 
- HEAD_END
 
- HEAD_MSG
 
- HEAD_OF_Q
 
- HEAD_OF_QUEUE_TAG
 
- HEAD_PANEL
 
- HEAD_SET_IN
 
- HEAD_SIZE
 
- HEAD_SYMBOLS
 
- HEAD_TEXT
 
- HEAD_TEXT_SECTION
 
- HEAD_UF_INT
 
- HEAD_WARN
 
- HEAD_WRAP_COUNT
 
- HEAD_WRAP_ONE
 
- HEALTH_BUFFER_SIZE
 
- HEALTH_DESC_PARAM_EOL_INFO
 
- HEALTH_DESC_PARAM_LEN
 
- HEALTH_DESC_PARAM_LIFE_TIME_EST_A
 
- HEALTH_DESC_PARAM_LIFE_TIME_EST_B
 
- HEALTH_DESC_PARAM_TYPE
 
- HEALTH_REPORT_EVENT_ID
 
- HEAP_SIZE
 
- HEARTBEAT_2ND_RANGE_END
 
- HEARTBEAT_2ND_RANGE_START
 
- HEARTBEAT_BUFFER_SIZE
 
- HEARTBEAT_DISABLE
 
- HEARTBEAT_INVERTED
 
- HEARTBEAT_LEN
 
- HEARTBEAT_SAMPLE_INTERVAL
 
- HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH
 
- HEARTBEAT_SYSTEM_INODE
 
- HEATHROW_AUX_CNTL_REG
 
- HEATHROW_BRIGHTNESS_CNTL
 
- HEATHROW_CONTRAST_CNTL
 
- HEATHROW_FCR
 
- HEATHROW_FRONT_LIGHT
 
- HEATHROW_MBCR
 
- HEB
 
- HECC_BUS_ERROR
 
- HECC_CANAA
 
- HECC_CANBTC
 
- HECC_CANBTC_SAM
 
- HECC_CANES
 
- HECC_CANES_ACKE
 
- HECC_CANES_BE
 
- HECC_CANES_BO
 
- HECC_CANES_CCE
 
- HECC_CANES_CRCE
 
- HECC_CANES_EP
 
- HECC_CANES_EW
 
- HECC_CANES_FE
 
- HECC_CANES_FLAGS
 
- HECC_CANES_PDA
 
- HECC_CANES_SA1
 
- HECC_CANES_SE
 
- HECC_CANES_SMA
 
- HECC_CANGAM
 
- HECC_CANGIF0
 
- HECC_CANGIF1
 
- HECC_CANGIF_AAIF
 
- HECC_CANGIF_BOIF
 
- HECC_CANGIF_EPIF
 
- HECC_CANGIF_GMIF
 
- HECC_CANGIF_MAIF
 
- HECC_CANGIF_MBOX_MASK
 
- HECC_CANGIF_RMLIF
 
- HECC_CANGIF_TCOIF
 
- HECC_CANGIF_WDIF
 
- HECC_CANGIF_WLIF
 
- HECC_CANGIF_WUIF
 
- HECC_CANGIM
 
- HECC_CANGIM_DEF_MASK
 
- HECC_CANGIM_I0EN
 
- HECC_CANGIM_I1EN
 
- HECC_CANGIM_SIL
 
- HECC_CANID_MASK
 
- HECC_CANLNT
 
- HECC_CANMC
 
- HECC_CANMCF
 
- HECC_CANMCF_RTR
 
- HECC_CANMC_ABO
 
- HECC_CANMC_CCR
 
- HECC_CANMC_PDR
 
- HECC_CANMC_SCM
 
- HECC_CANMC_SRES
 
- HECC_CANMC_STM
 
- HECC_CANMD
 
- HECC_CANMDH
 
- HECC_CANMDL
 
- HECC_CANME
 
- HECC_CANMID
 
- HECC_CANMID_AAM
 
- HECC_CANMID_AME
 
- HECC_CANMID_IDE
 
- HECC_CANMIL
 
- HECC_CANMIM
 
- HECC_CANMOTS
 
- HECC_CANOPC
 
- HECC_CANREC
 
- HECC_CANRFP
 
- HECC_CANRIOC
 
- HECC_CANRIOCE
 
- HECC_CANRIOC_EN
 
- HECC_CANRML
 
- HECC_CANRMP
 
- HECC_CANTA
 
- HECC_CANTEC
 
- HECC_CANTIOC
 
- HECC_CANTIOCE
 
- HECC_CANTIOC_EN
 
- HECC_CANTOC
 
- HECC_CANTOS
 
- HECC_CANTRR
 
- HECC_CANTRS
 
- HECC_CCE_WAIT_COUNT
 
- HECC_MAX_MAILBOXES
 
- HECC_MAX_RX_MBOX
 
- HECC_MAX_TX_MBOX
 
- HECC_MB_TX_SHIFT
 
- HECC_MODULE_VERSION
 
- HECC_RX_FIRST_MBOX
 
- HECC_RX_LAST_MBOX
 
- HECC_SET_REG
 
- HECC_TX_MASK
 
- HECC_TX_MB_MASK
 
- HECC_TX_PRIO_MASK
 
- HECC_TX_PRIO_SHIFT
 
- HECMI_ERR
 
- HEC_ERROR_COUNT_OFF
 
- HEC_MIF_CFG_VAL
 
- HEC_PERIOD
 
- HEDSEL
 
- HEEP_CTRL_WRD_PCIEX_CTRL_REG
 
- HEEP_CTRL_WRD_PCIEX_DATA_REG
 
- HEIGHT
 
- HEIGHT_ALIGN
 
- HEIGHT_OFF
 
- HEIGHT_SHIFT
 
- HEINEKEN_A_PID_PREFIRM
 
- HEINEKEN_A_PID_PSTFIRM
 
- HEINEKEN_B_PID_PREFIRM
 
- HEINEKEN_B_PID_PSTFIRM
 
- HELENE_AUTO
 
- HELENE_BW_1_7
 
- HELENE_BW_6
 
- HELENE_BW_7
 
- HELENE_BW_8
 
- HELENE_OFFSET
 
- HELIOS_JEDEC_ID
 
- HELPER_ACK_PACKET_FORMAT
 
- HELPER_CMD_ENTRY_POINT
 
- HELPER_CMD_PACKET_FORMAT
 
- HELPER_FW_LOAD_CHUNK_SZ
 
- HELPER_NAME
 
- HELPER_RETRY_REQUESTED
 
- HELP_FORMAT_INFO
 
- HELP_FORMAT_MAN
 
- HELP_FORMAT_NONE
 
- HELP_FORMAT_WEB
 
- HELP_PAD
 
- HELP_SPEC_ATTACH_FLAGS
 
- HELP_SPEC_ATTACH_TYPES
 
- HELP_SPEC_MAP
 
- HELP_SPEC_OPTIONS
 
- HELP_SPEC_PROGRAM
 
- HELP_STRING_UNINITIALIZED
 
- HEMA_PAL_ID
 
- HEMA_VERSION_ID
 
- HEM_TYPE_CQC
 
- HEM_TYPE_CQC_TIMER
 
- HEM_TYPE_CQE
 
- HEM_TYPE_IDX
 
- HEM_TYPE_IRRL
 
- HEM_TYPE_MTPT
 
- HEM_TYPE_MTT
 
- HEM_TYPE_QPC
 
- HEM_TYPE_QPC_TIMER
 
- HEM_TYPE_SCCC
 
- HEM_TYPE_SRQC
 
- HEM_TYPE_SRQWQE
 
- HEM_TYPE_TRRL
 
- HEND
 
- HEND_IP_PHONE_MODE
 
- HEND_WIFI_PHONE_MODE
 
- HENQNUM_LEN
 
- HENQNUM_POS
 
- HEQ_INSTR
 
- HERMES_16BIT_REGSPACING
 
- HERMES_32BIT_REGSPACING
 
- HERMES_802_11_OFFSET
 
- HERMES_802_2_OFFSET
 
- HERMES_802_3_OFFSET
 
- HERMES_ALLOCFID
 
- HERMES_ALLOC_LEN_MAX
 
- HERMES_ALLOC_LEN_MIN
 
- HERMES_AUTH_OPEN
 
- HERMES_AUTH_SHARED_KEY
 
- HERMES_AUXDATA
 
- HERMES_AUXOFFSET
 
- HERMES_AUXPAGE
 
- HERMES_AUX_DISABLE
 
- HERMES_AUX_DISABLED
 
- HERMES_AUX_ENABLE
 
- HERMES_AUX_ENABLED
 
- HERMES_AUX_PW0
 
- HERMES_AUX_PW1
 
- HERMES_AUX_PW2
 
- HERMES_BAP_BUSY_TIMEOUT
 
- HERMES_BAP_DATALEN_MAX
 
- HERMES_BAP_OFFSET_MAX
 
- HERMES_BYTES_TO_RECLEN
 
- HERMES_CHINFORESULT_MAX
 
- HERMES_CMD
 
- HERMES_CMD_ACCESS
 
- HERMES_CMD_AINFO
 
- HERMES_CMD_ALLOC
 
- HERMES_CMD_BUSY
 
- HERMES_CMD_CMDCODE
 
- HERMES_CMD_DIAG
 
- HERMES_CMD_DISABLE
 
- HERMES_CMD_DOWNLD
 
- HERMES_CMD_ENABLE
 
- HERMES_CMD_INIT
 
- HERMES_CMD_INQUIRE
 
- HERMES_CMD_MACPORT
 
- HERMES_CMD_NOTIFY
 
- HERMES_CMD_PROGMODE
 
- HERMES_CMD_READMIF
 
- HERMES_CMD_RECL
 
- HERMES_CMD_TEST
 
- HERMES_CMD_TX
 
- HERMES_CMD_WRITE
 
- HERMES_CMD_WRITEMIF
 
- HERMES_CONTROL
 
- HERMES_DATA0
 
- HERMES_DATA1
 
- HERMES_DEBUG
 
- HERMES_DESCRIPTOR_OFFSET
 
- HERMES_EVACK
 
- HERMES_EVSTAT
 
- HERMES_EV_ALLOC
 
- HERMES_EV_CMD
 
- HERMES_EV_DTIM
 
- HERMES_EV_INFDROP
 
- HERMES_EV_INFO
 
- HERMES_EV_RX
 
- HERMES_EV_TICK
 
- HERMES_EV_TX
 
- HERMES_EV_TXEXC
 
- HERMES_EV_WTERR
 
- HERMES_HOSTSCAN_SYMBOL_5SEC
 
- HERMES_HOSTSCAN_SYMBOL_BCAST
 
- HERMES_HOSTSCAN_SYMBOL_ONCE
 
- HERMES_HOSTSCAN_SYMBOL_PASSIVE
 
- HERMES_INFOFID
 
- HERMES_INQ_CHANNELINFO
 
- HERMES_INQ_HOSTSCAN
 
- HERMES_INQ_HOSTSCAN_SYMBOL
 
- HERMES_INQ_LINKSTATUS
 
- HERMES_INQ_SCAN
 
- HERMES_INQ_SEC_STAT_AGERE
 
- HERMES_INQ_TALLIES
 
- HERMES_INTEN
 
- HERMES_LINKSTATUS_AP_CHANGE
 
- HERMES_LINKSTATUS_AP_IN_RANGE
 
- HERMES_LINKSTATUS_AP_OUT_OF_RANGE
 
- HERMES_LINKSTATUS_ASSOC_FAILED
 
- HERMES_LINKSTATUS_CONNECTED
 
- HERMES_LINKSTATUS_DISCONNECTED
 
- HERMES_LINKSTATUS_NOT_CONNECTED
 
- HERMES_LTV_LEN_MAX
 
- HERMES_MAGIC
 
- HERMES_MAX_MULTICAST
 
- HERMES_MIC_KEY_ID_SHIFT
 
- HERMES_NUMPORTS_MAX
 
- HERMES_OFFSET0
 
- HERMES_OFFSET1
 
- HERMES_OFFSET_BUSY
 
- HERMES_OFFSET_DATAOFF
 
- HERMES_OFFSET_ERR
 
- HERMES_PARAM0
 
- HERMES_PARAM1
 
- HERMES_PARAM2
 
- HERMES_PCI_COR
 
- HERMES_PCI_COR_BUSYT
 
- HERMES_PCI_COR_MASK
 
- HERMES_PCI_COR_OFFT
 
- HERMES_PCI_COR_ONT
 
- HERMES_PDA_LEN_MAX
 
- HERMES_PDA_RECS_MAX
 
- HERMES_PDR_LEN_MAX
 
- HERMES_PORTID_MAX
 
- HERMES_PROGRAM_DISABLE
 
- HERMES_PROGRAM_ENABLE_NON_VOLATILE
 
- HERMES_PROGRAM_ENABLE_VOLATILE
 
- HERMES_PROGRAM_NON_VOLATILE
 
- HERMES_READ_RECORD
 
- HERMES_RECLEN_TO_BYTES
 
- HERMES_RESP0
 
- HERMES_RESP1
 
- HERMES_RESP2
 
- HERMES_RID_AUTHENTICATIONALGORITHMS
 
- HERMES_RID_BUILDSEQ
 
- HERMES_RID_CCAMODE
 
- HERMES_RID_CFIACTRANGES
 
- HERMES_RID_CFIACTRANGES2
 
- HERMES_RID_CFISUPRANGE
 
- HERMES_RID_CFPOLLABLE
 
- HERMES_RID_CHANNELLIST
 
- HERMES_RID_CIS
 
- HERMES_RID_CNFADDDEFAULTTKIPKEY_AGERE
 
- HERMES_RID_CNFADDMAPPEDTKIPKEY_AGERE
 
- HERMES_RID_CNFALTRETRYCOUNT
 
- HERMES_RID_CNFAPPCFINFO
 
- HERMES_RID_CNFAUTHENTICATESTATION
 
- HERMES_RID_CNFAUTHENTICATION
 
- HERMES_RID_CNFAUTHENTICATIONRSPTO
 
- HERMES_RID_CNFAUTHENTICATION_AGERE
 
- HERMES_RID_CNFBASICRATES
 
- HERMES_RID_CNFBASICRATES_SYMBOL
 
- HERMES_RID_CNFBEACONINT
 
- HERMES_RID_CNFCACHEDPMKADDRESS
 
- HERMES_RID_CNFCHANNELINFOREQUEST
 
- HERMES_RID_CNFCREATEIBSS
 
- HERMES_RID_CNFDEFAULTKEY0
 
- HERMES_RID_CNFDEFAULTKEY1
 
- HERMES_RID_CNFDEFAULTKEY2
 
- HERMES_RID_CNFDEFAULTKEY3
 
- HERMES_RID_CNFDESIREDSSID
 
- HERMES_RID_CNFDISASSOCIATE
 
- HERMES_RID_CNFDROPUNENCRYPTED
 
- HERMES_RID_CNFENHSECURITY
 
- HERMES_RID_CNFEXCLUDELONGPREAMBLE
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD0
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD1
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD2
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD3
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD4
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD5
 
- HERMES_RID_CNFFRAGMENTATIONTHRESHOLD6
 
- HERMES_RID_CNFGROUPADDRESSES
 
- HERMES_RID_CNFHOSTAUTHENTICATION
 
- HERMES_RID_CNFHOSTSCAN
 
- HERMES_RID_CNFHOSTSCAN_SYMBOL
 
- HERMES_RID_CNFJOINREQUEST
 
- HERMES_RID_CNFKEYLENGTH_SYMBOL
 
- HERMES_RID_CNFMANDATORYBSSID_SYMBOL
 
- HERMES_RID_CNFMAXASSOCSTA
 
- HERMES_RID_CNFMAXDATALEN
 
- HERMES_RID_CNFMAXSLEEPDURATION
 
- HERMES_RID_CNFMMLIFE
 
- HERMES_RID_CNFMULTICASTPMBUFFERING
 
- HERMES_RID_CNFMULTICASTRECEIVE
 
- HERMES_RID_CNFMWOROBUST_AGERE
 
- HERMES_RID_CNFOWNATIMWINDOW
 
- HERMES_RID_CNFOWNCHANNEL
 
- HERMES_RID_CNFOWNDTIMPERIOD
 
- HERMES_RID_CNFOWNMACADDR
 
- HERMES_RID_CNFOWNNAME
 
- HERMES_RID_CNFOWNSSID
 
- HERMES_RID_CNFPMENABLED
 
- HERMES_RID_CNFPMEPS
 
- HERMES_RID_CNFPMHOLDOVERDURATION
 
- HERMES_RID_CNFPORTTYPE
 
- HERMES_RID_CNFPREAMBLE_SYMBOL
 
- HERMES_RID_CNFPRIORITYQUSAGE
 
- HERMES_RID_CNFPROMISCUOUSMODE
 
- HERMES_RID_CNFRCVCRCERROR
 
- HERMES_RID_CNFREMDEFAULTTKIPKEY_AGERE
 
- HERMES_RID_CNFREMMAPPEDTKIPKEY_AGERE
 
- HERMES_RID_CNFREMOVEPMKADDRESS
 
- HERMES_RID_CNFROAMINGMODE
 
- HERMES_RID_CNFRTSTHRESHOLD
 
- HERMES_RID_CNFRTSTHRESHOLD0
 
- HERMES_RID_CNFRTSTHRESHOLD1
 
- HERMES_RID_CNFRTSTHRESHOLD2
 
- HERMES_RID_CNFRTSTHRESHOLD3
 
- HERMES_RID_CNFRTSTHRESHOLD4
 
- HERMES_RID_CNFRTSTHRESHOLD5
 
- HERMES_RID_CNFRTSTHRESHOLD6
 
- HERMES_RID_CNFSCANCHANNELS2GHZ
 
- HERMES_RID_CNFSCANREQUEST
 
- HERMES_RID_CNFSCANSSID_AGERE
 
- HERMES_RID_CNFSETWPAAUTHMGMTSUITE_AGERE
 
- HERMES_RID_CNFSETWPACAPABILITIES_AGERE
 
- HERMES_RID_CNFSHORTPREAMBLE
 
- HERMES_RID_CNFSTAPCFINFO
 
- HERMES_RID_CNFSUPPORTEDRATES
 
- HERMES_RID_CNFSYSTEMSCALE
 
- HERMES_RID_CNFTHIRTY2TALLY
 
- HERMES_RID_CNFTICKTIME
 
- HERMES_RID_CNFTIMCTRL
 
- HERMES_RID_CNFTXCONTROL
 
- HERMES_RID_CNFTXKEY_AGERE
 
- HERMES_RID_CNFTXRATECONTROL
 
- HERMES_RID_CNFWDSADDRESS
 
- HERMES_RID_CNFWDSADDRESS1
 
- HERMES_RID_CNFWDSADDRESS2
 
- HERMES_RID_CNFWDSADDRESS3
 
- HERMES_RID_CNFWDSADDRESS4
 
- HERMES_RID_CNFWDSADDRESS5
 
- HERMES_RID_CNFWDSADDRESS6
 
- HERMES_RID_CNFWEPDEFAULTKEYID
 
- HERMES_RID_CNFWEPENABLED_AGERE
 
- HERMES_RID_CNFWEPFLAGS_INTERSIL
 
- HERMES_RID_CNFWEPKEYMAPPINGTABLE
 
- HERMES_RID_CNFWEPKEYS_AGERE
 
- HERMES_RID_COMMSQUALITY
 
- HERMES_RID_CURRENTBEACONINTERVAL
 
- HERMES_RID_CURRENTBSSID
 
- HERMES_RID_CURRENTCHANNEL
 
- HERMES_RID_CURRENTPOWERSTATE
 
- HERMES_RID_CURRENTSCALETHRESHOLDS
 
- HERMES_RID_CURRENTSSID
 
- HERMES_RID_CURRENTTXRATE
 
- HERMES_RID_CURRENTTXRATE1
 
- HERMES_RID_CURRENTTXRATE2
 
- HERMES_RID_CURRENTTXRATE3
 
- HERMES_RID_CURRENTTXRATE4
 
- HERMES_RID_CURRENTTXRATE5
 
- HERMES_RID_CURRENTTXRATE6
 
- HERMES_RID_CURRENT_ASSOC_REQ_INFO
 
- HERMES_RID_CURRENT_ASSOC_RESP_INFO
 
- HERMES_RID_CURRENT_COUNTRY_INFO
 
- HERMES_RID_CURRENT_TKIP_IV
 
- HERMES_RID_CURRENT_WPA_IE
 
- HERMES_RID_DBMCOMMSQUALITY_INTERSIL
 
- HERMES_RID_DOWNLOADBUFFER
 
- HERMES_RID_FWID
 
- HERMES_RID_LONGRETRYLIMIT
 
- HERMES_RID_MAXLOADTIME
 
- HERMES_RID_MAXRECEIVELIFETIME
 
- HERMES_RID_MAXTRANSMITLIFETIME
 
- HERMES_RID_MFIACTRANGES
 
- HERMES_RID_MFISUPRANGE
 
- HERMES_RID_NICID
 
- HERMES_RID_NICSERNUM
 
- HERMES_RID_OWNMACADDR
 
- HERMES_RID_PHYTYPE
 
- HERMES_RID_PORTSTATUS
 
- HERMES_RID_PRIID
 
- HERMES_RID_PRISUPRANGE
 
- HERMES_RID_PRIVACYOPTIONIMPLEMENTED
 
- HERMES_RID_PROTOCOLRSPTIME
 
- HERMES_RID_REGULATORYDOMAINS
 
- HERMES_RID_SCANRESULTSTABLE
 
- HERMES_RID_SECONDARYVERSION_SYMBOL
 
- HERMES_RID_SHORTRETRYLIMIT
 
- HERMES_RID_STAID
 
- HERMES_RID_STASUPRANGE
 
- HERMES_RID_SUPPORTEDDATARATES
 
- HERMES_RID_TEMPTYPE
 
- HERMES_RID_TXQUEUEEMPTY
 
- HERMES_RXFID
 
- HERMES_RXSTAT_1042
 
- HERMES_RXSTAT_BADCRC
 
- HERMES_RXSTAT_ERR
 
- HERMES_RXSTAT_MACPORT
 
- HERMES_RXSTAT_MIC
 
- HERMES_RXSTAT_MIC_KEY_ID
 
- HERMES_RXSTAT_MSGTYPE
 
- HERMES_RXSTAT_PCF
 
- HERMES_RXSTAT_TUNNEL
 
- HERMES_RXSTAT_UNDECRYPTABLE
 
- HERMES_RXSTAT_WMP
 
- HERMES_SCANRESULT_MAX
 
- HERMES_SELECT0
 
- HERMES_SELECT1
 
- HERMES_STATUS
 
- HERMES_STATUS_CMDCODE
 
- HERMES_STATUS_RESULT
 
- HERMES_SWSUPPORT0
 
- HERMES_SWSUPPORT1
 
- HERMES_SWSUPPORT2
 
- HERMES_TEST_MONITOR
 
- HERMES_TEST_SET_CHANNEL
 
- HERMES_TEST_STOP
 
- HERMES_TXCNTL2_OFFSET
 
- HERMES_TXCOMPLFID
 
- HERMES_TXCTRL_802_11
 
- HERMES_TXCTRL_ALT_RTRY
 
- HERMES_TXCTRL_MIC
 
- HERMES_TXCTRL_MIC_KEY_ID
 
- HERMES_TXCTRL_TX_EX
 
- HERMES_TXCTRL_TX_OK
 
- HERMES_TXSTAT_AGEDERR
 
- HERMES_TXSTAT_DISCON
 
- HERMES_TXSTAT_FORMERR
 
- HERMES_TXSTAT_RETRYERR
 
- HERMES_WEP_EXCL_UNENCRYPTED
 
- HERMES_WEP_HOST_DECRYPT
 
- HERMES_WEP_HOST_ENCRYPT
 
- HERMES_WEP_PRIVACY_INVOKED
 
- HERMES_WRITE_RECORD
 
- HES
 
- HEST_DISABLED
 
- HEST_ENABLED
 
- HEST_NOT_FOUND
 
- HEST_PFX
 
- HEVC_ENC_CMD_END
 
- HEVC_ENC_CMD_FENCE
 
- HEVC_ENC_CMD_FLUSH_TLB
 
- HEVC_ENC_CMD_IB_VM
 
- HEVC_ENC_CMD_NO_OP
 
- HEVC_ENC_CMD_REG_WAIT
 
- HEVC_ENC_CMD_REG_WRITE
 
- HEVC_ENC_CMD_TRAP
 
- HEVC_ENC_CMD_UPDATE_PTB
 
- HEVC_ENC_CMD_WAIT_GE
 
- HEVC_NR_CLK
 
- HEX
 
- HEXAGON_ASM_USER_H
 
- HEXAGON_CPUINTS
 
- HEXAGON_L1_PTE_SIZE
 
- HEXAGON_OPT_FUNC_BEGIN
 
- HEXAGON_OPT_FUNC_FINISH
 
- HEXAGON_P_vrmpyh_PP
 
- HEXAGON_P_vrmpyhacc_PP
 
- HEXAGON_R_cl0_R
 
- HEXAGON_VM_SED_NULL
 
- HEXDIR_LEN
 
- HEXIUM_AUDIOS
 
- HEXIUM_GEMINI
 
- HEXIUM_GEMINI_DUAL
 
- HEXIUM_GEMINI_DUAL_V_1_0
 
- HEXIUM_GEMINI_V_1_0
 
- HEXIUM_HV_PCI6_ORION
 
- HEXIUM_INPUTS
 
- HEXIUM_ORION_1SVHS_3BNC
 
- HEXIUM_ORION_4BNC
 
- HEX_0
 
- HEX_1
 
- HEX_2
 
- HEX_3
 
- HEX_4
 
- HEX_5
 
- HEX_6
 
- HEX_7
 
- HEX_8
 
- HEX_9
 
- HEX_A
 
- HEX_ASCII
 
- HEX_B
 
- HEX_C
 
- HEX_CHARS
 
- HEX_D
 
- HEX_DISPLAY_UNIT
 
- HEX_E
 
- HEX_F
 
- HEX_GROUP_SIZE
 
- HEX_LINE_BITS
 
- HEX_LINE_CHARS
 
- HEX_MAX_LINES
 
- HEX_PREFIX
 
- HEX_ROW_SIZE
 
- HEX_STR
 
- HE_AIR_SNIFFER_CONFIG_CMD
 
- HE_COLORSET_ADDR
 
- HE_COLORSET_JUMP_ARROWS
 
- HE_COLORSET_MEDIUM
 
- HE_COLORSET_NORMAL
 
- HE_COLORSET_ROOT
 
- HE_COLORSET_SELECTED
 
- HE_COLORSET_TOP
 
- HE_DEV
 
- HE_GET_REG
 
- HE_LOOKUP_VCC
 
- HE_MAXCIDBITS
 
- HE_MAXIOV
 
- HE_NUM_CS_STPER
 
- HE_NUM_GROUPS
 
- HE_PREP
 
- HE_REGMAP_SIZE
 
- HE_REGTYPE_MBOX
 
- HE_REGTYPE_PCI
 
- HE_REGTYPE_RCM
 
- HE_REGTYPE_TCM
 
- HE_TPD_BUFSIZE
 
- HE_VCC
 
- HF
 
- HF2_TYPE
 
- HFA3841_PDA_BASE
 
- HFA3841_PDA_BOGUS_BASE
 
- HFA3842_PDA_BASE
 
- HFA384X_ALLOCFID_OFF
 
- HFA384X_ALLOC_COMPL_TIMEOUT
 
- HFA384X_AUXDATA_OFF
 
- HFA384X_AUXOFFSET_OFF
 
- HFA384X_AUXPAGE_OFF
 
- HFA384X_AUX_MAGIC0
 
- HFA384X_AUX_MAGIC1
 
- HFA384X_AUX_MAGIC2
 
- HFA384X_AUX_PORT_DISABLE
 
- HFA384X_AUX_PORT_DISABLED
 
- HFA384X_AUX_PORT_ENABLE
 
- HFA384X_AUX_PORT_ENABLED
 
- HFA384X_AUX_PORT_MASK
 
- HFA384X_BAP0_EVENTS
 
- HFA384X_BAP_BUSY_TIMEOUT
 
- HFA384X_CMDCODE_ACCESS
 
- HFA384X_CMDCODE_ACCESS_WRITE
 
- HFA384X_CMDCODE_ALLOC
 
- HFA384X_CMDCODE_DISABLE
 
- HFA384X_CMDCODE_DOWNLOAD
 
- HFA384X_CMDCODE_ENABLE
 
- HFA384X_CMDCODE_INIT
 
- HFA384X_CMDCODE_INQUIRE
 
- HFA384X_CMDCODE_MASK
 
- HFA384X_CMDCODE_READMIF
 
- HFA384X_CMDCODE_TEST
 
- HFA384X_CMDCODE_TRANSMIT
 
- HFA384X_CMDCODE_WRITEMIF
 
- HFA384X_CMD_BUSY
 
- HFA384X_CMD_BUSY_TIMEOUT
 
- HFA384X_CMD_COMPL_TIMEOUT
 
- HFA384X_CMD_OFF
 
- HFA384X_CMD_TX_RECLAIM
 
- HFA384X_COMP_ID_FW_AP
 
- HFA384X_COMP_ID_PRI
 
- HFA384X_COMP_ID_STA
 
- HFA384X_CONTROL_OFF
 
- HFA384X_DATA0_OFF
 
- HFA384X_DATA1_OFF
 
- HFA384X_DL_COMPL_TIMEOUT
 
- HFA384X_EVACK_OFF
 
- HFA384X_EVENT_MASK
 
- HFA384X_EVSTAT_OFF
 
- HFA384X_EV_ALLOC
 
- HFA384X_EV_CMD
 
- HFA384X_EV_DTIM
 
- HFA384X_EV_INFDROP
 
- HFA384X_EV_INFO
 
- HFA384X_EV_PCI_M0
 
- HFA384X_EV_PCI_M1
 
- HFA384X_EV_RX
 
- HFA384X_EV_TICK
 
- HFA384X_EV_TX
 
- HFA384X_EV_TXEXC
 
- HFA384X_EV_WTERR
 
- HFA384X_INB
 
- HFA384X_INFOFID_OFF
 
- HFA384X_INFO_ASSOCSTATUS
 
- HFA384X_INFO_AUTHREQ
 
- HFA384X_INFO_CHANNELINFORESULTS
 
- HFA384X_INFO_COMMTALLIES
 
- HFA384X_INFO_HANDOVERADDR
 
- HFA384X_INFO_HANDOVERDEAUTHADDR
 
- HFA384X_INFO_HOSTSCANRESULTS
 
- HFA384X_INFO_KEYIDCHANGED
 
- HFA384X_INFO_LINKSTATUS
 
- HFA384X_INFO_PSUSERCNT
 
- HFA384X_INFO_SCANRESULTS
 
- HFA384X_INIT_TIMEOUT
 
- HFA384X_INSW
 
- HFA384X_INTEN_OFF
 
- HFA384X_INW
 
- HFA384X_INW_DATA
 
- HFA384X_LEVEL_TO_dBm
 
- HFA384X_LEVEL_TO_dBm_sign
 
- HFA384X_LINKSTATUS_AP_CHANGE
 
- HFA384X_LINKSTATUS_AP_IN_RANGE
 
- HFA384X_LINKSTATUS_AP_OUT_OF_RANGE
 
- HFA384X_LINKSTATUS_ASSOC_FAILED
 
- HFA384X_LINKSTATUS_CONNECTED
 
- HFA384X_LINKSTATUS_DISCONNECTED
 
- HFA384X_MAGIC
 
- HFA384X_OFFSET0_OFF
 
- HFA384X_OFFSET1_OFF
 
- HFA384X_OFFSET_BUSY
 
- HFA384X_OFFSET_ERR
 
- HFA384X_OUTB
 
- HFA384X_OUTSW
 
- HFA384X_OUTW
 
- HFA384X_OUTW_DATA
 
- HFA384X_PARAM0_OFF
 
- HFA384X_PARAM1_OFF
 
- HFA384X_PARAM2_OFF
 
- HFA384X_PCICOR_OFF
 
- HFA384X_PCIHCR_OFF
 
- HFA384X_PCI_CTL_FROM_BAP
 
- HFA384X_PCI_CTL_TO_BAP
 
- HFA384X_PCI_M0_ADDRH_OFF
 
- HFA384X_PCI_M0_ADDRL_OFF
 
- HFA384X_PCI_M0_CTL_OFF
 
- HFA384X_PCI_M0_LEN_OFF
 
- HFA384X_PCI_M1_ADDRH_OFF
 
- HFA384X_PCI_M1_ADDRL_OFF
 
- HFA384X_PCI_M1_CTL_OFF
 
- HFA384X_PCI_M1_LEN_OFF
 
- HFA384X_PCI_STATUS_OFF
 
- HFA384X_PORTTYPE_BSS
 
- HFA384X_PORTTYPE_HOSTAP
 
- HFA384X_PORTTYPE_IBSS
 
- HFA384X_PORTTYPE_PSEUDO_IBSS
 
- HFA384X_PORTTYPE_WDS
 
- HFA384X_PROGMODE_DISABLE
 
- HFA384X_PROGMODE_ENABLE_NON_VOLATILE
 
- HFA384X_PROGMODE_ENABLE_VOLATILE
 
- HFA384X_PROGMODE_PROGRAM_NON_VOLATILE
 
- HFA384X_RATES_11MBPS
 
- HFA384X_RATES_1MBPS
 
- HFA384X_RATES_2MBPS
 
- HFA384X_RATES_5MBPS
 
- HFA384X_RESP0_OFF
 
- HFA384X_RESP1_OFF
 
- HFA384X_RESP2_OFF
 
- HFA384X_RID_ASSOCIATIONFAILURE
 
- HFA384X_RID_AUTHENTICATESTATION
 
- HFA384X_RID_AUTHENTICATIONALGORITHMS
 
- HFA384X_RID_AUTHENTICATIONUSED
 
- HFA384X_RID_BROADCASTKEYID
 
- HFA384X_RID_BUILDSEQ
 
- HFA384X_RID_CAPINFO
 
- HFA384X_RID_CCAMODE
 
- HFA384X_RID_CFIACTRANGES
 
- HFA384X_RID_CFIACTRANGES2
 
- HFA384X_RID_CFISUPRANGE
 
- HFA384X_RID_CFPOLLABLE
 
- HFA384X_RID_CHANNELINFOREQUEST
 
- HFA384X_RID_CHANNELLIST
 
- HFA384X_RID_CIS
 
- HFA384X_RID_CNFALTRETRYCOUNT
 
- HFA384X_RID_CNFAPPCFINFO
 
- HFA384X_RID_CNFAUTHENTICATION
 
- HFA384X_RID_CNFAUTHENTICATIONRSPTO
 
- HFA384X_RID_CNFBASICRATES
 
- HFA384X_RID_CNFBEACONINT
 
- HFA384X_RID_CNFDBMADJUST
 
- HFA384X_RID_CNFDEFAULTKEY0
 
- HFA384X_RID_CNFDEFAULTKEY1
 
- HFA384X_RID_CNFDEFAULTKEY2
 
- HFA384X_RID_CNFDEFAULTKEY3
 
- HFA384X_RID_CNFDESIREDSSID
 
- HFA384X_RID_CNFENHSECURITY
 
- HFA384X_RID_CNFEXCLUDELONGPREAMBLE
 
- HFA384X_RID_CNFFAASWITCHCTRL
 
- HFA384X_RID_CNFFALLBACKCTRL
 
- HFA384X_RID_CNFHOSTAUTHENTICATION
 
- HFA384X_RID_CNFLFOENABLED
 
- HFA384X_RID_CNFMAXASSOCSTA
 
- HFA384X_RID_CNFMAXDATALEN
 
- HFA384X_RID_CNFMAXSLEEPDURATION
 
- HFA384X_RID_CNFMMLIFE
 
- HFA384X_RID_CNFMULTICASTPMBUFFERING
 
- HFA384X_RID_CNFMULTICASTRECEIVE
 
- HFA384X_RID_CNFOWNATIMWINDOW
 
- HFA384X_RID_CNFOWNCHANNEL
 
- HFA384X_RID_CNFOWNDTIMPERIOD
 
- HFA384X_RID_CNFOWNMACADDR
 
- HFA384X_RID_CNFOWNNAME
 
- HFA384X_RID_CNFOWNSSID
 
- HFA384X_RID_CNFPASSIVESCANCTRL
 
- HFA384X_RID_CNFPMENABLED
 
- HFA384X_RID_CNFPMEPS
 
- HFA384X_RID_CNFPMHOLDOVERDURATION
 
- HFA384X_RID_CNFPORTTYPE
 
- HFA384X_RID_CNFPRIORITYQUSAGE
 
- HFA384X_RID_CNFRCVCRCERROR
 
- HFA384X_RID_CNFROAMINGMODE
 
- HFA384X_RID_CNFSHORTPREAMBLE
 
- HFA384X_RID_CNFSTAPCFINFO
 
- HFA384X_RID_CNFSUPPORTEDRATES
 
- HFA384X_RID_CNFSYSTEMSCALE
 
- HFA384X_RID_CNFTHIRTY2TALLY
 
- HFA384X_RID_CNFTIMCTRL
 
- HFA384X_RID_CNFTXCONTROL
 
- HFA384X_RID_CNFWDSADDRESS
 
- HFA384X_RID_CNFWDSADDRESS1
 
- HFA384X_RID_CNFWDSADDRESS2
 
- HFA384X_RID_CNFWDSADDRESS3
 
- HFA384X_RID_CNFWDSADDRESS4
 
- HFA384X_RID_CNFWDSADDRESS5
 
- HFA384X_RID_CNFWDSADDRESS6
 
- HFA384X_RID_CNFWEPDEFAULTKEYID
 
- HFA384X_RID_CNFWEPFLAGS
 
- HFA384X_RID_CNFWEPKEYMAPPINGTABLE
 
- HFA384X_RID_COMMSQUALITY
 
- HFA384X_RID_CREATEIBSS
 
- HFA384X_RID_CURRENTBEACONINTERVAL
 
- HFA384X_RID_CURRENTBSSID
 
- HFA384X_RID_CURRENTCHANNEL
 
- HFA384X_RID_CURRENTPOWERSTATE
 
- HFA384X_RID_CURRENTSCALETHRESHOLDS
 
- HFA384X_RID_CURRENTSSID
 
- HFA384X_RID_CURRENTTXRATE
 
- HFA384X_RID_CURRENTTXRATE1
 
- HFA384X_RID_CURRENTTXRATE2
 
- HFA384X_RID_CURRENTTXRATE3
 
- HFA384X_RID_CURRENTTXRATE4
 
- HFA384X_RID_CURRENTTXRATE5
 
- HFA384X_RID_CURRENTTXRATE6
 
- HFA384X_RID_DBMCOMMSQUALITY
 
- HFA384X_RID_DISALLOWEDBSSID
 
- HFA384X_RID_DOWNLOADBUFFER
 
- HFA384X_RID_ENTSECFLAGEYID
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD0
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD1
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD2
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD3
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD4
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD5
 
- HFA384X_RID_FRAGMENTATIONTHRESHOLD6
 
- HFA384X_RID_FWID
 
- HFA384X_RID_GENERICELEMENT
 
- HFA384X_RID_GROUPADDRESSES
 
- HFA384X_RID_HFODELAY
 
- HFA384X_RID_HOSTSCAN
 
- HFA384X_RID_HOSTSCANRESULTS
 
- HFA384X_RID_JOINREQUEST
 
- HFA384X_RID_LED_CTRL
 
- HFA384X_RID_LFO_VOLT_REG_TEST_RES
 
- HFA384X_RID_LISTENINTERVAL
 
- HFA384X_RID_LONGRETRYLIMIT
 
- HFA384X_RID_MAXLOADTIME
 
- HFA384X_RID_MAXRECEIVELIFETIME
 
- HFA384X_RID_MAXTRANSMITLIFETIME
 
- HFA384X_RID_MDCCONTROL
 
- HFA384X_RID_MDCCOUNTRY
 
- HFA384X_RID_MFIACTRANGES
 
- HFA384X_RID_MFISUPRANGE
 
- HFA384X_RID_NICID
 
- HFA384X_RID_NICSERNUM
 
- HFA384X_RID_OWNMACADDR
 
- HFA384X_RID_PHYTYPE
 
- HFA384X_RID_PORTSTATUS
 
- HFA384X_RID_PRIID
 
- HFA384X_RID_PRISUPRANGE
 
- HFA384X_RID_PRIVACYOPTIONIMPLEMENTED
 
- HFA384X_RID_PRODUCTNAME
 
- HFA384X_RID_PROMISCUOUSMODE
 
- HFA384X_RID_PROPAGATIONDELAY
 
- HFA384X_RID_PROTOCOLRSPTIME
 
- HFA384X_RID_REGULATORYDOMAINS
 
- HFA384X_RID_RTSTHRESHOLD
 
- HFA384X_RID_RTSTHRESHOLD0
 
- HFA384X_RID_RTSTHRESHOLD1
 
- HFA384X_RID_RTSTHRESHOLD2
 
- HFA384X_RID_RTSTHRESHOLD3
 
- HFA384X_RID_RTSTHRESHOLD4
 
- HFA384X_RID_RTSTHRESHOLD5
 
- HFA384X_RID_RTSTHRESHOLD6
 
- HFA384X_RID_SCANREQUEST
 
- HFA384X_RID_SCANRESULTSTABLE
 
- HFA384X_RID_SHORTRETRYLIMIT
 
- HFA384X_RID_SSNHANDLINGMODE
 
- HFA384X_RID_STAID
 
- HFA384X_RID_STASUPRANGE
 
- HFA384X_RID_SUPPORTEDDATARATES
 
- HFA384X_RID_SW_ANT_DIV
 
- HFA384X_RID_TEMPTYPE
 
- HFA384X_RID_TICKTIME
 
- HFA384X_RID_TXPOWERMAX
 
- HFA384X_RID_TXRATECONTROL
 
- HFA384X_RID_TXRATECONTROL0
 
- HFA384X_RID_TXRATECONTROL1
 
- HFA384X_RID_TXRATECONTROL2
 
- HFA384X_RID_TXRATECONTROL3
 
- HFA384X_RID_TXRATECONTROL4
 
- HFA384X_RID_TXRATECONTROL5
 
- HFA384X_RID_TXRATECONTROL6
 
- HFA384X_RID_UNKNOWN1
 
- HFA384X_RID_UNKNOWN2
 
- HFA384X_RID_UNKNOWN3
 
- HFA384X_RID_WEPKEYDISABLE
 
- HFA384X_RID_WEPKEYMAPINDEX
 
- HFA384X_ROAMING_DISABLED
 
- HFA384X_ROAMING_FIRMWARE
 
- HFA384X_ROAMING_HOST
 
- HFA384X_RXFID_OFF
 
- HFA384X_RX_MSGTYPE_BRIDGETUNNEL
 
- HFA384X_RX_MSGTYPE_MGMT
 
- HFA384X_RX_MSGTYPE_NORMAL
 
- HFA384X_RX_MSGTYPE_RFC1042
 
- HFA384X_RX_STATUS_FCSERR
 
- HFA384X_RX_STATUS_GET_MACPORT
 
- HFA384X_RX_STATUS_GET_MSGTYPE
 
- HFA384X_RX_STATUS_MACPORT
 
- HFA384X_RX_STATUS_MSGTYPE
 
- HFA384X_RX_STATUS_PCF
 
- HFA384X_RX_STATUS_UNDECR
 
- HFA384X_SCAN_FIRMWARE_INITIATED
 
- HFA384X_SCAN_HOST_INITIATED
 
- HFA384X_SCAN_INQUIRY_FROM_HOST
 
- HFA384X_SCAN_IN_PROGRESS
 
- HFA384X_SCAN_MAX_RESULTS
 
- HFA384X_SELECT0_OFF
 
- HFA384X_SELECT1_OFF
 
- HFA384X_STATUS_OFF
 
- HFA384X_SWSUPPORT0_OFF
 
- HFA384X_SWSUPPORT1_OFF
 
- HFA384X_SWSUPPORT2_OFF
 
- HFA384X_TEST_CFG_BITS
 
- HFA384X_TEST_CFG_BIT_ALC
 
- HFA384X_TEST_CHANGE_CHANNEL
 
- HFA384X_TEST_MONITOR
 
- HFA384X_TEST_STOP
 
- HFA384X_TXCOMPLFID_OFF
 
- HFA384X_TX_CTRL_802_11
 
- HFA384X_TX_CTRL_802_3
 
- HFA384X_TX_CTRL_ALT_RTRY
 
- HFA384X_TX_CTRL_FLAGS
 
- HFA384X_TX_CTRL_TX_EX
 
- HFA384X_TX_CTRL_TX_OK
 
- HFA384X_TX_STATUS_AGEDERR
 
- HFA384X_TX_STATUS_DISCON
 
- HFA384X_TX_STATUS_FORMERR
 
- HFA384X_TX_STATUS_RETRYERR
 
- HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED
 
- HFA384X_WEPFLAGS_HOSTDECRYPT
 
- HFA384X_WEPFLAGS_HOSTENCRYPT
 
- HFA384X_WEPFLAGS_PRIVACYINVOKED
 
- HFA384x_ADDR_AUX_MKFLAT
 
- HFA384x_ADDR_AUX_OFF_MASK
 
- HFA384x_ADDR_AUX_PAGE_MASK
 
- HFA384x_ADDR_CMD_MKOFF
 
- HFA384x_ADDR_CMD_MKPAGE
 
- HFA384x_ADDR_FLAT_AUX_OFF_MASK
 
- HFA384x_ADDR_FLAT_AUX_PAGE_MASK
 
- HFA384x_ADDR_FLAT_CMD_OFF_MASK
 
- HFA384x_ADDR_FLAT_CMD_PAGE_MASK
 
- HFA384x_ASSOCSTATUS_AUTHFAIL
 
- HFA384x_ASSOCSTATUS_REASSOC
 
- HFA384x_ASSOCSTATUS_STAASSOC
 
- HFA384x_CHINFORESULT_BSSACTIVE
 
- HFA384x_CHINFORESULT_MAX
 
- HFA384x_CHINFORESULT_PCFACTIVE
 
- HFA384x_CMDCODE_DISABLE
 
- HFA384x_CMDCODE_DOWNLD
 
- HFA384x_CMDCODE_ENABLE
 
- HFA384x_CMDCODE_INIT
 
- HFA384x_CMDCODE_INQ
 
- HFA384x_CMDCODE_MONITOR
 
- HFA384x_CMD_AINFO
 
- HFA384x_CMD_AINFO_SET
 
- HFA384x_CMD_CMDCODE
 
- HFA384x_CMD_CMDCODE_SET
 
- HFA384x_CMD_ERR
 
- HFA384x_CMD_MACPORT
 
- HFA384x_CMD_MACPORT_SET
 
- HFA384x_CMD_PROGMODE
 
- HFA384x_CMD_PROGMODE_SET
 
- HFA384x_CNFAUTHENTICATION_LEAP
 
- HFA384x_CNFAUTHENTICATION_OPENSYSTEM
 
- HFA384x_CNFAUTHENTICATION_SHAREDKEY
 
- HFA384x_CREATEIBSS_JOINCREATEIBSS
 
- HFA384x_DLSTATE_DISABLED
 
- HFA384x_DLSTATE_FLASHENABLED
 
- HFA384x_DLSTATE_RAMENABLED
 
- HFA384x_FIRMWARE_VERSION
 
- HFA384x_HSCANRESULT_MAX
 
- HFA384x_IT_ASSOCREQ
 
- HFA384x_IT_ASSOCSTATUS
 
- HFA384x_IT_AUTHREQ
 
- HFA384x_IT_CHINFORESULTS
 
- HFA384x_IT_COMMTALLIES
 
- HFA384x_IT_HANDOVERADDR
 
- HFA384x_IT_HOSTSCANRESULTS
 
- HFA384x_IT_KEYIDCHANGED
 
- HFA384x_IT_LINKSTATUS
 
- HFA384x_IT_MICFAILURE
 
- HFA384x_IT_PSUSERCNT
 
- HFA384x_IT_SCANRESULTS
 
- HFA384x_LINK_AP_CHANGE
 
- HFA384x_LINK_AP_INRANGE
 
- HFA384x_LINK_AP_OUTOFRANGE
 
- HFA384x_LINK_ASSOCFAIL
 
- HFA384x_LINK_CONNECTED
 
- HFA384x_LINK_DISCONNECTED
 
- HFA384x_LINK_NOTCONNECTED
 
- HFA384x_MONITOR_DISABLE
 
- HFA384x_MONITOR_ENABLE
 
- HFA384x_NUMPORTS_MAX
 
- HFA384x_PDA_LEN_MAX
 
- HFA384x_PDA_RECS_MAX
 
- HFA384x_PDR_3842_NIC_CONFIG
 
- HFA384x_PDR_ALLOWED_CHANNEL
 
- HFA384x_PDR_ANT_DIVERSITY
 
- HFA384x_PDR_CFISUPRANGE
 
- HFA384x_PDR_DEFAULT_CHANNEL
 
- HFA384x_PDR_END_OF_PDA
 
- HFA384x_PDR_HFA3861_BASELINE
 
- HFA384x_PDR_HFA3861_CHCALI
 
- HFA384x_PDR_HFA3861_CHCALSP
 
- HFA384x_PDR_HFA3861_IFRF
 
- HFA384x_PDR_HFA3861_MANF_TESTI
 
- HFA384x_PDR_HFA3861_MANF_TESTSP
 
- HFA384x_PDR_HFA3861_SHADOW
 
- HFA384x_PDR_HFO_DELAY
 
- HFA384x_PDR_IFR_SETTING
 
- HFA384x_PDR_LEN_MAX
 
- HFA384x_PDR_MAC_ADDRESS
 
- HFA384x_PDR_MASTER_CHAN_LIST
 
- HFA384x_PDR_MAX_TX_POWER
 
- HFA384x_PDR_MFISUPRANGE
 
- HFA384x_PDR_MKK_MEASUREMENTS
 
- HFA384x_PDR_NICID
 
- HFA384x_PDR_NIC_RAMSIZE
 
- HFA384x_PDR_NIC_SERIAL
 
- HFA384x_PDR_PCB_PARTNUM
 
- HFA384x_PDR_PCI_ID
 
- HFA384x_PDR_PCI_IFCONF
 
- HFA384x_PDR_PCI_PMCONF
 
- HFA384x_PDR_PDAVER
 
- HFA384x_PDR_REGDOMAIN
 
- HFA384x_PDR_RFENRGY
 
- HFA384x_PDR_RFR_SETTING
 
- HFA384x_PDR_SCALE_THRESH
 
- HFA384x_PDR_TEMPTYPE
 
- HFA384x_PDR_USB_ID
 
- HFA384x_PDR_USB_MANUFACTURER
 
- HFA384x_PDR_USB_MAX_POWER
 
- HFA384x_PDR_USB_POWER_TYPE
 
- HFA384x_PDR_USB_PRODUCT
 
- HFA384x_PORTID_MAX
 
- HFA384x_PORTSTATUS_DISABLED
 
- HFA384x_PORTTYPE_BSS
 
- HFA384x_PORTTYPE_IBSS
 
- HFA384x_PORTTYPE_PSUEDOIBSS
 
- HFA384x_PROGMODE_DISABLE
 
- HFA384x_PROGMODE_NV
 
- HFA384x_PROGMODE_NVWRITE
 
- HFA384x_PROGMODE_RAM
 
- HFA384x_PSTATUS_CONN_IBSS
 
- HFA384x_RATEBIT_1
 
- HFA384x_RATEBIT_11
 
- HFA384x_RATEBIT_2
 
- HFA384x_RATEBIT_5dot5
 
- HFA384x_RIDDATA_MAXLEN
 
- HFA384x_RID_AUTHENTICATESTA
 
- HFA384x_RID_CFISUPRANGE
 
- HFA384x_RID_CNFAPBCNINT
 
- HFA384x_RID_CNFAUTHENTICATION
 
- HFA384x_RID_CNFBASICRATES
 
- HFA384x_RID_CNFDBMADJUST
 
- HFA384x_RID_CNFDESIREDSSID
 
- HFA384x_RID_CNFDESIREDSSID_LEN
 
- HFA384x_RID_CNFMAXDATALEN
 
- HFA384x_RID_CNFOWNCHANNEL
 
- HFA384x_RID_CNFOWNMACADDR
 
- HFA384x_RID_CNFOWNMACADDR_LEN
 
- HFA384x_RID_CNFOWNSSID
 
- HFA384x_RID_CNFOWNSSID_LEN
 
- HFA384x_RID_CNFPASSIVESCANCTRL
 
- HFA384x_RID_CNFPORTTYPE
 
- HFA384x_RID_CNFROAMINGMODE
 
- HFA384x_RID_CNFSUPPRATES
 
- HFA384x_RID_CNFWEP128DEFAULTKEY_LEN
 
- HFA384x_RID_CNFWEPDEFAULTKEY0
 
- HFA384x_RID_CNFWEPDEFAULTKEY1
 
- HFA384x_RID_CNFWEPDEFAULTKEY2
 
- HFA384x_RID_CNFWEPDEFAULTKEY3
 
- HFA384x_RID_CNFWEPDEFAULTKEYID
 
- HFA384x_RID_CNFWEPDEFAULTKEY_LEN
 
- HFA384x_RID_CNFWEPFLAGS
 
- HFA384x_RID_CNFWPADATA
 
- HFA384x_RID_CREATEIBSS
 
- HFA384x_RID_CURRENTBSSID
 
- HFA384x_RID_CURRENTCHANNEL
 
- HFA384x_RID_CURRENTSSID
 
- HFA384x_RID_CURRENTTXRATE
 
- HFA384x_RID_DBMCOMMSQUALITY
 
- HFA384x_RID_DBMCOMMSQUALITY_LEN
 
- HFA384x_RID_DOWNLOADBUFFER
 
- HFA384x_RID_FRAGTHRESH
 
- HFA384x_RID_GUESSING_MAXLEN
 
- HFA384x_RID_HOSTSCAN
 
- HFA384x_RID_JOINREQUEST
 
- HFA384x_RID_JOINREQUEST_LEN
 
- HFA384x_RID_LONGRETRYLIMIT
 
- HFA384x_RID_MAXLOADTIME
 
- HFA384x_RID_MAXTXLIFETIME
 
- HFA384x_RID_MFISUPRANGE
 
- HFA384x_RID_NICIDENTITY
 
- HFA384x_RID_NICSERIALNUMBER
 
- HFA384x_RID_NICSERIALNUMBER_LEN
 
- HFA384x_RID_PORTSTATUS
 
- HFA384x_RID_PRIIDENTITY
 
- HFA384x_RID_PRISUPRANGE
 
- HFA384x_RID_PRIVACYOPTIMP
 
- HFA384x_RID_PRI_CFIACTRANGES
 
- HFA384x_RID_PROMISCMODE
 
- HFA384x_RID_RTSTHRESH
 
- HFA384x_RID_SHORTRETRYLIMIT
 
- HFA384x_RID_STAIDENTITY
 
- HFA384x_RID_STASUPRANGE
 
- HFA384x_RID_STA_CFIACTRANGES
 
- HFA384x_RID_STA_MFIACTRANGES
 
- HFA384x_RID_TXPOWERMAX
 
- HFA384x_RID_TXRATECNTL
 
- HFA384x_ROAMMODE_HOSTSCAN_HOSTROAM
 
- HFA384x_RXSTATUS_FCSERR
 
- HFA384x_RXSTATUS_ISFCSERR
 
- HFA384x_RXSTATUS_MACPORT
 
- HFA384x_RXSTATUS_MACPORT_GET
 
- HFA384x_SCANRESULT_MAX
 
- HFA384x_STATE_INIT
 
- HFA384x_STATE_PREINIT
 
- HFA384x_STATE_RUNNING
 
- HFA384x_STATUS_RESULT
 
- HFA384x_STATUS_RESULT_SET
 
- HFA384x_TXSTATUS_ACKERR
 
- HFA384x_TXSTATUS_AGEDERR
 
- HFA384x_TXSTATUS_DISCON
 
- HFA384x_TXSTATUS_FORMERR
 
- HFA384x_TXSTATUS_ISERROR
 
- HFA384x_TXSTATUS_RETRYERR
 
- HFA384x_TX_MACPORT
 
- HFA384x_TX_MACPORT_SET
 
- HFA384x_TX_SET
 
- HFA384x_TX_STRUCTYPE
 
- HFA384x_TX_STRUCTYPE_SET
 
- HFA384x_TX_TXEX
 
- HFA384x_TX_TXEX_SET
 
- HFA384x_TX_TXOK
 
- HFA384x_TX_TXOK_SET
 
- HFA384x_USB_BUFAVAIL
 
- HFA384x_USB_CMDREQ
 
- HFA384x_USB_CMDRESP
 
- HFA384x_USB_ERROR
 
- HFA384x_USB_INFOFRM
 
- HFA384x_USB_ISRXFRM
 
- HFA384x_USB_ISTXFRM
 
- HFA384x_USB_RMEMREQ
 
- HFA384x_USB_RMEMRESP
 
- HFA384x_USB_RRIDREQ
 
- HFA384x_USB_RRIDRESP
 
- HFA384x_USB_RWMEM_MAXLEN
 
- HFA384x_USB_TXFRM
 
- HFA384x_USB_WMEMREQ
 
- HFA384x_USB_WMEMRESP
 
- HFA384x_USB_WRIDREQ
 
- HFA384x_USB_WRIDRESP
 
- HFA384x_WEPFLAGS_DISABLE_RXCRYPT
 
- HFA384x_WEPFLAGS_DISABLE_TXCRYPT
 
- HFA384x_WEPFLAGS_EXCLUDE
 
- HFA384x_WEPFLAGS_PRIVINVOKED
 
- HFA386X_CR_A_D_TEST_MODES2
 
- HFA386X_CR_MANUAL_TX_POWER
 
- HFA386X_CR_MEASURED_TX_POWER
 
- HFA386X_CR_RX_CONFIGURE
 
- HFA386X_CR_TX_CONFIGURE
 
- HFB_CTRL
 
- HFB_FLT_ENABLE_V3PLUS
 
- HFB_FLT_LEN_V2
 
- HFB_FLT_LEN_V3PLUS
 
- HFB_PITCH_ADDR
 
- HFB_PITCH_ADDR_LG
 
- HFCLK_FREQ_19p2_MHZ
 
- HFCLK_FREQ_26_MHZ
 
- HFCLK_FREQ_38p4_MHZ
 
- HFCPCI_ACTIVATE
 
- HFCPCI_ANYINT
 
- HFCPCI_AUTO_AWAKE
 
- HFCPCI_AUTO_TIMER
 
- HFCPCI_AUX1_D
 
- HFCPCI_AUX1_RSL
 
- HFCPCI_AUX1_SSL
 
- HFCPCI_AUX2_D
 
- HFCPCI_AUX2_RSL
 
- HFCPCI_AUX2_SSL
 
- HFCPCI_AUX_MSK
 
- HFCPCI_B1_D
 
- HFCPCI_B1_REC
 
- HFCPCI_B1_REV
 
- HFCPCI_B1_RSL
 
- HFCPCI_B1_SEND
 
- HFCPCI_B1_SSL
 
- HFCPCI_B2_D
 
- HFCPCI_B2_REC
 
- HFCPCI_B2_REV
 
- HFCPCI_B2_RSL
 
- HFCPCI_B2_SEND
 
- HFCPCI_B2_SSL
 
- HFCPCI_BTRANS_THRESHOLD
 
- HFCPCI_BTRANS_THRESMASK
 
- HFCPCI_B_MODE
 
- HFCPCI_CHG_B1_B2
 
- HFCPCI_CHIP_ID
 
- HFCPCI_CIRM
 
- HFCPCI_CLKDEL
 
- HFCPCI_CLTIMER
 
- HFCPCI_CONNECT
 
- HFCPCI_CTMT
 
- HFCPCI_DBIT_1
 
- HFCPCI_DO_ACTION
 
- HFCPCI_D_REC
 
- HFCPCI_D_SEND
 
- HFCPCI_E_REC
 
- HFCPCI_F0IO_POSITIV
 
- HFCPCI_F0_2C4
 
- HFCPCI_F0_NEGATIV
 
- HFCPCI_FIFOEN_B1
 
- HFCPCI_FIFOEN_B1RX
 
- HFCPCI_FIFOEN_B1TX
 
- HFCPCI_FIFOEN_B2
 
- HFCPCI_FIFOEN_B2RX
 
- HFCPCI_FIFOEN_B2TX
 
- HFCPCI_FIFOEN_DTX
 
- HFCPCI_FIFO_EN
 
- HFCPCI_FILLEMPTY
 
- HFCPCI_FRAMEINT
 
- HFCPCI_GCI_I_CHG
 
- HFCPCI_GCI_MON_REC
 
- HFCPCI_IGNORE_COL
 
- HFCPCI_INTS_B1REC
 
- HFCPCI_INTS_B1TRANS
 
- HFCPCI_INTS_B2REC
 
- HFCPCI_INTS_B2TRANS
 
- HFCPCI_INTS_DREC
 
- HFCPCI_INTS_DTRANS
 
- HFCPCI_INTS_L1STATE
 
- HFCPCI_INTS_TIMER
 
- HFCPCI_INT_M1
 
- HFCPCI_INT_M2
 
- HFCPCI_INT_S1
 
- HFCPCI_INT_S2
 
- HFCPCI_IRQ_ENABLE
 
- HFCPCI_LOAD_STATE
 
- HFCPCI_MASTER
 
- HFCPCI_MON1_D
 
- HFCPCI_MON2_D
 
- HFCPCI_MST_EMOD
 
- HFCPCI_MST_MODE
 
- HFCPCI_NBUSY
 
- HFCPCI_NT_G2_G3
 
- HFCPCI_PCI_PROC
 
- HFCPCI_PMESEL
 
- HFCPCI_PROC_TRANS
 
- HFCPCI_RESET
 
- HFCPCI_SCTRL
 
- HFCPCI_SCTRL_E
 
- HFCPCI_SCTRL_R
 
- HFCPCI_SLAVE
 
- HFCPCI_SQ
 
- HFCPCI_STATES
 
- HFCPCI_STATE_MSK
 
- HFCPCI_STATINT
 
- HFCPCI_STATUS
 
- HFCPCI_TIM25
 
- HFCPCI_TIM3_125
 
- HFCPCI_TIM400
 
- HFCPCI_TIM50
 
- HFCPCI_TIM800
 
- HFCPCI_TIMER_ELAP
 
- HFCPCI_TRANSB1
 
- HFCPCI_TRANSB2
 
- HFCPCI_TRM
 
- HFCPCI_TRxR
 
- HFCUSB_ACTIVATE
 
- HFCUSB_B1_RSL
 
- HFCUSB_B1_RX
 
- HFCUSB_B1_SSL
 
- HFCUSB_B1_TX
 
- HFCUSB_B2_RSL
 
- HFCUSB_B2_RX
 
- HFCUSB_B2_SSL
 
- HFCUSB_B2_TX
 
- HFCUSB_CHIPID
 
- HFCUSB_CHIP_ID
 
- HFCUSB_CIRM
 
- HFCUSB_CLKDEL
 
- HFCUSB_CON_HDLC
 
- HFCUSB_DO_ACTION
 
- HFCUSB_D_RX
 
- HFCUSB_D_TX
 
- HFCUSB_FIFO
 
- HFCUSB_F_CROSS
 
- HFCUSB_F_THRES
 
- HFCUSB_F_USAGE
 
- HFCUSB_HDLC_PAR
 
- HFCUSB_INC_RES_F
 
- HFCUSB_LOAD_STATE
 
- HFCUSB_MST_MODE0
 
- HFCUSB_MST_MODE1
 
- HFCUSB_NT_G2_G3
 
- HFCUSB_NUM_FIFOS
 
- HFCUSB_PCM_RX
 
- HFCUSB_PCM_TX
 
- HFCUSB_P_DATA
 
- HFCUSB_RX_THRESHOLD
 
- HFCUSB_SCTRL
 
- HFCUSB_SCTRL_E
 
- HFCUSB_SCTRL_R
 
- HFCUSB_STATES
 
- HFCUSB_TX_THRESHOLD
 
- HFCUSB_USB_SIZE
 
- HFCUSB_USB_SIZE_I
 
- HFC_ABOCOM_2BD1
 
- HFC_ANIGMA_MC145575
 
- HFC_ASUS_0675
 
- HFC_BERKOM_A1T
 
- HFC_BERKOM_TCONCEPT
 
- HFC_CCD_2BD0
 
- HFC_CCD_B000
 
- HFC_CCD_B006
 
- HFC_CCD_B007
 
- HFC_CCD_B008
 
- HFC_CCD_B009
 
- HFC_CCD_B00A
 
- HFC_CCD_B00B
 
- HFC_CCD_B00C
 
- HFC_CCD_B100
 
- HFC_CCD_B700
 
- HFC_CCD_B701
 
- HFC_CFG_2HFC
 
- HFC_CFG_CRC4
 
- HFC_CFG_DIS_ECHANNEL
 
- HFC_CFG_DTMF
 
- HFC_CFG_MASTER
 
- HFC_CFG_NEG_F0
 
- HFC_CFG_NONCAP_TX
 
- HFC_CFG_OPTICAL
 
- HFC_CFG_PCM
 
- HFC_CFG_REG_ECHANNEL
 
- HFC_CFG_REPORT_AIS
 
- HFC_CFG_REPORT_LOS
 
- HFC_CFG_REPORT_RDI
 
- HFC_CFG_REPORT_SLIP
 
- HFC_CFG_SLAVE
 
- HFC_CFG_SLAVEHFC
 
- HFC_CFG_SW_DD_DU
 
- HFC_CHAN_B1
 
- HFC_CHAN_B2
 
- HFC_CHAN_D
 
- HFC_CHAN_E
 
- HFC_CHIP_B410P
 
- HFC_CHIP_CLOCK2
 
- HFC_CHIP_CONF
 
- HFC_CHIP_DTMF
 
- HFC_CHIP_E1CLOCK_GET
 
- HFC_CHIP_E1CLOCK_PUT
 
- HFC_CHIP_EMBSD
 
- HFC_CHIP_EXRAM_128
 
- HFC_CHIP_EXRAM_512
 
- HFC_CHIP_PCM_MASTER
 
- HFC_CHIP_PCM_SLAVE
 
- HFC_CHIP_PLXSD
 
- HFC_CHIP_REVISION0
 
- HFC_CHIP_RX_SYNC
 
- HFC_CHIP_ULAW
 
- HFC_CHIP_WATCHDOG
 
- HFC_CTRL_BUFSIZE
 
- HFC_CTRL_TIMEOUT
 
- HFC_DIGI_DF_M_A
 
- HFC_DIGI_DF_M_E
 
- HFC_DIGI_DF_M_IOM2_A
 
- HFC_DIGI_DF_M_IOM2_E
 
- HFC_IO_MODE_EMBSD
 
- HFC_IO_MODE_PCIMEM
 
- HFC_IO_MODE_PLXSD
 
- HFC_IO_MODE_REGIO
 
- HFC_L1_ACTIVATE_NT
 
- HFC_L1_ACTIVATE_TE
 
- HFC_L1_DEACTIVATE_NT
 
- HFC_L1_FORCE_DEACTIVATE_TE
 
- HFC_MAX_NT_LAYER1_STATE
 
- HFC_MAX_TE_LAYER1_STATE
 
- HFC_MULTI_VERSION
 
- HFC_PLL
 
- HFC_RDY
 
- HFC_SITECOM_DC105V2
 
- HFC_SPL_LOOP_OFF
 
- HFC_SPL_LOOP_ON
 
- HFC_TYPE_4S
 
- HFC_TYPE_8S
 
- HFC_TYPE_E1
 
- HFC_TYPE_XHFC
 
- HFC_VOL_CHANGE_RX
 
- HFC_VOL_CHANGE_TX
 
- HFC_ZOLTRIX_2BD0
 
- HFC_cleanup
 
- HFC_inb
 
- HFC_inb_debug
 
- HFC_inb_embsd
 
- HFC_inb_nodebug
 
- HFC_inb_pcimem
 
- HFC_inb_regio
 
- HFC_init
 
- HFC_inw
 
- HFC_inw_debug
 
- HFC_inw_embsd
 
- HFC_inw_nodebug
 
- HFC_inw_pcimem
 
- HFC_inw_regio
 
- HFC_outb
 
- HFC_outb_debug
 
- HFC_outb_embsd
 
- HFC_outb_nodebug
 
- HFC_outb_pcimem
 
- HFC_outb_regio
 
- HFC_wait
 
- HFC_wait_debug
 
- HFC_wait_embsd
 
- HFC_wait_nodebug
 
- HFC_wait_pcimem
 
- HFC_wait_regio
 
- HFCmulti_cleanup
 
- HFCmulti_init
 
- HFGFlags
 
- HFG_CONTEXT_SWITCH_MODE
 
- HFG_CONTEXT_SWITCH_MODE_BIT
 
- HFG_FIRST_EXECUTE_MODE
 
- HFG_FIRST_EXECUTE_MODE_BIT
 
- HFG_STACK
 
- HFG_TREE_SCB
 
- HFI1_ADMIN_JKEY_RANGE
 
- HFI1_CAP_ALLOW_PERM_JKEY
 
- HFI1_CAP_CLEAR
 
- HFI1_CAP_DMA_RTAIL
 
- HFI1_CAP_EARLY_CREDIT_RETURN
 
- HFI1_CAP_EXTENDED_PSN
 
- HFI1_CAP_HDRSUPP
 
- HFI1_CAP_IS_KSET
 
- HFI1_CAP_IS_USET
 
- HFI1_CAP_K2U
 
- HFI1_CAP_KCLEAR
 
- HFI1_CAP_KGET
 
- HFI1_CAP_KGET_MASK
 
- HFI1_CAP_KSET
 
- HFI1_CAP_LOCK
 
- HFI1_CAP_LOCKED
 
- HFI1_CAP_LOCKED_MASK
 
- HFI1_CAP_LOCKED_SHIFT
 
- HFI1_CAP_LOCKED_SMASK
 
- HFI1_CAP_MASK
 
- HFI1_CAP_MASK_DEFAULT
 
- HFI1_CAP_MISC_MASK
 
- HFI1_CAP_MISC_SHIFT
 
- HFI1_CAP_MULTI_PKT_EGR
 
- HFI1_CAP_MUST_HAVE_KERN
 
- HFI1_CAP_NODROP_EGR_FULL
 
- HFI1_CAP_NODROP_RHQ_FULL
 
- HFI1_CAP_NO_INTEGRITY
 
- HFI1_CAP_OPFN
 
- HFI1_CAP_PKEY_CHECK
 
- HFI1_CAP_PRINT_UNIMPL
 
- HFI1_CAP_RESERVED_MASK
 
- HFI1_CAP_SDMA
 
- HFI1_CAP_SDMA_AHG
 
- HFI1_CAP_SDMA_HEAD_CHECK
 
- HFI1_CAP_SET
 
- HFI1_CAP_STATIC_RATE_CTRL
 
- HFI1_CAP_TID_RDMA
 
- HFI1_CAP_TID_UNMAP
 
- HFI1_CAP_UCLEAR
 
- HFI1_CAP_UGET
 
- HFI1_CAP_UGET_MASK
 
- HFI1_CAP_USER_SHIFT
 
- HFI1_CAP_USET
 
- HFI1_CAP_USE_SDMA_HEAD
 
- HFI1_CAP_WRITABLE_MASK
 
- HFI1_CHIP_VERS_MAJ
 
- HFI1_CHIP_VERS_MIN
 
- HFI1_CONG_TIMER_PSINTERVAL
 
- HFI1_CREDIT_RETURN_RATE
 
- HFI1_CTRL_CTXT
 
- HFI1_CTXT_BASE_FAILED
 
- HFI1_CTXT_BASE_UNINIT
 
- HFI1_CTXT_WAITING_RCV
 
- HFI1_CTXT_WAITING_URG
 
- HFI1_DEFAULT_ACTIVE_MTU
 
- HFI1_DEFAULT_MAX_MTU
 
- HFI1_DRIVER_VERSION
 
- HFI1_DRIVER_VERSION_BASE
 
- HFI1_EFIVAR_GUID
 
- HFI1_EFT_PLATFORM_CONFIG
 
- HFI1_EVENT_FROZEN
 
- HFI1_EVENT_LID_CHANGE
 
- HFI1_EVENT_LINKDOWN
 
- HFI1_EVENT_LMC_CHANGE
 
- HFI1_EVENT_SL2VL_CHANGE
 
- HFI1_EVENT_TID_MMU_NOTIFY
 
- HFI1_FAULT_DIR_RX
 
- HFI1_FAULT_DIR_TX
 
- HFI1_FAULT_DIR_TXRX
 
- HFI1_FORCED_FREEZE
 
- HFI1_FROZEN
 
- HFI1_GUIDS_PER_PORT
 
- HFI1_HAS_GRH
 
- HFI1_HAS_SDMA_TIMEOUT
 
- HFI1_HAS_SEND_DMA
 
- HFI1_IB_CFG_HRTBT
 
- HFI1_IB_CFG_LIDLMC
 
- HFI1_IB_CFG_LINKDEFAULT
 
- HFI1_IB_CFG_LINKLATENCY
 
- HFI1_IB_CFG_LREV_ENB
 
- HFI1_IB_CFG_LWID
 
- HFI1_IB_CFG_LWID_DG_ENB
 
- HFI1_IB_CFG_LWID_ENB
 
- HFI1_IB_CFG_MTU
 
- HFI1_IB_CFG_OP_VLS
 
- HFI1_IB_CFG_OVERRUN_THRESH
 
- HFI1_IB_CFG_PHYERR_THRESH
 
- HFI1_IB_CFG_PKEYS
 
- HFI1_IB_CFG_PMA_TICKS
 
- HFI1_IB_CFG_PORT
 
- HFI1_IB_CFG_RXPOL_ENB
 
- HFI1_IB_CFG_SPD
 
- HFI1_IB_CFG_SPD_ENB
 
- HFI1_IB_CFG_VL_HIGH_CAP
 
- HFI1_IB_CFG_VL_HIGH_LIMIT
 
- HFI1_IB_CFG_VL_LOW_CAP
 
- HFI1_INITTED
 
- HFI1_IOCTL_ACK_EVENT
 
- HFI1_IOCTL_ASSIGN_CTXT
 
- HFI1_IOCTL_CREDIT_UPD
 
- HFI1_IOCTL_CTXT_INFO
 
- HFI1_IOCTL_CTXT_RESET
 
- HFI1_IOCTL_GET_VERS
 
- HFI1_IOCTL_POLL_TYPE
 
- HFI1_IOCTL_RECV_CTRL
 
- HFI1_IOCTL_SET_PKEY
 
- HFI1_IOCTL_TID_FREE
 
- HFI1_IOCTL_TID_INVAL_READ
 
- HFI1_IOCTL_TID_UPDATE
 
- HFI1_IOCTL_USER_INFO
 
- HFI1_JKEY_MASK
 
- HFI1_JKEY_WIDTH
 
- HFI1_KDETH_BTH_SEQ_MASK
 
- HFI1_KDETH_BTH_SEQ_SHIFT
 
- HFI1_KERNEL_MAX_JKEY
 
- HFI1_KERNEL_MIN_JKEY
 
- HFI1_KERN_SWVERSION
 
- HFI1_KERN_TYPE
 
- HFI1_LRH_BTH
 
- HFI1_LRH_GRH
 
- HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES
 
- HFI1_MAX_EAGER_BUFFER_SIZE
 
- HFI1_MAX_HDRQ_EGRBUF_CNT
 
- HFI1_MAX_RDMA_ATOMIC
 
- HFI1_MAX_SHARED_CTXTS
 
- HFI1_MAX_VLS_SUPPORTED
 
- HFI1_MIN_EAGER_BUFFER_SIZE
 
- HFI1_MIN_HDRQ_EGRBUF_CNT
 
- HFI1_MIN_USER_CTXT_BUFCNT
 
- HFI1_MIN_VLS_SUPPORTED
 
- HFI1_MISC_GET
 
- HFI1_MMAP_CTXT_MASK
 
- HFI1_MMAP_CTXT_SHIFT
 
- HFI1_MMAP_MAGIC
 
- HFI1_MMAP_MAGIC_MASK
 
- HFI1_MMAP_MAGIC_SHIFT
 
- HFI1_MMAP_OFFSET_MASK
 
- HFI1_MMAP_OFFSET_SHIFT
 
- HFI1_MMAP_SUBCTXT_MASK
 
- HFI1_MMAP_SUBCTXT_SHIFT
 
- HFI1_MMAP_TOKEN
 
- HFI1_MMAP_TOKEN_GET
 
- HFI1_MMAP_TOKEN_SET
 
- HFI1_MMAP_TYPE_MASK
 
- HFI1_MMAP_TYPE_SHIFT
 
- HFI1_NMINORS
 
- HFI1_NUM_VNIC_CTXT
 
- HFI1_ODR_MASK
 
- HFI1_OUI
 
- HFI1_OUI_LSB
 
- HFI1_PART_ENFORCE_IN
 
- HFI1_PART_ENFORCE_OUT
 
- HFI1_PBC_LENGTH_MASK
 
- HFI1_PKT_KERNEL_SC_INTEGRITY
 
- HFI1_PKT_TYPE_16B
 
- HFI1_PKT_TYPE_9B
 
- HFI1_PKT_USER_SC_INTEGRITY
 
- HFI1_POLL_TYPE_ANYRCV
 
- HFI1_POLL_TYPE_URGENT
 
- HFI1_PORT_GUID_INDEX
 
- HFI1_PRESENT
 
- HFI1_PSM_IOC_BASE_SEQ
 
- HFI1_PSN_CREDIT
 
- HFI1_QP_WQE_INVALID
 
- HFI1_RCVCTRL_CTXT_DIS
 
- HFI1_RCVCTRL_CTXT_ENB
 
- HFI1_RCVCTRL_INTRAVAIL_DIS
 
- HFI1_RCVCTRL_INTRAVAIL_ENB
 
- HFI1_RCVCTRL_NO_EGR_DROP_DIS
 
- HFI1_RCVCTRL_NO_EGR_DROP_ENB
 
- HFI1_RCVCTRL_NO_RHQ_DROP_DIS
 
- HFI1_RCVCTRL_NO_RHQ_DROP_ENB
 
- HFI1_RCVCTRL_ONE_PKT_EGR_DIS
 
- HFI1_RCVCTRL_ONE_PKT_EGR_ENB
 
- HFI1_RCVCTRL_PKEY_DIS
 
- HFI1_RCVCTRL_PKEY_ENB
 
- HFI1_RCVCTRL_TAILUPD_DIS
 
- HFI1_RCVCTRL_TAILUPD_ENB
 
- HFI1_RCVCTRL_TIDFLOW_DIS
 
- HFI1_RCVCTRL_TIDFLOW_ENB
 
- HFI1_RCVCTRL_URGENT_DIS
 
- HFI1_RCVCTRL_URGENT_ENB
 
- HFI1_RCVDHR_ENTSIZE_32
 
- HFI1_RCVHDR_ENTSIZE_16
 
- HFI1_RCVHDR_ENTSIZE_2
 
- HFI1_RC_H
 
- HFI1_R_TID_RSC_TIMER
 
- HFI1_R_TID_SW_PSN
 
- HFI1_R_TID_WAIT_INTERLCK
 
- HFI1_SC2VL_ATTR
 
- HFI1_SDMA_REQ_IOVCNT_MASK
 
- HFI1_SDMA_REQ_IOVCNT_SHIFT
 
- HFI1_SDMA_REQ_OPCODE_MASK
 
- HFI1_SDMA_REQ_OPCODE_SHIFT
 
- HFI1_SDMA_REQ_VERSION_MASK
 
- HFI1_SDMA_REQ_VERSION_SHIFT
 
- HFI1_SDMA_TXREQ_H
 
- HFI1_SHUTDOWN
 
- HFI1_SL2SC_ATTR
 
- HFI1_STATUS_CHIP_PRESENT
 
- HFI1_STATUS_HWERROR
 
- HFI1_STATUS_IB_CONF
 
- HFI1_STATUS_IB_READY
 
- HFI1_STATUS_INITTED
 
- HFI1_SWMAJOR_SHIFT
 
- HFI1_S_AHG_CLEAR
 
- HFI1_S_AHG_VALID
 
- HFI1_S_ANY_TID_WAIT_SEND
 
- HFI1_S_ANY_WAIT
 
- HFI1_S_ANY_WAIT_IO
 
- HFI1_S_MIN_BIT_MASK
 
- HFI1_S_TID_BUSY_SET
 
- HFI1_S_TID_RETRY_TIMER
 
- HFI1_S_TID_WAIT_INTERLCK
 
- HFI1_S_WAIT_HALT
 
- HFI1_S_WAIT_PIO_DRAIN
 
- HFI1_S_WAIT_TID_RESP
 
- HFI1_S_WAIT_TID_SPACE
 
- HFI1_TID_RDMA_H
 
- HFI1_TID_RDMA_WRITE_CNT
 
- HFI1_TRACE_MINOR
 
- HFI1_TRAFFIC_ACTIVE_THRESHOLD
 
- HFI1_USER_MINOR_BASE
 
- HFI1_USER_SWMAJOR
 
- HFI1_USER_SWMINOR
 
- HFI1_USER_SWVERSION
 
- HFI1_UVERBS_ABI_VERSION
 
- HFI1_VENDOR_IPG
 
- HFI1_VERBS_E_ATOMIC_VADDR
 
- HFI1_VERBS_H
 
- HFI1_VERBS_TXREQ_H
 
- HFI1_VL2MTU_ATTR
 
- HFI1_VNIC_GET_L4_HDR
 
- HFI1_VNIC_GET_VESWID
 
- HFI1_VNIC_L4_HDR_OFFSET
 
- HFI1_VNIC_MAX_PAD
 
- HFI1_VNIC_MAX_QUEUE
 
- HFI1_VNIC_MAX_TXQ
 
- HFI1_VNIC_RCV_Q_SIZE
 
- HFI1_VNIC_SC_OFFSET_HI
 
- HFI1_VNIC_SC_OFFSET_LOW
 
- HFI1_VNIC_SC_SHIFT
 
- HFI1_VNIC_SDMA_DESC_WTRMRK
 
- HFI1_VNIC_SDMA_Q_ACTIVE
 
- HFI1_VNIC_SDMA_Q_DEFERRED
 
- HFI1_VNIC_TXREQ_NAME_LEN
 
- HFI1_VNIC_UP
 
- HFI1_XMIT_RATE_PICO
 
- HFI1_XMIT_RATE_UNSUPPORTED
 
- HFIR
 
- HFIR_FRINT_MASK
 
- HFIR_FRINT_SHIFT
 
- HFIR_RLDCTRL
 
- HFI_ARCH_COMMON_OFFSET
 
- HFI_ARCH_OX_OFFSET
 
- HFI_BASE_GUID
 
- HFI_BUFFERFLAG_CODECCONFIG
 
- HFI_BUFFERFLAG_DATACORRUPT
 
- HFI_BUFFERFLAG_DECODEONLY
 
- HFI_BUFFERFLAG_DISCONTINUITY
 
- HFI_BUFFERFLAG_DROP_FRAME
 
- HFI_BUFFERFLAG_ENDOFFRAME
 
- HFI_BUFFERFLAG_ENDOFSUBFRAME
 
- HFI_BUFFERFLAG_EOS
 
- HFI_BUFFERFLAG_EOSEQ
 
- HFI_BUFFERFLAG_EXTRADATA
 
- HFI_BUFFERFLAG_MBAFF
 
- HFI_BUFFERFLAG_READONLY
 
- HFI_BUFFERFLAG_STARTTIME
 
- HFI_BUFFERFLAG_SYNCFRAME
 
- HFI_BUFFERFLAG_TEI
 
- HFI_BUFFERFLAG_TIMESTAMPINVALID
 
- HFI_BUFFERFLAG_VPE_YUV_601_709_CSC_CLAMP
 
- HFI_BUFFER_EXTRADATA_INPUT
 
- HFI_BUFFER_EXTRADATA_OUTPUT
 
- HFI_BUFFER_EXTRADATA_OUTPUT2
 
- HFI_BUFFER_INPUT
 
- HFI_BUFFER_INTERNAL_PERSIST
 
- HFI_BUFFER_INTERNAL_PERSIST_1
 
- HFI_BUFFER_INTERNAL_SCRATCH
 
- HFI_BUFFER_INTERNAL_SCRATCH_1
 
- HFI_BUFFER_INTERNAL_SCRATCH_2
 
- HFI_BUFFER_MODE_DYNAMIC
 
- HFI_BUFFER_MODE_RING
 
- HFI_BUFFER_MODE_STATIC
 
- HFI_BUFFER_OUTPUT
 
- HFI_BUFFER_OUTPUT2
 
- HFI_BUFFER_TYPE_MAX
 
- HFI_BUFREQ_COUNT_MIN
 
- HFI_BUFREQ_COUNT_MIN_HOST
 
- HFI_BUFREQ_HOLD_COUNT
 
- HFI_CAPABILITY_BFRAME
 
- HFI_CAPABILITY_BITRATE
 
- HFI_CAPABILITY_CP_OUTPUT2_THRESH
 
- HFI_CAPABILITY_ENC_LTR_COUNT
 
- HFI_CAPABILITY_FRAMERATE
 
- HFI_CAPABILITY_FRAME_HEIGHT
 
- HFI_CAPABILITY_FRAME_WIDTH
 
- HFI_CAPABILITY_HIER_B_NUM_ENH_LAYERS
 
- HFI_CAPABILITY_HIER_P_HYBRID_NUM_ENH_LAYERS
 
- HFI_CAPABILITY_HIER_P_NUM_ENH_LAYERS
 
- HFI_CAPABILITY_LCU_SIZE
 
- HFI_CAPABILITY_MBS_PER_FRAME
 
- HFI_CAPABILITY_MBS_PER_SECOND
 
- HFI_CAPABILITY_MBS_PER_SECOND_POWERSAVE
 
- HFI_CAPABILITY_PEAKBITRATE
 
- HFI_CAPABILITY_SCALE_X
 
- HFI_CAPABILITY_SCALE_Y
 
- HFI_CHROMA_SITE_0
 
- HFI_CHROMA_SITE_1
 
- HFI_CHROMA_SITE_2
 
- HFI_CHROMA_SITE_3
 
- HFI_CHROMA_SITE_4
 
- HFI_CHROMA_SITE_5
 
- HFI_CMD_SESSION_CONTINUE
 
- HFI_CMD_SESSION_EMPTY_BUFFER
 
- HFI_CMD_SESSION_FILL_BUFFER
 
- HFI_CMD_SESSION_FLUSH
 
- HFI_CMD_SESSION_GET_PROPERTY
 
- HFI_CMD_SESSION_GET_SEQUENCE_HEADER
 
- HFI_CMD_SESSION_LOAD_RESOURCES
 
- HFI_CMD_SESSION_PARSE_SEQUENCE_HEADER
 
- HFI_CMD_SESSION_RELEASE_BUFFERS
 
- HFI_CMD_SESSION_RELEASE_RESOURCES
 
- HFI_CMD_SESSION_RESUME
 
- HFI_CMD_SESSION_SET_BUFFERS
 
- HFI_CMD_SESSION_SET_PROPERTY
 
- HFI_CMD_SESSION_START
 
- HFI_CMD_SESSION_STOP
 
- HFI_CMD_SESSION_SUSPEND
 
- HFI_CMD_SESSION_SYNC
 
- HFI_CMD_START_OFFSET
 
- HFI_CMD_SYS_GET_PROPERTY
 
- HFI_CMD_SYS_INIT
 
- HFI_CMD_SYS_PC_PREP
 
- HFI_CMD_SYS_PING
 
- HFI_CMD_SYS_RELEASE_RESOURCE
 
- HFI_CMD_SYS_SESSION_ABORT
 
- HFI_CMD_SYS_SESSION_END
 
- HFI_CMD_SYS_SESSION_INIT
 
- HFI_CMD_SYS_SET_BUFFERS
 
- HFI_CMD_SYS_SET_PROPERTY
 
- HFI_CMD_SYS_SET_RESOURCE
 
- HFI_CMD_SYS_TEST_SSR
 
- HFI_COLOR_FORMAT_10_BIT_BASE
 
- HFI_COLOR_FORMAT_BGR565
 
- HFI_COLOR_FORMAT_BGR888
 
- HFI_COLOR_FORMAT_MONOCHROME
 
- HFI_COLOR_FORMAT_NV12
 
- HFI_COLOR_FORMAT_NV12_4x4TILE
 
- HFI_COLOR_FORMAT_NV12_UBWC
 
- HFI_COLOR_FORMAT_NV21
 
- HFI_COLOR_FORMAT_NV21_4x4TILE
 
- HFI_COLOR_FORMAT_RGB565
 
- HFI_COLOR_FORMAT_RGB888
 
- HFI_COLOR_FORMAT_RGBA8888
 
- HFI_COLOR_FORMAT_RGBA8888_UBWC
 
- HFI_COLOR_FORMAT_UBWC_BASE
 
- HFI_COLOR_FORMAT_UYVY
 
- HFI_COLOR_FORMAT_VYUY
 
- HFI_COLOR_FORMAT_YUV420_TP10
 
- HFI_COLOR_FORMAT_YUV420_TP10_UBWC
 
- HFI_COLOR_FORMAT_YUV444
 
- HFI_COLOR_FORMAT_YUYV
 
- HFI_COLOR_FORMAT_YVYU
 
- HFI_COMMAND_QUEUE
 
- HFI_CTRL_TO_HOST_DBG_Q
 
- HFI_CTRL_TO_HOST_MSG_Q
 
- HFI_DEBUG_MODE_QDSS
 
- HFI_DEBUG_MODE_QUEUE
 
- HFI_DEBUG_MSG_ERROR
 
- HFI_DEBUG_MSG_FATAL
 
- HFI_DEBUG_MSG_HIGH
 
- HFI_DEBUG_MSG_LOW
 
- HFI_DEBUG_MSG_MEDIUM
 
- HFI_DEBUG_MSG_PERF
 
- HFI_DIVX_FORMAT_4
 
- HFI_DIVX_FORMAT_5
 
- HFI_DIVX_FORMAT_6
 
- HFI_DIVX_PROFILE_HD
 
- HFI_DIVX_PROFILE_HT
 
- HFI_DIVX_PROFILE_MOBILE
 
- HFI_DIVX_PROFILE_MT
 
- HFI_DIVX_PROFILE_QMOBILE
 
- HFI_DOMAIN_BASE_COMMON
 
- HFI_DOMAIN_BASE_VDEC
 
- HFI_DOMAIN_BASE_VENC
 
- HFI_DOMAIN_BASE_VPE
 
- HFI_ERR_NONE
 
- HFI_ERR_SESSION_BAD_POINTER
 
- HFI_ERR_SESSION_BUFFERCOUNT_TOOSMALL
 
- HFI_ERR_SESSION_CMDSIZE
 
- HFI_ERR_SESSION_EMPTY_BUFFER_DONE_OUTPUT_PENDING
 
- HFI_ERR_SESSION_ENC_OVERFLOW
 
- HFI_ERR_SESSION_FATAL
 
- HFI_ERR_SESSION_INCORRECT_STATE_OPERATION
 
- HFI_ERR_SESSION_INSUFFICIENT_RESOURCES
 
- HFI_ERR_SESSION_INVALID_PARAMETER
 
- HFI_ERR_SESSION_INVALID_SCALE_FACTOR
 
- HFI_ERR_SESSION_INVALID_SESSION_ID
 
- HFI_ERR_SESSION_INVALID_STREAM_ID
 
- HFI_ERR_SESSION_SAME_STATE_OPERATION
 
- HFI_ERR_SESSION_START_CODE_NOT_FOUND
 
- HFI_ERR_SESSION_STREAM_CORRUPT
 
- HFI_ERR_SESSION_STREAM_CORRUPT_OUTPUT_STALLED
 
- HFI_ERR_SESSION_SYNC_FRAME_NOT_DETECTED
 
- HFI_ERR_SESSION_UNSUPPORTED_PROPERTY
 
- HFI_ERR_SESSION_UNSUPPORTED_SETTING
 
- HFI_ERR_SESSION_UNSUPPORTED_STREAM
 
- HFI_ERR_SESSION_UNSUPPORT_BUFFERTYPE
 
- HFI_ERR_SESSION_UNSUPPORT_CMD
 
- HFI_ERR_SESSION_UPSCALE_NOT_SUPPORTED
 
- HFI_ERR_SYS_FATAL
 
- HFI_ERR_SYS_INSUFFICIENT_RESOURCES
 
- HFI_ERR_SYS_INVALID_PARAMETER
 
- HFI_ERR_SYS_MAX_SESSIONS_REACHED
 
- HFI_ERR_SYS_SESSION_ID_OUT_OF_RANGE
 
- HFI_ERR_SYS_SESSION_IN_USE
 
- HFI_ERR_SYS_UNSUPPORTED_CODEC
 
- HFI_ERR_SYS_UNSUPPORTED_DOMAIN
 
- HFI_ERR_SYS_VERSION_MISMATCH
 
- HFI_EVENT_DATA_SEQUENCE_CHANGED_INSUFFICIENT_BUF_RESOURCES
 
- HFI_EVENT_DATA_SEQUENCE_CHANGED_SUFFICIENT_BUF_RESOURCES
 
- HFI_EVENT_RELEASE_BUFFER_REFERENCE
 
- HFI_EVENT_SESSION_ERROR
 
- HFI_EVENT_SESSION_LTRUSE_FAILED
 
- HFI_EVENT_SESSION_PROPERTY_CHANGED
 
- HFI_EVENT_SESSION_SEQUENCE_CHANGED
 
- HFI_EVENT_SYS_ERROR
 
- HFI_EXTRADATA_FRAME_BITS_INFO
 
- HFI_EXTRADATA_FRAME_QP
 
- HFI_EXTRADATA_FRAME_RATE
 
- HFI_EXTRADATA_INDEX
 
- HFI_EXTRADATA_INTERLACE_VIDEO
 
- HFI_EXTRADATA_MB_QUANTIZATION
 
- HFI_EXTRADATA_METADATA_FILLER
 
- HFI_EXTRADATA_METADATA_LTR
 
- HFI_EXTRADATA_MPEG2_SEQDISP
 
- HFI_EXTRADATA_MULTISLICE_INFO
 
- HFI_EXTRADATA_NONE
 
- HFI_EXTRADATA_NUM_CONCEALED_MB
 
- HFI_EXTRADATA_PANSCAN_WINDOW
 
- HFI_EXTRADATA_RECOVERY_POINT_SEI
 
- HFI_EXTRADATA_S3D_FRAME_PACKING
 
- HFI_EXTRADATA_STREAM_USERDATA
 
- HFI_EXTRADATA_TIMESTAMP
 
- HFI_EXTRADATA_VC1_FRAMEDISP
 
- HFI_EXTRADATA_VC1_SEQDISP
 
- HFI_F2H_MSG_ACK
 
- HFI_F2H_MSG_ERROR
 
- HFI_FLIP_HORIZONTAL
 
- HFI_FLIP_NONE
 
- HFI_FLIP_VERTICAL
 
- HFI_FLUSH_ALL
 
- HFI_FLUSH_INPUT
 
- HFI_FLUSH_OUTPUT
 
- HFI_FLUSH_OUTPUT2
 
- HFI_FRAME_NOTCODED
 
- HFI_FRAME_YUV
 
- HFI_H263_LEVEL_10
 
- HFI_H263_LEVEL_20
 
- HFI_H263_LEVEL_30
 
- HFI_H263_LEVEL_40
 
- HFI_H263_LEVEL_45
 
- HFI_H263_LEVEL_50
 
- HFI_H263_LEVEL_60
 
- HFI_H263_LEVEL_70
 
- HFI_H263_PROFILE_BASELINE
 
- HFI_H264_CABAC_MODEL_0
 
- HFI_H264_CABAC_MODEL_1
 
- HFI_H264_CABAC_MODEL_2
 
- HFI_H264_DB_MODE_ALL_BOUNDARY
 
- HFI_H264_DB_MODE_DISABLE
 
- HFI_H264_DB_MODE_SKIP_SLICE_BOUNDARY
 
- HFI_H264_ENTROPY_CABAC
 
- HFI_H264_ENTROPY_CAVLC
 
- HFI_H264_LEVEL_1
 
- HFI_H264_LEVEL_11
 
- HFI_H264_LEVEL_12
 
- HFI_H264_LEVEL_13
 
- HFI_H264_LEVEL_1b
 
- HFI_H264_LEVEL_2
 
- HFI_H264_LEVEL_21
 
- HFI_H264_LEVEL_22
 
- HFI_H264_LEVEL_3
 
- HFI_H264_LEVEL_31
 
- HFI_H264_LEVEL_32
 
- HFI_H264_LEVEL_4
 
- HFI_H264_LEVEL_41
 
- HFI_H264_LEVEL_42
 
- HFI_H264_LEVEL_5
 
- HFI_H264_LEVEL_51
 
- HFI_H264_LEVEL_52
 
- HFI_H264_PROFILE_BASELINE
 
- HFI_H264_PROFILE_CONSTRAINED_BASE
 
- HFI_H264_PROFILE_CONSTRAINED_HIGH
 
- HFI_H264_PROFILE_HIGH
 
- HFI_H264_PROFILE_MAIN
 
- HFI_H264_PROFILE_MULTIVIEW_HIGH
 
- HFI_H264_PROFILE_STEREO_HIGH
 
- HFI_H2F_MSG_BW_TABLE
 
- HFI_H2F_MSG_FW_VERSION
 
- HFI_H2F_MSG_INIT
 
- HFI_H2F_MSG_PERF_TABLE
 
- HFI_H2F_MSG_TEST
 
- HFI_HEADER_ID
 
- HFI_HEADER_SEQNUM
 
- HFI_HEADER_SIZE
 
- HFI_HEVC_LEVEL_1
 
- HFI_HEVC_LEVEL_2
 
- HFI_HEVC_LEVEL_21
 
- HFI_HEVC_LEVEL_3
 
- HFI_HEVC_LEVEL_31
 
- HFI_HEVC_LEVEL_4
 
- HFI_HEVC_LEVEL_41
 
- HFI_HEVC_LEVEL_5
 
- HFI_HEVC_LEVEL_51
 
- HFI_HEVC_LEVEL_52
 
- HFI_HEVC_LEVEL_6
 
- HFI_HEVC_LEVEL_61
 
- HFI_HEVC_LEVEL_62
 
- HFI_HEVC_PROFILE_MAIN
 
- HFI_HEVC_PROFILE_MAIN10
 
- HFI_HEVC_PROFILE_MAIN_STILL_PIC
 
- HFI_HEVC_TIER_HIGH0
 
- HFI_HEVC_TIER_MAIN
 
- HFI_HOST_TO_CTRL_CMD_Q
 
- HFI_INDEX_EXTRADATA_ASPECT_RATIO
 
- HFI_INDEX_EXTRADATA_DIGITAL_ZOOM
 
- HFI_INDEX_EXTRADATA_INPUT_CROP
 
- HFI_INDEX_EXTRADATA_OUTPUT_CROP
 
- HFI_INTERLACE_FRAME_BOTTOMFIELDFIRST
 
- HFI_INTERLACE_FRAME_PROGRESSIVE
 
- HFI_INTERLACE_FRAME_TOPFIELDFIRST
 
- HFI_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST
 
- HFI_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST
 
- HFI_INTRA_REFRESH_ADAPTIVE
 
- HFI_INTRA_REFRESH_CYCLIC
 
- HFI_INTRA_REFRESH_CYCLIC_ADAPTIVE
 
- HFI_INTRA_REFRESH_NONE
 
- HFI_INTRA_REFRESH_RANDOM
 
- HFI_LTR_MODE_DISABLE
 
- HFI_LTR_MODE_MANUAL
 
- HFI_LTR_MODE_PERIODIC
 
- HFI_MASK_QHDR_ID_TYPE
 
- HFI_MASK_QHDR_PRI_TYPE
 
- HFI_MASK_QHDR_RX_TYPE
 
- HFI_MASK_QHDR_STATUS
 
- HFI_MASK_QHDR_TX_TYPE
 
- HFI_MAX_BIAS_COEFFS
 
- HFI_MAX_LIMIT_COEFFS
 
- HFI_MAX_MATRIX_COEFFS
 
- HFI_MAX_PROFILE_COUNT
 
- HFI_MPEG2_LEVEL_H14
 
- HFI_MPEG2_LEVEL_HL
 
- HFI_MPEG2_LEVEL_LL
 
- HFI_MPEG2_LEVEL_ML
 
- HFI_MPEG2_PROFILE_422
 
- HFI_MPEG2_PROFILE_HIGH
 
- HFI_MPEG2_PROFILE_MAIN
 
- HFI_MPEG2_PROFILE_SIMPLE
 
- HFI_MPEG2_PROFILE_SNR
 
- HFI_MPEG2_PROFILE_SPATIAL
 
- HFI_MPEG4_LEVEL_0
 
- HFI_MPEG4_LEVEL_0b
 
- HFI_MPEG4_LEVEL_1
 
- HFI_MPEG4_LEVEL_2
 
- HFI_MPEG4_LEVEL_3
 
- HFI_MPEG4_LEVEL_3b
 
- HFI_MPEG4_LEVEL_4
 
- HFI_MPEG4_LEVEL_4a
 
- HFI_MPEG4_LEVEL_5
 
- HFI_MPEG4_LEVEL_6
 
- HFI_MPEG4_LEVEL_7
 
- HFI_MPEG4_LEVEL_8
 
- HFI_MPEG4_LEVEL_9
 
- HFI_MPEG4_PROFILE_ADVANCEDSIMPLE
 
- HFI_MPEG4_PROFILE_SIMPLE
 
- HFI_MSG_ACK
 
- HFI_MSG_CMD
 
- HFI_MSG_EVENT_NOTIFY
 
- HFI_MSG_ID
 
- HFI_MSG_SESSION_EMPTY_BUFFER
 
- HFI_MSG_SESSION_FILL_BUFFER
 
- HFI_MSG_SESSION_FLUSH
 
- HFI_MSG_SESSION_GET_SEQUENCE_HEADER
 
- HFI_MSG_SESSION_LOAD_RESOURCES
 
- HFI_MSG_SESSION_PARSE_SEQUENCE_HEADER
 
- HFI_MSG_SESSION_PROPERTY_INFO
 
- HFI_MSG_SESSION_RELEASE_BUFFERS
 
- HFI_MSG_SESSION_RELEASE_RESOURCES
 
- HFI_MSG_SESSION_RESUME
 
- HFI_MSG_SESSION_START
 
- HFI_MSG_SESSION_STOP
 
- HFI_MSG_SESSION_SUSPEND
 
- HFI_MSG_START_OFFSET
 
- HFI_MSG_SYS_COV
 
- HFI_MSG_SYS_DEBUG
 
- HFI_MSG_SYS_IDLE
 
- HFI_MSG_SYS_INIT
 
- HFI_MSG_SYS_PC_PREP
 
- HFI_MSG_SYS_PING_ACK
 
- HFI_MSG_SYS_PROPERTY_INFO
 
- HFI_MSG_SYS_RELEASE_RESOURCE
 
- HFI_MSG_SYS_SESSION_ABORT
 
- HFI_MSG_SYS_SESSION_END
 
- HFI_MSG_SYS_SESSION_INIT
 
- HFI_MULTI_SLICE_BY_BYTE_COUNT
 
- HFI_MULTI_SLICE_BY_MB_COUNT
 
- HFI_MULTI_SLICE_GOB
 
- HFI_MULTI_SLICE_OFF
 
- HFI_MVC_BUFFER_LAYOUT_SEQ
 
- HFI_MVC_BUFFER_LAYOUT_SIDEBYSIDE
 
- HFI_MVC_BUFFER_LAYOUT_TOP_BOTTOM
 
- HFI_NAL_FORMAT_FOUR_BYTE_LENGTH
 
- HFI_NAL_FORMAT_ONE_BYTE_LENGTH
 
- HFI_NAL_FORMAT_ONE_NAL_PER_BUFFER
 
- HFI_NAL_FORMAT_STARTCODES
 
- HFI_NAL_FORMAT_TWO_BYTE_LENGTH
 
- HFI_OUTPUT_ORDER_DECODE
 
- HFI_OUTPUT_ORDER_DISPLAY
 
- HFI_OX_BASE
 
- HFI_PICTURE_B
 
- HFI_PICTURE_I
 
- HFI_PICTURE_IDR
 
- HFI_PICTURE_P
 
- HFI_PICTURE_TYPE_B
 
- HFI_PICTURE_TYPE_I
 
- HFI_PICTURE_TYPE_IDR
 
- HFI_PICTURE_TYPE_P
 
- HFI_PRIOIRTY_MEDIUM
 
- HFI_PRIORITY_HIGH
 
- HFI_PRIORITY_LOW
 
- HFI_PROPERTY_CONFIG_BATCH_INFO
 
- HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS
 
- HFI_PROPERTY_CONFIG_FRAME_RATE
 
- HFI_PROPERTY_CONFIG_PRIORITY
 
- HFI_PROPERTY_CONFIG_REALTIME
 
- HFI_PROPERTY_CONFIG_VDEC_ENTROPY
 
- HFI_PROPERTY_CONFIG_VDEC_MB_ERROR_MAP
 
- HFI_PROPERTY_CONFIG_VDEC_MB_ERROR_MAP_REPORTING
 
- HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER
 
- HFI_PROPERTY_CONFIG_VENC_FRAME_QP
 
- HFI_PROPERTY_CONFIG_VENC_HIER_P_ENH_LAYER
 
- HFI_PROPERTY_CONFIG_VENC_IDR_PERIOD
 
- HFI_PROPERTY_CONFIG_VENC_INTRA_PERIOD
 
- HFI_PROPERTY_CONFIG_VENC_LTRPERIOD
 
- HFI_PROPERTY_CONFIG_VENC_MARKLTRFRAME
 
- HFI_PROPERTY_CONFIG_VENC_MAX_BITRATE
 
- HFI_PROPERTY_CONFIG_VENC_PERF_MODE
 
- HFI_PROPERTY_CONFIG_VENC_REQUEST_SYNC_FRAME
 
- HFI_PROPERTY_CONFIG_VENC_SLICE_SIZE
 
- HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER
 
- HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE
 
- HFI_PROPERTY_CONFIG_VENC_USELTRFRAME
 
- HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE
 
- HFI_PROPERTY_CONFIG_VPE_DEINTERLACE
 
- HFI_PROPERTY_CONFIG_VPE_OPERATIONS
 
- HFI_PROPERTY_CONFIG_VPE_OX_START
 
- HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE
 
- HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE_SUPPORTED
 
- HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL
 
- HFI_PROPERTY_PARAM_BUFFER_DISPLAY_HOLD_COUNT_ACTUAL
 
- HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL
 
- HFI_PROPERTY_PARAM_CAPABILITY_SUPPORTED
 
- HFI_PROPERTY_PARAM_CHROMA_SITE
 
- HFI_PROPERTY_PARAM_CODEC_MASK_SUPPORTED
 
- HFI_PROPERTY_PARAM_CODEC_SUPPORTED
 
- HFI_PROPERTY_PARAM_DIVX_FORMAT
 
- HFI_PROPERTY_PARAM_ERR_DETECTION_CODE_EXTRADATA
 
- HFI_PROPERTY_PARAM_EXTRA_DATA_HEADER_CONFIG
 
- HFI_PROPERTY_PARAM_FRAME_SIZE
 
- HFI_PROPERTY_PARAM_INDEX_EXTRADATA
 
- HFI_PROPERTY_PARAM_INTERLACE_FORMAT_SUPPORTED
 
- HFI_PROPERTY_PARAM_MAX_SEQUENCE_HEADER_SIZE
 
- HFI_PROPERTY_PARAM_MAX_SESSIONS_SUPPORTED
 
- HFI_PROPERTY_PARAM_MULTI_VIEW_FORMAT
 
- HFI_PROPERTY_PARAM_MVC_BUFFER_LAYOUT
 
- HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SELECT
 
- HFI_PROPERTY_PARAM_NAL_STREAM_FORMAT_SUPPORTED
 
- HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT
 
- HFI_PROPERTY_PARAM_PROFILE_LEVEL_SUPPORTED
 
- HFI_PROPERTY_PARAM_PROPERTIES_SUPPORTED
 
- HFI_PROPERTY_PARAM_S3D_FRAME_PACKING_EXTRADATA
 
- HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT
 
- HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SUPPORTED
 
- HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO
 
- HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO
 
- HFI_PROPERTY_PARAM_VDEC_AVC_SESSION_SELECT
 
- HFI_PROPERTY_PARAM_VDEC_COLOUR_SPACE
 
- HFI_PROPERTY_PARAM_VDEC_CONCEAL_COLOR
 
- HFI_PROPERTY_PARAM_VDEC_CONTINUE_DATA_TRANSFER
 
- HFI_PROPERTY_PARAM_VDEC_DISPLAY_PICTURE_BUFFER_COUNT
 
- HFI_PROPERTY_PARAM_VDEC_FRAME_ASSEMBLY
 
- HFI_PROPERTY_PARAM_VDEC_FRAME_BITS_INFO_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_FRAME_QP_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_FRAME_RATE_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_H264_ENTROPY_SWITCHING
 
- HFI_PROPERTY_PARAM_VDEC_INTERLACE_VIDEO_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_MB_QUANTIZATION
 
- HFI_PROPERTY_PARAM_VDEC_MPEG2_SEQDISP_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM
 
- HFI_PROPERTY_PARAM_VDEC_MULTI_VIEW_SELECT
 
- HFI_PROPERTY_PARAM_VDEC_NONCP_OUTPUT2
 
- HFI_PROPERTY_PARAM_VDEC_NUM_CONCEALED_MB
 
- HFI_PROPERTY_PARAM_VDEC_OUTPUT2_KEEP_ASPECT_RATIO
 
- HFI_PROPERTY_PARAM_VDEC_OUTPUT_ORDER
 
- HFI_PROPERTY_PARAM_VDEC_PANSCAN_WNDW_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_PICTURE_TYPE_DECODE
 
- HFI_PROPERTY_PARAM_VDEC_PIC_STRUCT
 
- HFI_PROPERTY_PARAM_VDEC_PIXEL_BITDEPTH
 
- HFI_PROPERTY_PARAM_VDEC_RECOVERY_POINT_SEI_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_SCS_THRESHOLD
 
- HFI_PROPERTY_PARAM_VDEC_STREAM_USERDATA_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_THUMBNAIL_MODE
 
- HFI_PROPERTY_PARAM_VDEC_TIMESTAMP_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_VC1_FRAMEDISP_EXTRADATA
 
- HFI_PROPERTY_PARAM_VDEC_VC1_SEQDISP_EXTRADATA
 
- HFI_PROPERTY_PARAM_VENC_ADVANCED
 
- HFI_PROPERTY_PARAM_VENC_ASPECT_RATIO
 
- HFI_PROPERTY_PARAM_VENC_DISABLE_RC_TIMESTAMP
 
- HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL
 
- HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL
 
- HFI_PROPERTY_PARAM_VENC_H264_GENERATE_AUDNAL
 
- HFI_PROPERTY_PARAM_VENC_H264_IDR_S3D_FRAME_PACKING_NAL
 
- HFI_PROPERTY_PARAM_VENC_H264_NAL_SVC_EXT
 
- HFI_PROPERTY_PARAM_VENC_H264_PICORDER_CNT_TYPE
 
- HFI_PROPERTY_PARAM_VENC_H264_PPS_ID
 
- HFI_PROPERTY_PARAM_VENC_H264_SPS_ID
 
- HFI_PROPERTY_PARAM_VENC_H264_VUI_BITSTREAM_RESTRC
 
- HFI_PROPERTY_PARAM_VENC_H264_VUI_TIMING_INFO
 
- HFI_PROPERTY_PARAM_VENC_HIER_B_MAX_NUM_ENH_LAYER
 
- HFI_PROPERTY_PARAM_VENC_HIER_P_HYBRID_MODE
 
- HFI_PROPERTY_PARAM_VENC_HIER_P_MAX_NUM_ENH_LAYER
 
- HFI_PROPERTY_PARAM_VENC_INITIAL_QP
 
- HFI_PROPERTY_PARAM_VENC_INTRA_REFRESH
 
- HFI_PROPERTY_PARAM_VENC_LTRMODE
 
- HFI_PROPERTY_PARAM_VENC_LTR_INFO
 
- HFI_PROPERTY_PARAM_VENC_MAX_NUM_B_FRAMES
 
- HFI_PROPERTY_PARAM_VENC_MBI_DUMPING
 
- HFI_PROPERTY_PARAM_VENC_MPEG4_AC_PREDICTION
 
- HFI_PROPERTY_PARAM_VENC_MPEG4_HEADER_EXTENSION
 
- HFI_PROPERTY_PARAM_VENC_MPEG4_SHORT_HEADER
 
- HFI_PROPERTY_PARAM_VENC_MPEG4_TIME_RESOLUTION
 
- HFI_PROPERTY_PARAM_VENC_MULTIREF_P
 
- HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_CONTROL
 
- HFI_PROPERTY_PARAM_VENC_MULTI_SLICE_INFO
 
- HFI_PROPERTY_PARAM_VENC_NUMREF
 
- HFI_PROPERTY_PARAM_VENC_OPEN_GOP
 
- HFI_PROPERTY_PARAM_VENC_PRESERVE_TEXT_QUALITY
 
- HFI_PROPERTY_PARAM_VENC_QUALITY_VS_SPEED
 
- HFI_PROPERTY_PARAM_VENC_RATE_CONTROL
 
- HFI_PROPERTY_PARAM_VENC_SESSION_QP
 
- HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE
 
- HFI_PROPERTY_PARAM_VENC_SLICE_DELIVERY_MODE
 
- HFI_PROPERTY_PARAM_VENC_VBV_HRD_BUF_SIZE
 
- HFI_PROPERTY_PARAM_VENC_VC1_PERF_CFG
 
- HFI_PROPERTY_PARAM_VENC_VIDEO_FULL_RANGE
 
- HFI_PROPERTY_PARAM_VENC_VPX_ERROR_RESILIENCE_MODE
 
- HFI_PROPERTY_PARAM_VPE_COLOR_SPACE_CONVERSION
 
- HFI_PROPERTY_PARAM_WORK_MODE
 
- HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL
 
- HFI_PROPERTY_SYS_CONFIG_COVERAGE
 
- HFI_PROPERTY_SYS_CONFIG_VCODEC_CLKFREQ
 
- HFI_PROPERTY_SYS_DEBUG_CONFIG
 
- HFI_PROPERTY_SYS_IDLE_INDICATOR
 
- HFI_PROPERTY_SYS_IMAGE_VERSION
 
- HFI_PROPERTY_SYS_RESOURCE_OCMEM_REQUIREMENT_INFO
 
- HFI_RATE_CONTROL_CBR_CFR
 
- HFI_RATE_CONTROL_CBR_VFR
 
- HFI_RATE_CONTROL_OFF
 
- HFI_RATE_CONTROL_VBR_CFR
 
- HFI_RATE_CONTROL_VBR_VFR
 
- HFI_RESOURCE_OCMEM
 
- HFI_RESPONSE_PAYLOAD_SIZE
 
- HFI_RESPONSE_QUEUE
 
- HFI_ROTATE_180
 
- HFI_ROTATE_270
 
- HFI_ROTATE_90
 
- HFI_ROTATE_NONE
 
- HFI_TEST_SSR_HW_WDOG_IRQ
 
- HFI_TEST_SSR_SW_DIV_BY_ZERO
 
- HFI_TEST_SSR_SW_ERR_FATAL
 
- HFI_TRANSITION_ALLOWED
 
- HFI_TRANSITION_DISALLOWED
 
- HFI_TRANSITION_IGNORED
 
- HFI_TRANSITION_UNDEFINED
 
- HFI_TX_TIMEOUT_MS
 
- HFI_UNUSED_PICT
 
- HFI_VC1_LEVEL_0
 
- HFI_VC1_LEVEL_1
 
- HFI_VC1_LEVEL_2
 
- HFI_VC1_LEVEL_3
 
- HFI_VC1_LEVEL_4
 
- HFI_VC1_LEVEL_HIGH
 
- HFI_VC1_LEVEL_LOW
 
- HFI_VC1_LEVEL_MEDIUM
 
- HFI_VC1_PROFILE_ADVANCED
 
- HFI_VC1_PROFILE_MAIN
 
- HFI_VC1_PROFILE_SIMPLE
 
- HFI_VENC_PERFMODE_MAX_QUALITY
 
- HFI_VENC_PERFMODE_POWER_SAVE
 
- HFI_VERSION_1XX
 
- HFI_VERSION_3XX
 
- HFI_VERSION_4XX
 
- HFI_VIDEO_ARCH_OX
 
- HFI_VIDEO_CODEC_DIVX
 
- HFI_VIDEO_CODEC_DIVX_311
 
- HFI_VIDEO_CODEC_H263
 
- HFI_VIDEO_CODEC_H264
 
- HFI_VIDEO_CODEC_HEVC
 
- HFI_VIDEO_CODEC_HEVC_HYBRID
 
- HFI_VIDEO_CODEC_MPEG1
 
- HFI_VIDEO_CODEC_MPEG2
 
- HFI_VIDEO_CODEC_MPEG4
 
- HFI_VIDEO_CODEC_SPARK
 
- HFI_VIDEO_CODEC_VC1
 
- HFI_VIDEO_CODEC_VP8
 
- HFI_VIDEO_CODEC_VP9
 
- HFI_VPX_PROFILE_ADVANCED
 
- HFI_VPX_PROFILE_SIMPLE
 
- HFI_VPX_PROFILE_VERSION_0
 
- HFI_VPX_PROFILE_VERSION_1
 
- HFI_VPX_PROFILE_VERSION_2
 
- HFI_VPX_PROFILE_VERSION_3
 
- HFLAG_20_21
 
- HFLAG_AUTO
 
- HFLAG_FENABLE
 
- HFLAG_FULL
 
- HFLAG_INIT
 
- HFLAG_LANCE
 
- HFLAG_LINKUP
 
- HFLAG_MACFULL
 
- HFLAG_NOT_A0
 
- HFLAG_PCI
 
- HFLAG_POLL
 
- HFLAG_POLLENABLE
 
- HFLAG_QUATTRO
 
- HFLAG_RXCV
 
- HFLAG_RXENABLE
 
- HFLBADDR
 
- HFLIP
 
- HFLIP_CHECK_DELAY
 
- HFLIP_IMG
 
- HFLIP_READY_DELAY
 
- HFMAX
 
- HFMIN
 
- HFNUM
 
- HFNUM_FRNUM_MASK
 
- HFNUM_FRNUM_SHIFT
 
- HFNUM_FRREM_MASK
 
- HFNUM_FRREM_SHIFT
 
- HFNUM_MAX_FRNUM
 
- HFP
 
- HFPR
 
- HFP_LEN
 
- HFP_MASK
 
- HFP_PACKET_OVERHEAD
 
- HFREF
 
- HFRMEN
 
- HFSCR_BHRB
 
- HFSCR_DSCR
 
- HFSCR_EBB
 
- HFSCR_FP
 
- HFSCR_INTR_CAUSE
 
- HFSCR_MSGP
 
- HFSCR_PM
 
- HFSCR_TAR
 
- HFSCR_TM
 
- HFSCR_VECVSX
 
- HFSC_FSC
 
- HFSC_RSC
 
- HFSC_USC
 
- HFSPLUS_ACL_EXISTS
 
- HFSPLUS_ALLOC_CNID
 
- HFSPLUS_ATTR_CNID
 
- HFSPLUS_ATTR_EXTENTS
 
- HFSPLUS_ATTR_FORK_DATA
 
- HFSPLUS_ATTR_INLINE_DATA
 
- HFSPLUS_ATTR_KEYLEN
 
- HFSPLUS_ATTR_MAX_STRLEN
 
- HFSPLUS_ATTR_TREE_NODE_SIZE
 
- HFSPLUS_BAD_CNID
 
- HFSPLUS_BTREE_HDR_NODE_RECS_COUNT
 
- HFSPLUS_BTREE_HDR_USER_BYTES
 
- HFSPLUS_CAT_CNID
 
- HFSPLUS_CAT_KEYLEN
 
- HFSPLUS_CREATING_ATTR_TREE
 
- HFSPLUS_CURRENT_VERSION
 
- HFSPLUS_DEF_CR_TYPE
 
- HFSPLUS_EMPTY_ATTR_TREE
 
- HFSPLUS_EXCH_CNID
 
- HFSPLUS_EXT_CNID
 
- HFSPLUS_EXT_DIRTY
 
- HFSPLUS_EXT_KEYLEN
 
- HFSPLUS_EXT_NEW
 
- HFSPLUS_FAILED_ATTR_TREE
 
- HFSPLUS_FILE
 
- HFSPLUS_FILE_LOCKED
 
- HFSPLUS_FILE_THREAD
 
- HFSPLUS_FILE_THREAD_EXISTS
 
- HFSPLUS_FIRSTUSER_CNID
 
- HFSPLUS_FLG_APPEND
 
- HFSPLUS_FLG_IMMUTABLE
 
- HFSPLUS_FLG_NODUMP
 
- HFSPLUS_FOLDER
 
- HFSPLUS_FOLDER_THREAD
 
- HFSPLUS_HAS_FOLDER_COUNT
 
- HFSPLUS_I
 
- HFSPLUS_INODE_SIZE
 
- HFSPLUS_INVALID_ATTR_RECORD
 
- HFSPLUS_IOC_BLESS
 
- HFSPLUS_IOC_EXT2_GETFLAGS
 
- HFSPLUS_IOC_EXT2_SETFLAGS
 
- HFSPLUS_IS_RSRC
 
- HFSPLUS_I_ALLOC_DIRTY
 
- HFSPLUS_I_ATTR_DIRTY
 
- HFSPLUS_I_CAT_DIRTY
 
- HFSPLUS_I_EXT_DIRTY
 
- HFSPLUS_I_RSRC
 
- HFSPLUS_KEY_BINARY
 
- HFSPLUS_KEY_CASEFOLDING
 
- HFSPLUS_MAX_INLINE_DATA_SIZE
 
- HFSPLUS_MAX_STRLEN
 
- HFSPLUS_MIN_THREAD_SZ
 
- HFSPLUS_MIN_VERSION
 
- HFSPLUS_NODE_MXSZ
 
- HFSPLUS_POR_CNID
 
- HFSPLUS_ROOT_CNID
 
- HFSPLUS_SB
 
- HFSPLUS_SB_CASEFOLD
 
- HFSPLUS_SB_FORCE
 
- HFSPLUS_SB_HFSX
 
- HFSPLUS_SB_NOBARRIER
 
- HFSPLUS_SB_NODECOMPOSE
 
- HFSPLUS_SB_WRITEBACKUP
 
- HFSPLUS_SECTOR_SHIFT
 
- HFSPLUS_SECTOR_SIZE
 
- HFSPLUS_START_CNID
 
- HFSPLUS_SUPER_MAGIC
 
- HFSPLUS_TREE_HEAD
 
- HFSPLUS_TYPE_DATA
 
- HFSPLUS_TYPE_RSRC
 
- HFSPLUS_VALID_ATTR_TREE
 
- HFSPLUS_VOLHEAD_SECTOR
 
- HFSPLUS_VOLHEAD_SIG
 
- HFSPLUS_VOLHEAD_SIGX
 
- HFSPLUS_VOL_INCNSTNT
 
- HFSPLUS_VOL_JOURNALED
 
- HFSPLUS_VOL_NOCACHE
 
- HFSPLUS_VOL_NODEID_REUSED
 
- HFSPLUS_VOL_SOFTLOCK
 
- HFSPLUS_VOL_SPARE_BLK
 
- HFSPLUS_VOL_UNMNT
 
- HFSPLUS_VOL_UNUSED_NODE_FIX
 
- HFSPLUS_XATTR_ACL_NAME
 
- HFSPLUS_XATTR_EXISTS
 
- HFSPLUS_XATTR_FINDER_INFO_NAME
 
- HFSP_HARDLINK_TYPE
 
- HFSP_HFSPLUS_CREATOR
 
- HFSP_HIDDENDIR_NAME
 
- HFSP_MOUNT_VERSION
 
- HFSP_SYMLINK_CREATOR
 
- HFSP_SYMLINK_TYPE
 
- HFSP_WRAPOFF_ABLKSIZE
 
- HFSP_WRAPOFF_ABLKSTART
 
- HFSP_WRAPOFF_ATTRIB
 
- HFSP_WRAPOFF_EMBEDEXT
 
- HFSP_WRAPOFF_EMBEDSIG
 
- HFSP_WRAPOFF_SIG
 
- HFSP_WRAP_ATTRIB_SLOCK
 
- HFSP_WRAP_ATTRIB_SPARED
 
- HFSP_WRAP_MAGIC
 
- HFS_ALLOC_CNID
 
- HFS_ATTR_CNID
 
- HFS_BAD_CNID
 
- HFS_BKEY
 
- HFS_BNODE_DELETED
 
- HFS_BNODE_DIRTY
 
- HFS_BNODE_ERROR
 
- HFS_BNODE_LOCK
 
- HFS_BNODE_NEW
 
- HFS_CAT_CNID
 
- HFS_CDR_DIR
 
- HFS_CDR_FIL
 
- HFS_CDR_FTH
 
- HFS_CDR_THD
 
- HFS_CREATOR
 
- HFS_DD_BLK
 
- HFS_DIR_DIR
 
- HFS_DIR_EXPFOLDER
 
- HFS_DIR_INEXPFOLDER
 
- HFS_DIR_LOCK
 
- HFS_DIR_MOUNTED
 
- HFS_DIR_THD
 
- HFS_DRVR_DESC_MAGIC
 
- HFS_EXCH_CNID
 
- HFS_EXT_CNID
 
- HFS_FIL_DIR
 
- HFS_FIL_DOPEN
 
- HFS_FIL_LOCK
 
- HFS_FIL_NOCOPY
 
- HFS_FIL_ROPEN
 
- HFS_FIL_THD
 
- HFS_FIL_USED
 
- HFS_FIRSTUSER_CNID
 
- HFS_FK_DATA
 
- HFS_FK_RSRC
 
- HFS_FLG_ALT_MDB_DIRTY
 
- HFS_FLG_BITMAP_DIRTY
 
- HFS_FLG_EXT_DIRTY
 
- HFS_FLG_EXT_NEW
 
- HFS_FLG_INITED
 
- HFS_FLG_INVISIBLE
 
- HFS_FLG_LOCKED
 
- HFS_FLG_MDB_DIRTY
 
- HFS_FLG_RSRC
 
- HFS_I
 
- HFS_IS_RSRC
 
- HFS_MAX_CAT_KEYLEN
 
- HFS_MAX_EXT_KEYLEN
 
- HFS_MAX_NAMELEN
 
- HFS_MAX_VALENCE
 
- HFS_MDB_BLK
 
- HFS_MFS_SUPER_MAGIC
 
- HFS_NAMELEN
 
- HFS_NEW_PMAP_MAGIC
 
- HFS_NODE_HEADER
 
- HFS_NODE_INDEX
 
- HFS_NODE_LEAF
 
- HFS_NODE_MAP
 
- HFS_OLD_PMAP_MAGIC
 
- HFS_PMAP_BLK
 
- HFS_POR_CNID
 
- HFS_ROOT_CNID
 
- HFS_SB
 
- HFS_SB_ATTRIB_HLOCK
 
- HFS_SB_ATTRIB_INCNSTNT
 
- HFS_SB_ATTRIB_SLOCK
 
- HFS_SB_ATTRIB_SPARED
 
- HFS_SB_ATTRIB_UNMNT
 
- HFS_SECTOR_SIZE
 
- HFS_SECTOR_SIZE_BITS
 
- HFS_SEED0__RESERVED_MASK
 
- HFS_SEED0__RESERVED__SHIFT
 
- HFS_SEED1__RESERVED_MASK
 
- HFS_SEED1__RESERVED__SHIFT
 
- HFS_SEED2__RESERVED_MASK
 
- HFS_SEED2__RESERVED__SHIFT
 
- HFS_SEED3__RESERVED_MASK
 
- HFS_SEED3__RESERVED__SHIFT
 
- HFS_START_CNID
 
- HFS_SUPER_MAGIC
 
- HFS_TREE_BIGKEYS
 
- HFS_TREE_VARIDXKEYS
 
- HFS_TYPE
 
- HFS_VALID_MODE_BITS
 
- HF_ACT_PM
 
- HF_ATSC
 
- HF_AnalogMax
 
- HF_B
 
- HF_DATA_IN
 
- HF_DK
 
- HF_DP_SAVED
 
- HF_DVBC
 
- HF_DVBC_6MHZ
 
- HF_DVBC_7MHZ
 
- HF_DVBC_8MHZ
 
- HF_DVBT
 
- HF_DVBT_6MHZ
 
- HF_DVBT_7MHZ
 
- HF_DVBT_8MHZ
 
- HF_ENABLE
 
- HF_EXT_ERR
 
- HF_FM_Radio
 
- HF_G
 
- HF_GIF_MASK
 
- HF_GUEST_MASK
 
- HF_HIF_MASK
 
- HF_HINT_IARB
 
- HF_I
 
- HF_IN_PM0
 
- HF_IN_PM1
 
- HF_IRET_MASK
 
- HF_L
 
- HF_L1
 
- HF_MN
 
- HF_NMI_MASK
 
- HF_None
 
- HF_PRT
 
- HF_REG
 
- HF_S
 
- HF_SENSE
 
- HF_SMM_INSIDE_NMI_MASK
 
- HF_SMM_MASK
 
- HF_VINTR_MASK
 
- HFilterAutoFormat
 
- HFilterCIF
 
- HFilterICON
 
- HFilterQCIF
 
- HG8BIT
 
- HGA_CONFIG_COL132
 
- HGA_CURSOR_BLINKING
 
- HGA_CURSOR_OFF
 
- HGA_CURSOR_SLOWBLINK
 
- HGA_GFX
 
- HGA_GFX_MODE_EN
 
- HGA_GFX_PAGE_EN
 
- HGA_GFX_PORT
 
- HGA_INDEX_PORT
 
- HGA_MODE_BLINK_EN
 
- HGA_MODE_GFX_PAGE1
 
- HGA_MODE_GRAPHICS
 
- HGA_MODE_PORT
 
- HGA_MODE_VIDEO_EN
 
- HGA_ROWADDR
 
- HGA_STATUS_HSYNC
 
- HGA_STATUS_PORT
 
- HGA_STATUS_VIDEO
 
- HGA_STATUS_VSYNC
 
- HGA_TXT
 
- HGA_VALUE_PORT
 
- HGC_AXI_FIFO_ERR_INFO
 
- HGC_COM_INT_MSK
 
- HGC_CQE_ECC_1B_ADDR_MSK
 
- HGC_CQE_ECC_1B_ADDR_OFF
 
- HGC_CQE_ECC_ADDR
 
- HGC_CQE_ECC_MB_ADDR_MSK
 
- HGC_CQE_ECC_MB_ADDR_OFF
 
- HGC_DFX_CFG2
 
- HGC_DQE_ECC_1B_ADDR_MSK
 
- HGC_DQE_ECC_1B_ADDR_OFF
 
- HGC_DQE_ECC_ADDR
 
- HGC_DQE_ECC_MB_ADDR_MSK
 
- HGC_DQE_ECC_MB_ADDR_OFF
 
- HGC_DQ_ECC_ADDR
 
- HGC_DQ_ECC_ADDR_BAD_MSK
 
- HGC_DQ_ECC_ADDR_BAD_OFF
 
- HGC_ECC_ERR
 
- HGC_ERR_STAT_EN
 
- HGC_GET_ITV_TIME
 
- HGC_INVLD_DQE_INFO
 
- HGC_INVLD_DQE_INFO_ABORT_MSK
 
- HGC_INVLD_DQE_INFO_ABORT_OFF
 
- HGC_INVLD_DQE_INFO_DQ_MSK
 
- HGC_INVLD_DQE_INFO_DQ_OFF
 
- HGC_INVLD_DQE_INFO_FB_CH0_MSK
 
- HGC_INVLD_DQE_INFO_FB_CH0_OFF
 
- HGC_INVLD_DQE_INFO_FB_CH3_OFF
 
- HGC_INVLD_DQE_INFO_FORCE_MSK
 
- HGC_INVLD_DQE_INFO_FORCE_OFF
 
- HGC_INVLD_DQE_INFO_IPTT_OF_MSK
 
- HGC_INVLD_DQE_INFO_IPTT_OF_OFF
 
- HGC_INVLD_DQE_INFO_OFL_MSK
 
- HGC_INVLD_DQE_INFO_OFL_OFF
 
- HGC_INVLD_DQE_INFO_PHY_MSK
 
- HGC_INVLD_DQE_INFO_PHY_OFF
 
- HGC_INVLD_DQE_INFO_SSP_ERR_MSK
 
- HGC_INVLD_DQE_INFO_SSP_ERR_OFF
 
- HGC_INVLD_DQE_INFO_TYPE_MSK
 
- HGC_INVLD_DQE_INFO_TYPE_OFF
 
- HGC_IOMB_PROC1_STATUS
 
- HGC_IOST_ECC_1B_ADDR_MSK
 
- HGC_IOST_ECC_1B_ADDR_OFF
 
- HGC_IOST_ECC_ADDR
 
- HGC_IOST_ECC_ADDR_BAD_MSK
 
- HGC_IOST_ECC_ADDR_BAD_OFF
 
- HGC_IOST_ECC_MB_ADDR_MSK
 
- HGC_IOST_ECC_MB_ADDR_OFF
 
- HGC_ITCT_ECC_1B_ADDR_MSK
 
- HGC_ITCT_ECC_1B_ADDR_OFF
 
- HGC_ITCT_ECC_ADDR
 
- HGC_ITCT_ECC_ADDR_BAD_MSK
 
- HGC_ITCT_ECC_ADDR_BAD_OFF
 
- HGC_ITCT_ECC_MB_ADDR_MSK
 
- HGC_ITCT_ECC_MB_ADDR_OFF
 
- HGC_LM_DFX_STATUS2
 
- HGC_LM_DFX_STATUS2_IOSTLIST_MSK
 
- HGC_LM_DFX_STATUS2_IOSTLIST_OFF
 
- HGC_LM_DFX_STATUS2_ITCTLIST_MSK
 
- HGC_LM_DFX_STATUS2_ITCTLIST_OFF
 
- HGC_RXM_DFX_STATUS14
 
- HGC_RXM_DFX_STATUS14_MEM0_MSK
 
- HGC_RXM_DFX_STATUS14_MEM0_OFF
 
- HGC_RXM_DFX_STATUS14_MEM1_MSK
 
- HGC_RXM_DFX_STATUS14_MEM1_OFF
 
- HGC_RXM_DFX_STATUS14_MEM2_MSK
 
- HGC_RXM_DFX_STATUS14_MEM2_OFF
 
- HGC_RXM_DFX_STATUS15
 
- HGC_RXM_DFX_STATUS15_MEM3_MSK
 
- HGC_RXM_DFX_STATUS15_MEM3_OFF
 
- HGC_SAS_TXFAIL_RETRY_CTRL
 
- HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL
 
- HGC_TRANS_TASK_CNT_LIMIT
 
- HGO_DATA_SIZE
 
- HGPCI_MAX_DATA_BYTES
 
- HGPCI_REQ_BUFFER_SIZE
 
- HGPK_GS
 
- HGPK_MODEL_A
 
- HGPK_MODEL_B
 
- HGPK_MODEL_C
 
- HGPK_MODEL_D
 
- HGPK_MODEL_PREA
 
- HGPK_MODE_GLIDESENSOR
 
- HGPK_MODE_INVALID
 
- HGPK_MODE_MOUSE
 
- HGPK_MODE_PENTABLET
 
- HGPK_PT
 
- HGSMIHOSTFLAGS_COMMANDS_PENDING
 
- HGSMIHOSTFLAGS_CURSOR_CAPABILITIES
 
- HGSMIHOSTFLAGS_HOTPLUG
 
- HGSMIHOSTFLAGS_IRQ
 
- HGSMIHOSTFLAGS_VSYNC
 
- HGSMI_BUFFER_HEADER_F_SEQ_CONTINUE
 
- HGSMI_BUFFER_HEADER_F_SEQ_END
 
- HGSMI_BUFFER_HEADER_F_SEQ_MASK
 
- HGSMI_BUFFER_HEADER_F_SEQ_SINGLE
 
- HGSMI_BUFFER_HEADER_F_SEQ_START
 
- HGSMI_CC_HOST_FLAGS_LOCATION
 
- HGSMI_CH_HGSMI
 
- HGSMI_CH_OPENGL
 
- HGSMI_CH_RESERVED
 
- HGSMI_CH_SEAMLESS
 
- HGSMI_CH_SEAMLESS2
 
- HGSMI_CH_STRING_FIRST
 
- HGSMI_CH_STRING_LAST
 
- HGSMI_CH_VBVA
 
- HGSMI_NUMBER_OF_CHANNELS
 
- HGT_DATA_SIZE
 
- HGT_NUM_HUE_AREAS
 
- HH1
 
- HH2
 
- HHA_CNT0_LOWER
 
- HHA_EVENT_CTRL
 
- HHA_EVENT_TYPE0
 
- HHA_EVTYPE_NONE
 
- HHA_INT_CLEAR
 
- HHA_INT_MASK
 
- HHA_INT_STATUS
 
- HHA_NR_COUNTERS
 
- HHA_PERF_CTRL
 
- HHA_PERF_CTRL_EN
 
- HHBM_64BIT
 
- HHBM_CONFIG_SOFT_RESET
 
- HHBM_DONE
 
- HHBM_RD_REQ
 
- HHBM_WR_REQ
 
- HHEAD_CONFIG
 
- HHEAD_SEC_INTR
 
- HHF_ARRAYS_CNT
 
- HHF_ARRAYS_LEN
 
- HHF_BIT_MASK
 
- HHF_BIT_MASK_LEN
 
- HHIER_REG
 
- HHIMR_REG
 
- HHIRQSR_REG
 
- HHISR_REG
 
- HHI_32K_CLK_CNTL
 
- HHI_AUDIO_MEM_PD_REG0
 
- HHI_AUD_CLK_CNTL
 
- HHI_AUD_CLK_CNTL2
 
- HHI_AUD_CLK_CNTL3
 
- HHI_BT656_CLK_CNTL
 
- HHI_DPLL_TOP2_I
 
- HHI_DPLL_TOP_I
 
- HHI_FIX_PLL_CNTL0
 
- HHI_FIX_PLL_CNTL1
 
- HHI_FIX_PLL_CNTL3
 
- HHI_GCLK2_AO
 
- HHI_GCLK2_MPEG0
 
- HHI_GCLK2_MPEG1
 
- HHI_GCLK2_MPEG2
 
- HHI_GCLK2_OTHER
 
- HHI_GCLK_AO
 
- HHI_GCLK_MPEG0
 
- HHI_GCLK_MPEG1
 
- HHI_GCLK_MPEG2
 
- HHI_GCLK_OTHER
 
- HHI_GCLK_OTHER2
 
- HHI_GEN_CLK_CNTL
 
- HHI_GP0_PLL_CNTL
 
- HHI_GP0_PLL_CNTL0
 
- HHI_GP0_PLL_CNTL1
 
- HHI_GP0_PLL_CNTL2
 
- HHI_GP0_PLL_CNTL3
 
- HHI_GP0_PLL_CNTL4
 
- HHI_GP0_PLL_CNTL5
 
- HHI_GP0_PLL_CNTL6
 
- HHI_GP0_PLL_STS
 
- HHI_GP1_PLL_CNTL0
 
- HHI_GP1_PLL_CNTL1
 
- HHI_GP1_PLL_CNTL2
 
- HHI_GP1_PLL_CNTL3
 
- HHI_GP1_PLL_CNTL4
 
- HHI_GP1_PLL_CNTL5
 
- HHI_GP1_PLL_CNTL6
 
- HHI_GP1_PLL_STS
 
- HHI_GP_PLL_CNTL
 
- HHI_HDCP22_CLK_CNTL
 
- HHI_HDMI_CLK_CNTL
 
- HHI_HDMI_PHY_CNTL0
 
- HHI_HDMI_PHY_CNTL1
 
- HHI_HDMI_PHY_CNTL2
 
- HHI_HDMI_PHY_CNTL3
 
- HHI_HDMI_PHY_CNTL4
 
- HHI_HDMI_PHY_CNTL5
 
- HHI_HDMI_PLL_CNTL
 
- HHI_HDMI_PLL_CNTL0
 
- HHI_HDMI_PLL_CNTL1
 
- HHI_HDMI_PLL_CNTL2
 
- HHI_HDMI_PLL_CNTL3
 
- HHI_HDMI_PLL_CNTL4
 
- HHI_HDMI_PLL_CNTL5
 
- HHI_HDMI_PLL_CNTL6
 
- HHI_HDMI_PLL_CNTL7
 
- HHI_HDMI_PLL_CNTL_EN
 
- HHI_HDMI_PLL_CNTL_I
 
- HHI_HIFI_PLL_CNTL
 
- HHI_HIFI_PLL_CNTL0
 
- HHI_HIFI_PLL_CNTL1
 
- HHI_HIFI_PLL_CNTL2
 
- HHI_HIFI_PLL_CNTL3
 
- HHI_HIFI_PLL_CNTL4
 
- HHI_HIFI_PLL_CNTL5
 
- HHI_HIFI_PLL_CNTL6
 
- HHI_HIFI_PLL_STS
 
- HHI_MALI_CLK_CNTL
 
- HHI_MEM_PD_REG0
 
- HHI_MEM_PD_REG1
 
- HHI_MIPIDSI_PHY_CLK_CNTL
 
- HHI_MIPI_CNTL0
 
- HHI_MIPI_CNTL1
 
- HHI_MIPI_CNTL2
 
- HHI_MIPI_STS
 
- HHI_MPEG_CLK_CNTL
 
- HHI_MPLL3_CNTL0
 
- HHI_MPLL3_CNTL1
 
- HHI_MPLL_CNTL
 
- HHI_MPLL_CNTL0
 
- HHI_MPLL_CNTL1
 
- HHI_MPLL_CNTL10
 
- HHI_MPLL_CNTL2
 
- HHI_MPLL_CNTL3
 
- HHI_MPLL_CNTL4
 
- HHI_MPLL_CNTL5
 
- HHI_MPLL_CNTL6
 
- HHI_MPLL_CNTL7
 
- HHI_MPLL_CNTL8
 
- HHI_MPLL_CNTL9
 
- HHI_NAND_CLK_CNTL
 
- HHI_NANOQ_MEM_PD_REG0
 
- HHI_NANOQ_MEM_PD_REG1
 
- HHI_PCIE_PLL_CNTL
 
- HHI_PCIE_PLL_CNTL0
 
- HHI_PCIE_PLL_CNTL1
 
- HHI_PCIE_PLL_CNTL2
 
- HHI_PCIE_PLL_CNTL3
 
- HHI_PCIE_PLL_CNTL4
 
- HHI_PCIE_PLL_CNTL5
 
- HHI_PCIE_PLL_CNTL6
 
- HHI_PCIE_PLL_STS
 
- HHI_PCM_CLK_CNTL
 
- HHI_PLL_TOP_MISC
 
- HHI_SAR_CLK_CNTL
 
- HHI_SD_EMMC_CLK_CNTL
 
- HHI_SPICC_CLK_CNTL
 
- HHI_SPICC_HCLK_CNTL
 
- HHI_SYS1_PLL_CNTL0
 
- HHI_SYS1_PLL_CNTL1
 
- HHI_SYS1_PLL_CNTL2
 
- HHI_SYS1_PLL_CNTL3
 
- HHI_SYS1_PLL_CNTL4
 
- HHI_SYS1_PLL_CNTL5
 
- HHI_SYS1_PLL_CNTL6
 
- HHI_SYS_CPUB_CLK_CNTL
 
- HHI_SYS_CPUB_CLK_CNTL1
 
- HHI_SYS_CPU_CLK_CNTL0
 
- HHI_SYS_CPU_CLK_CNTL1
 
- HHI_SYS_CPU_CLK_CNTL2
 
- HHI_SYS_CPU_CLK_CNTL3
 
- HHI_SYS_CPU_CLK_CNTL4
 
- HHI_SYS_CPU_CLK_CNTL5
 
- HHI_SYS_CPU_CLK_CNTL6
 
- HHI_SYS_CPU_RESET_CNTL
 
- HHI_SYS_OSCIN_CNTL
 
- HHI_SYS_PLL_CNTL
 
- HHI_SYS_PLL_CNTL0
 
- HHI_SYS_PLL_CNTL1
 
- HHI_SYS_PLL_CNTL2
 
- HHI_SYS_PLL_CNTL3
 
- HHI_SYS_PLL_CNTL4
 
- HHI_SYS_PLL_CNTL5
 
- HHI_SYS_PLL_CNTL6
 
- HHI_SYS_PLL_STS
 
- HHI_TIMER90K
 
- HHI_TS_CLK_CNTL
 
- HHI_USB_CLK_CNTL
 
- HHI_VAPBCLK_CNTL
 
- HHI_VDAC_CNTL0
 
- HHI_VDAC_CNTL0_G12A
 
- HHI_VDAC_CNTL1
 
- HHI_VDAC_CNTL1_G12A
 
- HHI_VDEC2_CLK_CNTL
 
- HHI_VDEC3_CLK_CNTL
 
- HHI_VDEC4_CLK_CNTL
 
- HHI_VDEC_CLK_CNTL
 
- HHI_VDIN_MEAS_CLK_CNTL
 
- HHI_VID_CLK_CNTL
 
- HHI_VID_CLK_CNTL2
 
- HHI_VID_CLK_DIV
 
- HHI_VID_DIVIDER_CNTL
 
- HHI_VID_LOCK_CLK_CNTL
 
- HHI_VID_PLL_CLK_DIV
 
- HHI_VID_PLL_CNTL
 
- HHI_VID_PLL_CNTL2
 
- HHI_VIID_CLK_CNTL
 
- HHI_VIID_CLK_DIV
 
- HHI_VPU_CLKB_CNTL
 
- HHI_VPU_CLKC_CNTL
 
- HHI_VPU_CLK_CNTL
 
- HHI_VPU_MEM_PD_REG0
 
- HHI_VPU_MEM_PD_REG1
 
- HHI_VPU_MEM_PD_REG2
 
- HHI_VPU_MEM_PD_REG3
 
- HHI_VPU_MEM_PD_REG4
 
- HHI_XTAL_DIVN_CNTL
 
- HHT
 
- HH_DATA_ALIGN
 
- HH_DATA_MOD
 
- HH_DATA_OFF
 
- HH_FLOWS_CNT
 
- HI
 
- HI2C_EDID_READ
 
- HI2C_ENABLE_TRANSACTION
 
- HI2C_HDCP_READ
 
- HI2C_HDCP_RI_READ
 
- HI2C_HDCP_WRITE
 
- HI2C_READ_CONTINUE
 
- HI3110_AFTER_SUSPEND_DOWN
 
- HI3110_AFTER_SUSPEND_POWER
 
- HI3110_AFTER_SUSPEND_RESTART
 
- HI3110_AFTER_SUSPEND_UP
 
- HI3110_BTR0_BRP_SHIFT
 
- HI3110_BTR0_SJW_SHIFT
 
- HI3110_BTR1_SAMP_1PERBIT
 
- HI3110_BTR1_SAMP_3PERBIT
 
- HI3110_BTR1_TSEG1_SHIFT
 
- HI3110_BTR1_TSEG2_SHIFT
 
- HI3110_CAN_FRAME_MAX_BITS
 
- HI3110_CAN_MAX_DATA_LEN
 
- HI3110_CTRL0_INIT_MODE
 
- HI3110_CTRL0_LOOPBACK_MODE
 
- HI3110_CTRL0_MODE_MASK
 
- HI3110_CTRL0_MONITOR_MODE
 
- HI3110_CTRL0_NORMAL_MODE
 
- HI3110_CTRL0_SLEEP_MODE
 
- HI3110_CTRL1_TXEN
 
- HI3110_EFF_FLAGS
 
- HI3110_ERR_ACKERR
 
- HI3110_ERR_BITERR
 
- HI3110_ERR_BUSOFF
 
- HI3110_ERR_CRCERR
 
- HI3110_ERR_FRMERR
 
- HI3110_ERR_PASSIVE_MASK
 
- HI3110_ERR_PROTOCOL_MASK
 
- HI3110_ERR_RXERRP
 
- HI3110_ERR_STUFERR
 
- HI3110_ERR_TXERRP
 
- HI3110_FIFO_EXT_DATA_OFF
 
- HI3110_FIFO_EXT_DLC_OFF
 
- HI3110_FIFO_ID_OFF
 
- HI3110_FIFO_STD_DATA_OFF
 
- HI3110_FIFO_STD_DLC_OFF
 
- HI3110_FIFO_TAG_OFF
 
- HI3110_FIFO_WOTIME_DAT_OFF
 
- HI3110_FIFO_WOTIME_DLC_OFF
 
- HI3110_FIFO_WOTIME_ID_OFF
 
- HI3110_FIFO_WOTIME_ID_RTR
 
- HI3110_FIFO_WOTIME_TAG_IDE
 
- HI3110_FIFO_WOTIME_TAG_OFF
 
- HI3110_INT_BUSERR
 
- HI3110_INT_F0MESS
 
- HI3110_INT_F1MESS
 
- HI3110_INT_MCHG
 
- HI3110_INT_RXFIFO
 
- HI3110_INT_RXTMP
 
- HI3110_INT_TXCPLT
 
- HI3110_INT_WAKEUP
 
- HI3110_MASTER_RESET
 
- HI3110_OST_DELAY_MS
 
- HI3110_READ_BTR0
 
- HI3110_READ_BTR1
 
- HI3110_READ_CTRL0
 
- HI3110_READ_CTRL1
 
- HI3110_READ_ERR
 
- HI3110_READ_FIFO_WOTIME
 
- HI3110_READ_INTF
 
- HI3110_READ_MESSTAT
 
- HI3110_READ_REC
 
- HI3110_READ_STATF
 
- HI3110_READ_TEC
 
- HI3110_RX_BUF_LEN
 
- HI3110_STAT_BUSOFF
 
- HI3110_STAT_ERRP
 
- HI3110_STAT_ERRW
 
- HI3110_STAT_RXFMTY
 
- HI3110_STAT_TXMTY
 
- HI3110_TX_ECHO_SKB_MAX
 
- HI3110_TX_EXT_BUF_LEN
 
- HI3110_TX_STD_BUF_LEN
 
- HI3110_WRITE_BTR0
 
- HI3110_WRITE_BTR1
 
- HI3110_WRITE_CTRL0
 
- HI3110_WRITE_CTRL1
 
- HI3110_WRITE_FIFO
 
- HI3110_WRITE_INTE
 
- HI3516CV300_APB_CLK
 
- HI3516CV300_CRG_NR_CLKS
 
- HI3516CV300_DMAC_CLK
 
- HI3516CV300_ETH_CLK
 
- HI3516CV300_ETH_MACIF_CLK
 
- HI3516CV300_FIXED_100M
 
- HI3516CV300_FIXED_148P5M
 
- HI3516CV300_FIXED_198M
 
- HI3516CV300_FIXED_24M
 
- HI3516CV300_FIXED_297M
 
- HI3516CV300_FIXED_3M
 
- HI3516CV300_FIXED_49P5
 
- HI3516CV300_FIXED_50M
 
- HI3516CV300_FIXED_6M
 
- HI3516CV300_FIXED_83P3M
 
- HI3516CV300_FIXED_99M
 
- HI3516CV300_FMC_CLK
 
- HI3516CV300_FMC_MUX
 
- HI3516CV300_INNER_CLK_OFFSET
 
- HI3516CV300_MMC0_CLK
 
- HI3516CV300_MMC0_MUX
 
- HI3516CV300_MMC1_CLK
 
- HI3516CV300_MMC1_MUX
 
- HI3516CV300_MMC2_CLK
 
- HI3516CV300_MMC2_MUX
 
- HI3516CV300_MMC3_CLK
 
- HI3516CV300_MMC3_MUX
 
- HI3516CV300_PWM_CLK
 
- HI3516CV300_PWM_MUX
 
- HI3516CV300_SPI0_CLK
 
- HI3516CV300_SPI1_CLK
 
- HI3516CV300_SYSCTRL_NR_CLKS
 
- HI3516CV300_UART0_CLK
 
- HI3516CV300_UART1_CLK
 
- HI3516CV300_UART2_CLK
 
- HI3516CV300_UART_MUX
 
- HI3516CV300_USB2_BUS_CLK
 
- HI3516CV300_USB2_HST_PHY_CLK
 
- HI3516CV300_USB2_OHCI12M_CLK
 
- HI3516CV300_USB2_OHCI48M_CLK
 
- HI3516CV300_USB2_OTG_UTMI_CLK
 
- HI3516CV300_USB2_PHY_CLK
 
- HI3516CV300_USB2_UTMI0_CLK
 
- HI3516CV300_WDT_CLK
 
- HI3519_DMA_CLK
 
- HI3519_ETH_MACIF_CLK
 
- HI3519_ETH_MAC_CLK
 
- HI3519_ETH_PHY_CLK
 
- HI3519_FIXED_125M
 
- HI3519_FIXED_150M
 
- HI3519_FIXED_200M
 
- HI3519_FIXED_24M
 
- HI3519_FIXED_250M
 
- HI3519_FIXED_300M
 
- HI3519_FIXED_400M
 
- HI3519_FIXED_50M
 
- HI3519_FIXED_75M
 
- HI3519_FMC_CLK
 
- HI3519_FMC_MUX
 
- HI3519_INNER_CLK_OFFSET
 
- HI3519_IR_CLK
 
- HI3519_NR_CLKS
 
- HI3519_PWM_CLK
 
- HI3519_SPI0_CLK
 
- HI3519_SPI1_CLK
 
- HI3519_SPI2_CLK
 
- HI3519_UART0_CLK
 
- HI3519_UART1_CLK
 
- HI3519_UART2_CLK
 
- HI3519_UART3_CLK
 
- HI3519_UART4_CLK
 
- HI3519_USB2_BUS_CLK
 
- HI3519_USB2_PORT_CLK
 
- HI3519_USB3_CLK
 
- HI3620_ACP_CLK
 
- HI3620_CFGAXI_DIV
 
- HI3620_CTRL
 
- HI3620_DDRC_PER_CLK
 
- HI3620_DMAC_CLK
 
- HI3620_DPHY0_CLK
 
- HI3620_DPHY1_CLK
 
- HI3620_DPHY2_CLK
 
- HI3620_EDC0_MUX
 
- HI3620_EDC1_MUX
 
- HI3620_G2D_MUX
 
- HI3620_GPIOCLK0
 
- HI3620_GPIOCLK1
 
- HI3620_GPIOCLK10
 
- HI3620_GPIOCLK11
 
- HI3620_GPIOCLK12
 
- HI3620_GPIOCLK13
 
- HI3620_GPIOCLK14
 
- HI3620_GPIOCLK15
 
- HI3620_GPIOCLK16
 
- HI3620_GPIOCLK17
 
- HI3620_GPIOCLK18
 
- HI3620_GPIOCLK19
 
- HI3620_GPIOCLK2
 
- HI3620_GPIOCLK20
 
- HI3620_GPIOCLK21
 
- HI3620_GPIOCLK3
 
- HI3620_GPIOCLK4
 
- HI3620_GPIOCLK5
 
- HI3620_GPIOCLK6
 
- HI3620_GPIOCLK7
 
- HI3620_GPIOCLK8
 
- HI3620_GPIOCLK9
 
- HI3620_HSIC_DIV
 
- HI3620_I2CCLK0
 
- HI3620_I2CCLK1
 
- HI3620_I2CCLK2
 
- HI3620_I2CCLK3
 
- HI3620_KPC_CLK
 
- HI3620_LDI0_MUX
 
- HI3620_LDI1_MUX
 
- HI3620_MCU_CLK
 
- HI3620_MMC1_DIV
 
- HI3620_MMC1_MUX
 
- HI3620_MMC1_MUX2
 
- HI3620_MMC2_DIV
 
- HI3620_MMC2_MUX
 
- HI3620_MMC3_DIV
 
- HI3620_MMC3_MUX
 
- HI3620_MMC_CIUCLK1
 
- HI3620_MMC_CIUCLK2
 
- HI3620_MMC_CIUCLK3
 
- HI3620_MMC_CLK1
 
- HI3620_MMC_CLK2
 
- HI3620_MMC_CLK3
 
- HI3620_NONE_CLOCK
 
- HI3620_NR_CLKS
 
- HI3620_OSC26M
 
- HI3620_OSC32K
 
- HI3620_PCLK
 
- HI3620_PLL_ARM0
 
- HI3620_PLL_ARM1
 
- HI3620_PLL_GPU
 
- HI3620_PLL_HDMI
 
- HI3620_PLL_PERI
 
- HI3620_PLL_USB
 
- HI3620_PWM0_MUX
 
- HI3620_PWM1_MUX
 
- HI3620_PWMCLK0
 
- HI3620_PWMCLK1
 
- HI3620_RCLK_CFGAXI
 
- HI3620_RCLK_HSIC
 
- HI3620_RCLK_PICO
 
- HI3620_RCLK_TCXO
 
- HI3620_RTCCLK
 
- HI3620_SAXI_MUX
 
- HI3620_SCI_CLK
 
- HI3620_SD_CIUCLK
 
- HI3620_SD_CLK
 
- HI3620_SD_DIV
 
- HI3620_SD_MUX
 
- HI3620_SHAREAXI_DIV
 
- HI3620_SPI0_MUX
 
- HI3620_SPI1_MUX
 
- HI3620_SPI2_MUX
 
- HI3620_SPICLK0
 
- HI3620_SPICLK1
 
- HI3620_SPICLK2
 
- HI3620_SYSCTRL_PHYS_BASE
 
- HI3620_SYSCTRL_VIRT_BASE
 
- HI3620_TIMER0_MUX
 
- HI3620_TIMER1_MUX
 
- HI3620_TIMER2_MUX
 
- HI3620_TIMER3_MUX
 
- HI3620_TIMER4_MUX
 
- HI3620_TIMER5_MUX
 
- HI3620_TIMER6_MUX
 
- HI3620_TIMER7_MUX
 
- HI3620_TIMER8_MUX
 
- HI3620_TIMER9_MUX
 
- HI3620_TIMERCLK01
 
- HI3620_TIMERCLK23
 
- HI3620_TIMERCLK45
 
- HI3620_TIMERCLK67
 
- HI3620_TIMERCLK89
 
- HI3620_TIMER_RCLK01
 
- HI3620_TIMER_RCLK23
 
- HI3620_UART0_MUX
 
- HI3620_UART1_MUX
 
- HI3620_UART2_MUX
 
- HI3620_UART3_MUX
 
- HI3620_UART4_MUX
 
- HI3620_UARTCLK0
 
- HI3620_UARTCLK1
 
- HI3620_UARTCLK2
 
- HI3620_UARTCLK3
 
- HI3620_UARTCLK4
 
- HI3620_USB2DVC_CLK
 
- HI3620_USBPHY_CLK
 
- HI3620_VDEC_MUX
 
- HI3620_VENC_MUX
 
- HI3620_VPP_MUX
 
- HI3660_ACLK_DIV_MMBUF
 
- HI3660_ACLK_GATE_DSS
 
- HI3660_ACLK_GATE_PCIE
 
- HI3660_ACLK_GATE_USB3OTG
 
- HI3660_ACLK_MUX_MMBUF
 
- HI3660_AUTODIV_EMMC0BUS
 
- HI3660_AUTODIV_SYSBUS
 
- HI3660_BIG_SENSOR
 
- HI3660_CLKIN_REF
 
- HI3660_CLKIN_SYS
 
- HI3660_CLK_320M_PLL_GT
 
- HI3660_CLK_480M
 
- HI3660_CLK_A53HPM_ANDGT
 
- HI3660_CLK_ABB_USB
 
- HI3660_CLK_ANDGT_EDC0
 
- HI3660_CLK_ANDGT_LDI0
 
- HI3660_CLK_ANDGT_LDI1
 
- HI3660_CLK_ANDGT_MMC
 
- HI3660_CLK_ANDGT_SD
 
- HI3660_CLK_ANDGT_SDIO
 
- HI3660_CLK_ANDGT_SPI
 
- HI3660_CLK_ANDGT_UART0
 
- HI3660_CLK_ANDGT_UART1
 
- HI3660_CLK_ANDGT_UARTH
 
- HI3660_CLK_ANDGT_VDEC
 
- HI3660_CLK_ANDGT_VENC
 
- HI3660_CLK_ANGT_ISP_SNCLK
 
- HI3660_CLK_AOMM_ANDGT
 
- HI3660_CLK_DIV_320M
 
- HI3660_CLK_DIV_A53
 
- HI3660_CLK_DIV_AOBUS
 
- HI3660_CLK_DIV_AOMM
 
- HI3660_CLK_DIV_CFGBUS
 
- HI3660_CLK_DIV_EDC0
 
- HI3660_CLK_DIV_I2C
 
- HI3660_CLK_DIV_IOPERI
 
- HI3660_CLK_DIV_ISP_SNCLK
 
- HI3660_CLK_DIV_LDI0
 
- HI3660_CLK_DIV_LDI1
 
- HI3660_CLK_DIV_MMC
 
- HI3660_CLK_DIV_MMC0BUS
 
- HI3660_CLK_DIV_MMC1BUS
 
- HI3660_CLK_DIV_PCIEPHY
 
- HI3660_CLK_DIV_SD
 
- HI3660_CLK_DIV_SDIO
 
- HI3660_CLK_DIV_SPI
 
- HI3660_CLK_DIV_SYSBUS
 
- HI3660_CLK_DIV_UART0
 
- HI3660_CLK_DIV_UART1
 
- HI3660_CLK_DIV_UARTH
 
- HI3660_CLK_DIV_UFSPERI
 
- HI3660_CLK_DIV_UFSPHY
 
- HI3660_CLK_DIV_VDEC
 
- HI3660_CLK_DIV_VENC
 
- HI3660_CLK_DIV_VIVOBUS
 
- HI3660_CLK_FACTOR_MMC
 
- HI3660_CLK_FAC_ISP_SNCLK
 
- HI3660_CLK_FLL_MMBUF_ANDGT
 
- HI3660_CLK_FLL_SRC
 
- HI3660_CLK_GATE_AOMM
 
- HI3660_CLK_GATE_DMAC
 
- HI3660_CLK_GATE_DSS_AXI_MM
 
- HI3660_CLK_GATE_EDC0
 
- HI3660_CLK_GATE_I2C0
 
- HI3660_CLK_GATE_I2C1
 
- HI3660_CLK_GATE_I2C2
 
- HI3660_CLK_GATE_I2C3
 
- HI3660_CLK_GATE_I2C4
 
- HI3660_CLK_GATE_I2C6
 
- HI3660_CLK_GATE_I2C7
 
- HI3660_CLK_GATE_ISP_SNCLK0
 
- HI3660_CLK_GATE_ISP_SNCLK1
 
- HI3660_CLK_GATE_ISP_SNCLK2
 
- HI3660_CLK_GATE_LDI0
 
- HI3660_CLK_GATE_LDI1
 
- HI3660_CLK_GATE_PCIEAUX
 
- HI3660_CLK_GATE_PCIEPHY_GT
 
- HI3660_CLK_GATE_SD
 
- HI3660_CLK_GATE_SDIO0
 
- HI3660_CLK_GATE_SPI0
 
- HI3660_CLK_GATE_SPI1
 
- HI3660_CLK_GATE_SPI2
 
- HI3660_CLK_GATE_SPI3
 
- HI3660_CLK_GATE_SPI4
 
- HI3660_CLK_GATE_TXDPHY0_CFG
 
- HI3660_CLK_GATE_TXDPHY0_REF
 
- HI3660_CLK_GATE_TXDPHY1_CFG
 
- HI3660_CLK_GATE_TXDPHY1_REF
 
- HI3660_CLK_GATE_UART1
 
- HI3660_CLK_GATE_UART2
 
- HI3660_CLK_GATE_UART4
 
- HI3660_CLK_GATE_UART5
 
- HI3660_CLK_GATE_UFSIO_REF
 
- HI3660_CLK_GATE_UFSPHY_CFG
 
- HI3660_CLK_GATE_UFSPHY_GT
 
- HI3660_CLK_GATE_UFS_SUBSYS
 
- HI3660_CLK_GATE_VDEC
 
- HI3660_CLK_GATE_VENC
 
- HI3660_CLK_GATE_VIVOBUS
 
- HI3660_CLK_I2C0_IOMCU
 
- HI3660_CLK_I2C1_IOMCU
 
- HI3660_CLK_I2C2_IOMCU
 
- HI3660_CLK_I2C6_IOMCU
 
- HI3660_CLK_INV
 
- HI3660_CLK_IOMCU_PERI0
 
- HI3660_CLK_MMBUF_PLL_ANDGT
 
- HI3660_CLK_MUX_320M
 
- HI3660_CLK_MUX_A53HPM
 
- HI3660_CLK_MUX_EDC0
 
- HI3660_CLK_MUX_I2C
 
- HI3660_CLK_MUX_IOPERI
 
- HI3660_CLK_MUX_ISP_SNCLK
 
- HI3660_CLK_MUX_LDI0
 
- HI3660_CLK_MUX_LDI1
 
- HI3660_CLK_MUX_MMC_PLL
 
- HI3660_CLK_MUX_SDIO_PLL
 
- HI3660_CLK_MUX_SDIO_SYS
 
- HI3660_CLK_MUX_SD_PLL
 
- HI3660_CLK_MUX_SD_SYS
 
- HI3660_CLK_MUX_SPI
 
- HI3660_CLK_MUX_SYSBUS
 
- HI3660_CLK_MUX_UART0
 
- HI3660_CLK_MUX_UART1
 
- HI3660_CLK_MUX_UARTH
 
- HI3660_CLK_MUX_VDEC
 
- HI3660_CLK_MUX_VENC
 
- HI3660_CLK_MUX_VIVOBUS
 
- HI3660_CLK_PPLL0
 
- HI3660_CLK_PPLL1
 
- HI3660_CLK_PPLL2
 
- HI3660_CLK_PPLL3
 
- HI3660_CLK_SCPLL
 
- HI3660_CLK_STUB_CLUSTER0
 
- HI3660_CLK_STUB_CLUSTER1
 
- HI3660_CLK_STUB_DDR
 
- HI3660_CLK_STUB_GPU
 
- HI3660_CLK_STUB_NUM
 
- HI3660_CLK_SW_MMBUF
 
- HI3660_CLK_SYS_MMBUF_ANDGT
 
- HI3660_CLK_UART0_DBG
 
- HI3660_CLK_UART6
 
- HI3660_CLK_VIVOBUS_ANDGT
 
- HI3660_FACTOR_UART3
 
- HI3660_G3D_SENSOR
 
- HI3660_GATE_ABB_192
 
- HI3660_GATE_UFS_TCXO_EN
 
- HI3660_GATE_USB_TCXO_EN
 
- HI3660_HCLK_GATE_SD
 
- HI3660_HCLK_GATE_SDIO0
 
- HI3660_INT_CLR
 
- HI3660_INT_EN
 
- HI3660_LAG
 
- HI3660_LITTLE_SENSOR
 
- HI3660_MODEM_SENSOR
 
- HI3660_OFFSET
 
- HI3660_OSC19M
 
- HI3660_OSC32K
 
- HI3660_PCIEPHY_REF
 
- HI3660_PCLK
 
- HI3660_PCLK_AO_GPIO0
 
- HI3660_PCLK_AO_GPIO1
 
- HI3660_PCLK_AO_GPIO2
 
- HI3660_PCLK_AO_GPIO3
 
- HI3660_PCLK_AO_GPIO4
 
- HI3660_PCLK_AO_GPIO5
 
- HI3660_PCLK_AO_GPIO6
 
- HI3660_PCLK_DIV_MMBUF
 
- HI3660_PCLK_GATE_DSI0
 
- HI3660_PCLK_GATE_DSI1
 
- HI3660_PCLK_GATE_DSS
 
- HI3660_PCLK_GATE_MMBUF
 
- HI3660_PCLK_GATE_PCIE_PHY
 
- HI3660_PCLK_GATE_PCIE_SYS
 
- HI3660_PCLK_GPIO0
 
- HI3660_PCLK_GPIO1
 
- HI3660_PCLK_GPIO10
 
- HI3660_PCLK_GPIO11
 
- HI3660_PCLK_GPIO12
 
- HI3660_PCLK_GPIO13
 
- HI3660_PCLK_GPIO14
 
- HI3660_PCLK_GPIO15
 
- HI3660_PCLK_GPIO16
 
- HI3660_PCLK_GPIO17
 
- HI3660_PCLK_GPIO18
 
- HI3660_PCLK_GPIO19
 
- HI3660_PCLK_GPIO2
 
- HI3660_PCLK_GPIO20
 
- HI3660_PCLK_GPIO21
 
- HI3660_PCLK_GPIO3
 
- HI3660_PCLK_GPIO4
 
- HI3660_PCLK_GPIO5
 
- HI3660_PCLK_GPIO6
 
- HI3660_PCLK_GPIO7
 
- HI3660_PCLK_GPIO8
 
- HI3660_PCLK_GPIO9
 
- HI3660_PCLK_MMBUF_ANDGT
 
- HI3660_PERI_VOLT_HOLD
 
- HI3660_STUB_CLOCK_DATA
 
- HI3660_TEMP
 
- HI3660_TEMP_BASE
 
- HI3660_TEMP_LAG
 
- HI3660_TEMP_STEP
 
- HI3660_TH
 
- HI3660_USB_DEFAULT_PHY_PARAM
 
- HI3660_VENC_VOLT_HOLD
 
- HI3670_ABB_AUDIO_EN0
 
- HI3670_ABB_AUDIO_EN1
 
- HI3670_ABB_AUDIO_GT_EN0
 
- HI3670_ABB_AUDIO_GT_EN1
 
- HI3670_ACLK_DIV_MMBUF
 
- HI3670_ACLK_GATE_ASC
 
- HI3670_ACLK_GATE_DISP_NOC_SUBSYS
 
- HI3670_ACLK_GATE_DSS
 
- HI3670_ACLK_GATE_NOC_DSS
 
- HI3670_ACLK_GATE_PCIE
 
- HI3670_ACLK_GATE_USB3DVFS
 
- HI3670_AUTODIV_DMABUS
 
- HI3670_AUTODIV_EMMC0BUS
 
- HI3670_AUTODIV_SYSBUS
 
- HI3670_CLKANDGT_ASP_SUBSYS_PERI
 
- HI3670_CLKDIV_DP_AUDIO_PLL_AO
 
- HI3670_CLKGT_DP_AUDIO_PLL_AO
 
- HI3670_CLKIN_REF
 
- HI3670_CLKIN_SYS
 
- HI3670_CLK_320M_PLL_GT
 
- HI3670_CLK_480M
 
- HI3670_CLK_A53HPM_ANDGT
 
- HI3670_CLK_ANDGT_EDC0
 
- HI3670_CLK_ANDGT_ICS
 
- HI3670_CLK_ANDGT_IOPERI
 
- HI3670_CLK_ANDGT_LDI0
 
- HI3670_CLK_ANDGT_LDI1
 
- HI3670_CLK_ANDGT_OUT0
 
- HI3670_CLK_ANDGT_OUT1
 
- HI3670_CLK_ANDGT_PCIEAXI
 
- HI3670_CLK_ANDGT_PTP
 
- HI3670_CLK_ANDGT_RXDPHY
 
- HI3670_CLK_ANDGT_SD
 
- HI3670_CLK_ANDGT_SDIO
 
- HI3670_CLK_ANDGT_SPI
 
- HI3670_CLK_ANDGT_UART0
 
- HI3670_CLK_ANDGT_UARTH
 
- HI3670_CLK_ANDGT_UARTL
 
- HI3670_CLK_ANDGT_VDEC
 
- HI3670_CLK_ANDGT_VENC
 
- HI3670_CLK_ANGT_ASP_SUBSYS
 
- HI3670_CLK_ASP_SUBSYS_PERI_DIV
 
- HI3670_CLK_CCI400_BYPASS
 
- HI3670_CLK_CSI_TRANS_GT
 
- HI3670_CLK_DIV_320M
 
- HI3670_CLK_DIV_A53HPM
 
- HI3670_CLK_DIV_AOBUS
 
- HI3670_CLK_DIV_AO_ASP
 
- HI3670_CLK_DIV_AO_ASP_GT
 
- HI3670_CLK_DIV_ASP_SUBSYS
 
- HI3670_CLK_DIV_CFGBUS
 
- HI3670_CLK_DIV_CLKOUT0_PLL
 
- HI3670_CLK_DIV_CLKOUT0_TCXO
 
- HI3670_CLK_DIV_CLKOUT1_PLL
 
- HI3670_CLK_DIV_CLKOUT1_TCXO
 
- HI3670_CLK_DIV_CSI_TRANS
 
- HI3670_CLK_DIV_DSI_TRANS
 
- HI3670_CLK_DIV_EDC0
 
- HI3670_CLK_DIV_I2C
 
- HI3670_CLK_DIV_ICS
 
- HI3670_CLK_DIV_IOPERI
 
- HI3670_CLK_DIV_LDI0
 
- HI3670_CLK_DIV_LDI1
 
- HI3670_CLK_DIV_MMC0BUS
 
- HI3670_CLK_DIV_MMC1BUS
 
- HI3670_CLK_DIV_PCIEAXI
 
- HI3670_CLK_DIV_PTP
 
- HI3670_CLK_DIV_SD
 
- HI3670_CLK_DIV_SDIO
 
- HI3670_CLK_DIV_SPI
 
- HI3670_CLK_DIV_SYSBUS
 
- HI3670_CLK_DIV_UART0
 
- HI3670_CLK_DIV_UARTH
 
- HI3670_CLK_DIV_UARTL
 
- HI3670_CLK_DIV_UFS_SUBSYS
 
- HI3670_CLK_DIV_VCODECBUS
 
- HI3670_CLK_DIV_VDEC
 
- HI3670_CLK_DIV_VENC
 
- HI3670_CLK_DIV_VIVOBUS
 
- HI3670_CLK_DSI_TRANS_GT
 
- HI3670_CLK_FACTOR_MMC
 
- HI3670_CLK_FACTOR_RXDPHY
 
- HI3670_CLK_FACTOR_UART0
 
- HI3670_CLK_FACTOR_USB3PHY_PLL
 
- HI3670_CLK_FLL_SRC
 
- HI3670_CLK_GATE_A53HPM
 
- HI3670_CLK_GATE_A57HPM
 
- HI3670_CLK_GATE_ABB_USB
 
- HI3670_CLK_GATE_AOHPM
 
- HI3670_CLK_GATE_AO_ASP
 
- HI3670_CLK_GATE_ASP_SUBSYS
 
- HI3670_CLK_GATE_ASP_SUBSYS_PERI
 
- HI3670_CLK_GATE_ASP_TCXO
 
- HI3670_CLK_GATE_ATDIV_VIVO
 
- HI3670_CLK_GATE_BRG
 
- HI3670_CLK_GATE_CCI400
 
- HI3670_CLK_GATE_CSI_TRANS
 
- HI3670_CLK_GATE_DMAC
 
- HI3670_CLK_GATE_DP_AUDIO_PLL
 
- HI3670_CLK_GATE_DP_AUDIO_PLL_AO
 
- HI3670_CLK_GATE_DSI_TRANS
 
- HI3670_CLK_GATE_DSS_AXI_MM
 
- HI3670_CLK_GATE_EDC0
 
- HI3670_CLK_GATE_GPUHPM
 
- HI3670_CLK_GATE_I2C0
 
- HI3670_CLK_GATE_I2C1
 
- HI3670_CLK_GATE_I2C2
 
- HI3670_CLK_GATE_I2C3
 
- HI3670_CLK_GATE_I2C4
 
- HI3670_CLK_GATE_I2C7
 
- HI3670_CLK_GATE_ICSFREQ
 
- HI3670_CLK_GATE_ISP_SNCLK0
 
- HI3670_CLK_GATE_ISP_SNCLK1
 
- HI3670_CLK_GATE_ISP_SNCLK2
 
- HI3670_CLK_GATE_LDI0
 
- HI3670_CLK_GATE_LDI1FREQ
 
- HI3670_CLK_GATE_MEDIA_TCXO
 
- HI3670_CLK_GATE_MMBUF
 
- HI3670_CLK_GATE_MMC1_PCIEAXI
 
- HI3670_CLK_GATE_OUT0
 
- HI3670_CLK_GATE_OUT1
 
- HI3670_CLK_GATE_PA_A53
 
- HI3670_CLK_GATE_PA_A57
 
- HI3670_CLK_GATE_PA_G3D
 
- HI3670_CLK_GATE_PCIEAUX
 
- HI3670_CLK_GATE_PCIEIO
 
- HI3670_CLK_GATE_PCIEPHY_REF
 
- HI3670_CLK_GATE_PCIE_DEBOUNCE
 
- HI3670_CLK_GATE_PCIE_HP
 
- HI3670_CLK_GATE_PERI0_IOMCU
 
- HI3670_CLK_GATE_PERIHPM
 
- HI3670_CLK_GATE_PPLL0_MEDIA
 
- HI3670_CLK_GATE_PPLL2_MEDIA
 
- HI3670_CLK_GATE_PPLL3_MEDIA
 
- HI3670_CLK_GATE_PPLL4_MEDIA
 
- HI3670_CLK_GATE_PPLL6_MEDIA
 
- HI3670_CLK_GATE_PPLL7_MEDIA
 
- HI3670_CLK_GATE_PWM
 
- HI3670_CLK_GATE_RXDPHY0_CFG
 
- HI3670_CLK_GATE_RXDPHY1_CFG
 
- HI3670_CLK_GATE_RXDPHY2_CFG
 
- HI3670_CLK_GATE_SD
 
- HI3670_CLK_GATE_SDIO
 
- HI3670_CLK_GATE_SPI
 
- HI3670_CLK_GATE_SPI0
 
- HI3670_CLK_GATE_SPI1
 
- HI3670_CLK_GATE_SPI2
 
- HI3670_CLK_GATE_SPI4
 
- HI3670_CLK_GATE_SYSCNT
 
- HI3670_CLK_GATE_TXDPHY0_CFG
 
- HI3670_CLK_GATE_TXDPHY0_REF
 
- HI3670_CLK_GATE_TXDPHY1_CFG
 
- HI3670_CLK_GATE_TXDPHY1_REF
 
- HI3670_CLK_GATE_UART0
 
- HI3670_CLK_GATE_UART1
 
- HI3670_CLK_GATE_UART2
 
- HI3670_CLK_GATE_UART3
 
- HI3670_CLK_GATE_UART4
 
- HI3670_CLK_GATE_UART5
 
- HI3670_CLK_GATE_UFSIO_REF
 
- HI3670_CLK_GATE_UFSPHY_REF
 
- HI3670_CLK_GATE_UFS_SUBSYS
 
- HI3670_CLK_GATE_USB2PHY_REF
 
- HI3670_CLK_GATE_USB3OTG_REF
 
- HI3670_CLK_GATE_VCODECBUS2DDR
 
- HI3670_CLK_GATE_VCODECBUS_GT
 
- HI3670_CLK_GATE_VDECFREQ
 
- HI3670_CLK_GATE_VENCFREQ
 
- HI3670_CLK_GATE_VIVOBUSFREQ
 
- HI3670_CLK_GATE_VIVOBUS_ANDGT
 
- HI3670_CLK_I2C0_GATE_IOMCU
 
- HI3670_CLK_I2C1_GATE_IOMCU
 
- HI3670_CLK_I2C2_GATE_IOMCU
 
- HI3670_CLK_INVALID
 
- HI3670_CLK_ISP_SNCLK_ANGT
 
- HI3670_CLK_ISP_SNCLK_DIV0
 
- HI3670_CLK_ISP_SNCLK_DIV1
 
- HI3670_CLK_ISP_SNCLK_DIV2
 
- HI3670_CLK_ISP_SNCLK_FAC
 
- HI3670_CLK_ISP_SNCLK_MUX0
 
- HI3670_CLK_ISP_SNCLK_MUX1
 
- HI3670_CLK_ISP_SNCLK_MUX2
 
- HI3670_CLK_MMBUF_PLL_ANDGT
 
- HI3670_CLK_MUX_320M
 
- HI3670_CLK_MUX_A53HPM
 
- HI3670_CLK_MUX_AO_ASP
 
- HI3670_CLK_MUX_ASP_PLL
 
- HI3670_CLK_MUX_ASP_SUBSYS_PERI
 
- HI3670_CLK_MUX_CLKOUT0
 
- HI3670_CLK_MUX_CLKOUT1
 
- HI3670_CLK_MUX_EDC0
 
- HI3670_CLK_MUX_I2C
 
- HI3670_CLK_MUX_ICS
 
- HI3670_CLK_MUX_LDI0
 
- HI3670_CLK_MUX_LDI1
 
- HI3670_CLK_MUX_PCIEAXI
 
- HI3670_CLK_MUX_RXDPHY_CFG
 
- HI3670_CLK_MUX_SDIO_PLL
 
- HI3670_CLK_MUX_SDIO_SYS
 
- HI3670_CLK_MUX_SD_PLL
 
- HI3670_CLK_MUX_SD_SYS
 
- HI3670_CLK_MUX_SPI
 
- HI3670_CLK_MUX_SYSBUS
 
- HI3670_CLK_MUX_UART0
 
- HI3670_CLK_MUX_UARTH
 
- HI3670_CLK_MUX_UARTL
 
- HI3670_CLK_MUX_UFS_SUBSYS
 
- HI3670_CLK_MUX_VCODECBUS
 
- HI3670_CLK_MUX_VDEC
 
- HI3670_CLK_MUX_VENC
 
- HI3670_CLK_MUX_VIVOBUS
 
- HI3670_CLK_PCIEPLL_REV
 
- HI3670_CLK_PPLL0
 
- HI3670_CLK_PPLL1
 
- HI3670_CLK_PPLL2
 
- HI3670_CLK_PPLL3
 
- HI3670_CLK_PPLL4
 
- HI3670_CLK_PPLL6
 
- HI3670_CLK_PPLL7
 
- HI3670_CLK_PPLL_PCIE
 
- HI3670_CLK_SCPLL
 
- HI3670_CLK_SDIO_SYS
 
- HI3670_CLK_SDIO_SYS_GT
 
- HI3670_CLK_SD_SYS
 
- HI3670_CLK_SD_SYS_GT
 
- HI3670_CLK_SPI0_GATE_IOMCU
 
- HI3670_CLK_SPI2_GATE_IOMCU
 
- HI3670_CLK_STUB_CLUSTER0
 
- HI3670_CLK_STUB_CLUSTER1
 
- HI3670_CLK_STUB_DDR
 
- HI3670_CLK_STUB_DDR_LIMIT
 
- HI3670_CLK_STUB_DDR_VOTE
 
- HI3670_CLK_STUB_GPU
 
- HI3670_CLK_STUB_NUM
 
- HI3670_CLK_SW_MMBUF
 
- HI3670_CLK_UART0_DBG
 
- HI3670_CLK_UART3_GATE_IOMCU
 
- HI3670_CLK_UART6
 
- HI3670_EDC_VOLT_HOLD
 
- HI3670_GATE_ABB_192
 
- HI3670_GATE_UFS_TCXO_EN
 
- HI3670_GATE_USB_TCXO_EN
 
- HI3670_HCLK_GATE_SD
 
- HI3670_HCLK_GATE_SDIO
 
- HI3670_HCLK_GATE_USB3OTG
 
- HI3670_ICS_VOLT_HIGH
 
- HI3670_ICS_VOLT_MIDDLE
 
- HI3670_OSC19M
 
- HI3670_OSC32K
 
- HI3670_PCLK
 
- HI3670_PCLK_ANDGT_MMC1_PCIE
 
- HI3670_PCLK_AO_GPIO0
 
- HI3670_PCLK_AO_GPIO1
 
- HI3670_PCLK_AO_GPIO2
 
- HI3670_PCLK_AO_GPIO3
 
- HI3670_PCLK_AO_GPIO4
 
- HI3670_PCLK_AO_GPIO5
 
- HI3670_PCLK_AO_GPIO6
 
- HI3670_PCLK_DIV_MMBUF
 
- HI3670_PCLK_DIV_MMC1_PCIE
 
- HI3670_PCLK_GATE_DISP_NOC_SUBSYS
 
- HI3670_PCLK_GATE_DSI0
 
- HI3670_PCLK_GATE_DSI1
 
- HI3670_PCLK_GATE_DSS
 
- HI3670_PCLK_GATE_I2C3
 
- HI3670_PCLK_GATE_I2C4
 
- HI3670_PCLK_GATE_I2C7
 
- HI3670_PCLK_GATE_MMBUF
 
- HI3670_PCLK_GATE_MMBUF_CFG
 
- HI3670_PCLK_GATE_MMC0_IOC
 
- HI3670_PCLK_GATE_MMC1_IOC
 
- HI3670_PCLK_GATE_MMC1_PCIE
 
- HI3670_PCLK_GATE_NOC_DSS_CFG
 
- HI3670_PCLK_GATE_PCIE_PHY
 
- HI3670_PCLK_GATE_PCIE_SYS
 
- HI3670_PCLK_GATE_PCTRL
 
- HI3670_PCLK_GATE_SPI
 
- HI3670_PCLK_GATE_SPI1
 
- HI3670_PCLK_GATE_SPI4
 
- HI3670_PCLK_GATE_SYSCNT
 
- HI3670_PCLK_GATE_UART0
 
- HI3670_PCLK_GATE_UART1
 
- HI3670_PCLK_GATE_UART2
 
- HI3670_PCLK_GATE_UART4
 
- HI3670_PCLK_GATE_UART5
 
- HI3670_PCLK_GPIO0
 
- HI3670_PCLK_GPIO1
 
- HI3670_PCLK_GPIO10
 
- HI3670_PCLK_GPIO11
 
- HI3670_PCLK_GPIO12
 
- HI3670_PCLK_GPIO13
 
- HI3670_PCLK_GPIO14
 
- HI3670_PCLK_GPIO15
 
- HI3670_PCLK_GPIO16
 
- HI3670_PCLK_GPIO17
 
- HI3670_PCLK_GPIO18
 
- HI3670_PCLK_GPIO19
 
- HI3670_PCLK_GPIO2
 
- HI3670_PCLK_GPIO20
 
- HI3670_PCLK_GPIO21
 
- HI3670_PCLK_GPIO3
 
- HI3670_PCLK_GPIO4
 
- HI3670_PCLK_GPIO5
 
- HI3670_PCLK_GPIO6
 
- HI3670_PCLK_GPIO7
 
- HI3670_PCLK_GPIO8
 
- HI3670_PCLK_GPIO9
 
- HI3670_PCLK_MMBUF_ANDGT
 
- HI3670_PERI_VOLT_HOLD
 
- HI3670_PERI_VOLT_MIDDLE
 
- HI3670_PPLL0_EN_ACPU
 
- HI3670_PPLL0_GT_CPU
 
- HI3670_PPLL1_EN_ACPU
 
- HI3670_PPLL1_GT_CPU
 
- HI3670_PPLL2_EN_ACPU
 
- HI3670_PPLL2_GT_CPU
 
- HI3670_PPLL3_EN_ACPU
 
- HI3670_PPLL3_GT_CPU
 
- HI3670_VDEC_VOLT_HOLD
 
- HI3670_VENC_VOLT_HOLD
 
- HI3798CV200_COMBPHY0_MUX
 
- HI3798CV200_COMBPHY1_MUX
 
- HI3798CV200_CRG_NR_CLKS
 
- HI3798CV200_ETH_BUS0_CLK
 
- HI3798CV200_ETH_BUS1_CLK
 
- HI3798CV200_ETH_BUS_CLK
 
- HI3798CV200_ETH_PUB_CLK
 
- HI3798CV200_FIXED_100M
 
- HI3798CV200_FIXED_12M
 
- HI3798CV200_FIXED_150M
 
- HI3798CV200_FIXED_166P5M
 
- HI3798CV200_FIXED_200M
 
- HI3798CV200_FIXED_24M
 
- HI3798CV200_FIXED_250M
 
- HI3798CV200_FIXED_25M
 
- HI3798CV200_FIXED_300M
 
- HI3798CV200_FIXED_400M
 
- HI3798CV200_FIXED_48M
 
- HI3798CV200_FIXED_50M
 
- HI3798CV200_FIXED_60M
 
- HI3798CV200_FIXED_75M
 
- HI3798CV200_INNER_CLK_OFFSET
 
- HI3798CV200_MMC_MUX
 
- HI3798CV200_SDIO0_MUX
 
- HI3798CV200_SYSCTRL_NR_CLKS
 
- HI6220_1000_1200
 
- HI6220_1000_1440
 
- HI6220_1440_1200
 
- HI6220_150M
 
- HI6220_300M
 
- HI6220_ACLK_CODEC_VPU
 
- HI6220_ACPU_SFT_AT_S
 
- HI6220_ADE_CORE
 
- HI6220_ADE_CORE_GATE
 
- HI6220_ADE_CORE_SRC
 
- HI6220_ADE_PIX_SRC
 
- HI6220_AO_NR_CLKS
 
- HI6220_BBPPLL0_DIV
 
- HI6220_BBPPLL_SEL
 
- HI6220_CFG_CSI2PHY
 
- HI6220_CFG_CSI4PHY
 
- HI6220_CLK_BUS
 
- HI6220_CLK_PICOPHY
 
- HI6220_CLK_TCXO
 
- HI6220_CLUSTER0_SENSOR
 
- HI6220_CLUSTER1_SENSOR
 
- HI6220_CODEC_JPEG
 
- HI6220_CODEC_VPU_GATE
 
- HI6220_CODEC_VPU_SRC
 
- HI6220_CS_ATB
 
- HI6220_CS_ATB_DIV
 
- HI6220_CS_ATB_SYSPLL
 
- HI6220_CS_DAPB
 
- HI6220_DACODEC_PCLK
 
- HI6220_DAPB_CLK
 
- HI6220_DDRC_AXI1
 
- HI6220_DDRC_SRC
 
- HI6220_DDR_SRC
 
- HI6220_DSI_PCLK
 
- HI6220_EDMAC_ACLK
 
- HI6220_G3D_CLK
 
- HI6220_G3D_PCLK
 
- HI6220_HIFI
 
- HI6220_HIFI_DIV
 
- HI6220_HIFI_SEL
 
- HI6220_HIFI_SRC
 
- HI6220_I2C0_CLK
 
- HI6220_I2C1_CLK
 
- HI6220_I2C2_CLK
 
- HI6220_I2C3_CLK
 
- HI6220_ISP_SCLK
 
- HI6220_ISP_SCLK1
 
- HI6220_ISP_SCLK_GATE
 
- HI6220_ISP_SCLK_GATE1
 
- HI6220_ISP_SCLK_SRC
 
- HI6220_MBOX_CMD_SET
 
- HI6220_MBOX_FREQ
 
- HI6220_MBOX_MSG_LEN
 
- HI6220_MBOX_OBJ_AP
 
- HI6220_MEDIA_NR_CLKS
 
- HI6220_MEDIA_PLL_SRC
 
- HI6220_MED_MMU
 
- HI6220_MED_SYSPLL
 
- HI6220_MMC0_CIUCLK
 
- HI6220_MMC0_CLK
 
- HI6220_MMC0_DIV
 
- HI6220_MMC0_MUX0
 
- HI6220_MMC0_MUX1
 
- HI6220_MMC0_PAD
 
- HI6220_MMC0_SEL
 
- HI6220_MMC0_SMP
 
- HI6220_MMC0_SMP_IN
 
- HI6220_MMC0_SRC
 
- HI6220_MMC0_SRC_SEL
 
- HI6220_MMC0_SYSPLL
 
- HI6220_MMC1_CIUCLK
 
- HI6220_MMC1_CLK
 
- HI6220_MMC1_DIV
 
- HI6220_MMC1_MUX0
 
- HI6220_MMC1_MUX1
 
- HI6220_MMC1_PAD
 
- HI6220_MMC1_SEL
 
- HI6220_MMC1_SMP
 
- HI6220_MMC1_SMP_IN
 
- HI6220_MMC1_SRC
 
- HI6220_MMC1_SRC_SEL
 
- HI6220_MMC1_SYSPLL
 
- HI6220_MMC2_CIUCLK
 
- HI6220_MMC2_CLK
 
- HI6220_MMC2_DIV
 
- HI6220_MMC2_MUX0
 
- HI6220_MMC2_MUX1
 
- HI6220_MMC2_PAD
 
- HI6220_MMC2_SEL
 
- HI6220_MMC2_SMP
 
- HI6220_MMC2_SMP_IN
 
- HI6220_MMC2_SRC
 
- HI6220_MMC2_SRC_SEL
 
- HI6220_MMC2_SYSPLL
 
- HI6220_MMU_CLK
 
- HI6220_NONE_CLOCK
 
- HI6220_PICOPHY_SRC
 
- HI6220_PLL0_BBP_GATE
 
- HI6220_PLL1_DDR
 
- HI6220_PLL1_DDR_GATE
 
- HI6220_PLL_BBP
 
- HI6220_PLL_DDR
 
- HI6220_PLL_DDR_GATE
 
- HI6220_PLL_GPU
 
- HI6220_PLL_GPU_GATE
 
- HI6220_PLL_MEDIA
 
- HI6220_PLL_MEDIA_GATE
 
- HI6220_PLL_SYS
 
- HI6220_PLL_SYS_MEDIA
 
- HI6220_POWER_NR_CLKS
 
- HI6220_REF32K
 
- HI6220_RTC0_PCLK
 
- HI6220_RTC1_PCLK
 
- HI6220_SPI_CLK
 
- HI6220_STUB_ACPU0
 
- HI6220_STUB_ACPU1
 
- HI6220_STUB_DDR
 
- HI6220_STUB_GPU
 
- HI6220_SYS_NR_CLKS
 
- HI6220_TEMP0_CFG
 
- HI6220_TEMP0_CFG_HDAK_MSK
 
- HI6220_TEMP0_CFG_SS_MSK
 
- HI6220_TEMP0_EN
 
- HI6220_TEMP0_INT_CLR
 
- HI6220_TEMP0_INT_EN
 
- HI6220_TEMP0_LAG
 
- HI6220_TEMP0_RST_MSK
 
- HI6220_TEMP0_RST_TH
 
- HI6220_TEMP0_TH
 
- HI6220_TEMP0_VALUE
 
- HI6220_TEMP_BASE
 
- HI6220_TEMP_LAG
 
- HI6220_TEMP_RESET
 
- HI6220_TEMP_STEP
 
- HI6220_TIMER0_PCLK
 
- HI6220_TIMER1_PCLK
 
- HI6220_TIMER2_PCLK
 
- HI6220_TIMER3_PCLK
 
- HI6220_TIMER4_PCLK
 
- HI6220_TIMER5_PCLK
 
- HI6220_TIMER6_PCLK
 
- HI6220_TIMER7_PCLK
 
- HI6220_TIMER8_PCLK
 
- HI6220_TSENSOR_CLK
 
- HI6220_UART0_PCLK
 
- HI6220_UART1_PCLK
 
- HI6220_UART1_SRC
 
- HI6220_UART2_PCLK
 
- HI6220_UART2_SRC
 
- HI6220_UART3_PCLK
 
- HI6220_UART3_SRC
 
- HI6220_UART4_PCLK
 
- HI6220_UART4_SRC
 
- HI6220_USBOTG_HCLK
 
- HI6220_VPU_CODEC
 
- HI6220_WDT0_PCLK
 
- HI6220_WDT1_PCLK
 
- HI6220_WDT2_PCLK
 
- HI6421
 
- HI6421V530_LDO
 
- HI6421V530_LDO11
 
- HI6421V530_LDO15
 
- HI6421V530_LDO16
 
- HI6421V530_LDO3
 
- HI6421V530_LDO9
 
- HI6421V530_LDO_ENABLE_TIME
 
- HI6421_BUCK0
 
- HI6421_BUCK012
 
- HI6421_BUCK1
 
- HI6421_BUCK2
 
- HI6421_BUCK3
 
- HI6421_BUCK345
 
- HI6421_BUCK4
 
- HI6421_BUCK5
 
- HI6421_LDO
 
- HI6421_LDO0
 
- HI6421_LDO1
 
- HI6421_LDO10
 
- HI6421_LDO11
 
- HI6421_LDO12
 
- HI6421_LDO13
 
- HI6421_LDO14
 
- HI6421_LDO15
 
- HI6421_LDO16
 
- HI6421_LDO17
 
- HI6421_LDO18
 
- HI6421_LDO19
 
- HI6421_LDO2
 
- HI6421_LDO20
 
- HI6421_LDO3
 
- HI6421_LDO4
 
- HI6421_LDO5
 
- HI6421_LDO6
 
- HI6421_LDO7
 
- HI6421_LDO8
 
- HI6421_LDO9
 
- HI6421_LDOAUDIO
 
- HI6421_LDO_ENABLE_TIME
 
- HI6421_LDO_LINEAR
 
- HI6421_LDO_LINEAR_RANGE
 
- HI6421_NUM_REGULATORS
 
- HI6421_OCP_AUTO_STOP_ENABLE
 
- HI6421_OCP_AUTO_STOP_MASK
 
- HI6421_OCP_DEB_CTRL_REG
 
- HI6421_OCP_DEB_SEL_16MS
 
- HI6421_OCP_DEB_SEL_32MS
 
- HI6421_OCP_DEB_SEL_64MS
 
- HI6421_OCP_DEB_SEL_8MS
 
- HI6421_OCP_DEB_SEL_MASK
 
- HI6421_OCP_EN_DEBOUNCE_ENABLE
 
- HI6421_OCP_EN_DEBOUNCE_MASK
 
- HI6421_REG_MAX
 
- HI6421_REG_TO_BUS_ADDR
 
- HI6421_V530
 
- HI655X_ANA_IRQM_BASE
 
- HI655X_BITS
 
- HI655X_BUS_ADDR
 
- HI655X_CLK_BASE
 
- HI655X_CLK_SET
 
- HI655X_IRQ_ARRAY
 
- HI655X_IRQ_CLR
 
- HI655X_IRQ_MASK
 
- HI655X_IRQ_MASK_BASE
 
- HI655X_IRQ_STAT_BASE
 
- HI655X_LDO
 
- HI655X_LDO0
 
- HI655X_LDO1
 
- HI655X_LDO10
 
- HI655X_LDO11
 
- HI655X_LDO12
 
- HI655X_LDO13
 
- HI655X_LDO14
 
- HI655X_LDO15
 
- HI655X_LDO16
 
- HI655X_LDO17
 
- HI655X_LDO18
 
- HI655X_LDO19
 
- HI655X_LDO2
 
- HI655X_LDO20
 
- HI655X_LDO21
 
- HI655X_LDO22
 
- HI655X_LDO3
 
- HI655X_LDO4
 
- HI655X_LDO5
 
- HI655X_LDO6
 
- HI655X_LDO7
 
- HI655X_LDO8
 
- HI655X_LDO9
 
- HI655X_LDO_LINEAR
 
- HI655X_NR_IRQ
 
- HI655X_STRIDE
 
- HI655X_VER_REG
 
- HI8435_CTRL_REG
 
- HI8435_CTRL_SRST
 
- HI8435_CTRL_TEST
 
- HI8435_GOCENHYS_REG
 
- HI8435_PSEN_REG
 
- HI8435_READ_OPCODE
 
- HI8435_SO15_8_REG
 
- HI8435_SO23_16_REG
 
- HI8435_SO31_0_REG
 
- HI8435_SO31_24_REG
 
- HI8435_SO7_0_REG
 
- HI8435_SOCENHYS_REG
 
- HI8435_TMDATA_REG
 
- HI8435_VOLTAGE_CHANNEL
 
- HI8435_WRITE_OPCODE
 
- HIA_MST_CTRL
 
- HIA_OPTIONS
 
- HIA_VERSION
 
- HIBERN8TIME_UNIT_US
 
- HIBERNATE
 
- HIBERNATE_SIG
 
- HIBERNATE_TEXT
 
- HIBERNATION_FIRST
 
- HIBERNATION_INVALID
 
- HIBERNATION_MAX
 
- HIBERNATION_PLATFORM
 
- HIBERNATION_REBOOT
 
- HIBERNATION_SHUTDOWN
 
- HIBERNATION_SUSPEND
 
- HIBERNATION_TEST_RESUME
 
- HIBERR
 
- HIBIT
 
- HIBMC_CRTSELECT_CRT
 
- HIBMC_CRT_AUTO_CENTERING_BR
 
- HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM
 
- HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM_MASK
 
- HIBMC_CRT_AUTO_CENTERING_BR_RIGHT
 
- HIBMC_CRT_AUTO_CENTERING_BR_RIGHT_MASK
 
- HIBMC_CRT_AUTO_CENTERING_TL
 
- HIBMC_CRT_AUTO_CENTERING_TL_LEFT
 
- HIBMC_CRT_AUTO_CENTERING_TL_LEFT_MASK
 
- HIBMC_CRT_AUTO_CENTERING_TL_TOP
 
- HIBMC_CRT_AUTO_CENTERING_TL_TOP_MASK
 
- HIBMC_CRT_DISP_CTL
 
- HIBMC_CRT_DISP_CTL_CLOCK_PHASE
 
- HIBMC_CRT_DISP_CTL_CLOCK_PHASE_MASK
 
- HIBMC_CRT_DISP_CTL_CRTSELECT
 
- HIBMC_CRT_DISP_CTL_CRTSELECT_MASK
 
- HIBMC_CRT_DISP_CTL_FORMAT
 
- HIBMC_CRT_DISP_CTL_FORMAT_MASK
 
- HIBMC_CRT_DISP_CTL_HSYNC_PHASE
 
- HIBMC_CRT_DISP_CTL_HSYNC_PHASE_MASK
 
- HIBMC_CRT_DISP_CTL_PLANE
 
- HIBMC_CRT_DISP_CTL_PLANE_MASK
 
- HIBMC_CRT_DISP_CTL_TIMING
 
- HIBMC_CRT_DISP_CTL_TIMING_MASK
 
- HIBMC_CRT_DISP_CTL_VSYNC_PHASE
 
- HIBMC_CRT_DISP_CTL_VSYNC_PHASE_MASK
 
- HIBMC_CRT_FB_ADDRESS
 
- HIBMC_CRT_FB_WIDTH
 
- HIBMC_CRT_FB_WIDTH_OFFS
 
- HIBMC_CRT_FB_WIDTH_OFFS_MASK
 
- HIBMC_CRT_FB_WIDTH_WIDTH
 
- HIBMC_CRT_FB_WIDTH_WIDTH_MASK
 
- HIBMC_CRT_HORZ_SYNC
 
- HIBMC_CRT_HORZ_SYNC_START
 
- HIBMC_CRT_HORZ_SYNC_START_MASK
 
- HIBMC_CRT_HORZ_SYNC_WIDTH
 
- HIBMC_CRT_HORZ_SYNC_WIDTH_MASK
 
- HIBMC_CRT_HORZ_TOTAL
 
- HIBMC_CRT_HORZ_TOTAL_DISP_END
 
- HIBMC_CRT_HORZ_TOTAL_DISP_END_MASK
 
- HIBMC_CRT_HORZ_TOTAL_TOTAL
 
- HIBMC_CRT_HORZ_TOTAL_TOTAL_MASK
 
- HIBMC_CRT_PLL_CTRL
 
- HIBMC_CRT_VERT_SYNC
 
- HIBMC_CRT_VERT_SYNC_HEIGHT
 
- HIBMC_CRT_VERT_SYNC_HEIGHT_MASK
 
- HIBMC_CRT_VERT_SYNC_START
 
- HIBMC_CRT_VERT_SYNC_START_MASK
 
- HIBMC_CRT_VERT_TOTAL
 
- HIBMC_CRT_VERT_TOTAL_DISP_END
 
- HIBMC_CRT_VERT_TOTAL_DISP_END_MASK
 
- HIBMC_CRT_VERT_TOTAL_TOTAL
 
- HIBMC_CRT_VERT_TOTAL_TOTAL_MASK
 
- HIBMC_CURRENT_GATE
 
- HIBMC_CURR_GATE_DISPLAY
 
- HIBMC_CURR_GATE_DISPLAY_MASK
 
- HIBMC_CURR_GATE_LOCALMEM
 
- HIBMC_CURR_GATE_LOCALMEM_MASK
 
- HIBMC_DISPLAY_CONTROL_FPEN
 
- HIBMC_DISPLAY_CONTROL_FPVDDEN
 
- HIBMC_DISPLAY_CONTROL_HISILE
 
- HIBMC_DISPLAY_CONTROL_PANELDATE
 
- HIBMC_DISPLAY_CONTROL_VBIASEN
 
- HIBMC_DRM_DRV_H
 
- HIBMC_DRM_HW_H
 
- HIBMC_FIELD
 
- HIBMC_MISC_CTRL
 
- HIBMC_MODE0_GATE
 
- HIBMC_MODE1_GATE
 
- HIBMC_MSCCTL_LOCALMEM_RESET
 
- HIBMC_MSCCTL_LOCALMEM_RESET_MASK
 
- HIBMC_PANEL_PLL_CTRL
 
- HIBMC_PLL_CTRL_BYPASS
 
- HIBMC_PLL_CTRL_BYPASS_MASK
 
- HIBMC_PLL_CTRL_INPUT
 
- HIBMC_PLL_CTRL_INPUT_MASK
 
- HIBMC_PLL_CTRL_M
 
- HIBMC_PLL_CTRL_M_MASK
 
- HIBMC_PLL_CTRL_N
 
- HIBMC_PLL_CTRL_N_MASK
 
- HIBMC_PLL_CTRL_OD
 
- HIBMC_PLL_CTRL_OD_MASK
 
- HIBMC_PLL_CTRL_POD
 
- HIBMC_PLL_CTRL_POD_MASK
 
- HIBMC_PLL_CTRL_POWER
 
- HIBMC_PLL_CTRL_POWER_MASK
 
- HIBMC_POWER_MODE_CTRL
 
- HIBMC_PW_MODE_CTL_MODE
 
- HIBMC_PW_MODE_CTL_MODE_MASK
 
- HIBMC_PW_MODE_CTL_MODE_MODE0
 
- HIBMC_PW_MODE_CTL_MODE_MODE1
 
- HIBMC_PW_MODE_CTL_MODE_SHIFT
 
- HIBMC_PW_MODE_CTL_MODE_SLEEP
 
- HIBMC_PW_MODE_CTL_OSC_INPUT
 
- HIBMC_PW_MODE_CTL_OSC_INPUT_MASK
 
- HIBMC_RAW_INTERRUPT
 
- HIBMC_RAW_INTERRUPT_EN
 
- HIBMC_RAW_INTERRUPT_EN_VBLANK
 
- HIBMC_RAW_INTERRUPT_EN_VBLANK_MASK
 
- HIBMC_RAW_INTERRUPT_VBLANK
 
- HIBMC_RAW_INTERRUPT_VBLANK_MASK
 
- HIBNEG_BYPSS_BRKTIMER
 
- HIBNEG_DEF
 
- HIBNEG_GATE_25M_EN
 
- HIBNEG_GTX_CLK_DELAY_MASK
 
- HIBNEG_GTX_CLK_DELAY_SHIFT
 
- HIBNEG_HIB_PULSE
 
- HIBNEG_ONOFF_ANACHG_SUDEN
 
- HIBNEG_PSHIB_EN
 
- HIBNEG_RST_80U
 
- HIBNEG_RST_TIMER_MASK
 
- HIBNEG_RST_TIMER_SHIFT
 
- HIBNEG_WAKE_BOTH
 
- HIBYTE
 
- HICR5
 
- HICR5_ENFWH
 
- HICR5_ENINT_SNP0W
 
- HICR5_ENINT_SNP1W
 
- HICR5_ENL2H
 
- HICR5_EN_SNP0W
 
- HICR5_EN_SNP1W
 
- HICR6
 
- HICR6_STR_SNP0W
 
- HICR6_STR_SNP1W
 
- HICR7
 
- HICR8
 
- HICRB
 
- HICRB_ENSNP0D
 
- HICRB_ENSNP1D
 
- HICR_CHGM
 
- HICR_HOST_ALIVENESS_RESP_ACK
 
- HICR_HOST_ALIVENESS_RESP_REG
 
- HICR_IEV
 
- HICR_SEC_IPC_OUTPUT_DOORBELL_REG
 
- HICR_SEC_IPC_READINESS_HOST_RDY
 
- HICR_SEC_IPC_READINESS_RDY_CLR
 
- HICR_SEC_IPC_READINESS_REG
 
- HICR_SEC_IPC_READINESS_SEC_RDY
 
- HICR_SEC_IPC_READINESS_SYS_RDY
 
- HIC_CAPTURE_STILL
 
- HIC_CAPTURE_VIDEO
 
- HIC_CLOSE_SENSOR
 
- HIC_GET_PARAMETER
 
- HIC_GET_SET_FILE_ADDR
 
- HIC_GET_STATUS
 
- HIC_LOAD_SET_FILE
 
- HIC_MSG_CONFIG
 
- HIC_MSG_TEST
 
- HIC_OPEN_SENSOR
 
- HIC_POWER_DOWN
 
- HIC_PREVIEW_STILL
 
- HIC_PREVIEW_VIDEO
 
- HIC_SET_PARAMETER
 
- HIC_SET_TUNE
 
- HIC_SIMMIAN_INIT
 
- HIC_SIMMIAN_READ
 
- HIC_SIMMIAN_WRITE
 
- HIC_STREAM_OFF
 
- HIC_STREAM_ON
 
- HID0
 
- HID0_ABE
 
- HID0_BHTCLR
 
- HID0_BHTE
 
- HID0_BTCD
 
- HID0_BTIC
 
- HID0_CBE_SYSERR_INT_EN
 
- HID0_CBE_SYSERR_WAKEUP
 
- HID0_CBE_THERM_INT_EN
 
- HID0_CBE_THERM_WAKEUP
 
- HID0_DAPUEN
 
- HID0_DCE
 
- HID0_DCFA
 
- HID0_DCI
 
- HID0_DLOCK
 
- HID0_DOZE
 
- HID0_DPM
 
- HID0_EBA
 
- HID0_EBD
 
- HID0_ECLK
 
- HID0_EICE
 
- HID0_EMCP
 
- HID0_FOLD
 
- HID0_HDICE_SH
 
- HID0_HIGH_BAT
 
- HID0_ICE
 
- HID0_ICFI
 
- HID0_ILOCK
 
- HID0_LRSTK
 
- HID0_NAP
 
- HID0_NHR
 
- HID0_NOPDST
 
- HID0_NOPTI
 
- HID0_PAR
 
- HID0_POWER8_1TO2LPAR
 
- HID0_POWER8_1TO4LPAR
 
- HID0_POWER8_2LPARMODE
 
- HID0_POWER8_4LPARMODE
 
- HID0_POWER8_DYNLPARDIS
 
- HID0_POWER9_RADIX
 
- HID0_SBCLK
 
- HID0_SGE
 
- HID0_SIED
 
- HID0_SLEEP
 
- HID0_SPD
 
- HID0_STEN
 
- HID0_TBEN
 
- HID0_XAEN
 
- HID1
 
- HID1_ABE
 
- HID1_ASTME
 
- HID1_ATS
 
- HID1_DFS
 
- HID1_EMCP
 
- HID1_MID_MASK
 
- HID1_MPXTT
 
- HID1_PC0
 
- HID1_PC1
 
- HID1_PC2
 
- HID1_PC3
 
- HID1_PLL_CFG_MASK
 
- HID1_PS
 
- HID1_R1DPE
 
- HID1_R2DPE
 
- HID1_RFXE
 
- HID1_SYNCBE
 
- HID2
 
- HID3
 
- HID4_LPES0
 
- HID4_LPES1
 
- HID4_LPID1_SH
 
- HID4_LPID5_SH
 
- HID4_RMLS0_SH
 
- HID4_RMLS2_SH
 
- HID4_RMOR
 
- HID4_RMOR_SH
 
- HID6_DLP
 
- HID6_LB
 
- HIDDEN_AREA
 
- HIDDEV_BUFFER_SIZE
 
- HIDDEV_FLAGS
 
- HIDDEV_FLAG_REPORT
 
- HIDDEV_FLAG_UREF
 
- HIDDEV_MINORS
 
- HIDDEV_MINOR_BASE
 
- HIDEEP_DWZ_INFO
 
- HIDEEP_ESI_BASE
 
- HIDEEP_ESI_TX_INVALID
 
- HIDEEP_EVENT_ADDR
 
- HIDEEP_FLASH_BASE
 
- HIDEEP_FLASH_CACHE_CFG
 
- HIDEEP_FLASH_CFG
 
- HIDEEP_FLASH_CON
 
- HIDEEP_FLASH_PIO_SIG
 
- HIDEEP_FLASH_STA
 
- HIDEEP_FLASH_TIM
 
- HIDEEP_I2C_NAME
 
- HIDEEP_KEY_EVENT_INDEX
 
- HIDEEP_KEY_FIRST_PRESSED
 
- HIDEEP_KEY_IDX_MASK
 
- HIDEEP_KEY_MAX
 
- HIDEEP_KEY_PRESSED
 
- HIDEEP_KEY_PRESSED_MASK
 
- HIDEEP_MAX_EVENT
 
- HIDEEP_MT_MAX
 
- HIDEEP_MT_RELEASED
 
- HIDEEP_NVM_DEFAULT_PAGE
 
- HIDEEP_NVM_MASK_OFS
 
- HIDEEP_NVM_PAGE_SIZE
 
- HIDEEP_NVM_SFR_RPAGE
 
- HIDEEP_NVM_SFR_WPAGE
 
- HIDEEP_PERASE
 
- HIDEEP_PERIPHERAL_BASE
 
- HIDEEP_PIO_SIG
 
- HIDEEP_PROT_MODE
 
- HIDEEP_RESET_CMD
 
- HIDEEP_SYSCON_BASE
 
- HIDEEP_SYSCON_CLK_CON
 
- HIDEEP_SYSCON_CLK_ENA
 
- HIDEEP_SYSCON_MOD_CON
 
- HIDEEP_SYSCON_PGM_ID
 
- HIDEEP_SYSCON_PWR_CON
 
- HIDEEP_SYSCON_RST_CON
 
- HIDEEP_SYSCON_SPC_CON
 
- HIDEEP_SYSCON_WDT_CNT
 
- HIDEEP_SYSCON_WDT_CON
 
- HIDEEP_TOUCH_EVENT_INDEX
 
- HIDEEP_TS_NAME
 
- HIDEEP_WRONLY
 
- HIDEEP_XFER_BUF_SIZE
 
- HIDEEP_YRAM_BASE
 
- HIDEPID_INVISIBLE
 
- HIDEPID_NO_ACCESS
 
- HIDEPID_OFF
 
- HIDE_CURSOR
 
- HIDE_LIST
 
- HIDE_PCI_ASSERTS
 
- HIDE_PORT_STAT
 
- HIDE_STATUS_PHASE
 
- HIDG_MINORS
 
- HIDG_PRODUCT_NUM
 
- HIDG_VENDOR_NUM
 
- HIDIOCAPPLICATION
 
- HIDIOCGCOLLECTIONINDEX
 
- HIDIOCGCOLLECTIONINFO
 
- HIDIOCGDEVINFO
 
- HIDIOCGFEATURE
 
- HIDIOCGFIELDINFO
 
- HIDIOCGFLAG
 
- HIDIOCGNAME
 
- HIDIOCGPHYS
 
- HIDIOCGRAWINFO
 
- HIDIOCGRAWNAME
 
- HIDIOCGRAWPHYS
 
- HIDIOCGRDESC
 
- HIDIOCGRDESCSIZE
 
- HIDIOCGREPORT
 
- HIDIOCGREPORTINFO
 
- HIDIOCGSTRING
 
- HIDIOCGUCODE
 
- HIDIOCGUSAGE
 
- HIDIOCGUSAGES
 
- HIDIOCGVERSION
 
- HIDIOCINITREPORT
 
- HIDIOCSFEATURE
 
- HIDIOCSFLAG
 
- HIDIOCSREPORT
 
- HIDIOCSUSAGE
 
- HIDIOCSUSAGES
 
- HIDMAMEM
 
- HIDMA_AUTOSUSPEND_TIMEOUT
 
- HIDMA_CFG_OFFSET
 
- HIDMA_CHRESET_TIMEOUT_MASK
 
- HIDMA_CHRESET_TIMEOUT_OFFSET
 
- HIDMA_CH_CONTROL_MASK
 
- HIDMA_CH_DISABLE
 
- HIDMA_CH_DISABLED
 
- HIDMA_CH_ENABLE
 
- HIDMA_CH_ENABLED
 
- HIDMA_CH_RESET
 
- HIDMA_CH_RUNNING
 
- HIDMA_CH_STATE
 
- HIDMA_CH_STATE_BIT_POS
 
- HIDMA_CH_STATE_MASK
 
- HIDMA_CH_STOPPED
 
- HIDMA_CH_SUSPEND
 
- HIDMA_CH_SUSPENDED
 
- HIDMA_ERR_CODE_UNEXPECTED_TERMINATE
 
- HIDMA_ERR_INFO_SW
 
- HIDMA_ERR_INT_MASK
 
- HIDMA_EVCA_CTRLSTS_REG
 
- HIDMA_EVCA_DOORBELL_REG
 
- HIDMA_EVCA_INTCTRL_REG
 
- HIDMA_EVCA_IRQ_CLR_REG
 
- HIDMA_EVCA_IRQ_EN_REG
 
- HIDMA_EVCA_IRQ_STAT_REG
 
- HIDMA_EVCA_RING_HIGH_REG
 
- HIDMA_EVCA_RING_LEN_REG
 
- HIDMA_EVCA_RING_LOW_REG
 
- HIDMA_EVCA_WRITE_PTR_REG
 
- HIDMA_EVRE_CFG_IDX
 
- HIDMA_EVRE_CODE_BIT_POS
 
- HIDMA_EVRE_CODE_MASK
 
- HIDMA_EVRE_ERRINFO_BIT_POS
 
- HIDMA_EVRE_ERRINFO_MASK
 
- HIDMA_EVRE_SIZE
 
- HIDMA_EVRE_STATUS_COMPLETE
 
- HIDMA_EVRE_STATUS_ERROR
 
- HIDMA_HW_VERSION_OFFSET
 
- HIDMA_IDENTITY_CAP
 
- HIDMA_INCREMENT_ITERATOR
 
- HIDMA_IRQ_EV_CH_EOB_IRQ_BIT_POS
 
- HIDMA_IRQ_EV_CH_WR_RESP_BIT_POS
 
- HIDMA_IRQ_TR_CH_DATA_RD_ER_BIT_POS
 
- HIDMA_IRQ_TR_CH_DATA_WR_ER_BIT_POS
 
- HIDMA_IRQ_TR_CH_INVALID_TRE_BIT_POS
 
- HIDMA_IRQ_TR_CH_TRE_RD_RSP_ER_BIT_POS
 
- HIDMA_MAX_BUS_REQ_LEN_MASK
 
- HIDMA_MAX_BUS_REQ_LEN_OFFSET
 
- HIDMA_MAX_BUS_WR_REQ_BIT_POS
 
- HIDMA_MAX_CHANNEL_WEIGHT
 
- HIDMA_MAX_RD_XACTIONS_MASK
 
- HIDMA_MAX_WR_XACTIONS_BIT_POS
 
- HIDMA_MAX_WR_XACTIONS_MASK
 
- HIDMA_MAX_XACTIONS_OFFSET
 
- HIDMA_MSI_CAP
 
- HIDMA_MSI_INTS
 
- HIDMA_NR_DEFAULT_DESC
 
- HIDMA_PRIORITY_BIT_POS
 
- HIDMA_QOS_N_OFFSET
 
- HIDMA_TRCA_CTRLSTS_REG
 
- HIDMA_TRCA_DOORBELL_REG
 
- HIDMA_TRCA_RING_HIGH_REG
 
- HIDMA_TRCA_RING_LEN_REG
 
- HIDMA_TRCA_RING_LOW_REG
 
- HIDMA_TRE_CFG_IDX
 
- HIDMA_TRE_DEST_HI_IDX
 
- HIDMA_TRE_DEST_LOW_IDX
 
- HIDMA_TRE_LEN_IDX
 
- HIDMA_TRE_MEMCPY
 
- HIDMA_TRE_MEMSET
 
- HIDMA_TRE_SIZE
 
- HIDMA_TRE_SRC_HI_IDX
 
- HIDMA_TRE_SRC_LOW_IDX
 
- HIDMA_WEIGHT_MASK
 
- HIDMA_WRR_BIT_POS
 
- HIDPCONNADD
 
- HIDPCONNDEL
 
- HIDPGETCONNINFO
 
- HIDPGETCONNLIST
 
- HIDPP
 
- HIDPP20_ERROR
 
- HIDPP_AUTOCENTER_PARAMS_LENGTH
 
- HIDPP_CAPABILITY_BATTERY_LEVEL_STATUS
 
- HIDPP_CAPABILITY_BATTERY_MILEAGE
 
- HIDPP_CAPABILITY_HIDPP10_BATTERY
 
- HIDPP_CAPABILITY_HIDPP20_BATTERY
 
- HIDPP_DEVICE_NAME
 
- HIDPP_DEVICE_TYPE_KEYBOARD
 
- HIDPP_DEVICE_TYPE_MASK
 
- HIDPP_DEVICE_TYPE_MOUSE
 
- HIDPP_ENABLE_BAT_REPORT
 
- HIDPP_ENABLE_CONSUMER_REPORT
 
- HIDPP_ENABLE_FAST_SCROLL
 
- HIDPP_ENABLE_HWHEEL_REPORT
 
- HIDPP_ENABLE_MOUSE_EXTRA_BTN_REPORT
 
- HIDPP_ENABLE_SPECIAL_BUTTON_FUNC
 
- HIDPP_ENABLE_WHEEL_REPORT
 
- HIDPP_ERROR
 
- HIDPP_ERROR_ALREADY_EXISTS
 
- HIDPP_ERROR_BUSY
 
- HIDPP_ERROR_CONNECT_FAIL
 
- HIDPP_ERROR_INVALID_ADRESS
 
- HIDPP_ERROR_INVALID_PARAM_VALUE
 
- HIDPP_ERROR_INVALID_SUBID
 
- HIDPP_ERROR_INVALID_VALUE
 
- HIDPP_ERROR_REQUEST_UNAVAILABLE
 
- HIDPP_ERROR_RESOURCE_ERROR
 
- HIDPP_ERROR_SUCCESS
 
- HIDPP_ERROR_TOO_MANY_DEVICES
 
- HIDPP_ERROR_UNKNOWN_DEVICE
 
- HIDPP_ERROR_WRONG_PIN_CODE
 
- HIDPP_EXTENDED_PAIRING
 
- HIDPP_FAKE_DEVICE_ARRIVAL
 
- HIDPP_FF_DESTROY_EFFECT
 
- HIDPP_FF_DOWNLOAD_EFFECT
 
- HIDPP_FF_EFFECTID_AUTOCENTER
 
- HIDPP_FF_EFFECTID_NONE
 
- HIDPP_FF_EFFECT_AUTOSTART
 
- HIDPP_FF_EFFECT_CONSTANT
 
- HIDPP_FF_EFFECT_DAMPER
 
- HIDPP_FF_EFFECT_FRICTION
 
- HIDPP_FF_EFFECT_INERTIA
 
- HIDPP_FF_EFFECT_PERIODIC_SAWTOOTHDOWN
 
- HIDPP_FF_EFFECT_PERIODIC_SAWTOOTHUP
 
- HIDPP_FF_EFFECT_PERIODIC_SINE
 
- HIDPP_FF_EFFECT_PERIODIC_SQUARE
 
- HIDPP_FF_EFFECT_PERIODIC_TRIANGLE
 
- HIDPP_FF_EFFECT_RAMP
 
- HIDPP_FF_EFFECT_SPRING
 
- HIDPP_FF_EFFECT_STATE_GET
 
- HIDPP_FF_EFFECT_STATE_PAUSE
 
- HIDPP_FF_EFFECT_STATE_PLAY
 
- HIDPP_FF_EFFECT_STATE_STOP
 
- HIDPP_FF_GET_APERTURE
 
- HIDPP_FF_GET_GLOBAL_GAINS
 
- HIDPP_FF_GET_INFO
 
- HIDPP_FF_MAX_PARAMS
 
- HIDPP_FF_RESERVED_SLOTS
 
- HIDPP_FF_RESET_ALL
 
- HIDPP_FF_SET_APERTURE
 
- HIDPP_FF_SET_EFFECT_STATE
 
- HIDPP_FF_SET_GLOBAL_GAINS
 
- HIDPP_GET_LONG_REGISTER
 
- HIDPP_GET_REGISTER
 
- HIDPP_LINK_STATUS_MASK
 
- HIDPP_MANUFACTURER_MASK
 
- HIDPP_PAGE_BATTERY_LEVEL_STATUS
 
- HIDPP_PAGE_G920_FORCE_FEEDBACK
 
- HIDPP_PAGE_GET_DEVICE_NAME_TYPE
 
- HIDPP_PAGE_HIRES_WHEEL
 
- HIDPP_PAGE_HI_RESOLUTION_SCROLLING
 
- HIDPP_PAGE_ROOT
 
- HIDPP_PAGE_ROOT_IDX
 
- HIDPP_PAGE_SOLAR_KEYBOARD
 
- HIDPP_PAGE_TOUCHPAD_FW_ITEMS
 
- HIDPP_PAGE_TOUCHPAD_RAW_XY
 
- HIDPP_PAIRING_INFORMATION
 
- HIDPP_PARAM_27MHZ_DEVID
 
- HIDPP_PARAM_DEVICE_INFO
 
- HIDPP_PARAM_EQUAD_LSB
 
- HIDPP_PARAM_EQUAD_MSB
 
- HIDPP_PARAM_PROTO_TYPE
 
- HIDPP_QUIRK_CLASS_G920
 
- HIDPP_QUIRK_CLASS_K400
 
- HIDPP_QUIRK_CLASS_K750
 
- HIDPP_QUIRK_CLASS_M560
 
- HIDPP_QUIRK_CLASS_WTP
 
- HIDPP_QUIRK_DELAYED_INIT
 
- HIDPP_QUIRK_FORCE_OUTPUT_REPORTS
 
- HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS
 
- HIDPP_QUIRK_HIDPP_EXTRA_MOUSE_BTNS
 
- HIDPP_QUIRK_HIDPP_WHEELS
 
- HIDPP_QUIRK_HI_RES_SCROLL
 
- HIDPP_QUIRK_HI_RES_SCROLL_1P0
 
- HIDPP_QUIRK_HI_RES_SCROLL_X2120
 
- HIDPP_QUIRK_HI_RES_SCROLL_X2121
 
- HIDPP_QUIRK_KBD_SCROLL_WHEEL
 
- HIDPP_QUIRK_KBD_ZOOM_WHEEL
 
- HIDPP_QUIRK_NO_HIDINPUT
 
- HIDPP_QUIRK_UNIFYING
 
- HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS
 
- HIDPP_RECEIVER_INDEX
 
- HIDPP_REG_BATTERY_MILEAGE
 
- HIDPP_REG_BATTERY_STATUS
 
- HIDPP_REG_CONNECTION_STATE
 
- HIDPP_REG_ENABLE_REPORTS
 
- HIDPP_REG_FEATURES
 
- HIDPP_REG_PAIRING_INFORMATION
 
- HIDPP_REPORT_LONG_LENGTH
 
- HIDPP_REPORT_SHORT_LENGTH
 
- HIDPP_REPORT_VERY_LONG_MAX_LENGTH
 
- HIDPP_SET_LONG_REGISTER
 
- HIDPP_SET_REGISTER
 
- HIDPP_SUB_ID_CONSUMER_VENDOR_KEYS
 
- HIDPP_SUB_ID_MOUSE_EXTRA_BTNS
 
- HIDPP_SUB_ID_ROLLER
 
- HIDP_BLUETOOTH_VENDOR_ID
 
- HIDP_BOOT_PROTOCOL_MODE
 
- HIDP_CTRL_EXIT_SUSPEND
 
- HIDP_CTRL_HARD_RESET
 
- HIDP_CTRL_NOP
 
- HIDP_CTRL_SOFT_RESET
 
- HIDP_CTRL_SUSPEND
 
- HIDP_CTRL_VIRTUAL_CABLE_UNPLUG
 
- HIDP_DATA_RSRVD_MASK
 
- HIDP_DATA_RTYPE_FEATURE
 
- HIDP_DATA_RTYPE_INPUT
 
- HIDP_DATA_RTYPE_MASK
 
- HIDP_DATA_RTYPE_OTHER
 
- HIDP_DATA_RTYPE_OUPUT
 
- HIDP_HEADER_PARAM_MASK
 
- HIDP_HEADER_TRANS_MASK
 
- HIDP_HSHK_ERR_FATAL
 
- HIDP_HSHK_ERR_INVALID_PARAMETER
 
- HIDP_HSHK_ERR_INVALID_REPORT_ID
 
- HIDP_HSHK_ERR_UNKNOWN
 
- HIDP_HSHK_ERR_UNSUPPORTED_REQUEST
 
- HIDP_HSHK_NOT_READY
 
- HIDP_HSHK_SUCCESSFUL
 
- HIDP_PROTO_BOOT
 
- HIDP_PROTO_REPORT
 
- HIDP_SESSION_IDLING
 
- HIDP_SESSION_PREPARING
 
- HIDP_SESSION_RUNNING
 
- HIDP_TRANS_DATA
 
- HIDP_TRANS_DATC
 
- HIDP_TRANS_GET_IDLE
 
- HIDP_TRANS_GET_PROTOCOL
 
- HIDP_TRANS_GET_REPORT
 
- HIDP_TRANS_HANDSHAKE
 
- HIDP_TRANS_HID_CONTROL
 
- HIDP_TRANS_SET_IDLE
 
- HIDP_TRANS_SET_PROTOCOL
 
- HIDP_TRANS_SET_REPORT
 
- HIDP_VIRTUAL_CABLE_UNPLUG
 
- HIDP_WAITING_FOR_RETURN
 
- HIDP_WAITING_FOR_SEND_ACK
 
- HIDRAW_BUFFER_SIZE
 
- HIDRAW_FIRST_MINOR
 
- HIDRAW_MAX_DEVICES
 
- HIDSP_DAT_IN_OFF
 
- HIDSP_INPUT_CLIPPING
 
- HIDSP_INT_PLAY_UNDER
 
- HIDSP_INT_RECORD_OVER
 
- HIDSP_MIDI_FRAME_ERR
 
- HIDSP_MIDI_IN_OVER
 
- HIDSP_MIDI_OVERRUN_ERR
 
- HIDSP_MIDI_PARITY_ERR
 
- HIDSP_MIX_CLIPPING
 
- HIDSP_PLAY_UNDER
 
- HIDSP_RECQ_OVERFLOW
 
- HIDSP_SSI_RX_OVERFLOW
 
- HIDSP_SSI_TX_UNDER
 
- HIDWORD
 
- HIDX_BITS
 
- HIDX_SHIFT_BY_ONE
 
- HIDX_UNSHIFT_BY_ONE
 
- HID_AD_BRIGHTNESS
 
- HID_ANY_ID
 
- HID_BATTERY_QUERIED
 
- HID_BATTERY_QUIRK_FEATURE
 
- HID_BATTERY_QUIRK_IGNORE
 
- HID_BATTERY_QUIRK_PERCENT
 
- HID_BATTERY_REPORTED
 
- HID_BATTERY_UNKNOWN
 
- HID_BLUETOOTH_DEVICE
 
- HID_BOOT_PROTOCOL
 
- HID_BUS_ANY
 
- HID_CLAIMED_DRIVER
 
- HID_CLAIMED_HIDDEV
 
- HID_CLAIMED_HIDRAW
 
- HID_CLAIMED_INPUT
 
- HID_CLEAR_HALT
 
- HID_CL_RX_RING_SIZE
 
- HID_CL_TX_RING_SIZE
 
- HID_COLLECTION_APPLICATION
 
- HID_COLLECTION_LOGICAL
 
- HID_COLLECTION_PHYSICAL
 
- HID_COLLECTION_STACK_SIZE
 
- HID_CONNECT_DEFAULT
 
- HID_CONNECT_DRIVER
 
- HID_CONNECT_FF
 
- HID_CONNECT_HIDDEV
 
- HID_CONNECT_HIDDEV_FORCE
 
- HID_CONNECT_HIDINPUT
 
- HID_CONNECT_HIDINPUT_FORCE
 
- HID_CONNECT_HIDRAW
 
- HID_CONTROL_FIFO_SIZE
 
- HID_COUNTRY_INTERNATIONAL_ISO
 
- HID_CP_AC_PAN
 
- HID_CP_APPLICATIONLAUNCHBUTTONS
 
- HID_CP_CHANNELCENTER
 
- HID_CP_CHANNELCENTERFRONT
 
- HID_CP_CHANNELFRONT
 
- HID_CP_CHANNELLEFT
 
- HID_CP_CHANNELLOWFREQUENCYENHANCEMENT
 
- HID_CP_CHANNELRIGHT
 
- HID_CP_CHANNELSIDE
 
- HID_CP_CHANNELSURROUND
 
- HID_CP_CHANNELTOP
 
- HID_CP_CHANNELUNKNOWN
 
- HID_CP_CONSUMERCONTROL
 
- HID_CP_CONSUMER_CONTROL
 
- HID_CP_FUNCTIONBUTTONS
 
- HID_CP_GENERICGUIAPPLICATIONCONTROLS
 
- HID_CP_GRAPHICEQUALIZER
 
- HID_CP_HEADPHONE
 
- HID_CP_MEDIASELECTION
 
- HID_CP_MICROPHONE
 
- HID_CP_NUMERICKEYPAD
 
- HID_CP_PLAYBACKSPEED
 
- HID_CP_PROGRAMMABLEBUTTONS
 
- HID_CP_PROXIMITY
 
- HID_CP_SELECTDISC
 
- HID_CP_SELECTION
 
- HID_CP_SPEAKERSYSTEM
 
- HID_CTRL_RUNNING
 
- HID_CUSTOM_FIFO_SIZE
 
- HID_CUSTOM_MAX_CORE_ATTRS
 
- HID_CUSTOM_MAX_FEATURE_BYTES
 
- HID_CUSTOM_NAME_LENGTH
 
- HID_CUSTOM_TOTAL_ATTRS
 
- HID_DC_BATTERYSTRENGTH
 
- HID_DEBUG_BUFSIZE
 
- HID_DEBUG_FIFOSIZE
 
- HID_DEFAULT_NUM_COLLECTIONS
 
- HID_DESCRIPTOR_SIZE
 
- HID_DEVICE
 
- HID_DEVICE_ID_ALPS_1222
 
- HID_DEVICE_ID_ALPS_T4_BTNLESS
 
- HID_DEVICE_ID_ALPS_U1
 
- HID_DEVICE_ID_ALPS_U1_DUAL
 
- HID_DEVICE_ID_ALPS_U1_DUAL_3BTN_PTP
 
- HID_DEVICE_ID_ALPS_U1_DUAL_PTP
 
- HID_DEVICE_ID_ALPS_U1_UNICORN_LEGACY
 
- HID_DEVICE_TYPE
 
- HID_DG_AZIMUTH
 
- HID_DG_BARRELPRESSURE
 
- HID_DG_BARRELSWITCH
 
- HID_DG_BARRELSWITCH2
 
- HID_DG_BATTERYSTRENGTH
 
- HID_DG_BUTTONSWITCH
 
- HID_DG_BUTTONTYPE
 
- HID_DG_CONFIDENCE
 
- HID_DG_CONTACTCOUNT
 
- HID_DG_CONTACTID
 
- HID_DG_CONTACTMAX
 
- HID_DG_DEVICECONFIG
 
- HID_DG_DEVICEINDEX
 
- HID_DG_DEVICESETTINGS
 
- HID_DG_DIGITIZER
 
- HID_DG_ERASER
 
- HID_DG_FINGER
 
- HID_DG_HEIGHT
 
- HID_DG_INPUTMODE
 
- HID_DG_INRANGE
 
- HID_DG_INVERT
 
- HID_DG_LATENCYMODE
 
- HID_DG_LIGHTPEN
 
- HID_DG_PEN
 
- HID_DG_PROGRAMCHANGEKEY
 
- HID_DG_PUCK
 
- HID_DG_SCANTIME
 
- HID_DG_STYLUS
 
- HID_DG_SURFACESWITCH
 
- HID_DG_TABLETFUNCTIONKEY
 
- HID_DG_TABLETPICK
 
- HID_DG_TAP
 
- HID_DG_TILT_X
 
- HID_DG_TILT_Y
 
- HID_DG_TIPPRESSURE
 
- HID_DG_TIPSWITCH
 
- HID_DG_TIPSWITCH2
 
- HID_DG_TOOLSERIALNUMBER
 
- HID_DG_TOUCH
 
- HID_DG_TOUCHPAD
 
- HID_DG_TOUCHSCREEN
 
- HID_DG_TWIST
 
- HID_DG_UNTOUCH
 
- HID_DG_WHITEBOARD
 
- HID_DG_WIDTH
 
- HID_DISCONNECTED
 
- HID_DOWNLOAD
 
- HID_DT_HID
 
- HID_DT_PHYSICAL
 
- HID_DT_REPORT
 
- HID_EVENT_FILTER_UUID
 
- HID_FEATURE_REPORT
 
- HID_FIELD_BUFFERED_BYTE
 
- HID_FIELD_CONSTANT
 
- HID_FIELD_INDEX_NONE
 
- HID_FIELD_NONLINEAR
 
- HID_FIELD_NO_PREFERRED
 
- HID_FIELD_NULL_STATE
 
- HID_FIELD_RELATIVE
 
- HID_FIELD_VARIABLE
 
- HID_FIELD_VOLATILE
 
- HID_FIELD_WRAP
 
- HID_GD_BUFFER
 
- HID_GD_BYTECOUNT
 
- HID_GD_DIAL
 
- HID_GD_DOWN
 
- HID_GD_FEATURE
 
- HID_GD_GAMEPAD
 
- HID_GD_HATSWITCH
 
- HID_GD_JOYSTICK
 
- HID_GD_KEYBOARD
 
- HID_GD_KEYPAD
 
- HID_GD_LEFT
 
- HID_GD_MOTION
 
- HID_GD_MOUSE
 
- HID_GD_MULTIAXIS
 
- HID_GD_POINTER
 
- HID_GD_RESOLUTION_MULTIPLIER
 
- HID_GD_RFKILL_BTN
 
- HID_GD_RFKILL_LED
 
- HID_GD_RFKILL_SWITCH
 
- HID_GD_RIGHT
 
- HID_GD_RX
 
- HID_GD_RY
 
- HID_GD_RZ
 
- HID_GD_SELECT
 
- HID_GD_SLIDER
 
- HID_GD_START
 
- HID_GD_SYSTEM_CONTROL
 
- HID_GD_SYSTEM_MULTIAXIS
 
- HID_GD_UP
 
- HID_GD_VBRX
 
- HID_GD_VBRY
 
- HID_GD_VBRZ
 
- HID_GD_VNO
 
- HID_GD_VX
 
- HID_GD_VY
 
- HID_GD_VZ
 
- HID_GD_WHEEL
 
- HID_GD_WIRELESS_RADIO_CTLS
 
- HID_GD_X
 
- HID_GD_Y
 
- HID_GD_Z
 
- HID_GENERIC
 
- HID_GLOBAL_ITEM_TAG_LOGICAL_MAXIMUM
 
- HID_GLOBAL_ITEM_TAG_LOGICAL_MINIMUM
 
- HID_GLOBAL_ITEM_TAG_PHYSICAL_MAXIMUM
 
- HID_GLOBAL_ITEM_TAG_PHYSICAL_MINIMUM
 
- HID_GLOBAL_ITEM_TAG_POP
 
- HID_GLOBAL_ITEM_TAG_PUSH
 
- HID_GLOBAL_ITEM_TAG_REPORT_COUNT
 
- HID_GLOBAL_ITEM_TAG_REPORT_ID
 
- HID_GLOBAL_ITEM_TAG_REPORT_SIZE
 
- HID_GLOBAL_ITEM_TAG_UNIT
 
- HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT
 
- HID_GLOBAL_ITEM_TAG_USAGE_PAGE
 
- HID_GLOBAL_STACK_SIZE
 
- HID_GROUP_ANY
 
- HID_GROUP_GENERIC
 
- HID_GROUP_LOGITECH_27MHZ_DEVICE
 
- HID_GROUP_LOGITECH_DJ_DEVICE
 
- HID_GROUP_MULTITOUCH
 
- HID_GROUP_MULTITOUCH_WIN_8
 
- HID_GROUP_RMI
 
- HID_GROUP_SENSOR_HUB
 
- HID_GROUP_STEAM
 
- HID_GROUP_WACOM
 
- HID_I2C_DEVICE
 
- HID_IDS_H_FILE
 
- HID_INPUT_REPORT
 
- HID_IN_POLLING
 
- HID_IN_RUNNING
 
- HID_IR0
 
- HID_IR1
 
- HID_IR2
 
- HID_IR3
 
- HID_ITEM_FORMAT_LONG
 
- HID_ITEM_FORMAT_SHORT
 
- HID_ITEM_TAG_LONG
 
- HID_ITEM_TYPE_GLOBAL
 
- HID_ITEM_TYPE_LOCAL
 
- HID_ITEM_TYPE_MAIN
 
- HID_ITEM_TYPE_RESERVED
 
- HID_KEYS_PRESSED
 
- HID_LATENCY_HIGH
 
- HID_LATENCY_NORMAL
 
- HID_LOCAL_ITEM_TAG_DELIMITER
 
- HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX
 
- HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM
 
- HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM
 
- HID_LOCAL_ITEM_TAG_STRING_INDEX
 
- HID_LOCAL_ITEM_TAG_STRING_MAXIMUM
 
- HID_LOCAL_ITEM_TAG_STRING_MINIMUM
 
- HID_LOCAL_ITEM_TAG_USAGE
 
- HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM
 
- HID_LOCAL_ITEM_TAG_USAGE_MINIMUM
 
- HID_MAIN_ITEM_BUFFERED_BYTE
 
- HID_MAIN_ITEM_CONSTANT
 
- HID_MAIN_ITEM_NONLINEAR
 
- HID_MAIN_ITEM_NO_PREFERRED
 
- HID_MAIN_ITEM_NULL_STATE
 
- HID_MAIN_ITEM_RELATIVE
 
- HID_MAIN_ITEM_TAG_BEGIN_COLLECTION
 
- HID_MAIN_ITEM_TAG_END_COLLECTION
 
- HID_MAIN_ITEM_TAG_FEATURE
 
- HID_MAIN_ITEM_TAG_INPUT
 
- HID_MAIN_ITEM_TAG_OUTPUT
 
- HID_MAIN_ITEM_VARIABLE
 
- HID_MAIN_ITEM_VOLATILE
 
- HID_MAIN_ITEM_WRAP
 
- HID_MAX_BUFFER_SIZE
 
- HID_MAX_DESCRIPTOR_SIZE
 
- HID_MAX_FIELDS
 
- HID_MAX_IDS
 
- HID_MAX_MULTI_USAGES
 
- HID_MAX_PHY_DEVICES
 
- HID_MAX_USAGES
 
- HID_MFG
 
- HID_MIN_BUFFER_SIZE
 
- HID_NO_BANDWIDTH
 
- HID_OPENED
 
- HID_OR0
 
- HID_OR1
 
- HID_OR2
 
- HID_OR3
 
- HID_OR_GENERIC_HID_REG
 
- HID_OR_GPO_BUZ_SPDIF
 
- HID_OR_MAP_MCU_EEPROM
 
- HID_OUTPUT_FIFO_SIZE
 
- HID_OUTPUT_REPORT
 
- HID_OUT_RUNNING
 
- HID_PRD
 
- HID_PRODUCT_ID_COSMO
 
- HID_PRODUCT_ID_T3_BTNLESS
 
- HID_PRODUCT_ID_T4_BTNLESS
 
- HID_PRODUCT_ID_U1
 
- HID_PRODUCT_ID_U1_DUAL
 
- HID_PRODUCT_ID_U1_PTP_1
 
- HID_PRODUCT_ID_U1_PTP_2
 
- HID_QUIRK_ALWAYS_POLL
 
- HID_QUIRK_BADPAD
 
- HID_QUIRK_FULLSPEED_INTERVAL
 
- HID_QUIRK_HAVE_SPECIAL_DRIVER
 
- HID_QUIRK_HIDDEV_FORCE
 
- HID_QUIRK_HIDINPUT_FORCE
 
- HID_QUIRK_IGNORE
 
- HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE
 
- HID_QUIRK_INPUT_PER_APP
 
- HID_QUIRK_INVERT
 
- HID_QUIRK_MULTI_INPUT
 
- HID_QUIRK_NOGET
 
- HID_QUIRK_NOTOUCH
 
- HID_QUIRK_NO_IGNORE
 
- HID_QUIRK_NO_INIT_REPORTS
 
- HID_QUIRK_NO_INPUT_SYNC
 
- HID_QUIRK_NO_OUTPUT_REPORTS_ON_INTR_EP
 
- HID_QUIRK_SKIP_OUTPUT_REPORTS
 
- HID_QUIRK_SKIP_OUTPUT_REPORT_ID
 
- HID_REPORT_ID
 
- HID_REPORT_ID_FIRST
 
- HID_REPORT_ID_MASK
 
- HID_REPORT_ID_MAX
 
- HID_REPORT_ID_NEXT
 
- HID_REPORT_ID_UNKNOWN
 
- HID_REPORT_PROTOCOL
 
- HID_REPORT_SIZE
 
- HID_REPORT_TYPES
 
- HID_REPORT_TYPE_FEATURE
 
- HID_REPORT_TYPE_INPUT
 
- HID_REPORT_TYPE_MAX
 
- HID_REPORT_TYPE_MIN
 
- HID_REPORT_TYPE_OUTPUT
 
- HID_REQ_GET_IDLE
 
- HID_REQ_GET_PROTOCOL
 
- HID_REQ_GET_REPORT
 
- HID_REQ_SET_IDLE
 
- HID_REQ_SET_PROTOCOL
 
- HID_REQ_SET_REPORT
 
- HID_RESET_PENDING
 
- HID_RESUME_RUNNING
 
- HID_REV
 
- HID_SCAN_FLAG_GD_POINTER
 
- HID_SCAN_FLAG_MT_WIN_8
 
- HID_SCAN_FLAG_VENDOR_SPECIFIC
 
- HID_SENSOR_HUB_ENUM_QUIRK
 
- HID_STARTED
 
- HID_STAT_ADDED
 
- HID_STAT_DUP_DETECTED
 
- HID_STAT_PARSED
 
- HID_STAT_REPROBED
 
- HID_STRING_SIZE
 
- HID_SUSPENDED
 
- HID_TERMINATOR
 
- HID_TYPE_OTHER
 
- HID_TYPE_USBMOUSE
 
- HID_TYPE_USBNONE
 
- HID_UP_ASUSVENDOR
 
- HID_UP_BUTTON
 
- HID_UP_CONSUMER
 
- HID_UP_CUSTOM
 
- HID_UP_DIGITIZER
 
- HID_UP_GENDESK
 
- HID_UP_GENDEVCTRLS
 
- HID_UP_GOOGLEVENDOR
 
- HID_UP_HPVENDOR
 
- HID_UP_HPVENDOR2
 
- HID_UP_KEYBOARD
 
- HID_UP_LED
 
- HID_UP_LNVENDOR
 
- HID_UP_LOGIVENDOR
 
- HID_UP_LOGIVENDOR2
 
- HID_UP_LOGIVENDOR3
 
- HID_UP_MSVENDOR
 
- HID_UP_ORDINAL
 
- HID_UP_PID
 
- HID_UP_SENSOR
 
- HID_UP_SIMULATION
 
- HID_UP_TELEPHONY
 
- HID_UP_TIVOVENDOR
 
- HID_UP_UNDEFINED
 
- HID_UP_VENDOR_DEFINED_MAX
 
- HID_UP_VENDOR_DEFINED_MIN
 
- HID_USAGE
 
- HID_USAGE_ID
 
- HID_USAGE_PAGE
 
- HID_USAGE_SENSOR_ACCEL_3D
 
- HID_USAGE_SENSOR_ACCEL_X_AXIS
 
- HID_USAGE_SENSOR_ACCEL_Y_AXIS
 
- HID_USAGE_SENSOR_ACCEL_Z_AXIS
 
- HID_USAGE_SENSOR_ALS
 
- HID_USAGE_SENSOR_ANGL_VELOCITY_X_AXIS
 
- HID_USAGE_SENSOR_ANGL_VELOCITY_Y_AXIS
 
- HID_USAGE_SENSOR_ANGL_VELOCITY_Z_AXIS
 
- HID_USAGE_SENSOR_ATMOSPHERIC_HUMIDITY
 
- HID_USAGE_SENSOR_ATMOSPHERIC_PRESSURE
 
- HID_USAGE_SENSOR_COLLECTION
 
- HID_USAGE_SENSOR_COMPASS_3D
 
- HID_USAGE_SENSOR_DATA_ACCELERATION
 
- HID_USAGE_SENSOR_DATA_ANGL_VELOCITY
 
- HID_USAGE_SENSOR_DATA_ATMOSPHERIC_PRESSURE
 
- HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE
 
- HID_USAGE_SENSOR_DATA_LIGHT
 
- HID_USAGE_SENSOR_DATA_MOD_CHANGE_SENSITIVITY_ABS
 
- HID_USAGE_SENSOR_DATA_MOD_NONE
 
- HID_USAGE_SENSOR_DATA_ORIENTATION
 
- HID_USAGE_SENSOR_DATA_PRESENCE
 
- HID_USAGE_SENSOR_DEVICE_ORIENTATION
 
- HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION
 
- HID_USAGE_SENSOR_GRAVITY_VECTOR
 
- HID_USAGE_SENSOR_GYRO_3D
 
- HID_USAGE_SENSOR_HUMAN_PRESENCE
 
- HID_USAGE_SENSOR_HUMIDITY
 
- HID_USAGE_SENSOR_INCLINOMETER_3D
 
- HID_USAGE_SENSOR_LIGHT_ILLUM
 
- HID_USAGE_SENSOR_ORIENT_COMP_MAGN_NORTH
 
- HID_USAGE_SENSOR_ORIENT_COMP_TRUE_NORTH
 
- HID_USAGE_SENSOR_ORIENT_DISTANCE
 
- HID_USAGE_SENSOR_ORIENT_DISTANCE_OUT_OF_RANGE
 
- HID_USAGE_SENSOR_ORIENT_DISTANCE_X
 
- HID_USAGE_SENSOR_ORIENT_DISTANCE_Y
 
- HID_USAGE_SENSOR_ORIENT_DISTANCE_Z
 
- HID_USAGE_SENSOR_ORIENT_MAGN_FLUX
 
- HID_USAGE_SENSOR_ORIENT_MAGN_FLUX_X_AXIS
 
- HID_USAGE_SENSOR_ORIENT_MAGN_FLUX_Y_AXIS
 
- HID_USAGE_SENSOR_ORIENT_MAGN_FLUX_Z_AXIS
 
- HID_USAGE_SENSOR_ORIENT_MAGN_HEADING
 
- HID_USAGE_SENSOR_ORIENT_MAGN_HEADING_X
 
- HID_USAGE_SENSOR_ORIENT_MAGN_HEADING_Y
 
- HID_USAGE_SENSOR_ORIENT_MAGN_HEADING_Z
 
- HID_USAGE_SENSOR_ORIENT_MAGN_NORTH
 
- HID_USAGE_SENSOR_ORIENT_QUATERNION
 
- HID_USAGE_SENSOR_ORIENT_ROTATION_MATRIX
 
- HID_USAGE_SENSOR_ORIENT_TILT
 
- HID_USAGE_SENSOR_ORIENT_TILT_X
 
- HID_USAGE_SENSOR_ORIENT_TILT_Y
 
- HID_USAGE_SENSOR_ORIENT_TILT_Z
 
- HID_USAGE_SENSOR_ORIENT_TRUE_NORTH
 
- HID_USAGE_SENSOR_PRESSURE
 
- HID_USAGE_SENSOR_PROP_ACCURACY
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_D0_FULL_POWER_ENUM
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_D1_LOW_POWER_ENUM
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_D2_STANDBY_WITH_WAKE_ENUM
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_D3_SLEEP_WITH_WAKE_ENUM
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_D4_POWER_OFF_ENUM
 
- HID_USAGE_SENSOR_PROP_POWER_STATE_UNDEFINED_ENUM
 
- HID_USAGE_SENSOR_PROP_RANGE_MAXIMUM
 
- HID_USAGE_SENSOR_PROP_RANGE_MINIMUM
 
- HID_USAGE_SENSOR_PROP_REPORTING_STATE_ALL_EVENTS_ENUM
 
- HID_USAGE_SENSOR_PROP_REPORTING_STATE_NO_EVENTS_ENUM
 
- HID_USAGE_SENSOR_PROP_REPORT_INTERVAL
 
- HID_USAGE_SENSOR_PROP_REPORT_LATENCY
 
- HID_USAGE_SENSOR_PROP_REPORT_STATE
 
- HID_USAGE_SENSOR_PROP_RESOLUTION
 
- HID_USAGE_SENSOR_PROP_SENSITIVITY_ABS
 
- HID_USAGE_SENSOR_PROP_SENSITIVITY_RANGE_PCT
 
- HID_USAGE_SENSOR_PROP_SENSITIVITY_REL_PCT
 
- HID_USAGE_SENSOR_PROX
 
- HID_USAGE_SENSOR_PROY_POWER_STATE
 
- HID_USAGE_SENSOR_RELATIVE_ORIENTATION
 
- HID_USAGE_SENSOR_TEMPERATURE
 
- HID_USAGE_SENSOR_TIME
 
- HID_USAGE_SENSOR_TIME_DAY
 
- HID_USAGE_SENSOR_TIME_HOUR
 
- HID_USAGE_SENSOR_TIME_MINUTE
 
- HID_USAGE_SENSOR_TIME_MONTH
 
- HID_USAGE_SENSOR_TIME_SECOND
 
- HID_USAGE_SENSOR_TIME_TIMESTAMP
 
- HID_USAGE_SENSOR_TIME_YEAR
 
- HID_USAGE_SENSOR_UNITS_AMPERE
 
- HID_USAGE_SENSOR_UNITS_CENTIMETER
 
- HID_USAGE_SENSOR_UNITS_DEGREES
 
- HID_USAGE_SENSOR_UNITS_DEGREES_PER_SECOND
 
- HID_USAGE_SENSOR_UNITS_DEGREES_PER_SEC_SQRD
 
- HID_USAGE_SENSOR_UNITS_FAHRENHEIT
 
- HID_USAGE_SENSOR_UNITS_FARAD
 
- HID_USAGE_SENSOR_UNITS_G
 
- HID_USAGE_SENSOR_UNITS_GAUSS
 
- HID_USAGE_SENSOR_UNITS_GRAM
 
- HID_USAGE_SENSOR_UNITS_HENRY
 
- HID_USAGE_SENSOR_UNITS_HERTZ
 
- HID_USAGE_SENSOR_UNITS_KELVIN
 
- HID_USAGE_SENSOR_UNITS_LUX
 
- HID_USAGE_SENSOR_UNITS_METERS_PER_SECOND
 
- HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD
 
- HID_USAGE_SENSOR_UNITS_MILLISECOND
 
- HID_USAGE_SENSOR_UNITS_NEWTON
 
- HID_USAGE_SENSOR_UNITS_NOT_SPECIFIED
 
- HID_USAGE_SENSOR_UNITS_OHM
 
- HID_USAGE_SENSOR_UNITS_PASCAL
 
- HID_USAGE_SENSOR_UNITS_PERCENT
 
- HID_USAGE_SENSOR_UNITS_RADIANS
 
- HID_USAGE_SENSOR_UNITS_RADIANS_PER_SECOND
 
- HID_USAGE_SENSOR_UNITS_RADIANS_PER_SEC_SQRD
 
- HID_USAGE_SENSOR_UNITS_SECOND
 
- HID_USAGE_SENSOR_UNITS_VOLT
 
- HID_USAGE_SENSOR_UNITS_WATT
 
- HID_USB_DEVICE
 
- HID_VD_ASUS_CUSTOM_MEDIA_KEYS
 
- HID_VD_KBD_FOLDED
 
- HID_VERSION
 
- HIERARCHICAL_P_QP
 
- HIERARCHY_1
 
- HIERARCHY_2
 
- HIERARCHY_4
 
- HIERARCHY_AUTO
 
- HIERARCHY_INDENT
 
- HIERARCHY_NONE
 
- HIERARCHY_NUM
 
- HIER_ALPHA_1
 
- HIER_ALPHA_2
 
- HIER_ALPHA_4
 
- HIER_HIGH_PRIORITY
 
- HIER_INT_0_EN
 
- HIER_INT_1_EN
 
- HIER_INT_2_EN
 
- HIER_INT_3_EN
 
- HIER_INT_4_EN
 
- HIER_INT_5_EN
 
- HIER_INT_6_EN
 
- HIER_INT_7_EN
 
- HIER_INT_EN_MSK
 
- HIER_LOW_PRIORITY
 
- HIER_NONE
 
- HIER_NO_PRIORITY
 
- HIER_REG
 
- HIER_UNKNOWN
 
- HIF
 
- HIFACE_CHIP_H
 
- HIFACE_PCM_H
 
- HIFACE_RATE_176400
 
- HIFACE_RATE_192000
 
- HIFACE_RATE_352800
 
- HIFACE_RATE_384000
 
- HIFACE_RATE_44100
 
- HIFACE_RATE_48000
 
- HIFACE_RATE_88200
 
- HIFACE_RATE_96000
 
- HIFACE_SET_RATE_REQUEST
 
- HIFAR
 
- HIFCS_MARK
 
- HIFD00_MARK
 
- HIFD01_MARK
 
- HIFD02_MARK
 
- HIFD03_MARK
 
- HIFD04_MARK
 
- HIFD05_MARK
 
- HIFD06_MARK
 
- HIFD07_MARK
 
- HIFD08_MARK
 
- HIFD09_MARK
 
- HIFD10_MARK
 
- HIFD11_MARK
 
- HIFD12_MARK
 
- HIFD13_MARK
 
- HIFD14_MARK
 
- HIFD15_MARK
 
- HIFDREQ_MARK
 
- HIFEBL_A_MARK
 
- HIFEBL_B_MARK
 
- HIFINT_MARK
 
- HIFIX80
 
- HIFMC_DMA_MASK
 
- HIFMC_DMA_MAX_LEN
 
- HIFMC_MAX_CHIP_NUM
 
- HIFN_0_FIFOCNFG
 
- HIFN_0_FIFOSTAT
 
- HIFN_0_PUCNFG
 
- HIFN_0_PUCTRL
 
- HIFN_0_PUDATA
 
- HIFN_0_PUIER
 
- HIFN_0_PUISR
 
- HIFN_0_PUSTAT
 
- HIFN_0_SPACESIZE
 
- HIFN_1_7811_MIPSRST
 
- HIFN_1_7811_RNGCFG
 
- HIFN_1_7811_RNGDAT
 
- HIFN_1_7811_RNGENA
 
- HIFN_1_7811_RNGSTS
 
- HIFN_1_DMA_CNFG
 
- HIFN_1_DMA_CRAR
 
- HIFN_1_DMA_CSR
 
- HIFN_1_DMA_DRAR
 
- HIFN_1_DMA_IER
 
- HIFN_1_DMA_RRAR
 
- HIFN_1_DMA_SRAR
 
- HIFN_1_PLL
 
- HIFN_1_PUB_BASE
 
- HIFN_1_PUB_IEN
 
- HIFN_1_PUB_MEM
 
- HIFN_1_PUB_MEMEND
 
- HIFN_1_PUB_OP
 
- HIFN_1_PUB_OPLEN
 
- HIFN_1_PUB_RESET
 
- HIFN_1_PUB_STATUS
 
- HIFN_1_REVID
 
- HIFN_1_RNG_CONFIG
 
- HIFN_1_RNG_DATA
 
- HIFN_1_UNLOCK_SECRET1
 
- HIFN_1_UNLOCK_SECRET2
 
- HIFN_3DES_KEY_LENGTH
 
- HIFN_AES_IV_LENGTH
 
- HIFN_BAR0_SIZE
 
- HIFN_BAR1_SIZE
 
- HIFN_BAR2_SIZE
 
- HIFN_BASE_CMD_COMP
 
- HIFN_BASE_CMD_CRYPT
 
- HIFN_BASE_CMD_DECODE
 
- HIFN_BASE_CMD_DSTLEN_M
 
- HIFN_BASE_CMD_DSTLEN_S
 
- HIFN_BASE_CMD_LENMASK_HI
 
- HIFN_BASE_CMD_LENMASK_LO
 
- HIFN_BASE_CMD_MAC
 
- HIFN_BASE_CMD_PAD
 
- HIFN_BASE_CMD_SRCLEN_M
 
- HIFN_BASE_CMD_SRCLEN_S
 
- HIFN_BASE_RES_DSTLEN_M
 
- HIFN_BASE_RES_DSTLEN_S
 
- HIFN_BASE_RES_DSTOVERRUN
 
- HIFN_BASE_RES_SRCLEN_M
 
- HIFN_BASE_RES_SRCLEN_S
 
- HIFN_CHIP_ID
 
- HIFN_COMP_CMD_ALG_LZS
 
- HIFN_COMP_CMD_ALG_MASK
 
- HIFN_COMP_CMD_ALG_MPPC
 
- HIFN_COMP_CMD_CLEARHIST
 
- HIFN_COMP_CMD_LZS_STRIP0
 
- HIFN_COMP_CMD_MPPC_RESTART
 
- HIFN_COMP_CMD_ONE
 
- HIFN_COMP_CMD_SRCLEN_M
 
- HIFN_COMP_CMD_SRCLEN_S
 
- HIFN_COMP_CMD_UPDATEHIST
 
- HIFN_COMP_RES_ENDMARKER
 
- HIFN_COMP_RES_LCB_M
 
- HIFN_COMP_RES_LCB_S
 
- HIFN_COMP_RES_RESTART
 
- HIFN_COMP_RES_SRC_NOTZERO
 
- HIFN_CRYPT_CMD_ALG_3DES
 
- HIFN_CRYPT_CMD_ALG_AES
 
- HIFN_CRYPT_CMD_ALG_DES
 
- HIFN_CRYPT_CMD_ALG_MASK
 
- HIFN_CRYPT_CMD_ALG_RC4
 
- HIFN_CRYPT_CMD_CLR_CTX
 
- HIFN_CRYPT_CMD_KSZ_128
 
- HIFN_CRYPT_CMD_KSZ_192
 
- HIFN_CRYPT_CMD_KSZ_256
 
- HIFN_CRYPT_CMD_KSZ_MASK
 
- HIFN_CRYPT_CMD_MODE_CBC
 
- HIFN_CRYPT_CMD_MODE_CFB
 
- HIFN_CRYPT_CMD_MODE_ECB
 
- HIFN_CRYPT_CMD_MODE_MASK
 
- HIFN_CRYPT_CMD_MODE_OFB
 
- HIFN_CRYPT_CMD_NEW_IV
 
- HIFN_CRYPT_CMD_NEW_KEY
 
- HIFN_CRYPT_CMD_SRCLEN_M
 
- HIFN_CRYPT_CMD_SRCLEN_S
 
- HIFN_CRYPT_RES_SRC_NOTZERO
 
- HIFN_DEFAULT_ACTIVE_NUM
 
- HIFN_DES_KEY_LENGTH
 
- HIFN_DMACNFG_BIGENDIAN
 
- HIFN_DMACNFG_DMARESET
 
- HIFN_DMACNFG_LAST
 
- HIFN_DMACNFG_MODE
 
- HIFN_DMACNFG_MSTRESET
 
- HIFN_DMACNFG_POLLFREQ
 
- HIFN_DMACNFG_POLLINVAL
 
- HIFN_DMACNFG_UNLOCK
 
- HIFN_DMACSR_C_ABORT
 
- HIFN_DMACSR_C_CTRL
 
- HIFN_DMACSR_C_CTRL_DIS
 
- HIFN_DMACSR_C_CTRL_ENA
 
- HIFN_DMACSR_C_CTRL_NOP
 
- HIFN_DMACSR_C_DONE
 
- HIFN_DMACSR_C_LAST
 
- HIFN_DMACSR_C_WAIT
 
- HIFN_DMACSR_D_ABORT
 
- HIFN_DMACSR_D_CTRLMASK
 
- HIFN_DMACSR_D_CTRL_DIS
 
- HIFN_DMACSR_D_CTRL_ENA
 
- HIFN_DMACSR_D_CTRL_NOP
 
- HIFN_DMACSR_D_DONE
 
- HIFN_DMACSR_D_LAST
 
- HIFN_DMACSR_D_OVER
 
- HIFN_DMACSR_D_WAIT
 
- HIFN_DMACSR_ENGINE
 
- HIFN_DMACSR_ILLR
 
- HIFN_DMACSR_ILLW
 
- HIFN_DMACSR_PUBDONE
 
- HIFN_DMACSR_R_ABORT
 
- HIFN_DMACSR_R_CTRL
 
- HIFN_DMACSR_R_CTRL_DIS
 
- HIFN_DMACSR_R_CTRL_ENA
 
- HIFN_DMACSR_R_CTRL_NOP
 
- HIFN_DMACSR_R_DONE
 
- HIFN_DMACSR_R_LAST
 
- HIFN_DMACSR_R_OVER
 
- HIFN_DMACSR_R_WAIT
 
- HIFN_DMACSR_S_ABORT
 
- HIFN_DMACSR_S_CTRL
 
- HIFN_DMACSR_S_CTRL_DIS
 
- HIFN_DMACSR_S_CTRL_ENA
 
- HIFN_DMACSR_S_CTRL_NOP
 
- HIFN_DMACSR_S_DONE
 
- HIFN_DMACSR_S_LAST
 
- HIFN_DMACSR_S_WAIT
 
- HIFN_DMAIER_C_ABORT
 
- HIFN_DMAIER_C_DONE
 
- HIFN_DMAIER_C_LAST
 
- HIFN_DMAIER_C_WAIT
 
- HIFN_DMAIER_D_ABORT
 
- HIFN_DMAIER_D_DONE
 
- HIFN_DMAIER_D_LAST
 
- HIFN_DMAIER_D_OVER
 
- HIFN_DMAIER_D_WAIT
 
- HIFN_DMAIER_ENGINE
 
- HIFN_DMAIER_ILLR
 
- HIFN_DMAIER_ILLW
 
- HIFN_DMAIER_PUBDONE
 
- HIFN_DMAIER_R_ABORT
 
- HIFN_DMAIER_R_DONE
 
- HIFN_DMAIER_R_LAST
 
- HIFN_DMAIER_R_OVER
 
- HIFN_DMAIER_R_WAIT
 
- HIFN_DMAIER_S_ABORT
 
- HIFN_DMAIER_S_DONE
 
- HIFN_DMAIER_S_LAST
 
- HIFN_DMAIER_S_WAIT
 
- HIFN_DMA_CFG1
 
- HIFN_DMA_CFG2
 
- HIFN_DMA_CRA
 
- HIFN_DMA_DDRA
 
- HIFN_DMA_INTREN
 
- HIFN_DMA_RRA
 
- HIFN_DMA_SDRA
 
- HIFN_DMA_STCTL
 
- HIFN_D_CMD_RSIZE
 
- HIFN_D_DESTOVER
 
- HIFN_D_DST_DALIGN
 
- HIFN_D_DST_RSIZE
 
- HIFN_D_JUMP
 
- HIFN_D_LAST
 
- HIFN_D_LENGTH
 
- HIFN_D_MASKDONEIRQ
 
- HIFN_D_NOINVALID
 
- HIFN_D_OVER
 
- HIFN_D_RES_RSIZE
 
- HIFN_D_SRC_RSIZE
 
- HIFN_D_VALID
 
- HIFN_FIFOCNFG_THRESHOLD
 
- HIFN_FIFOSTAT_DST
 
- HIFN_FIFOSTAT_SRC
 
- HIFN_FLAG_CMD_BUSY
 
- HIFN_FLAG_DST_BUSY
 
- HIFN_FLAG_OLD_KEY
 
- HIFN_FLAG_RES_BUSY
 
- HIFN_FLAG_SRC_BUSY
 
- HIFN_IV_LENGTH
 
- HIFN_MAC_CMD_ALG_MASK
 
- HIFN_MAC_CMD_ALG_MD5
 
- HIFN_MAC_CMD_ALG_SHA1
 
- HIFN_MAC_CMD_APPEND
 
- HIFN_MAC_CMD_MODE_FULL
 
- HIFN_MAC_CMD_MODE_HASH
 
- HIFN_MAC_CMD_MODE_HMAC
 
- HIFN_MAC_CMD_MODE_MASK
 
- HIFN_MAC_CMD_MODE_SSL_MAC
 
- HIFN_MAC_CMD_NEW_KEY
 
- HIFN_MAC_CMD_POS_IPSEC
 
- HIFN_MAC_CMD_RESULT
 
- HIFN_MAC_CMD_SRCLEN_M
 
- HIFN_MAC_CMD_SRCLEN_S
 
- HIFN_MAC_CMD_TRUNC
 
- HIFN_MAC_KEY_LENGTH
 
- HIFN_MAC_RES_MISCOMPARE
 
- HIFN_MAC_RES_SRC_NOTZERO
 
- HIFN_MAC_TRUNC_LENGTH
 
- HIFN_MAX_COMMAND
 
- HIFN_MAX_CRYPT_KEY_LENGTH
 
- HIFN_MAX_DMALEN
 
- HIFN_MAX_IV_LENGTH
 
- HIFN_MAX_RESULT
 
- HIFN_MAX_RESULT_ORDER
 
- HIFN_MAX_SEGLEN
 
- HIFN_MD5_LENGTH
 
- HIFN_NAMESIZE
 
- HIFN_PLL_BP
 
- HIFN_PLL_FCK_MAX
 
- HIFN_PLL_IS_1_8
 
- HIFN_PLL_IS_9_12
 
- HIFN_PLL_ND_MULT_10
 
- HIFN_PLL_ND_MULT_12
 
- HIFN_PLL_ND_MULT_2
 
- HIFN_PLL_ND_MULT_4
 
- HIFN_PLL_ND_MULT_6
 
- HIFN_PLL_ND_MULT_8
 
- HIFN_PLL_ND_SHIFT
 
- HIFN_PLL_PE_CLK_HBI
 
- HIFN_PLL_PE_CLK_PLL
 
- HIFN_PLL_PK_CLK_HBI
 
- HIFN_PLL_PK_CLK_PLL
 
- HIFN_PLL_REF_CLK_HBI
 
- HIFN_PLL_REF_CLK_PLL
 
- HIFN_PLL_RESERVED_1
 
- HIFN_POLL_FREQUENCY
 
- HIFN_POLL_SCALAR
 
- HIFN_PUBBASE_ADDR
 
- HIFN_PUBIEN_DONE
 
- HIFN_PUBOPLEN_EXP_M
 
- HIFN_PUBOPLEN_EXP_S
 
- HIFN_PUBOPLEN_MOD_M
 
- HIFN_PUBOPLEN_MOD_S
 
- HIFN_PUBOPLEN_RED_M
 
- HIFN_PUBOPLEN_RED_S
 
- HIFN_PUBOP_AOFFSET_M
 
- HIFN_PUBOP_AOFFSET_S
 
- HIFN_PUBOP_BOFFSET_M
 
- HIFN_PUBOP_BOFFSET_S
 
- HIFN_PUBOP_MOFFSET_M
 
- HIFN_PUBOP_MOFFSET_S
 
- HIFN_PUBOP_OP_ADD
 
- HIFN_PUBOP_OP_ADDC
 
- HIFN_PUBOP_OP_DECA
 
- HIFN_PUBOP_OP_INCA
 
- HIFN_PUBOP_OP_MASK
 
- HIFN_PUBOP_OP_MODADD
 
- HIFN_PUBOP_OP_MODEXP
 
- HIFN_PUBOP_OP_MODMULT
 
- HIFN_PUBOP_OP_MODRED
 
- HIFN_PUBOP_OP_MODSUB
 
- HIFN_PUBOP_OP_MULT
 
- HIFN_PUBOP_OP_NOP
 
- HIFN_PUBOP_OP_SUB
 
- HIFN_PUBOP_OP_SUBC
 
- HIFN_PUBRST_RESET
 
- HIFN_PUBSTS_CARRY
 
- HIFN_PUBSTS_DONE
 
- HIFN_PUCNFG_BIGENDIAN
 
- HIFN_PUCNFG_BUS16
 
- HIFN_PUCNFG_BUS32
 
- HIFN_PUCNFG_CHIPID
 
- HIFN_PUCNFG_COMPSING
 
- HIFN_PUCNFG_DRAM
 
- HIFN_PUCNFG_DRAMMASK
 
- HIFN_PUCNFG_DRAMREFRESH
 
- HIFN_PUCNFG_DRFR_128
 
- HIFN_PUCNFG_DRFR_256
 
- HIFN_PUCNFG_DRFR_512
 
- HIFN_PUCNFG_DSZ_1M
 
- HIFN_PUCNFG_DSZ_256K
 
- HIFN_PUCNFG_DSZ_2M
 
- HIFN_PUCNFG_DSZ_32M
 
- HIFN_PUCNFG_DSZ_4M
 
- HIFN_PUCNFG_DSZ_512K
 
- HIFN_PUCNFG_DSZ_8M
 
- HIFN_PUCNFG_ENCCNFG
 
- HIFN_PUCNFG_SRAM
 
- HIFN_PUCNFG_TCALLPHASES
 
- HIFN_PUCNFG_TCDRVTOTEM
 
- HIFN_PUCTRL_CLRSRCFIFO
 
- HIFN_PUCTRL_DMAENA
 
- HIFN_PUCTRL_LOCKRAM
 
- HIFN_PUCTRL_RESET
 
- HIFN_PUCTRL_STOP
 
- HIFN_PUIER_CMDINVAL
 
- HIFN_PUIER_DATAERR
 
- HIFN_PUIER_DSTDATA
 
- HIFN_PUIER_DSTFIFO
 
- HIFN_PUIER_DSTOVER
 
- HIFN_PUIER_DSTRESULT
 
- HIFN_PUIER_SRCCMD
 
- HIFN_PUIER_SRCCTX
 
- HIFN_PUIER_SRCDATA
 
- HIFN_PUIER_SRCFIFO
 
- HIFN_PUISR_CMDINVAL
 
- HIFN_PUISR_DATAERR
 
- HIFN_PUISR_DSTDATA
 
- HIFN_PUISR_DSTFIFO
 
- HIFN_PUISR_DSTOVER
 
- HIFN_PUISR_DSTRESULT
 
- HIFN_PUISR_SRCCMD
 
- HIFN_PUISR_SRCCTX
 
- HIFN_PUISR_SRCDATA
 
- HIFN_PUISR_SRCFIFO
 
- HIFN_PUNCFG_DSZ_16M
 
- HIFN_PUSTAT_CHIPENA
 
- HIFN_PUSTAT_CHIPREV
 
- HIFN_PUSTAT_CMDINVAL
 
- HIFN_PUSTAT_DATAERR
 
- HIFN_PUSTAT_DSTDATA
 
- HIFN_PUSTAT_DSTFIFO
 
- HIFN_PUSTAT_DSTOVER
 
- HIFN_PUSTAT_DSTRESULT
 
- HIFN_PUSTAT_ENA_0
 
- HIFN_PUSTAT_ENA_1
 
- HIFN_PUSTAT_ENA_2
 
- HIFN_PUSTAT_REV_2
 
- HIFN_PUSTAT_REV_3
 
- HIFN_PUSTAT_SRCCMD
 
- HIFN_PUSTAT_SRCCTX
 
- HIFN_PUSTAT_SRCDATA
 
- HIFN_PUSTAT_SRCFIFO
 
- HIFN_QUEUE_LENGTH
 
- HIFN_RNGCFG_ENA
 
- HIFN_SHA1_LENGTH
 
- HIFN_USED_RESULT
 
- HIFRDY_MARK
 
- HIFRD_MARK
 
- HIFRS_MARK
 
- HIFWR_MARK
 
- HIF_8601_SILICON
 
- HIF_8601_VERSATILE
 
- HIF_9000_SILICON_VERSATILE
 
- HIF_ADH_SET2_CONF
 
- HIF_ADH_SET2_REQ
 
- HIF_ADH_SET_CONF
 
- HIF_ADH_SET_REQ
 
- HIF_AMODE_MASK
 
- HIF_AP_SET_CONF
 
- HIF_AP_SET_REQ
 
- HIF_ASSOC_INFO_IND
 
- HIF_ASYNCHRONOUS
 
- HIF_BLOCK_BASIS
 
- HIF_BYTE_BASIS
 
- HIF_CONNECT_IND
 
- HIF_DATA_IND
 
- HIF_DATA_REQ
 
- HIF_DIR_MASK
 
- HIF_DMA_BUFFER_SIZE
 
- HIF_DMODE_MASK
 
- HIF_EMODE_MASK
 
- HIF_EVENT_MASK
 
- HIF_FIRST
 
- HIF_FIXED_ADDRESS
 
- HIF_GMBOX_BASE_ADDR
 
- HIF_GMBOX_WIDTH
 
- HIF_H
 
- HIF_HIFBI
 
- HIF_HIFI
 
- HIF_HOLDER
 
- HIF_INCREMENTAL_ADDRESS
 
- HIF_INFRA_SET2_CONF
 
- HIF_INFRA_SET2_REQ
 
- HIF_INFRA_SET_CONF
 
- HIF_INFRA_SET_REQ
 
- HIF_MBOX0_BLOCK_SIZE
 
- HIF_MBOX0_EXT_BASE_ADDR
 
- HIF_MBOX0_EXT_WIDTH
 
- HIF_MBOX_BASE_ADDR
 
- HIF_MBOX_BLOCK_SIZE
 
- HIF_MBOX_END_ADDR
 
- HIF_MBOX_WIDTH
 
- HIF_MIB_GET_CONF
 
- HIF_MIB_GET_REQ
 
- HIF_MIB_SET_CONF
 
- HIF_MIB_SET_REQ
 
- HIF_MIC_FAILURE_CONF
 
- HIF_MIC_FAILURE_REQ
 
- HIF_OPS_H
 
- HIF_PHY_INFO_CONF
 
- HIF_PHY_INFO_IND
 
- HIF_PHY_INFO_REQ
 
- HIF_POWER_MGMT_CONF
 
- HIF_POWER_MGMT_REQ
 
- HIF_PS_ADH_SET_CONF
 
- HIF_PS_ADH_SET_REQ
 
- HIF_RD_ASYNC_BLOCK_FIX
 
- HIF_RD_SYNC_BLOCK_FIX
 
- HIF_RD_SYNC_BYTE_FIX
 
- HIF_RD_SYNC_BYTE_INC
 
- HIF_READ
 
- HIF_REG_CONFIG
 
- HIF_REG_CONFIG_ALLMULTICAST
 
- HIF_REG_CONFIG_CFG
 
- HIF_REG_CONFIG_FULLDUPLEX_ENABLE
 
- HIF_REG_CONFIG_PROMISCUOUS
 
- HIF_REG_CONFIG_RXENABLE
 
- HIF_REG_CONFIG_SLEEPMODE
 
- HIF_REG_CONFIG_SPEED100
 
- HIF_REG_CONFIG_TXENABLE
 
- HIF_REG_ETHERNET_ADDR
 
- HIF_REG_FRAME_DROP_COUNTER
 
- HIF_REG_MULTICAST_HASH
 
- HIF_REG_PACKET_GAP1
 
- HIF_REG_PACKET_GAP2
 
- HIF_REG_PAUSE_THRESHOLD
 
- HIF_REG_PAUSE_THRESHOLD_DEFAULT
 
- HIF_REG_PHY_CMD1
 
- HIF_REG_PHY_CMD1_PHYADDR
 
- HIF_REG_PHY_CMD1_READ
 
- HIF_REG_PHY_CMD1_WRITE
 
- HIF_REG_PHY_CMD2
 
- HIF_REG_PHY_CMD2_PEND_FLAG_BIT
 
- HIF_REG_PHY_CMD2_READY_FLAG_BIT
 
- HIF_REG_PHY_DATA
 
- HIF_REQ_MAX
 
- HIF_SCAN_CONF
 
- HIF_SCAN_IND
 
- HIF_SCAN_REQ
 
- HIF_SLEEP_CONF
 
- HIF_SLEEP_REQ
 
- HIF_START_CONF
 
- HIF_START_REQ
 
- HIF_STOP_CONF
 
- HIF_STOP_REQ
 
- HIF_SYNCHRONOUS
 
- HIF_TASK
 
- HIF_TASK_SLAVE
 
- HIF_TASK_SLAVE2
 
- HIF_TASK_SLAVE3
 
- HIF_USB_MAX_RXPIPES
 
- HIF_USB_MAX_TXPIPES
 
- HIF_USB_READY
 
- HIF_USB_START
 
- HIF_USB_TX_FLUSH
 
- HIF_USB_TX_STOP
 
- HIF_WAIT
 
- HIF_WRITE
 
- HIF_WR_ASYNC_BLOCK_INC
 
- HIF_WR_ASYNC_BYTE_INC
 
- HIF_WR_SYNC_BLOCK_INC
 
- HIF_WR_SYNC_BYTE_FIX
 
- HIF_WR_SYNC_BYTE_INC
 
- HIGH
 
- HIGH8
 
- HIGHBANK_SUSPEND_PARAM
 
- HIGHEST_MCS_SUPPORTED_MCS10
 
- HIGHEST_MCS_SUPPORTED_MCS11
 
- HIGHEST_MCS_SUPPORTED_MCS7
 
- HIGHEST_MCS_SUPPORTED_MCS8
 
- HIGHEST_MCS_SUPPORTED_MCS9
 
- HIGHEST_PERF
 
- HIGHEST_SINGLE_STREAM_MCS
 
- HIGHMEM_DEBUG
 
- HIGHMEM_START
 
- HIGHMEM_ZONE
 
- HIGHORDER
 
- HIGHPOWER_RADIOA_ARRAYLEN
 
- HIGHPRI_NICE_LEVEL
 
- HIGHSPEED_MAX_BITRATE
 
- HIGHWATERMARK
 
- HIGH_ACCURACY_PRESET
 
- HIGH_ADDR
 
- HIGH_ADDR_MARK
 
- HIGH_ADDR_SHIFT
 
- HIGH_BACKBIAS_VALUE
 
- HIGH_BANDWIDTH_OUT_TRANSACTION_PID
 
- HIGH_BITS_MASK
 
- HIGH_BITS_OFFSET
 
- HIGH_BIT_RATE
 
- HIGH_BIT_RATE_PACKET_ALIGN
 
- HIGH_BYTE_TERM
 
- HIGH_COALESCE
 
- HIGH_COMP_102
 
- HIGH_CONTENTION
 
- HIGH_CONTENTION_RECOVERY_DISABLE
 
- HIGH_COUNTER_MSK
 
- HIGH_COUNTER_SHFT
 
- HIGH_FREQUENCY_BAM
 
- HIGH_HYSTERESIS
 
- HIGH_INDEX_BIT
 
- HIGH_INDEX_MASK
 
- HIGH_KERNEL_NR
 
- HIGH_LOW_SWITCH_COUNT_REG
 
- HIGH_MARK
 
- HIGH_MEMORY
 
- HIGH_MOTION
 
- HIGH_OFFSET
 
- HIGH_OVER_AVERAGE
 
- HIGH_OVER_IMMEDIATE
 
- HIGH_PEAK
 
- HIGH_PERF_SQ
 
- HIGH_POWER
 
- HIGH_PRI
 
- HIGH_PRIORITY
 
- HIGH_PRIO_TID
 
- HIGH_PROGRAM_EN
 
- HIGH_QUEUE
 
- HIGH_QUEUE_INX
 
- HIGH_RES_NSEC
 
- HIGH_RXCOL_TICKS
 
- HIGH_RXMAX_FRAMES
 
- HIGH_RX_PENDING
 
- HIGH_SPD_EN_N_SHIFT
 
- HIGH_SPEED
 
- HIGH_SPEED_BUS_SPEED
 
- HIGH_SPEED_MAX_DTR
 
- HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK
 
- HIGH_SYNDROME
 
- HIGH_THRESHOLD
 
- HIGH_TXCOL_TICKS
 
- HIGH_TXMAX_FRAMES
 
- HIGH_UPPER_GPIO_VALUES
 
- HIGH_UPPER_GPIO_VALUES_MASK
 
- HIGH_WATERMARK
 
- HIGH_WATER_MARK
 
- HIGH_WORD
 
- HIGH_Z
 
- HII2S_ADC_PGA_CFG
 
- HII2S_ANTI_FREQ_JITTER_EN
 
- HII2S_APB_AFIFO_CFG_1
 
- HII2S_APB_AFIFO_CFG_2
 
- HII2S_BITS_16
 
- HII2S_BITS_18
 
- HII2S_BITS_20
 
- HII2S_BITS_24
 
- HII2S_CLK_SEL
 
- HII2S_CLK_SEL__EXT_12_288MHZ_SEL
 
- HII2S_CLK_SEL__I2S_BT_FM_SEL
 
- HII2S_CODEC_IRQ
 
- HII2S_CODEC_IRQ_MASK
 
- HII2S_DACL_AGC_CFG_1
 
- HII2S_DACL_AGC_CFG_2
 
- HII2S_DACR_AGC_CFG_1
 
- HII2S_DACR_AGC_CFG_2
 
- HII2S_DIG_FILTER_CLK_EN_CFG
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN
 
- HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN
 
- HII2S_DIG_FILTER_MODULE_CFG
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE
 
- HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK
 
- HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT
 
- HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK
 
- HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT
 
- HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER
 
- HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER
 
- HII2S_DMIC_SIF_CFG
 
- HII2S_FORMAT_I2S
 
- HII2S_FORMAT_LEFT_JUST
 
- HII2S_FORMAT_PCM_STD
 
- HII2S_FORMAT_PCM_USER
 
- HII2S_FORMAT_RIGHT_JUST
 
- HII2S_FS_CFG
 
- HII2S_FS_CFG__FS_ADCLR_MASK
 
- HII2S_FS_CFG__FS_ADCLR_SHIFT
 
- HII2S_FS_CFG__FS_DACLR_MASK
 
- HII2S_FS_CFG__FS_DACLR_SHIFT
 
- HII2S_FS_CFG__FS_S1_MASK
 
- HII2S_FS_CFG__FS_S1_SHIFT
 
- HII2S_FS_CFG__FS_S2_MASK
 
- HII2S_FS_CFG__FS_S2_SHIFT
 
- HII2S_FS_CFG__FS_ST_DL_L_MASK
 
- HII2S_FS_CFG__FS_ST_DL_L_SHIFT
 
- HII2S_FS_CFG__FS_ST_DL_R_MASK
 
- HII2S_FS_CFG__FS_ST_DL_R_SHIFT
 
- HII2S_FS_CFG__FS_VOICE_DLINK_MASK
 
- HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT
 
- HII2S_FS_RATE_16KHZ
 
- HII2S_FS_RATE_192KHZ
 
- HII2S_FS_RATE_32KHZ
 
- HII2S_FS_RATE_48KHZ
 
- HII2S_FS_RATE_8KHZ
 
- HII2S_FS_RATE_96KHZ
 
- HII2S_GAIN_100PC
 
- HII2S_GAIN_25PC
 
- HII2S_GAIN_50PC
 
- HII2S_I2S_CFG
 
- HII2S_I2S_CFG__S1_CHNNL_MODE
 
- HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT
 
- HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK
 
- HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT
 
- HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK
 
- HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT
 
- HII2S_I2S_CFG__S1_FRAME_MODE
 
- HII2S_I2S_CFG__S1_FUNC_MODE_MASK
 
- HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT
 
- HII2S_I2S_CFG__S1_IF_RX_EN
 
- HII2S_I2S_CFG__S1_IF_TX_EN
 
- HII2S_I2S_CFG__S1_LRCK_MODE
 
- HII2S_I2S_CFG__S1_MST_SLV
 
- HII2S_I2S_CFG__S1_RX_CLK_SEL
 
- HII2S_I2S_CFG__S1_TX_CLK_SEL
 
- HII2S_I2S_CFG__S2_CHNNL_MODE
 
- HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT
 
- HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK
 
- HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT
 
- HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK
 
- HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT
 
- HII2S_I2S_CFG__S2_FRAME_MODE
 
- HII2S_I2S_CFG__S2_FUNC_MODE_MASK
 
- HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT
 
- HII2S_I2S_CFG__S2_IF_RX_EN
 
- HII2S_I2S_CFG__S2_IF_TX_EN
 
- HII2S_I2S_CFG__S2_LRCK_MODE
 
- HII2S_I2S_CFG__S2_MST_SLV
 
- HII2S_I2S_CFG__S2_RX_CLK_SEL
 
- HII2S_I2S_CFG__S2_TX_CLK_SEL
 
- HII2S_IF_CLK_EN_CFG
 
- HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN
 
- HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN
 
- HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN
 
- HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN
 
- HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN
 
- HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN
 
- HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN
 
- HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN
 
- HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN
 
- HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN
 
- HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN
 
- HII2S_IF_CLK_EN_CFG__ST_DL_L_EN
 
- HII2S_IF_CLK_EN_CFG__ST_DL_R_EN
 
- HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN
 
- HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN
 
- HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN
 
- HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN
 
- HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN
 
- HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN
 
- HII2S_MEM_CFG
 
- HII2S_MISC_CFG
 
- HII2S_MISC_CFG__S1_DOUT_TEST_SEL
 
- HII2S_MISC_CFG__S2_DOUT_LEFT_SEL
 
- HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL
 
- HII2S_MISC_CFG__S2_DOUT_TEST_SEL
 
- HII2S_MISC_CFG__S3_DIN_TEST_SEL
 
- HII2S_MISC_CFG__S3_DOUT_LEFT_SEL
 
- HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL
 
- HII2S_MISC_CFG__ST_DL_TEST_SEL
 
- HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL
 
- HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL
 
- HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL
 
- HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL
 
- HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL
 
- HII2S_MUX_TOP_MODULE_CFG
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT
 
- HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT
 
- HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY
 
- HII2S_S1_INPUT_PGA_CFG
 
- HII2S_S2_INPUT_PGA_CFG
 
- HII2S_S2_SRC_CFG
 
- HII2S_S2_SRC_MODE_12
 
- HII2S_S2_SRC_MODE_2
 
- HII2S_S2_SRC_MODE_3
 
- HII2S_S2_SRC_MODE_6
 
- HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT
 
- HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT
 
- HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT
 
- HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT
 
- HII2S_STEREO_UPLINK_CHANNEL
 
- HII2S_STEREO_UPLINK_FIFO_TH_CFG
 
- HII2S_ST_DL_CHANNEL
 
- HII2S_ST_DL_FIFO_TH_CFG
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK
 
- HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT
 
- HII2S_ST_DL_PGA_CFG
 
- HII2S_SW_RST_N
 
- HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK
 
- HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT
 
- HII2S_SW_RST_N__ST_DL_WORDLEN_MASK
 
- HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT
 
- HII2S_SW_RST_N__SW_RST_N
 
- HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK
 
- HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT
 
- HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK
 
- HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT
 
- HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK
 
- HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT
 
- HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK
 
- HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT
 
- HII2S_THIRDMD_DLINK_CHANNEL
 
- HII2S_THIRDMD_PCM_PGA_CFG
 
- HII2S_THIRDMD_ULINK_CHANNEL
 
- HII2S_THIRD_MODEM_FIFO_TH
 
- HII2S_VOICE_DLINK_CHANNEL
 
- HII2S_VOICE_DL_SRC_MODE_12
 
- HII2S_VOICE_DL_SRC_MODE_2
 
- HII2S_VOICE_DL_SRC_MODE_3
 
- HII2S_VOICE_DL_SRC_MODE_6
 
- HII2S_VOICE_SIDETONE_DLINK_PGA_CFG
 
- HII2S_VOICE_UPLINK_CHANNEL
 
- HII2S_VOICE_UPLINK_FIFO_TH_CFG
 
- HILBASE
 
- HILINK_ACCESS_SEL_CFG
 
- HILINK_ERR_DFX
 
- HILINK_RESET_TIMOUT
 
- HILO_64
 
- HILO_64_REGPAIR
 
- HILO_DMA
 
- HILO_DMA_REGPAIR
 
- HILO_GEN
 
- HILO_GEN64
 
- HILO_SET
 
- HILO_U64
 
- HILSEN_ACF
 
- HILSEN_ACF2
 
- HILSEN_BREAK
 
- HILSEN_DHR
 
- HILSEN_DHR2
 
- HILSEN_DISC
 
- HILSEN_DISC0
 
- HILSEN_DOWN
 
- HILSEN_DOZE
 
- HILSEN_DSR
 
- HILSEN_END
 
- HILSEN_FOLLOW
 
- HILSEN_HEAL
 
- HILSEN_HEAL0
 
- HILSEN_IFC
 
- HILSEN_IFCACF
 
- HILSEN_LAST
 
- HILSEN_MASK
 
- HILSEN_MATCH
 
- HILSEN_NEXT
 
- HILSEN_OPERATE
 
- HILSEN_PROBE
 
- HILSEN_REPOLL
 
- HILSEN_RESTART
 
- HILSEN_SAME
 
- HILSEN_SCHED
 
- HILSEN_SLEEP
 
- HILSEN_START
 
- HILSEN_UP
 
- HILSE_CTS
 
- HILSE_EXPECT
 
- HILSE_EXPECT_DISC
 
- HILSE_EXPECT_LAST
 
- HILSE_FUNC
 
- HILSE_IN
 
- HILSE_OUT
 
- HILSE_OUT_DISC
 
- HILSE_OUT_LAST
 
- HIL_BUSY
 
- HIL_CLOCK
 
- HIL_CMD
 
- HIL_CMDCT_POL
 
- HIL_CMDCT_RPL
 
- HIL_CMDID_ACF
 
- HIL_CMD_ACF
 
- HIL_CMD_ACK
 
- HIL_CMD_AK1
 
- HIL_CMD_AK2
 
- HIL_CMD_AK3
 
- HIL_CMD_AK4
 
- HIL_CMD_AK5
 
- HIL_CMD_AK6
 
- HIL_CMD_AK7
 
- HIL_CMD_CAE
 
- HIL_CMD_DHR
 
- HIL_CMD_DKA
 
- HIL_CMD_DSR
 
- HIL_CMD_EK1
 
- HIL_CMD_EK2
 
- HIL_CMD_ELB
 
- HIL_CMD_EPT
 
- HIL_CMD_EXD
 
- HIL_CMD_IDD
 
- HIL_CMD_IFC
 
- HIL_CMD_POL
 
- HIL_CMD_PR1
 
- HIL_CMD_PR2
 
- HIL_CMD_PR3
 
- HIL_CMD_PR4
 
- HIL_CMD_PR5
 
- HIL_CMD_PR6
 
- HIL_CMD_PR7
 
- HIL_CMD_PRM
 
- HIL_CMD_PST
 
- HIL_CMD_RIO
 
- HIL_CMD_RNM
 
- HIL_CMD_RPL
 
- HIL_CMD_RRG
 
- HIL_CMD_RSC
 
- HIL_CMD_RST
 
- HIL_CMD_SHR
 
- HIL_CMD_TER
 
- HIL_CMD_WRG
 
- HIL_CNMT
 
- HIL_CTRL_APE
 
- HIL_CTRL_IPF
 
- HIL_CTRL_ONLY
 
- HIL_CTRL_TEST
 
- HIL_DATA
 
- HIL_DATA_RDY
 
- HIL_DO_ALTER_CTRL
 
- HIL_EK1_CLOCK
 
- HIL_EK2_CLOCK
 
- HIL_ERR_FERR
 
- HIL_ERR_FOF
 
- HIL_ERR_INT
 
- HIL_ERR_LERR
 
- HIL_ERR_NMI
 
- HIL_ERR_OB
 
- HIL_ERR_PERR
 
- HIL_EXD_HEADER_LOCALE
 
- HIL_EXD_HEADER_RNM
 
- HIL_EXD_HEADER_RRG
 
- HIL_EXD_HEADER_RST
 
- HIL_EXD_HEADER_WRG
 
- HIL_EXD_HEADER_WRG_TYPE1
 
- HIL_EXD_HEADER_WRG_TYPE2
 
- HIL_EXD_LEN
 
- HIL_EXD_LOCALE
 
- HIL_EXD_NUM_RRG
 
- HIL_EXD_NUM_WWG
 
- HIL_EXD_WRG_TYPE2_LEN
 
- HIL_IDD_AXIS_COUNTS_PER_M
 
- HIL_IDD_AXIS_MAX
 
- HIL_IDD_DID_ABS_RSVD1
 
- HIL_IDD_DID_ABS_RSVD1_MASK
 
- HIL_IDD_DID_ABS_RSVD2
 
- HIL_IDD_DID_ABS_RSVD2_MASK
 
- HIL_IDD_DID_ABS_RSVD3
 
- HIL_IDD_DID_ABS_RSVD3_MASK
 
- HIL_IDD_DID_ABS_TABLET
 
- HIL_IDD_DID_ABS_TABLET_MASK
 
- HIL_IDD_DID_ABS_TSCREEN
 
- HIL_IDD_DID_ABS_TSCREEN_MASK
 
- HIL_IDD_DID_CHAR_BARCODE
 
- HIL_IDD_DID_CHAR_BARCODE_MASK
 
- HIL_IDD_DID_CHAR_RSVD1
 
- HIL_IDD_DID_CHAR_RSVD1_MASK
 
- HIL_IDD_DID_CHAR_RSVD2
 
- HIL_IDD_DID_CHAR_RSVD2_MASK
 
- HIL_IDD_DID_CHAR_RSVD3
 
- HIL_IDD_DID_CHAR_RSVD3_MASK
 
- HIL_IDD_DID_KBLANG_USE_ESD
 
- HIL_IDD_DID_OTHER_BARCODE
 
- HIL_IDD_DID_OTHER_BARCODE_MASK
 
- HIL_IDD_DID_OTHER_RSVD1
 
- HIL_IDD_DID_OTHER_RSVD1_MASK
 
- HIL_IDD_DID_OTHER_RSVD2
 
- HIL_IDD_DID_OTHER_RSVD2_MASK
 
- HIL_IDD_DID_OTHER_RSVD3
 
- HIL_IDD_DID_OTHER_RSVD3_MASK
 
- HIL_IDD_DID_REL_MOUSE
 
- HIL_IDD_DID_REL_MOUSE_MASK
 
- HIL_IDD_DID_REL_QUAD
 
- HIL_IDD_DID_REL_QUAD_MASK
 
- HIL_IDD_DID_REL_RSVD1
 
- HIL_IDD_DID_REL_RSVD1_MASK
 
- HIL_IDD_DID_REL_RSVD2
 
- HIL_IDD_DID_REL_RSVD2_MASK
 
- HIL_IDD_DID_TYPE_ABS
 
- HIL_IDD_DID_TYPE_CHAR
 
- HIL_IDD_DID_TYPE_KB_INTEGRAL
 
- HIL_IDD_DID_TYPE_KB_ITF
 
- HIL_IDD_DID_TYPE_KB_LANG_MASK
 
- HIL_IDD_DID_TYPE_KB_RSVD
 
- HIL_IDD_DID_TYPE_KEYPAD
 
- HIL_IDD_DID_TYPE_MASK
 
- HIL_IDD_DID_TYPE_OTHER
 
- HIL_IDD_DID_TYPE_REL
 
- HIL_IDD_HAS_GEN_PROMPT
 
- HIL_IDD_HAS_GEN_PROXIMITY
 
- HIL_IDD_HEADER_16BIT
 
- HIL_IDD_HEADER_2X_AXIS
 
- HIL_IDD_HEADER_ABS
 
- HIL_IDD_HEADER_AXSET_MASK
 
- HIL_IDD_HEADER_EXD
 
- HIL_IDD_HEADER_IOD
 
- HIL_IDD_HEADER_RSC
 
- HIL_IDD_IOD
 
- HIL_IDD_IOD_NBUTTON_MASK
 
- HIL_IDD_IOD_PROMPT
 
- HIL_IDD_IOD_PROMPT_MASK
 
- HIL_IDD_IOD_PROMPT_SHIFT
 
- HIL_IDD_IOD_PROXIMITY
 
- HIL_IDD_LEN
 
- HIL_IDD_NUM_AXES_PER_SET
 
- HIL_IDD_NUM_AXSETS
 
- HIL_IDD_NUM_BUTTONS
 
- HIL_IDD_NUM_PROMPTS
 
- HIL_INTOFF
 
- HIL_INTON
 
- HIL_IRQ
 
- HIL_KBD_SET1_SHIFT
 
- HIL_KBD_SET1_UPBIT
 
- HIL_KBD_SET2_SHIFT
 
- HIL_KBD_SET2_UPBIT
 
- HIL_KBD_SET3_SHIFT
 
- HIL_KBD_SET3_UPBIT
 
- HIL_KEYCODES_SET1
 
- HIL_KEYCODES_SET1_TBLSIZE
 
- HIL_KEYCODES_SET3
 
- HIL_KEYCODES_SET3_TBLSIZE
 
- HIL_LOCALE_MAP
 
- HIL_LOCALE_MAX
 
- HIL_MLC_DEVMEM
 
- HIL_PACKET_MAX_LENGTH
 
- HIL_PKT_ADDR0
 
- HIL_PKT_ADDR1
 
- HIL_PKT_ADDR2
 
- HIL_PKT_ADDR_MASK
 
- HIL_PKT_ADDR_SHIFT
 
- HIL_PKT_CMD
 
- HIL_PKT_DATA0
 
- HIL_PKT_DATA1
 
- HIL_PKT_DATA2
 
- HIL_PKT_DATA3
 
- HIL_PKT_DATA4
 
- HIL_PKT_DATA5
 
- HIL_PKT_DATA6
 
- HIL_PKT_DATA7
 
- HIL_PKT_DATA_MASK
 
- HIL_PKT_DATA_SHIFT
 
- HIL_POL_AXIS_ALT
 
- HIL_POL_CHARTYPE_ASCII
 
- HIL_POL_CHARTYPE_BINARY
 
- HIL_POL_CHARTYPE_MASK
 
- HIL_POL_CHARTYPE_NONE
 
- HIL_POL_CHARTYPE_RSVD1
 
- HIL_POL_CHARTYPE_RSVD2
 
- HIL_POL_CHARTYPE_SET1
 
- HIL_POL_CHARTYPE_SET2
 
- HIL_POL_CHARTYPE_SET3
 
- HIL_POL_CTS
 
- HIL_POL_NUM_AXES_MASK
 
- HIL_POL_STATUS_PENDING
 
- HIL_READKBDSADR
 
- HIL_SETARD
 
- HIL_SETARR
 
- HIL_SETTONE
 
- HIL_TIMEOUT_DEV
 
- HIL_TIMEOUT_DEVS
 
- HIL_TIMEOUT_DEVS_DATA
 
- HIL_TIMEOUT_NORESP
 
- HIL_TIMEOUT_SELFTEST
 
- HIL_WIRE_ADDR0
 
- HIL_WIRE_ADDR1
 
- HIL_WIRE_ADDR2
 
- HIL_WIRE_COMMAND
 
- HIL_WIRE_DATA0
 
- HIL_WIRE_DATA1
 
- HIL_WIRE_DATA2
 
- HIL_WIRE_DATA3
 
- HIL_WIRE_DATA4
 
- HIL_WIRE_DATA5
 
- HIL_WIRE_DATA6
 
- HIL_WIRE_DATA7
 
- HIL_WIRE_PACKET_LEN
 
- HIL_WIRE_PARITY
 
- HIL_WIRE_START
 
- HIL_WIRE_STOP
 
- HIL_WRITEKBDSADR
 
- HIMR
 
- HIMT_DAT_OFF
 
- HIMT_DSP
 
- HIMT_MIDI_EOS
 
- HIMT_MIDI_IN_UCHAR
 
- HIMT_MIDI_OUT
 
- HIMT_PLAY_DONE
 
- HIMT_RECORD_DONE
 
- HIM_DISABLE
 
- HIM_ENABLE
 
- HINFC504_ADDRH
 
- HINFC504_ADDRL
 
- HINFC504_ADDR_CYCLE_MASK
 
- HINFC504_BUFFER_BASE_ADDRESS_LEN
 
- HINFC504_CHIP_DELAY
 
- HINFC504_CMD
 
- HINFC504_CON
 
- HINFC504_CON_BUS_WIDTH
 
- HINFC504_CON_ECCTYPE_MASK
 
- HINFC504_CON_ECCTYPE_SHIFT
 
- HINFC504_CON_OP_MODE_NORMAL
 
- HINFC504_CON_PAGEISZE_SHIFT
 
- HINFC504_CON_PAGESIZE_MASK
 
- HINFC504_CON_READY_BUSY_SEL
 
- HINFC504_DATA_NUM
 
- HINFC504_DMA_ADDR_DATA
 
- HINFC504_DMA_ADDR_OOB
 
- HINFC504_DMA_CTRL
 
- HINFC504_DMA_CTRL_ADDR_NUM_MASK
 
- HINFC504_DMA_CTRL_ADDR_NUM_SHIFT
 
- HINFC504_DMA_CTRL_BURST16_EN
 
- HINFC504_DMA_CTRL_BURST4_EN
 
- HINFC504_DMA_CTRL_BURST8_EN
 
- HINFC504_DMA_CTRL_CS_MASK
 
- HINFC504_DMA_CTRL_CS_SHIFT
 
- HINFC504_DMA_CTRL_DATA_AREA_EN
 
- HINFC504_DMA_CTRL_DMA_START
 
- HINFC504_DMA_CTRL_OOB_AREA_EN
 
- HINFC504_DMA_CTRL_WE
 
- HINFC504_DMA_LEN
 
- HINFC504_DMA_LEN_OOB_MASK
 
- HINFC504_DMA_LEN_OOB_SHIFT
 
- HINFC504_DMA_PARA
 
- HINFC504_DMA_PARA_DATA_ECC_EN
 
- HINFC504_DMA_PARA_DATA_EDC_EN
 
- HINFC504_DMA_PARA_DATA_RW_EN
 
- HINFC504_DMA_PARA_OOB_ECC_EN
 
- HINFC504_DMA_PARA_OOB_EDC_EN
 
- HINFC504_DMA_PARA_OOB_RW_EN
 
- HINFC504_ECC_16_BIT_SHIFT
 
- HINFC504_ECC_STATUS
 
- HINFC504_INTCLR
 
- HINFC504_INTCLR_CE
 
- HINFC504_INTCLR_DMA
 
- HINFC504_INTCLR_UE
 
- HINFC504_INTEN
 
- HINFC504_INTEN_CE
 
- HINFC504_INTEN_DMA
 
- HINFC504_INTEN_UE
 
- HINFC504_INTS
 
- HINFC504_INTS_CE
 
- HINFC504_INTS_DMA
 
- HINFC504_INTS_UE
 
- HINFC504_LOG_READ_ADDR
 
- HINFC504_LOG_READ_LEN
 
- HINFC504_MAX_CHIP
 
- HINFC504_NANDINFO_LEN
 
- HINFC504_NFC_DMA_TIMEOUT
 
- HINFC504_NFC_PM_TIMEOUT
 
- HINFC504_NFC_TIMEOUT
 
- HINFC504_OP
 
- HINFC504_OP_ADDR_CYCLE_MASK
 
- HINFC504_OP_ADDR_CYCLE_SHIFT
 
- HINFC504_OP_ADDR_EN
 
- HINFC504_OP_CMD1_EN
 
- HINFC504_OP_CMD2_EN
 
- HINFC504_OP_NF_CS_MASK
 
- HINFC504_OP_NF_CS_SHIFT
 
- HINFC504_OP_READ_DATA_EN
 
- HINFC504_OP_WAIT_READY_EN
 
- HINFC504_OP_WRITE_DATA_EN
 
- HINFC504_PWIDTH
 
- HINFC504_READY
 
- HINFC504_REG_BASE_ADDRESS_LEN
 
- HINFC504_RW_LATCH
 
- HINFC504_R_LATCH
 
- HINFC504_STATUS
 
- HINFC504_W_LATCH
 
- HINFC_VERSION
 
- HINIC_AEQ
 
- HINIC_AEQE_DATA_SIZE
 
- HINIC_AEQE_DESC_SIZE
 
- HINIC_AEQE_SIZE
 
- HINIC_AEQ_CONS_IDX_ADDR_BASE
 
- HINIC_AEQ_CTRL_0_ADDR_BASE
 
- HINIC_AEQ_CTRL_0_CLEAR
 
- HINIC_AEQ_CTRL_0_DMA_ATTR_MASK
 
- HINIC_AEQ_CTRL_0_DMA_ATTR_SHIFT
 
- HINIC_AEQ_CTRL_0_INT_IDX_MASK
 
- HINIC_AEQ_CTRL_0_INT_IDX_SHIFT
 
- HINIC_AEQ_CTRL_0_INT_MODE_MASK
 
- HINIC_AEQ_CTRL_0_INT_MODE_SHIFT
 
- HINIC_AEQ_CTRL_0_PCI_INTF_IDX_MASK
 
- HINIC_AEQ_CTRL_0_PCI_INTF_IDX_SHIFT
 
- HINIC_AEQ_CTRL_0_SET
 
- HINIC_AEQ_CTRL_1_ADDR_BASE
 
- HINIC_AEQ_CTRL_1_CLEAR
 
- HINIC_AEQ_CTRL_1_ELEM_SIZE_MASK
 
- HINIC_AEQ_CTRL_1_ELEM_SIZE_SHIFT
 
- HINIC_AEQ_CTRL_1_LEN_MASK
 
- HINIC_AEQ_CTRL_1_LEN_SHIFT
 
- HINIC_AEQ_CTRL_1_PAGE_SIZE_MASK
 
- HINIC_AEQ_CTRL_1_PAGE_SIZE_SHIFT
 
- HINIC_AEQ_CTRL_1_SET
 
- HINIC_AEQ_MTT_OFF_BASE_ADDR
 
- HINIC_AEQ_PROD_IDX_ADDR_BASE
 
- HINIC_API_CMD_CELL_CTRL_DATA_SZ_MASK
 
- HINIC_API_CMD_CELL_CTRL_DATA_SZ_SHIFT
 
- HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_MASK
 
- HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_SHIFT
 
- HINIC_API_CMD_CELL_CTRL_SET
 
- HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_MASK
 
- HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_SHIFT
 
- HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK
 
- HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_CLEAR
 
- HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_SET
 
- HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT
 
- HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK
 
- HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT
 
- HINIC_API_CMD_CHAIN_REQ_CLEAR
 
- HINIC_API_CMD_CHAIN_REQ_GET
 
- HINIC_API_CMD_CHAIN_REQ_RESTART_MASK
 
- HINIC_API_CMD_CHAIN_REQ_RESTART_SHIFT
 
- HINIC_API_CMD_CHAIN_REQ_SET
 
- HINIC_API_CMD_DESC_API_TYPE_MASK
 
- HINIC_API_CMD_DESC_API_TYPE_SHIFT
 
- HINIC_API_CMD_DESC_DEST_MASK
 
- HINIC_API_CMD_DESC_DEST_SHIFT
 
- HINIC_API_CMD_DESC_MGMT_BYPASS_MASK
 
- HINIC_API_CMD_DESC_MGMT_BYPASS_SHIFT
 
- HINIC_API_CMD_DESC_RD_WR_MASK
 
- HINIC_API_CMD_DESC_RD_WR_SHIFT
 
- HINIC_API_CMD_DESC_SET
 
- HINIC_API_CMD_DESC_SIZE_MASK
 
- HINIC_API_CMD_DESC_SIZE_SHIFT
 
- HINIC_API_CMD_DESC_XOR_CHKSUM_MASK
 
- HINIC_API_CMD_DESC_XOR_CHKSUM_SHIFT
 
- HINIC_API_CMD_MAX
 
- HINIC_API_CMD_PI_CLEAR
 
- HINIC_API_CMD_PI_IDX_MASK
 
- HINIC_API_CMD_PI_IDX_SHIFT
 
- HINIC_API_CMD_PI_SET
 
- HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK
 
- HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT
 
- HINIC_API_CMD_STATUS_CONS_IDX_MASK
 
- HINIC_API_CMD_STATUS_CONS_IDX_SHIFT
 
- HINIC_API_CMD_STATUS_GET
 
- HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_MASK
 
- HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT
 
- HINIC_API_CMD_STATUS_HEADER_GET
 
- HINIC_API_CMD_WRITE_TO_MGMT_CPU
 
- HINIC_AUTONEG_ACTIVE
 
- HINIC_AUTONEG_DISABLED
 
- HINIC_AUTONEG_SUPPORTED
 
- HINIC_AUTONEG_UNSUPPORTED
 
- HINIC_CB_ENABLED
 
- HINIC_CB_RUNNING
 
- HINIC_CEQ
 
- HINIC_CEQE_SIZE
 
- HINIC_CEQ_CMDQ
 
- HINIC_CEQ_CONS_IDX_ADDR_BASE
 
- HINIC_CEQ_CTRL_0_ADDR_BASE
 
- HINIC_CEQ_CTRL_0_CLEAR
 
- HINIC_CEQ_CTRL_0_DMA_ATTR_MASK
 
- HINIC_CEQ_CTRL_0_DMA_ATTR_SHIFT
 
- HINIC_CEQ_CTRL_0_INTR_IDX_MASK
 
- HINIC_CEQ_CTRL_0_INTR_IDX_SHIFT
 
- HINIC_CEQ_CTRL_0_INTR_MODE_MASK
 
- HINIC_CEQ_CTRL_0_INTR_MODE_SHIFT
 
- HINIC_CEQ_CTRL_0_KICK_THRESH_MASK
 
- HINIC_CEQ_CTRL_0_KICK_THRESH_SHIFT
 
- HINIC_CEQ_CTRL_0_PCI_INTF_IDX_MASK
 
- HINIC_CEQ_CTRL_0_PCI_INTF_IDX_SHIFT
 
- HINIC_CEQ_CTRL_0_SET
 
- HINIC_CEQ_CTRL_1_ADDR_BASE
 
- HINIC_CEQ_CTRL_1_CLEAR
 
- HINIC_CEQ_CTRL_1_LEN_MASK
 
- HINIC_CEQ_CTRL_1_LEN_SHIFT
 
- HINIC_CEQ_CTRL_1_PAGE_SIZE_MASK
 
- HINIC_CEQ_CTRL_1_PAGE_SIZE_SHIFT
 
- HINIC_CEQ_CTRL_1_SET
 
- HINIC_CEQ_ID_CMDQ
 
- HINIC_CEQ_MTT_OFF_BASE_ADDR
 
- HINIC_CEQ_PROD_IDX_ADDR_BASE
 
- HINIC_CFG_NIC_CAP
 
- HINIC_CMDQ_BUF_HW_RSVD
 
- HINIC_CMDQ_BUF_SIZE
 
- HINIC_CMDQ_CTRL_ACK_TYPE_MASK
 
- HINIC_CMDQ_CTRL_ACK_TYPE_SHIFT
 
- HINIC_CMDQ_CTRL_CMD_MASK
 
- HINIC_CMDQ_CTRL_CMD_SHIFT
 
- HINIC_CMDQ_CTRL_GET
 
- HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK
 
- HINIC_CMDQ_CTRL_HW_BUSY_BIT_SHIFT
 
- HINIC_CMDQ_CTRL_MOD_MASK
 
- HINIC_CMDQ_CTRL_MOD_SHIFT
 
- HINIC_CMDQ_CTRL_PI_MASK
 
- HINIC_CMDQ_CTRL_PI_SHIFT
 
- HINIC_CMDQ_CTRL_SET
 
- HINIC_CMDQ_CTXT_BLOCK_INFO_CLEAR
 
- HINIC_CMDQ_CTXT_BLOCK_INFO_SET
 
- HINIC_CMDQ_CTXT_CEQ_ARM_MASK
 
- HINIC_CMDQ_CTXT_CEQ_ARM_SHIFT
 
- HINIC_CMDQ_CTXT_CEQ_EN_MASK
 
- HINIC_CMDQ_CTXT_CEQ_EN_SHIFT
 
- HINIC_CMDQ_CTXT_CI_MASK
 
- HINIC_CMDQ_CTXT_CI_SHIFT
 
- HINIC_CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK
 
- HINIC_CMDQ_CTXT_CURR_WQE_PAGE_PFN_SHIFT
 
- HINIC_CMDQ_CTXT_EQ_ID_MASK
 
- HINIC_CMDQ_CTXT_EQ_ID_SHIFT
 
- HINIC_CMDQ_CTXT_PAGE_INFO_CLEAR
 
- HINIC_CMDQ_CTXT_PAGE_INFO_SET
 
- HINIC_CMDQ_CTXT_WQ_BLOCK_PFN_MASK
 
- HINIC_CMDQ_CTXT_WQ_BLOCK_PFN_SHIFT
 
- HINIC_CMDQ_CTXT_WRAPPED_MASK
 
- HINIC_CMDQ_CTXT_WRAPPED_SHIFT
 
- HINIC_CMDQ_DB_INFO_CMDQ_TYPE_MASK
 
- HINIC_CMDQ_DB_INFO_CMDQ_TYPE_SHIFT
 
- HINIC_CMDQ_DB_INFO_DB_TYPE_MASK
 
- HINIC_CMDQ_DB_INFO_DB_TYPE_SHIFT
 
- HINIC_CMDQ_DB_INFO_HI_PROD_IDX_MASK
 
- HINIC_CMDQ_DB_INFO_HI_PROD_IDX_SHIFT
 
- HINIC_CMDQ_DB_INFO_PATH_MASK
 
- HINIC_CMDQ_DB_INFO_PATH_SHIFT
 
- HINIC_CMDQ_DB_INFO_SET
 
- HINIC_CMDQ_H
 
- HINIC_CMDQ_MAX_DATA_SIZE
 
- HINIC_CMDQ_SYNC
 
- HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK
 
- HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_MASK
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_REQ_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_MASK
 
- HINIC_CMDQ_WQE_HEADER_COMPLETE_SECT_LEN_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_CTRL_LEN_MASK
 
- HINIC_CMDQ_WQE_HEADER_CTRL_LEN_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK
 
- HINIC_CMDQ_WQE_HEADER_DATA_FMT_SHIFT
 
- HINIC_CMDQ_WQE_HEADER_GET
 
- HINIC_CMDQ_WQE_HEADER_SET
 
- HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_MASK
 
- HINIC_CMDQ_WQE_HEADER_TOGGLED_WRAPPED_SHIFT
 
- HINIC_CMD_ACK_TYPE_CMDQ
 
- HINIC_COMMON_H
 
- HINIC_COMM_CMD_CMDQ_CTXT_GET
 
- HINIC_COMM_CMD_CMDQ_CTXT_SET
 
- HINIC_COMM_CMD_HWCTXT_GET
 
- HINIC_COMM_CMD_HWCTXT_SET
 
- HINIC_COMM_CMD_IO_RES_CLEAR
 
- HINIC_COMM_CMD_IO_STATUS_GET
 
- HINIC_COMM_CMD_MAX
 
- HINIC_COMM_CMD_RES_STATE_SET
 
- HINIC_COMM_CMD_SQ_HI_CI_SET
 
- HINIC_COMPILE_TIME_LEN
 
- HINIC_CSR_AEQ_CONS_IDX_ADDR
 
- HINIC_CSR_AEQ_CTRL_0_ADDR
 
- HINIC_CSR_AEQ_CTRL_1_ADDR
 
- HINIC_CSR_AEQ_HI_PHYS_ADDR_REG
 
- HINIC_CSR_AEQ_LO_PHYS_ADDR_REG
 
- HINIC_CSR_AEQ_MTT_OFF
 
- HINIC_CSR_AEQ_PROD_IDX_ADDR
 
- HINIC_CSR_API_CMD_BASE
 
- HINIC_CSR_API_CMD_CHAIN_CTRL_ADDR
 
- HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR
 
- HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR
 
- HINIC_CSR_API_CMD_CHAIN_NUM_CELLS_ADDR
 
- HINIC_CSR_API_CMD_CHAIN_PI_ADDR
 
- HINIC_CSR_API_CMD_CHAIN_REQ_ADDR
 
- HINIC_CSR_API_CMD_STATUS_ADDR
 
- HINIC_CSR_API_CMD_STATUS_HI_ADDR
 
- HINIC_CSR_API_CMD_STATUS_LO_ADDR
 
- HINIC_CSR_API_CMD_STRIDE
 
- HINIC_CSR_CEQ_CONS_IDX_ADDR
 
- HINIC_CSR_CEQ_CTRL_0_ADDR
 
- HINIC_CSR_CEQ_CTRL_1_ADDR
 
- HINIC_CSR_CEQ_HI_PHYS_ADDR_REG
 
- HINIC_CSR_CEQ_LO_PHYS_ADDR_REG
 
- HINIC_CSR_CEQ_MTT_OFF
 
- HINIC_CSR_CEQ_PROD_IDX_ADDR
 
- HINIC_CSR_DMA_ATTR_ADDR
 
- HINIC_CSR_EQ_PAGE_OFF_STRIDE
 
- HINIC_CSR_FUNC_ATTR0_ADDR
 
- HINIC_CSR_FUNC_ATTR1_ADDR
 
- HINIC_CSR_FUNC_ATTR4_ADDR
 
- HINIC_CSR_FUNC_ATTR5_ADDR
 
- HINIC_CSR_MAX_PORTS
 
- HINIC_CSR_MSIX_CNT_ADDR
 
- HINIC_CSR_MSIX_CNT_BASE
 
- HINIC_CSR_MSIX_CTRL_ADDR
 
- HINIC_CSR_MSIX_CTRL_BASE
 
- HINIC_CSR_MSIX_STRIDE
 
- HINIC_CSR_PPF_ELECTION_ADDR
 
- HINIC_CTRL_PATH
 
- HINIC_DATA_PATH
 
- HINIC_DB_CMDQ_TYPE
 
- HINIC_DB_DISABLE
 
- HINIC_DB_ENABLE
 
- HINIC_DB_MAX_AREAS
 
- HINIC_DB_PAGE_SIZE
 
- HINIC_DB_SIZE
 
- HINIC_DB_SQ_TYPE
 
- HINIC_DEFAULT_AEQ_LEN
 
- HINIC_DEFAULT_CEQ_LEN
 
- HINIC_DEV_H
 
- HINIC_DEV_ID_DUAL_PORT_100GE
 
- HINIC_DEV_ID_DUAL_PORT_100GE_MEZZ
 
- HINIC_DEV_ID_QUAD_PORT_25GE
 
- HINIC_DEV_ID_QUAD_PORT_25GE_MEZZ
 
- HINIC_DMA_ATTR_AT_MASK
 
- HINIC_DMA_ATTR_AT_SHIFT
 
- HINIC_DMA_ATTR_BASE
 
- HINIC_DMA_ATTR_CLEAR
 
- HINIC_DMA_ATTR_NO_SNOOPING_MASK
 
- HINIC_DMA_ATTR_NO_SNOOPING_SHIFT
 
- HINIC_DMA_ATTR_PH_MASK
 
- HINIC_DMA_ATTR_PH_SHIFT
 
- HINIC_DMA_ATTR_SET
 
- HINIC_DMA_ATTR_STRIDE
 
- HINIC_DMA_ATTR_ST_MASK
 
- HINIC_DMA_ATTR_ST_SHIFT
 
- HINIC_DMA_ATTR_TPH_EN_MASK
 
- HINIC_DMA_ATTR_TPH_EN_SHIFT
 
- HINIC_DRV_NAME
 
- HINIC_DUPLEX_FULL
 
- HINIC_DUPLEX_HALF
 
- HINIC_ELECTION_BASE
 
- HINIC_EQE_ENABLED
 
- HINIC_EQE_RUNNING
 
- HINIC_EQS_WQ_NAME
 
- HINIC_EQ_CI_CLEAR
 
- HINIC_EQ_CI_IDX_MASK
 
- HINIC_EQ_CI_IDX_SHIFT
 
- HINIC_EQ_CI_INT_ARMED_MASK
 
- HINIC_EQ_CI_INT_ARMED_SHIFT
 
- HINIC_EQ_CI_SET
 
- HINIC_EQ_CI_WRAPPED_MASK
 
- HINIC_EQ_CI_WRAPPED_SHIFT
 
- HINIC_EQ_CI_XOR_CHKSUM_MASK
 
- HINIC_EQ_CI_XOR_CHKSUM_SHIFT
 
- HINIC_EQ_ELEM_DESC_GET
 
- HINIC_EQ_ELEM_DESC_SET
 
- HINIC_EQ_ELEM_DESC_SIZE_MASK
 
- HINIC_EQ_ELEM_DESC_SIZE_SHIFT
 
- HINIC_EQ_ELEM_DESC_SRC_MASK
 
- HINIC_EQ_ELEM_DESC_SRC_SHIFT
 
- HINIC_EQ_ELEM_DESC_TYPE_MASK
 
- HINIC_EQ_ELEM_DESC_TYPE_SHIFT
 
- HINIC_EQ_ELEM_DESC_WRAPPED_MASK
 
- HINIC_EQ_ELEM_DESC_WRAPPED_SHIFT
 
- HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT
 
- HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT
 
- HINIC_EQ_MSIX_LLI_TIMER_DEFAULT
 
- HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT
 
- HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT
 
- HINIC_EQ_MTT_OFF_STRIDE
 
- HINIC_EQ_OFF_STRIDE
 
- HINIC_EQ_PAGE_SIZE
 
- HINIC_FA0_FUNC_IDX_MASK
 
- HINIC_FA0_FUNC_IDX_SHIFT
 
- HINIC_FA0_FUNC_TYPE_MASK
 
- HINIC_FA0_FUNC_TYPE_SHIFT
 
- HINIC_FA0_GET
 
- HINIC_FA0_PCI_INTF_IDX_MASK
 
- HINIC_FA0_PCI_INTF_IDX_SHIFT
 
- HINIC_FA0_PF_IDX_MASK
 
- HINIC_FA0_PF_IDX_SHIFT
 
- HINIC_FA1_AEQS_PER_FUNC_MASK
 
- HINIC_FA1_AEQS_PER_FUNC_SHIFT
 
- HINIC_FA1_CEQS_PER_FUNC_MASK
 
- HINIC_FA1_CEQS_PER_FUNC_SHIFT
 
- HINIC_FA1_DMA_ATTR_PER_FUNC_MASK
 
- HINIC_FA1_DMA_ATTR_PER_FUNC_SHIFT
 
- HINIC_FA1_GET
 
- HINIC_FA1_INIT_STATUS_MASK
 
- HINIC_FA1_INIT_STATUS_SHIFT
 
- HINIC_FA1_IRQS_PER_FUNC_MASK
 
- HINIC_FA1_IRQS_PER_FUNC_SHIFT
 
- HINIC_FA4_CLEAR
 
- HINIC_FA4_DB_STATE_MASK
 
- HINIC_FA4_DB_STATE_SHIFT
 
- HINIC_FA4_GET
 
- HINIC_FA4_OUTBOUND_STATE_MASK
 
- HINIC_FA4_OUTBOUND_STATE_SHIFT
 
- HINIC_FA4_SET
 
- HINIC_FA5_CLEAR
 
- HINIC_FA5_PF_ACTION_MASK
 
- HINIC_FA5_PF_ACTION_SHIFT
 
- HINIC_FA5_SET
 
- HINIC_FUNC_PORT_DISABLE
 
- HINIC_FUNC_PORT_ENABLE
 
- HINIC_FUNC_STAT
 
- HINIC_FUNC_TYPE
 
- HINIC_FW_VERSION_NAME
 
- HINIC_GET_RX_NUM_LRO
 
- HINIC_GET_RX_PKT_TYPE
 
- HINIC_GET_RX_VLAN_OFFLOAD_EN
 
- HINIC_GET_RX_VLAN_TAG
 
- HINIC_HWIF_FUNC_IDX
 
- HINIC_HWIF_NUM_AEQS
 
- HINIC_HWIF_NUM_CEQS
 
- HINIC_HWIF_NUM_IRQS
 
- HINIC_HWIF_PCI_INTF
 
- HINIC_HWIF_PF_IDX
 
- HINIC_HWIF_PPF_IDX
 
- HINIC_HW_API_CMD_H
 
- HINIC_HW_CSR_H
 
- HINIC_HW_DEV_H
 
- HINIC_HW_EQS_H
 
- HINIC_HW_IF_H
 
- HINIC_HW_IO_H
 
- HINIC_HW_MGMT_H
 
- HINIC_HW_QP_CTXT_H
 
- HINIC_HW_QP_H
 
- HINIC_HW_WQE_H
 
- HINIC_HW_WQ_H
 
- HINIC_INTF_UP
 
- HINIC_IS_PF
 
- HINIC_IS_PPF
 
- HINIC_L2TYPE_ETH
 
- HINIC_L4_OFF_DISABLE
 
- HINIC_LINK_STATE_DOWN
 
- HINIC_LINK_STATE_UP
 
- HINIC_LINK_UP
 
- HINIC_LRO_MAX_WQE_NUM_DEFAULT
 
- HINIC_LRO_RX_TIMER_DEFAULT
 
- HINIC_MAX_AEQS
 
- HINIC_MAX_AEQ_EVENTS
 
- HINIC_MAX_CEQS
 
- HINIC_MAX_CEQ_EVENTS
 
- HINIC_MAX_CMDQ_TYPES
 
- HINIC_MAX_JUMBO_FRAME_SIZE
 
- HINIC_MAX_QPS
 
- HINIC_MAX_SQ_BUFDESCS
 
- HINIC_MEDIA_UNKNOWN
 
- HINIC_MGMT_CB_ENABLED
 
- HINIC_MGMT_CB_RUNNING
 
- HINIC_MGMT_MSG_CMD_BASE
 
- HINIC_MGMT_MSG_CMD_LINK_STATUS
 
- HINIC_MGMT_MSG_CMD_MAX
 
- HINIC_MGMT_MSG_SYNC
 
- HINIC_MGMT_NUM_MSG_CMD
 
- HINIC_MGMT_VERSION_MAX_LEN
 
- HINIC_MIN_MTU_SIZE
 
- HINIC_MIN_TX_NUM_WQEBBS
 
- HINIC_MIN_TX_WQE_SIZE
 
- HINIC_MOD_CFGM
 
- HINIC_MOD_COMM
 
- HINIC_MOD_L2NIC
 
- HINIC_MOD_MAX
 
- HINIC_MSG_FROM_MGMT_CPU
 
- HINIC_MSG_HEADER_ASYNC_MGMT_TO_PF_MASK
 
- HINIC_MSG_HEADER_ASYNC_MGMT_TO_PF_SHIFT
 
- HINIC_MSG_HEADER_CMD_MASK
 
- HINIC_MSG_HEADER_CMD_SHIFT
 
- HINIC_MSG_HEADER_DIRECTION_MASK
 
- HINIC_MSG_HEADER_DIRECTION_SHIFT
 
- HINIC_MSG_HEADER_GET
 
- HINIC_MSG_HEADER_LAST_MASK
 
- HINIC_MSG_HEADER_LAST_SHIFT
 
- HINIC_MSG_HEADER_MODULE_MASK
 
- HINIC_MSG_HEADER_MODULE_SHIFT
 
- HINIC_MSG_HEADER_MSG_ID_MASK
 
- HINIC_MSG_HEADER_MSG_ID_SHIFT
 
- HINIC_MSG_HEADER_MSG_LEN_MASK
 
- HINIC_MSG_HEADER_MSG_LEN_SHIFT
 
- HINIC_MSG_HEADER_NO_ACK_MASK
 
- HINIC_MSG_HEADER_NO_ACK_SHIFT
 
- HINIC_MSG_HEADER_PCI_INTF_MASK
 
- HINIC_MSG_HEADER_PCI_INTF_SHIFT
 
- HINIC_MSG_HEADER_PF_IDX_MASK
 
- HINIC_MSG_HEADER_PF_IDX_SHIFT
 
- HINIC_MSG_HEADER_SEG_LEN_MASK
 
- HINIC_MSG_HEADER_SEG_LEN_SHIFT
 
- HINIC_MSG_HEADER_SEQID_MASK
 
- HINIC_MSG_HEADER_SEQID_SHIFT
 
- HINIC_MSG_HEADER_SET
 
- HINIC_MSG_HEADER_ZEROS_MASK
 
- HINIC_MSG_HEADER_ZEROS_SHIFT
 
- HINIC_MSIX_ATTR_GET
 
- HINIC_MSIX_ATTR_SET
 
- HINIC_MSIX_CNT_RESEND_TIMER_MASK
 
- HINIC_MSIX_CNT_RESEND_TIMER_SHIFT
 
- HINIC_MSIX_CNT_SET
 
- HINIC_MSIX_COALESC_TIMER_MASK
 
- HINIC_MSIX_COALESC_TIMER_SHIFT
 
- HINIC_MSIX_DISABLE
 
- HINIC_MSIX_ENABLE
 
- HINIC_MSIX_LLI_CREDIT_MASK
 
- HINIC_MSIX_LLI_CREDIT_SHIFT
 
- HINIC_MSIX_LLI_TIMER_MASK
 
- HINIC_MSIX_LLI_TIMER_SHIFT
 
- HINIC_MSIX_PENDING_LIMIT_MASK
 
- HINIC_MSIX_PENDING_LIMIT_SHIFT
 
- HINIC_MSIX_RESEND_TIMER_MASK
 
- HINIC_MSIX_RESEND_TIMER_SHIFT
 
- HINIC_MSS_DEFAULT
 
- HINIC_MSS_MIN
 
- HINIC_NODE_ID_MGMT
 
- HINIC_OUTBOUND_DISABLE
 
- HINIC_OUTBOUND_ENABLE
 
- HINIC_OUTER_L3TYPE_IPV4_CHKSUM
 
- HINIC_OUTER_L3TYPE_IPV4_NO_CHKSUM
 
- HINIC_OUTER_L3TYPE_IPV6
 
- HINIC_OUTER_L3TYPE_UNKNOWN
 
- HINIC_PCIE_AT_DISABLE
 
- HINIC_PCIE_NO_SNOOP
 
- HINIC_PCIE_PH_DISABLE
 
- HINIC_PCIE_SNOOP
 
- HINIC_PCIE_ST_DISABLE
 
- HINIC_PCIE_TPH_DISABLE
 
- HINIC_PCIE_TPH_ENABLE
 
- HINIC_PCI_CFG_REGS_BAR
 
- HINIC_PCI_DB_BAR
 
- HINIC_PCI_INTR_REGS_BAR
 
- HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT
 
- HINIC_PCI_MSIX_ENTRY_SIZE
 
- HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL
 
- HINIC_PF
 
- HINIC_PF_MGMT_ACTIVE
 
- HINIC_PF_MGMT_INIT
 
- HINIC_PKT_NOT_PARSED
 
- HINIC_PKT_PARSED
 
- HINIC_PORT_CMD_ADD_VLAN
 
- HINIC_PORT_CMD_CHANGE_MTU
 
- HINIC_PORT_CMD_CLEAN_VPORT_STAT
 
- HINIC_PORT_CMD_CLEAR_PORT_STATISTICS
 
- HINIC_PORT_CMD_DEL_MAC
 
- HINIC_PORT_CMD_DEL_VLAN
 
- HINIC_PORT_CMD_FWCTXT_INIT
 
- HINIC_PORT_CMD_GET_CAP
 
- HINIC_PORT_CMD_GET_GLOBAL_QPN
 
- HINIC_PORT_CMD_GET_LINK_STATE
 
- HINIC_PORT_CMD_GET_MAC
 
- HINIC_PORT_CMD_GET_MGMT_VERSION
 
- HINIC_PORT_CMD_GET_PORT_STATISTICS
 
- HINIC_PORT_CMD_GET_RSS_CTX_TBL
 
- HINIC_PORT_CMD_GET_RSS_HASH_ENGINE
 
- HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL
 
- HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL
 
- HINIC_PORT_CMD_GET_VPORT_STAT
 
- HINIC_PORT_CMD_RSS_CFG
 
- HINIC_PORT_CMD_RSS_TEMP_MGR
 
- HINIC_PORT_CMD_SET_FUNC_STATE
 
- HINIC_PORT_CMD_SET_LRO
 
- HINIC_PORT_CMD_SET_LRO_TIMER
 
- HINIC_PORT_CMD_SET_MAC
 
- HINIC_PORT_CMD_SET_PORT_STATE
 
- HINIC_PORT_CMD_SET_RQ_IQ_MAP
 
- HINIC_PORT_CMD_SET_RSS_CTX_TBL
 
- HINIC_PORT_CMD_SET_RSS_HASH_ENGINE
 
- HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL
 
- HINIC_PORT_CMD_SET_RX_CSUM
 
- HINIC_PORT_CMD_SET_RX_MODE
 
- HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD
 
- HINIC_PORT_CMD_SET_TSO
 
- HINIC_PORT_DISABLE
 
- HINIC_PORT_ENABLE
 
- HINIC_PORT_H
 
- HINIC_PORT_STAT
 
- HINIC_PORT_STATS_VERSION
 
- HINIC_PPF
 
- HINIC_PPF_ELECTION_CLEAR
 
- HINIC_PPF_ELECTION_GET
 
- HINIC_PPF_ELECTION_IDX_MASK
 
- HINIC_PPF_ELECTION_IDX_SHIFT
 
- HINIC_PPF_ELECTION_SET
 
- HINIC_PPF_ELECTION_STRIDE
 
- HINIC_QP_CTXT_TYPE_RQ
 
- HINIC_QP_CTXT_TYPE_SQ
 
- HINIC_Q_CTXT_MAX
 
- HINIC_RES_ACTIVE
 
- HINIC_RES_CLEAN
 
- HINIC_RQ_CQE_SGE_GET
 
- HINIC_RQ_CQE_SGE_LEN_MASK
 
- HINIC_RQ_CQE_SGE_LEN_SHIFT
 
- HINIC_RQ_CQE_STATUS_CLEAR
 
- HINIC_RQ_CQE_STATUS_CSUM_ERR_MASK
 
- HINIC_RQ_CQE_STATUS_CSUM_ERR_SHIFT
 
- HINIC_RQ_CQE_STATUS_GET
 
- HINIC_RQ_CQE_STATUS_RXDONE_MASK
 
- HINIC_RQ_CQE_STATUS_RXDONE_SHIFT
 
- HINIC_RQ_CTRL_BUFDESC_SECT_LEN_MASK
 
- HINIC_RQ_CTRL_BUFDESC_SECT_LEN_SHIFT
 
- HINIC_RQ_CTRL_COMPLETE_FORMAT_MASK
 
- HINIC_RQ_CTRL_COMPLETE_FORMAT_SHIFT
 
- HINIC_RQ_CTRL_COMPLETE_LEN_MASK
 
- HINIC_RQ_CTRL_COMPLETE_LEN_SHIFT
 
- HINIC_RQ_CTRL_LEN_MASK
 
- HINIC_RQ_CTRL_LEN_SHIFT
 
- HINIC_RQ_CTRL_SET
 
- HINIC_RQ_CTXT_CEQ_ATTR_EN_MASK
 
- HINIC_RQ_CTXT_CEQ_ATTR_EN_SHIFT
 
- HINIC_RQ_CTXT_CEQ_ATTR_SET
 
- HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_MASK
 
- HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_SHIFT
 
- HINIC_RQ_CTXT_PI_IDX_MASK
 
- HINIC_RQ_CTXT_PI_IDX_SHIFT
 
- HINIC_RQ_CTXT_PI_INTR_MASK
 
- HINIC_RQ_CTXT_PI_INTR_SHIFT
 
- HINIC_RQ_CTXT_PI_SET
 
- HINIC_RQ_CTXT_PREF_CACHE_MAX_MASK
 
- HINIC_RQ_CTXT_PREF_CACHE_MAX_SHIFT
 
- HINIC_RQ_CTXT_PREF_CACHE_MIN_MASK
 
- HINIC_RQ_CTXT_PREF_CACHE_MIN_SHIFT
 
- HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_MASK
 
- HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT
 
- HINIC_RQ_CTXT_PREF_CI_MASK
 
- HINIC_RQ_CTXT_PREF_CI_SHIFT
 
- HINIC_RQ_CTXT_PREF_SET
 
- HINIC_RQ_CTXT_PREF_WQ_HI_PFN_MASK
 
- HINIC_RQ_CTXT_PREF_WQ_HI_PFN_SHIFT
 
- HINIC_RQ_CTXT_SIZE
 
- HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_MASK
 
- HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT
 
- HINIC_RQ_CTXT_WQ_BLOCK_SET
 
- HINIC_RQ_CTXT_WQ_PAGE_CI_MASK
 
- HINIC_RQ_CTXT_WQ_PAGE_CI_SHIFT
 
- HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_MASK
 
- HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT
 
- HINIC_RQ_CTXT_WQ_PAGE_SET
 
- HINIC_RQ_DEPTH
 
- HINIC_RQ_PAGE_SIZE
 
- HINIC_RQ_WQEBB_SIZE
 
- HINIC_RQ_WQE_SIZE
 
- HINIC_RSS_ENABLE
 
- HINIC_RSS_HASH_ENGINE_TYPE_MAX
 
- HINIC_RSS_HASH_ENGINE_TYPE_TOEP
 
- HINIC_RSS_HASH_ENGINE_TYPE_XOR
 
- HINIC_RSS_INDIR_SIZE
 
- HINIC_RSS_KEY_SIZE
 
- HINIC_RSS_TYPE_GET
 
- HINIC_RSS_TYPE_IPV4_SHIFT
 
- HINIC_RSS_TYPE_IPV6_EXT_SHIFT
 
- HINIC_RSS_TYPE_IPV6_SHIFT
 
- HINIC_RSS_TYPE_SET
 
- HINIC_RSS_TYPE_TCP_IPV4_SHIFT
 
- HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT
 
- HINIC_RSS_TYPE_TCP_IPV6_SHIFT
 
- HINIC_RSS_TYPE_UDP_IPV4_SHIFT
 
- HINIC_RSS_TYPE_UDP_IPV6_SHIFT
 
- HINIC_RSS_TYPE_VALID_SHIFT
 
- HINIC_RXQ_STAT
 
- HINIC_RX_BUFFER_WRITE
 
- HINIC_RX_BUF_SZ
 
- HINIC_RX_BUF_SZ_1024_IDX
 
- HINIC_RX_BUF_SZ_128_IDX
 
- HINIC_RX_BUF_SZ_1536_IDX
 
- HINIC_RX_BUF_SZ_16384_IDX
 
- HINIC_RX_BUF_SZ_192_IDX
 
- HINIC_RX_BUF_SZ_2048_IDX
 
- HINIC_RX_BUF_SZ_256_IDX
 
- HINIC_RX_BUF_SZ_3072_IDX
 
- HINIC_RX_BUF_SZ_32_IDX
 
- HINIC_RX_BUF_SZ_384_IDX
 
- HINIC_RX_BUF_SZ_4096_IDX
 
- HINIC_RX_BUF_SZ_512_IDX
 
- HINIC_RX_BUF_SZ_64_IDX
 
- HINIC_RX_BUF_SZ_768_IDX
 
- HINIC_RX_BUF_SZ_8192_IDX
 
- HINIC_RX_BUF_SZ_96_IDX
 
- HINIC_RX_BUF_SZ_IDX
 
- HINIC_RX_CSUM_HW_CHECK_NONE
 
- HINIC_RX_CSUM_IPSU_OTHER_ERR
 
- HINIC_RX_CSUM_OFFLOAD_EN
 
- HINIC_RX_H
 
- HINIC_RX_IPV6_PKT
 
- HINIC_RX_MODE_BC
 
- HINIC_RX_MODE_MC
 
- HINIC_RX_MODE_MC_ALL
 
- HINIC_RX_MODE_PROMISC
 
- HINIC_RX_MODE_UC
 
- HINIC_SAVED_DATA_ARM_MASK
 
- HINIC_SAVED_DATA_ARM_SHIFT
 
- HINIC_SAVED_DATA_CLEAR
 
- HINIC_SAVED_DATA_GET
 
- HINIC_SAVED_DATA_SET
 
- HINIC_SCMD_DATA_LEN
 
- HINIC_SCTP_OFFLOAD_ENABLE
 
- HINIC_SET_ARM_CMDQ
 
- HINIC_SPEED_1000MB_LINK
 
- HINIC_SPEED_100GB_LINK
 
- HINIC_SPEED_100MB_LINK
 
- HINIC_SPEED_10GB_LINK
 
- HINIC_SPEED_10MB_LINK
 
- HINIC_SPEED_25GB_LINK
 
- HINIC_SPEED_40GB_LINK
 
- HINIC_SPEED_UNKNOWN
 
- HINIC_SQ_CTRL_BUFDESC_SECT_LEN_MASK
 
- HINIC_SQ_CTRL_BUFDESC_SECT_LEN_SHIFT
 
- HINIC_SQ_CTRL_CLEAR
 
- HINIC_SQ_CTRL_DATA_FORMAT_MASK
 
- HINIC_SQ_CTRL_DATA_FORMAT_SHIFT
 
- HINIC_SQ_CTRL_GET
 
- HINIC_SQ_CTRL_LEN_MASK
 
- HINIC_SQ_CTRL_LEN_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_MSS_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_MSS_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_PRI_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_PRI_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_SCTP_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_SCTP_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_TSO_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_TSO_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_UC_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_UC_SHIFT
 
- HINIC_SQ_CTRL_QUEUE_INFO_UFO_MASK
 
- HINIC_SQ_CTRL_QUEUE_INFO_UFO_SHIFT
 
- HINIC_SQ_CTRL_SET
 
- HINIC_SQ_CTRL_TASKSECT_LEN_MASK
 
- HINIC_SQ_CTRL_TASKSECT_LEN_SHIFT
 
- HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK
 
- HINIC_SQ_CTXT_CEQ_ATTR_EN_SHIFT
 
- HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK
 
- HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT
 
- HINIC_SQ_CTXT_CEQ_ATTR_SET
 
- HINIC_SQ_CTXT_CI_IDX_MASK
 
- HINIC_SQ_CTXT_CI_IDX_SHIFT
 
- HINIC_SQ_CTXT_CI_SET
 
- HINIC_SQ_CTXT_CI_WRAPPED_MASK
 
- HINIC_SQ_CTXT_CI_WRAPPED_SHIFT
 
- HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK
 
- HINIC_SQ_CTXT_PREF_CACHE_MAX_SHIFT
 
- HINIC_SQ_CTXT_PREF_CACHE_MIN_MASK
 
- HINIC_SQ_CTXT_PREF_CACHE_MIN_SHIFT
 
- HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK
 
- HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT
 
- HINIC_SQ_CTXT_PREF_CI_MASK
 
- HINIC_SQ_CTXT_PREF_CI_SHIFT
 
- HINIC_SQ_CTXT_PREF_SET
 
- HINIC_SQ_CTXT_PREF_WQ_HI_PFN_MASK
 
- HINIC_SQ_CTXT_PREF_WQ_HI_PFN_SHIFT
 
- HINIC_SQ_CTXT_SIZE
 
- HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_MASK
 
- HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT
 
- HINIC_SQ_CTXT_WQ_BLOCK_SET
 
- HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK
 
- HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT
 
- HINIC_SQ_CTXT_WQ_PAGE_PI_MASK
 
- HINIC_SQ_CTXT_WQ_PAGE_PI_SHIFT
 
- HINIC_SQ_CTXT_WQ_PAGE_SET
 
- HINIC_SQ_DB_INFO_COS_MASK
 
- HINIC_SQ_DB_INFO_COS_SHIFT
 
- HINIC_SQ_DB_INFO_PATH_MASK
 
- HINIC_SQ_DB_INFO_PATH_SHIFT
 
- HINIC_SQ_DB_INFO_PI_HI_MASK
 
- HINIC_SQ_DB_INFO_PI_HI_SHIFT
 
- HINIC_SQ_DB_INFO_QID_MASK
 
- HINIC_SQ_DB_INFO_QID_SHIFT
 
- HINIC_SQ_DB_INFO_SET
 
- HINIC_SQ_DB_INFO_TYPE_MASK
 
- HINIC_SQ_DB_INFO_TYPE_SHIFT
 
- HINIC_SQ_DEPTH
 
- HINIC_SQ_PAGE_SIZE
 
- HINIC_SQ_TASK_INFO0_INNER_L3TYPE_MASK
 
- HINIC_SQ_TASK_INFO0_INNER_L3TYPE_SHIFT
 
- HINIC_SQ_TASK_INFO0_L2HDR_LEN_MASK
 
- HINIC_SQ_TASK_INFO0_L2HDR_LEN_SHIFT
 
- HINIC_SQ_TASK_INFO0_L4_OFFLOAD_MASK
 
- HINIC_SQ_TASK_INFO0_L4_OFFLOAD_SHIFT
 
- HINIC_SQ_TASK_INFO0_PARSE_FLAG_MASK
 
- HINIC_SQ_TASK_INFO0_PARSE_FLAG_SHIFT
 
- HINIC_SQ_TASK_INFO0_SET
 
- HINIC_SQ_TASK_INFO0_TSO_FLAG_MASK
 
- HINIC_SQ_TASK_INFO0_TSO_FLAG_SHIFT
 
- HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_MASK
 
- HINIC_SQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT
 
- HINIC_SQ_TASK_INFO0_VLAN_TAG_MASK
 
- HINIC_SQ_TASK_INFO0_VLAN_TAG_SHIFT
 
- HINIC_SQ_TASK_INFO1_INNER_L3LEN_MASK
 
- HINIC_SQ_TASK_INFO1_INNER_L3LEN_SHIFT
 
- HINIC_SQ_TASK_INFO1_INNER_L4LEN_MASK
 
- HINIC_SQ_TASK_INFO1_INNER_L4LEN_SHIFT
 
- HINIC_SQ_TASK_INFO1_MEDIA_TYPE_MASK
 
- HINIC_SQ_TASK_INFO1_MEDIA_TYPE_SHIFT
 
- HINIC_SQ_TASK_INFO1_SET
 
- HINIC_SQ_TASK_INFO2_OUTER_L3LEN_MASK
 
- HINIC_SQ_TASK_INFO2_OUTER_L3LEN_SHIFT
 
- HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_MASK
 
- HINIC_SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT
 
- HINIC_SQ_TASK_INFO2_SET
 
- HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_MASK
 
- HINIC_SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT
 
- HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK
 
- HINIC_SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT
 
- HINIC_SQ_TASK_INFO4_L2TYPE_MASK
 
- HINIC_SQ_TASK_INFO4_L2TYPE_SHIFT
 
- HINIC_SQ_TASK_INFO4_SET
 
- HINIC_SQ_WQEBB_SIZE
 
- HINIC_SQ_WQE_MAX_SIZE
 
- HINIC_SQ_WQE_SIZE
 
- HINIC_TCP_OFFLOAD_ENABLE
 
- HINIC_TSO_DISABLE
 
- HINIC_TSO_ENABLE
 
- HINIC_TUNNEL_L4TYPE_UNKNOWN
 
- HINIC_TXQ_STAT
 
- HINIC_TX_H
 
- HINIC_UCODE_CMD_ARM_RQ
 
- HINIC_UCODE_CMD_ARM_SQ
 
- HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT
 
- HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE
 
- HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE
 
- HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT
 
- HINIC_UCODE_CMD_SET_IQ_ENABLE
 
- HINIC_UCODE_CMD_SET_RQ_FLUSH
 
- HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE
 
- HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE
 
- HINIC_UDP_OFFLOAD_ENABLE
 
- HINIC_VLAN_OFF_DISABLE
 
- HINIC_VLAN_OFF_ENABLE
 
- HINIC_WQ_BLOCK_PFN
 
- HINIC_WQ_BLOCK_PFN_SHIFT
 
- HINIC_WQ_NAME
 
- HINIC_WQ_PAGE_PFN
 
- HINIC_WQ_PAGE_PFN_SHIFT
 
- HINNERSHARED
 
- HINT_MBX_INT_PENDING
 
- HINT_PREFETCH
 
- HINT_SAFE_DMA
 
- HINT_STOP_MOST
 
- HINT_UDPATE_ENB
 
- HIP01_BOOT_ADDRESS
 
- HIP01_PERI9
 
- HIP04_CLK_168M
 
- HIP04_CLK_50M
 
- HIP04_MAX_CLUSTERS
 
- HIP04_MAX_CPUS_PER_CLUSTER
 
- HIP04_MAX_IRQS
 
- HIP04_MAX_TX_COALESCE_FRAMES
 
- HIP04_MAX_TX_COALESCE_USECS
 
- HIP04_MIN_TX_COALESCE_FRAMES
 
- HIP04_MIN_TX_COALESCE_USECS
 
- HIP04_NONE_CLOCK
 
- HIP04_NR_CLKS
 
- HIP04_OSC50M
 
- HIPIR_NOPEND
 
- HIPOWER
 
- HIPOWERon
 
- HIPOWERop
 
- HIPPI_ALEN
 
- HIPPI_DATA_LEN
 
- HIPPI_EXTENDED_SAP
 
- HIPPI_FRAME_LEN
 
- HIPPI_HLEN
 
- HIPPI_OUI_LEN
 
- HIPPI_UI_CMD
 
- HIPPI_ZLEN
 
- HIQ_CTRL
 
- HIRES_MODE
 
- HIRQ_GLOBAL
 
- HIRQ_PORT0
 
- HIRQ_PORT1
 
- HIRQ_SOFT
 
- HISI_ACC_QM_H
 
- HISI_ACC_SGL_ALIGN_SIZE
 
- HISI_ACC_SGL_H
 
- HISI_ACC_SGL_NR_MAX
 
- HISI_ACC_SGL_SGE_NR_DEF
 
- HISI_ACC_SGL_SGE_NR_MAX
 
- HISI_ACC_SGL_SGE_NR_MIN
 
- HISI_CPU_PART_TSV110
 
- HISI_GET_EVENTID
 
- HISI_MAX_COUNTERS
 
- HISI_MAX_PERIOD
 
- HISI_MAX_SATA_SUPPORT_V2_HW
 
- HISI_PHYES_NUM
 
- HISI_PHYE_LINK_RESET
 
- HISI_PHYE_PHY_UP
 
- HISI_PMU_ATTR
 
- HISI_PMU_EVENT_ATTR
 
- HISI_PMU_FORMAT_ATTR
 
- HISI_QUAD_DOM
 
- HISI_RESET_BIT_MASK
 
- HISI_RESET_OFFSET_MASK
 
- HISI_RESET_OFFSET_SHIFT
 
- HISI_SAS_BIST_CODE_MODE_CJTPAT
 
- HISI_SAS_BIST_CODE_MODE_FIXED_DATA
 
- HISI_SAS_BIST_CODE_MODE_HFTP
 
- HISI_SAS_BIST_CODE_MODE_JTPAT
 
- HISI_SAS_BIST_CODE_MODE_LFTP
 
- HISI_SAS_BIST_CODE_MODE_MFTP
 
- HISI_SAS_BIST_CODE_MODE_PRBS23
 
- HISI_SAS_BIST_CODE_MODE_PRBS31
 
- HISI_SAS_BIST_CODE_MODE_PRBS7
 
- HISI_SAS_BIST_CODE_MODE_SCRAMBED_0
 
- HISI_SAS_BIST_CODE_MODE_TRAIN
 
- HISI_SAS_BIST_CODE_MODE_TRAIN_DONE
 
- HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL
 
- HISI_SAS_BIST_LOOPBACK_MODE_REMOTE
 
- HISI_SAS_BIST_LOOPBACK_MODE_SERDES
 
- HISI_SAS_COMMAND_ENTRIES_V2_HW
 
- HISI_SAS_COMMAND_ENTRIES_V3_HW
 
- HISI_SAS_COMMAND_TABLE_SZ
 
- HISI_SAS_CQ_MAX_INT_NR
 
- HISI_SAS_DEBUGFS_REG
 
- HISI_SAS_DECLARE_RST_WORK_ON_STACK
 
- HISI_SAS_DEV_INIT
 
- HISI_SAS_DEV_NORMAL
 
- HISI_SAS_DEV_TYPE_SATA
 
- HISI_SAS_DEV_TYPE_SSP
 
- HISI_SAS_DEV_TYPE_STP
 
- HISI_SAS_DIF_PROT_MASK
 
- HISI_SAS_DISK_RECOVER_CNT
 
- HISI_SAS_DIX_PROT_MASK
 
- HISI_SAS_ERR_MULTI_BIT_ECC
 
- HISI_SAS_ERR_SINGLE_BIT_ECC
 
- HISI_SAS_FATAL_INT_NR
 
- HISI_SAS_INT_ABT_CMD
 
- HISI_SAS_INT_ABT_DEV
 
- HISI_SAS_IOST_CACHE
 
- HISI_SAS_IOST_ITCT_CACHE_DW_SZ
 
- HISI_SAS_IOST_ITCT_CACHE_NUM
 
- HISI_SAS_ITCT_CACHE
 
- HISI_SAS_MAX_COMMANDS
 
- HISI_SAS_MAX_DEVICES
 
- HISI_SAS_MAX_INT_NR
 
- HISI_SAS_MAX_ITCT_ENTRIES
 
- HISI_SAS_MAX_PHYS
 
- HISI_SAS_MAX_QUEUES
 
- HISI_SAS_MAX_SMP_RESP_SZ
 
- HISI_SAS_MAX_SSP_RESP_SZ
 
- HISI_SAS_MAX_STP_RESP_SZ
 
- HISI_SAS_MSI_COUNT_V3_HW
 
- HISI_SAS_PHY_BCAST_ACK
 
- HISI_SAS_PHY_CHNL_INT
 
- HISI_SAS_PHY_INT_ABNORMAL
 
- HISI_SAS_PHY_INT_NR
 
- HISI_SAS_PHY_MAX_INT_NR
 
- HISI_SAS_PHY_PHY_UPDOWN
 
- HISI_SAS_PHY_SL_PHY_ENABLED
 
- HISI_SAS_PROT_MASK
 
- HISI_SAS_QUEUE_SLOTS
 
- HISI_SAS_REJECT_CMD_BIT
 
- HISI_SAS_RESERVED_IPTT
 
- HISI_SAS_RESET_BIT
 
- HISI_SAS_RST_WORK_INIT
 
- HISI_SAS_SATA_PROTOCOL_ATAPI
 
- HISI_SAS_SATA_PROTOCOL_DMA
 
- HISI_SAS_SATA_PROTOCOL_FPDMA
 
- HISI_SAS_SATA_PROTOCOL_NONDATA
 
- HISI_SAS_SATA_PROTOCOL_PIO
 
- HISI_SAS_SGE_DIF_PAGE_CNT
 
- HISI_SAS_SGE_PAGE_CNT
 
- HISI_SAS_STATUS_BUF_SZ
 
- HISI_SAS_UNRESERVED_IPTT
 
- HISI_SAS_WAIT_PHYUP_TIMEOUT
 
- HISI_ZIP_H
 
- HISPD_MODE
 
- HISR_DMAI
 
- HISR_FROVR
 
- HISR_H0P
 
- HISR_INT0
 
- HISR_INT1
 
- HISR_INTENA
 
- HISR_INT_0_STS
 
- HISR_INT_1_STS
 
- HISR_INT_2_STS
 
- HISR_INT_3_STS
 
- HISR_INT_4_STS
 
- HISR_INT_5_STS
 
- HISR_INT_6_STS
 
- HISR_INT_7_STS
 
- HISR_INT_STS_MSK
 
- HISR_MIDI
 
- HISR_REG
 
- HISR_RESERVED
 
- HISR_SBINT
 
- HISR_VC0
 
- HISR_VC1
 
- HISR_VC10
 
- HISR_VC11
 
- HISR_VC12
 
- HISR_VC13
 
- HISR_VC14
 
- HISR_VC15
 
- HISR_VC2
 
- HISR_VC3
 
- HISR_VC4
 
- HISR_VC5
 
- HISR_VC6
 
- HISR_VC7
 
- HISR_VC8
 
- HISR_VC9
 
- HISR_VC_MASK
 
- HISTB_AHB_CLK
 
- HISTB_APB_CLK
 
- HISTB_COMBPHY0_CLK
 
- HISTB_COMBPHY1_CLK
 
- HISTB_ETH0_MACIF_CLK
 
- HISTB_ETH0_MAC_CLK
 
- HISTB_ETH1_MACIF_CLK
 
- HISTB_ETH1_MAC_CLK
 
- HISTB_FMC_CLK
 
- HISTB_I2C0_CLK
 
- HISTB_I2C1_CLK
 
- HISTB_I2C2_CLK
 
- HISTB_I2C3_CLK
 
- HISTB_I2C4_CLK
 
- HISTB_I2C5_CLK
 
- HISTB_IR_CLK
 
- HISTB_LEDC_CLK
 
- HISTB_LSADC_CLK
 
- HISTB_MCE_CLK
 
- HISTB_MMC_BIU_CLK
 
- HISTB_MMC_CIU_CLK
 
- HISTB_MMC_DRV_CLK
 
- HISTB_MMC_SAMPLE_CLK
 
- HISTB_OSC_CLK
 
- HISTB_PCIE_AUX_CLK
 
- HISTB_PCIE_BUS_CLK
 
- HISTB_PCIE_PIPE_CLK
 
- HISTB_PCIE_SYS_CLK
 
- HISTB_SCI_CLK
 
- HISTB_SDIO0_BIU_CLK
 
- HISTB_SDIO0_CIU_CLK
 
- HISTB_SDIO0_DRV_CLK
 
- HISTB_SDIO0_SAMPLE_CLK
 
- HISTB_SPI0_CLK
 
- HISTB_SPI1_CLK
 
- HISTB_SPI2_CLK
 
- HISTB_TIMER01_CLK
 
- HISTB_UART0_CLK
 
- HISTB_UART1_CLK
 
- HISTB_UART2_CLK
 
- HISTB_UART3_CLK
 
- HISTB_USB2_12M_CLK
 
- HISTB_USB2_48M_CLK
 
- HISTB_USB2_BUS_CLK
 
- HISTB_USB2_OTG_UTMI_CLK
 
- HISTB_USB2_PHY1_REF_CLK
 
- HISTB_USB2_PHY2_REF_CLK
 
- HISTB_USB2_PHY_CLK
 
- HISTB_USB2_UTMI_CLK
 
- HISTB_USB3_BUS_CLK
 
- HISTB_USB3_BUS_CLK1
 
- HISTB_USB3_PIPE_CLK
 
- HISTB_USB3_PIPE_CLK1
 
- HISTB_USB3_SUSPEND_CLK
 
- HISTB_USB3_SUSPEND_CLK1
 
- HISTB_USB3_UTMI_CLK
 
- HISTB_USB3_UTMI_CLK1
 
- HISTC_ABORT
 
- HISTC_CGROUP_ID
 
- HISTC_COMM
 
- HISTC_CPU
 
- HISTC_CYCLES
 
- HISTC_DSO
 
- HISTC_DSO_FROM
 
- HISTC_DSO_SIZE
 
- HISTC_DSO_TO
 
- HISTC_GLOBAL_WEIGHT
 
- HISTC_IN_TX
 
- HISTC_LOCAL_WEIGHT
 
- HISTC_MEM_DADDR_DSO
 
- HISTC_MEM_DADDR_SYMBOL
 
- HISTC_MEM_DCACHELINE
 
- HISTC_MEM_IADDR_SYMBOL
 
- HISTC_MEM_LOCKED
 
- HISTC_MEM_LVL
 
- HISTC_MEM_PHYS_DADDR
 
- HISTC_MEM_SNOOP
 
- HISTC_MEM_TLB
 
- HISTC_MISPREDICT
 
- HISTC_NR_COLS
 
- HISTC_PARENT
 
- HISTC_SOCKET
 
- HISTC_SRCFILE
 
- HISTC_SRCLINE
 
- HISTC_SRCLINE_FROM
 
- HISTC_SRCLINE_TO
 
- HISTC_SYMBOL
 
- HISTC_SYMBOL_FROM
 
- HISTC_SYMBOL_IPC
 
- HISTC_SYMBOL_TO
 
- HISTC_SYM_SIZE
 
- HISTC_THREAD
 
- HISTC_TIME
 
- HISTC_TRACE
 
- HISTC_TRANSACTION
 
- HISTOGRAM_BIN_DATA
 
- HISTOGRAM_INTERRUPT_ENABLE
 
- HISTOGRAM_INT_CONTROL
 
- HISTOGRAM_INT_CTRL_CLEAR
 
- HISTOGRAM_LOGIC_CONTROL
 
- HISTOGRAM_LOGIC_ENABLE
 
- HISTORY_INFO
 
- HISTORY_SIZE
 
- HISTORY_UUIDS
 
- HISTO_HIGH
 
- HISTO_LOW
 
- HISTO_MAX_SIZE
 
- HISTO_MIN_SIZE
 
- HISTO_PAD_SINK
 
- HISTO_PAD_SOURCE
 
- HIST_ACTIONS_MAX
 
- HIST_BAYER
 
- HIST_BROWSER_HELP_COMMON
 
- HIST_CONFIG_DMA
 
- HIST_DISABLED
 
- HIST_ENABLED
 
- HIST_ENTRIES
 
- HIST_FIELDS_MAX
 
- HIST_FIELD_FL_ALIAS
 
- HIST_FIELD_FL_CPU
 
- HIST_FIELD_FL_EXECNAME
 
- HIST_FIELD_FL_EXPR
 
- HIST_FIELD_FL_HEX
 
- HIST_FIELD_FL_HITCOUNT
 
- HIST_FIELD_FL_KEY
 
- HIST_FIELD_FL_LOG2
 
- HIST_FIELD_FL_STACKTRACE
 
- HIST_FIELD_FL_STRING
 
- HIST_FIELD_FL_SYM
 
- HIST_FIELD_FL_SYM_OFFSET
 
- HIST_FIELD_FL_SYSCALL
 
- HIST_FIELD_FL_TIMESTAMP
 
- HIST_FIELD_FL_TIMESTAMP_USECS
 
- HIST_FIELD_FL_VAR
 
- HIST_FIELD_FL_VAR_REF
 
- HIST_FIELD_OPERANDS_MAX
 
- HIST_FILTER__C2C
 
- HIST_FILTER__DSO
 
- HIST_FILTER__GUEST
 
- HIST_FILTER__HOST
 
- HIST_FILTER__PARENT
 
- HIST_FILTER__SOCKET
 
- HIST_FILTER__SYMBOL
 
- HIST_FILTER__THREAD
 
- HIST_INIT
 
- HIST_INTR_CLEAR
 
- HIST_INTR_EN
 
- HIST_INTR_STATUS
 
- HIST_KEY_SIZE_MAX
 
- HIST_MAX_INDEX
 
- HIST_MIN_INDEX
 
- HIST_STACKTRACE_DEPTH
 
- HIST_STACKTRACE_SIZE
 
- HIST_STACKTRACE_SKIP
 
- HIS_REPORT
 
- HIT
 
- HITCOUNT_IDX
 
- HITM_INC
 
- HIT_MASK
 
- HIT_SHIFT
 
- HIT_UK
 
- HIWORD
 
- HIWORD_OPA_MASK
 
- HIWORD_OPCODE_MASK
 
- HIWORD_RESULT_MASK
 
- HIWORD_UPDATE
 
- HIWORD_UPDATE_BIT
 
- HIX5HD2_BOOT_ADDRESS
 
- HIX5HD2_FEPHY_MUX
 
- HIX5HD2_FIXED_100M
 
- HIX5HD2_FIXED_1200M
 
- HIX5HD2_FIXED_125M
 
- HIX5HD2_FIXED_1500M
 
- HIX5HD2_FIXED_150M
 
- HIX5HD2_FIXED_1728M
 
- HIX5HD2_FIXED_187M
 
- HIX5HD2_FIXED_200M
 
- HIX5HD2_FIXED_24M
 
- HIX5HD2_FIXED_250M
 
- HIX5HD2_FIXED_25M
 
- HIX5HD2_FIXED_27M
 
- HIX5HD2_FIXED_288M
 
- HIX5HD2_FIXED_28P8M
 
- HIX5HD2_FIXED_2P02M
 
- HIX5HD2_FIXED_300M
 
- HIX5HD2_FIXED_345P6M
 
- HIX5HD2_FIXED_375M
 
- HIX5HD2_FIXED_400M
 
- HIX5HD2_FIXED_40M
 
- HIX5HD2_FIXED_432M
 
- HIX5HD2_FIXED_48M
 
- HIX5HD2_FIXED_500M
 
- HIX5HD2_FIXED_50M
 
- HIX5HD2_FIXED_54M
 
- HIX5HD2_FIXED_600M
 
- HIX5HD2_FIXED_60M
 
- HIX5HD2_FIXED_750M
 
- HIX5HD2_FIXED_75M
 
- HIX5HD2_FIXED_83M
 
- HIX5HD2_FWD_BUS_CLK
 
- HIX5HD2_FWD_SYS_CLK
 
- HIX5HD2_I2C0_CLK
 
- HIX5HD2_I2C0_RST
 
- HIX5HD2_I2C1_CLK
 
- HIX5HD2_I2C1_RST
 
- HIX5HD2_I2C2_CLK
 
- HIX5HD2_I2C2_RST
 
- HIX5HD2_I2C3_CLK
 
- HIX5HD2_I2C3_RST
 
- HIX5HD2_I2C4_CLK
 
- HIX5HD2_I2C4_RST
 
- HIX5HD2_I2C5_CLK
 
- HIX5HD2_I2C5_RST
 
- HIX5HD2_MAC0_CLK
 
- HIX5HD2_MAC0_PHY_CLK
 
- HIX5HD2_MAC1_CLK
 
- HIX5HD2_MMC_BIU_CLK
 
- HIX5HD2_MMC_CIU_CLK
 
- HIX5HD2_MMC_CIU_RST
 
- HIX5HD2_MMC_MUX
 
- HIX5HD2_NR_CLKS
 
- HIX5HD2_PERI_CRG20
 
- HIX5HD2_PERI_PMC0
 
- HIX5HD2_SATA_CLK
 
- HIX5HD2_SD_BIU_CLK
 
- HIX5HD2_SD_CIU_CLK
 
- HIX5HD2_SD_CIU_RST
 
- HIX5HD2_SD_MUX
 
- HIX5HD2_SFC_CLK
 
- HIX5HD2_SFC_MUX
 
- HIX5HD2_SFC_RST
 
- HIX5HD2_USB_CLK
 
- HIX5HD2_WDG0_CLK
 
- HIX5HD2_WDG0_RST
 
- HIX5I2C_COM
 
- HIX5I2C_CTRL
 
- HIX5I2C_ICR
 
- HIX5I2C_MAX_FREQ
 
- HIX5I2C_RXR
 
- HIX5I2C_SCL_H
 
- HIX5I2C_SCL_L
 
- HIX5I2C_SR
 
- HIX5I2C_STAT_INIT
 
- HIX5I2C_STAT_RW
 
- HIX5I2C_STAT_RW_ERR
 
- HIX5I2C_STAT_RW_SUCCESS
 
- HIX5I2C_STAT_SND_STOP
 
- HIX5I2C_TXR
 
- HIZA10_HIZ
 
- HIZA10_NAF
 
- HIZA14_HIZ
 
- HIZA14_KEYSC
 
- HIZA6_HIZ
 
- HIZA6_LCDC
 
- HIZA7_HIZ
 
- HIZA7_LCDC
 
- HIZA8_HIZ
 
- HIZA8_LCDC
 
- HIZA9_HIZ
 
- HIZA9_VIO
 
- HIZB0_HIZ
 
- HIZB0_VIO
 
- HIZB1_HIZ
 
- HIZB1_VIO
 
- HIZB4_HIZ
 
- HIZB4_SIUA
 
- HIZC10_HIZ
 
- HIZC10_IRQ2
 
- HIZC11_HIZ
 
- HIZC11_IRQ3
 
- HIZC12_HIZ
 
- HIZC12_IRQ4
 
- HIZC13_HIZ
 
- HIZC13_IRQ5
 
- HIZC14_HIZ
 
- HIZC14_IRQ6
 
- HIZC15_HIZ
 
- HIZC15_IRQ7
 
- HIZC8_HIZ
 
- HIZC8_IRQ0
 
- HIZC9_HIZ
 
- HIZC9_IRQ1
 
- HIZCRA
 
- HIZCRC
 
- HIZSET1
 
- HIZSET2
 
- HIZSET3
 
- HIZ_CHICKEN
 
- HIZ_RAW_STALL_OPT_DISABLE
 
- HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE
 
- HI_ACS_FLAGS_ENABLED
 
- HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK
 
- HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET
 
- HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK
 
- HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET
 
- HI_ACS_FLAGS_TEST_VAP
 
- HI_ACS_FLAGS_USE_WWAN
 
- HI_ARG
 
- HI_BYTE
 
- HI_CFG
 
- HI_CFG_CLOCK_REQ_SELECT
 
- HI_CFG_DEF_VAL
 
- HI_CFG_HOST_INT_ACTIVE_LOW
 
- HI_CFG_HOST_INT_ENABLE
 
- HI_CFG_RST232_ENABLE
 
- HI_CFG_UART_ENABLE
 
- HI_CFG_UART_TX_OUT_GPIO_14
 
- HI_CFG_UART_TX_OUT_GPIO_15
 
- HI_CFG_UART_TX_OUT_GPIO_7
 
- HI_CFG_VLYNQ_OUTPUT_ENABLE
 
- HI_COMM_EXEC__A
 
- HI_COMM_MB__A
 
- HI_CONSOLE_FLAGS_BAUD_SELECT
 
- HI_CONSOLE_FLAGS_ENABLE
 
- HI_CONSOLE_FLAGS_UART_MASK
 
- HI_CONSOLE_FLAGS_UART_SHIFT
 
- HI_CT_REG_COMM_STATE__A
 
- HI_CfgCommand
 
- HI_Command
 
- HI_DESC_IN_FW_BIT
 
- HI_DEV_LPL_TYPE_GET
 
- HI_EARLY_ALLOC_GET_IRAM_BANKS
 
- HI_EARLY_ALLOC_IRAM_BANKS_MASK
 
- HI_EARLY_ALLOC_IRAM_BANKS_SHIFT
 
- HI_EARLY_ALLOC_MAGIC
 
- HI_EARLY_ALLOC_MAGIC_MASK
 
- HI_EARLY_ALLOC_MAGIC_SHIFT
 
- HI_EARLY_ALLOC_VALID
 
- HI_FID_TABLE_BOTTOM
 
- HI_I2C_BRIDGE_DELAY
 
- HI_I2C_DELAY
 
- HI_IF_RAM_TRP_BPT0__AX
 
- HI_IF_RAM_USR_BEGIN__A
 
- HI_ITEM
 
- HI_LPL_ENABLED
 
- HI_MAGIC
 
- HI_NO_HISTORY
 
- HI_OBP_ADDRESS
 
- HI_OPTION_ALL_FW_MODE_MASK
 
- HI_OPTION_ALL_FW_SUBMODE_MASK
 
- HI_OPTION_ALL_FW_SUBMODE_SHIFT
 
- HI_OPTION_BMI_CRED_LIMIT
 
- HI_OPTION_DEV_MODE_LSB
 
- HI_OPTION_DEV_MODE_MSB
 
- HI_OPTION_DFS_SUPPORT
 
- HI_OPTION_DISABLE_DBGLOG
 
- HI_OPTION_EARLY_CFG_DONE
 
- HI_OPTION_ENABLE_PROFILE
 
- HI_OPTION_ENABLE_RFKILL
 
- HI_OPTION_FW_BRIDGE
 
- HI_OPTION_FW_BRIDGE_SHIFT
 
- HI_OPTION_FW_MODE_AP
 
- HI_OPTION_FW_MODE_BITS
 
- HI_OPTION_FW_MODE_BSS_STA
 
- HI_OPTION_FW_MODE_BT30AMP
 
- HI_OPTION_FW_MODE_IBSS
 
- HI_OPTION_FW_MODE_MASK
 
- HI_OPTION_FW_MODE_SHIFT
 
- HI_OPTION_FW_SUBMODE_BITS
 
- HI_OPTION_FW_SUBMODE_MASK
 
- HI_OPTION_FW_SUBMODE_NONE
 
- HI_OPTION_FW_SUBMODE_P2PCLIENT
 
- HI_OPTION_FW_SUBMODE_P2PDEV
 
- HI_OPTION_FW_SUBMODE_P2PGO
 
- HI_OPTION_FW_SUBMODE_SHIFT
 
- HI_OPTION_INIT_REG_SCAN
 
- HI_OPTION_MAC_ADDR_METHOD
 
- HI_OPTION_MAC_ADDR_METHOD_SHIFT
 
- HI_OPTION_NO_LFT_STBL
 
- HI_OPTION_NUM_DEV_LSB
 
- HI_OPTION_NUM_DEV_MASK
 
- HI_OPTION_NUM_DEV_MSB
 
- HI_OPTION_NUM_DEV_SHIFT
 
- HI_OPTION_OFFLOAD_AMSDU
 
- HI_OPTION_PAPRD_DISABLE
 
- HI_OPTION_RADIO_RETENTION_DISABLE
 
- HI_OPTION_RELAY_DOT11_HDR
 
- HI_OPTION_RF_KILL_MASK
 
- HI_OPTION_RF_KILL_SHIFT
 
- HI_OPTION_SKIP_ERA_TRACKING
 
- HI_OPTION_SKIP_MEMMAP
 
- HI_OPTION_SKIP_REG_SCAN
 
- HI_OPTION_TIMER_WAR
 
- HI_PERF_GP_ENABLE
 
- HI_POWER_MODE
 
- HI_POWER_STATE
 
- HI_PRIO_TABLE
 
- HI_PWR_SAVE_LPL_DEV0_LSB
 
- HI_PWR_SAVE_LPL_DEV_MASK
 
- HI_PWR_SAVE_LPL_ENABLED
 
- HI_QID
 
- HI_QUEUE_IDX
 
- HI_RA_RAM_SRV_CFG_ACT_BRD_OFF
 
- HI_RA_RAM_SRV_CFG_ACT_BRD_ON
 
- HI_RA_RAM_SRV_CFG_ACT_BRD__M
 
- HI_RA_RAM_SRV_CFG_ACT_PWD_EXE
 
- HI_RA_RAM_SRV_CFG_ACT_SLV0_ON
 
- HI_RA_RAM_SRV_CFG_ACT__A
 
- HI_RA_RAM_SRV_CFG_BDL__A
 
- HI_RA_RAM_SRV_CFG_DIV__A
 
- HI_RA_RAM_SRV_CFG_KEY__A
 
- HI_RA_RAM_SRV_CFG_WUP__A
 
- HI_RA_RAM_SRV_CMD_CONFIG
 
- HI_RA_RAM_SRV_CMD_EXECUTE
 
- HI_RA_RAM_SRV_CMD_RESET
 
- HI_RA_RAM_SRV_CMD__A
 
- HI_RA_RAM_SRV_RES__A
 
- HI_RA_RAM_SRV_RST_KEY_ACT
 
- HI_RA_RAM_SRV_RST_KEY__A
 
- HI_RA_RAM_USR_BEGIN__A
 
- HI_RECORD_HISTORY
 
- HI_RESET_FLAG_IS_VALID
 
- HI_RESET_FLAG_PRESERVE_APP_START
 
- HI_RESET_FLAG_PRESERVE_BOOT_INFO
 
- HI_RESET_FLAG_PRESERVE_HOST_INTEREST
 
- HI_RESET_FLAG_PRESERVE_NVRAM_STATE
 
- HI_RESET_FLAG_PRESERVE_ROMDATA
 
- HI_RESET_FLAG_WARM_RESET
 
- HI_RST_FUNC_ADDR
 
- HI_RST_FUNC_SIZE
 
- HI_ResetCommand
 
- HI_SMPS_ALLOW_MASK
 
- HI_SMPS_DATA_THRESH_MASK
 
- HI_SMPS_DATA_THRESH_SHIFT
 
- HI_SMPS_DISABLE_AUTO_MODE
 
- HI_SMPS_HIPWR_CM_MASK
 
- HI_SMPS_HIPWR_CM_SHIFT
 
- HI_SMPS_LOWPWR_CM_MASK
 
- HI_SMPS_LOWPWR_CM_SHIFT
 
- HI_SMPS_MODE_DYNAMIC
 
- HI_SMPS_MODE_MASK
 
- HI_SMPS_MODE_STATIC
 
- HI_SMPS_RSSI_THRESH_MASK
 
- HI_SMPS_RSSI_THRESH_SHIFT
 
- HI_SOFTIRQ
 
- HI_SPEED_SWITCH
 
- HI_STAT
 
- HI_TR_BROADCAST
 
- HI_TR_FUNC_ADDR
 
- HI_TR_FUNC_SIZE
 
- HI_TR_READ
 
- HI_TR_READ_WRITE
 
- HI_TR_WRITE
 
- HI_VCOFREQ_TABLE_BOTTOM
 
- HI_WOW_EXT_ENABLED_MASK
 
- HI_WOW_EXT_GET_NUM_LISTS
 
- HI_WOW_EXT_GET_NUM_PATTERNS
 
- HI_WOW_EXT_GET_PATTERN_SIZE
 
- HI_WOW_EXT_MAKE_CONFIG
 
- HI_WOW_EXT_NUM_LIST_MASK
 
- HI_WOW_EXT_NUM_LIST_SHIFT
 
- HI_WOW_EXT_NUM_PATTERNS_MASK
 
- HI_WOW_EXT_NUM_PATTERNS_SHIFT
 
- HI_WOW_EXT_PATTERN_SIZE_MASK
 
- HI_WOW_EXT_PATTERN_SIZE_SHIFT
 
- HJELMSLUND_USB485_ISO_PID
 
- HKDF_CONTEXT_KEY_IDENTIFIER
 
- HKDF_CONTEXT_PER_FILE_KEY
 
- HKDF_CONTEXT_PER_MODE_KEY
 
- HKDF_HASHLEN
 
- HKDF_HMAC_ALG
 
- HKEY
 
- HKEY_DATALEN
 
- HKEY_NOTIFY
 
- HK_FLAG_DOMAIN
 
- HK_FLAG_MISC
 
- HK_FLAG_RCU
 
- HK_FLAG_SCHED
 
- HK_FLAG_TICK
 
- HK_FLAG_TIMER
 
- HK_FLAG_WQ
 
- HK_MAXIMUM_MESSAGE_SIZE
 
- HLCGE_PORT_TYPE
 
- HLIEH
 
- HLIEL
 
- HLIPH
 
- HLIPL
 
- HLIST_HEAD
 
- HLIST_HEAD_INIT
 
- HLNotchFilter135NTSC
 
- HLNotchFilter135PAL
 
- HLNotchFilter4xFsc
 
- HLNotchFilterSquare
 
- HLOS1_VOTE_AGGRE0_NOC_GDSC
 
- HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC
 
- HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC
 
- HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC
 
- HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC
 
- HLOS1_VOTE_LPASS_ADSP_GDSC
 
- HLOS1_VOTE_LPASS_CORE_GDSC
 
- HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC
 
- HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC
 
- HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC
 
- HLSQ_BLOCK_ID_SP_FS
 
- HLSQ_BLOCK_ID_SP_VS
 
- HLSQ_BLOCK_ID_TP_MIPMAP
 
- HLSQ_BLOCK_ID_TP_TEX
 
- HLSQ_BUSY_CYCLES
 
- HLSQ_DBG_REGS
 
- HLSQ_DI_TO_FS_START_SP
 
- HLSQ_DI_TO_VS_START_SP
 
- HLSQ_FLUSH
 
- HLSQ_FS_STAGE_START_TO_DONE_SP
 
- HLSQ_PERF_ACTIVE_CYCLES
 
- HLSQ_PERF_DI_TO_FS_START_SP0
 
- HLSQ_PERF_DI_TO_VS_START_SP0
 
- HLSQ_PERF_FS16_THREADS
 
- HLSQ_PERF_FS32_THREADS
 
- HLSQ_PERF_FS8_THREADS
 
- HLSQ_PERF_FS_START_TO_DONE_SP0
 
- HLSQ_PERF_PIXELS
 
- HLSQ_PERF_QUADS
 
- HLSQ_PERF_RBBM_LOAD_CYCLES
 
- HLSQ_PERF_SP_FS_CONSTANT
 
- HLSQ_PERF_SP_FS_DATA_BYTES
 
- HLSQ_PERF_SP_FS_INSTRUCTIONS
 
- HLSQ_PERF_SP_STATE_COPY_CYCLES_FS
 
- HLSQ_PERF_SP_STATE_COPY_CYCLES_VS
 
- HLSQ_PERF_SP_VS_CONSTANT
 
- HLSQ_PERF_SP_VS_DATA_BYTES
 
- HLSQ_PERF_SP_VS_INSTRUCTIONS
 
- HLSQ_PERF_STALL_CYCLES_SP_FS
 
- HLSQ_PERF_STALL_CYCLES_SP_STATE
 
- HLSQ_PERF_STALL_CYCLES_SP_VS
 
- HLSQ_PERF_STALL_CYCLES_UCHE
 
- HLSQ_PERF_TP_STATE
 
- HLSQ_PERF_UCHE_LATENCY_COUNT
 
- HLSQ_PERF_UCHE_LATENCY_CYCLES
 
- HLSQ_PERF_VERTICES
 
- HLSQ_PERF_VS16_THREADS
 
- HLSQ_PERF_VS8_THREADS
 
- HLSQ_PERF_VS_START_TO_DONE_SP0
 
- HLSQ_PIXELS
 
- HLSQ_QUADS
 
- HLSQ_RBBM_LOAD_CYCLES
 
- HLSQ_SP_FS_STAGE_CONSTANT
 
- HLSQ_SP_FS_STAGE_DATA_BYTES
 
- HLSQ_SP_FS_STAGE_INSTRUCTIONS
 
- HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE
 
- HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE
 
- HLSQ_SP_VS_STAGE_CONSTANT
 
- HLSQ_SP_VS_STAGE_DATA_BYTES
 
- HLSQ_SP_VS_STAGE_INSTRUCTIONS
 
- HLSQ_STALL_CYCLES_SP_FS_STAGE
 
- HLSQ_STALL_CYCLES_SP_STATE
 
- HLSQ_STALL_CYCLES_SP_VS_STAGE
 
- HLSQ_STALL_CYCLES_UCHE
 
- HLSQ_STARVE_CYCLES_VFD
 
- HLSQ_TP_STATE
 
- HLSQ_UCHE_LATENCY_COUNT
 
- HLSQ_UCHE_LATENCY_CYCLES
 
- HLSQ_VERTICES
 
- HLSQ_VS_STAGE_START_TO_DONE_SP
 
- HLS_DEFAULT
 
- HLS_DN_DISABLE
 
- HLS_DN_DOWNDEF
 
- HLS_DN_OFFLINE
 
- HLS_DN_POLL
 
- HLS_DOWN
 
- HLS_GOING_OFFLINE
 
- HLS_GOING_UP
 
- HLS_LINK_COOLDOWN
 
- HLS_UP
 
- HLS_UP_ACTIVE
 
- HLS_UP_ARMED
 
- HLS_UP_INIT
 
- HLS_VERIFY_CAP
 
- HLVL_STS
 
- HLWD_NR_IRQS
 
- HL_ARMCP_EEPROM_TIMEOUT_USEC
 
- HL_ARMCP_INFO_TIMEOUT_USEC
 
- HL_BD_SIZE
 
- HL_BOOT_IF_H
 
- HL_CB_OP_CREATE
 
- HL_CB_OP_DESTROY
 
- HL_COMMAND_END
 
- HL_COMMAND_START
 
- HL_CPU_ACCESSIBLE_MEM_SIZE
 
- HL_CQ_ENTRY_SIZE
 
- HL_CQ_LENGTH
 
- HL_CQ_SIZE_IN_BYTES
 
- HL_CS_FLAGS_FORCE_RESTORE
 
- HL_CS_STATUS_SUCCESS
 
- HL_DEBUG_MAX_AUX_VALUES
 
- HL_DEBUG_OP_BMON
 
- HL_DEBUG_OP_ETF
 
- HL_DEBUG_OP_ETR
 
- HL_DEBUG_OP_FUNNEL
 
- HL_DEBUG_OP_SET_MODE
 
- HL_DEBUG_OP_SPMU
 
- HL_DEBUG_OP_STM
 
- HL_DEBUG_OP_TIMESTAMP
 
- HL_DEVICE_HW_STATE_CLEAN
 
- HL_DEVICE_HW_STATE_DIRTY
 
- HL_DEVICE_STATUS_IN_RESET
 
- HL_DEVICE_STATUS_MALFUNCTION
 
- HL_DEVICE_STATUS_OPERATIONAL
 
- HL_DEVICE_TIMEOUT_USEC
 
- HL_DRIVER_AUTHOR
 
- HL_DRIVER_DESC
 
- HL_EQ_ENTRY_SIZE
 
- HL_EQ_LENGTH
 
- HL_EQ_SIZE_IN_BYTES
 
- HL_FPGA_IRQ_BASE
 
- HL_HEARTBEAT_PER_USEC
 
- HL_IDLE_BUSY_TS_ARR_SIZE
 
- HL_INFO_DEVICE_STATUS
 
- HL_INFO_DEVICE_UTILIZATION
 
- HL_INFO_DRAM_USAGE
 
- HL_INFO_HW_EVENTS
 
- HL_INFO_HW_EVENTS_AGGREGATE
 
- HL_INFO_HW_IDLE
 
- HL_INFO_HW_IP_INFO
 
- HL_INFO_VERSION_MAX_LEN
 
- HL_IOCTL_CB
 
- HL_IOCTL_CS
 
- HL_IOCTL_DEBUG
 
- HL_IOCTL_DEF
 
- HL_IOCTL_INFO
 
- HL_IOCTL_MEMORY
 
- HL_IOCTL_WAIT_CS
 
- HL_KERNEL_ASID_ID
 
- HL_MAX_CB_SIZE
 
- HL_MAX_JOBS_PER_CS
 
- HL_MAX_MINORS
 
- HL_MAX_PENDING_CS
 
- HL_MAX_QUEUES
 
- HL_MEM_CONTIGUOUS
 
- HL_MEM_OP_ALLOC
 
- HL_MEM_OP_FREE
 
- HL_MEM_OP_MAP
 
- HL_MEM_OP_UNMAP
 
- HL_MEM_SHARED
 
- HL_MEM_USERPTR
 
- HL_MMAP_CB_MASK
 
- HL_MMU_DEBUG
 
- HL_NAME
 
- HL_NR_IRL
 
- HL_PAGE_SIZE
 
- HL_PCI_ELBI_TIMEOUT_MSEC
 
- HL_PENDING_RESET_PER_SEC
 
- HL_PLDM_PCI_ELBI_TIMEOUT_MSEC
 
- HL_PLDM_PENDING_RESET_PER_SEC
 
- HL_PLL_LOW_JOB_FREQ_USEC
 
- HL_PTE_SIZE
 
- HL_QUEUE_LENGTH
 
- HL_QUEUE_SIZE_IN_BYTES
 
- HL_SIM_MAX_TIMEOUT_US
 
- HL_WAIT_CS_STATUS_ABORTED
 
- HL_WAIT_CS_STATUS_BUSY
 
- HL_WAIT_CS_STATUS_COMPLETED
 
- HL_WAIT_CS_STATUS_INTERRUPTED
 
- HL_WAIT_CS_STATUS_TIMEDOUT
 
- HMAC_CTX
 
- HMAC_IPAD_CONST
 
- HMAC_IPAD_VALUE
 
- HMAC_OPAD_CONST
 
- HMAC_OPAD_VALUE
 
- HMAC_PAD_BLOCKLEN
 
- HMA_DMA_MAPPED_FLAG
 
- HMA_FLAG
 
- HMA_MAX_ADDR_IN_CMD
 
- HMA_MAX_NO_FW_ADDRESS
 
- HMA_MAX_TOTAL_SIZE
 
- HMA_MIN_TOTAL_SIZE
 
- HMA_MUX_F
 
- HMA_MUX_S
 
- HMA_MUX_V
 
- HMA_PAGE_ORDER
 
- HMA_PAGE_SIZE
 
- HMB
 
- HMB_DATA_DEVREADY
 
- HMB_DATA_FC
 
- HMB_DATA_FCDATA_MASK
 
- HMB_DATA_FCDATA_SHIFT
 
- HMB_DATA_FWHALT
 
- HMB_DATA_FWREADY
 
- HMB_DATA_NAKHANDLED
 
- HMB_DATA_VERSION_MASK
 
- HMB_DATA_VERSION_SHIFT
 
- HMC
 
- HMC5843_CHANNEL
 
- HMC5843_CONFIG_REG_A
 
- HMC5843_CONFIG_REG_B
 
- HMC5843_CORE_H
 
- HMC5843_DATA_OUTPUT_LOCK
 
- HMC5843_DATA_OUT_MSB_REGS
 
- HMC5843_DATA_READY
 
- HMC5843_ID
 
- HMC5843_ID_END
 
- HMC5843_ID_REG
 
- HMC5843_MEAS_CONF_MASK
 
- HMC5843_MEAS_CONF_NEGATIVE_BIAS
 
- HMC5843_MEAS_CONF_NORMAL
 
- HMC5843_MEAS_CONF_POSITIVE_BIAS
 
- HMC5843_MODE_CONVERSION_CONTINUOUS
 
- HMC5843_MODE_CONVERSION_SINGLE
 
- HMC5843_MODE_IDLE
 
- HMC5843_MODE_MASK
 
- HMC5843_MODE_REG
 
- HMC5843_MODE_SLEEP
 
- HMC5843_PM_OPS
 
- HMC5843_RANGE_GAIN_DEFAULT
 
- HMC5843_RANGE_GAIN_MASK
 
- HMC5843_RANGE_GAIN_OFFSET
 
- HMC5843_RATE_DEFAULT
 
- HMC5843_RATE_MASK
 
- HMC5843_RATE_OFFSET
 
- HMC5843_STATUS_REG
 
- HMC5883L_ID
 
- HMC5883_ID
 
- HMC5983_CHANNEL
 
- HMC5983_ID
 
- HMCCOLD_RESET
 
- HMCDRV_CACHE_SIZE_DFLT
 
- HMCDRV_CACHE_TIMEOUT
 
- HMCDRV_DEV_BUSY_DELAY
 
- HMCDRV_DEV_BUSY_RETRIES
 
- HMCDRV_DEV_NAME
 
- HMCDRV_FTP_APPEND
 
- HMCDRV_FTP_CANCEL
 
- HMCDRV_FTP_DELETE
 
- HMCDRV_FTP_DIR
 
- HMCDRV_FTP_FIDENT_MAX
 
- HMCDRV_FTP_GET
 
- HMCDRV_FTP_NLIST
 
- HMCDRV_FTP_NOOP
 
- HMCDRV_FTP_PUT
 
- HMC_1510
 
- HMC_1610
 
- HMC_ID_LEN
 
- HMC_OBJS_CREATED
 
- HMC_PADEN
 
- HMC_TLLATTACH
 
- HMC_TLLSPEED
 
- HMD
 
- HMD_FORCE_CHILD
 
- HMD_FORCE_SIBLING
 
- HMD_NORMAL
 
- HMEDEBUG
 
- HMEMTYPE_READ_TRANS_MSK
 
- HMEMTYPE_READ_TRANS_SHFT
 
- HMEM_TYPE_LAST_TRANS_MSK
 
- HMEM_TYPE_LAST_TRANS_SHFT
 
- HMEM_TYPE_START_MID_TRANS_MSK
 
- HMEM_TYPE_START_MID_TRANS_SHFT
 
- HMER_DEBUG_TRIG
 
- HMM_FAULT_ALLOW_RETRY
 
- HMM_FAULT_SNAPSHOT
 
- HMM_PFN_DEVICE_PRIVATE
 
- HMM_PFN_ERROR
 
- HMM_PFN_FLAG_MAX
 
- HMM_PFN_NONE
 
- HMM_PFN_SPECIAL
 
- HMM_PFN_VALID
 
- HMM_PFN_VALUE_MAX
 
- HMM_PFN_WRITE
 
- HMM_RANGE_DEFAULT_TIMEOUT
 
- HMODEADD
 
- HMSS_AHB_CLK_SRC
 
- HMSS_GPLL0_CLK_SRC
 
- HMSS_GPLL4_CLK_SRC
 
- HMSS_RBCPR_CLK_SRC
 
- HMT_EXTRA_HIGH
 
- HMT_HIGH
 
- HMT_LOW
 
- HMT_MEDIUM
 
- HMT_MEDIUM_HIGH
 
- HMT_MEDIUM_LOW
 
- HMT_VERY_LOW
 
- HMT_high
 
- HMT_low
 
- HMT_medium
 
- HMT_medium_high
 
- HMT_medium_low
 
- HMT_very_low
 
- HMU_PARTNER_TYPE
 
- HM_ADD
 
- HM_REMOVE
 
- HM_TIMEOUT
 
- HNAE3_BPE
 
- HNAE3_CLASS_NAME_SIZE
 
- HNAE3_CLIENT_KNIC
 
- HNAE3_CLIENT_NAME_LENGTH
 
- HNAE3_CLIENT_ROCE
 
- HNAE3_CMDQ_ECC_ERROR
 
- HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF
 
- HNAE3_DEV_ID_100G_RDMA_MACSEC
 
- HNAE3_DEV_ID_100G_VF
 
- HNAE3_DEV_ID_25GE
 
- HNAE3_DEV_ID_25GE_RDMA
 
- HNAE3_DEV_ID_25GE_RDMA_MACSEC
 
- HNAE3_DEV_ID_50GE_RDMA
 
- HNAE3_DEV_ID_50GE_RDMA_MACSEC
 
- HNAE3_DEV_ID_GE
 
- HNAE3_DEV_INITED_B
 
- HNAE3_DEV_SUPPORT_DCB_B
 
- HNAE3_DEV_SUPPORT_FD_B
 
- HNAE3_DEV_SUPPORT_GRO_B
 
- HNAE3_DEV_SUPPORT_ROCE_B
 
- HNAE3_DEV_SUPPORT_ROCE_DCB_BITS
 
- HNAE3_DOWN_CLIENT
 
- HNAE3_FEC_AUTO
 
- HNAE3_FEC_BASER
 
- HNAE3_FEC_RS
 
- HNAE3_FEC_USER_DEF
 
- HNAE3_FLR_DONE
 
- HNAE3_FLR_DOWN
 
- HNAE3_FLR_RESET
 
- HNAE3_FUNC_RESET
 
- HNAE3_FW_VERSION_BYTE0_MASK
 
- HNAE3_FW_VERSION_BYTE0_SHIFT
 
- HNAE3_FW_VERSION_BYTE1_MASK
 
- HNAE3_FW_VERSION_BYTE1_SHIFT
 
- HNAE3_FW_VERSION_BYTE2_MASK
 
- HNAE3_FW_VERSION_BYTE2_SHIFT
 
- HNAE3_FW_VERSION_BYTE3_MASK
 
- HNAE3_FW_VERSION_BYTE3_SHIFT
 
- HNAE3_GLOBAL_RESET
 
- HNAE3_IMP_RD_POISON_ERROR
 
- HNAE3_IMP_RESET
 
- HNAE3_INIT_CLIENT
 
- HNAE3_INT_NAME_LEN
 
- HNAE3_IS_TX_RING
 
- HNAE3_ITR_COUNTDOWN_START
 
- HNAE3_KNIC_CLIENT_INITED_B
 
- HNAE3_LOOP_APP
 
- HNAE3_LOOP_NONE
 
- HNAE3_LOOP_PARALLEL_SERDES
 
- HNAE3_LOOP_PHY
 
- HNAE3_LOOP_SERIAL_SERDES
 
- HNAE3_MAX_TC
 
- HNAE3_MAX_USER_PRIO
 
- HNAE3_MEDIA_TYPE_BACKPLANE
 
- HNAE3_MEDIA_TYPE_COPPER
 
- HNAE3_MEDIA_TYPE_FIBER
 
- HNAE3_MEDIA_TYPE_NONE
 
- HNAE3_MEDIA_TYPE_UNKNOWN
 
- HNAE3_MIN_VECTOR_NUM
 
- HNAE3_MODULE_TYPE_AOC
 
- HNAE3_MODULE_TYPE_CR
 
- HNAE3_MODULE_TYPE_FIBRE_LR
 
- HNAE3_MODULE_TYPE_FIBRE_SR
 
- HNAE3_MODULE_TYPE_KR
 
- HNAE3_MODULE_TYPE_TP
 
- HNAE3_MODULE_TYPE_UNKNOWN
 
- HNAE3_MOD_VERSION
 
- HNAE3_MPE
 
- HNAE3_NONE_RESET
 
- HNAE3_OVERFLOW_MPE
 
- HNAE3_OVERFLOW_UPE
 
- HNAE3_PORT_BASE_VLAN_DISABLE
 
- HNAE3_PORT_BASE_VLAN_ENABLE
 
- HNAE3_PORT_BASE_VLAN_MODIFY
 
- HNAE3_PORT_BASE_VLAN_NOCHANGE
 
- HNAE3_PPU_POISON_ERROR
 
- HNAE3_RESTORE_CLIENT
 
- HNAE3_RING_GL_IDX_M
 
- HNAE3_RING_GL_IDX_S
 
- HNAE3_RING_GL_RX
 
- HNAE3_RING_GL_TX
 
- HNAE3_RING_TYPE_B
 
- HNAE3_RING_TYPE_RX
 
- HNAE3_RING_TYPE_TX
 
- HNAE3_ROCE_CLIENT_INITED_B
 
- HNAE3_SUPPORT_APP_LOOPBACK
 
- HNAE3_SUPPORT_PHY_LOOPBACK
 
- HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK
 
- HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK
 
- HNAE3_SUPPORT_VF
 
- HNAE3_UNIC_CLIENT_INITED_B
 
- HNAE3_UNINIT_CLIENT
 
- HNAE3_UNKNOWN_RESET
 
- HNAE3_UPE
 
- HNAE3_UP_CLIENT
 
- HNAE3_USER_MPE
 
- HNAE3_USER_UPE
 
- HNAE3_VF_FULL_RESET
 
- HNAE3_VF_FUNC_RESET
 
- HNAE3_VF_PF_FUNC_RESET
 
- HNAE3_VF_RESET
 
- HNAE3_VLAN_FLTR
 
- HNAE_AE_REGISTER
 
- HNAE_BULK_LATENCY_COAL_PARAM
 
- HNAE_COPYRIGHT
 
- HNAE_DEFAULT_DEVICE_DESCR
 
- HNAE_DRIVER_NAME
 
- HNAE_DRIVER_STRING
 
- HNAE_DRIVER_VERSION
 
- HNAE_LED_ACTIVE
 
- HNAE_LED_INACTIVE
 
- HNAE_LED_OFF
 
- HNAE_LED_ON
 
- HNAE_LOWEST_LATENCY_COAL_PARAM
 
- HNAE_LOW_LATENCY_COAL_PARAM
 
- HNAE_MEDIA_TYPE_BACKPLANE
 
- HNAE_MEDIA_TYPE_COPPER
 
- HNAE_MEDIA_TYPE_FIBER
 
- HNAE_MEDIA_TYPE_UNKNOWN
 
- HNAE_PORT_DEBUG
 
- HNAE_PORT_SERVICE
 
- HNBU_CHIPID
 
- HNDSPK2ACLNK
 
- HNS3_BD_SIZE_1024_TYPE
 
- HNS3_BD_SIZE_2048_TYPE
 
- HNS3_BD_SIZE_4096_TYPE
 
- HNS3_BD_SIZE_512_TYPE
 
- HNS3_BUFFER_SIZE_2048
 
- HNS3_DBG_BUF_LEN
 
- HNS3_DBG_READ_LEN
 
- HNS3_DBG_WRITE_LEN
 
- HNS3_FLOW_HIGH
 
- HNS3_FLOW_LOW
 
- HNS3_FLOW_MID
 
- HNS3_FLOW_ULTRA
 
- HNS3_INNER_VLAN_TAG
 
- HNS3_INT_GL_18K
 
- HNS3_INT_GL_20K
 
- HNS3_INT_GL_50K
 
- HNS3_INT_GL_8K
 
- HNS3_INT_GL_MAX
 
- HNS3_INT_RL_ENABLE_MASK
 
- HNS3_INT_RL_MAX
 
- HNS3_L2_TYPE_BROADCAST
 
- HNS3_L2_TYPE_INVALID
 
- HNS3_L2_TYPE_MULTICAST
 
- HNS3_L2_TYPE_UNICAST
 
- HNS3_L3T_IPV4
 
- HNS3_L3T_IPV6
 
- HNS3_L3T_NONE
 
- HNS3_L3T_RESERVED
 
- HNS3_L3_TYPE_ARP
 
- HNS3_L3_TYPE_BPDU
 
- HNS3_L3_TYPE_CNM
 
- HNS3_L3_TYPE_IPV4
 
- HNS3_L3_TYPE_IPV4_OPT
 
- HNS3_L3_TYPE_IPV6
 
- HNS3_L3_TYPE_IPV6_EXT
 
- HNS3_L3_TYPE_LLDP
 
- HNS3_L3_TYPE_MAC_PAUSE
 
- HNS3_L3_TYPE_PARSE_FAIL
 
- HNS3_L3_TYPE_PFC_PAUSE
 
- HNS3_L3_TYPE_RARP
 
- HNS3_L4T_SCTP
 
- HNS3_L4T_TCP
 
- HNS3_L4T_UDP
 
- HNS3_L4T_UNKNOWN
 
- HNS3_L4_TYPE_GRE
 
- HNS3_L4_TYPE_ICMP
 
- HNS3_L4_TYPE_IGMP
 
- HNS3_L4_TYPE_PARSE_FAIL
 
- HNS3_L4_TYPE_SCTP
 
- HNS3_L4_TYPE_TCP
 
- HNS3_L4_TYPE_UDP
 
- HNS3_MAC_MAX_FRAME
 
- HNS3_MAC_VLAN_CFG_FLAG_BIT
 
- HNS3_MAX_BD_NUM_NORMAL
 
- HNS3_MAX_BD_NUM_TSO
 
- HNS3_MAX_BD_PER_PKT
 
- HNS3_MAX_BD_SIZE
 
- HNS3_MAX_MTU
 
- HNS3_MIN_TX_LEN
 
- HNS3_MOD_VERSION
 
- HNS3_NEED_ADD_FRAG
 
- HNS3_NIC_LB_DST_MAC_ADDR
 
- HNS3_NIC_LB_SETUP_USEC
 
- HNS3_NIC_LB_TEST_NO_MEM_ERR
 
- HNS3_NIC_LB_TEST_PACKET_SIZE
 
- HNS3_NIC_LB_TEST_PKT_NUM
 
- HNS3_NIC_LB_TEST_RING_ID
 
- HNS3_NIC_LB_TEST_RX_CNT_ERR
 
- HNS3_NIC_LB_TEST_TX_CNT_ERR
 
- HNS3_NIC_STATE2_RESET_REQUESTED
 
- HNS3_NIC_STATE_DISABLED
 
- HNS3_NIC_STATE_DOWN
 
- HNS3_NIC_STATE_INITED
 
- HNS3_NIC_STATE_MAX
 
- HNS3_NIC_STATE_REMOVING
 
- HNS3_NIC_STATE_RESETTING
 
- HNS3_NIC_STATE_SERVICE_INITED
 
- HNS3_NIC_STATE_SERVICE_SCHED
 
- HNS3_NIC_STATE_TESTING
 
- HNS3_OL3T_IPV4_CSUM
 
- HNS3_OL3T_IPV4_NO_CSUM
 
- HNS3_OL3T_IPV6
 
- HNS3_OL3T_NONE
 
- HNS3_OL3_TYPE_IPV4
 
- HNS3_OL3_TYPE_IPV4_OPT
 
- HNS3_OL3_TYPE_IPV6
 
- HNS3_OL3_TYPE_IPV6_EXT
 
- HNS3_OL3_TYPE_PARSE_FAIL
 
- HNS3_OL4_TYPE_MAC_IN_UDP
 
- HNS3_OL4_TYPE_NO_TUN
 
- HNS3_OL4_TYPE_NVGRE
 
- HNS3_OL4_TYPE_UNKNOWN
 
- HNS3_OUTER_VLAN_TAG
 
- HNS3_RING_ASID_REG
 
- HNS3_RING_BD_MULTIPLE
 
- HNS3_RING_CFG_VF_NUM_REG
 
- HNS3_RING_COULD_BE_RST
 
- HNS3_RING_EN_B
 
- HNS3_RING_EN_REG
 
- HNS3_RING_INTMSK_RXWL_REG
 
- HNS3_RING_INTMSK_RX_OVERTIME_REG
 
- HNS3_RING_INTMSK_TXWL_REG
 
- HNS3_RING_INTMSK_TX_OVERTIME_REG
 
- HNS3_RING_INTSTS_RX_OVERTIME_REG
 
- HNS3_RING_INTSTS_RX_RING_REG
 
- HNS3_RING_INTSTS_TX_OVERTIME_REG
 
- HNS3_RING_INTSTS_TX_RING_REG
 
- HNS3_RING_MAX_PENDING
 
- HNS3_RING_MB_CTRL_REG
 
- HNS3_RING_MB_DATA_BASE_REG
 
- HNS3_RING_MIN_PENDING
 
- HNS3_RING_NAME_LEN
 
- HNS3_RING_PREFETCH_EN_REG
 
- HNS3_RING_RX_RING_BASEADDR_H_REG
 
- HNS3_RING_RX_RING_BASEADDR_L_REG
 
- HNS3_RING_RX_RING_BD_LEN_REG
 
- HNS3_RING_RX_RING_BD_NUM_REG
 
- HNS3_RING_RX_RING_FBDNUM_REG
 
- HNS3_RING_RX_RING_HEAD_REG
 
- HNS3_RING_RX_RING_PKTNUM_RECORD_REG
 
- HNS3_RING_RX_RING_TAIL_REG
 
- HNS3_RING_T0_BE_RST
 
- HNS3_RING_TX_RING_BASEADDR_H_REG
 
- HNS3_RING_TX_RING_BASEADDR_L_REG
 
- HNS3_RING_TX_RING_BD_ERR_REG
 
- HNS3_RING_TX_RING_BD_NUM_REG
 
- HNS3_RING_TX_RING_EBDNUM_REG
 
- HNS3_RING_TX_RING_EBD_OFFSET_REG
 
- HNS3_RING_TX_RING_FBDNUM_REG
 
- HNS3_RING_TX_RING_HEAD_REG
 
- HNS3_RING_TX_RING_OFFSET_REG
 
- HNS3_RING_TX_RING_PKTNUM_RECORD_REG
 
- HNS3_RING_TX_RING_TAIL_REG
 
- HNS3_RING_TX_RING_TC_REG
 
- HNS3_RING_WRR_WEIGHT_REG
 
- HNS3_RXD_BDTYPE_M
 
- HNS3_RXD_BDTYPE_S
 
- HNS3_RXD_CRCP_B
 
- HNS3_RXD_DMAC_M
 
- HNS3_RXD_DMAC_S
 
- HNS3_RXD_DOI_B
 
- HNS3_RXD_EXTEND_B
 
- HNS3_RXD_FBHI_M
 
- HNS3_RXD_FBHI_S
 
- HNS3_RXD_FBLI_M
 
- HNS3_RXD_FBLI_S
 
- HNS3_RXD_FE_B
 
- HNS3_RXD_FRAG_B
 
- HNS3_RXD_GRO_COUNT_M
 
- HNS3_RXD_GRO_COUNT_S
 
- HNS3_RXD_GRO_ECN_B
 
- HNS3_RXD_GRO_FIXID_B
 
- HNS3_RXD_GRO_SIZE_M
 
- HNS3_RXD_GRO_SIZE_S
 
- HNS3_RXD_HOI_B
 
- HNS3_RXD_L2E_B
 
- HNS3_RXD_L3E_B
 
- HNS3_RXD_L3ID_M
 
- HNS3_RXD_L3ID_S
 
- HNS3_RXD_L3L4P_B
 
- HNS3_RXD_L4E_B
 
- HNS3_RXD_L4ID_M
 
- HNS3_RXD_L4ID_S
 
- HNS3_RXD_LKBK_B
 
- HNS3_RXD_LUM_B
 
- HNS3_RXD_ODMAC_M
 
- HNS3_RXD_ODMAC_S
 
- HNS3_RXD_OL3E_B
 
- HNS3_RXD_OL3ID_M
 
- HNS3_RXD_OL3ID_S
 
- HNS3_RXD_OL4E_B
 
- HNS3_RXD_OL4ID_M
 
- HNS3_RXD_OL4ID_S
 
- HNS3_RXD_OVLAN_M
 
- HNS3_RXD_OVLAN_S
 
- HNS3_RXD_STRP_TAGP_M
 
- HNS3_RXD_STRP_TAGP_S
 
- HNS3_RXD_TRUNCAT_B
 
- HNS3_RXD_TSIND_M
 
- HNS3_RXD_TSIND_S
 
- HNS3_RXD_UDP0_B
 
- HNS3_RXD_VLAN_M
 
- HNS3_RXD_VLAN_S
 
- HNS3_RXD_VLD_B
 
- HNS3_RXQ_STATS_COUNT
 
- HNS3_RX_FLAG_L3ID_IPV4
 
- HNS3_RX_FLAG_L3ID_IPV6
 
- HNS3_RX_FLAG_L4ID_TCP
 
- HNS3_RX_FLAG_L4ID_UDP
 
- HNS3_RX_FLAG_VLAN_PRESENT
 
- HNS3_RX_HEAD_SIZE
 
- HNS3_RX_LOW_BYTE_RATE
 
- HNS3_RX_MID_BYTE_RATE
 
- HNS3_RX_RING_INT_STS_REG
 
- HNS3_RX_ULTRA_PACKET_RATE
 
- HNS3_SELF_TEST_TYPE_NUM
 
- HNS3_STRP_BOTH
 
- HNS3_STRP_INNER_VLAN
 
- HNS3_STRP_OUTER_VLAN
 
- HNS3_TQP_STAT
 
- HNS3_TQP_STATS_COUNT
 
- HNS3_TUN_MAC_IN_UDP
 
- HNS3_TUN_NONE
 
- HNS3_TUN_NVGRE
 
- HNS3_TUN_OTHER
 
- HNS3_TXD_BDTYPE_M
 
- HNS3_TXD_BDTYPE_S
 
- HNS3_TXD_DECTTL_M
 
- HNS3_TXD_DECTTL_S
 
- HNS3_TXD_EXTEND_B
 
- HNS3_TXD_FE_B
 
- HNS3_TXD_L2LEN_M
 
- HNS3_TXD_L2LEN_S
 
- HNS3_TXD_L3CS_B
 
- HNS3_TXD_L3LEN_M
 
- HNS3_TXD_L3LEN_S
 
- HNS3_TXD_L3T_M
 
- HNS3_TXD_L3T_S
 
- HNS3_TXD_L4CS_B
 
- HNS3_TXD_L4LEN_M
 
- HNS3_TXD_L4LEN_S
 
- HNS3_TXD_L4T_M
 
- HNS3_TXD_L4T_S
 
- HNS3_TXD_MACSEC_B
 
- HNS3_TXD_MSS_M
 
- HNS3_TXD_MSS_S
 
- HNS3_TXD_OL3T_M
 
- HNS3_TXD_OL3T_S
 
- HNS3_TXD_OVLAN_B
 
- HNS3_TXD_RA_B
 
- HNS3_TXD_RI_B
 
- HNS3_TXD_SC_M
 
- HNS3_TXD_SC_S
 
- HNS3_TXD_TSO_B
 
- HNS3_TXD_TSYN_B
 
- HNS3_TXD_TUNTYPE_M
 
- HNS3_TXD_TUNTYPE_S
 
- HNS3_TXD_VLAN_B
 
- HNS3_TXD_VLD_B
 
- HNS3_TXQ_STATS_COUNT
 
- HNS3_TX_LAST_SIZE_M
 
- HNS3_TX_REG_OFFSET
 
- HNS3_TX_RING_INT_STS_REG
 
- HNS3_TX_TIMEOUT
 
- HNS3_UDP_TNL_GENEVE
 
- HNS3_UDP_TNL_MAX
 
- HNS3_UDP_TNL_VXLAN
 
- HNS3_VECTOR_GL0_OFFSET
 
- HNS3_VECTOR_GL1_OFFSET
 
- HNS3_VECTOR_GL2_OFFSET
 
- HNS3_VECTOR_INITED
 
- HNS3_VECTOR_NOT_INITED
 
- HNS3_VECTOR_PF_MAX_NUM
 
- HNS3_VECTOR_RL_EN_B
 
- HNS3_VECTOR_RL_OFFSET
 
- HNS3_VECTOR_RX_IRQ
 
- HNS3_VECTOR_TX_IRQ
 
- HNSV2_SERVICE_RING_IRQ_IDX
 
- HNSV2_TXD_BUFNUM_M
 
- HNSV2_TXD_BUFNUM_S
 
- HNSV2_TXD_FE_B
 
- HNSV2_TXD_IPV6_B
 
- HNSV2_TXD_L3CS_B
 
- HNSV2_TXD_L4CS_B
 
- HNSV2_TXD_PORTID_M
 
- HNSV2_TXD_PORTID_S
 
- HNSV2_TXD_RI_B
 
- HNSV2_TXD_SCTP_B
 
- HNSV2_TXD_SNAP_B
 
- HNSV2_TXD_TSE_B
 
- HNSV2_TXD_VLAN_EN_B
 
- HNSV2_TXD_VLD_B
 
- HNS_ABI_USER_H
 
- HNS_BD_SIZE_1024_TYPE
 
- HNS_BD_SIZE_2048_TYPE
 
- HNS_BD_SIZE_4096_TYPE
 
- HNS_BD_SIZE_512_TYPE
 
- HNS_BUFFER_SIZE_2048
 
- HNS_CHIP_VERSION
 
- HNS_COAL_BDNUM
 
- HNS_DEBUG_OFFSET
 
- HNS_DEBUG_RING_IRQ_IDX
 
- HNS_DSAF_CHN_RESET_FUNC
 
- HNS_DSAF_DEBUG_NW_REG_OFFSET
 
- HNS_DSAF_I4TC_CFG
 
- HNS_DSAF_I8TC_CFG
 
- HNS_DSAF_IS_DEBUG
 
- HNS_DSAF_MAX_DESC_CNT
 
- HNS_DSAF_MIN_DESC_CNT
 
- HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000
 
- HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500
 
- HNS_DSAF_PFC_UNIT_CNT_FOR_XGE
 
- HNS_DSAF_RESET_FUNC
 
- HNS_DSAF_SBM_NUM
 
- HNS_DUMP_REG_NUM
 
- HNS_GE_RESET_FUNC
 
- HNS_ICL_SWITCH_CMD_ROCEE_SEL
 
- HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT
 
- HNS_LB_TX_RING
 
- HNS_LED_FC_REG
 
- HNS_LED_FORCE_OFF
 
- HNS_LED_FORCE_ON
 
- HNS_LED_PC_REG
 
- HNS_LOWEST_LATENCY_RATE
 
- HNS_LOW_LATENCY_RATE
 
- HNS_MAC_HILINK3V2_REG
 
- HNS_MAC_HILINK3_REG
 
- HNS_MAC_HILINK4V2_REG
 
- HNS_MAC_HILINK4_REG
 
- HNS_MAC_LANE0_CTLEDFE_REG
 
- HNS_MAC_LANE0_STATE_REG
 
- HNS_MAC_LANE1_CTLEDFE_REG
 
- HNS_MAC_LANE1_STATE_REG
 
- HNS_MAC_LANE2_CTLEDFE_REG
 
- HNS_MAC_LANE2_STATE_REG
 
- HNS_MAC_LANE3_CTLEDFE_REG
 
- HNS_MAC_LANE3_STATE_REG
 
- HNS_MAX_WAIT_CNT
 
- HNS_NET_STATS_CNT
 
- HNS_NIC_TX_TIMEOUT
 
- HNS_OP_GET_PORT_TYPE_FUNC
 
- HNS_OP_GET_SFP_STAT_FUNC
 
- HNS_OP_LED_SET_FUNC
 
- HNS_OP_LOCATE_LED_SET_FUNC
 
- HNS_OP_RESET_FUNC
 
- HNS_OP_SERDES_LP_FUNC
 
- HNS_PHY_CSC_REG
 
- HNS_PHY_CSS_REG
 
- HNS_PHY_PAGE_COPPER
 
- HNS_PHY_PAGE_LED
 
- HNS_PHY_PAGE_MDIX
 
- HNS_PHY_PAGE_REG
 
- HNS_PPEV2_MAX_FRAME_LEN
 
- HNS_PPEV2_RSS_IND_TBL_SIZE
 
- HNS_PPEV2_RSS_KEY_NUM
 
- HNS_PPEV2_RSS_KEY_SIZE
 
- HNS_PPE_COM_NUM
 
- HNS_PPE_DEBUG_NW_ENGINE_NUM
 
- HNS_PPE_RESET_FUNC
 
- HNS_PPE_SERVICE_NW_ENGINE_NUM
 
- HNS_QUERY_FW_VER
 
- HNS_RCBV2_RING_MAX_TXBD_PER_PKT
 
- HNS_RCB_CLK_FREQ_MHZ
 
- HNS_RCB_COMMON_DUMP_REG_NUM
 
- HNS_RCB_COMMON_ENDIAN
 
- HNS_RCB_DEBUG_NW_ENGINE_NUM
 
- HNS_RCB_DEF_COALESCED_USECS
 
- HNS_RCB_DEF_GAP_TIME_USECS
 
- HNS_RCB_DEF_RX_COALESCED_FRAMES
 
- HNS_RCB_DEF_TX_COALESCED_FRAMES
 
- HNS_RCB_IRQ_IDX_RX
 
- HNS_RCB_IRQ_IDX_TX
 
- HNS_RCB_IRQ_NUM_PER_QUEUE
 
- HNS_RCB_MAX_COALESCED_FRAMES
 
- HNS_RCB_MAX_COALESCED_USECS
 
- HNS_RCB_MAX_PKT_SIZE
 
- HNS_RCB_MIN_COALESCED_FRAMES
 
- HNS_RCB_REG_OFFSET
 
- HNS_RCB_RING_DUMP_REG_NUM
 
- HNS_RCB_RING_MAX_BD_PER_PKT
 
- HNS_RCB_RING_MAX_PENDING_BD
 
- HNS_RCB_RING_MAX_TXBD_PER_PKT
 
- HNS_RCB_RING_MIN_PENDING_BD
 
- HNS_RCB_RX_FRAMES_HIGH
 
- HNS_RCB_RX_FRAMES_LOW
 
- HNS_RCB_RX_USECS_HIGH
 
- HNS_RCB_RX_USECS_LOW
 
- HNS_RCB_SERVICE_NW_ENGINE_NUM
 
- HNS_RCB_TX_FRAMES_HIGH
 
- HNS_RCB_TX_FRAMES_LOW
 
- HNS_RCB_TX_PKTLINE_OFFSET
 
- HNS_RCB_TX_REG_OFFSET
 
- HNS_RCB_TX_USECS_HIGH
 
- HNS_RCB_TX_USECS_LOW
 
- HNS_RING_STATIC_REG_NUM
 
- HNS_ROCE_AEQ
 
- HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M
 
- HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S
 
- HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M
 
- HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S
 
- HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M
 
- HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S
 
- HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M
 
- HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S
 
- HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M
 
- HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S
 
- HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M
 
- HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S
 
- HNS_ROCE_AEQE_U32_4_OWNER_S
 
- HNS_ROCE_AEQ_DEFAULT_BURST_NUM
 
- HNS_ROCE_AEQ_DEFAULT_INTERVAL
 
- HNS_ROCE_AEQ_ENTRY_SIZE
 
- HNS_ROCE_ALOGN_UP
 
- HNS_ROCE_BA_SIZE
 
- HNS_ROCE_BT_RSV_BUF_SIZE
 
- HNS_ROCE_CAP_FLAG_ATOMIC
 
- HNS_ROCE_CAP_FLAG_FRMR
 
- HNS_ROCE_CAP_FLAG_MW
 
- HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL
 
- HNS_ROCE_CAP_FLAG_RECORD_DB
 
- HNS_ROCE_CAP_FLAG_REREG_MR
 
- HNS_ROCE_CAP_FLAG_ROCE_V1_V2
 
- HNS_ROCE_CAP_FLAG_RQ_INLINE
 
- HNS_ROCE_CAP_FLAG_SQ_RECORD_DB
 
- HNS_ROCE_CAP_FLAG_SRQ
 
- HNS_ROCE_CEQ
 
- HNS_ROCE_CEQE_CEQE_COMP_CQN_M
 
- HNS_ROCE_CEQE_CEQE_COMP_CQN_S
 
- HNS_ROCE_CEQE_CEQE_COMP_OWNER_S
 
- HNS_ROCE_CEQ_DEFAULT_BURST_NUM
 
- HNS_ROCE_CEQ_DEFAULT_INTERVAL
 
- HNS_ROCE_CEQ_ENTRY_SIZE
 
- HNS_ROCE_CMD_2ERR_QP
 
- HNS_ROCE_CMD_2RST_QP
 
- HNS_ROCE_CMD_CREATE_AEQC
 
- HNS_ROCE_CMD_CREATE_CEQC
 
- HNS_ROCE_CMD_DESTROY_AEQC
 
- HNS_ROCE_CMD_DESTROY_CEQC
 
- HNS_ROCE_CMD_DESTROY_CQC_BT0
 
- HNS_ROCE_CMD_DESTROY_CQC_BT1
 
- HNS_ROCE_CMD_DESTROY_CQC_BT2
 
- HNS_ROCE_CMD_DESTROY_MPT_BT0
 
- HNS_ROCE_CMD_DESTROY_MPT_BT1
 
- HNS_ROCE_CMD_DESTROY_MPT_BT2
 
- HNS_ROCE_CMD_DESTROY_QPC_BT0
 
- HNS_ROCE_CMD_DESTROY_QPC_BT1
 
- HNS_ROCE_CMD_DESTROY_QPC_BT2
 
- HNS_ROCE_CMD_DESTROY_SRQC_BT0
 
- HNS_ROCE_CMD_DESTROY_SRQC_BT1
 
- HNS_ROCE_CMD_DESTROY_SRQC_BT2
 
- HNS_ROCE_CMD_FLAG_ERR_INTR
 
- HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT
 
- HNS_ROCE_CMD_FLAG_IN
 
- HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT
 
- HNS_ROCE_CMD_FLAG_NEXT
 
- HNS_ROCE_CMD_FLAG_NEXT_SHIFT
 
- HNS_ROCE_CMD_FLAG_NO_INTR
 
- HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT
 
- HNS_ROCE_CMD_FLAG_OUT
 
- HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT
 
- HNS_ROCE_CMD_FLAG_WR
 
- HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT
 
- HNS_ROCE_CMD_HW2SW_CQ
 
- HNS_ROCE_CMD_HW2SW_MPT
 
- HNS_ROCE_CMD_HW2SW_SRQ
 
- HNS_ROCE_CMD_INIT2RTR_QP
 
- HNS_ROCE_CMD_MODIFY_AEQC
 
- HNS_ROCE_CMD_MODIFY_CEQC
 
- HNS_ROCE_CMD_MODIFY_CQC
 
- HNS_ROCE_CMD_MODIFY_QPC
 
- HNS_ROCE_CMD_MODIFY_SRQC
 
- HNS_ROCE_CMD_QUERY_AEQC
 
- HNS_ROCE_CMD_QUERY_CEQC
 
- HNS_ROCE_CMD_QUERY_CQC
 
- HNS_ROCE_CMD_QUERY_MPT
 
- HNS_ROCE_CMD_QUERY_QP
 
- HNS_ROCE_CMD_QUERY_QPC
 
- HNS_ROCE_CMD_QUERY_SRQC
 
- HNS_ROCE_CMD_READ_CQC_BT0
 
- HNS_ROCE_CMD_READ_CQC_BT1
 
- HNS_ROCE_CMD_READ_CQC_BT2
 
- HNS_ROCE_CMD_READ_CQC_TIMER_BT0
 
- HNS_ROCE_CMD_READ_MPT_BT0
 
- HNS_ROCE_CMD_READ_MPT_BT1
 
- HNS_ROCE_CMD_READ_MPT_BT2
 
- HNS_ROCE_CMD_READ_QPC_BT0
 
- HNS_ROCE_CMD_READ_QPC_BT1
 
- HNS_ROCE_CMD_READ_QPC_BT2
 
- HNS_ROCE_CMD_READ_QPC_TIMER_BT0
 
- HNS_ROCE_CMD_READ_SCCC_BT0
 
- HNS_ROCE_CMD_READ_SRQC_BT0
 
- HNS_ROCE_CMD_READ_SRQC_BT1
 
- HNS_ROCE_CMD_READ_SRQC_BT2
 
- HNS_ROCE_CMD_RST2INIT_QP
 
- HNS_ROCE_CMD_RTR2RTS_QP
 
- HNS_ROCE_CMD_RTS2RTS_QP
 
- HNS_ROCE_CMD_RTS2SQD_QP
 
- HNS_ROCE_CMD_SQD2RTS_QP
 
- HNS_ROCE_CMD_SQD2SQD_QP
 
- HNS_ROCE_CMD_SUCCESS
 
- HNS_ROCE_CMD_SW2HW_CQ
 
- HNS_ROCE_CMD_SW2HW_MPT
 
- HNS_ROCE_CMD_SW2HW_SRQ
 
- HNS_ROCE_CMD_TIMEOUT_MSECS
 
- HNS_ROCE_CMD_WRITE_CQC_BT0
 
- HNS_ROCE_CMD_WRITE_CQC_BT1
 
- HNS_ROCE_CMD_WRITE_CQC_BT2
 
- HNS_ROCE_CMD_WRITE_CQC_TIMER_BT0
 
- HNS_ROCE_CMD_WRITE_MPT_BT0
 
- HNS_ROCE_CMD_WRITE_MPT_BT1
 
- HNS_ROCE_CMD_WRITE_MPT_BT2
 
- HNS_ROCE_CMD_WRITE_QPC_BT0
 
- HNS_ROCE_CMD_WRITE_QPC_BT1
 
- HNS_ROCE_CMD_WRITE_QPC_BT2
 
- HNS_ROCE_CMD_WRITE_QPC_TIMER_BT0
 
- HNS_ROCE_CMD_WRITE_SCCC_BT0
 
- HNS_ROCE_CMD_WRITE_SRQC_BT0
 
- HNS_ROCE_CMD_WRITE_SRQC_BT1
 
- HNS_ROCE_CMD_WRITE_SRQC_BT2
 
- HNS_ROCE_CMQ_DESC_NUM_S
 
- HNS_ROCE_CMQ_SCC_CLR_DONE_CNT
 
- HNS_ROCE_CMQ_TX_TIMEOUT
 
- HNS_ROCE_CONTEXT_HOP_NUM
 
- HNS_ROCE_CQE_HOP_NUM
 
- HNS_ROCE_CQE_OPCODE_MASK
 
- HNS_ROCE_CQE_QPN_MASK
 
- HNS_ROCE_CQE_STATUS_MASK
 
- HNS_ROCE_CQE_SUCCESS
 
- HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR
 
- HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR
 
- HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR
 
- HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR
 
- HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR
 
- HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR
 
- HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR
 
- HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR
 
- HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR
 
- HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR
 
- HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR
 
- HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR
 
- HNS_ROCE_CQE_V2_BAD_RESP_ERR
 
- HNS_ROCE_CQE_V2_LOCAL_ACCESS_ERR
 
- HNS_ROCE_CQE_V2_LOCAL_LENGTH_ERR
 
- HNS_ROCE_CQE_V2_LOCAL_PROT_ERR
 
- HNS_ROCE_CQE_V2_LOCAL_QP_OP_ERR
 
- HNS_ROCE_CQE_V2_MW_BIND_ERR
 
- HNS_ROCE_CQE_V2_REMOTE_ABORT_ERR
 
- HNS_ROCE_CQE_V2_REMOTE_ACCESS_ERR
 
- HNS_ROCE_CQE_V2_REMOTE_INVAL_REQ_ERR
 
- HNS_ROCE_CQE_V2_REMOTE_OP_ERR
 
- HNS_ROCE_CQE_V2_RNR_RETRY_EXC_ERR
 
- HNS_ROCE_CQE_V2_SUCCESS
 
- HNS_ROCE_CQE_V2_TRANSPORT_RETRY_EXC_ERR
 
- HNS_ROCE_CQE_V2_WR_FLUSH_ERR
 
- HNS_ROCE_CQE_WCMD_EMPTY_BIT
 
- HNS_ROCE_DB_PER_PAGE
 
- HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP
 
- HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF
 
- HNS_ROCE_DB_SUBTYPE_ODB_OVF
 
- HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP
 
- HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF
 
- HNS_ROCE_DB_SUBTYPE_SDB_OVF
 
- HNS_ROCE_DB_TYPE_COUNT
 
- HNS_ROCE_DB_UNIT_SIZE
 
- HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS
 
- HNS_ROCE_EQC_ARM_ST_M
 
- HNS_ROCE_EQC_ARM_ST_S
 
- HNS_ROCE_EQC_BA_PG_SZ_M
 
- HNS_ROCE_EQC_BA_PG_SZ_S
 
- HNS_ROCE_EQC_BUF_PG_SZ_M
 
- HNS_ROCE_EQC_BUF_PG_SZ_S
 
- HNS_ROCE_EQC_COALESCE_M
 
- HNS_ROCE_EQC_COALESCE_S
 
- HNS_ROCE_EQC_CONS_INDX_M
 
- HNS_ROCE_EQC_CONS_INDX_S
 
- HNS_ROCE_EQC_CUR_EQE_BA_H_M
 
- HNS_ROCE_EQC_CUR_EQE_BA_H_S
 
- HNS_ROCE_EQC_CUR_EQE_BA_L_M
 
- HNS_ROCE_EQC_CUR_EQE_BA_L_S
 
- HNS_ROCE_EQC_CUR_EQE_BA_M_M
 
- HNS_ROCE_EQC_CUR_EQE_BA_M_S
 
- HNS_ROCE_EQC_EQE_BA_H_M
 
- HNS_ROCE_EQC_EQE_BA_H_S
 
- HNS_ROCE_EQC_EQE_BA_L_M
 
- HNS_ROCE_EQC_EQE_BA_L_S
 
- HNS_ROCE_EQC_EQE_CNT_M
 
- HNS_ROCE_EQC_EQE_CNT_S
 
- HNS_ROCE_EQC_EQN_M
 
- HNS_ROCE_EQC_EQN_S
 
- HNS_ROCE_EQC_EQ_ST_M
 
- HNS_ROCE_EQC_EQ_ST_S
 
- HNS_ROCE_EQC_HOP_NUM_M
 
- HNS_ROCE_EQC_HOP_NUM_S
 
- HNS_ROCE_EQC_MAX_CNT_M
 
- HNS_ROCE_EQC_MAX_CNT_S
 
- HNS_ROCE_EQC_MSI_INDX_M
 
- HNS_ROCE_EQC_MSI_INDX_S
 
- HNS_ROCE_EQC_NXT_EQE_BA_H_M
 
- HNS_ROCE_EQC_NXT_EQE_BA_H_S
 
- HNS_ROCE_EQC_NXT_EQE_BA_L_M
 
- HNS_ROCE_EQC_NXT_EQE_BA_L_S
 
- HNS_ROCE_EQC_OVER_IGNORE_M
 
- HNS_ROCE_EQC_OVER_IGNORE_S
 
- HNS_ROCE_EQC_PERIOD_M
 
- HNS_ROCE_EQC_PERIOD_S
 
- HNS_ROCE_EQC_PROD_INDX_M
 
- HNS_ROCE_EQC_PROD_INDX_S
 
- HNS_ROCE_EQC_REPORT_TIMER_M
 
- HNS_ROCE_EQC_REPORT_TIMER_S
 
- HNS_ROCE_EQC_SHIFT_M
 
- HNS_ROCE_EQC_SHIFT_S
 
- HNS_ROCE_EQE_HOP_NUM
 
- HNS_ROCE_EQ_DB_CMD_AEQ
 
- HNS_ROCE_EQ_DB_CMD_AEQ_ARMED
 
- HNS_ROCE_EQ_DB_CMD_CEQ
 
- HNS_ROCE_EQ_DB_CMD_CEQ_ARMED
 
- HNS_ROCE_EQ_INIT_CONS_IDX
 
- HNS_ROCE_EQ_INIT_EQE_CNT
 
- HNS_ROCE_EQ_INIT_MSI_IDX
 
- HNS_ROCE_EQ_INIT_NXT_EQE_BA
 
- HNS_ROCE_EQ_INIT_PROD_IDX
 
- HNS_ROCE_EQ_INIT_REPORT_TIMER
 
- HNS_ROCE_EQ_STAT_INVALID
 
- HNS_ROCE_EQ_STAT_VALID
 
- HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW
 
- HNS_ROCE_EVENT_TYPE_COMM_EST
 
- HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR
 
- HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID
 
- HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW
 
- HNS_ROCE_EVENT_TYPE_DB_OVERFLOW
 
- HNS_ROCE_EVENT_TYPE_FLR
 
- HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR
 
- HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR
 
- HNS_ROCE_EVENT_TYPE_MB
 
- HNS_ROCE_EVENT_TYPE_PATH_MIG
 
- HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED
 
- HNS_ROCE_EVENT_TYPE_PORT_CHANGE
 
- HNS_ROCE_EVENT_TYPE_SQ_DRAINED
 
- HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR
 
- HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH
 
- HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH
 
- HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR
 
- HNS_ROCE_FLOW_LABEL_MASK
 
- HNS_ROCE_FRMR_MAX_PA
 
- HNS_ROCE_GID_SIZE
 
- HNS_ROCE_HEM_CHUNK_LEN
 
- HNS_ROCE_HEM_PAGE_SHIFT
 
- HNS_ROCE_HEM_PAGE_SIZE
 
- HNS_ROCE_HOP_NUM_0
 
- HNS_ROCE_HW_MB_STATUS_MASK
 
- HNS_ROCE_HW_RUN_BIT_SHIFT
 
- HNS_ROCE_HW_VER1
 
- HNS_ROCE_IB_MIN_SQ_STRIDE
 
- HNS_ROCE_IDX_HOP_NUM
 
- HNS_ROCE_IDX_QUE_ENTRY_SZ
 
- HNS_ROCE_INT_MASK_DISABLE
 
- HNS_ROCE_INT_MASK_ENABLE
 
- HNS_ROCE_INT_NAME_LEN
 
- HNS_ROCE_INVALID_LKEY
 
- HNS_ROCE_LAVWQE_KEY_STATE_ERROR
 
- HNS_ROCE_LAVWQE_LENGTH_ERROR
 
- HNS_ROCE_LAVWQE_MR_OPERATION_ERROR
 
- HNS_ROCE_LAVWQE_PD_ERROR
 
- HNS_ROCE_LAVWQE_RW_ACC_ERROR
 
- HNS_ROCE_LAVWQE_R_KEY_VIOLATION
 
- HNS_ROCE_LAVWQE_VA_ERROR
 
- HNS_ROCE_LINK_TABLE_BA1_M
 
- HNS_ROCE_LINK_TABLE_BA1_S
 
- HNS_ROCE_LINK_TABLE_NXT_PTR_M
 
- HNS_ROCE_LINK_TABLE_NXT_PTR_S
 
- HNS_ROCE_LWQCE_MTU_ERROR
 
- HNS_ROCE_LWQCE_PORT_ERROR
 
- HNS_ROCE_LWQCE_QPC_ERROR
 
- HNS_ROCE_LWQCE_SL_ERROR
 
- HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR
 
- HNS_ROCE_LWQCE_WQE_ADDR_ERROR
 
- HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR
 
- HNS_ROCE_MAILBOX_SIZE
 
- HNS_ROCE_MAX_BT_LEVEL
 
- HNS_ROCE_MAX_BT_REGION
 
- HNS_ROCE_MAX_FREE_CQ_WAIT_CNT
 
- HNS_ROCE_MAX_GID_NUM
 
- HNS_ROCE_MAX_INNER_MTPT_NUM
 
- HNS_ROCE_MAX_IRQ_NUM
 
- HNS_ROCE_MAX_MSG_LEN
 
- HNS_ROCE_MAX_MTPT_PBL_NUM
 
- HNS_ROCE_MAX_PORTS
 
- HNS_ROCE_MAX_SGE_NUM
 
- HNS_ROCE_MIN_CQE_CNT
 
- HNS_ROCE_MIN_CQE_NUM
 
- HNS_ROCE_MIN_WQE_NUM
 
- HNS_ROCE_MTT_ENTRY_PER_SEG
 
- HNS_ROCE_MTT_HOP_NUM
 
- HNS_ROCE_ODB_EXTEND_MODE
 
- HNS_ROCE_ODB_POLL_MODE
 
- HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE
 
- HNS_ROCE_OPCODE_SEND_DATA_RECEIVE
 
- HNS_ROCE_OPC_ALLOC_PF_RES
 
- HNS_ROCE_OPC_ALLOC_VF_RES
 
- HNS_ROCE_OPC_CFG_BT_ATTR
 
- HNS_ROCE_OPC_CFG_EXT_LLM
 
- HNS_ROCE_OPC_CFG_GLOBAL_PARAM
 
- HNS_ROCE_OPC_CFG_SGID_TB
 
- HNS_ROCE_OPC_CFG_SMAC_TB
 
- HNS_ROCE_OPC_CFG_TMOUT_LLM
 
- HNS_ROCE_OPC_CLR_SCCC
 
- HNS_ROCE_OPC_FUNC_CLEAR
 
- HNS_ROCE_OPC_POST_MB
 
- HNS_ROCE_OPC_QUERY_HW_VER
 
- HNS_ROCE_OPC_QUERY_MB_ST
 
- HNS_ROCE_OPC_QUERY_PF_RES
 
- HNS_ROCE_OPC_QUERY_PF_TIMER_RES
 
- HNS_ROCE_OPC_QUERY_SCCC
 
- HNS_ROCE_OPC_RESET_SCCC
 
- HNS_ROCE_PBL_HOP_NUM
 
- HNS_ROCE_PCI_BAR_NUM
 
- HNS_ROCE_PORT_DOWN
 
- HNS_ROCE_PORT_NUM_SHIFT
 
- HNS_ROCE_PORT_UP
 
- HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS
 
- HNS_ROCE_QP_NUM_ST
 
- HNS_ROCE_QP_NUM_STATE
 
- HNS_ROCE_QP_STATE_ERR
 
- HNS_ROCE_QP_STATE_INIT
 
- HNS_ROCE_QP_STATE_RST
 
- HNS_ROCE_QP_STATE_RTR
 
- HNS_ROCE_QP_STATE_RTS
 
- HNS_ROCE_QP_STATE_SQD
 
- HNS_ROCE_QP_ST_ERR
 
- HNS_ROCE_QP_ST_INIT
 
- HNS_ROCE_QP_ST_RST
 
- HNS_ROCE_QP_ST_RTR
 
- HNS_ROCE_QP_ST_RTS
 
- HNS_ROCE_QP_ST_SQD
 
- HNS_ROCE_QP_ST_SQER
 
- HNS_ROCE_QP_ST_SQ_DRAINING
 
- HNS_ROCE_RESET_FUNC
 
- HNS_ROCE_RST_DIRECT_RETURN
 
- HNS_ROCE_SCCC_HOP_NUM
 
- HNS_ROCE_SDB_EXTEND_MODE
 
- HNS_ROCE_SDB_NORMAL_MODE
 
- HNS_ROCE_SGE_IN_WQE
 
- HNS_ROCE_SGE_SHIFT
 
- HNS_ROCE_SGE_SIZE
 
- HNS_ROCE_SL_SHIFT
 
- HNS_ROCE_SQ_OPCODE_ATOMIC_COMP_AND_SWAP
 
- HNS_ROCE_SQ_OPCODE_ATOMIC_FETCH_AND_ADD
 
- HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_COMP_AND_SWAP
 
- HNS_ROCE_SQ_OPCODE_ATOMIC_MASK_FETCH_AND_ADD
 
- HNS_ROCE_SQ_OPCODE_BIND_MW
 
- HNS_ROCE_SQ_OPCODE_FAST_REG_WR
 
- HNS_ROCE_SQ_OPCODE_LOCAL_INV
 
- HNS_ROCE_SQ_OPCODE_RDMA_READ
 
- HNS_ROCE_SQ_OPCODE_RDMA_WRITE
 
- HNS_ROCE_SQ_OPCODE_RDMA_WRITE_WITH_IMM
 
- HNS_ROCE_SQ_OPCODE_SEND
 
- HNS_ROCE_SQ_OPCODE_SEND_WITH_IMM
 
- HNS_ROCE_SQ_OPCODE_SEND_WITH_INV
 
- HNS_ROCE_SRQWQE_HOP_NUM
 
- HNS_ROCE_STATE_INIT
 
- HNS_ROCE_STATE_INITED
 
- HNS_ROCE_STATE_NON_INIT
 
- HNS_ROCE_STATE_NON_RST
 
- HNS_ROCE_STATE_RST_BEF_DOWN
 
- HNS_ROCE_STATE_RST_DOWN
 
- HNS_ROCE_STATE_RST_INIT
 
- HNS_ROCE_STATE_RST_INITED
 
- HNS_ROCE_STATE_RST_UNINIT
 
- HNS_ROCE_STATE_UNINIT
 
- HNS_ROCE_SUPPORT_CQ_RECORD_DB
 
- HNS_ROCE_SUPPORT_RQ_RECORD_DB
 
- HNS_ROCE_SUPPORT_SQ_RECORD_DB
 
- HNS_ROCE_TCLASS_SHIFT
 
- HNS_ROCE_V1_ABNORMAL_VEC_NUM
 
- HNS_ROCE_V1_AEQE_VEC_NUM
 
- HNS_ROCE_V1_ASYNC_EQE_NUM
 
- HNS_ROCE_V1_COMP_EQE_NUM
 
- HNS_ROCE_V1_COMP_VEC_NUM
 
- HNS_ROCE_V1_CONS_IDX_M
 
- HNS_ROCE_V1_CQC_ENTRY_SIZE
 
- HNS_ROCE_V1_CQE_ENTRY_SIZE
 
- HNS_ROCE_V1_DB_RSVD
 
- HNS_ROCE_V1_EXT_ODB_ALEPT
 
- HNS_ROCE_V1_EXT_ODB_ALFUL
 
- HNS_ROCE_V1_EXT_ODB_DEPTH
 
- HNS_ROCE_V1_EXT_ODB_ENTRY
 
- HNS_ROCE_V1_EXT_ODB_SIZE
 
- HNS_ROCE_V1_EXT_RAQ_WF
 
- HNS_ROCE_V1_EXT_SDB_ALEPT
 
- HNS_ROCE_V1_EXT_SDB_ALFUL
 
- HNS_ROCE_V1_EXT_SDB_DEPTH
 
- HNS_ROCE_V1_EXT_SDB_ENTRY
 
- HNS_ROCE_V1_EXT_SDB_SIZE
 
- HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS
 
- HNS_ROCE_V1_FREE_MR_WAIT_VALUE
 
- HNS_ROCE_V1_GID_NUM
 
- HNS_ROCE_V1_INLINE_SIZE
 
- HNS_ROCE_V1_IRRL_ENTRY_SIZE
 
- HNS_ROCE_V1_MAX_CQE_NUM
 
- HNS_ROCE_V1_MAX_CQ_NUM
 
- HNS_ROCE_V1_MAX_IRQ_NUM
 
- HNS_ROCE_V1_MAX_MTPT_NUM
 
- HNS_ROCE_V1_MAX_MTT_SEGS
 
- HNS_ROCE_V1_MAX_PD_NUM
 
- HNS_ROCE_V1_MAX_QP_DEST_RDMA
 
- HNS_ROCE_V1_MAX_QP_INIT_RDMA
 
- HNS_ROCE_V1_MAX_QP_NUM
 
- HNS_ROCE_V1_MAX_RQ_DESC_SZ
 
- HNS_ROCE_V1_MAX_SQ_DESC_SZ
 
- HNS_ROCE_V1_MAX_WQE_NUM
 
- HNS_ROCE_V1_MTPT_ENTRY_SIZE
 
- HNS_ROCE_V1_MTT_ENTRY_SIZE
 
- HNS_ROCE_V1_ODB_ALEPT
 
- HNS_ROCE_V1_ODB_ALFUL
 
- HNS_ROCE_V1_ODB_DEPTH
 
- HNS_ROCE_V1_PAGE_SIZE_SUPPORT
 
- HNS_ROCE_V1_PHY_UAR_NUM
 
- HNS_ROCE_V1_QPC_ENTRY_SIZE
 
- HNS_ROCE_V1_RAQ_DEPTH
 
- HNS_ROCE_V1_RAQ_ENTRY
 
- HNS_ROCE_V1_RAQ_SIZE
 
- HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS
 
- HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE
 
- HNS_ROCE_V1_RESV_QP
 
- HNS_ROCE_V1_SDB_ALEPT
 
- HNS_ROCE_V1_SDB_ALFUL
 
- HNS_ROCE_V1_SDB_DEPTH
 
- HNS_ROCE_V1_SG_NUM
 
- HNS_ROCE_V1_TABLE_CHUNK_SIZE
 
- HNS_ROCE_V1_TPTR_BUF_SIZE
 
- HNS_ROCE_V1_TPTR_ENTRY_SIZE
 
- HNS_ROCE_V1_UAR_NUM
 
- HNS_ROCE_V2_ABNORMAL_VEC_NUM
 
- HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_M
 
- HNS_ROCE_V2_AEQE_EVENT_QUEUE_NUM_S
 
- HNS_ROCE_V2_AEQE_EVENT_TYPE_M
 
- HNS_ROCE_V2_AEQE_EVENT_TYPE_S
 
- HNS_ROCE_V2_AEQE_SUB_TYPE_M
 
- HNS_ROCE_V2_AEQE_SUB_TYPE_S
 
- HNS_ROCE_V2_AEQE_VEC_NUM
 
- HNS_ROCE_V2_AEQ_AEQE_OWNER_S
 
- HNS_ROCE_V2_ASYNC_EQE_NUM
 
- HNS_ROCE_V2_CEQE_COMP_CQN_M
 
- HNS_ROCE_V2_CEQE_COMP_CQN_S
 
- HNS_ROCE_V2_CEQ_CEQE_OWNER_S
 
- HNS_ROCE_V2_COMP_EQE_NUM
 
- HNS_ROCE_V2_COMP_VEC_NUM
 
- HNS_ROCE_V2_CONS_IDX_M
 
- HNS_ROCE_V2_CQC_ENTRY_SZ
 
- HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ
 
- HNS_ROCE_V2_CQE_ENTRY_SIZE
 
- HNS_ROCE_V2_CQE_QPN_MASK
 
- HNS_ROCE_V2_CQE_STATUS_MASK
 
- HNS_ROCE_V2_CQ_DB_NTR
 
- HNS_ROCE_V2_CQ_DB_PTR
 
- HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM
 
- HNS_ROCE_V2_CQ_DEFAULT_INTERVAL
 
- HNS_ROCE_V2_EQN_M
 
- HNS_ROCE_V2_EQ_ALWAYS_ARMED
 
- HNS_ROCE_V2_EQ_ARMED
 
- HNS_ROCE_V2_EQ_COALESCE_0
 
- HNS_ROCE_V2_EQ_COALESCE_1
 
- HNS_ROCE_V2_EQ_DB_CMD_M
 
- HNS_ROCE_V2_EQ_DB_CMD_S
 
- HNS_ROCE_V2_EQ_DB_PARA_M
 
- HNS_ROCE_V2_EQ_DB_PARA_S
 
- HNS_ROCE_V2_EQ_DB_TAG_M
 
- HNS_ROCE_V2_EQ_DB_TAG_S
 
- HNS_ROCE_V2_EQ_FIRED
 
- HNS_ROCE_V2_EQ_OVER_IGNORE_0
 
- HNS_ROCE_V2_EQ_OVER_IGNORE_1
 
- HNS_ROCE_V2_EQ_STATE_FAILURE
 
- HNS_ROCE_V2_EQ_STATE_INVALID
 
- HNS_ROCE_V2_EQ_STATE_OVERFLOW
 
- HNS_ROCE_V2_EQ_STATE_VALID
 
- HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS
 
- HNS_ROCE_V2_GID_INDEX_NUM
 
- HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS
 
- HNS_ROCE_V2_HW_RST_COMPLETION_WAIT
 
- HNS_ROCE_V2_HW_RST_TIMEOUT
 
- HNS_ROCE_V2_HW_RST_UNINT_DELAY
 
- HNS_ROCE_V2_IRRL_ENTRY_SZ
 
- HNS_ROCE_V2_MAX_CQC_TIMER_NUM
 
- HNS_ROCE_V2_MAX_CQE_NUM
 
- HNS_ROCE_V2_MAX_CQE_SEGS
 
- HNS_ROCE_V2_MAX_CQ_NUM
 
- HNS_ROCE_V2_MAX_EXTEND_SGE_NUM
 
- HNS_ROCE_V2_MAX_IDX_SEGS
 
- HNS_ROCE_V2_MAX_INNER_MTPT_NUM
 
- HNS_ROCE_V2_MAX_IRQ_NUM
 
- HNS_ROCE_V2_MAX_MTPT_NUM
 
- HNS_ROCE_V2_MAX_MTT_SEGS
 
- HNS_ROCE_V2_MAX_PD_NUM
 
- HNS_ROCE_V2_MAX_QPC_TIMER_NUM
 
- HNS_ROCE_V2_MAX_QP_DEST_RDMA
 
- HNS_ROCE_V2_MAX_QP_INIT_RDMA
 
- HNS_ROCE_V2_MAX_QP_NUM
 
- HNS_ROCE_V2_MAX_RQ_DESC_SZ
 
- HNS_ROCE_V2_MAX_RQ_SGE_NUM
 
- HNS_ROCE_V2_MAX_SQ_DESC_SZ
 
- HNS_ROCE_V2_MAX_SQ_INLINE
 
- HNS_ROCE_V2_MAX_SQ_SGE_NUM
 
- HNS_ROCE_V2_MAX_SRQ
 
- HNS_ROCE_V2_MAX_SRQWQE_NUM
 
- HNS_ROCE_V2_MAX_SRQWQE_SEGS
 
- HNS_ROCE_V2_MAX_SRQ_DESC_SZ
 
- HNS_ROCE_V2_MAX_SRQ_NUM
 
- HNS_ROCE_V2_MAX_SRQ_SGE
 
- HNS_ROCE_V2_MAX_SRQ_SGE_NUM
 
- HNS_ROCE_V2_MAX_SRQ_WR
 
- HNS_ROCE_V2_MAX_WQE_NUM
 
- HNS_ROCE_V2_MTPT_ENTRY_SZ
 
- HNS_ROCE_V2_MTT_ENTRY_SZ
 
- HNS_ROCE_V2_OPCODE_RDMA_WRITE_IMM
 
- HNS_ROCE_V2_OPCODE_SEND
 
- HNS_ROCE_V2_OPCODE_SEND_WITH_IMM
 
- HNS_ROCE_V2_OPCODE_SEND_WITH_INV
 
- HNS_ROCE_V2_PAGE_SIZE_SUPPORTED
 
- HNS_ROCE_V2_PHY_UAR_NUM
 
- HNS_ROCE_V2_QPC_ENTRY_SZ
 
- HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ
 
- HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT
 
- HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL
 
- HNS_ROCE_V2_RQ_DB
 
- HNS_ROCE_V2_RSV_QPS
 
- HNS_ROCE_V2_SCCC_ENTRY_SZ
 
- HNS_ROCE_V2_SQ_DB
 
- HNS_ROCE_V2_SRQC_ENTRY_SZ
 
- HNS_ROCE_V2_SRQ_DB
 
- HNS_ROCE_V2_TABLE_CHUNK_SIZE
 
- HNS_ROCE_V2_TRRL_ENTRY_SZ
 
- HNS_ROCE_V2_UAR_NUM
 
- HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE
 
- HNS_ROCE_V2_VF_ABN_INT_CFG_M
 
- HNS_ROCE_V2_VF_ABN_INT_EN_M
 
- HNS_ROCE_V2_VF_ABN_INT_EN_S
 
- HNS_ROCE_V2_VF_ABN_INT_ST_M
 
- HNS_ROCE_V2_VF_EVENT_INT_EN_M
 
- HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S
 
- HNS_ROCE_V2_VF_INT_ST_BUS_ERR_S
 
- HNS_ROCE_V2_VF_INT_ST_OTHER_ERR_S
 
- HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP
 
- HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD
 
- HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP
 
- HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD
 
- HNS_ROCE_V2_WQE_OP_BIND_MW_TYPE
 
- HNS_ROCE_V2_WQE_OP_FAST_REG_PMR
 
- HNS_ROCE_V2_WQE_OP_LOCAL_INV
 
- HNS_ROCE_V2_WQE_OP_MASK
 
- HNS_ROCE_V2_WQE_OP_RDMA_READ
 
- HNS_ROCE_V2_WQE_OP_RDMA_WRITE
 
- HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM
 
- HNS_ROCE_V2_WQE_OP_SEND
 
- HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM
 
- HNS_ROCE_V2_WQE_OP_SEND_WITH_INV
 
- HNS_ROCE_VF_CQC_BT_NUM
 
- HNS_ROCE_VF_EQC_NUM
 
- HNS_ROCE_VF_MPT_BT_NUM
 
- HNS_ROCE_VF_QPC_BT_NUM
 
- HNS_ROCE_VF_SCCC_BT_NUM
 
- HNS_ROCE_VF_SGID_NUM
 
- HNS_ROCE_VF_SL_NUM
 
- HNS_ROCE_VF_SMAC_NUM
 
- HNS_ROCE_VF_SRQC_BT_NUM
 
- HNS_ROCE_VLAN_SL_BIT_MASK
 
- HNS_ROCE_VLAN_SL_SHIFT
 
- HNS_ROCE_WQE_CQ_NOTIFY
 
- HNS_ROCE_WQE_FENCE
 
- HNS_ROCE_WQE_IMM
 
- HNS_ROCE_WQE_INLINE
 
- HNS_ROCE_WQE_OPCODE_LOCAL_INV
 
- HNS_ROCE_WQE_OPCODE_MASK
 
- HNS_ROCE_WQE_OPCODE_RDMA_READ
 
- HNS_ROCE_WQE_OPCODE_RDMA_WRITE
 
- HNS_ROCE_WQE_OPCODE_SEND
 
- HNS_ROCE_WQE_OPCODE_UD_SEND
 
- HNS_ROCE_WQE_REGION_MAX
 
- HNS_ROCE_WQE_SE
 
- HNS_ROCE_WQE_SGE_NUM_BIT
 
- HNS_RXD_ASID_M
 
- HNS_RXD_ASID_S
 
- HNS_RXD_BUFNUM_M
 
- HNS_RXD_BUFNUM_S
 
- HNS_RXD_CFI_B
 
- HNS_RXD_DMAC_M
 
- HNS_RXD_DMAC_S
 
- HNS_RXD_DROP_B
 
- HNS_RXD_FE_B
 
- HNS_RXD_FRAG_B
 
- HNS_RXD_IPOFFSET_M
 
- HNS_RXD_IPOFFSET_S
 
- HNS_RXD_L2E_B
 
- HNS_RXD_L3E_B
 
- HNS_RXD_L3ID_M
 
- HNS_RXD_L3ID_S
 
- HNS_RXD_L4E_B
 
- HNS_RXD_L4ID_M
 
- HNS_RXD_L4ID_S
 
- HNS_RXD_PORTID_M
 
- HNS_RXD_PORTID_S
 
- HNS_RXD_PRI_M
 
- HNS_RXD_PRI_S
 
- HNS_RXD_VLANID_M
 
- HNS_RXD_VLANID_S
 
- HNS_RXD_VLAN_M
 
- HNS_RXD_VLAN_S
 
- HNS_RXD_VLD_B
 
- HNS_RX_FLAG_L3ID_IPV4
 
- HNS_RX_FLAG_L3ID_IPV6
 
- HNS_RX_FLAG_L4ID_SCTP
 
- HNS_RX_FLAG_L4ID_TCP
 
- HNS_RX_FLAG_L4ID_UDP
 
- HNS_RX_FLAG_VLAN_PRESENT
 
- HNS_RX_HEAD_SIZE
 
- HNS_SERVICE_RING_IRQ_IDX
 
- HNS_SRV_OFFSET
 
- HNS_STATIC_REG_NUM
 
- HNS_SWITCH_PARAMETER_CFG
 
- HNS_TSO_MDOE_4BD_16K
 
- HNS_TSO_MODE_8BD_32K
 
- HNS_TXD_ASID_M
 
- HNS_TXD_ASID_S
 
- HNS_TXD_BUFNUM_M
 
- HNS_TXD_BUFNUM_S
 
- HNS_TXD_FE_B
 
- HNS_TXD_IPOFFSET_M
 
- HNS_TXD_IPOFFSET_S
 
- HNS_TXD_L3CS_B
 
- HNS_TXD_L4CS_B
 
- HNS_TXD_PORTID_M
 
- HNS_TXD_PORTID_S
 
- HNS_TXD_RA_B
 
- HNS_TXD_RI_B
 
- HNS_TXD_VLD_B
 
- HNS_TX_TIMEO_LIMIT
 
- HNS_XGE_RESET_FUNC
 
- HNS_XGMAC_DUMP_NUM
 
- HNS_XGMAC_LF_INSERT
 
- HNS_XGMAC_NO_LF_RF_INSERT
 
- HNib
 
- HOLD
 
- HOLD1
 
- HOLDEN
 
- HOLDINGPEN_CPU_OFFSET
 
- HOLDINGPEN_LOCATION_OFFSET
 
- HOLDING_TIME_DEFAULT
 
- HOLDOVER_01_MASK
 
- HOLDOVER_10_MASK
 
- HOLDOVER_MASK
 
- HOLDOVER_MODE
 
- HOLDSM
 
- HOLD_BOOT
 
- HOLD_EN
 
- HOLD_KEY_EN
 
- HOLESTARTBLOCK
 
- HOLE_ADDR
 
- HOLE_SIZE
 
- HOLLY_PCI_CFG_PHYS
 
- HOLTEKFF_MSG_LENGTH
 
- HOLTEK_FDX
 
- HOME
 
- HOME_CMD
 
- HOME_HOLD
 
- HOME_MODE
 
- HOME_PRESS
 
- HOME_RELEASE
 
- HONEYWELL_HGI80_PRODUCT_ID
 
- HONEYWELL_VENDOR_ID
 
- HOOK2MANIP
 
- HOOKN_BIT
 
- HOOK_POWER_POST
 
- HOOK_POWER_PRE
 
- HOOK_STATUS
 
- HOOK_SWITCH_MASK
 
- HOONTECH_DEVICE_DESC
 
- HOP0_MASK
 
- HOP0_SHIFT
 
- HOP0_TABLES_TOTAL_SIZE
 
- HOP1_MASK
 
- HOP1_SHIFT
 
- HOP2_MASK
 
- HOP2_SHIFT
 
- HOP3_MASK
 
- HOP3_SHIFT
 
- HOP4_MASK
 
- HOP4_SHIFT
 
- HOP_NUMBER
 
- HOP_TABLE_SIZE
 
- HORIZONTAL_ADDRESS_MASK
 
- HORIZONTAL_ADDRESS_SHIFT
 
- HORIZONTAL_TAPS_2
 
- HORIZONTAL_TAPS_5
 
- HORIZ_ACTIVE_AREA_COUNT_REG
 
- HORIZ_AUTO_SCALE
 
- HORIZ_BACK_PORCH_COUNT_REG
 
- HORIZ_FRONT_PORCH_COUNT_REG
 
- HORIZ_INTERP_BILINEAR
 
- HORIZ_INTERP_DISABLE
 
- HORIZ_INTERP_MASK
 
- HORIZ_POS
 
- HORIZ_SEED
 
- HORIZ_SYNC_PAD_COUNT_REG
 
- HORIZ_TIM_CTRL
 
- HORIZ_VAL
 
- HORNET_JDEC_ID
 
- HORZ_AUTO_RATIO
 
- HORZ_AUTO_RATIO_INC
 
- HORZ_DIVBY2_EN
 
- HORZ_FP_LOOP_STRETCH
 
- HORZ_MAX_TAPS
 
- HORZ_PANEL_SHIFT
 
- HORZ_PANEL_SIZE
 
- HORZ_PH
 
- HORZ_STRETCHING
 
- HORZ_STRETCHING_LG
 
- HORZ_STRETCH_BLEND
 
- HORZ_STRETCH_EN
 
- HORZ_STRETCH_ENABLE
 
- HORZ_STRETCH_LOOP
 
- HORZ_STRETCH_LOOP09
 
- HORZ_STRETCH_LOOP11
 
- HORZ_STRETCH_LOOP12
 
- HORZ_STRETCH_LOOP14
 
- HORZ_STRETCH_LOOP15
 
- HORZ_STRETCH_MODE
 
- HORZ_STRETCH_PIXREP
 
- HORZ_STRETCH_RATIO
 
- HORZ_STRETCH_RATIO_MASK
 
- HORZ_STRETCH_RATIO_MAX
 
- HOR_PHASE_SHIFT
 
- HOST1X_BUS_H
 
- HOST1X_CHANNEL_CHANNELCTRL
 
- HOST1X_CHANNEL_CHANNELCTRL_KERNEL_FILTER_GBUFFER
 
- HOST1X_CHANNEL_CHANNELSTAT
 
- HOST1X_CHANNEL_CMDFIFO_RDATA
 
- HOST1X_CHANNEL_CMDFIFO_STAT
 
- HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY
 
- HOST1X_CHANNEL_CMDPROC_STOP
 
- HOST1X_CHANNEL_CMDP_CLASS
 
- HOST1X_CHANNEL_CMDP_OFFSET
 
- HOST1X_CHANNEL_DMACTRL
 
- HOST1X_CHANNEL_DMACTRL_DMAGETRST
 
- HOST1X_CHANNEL_DMACTRL_DMAINITGET
 
- HOST1X_CHANNEL_DMACTRL_DMASTOP
 
- HOST1X_CHANNEL_DMACTRL_DMASTOP_V
 
- HOST1X_CHANNEL_DMAEND
 
- HOST1X_CHANNEL_DMAEND_HI
 
- HOST1X_CHANNEL_DMAGET
 
- HOST1X_CHANNEL_DMAGET_HI
 
- HOST1X_CHANNEL_DMAPUT
 
- HOST1X_CHANNEL_DMAPUT_HI
 
- HOST1X_CHANNEL_DMASTART
 
- HOST1X_CHANNEL_DMASTART_HI
 
- HOST1X_CHANNEL_FIFOSTAT
 
- HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V
 
- HOST1X_CHANNEL_SMMU_STREAMID
 
- HOST1X_CHANNEL_TEARDOWN
 
- HOST1X_CLASS_GR2D
 
- HOST1X_CLASS_GR2D_SB
 
- HOST1X_CLASS_GR3D
 
- HOST1X_CLASS_HOST1X
 
- HOST1X_CLASS_VIC
 
- HOST1X_DEBUG_MAX_PAGE_OFFSET
 
- HOST1X_DEV_H
 
- HOST1X_DRM_H
 
- HOST1X_HOST1X01_H
 
- HOST1X_HOST1X02_H
 
- HOST1X_HOST1X04_H
 
- HOST1X_HOST1X05_H
 
- HOST1X_HOST1X06_H
 
- HOST1X_HOST1X07_H
 
- HOST1X_HV_CH_KERNEL_FILTER_GBUFFER
 
- HOST1X_HV_CMDFIFO_PEEK_CTRL
 
- HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR
 
- HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL
 
- HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE
 
- HOST1X_HV_CMDFIFO_PEEK_PTRS
 
- HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V
 
- HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V
 
- HOST1X_HV_CMDFIFO_PEEK_READ
 
- HOST1X_HV_CMDFIFO_SETUP
 
- HOST1X_HV_CMDFIFO_SETUP_BASE_V
 
- HOST1X_HV_CMDFIFO_SETUP_LIMIT_V
 
- HOST1X_HV_ICG_EN_OVERRIDE
 
- HOST1X_HV_SYNCPT_PROT_EN
 
- HOST1X_HV_SYNCPT_PROT_EN_CH_EN
 
- HOST1X_HW
 
- HOST1X_HW_HOST1X02_CHANNEL_H
 
- HOST1X_HW_HOST1X02_SYNC_H
 
- HOST1X_HW_HOST1X02_UCLASS_H
 
- HOST1X_HW_HOST1X04_CHANNEL_H
 
- HOST1X_HW_HOST1X04_SYNC_H
 
- HOST1X_HW_HOST1X04_UCLASS_H
 
- HOST1X_HW_HOST1X05_CHANNEL_H
 
- HOST1X_HW_HOST1X05_SYNC_H
 
- HOST1X_HW_HOST1X05_UCLASS_H
 
- HOST1X_HW_HOST1X06_CHANNEL_H
 
- HOST1X_HW_HOST1X06_UCLASS_H
 
- HOST1X_HW_HOST1X07_CHANNEL_H
 
- HOST1X_HW_HOST1X07_UCLASS_H
 
- HOST1X_INTR_ACTION_COUNT
 
- HOST1X_INTR_ACTION_SUBMIT_COMPLETE
 
- HOST1X_INTR_ACTION_WAKEUP
 
- HOST1X_INTR_ACTION_WAKEUP_INTERRUPTIBLE
 
- HOST1X_OPCODE_EXTEND
 
- HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK
 
- HOST1X_OPCODE_EXTEND_RELEASE_MLOCK
 
- HOST1X_OPCODE_GATHER
 
- HOST1X_OPCODE_GATHER_W
 
- HOST1X_OPCODE_IMM
 
- HOST1X_OPCODE_INCR
 
- HOST1X_OPCODE_INCR_W
 
- HOST1X_OPCODE_MASK
 
- HOST1X_OPCODE_NONINCR
 
- HOST1X_OPCODE_NONINCR_W
 
- HOST1X_OPCODE_NOP
 
- HOST1X_OPCODE_RESTART
 
- HOST1X_OPCODE_RESTART_W
 
- HOST1X_OPCODE_SETAPPID
 
- HOST1X_OPCODE_SETCLASS
 
- HOST1X_OPCODE_SETPYLD
 
- HOST1X_OPCODE_SETSTRMID
 
- HOST1X_PUSHBUFFER_SLOTS
 
- HOST1X_SYNCPT_CLIENT_MANAGED
 
- HOST1X_SYNCPT_HAS_BASE
 
- HOST1X_SYNCPT_RESERVED
 
- HOST1X_SYNC_CBREAD
 
- HOST1X_SYNC_CBSTAT
 
- HOST1X_SYNC_CBSTAT_CBCLASS_V
 
- HOST1X_SYNC_CBSTAT_CBOFFSET_V
 
- HOST1X_SYNC_CFPEEK_CTRL
 
- HOST1X_SYNC_CFPEEK_CTRL_ADDR_F
 
- HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F
 
- HOST1X_SYNC_CFPEEK_CTRL_ENA_F
 
- HOST1X_SYNC_CFPEEK_PTRS
 
- HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V
 
- HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V
 
- HOST1X_SYNC_CFPEEK_READ
 
- HOST1X_SYNC_CF_SETUP
 
- HOST1X_SYNC_CF_SETUP_BASE_V
 
- HOST1X_SYNC_CF_SETUP_LIMIT_V
 
- HOST1X_SYNC_CH_TEARDOWN
 
- HOST1X_SYNC_CMDPROC_STOP
 
- HOST1X_SYNC_CTXSW_TIMEOUT_CFG
 
- HOST1X_SYNC_IP_BUSY_TIMEOUT
 
- HOST1X_SYNC_MLOCK_OWNER
 
- HOST1X_SYNC_MLOCK_OWNER_CHID_V
 
- HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V
 
- HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V
 
- HOST1X_SYNC_SYNCPT
 
- HOST1X_SYNC_SYNCPT_BASE
 
- HOST1X_SYNC_SYNCPT_CH_APP
 
- HOST1X_SYNC_SYNCPT_CH_APP_CH
 
- HOST1X_SYNC_SYNCPT_CPU_INCR
 
- HOST1X_SYNC_SYNCPT_INT_THRESH
 
- HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS
 
- HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE
 
- HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0
 
- HOST1X_SYNC_USEC_CLK
 
- HOST1X_UCLASS_INCR_SYNCPT
 
- HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F
 
- HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F
 
- HOST1X_UCLASS_INCR_SYNCPT_COND_F
 
- HOST1X_UCLASS_INCR_SYNCPT_INDX_F
 
- HOST1X_UCLASS_INDOFF
 
- HOST1X_UCLASS_INDOFF_AUTOINC_F
 
- HOST1X_UCLASS_INDOFF_INDBE_F
 
- HOST1X_UCLASS_INDOFF_INDMODID_F
 
- HOST1X_UCLASS_INDOFF_INDROFFSET_F
 
- HOST1X_UCLASS_LOAD_SYNCPT_BASE
 
- HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F
 
- HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F
 
- HOST1X_UCLASS_WAIT_SYNCPT
 
- HOST1X_UCLASS_WAIT_SYNCPT_BASE
 
- HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F
 
- HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F
 
- HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F
 
- HOST1X_UCLASS_WAIT_SYNCPT_INDX_F
 
- HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F
 
- HOST1X_WAIT_SYNCPT_OFFSET
 
- HOST2BMC
 
- HOST2_SCSI_DIRECTION_VALID
 
- HOSTADDR
 
- HOSTAP_80211_H
 
- HOSTAP_ANTSEL_DIVERSITY
 
- HOSTAP_ANTSEL_DO_NOT_TOUCH
 
- HOSTAP_ANTSEL_HIGH
 
- HOSTAP_ANTSEL_LOW
 
- HOSTAP_AP_H
 
- HOSTAP_BITS_BAP_TASKLET
 
- HOSTAP_BITS_BAP_TASKLET2
 
- HOSTAP_BITS_TRANSMIT
 
- HOSTAP_CMD_QUEUE_MAX_LEN
 
- HOSTAP_COMMON_H
 
- HOSTAP_CONFIG_H
 
- HOSTAP_CRYPT_ALG_NAME_LEN
 
- HOSTAP_CRYPT_ERR_CARD_CONF_FAILED
 
- HOSTAP_CRYPT_ERR_CRYPT_INIT_FAILED
 
- HOSTAP_CRYPT_ERR_KEY_SET_FAILED
 
- HOSTAP_CRYPT_ERR_TX_KEY_SET_FAILED
 
- HOSTAP_CRYPT_ERR_UNKNOWN_ADDR
 
- HOSTAP_CRYPT_ERR_UNKNOWN_ALG
 
- HOSTAP_CRYPT_FLAG_PERMANENT
 
- HOSTAP_CRYPT_FLAG_SET_TX_KEY
 
- HOSTAP_H
 
- HOSTAP_HW_ENABLE_CMDCOMPL
 
- HOSTAP_HW_NO_DISABLE
 
- HOSTAP_HW_PCCARD
 
- HOSTAP_HW_PCI
 
- HOSTAP_HW_PLX
 
- HOSTAP_INTERFACE_AP
 
- HOSTAP_INTERFACE_MAIN
 
- HOSTAP_INTERFACE_MASTER
 
- HOSTAP_INTERFACE_STA
 
- HOSTAP_INTERFACE_WDS
 
- HOSTAP_MAX_BSS_COUNT
 
- HOSTAP_SKB_TX_DATA_MAGIC
 
- HOSTAP_TASKLET_INIT
 
- HOSTAP_TX_FLAGS_ADD_MOREDATA
 
- HOSTAP_TX_FLAGS_BUFFERED_FRAME
 
- HOSTAP_TX_FLAGS_WDS
 
- HOSTAP_WDS_AP_CLIENT
 
- HOSTAP_WDS_BROADCAST_RA
 
- HOSTAP_WDS_STANDARD_FRAME
 
- HOSTAP_WLAN_H
 
- HOSTAUDIO_DEV_DSP
 
- HOSTAUDIO_DEV_MIXER
 
- HOSTBUSY_F
 
- HOSTBUSY_S
 
- HOSTBUSY_V
 
- HOSTCC_FLOW_ATTN
 
- HOSTCC_FLOW_ATTN_MBUF_LWM
 
- HOSTCC_JUMBO_CON_IDX
 
- HOSTCC_MINI_CON_IDX
 
- HOSTCC_MODE
 
- HOSTCC_MODE_32BYTE
 
- HOSTCC_MODE_64BYTE
 
- HOSTCC_MODE_ATTN
 
- HOSTCC_MODE_CLRTICK_RXBD
 
- HOSTCC_MODE_CLRTICK_TXBD
 
- HOSTCC_MODE_COAL_VEC1_NOW
 
- HOSTCC_MODE_ENABLE
 
- HOSTCC_MODE_FULL_STATUS
 
- HOSTCC_MODE_NOINT_ON_FORCE
 
- HOSTCC_MODE_NOINT_ON_NOW
 
- HOSTCC_MODE_NOW
 
- HOSTCC_MODE_RESET
 
- HOSTCC_RET_PROD_IDX_0
 
- HOSTCC_RET_PROD_IDX_1
 
- HOSTCC_RET_PROD_IDX_10
 
- HOSTCC_RET_PROD_IDX_11
 
- HOSTCC_RET_PROD_IDX_12
 
- HOSTCC_RET_PROD_IDX_13
 
- HOSTCC_RET_PROD_IDX_14
 
- HOSTCC_RET_PROD_IDX_15
 
- HOSTCC_RET_PROD_IDX_2
 
- HOSTCC_RET_PROD_IDX_3
 
- HOSTCC_RET_PROD_IDX_4
 
- HOSTCC_RET_PROD_IDX_5
 
- HOSTCC_RET_PROD_IDX_6
 
- HOSTCC_RET_PROD_IDX_7
 
- HOSTCC_RET_PROD_IDX_8
 
- HOSTCC_RET_PROD_IDX_9
 
- HOSTCC_RXCOAL_MAXF_INT
 
- HOSTCC_RXCOAL_MAXF_INT_VEC1
 
- HOSTCC_RXCOAL_TICK_INT
 
- HOSTCC_RXCOL_TICKS
 
- HOSTCC_RXCOL_TICKS_VEC1
 
- HOSTCC_RXMAX_FRAMES
 
- HOSTCC_RXMAX_FRAMES_VEC1
 
- HOSTCC_SND_CON_IDX_0
 
- HOSTCC_SND_CON_IDX_1
 
- HOSTCC_SND_CON_IDX_10
 
- HOSTCC_SND_CON_IDX_11
 
- HOSTCC_SND_CON_IDX_12
 
- HOSTCC_SND_CON_IDX_13
 
- HOSTCC_SND_CON_IDX_14
 
- HOSTCC_SND_CON_IDX_15
 
- HOSTCC_SND_CON_IDX_2
 
- HOSTCC_SND_CON_IDX_3
 
- HOSTCC_SND_CON_IDX_4
 
- HOSTCC_SND_CON_IDX_5
 
- HOSTCC_SND_CON_IDX_6
 
- HOSTCC_SND_CON_IDX_7
 
- HOSTCC_SND_CON_IDX_8
 
- HOSTCC_SND_CON_IDX_9
 
- HOSTCC_STATBLCK_RING1
 
- HOSTCC_STATS_BLK_HOST_ADDR
 
- HOSTCC_STATS_BLK_NIC_ADDR
 
- HOSTCC_STATUS
 
- HOSTCC_STATUS_BLK_HOST_ADDR
 
- HOSTCC_STATUS_BLK_NIC_ADDR
 
- HOSTCC_STATUS_ERROR_ATTN
 
- HOSTCC_STAT_COAL_TICKS
 
- HOSTCC_STD_CON_IDX
 
- HOSTCC_TXCOAL_MAXF_INT
 
- HOSTCC_TXCOAL_MAXF_INT_VEC1
 
- HOSTCC_TXCOAL_TICK_INT
 
- HOSTCC_TXCOL_TICKS
 
- HOSTCC_TXCOL_TICKS_VEC1
 
- HOSTCC_TXMAX_FRAMES
 
- HOSTCC_TXMAX_FRAMES_VEC1
 
- HOSTCMD_SUPPORTED_RATES
 
- HOSTCR_ADHOC
 
- HOSTCR_AP
 
- HOSTCR_MACEN
 
- HOSTCR_RXON
 
- HOSTCR_RXONST
 
- HOSTCR_SOFTRST
 
- HOSTCR_TXON
 
- HOSTCR_TXONST
 
- HOSTDATA
 
- HOSTERR
 
- HOSTFCMODE_INGRESS_QUEUE_X
 
- HOSTFCMODE_STATUS_PAGE_X
 
- HOSTFLAGS_DISABLE_BG_SLEEP
 
- HOSTFN0_INT_MSK
 
- HOSTFN0_INT_STATUS
 
- HOSTFN0_LPU0_CMD_STAT
 
- HOSTFN0_LPU1_CMD_STAT
 
- HOSTFN0_LPU_MBOX0_0
 
- HOSTFN1_INT_MSK
 
- HOSTFN1_INT_STATUS
 
- HOSTFN1_LPU0_CMD_STAT
 
- HOSTFN1_LPU1_CMD_STAT
 
- HOSTFN1_LPU_MBOX0_8
 
- HOSTFN2_INT_MSK
 
- HOSTFN2_INT_STATUS
 
- HOSTFN2_LPU0_CMD_STAT
 
- HOSTFN2_LPU1_CMD_STAT
 
- HOSTFN2_LPU_MBOX0_0
 
- HOSTFN3_INT_MSK
 
- HOSTFN3_INT_STATUS
 
- HOSTFN3_LPU0_CMD_STAT
 
- HOSTFN3_LPU1_CMD_STAT
 
- HOSTFN3_LPU_MBOX0_8
 
- HOSTFN_MSIX_DEFAULT
 
- HOSTFN_MSIX_VT_INDEX_MBOX_ERR
 
- HOSTFN_MSIX_VT_OFST_NUMVT
 
- HOSTFS_ATTR_ATIME
 
- HOSTFS_ATTR_ATIME_SET
 
- HOSTFS_ATTR_ATTR_FLAG
 
- HOSTFS_ATTR_CTIME
 
- HOSTFS_ATTR_FORCE
 
- HOSTFS_ATTR_GID
 
- HOSTFS_ATTR_MODE
 
- HOSTFS_ATTR_MTIME
 
- HOSTFS_ATTR_MTIME_SET
 
- HOSTFS_ATTR_SIZE
 
- HOSTFS_ATTR_UID
 
- HOSTFS_I
 
- HOSTFS_SUPER_MAGIC
 
- HOSTIF_DM_ADD_DEVICE
 
- HOSTIF_DM_COMMAND_BASE
 
- HOSTIF_DM_ENUM_DEVICES
 
- HOSTIF_DONTCARE
 
- HOSTIF_GET_FEATURE_REPORT
 
- HOSTIF_GET_HID_DESCRIPTOR
 
- HOSTIF_GET_INPUT_REPORT
 
- HOSTIF_GET_REPORT_DESCRIPTOR
 
- HOSTIF_HID_COMMAND_BASE
 
- HOSTIF_PCI_MASTER_HOST_DIRECT
 
- HOSTIF_PCI_MASTER_HOST_INDIRECT
 
- HOSTIF_PKT_RING
 
- HOSTIF_PUBLISH_INPUT_REPORT
 
- HOSTIF_PUBLISH_INPUT_REPORT_LIST
 
- HOSTIF_SET_FEATURE_REPORT
 
- HOSTIF_SLAVE
 
- HOSTINTFPORTADDRCONTDSP0
 
- HOSTINTFPORTADDRCONTDSP1
 
- HOSTINTFPORTADDRCONTDSP2
 
- HOSTINTFPORTADDRCONTDSP3
 
- HOSTINTFPORTDATADSP0
 
- HOSTINTFPORTDATADSP1
 
- HOSTINTFPORTDATADSP2
 
- HOSTINTFPORTDATADSP3
 
- HOSTINTMASK
 
- HOSTIOPORT0
 
- HOSTIOPORT1
 
- HOSTNO
 
- HOSTPAGESIZEPF0_G
 
- HOSTPAGESIZEPF0_M
 
- HOSTPAGESIZEPF0_S
 
- HOSTPAGESIZEPF0_V
 
- HOSTPAGESIZEPF1_G
 
- HOSTPAGESIZEPF1_M
 
- HOSTPAGESIZEPF1_S
 
- HOSTPAGESIZEPF1_V
 
- HOSTPAGESIZEPF2_G
 
- HOSTPAGESIZEPF2_M
 
- HOSTPAGESIZEPF2_S
 
- HOSTPAGESIZEPF2_V
 
- HOSTPAGESIZEPF3_G
 
- HOSTPAGESIZEPF3_M
 
- HOSTPAGESIZEPF3_S
 
- HOSTPAGESIZEPF3_V
 
- HOSTPAGESIZEPF4_G
 
- HOSTPAGESIZEPF4_M
 
- HOSTPAGESIZEPF4_S
 
- HOSTPAGESIZEPF4_V
 
- HOSTPAGESIZEPF5_G
 
- HOSTPAGESIZEPF5_M
 
- HOSTPAGESIZEPF5_S
 
- HOSTPAGESIZEPF5_V
 
- HOSTPAGESIZEPF6_G
 
- HOSTPAGESIZEPF6_M
 
- HOSTPAGESIZEPF6_S
 
- HOSTPAGESIZEPF6_V
 
- HOSTPAGESIZEPF7_G
 
- HOSTPAGESIZEPF7_M
 
- HOSTPAGESIZEPF7_S
 
- HOSTPAGESIZEPF7_V
 
- HOSTPC_PHCD
 
- HOSTPC_PSPD
 
- HOSTQ_SIZE
 
- HOSTRCB_ERROR_RESPONSE_SENT
 
- HOSTRCB_INTERNAL_OP_ERROR
 
- HOSTRCB_NOTIFICATIONS_LOST
 
- HOSTRCB_OVERLAY_ID_08
 
- HOSTRCB_OVERLAY_ID_09
 
- HOSTRCB_OVERLAY_ID_11
 
- HOSTRCB_OVERLAY_ID_12
 
- HOSTRCB_OVERLAY_ID_13
 
- HOSTRCB_OVERLAY_ID_14
 
- HOSTRCB_OVERLAY_ID_16
 
- HOSTRCB_OVERLAY_ID_17
 
- HOSTRCB_OVERLAY_ID_20
 
- HOSTRCB_OVERLAY_ID_FF
 
- HOSTRCB_TYPE_CCN
 
- HOSTRCB_TYPE_LDN
 
- HOSTSLEEP
 
- HOSTSTOP
 
- HOSTUEADDR
 
- HOSTUESTATUS
 
- HOSTWDSZ
 
- HOSTWEP_DECRYPT
 
- HOSTWEP_DEFAULTKEY_MASK
 
- HOSTWEP_ENCRYPT
 
- HOSTWEP_EXCLUDEUNENCRYPTED
 
- HOSTWEP_PRIVACYINVOKED
 
- HOSTWEP_SHAREDKEY
 
- HOSTWRITE_F
 
- HOSTWRITE_S
 
- HOSTWRITE_V
 
- HOST_15BPP
 
- HOST_16BPP
 
- HOST_1BPP
 
- HOST_24BPP
 
- HOST_32BPP
 
- HOST_4BPP
 
- HOST_8BPP
 
- HOST_ABORTED
 
- HOST_ACTRL
 
- HOST_AHCI_EN
 
- HOST_ALLOWED
 
- HOST_BAD_PHAS
 
- HOST_BG_SCAN_TRIG
 
- HOST_BIG_ENDIAN_EN
 
- HOST_BIST_CTRL
 
- HOST_BIST_PTRN
 
- HOST_BIST_STAT
 
- HOST_BLKSIZE
 
- HOST_BUFFER_FIELD
 
- HOST_BUF_COEFF_COMPAT_VER_MASK
 
- HOST_BUF_COEFF_COMPAT_VER_SHIFT
 
- HOST_BUF_COEFF_SUPPORTED_COMPAT_VER
 
- HOST_BUSNUM_IND__HOST_ID_MASK
 
- HOST_BUSNUM_IND__HOST_ID__SHIFT
 
- HOST_BUSNUM__HOST_ID_MASK
 
- HOST_BUSNUM__HOST_ID__SHIFT
 
- HOST_BUS_FREE
 
- HOST_BYTE
 
- HOST_BYTE_ALIGN
 
- HOST_CALLEE_LR
 
- HOST_CAP
 
- HOST_CAP2
 
- HOST_CAP2_APST
 
- HOST_CAP2_BOH
 
- HOST_CAP2_DESO
 
- HOST_CAP2_NVMHCI
 
- HOST_CAP2_SADM
 
- HOST_CAP2_SDS
 
- HOST_CAP_64
 
- HOST_CAP_ALPM
 
- HOST_CAP_CCC
 
- HOST_CAP_CLO
 
- HOST_CAP_EMS
 
- HOST_CAP_FBS
 
- HOST_CAP_LED
 
- HOST_CAP_MPS
 
- HOST_CAP_NCQ
 
- HOST_CAP_NZDMA
 
- HOST_CAP_ONLY
 
- HOST_CAP_PART
 
- HOST_CAP_PIO_MULTI
 
- HOST_CAP_PMP
 
- HOST_CAP_SNTF
 
- HOST_CAP_SSC
 
- HOST_CAP_SSS
 
- HOST_CAP_SXS
 
- HOST_CLIENT_PROPERTIES_REQ_CMD
 
- HOST_CLIENT_PROPERTIES_RES_CMD
 
- HOST_CMD
 
- HOST_CMD53_FIN
 
- HOST_CMDARG
 
- HOST_CMDS_BUF_LEN
 
- HOST_CMD_APCMD_STA_LIST
 
- HOST_CMD_APCMD_SYS_RESET
 
- HOST_CMD_CSR
 
- HOST_CMD_CSR_HOST_COMMAND
 
- HOST_CMD_CSR_INTERRUPT_MCU
 
- HOST_CMD_DINO_CONFIG
 
- HOST_CNTL
 
- HOST_COMMAND
 
- HOST_COMMAND_MARK
 
- HOST_COMMAND_NO_WAIT
 
- HOST_COMMAND_PARAMS_REG_LEN
 
- HOST_COMMAND_WAIT
 
- HOST_COMPLETE
 
- HOST_COMPLETE_TIMEOUT
 
- HOST_CONFIG
 
- HOST_CONFIG2
 
- HOST_CONTROL
 
- HOST_CONTROL_CLOCK_EN
 
- HOST_CONTROL_FAST_CLK
 
- HOST_CONTROL_HW_OC_P
 
- HOST_CONTROL_IF_PAR4
 
- HOST_CONTROL_IF_PAR8
 
- HOST_CONTROL_IF_SERIAL
 
- HOST_CONTROL_IF_SHIFT
 
- HOST_CONTROL_LED
 
- HOST_CONTROL_POWER_EN
 
- HOST_CONTROL_REI
 
- HOST_CONTROL_REO
 
- HOST_CONTROL_RESET
 
- HOST_CONTROL_RESET_REQ
 
- HOST_CONTROL_TDELAY_EN
 
- HOST_COUNTER
 
- HOST_COUNTER_CLEAR
 
- HOST_CR
 
- HOST_CR0
 
- HOST_CR3
 
- HOST_CR4
 
- HOST_CRASHING
 
- HOST_CS_SELECTOR
 
- HOST_CTL
 
- HOST_CTL_REG
 
- HOST_CTRL
 
- HOST_CTRL_DEVSEL
 
- HOST_CTRL_GLOBAL_RST
 
- HOST_CTRL_INT_MASK_REG
 
- HOST_CTRL_INT_STATUS_REG
 
- HOST_CTRL_IO
 
- HOST_CTRL_M66EN
 
- HOST_CTRL_REQ64
 
- HOST_CTRL_STOP
 
- HOST_CTRL_TRDY
 
- HOST_DATA
 
- HOST_DATA0
 
- HOST_DATA1
 
- HOST_DATA2
 
- HOST_DATA3
 
- HOST_DATA4
 
- HOST_DATA5
 
- HOST_DATA6
 
- HOST_DATA7
 
- HOST_DATA8
 
- HOST_DATA9
 
- HOST_DATAA
 
- HOST_DATAB
 
- HOST_DATAC
 
- HOST_DATAD
 
- HOST_DATAE
 
- HOST_DATAF
 
- HOST_DATA_IO
 
- HOST_DATA_LAST
 
- HOST_DATA_START_ADDR
 
- HOST_DEBUG
 
- HOST_DEVICE_LIST_SZ
 
- HOST_DEV_RST
 
- HOST_DIAGNOSTIC_OFFSET
 
- HOST_DIAG_RESET_ADAPTER
 
- HOST_DIAG_WRITE_ENABLE
 
- HOST_DMA_A
 
- HOST_DMA_ALT_QTD
 
- HOST_DMA_EOL
 
- HOST_DMA_IOC
 
- HOST_DMA_ISOC_NBYTES_MASK
 
- HOST_DMA_ISOC_NBYTES_SHIFT
 
- HOST_DMA_NBYTES_LIMIT
 
- HOST_DMA_NBYTES_MASK
 
- HOST_DMA_NBYTES_SHIFT
 
- HOST_DMA_QTD_OFFSET_MASK
 
- HOST_DMA_QTD_OFFSET_SHIFT
 
- HOST_DMA_STS_MASK
 
- HOST_DMA_STS_PKTERR
 
- HOST_DMA_STS_SHIFT
 
- HOST_DMA_SUP
 
- HOST_DO_DU
 
- HOST_DS
 
- HOST_DS_SELECTOR
 
- HOST_EM_CTL
 
- HOST_EM_LOC
 
- HOST_EN
 
- HOST_ENABLE
 
- HOST_ENDIAN_HIGH_WORD1
 
- HOST_ENDIAN_LOW_WORD0
 
- HOST_ENTER_S1
 
- HOST_ENTER_S3
 
- HOST_ENUM_REQ_CMD
 
- HOST_ENUM_RES_CMD
 
- HOST_EOT_GEN
 
- HOST_ERROR_INDICATOR
 
- HOST_ES
 
- HOST_ES_SELECTOR
 
- HOST_EVENT_MARK
 
- HOST_FENCE
 
- HOST_FLAGS_OFFSET
 
- HOST_FLASH_CMD
 
- HOST_FLASH_DATA
 
- HOST_FRAME_MASK
 
- HOST_FRAME_REG
 
- HOST_FS
 
- HOST_FS_BASE
 
- HOST_FS_SELECTOR
 
- HOST_F_ACTIVE
 
- HOST_F_DBDMA
 
- HOST_F_DMA
 
- HOST_F_RECV
 
- HOST_F_STOP
 
- HOST_F_XMIT
 
- HOST_GDTR_BASE
 
- HOST_GET
 
- HOST_GPIO_CTRL
 
- HOST_GS
 
- HOST_GS_BASE
 
- HOST_GS_SELECTOR
 
- HOST_GUEST_PADDING
 
- HOST_HANDSHAKE_TIMEOUT
 
- HOST_HDR_OFFSET
 
- HOST_HIGH_CMD_ENTRIES
 
- HOST_HIGH_GM_SIZE
 
- HOST_HIGH_RESP_ENTRIES
 
- HOST_HSORG
 
- HOST_I2C_ADDR
 
- HOST_I2C_CTRL
 
- HOST_I2C_DATA
 
- HOST_I2C_XFER_CNT
 
- HOST_IA32_EFER
 
- HOST_IA32_EFER_HIGH
 
- HOST_IA32_PAT
 
- HOST_IA32_PAT_HIGH
 
- HOST_IA32_PERF_GLOBAL_CTRL
 
- HOST_IA32_PERF_GLOBAL_CTRL_HIGH
 
- HOST_IA32_SYSENTER_CS
 
- HOST_IA32_SYSENTER_EIP
 
- HOST_IA32_SYSENTER_ESP
 
- HOST_IDTR_BASE
 
- HOST_IF_CFG_ADD_RX_ALIGNMENT
 
- HOST_IF_CFG_RX_FIFO_ENABLE
 
- HOST_IF_CFG_RX_PAD_TO_SDIO_BLK
 
- HOST_IF_CFG_TX_EXTRA_BLKS_SWAP
 
- HOST_IF_CFG_TX_PAD_TO_SDIO_BLK
 
- HOST_IF_CONNECTED
 
- HOST_IF_CONNECTING
 
- HOST_IF_FORCE_32BIT
 
- HOST_IF_IDLE
 
- HOST_IF_P2P_LISTEN
 
- HOST_IF_SCANNING
 
- HOST_IF_WAITING_CONN_RESP
 
- HOST_INFO_MACRDCTBLN
 
- HOST_INFO_MPR
 
- HOST_INT
 
- HOST_INTEREST_MAX_SIZE
 
- HOST_INTEREST_SMPS_IS_ALLOWED
 
- HOST_INTERFACE_ERROR
 
- HOST_INTERFACE_VERSION
 
- HOST_INTERFACE_VERSION_MASK
 
- HOST_INTERFACE_VERSION_SHIFT
 
- HOST_INTR_CMD_DONE
 
- HOST_INTR_DNLD_DONE
 
- HOST_INTR_EVENT_RDY
 
- HOST_INTR_MASK
 
- HOST_INTR_UPLD_RDY
 
- HOST_INT_CTRL
 
- HOST_INT_H
 
- HOST_INT_STATUS
 
- HOST_INT_STATUS_ADDRESS
 
- HOST_INT_STATUS_COUNTER
 
- HOST_INT_STATUS_COUNTER_LSB
 
- HOST_INT_STATUS_COUNTER_MASK
 
- HOST_INT_STATUS_COUNTER_S
 
- HOST_INT_STATUS_CPU
 
- HOST_INT_STATUS_CPU_LSB
 
- HOST_INT_STATUS_CPU_MASK
 
- HOST_INT_STATUS_CPU_S
 
- HOST_INT_STATUS_ERROR
 
- HOST_INT_STATUS_ERROR_LSB
 
- HOST_INT_STATUS_ERROR_MASK
 
- HOST_INT_STATUS_ERROR_S
 
- HOST_INV_CMD
 
- HOST_IRQ_EN
 
- HOST_IRQ_EN_REG
 
- HOST_IRQ_MASK
 
- HOST_IRQ_STAT
 
- HOST_KERNEL_ID
 
- HOST_KEY_LEN
 
- HOST_LINK_BUF_SIZE
 
- HOST_LOW_GM_SIZE
 
- HOST_MASK
 
- HOST_MBOX
 
- HOST_MEM_BIST_STAT
 
- HOST_MEM_BLOCK
 
- HOST_MEM_CFG_PAGE
 
- HOST_MIN_STACK_SIZE
 
- HOST_MODE
 
- HOST_MODE8
 
- HOST_MRSM
 
- HOST_MSG_SIZE
 
- HOST_MSIX_ERR_INDEX_FN0
 
- HOST_MSIX_ERR_INDEX_FN1
 
- HOST_MSIX_ERR_INDEX_FN2
 
- HOST_MSIX_ERR_INDEX_FN3
 
- HOST_NORM_CMD_ENTRIES
 
- HOST_NORM_RESP_ENTRIES
 
- HOST_NOTIFICATION_CALIB_KEEP_RESULTS
 
- HOST_NOTIFICATION_CHANNEL_SWITCHED
 
- HOST_NOTIFICATION_DINO_CONFIG_RESPONSE
 
- HOST_NOTIFICATION_MEASUREMENT_ENDED
 
- HOST_NOTIFICATION_MEASUREMENT_STARTED
 
- HOST_NOTIFICATION_NOISE_STATS
 
- HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD
 
- HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED
 
- HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED
 
- HOST_NOTIFICATION_STATUS_ASSOCIATED
 
- HOST_NOTIFICATION_STATUS_AUTHENTICATE
 
- HOST_NOTIFICATION_STATUS_BEACON_MISSING
 
- HOST_NOTIFICATION_STATUS_BEACON_STATE
 
- HOST_NOTIFICATION_STATUS_FRAG_LENGTH
 
- HOST_NOTIFICATION_STATUS_LINK_DETERIORATION
 
- HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT
 
- HOST_NOTIFICATION_STATUS_SCAN_COMPLETED
 
- HOST_NOTIFICATION_STATUS_TGI_TX_KEY
 
- HOST_NOTIFICATION_TX_STATUS
 
- HOST_NOTIFICATION_VAL
 
- HOST_NV_GPR
 
- HOST_NV_GPRS
 
- HOST_ORDER
 
- HOST_PAGE_NUM_FN0
 
- HOST_PAGE_NUM_FN1
 
- HOST_PAGE_NUM_FN2
 
- HOST_PAGE_NUM_FN3
 
- HOST_PATH_CNTL
 
- HOST_PHYS_BASE
 
- HOST_PHYS_SIZE
 
- HOST_PHY_CFG
 
- HOST_PORT
 
- HOST_PORTS_IMPL
 
- HOST_PORT_EVENT_INTERRUPT
 
- HOST_PORT_NUM
 
- HOST_POWER_UP
 
- HOST_PRE_POWER_DOWN
 
- HOST_R1
 
- HOST_R2
 
- HOST_RD_CMD
 
- HOST_REG1
 
- HOST_REG2
 
- HOST_REG3
 
- HOST_REGISTER1
 
- HOST_REGISTER2
 
- HOST_REQUEST_FLAG
 
- HOST_REQ_DONE
 
- HOST_RESET
 
- HOST_RESET_SETTLE_TIME
 
- HOST_RIP
 
- HOST_RSP
 
- HOST_RUN
 
- HOST_RXF_PAGENO_MASK
 
- HOST_RXF_PAGENO_SHIFT
 
- HOST_RXF_VALID
 
- HOST_RXPORT
 
- HOST_SCSI_RST
 
- HOST_SEL_TOUT
 
- HOST_SEM0_INFO_REG
 
- HOST_SEM0_REG
 
- HOST_SEM1_INFO_REG
 
- HOST_SEM1_REG
 
- HOST_SEM2_INFO_REG
 
- HOST_SEM2_REG
 
- HOST_SEM3_INFO_REG
 
- HOST_SEM3_REG
 
- HOST_SEM4_INFO_REG
 
- HOST_SEM4_REG
 
- HOST_SEM5_INFO_REG
 
- HOST_SEM5_REG
 
- HOST_SEM6_INFO_REG
 
- HOST_SEM6_REG
 
- HOST_SEM7_INFO_REG
 
- HOST_SEM7_REG
 
- HOST_SG_TBL_BUF_LEN
 
- HOST_SG_TBL_ITEMS
 
- HOST_SLEEP_EVENT_S0IX_RESUME
 
- HOST_SLEEP_EVENT_S0IX_SUSPEND
 
- HOST_SLEEP_EVENT_S3_RESUME
 
- HOST_SLEEP_EVENT_S3_SUSPEND
 
- HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND
 
- HOST_SLEEP_MODE_CMD_PROCESSED
 
- HOST_SLEEP_STATE
 
- HOST_SLOT_STAT
 
- HOST_SMC_MSG
 
- HOST_SMC_MSG_MASK
 
- HOST_SMC_MSG_SHIFT
 
- HOST_SMC_RESP
 
- HOST_SMC_RESP_MASK
 
- HOST_SMC_RESP_SHIFT
 
- HOST_SSTAT_ATTN
 
- HOST_SS_SELECTOR
 
- HOST_STACK_END_ADDR
 
- HOST_STACK_LR
 
- HOST_STACK_SIZE
 
- HOST_START_REQ_CMD
 
- HOST_START_RES_CMD
 
- HOST_STAT
 
- HOST_STATUS
 
- HOST_STAT_MASK
 
- HOST_STOP_REQ_CMD
 
- HOST_STOP_RES_CMD
 
- HOST_SWIF_OFFSH
 
- HOST_SYSTEM_TIME_USEC
 
- HOST_S_CMD
 
- HOST_S_DATA
 
- HOST_S_IDLE
 
- HOST_S_STOP
 
- HOST_TABLE_OF_DEVICES
 
- HOST_TERM_CMD53
 
- HOST_TEXT_START_ADDR
 
- HOST_TID
 
- HOST_TIMEOUT
 
- HOST_TO_DEVICE
 
- HOST_TO_ECF_BASE
 
- HOST_TO_NGENE
 
- HOST_TO_VPU
 
- HOST_TRANSITION_DETECT
 
- HOST_TR_BASE
 
- HOST_TR_SELECTOR
 
- HOST_TXPORT
 
- HOST_TX_PRI_MAP_DEFAULT
 
- HOST_T_BD_MASK
 
- HOST_T_ERROR
 
- HOST_UTC_TIME_USEC
 
- HOST_VERSION
 
- HOST_VIEW_SHMEM_BASE
 
- HOST_VSA_ADDR
 
- HOST_VSA_DATA
 
- HOST_WIDE_INT_PRINT_HEX_PURE
 
- HOST_WRITE_PORT_ENABLE
 
- HOST_WRT
 
- HOST_WRT_CMD
 
- HOT
 
- HOTDIE_INTR_OFFSET
 
- HOTKEY
 
- HOTKEY_CONFIG_CRITICAL_END
 
- HOTKEY_CONFIG_CRITICAL_START
 
- HOTMON_CONFIG_HIGH
 
- HOTMON_CONFIG_LOW
 
- HOTPLUG_CHG
 
- HOTPLUG_DEBOUNCE_MS
 
- HOTPLUG_DELAY_TIMEOUT
 
- HOTPLUG_INT_EN_MASK
 
- HOTPLUG_INT_STATUS_G4X
 
- HOTPLUG_INT_STATUS_I915
 
- HOTSPOT_UPDATE_PERIOD
 
- HOT_ADD_DISK
 
- HOT_GENERATE_ERROR
 
- HOT_PLUG_CNCT
 
- HOT_PLUG_CNCT_CLR
 
- HOT_PLUG_CNCT_EN
 
- HOT_PLUG_DELAY
 
- HOT_PLUG_DIS
 
- HOT_PLUG_EN
 
- HOT_REMOVE_DISK
 
- HOT_RESET_GEN
 
- HOT_RST_INTR
 
- HOT_RX_RESET_TS2
 
- HOT_SPOT_CMD
 
- HOT_SPOT_MAX_NUM_OF_SESSIONS
 
- HOT_SPOT_RSP_STATUS_OK
 
- HOT_SPOT_RSP_STATUS_TOO_MANY_EVENTS
 
- HOT_TX_NORESET_TS2
 
- HOURS
 
- HOURS_REG_MSK
 
- HOURS_TENS
 
- HOURS_UNITS
 
- HOUR_12
 
- HOUR_AMPM
 
- HOUR_AM_PM
 
- HOUR_MASK
 
- HOUR_PM
 
- HOUR_PM_MASK
 
- HOUR_PM_SHIFT
 
- HOUR_SHIFT
 
- HOUTSIZE
 
- HOWNER_KERNEL
 
- HP03_ADC_ADDR
 
- HP03_ADC_READ_PRESSURE
 
- HP03_ADC_READ_REG
 
- HP03_ADC_READ_TEMP
 
- HP03_ADC_WRITE_REG
 
- HP03_EEPROM_AB_OFFSET
 
- HP03_EEPROM_ADDR
 
- HP03_EEPROM_CD_OFFSET
 
- HP03_EEPROM_CX_OFFSET
 
- HP100_ACCFA
 
- HP100_ACCNA
 
- HP100_ACC_BC
 
- HP100_ACC_ERRORED
 
- HP100_ACC_MC
 
- HP100_ACC_PHY
 
- HP100_ADV_NXT_PKT
 
- HP100_ALN_ERR
 
- HP100_ARB_MODE
 
- HP100_AUI_SEL
 
- HP100_AUI_ST
 
- HP100_AUTO_COMPARE
 
- HP100_AUTO_MODE
 
- HP100_AUTO_SEL_10
 
- HP100_BAD_SYMBOL_ERR
 
- HP100_BM_BURST_RD
 
- HP100_BM_BURST_WR
 
- HP100_BM_MASTER
 
- HP100_BM_PAGE_CK
 
- HP100_BM_PCI_8CLK
 
- HP100_BM_READ
 
- HP100_BM_WRITE
 
- HP100_BOND_HP
 
- HP100_BOOT_EN
 
- HP100_BRIDGE
 
- HP100_BROADCAST_ADDR
 
- HP100_BUSTYPE_MASK
 
- HP100_BUS_EISA
 
- HP100_BUS_ISA
 
- HP100_BUS_PCI
 
- HP100_CARD_MACVER
 
- HP100_CHIPID_LASSEN
 
- HP100_CHIPID_MASK
 
- HP100_CHIPID_RAINIER
 
- HP100_CHIPID_SHASTA
 
- HP100_CRC_ERR
 
- HP100_CRC_I
 
- HP100_DEBUG
 
- HP100_DEBUG_B
 
- HP100_DEBUG_BM
 
- HP100_DEBUG_EN
 
- HP100_DEBUG_IRQ
 
- HP100_DEBUG_RX
 
- HP100_DEBUG_TRAINING
 
- HP100_DEBUG_TX
 
- HP100_DEFAULT_PRIORITY_TX
 
- HP100_DEFAULT_RX_RATIO
 
- HP100_DEVICES
 
- HP100_DIS_CANCEL
 
- HP100_DOT3_MAC
 
- HP100_EEPROM_LOAD
 
- HP100_EE_EN
 
- HP100_EE_LOAD
 
- HP100_EE_MASK
 
- HP100_EE_NOLOAD
 
- HP100_EN_ADAPTIVE
 
- HP100_EN_BUS_FAIL
 
- HP100_EN_EARLY_RX
 
- HP100_EN_EARLY_TX
 
- HP100_EN_LOW_RX
 
- HP100_EN_LOW_TX
 
- HP100_EN_PDL_WB
 
- HP100_EN_TX_UR_IRQ
 
- HP100_ET_CNT_MASK
 
- HP100_FAKE_INT
 
- HP100_FRAME_FORMAT
 
- HP100_FREE_SPACE
 
- HP100_FULLDUP
 
- HP100_HUB_MACVER
 
- HP100_HW_ID_CASCADE
 
- HP100_HW_RST
 
- HP100_IGNORE_PAR
 
- HP100_INT_EN
 
- HP100_IO_EN
 
- HP100_IRQMASK
 
- HP100_IRQ_HI_MASK
 
- HP100_IRQ_SCRAMBLE
 
- HP100_ISR_CLRMODE
 
- HP100_KEEP_CRC
 
- HP100_LAN_10
 
- HP100_LAN_100
 
- HP100_LAN_COAX
 
- HP100_LAN_ERR
 
- HP100_LBK_MAC
 
- HP100_LBK_XCVR
 
- HP100_LEVEL_IRQ
 
- HP100_LINK_BEAT_DIS
 
- HP100_LINK_BEAT_ST
 
- HP100_LINK_CABLE_ST
 
- HP100_LINK_CMD
 
- HP100_LINK_FAIL_ST
 
- HP100_LINK_GOOD_ST
 
- HP100_LINK_UP_ST
 
- HP100_LOAD_ADDR
 
- HP100_LOW_TH
 
- HP100_LO_MEM
 
- HP100_LRF_EN
 
- HP100_MAC10_SEL
 
- HP100_MAC1MODE1
 
- HP100_MAC1MODE2
 
- HP100_MAC1MODE3
 
- HP100_MAC1MODE4
 
- HP100_MAC1MODE5
 
- HP100_MAC1MODE6
 
- HP100_MAC1MODE7
 
- HP100_MAC1MODEMASK
 
- HP100_MAC2MODE1
 
- HP100_MAC2MODE2
 
- HP100_MAC2MODE3
 
- HP100_MAC2MODE4
 
- HP100_MAC2MODE5
 
- HP100_MAC2MODE6
 
- HP100_MAC2MODE7
 
- HP100_MAC2MODEMASK
 
- HP100_MACRQ_FRAMEFMT_802_3
 
- HP100_MACRQ_FRAMEFMT_802_5
 
- HP100_MACRQ_FRAMEFMT_EITHER
 
- HP100_MACRQ_PROMSC
 
- HP100_MACRQ_REPEATER
 
- HP100_MAC_SEL_ST
 
- HP100_MALLOW_ACCDENIED
 
- HP100_MALLOW_CONFIGURE
 
- HP100_MALLOW_DUPADDR
 
- HP100_MALLOW_FRAMEFMT
 
- HP100_MALLOW_PROMSC
 
- HP100_MALLOW_REPEATER
 
- HP100_MAX_PACKET_SIZE
 
- HP100_MEM_EN
 
- HP100_MIN_PACKET_SIZE
 
- HP100_MISC_ERROR
 
- HP100_MMAP_DIS
 
- HP100_MULTICAST_FILTER
 
- HP100_MULTI_ADDR_HASH
 
- HP100_MULTI_ADDR_NO_HASH
 
- HP100_MWI
 
- HP100_NO_MEM
 
- HP100_PACKET_PACE
 
- HP100_PAGE_EEPROM_CTRL
 
- HP100_PAGE_HW_MAP
 
- HP100_PAGE_ID_MAC_ADDR
 
- HP100_PAGE_MAC_ADDRESS
 
- HP100_PAGE_MAC_CTRL
 
- HP100_PAGE_MMU_CFG
 
- HP100_PAGE_MMU_POINTER
 
- HP100_PAGE_PERFORMANCE
 
- HP100_PCI_IRQ_HI_MASK
 
- HP100_PCI_RESET
 
- HP100_PDL_USE3
 
- HP100_PHYS_ADDR_MATCH
 
- HP100_PHYS_ADDR_NO_MATCH
 
- HP100_PKT_LEN_MASK
 
- HP100_PRIORITY_TX
 
- HP100_PROM_MODE
 
- HP100_RAM_SIZE_MASK
 
- HP100_RAM_SIZE_SHIFT
 
- HP100_RCV_IPM_ERR
 
- HP100_RD_LINE_PDL
 
- HP100_RD_TX_DATA_MASK
 
- HP100_REGION_SIZE
 
- HP100_REG_10_LAN_CFG_1
 
- HP100_REG_10_LAN_CFG_2
 
- HP100_REG_32_FRAGMENT_LEN
 
- HP100_REG_32_OFFSET
 
- HP100_REG_ABORT
 
- HP100_REG_BM
 
- HP100_REG_BOARD_ID
 
- HP100_REG_BOARD_IO_CHCK
 
- HP100_REG_BOOTROM_CTRL
 
- HP100_REG_CRC
 
- HP100_REG_DATA16
 
- HP100_REG_DATA32
 
- HP100_REG_DROPPED
 
- HP100_REG_EARLYRXCFG
 
- HP100_REG_EARLYTXCFG
 
- HP100_REG_ECB_MEM_STOP
 
- HP100_REG_EEPROM_CTRL
 
- HP100_REG_FRAGMENT_LEN
 
- HP100_REG_HASH_BYTE0
 
- HP100_REG_HW_ID
 
- HP100_REG_IO_MAP
 
- HP100_REG_IRQ_CHANNEL
 
- HP100_REG_IRQ_MASK
 
- HP100_REG_IRQ_STATUS
 
- HP100_REG_ISAPNPCFG1
 
- HP100_REG_ISAPNPCFG2
 
- HP100_REG_LAN_ADDR
 
- HP100_REG_LAN_ADDR_CHCK
 
- HP100_REG_MAC_ADDR
 
- HP100_REG_MAC_CFG_1
 
- HP100_REG_MAC_CFG_2
 
- HP100_REG_MAC_CFG_3
 
- HP100_REG_MAC_CFG_4
 
- HP100_REG_MEM_MAP_LSW
 
- HP100_REG_MEM_MAP_MSW
 
- HP100_REG_MODECTRL1
 
- HP100_REG_MODECTRL2
 
- HP100_REG_OFFSET
 
- HP100_REG_OPTION_LSW
 
- HP100_REG_OPTION_MSW
 
- HP100_REG_PAGING
 
- HP100_REG_PCIBUSMLAT
 
- HP100_REG_PCICTRL1
 
- HP100_REG_PCICTRL2
 
- HP100_REG_PDL_MEM_STOP
 
- HP100_REG_PTR_MEMDEBUG
 
- HP100_REG_PTR_RINGPTRS
 
- HP100_REG_PTR_RPDLEND
 
- HP100_REG_PTR_RPDLSTART
 
- HP100_REG_PTR_RXEND
 
- HP100_REG_PTR_RXSTART
 
- HP100_REG_PTR_TXEND
 
- HP100_REG_PTR_TXSTART
 
- HP100_REG_RX_MEM_STOP
 
- HP100_REG_RX_PDA
 
- HP100_REG_RX_PDL
 
- HP100_REG_RX_PKT_CNT
 
- HP100_REG_RX_RING
 
- HP100_REG_SL_EARLY
 
- HP100_REG_SOFT_MODEL
 
- HP100_REG_SRAM
 
- HP100_REG_STAT_ABORT
 
- HP100_REG_STAT_DROPPED
 
- HP100_REG_STAT_ERRORED
 
- HP100_REG_TRACE
 
- HP100_REG_TRAIN_ALLOW
 
- HP100_REG_TRAIN_REQUEST
 
- HP100_REG_TX_MEM_FREE
 
- HP100_REG_TX_MEM_STOP
 
- HP100_REG_TX_PDA_H
 
- HP100_REG_TX_PDA_L
 
- HP100_REG_TX_PDL
 
- HP100_REG_TX_PKT_CNT
 
- HP100_REG_VG_LAN_CFG_1
 
- HP100_REG_VG_LAN_CFG_2
 
- HP100_REPEATER
 
- HP100_RESET_HB
 
- HP100_RESET_LB
 
- HP100_RUNT_ERR
 
- HP100_RX_EARLY_INT
 
- HP100_RX_EN
 
- HP100_RX_ERROR
 
- HP100_RX_HDR
 
- HP100_RX_IDLE
 
- HP100_RX_PACKET
 
- HP100_RX_PDA_ZERO
 
- HP100_RX_PDL_FILL_COMPL
 
- HP100_RX_PRI
 
- HP100_RX_TRIP_MASK
 
- HP100_R_ROL_ST
 
- HP100_SDF_ERR
 
- HP100_SET_HB
 
- HP100_SET_LB
 
- HP100_SIG_LEN
 
- HP100_SKEW_ERR
 
- HP100_SQU_ST
 
- HP100_STOP_EN
 
- HP100_SYMBOL_BAL_ERR
 
- HP100_TRI_INT
 
- HP100_TRN_DONE
 
- HP100_TRUNC_ERR
 
- HP100_TR_MODE
 
- HP100_TX_CMD
 
- HP100_TX_CNT_FLG
 
- HP100_TX_COMPLETE
 
- HP100_TX_DUALQ
 
- HP100_TX_EN
 
- HP100_TX_ERROR
 
- HP100_TX_IDLE
 
- HP100_TX_PDA_ZERO
 
- HP100_TX_SAME
 
- HP100_TX_SPACE_AVAIL
 
- HP100_USE_ISA
 
- HP100_VG_ALN_ERR
 
- HP100_VG_RESET
 
- HP100_VG_SEL
 
- HP100_XCVR_7213
 
- HP100_XCVR_82503
 
- HP100_XCVR_LXT901_10
 
- HP100_ZERO_WAIT_EN
 
- HP206C_CMD_ADC_CVT
 
- HP206C_CMD_ADC_CVT_CHNL_PT
 
- HP206C_CMD_ADC_CVT_CHNL_T
 
- HP206C_CMD_ADC_CVT_OSR_1024
 
- HP206C_CMD_ADC_CVT_OSR_128
 
- HP206C_CMD_ADC_CVT_OSR_2048
 
- HP206C_CMD_ADC_CVT_OSR_256
 
- HP206C_CMD_ADC_CVT_OSR_4096
 
- HP206C_CMD_ADC_CVT_OSR_512
 
- HP206C_CMD_READ_P
 
- HP206C_CMD_READ_REG
 
- HP206C_CMD_READ_T
 
- HP206C_CMD_SOFT_RST
 
- HP206C_CMD_WRITE_REG
 
- HP206C_DEV_RDY_WAIT_US
 
- HP206C_FLAG_CMPS_EN
 
- HP206C_FLAG_DEV_RDY
 
- HP206C_MAX_DEV_RDY_WAIT_COUNT
 
- HP206C_REG_INT_CFG
 
- HP206C_REG_INT_EN
 
- HP206C_REG_INT_SRC
 
- HP206C_REG_PARA
 
- HP300_BOOTI_VERSION
 
- HP300_LEDS
 
- HP300_TIMER_CLOCK_FREQ
 
- HP300_TIMER_CYCLES
 
- HP3DC
 
- HP4X_IDS
 
- HP680_BATTERY_AC_ON
 
- HP680_BATTERY_MAX
 
- HP680_BATTERY_MIN
 
- HP680_BTN_IRQ
 
- HP680_DEFAULT_INTENSITY
 
- HP680_HD64461_IRQ
 
- HP680_MAX_INTENSITY
 
- HP680_TS_ABS_X_MAX
 
- HP680_TS_ABS_X_MIN
 
- HP680_TS_ABS_Y_MAX
 
- HP680_TS_ABS_Y_MIN
 
- HP680_TS_IRQ
 
- HPAGE_16GB_SHIFT
 
- HPAGE_256MB_SHIFT
 
- HPAGE_2GB_SHIFT
 
- HPAGE_64K_SHIFT
 
- HPAGE_CACHE_INDEX_MASK
 
- HPAGE_MASK
 
- HPAGE_PMD_MASK
 
- HPAGE_PMD_NR
 
- HPAGE_PMD_ORDER
 
- HPAGE_PMD_SHIFT
 
- HPAGE_PMD_SIZE
 
- HPAGE_PUD_MASK
 
- HPAGE_PUD_SHIFT
 
- HPAGE_PUD_SIZE
 
- HPAGE_REGION_BASE
 
- HPAGE_RESV_MASK
 
- HPAGE_RESV_OWNER
 
- HPAGE_RESV_UNMAPPED
 
- HPAGE_SHIFT
 
- HPAGE_SHIFT_DEFAULT
 
- HPAGE_SIZE
 
- HPAPCI_BAUD_BASE
 
- HPBDMAC0_3
 
- HPBDMAC11_18
 
- HPBDMAC19_22
 
- HPBDMAC23_25_27_28
 
- HPBDMAC4_10
 
- HPBDMAC_M
 
- HPBITMODE_16
 
- HPBITMODE_8
 
- HPBLKSEL_0
 
- HPBLKSEL_1
 
- HPB_0
 
- HPB_1
 
- HPB_2
 
- HPC3_BESTAT_BLMASK
 
- HPC3_BESTAT_CTYPE
 
- HPC3_BESTAT_PIDMASK
 
- HPC3_BESTAT_PIDSHIFT
 
- HPC3_CHIP0_BASE
 
- HPC3_CHIP1_BASE
 
- HPC3_DMACFG_BURST_MASK
 
- HPC3_DMACFG_BURST_SHIFT
 
- HPC3_DMACFG_D3R_MASK
 
- HPC3_DMACFG_D3R_SHIFT
 
- HPC3_DMACFG_D3W_MASK
 
- HPC3_DMACFG_D3W_SHIFT
 
- HPC3_DMACFG_D4R_MASK
 
- HPC3_DMACFG_D4R_SHIFT
 
- HPC3_DMACFG_D4W_MASK
 
- HPC3_DMACFG_D4W_SHIFT
 
- HPC3_DMACFG_D5R_MASK
 
- HPC3_DMACFG_D5R_SHIFT
 
- HPC3_DMACFG_D5W_MASK
 
- HPC3_DMACFG_D5W_SHIFT
 
- HPC3_DMACFG_DRQLIVE
 
- HPC3_DMACFG_DS16
 
- HPC3_DMACFG_EVENHI
 
- HPC3_DMACFG_RTIME
 
- HPC3_EDCFG_D1
 
- HPC3_EDCFG_D2
 
- HPC3_EDCFG_D3
 
- HPC3_EDCFG_FEOP
 
- HPC3_EDCFG_FIRQ
 
- HPC3_EDCFG_FRXDC
 
- HPC3_EDCFG_PTO
 
- HPC3_EDCFG_WCTRL
 
- HPC3_EEPROM_CSEL
 
- HPC3_EEPROM_DATI
 
- HPC3_EEPROM_DATO
 
- HPC3_EEPROM_ECLK
 
- HPC3_EEPROM_EPROT
 
- HPC3_EPCFG_P1
 
- HPC3_EPCFG_P2
 
- HPC3_EPCFG_P3
 
- HPC3_EPCFG_TST
 
- HPC3_ERST_CLRIRQ
 
- HPC3_ERST_CRESET
 
- HPC3_ERST_LBACK
 
- HPC3_ERXBCD_BCNTMSK
 
- HPC3_ERXBCD_EOX
 
- HPC3_ERXBCD_XIE
 
- HPC3_ERXCTRL_ACTIVE
 
- HPC3_ERXCTRL_AMASK
 
- HPC3_ERXCTRL_ENDIAN
 
- HPC3_ERXCTRL_RBO
 
- HPC3_ERXCTRL_STAT50
 
- HPC3_ERXCTRL_STAT6
 
- HPC3_ERXCTRL_STAT7
 
- HPC3_ETXBCD_BCNTMSK
 
- HPC3_ETXBCD_EOP
 
- HPC3_ETXBCD_EOX
 
- HPC3_ETXBCD_ESAMP
 
- HPC3_ETXBCD_XIE
 
- HPC3_ETXCTRL_ACTIVE
 
- HPC3_ETXCTRL_AMASK
 
- HPC3_ETXCTRL_ENDIAN
 
- HPC3_ETXCTRL_STAT30
 
- HPC3_ETXCTRL_STAT4
 
- HPC3_ETXCTRL_STAT75
 
- HPC3_GIOMISC_DENDIAN
 
- HPC3_GIOMISC_ERTIME
 
- HPC3_ISTAT_PBIMASK
 
- HPC3_ISTAT_SC0MASK
 
- HPC3_ISTAT_SC1MASK
 
- HPC3_PDMACTRL_ACT
 
- HPC3_PDMACTRL_FB
 
- HPC3_PDMACTRL_FE
 
- HPC3_PDMACTRL_FLSH
 
- HPC3_PDMACTRL_HW
 
- HPC3_PDMACTRL_INT
 
- HPC3_PDMACTRL_ISACT
 
- HPC3_PDMACTRL_LD
 
- HPC3_PDMACTRL_RCV
 
- HPC3_PDMACTRL_RT
 
- HPC3_PDMACTRL_SEL
 
- HPC3_PIOCFG_DS16
 
- HPC3_PIOCFG_EVENHI
 
- HPC3_PIOCFG_P2R_MASK
 
- HPC3_PIOCFG_P2R_SHIFT
 
- HPC3_PIOCFG_P2W_MASK
 
- HPC3_PIOCFG_P2W_SHIFT
 
- HPC3_PIOCFG_P3R_MASK
 
- HPC3_PIOCFG_P3R_SHIFT
 
- HPC3_PIOCFG_P3W_MASK
 
- HPC3_PIOCFG_P3W_SHIFT
 
- HPC3_PIOCFG_P4R_MASK
 
- HPC3_PIOCFG_P4R_SHIFT
 
- HPC3_PIOCFG_P4W_MASK
 
- HPC3_PIOCFG_P4W_SHIFT
 
- HPC3_PROM_STAT
 
- HPC3_PROM_SWAP
 
- HPC3_PROM_WENAB
 
- HPC3_SBCD_BCNTMSK
 
- HPC3_SBCD_EOX
 
- HPC3_SBCD_XIE
 
- HPC3_SCTRL_ACTIVE
 
- HPC3_SCTRL_AMASK
 
- HPC3_SCTRL_CRESET
 
- HPC3_SCTRL_DIR
 
- HPC3_SCTRL_ENDIAN
 
- HPC3_SCTRL_FLUSH
 
- HPC3_SCTRL_IRQ
 
- HPC3_SCTRL_PERR
 
- HPC3_SDCFG_D1
 
- HPC3_SDCFG_D2
 
- HPC3_SDCFG_D3
 
- HPC3_SDCFG_EPAR
 
- HPC3_SDCFG_ERLY
 
- HPC3_SDCFG_HCLK
 
- HPC3_SDCFG_HW
 
- HPC3_SDCFG_HWAT
 
- HPC3_SDCFG_POLL
 
- HPC3_SDCFG_SWAP
 
- HPC3_SPCFG_EPAR
 
- HPC3_SPCFG_FUJI
 
- HPC3_SPCFG_HW
 
- HPC3_SPCFG_P1
 
- HPC3_SPCFG_P2R
 
- HPC3_SPCFG_P2W
 
- HPC3_SPCFG_P3
 
- HPC3_SPCFG_SWAP
 
- HPCDMA_BCNT
 
- HPCDMA_EIPC
 
- HPCDMA_EOR
 
- HPCDMA_EORP
 
- HPCDMA_EOX
 
- HPCDMA_EOXP
 
- HPCDMA_ETXD
 
- HPCDMA_OWN
 
- HPCDMA_XIE
 
- HPCDMA_XIU
 
- HPCNTENR
 
- HPCR
 
- HPCVR_HC
 
- HPC_ALLSLOT_OFF
 
- HPC_ALLSLOT_ON
 
- HPC_BUS_100PCIXMODE
 
- HPC_BUS_133PCIXMODE
 
- HPC_BUS_33CONVMODE
 
- HPC_BUS_66CONVMODE
 
- HPC_BUS_66PCIXMODE
 
- HPC_CTLR_CLEARIRQ
 
- HPC_CTLR_DISABLEIRQ
 
- HPC_CTLR_ENABLEIRQ
 
- HPC_CTLR_FINISHED
 
- HPC_CTLR_FINISHED_NO
 
- HPC_CTLR_FINISHED_YES
 
- HPC_CTLR_IRQSTEER
 
- HPC_CTLR_IRQ_PENDG
 
- HPC_CTLR_IRQ_ROUTG
 
- HPC_CTLR_RESET
 
- HPC_CTLR_RESULE2
 
- HPC_CTLR_RESULT0
 
- HPC_CTLR_RESULT1
 
- HPC_CTLR_RESULT3
 
- HPC_CTLR_RESULT_FAILED
 
- HPC_CTLR_RESULT_NORESP
 
- HPC_CTLR_RESULT_RSVD
 
- HPC_CTLR_RESULT_SUCCESS
 
- HPC_CTLR_WORKING
 
- HPC_CTLR_WORKING_NO
 
- HPC_CTLR_WORKING_TOUT
 
- HPC_CTLR_WORKING_YES
 
- HPC_DEVICE_ID
 
- HPC_DMA_SIZE
 
- HPC_ERROR
 
- HPC_GETACCESS_TIMEOUT
 
- HPC_I2CSTATUS_CHECK
 
- HPC_PCI_OFFSET
 
- HPC_SLOT_ATTN
 
- HPC_SLOT_ATTNOFF
 
- HPC_SLOT_ATTNON
 
- HPC_SLOT_ATTN_BLINK
 
- HPC_SLOT_ATTN_BLINK_OFF
 
- HPC_SLOT_ATTN_BLINK_ON
 
- HPC_SLOT_ATTN_OFF
 
- HPC_SLOT_ATTN_ON
 
- HPC_SLOT_BLINKLED
 
- HPC_SLOT_BLINK_ATTN
 
- HPC_SLOT_BUS_MODE
 
- HPC_SLOT_BUS_MODE_MISM
 
- HPC_SLOT_BUS_MODE_OK
 
- HPC_SLOT_BUS_SPEED
 
- HPC_SLOT_BUS_SPEED_MISM
 
- HPC_SLOT_BUS_SPEED_OK
 
- HPC_SLOT_CONNECT
 
- HPC_SLOT_CONNECTED
 
- HPC_SLOT_DISCONNECTED
 
- HPC_SLOT_EMPTY
 
- HPC_SLOT_LATCH
 
- HPC_SLOT_LATCH_CLOSED
 
- HPC_SLOT_LATCH_OPEN
 
- HPC_SLOT_OFF
 
- HPC_SLOT_ON
 
- HPC_SLOT_PCIX
 
- HPC_SLOT_PCIX_NO
 
- HPC_SLOT_PCIX_YES
 
- HPC_SLOT_POWER
 
- HPC_SLOT_POWER_OFF
 
- HPC_SLOT_POWER_ON
 
- HPC_SLOT_PRSNT1
 
- HPC_SLOT_PRSNT2
 
- HPC_SLOT_PRSNT_15
 
- HPC_SLOT_PRSNT_25
 
- HPC_SLOT_PRSNT_7
 
- HPC_SLOT_PWRGD
 
- HPC_SLOT_PWRGD_FAULT_NONE
 
- HPC_SLOT_PWRGD_GOOD
 
- HPC_SLOT_RSRVD1
 
- HPC_SLOT_RSRVD2
 
- HPC_SLOT_RSRVD3
 
- HPC_SLOT_SPEED1
 
- HPC_SLOT_SPEED2
 
- HPC_SLOT_SPEED_133
 
- HPC_SLOT_SPEED_33
 
- HPC_SLOT_SPEED_66
 
- HPC_SUBSYSTEM_ID
 
- HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD0_REGISTER_OFFSET
 
- HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD1_REGISTER_OFFSET
 
- HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD2_REGISTER_OFFSET
 
- HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD3_REGISTER_OFFSET
 
- HPD48
 
- HPD48_MARK
 
- HPD49
 
- HPD49_MARK
 
- HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD4_REGISTER_OFFSET
 
- HPD50
 
- HPD50_MARK
 
- HPD51
 
- HPD51_MARK
 
- HPD52
 
- HPD52_MARK
 
- HPD53
 
- HPD53_MARK
 
- HPD54
 
- HPD54_MARK
 
- HPD55
 
- HPD55_MARK
 
- HPD56
 
- HPD56_MARK
 
- HPD57
 
- HPD57_MARK
 
- HPD58
 
- HPD58_MARK
 
- HPD59
 
- HPD59_MARK
 
- HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK
 
- HPD5_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT
 
- HPD5_DC_HPD_CONTROL__DC_HPD_EN_MASK
 
- HPD5_DC_HPD_CONTROL__DC_HPD_EN__SHIFT
 
- HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK
 
- HPD5_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK
 
- HPD5_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK
 
- HPD5_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK
 
- HPD5_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT
 
- HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK
 
- HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT
 
- HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK
 
- HPD5_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT
 
- HPD5_REGISTER_OFFSET
 
- HPD60
 
- HPD60_MARK
 
- HPD61
 
- HPD61_MARK
 
- HPD62
 
- HPD62_MARK
 
- HPD63
 
- HPD63_MARK
 
- HPDCA_BAUD_BASE
 
- HPDET_DEBOUNCE
 
- HPDInterruptService
 
- HPDQM4
 
- HPDQM4_MARK
 
- HPDQM5
 
- HPDQM5_MARK
 
- HPDQM6
 
- HPDQM6_MARK
 
- HPDQM7
 
- HPDQM7_MARK
 
- HPDSPRESET_OFF
 
- HPDSPRESET_ON
 
- HPD_AUTO_HPD_ALL_CH
 
- HPD_AUTO_HPD_F3TECH
 
- HPD_AUTO_HPD_NEW_CH
 
- HPD_AUTO_HPD_PRV_CH
 
- HPD_AUTO_HPD_UNSEL
 
- HPD_AUTO_HP_OTHER
 
- HPD_AUTO_READ_EDID
 
- HPD_CHANGE_INT
 
- HPD_CHANGE_INT_MASK
 
- HPD_CHECK_INTERVAL
 
- HPD_CRT
 
- HPD_CTL
 
- HPD_CTRL
 
- HPD_DISABLE
 
- HPD_DISABLED
 
- HPD_ENABLED
 
- HPD_EVENT_DET
 
- HPD_EVENT_MASK
 
- HPD_FILTER_TIMER
 
- HPD_GPIO_INDEX
 
- HPD_GPIO_REG_LIST
 
- HPD_GPIO_REG_LIST_ENTRY
 
- HPD_HIGH_BP
 
- HPD_HIGH_OTHER
 
- HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK
 
- HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT
 
- HPD_INT_CONTROL_ACK
 
- HPD_INT_CONTROL_ACK_0
 
- HPD_INT_CONTROL_ACK_1
 
- HPD_INT_CONTROL_GEN_INT_ON_CON
 
- HPD_INT_CONTROL_GEN_INT_ON_DISCON
 
- HPD_INT_CONTROL_POLARITY
 
- HPD_INT_CONTROL_RX_INT_ACK
 
- HPD_INT_CONTROL_RX_INT_ACK_0
 
- HPD_INT_CONTROL_RX_INT_ACK_1
 
- HPD_IRQ_DET_MAX_TIMER
 
- HPD_IRQ_DET_MIN_TIMER
 
- HPD_LOST
 
- HPD_LOW_BP
 
- HPD_LOW_OTHER
 
- HPD_MAN_CTRL_5VEN
 
- HPD_MAN_CTRL_HPD_A
 
- HPD_MAN_CTRL_HPD_B
 
- HPD_MAN_CTRL_HPD_PULSE
 
- HPD_MARK_DISABLED
 
- HPD_MASK_SH_LIST
 
- HPD_MASK_SH_LIST_DCE8
 
- HPD_NONE
 
- HPD_NUM_PINS
 
- HPD_PORT_A
 
- HPD_PORT_B
 
- HPD_PORT_C
 
- HPD_PORT_D
 
- HPD_PORT_E
 
- HPD_PORT_F
 
- HPD_PORT_G
 
- HPD_PORT_H
 
- HPD_PORT_I
 
- HPD_POWER_BP_HIGH
 
- HPD_POWER_BP_LOW
 
- HPD_POWER_BP_MASK
 
- HPD_POWER_BP_SHIFT
 
- HPD_POWER_EDID_ONLY
 
- HPD_PULSE
 
- HPD_REG
 
- HPD_REG_LIST
 
- HPD_REG_LIST_DCE8
 
- HPD_REG_READ
 
- HPD_REG_UPDATE
 
- HPD_REG_UPDATE_N
 
- HPD_RETRY_DELAY
 
- HPD_SDVO_B
 
- HPD_SDVO_C
 
- HPD_SOURCEID1
 
- HPD_SOURCEID2
 
- HPD_SOURCEID3
 
- HPD_SOURCEID4
 
- HPD_SOURCEID5
 
- HPD_SOURCEID6
 
- HPD_SOURCEID_COUNT
 
- HPD_SOURCEID_UNKNOWN
 
- HPD_STABLE_TIMER
 
- HPD_STATUS
 
- HPD_STORM_DEFAULT_THRESHOLD
 
- HPD_STORM_DETECT_PERIOD
 
- HPD_STORM_REENABLE_DELAY
 
- HPD_TV
 
- HPD_UNPLGED_DET_MIN_TIMER
 
- HPEE_DMA_CHANNEL_MASK
 
- HPEE_DMA_MAX_ENT
 
- HPEE_DMA_MORE
 
- HPEE_DMA_SHARED
 
- HPEE_DMA_SIZE_BYTE
 
- HPEE_DMA_SIZE_DWORD
 
- HPEE_DMA_SIZE_MASK
 
- HPEE_DMA_SIZE_WORD
 
- HPEE_DMA_TIMING_ISA
 
- HPEE_DMA_TIMING_MASK
 
- HPEE_DMA_TIMING_TYPEA
 
- HPEE_DMA_TIMING_TYPEB
 
- HPEE_DMA_TIMING_TYPEC
 
- HPEE_FLAG_BOARD_IS_ISA
 
- HPEE_FUNCTION_INFO_CFG_FREE_FORM
 
- HPEE_FUNCTION_INFO_F_DISABLED
 
- HPEE_FUNCTION_INFO_HAVE_DMA
 
- HPEE_FUNCTION_INFO_HAVE_FUNCTION
 
- HPEE_FUNCTION_INFO_HAVE_IRQ
 
- HPEE_FUNCTION_INFO_HAVE_MEMORY
 
- HPEE_FUNCTION_INFO_HAVE_PORT
 
- HPEE_FUNCTION_INFO_HAVE_PORT_INIT
 
- HPEE_FUNCTION_INFO_HAVE_TYPE
 
- HPEE_IRQ_CHANNEL_MASK
 
- HPEE_IRQ_MAX_ENT
 
- HPEE_IRQ_MORE
 
- HPEE_IRQ_TRIG_LEVEL
 
- HPEE_MAX_LENGTH
 
- HPEE_MEMORY_CACHABLE
 
- HPEE_MEMORY_DECODE_20BITS
 
- HPEE_MEMORY_DECODE_24BITS
 
- HPEE_MEMORY_DECODE_32BITS
 
- HPEE_MEMORY_DECODE_MASK
 
- HPEE_MEMORY_MAX_ENT
 
- HPEE_MEMORY_MORE
 
- HPEE_MEMORY_SHARED
 
- HPEE_MEMORY_TYPE_EXP
 
- HPEE_MEMORY_TYPE_MASK
 
- HPEE_MEMORY_TYPE_OTH
 
- HPEE_MEMORY_TYPE_SYS
 
- HPEE_MEMORY_TYPE_VIR
 
- HPEE_MEMORY_WIDTH_BYTE
 
- HPEE_MEMORY_WIDTH_DWORD
 
- HPEE_MEMORY_WIDTH_MASK
 
- HPEE_MEMORY_WIDTH_WORD
 
- HPEE_MEMORY_WRITABLE
 
- HPEE_PORT_INIT_MASK
 
- HPEE_PORT_INIT_MAX_LEN
 
- HPEE_PORT_INIT_MORE
 
- HPEE_PORT_INIT_WIDTH_BYTE
 
- HPEE_PORT_INIT_WIDTH_DWORD
 
- HPEE_PORT_INIT_WIDTH_MASK
 
- HPEE_PORT_INIT_WIDTH_WORD
 
- HPEE_PORT_MAX_ENT
 
- HPEE_PORT_MORE
 
- HPEE_PORT_SHARED
 
- HPEE_PORT_SIZE_MASK
 
- HPEE_SELECTION_MAX_ENT
 
- HPEE_SLOT_FEATURES_CFG_INCOMPLETE
 
- HPEE_SLOT_FEATURES_ENABLE
 
- HPEE_SLOT_FEATURES_IOCHK
 
- HPEE_SLOT_INFO
 
- HPEE_SLOT_INFO_DUPLICATE
 
- HPEE_SLOT_INFO_EMBEDDED
 
- HPEE_SLOT_INFO_NO_READID
 
- HPEE_SLOT_INFO_VIRTUAL
 
- HPEE_TYPE_MAX_LEN
 
- HPEPR
 
- HPET_ADDR
 
- HPET_CFG
 
- HPET_CFG_ENABLE
 
- HPET_CFG_LEGACY
 
- HPET_COMPARE_VAL
 
- HPET_COUNTER
 
- HPET_COUNTER_CLK_PERIOD_MASK
 
- HPET_COUNTER_CLK_PERIOD_SHIFT
 
- HPET_COUNTER_SIZE_MASK
 
- HPET_DEV_NAME
 
- HPET_DPI
 
- HPET_DRIFT
 
- HPET_ENABLE_CNF_MASK
 
- HPET_EPI
 
- HPET_FREQ
 
- HPET_ID
 
- HPET_ID_64BIT
 
- HPET_ID_LEGSUP
 
- HPET_ID_NUMBER
 
- HPET_ID_NUMBER_SHIFT
 
- HPET_ID_REV
 
- HPET_ID_VENDOR
 
- HPET_ID_VENDOR_SHIFT
 
- HPET_IE
 
- HPET_IE_OFF
 
- HPET_IE_ON
 
- HPET_INFO
 
- HPET_INFO_PERIODIC
 
- HPET_IRQFREQ
 
- HPET_LEGACY_8254
 
- HPET_LEGACY_RTC
 
- HPET_LEG_RT_CAP_MASK
 
- HPET_LEG_RT_CNF_MASK
 
- HPET_MASK
 
- HPET_MAX_IRQ
 
- HPET_MAX_PERIOD
 
- HPET_MAX_TIMERS
 
- HPET_MINOR
 
- HPET_MIN_CYCLES
 
- HPET_MIN_PERIOD
 
- HPET_MIN_PROG_DELTA
 
- HPET_MMAP_SIZE
 
- HPET_MMIO_ADDR
 
- HPET_MODE_CLOCKEVT
 
- HPET_MODE_DEVICE
 
- HPET_MODE_LEGACY
 
- HPET_MODE_UNUSED
 
- HPET_NUM_TIM_CAP_MASK
 
- HPET_NUM_TIM_CAP_SHIFT
 
- HPET_OPEN
 
- HPET_PERIOD
 
- HPET_PERIODIC
 
- HPET_RANGE_SIZE
 
- HPET_RESOURCE_NAME_SIZE
 
- HPET_SHARED_IRQ
 
- HPET_STATUS
 
- HPET_T0_CFG
 
- HPET_T0_CMP
 
- HPET_T0_IRQ
 
- HPET_T0_IRS
 
- HPET_T0_ROUTE
 
- HPET_T1_CFG
 
- HPET_T1_CMP
 
- HPET_T1_IRS
 
- HPET_T1_ROUTE
 
- HPET_T2_CFG
 
- HPET_T2_CMP
 
- HPET_T2_ROUTE
 
- HPET_T3_IRS
 
- HPET_TN_32BIT
 
- HPET_TN_64BIT_CAP
 
- HPET_TN_ENABLE
 
- HPET_TN_FSB
 
- HPET_TN_FSB_CAP
 
- HPET_TN_LEVEL
 
- HPET_TN_PERIODIC
 
- HPET_TN_PERIODIC_CAP
 
- HPET_TN_ROUTE
 
- HPET_TN_ROUTE_SHIFT
 
- HPET_TN_SETVAL
 
- HPET_Tn_CFG
 
- HPET_Tn_CMP
 
- HPET_Tn_ROUTE
 
- HPET_USER_FREQ
 
- HPET_VENDOR_ID_MASK
 
- HPET_VENDOR_ID_SHIFT
 
- HPFAR
 
- HPFAR_MASK
 
- HPFB_DHLSB
 
- HPFB_DHMSB
 
- HPFB_DWLSB
 
- HPFB_DWMSB
 
- HPFB_FBHLSB
 
- HPFB_FBHMSB
 
- HPFB_FBOLSB
 
- HPFB_FBOMSB
 
- HPFB_FBWLSB
 
- HPFB_FBWMSB
 
- HPFB_NUMPLANES
 
- HPFS_SUPER_MAGIC
 
- HPG_WINTV
 
- HPG_WINTV_LIVE_PAL_BG
 
- HPG_WINTV_LIVE_PRO_NTSC_MN
 
- HPG_WINTV_NTSC_FM
 
- HPG_WINTV_NTSC_MN
 
- HPG_WINTV_PAL_BG
 
- HPG_WINTV_PAL_BG_FM
 
- HPG_WINTV_PAL_D_K
 
- HPG_WINTV_PAL_D_K_FM
 
- HPG_WINTV_PAL_I
 
- HPG_WINTV_PAL_I_FM
 
- HPG_WINTV_PAL_SECAM_L
 
- HPG_WINTV_PRO_NTSC_MN
 
- HPG_WINTV_PRO_NTSC_MN_FM
 
- HPG_WINTV_PRO_NTSC_MN_FM_V2
 
- HPG_WINTV_PRO_NTSC_MN_V2
 
- HPG_WINTV_PRO_NTSC_MN_V3
 
- HPG_WINTV_PRO_PAL
 
- HPG_WINTV_PRO_PAL_BG
 
- HPG_WINTV_PRO_PAL_BG_D_K
 
- HPG_WINTV_PRO_PAL_BG_FM
 
- HPG_WINTV_PRO_PAL_BG_V2
 
- HPG_WINTV_PRO_PAL_D_K
 
- HPG_WINTV_PRO_PAL_D_K_FM
 
- HPG_WINTV_PRO_PAL_FM
 
- HPG_WINTV_PRO_PAL_I
 
- HPG_WINTV_PRO_PAL_I_D_K
 
- HPG_WINTV_PRO_PAL_I_FM
 
- HPG_WINTV_PRO_PAL_SECAM
 
- HPG_WINTV_PRO_PAL_SECAM_L
 
- HPG_WINTV_PRO_PAL_SECAM_V2
 
- HPG_WINTV_PRO_TEMIC_PAL_BG_FM
 
- HPG_WINTV_PRO_TEMIC_PAL_FM
 
- HPHW_A_DIRECT
 
- HPHW_A_DMA
 
- HPHW_BA
 
- HPHW_BCPORT
 
- HPHW_BRIDGE
 
- HPHW_B_DMA
 
- HPHW_CIO
 
- HPHW_CONSOLE
 
- HPHW_FABRIC
 
- HPHW_FAULTY
 
- HPHW_FIO
 
- HPHW_IOA
 
- HPHW_MC
 
- HPHW_MEMORY
 
- HPHW_NPROC
 
- HPHW_OBSOLETE
 
- HPHW_OTHER
 
- HPI6000_ERROR_BASE
 
- HPI6000_ERROR_CONTROL_CACHE_ADDRLEN
 
- HPI6000_ERROR_CONTROL_CACHE_FLUSH
 
- HPI6000_ERROR_CONTROL_CACHE_PARAMS
 
- HPI6000_ERROR_CONTROL_CACHE_READ
 
- HPI6000_ERROR_GET_DATA_ACK
 
- HPI6000_ERROR_GET_DATA_CMD
 
- HPI6000_ERROR_GET_DATA_IDLECMD
 
- HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT
 
- HPI6000_ERROR_GET_DATA_READ
 
- HPI6000_ERROR_INIT_DSPHPI
 
- HPI6000_ERROR_INIT_DSPINTMEM
 
- HPI6000_ERROR_INIT_NOACK
 
- HPI6000_ERROR_INIT_PCI2040
 
- HPI6000_ERROR_INIT_PLDTEST1
 
- HPI6000_ERROR_INIT_PLDTEST2
 
- HPI6000_ERROR_INIT_SDRAM1
 
- HPI6000_ERROR_INIT_SDRAM2
 
- HPI6000_ERROR_INIT_VERIFY
 
- HPI6000_ERROR_MSG_GET_ADR
 
- HPI6000_ERROR_MSG_RESP_BLOCKREAD32
 
- HPI6000_ERROR_MSG_RESP_BLOCKWRITE32
 
- HPI6000_ERROR_MSG_RESP_GETRESPCMD
 
- HPI6000_ERROR_MSG_RESP_GET_RESP_ACK
 
- HPI6000_ERROR_MSG_RESP_IDLECMD
 
- HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT
 
- HPI6000_ERROR_RESP_GET_ADR
 
- HPI6000_ERROR_RESP_GET_LEN
 
- HPI6000_ERROR_SEND_DATA_ACK
 
- HPI6000_ERROR_SEND_DATA_ADR
 
- HPI6000_ERROR_SEND_DATA_CMD
 
- HPI6000_ERROR_SEND_DATA_IDLECMD
 
- HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT
 
- HPI6000_ERROR_SEND_DATA_TIMEOUT
 
- HPI6000_ERROR_SEND_DATA_WRITE
 
- HPI6000_ERROR_UNHANDLED_SUBSYS_ID
 
- HPI6205_ERROR_6205_DSPPAGE
 
- HPI6205_ERROR_6205_EEPROM
 
- HPI6205_ERROR_6205_INIT_FAILED
 
- HPI6205_ERROR_6205_NO_IRQ
 
- HPI6205_ERROR_6205_REG
 
- HPI6205_ERROR_BASE
 
- HPI6205_ERROR_C6713_HPIA
 
- HPI6205_ERROR_C6713_HPIC
 
- HPI6205_ERROR_C6713_PLL
 
- HPI6205_ERROR_DSP_EMIF1
 
- HPI6205_ERROR_DSP_EMIF2
 
- HPI6205_ERROR_DSP_EMIF3
 
- HPI6205_ERROR_DSP_EMIF4
 
- HPI6205_ERROR_DSP_EXTMEM
 
- HPI6205_ERROR_DSP_INTMEM
 
- HPI6205_ERROR_DSP_PLD
 
- HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT
 
- HPI6205_ERROR_MSG_RESP_TIMEOUT
 
- HPI6205_MAX_FILES_TO_LOAD
 
- HPI6205_SIZEOF_DATA
 
- HPI6205_TIMEOUT
 
- HPIAH_ADDR
 
- HPIAL_ADDR
 
- HPICH_ADDR
 
- HPICL_ADDR
 
- HPICMN_PAD_OFS_AND_SIZE
 
- HPICR_HF0
 
- HPICR_HF1
 
- HPICR_HM0
 
- HPICR_HM1
 
- HPICR_INIT
 
- HPICR_RREQ
 
- HPICR_TREQ
 
- HPIDH_ADDR
 
- HPIDIH_ADDR
 
- HPIDIL_ADDR
 
- HPIDL_ADDR
 
- HPID_KVM
 
- HPID_VSIE
 
- HPIMSGX_ALLADAPTERS
 
- HPIMSGX__cleanup
 
- HPIMSGX__init
 
- HPIMSGX__reset
 
- HPINET_ASI_DATA_SIZE
 
- HPINET_ASI_HDR_SIZE
 
- HPINET_ETHERNET_DATA_SIZE
 
- HPINET_IP_DATA_SIZE
 
- HPINET_IP_HDR_SIZE
 
- HPINET_UDP_DATA_SIZE
 
- HPINET_UDP_HDR_SIZE
 
- HPINTENR
 
- HPIO_210
 
- HPIO_220
 
- HPIO_230
 
- HPIO_240
 
- HPIO_250
 
- HPIO_260
 
- HPIO_290
 
- HPIO_3E0
 
- HPIRQ_10
 
- HPIRQ_11
 
- HPIRQ_12
 
- HPIRQ_15
 
- HPIRQ_5
 
- HPIRQ_7
 
- HPIRQ_9
 
- HPIRQ_NONE
 
- HPISR_DMA
 
- HPISR_HF2
 
- HPISR_HF3
 
- HPISR_HREQ
 
- HPISR_RXDF
 
- HPISR_TRDY
 
- HPISR_TXDE
 
- HPI_6000
 
- HPI_6205
 
- HPI_ADAPTER_ASI
 
- HPI_ADAPTER_CLOSE
 
- HPI_ADAPTER_DEBUG_READ
 
- HPI_ADAPTER_DELETE
 
- HPI_ADAPTER_ENABLE_CAPABILITY
 
- HPI_ADAPTER_END_FLASH
 
- HPI_ADAPTER_ENUM_PROPERTY
 
- HPI_ADAPTER_FAMILY_ASI
 
- HPI_ADAPTER_FAMILY_MASK
 
- HPI_ADAPTER_FILESTORE_DELETE_ALL
 
- HPI_ADAPTER_FIND_OBJECT
 
- HPI_ADAPTER_FUNCTION_COUNT
 
- HPI_ADAPTER_GET_ASSERT
 
- HPI_ADAPTER_GET_INFO
 
- HPI_ADAPTER_GET_MODE
 
- HPI_ADAPTER_GET_PROPERTY
 
- HPI_ADAPTER_INDEX_INVALID
 
- HPI_ADAPTER_IRQ_CALLBACK
 
- HPI_ADAPTER_IRQ_QUERY_AND_CLEAR
 
- HPI_ADAPTER_MODES
 
- HPI_ADAPTER_MODE_1
 
- HPI_ADAPTER_MODE_12OSTREAM
 
- HPI_ADAPTER_MODE_16OSTREAM
 
- HPI_ADAPTER_MODE_1OSTREAM
 
- HPI_ADAPTER_MODE_2
 
- HPI_ADAPTER_MODE_3
 
- HPI_ADAPTER_MODE_4OSTREAM
 
- HPI_ADAPTER_MODE_6OSTREAM
 
- HPI_ADAPTER_MODE_8OSTREAM
 
- HPI_ADAPTER_MODE_9OSTREAM
 
- HPI_ADAPTER_MODE_CMDS
 
- HPI_ADAPTER_MODE_LOW_LATENCY
 
- HPI_ADAPTER_MODE_MONO
 
- HPI_ADAPTER_MODE_MULTICHANNEL
 
- HPI_ADAPTER_MODE_QUERY
 
- HPI_ADAPTER_MODE_SET
 
- HPI_ADAPTER_MODULE_INFO
 
- HPI_ADAPTER_OPEN
 
- HPI_ADAPTER_PROGRAM_FLASH
 
- HPI_ADAPTER_PROPERTIES
 
- HPI_ADAPTER_PROPERTY_BUFFER_UPDATE_COUNT
 
- HPI_ADAPTER_PROPERTY_CAPS1
 
- HPI_ADAPTER_PROPERTY_CAPS2
 
- HPI_ADAPTER_PROPERTY_CURCHANNELS
 
- HPI_ADAPTER_PROPERTY_ENABLE_SSX2
 
- HPI_ADAPTER_PROPERTY_ERRATA_1
 
- HPI_ADAPTER_PROPERTY_EXTENDED_ADAPTER_TYPE
 
- HPI_ADAPTER_PROPERTY_FIRMWARE_ID
 
- HPI_ADAPTER_PROPERTY_GRANULARITY
 
- HPI_ADAPTER_PROPERTY_GROUPING
 
- HPI_ADAPTER_PROPERTY_INTERVAL
 
- HPI_ADAPTER_PROPERTY_IP_ADDRESS
 
- HPI_ADAPTER_PROPERTY_IRQ_RATE
 
- HPI_ADAPTER_PROPERTY_LATENCY
 
- HPI_ADAPTER_PROPERTY_LOGTABBEG
 
- HPI_ADAPTER_PROPERTY_LOGTABLEN
 
- HPI_ADAPTER_PROPERTY_MAC_ADDRESS_LSB
 
- HPI_ADAPTER_PROPERTY_MAC_ADDRESS_MSB
 
- HPI_ADAPTER_PROPERTY_READONLYBASE
 
- HPI_ADAPTER_PROPERTY_SOFTWARE_VERSION
 
- HPI_ADAPTER_PROPERTY_SSX2_SETTING
 
- HPI_ADAPTER_PROPERTY_SUPPORTS_FW_UPDATE
 
- HPI_ADAPTER_PROPERTY_SUPPORTS_IRQ
 
- HPI_ADAPTER_PROPERTY_SUPPORTS_SSX2
 
- HPI_ADAPTER_PROPERTY_SYNC_HEADER_CONNECTIONS
 
- HPI_ADAPTER_QUERY_FLASH
 
- HPI_ADAPTER_READ_FLASH
 
- HPI_ADAPTER_SELFTEST
 
- HPI_ADAPTER_SET_MODE
 
- HPI_ADAPTER_SET_PROPERTY
 
- HPI_ADAPTER_START_FLASH
 
- HPI_ADAPTER_TEST_ASSERT
 
- HPI_ADDR
 
- HPI_ADDR_INIT_BUFFER
 
- HPI_ADDR_INTR_RET_DATA
 
- HPI_ADDR_INTR_RET_VALUE
 
- HPI_ADDR_INTR_STATUS
 
- HPI_ADDR_INTR_WR_INDEX
 
- HPI_ADDR_INTR_WR_PARAM
 
- HPI_ADDR_VIDEO_BUFFER
 
- HPI_AESEBURX_CHANNELSTATUS
 
- HPI_AESEBURX_ERRORSTATUS
 
- HPI_AESEBURX_FORMAT
 
- HPI_AESEBURX_SAMPLERATE
 
- HPI_AESEBURX_USERDATA
 
- HPI_AESEBUTX_CHANNELSTATUS
 
- HPI_AESEBUTX_FORMAT
 
- HPI_AESEBUTX_SAMPLERATE
 
- HPI_AESEBUTX_USERDATA
 
- HPI_AESEBU_ERRORS
 
- HPI_AESEBU_ERROR_BIPHASE_VIOLATION
 
- HPI_AESEBU_ERROR_CRC
 
- HPI_AESEBU_ERROR_NOT_LOCKED
 
- HPI_AESEBU_ERROR_PARITY_ERROR
 
- HPI_AESEBU_ERROR_POOR_QUALITY
 
- HPI_AESEBU_ERROR_VALIDITY
 
- HPI_AESEBU_FORMATS
 
- HPI_AESEBU_FORMAT_AESEBU
 
- HPI_AESEBU_FORMAT_SPDIF
 
- HPI_ALIST_LOCKING
 
- HPI_ASYNCEVENT_CLOSE
 
- HPI_ASYNCEVENT_FUNCTION_COUNT
 
- HPI_ASYNCEVENT_GET
 
- HPI_ASYNCEVENT_GETCOUNT
 
- HPI_ASYNCEVENT_OPEN
 
- HPI_ASYNCEVENT_SENDEVENTS
 
- HPI_ASYNCEVENT_WAIT
 
- HPI_ASYNC_EVENT_GPIO
 
- HPI_ASYNC_EVENT_SILENCE
 
- HPI_ASYNC_EVENT_TONE
 
- HPI_BITMASK_ALL_CHANNELS
 
- HPI_BITSTREAM_ACTIVITY
 
- HPI_BITSTREAM_CLOCK_EDGE
 
- HPI_BITSTREAM_CLOCK_SOURCE
 
- HPI_BITSTREAM_DATA_POLARITY
 
- HPI_BUFFER_CMDS
 
- HPI_BUFFER_CMD_EXTERNAL
 
- HPI_BUFFER_CMD_INTERNAL_ALLOC
 
- HPI_BUFFER_CMD_INTERNAL_FREE
 
- HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER
 
- HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER
 
- HPI_BUILD_DEBUG
 
- HPI_BUILD_KERNEL_MODE
 
- HPI_BUS_ISAPNP
 
- HPI_BUS_NET
 
- HPI_BUS_PCI
 
- HPI_BUS_USB
 
- HPI_CACHE_INVALID_SHORT
 
- HPI_CACHE_INVALID_UINT16
 
- HPI_CAPABILITY_MAX
 
- HPI_CAPABILITY_MPEG_LAYER3
 
- HPI_CAPABILITY_NONE
 
- HPI_CHANNEL_MODES
 
- HPI_CHANNEL_MODE_LAST
 
- HPI_CHANNEL_MODE_LEFT_TO_STEREO
 
- HPI_CHANNEL_MODE_MODE
 
- HPI_CHANNEL_MODE_NORMAL
 
- HPI_CHANNEL_MODE_RIGHT_TO_STEREO
 
- HPI_CHANNEL_MODE_STEREO_TO_LEFT
 
- HPI_CHANNEL_MODE_STEREO_TO_RIGHT
 
- HPI_CHANNEL_MODE_SWAP
 
- HPI_CLOCK_GET_TIME
 
- HPI_CLOCK_OPEN
 
- HPI_CLOCK_SET_TIME
 
- HPI_COBRANET_GET
 
- HPI_COBRANET_GET_PACKET
 
- HPI_COBRANET_GET_STATUS
 
- HPI_COBRANET_HMI_STATUS_RXPACKET
 
- HPI_COBRANET_HMI_STATUS_TXPACKET
 
- HPI_COBRANET_HMI_cobra_bridge
 
- HPI_COBRANET_HMI_cobra_bridge_rx_pkt_buf
 
- HPI_COBRANET_HMI_cobra_bridge_tx_pkt_buf
 
- HPI_COBRANET_HMI_cobra_if_phy_address
 
- HPI_COBRANET_HMI_cobra_if_table1
 
- HPI_COBRANET_HMI_cobra_ip_mon_currentIP
 
- HPI_COBRANET_HMI_cobra_ip_mon_staticIP
 
- HPI_COBRANET_HMI_cobra_protocolIP
 
- HPI_COBRANET_HMI_cobra_sys
 
- HPI_COBRANET_HMI_cobra_sys_contact
 
- HPI_COBRANET_HMI_cobra_sys_desc
 
- HPI_COBRANET_HMI_cobra_sys_location
 
- HPI_COBRANET_HMI_cobra_sys_name
 
- HPI_COBRANET_HMI_cobra_sys_objectID
 
- HPI_COBRANET_SEND_PACKET
 
- HPI_COBRANET_SET
 
- HPI_COMMON
 
- HPI_COMPANDER_ATTACK
 
- HPI_COMPANDER_DECAY
 
- HPI_COMPANDER_MAKEUPGAIN
 
- HPI_COMPANDER_PARAMS
 
- HPI_COMPANDER_RATIO
 
- HPI_COMPANDER_THRESHOLD
 
- HPI_CONTROLS
 
- HPI_CONTROL_AESEBURX
 
- HPI_CONTROL_AESEBUTX
 
- HPI_CONTROL_AESEBU_RECEIVER
 
- HPI_CONTROL_AESEBU_TRANSMITTER
 
- HPI_CONTROL_ATTRIBUTES
 
- HPI_CONTROL_BITSTREAM
 
- HPI_CONTROL_CHANNEL_MODE
 
- HPI_CONTROL_COBRANET
 
- HPI_CONTROL_COMPANDER
 
- HPI_CONTROL_CONNECTION
 
- HPI_CONTROL_EQUALIZER
 
- HPI_CONTROL_FUNCTION_COUNT
 
- HPI_CONTROL_GENERIC
 
- HPI_CONTROL_GET_INFO
 
- HPI_CONTROL_GET_STATE
 
- HPI_CONTROL_LAST_INDEX
 
- HPI_CONTROL_LEVEL
 
- HPI_CONTROL_METER
 
- HPI_CONTROL_MICROPHONE
 
- HPI_CONTROL_MULTIPLEXER
 
- HPI_CONTROL_MUTE
 
- HPI_CONTROL_PAD
 
- HPI_CONTROL_PARAMETRIC_EQ
 
- HPI_CONTROL_SAMPLECLOCK
 
- HPI_CONTROL_SET_STATE
 
- HPI_CONTROL_SILENCEDETECTOR
 
- HPI_CONTROL_SRC
 
- HPI_CONTROL_TONEDETECTOR
 
- HPI_CONTROL_TUNER
 
- HPI_CONTROL_UNIVERSAL
 
- HPI_CONTROL_VOLUME
 
- HPI_CONTROL_VOX
 
- HPI_CTL_ATTR
 
- HPI_CTL_ATTR_CONTROL
 
- HPI_CTL_ATTR_INDEX
 
- HPI_DATA
 
- HPI_DATA_WIDTH
 
- HPI_DEBUG_ASSERT
 
- HPI_DEBUG_DATA
 
- HPI_DEBUG_FLAG_DEBUG
 
- HPI_DEBUG_FLAG_ERROR
 
- HPI_DEBUG_FLAG_INFO
 
- HPI_DEBUG_FLAG_NOTICE
 
- HPI_DEBUG_FLAG_VERBOSE
 
- HPI_DEBUG_FLAG_WARNING
 
- HPI_DEBUG_LEVEL_DEBUG
 
- HPI_DEBUG_LEVEL_DEFAULT
 
- HPI_DEBUG_LEVEL_ERROR
 
- HPI_DEBUG_LEVEL_INFO
 
- HPI_DEBUG_LEVEL_NOTICE
 
- HPI_DEBUG_LEVEL_VERBOSE
 
- HPI_DEBUG_LEVEL_WARNING
 
- HPI_DEBUG_LOG
 
- HPI_DEBUG_MESSAGE
 
- HPI_DEBUG_RESPONSE
 
- HPI_DESTNODES
 
- HPI_DESTNODE_AESEBU_OUT
 
- HPI_DESTNODE_ANALOG
 
- HPI_DESTNODE_AVB
 
- HPI_DESTNODE_BLULINK
 
- HPI_DESTNODE_COBRANET
 
- HPI_DESTNODE_INTERNAL
 
- HPI_DESTNODE_ISTREAM
 
- HPI_DESTNODE_LAST_INDEX
 
- HPI_DESTNODE_LINEOUT
 
- HPI_DESTNODE_NONE
 
- HPI_DESTNODE_RF
 
- HPI_DESTNODE_RTP_SOURCE
 
- HPI_DESTNODE_SPEAKER
 
- HPI_EQUALIZER_COEFFICIENTS
 
- HPI_EQUALIZER_FILTER
 
- HPI_EQUALIZER_NUM_FILTERS
 
- HPI_ERROR_BACKEND_BASE
 
- HPI_ERROR_BAD_ADAPTER
 
- HPI_ERROR_BAD_ADAPTER_MODE
 
- HPI_ERROR_BAD_ADAPTER_NUMBER
 
- HPI_ERROR_BAD_CHECKSUM
 
- HPI_ERROR_BAD_SEQUENCE
 
- HPI_ERROR_CODES
 
- HPI_ERROR_CONTROL_CACHING
 
- HPI_ERROR_CONTROL_DISABLED
 
- HPI_ERROR_CONTROL_I2C_MISSING_ACK
 
- HPI_ERROR_CONTROL_NOT_READY
 
- HPI_ERROR_CUSTOM
 
- HPI_ERROR_DSP_BOOTLOAD
 
- HPI_ERROR_DSP_COMMUNICATION
 
- HPI_ERROR_DSP_FILE_ACCESS_DENIED
 
- HPI_ERROR_DSP_FILE_FORMAT
 
- HPI_ERROR_DSP_FILE_NOT_FOUND
 
- HPI_ERROR_DSP_FILE_NO_HEADER
 
- HPI_ERROR_DSP_FILE_NULL_HEADER
 
- HPI_ERROR_DSP_FILE_OTHER_ERROR
 
- HPI_ERROR_DSP_FILE_SHARING_VIOLATION
 
- HPI_ERROR_DSP_HARDWARE
 
- HPI_ERROR_DSP_SECTION_NOT_FOUND
 
- HPI_ERROR_DUPLICATE_ADAPTER_NUMBER
 
- HPI_ERROR_ENTITY_ITEM_COUNT
 
- HPI_ERROR_ENTITY_ROLE_INVALID
 
- HPI_ERROR_ENTITY_SIZE_MISMATCH
 
- HPI_ERROR_ENTITY_TYPE_INVALID
 
- HPI_ERROR_ENTITY_TYPE_MISMATCH
 
- HPI_ERROR_FLASH_ERASE
 
- HPI_ERROR_FLASH_PROGRAM
 
- HPI_ERROR_FLASH_READ
 
- HPI_ERROR_FLASH_READ_NO_FILE
 
- HPI_ERROR_FLASH_SIZE
 
- HPI_ERROR_FLASH_START
 
- HPI_ERROR_FLASH_TYPE
 
- HPI_ERROR_FLASH_VERIFY
 
- HPI_ERROR_I2C_BAD_ADR
 
- HPI_ERROR_I2C_MISSING_ACK
 
- HPI_ERROR_INCOMPATIBLE_SAMPLERATE
 
- HPI_ERROR_INVALID_BITRATE
 
- HPI_ERROR_INVALID_CHANNELS
 
- HPI_ERROR_INVALID_CONTROL
 
- HPI_ERROR_INVALID_CONTROL_ATTRIBUTE
 
- HPI_ERROR_INVALID_CONTROL_VALUE
 
- HPI_ERROR_INVALID_DATASIZE
 
- HPI_ERROR_INVALID_DATA_POINTER
 
- HPI_ERROR_INVALID_FORMAT
 
- HPI_ERROR_INVALID_FUNC
 
- HPI_ERROR_INVALID_HANDLE
 
- HPI_ERROR_INVALID_NODE
 
- HPI_ERROR_INVALID_OBJ
 
- HPI_ERROR_INVALID_OBJ_INDEX
 
- HPI_ERROR_INVALID_OPERATION
 
- HPI_ERROR_INVALID_PACKET_ORDER
 
- HPI_ERROR_INVALID_RESOURCE
 
- HPI_ERROR_INVALID_RESPONSE
 
- HPI_ERROR_INVALID_SAMPLERATE
 
- HPI_ERROR_INVALID_STRING
 
- HPI_ERROR_INVALID_TYPE
 
- HPI_ERROR_MEMORY_ALLOC
 
- HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL
 
- HPI_ERROR_MUTEX_TIMEOUT
 
- HPI_ERROR_NETWORK_TIMEOUT
 
- HPI_ERROR_NETWORK_TOO_MANY_CLIENTS
 
- HPI_ERROR_NO_INTERADAPTER_GROUPS
 
- HPI_ERROR_NO_INTERDSP_GROUPS
 
- HPI_ERROR_NVMEM_BUSY
 
- HPI_ERROR_NVMEM_FAIL
 
- HPI_ERROR_NVMEM_FULL
 
- HPI_ERROR_OBJ_ALREADY_OPEN
 
- HPI_ERROR_OBJ_NOT_OPEN
 
- HPI_ERROR_PLD_LOAD
 
- HPI_ERROR_PROCESSING_MESSAGE
 
- HPI_ERROR_REPORT
 
- HPI_ERROR_RESERVED_1
 
- HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL
 
- HPI_ERROR_RESPONSE_MISMATCH
 
- HPI_ERROR_TOO_MANY_CAPABILITY_CHANGE_ATTEMPTS
 
- HPI_ERROR_UNIMPLEMENTED
 
- HPI_ERROR_WAIT_CANCELLED
 
- HPI_ETHERNET_HEADER_SIZE
 
- HPI_ETHERNET_PACKET_HOSTED_VIA_HMI
 
- HPI_ETHERNET_PACKET_HOSTED_VIA_HMI_V1
 
- HPI_ETHERNET_PACKET_HOSTED_VIA_HPI
 
- HPI_ETHERNET_PACKET_HOSTED_VIA_HPI_V1
 
- HPI_ETHERNET_PACKET_ID
 
- HPI_ETHERNET_PACKET_V1
 
- HPI_ETHERNET_TIMEOUT_MS
 
- HPI_ETHERNET_UDP_PORT
 
- HPI_EXTRACT_INDEX
 
- HPI_FILTER_TYPE
 
- HPI_FILTER_TYPE_BANDPASS
 
- HPI_FILTER_TYPE_BANDSTOP
 
- HPI_FILTER_TYPE_BYPASS
 
- HPI_FILTER_TYPE_EQ_BAND
 
- HPI_FILTER_TYPE_HIGHPASS
 
- HPI_FILTER_TYPE_HIGHSHELF
 
- HPI_FILTER_TYPE_LOWPASS
 
- HPI_FILTER_TYPE_LOWSHELF
 
- HPI_FORMATS
 
- HPI_FORMAT_AA_TAGIT1_HITS
 
- HPI_FORMAT_AA_TAGIT1_HITS_EX1
 
- HPI_FORMAT_AA_TAGIT1_INSERTS
 
- HPI_FORMAT_DOLBY_AC2
 
- HPI_FORMAT_DOLBY_AC3
 
- HPI_FORMAT_MIXER_NATIVE
 
- HPI_FORMAT_MPEG_L1
 
- HPI_FORMAT_MPEG_L2
 
- HPI_FORMAT_MPEG_L3
 
- HPI_FORMAT_OEM1
 
- HPI_FORMAT_OEM2
 
- HPI_FORMAT_PCM16_BIGENDIAN
 
- HPI_FORMAT_PCM16_SIGNED
 
- HPI_FORMAT_PCM24_SIGNED
 
- HPI_FORMAT_PCM32_FLOAT
 
- HPI_FORMAT_PCM32_SIGNED
 
- HPI_FORMAT_PCM8_UNSIGNED
 
- HPI_FORMAT_RAW_BITSTREAM
 
- HPI_FORMAT_UNDEFINED
 
- HPI_FUNCTION_IDS
 
- HPI_FUNC_ID
 
- HPI_GAIN_OFF
 
- HPI_GENERIC_ENABLE
 
- HPI_GENERIC_EVENT_ENABLE
 
- HPI_GPIO_FUNCTION_COUNT
 
- HPI_GPIO_OPEN
 
- HPI_GPIO_READ_ALL
 
- HPI_GPIO_READ_BIT
 
- HPI_GPIO_WRITE_BIT
 
- HPI_GPIO_WRITE_STATUS
 
- HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
 
- HPI_HIF_ADAPTER_INFO_EXTRACT_HWVERSION_MAJOR
 
- HPI_HIF_ADAPTER_INFO_EXTRACT_HWVERSION_MINOR
 
- HPI_HIF_ADDR
 
- HPI_HIF_BASE
 
- HPI_HIF_DATA_MASK
 
- HPI_HIF_ERROR_MASK
 
- HPI_HIF_GET_DATA
 
- HPI_HIF_GET_RESP
 
- HPI_HIF_IDLE
 
- HPI_HIF_PACK_ADAPTER_INFO
 
- HPI_HIF_RESET
 
- HPI_HIF_SEND_DATA
 
- HPI_HIF_SEND_DONE
 
- HPI_HIF_SEND_MSG
 
- HPI_ID_ISAPNP_AUDIOSCIENCE
 
- HPI_IOCTL_LINUX
 
- HPI_IRQ_MESSAGE
 
- HPI_IRQ_MIXER
 
- HPI_IRQ_NONE
 
- HPI_IRQ_ROUTING_REG
 
- HPI_ISTREAM_ANC_GET_INFO
 
- HPI_ISTREAM_ANC_RESET
 
- HPI_ISTREAM_ANC_WRITE
 
- HPI_ISTREAM_CLOSE
 
- HPI_ISTREAM_FUNCTION_COUNT
 
- HPI_ISTREAM_GET_INFO
 
- HPI_ISTREAM_GROUP_ADD
 
- HPI_ISTREAM_GROUP_GETMAP
 
- HPI_ISTREAM_GROUP_RESET
 
- HPI_ISTREAM_HOSTBUFFER_ALLOC
 
- HPI_ISTREAM_HOSTBUFFER_FREE
 
- HPI_ISTREAM_HOSTBUFFER_GET_INFO
 
- HPI_ISTREAM_MPEG_ANC_ALIGNS
 
- HPI_ISTREAM_OPEN
 
- HPI_ISTREAM_QUERY_FORMAT
 
- HPI_ISTREAM_READ
 
- HPI_ISTREAM_RESET
 
- HPI_ISTREAM_SET_FORMAT
 
- HPI_ISTREAM_START
 
- HPI_ISTREAM_STOP
 
- HPI_ISTREAM_WAIT
 
- HPI_ISTREAM_WAIT_START
 
- HPI_LEVEL_GAIN
 
- HPI_LEVEL_RANGE
 
- HPI_LIB_VER
 
- HPI_LOCKING
 
- HPI_MAILBOX
 
- HPI_MAX_ADAPTERS
 
- HPI_MAX_ADAPTER_MEM_SPACES
 
- HPI_MAX_ANC_BYTES_PER_FRAME
 
- HPI_MAX_CHANNELS
 
- HPI_MAX_CONTROLS
 
- HPI_MAX_NODES
 
- HPI_MAX_PAYLOAD_SIZE
 
- HPI_MAX_STREAMS
 
- HPI_MESSAGE_LOWER_LAYER
 
- HPI_MESSAGE_SIZE_BY_OBJECT
 
- HPI_MESSAGE_TYPES
 
- HPI_METER_MINIMUM
 
- HPI_METER_NUM_CHANNELS
 
- HPI_METER_PEAK
 
- HPI_METER_PEAK_BALLISTICS
 
- HPI_METER_RMS
 
- HPI_METER_RMS_BALLISTICS
 
- HPI_MICROPHONE_PHANTOM_POWER
 
- HPI_MIN_NETWORK_ADAPTER_IDX
 
- HPI_MIXER_CLOSE
 
- HPI_MIXER_FUNCTION_COUNT
 
- HPI_MIXER_GET_BLOCK_HANDLE
 
- HPI_MIXER_GET_CACHE_INFO
 
- HPI_MIXER_GET_CONNECTIONS
 
- HPI_MIXER_GET_CONTROL
 
- HPI_MIXER_GET_CONTROL_ARRAY_BY_INDEX
 
- HPI_MIXER_GET_CONTROL_BY_INDEX
 
- HPI_MIXER_GET_CONTROL_MULTIPLE_CHANGED
 
- HPI_MIXER_GET_CONTROL_MULTIPLE_RESET
 
- HPI_MIXER_GET_CONTROL_MULTIPLE_VALUES
 
- HPI_MIXER_GET_INFO
 
- HPI_MIXER_GET_NODE_INFO
 
- HPI_MIXER_GET_PARAMETER_HANDLE
 
- HPI_MIXER_OPEN
 
- HPI_MIXER_SET_CONNECTION
 
- HPI_MIXER_STORE
 
- HPI_MIXER_STORE_COMMAND
 
- HPI_MIXER_STORE_DELETE
 
- HPI_MIXER_STORE_DISABLE
 
- HPI_MIXER_STORE_ENABLE
 
- HPI_MIXER_STORE_RESTORE
 
- HPI_MIXER_STORE_SAVE
 
- HPI_MIXER_STORE_SAVE_SINGLE
 
- HPI_MODULE_FAMILY_ASI
 
- HPI_MODULE_FAMILY_MASK
 
- HPI_MPEG_ANC_ALIGN_LEFT
 
- HPI_MPEG_ANC_ALIGN_RIGHT
 
- HPI_MPEG_ANC_HASENERGY
 
- HPI_MPEG_ANC_MODES
 
- HPI_MPEG_ANC_RAW
 
- HPI_MPEG_MODES
 
- HPI_MPEG_MODE_DEFAULT
 
- HPI_MPEG_MODE_DUALCHANNEL
 
- HPI_MPEG_MODE_JOINTSTEREO
 
- HPI_MPEG_MODE_STEREO
 
- HPI_MULTIPLEXER_QUERYSOURCE
 
- HPI_MULTIPLEXER_SOURCE
 
- HPI_NMIXER_CONTROLS
 
- HPI_NO_OS_FILE_OPS
 
- HPI_NVMEMORY_FUNCTION_COUNT
 
- HPI_NVMEMORY_OPEN
 
- HPI_NVMEMORY_READ_BYTE
 
- HPI_NVMEMORY_WRITE_BYTE
 
- HPI_OBJECT_TYPES
 
- HPI_OBJ_ADAPTER
 
- HPI_OBJ_ASYNCEVENT
 
- HPI_OBJ_CLOCK
 
- HPI_OBJ_CONTROL
 
- HPI_OBJ_FUNCTION_SPACING
 
- HPI_OBJ_GPIO
 
- HPI_OBJ_ISTREAM
 
- HPI_OBJ_MIXER
 
- HPI_OBJ_NODE
 
- HPI_OBJ_NVMEMORY
 
- HPI_OBJ_OSTREAM
 
- HPI_OBJ_PROFILE
 
- HPI_OBJ_SUBSYSTEM
 
- HPI_OBJ_WATCHDOG
 
- HPI_OSTREAM_ANC_GET_INFO
 
- HPI_OSTREAM_ANC_READ
 
- HPI_OSTREAM_ANC_RESET
 
- HPI_OSTREAM_CLOSE
 
- HPI_OSTREAM_DATA
 
- HPI_OSTREAM_FUNCTION_COUNT
 
- HPI_OSTREAM_GET_INFO
 
- HPI_OSTREAM_GROUP_ADD
 
- HPI_OSTREAM_GROUP_GETMAP
 
- HPI_OSTREAM_GROUP_RESET
 
- HPI_OSTREAM_HOSTBUFFER_ALLOC
 
- HPI_OSTREAM_HOSTBUFFER_FREE
 
- HPI_OSTREAM_HOSTBUFFER_GET_INFO
 
- HPI_OSTREAM_OPEN
 
- HPI_OSTREAM_QUERY_FORMAT
 
- HPI_OSTREAM_RESET
 
- HPI_OSTREAM_SET_FORMAT
 
- HPI_OSTREAM_SET_PUNCHINOUT
 
- HPI_OSTREAM_SET_TIMESCALE
 
- HPI_OSTREAM_SET_VELOCITY
 
- HPI_OSTREAM_SINEGEN
 
- HPI_OSTREAM_START
 
- HPI_OSTREAM_STOP
 
- HPI_OSTREAM_TIMESCALE_PASSTHROUGH
 
- HPI_OSTREAM_TIMESCALE_UNITS
 
- HPI_OSTREAM_VELOCITY_UNITS
 
- HPI_OSTREAM_WAIT
 
- HPI_OSTREAM_WAIT_START
 
- HPI_OSTREAM_WRITE
 
- HPI_OS_DEFINED
 
- HPI_OS_LINUX_KERNEL
 
- HPI_PAD_ARTIST
 
- HPI_PAD_ARTIST_LEN
 
- HPI_PAD_CHANNEL_NAME
 
- HPI_PAD_CHANNEL_NAME_LEN
 
- HPI_PAD_COMMENT
 
- HPI_PAD_COMMENT_LEN
 
- HPI_PAD_PROGRAM_ID
 
- HPI_PAD_PROGRAM_TYPE
 
- HPI_PAD_PROGRAM_TYPE_INVALID
 
- HPI_PAD_TA_ACTIVE
 
- HPI_PAD_TA_SUPPORT
 
- HPI_PAD_TITLE
 
- HPI_PAD_TITLE_LEN
 
- HPI_PCI_DEV_ID_DSP6205
 
- HPI_PCI_DEV_ID_PCI2040
 
- HPI_PCI_VENDOR_ID_AUDIOSCIENCE
 
- HPI_PCI_VENDOR_ID_MOTOROLA
 
- HPI_PCI_VENDOR_ID_TI
 
- HPI_POLARITY_NEGATIVE
 
- HPI_POLARITY_POSITIVE
 
- HPI_PROFILE_GET
 
- HPI_PROFILE_GET_IDLECOUNT
 
- HPI_PROFILE_GET_NAME
 
- HPI_PROFILE_GET_UTILIZATION
 
- HPI_PROFILE_OPEN_ALL
 
- HPI_PROFILE_START_ALL
 
- HPI_PROFILE_STOP_ALL
 
- HPI_RDS_DATATYPE_RBDS
 
- HPI_RDS_DATATYPE_RDS
 
- HPI_RESET
 
- HPI_RESPONSE_SIZE_BY_OBJECT
 
- HPI_SAMPLECLOCK_AUTO
 
- HPI_SAMPLECLOCK_LOCAL_LOCK
 
- HPI_SAMPLECLOCK_LOCAL_SAMPLERATE
 
- HPI_SAMPLECLOCK_SAMPLERATE
 
- HPI_SAMPLECLOCK_SOURCE
 
- HPI_SAMPLECLOCK_SOURCES
 
- HPI_SAMPLECLOCK_SOURCE_AESEBU_INPUT
 
- HPI_SAMPLECLOCK_SOURCE_AESEBU_SYNC
 
- HPI_SAMPLECLOCK_SOURCE_BLULINK
 
- HPI_SAMPLECLOCK_SOURCE_INDEX
 
- HPI_SAMPLECLOCK_SOURCE_LAST
 
- HPI_SAMPLECLOCK_SOURCE_LOCAL
 
- HPI_SAMPLECLOCK_SOURCE_NETWORK
 
- HPI_SAMPLECLOCK_SOURCE_PREV_MODULE
 
- HPI_SAMPLECLOCK_SOURCE_SMPTE
 
- HPI_SAMPLECLOCK_SOURCE_WORD
 
- HPI_SAMPLECLOCK_SOURCE_WORD_HEADER
 
- HPI_SILENCEDETECTOR_DELAY
 
- HPI_SILENCEDETECTOR_STATE
 
- HPI_SILENCEDETECTOR_THRESHOLD
 
- HPI_SOURCENODES
 
- HPI_SOURCENODE_ADAPTER
 
- HPI_SOURCENODE_AESEBU_IN
 
- HPI_SOURCENODE_ANALOG
 
- HPI_SOURCENODE_AVB
 
- HPI_SOURCENODE_BLULINK
 
- HPI_SOURCENODE_CLOCK_SOURCE
 
- HPI_SOURCENODE_COBRANET
 
- HPI_SOURCENODE_INTERNAL
 
- HPI_SOURCENODE_LAST_INDEX
 
- HPI_SOURCENODE_LINEIN
 
- HPI_SOURCENODE_MICROPHONE
 
- HPI_SOURCENODE_NONE
 
- HPI_SOURCENODE_OSTREAM
 
- HPI_SOURCENODE_RAW_BITSTREAM
 
- HPI_SOURCENODE_RF
 
- HPI_SOURCENODE_RTP_DESTINATION
 
- HPI_SOURCENODE_TUNER
 
- HPI_STATE_DRAINED
 
- HPI_STATE_PLAYING
 
- HPI_STATE_RECORDING
 
- HPI_STATE_SINEGEN
 
- HPI_STATE_STOPPED
 
- HPI_STATE_WAIT
 
- HPI_STATUS
 
- HPI_STATUS_ADDR
 
- HPI_STREAM_STATES
 
- HPI_STRING_LEN
 
- HPI_SUBSYS_CLOSE
 
- HPI_SUBSYS_CREATE_ADAPTER
 
- HPI_SUBSYS_DRIVER_LOAD
 
- HPI_SUBSYS_DRIVER_UNLOAD
 
- HPI_SUBSYS_FUNCTION_COUNT
 
- HPI_SUBSYS_GET_ADAPTER
 
- HPI_SUBSYS_GET_INFO
 
- HPI_SUBSYS_GET_NUM_ADAPTERS
 
- HPI_SUBSYS_GET_VERSION
 
- HPI_SUBSYS_OPEN
 
- HPI_SUBSYS_OPTIONS
 
- HPI_SUBSYS_OPTION_GET
 
- HPI_SUBSYS_OPTION_INFO
 
- HPI_SUBSYS_OPTION_SET
 
- HPI_SUBSYS_OPT_NET_ADAPTER_ADDRESS_ADD
 
- HPI_SUBSYS_OPT_NET_ADDR
 
- HPI_SUBSYS_OPT_NET_BROADCAST
 
- HPI_SUBSYS_OPT_NET_ENABLE
 
- HPI_SUBSYS_OPT_NET_MASK
 
- HPI_SUBSYS_OPT_NET_UNICAST
 
- HPI_SUBSYS_SET_NETWORK_INTERFACE
 
- HPI_SWAP_ENABLE
 
- HPI_SWITCH_OFF
 
- HPI_SWITCH_ON
 
- HPI_SWITCH_STATES
 
- HPI_TONEDETECTOR_FREQUENCY
 
- HPI_TONEDETECTOR_STATE
 
- HPI_TONEDETECTOR_THRESHOLD
 
- HPI_TUNER_BAND
 
- HPI_TUNER_BAND_AM
 
- HPI_TUNER_BAND_AUX
 
- HPI_TUNER_BAND_DAB
 
- HPI_TUNER_BAND_FM
 
- HPI_TUNER_BAND_FM_STEREO
 
- HPI_TUNER_BAND_LAST
 
- HPI_TUNER_BAND_TV
 
- HPI_TUNER_BAND_TV_NTSC_M
 
- HPI_TUNER_BAND_TV_PAL_BG
 
- HPI_TUNER_BAND_TV_PAL_DK
 
- HPI_TUNER_BAND_TV_PAL_I
 
- HPI_TUNER_BAND_TV_SECAM_L
 
- HPI_TUNER_DEEMPHASIS
 
- HPI_TUNER_DIGITAL
 
- HPI_TUNER_FM_STEREO
 
- HPI_TUNER_FREQ
 
- HPI_TUNER_GAIN
 
- HPI_TUNER_HDRADIO_BLEND
 
- HPI_TUNER_HDRADIO_DSP_VERSION
 
- HPI_TUNER_HDRADIO_SDK_VERSION
 
- HPI_TUNER_HDRADIO_SIGNAL_QUALITY
 
- HPI_TUNER_LEVEL_AVG
 
- HPI_TUNER_LEVEL_RAW
 
- HPI_TUNER_MODE
 
- HPI_TUNER_MODES
 
- HPI_TUNER_MODE_RDS
 
- HPI_TUNER_MODE_RDS_DISABLE
 
- HPI_TUNER_MODE_RDS_RBDS
 
- HPI_TUNER_MODE_RDS_RDS
 
- HPI_TUNER_MODE_RSS
 
- HPI_TUNER_MODE_RSS_DISABLE
 
- HPI_TUNER_MODE_RSS_ENABLE
 
- HPI_TUNER_MODE_VALUES
 
- HPI_TUNER_MULTIPROGRAM
 
- HPI_TUNER_PLL_LOCKED
 
- HPI_TUNER_PROGRAM
 
- HPI_TUNER_RDS
 
- HPI_TUNER_SNR
 
- HPI_TUNER_STATUS
 
- HPI_TUNER_STATUS_BITS
 
- HPI_TUNER_VIDEO_COLOR_PRESENT
 
- HPI_TUNER_VIDEO_HORZ_SYNC_MISSING
 
- HPI_TUNER_VIDEO_IS_60HZ
 
- HPI_TUNER_VIDEO_STATUS_VALID
 
- HPI_TYPE_COMMAND
 
- HPI_TYPE_DATA
 
- HPI_TYPE_NOTIFICATION
 
- HPI_TYPE_REQUEST
 
- HPI_TYPE_RESPONSE
 
- HPI_TYPE_SSX2BYPASS_MESSAGE
 
- HPI_T_CYC_NS
 
- HPI_UNITS_PER_dB
 
- HPI_UNIVERSAL_ENTITY
 
- HPI_USB_LINUX_TAG
 
- HPI_USB_VENDOR_ID_AUDIOSCIENCE
 
- HPI_USB_W2K_TAG
 
- HPI_VER
 
- HPI_VERSION_CONSTRUCTOR
 
- HPI_VER_MAJOR
 
- HPI_VER_MINOR
 
- HPI_VER_RELEASE
 
- HPI_VER_STRING
 
- HPI_VOLUME_AUTOFADE
 
- HPI_VOLUME_AUTOFADES
 
- HPI_VOLUME_AUTOFADE_LINEAR
 
- HPI_VOLUME_AUTOFADE_LOG
 
- HPI_VOLUME_FLAGS
 
- HPI_VOLUME_FLAG_HAS_AUTOFADE
 
- HPI_VOLUME_FLAG_HAS_MUTE
 
- HPI_VOLUME_FLAG_MUTED
 
- HPI_VOLUME_GAIN
 
- HPI_VOLUME_GAIN_AND_FLAGS
 
- HPI_VOLUME_MUTE
 
- HPI_VOLUME_NUM_CHANNELS
 
- HPI_VOLUME_RANGE
 
- HPI_VOX_THRESHOLD
 
- HPI_WATCHDOG_OPEN
 
- HPI_WATCHDOG_PING
 
- HPI_WATCHDOG_SET_TIME
 
- HPLANCE_ID
 
- HPLANCE_IDOFF
 
- HPLANCE_MEMOFF
 
- HPLANCE_NVRAMOFF
 
- HPLANCE_REGOFF
 
- HPLANCE_STATUS
 
- HPLCOM_CFG
 
- HPLCOM_CTRL
 
- HPLCOM_PWR_ON
 
- HPLLCC
 
- HPLLVCO
 
- HPLLVCO_MOBILE
 
- HPLOUT_CTRL
 
- HPLOUT_PWR_ON
 
- HPL_MIXER
 
- HPMC_IODC_BUF_SIZE
 
- HPMC_PIM_DATA_SIZE
 
- HPMC_SET_PARAMS_INTR
 
- HPMC_SET_PARAMS_WAKE
 
- HPMEM_B000
 
- HPMEM_C800
 
- HPMEM_D000
 
- HPMEM_D400
 
- HPMEM_D800
 
- HPMEM_E000
 
- HPMEM_E800
 
- HPMEM_NONE
 
- HPMIXL_DIS
 
- HPMIXL_EN
 
- HPMIXL_INIT2_DIS
 
- HPMIXL_INIT2_EN
 
- HPMIXL_INIT2_MASK
 
- HPMIXL_INIT_DIS
 
- HPMIXL_INIT_EN
 
- HPMIXL_INIT_MASK
 
- HPMIXL_MASK
 
- HPMIXR_DIS
 
- HPMIXR_EN
 
- HPMIXR_INIT2_DIS
 
- HPMIXR_INIT2_EN
 
- HPMIXR_INIT2_MASK
 
- HPMIXR_INIT_DIS
 
- HPMIXR_INIT_EN
 
- HPMIXR_INIT_MASK
 
- HPMIXR_MASK
 
- HPMIX_CTRL
 
- HPMTN
 
- HPM_DEBUG
 
- HPM_HIPM_GEN_CFG
 
- HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE
 
- HPM_HIPM_GEN_CFG_CR_PG_EN
 
- HPM_HIPM_GEN_CFG_CR_SLP_EN
 
- HPOFSR
 
- HPON_FSM_BONDING_1T2R
 
- HPON_FSM_BONDING_MASK
 
- HPOSTAMBLE
 
- HPOUT1L
 
- HPOUT1R
 
- HPOUT2L
 
- HPOUT2R
 
- HPOUTL_DIS
 
- HPOUTL_EN
 
- HPOUTL_GAIN_CTRL
 
- HPOUTL_GAIN_MASK
 
- HPOUTL_INIT_DIS
 
- HPOUTL_INIT_EN
 
- HPOUTL_INIT_MASK
 
- HPOUTL_MASK
 
- HPOUTL_MUTE
 
- HPOUTL_MUTE_MASK
 
- HPOUTL_POP_MASK
 
- HPOUTL_POP_WORK
 
- HPOUTL_POP_XCHARGE
 
- HPOUTL_UNMUTE
 
- HPOUTL_ZERO_CROSSING_MASK
 
- HPOUTL_ZERO_CROSSING_OFF
 
- HPOUTL_ZERO_CROSSING_ON
 
- HPOUTR_DIS
 
- HPOUTR_EN
 
- HPOUTR_GAIN_CTRL
 
- HPOUTR_GAIN_MASK
 
- HPOUTR_INIT_DIS
 
- HPOUTR_INIT_EN
 
- HPOUTR_INIT_MASK
 
- HPOUTR_MASK
 
- HPOUTR_MUTE
 
- HPOUTR_MUTE_MASK
 
- HPOUTR_POP_MASK
 
- HPOUTR_POP_WORK
 
- HPOUTR_POP_XCHARGE
 
- HPOUTR_UNMUTE
 
- HPOUTR_ZERO_CROSSING_MASK
 
- HPOUTR_ZERO_CROSSING_OFF
 
- HPOUTR_ZERO_CROSSING_ON
 
- HPOUT_CTRL
 
- HPOUT_POP_CTRL
 
- HPOUT_POP_REDUCTION
 
- HPOUT_SC
 
- HPOUT_SC_OCMV_1_35V
 
- HPOUT_SC_OCMV_1_5V
 
- HPOUT_SC_OCMV_1_65V
 
- HPOUT_SC_OCMV_1_8V
 
- HPOUT_SC_OCMV_MASK
 
- HPOUT_SC_OCMV_SHIFT
 
- HPPRORESET_OFF
 
- HPPRORESET_ON
 
- HPP_PERCENT_ACC_FNS
 
- HPP_PERCENT_FNS
 
- HPP_RAW_FNS
 
- HPP__COLOR_ACC_PRINT_FNS
 
- HPP__COLOR_PRINT_FNS
 
- HPP__PRINT_FNS
 
- HPQ
 
- HPQBusy
 
- HPQFull
 
- HPQOver
 
- HPQ_PUBLIC_DIS
 
- HPRCOM_CFG
 
- HPRCOM_CTRL
 
- HPRCOM_PWR_ON
 
- HPREAMBLE
 
- HPRINTK
 
- HPROT_BUFFERABLE
 
- HPROT_CACHABLE
 
- HPROT_DATA_CACHE
 
- HPROT_PRIVILIGED
 
- HPROUT_CTRL
 
- HPROUT_PWR_ON
 
- HPRT0
 
- HPRT0_CONNDET
 
- HPRT0_CONNSTS
 
- HPRT0_ENA
 
- HPRT0_ENACHG
 
- HPRT0_LNSTS_MASK
 
- HPRT0_LNSTS_SHIFT
 
- HPRT0_OVRCURRACT
 
- HPRT0_OVRCURRCHG
 
- HPRT0_PWR
 
- HPRT0_RES
 
- HPRT0_RST
 
- HPRT0_SPD_FULL_SPEED
 
- HPRT0_SPD_HIGH_SPEED
 
- HPRT0_SPD_LOW_SPEED
 
- HPRT0_SPD_MASK
 
- HPRT0_SPD_SHIFT
 
- HPRT0_SUSP
 
- HPRT0_TSTCTL_MASK
 
- HPRT0_TSTCTL_SHIFT
 
- HPR_BLRC
 
- HPR_MIXER
 
- HPR_SPR1
 
- HPR_SPR2
 
- HPR_TCL0
 
- HPR_TCL1
 
- HPR_TCL2
 
- HPR_TCL3
 
- HPR_TCL4
 
- HPS2FPGA_BRIDGE_NAME
 
- HPS2FPGA_RESET
 
- HPSA
 
- HPSATMF_BITS_SUPPORTED
 
- HPSATMF_IOACCEL_ENABLED
 
- HPSATMF_LOG_CLEAR_ACA
 
- HPSATMF_LOG_CLEAR_TSET
 
- HPSATMF_LOG_LUN_RESET
 
- HPSATMF_LOG_NEX_RESET
 
- HPSATMF_LOG_QRY_ASYNC
 
- HPSATMF_LOG_QRY_TASK
 
- HPSATMF_LOG_QRY_TSET
 
- HPSATMF_LOG_TASK_ABORT
 
- HPSATMF_LOG_TSET_ABORT
 
- HPSATMF_MASK_SUPPORTED
 
- HPSATMF_PHYS_CLEAR_ACA
 
- HPSATMF_PHYS_CLEAR_TSET
 
- HPSATMF_PHYS_LUN_RESET
 
- HPSATMF_PHYS_NEX_RESET
 
- HPSATMF_PHYS_QRY_ASYNC
 
- HPSATMF_PHYS_QRY_TASK
 
- HPSATMF_PHYS_QRY_TSET
 
- HPSATMF_PHYS_TASK_ABORT
 
- HPSATMF_PHYS_TSET_ABORT
 
- HPSA_ABORT_MSG
 
- HPSA_BOARD_NOT_READY_ITERATIONS
 
- HPSA_BOARD_NOT_READY_WAIT_SECS
 
- HPSA_BOARD_READY_ITERATIONS
 
- HPSA_BOARD_READY_POLL_INTERVAL
 
- HPSA_BOARD_READY_POLL_INTERVAL_MSECS
 
- HPSA_BOARD_READY_WAIT_SECS
 
- HPSA_BUS_RESET_TYPE
 
- HPSA_CACHE_FLUSH
 
- HPSA_CISS_READ
 
- HPSA_CMDS_RESERVED_FOR_ABORTS
 
- HPSA_CMDS_RESERVED_FOR_DRIVER
 
- HPSA_CMD_H
 
- HPSA_CTLR_RESET_TYPE
 
- HPSA_DEVICE_RESET_MSG
 
- HPSA_DIAG_OPTS_DISABLE_RLD_CACHING
 
- HPSA_DRIVER_VERSION
 
- HPSA_EH_PTRAID_TIMEOUT
 
- HPSA_ERROR_BIT
 
- HPSA_EVENT_MONITOR_INTERVAL
 
- HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE
 
- HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE
 
- HPSA_EXTERNAL_RAID_VOLUME_BUS
 
- HPSA_FIRMWARE_READY
 
- HPSA_GET_RAID_MAP
 
- HPSA_H
 
- HPSA_HBA_BUS
 
- HPSA_INQUIRY
 
- HPSA_INQUIRY_FAILED
 
- HPSA_INTR_OFF
 
- HPSA_INTR_ON
 
- HPSA_IOACCEL2_HEADER_SZ
 
- HPSA_LEGACY_HBA_BUS
 
- HPSA_LUN_RESET_TYPE
 
- HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER
 
- HPSA_LV_ENCRYPTED_NO_KEY
 
- HPSA_LV_FAILED
 
- HPSA_LV_NOT_AVAILABLE
 
- HPSA_LV_OK
 
- HPSA_LV_PENDING_ENCRYPTION
 
- HPSA_LV_PENDING_ENCRYPTION_REKEYING
 
- HPSA_LV_PENDING_RPI
 
- HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER
 
- HPSA_LV_UNDERGOING_ENCRYPTION
 
- HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING
 
- HPSA_LV_UNDERGOING_ERASE
 
- HPSA_LV_UNDERGOING_RPI
 
- HPSA_MAP_DEBUG
 
- HPSA_MAX_CONCURRENT_PASSTHRUS
 
- HPSA_MAX_DEVICES
 
- HPSA_MAX_LUN
 
- HPSA_MAX_PHYS_LUN
 
- HPSA_MAX_POLL_TIME_SECS
 
- HPSA_MAX_WAIT_INTERVAL_SECS
 
- HPSA_MSG_SEND_RETRY_INTERVAL_MSECS
 
- HPSA_MSG_SEND_RETRY_LIMIT
 
- HPSA_NEXUS_RESET_TYPE
 
- HPSA_NOOP
 
- HPSA_NRESERVED_CMDS
 
- HPSA_PHYSICAL_DEVICE_BUS
 
- HPSA_PHYS_TARGET_RESET
 
- HPSA_POST_RESET_NOOP_RETRIES
 
- HPSA_POST_RESET_PAUSE_MSECS
 
- HPSA_RAID_0
 
- HPSA_RAID_1
 
- HPSA_RAID_4
 
- HPSA_RAID_5
 
- HPSA_RAID_51
 
- HPSA_RAID_6
 
- HPSA_RAID_ADM
 
- HPSA_RAID_VOLUME_BUS
 
- HPSA_REPORT_LOG
 
- HPSA_REPORT_PHYS
 
- HPSA_REPORT_PHYS_EXTENDED
 
- HPSA_RESET
 
- HPSA_RESET_TYPE_BUS
 
- HPSA_RESET_TYPE_CONTROLLER
 
- HPSA_RESET_TYPE_LUN
 
- HPSA_SCAN
 
- HPSA_SG_CHAIN
 
- HPSA_SG_LAST
 
- HPSA_SIMPLE_ERROR_BITS
 
- HPSA_TARGET_RESET_TYPE
 
- HPSA_TASK_MANAGEMENT
 
- HPSA_TMF_ABORT_TASK
 
- HPSA_TMF_ABORT_TASK_SET
 
- HPSA_TMF_CLEAR_ACA
 
- HPSA_TMF_CLEAR_TASK_SET
 
- HPSA_TMF_QUERY_ASYNCEVENT
 
- HPSA_TMF_QUERY_TASK
 
- HPSA_TMF_QUERY_TASK_SET
 
- HPSA_TUR_RETRY_LIMIT
 
- HPSA_VPD_HEADER_SZ
 
- HPSA_VPD_LV_DEVICE_GEOMETRY
 
- HPSA_VPD_LV_DEVICE_ID
 
- HPSA_VPD_LV_IOACCEL_STATUS
 
- HPSA_VPD_LV_STATUS
 
- HPSA_VPD_LV_STATUS_UNSUPPORTED
 
- HPSA_VPD_SUPPORTED_PAGES
 
- HPSCSI_RESET
 
- HPSIR
 
- HPSIZE
 
- HPSPR
 
- HPS_CTRL
 
- HPS_H_PRESCALE
 
- HPS_H_SCALE
 
- HPS_SETUP
 
- HPS_V_GAIN
 
- HPS_V_SCALE
 
- HPT302
 
- HPT302N
 
- HPT302_ALLOW_ATA133_6
 
- HPT366_ALLOW_ATA66_3
 
- HPT366_ALLOW_ATA66_4
 
- HPT36x
 
- HPT370
 
- HPT370A
 
- HPT370_ALLOW_ATA100_5
 
- HPT371
 
- HPT371N
 
- HPT371_ALLOW_ATA133_6
 
- HPT372
 
- HPT372A
 
- HPT372N
 
- HPT372_ALLOW_ATA133_6
 
- HPT374
 
- HPTEG_CACHE_NUM
 
- HPTEG_HASH_BITS_PTE
 
- HPTEG_HASH_BITS_PTE_LONG
 
- HPTEG_HASH_BITS_VPTE
 
- HPTEG_HASH_BITS_VPTE_64K
 
- HPTEG_HASH_BITS_VPTE_LONG
 
- HPTEG_HASH_NUM_PTE
 
- HPTEG_HASH_NUM_PTE_LONG
 
- HPTEG_HASH_NUM_VPTE
 
- HPTEG_HASH_NUM_VPTE_64K
 
- HPTEG_HASH_NUM_VPTE_LONG
 
- HPTES_PER_GROUP
 
- HPTE_GR_MODIFIED
 
- HPTE_GR_RESERVED
 
- HPTE_LOCAL_UPDATE
 
- HPTE_LOCK_BIT
 
- HPTE_NOHPTE_UPDATE
 
- HPTE_R_3_0_SSIZE_MASK
 
- HPTE_R_3_0_SSIZE_SHIFT
 
- HPTE_R_C
 
- HPTE_R_G
 
- HPTE_R_I
 
- HPTE_R_KEY
 
- HPTE_R_KEY_BIT0
 
- HPTE_R_KEY_BIT1
 
- HPTE_R_KEY_BIT2
 
- HPTE_R_KEY_BIT3
 
- HPTE_R_KEY_BIT4
 
- HPTE_R_KEY_HI
 
- HPTE_R_KEY_LO
 
- HPTE_R_M
 
- HPTE_R_N
 
- HPTE_R_PP
 
- HPTE_R_PP0
 
- HPTE_R_PPP
 
- HPTE_R_R
 
- HPTE_R_RPN
 
- HPTE_R_RPN_3_0
 
- HPTE_R_RPN_SHIFT
 
- HPTE_R_TS
 
- HPTE_R_W
 
- HPTE_R_WIMG
 
- HPTE_SIZE
 
- HPTE_V_1TB_SEG
 
- HPTE_V_ABSENT
 
- HPTE_V_AVPN
 
- HPTE_V_AVPN_3_0
 
- HPTE_V_AVPN_SHIFT
 
- HPTE_V_AVPN_VAL
 
- HPTE_V_BOLTED
 
- HPTE_V_COMMON_BITS
 
- HPTE_V_COMPARE
 
- HPTE_V_HVLOCK
 
- HPTE_V_LARGE
 
- HPTE_V_LOCK
 
- HPTE_V_SECONDARY
 
- HPTE_V_SSIZE_SHIFT
 
- HPTE_V_VALID
 
- HPTE_V_VRMA_MASK
 
- HPTIOP_MAX_REQUESTS
 
- HPTXFSIZ
 
- HPTXSTS
 
- HPT_ALIGN_PAGES
 
- HPT_DELAY_INTERRUPT
 
- HPT_IOCTL_RESULT_FAILED
 
- HPT_IOCTL_RESULT_OK
 
- HPT_PCI_FAST
 
- HPT_RESET_STATE_ENGINE
 
- HPT_RESIZE_TIMEOUT
 
- HPT_SCP
 
- HPU
 
- HPVDD
 
- HPW
 
- HPWAITSTATE_0
 
- HPWAITSTATE_1
 
- HPWDT_MAX_TICKS
 
- HPWDT_MAX_TIMER
 
- HPWDT_VERSION
 
- HPWMI_ALS_QUERY
 
- HPWMI_BACKLIT_KB_BRIGHTNESS
 
- HPWMI_BATTERY_CHARGE_PERIOD
 
- HPWMI_BATTERY_QUERY
 
- HPWMI_BEZEL_BUTTON
 
- HPWMI_BIOS_GUID
 
- HPWMI_BIOS_QUERY
 
- HPWMI_BLUETOOTH
 
- HPWMI_COOLSENSE_SYSTEM_HOT
 
- HPWMI_COOLSENSE_SYSTEM_MOBILE
 
- HPWMI_CPU_BATTERY_THROTTLE
 
- HPWMI_DISPLAY_QUERY
 
- HPWMI_DOCK_EVENT
 
- HPWMI_DOCK_MASK
 
- HPWMI_EVENT_GUID
 
- HPWMI_FEATURE2_QUERY
 
- HPWMI_FEATURE_QUERY
 
- HPWMI_GPS
 
- HPWMI_HARDWARE_QUERY
 
- HPWMI_HDDTEMP_QUERY
 
- HPWMI_HOTKEY_QUERY
 
- HPWMI_LID_SWITCH
 
- HPWMI_LOCK_SWITCH
 
- HPWMI_MAX_RFKILL2_DEVICES
 
- HPWMI_ODM
 
- HPWMI_PARK_HDD
 
- HPWMI_PEAKSHIFT_PERIOD
 
- HPWMI_POSTCODEERROR_QUERY
 
- HPWMI_POWER_BIOS
 
- HPWMI_POWER_HARD
 
- HPWMI_POWER_SOFT
 
- HPWMI_POWER_STATE
 
- HPWMI_PROXIMITY_SENSOR
 
- HPWMI_READ
 
- HPWMI_RET_INVALID_PARAMETERS
 
- HPWMI_RET_UNKNOWN_CMDTYPE
 
- HPWMI_RET_UNKNOWN_COMMAND
 
- HPWMI_RET_WRONG_SIGNATURE
 
- HPWMI_SCREEN_ROTATION
 
- HPWMI_SMART_ADAPTER
 
- HPWMI_TABLET_MASK
 
- HPWMI_WIFI
 
- HPWMI_WIRELESS
 
- HPWMI_WIRELESS2_QUERY
 
- HPWMI_WIRELESS_QUERY
 
- HPWMI_WRITE
 
- HPWMI_WWAN
 
- HPW_MASK
 
- HPX_CFG_DVSEC
 
- HPX_CFG_MAX
 
- HPX_CFG_PCICFG
 
- HPX_CFG_PCIE_CAP
 
- HPX_CFG_PCIE_CAP_EXT
 
- HPX_CFG_VEND_CAP
 
- HPX_FN_NORMAL
 
- HPX_FN_SRIOV_PHYS
 
- HPX_FN_SRIOV_VIRT
 
- HPX_TYPE_DOWNSTREAM
 
- HPX_TYPE_ENDPOINT
 
- HPX_TYPE_LEG_END
 
- HPX_TYPE_PCIE_BRIDGE
 
- HPX_TYPE_PCI_BRIDGE
 
- HPX_TYPE_RC_EC
 
- HPX_TYPE_RC_END
 
- HPX_TYPE_ROOT_PORT
 
- HPX_TYPE_UPSTREAM
 
- HPZ0_S
 
- HPZ0_V
 
- HPZ1_S
 
- HPZ1_V
 
- HPZ2_S
 
- HPZ2_V
 
- HPZ3_S
 
- HPZ3_V
 
- HP_320
 
- HP_330
 
- HP_340
 
- HP_345
 
- HP_350
 
- HP_360
 
- HP_370
 
- HP_375
 
- HP_380
 
- HP_385
 
- HP_400
 
- HP_425E
 
- HP_425S
 
- HP_425T
 
- HP_433S
 
- HP_433T
 
- HP_ACCEL_PM
 
- HP_AUTO_MDIX_X_OVER_IND_MASK
 
- HP_BITM
 
- HP_BLKS
 
- HP_BMC_PROD_ID
 
- HP_BUS_WIDTH_16
 
- HP_BUS_WIDTH_32
 
- HP_BUS_WIDTH_8
 
- HP_BUS_WIDTH_UNK
 
- HP_CFG_NUM_CPU_MASK
 
- HP_CFG_NUM_CPU_SHIFT
 
- HP_CFG_PARSE_EN
 
- HP_CFG_SYN_INC_MASK
 
- HP_CFG_TCP_THRESH_MASK
 
- HP_CFG_TCP_THRESH_SHIFT
 
- HP_COUNT_G
 
- HP_COUNT_M
 
- HP_COUNT_S
 
- HP_COUNT_T5_G
 
- HP_COUNT_T5_M
 
- HP_COUNT_T5_S
 
- HP_CVR
 
- HP_CVR_DEF
 
- HP_DATA_RAM_FDB_DATA_MASK
 
- HP_DATA_RAM_FDB_FDB_MASK
 
- HP_DEV_SPEED_ASYNC
 
- HP_DEV_SPEED_FAST
 
- HP_DEV_SPEED_SCSI1
 
- HP_DEV_SPEED_ULTRA
 
- HP_DEV_SPEED_ULTRA160
 
- HP_DEV_SPEED_ULTRA2
 
- HP_DEV_SPEED_ULTRA320
 
- HP_DSPR
 
- HP_FF_WU1
 
- HP_FF_WU2
 
- HP_FIFO
 
- HP_FIFO_COUNT
 
- HP_FILTER_RESET
 
- HP_FIRST_WORD
 
- HP_GAIN_RESTORE
 
- HP_GAIN_SET_ZERO
 
- HP_GETHOSTINFO
 
- HP_GETHOSTINFO1
 
- HP_GETTARGETINFO
 
- HP_IANA_MFR_ID
 
- HP_ICR
 
- HP_ICR_DEF
 
- HP_INFO
 
- HP_INSTR_RAM_ADDR_MASK
 
- HP_INSTR_RAM_HI_MASK_MASK
 
- HP_INSTR_RAM_HI_MASK_SHIFT
 
- HP_INSTR_RAM_HI_VAL_MASK
 
- HP_INSTR_RAM_HI_VAL_SHIFT
 
- HP_INSTR_RAM_LOW_OUTARG_MASK
 
- HP_INSTR_RAM_LOW_OUTARG_SHIFT
 
- HP_INSTR_RAM_LOW_OUTEN_MASK
 
- HP_INSTR_RAM_LOW_OUTEN_SHIFT
 
- HP_INSTR_RAM_LOW_OUTMASK_MASK
 
- HP_INSTR_RAM_LOW_OUTMASK_SHIFT
 
- HP_INSTR_RAM_LOW_OUTSHIFT_MASK
 
- HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT
 
- HP_INSTR_RAM_MID_FNEXT_MASK
 
- HP_INSTR_RAM_MID_FNEXT_SHIFT
 
- HP_INSTR_RAM_MID_FOFF_MASK
 
- HP_INSTR_RAM_MID_FOFF_SHIFT
 
- HP_INSTR_RAM_MID_OP_MASK
 
- HP_INSTR_RAM_MID_OP_SHIFT
 
- HP_INSTR_RAM_MID_OUTARG_MASK
 
- HP_INSTR_RAM_MID_OUTARG_SHIFT
 
- HP_INSTR_RAM_MID_OUTOP_MASK
 
- HP_INSTR_RAM_MID_OUTOP_SHIFT
 
- HP_INSTR_RAM_MID_SNEXT_MASK
 
- HP_INSTR_RAM_MID_SNEXT_SHIFT
 
- HP_INSTR_RAM_MID_SOFF_MASK
 
- HP_INSTR_RAM_MID_SOFF_SHIFT
 
- HP_INT_THRESH_M
 
- HP_INT_THRESH_S
 
- HP_INT_THRESH_T5_M
 
- HP_INT_THRESH_T5_S
 
- HP_INT_THRESH_T5_V
 
- HP_INT_THRESH_V
 
- HP_IOC_MAGIC
 
- HP_IRDA
 
- HP_IRQM
 
- HP_ISR
 
- HP_ISR_DEF
 
- HP_IVR
 
- HP_IVR_DEF
 
- HP_LCM220_PRODUCT_ID
 
- HP_LCM960_PRODUCT_ID
 
- HP_LD220TA_PRODUCT_ID
 
- HP_LD220_PRODUCT_ID
 
- HP_LD381_PRODUCT_ID
 
- HP_LD960TA_PRODUCT_ID
 
- HP_LD960_PRODUCT_ID
 
- HP_LEFT
 
- HP_LM920_PRODUCT_ID
 
- HP_LM940_PRODUCT_ID
 
- HP_LOOPS
 
- HP_MEMM
 
- HP_MS
 
- HP_MUX_HP
 
- HP_MUX_HPSPK
 
- HP_MUX_HP_IMPEDANCE
 
- HP_MUX_MASK
 
- HP_MUX_OPEN
 
- HP_MUX_TEST_MODE
 
- HP_NU
 
- HP_NUM_WORDS
 
- HP_NU_DEF
 
- HP_OUT
 
- HP_PER_CPU
 
- HP_POWER_EVENT
 
- HP_PROR
 
- HP_RAM_BIST_FDBM_AGE0_PASS
 
- HP_RAM_BIST_FDBM_AGE1_PASS
 
- HP_RAM_BIST_FDBM_FLOWID00_PASS
 
- HP_RAM_BIST_FDBM_FLOWID01_PASS
 
- HP_RAM_BIST_FDBM_FLOWID10_PASS
 
- HP_RAM_BIST_FDBM_FLOWID11_PASS
 
- HP_RAM_BIST_FDBM_FLOWID20_PASS
 
- HP_RAM_BIST_FDBM_FLOWID21_PASS
 
- HP_RAM_BIST_FDBM_FLOWID30_PASS
 
- HP_RAM_BIST_FDBM_FLOWID31_PASS
 
- HP_RAM_BIST_FDBM_TCPSEQ_PASS
 
- HP_RAM_BIST_HP_DATA_PASS
 
- HP_RAM_BIST_HP_INSTR0_PASS
 
- HP_RAM_BIST_HP_INSTR1_PASS
 
- HP_RAM_BIST_HP_INSTR2_PASS
 
- HP_RAM_BIST_START
 
- HP_RAM_BIST_SUMMARY
 
- HP_RIGHT
 
- HP_RING
 
- HP_RXH
 
- HP_RXL
 
- HP_RXM
 
- HP_SDC_ACT_AFTER
 
- HP_SDC_ACT_CALLBACK
 
- HP_SDC_ACT_DATAIN
 
- HP_SDC_ACT_DATAOUT
 
- HP_SDC_ACT_DATAREG
 
- HP_SDC_ACT_DEAD
 
- HP_SDC_ACT_DEALLOC
 
- HP_SDC_ACT_DURING
 
- HP_SDC_ACT_POSTCMD
 
- HP_SDC_ACT_PRECMD
 
- HP_SDC_ACT_SEMAPHORE
 
- HP_SDC_CFG
 
- HP_SDC_CFG_IDPROM
 
- HP_SDC_CFG_KBD
 
- HP_SDC_CFG_KBD_NEW
 
- HP_SDC_CFG_KBD_OLD
 
- HP_SDC_CFG_NEW
 
- HP_SDC_CFG_REV
 
- HP_SDC_CFG_ROLLOVER
 
- HP_SDC_CMD_DO_BEEP
 
- HP_SDC_CMD_DO_HIL
 
- HP_SDC_CMD_DO_RTCR
 
- HP_SDC_CMD_DO_RTCW
 
- HP_SDC_CMD_LOAD_CT
 
- HP_SDC_CMD_LOAD_DT
 
- HP_SDC_CMD_LOAD_FHS
 
- HP_SDC_CMD_LOAD_MT
 
- HP_SDC_CMD_LOAD_RT
 
- HP_SDC_CMD_READ_D0
 
- HP_SDC_CMD_READ_D1
 
- HP_SDC_CMD_READ_D2
 
- HP_SDC_CMD_READ_D3
 
- HP_SDC_CMD_READ_IM
 
- HP_SDC_CMD_READ_KBC
 
- HP_SDC_CMD_READ_KBN
 
- HP_SDC_CMD_READ_KCC
 
- HP_SDC_CMD_READ_KLC
 
- HP_SDC_CMD_READ_LPC
 
- HP_SDC_CMD_READ_LPR
 
- HP_SDC_CMD_READ_LPS
 
- HP_SDC_CMD_READ_RAM
 
- HP_SDC_CMD_READ_RSV
 
- HP_SDC_CMD_READ_STR
 
- HP_SDC_CMD_READ_T1
 
- HP_SDC_CMD_READ_T2
 
- HP_SDC_CMD_READ_T3
 
- HP_SDC_CMD_READ_T4
 
- HP_SDC_CMD_READ_T5
 
- HP_SDC_CMD_READ_USE
 
- HP_SDC_CMD_READ_VT1
 
- HP_SDC_CMD_READ_VT2
 
- HP_SDC_CMD_READ_VT3
 
- HP_SDC_CMD_READ_VT4
 
- HP_SDC_CMD_READ_XTD
 
- HP_SDC_CMD_SET_ARD
 
- HP_SDC_CMD_SET_ARR
 
- HP_SDC_CMD_SET_BELL
 
- HP_SDC_CMD_SET_CT
 
- HP_SDC_CMD_SET_D0
 
- HP_SDC_CMD_SET_D1
 
- HP_SDC_CMD_SET_D2
 
- HP_SDC_CMD_SET_D3
 
- HP_SDC_CMD_SET_DT
 
- HP_SDC_CMD_SET_FHS
 
- HP_SDC_CMD_SET_IM
 
- HP_SDC_CMD_SET_KBC
 
- HP_SDC_CMD_SET_KBN
 
- HP_SDC_CMD_SET_LPC
 
- HP_SDC_CMD_SET_LPR
 
- HP_SDC_CMD_SET_LPS
 
- HP_SDC_CMD_SET_MT
 
- HP_SDC_CMD_SET_RAMP
 
- HP_SDC_CMD_SET_RPGR
 
- HP_SDC_CMD_SET_RSV
 
- HP_SDC_CMD_SET_RTD
 
- HP_SDC_CMD_SET_RTMS
 
- HP_SDC_CMD_SET_STR
 
- HP_SDC_CMD_SET_VT1
 
- HP_SDC_CMD_SET_VT2
 
- HP_SDC_CMD_SET_VT3
 
- HP_SDC_CMD_SET_VT4
 
- HP_SDC_CMD_SET_XTD
 
- HP_SDC_D0
 
- HP_SDC_D1
 
- HP_SDC_D2
 
- HP_SDC_D3
 
- HP_SDC_DATA
 
- HP_SDC_HIL_AUTO
 
- HP_SDC_HIL_CMD
 
- HP_SDC_HIL_DAT
 
- HP_SDC_HIL_ERR
 
- HP_SDC_HIL_ISERR
 
- HP_SDC_HIL_R1MASK
 
- HP_SDC_HIL_RC
 
- HP_SDC_HIL_RC_DONE
 
- HP_SDC_HIL_TO
 
- HP_SDC_IM
 
- HP_SDC_IM_FH
 
- HP_SDC_IM_HIL
 
- HP_SDC_IM_MASK
 
- HP_SDC_IM_PT
 
- HP_SDC_IM_RESET
 
- HP_SDC_IM_TIMERS
 
- HP_SDC_KBC
 
- HP_SDC_KBLANGUAGE
 
- HP_SDC_KBN
 
- HP_SDC_LPC
 
- HP_SDC_LPC_APE_IPF
 
- HP_SDC_LPC_ARCONERR
 
- HP_SDC_LPC_ARCQUIET
 
- HP_SDC_LPC_COOK
 
- HP_SDC_LPC_RC
 
- HP_SDC_LPR
 
- HP_SDC_LPS
 
- HP_SDC_LPS_ACFAIL
 
- HP_SDC_LPS_ACSUCC
 
- HP_SDC_LPS_NDEV
 
- HP_SDC_MAX_REG_DELAY
 
- HP_SDC_NMISTATUS_FHS
 
- HP_SDC_RSV
 
- HP_SDC_STATUS_HILCMD
 
- HP_SDC_STATUS_HILDATA
 
- HP_SDC_STATUS_IBF
 
- HP_SDC_STATUS_IRQMASK
 
- HP_SDC_STATUS_KCOOKED
 
- HP_SDC_STATUS_KMOD_CUP
 
- HP_SDC_STATUS_KMOD_SUP
 
- HP_SDC_STATUS_KRPG
 
- HP_SDC_STATUS_PERIODIC
 
- HP_SDC_STATUS_PUP
 
- HP_SDC_STATUS_REG
 
- HP_SDC_STATUS_TIMER
 
- HP_SDC_STATUS_USERTIMER
 
- HP_SDC_STR
 
- HP_SDC_USE
 
- HP_SDC_USE_LOOP
 
- HP_SDC_VT1
 
- HP_SDC_VT2
 
- HP_SDC_VT3
 
- HP_SDC_VT4
 
- HP_SDC_XTD
 
- HP_SDC_XTD_BBRTC
 
- HP_SDC_XTD_BEEPER
 
- HP_SDC_XTD_REV
 
- HP_SDC_XTD_REV_STRINGS
 
- HP_SETUP_ADDR_CNT
 
- HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND_MASK
 
- HP_SMU_COMMAND_UPDATE__HP_SMU_COMMAND__SHIFT
 
- HP_STATUS0_HRP_OPCODE_MASK
 
- HP_STATUS0_L3_OFF_MASK
 
- HP_STATUS0_LB_CPUNUM_MASK
 
- HP_STATUS0_SAP_MASK
 
- HP_STATUS1_ACCUR2_MASK
 
- HP_STATUS1_FLOWID_MASK
 
- HP_STATUS1_TCP_OFF_MASK
 
- HP_STATUS1_TCP_SIZE_MASK
 
- HP_STATUS2_ACCUR1_MASK
 
- HP_STATUS2_ACCUR2_MASK
 
- HP_STATUS2_BWO_REASSM
 
- HP_STATUS2_CSUM_OFF_MASK
 
- HP_STATUS2_CTRL_PACKET_FLAG
 
- HP_STATUS2_DATA_MASK_ZERO
 
- HP_STATUS2_FORCE_DROP
 
- HP_STATUS2_FORCE_TCP_CHECK
 
- HP_STATUS2_FORCE_TCP_NOCHECK
 
- HP_STATUS2_JH_SPLIT_EN
 
- HP_STATUS2_MASK_TCP_THRESH
 
- HP_STATUS2_NO_ASSIST
 
- HP_STATUS2_SYN_FLAG
 
- HP_STATUS2_TCP_CHECK
 
- HP_STATUS2_TCP_FLAG_CHECK
 
- HP_STATUS2_TCP_NOCHECK
 
- HP_STATUS_FAILED
 
- HP_STATUS_OK
 
- HP_STATUS_OTHER
 
- HP_SUPR_RM
 
- HP_SW_NAME
 
- HP_SW_PATH_ACTIVE
 
- HP_SW_PATH_PASSIVE
 
- HP_SW_PATH_UNINITIALIZED
 
- HP_SW_RETRIES
 
- HP_SW_TIMEOUT
 
- HP_TCP_THRESH_VAL
 
- HP_TD620_PRODUCT_ID
 
- HP_THERMAL_NUM
 
- HP_THREAD_ACTIVE
 
- HP_THREAD_NONE
 
- HP_THREAD_PARKED
 
- HP_TXH
 
- HP_TXL
 
- HP_TXM
 
- HP_VENDOR_ID
 
- HP_WAIT
 
- HP_WORKAROUND_DEFAULT
 
- HP_ZX1_GART_SIZE
 
- HP_ZX1_IBASE
 
- HP_ZX1_IMASK
 
- HP_ZX1_IOC_OFFSET
 
- HP_ZX1_IOVA_BASE
 
- HP_ZX1_IOVA_SIZE
 
- HP_ZX1_IOVA_TO_PDIR
 
- HP_ZX1_PCOM
 
- HP_ZX1_PDIR_BASE
 
- HP_ZX1_PDIR_VALID_BIT
 
- HP_ZX1_SBA_IOMMU_COOKIE
 
- HP_ZX1_TCNFG
 
- HQ2_MYSTERY_OFFS
 
- HQDA
 
- HQD_N_REGS
 
- HQSEL_BEQ
 
- HQSEL_BKQ
 
- HQSEL_HIQ
 
- HQSEL_MGTQ
 
- HQSEL_VIQ
 
- HQSEL_VOQ
 
- HQVDP_DMEM
 
- HQVDP_FMW_NAME
 
- HQVDP_MBX
 
- HQVDP_MBX_CURRENT_CMD
 
- HQVDP_MBX_GP_STATUS
 
- HQVDP_MBX_INFO_HOST
 
- HQVDP_MBX_INFO_XP70
 
- HQVDP_MBX_IRQ_TO_HOST
 
- HQVDP_MBX_IRQ_TO_XP70
 
- HQVDP_MBX_NEXT_CMD
 
- HQVDP_MBX_SOFT_VSYNC
 
- HQVDP_MBX_STARTUP_CTRL1
 
- HQVDP_MBX_STARTUP_CTRL2
 
- HQVDP_MBX_SW_RESET_CTRL
 
- HQVDP_PMEM
 
- HQVDP_RD_PLUG
 
- HQVDP_RD_PLUG_CONTROL
 
- HQVDP_RD_PLUG_MAX_CHK
 
- HQVDP_RD_PLUG_MAX_MSG
 
- HQVDP_RD_PLUG_MAX_OPC
 
- HQVDP_RD_PLUG_MIN_OPC
 
- HQVDP_RD_PLUG_MIN_SPACE
 
- HQVDP_RD_PLUG_PAGE_SIZE
 
- HQVDP_WR_PLUG
 
- HQVDP_WR_PLUG_CONTROL
 
- HQVDP_WR_PLUG_MAX_CHK
 
- HQVDP_WR_PLUG_MAX_MSG
 
- HQVDP_WR_PLUG_MAX_OPC
 
- HQVDP_WR_PLUG_MIN_OPC
 
- HQVDP_WR_PLUG_MIN_SPACE
 
- HQVDP_WR_PLUG_PAGE_SIZE
 
- HR222_LINE_CAPTURE_LEVEL_MAX
 
- HR222_LINE_CAPTURE_LEVEL_MIN
 
- HR222_LINE_CAPTURE_ZERO_LEVEL
 
- HR222_LINE_PLAYBACK_LEVEL_MAX
 
- HR222_LINE_PLAYBACK_LEVEL_MIN
 
- HR222_LINE_PLAYBACK_ZERO_LEVEL
 
- HR222_MICRO_CAPTURE_LEVEL_MAX
 
- HR222_MICRO_CAPTURE_LEVEL_MIN
 
- HR22_CLOCK_TYPE_AES_1
 
- HR22_CLOCK_TYPE_AES_SYNC
 
- HR22_CLOCK_TYPE_INTERNAL
 
- HR22_CLOCK_TYPE_MAX
 
- HRD_DSAF_4TC_MODE
 
- HRD_DSAF_8TC_MODE
 
- HRD_DSAF_MODE
 
- HRD_DSAF_NO_DSAF_MODE
 
- HREF
 
- HREF_HSIZE_SHIFT
 
- HREF_HSTART_SHIFT
 
- HREF_VSIZE_SHIFT
 
- HREF_VSTART_SHIFT
 
- HREQPERR_F
 
- HREQPERR_S
 
- HREQPERR_V
 
- HREQWRPERR_F
 
- HREQWRPERR_S
 
- HREQWRPERR_V
 
- HREQ_CONFIG_DONE
 
- HREQ_ENABLE
 
- HREQ_EXECUTION_ONGOING
 
- HREQ_FEATURE_NOT_SUPPORTED
 
- HREQ_INTERFACE_TEST
 
- HREQ_INVALID
 
- HREQ_LCB_RESET
 
- HREQ_LOAD_CONFIG
 
- HREQ_NOT_SUPPORTED
 
- HREQ_READ_CONFIG
 
- HREQ_REQUEST_REJECTED
 
- HREQ_SAVE_CONFIG
 
- HREQ_SET_TX_EQ_ABS
 
- HREQ_SET_TX_EQ_REL
 
- HREQ_SUCCESS
 
- HRESP_FROM_NOC_ERR
 
- HRFI_TO_GUEST
 
- HRFI_TO_KERNEL
 
- HRFI_TO_UNKNOWN
 
- HRFI_TO_USER
 
- HRFI_TO_USER_OR_KERNEL
 
- HRIR
 
- HRRQ_ENTRY_SIZE
 
- HRRQ_RESPONSE_BIT
 
- HRRQ_TOGGLE_BIT
 
- HRSPPERR_F
 
- HRSPPERR_S
 
- HRSPPERR_V
 
- HRST
 
- HRST_CRYPTO
 
- HRST_CVBS
 
- HRST_EMMC
 
- HRST_HOST0
 
- HRST_HOST0_ARB
 
- HRST_HOST0_AUX
 
- HRST_I2S0_8CH
 
- HRST_I2S1_2CH
 
- HRST_I2S2_2CH
 
- HRST_IEP
 
- HRST_ISP
 
- HRST_ISP_NIU
 
- HRST_NANDC
 
- HRST_OTG
 
- HRST_PERIPH
 
- HRST_PERIPH_NIU
 
- HRST_RGA
 
- HRST_RKVDEC
 
- HRST_RKVDEC_NIU
 
- HRST_RKVENC
 
- HRST_RKVENC_NIU
 
- HRST_ROM
 
- HRST_SDIO
 
- HRST_SDMMC
 
- HRST_SFC
 
- HRST_SYSBUS
 
- HRST_VIO_NIU
 
- HRST_VIP0
 
- HRST_VIP1
 
- HRST_VIP2
 
- HRST_VIP3
 
- HRST_VOP
 
- HRST_VPU
 
- HRST_VPU_NIU
 
- HRTF_SZ
 
- HRTIMER_ACTIVE_ALL
 
- HRTIMER_ACTIVE_HARD
 
- HRTIMER_ACTIVE_SOFT
 
- HRTIMER_BASE_BOOTTIME
 
- HRTIMER_BASE_BOOTTIME_SOFT
 
- HRTIMER_BASE_MONOTONIC
 
- HRTIMER_BASE_MONOTONIC_SOFT
 
- HRTIMER_BASE_REALTIME
 
- HRTIMER_BASE_REALTIME_SOFT
 
- HRTIMER_BASE_TAI
 
- HRTIMER_BASE_TAI_SOFT
 
- HRTIMER_DEFAULT_SAMPLING_FREQUENCY
 
- HRTIMER_MAX_CLOCK_BASES
 
- HRTIMER_MODE_ABS
 
- HRTIMER_MODE_ABS_HARD
 
- HRTIMER_MODE_ABS_PINNED
 
- HRTIMER_MODE_ABS_PINNED_HARD
 
- HRTIMER_MODE_ABS_PINNED_SOFT
 
- HRTIMER_MODE_ABS_SOFT
 
- HRTIMER_MODE_HARD
 
- HRTIMER_MODE_PINNED
 
- HRTIMER_MODE_REL
 
- HRTIMER_MODE_REL_HARD
 
- HRTIMER_MODE_REL_PINNED
 
- HRTIMER_MODE_REL_PINNED_HARD
 
- HRTIMER_MODE_REL_PINNED_SOFT
 
- HRTIMER_MODE_REL_SOFT
 
- HRTIMER_MODE_SOFT
 
- HRTIMER_NORESTART
 
- HRTIMER_RESTART
 
- HRTIMER_SOFTIRQ
 
- HRTIMER_STATE_ENQUEUED
 
- HRTIMER_STATE_INACTIVE
 
- HRTIM_CK
 
- HRTS0_A_MARK
 
- HRTS0_B_MARK
 
- HRTS0_C_MARK
 
- HRTS0_D_MARK
 
- HRTS0_MARK
 
- HRTS0_N_B_MARK
 
- HRTS0_N_C_MARK
 
- HRTS0_N_D_MARK
 
- HRTS0_N_E_MARK
 
- HRTS0_N_F_MARK
 
- HRTS0_N_MARK
 
- HRTS1_A_MARK
 
- HRTS1_B_MARK
 
- HRTS1_MARK
 
- HRTS1_N_A_MARK
 
- HRTS1_N_B_MARK
 
- HRTS1_N_C_MARK
 
- HRTS1_N_E_MARK
 
- HRTS1_N_MARK
 
- HRTS2_N_B_MARK
 
- HRTS2_N_MARK
 
- HRT_FREQ
 
- HRT_RESERVED1
 
- HRT_RESERVED2
 
- HRW_ARB_BYPASS
 
- HRW_AUD_RUN22
 
- HRW_BAY_DEV_MASK
 
- HRW_BAY_FLOPPY_ENABLE
 
- HRW_BAY_IDE_ENABLE
 
- HRW_BAY_PCI_ENABLE
 
- HRW_BAY_POWER_N
 
- HRW_BAY_RESET_N
 
- HRW_BMAC_IO_ENABLE
 
- HRW_BMAC_RESET
 
- HRW_DEFAULTS
 
- HRW_GPIO_MODEM_RESET
 
- HRW_HOOK_MB_CNT_N
 
- HRW_IDE0_ENABLE
 
- HRW_IDE0_RESET_N
 
- HRW_IDE1_RESET_N
 
- HRW_IOBUS_ENABLE
 
- HRW_MESH_ENABLE
 
- HRW_MFDC_CELL_ENABLE
 
- HRW_PORT_OR_DESK_VIA_N
 
- HRW_PWM_MON_ID_N
 
- HRW_RESET_SCC
 
- HRW_SCCA_IO
 
- HRW_SCCB_IO
 
- HRW_SCC_ENABLE
 
- HRW_SCC_TRANS_EN_N
 
- HRW_SCSI_LINK_MODE
 
- HRW_SLOW_SCC_PCLK
 
- HRW_SOUND_CLK_ENABLE
 
- HRW_SOUND_POWER_N
 
- HRW_SWIM_CLONE_FLOPPY
 
- HRW_SWIM_ENABLE
 
- HRW_USE_MFDC
 
- HRX0_A_MARK
 
- HRX0_B_MARK
 
- HRX0_C_MARK
 
- HRX0_D_MARK
 
- HRX0_E_MARK
 
- HRX0_F_MARK
 
- HRX0_MARK
 
- HRX1_A_MARK
 
- HRX1_B_MARK
 
- HRX1_C_MARK
 
- HRX1_D_MARK
 
- HRX1_MARK
 
- HRX2_B_MARK
 
- HRX2_C_MARK
 
- HRX2_MARK
 
- HRZ_DEV
 
- HRZ_IO_EXTENT
 
- HRZ_MAX_VPI
 
- HRZ_VCC
 
- HR_MAX
 
- HR_MIN
 
- HR_TM27MPD
 
- HR_TMCLKSEL
 
- HR_TMEN
 
- HS
 
- HS200_MODE
 
- HS400_FIXED_CIU_CLK_DIV
 
- HS400_MODE
 
- HSAR_DSP_ADDR_MASK
 
- HSAR_END
 
- HSAR_ERR
 
- HSAR_HOST_ADDR_MASK
 
- HSAR_MEMID_MASK
 
- HSAR_MEMID_OMNI_MEM
 
- HSAR_MEMID_SP_DEBUG
 
- HSAR_MEMID_SP_DMEM0
 
- HSAR_MEMID_SP_DMEM1
 
- HSAR_MEMID_SP_PMEM
 
- HSA_CACHE_TYPE_CPU
 
- HSA_CACHE_TYPE_DATA
 
- HSA_CACHE_TYPE_HSACU
 
- HSA_CACHE_TYPE_INSTRUCTION
 
- HSA_CACHE_TYPE_RESERVED
 
- HSA_CAP_AQL_QUEUE_DOUBLE_MAP
 
- HSA_CAP_ATS_PRESENT
 
- HSA_CAP_DOORBELL_TYPE_1_0
 
- HSA_CAP_DOORBELL_TYPE_2_0
 
- HSA_CAP_DOORBELL_TYPE_PRE_1_0
 
- HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK
 
- HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT
 
- HSA_CAP_HOT_PLUGGABLE
 
- HSA_CAP_MEM_EDCSUPPORTED
 
- HSA_CAP_QUEUE_IDLE_EVENT
 
- HSA_CAP_QUEUE_SIZE_32BIT
 
- HSA_CAP_QUEUE_SIZE_POW2
 
- HSA_CAP_RASEVENTNOTIFY
 
- HSA_CAP_RESERVED
 
- HSA_CAP_SHARED_WITH_GRAPHICS
 
- HSA_CAP_SRAM_EDCSUPPORTED
 
- HSA_CAP_VA_LIMIT
 
- HSA_CAP_WATCH_POINTS_SUPPORTED
 
- HSA_CAP_WATCH_POINTS_TOTALBITS_MASK
 
- HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT
 
- HSA_DBG_MAX_WAVEMODE
 
- HSA_DBG_MAX_WAVEMSG
 
- HSA_DBG_MAX_WAVEOP
 
- HSA_DBG_NUM_WAVEMODE
 
- HSA_DBG_NUM_WAVEMSG
 
- HSA_DBG_NUM_WAVEOP
 
- HSA_DBG_WATCH_ALL
 
- HSA_DBG_WATCH_ATOMIC
 
- HSA_DBG_WATCH_MODE
 
- HSA_DBG_WATCH_NONREAD
 
- HSA_DBG_WATCH_NUM
 
- HSA_DBG_WATCH_READ
 
- HSA_DBG_WATCH_SIZE
 
- HSA_DBG_WAVEMODE
 
- HSA_DBG_WAVEMODE_BROADCAST_PROCESS
 
- HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU
 
- HSA_DBG_WAVEMODE_SINGLE
 
- HSA_DBG_WAVEMSG_AUTO
 
- HSA_DBG_WAVEMSG_ERROR
 
- HSA_DBG_WAVEMSG_TYPE
 
- HSA_DBG_WAVEMSG_USER
 
- HSA_DBG_WAVEOP
 
- HSA_DBG_WAVEOP_DEBUG
 
- HSA_DBG_WAVEOP_HALT
 
- HSA_DBG_WAVEOP_KILL
 
- HSA_DBG_WAVEOP_RESUME
 
- HSA_DBG_WAVEOP_TRAP
 
- HSA_DEVICE
 
- HSA_DEVICE_CPU
 
- HSA_DEVICE_GPU
 
- HSA_EVENTTYPE
 
- HSA_EVENTTYPE_DEBUG_EVENT
 
- HSA_EVENTTYPE_DEVICESTATECHANGE
 
- HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS
 
- HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE
 
- HSA_EVENTTYPE_DEVICESTATUSCHANGE_START
 
- HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP
 
- HSA_EVENTTYPE_HW_EXCEPTION
 
- HSA_EVENTTYPE_MAXID
 
- HSA_EVENTTYPE_NODECHANGE
 
- HSA_EVENTTYPE_NODECHANGE_ADD
 
- HSA_EVENTTYPE_NODECHANGE_FLAGS
 
- HSA_EVENTTYPE_NODECHANGE_REMOVE
 
- HSA_EVENTTYPE_NODECHANGE_SIZE
 
- HSA_EVENTTYPE_PROFILE_EVENT
 
- HSA_EVENTTYPE_QUEUE_EVENT
 
- HSA_EVENTTYPE_SIGNAL
 
- HSA_EVENTTYPE_SYSTEM_EVENT
 
- HSA_EVENTTYPE_TYPE_SIZE
 
- HSA_LEN
 
- HSA_MEM_FLAGS_HOT_PLUGGABLE
 
- HSA_MEM_FLAGS_NON_VOLATILE
 
- HSA_MEM_FLAGS_RESERVED
 
- HSA_MEM_HEAP_TYPE_FB_PRIVATE
 
- HSA_MEM_HEAP_TYPE_FB_PUBLIC
 
- HSA_MEM_HEAP_TYPE_GPU_GDS
 
- HSA_MEM_HEAP_TYPE_GPU_LDS
 
- HSA_MEM_HEAP_TYPE_GPU_SCRATCH
 
- HSA_MEM_HEAP_TYPE_SYSTEM
 
- HSA_PACKET_OVERHEAD
 
- HSA_SOC15_INT_H_INCLUDED
 
- HSB
 
- HSBEGIN
 
- HSC
 
- HSCALER_CTRL
 
- HSCALE_CTRL
 
- HSCALE_EN
 
- HSCALE_LO
 
- HSCIF
 
- HSCIF0_HCTS_N_MARK
 
- HSCIF0_HRTS_N_MARK
 
- HSCIF0_HRX_B_MARK
 
- HSCIF0_HRX_MARK
 
- HSCIF0_HSCK_B_MARK
 
- HSCIF0_HSCK_MARK
 
- HSCIF0_HTX_B_MARK
 
- HSCIF0_HTX_MARK
 
- HSCIF1_HCTS_N_B_MARK
 
- HSCIF1_HCTS_N_MARK
 
- HSCIF1_HRTS_N_B_MARK
 
- HSCIF1_HRTS_N_MARK
 
- HSCIF1_HRX_B_MARK
 
- HSCIF1_HRX_MARK
 
- HSCIF1_HSCK_MARK
 
- HSCIF1_HTX_B_MARK
 
- HSCIF1_HTX_MARK
 
- HSCIF2_HCTS_N_MARK
 
- HSCIF2_HRTS_N_MARK
 
- HSCIF2_HRX_MARK
 
- HSCIF2_HSCK_MARK
 
- HSCIF2_HTX_MARK
 
- HSCIF_SRDE
 
- HSCIF_SRE
 
- HSCIF_SRHP_MASK
 
- HSCIF_SRHP_SHIFT
 
- HSCK0_A_MARK
 
- HSCK0_B_MARK
 
- HSCK0_C_MARK
 
- HSCK0_D_MARK
 
- HSCK0_MARK
 
- HSCK1_A_MARK
 
- HSCK1_B_MARK
 
- HSCK1_C_MARK
 
- HSCK1_E_MARK
 
- HSCK1_MARK
 
- HSCK2_C_MARK
 
- HSCK2_MARK
 
- HSCOEFF0
 
- HSCOEFF1
 
- HSCOEFF2
 
- HSCOEFF3
 
- HSCOEFF4
 
- HSCOEFF5
 
- HSCOEFF6
 
- HSCOEFF7
 
- HSCOEFF8
 
- HSCR0_AME
 
- HSCR0_AbortURn
 
- HSCR0_EFrmURn
 
- HSCR0_HSSP
 
- HSCR0_ITR
 
- HSCR0_LBM
 
- HSCR0_RIE
 
- HSCR0_RXE
 
- HSCR0_TIE
 
- HSCR0_TUS
 
- HSCR0_TXE
 
- HSCR0_UART
 
- HSCR1_AMV
 
- HSCR2_RXP
 
- HSCR2_RcDataH
 
- HSCR2_RcDataL
 
- HSCR2_TXP
 
- HSCR2_TrDataH
 
- HSCR2_TrDataL
 
- HSCTLR_A
 
- HSCTLR_C
 
- HSCTLR_EE
 
- HSCTLR_FI
 
- HSCTLR_I
 
- HSCTLR_M
 
- HSCTLR_MASK
 
- HSCTLR_TE
 
- HSCTLR_WXN
 
- HSCX_VSTR
 
- HSCX__EXA
 
- HSCX__EXB
 
- HSCX__ICA
 
- HSC_ARB_PRIO
 
- HSC_ARB_RR
 
- HSC_BANK_LENGTH
 
- HSC_BASEMINOR
 
- HSC_CH_MASK
 
- HSC_CH_OPEN
 
- HSC_CH_READ
 
- HSC_CH_WLINE
 
- HSC_CH_WRITE
 
- HSC_DEVS
 
- HSC_FLOW_SYNC
 
- HSC_GET_RX
 
- HSC_GET_TX
 
- HSC_HORIZ_SCALER_EN
 
- HSC_ID_BITS
 
- HSC_ID_MASK
 
- HSC_INI_RCV_NUM0
 
- HSC_IO
 
- HSC_IOR
 
- HSC_IOW
 
- HSC_IOWR
 
- HSC_MODE_FRAME
 
- HSC_MODE_STREAM
 
- HSC_MSGS
 
- HSC_PM_DISABLE
 
- HSC_PM_ENABLE
 
- HSC_PORT_ID_BITS
 
- HSC_PORT_ID_MASK
 
- HSC_RESET
 
- HSC_RPT_P0_NUM0
 
- HSC_RX
 
- HSC_RXBREAK
 
- HSC_SEND_BREAK
 
- HSC_SET_PM
 
- HSC_SET_RX
 
- HSC_SET_TX
 
- HSC_TX
 
- HSDEVP_FROM_AP
 
- HSDEV_FROM_AP
 
- HSDEV_FROM_HOST
 
- HSDEV_FROM_HSDEVP
 
- HSDEV_FROM_QC
 
- HSDIV_DISPC
 
- HSDIV_DSI
 
- HSDK_APB_RESET
 
- HSDK_AXI_RESET
 
- HSDK_DMAC_RESET
 
- HSDK_EBI_RESET
 
- HSDK_ETH_RESET
 
- HSDK_GFX_RESET
 
- HSDK_GPIO_INTC
 
- HSDK_HDMI_RESET
 
- HSDK_MAX_RESETS
 
- HSDK_PLL_MAX_LOCK_TIME
 
- HSDK_SDIO_RESET
 
- HSDK_USB_RESET
 
- HSDMA_ALIGN_SIZE
 
- HSDMA_BASE_OFFSET
 
- HSDMA_BT_SIZE_128BYTES
 
- HSDMA_BT_SIZE_16BYTES
 
- HSDMA_BT_SIZE_32BYTES
 
- HSDMA_BT_SIZE_64BYTES
 
- HSDMA_DELAY
 
- HSDMA_DELAY_INIT
 
- HSDMA_DELAY_INT_EN
 
- HSDMA_DELAY_PEND_OFFSET
 
- HSDMA_DELAY_RX_OFFSET
 
- HSDMA_DELAY_TIME_OFFSET
 
- HSDMA_DELAY_TX_OFFSET
 
- HSDMA_DESCS_MASK
 
- HSDMA_DESCS_MAX
 
- HSDMA_DESCS_NUM
 
- HSDMA_DESC_DONE
 
- HSDMA_DESC_LS0
 
- HSDMA_DESC_LS1
 
- HSDMA_DESC_PLEN0
 
- HSDMA_DESC_PLEN1
 
- HSDMA_DESC_TAG
 
- HSDMA_GLO_32B_DESC
 
- HSDMA_GLO_BIG_ENDIAN
 
- HSDMA_GLO_BT_MASK
 
- HSDMA_GLO_BT_SHIFT
 
- HSDMA_GLO_BYTE_SWAP
 
- HSDMA_GLO_CLK_GATE
 
- HSDMA_GLO_DEFAULT
 
- HSDMA_GLO_MULTI_DMA
 
- HSDMA_GLO_RX_BUSY
 
- HSDMA_GLO_RX_DMA
 
- HSDMA_GLO_TWO_BUF
 
- HSDMA_GLO_TX_2B_OFFSET
 
- HSDMA_GLO_TX_BUSY
 
- HSDMA_GLO_TX_DMA
 
- HSDMA_GLO_TX_DONE
 
- HSDMA_INFO_BASE_MASK
 
- HSDMA_INFO_BASE_SHIFT
 
- HSDMA_INFO_INDEX_MASK
 
- HSDMA_INFO_INDEX_SHIFT
 
- HSDMA_INFO_RX_MASK
 
- HSDMA_INFO_RX_SHIFT
 
- HSDMA_INFO_TX_MASK
 
- HSDMA_INFO_TX_SHIFT
 
- HSDMA_INT_DELAY_RX_COH
 
- HSDMA_INT_DELAY_RX_INT
 
- HSDMA_INT_DELAY_TX_COH
 
- HSDMA_INT_DELAY_TX_INT
 
- HSDMA_INT_RX_MASK
 
- HSDMA_INT_RX_Q0
 
- HSDMA_INT_RX_SHIFT
 
- HSDMA_INT_TX_MASK
 
- HSDMA_INT_TX_Q0
 
- HSDMA_INT_TX_SHIFT
 
- HSDMA_MAX_PLEN
 
- HSDMA_NEXT_DESC
 
- HSDMA_PLEN_MASK
 
- HSDMA_REG_DELAY_INT
 
- HSDMA_REG_FREEQ_THRES
 
- HSDMA_REG_GLO_CFG
 
- HSDMA_REG_INFO
 
- HSDMA_REG_INT_MASK
 
- HSDMA_REG_INT_STATUS
 
- HSDMA_REG_RST_CFG
 
- HSDMA_REG_RX_BASE
 
- HSDMA_REG_RX_CNT
 
- HSDMA_REG_RX_CRX
 
- HSDMA_REG_RX_DRX
 
- HSDMA_REG_SCH_Q01
 
- HSDMA_REG_SCH_Q23
 
- HSDMA_REG_TX_BASE
 
- HSDMA_REG_TX_CNT
 
- HSDMA_REG_TX_CTX
 
- HSDMA_REG_TX_DTX
 
- HSDMA_RST_RX_SHIFT
 
- HSDMA_RST_TX_SHIFT
 
- HSDR_CRE
 
- HSDR_DATA
 
- HSDR_EOF
 
- HSDR_ROR
 
- HSD_ERR_SHIFT
 
- HSE
 
- HSEM
 
- HSEM_CK
 
- HSEM_CTRL_REG
 
- HSEM_ICRALL
 
- HSEM_MASTER_ID
 
- HSEM_PROTOCOL_1
 
- HSEM_R
 
- HSEM_REGISTER_OFFSET
 
- HSEND
 
- HSE_1M
 
- HSE_CK
 
- HSFREQRANGE_SEL
 
- HSFSTS_CTL
 
- HSFSTS_CTL_AEL
 
- HSFSTS_CTL_FCERR
 
- HSFSTS_CTL_FCYCLE_ERASE
 
- HSFSTS_CTL_FCYCLE_ERASE_64K
 
- HSFSTS_CTL_FCYCLE_MASK
 
- HSFSTS_CTL_FCYCLE_RDID
 
- HSFSTS_CTL_FCYCLE_RDSR
 
- HSFSTS_CTL_FCYCLE_READ
 
- HSFSTS_CTL_FCYCLE_SHIFT
 
- HSFSTS_CTL_FCYCLE_WRITE
 
- HSFSTS_CTL_FCYCLE_WRSR
 
- HSFSTS_CTL_FDBC_MASK
 
- HSFSTS_CTL_FDBC_SHIFT
 
- HSFSTS_CTL_FDONE
 
- HSFSTS_CTL_FDV
 
- HSFSTS_CTL_FGO
 
- HSFSTS_CTL_FLOCKDN
 
- HSFSTS_CTL_FSMIE
 
- HSFSTS_CTL_SCIP
 
- HSHARED
 
- HSHK_CFG_OFFSET
 
- HSHK_CFG_RATE
 
- HSHK_CFG_WIDE_XFR
 
- HSI2C_10BIT_ADDR_MODE
 
- HSI2C_ADDR
 
- HSI2C_AUTO_CONF
 
- HSI2C_AUTO_MODE
 
- HSI2C_CLK_CTL
 
- HSI2C_CLK_SLOT
 
- HSI2C_CMD_READ_DATA
 
- HSI2C_CMD_SEND_STOP
 
- HSI2C_CONF
 
- HSI2C_CTL
 
- HSI2C_ERR_STATUS
 
- HSI2C_FIFO_CTL
 
- HSI2C_FIFO_STATUS
 
- HSI2C_FS_TX_CLOCK
 
- HSI2C_FUNC_MODE_I2C
 
- HSI2C_HS_MODE
 
- HSI2C_HS_TX_CLOCK
 
- HSI2C_INT_ENABLE
 
- HSI2C_INT_I2C
 
- HSI2C_INT_I2C_TRANS
 
- HSI2C_INT_NO_DEV
 
- HSI2C_INT_NO_DEV_ACK
 
- HSI2C_INT_RX_ALMOSTFULL
 
- HSI2C_INT_RX_ALMOSTFULL_EN
 
- HSI2C_INT_RX_OVERRUN
 
- HSI2C_INT_RX_UNDERRUN
 
- HSI2C_INT_STATUS
 
- HSI2C_INT_TIMEOUT
 
- HSI2C_INT_TRAILING
 
- HSI2C_INT_TRAILING_EN
 
- HSI2C_INT_TRANS_ABORT
 
- HSI2C_INT_TRANS_DONE
 
- HSI2C_INT_TX_ALMOSTEMPTY
 
- HSI2C_INT_TX_ALMOSTEMPTY_EN
 
- HSI2C_INT_TX_OVERRUN
 
- HSI2C_INT_TX_UNDERRUN
 
- HSI2C_MANUAL_CMD
 
- HSI2C_MASTER
 
- HSI2C_MASTER_BUSY
 
- HSI2C_MASTER_ID
 
- HSI2C_MASTER_RUN
 
- HSI2C_MASTER_ST_ADDR0
 
- HSI2C_MASTER_ST_ADDR1
 
- HSI2C_MASTER_ST_ADDR2
 
- HSI2C_MASTER_ST_ADDR_SR
 
- HSI2C_MASTER_ST_IDLE
 
- HSI2C_MASTER_ST_LOSE
 
- HSI2C_MASTER_ST_MASK
 
- HSI2C_MASTER_ST_MASTER_ID
 
- HSI2C_MASTER_ST_NO_ACK
 
- HSI2C_MASTER_ST_READ
 
- HSI2C_MASTER_ST_RESTART
 
- HSI2C_MASTER_ST_START
 
- HSI2C_MASTER_ST_STOP
 
- HSI2C_MASTER_ST_WAIT
 
- HSI2C_MASTER_ST_WAIT_CMD
 
- HSI2C_MASTER_ST_WRITE
 
- HSI2C_NO_DEV
 
- HSI2C_NO_DEV_ACK
 
- HSI2C_READ_WRITE
 
- HSI2C_RXCHON
 
- HSI2C_RXFIFO_EN
 
- HSI2C_RXFIFO_TRIGGER_LEVEL
 
- HSI2C_RX_DATA
 
- HSI2C_RX_FIFO_EMPTY
 
- HSI2C_RX_FIFO_FULL
 
- HSI2C_RX_FIFO_LVL
 
- HSI2C_SLAVE_BUSY
 
- HSI2C_SLV_ADDR_MAS
 
- HSI2C_SLV_ADDR_SLV
 
- HSI2C_STOP_AFTER_TRANS
 
- HSI2C_SW_RST
 
- HSI2C_TIMEOUT
 
- HSI2C_TIMEOUT_AUTO
 
- HSI2C_TIMEOUT_EN
 
- HSI2C_TIMEOUT_MASK
 
- HSI2C_TIMING_FS1
 
- HSI2C_TIMING_FS2
 
- HSI2C_TIMING_FS3
 
- HSI2C_TIMING_HS1
 
- HSI2C_TIMING_HS2
 
- HSI2C_TIMING_HS3
 
- HSI2C_TIMING_SLA
 
- HSI2C_TRAILIG_CTL
 
- HSI2C_TRAILING_COUNT
 
- HSI2C_TRANS_ABORT
 
- HSI2C_TRANS_DONE
 
- HSI2C_TRANS_STATUS
 
- HSI2C_TXCHON
 
- HSI2C_TXFIFO_EN
 
- HSI2C_TXFIFO_TRIGGER_LEVEL
 
- HSI2C_TX_DATA
 
- HSI2C_TX_FIFO_EMPTY
 
- HSI2C_TX_FIFO_FULL
 
- HSI2C_TX_FIFO_LVL
 
- HSIC_CONFIG
 
- HSIC_CTRL
 
- HSIC_CTRL_HSIC_ENABLE
 
- HSIC_CTRL_PLL_BYPASS
 
- HSIC_INT
 
- HSIC_INT_CONNECT
 
- HSIC_INT_CONNECT_INT_EN
 
- HSIC_INT_CORE
 
- HSIC_INT_CORE_INT_EN
 
- HSIC_INT_HS_READY
 
- HSIC_INT_READY_INT_EN
 
- HSIC_PAD_CTRL
 
- HSIC_PD_RX_DATA0
 
- HSIC_PD_RX_STROBE
 
- HSIC_PD_TRK
 
- HSIC_PD_TX_DATA0
 
- HSIC_PD_TX_STROBE
 
- HSIC_PD_ZI_DATA0
 
- HSIC_PD_ZI_STROBE
 
- HSIC_PINGROUP
 
- HSIC_PORT_MASK
 
- HSIC_PORT_SHIFT
 
- HSIC_RPD_DATA0
 
- HSIC_RPD_STROBE
 
- HSIC_RPU_DATA0
 
- HSIC_RPU_STROBE
 
- HSIC_TRK_DONE_RESET_TIMER
 
- HSIC_TRK_START_TIMER
 
- HSIC_TSTCLK0
 
- HSIC_TSTCLK1
 
- HSIC_USB_CLK_PHY
 
- HSIC_USB_CLK_PMU
 
- HSIC_USB_CTRL
 
- HSIC_USB_CTRL_CLKEN
 
- HSIMR_GPIO12_0_INT_EN
 
- HSIMR_GPIO9_INT_EN
 
- HSIMR_PDN_INT_EN
 
- HSIMR_RON_INT_EN
 
- HSIMR_SPS_OCP_INT_EN
 
- HSIO
 
- HSIO_CLK_CFG
 
- HSIO_CLK_CFG_CLKDIV_PHY
 
- HSIO_CLK_CFG_CLKDIV_PHY_DIS
 
- HSIO_CLK_CFG_CLKDIV_PHY_M
 
- HSIO_CLK_CFG_CLKDIV_PHY_X
 
- HSIO_HW_CFG
 
- HSIO_HW_CFG_DEV1G_4_MODE
 
- HSIO_HW_CFG_DEV1G_5_MODE
 
- HSIO_HW_CFG_DEV1G_6_MODE
 
- HSIO_HW_CFG_DEV1G_9_MODE
 
- HSIO_HW_CFG_DEV2G5_10_MODE
 
- HSIO_HW_CFG_PCIE_ENA
 
- HSIO_HW_CFG_QSGMII_ENA
 
- HSIO_HW_QSGMII_CFG
 
- HSIO_HW_QSGMII_CFG_E_DET_ENA
 
- HSIO_HW_QSGMII_CFG_FLIP_LANES
 
- HSIO_HW_QSGMII_CFG_SHYST_DIS
 
- HSIO_HW_QSGMII_CFG_USE_I1_ENA
 
- HSIO_HW_QSGMII_STAT
 
- HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS
 
- HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_M
 
- HSIO_HW_QSGMII_STAT_DELAY_VAR_X200PS_X
 
- HSIO_HW_QSGMII_STAT_SYNC
 
- HSIO_MCB_S1G_ADDR_CFG
 
- HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR
 
- HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR_M
 
- HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT
 
- HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT
 
- HSIO_MCB_S6G_ADDR_CFG
 
- HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR
 
- HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR_M
 
- HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT
 
- HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT
 
- HSIO_PLL5G_BIST_CFG0
 
- HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE
 
- HSIO_PLL5G_BIST_CFG0_PLLB_DIV_FACTOR_PRE_M
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_M
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_REPEAT_X
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_M
 
- HSIO_PLL5G_BIST_CFG0_PLLB_LOCK_UNCERT_X
 
- HSIO_PLL5G_BIST_CFG0_PLLB_MEAS_MODE
 
- HSIO_PLL5G_BIST_CFG0_PLLB_START_BIST
 
- HSIO_PLL5G_BIST_CFG1
 
- HSIO_PLL5G_BIST_CFG2
 
- HSIO_PLL5G_BIST_STAT0
 
- HSIO_PLL5G_BIST_STAT0_PLLB_BUSY
 
- HSIO_PLL5G_BIST_STAT0_PLLB_DONE_N
 
- HSIO_PLL5G_BIST_STAT0_PLLB_FAIL
 
- HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT
 
- HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_M
 
- HSIO_PLL5G_BIST_STAT0_PLLB_FSM_STAT_X
 
- HSIO_PLL5G_BIST_STAT1
 
- HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT
 
- HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_M
 
- HSIO_PLL5G_BIST_STAT1_PLLB_CNT_OUT_X
 
- HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF
 
- HSIO_PLL5G_BIST_STAT1_PLLB_CNT_REF_DIFF_M
 
- HSIO_PLL5G_CFG0
 
- HSIO_PLL5G_CFG0_CORE_CLK_DIV
 
- HSIO_PLL5G_CFG0_CORE_CLK_DIV_M
 
- HSIO_PLL5G_CFG0_CPU_CLK_DIV
 
- HSIO_PLL5G_CFG0_CPU_CLK_DIV_M
 
- HSIO_PLL5G_CFG0_CPU_CLK_DIV_X
 
- HSIO_PLL5G_CFG0_DIV4
 
- HSIO_PLL5G_CFG0_ENA_BIAS
 
- HSIO_PLL5G_CFG0_ENA_CLKTREE
 
- HSIO_PLL5G_CFG0_ENA_CP1
 
- HSIO_PLL5G_CFG0_ENA_LANE
 
- HSIO_PLL5G_CFG0_ENA_LOCK_FINE
 
- HSIO_PLL5G_CFG0_ENA_ROT
 
- HSIO_PLL5G_CFG0_ENA_VCO_BUF
 
- HSIO_PLL5G_CFG0_ENA_VCO_CONTRH
 
- HSIO_PLL5G_CFG0_LOOP_BW_RES
 
- HSIO_PLL5G_CFG0_LOOP_BW_RES_M
 
- HSIO_PLL5G_CFG0_LOOP_BW_RES_X
 
- HSIO_PLL5G_CFG0_SELBGV820
 
- HSIO_PLL5G_CFG0_SELBGV820_M
 
- HSIO_PLL5G_CFG0_SELBGV820_X
 
- HSIO_PLL5G_CFG0_SELCPI
 
- HSIO_PLL5G_CFG0_SELCPI_M
 
- HSIO_PLL5G_CFG0_SELCPI_X
 
- HSIO_PLL5G_CFG1
 
- HSIO_PLL5G_CFG1_ENA_DIRECT
 
- HSIO_PLL5G_CFG1_FORCE_SET_ENA
 
- HSIO_PLL5G_CFG1_HALF_RATE
 
- HSIO_PLL5G_CFG1_OUT_OF_RANGE_RECAL_ENA
 
- HSIO_PLL5G_CFG1_PWD_RX
 
- HSIO_PLL5G_CFG1_PWD_TX
 
- HSIO_PLL5G_CFG1_QUARTER_RATE
 
- HSIO_PLL5G_CFG1_RC_CTRL_DATA
 
- HSIO_PLL5G_CFG1_RC_CTRL_DATA_M
 
- HSIO_PLL5G_CFG1_RC_CTRL_DATA_X
 
- HSIO_PLL5G_CFG1_RC_ENABLE
 
- HSIO_PLL5G_CFG1_READBACK_DATA_SEL
 
- HSIO_PLL5G_CFG1_ROT_DIR
 
- HSIO_PLL5G_CFG1_ROT_SPEED
 
- HSIO_PLL5G_CFG2
 
- HSIO_PLL5G_CFG2_AMPC_SEL
 
- HSIO_PLL5G_CFG2_AMPC_SEL_M
 
- HSIO_PLL5G_CFG2_AMPC_SEL_X
 
- HSIO_PLL5G_CFG2_DISABLE_FSM
 
- HSIO_PLL5G_CFG2_DISABLE_FSM_POR
 
- HSIO_PLL5G_CFG2_ENA_AMPCTRL
 
- HSIO_PLL5G_CFG2_ENA_AMP_CTRL_FORCE
 
- HSIO_PLL5G_CFG2_ENA_CLK_BYPASS
 
- HSIO_PLL5G_CFG2_ENA_CLK_BYPASS1
 
- HSIO_PLL5G_CFG2_ENA_CP2
 
- HSIO_PLL5G_CFG2_ENA_FBTESTOUT
 
- HSIO_PLL5G_CFG2_ENA_GAIN_TEST
 
- HSIO_PLL5G_CFG2_ENA_PFD_IN_FLIP
 
- HSIO_PLL5G_CFG2_ENA_RCPLL
 
- HSIO_PLL5G_CFG2_ENA_TEST_MODE
 
- HSIO_PLL5G_CFG2_ENA_VCO_NREF_TESTOUT
 
- HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET
 
- HSIO_PLL5G_CFG2_EN_RESET_LIM_DET
 
- HSIO_PLL5G_CFG2_EN_RESET_OVERRUN
 
- HSIO_PLL5G_CFG2_FRC_FSM_POR
 
- HSIO_PLL5G_CFG2_GAIN_TEST
 
- HSIO_PLL5G_CFG2_GAIN_TEST_M
 
- HSIO_PLL5G_CFG2_GAIN_TEST_X
 
- HSIO_PLL5G_CFG2_PWD_AMPCTRL_N
 
- HSIO_PLL5G_CFG3
 
- HSIO_PLL5G_CFG3_ENA_ANA_TEST_OUT
 
- HSIO_PLL5G_CFG3_ENA_TEST_OUT
 
- HSIO_PLL5G_CFG3_FBDIVSEL
 
- HSIO_PLL5G_CFG3_FBDIVSEL_M
 
- HSIO_PLL5G_CFG3_FBDIVSEL_TST_ENA
 
- HSIO_PLL5G_CFG3_FORCE_CP
 
- HSIO_PLL5G_CFG3_FORCE_ENA
 
- HSIO_PLL5G_CFG3_FORCE_HI
 
- HSIO_PLL5G_CFG3_FORCE_LO
 
- HSIO_PLL5G_CFG3_FORCE_VCO_CONTRH
 
- HSIO_PLL5G_CFG3_RST_FB_N
 
- HSIO_PLL5G_CFG3_SEL_CML_CMOS_PFD
 
- HSIO_PLL5G_CFG3_SEL_FBDCLK
 
- HSIO_PLL5G_CFG3_TESTOUT_SEL
 
- HSIO_PLL5G_CFG3_TESTOUT_SEL_M
 
- HSIO_PLL5G_CFG3_TESTOUT_SEL_X
 
- HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL
 
- HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_M
 
- HSIO_PLL5G_CFG3_TEST_ANA_OUT_SEL_X
 
- HSIO_PLL5G_CFG4
 
- HSIO_PLL5G_CFG4_IB_BIAS_CTRL
 
- HSIO_PLL5G_CFG4_IB_BIAS_CTRL_M
 
- HSIO_PLL5G_CFG4_IB_BIAS_CTRL_X
 
- HSIO_PLL5G_CFG4_IB_CTRL
 
- HSIO_PLL5G_CFG4_IB_CTRL_M
 
- HSIO_PLL5G_CFG5
 
- HSIO_PLL5G_CFG5_OB_BIAS_CTRL
 
- HSIO_PLL5G_CFG5_OB_BIAS_CTRL_M
 
- HSIO_PLL5G_CFG5_OB_BIAS_CTRL_X
 
- HSIO_PLL5G_CFG5_OB_CTRL
 
- HSIO_PLL5G_CFG5_OB_CTRL_M
 
- HSIO_PLL5G_CFG6
 
- HSIO_PLL5G_CFG6_DDR_CLK_DIV
 
- HSIO_PLL5G_CFG6_DDR_CLK_DIV_M
 
- HSIO_PLL5G_CFG6_DIV125REF_SEL
 
- HSIO_PLL5G_CFG6_DIV125REF_SEL_M
 
- HSIO_PLL5G_CFG6_DIV125REF_SEL_X
 
- HSIO_PLL5G_CFG6_ENA_FBCLKC2
 
- HSIO_PLL5G_CFG6_ENA_REFCLKC2
 
- HSIO_PLL5G_CFG6_POR_DEL_SEL
 
- HSIO_PLL5G_CFG6_POR_DEL_SEL_M
 
- HSIO_PLL5G_CFG6_POR_DEL_SEL_X
 
- HSIO_PLL5G_CFG6_REFCLK_SEL
 
- HSIO_PLL5G_CFG6_REFCLK_SEL_M
 
- HSIO_PLL5G_CFG6_REFCLK_SEL_SRC
 
- HSIO_PLL5G_CFG6_REFCLK_SEL_X
 
- HSIO_PLL5G_CFG6_REFCLK_SRC
 
- HSIO_PLL5G_STATUS0
 
- HSIO_PLL5G_STATUS0_CALIBRATION_DONE
 
- HSIO_PLL5G_STATUS0_CALIBRATION_ERR
 
- HSIO_PLL5G_STATUS0_LOCK_STATUS
 
- HSIO_PLL5G_STATUS0_OUT_OF_RANGE_ERR
 
- HSIO_PLL5G_STATUS0_RANGE_LIM
 
- HSIO_PLL5G_STATUS0_READBACK_DATA
 
- HSIO_PLL5G_STATUS0_READBACK_DATA_M
 
- HSIO_PLL5G_STATUS0_READBACK_DATA_X
 
- HSIO_PLL5G_STATUS1
 
- HSIO_PLL5G_STATUS1_FBCNT_DIF
 
- HSIO_PLL5G_STATUS1_FBCNT_DIF_M
 
- HSIO_PLL5G_STATUS1_FBCNT_DIF_X
 
- HSIO_PLL5G_STATUS1_FSM_LOCK
 
- HSIO_PLL5G_STATUS1_FSM_STAT
 
- HSIO_PLL5G_STATUS1_FSM_STAT_M
 
- HSIO_PLL5G_STATUS1_FSM_STAT_X
 
- HSIO_PLL5G_STATUS1_GAIN_STAT
 
- HSIO_PLL5G_STATUS1_GAIN_STAT_M
 
- HSIO_PLL5G_STATUS1_GAIN_STAT_X
 
- HSIO_PLL5G_STATUS1_SIG_DEL
 
- HSIO_PLL5G_STATUS1_SIG_DEL_M
 
- HSIO_PLL5G_STATUS1_SIG_DEL_X
 
- HSIO_RCOMP_CFG0
 
- HSIO_RCOMP_CFG0_FORCE_ENA
 
- HSIO_RCOMP_CFG0_MODE_SEL
 
- HSIO_RCOMP_CFG0_MODE_SEL_M
 
- HSIO_RCOMP_CFG0_MODE_SEL_X
 
- HSIO_RCOMP_CFG0_PWD_ENA
 
- HSIO_RCOMP_CFG0_RCOMP_VAL
 
- HSIO_RCOMP_CFG0_RCOMP_VAL_M
 
- HSIO_RCOMP_CFG0_RUN_CAL
 
- HSIO_RCOMP_CFG0_SPEED_SEL
 
- HSIO_RCOMP_CFG0_SPEED_SEL_M
 
- HSIO_RCOMP_CFG0_SPEED_SEL_X
 
- HSIO_RCOMP_STATUS
 
- HSIO_RCOMP_STATUS_BUSY
 
- HSIO_RCOMP_STATUS_DELTA_ALERT
 
- HSIO_RCOMP_STATUS_RCOMP
 
- HSIO_RCOMP_STATUS_RCOMP_M
 
- HSIO_S1G_COMMON_CFG
 
- HSIO_S1G_COMMON_CFG_ENA_DIRECT
 
- HSIO_S1G_COMMON_CFG_ENA_ELOOP
 
- HSIO_S1G_COMMON_CFG_ENA_FLOOP
 
- HSIO_S1G_COMMON_CFG_ENA_ILOOP
 
- HSIO_S1G_COMMON_CFG_ENA_LANE
 
- HSIO_S1G_COMMON_CFG_ENA_PLOOP
 
- HSIO_S1G_COMMON_CFG_HRATE
 
- HSIO_S1G_COMMON_CFG_IF_MODE
 
- HSIO_S1G_COMMON_CFG_LANE_CTRL
 
- HSIO_S1G_COMMON_CFG_LANE_CTRL_M
 
- HSIO_S1G_COMMON_CFG_LANE_CTRL_X
 
- HSIO_S1G_COMMON_CFG_PWD_RX
 
- HSIO_S1G_COMMON_CFG_PWD_TX
 
- HSIO_S1G_COMMON_CFG_SE_AUTO_SQUELCH_ENA
 
- HSIO_S1G_COMMON_CFG_SYS_RST
 
- HSIO_S1G_DES_CFG
 
- HSIO_S1G_DES_CFG_DES_BW_ANA
 
- HSIO_S1G_DES_CFG_DES_BW_ANA_M
 
- HSIO_S1G_DES_CFG_DES_BW_ANA_X
 
- HSIO_S1G_DES_CFG_DES_BW_HYST
 
- HSIO_S1G_DES_CFG_DES_BW_HYST_M
 
- HSIO_S1G_DES_CFG_DES_BW_HYST_X
 
- HSIO_S1G_DES_CFG_DES_CPMD_SEL
 
- HSIO_S1G_DES_CFG_DES_CPMD_SEL_M
 
- HSIO_S1G_DES_CFG_DES_CPMD_SEL_X
 
- HSIO_S1G_DES_CFG_DES_MBTR_CTRL
 
- HSIO_S1G_DES_CFG_DES_MBTR_CTRL_M
 
- HSIO_S1G_DES_CFG_DES_MBTR_CTRL_X
 
- HSIO_S1G_DES_CFG_DES_PHS_CTRL
 
- HSIO_S1G_DES_CFG_DES_PHS_CTRL_M
 
- HSIO_S1G_DES_CFG_DES_PHS_CTRL_X
 
- HSIO_S1G_DES_CFG_DES_SWAP_ANA
 
- HSIO_S1G_DES_CFG_DES_SWAP_HYST
 
- HSIO_S1G_DFT_CFG0
 
- HSIO_S1G_DFT_CFG0_INV_DIS
 
- HSIO_S1G_DFT_CFG0_LAZYBIT
 
- HSIO_S1G_DFT_CFG0_PRBS_SEL
 
- HSIO_S1G_DFT_CFG0_PRBS_SEL_M
 
- HSIO_S1G_DFT_CFG0_PRBS_SEL_X
 
- HSIO_S1G_DFT_CFG0_RX_DFT_ENA
 
- HSIO_S1G_DFT_CFG0_RX_PDSENS_ENA
 
- HSIO_S1G_DFT_CFG0_RX_PHS_CORR_DIS
 
- HSIO_S1G_DFT_CFG0_TEST_MODE
 
- HSIO_S1G_DFT_CFG0_TEST_MODE_M
 
- HSIO_S1G_DFT_CFG0_TEST_MODE_X
 
- HSIO_S1G_DFT_CFG0_TX_DFT_ENA
 
- HSIO_S1G_DFT_CFG1
 
- HSIO_S1G_DFT_CFG1_TX_FREQOFF_DIR
 
- HSIO_S1G_DFT_CFG1_TX_FREQOFF_ENA
 
- HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL
 
- HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_M
 
- HSIO_S1G_DFT_CFG1_TX_JITTER_AMPL_X
 
- HSIO_S1G_DFT_CFG1_TX_JI_ENA
 
- HSIO_S1G_DFT_CFG1_TX_STEP_FREQ
 
- HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_M
 
- HSIO_S1G_DFT_CFG1_TX_STEP_FREQ_X
 
- HSIO_S1G_DFT_CFG1_TX_WAVEFORM_SEL
 
- HSIO_S1G_DFT_CFG2
 
- HSIO_S1G_DFT_CFG2_RX_FREQOFF_DIR
 
- HSIO_S1G_DFT_CFG2_RX_FREQOFF_ENA
 
- HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL
 
- HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_M
 
- HSIO_S1G_DFT_CFG2_RX_JITTER_AMPL_X
 
- HSIO_S1G_DFT_CFG2_RX_JI_ENA
 
- HSIO_S1G_DFT_CFG2_RX_STEP_FREQ
 
- HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_M
 
- HSIO_S1G_DFT_CFG2_RX_STEP_FREQ_X
 
- HSIO_S1G_DFT_CFG2_RX_WAVEFORM_SEL
 
- HSIO_S1G_DFT_STATUS
 
- HSIO_S1G_DFT_STATUS_BIST_ACTIVE
 
- HSIO_S1G_DFT_STATUS_BIST_COMPLETE_N
 
- HSIO_S1G_DFT_STATUS_BIST_ERROR
 
- HSIO_S1G_DFT_STATUS_BIST_NOSYNC
 
- HSIO_S1G_DFT_STATUS_PLL_BIST_FAILED
 
- HSIO_S1G_DFT_STATUS_PLL_BIST_NOT_DONE
 
- HSIO_S1G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR
 
- HSIO_S1G_IB_CFG
 
- HSIO_S1G_IB_CFG_ACJTAG_HYST
 
- HSIO_S1G_IB_CFG_ACJTAG_HYST_M
 
- HSIO_S1G_IB_CFG_ACJTAG_HYST_X
 
- HSIO_S1G_IB_CFG_IB_DET_LEV
 
- HSIO_S1G_IB_CFG_IB_DET_LEV_M
 
- HSIO_S1G_IB_CFG_IB_DET_LEV_X
 
- HSIO_S1G_IB_CFG_IB_ENA_CMV_TERM
 
- HSIO_S1G_IB_CFG_IB_ENA_DC_COUPLING
 
- HSIO_S1G_IB_CFG_IB_ENA_DETLEV
 
- HSIO_S1G_IB_CFG_IB_ENA_HYST
 
- HSIO_S1G_IB_CFG_IB_ENA_OFFSET_COMP
 
- HSIO_S1G_IB_CFG_IB_EQ_GAIN
 
- HSIO_S1G_IB_CFG_IB_EQ_GAIN_M
 
- HSIO_S1G_IB_CFG_IB_EQ_GAIN_X
 
- HSIO_S1G_IB_CFG_IB_FX100_ENA
 
- HSIO_S1G_IB_CFG_IB_HYST_LEV
 
- HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL
 
- HSIO_S1G_IB_CFG_IB_RESISTOR_CTRL_M
 
- HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ
 
- HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_M
 
- HSIO_S1G_IB_CFG_IB_SEL_CORNER_FREQ_X
 
- HSIO_S1G_MISC_CFG
 
- HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA
 
- HSIO_S1G_MISC_CFG_DES_100FX_CPMD_MODE
 
- HSIO_S1G_MISC_CFG_DES_100FX_CPMD_SWAP
 
- HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE
 
- HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_M
 
- HSIO_S1G_MISC_CFG_DES_100FX_KICK_MODE_X
 
- HSIO_S1G_MISC_CFG_LANE_RST
 
- HSIO_S1G_MISC_CFG_RX_DATA_INV_ENA
 
- HSIO_S1G_MISC_CFG_RX_LPI_MODE_ENA
 
- HSIO_S1G_MISC_CFG_TX_DATA_INV_ENA
 
- HSIO_S1G_MISC_CFG_TX_LPI_MODE_ENA
 
- HSIO_S1G_MISC_STATUS
 
- HSIO_S1G_MISC_STATUS_DES_100FX_PHASE_SEL
 
- HSIO_S1G_OB_CFG
 
- HSIO_S1G_OB_CFG_OB_AMP_CTRL
 
- HSIO_S1G_OB_CFG_OB_AMP_CTRL_M
 
- HSIO_S1G_OB_CFG_OB_AMP_CTRL_X
 
- HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL
 
- HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_M
 
- HSIO_S1G_OB_CFG_OB_CMM_BIAS_CTRL_X
 
- HSIO_S1G_OB_CFG_OB_DIS_VCM_CTRL
 
- HSIO_S1G_OB_CFG_OB_EN_MEAS_VREG
 
- HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL
 
- HSIO_S1G_OB_CFG_OB_RESISTOR_CTRL_M
 
- HSIO_S1G_OB_CFG_OB_SLP
 
- HSIO_S1G_OB_CFG_OB_SLP_M
 
- HSIO_S1G_OB_CFG_OB_SLP_X
 
- HSIO_S1G_OB_CFG_OB_VCM_CTRL
 
- HSIO_S1G_OB_CFG_OB_VCM_CTRL_M
 
- HSIO_S1G_OB_CFG_OB_VCM_CTRL_X
 
- HSIO_S1G_PLL_CFG
 
- HSIO_S1G_PLL_CFG_PLL_ENA_FB_DIV2
 
- HSIO_S1G_PLL_CFG_PLL_ENA_RC_DIV2
 
- HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA
 
- HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M
 
- HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_X
 
- HSIO_S1G_PLL_CFG_PLL_FSM_ENA
 
- HSIO_S1G_PLL_CFG_PLL_FSM_FORCE_SET_ENA
 
- HSIO_S1G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA
 
- HSIO_S1G_PLL_CFG_PLL_RB_DATA_SEL
 
- HSIO_S1G_PLL_STATUS
 
- HSIO_S1G_PLL_STATUS_PLL_CAL_ERR
 
- HSIO_S1G_PLL_STATUS_PLL_CAL_NOT_DONE
 
- HSIO_S1G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR
 
- HSIO_S1G_PLL_STATUS_PLL_RB_DATA
 
- HSIO_S1G_PLL_STATUS_PLL_RB_DATA_M
 
- HSIO_S1G_RC_PLL_BIST_CFG
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_ENA
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW
 
- HSIO_S1G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M
 
- HSIO_S1G_SER_CFG
 
- HSIO_S1G_SER_CFG_SER_ALISEL
 
- HSIO_S1G_SER_CFG_SER_ALISEL_M
 
- HSIO_S1G_SER_CFG_SER_ALISEL_X
 
- HSIO_S1G_SER_CFG_SER_BIG_WIN
 
- HSIO_S1G_SER_CFG_SER_CPMD_SEL
 
- HSIO_S1G_SER_CFG_SER_DEEMPH
 
- HSIO_S1G_SER_CFG_SER_ENALI
 
- HSIO_S1G_SER_CFG_SER_ENHYS
 
- HSIO_S1G_SER_CFG_SER_EN_WIN
 
- HSIO_S1G_SER_CFG_SER_IDLE
 
- HSIO_S1G_SER_CFG_SER_SWAP_CPMD
 
- HSIO_S1G_TP_CFG
 
- HSIO_S6G_ACJTAG_CFG
 
- HSIO_S6G_ACJTAG_CFG_ACJTAG_ENA
 
- HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_CLK
 
- HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_N
 
- HSIO_S6G_ACJTAG_CFG_ACJTAG_INIT_DATA_P
 
- HSIO_S6G_ACJTAG_CFG_JTAG_CTRL_ENA
 
- HSIO_S6G_ACJTAG_CFG_OB_DIRECT
 
- HSIO_S6G_ACJTAG_STATUS
 
- HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_N
 
- HSIO_S6G_ACJTAG_STATUS_ACJTAG_CAPT_DATA_P
 
- HSIO_S6G_ACJTAG_STATUS_IB_DIRECT
 
- HSIO_S6G_COMMON_CFG
 
- HSIO_S6G_COMMON_CFG_ENA_DIRECT
 
- HSIO_S6G_COMMON_CFG_ENA_ELOOP
 
- HSIO_S6G_COMMON_CFG_ENA_FLOOP
 
- HSIO_S6G_COMMON_CFG_ENA_ILOOP
 
- HSIO_S6G_COMMON_CFG_ENA_LANE
 
- HSIO_S6G_COMMON_CFG_ENA_PLOOP
 
- HSIO_S6G_COMMON_CFG_HRATE
 
- HSIO_S6G_COMMON_CFG_IF_MODE
 
- HSIO_S6G_COMMON_CFG_IF_MODE_M
 
- HSIO_S6G_COMMON_CFG_LANE_CTRL
 
- HSIO_S6G_COMMON_CFG_LANE_CTRL_M
 
- HSIO_S6G_COMMON_CFG_LANE_CTRL_X
 
- HSIO_S6G_COMMON_CFG_PWD_RX
 
- HSIO_S6G_COMMON_CFG_PWD_TX
 
- HSIO_S6G_COMMON_CFG_QRATE
 
- HSIO_S6G_COMMON_CFG_SE_AUTO_SQUELCH_ENA
 
- HSIO_S6G_COMMON_CFG_SE_DIV2_ENA
 
- HSIO_S6G_COMMON_CFG_SYS_RST
 
- HSIO_S6G_DES_CFG
 
- HSIO_S6G_DES_CFG_DES_BW_ANA
 
- HSIO_S6G_DES_CFG_DES_BW_ANA_M
 
- HSIO_S6G_DES_CFG_DES_BW_ANA_X
 
- HSIO_S6G_DES_CFG_DES_BW_HYST
 
- HSIO_S6G_DES_CFG_DES_BW_HYST_M
 
- HSIO_S6G_DES_CFG_DES_BW_HYST_X
 
- HSIO_S6G_DES_CFG_DES_CPMD_SEL
 
- HSIO_S6G_DES_CFG_DES_CPMD_SEL_M
 
- HSIO_S6G_DES_CFG_DES_CPMD_SEL_X
 
- HSIO_S6G_DES_CFG_DES_MBTR_CTRL
 
- HSIO_S6G_DES_CFG_DES_MBTR_CTRL_M
 
- HSIO_S6G_DES_CFG_DES_MBTR_CTRL_X
 
- HSIO_S6G_DES_CFG_DES_PHS_CTRL
 
- HSIO_S6G_DES_CFG_DES_PHS_CTRL_M
 
- HSIO_S6G_DES_CFG_DES_PHS_CTRL_X
 
- HSIO_S6G_DES_CFG_DES_SWAP_ANA
 
- HSIO_S6G_DES_CFG_DES_SWAP_HYST
 
- HSIO_S6G_DFT_CFG0
 
- HSIO_S6G_DFT_CFG0_INV_DIS
 
- HSIO_S6G_DFT_CFG0_LAZYBIT
 
- HSIO_S6G_DFT_CFG0_PRBS_SEL
 
- HSIO_S6G_DFT_CFG0_PRBS_SEL_M
 
- HSIO_S6G_DFT_CFG0_PRBS_SEL_X
 
- HSIO_S6G_DFT_CFG0_RX_DFT_ENA
 
- HSIO_S6G_DFT_CFG0_RX_PDSENS_ENA
 
- HSIO_S6G_DFT_CFG0_RX_PHS_CORR_DIS
 
- HSIO_S6G_DFT_CFG0_TEST_MODE
 
- HSIO_S6G_DFT_CFG0_TEST_MODE_M
 
- HSIO_S6G_DFT_CFG0_TEST_MODE_X
 
- HSIO_S6G_DFT_CFG0_TX_DFT_ENA
 
- HSIO_S6G_DFT_CFG1
 
- HSIO_S6G_DFT_CFG1_TX_FREQOFF_DIR
 
- HSIO_S6G_DFT_CFG1_TX_FREQOFF_ENA
 
- HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL
 
- HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_M
 
- HSIO_S6G_DFT_CFG1_TX_JITTER_AMPL_X
 
- HSIO_S6G_DFT_CFG1_TX_JI_ENA
 
- HSIO_S6G_DFT_CFG1_TX_STEP_FREQ
 
- HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_M
 
- HSIO_S6G_DFT_CFG1_TX_STEP_FREQ_X
 
- HSIO_S6G_DFT_CFG1_TX_WAVEFORM_SEL
 
- HSIO_S6G_DFT_CFG2
 
- HSIO_S6G_DFT_CFG2_RX_FREQOFF_DIR
 
- HSIO_S6G_DFT_CFG2_RX_FREQOFF_ENA
 
- HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL
 
- HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_M
 
- HSIO_S6G_DFT_CFG2_RX_JITTER_AMPL_X
 
- HSIO_S6G_DFT_CFG2_RX_JI_ENA
 
- HSIO_S6G_DFT_CFG2_RX_STEP_FREQ
 
- HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_M
 
- HSIO_S6G_DFT_CFG2_RX_STEP_FREQ_X
 
- HSIO_S6G_DFT_CFG2_RX_WAVEFORM_SEL
 
- HSIO_S6G_DFT_STATUS
 
- HSIO_S6G_DFT_STATUS_BIST_ACTIVE
 
- HSIO_S6G_DFT_STATUS_BIST_COMPLETE_N
 
- HSIO_S6G_DFT_STATUS_BIST_ERROR
 
- HSIO_S6G_DFT_STATUS_BIST_NOSYNC
 
- HSIO_S6G_DFT_STATUS_PLL_BIST_FAILED
 
- HSIO_S6G_DFT_STATUS_PLL_BIST_NOT_DONE
 
- HSIO_S6G_DFT_STATUS_PLL_BIST_TIMEOUT_ERR
 
- HSIO_S6G_DFT_STATUS_PRBS_SYNC_STAT
 
- HSIO_S6G_DIG_CFG
 
- HSIO_S6G_DIG_CFG_GP
 
- HSIO_S6G_DIG_CFG_GP_M
 
- HSIO_S6G_DIG_CFG_GP_X
 
- HSIO_S6G_DIG_CFG_SIGDET_AST
 
- HSIO_S6G_DIG_CFG_SIGDET_AST_M
 
- HSIO_S6G_DIG_CFG_SIGDET_AST_X
 
- HSIO_S6G_DIG_CFG_SIGDET_DST
 
- HSIO_S6G_DIG_CFG_SIGDET_DST_M
 
- HSIO_S6G_DIG_CFG_SIGDET_TESTMODE
 
- HSIO_S6G_DIG_CFG_TX_BIT_DOUBLING_MODE_ENA
 
- HSIO_S6G_ERR_CNT
 
- HSIO_S6G_GP_CFG
 
- HSIO_S6G_GP_CFG_GP_LSB
 
- HSIO_S6G_GP_CFG_GP_LSB_M
 
- HSIO_S6G_GP_CFG_GP_MSB
 
- HSIO_S6G_GP_CFG_GP_MSB_M
 
- HSIO_S6G_GP_CFG_GP_MSB_X
 
- HSIO_S6G_IB_CFG
 
- HSIO_S6G_IB_CFG1
 
- HSIO_S6G_IB_CFG1_IB_FILT_HP
 
- HSIO_S6G_IB_CFG1_IB_FILT_LP
 
- HSIO_S6G_IB_CFG1_IB_FILT_MID
 
- HSIO_S6G_IB_CFG1_IB_FILT_OFFSET
 
- HSIO_S6G_IB_CFG1_IB_FRC_HP
 
- HSIO_S6G_IB_CFG1_IB_FRC_LP
 
- HSIO_S6G_IB_CFG1_IB_FRC_MID
 
- HSIO_S6G_IB_CFG1_IB_FRC_OFFSET
 
- HSIO_S6G_IB_CFG1_IB_SCALY
 
- HSIO_S6G_IB_CFG1_IB_SCALY_M
 
- HSIO_S6G_IB_CFG1_IB_SCALY_X
 
- HSIO_S6G_IB_CFG1_IB_TJTAG
 
- HSIO_S6G_IB_CFG1_IB_TJTAG_M
 
- HSIO_S6G_IB_CFG1_IB_TJTAG_X
 
- HSIO_S6G_IB_CFG1_IB_TSDET
 
- HSIO_S6G_IB_CFG1_IB_TSDET_M
 
- HSIO_S6G_IB_CFG1_IB_TSDET_X
 
- HSIO_S6G_IB_CFG2
 
- HSIO_S6G_IB_CFG2_IB_OCALS
 
- HSIO_S6G_IB_CFG2_IB_OCALS_M
 
- HSIO_S6G_IB_CFG2_IB_OCALS_X
 
- HSIO_S6G_IB_CFG2_IB_OINFI
 
- HSIO_S6G_IB_CFG2_IB_OINFI_M
 
- HSIO_S6G_IB_CFG2_IB_OINFI_X
 
- HSIO_S6G_IB_CFG2_IB_OINFS
 
- HSIO_S6G_IB_CFG2_IB_OINFS_M
 
- HSIO_S6G_IB_CFG2_IB_OINFS_X
 
- HSIO_S6G_IB_CFG2_IB_TAUX
 
- HSIO_S6G_IB_CFG2_IB_TAUX_M
 
- HSIO_S6G_IB_CFG2_IB_TAUX_X
 
- HSIO_S6G_IB_CFG2_IB_TCALV
 
- HSIO_S6G_IB_CFG2_IB_TCALV_M
 
- HSIO_S6G_IB_CFG2_IB_TCALV_X
 
- HSIO_S6G_IB_CFG2_IB_TINFV
 
- HSIO_S6G_IB_CFG2_IB_TINFV_M
 
- HSIO_S6G_IB_CFG2_IB_TINFV_X
 
- HSIO_S6G_IB_CFG2_IB_UMAX
 
- HSIO_S6G_IB_CFG2_IB_UMAX_M
 
- HSIO_S6G_IB_CFG2_IB_UMAX_X
 
- HSIO_S6G_IB_CFG2_IB_UREG
 
- HSIO_S6G_IB_CFG2_IB_UREG_M
 
- HSIO_S6G_IB_CFG3
 
- HSIO_S6G_IB_CFG3_IB_INI_HP
 
- HSIO_S6G_IB_CFG3_IB_INI_HP_M
 
- HSIO_S6G_IB_CFG3_IB_INI_HP_X
 
- HSIO_S6G_IB_CFG3_IB_INI_LP
 
- HSIO_S6G_IB_CFG3_IB_INI_LP_M
 
- HSIO_S6G_IB_CFG3_IB_INI_LP_X
 
- HSIO_S6G_IB_CFG3_IB_INI_MID
 
- HSIO_S6G_IB_CFG3_IB_INI_MID_M
 
- HSIO_S6G_IB_CFG3_IB_INI_MID_X
 
- HSIO_S6G_IB_CFG3_IB_INI_OFFSET
 
- HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M
 
- HSIO_S6G_IB_CFG4
 
- HSIO_S6G_IB_CFG4_IB_MAX_HP
 
- HSIO_S6G_IB_CFG4_IB_MAX_HP_M
 
- HSIO_S6G_IB_CFG4_IB_MAX_HP_X
 
- HSIO_S6G_IB_CFG4_IB_MAX_LP
 
- HSIO_S6G_IB_CFG4_IB_MAX_LP_M
 
- HSIO_S6G_IB_CFG4_IB_MAX_LP_X
 
- HSIO_S6G_IB_CFG4_IB_MAX_MID
 
- HSIO_S6G_IB_CFG4_IB_MAX_MID_M
 
- HSIO_S6G_IB_CFG4_IB_MAX_MID_X
 
- HSIO_S6G_IB_CFG4_IB_MAX_OFFSET
 
- HSIO_S6G_IB_CFG4_IB_MAX_OFFSET_M
 
- HSIO_S6G_IB_CFG5
 
- HSIO_S6G_IB_CFG5_IB_MIN_HP
 
- HSIO_S6G_IB_CFG5_IB_MIN_HP_M
 
- HSIO_S6G_IB_CFG5_IB_MIN_HP_X
 
- HSIO_S6G_IB_CFG5_IB_MIN_LP
 
- HSIO_S6G_IB_CFG5_IB_MIN_LP_M
 
- HSIO_S6G_IB_CFG5_IB_MIN_LP_X
 
- HSIO_S6G_IB_CFG5_IB_MIN_MID
 
- HSIO_S6G_IB_CFG5_IB_MIN_MID_M
 
- HSIO_S6G_IB_CFG5_IB_MIN_MID_X
 
- HSIO_S6G_IB_CFG5_IB_MIN_OFFSET
 
- HSIO_S6G_IB_CFG5_IB_MIN_OFFSET_M
 
- HSIO_S6G_IB_CFG_IB_ANA_TEST_ENA
 
- HSIO_S6G_IB_CFG_IB_CAL_ENA
 
- HSIO_S6G_IB_CFG_IB_CONCUR
 
- HSIO_S6G_IB_CFG_IB_EQZ_ENA
 
- HSIO_S6G_IB_CFG_IB_ICML_ADJ
 
- HSIO_S6G_IB_CFG_IB_ICML_ADJ_M
 
- HSIO_S6G_IB_CFG_IB_ICML_ADJ_X
 
- HSIO_S6G_IB_CFG_IB_REG_ENA
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_M
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_HP_X
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_M
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_LP_X
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_M
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_MID_X
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M
 
- HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_X
 
- HSIO_S6G_IB_CFG_IB_RTRM_ADJ
 
- HSIO_S6G_IB_CFG_IB_RTRM_ADJ_M
 
- HSIO_S6G_IB_CFG_IB_RTRM_ADJ_X
 
- HSIO_S6G_IB_CFG_IB_SAM_ENA
 
- HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL
 
- HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M
 
- HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_X
 
- HSIO_S6G_IB_CFG_IB_SIG_DET_ENA
 
- HSIO_S6G_IB_CFG_IB_SOFSI
 
- HSIO_S6G_IB_CFG_IB_SOFSI_M
 
- HSIO_S6G_IB_CFG_IB_SOFSI_X
 
- HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL
 
- HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_M
 
- HSIO_S6G_IB_CFG_IB_TERM_MODE_SEL_X
 
- HSIO_S6G_IB_CFG_IB_VBULK_SEL
 
- HSIO_S6G_IB_STATUS0
 
- HSIO_S6G_IB_STATUS0_IB_CAL_DONE
 
- HSIO_S6G_IB_STATUS0_IB_HP_GAIN_ACT
 
- HSIO_S6G_IB_STATUS0_IB_LP_GAIN_ACT
 
- HSIO_S6G_IB_STATUS0_IB_MID_GAIN_ACT
 
- HSIO_S6G_IB_STATUS0_IB_OFFSDIR
 
- HSIO_S6G_IB_STATUS0_IB_OFFSET_ACT
 
- HSIO_S6G_IB_STATUS0_IB_OFFSET_ERR
 
- HSIO_S6G_IB_STATUS0_IB_OFFSET_VLD
 
- HSIO_S6G_IB_STATUS0_IB_SIG_DET
 
- HSIO_S6G_IB_STATUS1
 
- HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT
 
- HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_M
 
- HSIO_S6G_IB_STATUS1_IB_HP_GAIN_STAT_X
 
- HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT
 
- HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_M
 
- HSIO_S6G_IB_STATUS1_IB_LP_GAIN_STAT_X
 
- HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT
 
- HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_M
 
- HSIO_S6G_IB_STATUS1_IB_MID_GAIN_STAT_X
 
- HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT
 
- HSIO_S6G_IB_STATUS1_IB_OFFSET_STAT_M
 
- HSIO_S6G_MISC_CFG
 
- HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA
 
- HSIO_S6G_MISC_CFG_DES_100FX_CPMD_MODE
 
- HSIO_S6G_MISC_CFG_DES_100FX_CPMD_SWAP
 
- HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE
 
- HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_M
 
- HSIO_S6G_MISC_CFG_DES_100FX_KICK_MODE_X
 
- HSIO_S6G_MISC_CFG_LANE_RST
 
- HSIO_S6G_MISC_CFG_RX_BUS_FLIP_ENA
 
- HSIO_S6G_MISC_CFG_RX_DATA_INV_ENA
 
- HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA
 
- HSIO_S6G_MISC_CFG_SEL_RECO_CLK
 
- HSIO_S6G_MISC_CFG_SEL_RECO_CLK_M
 
- HSIO_S6G_MISC_CFG_SEL_RECO_CLK_X
 
- HSIO_S6G_MISC_CFG_TX_BUS_FLIP_ENA
 
- HSIO_S6G_MISC_CFG_TX_DATA_INV_ENA
 
- HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA
 
- HSIO_S6G_MISC_STATUS
 
- HSIO_S6G_MISC_STATUS_DES_100FX_PHASE_SEL
 
- HSIO_S6G_OB_ANEG_CFG
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_M
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_ENA_CAS_X
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_LEV_M
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_M
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST0_X
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_M
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_POST1_X
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_M
 
- HSIO_S6G_OB_ANEG_CFG_AN_OB_PREC_X
 
- HSIO_S6G_OB_CFG
 
- HSIO_S6G_OB_CFG1
 
- HSIO_S6G_OB_CFG1_OB_ENA_CAS
 
- HSIO_S6G_OB_CFG1_OB_ENA_CAS_M
 
- HSIO_S6G_OB_CFG1_OB_ENA_CAS_X
 
- HSIO_S6G_OB_CFG1_OB_LEV
 
- HSIO_S6G_OB_CFG1_OB_LEV_M
 
- HSIO_S6G_OB_CFG_OB_ENA1V_MODE
 
- HSIO_S6G_OB_CFG_OB_IDLE
 
- HSIO_S6G_OB_CFG_OB_POL
 
- HSIO_S6G_OB_CFG_OB_POST0
 
- HSIO_S6G_OB_CFG_OB_POST0_M
 
- HSIO_S6G_OB_CFG_OB_POST0_X
 
- HSIO_S6G_OB_CFG_OB_POST1
 
- HSIO_S6G_OB_CFG_OB_POST1_M
 
- HSIO_S6G_OB_CFG_OB_POST1_X
 
- HSIO_S6G_OB_CFG_OB_PREC
 
- HSIO_S6G_OB_CFG_OB_PREC_M
 
- HSIO_S6G_OB_CFG_OB_PREC_X
 
- HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL
 
- HSIO_S6G_OB_CFG_OB_RESISTOR_CTRL_M
 
- HSIO_S6G_OB_CFG_OB_R_ADJ_MUX
 
- HSIO_S6G_OB_CFG_OB_R_ADJ_PDR
 
- HSIO_S6G_OB_CFG_OB_R_COR
 
- HSIO_S6G_OB_CFG_OB_SEL_RCTRL
 
- HSIO_S6G_OB_CFG_OB_SR
 
- HSIO_S6G_OB_CFG_OB_SR_H
 
- HSIO_S6G_OB_CFG_OB_SR_M
 
- HSIO_S6G_OB_CFG_OB_SR_X
 
- HSIO_S6G_PLL_CFG
 
- HSIO_S6G_PLL_CFG_PLL_DIV4
 
- HSIO_S6G_PLL_CFG_PLL_ENA_OFFS
 
- HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_M
 
- HSIO_S6G_PLL_CFG_PLL_ENA_OFFS_X
 
- HSIO_S6G_PLL_CFG_PLL_ENA_ROT
 
- HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA
 
- HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M
 
- HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_X
 
- HSIO_S6G_PLL_CFG_PLL_FSM_ENA
 
- HSIO_S6G_PLL_CFG_PLL_FSM_FORCE_SET_ENA
 
- HSIO_S6G_PLL_CFG_PLL_FSM_OOR_RECAL_ENA
 
- HSIO_S6G_PLL_CFG_PLL_RB_DATA_SEL
 
- HSIO_S6G_PLL_CFG_PLL_ROT_DIR
 
- HSIO_S6G_PLL_CFG_PLL_ROT_FRQ
 
- HSIO_S6G_PLL_STATUS
 
- HSIO_S6G_PLL_STATUS_PLL_CAL_ERR
 
- HSIO_S6G_PLL_STATUS_PLL_CAL_NOT_DONE
 
- HSIO_S6G_PLL_STATUS_PLL_OUT_OF_RANGE_ERR
 
- HSIO_S6G_PLL_STATUS_PLL_RB_DATA
 
- HSIO_S6G_PLL_STATUS_PLL_RB_DATA_M
 
- HSIO_S6G_RC_PLL_BIST_CFG
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_ENA
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_M
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_FBS_HIGH_X
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_M
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_HIGH_X
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW
 
- HSIO_S6G_RC_PLL_BIST_CFG_PLL_BIST_LOW_M
 
- HSIO_S6G_REVID
 
- HSIO_S6G_REVID_DES_REV
 
- HSIO_S6G_REVID_DES_REV_M
 
- HSIO_S6G_REVID_DES_REV_X
 
- HSIO_S6G_REVID_IB_REV
 
- HSIO_S6G_REVID_IB_REV_M
 
- HSIO_S6G_REVID_OB_REV
 
- HSIO_S6G_REVID_OB_REV_M
 
- HSIO_S6G_REVID_OB_REV_X
 
- HSIO_S6G_REVID_RCPLL_REV
 
- HSIO_S6G_REVID_RCPLL_REV_M
 
- HSIO_S6G_REVID_RCPLL_REV_X
 
- HSIO_S6G_REVID_SERDES_REV
 
- HSIO_S6G_REVID_SERDES_REV_M
 
- HSIO_S6G_REVID_SERDES_REV_X
 
- HSIO_S6G_REVID_SER_REV
 
- HSIO_S6G_REVID_SER_REV_M
 
- HSIO_S6G_REVID_SER_REV_X
 
- HSIO_S6G_SER_CFG
 
- HSIO_S6G_SER_CFG_SER_4TAP_ENA
 
- HSIO_S6G_SER_CFG_SER_ALISEL
 
- HSIO_S6G_SER_CFG_SER_ALISEL_M
 
- HSIO_S6G_SER_CFG_SER_ALISEL_X
 
- HSIO_S6G_SER_CFG_SER_BIG_WIN
 
- HSIO_S6G_SER_CFG_SER_CPMD_SEL
 
- HSIO_S6G_SER_CFG_SER_ENALI
 
- HSIO_S6G_SER_CFG_SER_ENHYS
 
- HSIO_S6G_SER_CFG_SER_EN_WIN
 
- HSIO_S6G_SER_CFG_SER_SWAP_CPMD
 
- HSIO_S6G_TP_CFG0
 
- HSIO_S6G_TP_CFG1
 
- HSIO_SYNC_ETH_CFG
 
- HSIO_SYNC_ETH_CFG_RECO_CLK_ENA
 
- HSIO_SYNC_ETH_CFG_RSZ
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_M
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_DIV_X
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_M
 
- HSIO_SYNC_ETH_CFG_SEL_RECO_CLK_SRC_X
 
- HSIO_SYNC_ETH_PLL_CFG
 
- HSIO_SYNC_ETH_PLL_CFG_PLL_AUTO_SQUELCH_ENA
 
- HSIO_TEMP_SENSOR_CFG
 
- HSIO_TEMP_SENSOR_CFG_RUN_WID
 
- HSIO_TEMP_SENSOR_CFG_RUN_WID_M
 
- HSIO_TEMP_SENSOR_CFG_RUN_WID_X
 
- HSIO_TEMP_SENSOR_CFG_SAMPLE_PER
 
- HSIO_TEMP_SENSOR_CFG_SAMPLE_PER_M
 
- HSIO_TEMP_SENSOR_CTRL
 
- HSIO_TEMP_SENSOR_CTRL_FORCE_CLK
 
- HSIO_TEMP_SENSOR_CTRL_FORCE_NO_RST
 
- HSIO_TEMP_SENSOR_CTRL_FORCE_POWER_UP
 
- HSIO_TEMP_SENSOR_CTRL_FORCE_RUN
 
- HSIO_TEMP_SENSOR_CTRL_FORCE_TEMP_RD
 
- HSIO_TEMP_SENSOR_CTRL_SAMPLE_ENA
 
- HSIO_TEMP_SENSOR_STAT
 
- HSIO_TEMP_SENSOR_STAT_TEMP
 
- HSIO_TEMP_SENSOR_STAT_TEMP_M
 
- HSIO_TEMP_SENSOR_STAT_TEMP_VALID
 
- HSIPHASH_ALIGNMENT
 
- HSIPROUND
 
- HSISR_GPIO12_0_INT
 
- HSISR_GPIO9_INT
 
- HSISR_PDNINT
 
- HSISR_RON_INT
 
- HSISR_RON_INT_EN
 
- HSISR_SPS_OCP_INT
 
- HSIT_MAX_SIZE
 
- HSIT_MIN_SIZE
 
- HSIT_PAD_SINK
 
- HSIT_PAD_SOURCE
 
- HSIZE
 
- HSIZE8
 
- HSIZE8_SET
 
- HSIZE_16
 
- HSIZE_32
 
- HSIZE_8
 
- HSIZE_MASK
 
- HSIZE_SET
 
- HSI_ARB_PRIO
 
- HSI_ARB_RR
 
- HSI_CHAR_MAGIC
 
- HSI_CK
 
- HSI_DIV
 
- HSI_EVENT_START_RX
 
- HSI_EVENT_STOP_RX
 
- HSI_FLOW_PIPE
 
- HSI_FLOW_SYNC
 
- HSI_KER_CK
 
- HSI_MAX_CHANNELS
 
- HSI_MODE_FRAME
 
- HSI_MODE_STREAM
 
- HSI_MSG_READ
 
- HSI_MSG_WRITE
 
- HSI_RX_DATA
 
- HSI_RX_DATA_MARK
 
- HSI_RX_FLAG
 
- HSI_RX_FLAG_MARK
 
- HSI_RX_READY
 
- HSI_RX_READY_MARK
 
- HSI_RX_WAKE
 
- HSI_RX_WAKE_MARK
 
- HSI_STATUS_COMPLETED
 
- HSI_STATUS_ERROR
 
- HSI_STATUS_PENDING
 
- HSI_STATUS_PROCEEDING
 
- HSI_STATUS_QUEUED
 
- HSI_TX_DATA
 
- HSI_TX_DATA_MARK
 
- HSI_TX_FLAG
 
- HSI_TX_FLAG_MARK
 
- HSI_TX_READY
 
- HSI_TX_READY_MARK
 
- HSI_TX_WAKE
 
- HSI_TX_WAKE_MARK
 
- HSLOWCTL
 
- HSMIC
 
- HSMMC_HAS_HSPE_SUPPORT
 
- HSMMC_HAS_PBIAS
 
- HSMMC_HAS_UPDATED_RESET
 
- HSMMC_NAME_LEN
 
- HSMMC_SDIO_IRQ_ENABLED
 
- HSMODE
 
- HSMP_EADDR_mskEADDR
 
- HSMP_EADDR_offEADDR
 
- HSMP_SADDR_mskEN
 
- HSMP_SADDR_mskRANGE
 
- HSMP_SADDR_mskSADDR
 
- HSMP_SADDR_offEN
 
- HSMP_SADDR_offRANGE
 
- HSMP_SADDR_offSADDR
 
- HSM_CLOCK_FREQ
 
- HSM_ST
 
- HSM_ST_ERR
 
- HSM_ST_FIRST
 
- HSM_ST_IDLE
 
- HSM_ST_LAST
 
- HSORG_DISABLE_SLOTGRP_INTR
 
- HSORG_DISABLE_SLOTGRP_PXIS
 
- HSORG_HWREV
 
- HSORG_SLOTGROUPS
 
- HSORG_STYLE
 
- HSOTG_REG
 
- HSO_INFO_CRC_BUG
 
- HSO_INFO_MASK
 
- HSO_INTF_BULK
 
- HSO_INTF_MASK
 
- HSO_INTF_MUX
 
- HSO_MAX_NET_DEVICES
 
- HSO_NET_RUNNING
 
- HSO_NET_TX_TIMEOUT
 
- HSO_PORT_APP
 
- HSO_PORT_APP2
 
- HSO_PORT_CONTROL
 
- HSO_PORT_DIAG
 
- HSO_PORT_DIAG2
 
- HSO_PORT_GPS
 
- HSO_PORT_GPS_CONTROL
 
- HSO_PORT_MASK
 
- HSO_PORT_MODEM
 
- HSO_PORT_MSD
 
- HSO_PORT_NETWORK
 
- HSO_PORT_NO_PORT
 
- HSO_PORT_PCSC
 
- HSO_PORT_VOICE
 
- HSO_SERIAL_MAGIC
 
- HSO_SERIAL_TTY_MINORS
 
- HSO__MAX_MTU
 
- HSPCLKDIV_MAX
 
- HSPE
 
- HSPEC_BASE
 
- HSPHY_CFG0
 
- HSPHY_CFG0_HSDISC_MASK
 
- HSPHY_CFG0_HS_I_MASK
 
- HSPHY_CFG0_RTERM_MASK
 
- HSPHY_CFG0_SEL_T_MASK
 
- HSPHY_CFG0_SWING_MASK
 
- HSPHY_CFG0_TRIMMASK
 
- HSPHY_CFG1
 
- HSPHY_CFG1_ADR_EN
 
- HSPHY_CFG1_ADR_MASK
 
- HSPHY_CFG1_DAT_EN
 
- HSPHY_CFG1_DAT_MASK
 
- HSPHY_PCTL_VAL
 
- HSPHY_SESS_VLD_CTRL
 
- HSPI
 
- HSPI_CLK0_A_MARK
 
- HSPI_CLK0_B_MARK
 
- HSPI_CLK0_C_MARK
 
- HSPI_CLK0_MARK
 
- HSPI_CLK1_A_MARK
 
- HSPI_CLK1_B_MARK
 
- HSPI_CLK1_C_MARK
 
- HSPI_CLK1_D_MARK
 
- HSPI_CLK1_MARK
 
- HSPI_CLK2_A_MARK
 
- HSPI_CLK2_B_MARK
 
- HSPI_CLK2_MARK
 
- HSPI_CLK_A_MARK
 
- HSPI_CLK_B_MARK
 
- HSPI_CLK_MARK
 
- HSPI_CS0_A_MARK
 
- HSPI_CS0_B_MARK
 
- HSPI_CS0_C_MARK
 
- HSPI_CS0_MARK
 
- HSPI_CS1_A_MARK
 
- HSPI_CS1_B_MARK
 
- HSPI_CS1_C_MARK
 
- HSPI_CS1_D_MARK
 
- HSPI_CS1_MARK
 
- HSPI_CS2_A_MARK
 
- HSPI_CS2_B_MARK
 
- HSPI_CS2_MARK
 
- HSPI_CS_A_MARK
 
- HSPI_CS_B_MARK
 
- HSPI_CS_MARK
 
- HSPI_PFC_DAT
 
- HSPI_PFC_PIN
 
- HSPI_RX0_A_MARK
 
- HSPI_RX0_B_MARK
 
- HSPI_RX0_C_MARK
 
- HSPI_RX0_MARK
 
- HSPI_RX1_A_MARK
 
- HSPI_RX1_B_MARK
 
- HSPI_RX1_C_MARK
 
- HSPI_RX1_D_MARK
 
- HSPI_RX1_MARK
 
- HSPI_RX2_A_MARK
 
- HSPI_RX2_B_MARK
 
- HSPI_RX2_MARK
 
- HSPI_RX_A_MARK
 
- HSPI_RX_B_MARK
 
- HSPI_RX_MARK
 
- HSPI_TX0_B_MARK
 
- HSPI_TX0_C_MARK
 
- HSPI_TX0_MARK
 
- HSPI_TX1_A_MARK
 
- HSPI_TX1_B_MARK
 
- HSPI_TX1_C_MARK
 
- HSPI_TX1_D_MARK
 
- HSPI_TX1_MARK
 
- HSPI_TX2_A_MARK
 
- HSPI_TX2_B_MARK
 
- HSPI_TX2_MARK
 
- HSPI_TX_A_MARK
 
- HSPI_TX_B_MARK
 
- HSPI_TX_MARK
 
- HSPLL_NDIV_FRAC_VAL
 
- HSPLL_NDIV_INT_VAL
 
- HSPLL_PDIV_MASK
 
- HSPLL_PDIV_VAL
 
- HSPROC
 
- HSP_ALIGNMENT
 
- HSP_BA
 
- HSP_CLOCK
 
- HSP_DB_BPMP
 
- HSP_DB_CCPLEX
 
- HSP_DB_ENABLE
 
- HSP_DB_MAX
 
- HSP_DB_PENDING
 
- HSP_DB_RAW
 
- HSP_DB_TRIGGER
 
- HSP_HI
 
- HSP_INT_DIMENSIONING
 
- HSP_INT_EMPTY_MASK
 
- HSP_INT_EMPTY_SHIFT
 
- HSP_INT_FULL_MASK
 
- HSP_INT_FULL_SHIFT
 
- HSP_INT_IE
 
- HSP_INT_IR
 
- HSP_INT_IV
 
- HSP_IRQ
 
- HSP_LOW
 
- HSP_MAX_SIZE
 
- HSP_SIZE
 
- HSP_SM_SHRD_MBOX
 
- HSP_SM_SHRD_MBOX_EMPTY_INT_IE
 
- HSP_SM_SHRD_MBOX_FULL
 
- HSP_SM_SHRD_MBOX_FULL_INT_IE
 
- HSP_nAS_SHIFT
 
- HSP_nDB_SHIFT
 
- HSP_nINT_MASK
 
- HSP_nSI_SHIFT
 
- HSP_nSM_SHIFT
 
- HSP_nSS_SHIFT
 
- HSR
 
- HSR0_VC16
 
- HSR0_VC17
 
- HSR0_VC18
 
- HSR0_VC19
 
- HSR0_VC20
 
- HSR0_VC21
 
- HSR0_VC22
 
- HSR0_VC23
 
- HSR0_VC24
 
- HSR0_VC25
 
- HSR0_VC26
 
- HSR0_VC27
 
- HSR0_VC28
 
- HSR0_VC29
 
- HSR0_VC30
 
- HSR0_VC31
 
- HSR0_VC32
 
- HSR0_VC33
 
- HSR0_VC34
 
- HSR0_VC35
 
- HSR0_VC36
 
- HSR0_VC37
 
- HSR0_VC38
 
- HSR0_VC39
 
- HSR0_VC40
 
- HSR0_VC41
 
- HSR0_VC42
 
- HSR0_VC43
 
- HSR0_VC44
 
- HSR0_VC45
 
- HSR0_VC46
 
- HSR0_VC47
 
- HSR0_VC_MASK
 
- HSRA
 
- HSRECN
 
- HSREF_CLK_DIV_MASK
 
- HSREF_CLK_DIV_POS
 
- HSRR1_DENORM
 
- HSRR1_HISI_WRITE
 
- HSRTRGR
 
- HSRX_RISC_INT
 
- HSRX_RISC_IOCB_INT
 
- HSRX_RISC_MB_INT
 
- HSRX_RISC_PAUSED
 
- HSR_ACTION
 
- HSR_AGE_CNT_DEFAULT_M
 
- HSR_AGE_CNT_DEFAULT_S
 
- HSR_AGING_ENABLE
 
- HSR_ALMOST_FULL_INT
 
- HSR_ANNOUNCE_INTERVAL
 
- HSR_A_ADDR_B_IFINDEX
 
- HSR_A_IF1_AGE
 
- HSR_A_IF1_IFINDEX
 
- HSR_A_IF1_SEQ
 
- HSR_A_IF2_AGE
 
- HSR_A_IF2_IFINDEX
 
- HSR_A_IF2_SEQ
 
- HSR_A_IFINDEX
 
- HSR_A_MAX
 
- HSR_A_NODE_ADDR
 
- HSR_A_NODE_ADDR_B
 
- HSR_A_UNSPEC
 
- HSR_COND
 
- HSR_COND_SHIFT
 
- HSR_CPU_ACCESS_ENTRY_INDEX_M
 
- HSR_CV
 
- HSR_CV_SHIFT
 
- HSR_C_GET_NODE_LIST
 
- HSR_C_GET_NODE_STATUS
 
- HSR_C_MAX
 
- HSR_C_NODE_DOWN
 
- HSR_C_RING_ERROR
 
- HSR_C_SET_NODE_LIST
 
- HSR_C_SET_NODE_STATUS
 
- HSR_C_UNSPEC
 
- HSR_DABT_CM
 
- HSR_DABT_S1PTW
 
- HSR_DIRECT
 
- HSR_DIRECT_INDEX_M
 
- HSR_DST_MAC_INDEX_LO_S
 
- HSR_DUPLICATE_DISCARD
 
- HSR_EC
 
- HSR_EC_BXJ
 
- HSR_EC_CP10_ID
 
- HSR_EC_CP14_64
 
- HSR_EC_CP14_LS
 
- HSR_EC_CP14_MR
 
- HSR_EC_CP15_32
 
- HSR_EC_CP15_64
 
- HSR_EC_CP_0_13
 
- HSR_EC_DABT
 
- HSR_EC_DABT_HYP
 
- HSR_EC_HVC
 
- HSR_EC_IABT
 
- HSR_EC_IABT_HYP
 
- HSR_EC_JAZELLE
 
- HSR_EC_MAX
 
- HSR_EC_SHIFT
 
- HSR_EC_SMC
 
- HSR_EC_SVC_HYP
 
- HSR_EC_UNKNOWN
 
- HSR_EC_WFI
 
- HSR_ENTRY_INDEX_M
 
- HSR_FAIL_INDEX_M
 
- HSR_FAIL_LEARN_INDEX_M
 
- HSR_FLUSH_TABLE
 
- HSR_FSC
 
- HSR_FSC_TYPE
 
- HSR_HASH_DISABLE
 
- HSR_HASH_LOWER_BITS
 
- HSR_HASH_OPTION_M
 
- HSR_HASH_UPPER_BITS
 
- HSR_HASH_XOR_BOTH_BITS
 
- HSR_HLEN
 
- HSR_HVC_IMM_MASK
 
- HSR_IL
 
- HSR_INDEX_MAX
 
- HSR_ISS
 
- HSR_ISV
 
- HSR_ISV_SHIFT
 
- HSR_LEARN_FAIL_INT
 
- HSR_LEARN_MCAST_DISABLE
 
- HSR_LEARN_UCAST_DISABLE
 
- HSR_LIFE_CHECK_INTERVAL
 
- HSR_NODE_FORGET_TIME
 
- HSR_NODE_UNICAST
 
- HSR_PATH_INDEX_M
 
- HSR_PROC_MCAST_SRC
 
- HSR_PT_INTERLINK
 
- HSR_PT_MASTER
 
- HSR_PT_NONE
 
- HSR_PT_PORTS
 
- HSR_PT_SLAVE_A
 
- HSR_PT_SLAVE_B
 
- HSR_READ
 
- HSR_RISC_INT
 
- HSR_RISC_PAUSED
 
- HSR_SEARCH
 
- HSR_SEARCH_END
 
- HSR_SEQNR_START
 
- HSR_SRC_MAC_INDEX_HI
 
- HSR_SRT_MASK
 
- HSR_SRT_SHIFT
 
- HSR_SSE
 
- HSR_START
 
- HSR_SUP_SEQNR_START
 
- HSR_TLV_ANNOUNCE
 
- HSR_TLV_LIFE_CHECK
 
- HSR_V1_SUP_LSDUSIZE
 
- HSR_VALID
 
- HSR_VALID_CNT_M
 
- HSR_VALID_CNT_S
 
- HSR_V_AGE_CNT_M
 
- HSR_V_AGE_CNT_S
 
- HSR_V_DST_MAC_ADDR_LO_S
 
- HSR_V_EXP_SEQ_1_S
 
- HSR_V_EXP_SEQ_2_S
 
- HSR_V_PATH_ID_M
 
- HSR_V_SEQ_CNT_1_S
 
- HSR_V_SEQ_CNT_2_S
 
- HSR_V_SEQ_M
 
- HSR_V_SRC_MAC_ADDR_HI
 
- HSR_V_START_SEQ_1_S
 
- HSR_V_START_SEQ_2_S
 
- HSR_V_STATIC_VALID
 
- HSR_WFI_IS_WFE
 
- HSR_WINDOW_OVERFLOW_INT
 
- HSR_WNR
 
- HSR_WRITE
 
- HSR_WRITE_FAIL_INT
 
- HSS
 
- HSS0_CHL_RXTRIG_QUEUE
 
- HSS0_PKT_RXFREE0_QUEUE
 
- HSS0_PKT_RXFREE1_QUEUE
 
- HSS0_PKT_RXFREE2_QUEUE
 
- HSS0_PKT_RXFREE3_QUEUE
 
- HSS0_PKT_RX_QUEUE
 
- HSS0_PKT_TX0_QUEUE
 
- HSS0_PKT_TX1_QUEUE
 
- HSS0_PKT_TX2_QUEUE
 
- HSS0_PKT_TX3_QUEUE
 
- HSS0_PKT_TXDONE_QUEUE
 
- HSS1394_ADDRESS
 
- HSS1394_MAX_PACKET_SIZE
 
- HSS1394_TAG_CHANGE_ADDRESS
 
- HSS1394_TAG_USER_DATA
 
- HSS1_CHL_RXTRIG_QUEUE
 
- HSS1_PKT_RXFREE0_QUEUE
 
- HSS1_PKT_RXFREE1_QUEUE
 
- HSS1_PKT_RXFREE2_QUEUE
 
- HSS1_PKT_RXFREE3_QUEUE
 
- HSS1_PKT_RX_QUEUE
 
- HSS1_PKT_TX0_QUEUE
 
- HSS1_PKT_TX1_QUEUE
 
- HSS1_PKT_TX2_QUEUE
 
- HSS1_PKT_TX3_QUEUE
 
- HSS1_PKT_TXDONE_QUEUE
 
- HSSCR_TOT_SHIFT
 
- HSSL_ASYNCW
 
- HSSL_DVALID
 
- HSSL_HACT
 
- HSSL_HLOCK
 
- HSSL_HSYNC
 
- HSSL_ZERO
 
- HSSPI_BUFFER_LEN
 
- HSSPI_BUS_NUM
 
- HSSPI_FIFO_REG
 
- HSSPI_GLOBAL_CTRL_REG
 
- HSSPI_GLOBAL_EXT_TRIGGER_REG
 
- HSSPI_INT_CLEAR_ALL
 
- HSSPI_INT_MASK_REG
 
- HSSPI_INT_STATUS_MASKED_REG
 
- HSSPI_INT_STATUS_REG
 
- HSSPI_MAX_PREPEND_LEN
 
- HSSPI_MAX_SYNC_CLOCK
 
- HSSPI_OPCODE_LEN
 
- HSSPI_OP_CODE_SHIFT
 
- HSSPI_OP_MULTIBIT
 
- HSSPI_OP_READ
 
- HSSPI_OP_READ_WRITE
 
- HSSPI_OP_SETIRQ
 
- HSSPI_OP_SLEEP
 
- HSSPI_OP_WRITE
 
- HSSPI_PINGPONG_COMMAND_REG
 
- HSSPI_PINGPONG_STATUS_REG
 
- HSSPI_PINGx_CMD_DONE
 
- HSSPI_PINGx_CTRL_INVAL
 
- HSSPI_PINGx_POLL_TIMEOUT
 
- HSSPI_PINGx_RX_OVER
 
- HSSPI_PINGx_TX_UNDER
 
- HSSPI_PLL_HZ_6328
 
- HSSPI_PLL_HZ_6362
 
- HSSPI_PROFILE_CLK_CTRL_REG
 
- HSSPI_PROFILE_MODE_CTRL_REG
 
- HSSPI_PROFILE_SIGNAL_CTRL_REG
 
- HSSPI_SPI_MAX_CS
 
- HSSPKR
 
- HSSR0_EIF
 
- HSSR0_FRE
 
- HSSR0_RAB
 
- HSSR0_RFS
 
- HSSR0_TFS
 
- HSSR0_TUR
 
- HSSR1_CRE
 
- HSSR1_EOF
 
- HSSR1_RNE
 
- HSSR1_ROR
 
- HSSR1_RSY
 
- HSSR1_TBY
 
- HSSR1_TNF
 
- HSSRR
 
- HSS_104M
 
- HSS_156M
 
- HSS_208M
 
- HSS_312M
 
- HSS_CONFIG_CLOCK_CR
 
- HSS_CONFIG_CORE_CR
 
- HSS_CONFIG_RX_FCR
 
- HSS_CONFIG_RX_LUT
 
- HSS_CONFIG_RX_PCR
 
- HSS_CONFIG_TX_FCR
 
- HSS_CONFIG_TX_LUT
 
- HSS_CONFIG_TX_PCR
 
- HSS_COUNT
 
- HSTART
 
- HSTATE_ATTR
 
- HSTATE_ATTR_RO
 
- HSTATE_FIELD
 
- HSTATE_NAME_LEN
 
- HSTATUS
 
- HSTCNTLD
 
- HSTCP_AIMD_MAX
 
- HSTDRPLT64
 
- HSTIMEOUT
 
- HSTIMEOUTENABLE
 
- HSTIM_HS_HIGH_PHASE_SHIFT
 
- HSTIM_HS_HOLD_SHIFT
 
- HSTIM_HS_MODE_MASK
 
- HSTIM_HS_SETUP_SHIFT
 
- HSTIM_OFFSET
 
- HSTL0_16mA
 
- HSTL1_8mA
 
- HSTLDCMD
 
- HSTLENCHK
 
- HSTMACADR_LSW_ADDR
 
- HSTMACADR_MSW_ADDR
 
- HSTMACRST
 
- HSTMAXFRAME_LENGTH_ADDR
 
- HSTMIIMCMD_LEN
 
- HSTMIIMCMD_POS
 
- HSTMIIMWRDAT_LEN
 
- HSTMIIMWRDAT_POS
 
- HSTPHYADX_LEN
 
- HSTPHYADX_POS
 
- HSTPPEN
 
- HSTR
 
- HSTRCTLEN
 
- HSTREGADX_LEN
 
- HSTREGADX_POS
 
- HSTRFEN
 
- HSTR_EL2_T
 
- HSTR_T
 
- HSTR_TJDBX
 
- HSTR_TTEE
 
- HSTS
 
- HSTTCTLEN
 
- HSTTFEN
 
- HSTTRGR
 
- HSTXVREGCNT
 
- HSTXVREGEN
 
- HSTX_CKLP_EN
 
- HSTX_TIMED_OUT
 
- HSTX_TIMEOUT
 
- HSTX_TIMEOUT_ERR
 
- HSTX_TIMEOUT_MAX
 
- HSTX_TIMEOUT_VALUE
 
- HSTX_TIMEOUT_VALUE_MASK
 
- HSTX_TIMEOUT_VALUE_SHIFT
 
- HSTX_TO_CNT
 
- HSTX_TRIM_MASK
 
- HSTX_TRIM_SHIFT
 
- HST_ALLOC_BUF
 
- HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT
 
- HST_CLK0_SW2_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK
 
- HST_CLK0_SW2_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT
 
- HST_CNTL1_LAST
 
- HST_CNTL1_TIMEOUT
 
- HST_CNTL2_BLOCK
 
- HST_CNTL2_BYTE
 
- HST_CNTL2_BYTE_DATA
 
- HST_CNTL2_KILL
 
- HST_CNTL2_QUICK
 
- HST_CNTL2_SIZEMASK
 
- HST_CNTL2_START
 
- HST_CNTL2_WORD_DATA
 
- HST_DEV_ACTIVATE
 
- HST_DEV_SCAN
 
- HST_DEV_SCAN_START
 
- HST_ERROR
 
- HST_GET_FW_VER
 
- HST_IDLE_EN
 
- HST_INVALID
 
- HST_PORT_SCAN
 
- HST_PROBE_FINISHED
 
- HST_PROBE_START
 
- HST_RDBUSY
 
- HST_STS_BAD
 
- HST_STS_BUSERR
 
- HST_STS_BUSY
 
- HST_STS_DEVERR
 
- HST_STS_DONE
 
- HST_STS_FAIL
 
- HST_STS_INTR
 
- HST_SYNC_TIME
 
- HSUNIT_CLKGATE_DIS
 
- HSU_CH_BSR
 
- HSU_CH_CR
 
- HSU_CH_CR_CHA
 
- HSU_CH_CR_CHD
 
- HSU_CH_D0SAR
 
- HSU_CH_D0TSR
 
- HSU_CH_D1SAR
 
- HSU_CH_D1TSR
 
- HSU_CH_D2SAR
 
- HSU_CH_D2TSR
 
- HSU_CH_D3SAR
 
- HSU_CH_D3TSR
 
- HSU_CH_DCR
 
- HSU_CH_DCR_CHDI
 
- HSU_CH_DCR_CHEI
 
- HSU_CH_DCR_CHSOD
 
- HSU_CH_DCR_CHSOE
 
- HSU_CH_DCR_CHSOTO
 
- HSU_CH_DCR_CHTOI
 
- HSU_CH_DCR_DESCA
 
- HSU_CH_DxSAR
 
- HSU_CH_DxTSR
 
- HSU_CH_DxTSR_MASK
 
- HSU_CH_DxTSR_TSR
 
- HSU_CH_MTSR
 
- HSU_CH_SR
 
- HSU_CH_SR_CDESC_ANY
 
- HSU_CH_SR_CHE
 
- HSU_CH_SR_DESCE
 
- HSU_CH_SR_DESCE_ANY
 
- HSU_CH_SR_DESCTO
 
- HSU_CH_SR_DESCTO_ANY
 
- HSU_DMA_BUSWIDTHS
 
- HSU_DMA_CHAN_LENGTH
 
- HSU_DMA_CHAN_NR_DESC
 
- HSU_PCI_CHAN_OFFSET
 
- HSU_PCI_DMAISR
 
- HSU_PCI_DMASR
 
- HSWEP_C0_MSR_PMON_BOX_CTL
 
- HSWEP_C0_MSR_PMON_BOX_FILTER0
 
- HSWEP_C0_MSR_PMON_CTL0
 
- HSWEP_C0_MSR_PMON_CTR0
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_C6
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_NC
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_NID
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE
 
- HSWEP_CB0_MSR_PMON_BOX_FILTER_TID
 
- HSWEP_CBO_MSR_OFFSET
 
- HSWEP_PCI_PCU_3
 
- HSWEP_PCI_UNCORE_HA
 
- HSWEP_PCI_UNCORE_IMC
 
- HSWEP_PCI_UNCORE_IRP
 
- HSWEP_PCI_UNCORE_QPI
 
- HSWEP_PCI_UNCORE_R2PCIE
 
- HSWEP_PCI_UNCORE_R3QPI
 
- HSWEP_PCU_MSR_PMON_BOX_CTL
 
- HSWEP_PCU_MSR_PMON_BOX_FILTER
 
- HSWEP_PCU_MSR_PMON_CTL0
 
- HSWEP_PCU_MSR_PMON_CTR0
 
- HSWEP_S0_MSR_PMON_BOX_CTL
 
- HSWEP_S0_MSR_PMON_CTL0
 
- HSWEP_S0_MSR_PMON_CTR0
 
- HSWEP_SBOX_MSR_OFFSET
 
- HSWEP_S_MSR_PMON_RAW_EVENT_MASK
 
- HSWEP_U_MSR_PMON_BOX_FILTER_CID
 
- HSWEP_U_MSR_PMON_BOX_FILTER_MASK
 
- HSWEP_U_MSR_PMON_BOX_FILTER_TID
 
- HSWEP_U_MSR_PMON_CTL0
 
- HSWEP_U_MSR_PMON_CTR0
 
- HSWEP_U_MSR_PMON_FILTER
 
- HSWEP_U_MSR_PMON_UCLK_FIXED_CTL
 
- HSWEP_U_MSR_PMON_UCLK_FIXED_CTR
 
- HSWEQ_DCN_PIXEL_RATE_REG_LIST
 
- HSWR
 
- HSW_ANY_RESPONSE
 
- HSW_ANY_SNOOP
 
- HSW_AUD_CFG
 
- HSW_AUD_CHICKENBIT
 
- HSW_AUD_DIP_ELD_CTRL
 
- HSW_AUD_EDID_DATA
 
- HSW_AUD_MISC_CTRL
 
- HSW_AUD_M_CTS_ENABLE
 
- HSW_AUD_PIN_ELD_CP_VLD
 
- HSW_AUD_PIPE_CONV_CFG
 
- HSW_BLC_PWM2_CTL
 
- HSW_CACHEABILITY_CONTROL
 
- HSW_CAGF_MASK
 
- HSW_CAGF_SHIFT
 
- HSW_CDCLK_LIMIT
 
- HSW_CPU_SSC_ENABLE
 
- HSW_CS_GPR
 
- HSW_CS_GPR_UDW
 
- HSW_CXT_TOTAL_SIZE
 
- HSW_DEMAND_DATA_RD
 
- HSW_DEMAND_READ
 
- HSW_DEMAND_RFO
 
- HSW_DEMAND_WRITE
 
- HSW_DISPLAY_POWER_DOMAINS
 
- HSW_DISP_PW_GLOBAL
 
- HSW_ECOCHK_ARB_PRIO_SOL
 
- HSW_EDP_PSR_BASE
 
- HSW_EDRAM_CAP
 
- HSW_EXT_CSTATE_COUNT
 
- HSW_F1_EU_DIS_10EUS
 
- HSW_F1_EU_DIS_6EUS
 
- HSW_F1_EU_DIS_8EUS
 
- HSW_F1_EU_DIS_MASK
 
- HSW_F1_EU_DIS_SHIFT
 
- HSW_FBCQ_DIS
 
- HSW_FORMATS
 
- HSW_FREQUENCY
 
- HSW_GTT_ADDR_ENCODE
 
- HSW_GTT_CACHE_EN
 
- HSW_IDICR
 
- HSW_IN_TX
 
- HSW_IN_TX_CHECKPOINTED
 
- HSW_L3_MISS
 
- HSW_L3_MISS_LOCAL_DRAM
 
- HSW_L3_MISS_REMOTE
 
- HSW_L3_MISS_REMOTE_HOP0
 
- HSW_L3_MISS_REMOTE_HOP1
 
- HSW_L3_MISS_REMOTE_HOP2P
 
- HSW_LLC_ACCESS
 
- HSW_MBVID2_MISR0
 
- HSW_MBVID2_NOA0
 
- HSW_MBVID2_NOA1
 
- HSW_MBVID2_NOA2
 
- HSW_MBVID2_NOA3
 
- HSW_MBVID2_NOA4
 
- HSW_MBVID2_NOA5
 
- HSW_MBVID2_NOA6
 
- HSW_MBVID2_NOA7
 
- HSW_MBVID2_NOA8
 
- HSW_MBVID2_NOA9
 
- HSW_MI_RS_RESTORE_STATE_EN
 
- HSW_MI_RS_SAVE_STATE_EN
 
- HSW_NDE_RSTWRN_OPT
 
- HSW_PAVP_FUSE1
 
- HSW_PCM_COUNT
 
- HSW_PCM_DAI_ID_LOOPBACK
 
- HSW_PCM_DAI_ID_OFFLOAD0
 
- HSW_PCM_DAI_ID_OFFLOAD1
 
- HSW_PCM_DAI_ID_SYSTEM
 
- HSW_PCM_PERIODS_MAX
 
- HSW_PCM_PERIODS_MIN
 
- HSW_PCODE_DE_WRITE_FREQ_REQ
 
- HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
 
- HSW_PIPE_OFFSETS
 
- HSW_PLATFORM
 
- HSW_PM_STATE_D0
 
- HSW_PM_STATE_D3
 
- HSW_PM_STATE_RTD3
 
- HSW_PTE_ADDR_ENCODE
 
- HSW_PTE_UNCACHED
 
- HSW_PWR_WELL_CTL1
 
- HSW_PWR_WELL_CTL2
 
- HSW_PWR_WELL_CTL3
 
- HSW_PWR_WELL_CTL4
 
- HSW_PWR_WELL_CTL5
 
- HSW_PWR_WELL_CTL6
 
- HSW_PWR_WELL_CTL_REQ
 
- HSW_PWR_WELL_CTL_STATE
 
- HSW_PWR_WELL_ENABLE_SINGLE_STEP
 
- HSW_PWR_WELL_FORCE_ON
 
- HSW_PWR_WELL_PWR_GATE_OVERRIDE
 
- HSW_PW_CTL_IDX_GLOBAL
 
- HSW_RCS_CONTEXT_ENABLE
 
- HSW_RCS_INHIBIT
 
- HSW_REF_CLK_SELECT
 
- HSW_ROW_CHICKEN3
 
- HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
 
- HSW_SAMPLE_C_PERFORMANCE
 
- HSW_SCRATCH1
 
- HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
 
- HSW_SELECTIVE_READ_ADDRESSING_MASK
 
- HSW_SELECTIVE_READ_ADDRESSING_SHIFT
 
- HSW_SELECTIVE_WRITE_ADDRESS_MASK
 
- HSW_SELECTIVE_WRITE_ADDRESS_SHIFT
 
- HSW_SNOOP_DRAM
 
- HSW_SNOOP_HITM
 
- HSW_SNOOP_HIT_NO_FWD
 
- HSW_SNOOP_HIT_WITH_FWD
 
- HSW_SNOOP_MISS
 
- HSW_SNOOP_NONE
 
- HSW_SNOOP_NON_DRAM
 
- HSW_SNOOP_NOT_NEEDED
 
- HSW_STEREO_3D_CTL
 
- HSW_SUPPLIER_NONE
 
- HSW_TVIDEO_DIP_AVI_DATA
 
- HSW_TVIDEO_DIP_CTL
 
- HSW_TVIDEO_DIP_GCP
 
- HSW_TVIDEO_DIP_GMP_DATA
 
- HSW_TVIDEO_DIP_SPD_DATA
 
- HSW_TVIDEO_DIP_VSC_DATA
 
- HSW_TVIDEO_DIP_VS_DATA
 
- HSW_VOLUME_MAX
 
- HSW_WAIT_FOR_RC6_EXIT_ENABLE
 
- HSW_WB_ELLC_LLC_AGE0
 
- HSW_WB_ELLC_LLC_AGE3
 
- HSW_WB_LLC_AGE0
 
- HSW_WB_LLC_AGE3
 
- HSW_WM_LP_VAL
 
- HSW_WT_ELLC_LLC_AGE0
 
- HSW_WT_ELLC_LLC_AGE3
 
- HSX_SPLIT_BAR_MW_COUNT
 
- HSYNC
 
- HSYNC2VSYNC_F1_L1
 
- HSYNC2VSYNC_F2_L1
 
- HSYNC2VSYNC_POL_CTRL
 
- HSYNC2VSYNC_STATUS
 
- HSYNCEND_MASK
 
- HSYNCEND_SHIFT
 
- HSYNCPOS
 
- HSYNCSTART_MASK
 
- HSYNCSTART_SHIFT
 
- HSYNC_A
 
- HSYNC_ACTIVE_LOW
 
- HSYNC_B
 
- HSYNC_C
 
- HSYNC_CNTL
 
- HSYNC_DELAY_MASK
 
- HSYNC_DELAY_SHIFT
 
- HSYNC_END
 
- HSYNC_HE_ADDR
 
- HSYNC_HIGH
 
- HSYNC_HS_ADDR
 
- HSYNC_MARK
 
- HSYNC_OFF
 
- HSYNC_ON
 
- HSYNC_POL
 
- HSYNC_POLARITY_CFG
 
- HSYNC_POSITIVE
 
- HSYNC_START
 
- HSYNC_VE_ADDR
 
- HSYNC_VS_ADDR
 
- HS_ABORTED
 
- HS_ACTIVATE
 
- HS_ACTIVATED
 
- HS_ALT_IFC_1_OFFSET
 
- HS_ATTR
 
- HS_ATTR_CFG_BLK_SIZE_MASK_
 
- HS_ATTR_DEV_DESC_SIZE_MASK_
 
- HS_ATTR_POLL_INT_MASK_
 
- HS_BLOCK
 
- HS_BULK_MAX_PACKET_SIZE
 
- HS_BUSY
 
- HS_BW_BOUNDARY
 
- HS_BW_LIMIT
 
- HS_BW_RESERVED
 
- HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF
 
- HS_CAPABILITY_SUPPORT_COMPACT_SG
 
- HS_CAPABILITY_SUPPORT_DYN_SRC
 
- HS_CAPABILITY_SUPPORT_PRD_HOST
 
- HS_CFG_CANCEL
 
- HS_CFG_COND_BROADCAST_DATA
 
- HS_CFG_COND_DEF
 
- HS_CFG_COND_MAC_EVENT
 
- HS_CFG_COND_MULTICAST_DATA
 
- HS_CFG_COND_UNICAST_DATA
 
- HS_CFG_GAP_DEF
 
- HS_CFG_GPIO_DEF
 
- HS_CHANNELS_RESERVED
 
- HS_COMPLETE
 
- HS_COMP_ERR
 
- HS_CONFIGURE
 
- HS_CRIT_TEMP
 
- HS_CSR_DHA
 
- HS_CSR_EIM
 
- HS_CSR_EXT
 
- HS_CSR_INS
 
- HS_CSR_LOO
 
- HS_CSR_PI
 
- HS_CSR_PIE
 
- HS_CTL_MAX_PACKET_SIZE
 
- HS_CTRL_FIFO_EMPTY
 
- HS_CTRL_FIFO_FULL
 
- HS_CTRL_FIFO_HALF_EMPTY
 
- HS_CURR_LEVEL
 
- HS_CURR_LEVEL_PADX_SHIFT
 
- HS_CURR_LEVEL_PAD_MASK
 
- HS_DATA_FIFO_EMPTY
 
- HS_DATA_FIFO_FULL
 
- HS_DATA_FIFO_HALF_EMPTY
 
- HS_DEACTIVATED
 
- HS_DEF_INACTIVITY_TIMEOUT
 
- HS_DEF_WAKE_INTERVAL
 
- HS_DISCONNECT
 
- HS_DIV_MASK
 
- HS_DIV_MAX
 
- HS_DIV_MAX_ODD
 
- HS_DIV_OFFSET
 
- HS_DIV_SHIFT
 
- HS_DONEMASK
 
- HS_DRV_EN_MASK
 
- HS_ENABLE
 
- HS_EXIT
 
- HS_EXIT_MASK
 
- HS_EXIT_OVERRIDE
 
- HS_EXIT_SHIFT
 
- HS_EXT_CLK_FREQ
 
- HS_FAIL
 
- HS_FFER1
 
- HS_FFER2
 
- HS_FFER3
 
- HS_FFER4
 
- HS_FFER5
 
- HS_FFER6
 
- HS_FFER7
 
- HS_FFER8
 
- HS_FFERM
 
- HS_FFRDY
 
- HS_GENERIC_WR_FIFO_FULL
 
- HS_GEN_CTRL_REG
 
- HS_GEN_DATA_REG
 
- HS_GET_STATE
 
- HS_GET_STATUS
 
- HS_GS
 
- HS_HREF_DELAY_MASK
 
- HS_HREF_DELAY_SHIFT
 
- HS_HREF_INV_SHIFT
 
- HS_HREF_PXQ_SHIFT
 
- HS_HREF_SEL_HREF_HDMI
 
- HS_HREF_SEL_HREF_VHREF
 
- HS_HREF_SEL_HS_VHREF
 
- HS_HREF_SEL_MASK
 
- HS_HREF_SEL_NONE
 
- HS_HREF_SEL_SHIFT
 
- HS_IDLE
 
- HS_INT_MAX_PACKET_SIZE
 
- HS_INVALMASK
 
- HS_INVERT_CLK
 
- HS_INVERT_DAT
 
- HS_INVOCATION_COUNT
 
- HS_INVOCATION_COUNT_UDW
 
- HS_IN_RESELECT
 
- HS_IO_CTRL_SELECT
 
- HS_ISO_MAX_PACKET_SIZE
 
- HS_LED_OFF
 
- HS_LED_ON
 
- HS_LE_16_16_SCALE
 
- HS_LP_PWR_SW_CNT_MASK
 
- HS_LP_PWR_SW_CNT_SHIFT
 
- HS_LS_DBI_ENABLE_REG
 
- HS_LT_10_16_SCALE
 
- HS_LT_11_16_SCALE
 
- HS_LT_12_16_SCALE
 
- HS_LT_13_16_SCALE
 
- HS_LT_14_16_SCALE
 
- HS_LT_15_16_SCALE
 
- HS_LT_9_16_SCALE
 
- HS_MASK
 
- HS_MBRDY
 
- HS_NEGOTIATE
 
- HS_NSECS
 
- HS_NSECS_ISO
 
- HS_OVERHEAD
 
- HS_OVERHEAD_TYPE
 
- HS_PAGE_CL_INFO
 
- HS_PAGE_FIRM_CAP
 
- HS_PAGE_FIRM_CTL
 
- HS_PAGE_HOST_INFO
 
- HS_PAGE_TOTAL
 
- HS_PAGE_VERIFY_SIZE
 
- HS_PHY_AHB_MODE
 
- HS_PHY_CTRL
 
- HS_PHY_DIG_CLAMP_N
 
- HS_PHY_GENCONFIG
 
- HS_PHY_GENCONFIG_2
 
- HS_PHY_POR_ASSERT
 
- HS_PHY_SEC_CTRL
 
- HS_PHY_SESS_VLD_CTRL_EN
 
- HS_PHY_TXFIFO_IDLE_FORCE_DIS
 
- HS_PHY_ULPI_TX_PKT_EN_CLR_FIX
 
- HS_POL_ACTIVE_LOW
 
- HS_PREP
 
- HS_PREPARE
 
- HS_PREPARE_MASK
 
- HS_PREPARE_OVERRIDE
 
- HS_PREPARE_SHIFT
 
- HS_PRIO
 
- HS_PRT
 
- HS_QUERY_SWITCH_OK
 
- HS_REG
 
- HS_REG_OFFSET
 
- HS_RESET
 
- HS_RX_CONTROL_OF_LANE_0
 
- HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE
 
- HS_SELECTING
 
- HS_SEL_TIMEOUT
 
- HS_SET_STATE
 
- HS_SET_STATUS
 
- HS_SHIFT
 
- HS_SKEWCAL_DONE
 
- HS_SKEWCAL_EN
 
- HS_SKIPMASK
 
- HS_SQUELCH_LEVEL
 
- HS_SQUELCH_MASK
 
- HS_SQUELCH_SHIFT
 
- HS_STAGE_OFF
 
- HS_STAGE_ON
 
- HS_STANDARD_ID
 
- HS_STARTING
 
- HS_STATUS_ERR
 
- HS_STATUS_INVALID
 
- HS_STATUS_OK
 
- HS_SUPPORT
 
- HS_SUPPORT_MASK
 
- HS_SWITCH_BUSY
 
- HS_S_ABORT
 
- HS_S_END
 
- HS_S_PAGE_ADDR
 
- HS_S_QUERY_PAGE
 
- HS_S_RESET
 
- HS_S_SEND_PAGE
 
- HS_S_START
 
- HS_TERM_RANGE_ADJ_MASK
 
- HS_TERM_RANGE_ADJ_SHIFT
 
- HS_TIMEOUT
 
- HS_TRAIL
 
- HS_TRAIL_MASK
 
- HS_TRAIL_OVERRIDE
 
- HS_TRAIL_SHIFT
 
- HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL
 
- HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL
 
- HS_TX_CLOCK_LANE_POST_TIME_CONTROL
 
- HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL
 
- HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL
 
- HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL
 
- HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL
 
- HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL
 
- HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL
 
- HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL
 
- HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL
 
- HS_TX_TIMEOUT
 
- HS_TX_TIMEOUT_REG
 
- HS_UNEXPECTED
 
- HS_UP_SCALE
 
- HS_USB_PKT_SIZE
 
- HS_USB_STAT
 
- HS_USECS
 
- HS_USECS_ISO
 
- HS_VCONTROL
 
- HS_VLOADM
 
- HS_VSTAIN
 
- HS_VSTAOUT
 
- HS_WAIT
 
- HS_WAKEUP_REASON
 
- HS_WIDTH
 
- HS_ZERO
 
- HS_ZERO_MASK
 
- HS_ZERO_OVERRIDE
 
- HS_ZERO_SHIFT
 
- HT
 
- HT16K33_FB_SIZE
 
- HT16K33_MATRIX_KEYPAD_MAX_COLS
 
- HT16K33_MATRIX_KEYPAD_MAX_ROWS
 
- HT16K33_MATRIX_LED_MAX_COLS
 
- HT16K33_MATRIX_LED_MAX_ROWS
 
- HT1LO_PCICFG_BASE
 
- HT1LO_PCICFG_BASE_TP1
 
- HT40_CHANNEL_CENTER_SHIFT
 
- HT40_OBSS_SCAN
 
- HT6560A
 
- HT6560B
 
- HT6560B_VERSION
 
- HTABLE_REGION_BITS
 
- HTAB_CREATE_FLAG_MASK
 
- HTAB_SIZE_MAX
 
- HTAB_SIZE_MIN
 
- HTB_CANT_SEND
 
- HTB_CAN_SEND
 
- HTB_DIRECT
 
- HTB_MAY_BORROW
 
- HTB_VER
 
- HTB_WARN_TOOMANYEVENTS
 
- HTCCheck
 
- HTCHERALD_GIRQ_BTNS
 
- HTCHERALD_GPIO_POWER
 
- HTCHERALD_GPIO_SLIDE
 
- HTCHERALD_GPIO_TS
 
- HTCHERALD_GPIO_USB_DM
 
- HTCHERALD_GPIO_USB_DP
 
- HTCHERALD_GPIO_USB_EN1
 
- HTCHERALD_GPIO_USB_EN2
 
- HTCLNG
 
- HTCPEN_IRQ
 
- HTCPEN_PORT_DATA
 
- HTCPEN_PORT_INDEX
 
- HTCPEN_PORT_INIT
 
- HTCPEN_PORT_IRQ_CLEAR
 
- HTCPLD_BASE
 
- HTCPLD_GPIO_DOWN_DPAD
 
- HTCPLD_GPIO_DOWN_KBD
 
- HTCPLD_GPIO_ENTER_DPAD
 
- HTCPLD_GPIO_INT_RESET_HI
 
- HTCPLD_GPIO_INT_RESET_LO
 
- HTCPLD_GPIO_LED_ALT
 
- HTCPLD_GPIO_LED_BT
 
- HTCPLD_GPIO_LED_CAPS
 
- HTCPLD_GPIO_LED_DPAD
 
- HTCPLD_GPIO_LED_GREEN_FLASH
 
- HTCPLD_GPIO_LED_GREEN_SOLID
 
- HTCPLD_GPIO_LED_KBD
 
- HTCPLD_GPIO_LED_RED_FLASH
 
- HTCPLD_GPIO_LED_RED_SOLID
 
- HTCPLD_GPIO_LED_VIBRATE
 
- HTCPLD_GPIO_LED_WIFI
 
- HTCPLD_GPIO_LEFT_DPAD
 
- HTCPLD_GPIO_LEFT_KBD
 
- HTCPLD_GPIO_RIGHT_DPAD
 
- HTCPLD_GPIO_RIGHT_KBD
 
- HTCPLD_GPIO_START_OFFSET
 
- HTCPLD_GPIO_UP_DPAD
 
- HTCPLD_GPIO_UP_KBD
 
- HTCPLD_IRQ
 
- HTCPLD_IRQ_DOWN_DPAD
 
- HTCPLD_IRQ_DOWN_KBD
 
- HTCPLD_IRQ_ENTER_DPAD
 
- HTCPLD_IRQ_LEFT_DPAD
 
- HTCPLD_IRQ_LEFT_KBD
 
- HTCPLD_IRQ_RIGHT_DPAD
 
- HTCPLD_IRQ_RIGHT_KBD
 
- HTCPLD_IRQ_UP_DPAD
 
- HTCPLD_IRQ_UP_KBD
 
- HTCR
 
- HTCR_MASK
 
- HTC_7010_MODULE_FW
 
- HTC_9271_MODULE_FW
 
- HTC_CONFIG__CSR_ADDR_MASK
 
- HTC_CONFIG__CSR_ADDR__SHIFT
 
- HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK
 
- HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT
 
- HTC_CONFIG__Reserved_MASK
 
- HTC_CONFIG__Reserved__SHIFT
 
- HTC_CONFIG__TCEN_ID_MASK
 
- HTC_CONFIG__TCEN_ID__SHIFT
 
- HTC_CONN_FLGS_DISABLE_CRED_FLOW_CTRL
 
- HTC_CONN_FLGS_REDUCE_CRED_DRIB
 
- HTC_CONN_FLGS_SET_RECV_ALLOC_MASK
 
- HTC_CONN_FLGS_SET_RECV_ALLOC_SHIFT
 
- HTC_CONN_FLGS_THRESH_LVL_HALF
 
- HTC_CONN_FLGS_THRESH_LVL_QUAT
 
- HTC_CONN_FLGS_THRESH_LVL_THREE_QUAT
 
- HTC_CONN_FLGS_THRESH_MASK
 
- HTC_CONTROL_BUFFER_SIZE
 
- HTC_CREDIT_DIST_ACTIVITY_CHANGE
 
- HTC_CREDIT_DIST_SEEK_CREDITS
 
- HTC_CREDIT_DIST_SEND_COMPLETE
 
- HTC_CTRL_RSVD_SVC
 
- HTC_EGPIO_INPUT
 
- HTC_EGPIO_OUTPUT
 
- HTC_ENABLE
 
- HTC_EP_ACTIVE
 
- HTC_FLAGS_NEED_CREDIT_UPDATE
 
- HTC_FLAGS_RECV_TRAILER
 
- HTC_FLAGS_SEND_BUNDLE
 
- HTC_FLAGS_TX_FIXUP_NETBUF
 
- HTC_FLGS_TX_BNDL_PAD_EN
 
- HTC_FLG_RX_BNDL_CNT
 
- HTC_FLG_RX_BNDL_CNT_S
 
- HTC_FLG_RX_TRAILER
 
- HTC_FLG_RX_UNUSED
 
- HTC_FWFLAG_NO_RMW
 
- HTC_FW_PATH
 
- HTC_H
 
- HTC_HDR_LENGTH
 
- HTC_HOST_MAX_MSG_PER_BUNDLE
 
- HTC_HOST_MAX_MSG_PER_RX_BUNDLE
 
- HTC_HST_H
 
- HTC_LOC_CTRL
 
- HTC_LOOPBACK_RSVD_SVC
 
- HTC_MAILBOX
 
- HTC_MAILBOX_NUM_MAX
 
- HTC_MAX_CONTROL_MESSAGE_LENGTH
 
- HTC_MAX_CTRL_MSG_LEN
 
- HTC_MAX_PAYLOAD_LENGTH
 
- HTC_MAX_TX_STATUS
 
- HTC_MIN_HTC_MSGS_TO_BUNDLE
 
- HTC_MODE_11NA
 
- HTC_MODE_11NG
 
- HTC_MSG_CONFIG_PIPE_ID
 
- HTC_MSG_CONFIG_PIPE_RESPONSE_ID
 
- HTC_MSG_CONNECT_SERVICE_ID
 
- HTC_MSG_CONNECT_SERVICE_RESPONSE_ID
 
- HTC_MSG_CONN_SVC_ID
 
- HTC_MSG_CONN_SVC_RESP_ID
 
- HTC_MSG_READY_ID
 
- HTC_MSG_SETUP_COMPLETE_EX_ID
 
- HTC_MSG_SETUP_COMPLETE_ID
 
- HTC_M_AHDEMO
 
- HTC_M_HOSTAP
 
- HTC_M_IBSS
 
- HTC_M_MONITOR
 
- HTC_M_STA
 
- HTC_M_WDS
 
- HTC_OPS_H
 
- HTC_OP_CONFIG_PIPE_CREDITS
 
- HTC_OP_START_WAIT
 
- HTC_OP_STATE_SETUP_COMPLETE
 
- HTC_OP_STATE_STOPPING
 
- HTC_PACKET_CONTAINER_ALLOCATION
 
- HTC_PROTOCOL_VERSION
 
- HTC_RECORD_CREDITS
 
- HTC_RECORD_LOOKAHEAD
 
- HTC_RECORD_LOOKAHEAD_BUNDLE
 
- HTC_RECORD_NULL
 
- HTC_RECV_WAIT_BUFFERS
 
- HTC_RX_FLAGS_INDICATE_MORE_PKTS
 
- HTC_RX_FRAME_HEADER_SIZE
 
- HTC_RX_PKT_IGNORE_LOOKAHEAD
 
- HTC_RX_PKT_NO_RECYCLE
 
- HTC_RX_PKT_PART_OF_BUNDLE
 
- HTC_RX_PKT_REFRESH_HDR
 
- HTC_SEND_FULL_DROP
 
- HTC_SEND_FULL_KEEP
 
- HTC_SEND_QUEUE_DROP
 
- HTC_SEND_QUEUE_OK
 
- HTC_SERVICE_FAILED
 
- HTC_SERVICE_GROUP_LAST
 
- HTC_SERVICE_META_DATA_MAX_LENGTH
 
- HTC_SERVICE_NOT_FOUND
 
- HTC_SERVICE_NO_MORE_EP
 
- HTC_SERVICE_NO_RESOURCES
 
- HTC_SERVICE_SUCCESS
 
- HTC_SERVICE_TX_PACKET_TAG
 
- HTC_SETUP_COMP_FLG_DISABLE_TX_CREDIT_FLOW
 
- HTC_SETUP_COMP_FLG_RX_BNDL_EN
 
- HTC_SKB_CB
 
- HTC_TARGET_CREDIT_INTR_MASK
 
- HTC_TARGET_DEBUG_INTR_MASK
 
- HTC_TARGET_RESPONSE_POLL_COUNT
 
- HTC_TARGET_RESPONSE_POLL_WAIT
 
- HTC_TARGET_RESPONSE_TIMEOUT
 
- HTC_TEST_GROUP
 
- HTC_TX_PACKET_TAG_ALL
 
- HTC_TX_PACKET_TAG_USER_DEFINED
 
- HTC_USB_H
 
- HTC_VERSION_2P0
 
- HTC_VERSION_2P1
 
- HTConstructCapabilityElement
 
- HTConstructInfoElement
 
- HTConstructRT2RTAggElement
 
- HTDebugHTCapability
 
- HTDebugHTInfo
 
- HTEN
 
- HTFilterMCSRate
 
- HTGetHighestMCSRate
 
- HTH
 
- HTIM01
 
- HTIM02
 
- HTIM1
 
- HTIM2
 
- HTIOTActDetermineRaFunc
 
- HTIOTActIsCCDFsync
 
- HTIOTActIsDisableEDCATurbo
 
- HTIOTActIsDisableMCS14
 
- HTIOTActIsDisableMCS15
 
- HTIOTActIsDisableMCSTwoSpatialStream
 
- HTIOTActIsMgntUseCCK6M
 
- HTIOTPeerDetermine
 
- HTInitializeBssDesc
 
- HTInitializeHTInfo
 
- HTLB_16G_INDEX
 
- HTLB_16M_INDEX
 
- HTLB_BUDDY_PGALLOC
 
- HTLB_BUDDY_PGALLOC_FAIL
 
- HTL_CTRL
 
- HTM_A
 
- HTM_R
 
- HTM_SI
 
- HTMcsToDataRate
 
- HTOSDATADELAY
 
- HTOTAL
 
- HTOTAL2_CNTL
 
- HTOTAL_A
 
- HTOTAL_B
 
- HTOTAL_C
 
- HTOTAL_CNTL
 
- HTOTAL_MASK
 
- HTOTAL_SHIFT
 
- HTOnAssocRsp
 
- HTPHY_MMPLCPLen
 
- HTPHY_RXPWR_ANT0
 
- HTPHY_RXPWR_ANT1
 
- HTPHY_RXPWR_ANT2
 
- HTPIDR
 
- HTPLG_PIN_SEL_OFF
 
- HTPR
 
- HTRANS_MODE
 
- HTResetIOTSetting
 
- HTResetSelfAndSavePeerSetting
 
- HTS221_AVG_DEPTH
 
- HTS221_BDU_MASK
 
- HTS221_DATA_SIZE
 
- HTS221_DEV_NAME
 
- HTS221_ENABLE_MASK
 
- HTS221_H
 
- HTS221_HUMIDITY_AVG_MASK
 
- HTS221_I2C_AUTO_INCREMENT
 
- HTS221_ODR_MASK
 
- HTS221_REG_0RH_CAL_X_H
 
- HTS221_REG_0RH_CAL_Y_H
 
- HTS221_REG_0T_CAL_X_L
 
- HTS221_REG_0T_CAL_Y_H
 
- HTS221_REG_1RH_CAL_X_H
 
- HTS221_REG_1RH_CAL_Y_H
 
- HTS221_REG_1T_CAL_X_L
 
- HTS221_REG_1T_CAL_Y_H
 
- HTS221_REG_AVG_ADDR
 
- HTS221_REG_CNTRL1_ADDR
 
- HTS221_REG_CNTRL2_ADDR
 
- HTS221_REG_DRDY_EN_ADDR
 
- HTS221_REG_DRDY_EN_MASK
 
- HTS221_REG_DRDY_HL_ADDR
 
- HTS221_REG_DRDY_HL_MASK
 
- HTS221_REG_DRDY_PP_OD_ADDR
 
- HTS221_REG_DRDY_PP_OD_MASK
 
- HTS221_REG_H_OUT_L
 
- HTS221_REG_STATUS_ADDR
 
- HTS221_REG_T1_T0_CAL_Y_H
 
- HTS221_REG_T_OUT_L
 
- HTS221_REG_WHOAMI_ADDR
 
- HTS221_REG_WHOAMI_VAL
 
- HTS221_RH_DRDY_MASK
 
- HTS221_SENSOR_H
 
- HTS221_SENSOR_MAX
 
- HTS221_SENSOR_T
 
- HTS221_SPI_AUTO_INCREMENT
 
- HTS221_SPI_READ
 
- HTS221_TEMP_AVG_MASK
 
- HTS221_TEMP_DRDY_MASK
 
- HTS2_PPL_MASK
 
- HTS2_PRST_MASK
 
- HTS2_PRST_RUNNING
 
- HTS2_PRST_SHIFT
 
- HTS2_PRST_TDISERR
 
- HTS2_PRST_TDISHT
 
- HTS2_PRST_TDISOP
 
- HTS2_PRST_TDISPLAT
 
- HTS2_PRST_TDISPM
 
- HTS2_PRST_TDISUSR
 
- HTS2_PRST_UNLOADED
 
- HTSIZE
 
- HTS_GPL_MASK
 
- HTS_GPL_SHIFT
 
- HTS_GTD_DIS
 
- HTS_NVV
 
- HTS_PCPL_MASK
 
- HTS_PCPL_SHIFT
 
- HTS_PCTD_DIS
 
- HTS_PP_BAL
 
- HTS_PP_DEF
 
- HTS_PP_GFX
 
- HTS_PP_MASK
 
- HTS_PP_PROC
 
- HTS_PP_SHIFT
 
- HTS_PTL_MASK
 
- HTS_PTL_SHIFT
 
- HTSetConnectBwMode
 
- HTSetConnectBwModeCallback
 
- HTT_10X_T2H_MSG_TYPE_AGGR_CONF
 
- HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE
 
- HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
 
- HTT_10X_T2H_MSG_TYPE_PEER_MAP
 
- HTT_10X_T2H_MSG_TYPE_PEER_UNMAP
 
- HTT_10X_T2H_MSG_TYPE_PKTLOG
 
- HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND
 
- HTT_10X_T2H_MSG_TYPE_RX_ADDBA
 
- HTT_10X_T2H_MSG_TYPE_RX_DELBA
 
- HTT_10X_T2H_MSG_TYPE_RX_FLUSH
 
- HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND
 
- HTT_10X_T2H_MSG_TYPE_RX_IND
 
- HTT_10X_T2H_MSG_TYPE_SEC_IND
 
- HTT_10X_T2H_MSG_TYPE_STATS_CONF
 
- HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD
 
- HTT_10X_T2H_MSG_TYPE_TEST
 
- HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND
 
- HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND
 
- HTT_10X_T2H_MSG_TYPE_VERSION_CONF
 
- HTT_10X_T2H_NUM_MSGS
 
- HTT_10_4_T2H_MSG_TYPE_AGGR_CONF
 
- HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE
 
- HTT_10_4_T2H_MSG_TYPE_EN_STATS
 
- HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
 
- HTT_10_4_T2H_MSG_TYPE_PEER_MAP
 
- HTT_10_4_T2H_MSG_TYPE_PEER_STATS
 
- HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP
 
- HTT_10_4_T2H_MSG_TYPE_PKTLOG
 
- HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND
 
- HTT_10_4_T2H_MSG_TYPE_RX_ADDBA
 
- HTT_10_4_T2H_MSG_TYPE_RX_DELBA
 
- HTT_10_4_T2H_MSG_TYPE_RX_FLUSH
 
- HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND
 
- HTT_10_4_T2H_MSG_TYPE_RX_IND
 
- HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
 
- HTT_10_4_T2H_MSG_TYPE_RX_PN_IND
 
- HTT_10_4_T2H_MSG_TYPE_SEC_IND
 
- HTT_10_4_T2H_MSG_TYPE_STATS_CONF
 
- HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD
 
- HTT_10_4_T2H_MSG_TYPE_TEST
 
- HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND
 
- HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
 
- HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM
 
- HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND
 
- HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND
 
- HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND
 
- HTT_10_4_T2H_MSG_TYPE_VERSION_CONF
 
- HTT_10_4_T2H_NUM_MSGS
 
- HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT
 
- HTT_DATA_TX_DESC_FLAGS0_NO_AGGR
 
- HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY
 
- HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT
 
- HTT_DATA_TX_DESC_FLAGS0_RSVD0
 
- HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD
 
- HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD
 
- HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS
 
- HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB
 
- HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK
 
- HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH
 
- HTT_DATA_TX_DESC_FLAGS1_POSTPONED
 
- HTT_DATA_TX_DESC_FLAGS1_RSVD1
 
- HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS
 
- HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB
 
- HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK
 
- HTT_DATA_TX_EXT_TID_INVALID
 
- HTT_DATA_TX_EXT_TID_MGMT
 
- HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST
 
- HTT_DATA_TX_STATUS_DISCARD
 
- HTT_DATA_TX_STATUS_DOWNLOAD_FAIL
 
- HTT_DATA_TX_STATUS_LSB
 
- HTT_DATA_TX_STATUS_MASK
 
- HTT_DATA_TX_STATUS_NO_ACK
 
- HTT_DATA_TX_STATUS_OK
 
- HTT_DATA_TX_STATUS_POSTPONE
 
- HTT_DATA_TX_TID_INVALID
 
- HTT_DATA_TX_TID_LSB
 
- HTT_DATA_TX_TID_MASK
 
- HTT_DBG_NUM_STATS
 
- HTT_DBG_STATS_RX_RATE_INFO
 
- HTT_DBG_STATS_RX_REORDER
 
- HTT_DBG_STATS_STATUS_ERROR
 
- HTT_DBG_STATS_STATUS_INVALID
 
- HTT_DBG_STATS_STATUS_PARTIAL
 
- HTT_DBG_STATS_STATUS_PRESENT
 
- HTT_DBG_STATS_STATUS_SERIES_DONE
 
- HTT_DBG_STATS_TX_PPDU_LOG
 
- HTT_DBG_STATS_TX_RATE_INFO
 
- HTT_DBG_STATS_WAL_PDEV_TXRX
 
- HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB
 
- HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK
 
- HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB
 
- HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK
 
- HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID
 
- HTT_FRAG_DESC_BANK_CFG_INFO_SWAP
 
- HTT_FRAG_DESC_BANK_MAX
 
- HTT_H2T_MSG_TYPE_AGGR_CFG
 
- HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG
 
- HTT_H2T_MSG_TYPE_MGMT_TX
 
- HTT_H2T_MSG_TYPE_RX_RING_CFG
 
- HTT_H2T_MSG_TYPE_STATS_REQ
 
- HTT_H2T_MSG_TYPE_SYNC
 
- HTT_H2T_MSG_TYPE_TX_FETCH_RESP
 
- HTT_H2T_MSG_TYPE_TX_FRM
 
- HTT_H2T_MSG_TYPE_VERSION_REQ
 
- HTT_H2T_NUM_MSGS
 
- HTT_INVALID_PEERID
 
- HTT_LOG2_MAX_CACHE_LINE_SIZE
 
- HTT_MAC_ADDR_LEN
 
- HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
 
- HTT_MAIN_T2H_MSG_TYPE_PEER_MAP
 
- HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP
 
- HTT_MAIN_T2H_MSG_TYPE_PKTLOG
 
- HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA
 
- HTT_MAIN_T2H_MSG_TYPE_RX_DELBA
 
- HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH
 
- HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND
 
- HTT_MAIN_T2H_MSG_TYPE_RX_IND
 
- HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
 
- HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND
 
- HTT_MAIN_T2H_MSG_TYPE_SEC_IND
 
- HTT_MAIN_T2H_MSG_TYPE_STATS_CONF
 
- HTT_MAIN_T2H_MSG_TYPE_TEST
 
- HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND
 
- HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
 
- HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND
 
- HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF
 
- HTT_MAIN_T2H_NUM_MSGS
 
- HTT_MAX_CACHE_LINE_SIZE_MASK
 
- HTT_MGMT_FRM_HDR_DOWNLOAD_LEN
 
- HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI
 
- HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK
 
- HTT_MGMT_TX_STATUS_DROP
 
- HTT_MGMT_TX_STATUS_OK
 
- HTT_MGMT_TX_STATUS_RETRY
 
- HTT_MSDU_CHECKSUM_ENABLE
 
- HTT_MSDU_CHECKSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE
 
- HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE
 
- HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE
 
- HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE
 
- HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64
 
- HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE
 
- HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64
 
- HTT_NUM_SECURITY_TYPES
 
- HTT_Q_DEPTH_TYPE_BYTES
 
- HTT_Q_DEPTH_TYPE_MSDUS
 
- HTT_RESP_HDR_MSG_TYPE_LSB
 
- HTT_RESP_HDR_MSG_TYPE_MASK
 
- HTT_RESP_HDR_MSG_TYPE_OFFSET
 
- HTT_RX_BA_INFO0_PEER_ID_LSB
 
- HTT_RX_BA_INFO0_PEER_ID_MASK
 
- HTT_RX_BA_INFO0_TID_LSB
 
- HTT_RX_BA_INFO0_TID_MASK
 
- HTT_RX_BUF_SIZE
 
- HTT_RX_CCK_11_LP
 
- HTT_RX_CCK_11_SP
 
- HTT_RX_CCK_1_LP
 
- HTT_RX_CCK_2_LP
 
- HTT_RX_CCK_2_SP
 
- HTT_RX_CCK_5_5_LP
 
- HTT_RX_CCK_5_5_SP
 
- HTT_RX_DESC_ALIGN
 
- HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB
 
- HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK
 
- HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB
 
- HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK
 
- HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB
 
- HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK
 
- HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB
 
- HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK
 
- HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB
 
- HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK
 
- HTT_RX_FLUSH_MPDU_DISCARD
 
- HTT_RX_FLUSH_MPDU_REORDER
 
- HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB
 
- HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK
 
- HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB
 
- HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK
 
- HTT_RX_FRAG_IND_INFO0_HEADER_LEN
 
- HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB
 
- HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK
 
- HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB
 
- HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK
 
- HTT_RX_HT
 
- HTT_RX_HT_WITH_TXBF
 
- HTT_RX_INDICATION_INFO0_END_VALID
 
- HTT_RX_INDICATION_INFO0_EXT_TID_LSB
 
- HTT_RX_INDICATION_INFO0_EXT_TID_MASK
 
- HTT_RX_INDICATION_INFO0_FLUSH_VALID
 
- HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK
 
- HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB
 
- HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK
 
- HTT_RX_INDICATION_INFO0_PHY_ERR_VALID
 
- HTT_RX_INDICATION_INFO0_PPDU_DURATION
 
- HTT_RX_INDICATION_INFO0_RELEASE_VALID
 
- HTT_RX_INDICATION_INFO0_START_VALID
 
- HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB
 
- HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK
 
- HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB
 
- HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK
 
- HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB
 
- HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK
 
- HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB
 
- HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK
 
- HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB
 
- HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK
 
- HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB
 
- HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK
 
- HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB
 
- HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK
 
- HTT_RX_INDICATION_INFO2_SERVICE_LSB
 
- HTT_RX_INDICATION_INFO2_SERVICE_MASK
 
- HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB
 
- HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK
 
- HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR
 
- HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR
 
- HTT_RX_IND_MPDU_STATUS_ERR_DUP
 
- HTT_RX_IND_MPDU_STATUS_ERR_FCS
 
- HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER
 
- HTT_RX_IND_MPDU_STATUS_ERR_MISC
 
- HTT_RX_IND_MPDU_STATUS_ERR_REPLAY
 
- HTT_RX_IND_MPDU_STATUS_MGMT_CTRL
 
- HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR
 
- HTT_RX_IND_MPDU_STATUS_OK
 
- HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC
 
- HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR
 
- HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR
 
- HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER
 
- HTT_RX_IND_MPDU_STATUS_UNKNOWN
 
- HTT_RX_IN_ORD_IND_INFO_FRAG_LSB
 
- HTT_RX_IN_ORD_IND_INFO_FRAG_MASK
 
- HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB
 
- HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK
 
- HTT_RX_IN_ORD_IND_INFO_TID_LSB
 
- HTT_RX_IN_ORD_IND_INFO_TID_MASK
 
- HTT_RX_LEGACY
 
- HTT_RX_LEGACY_RATE_CCK
 
- HTT_RX_LEGACY_RATE_OFDM
 
- HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2
 
- HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2
 
- HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2
 
- HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2
 
- HTT_RX_MPDU_ENCRYPT_NONE
 
- HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC
 
- HTT_RX_MPDU_ENCRYPT_TKIP_WPA
 
- HTT_RX_MPDU_ENCRYPT_WAPI
 
- HTT_RX_MPDU_ENCRYPT_WEP104
 
- HTT_RX_MPDU_ENCRYPT_WEP128
 
- HTT_RX_MPDU_ENCRYPT_WEP40
 
- HTT_RX_MSDU_SIZE
 
- HTT_RX_NON_PN_CHECK
 
- HTT_RX_NON_TKIP_MIC
 
- HTT_RX_OFDM_12
 
- HTT_RX_OFDM_18
 
- HTT_RX_OFDM_24
 
- HTT_RX_OFDM_36
 
- HTT_RX_OFDM_48
 
- HTT_RX_OFDM_54
 
- HTT_RX_OFDM_6
 
- HTT_RX_OFDM_9
 
- HTT_RX_PN_CHECK
 
- HTT_RX_PPDU_START_PREAMBLE_HT
 
- HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF
 
- HTT_RX_PPDU_START_PREAMBLE_LEGACY
 
- HTT_RX_PPDU_START_PREAMBLE_VHT
 
- HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF
 
- HTT_RX_RING_FILL_LEVEL
 
- HTT_RX_RING_FILL_LEVEL_DUAL_MAC
 
- HTT_RX_RING_FLAGS_CTRL_RX
 
- HTT_RX_RING_FLAGS_FRAG_INFO
 
- HTT_RX_RING_FLAGS_MAC80211_HDR
 
- HTT_RX_RING_FLAGS_MGMT_RX
 
- HTT_RX_RING_FLAGS_MPDU_END
 
- HTT_RX_RING_FLAGS_MPDU_START
 
- HTT_RX_RING_FLAGS_MSDU_END
 
- HTT_RX_RING_FLAGS_MSDU_PAYLOAD
 
- HTT_RX_RING_FLAGS_MSDU_START
 
- HTT_RX_RING_FLAGS_MULTICAST_RX
 
- HTT_RX_RING_FLAGS_NULL_RX
 
- HTT_RX_RING_FLAGS_PHY_DATA_RX
 
- HTT_RX_RING_FLAGS_PPDU_END
 
- HTT_RX_RING_FLAGS_PPDU_START
 
- HTT_RX_RING_FLAGS_RX_ATTENTION
 
- HTT_RX_RING_FLAGS_UNICAST_RX
 
- HTT_RX_RING_REFILL_RESCHED_MS
 
- HTT_RX_RING_REFILL_RETRY_MS
 
- HTT_RX_RING_SIZE
 
- HTT_RX_RING_SIZE_MAX
 
- HTT_RX_RING_SIZE_MIN
 
- HTT_RX_TKIP_MIC
 
- HTT_RX_VHT
 
- HTT_RX_VHT_WITH_TXBF
 
- HTT_SECURITY_AES_CCMP
 
- HTT_SECURITY_IS_UNICAST
 
- HTT_SECURITY_NONE
 
- HTT_SECURITY_TKIP
 
- HTT_SECURITY_TKIP_NOMIC
 
- HTT_SECURITY_TYPE_LSB
 
- HTT_SECURITY_TYPE_MASK
 
- HTT_SECURITY_WAPI
 
- HTT_SECURITY_WEP104
 
- HTT_SECURITY_WEP128
 
- HTT_SECURITY_WEP40
 
- HTT_STATS_BIT_MASK
 
- HTT_STATS_CONF_ITEM_INFO_STATUS_LSB
 
- HTT_STATS_CONF_ITEM_INFO_STATUS_MASK
 
- HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB
 
- HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK
 
- HTT_STATS_REQ_CFG_STAT_TYPE_INVALID
 
- HTT_T2H_MSG_TYPE_AGGR_CONF
 
- HTT_T2H_MSG_TYPE_CHAN_CHANGE
 
- HTT_T2H_MSG_TYPE_EN_STATS
 
- HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION
 
- HTT_T2H_MSG_TYPE_PEER_MAP
 
- HTT_T2H_MSG_TYPE_PEER_STATS
 
- HTT_T2H_MSG_TYPE_PEER_UNMAP
 
- HTT_T2H_MSG_TYPE_PKTLOG
 
- HTT_T2H_MSG_TYPE_RC_UPDATE_IND
 
- HTT_T2H_MSG_TYPE_RX_ADDBA
 
- HTT_T2H_MSG_TYPE_RX_DELBA
 
- HTT_T2H_MSG_TYPE_RX_FLUSH
 
- HTT_T2H_MSG_TYPE_RX_FRAG_IND
 
- HTT_T2H_MSG_TYPE_RX_IND
 
- HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND
 
- HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
 
- HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR
 
- HTT_T2H_MSG_TYPE_RX_PN_IND
 
- HTT_T2H_MSG_TYPE_SEC_IND
 
- HTT_T2H_MSG_TYPE_STATS_CONF
 
- HTT_T2H_MSG_TYPE_STATS_NOUPLOAD
 
- HTT_T2H_MSG_TYPE_TEST
 
- HTT_T2H_MSG_TYPE_TX_COMPL_IND
 
- HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
 
- HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM
 
- HTT_T2H_MSG_TYPE_TX_FETCH_IND
 
- HTT_T2H_MSG_TYPE_TX_INSPECT_IND
 
- HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND
 
- HTT_T2H_MSG_TYPE_VERSION_CONF
 
- HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE
 
- HTT_T2H_NUM_MSGS
 
- HTT_TARGET_VERSION_TIMEOUT_HZ
 
- HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE
 
- HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND
 
- HTT_TLV_T2H_MSG_TYPE_PEER_MAP
 
- HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP
 
- HTT_TLV_T2H_MSG_TYPE_PKTLOG
 
- HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND
 
- HTT_TLV_T2H_MSG_TYPE_RX_ADDBA
 
- HTT_TLV_T2H_MSG_TYPE_RX_DELBA
 
- HTT_TLV_T2H_MSG_TYPE_RX_FLUSH
 
- HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND
 
- HTT_TLV_T2H_MSG_TYPE_RX_IND
 
- HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND
 
- HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND
 
- HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR
 
- HTT_TLV_T2H_MSG_TYPE_RX_PN_IND
 
- HTT_TLV_T2H_MSG_TYPE_SEC_IND
 
- HTT_TLV_T2H_MSG_TYPE_STATS_CONF
 
- HTT_TLV_T2H_MSG_TYPE_TEST
 
- HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND
 
- HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND
 
- HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND
 
- HTT_TLV_T2H_MSG_TYPE_VERSION_CONF
 
- HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE
 
- HTT_TLV_T2H_NUM_MSGS
 
- HTT_TXRX_SEC_MCAST
 
- HTT_TXRX_SEC_UCAST
 
- HTT_TX_CMPL_FLAG_DATA_RSSI
 
- HTT_TX_CMPL_FLAG_PA_PRESENT
 
- HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT
 
- HTT_TX_CMPL_FLAG_PPID_PRESENT
 
- HTT_TX_COMPL_INV_MSDU_ID
 
- HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK
 
- HTT_TX_COMPL_STATE_ACK
 
- HTT_TX_COMPL_STATE_DISCARD
 
- HTT_TX_COMPL_STATE_NOACK
 
- HTT_TX_COMPL_STATE_NONE
 
- HTT_TX_DATA_APPEND_RETRIES
 
- HTT_TX_DATA_APPEND_TIMESTAMP
 
- HTT_TX_DATA_RSSI_ENABLE_WCN3990
 
- HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB
 
- HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK
 
- HTT_TX_FETCH_RECORD_INFO_TID_LSB
 
- HTT_TX_FETCH_RECORD_INFO_TID_MASK
 
- HTT_TX_HL_NEEDED_HEADROOM
 
- HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE
 
- HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB
 
- HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK
 
- HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB
 
- HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK
 
- HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB
 
- HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK
 
- HTT_TX_MODE_SWITCH_PUSH
 
- HTT_TX_MODE_SWITCH_PUSH_PULL
 
- HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB
 
- HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK
 
- HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB
 
- HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK
 
- HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK
 
- HTT_TX_PPDU_DUR_INFO0_TID_MASK
 
- HTT_TX_Q_STATE_ENTRY_COEFFICIENT
 
- HTT_TX_Q_STATE_ENTRY_EXP_LSB
 
- HTT_TX_Q_STATE_ENTRY_EXP_MASK
 
- HTT_TX_Q_STATE_ENTRY_FACTOR_LSB
 
- HTT_TX_Q_STATE_ENTRY_FACTOR_MASK
 
- HTT_TX_Q_STATE_ENTRY_MULTIPLIER
 
- HTT_TX_Q_STATE_ENTRY_SIZE
 
- HTT_TX_Q_STATE_NUM_PEERS
 
- HTT_TX_Q_STATE_NUM_TIDS
 
- HTU21
 
- HTU21_RESET
 
- HTUpdateDefaultSetting
 
- HTUpdateSelfAndPeerSetting
 
- HTUseDefaultSetting
 
- HTW
 
- HTWDEEF
 
- HTWDEEF_MASK
 
- HTWDEEF_SHIFT
 
- HTWSEEF
 
- HTWSEEF_MASK
 
- HTWSEEF_SHIFT
 
- HTW_MASK
 
- HTW_SHIFT
 
- HTX0_A_MARK
 
- HTX0_B_MARK
 
- HTX0_C_MARK
 
- HTX0_D_MARK
 
- HTX0_E_MARK
 
- HTX0_F_MARK
 
- HTX0_MARK
 
- HTX1_A_MARK
 
- HTX1_B_MARK
 
- HTX1_C_MARK
 
- HTX1_D_MARK
 
- HTX1_MARK
 
- HTX2_B_MARK
 
- HTX2_C_MARK
 
- HTX2_D_MARK
 
- HTX2_MARK
 
- HTYPE
 
- HT_3BIT_CAP_MASK
 
- HT_5BIT_CAP_MASK
 
- HT_AGGRE_MODE_E
 
- HT_AGGRE_SIZE_E
 
- HT_AGG_AUTO
 
- HT_AGG_BURST_RETRIES
 
- HT_AGG_FORCE_DISABLE
 
- HT_AGG_FORCE_ENABLE
 
- HT_AGG_MAX_RETRIES
 
- HT_AGG_RETRIES_PERIOD
 
- HT_AGG_SIZE_16K
 
- HT_AGG_SIZE_32K
 
- HT_AGG_SIZE_64K
 
- HT_AGG_SIZE_8K
 
- HT_AGG_STATE_DRV_READY
 
- HT_AGG_STATE_OPERATIONAL
 
- HT_AGG_STATE_RESPONSE_RECEIVED
 
- HT_AGG_STATE_START_CB
 
- HT_AGG_STATE_STOPPING
 
- HT_AGG_STATE_STOP_CB
 
- HT_AGG_STATE_WANT_START
 
- HT_AGG_STATE_WANT_STOP
 
- HT_BASIC_RATE
 
- HT_BRIDGE_DEVICE
 
- HT_BW_20
 
- HT_BW_40
 
- HT_CAPTYPE_DIRECT_ROUTE
 
- HT_CAPTYPE_ERROR_RETRY
 
- HT_CAPTYPE_EXTCONF
 
- HT_CAPTYPE_GEN3
 
- HT_CAPTYPE_HOST
 
- HT_CAPTYPE_IRQ
 
- HT_CAPTYPE_MSI_MAPPING
 
- HT_CAPTYPE_PM
 
- HT_CAPTYPE_REMAPPING_40
 
- HT_CAPTYPE_REMAPPING_64
 
- HT_CAPTYPE_SLAVE
 
- HT_CAPTYPE_UNITID_CLUMP
 
- HT_CAPTYPE_VCSET
 
- HT_CAP_AMPDU_FACTOR
 
- HT_CAP_RX_STBC_NO
 
- HT_CAP_RX_STBC_ONE_STREAM
 
- HT_CAP_SIZEOF_LONG
 
- HT_CAP_SIZEOF_SHORT
 
- HT_CFG_SPACE
 
- HT_CHANNEL_WIDTH
 
- HT_CHANNEL_WIDTH_10
 
- HT_CHANNEL_WIDTH_160
 
- HT_CHANNEL_WIDTH_20
 
- HT_CHANNEL_WIDTH_20_40
 
- HT_CHANNEL_WIDTH_40
 
- HT_CHANNEL_WIDTH_80
 
- HT_CHANNEL_WIDTH_MAX
 
- HT_CONFIG
 
- HT_CONFIG_DEFAULT
 
- HT_CONFIG_PORT
 
- HT_CTRL_CFG
 
- HT_CXLFLASH_AFU_DEBUG
 
- HT_CXLFLASH_AFU_DEBUG_MAX_DATA_LEN
 
- HT_CXLFLASH_AFU_DEBUG_SUBCMD_LEN
 
- HT_CXLFLASH_HOST_READ
 
- HT_CXLFLASH_HOST_WRITE
 
- HT_CXLFLASH_LUN_PROVISION
 
- HT_CXLFLASH_LUN_PROVISION_SUBCMD_CREATE_LUN
 
- HT_CXLFLASH_LUN_PROVISION_SUBCMD_DELETE_LUN
 
- HT_CXLFLASH_LUN_PROVISION_SUBCMD_QUERY_PORT
 
- HT_CXLFLASH_VERSION_0
 
- HT_ERRCTRL_DETECTED
 
- HT_ERRCTRL_ENABLE
 
- HT_EXTCHNL_OFFSET_LOWER
 
- HT_EXTCHNL_OFFSET_NO_DEF
 
- HT_EXTCHNL_OFFSET_NO_EXT
 
- HT_EXTCHNL_OFFSET_UPPER
 
- HT_FBK_CFG0
 
- HT_FBK_CFG0_HTMCS0FBK
 
- HT_FBK_CFG0_HTMCS1FBK
 
- HT_FBK_CFG0_HTMCS2FBK
 
- HT_FBK_CFG0_HTMCS3FBK
 
- HT_FBK_CFG0_HTMCS4FBK
 
- HT_FBK_CFG0_HTMCS5FBK
 
- HT_FBK_CFG0_HTMCS6FBK
 
- HT_FBK_CFG0_HTMCS7FBK
 
- HT_FBK_CFG1
 
- HT_FBK_CFG1_HTMCS10FBK
 
- HT_FBK_CFG1_HTMCS11FBK
 
- HT_FBK_CFG1_HTMCS12FBK
 
- HT_FBK_CFG1_HTMCS13FBK
 
- HT_FBK_CFG1_HTMCS14FBK
 
- HT_FBK_CFG1_HTMCS15FBK
 
- HT_FBK_CFG1_HTMCS8FBK
 
- HT_FBK_CFG1_HTMCS9FBK
 
- HT_INFINITY
 
- HT_INFORMATION_ELE
 
- HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY
 
- HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH
 
- HT_INFO_HT_PARAM_RIFS_MODE
 
- HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE
 
- HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW
 
- HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK
 
- HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY
 
- HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT
 
- HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT
 
- HT_INFO_OPERATION_MODE_OP_MODE_MASK
 
- HT_INFO_OPERATION_MODE_OP_MODE_OFFSET
 
- HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT
 
- HT_INFO_STBC_PARAM_DUAL_BEACON
 
- HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT
 
- HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED
 
- HT_INFO_STBC_PARAM_PCO_ACTIVE
 
- HT_INFO_STBC_PARAM_PCO_PHASE
 
- HT_INFO_STBC_PARAM_SECONDARY_BC
 
- HT_INFO_STBC_PARAM_SECONDARY_BCN
 
- HT_IOT_ACTION_E
 
- HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT
 
- HT_IOT_ACT_AMSDU_ENABLE
 
- HT_IOT_ACT_CDD_FSYNC
 
- HT_IOT_ACT_DISABLE_ALL_2SS
 
- HT_IOT_ACT_DISABLE_CCK_RATE
 
- HT_IOT_ACT_DISABLE_EDCA_TURBO
 
- HT_IOT_ACT_DISABLE_HIGH_POWER
 
- HT_IOT_ACT_DISABLE_MCS14
 
- HT_IOT_ACT_DISABLE_MCS15
 
- HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI
 
- HT_IOT_ACT_DISABLE_SHORT_GI
 
- HT_IOT_ACT_DISABLE_TX_2SS
 
- HT_IOT_ACT_DISABLE_TX_40_MHZ
 
- HT_IOT_ACT_EDCA_BIAS_ON_RX
 
- HT_IOT_ACT_FORCED_CTS2SELF
 
- HT_IOT_ACT_FORCED_ENABLE_BE_TXOP
 
- HT_IOT_ACT_FORCED_RTS
 
- HT_IOT_ACT_HYBRID_AGGREGATION
 
- HT_IOT_ACT_MGNT_USE_CCK_6M
 
- HT_IOT_ACT_MID_HIGHPOWER
 
- HT_IOT_ACT_NULL_DATA_POWER_SAVING
 
- HT_IOT_ACT_PURE_N_MODE
 
- HT_IOT_ACT_REJECT_ADDBA_REQ
 
- HT_IOT_ACT_TX_NO_AGGREGATION
 
- HT_IOT_ACT_TX_USE_AMSDU_4K
 
- HT_IOT_ACT_TX_USE_AMSDU_8K
 
- HT_IOT_ACT_WA_IOT_Broadcom
 
- HT_IOT_PEER
 
- HT_IOT_PEER_92U_SOFTAP
 
- HT_IOT_PEER_AIRGO
 
- HT_IOT_PEER_ATHEROS
 
- HT_IOT_PEER_BROADCOM
 
- HT_IOT_PEER_CISCO
 
- HT_IOT_PEER_E
 
- HT_IOT_PEER_INTEL
 
- HT_IOT_PEER_MARVELL
 
- HT_IOT_PEER_MAX
 
- HT_IOT_PEER_MERU
 
- HT_IOT_PEER_RALINK
 
- HT_IOT_PEER_REALTEK
 
- HT_IOT_PEER_REALTEK_81XX
 
- HT_IOT_PEER_REALTEK_92SE
 
- HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP
 
- HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP
 
- HT_IOT_PEER_REALTEK_SOFTAP
 
- HT_IOT_PEER_REALTEK_WOW
 
- HT_IOT_PEER_RTK_APCLIENT
 
- HT_IOT_PEER_SELF_SOFTAP
 
- HT_IOT_PEER_TENDA
 
- HT_IOT_PEER_UNKNOWN
 
- HT_IOT_RAFUNC_DISABLE_ALL
 
- HT_IOT_RAFUNC_PEER_1R
 
- HT_IOT_RAFUNC_TX_AMSDU
 
- HT_IO_SPACE
 
- HT_LDPC_EN
 
- HT_LINKCTRL_DETECTED
 
- HT_LINKERR_DETECTED
 
- HT_LINK_CLEAR_MASK
 
- HT_LINK_CRCFEN
 
- HT_LINK_LKFAIL
 
- HT_LTF
 
- HT_MASK
 
- HT_MCS0_MCS7
 
- HT_MCS16_MCS23
 
- HT_MCS24_MCS31
 
- HT_MCS8_MCS15
 
- HT_MEMORY_SPACE
 
- HT_MODE_DEFAULT
 
- HT_MODE_SISO20
 
- HT_MODE_WIDE
 
- HT_MPDU_BIT
 
- HT_MPDU_FAIL_BIT
 
- HT_MPDU_OK_BIT
 
- HT_MSI_ADDR_HI
 
- HT_MSI_ADDR_LO
 
- HT_MSI_ADDR_LO_MASK
 
- HT_MSI_FIXED_ADDR
 
- HT_MSI_FLAGS
 
- HT_MSI_FLAGS_ENABLE
 
- HT_MSI_FLAGS_FIXED
 
- HT_MULTI_EN
 
- HT_PPDU_BIT
 
- HT_PREFETCH_MODE
 
- HT_PickMCSRate
 
- HT_RANGE_END
 
- HT_RANGE_START
 
- HT_RATE_INIT
 
- HT_RC_2_STREAMS
 
- HT_RSSI_IQ
 
- HT_RSSI_NB
 
- HT_RSSI_TBD
 
- HT_RSSI_TSSI_2G
 
- HT_RSSI_TSSI_5G
 
- HT_RSSI_W1
 
- HT_RSSI_W2
 
- HT_RX_REORDER_BUF_TIMEOUT
 
- HT_SECONDARY_IF
 
- HT_SHIFT
 
- HT_SIG
 
- HT_SPEC_VER
 
- HT_SPEC_VER_EWC
 
- HT_SPEC_VER_IEEE
 
- HT_STBC_EN
 
- HT_STF
 
- HT_STREAM_1X1
 
- HT_STREAM_2X2
 
- HT_TARGET_RATE_0_8_16
 
- HT_TARGET_RATE_12
 
- HT_TARGET_RATE_13
 
- HT_TARGET_RATE_14
 
- HT_TARGET_RATE_15
 
- HT_TARGET_RATE_1_3_9_11_17_19
 
- HT_TARGET_RATE_20
 
- HT_TARGET_RATE_21
 
- HT_TARGET_RATE_22
 
- HT_TARGET_RATE_23
 
- HT_TARGET_RATE_4
 
- HT_TARGET_RATE_5
 
- HT_TARGET_RATE_6
 
- HT_TARGET_RATE_7
 
- HT_TIMING
 
- HT_TIMING_DEFAULT
 
- HT_caps_element
 
- HT_caps_handler
 
- HT_info_element
 
- HT_info_handler
 
- HT_update_self_and_peer_setting
 
- HUAWEI_PRODUCT_E173
 
- HUAWEI_PRODUCT_E173S6
 
- HUAWEI_PRODUCT_E1750
 
- HUAWEI_PRODUCT_K3765
 
- HUAWEI_PRODUCT_K4505
 
- HUAWEI_PRODUCT_K4605
 
- HUAWEI_VENDOR_ID
 
- HUB6
 
- HUBBUB_HVM_REG_FIELD_LIST
 
- HUBBUB_HVM_REG_LIST
 
- HUBBUB_MASK_SH_LIST_DCN10
 
- HUBBUB_MASK_SH_LIST_DCN20
 
- HUBBUB_MASK_SH_LIST_DCN21
 
- HUBBUB_MASK_SH_LIST_DCN_COMMON
 
- HUBBUB_MASK_SH_LIST_HVM
 
- HUBBUB_MASK_SH_LIST_STUTTER
 
- HUBBUB_REG_LIST_DCN10
 
- HUBBUB_REG_LIST_DCN20
 
- HUBBUB_REG_LIST_DCN20_COMMON
 
- HUBBUB_REG_LIST_DCN21
 
- HUBBUB_REG_LIST_DCN_COMMON
 
- HUBBUB_RET_ROB__MEM_PG
 
- HUBBUB_RET_ROB__MEM_PG__0
 
- HUBBUB_RET_ZERO__MEM_PG
 
- HUBBUB_RET_ZERO__MEM_PG__0
 
- HUBBUB_SDP_TAG_EXT__MEM_PG
 
- HUBBUB_SDP_TAG_EXT__MEM_PG__0
 
- HUBBUB_SDP_TAG_INT__MEM_PG
 
- HUBBUB_SDP_TAG_INT__MEM_PG__0
 
- HUBBUB_SF
 
- HUBBUB_SR_WATERMARK_REG_LIST
 
- HUBBUB_STUTTER_REG_FIELD_LIST
 
- HUBBUB_VM_REG_LIST
 
- HUBII_XBOW_CREDIT
 
- HUBII_XBOW_REV2_CREDIT
 
- HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK
 
- HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT
 
- HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK
 
- HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT
 
- HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK
 
- HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT
 
- HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK
 
- HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT
 
- HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP4_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP4_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP4_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP4_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP4_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP4_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP4_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP4_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP4_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP4_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP4_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP4_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP4_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP4_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP4_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP4_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP4_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP4_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP4_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP4_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP4_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP4_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP4_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP4_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP4_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP4_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP4_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP4_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP4_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_BLANK_EN_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_DISABLE_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_DISABLE__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_IN_BLANK_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_TTU_MODE_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_VTG_SEL_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT
 
- HUBP5_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK
 
- HUBP5_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__MPTE_GROUP_SIZE_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__MPTE_GROUP_SIZE__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK
 
- HUBP5_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT
 
- HUBP5_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK
 
- HUBP5_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_SE_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT
 
- HUBP5_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK
 
- HUBP5_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT
 
- HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK
 
- HUBP5_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT
 
- HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK
 
- HUBP5_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT
 
- HUBP5_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK
 
- HUBP5_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT
 
- HUBP5_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK
 
- HUBP5_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT
 
- HUBP5_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK
 
- HUBP5_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT
 
- HUBP5_DCSURF_TILING_CONFIG__DIM_TYPE_MASK
 
- HUBP5_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT
 
- HUBP5_DCSURF_TILING_CONFIG__META_LINEAR_MASK
 
- HUBP5_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT
 
- HUBP5_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK
 
- HUBP5_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT
 
- HUBP5_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK
 
- HUBP5_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT
 
- HUBP5_DCSURF_TILING_CONFIG__SW_MODE_MASK
 
- HUBP5_DCSURF_TILING_CONFIG__SW_MODE__SHIFT
 
- HUBP5_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK
 
- HUBP5_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT
 
- HUBP5_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK
 
- HUBP5_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK
 
- HUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT
 
- HUBPORT
 
- HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ0_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ0_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK
 
- HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK
 
- HUBPREQ0_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ0_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT
 
- HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK
 
- HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ0_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK
 
- HUBPREQ0_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK
 
- HUBPREQ0_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ0_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ0_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT
 
- HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK
 
- HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT
 
- HUBPREQ0_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ1_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ1_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK
 
- HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK
 
- HUBPREQ1_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ1_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT
 
- HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK
 
- HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ1_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK
 
- HUBPREQ1_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK
 
- HUBPREQ1_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ1_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ1_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT
 
- HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK
 
- HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT
 
- HUBPREQ1_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ2_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ2_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK
 
- HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK
 
- HUBPREQ2_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ2_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT
 
- HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK
 
- HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ2_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK
 
- HUBPREQ2_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK
 
- HUBPREQ2_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ2_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ2_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT
 
- HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK
 
- HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT
 
- HUBPREQ2_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ3_CURSOR_SETTINS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ3_CURSOR_SETTINS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_CLEAR__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS_MODE__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_ERROR_STATUS__SHIFT
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_CONTEXT0_STATUS__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB__SHIFT
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_UPDATE_PENDING_HIGH_EXTEND_ENABLE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING_MASK
 
- HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_PENDING__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_ENABLE__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_MODE__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_FREE_ENTRY__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_CONTROL__SURFACE_FRAME_PACING_QUEUE_RESET__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME_MASK
 
- HUBPREQ3_DCSURF_FRAME_PACING_TIME__SURFACE_FRAME_PACING_TIME__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ3_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT
 
- HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK
 
- HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_C__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_FINE_GRAIN_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ3_PREFETCH_SETTINS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH_MASK
 
- HUBPREQ3_PREFETCH_SETTINS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH_MASK
 
- HUBPREQ3_PREFETCH_SETTINS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ3_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ3_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT
 
- HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK
 
- HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT
 
- HUBPREQ3_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ4_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ4_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ4_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ4_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ4_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ4_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ4_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ4_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ4_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ4_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ4_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ4_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ4_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ4_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ4_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ4_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ4_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ4_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ4_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ4_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ4_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ4_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ4_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ4_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ4_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ4_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ4_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ4_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ4_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ4_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ4_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ4_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ4_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ4_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ4_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ4_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ4_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ4_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ4_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ4_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ4_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ4_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ4_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ4_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ4_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ4_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ4_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ4_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ4_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ4_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ4_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ4_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ4_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ4_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ4_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ4_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ4_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ4_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ4_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ4_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ4_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ4_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ4_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ4_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ4_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ4_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ4_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ4_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ4_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ4_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ4_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ4_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ4_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ4_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ4_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ5_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK
 
- HUBPREQ5_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT
 
- HUBPREQ5_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK
 
- HUBPREQ5_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT
 
- HUBPREQ5_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK
 
- HUBPREQ5_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK
 
- HUBPREQ5_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ5_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ5_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ5_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK
 
- HUBPREQ5_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ5_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK
 
- HUBPREQ5_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ5_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK
 
- HUBPREQ5_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ5_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK
 
- HUBPREQ5_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT
 
- HUBPREQ5_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK
 
- HUBPREQ5_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT
 
- HUBPREQ5_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK
 
- HUBPREQ5_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ5_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK
 
- HUBPREQ5_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT
 
- HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK
 
- HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT
 
- HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK
 
- HUBPREQ5_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- HUBPREQ5_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- HUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK
 
- HUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT
 
- HUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK
 
- HUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK
 
- HUBPREQ5_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT
 
- HUBPREQ5_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME_MASK
 
- HUBPREQ5_DCSURF_FRAME_PACING_TIME__FRAME_PACING_TIME__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__EARLIEST_GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_INUSE_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__GPUID__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__MY_GPUID_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__MY_GPUID__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__PACING_COUNTER_RESET__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_EN_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_EN__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_LEVEL__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_DONE_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE_MASK
 
- HUBPREQ5_DCSURF_QUEUE_CONTROL__QUEUE_PURGE__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK
 
- HUBPREQ5_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK
 
- HUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK
 
- HUBPREQ5_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK
 
- HUBPREQ5_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK
 
- HUBPREQ5_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_PITCH__META_PITCH_MASK
 
- HUBPREQ5_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT
 
- HUBPREQ5_DCSURF_SURFACE_PITCH__PITCH_MASK
 
- HUBPREQ5_DCSURF_SURFACE_PITCH__PITCH__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_TMZ__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ_MASK
 
- HUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB__VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_TMZ__SHIFT
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_MASK
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__SHIFT
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_MASK
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__SHIFT
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP_MASK
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SNOOP__SHIFT
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM_MASK
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM__SHIFT
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ_MASK
 
- HUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__MC_VM_SYSTEM_APERTURE_DEFAULT_TMZ__SHIFT
 
- HUBPREQ5_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK
 
- HUBPREQ5_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT
 
- HUBPREQ5_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK
 
- HUBPREQ5_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT
 
- HUBPREQ5_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK
 
- HUBPREQ5_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT
 
- HUBPREQ5_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK
 
- HUBPREQ5_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT
 
- HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK
 
- HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT
 
- HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK
 
- HUBPREQ5_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT
 
- HUBPREQ5_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK
 
- HUBPREQ5_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT
 
- HUBPREQ5_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK
 
- HUBPREQ5_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK
 
- HUBPREQ5_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK
 
- HUBPREQ5_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK
 
- HUBPREQ5_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK
 
- HUBPREQ5_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK
 
- HUBPREQ5_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK
 
- HUBPREQ5_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK
 
- HUBPREQ5_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK
 
- HUBPREQ5_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT
 
- HUBPREQ5_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK
 
- HUBPREQ5_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT
 
- HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK
 
- HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT
 
- HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK
 
- HUBPREQ5_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT
 
- HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK
 
- HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT
 
- HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK
 
- HUBPREQ5_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT
 
- HUBPREQ5_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK
 
- HUBPREQ5_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT
 
- HUBPREQ5_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK
 
- HUBPREQ5_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT
 
- HUBPREQ5_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK
 
- HUBPREQ5_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT
 
- HUBPREQ5_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK
 
- HUBPREQ5_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT
 
- HUBPREQ5_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER_MASK
 
- HUBPREQ5_SURFACE_CURRENT_PACING_COUNTER__CURRENT_PACING_COUNTER__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT
 
- HUBPREQ5_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK
 
- HUBPREQ5_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT
 
- HUBPREQ5_VMID_SETTINGS_0__VMID_MASK
 
- HUBPREQ5_VMID_SETTINGS_0__VMID__SHIFT
 
- HUBPREQ_DPTE__MEM_PG
 
- HUBPREQ_DPTE__MEM_PG__0
 
- HUBPREQ_META__MEM_PG
 
- HUBPREQ_META__MEM_PG__0
 
- HUBPREQ_MPTE__MEM_PG
 
- HUBPREQ_MPTE__MEM_PG__0
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__HUBPRET_MEM_PWR_CTRL_SPARE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET4_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET4_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET4_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET4_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET4_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET4_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET4_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET4_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET4_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET4_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK
 
- HUBPRET5_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK
 
- HUBPRET5_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK
 
- HUBPRET5_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT
 
- HUBPRET5_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK
 
- HUBPRET5_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK
 
- HUBPRET5_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK
 
- HUBPRET5_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK
 
- HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK
 
- HUBPRET5_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK
 
- HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK
 
- HUBPRET5_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK
 
- HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT
 
- HUBPRET5_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT
 
- HUBPRET_CUR_CDC__MEM_PG
 
- HUBPRET_CUR_CDC__MEM_PG__0
 
- HUBPRET_CUR_ROB__MEM_PG
 
- HUBPRET_CUR_ROB__MEM_PG__0
 
- HUBPRET_DET__MEM_PG
 
- HUBPRET_DET__MEM_PG__0
 
- HUBPRET_PIX_CDC__MEM_PG
 
- HUBPRET_PIX_CDC__MEM_PG__0
 
- HUBPXFC0_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC0_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC0_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC0_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC0_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC0_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC1_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC1_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC1_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC1_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC1_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC2_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC2_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC2_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC2_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC2_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC3_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC3_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC3_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC3_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC3_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC4_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC4_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC4_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC4_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC4_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__ALPHA_POSITION_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__ALPHA_POSITION__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__BW_REDUCTION_MODE_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__BW_REDUCTION_MODE__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__CHUNK_SIZE_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__CHUNK_SIZE__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__MXFC_ENABLE_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__MXFC_ENABLE__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__PIXEL_64BPP_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__PIXEL_64BPP__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__RD_VMID_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__RD_VMID__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__SXFCDPE_OPPORTUNISTIC_PACKING__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__SXFC_ENABLE_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__SXFC_ENABLE__SHIFT
 
- HUBPXFC5_HUBP_XFC_CNTL__XBUF_FULL_ENABLE_MASK
 
- HUBPXFC5_HUBP_XFC_CNTL__XBUF_FULL_ENABLE__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__PRECHARGE_DELAY__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__REMOTE_SURFACE_FLIP_LATENCY__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG0__TRANSFER_DELAY__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG1__XFC_PREFETCH_MARGIN__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WATERMARK__SHIFT
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE_MASK
 
- HUBPXFC5_HUBP_XFC_DELAY_CONFIG2__XFC_UNDERFLOW_WM_DISABLE__SHIFT
 
- HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START_MASK
 
- HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_X_START__SHIFT
 
- HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START_MASK
 
- HUBPXFC5_HUBP_XFC_MPC_CONFIG__SLV_MPC_DST_Y_START__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0__SLV_VINIT__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1__SLV_VRATIO__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VREADY_OFFSET__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0__SLV_VSTARTUP_OFFSET__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_OFFSET__SHIFT
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH_MASK
 
- HUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1__SLV_VUPDATE_WIDTH__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_IGNORED_REQINI_UNDERFLOW__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_CLR__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_SXFCCTL_LOST_CMD__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CLR__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_CNT__SHIFT
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS_MASK
 
- HUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS__XFC_UNDERFLOW_STATUS__SHIFT
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB_MASK
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB__XBUF_RD_BASE0_ADDR_LSB__SHIFT
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB_MASK
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB__XBUF_RD_BASE0_ADDR_MSB__SHIFT
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB_MASK
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB__XBUF_RD_BASE1_ADDR_LSB__SHIFT
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB_MASK
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB__XBUF_RD_BASE1_ADDR_MSB__SHIFT
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH_MASK
 
- HUBPXFC5_HUBP_XFC_XBUF_RD_PITCH__XBUF_RD_PITCH__SHIFT
 
- HUBP_BLANK_EN
 
- HUBP_BLANK_SW_ASSERT
 
- HUBP_BLANK_SW_DEASSERT
 
- HUBP_COMMON_REG_VARIABLE_LIST
 
- HUBP_DISABLE
 
- HUBP_DISABLED
 
- HUBP_ENABLED
 
- HUBP_IN_ACTIVE
 
- HUBP_IN_BLANK
 
- HUBP_IN_VBLANK
 
- HUBP_MASK_SH_LIST_DCN
 
- HUBP_MASK_SH_LIST_DCN10
 
- HUBP_MASK_SH_LIST_DCN20
 
- HUBP_MASK_SH_LIST_DCN21
 
- HUBP_MASK_SH_LIST_DCN21_COMMON
 
- HUBP_MASK_SH_LIST_DCN2_COMMON
 
- HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON
 
- HUBP_MASK_SH_LIST_DCN_COMMON
 
- HUBP_MASK_SH_LIST_DCN_SHARE_COMMON
 
- HUBP_MASK_SH_LIST_DCN_VM
 
- HUBP_MEASURE_WIN_MODE_DCFCLK
 
- HUBP_MEASURE_WIN_MODE_DCFCLK_0
 
- HUBP_MEASURE_WIN_MODE_DCFCLK_1
 
- HUBP_MEASURE_WIN_MODE_DCFCLK_2
 
- HUBP_MEASURE_WIN_MODE_DCFCLK_3
 
- HUBP_NO_OUTSTANDING_REQ
 
- HUBP_REG_LIST_DCN
 
- HUBP_REG_LIST_DCN10
 
- HUBP_REG_LIST_DCN20
 
- HUBP_REG_LIST_DCN21
 
- HUBP_REG_LIST_DCN2_COMMON
 
- HUBP_REG_LIST_DCN_VM
 
- HUBP_SF
 
- HUBP_TTU_DISABLE
 
- HUBP_TTU_DISABLED
 
- HUBP_TTU_ENABLED
 
- HUBP_VREADY_AT_OR_AFTER_VSYNC
 
- HUBP_VTG_SEL
 
- HUBP_XFC_CHUNK_SIZE_16KB
 
- HUBP_XFC_CHUNK_SIZE_1KB
 
- HUBP_XFC_CHUNK_SIZE_256B
 
- HUBP_XFC_CHUNK_SIZE_2KB
 
- HUBP_XFC_CHUNK_SIZE_32KB
 
- HUBP_XFC_CHUNK_SIZE_4KB
 
- HUBP_XFC_CHUNK_SIZE_512B
 
- HUBP_XFC_CHUNK_SIZE_8KB
 
- HUBP_XFC_CHUNK_SIZE_ENUM
 
- HUBP_XFC_FRAME_MODE_ENUM
 
- HUBP_XFC_FULL_FRAME_MODE
 
- HUBP_XFC_PARTIAL_FRAME_MODE
 
- HUBP_XFC_PIXEL_FORMAT_ENUM
 
- HUBP_XFC_PIXEL_IS_32BPP
 
- HUBP_XFC_PIXEL_IS_64BPP
 
- HUB_BH_RESET_TIME
 
- HUB_CHANGE_LOCAL_POWER
 
- HUB_CHANGE_OVERCURRENT
 
- HUB_CHAR_COMMON_LPSM
 
- HUB_CHAR_COMMON_OCPM
 
- HUB_CHAR_COMPOUND
 
- HUB_CHAR_INDV_PORT_LPSM
 
- HUB_CHAR_INDV_PORT_OCPM
 
- HUB_CHAR_LPSM
 
- HUB_CHAR_NO_LPSM
 
- HUB_CHAR_NO_OCPM
 
- HUB_CHAR_OCPM
 
- HUB_CHAR_PORTIND
 
- HUB_CHAR_TTTT
 
- HUB_CLASS_REQ
 
- HUB_CLEAR_TT_BUFFER
 
- HUB_DEBOUNCE_STABLE
 
- HUB_DEBOUNCE_STEP
 
- HUB_DEBOUNCE_TIMEOUT
 
- HUB_DISCONNECT
 
- HUB_EXT_PORT_STATUS
 
- HUB_GET_PORT_ERR_COUNT
 
- HUB_GET_TT_STATE
 
- HUB_INIT
 
- HUB_INIT2
 
- HUB_INIT3
 
- HUB_IP_ERROR
 
- HUB_IP_MASK
 
- HUB_IP_PEND0
 
- HUB_IP_PEND1_CC
 
- HUB_IP_PROF
 
- HUB_IP_RT
 
- HUB_LED_AMBER
 
- HUB_LED_AUTO
 
- HUB_LED_GREEN
 
- HUB_LED_OFF
 
- HUB_LONG_RESET_TIME
 
- HUB_NIC_ADDR
 
- HUB_NUM_BIG_WINDOW
 
- HUB_NUM_WIDGET
 
- HUB_PASSWORD
 
- HUB_PIO_MAP_TO_IO
 
- HUB_PIO_MAP_TO_MEM
 
- HUB_PORT_PD_STATUS
 
- HUB_PORT_STATUS
 
- HUB_POST_RESET
 
- HUB_PRE_RESET
 
- HUB_QUIRK_CHECK_PORT_AUTOSUSPEND
 
- HUB_QUIRK_DISABLE_AUTOSUSPEND
 
- HUB_REGISTER_WIDGET
 
- HUB_RESET_RESUME
 
- HUB_RESET_TIMEOUT
 
- HUB_RESET_TT
 
- HUB_RESUME
 
- HUB_REV_1_0
 
- HUB_REV_2_0
 
- HUB_REV_2_1
 
- HUB_REV_2_2
 
- HUB_REV_2_3
 
- HUB_REV_2_4
 
- HUB_ROOT_RESET_TIME
 
- HUB_SET_DEPTH
 
- HUB_SHORT_RESET_TIME
 
- HUB_SPEED_HIGH
 
- HUB_SPEED_SUPER
 
- HUB_STATUS_LOCAL_POWER
 
- HUB_STATUS_OVERCURRENT
 
- HUB_STOP_TT
 
- HUB_SUSPEND
 
- HUB_TTTT_16_BITS
 
- HUB_TTTT_24_BITS
 
- HUB_TTTT_32_BITS
 
- HUB_TTTT_8_BITS
 
- HUB_WIDGET_ID_MAX
 
- HUB_WIDGET_ID_MIN
 
- HUB_WIDGET_PART_NUM
 
- HUC_FW_BLOB
 
- HUC_FW_VERIFIED
 
- HUC_LOADING_AGENT_GUC
 
- HUC_LOADING_AGENT_VCR
 
- HUC_LOAD_SUCCESSFUL
 
- HUC_STATUS2
 
- HUC_UKERNEL
 
- HUDI
 
- HUDI0
 
- HUDI1
 
- HUDII
 
- HUDSON2_MAIN_PORTS
 
- HUE
 
- HUE0
 
- HUE1
 
- HUECOS
 
- HUESIN
 
- HUE_CTRL_BYTE
 
- HUE_DEFAULT
 
- HUE_EN
 
- HUE_MASK
 
- HUE_REG
 
- HUFF_CHROMA_AC_OFF
 
- HUFF_CHROMA_DC_OFF
 
- HUFF_LUMA_AC_OFF
 
- HUFF_LUMA_DC_OFF
 
- HUF_BLOCKBOUND
 
- HUF_BLOCKSIZE_MAX
 
- HUF_CElt
 
- HUF_CElt_s
 
- HUF_COMPRESSBOUND
 
- HUF_COMPRESS_WORKSPACE_SIZE
 
- HUF_COMPRESS_WORKSPACE_SIZE_U32
 
- HUF_CREATE_STATIC_CTABLE
 
- HUF_CREATE_STATIC_DTABLEX2
 
- HUF_CREATE_STATIC_DTABLEX4
 
- HUF_CTABLEBOUND
 
- HUF_DECODE_SYMBOLX2_0
 
- HUF_DECODE_SYMBOLX2_1
 
- HUF_DECODE_SYMBOLX2_2
 
- HUF_DECODE_SYMBOLX4_0
 
- HUF_DECODE_SYMBOLX4_1
 
- HUF_DECODE_SYMBOLX4_2
 
- HUF_DECOMPRESS_WORKSPACE_SIZE
 
- HUF_DECOMPRESS_WORKSPACE_SIZE_U32
 
- HUF_DEltX2
 
- HUF_DEltX4
 
- HUF_DTABLE_SIZE
 
- HUF_DTable
 
- HUF_FLUSHBITS
 
- HUF_FLUSHBITS_1
 
- HUF_FLUSHBITS_2
 
- HUF_H_298734234
 
- HUF_STATIC_ASSERT
 
- HUF_SYMBOLVALUE_MAX
 
- HUF_TABLELOG_ABSOLUTEMAX
 
- HUF_TABLELOG_DEFAULT
 
- HUF_TABLELOG_MAX
 
- HUF_buildCTable_wksp
 
- HUF_compress1X_repeat
 
- HUF_compress1X_usingCTable
 
- HUF_compress1X_wksp
 
- HUF_compress4X_repeat
 
- HUF_compress4X_usingCTable
 
- HUF_compress4X_wksp
 
- HUF_compressBound
 
- HUF_compressCTable_internal
 
- HUF_compressWeights_wksp
 
- HUF_compress_internal
 
- HUF_decodeLastSymbolX4
 
- HUF_decodeStreamX2
 
- HUF_decodeStreamX4
 
- HUF_decodeSymbolX2
 
- HUF_decodeSymbolX4
 
- HUF_decompress1X2_DCtx_wksp
 
- HUF_decompress1X2_usingDTable
 
- HUF_decompress1X2_usingDTable_internal
 
- HUF_decompress1X4_DCtx_wksp
 
- HUF_decompress1X4_usingDTable
 
- HUF_decompress1X4_usingDTable_internal
 
- HUF_decompress1X_DCtx_wksp
 
- HUF_decompress1X_usingDTable
 
- HUF_decompress4X2_DCtx_wksp
 
- HUF_decompress4X2_usingDTable
 
- HUF_decompress4X2_usingDTable_internal
 
- HUF_decompress4X4_DCtx_wksp
 
- HUF_decompress4X4_usingDTable
 
- HUF_decompress4X4_usingDTable_internal
 
- HUF_decompress4X_DCtx_wksp
 
- HUF_decompress4X_hufOnly_wksp
 
- HUF_decompress4X_usingDTable
 
- HUF_encodeSymbol
 
- HUF_estimateCompressedSize
 
- HUF_fillDTableX4
 
- HUF_fillDTableX4Level2
 
- HUF_getDTableDesc
 
- HUF_isError
 
- HUF_optimalTableLog
 
- HUF_readCTable_wksp
 
- HUF_readDTableX2_wksp
 
- HUF_readDTableX4_wksp
 
- HUF_readStats_wksp
 
- HUF_repeat
 
- HUF_repeat_check
 
- HUF_repeat_none
 
- HUF_repeat_valid
 
- HUF_selectDecoder
 
- HUF_setMaxHeight
 
- HUF_sort
 
- HUF_static_assert
 
- HUF_validateCTable
 
- HUF_writeCTable_wksp
 
- HUGE
 
- HUGEN
 
- HUGEPD_ADDR_MASK
 
- HUGEPD_FREELIST_SIZE
 
- HUGEPD_SHIFT_MASK
 
- HUGEPD_VAL_BITS
 
- HUGETLBFS_I
 
- HUGETLBFS_MAGIC
 
- HUGETLBFS_SB
 
- HUGETLB_ANONHUGE_INODE
 
- HUGETLB_ANON_FILE
 
- HUGETLB_CGROUP_MIN_ORDER
 
- HUGETLB_FLAG_ENCODE_16GB
 
- HUGETLB_FLAG_ENCODE_16MB
 
- HUGETLB_FLAG_ENCODE_1GB
 
- HUGETLB_FLAG_ENCODE_1MB
 
- HUGETLB_FLAG_ENCODE_256MB
 
- HUGETLB_FLAG_ENCODE_2GB
 
- HUGETLB_FLAG_ENCODE_2MB
 
- HUGETLB_FLAG_ENCODE_32MB
 
- HUGETLB_FLAG_ENCODE_512KB
 
- HUGETLB_FLAG_ENCODE_512MB
 
- HUGETLB_FLAG_ENCODE_64KB
 
- HUGETLB_FLAG_ENCODE_8MB
 
- HUGETLB_FLAG_ENCODE_MASK
 
- HUGETLB_FLAG_ENCODE_SHIFT
 
- HUGETLB_NEED_PRELOAD
 
- HUGETLB_PAGE_DTOR
 
- HUGETLB_PAGE_ORDER
 
- HUGETLB_PGDIR_MASK
 
- HUGETLB_PGDIR_SHIFT
 
- HUGETLB_PGDIR_SIZE
 
- HUGETLB_SHMFS_INODE
 
- HUGETLB_SIZE
 
- HUGE_MAX_HSTATE
 
- HUGE_WRITEBACK
 
- HUM
 
- HUME
 
- HUME_MASK
 
- HUME_SHIFT
 
- HUM_MASK
 
- HUM_SHIFT
 
- HUNG_TASK_LOCK_BREAK
 
- HUNT
 
- HUNT_10G_ONLY_STAT_MASK
 
- HUNT_40G_EXTRA_STAT_MASK
 
- HUNT_COMMON_STAT_MASK
 
- HUNT_FILTER_TBL_ROWS
 
- HUNT_MC_BOOTROM_COPYCODE_VEC
 
- HUNT_MC_BOOTROM_NOFLASH_VEC
 
- HUNT_MC_BOOTROM_RECOVERY_VEC
 
- HUNT_PM_AND_RXDP_STAT_MASK
 
- HUPCL
 
- HURR_RIOIB
 
- HURR_SCALABILTY
 
- HUSB_RESET_INT
 
- HUSB_SIE_INIT_INT
 
- HUSB_SIE_pCurrentTDPtr
 
- HUSB_SIE_pTDListDone_Sem
 
- HUSB_TDListDone
 
- HUSB_pEOT
 
- HV7131_REG_ABCG
 
- HV7131_REG_AGCG
 
- HV7131_REG_APBV
 
- HV7131_REG_ARCG
 
- HV7131_REG_ARLV
 
- HV7131_REG_ASLP
 
- HV7131_REG_FCSL
 
- HV7131_REG_FCSU
 
- HV7131_REG_FRSL
 
- HV7131_REG_FRSU
 
- HV7131_REG_FWHL
 
- HV7131_REG_FWHU
 
- HV7131_REG_FWWL
 
- HV7131_REG_FWWU
 
- HV7131_REG_HIREFNOH
 
- HV7131_REG_HIREFNOL
 
- HV7131_REG_LOREFNOH
 
- HV7131_REG_LOREFNOL
 
- HV7131_REG_MODE_A
 
- HV7131_REG_MODE_B
 
- HV7131_REG_MODE_C
 
- HV7131_REG_OFSB
 
- HV7131_REG_OFSG
 
- HV7131_REG_OFSR
 
- HV7131_REG_THBL
 
- HV7131_REG_THBU
 
- HV7131_REG_TITL
 
- HV7131_REG_TITM
 
- HV7131_REG_TITU
 
- HV7131_REG_TMCD
 
- HV7131_REG_TVBL
 
- HV7131_REG_TVBU
 
- HVA_DEFAULT_FRAME_DEN
 
- HVA_DEFAULT_FRAME_NUM
 
- HVA_DEFAULT_HEIGHT
 
- HVA_DEFAULT_WIDTH
 
- HVA_FLAG_FRAMEINFO
 
- HVA_FLAG_STREAMINFO
 
- HVA_H
 
- HVA_HEIGHT_ALIGNMENT
 
- HVA_HIF_FIFO_CMD
 
- HVA_HIF_FIFO_STS
 
- HVA_HIF_REG_BSM
 
- HVA_HIF_REG_CFL
 
- HVA_HIF_REG_CLK_GATING
 
- HVA_HIF_REG_CNT
 
- HVA_HIF_REG_EMI_ERR
 
- HVA_HIF_REG_ERR_IT_ACK
 
- HVA_HIF_REG_HEC_CHKSYN_DIS
 
- HVA_HIF_REG_HEC_MIF_CFG
 
- HVA_HIF_REG_HEC_MIF_ERR
 
- HVA_HIF_REG_HEC_STS
 
- HVA_HIF_REG_HJE_STS
 
- HVA_HIF_REG_HVC_STS
 
- HVA_HIF_REG_IT_ACK
 
- HVA_HIF_REG_LMI_ERR
 
- HVA_HIF_REG_MIF_CFG
 
- HVA_HIF_REG_RST
 
- HVA_HIF_REG_RST_ACK
 
- HVA_HIF_REG_SFL
 
- HVA_HIF_REG_VERSION
 
- HVA_HW_H
 
- HVA_MAX_ENCODERS
 
- HVA_MAX_FORMATS
 
- HVA_MAX_HEIGHT
 
- HVA_MAX_INSTANCES
 
- HVA_MAX_WIDTH
 
- HVA_MEM_H
 
- HVA_MIN_HEIGHT
 
- HVA_MIN_WIDTH
 
- HVA_NAME
 
- HVA_PREFIX
 
- HVA_VERSION_UNKNOWN
 
- HVA_VERSION_V400
 
- HVA_WIDTH_ALIGNMENT
 
- HVCALL
 
- HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST
 
- HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE
 
- HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST
 
- HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX
 
- HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE
 
- HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX
 
- HVCALL_NOTIFY_LONG_SPIN_WAIT
 
- HVCALL_POST_MESSAGE
 
- HVCALL_RETARGET_INTERRUPT
 
- HVCALL_SEND_IPI
 
- HVCALL_SEND_IPI_EX
 
- HVCALL_SIGNAL_EVENT
 
- HVCS_ARCH_VERSION
 
- HVCS_BUFF_LEN
 
- HVCS_CLC_LENGTH
 
- HVCS_CLOSE_WAIT
 
- HVCS_DEFAULT_SERVER_ADAPTERS
 
- HVCS_DRIVER_VERSION
 
- HVCS_MAX_FROM_USER
 
- HVCS_MAX_SERVER_ADAPTERS
 
- HVCS_MINOR_START
 
- HVCS_QUICK_READ
 
- HVCS_READ_MASK
 
- HVCS_SCHED_READ
 
- HVCS_TRY_WRITE
 
- HVC_ALLOC_TTY_ADAPTERS
 
- HVC_ATOMIC_READ_MAX
 
- HVC_BOOT_ARRAY_SIZE
 
- HVC_CLOSE_WAIT
 
- HVC_CONSOLE_H
 
- HVC_COOKIE
 
- HVC_IUCV_MAGIC
 
- HVC_MAJOR
 
- HVC_MINOR
 
- HVC_POLL_READ
 
- HVC_POLL_WRITE
 
- HVC_RESET_VECTORS
 
- HVC_SET_VECTORS
 
- HVC_SOFT_RESTART
 
- HVC_STUB_ERR
 
- HVC_STUB_HCALL_NR
 
- HVD
 
- HVD_LVD_SE
 
- HVERSION_ANY_ID
 
- HVERSION_REV_ANY_ID
 
- HVFB_HEIGHT
 
- HVFB_HEIGHT_MIN
 
- HVFB_UPDATE_DELAY
 
- HVFB_WIDTH
 
- HVFB_WIDTH_MIN
 
- HVF_CNTRL_0_INTPOL
 
- HVF_CNTRL_0_PREFIL
 
- HVF_CNTRL_0_RWB
 
- HVF_CNTRL_0_SM
 
- HVF_CNTRL_1_FOR
 
- HVF_CNTRL_1_PAD
 
- HVF_CNTRL_1_SEMI_PLANAR
 
- HVF_CNTRL_1_VQR
 
- HVF_CNTRL_1_YUVBLK
 
- HVMMEM_mmio_dm
 
- HVMMEM_ram_ro
 
- HVMMEM_ram_rw
 
- HVMOP_get_mem_type
 
- HVMOP_get_param
 
- HVMOP_pagetable_dying
 
- HVMOP_set_param
 
- HVMPTM_delay_for_missed_ticks
 
- HVMPTM_no_delay_for_missed_ticks
 
- HVMPTM_no_missed_ticks_pending
 
- HVMPTM_one_missed_tick_pending
 
- HVMSG_EVENTLOG_BUFFERCOMPLETE
 
- HVMSG_GPA_INTERCEPT
 
- HVMSG_INVALID_VP_REGISTER_VALUE
 
- HVMSG_NONE
 
- HVMSG_TIMER_EXPIRED
 
- HVMSG_UNMAPPED_GPA
 
- HVMSG_UNRECOVERABLE_EXCEPTION
 
- HVMSG_UNSUPPORTED_FEATURE
 
- HVMSG_X64_APIC_EOI
 
- HVMSG_X64_CPUID_INTERCEPT
 
- HVMSG_X64_EXCEPTION_INTERCEPT
 
- HVMSG_X64_IOPORT_INTERCEPT
 
- HVMSG_X64_LEGACY_FP_ERROR
 
- HVMSG_X64_MSR_INTERCEPT
 
- HVM_CALLBACK_VECTOR
 
- HVM_CALLBACK_VIA_TYPE_SHIFT
 
- HVM_CALLBACK_VIA_TYPE_VECTOR
 
- HVM_EV_GENEX
 
- HVM_EV_INTR
 
- HVM_EV_INTR_0
 
- HVM_EV_MACHCHECK
 
- HVM_EV_RESET
 
- HVM_EV_TRAP
 
- HVM_GE_C_BUS
 
- HVM_GE_C_CACHE
 
- HVM_GE_C_INVI
 
- HVM_GE_C_PCAL
 
- HVM_GE_C_PRIVI
 
- HVM_GE_C_RMAL
 
- HVM_GE_C_RPROT
 
- HVM_GE_C_RUSER
 
- HVM_GE_C_WMAL
 
- HVM_GE_C_WPROT
 
- HVM_GE_C_WREG
 
- HVM_GE_C_WUSER
 
- HVM_GE_C_XMAL
 
- HVM_GE_C_XPROT
 
- HVM_GE_C_XUSER
 
- HVM_HUGEPAGE_SIZE
 
- HVM_MAX_INTR
 
- HVM_MCHK_C_BADEX
 
- HVM_MCHK_C_BADPT
 
- HVM_MCHK_C_BADSP
 
- HVM_MCHK_C_DOWN
 
- HVM_MCHK_C_REGWR
 
- HVM_NR_PARAMS
 
- HVM_PARAM_ACPI_S_STATE
 
- HVM_PARAM_BUFIOREQ_PFN
 
- HVM_PARAM_CALLBACK_IRQ
 
- HVM_PARAM_CALLBACK_TYPE_GSI
 
- HVM_PARAM_CALLBACK_TYPE_PCI_INTX
 
- HVM_PARAM_CALLBACK_TYPE_PPI
 
- HVM_PARAM_CALLBACK_TYPE_VECTOR
 
- HVM_PARAM_CONSOLE_EVTCHN
 
- HVM_PARAM_CONSOLE_PFN
 
- HVM_PARAM_DM_DOMAIN
 
- HVM_PARAM_HPET_ENABLED
 
- HVM_PARAM_IDENT_PT
 
- HVM_PARAM_IOREQ_PFN
 
- HVM_PARAM_PAE_ENABLED
 
- HVM_PARAM_STORE_EVTCHN
 
- HVM_PARAM_STORE_PFN
 
- HVM_PARAM_TIMER_MODE
 
- HVM_PARAM_VM86_TSS
 
- HVM_PARAM_VPT_ALIGN
 
- HVM_TRAP1_FORMERLY_VMWIRE
 
- HVM_TRAP1_VMCACHE
 
- HVM_TRAP1_VMCLRMAP
 
- HVM_TRAP1_VMGETIE
 
- HVM_TRAP1_VMGETREGS
 
- HVM_TRAP1_VMGETTIME
 
- HVM_TRAP1_VMINTOP
 
- HVM_TRAP1_VMNEWMAP
 
- HVM_TRAP1_VMRTE
 
- HVM_TRAP1_VMSETIE
 
- HVM_TRAP1_VMSETREGS
 
- HVM_TRAP1_VMSETTIME
 
- HVM_TRAP1_VMSETVEC
 
- HVM_TRAP1_VMSTART
 
- HVM_TRAP1_VMSTOP
 
- HVM_TRAP1_VMTIMEROP
 
- HVM_TRAP1_VMVERSION
 
- HVM_TRAP1_VMVPID
 
- HVM_TRAP1_VMWAIT
 
- HVM_TRAP1_VMYIELD
 
- HVM_VMEST_CAUSE_MSK
 
- HVM_VMEST_CAUSE_SFT
 
- HVM_VMEST_EVENTNUM_MSK
 
- HVM_VMEST_EVENTNUM_SFT
 
- HVM_VMEST_IE_MSK
 
- HVM_VMEST_IE_SFT
 
- HVM_VMEST_SS_MSK
 
- HVM_VMEST_SS_SFT
 
- HVM_VMEST_UM_MSK
 
- HVM_VMEST_UM_SFT
 
- HVPCI_DOM_INVALID
 
- HVPCI_DOM_MAP_SIZE
 
- HVSC
 
- HVSI_CLOSED
 
- HVSI_CONSOLE
 
- HVSI_FSP_DIED
 
- HVSI_INBUF_SIZE
 
- HVSI_MAJOR
 
- HVSI_MAX_OUTGOING_DATA
 
- HVSI_MAX_PACKET
 
- HVSI_MAX_READ
 
- HVSI_MINOR
 
- HVSI_OPEN
 
- HVSI_PROTOCOL_STATE
 
- HVSI_TIMEOUT
 
- HVSI_TSCD
 
- HVSI_TSDTR
 
- HVSI_VERSION
 
- HVSI_WAIT_FOR_MCTRL_RESPONSE
 
- HVSI_WAIT_FOR_VER_QUERY
 
- HVSI_WAIT_FOR_VER_RESPONSE
 
- HVSRC_HORI
 
- HVSRC_PARAM_CTRL_DFLT
 
- HVSRC_VERT
 
- HVSYNC
 
- HVS_BOOTLOADER_DLIST_END
 
- HVS_CLOSE_TIMEOUT
 
- HVS_HEADER_LEN
 
- HVS_MTU_SIZE
 
- HVS_PIXEL_FORMAT_AYUV444_RGB
 
- HVS_PIXEL_FORMAT_H264
 
- HVS_PIXEL_FORMAT_PALETTE
 
- HVS_PIXEL_FORMAT_RGB332
 
- HVS_PIXEL_FORMAT_RGB555
 
- HVS_PIXEL_FORMAT_RGB565
 
- HVS_PIXEL_FORMAT_RGB888
 
- HVS_PIXEL_FORMAT_RGBA4444
 
- HVS_PIXEL_FORMAT_RGBA5551
 
- HVS_PIXEL_FORMAT_RGBA6666
 
- HVS_PIXEL_FORMAT_RGBA8888
 
- HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE
 
- HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE
 
- HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE
 
- HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE
 
- HVS_PIXEL_FORMAT_YUV444_RGB
 
- HVS_PIXEL_ORDER_ABGR
 
- HVS_PIXEL_ORDER_ARGB
 
- HVS_PIXEL_ORDER_BGRA
 
- HVS_PIXEL_ORDER_RGBA
 
- HVS_PIXEL_ORDER_XBGR
 
- HVS_PIXEL_ORDER_XBRG
 
- HVS_PIXEL_ORDER_XRBG
 
- HVS_PIXEL_ORDER_XRGB
 
- HVS_PIXEL_ORDER_XYCBCR
 
- HVS_PIXEL_ORDER_XYCRCB
 
- HVS_PIXEL_ORDER_YXCBCR
 
- HVS_PIXEL_ORDER_YXCRCB
 
- HVS_PKT_LEN
 
- HVS_READ
 
- HVS_SEND_BUF_SIZE
 
- HVS_WRITE
 
- HVTRAMP_DESCR_CPU
 
- HVTRAMP_DESCR_FAULT_INFO_PA
 
- HVTRAMP_DESCR_FAULT_INFO_VA
 
- HVTRAMP_DESCR_MAPS
 
- HVTRAMP_DESCR_NUM_MAPPINGS
 
- HVTRAMP_DESCR_THREAD_REG
 
- HVTRAMP_MAPPING_SIZE
 
- HVTRAMP_MAPPING_TTE
 
- HVTRAMP_MAPPING_VADDR
 
- HVUTIL_DEVICE_DYING
 
- HVUTIL_DEVICE_INIT
 
- HVUTIL_HOSTMSG_RECEIVED
 
- HVUTIL_READY
 
- HVUTIL_TRANSPORT_CHARDEV
 
- HVUTIL_TRANSPORT_DESTROY
 
- HVUTIL_TRANSPORT_INIT
 
- HVUTIL_TRANSPORT_NETLINK
 
- HVUTIL_USERSPACE_RECV
 
- HVUTIL_USERSPACE_REQ
 
- HV_24X7_CATALOG_MAGIC
 
- HV_AVMA1_GUID
 
- HV_AVMA2_GUID
 
- HV_BACKUP
 
- HV_BALANCED
 
- HV_BUTTON_FROM_GD
 
- HV_CALL_BATCHED
 
- HV_CALL_DIRECT
 
- HV_CALL_ISR
 
- HV_CAPS_ATTR
 
- HV_CCB_ALL_OR_NOTHING
 
- HV_CCB_ARG0_PRIVILEGED
 
- HV_CCB_ARG0_TYPE_NUCLEUS
 
- HV_CCB_ARG0_TYPE_PRIMARY
 
- HV_CCB_ARG0_TYPE_REAL
 
- HV_CCB_ARG0_TYPE_SECONDARY
 
- HV_CCB_INFO
 
- HV_CCB_KILL
 
- HV_CCB_KILL_COMPLETED
 
- HV_CCB_KILL_DEQUEUED
 
- HV_CCB_KILL_KILLED
 
- HV_CCB_KILL_NOTFOUND
 
- HV_CCB_QUERY_CMD
 
- HV_CCB_QUEUE_INFO
 
- HV_CCB_STATE_COMPLETED
 
- HV_CCB_STATE_ENQUEUED
 
- HV_CCB_STATE_INPROGRESS
 
- HV_CCB_STATE_NOTFOUND
 
- HV_CCB_SUBMIT
 
- HV_CCB_VA_NUCLEUS
 
- HV_CCB_VA_PRIVILEGED
 
- HV_CCB_VA_READ_ADI_DISABLE
 
- HV_CCB_VA_REJECT
 
- HV_CCB_VA_SECONDARY
 
- HV_CLOCK_HZ
 
- HV_CLOCK_SIZE
 
- HV_COLC_LOWER
 
- HV_COLC_UPPER
 
- HV_CONFIG_BLOCK_SIZE_MAX
 
- HV_CORE_EXIT
 
- HV_CORE_GET_VER
 
- HV_CORE_PUTCHAR
 
- HV_CORE_SET_VER
 
- HV_CORE_TRAP
 
- HV_CPU_QUEUE_CPU_MONDO
 
- HV_CPU_QUEUE_DEVICE_MONDO
 
- HV_CPU_QUEUE_NONRES_ERROR
 
- HV_CPU_QUEUE_RES_ERROR
 
- HV_CPU_STATE_ERROR
 
- HV_CPU_STATE_RUNNING
 
- HV_CPU_STATE_STOPPED
 
- HV_CRASH_CTL_CRASH_NOTIFY
 
- HV_CRASH_CTL_CRASH_NOTIFY_MSG
 
- HV_CROP
 
- HV_CTRL_ENABLE
 
- HV_CTRL_TEST
 
- HV_CTRL_TO_PME
 
- HV_DC_LOWER
 
- HV_DC_UPPER
 
- HV_DEFAULT_L4HASH
 
- HV_DEPRECATING_AEOI_RECOMMENDED
 
- HV_DEVICE_INTERRUPT_TARGET_MULTICAST
 
- HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET
 
- HV_DM
 
- HV_DM_GUID
 
- HV_DRV_VERSION
 
- HV_EBADALIGN
 
- HV_EBADPGSZ
 
- HV_EBADTRAP
 
- HV_EBADTSB
 
- HV_EBUSY
 
- HV_ECHANNEL
 
- HV_ECOL_LOWER
 
- HV_ECOL_UPPER
 
- HV_ECPUERROR
 
- HV_EINVAL
 
- HV_EIO
 
- HV_ENOACCESS
 
- HV_ENOCPU
 
- HV_ENOINTR
 
- HV_ENOMAP
 
- HV_ENORADDR
 
- HV_ENOTSUPPORTED
 
- HV_EOK
 
- HV_ERROR_ALREADY_EXISTS
 
- HV_ERROR_DEVICE_NOT_CONNECTED
 
- HV_ERROR_DISK_FULL
 
- HV_ERROR_MACHINE_LOCKED
 
- HV_ERROR_NOT_SUPPORTED
 
- HV_ETOOMANY
 
- HV_EUNAVAILABLE
 
- HV_EVENT_FLAGS_COUNT
 
- HV_EVENT_FLAGS_LONG_COUNT
 
- HV_EWOULDBLOCK
 
- HV_E_FAIL
 
- HV_FACTOR
 
- HV_FAST_CONS_GETCHAR
 
- HV_FAST_CONS_PUTCHAR
 
- HV_FAST_CONS_READ
 
- HV_FAST_CONS_WRITE
 
- HV_FAST_CPU_GET_RTBA
 
- HV_FAST_CPU_MONDO_SEND
 
- HV_FAST_CPU_MYID
 
- HV_FAST_CPU_POKE
 
- HV_FAST_CPU_QCONF
 
- HV_FAST_CPU_QINFO
 
- HV_FAST_CPU_SET_RTBA
 
- HV_FAST_CPU_START
 
- HV_FAST_CPU_STATE
 
- HV_FAST_CPU_STOP
 
- HV_FAST_CPU_YIELD
 
- HV_FAST_DUMP_BUF_INFO
 
- HV_FAST_DUMP_BUF_UPDATE
 
- HV_FAST_FIRE_GET_PERFREG
 
- HV_FAST_FIRE_SET_PERFREG
 
- HV_FAST_GET_PERFREG
 
- HV_FAST_INTR_DEVINO2SYSINO
 
- HV_FAST_INTR_GETENABLED
 
- HV_FAST_INTR_GETSTATE
 
- HV_FAST_INTR_GETTARGET
 
- HV_FAST_INTR_SETENABLED
 
- HV_FAST_INTR_SETSTATE
 
- HV_FAST_INTR_SETTARGET
 
- HV_FAST_LDC_COPY
 
- HV_FAST_LDC_GET_MAP_TABLE
 
- HV_FAST_LDC_MAPIN
 
- HV_FAST_LDC_REVOKE
 
- HV_FAST_LDC_RX_GET_STATE
 
- HV_FAST_LDC_RX_QCONF
 
- HV_FAST_LDC_RX_QINFO
 
- HV_FAST_LDC_RX_SET_QHEAD
 
- HV_FAST_LDC_SET_MAP_TABLE
 
- HV_FAST_LDC_TX_GET_STATE
 
- HV_FAST_LDC_TX_QCONF
 
- HV_FAST_LDC_TX_QINFO
 
- HV_FAST_LDC_TX_SET_QTAIL
 
- HV_FAST_LDC_UNMAP
 
- HV_FAST_M7_GET_PERFREG
 
- HV_FAST_M7_SET_PERFREG
 
- HV_FAST_MACH_DESC
 
- HV_FAST_MACH_EXIT
 
- HV_FAST_MACH_GET_SOFT_STATE
 
- HV_FAST_MACH_SET_SOFT_STATE
 
- HV_FAST_MACH_SET_WATCHDOG
 
- HV_FAST_MACH_SIR
 
- HV_FAST_MEM_SCRUB
 
- HV_FAST_MEM_SYNC
 
- HV_FAST_MMUSTAT_CONF
 
- HV_FAST_MMUSTAT_INFO
 
- HV_FAST_MMU_DEMAP_ALL
 
- HV_FAST_MMU_DEMAP_CTX
 
- HV_FAST_MMU_DEMAP_PAGE
 
- HV_FAST_MMU_ENABLE
 
- HV_FAST_MMU_FAULT_AREA_CONF
 
- HV_FAST_MMU_FAULT_AREA_INFO
 
- HV_FAST_MMU_MAP_PERM_ADDR
 
- HV_FAST_MMU_TSB_CTX0
 
- HV_FAST_MMU_TSB_CTX0_INFO
 
- HV_FAST_MMU_TSB_CTXNON0
 
- HV_FAST_MMU_TSB_CTXNON0_INFO
 
- HV_FAST_MMU_UNMAP_PERM_ADDR
 
- HV_FAST_N2_GET_PERFREG
 
- HV_FAST_N2_SET_PERFREG
 
- HV_FAST_NCS_GETHEAD
 
- HV_FAST_NCS_GETTAIL
 
- HV_FAST_NCS_QCONF
 
- HV_FAST_NCS_QHANDLE_TO_DEVINO
 
- HV_FAST_NCS_QINFO
 
- HV_FAST_NCS_REQUEST
 
- HV_FAST_NCS_SETHEAD_MARKER
 
- HV_FAST_NCS_SETTAIL
 
- HV_FAST_PCI_CONFIG_GET
 
- HV_FAST_PCI_CONFIG_PUT
 
- HV_FAST_PCI_DMA_SYNC
 
- HV_FAST_PCI_IOMMU_DEMAP
 
- HV_FAST_PCI_IOMMU_GETBYPASS
 
- HV_FAST_PCI_IOMMU_GETMAP
 
- HV_FAST_PCI_IOMMU_MAP
 
- HV_FAST_PCI_IOTSB_BIND
 
- HV_FAST_PCI_IOTSB_CONF
 
- HV_FAST_PCI_IOTSB_DEMAP
 
- HV_FAST_PCI_IOTSB_GETMAP
 
- HV_FAST_PCI_IOTSB_GET_BINDING
 
- HV_FAST_PCI_IOTSB_INFO
 
- HV_FAST_PCI_IOTSB_MAP
 
- HV_FAST_PCI_IOTSB_MAP_ONE
 
- HV_FAST_PCI_IOTSB_SYNC_MAPPINGS
 
- HV_FAST_PCI_IOTSB_UNBIND
 
- HV_FAST_PCI_IOTSB_UNCONF
 
- HV_FAST_PCI_MSG_GETMSIQ
 
- HV_FAST_PCI_MSG_GETVALID
 
- HV_FAST_PCI_MSG_SETMSIQ
 
- HV_FAST_PCI_MSG_SETVALID
 
- HV_FAST_PCI_MSIQ_CONF
 
- HV_FAST_PCI_MSIQ_GETHEAD
 
- HV_FAST_PCI_MSIQ_GETSTATE
 
- HV_FAST_PCI_MSIQ_GETTAIL
 
- HV_FAST_PCI_MSIQ_GETVALID
 
- HV_FAST_PCI_MSIQ_INFO
 
- HV_FAST_PCI_MSIQ_SETHEAD
 
- HV_FAST_PCI_MSIQ_SETSTATE
 
- HV_FAST_PCI_MSIQ_SETVALID
 
- HV_FAST_PCI_MSI_GETMSIQ
 
- HV_FAST_PCI_MSI_GETSTATE
 
- HV_FAST_PCI_MSI_GETVALID
 
- HV_FAST_PCI_MSI_SETMSIQ
 
- HV_FAST_PCI_MSI_SETSTATE
 
- HV_FAST_PCI_MSI_SETVALID
 
- HV_FAST_PCI_PEEK
 
- HV_FAST_PCI_POKE
 
- HV_FAST_REBOOT_DATA_SET
 
- HV_FAST_RNG_CTL_READ
 
- HV_FAST_RNG_CTL_WRITE
 
- HV_FAST_RNG_DATA_READ
 
- HV_FAST_RNG_DATA_READ_DIAG
 
- HV_FAST_RNG_GET_DIAG_CTL
 
- HV_FAST_SET_PERFREG
 
- HV_FAST_SVC_CLRSTATUS
 
- HV_FAST_SVC_GETSTATUS
 
- HV_FAST_SVC_RECV
 
- HV_FAST_SVC_SEND
 
- HV_FAST_SVC_SETSTATUS
 
- HV_FAST_T5_GET_PERFREG
 
- HV_FAST_T5_SET_PERFREG
 
- HV_FAST_TOD_GET
 
- HV_FAST_TOD_SET
 
- HV_FAST_TRAP
 
- HV_FAST_TTRACE_BUF_CONF
 
- HV_FAST_TTRACE_BUF_INFO
 
- HV_FAST_TTRACE_ENABLE
 
- HV_FAST_TTRACE_FREEZE
 
- HV_FAST_VINTR_GET_COOKIE
 
- HV_FAST_VINTR_GET_STATE
 
- HV_FAST_VINTR_GET_TARGET
 
- HV_FAST_VINTR_GET_VALID
 
- HV_FAST_VINTR_SET_COOKIE
 
- HV_FAST_VINTR_SET_STATE
 
- HV_FAST_VINTR_SET_TARGET
 
- HV_FAST_VINTR_SET_VALID
 
- HV_FAST_VT_GET_PERFREG
 
- HV_FAST_VT_SET_PERFREG
 
- HV_FAULT_D_ADDR_OFFSET
 
- HV_FAULT_D_CTX_OFFSET
 
- HV_FAULT_D_TYPE_OFFSET
 
- HV_FAULT_I_ADDR_OFFSET
 
- HV_FAULT_I_CTX_OFFSET
 
- HV_FAULT_I_TYPE_OFFSET
 
- HV_FAULT_TYPE_FAST_MISS
 
- HV_FAULT_TYPE_FAST_PROT
 
- HV_FAULT_TYPE_INV_ASI
 
- HV_FAULT_TYPE_INV_PGSZ
 
- HV_FAULT_TYPE_INV_RA
 
- HV_FAULT_TYPE_INV_VA
 
- HV_FAULT_TYPE_MCD
 
- HV_FAULT_TYPE_MCD_DIS
 
- HV_FAULT_TYPE_MMU_MISS
 
- HV_FAULT_TYPE_MULTIPLE
 
- HV_FAULT_TYPE_NC_ATOMIC
 
- HV_FAULT_TYPE_NFO
 
- HV_FAULT_TYPE_NFO_SEFF
 
- HV_FAULT_TYPE_PRIV_ACT
 
- HV_FAULT_TYPE_PRIV_VIOL
 
- HV_FAULT_TYPE_PROT_VIOL
 
- HV_FAULT_TYPE_RESV1
 
- HV_FAULT_TYPE_UNALIGNED
 
- HV_FB
 
- HV_FC
 
- HV_FCOPY
 
- HV_FCOPY_GUID
 
- HV_FEATURE_FREQUENCY_MSRS_AVAILABLE
 
- HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE
 
- HV_FLUSH_ALL_PROCESSORS
 
- HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES
 
- HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY
 
- HV_FLUSH_USE_EXTENDED_RANGE_FORMAT
 
- HV_GENERIC_SET_ALL
 
- HV_GENERIC_SET_FORMAT
 
- HV_GENERIC_SET_SPARSE_4K
 
- HV_GPCI_CM_EXPANDED
 
- HV_GPCI_CM_GA
 
- HV_GPCI_CM_LAB
 
- HV_GRP_ATU
 
- HV_GRP_CORE
 
- HV_GRP_DAX
 
- HV_GRP_DIAG
 
- HV_GRP_FIRE_PERF
 
- HV_GRP_INTR
 
- HV_GRP_KT_CPU
 
- HV_GRP_LDOM
 
- HV_GRP_M7_PERF
 
- HV_GRP_N2_CPU
 
- HV_GRP_NCS
 
- HV_GRP_NIAG_PERF
 
- HV_GRP_NIU
 
- HV_GRP_PBOOT
 
- HV_GRP_PCI
 
- HV_GRP_REBOOT_DATA
 
- HV_GRP_RNG
 
- HV_GRP_SDIO
 
- HV_GRP_SDIO_ERR
 
- HV_GRP_SOFT_STATE
 
- HV_GRP_SUN4V
 
- HV_GRP_SVC_CHAN
 
- HV_GRP_T5_CPU
 
- HV_GRP_TM
 
- HV_GRP_TPM
 
- HV_GRP_VF_CPU
 
- HV_GRP_VT_CPU
 
- HV_GUEST_STATE_VERSION
 
- HV_GUID_NOTFOUND
 
- HV_HB
 
- HV_HEART_BEAT_GUID
 
- HV_HYPERCALL_FAST_BIT
 
- HV_HYPERCALL_PARAM_ALIGN
 
- HV_HYPERCALL_REP_COMP_MASK
 
- HV_HYPERCALL_REP_COMP_OFFSET
 
- HV_HYPERCALL_REP_START_MASK
 
- HV_HYPERCALL_REP_START_OFFSET
 
- HV_HYPERCALL_RESULT_MASK
 
- HV_HYPERCALL_VARHEAD_OFFSET
 
- HV_HYP_PAGE_MASK
 
- HV_HYP_PAGE_SHIFT
 
- HV_HYP_PAGE_SIZE
 
- HV_IDE
 
- HV_IDE_GUID
 
- HV_INTC_FC_PAGE_START
 
- HV_INTR_DISABLED
 
- HV_INTR_ENABLED
 
- HV_INTR_STATE_DELIVERED
 
- HV_INTR_STATE_IDLE
 
- HV_INTR_STATE_RECEIVED
 
- HV_INT_ENABLE
 
- HV_INT_PENDING
 
- HV_INVALIDARG
 
- HV_IPI_HIGH_VECTOR
 
- HV_IPI_LOW_VECTOR
 
- HV_KBD
 
- HV_KBD_GUID
 
- HV_KMRN_FIFO_CTRLSTA
 
- HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
 
- HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
 
- HV_KMRN_MDIO_SLOW
 
- HV_KMRN_MODE_CTRL
 
- HV_KVP
 
- HV_KVP_EXCHANGE_MAX_KEY_SIZE
 
- HV_KVP_EXCHANGE_MAX_VALUE_SIZE
 
- HV_KVP_GUID
 
- HV_LATECOL_LOWER
 
- HV_LATECOL_UPPER
 
- HV_LED_CONFIG
 
- HV_LINUX_VENDOR_ID
 
- HV_LOCALIZED
 
- HV_MAX_FLUSH_PAGES
 
- HV_MAX_FLUSH_REP_COUNT
 
- HV_MAX_MAX_DELTA_TICKS
 
- HV_MCC_LOWER
 
- HV_MCC_UPPER
 
- HV_MESSAGE_PAYLOAD_BYTE_COUNT
 
- HV_MESSAGE_PAYLOAD_QWORD_COUNT
 
- HV_MESSAGE_SIZE
 
- HV_MIN_DELTA_TICKS
 
- HV_MMU_ALL
 
- HV_MMU_DMMU
 
- HV_MMU_IMMU
 
- HV_MMU_MAP_ADDR_TRAP
 
- HV_MMU_UNMAP_ADDR_TRAP
 
- HV_MOUSE
 
- HV_MOUSE_GUID
 
- HV_MSG_INVALID
 
- HV_MSG_VALID
 
- HV_MSIQSTATE_ERROR
 
- HV_MSIQSTATE_IDLE
 
- HV_MSIQ_INVALID
 
- HV_MSIQ_VALID
 
- HV_MSISTATE_DELIVERED
 
- HV_MSISTATE_IDLE
 
- HV_MSITYPE_MSI32
 
- HV_MSITYPE_MSI64
 
- HV_MSIVALID_INVALID
 
- HV_MSIVALID_VALID
 
- HV_MSR_REFERENCE_TSC_AVAILABLE
 
- HV_MSR_SYNTIMER_AVAILABLE
 
- HV_MSR_TIME_REF_COUNT_AVAILABLE
 
- HV_MUX_DATA_CTRL
 
- HV_MUX_DATA_CTRL_FORCE_SPEED
 
- HV_MUX_DATA_CTRL_GEN_TO_MAC
 
- HV_M_STATUS
 
- HV_M_STATUS_AUTONEG_COMPLETE
 
- HV_M_STATUS_LINK_UP
 
- HV_M_STATUS_SPEED_100
 
- HV_M_STATUS_SPEED_1000
 
- HV_M_STATUS_SPEED_MASK
 
- HV_N2_PERF_DRAM_CNT0
 
- HV_N2_PERF_DRAM_CNT1
 
- HV_N2_PERF_DRAM_CNT2
 
- HV_N2_PERF_DRAM_CNT3
 
- HV_N2_PERF_DRAM_CTL0
 
- HV_N2_PERF_DRAM_CTL1
 
- HV_N2_PERF_DRAM_CTL2
 
- HV_N2_PERF_DRAM_CTL3
 
- HV_N2_PERF_SPARC_CTL
 
- HV_NCS_QCONF
 
- HV_NCS_QTAIL_UPDATE
 
- HV_NCS_QTYPE_CWQ
 
- HV_NCS_QTYPE_MAU
 
- HV_NCS_SYNCFLAG_ASYNC
 
- HV_NCS_SYNCFLAG_SYNC
 
- HV_ND
 
- HV_ND_GUID
 
- HV_NIC
 
- HV_NIC_GUID
 
- HV_OEM_BITS
 
- HV_OEM_BITS_GBE_DIS
 
- HV_OEM_BITS_LPLU
 
- HV_OEM_BITS_RESTART_AN
 
- HV_OFFSET
 
- HV_PARTITION_ID_SELF
 
- HV_PCIE
 
- HV_PCIE_GUID
 
- HV_PCIE_MSGTYPE_CORR_MSG
 
- HV_PCIE_MSGTYPE_FATAL_MSG
 
- HV_PCIE_MSGTYPE_NONFATAL_MSG
 
- HV_PCIE_MSGTYPE_PME_ACK_MSG
 
- HV_PCIE_MSGTYPE_PME_MSG
 
- HV_PCI_DEVICE_BUILD
 
- HV_PCI_IOTSB_INDEX_COUNT
 
- HV_PCI_MAP_ATTR_READ
 
- HV_PCI_MAP_ATTR_RELAXED_ORDER
 
- HV_PCI_MAP_ATTR_WRITE
 
- HV_PCI_SYNC_FOR_CPU
 
- HV_PCI_SYNC_FOR_DEVICE
 
- HV_PCI_TSBID
 
- HV_PERF_DOMAIN_
 
- HV_PERF_DOMAIN_MAX
 
- HV_PERF_DRAM_PERF_CNT_REG_0
 
- HV_PERF_DRAM_PERF_CNT_REG_1
 
- HV_PERF_DRAM_PERF_CNT_REG_2
 
- HV_PERF_DRAM_PERF_CNT_REG_3
 
- HV_PERF_DRAM_PERF_CTRL_REG_0
 
- HV_PERF_DRAM_PERF_CTRL_REG_1
 
- HV_PERF_DRAM_PERF_CTRL_REG_2
 
- HV_PERF_DRAM_PERF_CTRL_REG_3
 
- HV_PERF_JBUS_PERF_CNT_REG
 
- HV_PERF_JBUS_PERF_CTRL_REG
 
- HV_PGSZ_IDX_16GB
 
- HV_PGSZ_IDX_256MB
 
- HV_PGSZ_IDX_2GB
 
- HV_PGSZ_IDX_32MB
 
- HV_PGSZ_IDX_4MB
 
- HV_PGSZ_IDX_512K
 
- HV_PGSZ_IDX_64K
 
- HV_PGSZ_IDX_8K
 
- HV_PGSZ_IDX_BASE
 
- HV_PGSZ_IDX_HUGE
 
- HV_PGSZ_MASK_16GB
 
- HV_PGSZ_MASK_256MB
 
- HV_PGSZ_MASK_2GB
 
- HV_PGSZ_MASK_32MB
 
- HV_PGSZ_MASK_4MB
 
- HV_PGSZ_MASK_512K
 
- HV_PGSZ_MASK_64K
 
- HV_PGSZ_MASK_8K
 
- HV_PGSZ_MASK_BASE
 
- HV_PGSZ_MASK_HUGE
 
- HV_PM_CTRL
 
- HV_PM_CTRL_K1_CLK_REQ
 
- HV_PM_CTRL_K1_ENABLE
 
- HV_PROCESSOR_POWER_STATE_C0
 
- HV_PROCESSOR_POWER_STATE_C1
 
- HV_PROCESSOR_POWER_STATE_C2
 
- HV_PROCESSOR_POWER_STATE_C3
 
- HV_PROTOCOL_HVSI
 
- HV_PROTOCOL_RAW
 
- HV_RDV_GUID
 
- HV_REFERENCE_TSC_PAGE
 
- HV_RING_SIZE
 
- HV_RNG_NUM_CONTROL
 
- HV_RNG_STATE_CONFIGURED
 
- HV_RNG_STATE_ERROR
 
- HV_RNG_STATE_HEALTHCHECK
 
- HV_RNG_STATE_UNCONFIGURED
 
- HV_RST
 
- HV_SCC_LOWER
 
- HV_SCC_UPPER
 
- HV_SCSI
 
- HV_SCSI_GUID
 
- HV_SHUTDOWN
 
- HV_SHUTDOWN_GUID
 
- HV_SIZE
 
- HV_SMB_ADDR
 
- HV_SMB_ADDR_FREQ_HIGH_SHIFT
 
- HV_SMB_ADDR_FREQ_LOW_SHIFT
 
- HV_SMB_ADDR_FREQ_MASK
 
- HV_SMB_ADDR_MASK
 
- HV_SMB_ADDR_PEC_EN
 
- HV_SMB_ADDR_VALID
 
- HV_SOFT_STATE_NORMAL
 
- HV_SOFT_STATE_TRANSITION
 
- HV_STATS_PAGE
 
- HV_STATUS_INSUFFICIENT_BUFFERS
 
- HV_STATUS_INSUFFICIENT_MEMORY
 
- HV_STATUS_INVALID_ALIGNMENT
 
- HV_STATUS_INVALID_CONNECTION_ID
 
- HV_STATUS_INVALID_HYPERCALL_CODE
 
- HV_STATUS_INVALID_HYPERCALL_INPUT
 
- HV_STATUS_INVALID_PARAMETER
 
- HV_STATUS_INVALID_PORT_ID
 
- HV_STATUS_SUCCESS
 
- HV_STIMER_DIRECT_MODE_AVAILABLE
 
- HV_SUPPORT_HFSCR
 
- HV_SUPPORT_NONE
 
- HV_SYNIC_CONTROL_ENABLE
 
- HV_SYNIC_FIRST_VALID_VECTOR
 
- HV_SYNIC_SIEFP_ENABLE
 
- HV_SYNIC_SIMP_ENABLE
 
- HV_SYNIC_SINT_AUTO_EOI
 
- HV_SYNIC_SINT_COUNT
 
- HV_SYNIC_SINT_MASKED
 
- HV_SYNIC_SINT_VECTOR_MASK
 
- HV_SYNIC_STIMER_COUNT
 
- HV_SYNIC_VERSION_1
 
- HV_SYNTHFC_GUID
 
- HV_SYNTHVID_GUID
 
- HV_S_CONT
 
- HV_S_OK
 
- HV_TCP4_L4HASH
 
- HV_TCP6_L4HASH
 
- HV_TLB_FLUSH_UNIT
 
- HV_TNCRS_LOWER
 
- HV_TNCRS_UPPER
 
- HV_TRAP_TRACE_CTRL_HEAD_OFFSET
 
- HV_TRAP_TRACE_CTRL_TAIL_OFFSET
 
- HV_TRAP_TRACE_ENTRY_F1
 
- HV_TRAP_TRACE_ENTRY_F2
 
- HV_TRAP_TRACE_ENTRY_F3
 
- HV_TRAP_TRACE_ENTRY_F4
 
- HV_TRAP_TRACE_ENTRY_GL
 
- HV_TRAP_TRACE_ENTRY_HPSTATE
 
- HV_TRAP_TRACE_ENTRY_TAG
 
- HV_TRAP_TRACE_ENTRY_TICK
 
- HV_TRAP_TRACE_ENTRY_TL
 
- HV_TRAP_TRACE_ENTRY_TPC
 
- HV_TRAP_TRACE_ENTRY_TSTATE
 
- HV_TRAP_TRACE_ENTRY_TT
 
- HV_TRAP_TRACE_ENTRY_TYPE
 
- HV_TRAP_TYPE_GUEST
 
- HV_TRAP_TYPE_HV
 
- HV_TRAP_TYPE_UNDEF
 
- HV_TS
 
- HV_TSB_DESCR_ASSOC_OFFSET
 
- HV_TSB_DESCR_CTX_IDX_OFFSET
 
- HV_TSB_DESCR_NUM_TTES_OFFSET
 
- HV_TSB_DESCR_PGSZ_IDX_OFFSET
 
- HV_TSB_DESCR_PGSZ_MASK_OFFSET
 
- HV_TSB_DESCR_RESV_OFFSET
 
- HV_TSB_DESCR_TSB_BASE_OFFSET
 
- HV_TS_GUID
 
- HV_TTRACE_ADDENTRY_TRAP
 
- HV_UDP4_L4HASH
 
- HV_UDP6_L4HASH
 
- HV_UNKNOWN
 
- HV_UTIL_NEGO_TIMEOUT
 
- HV_UTIL_TIMEOUT
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP
 
- HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE
 
- HV_VSS_GUID
 
- HV_X64_ACCESS_FREQUENCY_MSRS
 
- HV_X64_ACCESS_MEMORY_POOL
 
- HV_X64_ACCESS_PARTITION_ID
 
- HV_X64_ACCESS_REENLIGHTENMENT
 
- HV_X64_ACCESS_STATS
 
- HV_X64_ADJUST_MESSAGE_BUFFERS
 
- HV_X64_APIC_ACCESS_RECOMMENDED
 
- HV_X64_AS_SWITCH_RECOMMENDED
 
- HV_X64_CLUSTER_IPI_RECOMMENDED
 
- HV_X64_CONNECT_PORT
 
- HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE
 
- HV_X64_CPU_POWER_MANAGEMENT
 
- HV_X64_CREATE_PARTITIONS
 
- HV_X64_CREATE_PORT
 
- HV_X64_DEBUGGING
 
- HV_X64_ENLIGHTENED_VMCS_RECOMMENDED
 
- HV_X64_ENLIGHTENED_VMCS_VERSION
 
- HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED
 
- HV_X64_GUEST_DEBUGGING_AVAILABLE
 
- HV_X64_GUEST_IDLE_STATE_AVAILABLE
 
- HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE
 
- HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED
 
- HV_X64_MSR_APIC_ACCESS_AVAILABLE
 
- HV_X64_MSR_APIC_FREQUENCY
 
- HV_X64_MSR_CRASH_CTL
 
- HV_X64_MSR_CRASH_P0
 
- HV_X64_MSR_CRASH_P1
 
- HV_X64_MSR_CRASH_P2
 
- HV_X64_MSR_CRASH_P3
 
- HV_X64_MSR_CRASH_P4
 
- HV_X64_MSR_CRASH_PARAMS
 
- HV_X64_MSR_EOI
 
- HV_X64_MSR_EOM
 
- HV_X64_MSR_GUEST_IDLE
 
- HV_X64_MSR_GUEST_IDLE_AVAILABLE
 
- HV_X64_MSR_GUEST_OS_ID
 
- HV_X64_MSR_HYPERCALL
 
- HV_X64_MSR_HYPERCALL_AVAILABLE
 
- HV_X64_MSR_HYPERCALL_ENABLE
 
- HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK
 
- HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT
 
- HV_X64_MSR_ICR
 
- HV_X64_MSR_REENLIGHTENMENT_CONTROL
 
- HV_X64_MSR_REFERENCE_TSC
 
- HV_X64_MSR_RESET
 
- HV_X64_MSR_RESET_AVAILABLE
 
- HV_X64_MSR_SCONTROL
 
- HV_X64_MSR_SIEFP
 
- HV_X64_MSR_SIMP
 
- HV_X64_MSR_SINT0
 
- HV_X64_MSR_SINT1
 
- HV_X64_MSR_SINT10
 
- HV_X64_MSR_SINT11
 
- HV_X64_MSR_SINT12
 
- HV_X64_MSR_SINT13
 
- HV_X64_MSR_SINT14
 
- HV_X64_MSR_SINT15
 
- HV_X64_MSR_SINT2
 
- HV_X64_MSR_SINT3
 
- HV_X64_MSR_SINT4
 
- HV_X64_MSR_SINT5
 
- HV_X64_MSR_SINT6
 
- HV_X64_MSR_SINT7
 
- HV_X64_MSR_SINT8
 
- HV_X64_MSR_SINT9
 
- HV_X64_MSR_STAT_PAGES_AVAILABLE
 
- HV_X64_MSR_STIMER0_CONFIG
 
- HV_X64_MSR_STIMER0_COUNT
 
- HV_X64_MSR_STIMER1_CONFIG
 
- HV_X64_MSR_STIMER1_COUNT
 
- HV_X64_MSR_STIMER2_CONFIG
 
- HV_X64_MSR_STIMER2_COUNT
 
- HV_X64_MSR_STIMER3_CONFIG
 
- HV_X64_MSR_STIMER3_COUNT
 
- HV_X64_MSR_SVERSION
 
- HV_X64_MSR_SYNIC_AVAILABLE
 
- HV_X64_MSR_TIME_REF_COUNT
 
- HV_X64_MSR_TPR
 
- HV_X64_MSR_TSC_EMULATION_CONTROL
 
- HV_X64_MSR_TSC_EMULATION_STATUS
 
- HV_X64_MSR_TSC_FREQUENCY
 
- HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT
 
- HV_X64_MSR_TSC_REFERENCE_ENABLE
 
- HV_X64_MSR_VP_ASSIST_PAGE
 
- HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK
 
- HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT
 
- HV_X64_MSR_VP_ASSIST_PAGE_ENABLE
 
- HV_X64_MSR_VP_INDEX
 
- HV_X64_MSR_VP_INDEX_AVAILABLE
 
- HV_X64_MSR_VP_RUNTIME
 
- HV_X64_MSR_VP_RUNTIME_AVAILABLE
 
- HV_X64_MWAIT_AVAILABLE
 
- HV_X64_NESTED_DIRECT_FLUSH
 
- HV_X64_NESTED_GUEST_MAPPING_FLUSH
 
- HV_X64_NESTED_MSR_BITMAP
 
- HV_X64_NO_NONARCH_CORESHARING
 
- HV_X64_PERF_MONITOR_AVAILABLE
 
- HV_X64_POST_MESSAGES
 
- HV_X64_RELAXED_TIMING_RECOMMENDED
 
- HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED
 
- HV_X64_SIGNAL_EVENTS
 
- HV_X64_SYSTEM_RESET_RECOMMENDED
 
- HW1_TS_PUSH_EN
 
- HW2_I2C1_INT
 
- HW2_I2C2_INT
 
- HW2_INT_CLR_STATUS
 
- HW2_INT_MASK5_PCI
 
- HW2_TS_PUSH_EN
 
- HW3_TS_PUSH_EN
 
- HW4_TS_PUSH_EN
 
- HW90_BLOCK_MAC
 
- HW90_BLOCK_MAXIMUM
 
- HW90_BLOCK_PHY0
 
- HW90_BLOCK_PHY1
 
- HW90_BLOCK_RF
 
- HWA742_AUTO_UPDATE_TIME
 
- HWA742_CLK_SRC_REG
 
- HWA742_CONFIG_REG
 
- HWA742_DISP_MODE_REG
 
- HWA742_HP_S_REG
 
- HWA742_HS_W_REG
 
- HWA742_H_DISP_REG
 
- HWA742_H_NDP_REG
 
- HWA742_INPUT_MODE_REG
 
- HWA742_MEMORY_READ_0
 
- HWA742_MEMORY_READ_1
 
- HWA742_MEMORY_READ_2
 
- HWA742_MEMORY_WRITE_LSB
 
- HWA742_MEMORY_WRITE_MSB
 
- HWA742_NDP_CTRL
 
- HWA742_PANEL_TYPE_REG
 
- HWA742_PCLK_POL_REG
 
- HWA742_PLL_0_REG
 
- HWA742_PLL_1_REG
 
- HWA742_PLL_2_REG
 
- HWA742_PLL_3_REG
 
- HWA742_PLL_4_REG
 
- HWA742_PLL_DIV_REG
 
- HWA742_POWER_SAVE
 
- HWA742_REV_CODE_REG
 
- HWA742_TRANSL_MODE_REG1
 
- HWA742_VP_S_REG
 
- HWA742_VS_W_REG
 
- HWA742_V_DISP_1_REG
 
- HWA742_V_DISP_2_REG
 
- HWA742_V_NDP_REG
 
- HWA742_WINDOW_TYPE
 
- HWA742_WINDOW_X_END_0
 
- HWA742_WINDOW_X_END_1
 
- HWA742_WINDOW_X_START_0
 
- HWA742_WINDOW_X_START_1
 
- HWA742_WINDOW_Y_END_0
 
- HWA742_WINDOW_Y_END_1
 
- HWA742_WINDOW_Y_START_0
 
- HWA742_WINDOW_Y_START_1
 
- HWABR
 
- HWACC_PWR_ST_OK
 
- HWACR
 
- HWAHC_EPROTO_MAX
 
- HWAHC_EPROTO_PERIOD
 
- HWA_NOTIF_BPST_ADJ
 
- HWA_NOTIF_DN
 
- HWBLKINST_HWBLK_MASK
 
- HWBLKINST_HWBLK_SHIFT
 
- HWBLKINST_INSTANCE_MASK
 
- HWBLK_2DDMAC
 
- HWBLK_2DG
 
- HWBLK_ADC
 
- HWBLK_ATAPI
 
- HWBLK_BEU
 
- HWBLK_BEU0
 
- HWBLK_BEU1
 
- HWBLK_CEU
 
- HWBLK_CEU0
 
- HWBLK_CEU1
 
- HWBLK_CMT
 
- HWBLK_DMAC0
 
- HWBLK_DMAC1
 
- HWBLK_ETHER
 
- HWBLK_FLCTL
 
- HWBLK_FPU
 
- HWBLK_HUDI
 
- HWBLK_IC
 
- HWBLK_ICB
 
- HWBLK_IIC
 
- HWBLK_IIC0
 
- HWBLK_IIC1
 
- HWBLK_ILMEM
 
- HWBLK_INTC
 
- HWBLK_IRDA
 
- HWBLK_JPU
 
- HWBLK_KEYSC
 
- HWBLK_L2C
 
- HWBLK_LCDC
 
- HWBLK_MERAM
 
- HWBLK_MMC
 
- HWBLK_MSIOF0
 
- HWBLK_MSIOF1
 
- HWBLK_NR
 
- HWBLK_OC
 
- HWBLK_RSMEM
 
- HWBLK_RTC
 
- HWBLK_RWDT
 
- HWBLK_SCIF0
 
- HWBLK_SCIF1
 
- HWBLK_SCIF2
 
- HWBLK_SCIF3
 
- HWBLK_SCIF4
 
- HWBLK_SCIF5
 
- HWBLK_SDHI
 
- HWBLK_SDHI0
 
- HWBLK_SDHI1
 
- HWBLK_SHYWAY
 
- HWBLK_SIU
 
- HWBLK_SPU
 
- HWBLK_TLB
 
- HWBLK_TMU
 
- HWBLK_TMU0
 
- HWBLK_TMU1
 
- HWBLK_TPU
 
- HWBLK_TSIF
 
- HWBLK_UBC
 
- HWBLK_URAM
 
- HWBLK_USB
 
- HWBLK_USB0
 
- HWBLK_USB1
 
- HWBLK_USBF
 
- HWBLK_VEU
 
- HWBLK_VEU0
 
- HWBLK_VEU1
 
- HWBLK_VEU2H0
 
- HWBLK_VEU2H1
 
- HWBLK_VOU
 
- HWBLK_VPU
 
- HWBLK_XYMEM
 
- HWBUG_ASIFLUSH_BROKEN
 
- HWBUG_COPYBACK_BROKEN
 
- HWBUG_KERN_ACCBROKEN
 
- HWBUG_KERN_CBITBROKEN
 
- HWBUG_MODIFIED_BITROT
 
- HWBUG_PACINIT_BITROT
 
- HWBUG_PC_BADFAULT_ADDR
 
- HWBUG_SUPERSCALAR_BAD
 
- HWBUG_VACFLUSH_BITROT
 
- HWBUTTON_HI
 
- HWBUTTON_LO
 
- HWCAP2_AES
 
- HWCAP2_CRC32
 
- HWCAP2_DCPODP
 
- HWCAP2_FLAGM2
 
- HWCAP2_FRINT
 
- HWCAP2_PMULL
 
- HWCAP2_RING3MWAIT
 
- HWCAP2_SHA1
 
- HWCAP2_SHA2
 
- HWCAP2_SVE2
 
- HWCAP2_SVEAES
 
- HWCAP2_SVEBITPERM
 
- HWCAP2_SVEPMULL
 
- HWCAP2_SVESHA3
 
- HWCAP2_SVESM4
 
- HWCAP_26BIT
 
- HWCAP_AES
 
- HWCAP_ASIMD
 
- HWCAP_ASIMDDP
 
- HWCAP_ASIMDFHM
 
- HWCAP_ASIMDHP
 
- HWCAP_ASIMDRDM
 
- HWCAP_ATOMICS
 
- HWCAP_AUDIO
 
- HWCAP_BASE16
 
- HWCAP_CAP
 
- HWCAP_CAP_MATCH
 
- HWCAP_CMOV
 
- HWCAP_CPUID
 
- HWCAP_CPUID_MATCH
 
- HWCAP_CRC32
 
- HWCAP_CRUNCH
 
- HWCAP_DCPOP
 
- HWCAP_DIT
 
- HWCAP_DIV
 
- HWCAP_DX_REGS
 
- HWCAP_EDM
 
- HWCAP_EDSP
 
- HWCAP_ENCRYPT
 
- HWCAP_EVTSTRM
 
- HWCAP_EXT
 
- HWCAP_EXT2
 
- HWCAP_FAST_MULT
 
- HWCAP_FCMA
 
- HWCAP_FLAGM
 
- HWCAP_FP
 
- HWCAP_FPA
 
- HWCAP_FPHP
 
- HWCAP_FPU
 
- HWCAP_FPU_DP
 
- HWCAP_HALF
 
- HWCAP_HSMP
 
- HWCAP_HWPRE
 
- HWCAP_IDIV
 
- HWCAP_IDIVA
 
- HWCAP_IDIVT
 
- HWCAP_ILRCPC
 
- HWCAP_INT_SIE
 
- HWCAP_IWMMXT
 
- HWCAP_JAVA
 
- HWCAP_JSCVT
 
- HWCAP_L2C
 
- HWCAP_LMDMA
 
- HWCAP_LOONGSON_EXT
 
- HWCAP_LOONGSON_EXT2
 
- HWCAP_LOONGSON_MMI
 
- HWCAP_LPAE
 
- HWCAP_LRCPC
 
- HWCAP_MAC
 
- HWCAP_MFUSR_PC
 
- HWCAP_MIPS_CRC32
 
- HWCAP_MIPS_DSP
 
- HWCAP_MIPS_DSP2
 
- HWCAP_MIPS_DSP3
 
- HWCAP_MIPS_MDMX
 
- HWCAP_MIPS_MIPS16
 
- HWCAP_MIPS_MIPS16E2
 
- HWCAP_MIPS_MIPS3D
 
- HWCAP_MIPS_MSA
 
- HWCAP_MIPS_R6
 
- HWCAP_MIPS_SMARTMIPS
 
- HWCAP_MSP
 
- HWCAP_MULTI_CAP
 
- HWCAP_NEON
 
- HWCAP_PACA
 
- HWCAP_PACG
 
- HWCAP_PFM
 
- HWCAP_PMULL
 
- HWCAP_REDUCED_REGS
 
- HWCAP_S390_DFLT
 
- HWCAP_S390_DFP
 
- HWCAP_S390_EIMM
 
- HWCAP_S390_ESAN3
 
- HWCAP_S390_ETF3EH
 
- HWCAP_S390_GS
 
- HWCAP_S390_HIGH_GPRS
 
- HWCAP_S390_HPAGE
 
- HWCAP_S390_LDISP
 
- HWCAP_S390_MSA
 
- HWCAP_S390_SORT
 
- HWCAP_S390_STFLE
 
- HWCAP_S390_TE
 
- HWCAP_S390_VXRS
 
- HWCAP_S390_VXRS_BCD
 
- HWCAP_S390_VXRS_EXT
 
- HWCAP_S390_VXRS_EXT2
 
- HWCAP_S390_VXRS_PDE
 
- HWCAP_S390_ZARCH
 
- HWCAP_SB
 
- HWCAP_SHA1
 
- HWCAP_SHA2
 
- HWCAP_SHA3
 
- HWCAP_SHA512
 
- HWCAP_SM3
 
- HWCAP_SM4
 
- HWCAP_SPARC_ADI
 
- HWCAP_SPARC_BLKINIT
 
- HWCAP_SPARC_CRYPTO
 
- HWCAP_SPARC_FLUSH
 
- HWCAP_SPARC_MULDIV
 
- HWCAP_SPARC_N2
 
- HWCAP_SPARC_STBAR
 
- HWCAP_SPARC_SWAP
 
- HWCAP_SPARC_ULTRA3
 
- HWCAP_SPARC_V9
 
- HWCAP_SSBS
 
- HWCAP_STRING
 
- HWCAP_SVE
 
- HWCAP_SWP
 
- HWCAP_THUMB
 
- HWCAP_THUMBEE
 
- HWCAP_TLS
 
- HWCAP_TRACE
 
- HWCAP_UNICORE16
 
- HWCAP_UNICORE_F64
 
- HWCAP_USCAT
 
- HWCAP_V2
 
- HWCAP_VFP
 
- HWCAP_VFPD32
 
- HWCAP_VFPv3
 
- HWCAP_VFPv3D16
 
- HWCAP_VFPv4
 
- HWCAP_VIDEO
 
- HWCLK_POLL_INTERVAL
 
- HWCONF_TERMINATE_OFF
 
- HWCONF_TERMINATE_ON
 
- HWCURC0
 
- HWCURC1
 
- HWCURLOC
 
- HWCURPATADDR
 
- HWCURSOR_ENABLE
 
- HWC_ADDRESS
 
- HWC_ADDRESS_ADDRESS_MASK
 
- HWC_ADDRESS_CS
 
- HWC_ADDRESS_ENABLE
 
- HWC_ADDRESS_EXT
 
- HWC_COLOR_12
 
- HWC_COLOR_12_1_RGB565_MASK
 
- HWC_COLOR_12_2_RGB565_MASK
 
- HWC_COLOR_12_2_RGB565_SHIFT
 
- HWC_COLOR_3
 
- HWC_COLOR_3_RGB565_MASK
 
- HWC_FRAMEDONE
 
- HWC_FRAMEDONE_ENA
 
- HWC_FRAMEDONE_ENA_MASK
 
- HWC_FRAMEDONE_LEVEL
 
- HWC_FRAMEDONE_LEVEL_MASK
 
- HWC_FRAMEDONE_MASK
 
- HWC_LOCATION
 
- HWC_LOCATION_LEFT
 
- HWC_LOCATION_TOP
 
- HWC_LOCATION_X_MASK
 
- HWC_LOCATION_Y_MASK
 
- HWC_LOCATION_Y_SHIFT
 
- HWDLH
 
- HWDLL
 
- HWEF_SIZE
 
- HWEIGHT
 
- HWEIGHT16
 
- HWEIGHT32
 
- HWEIGHT64
 
- HWEIGHT8
 
- HWEIGHT_WHOLE
 
- HWEVENT_opts
 
- HWEV_ALL_SENT
 
- HWEV_DCD_OFF
 
- HWEV_DCD_ON
 
- HWEX_MSR_BIT
 
- HWE_AUTO
 
- HWE_AUTO_P
 
- HWE_MASK
 
- HWFCR
 
- HWFOR
 
- HWFQ_EMPTY_INT_BIT
 
- HWH_TYPE_INVALID
 
- HWH_TYPE_IO
 
- HWH_TYPE_IO_RD
 
- HWH_TYPE_LOGIN
 
- HWH_TYPE_LOGOUT
 
- HWH_TYPE_NOP
 
- HWH_TYPE_TMF
 
- HWI2C400
 
- HWI2C_WAIT_TIMEOUT
 
- HWICAP_DEVICES
 
- HWICAP_REGS
 
- HWID
 
- HWID_MASK
 
- HWID_MCATYPE
 
- HWID_MINIP16
 
- HWID_MINIP4
 
- HWID_MINIP8
 
- HWID_NONE
 
- HWID_OFFSET
 
- HWIER
 
- HWIIR
 
- HWILSE_INTERFACE_F0
 
- HWINFO_MAX_CAPS_GROUPS
 
- HWINFO_NAME_SIZE_BYTES
 
- HWINFO_SIZE_MIN
 
- HWINFO_WAIT
 
- HWINT_DISABLED
 
- HWINT_ENABLED
 
- HWIP_MAX_INSTANCE
 
- HWIRQ_BANK
 
- HWIRQ_BIT
 
- HWIRQ_TO_DEVID
 
- HWIRQ_TO_GPIO
 
- HWIRQ_TO_IRQID
 
- HWISR
 
- HWI_GET_ASYNC_PDU_CTX
 
- HWI_GET_DEF_BUFQ_ID
 
- HWI_GET_DEF_HDRQ_ID
 
- HWI_MEM_ADDN_CONTEXT
 
- HWI_MEM_ASYNC_DATA_BUF_ULP0
 
- HWI_MEM_ASYNC_DATA_BUF_ULP1
 
- HWI_MEM_ASYNC_DATA_HANDLE_ULP0
 
- HWI_MEM_ASYNC_DATA_HANDLE_ULP1
 
- HWI_MEM_ASYNC_DATA_RING_ULP0
 
- HWI_MEM_ASYNC_DATA_RING_ULP1
 
- HWI_MEM_ASYNC_HEADER_BUF_ULP0
 
- HWI_MEM_ASYNC_HEADER_BUF_ULP1
 
- HWI_MEM_ASYNC_HEADER_HANDLE_ULP0
 
- HWI_MEM_ASYNC_HEADER_HANDLE_ULP1
 
- HWI_MEM_ASYNC_HEADER_RING_ULP0
 
- HWI_MEM_ASYNC_HEADER_RING_ULP1
 
- HWI_MEM_ASYNC_PDU_CONTEXT_ULP0
 
- HWI_MEM_ASYNC_PDU_CONTEXT_ULP1
 
- HWI_MEM_SGE
 
- HWI_MEM_SGLH
 
- HWI_MEM_TEMPLATE_HDR_ULP0
 
- HWI_MEM_TEMPLATE_HDR_ULP1
 
- HWI_MEM_WRB
 
- HWI_MEM_WRBH
 
- HWLCR
 
- HWLOCK_IN_ATOMIC
 
- HWLOCK_IRQ
 
- HWLOCK_IRQSTATE
 
- HWLOCK_RAW
 
- HWLSR
 
- HWMCR
 
- HWME_EDTHRESHOLD
 
- HWME_EDVALUE
 
- HWME_GET_CONFIRM
 
- HWME_GET_REQUEST
 
- HWME_LQILIMIT
 
- HWME_SET_CONFIRM
 
- HWME_SET_REQUEST
 
- HWME_SYSCLKOUT
 
- HWME_WAKEUP_INDICATION
 
- HWMOD_16BIT_REG
 
- HWMOD_BLOCK_WFI
 
- HWMOD_CLKDM_NOAUTO
 
- HWMOD_CONTROL_OPT_CLKS_IN_RESET
 
- HWMOD_EXT_OPT_MAIN_CLK
 
- HWMOD_FORCE_MSTANDBY
 
- HWMOD_IDLEMODE_FORCE
 
- HWMOD_IDLEMODE_NO
 
- HWMOD_IDLEMODE_SMART
 
- HWMOD_IDLEMODE_SMART_WKUP
 
- HWMOD_INIT_NO_IDLE
 
- HWMOD_INIT_NO_RESET
 
- HWMOD_NO_IDLE
 
- HWMOD_NO_IDLEST
 
- HWMOD_NO_OCP_AUTOIDLE
 
- HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK
 
- HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
 
- HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET
 
- HWMOD_OPT_CLKS_NEEDED
 
- HWMOD_RECONFIG_IO_CHAIN
 
- HWMOD_SET_DEFAULT_CLOCKACT
 
- HWMOD_SWSUP_MSTANDBY
 
- HWMOD_SWSUP_SIDLE
 
- HWMOD_SWSUP_SIDLE_ACT
 
- HWMON_CHANNEL_INFO
 
- HWMON_C_ALARM
 
- HWMON_C_ALARMS
 
- HWMON_C_AVERAGE
 
- HWMON_C_CRIT
 
- HWMON_C_CRIT_ALARM
 
- HWMON_C_CURR_RESET_HISTORY
 
- HWMON_C_CURR_SAMPLES
 
- HWMON_C_HIGHEST
 
- HWMON_C_INPUT
 
- HWMON_C_IN_RESET_HISTORY
 
- HWMON_C_IN_SAMPLES
 
- HWMON_C_LABEL
 
- HWMON_C_LCRIT
 
- HWMON_C_LCRIT_ALARM
 
- HWMON_C_LOWEST
 
- HWMON_C_MAX
 
- HWMON_C_MAX_ALARM
 
- HWMON_C_MIN
 
- HWMON_C_MIN_ALARM
 
- HWMON_C_POWER_RESET_HISTORY
 
- HWMON_C_POWER_SAMPLES
 
- HWMON_C_REGISTER_TZ
 
- HWMON_C_RESET_HISTORY
 
- HWMON_C_SAMPLES
 
- HWMON_C_TEMP_RESET_HISTORY
 
- HWMON_C_TEMP_SAMPLES
 
- HWMON_C_UPDATE_INTERVAL
 
- HWMON_E_INPUT
 
- HWMON_E_LABEL
 
- HWMON_F_ALARM
 
- HWMON_F_DIV
 
- HWMON_F_FAULT
 
- HWMON_F_INPUT
 
- HWMON_F_LABEL
 
- HWMON_F_MAX
 
- HWMON_F_MAX_ALARM
 
- HWMON_F_MIN
 
- HWMON_F_MIN_ALARM
 
- HWMON_F_PULSES
 
- HWMON_F_TARGET
 
- HWMON_H_ALARM
 
- HWMON_H_FAULT
 
- HWMON_H_INPUT
 
- HWMON_H_LABEL
 
- HWMON_H_MAX
 
- HWMON_H_MAX_HYST
 
- HWMON_H_MIN
 
- HWMON_H_MIN_HYST
 
- HWMON_ID_FORMAT
 
- HWMON_ID_PREFIX
 
- HWMON_I_ALARM
 
- HWMON_I_AVERAGE
 
- HWMON_I_CRIT
 
- HWMON_I_CRIT_ALARM
 
- HWMON_I_ENABLE
 
- HWMON_I_HIGHEST
 
- HWMON_I_INPUT
 
- HWMON_I_LABEL
 
- HWMON_I_LCRIT
 
- HWMON_I_LCRIT_ALARM
 
- HWMON_I_LOWEST
 
- HWMON_I_MAX
 
- HWMON_I_MAX_ALARM
 
- HWMON_I_MIN
 
- HWMON_I_MIN_ALARM
 
- HWMON_I_RESET_HISTORY
 
- HWMON_NR_SENSOR_TYPES
 
- HWMON_PACK_ENABLE
 
- HWMON_PACK_FLAGS
 
- HWMON_PACK_LIMIT1
 
- HWMON_PACK_LIMIT2
 
- HWMON_PACK_NAME
 
- HWMON_PWM_ENABLE
 
- HWMON_PWM_FREQ
 
- HWMON_PWM_INPUT
 
- HWMON_PWM_MODE
 
- HWMON_P_ACCURACY
 
- HWMON_P_ALARM
 
- HWMON_P_AVERAGE
 
- HWMON_P_AVERAGE_HIGHEST
 
- HWMON_P_AVERAGE_INTERVAL
 
- HWMON_P_AVERAGE_INTERVAL_MAX
 
- HWMON_P_AVERAGE_INTERVAL_MIN
 
- HWMON_P_AVERAGE_LOWEST
 
- HWMON_P_AVERAGE_MAX
 
- HWMON_P_AVERAGE_MIN
 
- HWMON_P_CAP
 
- HWMON_P_CAP_ALARM
 
- HWMON_P_CAP_HYST
 
- HWMON_P_CAP_MAX
 
- HWMON_P_CAP_MIN
 
- HWMON_P_CRIT
 
- HWMON_P_CRIT_ALARM
 
- HWMON_P_INPUT
 
- HWMON_P_INPUT_HIGHEST
 
- HWMON_P_INPUT_LOWEST
 
- HWMON_P_LABEL
 
- HWMON_P_LCRIT
 
- HWMON_P_LCRIT_ALARM
 
- HWMON_P_MAX
 
- HWMON_P_MAX_ALARM
 
- HWMON_P_MIN
 
- HWMON_P_MIN_ALARM
 
- HWMON_P_RESET_HISTORY
 
- HWMON_TYPE_FAN
 
- HWMON_TYPE_TEMP
 
- HWMON_TYPE_VOLT
 
- HWMON_T_ALARM
 
- HWMON_T_CRIT
 
- HWMON_T_CRIT_ALARM
 
- HWMON_T_CRIT_HYST
 
- HWMON_T_EMERGENCY
 
- HWMON_T_EMERGENCY_ALARM
 
- HWMON_T_EMERGENCY_HYST
 
- HWMON_T_FAULT
 
- HWMON_T_HIGHEST
 
- HWMON_T_INPUT
 
- HWMON_T_LABEL
 
- HWMON_T_LCRIT
 
- HWMON_T_LCRIT_ALARM
 
- HWMON_T_LCRIT_HYST
 
- HWMON_T_LOWEST
 
- HWMON_T_MAX
 
- HWMON_T_MAX_ALARM
 
- HWMON_T_MAX_HYST
 
- HWMON_T_MIN
 
- HWMON_T_MIN_ALARM
 
- HWMON_T_MIN_HYST
 
- HWMON_T_OFFSET
 
- HWMON_T_RESET_HISTORY
 
- HWMON_T_TYPE
 
- HWMSR
 
- HWMTM
 
- HWM_ASYNC_TXD_COUNT
 
- HWM_E0001
 
- HWM_E0001_MSG
 
- HWM_E0002
 
- HWM_E0002_MSG
 
- HWM_E0003
 
- HWM_E0003_MSG
 
- HWM_E0004
 
- HWM_E0004_MSG
 
- HWM_E0005
 
- HWM_E0005_MSG
 
- HWM_E0006
 
- HWM_E0006_MSG
 
- HWM_E0007
 
- HWM_E0007_MSG
 
- HWM_E0008
 
- HWM_E0008_MSG
 
- HWM_E0009
 
- HWM_E0009_MSG
 
- HWM_E0010
 
- HWM_E0010_MSG
 
- HWM_E0011
 
- HWM_E0011_MSG
 
- HWM_E0012
 
- HWM_E0012_MSG
 
- HWM_E0013
 
- HWM_E0013_MSG
 
- HWM_EBASE
 
- HWM_GET_CURR_RXD
 
- HWM_GET_CURR_TXD
 
- HWM_GET_RX_FRAG_LEN
 
- HWM_GET_RX_FREE
 
- HWM_GET_RX_PHYS
 
- HWM_GET_RX_USED
 
- HWM_GET_TX_LEN
 
- HWM_GET_TX_PHYS
 
- HWM_GET_TX_USED
 
- HWM_RX_CHECK
 
- HWM_SYNC_TXD_COUNT
 
- HWORD
 
- HWORD_START
 
- HWPC
 
- HWPC_RX_CTRL
 
- HWPC_TX_EN
 
- HWPI
 
- HWP_ACTIVITY_WINDOW
 
- HWP_ACTIVITY_WINDOW_BIT
 
- HWP_BASE_BIT
 
- HWP_CAP_HIGHEST
 
- HWP_CAP_LOWEST
 
- HWP_CHANGE_TO_GUARANTEED_INT
 
- HWP_DESIRED_PERF
 
- HWP_ENERGY_PERF_PREFERENCE
 
- HWP_ENERGY_PERF_PREFERENCE_BIT
 
- HWP_EPP_BALANCE_PERFORMANCE
 
- HWP_EPP_BALANCE_POWERSAVE
 
- HWP_EPP_PERFORMANCE
 
- HWP_EPP_POWERSAVE
 
- HWP_EXCURSION_TO_MINIMUM
 
- HWP_EXCURSION_TO_MINIMUM_INT
 
- HWP_GUARANTEED_CHANGE
 
- HWP_GUARANTEED_PERF
 
- HWP_HIGHEST_PERF
 
- HWP_HXS_COUNT
 
- HWP_HXS_PCAC_PSTAT
 
- HWP_HXS_PCAC_PSTOP
 
- HWP_HXS_PHE_REPORT
 
- HWP_HXS_SH_PAD_REM
 
- HWP_HXS_TCP_OFFSET
 
- HWP_HXS_UDP_OFFSET
 
- HWP_LOWEST_PERF
 
- HWP_MAX_PERF
 
- HWP_MIN_PERF
 
- HWP_MOSTEFFICIENT_PERF
 
- HWP_NOTIFICATIONS_BIT
 
- HWP_OFFSET
 
- HWP_PACKAGE_CONTROL
 
- HWP_PACKAGE_LEVEL_REQUEST_BIT
 
- HWP_PORT_REGS_OFFSET
 
- HWP_RPIMAC_PEN
 
- HWQ_CMP
 
- HWQ_FREE_SLOTS
 
- HWQ_MODE_CPU
 
- HWQ_MODE_RR
 
- HWQ_MODE_TAG
 
- HWQ_TYPE_CTX
 
- HWQ_TYPE_L2_CMPL
 
- HWQ_TYPE_QUEUE
 
- HWRBR
 
- HWRENA
 
- HWRM_CFA_ADV_FLOW_MGNT_QCAPS
 
- HWRM_CFA_COUNTER_CFG
 
- HWRM_CFA_COUNTER_QCAPS
 
- HWRM_CFA_COUNTER_QCFG
 
- HWRM_CFA_COUNTER_QSTATS
 
- HWRM_CFA_CTX_MEM_QCAPS
 
- HWRM_CFA_CTX_MEM_QCTX
 
- HWRM_CFA_CTX_MEM_RGTR
 
- HWRM_CFA_CTX_MEM_UNRGTR
 
- HWRM_CFA_DECAP_FILTER_ALLOC
 
- HWRM_CFA_DECAP_FILTER_FREE
 
- HWRM_CFA_EEM_CFG
 
- HWRM_CFA_EEM_OP
 
- HWRM_CFA_EEM_QCAPS
 
- HWRM_CFA_EEM_QCFG
 
- HWRM_CFA_EM_FLOW_ALLOC
 
- HWRM_CFA_EM_FLOW_CFG
 
- HWRM_CFA_EM_FLOW_FREE
 
- HWRM_CFA_ENCAP_RECORD_ALLOC
 
- HWRM_CFA_ENCAP_RECORD_FREE
 
- HWRM_CFA_FLOW_AGING_CFG
 
- HWRM_CFA_FLOW_AGING_QCAPS
 
- HWRM_CFA_FLOW_AGING_QCFG
 
- HWRM_CFA_FLOW_AGING_TIMER_RESET
 
- HWRM_CFA_FLOW_ALLOC
 
- HWRM_CFA_FLOW_FLUSH
 
- HWRM_CFA_FLOW_FREE
 
- HWRM_CFA_FLOW_INFO
 
- HWRM_CFA_FLOW_STATS
 
- HWRM_CFA_L2_FILTER_ALLOC
 
- HWRM_CFA_L2_FILTER_CFG
 
- HWRM_CFA_L2_FILTER_FREE
 
- HWRM_CFA_L2_SET_RX_MASK
 
- HWRM_CFA_METER_INSTANCE_ALLOC
 
- HWRM_CFA_METER_INSTANCE_CFG
 
- HWRM_CFA_METER_INSTANCE_FREE
 
- HWRM_CFA_METER_PROFILE_ALLOC
 
- HWRM_CFA_METER_PROFILE_CFG
 
- HWRM_CFA_METER_PROFILE_FREE
 
- HWRM_CFA_METER_QCAPS
 
- HWRM_CFA_NTUPLE_FILTER_ALLOC
 
- HWRM_CFA_NTUPLE_FILTER_CFG
 
- HWRM_CFA_NTUPLE_FILTER_FREE
 
- HWRM_CFA_PAIR_ALLOC
 
- HWRM_CFA_PAIR_FREE
 
- HWRM_CFA_PAIR_INFO
 
- HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE
 
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC
 
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE
 
- HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO
 
- HWRM_CFA_TCP_FLAG_PROCESS_QCFG
 
- HWRM_CFA_TFLIB
 
- HWRM_CFA_TUNNEL_FILTER_ALLOC
 
- HWRM_CFA_TUNNEL_FILTER_FREE
 
- HWRM_CFA_VFR_ALLOC
 
- HWRM_CFA_VFR_FREE
 
- HWRM_CFA_VF_PAIR_ALLOC
 
- HWRM_CFA_VF_PAIR_FREE
 
- HWRM_CFA_VF_PAIR_INFO
 
- HWRM_CFA_VLAN_ANTISPOOF_CFG
 
- HWRM_CFA_VLAN_ANTISPOOF_QCFG
 
- HWRM_CMD_TIMEOUT
 
- HWRM_COREDUMP_TIMEOUT
 
- HWRM_DBG_CFG
 
- HWRM_DBG_CMN_FLAGS_MORE
 
- HWRM_DBG_COREDUMP_INITIATE
 
- HWRM_DBG_COREDUMP_LIST
 
- HWRM_DBG_COREDUMP_RETRIEVE
 
- HWRM_DBG_CRASHDUMP_ERASE
 
- HWRM_DBG_CRASHDUMP_HEADER
 
- HWRM_DBG_DUMP
 
- HWRM_DBG_ERASE_NVM
 
- HWRM_DBG_FW_CLI
 
- HWRM_DBG_I2C_CMD
 
- HWRM_DBG_READ_DIRECT
 
- HWRM_DBG_READ_INDIRECT
 
- HWRM_DBG_RING_INFO_GET
 
- HWRM_DBG_WRITE_DIRECT
 
- HWRM_DBG_WRITE_INDIRECT
 
- HWRM_ENGINE_CKV_CKEK_ADD
 
- HWRM_ENGINE_CKV_CKEK_DELETE
 
- HWRM_ENGINE_CKV_FLUSH
 
- HWRM_ENGINE_CKV_KEY_ADD
 
- HWRM_ENGINE_CKV_KEY_DELETE
 
- HWRM_ENGINE_CKV_KEY_GEN
 
- HWRM_ENGINE_CKV_KEY_LABEL_CFG
 
- HWRM_ENGINE_CKV_KEY_LABEL_QCFG
 
- HWRM_ENGINE_CKV_RNG_GET
 
- HWRM_ENGINE_CKV_STATUS
 
- HWRM_ENGINE_CONFIG_QUERY
 
- HWRM_ENGINE_CQ_ALLOC
 
- HWRM_ENGINE_CQ_FREE
 
- HWRM_ENGINE_FUNC_QCFG
 
- HWRM_ENGINE_NQ_ALLOC
 
- HWRM_ENGINE_NQ_FREE
 
- HWRM_ENGINE_ON_DIE_RQE_CREDITS
 
- HWRM_ENGINE_QG_CONFIG_QUERY
 
- HWRM_ENGINE_QG_FUNC_BIND
 
- HWRM_ENGINE_QG_METER_BIND
 
- HWRM_ENGINE_QG_METER_PROFILE_ALLOC
 
- HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY
 
- HWRM_ENGINE_QG_METER_PROFILE_FREE
 
- HWRM_ENGINE_QG_METER_PROFILE_QUERY
 
- HWRM_ENGINE_QG_METER_QUERY
 
- HWRM_ENGINE_QG_METER_UNBIND
 
- HWRM_ENGINE_QG_QUERY
 
- HWRM_ENGINE_QG_SG_UNBIND
 
- HWRM_ENGINE_RQ_ALLOC
 
- HWRM_ENGINE_RQ_FREE
 
- HWRM_ENGINE_SG_CONFIG_QUERY
 
- HWRM_ENGINE_SG_METER_CONFIG
 
- HWRM_ENGINE_SG_METER_QUERY
 
- HWRM_ENGINE_SG_QG_BIND
 
- HWRM_ENGINE_SG_QUERY
 
- HWRM_ENGINE_STATS_CLEAR
 
- HWRM_ENGINE_STATS_CONFIG
 
- HWRM_ENGINE_STATS_QUERY
 
- HWRM_ERROR_RECOVERY_QCFG
 
- HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 
- HWRM_ERR_CODE_FAIL
 
- HWRM_ERR_CODE_HOT_RESET_FAIL
 
- HWRM_ERR_CODE_HOT_RESET_PROGRESS
 
- HWRM_ERR_CODE_HWRM_ERROR
 
- HWRM_ERR_CODE_INVALID_ENABLES
 
- HWRM_ERR_CODE_INVALID_FLAGS
 
- HWRM_ERR_CODE_INVALID_PARAMS
 
- HWRM_ERR_CODE_KEY_ALREADY_EXISTS
 
- HWRM_ERR_CODE_KEY_HASH_COLLISION
 
- HWRM_ERR_CODE_LAST
 
- HWRM_ERR_CODE_NO_BUFFER
 
- HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC
 
- HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED
 
- HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR
 
- HWRM_ERR_CODE_SUCCESS
 
- HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE
 
- HWRM_ERR_CODE_UNKNOWN_ERR
 
- HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR
 
- HWRM_ERR_CODE_UNSUPPORTED_TLV
 
- HWRM_EXEC_FWD_RESP
 
- HWRM_FUNC_BACKING_STORE_CFG
 
- HWRM_FUNC_BACKING_STORE_QCAPS
 
- HWRM_FUNC_BACKING_STORE_QCFG
 
- HWRM_FUNC_BUF_RGTR
 
- HWRM_FUNC_BUF_UNRGTR
 
- HWRM_FUNC_CFG
 
- HWRM_FUNC_CLR_STATS
 
- HWRM_FUNC_DRV_IF_CHANGE
 
- HWRM_FUNC_DRV_QVER
 
- HWRM_FUNC_DRV_RGTR
 
- HWRM_FUNC_DRV_UNRGTR
 
- HWRM_FUNC_GETFID
 
- HWRM_FUNC_HOST_PF_IDS_QUERY
 
- HWRM_FUNC_QCAPS
 
- HWRM_FUNC_QCFG
 
- HWRM_FUNC_QSTATS
 
- HWRM_FUNC_RESET
 
- HWRM_FUNC_RESOURCE_QCAPS
 
- HWRM_FUNC_VF_ALLOC
 
- HWRM_FUNC_VF_BW_CFG
 
- HWRM_FUNC_VF_BW_QCFG
 
- HWRM_FUNC_VF_CFG
 
- HWRM_FUNC_VF_FREE
 
- HWRM_FUNC_VF_RESC_FREE
 
- HWRM_FUNC_VF_RESOURCE_CFG
 
- HWRM_FUNC_VF_VNIC_IDS_QUERY
 
- HWRM_FUNC_VLAN_CFG
 
- HWRM_FUNC_VLAN_QCFG
 
- HWRM_FWD_ASYNC_EVENT_CMPL
 
- HWRM_FWD_RESP
 
- HWRM_FW_GET_STRUCTURED_DATA
 
- HWRM_FW_GET_TIME
 
- HWRM_FW_HEALTH_CHECK
 
- HWRM_FW_IPC_MAILBOX
 
- HWRM_FW_IPC_MSG
 
- HWRM_FW_QSTATUS
 
- HWRM_FW_RESET
 
- HWRM_FW_SET_STRUCTURED_DATA
 
- HWRM_FW_SET_TIME
 
- HWRM_FW_STATE_BACKUP
 
- HWRM_FW_STATE_BUFFER_QCAPS
 
- HWRM_FW_STATE_QUIESCE
 
- HWRM_FW_STATE_RESTORE
 
- HWRM_FW_SYNC
 
- HWRM_LAST
 
- HWRM_MAX_REQ_LEN
 
- HWRM_MAX_RESP_LEN
 
- HWRM_MAX_TIMEOUT
 
- HWRM_MFG_FRU_WRITE_CONTROL
 
- HWRM_MFG_HDMA_TEST
 
- HWRM_MFG_OTP_CFG
 
- HWRM_MFG_OTP_QCFG
 
- HWRM_MFG_TIMERS_QUERY
 
- HWRM_MIN_TIMEOUT
 
- HWRM_NA_SIGNATURE
 
- HWRM_NVM_ERASE_DIR_ENTRY
 
- HWRM_NVM_FACTORY_DEFAULTS
 
- HWRM_NVM_FIND_DIR_ENTRY
 
- HWRM_NVM_FLUSH
 
- HWRM_NVM_GET_DEV_INFO
 
- HWRM_NVM_GET_DIR_ENTRIES
 
- HWRM_NVM_GET_DIR_INFO
 
- HWRM_NVM_GET_VARIABLE
 
- HWRM_NVM_INSTALL_UPDATE
 
- HWRM_NVM_MODIFY
 
- HWRM_NVM_MOD_DIR_ENTRY
 
- HWRM_NVM_RAW_DUMP
 
- HWRM_NVM_RAW_WRITE_BLK
 
- HWRM_NVM_READ
 
- HWRM_NVM_SET_VARIABLE
 
- HWRM_NVM_VALIDATE_OPTION
 
- HWRM_NVM_VERIFY_UPDATE
 
- HWRM_NVM_WRITE
 
- HWRM_OEM_CMD
 
- HWRM_PCIE_QSTATS
 
- HWRM_PORT_CLR_STATS
 
- HWRM_PORT_LED_CFG
 
- HWRM_PORT_LED_QCAPS
 
- HWRM_PORT_LED_QCFG
 
- HWRM_PORT_LPBK_CLR_STATS
 
- HWRM_PORT_LPBK_QSTATS
 
- HWRM_PORT_MAC_CFG
 
- HWRM_PORT_MAC_PTP_QCFG
 
- HWRM_PORT_MAC_QCFG
 
- HWRM_PORT_PHY_CFG
 
- HWRM_PORT_PHY_I2C_READ
 
- HWRM_PORT_PHY_I2C_WRITE
 
- HWRM_PORT_PHY_MDIO_BUS_ACQUIRE
 
- HWRM_PORT_PHY_MDIO_BUS_RELEASE
 
- HWRM_PORT_PHY_MDIO_READ
 
- HWRM_PORT_PHY_MDIO_WRITE
 
- HWRM_PORT_PHY_QCAPS
 
- HWRM_PORT_PHY_QCFG
 
- HWRM_PORT_PRBS_TEST
 
- HWRM_PORT_QSTATS
 
- HWRM_PORT_QSTATS_EXT
 
- HWRM_PORT_SFP_SIDEBAND_CFG
 
- HWRM_PORT_SFP_SIDEBAND_QCFG
 
- HWRM_PORT_TS_QUERY
 
- HWRM_QUEUE_CFG
 
- HWRM_QUEUE_COS2BW_CFG
 
- HWRM_QUEUE_COS2BW_QCFG
 
- HWRM_QUEUE_DSCP2PRI_CFG
 
- HWRM_QUEUE_DSCP2PRI_QCFG
 
- HWRM_QUEUE_DSCP_QCAPS
 
- HWRM_QUEUE_PFCENABLE_CFG
 
- HWRM_QUEUE_PFCENABLE_QCFG
 
- HWRM_QUEUE_PRI2COS_CFG
 
- HWRM_QUEUE_PRI2COS_QCFG
 
- HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN
 
- HWRM_QUEUE_QCFG
 
- HWRM_QUEUE_QPORTCFG
 
- HWRM_REG_POWER_QUERY
 
- HWRM_REJECT_FWD_RESP
 
- HWRM_RESERVED1
 
- HWRM_RESERVED5
 
- HWRM_RESERVED6
 
- HWRM_RESET_TIMEOUT
 
- HWRM_RESP_ERR_CODE_MASK
 
- HWRM_RESP_LEN_MASK
 
- HWRM_RESP_LEN_OFFSET
 
- HWRM_RESP_LEN_SFT
 
- HWRM_RESP_VALID_KEY
 
- HWRM_RESP_VALID_MASK
 
- HWRM_RING_AGGINT_QCAPS
 
- HWRM_RING_ALLOC
 
- HWRM_RING_ALLOC_AGG
 
- HWRM_RING_ALLOC_CMPL
 
- HWRM_RING_ALLOC_NQ
 
- HWRM_RING_ALLOC_RX
 
- HWRM_RING_ALLOC_TX
 
- HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
 
- HWRM_RING_CMPL_RING_QAGGINT_PARAMS
 
- HWRM_RING_FREE
 
- HWRM_RING_GRP_ALLOC
 
- HWRM_RING_GRP_FREE
 
- HWRM_RING_RESET
 
- HWRM_SELFTEST_EXEC
 
- HWRM_SELFTEST_IRQ
 
- HWRM_SELFTEST_QLIST
 
- HWRM_SELFTEST_RETRIEVE_SERDES_DATA
 
- HWRM_SHORT_MAX_TIMEOUT
 
- HWRM_SHORT_MIN_TIMEOUT
 
- HWRM_SHORT_TIMEOUT_COUNTER
 
- HWRM_STAT_CTX_ALLOC
 
- HWRM_STAT_CTX_CLR_STATS
 
- HWRM_STAT_CTX_ENG_QUERY
 
- HWRM_STAT_CTX_FREE
 
- HWRM_STAT_CTX_QUERY
 
- HWRM_STRUCT_DATA_SUBTYPE_HOST_OPERATIONAL
 
- HWRM_TARGET_ID_APE
 
- HWRM_TARGET_ID_BONO
 
- HWRM_TARGET_ID_KONG
 
- HWRM_TARGET_ID_TOOLS
 
- HWRM_TEMP_MONITOR_QUERY
 
- HWRM_TOTAL_TIMEOUT
 
- HWRM_TUNNEL_DST_PORT_ALLOC
 
- HWRM_TUNNEL_DST_PORT_FREE
 
- HWRM_TUNNEL_DST_PORT_QUERY
 
- HWRM_VALID_BIT_DELAY_USEC
 
- HWRM_VERSION_MAJOR
 
- HWRM_VERSION_MINOR
 
- HWRM_VERSION_RCFW_CMDQ_DEPTH_CHECK
 
- HWRM_VERSION_RSVD
 
- HWRM_VERSION_STR
 
- HWRM_VERSION_UPDATE
 
- HWRM_VER_GET
 
- HWRM_VNIC_ALLOC
 
- HWRM_VNIC_CFG
 
- HWRM_VNIC_FREE
 
- HWRM_VNIC_PLCMODES_CFG
 
- HWRM_VNIC_PLCMODES_QCFG
 
- HWRM_VNIC_QCAPS
 
- HWRM_VNIC_QCFG
 
- HWRM_VNIC_RSS_CFG
 
- HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
 
- HWRM_VNIC_RSS_COS_LB_CTX_FREE
 
- HWRM_VNIC_RSS_QCFG
 
- HWRM_VNIC_TPA_CFG
 
- HWRM_VNIC_TPA_QCFG
 
- HWRM_WOL_FILTER_ALLOC
 
- HWRM_WOL_FILTER_FREE
 
- HWRM_WOL_FILTER_QCFG
 
- HWRM_WOL_REASON_QCFG
 
- HWRNG
 
- HWRNG_MINOR
 
- HWRPB_CRB_OFFSET
 
- HWRST_STATUS_ALARM
 
- HWRST_STATUS_AUTODLOADER
 
- HWRST_STATUS_CFTREBOOT
 
- HWRST_STATUS_FACTORYTEST
 
- HWRST_STATUS_FASTBOOT
 
- HWRST_STATUS_IQMODE
 
- HWRST_STATUS_NORMAL
 
- HWRST_STATUS_PANIC
 
- HWRST_STATUS_RECOVERY
 
- HWRST_STATUS_SECURITY
 
- HWRST_STATUS_SLEEP
 
- HWRST_STATUS_SPECIAL
 
- HWRST_STATUS_SPRDISK
 
- HWRST_STATUS_WATCHDOG
 
- HWSEED
 
- HWSEQ_BLND_MASK_SH_LIST
 
- HWSEQ_BLND_REG_LIST
 
- HWSEQ_CZ_REG_LIST
 
- HWSEQ_DCE10_MASK_SH_LIST
 
- HWSEQ_DCE10_REG_LIST
 
- HWSEQ_DCE112_MASK_SH_LIST
 
- HWSEQ_DCE112_REG_LIST
 
- HWSEQ_DCE11_MASK_SH_LIST
 
- HWSEQ_DCE11_REG_LIST_BASE
 
- HWSEQ_DCE120_REG_LIST
 
- HWSEQ_DCE12_MASK_SH_LIST
 
- HWSEQ_DCE8_MASK_SH_LIST
 
- HWSEQ_DCE8_REG_LIST
 
- HWSEQ_DCEF_MASK_SH_LIST
 
- HWSEQ_DCEF_REG_LIST
 
- HWSEQ_DCEF_REG_LIST_DCE8
 
- HWSEQ_DCN1_MASK_SH_LIST
 
- HWSEQ_DCN1_REG_LIST
 
- HWSEQ_DCN21_MASK_SH_LIST
 
- HWSEQ_DCN21_REG_LIST
 
- HWSEQ_DCN2_MASK_SH_LIST
 
- HWSEQ_DCN2_REG_LIST
 
- HWSEQ_DCN_MASK_SH_LIST
 
- HWSEQ_DCN_REG_FIELD_LIST
 
- HWSEQ_DCN_REG_LIST
 
- HWSEQ_GFX9_DCHUB_MASK_SH_LIST
 
- HWSEQ_LVTMA_MASK_SH_LIST
 
- HWSEQ_PHYPLL_MASK_SH_LIST
 
- HWSEQ_PHYPLL_REG_LIST
 
- HWSEQ_PIXEL_RATE_MASK_SH_LIST
 
- HWSEQ_PIXEL_RATE_REG_LIST
 
- HWSEQ_REG_FIELD_LIST
 
- HWSEQ_ST_REG_LIST
 
- HWSEQ_VG20_MASK_SH_LIST
 
- HWSEQ_VG20_REG_LIST
 
- HWSET_MAX_SIZE
 
- HWSET_MAX_SIZE_128
 
- HWSET_MAX_SIZE_256
 
- HWSET_MAX_SIZE_512
 
- HWSET_MAX_SIZE_8723B
 
- HWSET_MAX_SIZE_88E
 
- HWSET_MAX_SIZE_92S
 
- HWSI
 
- HWSIM_ATTR_ADDR_RECEIVER
 
- HWSIM_ATTR_ADDR_TRANSMITTER
 
- HWSIM_ATTR_CHANNELS
 
- HWSIM_ATTR_CIPHER_SUPPORT
 
- HWSIM_ATTR_COOKIE
 
- HWSIM_ATTR_DESTROY_RADIO_ON_CLOSE
 
- HWSIM_ATTR_FLAGS
 
- HWSIM_ATTR_FRAME
 
- HWSIM_ATTR_FREQ
 
- HWSIM_ATTR_IFTYPE_SUPPORT
 
- HWSIM_ATTR_MAX
 
- HWSIM_ATTR_NO_VIF
 
- HWSIM_ATTR_PAD
 
- HWSIM_ATTR_PERM_ADDR
 
- HWSIM_ATTR_RADIO_ID
 
- HWSIM_ATTR_RADIO_NAME
 
- HWSIM_ATTR_REG_CUSTOM_REG
 
- HWSIM_ATTR_REG_HINT_ALPHA2
 
- HWSIM_ATTR_REG_STRICT_REG
 
- HWSIM_ATTR_RX_RATE
 
- HWSIM_ATTR_SIGNAL
 
- HWSIM_ATTR_SUPPORT_P2P_DEVICE
 
- HWSIM_ATTR_TX_INFO
 
- HWSIM_ATTR_TX_INFO_FLAGS
 
- HWSIM_ATTR_UNSPEC
 
- HWSIM_ATTR_USE_CHANCTX
 
- HWSIM_CHANCTX_MAGIC
 
- HWSIM_CMD_CREATE_RADIO
 
- HWSIM_CMD_DEL_RADIO
 
- HWSIM_CMD_DESTROY_RADIO
 
- HWSIM_CMD_FRAME
 
- HWSIM_CMD_GET_RADIO
 
- HWSIM_CMD_MAX
 
- HWSIM_CMD_NEW_RADIO
 
- HWSIM_CMD_REGISTER
 
- HWSIM_CMD_TX_INFO_FRAME
 
- HWSIM_CMD_UNSPEC
 
- HWSIM_COMMON_OPS
 
- HWSIM_DEFAULT_IF_LIMIT
 
- HWSIM_IFTYPE_SUPPORT_MASK
 
- HWSIM_MCGRP_CONFIG
 
- HWSIM_MESH_BIT
 
- HWSIM_REGTEST_ALL
 
- HWSIM_REGTEST_CUSTOM_WORLD
 
- HWSIM_REGTEST_CUSTOM_WORLD_2
 
- HWSIM_REGTEST_DIFF_COUNTRY
 
- HWSIM_REGTEST_DISABLED
 
- HWSIM_REGTEST_DRIVER_REG_ALL
 
- HWSIM_REGTEST_DRIVER_REG_FOLLOW
 
- HWSIM_REGTEST_STRICT_ALL
 
- HWSIM_REGTEST_STRICT_AND_DRIVER_REG
 
- HWSIM_REGTEST_STRICT_FOLLOW
 
- HWSIM_REGTEST_WORLD_ROAM
 
- HWSIM_STA_MAGIC
 
- HWSIM_TM_ATTR_CMD
 
- HWSIM_TM_ATTR_MAX
 
- HWSIM_TM_ATTR_PS
 
- HWSIM_TM_CMD_GET_PS
 
- HWSIM_TM_CMD_SET_PS
 
- HWSIM_TM_CMD_STOP_QUEUES
 
- HWSIM_TM_CMD_WAKE_QUEUES
 
- HWSIM_TX_CTL_NO_ACK
 
- HWSIM_TX_CTL_REQ_TX_STATUS
 
- HWSIM_TX_STAT_ACK
 
- HWSIM_VIF_MAGIC
 
- HWSPINLOCK_MASTERID
 
- HWSPINLOCK_NOTTAKEN
 
- HWSPINLOCK_RECCTRL
 
- HWSPINLOCK_RETRY_DELAY_US
 
- HWSPINLOCK_TIMEOUT
 
- HWSPINLOCK_TOKEN
 
- HWSPINLOCK_UNUSED
 
- HWSPINLOCK_USER_BITS
 
- HWSPNLCK_RETRY_DELAY
 
- HWSPNLCK_TIMEOUT
 
- HWSPR
 
- HWSTAM
 
- HWSTATE
 
- HWSTATE_PAUSE
 
- HWSTATE_RUN
 
- HWSTATE_STARTUP
 
- HWSTATE_STOP
 
- HWSTATUS_CMD
 
- HWSTATUS_CMD_DEFAULT
 
- HWSTATUS_MASK
 
- HWSTATUS_MASK_DEFAULT
 
- HWSTATUS_RBSY_MASK
 
- HWSTATUS_RBSY_VALUE
 
- HWSTATUS_RDSTATUS_MASK
 
- HWSTATUS_RDSTATUS_VALUE
 
- HWS_ADDRESS_MASK
 
- HWS_NEEDS_PHYSICAL
 
- HWS_PGA
 
- HWS_SF
 
- HWS_SF1
 
- HWS_START_ADDRESS_SHIFT
 
- HWTHR
 
- HWTRAP_XTAL_20MHZ
 
- HWTRAP_XTAL_25MHZ
 
- HWTRAP_XTAL_40MHZ
 
- HWTRAP_XTAL_MASK
 
- HWTRGEN_ENABLE
 
- HWTRGMASK_ENABLE
 
- HWTRIGEN_PER_ENABLE
 
- HWTSTAMP_FILTER_ALL
 
- HWTSTAMP_FILTER_NONE
 
- HWTSTAMP_FILTER_NTP_ALL
 
- HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
 
- HWTSTAMP_FILTER_PTP_V1_L4_EVENT
 
- HWTSTAMP_FILTER_PTP_V1_L4_SYNC
 
- HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
 
- HWTSTAMP_FILTER_PTP_V2_EVENT
 
- HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
 
- HWTSTAMP_FILTER_PTP_V2_L2_EVENT
 
- HWTSTAMP_FILTER_PTP_V2_L2_SYNC
 
- HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
 
- HWTSTAMP_FILTER_PTP_V2_L4_EVENT
 
- HWTSTAMP_FILTER_PTP_V2_L4_SYNC
 
- HWTSTAMP_FILTER_PTP_V2_SYNC
 
- HWTSTAMP_FILTER_SOME
 
- HWTSTAMP_TX_OFF
 
- HWTSTAMP_TX_ON
 
- HWTSTAMP_TX_ONESTEP_SYNC
 
- HWTYPE_ANY_ID
 
- HWT_MAX
 
- HWUART
 
- HWVER_10200
 
- HWVER_10300
 
- HWVER_130
 
- HWVER_131
 
- HWVER_20101
 
- HWVID
 
- HWV_CONFB
 
- HWV_IRQ
 
- HWXMIT_ENTRY
 
- HW_ACCESS_ELP_CTRL_REG
 
- HW_ACCESS_ELP_CTRL_REG_ADDR
 
- HW_ACCESS_MEMORY_MAX_RANGE
 
- HW_ACCESS_PART0_SIZE_ADDR
 
- HW_ACCESS_PART0_START_ADDR
 
- HW_ACCESS_PART1_SIZE_ADDR
 
- HW_ACCESS_PART1_START_ADDR
 
- HW_ACCESS_PRAM_MAX_RANGE
 
- HW_ACCESS_REGISTER_SIZE
 
- HW_ACCESS_WSPI_FIXED_BUSY_LEN
 
- HW_ACCESS_WSPI_INIT_CMD_MASK
 
- HW_ACTIVATE_IND
 
- HW_ACTIVATE_REQ
 
- HW_ADCANACLKDIV
 
- HW_ADDR
 
- HW_ADDR_LEN
 
- HW_AHBCLKCTRL0
 
- HW_AHBCLKCTRL1
 
- HW_ALDOM
 
- HW_ALDOW
 
- HW_ALDOY
 
- HW_ALGO_LEVEL
 
- HW_ALGO_TOGGLE
 
- HW_ALHOUR
 
- HW_ALMIN
 
- HW_ALMON
 
- HW_ALSEC
 
- HW_ALYEAR
 
- HW_AMR
 
- HW_ANA_DIGI_OC
 
- HW_ANTDIV
 
- HW_APBHX_CHANNEL_CTRL
 
- HW_APBHX_CHn_BAR
 
- HW_APBHX_CHn_NXTCMDAR
 
- HW_APBHX_CHn_SEMA
 
- HW_APBHX_CTRL0
 
- HW_APBHX_CTRL1
 
- HW_APBHX_CTRL2
 
- HW_APBX_CHn_DEBUG1
 
- HW_ASSISTED_I2C_STATUS_FAILURE
 
- HW_ASSISTED_I2C_STATUS_SUCCESS
 
- HW_ATL_A0_ERR_INT
 
- HW_ATL_A0_FW_SEMA_RAM
 
- HW_ATL_A0_FW_VER_EXPECTED
 
- HW_ATL_A0_H
 
- HW_ATL_A0_INTERNAL_H
 
- HW_ATL_A0_INT_MASK
 
- HW_ATL_A0_MAC
 
- HW_ATL_A0_MAC_MAX
 
- HW_ATL_A0_MAC_MIN
 
- HW_ATL_A0_MAX_RXD
 
- HW_ATL_A0_MAX_TXD
 
- HW_ATL_A0_MIN_RXD
 
- HW_ATL_A0_MIN_TXD
 
- HW_ATL_A0_MPI_CONTROL_ADR
 
- HW_ATL_A0_MPI_SPEED_MSK
 
- HW_ATL_A0_MPI_SPEED_SHIFT
 
- HW_ATL_A0_MPI_STATE_ADR
 
- HW_ATL_A0_MTU_JUMBO
 
- HW_ATL_A0_RINGS_MAX
 
- HW_ATL_A0_RSS_MAX
 
- HW_ATL_A0_RSS_REDIRECTION_BITS
 
- HW_ATL_A0_RSS_REDIRECTION_MAX
 
- HW_ATL_A0_RXBUF_MAX
 
- HW_ATL_A0_RXD_DD
 
- HW_ATL_A0_RXD_NCEA0
 
- HW_ATL_A0_RXD_SIZE
 
- HW_ATL_A0_RXD_WB_STAT2_EOP
 
- HW_ATL_A0_RX_RINGS
 
- HW_ATL_A0_TC_MAX
 
- HW_ATL_A0_TXBUF_MAX
 
- HW_ATL_A0_TXD_CTL2_CTX_EN
 
- HW_ATL_A0_TXD_CTL2_CTX_IDX
 
- HW_ATL_A0_TXD_CTL2_LEN
 
- HW_ATL_A0_TXD_CTL_BLEN
 
- HW_ATL_A0_TXD_CTL_CMD_FCS
 
- HW_ATL_A0_TXD_CTL_CMD_IPCSO
 
- HW_ATL_A0_TXD_CTL_CMD_IPV6
 
- HW_ATL_A0_TXD_CTL_CMD_LSO
 
- HW_ATL_A0_TXD_CTL_CMD_TCP
 
- HW_ATL_A0_TXD_CTL_CMD_TUCSO
 
- HW_ATL_A0_TXD_CTL_CMD_VLAN
 
- HW_ATL_A0_TXD_CTL_CMD_VXLAN
 
- HW_ATL_A0_TXD_CTL_CMD_WB
 
- HW_ATL_A0_TXD_CTL_CMD_X
 
- HW_ATL_A0_TXD_CTL_DD
 
- HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC
 
- HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD
 
- HW_ATL_A0_TXD_CTL_EOP
 
- HW_ATL_A0_TXD_SIZE
 
- HW_ATL_A0_TX_RINGS
 
- HW_ATL_A0_UCP_0X370_REG
 
- HW_ATL_B0_CHIP_REVISION_B0
 
- HW_ATL_B0_CHIP_REVISION_UNKNOWN
 
- HW_ATL_B0_ERR_INT
 
- HW_ATL_B0_FLUSH
 
- HW_ATL_B0_FW_SEMA_RAM
 
- HW_ATL_B0_FW_VER_EXPECTED
 
- HW_ATL_B0_H
 
- HW_ATL_B0_INTERNAL_H
 
- HW_ATL_B0_INT_MASK
 
- HW_ATL_B0_LRO_RXD_MAX
 
- HW_ATL_B0_MAC
 
- HW_ATL_B0_MAC_MAX
 
- HW_ATL_B0_MAC_MIN
 
- HW_ATL_B0_MAX_RXD
 
- HW_ATL_B0_MAX_TXD
 
- HW_ATL_B0_MCAST_FILTERS_MAX
 
- HW_ATL_B0_MIN_RXD
 
- HW_ATL_B0_MIN_TXD
 
- HW_ATL_B0_MPI_CONTROL_ADR
 
- HW_ATL_B0_MPI_SPEED_MSK
 
- HW_ATL_B0_MPI_SPEED_SHIFT
 
- HW_ATL_B0_MPI_STATE_ADR
 
- HW_ATL_B0_MTU
 
- HW_ATL_B0_MTU_JUMBO
 
- HW_ATL_B0_RINGS_MAX
 
- HW_ATL_B0_RSS_HASHKEY_BITS
 
- HW_ATL_B0_RSS_MAX
 
- HW_ATL_B0_RSS_REDIRECTION_BITS
 
- HW_ATL_B0_RSS_REDIRECTION_MAX
 
- HW_ATL_B0_RS_SLIP_ENABLED
 
- HW_ATL_B0_RXBUF_MAX
 
- HW_ATL_B0_RXD_DD
 
- HW_ATL_B0_RXD_NCEA0
 
- HW_ATL_B0_RXD_SIZE
 
- HW_ATL_B0_RXD_WB_PKTTYPE_VLAN
 
- HW_ATL_B0_RXD_WB_PKTTYPE_VLAN_DOUBLE
 
- HW_ATL_B0_RXD_WB_STAT2_DD
 
- HW_ATL_B0_RXD_WB_STAT2_EOP
 
- HW_ATL_B0_RXD_WB_STAT2_IP4ERR
 
- HW_ATL_B0_RXD_WB_STAT2_MACERR
 
- HW_ATL_B0_RXD_WB_STAT2_RSCCNT
 
- HW_ATL_B0_RXD_WB_STAT2_RXESTAT
 
- HW_ATL_B0_RXD_WB_STAT2_RXSTAT
 
- HW_ATL_B0_RXD_WB_STAT2_TCPUPDERR
 
- HW_ATL_B0_RXD_WB_STAT_HDRLEN
 
- HW_ATL_B0_RXD_WB_STAT_HDRLEN_SHIFT
 
- HW_ATL_B0_RXD_WB_STAT_PKTTYPE
 
- HW_ATL_B0_RXD_WB_STAT_PKTTYPE_SHIFT
 
- HW_ATL_B0_RXD_WB_STAT_RSSTYPE
 
- HW_ATL_B0_RXD_WB_STAT_RSSTYPE_SHIFT
 
- HW_ATL_B0_RXD_WB_STAT_RXCTRL
 
- HW_ATL_B0_RXD_WB_STAT_RXCTRL_SHIFT
 
- HW_ATL_B0_RXD_WB_STAT_SPLHDR
 
- HW_ATL_B0_RX_RINGS
 
- HW_ATL_B0_TCRSS_4_8
 
- HW_ATL_B0_TC_MAX
 
- HW_ATL_B0_TXBUF_MAX
 
- HW_ATL_B0_TXC_CTL_CMD
 
- HW_ATL_B0_TXC_CTL_CTX_ID
 
- HW_ATL_B0_TXC_CTL_DESC_TYPE
 
- HW_ATL_B0_TXC_CTL_L2LEN
 
- HW_ATL_B0_TXC_CTL_L3LEN
 
- HW_ATL_B0_TXC_CTL_VLAN
 
- HW_ATL_B0_TXC_LEN2_L3LEN
 
- HW_ATL_B0_TXC_LEN2_L4LEN
 
- HW_ATL_B0_TXC_LEN2_MSSLEN
 
- HW_ATL_B0_TXC_LEN_OUTLEN
 
- HW_ATL_B0_TXC_LEN_TUNLEN
 
- HW_ATL_B0_TXD_CTL2_CTX_EN
 
- HW_ATL_B0_TXD_CTL2_CTX_IDX
 
- HW_ATL_B0_TXD_CTL2_LEN
 
- HW_ATL_B0_TXD_CTL_BLEN
 
- HW_ATL_B0_TXD_CTL_CMD_FCS
 
- HW_ATL_B0_TXD_CTL_CMD_IPCSO
 
- HW_ATL_B0_TXD_CTL_CMD_IPV6
 
- HW_ATL_B0_TXD_CTL_CMD_LSO
 
- HW_ATL_B0_TXD_CTL_CMD_TCP
 
- HW_ATL_B0_TXD_CTL_CMD_TUCSO
 
- HW_ATL_B0_TXD_CTL_CMD_VLAN
 
- HW_ATL_B0_TXD_CTL_CMD_VXLAN
 
- HW_ATL_B0_TXD_CTL_CMD_WB
 
- HW_ATL_B0_TXD_CTL_CMD_X
 
- HW_ATL_B0_TXD_CTL_DD
 
- HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC
 
- HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD
 
- HW_ATL_B0_TXD_CTL_EOP
 
- HW_ATL_B0_TXD_SIZE
 
- HW_ATL_B0_TX_RINGS
 
- HW_ATL_B0_UCAST_FILTERS_MAX
 
- HW_ATL_B0_UCP_0X370_REG
 
- HW_ATL_FLUSH
 
- HW_ATL_FW2X_CAP_ASYM_PAUSE
 
- HW_ATL_FW2X_CAP_EEE_10G_MASK
 
- HW_ATL_FW2X_CAP_EEE_1G_MASK
 
- HW_ATL_FW2X_CAP_EEE_2G5_MASK
 
- HW_ATL_FW2X_CAP_EEE_5G_MASK
 
- HW_ATL_FW2X_CAP_PAUSE
 
- HW_ATL_FW2X_CAP_SLEEP_PROXY
 
- HW_ATL_FW2X_CAP_WOL
 
- HW_ATL_FW2X_CTRL_ASYMMETRIC_PAUSE
 
- HW_ATL_FW2X_CTRL_FORCE_RECONNECT
 
- HW_ATL_FW2X_CTRL_LINK_DROP
 
- HW_ATL_FW2X_CTRL_PAUSE
 
- HW_ATL_FW2X_CTRL_SLEEP_PROXY
 
- HW_ATL_FW2X_CTRL_TEMPERATURE
 
- HW_ATL_FW2X_CTRL_WOL
 
- HW_ATL_FW2X_MPI_CONTROL2_ADDR
 
- HW_ATL_FW2X_MPI_CONTROL_ADDR
 
- HW_ATL_FW2X_MPI_EFUSE_ADDR
 
- HW_ATL_FW2X_MPI_MBOX_ADDR
 
- HW_ATL_FW2X_MPI_RPC_ADDR
 
- HW_ATL_FW2X_MPI_STATE2_ADDR
 
- HW_ATL_FW2X_MPI_STATE_ADDR
 
- HW_ATL_FW_SM_RAM
 
- HW_ATL_FW_VER_1X
 
- HW_ATL_FW_VER_2X
 
- HW_ATL_FW_VER_3X
 
- HW_ATL_GEN_INTR_MAP_ADR
 
- HW_ATL_GEN_INTR_STAT_ADR
 
- HW_ATL_GET_REG_LOCATION_FL3L4
 
- HW_ATL_GLB_CPU_SCRATCH_SCP_ADR
 
- HW_ATL_GLB_CPU_SEM_ADR
 
- HW_ATL_GLB_MIF_ID_ADR
 
- HW_ATL_GLB_REG_RES_DIS_ADR
 
- HW_ATL_GLB_REG_RES_DIS_DEFAULT
 
- HW_ATL_GLB_REG_RES_DIS_MSK
 
- HW_ATL_GLB_REG_RES_DIS_MSKN
 
- HW_ATL_GLB_REG_RES_DIS_SHIFT
 
- HW_ATL_GLB_REG_RES_DIS_WIDTH
 
- HW_ATL_GLB_SOFT_RES_ADR
 
- HW_ATL_GLB_SOFT_RES_DEFAULT
 
- HW_ATL_GLB_SOFT_RES_MSK
 
- HW_ATL_GLB_SOFT_RES_MSKN
 
- HW_ATL_GLB_SOFT_RES_SHIFT
 
- HW_ATL_GLB_SOFT_RES_WIDTH
 
- HW_ATL_INTR_GLB_CTL_ADR
 
- HW_ATL_INTR_MODER_MAX
 
- HW_ATL_INTR_MODER_MIN
 
- HW_ATL_INTR_THR_ADR
 
- HW_ATL_ITR_IAMRLSW_ADR
 
- HW_ATL_ITR_IMCRLSW_ADR
 
- HW_ATL_ITR_IMSRLSW_ADR
 
- HW_ATL_ITR_ISCRLSW_ADR
 
- HW_ATL_ITR_ISRLSW_ADR
 
- HW_ATL_ITR_REG_RES_DSBL_ADR
 
- HW_ATL_ITR_REG_RES_DSBL_MSK
 
- HW_ATL_ITR_REG_RES_DSBL_SHIFT
 
- HW_ATL_ITR_RES_ADR
 
- HW_ATL_ITR_RES_MSK
 
- HW_ATL_ITR_RES_SHIFT
 
- HW_ATL_ITR_RSC_DELAY_ADR
 
- HW_ATL_ITR_RSC_DELAY_MSK
 
- HW_ATL_ITR_RSC_DELAY_SHIFT
 
- HW_ATL_ITR_RSC_DELAY_WIDTH
 
- HW_ATL_ITR_RSC_EN_ADR
 
- HW_ATL_LLH_H
 
- HW_ATL_LLH_INTERNAL_H
 
- HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR
 
- HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR
 
- HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR
 
- HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR
 
- HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR
 
- HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR
 
- HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR
 
- HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR
 
- HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR
 
- HW_ATL_MAC_PHY_CONTROL
 
- HW_ATL_MAC_PHY_MPI_RESET_BIT
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT
 
- HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH
 
- HW_ATL_MIF_ADDR
 
- HW_ATL_MIF_CMD
 
- HW_ATL_MIF_VAL
 
- HW_ATL_MPI_BOOT_EXIT_CODE
 
- HW_ATL_MPI_CONTROL_ADR
 
- HW_ATL_MPI_DAISY_CHAIN_STATUS
 
- HW_ATL_MPI_DIRTY_WAKE_MSK
 
- HW_ATL_MPI_FW_VERSION
 
- HW_ATL_MPI_RPC_ADDR
 
- HW_ATL_MPI_SPEED_MSK
 
- HW_ATL_MPI_SPEED_SHIFT
 
- HW_ATL_MPI_STATE_ADR
 
- HW_ATL_MPI_STATE_MSK
 
- HW_ATL_MPI_STATE_SHIFT
 
- HW_ATL_MSM_REG_ACCESS_BUSY_ADR
 
- HW_ATL_MSM_REG_ACCESS_BUSY_MSK
 
- HW_ATL_MSM_REG_ACCESS_BUSY_MSKN
 
- HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT
 
- HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH
 
- HW_ATL_MSM_REG_ADDR_ADR
 
- HW_ATL_MSM_REG_ADDR_DEFAULT
 
- HW_ATL_MSM_REG_ADDR_MSK
 
- HW_ATL_MSM_REG_ADDR_MSKN
 
- HW_ATL_MSM_REG_ADDR_SHIFT
 
- HW_ATL_MSM_REG_ADDR_WIDTH
 
- HW_ATL_MSM_REG_RD_DATA_ADR
 
- HW_ATL_MSM_REG_RD_DATA_MSK
 
- HW_ATL_MSM_REG_RD_DATA_MSKN
 
- HW_ATL_MSM_REG_RD_DATA_SHIFT
 
- HW_ATL_MSM_REG_RD_DATA_WIDTH
 
- HW_ATL_MSM_REG_RD_STROBE_ADR
 
- HW_ATL_MSM_REG_RD_STROBE_DEFAULT
 
- HW_ATL_MSM_REG_RD_STROBE_MSK
 
- HW_ATL_MSM_REG_RD_STROBE_MSKN
 
- HW_ATL_MSM_REG_RD_STROBE_SHIFT
 
- HW_ATL_MSM_REG_RD_STROBE_WIDTH
 
- HW_ATL_MSM_REG_WR_DATA_ADR
 
- HW_ATL_MSM_REG_WR_DATA_DEFAULT
 
- HW_ATL_MSM_REG_WR_DATA_MSK
 
- HW_ATL_MSM_REG_WR_DATA_MSKN
 
- HW_ATL_MSM_REG_WR_DATA_SHIFT
 
- HW_ATL_MSM_REG_WR_DATA_WIDTH
 
- HW_ATL_MSM_REG_WR_STROBE_ADR
 
- HW_ATL_MSM_REG_WR_STROBE_DEFAULT
 
- HW_ATL_MSM_REG_WR_STROBE_MSK
 
- HW_ATL_MSM_REG_WR_STROBE_MSKN
 
- HW_ATL_MSM_REG_WR_STROBE_SHIFT
 
- HW_ATL_MSM_REG_WR_STROBE_WIDTH
 
- HW_ATL_NIC_NAME
 
- HW_ATL_PCI_REG_CONTROL6_ADR
 
- HW_ATL_PCI_REG_RES_DSBL_ADR
 
- HW_ATL_PCI_REG_RES_DSBL_DEFAULT
 
- HW_ATL_PCI_REG_RES_DSBL_MSK
 
- HW_ATL_PCI_REG_RES_DSBL_MSKN
 
- HW_ATL_PCI_REG_RES_DSBL_SHIFT
 
- HW_ATL_PCI_REG_RES_DSBL_WIDTH
 
- HW_ATL_RDM_DCADCPUID_ADR
 
- HW_ATL_RDM_DCADCPUID_MSK
 
- HW_ATL_RDM_DCADCPUID_SHIFT
 
- HW_ATL_RDM_DCADDESC_EN_ADR
 
- HW_ATL_RDM_DCADDESC_EN_DEFAULT
 
- HW_ATL_RDM_DCADDESC_EN_MSK
 
- HW_ATL_RDM_DCADDESC_EN_MSKN
 
- HW_ATL_RDM_DCADDESC_EN_SHIFT
 
- HW_ATL_RDM_DCADDESC_EN_WIDTH
 
- HW_ATL_RDM_DCADHDR_EN_ADR
 
- HW_ATL_RDM_DCADHDR_EN_DEFAULT
 
- HW_ATL_RDM_DCADHDR_EN_MSK
 
- HW_ATL_RDM_DCADHDR_EN_MSKN
 
- HW_ATL_RDM_DCADHDR_EN_SHIFT
 
- HW_ATL_RDM_DCADHDR_EN_WIDTH
 
- HW_ATL_RDM_DCADPAY_EN_ADR
 
- HW_ATL_RDM_DCADPAY_EN_DEFAULT
 
- HW_ATL_RDM_DCADPAY_EN_MSK
 
- HW_ATL_RDM_DCADPAY_EN_MSKN
 
- HW_ATL_RDM_DCADPAY_EN_SHIFT
 
- HW_ATL_RDM_DCADPAY_EN_WIDTH
 
- HW_ATL_RDM_DCA_EN_ADR
 
- HW_ATL_RDM_DCA_EN_DEFAULT
 
- HW_ATL_RDM_DCA_EN_MSK
 
- HW_ATL_RDM_DCA_EN_MSKN
 
- HW_ATL_RDM_DCA_EN_SHIFT
 
- HW_ATL_RDM_DCA_EN_WIDTH
 
- HW_ATL_RDM_DCA_MODE_ADR
 
- HW_ATL_RDM_DCA_MODE_DEFAULT
 
- HW_ATL_RDM_DCA_MODE_MSK
 
- HW_ATL_RDM_DCA_MODE_MSKN
 
- HW_ATL_RDM_DCA_MODE_SHIFT
 
- HW_ATL_RDM_DCA_MODE_WIDTH
 
- HW_ATL_RDM_DESCDDATA_SIZE_ADR
 
- HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT
 
- HW_ATL_RDM_DESCDDATA_SIZE_MSK
 
- HW_ATL_RDM_DESCDDATA_SIZE_MSKN
 
- HW_ATL_RDM_DESCDDATA_SIZE_SHIFT
 
- HW_ATL_RDM_DESCDDATA_SIZE_WIDTH
 
- HW_ATL_RDM_DESCDEN_ADR
 
- HW_ATL_RDM_DESCDEN_DEFAULT
 
- HW_ATL_RDM_DESCDEN_MSK
 
- HW_ATL_RDM_DESCDEN_MSKN
 
- HW_ATL_RDM_DESCDEN_SHIFT
 
- HW_ATL_RDM_DESCDEN_WIDTH
 
- HW_ATL_RDM_DESCDHDR_SIZE_ADR
 
- HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT
 
- HW_ATL_RDM_DESCDHDR_SIZE_MSK
 
- HW_ATL_RDM_DESCDHDR_SIZE_MSKN
 
- HW_ATL_RDM_DESCDHDR_SIZE_SHIFT
 
- HW_ATL_RDM_DESCDHDR_SIZE_WIDTH
 
- HW_ATL_RDM_DESCDHDR_SPLIT_ADR
 
- HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT
 
- HW_ATL_RDM_DESCDHDR_SPLIT_MSK
 
- HW_ATL_RDM_DESCDHDR_SPLIT_MSKN
 
- HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT
 
- HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH
 
- HW_ATL_RDM_DESCDHD_ADR
 
- HW_ATL_RDM_DESCDHD_MSK
 
- HW_ATL_RDM_DESCDHD_MSKN
 
- HW_ATL_RDM_DESCDHD_SHIFT
 
- HW_ATL_RDM_DESCDHD_WIDTH
 
- HW_ATL_RDM_DESCDLEN_ADR
 
- HW_ATL_RDM_DESCDLEN_DEFAULT
 
- HW_ATL_RDM_DESCDLEN_MSK
 
- HW_ATL_RDM_DESCDLEN_MSKN
 
- HW_ATL_RDM_DESCDLEN_SHIFT
 
- HW_ATL_RDM_DESCDLEN_WIDTH
 
- HW_ATL_RDM_DESCDRESET_ADR
 
- HW_ATL_RDM_DESCDRESET_DEFAULT
 
- HW_ATL_RDM_DESCDRESET_MSK
 
- HW_ATL_RDM_DESCDRESET_MSKN
 
- HW_ATL_RDM_DESCDRESET_SHIFT
 
- HW_ATL_RDM_DESCDRESET_WIDTH
 
- HW_ATL_RDM_INT_DESC_WRB_EN_ADR
 
- HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT
 
- HW_ATL_RDM_INT_DESC_WRB_EN_MSK
 
- HW_ATL_RDM_INT_DESC_WRB_EN_MSKN
 
- HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT
 
- HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH
 
- HW_ATL_RDM_INT_RIM_EN_ADR
 
- HW_ATL_RDM_INT_RIM_EN_DEFAULT
 
- HW_ATL_RDM_INT_RIM_EN_MSK
 
- HW_ATL_RDM_INT_RIM_EN_MSKN
 
- HW_ATL_RDM_INT_RIM_EN_SHIFT
 
- HW_ATL_RDM_INT_RIM_EN_WIDTH
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT
 
- HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH
 
- HW_ATL_RPB_DMA_SYS_LBK_ADR
 
- HW_ATL_RPB_DMA_SYS_LBK_DEFAULT
 
- HW_ATL_RPB_DMA_SYS_LBK_MSK
 
- HW_ATL_RPB_DMA_SYS_LBK_MSKN
 
- HW_ATL_RPB_DMA_SYS_LBK_SHIFT
 
- HW_ATL_RPB_DMA_SYS_LBK_WIDTH
 
- HW_ATL_RPB_RPF_RX_TC_MODE_ADR
 
- HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT
 
- HW_ATL_RPB_RPF_RX_TC_MODE_MSK
 
- HW_ATL_RPB_RPF_RX_TC_MODE_MSKN
 
- HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT
 
- HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH
 
- HW_ATL_RPB_RXBBUF_SIZE_ADR
 
- HW_ATL_RPB_RXBBUF_SIZE_DEFAULT
 
- HW_ATL_RPB_RXBBUF_SIZE_MSK
 
- HW_ATL_RPB_RXBBUF_SIZE_MSKN
 
- HW_ATL_RPB_RXBBUF_SIZE_SHIFT
 
- HW_ATL_RPB_RXBBUF_SIZE_WIDTH
 
- HW_ATL_RPB_RXBHI_THRESH_ADR
 
- HW_ATL_RPB_RXBHI_THRESH_DEFAULT
 
- HW_ATL_RPB_RXBHI_THRESH_MSK
 
- HW_ATL_RPB_RXBHI_THRESH_MSKN
 
- HW_ATL_RPB_RXBHI_THRESH_SHIFT
 
- HW_ATL_RPB_RXBHI_THRESH_WIDTH
 
- HW_ATL_RPB_RXBLO_THRESH_ADR
 
- HW_ATL_RPB_RXBLO_THRESH_DEFAULT
 
- HW_ATL_RPB_RXBLO_THRESH_MSK
 
- HW_ATL_RPB_RXBLO_THRESH_MSKN
 
- HW_ATL_RPB_RXBLO_THRESH_SHIFT
 
- HW_ATL_RPB_RXBLO_THRESH_WIDTH
 
- HW_ATL_RPB_RXBXOFF_EN_ADR
 
- HW_ATL_RPB_RXBXOFF_EN_DEFAULT
 
- HW_ATL_RPB_RXBXOFF_EN_MSK
 
- HW_ATL_RPB_RXBXOFF_EN_MSKN
 
- HW_ATL_RPB_RXBXOFF_EN_SHIFT
 
- HW_ATL_RPB_RXBXOFF_EN_WIDTH
 
- HW_ATL_RPB_RX_BUF_EN_ADR
 
- HW_ATL_RPB_RX_BUF_EN_DEFAULT
 
- HW_ATL_RPB_RX_BUF_EN_MSK
 
- HW_ATL_RPB_RX_BUF_EN_MSKN
 
- HW_ATL_RPB_RX_BUF_EN_SHIFT
 
- HW_ATL_RPB_RX_BUF_EN_WIDTH
 
- HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR
 
- HW_ATL_RPB_RX_FC_MODE_ADR
 
- HW_ATL_RPB_RX_FC_MODE_DEFAULT
 
- HW_ATL_RPB_RX_FC_MODE_MSK
 
- HW_ATL_RPB_RX_FC_MODE_MSKN
 
- HW_ATL_RPB_RX_FC_MODE_SHIFT
 
- HW_ATL_RPB_RX_FC_MODE_WIDTH
 
- HW_ATL_RPC_CONTROL_ADR
 
- HW_ATL_RPC_STATE_ADR
 
- HW_ATL_RPFL2BC_ACT_ADR
 
- HW_ATL_RPFL2BC_ACT_DEFAULT
 
- HW_ATL_RPFL2BC_ACT_MSK
 
- HW_ATL_RPFL2BC_ACT_MSKN
 
- HW_ATL_RPFL2BC_ACT_SHIFT
 
- HW_ATL_RPFL2BC_ACT_WIDTH
 
- HW_ATL_RPFL2BC_EN_ADR
 
- HW_ATL_RPFL2BC_EN_DEFAULT
 
- HW_ATL_RPFL2BC_EN_MSK
 
- HW_ATL_RPFL2BC_EN_MSKN
 
- HW_ATL_RPFL2BC_EN_SHIFT
 
- HW_ATL_RPFL2BC_EN_WIDTH
 
- HW_ATL_RPFL2BC_THRESH_ADR
 
- HW_ATL_RPFL2BC_THRESH_DEFAULT
 
- HW_ATL_RPFL2BC_THRESH_MSK
 
- HW_ATL_RPFL2BC_THRESH_MSKN
 
- HW_ATL_RPFL2BC_THRESH_SHIFT
 
- HW_ATL_RPFL2BC_THRESH_WIDTH
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_ADR
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_MSK
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT
 
- HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH
 
- HW_ATL_RPFL2MC_ENF_ADR
 
- HW_ATL_RPFL2MC_ENF_DEFAULT
 
- HW_ATL_RPFL2MC_ENF_MSK
 
- HW_ATL_RPFL2MC_ENF_MSKN
 
- HW_ATL_RPFL2MC_ENF_SHIFT
 
- HW_ATL_RPFL2MC_ENF_WIDTH
 
- HW_ATL_RPFL2PROMIS_MODE_ADR
 
- HW_ATL_RPFL2PROMIS_MODE_DEFAULT
 
- HW_ATL_RPFL2PROMIS_MODE_MSK
 
- HW_ATL_RPFL2PROMIS_MODE_MSKN
 
- HW_ATL_RPFL2PROMIS_MODE_SHIFT
 
- HW_ATL_RPFL2PROMIS_MODE_WIDTH
 
- HW_ATL_RPFL2UC_ACTF_ADR
 
- HW_ATL_RPFL2UC_ACTF_DEFAULT
 
- HW_ATL_RPFL2UC_ACTF_MSK
 
- HW_ATL_RPFL2UC_ACTF_MSKN
 
- HW_ATL_RPFL2UC_ACTF_SHIFT
 
- HW_ATL_RPFL2UC_ACTF_WIDTH
 
- HW_ATL_RPFL2UC_DAFLSW_ADR
 
- HW_ATL_RPFL2UC_DAFMSW_ADR
 
- HW_ATL_RPFL2UC_DAFMSW_MSK
 
- HW_ATL_RPFL2UC_DAFMSW_SHIFT
 
- HW_ATL_RPFL2UC_ENF_ADR
 
- HW_ATL_RPFL2UC_ENF_DEFAULT
 
- HW_ATL_RPFL2UC_ENF_MSK
 
- HW_ATL_RPFL2UC_ENF_MSKN
 
- HW_ATL_RPFL2UC_ENF_SHIFT
 
- HW_ATL_RPFL2UC_ENF_WIDTH
 
- HW_ATL_RPF_ET_ACTF_ADR
 
- HW_ATL_RPF_ET_ACTF_DEFAULT
 
- HW_ATL_RPF_ET_ACTF_MSK
 
- HW_ATL_RPF_ET_ACTF_MSKN
 
- HW_ATL_RPF_ET_ACTF_SHIFT
 
- HW_ATL_RPF_ET_ACTF_WIDTH
 
- HW_ATL_RPF_ET_ENF_ADR
 
- HW_ATL_RPF_ET_ENF_DEFAULT
 
- HW_ATL_RPF_ET_ENF_MSK
 
- HW_ATL_RPF_ET_ENF_MSKN
 
- HW_ATL_RPF_ET_ENF_SHIFT
 
- HW_ATL_RPF_ET_ENF_WIDTH
 
- HW_ATL_RPF_ET_MNG_RXQF_ADR
 
- HW_ATL_RPF_ET_MNG_RXQF_DEFAULT
 
- HW_ATL_RPF_ET_MNG_RXQF_MSK
 
- HW_ATL_RPF_ET_MNG_RXQF_MSKN
 
- HW_ATL_RPF_ET_MNG_RXQF_SHIFT
 
- HW_ATL_RPF_ET_MNG_RXQF_WIDTH
 
- HW_ATL_RPF_ET_RXQFEN_ADR
 
- HW_ATL_RPF_ET_RXQFEN_DEFAULT
 
- HW_ATL_RPF_ET_RXQFEN_MSK
 
- HW_ATL_RPF_ET_RXQFEN_MSKN
 
- HW_ATL_RPF_ET_RXQFEN_SHIFT
 
- HW_ATL_RPF_ET_RXQFEN_WIDTH
 
- HW_ATL_RPF_ET_RXQF_ADR
 
- HW_ATL_RPF_ET_RXQF_DEFAULT
 
- HW_ATL_RPF_ET_RXQF_MSK
 
- HW_ATL_RPF_ET_RXQF_MSKN
 
- HW_ATL_RPF_ET_RXQF_SHIFT
 
- HW_ATL_RPF_ET_RXQF_WIDTH
 
- HW_ATL_RPF_ET_UPFEN_ADR
 
- HW_ATL_RPF_ET_UPFEN_DEFAULT
 
- HW_ATL_RPF_ET_UPFEN_MSK
 
- HW_ATL_RPF_ET_UPFEN_MSKN
 
- HW_ATL_RPF_ET_UPFEN_SHIFT
 
- HW_ATL_RPF_ET_UPFEN_WIDTH
 
- HW_ATL_RPF_ET_UPF_ADR
 
- HW_ATL_RPF_ET_UPF_DEFAULT
 
- HW_ATL_RPF_ET_UPF_MSK
 
- HW_ATL_RPF_ET_UPF_MSKN
 
- HW_ATL_RPF_ET_UPF_SHIFT
 
- HW_ATL_RPF_ET_UPF_WIDTH
 
- HW_ATL_RPF_ET_VALF_ADR
 
- HW_ATL_RPF_ET_VALF_DEFAULT
 
- HW_ATL_RPF_ET_VALF_MSK
 
- HW_ATL_RPF_ET_VALF_MSKN
 
- HW_ATL_RPF_ET_VALF_SHIFT
 
- HW_ATL_RPF_ET_VALF_WIDTH
 
- HW_ATL_RPF_L3_DSTA_ADR
 
- HW_ATL_RPF_L3_DSTA_DEFAULT
 
- HW_ATL_RPF_L3_DSTA_MSK
 
- HW_ATL_RPF_L3_DSTA_MSKN
 
- HW_ATL_RPF_L3_DSTA_SHIFT
 
- HW_ATL_RPF_L3_DSTA_WIDTH
 
- HW_ATL_RPF_L3_REG_CTRL_ADR
 
- HW_ATL_RPF_L3_SRCA_ADR
 
- HW_ATL_RPF_L3_SRCA_DEFAULT
 
- HW_ATL_RPF_L3_SRCA_MSK
 
- HW_ATL_RPF_L3_SRCA_MSKN
 
- HW_ATL_RPF_L3_SRCA_SHIFT
 
- HW_ATL_RPF_L3_SRCA_WIDTH
 
- HW_ATL_RPF_L4_DPD_ADR
 
- HW_ATL_RPF_L4_DPD_DEFAULT
 
- HW_ATL_RPF_L4_DPD_MSK
 
- HW_ATL_RPF_L4_DPD_MSKN
 
- HW_ATL_RPF_L4_DPD_SHIFT
 
- HW_ATL_RPF_L4_DPD_WIDTH
 
- HW_ATL_RPF_L4_SPD_ADR
 
- HW_ATL_RPF_L4_SPD_DEFAULT
 
- HW_ATL_RPF_L4_SPD_MSK
 
- HW_ATL_RPF_L4_SPD_MSKN
 
- HW_ATL_RPF_L4_SPD_SHIFT
 
- HW_ATL_RPF_L4_SPD_WIDTH
 
- HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT
 
- HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH
 
- HW_ATL_RPF_RSS_KEY_ADDR_ADR
 
- HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT
 
- HW_ATL_RPF_RSS_KEY_ADDR_MSK
 
- HW_ATL_RPF_RSS_KEY_ADDR_MSKN
 
- HW_ATL_RPF_RSS_KEY_ADDR_SHIFT
 
- HW_ATL_RPF_RSS_KEY_ADDR_WIDTH
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_ADR
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_MSK
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT
 
- HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_ADR
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_MSK
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT
 
- HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH
 
- HW_ATL_RPF_RSS_REDIR_ADDR_ADR
 
- HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT
 
- HW_ATL_RPF_RSS_REDIR_ADDR_MSK
 
- HW_ATL_RPF_RSS_REDIR_ADDR_MSKN
 
- HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT
 
- HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT
 
- HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT
 
- HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT
 
- HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT
 
- HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH
 
- HW_ATL_RPF_VL_ACT_F_ADR
 
- HW_ATL_RPF_VL_ACT_F_DEFAULT
 
- HW_ATL_RPF_VL_ACT_F_MSK
 
- HW_ATL_RPF_VL_ACT_F_MSKN
 
- HW_ATL_RPF_VL_ACT_F_SHIFT
 
- HW_ATL_RPF_VL_ACT_F_WIDTH
 
- HW_ATL_RPF_VL_EN_F_ADR
 
- HW_ATL_RPF_VL_EN_F_DEFAULT
 
- HW_ATL_RPF_VL_EN_F_MSK
 
- HW_ATL_RPF_VL_EN_F_MSKN
 
- HW_ATL_RPF_VL_EN_F_SHIFT
 
- HW_ATL_RPF_VL_EN_F_WIDTH
 
- HW_ATL_RPF_VL_ID_F_ADR
 
- HW_ATL_RPF_VL_ID_F_DEFAULT
 
- HW_ATL_RPF_VL_ID_F_MSK
 
- HW_ATL_RPF_VL_ID_F_MSKN
 
- HW_ATL_RPF_VL_ID_F_SHIFT
 
- HW_ATL_RPF_VL_ID_F_WIDTH
 
- HW_ATL_RPF_VL_INNER_TPID_ADR
 
- HW_ATL_RPF_VL_INNER_TPID_DEFAULT
 
- HW_ATL_RPF_VL_INNER_TPID_MSK
 
- HW_ATL_RPF_VL_INNER_TPID_MSKN
 
- HW_ATL_RPF_VL_INNER_TPID_SHIFT
 
- HW_ATL_RPF_VL_INNER_TPID_WIDTH
 
- HW_ATL_RPF_VL_OUTER_TPID_ADR
 
- HW_ATL_RPF_VL_OUTER_TPID_DEFAULT
 
- HW_ATL_RPF_VL_OUTER_TPID_MSK
 
- HW_ATL_RPF_VL_OUTER_TPID_MSKN
 
- HW_ATL_RPF_VL_OUTER_TPID_SHIFT
 
- HW_ATL_RPF_VL_OUTER_TPID_WIDTH
 
- HW_ATL_RPF_VL_PROMIS_MODE_ADR
 
- HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT
 
- HW_ATL_RPF_VL_PROMIS_MODE_MSK
 
- HW_ATL_RPF_VL_PROMIS_MODE_MSKN
 
- HW_ATL_RPF_VL_PROMIS_MODE_SHIFT
 
- HW_ATL_RPF_VL_PROMIS_MODE_WIDTH
 
- HW_ATL_RPF_VL_RXQ_EN_F_ADR
 
- HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT
 
- HW_ATL_RPF_VL_RXQ_EN_F_MSK
 
- HW_ATL_RPF_VL_RXQ_EN_F_MSKN
 
- HW_ATL_RPF_VL_RXQ_EN_F_SHIFT
 
- HW_ATL_RPF_VL_RXQ_EN_F_WIDTH
 
- HW_ATL_RPF_VL_RXQ_F_ADR
 
- HW_ATL_RPF_VL_RXQ_F_DEFAULT
 
- HW_ATL_RPF_VL_RXQ_F_MSK
 
- HW_ATL_RPF_VL_RXQ_F_MSKN
 
- HW_ATL_RPF_VL_RXQ_F_SHIFT
 
- HW_ATL_RPF_VL_RXQ_F_WIDTH
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_ADR
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_MSK
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT
 
- HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH
 
- HW_ATL_RPOL4CHK_EN_ADR
 
- HW_ATL_RPOL4CHK_EN_DEFAULT
 
- HW_ATL_RPOL4CHK_EN_MSK
 
- HW_ATL_RPOL4CHK_EN_MSKN
 
- HW_ATL_RPOL4CHK_EN_SHIFT
 
- HW_ATL_RPOL4CHK_EN_WIDTH
 
- HW_ATL_RPO_DESCDVL_STRIP_ADR
 
- HW_ATL_RPO_DESCDVL_STRIP_DEFAULT
 
- HW_ATL_RPO_DESCDVL_STRIP_MSK
 
- HW_ATL_RPO_DESCDVL_STRIP_MSKN
 
- HW_ATL_RPO_DESCDVL_STRIP_SHIFT
 
- HW_ATL_RPO_DESCDVL_STRIP_WIDTH
 
- HW_ATL_RPO_IPV4CHK_EN_ADR
 
- HW_ATL_RPO_IPV4CHK_EN_DEFAULT
 
- HW_ATL_RPO_IPV4CHK_EN_MSK
 
- HW_ATL_RPO_IPV4CHK_EN_MSKN
 
- HW_ATL_RPO_IPV4CHK_EN_SHIFT
 
- HW_ATL_RPO_IPV4CHK_EN_WIDTH
 
- HW_ATL_RPO_LRO_EN_ADR
 
- HW_ATL_RPO_LRO_EN_DEFAULT
 
- HW_ATL_RPO_LRO_EN_MSK
 
- HW_ATL_RPO_LRO_EN_MSKN
 
- HW_ATL_RPO_LRO_EN_SHIFT
 
- HW_ATL_RPO_LRO_EN_WIDTH
 
- HW_ATL_RPO_LRO_INA_IVAL_ADR
 
- HW_ATL_RPO_LRO_INA_IVAL_DEFAULT
 
- HW_ATL_RPO_LRO_INA_IVAL_MSK
 
- HW_ATL_RPO_LRO_INA_IVAL_MSKN
 
- HW_ATL_RPO_LRO_INA_IVAL_SHIFT
 
- HW_ATL_RPO_LRO_INA_IVAL_WIDTH
 
- HW_ATL_RPO_LRO_LDES_MAX_DEFAULT
 
- HW_ATL_RPO_LRO_LDES_MAX_WIDTH
 
- HW_ATL_RPO_LRO_MAX_IVAL_ADR
 
- HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT
 
- HW_ATL_RPO_LRO_MAX_IVAL_MSK
 
- HW_ATL_RPO_LRO_MAX_IVAL_MSKN
 
- HW_ATL_RPO_LRO_MAX_IVAL_SHIFT
 
- HW_ATL_RPO_LRO_MAX_IVAL_WIDTH
 
- HW_ATL_RPO_LRO_PKT_MIN_ADR
 
- HW_ATL_RPO_LRO_PKT_MIN_DEFAULT
 
- HW_ATL_RPO_LRO_PKT_MIN_MSK
 
- HW_ATL_RPO_LRO_PKT_MIN_MSKN
 
- HW_ATL_RPO_LRO_PKT_MIN_SHIFT
 
- HW_ATL_RPO_LRO_PKT_MIN_WIDTH
 
- HW_ATL_RPO_LRO_PTOPT_EN_ADR
 
- HW_ATL_RPO_LRO_PTOPT_EN_DEFALT
 
- HW_ATL_RPO_LRO_PTOPT_EN_MSK
 
- HW_ATL_RPO_LRO_PTOPT_EN_MSKN
 
- HW_ATL_RPO_LRO_PTOPT_EN_SHIFT
 
- HW_ATL_RPO_LRO_PTOPT_EN_WIDTH
 
- HW_ATL_RPO_LRO_QSES_LMT_ADR
 
- HW_ATL_RPO_LRO_QSES_LMT_DEFAULT
 
- HW_ATL_RPO_LRO_QSES_LMT_MSK
 
- HW_ATL_RPO_LRO_QSES_LMT_MSKN
 
- HW_ATL_RPO_LRO_QSES_LMT_SHIFT
 
- HW_ATL_RPO_LRO_QSES_LMT_WIDTH
 
- HW_ATL_RPO_LRO_RSC_MAX_ADR
 
- HW_ATL_RPO_LRO_RSC_MAX_DEFAULT
 
- HW_ATL_RPO_LRO_RSC_MAX_MSK
 
- HW_ATL_RPO_LRO_RSC_MAX_MSKN
 
- HW_ATL_RPO_LRO_RSC_MAX_SHIFT
 
- HW_ATL_RPO_LRO_RSC_MAX_WIDTH
 
- HW_ATL_RPO_LRO_TB_DIV_ADR
 
- HW_ATL_RPO_LRO_TB_DIV_DEFAULT
 
- HW_ATL_RPO_LRO_TB_DIV_MSK
 
- HW_ATL_RPO_LRO_TB_DIV_MSKN
 
- HW_ATL_RPO_LRO_TB_DIV_SHIFT
 
- HW_ATL_RPO_LRO_TB_DIV_WIDTH
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT
 
- HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_ADR
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_MSK
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT
 
- HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH
 
- HW_ATL_RX_ACTION_FL3F4_SHIFT
 
- HW_ATL_RX_CNT_REG_ADDR_IPV6
 
- HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4
 
- HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4
 
- HW_ATL_RX_DISCARD
 
- HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR
 
- HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR
 
- HW_ATL_RX_DMA_DESC_STAT_ADR
 
- HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR
 
- HW_ATL_RX_ENABLE_ARP_FLTR_L3
 
- HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3
 
- HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4
 
- HW_ATL_RX_ENABLE_CMP_PROT_L4
 
- HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3
 
- HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4
 
- HW_ATL_RX_ENABLE_FLTR_L3L4
 
- HW_ATL_RX_ENABLE_L3_IPV6
 
- HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4
 
- HW_ATL_RX_ENABLE_QUEUE_L3L4
 
- HW_ATL_RX_FLR_CONTROL2_ADR
 
- HW_ATL_RX_FLR_MCST_FLR_ADR
 
- HW_ATL_RX_FLR_MCST_FLR_MSK_ADR
 
- HW_ATL_RX_FLR_RSS_CONTROL1_ADR
 
- HW_ATL_RX_HOST
 
- HW_ATL_RX_ICMP
 
- HW_ATL_RX_INTR_MODERATION_CTL_ADR
 
- HW_ATL_RX_QUEUE_FL3L4_SHIFT
 
- HW_ATL_RX_REG_RES_DSBL_ADR
 
- HW_ATL_RX_REG_RES_DSBL_DEFAULT
 
- HW_ATL_RX_REG_RES_DSBL_MSK
 
- HW_ATL_RX_REG_RES_DSBL_MSKN
 
- HW_ATL_RX_REG_RES_DSBL_SHIFT
 
- HW_ATL_RX_REG_RES_DSBL_WIDTH
 
- HW_ATL_RX_SCTP
 
- HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4
 
- HW_ATL_RX_TCP
 
- HW_ATL_RX_UDP
 
- HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW
 
- HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW
 
- HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW
 
- HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW
 
- HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW
 
- HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW
 
- HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW
 
- HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW
 
- HW_ATL_TDM_DCADCPUID_ADR
 
- HW_ATL_TDM_DCADCPUID_DEFAULT
 
- HW_ATL_TDM_DCADCPUID_MSK
 
- HW_ATL_TDM_DCADCPUID_MSKN
 
- HW_ATL_TDM_DCADCPUID_SHIFT
 
- HW_ATL_TDM_DCADCPUID_WIDTH
 
- HW_ATL_TDM_DCADDESC_EN_ADR
 
- HW_ATL_TDM_DCADDESC_EN_DEFAULT
 
- HW_ATL_TDM_DCADDESC_EN_MSK
 
- HW_ATL_TDM_DCADDESC_EN_MSKN
 
- HW_ATL_TDM_DCADDESC_EN_SHIFT
 
- HW_ATL_TDM_DCADDESC_EN_WIDTH
 
- HW_ATL_TDM_DCA_DCPUID_ADR
 
- HW_ATL_TDM_DCA_DCPUID_DEFAULT
 
- HW_ATL_TDM_DCA_DCPUID_MSK
 
- HW_ATL_TDM_DCA_DCPUID_MSKN
 
- HW_ATL_TDM_DCA_DCPUID_SHIFT
 
- HW_ATL_TDM_DCA_DCPUID_WIDTH
 
- HW_ATL_TDM_DCA_DDESC_EN_ADR
 
- HW_ATL_TDM_DCA_DDESC_EN_DEFAULT
 
- HW_ATL_TDM_DCA_DDESC_EN_MSK
 
- HW_ATL_TDM_DCA_DDESC_EN_MSKN
 
- HW_ATL_TDM_DCA_DDESC_EN_SHIFT
 
- HW_ATL_TDM_DCA_DDESC_EN_WIDTH
 
- HW_ATL_TDM_DCA_EN_ADR
 
- HW_ATL_TDM_DCA_EN_DEFAULT
 
- HW_ATL_TDM_DCA_EN_MSK
 
- HW_ATL_TDM_DCA_EN_MSKN
 
- HW_ATL_TDM_DCA_EN_SHIFT
 
- HW_ATL_TDM_DCA_EN_WIDTH
 
- HW_ATL_TDM_DCA_MODE_ADR
 
- HW_ATL_TDM_DCA_MODE_DEFAULT
 
- HW_ATL_TDM_DCA_MODE_MSK
 
- HW_ATL_TDM_DCA_MODE_MSKN
 
- HW_ATL_TDM_DCA_MODE_SHIFT
 
- HW_ATL_TDM_DCA_MODE_WIDTH
 
- HW_ATL_TDM_DESCDEN_ADR
 
- HW_ATL_TDM_DESCDEN_DEFAULT
 
- HW_ATL_TDM_DESCDEN_MSK
 
- HW_ATL_TDM_DESCDEN_MSKN
 
- HW_ATL_TDM_DESCDEN_SHIFT
 
- HW_ATL_TDM_DESCDEN_WIDTH
 
- HW_ATL_TDM_DESCDHD_ADR
 
- HW_ATL_TDM_DESCDHD_MSK
 
- HW_ATL_TDM_DESCDHD_MSKN
 
- HW_ATL_TDM_DESCDHD_SHIFT
 
- HW_ATL_TDM_DESCDHD_WIDTH
 
- HW_ATL_TDM_DESCDLEN_ADR
 
- HW_ATL_TDM_DESCDLEN_DEFAULT
 
- HW_ATL_TDM_DESCDLEN_MSK
 
- HW_ATL_TDM_DESCDLEN_MSKN
 
- HW_ATL_TDM_DESCDLEN_SHIFT
 
- HW_ATL_TDM_DESCDLEN_WIDTH
 
- HW_ATL_TDM_DESCDWRB_THRESH_ADR
 
- HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT
 
- HW_ATL_TDM_DESCDWRB_THRESH_MSK
 
- HW_ATL_TDM_DESCDWRB_THRESH_MSKN
 
- HW_ATL_TDM_DESCDWRB_THRESH_SHIFT
 
- HW_ATL_TDM_DESCDWRB_THRESH_WIDTH
 
- HW_ATL_TDM_DESC_DEN_ADR
 
- HW_ATL_TDM_DESC_DEN_DEFAULT
 
- HW_ATL_TDM_DESC_DEN_MSK
 
- HW_ATL_TDM_DESC_DEN_MSKN
 
- HW_ATL_TDM_DESC_DEN_SHIFT
 
- HW_ATL_TDM_DESC_DEN_WIDTH
 
- HW_ATL_TDM_DESC_DHD_ADR
 
- HW_ATL_TDM_DESC_DHD_MSK
 
- HW_ATL_TDM_DESC_DHD_MSKN
 
- HW_ATL_TDM_DESC_DHD_SHIFT
 
- HW_ATL_TDM_DESC_DHD_WIDTH
 
- HW_ATL_TDM_DESC_DLEN_ADR
 
- HW_ATL_TDM_DESC_DLEN_DEFAULT
 
- HW_ATL_TDM_DESC_DLEN_MSK
 
- HW_ATL_TDM_DESC_DLEN_MSKN
 
- HW_ATL_TDM_DESC_DLEN_SHIFT
 
- HW_ATL_TDM_DESC_DLEN_WIDTH
 
- HW_ATL_TDM_DESC_DWRB_THRESH_ADR
 
- HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT
 
- HW_ATL_TDM_DESC_DWRB_THRESH_MSK
 
- HW_ATL_TDM_DESC_DWRB_THRESH_MSKN
 
- HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT
 
- HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH
 
- HW_ATL_TDM_INT_DESC_WRB_EN_ADR
 
- HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT
 
- HW_ATL_TDM_INT_DESC_WRB_EN_MSK
 
- HW_ATL_TDM_INT_DESC_WRB_EN_MSKN
 
- HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT
 
- HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH
 
- HW_ATL_TDM_INT_MOD_EN_ADR
 
- HW_ATL_TDM_INT_MOD_EN_DEFAULT
 
- HW_ATL_TDM_INT_MOD_EN_MSK
 
- HW_ATL_TDM_INT_MOD_EN_MSKN
 
- HW_ATL_TDM_INT_MOD_EN_SHIFT
 
- HW_ATL_TDM_INT_MOD_EN_WIDTH
 
- HW_ATL_TDM_LSO_EN_ADR
 
- HW_ATL_TDM_LSO_EN_DEFAULT
 
- HW_ATL_TDM_LSO_EN_MSK
 
- HW_ATL_TDM_LSO_EN_MSKN
 
- HW_ATL_TDM_LSO_EN_SHIFT
 
- HW_ATL_TDM_LSO_EN_WIDTH
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT
 
- HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT
 
- HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT
 
- HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_ADR
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_MSK
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT
 
- HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH
 
- HW_ATL_TPB_DMA_SYS_LBK_ADR
 
- HW_ATL_TPB_DMA_SYS_LBK_DEFAULT
 
- HW_ATL_TPB_DMA_SYS_LBK_MSK
 
- HW_ATL_TPB_DMA_SYS_LBK_MSKN
 
- HW_ATL_TPB_DMA_SYS_LBK_SHIFT
 
- HW_ATL_TPB_DMA_SYS_LBK_WIDTH
 
- HW_ATL_TPB_TXBBUF_SIZE_ADR
 
- HW_ATL_TPB_TXBBUF_SIZE_DEFAULT
 
- HW_ATL_TPB_TXBBUF_SIZE_MSK
 
- HW_ATL_TPB_TXBBUF_SIZE_MSKN
 
- HW_ATL_TPB_TXBBUF_SIZE_SHIFT
 
- HW_ATL_TPB_TXBBUF_SIZE_WIDTH
 
- HW_ATL_TPB_TXBHI_THRESH_ADR
 
- HW_ATL_TPB_TXBHI_THRESH_DEFAULT
 
- HW_ATL_TPB_TXBHI_THRESH_MSK
 
- HW_ATL_TPB_TXBHI_THRESH_MSKN
 
- HW_ATL_TPB_TXBHI_THRESH_SHIFT
 
- HW_ATL_TPB_TXBHI_THRESH_WIDTH
 
- HW_ATL_TPB_TXBLO_THRESH_ADR
 
- HW_ATL_TPB_TXBLO_THRESH_DEFAULT
 
- HW_ATL_TPB_TXBLO_THRESH_MSK
 
- HW_ATL_TPB_TXBLO_THRESH_MSKN
 
- HW_ATL_TPB_TXBLO_THRESH_SHIFT
 
- HW_ATL_TPB_TXBLO_THRESH_WIDTH
 
- HW_ATL_TPB_TX_BUF_EN_ADR
 
- HW_ATL_TPB_TX_BUF_EN_DEFAULT
 
- HW_ATL_TPB_TX_BUF_EN_MSK
 
- HW_ATL_TPB_TX_BUF_EN_MSKN
 
- HW_ATL_TPB_TX_BUF_EN_SHIFT
 
- HW_ATL_TPB_TX_BUF_EN_WIDTH
 
- HW_ATL_TPB_TX_SCP_INS_EN_ADR
 
- HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT
 
- HW_ATL_TPB_TX_SCP_INS_EN_MSK
 
- HW_ATL_TPB_TX_SCP_INS_EN_MSKN
 
- HW_ATL_TPB_TX_SCP_INS_EN_SHIFT
 
- HW_ATL_TPB_TX_SCP_INS_EN_WIDTH
 
- HW_ATL_TPB_TX_TC_MODE_ADDR
 
- HW_ATL_TPB_TX_TC_MODE_DEFAULT
 
- HW_ATL_TPB_TX_TC_MODE_MSK
 
- HW_ATL_TPB_TX_TC_MODE_MSKN
 
- HW_ATL_TPB_TX_TC_MODE_SHIFT
 
- HW_ATL_TPB_TX_TC_MODE_WIDTH
 
- HW_ATL_TPOL4CHK_EN_ADR
 
- HW_ATL_TPOL4CHK_EN_DEFAULT
 
- HW_ATL_TPOL4CHK_EN_MSK
 
- HW_ATL_TPOL4CHK_EN_MSKN
 
- HW_ATL_TPOL4CHK_EN_SHIFT
 
- HW_ATL_TPOL4CHK_EN_WIDTH
 
- HW_ATL_TPO_IPV4CHK_EN_ADR
 
- HW_ATL_TPO_IPV4CHK_EN_DEFAULT
 
- HW_ATL_TPO_IPV4CHK_EN_MSK
 
- HW_ATL_TPO_IPV4CHK_EN_MSKN
 
- HW_ATL_TPO_IPV4CHK_EN_SHIFT
 
- HW_ATL_TPO_IPV4CHK_EN_WIDTH
 
- HW_ATL_TPO_PKT_SYS_LBK_ADR
 
- HW_ATL_TPO_PKT_SYS_LBK_DEFAULT
 
- HW_ATL_TPO_PKT_SYS_LBK_MSK
 
- HW_ATL_TPO_PKT_SYS_LBK_MSKN
 
- HW_ATL_TPO_PKT_SYS_LBK_SHIFT
 
- HW_ATL_TPO_PKT_SYS_LBK_WIDTH
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT
 
- HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH
 
- HW_ATL_TPS_DATA_TCTWEIGHT_ADR
 
- HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT
 
- HW_ATL_TPS_DATA_TCTWEIGHT_MSK
 
- HW_ATL_TPS_DATA_TCTWEIGHT_MSKN
 
- HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT
 
- HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_ADR
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_MSK
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT
 
- HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH
 
- HW_ATL_TPS_DESC_RATE_LIM_ADR
 
- HW_ATL_TPS_DESC_RATE_LIM_DEFAULT
 
- HW_ATL_TPS_DESC_RATE_LIM_MSK
 
- HW_ATL_TPS_DESC_RATE_LIM_MSKN
 
- HW_ATL_TPS_DESC_RATE_LIM_SHIFT
 
- HW_ATL_TPS_DESC_RATE_LIM_WIDTH
 
- HW_ATL_TPS_DESC_RATE_TA_RST_ADR
 
- HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT
 
- HW_ATL_TPS_DESC_RATE_TA_RST_MSK
 
- HW_ATL_TPS_DESC_RATE_TA_RST_MSKN
 
- HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT
 
- HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT
 
- HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH
 
- HW_ATL_TPS_DESC_TCTWEIGHT_ADR
 
- HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT
 
- HW_ATL_TPS_DESC_TCTWEIGHT_MSK
 
- HW_ATL_TPS_DESC_TCTWEIGHT_MSKN
 
- HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT
 
- HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_ADR
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_MSK
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT
 
- HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_ADR
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_MSK
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT
 
- HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH
 
- HW_ATL_TX_DMA_DEBUG_CTL_ADR
 
- HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR
 
- HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR
 
- HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR
 
- HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR
 
- HW_ATL_TX_INTR_MODERATION_CTL_ADR
 
- HW_ATL_TX_REG_RES_DSBL_ADR
 
- HW_ATL_TX_REG_RES_DSBL_DEFAULT
 
- HW_ATL_TX_REG_RES_DSBL_MSK
 
- HW_ATL_TX_REG_RES_DSBL_MSKN
 
- HW_ATL_TX_REG_RES_DSBL_SHIFT
 
- HW_ATL_TX_REG_RES_DSBL_WIDTH
 
- HW_ATL_UCP_0X370_REG
 
- HW_ATL_UTILS_H
 
- HW_AUTH_DONE
 
- HW_AUTH_STATE_CHG
 
- HW_AUTO_SWITCH_SD_BUS
 
- HW_BAR_BF
 
- HW_BAR_CLOCK
 
- HW_BAR_COUNT
 
- HW_BAR_DB
 
- HW_BB_DFS_HANG
 
- HW_BB_RIFS_HANG
 
- HW_BB_RX_CLEAR_STUCK_HANG
 
- HW_BB_WATCHDOG
 
- HW_BCH_CTRL
 
- HW_BCH_CTRL_CLR
 
- HW_BCH_CTRL_SET
 
- HW_BCH_CTRL_TOG
 
- HW_BCH_DATAPTR
 
- HW_BCH_ENCODEPTR
 
- HW_BCH_FLASH0LAYOUT0
 
- HW_BCH_FLASH0LAYOUT1
 
- HW_BCH_LAYOUTSELECT
 
- HW_BCH_METAPTR
 
- HW_BCH_MODE
 
- HW_BCH_STATUS0
 
- HW_BCH_VERSION
 
- HW_BDIS_ACON_EN
 
- HW_BEACON_BASE
 
- HW_BEACON_BASE0
 
- HW_BEACON_BASE1
 
- HW_BEACON_BASE2
 
- HW_BEACON_BASE3
 
- HW_BEACON_BASE4
 
- HW_BEACON_BASE5
 
- HW_BEACON_BASE6
 
- HW_BEACON_BASE7
 
- HW_BEACON_OFFSET
 
- HW_BG_RATES_MASK
 
- HW_BKSV_RDY
 
- HW_BLOCK
 
- HW_BLOCK_MAC
 
- HW_BLOCK_MAXIMUM
 
- HW_BLOCK_PHY0
 
- HW_BLOCK_PHY1
 
- HW_BLOCK_RF
 
- HW_BLOCK_SIZE
 
- HW_BREAKPOINT_ALIGN
 
- HW_BREAKPOINT_EMPTY
 
- HW_BREAKPOINT_INSTALL
 
- HW_BREAKPOINT_INVALID
 
- HW_BREAKPOINT_LEN_1
 
- HW_BREAKPOINT_LEN_2
 
- HW_BREAKPOINT_LEN_3
 
- HW_BREAKPOINT_LEN_4
 
- HW_BREAKPOINT_LEN_5
 
- HW_BREAKPOINT_LEN_6
 
- HW_BREAKPOINT_LEN_7
 
- HW_BREAKPOINT_LEN_8
 
- HW_BREAKPOINT_R
 
- HW_BREAKPOINT_RESTORE
 
- HW_BREAKPOINT_RW
 
- HW_BREAKPOINT_UNINSTALL
 
- HW_BREAKPOINT_W
 
- HW_BREAKPOINT_X
 
- HW_BRK_TYPE_DABR
 
- HW_BRK_TYPE_EXTRANEOUS_IRQ
 
- HW_BRK_TYPE_HYP
 
- HW_BRK_TYPE_KERNEL
 
- HW_BRK_TYPE_PRIV_ALL
 
- HW_BRK_TYPE_RDWR
 
- HW_BRK_TYPE_READ
 
- HW_BRK_TYPE_TRANSLATE
 
- HW_BRK_TYPE_USER
 
- HW_BRK_TYPE_WRITE
 
- HW_BROADWAY_ICR
 
- HW_BROADWAY_IMR
 
- HW_BSSID_0
 
- HW_BSSID_1
 
- HW_BSSID_2
 
- HW_BSSID_3
 
- HW_BSSID_MAX
 
- HW_BUFFER_MASK
 
- HW_BUFFER_NUM
 
- HW_BUF_SPD_THRESHOLD
 
- HW_CALIBRATION
 
- HW_CAMMCLKDIV
 
- HW_CAPABILITY
 
- HW_CAP_CPU
 
- HW_CAP_CPU_Q
 
- HW_CAP_DDR_0
 
- HW_CAP_DDR_1
 
- HW_CAP_DMA
 
- HW_CAP_GOLDEN
 
- HW_CAP_MME
 
- HW_CAP_MMU
 
- HW_CAP_MSIX
 
- HW_CAP_PLL
 
- HW_CAP_TPC
 
- HW_CAP_TPC_MBIST
 
- HW_CAP_TSO
 
- HW_CARD_DISABLED
 
- HW_CCR
 
- HW_CFG
 
- HW_CFG_32_16_BIT_MODE_
 
- HW_CFG_BCE
 
- HW_CFG_BCE_
 
- HW_CFG_BIR
 
- HW_CFG_BIR_
 
- HW_CFG_CLK125_EN_
 
- HW_CFG_CONNECT_BUF_
 
- HW_CFG_CONNECT_EN_
 
- HW_CFG_CONNECT_POL_
 
- HW_CFG_DRP_
 
- HW_CFG_EEE_PHY_LUSU_
 
- HW_CFG_EEE_TSU_
 
- HW_CFG_EEM
 
- HW_CFG_EEM_
 
- HW_CFG_EE_OTP_RELOAD_
 
- HW_CFG_ETC
 
- HW_CFG_ETC_
 
- HW_CFG_EXT_PHY_DET_
 
- HW_CFG_EXT_PHY_EN_
 
- HW_CFG_IME
 
- HW_CFG_IME_
 
- HW_CFG_LED0_EN_
 
- HW_CFG_LED1_EN_
 
- HW_CFG_LED2_EN_
 
- HW_CFG_LED3_EN_
 
- HW_CFG_LEDB
 
- HW_CFG_LEDB_
 
- HW_CFG_LRST
 
- HW_CFG_LRST_
 
- HW_CFG_MEF
 
- HW_CFG_MEF_
 
- HW_CFG_NETDET_EN_
 
- HW_CFG_NETDET_STS_
 
- HW_CFG_PHY_BOOST
 
- HW_CFG_PHY_BOOST_12
 
- HW_CFG_PHY_BOOST_4
 
- HW_CFG_PHY_BOOST_8
 
- HW_CFG_PHY_BOOST_NORMAL
 
- HW_CFG_PHY_CLK_SEL_
 
- HW_CFG_PHY_CLK_SEL_CLK_DIS_
 
- HW_CFG_PHY_CLK_SEL_EXT_PHY_
 
- HW_CFG_PHY_CLK_SEL_INT_PHY_
 
- HW_CFG_PORT_SWAP
 
- HW_CFG_PSEL_
 
- HW_CFG_REFCLK25_EN_
 
- HW_CFG_RELOAD_TYPE_ALL_
 
- HW_CFG_RST_PROTECT
 
- HW_CFG_RST_PROTECT_
 
- HW_CFG_RXDOFF_
 
- HW_CFG_SBP
 
- HW_CFG_SBP_
 
- HW_CFG_SF_
 
- HW_CFG_SMDET_EN
 
- HW_CFG_SMDET_STS
 
- HW_CFG_SMI_SEL_
 
- HW_CFG_SRST
 
- HW_CFG_SRST_
 
- HW_CFG_SRST_TO_
 
- HW_CFG_SUSPEND_N_POL_
 
- HW_CFG_SUSPEND_N_SEL_0123N
 
- HW_CFG_SUSPEND_N_SEL_012N
 
- HW_CFG_SUSPEND_N_SEL_12N
 
- HW_CFG_SUSPEND_N_SEL_2
 
- HW_CFG_SUSPEND_N_SEL_MASK_
 
- HW_CFG_TR_
 
- HW_CFG_TTM_
 
- HW_CFG_TX_FIF_SZ_
 
- HW_CID
 
- HW_CIIR
 
- HW_CIS_BASE
 
- HW_CLKOUTCLKDIV
 
- HW_CLKOUTCLKSEL
 
- HW_CLKOUTCLKUEN
 
- HW_CMD_BLK_DISCARD
 
- HW_CMD_BLK_READ
 
- HW_CMD_BLK_RECON_READ
 
- HW_CMD_BLK_WRITE
 
- HW_CMD_IDX
 
- HW_CMD_SLOT_SZ
 
- HW_CMPD_RING_SIZE
 
- HW_CNTRS_MAX
 
- HW_COMN_DMA
 
- HW_COMN_IRQ
 
- HW_COMPLY_KRN_NOT_D_CACHED
 
- HW_CONFIG_DUMMY_BITS
 
- HW_CONFIG_REG
 
- HW_CONS_IDX
 
- HW_CONTROL
 
- HW_CONTROL_MASK
 
- HW_CPUCLKDIV
 
- HW_CS_CTS_BASE
 
- HW_CTCR
 
- HW_CTIME0
 
- HW_CTIME1
 
- HW_CTIME2
 
- HW_CTRL
 
- HW_CTRL_COMPATIBLE
 
- HW_CTRL_RESETS
 
- HW_CTRL_RESETS_SYS
 
- HW_CURSOR_AREA_SIZE_300
 
- HW_CURSOR_AREA_SIZE_315
 
- HW_CURSOR_CAP
 
- HW_CURSOR_ENABLE
 
- HW_CURSOR_SIZE
 
- HW_Cursor_OFF
 
- HW_Cursor_ON
 
- HW_DACK_POL_HIGH
 
- HW_DATA_BUS_32BIT
 
- HW_DDC_FROM_BASE
 
- HW_DDC_MASTER
 
- HW_DEACT_CNF
 
- HW_DEACT_IND
 
- HW_DEACT_REQ
 
- HW_DEBUG
 
- HW_DEBUG_IND__HW_00_DEBUG_MASK
 
- HW_DEBUG_IND__HW_00_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_01_DEBUG_MASK
 
- HW_DEBUG_IND__HW_01_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_02_DEBUG_MASK
 
- HW_DEBUG_IND__HW_02_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_03_DEBUG_MASK
 
- HW_DEBUG_IND__HW_03_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_04_DEBUG_MASK
 
- HW_DEBUG_IND__HW_04_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_05_DEBUG_MASK
 
- HW_DEBUG_IND__HW_05_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_06_DEBUG_MASK
 
- HW_DEBUG_IND__HW_06_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_07_DEBUG_MASK
 
- HW_DEBUG_IND__HW_07_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_08_DEBUG_MASK
 
- HW_DEBUG_IND__HW_08_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_09_DEBUG_MASK
 
- HW_DEBUG_IND__HW_09_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_10_DEBUG_MASK
 
- HW_DEBUG_IND__HW_10_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_11_DEBUG_MASK
 
- HW_DEBUG_IND__HW_11_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_12_DEBUG_MASK
 
- HW_DEBUG_IND__HW_12_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_13_DEBUG_MASK
 
- HW_DEBUG_IND__HW_13_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_14_DEBUG_MASK
 
- HW_DEBUG_IND__HW_14_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_15_DEBUG_MASK
 
- HW_DEBUG_IND__HW_15_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_16_DEBUG_MASK
 
- HW_DEBUG_IND__HW_16_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_17_DEBUG_MASK
 
- HW_DEBUG_IND__HW_17_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_18_DEBUG_MASK
 
- HW_DEBUG_IND__HW_18_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_19_DEBUG_MASK
 
- HW_DEBUG_IND__HW_19_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_20_DEBUG_MASK
 
- HW_DEBUG_IND__HW_20_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_21_DEBUG_MASK
 
- HW_DEBUG_IND__HW_21_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_22_DEBUG_MASK
 
- HW_DEBUG_IND__HW_22_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_23_DEBUG_MASK
 
- HW_DEBUG_IND__HW_23_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_24_DEBUG_MASK
 
- HW_DEBUG_IND__HW_24_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_25_DEBUG_MASK
 
- HW_DEBUG_IND__HW_25_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_26_DEBUG_MASK
 
- HW_DEBUG_IND__HW_26_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_27_DEBUG_MASK
 
- HW_DEBUG_IND__HW_27_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_28_DEBUG_MASK
 
- HW_DEBUG_IND__HW_28_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_29_DEBUG_MASK
 
- HW_DEBUG_IND__HW_29_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_30_DEBUG_MASK
 
- HW_DEBUG_IND__HW_30_DEBUG__SHIFT
 
- HW_DEBUG_IND__HW_31_DEBUG_MASK
 
- HW_DEBUG_IND__HW_31_DEBUG__SHIFT
 
- HW_DEBUG_SETTING_BASE
 
- HW_DEBUG_SETTING_BASE2
 
- HW_DEBUG__HW_00_DEBUG_MASK
 
- HW_DEBUG__HW_00_DEBUG__SHIFT
 
- HW_DEBUG__HW_01_DEBUG_MASK
 
- HW_DEBUG__HW_01_DEBUG__SHIFT
 
- HW_DEBUG__HW_02_DEBUG_MASK
 
- HW_DEBUG__HW_02_DEBUG__SHIFT
 
- HW_DEBUG__HW_03_DEBUG_MASK
 
- HW_DEBUG__HW_03_DEBUG__SHIFT
 
- HW_DEBUG__HW_04_DEBUG_MASK
 
- HW_DEBUG__HW_04_DEBUG__SHIFT
 
- HW_DEBUG__HW_05_DEBUG_MASK
 
- HW_DEBUG__HW_05_DEBUG__SHIFT
 
- HW_DEBUG__HW_06_DEBUG_MASK
 
- HW_DEBUG__HW_06_DEBUG__SHIFT
 
- HW_DEBUG__HW_07_DEBUG_MASK
 
- HW_DEBUG__HW_07_DEBUG__SHIFT
 
- HW_DEBUG__HW_08_DEBUG_MASK
 
- HW_DEBUG__HW_08_DEBUG__SHIFT
 
- HW_DEBUG__HW_09_DEBUG_MASK
 
- HW_DEBUG__HW_09_DEBUG__SHIFT
 
- HW_DEBUG__HW_10_DEBUG_MASK
 
- HW_DEBUG__HW_10_DEBUG__SHIFT
 
- HW_DEBUG__HW_11_DEBUG_MASK
 
- HW_DEBUG__HW_11_DEBUG__SHIFT
 
- HW_DEBUG__HW_12_DEBUG_MASK
 
- HW_DEBUG__HW_12_DEBUG__SHIFT
 
- HW_DEBUG__HW_13_DEBUG_MASK
 
- HW_DEBUG__HW_13_DEBUG__SHIFT
 
- HW_DEBUG__HW_14_DEBUG_MASK
 
- HW_DEBUG__HW_14_DEBUG__SHIFT
 
- HW_DEBUG__HW_15_DEBUG_MASK
 
- HW_DEBUG__HW_15_DEBUG__SHIFT
 
- HW_DEBUG__HW_16_DEBUG_MASK
 
- HW_DEBUG__HW_16_DEBUG__SHIFT
 
- HW_DEBUG__HW_17_DEBUG_MASK
 
- HW_DEBUG__HW_17_DEBUG__SHIFT
 
- HW_DEBUG__HW_18_DEBUG_MASK
 
- HW_DEBUG__HW_18_DEBUG__SHIFT
 
- HW_DEBUG__HW_19_DEBUG_MASK
 
- HW_DEBUG__HW_19_DEBUG__SHIFT
 
- HW_DEBUG__HW_20_DEBUG_MASK
 
- HW_DEBUG__HW_20_DEBUG__SHIFT
 
- HW_DEBUG__HW_21_DEBUG_MASK
 
- HW_DEBUG__HW_21_DEBUG__SHIFT
 
- HW_DEBUG__HW_22_DEBUG_MASK
 
- HW_DEBUG__HW_22_DEBUG__SHIFT
 
- HW_DEBUG__HW_23_DEBUG_MASK
 
- HW_DEBUG__HW_23_DEBUG__SHIFT
 
- HW_DEBUG__HW_24_DEBUG_MASK
 
- HW_DEBUG__HW_24_DEBUG__SHIFT
 
- HW_DEBUG__HW_25_DEBUG_MASK
 
- HW_DEBUG__HW_25_DEBUG__SHIFT
 
- HW_DEBUG__HW_26_DEBUG_MASK
 
- HW_DEBUG__HW_26_DEBUG__SHIFT
 
- HW_DEBUG__HW_27_DEBUG_MASK
 
- HW_DEBUG__HW_27_DEBUG__SHIFT
 
- HW_DEBUG__HW_28_DEBUG_MASK
 
- HW_DEBUG__HW_28_DEBUG__SHIFT
 
- HW_DEBUG__HW_29_DEBUG_MASK
 
- HW_DEBUG__HW_29_DEBUG__SHIFT
 
- HW_DEBUG__HW_30_DEBUG_MASK
 
- HW_DEBUG__HW_30_DEBUG__SHIFT
 
- HW_DEBUG__HW_31_DEBUG_MASK
 
- HW_DEBUG__HW_31_DEBUG__SHIFT
 
- HW_DEF_FA_CNT_DUMP
 
- HW_DEF_ODM_DBG_FLAG
 
- HW_DEF_ODM_DBG_LEVEL
 
- HW_DEF_RA_INFO_DUMP
 
- HW_DELAY
 
- HW_DESC_OWN
 
- HW_DESC_RXBUFF_ADDR
 
- HW_DESC_RXERO
 
- HW_DESC_RXOWN
 
- HW_DESC_RXPKT_LEN
 
- HW_DESC_RX_PREPARE
 
- HW_DESC_SIZE_WORDS
 
- HW_DESC_TXBUFF_ADDR
 
- HW_DESC_TX_NEXTDESC_ADDR
 
- HW_DEV_DMA
 
- HW_DFS_CTS_BASE
 
- HW_DIGCTL_CHIPID
 
- HW_DIGCTL_CHIPID_MASK
 
- HW_DIGCTL_CHIPID_MX23
 
- HW_DIGCTL_CHIPID_MX28
 
- HW_DIGCTL_REV_MASK
 
- HW_DIR
 
- HW_DISABLE
 
- HW_DMA_CAP_32B
 
- HW_DMA_CAP_64B
 
- HW_DMA_CAP_64B_PTP
 
- HW_DMA_CAP_PTP
 
- HW_DM_PULLDOWN
 
- HW_DOM
 
- HW_DOW
 
- HW_DOY
 
- HW_DP_PULLDOWN
 
- HW_DP_PULLUP
 
- HW_DREQ_POL_HIGH
 
- HW_D_NOBLOCKED
 
- HW_ENABLE
 
- HW_ENABLE_GATE
 
- HW_ENCRY_SW_DECRY
 
- HW_ERR
 
- HW_ERROR
 
- HW_ERROR_SCRUB_OFF
 
- HW_ERROR_SCRUB_ON
 
- HW_EVENTS_CTL
 
- HW_EVENT_AICA_SYS
 
- HW_EVENT_BROADCAST_CHANGE
 
- HW_EVENT_BROADCAST_EXP
 
- HW_EVENT_BROADCAST_SES
 
- HW_EVENT_CHIP_RESET_COMPLETE
 
- HW_EVENT_ERR_CORRECTED
 
- HW_EVENT_ERR_DEFERRED
 
- HW_EVENT_ERR_FATAL
 
- HW_EVENT_ERR_INFO
 
- HW_EVENT_ERR_UNCORRECTED
 
- HW_EVENT_EXTERNAL
 
- HW_EVENT_FLASH_FW_ERR
 
- HW_EVENT_G2_DMA
 
- HW_EVENT_GDROM_CMD
 
- HW_EVENT_GDROM_DMA
 
- HW_EVENT_HARD_RESET_RECEIVED
 
- HW_EVENT_ID_FRAME_TIMEOUT
 
- HW_EVENT_INBOUND_CRC_ERROR
 
- HW_EVENT_IRQ_BASE
 
- HW_EVENT_IRQ_MAX
 
- HW_EVENT_ISP_ERR
 
- HW_EVENT_LINK_ERR_CODE_VIOLATION
 
- HW_EVENT_LINK_ERR_DISPARITY_ERROR
 
- HW_EVENT_LINK_ERR_INVALID_DWORD
 
- HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH
 
- HW_EVENT_LINK_ERR_PHY_RESET_FAILED
 
- HW_EVENT_MALFUNCTION
 
- HW_EVENT_MAPLE_DMA
 
- HW_EVENT_NVRAM_CHKSUM_ERR
 
- HW_EVENT_PARITY_ERR
 
- HW_EVENT_PHY_DOWN
 
- HW_EVENT_PHY_ERROR
 
- HW_EVENT_PHY_START_STATUS
 
- HW_EVENT_PHY_STOP_STATUS
 
- HW_EVENT_PORT_INVALID
 
- HW_EVENT_PORT_RECOVER
 
- HW_EVENT_PORT_RECOVERY_TIMER_TMO
 
- HW_EVENT_PORT_RESET_COMPLETE
 
- HW_EVENT_PORT_RESET_TIMER_TMO
 
- HW_EVENT_PVR2_DMA
 
- HW_EVENT_RESET_ERR
 
- HW_EVENT_RESET_START
 
- HW_EVENT_SAS_PHY_UP
 
- HW_EVENT_SATA_PHY_UP
 
- HW_EVENT_SATA_SPINUP_HOLD
 
- HW_EVENT_VSYNC
 
- HW_FEATURE_32_BIT_UNIFORM_ADDRESS
 
- HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG
 
- HW_FEATURE_AARCH64_MMU
 
- HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL
 
- HW_FEATURE_BRNDOUT_CC
 
- HW_FEATURE_BRNDOUT_KILL
 
- HW_FEATURE_COHERENCY_REG
 
- HW_FEATURE_FLUSH_REDUCTION
 
- HW_FEATURE_IMAGES_IN_FRAGMENT_SHADERS
 
- HW_FEATURE_INTERPIPE_REG_ALIASING
 
- HW_FEATURE_JOBCHAIN_DISAMBIGUATION
 
- HW_FEATURE_LD_ST_LEA_TEX
 
- HW_FEATURE_LD_ST_TILEBUFFER
 
- HW_FEATURE_LEN
 
- HW_FEATURE_LINEAR_FILTER_FLOAT
 
- HW_FEATURE_MRT
 
- HW_FEATURE_MSAA_16X
 
- HW_FEATURE_NEXT_INSTRUCTION_TYPE
 
- HW_FEATURE_OPTIMIZED_COVERAGE_MASK
 
- HW_FEATURE_OUT_OF_ORDER_EXEC
 
- HW_FEATURE_PROTECTED_DEBUG_MODE
 
- HW_FEATURE_PROTECTED_MODE
 
- HW_FEATURE_PWRON_DURING_PWROFF_TRANS
 
- HW_FEATURE_RFKILL
 
- HW_FEATURE_T7XX_PAIRING_RULES
 
- HW_FEATURE_TEST4_DATUM_MODE
 
- HW_FEATURE_THREAD_GROUP_SPLIT
 
- HW_FEATURE_TLS_HASHING
 
- HW_FEATURE_V4
 
- HW_FEATURE_WARPING
 
- HW_FEATURE_WORKGROUP_ROUND_MULTIPLE_OF_4
 
- HW_FEATURE_XAFFINITY
 
- HW_Fsync
 
- HW_GENERIC_FROM_BASE
 
- HW_GLOBAL_INTR_EN
 
- HW_GPIOB_DIR
 
- HW_GPIOB_IN
 
- HW_GPIOB_INMIR
 
- HW_GPIOB_INTFLAG
 
- HW_GPIOB_INTLVL
 
- HW_GPIOB_INTMASK
 
- HW_GPIOB_OUT
 
- HW_GPIO_BASE
 
- HW_GPIO_COMPATIBLE
 
- HW_GPIO_DIR
 
- HW_GPIO_ENABLE
 
- HW_GPIO_FROM_BASE
 
- HW_GPIO_IN
 
- HW_GPIO_INMIR
 
- HW_GPIO_INTFLAG
 
- HW_GPIO_INTLVL
 
- HW_GPIO_INTMASK
 
- HW_GPIO_OUT
 
- HW_GPIO_OWNER
 
- HW_GPIO_SENSOR_BAR
 
- HW_GPIO_SHUTDOWN
 
- HW_GPIO_SLOT_LED
 
- HW_GPMI_AUXILIARY
 
- HW_GPMI_COMPARE
 
- HW_GPMI_CTRL0
 
- HW_GPMI_CTRL0_CLR
 
- HW_GPMI_CTRL0_SET
 
- HW_GPMI_CTRL0_TOG
 
- HW_GPMI_CTRL1
 
- HW_GPMI_CTRL1_CLR
 
- HW_GPMI_CTRL1_SET
 
- HW_GPMI_CTRL1_TOG
 
- HW_GPMI_DATA
 
- HW_GPMI_DEBUG
 
- HW_GPMI_ECCCOUNT
 
- HW_GPMI_ECCCTRL
 
- HW_GPMI_ECCCTRL_CLR
 
- HW_GPMI_ECCCTRL_SET
 
- HW_GPMI_ECCCTRL_TOG
 
- HW_GPMI_PAYLOAD
 
- HW_GPMI_STAT
 
- HW_GPMI_TIMING0
 
- HW_GPMI_TIMING1
 
- HW_GPMI_TIMING2
 
- HW_GPREG0
 
- HW_GPREG1
 
- HW_GPREG2
 
- HW_GPREG3
 
- HW_GPREG4
 
- HW_H
 
- HW_HASH_INDEX_SIZE
 
- HW_HASH_KEY_SIZE
 
- HW_HOUR
 
- HW_HPD_FROM_BASE
 
- HW_HT_RATES_OFFSET
 
- HW_I2C_READ
 
- HW_I2C_SMBUS_BYTE_WR
 
- HW_I2C_WRITE
 
- HW_I2S0CLKSEL
 
- HW_I2S0CLKUEN
 
- HW_I2S0MCLKDIV
 
- HW_I2S0SCLKDIV
 
- HW_I2S1CLKSEL
 
- HW_I2S1CLKUEN
 
- HW_I2S1MCLKDIV
 
- HW_I2S1SCLKDIV
 
- HW_ICOLL_CTRL
 
- HW_ICOLL_INTERRUPT0
 
- HW_ICOLL_INTERRUPTn
 
- HW_ICOLL_LEVELACK
 
- HW_ICOLL_STAT_OFFSET
 
- HW_ICOLL_VECTOR
 
- HW_ID
 
- HW_ID_MAX
 
- HW_ILR
 
- HW_INFO_INDEX
 
- HW_INJ
 
- HW_INTERRUPT_ASSERT_SET_0
 
- HW_INTERRUPT_ASSERT_SET_1
 
- HW_INTERRUPT_ASSERT_SET_2
 
- HW_INTR_EDGE_TRIG
 
- HW_INTR_HIGH_ACT
 
- HW_INTR_STATUS
 
- HW_INT_WRITE_CLR
 
- HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT
 
- HW_IOP_RESET
 
- HW_IR
 
- HW_IRQ_EXTERN_BASE
 
- HW_IRQ_IPI_COUNT
 
- HW_IRQ_MX_BASE
 
- HW_ISSUE_10327
 
- HW_ISSUE_10649
 
- HW_ISSUE_10676
 
- HW_ISSUE_10797
 
- HW_ISSUE_10817
 
- HW_ISSUE_10883
 
- HW_ISSUE_10959
 
- HW_ISSUE_10969
 
- HW_ISSUE_11020
 
- HW_ISSUE_11024
 
- HW_ISSUE_11035
 
- HW_ISSUE_11056
 
- HW_ISSUE_6367
 
- HW_ISSUE_6787
 
- HW_ISSUE_8186
 
- HW_ISSUE_8245
 
- HW_ISSUE_8316
 
- HW_ISSUE_8394
 
- HW_ISSUE_8401
 
- HW_ISSUE_8408
 
- HW_ISSUE_8443
 
- HW_ISSUE_8987
 
- HW_ISSUE_9435
 
- HW_ISSUE_9510
 
- HW_ISSUE_9630
 
- HW_ISSUE_END
 
- HW_ISSUE_T76X_3542
 
- HW_ISSUE_T76X_3953
 
- HW_ISSUE_TGOX_R1_1234
 
- HW_ISSUE_TMIX_8438
 
- HW_ISSUE_TMIX_8463
 
- HW_KEY_DEFAULT
 
- HW_KEY_DYNAMIC
 
- HW_KEY_MASK_CIPHER_DO
 
- HW_KEY_SHIFT_CIPHER_CFG2
 
- HW_LAYOUT_DVI_ONLY
 
- HW_LAYOUT_LCD1_LCD2
 
- HW_LAYOUT_LCD_DVI
 
- HW_LAYOUT_LCD_EXTERNAL_LCD2
 
- HW_LAYOUT_LCD_ONLY
 
- HW_LCDCLKDIV
 
- HW_LED
 
- HW_LINK_TRAINING_PATTERN
 
- HW_LOCK_MAX_RESOURCE_VALUE
 
- HW_LOCK_RESOURCE_DCBX_ADMIN_MIB
 
- HW_LOCK_RESOURCE_DRV_FLAGS
 
- HW_LOCK_RESOURCE_GPIO
 
- HW_LOCK_RESOURCE_MDIO
 
- HW_LOCK_RESOURCE_NVRAM
 
- HW_LOCK_RESOURCE_PORT0_ATT_MASK
 
- HW_LOCK_RESOURCE_RECOVERY_LEADER_0
 
- HW_LOCK_RESOURCE_RECOVERY_LEADER_1
 
- HW_LOCK_RESOURCE_RECOVERY_REG
 
- HW_LOCK_RESOURCE_RESET
 
- HW_LOCK_RESOURCE_SPIO
 
- HW_LSB_MASK
 
- HW_LSB_SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT
 
- HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT
 
- HW_MACCLKDIV
 
- HW_MACHINE_BOOT_DONE
 
- HW_MAC_HANG
 
- HW_MAINCLKSEL
 
- HW_MAINCLKUEN
 
- HW_MB_STORE_SZ
 
- HW_MCAST_SIZE
 
- HW_MCR
 
- HW_MIB_SIZE
 
- HW_MIB_ifInRangeLengthErrors
 
- HW_MIB_ifLateCollisions
 
- HW_MIB_ifRx1024To1518Pkts
 
- HW_MIB_ifRx128To255Pkts
 
- HW_MIB_ifRx256To511Pkts
 
- HW_MIB_ifRx512To1023Pkts
 
- HW_MIB_ifRx64Pkts
 
- HW_MIB_ifRx65To127Pkts
 
- HW_MIB_ifRxAllPkts
 
- HW_MIB_ifRxErrorPkts
 
- HW_MIB_ifRxJumboPkts
 
- HW_MIB_ifRxLongOkPkt
 
- HW_MIB_ifRxLongPktErrPkt
 
- HW_MIB_ifRxMacControlFrames
 
- HW_MIB_ifRxNobuf
 
- HW_MIB_ifRxOkPkts
 
- HW_MIB_ifRxPktCRCE
 
- HW_MIB_ifRxPktFAE
 
- HW_MIB_ifRxRuntErrPkt
 
- HW_MIB_ifRxRuntOkPkt
 
- HW_MIB_ifRxSymbolErrors
 
- HW_MIB_ifTXSQEErrors
 
- HW_MIB_ifTx1024To1518Pkts
 
- HW_MIB_ifTx128To255Pkts
 
- HW_MIB_ifTx256To511Pkts
 
- HW_MIB_ifTx512To1023Pkts
 
- HW_MIB_ifTx64Pkts
 
- HW_MIB_ifTx65To127Pkts
 
- HW_MIB_ifTxEtherCollisions
 
- HW_MIB_ifTxJumboPkts
 
- HW_MIB_ifTxMacControlFrames
 
- HW_MIB_ifTxOkPkts
 
- HW_MIMO_RATES_OFFSET
 
- HW_MIN
 
- HW_MIRRORING_DISABLE
 
- HW_MIRRORING_ENABLE
 
- HW_MOD_CONNECT
 
- HW_MOD_FCERROR
 
- HW_MOD_FRH
 
- HW_MOD_FRM
 
- HW_MOD_FTH
 
- HW_MOD_FTM
 
- HW_MOD_FTS
 
- HW_MOD_LASTDATA
 
- HW_MOD_NOCARR
 
- HW_MOD_OK
 
- HW_MOD_READY
 
- HW_MONTH
 
- HW_MR0
 
- HW_MR1
 
- HW_MR2
 
- HW_MR3
 
- HW_MULTICAST_SIZE
 
- HW_NANDCLKDIV
 
- HW_NO_CHANGE
 
- HW_NULL_BASE
 
- HW_OFF
 
- HW_OFF_RAMRET
 
- HW_ON
 
- HW_ONLY_GATE
 
- HW_OP_UNSUPPORTED
 
- HW_OTG_CTRL_CLR
 
- HW_OTG_CTRL_SET
 
- HW_OTG_DISABLE
 
- HW_OTG_SE0_EN
 
- HW_OWNER
 
- HW_PAGE_MASK
 
- HW_PAGE_SHIFT
 
- HW_PAGE_SIZE
 
- HW_PARAM_ENTRY
 
- HW_PART0_SIZE_ADDR
 
- HW_PART0_START_ADDR
 
- HW_PART1_SIZE_ADDR
 
- HW_PART1_START_ADDR
 
- HW_PART2_SIZE_ADDR
 
- HW_PART2_START_ADDR
 
- HW_PART3_SIZE_ADDR
 
- HW_PART3_START_ADDR
 
- HW_PARTITION_REGISTERS_ADDR
 
- HW_PATCH_LEVEL_RD
 
- HW_PC
 
- HW_PHYRESTART_CLC_WAR
 
- HW_PHY_OFF_LOOP_DELAY
 
- HW_PI
 
- HW_PI2
 
- HW_POINT_POSITION_LEFT
 
- HW_POINT_POSITION_MIDDLE
 
- HW_POINT_POSITION_RIGHT
 
- HW_POWERDOWN
 
- HW_POWERUP_IND
 
- HW_POWERUP_REQ
 
- HW_POWER_DOWN_DELAY
 
- HW_PR
 
- HW_PRTY_ASSERT_SET_0
 
- HW_PRTY_ASSERT_SET_1
 
- HW_PRTY_ASSERT_SET_2
 
- HW_PRTY_ASSERT_SET_3
 
- HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD
 
- HW_PRTY_ASSERT_SET_4
 
- HW_PTR
 
- HW_PWR0
 
- HW_PWR1
 
- HW_PWR2
 
- HW_PWR3
 
- HW_PWR4
 
- HW_PXP_ALPHA_A_CTRL
 
- HW_PXP_ALPHA_B_CTRL
 
- HW_PXP_ALPHA_B_CTRL_1
 
- HW_PXP_AS_BUF
 
- HW_PXP_AS_CLRKEYHIGH_0
 
- HW_PXP_AS_CLRKEYHIGH_1
 
- HW_PXP_AS_CLRKEYLOW_0
 
- HW_PXP_AS_CLRKEYLOW_1
 
- HW_PXP_AS_CTRL
 
- HW_PXP_AS_PITCH
 
- HW_PXP_CFA
 
- HW_PXP_CSC1_COEF0
 
- HW_PXP_CSC1_COEF1
 
- HW_PXP_CSC1_COEF2
 
- HW_PXP_CSC2_COEF0
 
- HW_PXP_CSC2_COEF1
 
- HW_PXP_CSC2_COEF2
 
- HW_PXP_CSC2_COEF3
 
- HW_PXP_CSC2_COEF4
 
- HW_PXP_CSC2_COEF5
 
- HW_PXP_CSC2_CTRL
 
- HW_PXP_CTRL
 
- HW_PXP_CTRL2
 
- HW_PXP_CTRL2_CLR
 
- HW_PXP_CTRL2_SET
 
- HW_PXP_CTRL2_TOG
 
- HW_PXP_CTRL_CLR
 
- HW_PXP_CTRL_SET
 
- HW_PXP_CTRL_TOG
 
- HW_PXP_DATA_PATH_CTRL0
 
- HW_PXP_DATA_PATH_CTRL0_CLR
 
- HW_PXP_DATA_PATH_CTRL0_SET
 
- HW_PXP_DATA_PATH_CTRL0_TOG
 
- HW_PXP_DATA_PATH_CTRL1
 
- HW_PXP_DATA_PATH_CTRL1_CLR
 
- HW_PXP_DATA_PATH_CTRL1_SET
 
- HW_PXP_DATA_PATH_CTRL1_TOG
 
- HW_PXP_DEBUG
 
- HW_PXP_DEBUGCTRL
 
- HW_PXP_INIT_MEM_CTRL
 
- HW_PXP_INIT_MEM_CTRL_CLR
 
- HW_PXP_INIT_MEM_CTRL_SET
 
- HW_PXP_INIT_MEM_CTRL_TOG
 
- HW_PXP_INIT_MEM_DATA
 
- HW_PXP_INIT_MEM_DATA_HIGH
 
- HW_PXP_IRQ
 
- HW_PXP_IRQ_CLR
 
- HW_PXP_IRQ_MASK
 
- HW_PXP_IRQ_MASK_CLR
 
- HW_PXP_IRQ_MASK_SET
 
- HW_PXP_IRQ_MASK_TOG
 
- HW_PXP_IRQ_SET
 
- HW_PXP_IRQ_TOG
 
- HW_PXP_LUT_ADDR
 
- HW_PXP_LUT_CTRL
 
- HW_PXP_LUT_DATA
 
- HW_PXP_LUT_EXTMEM
 
- HW_PXP_NEXT
 
- HW_PXP_OUT_AS_LRC
 
- HW_PXP_OUT_AS_ULC
 
- HW_PXP_OUT_BUF
 
- HW_PXP_OUT_BUF2
 
- HW_PXP_OUT_CTRL
 
- HW_PXP_OUT_CTRL_CLR
 
- HW_PXP_OUT_CTRL_SET
 
- HW_PXP_OUT_CTRL_TOG
 
- HW_PXP_OUT_LRC
 
- HW_PXP_OUT_PITCH
 
- HW_PXP_OUT_PS_LRC
 
- HW_PXP_OUT_PS_ULC
 
- HW_PXP_POWER_REG0
 
- HW_PXP_POWER_REG1
 
- HW_PXP_PS_BACKGROUND_0
 
- HW_PXP_PS_BACKGROUND_1
 
- HW_PXP_PS_BUF
 
- HW_PXP_PS_CLRKEYHIGH_0
 
- HW_PXP_PS_CLRKEYHIGH_1
 
- HW_PXP_PS_CLRKEYLOW_0
 
- HW_PXP_PS_CLRKEYLOW_1
 
- HW_PXP_PS_CTRL
 
- HW_PXP_PS_CTRL_CLR
 
- HW_PXP_PS_CTRL_SET
 
- HW_PXP_PS_CTRL_TOG
 
- HW_PXP_PS_OFFSET
 
- HW_PXP_PS_PITCH
 
- HW_PXP_PS_SCALE
 
- HW_PXP_PS_UBUF
 
- HW_PXP_PS_VBUF
 
- HW_PXP_STAT
 
- HW_PXP_STAT_CLR
 
- HW_PXP_STAT_SET
 
- HW_PXP_STAT_TOG
 
- HW_PXP_VERSION
 
- HW_QUADSPICLKDIV
 
- HW_QUEUE_ENTRY
 
- HW_QUEUE_LENGTH
 
- HW_QUEUE_SLOTS_MAX
 
- HW_RATE_INDEX_11MBPS
 
- HW_RATE_INDEX_12MBPS
 
- HW_RATE_INDEX_18MBPS
 
- HW_RATE_INDEX_1MBPS
 
- HW_RATE_INDEX_24MBPS
 
- HW_RATE_INDEX_2MBPS
 
- HW_RATE_INDEX_36MBPS
 
- HW_RATE_INDEX_48MBPS
 
- HW_RATE_INDEX_54MBPS
 
- HW_RATE_INDEX_5_5MBPS
 
- HW_RATE_INDEX_6MBPS
 
- HW_RATE_INDEX_9MBPS
 
- HW_RAW
 
- HW_READY_TIMEOUT
 
- HW_REG
 
- HW_REG_BLND
 
- HW_REG_CRTC
 
- HW_RESET
 
- HW_RESET_IND
 
- HW_RESET_REQ
 
- HW_REV
 
- HW_REVID
 
- HW_REVID_MASK
 
- HW_REVISION_ID
 
- HW_REV_REG
 
- HW_ROP2_COPY
 
- HW_ROP2_XOR
 
- HW_ROTATION__GRPH_ROTATION_ANGLE_MASK
 
- HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT
 
- HW_RTS_EN
 
- HW_RXBD_RING_SIZE
 
- HW_RX_FIFO_DEPTH
 
- HW_S5
 
- HW_SCATTER_GATHER_ELEMENT
 
- HW_SEC
 
- HW_SEL_CP_EXT
 
- HW_SEQ_EN
 
- HW_SHA_DONE
 
- HW_SOFT_RESET
 
- HW_SOURCE_SEL_DSC_JPEG
 
- HW_SOURCE_SEL_DSC_VLP
 
- HW_SOURCE_SEL_DSC_VUP
 
- HW_SOURCE_SEL_NONE
 
- HW_SPEED_100_MBPS
 
- HW_SPEED_10_MBPS
 
- HW_SPEED_DEFAULT
 
- HW_SPEED_HOME
 
- HW_SPEED_UNCONFIG
 
- HW_SPI0CLKDIV
 
- HW_SPI1CLKDIV
 
- HW_SPINLOCK_BASE
 
- HW_SPINLOCK_NUMBER
 
- HW_SPINLOCK_OFFSET
 
- HW_SSN
 
- HW_SSP0CLKDIV
 
- HW_SSP_BLOCK_SIZE
 
- HW_SSP_CMD0
 
- HW_SSP_CMD1
 
- HW_SSP_CTRL0
 
- HW_SSP_CTRL1
 
- HW_SSP_DATA
 
- HW_SSP_SDRESP0
 
- HW_SSP_SDRESP1
 
- HW_SSP_SDRESP2
 
- HW_SSP_SDRESP3
 
- HW_SSP_STATUS
 
- HW_SSP_TIMING
 
- HW_SSP_XFER_SIZE
 
- HW_STARLET_ICR
 
- HW_STARLET_IMR
 
- HW_STAT
 
- HW_STATUS_CNT
 
- HW_STATUS_CRC
 
- HW_STATUS_FAULT
 
- HW_STATUS_HARD_ERR
 
- HW_STATUS_REG
 
- HW_STATUS_SOFT_ERR
 
- HW_STEP_LOCATION_BITS
 
- HW_STRAP1
 
- HW_STRAP2
 
- HW_SW_GATE
 
- HW_SW_GATE_AUTO
 
- HW_SW_SEL_HC_DC
 
- HW_SYNC_SLEEP_TIME_INTERVAL
 
- HW_SYNC_TIMEOUT_MSECS
 
- HW_SYSAHBCLKDIV
 
- HW_SYSPLLCTRL
 
- HW_TC0
 
- HW_TC1
 
- HW_TC2
 
- HW_TC3
 
- HW_TCR
 
- HW_TEST
 
- HW_TESTLOOP
 
- HW_TESTRX_HDLC
 
- HW_TESTRX_OFF
 
- HW_TESTRX_RAW
 
- HW_TIMER3_IND
 
- HW_TIMER3_VALUE
 
- HW_TIMER3_VMASK
 
- HW_TIMROT_FIXED_COUNTn
 
- HW_TIMROT_ROTCTRL
 
- HW_TIMROT_RUNNING_COUNTn
 
- HW_TIMROT_TIMCOUNTn
 
- HW_TIMROT_TIMCTRLn
 
- HW_TO_DEV_PORT
 
- HW_TPL_FR_MT_PR_IV_P_FC
 
- HW_TPL_FR_MT_PR_OV_P_FC
 
- HW_TRACE
 
- HW_TRACECLKDIV
 
- HW_TRAINING_FINISH
 
- HW_TRAP_P
 
- HW_TRIG_EN
 
- HW_TWIN
 
- HW_TXBD_RING_SIZE
 
- HW_TX_FIFO_DEPTH
 
- HW_UART0CLKDIV
 
- HW_UART1CLKDIV
 
- HW_UART2CLKDIV
 
- HW_UART3CLKDIV
 
- HW_UART4CLKDIV
 
- HW_UART5CLKDIV
 
- HW_UART6CLKDIV
 
- HW_UART7CLKDIV
 
- HW_UART8CLKDIV
 
- HW_UART9CLKDIV
 
- HW_UARTCLKSEL
 
- HW_UARTCLKUEN
 
- HW_USB2_3_SEL
 
- HW_USBPHY_CTRL
 
- HW_USBPHY_CTRL_CLR
 
- HW_USBPHY_CTRL_SET
 
- HW_USBPHY_DEBUG_CLR
 
- HW_USBPHY_DEBUG_SET
 
- HW_USBPHY_IP
 
- HW_USBPHY_IP_CLR
 
- HW_USBPHY_IP_SET
 
- HW_USBPHY_PLL_SIC
 
- HW_USBPHY_PLL_SIC_CLR
 
- HW_USBPHY_PLL_SIC_SET
 
- HW_USBPHY_PWD
 
- HW_USBPHY_TX
 
- HW_VARIABLES
 
- HW_VAR_1X1_RECV_COMBINE
 
- HW_VAR_ACK_PREAMBLE
 
- HW_VAR_ACM_CTRL
 
- HW_VAR_AC_PARAM
 
- HW_VAR_AC_PARAM_BE
 
- HW_VAR_AC_PARAM_BK
 
- HW_VAR_AC_PARAM_VI
 
- HW_VAR_AC_PARAM_VO
 
- HW_VAR_AES_11N_FIX
 
- HW_VAR_AID
 
- HW_VAR_AMPDU_FACTOR
 
- HW_VAR_AMPDU_MAX_TIME
 
- HW_VAR_AMPDU_MIN_SPACE
 
- HW_VAR_ANTENNA_DIVERSITY_LINK
 
- HW_VAR_ANTENNA_DIVERSITY_SELECT
 
- HW_VAR_APFM_ON_MAC
 
- HW_VAR_AP_WOWLAN
 
- HW_VAR_ATIM_WINDOW
 
- HW_VAR_AUTOLOAD_STATUS
 
- HW_VAR_BASIC_RATE
 
- HW_VAR_BCN_FUNC
 
- HW_VAR_BCN_VALID
 
- HW_VAR_BEACON_INTERVAL
 
- HW_VAR_BSSID
 
- HW_VAR_BT_ISSUE_DELBA
 
- HW_VAR_BT_SET_COEXIST
 
- HW_VAR_BUS_SPEED
 
- HW_VAR_C2H_HANDLE
 
- HW_VAR_CAM_EMPTY_ENTRY
 
- HW_VAR_CAM_INVALID_ALL
 
- HW_VAR_CAM_READ
 
- HW_VAR_CAM_WRITE
 
- HW_VAR_CCX_CHNL_LOAD
 
- HW_VAR_CCX_CLM_NHM
 
- HW_VAR_CCX_NOISE_HISTOGRAM
 
- HW_VAR_CECHK_BSSID
 
- HW_VAR_CHECK_BSSID
 
- HW_VAR_CHECK_TXBUF
 
- HW_VAR_CHK_HI_QUEUE_EMPTY
 
- HW_VAR_COMMAND
 
- HW_VAR_CONTENTION_WINDOW
 
- HW_VAR_CORRECT_TSF
 
- HW_VAR_CPU_RST
 
- HW_VAR_CPWM
 
- HW_VAR_CS_COUNTER
 
- HW_VAR_CTRL_FILTER
 
- HW_VAR_CURRENT_ANTENNA
 
- HW_VAR_CW_CONFIG
 
- HW_VAR_CW_VALUES
 
- HW_VAR_DATA_FILTER
 
- HW_VAR_DEFAULTKEY0
 
- HW_VAR_DEFAULTKEY1
 
- HW_VAR_DEFAULTKEY2
 
- HW_VAR_DEFAULTKEY3
 
- HW_VAR_DIFS
 
- HW_VAR_DIS_REQ_QSIZE
 
- HW_VAR_DIS_Req_Qsize
 
- HW_VAR_DL_BCN_SEL
 
- HW_VAR_DL_FW_RSVD_PAGE
 
- HW_VAR_DL_RSVD_PAGE
 
- HW_VAR_DM_FLAG
 
- HW_VAR_DM_FUNC_CLR
 
- HW_VAR_DM_FUNC_OP
 
- HW_VAR_DM_FUNC_SET
 
- HW_VAR_DM_IN_LPS
 
- HW_VAR_DO_IQK
 
- HW_VAR_DUAL_TSF_RST
 
- HW_VAR_EFUSE_BT_BYTES
 
- HW_VAR_EFUSE_BT_USAGE
 
- HW_VAR_EFUSE_BYTES
 
- HW_VAR_EFUSE_USAGE
 
- HW_VAR_EIFS
 
- HW_VAR_ETHER_ADDR
 
- HW_VAR_FIFO_CLEARN_UP
 
- HW_VAR_FWLPS_RF_ON
 
- HW_VAR_FW_LPS_ACTION
 
- HW_VAR_FW_PSMODE_STATUS
 
- HW_VAR_FW_PS_STATE
 
- HW_VAR_H2C_FW_JOINBSSRPT
 
- HW_VAR_H2C_FW_MEDIASTATUSRPT
 
- HW_VAR_H2C_FW_OFFLOAD
 
- HW_VAR_H2C_FW_P2P_PS_OFFLOAD
 
- HW_VAR_H2C_FW_PWRMODE
 
- HW_VAR_H2C_FW_UPDATE_GTK
 
- HW_VAR_H2C_MEDIA_STATUS_RPT
 
- HW_VAR_H2C_PS_TUNE_PARAM
 
- HW_VAR_HANDLE_FW_C2H
 
- HW_VAR_HW_SEQ_ENABLE
 
- HW_VAR_INITIAL_GAIN
 
- HW_VAR_INIT_RTS_RATE
 
- HW_VAR_INIT_TX_RATE
 
- HW_VAR_INT_AC
 
- HW_VAR_INT_MIGRATION
 
- HW_VAR_IO_CMD
 
- HW_VAR_KEEP_ALIVE
 
- HW_VAR_LBK_MODE
 
- HW_VAR_LISTEN_INTERVAL
 
- HW_VAR_MACID_SLEEP
 
- HW_VAR_MACID_WAKEUP
 
- HW_VAR_MAC_ADDR
 
- HW_VAR_MAX_RX_AMPDU_FACTOR
 
- HW_VAR_MCS_RATE_AVAILABLE
 
- HW_VAR_MEDIA_STATUS
 
- HW_VAR_MEDIA_STATUS1
 
- HW_VAR_MGT_FILTER
 
- HW_VAR_MLME_DISCONNECT
 
- HW_VAR_MLME_JOIN
 
- HW_VAR_MLME_SITESURVEY
 
- HW_VAR_MRC
 
- HW_VAR_MULTICAST_REG
 
- HW_VAR_NAV_UPPER
 
- HW_VAR_OFF_RCR_AM
 
- HW_VAR_ON_RCR_AM
 
- HW_VAR_PCIE_STOP_TX_DMA
 
- HW_VAR_PORT_SWITCH
 
- HW_VAR_R2T_SIFS
 
- HW_VAR_RATE_FALLBACK_CONTROL
 
- HW_VAR_RATR_0
 
- HW_VAR_RCR
 
- HW_VAR_RESET_WFCRC
 
- HW_VAR_RESP_SIFS
 
- HW_VAR_RESUME_CLK_ON
 
- HW_VAR_RETRY_COUNT
 
- HW_VAR_RETRY_LIMIT
 
- HW_VAR_RF_2R_DISABLE
 
- HW_VAR_RF_OFF_BY_HW
 
- HW_VAR_RF_RECOVERY
 
- HW_VAR_RF_STATE
 
- HW_VAR_RF_TIMING
 
- HW_VAR_RF_TYPE
 
- HW_VAR_RPT_TIMER_SETTING
 
- HW_VAR_RPWM_TOG
 
- HW_VAR_RRSR
 
- HW_VAR_RXDMA_AGG_PG_TH
 
- HW_VAR_SECURITY_CONF
 
- HW_VAR_SEC_CFG
 
- HW_VAR_SEC_DK_CFG
 
- HW_VAR_SET_DEV_POWER
 
- HW_VAR_SET_OPMODE
 
- HW_VAR_SET_REQ_FW_PS
 
- HW_VAR_SET_RPWM
 
- HW_VAR_SHORTGI_DENSITY
 
- HW_VAR_SIFS
 
- HW_VAR_SLOT_TIME
 
- HW_VAR_SOUNDING_CLK
 
- HW_VAR_SOUNDING_ENTER
 
- HW_VAR_SOUNDING_FW_NDPA
 
- HW_VAR_SOUNDING_LEAVE
 
- HW_VAR_SOUNDING_RATE
 
- HW_VAR_SOUNDING_STATUS
 
- HW_VAR_STOP_SEND_BEACON
 
- HW_VAR_SWITCH_EPHY_WOWLAN
 
- HW_VAR_SWITCH_EPHY_WoWLAN
 
- HW_VAR_SYS_CLKR
 
- HW_VAR_TDLS_DONE_CH_SEN
 
- HW_VAR_TDLS_INIT_CH_SEN
 
- HW_VAR_TDLS_RS_RCR
 
- HW_VAR_TDLS_WRCR
 
- HW_VAR_TRIGGER_GPIO_0
 
- HW_VAR_TR_SWITCH
 
- HW_VAR_TSF_TIMER
 
- HW_VAR_TURBO_MODE
 
- HW_VAR_TXOPLIMIT
 
- HW_VAR_TXPAUSE
 
- HW_VAR_TX_RATE_REG
 
- HW_VAR_TX_RPT_MAX_MACID
 
- HW_VAR_TxOPLimit
 
- HW_VAR_USB_MODE
 
- HW_VAR_USB_RX_AGGR
 
- HW_VAR_USER_CONTROL_TURBO_MODE
 
- HW_VAR_WAKEUP_REASON
 
- HW_VAR_WF_CRC
 
- HW_VAR_WF_IS_MAC_ADDR
 
- HW_VAR_WF_MASK
 
- HW_VAR_WIRELESS_MODE
 
- HW_VAR_WOWLAN
 
- HW_VAR_WPA_CONFIG
 
- HW_VBUS_CHRG
 
- HW_VBUS_DISCHRG
 
- HW_VBUS_DRV
 
- HW_VERSION
 
- HW_VERSION_1
 
- HW_VERSION_2
 
- HW_VERSION_UNKNOWN
 
- HW_VER_MAJOR_MASK
 
- HW_VER_MAJOR_SHFT
 
- HW_VER_MASK
 
- HW_VER_MINOR_MASK
 
- HW_VER_MINOR_SHFT
 
- HW_VER_SPARROW_B0
 
- HW_VER_SPARROW_D0
 
- HW_VER_STEP_MASK
 
- HW_VER_TALYN
 
- HW_VER_TALYN_MB
 
- HW_VER_UNKNOWN
 
- HW_VF_HANDLE
 
- HW_VOL_COUNTER_MASTER
 
- HW_VOL_COUNTER_VOICE
 
- HW_WDFEED
 
- HW_WDMOD
 
- HW_WDTC
 
- HW_WDTCLKDIV
 
- HW_WDTCLKSEL
 
- HW_WDTCLKUEN
 
- HW_WDTV
 
- HW_WIN
 
- HW_YEAR
 
- HW_reset
 
- HWtype
 
- HX4700_ASIC3_GPIO_BASE
 
- HX4700_EGPIO_BASE
 
- HX4700_NR_IRQS
 
- HX711_GAIN_MAX
 
- HX8357B
 
- HX8357B_GAMMASET
 
- HX8357B_RDID1
 
- HX8357B_RDID2
 
- HX8357B_RDID3
 
- HX8357B_RDID4
 
- HX8357B_SETCABC
 
- HX8357B_SETDDB
 
- HX8357B_SETDGC
 
- HX8357B_SETDISPLAY
 
- HX8357B_SETDISPLAYFRAME
 
- HX8357B_SETDISPMODE
 
- HX8357B_SETGAMMA
 
- HX8357B_SETID
 
- HX8357B_SETOTP
 
- HX8357B_SETPANELRELATED
 
- HX8357B_SETPOWER
 
- HX8357B_SETPWRNORMAL
 
- HX8357B_SETVCOM
 
- HX8357B_SET_PANEL_DRIVING
 
- HX8357D
 
- HX8357D_MADCTL_BGR
 
- HX8357D_MADCTL_MH
 
- HX8357D_MADCTL_ML
 
- HX8357D_MADCTL_MV
 
- HX8357D_MADCTL_MX
 
- HX8357D_MADCTL_MY
 
- HX8357D_MADCTL_RGB
 
- HX8357D_SETC
 
- HX8357D_SETCOM
 
- HX8357D_SETCYC
 
- HX8357D_SETEXTC
 
- HX8357D_SETGAMMA
 
- HX8357D_SETOSC
 
- HX8357D_SETPANEL
 
- HX8357D_SETPOWER
 
- HX8357D_SETRGB
 
- HX8357D_SETSTBA
 
- HX8357_BLACK
 
- HX8357_BLUE
 
- HX8357_CYAN
 
- HX8357_ENTER_IDLE_MODE
 
- HX8357_ENTER_INVERSION_MODE
 
- HX8357_ENTER_NORMAL_MODE
 
- HX8357_ENTER_PARTIAL_MODE
 
- HX8357_ENTER_SLEEP_MODE
 
- HX8357_EXIT_IDLE_MODE
 
- HX8357_EXIT_INVERSION_MODE
 
- HX8357_EXIT_SLEEP_MODE
 
- HX8357_GET_BLUE_CHANNEL
 
- HX8357_GET_DIAGNOSTIC_RESULT
 
- HX8357_GET_DISPLAY_MODE
 
- HX8357_GET_GREEN_CHANNEL
 
- HX8357_GET_MADCTL
 
- HX8357_GET_PIXEL_FORMAT
 
- HX8357_GET_POWER_MODE
 
- HX8357_GET_RED_CHANNEL
 
- HX8357_GET_SCAN_LINES
 
- HX8357_GET_SIGNAL_MODE
 
- HX8357_GREEN
 
- HX8357_MAGENTA
 
- HX8357_NUM_IM_PINS
 
- HX8357_READ_DDB_START
 
- HX8357_READ_MEMORY_CONTINUE
 
- HX8357_READ_MEMORY_START
 
- HX8357_RED
 
- HX8357_SETOSC
 
- HX8357_SETPANEL
 
- HX8357_SETPWR1
 
- HX8357_SETRGB
 
- HX8357_SET_ADDRESS_MODE
 
- HX8357_SET_COLUMN_ADDRESS
 
- HX8357_SET_DISPLAY_FRAME
 
- HX8357_SET_DISPLAY_MODE
 
- HX8357_SET_DISPLAY_MODE_RGB_INTERFACE
 
- HX8357_SET_DISPLAY_MODE_RGB_THROUGH
 
- HX8357_SET_DISPLAY_OFF
 
- HX8357_SET_DISPLAY_ON
 
- HX8357_SET_GAMMA
 
- HX8357_SET_PAGE_ADDRESS
 
- HX8357_SET_PANEL_DRIVING
 
- HX8357_SET_PANEL_RELATED
 
- HX8357_SET_PARTIAL_AREA
 
- HX8357_SET_PIXEL_FORMAT
 
- HX8357_SET_PIXEL_FORMAT_DBI_16BIT
 
- HX8357_SET_PIXEL_FORMAT_DBI_18BIT
 
- HX8357_SET_PIXEL_FORMAT_DBI_3BIT
 
- HX8357_SET_PIXEL_FORMAT_DPI_16BIT
 
- HX8357_SET_PIXEL_FORMAT_DPI_18BIT
 
- HX8357_SET_PIXEL_FORMAT_DPI_3BIT
 
- HX8357_SET_POWER
 
- HX8357_SET_POWER_NORMAL
 
- HX8357_SET_RGB
 
- HX8357_SET_RGB_ENABLE_HIGH
 
- HX8357_SET_SCROLL_AREA
 
- HX8357_SET_SCROLL_START
 
- HX8357_SET_TEAR_OFF
 
- HX8357_SET_TEAR_ON
 
- HX8357_SET_TEAR_SCAN_LINES
 
- HX8357_SET_VCOM
 
- HX8357_SWRESET
 
- HX8357_TFTHEIGHT
 
- HX8357_TFTWIDTH
 
- HX8357_WHITE
 
- HX8357_WRITE_MEMORY_CONTINUE
 
- HX8357_WRITE_MEMORY_START
 
- HX8357_YELLOW
 
- HX8369_SET_DISPLAY_BRIGHTNESS
 
- HX8369_SET_DISPLAY_MODE
 
- HX8369_SET_DISPLAY_WAVEFORM_CYC
 
- HX8369_SET_EXTENSION_COMMAND
 
- HX8369_SET_GAMMA_CURVE_RELATED
 
- HX8369_SET_GIP
 
- HX8369_SET_POWER
 
- HX8369_SET_VCOM
 
- HX8369_WRITE_CABC_BRIGHT_CTRL
 
- HX8369_WRITE_CABC_DISPLAY_VALUE
 
- HX8369_WRITE_CABC_MIN_BRIGHTNESS
 
- HX_DMAP_DIRTY
 
- HX_PRT
 
- HX_REG
 
- HY29F002T
 
- HYDRA_ADDRPROM
 
- HYDRA_CPD_PD0
 
- HYDRA_CPD_PD1
 
- HYDRA_CPD_PD2
 
- HYDRA_CPD_PD3
 
- HYDRA_CPU_RESET_CHECK_OFFSET
 
- HYDRA_CPU_RESET_CHECK_REG
 
- HYDRA_CPU_RESET_DATA
 
- HYDRA_CPU_RESET_REG
 
- HYDRA_CRYSTAL_CAP
 
- HYDRA_CRYSTAL_SETTING
 
- HYDRA_DEMOD0_VERSION
 
- HYDRA_DEMOD1_VERSION
 
- HYDRA_DEMOD2_VERSION
 
- HYDRA_DEMOD3_VERSION
 
- HYDRA_DEMOD4_VERSION
 
- HYDRA_DEMOD5_VERSION
 
- HYDRA_DEMOD6_VERSION
 
- HYDRA_DEMOD7_VERSION
 
- HYDRA_DEMOD_0_BASE_ADDR
 
- HYDRA_DEMOD_STATUS_LOCK
 
- HYDRA_DEMOD_STATUS_UNLOCK
 
- HYDRA_DISABLE_CLK_1
 
- HYDRA_DISABLE_CLK_2
 
- HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET
 
- HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET
 
- HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET
 
- HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET
 
- HYDRA_DMD_DISPLAY_I_ADDR_OFFSET
 
- HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET
 
- HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET
 
- HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET
 
- HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET
 
- HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET
 
- HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET
 
- HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET
 
- HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET
 
- HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET
 
- HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET
 
- HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET
 
- HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET
 
- HYDRA_DMD_SNR_ADDR_OFFSET
 
- HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET
 
- HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET
 
- HYDRA_DMD_STANDARD_ADDR_OFFSET
 
- HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR
 
- HYDRA_DMD_STATUS_END_ADDR_OFFSET
 
- HYDRA_DMD_STATUS_INPUT_POWER_ADDR
 
- HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET
 
- HYDRA_DMD_STATUS_OFFSET
 
- HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET
 
- HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET
 
- HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET
 
- HYDRA_DMD_TUNER_ID_ADDR_OFFSET
 
- HYDRA_FC_ARB_BYPASS
 
- HYDRA_FC_MPIC_ENABLE
 
- HYDRA_FC_MPIC_IS_MASTER
 
- HYDRA_FC_RESET_SCC
 
- HYDRA_FC_SCCA_ENABLE
 
- HYDRA_FC_SCCB_ENABLE
 
- HYDRA_FC_SCC_CELL_EN
 
- HYDRA_FC_SCSI_CELL_EN
 
- HYDRA_FC_SLOW_SCC_PCLK
 
- HYDRA_FIRMWARE_PATCH_VERSION
 
- HYDRA_FIRMWARE_VERSION
 
- HYDRA_FIXED_PID_BANK_A_REG
 
- HYDRA_FIXED_PID_BANK_B_REG
 
- HYDRA_FW_RC_VERSION
 
- HYDRA_HEAR_BEAT
 
- HYDRA_INTR_MASK_REG
 
- HYDRA_INTR_STATUS_REG
 
- HYDRA_INT_ADB
 
- HYDRA_INT_ADB_NMI
 
- HYDRA_INT_EXT1
 
- HYDRA_INT_EXT2
 
- HYDRA_INT_EXT3
 
- HYDRA_INT_EXT4
 
- HYDRA_INT_EXT5
 
- HYDRA_INT_EXT6
 
- HYDRA_INT_EXT7
 
- HYDRA_INT_SCCA
 
- HYDRA_INT_SCCA_RX_DMA
 
- HYDRA_INT_SCCA_TX_DMA
 
- HYDRA_INT_SCCB
 
- HYDRA_INT_SCCB_RX_DMA
 
- HYDRA_INT_SCCB_TX_DMA
 
- HYDRA_INT_SCSI
 
- HYDRA_INT_SCSI_DMA
 
- HYDRA_INT_SIO
 
- HYDRA_INT_SPARE
 
- HYDRA_INT_VIA
 
- HYDRA_MODULES_CLK_1_REG
 
- HYDRA_MODULES_CLK_2_REG
 
- HYDRA_NIC_BASE
 
- HYDRA_PRCM_ROOT_CLK_DISABLE
 
- HYDRA_PRCM_ROOT_CLK_REG
 
- HYDRA_REGULAR_PID_BANK_A_REG
 
- HYDRA_REGULAR_PID_BANK_B_REG
 
- HYDRA_RESET_BBAND_DATA
 
- HYDRA_RESET_BBAND_REG
 
- HYDRA_RESET_TRANSPORT_FIFO_DATA
 
- HYDRA_RESET_TRANSPORT_FIFO_REG
 
- HYDRA_RESET_XBAR_DATA
 
- HYDRA_RESET_XBAR_REG
 
- HYDRA_SCLK
 
- HYDRA_SCLK_OE
 
- HYDRA_SDAT
 
- HYDRA_SDAT_OE
 
- HYDRA_SKU_ID_REG
 
- HYDRA_SKU_MGMT
 
- HYDRA_TEMPARATURE
 
- HYDRA_TS_CTRL_BASE_ADDR
 
- HYDRA_TUNER_0_BASE_ADDR
 
- HYDRA_TUNER_AGC_LOCK_OFFSET
 
- HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET
 
- HYDRA_TUNER_ENABLE_COMPLETE
 
- HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET
 
- HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET
 
- HYDRA_TUNER_SPECTRUM_STATUS_OFFSET
 
- HYDRA_TUNER_STATUS_OFFSET
 
- HYDRA_VERSION
 
- HYGON_MSR_RANGE
 
- HYM8563_ALM_BIT_DISABLE
 
- HYM8563_ALM_DAY
 
- HYM8563_ALM_HOUR
 
- HYM8563_ALM_MIN
 
- HYM8563_ALM_WEEK
 
- HYM8563_CLKOUT
 
- HYM8563_CLKOUT_1
 
- HYM8563_CLKOUT_1024
 
- HYM8563_CLKOUT_32
 
- HYM8563_CLKOUT_32768
 
- HYM8563_CLKOUT_ENABLE
 
- HYM8563_CLKOUT_MASK
 
- HYM8563_CTL1
 
- HYM8563_CTL1_STOP
 
- HYM8563_CTL1_TEST
 
- HYM8563_CTL1_TESTC
 
- HYM8563_CTL2
 
- HYM8563_CTL2_AF
 
- HYM8563_CTL2_AIE
 
- HYM8563_CTL2_TF
 
- HYM8563_CTL2_TIE
 
- HYM8563_CTL2_TI_TP
 
- HYM8563_DAY
 
- HYM8563_DAY_MASK
 
- HYM8563_HOUR
 
- HYM8563_HOUR_MASK
 
- HYM8563_MIN
 
- HYM8563_MIN_MASK
 
- HYM8563_MONTH
 
- HYM8563_MONTH_CENTURY
 
- HYM8563_MONTH_MASK
 
- HYM8563_SEC
 
- HYM8563_SEC_MASK
 
- HYM8563_SEC_VL
 
- HYM8563_TMR_CNT
 
- HYM8563_TMR_CTL
 
- HYM8563_TMR_CTL_1
 
- HYM8563_TMR_CTL_1_60
 
- HYM8563_TMR_CTL_4096
 
- HYM8563_TMR_CTL_64
 
- HYM8563_TMR_CTL_ENABLE
 
- HYM8563_TMR_CTL_MASK
 
- HYM8563_WEEKDAY
 
- HYM8563_WEEKDAY_MASK
 
- HYM8563_YEAR
 
- HYNIX
 
- HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE
 
- HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE
 
- HYPERBOWL_MODE2_8_24
 
- HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES
 
- HYPERCALL
 
- HYPERCALL0
 
- HYPERCALL1
 
- HYPERCALL2
 
- HYPERCALL3
 
- HYPERCALL4
 
- HYPERCALL5
 
- HYPERCALL_SIMPLE
 
- HYPERFLASH
 
- HYPERRAM
 
- HYPERSPARC_ACENABLE
 
- HYPERSPARC_BMODE
 
- HYPERSPARC_CENABLE
 
- HYPERSPARC_CMODE
 
- HYPERSPARC_CSIZE
 
- HYPERSPARC_CWENABLE
 
- HYPERSPARC_ICCR_FTD
 
- HYPERSPARC_ICCR_ICE
 
- HYPERSPARC_MENABLE
 
- HYPERSPARC_MIDMASK
 
- HYPERSPARC_MRFLCT
 
- HYPERSPARC_NFAULT
 
- HYPERSPARC_SBENABLE
 
- HYPERSPARC_WBENABLE
 
- HYPERVISOR_ATTR_RO
 
- HYPERVISOR_ATTR_RW
 
- HYPERVISOR_CALLBACK_VECTOR
 
- HYPERVISOR_TEXT
 
- HYPERVISOR_VIRT_START
 
- HYPERVISOR_callback_op
 
- HYPERVISOR_console_io
 
- HYPERVISOR_dm_op
 
- HYPERVISOR_event_channel_op
 
- HYPERVISOR_get_debugreg
 
- HYPERVISOR_grant_table_op
 
- HYPERVISOR_hvm_op
 
- HYPERVISOR_mca
 
- HYPERVISOR_memory_op
 
- HYPERVISOR_mmu_update
 
- HYPERVISOR_mmuext_op
 
- HYPERVISOR_multicall
 
- HYPERVISOR_physdev_op
 
- HYPERVISOR_platform_op
 
- HYPERVISOR_sched_op
 
- HYPERVISOR_set_debugreg
 
- HYPERVISOR_set_gdt
 
- HYPERVISOR_set_segment_base
 
- HYPERVISOR_set_timer_op
 
- HYPERVISOR_set_trap_table
 
- HYPERVISOR_suspend
 
- HYPERVISOR_tmem_op
 
- HYPERVISOR_update_descriptor
 
- HYPERVISOR_update_va_mapping
 
- HYPERVISOR_vcpu_op
 
- HYPERVISOR_vm_assist
 
- HYPERVISOR_xen_version
 
- HYPERVISOR_xenpmu_op
 
- HYPERV_CPUID_ENLIGHTMENT_INFO
 
- HYPERV_CPUID_FEATURES
 
- HYPERV_CPUID_IMPLEMENT_LIMITS
 
- HYPERV_CPUID_INTERFACE
 
- HYPERV_CPUID_MAX
 
- HYPERV_CPUID_MIN
 
- HYPERV_CPUID_NESTED_FEATURES
 
- HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS
 
- HYPERV_CPUID_VERSION
 
- HYPERV_HYPERVISOR_PRESENT_BIT
 
- HYPERV_REENLIGHTENMENT_VECTOR
 
- HYPERV_STIMER0_VECTOR
 
- HYPER_CMAP24
 
- HYPER_CMAP8
 
- HYPER_CMAP_TYPE
 
- HYPER_CONFIG_PLANES_24
 
- HYPER_ENABLE_DISABLE_DISPLAY
 
- HYPER_PAV
 
- HYPER_STREAM_ID_EN_CFG
 
- HYPFS_DIAG304
 
- HYPFS_IOCTL_MAGIC
 
- HYPFS_MAGIC
 
- HYP_MODE
 
- HYSDN_CARD
 
- HYSDN_DEFS_H
 
- HYSDN_MAXVERSION
 
- HYSDN_MAX_CAPI_SKB
 
- HYST
 
- HYSTART_ACK_TRAIN
 
- HYSTART_DELAY
 
- HYSTART_DELAY_MAX
 
- HYSTART_DELAY_MIN
 
- HYSTART_DELAY_THRESH
 
- HYSTART_MIN_SAMPLES
 
- HYSTERESIS_DEFAULT
 
- HYSTERSIS
 
- HYSTTHRESH
 
- HYST_FROM_REG
 
- HYST_TO_REG
 
- HZ
 
- HZIP_ALG_PRIORITY
 
- HZIP_ALG_TYPE_COMP
 
- HZIP_ALG_TYPE_DECOMP
 
- HZIP_ALG_TYPE_GZIP
 
- HZIP_ALG_TYPE_ZLIB
 
- HZIP_BD_RUSER_32_63
 
- HZIP_BD_STATUS_M
 
- HZIP_BD_WUSER_32_63
 
- HZIP_BUF_SIZE
 
- HZIP_BUF_TYPE_M
 
- HZIP_CLEAR_ENABLE
 
- HZIP_CLOCK_GATE_CTRL
 
- HZIP_COMP_CORE0
 
- HZIP_COMP_CORE1
 
- HZIP_COMP_CORE_NUM
 
- HZIP_CORE_DEBUG_COMP_0
 
- HZIP_CORE_DEBUG_COMP_1
 
- HZIP_CORE_DEBUG_DECOMP_0
 
- HZIP_CORE_DEBUG_DECOMP_1
 
- HZIP_CORE_DEBUG_DECOMP_2
 
- HZIP_CORE_DEBUG_DECOMP_3
 
- HZIP_CORE_DEBUG_DECOMP_4
 
- HZIP_CORE_DEBUG_DECOMP_5
 
- HZIP_CORE_INT_DISABLE
 
- HZIP_CORE_INT_MASK
 
- HZIP_CORE_INT_SOURCE
 
- HZIP_CORE_INT_STATUS
 
- HZIP_CORE_INT_STATUS_M_ECC
 
- HZIP_CORE_NUM
 
- HZIP_CORE_SRAM_ECC_ERR_INFO
 
- HZIP_CTX_Q_NUM
 
- HZIP_CURRENT_QM
 
- HZIP_DATA_RUSER_32_63
 
- HZIP_DATA_WUSER_32_63
 
- HZIP_DEBUG_FILE_NUM
 
- HZIP_DECOMP_CORE0
 
- HZIP_DECOMP_CORE1
 
- HZIP_DECOMP_CORE2
 
- HZIP_DECOMP_CORE3
 
- HZIP_DECOMP_CORE4
 
- HZIP_DECOMP_CORE5
 
- HZIP_DECOMP_CORE_NUM
 
- HZIP_FSM_MAX_CNT
 
- HZIP_GZIP_HEAD_BUF
 
- HZIP_GZIP_HEAD_SIZE
 
- HZIP_IN_SGE_DATA_OFFSET_M
 
- HZIP_NC_ERR
 
- HZIP_NUMA_DISTANCE
 
- HZIP_OUT_SGE_DATA_OFFSET_M
 
- HZIP_PBUFFER
 
- HZIP_PF_DEF_Q_BASE
 
- HZIP_PF_DEF_Q_NUM
 
- HZIP_PORT_ARCA_CHE_0
 
- HZIP_PORT_ARCA_CHE_1
 
- HZIP_PORT_AWCA_CHE_0
 
- HZIP_PORT_AWCA_CHE_1
 
- HZIP_QM_IDEL_STATUS
 
- HZIP_QUEUE_NUM_V1
 
- HZIP_QUEUE_NUM_V2
 
- HZIP_REQ_TYPE_M
 
- HZIP_SGL
 
- HZIP_SGL_RUSER_32_63
 
- HZIP_SOFT_CTRL_CNT_CLR_CE
 
- HZIP_SQE_SIZE
 
- HZIP_SQ_SIZE
 
- HZIP_VF_NUM
 
- HZIP_ZLIB_HEAD_SIZE
 
- HZSCALE
 
- HZ_PER_MHZ
 
- HZ_TO_MHZ
 
- HZ_TO_NANOSECONDS
 
- HZ_TO_PS
 
- H_16G_CACHE_INDEX
 
- H_16M_CACHE_INDEX
 
- H_ABORT
 
- H_ACT
 
- H_ACTIVE
 
- H_ACTIVE_HI
 
- H_ACTIVE_LO
 
- H_ACTIVE_MASK
 
- H_ACTIVE_SHIFT
 
- H_ADAPTER_PARM
 
- H_ADDR_INDEX
 
- H_ADD_CONN
 
- H_ADD_LOGICAL_LAN_BUFFER
 
- H_ALIAS_EXIST
 
- H_ALIGN
 
- H_ALIGN_SINK
 
- H_ALIGN_SRC
 
- H_ALLOC_HEA_RESOURCE
 
- H_ALLOC_RESOURCE
 
- H_ALL_RES_EQ_ACT_EQE
 
- H_ALL_RES_EQ_ACT_EQ_IST_1
 
- H_ALL_RES_EQ_ACT_EQ_IST_2
 
- H_ALL_RES_EQ_ACT_EQ_IST_3
 
- H_ALL_RES_EQ_ACT_EQ_IST_4
 
- H_ALL_RES_EQ_ACT_EQ_IST_C
 
- H_ALL_RES_EQ_ACT_PS
 
- H_ALL_RES_EQ_INH_EQE_GEN
 
- H_ALL_RES_EQ_LIOBN
 
- H_ALL_RES_EQ_MAX_EQE
 
- H_ALL_RES_EQ_NEQ
 
- H_ALL_RES_EQ_NON_NEQ_ISN
 
- H_ALL_RES_EQ_RES_TYPE
 
- H_ALL_RES_QP_ACT_R1SGE
 
- H_ALL_RES_QP_ACT_R1WQE
 
- H_ALL_RES_QP_ACT_R2SGE
 
- H_ALL_RES_QP_ACT_R2WQE
 
- H_ALL_RES_QP_ACT_R3SGE
 
- H_ALL_RES_QP_ACT_R3WQE
 
- H_ALL_RES_QP_ACT_SSGE
 
- H_ALL_RES_QP_ACT_SWQE
 
- H_ALL_RES_QP_ACT_SWQE_IDL
 
- H_ALL_RES_QP_DMA128
 
- H_ALL_RES_QP_EQEG
 
- H_ALL_RES_QP_EQPO
 
- H_ALL_RES_QP_HSM
 
- H_ALL_RES_QP_LIOBN_RQ1
 
- H_ALL_RES_QP_LIOBN_RQ2
 
- H_ALL_RES_QP_LIOBN_RQ3
 
- H_ALL_RES_QP_LIOBN_SQ
 
- H_ALL_RES_QP_LL_QP
 
- H_ALL_RES_QP_MAX_R1SGE
 
- H_ALL_RES_QP_MAX_R1WQE
 
- H_ALL_RES_QP_MAX_R2SGE
 
- H_ALL_RES_QP_MAX_R2WQE
 
- H_ALL_RES_QP_MAX_R3SGE
 
- H_ALL_RES_QP_MAX_R3WQE
 
- H_ALL_RES_QP_MAX_SSGE
 
- H_ALL_RES_QP_MAX_SWQE
 
- H_ALL_RES_QP_PD
 
- H_ALL_RES_QP_PORT_NUM
 
- H_ALL_RES_QP_QPP
 
- H_ALL_RES_QP_RES_TYP
 
- H_ALL_RES_QP_RQR
 
- H_ALL_RES_QP_SIGT
 
- H_ALL_RES_QP_SIZE_RQ1
 
- H_ALL_RES_QP_SIZE_RQ2
 
- H_ALL_RES_QP_SIZE_RQ3
 
- H_ALL_RES_QP_SIZE_SQ
 
- H_ALL_RES_QP_SWQE_IDL
 
- H_ALL_RES_QP_TENURE
 
- H_ALL_RES_QP_TH_RQ2
 
- H_ALL_RES_QP_TH_RQ3
 
- H_ALL_RES_QP_TOKEN
 
- H_ALL_RES_TYPE_CQ
 
- H_ALL_RES_TYPE_EQ
 
- H_ALL_RES_TYPE_MR
 
- H_ALL_RES_TYPE_MW
 
- H_ALL_RES_TYPE_QP
 
- H_ALT_TABLE
 
- H_ANDCOND
 
- H_ASR_OFF
 
- H_ASR_ON
 
- H_ATTACH_CA_PROCESS
 
- H_ATTACH_MCQP
 
- H_ATTR_PARM
 
- H_AUTHORITY
 
- H_AVPN
 
- H_BAD_CCB_OR_SG
 
- H_BAD_DATA
 
- H_BAD_MODE
 
- H_BAD_TARGET_DIR
 
- H_BEST_ENERGY
 
- H_BLANKING
 
- H_BLANKING_HI
 
- H_BLANKING_LO
 
- H_BLANKSCALE
 
- H_BLANK_END_INDEX
 
- H_BLANK_END_SHADOW_INDEX
 
- H_BLANK_START_INDEX
 
- H_BLOCK_REMOVE
 
- H_BORDER
 
- H_BULK_REMOVE
 
- H_BULK_REMOVE_ABSOLUTE
 
- H_BULK_REMOVE_ANDCOND
 
- H_BULK_REMOVE_AVPN
 
- H_BULK_REMOVE_CODE
 
- H_BULK_REMOVE_END
 
- H_BULK_REMOVE_FLAGS
 
- H_BULK_REMOVE_HW
 
- H_BULK_REMOVE_MAX_BATCH
 
- H_BULK_REMOVE_NOT_FOUND
 
- H_BULK_REMOVE_PARM
 
- H_BULK_REMOVE_PTEX
 
- H_BULK_REMOVE_RC
 
- H_BULK_REMOVE_REQUEST
 
- H_BULK_REMOVE_RESPONSE
 
- H_BULK_REMOVE_SUCCESS
 
- H_BULK_REMOVE_TYPE
 
- H_BUSY
 
- H_CBD
 
- H_CBRP
 
- H_CBWP
 
- H_CB_ALIGNMENT
 
- H_CB_WW
 
- H_CEDE
 
- H_CHANGE_LOGICAL_LAN_MAC
 
- H_CIF
 
- H_CLEAR_HPT
 
- H_CLEAR_MOD
 
- H_CLEAR_REF
 
- H_CLOSED
 
- H_COALESCE_CAND
 
- H_COLLECT_CA_INT_INFO
 
- H_CONFER
 
- H_CONSTRAINED
 
- H_CONTINUE
 
- H_CONTROL_CA_FACILITY
 
- H_CONTROL_CA_FACILITY_COLLECT_VPD
 
- H_CONTROL_CA_FACILITY_RESET
 
- H_CONTROL_CA_FAULTS
 
- H_CONTROL_CA_FAULTS_RESPOND_AFU
 
- H_CONTROL_CA_FAULTS_RESPOND_PSL
 
- H_CONTROL_CA_FUNCTION
 
- H_CONTROL_CA_FUNCTION_ACK_FUNCTION_ERR_INT
 
- H_CONTROL_CA_FUNCTION_COLLECT_VPD
 
- H_CONTROL_CA_FUNCTION_GET_AFU_ERR
 
- H_CONTROL_CA_FUNCTION_GET_CONFIG
 
- H_CONTROL_CA_FUNCTION_GET_DOWNLOAD_STATE
 
- H_CONTROL_CA_FUNCTION_GET_ERROR_LOG
 
- H_CONTROL_CA_FUNCTION_GET_FUNCTION_ERR_INT
 
- H_CONTROL_CA_FUNCTION_READ_ERR_STATE
 
- H_CONTROL_CA_FUNCTION_RESET
 
- H_CONTROL_CA_FUNCTION_RESUME_PROCESS
 
- H_CONTROL_CA_FUNCTION_SUSPEND_PROCESS
 
- H_CONTROL_CA_FUNCTION_TERMINATE_PROCESS
 
- H_COP
 
- H_COPY_PAGE
 
- H_COPY_RDMA
 
- H_COPY_TOFROM_GUEST
 
- H_COP_HW
 
- H_CPPR
 
- H_CPU_BEHAV_BNDS_CHK_SPEC_BAR
 
- H_CPU_BEHAV_FAVOUR_SECURITY
 
- H_CPU_BEHAV_FLUSH_COUNT_CACHE
 
- H_CPU_BEHAV_L1D_FLUSH_PR
 
- H_CPU_CHAR_BCCTRL_SERIALISED
 
- H_CPU_CHAR_BCCTR_FLUSH_ASSIST
 
- H_CPU_CHAR_BRANCH_HINTS_HONORED
 
- H_CPU_CHAR_COUNT_CACHE_DISABLED
 
- H_CPU_CHAR_L1D_FLUSH_ORI30
 
- H_CPU_CHAR_L1D_FLUSH_TRIG2
 
- H_CPU_CHAR_L1D_THREAD_PRIV
 
- H_CPU_CHAR_SPEC_BAR_ORI31
 
- H_CPU_CHAR_THREAD_RECONFIG_CTRL
 
- H_CREATE_RPT
 
- H_CSR
 
- H_CSR_IE_MASK
 
- H_CSR_IS_MASK
 
- H_CUT_VERSION
 
- H_D0I3C
 
- H_D0I3C_CIP
 
- H_D0I3C_I3
 
- H_D0I3C_IE
 
- H_D0I3C_IR
 
- H_D0I3C_IS
 
- H_D0I3C_RR
 
- H_DDA_INC
 
- H_DEFINE_AQP0
 
- H_DEFINE_AQP1
 
- H_DEL_CONN
 
- H_DEREG_BCMC
 
- H_DEST_PARM
 
- H_DETACH_CA_PROCESS
 
- H_DETACH_MCQP
 
- H_DIRECTION
 
- H_DISABLE_ALL_VIO_INTS
 
- H_DISABLE_AND_GETC
 
- H_DISABLE_AND_GET_HEA
 
- H_DISABLE_GET_EHEA_WQE_P
 
- H_DISABLE_GET_RQC
 
- H_DISABLE_GET_SQ_WQE_P
 
- H_DISABLE_MIGRATION
 
- H_DISABLE_VIO_INTERRUPT
 
- H_DOWNLOAD_CA_FACILITY
 
- H_DOWNLOAD_CA_FACILITY_DOWNLOAD
 
- H_DOWNLOAD_CA_FACILITY_VALIDATE
 
- H_DOWNLOAD_CA_FUNCTION
 
- H_DROPPED
 
- H_DUPLICATE_CCB
 
- H_ENABLE_CRQ
 
- H_ENABLE_MIGRATION
 
- H_ENABLE_PREPARE_FOR_SUSPEND
 
- H_ENABLE_VIO_INTERRUPT
 
- H_ENTER
 
- H_ENTER_NESTED
 
- H_EOI
 
- H_EQ_PARM
 
- H_ERROR_DATA
 
- H_EXACT
 
- H_EXP_3_OVER_2
 
- H_EXP_9_OVER_8
 
- H_EXP_OFF
 
- H_FILTER
 
- H_FREE_CRQ
 
- H_FREE_LOGICAL_LAN
 
- H_FREE_LOGICAL_LAN_BUFFER
 
- H_FREE_RESOURCE
 
- H_FREE_SUB_CRQ
 
- H_FREE_VTERM
 
- H_FRE_2N
 
- H_FUNCTION
 
- H_GET_24X7_CATALOG_PAGE
 
- H_GET_24X7_DATA
 
- H_GET_CPU_CHARACTERISTICS
 
- H_GET_EM_PARMS
 
- H_GET_HCA_INFO
 
- H_GET_HEA_INFO
 
- H_GET_ILLAN_NUM_VLAN_IDS
 
- H_GET_ILLAN_SWITCH_ID
 
- H_GET_ILLAN_VLAN_ID_LIST
 
- H_GET_MPP
 
- H_GET_MPP_X
 
- H_GET_PARTNER_INFO
 
- H_GET_PARTNER_WWPN_LIST
 
- H_GET_PERF_COUNT
 
- H_GET_PERF_COUNTER_INFO
 
- H_GET_PPP
 
- H_GET_SESSION_TOKEN
 
- H_GET_TCE
 
- H_GET_TERM_CHAR
 
- H_GET_TRACE_BUFFER
 
- H_GET_VIOA_DUMP
 
- H_GET_VIOA_DUMP_SIZE
 
- H_GRADIENT
 
- H_HARDWARE
 
- H_HOME_NODE_ASSOCIATIVITY
 
- H_HPG_CSR
 
- H_HPG_CSR_PGI
 
- H_HPG_CSR_PGIHEXR
 
- H_HYPERVISOR_DATA
 
- H_ICACHE_INVALIDATE
 
- H_ICACHE_SYNCHRONIZE
 
- H_IE
 
- H_IG
 
- H_ILLAN_ATTRIBUTES
 
- H_INTERRUPT
 
- H_INT_ESB
 
- H_INT_GET_OS_REPORTING_LINE
 
- H_INT_GET_QUEUE_CONFIG
 
- H_INT_GET_QUEUE_INFO
 
- H_INT_GET_SOURCE_CONFIG
 
- H_INT_GET_SOURCE_INFO
 
- H_INT_RESET
 
- H_INT_SET_OS_REPORTING_LINE
 
- H_INT_SET_QUEUE_CONFIG
 
- H_INT_SET_SOURCE_CONFIG
 
- H_INT_SYNC
 
- H_INVALID_CCB_OP
 
- H_IN_PROGRESS
 
- H_IPI
 
- H_IPOLL
 
- H_IS
 
- H_IS_LONG_BUSY
 
- H_JFS_XATTR
 
- H_JOIN
 
- H_KERN_IO_END
 
- H_KERN_IO_SIZE
 
- H_KERN_IO_START
 
- H_KERN_MAP_SIZE
 
- H_KERN_VIRT_START
 
- H_LARGE_PAGE
 
- H_LINK_CCB_BAD
 
- H_LOCAL
 
- H_LOGICAL_CACHE_LOAD
 
- H_LOGICAL_CACHE_STORE
 
- H_LOGICAL_CI_LOAD
 
- H_LOGICAL_CI_STORE
 
- H_LOGICAL_DCBF
 
- H_LOGICAL_ICBI
 
- H_LONG_BUSY_END_RANGE
 
- H_LONG_BUSY_ORDER_100_MSEC
 
- H_LONG_BUSY_ORDER_100_SEC
 
- H_LONG_BUSY_ORDER_10_MSEC
 
- H_LONG_BUSY_ORDER_10_SEC
 
- H_LONG_BUSY_ORDER_1_MSEC
 
- H_LONG_BUSY_ORDER_1_SEC
 
- H_LONG_BUSY_START_RANGE
 
- H_MANAGE_TRACE
 
- H_MASK_PARM
 
- H_MAXPACKET
 
- H_MAX_RATE
 
- H_MCG_FULL
 
- H_MCG_PARM
 
- H_MEHEAPORT_CAT
 
- H_MEHEAPORT_PN
 
- H_MEM_ACCESS_PARM
 
- H_MEM_PARM
 
- H_MIGRATE_DMA
 
- H_MIN_RATE
 
- H_MIRROR_EN
 
- H_MLENGTH_PARM
 
- H_MODIFY_HEA_PORT
 
- H_MODIFY_HEA_QP
 
- H_MODIFY_PORT
 
- H_MODIFY_QP
 
- H_MR_CONDITION
 
- H_MULTICAST_CTRL
 
- H_MULTI_THREADS_ACTIVE
 
- H_N
 
- H_NOT_ACTIVE
 
- H_NOT_AVAILABLE
 
- H_NOT_ENOUGH_RESOURCES
 
- H_NOT_FOUND
 
- H_NO_MEM
 
- H_OFFSET
 
- H_OF_PORT_A
 
- H_OF_PORT_H
 
- H_OP_MODE
 
- H_OUTSTANDING_COP_OPS
 
- H_OVERLAP
 
- H_OVER_UNDER_RUN
 
- H_P2
 
- H_P3
 
- H_P4
 
- H_P5
 
- H_P6
 
- H_P7
 
- H_P8
 
- H_P9
 
- H_PAGE_4K_PFN
 
- H_PAGE_BUSY
 
- H_PAGE_COMBO
 
- H_PAGE_F_GIX
 
- H_PAGE_F_GIX_SHIFT
 
- H_PAGE_F_SECOND
 
- H_PAGE_HASHPTE
 
- H_PAGE_INIT
 
- H_PAGE_REGISTERED
 
- H_PAGE_SET_ACTIVE
 
- H_PAGE_SET_LOANED
 
- H_PAGE_SET_UNUSED
 
- H_PAGE_STATE_CHANGE
 
- H_PAGE_THP_HUGE
 
- H_PAGE_UNUSED
 
- H_PARAMETER
 
- H_PARTIAL
 
- H_PARTIAL_STORE
 
- H_PENDING
 
- H_PERFMON
 
- H_PERMISSION
 
- H_PGD_INDEX_SIZE
 
- H_PGD_TABLE_SIZE
 
- H_PGTABLE_EADDR_SIZE
 
- H_PGTABLE_RANGE
 
- H_PIC
 
- H_PI_SHIFT_VAL
 
- H_PMD_BAD_BITS
 
- H_PMD_FRAG_NR
 
- H_PMD_FRAG_SIZE_SHIFT
 
- H_PMD_INDEX_SIZE
 
- H_PMD_TABLE_SIZE
 
- H_POLL_PENDING
 
- H_PORT_CB0
 
- H_PORT_CB0_ALL
 
- H_PORT_CB0_DEFQPNARRAY
 
- H_PORT_CB0_MAC
 
- H_PORT_CB0_PRC
 
- H_PORT_CB1
 
- H_PORT_CB1_ALL
 
- H_PORT_CB2
 
- H_PORT_CB2_ALL
 
- H_PORT_CB3
 
- H_PORT_CB4
 
- H_PORT_CB4_ALL
 
- H_PORT_CB4_JUMBO
 
- H_PORT_CB4_SPEED
 
- H_PORT_CB5
 
- H_PORT_CB5_RCU
 
- H_PORT_CB6
 
- H_PORT_CB6_ALL
 
- H_PORT_CB7
 
- H_PORT_CB7_DUCQPN
 
- H_PORT_PARM
 
- H_POSITION
 
- H_POS_UNIT
 
- H_PP1
 
- H_PP2
 
- H_PRESCALED_SIZE
 
- H_PRIVILEGE
 
- H_PROD
 
- H_PROTECT
 
- H_PTEG_FULL
 
- H_PTE_FRAG_NR
 
- H_PTE_FRAG_SIZE_SHIFT
 
- H_PTE_INDEX_SIZE
 
- H_PTE_NONE_MASK
 
- H_PTE_PKEY
 
- H_PTE_PKEY_BIT0
 
- H_PTE_PKEY_BIT1
 
- H_PTE_PKEY_BIT2
 
- H_PTE_PKEY_BIT3
 
- H_PTE_PKEY_BIT4
 
- H_PTE_TABLE_SIZE
 
- H_PUD_BAD_BITS
 
- H_PUD_CACHE_INDEX
 
- H_PUD_INDEX_SIZE
 
- H_PUD_TABLE_SIZE
 
- H_PULSE0_ENABLE
 
- H_PULSE1_ENABLE
 
- H_PULSE2_ENABLE
 
- H_PURR
 
- H_PUT_TCE
 
- H_PUT_TCE_INDIRECT
 
- H_PUT_TERM_CHAR
 
- H_P_COUNTER
 
- H_QCIF
 
- H_QPCB0_ALL
 
- H_QPCB0_MAX_RWQE
 
- H_QPCB0_MAX_SWQE
 
- H_QPCB0_PORT_NB
 
- H_QPCB0_QP_AER
 
- H_QPCB0_QP_CTL_REG
 
- H_QPCB0_QP_TENURE
 
- H_QPCB1_ALL
 
- H_QPCB1_ASYN_EV_EQ_NB
 
- H_QPCB1_QPN
 
- H_QPCB1_RQ_CQ_HANDLE
 
- H_QPCB1_SGEL_NB_RQ1
 
- H_QPCB1_SGEL_NB_RQ2
 
- H_QPCB1_SGEL_NB_RQ3
 
- H_QPCB1_SGEL_NB_SQ
 
- H_QPCB1_SQ_CQ_HANDLE
 
- H_QP_CR_ENABLED
 
- H_QP_CR_RES_STATE
 
- H_QP_CR_STATE_ERROR
 
- H_QP_CR_STATE_INITIALIZED
 
- H_QP_CR_STATE_RDY2RCV
 
- H_QP_CR_STATE_RDY2SND
 
- H_QP_CR_STATE_RESET
 
- H_QUERY_HCA
 
- H_QUERY_HEA
 
- H_QUERY_HEA_PORT
 
- H_QUERY_HEA_QP
 
- H_QUERY_INT_STATE
 
- H_QUERY_MR
 
- H_QUERY_MW
 
- H_QUERY_PORT
 
- H_QUERY_QP
 
- H_QXL_DEV
 
- H_RANDOM
 
- H_RCQ_PARM
 
- H_RDY
 
- H_READ
 
- H_READY_FOR_SUSPEND
 
- H_READ_4
 
- H_REAL_TO_LOGICAL
 
- H_REGBCMC_MACADDR
 
- H_REGBCMC_PN
 
- H_REGBCMC_REGTYPE
 
- H_REGBCMC_VLANID
 
- H_REGISTER_HEA_RPAGES
 
- H_REGISTER_LOGICAL_LAN
 
- H_REGISTER_PROC_TBL
 
- H_REGISTER_RPAGES
 
- H_REGISTER_SMR
 
- H_REGISTER_VPA
 
- H_REGISTER_VTERM
 
- H_REG_BCMC
 
- H_REG_CRQ
 
- H_REG_RPAGE_PAGE_SIZE
 
- H_REG_RPAGE_QT
 
- H_REG_SUB_CRQ
 
- H_REMOTE_PARM
 
- H_REMOVE
 
- H_REMOVE_RPT
 
- H_REQUEST_VMC
 
- H_REREGISTER_PMR
 
- H_RESCINDED
 
- H_RESERVED_DABR
 
- H_RESET_EVENTS
 
- H_RESIZE_HPT_COMMIT
 
- H_RESIZE_HPT_PREPARE
 
- H_RESIZE_MR
 
- H_RESOURCE
 
- H_RH_PARM
 
- H_RST
 
- H_RTAS
 
- H_RT_PARM
 
- H_R_STATE
 
- H_R_XLATE
 
- H_SCALEFACTOR
 
- H_SCM_BIND_MEM
 
- H_SCM_HEALTH
 
- H_SCM_PERFORMANCE_STATS
 
- H_SCM_QUERY_BLOCK_MEM_BINDING
 
- H_SCM_QUERY_LOGICAL_MEM_BINDING
 
- H_SCM_READ_METADATA
 
- H_SCM_UNBIND_ALL
 
- H_SCM_UNBIND_MEM
 
- H_SCM_WRITE_METADATA
 
- H_SCQ_PARM
 
- H_SEL_TIMEOUT
 
- H_SEND_CRQ
 
- H_SEND_LOGICAL_LAN
 
- H_SEND_SUB_CRQ
 
- H_SEND_SUB_CRQ_INDIRECT
 
- H_SESSION_ERR_DETECTED
 
- H_SET_ASR
 
- H_SET_DABR
 
- H_SET_MODE
 
- H_SET_MODE_RESOURCE_ADDR_TRANS_MODE
 
- H_SET_MODE_RESOURCE_LE
 
- H_SET_MODE_RESOURCE_SET_CIABR
 
- H_SET_MODE_RESOURCE_SET_DAWR
 
- H_SET_MPP
 
- H_SET_PARTITION_TABLE
 
- H_SET_PPP
 
- H_SET_SPRG0
 
- H_SET_XDABR
 
- H_SG_LIST
 
- H_SHIFT_VAL
 
- H_SIGNAL_SYS_RESET
 
- H_SIGNAL_SYS_RESET_ALL
 
- H_SIGNAL_SYS_RESET_ALL_OTHERS
 
- H_SIGT_PARM
 
- H_SIZE
 
- H_SIZE_HI
 
- H_SIZE_LO
 
- H_SOURCE_PARM
 
- H_SPEED_100M_F
 
- H_SPEED_100M_H
 
- H_SPEED_10G_F
 
- H_SPEED_10M_F
 
- H_SPEED_10M_H
 
- H_SPEED_1G_F
 
- H_START
 
- H_STATE
 
- H_STATE_DISABLE
 
- H_STATE_NORMAL
 
- H_STATE_PERM_UNAVAILABLE
 
- H_STATE_TEMP_UNAVAILABLE
 
- H_STATUS_GOOD
 
- H_STUFF_TCE
 
- H_ST_PARM
 
- H_SUCCESS
 
- H_SXGA
 
- H_SYNC_END_INDEX
 
- H_SYNC_OFFSET
 
- H_SYNC_OFFSET_HI
 
- H_SYNC_OFFSET_LO
 
- H_SYNC_PERCENT
 
- H_SYNC_START_INDEX
 
- H_SYNC_WIDTH
 
- H_SYNC_WIDTH_HI
 
- H_SYNC_WIDTH_LO
 
- H_TABLE_FULL
 
- H_TABLE_POS1
 
- H_TABLE_POS2
 
- H_TARGET_PHASE_F
 
- H_TIMING_DIV_BY2
 
- H_TIMING_NO_DIV
 
- H_TLBIE_P1_ENC
 
- H_TLB_INVALIDATE
 
- H_TOKEN_PARM
 
- H_TOO_BIG
 
- H_TOO_HARD
 
- H_TOTAL
 
- H_TOTAL_INDEX
 
- H_TOTAL_SHADOW_INDEX
 
- H_TRACE_PARM
 
- H_TSIZE_PARM
 
- H_TST_J
 
- H_TST_K
 
- H_TST_NORMAL
 
- H_TST_PACKET
 
- H_TST_SE0_NAK
 
- H_UBRLCR_BREAK
 
- H_UBRLCR_FIFO
 
- H_UBRLCR_PARENB
 
- H_UBRLCR_PAREVN
 
- H_UBRLCR_STOPB
 
- H_UDI
 
- H_UNBIND_SCOPE_ALL
 
- H_UNBIND_SCOPE_DRC
 
- H_UNEXP_BUS_FREE
 
- H_UNSUPPORTED
 
- H_UNSUPPORTED_FLAG_END
 
- H_UNSUPPORTED_FLAG_START
 
- H_VASI_ABORTED
 
- H_VASI_COMPLETED
 
- H_VASI_ENABLED
 
- H_VASI_INVALID
 
- H_VASI_RESUMED
 
- H_VASI_STATE
 
- H_VASI_SUSPENDED
 
- H_VASI_SUSPENDING
 
- H_VIOCTL
 
- H_VIO_SIGNAL
 
- H_VL_PARM
 
- H_VMALLOC_END
 
- H_VMALLOC_SIZE
 
- H_VMALLOC_START
 
- H_VMEMMAP_END
 
- H_VMEMMAP_SIZE
 
- H_VMEMMAP_START
 
- H_VPA_DEREG_DTL
 
- H_VPA_DEREG_SLB
 
- H_VPA_DEREG_VPA
 
- H_VPA_FUNC_MASK
 
- H_VPA_FUNC_SHIFT
 
- H_VPA_REG_DTL
 
- H_VPA_REG_SLB
 
- H_VPA_REG_VPA
 
- H_VTERM_PARTNER_INFO
 
- H_WIDTH_1
 
- H_WIDTH_12
 
- H_WIDTH_16
 
- H_WIDTH_20
 
- H_WIDTH_24
 
- H_WIDTH_28
 
- H_WIDTH_4
 
- H_WIDTH_8
 
- H_XIRR
 
- H_XIRR_X
 
- H_ZERO_PAGE
 
- HalDetectPwrDownMode
 
- HalPwrSeqCmdParsing
 
- HalQueryTxBufferStatus8723BSdio
 
- HalQueryTxOQTBufferStatus8723BSdio
 
- HalRxAggr8723BSdio
 
- HalRxCheckStuck819xUsb
 
- HalSdioGetCmdAddr8723BSdio
 
- HalSetBrateCfg
 
- HalSetOutPutGPIO
 
- HalTxCheckStuck819xUsb
 
- HalUsbSetQueuePipeMapping8188EUsb
 
- Hal_BT_EfusePowerSwitch
 
- Hal_ChannelPlanToRegulation
 
- Hal_DetectWoWMode
 
- Hal_EfuseGetCurrentSize
 
- Hal_EfuseParseAntennaDiversity_8723B
 
- Hal_EfuseParseBTCoexistInfo_8723B
 
- Hal_EfuseParseBoardType88E
 
- Hal_EfuseParseBoardType_8723BS
 
- Hal_EfuseParseChnlPlan_8723B
 
- Hal_EfuseParseCustomerID88E
 
- Hal_EfuseParseCustomerID_8723B
 
- Hal_EfuseParseEEPROMVer88E
 
- Hal_EfuseParseEEPROMVer_8723B
 
- Hal_EfuseParseIDCode
 
- Hal_EfuseParseIDCode88E
 
- Hal_EfuseParseMACAddr_8188EU
 
- Hal_EfuseParseMACAddr_8723BS
 
- Hal_EfuseParsePIDVID_8188EU
 
- Hal_EfuseParsePackageType_8723B
 
- Hal_EfuseParseThermalMeter_8723B
 
- Hal_EfuseParseTxPowerInfo_8723B
 
- Hal_EfuseParseVoltage_8723B
 
- Hal_EfuseParseXtal_8188E
 
- Hal_EfuseParseXtal_8723B
 
- Hal_EfusePgPacketRead
 
- Hal_EfusePgPacketWrite
 
- Hal_EfusePgPacketWrite_BT
 
- Hal_EfusePowerSwitch
 
- Hal_EfuseWordEnableDataWrite
 
- Hal_GetChnlGroup8723B
 
- Hal_GetChnlGroup88E
 
- Hal_GetEfuseDefinition
 
- Hal_InitPGData
 
- Hal_InitPGData88E
 
- Hal_MappingOutPipe
 
- Hal_ReadAntennaDiversity88E
 
- Hal_ReadEFuse
 
- Hal_ReadPowerSavingMode88E
 
- Hal_ReadPowerValueFromPROM_8188E
 
- Hal_ReadPowerValueFromPROM_8723B
 
- Hal_ReadRFGainOffset
 
- Hal_ReadThermalMeter_88E
 
- Hal_ReadTxPowerInfo88E
 
- HalfDCLK
 
- HamaUSBSightcam
 
- HamaUSBSightcam2
 
- HandshakeDisables
 
- Hangul_LBase
 
- Hangul_LCount
 
- Hangul_NCount
 
- Hangul_SBase
 
- Hangul_SCount
 
- Hangul_TBase
 
- Hangul_TCount
 
- Hangul_VBase
 
- Hangul_VCount
 
- HasBrokenTx
 
- HasHltClk
 
- HasLWake
 
- HasMACAddrBug
 
- HasMII
 
- HasMulticastBug
 
- HashFilter
 
- HashKey
 
- HashKey_2
 
- HashKey_2_k
 
- HashKey_3
 
- HashKey_3_k
 
- HashKey_4
 
- HashKey_4_k
 
- HashKey_k
 
- HashTable
 
- HashTable0
 
- HashTable1
 
- HashTbl
 
- HaveWideTiming
 
- Hcbadr_Colkey
 
- Hcbadr_Glalpha
 
- Hcckmsk_Colkey_M
 
- Hcctrl_Cbase_Adr
 
- Hcpos_Curblink
 
- Hcpos_Xstart
 
- Hcpos_Ystart
 
- Hcsize_Cheight
 
- Hcsize_Cwidth
 
- Hdp_SurfaceEndian
 
- Heartbeat_type
 
- Hi16
 
- Hi8
 
- HiCModeIndex
 
- HiPOWERen
 
- HiPOWERep
 
- HiPOWERon
 
- HiPOWERop
 
- HiPriTxRingPtr
 
- HiTVDataLen
 
- HiTVSimuVCLK
 
- HiTVTextVCLK
 
- HiTVVCLK
 
- HiTVVCLKDIV2
 
- HiTxRingAddr
 
- HideWindow
 
- HighPriority
 
- HighThresholdShift
 
- Hit_Invalidate
 
- Hit_Invalidate_D
 
- Hit_Invalidate_I
 
- Hit_Invalidate_I_Loongson2
 
- Hit_Invalidate_S
 
- Hit_Invalidate_SD
 
- Hit_Invalidate_SI
 
- Hit_Set_Virtual_SD
 
- Hit_Set_Virtual_SI
 
- Hit_Writeback
 
- Hit_Writeback_D
 
- Hit_Writeback_I
 
- Hit_Writeback_Inv
 
- Hit_Writeback_Inv_D
 
- Hit_Writeback_Inv_S
 
- Hit_Writeback_Inv_SD
 
- Hit_Writeback_SD
 
- HltClk
 
- Hold
 
- HorStretch
 
- HorizOverflow
 
- HostBusAdapterStatus
 
- HostCmd_ACT_BITWISE_CLR
 
- HostCmd_ACT_BITWISE_SET
 
- HostCmd_ACT_GEN_GET
 
- HostCmd_ACT_GEN_REMOVE
 
- HostCmd_ACT_GEN_SET
 
- HostCmd_ACT_GET_BOTH
 
- HostCmd_ACT_GET_RX
 
- HostCmd_ACT_GET_TX
 
- HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON
 
- HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE
 
- HostCmd_ACT_MAC_DYNAMIC_BW_ENABLE
 
- HostCmd_ACT_MAC_ETHERNETII_ENABLE
 
- HostCmd_ACT_MAC_PROMISCUOUS_ENABLE
 
- HostCmd_ACT_MAC_RX_ON
 
- HostCmd_ACT_MAC_TX_ON
 
- HostCmd_ACT_MAC_WEP_ENABLE
 
- HostCmd_ACT_SET_BOTH
 
- HostCmd_ACT_SET_RX
 
- HostCmd_ACT_SET_TX
 
- HostCmd_BSS_MODE_ANY
 
- HostCmd_BSS_MODE_IBSS
 
- HostCmd_BSS_NUM_MASK
 
- HostCmd_BSS_TYPE_MASK
 
- HostCmd_CMD_11AC_CFG
 
- HostCmd_CMD_11N_ADDBA_REQ
 
- HostCmd_CMD_11N_ADDBA_RSP
 
- HostCmd_CMD_11N_CFG
 
- HostCmd_CMD_11N_DELBA
 
- HostCmd_CMD_802_11D_DOMAIN_INFO
 
- HostCmd_CMD_802_11_AD_HOC_JOIN
 
- HostCmd_CMD_802_11_AD_HOC_START
 
- HostCmd_CMD_802_11_AD_HOC_STOP
 
- HostCmd_CMD_802_11_ASSOCIATE
 
- HostCmd_CMD_802_11_BG_SCAN_CONFIG
 
- HostCmd_CMD_802_11_BG_SCAN_QUERY
 
- HostCmd_CMD_802_11_DEAUTHENTICATE
 
- HostCmd_CMD_802_11_EEPROM_ACCESS
 
- HostCmd_CMD_802_11_GET_LOG
 
- HostCmd_CMD_802_11_HS_CFG_ENH
 
- HostCmd_CMD_802_11_IBSS_COALESCING_STATUS
 
- HostCmd_CMD_802_11_KEY_MATERIAL
 
- HostCmd_CMD_802_11_MAC_ADDRESS
 
- HostCmd_CMD_802_11_PS_MODE_ENH
 
- HostCmd_CMD_802_11_SCAN
 
- HostCmd_CMD_802_11_SCAN_EXT
 
- HostCmd_CMD_802_11_SNMP_MIB
 
- HostCmd_CMD_802_11_SUBSCRIBE_EVENT
 
- HostCmd_CMD_802_11_TX_RATE_QUERY
 
- HostCmd_CMD_AMSDU_AGGR_CTRL
 
- HostCmd_CMD_BBP_REG_ACCESS
 
- HostCmd_CMD_CAU_REG_ACCESS
 
- HostCmd_CMD_CFG_DATA
 
- HostCmd_CMD_CHAN_REGION_CFG
 
- HostCmd_CMD_CHAN_REPORT_REQUEST
 
- HostCmd_CMD_COALESCE_CFG
 
- HostCmd_CMD_FUNC_INIT
 
- HostCmd_CMD_FUNC_SHUTDOWN
 
- HostCmd_CMD_FW_DUMP_EVENT
 
- HostCmd_CMD_GET_HW_SPEC
 
- HostCmd_CMD_GTK_REKEY_OFFLOAD_CFG
 
- HostCmd_CMD_HS_WAKEUP_REASON
 
- HostCmd_CMD_ID_MASK
 
- HostCmd_CMD_MAC_CONTROL
 
- HostCmd_CMD_MAC_MULTICAST_ADR
 
- HostCmd_CMD_MAC_REG_ACCESS
 
- HostCmd_CMD_MC_POLICY
 
- HostCmd_CMD_MEF_CFG
 
- HostCmd_CMD_MEM_ACCESS
 
- HostCmd_CMD_MGMT_FRAME_REG
 
- HostCmd_CMD_P2P_MODE_CFG
 
- HostCmd_CMD_PACKET_AGGR_CTRL
 
- HostCmd_CMD_PCIE_DESC_DETAILS
 
- HostCmd_CMD_PMIC_REG_ACCESS
 
- HostCmd_CMD_RECONFIGURE_TX_BUFF
 
- HostCmd_CMD_REMAIN_ON_CHAN
 
- HostCmd_CMD_RF_ANTENNA
 
- HostCmd_CMD_RF_REG_ACCESS
 
- HostCmd_CMD_RF_TX_PWR
 
- HostCmd_CMD_ROBUST_COEX
 
- HostCmd_CMD_RSSI_INFO
 
- HostCmd_CMD_SDIO_SP_RX_AGGR_CFG
 
- HostCmd_CMD_SET_BSS_MODE
 
- HostCmd_CMD_STA_CONFIGURE
 
- HostCmd_CMD_TDLS_CONFIG
 
- HostCmd_CMD_TDLS_OPER
 
- HostCmd_CMD_TXPWR_CFG
 
- HostCmd_CMD_TX_RATE_CFG
 
- HostCmd_CMD_UAP_BSS_START
 
- HostCmd_CMD_UAP_BSS_STOP
 
- HostCmd_CMD_UAP_STA_DEAUTH
 
- HostCmd_CMD_UAP_SYS_CONFIG
 
- HostCmd_CMD_VERSION_EXT
 
- HostCmd_CMD_WMM_GET_STATUS
 
- HostCmd_GET_BSS_NO
 
- HostCmd_GET_BSS_TYPE
 
- HostCmd_GET_SEQ_NO
 
- HostCmd_RESULT_OK
 
- HostCmd_RET_BIT
 
- HostCmd_SCAN_RADIO_TYPE_A
 
- HostCmd_SCAN_RADIO_TYPE_BG
 
- HostCmd_SEQ_NUM_MASK
 
- HostCmd_SET_SEQ_NO_BSS_INFO
 
- HostCmd_WEP_KEY_INDEX_MASK
 
- HostError
 
- HostFileSystem
 
- HostHighCmdNotFull
 
- HostHighCmdQue
 
- HostHighCmdQueue
 
- HostHighRespNotFull
 
- HostHighRespQue
 
- HostHighRespQueue
 
- HostNormCmdNotFull
 
- HostNormCmdQue
 
- HostNormCmdQueue
 
- HostNormRespNotFull
 
- HostNormRespQue
 
- HostNormRespQueue
 
- HostOwned
 
- HostPowerFail
 
- HostProcessed
 
- HostReset
 
- HostRidDesc
 
- HostRxDesc
 
- HostShutdown
 
- HostStat
 
- HostTxDesc
 
- HostVM
 
- HostWakeUpGpioClear
 
- HostWrite
 
- Host_Sleep_Action
 
- HotKeySwitch
 
- HotPlugFunction
 
- HsaDbgWaveMessage
 
- HsaDbgWaveMessageAMD
 
- HsaDbgWaveMsgAMDGen2
 
- HsaDeviceStateChange
 
- HsaEvent
 
- HsaEventData
 
- HsaEventDescriptor
 
- HsaNodeChange
 
- HsaSyncVar
 
- HufLog
 
- HugeFrame
 
- Hung
 
- HwRateToMRate
 
- HwRateToMRate90
 
- Hydra
 
- HyperSparc
 
- HzToHuman
 
[..]