[..]
- G
- G0
- G0_INMQ_L
- G0_INMQ_S
- G0_PORT_VID
- G0_PORT_VID_DEF
- G0_PORT_VID_MASK
- G0_RBPL_BS
- G0_RBPL_QI
- G0_RBPL_S
- G0_RBPL_T
- G0_RBPS_BS
- G0_RBPS_QI
- G0_RBPS_S
- G0_RBPS_T
- G0_RBRQ_H
- G0_RBRQ_I
- G0_RBRQ_Q
- G0_RBRQ_ST
- G0_TBRQ_B_T
- G0_TBRQ_H
- G0_TBRQ_S
- G0_TBRQ_THRESH
- G1
- G10_MPI_H
- G10_MPI_INLINE_DECL
- G10_MPI_INLINE_H
- G10_MPI_INTERNAL_H
- G12A_TOHDMITX_DRV_NAME
- G17
- G18
- G18_1610_KBR0
- G19
- G1_INMQ_L
- G1_INMQ_S
- G1_RBPL_BS
- G1_RBPL_QI
- G1_RBPL_S
- G1_RBPL_T
- G1_RBPS_BS
- G1_RBPS_QI
- G1_RBPS_S
- G1_RBPS_T
- G1_REG_ADDR_DIR_MV
- G1_REG_ADDR_DST
- G1_REG_ADDR_QTABLE
- G1_REG_ADDR_REF
- G1_REG_ADDR_REF_FIELD_E
- G1_REG_ADDR_REF_TOPC_E
- G1_REG_ADDR_STR
- G1_REG_ALT_SCAN_E
- G1_REG_ALT_SCAN_FLAG_E
- G1_REG_APF_THRESHOLD
- G1_REG_BD_P_REF_PIC
- G1_REG_BD_P_REF_PIC_BINIT_RLIST_B15
- G1_REG_BD_P_REF_PIC_BINIT_RLIST_F15
- G1_REG_BD_P_REF_PIC_PINIT_RLIST_F0
- G1_REG_BD_P_REF_PIC_PINIT_RLIST_F1
- G1_REG_BD_P_REF_PIC_PINIT_RLIST_F2
- G1_REG_BD_P_REF_PIC_PINIT_RLIST_F3
- G1_REG_BD_P_REF_PIC_QUANT_DELTA_4
- G1_REG_BD_REF_PIC
- G1_REG_BD_REF_PIC_BINIT_RLIST_B0
- G1_REG_BD_REF_PIC_BINIT_RLIST_B1
- G1_REG_BD_REF_PIC_BINIT_RLIST_B2
- G1_REG_BD_REF_PIC_BINIT_RLIST_F0
- G1_REG_BD_REF_PIC_BINIT_RLIST_F1
- G1_REG_BD_REF_PIC_BINIT_RLIST_F2
- G1_REG_BD_REF_PIC_PRED_TAP_2_4
- G1_REG_BD_REF_PIC_PRED_TAP_2_M1
- G1_REG_BD_REF_PIC_PRED_TAP_4_4
- G1_REG_BD_REF_PIC_PRED_TAP_4_M1
- G1_REG_BD_REF_PIC_PRED_TAP_6_4
- G1_REG_BD_REF_PIC_PRED_TAP_6_M1
- G1_REG_BD_REF_PIC_QUANT_2
- G1_REG_BD_REF_PIC_QUANT_3
- G1_REG_BD_REF_PIC_QUANT_DELTA_2
- G1_REG_BD_REF_PIC_QUANT_DELTA_3
- G1_REG_CONFIG
- G1_REG_CONFIG_DEC_ADV_PRE_DIS
- G1_REG_CONFIG_DEC_AXI_RD_ID
- G1_REG_CONFIG_DEC_CLK_GATE_E
- G1_REG_CONFIG_DEC_DATA_DISC_E
- G1_REG_CONFIG_DEC_INSWAP32_E
- G1_REG_CONFIG_DEC_IN_ENDIAN
- G1_REG_CONFIG_DEC_LATENCY
- G1_REG_CONFIG_DEC_MAX_BURST
- G1_REG_CONFIG_DEC_OUTSWAP32_E
- G1_REG_CONFIG_DEC_OUT_ENDIAN
- G1_REG_CONFIG_DEC_OUT_TILED_E
- G1_REG_CONFIG_DEC_SCMD_DIS
- G1_REG_CONFIG_DEC_STRENDIAN_E
- G1_REG_CONFIG_DEC_STRSWAP32_E
- G1_REG_CONFIG_DEC_TIMEOUT_E
- G1_REG_CONFIG_PRIORITY_MODE
- G1_REG_CONFIG_TILED_MODE_LSB
- G1_REG_CONFIG_TILED_MODE_MSB
- G1_REG_CON_MV_E
- G1_REG_DEC_ADV_PRE_DIS
- G1_REG_DEC_AXI_RD_ID
- G1_REG_DEC_AXI_WR_ID
- G1_REG_DEC_CLK_GATE_E
- G1_REG_DEC_CTRL0
- G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E
- G1_REG_DEC_CTRL0_DEC_AXI_WR_ID
- G1_REG_DEC_CTRL0_DEC_MODE
- G1_REG_DEC_CTRL0_DEC_OUT_DIS
- G1_REG_DEC_CTRL0_DIVX3_E
- G1_REG_DEC_CTRL0_FILTERING_DIS
- G1_REG_DEC_CTRL0_FWD_INTERLACE_E
- G1_REG_DEC_CTRL0_MVC_E
- G1_REG_DEC_CTRL0_PICORD_COUNT_E
- G1_REG_DEC_CTRL0_PIC_B_E
- G1_REG_DEC_CTRL0_PIC_FIELDMODE_E
- G1_REG_DEC_CTRL0_PIC_FIXED_QUANT
- G1_REG_DEC_CTRL0_PIC_INTERLACE_E
- G1_REG_DEC_CTRL0_PIC_INTER_E
- G1_REG_DEC_CTRL0_PIC_TOPFIELD_E
- G1_REG_DEC_CTRL0_PJPEG_E
- G1_REG_DEC_CTRL0_REFTOPFIRST_E
- G1_REG_DEC_CTRL0_REF_TOPFIELD_E
- G1_REG_DEC_CTRL0_RLC_MODE_E
- G1_REG_DEC_CTRL0_SEQ_MBAFF_E
- G1_REG_DEC_CTRL0_SKIP_MODE
- G1_REG_DEC_CTRL0_SORENSON_E
- G1_REG_DEC_CTRL0_WEBP_E
- G1_REG_DEC_CTRL0_WRITE_MVS_E
- G1_REG_DEC_CTRL1
- G1_REG_DEC_CTRL1_ALT_SCAN_E
- G1_REG_DEC_CTRL1_MB_HEIGHT_OFF
- G1_REG_DEC_CTRL1_MB_WIDTH_OFF
- G1_REG_DEC_CTRL1_PIC_MB_HEIGHT_P
- G1_REG_DEC_CTRL1_PIC_MB_H_EXT
- G1_REG_DEC_CTRL1_PIC_MB_WIDTH
- G1_REG_DEC_CTRL1_PIC_MB_W_EXT
- G1_REG_DEC_CTRL1_PIC_REFER_FLAG
- G1_REG_DEC_CTRL1_REF_FRAMES
- G1_REG_DEC_CTRL1_TOPFIELDFIRST_E
- G1_REG_DEC_CTRL2
- G1_REG_DEC_CTRL2_2MV_BLK_PAT_TAB
- G1_REG_DEC_CTRL2_4MV_BLK_PAT_TAB
- G1_REG_DEC_CTRL2_ALPHA_OFFSET
- G1_REG_DEC_CTRL2_BETA_OFFSET
- G1_REG_DEC_CTRL2_BOOLEAN_RANGE
- G1_REG_DEC_CTRL2_BOOLEAN_VALUE
- G1_REG_DEC_CTRL2_CBPTAB
- G1_REG_DEC_CTRL2_CB_AC_VLCTABLE
- G1_REG_DEC_CTRL2_CB_DC_VLCTABLE
- G1_REG_DEC_CTRL2_CB_DC_VLCTABLE3
- G1_REG_DEC_CTRL2_CH_QP_OFFSET
- G1_REG_DEC_CTRL2_CH_QP_OFFSET2
- G1_REG_DEC_CTRL2_CON_MV_E
- G1_REG_DEC_CTRL2_CR_AC_VLCTABLE
- G1_REG_DEC_CTRL2_CR_DC_VLCTABLE
- G1_REG_DEC_CTRL2_CR_DC_VLCTABLE3
- G1_REG_DEC_CTRL2_DQBI_LEVEL
- G1_REG_DEC_CTRL2_DQ_PROFILE
- G1_REG_DEC_CTRL2_FAST_UVMC_E
- G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E
- G1_REG_DEC_CTRL2_FRAME_PRED_DCT
- G1_REG_DEC_CTRL2_HUFFMAN_E
- G1_REG_DEC_CTRL2_INTRADC_VLC_THR
- G1_REG_DEC_CTRL2_INTRA_DC_PREC
- G1_REG_DEC_CTRL2_INTRA_VLC_TAB
- G1_REG_DEC_CTRL2_JPEG_FILRIGHT_E
- G1_REG_DEC_CTRL2_JPEG_MODE
- G1_REG_DEC_CTRL2_JPEG_QTABLES
- G1_REG_DEC_CTRL2_JPEG_STREAM_ALL
- G1_REG_DEC_CTRL2_MB_MODE_TAB
- G1_REG_DEC_CTRL2_MULTISTREAM_E
- G1_REG_DEC_CTRL2_MVTAB
- G1_REG_DEC_CTRL2_QSCALE_TYPE
- G1_REG_DEC_CTRL2_RANGE_RED_FRM_E
- G1_REG_DEC_CTRL2_STRM1_START_BIT
- G1_REG_DEC_CTRL2_STRM_START_BIT
- G1_REG_DEC_CTRL2_SYNC_MARKER_E
- G1_REG_DEC_CTRL2_TRANSACFRM
- G1_REG_DEC_CTRL2_TRANSACFRM2
- G1_REG_DEC_CTRL2_TRANSDCTAB
- G1_REG_DEC_CTRL2_TYPE1_QUANT_E
- G1_REG_DEC_CTRL2_VOP_TIME_INCR
- G1_REG_DEC_CTRL3
- G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E
- G1_REG_DEC_CTRL3_INIT_QP
- G1_REG_DEC_CTRL3_START_CODE_E
- G1_REG_DEC_CTRL3_STREAM_LEN
- G1_REG_DEC_CTRL3_STREAM_LEN_EXT
- G1_REG_DEC_CTRL4
- G1_REG_DEC_CTRL4_2ND_BYTE_EMUL_E
- G1_REG_DEC_CTRL4_ALT_PQUANT
- G1_REG_DEC_CTRL4_AVS_H264_H_EXT
- G1_REG_DEC_CTRL4_BILIN_MC_E
- G1_REG_DEC_CTRL4_BITPLANE0_E
- G1_REG_DEC_CTRL4_BITPLANE1_E
- G1_REG_DEC_CTRL4_BITPLANE2_E
- G1_REG_DEC_CTRL4_BLACKWHITE_E
- G1_REG_DEC_CTRL4_CABAC_E
- G1_REG_DEC_CTRL4_CH_MV_RES
- G1_REG_DEC_CTRL4_DCT1_START_BIT
- G1_REG_DEC_CTRL4_DCT2_START_BIT
- G1_REG_DEC_CTRL4_DIR_8X8_INFER_E
- G1_REG_DEC_CTRL4_DQUANT_E
- G1_REG_DEC_CTRL4_DQ_EDGES
- G1_REG_DEC_CTRL4_FRAMENUM
- G1_REG_DEC_CTRL4_FRAMENUM_LEN
- G1_REG_DEC_CTRL4_HALFQP_E
- G1_REG_DEC_CTRL4_INIT_DC_MATCH0
- G1_REG_DEC_CTRL4_INIT_DC_MATCH1
- G1_REG_DEC_CTRL4_PJPEG_AH
- G1_REG_DEC_CTRL4_PJPEG_AL
- G1_REG_DEC_CTRL4_PJPEG_FILDOWN_E
- G1_REG_DEC_CTRL4_PJPEG_HDIV8
- G1_REG_DEC_CTRL4_PJPEG_SE
- G1_REG_DEC_CTRL4_PJPEG_SS
- G1_REG_DEC_CTRL4_PJPEG_WDIV8
- G1_REG_DEC_CTRL4_PQINDEX
- G1_REG_DEC_CTRL4_TTFRM
- G1_REG_DEC_CTRL4_TTMBF
- G1_REG_DEC_CTRL4_UNIQP_E
- G1_REG_DEC_CTRL4_VC1_ADV_E
- G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT
- G1_REG_DEC_CTRL4_VP7_VERSION
- G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC
- G1_REG_DEC_CTRL4_WEIGHT_PRED_E
- G1_REG_DEC_CTRL5
- G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E
- G1_REG_DEC_CTRL5_CONST_INTRA_E
- G1_REG_DEC_CTRL5_DIVX3_SLICE_SIZE
- G1_REG_DEC_CTRL5_DIVX_IDCT_E
- G1_REG_DEC_CTRL5_FILT_CTRL_PRES
- G1_REG_DEC_CTRL5_IDR_PIC_E
- G1_REG_DEC_CTRL5_IDR_PIC_ID
- G1_REG_DEC_CTRL5_INIT_DC_COMP0
- G1_REG_DEC_CTRL5_INIT_DC_COMP1
- G1_REG_DEC_CTRL5_LOOP_FILT_LIMIT
- G1_REG_DEC_CTRL5_MV_SCALEFACTOR
- G1_REG_DEC_CTRL5_MV_THRESHOLD
- G1_REG_DEC_CTRL5_PJPEG_REST_FREQ
- G1_REG_DEC_CTRL5_RDPIC_CNT_PRES
- G1_REG_DEC_CTRL5_REFPIC_MK_LEN
- G1_REG_DEC_CTRL5_REF_DIST_BWD
- G1_REG_DEC_CTRL5_REF_DIST_FWD
- G1_REG_DEC_CTRL5_RV_BWD_SCALE
- G1_REG_DEC_CTRL5_RV_FWD_SCALE
- G1_REG_DEC_CTRL5_RV_OSV_QUANT
- G1_REG_DEC_CTRL5_RV_PROFILE
- G1_REG_DEC_CTRL5_VARIANCE_TEST_E
- G1_REG_DEC_CTRL5_VAR_THRESHOLD
- G1_REG_DEC_CTRL6
- G1_REG_DEC_CTRL6_COEFFS_PART_AM
- G1_REG_DEC_CTRL6_ICOMP0_E
- G1_REG_DEC_CTRL6_ISCALE0
- G1_REG_DEC_CTRL6_ISHIFT0
- G1_REG_DEC_CTRL6_PIC_SLICE_AM
- G1_REG_DEC_CTRL6_POC_LENGTH
- G1_REG_DEC_CTRL6_PPS_ID
- G1_REG_DEC_CTRL6_REFIDX0_ACTIVE
- G1_REG_DEC_CTRL6_REFIDX1_ACTIVE
- G1_REG_DEC_CTRL6_STREAM1_LEN
- G1_REG_DEC_CTRL7
- G1_REG_DEC_CTRL7_DCT3_START_BIT
- G1_REG_DEC_CTRL7_DCT4_START_BIT
- G1_REG_DEC_CTRL7_DCT5_START_BIT
- G1_REG_DEC_CTRL7_DCT6_START_BIT
- G1_REG_DEC_CTRL7_DCT7_START_BIT
- G1_REG_DEC_CTRL7_ICOMP2_E
- G1_REG_DEC_CTRL7_ISCALE2
- G1_REG_DEC_CTRL7_ISHIFT2
- G1_REG_DEC_CTRL7_PINIT_RLIST_F10
- G1_REG_DEC_CTRL7_PINIT_RLIST_F11
- G1_REG_DEC_CTRL7_PINIT_RLIST_F12
- G1_REG_DEC_CTRL7_PINIT_RLIST_F13
- G1_REG_DEC_CTRL7_PINIT_RLIST_F14
- G1_REG_DEC_CTRL7_PINIT_RLIST_F15
- G1_REG_DEC_DATA_DISC_E
- G1_REG_DEC_E
- G1_REG_DEC_INSWAP32_E
- G1_REG_DEC_IN_ENDIAN
- G1_REG_DEC_LATENCY
- G1_REG_DEC_MAX_BURST
- G1_REG_DEC_MODE
- G1_REG_DEC_OUTSWAP32_E
- G1_REG_DEC_OUT_BASE
- G1_REG_DEC_OUT_ENDIAN
- G1_REG_DEC_SCMD_DIS
- G1_REG_DEC_STRENDIAN_E
- G1_REG_DEC_STRSWAP32_E
- G1_REG_DEC_TIMEOUT_E
- G1_REG_ERR_CONC
- G1_REG_ERR_CONC_STARTMB_X
- G1_REG_ERR_CONC_STARTMB_Y
- G1_REG_FCODE_BWD_HOR
- G1_REG_FCODE_BWD_VER
- G1_REG_FCODE_FWD_HOR
- G1_REG_FCODE_FWD_VER
- G1_REG_FILTERING_DIS
- G1_REG_FRAME_PRED_DCT
- G1_REG_FWD_INTERLACE_E
- G1_REG_FWD_PIC
- G1_REG_FWD_PIC1_ICOMP1_E
- G1_REG_FWD_PIC1_ISCALE1
- G1_REG_FWD_PIC1_ISHIFT1
- G1_REG_FWD_PIC1_SEGMENT_BASE
- G1_REG_FWD_PIC1_SEGMENT_E
- G1_REG_FWD_PIC1_SEGMENT_UPD_E
- G1_REG_FWD_PIC_PINIT_RLIST_F0
- G1_REG_FWD_PIC_PINIT_RLIST_F1
- G1_REG_FWD_PIC_PINIT_RLIST_F2
- G1_REG_FWD_PIC_PINIT_RLIST_F3
- G1_REG_FWD_PIC_PINIT_RLIST_F4
- G1_REG_FWD_PIC_PINIT_RLIST_F5
- G1_REG_INIT_QP
- G1_REG_INTERRUPT
- G1_REG_INTERRUPT_DEC_ASO_INT
- G1_REG_INTERRUPT_DEC_BUFFER_INT
- G1_REG_INTERRUPT_DEC_BUS_INT
- G1_REG_INTERRUPT_DEC_E
- G1_REG_INTERRUPT_DEC_ERROR_INT
- G1_REG_INTERRUPT_DEC_IRQ
- G1_REG_INTERRUPT_DEC_IRQ_DIS
- G1_REG_INTERRUPT_DEC_PIC_INF
- G1_REG_INTERRUPT_DEC_RDY_INT
- G1_REG_INTERRUPT_DEC_SLICE_INT
- G1_REG_INTERRUPT_DEC_TIMEOUT
- G1_REG_INTRA_DC_PREC
- G1_REG_INTRA_VLC_TAB
- G1_REG_LT_REF
- G1_REG_MV_ACCURACY_BWD
- G1_REG_MV_ACCURACY_FWD
- G1_REG_PIC_B_E
- G1_REG_PIC_FIELDMODE_E
- G1_REG_PIC_INTERLACE_E
- G1_REG_PIC_INTER_E
- G1_REG_PIC_MB_HEIGHT_P
- G1_REG_PIC_MB_WIDTH
- G1_REG_PIC_TOPFIELD_E
- G1_REG_PRED_FLT
- G1_REG_PRED_FLT_PRED_BC_TAP_0_0
- G1_REG_PRED_FLT_PRED_BC_TAP_0_1
- G1_REG_PRED_FLT_PRED_BC_TAP_0_2
- G1_REG_QSCALE_TYPE
- G1_REG_QTABLE_BASE
- G1_REG_REFER0_BASE
- G1_REG_REFER1_BASE
- G1_REG_REFER2_BASE
- G1_REG_REFER3_BASE
- G1_REG_REF_BUF_CTRL
- G1_REG_REF_BUF_CTRL2
- G1_REG_REF_BUF_CTRL2_APF_THRESHOLD
- G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E
- G1_REG_REF_BUF_CTRL2_REFBU2_PICID
- G1_REG_REF_BUF_CTRL2_REFBU2_THR
- G1_REG_REF_BUF_CTRL_REFBU_E
- G1_REG_REF_BUF_CTRL_REFBU_EVAL_E
- G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E
- G1_REG_REF_BUF_CTRL_REFBU_PICID
- G1_REG_REF_BUF_CTRL_REFBU_THR
- G1_REG_REF_BUF_CTRL_REFBU_Y_OFFSET
- G1_REG_REF_PIC
- G1_REG_REF_PIC_FILT_SHARPNESS
- G1_REG_REF_PIC_FILT_TYPE_E
- G1_REG_REF_PIC_LF_LEVEL_0
- G1_REG_REF_PIC_LF_LEVEL_1
- G1_REG_REF_PIC_LF_LEVEL_2
- G1_REG_REF_PIC_LF_LEVEL_3
- G1_REG_REF_PIC_MB_ADJ_0
- G1_REG_REF_PIC_MB_ADJ_1
- G1_REG_REF_PIC_MB_ADJ_2
- G1_REG_REF_PIC_MB_ADJ_3
- G1_REG_REF_PIC_QUANT_0
- G1_REG_REF_PIC_QUANT_1
- G1_REG_REF_PIC_QUANT_DELTA_0
- G1_REG_REF_PIC_QUANT_DELTA_1
- G1_REG_REF_PIC_REFER0_NBR
- G1_REG_REF_PIC_REFER1_NBR
- G1_REG_RLC_MODE_E
- G1_REG_RLC_VLC_BASE
- G1_REG_SOFT_RESET
- G1_REG_STARTMB_X
- G1_REG_STARTMB_Y
- G1_REG_STREAM_LEN
- G1_REG_STRM_START_BIT
- G1_REG_TOPFIELDFIRST_E
- G1_REG_VALID_REF
- G1_REG_WRITE_MVS_E
- G1_SWREG
- G2
- G20
- G200
- G200_EH
- G200_EH3
- G200_ER
- G200_EV
- G200_EW3
- G200_SE_A
- G200_SE_B
- G200_WB
- G21
- G22
- G23
- G24
- G26
- G2CNTRL
- G2CNTRL_HRDY
- G2CNTRL_HRST
- G2CNTRL_IRST
- G2D_BITBLT_HOLD
- G2D_BITBLT_START
- G2D_BIT_ENGINE_BUSY
- G2D_BIT_SUSPEND_RUNQUEUE
- G2D_BUF_USERPTR
- G2D_CLK_G2D
- G2D_CLK_JPEG
- G2D_CLK_MDMA
- G2D_CLK_SLIM_SSS
- G2D_CLK_SMMU3_G2D
- G2D_CLK_SMMU3_JPEG
- G2D_CLK_SMMU_MDMA
- G2D_CLK_SMMU_SLIM_SSS
- G2D_CLK_SMMU_SSS
- G2D_CLK_SSS
- G2D_CMDLIST_DATA_NUM
- G2D_CMDLIST_NUM
- G2D_CMDLIST_POOL_SIZE
- G2D_CMDLIST_SIZE
- G2D_DMA_BITBLT_DONE_COUNT
- G2D_DMA_COMMAND
- G2D_DMA_CONTINUE
- G2D_DMA_DONE
- G2D_DMA_HALT
- G2D_DMA_HOLD_CMD
- G2D_DMA_LIST_DONE_COUNT
- G2D_DMA_LIST_DONE_COUNT_OFFSET
- G2D_DMA_SFR_BASE_ADDR
- G2D_DMA_START
- G2D_DMA_STATUS
- G2D_DOUT_PCLK_G2D_83
- G2D_DST_BASE_ADDR
- G2D_DST_COLOR_MODE
- G2D_DST_LEFT_TOP
- G2D_DST_PLANE2_BASE_ADDR
- G2D_DST_RIGHT_BOTTOM
- G2D_DST_STRIDE
- G2D_EVENT_NONSTOP
- G2D_EVENT_NOT
- G2D_EVENT_STOP
- G2D_FMT_A8
- G2D_FMT_ARGB1555
- G2D_FMT_ARGB4444
- G2D_FMT_ARGB8888
- G2D_FMT_L8
- G2D_FMT_PACKED_RGB888
- G2D_FMT_RGB565
- G2D_FMT_XRGB1555
- G2D_FMT_XRGB4444
- G2D_FMT_XRGB8888
- G2D_HW_MAJOR_VER
- G2D_HW_MINOR_VER
- G2D_INTC_PEND
- G2D_INTEN
- G2D_INTEN_ACF
- G2D_INTEN_GCF
- G2D_INTEN_SCF
- G2D_INTEN_UCF
- G2D_INTP_ACMD_FIN
- G2D_INTP_GCMD_FIN
- G2D_INTP_SCMD_FIN
- G2D_INTP_UCMD_FIN
- G2D_LEN_MAX
- G2D_LEN_MIN
- G2D_LIST_HOLD
- G2D_MOUT_ACLK_G2D_333_USER
- G2D_MSK_BASE_ADDR
- G2D_NAME
- G2D_NR_CLK
- G2D_PAT_BASE_ADDR
- G2D_R
- G2D_SFRCLEAR
- G2D_SOFT_RESET
- G2D_SRC_BASE_ADDR
- G2D_SRC_COLOR_MODE
- G2D_SRC_LEFT_TOP
- G2D_SRC_PLANE2_BASE_ADDR
- G2D_SRC_RIGHT_BOTTOM
- G2D_SRC_STRIDE
- G2D_START_BITBLT
- G2D_START_CASESEL
- G2D_START_NHOLT
- G2D_TIMEOUT
- G2D_USER_HOLD
- G2D_VALID_END
- G2D_VALID_START
- G2INTST
- G2INTST_ASNEVENT
- G2INTST_CCBERROR
- G2INTST_CCBGOOD
- G2INTST_CCBRETRY
- G2INTST_CMDERROR
- G2INTST_CMDGOOD
- G2INTST_HARDFAIL
- G2INTST_MASK
- G2STAT
- G2STAT2
- G2STAT2_READY
- G2STAT_BUSY
- G2STAT_INTPEND
- G2STAT_MBXOUT
- G2_CASCADE_CHAN
- G2_DMA_BASE
- G2_FIFO
- G2_INMQ_L
- G2_INMQ_S
- G2_NR_DMA_CHANNELS
- G2_RBPL_BS
- G2_RBPL_QI
- G2_RBPL_S
- G2_RBPL_T
- G2_RBPS_BS
- G2_RBPS_QI
- G2_RBPS_S
- G2_RBPS_T
- G3
- G33_GMCH_GMS_STOLEN_128M
- G33_GMCH_GMS_STOLEN_256M
- G33_GMCH_SIZE_1M
- G33_GMCH_SIZE_2M
- G33_GMCH_SIZE_MASK
- G364_MEM_BASE
- G364_PORT_BASE
- G3DCLK_STOPCTRL
- G3D_CLK_G3D
- G3D_CLK_G3D_HPM
- G3D_DOUT_ACLK_G3D
- G3D_DOUT_PCLK_G3D
- G3D_EMA_CTRL
- G3D_EMA_STATUS
- G3D_FOUT_G3D_PLL
- G3D_MOUT_G3D_PLL
- G3D_NR_CLK
- G3D_PLL_CON0
- G3D_PLL_CON1
- G3D_PLL_FDET
- G3D_PLL_FREQ_DET
- G3D_PLL_LOCK
- G3_INMQ_L
- G3_INMQ_S
- G3_RBPL_BS
- G3_RBPL_QI
- G3_RBPL_S
- G3_RBPL_T
- G3_RBPS_BS
- G3_RBPS_QI
- G3_RBPS_S
- G3_RBPS_T
- G4
- G400_XMISCCTRL_VDO_BYPASS656
- G400_XMISCCTRL_VDO_C2_BYPASS656
- G400_XMISCCTRL_VDO_C2_MAFC12
- G400_XMISCCTRL_VDO_MAFC12
- G400_XMISCCTRL_VDO_MASK
- G450CTRLS
- G450_MNP_FREQBITS
- G4X_AUD_CNTL_ST
- G4X_AUD_VID_DID
- G4X_ELDV_DEVCL_DEVBLC
- G4X_ELDV_DEVCTG
- G4X_ELD_ACK
- G4X_ELD_ADDR_MASK
- G4X_FIFO_LINE_SIZE
- G4X_FIFO_SIZE
- G4X_HDMIW_HDMIEDID
- G4X_MAX_WM
- G4X_STOLEN_RESERVED_ADDR1_MASK
- G4X_STOLEN_RESERVED_ADDR2_MASK
- G4X_STOLEN_RESERVED_ENABLE
- G4X_WM_LEVEL_HPLL
- G4X_WM_LEVEL_NORMAL
- G4X_WM_LEVEL_SR
- G4_INMQ_L
- G4_INMQ_S
- G4_RBPL_BS
- G4_RBPL_QI
- G4_RBPL_S
- G4_RBPL_T
- G4_RBPS_BS
- G4_RBPS_QI
- G4_RBPS_S
- G4_RBPS_T
- G4x_GMCH_SIZE_1M
- G4x_GMCH_SIZE_2M
- G4x_GMCH_SIZE_MASK
- G4x_GMCH_SIZE_VT_1M
- G4x_GMCH_SIZE_VT_1_5M
- G4x_GMCH_SIZE_VT_2M
- G4x_GMCH_SIZE_VT_EN
- G5
- G5_CRT_THROD_VAL
- G5_INMQ_L
- G5_INMQ_S
- G5_RBPL_BS
- G5_RBPL_QI
- G5_RBPL_S
- G5_RBPL_T
- G5_RBPS_BS
- G5_RBPS_QI
- G5_RBPS_S
- G5_RBPS_T
- G6
- G6XXX_PMA_PMD_VS1
- G6XXX_PMA_PMD_VS1_PLL_RESET
- G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET
- G6XXX_XGXS_XAUI_VS2
- G6XXX_XGXS_XAUI_VS2_INPUT_MASK
- G6_INMQ_L
- G6_INMQ_S
- G6_RBPL_BS
- G6_RBPL_QI
- G6_RBPL_S
- G6_RBPL_T
- G6_RBPS_BS
- G6_RBPS_QI
- G6_RBPS_S
- G6_RBPS_T
- G7
- G723_FDMA_PAGES
- G723_FRAMES_PER_PAGE
- G723_INTR_ORDER
- G723_PERIOD_BLOCK
- G723_PERIOD_BYTES
- G75_FEATURES
- G760A_DEFAULT_CLK
- G760A_DEFAULT_FAN_DIV
- G760A_REG_ACT_CNT
- G760A_REG_FAN_STA
- G760A_REG_FAN_STA_RPM_LOW
- G760A_REG_FAN_STA_RPM_OFF
- G760A_REG_SET_CNT
- G760A_UPDATE_INTERVAL
- G762_CLKDIV_FROM_REG
- G762_FAN_MODE_CLOSED_LOOP
- G762_FAN_MODE_OPEN_LOOP
- G762_GEARMULT_FROM_REG
- G762_OUT_MODE_DC
- G762_OUT_MODE_PWM
- G762_PULSE_FROM_REG
- G762_PWM_POLARITY_NEGATIVE
- G762_PWM_POLARITY_POSITIVE
- G762_REG_ACT_CNT
- G762_REG_FAN_CMD1
- G762_REG_FAN_CMD1_CLK_DIV_ID0
- G762_REG_FAN_CMD1_CLK_DIV_ID1
- G762_REG_FAN_CMD1_DET_FAN_FAIL
- G762_REG_FAN_CMD1_DET_FAN_OOC
- G762_REG_FAN_CMD1_FAN_MODE
- G762_REG_FAN_CMD1_OUT_MODE
- G762_REG_FAN_CMD1_PULSE_PER_REV
- G762_REG_FAN_CMD1_PWM_POLARITY
- G762_REG_FAN_CMD2
- G762_REG_FAN_CMD2_FAN_STARTV_0
- G762_REG_FAN_CMD2_FAN_STARTV_1
- G762_REG_FAN_CMD2_GEAR_MODE_0
- G762_REG_FAN_CMD2_GEAR_MODE_1
- G762_REG_FAN_STA
- G762_REG_FAN_STA_FAIL
- G762_REG_FAN_STA_OOC
- G762_REG_SET_CNT
- G762_REG_SET_OUT
- G762_UPDATE_INTERVAL
- G7_1
- G7_2
- G7_3
- G7_4
- G7_INMQ_L
- G7_INMQ_S
- G7_RBPL_BS
- G7_RBPL_QI
- G7_RBPL_S
- G7_RBPL_T
- G7_RBPS_BS
- G7_RBPS_QI
- G7_RBPS_S
- G7_RBPS_T
- G82_CHANNEL_DMA
- G82_CHANNEL_GPFIFO
- G82_DISP
- G82_DISP_BASE_CHANNEL_DMA
- G82_DISP_CORE_CHANNEL_DMA
- G82_DISP_CURSOR
- G82_DISP_OVERLAY
- G82_DISP_OVERLAY_CHANNEL_DMA
- G82_MPEG
- G82_TESLA
- G98_MSPDEC
- G98_MSPPP
- G98_MSVLD
- G98_SEC
- GAA_MMIO
- GAA_NCRAM
- GAA_RAM
- GAA_REGISTER
- GAB_CTL
- GAB_CTL_CONT_AFTER_PAGEFAULT
- GAB_CURRENT
- GAB_MAX_CHAN_TYPE
- GAB_POWER
- GAB_VOLTAGE
- GACC_FETCH
- GACC_IFETCH
- GACC_STORE
- GAC_ECO_BITS
- GADGETFS_CLEAR_HALT
- GADGETFS_CONNECT
- GADGETFS_DISCONNECT
- GADGETFS_FIFO_FLUSH
- GADGETFS_FIFO_STATUS
- GADGETFS_MAGIC
- GADGETFS_NOP
- GADGETFS_SETUP
- GADGETFS_SUSPEND
- GADGET_GET_PRINTER_STATUS
- GADGET_NAME
- GADGET_SET_PRINTER_STATUS
- GAFR
- GAFR_L
- GAFR_OFFSET
- GAFR_U
- GAHBCFG
- GAHBCFG_AHB_SINGLE
- GAHBCFG_CTRL_MASK
- GAHBCFG_DMA_EN
- GAHBCFG_GLBL_INTR_EN
- GAHBCFG_HBSTLEN_INCR
- GAHBCFG_HBSTLEN_INCR16
- GAHBCFG_HBSTLEN_INCR4
- GAHBCFG_HBSTLEN_INCR8
- GAHBCFG_HBSTLEN_MASK
- GAHBCFG_HBSTLEN_SHIFT
- GAHBCFG_HBSTLEN_SINGLE
- GAHBCFG_NOTI_ALL_DMA_WRIT
- GAHBCFG_NP_TXF_EMP_LVL
- GAHBCFG_P_TXF_EMP_LVL
- GAHBCFG_REM_MEM_SUPP
- GAIN
- GAIN1_MODE_MASK
- GAIN1_MODE_MASK_SFT
- GAIN1_MODE_SFT
- GAIN1_ON_MASK
- GAIN1_ON_MASK_SFT
- GAIN1_ON_SFT
- GAIN1_SAMPLE_PER_STEP_MASK
- GAIN1_SAMPLE_PER_STEP_MASK_SFT
- GAIN1_SAMPLE_PER_STEP_SFT
- GAIN1_TARGET_MASK
- GAIN1_TARGET_MASK_SFT
- GAIN1_TARGET_SFT
- GAIN2_MODE_MASK
- GAIN2_MODE_MASK_SFT
- GAIN2_MODE_SFT
- GAIN2_ON_MASK
- GAIN2_ON_MASK_SFT
- GAIN2_ON_SFT
- GAIN2_SAMPLE_PER_STEP_MASK
- GAIN2_SAMPLE_PER_STEP_MASK_SFT
- GAIN2_SAMPLE_PER_STEP_SFT
- GAIN2_TARGET_MASK
- GAIN2_TARGET_MASK_SFT
- GAIN2_TARGET_SFT
- GAINFUNC0_IN
- GAINFUNC0_OUT
- GAINFUNC1_IN
- GAINFUNC1_OUT
- GAINFUNC2_IN
- GAINFUNC2_OUT
- GAINFUNC3_IN
- GAINFUNC3_OUT
- GAINFUNC4_IN
- GAINFUNC4_OUT
- GAINLEFT
- GAINRIGHT
- GAINSEL_MULTI_12
- GAINSEL_MULTI_16
- GAINSEL_MULTI_24
- GAINSEL_MULTI_3
- GAINSEL_MULTI_4
- GAINSEL_MULTI_6
- GAINSEL_MULTI_8
- GAINSEL_MULTI_MAX
- GAIN_0_2
- GAIN_128x
- GAIN_16x
- GAIN_1_3
- GAIN_2x
- GAIN_32x
- GAIN_4x
- GAIN_64x
- GAIN_8x
- GAIN_ALPHA
- GAIN_AUGMENT
- GAIN_DB_TO_VOXWARE
- GAIN_DEFAULT
- GAIN_H3A_EN_SHIFT
- GAIN_INTEGER_SHIFT
- GAIN_IPIPE_EN_SHIFT
- GAIN_MAX
- GAIN_OFFSET_EN_MASK
- GAIN_SDRAM_EN_SHIFT
- GAIN_TAPER
- GAIN_VOXWARE_TO_DB
- GAIN_X
- GAIN_Y
- GAIN_Z
- GAISLER_AHB2AHB
- GAISLER_AHBJTAG
- GAISLER_AHBRAM
- GAISLER_AHBSTAT
- GAISLER_AHBTRACE
- GAISLER_AHBUART
- GAISLER_APBMST
- GAISLER_APBUART
- GAISLER_ATACTRL
- GAISLER_DDR2SPA
- GAISLER_DDRSPA
- GAISLER_ETHAHB
- GAISLER_ETHDSU
- GAISLER_ETHMAC
- GAISLER_FTMCTRL
- GAISLER_GPTIMER
- GAISLER_GR712RC
- GAISLER_GRACECTRL
- GAISLER_GRGPIO
- GAISLER_GRSYSMON
- GAISLER_I2CMST
- GAISLER_IRQMP
- GAISLER_KBD
- GAISLER_L2C
- GAISLER_L2TIME
- GAISLER_LEON3
- GAISLER_LEON3DSU
- GAISLER_LEON4
- GAISLER_LEON4DSU
- GAISLER_PCIDMA
- GAISLER_PCIFBRG
- GAISLER_PCISBRG
- GAISLER_PCITRACE
- GAISLER_PCITRG
- GAISLER_PIOPORT
- GAISLER_PLUGPLAY
- GAISLER_SDCTRL
- GAISLER_SPICTRL
- GAISLER_SPIMCTRL
- GAISLER_SRCTRL
- GAISLER_SVGA
- GAISLER_USBDC
- GAISLER_USBEHC
- GAISLER_USBUHC
- GAISLER_VGA
- GALAXY_COMMAND_GET_TYPE
- GALAXY_COMMAND_SB8MODE
- GALAXY_COMMAND_WSSMODE
- GALAXY_CONFIG_CDA_310
- GALAXY_CONFIG_CDA_320
- GALAXY_CONFIG_CDA_340
- GALAXY_CONFIG_CDA_350
- GALAXY_CONFIG_CDA_MASK
- GALAXY_CONFIG_CDDMA16_5
- GALAXY_CONFIG_CDDMA16_6
- GALAXY_CONFIG_CDDMA16_7
- GALAXY_CONFIG_CDDMA16_DISABLE
- GALAXY_CONFIG_CDDMA16_MASK
- GALAXY_CONFIG_CDDMA8_0
- GALAXY_CONFIG_CDDMA8_1
- GALAXY_CONFIG_CDDMA8_3
- GALAXY_CONFIG_CDDMA8_DISABLE
- GALAXY_CONFIG_CDDMA8_MASK
- GALAXY_CONFIG_CDDMA_0
- GALAXY_CONFIG_CDDMA_1
- GALAXY_CONFIG_CDDMA_3
- GALAXY_CONFIG_CDDMA_DISABLE
- GALAXY_CONFIG_CDDMA_MASK
- GALAXY_CONFIG_CDIRQ_11
- GALAXY_CONFIG_CDIRQ_12
- GALAXY_CONFIG_CDIRQ_15
- GALAXY_CONFIG_CDIRQ_5
- GALAXY_CONFIG_CDIRQ_MASK
- GALAXY_CONFIG_CD_AZTECH
- GALAXY_CONFIG_CD_DISABLE
- GALAXY_CONFIG_CD_MASK
- GALAXY_CONFIG_CD_MITSUMI
- GALAXY_CONFIG_CD_PANASONIC
- GALAXY_CONFIG_CD_SONY
- GALAXY_CONFIG_CD_UNUSED_5
- GALAXY_CONFIG_CD_UNUSED_6
- GALAXY_CONFIG_CD_UNUSED_7
- GALAXY_CONFIG_GAME_ENABLE
- GALAXY_CONFIG_MASK
- GALAXY_CONFIG_MPUA_300
- GALAXY_CONFIG_MPUA_330
- GALAXY_CONFIG_MPUIRQ_10
- GALAXY_CONFIG_MPUIRQ_2
- GALAXY_CONFIG_MPUIRQ_3
- GALAXY_CONFIG_MPUIRQ_5
- GALAXY_CONFIG_MPUIRQ_7
- GALAXY_CONFIG_MPU_ENABLE
- GALAXY_CONFIG_SBA_220
- GALAXY_CONFIG_SBA_240
- GALAXY_CONFIG_SBA_260
- GALAXY_CONFIG_SBA_280
- GALAXY_CONFIG_SBA_MASK
- GALAXY_CONFIG_SBDMA_0
- GALAXY_CONFIG_SBDMA_1
- GALAXY_CONFIG_SBDMA_3
- GALAXY_CONFIG_SBDMA_DISABLE
- GALAXY_CONFIG_SBIRQ_10
- GALAXY_CONFIG_SBIRQ_2
- GALAXY_CONFIG_SBIRQ_3
- GALAXY_CONFIG_SBIRQ_5
- GALAXY_CONFIG_SBIRQ_7
- GALAXY_CONFIG_SIZE
- GALAXY_CONFIG_UNUSED
- GALAXY_CONFIG_UNUSED_MASK
- GALAXY_CONFIG_WSSA_530
- GALAXY_CONFIG_WSSA_604
- GALAXY_CONFIG_WSSA_E80
- GALAXY_CONFIG_WSSA_F40
- GALAXY_CONFIG_WSS_ENABLE
- GALAXY_DSP_MAJOR
- GALAXY_DSP_MINOR
- GALAXY_MODE_SB8
- GALAXY_MODE_WSS
- GALAXY_PORT_CONFIG
- GAL_ISC
- GAM1
- GAM10
- GAM11
- GAM12
- GAM13
- GAM14
- GAM15
- GAM2
- GAM3
- GAM4
- GAM5
- GAM6
- GAM7
- GAM8
- GAM9
- GAMC_RX_MAX_FRAME
- GAMEPORT_ATTACH_DRIVER
- GAMEPORT_AXES
- GAMEPORT_GCR
- GAMEPORT_ID_VENDOR_ANALOG
- GAMEPORT_ID_VENDOR_CREATIVE
- GAMEPORT_ID_VENDOR_GENIUS
- GAMEPORT_ID_VENDOR_GRAVIS
- GAMEPORT_ID_VENDOR_GUILLEMOT
- GAMEPORT_ID_VENDOR_INTERACT
- GAMEPORT_ID_VENDOR_LOGITECH
- GAMEPORT_ID_VENDOR_MADCATZ
- GAMEPORT_ID_VENDOR_MICROSOFT
- GAMEPORT_ID_VENDOR_THRUSTMASTER
- GAMEPORT_LEGACY
- GAMEPORT_MODE_ADC
- GAMEPORT_MODE_COOKED
- GAMEPORT_MODE_DISABLED
- GAMEPORT_MODE_RAW
- GAMEPORT_REGISTER_PORT
- GAME_AXES_ENABLE_1
- GAME_AXES_ENABLE_2
- GAME_AXES_ENABLE_3
- GAME_AXES_ENABLE_4
- GAME_AXES_LATCH_ENABLE
- GAME_AXES_READ_MASK
- GAME_AXES_SAMPLING_READY
- GAME_HWCFG_ADC_COUNTER_FREQ_1_2
- GAME_HWCFG_ADC_COUNTER_FREQ_1_20
- GAME_HWCFG_ADC_COUNTER_FREQ_1_200
- GAME_HWCFG_ADC_COUNTER_FREQ_MASK
- GAME_HWCFG_ADC_COUNTER_FREQ_STD
- GAME_HWCFG_IRQ_ENABLE
- GAME_HWCFG_LEGACY_ADDRESS_ENABLE
- GAME_IO_ENABLE
- GAME_PORT_ENABLE
- GAMMA
- GAMMAWD
- GAMMA_ADDR_PORT
- GAMMA_AUTO
- GAMMA_BIAS
- GAMMA_CMD_CNT
- GAMMA_CNTL_PORT
- GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END_MASK
- GAMMA_CORR_CNTLA_END_CNTL1__GAMMA_CORR_CNTLA_EXP_REGION_END__SHIFT
- GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE_MASK
- GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_BASE__SHIFT
- GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE_MASK
- GAMMA_CORR_CNTLA_END_CNTL2__GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE__SHIFT
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_0_1__GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_10_11__GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_12_13__GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_14_15__GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_2_3__GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_4_5__GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_6_7__GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLA_REGION_8_9__GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
- GAMMA_CORR_CNTLA_SLOPE_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
- GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_MASK
- GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT_MASK
- GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
- GAMMA_CORR_CNTLA_START_CNTL__GAMMA_CORR_CNTLA_EXP_REGION_START__SHIFT
- GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END_MASK
- GAMMA_CORR_CNTLB_END_CNTL1__GAMMA_CORR_CNTLB_EXP_REGION_END__SHIFT
- GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE_MASK
- GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_BASE__SHIFT
- GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE_MASK
- GAMMA_CORR_CNTLB_END_CNTL2__GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE__SHIFT
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_0_1__GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_10_11__GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_12_13__GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_14_15__GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_2_3__GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_4_5__GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_6_7__GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
- GAMMA_CORR_CNTLB_REGION_8_9__GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
- GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
- GAMMA_CORR_CNTLB_SLOPE_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
- GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_MASK
- GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT_MASK
- GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
- GAMMA_CORR_CNTLB_START_CNTL__GAMMA_CORR_CNTLB_EXP_REGION_START__SHIFT
- GAMMA_CORR_CONTROL_A
- GAMMA_CORR_CONTROL_B
- GAMMA_CORR_CONTROL_BYPASS
- GAMMA_CORR_CONTROL__GAMMA_CORR_MODE_MASK
- GAMMA_CORR_CONTROL__GAMMA_CORR_MODE__SHIFT
- GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA_MASK
- GAMMA_CORR_LUT_DATA__GAMMA_CORR_LUT_DATA__SHIFT
- GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX_MASK
- GAMMA_CORR_LUT_INDEX__GAMMA_CORR_LUT_INDEX__SHIFT
- GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK_MASK
- GAMMA_CORR_LUT_WRITE_EN_MASK__GAMMA_CORR_LUT_WRITE_EN_MASK__SHIFT
- GAMMA_CORR_MODE_A
- GAMMA_CORR_MODE_B
- GAMMA_CORR_MODE_BYPASS
- GAMMA_CS_TFM_1D
- GAMMA_CS_TFM_1D_ENTRIES
- GAMMA_CTRL_1
- GAMMA_CTRL_10
- GAMMA_CTRL_2
- GAMMA_CTRL_3
- GAMMA_CTRL_4
- GAMMA_CTRL_5
- GAMMA_CTRL_6
- GAMMA_CTRL_7
- GAMMA_CTRL_8
- GAMMA_CTRL_9
- GAMMA_CUSTOM
- GAMMA_CUSTOM_ENTRIES
- GAMMA_DATA_PORT
- GAMMA_DEF
- GAMMA_EN
- GAMMA_ENTRIES
- GAMMA_FORMATTER
- GAMMA_HW_POINTS_NUM
- GAMMA_LEN
- GAMMA_LEVEL_NUM
- GAMMA_LUT_EN
- GAMMA_MAX
- GAMMA_MAX_ENTRIES
- GAMMA_MODE
- GAMMA_MODE_MODE_10BIT
- GAMMA_MODE_MODE_12BIT
- GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED
- GAMMA_MODE_MODE_8BIT
- GAMMA_MODE_MODE_MASK
- GAMMA_MODE_MODE_SPLIT
- GAMMA_MOUT_EN_RDMA1
- GAMMA_NUM
- GAMMA_PROBE_COLOR_H
- GAMMA_PROBE_COLOR_L
- GAMMA_PROBE_CTRL
- GAMMA_PROBE_HL_COLOR
- GAMMA_PROBE_POS_X
- GAMMA_PROBE_POS_Y
- GAMMA_RGB_256
- GAMMA_RGB_256_ENTRIES
- GAMMA_RGB_FLOAT_1024
- GAMMA_RGB_FLOAT_1024_ENTRIES
- GAMMA_TABLE_COUNT
- GAMMA_TABLE_LEN
- GAMMA_VCOM_HSWITCH_ADDR
- GAMTARBMODE
- GAMT_CHKN_BIT_REG
- GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
- GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT
- GAMT_CHKN_DISABLE_L3_COH_PIPE
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
- GAMUT_COEF
- GAMUT_COEF_B
- GAMUT_EN
- GAMUT_MATRIX_SIZE
- GAMUT_REMAP_BYPASS
- GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK
- GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT
- GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK
- GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT
- GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK
- GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT
- GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK
- GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT
- GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK
- GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT
- GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK
- GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT
- GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK
- GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT
- GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK
- GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT
- GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK
- GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT
- GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK
- GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT
- GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK
- GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT
- GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK
- GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT
- GAMUT_REMAP_COEFF
- GAMUT_REMAP_COMA_COEFF
- GAMUT_REMAP_COMB_COEFF
- GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK
- GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
- GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK
- GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT
- GAMUT_REMAP_MODE_1
- GAMUT_REMAP_MODE_2
- GAMUT_REMAP_MODE_3
- GAMUT_REMAP_MODE_BYPASS
- GAMUT_REMAP_PROG_COEFF
- GAMUT_REMAP_PROG_SHARED_MATRIXA
- GAMUT_REMAP_PROG_SHARED_MATRIXB
- GAMW_ECO_DEV_CTX_RELOAD_DISABLE
- GAMW_ECO_ENABLE_64K_IPS_FIELD
- GAM_BENABLE
- GAM_CTL_BACK_MASK
- GAM_CTL_CURSOR_MASK
- GAM_CTL_GDP0_MASK
- GAM_CTL_GDP1_MASK
- GAM_CTL_GDP2_MASK
- GAM_CTL_GDP3_MASK
- GAM_CTL_VID0_MASK
- GAM_CTL_VID1_MASK
- GAM_DEPTH_GDP0_ID
- GAM_DEPTH_GDP1_ID
- GAM_DEPTH_GDP2_ID
- GAM_DEPTH_GDP3_ID
- GAM_DEPTH_MASK_ID
- GAM_DEPTH_VID0_ID
- GAM_DEPTH_VID1_ID
- GAM_ECOCHK
- GAM_ENABLE
- GAM_ENABLES
- GAM_GDP_AGC_FULL_RANGE
- GAM_GDP_AGC_OFFSET
- GAM_GDP_ALPHARANGE_255
- GAM_GDP_CML_OFFSET
- GAM_GDP_CTL_OFFSET
- GAM_GDP_KEY1_OFFSET
- GAM_GDP_KEY2_OFFSET
- GAM_GDP_MST_OFFSET
- GAM_GDP_NVN_OFFSET
- GAM_GDP_PML_OFFSET
- GAM_GDP_PMP_OFFSET
- GAM_GDP_PPT_IGNORE
- GAM_GDP_PPT_OFFSET
- GAM_GDP_SIZE_MAX_HEIGHT
- GAM_GDP_SIZE_MAX_WIDTH
- GAM_GDP_SIZE_OFFSET
- GAM_GDP_VPO_OFFSET
- GAM_GDP_VPS_OFFSET
- GAM_GENABLE
- GAM_MIXER_ACT
- GAM_MIXER_AVO
- GAM_MIXER_AVS
- GAM_MIXER_BCO
- GAM_MIXER_BCS
- GAM_MIXER_BKC
- GAM_MIXER_CRB
- GAM_MIXER_CTL
- GAM_MIXER_MBP
- GAM_MIXER_MX0
- GAM_MIXER_NB_DEPTH_LEVEL
- GAM_RENABLE
- GANG_EN
- GAOP
- GAP
- GAPD
- GAPSPCI_BBA_CONFIG
- GAPSPCI_BBA_CONFIG_SIZE
- GAPSPCI_DMA_BASE
- GAPSPCI_DMA_SIZE
- GAPSPCI_IRQ
- GAPSPCI_REGS
- GARBAGE_BYTE
- GARBAGE_INT
- GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_ME_COMMAND_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_ME_COMMAND__ADDRESS__SHIFT
- GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_PFP_COMMAND_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_PFP_COMMAND__ADDRESS__SHIFT
- GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_PIO_COMMAND_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS_MASK
- GARLIC_COHE_CP_DMA_PIO_COMMAND__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_CP_RB0_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB0_WPTR__ADDRESS_MASK
- GARLIC_COHE_CP_RB0_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_CP_RB1_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB1_WPTR__ADDRESS_MASK
- GARLIC_COHE_CP_RB1_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_CP_RB2_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_CP_RB2_WPTR__ADDRESS_MASK
- GARLIC_COHE_CP_RB2_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS_MASK
- GARLIC_COHE_GARLIC_FLUSH_REQ_IND__ADDRESS__SHIFT
- GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS_MASK
- GARLIC_COHE_GARLIC_FLUSH_REQ__ADDRESS__SHIFT
- GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SAM_SAB_RBI_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS_MASK
- GARLIC_COHE_SAM_SAB_RBI_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SAM_SAB_RBO_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS_MASK
- GARLIC_COHE_SAM_SAB_RBO_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SDMA0_GFX_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_SDMA0_GFX_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SDMA1_GFX_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_SDMA1_GFX_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SDMA2_GFX_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_SDMA2_GFX_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_SDMA3_GFX_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_SDMA3_GFX_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_UVD_RBC_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_UVD_RBC_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_VCE_OUT_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_VCE_OUT_RB_WPTR__ADDRESS__SHIFT
- GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS_MASK
- GARLIC_COHE_VCE_RB_WPTR2_IND__ADDRESS__SHIFT
- GARLIC_COHE_VCE_RB_WPTR2__ADDRESS_MASK
- GARLIC_COHE_VCE_RB_WPTR2__ADDRESS__SHIFT
- GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS_MASK
- GARLIC_COHE_VCE_RB_WPTR_IND__ADDRESS__SHIFT
- GARLIC_COHE_VCE_RB_WPTR__ADDRESS_MASK
- GARLIC_COHE_VCE_RB_WPTR__ADDRESS__SHIFT
- GARLIC_FLUSH_ADDR_END_0__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_0__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_1__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_1__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_2__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_2__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_3__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_3__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_4__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_4__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_5__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_5__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_6__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_6__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_END_7__ADDR_END_MASK
- GARLIC_FLUSH_ADDR_END_7__ADDR_END__SHIFT
- GARLIC_FLUSH_ADDR_START_0__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_0__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_0__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_0__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_0__MODE_MASK
- GARLIC_FLUSH_ADDR_START_0__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_1__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_1__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_1__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_1__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_1__MODE_MASK
- GARLIC_FLUSH_ADDR_START_1__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_2__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_2__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_2__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_2__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_2__MODE_MASK
- GARLIC_FLUSH_ADDR_START_2__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_3__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_3__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_3__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_3__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_3__MODE_MASK
- GARLIC_FLUSH_ADDR_START_3__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_4__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_4__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_4__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_4__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_4__MODE_MASK
- GARLIC_FLUSH_ADDR_START_4__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_5__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_5__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_5__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_5__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_5__MODE_MASK
- GARLIC_FLUSH_ADDR_START_5__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_6__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_6__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_6__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_6__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_6__MODE_MASK
- GARLIC_FLUSH_ADDR_START_6__MODE__SHIFT
- GARLIC_FLUSH_ADDR_START_7__ADDR_START_MASK
- GARLIC_FLUSH_ADDR_START_7__ADDR_START__SHIFT
- GARLIC_FLUSH_ADDR_START_7__ENABLE_MASK
- GARLIC_FLUSH_ADDR_START_7__ENABLE__SHIFT
- GARLIC_FLUSH_ADDR_START_7__MODE_MASK
- GARLIC_FLUSH_ADDR_START_7__MODE__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND_MASK
- GARLIC_FLUSH_CNTL_IND__CP_DMA_ME_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND_MASK
- GARLIC_FLUSH_CNTL_IND__CP_DMA_PFP_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND_MASK
- GARLIC_FLUSH_CNTL_IND__CP_DMA_PIO_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__CP_RB0_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__CP_RB1_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__CP_RB2_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__DISABLE_ALL_MASK
- GARLIC_FLUSH_CNTL_IND__DISABLE_ALL__SHIFT
- GARLIC_FLUSH_CNTL_IND__DISPLAY_MASK
- GARLIC_FLUSH_CNTL_IND__DISPLAY__SHIFT
- GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL_MASK
- GARLIC_FLUSH_CNTL_IND__HOST_DOORBELL__SHIFT
- GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE_MASK
- GARLIC_FLUSH_CNTL_IND__IGNORE_MC_DISABLE__SHIFT
- GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBI_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SAM_SAB_RBO_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SDMA0_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SDMA1_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SDMA2_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__SDMA3_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL_MASK
- GARLIC_FLUSH_CNTL_IND__SELFRING_DOORBELL__SHIFT
- GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__UVD_RBC_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__VCE_OUT_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2_MASK
- GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR2__SHIFT
- GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL_IND__VCE_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND_MASK
- GARLIC_FLUSH_CNTL__CP_DMA_ME_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND_MASK
- GARLIC_FLUSH_CNTL__CP_DMA_PFP_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND_MASK
- GARLIC_FLUSH_CNTL__CP_DMA_PIO_COMMAND__SHIFT
- GARLIC_FLUSH_CNTL__CP_RB0_WPTR_MASK
- GARLIC_FLUSH_CNTL__CP_RB0_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__CP_RB1_WPTR_MASK
- GARLIC_FLUSH_CNTL__CP_RB1_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__CP_RB2_WPTR_MASK
- GARLIC_FLUSH_CNTL__CP_RB2_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__DISABLE_ALL_MASK
- GARLIC_FLUSH_CNTL__DISABLE_ALL__SHIFT
- GARLIC_FLUSH_CNTL__DISPLAY_MASK
- GARLIC_FLUSH_CNTL__DISPLAY__SHIFT
- GARLIC_FLUSH_CNTL__HOST_DOORBELL_MASK
- GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT
- GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE_MASK
- GARLIC_FLUSH_CNTL__IGNORE_MC_DISABLE__SHIFT
- GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR_MASK
- GARLIC_FLUSH_CNTL__SAM_SAB_RBI_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR_MASK
- GARLIC_FLUSH_CNTL__SAM_SAB_RBO_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__SDMA0_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__SDMA1_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__SDMA2_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__SDMA3_GFX_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__SELFRING_DOORBELL_MASK
- GARLIC_FLUSH_CNTL__SELFRING_DOORBELL__SHIFT
- GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__UVD_RBC_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__VCE_OUT_RB_WPTR__SHIFT
- GARLIC_FLUSH_CNTL__VCE_RB_WPTR2_MASK
- GARLIC_FLUSH_CNTL__VCE_RB_WPTR2__SHIFT
- GARLIC_FLUSH_CNTL__VCE_RB_WPTR_MASK
- GARLIC_FLUSH_CNTL__VCE_RB_WPTR__SHIFT
- GARLIC_FLUSH_REQ_IND__FLUSH_REQ_MASK
- GARLIC_FLUSH_REQ_IND__FLUSH_REQ__SHIFT
- GARLIC_FLUSH_REQ__FLUSH_REQ_MASK
- GARLIC_FLUSH_REQ__FLUSH_REQ__SHIFT
- GARMIN_IQUE_3600_ID
- GARMIN_LAYERID_APPL
- GARMIN_LAYERID_PRIVATE
- GARMIN_LAYERID_TRANSPORT
- GARMIN_PKTHDR_LENGTH
- GARMIN_PKTID_L001_COMMAND_DATA
- GARMIN_PKTID_PVT_DATA
- GARMIN_VENDOR_ID
- GARP_ACTION_NONE
- GARP_ACTION_S_JOIN_IN
- GARP_ACTION_S_LEAVE_EMPTY
- GARP_ADDR_MAX
- GARP_ADDR_MIN
- GARP_ADDR_RANGE
- GARP_APPLICANT_AA
- GARP_APPLICANT_AO
- GARP_APPLICANT_AP
- GARP_APPLICANT_INVALID
- GARP_APPLICANT_LA
- GARP_APPLICANT_MAX
- GARP_APPLICANT_QA
- GARP_APPLICANT_QO
- GARP_APPLICANT_QP
- GARP_APPLICANT_VA
- GARP_APPLICANT_VO
- GARP_APPLICANT_VP
- GARP_APPLICATION_GVRP
- GARP_APPLICATION_MAX
- GARP_EMPTY
- GARP_END_MARK
- GARP_EVENT_MAX
- GARP_EVENT_REQ_JOIN
- GARP_EVENT_REQ_LEAVE
- GARP_EVENT_R_EMPTY
- GARP_EVENT_R_JOIN_EMPTY
- GARP_EVENT_R_JOIN_IN
- GARP_EVENT_R_LEAVE_EMPTY
- GARP_EVENT_R_LEAVE_IN
- GARP_EVENT_TRANSMIT_PDU
- GARP_GVRP_ADDRESS
- GARP_JOIN_EMPTY
- GARP_JOIN_IN
- GARP_LEAVE_ALL
- GARP_LEAVE_EMPTY
- GARP_LEAVE_IN
- GARP_PROTOCOL_ID
- GARTEN
- GARTPTEERR
- GART_CONFIG
- GART_ENTRY_ADDR
- GART_ENTRY_DATA
- GART_ENTRY_PHYS_ADDR_VALID
- GART_IOMMU_PGSIZES
- GART_MAX_ADDR
- GART_MAX_PHYS_ADDR
- GART_MIN_ADDR
- GART_PAGE_MASK
- GART_PAGE_SHIFT
- GART_PAGE_SIZE
- GART_REG_BASE
- GASGAUGE_INTR_OFFSET
- GASKET_DEV_MAX
- GASKET_END_OF_ATTR_ARRAY
- GASKET_EXTENDED_LVL0_SHIFT
- GASKET_EXTENDED_LVL0_WIDTH
- GASKET_EXTENDED_LVL1_SHIFT
- GASKET_FRAMEWORK_DESC_MAX
- GASKET_FRAMEWORK_VERSION
- GASKET_IOCTL_BASE
- GASKET_IOCTL_CLEAR_EVENTFD
- GASKET_IOCTL_CLEAR_INTERRUPT_COUNTS
- GASKET_IOCTL_CONFIG_COHERENT_ALLOCATOR
- GASKET_IOCTL_LOOPBACK_INTERRUPT
- GASKET_IOCTL_MAP_BUFFER
- GASKET_IOCTL_NUMBER_PAGE_TABLES
- GASKET_IOCTL_PAGE_TABLE_SIZE
- GASKET_IOCTL_PARTITION_PAGE_TABLE
- GASKET_IOCTL_RESET
- GASKET_IOCTL_SET_EVENTFD
- GASKET_IOCTL_SIMPLE_PAGE_TABLE_SIZE
- GASKET_IOCTL_UNMAP_BUFFER
- GASKET_MAX_NUM_PAGE_TABLES
- GASKET_NAME_MAX
- GASKET_NOMAP
- GASKET_NUM_BARS
- GASKET_PAGES_PER_SUBTABLE
- GASKET_PAGE_TABLE_MODE_EXTENDED
- GASKET_PAGE_TABLE_MODE_NORMAL
- GASKET_PAGE_TABLE_MODE_SIMPLE
- GASKET_SIMPLE_PAGE_SHIFT
- GASKET_STATUS_ALIVE
- GASKET_STATUS_DEAD
- GASKET_STATUS_DRIVER_EXIT
- GASKET_STATUS_LAMED
- GASKET_SYSFS_MAX_NODES
- GASKET_SYSFS_NUM_MAPPINGS
- GASKET_SYSFS_RO
- GASKET_UNUSED_BAR
- GASKET_VALID_SLOT_FLAG
- GAS_INITIAL_REQ
- GAS_INITIAL_RSP
- GATCL1RequestType
- GATCL1_TYPE_BYPASS
- GATCL1_TYPE_NORMAL
- GATCL1_TYPE_SHOOTDOWN
- GATE
- GATECLK
- GATED_CLOCK
- GATEWAY
- GATEWAY_PAGE_SIZE
- GATE_ADDR
- GATE_APMIXED
- GATE_APMIXED_FLAGS
- GATE_AUD
- GATE_AUDIO0
- GATE_AUDIO1
- GATE_AUDIO2
- GATE_AUDIO3
- GATE_BDP
- GATE_BDP0
- GATE_BDP1
- GATE_BLOCK
- GATE_BUS
- GATE_BUS_CDREX0
- GATE_BUS_CDREX1
- GATE_BUS_CPU
- GATE_BUS_DISP1
- GATE_BUS_DMC0
- GATE_BUS_DMC1
- GATE_BUS_DMC2
- GATE_BUS_DMC3
- GATE_BUS_FSYS0
- GATE_BUS_FSYS2
- GATE_BUS_GEN
- GATE_BUS_NOC
- GATE_BUS_PERIC
- GATE_BUS_PERIC1
- GATE_BUS_PERIS0
- GATE_BUS_PERIS1
- GATE_BUS_TOP
- GATE_CALL
- GATE_CAM
- GATE_CLOCKS
- GATE_CLR_SET_UPD_FLAGS
- GATE_DCLK0
- GATE_DCLK1
- GATE_DISP0
- GATE_DISP1
- GATE_EHDR
- GATE_ETH
- GATE_G3D
- GATE_HIF
- GATE_ICG
- GATE_ICG0
- GATE_ICG1
- GATE_ICG1_FLAGS
- GATE_ICG2
- GATE_ICG2_FLAGS
- GATE_IMG
- GATE_INFRA
- GATE_INFRA0
- GATE_INFRA1
- GATE_INFRA2
- GATE_INFRA3
- GATE_INTERRUPT
- GATE_IPE
- GATE_IPU_ADL_I
- GATE_IPU_CONN
- GATE_IPU_CONN_APB
- GATE_IPU_CONN_AXI1_I
- GATE_IPU_CONN_AXI2_I
- GATE_IPU_CONN_AXI_I
- GATE_IPU_CORE0
- GATE_IPU_CORE1
- GATE_IP_ACP
- GATE_IP_CAM
- GATE_IP_CPU
- GATE_IP_DISP1
- GATE_IP_DMC
- GATE_IP_DMC0
- GATE_IP_DMC1
- GATE_IP_FSYS
- GATE_IP_G2D
- GATE_IP_G3D
- GATE_IP_GEN
- GATE_IP_GPS
- GATE_IP_GSCL
- GATE_IP_GSCL0
- GATE_IP_GSCL1
- GATE_IP_ISP
- GATE_IP_ISP0
- GATE_IP_ISP1
- GATE_IP_LCD
- GATE_IP_LCD0
- GATE_IP_LEFTBUS
- GATE_IP_MFC
- GATE_IP_MSCL
- GATE_IP_PERIC
- GATE_IP_PERIL
- GATE_IP_PERIR
- GATE_IP_PERIS
- GATE_IP_RIGHTBUS
- GATE_IP_TV
- GATE_JPGDEC
- GATE_MFG
- GATE_MM0
- GATE_MM1
- GATE_MM2
- GATE_MP1
- GATE_MTK
- GATE_MTK_FLAGS
- GATE_ON
- GATE_PCIE
- GATE_PERI
- GATE_PERI0
- GATE_PERI1
- GATE_PERI2
- GATE_SCLK
- GATE_SCLK_CAM
- GATE_SCLK_CPU
- GATE_SCLK_DMC
- GATE_SCLK_FSYS
- GATE_SCLK_G3D
- GATE_SCLK_ISP
- GATE_SCLK_ISP_TOP
- GATE_SCLK_LCD
- GATE_SCLK_MFC
- GATE_SCLK_PERIL
- GATE_SGMII
- GATE_SSUSB
- GATE_TASK
- GATE_TOP
- GATE_TOP0
- GATE_TOP1
- GATE_TOP2
- GATE_TOP2_I
- GATE_TOP3
- GATE_TOP4_I
- GATE_TOP5
- GATE_TOP_AUD
- GATE_TOP_SCLK_DISP1
- GATE_TOP_SCLK_FSYS
- GATE_TOP_SCLK_GSCL
- GATE_TOP_SCLK_ISP
- GATE_TOP_SCLK_MAU
- GATE_TOP_SCLK_PERIC
- GATE_TRAP
- GATE_VDEC0
- GATE_VDEC0_I
- GATE_VDEC1
- GATE_VDEC1_I
- GATE_VENC
- GATE_VENCLT
- GATE_VENC_I
- GATHER_COUNT
- GAT_EXT
- GAT_GND
- GAT_NOUTNM2
- GAT_VCC
- GAUGECOUNT
- GAUSSR0
- GAVG
- GAYLE
- GAYLE_ADDRESS
- GAYLE_ATTRIBUTE
- GAYLE_ATTRIBUTESIZE
- GAYLE_CFG_0V
- GAYLE_CFG_100NS
- GAYLE_CFG_12V
- GAYLE_CFG_150NS
- GAYLE_CFG_250NS
- GAYLE_CFG_5V
- GAYLE_CFG_720NS
- GAYLE_CONTROL
- GAYLE_CS_BSY
- GAYLE_CS_BVD1
- GAYLE_CS_BVD2
- GAYLE_CS_CCDET
- GAYLE_CS_DA
- GAYLE_CS_IRQ
- GAYLE_CS_SC
- GAYLE_CS_WR
- GAYLE_HAS_CONTROL_REG
- GAYLE_IO
- GAYLE_IOSIZE
- GAYLE_IO_8BITODD
- GAYLE_IRQ_1200
- GAYLE_IRQ_4000
- GAYLE_IRQ_BSY
- GAYLE_IRQ_BVD1
- GAYLE_IRQ_BVD2
- GAYLE_IRQ_CCDET
- GAYLE_IRQ_DA
- GAYLE_IRQ_IDE
- GAYLE_IRQ_IDEACK0
- GAYLE_IRQ_IDEACK1
- GAYLE_IRQ_IRQ
- GAYLE_IRQ_SC
- GAYLE_IRQ_WR
- GAYLE_NEXT_PORT
- GAYLE_NUM_HWIFS
- GAYLE_NUM_PROBE_HWIFS
- GAYLE_ODD
- GAYLE_RAM
- GAYLE_RAMSIZE
- GAYLE_RESET
- GAZEL_CNTRL
- GAZEL_HSCX_EN
- GAZEL_INCSR
- GAZEL_INT_HSCX
- GAZEL_INT_ISAC
- GAZEL_IPAC_DATA_PORT
- GAZEL_IPAC_EN
- GAZEL_ISAC_EN
- GAZEL_PCI_EN
- GAZEL_RESET
- GAZEL_RESET_9050
- GA_CDCFG_REG
- GA_DEADLOCK_CNTL
- GA_DEVID
- GA_DMAA_REG
- GA_DMAB_REG
- GA_DMACFG_REG
- GA_ENHANCE
- GA_ENTRY_SIZE
- GA_FASTSYNC_CNTL
- GA_GUEST_NR
- GA_HMCTL_REG
- GA_INTCFG_REG
- GA_INTENA_REG
- GA_INTSTAT_REG
- GA_LOG_ENTRIES
- GA_LOG_SIZE
- GA_LOG_SIZE_512
- GA_LOG_SIZE_SHIFT
- GA_NXT_CMD
- GA_NXT_REQ_SIZE
- GA_NXT_RSP_SIZE
- GA_NXT_SNS_CMD_SIZE
- GA_NXT_SNS_DATA_SIZE
- GA_NXT_SNS_SCMD_LEN
- GA_POLY_MODE
- GA_REG
- GA_REQ_TYPE
- GA_ROUND_MODE
- GA_SMCFGA_REG
- GA_SMCFGB_REG
- GA_TAG
- GB
- GB2
- GBAUDIO_CODEC_HWPARAMS
- GBAUDIO_CODEC_PREPARE
- GBAUDIO_CODEC_SHUTDOWN
- GBAUDIO_CODEC_START
- GBAUDIO_CODEC_STARTUP
- GBAUDIO_CODEC_STOP
- GBAUDIO_DEVICE_BIT_DEFAULT
- GBAUDIO_DEVICE_BIT_IN
- GBAUDIO_DEVICE_IN_BUILTIN_MIC
- GBAUDIO_DEVICE_IN_WIRED_HEADSET
- GBAUDIO_DEVICE_NONE
- GBAUDIO_DEVICE_OUT_SPEAKER
- GBAUDIO_DEVICE_OUT_WIRED_HEADPHONE
- GBAUDIO_DEVICE_OUT_WIRED_HEADSET
- GBAUDIO_INVALID_ID
- GBAUDIO_MODULE_OFF
- GBAUDIO_MODULE_ON
- GBBASE
- GBBASE_COLKEY
- GBBASE_GLALPHA
- GBCODEC_JACK_BUTTON_MASK
- GBCODEC_JACK_MASK
- GBCR_ADV_1000FULL
- GBCR_ADV_1000HALF
- GBCR_MANUAL_AS_MASTER
- GBCR_MANUAL_CONFIG_ENABLE
- GBCR_PREFER_MASTER
- GBE
- GBE13_ALE_OFFSET
- GBE13_CPTS_OFFSET
- GBE13_EMAC_OFFSET
- GBE13_HOST_PORT_NUM
- GBE13_HOST_PORT_OFFSET
- GBE13_HW_STATS_OFFSET
- GBE13_NUM_ALE_ENTRIES
- GBE13_REG_VAL_STAT_ENABLE_ALL
- GBE13_SGMII_MODULE_OFFSET
- GBE13_SLAVE_PORT2_OFFSET
- GBE13_SLAVE_PORT_OFFSET
- GBECONT
- GBECONT_RMII0
- GBECONT_RMII1
- GBENU_ALE_OFFSET
- GBENU_CPTS_OFFSET
- GBENU_EMAC_OFFSET
- GBENU_ET_STATS_HOST_SIZE
- GBENU_ET_STATS_PORT_SIZE
- GBENU_HOST_PORT_NUM
- GBENU_HOST_PORT_OFFSET
- GBENU_HW_STATS_OFFSET
- GBENU_HW_STATS_REG_MAP_SZ
- GBENU_MODULE_NAME
- GBENU_SET_REG_OFS
- GBENU_SGMII_MODULE_OFFSET
- GBENU_SGMII_MODULE_SIZE
- GBENU_SLAVE_PORT_OFFSET
- GBENU_SM_REG_INDEX
- GBENU_SS_REG_INDEX
- GBENU_STATS0_MODULE
- GBENU_STATS1_MODULE
- GBENU_STATS2_MODULE
- GBENU_STATS3_MODULE
- GBENU_STATS4_MODULE
- GBENU_STATS5_MODULE
- GBENU_STATS6_MODULE
- GBENU_STATS7_MODULE
- GBENU_STATS8_MODULE
- GBENU_STATS_HOST
- GBENU_STATS_P1
- GBENU_STATS_P2
- GBENU_STATS_P3
- GBENU_STATS_P4
- GBENU_STATS_P5
- GBENU_STATS_P6
- GBENU_STATS_P7
- GBENU_STATS_P8
- GBE_BASE
- GBE_BMODE_BOTH
- GBE_CMODE_ARGB5
- GBE_CMODE_I12
- GBE_CMODE_I8
- GBE_CMODE_RG3B2
- GBE_CMODE_RGB10
- GBE_CMODE_RGB4
- GBE_CMODE_RGB8
- GBE_CMODE_RGBA5
- GBE_CONFIG_BASE_VIRT
- GBE_CONFIG_FLASH_READ
- GBE_CONFIG_FLASH_WRITE
- GBE_CONFIG_OFFSET
- GBE_CONFIG_RAM_BASE
- GBE_CRS_MAGIC
- GBE_CRS_START_XY_CRS_STARTX_LSB
- GBE_CRS_START_XY_CRS_STARTX_MSB
- GBE_CRS_START_XY_CRS_STARTY_LSB
- GBE_CRS_START_XY_CRS_STARTY_MSB
- GBE_CTL_P0_ENABLE
- GBE_CTRLSTAT_CHIPID_LSB
- GBE_CTRLSTAT_CHIPID_MSB
- GBE_CTRLSTAT_PCLKSEL_LSB
- GBE_CTRLSTAT_PCLKSEL_MSB
- GBE_CTRLSTAT_SENSE_N_LSB
- GBE_CTRLSTAT_SENSE_N_MSB
- GBE_DEFAULT_ALE_AGEOUT
- GBE_DEF_10G_MAC_CONTROL
- GBE_DEF_1G_MAC_CONTROL
- GBE_DID_CONTROL_DID_DMA_ENABLE_LSB
- GBE_DID_CONTROL_DID_DMA_ENABLE_MSB
- GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB
- GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB
- GBE_DID_START_XY_DID_STARTX_LSB
- GBE_DID_START_XY_DID_STARTX_MSB
- GBE_DID_START_XY_DID_STARTY_LSB
- GBE_DID_START_XY_DID_STARTY_MSB
- GBE_DOTCLK_M_LSB
- GBE_DOTCLK_M_MSB
- GBE_DOTCLK_N_LSB
- GBE_DOTCLK_N_MSB
- GBE_DOTCLK_P_LSB
- GBE_DOTCLK_P_MSB
- GBE_DOTCLK_RUN_LSB
- GBE_DOTCLK_RUN_MSB
- GBE_FP_DE_OFF_LSB
- GBE_FP_DE_OFF_MSB
- GBE_FP_DE_ON_LSB
- GBE_FP_DE_ON_MSB
- GBE_FP_HDRV_OFF_LSB
- GBE_FP_HDRV_OFF_MSB
- GBE_FP_HDRV_ON_LSB
- GBE_FP_HDRV_ON_MSB
- GBE_FP_VDRV_OFF_LSB
- GBE_FP_VDRV_OFF_MSB
- GBE_FP_VDRV_ON_LSB
- GBE_FP_VDRV_ON_MSB
- GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB
- GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB
- GBE_FRM_CONTROL_FRM_LINEAR_LSB
- GBE_FRM_CONTROL_FRM_LINEAR_MSB
- GBE_FRM_CONTROL_FRM_TILE_PTR_LSB
- GBE_FRM_CONTROL_FRM_TILE_PTR_MSB
- GBE_FRM_DEPTH_16
- GBE_FRM_DEPTH_32
- GBE_FRM_DEPTH_8
- GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB
- GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB
- GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB
- GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB
- GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB
- GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB
- GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB
- GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB
- GBE_FRM_SIZE_TILE_FRM_RHS_LSB
- GBE_FRM_SIZE_TILE_FRM_RHS_MSB
- GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB
- GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB
- GBE_HW_STATS_REG_MAP_SZ
- GBE_IDENT
- GBE_MAJOR_VERSION
- GBE_MASK_NO_PORTS
- GBE_MAX_HW_STAT_MODS
- GBE_MINOR_VERSION
- GBE_MODULE_NAME
- GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB
- GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB
- GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB
- GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB
- GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB
- GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB
- GBE_PIXEN_MAGIC_OFF
- GBE_PIXEN_MAGIC_ON
- GBE_PORT_MASK
- GBE_REG_ADDR
- GBE_RTL_VERSION
- GBE_RXHOOK_ORDER
- GBE_SET_REG_OFS
- GBE_SGMII34_REG_INDEX
- GBE_SM_REG_INDEX
- GBE_SS_ID_2U
- GBE_SS_ID_NU
- GBE_SS_REG_INDEX
- GBE_SS_VERSION_14
- GBE_STATSA_INFO
- GBE_STATSA_MODULE
- GBE_STATSB_INFO
- GBE_STATSB_MODULE
- GBE_STATSC_INFO
- GBE_STATSC_MODULE
- GBE_STATSD_INFO
- GBE_STATSD_MODULE
- GBE_STATS_CD_SEL
- GBE_TIMER_INTERVAL
- GBE_TLB_SIZE
- GBE_TXHOOK_ORDER
- GBE_TX_QUEUE
- GBE_VC_START_XY_VC_STARTX_LSB
- GBE_VC_START_XY_VC_STARTX_MSB
- GBE_VC_START_XY_VC_STARTY_LSB
- GBE_VC_START_XY_VC_STARTY_MSB
- GBE_VOF_DO_GENSYNC
- GBE_VOF_FLATPANEL
- GBE_VOF_MAGICKEY
- GBE_VOF_STEREO
- GBE_VOF_SYNC_ON_GREEN
- GBE_VOF_UNKNOWNMON
- GBE_VT_FLAGS_F2RF_HIGH_LSB
- GBE_VT_FLAGS_F2RF_HIGH_MSB
- GBE_VT_FLAGS_HDRV_INVERT_LSB
- GBE_VT_FLAGS_HDRV_INVERT_MSB
- GBE_VT_FLAGS_HDRV_LOW_LSB
- GBE_VT_FLAGS_HDRV_LOW_MSB
- GBE_VT_FLAGS_SYNC_HIGH_LSB
- GBE_VT_FLAGS_SYNC_HIGH_MSB
- GBE_VT_FLAGS_SYNC_LOW_LSB
- GBE_VT_FLAGS_SYNC_LOW_MSB
- GBE_VT_FLAGS_VDRV_INVERT_LSB
- GBE_VT_FLAGS_VDRV_INVERT_MSB
- GBE_VT_FLAGS_VDRV_LOW_LSB
- GBE_VT_FLAGS_VDRV_LOW_MSB
- GBE_VT_HBLANK_HBLANK_OFF_LSB
- GBE_VT_HBLANK_HBLANK_OFF_MSB
- GBE_VT_HBLANK_HBLANK_ON_LSB
- GBE_VT_HBLANK_HBLANK_ON_MSB
- GBE_VT_HCMAP_HCMAP_OFF_LSB
- GBE_VT_HCMAP_HCMAP_OFF_MSB
- GBE_VT_HCMAP_HCMAP_ON_LSB
- GBE_VT_HCMAP_HCMAP_ON_MSB
- GBE_VT_HPIXEN_HPIXEN_OFF_LSB
- GBE_VT_HPIXEN_HPIXEN_OFF_MSB
- GBE_VT_HPIXEN_HPIXEN_ON_LSB
- GBE_VT_HPIXEN_HPIXEN_ON_MSB
- GBE_VT_HSYNC_HSYNC_OFF_LSB
- GBE_VT_HSYNC_HSYNC_OFF_MSB
- GBE_VT_HSYNC_HSYNC_ON_LSB
- GBE_VT_HSYNC_HSYNC_ON_MSB
- GBE_VT_VBLANK_VBLANK_OFF_LSB
- GBE_VT_VBLANK_VBLANK_OFF_MSB
- GBE_VT_VBLANK_VBLANK_ON_LSB
- GBE_VT_VBLANK_VBLANK_ON_MSB
- GBE_VT_VCMAP_VCMAP_OFF_LSB
- GBE_VT_VCMAP_VCMAP_OFF_MSB
- GBE_VT_VCMAP_VCMAP_ON_LSB
- GBE_VT_VCMAP_VCMAP_ON_MSB
- GBE_VT_VPIXEN_VPIXEN_OFF_LSB
- GBE_VT_VPIXEN_VPIXEN_OFF_MSB
- GBE_VT_VPIXEN_VPIXEN_ON_LSB
- GBE_VT_VPIXEN_VPIXEN_ON_MSB
- GBE_VT_VSYNC_VSYNC_OFF_LSB
- GBE_VT_VSYNC_VSYNC_OFF_MSB
- GBE_VT_VSYNC_VSYNC_ON_LSB
- GBE_VT_VSYNC_VSYNC_ON_MSB
- GBE_VT_XYMAX_MAXX_LSB
- GBE_VT_XYMAX_MAXX_MSB
- GBE_VT_XYMAX_MAXY_LSB
- GBE_VT_XYMAX_MAXY_MSB
- GBE_VT_XY_FREEZE_LSB
- GBE_VT_XY_FREEZE_MSB
- GBE_VT_XY_X_LSB
- GBE_VT_XY_X_MSB
- GBE_VT_XY_Y_LSB
- GBE_VT_XY_Y_MSB
- GBE_WID_AUX_LSB
- GBE_WID_AUX_MSB
- GBE_WID_BUF_LSB
- GBE_WID_BUF_MSB
- GBE_WID_CM_LSB
- GBE_WID_CM_MSB
- GBE_WID_GAMMA_LSB
- GBE_WID_GAMMA_MSB
- GBE_WID_TYP_LSB
- GBE_WID_TYP_MSB
- GBF_FULL
- GBGGAIN
- GBITSHIFT
- GBIT_SUPPORT
- GBL_RSVD_TASKS
- GBL_WAKEUP_INT_MSK
- GBPA_ABORT
- GBPA_UPDATE
- GBPHY_PROTOCOL
- GBSR_LOCAL_MASTER
- GBSR_LOCAL_OK
- GBSR_LP_1000FULL
- GBSR_LP_1000HALF
- GBSR_MASTER_FAULT
- GBSR_REMOTE_OK
- GBULK_BIT_EN
- GB_AA_CONFIG
- GB_ADDR_CONFIG
- GB_ADDR_CONFIG_DEFAULT
- GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK
- GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT
- GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK
- GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT
- GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK
- GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT
- GB_ADDR_CONFIG_READ__NUM_BANKS_MASK
- GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT
- GB_ADDR_CONFIG_READ__NUM_GPUS_MASK
- GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT
- GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK
- GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT
- GB_ADDR_CONFIG_READ__NUM_PIPES_MASK
- GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT
- GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK
- GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT
- GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK
- GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT
- GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK
- GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT
- GB_ADDR_CONFIG_READ__ROW_SIZE_MASK
- GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT
- GB_ADDR_CONFIG_READ__SE_ENABLE_MASK
- GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT
- GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK
- GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT
- GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
- GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
- GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
- GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
- GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
- GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
- GB_ADDR_CONFIG__NUM_BANKS_MASK
- GB_ADDR_CONFIG__NUM_BANKS__SHIFT
- GB_ADDR_CONFIG__NUM_GPUS_MASK
- GB_ADDR_CONFIG__NUM_GPUS__SHIFT
- GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
- GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
- GB_ADDR_CONFIG__NUM_PIPES_MASK
- GB_ADDR_CONFIG__NUM_PIPES__SHIFT
- GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK
- GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
- GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
- GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
- GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
- GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
- GB_ADDR_CONFIG__ROW_SIZE_MASK
- GB_ADDR_CONFIG__ROW_SIZE__SHIFT
- GB_ADDR_CONFIG__SE_ENABLE_MASK
- GB_ADDR_CONFIG__SE_ENABLE__SHIFT
- GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
- GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
- GB_APB_CPORT_FLAG_CONTROL
- GB_APB_CPORT_FLAG_HIGH_PRIO
- GB_APB_REQUEST_ARPC_RUN
- GB_APB_REQUEST_AUDIO_CONTROL
- GB_APB_REQUEST_CPORT_COUNT
- GB_APB_REQUEST_CPORT_FLAGS
- GB_APB_REQUEST_CSI_TX_CONTROL
- GB_APB_REQUEST_EP_MAPPING
- GB_APB_REQUEST_LATENCY_TAG_DIS
- GB_APB_REQUEST_LATENCY_TAG_EN
- GB_APB_REQUEST_LOG
- GB_APB_REQUEST_RESET_CPORT
- GB_APB_REQUEST_TIMESYNC_AUTHORITATIVE
- GB_APB_REQUEST_TIMESYNC_DISABLE
- GB_APB_REQUEST_TIMESYNC_ENABLE
- GB_APB_REQUEST_TIMESYNC_GET_LAST_EVENT
- GB_AUDIO_ACCESS_INACTIVE
- GB_AUDIO_ACCESS_LOCK
- GB_AUDIO_ACCESS_OWNER
- GB_AUDIO_ACCESS_READ
- GB_AUDIO_ACCESS_TIMESTAMP
- GB_AUDIO_ACCESS_TLV_COMMAND
- GB_AUDIO_ACCESS_TLV_READ
- GB_AUDIO_ACCESS_TLV_WRITE
- GB_AUDIO_ACCESS_VOLATILE
- GB_AUDIO_ACCESS_WRITE
- GB_AUDIO_BUTTON_EVENT_PRESS
- GB_AUDIO_BUTTON_EVENT_RELEASE
- GB_AUDIO_CTL_ELEM_ACCESS_READ
- GB_AUDIO_CTL_ELEM_ACCESS_WRITE
- GB_AUDIO_CTL_ELEM_IFACE_CARD
- GB_AUDIO_CTL_ELEM_IFACE_HWDEP
- GB_AUDIO_CTL_ELEM_IFACE_MIXER
- GB_AUDIO_CTL_ELEM_IFACE_PCM
- GB_AUDIO_CTL_ELEM_IFACE_RAWMIDI
- GB_AUDIO_CTL_ELEM_IFACE_SEQUENCER
- GB_AUDIO_CTL_ELEM_IFACE_TIMER
- GB_AUDIO_CTL_ELEM_TYPE_BOOLEAN
- GB_AUDIO_CTL_ELEM_TYPE_ENUMERATED
- GB_AUDIO_CTL_ELEM_TYPE_INTEGER
- GB_AUDIO_CTL_ELEM_TYPE_INTEGER64
- GB_AUDIO_INVALID_INDEX
- GB_AUDIO_JACK_ANC_HEADPHONE
- GB_AUDIO_JACK_AVOUT
- GB_AUDIO_JACK_BTN_0
- GB_AUDIO_JACK_BTN_1
- GB_AUDIO_JACK_BTN_2
- GB_AUDIO_JACK_BTN_3
- GB_AUDIO_JACK_EVENT_INSERTION
- GB_AUDIO_JACK_EVENT_REMOVAL
- GB_AUDIO_JACK_HEADPHONE
- GB_AUDIO_JACK_HEADSET
- GB_AUDIO_JACK_LINEIN
- GB_AUDIO_JACK_LINEOUT
- GB_AUDIO_JACK_MECHANICAL
- GB_AUDIO_JACK_MICROPHONE
- GB_AUDIO_JACK_MICROPHONE2
- GB_AUDIO_JACK_OC_HPHL
- GB_AUDIO_JACK_OC_HPHR
- GB_AUDIO_JACK_VIDEOOUT
- GB_AUDIO_MANAGER_MODULE_NAME_LEN
- GB_AUDIO_MANAGER_MODULE_NAME_LEN_SSCANF
- GB_AUDIO_MANAGER_NAME
- GB_AUDIO_PCM_FMT_S16_BE
- GB_AUDIO_PCM_FMT_S16_LE
- GB_AUDIO_PCM_FMT_S24_BE
- GB_AUDIO_PCM_FMT_S24_LE
- GB_AUDIO_PCM_FMT_S32_BE
- GB_AUDIO_PCM_FMT_S32_LE
- GB_AUDIO_PCM_FMT_S8
- GB_AUDIO_PCM_FMT_U16_BE
- GB_AUDIO_PCM_FMT_U16_LE
- GB_AUDIO_PCM_FMT_U24_BE
- GB_AUDIO_PCM_FMT_U24_LE
- GB_AUDIO_PCM_FMT_U32_BE
- GB_AUDIO_PCM_FMT_U32_LE
- GB_AUDIO_PCM_FMT_U8
- GB_AUDIO_PCM_NAME_MAX
- GB_AUDIO_PCM_RATE_11025
- GB_AUDIO_PCM_RATE_16000
- GB_AUDIO_PCM_RATE_176400
- GB_AUDIO_PCM_RATE_192000
- GB_AUDIO_PCM_RATE_22050
- GB_AUDIO_PCM_RATE_32000
- GB_AUDIO_PCM_RATE_44100
- GB_AUDIO_PCM_RATE_48000
- GB_AUDIO_PCM_RATE_5512
- GB_AUDIO_PCM_RATE_64000
- GB_AUDIO_PCM_RATE_8000
- GB_AUDIO_PCM_RATE_88200
- GB_AUDIO_PCM_RATE_96000
- GB_AUDIO_SAMPLE_BUFFER_MIN_US
- GB_AUDIO_STREAMING_EVENT_CLOCKING
- GB_AUDIO_STREAMING_EVENT_DATA_LEN
- GB_AUDIO_STREAMING_EVENT_FAILURE
- GB_AUDIO_STREAMING_EVENT_HALT
- GB_AUDIO_STREAMING_EVENT_INTERNAL_ERROR
- GB_AUDIO_STREAMING_EVENT_OVERRUN
- GB_AUDIO_STREAMING_EVENT_PROTOCOL_ERROR
- GB_AUDIO_STREAMING_EVENT_UNDERRUN
- GB_AUDIO_STREAMING_EVENT_UNSPECIFIED
- GB_AUDIO_STREAM_TYPE_CAPTURE
- GB_AUDIO_STREAM_TYPE_PLAYBACK
- GB_AUDIO_TYPE_ACTIVATE_RX
- GB_AUDIO_TYPE_ACTIVATE_TX
- GB_AUDIO_TYPE_BUTTON_EVENT
- GB_AUDIO_TYPE_DEACTIVATE_RX
- GB_AUDIO_TYPE_DEACTIVATE_TX
- GB_AUDIO_TYPE_DISABLE_WIDGET
- GB_AUDIO_TYPE_ENABLE_WIDGET
- GB_AUDIO_TYPE_GET_CONTROL
- GB_AUDIO_TYPE_GET_PCM
- GB_AUDIO_TYPE_GET_TOPOLOGY
- GB_AUDIO_TYPE_GET_TOPOLOGY_SIZE
- GB_AUDIO_TYPE_JACK_EVENT
- GB_AUDIO_TYPE_SEND_DATA
- GB_AUDIO_TYPE_SET_CONTROL
- GB_AUDIO_TYPE_SET_PCM
- GB_AUDIO_TYPE_SET_RX_DATA_SIZE
- GB_AUDIO_TYPE_SET_TX_DATA_SIZE
- GB_AUDIO_TYPE_STREAMING_EVENT
- GB_AUDIO_WIDGET_STATE_DISABLED
- GB_AUDIO_WIDGET_STATE_ENAABLED
- GB_AUDIO_WIDGET_TYPE_ADC
- GB_AUDIO_WIDGET_TYPE_AIF_IN
- GB_AUDIO_WIDGET_TYPE_AIF_OUT
- GB_AUDIO_WIDGET_TYPE_CLOCK_SUPPLY
- GB_AUDIO_WIDGET_TYPE_DAC
- GB_AUDIO_WIDGET_TYPE_DAI_IN
- GB_AUDIO_WIDGET_TYPE_DAI_LINK
- GB_AUDIO_WIDGET_TYPE_DAI_OUT
- GB_AUDIO_WIDGET_TYPE_HP
- GB_AUDIO_WIDGET_TYPE_INPUT
- GB_AUDIO_WIDGET_TYPE_LINE
- GB_AUDIO_WIDGET_TYPE_MIC
- GB_AUDIO_WIDGET_TYPE_MICBIAS
- GB_AUDIO_WIDGET_TYPE_MIXER
- GB_AUDIO_WIDGET_TYPE_MIXER_NAMED_CTL
- GB_AUDIO_WIDGET_TYPE_MUX
- GB_AUDIO_WIDGET_TYPE_OUTPUT
- GB_AUDIO_WIDGET_TYPE_OUT_DRV
- GB_AUDIO_WIDGET_TYPE_PGA
- GB_AUDIO_WIDGET_TYPE_POST
- GB_AUDIO_WIDGET_TYPE_PRE
- GB_AUDIO_WIDGET_TYPE_REGULATOR_SUPPLY
- GB_AUDIO_WIDGET_TYPE_SIGGEN
- GB_AUDIO_WIDGET_TYPE_SPK
- GB_AUDIO_WIDGET_TYPE_SUPPLY
- GB_AUDIO_WIDGET_TYPE_SWITCH
- GB_AUDIO_WIDGET_TYPE_VALUE_MUX
- GB_AUDIO_WIDGET_TYPE_VIRT_MUX
- GB_AUDIO_WIDGET_TYPE_VMID
- GB_BACKEND_MAP
- GB_BACKEND_MAP__BACKEND_MAP_MASK
- GB_BACKEND_MAP__BACKEND_MAP__SHIFT
- GB_BOOTROM_BOOT_STAGE_ONE
- GB_BOOTROM_BOOT_STAGE_THREE
- GB_BOOTROM_BOOT_STAGE_TWO
- GB_BOOTROM_BOOT_STATUS_INSECURE
- GB_BOOTROM_BOOT_STATUS_INVALID
- GB_BOOTROM_BOOT_STATUS_SECURE
- GB_BOOTROM_FETCH_MAX
- GB_BOOTROM_TYPE_AP_READY
- GB_BOOTROM_TYPE_FIRMWARE_SIZE
- GB_BOOTROM_TYPE_GET_FIRMWARE
- GB_BOOTROM_TYPE_GET_VID_PID
- GB_BOOTROM_TYPE_READY_TO_BOOT
- GB_BOOTROM_TYPE_VERSION
- GB_BOOTROM_VERSION_MAJOR
- GB_BOOTROM_VERSION_MINOR
- GB_BUNDLE_AUTOSUSPEND_MS
- GB_CAMERA_CONFIGURE_STREAMS_ADJUSTED
- GB_CAMERA_CONFIGURE_STREAMS_TEST_ONLY
- GB_CAMERA_CSI_CLK_FREQ_MARGIN
- GB_CAMERA_CSI_CLK_FREQ_MAX
- GB_CAMERA_CSI_CLK_FREQ_MIN
- GB_CAMERA_CSI_FLAG_CLOCK_CONTINUOUS
- GB_CAMERA_CSI_NUM_DATA_LANES
- GB_CAMERA_DEBUGFS_BUFFER_CAPABILITIES
- GB_CAMERA_DEBUGFS_BUFFER_CAPTURE
- GB_CAMERA_DEBUGFS_BUFFER_FLUSH
- GB_CAMERA_DEBUGFS_BUFFER_MAX
- GB_CAMERA_DEBUGFS_BUFFER_STREAMS
- GB_CAMERA_IN_FLAG_TEST
- GB_CAMERA_MAX_SETTINGS_SIZE
- GB_CAMERA_MAX_STREAMS
- GB_CAMERA_OUT_FLAG_ADJUSTED
- GB_CAMERA_STATE_CONFIGURED
- GB_CAMERA_STATE_UNCONFIGURED
- GB_CAMERA_TYPE_CAPABILITIES
- GB_CAMERA_TYPE_CAPTURE
- GB_CAMERA_TYPE_CONFIGURE_STREAMS
- GB_CAMERA_TYPE_FLUSH
- GB_CAMERA_TYPE_METADATA
- GB_CAPTURE
- GB_CAP_TYPE_AUTHENTICATE
- GB_CAP_TYPE_GET_ENDPOINT_UID
- GB_CAP_TYPE_GET_IMS_CERTIFICATE
- GB_CHANNEL_MODE_ATTENTION
- GB_CHANNEL_MODE_BATTERY
- GB_CHANNEL_MODE_BLUETOOTH
- GB_CHANNEL_MODE_BUTTONS
- GB_CHANNEL_MODE_DEFINED_RANGE
- GB_CHANNEL_MODE_FLASH
- GB_CHANNEL_MODE_INDICATOR
- GB_CHANNEL_MODE_KEYBOARD
- GB_CHANNEL_MODE_NONE
- GB_CHANNEL_MODE_NOTIFICATION
- GB_CHANNEL_MODE_POWER
- GB_CHANNEL_MODE_TORCH
- GB_CHANNEL_MODE_VENDOR_RANGE
- GB_CHANNEL_MODE_WIRELESS
- GB_CHIP_ID
- GB_CONNECTION_CPORT_QUIESCE_TIMEOUT
- GB_CONNECTION_FLAG_CDSI1
- GB_CONNECTION_FLAG_CONTROL
- GB_CONNECTION_FLAG_CORE_MASK
- GB_CONNECTION_FLAG_CSD
- GB_CONNECTION_FLAG_HIGH_PRIO
- GB_CONNECTION_FLAG_NO_FLOWCTRL
- GB_CONNECTION_FLAG_OFFLOADED
- GB_CONNECTION_STATE_DISABLED
- GB_CONNECTION_STATE_DISCONNECTING
- GB_CONNECTION_STATE_ENABLED
- GB_CONNECTION_STATE_ENABLED_TX
- GB_CONTROL_BUNDLE_ID
- GB_CONTROL_BUNDLE_PM_BUSY
- GB_CONTROL_BUNDLE_PM_FAIL
- GB_CONTROL_BUNDLE_PM_INVAL
- GB_CONTROL_BUNDLE_PM_NA
- GB_CONTROL_BUNDLE_PM_OK
- GB_CONTROL_CPORT_ID
- GB_CONTROL_INTF_PM_BUSY
- GB_CONTROL_INTF_PM_NA
- GB_CONTROL_INTF_PM_OK
- GB_CONTROL_TYPE_BUNDLE_ACTIVATE
- GB_CONTROL_TYPE_BUNDLE_DEACTIVATE
- GB_CONTROL_TYPE_BUNDLE_RESUME
- GB_CONTROL_TYPE_BUNDLE_SUSPEND
- GB_CONTROL_TYPE_BUNDLE_VERSION
- GB_CONTROL_TYPE_CONNECTED
- GB_CONTROL_TYPE_DISCONNECTED
- GB_CONTROL_TYPE_DISCONNECTING
- GB_CONTROL_TYPE_GET_MANIFEST
- GB_CONTROL_TYPE_GET_MANIFEST_SIZE
- GB_CONTROL_TYPE_INTF_DEACTIVATE_PREPARE
- GB_CONTROL_TYPE_INTF_HIBERNATE_ABORT
- GB_CONTROL_TYPE_INTF_SUSPEND_PREPARE
- GB_CONTROL_TYPE_MODE_SWITCH
- GB_CONTROL_TYPE_PROBE_AP
- GB_CONTROL_TYPE_TIMESYNC_AUTHORITATIVE
- GB_CONTROL_TYPE_TIMESYNC_DISABLE
- GB_CONTROL_TYPE_TIMESYNC_ENABLE
- GB_CONTROL_TYPE_TIMESYNC_GET_LAST_EVENT
- GB_CONTROL_TYPE_VERSION
- GB_CONTROL_VERSION_MAJOR
- GB_CONTROL_VERSION_MINOR
- GB_EDC_DED_MODE
- GB_EDC_DED_MODE_HALT
- GB_EDC_DED_MODE_INT_HALT
- GB_EDC_DED_MODE_LOG
- GB_EDC_MODE__BYPASS_MASK
- GB_EDC_MODE__BYPASS__SHIFT
- GB_EDC_MODE__COUNT_FED_OUT_MASK
- GB_EDC_MODE__COUNT_FED_OUT__SHIFT
- GB_EDC_MODE__DED_MODE_MASK
- GB_EDC_MODE__DED_MODE__SHIFT
- GB_EDC_MODE__FORCE_SEC_ON_DED_MASK
- GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT
- GB_EDC_MODE__GATE_FUE_MASK
- GB_EDC_MODE__GATE_FUE__SHIFT
- GB_EDC_MODE__PROP_FED_MASK
- GB_EDC_MODE__PROP_FED__SHIFT
- GB_ENABLE
- GB_FIRMWARE_TAG_MAX_SIZE
- GB_FIRMWARE_U_TAG_MAX_SIZE
- GB_FW_BACKEND_FW_STATUS_FAIL_FETCH
- GB_FW_BACKEND_FW_STATUS_FAIL_FIND
- GB_FW_BACKEND_FW_STATUS_FAIL_WRITE
- GB_FW_BACKEND_FW_STATUS_INT
- GB_FW_BACKEND_FW_STATUS_NOT_SUPPORTED
- GB_FW_BACKEND_FW_STATUS_RETRY
- GB_FW_BACKEND_FW_STATUS_SUCCESS
- GB_FW_BACKEND_VERSION_STATUS_FAIL_INT
- GB_FW_BACKEND_VERSION_STATUS_NOT_AVAILABLE
- GB_FW_BACKEND_VERSION_STATUS_NOT_SUPPORTED
- GB_FW_BACKEND_VERSION_STATUS_RETRY
- GB_FW_BACKEND_VERSION_STATUS_SUCCESS
- GB_FW_DOWNLOAD_TYPE_FETCH_FIRMWARE
- GB_FW_DOWNLOAD_TYPE_FIND_FIRMWARE
- GB_FW_DOWNLOAD_TYPE_RELEASE_FIRMWARE
- GB_FW_LOAD_METHOD_INTERNAL
- GB_FW_LOAD_METHOD_UNIPRO
- GB_FW_LOAD_STATUS_FAILED
- GB_FW_LOAD_STATUS_UNVALIDATED
- GB_FW_LOAD_STATUS_VALIDATED
- GB_FW_LOAD_STATUS_VALIDATION_FAILED
- GB_FW_MGMT_TYPE_BACKEND_FW_UPDATE
- GB_FW_MGMT_TYPE_BACKEND_FW_UPDATED
- GB_FW_MGMT_TYPE_BACKEND_FW_VERSION
- GB_FW_MGMT_TYPE_INTERFACE_FW_VERSION
- GB_FW_MGMT_TYPE_LOADED_FW
- GB_FW_MGMT_TYPE_LOAD_AND_VALIDATE_FW
- GB_FW_U_BACKEND_FW_STATUS_FAIL_FETCH
- GB_FW_U_BACKEND_FW_STATUS_FAIL_FIND
- GB_FW_U_BACKEND_FW_STATUS_FAIL_WRITE
- GB_FW_U_BACKEND_FW_STATUS_INT
- GB_FW_U_BACKEND_FW_STATUS_NOT_SUPPORTED
- GB_FW_U_BACKEND_FW_STATUS_RETRY
- GB_FW_U_BACKEND_FW_STATUS_SUCCESS
- GB_FW_U_BACKEND_VERSION_STATUS_FAIL_INT
- GB_FW_U_BACKEND_VERSION_STATUS_NOT_AVAILABLE
- GB_FW_U_BACKEND_VERSION_STATUS_NOT_SUPPORTED
- GB_FW_U_BACKEND_VERSION_STATUS_RETRY
- GB_FW_U_BACKEND_VERSION_STATUS_SUCCESS
- GB_FW_U_LOAD_METHOD_INTERNAL
- GB_FW_U_LOAD_METHOD_UNIPRO
- GB_FW_U_LOAD_STATUS_FAILED
- GB_FW_U_LOAD_STATUS_UNVALIDATED
- GB_FW_U_LOAD_STATUS_VALIDATED
- GB_FW_U_LOAD_STATUS_VALIDATION_FAILED
- GB_GBPHY_AUTOSUSPEND_MS
- GB_GPIO_IRQ_TYPE_EDGE_BOTH
- GB_GPIO_IRQ_TYPE_EDGE_FALLING
- GB_GPIO_IRQ_TYPE_EDGE_RISING
- GB_GPIO_IRQ_TYPE_LEVEL_HIGH
- GB_GPIO_IRQ_TYPE_LEVEL_LOW
- GB_GPIO_IRQ_TYPE_NONE
- GB_GPIO_TYPE_ACTIVATE
- GB_GPIO_TYPE_DEACTIVATE
- GB_GPIO_TYPE_DIRECTION_IN
- GB_GPIO_TYPE_DIRECTION_OUT
- GB_GPIO_TYPE_GET_DIRECTION
- GB_GPIO_TYPE_GET_VALUE
- GB_GPIO_TYPE_IRQ_EVENT
- GB_GPIO_TYPE_IRQ_MASK
- GB_GPIO_TYPE_IRQ_TYPE
- GB_GPIO_TYPE_IRQ_UNMASK
- GB_GPIO_TYPE_LINE_COUNT
- GB_GPIO_TYPE_SET_DEBOUNCE
- GB_GPIO_TYPE_SET_VALUE
- GB_GPU_ID__GPU_ID_MASK
- GB_GPU_ID__GPU_ID__SHIFT
- GB_HID_FEATURE_REPORT
- GB_HID_INPUT_REPORT
- GB_HID_OUTPUT_REPORT
- GB_HID_READ_PENDING
- GB_HID_STARTED
- GB_HID_TYPE_GET_DESC
- GB_HID_TYPE_GET_REPORT
- GB_HID_TYPE_GET_REPORT_DESC
- GB_HID_TYPE_IRQ_EVENT
- GB_HID_TYPE_PWR_OFF
- GB_HID_TYPE_PWR_ON
- GB_HID_TYPE_SET_REPORT
- GB_I2C_TYPE_FUNCTIONALITY
- GB_I2C_TYPE_TRANSFER
- GB_INIT_BOOTROM_FALLBACK_UNIPRO_BOOT_STARTED
- GB_INIT_BOOTROM_UNIPRO_BOOT_STARTED
- GB_INIT_S2_LOADER_BOOT_STARTED
- GB_INIT_SPI_BOOT_STARTED
- GB_INIT_TRUSTED_SPI_BOOT_FINISHED
- GB_INIT_UNTRUSTED_SPI_BOOT_FINISHED
- GB_INTERFACE_AUTOSUSPEND_MS
- GB_INTERFACE_DEVICE_ID_BAD
- GB_INTERFACE_MODE_SWITCH_TIMEOUT
- GB_INTERFACE_QUIRK_FORCED_DISABLE
- GB_INTERFACE_QUIRK_LEGACY_MODE_SWITCH
- GB_INTERFACE_QUIRK_NO_BUNDLE_ACTIVATE
- GB_INTERFACE_QUIRK_NO_CPORT_FEATURES
- GB_INTERFACE_QUIRK_NO_GMP_IDS
- GB_INTERFACE_QUIRK_NO_INIT_STATUS
- GB_INTERFACE_QUIRK_NO_PM
- GB_INTERFACE_SUSPEND_HIBERNATE_DELAY_MS
- GB_INTERFACE_TYPE_DUMMY
- GB_INTERFACE_TYPE_GREYBUS
- GB_INTERFACE_TYPE_INVALID
- GB_INTERFACE_TYPE_UNIPRO
- GB_INTERFACE_TYPE_UNKNOWN
- GB_KEYCODE_ARA
- GB_LIGHTS_FLASH_FAULT_INDICATOR
- GB_LIGHTS_FLASH_FAULT_INPUT_VOLTAGE
- GB_LIGHTS_FLASH_FAULT_LED_OVER_TEMPERATURE
- GB_LIGHTS_FLASH_FAULT_OVER_CURRENT
- GB_LIGHTS_FLASH_FAULT_OVER_TEMPERATURE
- GB_LIGHTS_FLASH_FAULT_OVER_VOLTAGE
- GB_LIGHTS_FLASH_FAULT_SHORT_CIRCUIT
- GB_LIGHTS_FLASH_FAULT_TIMEOUT
- GB_LIGHTS_FLASH_FAULT_UNDER_VOLTAGE
- GB_LIGHTS_LIGHT_CONFIG
- GB_LIGHTS_TYPE_EVENT
- GB_LIGHTS_TYPE_GET_CHANNEL_CONFIG
- GB_LIGHTS_TYPE_GET_CHANNEL_FLASH_CONFIG
- GB_LIGHTS_TYPE_GET_FLASH_FAULT
- GB_LIGHTS_TYPE_GET_LIGHTS
- GB_LIGHTS_TYPE_GET_LIGHT_CONFIG
- GB_LIGHTS_TYPE_SET_BLINK
- GB_LIGHTS_TYPE_SET_BRIGHTNESS
- GB_LIGHTS_TYPE_SET_COLOR
- GB_LIGHTS_TYPE_SET_FADE
- GB_LIGHTS_TYPE_SET_FLASH_INTENSITY
- GB_LIGHTS_TYPE_SET_FLASH_STROBE
- GB_LIGHTS_TYPE_SET_FLASH_TIMEOUT
- GB_LIGHT_CHANNEL_BLINK
- GB_LIGHT_CHANNEL_FADER
- GB_LIGHT_CHANNEL_MULTICOLOR
- GB_LOG_MAX_LEN
- GB_LOG_TYPE_SEND_LOG
- GB_LOOPBACK_FIFO_DEFAULT
- GB_LOOPBACK_TIMEOUT_MAX
- GB_LOOPBACK_TIMEOUT_MIN
- GB_LOOPBACK_TYPE_PING
- GB_LOOPBACK_TYPE_SINK
- GB_LOOPBACK_TYPE_TRANSFER
- GB_LOOPBACK_US_WAIT_MAX
- GB_MACROTILE_MODE0
- GB_MACROTILE_MODE0__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE0__BANK_WIDTH_MASK
- GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE0__NUM_BANKS_MASK
- GB_MACROTILE_MODE0__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE10__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE10__BANK_WIDTH_MASK
- GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE10__NUM_BANKS_MASK
- GB_MACROTILE_MODE10__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE11__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE11__BANK_WIDTH_MASK
- GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE11__NUM_BANKS_MASK
- GB_MACROTILE_MODE11__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE12__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE12__BANK_WIDTH_MASK
- GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE12__NUM_BANKS_MASK
- GB_MACROTILE_MODE12__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE13__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE13__BANK_WIDTH_MASK
- GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE13__NUM_BANKS_MASK
- GB_MACROTILE_MODE13__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE14__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE14__BANK_WIDTH_MASK
- GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE14__NUM_BANKS_MASK
- GB_MACROTILE_MODE14__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE15__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE15__BANK_WIDTH_MASK
- GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE15__NUM_BANKS_MASK
- GB_MACROTILE_MODE15__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE1__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE1__BANK_WIDTH_MASK
- GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE1__NUM_BANKS_MASK
- GB_MACROTILE_MODE1__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE2__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE2__BANK_WIDTH_MASK
- GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE2__NUM_BANKS_MASK
- GB_MACROTILE_MODE2__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE3__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE3__BANK_WIDTH_MASK
- GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE3__NUM_BANKS_MASK
- GB_MACROTILE_MODE3__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE4__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE4__BANK_WIDTH_MASK
- GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE4__NUM_BANKS_MASK
- GB_MACROTILE_MODE4__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE5__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE5__BANK_WIDTH_MASK
- GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE5__NUM_BANKS_MASK
- GB_MACROTILE_MODE5__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE6__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE6__BANK_WIDTH_MASK
- GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE6__NUM_BANKS_MASK
- GB_MACROTILE_MODE6__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE7__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE7__BANK_WIDTH_MASK
- GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE7__NUM_BANKS_MASK
- GB_MACROTILE_MODE7__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE8__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE8__BANK_WIDTH_MASK
- GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE8__NUM_BANKS_MASK
- GB_MACROTILE_MODE8__NUM_BANKS__SHIFT
- GB_MACROTILE_MODE9__BANK_HEIGHT_MASK
- GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT
- GB_MACROTILE_MODE9__BANK_WIDTH_MASK
- GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT
- GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK
- GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT
- GB_MACROTILE_MODE9__NUM_BANKS_MASK
- GB_MACROTILE_MODE9__NUM_BANKS__SHIFT
- GB_MESSAGE_TYPE_RESPONSE
- GB_MSPOS0
- GB_MSPOS1
- GB_NAME
- GB_NUM_MINORS
- GB_OPERATION_FLAG_CORE
- GB_OPERATION_FLAG_INCOMING
- GB_OPERATION_FLAG_SHORT_RESPONSE
- GB_OPERATION_FLAG_UNIDIRECTIONAL
- GB_OPERATION_FLAG_USER_MASK
- GB_OPERATION_MESSAGE_SIZE_MAX
- GB_OPERATION_MESSAGE_SIZE_MIN
- GB_OPERATION_TIMEOUT_DEFAULT
- GB_OP_INTERRUPTED
- GB_OP_INVALID
- GB_OP_MALFUNCTION
- GB_OP_NONEXISTENT
- GB_OP_NO_MEMORY
- GB_OP_OVERFLOW
- GB_OP_PROTOCOL_BAD
- GB_OP_RETRY
- GB_OP_SUCCESS
- GB_OP_TIMEOUT
- GB_OP_UNKNOWN_ERROR
- GB_PIPE_SELECT
- GB_PLAYBACK
- GB_POWER_SUPPLY_BATTERY_TYPE
- GB_POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL
- GB_POWER_SUPPLY_CAPACITY_LEVEL_FULL
- GB_POWER_SUPPLY_CAPACITY_LEVEL_HIGH
- GB_POWER_SUPPLY_CAPACITY_LEVEL_LOW
- GB_POWER_SUPPLY_CAPACITY_LEVEL_NORMAL
- GB_POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN
- GB_POWER_SUPPLY_HEALTH_COLD
- GB_POWER_SUPPLY_HEALTH_DEAD
- GB_POWER_SUPPLY_HEALTH_GOOD
- GB_POWER_SUPPLY_HEALTH_OVERHEAT
- GB_POWER_SUPPLY_HEALTH_OVERVOLTAGE
- GB_POWER_SUPPLY_HEALTH_SAFETY_TIMER_EXPIRE
- GB_POWER_SUPPLY_HEALTH_UNKNOWN
- GB_POWER_SUPPLY_HEALTH_UNSPEC_FAILURE
- GB_POWER_SUPPLY_HEALTH_WATCHDOG_TIMER_EXPIRE
- GB_POWER_SUPPLY_MAINS_TYPE
- GB_POWER_SUPPLY_PROP_AUTHENTIC
- GB_POWER_SUPPLY_PROP_CALIBRATE
- GB_POWER_SUPPLY_PROP_CAPACITY
- GB_POWER_SUPPLY_PROP_CAPACITY_ALERT_MAX
- GB_POWER_SUPPLY_PROP_CAPACITY_ALERT_MIN
- GB_POWER_SUPPLY_PROP_CAPACITY_LEVEL
- GB_POWER_SUPPLY_PROP_CHARGE_AVG
- GB_POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT
- GB_POWER_SUPPLY_PROP_CHARGE_CONTROL_LIMIT_MAX
- GB_POWER_SUPPLY_PROP_CHARGE_COUNTER
- GB_POWER_SUPPLY_PROP_CHARGE_EMPTY
- GB_POWER_SUPPLY_PROP_CHARGE_EMPTY_DESIGN
- GB_POWER_SUPPLY_PROP_CHARGE_FULL
- GB_POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN
- GB_POWER_SUPPLY_PROP_CHARGE_NOW
- GB_POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT
- GB_POWER_SUPPLY_PROP_CHARGE_TYPE
- GB_POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT
- GB_POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX
- GB_POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE
- GB_POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX
- GB_POWER_SUPPLY_PROP_CURRENT_AVG
- GB_POWER_SUPPLY_PROP_CURRENT_BOOT
- GB_POWER_SUPPLY_PROP_CURRENT_MAX
- GB_POWER_SUPPLY_PROP_CURRENT_NOW
- GB_POWER_SUPPLY_PROP_CYCLE_COUNT
- GB_POWER_SUPPLY_PROP_ENERGY_AVG
- GB_POWER_SUPPLY_PROP_ENERGY_EMPTY
- GB_POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN
- GB_POWER_SUPPLY_PROP_ENERGY_FULL
- GB_POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN
- GB_POWER_SUPPLY_PROP_ENERGY_NOW
- GB_POWER_SUPPLY_PROP_HEALTH
- GB_POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT
- GB_POWER_SUPPLY_PROP_ONLINE
- GB_POWER_SUPPLY_PROP_POWER_AVG
- GB_POWER_SUPPLY_PROP_POWER_NOW
- GB_POWER_SUPPLY_PROP_PRESENT
- GB_POWER_SUPPLY_PROP_SCOPE
- GB_POWER_SUPPLY_PROP_STATUS
- GB_POWER_SUPPLY_PROP_TECHNOLOGY
- GB_POWER_SUPPLY_PROP_TEMP
- GB_POWER_SUPPLY_PROP_TEMP_ALERT_MAX
- GB_POWER_SUPPLY_PROP_TEMP_ALERT_MIN
- GB_POWER_SUPPLY_PROP_TEMP_AMBIENT
- GB_POWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MAX
- GB_POWER_SUPPLY_PROP_TEMP_AMBIENT_ALERT_MIN
- GB_POWER_SUPPLY_PROP_TEMP_MAX
- GB_POWER_SUPPLY_PROP_TEMP_MIN
- GB_POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG
- GB_POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW
- GB_POWER_SUPPLY_PROP_TIME_TO_FULL_AVG
- GB_POWER_SUPPLY_PROP_TIME_TO_FULL_NOW
- GB_POWER_SUPPLY_PROP_TYPE
- GB_POWER_SUPPLY_PROP_VOLTAGE_AVG
- GB_POWER_SUPPLY_PROP_VOLTAGE_BOOT
- GB_POWER_SUPPLY_PROP_VOLTAGE_MAX
- GB_POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN
- GB_POWER_SUPPLY_PROP_VOLTAGE_MIN
- GB_POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN
- GB_POWER_SUPPLY_PROP_VOLTAGE_NOW
- GB_POWER_SUPPLY_PROP_VOLTAGE_OCV
- GB_POWER_SUPPLY_SCOPE_DEVICE
- GB_POWER_SUPPLY_SCOPE_SYSTEM
- GB_POWER_SUPPLY_SCOPE_UNKNOWN
- GB_POWER_SUPPLY_STATUS_CHARGING
- GB_POWER_SUPPLY_STATUS_DISCHARGING
- GB_POWER_SUPPLY_STATUS_FULL
- GB_POWER_SUPPLY_STATUS_NOT_CHARGING
- GB_POWER_SUPPLY_STATUS_UNKNOWN
- GB_POWER_SUPPLY_TECH_LION
- GB_POWER_SUPPLY_TECH_LIPO
- GB_POWER_SUPPLY_TECH_LiFe
- GB_POWER_SUPPLY_TECH_LiMn
- GB_POWER_SUPPLY_TECH_NiCd
- GB_POWER_SUPPLY_TECH_NiMH
- GB_POWER_SUPPLY_TECH_UNKNOWN
- GB_POWER_SUPPLY_TYPE_EVENT
- GB_POWER_SUPPLY_TYPE_GET_DESCRIPTION
- GB_POWER_SUPPLY_TYPE_GET_PROPERTY
- GB_POWER_SUPPLY_TYPE_GET_PROP_DESCRIPTORS
- GB_POWER_SUPPLY_TYPE_GET_SUPPLIES
- GB_POWER_SUPPLY_TYPE_SET_PROPERTY
- GB_POWER_SUPPLY_UNKNOWN_TYPE
- GB_POWER_SUPPLY_UPDATE
- GB_POWER_SUPPLY_UPS_TYPE
- GB_POWER_SUPPLY_USB_ACA_TYPE
- GB_POWER_SUPPLY_USB_CDP_TYPE
- GB_POWER_SUPPLY_USB_DCP_TYPE
- GB_POWER_SUPPLY_USB_TYPE
- GB_PWM_TYPE_ACTIVATE
- GB_PWM_TYPE_CONFIG
- GB_PWM_TYPE_DEACTIVATE
- GB_PWM_TYPE_DISABLE
- GB_PWM_TYPE_ENABLE
- GB_PWM_TYPE_POLARITY
- GB_PWM_TYPE_PWM_COUNT
- GB_RAW_TYPE_SEND
- GB_REQUEST_TYPE_CPORT_SHUTDOWN
- GB_REQUEST_TYPE_INVALID
- GB_SDIO_BUSMODE_OPENDRAIN
- GB_SDIO_BUSMODE_PUSHPULL
- GB_SDIO_BUS_WIDTH_1
- GB_SDIO_BUS_WIDTH_4
- GB_SDIO_BUS_WIDTH_8
- GB_SDIO_CAP_1_2V_DDR
- GB_SDIO_CAP_1_8V_DDR
- GB_SDIO_CAP_4_BIT_DATA
- GB_SDIO_CAP_8_BIT_DATA
- GB_SDIO_CAP_DRIVER_TYPE_A
- GB_SDIO_CAP_DRIVER_TYPE_C
- GB_SDIO_CAP_DRIVER_TYPE_D
- GB_SDIO_CAP_ERASE
- GB_SDIO_CAP_HS200_1_2V
- GB_SDIO_CAP_HS200_1_8V
- GB_SDIO_CAP_HS400_1_2V
- GB_SDIO_CAP_HS400_1_8V
- GB_SDIO_CAP_MMC_HS
- GB_SDIO_CAP_NONREMOVABLE
- GB_SDIO_CAP_POWER_OFF_CARD
- GB_SDIO_CAP_SD_HS
- GB_SDIO_CAP_UHS_DDR50
- GB_SDIO_CAP_UHS_SDR104
- GB_SDIO_CAP_UHS_SDR12
- GB_SDIO_CAP_UHS_SDR25
- GB_SDIO_CAP_UHS_SDR50
- GB_SDIO_CARD_INSERTED
- GB_SDIO_CARD_REMOVED
- GB_SDIO_CMD_AC
- GB_SDIO_CMD_ADTC
- GB_SDIO_CMD_BC
- GB_SDIO_CMD_BCR
- GB_SDIO_DATA_READ
- GB_SDIO_DATA_STREAM
- GB_SDIO_DATA_WRITE
- GB_SDIO_POWER_OFF
- GB_SDIO_POWER_ON
- GB_SDIO_POWER_UNDEFINED
- GB_SDIO_POWER_UP
- GB_SDIO_RSP_136
- GB_SDIO_RSP_BUSY
- GB_SDIO_RSP_CRC
- GB_SDIO_RSP_NONE
- GB_SDIO_RSP_OPCODE
- GB_SDIO_RSP_PRESENT
- GB_SDIO_RSP_R1B
- GB_SDIO_RSP_R1_R5_R6_R7
- GB_SDIO_RSP_R2
- GB_SDIO_RSP_R3_R4
- GB_SDIO_SET_DRIVER_TYPE_A
- GB_SDIO_SET_DRIVER_TYPE_B
- GB_SDIO_SET_DRIVER_TYPE_C
- GB_SDIO_SET_DRIVER_TYPE_D
- GB_SDIO_SIGNAL_VOLTAGE_120
- GB_SDIO_SIGNAL_VOLTAGE_180
- GB_SDIO_SIGNAL_VOLTAGE_330
- GB_SDIO_TIMING_LEGACY
- GB_SDIO_TIMING_MMC_DDR52
- GB_SDIO_TIMING_MMC_HS
- GB_SDIO_TIMING_MMC_HS200
- GB_SDIO_TIMING_MMC_HS400
- GB_SDIO_TIMING_SD_HS
- GB_SDIO_TIMING_UHS_DDR50
- GB_SDIO_TIMING_UHS_SDR104
- GB_SDIO_TIMING_UHS_SDR12
- GB_SDIO_TIMING_UHS_SDR25
- GB_SDIO_TIMING_UHS_SDR50
- GB_SDIO_TYPE_COMMAND
- GB_SDIO_TYPE_EVENT
- GB_SDIO_TYPE_GET_CAPABILITIES
- GB_SDIO_TYPE_SET_IOS
- GB_SDIO_TYPE_TRANSFER
- GB_SDIO_VDD_165_195
- GB_SDIO_VDD_20_21
- GB_SDIO_VDD_21_22
- GB_SDIO_VDD_22_23
- GB_SDIO_VDD_23_24
- GB_SDIO_VDD_24_25
- GB_SDIO_VDD_25_26
- GB_SDIO_VDD_26_27
- GB_SDIO_VDD_27_28
- GB_SDIO_VDD_28_29
- GB_SDIO_VDD_29_30
- GB_SDIO_VDD_30_31
- GB_SDIO_VDD_31_32
- GB_SDIO_VDD_32_33
- GB_SDIO_VDD_33_34
- GB_SDIO_VDD_34_35
- GB_SDIO_VDD_35_36
- GB_SDIO_VDD_SHIFT
- GB_SDIO_WP
- GB_SELECT
- GB_SERIAL_1_5_STOP_BITS
- GB_SERIAL_1_STOP_BITS
- GB_SERIAL_2_STOP_BITS
- GB_SERIAL_AUTO_RTSCTS_EN
- GB_SERIAL_EVEN_PARITY
- GB_SERIAL_FLAG_FLUSH_RECEIVER
- GB_SERIAL_FLAG_FLUSH_TRANSMITTER
- GB_SERIAL_MARK_PARITY
- GB_SERIAL_NO_PARITY
- GB_SERIAL_ODD_PARITY
- GB_SERIAL_SPACE_PARITY
- GB_SPI_FLAG_HALF_DUPLEX
- GB_SPI_FLAG_NO_RX
- GB_SPI_FLAG_NO_TX
- GB_SPI_MODE_3WIRE
- GB_SPI_MODE_CPHA
- GB_SPI_MODE_CPOL
- GB_SPI_MODE_CS_HIGH
- GB_SPI_MODE_LOOP
- GB_SPI_MODE_LSB_FIRST
- GB_SPI_MODE_MODE_0
- GB_SPI_MODE_MODE_1
- GB_SPI_MODE_MODE_2
- GB_SPI_MODE_MODE_3
- GB_SPI_MODE_NO_CS
- GB_SPI_MODE_READY
- GB_SPI_SPI_DEV
- GB_SPI_SPI_MODALIAS
- GB_SPI_SPI_NOR
- GB_SPI_STATE_MSG_DONE
- GB_SPI_STATE_MSG_ERROR
- GB_SPI_STATE_MSG_IDLE
- GB_SPI_STATE_MSG_RUNNING
- GB_SPI_STATE_OP_DONE
- GB_SPI_STATE_OP_READY
- GB_SPI_TYPE_DEVICE_CONFIG
- GB_SPI_TYPE_MASTER_CONFIG
- GB_SPI_TYPE_TRANSFER
- GB_SPI_XFER_INPROGRESS
- GB_SPI_XFER_READ
- GB_SPI_XFER_WRITE
- GB_SVC_CPORT_FLAG_CSD_N
- GB_SVC_CPORT_FLAG_CSV_N
- GB_SVC_CPORT_FLAG_E2EFC
- GB_SVC_CPORT_ID
- GB_SVC_DEVICE_ID_AP
- GB_SVC_DEVICE_ID_MAX
- GB_SVC_DEVICE_ID_MIN
- GB_SVC_DEVICE_ID_SVC
- GB_SVC_INTF_BAD_MBOX
- GB_SVC_INTF_MAILBOX_AP
- GB_SVC_INTF_MAILBOX_GREYBUS
- GB_SVC_INTF_MAILBOX_NONE
- GB_SVC_INTF_MBOX_SET
- GB_SVC_INTF_NOT_DETECTED
- GB_SVC_INTF_NO_ORDER
- GB_SVC_INTF_NO_REFCLK
- GB_SVC_INTF_NO_UPRO_LINK
- GB_SVC_INTF_NO_V_SYS
- GB_SVC_INTF_OP_TIMEOUT
- GB_SVC_INTF_REFCLK_FAIL
- GB_SVC_INTF_REFCLK_OK
- GB_SVC_INTF_RELEASING
- GB_SVC_INTF_TYPE_DUMMY
- GB_SVC_INTF_TYPE_GREYBUS
- GB_SVC_INTF_TYPE_UNIPRO
- GB_SVC_INTF_TYPE_UNKNOWN
- GB_SVC_INTF_UNIPRO_FAIL
- GB_SVC_INTF_UNIPRO_NOT_OFF
- GB_SVC_INTF_UNIPRO_OK
- GB_SVC_INTF_UPRO_NOT_DOWN
- GB_SVC_INTF_UPRO_NOT_HIBERNATED
- GB_SVC_INTF_VSYS_FAIL
- GB_SVC_INTF_VSYS_OK
- GB_SVC_INTF_V_CHG
- GB_SVC_INTF_WAKE_BUSY
- GB_SVC_KEY_PRESSED
- GB_SVC_KEY_RELEASED
- GB_SVC_LARGE_AMPLITUDE
- GB_SVC_LARGE_DE_EMPHASIS
- GB_SVC_MODULE_INSERTED_FLAG_NO_PRIMARY
- GB_SVC_NO_DE_EMPHASIS
- GB_SVC_OP_SUCCESS
- GB_SVC_OP_UNKNOWN_ERROR
- GB_SVC_PWRMON_GET_SAMPLE_HWERR
- GB_SVC_PWRMON_GET_SAMPLE_INVAL
- GB_SVC_PWRMON_GET_SAMPLE_NOSUPP
- GB_SVC_PWRMON_GET_SAMPLE_OK
- GB_SVC_PWRMON_MAX_RAIL_COUNT
- GB_SVC_PWRMON_OP_NOT_PRESENT
- GB_SVC_PWRMON_RAIL_NAME_BUFSIZE
- GB_SVC_PWRMON_TYPE_CURR
- GB_SVC_PWRMON_TYPE_PWR
- GB_SVC_PWRMON_TYPE_VOL
- GB_SVC_PWRM_LINE_RESET
- GB_SVC_PWRM_QUIRK_HSSER
- GB_SVC_PWRM_RXTERMINATION
- GB_SVC_PWRM_SCRAMBLING
- GB_SVC_PWRM_TXTERMINATION
- GB_SVC_SETPWRM_PWR_BUSY
- GB_SVC_SETPWRM_PWR_ERROR_CAP
- GB_SVC_SETPWRM_PWR_FATAL_ERROR
- GB_SVC_SETPWRM_PWR_LOCAL
- GB_SVC_SETPWRM_PWR_OK
- GB_SVC_SETPWRM_PWR_REMOTE
- GB_SVC_SMALL_AMPLITUDE
- GB_SVC_SMALL_DE_EMPHASIS
- GB_SVC_STATE_PROTOCOL_VERSION
- GB_SVC_STATE_RESET
- GB_SVC_STATE_SVC_HELLO
- GB_SVC_TYPE_CONN_CREATE
- GB_SVC_TYPE_CONN_DESTROY
- GB_SVC_TYPE_DME_PEER_GET
- GB_SVC_TYPE_DME_PEER_SET
- GB_SVC_TYPE_INTF_ACTIVATE
- GB_SVC_TYPE_INTF_DEVICE_ID
- GB_SVC_TYPE_INTF_EJECT
- GB_SVC_TYPE_INTF_MAILBOX_EVENT
- GB_SVC_TYPE_INTF_OOPS
- GB_SVC_TYPE_INTF_REFCLK_DISABLE
- GB_SVC_TYPE_INTF_REFCLK_ENABLE
- GB_SVC_TYPE_INTF_RESET
- GB_SVC_TYPE_INTF_RESUME
- GB_SVC_TYPE_INTF_SET_PWRM
- GB_SVC_TYPE_INTF_UNIPRO_DISABLE
- GB_SVC_TYPE_INTF_UNIPRO_ENABLE
- GB_SVC_TYPE_INTF_VSYS_DISABLE
- GB_SVC_TYPE_INTF_VSYS_ENABLE
- GB_SVC_TYPE_MODULE_INSERTED
- GB_SVC_TYPE_MODULE_REMOVED
- GB_SVC_TYPE_PING
- GB_SVC_TYPE_PROTOCOL_VERSION
- GB_SVC_TYPE_PWRMON_INTF_SAMPLE_GET
- GB_SVC_TYPE_PWRMON_RAIL_COUNT_GET
- GB_SVC_TYPE_PWRMON_RAIL_NAMES_GET
- GB_SVC_TYPE_PWRMON_SAMPLE_GET
- GB_SVC_TYPE_ROUTE_CREATE
- GB_SVC_TYPE_ROUTE_DESTROY
- GB_SVC_TYPE_SVC_HELLO
- GB_SVC_TYPE_TIMESYNC_AUTHORITATIVE
- GB_SVC_TYPE_TIMESYNC_DISABLE
- GB_SVC_TYPE_TIMESYNC_ENABLE
- GB_SVC_TYPE_TIMESYNC_PING
- GB_SVC_TYPE_TIMESYNC_WAKE_PINS_ACQUIRE
- GB_SVC_TYPE_TIMESYNC_WAKE_PINS_RELEASE
- GB_SVC_UNIPRO_FAST_AUTO_MODE
- GB_SVC_UNIPRO_FAST_MODE
- GB_SVC_UNIPRO_HIBERNATE_MODE
- GB_SVC_UNIPRO_HS_SERIES_A
- GB_SVC_UNIPRO_HS_SERIES_B
- GB_SVC_UNIPRO_MODE_UNCHANGED
- GB_SVC_UNIPRO_OFF_MODE
- GB_SVC_UNIPRO_SLOW_AUTO_MODE
- GB_SVC_UNIPRO_SLOW_MODE
- GB_SVC_VERSION_MAJOR
- GB_SVC_VERSION_MINOR
- GB_SVC_WATCHDOG_BITE_PANIC_KERNEL
- GB_SVC_WATCHDOG_BITE_RESET_UNIPRO
- GB_TILE_CONFIG
- GB_TILE_MODE0
- GB_TILE_MODE0__ARRAY_MODE_MASK
- GB_TILE_MODE0__ARRAY_MODE__SHIFT
- GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE0__PIPE_CONFIG_MASK
- GB_TILE_MODE0__PIPE_CONFIG__SHIFT
- GB_TILE_MODE0__SAMPLE_SPLIT_MASK
- GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE0__TILE_SPLIT_MASK
- GB_TILE_MODE0__TILE_SPLIT__SHIFT
- GB_TILE_MODE1
- GB_TILE_MODE10
- GB_TILE_MODE10__ARRAY_MODE_MASK
- GB_TILE_MODE10__ARRAY_MODE__SHIFT
- GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE10__PIPE_CONFIG_MASK
- GB_TILE_MODE10__PIPE_CONFIG__SHIFT
- GB_TILE_MODE10__SAMPLE_SPLIT_MASK
- GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE10__TILE_SPLIT_MASK
- GB_TILE_MODE10__TILE_SPLIT__SHIFT
- GB_TILE_MODE11
- GB_TILE_MODE11__ARRAY_MODE_MASK
- GB_TILE_MODE11__ARRAY_MODE__SHIFT
- GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE11__PIPE_CONFIG_MASK
- GB_TILE_MODE11__PIPE_CONFIG__SHIFT
- GB_TILE_MODE11__SAMPLE_SPLIT_MASK
- GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE11__TILE_SPLIT_MASK
- GB_TILE_MODE11__TILE_SPLIT__SHIFT
- GB_TILE_MODE12
- GB_TILE_MODE12__ARRAY_MODE_MASK
- GB_TILE_MODE12__ARRAY_MODE__SHIFT
- GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE12__PIPE_CONFIG_MASK
- GB_TILE_MODE12__PIPE_CONFIG__SHIFT
- GB_TILE_MODE12__SAMPLE_SPLIT_MASK
- GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE12__TILE_SPLIT_MASK
- GB_TILE_MODE12__TILE_SPLIT__SHIFT
- GB_TILE_MODE13
- GB_TILE_MODE13__ARRAY_MODE_MASK
- GB_TILE_MODE13__ARRAY_MODE__SHIFT
- GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE13__PIPE_CONFIG_MASK
- GB_TILE_MODE13__PIPE_CONFIG__SHIFT
- GB_TILE_MODE13__SAMPLE_SPLIT_MASK
- GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE13__TILE_SPLIT_MASK
- GB_TILE_MODE13__TILE_SPLIT__SHIFT
- GB_TILE_MODE14
- GB_TILE_MODE14__ARRAY_MODE_MASK
- GB_TILE_MODE14__ARRAY_MODE__SHIFT
- GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE14__PIPE_CONFIG_MASK
- GB_TILE_MODE14__PIPE_CONFIG__SHIFT
- GB_TILE_MODE14__SAMPLE_SPLIT_MASK
- GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE14__TILE_SPLIT_MASK
- GB_TILE_MODE14__TILE_SPLIT__SHIFT
- GB_TILE_MODE15
- GB_TILE_MODE15__ARRAY_MODE_MASK
- GB_TILE_MODE15__ARRAY_MODE__SHIFT
- GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE15__PIPE_CONFIG_MASK
- GB_TILE_MODE15__PIPE_CONFIG__SHIFT
- GB_TILE_MODE15__SAMPLE_SPLIT_MASK
- GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE15__TILE_SPLIT_MASK
- GB_TILE_MODE15__TILE_SPLIT__SHIFT
- GB_TILE_MODE16
- GB_TILE_MODE16__ARRAY_MODE_MASK
- GB_TILE_MODE16__ARRAY_MODE__SHIFT
- GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE16__PIPE_CONFIG_MASK
- GB_TILE_MODE16__PIPE_CONFIG__SHIFT
- GB_TILE_MODE16__SAMPLE_SPLIT_MASK
- GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE16__TILE_SPLIT_MASK
- GB_TILE_MODE16__TILE_SPLIT__SHIFT
- GB_TILE_MODE17
- GB_TILE_MODE17__ARRAY_MODE_MASK
- GB_TILE_MODE17__ARRAY_MODE__SHIFT
- GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE17__PIPE_CONFIG_MASK
- GB_TILE_MODE17__PIPE_CONFIG__SHIFT
- GB_TILE_MODE17__SAMPLE_SPLIT_MASK
- GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE17__TILE_SPLIT_MASK
- GB_TILE_MODE17__TILE_SPLIT__SHIFT
- GB_TILE_MODE18
- GB_TILE_MODE18__ARRAY_MODE_MASK
- GB_TILE_MODE18__ARRAY_MODE__SHIFT
- GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE18__PIPE_CONFIG_MASK
- GB_TILE_MODE18__PIPE_CONFIG__SHIFT
- GB_TILE_MODE18__SAMPLE_SPLIT_MASK
- GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE18__TILE_SPLIT_MASK
- GB_TILE_MODE18__TILE_SPLIT__SHIFT
- GB_TILE_MODE19
- GB_TILE_MODE19__ARRAY_MODE_MASK
- GB_TILE_MODE19__ARRAY_MODE__SHIFT
- GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE19__PIPE_CONFIG_MASK
- GB_TILE_MODE19__PIPE_CONFIG__SHIFT
- GB_TILE_MODE19__SAMPLE_SPLIT_MASK
- GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE19__TILE_SPLIT_MASK
- GB_TILE_MODE19__TILE_SPLIT__SHIFT
- GB_TILE_MODE1__ARRAY_MODE_MASK
- GB_TILE_MODE1__ARRAY_MODE__SHIFT
- GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE1__PIPE_CONFIG_MASK
- GB_TILE_MODE1__PIPE_CONFIG__SHIFT
- GB_TILE_MODE1__SAMPLE_SPLIT_MASK
- GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE1__TILE_SPLIT_MASK
- GB_TILE_MODE1__TILE_SPLIT__SHIFT
- GB_TILE_MODE2
- GB_TILE_MODE20
- GB_TILE_MODE20__ARRAY_MODE_MASK
- GB_TILE_MODE20__ARRAY_MODE__SHIFT
- GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE20__PIPE_CONFIG_MASK
- GB_TILE_MODE20__PIPE_CONFIG__SHIFT
- GB_TILE_MODE20__SAMPLE_SPLIT_MASK
- GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE20__TILE_SPLIT_MASK
- GB_TILE_MODE20__TILE_SPLIT__SHIFT
- GB_TILE_MODE21
- GB_TILE_MODE21__ARRAY_MODE_MASK
- GB_TILE_MODE21__ARRAY_MODE__SHIFT
- GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE21__PIPE_CONFIG_MASK
- GB_TILE_MODE21__PIPE_CONFIG__SHIFT
- GB_TILE_MODE21__SAMPLE_SPLIT_MASK
- GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE21__TILE_SPLIT_MASK
- GB_TILE_MODE21__TILE_SPLIT__SHIFT
- GB_TILE_MODE22
- GB_TILE_MODE22__ARRAY_MODE_MASK
- GB_TILE_MODE22__ARRAY_MODE__SHIFT
- GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE22__PIPE_CONFIG_MASK
- GB_TILE_MODE22__PIPE_CONFIG__SHIFT
- GB_TILE_MODE22__SAMPLE_SPLIT_MASK
- GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE22__TILE_SPLIT_MASK
- GB_TILE_MODE22__TILE_SPLIT__SHIFT
- GB_TILE_MODE23
- GB_TILE_MODE23__ARRAY_MODE_MASK
- GB_TILE_MODE23__ARRAY_MODE__SHIFT
- GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE23__PIPE_CONFIG_MASK
- GB_TILE_MODE23__PIPE_CONFIG__SHIFT
- GB_TILE_MODE23__SAMPLE_SPLIT_MASK
- GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE23__TILE_SPLIT_MASK
- GB_TILE_MODE23__TILE_SPLIT__SHIFT
- GB_TILE_MODE24
- GB_TILE_MODE24__ARRAY_MODE_MASK
- GB_TILE_MODE24__ARRAY_MODE__SHIFT
- GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE24__PIPE_CONFIG_MASK
- GB_TILE_MODE24__PIPE_CONFIG__SHIFT
- GB_TILE_MODE24__SAMPLE_SPLIT_MASK
- GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE24__TILE_SPLIT_MASK
- GB_TILE_MODE24__TILE_SPLIT__SHIFT
- GB_TILE_MODE25
- GB_TILE_MODE25__ARRAY_MODE_MASK
- GB_TILE_MODE25__ARRAY_MODE__SHIFT
- GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE25__PIPE_CONFIG_MASK
- GB_TILE_MODE25__PIPE_CONFIG__SHIFT
- GB_TILE_MODE25__SAMPLE_SPLIT_MASK
- GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE25__TILE_SPLIT_MASK
- GB_TILE_MODE25__TILE_SPLIT__SHIFT
- GB_TILE_MODE26
- GB_TILE_MODE26__ARRAY_MODE_MASK
- GB_TILE_MODE26__ARRAY_MODE__SHIFT
- GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE26__PIPE_CONFIG_MASK
- GB_TILE_MODE26__PIPE_CONFIG__SHIFT
- GB_TILE_MODE26__SAMPLE_SPLIT_MASK
- GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE26__TILE_SPLIT_MASK
- GB_TILE_MODE26__TILE_SPLIT__SHIFT
- GB_TILE_MODE27
- GB_TILE_MODE27__ARRAY_MODE_MASK
- GB_TILE_MODE27__ARRAY_MODE__SHIFT
- GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE27__PIPE_CONFIG_MASK
- GB_TILE_MODE27__PIPE_CONFIG__SHIFT
- GB_TILE_MODE27__SAMPLE_SPLIT_MASK
- GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE27__TILE_SPLIT_MASK
- GB_TILE_MODE27__TILE_SPLIT__SHIFT
- GB_TILE_MODE28
- GB_TILE_MODE28__ARRAY_MODE_MASK
- GB_TILE_MODE28__ARRAY_MODE__SHIFT
- GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE28__PIPE_CONFIG_MASK
- GB_TILE_MODE28__PIPE_CONFIG__SHIFT
- GB_TILE_MODE28__SAMPLE_SPLIT_MASK
- GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE28__TILE_SPLIT_MASK
- GB_TILE_MODE28__TILE_SPLIT__SHIFT
- GB_TILE_MODE29
- GB_TILE_MODE29__ARRAY_MODE_MASK
- GB_TILE_MODE29__ARRAY_MODE__SHIFT
- GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE29__PIPE_CONFIG_MASK
- GB_TILE_MODE29__PIPE_CONFIG__SHIFT
- GB_TILE_MODE29__SAMPLE_SPLIT_MASK
- GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE29__TILE_SPLIT_MASK
- GB_TILE_MODE29__TILE_SPLIT__SHIFT
- GB_TILE_MODE2__ARRAY_MODE_MASK
- GB_TILE_MODE2__ARRAY_MODE__SHIFT
- GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE2__PIPE_CONFIG_MASK
- GB_TILE_MODE2__PIPE_CONFIG__SHIFT
- GB_TILE_MODE2__SAMPLE_SPLIT_MASK
- GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE2__TILE_SPLIT_MASK
- GB_TILE_MODE2__TILE_SPLIT__SHIFT
- GB_TILE_MODE3
- GB_TILE_MODE30
- GB_TILE_MODE30__ARRAY_MODE_MASK
- GB_TILE_MODE30__ARRAY_MODE__SHIFT
- GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE30__PIPE_CONFIG_MASK
- GB_TILE_MODE30__PIPE_CONFIG__SHIFT
- GB_TILE_MODE30__SAMPLE_SPLIT_MASK
- GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE30__TILE_SPLIT_MASK
- GB_TILE_MODE30__TILE_SPLIT__SHIFT
- GB_TILE_MODE31
- GB_TILE_MODE31__ARRAY_MODE_MASK
- GB_TILE_MODE31__ARRAY_MODE__SHIFT
- GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE31__PIPE_CONFIG_MASK
- GB_TILE_MODE31__PIPE_CONFIG__SHIFT
- GB_TILE_MODE31__SAMPLE_SPLIT_MASK
- GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE31__TILE_SPLIT_MASK
- GB_TILE_MODE31__TILE_SPLIT__SHIFT
- GB_TILE_MODE3__ARRAY_MODE_MASK
- GB_TILE_MODE3__ARRAY_MODE__SHIFT
- GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE3__PIPE_CONFIG_MASK
- GB_TILE_MODE3__PIPE_CONFIG__SHIFT
- GB_TILE_MODE3__SAMPLE_SPLIT_MASK
- GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE3__TILE_SPLIT_MASK
- GB_TILE_MODE3__TILE_SPLIT__SHIFT
- GB_TILE_MODE4
- GB_TILE_MODE4__ARRAY_MODE_MASK
- GB_TILE_MODE4__ARRAY_MODE__SHIFT
- GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE4__PIPE_CONFIG_MASK
- GB_TILE_MODE4__PIPE_CONFIG__SHIFT
- GB_TILE_MODE4__SAMPLE_SPLIT_MASK
- GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE4__TILE_SPLIT_MASK
- GB_TILE_MODE4__TILE_SPLIT__SHIFT
- GB_TILE_MODE5
- GB_TILE_MODE5__ARRAY_MODE_MASK
- GB_TILE_MODE5__ARRAY_MODE__SHIFT
- GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE5__PIPE_CONFIG_MASK
- GB_TILE_MODE5__PIPE_CONFIG__SHIFT
- GB_TILE_MODE5__SAMPLE_SPLIT_MASK
- GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE5__TILE_SPLIT_MASK
- GB_TILE_MODE5__TILE_SPLIT__SHIFT
- GB_TILE_MODE6
- GB_TILE_MODE6__ARRAY_MODE_MASK
- GB_TILE_MODE6__ARRAY_MODE__SHIFT
- GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE6__PIPE_CONFIG_MASK
- GB_TILE_MODE6__PIPE_CONFIG__SHIFT
- GB_TILE_MODE6__SAMPLE_SPLIT_MASK
- GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE6__TILE_SPLIT_MASK
- GB_TILE_MODE6__TILE_SPLIT__SHIFT
- GB_TILE_MODE7
- GB_TILE_MODE7__ARRAY_MODE_MASK
- GB_TILE_MODE7__ARRAY_MODE__SHIFT
- GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE7__PIPE_CONFIG_MASK
- GB_TILE_MODE7__PIPE_CONFIG__SHIFT
- GB_TILE_MODE7__SAMPLE_SPLIT_MASK
- GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE7__TILE_SPLIT_MASK
- GB_TILE_MODE7__TILE_SPLIT__SHIFT
- GB_TILE_MODE8
- GB_TILE_MODE8__ARRAY_MODE_MASK
- GB_TILE_MODE8__ARRAY_MODE__SHIFT
- GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE8__PIPE_CONFIG_MASK
- GB_TILE_MODE8__PIPE_CONFIG__SHIFT
- GB_TILE_MODE8__SAMPLE_SPLIT_MASK
- GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE8__TILE_SPLIT_MASK
- GB_TILE_MODE8__TILE_SPLIT__SHIFT
- GB_TILE_MODE9
- GB_TILE_MODE9__ARRAY_MODE_MASK
- GB_TILE_MODE9__ARRAY_MODE__SHIFT
- GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK
- GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT
- GB_TILE_MODE9__PIPE_CONFIG_MASK
- GB_TILE_MODE9__PIPE_CONFIG__SHIFT
- GB_TILE_MODE9__SAMPLE_SPLIT_MASK
- GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT
- GB_TILE_MODE9__TILE_SPLIT_MASK
- GB_TILE_MODE9__TILE_SPLIT__SHIFT
- GB_TILING_CONFIG
- GB_TILING_CONFIG_MACROTABLE_SIZE
- GB_TILING_CONFIG_TABLE_SIZE
- GB_UART_CREDIT_WAIT_TIMEOUT_MSEC
- GB_UART_CTRL_DCD
- GB_UART_CTRL_DSR
- GB_UART_CTRL_DTR
- GB_UART_CTRL_RI
- GB_UART_CTRL_RTS
- GB_UART_FIRMWARE_CREDITS
- GB_UART_RECV_FLAG_BREAK
- GB_UART_RECV_FLAG_FRAMING
- GB_UART_RECV_FLAG_OVERRUN
- GB_UART_RECV_FLAG_PARITY
- GB_UART_TYPE_FLUSH_FIFOS
- GB_UART_TYPE_RECEIVE_CREDITS
- GB_UART_TYPE_RECEIVE_DATA
- GB_UART_TYPE_SEND_BREAK
- GB_UART_TYPE_SEND_DATA
- GB_UART_TYPE_SERIAL_STATE
- GB_UART_TYPE_SET_CONTROL_LINE_STATE
- GB_UART_TYPE_SET_LINE_CODING
- GB_UART_WRITE_FIFO_SIZE
- GB_UART_WRITE_ROOM_MARGIN
- GB_USB_TYPE_HCD_START
- GB_USB_TYPE_HCD_STOP
- GB_USB_TYPE_HUB_CONTROL
- GB_VDROOP_TABLE_t
- GB_VIBRATOR_TYPE_OFF
- GB_VIBRATOR_TYPE_ON
- GBps
- GBps_to_icc
- GC
- GC1R_BBEN
- GC1R_BCP
- GC1R_BMEN
- GC1R_DT
- GC1R_DWP
- GC1R_GCT
- GC1R_IPP
- GC1R_LNIP
- GC1R_PBEN
- GC1R_SHREN
- GC1R_SPP
- GC1R_STREN
- GC1R_TP
- GC1R_WBCH
- GC1R_WGCH
- GC1R_WRCH
- GC2R_BW
- GC2R_DPAEN
- GC2R_DVAEN
- GC2R_EDCA
- GC2R_EDCEN
- GC2R_STSAEN
- GCAE
- GCAOFF
- GCAON
- GCAR
- GCBCR
- GCCR
- GCCR_ABORT
- GCCR_BIT
- GCCR_BP_RST
- GCCR_LMTT
- GCCR_LPTC
- GCCR_LTI
- GCCR_LTO
- GCCR_STOP
- GCCR_SYNC_CLR
- GCCR_TCR
- GCCR_TCR_CAPTURE
- GCCR_TCR_NOREQ
- GCCR_TCR_RESET
- GCCR_TCSS
- GCCR_TCSS_ADJGPTP
- GCCR_TCSS_AVTP
- GCCR_TCSS_GPTP
- GCC_ADSS_BCR
- GCC_AGGRE0_CNOC_AHB_CLK
- GCC_AGGRE0_NOC_BCR
- GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK
- GCC_AGGRE0_SNOC_AXI_CLK
- GCC_AGGRE1_NOC_BCR
- GCC_AGGRE1_NOC_XO_CLK
- GCC_AGGRE1_PNOC_AHB_CLK
- GCC_AGGRE1_UFS_AXI_CLK
- GCC_AGGRE1_USB3_AXI_CLK
- GCC_AGGRE2_NOC_BCR
- GCC_AGGRE2_UFS_AXI_CLK
- GCC_AGGRE2_USB3_AXI_CLK
- GCC_AGGRE_NOC_PCIE_TBU_CLK
- GCC_AGGRE_UFS_CARD_AXI_CLK
- GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK
- GCC_AGGRE_UFS_PHY_AXI_CLK
- GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK
- GCC_AGGRE_USB3_PRIM_AXI_CLK
- GCC_AGGRE_USB3_SEC_AXI_CLK
- GCC_AHB2PHY_EAST_BCR
- GCC_AHB_CLK
- GCC_APB2JTAG_BCR
- GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR
- GCC_APC0_VS_RESET
- GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR
- GCC_APC1_VS_RESET
- GCC_APC_VS_CLK
- GCC_APPS_AHB_CLK_SRC
- GCC_APPS_CLK_SRC
- GCC_APSS_AHB_CLK
- GCC_APSS_AHB_CLK_SRC
- GCC_APSS_AXI_CLK
- GCC_APSS_CPU_PLLDIV_CLK
- GCC_APSS_DDRPLL_VCO
- GCC_APSS_QDSS_TSCTR_DIV2_CLK
- GCC_APSS_QDSS_TSCTR_DIV8_CLK
- GCC_APSS_TCU_BCR
- GCC_APSS_TCU_CLK
- GCC_AUDIO_AHB_CLK
- GCC_AUDIO_BCR
- GCC_AUDIO_CORE_BCR
- GCC_AUDIO_PWM_CLK
- GCC_BAM_DMA_AHB_CLK
- GCC_BAM_DMA_AHB_CLK_SLEEP_ENA
- GCC_BAM_DMA_BCR
- GCC_BAM_DMA_INACTIVITY_TIMERS_CLK
- GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA
- GCC_BIMC_APSS_AXI_CLK
- GCC_BIMC_BCR
- GCC_BIMC_CDSP_CLK
- GCC_BIMC_CFG_AHB_CLK
- GCC_BIMC_CLK
- GCC_BIMC_DDR_CH0_CLK
- GCC_BIMC_DDR_CH1_CLK
- GCC_BIMC_DDR_CPLL0_CLK
- GCC_BIMC_DDR_CPLL1_CLK
- GCC_BIMC_GFX_CLK
- GCC_BIMC_GPU_CLK
- GCC_BIMC_HMSS_AXI_CLK
- GCC_BIMC_KPSS_AXI_CLK
- GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA
- GCC_BIMC_MDSS_CLK
- GCC_BIMC_MSS_Q6_AXI_CLK
- GCC_BIMC_SLEEP_CLK
- GCC_BIMC_SYSNOC_AXI_CLK
- GCC_BIMC_XO_CLK
- GCC_BLSP1_AHB_CLK
- GCC_BLSP1_AHB_CLK_SLEEP_ENA
- GCC_BLSP1_BCR
- GCC_BLSP1_QUP0_I2C_APPS_CLK
- GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC
- GCC_BLSP1_QUP0_SPI_APPS_CLK
- GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC
- GCC_BLSP1_QUP1_BCR
- GCC_BLSP1_QUP1_I2C_APPS_CLK
- GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC
- GCC_BLSP1_QUP1_SPI_APPS_CLK
- GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC
- GCC_BLSP1_QUP2_BCR
- GCC_BLSP1_QUP2_I2C_APPS_CLK
- GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC
- GCC_BLSP1_QUP2_SPI_APPS_CLK
- GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC
- GCC_BLSP1_QUP3_BCR
- GCC_BLSP1_QUP3_I2C_APPS_CLK
- GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC
- GCC_BLSP1_QUP3_SPI_APPS_CLK
- GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC
- GCC_BLSP1_QUP4_BCR
- GCC_BLSP1_QUP4_I2C_APPS_CLK
- GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC
- GCC_BLSP1_QUP4_SPI_APPS_CLK
- GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC
- GCC_BLSP1_QUP5_BCR
- GCC_BLSP1_QUP5_I2C_APPS_CLK
- GCC_BLSP1_QUP5_SPI_APPS_CLK
- GCC_BLSP1_QUP6_BCR
- GCC_BLSP1_QUP6_I2C_APPS_CLK
- GCC_BLSP1_QUP6_SPI_APPS_CLK
- GCC_BLSP1_SLEEP_CLK
- GCC_BLSP1_SLEEP_CLK_SLEEP_ENA
- GCC_BLSP1_UART0_APPS_CLK
- GCC_BLSP1_UART0_APPS_CLK_SRC
- GCC_BLSP1_UART1_APPS_CLK
- GCC_BLSP1_UART1_APPS_CLK_SRC
- GCC_BLSP1_UART1_BCR
- GCC_BLSP1_UART1_SIM_CLK
- GCC_BLSP1_UART2_APPS_CLK
- GCC_BLSP1_UART2_APPS_CLK_SRC
- GCC_BLSP1_UART2_BCR
- GCC_BLSP1_UART2_SIM_CLK
- GCC_BLSP1_UART3_APPS_CLK
- GCC_BLSP1_UART3_APPS_CLK_SRC
- GCC_BLSP1_UART3_BCR
- GCC_BLSP1_UART3_SIM_CLK
- GCC_BLSP1_UART4_APPS_CLK
- GCC_BLSP1_UART4_BCR
- GCC_BLSP1_UART4_SIM_CLK
- GCC_BLSP1_UART5_APPS_CLK
- GCC_BLSP1_UART5_BCR
- GCC_BLSP1_UART5_SIM_CLK
- GCC_BLSP1_UART6_APPS_CLK
- GCC_BLSP1_UART6_BCR
- GCC_BLSP1_UART6_SIM_CLK
- GCC_BLSP2_AHB_CLK
- GCC_BLSP2_AHB_CLK_SLEEP_ENA
- GCC_BLSP2_BCR
- GCC_BLSP2_QUP0_I2C_APPS_CLK
- GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC
- GCC_BLSP2_QUP0_SPI_APPS_CLK
- GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC
- GCC_BLSP2_QUP1_BCR
- GCC_BLSP2_QUP1_I2C_APPS_CLK
- GCC_BLSP2_QUP1_SPI_APPS_CLK
- GCC_BLSP2_QUP2_BCR
- GCC_BLSP2_QUP2_I2C_APPS_CLK
- GCC_BLSP2_QUP2_SPI_APPS_CLK
- GCC_BLSP2_QUP3_BCR
- GCC_BLSP2_QUP3_I2C_APPS_CLK
- GCC_BLSP2_QUP3_SPI_APPS_CLK
- GCC_BLSP2_QUP4_BCR
- GCC_BLSP2_QUP4_I2C_APPS_CLK
- GCC_BLSP2_QUP4_SPI_APPS_CLK
- GCC_BLSP2_QUP5_BCR
- GCC_BLSP2_QUP5_I2C_APPS_CLK
- GCC_BLSP2_QUP5_SPI_APPS_CLK
- GCC_BLSP2_QUP6_BCR
- GCC_BLSP2_QUP6_I2C_APPS_CLK
- GCC_BLSP2_QUP6_SPI_APPS_CLK
- GCC_BLSP2_SLEEP_CLK
- GCC_BLSP2_SLEEP_CLK_SLEEP_ENA
- GCC_BLSP2_UART0_APPS_CLK
- GCC_BLSP2_UART0_APPS_CLK_SRC
- GCC_BLSP2_UART1_APPS_CLK
- GCC_BLSP2_UART1_BCR
- GCC_BLSP2_UART1_SIM_CLK
- GCC_BLSP2_UART2_APPS_CLK
- GCC_BLSP2_UART2_BCR
- GCC_BLSP2_UART2_SIM_CLK
- GCC_BLSP2_UART3_APPS_CLK
- GCC_BLSP2_UART3_BCR
- GCC_BLSP2_UART3_SIM_CLK
- GCC_BLSP2_UART4_APPS_CLK
- GCC_BLSP2_UART4_BCR
- GCC_BLSP2_UART4_SIM_CLK
- GCC_BLSP2_UART5_APPS_CLK
- GCC_BLSP2_UART5_BCR
- GCC_BLSP2_UART5_SIM_CLK
- GCC_BLSP2_UART6_APPS_CLK
- GCC_BLSP2_UART6_BCR
- GCC_BLSP2_UART6_SIM_CLK
- GCC_BOOT_ROM_AHB_CLK
- GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA
- GCC_BOOT_ROM_BCR
- GCC_BYTE0_CLK_SRC
- GCC_CAMERA_AHB_CLK
- GCC_CAMERA_AXI_CLK
- GCC_CAMERA_HF_AXI_CLK
- GCC_CAMERA_SF_AXI_CLK
- GCC_CAMERA_XO_CLK
- GCC_CAMSS_AHB_BCR
- GCC_CAMSS_AHB_CLK
- GCC_CAMSS_CCI_AHB_CLK
- GCC_CAMSS_CCI_BCR
- GCC_CAMSS_CCI_CLK
- GCC_CAMSS_CPP_AHB_CLK
- GCC_CAMSS_CPP_CLK
- GCC_CAMSS_CSI0PHYTIMER_CLK
- GCC_CAMSS_CSI0PHY_BCR
- GCC_CAMSS_CSI0PHY_CLK
- GCC_CAMSS_CSI0PIX_BCR
- GCC_CAMSS_CSI0PIX_CLK
- GCC_CAMSS_CSI0RDI_BCR
- GCC_CAMSS_CSI0RDI_CLK
- GCC_CAMSS_CSI0_AHB_CLK
- GCC_CAMSS_CSI0_BCR
- GCC_CAMSS_CSI0_CLK
- GCC_CAMSS_CSI1PHYTIMER_CLK
- GCC_CAMSS_CSI1PHY_BCR
- GCC_CAMSS_CSI1PHY_CLK
- GCC_CAMSS_CSI1PIX_BCR
- GCC_CAMSS_CSI1PIX_CLK
- GCC_CAMSS_CSI1RDI_BCR
- GCC_CAMSS_CSI1RDI_CLK
- GCC_CAMSS_CSI1_AHB_CLK
- GCC_CAMSS_CSI1_BCR
- GCC_CAMSS_CSI1_CLK
- GCC_CAMSS_CSI_VFE0_BCR
- GCC_CAMSS_CSI_VFE0_CLK
- GCC_CAMSS_GP0_BCR
- GCC_CAMSS_GP0_CLK
- GCC_CAMSS_GP1_BCR
- GCC_CAMSS_GP1_CLK
- GCC_CAMSS_ISPIF_AHB_CLK
- GCC_CAMSS_ISPIF_BCR
- GCC_CAMSS_JPEG0_CLK
- GCC_CAMSS_JPEG_AHB_CLK
- GCC_CAMSS_JPEG_AXI_CLK
- GCC_CAMSS_JPEG_BCR
- GCC_CAMSS_MCLK0_BCR
- GCC_CAMSS_MCLK0_CLK
- GCC_CAMSS_MCLK1_BCR
- GCC_CAMSS_MCLK1_CLK
- GCC_CAMSS_MICRO_AHB_CLK
- GCC_CAMSS_MICRO_BCR
- GCC_CAMSS_PHY0_BCR
- GCC_CAMSS_PHY1_BCR
- GCC_CAMSS_TOP_AHB_CLK
- GCC_CAMSS_TOP_BCR
- GCC_CAMSS_VFE0_CLK
- GCC_CAMSS_VFE_AHB_CLK
- GCC_CAMSS_VFE_AXI_CLK
- GCC_CAMSS_VFE_BCR
- GCC_CDSP_BIMC_CLK_SRC
- GCC_CDSP_CFG_AHB_CLK
- GCC_CDSP_RESTART
- GCC_CDSP_TBU_CLK
- GCC_CE1_AHB_CLK
- GCC_CE1_AHB_CLK_SLEEP_ENA
- GCC_CE1_AXI_CLK
- GCC_CE1_AXI_CLK_SLEEP_ENA
- GCC_CE1_BCR
- GCC_CE1_CLK
- GCC_CE1_CLK_SLEEP_ENA
- GCC_CE2_AHB_CLK
- GCC_CE2_AHB_CLK_SLEEP_ENA
- GCC_CE2_AXI_CLK
- GCC_CE2_AXI_CLK_SLEEP_ENA
- GCC_CE2_BCR
- GCC_CE2_CLK
- GCC_CE2_CLK_SLEEP_ENA
- GCC_CE3_AHB_CLK
- GCC_CE3_AXI_CLK
- GCC_CE3_BCR
- GCC_CE3_CLK
- GCC_CFG_NOC_AHB_CLK
- GCC_CFG_NOC_DDR_CFG_CLK
- GCC_CFG_NOC_RPM_AHB_CLK
- GCC_CFG_NOC_USB2_AXI_CLK
- GCC_CFG_NOC_USB3_AXI_CLK
- GCC_CFG_NOC_USB3_PRIM_AXI_CLK
- GCC_CFG_NOC_USB3_SEC_AXI_CLK
- GCC_CMN_12GPLL_AHB_CLK
- GCC_CMN_12GPLL_BCR
- GCC_CMN_12GPLL_SYS_CLK
- GCC_CM_PHY_REFGEN1_BCR
- GCC_CM_PHY_REFGEN2_BCR
- GCC_CNOC_BUS_TIMEOUT0_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT0_BCR
- GCC_CNOC_BUS_TIMEOUT10_BCR
- GCC_CNOC_BUS_TIMEOUT11_BCR
- GCC_CNOC_BUS_TIMEOUT12_BCR
- GCC_CNOC_BUS_TIMEOUT13_BCR
- GCC_CNOC_BUS_TIMEOUT14_BCR
- GCC_CNOC_BUS_TIMEOUT1_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT1_BCR
- GCC_CNOC_BUS_TIMEOUT2_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT2_BCR
- GCC_CNOC_BUS_TIMEOUT3_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT3_BCR
- GCC_CNOC_BUS_TIMEOUT4_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT4_BCR
- GCC_CNOC_BUS_TIMEOUT5_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT5_BCR
- GCC_CNOC_BUS_TIMEOUT6_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT6_BCR
- GCC_CNOC_BUS_TIMEOUT7_AHB_CLK
- GCC_CNOC_BUS_TIMEOUT7_BCR
- GCC_CNOC_BUS_TIMEOUT8_BCR
- GCC_CNOC_BUS_TIMEOUT9_BCR
- GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR
- GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR
- GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR
- GCC_CODEC_DIGCODEC_CLK
- GCC_COMMON_H_INCLUDED
- GCC_CONFIG_NOC_BCR
- GCC_COPSS_SMMU_AHB_CLK
- GCC_COPSS_SMMU_AXI_CLK
- GCC_COPSS_SMMU_BCR
- GCC_CPUSS_AHB_CLK
- GCC_CPUSS_AHB_CLK_SRC
- GCC_CPUSS_DVM_BUS_CLK
- GCC_CPUSS_GNOC_CLK
- GCC_CPUSS_RBCPR_CLK
- GCC_CPUSS_RBCPR_CLK_SRC
- GCC_CRYPTO_AHB_CLK
- GCC_CRYPTO_AXI_CLK
- GCC_CRYPTO_BCR
- GCC_CRYPTO_CLK
- GCC_DADDI_IMM_ASM
- GCC_DCC_AHB_CLK
- GCC_DCC_BCR
- GCC_DCC_CLK
- GCC_DCC_XO_CLK
- GCC_DCD_BCR
- GCC_DCD_XO_CLK
- GCC_DDRSS_BCR
- GCC_DDRSS_GPU_AXI_CLK
- GCC_DDR_DIM_CFG_CLK
- GCC_DDR_DIM_SLEEP_CLK
- GCC_DEHR_BCR
- GCC_DEHR_CLK
- GCC_DISP_AHB_CLK
- GCC_DISP_AXI_CLK
- GCC_DISP_GPLL0_CLK_SRC
- GCC_DISP_GPLL0_DIV_CLK_SRC
- GCC_DISP_HF_AXI_CLK
- GCC_DISP_SF_AXI_CLK
- GCC_DISP_XO_CLK
- GCC_DUMMY_CLK
- GCC_EDP_CLKREF_CLK
- GCC_EMAC_AXI_CLK
- GCC_EMAC_BCR
- GCC_EMAC_CLK_SRC
- GCC_EMAC_PTP_CLK
- GCC_EMAC_PTP_CLK_SRC
- GCC_EMAC_RGMII_CLK
- GCC_EMAC_RGMII_CLK_SRC
- GCC_EMAC_SLV_AHB_CLK
- GCC_ESC0_CLK_SRC
- GCC_ESS_BCR
- GCC_ESS_CLK
- GCC_ETH_AXI_CLK
- GCC_ETH_PTP_CLK
- GCC_ETH_RGMII_CLK
- GCC_ETH_SLAVE_AHB_CLK
- GCC_FEPLL125DLY_CLK
- GCC_FEPLL125_CLK
- GCC_FEPLL200_CLK
- GCC_FEPLL500_CLK
- GCC_FEPLL_VCO
- GCC_FEPLL_WCSS2G_CLK
- GCC_FEPLL_WCSS5G_CLK
- GCC_GENI_IR_BCR
- GCC_GENI_IR_H_CLK
- GCC_GENI_IR_S_CLK
- GCC_GFX3D_CLK_SRC
- GCC_GFX_TBU_BCR
- GCC_GFX_TBU_CLK
- GCC_GFX_TCU_BCR
- GCC_GFX_TCU_CLK
- GCC_GLM_BCR
- GCC_GMEM_BCR
- GCC_GP1_CLK
- GCC_GP1_CLK_SRC
- GCC_GP2_CLK
- GCC_GP2_CLK_SRC
- GCC_GP3_CLK
- GCC_GP3_CLK_SRC
- GCC_GPLL0_AO_CLK_SRC
- GCC_GPLL0_AO_OUT_MAIN
- GCC_GPLL0_OUT_MAIN
- GCC_GPLL0_SLEEP_CLK_SRC
- GCC_GPLL1_OUT_MAIN
- GCC_GPLL3_OUT_MAIN
- GCC_GPLL4_OUT_MAIN
- GCC_GPLL6
- GCC_GPLL6_OUT_AUX
- GCC_GPU_BCR
- GCC_GPU_BIMC_GFX_CLK
- GCC_GPU_BIMC_GFX_SRC_CLK
- GCC_GPU_CFG_AHB_CLK
- GCC_GPU_GPLL0_CLK
- GCC_GPU_GPLL0_CLK_SRC
- GCC_GPU_GPLL0_DIV_CLK
- GCC_GPU_GPLL0_DIV_CLK_SRC
- GCC_GPU_IREF_CLK
- GCC_GPU_MEMNOC_GFX_CLK
- GCC_GPU_SNOC_DVM_GFX_CLK
- GCC_GPU_VS_CLK
- GCC_GPU_VS_RESET
- GCC_GTCU_AHB_BCR
- GCC_GTCU_AHB_CLK
- GCC_HDMI_APP_CLK_SRC
- GCC_HDMI_CLKREF_CLK
- GCC_HDMI_PCLK_CLK_SRC
- GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK
- GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK
- GCC_HMSS_AHB_CLK
- GCC_HMSS_AT_CLK
- GCC_HMSS_DVM_BUS_CLK
- GCC_HMSS_MSTR_AXI_CLK
- GCC_HMSS_RBCPR_CLK
- GCC_HMSS_SLV_AXI_CLK
- GCC_HMSS_TRIG_CLK
- GCC_IMEM_AXI_CLK
- GCC_IMEM_AXI_CLK_SLEEP_ENA
- GCC_IMEM_BCR
- GCC_IMEM_CFG_AHB_CLK
- GCC_IM_SLEEP_CLK
- GCC_IPA_BCR
- GCC_JPEG_TBU_BCR
- GCC_JPEG_TBU_CLK
- GCC_KPSS_AHB_CLK
- GCC_KPSS_AHB_CLK_SLEEP_ENA
- GCC_KPSS_AXI_CLK
- GCC_KPSS_AXI_CLK_SLEEP_ENA
- GCC_LPASS_AT_CLK
- GCC_LPASS_GPLL0_CLK_SRC
- GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA
- GCC_LPASS_MPORT_AXI_CLK
- GCC_LPASS_Q6_AXI_CLK
- GCC_LPASS_RESTART
- GCC_LPASS_SWAY_CLK
- GCC_LPASS_TRIG_CLK
- GCC_MDIO_AHB_CLK
- GCC_MDIO_BCR
- GCC_MDP_CLK_SRC
- GCC_MDP_TBU_BCR
- GCC_MDP_TBU_CLK
- GCC_MDSS_AHB_CLK
- GCC_MDSS_AXI_CLK
- GCC_MDSS_BCR
- GCC_MDSS_BYTE0_CLK
- GCC_MDSS_ESC0_CLK
- GCC_MDSS_HDMI_APP_CLK
- GCC_MDSS_HDMI_PCLK_CLK
- GCC_MDSS_MDP_CLK
- GCC_MDSS_MDP_VOTE_CLK
- GCC_MDSS_PCLK0_CLK
- GCC_MDSS_ROTATOR_VOTE_CLK
- GCC_MDSS_VSYNC_CLK
- GCC_MEM_NOC_NSS_AXI_CLK
- GCC_MMSS_BCR
- GCC_MMSS_BIMC_GFX_CLK
- GCC_MMSS_GPLL0_CLK
- GCC_MMSS_GPLL0_CLK_SRC
- GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA
- GCC_MMSS_GPLL0_DIV_CLK
- GCC_MMSS_NOC_AT_CLK
- GCC_MMSS_NOC_CFG_AHB_CLK
- GCC_MMSS_QM_AHB_CLK
- GCC_MMSS_QM_CORE_CLK
- GCC_MMSS_SYS_NOC_AXI_CLK
- GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK
- GCC_MM_SPDM_BCR
- GCC_MPM_AHB_CLK
- GCC_MPM_AHB_CLK_SLEEP_ENA
- GCC_MPM_AHB_RESET
- GCC_MPM_BCR
- GCC_MPM_NON_AHB_RESET
- GCC_MSG_RAM_AHB_CLK
- GCC_MSG_RAM_AHB_CLK_SLEEP_ENA
- GCC_MSG_RAM_BCR
- GCC_MSMPU_BCR
- GCC_MSS_AT_CLK
- GCC_MSS_AXIS2_CLK
- GCC_MSS_CFG_AHB_CLK
- GCC_MSS_GPLL0_DIV_CLK
- GCC_MSS_GPLL0_DIV_CLK_SRC
- GCC_MSS_MFAB_AXIS_CLK
- GCC_MSS_MNOC_BIMC_AXI_CLK
- GCC_MSS_Q6_BCR
- GCC_MSS_Q6_BIMC_AXI_CLK
- GCC_MSS_Q6_MEMNOC_AXI_CLK
- GCC_MSS_RESTART
- GCC_MSS_SNOC_AXI_CLK
- GCC_MSS_TBU_AXI_BCR
- GCC_MSS_TBU_GSS_AXI_BCR
- GCC_MSS_TBU_Q6_AXI_BCR
- GCC_MSS_VS_CLK
- GCC_MSS_VS_RESET
- GCC_NOC_CONF_XPU_AHB_CLK
- GCC_NPU_AT_CLK
- GCC_NPU_AXI_CLK
- GCC_NPU_BCR
- GCC_NPU_CFG_AHB_CLK
- GCC_NPU_GPLL0_CLK_SRC
- GCC_NPU_GPLL0_DIV_CLK_SRC
- GCC_NPU_TRIG_CLK
- GCC_NSSNOC_ATB_ARES
- GCC_NSSNOC_CE_APB_ARES
- GCC_NSSNOC_CE_APB_CLK
- GCC_NSSNOC_CE_AXI_ARES
- GCC_NSSNOC_CE_AXI_CLK
- GCC_NSSNOC_CRYPTO_ARES
- GCC_NSSNOC_CRYPTO_CLK
- GCC_NSSNOC_PPE_CFG_CLK
- GCC_NSSNOC_PPE_CLK
- GCC_NSSNOC_QOSGEN_REF_ARES
- GCC_NSSNOC_QOSGEN_REF_CLK
- GCC_NSSNOC_SNOC_ARES
- GCC_NSSNOC_SNOC_CLK
- GCC_NSSNOC_TIMEOUT_REF_ARES
- GCC_NSSNOC_TIMEOUT_REF_CLK
- GCC_NSSNOC_UBI0_AHB_ARES
- GCC_NSSNOC_UBI0_AHB_CLK
- GCC_NSSNOC_UBI1_AHB_ARES
- GCC_NSSNOC_UBI1_AHB_CLK
- GCC_NSS_BCR
- GCC_NSS_CE_APB_ARES
- GCC_NSS_CE_APB_CLK
- GCC_NSS_CE_AXI_ARES
- GCC_NSS_CE_AXI_CLK
- GCC_NSS_CFG_ARES
- GCC_NSS_CFG_CLK
- GCC_NSS_CRYPTO_ARES
- GCC_NSS_CRYPTO_CLK
- GCC_NSS_CSR_ARES
- GCC_NSS_CSR_CLK
- GCC_NSS_EDMA_CFG_CLK
- GCC_NSS_EDMA_CLK
- GCC_NSS_IMEM_ARES
- GCC_NSS_IMEM_CLK
- GCC_NSS_NOC_ARES
- GCC_NSS_NOC_CLK
- GCC_NSS_NOC_TBU_BCR
- GCC_NSS_PORT1_RX_CLK
- GCC_NSS_PORT1_TX_CLK
- GCC_NSS_PORT2_RX_CLK
- GCC_NSS_PORT2_TX_CLK
- GCC_NSS_PORT3_RX_CLK
- GCC_NSS_PORT3_TX_CLK
- GCC_NSS_PORT4_RX_CLK
- GCC_NSS_PORT4_TX_CLK
- GCC_NSS_PORT5_RX_CLK
- GCC_NSS_PORT5_TX_CLK
- GCC_NSS_PORT6_RX_CLK
- GCC_NSS_PORT6_TX_CLK
- GCC_NSS_PPE_BTQ_CLK
- GCC_NSS_PPE_CFG_CLK
- GCC_NSS_PPE_CLK
- GCC_NSS_PPE_IPE_CLK
- GCC_NSS_PTP_REF_CLK
- GCC_OBT_ODT_BCR
- GCC_OCMEM_NOC_CFG_AHB_CLK
- GCC_OCMEM_SYS_NOC_AXI_CLK
- GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA
- GCC_OFF_SMALL_ASM
- GCC_OXILI_AHB_CLK
- GCC_OXILI_BCR
- GCC_OXILI_GFX3D_CLK
- GCC_OXILI_GMEM_CLK
- GCC_PCIE0PHY_PHY_BCR
- GCC_PCIE0_AHB_ARES
- GCC_PCIE0_AHB_CLK
- GCC_PCIE0_AUX_CLK
- GCC_PCIE0_AXI_MASTER_ARES
- GCC_PCIE0_AXI_MASTER_STICKY_ARES
- GCC_PCIE0_AXI_M_CLK
- GCC_PCIE0_AXI_SLAVE_ARES
- GCC_PCIE0_AXI_S_CLK
- GCC_PCIE0_BCR
- GCC_PCIE0_CORE_STICKY_ARES
- GCC_PCIE0_LINK_DOWN_BCR
- GCC_PCIE0_PHY_BCR
- GCC_PCIE0_PHY_REFGEN_CLK
- GCC_PCIE0_PIPE_ARES
- GCC_PCIE0_PIPE_CLK
- GCC_PCIE0_SLEEP_ARES
- GCC_PCIE0_TBU_BCR
- GCC_PCIE1PHY_PHY_BCR
- GCC_PCIE1_AHB_ARES
- GCC_PCIE1_AHB_CLK
- GCC_PCIE1_AUX_CLK
- GCC_PCIE1_AXI_MASTER_ARES
- GCC_PCIE1_AXI_MASTER_STICKY_ARES
- GCC_PCIE1_AXI_M_CLK
- GCC_PCIE1_AXI_SLAVE_ARES
- GCC_PCIE1_AXI_S_CLK
- GCC_PCIE1_BCR
- GCC_PCIE1_CORE_STICKY_ARES
- GCC_PCIE1_LINK_DOWN_BCR
- GCC_PCIE1_PHY_BCR
- GCC_PCIE1_PHY_REFGEN_CLK
- GCC_PCIE1_PIPE_ARES
- GCC_PCIE1_PIPE_CLK
- GCC_PCIE1_SLEEP_ARES
- GCC_PCIE1_TBU_BCR
- GCC_PCIEPHY_0_PHY_BCR
- GCC_PCIE_0_AHB_ARES
- GCC_PCIE_0_AUX_CLK
- GCC_PCIE_0_AUX_CLK_SRC
- GCC_PCIE_0_AXI_MASTER_ARES
- GCC_PCIE_0_AXI_MASTER_STICKY_ARES
- GCC_PCIE_0_AXI_SLAVE_ARES
- GCC_PCIE_0_BCR
- GCC_PCIE_0_CFG_AHB_CLK
- GCC_PCIE_0_CLKREF_CLK
- GCC_PCIE_0_CORE_STICKY_ARES
- GCC_PCIE_0_LINK_DOWN_BCR
- GCC_PCIE_0_MSTR_AXI_CLK
- GCC_PCIE_0_NOCSR_COM_PHY_BCR
- GCC_PCIE_0_PHY_BCR
- GCC_PCIE_0_PIPE_ARES
- GCC_PCIE_0_PIPE_CLK
- GCC_PCIE_0_PIPE_CLK_SRC
- GCC_PCIE_0_SLEEP_ARES
- GCC_PCIE_0_SLV_AXI_CLK
- GCC_PCIE_0_SLV_Q2A_AXI_CLK
- GCC_PCIE_1_AUX_CLK
- GCC_PCIE_1_AUX_CLK_SRC
- GCC_PCIE_1_BCR
- GCC_PCIE_1_CFG_AHB_CLK
- GCC_PCIE_1_CLKREF_CLK
- GCC_PCIE_1_MSTR_AXI_CLK
- GCC_PCIE_1_PHY_BCR
- GCC_PCIE_1_PIPE_CLK
- GCC_PCIE_1_SLV_AXI_CLK
- GCC_PCIE_1_SLV_Q2A_AXI_CLK
- GCC_PCIE_2_AUX_CLK
- GCC_PCIE_2_BCR
- GCC_PCIE_2_CFG_AHB_CLK
- GCC_PCIE_2_MSTR_AXI_CLK
- GCC_PCIE_2_PHY_BCR
- GCC_PCIE_2_PIPE_CLK
- GCC_PCIE_2_SLV_AXI_CLK
- GCC_PCIE_AHB_CLK
- GCC_PCIE_AXI_M_CLK
- GCC_PCIE_AXI_S_CLK
- GCC_PCIE_BCR
- GCC_PCIE_CLKREF_CLK
- GCC_PCIE_PHY_AUX_CLK
- GCC_PCIE_PHY_BCR
- GCC_PCIE_PHY_CFG_AHB_BCR
- GCC_PCIE_PHY_CFG_AHB_CLK
- GCC_PCIE_PHY_COM_BCR
- GCC_PCIE_PHY_COM_NOCSR_BCR
- GCC_PCIE_PHY_NOCSR_COM_PHY_BCR
- GCC_PCIE_PHY_REFGEN_CLK
- GCC_PCIE_PHY_REFGEN_CLK_SRC
- GCC_PCLK0_CLK_SRC
- GCC_PCNOC_AHB_CLK
- GCC_PCNOC_AHB_CLK_SRC
- GCC_PCNOC_BCR
- GCC_PCNOC_BUS_TIMEOUT0_BCR
- GCC_PCNOC_BUS_TIMEOUT1_BCR
- GCC_PCNOC_BUS_TIMEOUT2_BCR
- GCC_PCNOC_BUS_TIMEOUT3_BCR
- GCC_PCNOC_BUS_TIMEOUT4_BCR
- GCC_PCNOC_BUS_TIMEOUT5_BCR
- GCC_PCNOC_BUS_TIMEOUT6_BCR
- GCC_PCNOC_BUS_TIMEOUT7_BCR
- GCC_PCNOC_BUS_TIMEOUT8_BCR
- GCC_PCNOC_BUS_TIMEOUT9_BCR
- GCC_PCNOC_TBU_BCR
- GCC_PCNOC_USB2_CLK
- GCC_PCNOC_USB3_CLK
- GCC_PDM2_CLK
- GCC_PDM2_CLK_SRC
- GCC_PDM_AHB_CLK
- GCC_PDM_BCR
- GCC_PDM_XO4_CLK
- GCC_PERIPH_NOC_AHB_CLK
- GCC_PERIPH_NOC_AT_CLK
- GCC_PERIPH_NOC_BCR
- GCC_PERIPH_NOC_CFG_AHB_CLK
- GCC_PERIPH_NOC_MPU_CFG_AHB_CLK
- GCC_PERIPH_NOC_USB20_AHB_CLK
- GCC_PERIPH_NOC_USB_HSIC_AHB_CLK
- GCC_PERIPH_XPU_AHB_CLK
- GCC_PIMEM_BCR
- GCC_PNOC_BUS_TIMEOUT0_AHB_CLK
- GCC_PNOC_BUS_TIMEOUT0_BCR
- GCC_PNOC_BUS_TIMEOUT1_AHB_CLK
- GCC_PNOC_BUS_TIMEOUT1_BCR
- GCC_PNOC_BUS_TIMEOUT2_AHB_CLK
- GCC_PNOC_BUS_TIMEOUT2_BCR
- GCC_PNOC_BUS_TIMEOUT3_AHB_CLK
- GCC_PNOC_BUS_TIMEOUT3_BCR
- GCC_PNOC_BUS_TIMEOUT4_AHB_CLK
- GCC_PNOC_BUS_TIMEOUT4_BCR
- GCC_PORT1_MAC_CLK
- GCC_PORT2_MAC_CLK
- GCC_PORT3_MAC_CLK
- GCC_PORT4_MAC_CLK
- GCC_PORT5_MAC_CLK
- GCC_PORT6_MAC_CLK
- GCC_PRNG_AHB_CLK
- GCC_PRNG_AHB_CLK_SLEEP_ENA
- GCC_PRNG_BCR
- GCC_PRONTO_TBU_BCR
- GCC_PWM0_XO512_CLK
- GCC_PWM1_XO512_CLK
- GCC_PWM2_XO512_CLK
- GCC_QDSS_AT_CLK
- GCC_QDSS_BCR
- GCC_QDSS_CFG_AHB_CLK
- GCC_QDSS_DAP_AHB_CLK
- GCC_QDSS_DAP_CLK
- GCC_QDSS_ETR_USB_CLK
- GCC_QDSS_RBCPR_XPU_AHB_CLK
- GCC_QDSS_STM_CLK
- GCC_QDSS_TRACECLKIN_CLK
- GCC_QDSS_TSCTR_DIV16_CLK
- GCC_QDSS_TSCTR_DIV2_CLK
- GCC_QDSS_TSCTR_DIV3_CLK
- GCC_QDSS_TSCTR_DIV4_CLK
- GCC_QDSS_TSCTR_DIV8_CLK
- GCC_QMIP_CAMERA_AHB_CLK
- GCC_QMIP_CAMERA_NRT_AHB_CLK
- GCC_QMIP_CAMERA_RT_AHB_CLK
- GCC_QMIP_DISP_AHB_CLK
- GCC_QMIP_VIDEO_AHB_CLK
- GCC_QMIP_VIDEO_CVP_AHB_CLK
- GCC_QMIP_VIDEO_VCODEC_AHB_CLK
- GCC_QPIC_AHB_CLK
- GCC_QPIC_BCR
- GCC_QPIC_CLK
- GCC_QREFS_VBG_CAL_BCR
- GCC_QSPI_AHB_CLK
- GCC_QSPI_BCR
- GCC_QSPI_CNOC_PERIPH_AHB_CLK
- GCC_QSPI_CORE_CLK
- GCC_QSPI_CORE_CLK_SRC
- GCC_QSPI_SER_CLK
- GCC_QUPV3_WRAP0_S0_CLK
- GCC_QUPV3_WRAP0_S0_CLK_SRC
- GCC_QUPV3_WRAP0_S1_CLK
- GCC_QUPV3_WRAP0_S1_CLK_SRC
- GCC_QUPV3_WRAP0_S2_CLK
- GCC_QUPV3_WRAP0_S2_CLK_SRC
- GCC_QUPV3_WRAP0_S3_CLK
- GCC_QUPV3_WRAP0_S3_CLK_SRC
- GCC_QUPV3_WRAP0_S4_CLK
- GCC_QUPV3_WRAP0_S4_CLK_SRC
- GCC_QUPV3_WRAP0_S5_CLK
- GCC_QUPV3_WRAP0_S5_CLK_SRC
- GCC_QUPV3_WRAP0_S6_CLK
- GCC_QUPV3_WRAP0_S6_CLK_SRC
- GCC_QUPV3_WRAP0_S7_CLK
- GCC_QUPV3_WRAP0_S7_CLK_SRC
- GCC_QUPV3_WRAP1_S0_CLK
- GCC_QUPV3_WRAP1_S0_CLK_SRC
- GCC_QUPV3_WRAP1_S1_CLK
- GCC_QUPV3_WRAP1_S1_CLK_SRC
- GCC_QUPV3_WRAP1_S2_CLK
- GCC_QUPV3_WRAP1_S2_CLK_SRC
- GCC_QUPV3_WRAP1_S3_CLK
- GCC_QUPV3_WRAP1_S3_CLK_SRC
- GCC_QUPV3_WRAP1_S4_CLK
- GCC_QUPV3_WRAP1_S4_CLK_SRC
- GCC_QUPV3_WRAP1_S5_CLK
- GCC_QUPV3_WRAP1_S5_CLK_SRC
- GCC_QUPV3_WRAP1_S6_CLK
- GCC_QUPV3_WRAP1_S6_CLK_SRC
- GCC_QUPV3_WRAP1_S7_CLK
- GCC_QUPV3_WRAP1_S7_CLK_SRC
- GCC_QUPV3_WRAP2_S0_CLK
- GCC_QUPV3_WRAP2_S0_CLK_SRC
- GCC_QUPV3_WRAP2_S1_CLK
- GCC_QUPV3_WRAP2_S1_CLK_SRC
- GCC_QUPV3_WRAP2_S2_CLK
- GCC_QUPV3_WRAP2_S2_CLK_SRC
- GCC_QUPV3_WRAP2_S3_CLK
- GCC_QUPV3_WRAP2_S3_CLK_SRC
- GCC_QUPV3_WRAP2_S4_CLK
- GCC_QUPV3_WRAP2_S4_CLK_SRC
- GCC_QUPV3_WRAP2_S5_CLK
- GCC_QUPV3_WRAP2_S5_CLK_SRC
- GCC_QUPV3_WRAPPER_0_BCR
- GCC_QUPV3_WRAPPER_1_BCR
- GCC_QUPV3_WRAPPER_2_BCR
- GCC_QUPV3_WRAP_0_M_AHB_CLK
- GCC_QUPV3_WRAP_0_S_AHB_CLK
- GCC_QUPV3_WRAP_1_M_AHB_CLK
- GCC_QUPV3_WRAP_1_S_AHB_CLK
- GCC_QUPV3_WRAP_2_M_AHB_CLK
- GCC_QUPV3_WRAP_2_S_AHB_CLK
- GCC_QUSB2PHY_PRIM_BCR
- GCC_QUSB2PHY_SEC_BCR
- GCC_QUSB2_0_PHY_BCR
- GCC_QUSB2_1_PHY_BCR
- GCC_QUSB2_PHY_BCR
- GCC_RBCPR_AHB_CLK
- GCC_RBCPR_BCR
- GCC_RBCPR_CLK
- GCC_RBCPR_CX_BCR
- GCC_RBCPR_MX_BCR
- GCC_RBCPR_WCSS_BCR
- GCC_REALIGN_WORDS
- GCC_RPM_BUS_AHB_CLK
- GCC_RPM_PROC_HCLK
- GCC_RPM_SLEEP_CLK
- GCC_RPM_TIMER_CLK
- GCC_RX0_USB2_CLKREF_CLK
- GCC_RX1_USB2_CLKREF_CLK
- GCC_RX2_USB2_CLKREF_CLK
- GCC_SATA_ASIC0_CLK
- GCC_SATA_AXI_CLK
- GCC_SATA_BCR
- GCC_SATA_CFG_AHB_CLK
- GCC_SATA_PMALIVE_CLK
- GCC_SATA_RX_CLK
- GCC_SATA_RX_OOB_CLK
- GCC_SDCC1_AHB_CLK
- GCC_SDCC1_APPS_CLK
- GCC_SDCC1_APPS_CLK_SRC
- GCC_SDCC1_BCR
- GCC_SDCC1_CDCCAL_FF_CLK
- GCC_SDCC1_CDCCAL_SLEEP_CLK
- GCC_SDCC1_ICE_CORE_CLK
- GCC_SDCC1_ICE_CORE_CLK_SRC
- GCC_SDCC1_INACTIVITY_TIMERS_CLK
- GCC_SDCC2_AHB_CLK
- GCC_SDCC2_APPS_CLK
- GCC_SDCC2_APPS_CLK_SRC
- GCC_SDCC2_BCR
- GCC_SDCC2_INACTIVITY_TIMERS_CLK
- GCC_SDCC3_AHB_CLK
- GCC_SDCC3_APPS_CLK
- GCC_SDCC3_BCR
- GCC_SDCC3_INACTIVITY_TIMERS_CLK
- GCC_SDCC4_AHB_CLK
- GCC_SDCC4_APPS_CLK
- GCC_SDCC4_APPS_CLK_SRC
- GCC_SDCC4_BCR
- GCC_SDCC4_INACTIVITY_TIMERS_CLK
- GCC_SDCC_PLLDIV_CLK
- GCC_SEC_CTRL_ACC_CLK
- GCC_SEC_CTRL_AHB_CLK
- GCC_SEC_CTRL_BCR
- GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK
- GCC_SEC_CTRL_CLK
- GCC_SEC_CTRL_SENSE_CLK
- GCC_SKL_BCR
- GCC_SLEEP_CLK_SRC
- GCC_SMMU_AGGRE0_AHB_CLK
- GCC_SMMU_AGGRE0_AXI_CLK
- GCC_SMMU_BCR
- GCC_SMMU_CATS_BCR
- GCC_SMMU_CFG_BCR
- GCC_SMMU_CFG_CLK
- GCC_SMMU_XPU_BCR
- GCC_SNOC_BUS_TIMEOUT0_AHB_CLK
- GCC_SNOC_BUS_TIMEOUT0_BCR
- GCC_SNOC_BUS_TIMEOUT1_BCR
- GCC_SNOC_BUS_TIMEOUT2_AHB_CLK
- GCC_SNOC_BUS_TIMEOUT2_BCR
- GCC_SNOC_BUS_TIMEOUT3_AHB_CLK
- GCC_SNOC_BUS_TIMEOUT3_BCR
- GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR
- GCC_SNOC_CNOC_AHB_CLK
- GCC_SNOC_PCNOC_AHB_CLK
- GCC_SNOC_PNOC_AHB_CLK
- GCC_SPDM_BCR
- GCC_SPDM_BIMC_CY_CLK
- GCC_SPDM_CFG_AHB_CLK
- GCC_SPDM_DEBUG_CY_CLK
- GCC_SPDM_FF_CLK
- GCC_SPDM_MSTR_AHB_CLK
- GCC_SPDM_PNOC_CY_CLK
- GCC_SPDM_RPM_CY_CLK
- GCC_SPDM_SNOC_CY_CLK
- GCC_SPMI_AHB_CLK
- GCC_SPMI_BCR
- GCC_SPMI_CNOC_AHB_CLK
- GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA
- GCC_SPMI_SER_CLK
- GCC_SPSS_AHB_CLK
- GCC_SPSS_BCR
- GCC_SRAM_SENSOR_BCR
- GCC_SSC_BCR
- GCC_SSC_RESET
- GCC_SYSTEM_NOC_BCR
- GCC_SYS_NOC_125M_CLK
- GCC_SYS_NOC_AT_CLK
- GCC_SYS_NOC_AXI_CLK
- GCC_SYS_NOC_CPUSS_AHB_CLK
- GCC_SYS_NOC_HMSS_AHB_CLK
- GCC_SYS_NOC_KPSS_AHB_CLK
- GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA
- GCC_SYS_NOC_PCIE0_AXI_CLK
- GCC_SYS_NOC_PCIE1_AXI_CLK
- GCC_SYS_NOC_QDSS_STM_AXI_CLK
- GCC_SYS_NOC_UFS_AXI_CLK
- GCC_SYS_NOC_USB0_AXI_CLK
- GCC_SYS_NOC_USB1_AXI_CLK
- GCC_SYS_NOC_USB3_AXI_CLK
- GCC_SYS_NOC_USB3_CLK
- GCC_SYS_NOC_USB3_SEC_AXI_CLK
- GCC_TCSR_AHB_CLK
- GCC_TCSR_BCR
- GCC_TIC_CLK
- GCC_TLMM_AHB_CLK
- GCC_TLMM_AHB_CLK_SLEEP_ENA
- GCC_TLMM_BCR
- GCC_TLMM_CLK
- GCC_TLMM_CLK_SLEEP_ENA
- GCC_TSIF_0_RESET
- GCC_TSIF_1_RESET
- GCC_TSIF_AHB_CLK
- GCC_TSIF_BCR
- GCC_TSIF_INACTIVITY_TIMERS_CLK
- GCC_TSIF_REF_CLK
- GCC_TSIF_REF_CLK_SRC
- GCC_UBI0_AHB_ARES
- GCC_UBI0_AHB_CLK
- GCC_UBI0_AXI_ARES
- GCC_UBI0_AXI_CLK
- GCC_UBI0_CLKRST_CLAMP_ENABLE
- GCC_UBI0_CORE_CLAMP_ENABLE
- GCC_UBI0_CORE_CLK
- GCC_UBI0_DBG_ARES
- GCC_UBI0_MPT_CLK
- GCC_UBI0_NC_AXI_ARES
- GCC_UBI0_NC_AXI_CLK
- GCC_UBI1_AHB_ARES
- GCC_UBI1_AHB_CLK
- GCC_UBI1_AXI_ARES
- GCC_UBI1_AXI_CLK
- GCC_UBI1_CLKRST_CLAMP_ENABLE
- GCC_UBI1_CORE_CLAMP_ENABLE
- GCC_UBI1_CORE_CLK
- GCC_UBI1_DBG_ARES
- GCC_UBI1_MPT_CLK
- GCC_UBI1_NC_AXI_ARES
- GCC_UBI1_NC_AXI_CLK
- GCC_UFS_AHB_CLK
- GCC_UFS_AXI_CLK
- GCC_UFS_AXI_HW_CTL_CLK
- GCC_UFS_BCR
- GCC_UFS_CARD_AHB_CLK
- GCC_UFS_CARD_AXI_CLK
- GCC_UFS_CARD_AXI_CLK_SRC
- GCC_UFS_CARD_AXI_HW_CTL_CLK
- GCC_UFS_CARD_BCR
- GCC_UFS_CARD_CLKREF_CLK
- GCC_UFS_CARD_ICE_CORE_CLK
- GCC_UFS_CARD_ICE_CORE_CLK_SRC
- GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK
- GCC_UFS_CARD_PHY_AUX_CLK
- GCC_UFS_CARD_PHY_AUX_CLK_SRC
- GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK
- GCC_UFS_CARD_RX_SYMBOL_0_CLK
- GCC_UFS_CARD_RX_SYMBOL_1_CLK
- GCC_UFS_CARD_TX_SYMBOL_0_CLK
- GCC_UFS_CARD_UNIPRO_CORE_CLK
- GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC
- GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK
- GCC_UFS_CLKREF_CLK
- GCC_UFS_ICE_CORE_CLK
- GCC_UFS_ICE_CORE_HW_CTL_CLK
- GCC_UFS_MEM_CLKREF_CLK
- GCC_UFS_PHY_AHB_CLK
- GCC_UFS_PHY_AUX_CLK
- GCC_UFS_PHY_AUX_HW_CTL_CLK
- GCC_UFS_PHY_AXI_CLK
- GCC_UFS_PHY_AXI_CLK_SRC
- GCC_UFS_PHY_AXI_HW_CTL_CLK
- GCC_UFS_PHY_BCR
- GCC_UFS_PHY_ICE_CORE_CLK
- GCC_UFS_PHY_ICE_CORE_CLK_SRC
- GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK
- GCC_UFS_PHY_PHY_AUX_CLK
- GCC_UFS_PHY_PHY_AUX_CLK_SRC
- GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK
- GCC_UFS_PHY_RX_SYMBOL_0_CLK
- GCC_UFS_PHY_RX_SYMBOL_1_CLK
- GCC_UFS_PHY_TX_SYMBOL_0_CLK
- GCC_UFS_PHY_UNIPRO_CORE_CLK
- GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC
- GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK
- GCC_UFS_RX_CFG_CLK
- GCC_UFS_RX_SYMBOL_0_CLK
- GCC_UFS_RX_SYMBOL_1_CLK
- GCC_UFS_SYS_CLK_CORE_CLK
- GCC_UFS_TX_CFG_CLK
- GCC_UFS_TX_SYMBOL_0_CLK
- GCC_UFS_TX_SYMBOL_1_CLK
- GCC_UFS_TX_SYMBOL_CLK_CORE_CLK
- GCC_UFS_UNIPRO_CORE_CLK
- GCC_UFS_UNIPRO_CORE_HW_CTL_CLK
- GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK
- GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK
- GCC_ULTAUDIO_AVSYNC_XO_CLK
- GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK
- GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK
- GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK
- GCC_ULTAUDIO_PCNOC_MPORT_CLK
- GCC_ULTAUDIO_PCNOC_SWAY_CLK
- GCC_ULTAUDIO_STC_XO_CLK
- GCC_ULT_AUDIO_BCR
- GCC_UNIPHY0_AHB_CLK
- GCC_UNIPHY0_BCR
- GCC_UNIPHY0_PORT1_RX_CLK
- GCC_UNIPHY0_PORT1_TX_CLK
- GCC_UNIPHY0_PORT2_RX_CLK
- GCC_UNIPHY0_PORT2_TX_CLK
- GCC_UNIPHY0_PORT3_RX_CLK
- GCC_UNIPHY0_PORT3_TX_CLK
- GCC_UNIPHY0_PORT4_RX_CLK
- GCC_UNIPHY0_PORT4_TX_CLK
- GCC_UNIPHY0_PORT5_RX_CLK
- GCC_UNIPHY0_PORT5_TX_CLK
- GCC_UNIPHY0_SYS_CLK
- GCC_UNIPHY1_AHB_CLK
- GCC_UNIPHY1_BCR
- GCC_UNIPHY1_PORT5_RX_CLK
- GCC_UNIPHY1_PORT5_TX_CLK
- GCC_UNIPHY1_SYS_CLK
- GCC_UNIPHY2_AHB_CLK
- GCC_UNIPHY2_BCR
- GCC_UNIPHY2_PORT6_RX_CLK
- GCC_UNIPHY2_PORT6_TX_CLK
- GCC_UNIPHY2_SYS_CLK
- GCC_USB0_AUX_CLK
- GCC_USB0_BCR
- GCC_USB0_MASTER_CLK
- GCC_USB0_MOCK_UTMI_CLK
- GCC_USB0_PHY_BCR
- GCC_USB0_PHY_CFG_AHB_CLK
- GCC_USB0_PIPE_CLK
- GCC_USB0_SLEEP_CLK
- GCC_USB0_TBU_BCR
- GCC_USB1_AUX_CLK
- GCC_USB1_BCR
- GCC_USB1_MASTER_CLK
- GCC_USB1_MOCK_UTMI_CLK
- GCC_USB1_PHY_BCR
- GCC_USB1_PHY_CFG_AHB_CLK
- GCC_USB1_PIPE_CLK
- GCC_USB1_SLEEP_CLK
- GCC_USB1_TBU_BCR
- GCC_USB20_MASTER_CLK
- GCC_USB20_MOCK_UTMI_CLK
- GCC_USB20_MOCK_UTMI_CLK_SRC
- GCC_USB20_SLEEP_CLK
- GCC_USB2A_PHY_BCR
- GCC_USB2A_PHY_SLEEP_CLK
- GCC_USB2B_PHY_BCR
- GCC_USB2B_PHY_SLEEP_CLK
- GCC_USB2_BCR
- GCC_USB2_HS_PHY_ONLY_BCR
- GCC_USB2_MASTER_CLK
- GCC_USB2_MOCK_UTMI_CLK
- GCC_USB2_PHY_BCR
- GCC_USB2_SLEEP_CLK
- GCC_USB30_MASTER_CLK
- GCC_USB30_MASTER_CLK_SRC
- GCC_USB30_MOCK_UTMI_CLK
- GCC_USB30_MOCK_UTMI_CLK_SRC
- GCC_USB30_PHY_COM_BCR
- GCC_USB30_PRIM_BCR
- GCC_USB30_PRIM_MASTER_CLK
- GCC_USB30_PRIM_MASTER_CLK_SRC
- GCC_USB30_PRIM_MOCK_UTMI_CLK
- GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC
- GCC_USB30_PRIM_SLEEP_CLK
- GCC_USB30_SEC_BCR
- GCC_USB30_SEC_MASTER_CLK
- GCC_USB30_SEC_MASTER_CLK_SRC
- GCC_USB30_SEC_MOCK_UTMI_CLK
- GCC_USB30_SEC_MOCK_UTMI_CLK_SRC
- GCC_USB30_SEC_SLEEP_CLK
- GCC_USB30_SLEEP_CLK
- GCC_USB3PHY_0_PHY_BCR
- GCC_USB3PHY_1_PHY_BCR
- GCC_USB3PHY_PHY_BCR
- GCC_USB3PHY_PHY_PRIM_BCR
- GCC_USB3PHY_PHY_SEC_BCR
- GCC_USB3_BCR
- GCC_USB3_CLKREF_CLK
- GCC_USB3_DP_PHY_BCR
- GCC_USB3_DP_PHY_PRIM_BCR
- GCC_USB3_DP_PHY_SEC_BCR
- GCC_USB3_MASTER_CLK
- GCC_USB3_MOCK_UTMI_CLK
- GCC_USB3_MOCK_UTMI_CLK_SRC
- GCC_USB3_PHY_AUX_CLK
- GCC_USB3_PHY_AUX_CLK_SRC
- GCC_USB3_PHY_BCR
- GCC_USB3_PHY_PIPE_CLK
- GCC_USB3_PHY_PRIM_BCR
- GCC_USB3_PHY_SEC_BCR
- GCC_USB3_PRIM_CLKREF_CLK
- GCC_USB3_PRIM_PHY_AUX_CLK
- GCC_USB3_PRIM_PHY_AUX_CLK_SRC
- GCC_USB3_PRIM_PHY_COM_AUX_CLK
- GCC_USB3_PRIM_PHY_PIPE_CLK
- GCC_USB3_SEC_CLKREF_CLK
- GCC_USB3_SEC_PHY_AUX_CLK
- GCC_USB3_SEC_PHY_AUX_CLK_SRC
- GCC_USB3_SEC_PHY_BCR
- GCC_USB3_SEC_PHY_COM_AUX_CLK
- GCC_USB3_SEC_PHY_PIPE_CLK
- GCC_USB3_SLEEP_CLK
- GCC_USB_20_BCR
- GCC_USB_30_BCR
- GCC_USB_30_SEC_BCR
- GCC_USB_HSIC_AHB_CLK
- GCC_USB_HSIC_CLK
- GCC_USB_HSIC_IO_CAL_CLK
- GCC_USB_HSIC_IO_CAL_SLEEP_CLK
- GCC_USB_HSIC_MOCK_UTMI_CLK
- GCC_USB_HSIC_SYSTEM_CLK
- GCC_USB_HS_AHB_CLK
- GCC_USB_HS_BCR
- GCC_USB_HS_HSIC_BCR
- GCC_USB_HS_INACTIVITY_TIMERS_CLK
- GCC_USB_HS_PHY_CFG_AHB_BCR
- GCC_USB_HS_PHY_CFG_AHB_CLK
- GCC_USB_HS_SYSTEM_CLK
- GCC_USB_HS_SYSTEM_CLK_SRC
- GCC_USB_PHY_CFG_AHB2PHY_BCR
- GCC_USB_PHY_CFG_AHB2PHY_CLK
- GCC_VDDA_VS_CLK
- GCC_VDDCX_VS_CLK
- GCC_VDDMX_VS_CLK
- GCC_VENUS0_AHB_CLK
- GCC_VENUS0_AXI_CLK
- GCC_VENUS0_BCR
- GCC_VENUS0_VCODEC0_CLK
- GCC_VENUS_RESTART
- GCC_VENUS_TBU_BCR
- GCC_VENUS_TBU_CLK
- GCC_VERSION
- GCC_VFE_TBU_BCR
- GCC_VFE_TBU_CLK
- GCC_VIDEO_AHB_CLK
- GCC_VIDEO_AXI0_CLK
- GCC_VIDEO_AXI1_CLK
- GCC_VIDEO_AXIC_CLK
- GCC_VIDEO_AXI_CLK
- GCC_VIDEO_XO_CLK
- GCC_VSENSOR_CLK_SRC
- GCC_VSYNC_CLK_SRC
- GCC_VS_BCR
- GCC_VS_CTRL_AHB_CLK
- GCC_VS_CTRL_CLK
- GCC_VS_CTRL_CLK_SRC
- GCC_WCSS2G_CLK
- GCC_WCSS2G_REF_CLK
- GCC_WCSS2G_RTC_CLK
- GCC_WCSS5G_CLK
- GCC_WCSS5G_REF_CLK
- GCC_WCSS5G_RTC_CLK
- GCC_WCSS_BCR
- GCC_WCSS_CORE_TBU_BCR
- GCC_WCSS_GPLL1_CLK_SRC
- GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA
- GCC_WCSS_Q6_AHB_CLK
- GCC_WCSS_Q6_AXIM_CLK
- GCC_WCSS_Q6_BCR
- GCC_WCSS_Q6_TBU_BCR
- GCC_WCSS_RESTART
- GCC_WDSP_RESTART
- GCC_XO_CLK
- GCC_XO_CLK_SRC
- GCC_XO_DIV4_CLK
- GCDESCRIBE
- GCDGMBUS
- GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK
- GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT
- GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK
- GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT
- GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK
- GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT
- GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK
- GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT
- GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK
- GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT
- GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK
- GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK
- GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK
- GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK
- GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK
- GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT
- GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK
- GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK
- GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK
- GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT
- GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK
- GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT
- GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK
- GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT
- GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK
- GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT
- GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK
- GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT
- GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK
- GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK
- GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK
- GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK
- GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK
- GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT
- GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK
- GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK
- GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK
- GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK
- GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK
- GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK
- GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK
- GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT
- GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK
- GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT
- GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK
- GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT
- GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK
- GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT
- GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK
- GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT
- GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK
- GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT
- GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK
- GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT
- GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK
- GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT
- GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK
- GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT
- GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK
- GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT
- GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK
- GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT
- GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK
- GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT
- GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK
- GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT
- GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK
- GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT
- GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK
- GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT
- GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK
- GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT
- GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK
- GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT
- GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK
- GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT
- GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK
- GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT
- GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK
- GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT
- GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK
- GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT
- GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK
- GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT
- GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK
- GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT
- GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK
- GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT
- GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK
- GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT
- GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK
- GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT
- GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK
- GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT
- GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK
- GCEA_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK
- GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK
- GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK
- GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT
- GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK
- GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK
- GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK
- GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK
- GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT
- GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK
- GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT
- GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK
- GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT
- GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK
- GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK
- GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK
- GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK
- GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK
- GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK
- GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK
- GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK
- GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT
- GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK
- GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT
- GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK
- GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT
- GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK
- GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT
- GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK
- GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT
- GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- GCEA_CGTT_CLK_CTRL__SPARE0_MASK
- GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT
- GCEA_CGTT_CLK_CTRL__SPARE1_MASK
- GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE_MASK
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE__SHIFT
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL_MASK
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL__SHIFT
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE_MASK
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE__SHIFT
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB_MASK
- GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB__SHIFT
- GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK
- GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE_MASK
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE__SHIFT
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE_MASK
- GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE__SHIFT
- GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK
- GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT
- GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK
- GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT
- GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK
- GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT
- GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK
- GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK
- GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK
- GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK
- GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK
- GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK
- GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT
- GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK
- GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT
- GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK
- GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT
- GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK
- GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT
- GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK
- GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK
- GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK
- GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT
- GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK
- GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK
- GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK
- GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK
- GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK
- GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK
- GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT
- GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK
- GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT
- GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK
- GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT
- GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK
- GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT
- GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK
- GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK
- GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK
- GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT
- GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK
- GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT
- GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK
- GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT
- GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK
- GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT
- GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK
- GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT
- GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK
- GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT
- GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK
- GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK
- GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK
- GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK
- GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK
- GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK
- GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK
- GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK
- GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK
- GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK
- GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK
- GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK
- GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT
- GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK
- GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT
- GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK
- GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT
- GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK
- GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT
- GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK
- GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT
- GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK
- GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT
- GCEA_ERR_STATUS__FUE_FLAG_MASK
- GCEA_ERR_STATUS__FUE_FLAG__SHIFT
- GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK
- GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT
- GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK
- GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT
- GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK
- GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT
- GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK
- GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT
- GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK
- GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT
- GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK
- GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT
- GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK
- GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT
- GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK
- GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT
- GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK
- GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT
- GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK
- GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT
- GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK
- GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT
- GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK
- GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK
- GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT
- GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK
- GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT
- GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK
- GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT
- GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK
- GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT
- GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK
- GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT
- GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK
- GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT
- GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK
- GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT
- GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK
- GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT
- GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK
- GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT
- GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK
- GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT
- GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK
- GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT
- GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK
- GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK
- GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK
- GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK
- GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK
- GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT
- GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK
- GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK
- GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT
- GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK
- GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT
- GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK
- GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT
- GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK
- GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT
- GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK
- GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT
- GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK
- GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK
- GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK
- GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK
- GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK
- GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT
- GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK
- GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK
- GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT
- GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK
- GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT
- GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK
- GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT
- GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK
- GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT
- GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK
- GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT
- GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK
- GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT
- GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK
- GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT
- GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK
- GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT
- GCEA_MISC__EARLY_SDP_ORIGDATA_MASK
- GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT
- GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK
- GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT
- GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK
- GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT
- GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK
- GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT
- GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK
- GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT
- GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK
- GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT
- GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK
- GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT
- GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK
- GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT
- GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK
- GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT
- GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK
- GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT
- GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK
- GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT
- GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK
- GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT
- GCEA_PERFCOUNTER0_CFG__CLEAR_MASK
- GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT
- GCEA_PERFCOUNTER0_CFG__ENABLE_MASK
- GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT
- GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK
- GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK
- GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- GCEA_PERFCOUNTER1_CFG__CLEAR_MASK
- GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT
- GCEA_PERFCOUNTER1_CFG__ENABLE_MASK
- GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT
- GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK
- GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK
- GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK
- GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT
- GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK
- GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK
- GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK
- GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT
- GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK
- GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT
- GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK
- GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT
- GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK
- GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT
- GCEA_PROBE_MAP__INTLV_SIZE_MASK
- GCEA_PROBE_MAP__INTLV_SIZE__SHIFT
- GCEA_RRET_MEM_RESERVE__VC0_MASK
- GCEA_RRET_MEM_RESERVE__VC0__SHIFT
- GCEA_RRET_MEM_RESERVE__VC1_MASK
- GCEA_RRET_MEM_RESERVE__VC1__SHIFT
- GCEA_RRET_MEM_RESERVE__VC2_MASK
- GCEA_RRET_MEM_RESERVE__VC2__SHIFT
- GCEA_RRET_MEM_RESERVE__VC3_MASK
- GCEA_RRET_MEM_RESERVE__VC3__SHIFT
- GCEA_RRET_MEM_RESERVE__VC4_MASK
- GCEA_RRET_MEM_RESERVE__VC4__SHIFT
- GCEA_RRET_MEM_RESERVE__VC5_MASK
- GCEA_RRET_MEM_RESERVE__VC5__SHIFT
- GCEA_RRET_MEM_RESERVE__VC6_MASK
- GCEA_RRET_MEM_RESERVE__VC6__SHIFT
- GCEA_RRET_MEM_RESERVE__VC7_MASK
- GCEA_RRET_MEM_RESERVE__VC7__SHIFT
- GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK
- GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT
- GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK
- GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT
- GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK
- GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT
- GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK
- GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT
- GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK
- GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT
- GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK
- GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT
- GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK
- GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT
- GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK
- GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT
- GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK
- GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT
- GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK
- GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT
- GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK
- GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT
- GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK
- GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT
- GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK
- GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT
- GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK
- GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT
- GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK
- GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT
- GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK
- GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK
- GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT
- GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK
- GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT
- GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK
- GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT
- GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK
- GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT
- GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK
- GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT
- GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK
- GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT
- GCEA_SDP_CREDITS__TAG_LIMIT_MASK
- GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT
- GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK
- GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK
- GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT
- GCEA_SDP_ENABLE__ENABLE_MASK
- GCEA_SDP_ENABLE__ENABLE__SHIFT
- GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT
- GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK
- GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT
- GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK
- GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT
- GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK
- GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK
- GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT
- GCEA_SDP_TAG_RESERVE0__VC0_MASK
- GCEA_SDP_TAG_RESERVE0__VC0__SHIFT
- GCEA_SDP_TAG_RESERVE0__VC1_MASK
- GCEA_SDP_TAG_RESERVE0__VC1__SHIFT
- GCEA_SDP_TAG_RESERVE0__VC2_MASK
- GCEA_SDP_TAG_RESERVE0__VC2__SHIFT
- GCEA_SDP_TAG_RESERVE0__VC3_MASK
- GCEA_SDP_TAG_RESERVE0__VC3__SHIFT
- GCEA_SDP_TAG_RESERVE1__VC4_MASK
- GCEA_SDP_TAG_RESERVE1__VC4__SHIFT
- GCEA_SDP_TAG_RESERVE1__VC5_MASK
- GCEA_SDP_TAG_RESERVE1__VC5__SHIFT
- GCEA_SDP_TAG_RESERVE1__VC6_MASK
- GCEA_SDP_TAG_RESERVE1__VC6__SHIFT
- GCEA_SDP_TAG_RESERVE1__VC7_MASK
- GCEA_SDP_TAG_RESERVE1__VC7__SHIFT
- GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK
- GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT
- GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT
- GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK
- GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK
- GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT
- GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT
- GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK
- GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT
- GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK
- GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT
- GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK
- GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT
- GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK
- GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT
- GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK
- GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT
- GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK
- GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT
- GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK
- GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT
- GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK
- GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT
- GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK
- GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT
- GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK
- GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT
- GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK
- GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT
- GCEA_TCC_XBR_MAXBURST__IO_RD_MASK
- GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT
- GCEA_TCC_XBR_MAXBURST__IO_WR_MASK
- GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT
- GCFASTLOCK
- GCFGC
- GCFGC2
- GCFG_DIS
- GCHD
- GCID
- GCI_CONTROL
- GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT
- GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK
- GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSMCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSMCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT
- GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK
- GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT
- GCK_ID_CLASSD
- GCK_ID_I2S0
- GCK_ID_I2S1
- GCK_INDEX_DT_AUDIO_PLL
- GCK_MCLK_FUSES__MClkADCA_MASK
- GCK_MCLK_FUSES__MClkADCA__SHIFT
- GCK_MCLK_FUSES__MClkDDCA_MASK
- GCK_MCLK_FUSES__MClkDDCA__SHIFT
- GCK_MCLK_FUSES__MClkDiDtFloor_MASK
- GCK_MCLK_FUSES__MClkDiDtFloor__SHIFT
- GCK_MCLK_FUSES__MClkDiDtWait_MASK
- GCK_MCLK_FUSES__MClkDiDtWait__SHIFT
- GCK_MCLK_FUSES__StartupMClkDid_MASK
- GCK_MCLK_FUSES__StartupMClkDid__SHIFT
- GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK
- GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT
- GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK
- GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT
- GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK
- GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT
- GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK
- GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT
- GCK_PLL_TEST_CNTL__TST_RESET_MASK
- GCK_PLL_TEST_CNTL__TST_RESET__SHIFT
- GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK
- GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT
- GCK_SMC_IND_DATA__SMC_IND_DATA_MASK
- GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT
- GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK
- GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT
- GCLK_EN
- GCLOCK
- GCLOCK_MINIMUM
- GCMAP
- GCMAP_HPUX
- GCMC_MEM_POWER_LS__LS_HOLD_MASK
- GCMC_MEM_POWER_LS__LS_HOLD__SHIFT
- GCMC_MEM_POWER_LS__LS_SETUP_MASK
- GCMC_MEM_POWER_LS__LS_SETUP__SHIFT
- GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK
- GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT
- GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK
- GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT
- GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK
- GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT
- GCMC_SHARED_VIRT_RESET_REQ__PF_MASK
- GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT
- GCMC_SHARED_VIRT_RESET_REQ__VF_MASK
- GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT
- GCMC_VM_AGP_BASE__AGP_BASE_MASK
- GCMC_VM_AGP_BASE__AGP_BASE__SHIFT
- GCMC_VM_AGP_BOT__AGP_BOT_MASK
- GCMC_VM_AGP_BOT__AGP_BOT__SHIFT
- GCMC_VM_AGP_TOP__AGP_TOP_MASK
- GCMC_VM_AGP_TOP__AGP_TOP__SHIFT
- GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK
- GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT
- GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK
- GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT
- GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK
- GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT
- GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK
- GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT
- GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK
- GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT
- GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK
- GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT
- GCMC_VM_FB_OFFSET__FB_OFFSET_MASK
- GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT
- GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK
- GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT
- GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK
- GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT
- GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK
- GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK
- GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT
- GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
- GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
- GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK
- GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT
- GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK
- GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT
- GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK
- GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT
- GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK
- GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT
- GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK
- GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT
- GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK
- GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT
- GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK
- GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT
- GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK
- GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT
- GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK
- GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT
- GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK
- GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT
- GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK
- GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT
- GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK
- GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT
- GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK
- GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT
- GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK
- GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT
- GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK
- GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT
- GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK
- GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT
- GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK
- GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT
- GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK
- GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT
- GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK
- GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT
- GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK
- GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT
- GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK
- GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT
- GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK
- GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT
- GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK
- GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT
- GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK
- GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT
- GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK
- GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT
- GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK
- GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT
- GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK
- GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT
- GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK
- GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT
- GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK
- GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT
- GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK
- GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT
- GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK
- GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT
- GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK
- GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT
- GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK
- GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT
- GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK
- GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT
- GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK
- GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK
- GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
- GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
- GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK
- GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
- GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
- GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
- GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
- GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK
- GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT
- GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK
- GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT
- GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK
- GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT
- GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK
- GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT
- GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK
- GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT
- GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK
- GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT
- GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK
- GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT
- GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK
- GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT
- GCMC_VM_STEERING__DEFAULT_STEERING_MASK
- GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT
- GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK
- GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT
- GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK
- GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT
- GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK
- GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT
- GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK
- GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT
- GCMP_ADDRSPACE_SZ
- GCMP_BASE_ADDR
- GCM_AAD_LEN
- GCM_AES_IV_LEN
- GCM_AES_IV_SIZE
- GCM_AES_SALT_SIZE
- GCM_BLOCK_LEN
- GCM_BLOCK_LEN_SIZE
- GCM_BLOCK_RFC4_IV_OFFSET
- GCM_BLOCK_RFC4_IV_SIZE
- GCM_BLOCK_RFC4_NONCE_OFFSET
- GCM_BLOCK_RFC4_NONCE_SIZE
- GCM_COMPLETE
- GCM_CTR_INIT
- GCM_CTX
- GCM_DESC_JOB_IO_LEN
- GCM_ENC_DEC
- GCM_ESP_DIGESTSIZE
- GCM_ESP_IV_SIZE
- GCM_ESP_SALT_OFFSET
- GCM_ESP_SALT_SIZE
- GCM_INIT
- GCM_IV_SIZE
- GCM_RFC4106_IV_SIZE
- GCM_RFC4543_IV_SIZE
- GCM_TAG_SIZE
- GCOFF
- GCON
- GCOV_ADD
- GCOV_COUNTERS
- GCOV_DATA_MAGIC
- GCOV_H
- GCOV_REMOVE
- GCOV_TAG_COUNTER_BASE
- GCOV_TAG_FOR_COUNTER
- GCOV_TAG_FUNCTION
- GCOV_TAG_FUNCTION_LENGTH
- GCPT
- GCP_AV_MUTE
- GCP_COLOR_INDICATION
- GCP_DEFAULT_PHASE_ENABLE
- GCR
- GCR3_VALID
- GCRCR
- GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK
- GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT
- GCRPerfSel
- GCR_ACCESSOR_RO
- GCR_ACCESSOR_RW
- GCR_ACKINT
- GCR_ACLINK_OFF
- GCR_ADDR_MARK
- GCR_A_INIT
- GCR_A_REG
- GCR_A_REMAP
- GCR_A_RUN
- GCR_B_ACTIVE
- GCR_B_DOZE
- GCR_B_REG
- GCR_CDONE_IE
- GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
- GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
- GCR_CGTT_SCLK_CTRL__ON_DELAY_MASK
- GCR_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
- GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
- GCR_CHAN_ENABLE
- GCR_CHIP_ID_HI
- GCR_CHIP_ID_LO
- GCR_CLKBPB
- GCR_CL_COHERENCE_OFS
- GCR_CL_ID_OFS
- GCR_CMD_STATUS__GCR_CONTROL_MASK
- GCR_CMD_STATUS__GCR_CONTROL__SHIFT
- GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK
- GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT
- GCR_CMD_STATUS__GCR_SRC_MASK
- GCR_CMD_STATUS__GCR_SRC__SHIFT
- GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK
- GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK
- GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT
- GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT
- GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK
- GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT
- GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK
- GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT
- GCR_COLD_RST
- GCR_CONFIG_PORT_SEL
- GCR_CORES
- GCR_CPC_BASE_OFS
- GCR_CX_ACCESSOR_RO
- GCR_CX_ACCESSOR_RW
- GCR_DATA
- GCR_DATA_MARK
- GCR_DEN
- GCR_DEPOL
- GCR_DESC_TYPE_HOST
- GCR_ENINT
- GCR_FIRST_MARK
- GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK
- GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT
- GCR_GENERAL_CNTL__CLIENT_ID_MASK
- GCR_GENERAL_CNTL__CLIENT_ID__SHIFT
- GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK
- GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT
- GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK
- GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT
- GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK
- GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT
- GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK
- GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT
- GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK
- GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT
- GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK
- GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT
- GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK
- GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT
- GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK
- GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT
- GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK
- GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT
- GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK
- GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT
- GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK
- GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT
- GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK
- GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT
- GCR_GIE
- GCR_HSPOL
- GCR_INDEX
- GCR_KBMOUSE_WAKEUP
- GCR_LOGICAL_DEV_NO
- GCR_LTDCEN
- GCR_MODE
- GCR_MODE_MIXED
- GCR_MODE_PASS
- GCR_MODE_PROXY
- GCR_PCPOL
- GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK
- GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT
- GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GCR_PERF_SEL_ALL_REQ
- GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ
- GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ
- GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ
- GCR_PERF_SEL_CPC_ALL_REQ
- GCR_PERF_SEL_CPC_GL1_ALL_REQ
- GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ
- GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPC_GL1_RANGE_REQ
- GCR_PERF_SEL_CPC_GL2_ALL_REQ
- GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ
- GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPC_GL2_RANGE_REQ
- GCR_PERF_SEL_CPC_METADATA_REQ
- GCR_PERF_SEL_CPC_SQC_DATA_REQ
- GCR_PERF_SEL_CPC_SQC_INST_REQ
- GCR_PERF_SEL_CPC_TCP_REQ
- GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ
- GCR_PERF_SEL_CPF_ALL_REQ
- GCR_PERF_SEL_CPF_GL1_ALL_REQ
- GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ
- GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPF_GL1_RANGE_REQ
- GCR_PERF_SEL_CPF_GL2_ALL_REQ
- GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ
- GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPF_GL2_RANGE_REQ
- GCR_PERF_SEL_CPF_METADATA_REQ
- GCR_PERF_SEL_CPF_SQC_DATA_REQ
- GCR_PERF_SEL_CPF_SQC_INST_REQ
- GCR_PERF_SEL_CPF_TCP_REQ
- GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ
- GCR_PERF_SEL_CPG_ALL_REQ
- GCR_PERF_SEL_CPG_GL1_ALL_REQ
- GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ
- GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPG_GL1_RANGE_REQ
- GCR_PERF_SEL_CPG_GL2_ALL_REQ
- GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ
- GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ
- GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ
- GCR_PERF_SEL_CPG_GL2_RANGE_REQ
- GCR_PERF_SEL_CPG_METADATA_REQ
- GCR_PERF_SEL_CPG_SQC_DATA_REQ
- GCR_PERF_SEL_CPG_SQC_INST_REQ
- GCR_PERF_SEL_CPG_TCP_REQ
- GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ
- GCR_PERF_SEL_NONE
- GCR_PERF_SEL_PHY_REQ
- GCR_PERF_SEL_SDMA0_ALL_REQ
- GCR_PERF_SEL_SDMA0_GL1_ALL_REQ
- GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ
- GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ
- GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ
- GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ
- GCR_PERF_SEL_SDMA0_GL2_ALL_REQ
- GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ
- GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ
- GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ
- GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ
- GCR_PERF_SEL_SDMA0_METADATA_REQ
- GCR_PERF_SEL_SDMA0_SQC_DATA_REQ
- GCR_PERF_SEL_SDMA0_SQC_INST_REQ
- GCR_PERF_SEL_SDMA0_TCP_REQ
- GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ
- GCR_PERF_SEL_SDMA1_ALL_REQ
- GCR_PERF_SEL_SDMA1_GL1_ALL_REQ
- GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ
- GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ
- GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ
- GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ
- GCR_PERF_SEL_SDMA1_GL2_ALL_REQ
- GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ
- GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ
- GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ
- GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ
- GCR_PERF_SEL_SDMA1_METADATA_REQ
- GCR_PERF_SEL_SDMA1_SQC_DATA_REQ
- GCR_PERF_SEL_SDMA1_SQC_INST_REQ
- GCR_PERF_SEL_SDMA1_TCP_REQ
- GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ
- GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ
- GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ
- GCR_PERF_SEL_UTCL2_FILTERED_RET
- GCR_PERF_SEL_UTCL2_INFLIGHT_REQ
- GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT
- GCR_PERF_SEL_UTCL2_REQ
- GCR_PERF_SEL_UTCL2_RET
- GCR_PERF_SEL_VIRT_REQ
- GCR_PIO_CNTL__GCR_DATA_INDEX_MASK
- GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT
- GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK
- GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT
- GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK
- GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT
- GCR_PIO_CNTL__GCR_READY_MASK
- GCR_PIO_CNTL__GCR_READY__SHIFT
- GCR_PIO_CNTL__GCR_REG_DONE_MASK
- GCR_PIO_CNTL__GCR_REG_DONE__SHIFT
- GCR_PIO_CNTL__GCR_REG_RESET_MASK
- GCR_PIO_CNTL__GCR_REG_RESET__SHIFT
- GCR_PIO_DATA__GCR_DATA_MASK
- GCR_PIO_DATA__GCR_DATA__SHIFT
- GCR_PRIRDY_IEN
- GCR_PRIRES_IEN
- GCR_REMAP
- GCR_RESET
- GCR_SDONE_IE
- GCR_SECOND_MARK
- GCR_SECRDY_IEN
- GCR_SECRES_IEN
- GCR_SELF_SYNC
- GCR_SLIP_BYTE
- GCR_SOFTWARE_RESET
- GCR_SPARE__SPARE_BIT_1_MASK
- GCR_SPARE__SPARE_BIT_1__SHIFT
- GCR_SPARE__SPARE_BIT_2_MASK
- GCR_SPARE__SPARE_BIT_2__SHIFT
- GCR_SPARE__SPARE_BIT_31_16_MASK
- GCR_SPARE__SPARE_BIT_31_16__SHIFT
- GCR_SPARE__SPARE_BIT_3_MASK
- GCR_SPARE__SPARE_BIT_3__SHIFT
- GCR_SPARE__SPARE_BIT_4_MASK
- GCR_SPARE__SPARE_BIT_4__SHIFT
- GCR_SPARE__SPARE_BIT_5_MASK
- GCR_SPARE__SPARE_BIT_5__SHIFT
- GCR_SPARE__SPARE_BIT_6_MASK
- GCR_SPARE__SPARE_BIT_6__SHIFT
- GCR_SPARE__SPARE_BIT_7_MASK
- GCR_SPARE__SPARE_BIT_7__SHIFT
- GCR_SPARE__SPARE_BIT_8_0_MASK
- GCR_SPARE__SPARE_BIT_8_0__SHIFT
- GCR_STARV_RETRY
- GCR_SWRES
- GCR_SYNC_CONV
- GCR_SYNC_EXC
- GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA0_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_SA0_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA0_VIRT_MASK
- GCR_TARGET_DISABLE__DISABLE_SA0_VIRT__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA1_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_SA1_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA1_VIRT_MASK
- GCR_TARGET_DISABLE__DISABLE_SA1_VIRT__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA2_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_SA2_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA2_VIRT_MASK
- GCR_TARGET_DISABLE__DISABLE_SA2_VIRT__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA3_PHY_MASK
- GCR_TARGET_DISABLE__DISABLE_SA3_PHY__SHIFT
- GCR_TARGET_DISABLE__DISABLE_SA3_VIRT_MASK
- GCR_TARGET_DISABLE__DISABLE_SA3_VIRT__SHIFT
- GCR_TEARDOWN
- GCR_VENDOR_ID_HI
- GCR_VENDOR_ID_LO
- GCR_VSPOL
- GCR_WARM_RST
- GCR_nDMAEN
- GCSR_CCIC_EN
- GCSR_MRC
- GCSR_MRS
- GCSR_SRC
- GCSR_SRS
- GCSTATIC_CMAP
- GCT0
- GCT1
- GCT2
- GCTERM
- GCTL
- GCTL_ABP
- GCTL_AID
- GCTL_AIE
- GCTL_BEP
- GCTL_BES
- GCTL_DBP
- GCTL_DPC
- GCTL_DSP
- GCTL_EAC
- GCTL_EAI
- GCTL_ET
- GCTL_FBP
- GCTL_ME
- GCTL_MRL
- GCTL_PR
- GCTL_SBP
- GCTL_SD
- GCTL_SDE
- GCTL_SDI
- GCTL_SE
- GCTL_SM
- GCTL_SR
- GCTL_TBP
- GCTL_UAA
- GCTL_XA
- GCTRL
- GCT_NODE_MAGIC
- GCT_NODE_PTR
- GCT_SUBTYPE_IO_PORT_MODULE
- GCT_TYPE_HOSE
- GCUNLOCK
- GCUNLOCK_MINIMUM
- GCUNMAP
- GCUNMAP_HPUX
- GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GCUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK
- GCUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK
- GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT
- GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- GCU_CONFIG_CVAL
- GCU_CONFIG_VALID0
- GCU_CONFIG_VALID1
- GCU_CONTROL_MODE
- GCU_CONTROL_SRST
- GCU_IRQ_CVAL0
- GCU_IRQ_CVAL1
- GCU_IRQ_ERR
- GCU_IRQ_MODE
- GCU_STATUS_ACTIVE
- GCU_STATUS_MERR
- GCU_STATUS_MODE
- GCU_STATUS_TCS0
- GCU_STATUS_TCS1
- GCVARIABLE_CMAP
- GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK
- GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT
- GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK
- GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK
- GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK
- GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK
- GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK
- GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT
- GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK
- GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT
- GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK
- GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK
- GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK
- GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK
- GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK
- GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT
- GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK
- GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT
- GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK
- GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT
- GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK
- GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT
- GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK
- GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT
- GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK
- GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT
- GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
- GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
- GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK
- GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT
- GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK
- GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT
- GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
- GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
- GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
- GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
- GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
- GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK
- GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT
- GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK
- GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT
- GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK
- GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK
- GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT
- GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK
- GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT
- GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK
- GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT
- GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK
- GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
- GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK
- GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK
- GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK
- GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT
- GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK
- GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
- GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK
- GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT
- GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK
- GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT
- GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK
- GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT
- GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK
- GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK
- GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK
- GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK
- GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT
- GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GCVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
- GCVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK
- GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT
- GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
- GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
- GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
- GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT
- GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK
- GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT
- GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
- GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT
- GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK
- GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT
- GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK
- GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT
- GCVM_L2_CNTL3__BANK_SELECT_MASK
- GCVM_L2_CNTL3__BANK_SELECT__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK
- GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK
- GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK
- GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
- GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK
- GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK
- GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK
- GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK
- GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT
- GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
- GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
- GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK
- GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT
- GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK
- GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT
- GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK
- GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT
- GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK
- GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT
- GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
- GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
- GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK
- GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT
- GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK
- GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT
- GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK
- GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT
- GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK
- GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT
- GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK
- GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
- GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK
- GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
- GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
- GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
- GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK
- GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT
- GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
- GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT
- GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
- GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
- GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK
- GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT
- GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK
- GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT
- GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK
- GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT
- GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK
- GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT
- GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK
- GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT
- GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK
- GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT
- GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK
- GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
- GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
- GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK
- GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT
- GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK
- GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT
- GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK
- GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT
- GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK
- GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK
- GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT
- GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK
- GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT
- GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
- GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
- GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
- GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK
- GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT
- GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK
- GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT
- GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
- GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
- GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
- GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT
- GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK
- GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT
- GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK
- GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT
- GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK
- GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT
- GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK
- GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT
- GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK
- GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT
- GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK
- GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT
- GCVM_L2_STATUS__L2_BUSY_MASK
- GCVM_L2_STATUS__L2_BUSY__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK
- GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
- GCVM_PCIE_ATS_CNTL__STU_MASK
- GCVM_PCIE_ATS_CNTL__STU__SHIFT
- GC_2D3D_REV
- GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK
- GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT
- GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK
- GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT
- GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK
- GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT
- GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK
- GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT
- GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK
- GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT
- GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK
- GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT
- GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
- GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
- GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
- GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
- GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
- GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
- GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
- GC_ATC_L2_CNTL2__BANK_SELECT_MASK
- GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT
- GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK
- GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
- GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK
- GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT
- GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK
- GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT
- GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
- GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
- GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK
- GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT
- GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK
- GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT
- GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK
- GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT
- GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK
- GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT
- GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK
- GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT
- GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK
- GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT
- GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
- GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK
- GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT
- GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK
- GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT
- GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK
- GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT
- GC_ATC_L2_MISC_CG__ENABLE_MASK
- GC_ATC_L2_MISC_CG__ENABLE__SHIFT
- GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK
- GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT
- GC_ATC_L2_MISC_CG__OFFDLY_MASK
- GC_ATC_L2_MISC_CG__OFFDLY__SHIFT
- GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK
- GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
- GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK
- GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
- GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK
- GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
- GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK
- GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
- GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK
- GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
- GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
- GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK
- GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT
- GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK
- GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT
- GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK
- GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT
- GC_ATC_L2_STATUS__BUSY_MASK
- GC_ATC_L2_STATUS__BUSY__SHIFT
- GC_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK
- GC_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT
- GC_BASE__INST0_SEG0
- GC_BASE__INST0_SEG1
- GC_BASE__INST0_SEG2
- GC_BASE__INST0_SEG3
- GC_BASE__INST0_SEG4
- GC_BASE__INST0_SEG5
- GC_BASE__INST1_SEG0
- GC_BASE__INST1_SEG1
- GC_BASE__INST1_SEG2
- GC_BASE__INST1_SEG3
- GC_BASE__INST1_SEG4
- GC_BASE__INST1_SEG5
- GC_BASE__INST2_SEG0
- GC_BASE__INST2_SEG1
- GC_BASE__INST2_SEG2
- GC_BASE__INST2_SEG3
- GC_BASE__INST2_SEG4
- GC_BASE__INST2_SEG5
- GC_BASE__INST3_SEG0
- GC_BASE__INST3_SEG1
- GC_BASE__INST3_SEG2
- GC_BASE__INST3_SEG3
- GC_BASE__INST3_SEG4
- GC_BASE__INST3_SEG5
- GC_BASE__INST4_SEG0
- GC_BASE__INST4_SEG1
- GC_BASE__INST4_SEG2
- GC_BASE__INST4_SEG3
- GC_BASE__INST4_SEG4
- GC_BASE__INST4_SEG5
- GC_BASE__INST5_SEG0
- GC_BASE__INST5_SEG1
- GC_BASE__INST5_SEG2
- GC_BASE__INST5_SEG3
- GC_BASE__INST5_SEG4
- GC_BASE__INST5_SEG5
- GC_BASE__INST6_SEG0
- GC_BASE__INST6_SEG1
- GC_BASE__INST6_SEG2
- GC_BASE__INST6_SEG3
- GC_BASE__INST6_SEG4
- GC_BASE__INST6_SEG5
- GC_BASE__INST7_SEG0
- GC_BASE__INST7_SEG1
- GC_BASE__INST7_SEG2
- GC_BASE__INST7_SEG3
- GC_BASE__INST7_SEG4
- GC_BASE__INST7_SEG5
- GC_BLOCK_COUNT
- GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CH0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CH0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK
- GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT
- GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK
- GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT
- GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT
- GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK
- GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT
- GC_CAC_AGGR_LOWER__AGGR_31_0_MASK
- GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT
- GC_CAC_AGGR_UPPER__AGGR_63_32_MASK
- GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT
- GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK
- GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK
- GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT
- GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK
- GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT
- GC_CAC_CNTL__CAC_BLOCK_ID_MASK
- GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT
- GC_CAC_CNTL__CAC_ENABLE_MASK
- GC_CAC_CNTL__CAC_ENABLE__SHIFT
- GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK
- GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT
- GC_CAC_CNTL__CAC_SIGNAL_ID_MASK
- GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT
- GC_CAC_CNTL__CAC_THRESHOLD_MASK
- GC_CAC_CNTL__CAC_THRESHOLD__SHIFT
- GC_CAC_CNTL__UNUSED_0_MASK
- GC_CAC_CNTL__UNUSED_0__SHIFT
- GC_CAC_CTRL_1__CAC_WINDOW_MASK
- GC_CAC_CTRL_1__CAC_WINDOW__SHIFT
- GC_CAC_CTRL_1__TDP_WINDOW_MASK
- GC_CAC_CTRL_1__TDP_WINDOW__SHIFT
- GC_CAC_CTRL_2__CAC_ENABLE_MASK
- GC_CAC_CTRL_2__CAC_ENABLE__SHIFT
- GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK
- GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT
- GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK
- GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT
- GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK
- GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT
- GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK
- GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT
- GC_CAC_CTRL_2__UNUSED_0_MASK
- GC_CAC_CTRL_2__UNUSED_0__SHIFT
- GC_CAC_ID__CAC_BLOCK_ID_MASK
- GC_CAC_ID__CAC_BLOCK_ID__SHIFT
- GC_CAC_ID__CAC_SIGNAL_ID_MASK
- GC_CAC_ID__CAC_SIGNAL_ID__SHIFT
- GC_CAC_ID__UNUSED_0_MASK
- GC_CAC_ID__UNUSED_0__SHIFT
- GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN_MASK
- GC_CAC_INDEX_AUTO_INCR_EN__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT
- GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK
- GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT
- GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK
- GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT
- GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK
- GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT
- GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK
- GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT
- GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK
- GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK
- GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK
- GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK
- GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_CB__OVRRD_SELECT_MASK
- GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_CB__OVRRD_VALUE_MASK
- GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_CP__OVRRD_SELECT_MASK
- GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_CP__OVRRD_VALUE_MASK
- GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_CU__OVRRD_SELECT_MASK
- GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_CU__OVRRD_VALUE_MASK
- GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK
- GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK
- GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_DB__OVRRD_SELECT_MASK
- GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_DB__OVRRD_VALUE_MASK
- GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_EA__OVRRD_SELECT_MASK
- GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_EA__OVRRD_VALUE_MASK
- GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK
- GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK
- GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_GE__OVRRD_SELECT_MASK
- GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_GE__OVRRD_VALUE_MASK
- GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK
- GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK
- GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK
- GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK
- GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_IA__OVRRD_SELECT_MASK
- GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_IA__OVRRD_VALUE_MASK
- GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK
- GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK
- GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_PA__OVRRD_SELECT_MASK
- GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_PA__OVRRD_VALUE_MASK
- GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_PC__OVRRD_SELECT_MASK
- GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_PC__OVRRD_VALUE_MASK
- GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_PG__OVRRD_SELECT_MASK
- GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_PG__OVRRD_VALUE_MASK
- GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_PH__OVRRD_SELECT_MASK
- GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_PH__OVRRD_VALUE_MASK
- GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK
- GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK
- GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK
- GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK
- GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_SC__OVRRD_SELECT_MASK
- GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_SC__OVRRD_VALUE_MASK
- GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK
- GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK
- GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK
- GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK
- GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK
- GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK
- GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_SX__OVRRD_SELECT_MASK
- GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_SX__OVRRD_VALUE_MASK
- GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_TA__OVRRD_SELECT_MASK
- GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_TA__OVRRD_VALUE_MASK
- GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK
- GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK
- GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK
- GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK
- GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_TD__OVRRD_SELECT_MASK
- GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_TD__OVRRD_VALUE_MASK
- GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK
- GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK
- GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK
- GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK
- GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK
- GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK
- GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK
- GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK
- GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK
- GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK
- GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK
- GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK
- GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT
- GC_CAC_OVRD_WD__OVRRD_SELECT_MASK
- GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT
- GC_CAC_OVRD_WD__OVRRD_VALUE_MASK
- GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT
- GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK
- GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT
- GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK
- GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT
- GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK
- GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT
- GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK
- GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT
- GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK
- GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT
- GC_CAC_SOFT_CTRL__UNUSED_MASK
- GC_CAC_SOFT_CTRL__UNUSED__SHIFT
- GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK
- GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT
- GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK
- GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT
- GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK
- GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT
- GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK
- GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT
- GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK
- GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT
- GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK
- GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT
- GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK
- GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT
- GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK
- GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT
- GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK
- GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT
- GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK
- GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT
- GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK
- GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT
- GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK
- GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT
- GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK
- GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK
- GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT
- GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK
- GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT
- GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK
- GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT
- GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK
- GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT
- GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK
- GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT
- GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK
- GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT
- GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK
- GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT
- GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK
- GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT
- GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK
- GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT
- GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK
- GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT
- GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK
- GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT
- GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK
- GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT
- GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK
- GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT
- GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK
- GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT
- GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK
- GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT
- GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK
- GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT
- GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK
- GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT
- GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK
- GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT
- GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK
- GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT
- GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK
- GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT
- GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK
- GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT
- GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK
- GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT
- GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK
- GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT
- GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK
- GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT
- GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK
- GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT
- GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK
- GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT
- GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK
- GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT
- GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK
- GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT
- GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK
- GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT
- GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK
- GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT
- GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK
- GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT
- GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK
- GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT
- GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK
- GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT
- GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK
- GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT
- GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK
- GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT
- GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK
- GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT
- GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK
- GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT
- GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK
- GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT
- GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK
- GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT
- GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK
- GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT
- GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK
- GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT
- GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK
- GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT
- GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK
- GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT
- GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK
- GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT
- GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK
- GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT
- GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK
- GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT
- GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK
- GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT
- GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK
- GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT
- GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK
- GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT
- GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK
- GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT
- GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK
- GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT
- GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK
- GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT
- GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK
- GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT
- GC_CAC_WEIGHT_PG_0__unused_MASK
- GC_CAC_WEIGHT_PG_0__unused__SHIFT
- GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK
- GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT
- GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK
- GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT
- GC_CAC_WEIGHT_RMI_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_RMI_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_RMI_0__UNUSED_MASK
- GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT
- GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK
- GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT
- GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK
- GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT
- GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK
- GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT
- GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK
- GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT
- GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK
- GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT
- GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK
- GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT
- GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK
- GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT
- GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK
- GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT
- GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK
- GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT
- GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK
- GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT
- GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK
- GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT
- GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK
- GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT
- GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK
- GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT
- GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK
- GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT
- GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK
- GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT
- GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK
- GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT
- GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK
- GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK
- GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT
- GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK
- GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT
- GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK
- GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT
- GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK
- GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT
- GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK
- GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT
- GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK
- GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT
- GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK
- GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT
- GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK
- GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT
- GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK
- GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT
- GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK
- GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK
- GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT
- GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK
- GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT
- GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK
- GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT
- GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK
- GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT
- GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK
- GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT
- GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK
- GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK
- GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT
- GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK
- GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT
- GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK
- GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT
- GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK
- GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT
- GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK
- GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT
- GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK
- GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT
- GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK
- GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT
- GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK
- GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT
- GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK
- GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT
- GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK
- GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT
- GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK
- GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT
- GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK
- GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK
- GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT
- GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK
- GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT
- GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK
- GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT
- GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK
- GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT
- GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK
- GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT
- GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK
- GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT
- GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK
- GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK
- GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT
- GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK
- GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT
- GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK
- GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT
- GC_CAP_CBLA
- GC_CAP_CBM
- GC_CAP_CBOA
- GC_CAP_CMDS
- GC_CAP_CMSS
- GC_CAP_CSC
- GC_CAP_IMG_END
- GC_CAP_IMG_START
- GC_CAP_VCM
- GC_CAP_VCS
- GC_CARMINE_INT_EN
- GC_CB
- GC_CBM_CBST
- GC_CBM_HRV
- GC_CBM_OO
- GC_CCF
- GC_CCF_CGE_100
- GC_CCF_CGE_133
- GC_CCF_CGE_166
- GC_CCF_COT_100
- GC_CCF_COT_133
- GC_CID
- GC_CID_CNAME_MSK
- GC_CID_VERSION_MSK
- GC_CLOCK_100_133
- GC_CLOCK_100_200
- GC_CLOCK_133_200
- GC_CLOCK_133_200_2
- GC_CLOCK_133_266
- GC_CLOCK_133_266_2
- GC_CLOCK_166_250
- GC_CLOCK_166_266
- GC_CLOCK_CONTROL_MASK
- GC_CPM_CEN0
- GC_CPM_CEN1
- GC_CPM_CUTC
- GC_CTRL_CLK_ENABLE
- GC_CTRL_CLK_EN_2D3D
- GC_CTRL_CLK_EN_DISP0
- GC_CTRL_CLK_EN_DISP1
- GC_CTRL_CLK_EN_DRAM
- GC_CTRL_INT_MASK
- GC_CTRL_SOFT_RST
- GC_CTRL_STATUS
- GC_CUOA0
- GC_CUOA1
- GC_CUY0_CUX0
- GC_CUY1_CUX1
- GC_DCM0
- GC_DCM01_CKS
- GC_DCM01_DEN
- GC_DCM01_ESY
- GC_DCM01_L0E
- GC_DCM01_RESV
- GC_DCM01_SC
- GC_DCM1
- GC_DCM1_DEN
- GC_DCM1_L1E
- GC_DCM2
- GC_DCM3
- GC_DCTL_DDRIF2_DDRIF1
- GC_DCTL_INIT_WAIT_CNT
- GC_DCTL_INIT_WAIT_INTERVAL
- GC_DCTL_IOCONT1_IOCONT0
- GC_DCTL_MODE_ADD
- GC_DCTL_REFRESH_SETTIME2
- GC_DCTL_RSV0_STATES
- GC_DCTL_RSV2_RSV1
- GC_DCTL_SETTIME1_EMODE
- GC_DCTL_STATES_MSK
- GC_DDR
- GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK
- GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT
- GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK
- GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT
- GC_DIDT_CTRL0__DIDT_SW_RST_MASK
- GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT
- GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK
- GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT
- GC_DIDT_CTRL0__PHASE_OFFSET_MASK
- GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT
- GC_DIDT_CTRL1__MAX_POWER_MASK
- GC_DIDT_CTRL1__MAX_POWER__SHIFT
- GC_DIDT_CTRL1__MIN_POWER_MASK
- GC_DIDT_CTRL1__MIN_POWER__SHIFT
- GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK
- GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT
- GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK
- GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT
- GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK
- GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT
- GC_DIDT_CTRL2__UNUSED_0_MASK
- GC_DIDT_CTRL2__UNUSED_0__SHIFT
- GC_DIDT_CTRL2__UNUSED_1_MASK
- GC_DIDT_CTRL2__UNUSED_1__SHIFT
- GC_DIDT_CTRL2__UNUSED_2_MASK
- GC_DIDT_CTRL2__UNUSED_2__SHIFT
- GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD_MASK
- GC_DIDT_DROOP_CTRL1__DIDT_DROOP_DELTA_THRESHOLD__SHIFT
- GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN_MASK
- GC_DIDT_DROOP_CTRL1__DIDT_DROOP_LEVEL_RELEASE_EN__SHIFT
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK
- GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT
- GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK
- GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT
- GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK
- GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT
- GC_DIDT_WEIGHT__DB_WEIGHT_MASK
- GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT
- GC_DIDT_WEIGHT__SQ_WEIGHT_MASK
- GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT
- GC_DIDT_WEIGHT__TCP_WEIGHT_MASK
- GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT
- GC_DIDT_WEIGHT__TD_WEIGHT_MASK
- GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT
- GC_DISPLAY_CLOCK_133_MHZ_PNV
- GC_DISPLAY_CLOCK_167_MHZ_PNV
- GC_DISPLAY_CLOCK_190_200_MHZ
- GC_DISPLAY_CLOCK_200_MHZ_PNV
- GC_DISPLAY_CLOCK_267_MHZ_PNV
- GC_DISPLAY_CLOCK_333_320_MHZ
- GC_DISPLAY_CLOCK_333_MHZ_PNV
- GC_DISPLAY_CLOCK_444_MHZ_PNV
- GC_DISPLAY_CLOCK_MASK
- GC_DISP_REFCLK_400
- GC_DISP_REFCLK_533
- GC_DLS
- GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK
- GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT
- GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK
- GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT
- GC_EDC_CTRL__EDC_EN_MASK
- GC_EDC_CTRL__EDC_EN__SHIFT
- GC_EDC_CTRL__EDC_FORCE_STALL_MASK
- GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT
- GC_EDC_CTRL__EDC_LEVEL_SEL_MASK
- GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT
- GC_EDC_CTRL__EDC_SW_RST_MASK
- GC_EDC_CTRL__EDC_SW_RST__SHIFT
- GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK
- GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT
- GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK
- GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT
- GC_EDC_CTRL__GC_EDC_ONLY_MODE_MASK
- GC_EDC_CTRL__GC_EDC_ONLY_MODE__SHIFT
- GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK
- GC_EDC_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT
- GC_EDC_CTRL__RELEASE_STEP_INTERVAL_MASK
- GC_EDC_CTRL__RELEASE_STEP_INTERVAL__SHIFT
- GC_EDC_CTRL__UNUSED_0_MASK
- GC_EDC_CTRL__UNUSED_0__SHIFT
- GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK
- GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT
- GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK
- GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT
- GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK
- GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT
- GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK
- GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT
- GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK
- GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT
- GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK
- GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT
- GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK
- GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT
- GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK
- GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT
- GC_EDC_OVERFLOW__PSM_COUNTER_MASK
- GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT
- GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK
- GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT
- GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK
- GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT
- GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK
- GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT
- GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK
- GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT
- GC_EVB_DCTL_DDRIF2_DDRIF1
- GC_EVB_DCTL_IOCONT1_IOCONT0
- GC_EVB_DCTL_MODE_ADD
- GC_EVB_DCTL_MODE_ADD_AFT_RST
- GC_EVB_DCTL_REFRESH_SETTIME2
- GC_EVB_DCTL_RSV0_STATES
- GC_EVB_DCTL_RSV0_STATES_AFT_RST
- GC_EVB_DCTL_RSV2_RSV1
- GC_EVB_DCTL_SETTIME1_EMODE
- GC_EVICT_RATIO
- GC_FAILURE_ATOMIC
- GC_FAILURE_PIN
- GC_FRM_MGMT_PORT_04
- GC_FRM_MGMT_PORT_M
- GC_FRM_MGMT_PORT_MII
- GC_GREEDY
- GC_HDB_HDP
- GC_HTP
- GC_HWID
- GC_HWIP
- GC_I2C_ADR
- GC_I2C_BCR
- GC_I2C_BSR
- GC_I2C_CCR
- GC_I2C_DAR
- GC_IDLE_CB
- GC_IDLE_GREEDY
- GC_IH_COOKIE_0_PTR__ADDR_MASK
- GC_IH_COOKIE_0_PTR__ADDR__SHIFT
- GC_IMASK
- GC_INT_EN
- GC_IST
- GC_L0DA0
- GC_L0DY_L0DX
- GC_L0EM
- GC_L0EM_L0EC_24
- GC_L0M
- GC_L0M_L0C_16
- GC_L0M_L0C_8
- GC_L0M_L0W_UNIT
- GC_L0OA0
- GC_L0PAL0
- GC_L0WH_L0WW
- GC_L0WY_L0WX
- GC_L1DA
- GC_L1EM
- GC_L1EM_DM
- GC_L1M
- GC_L1M_16
- GC_L1M_CS
- GC_L1M_YC
- GC_L1WH_L1WW
- GC_L1WY_L1WX
- GC_LIMIT_INVERSE
- GC_LOW_FREQUENCY_ENABLE
- GC_MARK_DIRTY
- GC_MARK_METADATA
- GC_MARK_RECLAIMABLE
- GC_MASTER_BUSY
- GC_MAX
- GC_MAX_BUCKETS_DIV
- GC_MAX_DEVICES
- GC_MAX_PORTS
- GC_MAX_SCAN_JIFFIES
- GC_MERGE_NODES
- GC_MIB_AC_EN
- GC_MIB_AC_HDR_EN
- GC_MMR
- GC_MMR_CORALP_EVB_VAL
- GC_MULTI
- GC_MULTI2
- GC_MULTI2_LENGTH
- GC_MULTI_LENGTH
- GC_N64
- GC_N64_CLOCK
- GC_N64_CMD_00
- GC_N64_CMD_01
- GC_N64_CMD_03
- GC_N64_CMD_1b
- GC_N64_CMD_80
- GC_N64_CMD_c0
- GC_N64_DELAY
- GC_N64_DWS
- GC_N64_LENGTH
- GC_N64_OUT
- GC_N64_POWER_R
- GC_N64_POWER_W
- GC_N64_REQUEST_DATA
- GC_N64_STOP_BIT
- GC_N64_STOP_LENGTH
- GC_NES
- GC_NES4
- GC_NES_CLOCK
- GC_NES_DELAY
- GC_NES_LATCH
- GC_NES_LENGTH
- GC_NES_POWER
- GC_NONE
- GC_NORMAL
- GC_NUM
- GC_PFP
- GC_PPP
- GC_PSX
- GC_PSX_ANALOG
- GC_PSX_BYTES
- GC_PSX_CLOCK
- GC_PSX_COMMAND
- GC_PSX_DELAY
- GC_PSX_ID
- GC_PSX_LEN
- GC_PSX_LENGTH
- GC_PSX_MOUSE
- GC_PSX_NEGCON
- GC_PSX_NORMAL
- GC_PSX_POWER
- GC_PSX_RUMBLE
- GC_PSX_SELECT
- GC_REFRESH_TIME
- GC_REGS_OFFS
- GC_RESET_MIB
- GC_REVISION
- GC_RE_REVISION
- GC_RSW
- GC_RX_BPDU_EN
- GC_SECTORS_USED_SIZE
- GC_SLEEP_MS
- GC_SNES
- GC_SNESMOUSE
- GC_SNESMOUSE_LENGTH
- GC_SNES_LENGTH
- GC_SRST
- GC_THREAD
- GC_THREAD_MIN_WB_PAGES
- GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK
- GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT
- GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK
- GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT
- GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK
- GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT
- GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK
- GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT
- GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK
- GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK
- GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT
- GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK
- GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT
- GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK
- GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT
- GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK
- GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT
- GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK
- GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT
- GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK
- GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT
- GC_THROTTLE_CTRL__INST_THROT_DECR_MASK
- GC_THROTTLE_CTRL__INST_THROT_DECR__SHIFT
- GC_THROTTLE_CTRL__INST_THROT_INCR_MASK
- GC_THROTTLE_CTRL__INST_THROT_INCR__SHIFT
- GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK
- GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT
- GC_THROTTLE_CTRL__PATTERN_MODE_MASK
- GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT
- GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX_MASK
- GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MAX__SHIFT
- GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN_MASK
- GC_THROTTLE_CTRL__PCC_FIXED_PATTERN_MIN__SHIFT
- GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK
- GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT
- GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK
- GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT
- GC_THROTTLE_CTRL__PCC_STALL_EN_MASK
- GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT
- GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL_MASK
- GC_THROTTLE_CTRL__PCC_THROT_INCR_STEP_INTERVAL__SHIFT
- GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK
- GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT
- GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK
- GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT
- GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK
- GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT
- GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK
- GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT
- GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK
- GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT
- GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK
- GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT
- GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK
- GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT
- GC_THROTTLE_STATUS__FSM_STATE_MASK
- GC_THROTTLE_STATUS__FSM_STATE__SHIFT
- GC_THROTTLE_STATUS__PATTERN_INDEX_MASK
- GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT
- GC_TIME
- GC_TIME_MSECS
- GC_ULPI_SEL
- GC_URGENT
- GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK
- GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT
- GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK
- GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT
- GC_USER_RB_BACKEND_DISABLE
- GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK
- GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT
- GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK
- GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT
- GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK
- GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT
- GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK
- GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT
- GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK
- GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT
- GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK
- GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT
- GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK
- GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT
- GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK
- GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT
- GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK
- GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT
- GC_USER_SHADER_ARRAY_CONFIG
- GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE_MASK
- GC_USER_SHADER_ARRAY_CONFIG__DPFP_RATE__SHIFT
- GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS_MASK
- GC_USER_SHADER_ARRAY_CONFIG__HALF_LDS__SHIFT
- GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK
- GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT
- GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK
- GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT
- GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE_MASK
- GC_USER_SHADER_ARRAY_CONFIG__SQC_BALANCE_DISABLE__SHIFT
- GC_USER_SHADER_PIPE_CONFIG
- GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK
- GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT
- GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK
- GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT
- GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK
- GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT
- GC_USER_SYS_RB_BACKEND_DISABLE
- GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK
- GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT
- GC_VCM_CM
- GC_VCM_VIE
- GC_VCM_VS_PAL
- GC_VDP_VSP
- GC_VSW_HSW_HSP
- GC_VTR
- GC_WH_WW
- GC_WU_IE
- GC_WU_INT_CLR
- GC_WU_ULPI_EN
- GC_WY_WX
- GD
- GD24_11025
- GD24_16000
- GD24_22050
- GD24_32000
- GD24_44100
- GD24_48000
- GD24_8000
- GD24_88200
- GD24_96000
- GD24_EXT_SYNC
- GD5FXGQ4UEXXG_REG_STATUS2
- GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS
- GD5FXGQ4UXFXXG_STATUS_ECC_MASK
- GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS
- GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR
- GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS
- GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS
- GD82559_1_IRQ
- GD82559_1_PIN
- GD82559_2_IRQ
- GD82559_2_PIN
- GDA
- GDAC_IB_UPALL
- GDA_ADDR
- GDA_MAGIC
- GDA_SIZE
- GDA_VERSION
- GDBELL_BTB_FLUSH
- GDBELL_EXCEPTION_PROLOG
- GDBELL_EXITS
- GDBELL_SET_KSTACK
- GDB_ADJUSTS_BREAK_OFFSET
- GDB_AT
- GDB_AX
- GDB_BA
- GDB_BADADDR
- GDB_BP
- GDB_BREAKINST
- GDB_BREAK_INSN
- GDB_BSTATUS
- GDB_BT
- GDB_BTR
- GDB_BUF_SIZE
- GDB_BX
- GDB_CCR
- GDB_CONFIG
- GDB_CPUID
- GDB_CS
- GDB_CSR
- GDB_CTL6
- GDB_CX
- GDB_CYCLLE
- GDB_DI
- GDB_DS
- GDB_DX
- GDB_EA
- GDB_EAR
- GDB_ECCINJ
- GDB_ER0
- GDB_ER1
- GDB_ER2
- GDB_ER3
- GDB_ER4
- GDB_ER5
- GDB_ER6
- GDB_ES
- GDB_ESR
- GDB_ESTATUS
- GDB_ET
- GDB_EXCEPTION
- GDB_EXR
- GDB_F0
- GDB_F31
- GDB_F32
- GDB_F62
- GDB_FP
- GDB_FPRS
- GDB_FS
- GDB_FSR
- GDB_G0
- GDB_G1
- GDB_G2
- GDB_G3
- GDB_G4
- GDB_G5
- GDB_G6
- GDB_G7
- GDB_GBR
- GDB_GP
- GDB_GS
- GDB_I0
- GDB_I1
- GDB_I2
- GDB_I3
- GDB_I4
- GDB_I5
- GDB_I7
- GDB_IENABLE
- GDB_INST
- GDB_IPENDING
- GDB_L0
- GDB_L1
- GDB_L2
- GDB_L3
- GDB_L4
- GDB_L5
- GDB_L6
- GDB_L7
- GDB_MACH
- GDB_MACL
- GDB_MAX_REGS
- GDB_MPUACC
- GDB_MPUBASE
- GDB_MSR
- GDB_NPC
- GDB_NUMREGBYTES
- GDB_O0
- GDB_O1
- GDB_O2
- GDB_O3
- GDB_O4
- GDB_O5
- GDB_O7
- GDB_ORIG_AX
- GDB_PC
- GDB_PR
- GDB_PS
- GDB_PSR
- GDB_PTEADDR
- GDB_PVR
- GDB_R0
- GDB_R1
- GDB_R10
- GDB_R11
- GDB_R12
- GDB_R13
- GDB_R14
- GDB_R15
- GDB_R16
- GDB_R17
- GDB_R18
- GDB_R19
- GDB_R2
- GDB_R20
- GDB_R21
- GDB_R22
- GDB_R23
- GDB_R3
- GDB_R4
- GDB_R5
- GDB_R6
- GDB_R7
- GDB_R8
- GDB_R9
- GDB_RA
- GDB_REDR
- GDB_REG
- GDB_RPID
- GDB_RTLBHI
- GDB_RTLBLO
- GDB_RTLBSX
- GDB_RTLBX
- GDB_RZPR
- GDB_SI
- GDB_SIZEOF_FLOAT_REG
- GDB_SIZEOF_REG
- GDB_SIZEOF_REG_U32
- GDB_SP
- GDB_SR
- GDB_SS
- GDB_STATE
- GDB_STATUS
- GDB_TBR
- GDB_TICK
- GDB_TLBACC
- GDB_TLBMISC
- GDB_VBR
- GDB_WIM
- GDB_Y
- GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK
- GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT
- GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK
- GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT
- GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK
- GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT
- GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK
- GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT
- GDC0_BIF_ACV_DOORBELL_RANGE__OFFSET_MASK
- GDC0_BIF_ACV_DOORBELL_RANGE__OFFSET__SHIFT
- GDC0_BIF_ACV_DOORBELL_RANGE__SIZE_MASK
- GDC0_BIF_ACV_DOORBELL_RANGE__SIZE__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ACV_ENABLE__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK
- GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT
- GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK
- GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT
- GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK
- GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT
- GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK
- GDC0_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT
- GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK
- GDC0_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT
- GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK
- GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT
- GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK
- GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT
- GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK
- GDC0_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT
- GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK
- GDC0_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT
- GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK
- GDC0_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK
- GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT
- GDC0_NGDC_RESERVED_0__RESERVED_MASK
- GDC0_NGDC_RESERVED_0__RESERVED__SHIFT
- GDC0_NGDC_RESERVED_1__RESERVED_MASK
- GDC0_NGDC_RESERVED_1__RESERVED__SHIFT
- GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK
- GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT
- GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK
- GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT
- GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK
- GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT
- GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK
- GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS_MASK
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_ACV_DIS__SHIFT
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK
- GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT
- GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK
- GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT
- GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK
- GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT
- GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK
- GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT
- GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK
- GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT
- GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK
- GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT
- GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK
- GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT
- GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK
- GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT
- GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK
- GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT
- GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK
- GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT
- GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK
- GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT
- GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK
- GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT
- GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK
- GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT
- GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK
- GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT
- GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK
- GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT
- GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK
- GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT
- GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK
- GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT
- GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK
- GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT
- GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK
- GDC1_GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT
- GDC1_NGDC_RESERVED_0__RESERVED_MASK
- GDC1_NGDC_RESERVED_0__RESERVED__SHIFT
- GDC1_NGDC_RESERVED_1__RESERVED_MASK
- GDC1_NGDC_RESERVED_1__RESERVED__SHIFT
- GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK
- GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT
- GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK
- GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT
- GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK
- GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK
- GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT
- GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK
- GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT
- GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det_MASK
- GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_EgStall_det__SHIFT
- GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det_MASK
- GDCL_RAS_CENTRAL_STATUS__GDCL_C2L_ErrEvent_det__SHIFT
- GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det_MASK
- GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_EgStall_det__SHIFT
- GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det_MASK
- GDCL_RAS_CENTRAL_STATUS__GDCL_L2C_ErrEvent_det__SHIFT
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det_MASK
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det__SHIFT
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det_MASK
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det__SHIFT
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det_MASK
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det__SHIFT
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det_MASK
- GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det__SHIFT
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK
- GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_STALL_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_STALL_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL2__GDCSOC_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK
- GDCSOC_RAS_LEAF2_MISC_CTRL__GDCSOC_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK
- GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN__SHIFT
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN_MASK
- GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET__SHIFT
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET_MASK
- GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET__SHIFT
- GDC_CMD_0_VECTOR
- GDC_CMD_0_VECTOR_BLPO
- GDC_CMD_0_VECTOR_NOEND
- GDC_CMD_0_VECTOR_NOEND_BLPO
- GDC_CMD_1_VECTOR
- GDC_CMD_1_VECTOR_BLPO
- GDC_CMD_1_VECTOR_NOEND
- GDC_CMD_1_VECTOR_NOEND_BLPO
- GDC_CMD_AA_0_VECTOR
- GDC_CMD_AA_0_VECTOR_BLPO
- GDC_CMD_AA_0_VECTOR_NOEND
- GDC_CMD_AA_0_VECTOR_NOEND_BLPO
- GDC_CMD_AA_1_VECTOR
- GDC_CMD_AA_1_VECTOR_BLPO
- GDC_CMD_AA_1_VECTOR_NOEND
- GDC_CMD_AA_1_VECTOR_NOEND_BLPO
- GDC_CMD_AA_X_VECTOR
- GDC_CMD_AA_X_VECTOR_BLPO
- GDC_CMD_AA_X_VECTOR_NOEND
- GDC_CMD_AA_X_VECTOR_NOEND_BLPO
- GDC_CMD_AA_Y_VECTOR
- GDC_CMD_AA_Y_VECTOR_BLPO
- GDC_CMD_AA_Y_VECTOR_NOEND
- GDC_CMD_AA_Y_VECTOR_NOEND_BLPO
- GDC_CMD_BITMAP
- GDC_CMD_BLTCOPY_ALT_ALPHA
- GDC_CMD_BLTCOPY_BOTTOM_LEFT
- GDC_CMD_BLTCOPY_BOTTOM_RIGHT
- GDC_CMD_BLTCOPY_TOP_LEFT
- GDC_CMD_BLTCOPY_TOP_RIGHT
- GDC_CMD_BLT_DRAW
- GDC_CMD_BLT_FILL
- GDC_CMD_BODY_BACK_COLOR
- GDC_CMD_BODY_FORE_COLOR
- GDC_CMD_BORDER_BACK_COLOR
- GDC_CMD_BORDER_FORE_COLOR
- GDC_CMD_CLEAR_POLY_FLAG
- GDC_CMD_DC_LOGOUT
- GDC_CMD_FAST_VECTOR_BLPO_FLAG
- GDC_CMD_FLAG_TRIANGLE_FAN
- GDC_CMD_FLUSH_FB
- GDC_CMD_FLUSH_Z
- GDC_CMD_GMDR1E
- GDC_CMD_GMDR2E
- GDC_CMD_LOAD_TEXTURE
- GDC_CMD_LOAD_TILE
- GDC_CMD_MDR1
- GDC_CMD_MDR1B
- GDC_CMD_MDR1S
- GDC_CMD_MDR2
- GDC_CMD_MDR2S
- GDC_CMD_MDR2TL
- GDC_CMD_NORMAL
- GDC_CMD_OVERLAP_SHADOW_XY
- GDC_CMD_OVERLAP_SHADOW_XY_COMPOSITION
- GDC_CMD_OVERLAP_Z_BORDER
- GDC_CMD_OVERLAP_Z_NON_TOPLEFT
- GDC_CMD_OVERLAP_Z_ORIGIN
- GDC_CMD_OVERLAP_Z_PACKED_ONBS
- GDC_CMD_OVERLAP_Z_SHADOW
- GDC_CMD_PIXEL
- GDC_CMD_PIXEL_Z
- GDC_CMD_POLYGON_BEGIN
- GDC_CMD_POLYGON_END
- GDC_CMD_SHADOW_BACK_COLOR
- GDC_CMD_SHADOW_FORE_COLOR
- GDC_CMD_TRAP_LEFT
- GDC_CMD_TRAP_RIGHT
- GDC_CMD_TRIANGLE_FAN
- GDC_CMD_VECTOR_BLPO_FLAG
- GDC_CMD_X_VECTOR
- GDC_CMD_X_VECTOR_BLPO
- GDC_CMD_X_VECTOR_NOEND
- GDC_CMD_X_VECTOR_NOEND_BLPO
- GDC_CMD_Y_VECTOR
- GDC_CMD_Y_VECTOR_BLPO
- GDC_CMD_Y_VECTOR_NOEND
- GDC_CMD_Y_VECTOR_NOEND_BLPO
- GDC_GEO_REG_INPUT_FIFO
- GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET_MASK
- GDC_PG_MISC_CNTL__GDC_PG_RESET_SELECT_COLD_RESET__SHIFT
- GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF0_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF1_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF2_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF3_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF4_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK
- GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK
- GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK
- GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT
- GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK
- GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK
- GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT
- GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN_MASK
- GDC_RAS_LEAF5_CTRL__LOCAL_ERR_REPORT_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK
- GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK
- GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK
- GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK
- GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK
- GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK
- GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT
- GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK
- GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK
- GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK
- GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK
- GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK
- GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK
- GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT
- GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK
- GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK
- GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT
- GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK
- GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK
- GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT
- GDC_REG_ALPHA
- GDC_REG_ALPHA_MAP_BASE
- GDC_REG_BACKGROUND_COLOR
- GDC_REG_CLIP_XMAX
- GDC_REG_CLIP_XMIN
- GDC_REG_CLIP_YMAX
- GDC_REG_CLIP_YMIN
- GDC_REG_CTRL
- GDC_REG_DDA_STATUS
- GDC_REG_DRAW_BASE
- GDC_REG_ENGINE_STATUS
- GDC_REG_ERROR_STATUS
- GDC_REG_FIFO_COUNT
- GDC_REG_FIFO_STATUS
- GDC_REG_FOREGROUND_COLOR
- GDC_REG_LINE_PATTERN
- GDC_REG_LINE_PATTERN_OFFSET
- GDC_REG_MODE_BITMAP
- GDC_REG_MODE_EXTENSION
- GDC_REG_MODE_LINE
- GDC_REG_MODE_MISC
- GDC_REG_MODE_POLYGON
- GDC_REG_MODE_TEXTURE
- GDC_REG_POLYGON_FLAG_BASE
- GDC_REG_SETUP_STATUS
- GDC_REG_TEXTURE_BASE
- GDC_REG_TEXURE_SIZE
- GDC_REG_TEX_BORDER_COLOR
- GDC_REG_TEX_BUF_OFFSET
- GDC_REG_TILE_SIZE
- GDC_REG_X_RESOLUTION
- GDC_REG_Z_BASE
- GDC_ROP_AND
- GDC_ROP_AND_INVERTED
- GDC_ROP_AND_REVERSE
- GDC_ROP_CLEAR
- GDC_ROP_COPY
- GDC_ROP_COPY_INVERTED
- GDC_ROP_EQUIV
- GDC_ROP_INVERT
- GDC_ROP_NAND
- GDC_ROP_NOP
- GDC_ROP_NOR
- GDC_ROP_OR
- GDC_ROP_OR_INVERTED
- GDC_ROP_OR_REVERSE
- GDC_ROP_SET
- GDC_ROP_XOR
- GDC_TYPE_BLTCOPYALTALPHABLENDP
- GDC_TYPE_BLTCOPYALTERNATEP
- GDC_TYPE_BLTCOPYP
- GDC_TYPE_BLTTEXTUREP
- GDC_TYPE_DC_LOGOUTADDR
- GDC_TYPE_DRAW
- GDC_TYPE_DRAWBITMAPP
- GDC_TYPE_DRAWLINE
- GDC_TYPE_DRAWLINE2I
- GDC_TYPE_DRAWLINE2IP
- GDC_TYPE_DRAWPIXEL
- GDC_TYPE_DRAWPIXELZ
- GDC_TYPE_DRAWRECTP
- GDC_TYPE_DRAWTRAP
- GDC_TYPE_DRAWVERTEX2I
- GDC_TYPE_DRAWVERTEX2IP
- GDC_TYPE_G_BEGIN
- GDC_TYPE_G_BEGINCONT
- GDC_TYPE_G_BEGINCONTE
- GDC_TYPE_G_BEGINE
- GDC_TYPE_G_DEPTHRANGE
- GDC_TYPE_G_END
- GDC_TYPE_G_ENDE
- GDC_TYPE_G_INIT
- GDC_TYPE_G_LOADMATRIX
- GDC_TYPE_G_NOP
- GDC_TYPE_G_VERTEX
- GDC_TYPE_G_VERTEXLOG
- GDC_TYPE_G_VERTEXNOPLOG
- GDC_TYPE_G_VIEWPORT
- GDC_TYPE_G_VIEWVOLUMEWCLIP
- GDC_TYPE_G_VIEWVOLUMEXYCLIP
- GDC_TYPE_G_VIEWVOLUMEZCLIP
- GDC_TYPE_INTERRUPT
- GDC_TYPE_LOADTEXTUREP
- GDC_TYPE_NOP
- GDC_TYPE_OVERLAPXYOFFT
- GDC_TYPE_OVERLAPZOFFT
- GDC_TYPE_SETCOLORREGISTER
- GDC_TYPE_SETGMODEREGISTER
- GDC_TYPE_SETLVERTEX2I
- GDC_TYPE_SETLVERTEX2IP
- GDC_TYPE_SETMODEREGISTER
- GDC_TYPE_SETREGISTER
- GDC_TYPE_SETVERTEX2I
- GDC_TYPE_SETVERTEX2IP
- GDC_TYPE_SYNC
- GDD_BAR
- GDD_DEV
- GDD_DTY
- GDD_GRP
- GDD_INS
- GDD_IRQ
- GDD_REV
- GDD_VAR
- GDFIFOCFG
- GDFIFOCFG_EPINFOBASE_MASK
- GDFIFOCFG_EPINFOBASE_SHIFT
- GDFIFOCFG_GDFIFOCFG_MASK
- GDFIFOCFG_GDFIFOCFG_SHIFT
- GDI_LINEAR_FRAME_MAP
- GDI_TILED_FRAME_MB_RASTER_MAP
- GDLM_ATTR
- GDLM_LVB_SIZE
- GDLM_STRNAME_BYTES
- GDMA_REF
- GDMA_REG_ACKSTS
- GDMA_REG_CTRL0
- GDMA_REG_CTRL0_BURST_MASK
- GDMA_REG_CTRL0_BURST_SHIFT
- GDMA_REG_CTRL0_CURR_MASK
- GDMA_REG_CTRL0_CURR_SHIFT
- GDMA_REG_CTRL0_DONE_INT
- GDMA_REG_CTRL0_DST_ADDR_FIXED
- GDMA_REG_CTRL0_ENABLE
- GDMA_REG_CTRL0_SRC_ADDR_FIXED
- GDMA_REG_CTRL0_SW_MODE
- GDMA_REG_CTRL0_TX_MASK
- GDMA_REG_CTRL0_TX_SHIFT
- GDMA_REG_CTRL1
- GDMA_REG_CTRL1_COHERENT
- GDMA_REG_CTRL1_DST_REQ_SHIFT
- GDMA_REG_CTRL1_FAIL
- GDMA_REG_CTRL1_MASK
- GDMA_REG_CTRL1_NEXT_MASK
- GDMA_REG_CTRL1_NEXT_SHIFT
- GDMA_REG_CTRL1_REQ_MASK
- GDMA_REG_CTRL1_SEG_MASK
- GDMA_REG_CTRL1_SEG_SHIFT
- GDMA_REG_CTRL1_SRC_REQ_SHIFT
- GDMA_REG_DONE_INT
- GDMA_REG_DST_ADDR
- GDMA_REG_FINSTS
- GDMA_REG_GCT
- GDMA_REG_GCT_ARBIT_RR
- GDMA_REG_GCT_CHAN_MASK
- GDMA_REG_GCT_CHAN_SHIFT
- GDMA_REG_GCT_VER_MASK
- GDMA_REG_GCT_VER_SHIFT
- GDMA_REG_PERF_END
- GDMA_REG_PERF_START
- GDMA_REG_REQSTS
- GDMA_REG_SRC_ADDR
- GDMA_REG_UNMASK_INT
- GDMA_RT305X_CTRL0_DST_REQ_SHIFT
- GDMA_RT305X_CTRL0_REQ_MASK
- GDMA_RT305X_CTRL0_SRC_REQ_SHIFT
- GDMA_RT305X_CTRL1_FAIL
- GDMA_RT305X_CTRL1_NEXT_MASK
- GDMA_RT305X_CTRL1_NEXT_SHIFT
- GDMA_RT305X_GCT
- GDMA_RT305X_STATUS_INT
- GDMA_RT305X_STATUS_SIGNAL
- GDMA_TRANSFER_SIZE_16BYTE
- GDMA_TRANSFER_SIZE_32BYTE
- GDMA_TRANSFER_SIZE_4BYTE
- GDMA_TRANSFER_SIZE_64BYTE
- GDMA_TRANSFER_SIZE_8BYTE
- GDM_TTY_MAJOR
- GDM_TTY_MINOR
- GDM_TTY_READY
- GDP2STR
- GDP_ABGR8888
- GDP_ARGB1555
- GDP_ARGB4444
- GDP_ARGB8565
- GDP_ARGB8888
- GDP_NODE_NB_BANK
- GDP_NODE_PER_FIELD
- GDP_RGB565
- GDP_RGB888
- GDP_RGB888_32
- GDP_XBGR8888
- GDRCTRL
- GDRCTRL_COLKEYM
- GDRCTRL_LNDBL
- GDRCTRL_LNHLV
- GDRCTRL_PIXDBL
- GDRCTRL_PIXHLV
- GDROM_ALTSTATUS_REG
- GDROM_BASE_REG
- GDROM_BCH_REG
- GDROM_BCL_REG
- GDROM_COM_EXECDIAG
- GDROM_COM_IDDEV
- GDROM_COM_PACKET
- GDROM_COM_SOFTRESET
- GDROM_DATA_REG
- GDROM_DEFAULT_TIMEOUT
- GDROM_DEV_NAME
- GDROM_DMA_ACCESS_CTRL_REG
- GDROM_DMA_DIRECTION_REG
- GDROM_DMA_ENABLE_REG
- GDROM_DMA_LENGTH_REG
- GDROM_DMA_STARTADDR_REG
- GDROM_DMA_STATUS_REG
- GDROM_DMA_WAIT_REG
- GDROM_DSEL_REG
- GDROM_ERROR_REG
- GDROM_HARD_SECTOR
- GDROM_INTSEC_REG
- GDROM_RESET_REG
- GDROM_SECNUM_REG
- GDROM_STATUSCOMMAND_REG
- GDSC_OFF
- GDSC_ON
- GDSC_POWER_DOWN_COMPLETE
- GDSC_POWER_UP_COMPLETE
- GDS_ADDR_BASE
- GDS_APPEND_COUNT_0
- GDS_APPEND_COUNT_1
- GDS_APPEND_COUNT_10
- GDS_APPEND_COUNT_11
- GDS_APPEND_COUNT_2
- GDS_APPEND_COUNT_3
- GDS_APPEND_COUNT_4
- GDS_APPEND_COUNT_5
- GDS_APPEND_COUNT_6
- GDS_APPEND_COUNT_7
- GDS_APPEND_COUNT_8
- GDS_APPEND_COUNT_9
- GDS_ATOM_BASE__BASE_MASK
- GDS_ATOM_BASE__BASE__SHIFT
- GDS_ATOM_BASE__UNUSED_MASK
- GDS_ATOM_BASE__UNUSED__SHIFT
- GDS_ATOM_CNTL__AINC_MASK
- GDS_ATOM_CNTL__AINC__SHIFT
- GDS_ATOM_CNTL__DMODE_MASK
- GDS_ATOM_CNTL__DMODE__SHIFT
- GDS_ATOM_CNTL__UNUSED1_MASK
- GDS_ATOM_CNTL__UNUSED1__SHIFT
- GDS_ATOM_CNTL__UNUSED2_MASK
- GDS_ATOM_CNTL__UNUSED2__SHIFT
- GDS_ATOM_COMPLETE__COMPLETE_MASK
- GDS_ATOM_COMPLETE__COMPLETE__SHIFT
- GDS_ATOM_COMPLETE__UNUSED_MASK
- GDS_ATOM_COMPLETE__UNUSED__SHIFT
- GDS_ATOM_DST__DST_MASK
- GDS_ATOM_DST__DST__SHIFT
- GDS_ATOM_OFFSET0__OFFSET0_MASK
- GDS_ATOM_OFFSET0__OFFSET0__SHIFT
- GDS_ATOM_OFFSET0__UNUSED_MASK
- GDS_ATOM_OFFSET0__UNUSED__SHIFT
- GDS_ATOM_OFFSET1__OFFSET1_MASK
- GDS_ATOM_OFFSET1__OFFSET1__SHIFT
- GDS_ATOM_OFFSET1__UNUSED_MASK
- GDS_ATOM_OFFSET1__UNUSED__SHIFT
- GDS_ATOM_OP__OP_MASK
- GDS_ATOM_OP__OP__SHIFT
- GDS_ATOM_OP__UNUSED_MASK
- GDS_ATOM_OP__UNUSED__SHIFT
- GDS_ATOM_READ0_U__DATA_MASK
- GDS_ATOM_READ0_U__DATA__SHIFT
- GDS_ATOM_READ0__DATA_MASK
- GDS_ATOM_READ0__DATA__SHIFT
- GDS_ATOM_READ1_U__DATA_MASK
- GDS_ATOM_READ1_U__DATA__SHIFT
- GDS_ATOM_READ1__DATA_MASK
- GDS_ATOM_READ1__DATA__SHIFT
- GDS_ATOM_SIZE__SIZE_MASK
- GDS_ATOM_SIZE__SIZE__SHIFT
- GDS_ATOM_SIZE__UNUSED_MASK
- GDS_ATOM_SIZE__UNUSED__SHIFT
- GDS_ATOM_SRC0_U__DATA_MASK
- GDS_ATOM_SRC0_U__DATA__SHIFT
- GDS_ATOM_SRC0__DATA_MASK
- GDS_ATOM_SRC0__DATA__SHIFT
- GDS_ATOM_SRC1_U__DATA_MASK
- GDS_ATOM_SRC1_U__DATA__SHIFT
- GDS_ATOM_SRC1__DATA_MASK
- GDS_ATOM_SRC1__DATA__SHIFT
- GDS_BUSY
- GDS_CNTL_STATUS__CREDIT_BUSY0_MASK
- GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT
- GDS_CNTL_STATUS__CREDIT_BUSY1_MASK
- GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT
- GDS_CNTL_STATUS__CREDIT_BUSY2_MASK
- GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT
- GDS_CNTL_STATUS__CREDIT_BUSY3_MASK
- GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT
- GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK
- GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT
- GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK
- GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT
- GDS_CNTL_STATUS__DS_BUSY_MASK
- GDS_CNTL_STATUS__DS_BUSY__SHIFT
- GDS_CNTL_STATUS__DS_RD_CLAMP_MASK
- GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT
- GDS_CNTL_STATUS__DS_WR_CLAMP_MASK
- GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT
- GDS_CNTL_STATUS__GDS_BUSY_MASK
- GDS_CNTL_STATUS__GDS_BUSY__SHIFT
- GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK
- GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT
- GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK
- GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT
- GDS_CNTL_STATUS__GWS_BUSY_MASK
- GDS_CNTL_STATUS__GWS_BUSY__SHIFT
- GDS_CNTL_STATUS__ORD_APP_BUSY_MASK
- GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT
- GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK
- GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT
- GDS_CNTL_STATUS__UNUSED_MASK
- GDS_CNTL_STATUS__UNUSED__SHIFT
- GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK
- GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT
- GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK
- GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT
- GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK
- GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT
- GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK
- GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT
- GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK
- GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT
- GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK
- GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT
- GDS_CONFIG__UNUSED_MASK
- GDS_CONFIG__UNUSED__SHIFT
- GDS_CS_CTXSW_CNT0__PTR_MASK
- GDS_CS_CTXSW_CNT0__PTR__SHIFT
- GDS_CS_CTXSW_CNT0__UPDN_MASK
- GDS_CS_CTXSW_CNT0__UPDN__SHIFT
- GDS_CS_CTXSW_CNT1__PTR_MASK
- GDS_CS_CTXSW_CNT1__PTR__SHIFT
- GDS_CS_CTXSW_CNT1__UPDN_MASK
- GDS_CS_CTXSW_CNT1__UPDN__SHIFT
- GDS_CS_CTXSW_CNT2__PTR_MASK
- GDS_CS_CTXSW_CNT2__PTR__SHIFT
- GDS_CS_CTXSW_CNT2__UPDN_MASK
- GDS_CS_CTXSW_CNT2__UPDN__SHIFT
- GDS_CS_CTXSW_CNT3__PTR_MASK
- GDS_CS_CTXSW_CNT3__PTR__SHIFT
- GDS_CS_CTXSW_CNT3__UPDN_MASK
- GDS_CS_CTXSW_CNT3__UPDN__SHIFT
- GDS_CS_CTXSW_STATUS__R_MASK
- GDS_CS_CTXSW_STATUS__R__SHIFT
- GDS_CS_CTXSW_STATUS__UNUSED_MASK
- GDS_CS_CTXSW_STATUS__UNUSED__SHIFT
- GDS_CS_CTXSW_STATUS__W_MASK
- GDS_CS_CTXSW_STATUS__W__SHIFT
- GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK
- GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT
- GDS_DEBUG_CNTL__UNUSED_MASK
- GDS_DEBUG_CNTL__UNUSED__SHIFT
- GDS_DEBUG_DATA__DATA_MASK
- GDS_DEBUG_DATA__DATA__SHIFT
- GDS_DEBUG_REG0__buff_write_MASK
- GDS_DEBUG_REG0__buff_write__SHIFT
- GDS_DEBUG_REG0__cstate_MASK
- GDS_DEBUG_REG0__cstate__SHIFT
- GDS_DEBUG_REG0__flush_request_MASK
- GDS_DEBUG_REG0__flush_request__SHIFT
- GDS_DEBUG_REG0__last_pixel_ptr_MASK
- GDS_DEBUG_REG0__last_pixel_ptr__SHIFT
- GDS_DEBUG_REG0__spare1_MASK
- GDS_DEBUG_REG0__spare1__SHIFT
- GDS_DEBUG_REG0__spare_MASK
- GDS_DEBUG_REG0__spare__SHIFT
- GDS_DEBUG_REG0__wbuf_fifo_empty_MASK
- GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT
- GDS_DEBUG_REG0__wbuf_fifo_full_MASK
- GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT
- GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK
- GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT
- GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK
- GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT
- GDS_DEBUG_REG0__write_buff_valid_MASK
- GDS_DEBUG_REG0__write_buff_valid__SHIFT
- GDS_DEBUG_REG1__addr_fifo_empty_MASK
- GDS_DEBUG_REG1__addr_fifo_empty__SHIFT
- GDS_DEBUG_REG1__addr_fifo_full_MASK
- GDS_DEBUG_REG1__addr_fifo_full__SHIFT
- GDS_DEBUG_REG1__awaiting_data_MASK
- GDS_DEBUG_REG1__awaiting_data__SHIFT
- GDS_DEBUG_REG1__buffer_invalid_MASK
- GDS_DEBUG_REG1__buffer_invalid__SHIFT
- GDS_DEBUG_REG1__buffer_loaded_MASK
- GDS_DEBUG_REG1__buffer_loaded__SHIFT
- GDS_DEBUG_REG1__data_ready_MASK
- GDS_DEBUG_REG1__data_ready__SHIFT
- GDS_DEBUG_REG1__pixel_addr_MASK
- GDS_DEBUG_REG1__pixel_addr__SHIFT
- GDS_DEBUG_REG1__pixel_vld_MASK
- GDS_DEBUG_REG1__pixel_vld__SHIFT
- GDS_DEBUG_REG1__spare_MASK
- GDS_DEBUG_REG1__spare__SHIFT
- GDS_DEBUG_REG1__tag_hit_MASK
- GDS_DEBUG_REG1__tag_hit__SHIFT
- GDS_DEBUG_REG1__tag_miss_MASK
- GDS_DEBUG_REG1__tag_miss__SHIFT
- GDS_DEBUG_REG2__app_sel_MASK
- GDS_DEBUG_REG2__app_sel__SHIFT
- GDS_DEBUG_REG2__cmd_write_MASK
- GDS_DEBUG_REG2__cmd_write__SHIFT
- GDS_DEBUG_REG2__ds_credit_avail_MASK
- GDS_DEBUG_REG2__ds_credit_avail__SHIFT
- GDS_DEBUG_REG2__ds_full_MASK
- GDS_DEBUG_REG2__ds_full__SHIFT
- GDS_DEBUG_REG2__ord_idx_free_MASK
- GDS_DEBUG_REG2__ord_idx_free__SHIFT
- GDS_DEBUG_REG2__req_MASK
- GDS_DEBUG_REG2__req__SHIFT
- GDS_DEBUG_REG2__spare_MASK
- GDS_DEBUG_REG2__spare__SHIFT
- GDS_DEBUG_REG3__pipe0_busy_num_MASK
- GDS_DEBUG_REG3__pipe0_busy_num__SHIFT
- GDS_DEBUG_REG3__pipe_num_busy_MASK
- GDS_DEBUG_REG3__pipe_num_busy__SHIFT
- GDS_DEBUG_REG3__spare_MASK
- GDS_DEBUG_REG3__spare__SHIFT
- GDS_DEBUG_REG4__cmd_write_MASK
- GDS_DEBUG_REG4__cmd_write__SHIFT
- GDS_DEBUG_REG4__credit_cnt_gt0_MASK
- GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT
- GDS_DEBUG_REG4__cur_reso_MASK
- GDS_DEBUG_REG4__cur_reso__SHIFT
- GDS_DEBUG_REG4__cur_reso_barrier_MASK
- GDS_DEBUG_REG4__cur_reso_barrier__SHIFT
- GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK
- GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT
- GDS_DEBUG_REG4__cur_reso_fed_MASK
- GDS_DEBUG_REG4__cur_reso_fed__SHIFT
- GDS_DEBUG_REG4__cur_reso_flag_MASK
- GDS_DEBUG_REG4__cur_reso_flag__SHIFT
- GDS_DEBUG_REG4__cur_reso_head_dirty_MASK
- GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT
- GDS_DEBUG_REG4__cur_reso_head_flag_MASK
- GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT
- GDS_DEBUG_REG4__cur_reso_head_valid_MASK
- GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT
- GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK
- GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT
- GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK
- GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT
- GDS_DEBUG_REG4__gws_bulkfree_MASK
- GDS_DEBUG_REG4__gws_bulkfree__SHIFT
- GDS_DEBUG_REG4__gws_busy_MASK
- GDS_DEBUG_REG4__gws_busy__SHIFT
- GDS_DEBUG_REG4__gws_out_stall_MASK
- GDS_DEBUG_REG4__gws_out_stall__SHIFT
- GDS_DEBUG_REG4__gws_req_MASK
- GDS_DEBUG_REG4__gws_req__SHIFT
- GDS_DEBUG_REG4__ram_gws_re_MASK
- GDS_DEBUG_REG4__ram_gws_re__SHIFT
- GDS_DEBUG_REG4__ram_gws_we_MASK
- GDS_DEBUG_REG4__ram_gws_we__SHIFT
- GDS_DEBUG_REG4__ram_read_busy_MASK
- GDS_DEBUG_REG4__ram_read_busy__SHIFT
- GDS_DEBUG_REG4__spare_MASK
- GDS_DEBUG_REG4__spare__SHIFT
- GDS_DEBUG_REG5__alloc_opco_error_MASK
- GDS_DEBUG_REG5__alloc_opco_error__SHIFT
- GDS_DEBUG_REG5__dealloc_opco_error_MASK
- GDS_DEBUG_REG5__dealloc_opco_error__SHIFT
- GDS_DEBUG_REG5__dec_error_MASK
- GDS_DEBUG_REG5__dec_error__SHIFT
- GDS_DEBUG_REG5__error_ds_address_MASK
- GDS_DEBUG_REG5__error_ds_address__SHIFT
- GDS_DEBUG_REG5__spare1_MASK
- GDS_DEBUG_REG5__spare1__SHIFT
- GDS_DEBUG_REG5__spare_MASK
- GDS_DEBUG_REG5__spare__SHIFT
- GDS_DEBUG_REG5__wrap_opco_error_MASK
- GDS_DEBUG_REG5__wrap_opco_error__SHIFT
- GDS_DEBUG_REG5__write_dis_MASK
- GDS_DEBUG_REG5__write_dis__SHIFT
- GDS_DEBUG_REG6__counters_busy_MASK
- GDS_DEBUG_REG6__counters_busy__SHIFT
- GDS_DEBUG_REG6__counters_enabled_MASK
- GDS_DEBUG_REG6__counters_enabled__SHIFT
- GDS_DEBUG_REG6__oa_busy_MASK
- GDS_DEBUG_REG6__oa_busy__SHIFT
- GDS_DEBUG_REG6__spare_MASK
- GDS_DEBUG_REG6__spare__SHIFT
- GDS_DMA_RQ_PENDING
- GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK
- GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT
- GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK
- GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT
- GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK
- GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT
- GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK
- GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT
- GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK
- GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT
- GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK
- GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT
- GDS_DSM_CNTL2__UNUSED_MASK
- GDS_DSM_CNTL2__UNUSED__SHIFT
- GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK
- GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT
- GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK
- GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT
- GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK
- GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT
- GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK
- GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT
- GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK
- GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT
- GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK
- GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT
- GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK
- GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT
- GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK
- GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT
- GDS_DSM_CNTL__UNUSED_MASK
- GDS_DSM_CNTL__UNUSED__SHIFT
- GDS_EDC_CNT__DED_MASK
- GDS_EDC_CNT__DED__SHIFT
- GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK
- GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT
- GDS_EDC_CNT__GDS_MEM_DED_MASK
- GDS_EDC_CNT__GDS_MEM_DED__SHIFT
- GDS_EDC_CNT__GDS_MEM_SEC_MASK
- GDS_EDC_CNT__GDS_MEM_SEC__SHIFT
- GDS_EDC_CNT__SEC_MASK
- GDS_EDC_CNT__SEC__SHIFT
- GDS_EDC_CNT__SED_MASK
- GDS_EDC_CNT__SED__SHIFT
- GDS_EDC_CNT__UNUSED_MASK
- GDS_EDC_CNT__UNUSED__SHIFT
- GDS_EDC_GRBM_CNT__DED_MASK
- GDS_EDC_GRBM_CNT__DED__SHIFT
- GDS_EDC_GRBM_CNT__SEC_MASK
- GDS_EDC_GRBM_CNT__SEC__SHIFT
- GDS_EDC_GRBM_CNT__UNUSED_MASK
- GDS_EDC_GRBM_CNT__UNUSED__SHIFT
- GDS_EDC_OA_DED__ME0_CS_DED_MASK
- GDS_EDC_OA_DED__ME0_CS_DED__SHIFT
- GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK
- GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT
- GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK
- GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT
- GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK
- GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT
- GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK
- GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT
- GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK
- GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT
- GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK
- GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT
- GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK
- GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT
- GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK
- GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT
- GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK
- GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT
- GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK
- GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT
- GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK
- GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT
- GDS_EDC_OA_DED__UNUSED0_MASK
- GDS_EDC_OA_DED__UNUSED0__SHIFT
- GDS_EDC_OA_DED__UNUSED1_MASK
- GDS_EDC_OA_DED__UNUSED1__SHIFT
- GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK
- GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT
- GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK
- GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT
- GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK
- GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT
- GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK
- GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT
- GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK
- GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT
- GDS_EDC_OA_PHY_CNT__UNUSED1_MASK
- GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK
- GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT
- GDS_EDC_OA_PIPE_CNT__UNUSED_MASK
- GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT
- GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK
- GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT
- GDS_ENHANCE2__GDSA_PC_CGTS_DIS_MASK
- GDS_ENHANCE2__GDSA_PC_CGTS_DIS__SHIFT
- GDS_ENHANCE2__GDSO_PC_CGTS_DIS_MASK
- GDS_ENHANCE2__GDSO_PC_CGTS_DIS__SHIFT
- GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK
- GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT
- GDS_ENHANCE2__MISC_MASK
- GDS_ENHANCE2__MISC__SHIFT
- GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK
- GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT
- GDS_ENHANCE2__UNUSED_MASK
- GDS_ENHANCE2__UNUSED__SHIFT
- GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE_MASK
- GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE__SHIFT
- GDS_ENHANCE__AUTO_INC_INDEX_MASK
- GDS_ENHANCE__AUTO_INC_INDEX__SHIFT
- GDS_ENHANCE__CGPG_RESTORE_MASK
- GDS_ENHANCE__CGPG_RESTORE__SHIFT
- GDS_ENHANCE__DS_MEM_CLK_GATE_DIS_MASK
- GDS_ENHANCE__DS_MEM_CLK_GATE_DIS__SHIFT
- GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK
- GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT
- GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK
- GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT
- GDS_ENHANCE__GDS_CLK_ENHANCE_DIS_MASK
- GDS_ENHANCE__GDS_CLK_ENHANCE_DIS__SHIFT
- GDS_ENHANCE__MISC_MASK
- GDS_ENHANCE__MISC__SHIFT
- GDS_ENHANCE__RD_BUF_TAG_MISS_MASK
- GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT
- GDS_ENHANCE__UNUSED_MASK
- GDS_ENHANCE__UNUSED__SHIFT
- GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK
- GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT
- GDS_GFX_CTXSW_STATUS__R_MASK
- GDS_GFX_CTXSW_STATUS__R__SHIFT
- GDS_GFX_CTXSW_STATUS__UNUSED_MASK
- GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT
- GDS_GFX_CTXSW_STATUS__W_MASK
- GDS_GFX_CTXSW_STATUS__W__SHIFT
- GDS_GRBM_SECDED_CNT__DED_MASK
- GDS_GRBM_SECDED_CNT__DED__SHIFT
- GDS_GRBM_SECDED_CNT__SEC_MASK
- GDS_GRBM_SECDED_CNT__SEC__SHIFT
- GDS_GS_CTXSW_CNT0__PTR_MASK
- GDS_GS_CTXSW_CNT0__PTR__SHIFT
- GDS_GS_CTXSW_CNT0__UPDN_MASK
- GDS_GS_CTXSW_CNT0__UPDN__SHIFT
- GDS_GS_CTXSW_CNT1__PTR_MASK
- GDS_GS_CTXSW_CNT1__PTR__SHIFT
- GDS_GS_CTXSW_CNT1__UPDN_MASK
- GDS_GS_CTXSW_CNT1__UPDN__SHIFT
- GDS_GS_CTXSW_CNT2__PTR_MASK
- GDS_GS_CTXSW_CNT2__PTR__SHIFT
- GDS_GS_CTXSW_CNT2__UPDN_MASK
- GDS_GS_CTXSW_CNT2__UPDN__SHIFT
- GDS_GS_CTXSW_CNT3__PTR_MASK
- GDS_GS_CTXSW_CNT3__PTR__SHIFT
- GDS_GS_CTXSW_CNT3__UPDN_MASK
- GDS_GS_CTXSW_CNT3__UPDN__SHIFT
- GDS_GWS_RESET0__RESOURCE0_RESET_MASK
- GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE10_RESET_MASK
- GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE11_RESET_MASK
- GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE12_RESET_MASK
- GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE13_RESET_MASK
- GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE14_RESET_MASK
- GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE15_RESET_MASK
- GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE16_RESET_MASK
- GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE17_RESET_MASK
- GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE18_RESET_MASK
- GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE19_RESET_MASK
- GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE1_RESET_MASK
- GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE20_RESET_MASK
- GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE21_RESET_MASK
- GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE22_RESET_MASK
- GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE23_RESET_MASK
- GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE24_RESET_MASK
- GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE25_RESET_MASK
- GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE26_RESET_MASK
- GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE27_RESET_MASK
- GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE28_RESET_MASK
- GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE29_RESET_MASK
- GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE2_RESET_MASK
- GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE30_RESET_MASK
- GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE31_RESET_MASK
- GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE3_RESET_MASK
- GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE4_RESET_MASK
- GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE5_RESET_MASK
- GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE6_RESET_MASK
- GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE7_RESET_MASK
- GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE8_RESET_MASK
- GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT
- GDS_GWS_RESET0__RESOURCE9_RESET_MASK
- GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE32_RESET_MASK
- GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE33_RESET_MASK
- GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE34_RESET_MASK
- GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE35_RESET_MASK
- GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE36_RESET_MASK
- GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE37_RESET_MASK
- GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE38_RESET_MASK
- GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE39_RESET_MASK
- GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE40_RESET_MASK
- GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE41_RESET_MASK
- GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE42_RESET_MASK
- GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE43_RESET_MASK
- GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE44_RESET_MASK
- GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE45_RESET_MASK
- GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE46_RESET_MASK
- GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE47_RESET_MASK
- GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE48_RESET_MASK
- GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE49_RESET_MASK
- GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE50_RESET_MASK
- GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE51_RESET_MASK
- GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE52_RESET_MASK
- GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE53_RESET_MASK
- GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE54_RESET_MASK
- GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE55_RESET_MASK
- GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE56_RESET_MASK
- GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE57_RESET_MASK
- GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE58_RESET_MASK
- GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE59_RESET_MASK
- GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE60_RESET_MASK
- GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE61_RESET_MASK
- GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE62_RESET_MASK
- GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT
- GDS_GWS_RESET1__RESOURCE63_RESET_MASK
- GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT
- GDS_GWS_RESOURCE_CNTL__INDEX_MASK
- GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT
- GDS_GWS_RESOURCE_CNTL__UNUSED_MASK
- GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT
- GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK
- GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT
- GDS_GWS_RESOURCE_CNT__UNUSED_MASK
- GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT
- GDS_GWS_RESOURCE_RESET__RESET_MASK
- GDS_GWS_RESOURCE_RESET__RESET__SHIFT
- GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK
- GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT
- GDS_GWS_RESOURCE_RESET__UNUSED_MASK
- GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT
- GDS_GWS_RESOURCE__COUNTER_MASK
- GDS_GWS_RESOURCE__COUNTER__SHIFT
- GDS_GWS_RESOURCE__DED_MASK
- GDS_GWS_RESOURCE__DED__SHIFT
- GDS_GWS_RESOURCE__FLAG_MASK
- GDS_GWS_RESOURCE__FLAG__SHIFT
- GDS_GWS_RESOURCE__HALTED_MASK
- GDS_GWS_RESOURCE__HALTED__SHIFT
- GDS_GWS_RESOURCE__HEAD_FLAG_MASK
- GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT
- GDS_GWS_RESOURCE__HEAD_QUEUE_MASK
- GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT
- GDS_GWS_RESOURCE__HEAD_VALID_MASK
- GDS_GWS_RESOURCE__HEAD_VALID__SHIFT
- GDS_GWS_RESOURCE__RELEASE_ALL_MASK
- GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT
- GDS_GWS_RESOURCE__TYPE_MASK
- GDS_GWS_RESOURCE__TYPE__SHIFT
- GDS_GWS_RESOURCE__UNUSED1_MASK
- GDS_GWS_RESOURCE__UNUSED1__SHIFT
- GDS_GWS_VMID0__BASE_MASK
- GDS_GWS_VMID0__BASE__SHIFT
- GDS_GWS_VMID0__SIZE_MASK
- GDS_GWS_VMID0__SIZE__SHIFT
- GDS_GWS_VMID0__UNUSED1_MASK
- GDS_GWS_VMID0__UNUSED1__SHIFT
- GDS_GWS_VMID0__UNUSED2_MASK
- GDS_GWS_VMID0__UNUSED2__SHIFT
- GDS_GWS_VMID10__BASE_MASK
- GDS_GWS_VMID10__BASE__SHIFT
- GDS_GWS_VMID10__SIZE_MASK
- GDS_GWS_VMID10__SIZE__SHIFT
- GDS_GWS_VMID10__UNUSED1_MASK
- GDS_GWS_VMID10__UNUSED1__SHIFT
- GDS_GWS_VMID10__UNUSED2_MASK
- GDS_GWS_VMID10__UNUSED2__SHIFT
- GDS_GWS_VMID11__BASE_MASK
- GDS_GWS_VMID11__BASE__SHIFT
- GDS_GWS_VMID11__SIZE_MASK
- GDS_GWS_VMID11__SIZE__SHIFT
- GDS_GWS_VMID11__UNUSED1_MASK
- GDS_GWS_VMID11__UNUSED1__SHIFT
- GDS_GWS_VMID11__UNUSED2_MASK
- GDS_GWS_VMID11__UNUSED2__SHIFT
- GDS_GWS_VMID12__BASE_MASK
- GDS_GWS_VMID12__BASE__SHIFT
- GDS_GWS_VMID12__SIZE_MASK
- GDS_GWS_VMID12__SIZE__SHIFT
- GDS_GWS_VMID12__UNUSED1_MASK
- GDS_GWS_VMID12__UNUSED1__SHIFT
- GDS_GWS_VMID12__UNUSED2_MASK
- GDS_GWS_VMID12__UNUSED2__SHIFT
- GDS_GWS_VMID13__BASE_MASK
- GDS_GWS_VMID13__BASE__SHIFT
- GDS_GWS_VMID13__SIZE_MASK
- GDS_GWS_VMID13__SIZE__SHIFT
- GDS_GWS_VMID13__UNUSED1_MASK
- GDS_GWS_VMID13__UNUSED1__SHIFT
- GDS_GWS_VMID13__UNUSED2_MASK
- GDS_GWS_VMID13__UNUSED2__SHIFT
- GDS_GWS_VMID14__BASE_MASK
- GDS_GWS_VMID14__BASE__SHIFT
- GDS_GWS_VMID14__SIZE_MASK
- GDS_GWS_VMID14__SIZE__SHIFT
- GDS_GWS_VMID14__UNUSED1_MASK
- GDS_GWS_VMID14__UNUSED1__SHIFT
- GDS_GWS_VMID14__UNUSED2_MASK
- GDS_GWS_VMID14__UNUSED2__SHIFT
- GDS_GWS_VMID15__BASE_MASK
- GDS_GWS_VMID15__BASE__SHIFT
- GDS_GWS_VMID15__SIZE_MASK
- GDS_GWS_VMID15__SIZE__SHIFT
- GDS_GWS_VMID15__UNUSED1_MASK
- GDS_GWS_VMID15__UNUSED1__SHIFT
- GDS_GWS_VMID15__UNUSED2_MASK
- GDS_GWS_VMID15__UNUSED2__SHIFT
- GDS_GWS_VMID1__BASE_MASK
- GDS_GWS_VMID1__BASE__SHIFT
- GDS_GWS_VMID1__SIZE_MASK
- GDS_GWS_VMID1__SIZE__SHIFT
- GDS_GWS_VMID1__UNUSED1_MASK
- GDS_GWS_VMID1__UNUSED1__SHIFT
- GDS_GWS_VMID1__UNUSED2_MASK
- GDS_GWS_VMID1__UNUSED2__SHIFT
- GDS_GWS_VMID2__BASE_MASK
- GDS_GWS_VMID2__BASE__SHIFT
- GDS_GWS_VMID2__SIZE_MASK
- GDS_GWS_VMID2__SIZE__SHIFT
- GDS_GWS_VMID2__UNUSED1_MASK
- GDS_GWS_VMID2__UNUSED1__SHIFT
- GDS_GWS_VMID2__UNUSED2_MASK
- GDS_GWS_VMID2__UNUSED2__SHIFT
- GDS_GWS_VMID3__BASE_MASK
- GDS_GWS_VMID3__BASE__SHIFT
- GDS_GWS_VMID3__SIZE_MASK
- GDS_GWS_VMID3__SIZE__SHIFT
- GDS_GWS_VMID3__UNUSED1_MASK
- GDS_GWS_VMID3__UNUSED1__SHIFT
- GDS_GWS_VMID3__UNUSED2_MASK
- GDS_GWS_VMID3__UNUSED2__SHIFT
- GDS_GWS_VMID4__BASE_MASK
- GDS_GWS_VMID4__BASE__SHIFT
- GDS_GWS_VMID4__SIZE_MASK
- GDS_GWS_VMID4__SIZE__SHIFT
- GDS_GWS_VMID4__UNUSED1_MASK
- GDS_GWS_VMID4__UNUSED1__SHIFT
- GDS_GWS_VMID4__UNUSED2_MASK
- GDS_GWS_VMID4__UNUSED2__SHIFT
- GDS_GWS_VMID5__BASE_MASK
- GDS_GWS_VMID5__BASE__SHIFT
- GDS_GWS_VMID5__SIZE_MASK
- GDS_GWS_VMID5__SIZE__SHIFT
- GDS_GWS_VMID5__UNUSED1_MASK
- GDS_GWS_VMID5__UNUSED1__SHIFT
- GDS_GWS_VMID5__UNUSED2_MASK
- GDS_GWS_VMID5__UNUSED2__SHIFT
- GDS_GWS_VMID6__BASE_MASK
- GDS_GWS_VMID6__BASE__SHIFT
- GDS_GWS_VMID6__SIZE_MASK
- GDS_GWS_VMID6__SIZE__SHIFT
- GDS_GWS_VMID6__UNUSED1_MASK
- GDS_GWS_VMID6__UNUSED1__SHIFT
- GDS_GWS_VMID6__UNUSED2_MASK
- GDS_GWS_VMID6__UNUSED2__SHIFT
- GDS_GWS_VMID7__BASE_MASK
- GDS_GWS_VMID7__BASE__SHIFT
- GDS_GWS_VMID7__SIZE_MASK
- GDS_GWS_VMID7__SIZE__SHIFT
- GDS_GWS_VMID7__UNUSED1_MASK
- GDS_GWS_VMID7__UNUSED1__SHIFT
- GDS_GWS_VMID7__UNUSED2_MASK
- GDS_GWS_VMID7__UNUSED2__SHIFT
- GDS_GWS_VMID8__BASE_MASK
- GDS_GWS_VMID8__BASE__SHIFT
- GDS_GWS_VMID8__SIZE_MASK
- GDS_GWS_VMID8__SIZE__SHIFT
- GDS_GWS_VMID8__UNUSED1_MASK
- GDS_GWS_VMID8__UNUSED1__SHIFT
- GDS_GWS_VMID8__UNUSED2_MASK
- GDS_GWS_VMID8__UNUSED2__SHIFT
- GDS_GWS_VMID9__BASE_MASK
- GDS_GWS_VMID9__BASE__SHIFT
- GDS_GWS_VMID9__SIZE_MASK
- GDS_GWS_VMID9__SIZE__SHIFT
- GDS_GWS_VMID9__UNUSED1_MASK
- GDS_GWS_VMID9__UNUSED1__SHIFT
- GDS_GWS_VMID9__UNUSED2_MASK
- GDS_GWS_VMID9__UNUSED2__SHIFT
- GDS_ID_AGUNWRKCORR
- GDS_ID_CPMSU
- GDS_ID_MDSMU
- GDS_ID_MDSROUTEINFO
- GDS_ID_OPREQ
- GDS_ID_ROUTTARGINSTR
- GDS_ID_SNACONDREPORT
- GDS_ID_TEXTCMD
- GDS_KEY_SELFDEFTEXTMSG
- GDS_OA_ADDRESS__CRAWLER_MASK
- GDS_OA_ADDRESS__CRAWLER_TYPE_MASK
- GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT
- GDS_OA_ADDRESS__CRAWLER__SHIFT
- GDS_OA_ADDRESS__DS_ADDRESS_MASK
- GDS_OA_ADDRESS__DS_ADDRESS__SHIFT
- GDS_OA_ADDRESS__ENABLE_MASK
- GDS_OA_ADDRESS__ENABLE__SHIFT
- GDS_OA_ADDRESS__NO_ALLOC_MASK
- GDS_OA_ADDRESS__NO_ALLOC__SHIFT
- GDS_OA_ADDRESS__UNUSED_MASK
- GDS_OA_ADDRESS__UNUSED__SHIFT
- GDS_OA_CGPG_RESTORE__MEID_MASK
- GDS_OA_CGPG_RESTORE__MEID__SHIFT
- GDS_OA_CGPG_RESTORE__PIPEID_MASK
- GDS_OA_CGPG_RESTORE__PIPEID__SHIFT
- GDS_OA_CGPG_RESTORE__QUEUEID_MASK
- GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT
- GDS_OA_CGPG_RESTORE__UNUSED_MASK
- GDS_OA_CGPG_RESTORE__UNUSED__SHIFT
- GDS_OA_CGPG_RESTORE__VMID_MASK
- GDS_OA_CGPG_RESTORE__VMID__SHIFT
- GDS_OA_CNTL__INDEX_MASK
- GDS_OA_CNTL__INDEX__SHIFT
- GDS_OA_CNTL__UNUSED_MASK
- GDS_OA_CNTL__UNUSED__SHIFT
- GDS_OA_COUNTER__SPACE_AVAILABLE_MASK
- GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT
- GDS_OA_DED__ME0_CS_DED_MASK
- GDS_OA_DED__ME0_CS_DED__SHIFT
- GDS_OA_DED__ME0_GFXHP3D_PIX_DED_MASK
- GDS_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT
- GDS_OA_DED__ME0_GFXHP3D_VTX_DED_MASK
- GDS_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT
- GDS_OA_DED__ME1_PIPE0_DED_MASK
- GDS_OA_DED__ME1_PIPE0_DED__SHIFT
- GDS_OA_DED__ME1_PIPE1_DED_MASK
- GDS_OA_DED__ME1_PIPE1_DED__SHIFT
- GDS_OA_DED__ME1_PIPE2_DED_MASK
- GDS_OA_DED__ME1_PIPE2_DED__SHIFT
- GDS_OA_DED__ME1_PIPE3_DED_MASK
- GDS_OA_DED__ME1_PIPE3_DED__SHIFT
- GDS_OA_DED__ME2_PIPE0_DED_MASK
- GDS_OA_DED__ME2_PIPE0_DED__SHIFT
- GDS_OA_DED__ME2_PIPE1_DED_MASK
- GDS_OA_DED__ME2_PIPE1_DED__SHIFT
- GDS_OA_DED__ME2_PIPE2_DED_MASK
- GDS_OA_DED__ME2_PIPE2_DED__SHIFT
- GDS_OA_DED__ME2_PIPE3_DED_MASK
- GDS_OA_DED__ME2_PIPE3_DED__SHIFT
- GDS_OA_DED__UNUSED0_MASK
- GDS_OA_DED__UNUSED0__SHIFT
- GDS_OA_DED__UNUSED1_MASK
- GDS_OA_DED__UNUSED1__SHIFT
- GDS_OA_INCDEC__INCDEC_MASK
- GDS_OA_INCDEC__INCDEC__SHIFT
- GDS_OA_INCDEC__VALUE_MASK
- GDS_OA_INCDEC__VALUE__SHIFT
- GDS_OA_RESET_MASK__ME0_CS_RESET_MASK
- GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT
- GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK
- GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT
- GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK
- GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT
- GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK
- GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT
- GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK
- GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT
- GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK
- GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT
- GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK
- GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT
- GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK
- GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT
- GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK
- GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT
- GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK
- GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT
- GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK
- GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT
- GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK
- GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT
- GDS_OA_RESET_MASK__UNUSED0_MASK
- GDS_OA_RESET_MASK__UNUSED0__SHIFT
- GDS_OA_RESET_MASK__UNUSED1_MASK
- GDS_OA_RESET_MASK__UNUSED1__SHIFT
- GDS_OA_RESET__PIPE_ID_MASK
- GDS_OA_RESET__PIPE_ID__SHIFT
- GDS_OA_RESET__RESET_MASK
- GDS_OA_RESET__RESET__SHIFT
- GDS_OA_RESET__UNUSED_MASK
- GDS_OA_RESET__UNUSED__SHIFT
- GDS_OA_RING_SIZE__RING_SIZE_MASK
- GDS_OA_RING_SIZE__RING_SIZE__SHIFT
- GDS_OA_VMID0__MASK_MASK
- GDS_OA_VMID0__MASK__SHIFT
- GDS_OA_VMID0__UNUSED_MASK
- GDS_OA_VMID0__UNUSED__SHIFT
- GDS_OA_VMID10__MASK_MASK
- GDS_OA_VMID10__MASK__SHIFT
- GDS_OA_VMID10__UNUSED_MASK
- GDS_OA_VMID10__UNUSED__SHIFT
- GDS_OA_VMID11__MASK_MASK
- GDS_OA_VMID11__MASK__SHIFT
- GDS_OA_VMID11__UNUSED_MASK
- GDS_OA_VMID11__UNUSED__SHIFT
- GDS_OA_VMID12__MASK_MASK
- GDS_OA_VMID12__MASK__SHIFT
- GDS_OA_VMID12__UNUSED_MASK
- GDS_OA_VMID12__UNUSED__SHIFT
- GDS_OA_VMID13__MASK_MASK
- GDS_OA_VMID13__MASK__SHIFT
- GDS_OA_VMID13__UNUSED_MASK
- GDS_OA_VMID13__UNUSED__SHIFT
- GDS_OA_VMID14__MASK_MASK
- GDS_OA_VMID14__MASK__SHIFT
- GDS_OA_VMID14__UNUSED_MASK
- GDS_OA_VMID14__UNUSED__SHIFT
- GDS_OA_VMID15__MASK_MASK
- GDS_OA_VMID15__MASK__SHIFT
- GDS_OA_VMID15__UNUSED_MASK
- GDS_OA_VMID15__UNUSED__SHIFT
- GDS_OA_VMID1__MASK_MASK
- GDS_OA_VMID1__MASK__SHIFT
- GDS_OA_VMID1__UNUSED_MASK
- GDS_OA_VMID1__UNUSED__SHIFT
- GDS_OA_VMID2__MASK_MASK
- GDS_OA_VMID2__MASK__SHIFT
- GDS_OA_VMID2__UNUSED_MASK
- GDS_OA_VMID2__UNUSED__SHIFT
- GDS_OA_VMID3__MASK_MASK
- GDS_OA_VMID3__MASK__SHIFT
- GDS_OA_VMID3__UNUSED_MASK
- GDS_OA_VMID3__UNUSED__SHIFT
- GDS_OA_VMID4__MASK_MASK
- GDS_OA_VMID4__MASK__SHIFT
- GDS_OA_VMID4__UNUSED_MASK
- GDS_OA_VMID4__UNUSED__SHIFT
- GDS_OA_VMID5__MASK_MASK
- GDS_OA_VMID5__MASK__SHIFT
- GDS_OA_VMID5__UNUSED_MASK
- GDS_OA_VMID5__UNUSED__SHIFT
- GDS_OA_VMID6__MASK_MASK
- GDS_OA_VMID6__MASK__SHIFT
- GDS_OA_VMID6__UNUSED_MASK
- GDS_OA_VMID6__UNUSED__SHIFT
- GDS_OA_VMID7__MASK_MASK
- GDS_OA_VMID7__MASK__SHIFT
- GDS_OA_VMID7__UNUSED_MASK
- GDS_OA_VMID7__UNUSED__SHIFT
- GDS_OA_VMID8__MASK_MASK
- GDS_OA_VMID8__MASK__SHIFT
- GDS_OA_VMID8__UNUSED_MASK
- GDS_OA_VMID8__UNUSED__SHIFT
- GDS_OA_VMID9__MASK_MASK
- GDS_OA_VMID9__MASK__SHIFT
- GDS_OA_VMID9__UNUSED_MASK
- GDS_OA_VMID9__UNUSED__SHIFT
- GDS_PARTITION_BASE
- GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK
- GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK
- GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK
- GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK
- GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK
- GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK
- GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK
- GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK
- GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK
- GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK
- GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK
- GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK
- GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT
- GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- GDS_PERFCOUNT_SELECT
- GDS_PERF_SEL_DS_ADDR_CONFL
- GDS_PERF_SEL_DS_BANK_CONFL
- GDS_PERF_SEL_GWS_BYPASS
- GDS_PERF_SEL_GWS_RELEASED
- GDS_PERF_SEL_RBUF_HIT
- GDS_PERF_SEL_RBUF_MISS
- GDS_PERF_SEL_SE0_SH0_2COMP_REQ
- GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP
- GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP
- GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID
- GDS_PERF_SEL_SE0_SH0_GDS_RD_OP
- GDS_PERF_SEL_SE0_SH0_GDS_REL_OP
- GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP
- GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE0_SH0_GDS_WR_OP
- GDS_PERF_SEL_SE0_SH0_NORET
- GDS_PERF_SEL_SE0_SH0_ORD_CNT
- GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID
- GDS_PERF_SEL_SE0_SH0_RET
- GDS_PERF_SEL_SE0_SH1_2COMP_REQ
- GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP
- GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP
- GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID
- GDS_PERF_SEL_SE0_SH1_GDS_RD_OP
- GDS_PERF_SEL_SE0_SH1_GDS_REL_OP
- GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP
- GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE0_SH1_GDS_WR_OP
- GDS_PERF_SEL_SE0_SH1_NORET
- GDS_PERF_SEL_SE0_SH1_ORD_CNT
- GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID
- GDS_PERF_SEL_SE0_SH1_RET
- GDS_PERF_SEL_SE1_SH0_2COMP_REQ
- GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP
- GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP
- GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID
- GDS_PERF_SEL_SE1_SH0_GDS_RD_OP
- GDS_PERF_SEL_SE1_SH0_GDS_REL_OP
- GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP
- GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE1_SH0_GDS_WR_OP
- GDS_PERF_SEL_SE1_SH0_NORET
- GDS_PERF_SEL_SE1_SH0_ORD_CNT
- GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID
- GDS_PERF_SEL_SE1_SH0_RET
- GDS_PERF_SEL_SE1_SH1_2COMP_REQ
- GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP
- GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP
- GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID
- GDS_PERF_SEL_SE1_SH1_GDS_RD_OP
- GDS_PERF_SEL_SE1_SH1_GDS_REL_OP
- GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP
- GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE1_SH1_GDS_WR_OP
- GDS_PERF_SEL_SE1_SH1_NORET
- GDS_PERF_SEL_SE1_SH1_ORD_CNT
- GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID
- GDS_PERF_SEL_SE1_SH1_RET
- GDS_PERF_SEL_SE2_SH0_2COMP_REQ
- GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP
- GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP
- GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID
- GDS_PERF_SEL_SE2_SH0_GDS_RD_OP
- GDS_PERF_SEL_SE2_SH0_GDS_REL_OP
- GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP
- GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE2_SH0_GDS_WR_OP
- GDS_PERF_SEL_SE2_SH0_NORET
- GDS_PERF_SEL_SE2_SH0_ORD_CNT
- GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID
- GDS_PERF_SEL_SE2_SH0_RET
- GDS_PERF_SEL_SE2_SH1_2COMP_REQ
- GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP
- GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP
- GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID
- GDS_PERF_SEL_SE2_SH1_GDS_RD_OP
- GDS_PERF_SEL_SE2_SH1_GDS_REL_OP
- GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP
- GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE2_SH1_GDS_WR_OP
- GDS_PERF_SEL_SE2_SH1_NORET
- GDS_PERF_SEL_SE2_SH1_ORD_CNT
- GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID
- GDS_PERF_SEL_SE2_SH1_RET
- GDS_PERF_SEL_SE3_SH0_2COMP_REQ
- GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP
- GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP
- GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID
- GDS_PERF_SEL_SE3_SH0_GDS_RD_OP
- GDS_PERF_SEL_SE3_SH0_GDS_REL_OP
- GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP
- GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE3_SH0_GDS_WR_OP
- GDS_PERF_SEL_SE3_SH0_NORET
- GDS_PERF_SEL_SE3_SH0_ORD_CNT
- GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID
- GDS_PERF_SEL_SE3_SH0_RET
- GDS_PERF_SEL_SE3_SH1_2COMP_REQ
- GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP
- GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP
- GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP
- GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID
- GDS_PERF_SEL_SE3_SH1_GDS_RD_OP
- GDS_PERF_SEL_SE3_SH1_GDS_REL_OP
- GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP
- GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD
- GDS_PERF_SEL_SE3_SH1_GDS_WR_OP
- GDS_PERF_SEL_SE3_SH1_NORET
- GDS_PERF_SEL_SE3_SH1_ORD_CNT
- GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID
- GDS_PERF_SEL_SE3_SH1_RET
- GDS_PERF_SEL_WBUF_FLUSH
- GDS_PERF_SEL_WBUF_WR
- GDS_PERF_SEL_WR_COMP
- GDS_PROTECTION_FAULT__ADDRESS_MASK
- GDS_PROTECTION_FAULT__ADDRESS__SHIFT
- GDS_PROTECTION_FAULT__CU_ID_MASK
- GDS_PROTECTION_FAULT__CU_ID__SHIFT
- GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK
- GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT
- GDS_PROTECTION_FAULT__GRBM_MASK
- GDS_PROTECTION_FAULT__GRBM__SHIFT
- GDS_PROTECTION_FAULT__SH_ID_MASK
- GDS_PROTECTION_FAULT__SH_ID__SHIFT
- GDS_PROTECTION_FAULT__SIMD_ID_MASK
- GDS_PROTECTION_FAULT__SIMD_ID__SHIFT
- GDS_PROTECTION_FAULT__WAVE_ID_MASK
- GDS_PROTECTION_FAULT__WAVE_ID__SHIFT
- GDS_PROTECTION_FAULT__WRITE_DIS_MASK
- GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT
- GDS_PS0_CTXSW_CNT0__PTR_MASK
- GDS_PS0_CTXSW_CNT0__PTR__SHIFT
- GDS_PS0_CTXSW_CNT0__UPDN_MASK
- GDS_PS0_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS0_CTXSW_CNT1__PTR_MASK
- GDS_PS0_CTXSW_CNT1__PTR__SHIFT
- GDS_PS0_CTXSW_CNT1__UPDN_MASK
- GDS_PS0_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS0_CTXSW_CNT2__PTR_MASK
- GDS_PS0_CTXSW_CNT2__PTR__SHIFT
- GDS_PS0_CTXSW_CNT2__UPDN_MASK
- GDS_PS0_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS0_CTXSW_CNT3__PTR_MASK
- GDS_PS0_CTXSW_CNT3__PTR__SHIFT
- GDS_PS0_CTXSW_CNT3__UPDN_MASK
- GDS_PS0_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS1_CTXSW_CNT0__PTR_MASK
- GDS_PS1_CTXSW_CNT0__PTR__SHIFT
- GDS_PS1_CTXSW_CNT0__UPDN_MASK
- GDS_PS1_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS1_CTXSW_CNT1__PTR_MASK
- GDS_PS1_CTXSW_CNT1__PTR__SHIFT
- GDS_PS1_CTXSW_CNT1__UPDN_MASK
- GDS_PS1_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS1_CTXSW_CNT2__PTR_MASK
- GDS_PS1_CTXSW_CNT2__PTR__SHIFT
- GDS_PS1_CTXSW_CNT2__UPDN_MASK
- GDS_PS1_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS1_CTXSW_CNT3__PTR_MASK
- GDS_PS1_CTXSW_CNT3__PTR__SHIFT
- GDS_PS1_CTXSW_CNT3__UPDN_MASK
- GDS_PS1_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS2_CTXSW_CNT0__PTR_MASK
- GDS_PS2_CTXSW_CNT0__PTR__SHIFT
- GDS_PS2_CTXSW_CNT0__UPDN_MASK
- GDS_PS2_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS2_CTXSW_CNT1__PTR_MASK
- GDS_PS2_CTXSW_CNT1__PTR__SHIFT
- GDS_PS2_CTXSW_CNT1__UPDN_MASK
- GDS_PS2_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS2_CTXSW_CNT2__PTR_MASK
- GDS_PS2_CTXSW_CNT2__PTR__SHIFT
- GDS_PS2_CTXSW_CNT2__UPDN_MASK
- GDS_PS2_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS2_CTXSW_CNT3__PTR_MASK
- GDS_PS2_CTXSW_CNT3__PTR__SHIFT
- GDS_PS2_CTXSW_CNT3__UPDN_MASK
- GDS_PS2_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS3_CTXSW_CNT0__PTR_MASK
- GDS_PS3_CTXSW_CNT0__PTR__SHIFT
- GDS_PS3_CTXSW_CNT0__UPDN_MASK
- GDS_PS3_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS3_CTXSW_CNT1__PTR_MASK
- GDS_PS3_CTXSW_CNT1__PTR__SHIFT
- GDS_PS3_CTXSW_CNT1__UPDN_MASK
- GDS_PS3_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS3_CTXSW_CNT2__PTR_MASK
- GDS_PS3_CTXSW_CNT2__PTR__SHIFT
- GDS_PS3_CTXSW_CNT2__UPDN_MASK
- GDS_PS3_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS3_CTXSW_CNT3__PTR_MASK
- GDS_PS3_CTXSW_CNT3__PTR__SHIFT
- GDS_PS3_CTXSW_CNT3__UPDN_MASK
- GDS_PS3_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS4_CTXSW_CNT0__PTR_MASK
- GDS_PS4_CTXSW_CNT0__PTR__SHIFT
- GDS_PS4_CTXSW_CNT0__UPDN_MASK
- GDS_PS4_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS4_CTXSW_CNT1__PTR_MASK
- GDS_PS4_CTXSW_CNT1__PTR__SHIFT
- GDS_PS4_CTXSW_CNT1__UPDN_MASK
- GDS_PS4_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS4_CTXSW_CNT2__PTR_MASK
- GDS_PS4_CTXSW_CNT2__PTR__SHIFT
- GDS_PS4_CTXSW_CNT2__UPDN_MASK
- GDS_PS4_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS4_CTXSW_CNT3__PTR_MASK
- GDS_PS4_CTXSW_CNT3__PTR__SHIFT
- GDS_PS4_CTXSW_CNT3__UPDN_MASK
- GDS_PS4_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS5_CTXSW_CNT0__PTR_MASK
- GDS_PS5_CTXSW_CNT0__PTR__SHIFT
- GDS_PS5_CTXSW_CNT0__UPDN_MASK
- GDS_PS5_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS5_CTXSW_CNT1__PTR_MASK
- GDS_PS5_CTXSW_CNT1__PTR__SHIFT
- GDS_PS5_CTXSW_CNT1__UPDN_MASK
- GDS_PS5_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS5_CTXSW_CNT2__PTR_MASK
- GDS_PS5_CTXSW_CNT2__PTR__SHIFT
- GDS_PS5_CTXSW_CNT2__UPDN_MASK
- GDS_PS5_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS5_CTXSW_CNT3__PTR_MASK
- GDS_PS5_CTXSW_CNT3__PTR__SHIFT
- GDS_PS5_CTXSW_CNT3__UPDN_MASK
- GDS_PS5_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS6_CTXSW_CNT0__PTR_MASK
- GDS_PS6_CTXSW_CNT0__PTR__SHIFT
- GDS_PS6_CTXSW_CNT0__UPDN_MASK
- GDS_PS6_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS6_CTXSW_CNT1__PTR_MASK
- GDS_PS6_CTXSW_CNT1__PTR__SHIFT
- GDS_PS6_CTXSW_CNT1__UPDN_MASK
- GDS_PS6_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS6_CTXSW_CNT2__PTR_MASK
- GDS_PS6_CTXSW_CNT2__PTR__SHIFT
- GDS_PS6_CTXSW_CNT2__UPDN_MASK
- GDS_PS6_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS6_CTXSW_CNT3__PTR_MASK
- GDS_PS6_CTXSW_CNT3__PTR__SHIFT
- GDS_PS6_CTXSW_CNT3__UPDN_MASK
- GDS_PS6_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS7_CTXSW_CNT0__PTR_MASK
- GDS_PS7_CTXSW_CNT0__PTR__SHIFT
- GDS_PS7_CTXSW_CNT0__UPDN_MASK
- GDS_PS7_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS7_CTXSW_CNT1__PTR_MASK
- GDS_PS7_CTXSW_CNT1__PTR__SHIFT
- GDS_PS7_CTXSW_CNT1__UPDN_MASK
- GDS_PS7_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS7_CTXSW_CNT2__PTR_MASK
- GDS_PS7_CTXSW_CNT2__PTR__SHIFT
- GDS_PS7_CTXSW_CNT2__UPDN_MASK
- GDS_PS7_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS7_CTXSW_CNT3__PTR_MASK
- GDS_PS7_CTXSW_CNT3__PTR__SHIFT
- GDS_PS7_CTXSW_CNT3__UPDN_MASK
- GDS_PS7_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS_CTXSW_CNT0__PTR_MASK
- GDS_PS_CTXSW_CNT0__PTR__SHIFT
- GDS_PS_CTXSW_CNT0__UPDN_MASK
- GDS_PS_CTXSW_CNT0__UPDN__SHIFT
- GDS_PS_CTXSW_CNT1__PTR_MASK
- GDS_PS_CTXSW_CNT1__PTR__SHIFT
- GDS_PS_CTXSW_CNT1__UPDN_MASK
- GDS_PS_CTXSW_CNT1__UPDN__SHIFT
- GDS_PS_CTXSW_CNT2__PTR_MASK
- GDS_PS_CTXSW_CNT2__PTR__SHIFT
- GDS_PS_CTXSW_CNT2__UPDN_MASK
- GDS_PS_CTXSW_CNT2__UPDN__SHIFT
- GDS_PS_CTXSW_CNT3__PTR_MASK
- GDS_PS_CTXSW_CNT3__PTR__SHIFT
- GDS_PS_CTXSW_CNT3__UPDN_MASK
- GDS_PS_CTXSW_CNT3__UPDN__SHIFT
- GDS_PS_CTXSW_IDX__PACKER_ID_MASK
- GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT
- GDS_PS_CTXSW_IDX__UNUSED_MASK
- GDS_PS_CTXSW_IDX__UNUSED__SHIFT
- GDS_RD_ADDR__READ_ADDR_MASK
- GDS_RD_ADDR__READ_ADDR__SHIFT
- GDS_RD_BURST_ADDR__BURST_ADDR_MASK
- GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT
- GDS_RD_BURST_COUNT__BURST_COUNT_MASK
- GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT
- GDS_RD_BURST_DATA__BURST_DATA_MASK
- GDS_RD_BURST_DATA__BURST_DATA__SHIFT
- GDS_RD_DATA__READ_DATA_MASK
- GDS_RD_DATA__READ_DATA__SHIFT
- GDS_SECDED_CNT__DED_MASK
- GDS_SECDED_CNT__DED__SHIFT
- GDS_SECDED_CNT__SEC_MASK
- GDS_SECDED_CNT__SEC__SHIFT
- GDS_VMID0_BASE__BASE_MASK
- GDS_VMID0_BASE__BASE__SHIFT
- GDS_VMID0_BASE__UNUSED_MASK
- GDS_VMID0_BASE__UNUSED__SHIFT
- GDS_VMID0_SIZE__SIZE_MASK
- GDS_VMID0_SIZE__SIZE__SHIFT
- GDS_VMID0_SIZE__UNUSED_MASK
- GDS_VMID0_SIZE__UNUSED__SHIFT
- GDS_VMID10_BASE__BASE_MASK
- GDS_VMID10_BASE__BASE__SHIFT
- GDS_VMID10_BASE__UNUSED_MASK
- GDS_VMID10_BASE__UNUSED__SHIFT
- GDS_VMID10_SIZE__SIZE_MASK
- GDS_VMID10_SIZE__SIZE__SHIFT
- GDS_VMID10_SIZE__UNUSED_MASK
- GDS_VMID10_SIZE__UNUSED__SHIFT
- GDS_VMID11_BASE__BASE_MASK
- GDS_VMID11_BASE__BASE__SHIFT
- GDS_VMID11_BASE__UNUSED_MASK
- GDS_VMID11_BASE__UNUSED__SHIFT
- GDS_VMID11_SIZE__SIZE_MASK
- GDS_VMID11_SIZE__SIZE__SHIFT
- GDS_VMID11_SIZE__UNUSED_MASK
- GDS_VMID11_SIZE__UNUSED__SHIFT
- GDS_VMID12_BASE__BASE_MASK
- GDS_VMID12_BASE__BASE__SHIFT
- GDS_VMID12_BASE__UNUSED_MASK
- GDS_VMID12_BASE__UNUSED__SHIFT
- GDS_VMID12_SIZE__SIZE_MASK
- GDS_VMID12_SIZE__SIZE__SHIFT
- GDS_VMID12_SIZE__UNUSED_MASK
- GDS_VMID12_SIZE__UNUSED__SHIFT
- GDS_VMID13_BASE__BASE_MASK
- GDS_VMID13_BASE__BASE__SHIFT
- GDS_VMID13_BASE__UNUSED_MASK
- GDS_VMID13_BASE__UNUSED__SHIFT
- GDS_VMID13_SIZE__SIZE_MASK
- GDS_VMID13_SIZE__SIZE__SHIFT
- GDS_VMID13_SIZE__UNUSED_MASK
- GDS_VMID13_SIZE__UNUSED__SHIFT
- GDS_VMID14_BASE__BASE_MASK
- GDS_VMID14_BASE__BASE__SHIFT
- GDS_VMID14_BASE__UNUSED_MASK
- GDS_VMID14_BASE__UNUSED__SHIFT
- GDS_VMID14_SIZE__SIZE_MASK
- GDS_VMID14_SIZE__SIZE__SHIFT
- GDS_VMID14_SIZE__UNUSED_MASK
- GDS_VMID14_SIZE__UNUSED__SHIFT
- GDS_VMID15_BASE__BASE_MASK
- GDS_VMID15_BASE__BASE__SHIFT
- GDS_VMID15_BASE__UNUSED_MASK
- GDS_VMID15_BASE__UNUSED__SHIFT
- GDS_VMID15_SIZE__SIZE_MASK
- GDS_VMID15_SIZE__SIZE__SHIFT
- GDS_VMID15_SIZE__UNUSED_MASK
- GDS_VMID15_SIZE__UNUSED__SHIFT
- GDS_VMID1_BASE__BASE_MASK
- GDS_VMID1_BASE__BASE__SHIFT
- GDS_VMID1_BASE__UNUSED_MASK
- GDS_VMID1_BASE__UNUSED__SHIFT
- GDS_VMID1_SIZE__SIZE_MASK
- GDS_VMID1_SIZE__SIZE__SHIFT
- GDS_VMID1_SIZE__UNUSED_MASK
- GDS_VMID1_SIZE__UNUSED__SHIFT
- GDS_VMID2_BASE__BASE_MASK
- GDS_VMID2_BASE__BASE__SHIFT
- GDS_VMID2_BASE__UNUSED_MASK
- GDS_VMID2_BASE__UNUSED__SHIFT
- GDS_VMID2_SIZE__SIZE_MASK
- GDS_VMID2_SIZE__SIZE__SHIFT
- GDS_VMID2_SIZE__UNUSED_MASK
- GDS_VMID2_SIZE__UNUSED__SHIFT
- GDS_VMID3_BASE__BASE_MASK
- GDS_VMID3_BASE__BASE__SHIFT
- GDS_VMID3_BASE__UNUSED_MASK
- GDS_VMID3_BASE__UNUSED__SHIFT
- GDS_VMID3_SIZE__SIZE_MASK
- GDS_VMID3_SIZE__SIZE__SHIFT
- GDS_VMID3_SIZE__UNUSED_MASK
- GDS_VMID3_SIZE__UNUSED__SHIFT
- GDS_VMID4_BASE__BASE_MASK
- GDS_VMID4_BASE__BASE__SHIFT
- GDS_VMID4_BASE__UNUSED_MASK
- GDS_VMID4_BASE__UNUSED__SHIFT
- GDS_VMID4_SIZE__SIZE_MASK
- GDS_VMID4_SIZE__SIZE__SHIFT
- GDS_VMID4_SIZE__UNUSED_MASK
- GDS_VMID4_SIZE__UNUSED__SHIFT
- GDS_VMID5_BASE__BASE_MASK
- GDS_VMID5_BASE__BASE__SHIFT
- GDS_VMID5_BASE__UNUSED_MASK
- GDS_VMID5_BASE__UNUSED__SHIFT
- GDS_VMID5_SIZE__SIZE_MASK
- GDS_VMID5_SIZE__SIZE__SHIFT
- GDS_VMID5_SIZE__UNUSED_MASK
- GDS_VMID5_SIZE__UNUSED__SHIFT
- GDS_VMID6_BASE__BASE_MASK
- GDS_VMID6_BASE__BASE__SHIFT
- GDS_VMID6_BASE__UNUSED_MASK
- GDS_VMID6_BASE__UNUSED__SHIFT
- GDS_VMID6_SIZE__SIZE_MASK
- GDS_VMID6_SIZE__SIZE__SHIFT
- GDS_VMID6_SIZE__UNUSED_MASK
- GDS_VMID6_SIZE__UNUSED__SHIFT
- GDS_VMID7_BASE__BASE_MASK
- GDS_VMID7_BASE__BASE__SHIFT
- GDS_VMID7_BASE__UNUSED_MASK
- GDS_VMID7_BASE__UNUSED__SHIFT
- GDS_VMID7_SIZE__SIZE_MASK
- GDS_VMID7_SIZE__SIZE__SHIFT
- GDS_VMID7_SIZE__UNUSED_MASK
- GDS_VMID7_SIZE__UNUSED__SHIFT
- GDS_VMID8_BASE__BASE_MASK
- GDS_VMID8_BASE__BASE__SHIFT
- GDS_VMID8_BASE__UNUSED_MASK
- GDS_VMID8_BASE__UNUSED__SHIFT
- GDS_VMID8_SIZE__SIZE_MASK
- GDS_VMID8_SIZE__SIZE__SHIFT
- GDS_VMID8_SIZE__UNUSED_MASK
- GDS_VMID8_SIZE__UNUSED__SHIFT
- GDS_VMID9_BASE__BASE_MASK
- GDS_VMID9_BASE__BASE__SHIFT
- GDS_VMID9_BASE__UNUSED_MASK
- GDS_VMID9_BASE__UNUSED__SHIFT
- GDS_VMID9_SIZE__SIZE_MASK
- GDS_VMID9_SIZE__SIZE__SHIFT
- GDS_VMID9_SIZE__UNUSED_MASK
- GDS_VMID9_SIZE__UNUSED__SHIFT
- GDS_VM_PROTECTION_FAULT__ADDRESS_MASK
- GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT
- GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK
- GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT
- GDS_VM_PROTECTION_FAULT__GRBM_MASK
- GDS_VM_PROTECTION_FAULT__GRBM__SHIFT
- GDS_VM_PROTECTION_FAULT__GWS_MASK
- GDS_VM_PROTECTION_FAULT__GWS__SHIFT
- GDS_VM_PROTECTION_FAULT__OA_MASK
- GDS_VM_PROTECTION_FAULT__OA__SHIFT
- GDS_VM_PROTECTION_FAULT__TMZ_MASK
- GDS_VM_PROTECTION_FAULT__TMZ__SHIFT
- GDS_VM_PROTECTION_FAULT__UNUSED1_MASK
- GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT
- GDS_VM_PROTECTION_FAULT__UNUSED2_MASK
- GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT
- GDS_VM_PROTECTION_FAULT__VMID_MASK
- GDS_VM_PROTECTION_FAULT__VMID__SHIFT
- GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK
- GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT
- GDS_VS_CTXSW_CNT0__PTR_MASK
- GDS_VS_CTXSW_CNT0__PTR__SHIFT
- GDS_VS_CTXSW_CNT0__UPDN_MASK
- GDS_VS_CTXSW_CNT0__UPDN__SHIFT
- GDS_VS_CTXSW_CNT1__PTR_MASK
- GDS_VS_CTXSW_CNT1__PTR__SHIFT
- GDS_VS_CTXSW_CNT1__UPDN_MASK
- GDS_VS_CTXSW_CNT1__UPDN__SHIFT
- GDS_VS_CTXSW_CNT2__PTR_MASK
- GDS_VS_CTXSW_CNT2__PTR__SHIFT
- GDS_VS_CTXSW_CNT2__UPDN_MASK
- GDS_VS_CTXSW_CNT2__UPDN__SHIFT
- GDS_VS_CTXSW_CNT3__PTR_MASK
- GDS_VS_CTXSW_CNT3__PTR__SHIFT
- GDS_VS_CTXSW_CNT3__UPDN_MASK
- GDS_VS_CTXSW_CNT3__UPDN__SHIFT
- GDS_WD_GDS_CSB__COUNTER_MASK
- GDS_WD_GDS_CSB__COUNTER__SHIFT
- GDS_WD_GDS_CSB__UNUSED_MASK
- GDS_WD_GDS_CSB__UNUSED__SHIFT
- GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK
- GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT
- GDS_WR_ADDR__WRITE_ADDR_MASK
- GDS_WR_ADDR__WRITE_ADDR__SHIFT
- GDS_WR_BURST_ADDR__WRITE_ADDR_MASK
- GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT
- GDS_WR_BURST_DATA__WRITE_DATA_MASK
- GDS_WR_BURST_DATA__WRITE_DATA__SHIFT
- GDS_WR_DATA__WRITE_DATA_MASK
- GDS_WR_DATA__WRITE_DATA__SHIFT
- GDT3
- GDTA
- GDTC_INIT
- GDTC_INIT_NO_WB
- GDTH_DATA_IN
- GDTH_DATA_OUT
- GDTH_MAXCMDS
- GDTH_MAXC_P_L
- GDTH_MAXSG
- GDTH_MAX_RAW
- GDTH_SCRATCH
- GDTH_STATISTICS
- GDTH_SUBVERSION
- GDTH_VERSION
- GDTH_VERSION_STR
- GDTIOCTL_CTRCNT
- GDTIOCTL_CTRTYPE
- GDTIOCTL_DRVERS
- GDTIOCTL_EVENT
- GDTIOCTL_GENERAL
- GDTIOCTL_HDRLIST
- GDTIOCTL_LOCKCHN
- GDTIOCTL_LOCKDRV
- GDTIOCTL_MAGIC
- GDTIOCTL_MASK
- GDTIOCTL_OSVERS
- GDTIOCTL_RESCAN
- GDTIOCTL_RESET_BUS
- GDTIOCTL_RESET_DRV
- GDTIOCTL_SCSI
- GDTOFFSOF
- GDT_64BIT
- GDT_CHICKEN_BITS
- GDT_CLUST_INFO
- GDT_CLUST_RESET
- GDT_DEVTYPE
- GDT_ENTRIES
- GDT_ENTRY
- GDT_ENTRY_APMBIOS_BASE
- GDT_ENTRY_BOOT_CS
- GDT_ENTRY_BOOT_DS
- GDT_ENTRY_BOOT_TSS
- GDT_ENTRY_CPUNODE
- GDT_ENTRY_DEFAULT_USER32_CS
- GDT_ENTRY_DEFAULT_USER_CS
- GDT_ENTRY_DEFAULT_USER_DS
- GDT_ENTRY_DOUBLEFAULT_TSS
- GDT_ENTRY_ESPFIX_SS
- GDT_ENTRY_INIT
- GDT_ENTRY_INVALID_SEG
- GDT_ENTRY_KERNEL32_CS
- GDT_ENTRY_KERNEL_CS
- GDT_ENTRY_KERNEL_DS
- GDT_ENTRY_LDT
- GDT_ENTRY_PERCPU
- GDT_ENTRY_PNPBIOS_CS16
- GDT_ENTRY_PNPBIOS_CS32
- GDT_ENTRY_PNPBIOS_DS
- GDT_ENTRY_PNPBIOS_TS1
- GDT_ENTRY_PNPBIOS_TS2
- GDT_ENTRY_STACK_CANARY
- GDT_ENTRY_TLS_ENTRIES
- GDT_ENTRY_TLS_MAX
- GDT_ENTRY_TLS_MIN
- GDT_ENTRY_TLS_MIN_I386
- GDT_ENTRY_TLS_MIN_X86_64
- GDT_ENTRY_TSS
- GDT_ESPFIX_OFFSET
- GDT_ESPFIX_SS
- GDT_EXT_INFO
- GDT_FLUSH
- GDT_FREEZE_IO
- GDT_GET_FEAT
- GDT_INFO
- GDT_INIT
- GDT_IOCTL
- GDT_MOUNT
- GDT_PCI
- GDT_PCIMPR
- GDT_PCINEW
- GDT_READ
- GDT_READ_THR
- GDT_REALTIME
- GDT_RELEASE
- GDT_RELEASE_ALL
- GDT_RELEASE_DRV
- GDT_RESERVE
- GDT_RESERVE_ALL
- GDT_RESERVE_DRV
- GDT_RESET
- GDT_RESET_BUS
- GDT_RW_ATTRIBS
- GDT_SCAN_END
- GDT_SCAN_START
- GDT_SET_FEAT
- GDT_SIZE
- GDT_STACK_CANARY_INIT
- GDT_UNFREEZE_IO
- GDT_UNMOUNT
- GDT_WRITE
- GDT_WRITE_THR
- GDT_WR_THROUGH
- GDT_X_INFO
- GDT_X_INIT_HOST
- GDT_X_INIT_RAW
- GDT_X_INIT_SCR
- GDWN_DIS
- GD_CHIP_ID
- GD_CLOCK_44
- GD_CLOCK_48
- GD_CLOCK_NOCHANGE
- GD_CLOCK_SPDIFIN
- GD_CLOCK_UNDEF
- GD_SESSION_OFFSET
- GD_SPDIF_STATUS_44
- GD_SPDIF_STATUS_48
- GD_SPDIF_STATUS_NOCHANGE
- GD_SPDIF_STATUS_UNDEF
- GD_TO_BLK
- GE00_PHYS_BASE
- GE01_PHYS_BASE
- GE10_PHYS_BASE
- GE11_PHYS_BASE
- GECMR
- GECMR_10
- GECMR_100
- GECMR_1000
- GECMR_BIT
- GECMR_SPEED
- GECMR_SPEED_100
- GECMR_SPEED_1000
- GEDR
- GEDR_OFFSET
- GEF_GPIO_DIRECT
- GEF_GPIO_IN
- GEF_GPIO_INT_STAT
- GEF_GPIO_MODE
- GEF_GPIO_OUT
- GEF_GPIO_OVERRUN
- GEF_GPIO_POLAR_A
- GEF_GPIO_POLAR_B
- GEF_GPIO_TRIG
- GEF_PIC_CPU0_INTR_MASK
- GEF_PIC_CPU0_MCP_MASK
- GEF_PIC_CPU1_INTR_MASK
- GEF_PIC_CPU1_MCP_MASK
- GEF_PIC_INTR_MASK
- GEF_PIC_INTR_STATUS
- GEF_PIC_MCP_MASK
- GEF_PIC_NUM_IRQS
- GEF_WDC_ENABLED_FALSE
- GEF_WDC_ENABLED_SHIFT
- GEF_WDC_ENABLED_TRUE
- GEF_WDC_ENABLE_SHIFT
- GEF_WDC_SERVICE_SHIFT
- GEF_WDOG_FLAG_OPENED
- GELF_ST_VISIBILITY
- GELIC_ALIGN
- GELIC_BUS_ID
- GELIC_CARD_FREE_RUN_COUNT_TIMER
- GELIC_CARD_NUMBER_OF_RX_FRAME
- GELIC_CARD_ONE_TIME_COUNT_TIMER
- GELIC_CARD_PORT_STATUS_CHANGED
- GELIC_CARD_RXINT
- GELIC_CARD_RX_CSUM_DEFAULT
- GELIC_CARD_RX_DESCR_CHAIN_END
- GELIC_CARD_RX_FIFO_FULL_ERR
- GELIC_CARD_RX_FLAGGED_DESCR
- GELIC_CARD_RX_INVALID_DESCR_ERR
- GELIC_CARD_RX_PROTECTION_ERR
- GELIC_CARD_RX_RAM_FULL_ERR
- GELIC_CARD_RX_RESPONCE_ERR
- GELIC_CARD_TXINT
- GELIC_CARD_TX_DESCR_CHAIN_END
- GELIC_CARD_TX_FLAGGED_DESCR
- GELIC_CARD_TX_INVALID_DESCR_ERR
- GELIC_CARD_TX_PROTECTION_ERR
- GELIC_CARD_TX_RAM_FULL_ERR
- GELIC_CARD_TX_RESPONCE_ERR
- GELIC_CARD_TX_SHORT_FRAME_ERR
- GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR
- GELIC_CARD_TX_TRANSFER_END
- GELIC_CARD_WLAN_COMMAND_COMPLETED
- GELIC_CARD_WLAN_EVENT_RECEIVED
- GELIC_DEBUG_PORT
- GELIC_DESCR_DATA_ERROR_CHK_MASK
- GELIC_DESCR_DATA_STATUS_CHK_MASK
- GELIC_DESCR_DMA_BUFFER_FULL
- GELIC_DESCR_DMA_CARDOWNED
- GELIC_DESCR_DMA_CMD_NO_CHKSUM
- GELIC_DESCR_DMA_CMD_TCP_CHKSUM
- GELIC_DESCR_DMA_CMD_UDP_CHKSUM
- GELIC_DESCR_DMA_COMPLETE
- GELIC_DESCR_DMA_FORCE_END
- GELIC_DESCR_DMA_FRAME_END
- GELIC_DESCR_DMA_NOT_IN_USE
- GELIC_DESCR_DMA_PROTECTION_ERROR
- GELIC_DESCR_DMA_RESPONSE_ERROR
- GELIC_DESCR_DMA_STAT_MASK
- GELIC_DESCR_RXALNERR
- GELIC_DESCR_RXCALERR
- GELIC_DESCR_RXCREXERR
- GELIC_DESCR_RXDATAERR
- GELIC_DESCR_RXDMADU
- GELIC_DESCR_RXDRPPKT
- GELIC_DESCR_RXIPCHK
- GELIC_DESCR_RXIPCHKERR
- GELIC_DESCR_RXIPFMTERR
- GELIC_DESCR_RXLSTFBF
- GELIC_DESCR_RXMLTCST
- GELIC_DESCR_RXOVERERR
- GELIC_DESCR_RXRNTERR
- GELIC_DESCR_RXRRECNUM
- GELIC_DESCR_RXTCPCHK
- GELIC_DESCR_RXTCPCHKERR
- GELIC_DESCR_RXVLNPKT
- GELIC_DESCR_RXWTPKT
- GELIC_DESCR_RX_DMA_CHAIN_END
- GELIC_DESCR_SIZE
- GELIC_DESCR_TX_DMA_CHAIN_END
- GELIC_DESCR_TX_DMA_FRAME_TAIL
- GELIC_DESCR_TX_DMA_IKE
- GELIC_DESCR_TX_DMA_NO_CHKSUM
- GELIC_DESCR_TX_DMA_TCP_CHKSUM
- GELIC_DESCR_TX_DMA_UDP_CHKSUM
- GELIC_DESCR_TX_TAIL
- GELIC_DEVICE_ID
- GELIC_EURUS_AUTH_OPEN
- GELIC_EURUS_AUTH_SHARED
- GELIC_EURUS_BSS_ADHOC
- GELIC_EURUS_BSS_INFRA
- GELIC_EURUS_CMD_ASSOC
- GELIC_EURUS_CMD_DISASSOC
- GELIC_EURUS_CMD_GET_COMMON_CFG
- GELIC_EURUS_CMD_GET_RSSI_CFG
- GELIC_EURUS_CMD_GET_SCAN
- GELIC_EURUS_CMD_GET_WEP_CFG
- GELIC_EURUS_CMD_GET_WPA_CFG
- GELIC_EURUS_CMD_MAX_INDEX
- GELIC_EURUS_CMD_SET_COMMON_CFG
- GELIC_EURUS_CMD_SET_WEP_CFG
- GELIC_EURUS_CMD_SET_WPA_CFG
- GELIC_EURUS_CMD_START_SCAN
- GELIC_EURUS_MAX_SCAN
- GELIC_EURUS_OPMODE_11B
- GELIC_EURUS_OPMODE_11BG
- GELIC_EURUS_OPMODE_11G
- GELIC_EURUS_SCAN_CAP_ADHOC
- GELIC_EURUS_SCAN_CAP_INFRA
- GELIC_EURUS_SCAN_CAP_MASK
- GELIC_EURUS_SCAN_SEC_MASK
- GELIC_EURUS_SCAN_SEC_NONE
- GELIC_EURUS_SCAN_SEC_WEP
- GELIC_EURUS_SCAN_SEC_WEP_104
- GELIC_EURUS_SCAN_SEC_WEP_40
- GELIC_EURUS_SCAN_SEC_WEP_MASK
- GELIC_EURUS_SCAN_SEC_WEP_UNKNOWN
- GELIC_EURUS_SCAN_SEC_WPA
- GELIC_EURUS_SCAN_SEC_WPA2
- GELIC_EURUS_SCAN_SEC_WPA_AES
- GELIC_EURUS_SCAN_SEC_WPA_MASK
- GELIC_EURUS_SCAN_SEC_WPA_TKIP
- GELIC_EURUS_SCAN_SEC_WPA_UNKNOWN
- GELIC_EURUS_WEP_SEC_104BIT
- GELIC_EURUS_WEP_SEC_40BIT
- GELIC_EURUS_WEP_SEC_NONE
- GELIC_EURUS_WPA_PSK_BIN
- GELIC_EURUS_WPA_PSK_PASSPHRASE
- GELIC_EURUS_WPA_SEC_NONE
- GELIC_EURUS_WPA_SEC_WPA2_AES_AES
- GELIC_EURUS_WPA_SEC_WPA2_TKIP_AES
- GELIC_EURUS_WPA_SEC_WPA2_TKIP_TKIP
- GELIC_EURUS_WPA_SEC_WPA_AES_AES
- GELIC_EURUS_WPA_SEC_WPA_TKIP_AES
- GELIC_EURUS_WPA_SEC_WPA_TKIP_TKIP
- GELIC_LV1_ETHER_AUTO_NEG
- GELIC_LV1_ETHER_FULL_DUPLEX
- GELIC_LV1_ETHER_LINK_UP
- GELIC_LV1_ETHER_SPEED_10
- GELIC_LV1_ETHER_SPEED_100
- GELIC_LV1_ETHER_SPEED_1000
- GELIC_LV1_ETHER_SPEED_MASK
- GELIC_LV1_GET_CHANNEL
- GELIC_LV1_GET_ETH_PORT_STATUS
- GELIC_LV1_GET_MAC_ADDRESS
- GELIC_LV1_GET_VLAN_ID
- GELIC_LV1_GET_WLAN_CMD_RESULT
- GELIC_LV1_GET_WLAN_EVENT
- GELIC_LV1_PHY_ETHERNET_0
- GELIC_LV1_POST_WLAN_CMD
- GELIC_LV1_SET_NEGOTIATION_MODE
- GELIC_LV1_SET_WOL
- GELIC_LV1_VLAN_RX_ETHERNET_0
- GELIC_LV1_VLAN_RX_WIRELESS
- GELIC_LV1_VLAN_TX_ETHERNET_0
- GELIC_LV1_VLAN_TX_WIRELESS
- GELIC_LV1_WL_EVENT_BEACON_LOST
- GELIC_LV1_WL_EVENT_CONNECTED
- GELIC_LV1_WL_EVENT_DEAUTH
- GELIC_LV1_WL_EVENT_DEVICE_READY
- GELIC_LV1_WL_EVENT_SCAN_COMPLETED
- GELIC_LV1_WL_EVENT_WPA_CONNECTED
- GELIC_LV1_WL_EVENT_WPA_ERROR
- GELIC_LV1_WOL_ADD_MATCH_ADDR
- GELIC_LV1_WOL_DELETE_MATCH_ADDR
- GELIC_LV1_WOL_MAGIC_PACKET
- GELIC_LV1_WOL_MATCH_ALL
- GELIC_LV1_WOL_MATCH_INDIVIDUAL
- GELIC_LV1_WOL_MP_DISABLE
- GELIC_LV1_WOL_MP_ENABLE
- GELIC_MAX_MESSAGE_SIZE
- GELIC_NET_BROADCAST_ADDR
- GELIC_NET_MAX_MTU
- GELIC_NET_MC_COUNT_MAX
- GELIC_NET_MIN_MTU
- GELIC_NET_RXBUF_ALIGN
- GELIC_NET_RX_DESCRIPTORS
- GELIC_NET_TX_DESCRIPTORS
- GELIC_NET_WATCHDOG_TIMEOUT
- GELIC_PORT_ETHERNET_0
- GELIC_PORT_MAX
- GELIC_PORT_WIRELESS
- GELIC_WEP_KEYS
- GELIC_WL_ASSOC_RETRY
- GELIC_WL_ASSOC_STAT_ASSOCIATED
- GELIC_WL_ASSOC_STAT_ASSOCIATING
- GELIC_WL_ASSOC_STAT_DISCONN
- GELIC_WL_BSS_MAX_ENT
- GELIC_WL_CIPHER_AES
- GELIC_WL_CIPHER_NONE
- GELIC_WL_CIPHER_TKIP
- GELIC_WL_CIPHER_WEP
- GELIC_WL_EURUS_PSK_MAX_LEN
- GELIC_WL_PRIV_GET_PSK
- GELIC_WL_PRIV_SET_PSK
- GELIC_WL_SCAN_STAT_GOT_LIST
- GELIC_WL_SCAN_STAT_INIT
- GELIC_WL_SCAN_STAT_SCANNING
- GELIC_WL_STAT_BSSID_SET
- GELIC_WL_STAT_CH_INFO
- GELIC_WL_STAT_CONFIGURED
- GELIC_WL_STAT_ESSID_SET
- GELIC_WL_STAT_WPA_LEVEL_SET
- GELIC_WL_STAT_WPA_PSK_SET
- GELIC_WL_WPA_LEVEL_NONE
- GELIC_WL_WPA_LEVEL_WPA
- GELIC_WL_WPA_LEVEL_WPA2
- GEM0_REF
- GEM0_REF_UNG
- GEM0_RX
- GEM0_TX
- GEM1_REF
- GEM1_REF_UNG
- GEM1_RX
- GEM1_TX
- GEM2_REF
- GEM2_REF_UNG
- GEM2_RX
- GEM2_TX
- GEM3_REF
- GEM3_REF_UNG
- GEM3_RX
- GEM3_TX
- GEMAC_V1
- GEMAC_V2
- GEMBIRD_START_FAULTY_RDESC
- GEMINI_ARB1_BURST_MASK
- GEMINI_ARB1_BURST_SHIFT
- GEMINI_ARB1_DMAC_HIGH_PRIO
- GEMINI_ARB1_GMAC0_HIGH_PRIO
- GEMINI_ARB1_GMAC1_HIGH_PRIO
- GEMINI_ARB1_IDE_HIGH_PRIO
- GEMINI_ARB1_PCI_HIGH_PRIO
- GEMINI_ARB1_PRIO_MASK
- GEMINI_ARB1_RAID_HIGH_PRIO
- GEMINI_ARB1_SECURITY_HIGH_PRIO
- GEMINI_ARB1_TVE_HIGH_PRIO
- GEMINI_ARB1_USB0_HIGH_PRIO
- GEMINI_ARB1_USB1_HIGH_PRIO
- GEMINI_CFGPIN
- GEMINI_CLK_AHB
- GEMINI_CLK_APB
- GEMINI_CLK_CPU
- GEMINI_CLK_GATES
- GEMINI_CLK_GATE_BOOT
- GEMINI_CLK_GATE_DDR
- GEMINI_CLK_GATE_FLASH
- GEMINI_CLK_GATE_GMAC0
- GEMINI_CLK_GATE_GMAC1
- GEMINI_CLK_GATE_IDE
- GEMINI_CLK_GATE_PCI
- GEMINI_CLK_GATE_SATA0
- GEMINI_CLK_GATE_SATA1
- GEMINI_CLK_GATE_SECURITY
- GEMINI_CLK_GATE_TVC
- GEMINI_CLK_GATE_USB0
- GEMINI_CLK_GATE_USB1
- GEMINI_CLK_PCI
- GEMINI_CLK_RTC
- GEMINI_CLK_TVC
- GEMINI_CLK_UART
- GEMINI_CTRL_ENABLE
- GEMINI_CTRL_IRQ_CLR
- GEMINI_CTRL_SHUTDOWN
- GEMINI_DEFAULT_BURST_SIZE
- GEMINI_DEFAULT_PRIO
- GEMINI_GLOBAL_ARB1_CTRL
- GEMINI_GLOBAL_CLOCK_CONTROL
- GEMINI_GLOBAL_MISC_CONTROL
- GEMINI_GLOBAL_MISC_CTRL
- GEMINI_GLOBAL_PCI_DLL_CONTROL
- GEMINI_GLOBAL_PLL_CONTROL
- GEMINI_GLOBAL_SOFT_RESET
- GEMINI_GLOBAL_STATUS
- GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII
- GEMINI_GMAC_IOSEL_GMAC0_GMII
- GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2
- GEMINI_GMAC_IOSEL_MASK
- GEMINI_IDE_IOMUX_MASK
- GEMINI_IDE_IOMUX_MODE0
- GEMINI_IDE_IOMUX_MODE1
- GEMINI_IDE_IOMUX_MODE2
- GEMINI_IDE_IOMUX_MODE3
- GEMINI_IDE_IOMUX_SHIFT
- GEMINI_MUXMODE_0
- GEMINI_MUXMODE_1
- GEMINI_MUXMODE_2
- GEMINI_MUXMODE_3
- GEMINI_NUM_CLKS
- GEMINI_PWC_CTRLREG
- GEMINI_PWC_ID
- GEMINI_PWC_IDREG
- GEMINI_PWC_STATREG
- GEMINI_RESET_APB
- GEMINI_RESET_CIR
- GEMINI_RESET_CPU1
- GEMINI_RESET_DMAC
- GEMINI_RESET_DRAM
- GEMINI_RESET_EXTERN
- GEMINI_RESET_FLASH
- GEMINI_RESET_GLOBAL
- GEMINI_RESET_GMAC0
- GEMINI_RESET_GMAC1
- GEMINI_RESET_GPIO0
- GEMINI_RESET_GPIO1
- GEMINI_RESET_GPIO2
- GEMINI_RESET_IDE
- GEMINI_RESET_INTCON0
- GEMINI_RESET_INTCON1
- GEMINI_RESET_LCD
- GEMINI_RESET_LPC
- GEMINI_RESET_PCI
- GEMINI_RESET_RAID
- GEMINI_RESET_RTC
- GEMINI_RESET_SATA0
- GEMINI_RESET_SATA1
- GEMINI_RESET_SECURITY
- GEMINI_RESET_SSP
- GEMINI_RESET_TIMER
- GEMINI_RESET_TVC
- GEMINI_RESET_UART
- GEMINI_RESET_USB0
- GEMINI_RESET_USB1
- GEMINI_RESET_WDOG
- GEMINI_SATA0_CTRL
- GEMINI_SATA0_STATUS
- GEMINI_SATA1_CTRL
- GEMINI_SATA1_STATUS
- GEMINI_SATA_CTRL_ATAPI_EN
- GEMINI_SATA_CTRL_BUS_WITH_20
- GEMINI_SATA_CTRL_EN
- GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN
- GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN
- GEMINI_SATA_CTRL_PHY_BIST_EN
- GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN
- GEMINI_SATA_CTRL_PHY_FORCE_IDLE
- GEMINI_SATA_CTRL_PHY_FORCE_READY
- GEMINI_SATA_CTRL_SLAVE_EN
- GEMINI_SATA_ID
- GEMINI_SATA_PHY_ID
- GEMINI_SATA_STATUS_BIST_DONE
- GEMINI_SATA_STATUS_BIST_OK
- GEMINI_SATA_STATUS_PHY_READY
- GEMINI_STAT_CIR
- GEMINI_STAT_POWERBUTTON
- GEMINI_STAT_RTC
- GEMTEK_CE
- GEMTEK_CK
- GEMTEK_DA
- GEMTEK_MAX
- GEMTEK_MT
- GEMTEK_NS
- GEMTEK_PLL_OFF
- GEMTEK_STDF_3_125_KHZ
- GEM_ADDR64_OFFSET
- GEM_ADDR64_SIZE
- GEM_ADDSUB_OFFSET
- GEM_ADDSUB_SIZE
- GEM_BF
- GEM_BFEXT
- GEM_BFINS
- GEM_BIT
- GEM_BUG_ON
- GEM_CLK_DIV16
- GEM_CLK_DIV32
- GEM_CLK_DIV48
- GEM_CLK_DIV64
- GEM_CLK_DIV8
- GEM_CLK_DIV96
- GEM_CLK_OFFSET
- GEM_CLK_SIZE
- GEM_CMPAEN_OFFSET
- GEM_CMPAEN_SIZE
- GEM_CMPA_OFFSET
- GEM_CMPA_SIZE
- GEM_CMPBEN_OFFSET
- GEM_CMPBEN_SIZE
- GEM_CMPB_OFFSET
- GEM_CMPB_SIZE
- GEM_CMPCEN_OFFSET
- GEM_CMPCEN_SIZE
- GEM_CMPC_OFFSET
- GEM_CMPC_SIZE
- GEM_DAW64_OFFSET
- GEM_DAW64_SIZE
- GEM_DBW128
- GEM_DBW32
- GEM_DBW64
- GEM_DBWDEF_OFFSET
- GEM_DBWDEF_SIZE
- GEM_DBW_OFFSET
- GEM_DBW_SIZE
- GEM_DCFG1
- GEM_DCFG10
- GEM_DCFG2
- GEM_DCFG3
- GEM_DCFG4
- GEM_DCFG5
- GEM_DCFG6
- GEM_DCFG7
- GEM_DCFG8
- GEM_DDRP_OFFSET
- GEM_DDRP_SIZE
- GEM_DEBUG_BUG_ON
- GEM_DEBUG_DECL
- GEM_DEBUG_EXEC
- GEM_DEBUG_WARN_ON
- GEM_DMACFG
- GEM_DMA_NSEC_OFFSET
- GEM_DMA_NSEC_SIZE
- GEM_DMA_RXVALID_OFFSET
- GEM_DMA_RXVALID_SIZE
- GEM_DMA_SECH_OFFSET
- GEM_DMA_SECH_SIZE
- GEM_DMA_SECL_OFFSET
- GEM_DMA_SECL_SIZE
- GEM_DMA_SEC_MASK
- GEM_DMA_SEC_TOP
- GEM_DMA_SEC_WIDTH
- GEM_DMA_TXVALID_OFFSET
- GEM_DMA_TXVALID_SIZE
- GEM_EFRN
- GEM_EFRSH
- GEM_EFRSL
- GEM_EFTN
- GEM_EFTSH
- GEM_EFTSL
- GEM_ENDIA_DESC_OFFSET
- GEM_ENDIA_DESC_SIZE
- GEM_ENDIA_PKT_OFFSET
- GEM_ENDIA_PKT_SIZE
- GEM_ETHT
- GEM_ETHT2IDX_OFFSET
- GEM_ETHT2IDX_SIZE
- GEM_ETHTCMP_OFFSET
- GEM_ETHTCMP_SIZE
- GEM_ETHTEN_OFFSET
- GEM_ETHTEN_SIZE
- GEM_EXCESSCOLLCNT
- GEM_FBLDO_OFFSET
- GEM_FBLDO_SIZE
- GEM_GBE_OFFSET
- GEM_GBE_SIZE
- GEM_HCLK_RATE
- GEM_HRB
- GEM_HRT
- GEM_IDR
- GEM_IER
- GEM_IMR
- GEM_IP4DST_CMP
- GEM_IP4SRC_CMP
- GEM_IRQCOR_OFFSET
- GEM_IRQCOR_SIZE
- GEM_ISR
- GEM_JML
- GEM_LATECOLLCNT
- GEM_MAX_MTU
- GEM_MAX_TX_LEN
- GEM_MIN_MTU
- GEM_MODULE_NAME
- GEM_MTU_MIN_SIZE
- GEM_MULTICOLLCNT
- GEM_NCFGR
- GEM_NDS_COLLISIONS_OFFSET
- GEM_NDS_RXCRCERR_OFFSET
- GEM_NDS_RXERR_OFFSET
- GEM_NDS_RXFIFOERR_OFFSET
- GEM_NDS_RXFRAMEERR_OFFSET
- GEM_NDS_RXLENERR_OFFSET
- GEM_NDS_RXOVERERR_OFFSET
- GEM_NDS_TXABORTEDERR_OFFSET
- GEM_NDS_TXCARRIERERR_OFFSET
- GEM_NDS_TXERR_OFFSET
- GEM_NDS_TXFIFOERR_OFFSET
- GEM_NSINCR_OFFSET
- GEM_NSINCR_SIZE
- GEM_OCTRXH
- GEM_OCTRXL
- GEM_OCTTXH
- GEM_OCTTXL
- GEM_ORX
- GEM_OTX
- GEM_PBUF_LSO_OFFSET
- GEM_PBUF_LSO_SIZE
- GEM_PCLK_RATE
- GEM_PCSSEL_OFFSET
- GEM_PCSSEL_SIZE
- GEM_PEFRN
- GEM_PEFRSH
- GEM_PEFRSL
- GEM_PEFTN
- GEM_PEFTSH
- GEM_PEFTSL
- GEM_PORT_CMP
- GEM_PTP_TIMER_NAME
- GEM_QUEUE_OFFSET
- GEM_QUEUE_SIZE
- GEM_RBQP
- GEM_RBQPH
- GEM_RBQS
- GEM_RGMII_OFFSET
- GEM_RGMII_SIZE
- GEM_RX1024CNT
- GEM_RX128CNT
- GEM_RX1519CNT
- GEM_RX256CNT
- GEM_RX512CNT
- GEM_RX64CNT
- GEM_RX65CNT
- GEM_RXALIGNCNT
- GEM_RXBDCTRL
- GEM_RXBD_RDBUFF_OFFSET
- GEM_RXBD_RDBUFF_SIZE
- GEM_RXBMS_OFFSET
- GEM_RXBMS_SIZE
- GEM_RXBROADCNT
- GEM_RXBS_OFFSET
- GEM_RXBS_SIZE
- GEM_RXCNT
- GEM_RXCOEN_OFFSET
- GEM_RXCOEN_SIZE
- GEM_RXEXT_OFFSET
- GEM_RXEXT_SIZE
- GEM_RXFCSCNT
- GEM_RXIPCCNT
- GEM_RXJABCNT
- GEM_RXLENGTHCNT
- GEM_RXMULTICNT
- GEM_RXORCNT
- GEM_RXOVRCNT
- GEM_RXPAUSECNT
- GEM_RXRESERRCNT
- GEM_RXSYMBCNT
- GEM_RXTCPCCNT
- GEM_RXTSMODE_OFFSET
- GEM_RXTSMODE_SIZE
- GEM_RXUDPCCNT
- GEM_RXUNDRCNT
- GEM_RX_CSUM_CHECKED_MASK
- GEM_RX_CSUM_IP_ONLY
- GEM_RX_CSUM_IP_TCP
- GEM_RX_CSUM_IP_UDP
- GEM_RX_CSUM_NONE
- GEM_RX_CSUM_OFFSET
- GEM_RX_CSUM_SIZE
- GEM_RX_PKT_BUFF_OFFSET
- GEM_RX_PKT_BUFF_SIZE
- GEM_RX_TYPEID_MATCH_OFFSET
- GEM_RX_TYPEID_MATCH_SIZE
- GEM_SA1B
- GEM_SA1T
- GEM_SA2B
- GEM_SA2T
- GEM_SA3B
- GEM_SA3T
- GEM_SA4B
- GEM_SA4T
- GEM_SCR2CMP_OFFSET
- GEM_SCR2CMP_SIZE
- GEM_SCR2ETH_OFFSET
- GEM_SCR2ETH_SIZE
- GEM_SCRT2
- GEM_SGMIIEN_OFFSET
- GEM_SGMIIEN_SIZE
- GEM_SHOW_DEBUG
- GEM_SNGLCOLLCNT
- GEM_STATS_LEN
- GEM_STAT_TITLE
- GEM_STAT_TITLE_BITS
- GEM_SUBNSINCRH_OFFSET
- GEM_SUBNSINCRH_SIZE
- GEM_SUBNSINCRL_OFFSET
- GEM_SUBNSINCRL_SIZE
- GEM_SUBNSINCR_OFFSET
- GEM_SUBNSINCR_SIZE
- GEM_T1SCR_OFFSET
- GEM_T1SCR_SIZE
- GEM_T2CMPOFST_OFFSET
- GEM_T2CMPOFST_SIZE
- GEM_T2CMPW0
- GEM_T2CMPW1
- GEM_T2CMP_OFFSET
- GEM_T2CMP_SIZE
- GEM_T2COMPOFST_ETYPE
- GEM_T2COMPOFST_IPHDR
- GEM_T2COMPOFST_SOF
- GEM_T2COMPOFST_TCPUDP
- GEM_T2DISMSK_OFFSET
- GEM_T2DISMSK_SIZE
- GEM_T2MASK_OFFSET
- GEM_T2MASK_SIZE
- GEM_T2OFST_OFFSET
- GEM_T2OFST_SIZE
- GEM_T2SCR_OFFSET
- GEM_T2SCR_SIZE
- GEM_TA
- GEM_TBQP
- GEM_TBQPH
- GEM_TI
- GEM_TISUBN
- GEM_TN
- GEM_TN_OFFSET
- GEM_TN_SIZE
- GEM_TRACE
- GEM_TRACE_DUMP
- GEM_TRACE_DUMP_ON
- GEM_TSEC_SIZE
- GEM_TSH
- GEM_TSH_OFFSET
- GEM_TSH_SIZE
- GEM_TSL
- GEM_TSL_OFFSET
- GEM_TSL_SIZE
- GEM_TSU
- GEM_TSU_OFFSET
- GEM_TSU_REF
- GEM_TSU_SIZE
- GEM_TX1024CNT
- GEM_TX128CNT
- GEM_TX1519CNT
- GEM_TX256CNT
- GEM_TX512CNT
- GEM_TX64CNT
- GEM_TX65CNT
- GEM_TXBCCNT
- GEM_TXBDCTRL
- GEM_TXBD_RDBUFF_OFFSET
- GEM_TXBD_RDBUFF_SIZE
- GEM_TXCNT
- GEM_TXCOEN_OFFSET
- GEM_TXCOEN_SIZE
- GEM_TXCSENSECNT
- GEM_TXDEFERCNT
- GEM_TXEXT_OFFSET
- GEM_TXEXT_SIZE
- GEM_TXMCCNT
- GEM_TXPAUSECNT
- GEM_TXPBMS_OFFSET
- GEM_TXPBMS_SIZE
- GEM_TXTSMODE_OFFSET
- GEM_TXTSMODE_SIZE
- GEM_TXURUNCNT
- GEM_TX_FRMLEN_OFFSET
- GEM_TX_FRMLEN_SIZE
- GEM_TX_PKT_BUFF_OFFSET
- GEM_TX_PKT_BUFF_SIZE
- GEM_USRIO
- GEM_VLANEN_OFFSET
- GEM_VLANEN_SIZE
- GEM_VLANPR_OFFSET
- GEM_VLANPR_SIZE
- GEM_WARN_ON
- GEN
- GEN0_CLK_SYNT
- GEN10_CACHE_MODE_SS
- GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
- GEN10_DFR_RATIO_EN_AND_CHICKEN
- GEN10_EU_DISABLE3
- GEN10_EU_DIS_SS_MASK
- GEN10_F2_SS_DIS_MASK
- GEN10_F2_SS_DIS_SHIFT
- GEN10_F2_S_ENA_MASK
- GEN10_F2_S_ENA_SHIFT
- GEN10_FEATURES
- GEN10_GT_NOA_ENABLE
- GEN10_L3BANK_MASK
- GEN10_L3BANK_PAIR_COUNT
- GEN10_L3_CHICKEN_MODE_REGISTER
- GEN10_LR_CONTEXT_RENDER_SIZE
- GEN10_MEDIA_WAKE_RATE_LIMIT
- GEN10_MIRROR_FUSE3
- GEN10_NOA_WRITE_HIGH
- GEN10_PAT_INDEX
- GEN10_PGCTL_VALID_SS_MASK
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK
- GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT
- GEN10_SAMPLER_MODE
- GEN10_SCRATCH_LNCF2
- GEN10_SLICE_PGCTL_ACK
- GEN10_SS01_EU_PGCTL_ACK
- GEN10_SS23_EU_PGCTL_ACK
- GEN11_ARBITRATION_PRIO_ORDER_MASK
- GEN11_AUDIO_CODEC_IRQ
- GEN11_BANK_HASH_ADDR_EXCL_BIT0
- GEN11_BANK_HASH_ADDR_EXCL_MASK
- GEN11_BCS
- GEN11_BCS_RSVD_INTR_MASK
- GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC
- GEN11_BSD2_RING_BASE
- GEN11_BSD3_RING_BASE
- GEN11_BSD4_RING_BASE
- GEN11_BSD_RING_BASE
- GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE
- GEN11_COMMON_SLICE_CHICKEN3
- GEN11_CRYPTO_RSVD_INTR_ENABLE
- GEN11_CRYPTO_RSVD_INTR_MASK
- GEN11_CSB_ENTRIES
- GEN11_CSB_PTR_MASK
- GEN11_CSB_READ_PTR_MASK
- GEN11_CSB_WRITE_PTR_MASK
- GEN11_CSME
- GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
- GEN11_DEFAULT_PAGE_SIZES
- GEN11_DE_HPD_IER
- GEN11_DE_HPD_IIR
- GEN11_DE_HPD_IMR
- GEN11_DE_HPD_IRQ
- GEN11_DE_HPD_ISR
- GEN11_DE_MISC_IRQ
- GEN11_DE_PCH_IRQ
- GEN11_DE_PIPE_A
- GEN11_DE_PIPE_B
- GEN11_DE_PIPE_C
- GEN11_DE_PORT_IRQ
- GEN11_DE_TBT_HOTPLUG_MASK
- GEN11_DE_TC_HOTPLUG_MASK
- GEN11_DISPLAY_INT_CTL
- GEN11_DISPLAY_IRQ
- GEN11_DISPLAY_IRQ_ENABLE
- GEN11_ENABLE_32_PLANE_MODE
- GEN11_ENGINE_CLASS_SHIFT
- GEN11_ENGINE_CLASS_WIDTH
- GEN11_ENGINE_INSTANCE_SHIFT
- GEN11_ENGINE_INSTANCE_WIDTH
- GEN11_EU_DISABLE
- GEN11_EU_DIS_MASK
- GEN11_FEATURES
- GEN11_GACB_PERF_CTRL
- GEN11_GFX_DISABLE_LEGACY_MODE
- GEN11_GFX_MSTR_IRQ
- GEN11_GLBLINVL
- GEN11_GPM_WGBOXPERF_INTR_ENABLE
- GEN11_GPM_WGBOXPERF_INTR_MASK
- GEN11_GRDOM_BLT
- GEN11_GRDOM_FULL
- GEN11_GRDOM_GUC
- GEN11_GRDOM_MEDIA
- GEN11_GRDOM_MEDIA2
- GEN11_GRDOM_MEDIA3
- GEN11_GRDOM_MEDIA4
- GEN11_GRDOM_RENDER
- GEN11_GRDOM_SFC0
- GEN11_GRDOM_SFC1
- GEN11_GRDOM_VECS
- GEN11_GRDOM_VECS2
- GEN11_GTPM
- GEN11_GT_DW0_IRQ
- GEN11_GT_DW1_IRQ
- GEN11_GT_DW_IRQ
- GEN11_GT_INTR_DW
- GEN11_GT_INTR_DW0
- GEN11_GT_INTR_DW1
- GEN11_GT_SLICE_ENABLE
- GEN11_GT_SUBSLICE_DISABLE
- GEN11_GT_S_ENA_MASK
- GEN11_GT_VDBOX_DISABLE_MASK
- GEN11_GT_VEBOX_DISABLE_MASK
- GEN11_GT_VEBOX_DISABLE_SHIFT
- GEN11_GT_VEBOX_VDBOX_DISABLE
- GEN11_GUC
- GEN11_GUC_HOST_INTERRUPT
- GEN11_GUC_SG_INTR_ENABLE
- GEN11_GUC_SG_INTR_MASK
- GEN11_GUNIT
- GEN11_GUNIT_CSME_INTR_ENABLE
- GEN11_GUNIT_CSME_INTR_MASK
- GEN11_GU_MISC_GSE
- GEN11_GU_MISC_IER
- GEN11_GU_MISC_IIR
- GEN11_GU_MISC_IMR
- GEN11_GU_MISC_IRQ
- GEN11_GU_MISC_ISR
- GEN11_HASH_CTRL_BIT0
- GEN11_HASH_CTRL_BIT4
- GEN11_HASH_CTRL_EXCL_BIT0
- GEN11_HASH_CTRL_EXCL_MASK
- GEN11_HASH_CTRL_MASK
- GEN11_HOTPLUG_CTL_ENABLE
- GEN11_HOTPLUG_CTL_LONG_DETECT
- GEN11_HOTPLUG_CTL_NO_DETECT
- GEN11_HOTPLUG_CTL_SHORT_DETECT
- GEN11_HUC_KERNEL_LOAD_INFO
- GEN11_I2M_WRITE_DISABLE
- GEN11_IIR_REG0_SELECTOR
- GEN11_IIR_REG1_SELECTOR
- GEN11_IIR_REG_SELECTOR
- GEN11_INTR_DATA_VALID
- GEN11_INTR_ENGINE_CLASS
- GEN11_INTR_ENGINE_INSTANCE
- GEN11_INTR_ENGINE_INTR
- GEN11_INTR_IDENTITY_REG
- GEN11_INTR_IDENTITY_REG0
- GEN11_INTR_IDENTITY_REG1
- GEN11_KCR
- GEN11_LQSC_CLEAN_EVICT_DISABLE
- GEN11_LR_CONTEXT_RENDER_SIZE
- GEN11_LSN_UNSLCVC
- GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC
- GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC
- GEN11_MASTER_IRQ
- GEN11_MAX_CONTEXT_HW_ID
- GEN11_MCR_SLICE
- GEN11_MCR_SLICE_MASK
- GEN11_MCR_SUBSLICE
- GEN11_MCR_SUBSLICE_MASK
- GEN11_MEDIA_SAMPLER_PG_ENABLE
- GEN11_MFX2_MOCS
- GEN11_MOCS_ENTRIES
- GEN11_NEEDS_FORCE_WAKE
- GEN11_NUM_MOCS_ENTRIES
- GEN11_PCU_IRQ
- GEN11_RCS0
- GEN11_RCS0_RSVD_INTR_MASK
- GEN11_RENDER_COPY_INTR_ENABLE
- GEN11_RPCS_S_CNT_MASK
- GEN11_RPCS_S_CNT_SHIFT
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
- GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT
- GEN11_SAMPLER_ENABLE_HEADLESS_MSG
- GEN11_SCRATCH2
- GEN11_SOFT_SCRATCH
- GEN11_SOFT_SCRATCH_COUNT
- GEN11_STATE_CACHE_REDIRECT_TO_CS
- GEN11_STOLEN_RESERVED_ADDR_MASK
- GEN11_SW_CTX_ID_SHIFT
- GEN11_SW_CTX_ID_WIDTH
- GEN11_TBT1_HOTPLUG
- GEN11_TBT2_HOTPLUG
- GEN11_TBT3_HOTPLUG
- GEN11_TBT4_HOTPLUG
- GEN11_TBT_HOTPLUG
- GEN11_TBT_HOTPLUG_CTL
- GEN11_TC1_HOTPLUG
- GEN11_TC2_HOTPLUG
- GEN11_TC3_HOTPLUG
- GEN11_TC4_HOTPLUG
- GEN11_TC_HOTPLUG
- GEN11_TC_HOTPLUG_CTL
- GEN11_TDL_CLOCK_GATING_FIX_DISABLE
- GEN11_VCS
- GEN11_VCS0_VCS1_INTR_MASK
- GEN11_VCS2_VCS3_INTR_MASK
- GEN11_VCS_SFC_FORCED_LOCK
- GEN11_VCS_SFC_FORCED_LOCK_BIT
- GEN11_VCS_SFC_LOCK_ACK_BIT
- GEN11_VCS_SFC_LOCK_STATUS
- GEN11_VCS_SFC_RESET_BIT
- GEN11_VCS_SFC_USAGE_BIT
- GEN11_VCS_VECS_INTR_ENABLE
- GEN11_VEBOX2_RING_BASE
- GEN11_VEBOX_RING_BASE
- GEN11_VECS
- GEN11_VECS0_VECS1_INTR_MASK
- GEN11_VECS_SFC_FORCED_LOCK
- GEN11_VECS_SFC_FORCED_LOCK_BIT
- GEN11_VECS_SFC_LOCK_ACK
- GEN11_VECS_SFC_LOCK_ACK_BIT
- GEN11_VECS_SFC_RESET_BIT
- GEN11_VECS_SFC_USAGE
- GEN11_VECS_SFC_USAGE_BIT
- GEN11_WDPERF
- GEN11_WOPCM_SIZE
- GEN12_CSB_CTX_VALID
- GEN12_CSB_SW_CTX_ID_MASK
- GEN12_CSR_MAX_FW_SIZE
- GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
- GEN12_CTX_STATUS_SWITCHED_TO_NEW_QUEUE
- GEN12_CTX_SWITCH_DETAIL
- GEN12_FAULT_TLB_DATA0
- GEN12_FAULT_TLB_DATA1
- GEN12_FEATURES
- GEN12_GLOBAL_MOCS
- GEN12_IDLE_CTX_ID
- GEN12_MAX_CONTEXT_HW_ID
- GEN12_PAT_INDEX
- GEN12_RING_FAULT_REG
- GEN12_TBT5_HOTPLUG
- GEN12_TBT6_HOTPLUG
- GEN12_TC5_HOTPLUG
- GEN12_TC6_HOTPLUG
- GEN1_CLK_SYNT
- GEN1_CORE_CLK_FREQ
- GEN1_REASON_SHIFT
- GEN2_CLK_SYNT
- GEN2_CORE_CLK_FREQ
- GEN2_EN_SHIFT
- GEN2_IER
- GEN2_IIR
- GEN2_IMR
- GEN2_INSTDONE
- GEN2_IRQ_INIT
- GEN2_IRQ_RESET
- GEN2_ISR
- GEN2_PCIEPHYADDR
- GEN2_PCIEPHYCTRL
- GEN2_PCIEPHYDATA
- GEN2_READ_FOOTER
- GEN2_READ_HEADER
- GEN2_REASON_SHIFT
- GEN2_WRITE_FOOTER
- GEN2_WRITE_HEADER
- GEN3_B2B_SPAD_OFFSET
- GEN3_BL_CMD_CHECKSUM_SEED
- GEN3_BL_CMD_INITIATE_BL
- GEN3_BL_CMD_LAUNCH_APP
- GEN3_BL_CMD_TERMINATE_BL
- GEN3_BL_CMD_VERIFY_BLOCK
- GEN3_BL_CMD_WRITE_BLOCK
- GEN3_BL_IDLE_FW_MAJ_VER_OFFSET
- GEN3_BL_IDLE_FW_MIN_VER_OFFSET
- GEN3_CLK_SYNT
- GEN3_CORERRSTS_OFFSET
- GEN3_CORE_CLK_FREQ
- GEN3_DB_COUNT
- GEN3_DB_LINK
- GEN3_DB_LINK_BIT
- GEN3_DB_MSIX_VECTOR_COUNT
- GEN3_DB_MSIX_VECTOR_SHIFT
- GEN3_DB_TOTAL_SHIFT
- GEN3_DEVCTRL_OFFSET
- GEN3_DEVSTS_OFFSET
- GEN3_EMBAR0XBASE_OFFSET
- GEN3_EMBAR0_OFFSET
- GEN3_EMBAR1SZ_OFFSET
- GEN3_EMBAR1XBASE_OFFSET
- GEN3_EMBAR1XLMT_OFFSET
- GEN3_EMBAR1_OFFSET
- GEN3_EMBAR2SZ_OFFSET
- GEN3_EMBAR2XBASE_OFFSET
- GEN3_EMBAR2XLMT_OFFSET
- GEN3_EMBAR2_OFFSET
- GEN3_EM_DOORBELL_OFFSET
- GEN3_EM_INT_DISABLE_OFFSET
- GEN3_EM_INT_STATUS_OFFSET
- GEN3_EM_SPAD_OFFSET
- GEN3_EQ_CONTROL_OFF
- GEN3_EQ_CONTROL_OFF_FB_MODE_MASK
- GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK
- GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT
- GEN3_FEATURES
- GEN3_FINGER_NUM
- GEN3_FUSE_MASK
- GEN3_GEN4_EQ_PRESET_INIT
- GEN3_IMBAR1SZ_OFFSET
- GEN3_IMBAR1XBASE_OFFSET
- GEN3_IMBAR1XLMT_OFFSET
- GEN3_IMBAR2SZ_OFFSET
- GEN3_IMBAR2XBASE_OFFSET
- GEN3_IMBAR2XLMT_OFFSET
- GEN3_IM_DOORBELL_OFFSET
- GEN3_IM_INT_DISABLE_OFFSET
- GEN3_IM_INT_STATUS_OFFSET
- GEN3_IM_SPAD_OFFSET
- GEN3_INTVEC_OFFSET
- GEN3_IRQ_INIT
- GEN3_IRQ_RESET
- GEN3_LINK_STATUS_OFFSET
- GEN3_MAX_FINGERS
- GEN3_NTBCNTL_OFFSET
- GEN3_RELATED_OFF
- GEN3_RELATED_OFF_GEN3_EQ_DISABLE
- GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL
- GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK
- GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT
- GEN3_SDVOB
- GEN3_SDVOC
- GEN3_SPAD_COUNT
- GEN3_SPCICMD_OFFSET
- GEN3_UNCERRSTS_OFFSET
- GEN3_USMEMMISS_OFFSET
- GEN4_CORE_CLK_FREQ
- GEN4_FEATURES
- GEN4_HDMIB
- GEN4_HDMIC
- GEN4_INSTDONE1
- GEN4_TIMESTAMP
- GEN5_APP_CONTRACT_REPORT_DESCRIPTOR_SIZE
- GEN5_APP_MAX_OUTPUT_LENGTH
- GEN5_APP_REPORT_DESCRIPTOR_ID
- GEN5_APP_REPORT_DESCRIPTOR_SIZE
- GEN5_BL_MAX_OUTPUT_LENGTH
- GEN5_BL_REPORT_DESCRIPTOR_ID
- GEN5_BL_REPORT_DESCRIPTOR_SIZE
- GEN5_CMD_EXECUTE_PANEL_SCAN
- GEN5_CMD_GET_PARAMETER
- GEN5_CMD_RETRIEVE_PANEL_SCAN
- GEN5_CMD_SET_PARAMETER
- GEN5_FEATURES
- GEN5_OLD_PUSH_BTN_REPORT_ID
- GEN5_PANEL_SCAN_MUTUAL_BASELINE
- GEN5_PANEL_SCAN_MUTUAL_DIFFCOUNT
- GEN5_PANEL_SCAN_MUTUAL_RAW_DATA
- GEN5_PANEL_SCAN_SELF_BASELINE
- GEN5_PANEL_SCAN_SELF_DIFFCOUNT
- GEN5_PANEL_SCAN_SELF_RAW_DATA
- GEN5_PARAMETER_ACT_INTERVL_ID
- GEN5_PARAMETER_ACT_INTERVL_SIZE
- GEN5_PARAMETER_ACT_LFT_INTERVL_ID
- GEN5_PARAMETER_ACT_LFT_INTERVL_SIZE
- GEN5_PARAMETER_DISABLE_PIP_REPORT
- GEN5_PARAMETER_LP_INTRVL_ID
- GEN5_PARAMETER_LP_INTRVL_SIZE
- GEN5_POWER_IDLE_MAX_INTRVL_TIME
- GEN5_POWER_READY_MAX_INTRVL_TIME
- GEN5_POWER_STATE_ACTIVE
- GEN5_POWER_STATE_BTN_ONLY
- GEN5_POWER_STATE_IDLE
- GEN5_POWER_STATE_LOOK_FOR_TOUCH
- GEN5_POWER_STATE_OFF
- GEN5_POWER_STATE_READY
- GEN5_PWC_DATA_ELEMENT_SIZE_MASK
- GEN5_RESP_DATA_STRUCTURE_OFFSET
- GEN5_RETRIEVE_DATA_ELEMENT_SIZE_MASK
- GEN5_RETRIEVE_MUTUAL_PWC_DATA
- GEN5_RETRIEVE_SELF_CAP_PWC_DATA
- GEN5_WA_STORES
- GEN6_AGGRESSIVE_TURBO
- GEN6_BLBUNIT_CLOCK_GATE_DISABLE
- GEN6_BLITTER_ECOSKPD
- GEN6_BLITTER_FBC_NOTIFY
- GEN6_BLITTER_LOCK_SHIFT
- GEN6_BRSYNC
- GEN6_BSD_GO_INDICATOR
- GEN6_BSD_RING_BASE
- GEN6_BSD_RNCID
- GEN6_BSD_SLEEP_FLUSH_DISABLE
- GEN6_BSD_SLEEP_INDICATOR
- GEN6_BSD_SLEEP_MSG_DISABLE
- GEN6_BSD_SLEEP_PSMI_CONTROL
- GEN6_BVESYNC
- GEN6_BVSYNC
- GEN6_CAGF_MASK
- GEN6_CAGF_SHIFT
- GEN6_CORE_CPD_STATE_MASK
- GEN6_CSUNIT_CLOCK_GATE_DISABLE
- GEN6_CURBSYTAVG_MASK
- GEN6_CURIAVG_MASK
- GEN6_CURICONT_MASK
- GEN6_CXT_EXTENDED_SIZE
- GEN6_CXT_PIPELINE_SIZE
- GEN6_CXT_POWER_SIZE
- GEN6_CXT_RENDER_SIZE
- GEN6_CXT_RING_SIZE
- GEN6_CXT_TOTAL_SIZE
- GEN6_DECODE_RC6_VID
- GEN6_DISABLE_CMD_IRQ
- GEN6_DISABLE_DEV_IRQ
- GEN6_ENABLE_CMD_IRQ
- GEN6_ENABLE_DEV_IRQ
- GEN6_ENCODE_RC6_VID
- GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
- GEN6_FEATURES
- GEN6_FENCE_PITCH_SHIFT
- GEN6_FREQUENCY
- GEN6_GAMUNIT_CLOCK_GATE_DISABLE
- GEN6_GDRST
- GEN6_GET_POWER_MODE_INTERVAL
- GEN6_GFXPAUSE
- GEN6_GRDOM_BLT
- GEN6_GRDOM_FULL
- GEN6_GRDOM_MEDIA
- GEN6_GRDOM_RENDER
- GEN6_GRDOM_VECS
- GEN6_GTT_ADDR_ENCODE
- GEN6_GT_CORE_STATUS
- GEN6_GT_GFX_RC6
- GEN6_GT_GFX_RC6_LOCKED
- GEN6_GT_GFX_RC6p
- GEN6_GT_GFX_RC6pp
- GEN6_GT_MODE
- GEN6_GT_PERF_STATUS
- GEN6_GT_THREAD_STATUS_CORE_MASK
- GEN6_GT_THREAD_STATUS_REG
- GEN6_MAX_RX_NUM
- GEN6_MBCTL
- GEN6_MBCTL_BME_UPDATE_ENABLE
- GEN6_MBCTL_BOOT_FETCH_MECH
- GEN6_MBCTL_CTX_FETCH_NEEDED
- GEN6_MBCTL_ENABLE_BOOT_FETCH
- GEN6_MBCTL_MAE_UPDATE_ENABLE
- GEN6_MBCUNIT_SNPCR
- GEN6_MBC_SNPCR_LOW
- GEN6_MBC_SNPCR_MASK
- GEN6_MBC_SNPCR_MAX
- GEN6_MBC_SNPCR_MED
- GEN6_MBC_SNPCR_MIN
- GEN6_MBC_SNPCR_SHIFT
- GEN6_NOSYNC
- GEN6_OACSUNIT_CLOCK_GATE_DISABLE
- GEN6_OFFSET
- GEN6_PCODE_DATA
- GEN6_PCODE_DATA1
- GEN6_PCODE_ERROR_MASK
- GEN6_PCODE_FREQ_IA_RATIO_SHIFT
- GEN6_PCODE_FREQ_RING_RATIO_SHIFT
- GEN6_PCODE_ILLEGAL_CMD
- GEN6_PCODE_MAILBOX
- GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
- GEN6_PCODE_READY
- GEN6_PCODE_READ_D_COMP
- GEN6_PCODE_READ_MIN_FREQ_TABLE
- GEN6_PCODE_READ_RC6VIDS
- GEN6_PCODE_SUCCESS
- GEN6_PCODE_TIMEOUT
- GEN6_PCODE_UNIMPLEMENTED_CMD
- GEN6_PCODE_WRITE_D_COMP
- GEN6_PCODE_WRITE_MIN_FREQ_TABLE
- GEN6_PCODE_WRITE_RC6VIDS
- GEN6_PDE_ADDR_ENCODE
- GEN6_PDE_SHIFT
- GEN6_PDE_VALID
- GEN6_PD_ALIGN
- GEN6_PD_SIZE
- GEN6_PMIER
- GEN6_PMIIR
- GEN6_PMIMR
- GEN6_PMINTRMSK
- GEN6_PMISR
- GEN6_PM_MBOX_EVENT
- GEN6_PM_RPS_EVENTS
- GEN6_PM_RP_DOWN_EI_EXPIRED
- GEN6_PM_RP_DOWN_THRESHOLD
- GEN6_PM_RP_DOWN_TIMEOUT
- GEN6_PM_RP_UP_EI_EXPIRED
- GEN6_PM_RP_UP_THRESHOLD
- GEN6_PM_THERMAL_EVENT
- GEN6_POWER_MODE_ACTIVE
- GEN6_POWER_MODE_BTN_ONLY
- GEN6_POWER_MODE_LP_MODE1
- GEN6_POWER_MODE_LP_MODE2
- GEN6_PSMI_SLEEP_MSG_DISABLE
- GEN6_PTES
- GEN6_PTE_ADDR_ENCODE
- GEN6_PTE_CACHE_LLC
- GEN6_PTE_UNCACHED
- GEN6_PTE_VALID
- GEN6_RBSYNC
- GEN6_RC0
- GEN6_RC1_WAKE_RATE_LIMIT
- GEN6_RC1e_THRESHOLD
- GEN6_RC3
- GEN6_RC6
- GEN6_RC6_THRESHOLD
- GEN6_RC6_WAKE_RATE_LIMIT
- GEN6_RC6p_THRESHOLD
- GEN6_RC6pp_THRESHOLD
- GEN6_RC6pp_WAKE_RATE_LIMIT
- GEN6_RC7
- GEN6_RCCUNIT_CLOCK_GATE_DISABLE
- GEN6_RCGCTL1
- GEN6_RCGCTL2
- GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
- GEN6_RCS_PWR_FSM
- GEN6_RCUBMABDTMR
- GEN6_RCZUNIT_CLOCK_GATE_DISABLE
- GEN6_RC_CONTROL
- GEN6_RC_CTL_EI_MODE
- GEN6_RC_CTL_HW_ENABLE
- GEN6_RC_CTL_RC1e_ENABLE
- GEN6_RC_CTL_RC6_ENABLE
- GEN6_RC_CTL_RC6p_ENABLE
- GEN6_RC_CTL_RC6pp_ENABLE
- GEN6_RC_CTL_RC7_ENABLE
- GEN6_RC_EVALUATION_INTERVAL
- GEN6_RC_IDLE_HYSTERSIS
- GEN6_RC_SLEEP
- GEN6_RC_SLEEP_PSMI_CONTROL
- GEN6_RC_STATE
- GEN6_RC_VIDEO_FREQ
- GEN6_RCn_MASK
- GEN6_READ_FOOTER
- GEN6_READ_HEADER
- GEN6_READ_OC_PARAMS
- GEN6_RETRIEVE_DATA_ID_ATTENURATOR_TRIM
- GEN6_RETRIEVE_DATA_ID_RX_ATTENURATOR_IDAC
- GEN6_RING_FAULT_REG_POSTING_READ
- GEN6_RING_FAULT_REG_READ
- GEN6_RING_FAULT_REG_RMW
- GEN6_RPDEUC
- GEN6_RPDEUCSW
- GEN6_RPDEUHWTC
- GEN6_RPNSWREQ
- GEN6_RPSTAT1
- GEN6_RP_CONTROL
- GEN6_RP_CUR_DOWN
- GEN6_RP_CUR_DOWN_EI
- GEN6_RP_CUR_UP
- GEN6_RP_CUR_UP_EI
- GEN6_RP_DOWN_EI
- GEN6_RP_DOWN_IDLE_AVG
- GEN6_RP_DOWN_IDLE_CONT
- GEN6_RP_DOWN_THRESHOLD
- GEN6_RP_DOWN_TIMEOUT
- GEN6_RP_EI_MASK
- GEN6_RP_ENABLE
- GEN6_RP_IDLE_HYSTERSIS
- GEN6_RP_INTERRUPT_LIMITS
- GEN6_RP_MEDIA_HW_MODE
- GEN6_RP_MEDIA_HW_NORMAL_MODE
- GEN6_RP_MEDIA_HW_TURBO_MODE
- GEN6_RP_MEDIA_IS_GFX
- GEN6_RP_MEDIA_MODE_MASK
- GEN6_RP_MEDIA_SW_MODE
- GEN6_RP_MEDIA_TURBO
- GEN6_RP_PREV_DOWN
- GEN6_RP_PREV_UP
- GEN6_RP_STATE_CAP
- GEN6_RP_STATE_LIMITS
- GEN6_RP_UP_BUSY_AVG
- GEN6_RP_UP_BUSY_CONT
- GEN6_RP_UP_EI
- GEN6_RP_UP_IDLE_MIN
- GEN6_RP_UP_THRESHOLD
- GEN6_RSTCTL
- GEN6_RVESYNC
- GEN6_RVSYNC
- GEN6_SET_POWER_MODE_INTERVAL
- GEN6_STOLEN_RESERVED
- GEN6_STOLEN_RESERVED_128K
- GEN6_STOLEN_RESERVED_1M
- GEN6_STOLEN_RESERVED_256K
- GEN6_STOLEN_RESERVED_512K
- GEN6_STOLEN_RESERVED_ADDR_MASK
- GEN6_STOLEN_RESERVED_ENABLE
- GEN6_STOLEN_RESERVED_SIZE_MASK
- GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
- GEN6_TURBO_DISABLE
- GEN6_UCGCTL1
- GEN6_UCGCTL2
- GEN6_UCGCTL3
- GEN6_VBSYNC
- GEN6_VEBSYNC
- GEN6_VERSYNC
- GEN6_VEVSYNC
- GEN6_VFUNIT_CLOCK_GATE_DISABLE
- GEN6_VRSYNC
- GEN6_VVESYNC
- GEN6_WIZ_HASHING
- GEN6_WIZ_HASHING_16x4
- GEN6_WIZ_HASHING_8x4
- GEN6_WIZ_HASHING_8x8
- GEN6_WIZ_HASHING_MASK
- GEN6_WRITE_FOOTER
- GEN6_WRITE_HEADER
- GEN7_3DPRIM_BASE_VERTEX
- GEN7_3DPRIM_END_OFFSET
- GEN7_3DPRIM_INSTANCE_COUNT
- GEN7_3DPRIM_START_INSTANCE
- GEN7_3DPRIM_START_VERTEX
- GEN7_3DPRIM_VERTEX_COUNT
- GEN7_COMMON_SLICE_CHICKEN1
- GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
- GEN7_CXT_EXTENDED_SIZE
- GEN7_CXT_GT1_SIZE
- GEN7_CXT_POWER_SIZE
- GEN7_CXT_RENDER_SIZE
- GEN7_CXT_RING_SIZE
- GEN7_CXT_SIZE
- GEN7_CXT_TOTAL_SIZE
- GEN7_CXT_VFSTATE_SIZE
- GEN7_DISABLE_DEMAND_PREFETCH
- GEN7_DISABLE_SAMPLER_PREFETCH
- GEN7_DOP_CLOCK_GATE_ENABLE
- GEN7_ERR_INT
- GEN7_FEATURES
- GEN7_FENCE_MAX_PITCH_VAL
- GEN7_FF_DS_SCHED_HS0
- GEN7_FF_DS_SCHED_HS1
- GEN7_FF_DS_SCHED_HW
- GEN7_FF_DS_SCHED_LOAD_BALANCE
- GEN7_FF_SCHED_MASK
- GEN7_FF_SLICE_CS_CHICKEN1
- GEN7_FF_THREAD_MODE
- GEN7_FF_TS_SCHED_HS0
- GEN7_FF_TS_SCHED_HS1
- GEN7_FF_TS_SCHED_HW
- GEN7_FF_TS_SCHED_LOAD_BALANCE
- GEN7_FF_VS_REF_CNT_FFME
- GEN7_FF_VS_SCHED_HS0
- GEN7_FF_VS_SCHED_HS1
- GEN7_FF_VS_SCHED_HW
- GEN7_FF_VS_SCHED_LOAD_BALANCE
- GEN7_GFX_MAX_REQ_COUNT
- GEN7_GFX_PEND_TLB0
- GEN7_GFX_PEND_TLB1
- GEN7_GFX_PRIO_CTRL
- GEN7_GPGPU_DISPATCHDIMX
- GEN7_GPGPU_DISPATCHDIMY
- GEN7_GPGPU_DISPATCHDIMZ
- GEN7_GT_MODE
- GEN7_GT_SCRATCH
- GEN7_GT_SCRATCH_REG_NUM
- GEN7_HALF_SLICE_CHICKEN1
- GEN7_HALF_SLICE_CHICKEN1_GT2
- GEN7_L3AGDIS
- GEN7_L3BANK2X_CLOCK_GATE_DISABLE
- GEN7_L3CDERRST1
- GEN7_L3CDERRST1_BANK_MASK
- GEN7_L3CDERRST1_ENABLE
- GEN7_L3CDERRST1_ROW_MASK
- GEN7_L3CDERRST1_SUBBANK_MASK
- GEN7_L3CNTLREG1
- GEN7_L3CNTLREG2
- GEN7_L3CNTLREG3
- GEN7_L3LOG
- GEN7_L3LOG_SIZE
- GEN7_L3SQCREG1
- GEN7_L3SQCREG4
- GEN7_L3_CHICKEN_MODE_REGISTER
- GEN7_LRA_LIMITS
- GEN7_LRA_LIMITS_REG_NUM
- GEN7_MAX_PS_THREAD_DEP
- GEN7_MEDIA_MAX_REQ_COUNT
- GEN7_MISCCPCTL
- GEN7_MSG_CTL
- GEN7_OABUFFER
- GEN7_OABUFFER_EDGE_TRIGGER
- GEN7_OABUFFER_OVERRUN_DISABLE
- GEN7_OABUFFER_RESUME
- GEN7_OABUFFER_STOP_RESUME_ENABLE
- GEN7_OACONTROL
- GEN7_OACONTROL_CTX_MASK
- GEN7_OACONTROL_ENABLE
- GEN7_OACONTROL_FORMAT_A13
- GEN7_OACONTROL_FORMAT_A13_B8_C8
- GEN7_OACONTROL_FORMAT_A29
- GEN7_OACONTROL_FORMAT_A29_B8_C8
- GEN7_OACONTROL_FORMAT_A45_B8_C8
- GEN7_OACONTROL_FORMAT_B4_C8
- GEN7_OACONTROL_FORMAT_B4_C8_A16
- GEN7_OACONTROL_FORMAT_C4_B8
- GEN7_OACONTROL_FORMAT_SHIFT
- GEN7_OACONTROL_PER_CTX_ENABLE
- GEN7_OACONTROL_TIMER_ENABLE
- GEN7_OACONTROL_TIMER_PERIOD_MASK
- GEN7_OACONTROL_TIMER_PERIOD_SHIFT
- GEN7_OASTATUS1
- GEN7_OASTATUS1_COUNTER_OVERFLOW
- GEN7_OASTATUS1_OABUFFER_OVERFLOW
- GEN7_OASTATUS1_REPORT_LOST
- GEN7_OASTATUS1_TAIL_MASK
- GEN7_OASTATUS2
- GEN7_OASTATUS2_HEAD_MASK
- GEN7_OASTATUS2_MEM_SELECT_GGTT
- GEN7_PARITY_ERROR_BANK
- GEN7_PARITY_ERROR_ROW
- GEN7_PARITY_ERROR_SUBBANK
- GEN7_PARITY_ERROR_VALID
- GEN7_PCODE_ILLEGAL_DATA
- GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
- GEN7_PCODE_TIMEOUT
- GEN7_PIPE_DE_LOAD_SL
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
- GEN7_PTE_CACHE_L3_LLC
- GEN7_RC_CTL_TO_MODE
- GEN7_ROW_CHICKEN2
- GEN7_ROW_CHICKEN2_GT2
- GEN7_ROW_INSTDONE
- GEN7_SAMPLER_INSTDONE
- GEN7_SARCHKMD
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
- GEN7_SC_INSTDONE
- GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
- GEN7_SO_NUM_PRIMS_WRITTEN
- GEN7_SO_NUM_PRIMS_WRITTEN_UDW
- GEN7_SO_PRIM_STORAGE_NEEDED
- GEN7_SO_PRIM_STORAGE_NEEDED_UDW
- GEN7_SO_WRITE_OFFSET
- GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
- GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
- GEN7_STOLEN_RESERVED_1M
- GEN7_STOLEN_RESERVED_256K
- GEN7_STOLEN_RESERVED_ADDR_MASK
- GEN7_STOLEN_RESERVED_SIZE_MASK
- GEN7_TDLUNIT_CLOCK_GATE_DISABLE
- GEN7_TLB_RD_ADDR
- GEN7_UCGCTL4
- GEN7_VDSUNIT_CLOCK_GATE_DISABLE
- GEN7_WA_FOR_GEN7_L3_CONTROL
- GEN7_WA_L3_CHICKEN_MODE
- GEN7_WR_WATERMARK
- GEN7_XCS_WA
- GEN8_3LVL_PDPES
- GEN8_4x4_STC_OPTIMIZATION_DISABLE
- GEN8_AUX_CHANNEL_A
- GEN8_BCS_IRQ_SHIFT
- GEN8_BSD2_RING_BASE
- GEN8_CENTROID_PIXEL_OPT_DIS
- GEN8_CHICKEN_DCPR_1
- GEN8_CSB_ENTRIES
- GEN8_CSB_PTR_MASK
- GEN8_CSB_READ_PTR_MASK
- GEN8_CSB_WRITE_PTR_MASK
- GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
- GEN8_CS_CHICKEN1
- GEN8_CTX_ADDRESSING_MODE_SHIFT
- GEN8_CTX_FORCE_PD_RESTORE
- GEN8_CTX_FORCE_RESTORE
- GEN8_CTX_ID_SHIFT
- GEN8_CTX_ID_WIDTH
- GEN8_CTX_L3LLC_COHERENT
- GEN8_CTX_PRIVILEGE
- GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
- GEN8_CTX_STATUS_ACTIVE_IDLE
- GEN8_CTX_STATUS_COMPLETE
- GEN8_CTX_STATUS_COMPLETED_MASK
- GEN8_CTX_STATUS_ELEMENT_SWITCH
- GEN8_CTX_STATUS_IDLE_ACTIVE
- GEN8_CTX_STATUS_LITE_RESTORE
- GEN8_CTX_STATUS_PREEMPTED
- GEN8_CTX_VALID
- GEN8_DECODE_PTE
- GEN8_DE_EDP_PSR
- GEN8_DE_MISC_GSE
- GEN8_DE_MISC_IER
- GEN8_DE_MISC_IIR
- GEN8_DE_MISC_IMR
- GEN8_DE_MISC_IRQ
- GEN8_DE_MISC_ISR
- GEN8_DE_PCH_IRQ
- GEN8_DE_PIPE_A_IRQ
- GEN8_DE_PIPE_B_IRQ
- GEN8_DE_PIPE_C_IRQ
- GEN8_DE_PIPE_IER
- GEN8_DE_PIPE_IIR
- GEN8_DE_PIPE_IMR
- GEN8_DE_PIPE_IRQ
- GEN8_DE_PIPE_IRQ_FAULT_ERRORS
- GEN8_DE_PIPE_ISR
- GEN8_DE_PORT_IER
- GEN8_DE_PORT_IIR
- GEN8_DE_PORT_IMR
- GEN8_DE_PORT_IRQ
- GEN8_DE_PORT_ISR
- GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE
- GEN8_DOP_CLOCK_GATE_GUC_ENABLE
- GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
- GEN8_DRBREGL
- GEN8_DRBREGU
- GEN8_DRB_VALID
- GEN8_ERRDETBCTRL
- GEN8_EU_DIS0_S0_MASK
- GEN8_EU_DIS0_S1_MASK
- GEN8_EU_DIS0_S1_SHIFT
- GEN8_EU_DIS1_S1_MASK
- GEN8_EU_DIS1_S2_MASK
- GEN8_EU_DIS1_S2_SHIFT
- GEN8_EU_DIS2_S2_MASK
- GEN8_EU_DISABLE0
- GEN8_EU_DISABLE1
- GEN8_EU_DISABLE2
- GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
- GEN8_F2_SS_DIS_MASK
- GEN8_F2_SS_DIS_SHIFT
- GEN8_F2_S_ENA_MASK
- GEN8_F2_S_ENA_SHIFT
- GEN8_FAULT_TLB_DATA0
- GEN8_FAULT_TLB_DATA1
- GEN8_FEATURES
- GEN8_FF_DOP_CLOCK_GATE_DISABLE
- GEN8_FF_DS_REF_CNT_FFME
- GEN8_FUSE2
- GEN8_GAMW_ECO_DEV_RW_IA
- GEN8_GAPSUNIT_CLOCK_GATE_DISABLE
- GEN8_GARBCNTL
- GEN8_GFX_PPGTT_48B
- GEN8_GRDOM_MEDIA2
- GEN8_GTCR
- GEN8_GTCR_INVALIDATE
- GEN8_GT_BCS_IRQ
- GEN8_GT_GUC_IRQ
- GEN8_GT_IER
- GEN8_GT_IIR
- GEN8_GT_IMR
- GEN8_GT_IRQS
- GEN8_GT_ISR
- GEN8_GT_PM_CONFIG
- GEN8_GT_PM_IRQ
- GEN8_GT_RCS_IRQ
- GEN8_GT_SLICE_INFO
- GEN8_GT_VCS0_IRQ
- GEN8_GT_VCS1_IRQ
- GEN8_GT_VECS_IRQ
- GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
- GEN8_HDC_CHICKEN1
- GEN8_HIGH_ADDRESS_BIT
- GEN8_IRQ_INIT_NDX
- GEN8_IRQ_RESET_NDX
- GEN8_L3CNTLREG
- GEN8_L3SQCREG1
- GEN8_L3SQCREG4
- GEN8_L3_LRA_1_GPGPU
- GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
- GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
- GEN8_LQSC_FLUSH_COHERENT_LINES
- GEN8_LQSC_RO_PERF_DIS
- GEN8_LR_CONTEXT_OTHER_SIZE
- GEN8_LR_CONTEXT_RENDER_SIZE
- GEN8_LSLICESTAT_MASK
- GEN8_MASTER_IRQ
- GEN8_MASTER_IRQ_CONTROL
- GEN8_MCR_SELECTOR
- GEN8_MCR_SLICE
- GEN8_MCR_SLICE_MASK
- GEN8_MCR_SUBSLICE
- GEN8_MCR_SUBSLICE_MASK
- GEN8_MISC_CTRL0
- GEN8_OABUFFER
- GEN8_OABUFFER_MEM_SELECT_GGTT
- GEN8_OABUFFER_UDW
- GEN8_OACONTROL
- GEN8_OACTXCONTROL
- GEN8_OACTXID
- GEN8_OAHEADPTR
- GEN8_OAHEADPTR_MASK
- GEN8_OASTATUS
- GEN8_OASTATUS_COUNTER_OVERFLOW
- GEN8_OASTATUS_OABUFFER_OVERFLOW
- GEN8_OASTATUS_OVERRUN_STATUS
- GEN8_OASTATUS_REPORT_LOST
- GEN8_OATAILPTR
- GEN8_OATAILPTR_MASK
- GEN8_OA_COUNTER_ENABLE
- GEN8_OA_COUNTER_RESUME
- GEN8_OA_DEBUG
- GEN8_OA_REPORT_FORMAT_A12
- GEN8_OA_REPORT_FORMAT_A12_B8_C8
- GEN8_OA_REPORT_FORMAT_A36_B8_C8
- GEN8_OA_REPORT_FORMAT_C4_B8
- GEN8_OA_REPORT_FORMAT_SHIFT
- GEN8_OA_SPECIFIC_CONTEXT_ENABLE
- GEN8_OA_TIMER_ENABLE
- GEN8_OA_TIMER_PERIOD_MASK
- GEN8_OA_TIMER_PERIOD_SHIFT
- GEN8_PAGE_SIZE
- GEN8_PCU_IER
- GEN8_PCU_IIR
- GEN8_PCU_IMR
- GEN8_PCU_IRQ
- GEN8_PCU_ISR
- GEN8_PDES
- GEN8_PDE_IPS_64K
- GEN8_PDE_PS_2M
- GEN8_PIPE_CDCLK_CRC_DONE
- GEN8_PIPE_CDCLK_CRC_ERROR
- GEN8_PIPE_CURSOR_FAULT
- GEN8_PIPE_FIFO_UNDERRUN
- GEN8_PIPE_PRIMARY_FAULT
- GEN8_PIPE_PRIMARY_FLIP_DONE
- GEN8_PIPE_SCAN_LINE_EVENT
- GEN8_PIPE_SPRITE_FAULT
- GEN8_PIPE_SPRITE_FLIP_DONE
- GEN8_PIPE_VBLANK
- GEN8_PIPE_VSYNC
- GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC
- GEN8_PORT_DP_A_HOTPLUG
- GEN8_PPAT
- GEN8_PPAT_AGE
- GEN8_PPAT_ELLC_OVERRIDE
- GEN8_PPAT_LLC
- GEN8_PPAT_LLCELLC
- GEN8_PPAT_LLCeLLC
- GEN8_PPAT_UC
- GEN8_PPAT_WB
- GEN8_PPAT_WC
- GEN8_PPAT_WT
- GEN8_PRIVATE_PAT_HI
- GEN8_PRIVATE_PAT_LO
- GEN8_PTE_SHIFT
- GEN8_PUSHBUS_CONTROL
- GEN8_PUSHBUS_ENABLE
- GEN8_PUSHBUS_SHIFT
- GEN8_RC6_CTX_INFO
- GEN8_RCS_IRQ_SHIFT
- GEN8_RC_SEMA_IDLE_MSG_DISABLE
- GEN8_RING_FAULT_ENGINE_ID
- GEN8_RING_FAULT_REG
- GEN8_RING_PDP_LDW
- GEN8_RING_PDP_UDW
- GEN8_ROW_CHICKEN
- GEN8_RPCS_ENABLE
- GEN8_RPCS_EU_MAX_MASK
- GEN8_RPCS_EU_MAX_SHIFT
- GEN8_RPCS_EU_MIN_MASK
- GEN8_RPCS_EU_MIN_SHIFT
- GEN8_RPCS_SS_CNT_ENABLE
- GEN8_RPCS_SS_CNT_MASK
- GEN8_RPCS_SS_CNT_SHIFT
- GEN8_RPCS_S_CNT_ENABLE
- GEN8_RPCS_S_CNT_MASK
- GEN8_RPCS_S_CNT_SHIFT
- GEN8_R_PWR_CLK_STATE
- GEN8_SAMPLER_POWER_BYPASS_DIS
- GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
- GEN8_SDEUNIT_CLOCK_GATE_DISABLE
- GEN8_SELECTIVE_READ_ADDRESSING_ENABLE
- GEN8_SELECTIVE_READ_SLICE_SELECT_MASK
- GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT
- GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK
- GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT
- GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE
- GEN8_SELECTIVE_WRITE_ADDRESS_MASK
- GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT
- GEN8_STATE_ACK
- GEN8_STOLEN_RESERVED_1M
- GEN8_STOLEN_RESERVED_2M
- GEN8_STOLEN_RESERVED_4M
- GEN8_STOLEN_RESERVED_8M
- GEN8_STOLEN_RESERVED_SIZE_MASK
- GEN8_ST_PO_DISABLE
- GEN8_UCGCTL6
- GEN8_VCS0_IRQ_SHIFT
- GEN8_VCS1_IRQ_SHIFT
- GEN8_VECS_IRQ_SHIFT
- GEN8_WD_IRQ_SHIFT
- GEN9LP_GT_PM_CONFIG
- GEN9_AUX_CHANNEL_B
- GEN9_AUX_CHANNEL_C
- GEN9_AUX_CHANNEL_D
- GEN9_BLT_MOCS
- GEN9_CAGF_MASK
- GEN9_CAGF_SHIFT
- GEN9_CCS_TLB_PREFETCH_ENABLE
- GEN9_CLKGATE_DIS_0
- GEN9_CLKGATE_DIS_4
- GEN9_CSFE_CHICKEN1_RCS
- GEN9_CS_DEBUG_MODE1
- GEN9_CTX_PREEMPT_REG
- GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT
- GEN9_DEFAULT_PAGE_SIZES
- GEN9_DE_PIPE_IRQ_FAULT_ERRORS
- GEN9_DG_MIRROR_FIX_ENABLE
- GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE
- GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
- GEN9_ENABLE_GPGPU_PREEMPTION
- GEN9_ENABLE_YV12_BUGFIX
- GEN9_EU_DISABLE
- GEN9_F2_SS_DIS_MASK
- GEN9_F2_SS_DIS_SHIFT
- GEN9_FACTOR_IN_CLR_VAL_HIZ
- GEN9_FEATURES
- GEN9_FFSC_PERCTX_PREEMPT_CTRL
- GEN9_FREQUENCY
- GEN9_FREQ_SCALER
- GEN9_GAMT_ECO_REG_RW_IA
- GEN9_GAPS_TSV_CREDIT_DISABLE
- GEN9_GFX_MOCS
- GEN9_GMBUS_BYTE_COUNT_MAX
- GEN9_GRDOM_GUC
- GEN9_GT_PM_CONFIG
- GEN9_GUC_FW_RESERVED
- GEN9_GUC_WOPCM_OFFSET
- GEN9_HALF_SLICE_CHICKEN5
- GEN9_HALF_SLICE_CHICKEN7
- GEN9_IZ_HASHING
- GEN9_IZ_HASHING_MASK
- GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
- GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
- GEN9_LNCFCMOCS
- GEN9_LP_FEATURES
- GEN9_LR_CONTEXT_RENDER_SIZE
- GEN9_MEDIA_PG_ENABLE
- GEN9_MEDIA_PG_IDLE_HYSTERESIS
- GEN9_MEDIA_POOL_ENABLE
- GEN9_MEDIA_POOL_STATE
- GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
- GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
- GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
- GEN9_MEM_LATENCY_LEVEL_MASK
- GEN9_MFX0_MOCS
- GEN9_MFX1_MOCS
- GEN9_MOCS_ENTRIES
- GEN9_MOCS_SIZE
- GEN9_NUM_MOCS_ENTRIES
- GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS
- GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS
- GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS
- GEN9_OA_DEBUG_INCLUDE_CLK_RATIO
- GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
- GEN9_PBE_COMPRESSED_HASH_SELECTION
- GEN9_PCODE_READ_MEM_LATENCY
- GEN9_PCODE_SAGV_CONTROL
- GEN9_PGCTL_SLICE_ACK
- GEN9_PGCTL_SSA_EU08_ACK
- GEN9_PGCTL_SSA_EU19_ACK
- GEN9_PGCTL_SSA_EU210_ACK
- GEN9_PGCTL_SSA_EU311_ACK
- GEN9_PGCTL_SSB_EU08_ACK
- GEN9_PGCTL_SSB_EU19_ACK
- GEN9_PGCTL_SSB_EU210_ACK
- GEN9_PGCTL_SSB_EU311_ACK
- GEN9_PGCTL_SS_ACK
- GEN9_PG_ENABLE
- GEN9_PIPE_CURSOR_FAULT
- GEN9_PIPE_PLANE1_FAULT
- GEN9_PIPE_PLANE1_FLIP_DONE
- GEN9_PIPE_PLANE2_FAULT
- GEN9_PIPE_PLANE2_FLIP_DONE
- GEN9_PIPE_PLANE3_FAULT
- GEN9_PIPE_PLANE3_FLIP_DONE
- GEN9_PIPE_PLANE4_FAULT
- GEN9_PIPE_PLANE4_FLIP_DONE
- GEN9_PIPE_PLANE_FLIP_DONE
- GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
- GEN9_PREEMPT_3D_OBJECT_LEVEL
- GEN9_PREEMPT_GPGPU_COMMAND_LEVEL
- GEN9_PREEMPT_GPGPU_LEVEL
- GEN9_PREEMPT_GPGPU_LEVEL_MASK
- GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL
- GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
- GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL
- GEN9_PWRGT_DOMAIN_STATUS
- GEN9_PWRGT_MEDIA_STATUS_MASK
- GEN9_PWRGT_RENDER_STATUS_MASK
- GEN9_RCS_FE_FSM2
- GEN9_RENDER_PG_ENABLE
- GEN9_RENDER_PG_IDLE_HYSTERESIS
- GEN9_RHWO_OPTIMIZATION_DISABLE
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
- GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT
- GEN9_SAGV_DISABLE
- GEN9_SAGV_ENABLE
- GEN9_SAGV_IS_DISABLED
- GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR
- GEN9_SLICE_COMMON_ECO_CHICKEN0
- GEN9_SLICE_COMMON_ECO_CHICKEN1
- GEN9_SLICE_PGCTL_ACK
- GEN9_SS01_EU_PGCTL_ACK
- GEN9_SS23_EU_PGCTL_ACK
- GEN9_STATE_ACK_SLICE1
- GEN9_STATE_ACK_SLICE2
- GEN9_STATE_ACK_TDL0
- GEN9_STATE_ACK_TDL1
- GEN9_STATE_ACK_TDL2
- GEN9_STATE_ACK_TDL3
- GEN9_SUBSLICE_TDL_ACK_BITS
- GEN9_TIMESTAMP_OVERRIDE
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK
- GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT
- GEN9_TSG_BARRIER_ACK_DISABLE
- GEN9_VEBOX_MOCS
- GEN9_WM_CHICKEN3
- GEN9_WOPCM_SIZE
- GEN9_XY_FAST_COPY_BLT_CMD
- GENBITSMASK
- GENCLK_DIV
- GENCMDDADDRH
- GENCMDDADDRL
- GENCMDIADDRH
- GENCMDIADDRL
- GENCONF_CLK_GATING_CTRL
- GENCONF_CLK_GATING_CTRL_ND_GATE
- GENCONF_CTRL0
- GENCONF_CTRL0_PORT0_RGMII
- GENCONF_CTRL0_PORT1_RGMII
- GENCONF_CTRL0_PORT1_RGMII_MII
- GENCONF_ND_CLK_CTRL
- GENCONF_ND_CLK_CTRL_EN
- GENCONF_PORT_CTRL0
- GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT
- GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR
- GENCONF_PORT_CTRL0_RX_DATA_SAMPLE
- GENCONF_PORT_CTRL1
- GENCONF_PORT_CTRL1_EN
- GENCONF_PORT_CTRL1_RESET
- GENCONF_SOC_DEVICE_MUX
- GENCONF_SOC_DEVICE_MUX_ECC_CLK_RST
- GENCONF_SOC_DEVICE_MUX_ECC_CORE_RST
- GENCONF_SOC_DEVICE_MUX_NFC_EN
- GENCONF_SOC_DEVICE_MUX_NFC_INT_EN
- GENCONF_SOFT_RESET1
- GENCONF_SOFT_RESET1_GOP
- GENCTL
- GENCTL_IOMAPPED_SCR
- GENELINK_CONNECT_WRITE
- GENELINK_INTERRUPT_INTERVAL
- GENELINK_INTERRUPT_PIPE
- GENENB__BLK_IO_BASE_MASK
- GENENB__BLK_IO_BASE__SHIFT
- GENERAL
- GENERAL_2D_CONTROL_REG
- GENERAL_ACT_REQ
- GENERAL_ASRC_EN_ON
- GENERAL_ASRC_MODE
- GENERAL_ATTEN_OFFSET
- GENERAL_ATTEN_WORD
- GENERAL_BIT_0
- GENERAL_BIT_1
- GENERAL_BIT_2
- GENERAL_BIT_3
- GENERAL_BUS_SETTINGS
- GENERAL_CONFIG
- GENERAL_CTL
- GENERAL_DEBUG
- GENERAL_EVENT_PAYLOAD
- GENERAL_INFORMATION_CONTAINER
- GENERAL_INFO_SET_FW_TX_BOUNDARY
- GENERAL_MAIN_CONTROL
- GENERAL_PWRMGT
- GENERAL_PWRMGT__ACPI_D3_VID_MASK
- GENERAL_PWRMGT__ACPI_D3_VID__SHIFT
- GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK
- GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT
- GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK
- GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT
- GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK
- GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT
- GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK
- GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT
- GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK
- GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT
- GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK
- GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT
- GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK
- GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT
- GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK
- GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT
- GENERAL_PWRMGT__SPARE11_MASK
- GENERAL_PWRMGT__SPARE11__SHIFT
- GENERAL_PWRMGT__SPARE18_MASK
- GENERAL_PWRMGT__SPARE18__SHIFT
- GENERAL_PWRMGT__SPARE27_MASK
- GENERAL_PWRMGT__SPARE27__SHIFT
- GENERAL_PWRMGT__SPARE_MASK
- GENERAL_PWRMGT__SPARE__SHIFT
- GENERAL_PWRMGT__STATIC_PM_EN_MASK
- GENERAL_PWRMGT__STATIC_PM_EN__SHIFT
- GENERAL_PWRMGT__SW_SMIO_INDEX_MASK
- GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT
- GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK
- GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT
- GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK
- GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT
- GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK
- GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT
- GENERAL_REQUEST
- GENERAL_SETTINGS_DRPW_LPD
- GENERAL_STATUS
- GENERAL_TEST_ACCESS
- GENERAL_TEST_ECHO
- GENERAL_UPDATE
- GENERAL_UPIU_REQUEST_SIZE
- GENERATED_MAX_DIV
- GENERATED_SOURCE_MAX
- GENERATE_AMI_CT8
- GENERATE_AMI_CT_16
- GENERATE_CASE
- GENERATE_DEVICE_REMOTE_WAKEUP
- GENERATE_ENUM
- GENERATE_ENUM_ENTRY
- GENERATE_MASK
- GENERATE_PERMUTATIONS_2_EVENTS
- GENERATE_PERMUTATIONS_3_EVENTS
- GENERATE_RECEIVE_PARITY
- GENERATE_RESUME
- GENERATE_STRING
- GENERATE_SW_INTERRUPT
- GENERATE_TESTCASE
- GENERATE_THUNK
- GENERATING_ASM_OFFSETS
- GENERATION_1_2_SETTING
- GENERATION_1_SETTING
- GENERATION_2_3_SETTING
- GENERATION_3_4_SETTING
- GENERATION_ID_FROM_USB_PRODUCT_ID
- GENERATION_MASK
- GENERIC
- GENERIC0_INT_ENABLE
- GENERIC0_INT_STATUS
- GENERIC1_INT_ENABLE
- GENERIC1_INT_STATUS
- GENERIC2_INT_ENABLE
- GENERIC2_INT_STATUS
- GENERICA_STEREOSYNC_SEL
- GENERICA_STEREOSYNC_SEL_D1
- GENERICA_STEREOSYNC_SEL_D2
- GENERICA_STEREOSYNC_SEL_D3
- GENERICA_STEREOSYNC_SEL_D4
- GENERICA_STEREOSYNC_SEL_D5
- GENERICA_STEREOSYNC_SEL_D6
- GENERICA_STEREOSYNC_SEL_RESERVED
- GENERICB_STEREOSYNC_SEL
- GENERICB_STEREOSYNC_SEL_D1
- GENERICB_STEREOSYNC_SEL_D2
- GENERICB_STEREOSYNC_SEL_D3
- GENERICB_STEREOSYNC_SEL_D4
- GENERICB_STEREOSYNC_SEL_D5
- GENERICB_STEREOSYNC_SEL_D6
- GENERICB_STEREOSYNC_SEL_RESERVED
- GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
- GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
- GENERICOBJECT_GLSYNC_ENUM_ID1
- GENERICOBJECT_MXM_OPM_ENUM_ID1
- GENERICOBJECT_PX2_NON_DRIVABLE_ID1
- GENERICOBJECT_PX2_NON_DRIVABLE_ID2
- GENERICOBJECT_STEREO_PIN_ENUM_ID1
- GENERIC_ADC_BATTERY_H
- GENERIC_ALL
- GENERIC_AZ_CONTROLLER_REGISTER_DISABLE
- GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED
- GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET
- GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED
- GENERIC_BITBANG
- GENERIC_CTRL_AUDIO
- GENERIC_CTRL_ENABLE
- GENERIC_CTRL_HBLANK
- GENERIC_CTRL_OTHER
- GENERIC_CTRL_SINGLE
- GENERIC_EDIDS
- GENERIC_ERROR_CODE_MASK
- GENERIC_EVENT_ATTR
- GENERIC_EVENT_PTR
- GENERIC_EXECUTE
- GENERIC_FILESIZE
- GENERIC_FT
- GENERIC_GPIO_REG_LIST
- GENERIC_GPIO_REG_LIST_ENTRY
- GENERIC_HDLC_VERSION
- GENERIC_HOST_SESSION_NUM
- GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK
- GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT
- GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK
- GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT
- GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK
- GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT
- GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK
- GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT
- GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK
- GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT
- GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK
- GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK
- GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT
- GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT
- GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK
- GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK
- GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT
- GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_ACK__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_INT__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_MASK__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DDC_READ_REQUEST_OCCURRED__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK
- GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK
- GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT
- GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK
- GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT
- GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK
- GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT
- GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK
- GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT
- GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK
- GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT
- GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK
- GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT
- GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK
- GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT
- GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK
- GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT
- GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK
- GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT
- GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK
- GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT
- GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL_MASK
- GENERIC_I2C_SPEED__GENERIC_I2C_START_STOP_TIMING_CNTL__SHIFT
- GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK
- GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT
- GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK
- GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT
- GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT
- GENERIC_ID_COUNT
- GENERIC_ID_GLSYNC
- GENERIC_ID_MXM_OPM
- GENERIC_ID_STEREO
- GENERIC_ID_UNKNOWN
- GENERIC_MAPPING
- GENERIC_MASK
- GENERIC_MASK_SH_LIST
- GENERIC_MPP
- GENERIC_MSI_DOMAIN_OPS
- GENERIC_NOP1
- GENERIC_NOP2
- GENERIC_NOP3
- GENERIC_NOP4
- GENERIC_NOP5
- GENERIC_NOP5_ATOMIC
- GENERIC_NOP6
- GENERIC_NOP7
- GENERIC_NOP8
- GENERIC_OBJECT_ID_BRACKET_LAYOUT
- GENERIC_OBJECT_ID_GLSYNC
- GENERIC_OBJECT_ID_MXM_OPM
- GENERIC_OBJECT_ID_NONE
- GENERIC_OBJECT_ID_PX2_NON_DRIVABLE
- GENERIC_OBJECT_ID_STEREO_PIN
- GENERIC_OP_EVT_CHNL
- GENERIC_READ
- GENERIC_REG
- GENERIC_REG_LIST
- GENERIC_RSP
- GENERIC_SMMU
- GENERIC_STAT_COUNT
- GENERIC_STAT_rx_nodesc_trunc
- GENERIC_STAT_rx_noskb_drops
- GENERIC_STEREOSYNC_SEL
- GENERIC_STEREOSYNC_SEL_D1
- GENERIC_STEREOSYNC_SEL_D2
- GENERIC_STEREOSYNC_SEL_D3
- GENERIC_STEREOSYNC_SEL_D4
- GENERIC_STEREOSYNC_SEL_D5
- GENERIC_STEREOSYNC_SEL_D6
- GENERIC_STEREOSYNC_SEL_RESERVED
- GENERIC_SUBSPACE_COMMAND
- GENERIC_SW_STAT
- GENERIC_VALUE
- GENERIC_WRITE
- GENERNAL_CONF_REG
- GENERNAL_STATUS_REG
- GENET_CB
- GENET_EXT_OFF
- GENET_GR_BRIDGE_OFF
- GENET_HAS_40BITS
- GENET_HAS_EXT
- GENET_HAS_MDIO_INTR
- GENET_HAS_MOCA_LINK_DET
- GENET_INTRL2_0_OFF
- GENET_INTRL2_1_OFF
- GENET_IO_MACRO
- GENET_IS_V1
- GENET_IS_V2
- GENET_IS_V3
- GENET_IS_V4
- GENET_IS_V5
- GENET_MAX_MQ_CNT
- GENET_MSG_DEFAULT
- GENET_POWER_CABLE_SENSE
- GENET_POWER_PASSIVE
- GENET_POWER_WOL_MAGIC
- GENET_Q0_PRIORITY
- GENET_Q16_RX_BD_CNT
- GENET_Q16_TX_BD_CNT
- GENET_RBUF_OFF
- GENET_RDMA_REG_OFF
- GENET_SYS_OFF
- GENET_TDMA_REG_OFF
- GENET_UMAC_OFF
- GENET_V1
- GENET_V2
- GENET_V3
- GENET_V4
- GENET_V5
- GENET_VER_FMT
- GENEVE_BASE_HLEN
- GENEVE_CRIT_OPT_TYPE
- GENEVE_DF_INHERIT
- GENEVE_DF_MAX
- GENEVE_DF_SET
- GENEVE_DF_UNSET
- GENEVE_EN_F
- GENEVE_EN_S
- GENEVE_EN_V
- GENEVE_G
- GENEVE_IPV4_HLEN
- GENEVE_IPV6_HLEN
- GENEVE_M
- GENEVE_NETDEV_VER
- GENEVE_N_VID
- GENEVE_S
- GENEVE_UDP_PORT
- GENEVE_V
- GENEVE_VER
- GENEVE_VID_MASK
- GENFC_RD__VSYNC_SEL_R_MASK
- GENFC_RD__VSYNC_SEL_R__SHIFT
- GENFC_WT_1__VSYNC_SEL_W_MASK
- GENFC_WT_1__VSYNC_SEL_W__SHIFT
- GENFC_WT__VSYNC_SEL_W_MASK
- GENFC_WT__VSYNC_SEL_W__SHIFT
- GENFREQSTATUS
- GENFSCON
- GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE
- GENHD_FL_CD
- GENHD_FL_EXT_DEVT
- GENHD_FL_HIDDEN
- GENHD_FL_MEDIA_CHANGE_NOTIFY
- GENHD_FL_NATIVE_CAPACITY
- GENHD_FL_NO_PART_SCAN
- GENHD_FL_REMOVABLE
- GENHD_FL_SUPPRESS_PARTITION_INFO
- GENHD_FL_UP
- GENIATECH_SU3000
- GENIATECH_T220
- GENI_ABORT_DONE
- GENI_CGC_CTRL
- GENI_CLK_CTRL_RO
- GENI_DMA_MODE_EN
- GENI_FORCE_DEFAULT_REG
- GENI_FW_REVISION_RO
- GENI_FW_S_REVISION_RO
- GENI_IF_DISABLE_RO
- GENI_ILLEGAL_CMD
- GENI_INIT_CFG_REVISION
- GENI_M_EVENT_EN
- GENI_M_IRQ_EN
- GENI_OUTPUT_CTRL
- GENI_OVERRUN
- GENI_SER_M_CLK_CFG
- GENI_SER_S_CLK_CFG
- GENI_SE_DMA
- GENI_SE_DMA_AHB_ERR_EN
- GENI_SE_DMA_DONE_EN
- GENI_SE_DMA_EOT_BUF
- GENI_SE_DMA_EOT_EN
- GENI_SE_FIFO
- GENI_SE_I2C
- GENI_SE_I3C
- GENI_SE_INVALID
- GENI_SE_NONE
- GENI_SE_SPI
- GENI_SE_UART
- GENI_SE_VERSION_MAJOR
- GENI_SE_VERSION_MINOR
- GENI_SE_VERSION_STEP
- GENI_S_EVENT_EN
- GENI_S_INIT_CFG_REVISION
- GENI_S_IRQ_EN
- GENI_TIMEOUT
- GENI_UART_CONS_PORTS
- GENI_UART_PORTS
- GENKEY_COUNT
- GENKEY_MODE_PRIVATE
- GENKEY_RSP_SIZE
- GENLMSG_DATA
- GENLMSG_DEFAULT_SIZE
- GENLMSG_PAYLOAD
- GENL_ADMIN_PERM
- GENL_CMD_CAP_DO
- GENL_CMD_CAP_DUMP
- GENL_CMD_CAP_HASPOL
- GENL_DONT_VALIDATE_DUMP
- GENL_DONT_VALIDATE_DUMP_STRICT
- GENL_DONT_VALIDATE_STRICT
- GENL_HDRLEN
- GENL_ID_CTRL
- GENL_ID_PMCRAID
- GENL_ID_VFS_DQUOT
- GENL_MAGIC_FAMILY
- GENL_MAGIC_FAMILY_HDRSZ
- GENL_MAGIC_FUNC_H
- GENL_MAGIC_INCLUDE_FILE
- GENL_MAGIC_STRUCT_H
- GENL_MAGIC_VERSION
- GENL_MAX_ID
- GENL_MIN_ID
- GENL_NAMSIZ
- GENL_SET_ERR_MSG
- GENL_START_ALLOC
- GENL_UNS_ADMIN_PERM
- GENL_doit
- GENL_dumpit
- GENL_mc_group
- GENL_notification
- GENL_op
- GENL_op_init
- GENL_struct
- GENMASK
- GENMASK_ULL
- GENMO_RD__GENMO_MONO_ADDRESS_B_MASK
- GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT
- GENMO_RD__ODD_EVEN_MD_PGSEL_MASK
- GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT
- GENMO_RD__VGA_CKSEL_MASK
- GENMO_RD__VGA_CKSEL__SHIFT
- GENMO_RD__VGA_HSYNC_POL_MASK
- GENMO_RD__VGA_HSYNC_POL__SHIFT
- GENMO_RD__VGA_RAM_EN_MASK
- GENMO_RD__VGA_RAM_EN__SHIFT
- GENMO_RD__VGA_VSYNC_POL_MASK
- GENMO_RD__VGA_VSYNC_POL__SHIFT
- GENMO_WT__GENMO_MONO_ADDRESS_B_MASK
- GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT
- GENMO_WT__ODD_EVEN_MD_PGSEL_MASK
- GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT
- GENMO_WT__VGA_CKSEL_MASK
- GENMO_WT__VGA_CKSEL__SHIFT
- GENMO_WT__VGA_HSYNC_POL_MASK
- GENMO_WT__VGA_HSYNC_POL__SHIFT
- GENMO_WT__VGA_RAM_EN_MASK
- GENMO_WT__VGA_RAM_EN__SHIFT
- GENMO_WT__VGA_VSYNC_POL_MASK
- GENMO_WT__VGA_VSYNC_POL__SHIFT
- GENPD_DEV_CALLBACK
- GENPD_FLAG_ACTIVE_WAKEUP
- GENPD_FLAG_ALWAYS_ON
- GENPD_FLAG_CPU_DOMAIN
- GENPD_FLAG_IRQ_SAFE
- GENPD_FLAG_PM_CLK
- GENPD_FLAG_RPM_ALWAYS_ON
- GENPD_RETRY_MAX_MS
- GENPOOL_OFFSET
- GENRADIX
- GENRADIX_ARY
- GENRADIX_ARY_SHIFT
- GENRADIX_DEPTH_MASK
- GENRADIX_MAX_DEPTH
- GENS0__CRT_INTR_MASK
- GENS0__CRT_INTR__SHIFT
- GENS0__SENSE_SWITCH_MASK
- GENS0__SENSE_SWITCH__SHIFT
- GENS1_1__NO_DISPLAY_MASK
- GENS1_1__NO_DISPLAY__SHIFT
- GENS1_1__PIXEL_READ_BACK_MASK
- GENS1_1__PIXEL_READ_BACK__SHIFT
- GENS1_1__VGA_VSTATUS_MASK
- GENS1_1__VGA_VSTATUS__SHIFT
- GENS1__NO_DISPLAY_MASK
- GENS1__NO_DISPLAY__SHIFT
- GENS1__PIXEL_READ_BACK_MASK
- GENS1__PIXEL_READ_BACK__SHIFT
- GENS1__VGA_VSTATUS_MASK
- GENS1__VGA_VSTATUS__SHIFT
- GENSEL_SEL
- GENSTR
- GENWQE_APP_OFFS
- GENWQE_CARD_FATAL_ERROR
- GENWQE_CARD_NO_MAX
- GENWQE_CARD_RELOAD_BITSTREAM
- GENWQE_CARD_STATE_MAX
- GENWQE_CARD_UNUSED
- GENWQE_CARD_USED
- GENWQE_DBG_DMA
- GENWQE_DBG_REGS
- GENWQE_DBG_UNIT0
- GENWQE_DBG_UNIT1
- GENWQE_DBG_UNIT2
- GENWQE_DBG_UNIT3
- GENWQE_DBG_UNIT4
- GENWQE_DBG_UNIT5
- GENWQE_DBG_UNIT6
- GENWQE_DBG_UNIT7
- GENWQE_DBG_UNITS
- GENWQE_DDCB_MAX
- GENWQE_DDCB_SOFTWARE_TIMEOUT
- GENWQE_DEVNAME
- GENWQE_EXECUTE_DDCB
- GENWQE_EXECUTE_RAW_DDCB
- GENWQE_EXTENDED_DIAG_SELECTOR
- GENWQE_FFDC_REGS
- GENWQE_GET_CARD_STATE
- GENWQE_HEALTH_CHECK_INTERVAL
- GENWQE_HSU_OFFS
- GENWQE_INJECT_BUS_RESET_FAILURE
- GENWQE_INJECT_GFIR_FATAL
- GENWQE_INJECT_GFIR_INFO
- GENWQE_INJECT_HARDWARE_FAILURE
- GENWQE_IOC_CODE
- GENWQE_KILL_TIMEOUT
- GENWQE_MAPPING_RAW
- GENWQE_MAPPING_SGL_PINNED
- GENWQE_MAPPING_SGL_TEMP
- GENWQE_MAX_FUNCS
- GENWQE_MAX_MINOR
- GENWQE_MAX_UNITS
- GENWQE_MAX_VFS
- GENWQE_MSI_IRQS
- GENWQE_PF_JOBTIMEOUT_MSEC
- GENWQE_PIN_MEM
- GENWQE_POLLING_ENABLED
- GENWQE_READ_REG16
- GENWQE_READ_REG32
- GENWQE_READ_REG64
- GENWQE_REQU_ENQUEUED
- GENWQE_REQU_FINISHED
- GENWQE_REQU_NEW
- GENWQE_REQU_STATE_MAX
- GENWQE_REQU_TAPPED
- GENWQE_SLU_ARCH_REQ
- GENWQE_SLU_OFFS
- GENWQE_SLU_READ
- GENWQE_SLU_UPDATE
- GENWQE_TYPE_ALTERA_230
- GENWQE_TYPE_ALTERA_530
- GENWQE_TYPE_ALTERA_A4
- GENWQE_TYPE_ALTERA_A7
- GENWQE_UID_OFFS
- GENWQE_UNPIN_MEM
- GENWQE_VF_JOBTIMEOUT_MSEC
- GENWQE_WRITE_REG16
- GENWQE_WRITE_REG32
- GENWQE_WRITE_REG64
- GEN_74X164_NUMBER_GPIOS
- GEN_ASSERTERR
- GEN_BINARY_RMWcc
- GEN_BINARY_RMWcc_5
- GEN_BINARY_RMWcc_6
- GEN_BINARY_SUFFIXED_RMWcc
- GEN_BOOT
- GEN_BOOT_DAT
- GEN_BTB_FLUSH
- GEN_BUFF_TYPE
- GEN_CMD
- GEN_CMD_CODE
- GEN_CMD_EMPTY
- GEN_CMD_FULL
- GEN_CNT
- GEN_CNTL_0
- GEN_CONF
- GEN_CRC
- GEN_CTL
- GEN_DECDIV
- GEN_DECINV
- GEN_DECOVF
- GEN_DEFAULT_PAGE_SIZES
- GEN_DEFPAR
- GEN_DO_PATCH
- GEN_DRV_CMD_HANDLER
- GEN_ELF_ARCH
- GEN_ELF_CLASS
- GEN_ELF_ENDIAN
- GEN_ELF_TEXT_OFFSET
- GEN_ERROR_INTR
- GEN_EVT_CODE
- GEN_FB_TIME_OUT
- GEN_FIFO_STAT_REG
- GEN_FLTDIV
- GEN_FLTINE
- GEN_FLTINV
- GEN_FLTOVF
- GEN_FLTUND
- GEN_FW_RANGE
- GEN_IH_INT_EN
- GEN_INDEX_PIX
- GEN_INDEX_PIX_ADDR
- GEN_INTDIV
- GEN_INTOVF
- GEN_INTR_MC
- GEN_INTR_RXDMA
- GEN_INTR_RXMAC
- GEN_INTR_RXPIC
- GEN_INTR_RXTRAFFIC
- GEN_INTR_RXXGXS
- GEN_INTR_TXDMA
- GEN_INTR_TXMAC
- GEN_INTR_TXPIC
- GEN_INTR_TXTRAFFIC
- GEN_INTR_TXXGXS
- GEN_INT_CNTL
- GEN_INT_STATUS
- GEN_IP_V4_CHECKSUM
- GEN_IV
- GEN_IV_SHIFT
- GEN_LONG_WRITE
- GEN_LW_TX_LP
- GEN_MASK
- GEN_MASK_BITS
- GEN_MAX_SLICES
- GEN_MAX_SUBSLICES
- GEN_MLME_EXT_HANDLER
- GEN_MP_IOCTL_SUBCODE
- GEN_NMI
- GEN_NULPTRERR
- GEN_OFF
- GEN_OID_LEDCONFIG
- GEN_OID_LINKSTATE
- GEN_OID_MACADDRESS
- GEN_OID_MIBOP
- GEN_OID_OPTIONS
- GEN_OID_WATCHDOG
- GEN_OPPT1
- GEN_OUTPUT_AB
- GEN_OVR_OUTPUT_EN
- GEN_PLD_R_EMPTY
- GEN_PLD_R_FULL
- GEN_PLD_W_EMPTY
- GEN_PLD_W_FULL
- GEN_PMU_FORMAT_ATTR
- GEN_POWER_ON
- GEN_PWR_VDEC_1
- GEN_PWR_VPU_HDMI
- GEN_PWR_VPU_HDMI_ISO
- GEN_RANGERR
- GEN_RD_CMD_BUSY
- GEN_READ_0
- GEN_READ_1
- GEN_READ_2
- GEN_READ_DATA_AVAIL
- GEN_READ_WB_REG_CASES
- GEN_REG_OFFSH
- GEN_REQUEST64
- GEN_RESET
- GEN_RESET_CNTL
- GEN_RGB
- GEN_ROPRAND
- GEN_SCI
- GEN_SELECTOR_INDEX_MASK
- GEN_SET_KSTACK
- GEN_SET_SEG
- GEN_SGMII_1_25GBPS
- GEN_SGMII_3_125GBPS
- GEN_SHORT_WRITE_0
- GEN_SHORT_WRITE_1
- GEN_SHORT_WRITE_2
- GEN_SMI
- GEN_SR_0P_TX_LP
- GEN_SR_1P_TX_LP
- GEN_SR_2P_TX_LP
- GEN_SSEU_STRIDE
- GEN_START
- GEN_STAT
- GEN_STKOVF
- GEN_STOP
- GEN_STRLENERR
- GEN_SUBRNG
- GEN_SUBRNG1
- GEN_SUBRNG2
- GEN_SUBRNG3
- GEN_SUBRNG4
- GEN_SUBRNG5
- GEN_SUBRNG6
- GEN_SUBRNG7
- GEN_SUBSTRERR
- GEN_SW_0P_TX_LP
- GEN_SW_1P_TX_LP
- GEN_SW_2P_TX_LP
- GEN_SYNTH2_3_CLK_MASK
- GEN_SYNTH2_3_CLK_SHIFT
- GEN_TCP_UDP_CHECKSUM
- GEN_TCP_UDP_CHK_FULL
- GEN_TEST_CNTL
- GEN_UNARY_RMWcc
- GEN_UNARY_RMWcc_3
- GEN_UNARY_RMWcc_4
- GEN_UNARY_SUFFIXED_RMWcc
- GEN_WRITE_WB_REG_CASES
- GEN_retl_g1_8
- GEN_retl_o2_1
- GEN_retl_o2_4
- GEN_retl_o4_1
- GEODEWDT_HZ
- GEODEWDT_MAX_SECONDS
- GEODEWDT_SCALE
- GEODE_RNG_DATA_REG
- GEODE_RNG_STATUS_REG
- GEOGRAPHY_ALLOWED
- GEOM
- GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE
- GEOMETRY_DESC_PARAM_DATA_ORDER
- GEOMETRY_DESC_PARAM_DEV_CAP
- GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC
- GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_LEN
- GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE
- GEOMETRY_DESC_PARAM_MAX_NUM_CTX
- GEOMETRY_DESC_PARAM_MAX_NUM_LUN
- GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE
- GEOMETRY_DESC_PARAM_MEM_TYPES
- GEOMETRY_DESC_PARAM_MIN_BLK_SIZE
- GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE
- GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE
- GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE
- GEOMETRY_DESC_PARAM_RPMB_RW_SIZE
- GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR
- GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS
- GEOMETRY_DESC_PARAM_SEC_RM_TYPES
- GEOMETRY_DESC_PARAM_SEG_SIZE
- GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE
- GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE
- GEOMETRY_DESC_PARAM_TYPE
- GEOMETRY_ROUND_NEAREST
- GEOMETRY_ROUND_TRUNC
- GEO_NO_INFO
- GEO_TX_POWER_LIMIT
- GEO_WMM_ETSI_5GHZ_INFO
- GEPHY_MAC_SEL
- GEP_CTRL
- GEP_FDXD
- GEP_FLED
- GEP_HRST
- GEP_INIT
- GEP_LNP
- GEP_MODE
- GEP_PHYL
- GEP_SDET
- GEP_SLNK
- GERROR_CMDQ_ERR
- GERROR_ERR_MASK
- GERROR_EVTQ_ABT_ERR
- GERROR_MSI_CMDQ_ABT_ERR
- GERROR_MSI_EVTQ_ABT_ERR
- GERROR_MSI_GERROR_ABT_ERR
- GERROR_MSI_INDEX
- GERROR_MSI_PRIQ_ABT_ERR
- GERROR_PRIQ_ABT_ERR
- GERROR_SFM_ERR
- GESTURE
- GESTURE_CODE_NO
- GESTURE_CODE_OFFSET
- GESTURE_DISABLE
- GESTURE_ENABLE
- GESTURE_MSK
- GESTURE_OFFSET
- GESTURE_PINCH
- GESTURE_ROTATE_L
- GESTURE_ROTATE_R
- GESTURE_SPREAD
- GET
- GET16
- GET16_A
- GET32
- GET32_0
- GET32_1
- GET32_2
- GET32_3
- GET32_A
- GET64
- GET64_A
- GETADAP
- GETALL
- GETBATTERYDATA
- GETBITS
- GETBITSTR
- GETBRIGHTNESS
- GETBYTE
- GETC
- GETCAP
- GETCC_TRAP
- GETCONTRAST
- GETDEVICEPARAMETERS
- GETHER
- GETHER0
- GETHER1
- GETHER2
- GETHER_MAX_ETH_FRAME_LEN
- GETID
- GETIREG
- GETNCNT
- GETOPT_STR
- GETPID
- GETPORT
- GETPSR_TRAP
- GETREG
- GETSCANKEYCODE
- GETSCL_BIT
- GETSDL_BIT
- GETSIGN
- GETSIZE
- GETSTCNT
- GETSUPP_TXBASTREAMS
- GETTICK
- GETTOUCHSAMPLES
- GETTYPE
- GETU16
- GETU32
- GETV
- GETVAL
- GETVXRES
- GETVYRES
- GETWORD
- GETZCNT
- GET_16
- GET_16BE
- GET_16LE
- GET_32
- GET_32BE
- GET_32BIT_NET_STATS
- GET_32LE
- GET_64
- GET_64BE
- GET_64BIT
- GET_64BIT_NET_STATS
- GET_64BIT_NET_STATS64
- GET_64LE
- GET_7BIT_ADDR
- GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER
- GET_8723B_C2H_TX_RPT_RETRY_OVER
- GET_8723B_H2CCMD_PWRMODE_PARM_MODE
- GET_8821AE_H2CCMD_PWRMODE_PARM_MODE
- GET_88E_H2CCMD_PWRMODE_PARM_MODE
- GET_8BIT_ADDR
- GET_8PSK_CONFIG
- GET_92E_H2CCMD_PWRMODE_PARM_MODE
- GET_ABID
- GET_ABS_X
- GET_ABS_Y
- GET_ABURST
- GET_ACK
- GET_ACTIVATION
- GET_ACTLR
- GET_ADAPTER
- GET_ADAPTER_PROPERTIES
- GET_ADAP_INFO
- GET_AEQ_ELEM
- GET_AE_CSR
- GET_AFE
- GET_AFF
- GET_AFFD
- GET_AFTER_BITS
- GET_AFULL
- GET_AGC
- GET_AGENT1ID
- GET_AGENTID
- GET_AINNERSHARED
- GET_AINST
- GET_ALEN
- GET_ALIAS
- GET_ALOCK
- GET_AMEMTYPE
- GET_AMID
- GET_AM_CLASS
- GET_APF
- GET_APIC_DELIVERY_MODE
- GET_APIC_DEST_FIELD
- GET_APIC_LOGICAL_ID
- GET_APIC_MAXLVT
- GET_APIC_TIMER_BASE
- GET_APIC_VERSION
- GET_APID
- GET_APRIV
- GET_APROTNS
- GET_ARG
- GET_ARP_PKT_LLC_TYPE
- GET_ARP_PKT_OPERATION
- GET_ARP_PKT_SENDER_IP_ADDR
- GET_ARP_PKT_SENDER_MAC_ADDR
- GET_ARP_PKT_TARGET_IP_ADDR
- GET_ARP_PKT_TARGET_MAC_ADDR
- GET_ARRAY_INFO
- GET_ASHARED
- GET_ATID
- GET_ATTR
- GET_AUX0
- GET_AUX1
- GET_AVG
- GET_AVG_PERF_COUNTER
- GET_AWRITE
- GET_A_BUS_DROP
- GET_A_BUS_REQ
- GET_A_SUSPEND_REQ
- GET_BARS
- GET_BATCHRSP
- GET_BE
- GET_BFBCR
- GET_BFBDFE
- GET_BFBSFE
- GET_BIOS
- GET_BIOS_PVT_DATA
- GET_BIT
- GET_BITFIELD
- GET_BITMAP_FILE
- GET_BITMASK
- GET_BITS
- GET_BITS_LE
- GET_BITS_SHIFT
- GET_BIT_VALUE
- GET_BLKOFF_FROM_SEG0
- GET_BLK_PTR_FROM_EQE
- GET_BLOCK_2
- GET_BLOCK_4
- GET_BLOCK_CREATE
- GET_BLOCK_NO_CREATE
- GET_BLOCK_NO_DANGLE
- GET_BLOCK_NO_HOLE
- GET_BLOCK_NO_IMUX
- GET_BLOCK_READ_DIRECT
- GET_BMIC_BUS
- GET_BMIC_DRIVE_NUMBER
- GET_BMIC_LEVEL_TWO_TARGET
- GET_BOOTLOADERMODE
- GET_BPMEMTYPE
- GET_BPMTCFG
- GET_BPRCISH
- GET_BPRCNSH
- GET_BPRCOSH
- GET_BPSHCFG
- GET_BSS_ROLE
- GET_BUS_TYPE
- GET_BUS_WIDTH
- GET_BUS_WORD
- GET_BYPASS
- GET_BYPASSD
- GET_BYTE
- GET_B_BUS_REQ
- GET_C2H_CMD_ID
- GET_C2H_DATA_PTR
- GET_C2H_SEQ
- GET_CALLBACK_DATA
- GET_CAP
- GET_CAP_CSR
- GET_CBACR_N
- GET_CBNDX
- GET_CBVMID
- GET_CCX_REPORT_SEQNUM
- GET_CCX_REPORT_STATUS
- GET_CELL
- GET_CEQ_ELEM
- GET_CFCFG
- GET_CFEIE
- GET_CFERE
- GET_CFG
- GET_CH
- GET_CHNL_CLASS
- GET_CHROM_CTL
- GET_CID
- GET_CID_ADDR
- GET_CID_NUM
- GET_CIE_WATCHDOG
- GET_CLIENTPD
- GET_CLKRC_DIV
- GET_CLUSTER_FROM_SECTOR
- GET_CLUSTER_MODE
- GET_CMD_SENSE_LEN
- GET_CMD_SENSE_PTR
- GET_CMD_SP
- GET_CNTR
- GET_COEX_RESP_BT_SCAN_TYPE
- GET_COMMAND_PACKET_FRAG_THRESHOLD
- GET_COMMAND_TABLE_COMMANDSET_REVISION
- GET_COMMAND_TABLE_PARAMETER_REVISION
- GET_COMM_PREFERRED_SETTINGS
- GET_COMPACT_SGD_SIZE
- GET_COMP_CODE
- GET_CONFIG
- GET_CONFIGURATION
- GET_CONFIGURATION_DESCRIPTOR
- GET_CONTEXT
- GET_CONTEXTIDR
- GET_CONTEXTIDR_ASID
- GET_CONTEXTIDR_PROCID
- GET_CONTEXT_DATA
- GET_CONTEXT_FIELD
- GET_CONTROL_BYTE
- GET_CONTROL_WORD
- GET_CORE
- GET_COUNTERID
- GET_COUNT_CYCLES
- GET_CQ_DESC
- GET_CR
- GET_CR2_INTO
- GET_CR2_INTO_AX
- GET_CRC_TIME_OUT
- GET_CR_HUME
- GET_CR_TLBIALLCFG
- GET_CSOURCE
- GET_CTR
- GET_CTX_REG
- GET_CTX_TLBIALL
- GET_CUR
- GET_CURRENT
- GET_CURRENT_ARG_TYPE
- GET_CURRENT_PGD
- GET_CURRENT_THREAD_INFO
- GET_CURR_AEQ_ELEM
- GET_CURR_CEQ_ELEM
- GET_CURR_PBLOCK_DESC_FROM_CORE
- GET_CVID_CHIP_TYPE
- GET_CVID_CUT_VERSION
- GET_CVID_IC_TYPE
- GET_CVID_MANUFACTUER
- GET_CVID_RF_TYPE
- GET_CVID_ROM_VERSION
- GET_DATA_TABLE_MAJOR_REVISION
- GET_DATA_TABLE_MINOR_REVISION
- GET_DCDEE
- GET_DDP_PARAMS
- GET_DDRC_EVENTID
- GET_DEBUG_DATA_CONTROL
- GET_DEF
- GET_DENTRY_SLOTS
- GET_DESCRIPTORS_CONTROL
- GET_DESCRIPTOR_BUFSIZE
- GET_DESCRIPTOR_TRIES
- GET_DEV
- GET_DEVICE_DESCRIPTOR
- GET_DEVICE_ID
- GET_DEVICE_QUALIFIER
- GET_DEVICE_STATUS
- GET_DEVID
- GET_DEVID_MASK
- GET_DEVRXMCSMAP
- GET_DEVTXMCSMAP
- GET_DEV_BASE_VERSION
- GET_DEV_CTRL_MAXPL
- GET_DEV_CTRL_MRRS
- GET_DEV_CUSTOM_VERSION
- GET_DEV_SPEED
- GET_DEV_STATUS
- GET_DFC
- GET_DINFO
- GET_DIR
- GET_DISK_INFO
- GET_DISPLAY_SURFACE_SIZE_PARAMETERS
- GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
- GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
- GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
- GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
- GET_DISTANCE_TO_VBLANKSTART
- GET_DMA_CMD
- GET_DMA_COUNT
- GET_DMA_MR
- GET_DMA_SUB_CMD
- GET_DMA_T
- GET_DNA
- GET_DNLV2PA
- GET_DOMID
- GET_DOMID_MASK
- GET_DOT11D_INFO
- GET_DPM_CUR_FREQ
- GET_DPSIZC
- GET_DPSIZR
- GET_DRA_CLASS
- GET_DRA_PACKAGE
- GET_DRIVER_BUFFER_PROPERTIES
- GET_DRIVER_VER
- GET_DSP_COPYRIGHT
- GET_DSP_VERSION
- GET_DUMP
- GET_DURATION
- GET_DURATION_RES
- GET_DVI_SIZE_BY_SYSTEM_BIOS
- GET_DVI_SIZE_BY_VGA_BIOS
- GET_DVI_SZIE_BY_HW_STRAPPING
- GET_EAR
- GET_EEPROM_ADDR
- GET_EEPROM_EFUSE_PRIV
- GET_EE_VALUE
- GET_EFI_CONFIG_TABLE
- GET_EFUSE_CURRENT_SIZE
- GET_EFUSE_HW_CAP_ANT_NUM
- GET_EFUSE_HW_CAP_BW
- GET_EFUSE_HW_CAP_HCI
- GET_EFUSE_HW_CAP_NSS
- GET_EFUSE_HW_CAP_PTCL
- GET_EFUSE_MAX_SIZE
- GET_EFUSE_OFFSET
- GET_EFUSE_WORD_EN
- GET_EMBEDDED_INFO
- GET_ENCRY_ALGO
- GET_ENDIAN
- GET_ENDPOINT_STATUS
- GET_END_PTR
- GET_ENGINE_CLOCK_PARAMETERS
- GET_ENGINE_CLOCK_PS_ALLOCATION
- GET_ENTRY
- GET_EP_CTX_STATE
- GET_EP_STREAM_CTL
- GET_EQ_ELEMENT
- GET_EQ_NUM_ELEMS_IN_PG
- GET_EQ_NUM_PAGES
- GET_ERR_FROM_TABLE
- GET_ESID
- GET_ESID_1T
- GET_ESR
- GET_ESRRESTORE
- GET_ESR_MULTI
- GET_ESYNR0
- GET_ESYNR0_ABID
- GET_ESYNR0_AMID
- GET_ESYNR0_APID
- GET_ESYNR0_ATID
- GET_ESYNR0_AVMID
- GET_ESYNR1
- GET_ESYNR1_ABURST
- GET_ESYNR1_AC
- GET_ESYNR1_AFULL
- GET_ESYNR1_AINNERSHARED
- GET_ESYNR1_AINST
- GET_ESYNR1_ALEN
- GET_ESYNR1_ALOCK
- GET_ESYNR1_AMEMTYPE
- GET_ESYNR1_AOOO
- GET_ESYNR1_APRIV
- GET_ESYNR1_APROTNS
- GET_ESYNR1_ASHARED
- GET_ESYNR1_ASIZE
- GET_ESYNR1_AWRITE
- GET_ESYNR1_DCD
- GET_EVENTID
- GET_EVENT_KEY
- GET_EVENT_STATUS_NOTIFICATION
- GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
- GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
- GET_EXT_CAPABILITY_ELE_BSS_COEXIST
- GET_FAN_AUTO_BITFIELD
- GET_FAR
- GET_FAULT
- GET_FAULTINFO_FROM_MC
- GET_FAULT_AFF
- GET_FAULT_APF
- GET_FAULT_HTWDEEF
- GET_FAULT_HTWSEEF
- GET_FAULT_MHF
- GET_FAULT_SL
- GET_FAULT_SS
- GET_FAULT_TF
- GET_FAULT_TLBMF
- GET_FBD_FAT_IDX
- GET_FBD_NF_IDX
- GET_FIELD
- GET_FIELD2
- GET_FIFO_SLOTS
- GET_FIRMWARE_HDR_CATEGORY
- GET_FIRMWARE_HDR_DATE
- GET_FIRMWARE_HDR_FUNCTION
- GET_FIRMWARE_HDR_HOUR
- GET_FIRMWARE_HDR_MINUTE
- GET_FIRMWARE_HDR_MONTH
- GET_FIRMWARE_HDR_ROMCODE_SIZE
- GET_FIRMWARE_HDR_RSVD1
- GET_FIRMWARE_HDR_RSVD2
- GET_FIRMWARE_HDR_RSVD3
- GET_FIRMWARE_HDR_RSVD4
- GET_FIRMWARE_HDR_RSVD5
- GET_FIRMWARE_HDR_SIGNATURE
- GET_FIRMWARE_HDR_SUB_VER
- GET_FIRMWARE_HDR_SVN_IDX
- GET_FIRMWARE_HDR_VERSION
- GET_FIRMWARE_VERSION
- GET_FLAG
- GET_FLAGS
- GET_FLEXIBLE_ARRAY_MEMBER_ADDR
- GET_FLOOR
- GET_FLOW_TABLE_CAP
- GET_FLVIC
- GET_FPA11
- GET_FPEMU_CTL
- GET_FPEXC_CTL
- GET_FPGA_VERS
- GET_FP_MODE
- GET_FRACTIONAL_PART
- GET_FRAG_ID
- GET_FRAME_TAG_BOT
- GET_FRAME_TAG_TOP
- GET_FREQ
- GET_FRONT_BITS
- GET_FSR
- GET_FSRRESTORE
- GET_FSYNR0
- GET_FSYNR1
- GET_FSYNR1_ASIZE
- GET_FW_DEFAULT_BANDS
- GET_FW_SENSE_LEN
- GET_FW_STATUS_CONTROL
- GET_FW_VERS
- GET_FW_VERSION
- GET_FW_VERSION_CONTROL
- GET_GATT
- GET_GATT_OFF
- GET_GBE_FIELD
- GET_GENERATION_NUMBER
- GET_GLB_CSR
- GET_GLOBAL_FIELD
- GET_GLOBAL_REG
- GET_GLOBAL_REG_N
- GET_GLOBAL_TLBIALL
- GET_GL_GLOBAL
- GET_GPD_HWO
- GET_GPIO_VAL_INV
- GET_GPIO_VAL_SHIFT
- GET_GPU_ID
- GET_HAF
- GET_HAL_DATA
- GET_HAL_RFPATH_NUM
- GET_HASH_VALUE
- GET_HC_INF0
- GET_HDR_OFFSET_2_0
- GET_HEADER_LENGTH
- GET_HEAP
- GET_HIGH_SLICE_INDEX
- GET_HIT
- GET_HOR_WAIT_CNT
- GET_HOST_INDEX_0100
- GET_HSTMODE
- GET_HTW
- GET_HTWDEEF
- GET_HTWSEEF
- GET_HT_CAPABILITY_ELE_LDPC_CAP
- GET_HT_CAPABILITY_ELE_RX_STBC
- GET_HT_CAPABILITY_ELE_TX_STBC
- GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP
- GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP
- GET_HT_CTRL_NDP_ANNOUNCEMENT
- GET_HUB_NIC
- GET_HUM
- GET_HUME
- GET_HWI_CONTROLLER_WS
- GET_HW_DATA
- GET_HW_QUEUE
- GET_HW_VERSION_COMMAND
- GET_IA64_MCA_DATA
- GET_ICPC0
- GET_ICPC1
- GET_ICPC2
- GET_ICPC3
- GET_ICPC4
- GET_ICPC5
- GET_ICPC6
- GET_ICPC7
- GET_ID
- GET_IDR
- GET_IDR_HANDLE
- GET_IFACE_NUMS
- GET_IFF_FROM_MAC
- GET_IMAGE
- GET_IMMSVAL
- GET_INDEX
- GET_INDEX_INTO_MASTER_TABLE
- GET_INFO
- GET_INFRACODE
- GET_INITIATOR_INDEX
- GET_INITIATOR_INDEX_0100
- GET_INPUT_CONTROL
- GET_INT
- GET_INTEGER_PART
- GET_INTERFACE_STATUS
- GET_INTERRUPT
- GET_INTR_TARGET
- GET_INT_ARG
- GET_INT_COAL
- GET_INT_COAL_RC
- GET_INT_PARM
- GET_INT_STATUS_SIZE
- GET_IOAT_VER_MAJOR
- GET_IOAT_VER_MINOR
- GET_IOC
- GET_IOCTL_VERSION
- GET_IOC_INDEX_0100
- GET_IOSPACE
- GET_IO_INDEX
- GET_IRPTNDX
- GET_IR_CODE
- GET_IR_DATA_VENDOR_REQUEST
- GET_ISCSI_IPV4ADDR
- GET_ISH
- GET_ISR
- GET_ISR_SMP
- GET_IVERSION
- GET_KEX_CFG
- GET_KEX_FLAGS
- GET_KEX_LD
- GET_KEX_LDFLAGS
- GET_KSM_PAGE_LOCK
- GET_KSM_PAGE_NOLOCK
- GET_KSM_PAGE_TRYLOCK
- GET_L2CC_CTRL_CPU
- GET_L2CC_STATUS_CPU
- GET_L2R_SEGNO
- GET_L2T_CAPACITY
- GET_LANGUAGE_CONTROL
- GET_LAN_BUCKET_CONTEXT
- GET_LAN_BUFFER_CONTEXT
- GET_LAN_FORM
- GET_LAN_PACKET_LENGTH
- GET_LAST_CPU
- GET_LAST_MMAP
- GET_LE
- GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
- GET_LEN
- GET_LEVEL
- GET_LINE_REQUEST
- GET_LINE_REQUEST_TYPE
- GET_LINK_ERROR_COUNT
- GET_LINK_STATUS_LANES
- GET_LIO
- GET_LKE
- GET_LOOP_TIMEOUT
- GET_LOW_SLICE_INDEX
- GET_LUM_CTL
- GET_M
- GET_M2VCBR_N
- GET_MAC_ADDRESS
- GET_MAJOR
- GET_MASK
- GET_MASKED_VAL
- GET_MASK_FROM_EQE
- GET_MASK_VAL
- GET_MAX
- GET_MAXL
- GET_MAX_ACCELENGINES
- GET_MAX_BANKS
- GET_MAX_OUTSTANDING_WR
- GET_MAX_PERIODS
- GET_MAX_SG_SUPPORT
- GET_MAX_VIFS
- GET_MEMORY_CLOCK_PARAMETERS
- GET_MEMORY_CLOCK_PS_ALLOCATION
- GET_MEM_OFFS_2M
- GET_MEM_SIZE
- GET_MFA_ADDR
- GET_MGMT_CONTROLLER_WS
- GET_MHF
- GET_MIN
- GET_MINOR
- GET_MPT_CTL
- GET_MSEG_HANDLE_STATUS
- GET_MS_INFORMATION
- GET_MT
- GET_MTC0
- GET_MTC1
- GET_MTC2
- GET_MTC3
- GET_MTC4
- GET_MTC5
- GET_MTC6
- GET_MTC7
- GET_MTUS
- GET_MULTI
- GET_MY_HUB_NIC
- GET_N
- GET_NAME_NTH_IDX
- GET_NCB
- GET_NEXT_BLOCK
- GET_NEXT_COUNT_IF_FLAG
- GET_NEXT_PRB_BLK_NUM
- GET_NIRPT
- GET_NM2VCBMT
- GET_NMRR
- GET_NOFAULT_MT
- GET_NOFAULT_NOS
- GET_NOFAULT_NS
- GET_NOFAULT_SH
- GET_NOFAULT_SS
- GET_NOS0
- GET_NOS1
- GET_NOS2
- GET_NOS3
- GET_NOS4
- GET_NOS5
- GET_NOS6
- GET_NOS7
- GET_NOTIFY_EVENT_SIZE_FIELD_MASK
- GET_NPFAULT_PA
- GET_NR_HUGE_PAGES
- GET_NSCFG
- GET_NSDESC
- GET_NUM_DMACH
- GET_NUM_EVQUE
- GET_NUM_PAENTRY
- GET_NUM_QDMACH
- GET_NUM_REGN
- GET_NUM_TOUCHES
- GET_NUM_VFS_PER_PATH
- GET_NUM_VFS_PER_PF
- GET_N_ADAP
- GET_OCPC0
- GET_OCPC1
- GET_OCPC2
- GET_OCPC3
- GET_OCPC4
- GET_OCPC5
- GET_OCPC6
- GET_OCPC7
- GET_ODM
- GET_OFFSET
- GET_OFFSET_TOP
- GET_OMAP_CLASS
- GET_OMAP_REVISION
- GET_OMAP_SUBCLASS
- GET_OMAP_TYPE
- GET_OP_REQ_DATA_OFFSET
- GET_OP_REQ_MODIFIER_OFFSET
- GET_OP_REQ_TOKEN_OFFSET
- GET_OP_REQ_TYPE_OFFSET
- GET_ORPHAN_BLOCKS
- GET_OTG_STATUS
- GET_OTHER_SPEED_CONFIGURATION
- GET_PACA
- GET_PAGE
- GET_PAGE_DIR_IDX
- GET_PAGE_DIR_OFF
- GET_PAR
- GET_PARAM_CROP_INFO
- GET_PARAM_DISP_FRAME_BUFFER
- GET_PARAM_DPB_SIZE
- GET_PARAM_FREE_FRAME_BUFFER
- GET_PARAM_PIC_INFO
- GET_PASID
- GET_PASID_MASK
- GET_PAYLOAD_LENGTH
- GET_PBDQC_FROM_RB
- GET_PBLOCK_DESC
- GET_PCC_VADDR
- GET_PCID
- GET_PCID_ADDR
- GET_PCI_MODE
- GET_PCK_TH
- GET_PD0
- GET_PD1
- GET_PERF_COUNTER
- GET_PERF_MODES
- GET_PFN
- GET_PHY_RX_PKT_ERROR
- GET_PHY_RX_PKT_RECV
- GET_PHY_STAT_P0_GAIN_A
- GET_PHY_STAT_P0_GAIN_B
- GET_PHY_STAT_P0_PWDB
- GET_PHY_STAT_P0_PWDB_A
- GET_PHY_STAT_P0_PWDB_B
- GET_PHY_STAT_P1_HT_RXSC
- GET_PHY_STAT_P1_L_RXSC
- GET_PHY_STAT_P1_PWDB_A
- GET_PHY_STAT_P1_PWDB_B
- GET_PHY_STAT_P1_RF_MODE
- GET_PIP_CMD_CODE
- GET_PIXEL_CLOCK_PS_ALLOCATION
- GET_PKG
- GET_PKT_OFFSET
- GET_PMU_CTX
- GET_PMU_OWNER
- GET_PNP_ISA_STRUCT
- GET_POLARITY
- GET_PORT
- GET_PORTS
- GET_PORT_ID
- GET_PORT_IMMUTABLE
- GET_PORT_STATUS
- GET_POWER_MODE
- GET_PR
- GET_PRIMARY_ADAPTER
- GET_PRIVCFG
- GET_PRI_TO_USE
- GET_PROCESSOR4M_ID
- GET_PRODUCTION_INFO_CONTROL
- GET_PROPERTY
- GET_PRRR
- GET_PS
- GET_PSSCR_EC
- GET_PSSCR_ESL
- GET_PSSCR_RL
- GET_PTMEMTYPE
- GET_PTMTCFG
- GET_PTSHCFG
- GET_PW
- GET_PWR_CFG_BASE
- GET_PWR_CFG_CMD
- GET_PWR_CFG_CUT_MASK
- GET_PWR_CFG_FAB_MASK
- GET_PWR_CFG_INTF_MASK
- GET_PWR_CFG_MASK
- GET_PWR_CFG_OFFSET
- GET_PWR_CFG_VALUE
- GET_QID
- GET_R2L_SEGNO
- GET_RAM
- GET_RAM_TYPE
- GET_RBDR_DESC
- GET_RCISH
- GET_RCNSH
- GET_RCOSH
- GET_RC_CODE
- GET_RD_BY_IDX
- GET_REG
- GET_REGISTER
- GET_REGISTER_TYPE
- GET_REG_BIT
- GET_REG_BITS
- GET_REPLY
- GET_REQ_ID
- GET_RES
- GET_RESET
- GET_RESUME
- GET_REV
- GET_RF6052_REAL_MAX_REG
- GET_RFD_BUFFER
- GET_RF_TYPE
- GET_RING_HEAD
- GET_RMM_HANDLE
- GET_ROMTABLE_INDEX
- GET_RPI
- GET_RPTR
- GET_RPUE
- GET_RPUEIE
- GET_RPUERE
- GET_RPU_ACR
- GET_RQ_STATS
- GET_RS_ERR_CNT
- GET_RS_UNCOR_BLK_CNT
- GET_RTBL_RANGE
- GET_RW
- GET_RWE
- GET_RWGE
- GET_RWVMID
- GET_RXD_BC
- GET_RXD_CFI
- GET_RXD_ERR
- GET_RXD_MARKER
- GET_RXD_PKT_ID
- GET_RXD_PRIO
- GET_RXD_RXFQ
- GET_RXD_RXP
- GET_RXD_TO
- GET_RXD_TYPE
- GET_RXD_VLAN_ID
- GET_RXD_VLAN_TCI
- GET_RXD_VTAG
- GET_RXF_TH
- GET_RXMCSSUPP
- GET_RXQS
- GET_RX_CHANNEL_FLAG
- GET_RX_CHANNEL_INFO
- GET_RX_COMPL_V0_BITS
- GET_RX_COMPL_V1_BITS
- GET_RX_DESC_A1_FIT
- GET_RX_DESC_A2_FIT
- GET_RX_DESC_BC
- GET_RX_DESC_BUFF_ADDR
- GET_RX_DESC_BUFF_ADDR64
- GET_RX_DESC_BW
- GET_RX_DESC_C2H
- GET_RX_DESC_CRC32
- GET_RX_DESC_DRV_INFO_SIZE
- GET_RX_DESC_EOR
- GET_RX_DESC_FAGGR
- GET_RX_DESC_FRAG
- GET_RX_DESC_FS
- GET_RX_DESC_HTC
- GET_RX_DESC_HWPC_ERR
- GET_RX_DESC_HWPC_IND
- GET_RX_DESC_HWRSVD
- GET_RX_DESC_ICV
- GET_RX_DESC_ICV_ERR
- GET_RX_DESC_IV0
- GET_RX_DESC_IV1
- GET_RX_DESC_LS
- GET_RX_DESC_MACID
- GET_RX_DESC_MC
- GET_RX_DESC_MD
- GET_RX_DESC_MF
- GET_RX_DESC_NEXT_IND
- GET_RX_DESC_NEXT_PKT_LEN
- GET_RX_DESC_OWN
- GET_RX_DESC_PAGGR
- GET_RX_DESC_PAM
- GET_RX_DESC_PHYST
- GET_RX_DESC_PKT_LEN
- GET_RX_DESC_PPDU_CNT
- GET_RX_DESC_PWR
- GET_RX_DESC_QOS
- GET_RX_DESC_RSVD
- GET_RX_DESC_RXHT
- GET_RX_DESC_RXMCS
- GET_RX_DESC_RX_RATE
- GET_RX_DESC_SECURITY
- GET_RX_DESC_SEQ
- GET_RX_DESC_SHIFT
- GET_RX_DESC_SPLCP
- GET_RX_DESC_SWDEC
- GET_RX_DESC_TID
- GET_RX_DESC_TSFL
- GET_RX_DESC_TYPE
- GET_RX_PAGE_INFO
- GET_RX_PAGE_SIZE
- GET_RX_STATS
- GET_RX_STATUS_DEC_MACID
- GET_RX_STATUS_DESC_A1_FIT
- GET_RX_STATUS_DESC_A1_FIT_8723B
- GET_RX_STATUS_DESC_A2_FIT
- GET_RX_STATUS_DESC_AMSDU
- GET_RX_STATUS_DESC_AMSDU_8723B
- GET_RX_STATUS_DESC_BC
- GET_RX_STATUS_DESC_BC_8723B
- GET_RX_STATUS_DESC_BSSID_FIT_8723B
- GET_RX_STATUS_DESC_BUFF_ADDR
- GET_RX_STATUS_DESC_BUFF_ADDR64_8723B
- GET_RX_STATUS_DESC_BUFF_ADDR_8723B
- GET_RX_STATUS_DESC_BW
- GET_RX_STATUS_DESC_BW_8723B
- GET_RX_STATUS_DESC_CHKERR_8723B
- GET_RX_STATUS_DESC_CHK_VLD_8723B
- GET_RX_STATUS_DESC_CRC32
- GET_RX_STATUS_DESC_CRC32_8723B
- GET_RX_STATUS_DESC_DRVINFO_SIZE
- GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B
- GET_RX_STATUS_DESC_EOR
- GET_RX_STATUS_DESC_EOR_8723B
- GET_RX_STATUS_DESC_EOSP_8723B
- GET_RX_STATUS_DESC_FAGGR
- GET_RX_STATUS_DESC_FIRST_SEG
- GET_RX_STATUS_DESC_FIRST_SEG_8723B
- GET_RX_STATUS_DESC_FRAG
- GET_RX_STATUS_DESC_FRAG_8723B
- GET_RX_STATUS_DESC_HTC
- GET_RX_STATUS_DESC_HTC_8723B
- GET_RX_STATUS_DESC_HWPC_ERR
- GET_RX_STATUS_DESC_HWPC_IND
- GET_RX_STATUS_DESC_ICV
- GET_RX_STATUS_DESC_ICV_8723B
- GET_RX_STATUS_DESC_IPVER_8723B
- GET_RX_STATUS_DESC_IP_CHK_RPT
- GET_RX_STATUS_DESC_IS_TCPUDP__8723B
- GET_RX_STATUS_DESC_IV0
- GET_RX_STATUS_DESC_IV1
- GET_RX_STATUS_DESC_LAST_SEG
- GET_RX_STATUS_DESC_LAST_SEG_8723B
- GET_RX_STATUS_DESC_LDPC_8723B
- GET_RX_STATUS_DESC_MACID_8723B
- GET_RX_STATUS_DESC_MAGIC_MATCH_8723B
- GET_RX_STATUS_DESC_MC
- GET_RX_STATUS_DESC_MC_8723B
- GET_RX_STATUS_DESC_MORE_DATA
- GET_RX_STATUS_DESC_MORE_DATA_8723B
- GET_RX_STATUS_DESC_MORE_FRAG
- GET_RX_STATUS_DESC_MORE_FRAG_8723B
- GET_RX_STATUS_DESC_NEXT_IND
- GET_RX_STATUS_DESC_NEXT_PKTLEN
- GET_RX_STATUS_DESC_OWN
- GET_RX_STATUS_DESC_OWN_8723B
- GET_RX_STATUS_DESC_PAGGR
- GET_RX_STATUS_DESC_PAGGR_8723B
- GET_RX_STATUS_DESC_PAM
- GET_RX_STATUS_DESC_PAM_8723B
- GET_RX_STATUS_DESC_PATTERN_MATCH_8723B
- GET_RX_STATUS_DESC_PHY_STATUS
- GET_RX_STATUS_DESC_PHY_STATUS_8723B
- GET_RX_STATUS_DESC_PKT_LEN
- GET_RX_STATUS_DESC_PKT_LEN_8723B
- GET_RX_STATUS_DESC_PWR
- GET_RX_STATUS_DESC_PWR_8723B
- GET_RX_STATUS_DESC_QOS
- GET_RX_STATUS_DESC_QOS_8723B
- GET_RX_STATUS_DESC_RPT_SEL_8723B
- GET_RX_STATUS_DESC_RXID_MATCH_8723B
- GET_RX_STATUS_DESC_RX_HT
- GET_RX_STATUS_DESC_RX_IS_QOS_8723B
- GET_RX_STATUS_DESC_RX_MCS
- GET_RX_STATUS_DESC_RX_RATE_8723B
- GET_RX_STATUS_DESC_SECURITY
- GET_RX_STATUS_DESC_SECURITY_8723B
- GET_RX_STATUS_DESC_SEQ
- GET_RX_STATUS_DESC_SEQ_8723B
- GET_RX_STATUS_DESC_SHIFT
- GET_RX_STATUS_DESC_SHIFT_8723B
- GET_RX_STATUS_DESC_SPLCP
- GET_RX_STATUS_DESC_SPLCP_8723B
- GET_RX_STATUS_DESC_STBC_8723B
- GET_RX_STATUS_DESC_SWDEC
- GET_RX_STATUS_DESC_SWDEC_8723B
- GET_RX_STATUS_DESC_TCP_CHK_RPT
- GET_RX_STATUS_DESC_TCP_CHK_VALID
- GET_RX_STATUS_DESC_TID
- GET_RX_STATUS_DESC_TID_8723B
- GET_RX_STATUS_DESC_TSFL
- GET_RX_STATUS_DESC_TSFL_8723B
- GET_RX_STATUS_DESC_TYPE
- GET_RX_STATUS_DESC_TYPE_8723B
- GET_RX_STATUS_DESC_UNICAST_MATCH_8723B
- GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B
- GET_SCL_FT_BIC
- GET_SCL_FT_BILI_DN
- GET_SCL_FT_BILI_UP
- GET_SCRATCH0
- GET_SCTLR
- GET_SD_CSD
- GET_SEC_FROM_SEG
- GET_SEG
- GET_SEGNO
- GET_SEGNO_FROM_SEG0
- GET_SEGOFF_FROM_SEG0
- GET_SEG_FROM_SEC
- GET_SEPROM
- GET_SEQ_FROM_MSGID
- GET_SERIAL_NUMBER
- GET_SET_CONFIGURATION
- GET_SET_INTERFACE
- GET_SFC
- GET_SFVS
- GET_SH
- GET_SHADOW_VCPU
- GET_SHDSH0
- GET_SHDSH1
- GET_SHNMSH0
- GET_SHNMSH1
- GET_SIGNAL_LOCK
- GET_SIGNAL_STRENGTH
- GET_SIGSET
- GET_SIT_TYPE
- GET_SIT_VBLOCKS
- GET_SKBUFF_QOS
- GET_SKIP
- GET_SL
- GET_SLOT_STATE
- GET_SLVIC
- GET_SMSTATE
- GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
- GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
- GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ
- GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ
- GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ
- GET_SNR
- GET_SNUM_COMP
- GET_SPDM0SEL
- GET_SPDM1SEL
- GET_SPDM2SEL
- GET_SPDM3SEL
- GET_SPDMBE
- GET_SPEED
- GET_SPEEDSTEP_FREQS
- GET_SPEEDSTEP_OWNER
- GET_SPEEDSTEP_STATE
- GET_SQ_DESC
- GET_SQ_STATS
- GET_SS
- GET_ST1
- GET_ST2
- GET_ST3
- GET_STALLD
- GET_START
- GET_STAT
- GET_STATS
- GET_STATS_64
- GET_STATUS
- GET_STATUS_3000
- GET_STATUS_3600
- GET_STATUS_3800
- GET_STATUS_4000
- GET_STATUS_4100
- GET_STATUS_ATN
- GET_STATUS_B00
- GET_STATUS_CTL
- GET_STATUS_IBF
- GET_STATUS_OBF
- GET_STATUS_STATE
- GET_STAT_COM
- GET_STID_RANGE
- GET_STOP
- GET_STRING_CONTROL
- GET_STRING_DESCRIPTOR_0
- GET_STRING_DESCRIPTOR_1
- GET_STRING_DESCRIPTOR_2
- GET_SUB_UNIT
- GET_SUM_BLOCK
- GET_SUM_TYPE
- GET_SWAP_RA_VAL
- GET_SW_DATA0
- GET_SW_DATA1
- GET_SW_DATA2
- GET_SW_DATA3
- GET_SW_VAL_IDX
- GET_SW_VAL_MASK
- GET_SW_VAL_REG
- GET_SW_VERSION_COMMAND
- GET_SY
- GET_SYSTEM_PASSWORD_KEY
- GET_SYSTEM_PORT_STATUS
- GET_SYSTEM_STATUS
- GET_SYSTEM_STRING
- GET_TAG
- GET_TAGGED_ADDR_CTRL
- GET_TARGET_ID
- GET_TBE
- GET_TBHSEL
- GET_TBLSEL
- GET_TD_SIZE
- GET_TESTBUSCR
- GET_TF
- GET_THERMAL_METER
- GET_THIS_PADDR
- GET_THREAD
- GET_THREAD_INFO
- GET_TICK_NINSTR
- GET_TID
- GET_TID_RANGE
- GET_TIME
- GET_TIMEOUT
- GET_TIMEOUT_OFFSET
- GET_TIPCF
- GET_TI_CLASS
- GET_TKIP_PN
- GET_TLBFLPTER
- GET_TLBIASID
- GET_TLBIASIDCFG
- GET_TLBIVA
- GET_TLBIVAA
- GET_TLBIVAACFG
- GET_TLBIVMID
- GET_TLBIVMIDCFG
- GET_TLBIVMID_VMID
- GET_TLBLCKR
- GET_TLBLCKR_TLBIALLCFG
- GET_TLBLKCRWE
- GET_TLBMCFG
- GET_TLBMF
- GET_TLBSIZE
- GET_TLBSLPTER
- GET_TLBTR0
- GET_TLBTR1
- GET_TLBTR1_PA
- GET_TLBTR1_VMID
- GET_TLBTR2
- GET_TLBTR2_ASID
- GET_TLBTR2_NSTID
- GET_TLBTR2_NV
- GET_TLBTR2_V
- GET_TLBTR2_VA
- GET_TNR
- GET_TOHM
- GET_TOK_CT
- GET_TOLM
- GET_TPD_BUFFER
- GET_TRAP_SL_FROM_CLASS_PORT_INFO
- GET_TRBS_PER_SEGMENT
- GET_TRE
- GET_TSC_CTL
- GET_TTBCR
- GET_TTBR0
- GET_TTBR0_IRGNH
- GET_TTBR0_IRGNL
- GET_TTBR0_NOS
- GET_TTBR0_ORGN
- GET_TTBR0_PA
- GET_TTBR0_SH
- GET_TTBR1
- GET_TTBR1_IRGNH
- GET_TTBR1_IRGNL
- GET_TTBR1_NOS
- GET_TTBR1_ORGN
- GET_TTBR1_PA
- GET_TTBR1_SH
- GET_TT_THINK_TIME
- GET_TUNER_STATUS
- GET_TUNE_STATUS
- GET_TWL_REV
- GET_TXD_T_CODE
- GET_TX_BUFFER_SIZE
- GET_TX_CHANNEL_FLAG
- GET_TX_CHANNEL_INFO
- GET_TX_COMPL_BITS
- GET_TX_DESC_AGG_BREAK
- GET_TX_DESC_AGG_ENABLE
- GET_TX_DESC_AMPDU_DENSITY
- GET_TX_DESC_ANTSEL_A
- GET_TX_DESC_ANTSEL_B
- GET_TX_DESC_AP_DCFE
- GET_TX_DESC_BAR_RTY_TH
- GET_TX_DESC_BMC
- GET_TX_DESC_CCX
- GET_TX_DESC_CCX_TAG
- GET_TX_DESC_CTS2AP_EN
- GET_TX_DESC_CTS2SELF
- GET_TX_DESC_DATA_BW
- GET_TX_DESC_DATA_RATE_FB_LIMIT
- GET_TX_DESC_DATA_RC
- GET_TX_DESC_DATA_RETRY_LIMIT
- GET_TX_DESC_DATA_SHORT
- GET_TX_DESC_DATA_SHORTGI
- GET_TX_DESC_DISABLE_FB
- GET_TX_DESC_DISABLE_RTS_FB
- GET_TX_DESC_EN_DESC_ID
- GET_TX_DESC_FIRST_SEG
- GET_TX_DESC_GF
- GET_TX_DESC_HTC
- GET_TX_DESC_HWSEQ_EN
- GET_TX_DESC_HW_RTS_ENABLE
- GET_TX_DESC_LAST_SEG
- GET_TX_DESC_LINIP
- GET_TX_DESC_LSIG_TXOP_EN
- GET_TX_DESC_MACID
- GET_TX_DESC_MAX_AGG_NUM
- GET_TX_DESC_MCS15_SGI_MAX_LEN
- GET_TX_DESC_MCS7_SGI_MAX_LEN
- GET_TX_DESC_MCSG1_MAX_LEN
- GET_TX_DESC_MCSG2_MAX_LEN
- GET_TX_DESC_MCSG3_MAX_LEN
- GET_TX_DESC_MCSG4_MAX_LEN
- GET_TX_DESC_MCSG5_MAX_LEN
- GET_TX_DESC_MCSG6_MAX_LEN
- GET_TX_DESC_MORE_FRAG
- GET_TX_DESC_NAV_USE_HDR
- GET_TX_DESC_NEXT_DESC_ADDRESS
- GET_TX_DESC_NEXT_DESC_ADDRESS64
- GET_TX_DESC_NEXT_HEAP_PAGE
- GET_TX_DESC_NO_ACM
- GET_TX_DESC_OFFSET
- GET_TX_DESC_OWN
- GET_TX_DESC_OWN_8723B
- GET_TX_DESC_PIFS
- GET_TX_DESC_PKT_ID
- GET_TX_DESC_PKT_OFFSET
- GET_TX_DESC_PKT_SIZE
- GET_TX_DESC_PORT_ID
- GET_TX_DESC_QOS
- GET_TX_DESC_QUEUE_SEL
- GET_TX_DESC_RATE_ID
- GET_TX_DESC_RAW
- GET_TX_DESC_RDG_ENABLE
- GET_TX_DESC_RDG_NAV_EXT
- GET_TX_DESC_RETRY_LIMIT_ENABLE
- GET_TX_DESC_RTS_BW
- GET_TX_DESC_RTS_ENABLE
- GET_TX_DESC_RTS_RATE
- GET_TX_DESC_RTS_RATE_FB_LIMIT
- GET_TX_DESC_RTS_RC
- GET_TX_DESC_RTS_SC
- GET_TX_DESC_RTS_SHORT
- GET_TX_DESC_RTS_STBC
- GET_TX_DESC_SEC_TYPE
- GET_TX_DESC_SEQ
- GET_TX_DESC_TAIL_PAGE
- GET_TX_DESC_TXAGC_A
- GET_TX_DESC_TXAGC_B
- GET_TX_DESC_TX_ANTL
- GET_TX_DESC_TX_ANT_CCK
- GET_TX_DESC_TX_ANT_HT
- GET_TX_DESC_TX_BUFFER_ADDRESS
- GET_TX_DESC_TX_BUFFER_ADDRESS64
- GET_TX_DESC_TX_BUFFER_ADDRESS_8723B
- GET_TX_DESC_TX_BUFFER_SIZE
- GET_TX_DESC_TX_RATE
- GET_TX_DESC_TX_STBC
- GET_TX_DESC_TX_SUB_CARRIER
- GET_TX_DESC_USB_TXAGG_NUM
- GET_TX_DESC_USE_MAX_LEN
- GET_TX_DESC_USE_RATE
- GET_TX_DESC_WAIT_DCTS
- GET_TX_EMPTY_DEFAULT_VALUE
- GET_TX_MAX_CHUNK
- GET_TX_PAGE_SIZE
- GET_TX_REPORT_RETRY_V1
- GET_TX_REPORT_RETRY_V2
- GET_TX_REPORT_SN_V1
- GET_TX_REPORT_SN_V2
- GET_TX_REPORT_ST_V1
- GET_TX_REPORT_ST_V2
- GET_TX_REPORT_TYPE1_DROP_0
- GET_TX_REPORT_TYPE1_DROP_1
- GET_TX_REPORT_TYPE1_RERTY_0
- GET_TX_REPORT_TYPE1_RERTY_1
- GET_TX_REPORT_TYPE1_RERTY_2
- GET_TX_REPORT_TYPE1_RERTY_3
- GET_TX_REPORT_TYPE1_RERTY_4
- GET_TX_RPT2_DESC_MACID_VALID_1_88E
- GET_TX_RPT2_DESC_MACID_VALID_2_88E
- GET_TX_RPT2_DESC_PKT_LEN_88E
- GET_TX_STATS
- GET_TYPE
- GET_UART_STATUS
- GET_UART_STATUS_MSR
- GET_UART_STATUS_TYPE
- GET_UDF_IEX_TRAP
- GET_UNALIGN_CTL
- GET_UNDECORATED_AVERAGE_RSSI
- GET_UNIPERIF_BIT_CONTROL
- GET_UNIPERIF_BIT_CONTROL_CHL_STS_UPDATE
- GET_UNIPERIF_BIT_CONTROL_CLR_UNDERFLOW_DURATION
- GET_UNIPERIF_CHANNEL_STA_REG0
- GET_UNIPERIF_CHANNEL_STA_REG1
- GET_UNIPERIF_CHANNEL_STA_REG2
- GET_UNIPERIF_CHANNEL_STA_REG3
- GET_UNIPERIF_CHANNEL_STA_REG4
- GET_UNIPERIF_CHANNEL_STA_REG5
- GET_UNIPERIF_CHANNEL_STA_REGN
- GET_UNIPERIF_CONFIG
- GET_UNIPERIF_CONFIG_BACK_STALL_REQ
- GET_UNIPERIF_CONFIG_CHANNEL_STA_CNTR
- GET_UNIPERIF_CONFIG_CHL_STS_UPDATE
- GET_UNIPERIF_CONFIG_DMA_TRIG_LIMIT
- GET_UNIPERIF_CONFIG_IDLE_MOD
- GET_UNIPERIF_CONFIG_MEM_FMT
- GET_UNIPERIF_CONFIG_MSTR_CLKEDGE
- GET_UNIPERIF_CONFIG_ONE_BIT_AUD
- GET_UNIPERIF_CONFIG_PARITY_CNTR
- GET_UNIPERIF_CONFIG_REPEAT_CHL_STS
- GET_UNIPERIF_CONFIG_SPDIF_SW_CTRL
- GET_UNIPERIF_CONFIG_SUBFRAME_SEL
- GET_UNIPERIF_CONFIG_USER_DAT_CNTR
- GET_UNIPERIF_CONFIG_VALIDITY_DAT_CNTR
- GET_UNIPERIF_CTRL
- GET_UNIPERIF_CTRL_BYTE_SWP
- GET_UNIPERIF_CTRL_DIVIDER
- GET_UNIPERIF_CTRL_EXIT_STBY_ON_EOBLOCK
- GET_UNIPERIF_CTRL_OPERATION
- GET_UNIPERIF_CTRL_READER_OUT_SEL
- GET_UNIPERIF_CTRL_ROUNDING
- GET_UNIPERIF_CTRL_SPDIF_FMT
- GET_UNIPERIF_CTRL_SPDIF_LAT
- GET_UNIPERIF_CTRL_UNDERFLOW_REC_WINDOW
- GET_UNIPERIF_CTRL_ZERO_STUFF
- GET_UNIPERIF_DBG_STANDBY_LEFT_SP
- GET_UNIPERIF_I2S_FMT
- GET_UNIPERIF_I2S_FMT_ALIGN
- GET_UNIPERIF_I2S_FMT_DATA_SIZE
- GET_UNIPERIF_I2S_FMT_LR_POL
- GET_UNIPERIF_I2S_FMT_NBIT
- GET_UNIPERIF_I2S_FMT_NO_OF_SAMPLES_TO_READ
- GET_UNIPERIF_I2S_FMT_NUM_CH
- GET_UNIPERIF_I2S_FMT_ORDER
- GET_UNIPERIF_I2S_FMT_PADDING
- GET_UNIPERIF_I2S_FMT_SCLK_EDGE
- GET_UNIPERIF_ITM
- GET_UNIPERIF_ITS
- GET_UNIPERIF_REG
- GET_UNIPERIF_SOFT_RST
- GET_UNIPERIF_SOFT_RST_SOFT_RST
- GET_UNIPERIF_STATUS_1
- GET_UNIPERIF_STATUS_1_UNDERFLOW_DURATION
- GET_UNIPERIF_TDM_ENABLE
- GET_UNIPERIF_TDM_ENABLE_EN_TDM
- GET_UNIPERIF_TDM_FS_REF_DIV
- GET_UNIPERIF_TDM_FS_REF_DIV_NUM_TIMESLOT
- GET_UNIPERIF_TDM_FS_REF_FREQ
- GET_UNIPERIF_TDM_FS_REF_FREQ_REF_FREQ
- GET_UNIPERIF_TDM_WORD_POS
- GET_UNIPERIF_USER_VALIDITY
- GET_UNIPERIF_USER_VALIDITY_VALIDITY_LR
- GET_UR
- GET_URB_TIMEOUT
- GET_USAGE_COUNT
- GET_USB_SPEED
- GET_USER
- GET_USERREG
- GET_UW
- GET_V2PCFG
- GET_V2PPR
- GET_V2PPW
- GET_V2PSR
- GET_V2PUR
- GET_V2PUW
- GET_VAL
- GET_VALUE_BYTE
- GET_VAR
- GET_VBR
- GET_VCC
- GET_VCE_INSTANCE
- GET_VERSION
- GET_VERSION_INFO_VENDOR_REQUEST
- GET_VERSION_MP
- GET_VERSION_TYPE
- GET_VERT_WAIT_CNT
- GET_VHTCAP_CHWDSET
- GET_VHTNSSMCS
- GET_VICTIM
- GET_VIT_ERR_CNT
- GET_VLAN_EGRESS_PRIORITY_CMD
- GET_VLAN_INGRESS_PRIORITY_CMD
- GET_VLAN_REALDEV_NAME_CMD
- GET_VLAN_VID_CMD
- GET_VLPI
- GET_VMID
- GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
- GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
- GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
- GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
- GET_VPD
- GET_VPD_RSP
- GET_VPD_SIZE
- GET_VPD_SIZE_RSP
- GET_VS
- GET_WCCR_SECS
- GET_WGSEL
- GET_WID_TYPE
- GET_WLDR_VAL
- GET_WPTR
- GET_WR_LEN
- GET_XFER_CNT
- GET_XN
- GET_XX_CTL
- GET_XY_CTL
- GET_YAL_STATUS
- GET_ZONE_FROM_SEC
- GET_ZONE_FROM_SEG
- GETest
- GE_ABORT
- GE_AUTO_NEG_CTL
- GE_CF_CRC_STRIP_REG
- GE_CNTL__BREAK_WAVE_AT_EOI_MASK
- GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT
- GE_CNTL__PACKET_TO_ONE_PA_MASK
- GE_CNTL__PACKET_TO_ONE_PA__SHIFT
- GE_CNTL__PRIM_GRP_SIZE_MASK
- GE_CNTL__PRIM_GRP_SIZE__SHIFT
- GE_CNTL__VERT_GRP_SIZE_MASK
- GE_CNTL__VERT_GRP_SIZE__SHIFT
- GE_COMMAND_OFF
- GE_CYC_TYPE_MASK
- GE_DEPTH_OFF
- GE_DESTAREAH_OFF
- GE_DESTAREAW_OFF
- GE_DESTAREAX_OFF
- GE_DESTAREAY_OFF
- GE_DESTBASE_OFF
- GE_DESTDISPH_OFF
- GE_DESTDISPW_OFF
- GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK
- GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT
- GE_DUPLEX_FULL
- GE_DUPLEX_HALF
- GE_DUPLEX_TYPE
- GE_ENABLE_OFF
- GE_FAST_CLKS__FORCE_FAST_CLK_MASK
- GE_FAST_CLKS__FORCE_FAST_CLK__SHIFT
- GE_FAST_CLKS__HYSTERESIS_MASK
- GE_FAST_CLKS__HYSTERESIS__SHIFT
- GE_FAST_CLKS__LOCK_MASK
- GE_FAST_CLKS__LOCK__SHIFT
- GE_FIRE_OFF
- GE_HEALTHCARE_NEMO_TRACKER_PID
- GE_HEALTHCARE_VID
- GE_HIGHCOLOR_OFF
- GE_HOST_STC
- GE_INDX_OFFSET__INDX_OFFSET_MASK
- GE_INDX_OFFSET__INDX_OFFSET__SHIFT
- GE_INTEN_OFF
- GE_MAX_FRM_SIZE_REG
- GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK
- GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT
- GE_MAX_VTX_INDX__MAX_INDX_MASK
- GE_MAX_VTX_INDX__MAX_INDX__SHIFT
- GE_MIN_VTX_INDX__MIN_INDX_MASK
- GE_MIN_VTX_INDX__MIN_INDX__SHIFT
- GE_MODE_CHANGE_EN
- GE_MODE_CHANGE_REG
- GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK
- GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT
- GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK
- GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT
- GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK
- GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT
- GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK
- GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT
- GE_PAT0C_OFF
- GE_PC_ALLOC__NUM_PC_LINES_MASK
- GE_PC_ALLOC__NUM_PC_LINES__SHIFT
- GE_PC_ALLOC__OVERSUB_EN_MASK
- GE_PC_ALLOC__OVERSUB_EN__SHIFT
- GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC_MASK
- GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC__SHIFT
- GE_PC_CNTL__PC_SIZE_MASK
- GE_PC_CNTL__PC_SIZE__SHIFT
- GE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK
- GE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT
- GE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GE_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER10_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER10_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER10_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER11_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER11_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER11_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
- GE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
- GE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
- GE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
- GE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
- GE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
- GE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
- GE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
- GE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK
- GE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT
- GE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- GE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- GE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- GE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- GE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- GE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- GE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- GE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- GE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- GE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- GE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- GE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- GE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK
- GE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT
- GE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- GE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- GE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- GE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- GE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK
- GE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT
- GE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK
- GE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT
- GE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK
- GE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT
- GE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK
- GE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT
- GE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK
- GE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT
- GE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK
- GE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT
- GE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK
- GE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT
- GE_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER4_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER4_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER4_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER5_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER5_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER5_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER6_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER6_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER6_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER7_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER7_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER7_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER8_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER8_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER8_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK
- GE_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT
- GE_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK
- GE_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT
- GE_PERFCOUNTER9_SELECT__PERF_MODE_MASK
- GE_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT
- GE_PERFCOUNTER9_SELECT__PERF_SEL0_MASK
- GE_PERFCOUNTER9_SELECT__PERF_SEL0__SHIFT
- GE_PERFCOUNT_SELECT
- GE_PORT_EN
- GE_PORT_MODE
- GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK
- GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT
- GE_PRIV_CONTROL__DISCARD_LEGACY_MASK
- GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT
- GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK
- GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT
- GE_RECV_CONTROL_REG
- GE_ROPCODE_OFF
- GE_RX_INT_THRESHOLD
- GE_RX_PAD_EN
- GE_RX_PORT_EN
- GE_RX_STRIP_CRC
- GE_RX_STRIP_PAD
- GE_RX_TIMEOUT
- GE_SHORT_RUNTS_THR_REG
- GE_SRCAREAH_OFF
- GE_SRCAREAW_OFF
- GE_SRCAREAX_OFF
- GE_SRCAREAY_OFF
- GE_SRCBASE_OFF
- GE_SRCDISPH_OFF
- GE_SRCDISPW_OFF
- GE_STATION_MAC_ADDRESS
- GE_STATUS_OFF
- GE_STATUS__PERFCOUNTER_STATUS_MASK
- GE_STATUS__PERFCOUNTER_STATUS__SHIFT
- GE_STATUS__THREAD_TRACE_STATUS_MASK
- GE_STATUS__THREAD_TRACE_STATUS__SHIFT
- GE_STEREO_CNTL__EN_STEREO_MASK
- GE_STEREO_CNTL__EN_STEREO__SHIFT
- GE_STEREO_CNTL__RT_SLICE_MASK
- GE_STEREO_CNTL__RT_SLICE__SHIFT
- GE_STEREO_CNTL__VIEWPORT_MASK
- GE_STEREO_CNTL__VIEWPORT__SHIFT
- GE_TRANSMIT_CONTROL_REG
- GE_TX_ADD_CRC
- GE_TX_AUTO_NEG
- GE_TX_LOCAL_PAGE_REG
- GE_TX_PORT_EN
- GE_TX_SHORT_PAD_THROUGH
- GE_USER_VGPR1__DATA_MASK
- GE_USER_VGPR1__DATA__SHIFT
- GE_USER_VGPR2__DATA_MASK
- GE_USER_VGPR2__DATA__SHIFT
- GE_USER_VGPR3__DATA_MASK
- GE_USER_VGPR3__DATA__SHIFT
- GE_USER_VGPR_EN__EN_USER_VGPR1_MASK
- GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT
- GE_USER_VGPR_EN__EN_USER_VGPR2_MASK
- GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT
- GE_USER_VGPR_EN__EN_USER_VGPR3_MASK
- GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT
- GElf_Nhdr
- GF100_DMA_V0_KIND_PITCH
- GF100_DMA_V0_KIND_VM
- GF100_DMA_V0_PRIV_US
- GF100_DMA_V0_PRIV_VM
- GF100_DMA_V0_PRIV__S
- GF100_MSPDEC
- GF100_MSPPP
- GF100_MSVLD
- GF110_DISP
- GF110_DISP_BASE_CHANNEL_DMA
- GF110_DISP_CORE_CHANNEL_DMA
- GF110_DISP_CURSOR
- GF110_DISP_OVERLAY
- GF110_DISP_OVERLAY_CONTROL_DMA
- GF119_DMA_V0_KIND_PITCH
- GF119_DMA_V0_KIND_VM
- GF119_DMA_V0_PAGE_LP
- GF119_DMA_V0_PAGE_SP
- GF128MUL_MASK
- GF128_MUL
- GF1_SINGLE
- GF20_PROT_CFG
- GF20_PROT_CFG_PROTECT_CTRL
- GF20_PROT_CFG_PROTECT_NAV_LONG
- GF20_PROT_CFG_PROTECT_NAV_SHORT
- GF20_PROT_CFG_PROTECT_RATE
- GF20_PROT_CFG_RTS_TH_EN
- GF20_PROT_CFG_TX_OP_ALLOW_CCK
- GF20_PROT_CFG_TX_OP_ALLOW_GF20
- GF20_PROT_CFG_TX_OP_ALLOW_GF40
- GF20_PROT_CFG_TX_OP_ALLOW_MM20
- GF20_PROT_CFG_TX_OP_ALLOW_MM40
- GF20_PROT_CFG_TX_OP_ALLOW_OFDM
- GF2K_ID_F23P
- GF2K_ID_F30
- GF2K_ID_F305
- GF2K_ID_F30D
- GF2K_ID_F31
- GF2K_ID_F31D
- GF2K_ID_G09
- GF2K_ID_MAX
- GF2K_LENGTH
- GF2K_START
- GF2K_STROBE
- GF2K_TIMEOUT
- GF40_PROT_CFG
- GF40_PROT_CFG_PROTECT_CTRL
- GF40_PROT_CFG_PROTECT_NAV_LONG
- GF40_PROT_CFG_PROTECT_NAV_SHORT
- GF40_PROT_CFG_PROTECT_RATE
- GF40_PROT_CFG_RTS_TH_EN
- GF40_PROT_CFG_TX_OP_ALLOW_CCK
- GF40_PROT_CFG_TX_OP_ALLOW_GF20
- GF40_PROT_CFG_TX_OP_ALLOW_GF40
- GF40_PROT_CFG_TX_OP_ALLOW_MM20
- GF40_PROT_CFG_TX_OP_ALLOW_MM40
- GF40_PROT_CFG_TX_OP_ALLOW_OFDM
- GF8_MUL
- GFAR_100_TIME
- GFAR_10_TIME
- GFAR_CB
- GFAR_DEV_WEIGHT
- GFAR_DOWN
- GFAR_EM_NUM
- GFAR_ER
- GFAR_ERRATA_12
- GFAR_ERRATA_74
- GFAR_ERRATA_76
- GFAR_ERRATA_A002
- GFAR_EXTRA_STATS_LEN
- GFAR_GBIT_TIME
- GFAR_INT_NAME_MAX
- GFAR_JUMBO_FRAME_SIZE
- GFAR_MAX_COAL_FRAMES
- GFAR_MAX_COAL_USECS
- GFAR_MQ_POLLING
- GFAR_NUM_IRQS
- GFAR_PM_OPS
- GFAR_RESETTING
- GFAR_RMON_LEN
- GFAR_RX
- GFAR_RXB_SIZE
- GFAR_RXB_TRUESIZE
- GFAR_RX_BUFF_ALLOC
- GFAR_RX_MAX_RING_SIZE
- GFAR_SKBFRAG_SIZE
- GFAR_SQ_POLLING
- GFAR_STATS_LEN
- GFAR_TX
- GFAR_TX_MAX_RING_SIZE
- GFAR_WOL_FILER_UCAST
- GFAR_WOL_MAGIC
- GFBR
- GFCR_GPIO_ON
- GFER
- GFER_OFFSET
- GFF_FCP_SCSI_OFFSET
- GFF_ID_CMD
- GFF_ID_REQ_SIZE
- GFF_ID_RSP_SIZE
- GFF_NVME_OFFSET
- GFF_REQUEST_SZ
- GFIELD
- GFIFOTest
- GFIFO_SIZE
- GFIFO_SIZE_128
- GFIR_ERR_TRIGGER
- GFLAGS
- GFP
- GFPIC_IRQ_BASE
- GFPIC_NR_IRQS
- GFPIC_REG_IRQ_DISABLE
- GFPIC_REG_IRQ_DISABLE_ALL
- GFPIC_REG_IRQ_ENABLE
- GFPIC_REG_IRQ_PENDING
- GFPN_ID_CMD
- GFPN_ID_REQ_SIZE
- GFPN_ID_RSP_SIZE
- GFP_ATOMIC
- GFP_BALLOON
- GFP_BOOT_MASK
- GFP_CONSTRAINT_MASK
- GFP_DMA
- GFP_DMA32
- GFP_F2FS_ZERO
- GFP_HIGHUSER
- GFP_HIGHUSER_MOVABLE
- GFP_IMAGE
- GFP_KDB
- GFP_KERNEL
- GFP_KERNEL_ACCOUNT
- GFP_MOVABLE_MASK
- GFP_MOVABLE_SHIFT
- GFP_NOFS
- GFP_NOIO
- GFP_NOWAIT
- GFP_PGTABLE_KERNEL
- GFP_PGTABLE_USER
- GFP_RECLAIM_MASK
- GFP_SLAB_BUG_MASK
- GFP_TRACE
- GFP_TRANSHUGE
- GFP_TRANSHUGE_LIGHT
- GFP_TRY
- GFP_USER
- GFP_VMALLOC32
- GFP_ZONEMASK
- GFP_ZONES_SHIFT
- GFP_ZONE_BAD
- GFP_ZONE_TABLE
- GFRM100
- GFRM100_SEARCH_KEY_AUDIO_DATA
- GFRM100_SEARCH_KEY_DOWN
- GFRM100_SEARCH_KEY_REPORT_ID
- GFRM100_SEARCH_KEY_UP
- GFRM200
- GFS2_ACL_MAX_ENTRIES
- GFS2_AF_ORLOV
- GFS2_ATTR
- GFS2_BASIC_BLOCK
- GFS2_BASIC_BLOCK_SHIFT
- GFS2_BIT_MASK
- GFS2_BIT_SIZE
- GFS2_BLKST_DINODE
- GFS2_BLKST_FREE
- GFS2_BLKST_UNLINKED
- GFS2_BLKST_USED
- GFS2_CONTROL_LOCK
- GFS2_DATA_DEFAULT
- GFS2_DATA_ORDERED
- GFS2_DATA_WRITEBACK
- GFS2_DIF_APPENDONLY
- GFS2_DIF_DIRECTIO
- GFS2_DIF_EA_INDIRECT
- GFS2_DIF_EXHASH
- GFS2_DIF_IMMUTABLE
- GFS2_DIF_INHERIT_DIRECTIO
- GFS2_DIF_INHERIT_JDATA
- GFS2_DIF_JDATA
- GFS2_DIF_NOATIME
- GFS2_DIF_SYNC
- GFS2_DIF_SYSTEM
- GFS2_DIF_TOPDIR
- GFS2_DIF_TRUNC_IN_PROG
- GFS2_DIF_UNUSED
- GFS2_DIRENT_SIZE
- GFS2_DIR_MAX_DEPTH
- GFS2_EA2DATA
- GFS2_EA2DATAPTRS
- GFS2_EA2NAME
- GFS2_EA2NEXT
- GFS2_EAFLAG_LAST
- GFS2_EAREQ_SIZE_STUFFED
- GFS2_EATYPE_LAST
- GFS2_EATYPE_SECURITY
- GFS2_EATYPE_SYS
- GFS2_EATYPE_UNUSED
- GFS2_EATYPE_USR
- GFS2_EATYPE_VALID
- GFS2_EA_BH2FIRST
- GFS2_EA_DATA_LEN
- GFS2_EA_IS_LAST
- GFS2_EA_IS_STUFFED
- GFS2_EA_MAX_DATA_LEN
- GFS2_EA_MAX_NAME_LEN
- GFS2_EA_REC_LEN
- GFS2_EA_SIZE
- GFS2_ERRORS_CONTINUE
- GFS2_ERRORS_DEFAULT
- GFS2_ERRORS_PANIC
- GFS2_ERRORS_RO
- GFS2_ERRORS_WITHDRAW
- GFS2_FAST_NAME_SIZE
- GFS2_FIELDMASK
- GFS2_FLAGS_USER_SET
- GFS2_FNAMESIZE
- GFS2_FORMAT_DE
- GFS2_FORMAT_DI
- GFS2_FORMAT_EA
- GFS2_FORMAT_ED
- GFS2_FORMAT_FS
- GFS2_FORMAT_IN
- GFS2_FORMAT_JD
- GFS2_FORMAT_LB
- GFS2_FORMAT_LD
- GFS2_FORMAT_LF
- GFS2_FORMAT_LH
- GFS2_FORMAT_MULTI
- GFS2_FORMAT_NONE
- GFS2_FORMAT_QC
- GFS2_FORMAT_QU
- GFS2_FORMAT_RB
- GFS2_FORMAT_RG
- GFS2_FORMAT_RI
- GFS2_FORMAT_SB
- GFS2_FREEZE_LOCK
- GFS2_FSNAME_LEN
- GFS2_GL_HASH_SHIFT
- GFS2_GL_HASH_SIZE
- GFS2_HASH_INDEX_MASK
- GFS2_HAS_UUID
- GFS2_I
- GFS2_INUM_QUANTUM
- GFS2_JTRUNC_REVOKES
- GFS2_LARGE_FH_SIZE
- GFS2_LFC_AIL_EMPTY_GL
- GFS2_LFC_AIL_FLUSH
- GFS2_LFC_DO_SYNC
- GFS2_LFC_EVICT_INODE
- GFS2_LFC_FREEZE_GO_SYNC
- GFS2_LFC_INODE_GO_INVAL
- GFS2_LFC_INODE_GO_SYNC
- GFS2_LFC_INPLACE_RESERVE
- GFS2_LFC_JDATA_WPAGES
- GFS2_LFC_KILL_SB
- GFS2_LFC_LOGD_AIL_FLUSH_REQD
- GFS2_LFC_LOGD_JFLUSH_REQD
- GFS2_LFC_MAKE_FS_RO
- GFS2_LFC_RGRP_GO_SYNC
- GFS2_LFC_SET_FLAGS
- GFS2_LFC_SHUTDOWN
- GFS2_LFC_SYNC_FS
- GFS2_LFC_TRANS_END
- GFS2_LFC_WRITE_INODE
- GFS2_LIVE_LOCK
- GFS2_LKS_DCOUNT
- GFS2_LKS_QCOUNT
- GFS2_LKS_SIRT
- GFS2_LKS_SIRTVAR
- GFS2_LKS_SRTT
- GFS2_LKS_SRTTB
- GFS2_LKS_SRTTVAR
- GFS2_LKS_SRTTVARB
- GFS2_LOCKNAME_LEN
- GFS2_LOG_DESC_JDATA
- GFS2_LOG_DESC_METADATA
- GFS2_LOG_DESC_REVOKE
- GFS2_LOG_HEAD_FLUSH_FREEZE
- GFS2_LOG_HEAD_FLUSH_NORMAL
- GFS2_LOG_HEAD_FLUSH_SHUTDOWN
- GFS2_LOG_HEAD_FLUSH_SYNC
- GFS2_LOG_HEAD_RECOVERY
- GFS2_LOG_HEAD_UNMOUNT
- GFS2_LOG_HEAD_USERSPACE
- GFS2_MAGIC
- GFS2_MAXQUOTAS
- GFS2_MAX_META_HEIGHT
- GFS2_METATYPE_DI
- GFS2_METATYPE_EA
- GFS2_METATYPE_ED
- GFS2_METATYPE_IN
- GFS2_METATYPE_JD
- GFS2_METATYPE_LB
- GFS2_METATYPE_LD
- GFS2_METATYPE_LF
- GFS2_METATYPE_LH
- GFS2_METATYPE_NONE
- GFS2_METATYPE_QC
- GFS2_METATYPE_RB
- GFS2_METATYPE_RG
- GFS2_METATYPE_SB
- GFS2_MIN_DIRENT_SIZE
- GFS2_MIN_LVB_SIZE
- GFS2_MOUNTED_LOCK
- GFS2_MOUNT_LOCK
- GFS2_NBBY
- GFS2_NR_LKSTATS
- GFS2_NR_SBSTATS
- GFS2_OLD_FH_SIZE
- GFS2_QCF_USER
- GFS2_QD_HASH_MASK
- GFS2_QD_HASH_SHIFT
- GFS2_QD_HASH_SIZE
- GFS2_QUOTA_ACCOUNT
- GFS2_QUOTA_DEFAULT
- GFS2_QUOTA_OFF
- GFS2_QUOTA_ON
- GFS2_RDF_CHECK
- GFS2_RDF_ERROR
- GFS2_RDF_MASK
- GFS2_RDF_PREFERRED
- GFS2_RDF_UPTODATE
- GFS2_RENAME_LOCK
- GFS2_RGF_DATAONLY
- GFS2_RGF_JOURNAL
- GFS2_RGF_METAONLY
- GFS2_RGF_NOALLOC
- GFS2_RGF_TRIMMED
- GFS2_SB
- GFS2_SB_ADDR
- GFS2_SB_LOCK
- GFS2_SEQ_GOODSIZE
- GFS2_SMALL_FH_SIZE
- GFS2_USE_HASH_FLAG
- GFS_MAX_DEVS
- GFS_PRODUCT_ID
- GFS_VENDOR_ID
- GFT_ADD_FILTER
- GFT_CAM_LINE_DATA_MASK
- GFT_CAM_LINE_DATA_SHIFT
- GFT_CAM_LINE_MAPPED_IP_VERSION_MASK
- GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK
- GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT
- GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT
- GFT_CAM_LINE_MAPPED_PF_ID_MASK
- GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK
- GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT
- GFT_CAM_LINE_MAPPED_PF_ID_SHIFT
- GFT_CAM_LINE_MAPPED_RESERVED1_MASK
- GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT
- GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK
- GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK
- GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT
- GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT
- GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK
- GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK
- GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT
- GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT
- GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK
- GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK
- GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT
- GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT
- GFT_CAM_LINE_MAPPED_VALID_MASK
- GFT_CAM_LINE_MAPPED_VALID_SHIFT
- GFT_CAM_LINE_MASK_BITS_MASK
- GFT_CAM_LINE_MASK_BITS_SHIFT
- GFT_CAM_LINE_RESERVED1_MASK
- GFT_CAM_LINE_RESERVED1_SHIFT
- GFT_CAM_LINE_VALID_MASK
- GFT_CAM_LINE_VALID_SHIFT
- GFT_DELETE_FILTER
- GFT_ID_CMD
- GFT_ID_REQ_SIZE
- GFT_ID_RSP_SIZE
- GFT_PROFILE_ARP_PROTOCOL
- GFT_PROFILE_FCOE_PROTOCOL
- GFT_PROFILE_GENEVE_IP_TUNNEL
- GFT_PROFILE_GENEVE_MAC_TUNNEL
- GFT_PROFILE_GRE_IP_TUNNEL
- GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL
- GFT_PROFILE_ICMP_PROTOCOL
- GFT_PROFILE_IPV4
- GFT_PROFILE_IPV6
- GFT_PROFILE_KEY_IP_VERSION_MASK
- GFT_PROFILE_KEY_IP_VERSION_SHIFT
- GFT_PROFILE_KEY_PF_ID_MASK
- GFT_PROFILE_KEY_PF_ID_SHIFT
- GFT_PROFILE_KEY_RESERVED0_MASK
- GFT_PROFILE_KEY_RESERVED0_SHIFT
- GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK
- GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT
- GFT_PROFILE_KEY_TUNNEL_TYPE_MASK
- GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT
- GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK
- GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT
- GFT_PROFILE_NO_TUNNEL
- GFT_PROFILE_RAW
- GFT_PROFILE_ROCE_PROTOCOL
- GFT_PROFILE_RROCE_PROTOCOL
- GFT_PROFILE_TCP_PROTOCOL
- GFT_PROFILE_TYPE_4_TUPLE
- GFT_PROFILE_TYPE_IP_DST_ADDR
- GFT_PROFILE_TYPE_IP_SRC_ADDR
- GFT_PROFILE_TYPE_L4_DST_PORT
- GFT_PROFILE_TYPE_TUNNEL_TYPE
- GFT_PROFILE_UDP_PROTOCOL
- GFT_PROFILE_USER_ETH_1_INNER
- GFT_PROFILE_USER_ETH_2_OUTER
- GFT_PROFILE_USER_IP_1_INNER
- GFT_PROFILE_USER_IP_2_OUTER
- GFT_PROFILE_USER_TCP_DST_PORT_1_INNER
- GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER
- GFT_PROFILE_USER_UDP_DST_PORT_1_INNER
- GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER
- GFT_PROFILE_VXLAN_TUNNEL
- GFT_RAM_LINE_DSCP_MASK
- GFT_RAM_LINE_DSCP_SHIFT
- GFT_RAM_LINE_DST_IP_MASK
- GFT_RAM_LINE_DST_IP_SHIFT
- GFT_RAM_LINE_DST_MAC_MASK
- GFT_RAM_LINE_DST_MAC_SHIFT
- GFT_RAM_LINE_DST_PORT_MASK
- GFT_RAM_LINE_DST_PORT_SHIFT
- GFT_RAM_LINE_ETHERTYPE_MASK
- GFT_RAM_LINE_ETHERTYPE_SHIFT
- GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK
- GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT
- GFT_RAM_LINE_PRIORITY_MASK
- GFT_RAM_LINE_PRIORITY_SHIFT
- GFT_RAM_LINE_PROVIDER_VLAN_MASK
- GFT_RAM_LINE_PROVIDER_VLAN_SHIFT
- GFT_RAM_LINE_RESERVED0_MASK
- GFT_RAM_LINE_RESERVED0_SHIFT
- GFT_RAM_LINE_RESERVED1_MASK
- GFT_RAM_LINE_RESERVED1_SHIFT
- GFT_RAM_LINE_SRC_IP_MASK
- GFT_RAM_LINE_SRC_IP_SHIFT
- GFT_RAM_LINE_SRC_MAC_MASK
- GFT_RAM_LINE_SRC_MAC_SHIFT
- GFT_RAM_LINE_SRC_PORT_MASK
- GFT_RAM_LINE_SRC_PORT_SHIFT
- GFT_RAM_LINE_TCP_FLAG_ACK_MASK
- GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT
- GFT_RAM_LINE_TCP_FLAG_CWR_MASK
- GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT
- GFT_RAM_LINE_TCP_FLAG_ECE_MASK
- GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT
- GFT_RAM_LINE_TCP_FLAG_FIN_MASK
- GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT
- GFT_RAM_LINE_TCP_FLAG_NS_MASK
- GFT_RAM_LINE_TCP_FLAG_NS_SHIFT
- GFT_RAM_LINE_TCP_FLAG_PSH_MASK
- GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT
- GFT_RAM_LINE_TCP_FLAG_RST_MASK
- GFT_RAM_LINE_TCP_FLAG_RST_SHIFT
- GFT_RAM_LINE_TCP_FLAG_SYN_MASK
- GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT
- GFT_RAM_LINE_TCP_FLAG_URG_MASK
- GFT_RAM_LINE_TCP_FLAG_URG_SHIFT
- GFT_RAM_LINE_TENANT_ID_MASK
- GFT_RAM_LINE_TENANT_ID_SHIFT
- GFT_RAM_LINE_TTL_EQUAL_ONE_MASK
- GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT
- GFT_RAM_LINE_TTL_MASK
- GFT_RAM_LINE_TTL_SHIFT
- GFT_RAM_LINE_TUNNEL_DSCP_MASK
- GFT_RAM_LINE_TUNNEL_DSCP_SHIFT
- GFT_RAM_LINE_TUNNEL_DST_IP_MASK
- GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT
- GFT_RAM_LINE_TUNNEL_DST_MAC_MASK
- GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT
- GFT_RAM_LINE_TUNNEL_DST_PORT_MASK
- GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT
- GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK
- GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT
- GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK
- GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT
- GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK
- GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT
- GFT_RAM_LINE_TUNNEL_PRIORITY_MASK
- GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT
- GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK
- GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT
- GFT_RAM_LINE_TUNNEL_SRC_IP_MASK
- GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT
- GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK
- GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT
- GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK
- GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT
- GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK
- GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT
- GFT_RAM_LINE_TUNNEL_TTL_MASK
- GFT_RAM_LINE_TUNNEL_TTL_SHIFT
- GFT_RAM_LINE_TUNNEL_VLAN_MASK
- GFT_RAM_LINE_TUNNEL_VLAN_SHIFT
- GFT_RAM_LINE_VLAN_MASK
- GFT_RAM_LINE_VLAN_SELECT_MASK
- GFT_RAM_LINE_VLAN_SELECT_SHIFT
- GFT_RAM_LINE_VLAN_SHIFT
- GFT_REQUEST_SZ
- GFX064
- GFX10_MEC_HPD_SIZE
- GFX10_NUM_GFX_RINGS
- GFX1_PWR_GATER_BUSY
- GFX1_PWR_GATER_STATE
- GFX2D
- GFX2D0_AHB_CLK
- GFX2D0_AHB_RESET
- GFX2D0_CLK
- GFX2D0_RESET
- GFX2D0_SRC
- GFX2D1_AHB_CLK
- GFX2D1_AHB_RESET
- GFX2D1_CLK
- GFX2D1_RESET
- GFX2D1_SRC
- GFX2_PWR_GATER_BUSY
- GFX2_PWR_GATER_STATE
- GFX3D
- GFX3D_AHB_CLK
- GFX3D_AHB_RESET
- GFX3D_AXI_CLK
- GFX3D_AXI_RESET
- GFX3D_CLK
- GFX3D_CLK_SRC
- GFX3D_DMAC
- GFX3D_ISENSE_CLK
- GFX3D_ISENSE_CLK_SRC
- GFX3D_MBX
- GFX3D_RESET
- GFX3D_SRC
- GFX6_NUM_COMPUTE_RINGS
- GFX6_NUM_GFX_RINGS
- GFX7_MEC_HPD_SIZE
- GFX7_NUM_GFX_RINGS
- GFX8_MEC_HPD_SIZE
- GFX8_NUM_GFX_RINGS
- GFX9_MEC_HPD_SIZE
- GFX9_NUM_COMPUTE_RINGS
- GFX9_NUM_GFX_RINGS
- GFXCLK_SOURCE_AFLL
- GFXCLK_SOURCE_COUNT
- GFXCLK_SOURCE_DFLL
- GFXCLK_SOURCE_PLL
- GFXEC
- GFXGAM0
- GFXGAM1
- GFXGAM10
- GFXGAM11
- GFXGAM12
- GFXGAM13
- GFXGAM14
- GFXGAM15
- GFXGAM16
- GFXGAM2
- GFXGAM3
- GFXGAM4
- GFXGAM5
- GFXGAM6
- GFXGAM7
- GFXGAM8
- GFXGAM9
- GFXHUB_FREE_VM_INV_ENGS_BITMAP
- GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK
- GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK
- GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK
- GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK
- GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK
- GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK
- GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK
- GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK
- GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK
- GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK
- GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK
- GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK
- GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK
- GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- GFXTGHYST
- GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR
- GFX_10_1__SRCID__CP_COMPUTE_QUERY_STATUS
- GFX_10_1__SRCID__CP_CTX_BUSY_INTERRUPT
- GFX_10_1__SRCID__CP_CTX_EMPTY_INTERRUPT
- GFX_10_1__SRCID__CP_ECC_ERROR
- GFX_10_1__SRCID__CP_EOP_INTERRUPT
- GFX_10_1__SRCID__CP_FUE_ERROR
- GFX_10_1__SRCID__CP_GDS_ALLOC_ERROR
- GFX_10_1__SRCID__CP_GENERIC_INT
- GFX_10_1__SRCID__CP_GPF
- GFX_10_1__SRCID__CP_IB1_INTERRUPT_PKT
- GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT
- GFX_10_1__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT
- GFX_10_1__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR
- GFX_10_1__SRCID__CP_PREEMPT_ACK
- GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT
- GFX_10_1__SRCID__CP_PRIV_REG_FAULT
- GFX_10_1__SRCID__CP_RB_INTERRUPT_PKT
- GFX_10_1__SRCID__CP_SIG_INCOMPLETE
- GFX_10_1__SRCID__CP_VM_DOORBELL
- GFX_10_1__SRCID__CP_WAIT_MEM_SEM_FAULT
- GFX_10_1__SRCID__GRBM_RD_TIMEOUT_ERROR
- GFX_10_1__SRCID__GRBM_REG_GUI_IDLE
- GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT
- GFX_10_1__SRCID__SQ_INTERRUPT_ID
- GFX_6_0_D_H
- GFX_6_0_SH_MASK_H
- GFX_7_0_D_H
- GFX_7_2_D_H
- GFX_7_2_ENUM_H
- GFX_7_2_SH_MASK_H
- GFX_8_0_D_H
- GFX_8_0_ENUM_H
- GFX_8_0_SH_MASK_H
- GFX_8_1_D_H
- GFX_8_1_ENUM_H
- GFX_8_1_SH_MASK_H
- GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR
- GFX_9_0__SRCID__CP_COMPUTE_QUERY_STATUS
- GFX_9_0__SRCID__CP_CTX_BUSY_INTERRUPT
- GFX_9_0__SRCID__CP_CTX_EMPTY_INTERRUPT
- GFX_9_0__SRCID__CP_ECC_ERROR
- GFX_9_0__SRCID__CP_EOP_INTERRUPT
- GFX_9_0__SRCID__CP_FUE_ERROR
- GFX_9_0__SRCID__CP_GDS_ALLOC_ERROR
- GFX_9_0__SRCID__CP_GPF
- GFX_9_0__SRCID__CP_IB1_INTERRUPT_PKT
- GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT
- GFX_9_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT
- GFX_9_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR
- GFX_9_0__SRCID__CP_PREEMPT_ACK
- GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT
- GFX_9_0__SRCID__CP_PRIV_REG_FAULT
- GFX_9_0__SRCID__CP_RB_INTERRUPT_PKT
- GFX_9_0__SRCID__CP_SIG_INCOMPLETE
- GFX_9_0__SRCID__CP_VM_DOORBELL
- GFX_9_0__SRCID__CP_WAIT_MEM_SEM_FAULT
- GFX_9_0__SRCID__GRBM_RD_TIMEOUT_ERROR
- GFX_9_0__SRCID__GRBM_REG_GUI_IDLE
- GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT
- GFX_9_0__SRCID__SQ_INTERRUPT_ID
- GFX_BUF_MAX_DESC
- GFX_CLK_FORCE_OFF
- GFX_CLK_FORCE_ON
- GFX_CLK_OFF_ACPI_D1
- GFX_CLK_OFF_ACPI_D2
- GFX_CLK_OFF_ACPI_D3
- GFX_CLK_OFF_PWR_DOWN_EN
- GFX_CLK_REQUEST_OFF
- GFX_CLOCK
- GFX_CLOCK_STATUS
- GFX_CMD_ID_AUTOLOAD_RLC
- GFX_CMD_ID_DESTROY_TMR
- GFX_CMD_ID_DESTROY_VMR
- GFX_CMD_ID_INVOKE_CMD
- GFX_CMD_ID_LOAD_ASD
- GFX_CMD_ID_LOAD_IP_FW
- GFX_CMD_ID_LOAD_TA
- GFX_CMD_ID_LOAD_TOC
- GFX_CMD_ID_MASK
- GFX_CMD_ID_PROG_REG
- GFX_CMD_ID_SAVE_RESTORE
- GFX_CMD_ID_SETUP_TMR
- GFX_CMD_ID_SETUP_VMR
- GFX_CMD_ID_UNLOAD_TA
- GFX_CMD_RESERVED_MASK
- GFX_CMD_RESPONSE_MASK
- GFX_CMD_STATUS_MASK
- GFX_COPY_STATE__SRC_STATE_ID_MASK
- GFX_COPY_STATE__SRC_STATE_ID__SHIFT
- GFX_CTRL_CMD_ID_CAN_INIT_RINGS
- GFX_CTRL_CMD_ID_CONSUME_CMD
- GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING
- GFX_CTRL_CMD_ID_DESTROY_RINGS
- GFX_CTRL_CMD_ID_DISABLE_INT
- GFX_CTRL_CMD_ID_ENABLE_INT
- GFX_CTRL_CMD_ID_GBR_IH_SET
- GFX_CTRL_CMD_ID_INIT_GPCOM_RING
- GFX_CTRL_CMD_ID_INIT_RBI_RING
- GFX_CTRL_CMD_ID_MAX
- GFX_CTRL_CMD_ID_MODE1_RST
- GFX_CU_PG_MASK
- GFX_DATA
- GFX_DPA_SETTING
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK
- GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT
- GFX_FLAG_RESPONSE
- GFX_FLSH_CNTL
- GFX_FLSH_CNTL_EN
- GFX_FLSH_CNTL_GEN6
- GFX_FORWARD_VBLANK_ALWAYS
- GFX_FORWARD_VBLANK_COND
- GFX_FORWARD_VBLANK_MASK
- GFX_FORWARD_VBLANK_NEVER
- GFX_FW_TYPE_ACCUM_CTRL_RAM
- GFX_FW_TYPE_ACP
- GFX_FW_TYPE_CP_CE
- GFX_FW_TYPE_CP_ME
- GFX_FW_TYPE_CP_MEC
- GFX_FW_TYPE_CP_MEC_ME1
- GFX_FW_TYPE_CP_MEC_ME2
- GFX_FW_TYPE_CP_MES
- GFX_FW_TYPE_CP_PFP
- GFX_FW_TYPE_DMCU_ERAM
- GFX_FW_TYPE_DMCU_ISR
- GFX_FW_TYPE_DMUB
- GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM
- GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS
- GFX_FW_TYPE_GLOBAL_TAP_DELAYS
- GFX_FW_TYPE_ISP
- GFX_FW_TYPE_MAX
- GFX_FW_TYPE_MES_STACK
- GFX_FW_TYPE_MMSCH
- GFX_FW_TYPE_NONE
- GFX_FW_TYPE_RLCG_SCRATCH_SR
- GFX_FW_TYPE_RLCP_CAM
- GFX_FW_TYPE_RLCP_SCRATCH_SR
- GFX_FW_TYPE_RLCV_SCRATCH_SR
- GFX_FW_TYPE_RLC_G
- GFX_FW_TYPE_RLC_P
- GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM
- GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL
- GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM
- GFX_FW_TYPE_RLC_SPP_CAM_EXT
- GFX_FW_TYPE_RLC_SRM_DRAM_SR
- GFX_FW_TYPE_RLC_V
- GFX_FW_TYPE_RLX6
- GFX_FW_TYPE_RLX6_DRAM_BOOT
- GFX_FW_TYPE_RLX6_DRAM_SR
- GFX_FW_TYPE_SDMA0
- GFX_FW_TYPE_SDMA0_JT
- GFX_FW_TYPE_SDMA0_PG_CONTEXT
- GFX_FW_TYPE_SDMA1
- GFX_FW_TYPE_SDMA1_JT
- GFX_FW_TYPE_SDMA1_PG_CONTEXT
- GFX_FW_TYPE_SDMA2
- GFX_FW_TYPE_SDMA3
- GFX_FW_TYPE_SDMA4
- GFX_FW_TYPE_SDMA5
- GFX_FW_TYPE_SDMA6
- GFX_FW_TYPE_SDMA7
- GFX_FW_TYPE_SE0_MUX_SELECT_RAM
- GFX_FW_TYPE_SE0_TAP_DELAYS
- GFX_FW_TYPE_SE1_MUX_SELECT_RAM
- GFX_FW_TYPE_SE1_TAP_DELAYS
- GFX_FW_TYPE_SMU
- GFX_FW_TYPE_TOC
- GFX_FW_TYPE_UVD
- GFX_FW_TYPE_UVD1
- GFX_FW_TYPE_VCE
- GFX_FW_TYPE_VCN
- GFX_FW_TYPE_VCN0_RAM
- GFX_FW_TYPE_VCN1_RAM
- GFX_GAP_PWROK__gfx_gap_pwrok_MASK
- GFX_GAP_PWROK__gfx_gap_pwrok__SHIFT
- GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower_MASK
- GFX_GOLDEN_TSC_SHADOW_LOWER__GFXGoldenTscShadowLower__SHIFT
- GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper_MASK
- GFX_GOLDEN_TSC_SHADOW_UPPER__GFXGoldenTscShadowUpper__SHIFT
- GFX_HARVESTING_CU_ID
- GFX_HARVESTING_PRIM_ID
- GFX_HARVESTING_RB_ID
- GFX_HAVESTING_PARAMETERS
- GFX_INDEX
- GFX_INSTR
- GFX_INTERRUPT_STEERING
- GFX_INTR_A
- GFX_INTR_B
- GFX_INT_REQ
- GFX_INT_STATUS
- GFX_LS_STATUS
- GFX_MACRO_BYPASS_CNTL
- GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK
- GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK
- GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT
- GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK
- GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK
- GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT
- GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK
- GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK
- GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT
- GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK
- GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK
- GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT
- GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK
- GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK
- GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT
- GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK
- GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK
- GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT
- GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK
- GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK
- GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT
- GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK
- GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK
- GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT
- GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK
- GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK
- GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT
- GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK
- GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK
- GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT
- GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK
- GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK
- GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT
- GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK
- GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK
- GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT
- GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK
- GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK
- GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT
- GFX_MOD
- GFX_MODE
- GFX_MODE_BIT_SET_IN_MASK
- GFX_MODE_GEN7
- GFX_OFF_DELAY_ENABLE
- GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS
- GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS
- GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS
- GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS
- GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS
- GFX_OP_3DSTATE_DX9_CONSTANTF_PS
- GFX_OP_3DSTATE_DX9_CONSTANTF_VS
- GFX_OP_3DSTATE_SO_DECL_LIST
- GFX_OP_3DSTATE_VF_STATISTICS
- GFX_OP_BREAKPOINT_INTERRUPT
- GFX_OP_COLOR_FACTOR
- GFX_OP_DESTBUFFER_INFO
- GFX_OP_DESTBUFFER_VARS
- GFX_OP_DRAWRECT_INFO
- GFX_OP_DRAWRECT_INFO_I965
- GFX_OP_LOAD_INDIRECT
- GFX_OP_MAP_INFO
- GFX_OP_PIPE_CONTROL
- GFX_OP_PRIMITIVE
- GFX_OP_RASTER_RULES
- GFX_OP_SCISSOR
- GFX_OP_SCISSOR_ENABLE
- GFX_OP_SCISSOR_INFO
- GFX_OP_SCISSOR_RECT
- GFX_OP_STIPPLE
- GFX_OP_USER_INTERRUPT
- GFX_PG_ENABLE
- GFX_PG_SRC
- GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK
- GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT
- GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK
- GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT
- GFX_PIPE_CONTROL__RESERVED_MASK
- GFX_PIPE_CONTROL__RESERVED__SHIFT
- GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK
- GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT
- GFX_POWER_GATING_CNTL
- GFX_POWER_GATING_ENABLE
- GFX_POWER_GATING_SRC
- GFX_POWER_STATUS
- GFX_PPGTT_ENABLE
- GFX_PRIO
- GFX_PSMI_GRANULARITY
- GFX_PWR_GATER_BUSY
- GFX_PWR_GATER_STATE
- GFX_REPLAY_MODE
- GFX_RUN_LIST_ENABLE
- GFX_SURFACE_FAULT_ENABLE
- GFX_SWITCH
- GFX_TLB_INVALIDATE_EXPLICIT
- GFX_VOLTAGE_CHANGE_EN
- GFX_VOLTAGE_CHANGE_MODE
- GF_M
- GF_N
- GF_POLY_SZ
- GF_T
- GG2_INT_ACK_SPECIAL
- GG2_ISA_IO_BASE
- GG2_ISA_MEM_BASE
- GG2_PCI_ADDR_MAP
- GG2_PCI_BUSNO
- GG2_PCI_CC_CTRL
- GG2_PCI_CONFIG_BASE
- GG2_PCI_DISCCTR
- GG2_PCI_DRAM_BANK0
- GG2_PCI_DRAM_BANK1
- GG2_PCI_DRAM_BANK2
- GG2_PCI_DRAM_BANK3
- GG2_PCI_DRAM_BANK4
- GG2_PCI_DRAM_BANK5
- GG2_PCI_DRAM_CTRL
- GG2_PCI_DRAM_TIME0
- GG2_PCI_DRAM_TIME1
- GG2_PCI_ERR_CTRL
- GG2_PCI_ERR_STATUS
- GG2_PCI_MEM_BASE
- GG2_PCI_PCI_CTRL
- GG2_PCI_PPC_CTRL
- GG2_PCI_ROM_CTRL
- GG2_PCI_ROM_TIME
- GG2_PCI_SUBBUSNO
- GG2_ROM_BASE0
- GG2_ROM_BASE1
- GG82563_CABLE_LENGTH_TABLE_SIZE
- GG82563_DSPD_CABLE_LENGTH
- GG82563_E_PHY_ID
- GG82563_ICR_DIS_PADDING
- GG82563_KMCR_PASS_FALSE_CARRIER
- GG82563_MAX_KMRN_RETRY
- GG82563_MIN_ALT_REG
- GG82563_MSCR_ASSERT_CRS_ON_TX
- GG82563_MSCR_TX_CLK_1000MBPS_25
- GG82563_MSCR_TX_CLK_100MBPS_25
- GG82563_MSCR_TX_CLK_10MBPS_2_5
- GG82563_MSCR_TX_CLK_MASK
- GG82563_PAGE_SHIFT
- GG82563_PHY_DSP_DISTANCE
- GG82563_PHY_INBAND_CTRL
- GG82563_PHY_KMRN_MODE_CTRL
- GG82563_PHY_MAC_SPEC_CTRL
- GG82563_PHY_PAGE_SELECT
- GG82563_PHY_PAGE_SELECT_ALT
- GG82563_PHY_PWR_MGMT_CTRL
- GG82563_PHY_SPEC_CTRL
- GG82563_PHY_SPEC_CTRL_2
- GG82563_PMCR_ENABLE_ELECTRICAL_IDLE
- GG82563_PSCR2_REVERSE_AUTO_NEG
- GG82563_PSCR_CROSSOVER_MODE_AUTO
- GG82563_PSCR_CROSSOVER_MODE_MASK
- GG82563_PSCR_CROSSOVER_MODE_MDI
- GG82563_PSCR_CROSSOVER_MODE_MDIX
- GG82563_PSCR_POLARITY_REVERSAL_DISABLE
- GG82563_REG
- GGC
- GGC_MEMORY_SIZE_1M
- GGC_MEMORY_SIZE_2M
- GGC_MEMORY_SIZE_2M_VT
- GGC_MEMORY_SIZE_3M_VT
- GGC_MEMORY_SIZE_4M_VT
- GGC_MEMORY_SIZE_MASK
- GGC_MEMORY_SIZE_NONE
- GGC_MEMORY_VT_ENABLED
- GGPIO
- GGPIO_OUT
- GGPIO_STM32_OTG_GCCFG_PWRDWN
- GGPIO_VAL
- GHASH_4_ENCRYPT_4_PARALLEL_DEC
- GHASH_4_ENCRYPT_4_PARALLEL_ENC
- GHASH_8_ENCRYPT_8_PARALLEL_AVX
- GHASH_8_ENCRYPT_8_PARALLEL_AVX2
- GHASH_BLOCK_SIZE
- GHASH_DIGEST_SIZE
- GHASH_LAST_4
- GHASH_LAST_8_AVX
- GHASH_LAST_8_AVX2
- GHASH_MUL
- GHASH_MUL_AVX
- GHASH_MUL_AVX2
- GHAT_CMD
- GHC_DPX
- GHC_LINK_POLL
- GHC_SPEED
- GHC_SPEED_1000M
- GHC_SPEED_100M
- GHC_SPEED_10M
- GHC_SWRST
- GHC_TO_CLK_GPHY
- GHC_TO_CLK_INVALID
- GHC_TO_CLK_OFF
- GHC_TO_CLK_PCIE
- GHC_TO_CLK_SRC
- GHC_TXMAC_CLK_GPHY
- GHC_TXMAC_CLK_INVALID
- GHC_TXMAC_CLK_OFF
- GHC_TXMAC_CLK_PCIE
- GHC_TXMAC_CLK_SRC
- GHES_ESOURCE_PREALLOC_MAX_SIZE
- GHES_ESTATUS_CACHES_SIZE
- GHES_ESTATUS_CACHE_ALLOCED_MAX
- GHES_ESTATUS_CACHE_AVG_SIZE
- GHES_ESTATUS_CACHE_LEN
- GHES_ESTATUS_FROM_CACHE
- GHES_ESTATUS_FROM_NODE
- GHES_ESTATUS_IN_CACHE_MAX_NSEC
- GHES_ESTATUS_MAX_SIZE
- GHES_ESTATUS_NODE_LEN
- GHES_ESTATUS_POOL_MIN_ALLOC_ORDER
- GHES_EXITING
- GHES_H
- GHES_PFX
- GHES_SEV_CORRECTED
- GHES_SEV_NO
- GHES_SEV_PANIC
- GHES_SEV_RECOVERABLE
- GHWCFG1
- GHWCFG2
- GHWCFG2_ARCHITECTURE_MASK
- GHWCFG2_ARCHITECTURE_SHIFT
- GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK
- GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT
- GHWCFG2_DYNAMIC_FIFO
- GHWCFG2_EXT_DMA_ARCH
- GHWCFG2_FS_PHY_TYPE_DEDICATED
- GHWCFG2_FS_PHY_TYPE_MASK
- GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED
- GHWCFG2_FS_PHY_TYPE_SHARED_ULPI
- GHWCFG2_FS_PHY_TYPE_SHARED_UTMI
- GHWCFG2_FS_PHY_TYPE_SHIFT
- GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK
- GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT
- GHWCFG2_HS_PHY_TYPE_MASK
- GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED
- GHWCFG2_HS_PHY_TYPE_SHIFT
- GHWCFG2_HS_PHY_TYPE_ULPI
- GHWCFG2_HS_PHY_TYPE_UTMI
- GHWCFG2_HS_PHY_TYPE_UTMI_ULPI
- GHWCFG2_INT_DMA_ARCH
- GHWCFG2_MULTI_PROC_INT
- GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK
- GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT
- GHWCFG2_NUM_DEV_EP_MASK
- GHWCFG2_NUM_DEV_EP_SHIFT
- GHWCFG2_NUM_HOST_CHAN_MASK
- GHWCFG2_NUM_HOST_CHAN_SHIFT
- GHWCFG2_OP_MODE_HNP_SRP_CAPABLE
- GHWCFG2_OP_MODE_MASK
- GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE
- GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE
- GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST
- GHWCFG2_OP_MODE_SHIFT
- GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE
- GHWCFG2_OP_MODE_SRP_CAPABLE_HOST
- GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE
- GHWCFG2_OP_MODE_UNDEFINED
- GHWCFG2_OTG_ENABLE_IC_USB
- GHWCFG2_PERIO_EP_SUPPORTED
- GHWCFG2_POINT2POINT
- GHWCFG2_SLAVE_ONLY_ARCH
- GHWCFG3
- GHWCFG3_ADP_SUPP
- GHWCFG3_BC_SUPPORT
- GHWCFG3_DFIFO_DEPTH_MASK
- GHWCFG3_DFIFO_DEPTH_SHIFT
- GHWCFG3_I2C
- GHWCFG3_OPTIONAL_FEATURES
- GHWCFG3_OTG_ENABLE_HSIC
- GHWCFG3_OTG_FUNC
- GHWCFG3_OTG_LPM_EN
- GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK
- GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT
- GHWCFG3_SYNCH_RESET_TYPE
- GHWCFG3_VENDOR_CTRL_IF
- GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK
- GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT
- GHWCFG4
- GHWCFG4_ACG_SUPPORTED
- GHWCFG4_A_VALID_FILT_EN
- GHWCFG4_B_VALID_FILT_EN
- GHWCFG4_DED_FIFO_EN
- GHWCFG4_DED_FIFO_SHIFT
- GHWCFG4_DESC_DMA
- GHWCFG4_DESC_DMA_DYN
- GHWCFG4_HIBER
- GHWCFG4_IDDIG_FILT_EN
- GHWCFG4_IPG_ISOC_SUPPORTED
- GHWCFG4_MIN_AHB_FREQ
- GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK
- GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT
- GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK
- GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT
- GHWCFG4_NUM_IN_EPS_MASK
- GHWCFG4_NUM_IN_EPS_SHIFT
- GHWCFG4_POWER_OPTIMIZ
- GHWCFG4_SERVICE_INTERVAL_SUPPORTED
- GHWCFG4_SESSION_END_FILT_EN
- GHWCFG4_UTMI_PHY_DATA_WIDTH_16
- GHWCFG4_UTMI_PHY_DATA_WIDTH_8
- GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16
- GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK
- GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT
- GHWCFG4_VBUS_VALID_FILT_EN
- GHWCFG4_XHIBER
- GHZ24_50
- GHZ_24
- GHZ_50
- GHZ_MAX
- GI14_2K_SYR_LOCK
- GI14_8K_SYR_LOCK
- GI14_SYR_LOCK
- GI2CCTL
- GI2CCTL_ACK
- GI2CCTL_ADDR_MASK
- GI2CCTL_ADDR_SHIFT
- GI2CCTL_BSYDNE
- GI2CCTL_I2CDATSE0
- GI2CCTL_I2CDEVADDR_MASK
- GI2CCTL_I2CDEVADDR_SHIFT
- GI2CCTL_I2CEN
- GI2CCTL_I2CSUSPCTL
- GI2CCTL_REGADDR_MASK
- GI2CCTL_REGADDR_SHIFT
- GI2CCTL_RW
- GI2CCTL_RWDATA_MASK
- GI2CCTL_RWDATA_SHIFT
- GI2C_PORT
- GIB_CONTROL
- GIB_FCS_STRIP
- GIB_FCS_STRIP_SHIFT
- GIB_GTX_CLK_125MHZ
- GIB_GTX_CLK_250MHZ
- GIB_GTX_CLK_EXT_CLK
- GIB_GTX_CLK_SEL_SHIFT
- GIB_IPG_LEN_MASK
- GIB_IPG_LEN_SHIFT
- GIB_LCL_LOOP_EN
- GIB_LCL_LOOP_TXEN
- GIB_MAC0
- GIB_MAC1
- GIB_PAD_EXTENSION_MASK
- GIB_PAD_EXTENSION_SHIFT
- GIB_PREAMBLE_LEN_MASK
- GIB_PREAMBLE_LEN_SHIFT
- GIB_RMT_LOOP_EN
- GIB_RMT_LOOP_RXEN
- GIB_RX_EN
- GIB_RX_FLUSH
- GIB_RX_PAUSE_EN
- GIB_TX_EN
- GIB_TX_FLUSH
- GIC
- GICC_ARCH_VERSION_V2
- GICC_DIS_BYPASS_MASK
- GICC_ENABLE
- GICC_IAR_INT_ID_MASK
- GICC_INT_PRI_THRESHOLD
- GICC_INT_SPURIOUS
- GICD_CLRSPI_NSR
- GICD_CLRSPI_SR
- GICD_CPENDSGIR
- GICD_CTLR
- GICD_CTLR_ARE_NS
- GICD_CTLR_DS
- GICD_CTLR_ENABLE_G1
- GICD_CTLR_ENABLE_G1A
- GICD_CTLR_ENABLE_SS_G0
- GICD_CTLR_ENABLE_SS_G1
- GICD_CTLR_RWP
- GICD_DISABLE
- GICD_ENABLE
- GICD_ICACTIVER
- GICD_ICACTIVERnE
- GICD_ICENABLER
- GICD_ICENABLERnE
- GICD_ICFGR
- GICD_ICFGRnE
- GICD_ICPENDR
- GICD_ICPENDRnE
- GICD_IDREGS
- GICD_IGROUPR
- GICD_IGROUPRnE
- GICD_IGRPMODR
- GICD_IIDR
- GICD_IIDR_IMPLEMENTER_MASK
- GICD_IIDR_IMPLEMENTER_SHIFT
- GICD_IIDR_PRODUCT_ID_MASK
- GICD_IIDR_PRODUCT_ID_SHIFT
- GICD_IIDR_REVISION_MASK
- GICD_IIDR_REVISION_SHIFT
- GICD_IIDR_VARIANT_MASK
- GICD_IIDR_VARIANT_SHIFT
- GICD_INT_ACTLOW_LVLTRIG
- GICD_INT_DEF_PRI
- GICD_INT_DEF_PRI_X4
- GICD_INT_EN_CLR_PPI
- GICD_INT_EN_CLR_X32
- GICD_INT_EN_SET_SGI
- GICD_INT_NMI_PRI
- GICD_IPRIORITYR
- GICD_IPRIORITYRnE
- GICD_IROUTER
- GICD_IROUTER_SPI_MODE_ANY
- GICD_IROUTER_SPI_MODE_ONE
- GICD_IROUTERnE
- GICD_ISACTIVER
- GICD_ISACTIVERnE
- GICD_ISENABLER
- GICD_ISENABLERnE
- GICD_ISPENDR
- GICD_ISPENDRnE
- GICD_ITARGETSR
- GICD_NSACR
- GICD_PIDR2
- GICD_SEIR
- GICD_SETSPI_NSR
- GICD_SETSPI_SR
- GICD_SGIR
- GICD_SPENDSGIR
- GICD_STATUSR
- GICD_TYPER
- GICD_TYPER_ESPI
- GICD_TYPER_ESPIS
- GICD_TYPER_ID_BITS
- GICD_TYPER_LPIS
- GICD_TYPER_MBIS
- GICD_TYPER_NUM_LPIS
- GICD_TYPER_RSS
- GICD_TYPER_SPIS
- GICH_APR
- GICH_EISR0
- GICH_EISR1
- GICH_ELRSR0
- GICH_ELRSR1
- GICH_HCR
- GICH_HCR_EN
- GICH_HCR_NPIE
- GICH_HCR_UIE
- GICH_LR0
- GICH_LR_ACTIVE_BIT
- GICH_LR_EOI
- GICH_LR_GROUP1
- GICH_LR_HW
- GICH_LR_PENDING_BIT
- GICH_LR_PHYSID_CPUID
- GICH_LR_PHYSID_CPUID_SHIFT
- GICH_LR_PRIORITY_SHIFT
- GICH_LR_STATE
- GICH_LR_VIRTUALID
- GICH_MISR
- GICH_MISR_EOI
- GICH_MISR_U
- GICH_VMCR
- GICH_VMCR_ACK_CTL_MASK
- GICH_VMCR_ACK_CTL_SHIFT
- GICH_VMCR_ALIAS_BINPOINT_MASK
- GICH_VMCR_ALIAS_BINPOINT_SHIFT
- GICH_VMCR_BINPOINT_MASK
- GICH_VMCR_BINPOINT_SHIFT
- GICH_VMCR_CBPR_MASK
- GICH_VMCR_CBPR_SHIFT
- GICH_VMCR_ENABLE_GRP0_MASK
- GICH_VMCR_ENABLE_GRP0_SHIFT
- GICH_VMCR_ENABLE_GRP1_MASK
- GICH_VMCR_ENABLE_GRP1_SHIFT
- GICH_VMCR_EOI_MODE_MASK
- GICH_VMCR_EOI_MODE_SHIFT
- GICH_VMCR_FIQ_EN_MASK
- GICH_VMCR_FIQ_EN_SHIFT
- GICH_VMCR_PRIMASK_MASK
- GICH_VMCR_PRIMASK_SHIFT
- GICH_VTR
- GICP_CLRSPI_NSR_OFFSET
- GICP_ODMIN_GM_EA_R0
- GICP_ODMIN_GM_EA_R1
- GICP_ODMIN_GM_EP_R0
- GICP_ODMIN_GM_EP_R1
- GICP_ODMIN_SET
- GICP_ODMI_INT_NUM_SHIFT
- GICP_SECR
- GICP_SEMR
- GICP_SETSPI_NSR_OFFSET
- GICP_SET_SEI_OFFSET
- GICR_CLRLPIR
- GICR_CTLR
- GICR_CTLR_ENABLE_LPIS
- GICR_CTLR_RWP
- GICR_ICACTIVER0
- GICR_ICENABLER0
- GICR_ICFGR0
- GICR_ICPENDR0
- GICR_IDREGS
- GICR_IGROUPR0
- GICR_IGRPMODR0
- GICR_IIDR
- GICR_INVALLR
- GICR_INVLPIR
- GICR_IPRIORITYR0
- GICR_ISACTIVER0
- GICR_ISENABLER0
- GICR_ISPENDR0
- GICR_MOVALLR
- GICR_MOVLPIR
- GICR_NSACR
- GICR_PENDBASER
- GICR_PENDBASER_ADDRESS
- GICR_PENDBASER_CACHEABILITY_MASK
- GICR_PENDBASER_INNER_CACHEABILITY_MASK
- GICR_PENDBASER_INNER_CACHEABILITY_SHIFT
- GICR_PENDBASER_InnerShareable
- GICR_PENDBASER_OUTER_CACHEABILITY_MASK
- GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT
- GICR_PENDBASER_PTZ
- GICR_PENDBASER_RaWaWb
- GICR_PENDBASER_RaWaWt
- GICR_PENDBASER_RaWb
- GICR_PENDBASER_RaWt
- GICR_PENDBASER_SHAREABILITY_MASK
- GICR_PENDBASER_SHAREABILITY_SHIFT
- GICR_PENDBASER_WaWb
- GICR_PENDBASER_WaWt
- GICR_PENDBASER_nC
- GICR_PENDBASER_nCnB
- GICR_PIDR2
- GICR_PROPBASER
- GICR_PROPBASER_ADDRESS
- GICR_PROPBASER_CACHEABILITY_MASK
- GICR_PROPBASER_IDBITS_MASK
- GICR_PROPBASER_INNER_CACHEABILITY_MASK
- GICR_PROPBASER_INNER_CACHEABILITY_SHIFT
- GICR_PROPBASER_InnerShareable
- GICR_PROPBASER_OUTER_CACHEABILITY_MASK
- GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT
- GICR_PROPBASER_RaWaWb
- GICR_PROPBASER_RaWaWt
- GICR_PROPBASER_RaWb
- GICR_PROPBASER_RaWt
- GICR_PROPBASER_SHAREABILITY_MASK
- GICR_PROPBASER_SHAREABILITY_SHIFT
- GICR_PROPBASER_WaWb
- GICR_PROPBASER_WaWt
- GICR_PROPBASER_nC
- GICR_PROPBASER_nCnB
- GICR_SEIR
- GICR_SETLPIR
- GICR_STATUSR
- GICR_SYNCR
- GICR_TYPER
- GICR_TYPER_CPU_NUMBER
- GICR_TYPER_DirectLPIS
- GICR_TYPER_LAST
- GICR_TYPER_NR_PPIS
- GICR_TYPER_PLPIS
- GICR_TYPER_VLPIS
- GICR_VPENDBASER
- GICR_VPENDBASER_CACHEABILITY_MASK
- GICR_VPENDBASER_Dirty
- GICR_VPENDBASER_IDAI
- GICR_VPENDBASER_INNER_CACHEABILITY_MASK
- GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT
- GICR_VPENDBASER_NonShareable
- GICR_VPENDBASER_OUTER_CACHEABILITY_MASK
- GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT
- GICR_VPENDBASER_PendingLast
- GICR_VPENDBASER_RaWaWb
- GICR_VPENDBASER_RaWaWt
- GICR_VPENDBASER_RaWb
- GICR_VPENDBASER_RaWt
- GICR_VPENDBASER_SHAREABILITY_MASK
- GICR_VPENDBASER_SHAREABILITY_SHIFT
- GICR_VPENDBASER_Valid
- GICR_VPENDBASER_WaWb
- GICR_VPENDBASER_WaWt
- GICR_VPENDBASER_nC
- GICR_VPENDBASER_nCnB
- GICR_VPROPBASER
- GICR_VPROPBASER_CACHEABILITY_MASK
- GICR_VPROPBASER_IDBITS_MASK
- GICR_VPROPBASER_INNER_CACHEABILITY_MASK
- GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT
- GICR_VPROPBASER_InnerShareable
- GICR_VPROPBASER_OUTER_CACHEABILITY_MASK
- GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT
- GICR_VPROPBASER_RaWaWb
- GICR_VPROPBASER_RaWaWt
- GICR_VPROPBASER_RaWb
- GICR_VPROPBASER_RaWt
- GICR_VPROPBASER_SHAREABILITY_MASK
- GICR_VPROPBASER_SHAREABILITY_SHIFT
- GICR_VPROPBASER_WaWb
- GICR_VPROPBASER_WaWt
- GICR_VPROPBASER_nC
- GICR_VPROPBASER_nCnB
- GICR_WAKER
- GICR_WAKER_ChildrenAsleep
- GICR_WAKER_ProcessorSleep
- GICV2M_GRAVITON_ADDRESS_ONLY
- GICV2M_NEEDS_SPI_OFFSET
- GICV_PMR_PRIORITY_MASK
- GICV_PMR_PRIORITY_SHIFT
- GIC_ACCESSOR_RO
- GIC_ACCESSOR_RO_INTR_BIT
- GIC_ACCESSOR_RO_INTR_REG
- GIC_ACCESSOR_RW
- GIC_ACCESSOR_RW_INTR_BIT
- GIC_ACCESSOR_RW_INTR_REG
- GIC_ADDRSPACE_SZ
- GIC_BASER_CACHEABILITY
- GIC_BASER_CACHE_MASK
- GIC_BASER_CACHE_RaWaWb
- GIC_BASER_CACHE_RaWaWt
- GIC_BASER_CACHE_RaWb
- GIC_BASER_CACHE_RaWt
- GIC_BASER_CACHE_SameAsInner
- GIC_BASER_CACHE_WaWb
- GIC_BASER_CACHE_WaWt
- GIC_BASER_CACHE_nC
- GIC_BASER_CACHE_nCnB
- GIC_BASER_InnerShareable
- GIC_BASER_NonShareable
- GIC_BASER_OuterShareable
- GIC_BASER_SHAREABILITY
- GIC_BASER_SHAREABILITY_MASK
- GIC_BASE_ADDR
- GIC_BIT
- GIC_CONFIG_COUNTBITS
- GIC_CONFIG_COUNTSTOP
- GIC_CONFIG_NUMINTERRUPTS
- GIC_CONFIG_PVPS
- GIC_CPU_ACTIVEPRIO
- GIC_CPU_ALIAS_BINPOINT
- GIC_CPU_BINPOINT
- GIC_CPU_CTRL
- GIC_CPU_CTRL_AckCtl
- GIC_CPU_CTRL_AckCtl_SHIFT
- GIC_CPU_CTRL_CBPR
- GIC_CPU_CTRL_CBPR_SHIFT
- GIC_CPU_CTRL_ENABLE
- GIC_CPU_CTRL_EOImodeNS
- GIC_CPU_CTRL_EOImodeNS_SHIFT
- GIC_CPU_CTRL_EnableGrp0
- GIC_CPU_CTRL_EnableGrp0_SHIFT
- GIC_CPU_CTRL_EnableGrp1
- GIC_CPU_CTRL_EnableGrp1_SHIFT
- GIC_CPU_CTRL_FIQEn
- GIC_CPU_CTRL_FIQEn_SHIFT
- GIC_CPU_DEACTIVATE
- GIC_CPU_EOI
- GIC_CPU_HIGHPRI
- GIC_CPU_IDENT
- GIC_CPU_INTACK
- GIC_CPU_MASK_RAW
- GIC_CPU_MASK_SIMPLE
- GIC_CPU_PIN_OFFSET
- GIC_CPU_PRIMASK
- GIC_CPU_RUNNINGPRI
- GIC_DIST_ACTIVE_CLEAR
- GIC_DIST_ACTIVE_SET
- GIC_DIST_CONFIG
- GIC_DIST_CTR
- GIC_DIST_CTRL
- GIC_DIST_ENABLE_CLEAR
- GIC_DIST_ENABLE_SET
- GIC_DIST_IGROUP
- GIC_DIST_IIDR
- GIC_DIST_PENDING_CLEAR
- GIC_DIST_PENDING_SET
- GIC_DIST_PRI
- GIC_DIST_SGI_PENDING_CLEAR
- GIC_DIST_SGI_PENDING_SET
- GIC_DIST_SOFTINT
- GIC_DIST_TARGET
- GIC_DUAL_DUAL
- GIC_DUAL_SINGLE
- GIC_ENCODE_SZ
- GIC_ESPI_NR
- GIC_HWIRQ_TO_LOCAL
- GIC_HWIRQ_TO_SHARED
- GIC_ID_NR
- GIC_INT_SET_PENDING_BASE
- GIC_IRQ_START
- GIC_IRQ_TYPE_LPI
- GIC_IRQ_TYPE_PARTITION
- GIC_LINE_NR
- GIC_LOCAL
- GIC_LOCAL_HWIRQ_BASE
- GIC_LOCAL_TO_HWIRQ
- GIC_LPI_OFFSET
- GIC_MAP_PIN_MAP
- GIC_MAP_PIN_MAP_TO_NMI
- GIC_MAP_PIN_MAP_TO_PIN
- GIC_MAX_INTRS
- GIC_MAX_LONGS
- GIC_MAX_OFFSET
- GIC_NCPU_OFFSET
- GIC_NUM_INTRS
- GIC_PIDR2_ARCH_GICv3
- GIC_PIDR2_ARCH_GICv4
- GIC_PIDR2_ARCH_MASK
- GIC_PIN_TO_VEC_OFFSET
- GIC_POL_ACTIVE_HIGH
- GIC_POL_ACTIVE_LOW
- GIC_POL_FALLING_EDGE
- GIC_POL_RISING_EDGE
- GIC_PPI
- GIC_PRIO_IRQOFF
- GIC_PRIO_IRQON
- GIC_PRIO_PSR_I_SET
- GIC_PTCE
- GIC_PTME
- GIC_SECTION
- GIC_SHARED
- GIC_SHARED_HWIRQ_BASE
- GIC_SHARED_TO_HWIRQ
- GIC_SPI
- GIC_TRIG_EDGE
- GIC_TRIG_LEVEL
- GIC_V2
- GIC_V3
- GIC_V3_CFG
- GIC_V3_CFG_SHIFT
- GIC_V3_DIST_SIZE
- GIC_V3_REDIST_SIZE
- GIC_VX_ACCESSOR_RO
- GIC_VX_ACCESSOR_RO_INTR_BIT
- GIC_VX_ACCESSOR_RO_INTR_REG
- GIC_VX_ACCESSOR_RW
- GIC_VX_ACCESSOR_RW_INTR_BIT
- GIC_VX_ACCESSOR_RW_INTR_REG
- GIC_VX_CTL_EIC
- GIC_VX_CTL_FDC_ROUTABLE
- GIC_VX_CTL_PERFCNT_ROUTABLE
- GIC_VX_CTL_SWINT_ROUTABLE
- GIC_VX_CTL_TIMER_ROUTABLE
- GIC_VX_IDENT_VPNUM
- GIC_VX_OTHER_VPNUM
- GIC_WEDGE_INTR
- GIC_WEDGE_RW
- GICv3_IDLE_PRIORITY
- GICv4_ITS_LIST_MAX
- GID
- GIDFF_REQUEST_SZ
- GID_ADD
- GID_ATCD0
- GID_ATCD1
- GID_ATCD10
- GID_ATCD11
- GID_ATCD12
- GID_ATCD13
- GID_ATCD14
- GID_ATCD15
- GID_ATCD2
- GID_ATCD3
- GID_ATCD4
- GID_ATCD5
- GID_ATCD6
- GID_ATCD7
- GID_ATCD8
- GID_ATCD9
- GID_ATTR_FIND_MASK_DEFAULT
- GID_ATTR_FIND_MASK_GID
- GID_ATTR_FIND_MASK_GID_TYPE
- GID_ATTR_FIND_MASK_NETDEV
- GID_BIT
- GID_DEL
- GID_HASHBITS
- GID_HASHMAX
- GID_LEN
- GID_LEN_V2
- GID_PN_CMD
- GID_PN_REQ_SIZE
- GID_PN_RSP_SIZE
- GID_PTCD
- GID_PTMD0
- GID_PTMD1
- GID_PTMD2
- GID_PTMD3
- GID_PTMD4
- GID_PTMD5
- GID_PTMD6
- GID_PTMD7
- GID_PTOD
- GID_PT_CMD
- GID_PT_N_PORT
- GID_PT_REQ_SIZE
- GID_PT_SNS_CMD_SIZE
- GID_PT_SNS_DATA_SIZE
- GID_PT_SNS_SCMD_LEN
- GID_REQUEST_SZ
- GID_TABLE_ENTRY_INVALID
- GID_TABLE_ENTRY_PENDING_DEL
- GID_TABLE_ENTRY_VALID
- GID_TO_GRU
- GID_TYPE_FLAG_ROCE_V1
- GID_TYPE_FLAG_ROCE_V2_IPV4
- GID_TYPE_FLAG_ROCE_V2_IPV6
- GID_T_MAX
- GIE
- GIE_ATCS0
- GIE_ATCS1
- GIE_ATCS10
- GIE_ATCS11
- GIE_ATCS12
- GIE_ATCS13
- GIE_ATCS14
- GIE_ATCS15
- GIE_ATCS2
- GIE_ATCS3
- GIE_ATCS4
- GIE_ATCS5
- GIE_ATCS6
- GIE_ATCS7
- GIE_ATCS8
- GIE_ATCS9
- GIE_BIT
- GIE_DISABLE
- GIE_ENABLE
- GIE_PTCS
- GIE_PTMS0
- GIE_PTMS1
- GIE_PTMS2
- GIE_PTMS3
- GIE_PTMS4
- GIE_PTMS5
- GIE_PTMS6
- GIE_PTMS7
- GIE_PTOS
- GIF_ALLOC_FAILED
- GIF_FREE_VFS_INODE
- GIF_GLOP_PENDING
- GIF_INVALID
- GIF_ORDERED
- GIF_QD_LOCKED
- GIF_SW_PAGED
- GIGASET_BRKCHARS
- GIGASET_CONFIG
- GIGASET_DEVNAME
- GIGASET_H
- GIGASET_INTERFACE_H
- GIGASET_IOCTL
- GIGASET_MINOR
- GIGASET_MINORS
- GIGASET_MODULENAME
- GIGASET_REDIR
- GIGASET_VERSION
- GIGA_CR_1000T_DEFAULT_CAP
- GIGA_CR_1000T_MS_ENABLE
- GIGA_CR_1000T_MS_VALUE
- GIGA_CR_1000T_REPEATER_DTE
- GIGA_CR_1000T_SPEED_MASK
- GIGA_CR_1000T_TEST_MODE_1
- GIGA_CR_1000T_TEST_MODE_2
- GIGA_CR_1000T_TEST_MODE_3
- GIGA_CR_1000T_TEST_MODE_4
- GIGA_CR_1000T_TEST_MODE_NORMAL
- GIGA_MAHR
- GIGA_MALR
- GIGA_PSSR_1000MBS
- GIGA_PSSR_100MBS
- GIGA_PSSR_10MBS
- GIGA_PSSR_DPLX
- GIGA_PSSR_SPD_DPLX_RESOLVED
- GIGA_PSSR_SPEED
- GIGVER_COMPAT
- GIGVER_DRIVER
- GIGVER_FWBASE
- GIG_COMPAT
- GIG_TICK
- GIG_VERSION
- GIMR
- GIMSK_CCIC_EN
- GINA20
- GINA24
- GINTMSK
- GINTMSK2
- GINTMSK2_WKUP_ALERT_INT_MSK
- GINTMSK_COMMON
- GINTSTS
- GINTSTS2
- GINTSTS2_WKUP_ALERT_INT
- GINTSTS_CONIDSTSCHNG
- GINTSTS_CURMODE_HOST
- GINTSTS_DISCONNINT
- GINTSTS_ENUMDONE
- GINTSTS_EOPF
- GINTSTS_EPMIS
- GINTSTS_ERLYSUSP
- GINTSTS_FET_SUSP
- GINTSTS_GINNAKEFF
- GINTSTS_GOUTNAKEFF
- GINTSTS_HCHINT
- GINTSTS_I2CINT
- GINTSTS_IEPINT
- GINTSTS_INCOMPL_IP
- GINTSTS_INCOMPL_SOIN
- GINTSTS_INCOMPL_SOOUT
- GINTSTS_ISOUTDROP
- GINTSTS_LPMTRANRCVD
- GINTSTS_MODEMIS
- GINTSTS_NPTXFEMP
- GINTSTS_OEPINT
- GINTSTS_OTGINT
- GINTSTS_PRTINT
- GINTSTS_PTXFEMP
- GINTSTS_RESETDET
- GINTSTS_RESTOREDONE
- GINTSTS_RXFLVL
- GINTSTS_SESSREQINT
- GINTSTS_SOF
- GINTSTS_ULPI_CK_INT
- GINTSTS_USBRST
- GINTSTS_USBSUSP
- GINTSTS_WKUPINT
- GINT_DIS
- GINVT_FULL
- GINVT_MMID
- GINVT_VA
- GIO
- GIOAdapter
- GIODRV_IOCGGIODATA1
- GIODRV_IOCGGIODATA2
- GIODRV_IOCGGIODATA4
- GIODRV_IOCHARDRESET
- GIODRV_IOCRESET
- GIODRV_IOCSGIODATA1
- GIODRV_IOCSGIODATA2
- GIODRV_IOCSGIODATA4
- GIODRV_IOCSGIOSETADDR
- GIODRV_IOC_MAGIC
- GIODRV_IOC_MAXNR
- GIOE
- GIO_32BIT_ID
- GIO_64BIT_IFACE
- GIO_ASYNC
- GIO_BANK_OFF
- GIO_BANK_SIZE
- GIO_CMAP
- GIO_DATA
- GIO_DIRECT_BASE
- GIO_DRIVER_NAME
- GIO_E0
- GIO_E1
- GIO_EC
- GIO_EI
- GIO_EM
- GIO_ERRMASK
- GIO_FONT
- GIO_FONTX
- GIO_I
- GIO_ID
- GIO_IDS
- GIO_IDT
- GIO_IDT0
- GIO_IDT1
- GIO_IDT2
- GIO_IDT3
- GIO_IEN
- GIO_IIA
- GIO_IIM
- GIO_IIR
- GIO_IODIR
- GIO_IRBH
- GIO_IRBL
- GIO_LEVEL
- GIO_LOCAL_BASE
- GIO_MAPPED_BASE
- GIO_MASK
- GIO_MINOR
- GIO_MST
- GIO_ODEN
- GIO_OH
- GIO_OL
- GIO_OUT0_222
- GIO_OUT0_73
- GIO_OUT12
- GIO_OUT13
- GIO_OUT14
- GIO_OUT15
- GIO_OUT1_221
- GIO_OUT1_70
- GIO_OUT2_220
- GIO_OUT2_71
- GIO_OUT3_219
- GIO_OUT3_67
- GIO_OUT4_218
- GIO_OUT4_68
- GIO_OUT5_217
- GIO_OUT5_69
- GIO_OUT6
- GIO_OUT7
- GIO_OUT8
- GIO_OUT9
- GIO_PID_CONTROLLER_CNTL_0__K_I_MASK
- GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT
- GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK
- GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT
- GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK
- GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT
- GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK
- GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT
- GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK
- GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT
- GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK
- GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT
- GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK
- GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT
- GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK
- GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT
- GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK
- GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT
- GIO_RAW
- GIO_RAWBH
- GIO_RAWBL
- GIO_READ
- GIO_REG_DATA
- GIO_REG_EC
- GIO_REG_EI
- GIO_REG_IODIR
- GIO_REG_LEVEL
- GIO_REG_MASK
- GIO_REG_ODEN
- GIO_REG_STAT
- GIO_REV
- GIO_ROM_PRESENT
- GIO_SCRNMAP
- GIO_SLOT_EXP0_BASE
- GIO_SLOT_EXP1_BASE
- GIO_SLOT_GFX_BASE
- GIO_STAT
- GIO_UNIMAP
- GIO_UNISCRNMAP
- GIO_VENDOR_CODE
- GIO_WRITE
- GIP
- GIRQ_CF
- GIRQ_SGN_EN
- GIRQ_STS
- GIRQ_STS_EN
- GIRQ_XD
- GIRT_COUNT
- GIS
- GISA_ADDR_MASK
- GISA_FORMAT1
- GISB_ERR_IRQ
- GISR
- GIS_BIT
- GIS_PTCF
- GIS_PTMF
- GIS_RESERVED
- GIT
- GITR
- GITS_BASER
- GITS_BASER_ADDR_48_to_52
- GITS_BASER_CACHEABILITY_MASK
- GITS_BASER_ENTRY_SIZE
- GITS_BASER_ENTRY_SIZE_MASK
- GITS_BASER_ENTRY_SIZE_SHIFT
- GITS_BASER_INDIRECT
- GITS_BASER_INNER_CACHEABILITY_MASK
- GITS_BASER_INNER_CACHEABILITY_SHIFT
- GITS_BASER_InnerShareable
- GITS_BASER_NR_PAGES
- GITS_BASER_NR_REGS
- GITS_BASER_OUTER_CACHEABILITY_MASK
- GITS_BASER_OUTER_CACHEABILITY_SHIFT
- GITS_BASER_PAGES_MAX
- GITS_BASER_PAGES_SHIFT
- GITS_BASER_PAGE_SIZE_16K
- GITS_BASER_PAGE_SIZE_4K
- GITS_BASER_PAGE_SIZE_64K
- GITS_BASER_PAGE_SIZE_MASK
- GITS_BASER_PAGE_SIZE_SHIFT
- GITS_BASER_PHYS_52_to_48
- GITS_BASER_RO_MASK
- GITS_BASER_RaWaWb
- GITS_BASER_RaWaWt
- GITS_BASER_RaWb
- GITS_BASER_RaWt
- GITS_BASER_SHAREABILITY_MASK
- GITS_BASER_SHAREABILITY_SHIFT
- GITS_BASER_TYPE
- GITS_BASER_TYPE_COLLECTION
- GITS_BASER_TYPE_DEVICE
- GITS_BASER_TYPE_NONE
- GITS_BASER_TYPE_RESERVED3
- GITS_BASER_TYPE_RESERVED5
- GITS_BASER_TYPE_RESERVED6
- GITS_BASER_TYPE_RESERVED7
- GITS_BASER_TYPE_SHIFT
- GITS_BASER_TYPE_VCPU
- GITS_BASER_VALID
- GITS_BASER_WaWb
- GITS_BASER_WaWt
- GITS_BASER_nC
- GITS_BASER_nCnB
- GITS_CBASER
- GITS_CBASER_ADDRESS
- GITS_CBASER_CACHEABILITY_MASK
- GITS_CBASER_INNER_CACHEABILITY_MASK
- GITS_CBASER_INNER_CACHEABILITY_SHIFT
- GITS_CBASER_InnerShareable
- GITS_CBASER_OUTER_CACHEABILITY_MASK
- GITS_CBASER_OUTER_CACHEABILITY_SHIFT
- GITS_CBASER_RaWaWb
- GITS_CBASER_RaWaWt
- GITS_CBASER_RaWb
- GITS_CBASER_RaWt
- GITS_CBASER_SHAREABILITY_MASK
- GITS_CBASER_SHAREABILITY_SHIFT
- GITS_CBASER_VALID
- GITS_CBASER_WaWb
- GITS_CBASER_WaWt
- GITS_CBASER_nC
- GITS_CBASER_nCnB
- GITS_CIDR0
- GITS_CIDR1
- GITS_CIDR2
- GITS_CIDR3
- GITS_CMD_CLEAR
- GITS_CMD_DISCARD
- GITS_CMD_GICv4
- GITS_CMD_INT
- GITS_CMD_INV
- GITS_CMD_INVALL
- GITS_CMD_MAPC
- GITS_CMD_MAPD
- GITS_CMD_MAPI
- GITS_CMD_MAPTI
- GITS_CMD_MOVALL
- GITS_CMD_MOVI
- GITS_CMD_SYNC
- GITS_CMD_VINVALL
- GITS_CMD_VMAPP
- GITS_CMD_VMAPTI
- GITS_CMD_VMOVI
- GITS_CMD_VMOVP
- GITS_CMD_VSYNC
- GITS_CREADR
- GITS_CTLR
- GITS_CTLR_ENABLE
- GITS_CTLR_ITS_NUMBER
- GITS_CTLR_ITS_NUMBER_SHIFT
- GITS_CTLR_ImDe
- GITS_CTLR_QUIESCENT
- GITS_CWRITER
- GITS_IDREGS_BASE
- GITS_IIDR
- GITS_IIDR_PRODUCTID_SHIFT
- GITS_IIDR_REV
- GITS_IIDR_REV_MASK
- GITS_IIDR_REV_SHIFT
- GITS_LVL1_ENTRY_SIZE
- GITS_PIDR0
- GITS_PIDR1
- GITS_PIDR2
- GITS_PIDR4
- GITS_TRANSLATER
- GITS_TYPER
- GITS_TYPER_DEVBITS
- GITS_TYPER_DEVBITS_SHIFT
- GITS_TYPER_HCC
- GITS_TYPER_HCC_SHIFT
- GITS_TYPER_IDBITS_SHIFT
- GITS_TYPER_ITT_ENTRY_SIZE
- GITS_TYPER_ITT_ENTRY_SIZE_SHIFT
- GITS_TYPER_PLPIS
- GITS_TYPER_PTA
- GITS_TYPER_VLPIS
- GITS_TYPER_VMOVP
- GIT_COMPAT_UTIL_H
- GIUFEDGEINHH
- GIUFEDGEINHL
- GIUINTALSELH
- GIUINTALSELL
- GIUINTENH
- GIUINTENL
- GIUINTHREG
- GIUINTHTSELH
- GIUINTHTSELL
- GIUINTLREG
- GIUINTSTATH
- GIUINTSTATL
- GIUINTTYPH
- GIUINTTYPL
- GIUINT_HIGH_MAX
- GIUINT_HIGH_OFFSET
- GIUINT_IRQ
- GIUIOSELH
- GIUIOSELL
- GIUPIODH
- GIUPIODL
- GIUPODAT
- GIUPODATEN
- GIUPODATH
- GIUPODATL
- GIUREDGEINHH
- GIUREDGEINHL
- GIUTERMUPDN
- GIUUSEUPDN
- GIU_IRQ
- GIU_IRQ_BASE
- GIU_IRQ_LAST
- GIVEUP_LIMIT
- GI_420
- GI_595
- GI_660X_ALT_SYNC
- GI_660X_HW_ARM_SEL_MASK
- GI_660X_PRESCALE_X2
- GI_660X_PRESCALE_X8
- GI_945
- GI_ARM
- GI_ARMED
- GI_ARM_COPY
- GI_AUTO_INC_MASK
- GI_BANK_SWITCH_ENABLE
- GI_BANK_SWITCH_MODE
- GI_BANK_SWITCH_START
- GI_BITS_TO_GATE
- GI_BITS_TO_GATE2
- GI_BITS_TO_SRC
- GI_CHIP_ID
- GI_CNT_DIR
- GI_CNT_DIR_MASK
- GI_CNT_MODE
- GI_CNT_MODE_MASK
- GI_CNT_MODE_NORMAL
- GI_CNT_MODE_QUADX1
- GI_CNT_MODE_QUADX2
- GI_CNT_MODE_QUADX4
- GI_CNT_MODE_SYNC_SRC
- GI_CNT_MODE_TWO_PULSE
- GI_COUNTING
- GI_COUNTING_ONCE
- GI_COUNTING_ONCE_MASK
- GI_DEVICE_DESC_SIMPLE_RW
- GI_DEVICE_DESC_SIMPLE_R_u16
- GI_DEVICE_DESC_SIMPLE_R_u8
- GI_DEVICE_DESC_SIMPLE_W_u16
- GI_DEVICE_DESC_SIMPLE_W_u8
- GI_DISARM
- GI_DISARM_AT_GATE
- GI_DISARM_AT_TC
- GI_DISARM_AT_TC_OR_GATE
- GI_DISARM_COPY
- GI_DMA_BANKSW_ERROR
- GI_DMA_ENABLE
- GI_DMA_INT_ENA
- GI_DMA_READBANK
- GI_DMA_RESET
- GI_DMA_WRITE
- GI_DRQ_ERROR
- GI_DRQ_STATUS
- GI_EDGE_GATE_MODE
- GI_EDGE_GATE_MODE_MASK
- GI_EDGE_GATE_NO_STARTS_OR_STOPS
- GI_EDGE_GATE_STARTS
- GI_EDGE_GATE_STARTS_STOPS
- GI_EDGE_GATE_STOPS_STARTS
- GI_FALLING_EDGE_GATING
- GI_GATE2_MODE
- GI_GATE2_POL_INVERT
- GI_GATE2_SEL
- GI_GATE2_SEL_MASK
- GI_GATE2_SUBSEL
- GI_GATE_ERROR
- GI_GATE_ERROR_CONFIRM
- GI_GATE_INTERRUPT
- GI_GATE_INTERRUPT_ACK
- GI_GATE_INTERRUPT_ENABLE
- GI_GATE_ON_BOTH_EDGES
- GI_GATE_POL_INVERT
- GI_GATE_SEL
- GI_GATE_SEL_LOAD_SRC
- GI_GATE_SEL_MASK
- GI_GATING_DISABLED
- GI_GATING_MODE
- GI_GATING_MODE_MASK
- GI_HW_ARM_ENA
- GI_HW_ARM_SEL
- GI_HW_SAVE
- GI_INDEX_MODE
- GI_INDEX_PHASE
- GI_INDEX_PHASE_MASK
- GI_INTERRUPT
- GI_LEVEL_GATING
- GI_LITTLE_BIG_ENDIAN
- GI_LOAD
- GI_LOADING_ON_GATE
- GI_LOADING_ON_TC
- GI_LOAD_SRC_SEL
- GI_MASK
- GI_M_ALT_SYNC
- GI_M_HW_ARM_SEL_MASK
- GI_M_PRESCALE_X2
- GI_M_PRESCALE_X8
- GI_NEXT_LOAD_SRC
- GI_NO_HARDWARE_DISARM
- GI_NO_LOAD_BETWEEN_GATES
- GI_OR_GATE
- GI_OUTPUT
- GI_OUTPUT_MODE
- GI_OUTPUT_MODE_MASK
- GI_OUTPUT_POL_INVERT
- GI_OUTPUT_TC_OR_GATE_TOGGLE
- GI_OUTPUT_TC_PULSE
- GI_OUTPUT_TC_TOGGLE
- GI_PERMANENT_STALE
- GI_PRESCALE_X2
- GI_PRESCALE_X8
- GI_READ_ACKS_IRQ
- GI_RELOAD_SRC_SWITCHING
- GI_RESET
- GI_RISING_EDGE_GATING
- GI_SAVE
- GI_SAVE_TRACE
- GI_SAVE_TRACE_COPY
- GI_SRC_POL_INVERT
- GI_SRC_SEL
- GI_SRC_SEL_MASK
- GI_SRC_SUBSEL
- GI_STALE_DATA
- GI_STOP_MODE
- GI_STOP_MODE_MASK
- GI_STOP_ON_GATE
- GI_STOP_ON_GATE_OR_SECOND_TC
- GI_STOP_ON_GATE_OR_TC
- GI_SYNC_GATE
- GI_TC
- GI_TC_ERROR
- GI_TC_ERROR_CONFIRM
- GI_TC_INTERRUPT_ACK
- GI_TC_INTERRUPT_ENABLE
- GI_WRITE_ACKS_IRQ
- GI_WRITE_SWITCH
- GIoCR
- GIoCtrl
- GK104_DISP
- GK104_DISP_BASE_CHANNEL_DMA
- GK104_DISP_CORE_CHANNEL_DMA
- GK104_DISP_CURSOR
- GK104_DISP_OVERLAY
- GK104_DISP_OVERLAY_CONTROL_DMA
- GK104_MSPDEC
- GK104_MSVLD
- GK110_DISP
- GK110_DISP_BASE_CHANNEL_DMA
- GK110_DISP_CORE_CHANNEL_DMA
- GK20A_CLK_GPC_MDIV
- GL0V_CACHE_POLICIES
- GL0V_CACHE_POLICY_HIT_EVICT
- GL0V_CACHE_POLICY_HIT_LRU
- GL0V_CACHE_POLICY_MISS_EVICT
- GL0V_CACHE_POLICY_MISS_LRU
- GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- GL1A_PERF_SEL
- GL1A_PERF_SEL_ARB_REQUESTS
- GL1A_PERF_SEL_BUSY
- GL1A_PERF_SEL_CYCLE
- GL1A_PERF_SEL_IO_32B_WDS_GL1C0
- GL1A_PERF_SEL_IO_32B_WDS_GL1C1
- GL1A_PERF_SEL_IO_32B_WDS_GL1C2
- GL1A_PERF_SEL_IO_32B_WDS_GL1C3
- GL1A_PERF_SEL_IO_32B_WDS_GL1C4
- GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0
- GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1
- GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2
- GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3
- GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4
- GL1A_PERF_SEL_MEM_32B_WDS_GL1C0
- GL1A_PERF_SEL_MEM_32B_WDS_GL1C1
- GL1A_PERF_SEL_MEM_32B_WDS_GL1C2
- GL1A_PERF_SEL_MEM_32B_WDS_GL1C3
- GL1A_PERF_SEL_MEM_32B_WDS_GL1C4
- GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0
- GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1
- GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2
- GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3
- GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4
- GL1A_PERF_SEL_REQUEST_GL1C0
- GL1A_PERF_SEL_REQUEST_GL1C1
- GL1A_PERF_SEL_REQUEST_GL1C2
- GL1A_PERF_SEL_REQUEST_GL1C3
- GL1A_PERF_SEL_REQUEST_GL1C4
- GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL
- GL1A_PERF_SEL_STALL_GL1C0
- GL1A_PERF_SEL_STALL_GL1C1
- GL1A_PERF_SEL_STALL_GL1C2
- GL1A_PERF_SEL_STALL_GL1C3
- GL1A_PERF_SEL_STALL_GL1C4
- GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0
- GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1
- GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2
- GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3
- GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4
- GL1CG_PERF_SEL
- GL1CG_PERF_SEL_CORE_REG_SCLK_VLD
- GL1CG_PERF_SEL_CYCLE
- GL1CG_PERF_SEL_GATE_EN1
- GL1CG_PERF_SEL_GATE_EN2
- GL1CG_PERF_SEL_REQ
- GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES
- GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES
- GL1C_CTRL__ACK_QUEUE_DISABLE_MASK
- GL1C_CTRL__ACK_QUEUE_DISABLE__SHIFT
- GL1C_CTRL__FORCE_HIT_MASK
- GL1C_CTRL__FORCE_HIT__SHIFT
- GL1C_CTRL__FORCE_MISS_MASK
- GL1C_CTRL__FORCE_MISS__SHIFT
- GL1C_CTRL__HIT_QUEUE_DISABLE_MASK
- GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT
- GL1C_CTRL__LATENCY_FIFO_SIZE_MASK
- GL1C_CTRL__LATENCY_FIFO_SIZE__SHIFT
- GL1C_CTRL__NOFILL_32B_MASK
- GL1C_CTRL__NOFILL_32B__SHIFT
- GL1C_CTRL__NOFILL_64B_MASK
- GL1C_CTRL__NOFILL_64B__SHIFT
- GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE_MASK
- GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE__SHIFT
- GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- GL1C_PERF_SEL
- GL1C_PERF_SEL_CORE_REG_SCLK_VLD
- GL1C_PERF_SEL_CYCLE
- GL1C_PERF_SEL_GATE_EN1
- GL1C_PERF_SEL_GATE_EN2
- GL1C_PERF_SEL_REQ
- GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES
- GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES
- GL1C_STATUS__GL2_DATA_VC0_STALL_MASK
- GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT
- GL1C_STATUS__GL2_DATA_VC1_STALL_MASK
- GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT
- GL1C_STATUS__GL2_REQ_VC0_STALL_MASK
- GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT
- GL1C_STATUS__GL2_REQ_VC1_STALL_MASK
- GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT
- GL1C_STATUS__GL2_RH_BUSY_MASK
- GL1C_STATUS__GL2_RH_BUSY__SHIFT
- GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK
- GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT
- GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK
- GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT
- GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK
- GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT
- GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK
- GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT
- GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK
- GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT
- GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK
- GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT
- GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK
- GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT
- GL1C_STATUS__TAG_ACK_STALL_MASK
- GL1C_STATUS__TAG_ACK_STALL__SHIFT
- GL1C_STATUS__TAG_BUSY_MASK
- GL1C_STATUS__TAG_BUSY__SHIFT
- GL1C_STATUS__TAG_EVICT_MASK
- GL1C_STATUS__TAG_EVICT__SHIFT
- GL1C_STATUS__TAG_GCR_INV_STALL_MASK
- GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT
- GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK
- GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT
- GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK
- GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT
- GL1C_STATUS__TAG_STALL_MASK
- GL1C_STATUS__TAG_STALL__SHIFT
- GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK
- GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT
- GL1_ARB_CTRL__NUM_MEM_PIPES_MASK
- GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT
- GL1_ARB_STATUS__REQ_ARB_BUSY_MASK
- GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT
- GL1_ARB_STATUS__RET_ARB_BUSY_MASK
- GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT
- GL1_CACHE_POLICIES
- GL1_CACHE_POLICY_HIT_EVICT
- GL1_CACHE_POLICY_HIT_LRU
- GL1_CACHE_POLICY_MISS_EVICT
- GL1_CACHE_POLICY_MISS_LRU
- GL1_CACHE_STORE_POLICIES
- GL1_CACHE_STORE_POLICY_BYPASS
- GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK
- GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT
- GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK
- GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT
- GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK
- GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT
- GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK
- GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT
- GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK
- GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT
- GL1_PIPE_STEER__PIPE0_MASK
- GL1_PIPE_STEER__PIPE0__SHIFT
- GL1_PIPE_STEER__PIPE10_MASK
- GL1_PIPE_STEER__PIPE10__SHIFT
- GL1_PIPE_STEER__PIPE11_MASK
- GL1_PIPE_STEER__PIPE11__SHIFT
- GL1_PIPE_STEER__PIPE12_MASK
- GL1_PIPE_STEER__PIPE12__SHIFT
- GL1_PIPE_STEER__PIPE13_MASK
- GL1_PIPE_STEER__PIPE13__SHIFT
- GL1_PIPE_STEER__PIPE14_MASK
- GL1_PIPE_STEER__PIPE14__SHIFT
- GL1_PIPE_STEER__PIPE15_MASK
- GL1_PIPE_STEER__PIPE15__SHIFT
- GL1_PIPE_STEER__PIPE1_MASK
- GL1_PIPE_STEER__PIPE1__SHIFT
- GL1_PIPE_STEER__PIPE2_MASK
- GL1_PIPE_STEER__PIPE2__SHIFT
- GL1_PIPE_STEER__PIPE3_MASK
- GL1_PIPE_STEER__PIPE3__SHIFT
- GL1_PIPE_STEER__PIPE4_MASK
- GL1_PIPE_STEER__PIPE4__SHIFT
- GL1_PIPE_STEER__PIPE5_MASK
- GL1_PIPE_STEER__PIPE5__SHIFT
- GL1_PIPE_STEER__PIPE6_MASK
- GL1_PIPE_STEER__PIPE6__SHIFT
- GL1_PIPE_STEER__PIPE7_MASK
- GL1_PIPE_STEER__PIPE7__SHIFT
- GL1_PIPE_STEER__PIPE8_MASK
- GL1_PIPE_STEER__PIPE8__SHIFT
- GL1_PIPE_STEER__PIPE9_MASK
- GL1_PIPE_STEER__PIPE9__SHIFT
- GL20_INPUT_GAIN_MAGIC_NUMBER
- GL2A_ADDR_MATCH_CTRL__DISABLE_MASK
- GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT
- GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK
- GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT
- GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK
- GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS_MASK
- GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__ON_DELAY_MASK
- GL2A_CGTT_SCLK_CTRL_1__ON_DELAY__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6__SHIFT
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7_MASK
- GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7__SHIFT
- GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
- GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
- GL2A_CGTT_SCLK_CTRL__ON_DELAY_MASK
- GL2A_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
- GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
- GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE_MASK
- GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE__SHIFT
- GL2A_CTRL__STAY_ON_BURST_MASK
- GL2A_CTRL__STAY_ON_BURST__SHIFT
- GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
- GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
- GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
- GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
- GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
- GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
- GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
- GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
- GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- GL2A_PERF_SEL
- GL2A_PERF_SEL_BUSY
- GL2A_PERF_SEL_CYCLE
- GL2A_PERF_SEL_NONE
- GL2A_PERF_SEL_REQ_BURST_GL2C0
- GL2A_PERF_SEL_REQ_BURST_GL2C1
- GL2A_PERF_SEL_REQ_BURST_GL2C2
- GL2A_PERF_SEL_REQ_BURST_GL2C3
- GL2A_PERF_SEL_REQ_BURST_GL2C4
- GL2A_PERF_SEL_REQ_BURST_GL2C5
- GL2A_PERF_SEL_REQ_BURST_GL2C6
- GL2A_PERF_SEL_REQ_BURST_GL2C7
- GL2A_PERF_SEL_REQ_GL2C0
- GL2A_PERF_SEL_REQ_GL2C1
- GL2A_PERF_SEL_REQ_GL2C2
- GL2A_PERF_SEL_REQ_GL2C3
- GL2A_PERF_SEL_REQ_GL2C4
- GL2A_PERF_SEL_REQ_GL2C5
- GL2A_PERF_SEL_REQ_GL2C6
- GL2A_PERF_SEL_REQ_GL2C7
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6
- GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7
- GL2A_PERF_SEL_REQ_STALL_GL2C0
- GL2A_PERF_SEL_REQ_STALL_GL2C1
- GL2A_PERF_SEL_REQ_STALL_GL2C2
- GL2A_PERF_SEL_REQ_STALL_GL2C3
- GL2A_PERF_SEL_REQ_STALL_GL2C4
- GL2A_PERF_SEL_REQ_STALL_GL2C5
- GL2A_PERF_SEL_REQ_STALL_GL2C6
- GL2A_PERF_SEL_REQ_STALL_GL2C7
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6
- GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7
- GL2A_PERF_SEL_RTN_CLIENT0
- GL2A_PERF_SEL_RTN_CLIENT1
- GL2A_PERF_SEL_RTN_CLIENT2
- GL2A_PERF_SEL_RTN_CLIENT3
- GL2A_PERF_SEL_RTN_CLIENT4
- GL2A_PERF_SEL_RTN_CLIENT5
- GL2A_PERF_SEL_RTN_CLIENT6
- GL2A_PERF_SEL_RTN_CLIENT7
- GL2A_PERF_SEL_RTN_STALL_GL2C0
- GL2A_PERF_SEL_RTN_STALL_GL2C1
- GL2A_PERF_SEL_RTN_STALL_GL2C2
- GL2A_PERF_SEL_RTN_STALL_GL2C3
- GL2A_PERF_SEL_RTN_STALL_GL2C4
- GL2A_PERF_SEL_RTN_STALL_GL2C5
- GL2A_PERF_SEL_RTN_STALL_GL2C6
- GL2A_PERF_SEL_RTN_STALL_GL2C7
- GL2A_PRIORITY_CTRL__DISABLE_MASK
- GL2A_PRIORITY_CTRL__DISABLE__SHIFT
- GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK
- GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT
- GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK
- GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT
- GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
- GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
- GL2C_CGTT_SCLK_CTRL__ON_DELAY_MASK
- GL2C_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
- GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
- GL2C_CM_CTRL0__HASH_MASK_MASK
- GL2C_CM_CTRL0__HASH_MASK__SHIFT
- GL2C_CM_CTRL1__BURST_MODE_MASK
- GL2C_CM_CTRL1__BURST_MODE__SHIFT
- GL2C_CM_CTRL1__BURST_TIMER_MASK
- GL2C_CM_CTRL1__BURST_TIMER__SHIFT
- GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK
- GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT
- GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK
- GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT
- GL2C_CM_CTRL1__HASH_MASK_MASK
- GL2C_CM_CTRL1__HASH_MASK__SHIFT
- GL2C_CM_CTRL1__MDC_ARB_MODE_MASK
- GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT
- GL2C_CM_CTRL1__READ_REQ_ONLY_MASK
- GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT
- GL2C_CM_CTRL1__RVF_SIZE_MASK
- GL2C_CM_CTRL1__RVF_SIZE__SHIFT
- GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK
- GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT
- GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK
- GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT
- GL2C_CM_CTRL1__WRITE_COH_MODE_MASK
- GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT
- GL2C_CM_CTRL2__READ_BURST_TIMER_MASK
- GL2C_CM_CTRL2__READ_BURST_TIMER__SHIFT
- GL2C_CM_STALL__QUEUE_MASK
- GL2C_CM_STALL__QUEUE__SHIFT
- GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK
- GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT
- GL2C_CTRL2__FILL_SIZE_32_MASK
- GL2C_CTRL2__FILL_SIZE_32__SHIFT
- GL2C_CTRL2__FILL_SIZE_64_MASK
- GL2C_CTRL2__FILL_SIZE_64__SHIFT
- GL2C_CTRL2__FORCE_MDC_INV_MASK
- GL2C_CTRL2__FORCE_MDC_INV__SHIFT
- GL2C_CTRL2__GCR_ALL_SET_MASK
- GL2C_CTRL2__GCR_ALL_SET__SHIFT
- GL2C_CTRL2__GCR_ARB_CTRL_MASK
- GL2C_CTRL2__GCR_ARB_CTRL__SHIFT
- GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK
- GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT
- GL2C_CTRL2__MAX_MIN_CTRL_MASK
- GL2C_CTRL2__MAX_MIN_CTRL__SHIFT
- GL2C_CTRL2__MDC_PF_BLOCK_MASK
- GL2C_CTRL2__MDC_PF_BLOCK__SHIFT
- GL2C_CTRL2__MDC_PF_DISABLE_MASK
- GL2C_CTRL2__MDC_PF_DISABLE__SHIFT
- GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK
- GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT
- GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK
- GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT
- GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK
- GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT
- GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK
- GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT
- GL2C_CTRL2__METADATA_VOLATILE_EN_MASK
- GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT
- GL2C_CTRL2__PROBE_FIFO_SIZE_MASK
- GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT
- GL2C_CTRL2__PROBE_UNSHARED_EN_MASK
- GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT
- GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK
- GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT
- GL2C_CTRL2__RB_VOLATILE_EN_MASK
- GL2C_CTRL2__RB_VOLATILE_EN__SHIFT
- GL2C_CTRL2__RO_DISABLE_MASK
- GL2C_CTRL2__RO_DISABLE__SHIFT
- GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK
- GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT
- GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK
- GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT
- GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK
- GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT
- GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ_MASK
- GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ__SHIFT
- GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE_MASK
- GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE__SHIFT
- GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK
- GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT
- GL2C_CTRL3__FGCG_OVERRIDE_MASK
- GL2C_CTRL3__FGCG_OVERRIDE__SHIFT
- GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK
- GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT
- GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK
- GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT
- GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK
- GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT
- GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA_MASK
- GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA__SHIFT
- GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK
- GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT
- GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK
- GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT
- GL2C_CTRL3__METADATA_NOFILL_MASK
- GL2C_CTRL3__METADATA_NOFILL__SHIFT
- GL2C_CTRL3__SCRATCH_MASK
- GL2C_CTRL3__SCRATCH__SHIFT
- GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK
- GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT
- GL2C_CTRL__CACHE_SIZE_MASK
- GL2C_CTRL__CACHE_SIZE__SHIFT
- GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK
- GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT
- GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK
- GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT
- GL2C_CTRL__LATENCY_FIFO_SIZE_MASK
- GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT
- GL2C_CTRL__LINEAR_SET_HASH_MASK
- GL2C_CTRL__LINEAR_SET_HASH__SHIFT
- GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK
- GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT
- GL2C_CTRL__MDC_SIZE_MASK
- GL2C_CTRL__MDC_SIZE__SHIFT
- GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK
- GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT
- GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK
- GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT
- GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK
- GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT
- GL2C_CTRL__RATE_MASK
- GL2C_CTRL__RATE__SHIFT
- GL2C_CTRL__SRC_FIFO_SIZE_MASK
- GL2C_CTRL__SRC_FIFO_SIZE__SHIFT
- GL2C_CTRL__WRITEBACK_MARGIN_MASK
- GL2C_CTRL__WRITEBACK_MARGIN__SHIFT
- GL2C_LB_CTR_CTRL__CLEAR_MASK
- GL2C_LB_CTR_CTRL__CLEAR__SHIFT
- GL2C_LB_CTR_CTRL__LOAD_MASK
- GL2C_LB_CTR_CTRL__LOAD__SHIFT
- GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK
- GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT
- GL2C_LB_CTR_CTRL__START_MASK
- GL2C_LB_CTR_CTRL__START__SHIFT
- GL2C_LB_CTR_SEL0__DIV0_MASK
- GL2C_LB_CTR_SEL0__DIV0__SHIFT
- GL2C_LB_CTR_SEL0__DIV1_MASK
- GL2C_LB_CTR_SEL0__DIV1__SHIFT
- GL2C_LB_CTR_SEL0__SEL0_MASK
- GL2C_LB_CTR_SEL0__SEL0__SHIFT
- GL2C_LB_CTR_SEL0__SEL1_MASK
- GL2C_LB_CTR_SEL0__SEL1__SHIFT
- GL2C_LB_CTR_SEL1__DIV2_MASK
- GL2C_LB_CTR_SEL1__DIV2__SHIFT
- GL2C_LB_CTR_SEL1__DIV3_MASK
- GL2C_LB_CTR_SEL1__DIV3__SHIFT
- GL2C_LB_CTR_SEL1__SEL2_MASK
- GL2C_LB_CTR_SEL1__SEL2__SHIFT
- GL2C_LB_CTR_SEL1__SEL3_MASK
- GL2C_LB_CTR_SEL1__SEL3__SHIFT
- GL2C_LB_DATA0__DATA_MASK
- GL2C_LB_DATA0__DATA__SHIFT
- GL2C_LB_DATA1__DATA_MASK
- GL2C_LB_DATA1__DATA__SHIFT
- GL2C_LB_DATA2__DATA_MASK
- GL2C_LB_DATA2__DATA__SHIFT
- GL2C_LB_DATA3__DATA_MASK
- GL2C_LB_DATA3__DATA__SHIFT
- GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK
- GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT
- GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
- GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
- GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
- GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
- GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
- GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
- GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
- GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
- GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
- GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
- GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
- GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
- GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
- GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
- GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
- GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
- GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- GL2C_PERF_SEL
- GL2C_PERF_SEL_ALL_GCR_INV_EVICT
- GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT
- GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE
- GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE
- GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK
- GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START
- GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START
- GL2C_PERF_SEL_ATOMIC
- GL2C_PERF_SEL_BUBBLE
- GL2C_PERF_SEL_BUSY
- GL2C_PERF_SEL_BYPASS_REQ
- GL2C_PERF_SEL_CLIENT0_REQ
- GL2C_PERF_SEL_CLIENT1_REQ
- GL2C_PERF_SEL_CLIENT2_REQ
- GL2C_PERF_SEL_CLIENT3_REQ
- GL2C_PERF_SEL_CLIENT4_REQ
- GL2C_PERF_SEL_CLIENT5_REQ
- GL2C_PERF_SEL_CLIENT6_REQ
- GL2C_PERF_SEL_CLIENT7_REQ
- GL2C_PERF_SEL_CM_CHANNEL0_REQ
- GL2C_PERF_SEL_CM_CHANNEL10_REQ
- GL2C_PERF_SEL_CM_CHANNEL11_REQ
- GL2C_PERF_SEL_CM_CHANNEL12_REQ
- GL2C_PERF_SEL_CM_CHANNEL13_REQ
- GL2C_PERF_SEL_CM_CHANNEL14_REQ
- GL2C_PERF_SEL_CM_CHANNEL15_REQ
- GL2C_PERF_SEL_CM_CHANNEL16_REQ
- GL2C_PERF_SEL_CM_CHANNEL17_REQ
- GL2C_PERF_SEL_CM_CHANNEL18_REQ
- GL2C_PERF_SEL_CM_CHANNEL19_REQ
- GL2C_PERF_SEL_CM_CHANNEL1_REQ
- GL2C_PERF_SEL_CM_CHANNEL20_REQ
- GL2C_PERF_SEL_CM_CHANNEL21_REQ
- GL2C_PERF_SEL_CM_CHANNEL22_REQ
- GL2C_PERF_SEL_CM_CHANNEL23_REQ
- GL2C_PERF_SEL_CM_CHANNEL24_REQ
- GL2C_PERF_SEL_CM_CHANNEL25_REQ
- GL2C_PERF_SEL_CM_CHANNEL26_REQ
- GL2C_PERF_SEL_CM_CHANNEL27_REQ
- GL2C_PERF_SEL_CM_CHANNEL28_REQ
- GL2C_PERF_SEL_CM_CHANNEL29_REQ
- GL2C_PERF_SEL_CM_CHANNEL2_REQ
- GL2C_PERF_SEL_CM_CHANNEL30_REQ
- GL2C_PERF_SEL_CM_CHANNEL31_REQ
- GL2C_PERF_SEL_CM_CHANNEL3_REQ
- GL2C_PERF_SEL_CM_CHANNEL4_REQ
- GL2C_PERF_SEL_CM_CHANNEL5_REQ
- GL2C_PERF_SEL_CM_CHANNEL6_REQ
- GL2C_PERF_SEL_CM_CHANNEL7_REQ
- GL2C_PERF_SEL_CM_CHANNEL8_REQ
- GL2C_PERF_SEL_CM_CHANNEL9_REQ
- GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ
- GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ
- GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ
- GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ
- GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ
- GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ
- GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ
- GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ
- GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ
- GL2C_PERF_SEL_CM_COMP_READ_REQ
- GL2C_PERF_SEL_CM_COMP_STENCIL_REQ
- GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ
- GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ
- GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ
- GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ
- GL2C_PERF_SEL_CM_DCC_STALL
- GL2C_PERF_SEL_CM_FULL_WRITE_REQ
- GL2C_PERF_SEL_CM_MERGE_BUF_FULL
- GL2C_PERF_SEL_CM_METADATA_WR_REQ
- GL2C_PERF_SEL_CM_NOOP_REQ
- GL2C_PERF_SEL_CM_NO_ACK_REQ
- GL2C_PERF_SEL_CM_READ_BACK_REQ
- GL2C_PERF_SEL_CM_RVF_FULL
- GL2C_PERF_SEL_CM_SDR_FULL
- GL2C_PERF_SEL_CM_WR_ACK_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_0_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_128_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_32_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_64_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_96_REQ
- GL2C_PERF_SEL_COMPRESSED_READ_REQ
- GL2C_PERF_SEL_CYCLE
- GL2C_PERF_SEL_C_RO_S_REQ
- GL2C_PERF_SEL_C_RO_US_REQ
- GL2C_PERF_SEL_C_RW_S_REQ
- GL2C_PERF_SEL_C_RW_US_REQ
- GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT
- GL2C_PERF_SEL_EA_ATOMIC
- GL2C_PERF_SEL_EA_ATOMIC_LEVEL
- GL2C_PERF_SEL_EA_RDREQ_128B
- GL2C_PERF_SEL_EA_RDREQ_32B
- GL2C_PERF_SEL_EA_RDREQ_64B
- GL2C_PERF_SEL_EA_RDREQ_96B
- GL2C_PERF_SEL_EA_RDREQ_DRAM
- GL2C_PERF_SEL_EA_RDREQ_DRAM_32B
- GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL
- GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL
- GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL
- GL2C_PERF_SEL_EA_RDREQ_SPLIT
- GL2C_PERF_SEL_EA_RDRET_NACK
- GL2C_PERF_SEL_EA_RD_COMPRESSED_32B
- GL2C_PERF_SEL_EA_RD_MDC_32B
- GL2C_PERF_SEL_EA_RD_UNCACHED_32B
- GL2C_PERF_SEL_EA_WRREQ_64B
- GL2C_PERF_SEL_EA_WRREQ_DRAM
- GL2C_PERF_SEL_EA_WRREQ_DRAM_32B
- GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL
- GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL
- GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL
- GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND
- GL2C_PERF_SEL_EA_WRRET_NACK
- GL2C_PERF_SEL_EA_WR_UNCACHED_32B
- GL2C_PERF_SEL_EVICT
- GL2C_PERF_SEL_FULLY_WRITTEN_HIT
- GL2C_PERF_SEL_FULL_HIT
- GL2C_PERF_SEL_GARLIC_READ
- GL2C_PERF_SEL_GARLIC_WRITE
- GL2C_PERF_SEL_GCR_ALL
- GL2C_PERF_SEL_GCR_DISCARD
- GL2C_PERF_SEL_GCR_GL2_INV_ALL
- GL2C_PERF_SEL_GCR_GL2_INV_RANGE
- GL2C_PERF_SEL_GCR_GL2_WB_ALL
- GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE
- GL2C_PERF_SEL_GCR_GL2_WB_RANGE
- GL2C_PERF_SEL_GCR_INV
- GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE
- GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT
- GL2C_PERF_SEL_GCR_INVL2_VOL_START
- GL2C_PERF_SEL_GCR_MDC_INV
- GL2C_PERF_SEL_GCR_MDC_INV_ALL
- GL2C_PERF_SEL_GCR_MDC_INV_RANGE
- GL2C_PERF_SEL_GCR_RANGE
- GL2C_PERF_SEL_GCR_UNSHARED
- GL2C_PERF_SEL_GCR_VOL
- GL2C_PERF_SEL_GCR_WB
- GL2C_PERF_SEL_GCR_WBINVL2_CYCLE
- GL2C_PERF_SEL_GCR_WBINVL2_EVICT
- GL2C_PERF_SEL_GCR_WBINVL2_START
- GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE
- GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT
- GL2C_PERF_SEL_GCR_WBL2_VOL_START
- GL2C_PERF_SEL_GL2A_LEVEL
- GL2C_PERF_SEL_HIGH_PRIORITY_REQ
- GL2C_PERF_SEL_HIT
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP
- GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO
- GL2C_PERF_SEL_IB_CM_STALL
- GL2C_PERF_SEL_IB_REQ
- GL2C_PERF_SEL_IB_STALL
- GL2C_PERF_SEL_IB_TAG_STALL
- GL2C_PERF_SEL_INTERNAL_PROBE
- GL2C_PERF_SEL_IO_READ
- GL2C_PERF_SEL_IO_WRITE
- GL2C_PERF_SEL_LATENCY_FIFO_FULL
- GL2C_PERF_SEL_LRU_REQ
- GL2C_PERF_SEL_MC_RDREQ
- GL2C_PERF_SEL_MC_RDREQ_LEVEL
- GL2C_PERF_SEL_MC_WRREQ
- GL2C_PERF_SEL_MC_WRREQ_LEVEL
- GL2C_PERF_SEL_MC_WRREQ_STALL
- GL2C_PERF_SEL_MDC_INV_METADATA
- GL2C_PERF_SEL_MDC_LEVEL
- GL2C_PERF_SEL_MDC_REQ
- GL2C_PERF_SEL_MDC_SECTOR_HIT
- GL2C_PERF_SEL_MDC_SECTOR_MISS
- GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL
- GL2C_PERF_SEL_MDC_TAG_HIT
- GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL
- GL2C_PERF_SEL_MDC_TAG_STALL
- GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL
- GL2C_PERF_SEL_METADATA_READ_REQ
- GL2C_PERF_SEL_MISS
- GL2C_PERF_SEL_NOA_REQ
- GL2C_PERF_SEL_NONE
- GL2C_PERF_SEL_NOP_ACK
- GL2C_PERF_SEL_NOP_RTN0
- GL2C_PERF_SEL_NORMAL_EVICT
- GL2C_PERF_SEL_NORMAL_WRITEBACK
- GL2C_PERF_SEL_ONION_READ
- GL2C_PERF_SEL_ONION_WRITE
- GL2C_PERF_SEL_PARTIAL_32B_HIT
- GL2C_PERF_SEL_PARTIAL_64B_HIT
- GL2C_PERF_SEL_PARTIAL_96B_HIT
- GL2C_PERF_SEL_PROBE
- GL2C_PERF_SEL_PROBE_ALL
- GL2C_PERF_SEL_PROBE_EVICT
- GL2C_PERF_SEL_PROBE_FILTER_DISABLED
- GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION
- GL2C_PERF_SEL_READ
- GL2C_PERF_SEL_READ_128_REQ
- GL2C_PERF_SEL_READ_32_REQ
- GL2C_PERF_SEL_READ_64_REQ
- GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE
- GL2C_PERF_SEL_READ_RETURN_TIMEOUT
- GL2C_PERF_SEL_REQ
- GL2C_PERF_SEL_REQ_TO_MISS_QUEUE
- GL2C_PERF_SEL_RETURN_ACK
- GL2C_PERF_SEL_RETURN_DATA
- GL2C_PERF_SEL_SHARED_REQ
- GL2C_PERF_SEL_SRC_FIFO_FULL
- GL2C_PERF_SEL_STREAM_REQ
- GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL
- GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL
- GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL
- GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL
- GL2C_PERF_SEL_TAG_PROBE_STALL
- GL2C_PERF_SEL_TAG_READ_DST_STALL
- GL2C_PERF_SEL_TAG_STALL
- GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL
- GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL
- GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL
- GL2C_PERF_SEL_UC_REQ
- GL2C_PERF_SEL_UNCACHED_WRITE
- GL2C_PERF_SEL_VOL_REQ
- GL2C_PERF_SEL_WRITE
- GL2C_PERF_SEL_WRITEBACK
- GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT
- GL2C_PERF_SEL_WRITE_32_REQ
- GL2C_PERF_SEL_WRITE_64_REQ
- GL2C_SOFT_RESET__HALT_FOR_RESET_MASK
- GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT
- GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC_MASK
- GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC__SHIFT
- GL2C_STATUS__COMPRESSED_GEN0_MASK
- GL2C_STATUS__COMPRESSED_GEN0__SHIFT
- GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE_MASK
- GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE__SHIFT
- GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC_MASK
- GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC__SHIFT
- GL2C_WBINVL2__DONE_MASK
- GL2C_WBINVL2__DONE__SHIFT
- GL2_CACHE_POLICIES
- GL2_CACHE_POLICY_BYPASS
- GL2_CACHE_POLICY_LRU
- GL2_CACHE_POLICY_NOA
- GL2_CACHE_POLICY_STREAM
- GL2_EA_CID
- GL2_EA_CID_CLIENT
- GL2_EA_CID_CP
- GL2_EA_CID_CPDMA
- GL2_EA_CID_DCC
- GL2_EA_CID_FMASK
- GL2_EA_CID_HTILE
- GL2_EA_CID_RLC
- GL2_EA_CID_RT
- GL2_EA_CID_SDMA
- GL2_EA_CID_TCPMETA
- GL2_EA_CID_UTCL2
- GL2_EA_CID_ZPCPSD
- GL2_EA_CID_Z_STENCIL
- GL2_NACKS
- GL2_NACK_DATA_ERROR
- GL2_NACK_NO_FAULT
- GL2_NACK_PAGE_FAULT
- GL2_NACK_PROTECTION_FAULT
- GL2_OP
- GL2_OP_ATOMIC_ADD_32
- GL2_OP_ATOMIC_ADD_64
- GL2_OP_ATOMIC_ADD_RTN_32
- GL2_OP_ATOMIC_ADD_RTN_64
- GL2_OP_ATOMIC_AND_32
- GL2_OP_ATOMIC_AND_64
- GL2_OP_ATOMIC_AND_RTN_32
- GL2_OP_ATOMIC_AND_RTN_64
- GL2_OP_ATOMIC_CMPSWAP_32
- GL2_OP_ATOMIC_CMPSWAP_64
- GL2_OP_ATOMIC_CMPSWAP_RTN_32
- GL2_OP_ATOMIC_CMPSWAP_RTN_64
- GL2_OP_ATOMIC_DEC_32
- GL2_OP_ATOMIC_DEC_64
- GL2_OP_ATOMIC_DEC_RTN_32
- GL2_OP_ATOMIC_DEC_RTN_64
- GL2_OP_ATOMIC_FCMPSWAP_32
- GL2_OP_ATOMIC_FCMPSWAP_64
- GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32
- GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64
- GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32
- GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64
- GL2_OP_ATOMIC_FCMPSWAP_RTN_32
- GL2_OP_ATOMIC_FCMPSWAP_RTN_64
- GL2_OP_ATOMIC_FMAX_32
- GL2_OP_ATOMIC_FMAX_64
- GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32
- GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64
- GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32
- GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64
- GL2_OP_ATOMIC_FMAX_RTN_32
- GL2_OP_ATOMIC_FMAX_RTN_64
- GL2_OP_ATOMIC_FMIN_32
- GL2_OP_ATOMIC_FMIN_64
- GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32
- GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64
- GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32
- GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64
- GL2_OP_ATOMIC_FMIN_RTN_32
- GL2_OP_ATOMIC_FMIN_RTN_64
- GL2_OP_ATOMIC_INC_32
- GL2_OP_ATOMIC_INC_64
- GL2_OP_ATOMIC_INC_RTN_32
- GL2_OP_ATOMIC_INC_RTN_64
- GL2_OP_ATOMIC_OR_32
- GL2_OP_ATOMIC_OR_64
- GL2_OP_ATOMIC_OR_RTN_32
- GL2_OP_ATOMIC_OR_RTN_64
- GL2_OP_ATOMIC_SMAX_32
- GL2_OP_ATOMIC_SMAX_64
- GL2_OP_ATOMIC_SMAX_RTN_32
- GL2_OP_ATOMIC_SMAX_RTN_64
- GL2_OP_ATOMIC_SMIN_32
- GL2_OP_ATOMIC_SMIN_64
- GL2_OP_ATOMIC_SMIN_RTN_32
- GL2_OP_ATOMIC_SMIN_RTN_64
- GL2_OP_ATOMIC_SUB_32
- GL2_OP_ATOMIC_SUB_64
- GL2_OP_ATOMIC_SUB_RTN_32
- GL2_OP_ATOMIC_SUB_RTN_64
- GL2_OP_ATOMIC_SWAP_32
- GL2_OP_ATOMIC_SWAP_64
- GL2_OP_ATOMIC_SWAP_RTN_32
- GL2_OP_ATOMIC_SWAP_RTN_64
- GL2_OP_ATOMIC_UMAX_32
- GL2_OP_ATOMIC_UMAX_64
- GL2_OP_ATOMIC_UMAX_RTN_32
- GL2_OP_ATOMIC_UMAX_RTN_64
- GL2_OP_ATOMIC_UMIN_32
- GL2_OP_ATOMIC_UMIN_64
- GL2_OP_ATOMIC_UMIN_RTN_32
- GL2_OP_ATOMIC_UMIN_RTN_64
- GL2_OP_ATOMIC_XOR_32
- GL2_OP_ATOMIC_XOR_64
- GL2_OP_ATOMIC_XOR_RTN_32
- GL2_OP_ATOMIC_XOR_RTN_64
- GL2_OP_GL1_INV
- GL2_OP_MASKS
- GL2_OP_MASK_64
- GL2_OP_MASK_FLUSH_DENROM
- GL2_OP_MASK_NO_RTN
- GL2_OP_NOP_ACK
- GL2_OP_NOP_RTN0
- GL2_OP_PROBE_FILTER
- GL2_OP_READ
- GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1
- GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2
- GL2_OP_WRITE
- GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK
- GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT
- GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK
- GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT
- GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK
- GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT
- GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK
- GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT
- GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK
- GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT
- GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK
- GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT
- GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK
- GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT
- GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK
- GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT
- GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK
- GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT
- GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK
- GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT
- GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK
- GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT
- GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK
- GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT
- GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK
- GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT
- GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK
- GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT
- GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK
- GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT
- GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK
- GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT
- GL518_REG_ALARM
- GL518_REG_CHIP_ID
- GL518_REG_CONF
- GL518_REG_FAN_COUNT
- GL518_REG_FAN_LIMIT
- GL518_REG_INT
- GL518_REG_MASK
- GL518_REG_MISC
- GL518_REG_REVISION
- GL518_REG_TEMP_HYST
- GL518_REG_TEMP_IN
- GL518_REG_TEMP_MAX
- GL518_REG_VDD
- GL518_REG_VDD_LIMIT
- GL518_REG_VENDOR_ID
- GL518_REG_VIN1
- GL518_REG_VIN1_LIMIT
- GL518_REG_VIN2
- GL518_REG_VIN2_LIMIT
- GL518_REG_VIN3
- GL518_REG_VIN3_LIMIT
- GL520_REG_ALARMS
- GL520_REG_BEEP_ENABLE
- GL520_REG_BEEP_MASK
- GL520_REG_CHIP_ID
- GL520_REG_CONF
- GL520_REG_FAN_DIV
- GL520_REG_FAN_INPUT
- GL520_REG_FAN_MIN
- GL520_REG_FAN_OFF
- GL520_REG_MASK
- GL520_REG_REVISION
- GL520_REG_VID_INPUT
- GL860_DEV_H
- GL861_READ
- GL861_REQ_I2C_RAW
- GL861_REQ_I2C_READ
- GL861_REQ_I2C_WRITE
- GL861_WRITE
- GLANTANK_UART
- GLBL_DED_ERRH
- GLBL_DED_ERRHMASK
- GLBL_DED_ERRL
- GLBL_DED_ERRLMASK
- GLBL_ERR_STS
- GLBL_INTR_MASK
- GLBL_MDED_ERRH
- GLBL_MDED_ERRHMASK
- GLBL_MDED_ERRL
- GLBL_MDED_ERRLMASK
- GLBL_MSEC_ERRH
- GLBL_MSEC_ERRL
- GLBL_SEC_ERRH
- GLBL_SEC_ERRL
- GLB_ARCH_ID
- GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK
- GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHA_SAMPLEDELAY__RESERVED_MASK
- GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHC0_SAMPLEDELAY__RESERVED_MASK
- GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHC1_SAMPLEDELAY__RESERVED_MASK
- GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHC2_SAMPLEDELAY__RESERVED_MASK
- GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHC3_SAMPLEDELAY__RESERVED_MASK
- GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CHCG_SAMPLEDELAY__RESERVED_MASK
- GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CORE_ID
- GLB_CORE_INFO
- GLB_CPC_SAMPLEDELAY__RESERVED_MASK
- GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CPF_SAMPLEDELAY__RESERVED_MASK
- GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_CPG_SAMPLEDELAY__RESERVED_MASK
- GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT
- GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA0_SAMPLEDELAY__RESERVED_MASK
- GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA10_SAMPLEDELAY__RESERVED_MASK
- GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA11_SAMPLEDELAY__RESERVED_MASK
- GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA12_SAMPLEDELAY__RESERVED_MASK
- GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA13_SAMPLEDELAY__RESERVED_MASK
- GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA14_SAMPLEDELAY__RESERVED_MASK
- GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA15_SAMPLEDELAY__RESERVED_MASK
- GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA1_SAMPLEDELAY__RESERVED_MASK
- GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA2_SAMPLEDELAY__RESERVED_MASK
- GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA3_SAMPLEDELAY__RESERVED_MASK
- GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA4_SAMPLEDELAY__RESERVED_MASK
- GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA5_SAMPLEDELAY__RESERVED_MASK
- GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA6_SAMPLEDELAY__RESERVED_MASK
- GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA7_SAMPLEDELAY__RESERVED_MASK
- GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA8_SAMPLEDELAY__RESERVED_MASK
- GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_EA9_SAMPLEDELAY__RESERVED_MASK
- GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT
- GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_FWCTRL
- GLB_GCR_SAMPLEDELAY__RESERVED_MASK
- GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GDS_SAMPLEDELAY__RESERVED_MASK
- GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GE_SAMPLEDELAY__RESERVED_MASK
- GLB_GE_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GE_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GE_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK
- GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_GPIO_CLK_DBG_MSK
- GLB_GPIO_CLK_DEB_ENA
- GLB_GPIO_INT_RST_D3_DIS
- GLB_GPIO_LED_PAD_SPEED_UP
- GLB_GPIO_RAND_BIT_1
- GLB_GPIO_RAND_ENA
- GLB_GPIO_STAT_RACE_DIS
- GLB_GPIO_TEST_SEL_BASE
- GLB_GPIO_TEST_SEL_MSK
- GLB_GUS_SAMPLEDELAY__RESERVED_MASK
- GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT
- GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_HOSTMAC_H16
- GLB_HOSTMAC_L32
- GLB_IRQ_ENA
- GLB_IRQ_RAW
- GLB_IRQ_STAT
- GLB_IRQ_STATUS
- GLB_IRQ_STATUS_ATU
- GLB_IRQ_STATUS_ATU0
- GLB_IRQ_STATUS_ATU1
- GLB_IRQ_STATUS_ATU2
- GLB_IRQ_STATUS_ATU3
- GLB_IRQ_STATUS_CU0
- GLB_IRQ_STATUS_CU1
- GLB_IRQ_STATUS_DOU0
- GLB_IRQ_STATUS_DOU1
- GLB_IRQ_STATUS_GCU
- GLB_IRQ_STATUS_LPU0
- GLB_IRQ_STATUS_LPU1
- GLB_IRQ_STATUS_PIPE0
- GLB_IRQ_STATUS_PIPE1
- GLB_IT_COEFF
- GLB_LT_COEFF_DATA
- GLB_LT_COEFF_NUM
- GLB_MACTCTRL
- GLB_MAC_H16
- GLB_MAC_H16_BASE
- GLB_MAC_L32
- GLB_MAC_L32_BASE
- GLB_PH_SAMPLEDELAY__RESERVED_MASK
- GLB_PH_SAMPLEDELAY__RESERVED__SHIFT
- GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_SCC_0
- GLB_SCC_1
- GLB_SCC_2
- GLB_SCC_3
- GLB_SC_COEFF_ADDR
- GLB_SC_COEFF_DATA
- GLB_SC_COEFF_MAX_NUM
- GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK
- GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT
- GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK
- GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT
- GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLB_SOFT_RESET
- GLB_VML2_SAMPLEDELAY__RESERVED_MASK
- GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT
- GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK
- GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT
- GLCP_CAP
- GLCP_CHIP_REV_ID
- GLCP_CLK4ACK
- GLCP_CLK_ACTIVE
- GLCP_CLK_DISABLE
- GLCP_CLK_DIS_DELAY
- GLCP_CLK_OFF
- GLCP_CONFIG
- GLCP_DBG_CLK_CTRL
- GLCP_DBG_OUT
- GLCP_DIAG
- GLCP_ERROR
- GLCP_GLB_PM
- GLCP_MSR_REG
- GLCP_PM
- GLCP_PM_CLK_DISABLE
- GLCP_RSVD1
- GLCP_RSVD2
- GLCP_RSVD3
- GLCP_SMI
- GLCP_SOFT_COM
- GLCP_SYS_RST
- GLDM_CLOCK_DETECT_BIT_ESYNC
- GLDM_CLOCK_DETECT_BIT_SPDIF
- GLDM_CLOCK_DETECT_BIT_SUPER
- GLDM_CLOCK_DETECT_BIT_WORD
- GLE
- GLENFARCLAS_PMIC_GPIO_BASE
- GLENFARCLAS_PMIC_IRQ_BASE
- GLFLXP_RXDID_FLAGS
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M
- GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S
- GLFLXP_RXDID_FLX_WRD_0
- GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M
- GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S
- GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M
- GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S
- GLFLXP_RXDID_FLX_WRD_1
- GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M
- GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S
- GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M
- GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S
- GLFLXP_RXDID_FLX_WRD_2
- GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M
- GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S
- GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M
- GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S
- GLFLXP_RXDID_FLX_WRD_3
- GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M
- GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S
- GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M
- GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S
- GLF_BLOCKING
- GLF_DEMOTE
- GLF_DEMOTE_IN_PROGRESS
- GLF_DIRTY
- GLF_FROZEN
- GLF_INITIAL
- GLF_INODE_CREATING
- GLF_INVALIDATE_IN_PROGRESS
- GLF_LFLUSH
- GLF_LOCK
- GLF_LRU
- GLF_OBJECT
- GLF_PENDING_DEMOTE
- GLF_QUEUED
- GLF_REPLY_PENDING
- GLGEN_RSTAT
- GLGEN_RSTAT_DEVSTATE_M
- GLGEN_RSTAT_RESET_TYPE_M
- GLGEN_RSTAT_RESET_TYPE_S
- GLGEN_RSTCTL
- GLGEN_RSTCTL_GRSTDEL_M
- GLGEN_RSTCTL_GRSTDEL_S
- GLGEN_RTRIG
- GLGEN_RTRIG_CORER_M
- GLGEN_RTRIG_GLOBR_M
- GLGEN_STAT
- GLGEN_VFLRSTAT
- GLINK_FEATURE_INTENTLESS
- GLINK_FEATURE_INTENT_REUSE
- GLINK_FEATURE_MIGRATION
- GLINK_FEATURE_TRACER_PKT
- GLINK_NAME_SIZE
- GLINK_SSR_CLEANUP_DONE
- GLINK_SSR_DO_CLEANUP
- GLINK_STATE_CLOSED
- GLINK_STATE_CLOSING
- GLINK_STATE_OPEN
- GLINK_STATE_OPENING
- GLINK_VERSION_1
- GLINT_CTL
- GLINT_CTL_DIS_AUTOMASK_M
- GLINT_CTL_ITR_GRAN_100_M
- GLINT_CTL_ITR_GRAN_100_S
- GLINT_CTL_ITR_GRAN_200_M
- GLINT_CTL_ITR_GRAN_200_S
- GLINT_CTL_ITR_GRAN_25_M
- GLINT_CTL_ITR_GRAN_25_S
- GLINT_CTL_ITR_GRAN_50_M
- GLINT_CTL_ITR_GRAN_50_S
- GLINT_DYN_CTL
- GLINT_DYN_CTL_CLEARPBA_M
- GLINT_DYN_CTL_INTENA_M
- GLINT_DYN_CTL_INTENA_MSK_M
- GLINT_DYN_CTL_INTERVAL_M
- GLINT_DYN_CTL_INTERVAL_S
- GLINT_DYN_CTL_ITR_INDX_M
- GLINT_DYN_CTL_ITR_INDX_S
- GLINT_DYN_CTL_SWINT_TRIG_M
- GLINT_DYN_CTL_SW_ITR_INDX_M
- GLINT_DYN_CTL_WB_ON_ITR_M
- GLINT_ITR
- GLINT_RATE
- GLINT_RATE_INTRL_ENA_M
- GLINT_VECT2FUNC
- GLINT_VECT2FUNC_IS_PF_M
- GLINT_VECT2FUNC_IS_PF_S
- GLINT_VECT2FUNC_PF_NUM_M
- GLINT_VECT2FUNC_PF_NUM_S
- GLINT_VECT2FUNC_VF_NUM_M
- GLINT_VECT2FUNC_VF_NUM_S
- GLITCH_FILTER_400NS
- GLIU_AERR
- GLIU_ARB
- GLIU_ASMI
- GLIU_CAP
- GLIU_COH
- GLIU_CONFIG
- GLIU_DEBUG
- GLIU_DIAG
- GLIU_ERROR
- GLIU_IOD_BM0
- GLIU_IOD_BM1
- GLIU_IOD_BM2
- GLIU_IOD_BM3
- GLIU_IOD_BM4
- GLIU_IOD_BM5
- GLIU_IOD_BM6
- GLIU_IOD_BM7
- GLIU_IOD_BM8
- GLIU_IOD_BM9
- GLIU_IOD_SC0
- GLIU_IOD_SC1
- GLIU_IOD_SC2
- GLIU_IOD_SC3
- GLIU_IOD_SC4
- GLIU_IOD_SC5
- GLIU_IOD_SC6
- GLIU_IOD_SC7
- GLIU_MSR_REG
- GLIU_NOUT_RESP
- GLIU_NOUT_WDATA
- GLIU_P2D_BM0
- GLIU_P2D_BM1
- GLIU_P2D_BM2
- GLIU_P2D_BM3
- GLIU_P2D_BM4
- GLIU_P2D_BMK0
- GLIU_P2D_BMK1
- GLIU_PAE
- GLIU_PHY_CAP
- GLIU_PM
- GLIU_SLV_DIS
- GLIU_SMI
- GLIU_WHOAMI
- GLI_9750_DRIVING_1_VALUE
- GLI_9750_DRIVING_2_VALUE
- GLI_9750_MISC_RX_INV_OFF
- GLI_9750_MISC_RX_INV_ON
- GLI_9750_MISC_RX_INV_VALUE
- GLI_9750_MISC_TX1_DLY_VALUE
- GLI_9750_MISC_TX1_INV_VALUE
- GLI_9750_PLL_TX2_DLY_VALUE
- GLI_9750_PLL_TX2_INV_VALUE
- GLI_9750_SW_CTRL_4_VALUE
- GLI_9750_TUNING_CONTROL_EN_OFF
- GLI_9750_TUNING_CONTROL_EN_ON
- GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE
- GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE
- GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE
- GLI_9750_WT_EN_OFF
- GLI_9750_WT_EN_ON
- GLI_MAX_TUNING_LOOP
- GLK_Ax_DEVICE_ID
- GLK_CL0_PWR_DOWN
- GLK_CL1_PWR_DOWN
- GLK_CL2_PWR_DOWN
- GLK_CLOCK_LANE_STOP_STATE
- GLK_COLORS
- GLK_COMMUNITY
- GLK_CSR_MAX_FW_SIZE
- GLK_CSR_PATH
- GLK_CSR_VERSION_REQUIRED
- GLK_DATA_LANE_STOP_STATE
- GLK_DISPLAY_AUX_A_POWER_DOMAINS
- GLK_DISPLAY_AUX_B_POWER_DOMAINS
- GLK_DISPLAY_AUX_C_POWER_DOMAINS
- GLK_DISPLAY_DC_OFF_POWER_DOMAINS
- GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS
- GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS
- GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS
- GLK_DISP_PW_DPIO_CMN_C
- GLK_DLY
- GLK_DPCM_AUDIO_CP
- GLK_DPCM_AUDIO_DMIC_CP
- GLK_DPCM_AUDIO_ECHO_REF_CP
- GLK_DPCM_AUDIO_HDMI1_PB
- GLK_DPCM_AUDIO_HDMI2_PB
- GLK_DPCM_AUDIO_HDMI3_PB
- GLK_DPCM_AUDIO_HS_PB
- GLK_DPCM_AUDIO_PB
- GLK_DPCM_AUDIO_REF_CP
- GLK_DPIO_CMN_A_POWER_DOMAINS
- GLK_DPIO_CMN_B_POWER_DOMAINS
- GLK_DPIO_CMN_C_POWER_DOMAINS
- GLK_DSI_PLL_RATIO_MAX
- GLK_DSI_PLL_RATIO_MIN
- GLK_FIREWALL_ENABLE
- GLK_GPI_IE
- GLK_GPI_IS
- GLK_HOSTSW_OWN
- GLK_LP00_LOW_PWR_MODE
- GLK_LP11_LOW_PWR_MODE
- GLK_LP_WAKE
- GLK_MAXIM_CODEC_DAI
- GLK_MIPIIO_ENABLE
- GLK_MIPIIO_PORT_POWERED
- GLK_MIPIIO_RESET_RELEASED
- GLK_PADCFGLOCK
- GLK_PAD_OWN
- GLK_PATH_PLL
- GLK_PHY_STATUS_PORT_READY
- GLK_PLAT_CLK_FREQ
- GLK_PW_CTL_IDX_AUX_A
- GLK_PW_CTL_IDX_AUX_B
- GLK_PW_CTL_IDX_AUX_C
- GLK_PW_CTL_IDX_DDI_A
- GLK_REALTEK_CODEC_DAI
- GLK_REVID_A0
- GLK_REVID_A1
- GLK_RX_CTRL1
- GLK_TUN_VAL
- GLK_TVIDEO_DIP_DRM_DATA
- GLK_TX_ESC_CLK_DIV1_MASK
- GLK_TX_ESC_CLK_DIV2_MASK
- GLK_ULPS_NOT_ACTIVE
- GLLAN_RCTL_0
- GLM_ANY_RESPONSE
- GLM_DEMAND_DATA_RD
- GLM_DEMAND_PREFETCH
- GLM_DEMAND_READ
- GLM_DEMAND_RFO
- GLM_DEMAND_WRITE
- GLM_LLC_ACCESS
- GLM_LLC_MISS
- GLM_SNP_ANY
- GLM_SNP_NONE_OR_MISS
- GLNVM_FLA
- GLNVM_FLA_LOCKED_M
- GLNVM_GENS
- GLNVM_GENS_SR_SIZE_M
- GLNVM_GENS_SR_SIZE_S
- GLNVM_ULD
- GLNVM_ULD_CORER_DONE_M
- GLNVM_ULD_GLOBR_DONE_M
- GLNVM_ULD_PCIER_DONE_1_M
- GLNVM_ULD_PCIER_DONE_2_M
- GLNVM_ULD_PCIER_DONE_M
- GLNVM_ULD_PE_DONE_M
- GLNVM_ULD_POR_DONE_1_M
- GLNVM_ULD_POR_DONE_M
- GLOBAL
- GLOBALENABLE_F
- GLOBALENABLE_S
- GLOBALENABLE_V
- GLOBALINT
- GLOBAL_AEU_BIT
- GLOBAL_ALPHA
- GLOBAL_ATU_CONTROL
- GLOBAL_ATU_CONTROL_ATE_AGE_5MIN
- GLOBAL_ATU_CONTROL_ATE_AGE_MASK
- GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT
- GLOBAL_ATU_CONTROL_ATUSIZE_1024
- GLOBAL_ATU_CONTROL_ATUSIZE_256
- GLOBAL_ATU_CONTROL_ATUSIZE_512
- GLOBAL_ATU_CONTROL_LEARNDIS
- GLOBAL_ATU_CONTROL_SWRESET
- GLOBAL_ATU_DATA
- GLOBAL_ATU_DATA_PORT_VECTOR_MASK
- GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT
- GLOBAL_ATU_DATA_STATE_MASK
- GLOBAL_ATU_DATA_STATE_MC_LOCKED
- GLOBAL_ATU_DATA_STATE_MC_STATIC
- GLOBAL_ATU_DATA_STATE_UC_LOCKED
- GLOBAL_ATU_DATA_STATE_UC_STATIC
- GLOBAL_ATU_DATA_STATE_UNUSED
- GLOBAL_ATU_MAC_01
- GLOBAL_ATU_MAC_23
- GLOBAL_ATU_MAC_45
- GLOBAL_ATU_OP
- GLOBAL_ATU_OP_BUSY
- GLOBAL_ATU_OP_FLUSH_ALL
- GLOBAL_ATU_OP_FLUSH_DB
- GLOBAL_ATU_OP_FLUSH_UNLOCKED
- GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB
- GLOBAL_ATU_OP_GET_NEXT_DB
- GLOBAL_ATU_OP_LOAD_DB
- GLOBAL_ATU_OP_NOP
- GLOBAL_BEEP_ENABLE_MASK
- GLOBAL_BEEP_ENABLE_SHIFT
- GLOBAL_BITMAP_SYSTEM_INODE
- GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK
- GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT
- GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK
- GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT
- GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK
- GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT
- GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK
- GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT
- GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK
- GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT
- GLOBAL_CFG
- GLOBAL_CFG_JUMBO
- GLOBAL_CFG_RESET
- GLOBAL_CFG_RX_STAT_EN
- GLOBAL_CFG_TX_STAT_EN
- GLOBAL_CLOCK_CAPABILITIES
- GLOBAL_CLOCK_SELECT
- GLOBAL_CLOCK_SOURCE_NAMES
- GLOBAL_CNTL_GCTL
- GLOBAL_CONFIG_1
- GLOBAL_CONFIG_2
- GLOBAL_CONTROL
- GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE
- GLOBAL_CONTROL_ATU_DONE_EN
- GLOBAL_CONTROL_ATU_FULL_EN
- GLOBAL_CONTROL_CONTROLLER_RESET
- GLOBAL_CONTROL_CTRMODE
- GLOBAL_CONTROL_DISCARD_EXCESS
- GLOBAL_CONTROL_EEPROM_DONE_EN
- GLOBAL_CONTROL_FLUSH_CONTROL
- GLOBAL_CONTROL_MAX_FRAME_1536
- GLOBAL_CONTROL_PHYINT_EN
- GLOBAL_CONTROL_RELOAD_EEPROM
- GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK
- GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT
- GLOBAL_CONTROL__CONTROLLER_RESET_MASK
- GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT
- GLOBAL_CONTROL__FLUSH_CONTROL_MASK
- GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT
- GLOBAL_CSR
- GLOBAL_CTRL_CLK_GATE_SSOFF
- GLOBAL_CTRL_CLK_POLARITY
- GLOBAL_CTRL_CS_POLARITY_MASK
- GLOBAL_CTRL_CS_POLARITY_SHIFT
- GLOBAL_CTRL_MOSI_IDLE
- GLOBAL_CTRL_PIN
- GLOBAL_CTRL_PLL_CLK_CTRL_MASK
- GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT
- GLOBAL_DMA_SKB_SIZE_REG
- GLOBAL_ENABLE
- GLOBAL_ENABLES_MASK
- GLOBAL_ENTRY
- GLOBAL_EVENTS
- GLOBAL_EXTENDED_STATUS
- GLOBAL_EXTERN
- GLOBAL_GMAC0_DATA_SKEW
- GLOBAL_GMAC1_DATA_SKEW
- GLOBAL_GMAC_CTRL_SKEW
- GLOBAL_HASH_TABLE_BASE_REG
- GLOBAL_HWFQ_RWPTR_REG
- GLOBAL_HW_FREEQ_BASE_SIZE_REG
- GLOBAL_IBML_EN
- GLOBAL_INODE_ALLOC_SYSTEM_INODE
- GLOBAL_INTERRUPT_ENABLE_0_REG
- GLOBAL_INTERRUPT_ENABLE_1_REG
- GLOBAL_INTERRUPT_ENABLE_2_REG
- GLOBAL_INTERRUPT_ENABLE_3_REG
- GLOBAL_INTERRUPT_ENABLE_4_REG
- GLOBAL_INTERRUPT_MASK
- GLOBAL_INTERRUPT_QUEUE
- GLOBAL_INTERRUPT_SELECT_0_REG
- GLOBAL_INTERRUPT_SELECT_1_REG
- GLOBAL_INTERRUPT_SELECT_2_REG
- GLOBAL_INTERRUPT_SELECT_3_REG
- GLOBAL_INTERRUPT_SELECT_4_REG
- GLOBAL_INTERRUPT_STATUS_0_REG
- GLOBAL_INTERRUPT_STATUS_1_REG
- GLOBAL_INTERRUPT_STATUS_2_REG
- GLOBAL_INTERRUPT_STATUS_3_REG
- GLOBAL_INTERRUPT_STATUS_4_REG
- GLOBAL_INTR_MASK
- GLOBAL_INT_ENABLE
- GLOBAL_INT_EN_FLAG
- GLOBAL_IODRIVE
- GLOBAL_MAC_01
- GLOBAL_MAC_01_DIFF_ADDR
- GLOBAL_MAC_23
- GLOBAL_MAC_45
- GLOBAL_MASTER_IO6
- GLOBAL_MIC_MUTE_DISABLE
- GLOBAL_MIC_MUTE_ENABLE
- GLOBAL_MISC_CTRL
- GLOBAL_MST_EN
- GLOBAL_NICK_NAME
- GLOBAL_NOTIFICATION
- GLOBAL_OPTION_B_CHANNEL_OPERATION
- GLOBAL_OPTION_CHANNEL_ALLOCATION
- GLOBAL_OPTION_DTMF
- GLOBAL_OPTION_EXTERNAL_CONTROLLER
- GLOBAL_OPTION_HANDSET
- GLOBAL_OPTION_INTERNAL_CONTROLLER
- GLOBAL_OPTION_SUPPL_SERVICES
- GLOBAL_OWNER
- GLOBAL_PARAMETERS_CONTAINER
- GLOBAL_PARAMETERS_PARTITION
- GLOBAL_PMAN_EN
- GLOBAL_PRIORITY
- GLOBAL_PWRMGT_EN
- GLOBAL_QUEUE_THRESHOLD_REG
- GLOBAL_ROOT_GID
- GLOBAL_ROOT_UID
- GLOBAL_SAMPLE_RATE
- GLOBAL_SERR_MASK
- GLOBAL_SHOTMODE_ERROR_NONE
- GLOBAL_SLV_EN
- GLOBAL_SOFTWARE_RESET
- GLOBAL_SPARE
- GLOBAL_STATUS
- GLOBAL_STATUS_ASIF
- GLOBAL_STATUS_ATU_DONE
- GLOBAL_STATUS_ATU_FULL
- GLOBAL_STATUS_BUFFER_OVF
- GLOBAL_STATUS_COND_CHG
- GLOBAL_STATUS_COUNTERS_FROZEN
- GLOBAL_STATUS_EEINT
- GLOBAL_STATUS_FLPIN
- GLOBAL_STATUS_FLUSH_STATUS
- GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED
- GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED
- GLOBAL_STATUS_INIT_READY
- GLOBAL_STATUS_LBRS_FROZEN
- GLOBAL_STATUS_PHY_INT
- GLOBAL_STATUS_SW_MODE_0
- GLOBAL_STATUS_SW_MODE_1
- GLOBAL_STATUS_SW_MODE_2
- GLOBAL_STATUS_SW_MODE_3
- GLOBAL_STATUS_SW_MODE_MASK
- GLOBAL_STATUS_TRACE_TOPAPMI
- GLOBAL_STATUS_UNC_OVF
- GLOBAL_STATUS__FLUSH_STATUS_MASK
- GLOBAL_STATUS__FLUSH_STATUS__SHIFT
- GLOBAL_SWFQ_RWPTR_REG
- GLOBAL_SW_FREEQ_BASE_SIZE_REG
- GLOBAL_TLBIALL
- GLOBAL_TOE_VERSION_REG
- GLOBAL_VARIABLE
- GLOBAL_VERSION
- GLOBAL_VILLAGE_GV_007_NTSC
- GLOBAL_WORD_ID
- GLOBDSPBREPTRREG
- GLOBDSPDEBGREG
- GLOB_CTRL
- GLOB_CTRL_ACNTRL
- GLOB_CTRL_B16
- GLOB_CTRL_B32
- GLOB_CTRL_B64
- GLOB_CTRL_BMODE
- GLOB_CTRL_EPAR
- GLOB_CTRL_MMODE
- GLOB_CTRL_RESET
- GLOB_MSIZE
- GLOB_PSIZE
- GLOB_PSIZE_2048
- GLOB_PSIZE_4096
- GLOB_PSIZE_6144
- GLOB_PSIZE_8192
- GLOB_REG_SIZE
- GLOB_RSIZE
- GLOB_SFT_RST
- GLOB_STAT
- GLOB_STAT_BM
- GLOB_STAT_ER
- GLOB_STAT_PER_QE
- GLOB_STAT_RX
- GLOB_STAT_TX
- GLOB_TSIZE
- GLOCK_BUG_ON
- GLOCK_WAIT_TABLE_BITS
- GLOCK_WAIT_TABLE_SIZE
- GLOCONT_BUFLEN
- GLOF_ASPACE
- GLOF_LRU
- GLOF_LVB
- GLO_CNT
- GLO_I0_B_MARK
- GLO_I0_C_MARK
- GLO_I0_D_MARK
- GLO_I0_MARK
- GLO_I1_B_MARK
- GLO_I1_C_MARK
- GLO_I1_D_MARK
- GLO_I1_MARK
- GLO_Q0_B_MARK
- GLO_Q0_C_MARK
- GLO_Q0_D_MARK
- GLO_Q0_MARK
- GLO_Q1_B_MARK
- GLO_Q1_C_MARK
- GLO_Q1_D_MARK
- GLO_Q1_MARK
- GLO_RFON_B_MARK
- GLO_RFON_C_MARK
- GLO_RFON_D_MARK
- GLO_RFON_MARK
- GLO_SCLK_B_MARK
- GLO_SCLK_C_MARK
- GLO_SCLK_D_MARK
- GLO_SCLK_MARK
- GLO_SDATA_B_MARK
- GLO_SDATA_C_MARK
- GLO_SDATA_D_MARK
- GLO_SDATA_MARK
- GLO_SS_B_MARK
- GLO_SS_C_MARK
- GLO_SS_D_MARK
- GLO_SS_MARK
- GLPCI_CNF2
- GLPCI_CNF2_CACHELINE_SIZE_M
- GLPMCFG
- GLPMCFG_APPL1RES
- GLPMCFG_BREMOTEWAKE
- GLPMCFG_COREL1RES_MASK
- GLPMCFG_COREL1RES_SHIFT
- GLPMCFG_ENBESL
- GLPMCFG_ENBLSLPM
- GLPMCFG_HIRD_MASK
- GLPMCFG_HIRD_SHIFT
- GLPMCFG_HIRD_THRES_EN
- GLPMCFG_HIRD_THRES_MASK
- GLPMCFG_HIRD_THRES_SHIFT
- GLPMCFG_HSICCON
- GLPMCFG_INVSELHSIC
- GLPMCFG_L1RESUMEOK
- GLPMCFG_LPMCAP
- GLPMCFG_LPM_ACCEPT_CTRL_ISOC
- GLPMCFG_LPM_CHNL_INDX_MASK
- GLPMCFG_LPM_CHNL_INDX_SHIFT
- GLPMCFG_LPM_REJECT_CTRL_CONTROL
- GLPMCFG_LPM_RETRYCNT_STS_MASK
- GLPMCFG_LPM_RETRYCNT_STS_SHIFT
- GLPMCFG_RETRY_CNT_MASK
- GLPMCFG_RETRY_CNT_SHIFT
- GLPMCFG_RSTRSLPSTS
- GLPMCFG_SLPSTS
- GLPMCFG_SNDLPM
- GLPR
- GLPRT_BPRCL
- GLPRT_BPTCL
- GLPRT_CRCERRS
- GLPRT_GORCL
- GLPRT_GOTCL
- GLPRT_ILLERRC
- GLPRT_LXOFFRXC
- GLPRT_LXOFFTXC
- GLPRT_LXONRXC
- GLPRT_LXONTXC
- GLPRT_MLFC
- GLPRT_MPRCL
- GLPRT_MPTCL
- GLPRT_MRFC
- GLPRT_PRC1023L
- GLPRT_PRC127L
- GLPRT_PRC1522L
- GLPRT_PRC255L
- GLPRT_PRC511L
- GLPRT_PRC64L
- GLPRT_PRC9522L
- GLPRT_PTC1023L
- GLPRT_PTC127L
- GLPRT_PTC1522L
- GLPRT_PTC255L
- GLPRT_PTC511L
- GLPRT_PTC64L
- GLPRT_PTC9522L
- GLPRT_PXOFFRXC
- GLPRT_PXOFFTXC
- GLPRT_PXONRXC
- GLPRT_PXONTXC
- GLPRT_RFC
- GLPRT_RJC
- GLPRT_RLEC
- GLPRT_ROC
- GLPRT_RUC
- GLPRT_RXON2OFFCNT
- GLPRT_TDOLD
- GLPRT_UPRCL
- GLPRT_UPTCL
- GLR_TRYFAILED
- GLSO_SEND_RPS
- GLSO_USE_DID
- GLTCLAN_CQ_CNTX
- GLUE
- GLUE_CBC_FUNC_CAST
- GLUE_CTR_FUNC_CAST
- GLUE_FUNC_CAST
- GLUE_XTS_FUNC_CAST
- GLV
- GLV_BPRCL
- GLV_BPTCL
- GLV_GORCL
- GLV_GOTCL
- GLV_MPRCL
- GLV_MPTCL
- GLV_RDPC
- GLV_TEPC
- GLV_UPRCL
- GLV_UPTCL
- GL_ADDR
- GL_ASYNC
- GL_CHIP_ID
- GL_CTRL0
- GL_CTRL1
- GL_CTRL2
- GL_CTRL3
- GL_DATA_FMT_MASK
- GL_DATA_FMT_SHIFT
- GL_EXACT
- GL_FMT_ARGB1555
- GL_FMT_ARGB4444
- GL_FMT_ARGB8888
- GL_FMT_RGB565
- GL_FMT_RGB888
- GL_GLOBAL_ALPHA_MASK
- GL_GLOBAL_ALPHA_SHIFT
- GL_GLOCK_DFT_HOLD
- GL_GLOCK_HOLD_DECR
- GL_GLOCK_HOLD_INCR
- GL_GLOCK_MAX_HOLD
- GL_GLOCK_MIN_HOLD
- GL_MAX_PACKET_LEN
- GL_MAX_TRANSMIT_PACKETS
- GL_MDET_RX
- GL_MDET_RX_MAL_TYPE_M
- GL_MDET_RX_MAL_TYPE_S
- GL_MDET_RX_PF_NUM_M
- GL_MDET_RX_PF_NUM_S
- GL_MDET_RX_QNUM_M
- GL_MDET_RX_QNUM_S
- GL_MDET_RX_VALID_M
- GL_MDET_RX_VF_NUM_M
- GL_MDET_RX_VF_NUM_S
- GL_MDET_TX_PQM
- GL_MDET_TX_PQM_MAL_TYPE_M
- GL_MDET_TX_PQM_MAL_TYPE_S
- GL_MDET_TX_PQM_PF_NUM_M
- GL_MDET_TX_PQM_PF_NUM_S
- GL_MDET_TX_PQM_QNUM_M
- GL_MDET_TX_PQM_QNUM_S
- GL_MDET_TX_PQM_VALID_M
- GL_MDET_TX_PQM_VF_NUM_M
- GL_MDET_TX_PQM_VF_NUM_S
- GL_MDET_TX_TCLAN
- GL_MDET_TX_TCLAN_MAL_TYPE_M
- GL_MDET_TX_TCLAN_MAL_TYPE_S
- GL_MDET_TX_TCLAN_PF_NUM_M
- GL_MDET_TX_TCLAN_PF_NUM_S
- GL_MDET_TX_TCLAN_QNUM_M
- GL_MDET_TX_TCLAN_QNUM_S
- GL_MDET_TX_TCLAN_VALID_M
- GL_MDET_TX_TCLAN_VF_NUM_M
- GL_MDET_TX_TCLAN_VF_NUM_S
- GL_NOCACHE
- GL_NUM
- GL_POS_END
- GL_POS_START
- GL_POS_X
- GL_POS_X_MASK
- GL_POS_X_SHIFT
- GL_POS_Y
- GL_POS_Y_MASK
- GL_POS_Y_SHIFT
- GL_PREEXT_L2_PMASK0
- GL_PREEXT_L2_PMASK1
- GL_PWR_MODE_CTL
- GL_PWR_MODE_CTL_CAR_MAX_BW_M
- GL_PWR_MODE_CTL_CAR_MAX_BW_S
- GL_RCV_BUF_SIZE
- GL_SCALER_BYPASS_MODE
- GL_SKIP
- GL_SRC_H
- GL_SRC_H_MASK
- GL_SRC_H_SHIFT
- GL_SRC_SIZE
- GL_SRC_W
- GL_SRC_W_MASK
- GL_SRC_W_SHIFT
- GL_STRIDE
- GL_UPDATE
- GL__CONSTANT_ALPHA
- GL__CONSTANT_COLOR
- GL__DST_ALPHA
- GL__DST_COLOR
- GL__ONE
- GL__ONE_MINUS_CONSTANT_ALPHA
- GL__ONE_MINUS_CONSTANT_COLOR
- GL__ONE_MINUS_DST_ALPHA
- GL__ONE_MINUS_DST_COLOR
- GL__ONE_MINUS_SRC_ALPHA
- GL__ONE_MINUS_SRC_COLOR
- GL__SRC_ALPHA
- GL__SRC_ALPHA_SATURATE
- GL__SRC_COLOR
- GL__ZERO
- GM100
- GM107_DISP
- GM107_DISP_CORE_CHANNEL_DMA
- GM12U320_BLOCK_COUNT
- GM12U320_ERR
- GM12U320_HEIGHT
- GM12U320_REAL_WIDTH
- GM12U320_USER_WIDTH
- GM200_DISP
- GM200_DISP_CORE_CHANNEL_DMA
- GM45_ERROR_CP_PRIV
- GM45_ERROR_MEM_PRIV
- GM45_ERROR_PAGE_TABLE
- GM45_GC_RENDER_CLOCK_266_MHZ
- GM45_GC_RENDER_CLOCK_320_MHZ
- GM45_GC_RENDER_CLOCK_400_MHZ
- GM45_GC_RENDER_CLOCK_533_MHZ
- GM45_GC_RENDER_CLOCK_MASK
- GM7113C
- GMAC0_HWTQ00_EOF_INT_BIT
- GMAC0_HWTQ01_EOF_INT_BIT
- GMAC0_HWTQ02_EOF_INT_BIT
- GMAC0_HWTQ03_EOF_INT_BIT
- GMAC0_INT_BITS
- GMAC0_IRQ0_2
- GMAC0_IRQ0_TXQ0_INTS
- GMAC0_IRQ4_8
- GMAC0_MIB_INT_BIT
- GMAC0_RESERVED_INT_BIT
- GMAC0_RXDERR_INT_BIT
- GMAC0_RXPERR_INT_BIT
- GMAC0_RX_OVERRUN_INT_BIT
- GMAC0_RX_PAUSE_OFF_INT_BIT
- GMAC0_RX_PAUSE_ON_INT_BIT
- GMAC0_SHUT
- GMAC0_STATUS_CHANGE_INT_BIT
- GMAC0_SWTQ00_EOF_INT_BIT
- GMAC0_SWTQ00_FIN_INT_BIT
- GMAC0_SWTQ01_EOF_INT_BIT
- GMAC0_SWTQ01_FIN_INT_BIT
- GMAC0_SWTQ02_EOF_INT_BIT
- GMAC0_SWTQ02_FIN_INT_BIT
- GMAC0_SWTQ03_EOF_INT_BIT
- GMAC0_SWTQ03_FIN_INT_BIT
- GMAC0_SWTQ04_EOF_INT_BIT
- GMAC0_SWTQ04_FIN_INT_BIT
- GMAC0_SWTQ05_EOF_INT_BIT
- GMAC0_SWTQ05_FIN_INT_BIT
- GMAC0_TXDERR_INT_BIT
- GMAC0_TXPERR_INT_BIT
- GMAC0_TX_PAUSE_OFF_INT_BIT
- GMAC0_TX_PAUSE_ON_INT_BIT
- GMAC0_USE_PWM01
- GMAC0_USE_TXCLK
- GMAC1_HWTQ10_EOF_INT_BIT
- GMAC1_HWTQ11_EOF_INT_BIT
- GMAC1_HWTQ12_EOF_INT_BIT
- GMAC1_HWTQ13_EOF_INT_BIT
- GMAC1_INT_BITS
- GMAC1_MIB_INT_BIT
- GMAC1_RESERVED_INT_BIT
- GMAC1_RXDERR_INT_BIT
- GMAC1_RXPERR_INT_BIT
- GMAC1_RX_OVERRUN_INT_BIT
- GMAC1_RX_PAUSE_OFF_INT_BIT
- GMAC1_RX_PAUSE_ON_INT_BIT
- GMAC1_SHUT
- GMAC1_STATUS_CHANGE_INT_BIT
- GMAC1_SWTQ10_EOF_INT_BIT
- GMAC1_SWTQ10_FIN_INT_BIT
- GMAC1_SWTQ11_EOF_INT_BIT
- GMAC1_SWTQ11_FIN_INT_BIT
- GMAC1_SWTQ12_EOF_INT_BIT
- GMAC1_SWTQ12_FIN_INT_BIT
- GMAC1_SWTQ13_EOF_INT_BIT
- GMAC1_SWTQ13_FIN_INT_BIT
- GMAC1_SWTQ14_EOF_INT_BIT
- GMAC1_SWTQ14_FIN_INT_BIT
- GMAC1_SWTQ15_EOF_INT_BIT
- GMAC1_SWTQ15_FIN_INT_BIT
- GMAC1_TXDERR_INT_BIT
- GMAC1_TXPERR_INT_BIT
- GMAC1_TX_PAUSE_OFF_INT_BIT
- GMAC1_TX_PAUSE_ON_INT_BIT
- GMAC1_USE_PWM23
- GMAC1_USE_TXCLK
- GMAC1_USE_UART0
- GMAC1_USE_UART1
- GMAC4_LPI_CTRL_STATUS
- GMAC4_LPI_CTRL_STATUS_LPIEN
- GMAC4_LPI_CTRL_STATUS_LPITCSE
- GMAC4_LPI_CTRL_STATUS_LPITXA
- GMAC4_LPI_CTRL_STATUS_PLS
- GMAC4_LPI_CTRL_STATUS_RLPIEN
- GMAC4_LPI_CTRL_STATUS_RLPIEX
- GMAC4_LPI_CTRL_STATUS_TLPIEN
- GMAC4_LPI_CTRL_STATUS_TLPIEX
- GMAC4_LPI_TIMER_CTRL
- GMAC4_PTP_SSIR_SSINC_SHIFT
- GMAC4_VERSION
- GMACSL_RET_WARN_RESET_INCOMPLETE
- GMAC_10000M_SGMII
- GMAC_1000M_GMII
- GMAC_1000M_RGMII
- GMAC_1000M_SGMII
- GMAC_100M_MII
- GMAC_100M_RGMII
- GMAC_100M_SGMII
- GMAC_10M_MII
- GMAC_10M_RGMII
- GMAC_10M_SGMII
- GMAC_125M_IN
- GMAC_1US_TIC_COUNTER
- GMAC_25M_OUT
- GMAC_50M_OUT
- GMAC_AAD_LEN
- GMAC_ACLK
- GMAC_ADDR_EN_B
- GMAC_ADDR_HIGH
- GMAC_ADDR_LOW
- GMAC_AHB_RESET
- GMAC_AHB_WEIGHT_REG
- GMAC_ANE_ACK
- GMAC_ANE_ADV
- GMAC_ANE_EXP
- GMAC_ANE_FD
- GMAC_ANE_HD
- GMAC_ANE_LPA
- GMAC_ANE_PSE
- GMAC_ANE_PSE_SHIFT
- GMAC_ANE_RFE
- GMAC_ANE_RFE_SHIFT
- GMAC_AN_CTRL
- GMAC_AN_CTRL_ANE
- GMAC_AN_CTRL_ECD
- GMAC_AN_CTRL_ELE
- GMAC_AN_CTRL_LR
- GMAC_AN_CTRL_RAN
- GMAC_AN_CTRL_SGMRAL
- GMAC_AN_NEG_STATE_REG
- GMAC_AN_NEG_STAT_AN_DONE_B
- GMAC_AN_NEG_STAT_FD_B
- GMAC_AN_NEG_STAT_HD_B
- GMAC_AN_NEG_STAT_NP_LNK_OK_B
- GMAC_AN_NEG_STAT_PS_M
- GMAC_AN_NEG_STAT_PS_S
- GMAC_AN_NEG_STAT_RF1_DUPLIEX_B
- GMAC_AN_NEG_STAT_RF2_B
- GMAC_AN_NEG_STAT_RX_SYNC_OK_B
- GMAC_AN_NEG_STAT_SPEED_M
- GMAC_AN_NEG_STAT_SPEED_S
- GMAC_AN_STATUS
- GMAC_AN_STATUS_ANA
- GMAC_AN_STATUS_ANC
- GMAC_AN_STATUS_ES
- GMAC_AN_STATUS_LS
- GMAC_ARP_ADDR
- GMAC_CF_CRC_STRIP_REG
- GMAC_CLK_CFG
- GMAC_CLK_ENB
- GMAC_CLK_SYNT
- GMAC_CONFIG
- GMAC_CONFIG0
- GMAC_CONFIG1
- GMAC_CONFIG2
- GMAC_CONFIG3
- GMAC_CONFIG_2K
- GMAC_CONFIG_ACS
- GMAC_CONFIG_ARPEN
- GMAC_CONFIG_BE
- GMAC_CONFIG_DCRS
- GMAC_CONFIG_DM
- GMAC_CONFIG_FES
- GMAC_CONFIG_INTF_RGMII
- GMAC_CONFIG_INTF_SEL_MASK
- GMAC_CONFIG_IPC
- GMAC_CONFIG_JD
- GMAC_CONFIG_JE
- GMAC_CONFIG_LM
- GMAC_CONFIG_PS
- GMAC_CONFIG_RE
- GMAC_CONFIG_SARC
- GMAC_CONFIG_SARC_SHIFT
- GMAC_CONFIG_TE
- GMAC_CONTROL
- GMAC_CONTROL_2K
- GMAC_CONTROL_ACS
- GMAC_CONTROL_BE
- GMAC_CONTROL_DC
- GMAC_CONTROL_DCRS
- GMAC_CONTROL_DM
- GMAC_CONTROL_DO
- GMAC_CONTROL_DR
- GMAC_CONTROL_FES
- GMAC_CONTROL_IFG_40
- GMAC_CONTROL_IFG_80
- GMAC_CONTROL_IFG_88
- GMAC_CONTROL_IPC
- GMAC_CONTROL_JD
- GMAC_CONTROL_JE
- GMAC_CONTROL_LM
- GMAC_CONTROL_LUD
- GMAC_CONTROL_PS
- GMAC_CONTROL_RE
- GMAC_CONTROL_TC
- GMAC_CONTROL_TE
- GMAC_CONTROL_WD
- GMAC_CORE1_CLK
- GMAC_CORE1_CLK_SRC
- GMAC_CORE1_RESET
- GMAC_CORE2_CLK
- GMAC_CORE2_CLK_SRC
- GMAC_CORE2_RESET
- GMAC_CORE3_CLK
- GMAC_CORE3_CLK_SRC
- GMAC_CORE3_RESET
- GMAC_CORE4_CLK
- GMAC_CORE4_CLK_SRC
- GMAC_CORE4_RESET
- GMAC_CORE_INIT
- GMAC_CTRL
- GMAC_DBG_CLK_LOS_MSK_B
- GMAC_DEBUG
- GMAC_DEBUG_RFCFCSTS_MASK
- GMAC_DEBUG_RFCFCSTS_SHIFT
- GMAC_DEBUG_RPESTS
- GMAC_DEBUG_RRCSTS_FLUSH
- GMAC_DEBUG_RRCSTS_IDLE
- GMAC_DEBUG_RRCSTS_MASK
- GMAC_DEBUG_RRCSTS_RDATA
- GMAC_DEBUG_RRCSTS_RSTAT
- GMAC_DEBUG_RRCSTS_SHIFT
- GMAC_DEBUG_RWCSTS
- GMAC_DEBUG_RXFSTS_AT
- GMAC_DEBUG_RXFSTS_BT
- GMAC_DEBUG_RXFSTS_EMPTY
- GMAC_DEBUG_RXFSTS_FULL
- GMAC_DEBUG_RXFSTS_MASK
- GMAC_DEBUG_RXFSTS_SHIFT
- GMAC_DEBUG_TFCSTS_GEN_PAUSE
- GMAC_DEBUG_TFCSTS_IDLE
- GMAC_DEBUG_TFCSTS_MASK
- GMAC_DEBUG_TFCSTS_SHIFT
- GMAC_DEBUG_TFCSTS_WAIT
- GMAC_DEBUG_TFCSTS_XFER
- GMAC_DEBUG_TPESTS
- GMAC_DEBUG_TRCSTS_IDLE
- GMAC_DEBUG_TRCSTS_MASK
- GMAC_DEBUG_TRCSTS_READ
- GMAC_DEBUG_TRCSTS_SHIFT
- GMAC_DEBUG_TRCSTS_TXW
- GMAC_DEBUG_TRCSTS_WRITE
- GMAC_DEBUG_TWCSTS
- GMAC_DEBUG_TXFSTS
- GMAC_DEBUG_TXPAUSED
- GMAC_DEBUG_TXSTSFSTS
- GMAC_DEF_MSK
- GMAC_DMA_CTRL_REG
- GMAC_DMA_RX_CURR_DESC_REG
- GMAC_DMA_RX_DESC_WORD0_REG
- GMAC_DMA_RX_DESC_WORD1_REG
- GMAC_DMA_RX_DESC_WORD2_REG
- GMAC_DMA_RX_DESC_WORD3_REG
- GMAC_DMA_RX_FIRST_DESC_REG
- GMAC_DMA_TX_CURR_DESC_REG
- GMAC_DMA_TX_DESC_WORD0_REG
- GMAC_DMA_TX_DESC_WORD1_REG
- GMAC_DMA_TX_DESC_WORD2_REG
- GMAC_DMA_TX_DESC_WORD3_REG
- GMAC_DMA_TX_FIRST_DESC_REG
- GMAC_DUPLEX_TYPE_B
- GMAC_DUPLEX_TYPE_REG
- GMAC_ETHTOOL_NAME
- GMAC_EXTHASH_BASE
- GMAC_FCB_LEN
- GMAC_FC_TX_TIMER_M
- GMAC_FC_TX_TIMER_REG
- GMAC_FC_TX_TIMER_S
- GMAC_FD_FC_ADDR_HIGH_REG
- GMAC_FD_FC_ADDR_LOW_REG
- GMAC_FD_FC_TYPE_REG
- GMAC_FIFO_ERR_AUTO_RST_B
- GMAC_FIFO_STATE_REG
- GMAC_FLOWCTRL_RELEASE_MAX
- GMAC_FLOWCTRL_RELEASE_MIN
- GMAC_FLOWCTRL_SET_MAX
- GMAC_FLOWCTRL_SET_MIN
- GMAC_FLOW_CTRL
- GMAC_FLOW_CTRL_FCB_BPA
- GMAC_FLOW_CTRL_PT_MASK
- GMAC_FLOW_CTRL_PT_SHIFT
- GMAC_FLOW_CTRL_RFE
- GMAC_FLOW_CTRL_TFE
- GMAC_FLOW_CTRL_UP
- GMAC_FRAME_FILTER
- GMAC_FRAME_FILTER_DAIF
- GMAC_FRAME_FILTER_DBF
- GMAC_FRAME_FILTER_HMC
- GMAC_FRAME_FILTER_HPF
- GMAC_FRAME_FILTER_HUC
- GMAC_FRAME_FILTER_PCF
- GMAC_FRAME_FILTER_PM
- GMAC_FRAME_FILTER_PR
- GMAC_FRAME_FILTER_RA
- GMAC_FRAME_FILTER_SAF
- GMAC_FRAME_FILTER_SAIF
- GMAC_FULL_DUPLEX
- GMAC_FULL_DUPLEX_MODE
- GMAC_HALF_DUPLEX_MODE
- GMAC_HASH_ENGINE_REG0
- GMAC_HASH_ENGINE_REG1
- GMAC_HASH_HIGH
- GMAC_HASH_LOW
- GMAC_HASH_TAB
- GMAC_HI_DCS
- GMAC_HI_DCS_SHIFT
- GMAC_HI_REG_AE
- GMAC_HW_FEATURE0
- GMAC_HW_FEATURE1
- GMAC_HW_FEATURE2
- GMAC_HW_FEATURE3
- GMAC_HW_FEAT_ADDMAC
- GMAC_HW_FEAT_ARPOFFSEL
- GMAC_HW_FEAT_ASP
- GMAC_HW_FEAT_AVSEL
- GMAC_HW_FEAT_DVLAN
- GMAC_HW_FEAT_EEESEL
- GMAC_HW_FEAT_FRPBS
- GMAC_HW_FEAT_FRPES
- GMAC_HW_FEAT_FRPSEL
- GMAC_HW_FEAT_GMIISEL
- GMAC_HW_FEAT_HDSEL
- GMAC_HW_FEAT_MGKSEL
- GMAC_HW_FEAT_MIISEL
- GMAC_HW_FEAT_MMCSEL
- GMAC_HW_FEAT_PCSSEL
- GMAC_HW_FEAT_PPSOUTNUM
- GMAC_HW_FEAT_RWKSEL
- GMAC_HW_FEAT_RXCHCNT
- GMAC_HW_FEAT_RXCOESEL
- GMAC_HW_FEAT_RXQCNT
- GMAC_HW_FEAT_SAVLANINS
- GMAC_HW_FEAT_SMASEL
- GMAC_HW_FEAT_TSSEL
- GMAC_HW_FEAT_TXCHCNT
- GMAC_HW_FEAT_TXCOSEL
- GMAC_HW_FEAT_TXQCNT
- GMAC_HW_FEAT_VLHASH
- GMAC_HW_HASH_TB_SZ
- GMAC_HW_RXFIFOSIZE
- GMAC_HW_TSOEN
- GMAC_HW_TXFIFOSIZE
- GMAC_HW_TX_QUEUE0_PTR_REG
- GMAC_HW_TX_QUEUE1_PTR_REG
- GMAC_HW_TX_QUEUE2_PTR_REG
- GMAC_HW_TX_QUEUE3_PTR_REG
- GMAC_HW_TX_QUEUE_BASE_REG
- GMAC_HW_TX_QUEUE_PTR_REG
- GMAC_INT_DEFAULT_ENABLE
- GMAC_INT_DEFAULT_MASK
- GMAC_INT_DISABLE_PCS
- GMAC_INT_DISABLE_PCSAN
- GMAC_INT_DISABLE_PCSLINK
- GMAC_INT_DISABLE_PMT
- GMAC_INT_DISABLE_RGMII
- GMAC_INT_DISABLE_TIMESTAMP
- GMAC_INT_EN
- GMAC_INT_LPI_EN
- GMAC_INT_MASK
- GMAC_INT_PCS_ANE
- GMAC_INT_PCS_LINK
- GMAC_INT_PCS_PHYIS
- GMAC_INT_PMT_EN
- GMAC_INT_RGSMIIS
- GMAC_INT_STATUS
- GMAC_INT_STATUS_LPIIS
- GMAC_INT_STATUS_MMCCSUM
- GMAC_INT_STATUS_MMCIS
- GMAC_INT_STATUS_MMCRIS
- GMAC_INT_STATUS_MMCTIS
- GMAC_INT_STATUS_PMT
- GMAC_INT_STATUS_TSTAMP
- GMAC_IN_BCAST
- GMAC_IN_DISCARDS
- GMAC_IN_ERRORS
- GMAC_IN_MAC1
- GMAC_IN_MAC2
- GMAC_IN_MCAST
- GMAC_IPG_TX_TIMER_REG
- GMAC_IRQ_MSK
- GMAC_IRQ_SRC
- GMAC_LD_LINK_COUNTER_REG
- GMAC_LINE_LOOPBACK_B
- GMAC_LINE_LOOP_BACK_REG
- GMAC_LINK_CTRL
- GMAC_LOOP_REG
- GMAC_LP_REG_CF2MI_LP_EN_B
- GMAC_LP_REG_CF_EXT_DRV_LP_B
- GMAC_MAC_SKIP_LEN_REG
- GMAC_MAX_FRM_SIZE_M
- GMAC_MAX_FRM_SIZE_REG
- GMAC_MAX_FRM_SIZE_S
- GMAC_MAX_PERFECT_ADDRESSES
- GMAC_MAX_PKT_LEN
- GMAC_MCAST_FIL0
- GMAC_MCAST_FIL1
- GMAC_MDIO_ADDR
- GMAC_MDIO_DATA
- GMAC_MIC_LEN
- GMAC_MII_ADDR
- GMAC_MII_ADDR_BUSY
- GMAC_MII_ADDR_WRITE
- GMAC_MII_DATA
- GMAC_MII_TX_EDGE_SEL_B
- GMAC_MIN_PKT_LEN
- GMAC_MMC_CTRL
- GMAC_MMC_RX_CSUM_OFFLOAD
- GMAC_MMC_RX_INTR
- GMAC_MMC_TX_INTR
- GMAC_MODE
- GMAC_MODE_CHANGE_EB_B
- GMAC_MODE_CHANGE_EN_REG
- GMAC_MR0CR0
- GMAC_MR0CR1
- GMAC_MR0CR2
- GMAC_MR1CR0
- GMAC_MR1CR1
- GMAC_MR1CR2
- GMAC_MR2CR0
- GMAC_MR2CR1
- GMAC_MR2CR2
- GMAC_MR3CR0
- GMAC_MR3CR1
- GMAC_MR3CR2
- GMAC_MUXREG
- GMAC_NONCE_LEN
- GMAC_OCTETS_TRANSMITTED_BAD_REG
- GMAC_OCTETS_TRANSMITTED_OK_REG
- GMAC_OFFLOAD_FEATURES
- GMAC_PACKET_FILTER
- GMAC_PACKET_FILTER_HMC
- GMAC_PACKET_FILTER_HPF
- GMAC_PACKET_FILTER_PCF
- GMAC_PACKET_FILTER_PM
- GMAC_PACKET_FILTER_PR
- GMAC_PACKET_FILTER_VTFE
- GMAC_PAUSE_EN_REG
- GMAC_PAUSE_EN_RX_FDFC_B
- GMAC_PAUSE_EN_TX_FDFC_B
- GMAC_PAUSE_EN_TX_HDFC_B
- GMAC_PAUSE_THR_REG
- GMAC_PCLK
- GMAC_PCS_BASE
- GMAC_PCS_IRQ_DEFAULT
- GMAC_PCS_RX_EN_REG
- GMAC_PHYIF_CONTROL_STATUS
- GMAC_PHYIF_CTRLSTATUS_FALSECARDET
- GMAC_PHYIF_CTRLSTATUS_JABTO
- GMAC_PHYIF_CTRLSTATUS_LNKMOD
- GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK
- GMAC_PHYIF_CTRLSTATUS_LNKSTS
- GMAC_PHYIF_CTRLSTATUS_LUD
- GMAC_PHYIF_CTRLSTATUS_SMIDRXS
- GMAC_PHYIF_CTRLSTATUS_SPEED
- GMAC_PHYIF_CTRLSTATUS_SPEED_125
- GMAC_PHYIF_CTRLSTATUS_SPEED_25
- GMAC_PHYIF_CTRLSTATUS_SPEED_2_5
- GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT
- GMAC_PHYIF_CTRLSTATUS_TC
- GMAC_PHY_125M_PAD_VAL
- GMAC_PHY_CLK_MASK
- GMAC_PHY_CLK_SHIFT
- GMAC_PHY_GMII
- GMAC_PHY_IF_GMII_VAL
- GMAC_PHY_IF_RGMII_VAL
- GMAC_PHY_IF_RMII_VAL
- GMAC_PHY_IF_SEL_MASK
- GMAC_PHY_IF_SGMII_VAL
- GMAC_PHY_INPUT_CLK_MASK
- GMAC_PHY_INPUT_CLK_SHIFT
- GMAC_PHY_INPUT_ENB_VAL
- GMAC_PHY_MII
- GMAC_PHY_OSC3_VAL
- GMAC_PHY_PLL2_VAL
- GMAC_PHY_RGMII_1000
- GMAC_PHY_RGMII_100_10
- GMAC_PHY_SYNT_ENB_VAL
- GMAC_PMT
- GMAC_PORT_EN_REG
- GMAC_PORT_MODE_M
- GMAC_PORT_MODE_REG
- GMAC_PORT_MODE_S
- GMAC_PORT_RX_EN_B
- GMAC_PORT_TX_EN_B
- GMAC_PPE_RX_PKT_MAX_LEN
- GMAC_PTP_CONFIG_REG
- GMAC_QX_TX_FLOW_CTRL
- GMAC_RECV_CONTROL_REG
- GMAC_RECV_CTRL_RUNT_PKT_EN_B
- GMAC_RECV_CTRL_STRIP_PAD_EN_B
- GMAC_REC_FILT_CONTROL_REG
- GMAC_REG3_MASK
- GMAC_REG4_MASK
- GMAC_REG_BMR
- GMAC_REG_FCR
- GMAC_REG_GAR
- GMAC_REG_GDR
- GMAC_REG_MCR
- GMAC_REG_MFFR
- GMAC_REG_NUM
- GMAC_REG_OMR
- GMAC_REG_RDLAR
- GMAC_REG_SHIFT_CR_GAR
- GMAC_REG_TDLAR
- GMAC_RESERVED
- GMAC_RESET_CONTROL_REG
- GMAC_RFCLK
- GMAC_RGMII_1000M_DELAY_B
- GMAC_RGSMIIIS
- GMAC_RGSMIIIS_FALSECARDET
- GMAC_RGSMIIIS_JABTO
- GMAC_RGSMIIIS_LNKMODE
- GMAC_RGSMIIIS_LNKMOD_MASK
- GMAC_RGSMIIIS_LNKSTS
- GMAC_RGSMIIIS_SMIDRXS
- GMAC_RGSMIIIS_SPEED
- GMAC_RGSMIIIS_SPEED_125
- GMAC_RGSMIIIS_SPEED_25
- GMAC_RGSMIIIS_SPEED_2_5
- GMAC_RGSMIIIS_SPEED_SHIFT
- GMAC_RMIICLK
- GMAC_RXDESC_0_T_chksum_status
- GMAC_RXDESC_0_T_derr
- GMAC_RXDESC_0_T_desc_count
- GMAC_RXDESC_0_T_perr
- GMAC_RXDESC_0_T_status
- GMAC_RXQCTRL_AVCPQ_MASK
- GMAC_RXQCTRL_AVCPQ_SHIFT
- GMAC_RXQCTRL_DCBCPQ_MASK
- GMAC_RXQCTRL_DCBCPQ_SHIFT
- GMAC_RXQCTRL_MCBCQEN
- GMAC_RXQCTRL_MCBCQEN_SHIFT
- GMAC_RXQCTRL_MCBCQ_MASK
- GMAC_RXQCTRL_MCBCQ_SHIFT
- GMAC_RXQCTRL_PSRQX_MASK
- GMAC_RXQCTRL_PSRQX_SHIFT
- GMAC_RXQCTRL_PTPQ_MASK
- GMAC_RXQCTRL_PTPQ_SHIFT
- GMAC_RXQCTRL_TACPQE
- GMAC_RXQCTRL_TACPQE_SHIFT
- GMAC_RXQCTRL_UPQ_MASK
- GMAC_RXQCTRL_UPQ_SHIFT
- GMAC_RXQ_CTRL0
- GMAC_RXQ_CTRL1
- GMAC_RXQ_CTRL2
- GMAC_RXQ_CTRL3
- GMAC_RX_ALIGN_ERRORS_REG
- GMAC_RX_AV_QUEUE_ENABLE
- GMAC_RX_BC_PKTS_REG
- GMAC_RX_DATA_ERR_REG
- GMAC_RX_DCB_QUEUE_ENABLE
- GMAC_RX_FAIL_COMMA_CNT_REG
- GMAC_RX_FCS_ERRORS_REG
- GMAC_RX_FILTER_AB
- GMAC_RX_FILTER_ACF
- GMAC_RX_FILTER_ACRC
- GMAC_RX_FILTER_AM
- GMAC_RX_FILTER_AOF
- GMAC_RX_FILTER_ARUNT
- GMAC_RX_FILTER_FDA
- GMAC_RX_FILTER_OSEN
- GMAC_RX_FILTER_PRM
- GMAC_RX_FILTER_RSV0
- GMAC_RX_FILTER_TXFC
- GMAC_RX_FILT_PKT_CNT_REG
- GMAC_RX_FLOW_CTRL
- GMAC_RX_FLOW_CTRL_RFE
- GMAC_RX_FLTR
- GMAC_RX_JABBER_ERRORS_REG
- GMAC_RX_LENGTHFIELD_ERR_CNT_REG
- GMAC_RX_LONG_ERRORS_REG
- GMAC_RX_MC_PKTS_REG
- GMAC_RX_OCTETS_BAD_REG
- GMAC_RX_OCTETS_TOTAL_FILT_REG
- GMAC_RX_OCTETS_TOTAL_OK_REG
- GMAC_RX_OVERRUN_CNT_REG
- GMAC_RX_PAUSE_MACCTRL_FRAM_REG
- GMAC_RX_PKTS_1024TO1518OCTETS_REG
- GMAC_RX_PKTS_128TO255OCTETS_REG
- GMAC_RX_PKTS_1519TOMAXOCTETS_REG
- GMAC_RX_PKTS_255TO511OCTETS_REG
- GMAC_RX_PKTS_512TO1023OCTETS_REG
- GMAC_RX_PKTS_64OCTETS_REG
- GMAC_RX_PKTS_65TO127OCTETS_REG
- GMAC_RX_QUEUE_CLEAR
- GMAC_RX_RUNT_ERR_CNT_REG
- GMAC_RX_SHORT_ERR_CNT_REG
- GMAC_RX_TAGGED_REG
- GMAC_RX_UC_PKTS_REG
- GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG
- GMAC_RX_VERY_LONG_ERR_CNT_REG
- GMAC_SHORT_RUNTS_THR_M
- GMAC_SHORT_RUNTS_THR_REG
- GMAC_SHORT_RUNTS_THR_S
- GMAC_SHUT
- GMAC_SIXTEEN_BIT_CNTR_REG
- GMAC_SPEED_10
- GMAC_SPEED_100
- GMAC_SPEED_1000
- GMAC_SPR0
- GMAC_SPR1
- GMAC_SPR2
- GMAC_SPR3
- GMAC_SPR4
- GMAC_SPR5
- GMAC_SPR6
- GMAC_SPR7
- GMAC_STATION_ADDR_HIGH_0_REG
- GMAC_STATION_ADDR_HIGH_1_REG
- GMAC_STATION_ADDR_HIGH_2_REG
- GMAC_STATION_ADDR_HIGH_3_REG
- GMAC_STATION_ADDR_HIGH_4_REG
- GMAC_STATION_ADDR_HIGH_5_REG
- GMAC_STATION_ADDR_HIGH_MSK_0_REG
- GMAC_STATION_ADDR_HIGH_MSK_1_REG
- GMAC_STATION_ADDR_LOW_0_REG
- GMAC_STATION_ADDR_LOW_1_REG
- GMAC_STATION_ADDR_LOW_2_REG
- GMAC_STATION_ADDR_LOW_3_REG
- GMAC_STATION_ADDR_LOW_4_REG
- GMAC_STATION_ADDR_LOW_5_REG
- GMAC_STATION_ADDR_LOW_MSK_0_REG
- GMAC_STATION_ADDR_LOW_MSK_1_REG
- GMAC_STATS_NUM
- GMAC_STATUS
- GMAC_STA_ADD0
- GMAC_STA_ADD1
- GMAC_STA_ADD2
- GMAC_SW_CONFIG_REG
- GMAC_SW_TX_QUEUE0_PTR_REG
- GMAC_SW_TX_QUEUE1_PTR_REG
- GMAC_SW_TX_QUEUE2_PTR_REG
- GMAC_SW_TX_QUEUE3_PTR_REG
- GMAC_SW_TX_QUEUE4_PTR_REG
- GMAC_SW_TX_QUEUE5_PTR_REG
- GMAC_SW_TX_QUEUE_BASE_REG
- GMAC_SW_TX_QUEUE_PTR_REG
- GMAC_TBI
- GMAC_TI_ST_CTRL
- GMAC_TI_ST_TST
- GMAC_TI_ST_VAL
- GMAC_TRANSMIT_CONTROL_REG
- GMAC_TXPAL_LEN
- GMAC_TXQCTRL_PSTQX_MASK
- GMAC_TXQCTRL_PSTQX_SHIFT
- GMAC_TXQ_PRTY_MAP0
- GMAC_TXQ_PRTY_MAP1
- GMAC_TX_AN_EN_B
- GMAC_TX_BC_PKTS_REG
- GMAC_TX_CRC_ADD_B
- GMAC_TX_CRC_ERROR_REG
- GMAC_TX_EXCESSIVE_LENGTH_DROP_REG
- GMAC_TX_FLOW_CTRL_PT_SHIFT
- GMAC_TX_FLOW_CTRL_TFE
- GMAC_TX_LOCAL_PAGE_REG
- GMAC_TX_LOOP_PKT_EN_B
- GMAC_TX_LOOP_PKT_HIG_PRI_B
- GMAC_TX_LOOP_PKT_PRI_REG
- GMAC_TX_MC_PKTS_REG
- GMAC_TX_PAD_EN_B
- GMAC_TX_PAUSE_FRAMES_REG
- GMAC_TX_PKTS_1024TO1518OCTETS_REG
- GMAC_TX_PKTS_128TO255OCTETS_REG
- GMAC_TX_PKTS_1519TOMAXOCTETS_REG
- GMAC_TX_PKTS_255TO511OCTETS_REG
- GMAC_TX_PKTS_512TO1023OCTETS_REG
- GMAC_TX_PKTS_64OCTETS_REG
- GMAC_TX_PKTS_65TO127OCTETS_REG
- GMAC_TX_TAGGED_REG
- GMAC_TX_UC_PKTS_REG
- GMAC_TX_UNDERRUN_REG
- GMAC_TX_WATER_LINE_MASK
- GMAC_TX_WATER_LINE_REG
- GMAC_TX_WATER_LINE_SHIFT
- GMAC_TX_WEIGHTING_CTRL_0_REG
- GMAC_TX_WEIGHTING_CTRL_1_REG
- GMAC_UC_MATCH_EN_B
- GMAC_VERSION
- GMAC_VLAN_CODE_REG
- GMAC_VLAN_CSVL
- GMAC_VLAN_DOVLTC
- GMAC_VLAN_EDVLP
- GMAC_VLAN_ESVL
- GMAC_VLAN_ETV
- GMAC_VLAN_HASH_TABLE
- GMAC_VLAN_INCL
- GMAC_VLAN_TAG
- GMAC_VLAN_VID
- GMAC_VLAN_VLC
- GMAC_VLAN_VLC_SHIFT
- GMAC_VLAN_VLTI
- GMAC_VLAN_VTHM
- GMAC_WAKEUP_FILTER
- GMAP_FAULT
- GMAP_NOTIFY_MPROT
- GMAP_NOTIFY_SHADOW
- GMAP_SHADOW_FAKE_TABLE
- GMA_COEF_REG
- GMA_CTL_REG
- GMA_PLL_INVALID
- GMBUS
- GMBUS0
- GMBUS1
- GMBUS1_TOTAL_BYTES_MASK
- GMBUS1_TOTAL_BYTES_SHIFT
- GMBUS2
- GMBUS3
- GMBUS4
- GMBUS5
- GMBUSFREQ_VLV
- GMBUS_2BYTE_INDEX_EN
- GMBUS_ACTIVE
- GMBUS_AKSV_SELECT
- GMBUS_BYTE_CNT_OVERRIDE
- GMBUS_BYTE_COUNT_MAX
- GMBUS_BYTE_COUNT_SHIFT
- GMBUS_CYCLE_INDEX
- GMBUS_CYCLE_NONE
- GMBUS_CYCLE_STOP
- GMBUS_CYCLE_WAIT
- GMBUS_DATA_PHASE
- GMBUS_ENT
- GMBUS_FORCE_BIT_RETRY
- GMBUS_HOLD_EXT
- GMBUS_HW_RDY
- GMBUS_HW_RDY_EN
- GMBUS_HW_WAIT_EN
- GMBUS_HW_WAIT_PHASE
- GMBUS_IDLE_EN
- GMBUS_IDLE_PHASE
- GMBUS_INT
- GMBUS_INUSE
- GMBUS_MAX_PHASE
- GMBUS_NAK_EN
- GMBUS_NOCYCLE
- GMBUS_NUM_PINS
- GMBUS_NUM_PORTS
- GMBUS_PIN_10_TC2_ICP
- GMBUS_PIN_11_TC3_ICP
- GMBUS_PIN_12_TC4_ICP
- GMBUS_PIN_13_TC5_TGP
- GMBUS_PIN_14_TC6_TGP
- GMBUS_PIN_1_BXT
- GMBUS_PIN_2_BXT
- GMBUS_PIN_3_BXT
- GMBUS_PIN_4_CNP
- GMBUS_PIN_9_TC1_ICP
- GMBUS_PIN_DISABLED
- GMBUS_PIN_DPB
- GMBUS_PIN_DPC
- GMBUS_PIN_DPD
- GMBUS_PIN_DPD_CHV
- GMBUS_PIN_PANEL
- GMBUS_PIN_RESERVED
- GMBUS_PIN_SSC
- GMBUS_PIN_VGADDC
- GMBUS_PORT_DISABLED
- GMBUS_PORT_DPB
- GMBUS_PORT_DPC
- GMBUS_PORT_DPD
- GMBUS_PORT_PANEL
- GMBUS_PORT_SSC
- GMBUS_PORT_VGADDC
- GMBUS_RATE_100KHZ
- GMBUS_RATE_1MHZ
- GMBUS_RATE_400KHZ
- GMBUS_RATE_50KHZ
- GMBUS_REG_READ
- GMBUS_REG_WRITE
- GMBUS_SATOER
- GMBUS_SLAVE_ADDR_SHIFT
- GMBUS_SLAVE_INDEX_SHIFT
- GMBUS_SLAVE_READ
- GMBUS_SLAVE_TIMEOUT_EN
- GMBUS_SLAVE_WRITE
- GMBUS_STALL_TIMEOUT
- GMBUS_STOP
- GMBUS_SW_CLR_INT
- GMBUS_SW_RDY
- GMBUS_WAIT_PHASE
- GMCON_DEBUG__GFX_CLEAR_MASK
- GMCON_DEBUG__GFX_CLEAR__SHIFT
- GMCON_DEBUG__GFX_STALL_MASK
- GMCON_DEBUG__GFX_STALL__SHIFT
- GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK
- GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT
- GMCON_DEBUG__MISC_FLAGS_MASK
- GMCON_DEBUG__MISC_FLAGS__SHIFT
- GMCON_DEBUG__SR_COMMIT_STATE_MASK
- GMCON_DEBUG__SR_COMMIT_STATE__SHIFT
- GMCON_DEBUG__STCTRL_ST_MASK
- GMCON_DEBUG__STCTRL_ST__SHIFT
- GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK
- GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT
- GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK
- GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT
- GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK
- GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT
- GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK
- GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT
- GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK
- GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT
- GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK
- GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT
- GMCON_MISC
- GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK
- GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT
- GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK
- GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT
- GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0_MASK
- GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE0__SHIFT
- GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1_MASK
- GMCON_MISC2__RENG_MEM_POWER_CTRL_OVERRIDE1__SHIFT
- GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK
- GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT
- GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK
- GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT
- GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK
- GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT
- GMCON_MISC2__STCTRL_LPT_TARGET_MASK
- GMCON_MISC2__STCTRL_LPT_TARGET__SHIFT
- GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK
- GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT
- GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK
- GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT
- GMCON_MISC3
- GMCON_MISC3__RENG_DISABLE_MCC_MASK
- GMCON_MISC3__RENG_DISABLE_MCC__SHIFT
- GMCON_MISC3__RENG_DISABLE_MCD_MASK
- GMCON_MISC3__RENG_DISABLE_MCD__SHIFT
- GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK
- GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT
- GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK
- GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT
- GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK
- GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT
- GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK
- GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT
- GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK
- GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT
- GMCON_MISC__CRITICAL_REGS_LOCK_MASK
- GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT
- GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK
- GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT
- GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK
- GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT
- GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK
- GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT
- GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK
- GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT
- GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK
- GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT
- GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK
- GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT
- GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK
- GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT
- GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK
- GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT
- GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK
- GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT
- GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK
- GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT
- GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK
- GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT
- GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK
- GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT
- GMCON_MISC__STCTRL_STUTTER_EN_MASK
- GMCON_MISC__STCTRL_STUTTER_EN__SHIFT
- GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK
- GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT
- GMCON_PERF_MON_CNTL0__START_MODE_MASK
- GMCON_PERF_MON_CNTL0__START_MODE__SHIFT
- GMCON_PERF_MON_CNTL0__START_THRESH_MASK
- GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT
- GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK
- GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT
- GMCON_PERF_MON_CNTL0__STOP_MODE_MASK
- GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT
- GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK
- GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT
- GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK
- GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT
- GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK
- GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT
- GMCON_PERF_MON_CNTL1__MON0_ID_MASK
- GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT
- GMCON_PERF_MON_CNTL1__MON1_ID_MASK
- GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT
- GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK
- GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT
- GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK
- GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT
- GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK
- GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT
- GMCON_PERF_MON_RSLT0__COUNT_MASK
- GMCON_PERF_MON_RSLT0__COUNT__SHIFT
- GMCON_PERF_MON_RSLT1__COUNT_MASK
- GMCON_PERF_MON_RSLT1__COUNT__SHIFT
- GMCON_PGFSM_CONFIG
- GMCON_PGFSM_CONFIG__FSM_ADDR_MASK
- GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT
- GMCON_PGFSM_CONFIG__P1_SELECT_MASK
- GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT
- GMCON_PGFSM_CONFIG__P2_SELECT_MASK
- GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT
- GMCON_PGFSM_CONFIG__POWER_DOWN_MASK
- GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT
- GMCON_PGFSM_CONFIG__POWER_UP_MASK
- GMCON_PGFSM_CONFIG__POWER_UP__SHIFT
- GMCON_PGFSM_CONFIG__READ_MASK
- GMCON_PGFSM_CONFIG__READ__SHIFT
- GMCON_PGFSM_CONFIG__REG_ADDR_MASK
- GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT
- GMCON_PGFSM_CONFIG__RSRVD_MASK
- GMCON_PGFSM_CONFIG__RSRVD__SHIFT
- GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK
- GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT
- GMCON_PGFSM_CONFIG__WRITE_MASK
- GMCON_PGFSM_CONFIG__WRITE__SHIFT
- GMCON_PGFSM_READ
- GMCON_PGFSM_READ__PGFSM_SELECT_MASK
- GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT
- GMCON_PGFSM_READ__READ_VALUE_MASK
- GMCON_PGFSM_READ__READ_VALUE__SHIFT
- GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK
- GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT
- GMCON_PGFSM_WRITE
- GMCON_PGFSM_WRITE__WRITE_VALUE_MASK
- GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT
- GMCON_RENG_EXECUTE
- GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK
- GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT
- GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK
- GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT
- GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK
- GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK
- GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT
- GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT
- GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK
- GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT
- GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK
- GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT
- GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK
- GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK
- GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT
- GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK
- GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT
- GMC_3D_FCN_EN_CLR
- GMC_3D_FCN_EN_SET
- GMC_6_0_D_H
- GMC_6_0_SH_MASK_H
- GMC_7_0_D_H
- GMC_7_0_SH_MASK_H
- GMC_7_1_D_H
- GMC_7_1_SH_MASK_H
- GMC_8_1_D_H
- GMC_8_1_ENUM_H
- GMC_8_1_SH_MASK_H
- GMC_8_2_D_H
- GMC_8_2_ENUM_H
- GMC_8_2_SH_MASK_H
- GMC_AUX_CLIP_CLEAR
- GMC_AUX_CLIP_LEAVE
- GMC_BRUSH_1x8COLOR
- GMC_BRUSH_1x8MONO
- GMC_BRUSH_1x8MONO_LBKGD
- GMC_BRUSH_32x1MONO
- GMC_BRUSH_32x1MONO_LBKGD
- GMC_BRUSH_32x32MONO
- GMC_BRUSH_32x32MONO_LBKGD
- GMC_BRUSH_8x1COLOR
- GMC_BRUSH_8x1MONO
- GMC_BRUSH_8x1MONO_LBKGD
- GMC_BRUSH_8x8COLOR
- GMC_BRUSH_8x8MONO
- GMC_BRUSH_8x8MONO_LBKGD
- GMC_BRUSH_NONE
- GMC_BRUSH_SOLIDCOLOR
- GMC_BRUSH_SOLID_COLOR
- GMC_BYP_MACSECRX_OFF
- GMC_BYP_MACSECRX_ON
- GMC_BYP_MACSECTX_OFF
- GMC_BYP_MACSECTX_ON
- GMC_BYP_RETR_OFF
- GMC_BYP_RETR_ON
- GMC_BYTE_ORDER_LSB_TO_MSB
- GMC_BYTE_ORDER_MSB_TO_LSB
- GMC_CLR_CMP_CNTL_DIS
- GMC_DP_CONVERSION_TEMP_6500
- GMC_DP_CONVERSION_TEMP_9300
- GMC_DP_SRC_HOST
- GMC_DP_SRC_HOST_BYTEALIGN
- GMC_DP_SRC_RECT
- GMC_DST_15BPP
- GMC_DST_16BPP
- GMC_DST_16BPP_ARGB4444
- GMC_DST_16BPP_VYUY422
- GMC_DST_16BPP_YVYU422
- GMC_DST_24BPP
- GMC_DST_32BPP
- GMC_DST_32BPP_AYUV444
- GMC_DST_8BPP
- GMC_DST_8BPP_RGB332
- GMC_DST_8BPP_RGB8
- GMC_DST_8BPP_Y8
- GMC_DST_CLIP_DEFAULT
- GMC_DST_CLIP_LEAVE
- GMC_DST_CLR_CMP_FCN_CLEAR
- GMC_DST_CLR_CMP_FCN_LEAVE
- GMC_DST_PITCH_OFFSET_DEFAULT
- GMC_DST_PITCH_OFFSET_LEAVE
- GMC_F_LOOPB_OFF
- GMC_F_LOOPB_ON
- GMC_H_BURST_OFF
- GMC_H_BURST_ON
- GMC_PAUSE_OFF
- GMC_PAUSE_ON
- GMC_PWR_GATER_BUSY
- GMC_PWR_GATER_STATE
- GMC_RST_CLR
- GMC_RST_SET
- GMC_SEC_RST_OFF
- GMC_SET_RST
- GMC_SRC_CLIP_DEFAULT
- GMC_SRC_CLIP_LEAVE
- GMC_SRC_DATATYPE_COLOR
- GMC_SRC_DSTCOLOR
- GMC_SRC_MONO
- GMC_SRC_MONO_LBKGD
- GMC_SRC_PITCH_OFFSET_DEFAULT
- GMC_SRC_PITCH_OFFSET_LEAVE
- GMC_WRITE_MASK_LEAVE
- GMC_WRITE_MASK_SET
- GMEM
- GMEM_AXI_CLK
- GMEM_CLAMP_IO_MASK
- GMEM_RESET_MASK
- GMF_ASF_RX_OVER_OFF
- GMF_ASF_RX_OVER_ON
- GMF_CLI_RX_C
- GMF_CLI_RX_FC
- GMF_CLI_RX_FO
- GMF_CLI_TX_FC
- GMF_CLI_TX_FU
- GMF_CLI_TX_PE
- GMF_OPER_OFF
- GMF_OPER_ON
- GMF_RP_STEP
- GMF_RP_TST_OFF
- GMF_RP_TST_ON
- GMF_RST_CLR
- GMF_RST_SET
- GMF_RX_CTRL_DEF
- GMF_RX_F_FL_OFF
- GMF_RX_F_FL_ON
- GMF_RX_OVER_OFF
- GMF_RX_OVER_ON
- GMF_WP_STEP
- GMF_WP_TST_OFF
- GMF_WP_TST_ON
- GMF_WSP_STEP
- GMF_WSP_TST_OFF
- GMF_WSP_TST_ON
- GMIIControl
- GMII_COL
- GMII_CRS
- GMII_GTX_CLK
- GMII_LED0_ACTIVE
- GMII_LED0_LINK_10
- GMII_LED0_LINK_100
- GMII_LED0_LINK_1000
- GMII_LED1_ACTIVE
- GMII_LED1_LINK_10
- GMII_LED1_LINK_100
- GMII_LED1_LINK_1000
- GMII_LED2_ACTIVE
- GMII_LED2_LINK_10
- GMII_LED2_LINK_100
- GMII_LED2_LINK_1000
- GMII_LED_ACT
- GMII_LED_ACTIVE_MASK
- GMII_LED_LINK
- GMII_LED_LINK_MASK
- GMII_MDC
- GMII_MDIO
- GMII_PHYPAGE
- GMII_PHY_PAGE_SELECT
- GMII_PHY_PGSEL_EXT
- GMII_PHY_PGSEL_PAGE0
- GMII_PHY_PGSEL_PAGE3
- GMII_PHY_PGSEL_PAGE5
- GMII_PHY_PHYSR
- GMII_PHY_PHYSR_100
- GMII_PHY_PHYSR_FULL
- GMII_PHY_PHYSR_GIGA
- GMII_PHY_PHYSR_LINK
- GMII_PHY_PHYSR_SMASK
- GMII_PO_EN
- GMII_PO_FULL_DUPLEX
- GMII_PO_LINK
- GMII_PO_RX_FLOW
- GMII_PO_SPEED_1000M
- GMII_PO_SPEED_100M
- GMII_PO_SPEED_10M
- GMII_PO_SPEED_2000M
- GMII_PO_SPEED_S
- GMII_PO_TX_FLOW
- GMII_RXD0
- GMII_RXD1
- GMII_RXD2
- GMII_RXD3
- GMII_RXD4
- GMII_RXD5
- GMII_RXD6
- GMII_RXD7
- GMII_RX_CLK
- GMII_RX_DV
- GMII_RX_ER
- GMII_SEL_MODE_MASK
- GMII_SPEED_UP_2G
- GMII_TXD0
- GMII_TXD1
- GMII_TXD2
- GMII_TXD3
- GMII_TXD4
- GMII_TXD5
- GMII_TXD6
- GMII_TXD7
- GMII_TX_CLK
- GMII_TX_EN
- GMII_TX_ER
- GMIR_INT_POLARITY
- GMIR_MDEV_INT
- GMIR_MHC_INT
- GMIR_MOTG_INT
- GMI_PORT_CFG_DUPLEX
- GMI_PORT_CFG_RX_IDLE
- GMI_PORT_CFG_SLOT_TIME
- GMI_PORT_CFG_SPEED
- GMI_PORT_CFG_SPEED_MSB
- GMI_PORT_CFG_TX_IDLE
- GMI_TXX_INT_LATE_COL
- GMI_TXX_INT_PTP_LOST
- GMI_TXX_INT_UNDFLW
- GMI_TXX_INT_XSCOL
- GMI_TXX_INT_XSDEF
- GMLC_RST_CLR
- GMLC_RST_SET
- GML_11KHZ
- GML_16KHZ
- GML_22KHZ
- GML_32KHZ
- GML_44KHZ
- GML_48KHZ
- GML_88KHZ
- GML_8KHZ
- GML_96KHZ
- GML_ADAT_CLOCK
- GML_ADAT_MODE
- GML_CLOCK_CLEAR_MASK
- GML_CLOCK_DETECT_BIT_ADAT
- GML_CLOCK_DETECT_BIT_ESYNC
- GML_CLOCK_DETECT_BIT_SPDIF
- GML_CLOCK_DETECT_BIT_SPDIF48
- GML_CLOCK_DETECT_BIT_SPDIF96
- GML_CLOCK_DETECT_BIT_WORD
- GML_CLOCK_DETECT_BIT_WORD48
- GML_CLOCK_DETECT_BIT_WORD96
- GML_CONVERTER_ENABLE
- GML_DIGITAL_IN_AUTO_MUTE
- GML_DIGITAL_MODE_CLEAR_MASK
- GML_DOUBLE_SPEED_MODE
- GML_ESYNC_CLOCK
- GML_ESYNCx2_CLOCK
- GML_SPDIF_24_BIT
- GML_SPDIF_CDROM_MODE
- GML_SPDIF_CLOCK
- GML_SPDIF_COPY_PERMIT
- GML_SPDIF_FORMAT_CLEAR_MASK
- GML_SPDIF_NOT_AUDIO
- GML_SPDIF_OPTICAL_MODE
- GML_SPDIF_PRO_MODE
- GML_SPDIF_RATE_CLEAR_MASK
- GML_SPDIF_SAMPLE_RATE0
- GML_SPDIF_SAMPLE_RATE1
- GML_SPDIF_TWO_CHANNEL
- GML_WORD_CLOCK
- GMM_ON_OFF
- GMODE_AUTO
- GMODE_B_DEFERRED
- GMODE_LEGACY_B
- GMODE_LRS
- GMODE_MAX
- GMODE_ONLY
- GMODE_PALETTE4BIT
- GMODE_PALETTE8BIT
- GMODE_PERFORMANCE
- GMODE_RESERVED
- GMODE_RGB1555
- GMODE_RGB565
- GMODE_RGB888PACKED
- GMODE_RGB888UNPACKED
- GMODE_RGBA888
- GMODE_SMPNCMD
- GMODE_YUV420PLANAR
- GMODE_YUV422PACKED
- GMODE_YUV422PLANAR
- GMPX_GMI_RX_INT
- GMPX_GMI_TX_INT
- GMPX_PCS_INT
- GMP_GRANULARITY
- GMR_FS_ANY_ERR
- GMR_FS_BAD_FC
- GMR_FS_BC
- GMR_FS_CRC_ERR
- GMR_FS_FRAGMENT
- GMR_FS_GOOD_FC
- GMR_FS_JABBER
- GMR_FS_LEN
- GMR_FS_LEN_SHIFT
- GMR_FS_LONG_ERR
- GMR_FS_MC
- GMR_FS_MII_ERR
- GMR_FS_RX_FF_OV
- GMR_FS_RX_OK
- GMR_FS_UN_SIZE
- GMR_FS_VLAN
- GMTT
- GMT_BOT
- GMT_CLN
- GMT_DR_OPEN
- GMT_D_1600
- GMT_D_6250
- GMT_D_800
- GMT_EOD
- GMT_EOF
- GMT_EOT
- GMT_IM_REP_EN
- GMT_ONLINE
- GMT_SM
- GMT_ST_CLR_IRQ
- GMT_ST_START
- GMT_ST_STOP
- GMT_TOKEN_SIZE
- GMT_WR_PROT
- GMUX_ACPI_HID
- GMUX_BRIGHTNESS_MASK
- GMUX_INTERRUPT_DISABLE
- GMUX_INTERRUPT_ENABLE
- GMUX_INTERRUPT_STATUS_ACTIVE
- GMUX_INTERRUPT_STATUS_DISPLAY
- GMUX_INTERRUPT_STATUS_HOTPLUG
- GMUX_INTERRUPT_STATUS_POWER
- GMUX_MAX_BRIGHTNESS
- GMUX_MIN_IO_LEN
- GMUX_PORT_BRIGHTNESS
- GMUX_PORT_DISCRETE_POWER
- GMUX_PORT_INTERRUPT_ENABLE
- GMUX_PORT_INTERRUPT_STATUS
- GMUX_PORT_MAX_BRIGHTNESS
- GMUX_PORT_READ
- GMUX_PORT_SWITCH_DDC
- GMUX_PORT_SWITCH_DISPLAY
- GMUX_PORT_SWITCH_EXTERNAL
- GMUX_PORT_SWITCH_GET_DISPLAY
- GMUX_PORT_SWITCH_GET_EXTERNAL
- GMUX_PORT_VALUE
- GMUX_PORT_VERSION_MAJOR
- GMUX_PORT_VERSION_MINOR
- GMUX_PORT_VERSION_RELEASE
- GMUX_PORT_WRITE
- GMU_COLD_BOOT
- GMU_IDLE_STATE_ACTIVE
- GMU_IDLE_STATE_IFPC
- GMU_IDLE_STATE_SPTP
- GMU_OOB_BOOT_SLUMBER
- GMU_OOB_BOOT_SLUMBER_ACK
- GMU_OOB_BOOT_SLUMBER_CLEAR
- GMU_OOB_BOOT_SLUMBER_REQUEST
- GMU_OOB_DCVS_ACK
- GMU_OOB_DCVS_CLEAR
- GMU_OOB_DCVS_REQUEST
- GMU_OOB_DCVS_SET
- GMU_OOB_GPU_SET
- GMU_OOB_GPU_SET_ACK
- GMU_OOB_GPU_SET_CLEAR
- GMU_OOB_GPU_SET_REQUEST
- GMU_PWR_COL_HYST
- GMU_WARM_BOOT
- GM_CHIP_ID
- GM_GPCR_AU_ALL_DIS
- GM_GPCR_AU_DUP_DIS
- GM_GPCR_AU_FCT_DIS
- GM_GPCR_AU_SPD_DIS
- GM_GPCR_BURST_ENA
- GM_GPCR_DUP_FULL
- GM_GPCR_FC_RX_DIS
- GM_GPCR_FC_TX_DIS
- GM_GPCR_FL_PASS
- GM_GPCR_GIGS_ENA
- GM_GPCR_LOOP_ENA
- GM_GPCR_PART_ENA
- GM_GPCR_PROM_ENA
- GM_GPCR_RX_ENA
- GM_GPCR_SPEED_100
- GM_GPCR_SPEED_1000
- GM_GPCR_TX_ENA
- GM_GPSR_DUPLEX
- GM_GPSR_EXC_COL
- GM_GPSR_FC_RX_DIS
- GM_GPSR_FC_TX_DIS
- GM_GPSR_GIG_SPEED
- GM_GPSR_LAT_COL
- GM_GPSR_LINK_UP
- GM_GPSR_PART_MODE
- GM_GPSR_PAUSE
- GM_GPSR_PHY_ST_CH
- GM_GPSR_PROM_EN
- GM_GPSR_SPEED
- GM_GPSR_TX_ACTIVE
- GM_GP_CTRL
- GM_GP_STAT
- GM_IS_RX_COMPL
- GM_IS_RX_CO_OV
- GM_IS_RX_FF_OR
- GM_IS_TX_COMPL
- GM_IS_TX_CO_OV
- GM_IS_TX_FF_UR
- GM_MC_ADDR_H1
- GM_MC_ADDR_H2
- GM_MC_ADDR_H3
- GM_MC_ADDR_H4
- GM_MIB_CNT_BASE
- GM_MIB_CNT_END
- GM_MIB_CNT_SIZE
- GM_NEW_FLOW_CTRL
- GM_PAR_MIB_CLR
- GM_PAR_MIB_TST
- GM_PHY_ADDR
- GM_PHY_RETRIES
- GM_RXCR_CRC_DIS
- GM_RXCR_MCF_ENA
- GM_RXCR_PASS_FC
- GM_RXCR_UCF_ENA
- GM_RXE_FIFO_OV
- GM_RXE_FRAG
- GM_RXF_1023B
- GM_RXF_127B
- GM_RXF_1518B
- GM_RXF_255B
- GM_RXF_511B
- GM_RXF_64B
- GM_RXF_BC_OK
- GM_RXF_FCS_ERR
- GM_RXF_JAB_PKT
- GM_RXF_LNG_ERR
- GM_RXF_MAX_SZ
- GM_RXF_MC_OK
- GM_RXF_MPAUSE
- GM_RXF_SHT
- GM_RXF_UC_OK
- GM_RXO_ERR_HI
- GM_RXO_ERR_LO
- GM_RXO_OK_HI
- GM_RXO_OK_LO
- GM_RX_CTRL
- GM_RX_IRQ_MSK
- GM_RX_IRQ_SRC
- GM_SERIAL_MODE
- GM_SMI_CTRL
- GM_SMI_CT_BUSY
- GM_SMI_CT_OP_RD
- GM_SMI_CT_PHY_AD
- GM_SMI_CT_PHY_A_MSK
- GM_SMI_CT_RD_VAL
- GM_SMI_CT_REG_AD
- GM_SMI_CT_REG_A_MSK
- GM_SMI_DATA
- GM_SMOD_DATABL_MSK
- GM_SMOD_IPG_MSK
- GM_SMOD_JUMBO_ENA
- GM_SMOD_LIMIT_4
- GM_SMOD_VLAN_ENA
- GM_SRC_ADDR_1H
- GM_SRC_ADDR_1L
- GM_SRC_ADDR_1M
- GM_SRC_ADDR_2H
- GM_SRC_ADDR_2L
- GM_SRC_ADDR_2M
- GM_SYNTH_PORT
- GM_TR_IRQ_MSK
- GM_TR_IRQ_SRC
- GM_TXCR_COL_THR_MSK
- GM_TXCR_CRC_DIS
- GM_TXCR_FORCE_JAM
- GM_TXCR_PAD_DIS
- GM_TXE_FIFO_UR
- GM_TXF_1023B
- GM_TXF_127B
- GM_TXF_1518B
- GM_TXF_255B
- GM_TXF_511B
- GM_TXF_64B
- GM_TXF_ABO_COL
- GM_TXF_BC_OK
- GM_TXF_COL
- GM_TXF_LAT_COL
- GM_TXF_MAX_SZ
- GM_TXF_MC_OK
- GM_TXF_MPAUSE
- GM_TXF_MUL_COL
- GM_TXF_SNG_COL
- GM_TXF_UC_OK
- GM_TXO_OK_HI
- GM_TXO_OK_LO
- GM_TXPA_BO_LIM_MSK
- GM_TXPA_JAMDAT_MSK
- GM_TXPA_JAMIPG_MSK
- GM_TXPA_JAMLEN_MSK
- GM_TX_CTRL
- GM_TX_FLOW_CTRL
- GM_TX_IRQ_MSK
- GM_TX_IRQ_SRC
- GM_TX_PARAM
- GM_USBPHY_TX_D_CAL
- GM_USBPHY_TX_TXCAL45DN
- GM_USBPHY_TX_TXCAL45DP
- GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6_MASK
- GNBPM_SMU_PWRMGT_DATA__UNBPM_AllCpusInCC6__SHIFT
- GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive_MASK
- GNBPM_SMU_PWRMGT_DATA__UNBPM_HtcActive__SHIFT
- GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE_MASK
- GNBPM_SMU_PWRMGT_DATA__UNBPM_SPARE__SHIFT
- GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt_MASK
- GNBPM_SMU_PWRMGT_DATA__UNBPM_SmuInt__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_AllCpusInCC6__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_AllowNbPstate__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_AllowSelfRefresh__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_HtcActive__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_IntrWake__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_PreSelfRefresh__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_ReqNbPstate__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_SmuIntSuperVminExit__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt_MASK
- GNBPM_SMU_PWRMGT_STATUS__PM_SmuInt__SHIFT
- GNBPM_SMU_PWRMGT_STATUS__SPARE_MASK
- GNBPM_SMU_PWRMGT_STATUS__SPARE__SHIFT
- GNB_SLOW
- GNB_SLOW_FSTATE_0_MASK
- GNB_SLOW_FSTATE_0_SHIFT
- GNB_SLOW_MASK
- GNB_SLOW_MODE
- GNB_SLOW_MODE_MASK
- GNB_SLOW_MODE_SHIFT
- GNB_SLOW_SHIFT
- GNB_TDP_LIMIT
- GNB_THERMTHRO_MASK
- GNB_TT
- GNB_TT_MASK
- GNB_TT_SHIFT
- GNLD_ACDC
- GNLD_ACG
- GNLD_AVFS
- GNLD_CG
- GNLD_DIDT
- GNLD_DPM_DCEFCLK
- GNLD_DPM_FCLK
- GNLD_DPM_GFXCLK
- GNLD_DPM_LINK
- GNLD_DPM_MAX
- GNLD_DPM_MP0CLK
- GNLD_DPM_PREFETCHER
- GNLD_DPM_SOCCLK
- GNLD_DPM_UCLK
- GNLD_DPM_UVD
- GNLD_DPM_VCE
- GNLD_DS_DCEFCLK
- GNLD_DS_FCLK
- GNLD_DS_GFXCLK
- GNLD_DS_LCLK
- GNLD_DS_MP0CLK
- GNLD_DS_MP1CLK
- GNLD_DS_SOCCLK
- GNLD_ECC
- GNLD_FAN_CONTROL
- GNLD_FEATURES_MAX
- GNLD_FEATURE_FAST_PPT_BIT
- GNLD_FW_CTF
- GNLD_GFXOFF
- GNLD_GFX_PER_CU_CG
- GNLD_LED_DISPLAY
- GNLD_PCC_LIMIT
- GNLD_PPT
- GNLD_RM
- GNLD_TDC
- GNLD_THERMAL
- GNLD_ULV
- GNLD_VR0HOT
- GNLD_VR1HOT
- GNLD_XGMI
- GNN_FT_CMD
- GNN_FT_REQ_SIZE
- GNN_ID_CMD
- GNN_ID_REQ_SIZE
- GNN_ID_RSP_SIZE
- GNN_ID_SNS_CMD_SIZE
- GNN_ID_SNS_DATA_SIZE
- GNN_ID_SNS_SCMD_LEN
- GNPTXFSIZ
- GNPTXSTS
- GNPTXSTS_NP_TXF_SPC_AVAIL_GET
- GNPTXSTS_NP_TXF_SPC_AVAIL_MASK
- GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT
- GNPTXSTS_NP_TXQ_SPC_AVAIL_GET
- GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK
- GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT
- GNPTXSTS_NP_TXQ_TOP_MASK
- GNPTXSTS_NP_TXQ_TOP_SHIFT
- GNRLMSGFLGS_DOM
- GNRLMSGFLGS_HOLDMSG
- GNRLMSGFLGS_SNDALRM
- GNRL_CTL
- GNSS_FLAG_HAS_WRITE_RAW
- GNSS_MINORS
- GNSS_READ_FIFO_SIZE
- GNSS_SERIAL_ACTIVE
- GNSS_SERIAL_OFF
- GNSS_SERIAL_STANDBY
- GNSS_TYPE_COUNT
- GNSS_TYPE_MTK
- GNSS_TYPE_NMEA
- GNSS_TYPE_SIRF
- GNSS_TYPE_UBX
- GNSS_WRITE_BUF_SIZE
- GNT0_GNTIN_MARK
- GNT1_MARK
- GNT2_MARK
- GNT3_MARK
- GNTALLOC_FLAG_WRITABLE
- GNTCOPY_dest_gref
- GNTCOPY_source_gref
- GNTDEV_COPY_BATCH
- GNTDEV_DMA_FLAG_COHERENT
- GNTDEV_DMA_FLAG_WC
- GNTMAP_application_map
- GNTMAP_contains_pte
- GNTMAP_device_map
- GNTMAP_guest_avail_mask
- GNTMAP_host_map
- GNTMAP_readonly
- GNTST_address_too_big
- GNTST_bad_copy_arg
- GNTST_bad_dev_addr
- GNTST_bad_domain
- GNTST_bad_gntref
- GNTST_bad_handle
- GNTST_bad_page
- GNTST_bad_virt_addr
- GNTST_eagain
- GNTST_general_error
- GNTST_no_device_space
- GNTST_okay
- GNTST_permission_denied
- GNTTABOP_cache_flush
- GNTTABOP_copy
- GNTTABOP_dump_table
- GNTTABOP_error_msgs
- GNTTABOP_get_status_frames
- GNTTABOP_get_version
- GNTTABOP_map_grant_ref
- GNTTABOP_query_size
- GNTTABOP_set_version
- GNTTABOP_setup_table
- GNTTABOP_transfer
- GNTTABOP_unmap_and_replace
- GNTTABOP_unmap_grant_ref
- GNTTAB_CACHE_CLEAN
- GNTTAB_CACHE_INVAL
- GNTTAB_CACHE_SOURCE_GREF
- GNTTAB_LIST_END
- GNTTAB_RESERVED_XENSTORE
- GNTTAB_UNMAP_REFS_DELAY
- GN_CHIP_ID
- GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA_MASK
- GN_FORCE_NBPS1__GN_FORCE_NBPS1_DATA__SHIFT
- GN_GNB_SLOW__GN_GNB_SLOW_DATA_MASK
- GN_GNB_SLOW__GN_GNB_SLOW_DATA__SHIFT
- GN_OTOMETRICS_VID
- GO
- GO7007_AUDIO_BCLK_POLAR
- GO7007_AUDIO_I2S_MASTER
- GO7007_AUDIO_I2S_MODE_1
- GO7007_AUDIO_I2S_MODE_2
- GO7007_AUDIO_I2S_MODE_3
- GO7007_AUDIO_OKI_MODE
- GO7007_AUDIO_ONE_CHANNEL
- GO7007_AUDIO_WORD_14
- GO7007_AUDIO_WORD_16
- GO7007_BOARDID_ADLINK_MPG24
- GO7007_BOARDID_ADS_USBAV_709
- GO7007_BOARDID_ENDURA
- GO7007_BOARDID_LIFEVIEW_LR192
- GO7007_BOARDID_MATRIX_II
- GO7007_BOARDID_MATRIX_RELOAD
- GO7007_BOARDID_MATRIX_REV
- GO7007_BOARDID_PCI_VOYAGER
- GO7007_BOARDID_PX_M402U
- GO7007_BOARDID_PX_TV402U
- GO7007_BOARDID_SENSORAY_2250
- GO7007_BOARDID_STAR_TREK
- GO7007_BOARDID_XMEN
- GO7007_BOARDID_XMEN_II
- GO7007_BOARDID_XMEN_III
- GO7007_BOARD_HAS_AUDIO
- GO7007_BOARD_HAS_TUNER
- GO7007_BOARD_USE_ONBOARD_I2C
- GO7007_BUF_PAGES
- GO7007_BUF_SIZE
- GO7007_CID_CUSTOM_BASE
- GO7007_FW_NAME
- GO7007_RATIO_16_9
- GO7007_RATIO_1_1
- GO7007_RATIO_4_3
- GO7007_SENSOR_656
- GO7007_SENSOR_BIT_WIDTH
- GO7007_SENSOR_CONFIG_MASK
- GO7007_SENSOR_FIELD_ID_POLAR
- GO7007_SENSOR_HREF_POLAR
- GO7007_SENSOR_SAA7115
- GO7007_SENSOR_SCALING
- GO7007_SENSOR_TV
- GO7007_SENSOR_VALID_ENABLE
- GO7007_SENSOR_VALID_POLAR
- GO7007_SENSOR_VBI
- GO7007_SENSOR_VREF_POLAR
- GO7007_STD_NTSC
- GO7007_STD_OTHER
- GO7007_STD_PAL
- GO7007_USB_EZUSB
- GO7007_USB_EZUSB_I2C
- GOA_BICLK1
- GOA_BICLK2
- GOA_BICLK3
- GOA_BICLK4
- GOA_BICLK_OPT1
- GOA_BICLK_OPT2
- GOA_VCLK1
- GOA_VCLK2
- GOA_VCLK_OPT1
- GOA_VSTV1
- GOA_VSTV2
- GOFF
- GOF_PER_SEC
- GOHUBS_PID
- GOHUBS_VID
- GOING_DISKLESS
- GOING_OFFLINE
- GOLDEN_RATIO_32
- GOLDEN_RATIO_64
- GOLDEN_RATIO_PRIME
- GOLDEN_RATIO_PRIME_32
- GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK
- GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT
- GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK
- GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT
- GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK
- GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT
- GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK
- GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT
- GOLDFISH_BATTERY_READ
- GOLDFISH_BATTERY_WRITE
- GOLDFISH_MMC_READ
- GOLDFISH_MMC_WRITE
- GOLDFISH_PDEV_BUS_BASE
- GOLDFISH_PDEV_BUS_END
- GOLDFISH_PDEV_BUS_IRQ
- GOLDFISH_PIPE_QEMU_H
- GOLDFISH_TIMER_HIGH
- GOLDFISH_TIMER_LOW
- GOLDFISH_TTY_BASE
- GOLDFISH_TTY_CMD_INT_DISABLE
- GOLDFISH_TTY_CMD_INT_ENABLE
- GOLDFISH_TTY_CMD_READ_BUFFER
- GOLDFISH_TTY_CMD_WRITE_BUFFER
- GOLDFISH_TTY_REG_BYTES_READY
- GOLDFISH_TTY_REG_CMD
- GOLDFISH_TTY_REG_DATA_LEN
- GOLDFISH_TTY_REG_DATA_PTR
- GOLDFISH_TTY_REG_DATA_PTR_HIGH
- GOLDFISH_TTY_REG_VERSION
- GOLDSTAR_CDROM_MAJOR
- GOOD
- GOODCOPY_LEN
- GOODCOREADDR
- GOODIX_BUFFER_STATUS_READY
- GOODIX_BUFFER_STATUS_TIMEOUT
- GOODIX_CMD_SCREEN_OFF
- GOODIX_CONFIG_911_LENGTH
- GOODIX_CONFIG_967_LENGTH
- GOODIX_CONFIG_MAX_LENGTH
- GOODIX_CONTACT_SIZE
- GOODIX_GPIO_INT_NAME
- GOODIX_GPIO_RST_NAME
- GOODIX_GT1X_REG_CONFIG_DATA
- GOODIX_GT9X_REG_CONFIG_DATA
- GOODIX_INT_TRIGGER
- GOODIX_MAX_CONTACTS
- GOODIX_MAX_CONTACT_SIZE
- GOODIX_MAX_HEIGHT
- GOODIX_MAX_WIDTH
- GOODIX_READ_COOR_ADDR
- GOODIX_REG_COMMAND
- GOODIX_REG_ID
- GOOD_COPY_LEN
- GOOD_DMA_DRIVE
- GOOD_FCS
- GOOD_FRAME
- GOOD_LINEAR
- GOOD_ME_REG
- GOOD_PACKET_LEN
- GOOD_STACK
- GOOD_STATE
- GOOGLE_IDS
- GOP_LIB1_CONTENT
- GOP_SIZE
- GOP_VBIOS_CONTENT
- GOSSIP_ACL_DEBUG
- GOSSIP_BUFMAP_DEBUG
- GOSSIP_CACHE_DEBUG
- GOSSIP_DCACHE_DEBUG
- GOSSIP_DEBUGFS_DEBUG
- GOSSIP_DEV_DEBUG
- GOSSIP_DIR_DEBUG
- GOSSIP_FILE_DEBUG
- GOSSIP_INIT_DEBUG
- GOSSIP_INODE_DEBUG
- GOSSIP_MAX_DEBUG
- GOSSIP_MAX_NR
- GOSSIP_NAME_DEBUG
- GOSSIP_NO_DEBUG
- GOSSIP_SUPER_DEBUG
- GOSSIP_SYSFS_DEBUG
- GOSSIP_UTILS_DEBUG
- GOSSIP_WAIT_DEBUG
- GOSSIP_XATTR_DEBUG
- GOTGCTL
- GOTGCTL_ASESVLD
- GOTGCTL_BSESVLD
- GOTGCTL_CHIRPEN
- GOTGCTL_CONID_B
- GOTGCTL_DBNCE_FLTR_BYPASS
- GOTGCTL_DBNC_SHORT
- GOTGCTL_DEVHNPEN
- GOTGCTL_HNPREQ
- GOTGCTL_HSTNEGSCS
- GOTGCTL_HSTSETHNPEN
- GOTGCTL_MULT_VALID_BC_MASK
- GOTGCTL_MULT_VALID_BC_SHIFT
- GOTGCTL_OTGVER
- GOTGCTL_SESREQ
- GOTGCTL_SESREQSCS
- GOTGINT
- GOTGINT_A_DEV_TOUT_CHG
- GOTGINT_DBNCE_DONE
- GOTGINT_HST_NEG_DET
- GOTGINT_HST_NEG_SUC_STS_CHNG
- GOTGINT_SES_END_DET
- GOTGINT_SES_REQ_SUC_STS_CHNG
- GOTO
- GOTO_DONE
- GOTO_ERROR_ON
- GOTO_PREVIOUS_ITEM
- GOTVIEW_SAT_HD
- GOT_PING_ACK
- GOV_TLED
- GOYAP_H_
- GOYA_ASYNC_EVENT_ID_AXI_ECC
- GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER
- GOYA_ASYNC_EVENT_ID_CPU_BMON
- GOYA_ASYNC_EVENT_ID_CPU_IF_ECC
- GOYA_ASYNC_EVENT_ID_DDR0_AXI_RD
- GOYA_ASYNC_EVENT_ID_DDR0_AXI_WR
- GOYA_ASYNC_EVENT_ID_DDR0_DB_ECC
- GOYA_ASYNC_EVENT_ID_DDR0_ECC_SCRUB
- GOYA_ASYNC_EVENT_ID_DDR0_PARITY
- GOYA_ASYNC_EVENT_ID_DDR0_PHY_DFI
- GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC
- GOYA_ASYNC_EVENT_ID_DDR0_SB_ECC_MC
- GOYA_ASYNC_EVENT_ID_DDR1_AXI_RD
- GOYA_ASYNC_EVENT_ID_DDR1_AXI_WR
- GOYA_ASYNC_EVENT_ID_DDR1_DB_ECC
- GOYA_ASYNC_EVENT_ID_DDR1_ECC_SCRUB
- GOYA_ASYNC_EVENT_ID_DDR1_PARITY
- GOYA_ASYNC_EVENT_ID_DDR1_PHY_DFI
- GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC
- GOYA_ASYNC_EVENT_ID_DDR1_SB_ECC_MC
- GOYA_ASYNC_EVENT_ID_DMA0_CH
- GOYA_ASYNC_EVENT_ID_DMA0_QM
- GOYA_ASYNC_EVENT_ID_DMA1_CH
- GOYA_ASYNC_EVENT_ID_DMA1_QM
- GOYA_ASYNC_EVENT_ID_DMA2_CH
- GOYA_ASYNC_EVENT_ID_DMA2_QM
- GOYA_ASYNC_EVENT_ID_DMA3_CH
- GOYA_ASYNC_EVENT_ID_DMA3_QM
- GOYA_ASYNC_EVENT_ID_DMA4_CH
- GOYA_ASYNC_EVENT_ID_DMA4_QM
- GOYA_ASYNC_EVENT_ID_DMA_BM_CH0
- GOYA_ASYNC_EVENT_ID_DMA_BM_CH1
- GOYA_ASYNC_EVENT_ID_DMA_BM_CH2
- GOYA_ASYNC_EVENT_ID_DMA_BM_CH3
- GOYA_ASYNC_EVENT_ID_DMA_BM_CH4
- GOYA_ASYNC_EVENT_ID_DMA_ECC
- GOYA_ASYNC_EVENT_ID_DMA_MACRO
- GOYA_ASYNC_EVENT_ID_DMA_ON_HBW
- GOYA_ASYNC_EVENT_ID_FAN
- GOYA_ASYNC_EVENT_ID_GIC500
- GOYA_ASYNC_EVENT_ID_HALT_MACHINE
- GOYA_ASYNC_EVENT_ID_INTS_REGISTER
- GOYA_ASYNC_EVENT_ID_L2_RAM_ECC
- GOYA_ASYNC_EVENT_ID_LAST_VALID_ID
- GOYA_ASYNC_EVENT_ID_MME_CMDQ
- GOYA_ASYNC_EVENT_ID_MME_ECC
- GOYA_ASYNC_EVENT_ID_MME_ECC_EXT
- GOYA_ASYNC_EVENT_ID_MME_QM
- GOYA_ASYNC_EVENT_ID_MME_WACS
- GOYA_ASYNC_EVENT_ID_MME_WACSD
- GOYA_ASYNC_EVENT_ID_MME_WACS_DOWN
- GOYA_ASYNC_EVENT_ID_MME_WACS_UP
- GOYA_ASYNC_EVENT_ID_MMU_DBG_BM
- GOYA_ASYNC_EVENT_ID_MMU_ECC
- GOYA_ASYNC_EVENT_ID_MMU_PAGE_FAULT
- GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU0
- GOYA_ASYNC_EVENT_ID_MMU_SBA_SPMU1
- GOYA_ASYNC_EVENT_ID_MMU_WR_PERM
- GOYA_ASYNC_EVENT_ID_PCIE_APB
- GOYA_ASYNC_EVENT_ID_PCIE_BM_D_P_WR
- GOYA_ASYNC_EVENT_ID_PCIE_BM_D_RD
- GOYA_ASYNC_EVENT_ID_PCIE_BM_U_P_WR
- GOYA_ASYNC_EVENT_ID_PCIE_BM_U_RD
- GOYA_ASYNC_EVENT_ID_PCIE_CORE
- GOYA_ASYNC_EVENT_ID_PCIE_DEC
- GOYA_ASYNC_EVENT_ID_PCIE_FLR
- GOYA_ASYNC_EVENT_ID_PCIE_HOT_RESET
- GOYA_ASYNC_EVENT_ID_PCIE_IF
- GOYA_ASYNC_EVENT_ID_PCIE_PERST
- GOYA_ASYNC_EVENT_ID_PCIE_PHY
- GOYA_ASYNC_EVENT_ID_PCIE_QDB
- GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG0
- GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG1
- GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG2
- GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG3
- GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG0
- GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG1
- GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG2
- GOYA_ASYNC_EVENT_ID_PCIE_QID1_ENG3
- GOYA_ASYNC_EVENT_ID_PI_UPDATE
- GOYA_ASYNC_EVENT_ID_PLL0
- GOYA_ASYNC_EVENT_ID_PLL1
- GOYA_ASYNC_EVENT_ID_PLL2
- GOYA_ASYNC_EVENT_ID_PLL3
- GOYA_ASYNC_EVENT_ID_PLL4
- GOYA_ASYNC_EVENT_ID_PLL5
- GOYA_ASYNC_EVENT_ID_PLL6
- GOYA_ASYNC_EVENT_ID_PSOC
- GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC
- GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_0
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_1
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_2
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_3
- GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_4
- GOYA_ASYNC_EVENT_ID_PSOC_MEM
- GOYA_ASYNC_EVENT_ID_SIZE
- GOYA_ASYNC_EVENT_ID_SOFT_RESET
- GOYA_ASYNC_EVENT_ID_SRAM0
- GOYA_ASYNC_EVENT_ID_SRAM1
- GOYA_ASYNC_EVENT_ID_SRAM10
- GOYA_ASYNC_EVENT_ID_SRAM11
- GOYA_ASYNC_EVENT_ID_SRAM12
- GOYA_ASYNC_EVENT_ID_SRAM13
- GOYA_ASYNC_EVENT_ID_SRAM14
- GOYA_ASYNC_EVENT_ID_SRAM15
- GOYA_ASYNC_EVENT_ID_SRAM16
- GOYA_ASYNC_EVENT_ID_SRAM17
- GOYA_ASYNC_EVENT_ID_SRAM18
- GOYA_ASYNC_EVENT_ID_SRAM19
- GOYA_ASYNC_EVENT_ID_SRAM2
- GOYA_ASYNC_EVENT_ID_SRAM20
- GOYA_ASYNC_EVENT_ID_SRAM21
- GOYA_ASYNC_EVENT_ID_SRAM22
- GOYA_ASYNC_EVENT_ID_SRAM23
- GOYA_ASYNC_EVENT_ID_SRAM24
- GOYA_ASYNC_EVENT_ID_SRAM25
- GOYA_ASYNC_EVENT_ID_SRAM26
- GOYA_ASYNC_EVENT_ID_SRAM27
- GOYA_ASYNC_EVENT_ID_SRAM28
- GOYA_ASYNC_EVENT_ID_SRAM29
- GOYA_ASYNC_EVENT_ID_SRAM3
- GOYA_ASYNC_EVENT_ID_SRAM4
- GOYA_ASYNC_EVENT_ID_SRAM5
- GOYA_ASYNC_EVENT_ID_SRAM6
- GOYA_ASYNC_EVENT_ID_SRAM7
- GOYA_ASYNC_EVENT_ID_SRAM8
- GOYA_ASYNC_EVENT_ID_SRAM9
- GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC0_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC0_DEC
- GOYA_ASYNC_EVENT_ID_TPC0_ECC
- GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC0_QM
- GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC1_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC1_DEC
- GOYA_ASYNC_EVENT_ID_TPC1_ECC
- GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC1_QM
- GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC2_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC2_DEC
- GOYA_ASYNC_EVENT_ID_TPC2_ECC
- GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC2_QM
- GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC3_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC3_DEC
- GOYA_ASYNC_EVENT_ID_TPC3_ECC
- GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC3_QM
- GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC4_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC4_DEC
- GOYA_ASYNC_EVENT_ID_TPC4_ECC
- GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC4_QM
- GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC5_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC5_DEC
- GOYA_ASYNC_EVENT_ID_TPC5_ECC
- GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC5_QM
- GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC6_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC6_DEC
- GOYA_ASYNC_EVENT_ID_TPC6_ECC
- GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC6_QM
- GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU
- GOYA_ASYNC_EVENT_ID_TPC7_CMDQ
- GOYA_ASYNC_EVENT_ID_TPC7_DEC
- GOYA_ASYNC_EVENT_ID_TPC7_ECC
- GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR
- GOYA_ASYNC_EVENT_ID_TPC7_QM
- GOYA_ASYNC_EVENT_ID_TS_EAST
- GOYA_ASYNC_EVENT_ID_TS_NORTH
- GOYA_ASYNC_EVENT_ID_TS_WEST
- GOYA_BLOCKS_H_
- GOYA_BMON_CPU_RD
- GOYA_BMON_CPU_WR
- GOYA_BMON_DMA_CH_0_0
- GOYA_BMON_DMA_CH_0_1
- GOYA_BMON_DMA_CH_1_0
- GOYA_BMON_DMA_CH_1_1
- GOYA_BMON_DMA_CH_2_0
- GOYA_BMON_DMA_CH_2_1
- GOYA_BMON_DMA_CH_3_0
- GOYA_BMON_DMA_CH_3_1
- GOYA_BMON_DMA_CH_4_0
- GOYA_BMON_DMA_CH_4_1
- GOYA_BMON_DMA_MACRO_0
- GOYA_BMON_DMA_MACRO_1
- GOYA_BMON_DMA_MACRO_2
- GOYA_BMON_DMA_MACRO_3
- GOYA_BMON_DMA_MACRO_4
- GOYA_BMON_DMA_MACRO_5
- GOYA_BMON_DMA_MACRO_6
- GOYA_BMON_DMA_MACRO_7
- GOYA_BMON_FIRST
- GOYA_BMON_LAST
- GOYA_BMON_MME1_SBA_0
- GOYA_BMON_MME1_SBA_1
- GOYA_BMON_MME3_SBB_0
- GOYA_BMON_MME3_SBB_1
- GOYA_BMON_MME4_WACS2_0
- GOYA_BMON_MME4_WACS2_1
- GOYA_BMON_MME4_WACS2_2
- GOYA_BMON_MME4_WACS_0
- GOYA_BMON_MME4_WACS_1
- GOYA_BMON_MME4_WACS_2
- GOYA_BMON_MME4_WACS_3
- GOYA_BMON_MME4_WACS_4
- GOYA_BMON_MME4_WACS_5
- GOYA_BMON_MME4_WACS_6
- GOYA_BMON_MMU_0
- GOYA_BMON_MMU_1
- GOYA_BMON_PCIE_MSTR_RD
- GOYA_BMON_PCIE_MSTR_WR
- GOYA_BMON_PCIE_SLV_RD
- GOYA_BMON_PCIE_SLV_WR
- GOYA_BMON_TPC0_EML_0
- GOYA_BMON_TPC0_EML_1
- GOYA_BMON_TPC0_EML_2
- GOYA_BMON_TPC0_EML_3
- GOYA_BMON_TPC1_EML_0
- GOYA_BMON_TPC1_EML_1
- GOYA_BMON_TPC1_EML_2
- GOYA_BMON_TPC1_EML_3
- GOYA_BMON_TPC2_EML_0
- GOYA_BMON_TPC2_EML_1
- GOYA_BMON_TPC2_EML_2
- GOYA_BMON_TPC2_EML_3
- GOYA_BMON_TPC3_EML_0
- GOYA_BMON_TPC3_EML_1
- GOYA_BMON_TPC3_EML_2
- GOYA_BMON_TPC3_EML_3
- GOYA_BMON_TPC4_EML_0
- GOYA_BMON_TPC4_EML_1
- GOYA_BMON_TPC4_EML_2
- GOYA_BMON_TPC4_EML_3
- GOYA_BMON_TPC5_EML_0
- GOYA_BMON_TPC5_EML_1
- GOYA_BMON_TPC5_EML_2
- GOYA_BMON_TPC5_EML_3
- GOYA_BMON_TPC6_EML_0
- GOYA_BMON_TPC6_EML_1
- GOYA_BMON_TPC6_EML_2
- GOYA_BMON_TPC6_EML_3
- GOYA_BMON_TPC7_EML_0
- GOYA_BMON_TPC7_EML_1
- GOYA_BMON_TPC7_EML_2
- GOYA_BMON_TPC7_EML_3
- GOYA_CB_POOL_CB_CNT
- GOYA_CB_POOL_CB_SIZE
- GOYA_CORESIGHT_H
- GOYA_CPU_RESET_WAIT_MSEC
- GOYA_CPU_TIMEOUT_USEC
- GOYA_DEFAULT_CARD_NAME
- GOYA_DMA_POOL_BLK_SIZE
- GOYA_ENGINE_ID_DMA_0
- GOYA_ENGINE_ID_DMA_1
- GOYA_ENGINE_ID_DMA_2
- GOYA_ENGINE_ID_DMA_3
- GOYA_ENGINE_ID_DMA_4
- GOYA_ENGINE_ID_MME_0
- GOYA_ENGINE_ID_SIZE
- GOYA_ENGINE_ID_TPC_0
- GOYA_ENGINE_ID_TPC_1
- GOYA_ENGINE_ID_TPC_2
- GOYA_ENGINE_ID_TPC_3
- GOYA_ENGINE_ID_TPC_4
- GOYA_ENGINE_ID_TPC_5
- GOYA_ENGINE_ID_TPC_6
- GOYA_ENGINE_ID_TPC_7
- GOYA_ETF_CPU_0
- GOYA_ETF_CPU_1
- GOYA_ETF_CPU_TRACE
- GOYA_ETF_DMA_CH_0_CS
- GOYA_ETF_DMA_CH_1_CS
- GOYA_ETF_DMA_CH_2_CS
- GOYA_ETF_DMA_CH_3_CS
- GOYA_ETF_DMA_CH_4_CS
- GOYA_ETF_DMA_MACRO_CS
- GOYA_ETF_FIRST
- GOYA_ETF_LAST
- GOYA_ETF_MME1_SBA
- GOYA_ETF_MME3_SBB
- GOYA_ETF_MME4_WACS
- GOYA_ETF_MME4_WACS2
- GOYA_ETF_MMU_CS
- GOYA_ETF_PCIE
- GOYA_ETF_PSOC
- GOYA_ETF_TPC0_EML
- GOYA_ETF_TPC1_EML
- GOYA_ETF_TPC2_EML
- GOYA_ETF_TPC3_EML
- GOYA_ETF_TPC4_EML
- GOYA_ETF_TPC5_EML
- GOYA_ETF_TPC6_EML
- GOYA_ETF_TPC7_EML
- GOYA_EVENT_QUEUE_MSIX_IDX
- GOYA_FUNNEL_CPU
- GOYA_FUNNEL_DMA_CH_6_1
- GOYA_FUNNEL_DMA_MACRO_3_1
- GOYA_FUNNEL_FIRST
- GOYA_FUNNEL_LAST
- GOYA_FUNNEL_MME0_RTR
- GOYA_FUNNEL_MME1_RTR
- GOYA_FUNNEL_MME2_RTR
- GOYA_FUNNEL_MME3_RTR
- GOYA_FUNNEL_MME4_RTR
- GOYA_FUNNEL_MME5_RTR
- GOYA_FUNNEL_PCIE
- GOYA_FUNNEL_PSOC
- GOYA_FUNNEL_TPC0_EML
- GOYA_FUNNEL_TPC1_EML
- GOYA_FUNNEL_TPC1_RTR
- GOYA_FUNNEL_TPC2_EML
- GOYA_FUNNEL_TPC2_RTR
- GOYA_FUNNEL_TPC3_EML
- GOYA_FUNNEL_TPC3_RTR
- GOYA_FUNNEL_TPC4_EML
- GOYA_FUNNEL_TPC4_RTR
- GOYA_FUNNEL_TPC5_EML
- GOYA_FUNNEL_TPC5_RTR
- GOYA_FUNNEL_TPC6_EML
- GOYA_FUNNEL_TPC6_RTR
- GOYA_FUNNEL_TPC7_EML
- GOYA_FW_IF_H
- GOYA_H
- GOYA_IRQ_HBW_AGENT_ID_MASK
- GOYA_IRQ_HBW_AGENT_ID_SHIFT
- GOYA_IRQ_HBW_ID_MASK
- GOYA_IRQ_HBW_ID_SHIFT
- GOYA_IRQ_HBW_INTERNAL_ID_MASK
- GOYA_IRQ_HBW_INTERNAL_ID_SHIFT
- GOYA_IRQ_HBW_X_MASK
- GOYA_IRQ_HBW_X_SHIFT
- GOYA_IRQ_HBW_Y_MASK
- GOYA_IRQ_HBW_Y_SHIFT
- GOYA_IRQ_LBW_AGENT_ID_MASK
- GOYA_IRQ_LBW_AGENT_ID_SHIFT
- GOYA_IRQ_LBW_ID_MASK
- GOYA_IRQ_LBW_ID_SHIFT
- GOYA_IRQ_LBW_INTERNAL_ID_MASK
- GOYA_IRQ_LBW_INTERNAL_ID_SHIFT
- GOYA_IRQ_LBW_X_MASK
- GOYA_IRQ_LBW_X_SHIFT
- GOYA_IRQ_LBW_Y_MASK
- GOYA_IRQ_LBW_Y_SHIFT
- GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
- GOYA_MAX_STRING_LEN
- GOYA_MMU_REGS_NUM
- GOYA_MSIX_ENTRIES
- GOYA_PACKETS_H
- GOYA_PKT_CTL_EB_MASK
- GOYA_PKT_CTL_EB_SHIFT
- GOYA_PKT_CTL_MB_MASK
- GOYA_PKT_CTL_MB_SHIFT
- GOYA_PKT_CTL_OPCODE_MASK
- GOYA_PKT_CTL_OPCODE_SHIFT
- GOYA_PKT_CTL_RB_MASK
- GOYA_PKT_CTL_RB_SHIFT
- GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK
- GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT
- GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK
- GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT
- GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK
- GOYA_PKT_LIN_DMA_CTL_RDCOMP_SHIFT
- GOYA_PKT_LIN_DMA_CTL_WO_MASK
- GOYA_PKT_LIN_DMA_CTL_WO_SHIFT
- GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK
- GOYA_PKT_LIN_DMA_CTL_WRCOMP_SHIFT
- GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK
- GOYA_PKT_WREG32_CTL_REG_OFFSET_SHIFT
- GOYA_PLDM_CORESIGHT_TIMEOUT_USEC
- GOYA_PLDM_MMU_TIMEOUT_USEC
- GOYA_PLDM_QMAN0_TIMEOUT_USEC
- GOYA_PLDM_RESET_TIMEOUT_MSEC
- GOYA_PLDM_RESET_WAIT_MSEC
- GOYA_PLL_FREQ_LOW
- GOYA_QMAN0_FENCE_VAL
- GOYA_QUEUE_ID_CPU_PQ
- GOYA_QUEUE_ID_DMA_0
- GOYA_QUEUE_ID_DMA_1
- GOYA_QUEUE_ID_DMA_2
- GOYA_QUEUE_ID_DMA_3
- GOYA_QUEUE_ID_DMA_4
- GOYA_QUEUE_ID_MME
- GOYA_QUEUE_ID_SIZE
- GOYA_QUEUE_ID_TPC0
- GOYA_QUEUE_ID_TPC1
- GOYA_QUEUE_ID_TPC2
- GOYA_QUEUE_ID_TPC3
- GOYA_QUEUE_ID_TPC4
- GOYA_QUEUE_ID_TPC5
- GOYA_QUEUE_ID_TPC6
- GOYA_QUEUE_ID_TPC7
- GOYA_REG_MAP_H_
- GOYA_RESET_TIMEOUT_MSEC
- GOYA_RESET_WAIT_MSEC
- GOYA_SPMU_DMA_CH_0_CS
- GOYA_SPMU_DMA_CH_1_CS
- GOYA_SPMU_DMA_CH_2_CS
- GOYA_SPMU_DMA_CH_3_CS
- GOYA_SPMU_DMA_CH_4_CS
- GOYA_SPMU_DMA_MACRO_CS
- GOYA_SPMU_FIRST
- GOYA_SPMU_LAST
- GOYA_SPMU_MME1_SBA
- GOYA_SPMU_MME3_SBB
- GOYA_SPMU_MME4_WACS
- GOYA_SPMU_MME4_WACS2
- GOYA_SPMU_MMU_CS
- GOYA_SPMU_PCIE
- GOYA_SPMU_TPC0_EML
- GOYA_SPMU_TPC1_EML
- GOYA_SPMU_TPC2_EML
- GOYA_SPMU_TPC3_EML
- GOYA_SPMU_TPC4_EML
- GOYA_SPMU_TPC5_EML
- GOYA_SPMU_TPC6_EML
- GOYA_SPMU_TPC7_EML
- GOYA_STM_CPU
- GOYA_STM_DMA_CH_0_CS
- GOYA_STM_DMA_CH_1_CS
- GOYA_STM_DMA_CH_2_CS
- GOYA_STM_DMA_CH_3_CS
- GOYA_STM_DMA_CH_4_CS
- GOYA_STM_DMA_MACRO_CS
- GOYA_STM_FIRST
- GOYA_STM_LAST
- GOYA_STM_MME1_SBA
- GOYA_STM_MME3_SBB
- GOYA_STM_MME4_WACS
- GOYA_STM_MME4_WACS2
- GOYA_STM_MMU_CS
- GOYA_STM_PCIE
- GOYA_STM_PSOC
- GOYA_STM_TPC0_EML
- GOYA_STM_TPC1_EML
- GOYA_STM_TPC2_EML
- GOYA_STM_TPC3_EML
- GOYA_STM_TPC4_EML
- GOYA_STM_TPC5_EML
- GOYA_STM_TPC6_EML
- GOYA_STM_TPC7_EML
- GOYA_TEST_QUEUE_WAIT_USEC
- GO_BIT_TIMEOUT
- GO_BIT_TIMEOUT_MSECS
- GO_CHIP_ID
- GO_DISKLESS
- GO_IDLE_STATE
- GO_INACTIVE_STATE
- GO_INTENT_ATTR_ID
- GO_NEG_CONF
- GO_NEG_REQ
- GO_NEG_RSP
- GO_SHIFT
- GO_STATE
- GO_STORE
- GP
- GP0
- GP0_CLK
- GP0_DATA
- GP0_IO
- GP0_OUT_ENABLE
- GP0_SRC
- GP1
- GP100
- GP100_DISP
- GP100_DISP_CORE_CHANNEL_DMA
- GP100_VMM_VN_FAULT_CANCEL
- GP100_VMM_VN_FAULT_REPLAY
- GP102_DISP
- GP102_DISP_CORE_CHANNEL_DMA
- GP1_CLK
- GP1_CLK_SRC
- GP1_DATA
- GP1_IO_BASE
- GP1_OUT_ENABLE
- GP1_SRC
- GP2
- GP2AP020A00F_ADD_MODE
- GP2AP020A00F_ALC_MASK
- GP2AP020A00F_ALC_OFF
- GP2AP020A00F_ALC_ON
- GP2AP020A00F_ALS_REG
- GP2AP020A00F_CHAN_TIMESTAMP
- GP2AP020A00F_CMD_ALS_HIGH_EV_DIS
- GP2AP020A00F_CMD_ALS_HIGH_EV_EN
- GP2AP020A00F_CMD_ALS_LOW_EV_DIS
- GP2AP020A00F_CMD_ALS_LOW_EV_EN
- GP2AP020A00F_CMD_PROX_HIGH_EV_DIS
- GP2AP020A00F_CMD_PROX_HIGH_EV_EN
- GP2AP020A00F_CMD_PROX_LOW_EV_DIS
- GP2AP020A00F_CMD_PROX_LOW_EV_EN
- GP2AP020A00F_CMD_READ_RAW_CLEAR
- GP2AP020A00F_CMD_READ_RAW_IR
- GP2AP020A00F_CMD_READ_RAW_PROXIMITY
- GP2AP020A00F_CMD_TRIGGER_CLEAR_DIS
- GP2AP020A00F_CMD_TRIGGER_CLEAR_EN
- GP2AP020A00F_CMD_TRIGGER_IR_DIS
- GP2AP020A00F_CMD_TRIGGER_IR_EN
- GP2AP020A00F_CMD_TRIGGER_PROX_DIS
- GP2AP020A00F_CMD_TRIGGER_PROX_EN
- GP2AP020A00F_D0_H_REG
- GP2AP020A00F_D0_L_REG
- GP2AP020A00F_D1_H_REG
- GP2AP020A00F_D1_L_REG
- GP2AP020A00F_D2_H_REG
- GP2AP020A00F_D2_L_REG
- GP2AP020A00F_DATA_READY_TIMEOUT
- GP2AP020A00F_DATA_REG
- GP2AP020A00F_FLAG_A
- GP2AP020A00F_FLAG_ALS_CLEAR_TRIGGER
- GP2AP020A00F_FLAG_ALS_FALLING_EV
- GP2AP020A00F_FLAG_ALS_IR_TRIGGER
- GP2AP020A00F_FLAG_ALS_RISING_EV
- GP2AP020A00F_FLAG_DATA_READY
- GP2AP020A00F_FLAG_LUX_MODE_HI
- GP2AP020A00F_FLAG_P
- GP2AP020A00F_FLAG_PROX_FALLING_EV
- GP2AP020A00F_FLAG_PROX_RISING_EV
- GP2AP020A00F_FLAG_PROX_TRIGGER
- GP2AP020A00F_FREQ_327_5kHz
- GP2AP020A00F_FREQ_81_8kHz
- GP2AP020A00F_FREQ_MASK
- GP2AP020A00F_INTTYPE_LEVEL
- GP2AP020A00F_INTTYPE_MASK
- GP2AP020A00F_INTTYPE_PULSE
- GP2AP020A00F_INTVAL_0
- GP2AP020A00F_INTVAL_16
- GP2AP020A00F_INTVAL_4
- GP2AP020A00F_INTVAL_8
- GP2AP020A00F_INTVAL_MASK
- GP2AP020A00F_IS_110mA
- GP2AP020A00F_IS_13_8mA
- GP2AP020A00F_IS_27_5mA
- GP2AP020A00F_IS_55mA
- GP2AP020A00F_IS_MASK
- GP2AP020A00F_LED_REG
- GP2AP020A00F_MAX_CHANNELS
- GP2AP020A00F_NUM_OPMODES
- GP2AP020A00F_NUM_REGS
- GP2AP020A00F_OP2_AUTO_SHUTDOWN
- GP2AP020A00F_OP2_CONT_OPERATION
- GP2AP020A00F_OP2_MASK
- GP2AP020A00F_OP3_MASK
- GP2AP020A00F_OP3_OPERATION
- GP2AP020A00F_OP3_SHUTDOWN
- GP2AP020A00F_OPMODE_ALS
- GP2AP020A00F_OPMODE_ALS_AND_PS
- GP2AP020A00F_OPMODE_PROX_DETECT
- GP2AP020A00F_OPMODE_PS
- GP2AP020A00F_OPMODE_READ_RAW_CLEAR
- GP2AP020A00F_OPMODE_READ_RAW_IR
- GP2AP020A00F_OPMODE_READ_RAW_PROXIMITY
- GP2AP020A00F_OPMODE_SHUTDOWN
- GP2AP020A00F_OP_ALS
- GP2AP020A00F_OP_ALS_AND_PS
- GP2AP020A00F_OP_DEBUG
- GP2AP020A00F_OP_MASK
- GP2AP020A00F_OP_PS
- GP2AP020A00F_OP_REG
- GP2AP020A00F_PH_H_REG
- GP2AP020A00F_PH_L_REG
- GP2AP020A00F_PIN_ALS
- GP2AP020A00F_PIN_ALS_OR_PS
- GP2AP020A00F_PIN_MASK
- GP2AP020A00F_PIN_PS
- GP2AP020A00F_PIN_PS_DETECT
- GP2AP020A00F_PL_H_REG
- GP2AP020A00F_PL_L_REG
- GP2AP020A00F_PROX_DETECT
- GP2AP020A00F_PROX_MASK
- GP2AP020A00F_PROX_NON_DETECT
- GP2AP020A00F_PRST_16_CYCLES
- GP2AP020A00F_PRST_4_CYCLES
- GP2AP020A00F_PRST_8_CYCLES
- GP2AP020A00F_PRST_MASK
- GP2AP020A00F_PRST_ONCE
- GP2AP020A00F_PS_REG
- GP2AP020A00F_RANGE_A_MASK
- GP2AP020A00F_RANGE_A_x1
- GP2AP020A00F_RANGE_A_x128
- GP2AP020A00F_RANGE_A_x16
- GP2AP020A00F_RANGE_A_x2
- GP2AP020A00F_RANGE_A_x32
- GP2AP020A00F_RANGE_A_x4
- GP2AP020A00F_RANGE_A_x64
- GP2AP020A00F_RANGE_A_x8
- GP2AP020A00F_RANGE_P_MASK
- GP2AP020A00F_RANGE_P_x1
- GP2AP020A00F_RANGE_P_x128
- GP2AP020A00F_RANGE_P_x16
- GP2AP020A00F_RANGE_P_x2
- GP2AP020A00F_RANGE_P_x32
- GP2AP020A00F_RANGE_P_x4
- GP2AP020A00F_RANGE_P_x64
- GP2AP020A00F_RANGE_P_x8
- GP2AP020A00F_RES_A_0_39ms
- GP2AP020A00F_RES_A_100ms
- GP2AP020A00F_RES_A_1_56ms
- GP2AP020A00F_RES_A_200ms
- GP2AP020A00F_RES_A_25ms
- GP2AP020A00F_RES_A_400ms
- GP2AP020A00F_RES_A_6_25ms
- GP2AP020A00F_RES_A_800ms
- GP2AP020A00F_RES_A_MASK
- GP2AP020A00F_RES_P_0_39ms_x2
- GP2AP020A00F_RES_P_100ms_x2
- GP2AP020A00F_RES_P_1_56ms_x2
- GP2AP020A00F_RES_P_200ms_x2
- GP2AP020A00F_RES_P_25ms_x2
- GP2AP020A00F_RES_P_400ms_x2
- GP2AP020A00F_RES_P_6_25ms_x2
- GP2AP020A00F_RES_P_800ms_x2
- GP2AP020A00F_RES_P_MASK
- GP2AP020A00F_RST
- GP2AP020A00F_SCAN_MODE_LIGHT_CLEAR
- GP2AP020A00F_SCAN_MODE_LIGHT_IR
- GP2AP020A00F_SCAN_MODE_PROXIMITY
- GP2AP020A00F_SUBTRACT_MODE
- GP2AP020A00F_THRESH_PH
- GP2AP020A00F_THRESH_PL
- GP2AP020A00F_THRESH_REG
- GP2AP020A00F_THRESH_TH
- GP2AP020A00F_THRESH_TL
- GP2AP020A00F_THRESH_VAL_ID
- GP2AP020A00F_TH_H_REG
- GP2AP020A00F_TH_L_REG
- GP2AP020A00F_TL_H_REG
- GP2AP020A00F_TL_L_REG
- GP2AP020A00F_TYPE_AUTO_CALC
- GP2AP020A00F_TYPE_MANUAL_CALC
- GP2AP020A00F_TYPE_MASK
- GP2A_ADDR_CON
- GP2A_ADDR_CYCLE
- GP2A_ADDR_GAIN
- GP2A_ADDR_HYS
- GP2A_ADDR_OPMOD
- GP2A_ADDR_PROX
- GP2A_CTRL_SSD
- GP2A_I2C_NAME
- GP2_CLK
- GP2_CLK_SRC
- GP2_DATA
- GP2_IO_BASE
- GP2_OUT_ENABLE
- GP2_SRC
- GP3
- GP3_CLK_SRC
- GP3_DATA
- GP3_OUT_ENABLE
- GP60
- GP8PSK_FE_H
- GP8PSK_FW_REV1
- GP8PSK_FW_REV2
- GP8PSK_FW_VERS
- GPADC_AUDOSUSPEND_DELAY
- GPADC_BUSY
- GPADL_TYPE_RING_BUFFER
- GPADL_TYPE_SERVER_SAVE_AREA
- GPADL_TYPE_TRANSACTION
- GPAFEN0
- GPAREN0
- GPAT_CMD
- GPBIAS2_GPADC1_SET
- GPBIAS2_GPADC1_UA
- GPC2CLK_OUT
- GPC2CLK_OUT_BYPDIV31
- GPC2CLK_OUT_BYPDIV_SHIFT
- GPC2CLK_OUT_BYPDIV_WIDTH
- GPC2CLK_OUT_INIT_MASK
- GPC2CLK_OUT_INIT_VAL
- GPC2CLK_OUT_SDIV14_INDIV4_MODE
- GPC2CLK_OUT_SDIV14_INDIV4_SHIFT
- GPC2CLK_OUT_SDIV14_INDIV4_WIDTH
- GPC2CLK_OUT_VCODIV1
- GPC2CLK_OUT_VCODIV2
- GPC2CLK_OUT_VCODIV_MASK
- GPC2CLK_OUT_VCODIV_SHIFT
- GPC2CLK_OUT_VCODIV_WIDTH
- GPCFG
- GPCLR0
- GPCMD_BLANK
- GPCMD_CLOSE_TRACK
- GPCMD_FLUSH_CACHE
- GPCMD_FORMAT_UNIT
- GPCMD_GET_CONFIGURATION
- GPCMD_GET_EVENT_STATUS_NOTIFICATION
- GPCMD_GET_MEDIA_STATUS
- GPCMD_GET_PERFORMANCE
- GPCMD_INQUIRY
- GPCMD_LOAD_UNLOAD
- GPCMD_MECHANISM_STATUS
- GPCMD_MODE_SELECT_10
- GPCMD_MODE_SENSE_10
- GPCMD_PAUSE_RESUME
- GPCMD_PLAYAUDIO_TI
- GPCMD_PLAY_AUDIO_10
- GPCMD_PLAY_AUDIO_MSF
- GPCMD_PLAY_AUDIO_TI
- GPCMD_PLAY_CD
- GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL
- GPCMD_READ_10
- GPCMD_READ_12
- GPCMD_READ_BUFFER
- GPCMD_READ_BUFFER_CAPACITY
- GPCMD_READ_CD
- GPCMD_READ_CDVD_CAPACITY
- GPCMD_READ_CD_MSF
- GPCMD_READ_DISC_INFO
- GPCMD_READ_DVD_STRUCTURE
- GPCMD_READ_FORMAT_CAPACITIES
- GPCMD_READ_HEADER
- GPCMD_READ_SUBCHANNEL
- GPCMD_READ_TOC_PMA_ATIP
- GPCMD_READ_TRACK_RZONE_INFO
- GPCMD_REPAIR_RZONE_TRACK
- GPCMD_REPORT_KEY
- GPCMD_REQUEST_SENSE
- GPCMD_RESERVE_RZONE_TRACK
- GPCMD_SCAN
- GPCMD_SEEK
- GPCMD_SEND_CUE_SHEET
- GPCMD_SEND_DVD_STRUCTURE
- GPCMD_SEND_EVENT
- GPCMD_SEND_KEY
- GPCMD_SEND_OPC
- GPCMD_SET_READ_AHEAD
- GPCMD_SET_SPEED
- GPCMD_SET_STREAMING
- GPCMD_START_STOP_UNIT
- GPCMD_STOP_PLAY_SCAN
- GPCMD_TEST_UNIT_READY
- GPCMD_VERIFY_10
- GPCMD_WRITE_10
- GPCMD_WRITE_12
- GPCMD_WRITE_AND_VERIFY_10
- GPCMD_WRITE_BUFFER
- GPCPLL_CFG
- GPCPLL_CFG2
- GPCPLL_CFG2_PLL_STEPA_SHIFT
- GPCPLL_CFG2_SDM_DIN_MASK
- GPCPLL_CFG2_SDM_DIN_NEW_MASK
- GPCPLL_CFG2_SDM_DIN_NEW_SHIFT
- GPCPLL_CFG2_SDM_DIN_NEW_WIDTH
- GPCPLL_CFG2_SDM_DIN_SHIFT
- GPCPLL_CFG2_SDM_DIN_WIDTH
- GPCPLL_CFG2_SETUP2_SHIFT
- GPCPLL_CFG3
- GPCPLL_CFG3_PLL_DFS_TESTOUT_SHIFT
- GPCPLL_CFG3_PLL_DFS_TESTOUT_WIDTH
- GPCPLL_CFG3_PLL_STEPB_SHIFT
- GPCPLL_CFG3_PLL_STEPB_WIDTH
- GPCPLL_CFG3_VCO_CTRL_MASK
- GPCPLL_CFG3_VCO_CTRL_SHIFT
- GPCPLL_CFG3_VCO_CTRL_WIDTH
- GPCPLL_CFG_ENABLE
- GPCPLL_CFG_IDDQ
- GPCPLL_CFG_LOCK
- GPCPLL_CFG_LOCK_DET_OFF
- GPCPLL_CFG_SYNC_MODE
- GPCPLL_COEFF
- GPCPLL_COEFF_M_SHIFT
- GPCPLL_COEFF_M_WIDTH
- GPCPLL_COEFF_N_MASK
- GPCPLL_COEFF_N_SHIFT
- GPCPLL_COEFF_N_WIDTH
- GPCPLL_COEFF_P_SHIFT
- GPCPLL_COEFF_P_WIDTH
- GPCPLL_DVFS0
- GPCPLL_DVFS0_DFS_COEFF_MASK
- GPCPLL_DVFS0_DFS_COEFF_SHIFT
- GPCPLL_DVFS0_DFS_COEFF_WIDTH
- GPCPLL_DVFS0_DFS_DET_MAX_MASK
- GPCPLL_DVFS0_DFS_DET_MAX_SHIFT
- GPCPLL_DVFS0_DFS_DET_MAX_WIDTH
- GPCPLL_DVFS1
- GPCPLL_DVFS1_DFS_CAL_DONE_BIT
- GPCPLL_DVFS1_DFS_CAL_DONE_SHIFT
- GPCPLL_DVFS1_DFS_CAL_DONE_WIDTH
- GPCPLL_DVFS1_DFS_CTRL_SHIFT
- GPCPLL_DVFS1_DFS_CTRL_WIDTH
- GPCPLL_DVFS1_DFS_EXT_CAL_SHIFT
- GPCPLL_DVFS1_DFS_EXT_CAL_WIDTH
- GPCPLL_DVFS1_DFS_EXT_DET_SHIFT
- GPCPLL_DVFS1_DFS_EXT_DET_WIDTH
- GPCPLL_DVFS1_DFS_EXT_SEL_SHIFT
- GPCPLL_DVFS1_DFS_EXT_SEL_WIDTH
- GPCPLL_DVFS1_DFS_EXT_STRB_SHIFT
- GPCPLL_DVFS1_DFS_EXT_STRB_WIDTH
- GPCPLL_DVFS1_EN_DFS_BIT
- GPCPLL_DVFS1_EN_DFS_CAL_BIT
- GPCPLL_DVFS1_EN_DFS_CAL_SHIFT
- GPCPLL_DVFS1_EN_DFS_CAL_WIDTH
- GPCPLL_DVFS1_EN_DFS_SHIFT
- GPCPLL_DVFS1_EN_DFS_WIDTH
- GPCPLL_DVFS1_EN_SDM_BIT
- GPCPLL_DVFS1_EN_SDM_SHIFT
- GPCPLL_DVFS1_EN_SDM_WIDTH
- GPCPLL_NDIV_SLOWDOWN
- GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT
- GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT
- GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT
- GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT
- GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT
- GPCR
- GPCR_DIR
- GPCR_DIR_PHY_RST
- GPCR_DIR_PIN
- GPCR_DIR_SERA_XCVR
- GPCR_DIR_SERB_XCVR
- GPCR_EDGE
- GPCR_EDGE_PIN
- GPCR_GEP_CNTL
- GPCR_INT_OUT_EN
- GPCR_MLAN_EN
- GPCR_OFFSET
- GPCR_PHY_RESET
- GPCR_UARTA_MODESEL
- GPCR_UARTB_MODESEL
- GPCT_ARM
- GPCT_CONT_PULSE_OUT
- GPCT_DISARM
- GPCT_DOWN
- GPCT_EXT_PIN
- GPCT_GET_INT_CLK_FRQ
- GPCT_HWUD
- GPCT_INT_CLOCK
- GPCT_NO_GATE
- GPCT_RESET
- GPCT_SET_DIRECTION
- GPCT_SET_GATE
- GPCT_SET_OPERATION
- GPCT_SET_SOURCE
- GPCT_SIMPLE_EVENT
- GPCT_SINGLE_PERIOD
- GPCT_SINGLE_PULSE_OUT
- GPCT_SINGLE_PW
- GPCT_UP
- GPC_1000HD
- GPC_75_OHM
- GPC_ADV_1000_FULL
- GPC_ADV_1000_HALF
- GPC_ADV_ALL
- GPC_ANEG_0
- GPC_ANEG_1
- GPC_ANEG_2
- GPC_ANEG_3
- GPC_ANEG_ADV_ALL_M
- GPC_BCAST
- GPC_BCAST_GPCPLL_CFG_BASE
- GPC_BCAST_GPCPLL_DVFS2
- GPC_BCAST_GPCPLL_DVFS2_DFS_EXT_STROBE_BIT
- GPC_BCAST_NDIV_SLOWDOWN_DEBUG
- GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK
- GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT
- GPC_CLK_MAX
- GPC_CLOCK
- GPC_CNTR
- GPC_CNTR_L2_PGE_SHIFT
- GPC_DETECT
- GPC_DIS_125
- GPC_DIS_FC
- GPC_DIS_SLEEP
- GPC_DUPLEX
- GPC_ENA_PAUSE
- GPC_ENA_XC
- GPC_FORCE_MASTER
- GPC_FORCE_SLAVE
- GPC_FRC100MBIT_FULL
- GPC_FRC100MBIT_HALF
- GPC_FRC10MBIT_FULL
- GPC_FRC10MBIT_HALF
- GPC_HWCFG_GMII_COP
- GPC_HWCFG_GMII_FIB
- GPC_HWCFG_M_0
- GPC_HWCFG_M_1
- GPC_HWCFG_M_2
- GPC_HWCFG_M_3
- GPC_IMR1
- GPC_IMR1_CORE0
- GPC_IMR1_CORE1
- GPC_IMR1_CORE2
- GPC_IMR1_CORE3
- GPC_INTPOL
- GPC_INT_POL_HI
- GPC_LEDCTL
- GPC_LEDMUX
- GPC_LINK
- GPC_LPCR_A_CORE_BSC
- GPC_M4_PU_PDN_FLG
- GPC_MAX
- GPC_MAX_IRQS
- GPC_PAUSE
- GPC_PDOWN
- GPC_PGC_CPU_MAPPING
- GPC_PGC_CPU_PDN
- GPC_PGC_CPU_PDNSCR
- GPC_PGC_CPU_PUPSCR
- GPC_PGC_CTRL
- GPC_PGC_CTRL_OFFS
- GPC_PGC_CTRL_PCR
- GPC_PGC_DISP_PDN
- GPC_PGC_DISP_SR
- GPC_PGC_DOMAIN_ARM
- GPC_PGC_DOMAIN_DISPLAY
- GPC_PGC_DOMAIN_PCI
- GPC_PGC_DOMAIN_PU
- GPC_PGC_GPU_PDN
- GPC_PGC_GPU_PDNSCR
- GPC_PGC_GPU_PUPSCR
- GPC_PGC_GPU_SR
- GPC_PGC_PCI_PDN
- GPC_PGC_PCI_SR
- GPC_PGC_PDNSCR_OFFS
- GPC_PGC_PUPSCR_OFFS
- GPC_PGC_SR
- GPC_PGC_SW2ISO_SHIFT
- GPC_PGC_SW_SHIFT
- GPC_PHYADDR_0
- GPC_PHYADDR_1
- GPC_PHYADDR_2
- GPC_PHYADDR_3
- GPC_PHYADDR_4
- GPC_PREF_MASTER
- GPC_PREF_SLAVE
- GPC_PU_PGC_SW_PDN_REQ
- GPC_PU_PGC_SW_PUP_REQ
- GPC_PU_PWRHSK
- GPC_REG12SEL
- GPC_REG18
- GPC_REG18SEL
- GPC_RST_CLR
- GPC_RST_SET
- GPC_RX_PAUSE
- GPC_SEL_BDT
- GPC_SLAVE
- GPC_SPEED
- GPC_SPILOCK
- GPC_TSTMODE
- GPC_TX_PAUSE
- GPC_UNIT
- GPDAT
- GPDIR
- GPDMA_DESC_BDP
- GPDMA_DESC_BUFLEN
- GPDMA_DESC_CHECKSUM
- GPDMA_DESC_EXTLEN
- GPDMA_DESC_HWO
- GPDMA_DESC_INT
- GPDMA_DESC_NEXT_H4
- GPDMA_DESC_PTR_H4
- GPDR
- GPDR_In
- GPDR_OFFSET
- GPDR_Out
- GPDX_DATA_INOUT
- GPDX_DATA_UPDATE_2_MASK
- GPDX_DATA_UPDATE_MASK
- GPDX_LED_AMBER_ON
- GPDX_LED_COLOR_MASK
- GPDX_LED_GREEN_ON
- GPDX_LED_UPDATE_MASK
- GPDX_LED_YELLOW_ON
- GPD_BUF_SIZE
- GPD_BUF_SIZE_EL
- GPD_DATA_LEN
- GPD_DATA_LEN_EL
- GPD_DATA_LEN_OG
- GPD_EXT_BUF
- GPD_EXT_BUF_EL
- GPD_EXT_BUF_OG
- GPD_EXT_FLAG_ZLP
- GPD_EXT_NGP
- GPD_EXT_NGP_EL
- GPD_EXT_NGP_OG
- GPD_FLAGS_BDP
- GPD_FLAGS_BPS
- GPD_FLAGS_HWO
- GPD_FLAGS_IOC
- GPD_FLAGS_ZLP
- GPD_RX_BUF_LEN
- GPD_RX_BUF_LEN_EL
- GPD_RX_BUF_LEN_OG
- GPD_STATE_ACTIVE
- GPD_STATE_POWER_OFF
- GPE
- GPE0A_EN_PORT
- GPE0A_PME_B0_EN_BIT
- GPE0A_PME_B0_STS_BIT
- GPE0A_PME_B0_VIRT_GPIO_PIN
- GPE0A_STS_PORT
- GPEDS0
- GPEFREQ_MASK
- GPEFREQ_OFFSET
- GPEP0_TIMEOUT
- GPEP0_TIMEOUT_ENABLE
- GPEP0_TIMEOUT_VALUE
- GPEP1_TIMEOUT
- GPEP1_TIMEOUT_ENABLE
- GPEP1_TIMEOUT_VALUE
- GPEP2_TIMEOUT
- GPEP2_TIMEOUT_ENABLE
- GPEP2_TIMEOUT_VALUE
- GPEP3_TIMEOUT
- GPEP3_TIMEOUT_ENABLE
- GPEP3_TIMEOUT_VALUE
- GPEX_ENABLE
- GPEX_ENABLE_UPDATE_2_MASK
- GPEX_ENABLE_UPDATE_MASK
- GPFEN0
- GPFIRST
- GPFSEL0
- GPGPU_OBJECT
- GPGPU_THREADS_DISPATCHED
- GPGPU_THREADS_DISPATCHED_UDW
- GPGPU_WALKER
- GPHEN0
- GPHY_CTRL
- GPHY_CTRL_100AB_EN
- GPHY_CTRL_10AB_EN
- GPHY_CTRL_ADDR_MASK
- GPHY_CTRL_ADDR_SHIFT
- GPHY_CTRL_ANEG_NOW
- GPHY_CTRL_BERT_START
- GPHY_CTRL_BP_VLTGSW
- GPHY_CTRL_CLS
- GPHY_CTRL_DEFAULT
- GPHY_CTRL_EXT_RESET
- GPHY_CTRL_EXT_RST_TO
- GPHY_CTRL_GATE_25M_EN
- GPHY_CTRL_GIGA_DIS
- GPHY_CTRL_HIB_EN
- GPHY_CTRL_HIB_PULSE
- GPHY_CTRL_LED_MODE
- GPHY_CTRL_LPW_EXIT
- GPHY_CTRL_PCLK_SEL_DIS
- GPHY_CTRL_PHY_IDDQ
- GPHY_CTRL_PHY_IDDQ_DIS
- GPHY_CTRL_PHY_PLL_BYPASS
- GPHY_CTRL_PHY_PLL_ON
- GPHY_CTRL_PIPE_MOD
- GPHY_CTRL_PWDOWN_HW
- GPHY_CTRL_PW_WOL_DIS
- GPHY_CTRL_REV_ANEG
- GPHY_CTRL_RTL_MODE
- GPHY_CTRL_SEL_ANA_RST
- GPHY_CTRL_TEST_MODE_MASK
- GPHY_CTRL_TEST_MODE_SHIFT
- GPHY_DUPLEX_LBN
- GPHY_DUPLEX_WIDTH
- GPHY_ISOLATE_LBN
- GPHY_ISOLATE_WIDTH
- GPHY_LINK_DOWN_INT
- GPHY_LINK_UP_INT
- GPHY_LOOPBACK_NEAR_LBN
- GPHY_LOOPBACK_NEAR_WIDTH
- GPHY_MODE_FE
- GPHY_MODE_GE
- GPHY_OCP
- GPHY_STS_MSK
- GPHY_WAKEUP_INT
- GPHY_XCONTROL_REG
- GPI
- GPI0_H2L_EVENT
- GPI0_L2H_EVENT
- GPI0_MARK
- GPI1_H2L_EVENT
- GPI1_L2H_EVENT
- GPI1_LDO_MASK
- GPI1_LDO_OFF
- GPI1_LDO_ON
- GPI1_MARK
- GPI2_MARK
- GPI3_MARK
- GPI3_PIN_IN_SEL
- GPI4_MARK
- GPI5_MARK
- GPI6_MARK
- GPI7_MARK
- GPIC_CFG_IC_EDGE_BOTH
- GPIC_CFG_IC_EDGE_FALL
- GPIC_CFG_IC_EDGE_RISE
- GPIC_CFG_IC_LEVEL_HIGH
- GPIC_CFG_IC_LEVEL_LOW
- GPIC_CFG_IC_MASK
- GPIC_CFG_IC_OFF
- GPIC_CFG_IDLEWAKE
- GPIC_CFG_IL_MASK
- GPIC_CFG_IL_SET
- GPIC_CFG_PC_DEV
- GPIC_CFG_PC_GPIN
- GPIC_CFG_PC_GPOHIGH
- GPIC_CFG_PC_GPOLOW
- GPIC_CFG_PC_MASK
- GPIC_GPIO_BANKOFF
- GPIC_GPIO_TO_BIT
- GPID0_DESC
- GPID2_DESC
- GPID4_DESC
- GPID6_DESC
- GPID_DESC
- GPIE
- GPIE0_DESC
- GPIE2_DESC
- GPIE4_DESC
- GPIE6_DESC
- GPIE_DESC
- GPIF_A00
- GPIF_A01
- GPIF_A02
- GPIF_A03
- GPIF_A04
- GPIF_A05
- GPIF_A06
- GPIF_A07
- GPIF_A08
- GPIF_A09
- GPIF_A10
- GPIF_A11
- GPIF_A12
- GPIF_A13
- GPIF_A14
- GPINDIS_BIT
- GPINR
- GPINT_TST_FAILURE
- GPIO
- GPIO0
- GPIO00_KP_MKIN0
- GPIO012_PIN_IN_SEL
- GPIO012_PIN_TO_BIT
- GPIO01_KP_MKOUT0
- GPIO02_KP_MKIN1
- GPIO03_KP_MKOUT1
- GPIO04_KP_MKIN2
- GPIO05_KP_MKOUT2
- GPIO06_KP_MKIN3
- GPIO07_KP_MKOUT3
- GPIO08
- GPIO08_KP_MKIN4
- GPIO09_KP_MKOUT4
- GPIO0IRQ
- GPIO0P0CTLI
- GPIO0P0CTLO
- GPIO0_2_CLK_EXT
- GPIO0_2_GPIO
- GPIO0_2_HZ_CLK
- GPIO0_2_KP_DKIN_0
- GPIO0_2_MMC4_DAT0
- GPIO0_2_ONE_WIRE
- GPIO0_2_USBH_PEN
- GPIO0_3
- GPIO0_COLIBRI_PXA270_SD_DETECT
- GPIO0_DATA
- GPIO0_DFI_D15
- GPIO0_DF_RDY
- GPIO0_DRQ
- GPIO0_GPIO
- GPIO0_HX4700_nKEY_POWER
- GPIO0_INCOME_SD_DETECT
- GPIO0_INCOME_SD_RO
- GPIO0_INT
- GPIO0_INTERRUPT
- GPIO0_INTERRUPT_ENABLE
- GPIO0_INTMD
- GPIO0_INT_EN
- GPIO0_ISR1H
- GPIO0_KEY_POWER
- GPIO0_KP_MKIN_0
- GPIO0_MAGICIAN_KEY_POWER
- GPIO0_MD
- GPIO0_OSRH
- GPIO0_OUTPUT_ENABLE
- GPIO0_RESET
- GPIO0_TSRH
- GPIO0_USB_P2_7
- GPIO0_ZIPITZ2_AC_DETECT
- GPIO1
- GPIO10
- GPIO100_DREQ_2
- GPIO100_FFUART_CTS
- GPIO100_GPIO
- GPIO100_HX4700_AUTO_SENSE
- GPIO100_KP_MKIN_0
- GPIO100_KP_MKIN_6
- GPIO100_LCD_DD14
- GPIO100_LCD_DD22
- GPIO100_MAGICIAN_KEY_VOL_UP
- GPIO100_MII_MDC
- GPIO100_TWSI5_SDA
- GPIO100_U2D_RESET
- GPIO100_U2D_TERM_SEL
- GPIO100_UART1_DCD
- GPIO100_UART1_RXD
- GPIO100_UART1_TXD
- GPIO100_USB_P2_2
- GPIO100_USB_P2_4
- GPIO100_USB_P2_5
- GPIO100_USB_P2_6
- GPIO101_GPIO
- GPIO101_KP_MKIN_1
- GPIO101_KP_MKIN_7
- GPIO101_LCD_DD15
- GPIO101_LCD_DD23
- GPIO101_MAGICIAN_KEY_VOL_DOWN
- GPIO101_MII_MDIO
- GPIO101_MMC2_DAT3
- GPIO101_U2D_SUSPEND
- GPIO101_U2D_XCVR_SEL
- GPIO101_UART1_CTS
- GPIO101_UART1_DSR
- GPIO101_UART1_DTR
- GPIO101_UART1_RTS
- GPIO101_USB_P2_1
- GPIO101_USB_P2_8
- GPIO102_FFUART_RXD
- GPIO102_GPIO
- GPIO102_HX4700_SYNAPTICS_POWER_ON
- GPIO102_KP_MKIN_2
- GPIO102_LCD_DD16
- GPIO102_MAGICIAN_KEY_PHONE
- GPIO102_MMC2_DAT2
- GPIO102_U2D_TERM_SEL
- GPIO102_UART1_DCD
- GPIO102_UART1_RI
- GPIO102_UART1_RXD
- GPIO102_UART1_TXD
- GPIO102_USB_P2_3
- GPIO102_USB_P2_4
- GPIO102_UTM_LINESTATE_0
- GPIO102_WLAN_RST
- GPIO102_nPCE_1
- GPIO103_CIF_DD_3
- GPIO103_CLK13MOUTDMD
- GPIO103_GPIO
- GPIO103_GSSP2_CLK
- GPIO103_HX4700_SYNAPTICS_INT
- GPIO103_KP_MKOUT_0
- GPIO103_LCD_CS
- GPIO103_LCD_DD17
- GPIO103_MAGICIAN_LED_KP
- GPIO103_MMC2_DAT1
- GPIO103_MMC3_CLK
- GPIO103_RX_DV
- GPIO103_U2D_SUSPEND
- GPIO103_UART1_DSR
- GPIO103_UART1_DTR
- GPIO103_USB_P2_5
- GPIO103_USB_P2_8
- GPIO103_UTM_LINESTATE_1
- GPIO104_CIF_DD_2
- GPIO104_CLK26MOUTDMD
- GPIO104_DFI_D7
- GPIO104_GPIO
- GPIO104_GSSP2_FRM
- GPIO104_KP_MKOUT_1
- GPIO104_KP_MKOUT_6
- GPIO104_LCD_DD18
- GPIO104_LCD_SPIDOUT
- GPIO104_MAGICIAN_LCD_VOFF_EN
- GPIO104_MMC2_DAT0
- GPIO104_PSKTSEL
- GPIO104_PWM4_OUT
- GPIO104_U2D_OPMODE1
- GPIO104_UART1_CTS
- GPIO104_UART1_RI
- GPIO104_UART1_RTS
- GPIO104_UART1_RXD
- GPIO104_USB_P2_3
- GPIO104_USB_P2_7
- GPIO104_UTM_LINESTATE_0
- GPIO105_CI2C_SDA
- GPIO105_CIF_DD_1
- GPIO105_CLK26MOUT
- GPIO105_DFI_D6
- GPIO105_GPIO
- GPIO105_GSSP2_RXD
- GPIO105_HX4700_nIR_ON
- GPIO105_KP_DKIN_0
- GPIO105_KP_MKOUT_2
- GPIO105_KP_MKOUT_7
- GPIO105_LCD_DD19
- GPIO105_LCD_SPIDIN
- GPIO105_MAGICIAN_LCD_VON_EN
- GPIO105_MMC2_CMD
- GPIO105_MMC3_CMD
- GPIO105_MMC_POWER
- GPIO105_UART1_DSR
- GPIO105_UART1_DTR
- GPIO105_UART3_CTS
- GPIO105_UART3_RTS
- GPIO105_USB_P2_5
- GPIO105_UTM_LINESTATE_1
- GPIO106_1WIRE
- GPIO106_CI2C_SCL
- GPIO106_CIF_DD_9
- GPIO106_DFI_D5
- GPIO106_GPIO
- GPIO106_GPS_UNKNOWN2
- GPIO106_GSSP2_TXD
- GPIO106_HX4700_CPU_BT_nRESET
- GPIO106_KP_DKIN_1
- GPIO106_KP_MKOUT_3
- GPIO106_LCD_DD20
- GPIO106_LCD_RESET
- GPIO106_MAGICIAN_LCD_DCDC_NRESET
- GPIO106_MMC2_CLK
- GPIO106_PWM2_OUT
- GPIO106_U2D_OPMODE_1
- GPIO106_UART1_CTS
- GPIO106_UART1_RTS
- GPIO106_UART3_CTS
- GPIO106_UART3_RTS
- GPIO106_USB_P2_7
- GPIO107_CIF_DD_8
- GPIO107_DFI_D4
- GPIO107_GPIO
- GPIO107_GPS_UNKNOWN3
- GPIO107_HX4700_SPK_nSD
- GPIO107_KP_DKIN_0
- GPIO107_KP_DKIN_2
- GPIO107_KP_MKOUT_4
- GPIO107_LCD_CS1
- GPIO107_LCD_DD21
- GPIO107_MAGICIAN_DS1WM_IRQ
- GPIO107_SSP2_RXD
- GPIO107_UART1_RXD
- GPIO107_UART1_TXD
- GPIO107_UART3_CTS
- GPIO107_UART3_RTS
- GPIO107_UART3_RXD
- GPIO107_UART3_TXD
- GPIO107_UTM_LINESTATE_0
- GPIO107_VPAC270_PCMCIA_PPEN
- GPIO108_CIF_DD_7
- GPIO108_DFI_D15
- GPIO108_GPIO
- GPIO108_KP_DKIN_1
- GPIO108_KP_DKIN_3
- GPIO108_KP_MKOUT_5
- GPIO108_LCD_DCLK
- GPIO108_LCD_DD22
- GPIO108_MAGICIAN_GSM_READY
- GPIO108_SSP2_TXD
- GPIO108_U2D_OPMODE1
- GPIO108_UART1_RXD
- GPIO108_UART1_TXD
- GPIO108_UART3_CTS
- GPIO108_UART3_RTS
- GPIO108_UART3_RXD
- GPIO108_UART3_TXD
- GPIO109_DFI_D14
- GPIO109_GPIO
- GPIO109_HX4700_CODEC_nPDN
- GPIO109_KP_DKIN_2
- GPIO109_KP_DKIN_4
- GPIO109_KP_MKIN1
- GPIO109_LCD_DD23
- GPIO109_MMC_DAT_1
- GPIO109_MSSDIO
- GPIO109_UART1_CTS
- GPIO109_UART1_RTS
- GPIO109_UART2_CTS
- GPIO109_UART2_RTS
- GPIO109_UART3_RXD
- GPIO109_UART3_TXD
- GPIO109_UTM_LINESTATE_0
- GPIO10_2_GPIO
- GPIO10_2_LCD_LDD_4
- GPIO10_2_MLCD_DD_4
- GPIO10_2_MMC3_DAT3
- GPIO10_CHOUT_1
- GPIO10_DFI_D5
- GPIO10_ETHIRQ
- GPIO10_FFUART_DCD
- GPIO10_GPIO
- GPIO10_HZ_CLK
- GPIO10_KP_DKIN_6
- GPIO10_KP_MKIN5
- GPIO10_KP_MKIN_5
- GPIO10_KP_MKIN_7
- GPIO10_LED_nCharging
- GPIO10_MAGICIAN_GSM_IRQ
- GPIO10_MMC1_DAT3
- GPIO10_MMC2_DAT1
- GPIO10_RTCCLK
- GPIO10_USB_HUB_RESET
- GPIO10_USB_P3_5
- GPIO10_UTM_CLK
- GPIO10_ZIPITZ2_LED_WIFI
- GPIO11
- GPIO110_DFI_D13
- GPIO110_GPIO
- GPIO110_HX4700_LCD_LVDD_3V3_ON
- GPIO110_KP_DKIN_3
- GPIO110_KP_DKIN_5
- GPIO110_KP_MKIN0
- GPIO110_MMC_DAT_2
- GPIO110_U2D_OPMODE_1
- GPIO110_UART1_CTS
- GPIO110_UART1_RTS
- GPIO110_UART2_RXD
- GPIO110_UART2_TXD
- GPIO110_UART3_RXD
- GPIO110_UART3_TXD
- GPIO111_DFI_D8
- GPIO111_GPIO
- GPIO111_HX4700_LCD_AVDD_3V3_ON
- GPIO111_KP_DKIN_4
- GPIO111_KP_DKIN_6
- GPIO111_KP_MKOUT7
- GPIO111_MMC3_DAT0
- GPIO111_MMC_DAT_3
- GPIO111_SSP2_CLK
- GPIO111_UART1_DSR
- GPIO111_UART1_RI
- GPIO111_UART2_CTS
- GPIO111_UART2_RTS
- GPIO111_UART2_RXD
- GPIO111_UART2_TXD
- GPIO112_GPIO
- GPIO112_HX4700_LCD_N2V7_7V3_ON
- GPIO112_KP_DKIN_5
- GPIO112_KP_DKIN_7
- GPIO112_KP_MKIN_6
- GPIO112_KP_MKOUT6
- GPIO112_MMC3_CMD
- GPIO112_MMC_CMD
- GPIO112_ND_RDY0
- GPIO112_SSP2_FRM
- GPIO112_UART1_DCD
- GPIO112_UART1_DTR
- GPIO112_UART2_CTS
- GPIO112_UART2_RTS
- GPIO112_UART2_RXD
- GPIO112_UART2_TXD
- GPIO112_nMSINS
- GPIO113_AC97_nRESET
- GPIO113_AC97_nRESET_GPIO_HIGH
- GPIO113_COLIBRI_PXA270_TS_IRQ
- GPIO113_GPIO
- GPIO113_GSM_EVENT
- GPIO113_I2S_MCLK
- GPIO113_I2S_SYSCLK
- GPIO113_INCOME_TS_IRQ
- GPIO113_KP_DKIN_0
- GPIO113_KP_DKIN_6
- GPIO113_KP_MKIN_0
- GPIO113_KP_MKIN_7
- GPIO113_SMC_RDY
- GPIO113_UART2_RXD
- GPIO113_UART2_TXD
- GPIO113_USB_P3_3
- GPIO113_VPAC270_TS_IRQ
- GPIO114_CIF_DD_1
- GPIO114_COLIBRI_PXA270_ETH_IRQ
- GPIO114_GPIO
- GPIO114_GSM_nMOD_DTE_UART_STATE
- GPIO114_HX4700_CF_RESET
- GPIO114_I2S_FRM
- GPIO114_I2S_MCLK
- GPIO114_INCOME_ETH_IRQ
- GPIO114_KP_DKIN_1
- GPIO114_KP_DKIN_7
- GPIO114_KP_MKIN_1
- GPIO114_MAGICIAN_UNKNOWN
- GPIO114_MMC_CD
- GPIO114_MN_CLK_OUT
- GPIO114_UART2_CTS
- GPIO114_UART2_RTS
- GPIO114_UEN
- GPIO114_UVS0
- GPIO114_VPAC270_ETH_IRQ
- GPIO115_CIF_DD_3
- GPIO115_DREQ_0
- GPIO115_GPIO
- GPIO115_I2S_BCLK
- GPIO115_KP_DKIN_0
- GPIO115_KP_DKIN_2
- GPIO115_KP_MKIN_0
- GPIO115_KP_MKIN_2
- GPIO115_LED_nKeyboard
- GPIO115_MAGICIAN_nPEN_IRQ
- GPIO115_MBREQ
- GPIO115_PWM1_OUT
- GPIO115_UEN
- GPIO115_WLAN_PWEN
- GPIO115_nUVS1
- GPIO116_AC97_SDATA_IN_0
- GPIO116_CIF_DD_2
- GPIO116_DVAL_0
- GPIO116_GPIO
- GPIO116_HX4700_CPU_HW_nRESET
- GPIO116_I2S_RXD
- GPIO116_I2S_TXD
- GPIO116_KP_DKIN_1
- GPIO116_KP_DKIN_3
- GPIO116_KP_MKIN_1
- GPIO116_KP_MKIN_3
- GPIO116_MAGICIAN_nCAM_EN
- GPIO116_MBGNT
- GPIO116_UDET
- GPIO116_nUVS2
- GPIO117_GPIO
- GPIO117_I2C_SCL
- GPIO117_I2S_TXD
- GPIO117_KP_DKIN_2
- GPIO117_KP_DKIN_4
- GPIO117_KP_MKIN_2
- GPIO117_KP_MKIN_4
- GPIO117_PWM1_OUT
- GPIO118_GPIO
- GPIO118_I2C_SDA
- GPIO118_KP_DKIN_3
- GPIO118_KP_DKIN_5
- GPIO118_KP_MKIN_3
- GPIO118_KP_MKIN_5
- GPIO118_PWM2_OUT
- GPIO119_GPIO
- GPIO119_KP_DKIN_4
- GPIO119_KP_DKIN_6
- GPIO119_KP_MKIN_4
- GPIO119_KP_MKIN_6
- GPIO119_MAGICIAN_UNKNOWN
- GPIO119_PWM3_OUT
- GPIO119_USBH2_PWR
- GPIO11_2_GPIO
- GPIO11_2_LCD_LDD_5
- GPIO11_2_MLCD_DD_5
- GPIO11_2_MMC3_CLK
- GPIO11_3_6MHz
- GPIO11_48_MHz
- GPIO11_AC97_SDATA_IN_2
- GPIO11_CHOUT_0
- GPIO11_DFI_D4
- GPIO11_EXT_SYNC0
- GPIO11_EXT_SYNC_0
- GPIO11_GPIO
- GPIO11_KP_DKIN_7
- GPIO11_KP_MKOUT5
- GPIO11_KP_MKOUT_5
- GPIO11_MAGICIAN_GSM_OUT1
- GPIO11_MMC1_DAT2
- GPIO11_MMC2_DAT2
- GPIO11_NAND_CS
- GPIO11_PWM0_OUT
- GPIO11_PWM2_OUT
- GPIO11_SSP2_RXD
- GPIO11_UART3_RTS
- GPIO11_USB_P3_1
- GPIO11_VPAC270_PCMCIA_RESET
- GPIO11_nCD
- GPIO11_nCD_MD
- GPIO12
- GPIO120_GPIO
- GPIO120_KP_DKIN_5
- GPIO120_KP_DKIN_7
- GPIO120_KP_MKIN_5
- GPIO120_KP_MKIN_7
- GPIO120_MAGICIAN_UNKNOWN
- GPIO120_PWM4_OUT
- GPIO120_USBH2_PEN
- GPIO121_GPIO
- GPIO121_KP_DKIN_6
- GPIO121_KP_MKIN4
- GPIO121_KP_MKOUT_0
- GPIO122_GPIO
- GPIO122_KP_DKIN_5
- GPIO122_KP_MKOUT_1
- GPIO122_PWM3_OUT
- GPIO123_CLK_REQ
- GPIO123_GPIO
- GPIO123_KP_DKIN_4
- GPIO123_KP_MKOUT_2
- GPIO123_PWM1_OUT
- GPIO124_GPIO
- GPIO124_KP_DKIN_3
- GPIO124_KP_MKOUT_3
- GPIO124_LCD_DD24
- GPIO124_MMC1_DAT7
- GPIO124_MN_CLK_OUT
- GPIO124_PWM2_OUT
- GPIO125_GPIO
- GPIO125_KP_DKIN_2
- GPIO125_KP_MKIN_2
- GPIO125_KP_MKOUT_4
- GPIO125_LCD_DD25
- GPIO125_MMC1_DAT6
- GPIO125_MMC4_DAT3
- GPIO125_PWM3_OUT
- GPIO126_EXT_CLK
- GPIO126_GPIO
- GPIO126_KP_DKIN_1
- GPIO126_KP_MKOUT_5
- GPIO126_KP_MKOUT_7
- GPIO126_LCD_DD33
- GPIO126_MMC4_DAT2
- GPIO126_OW_DQ
- GPIO126_PWM4_OUT
- GPIO126_RTC_MVT
- GPIO127_CLK_BYPASS_GB
- GPIO127_GPIO
- GPIO127_KP_DKIN_0
- GPIO127_KP_MKOUT_6
- GPIO127_LCD_CS_N
- GPIO127_LCD_DD26
- GPIO127_MMC4_DAT1
- GPIO128_GPIO
- GPIO128_LCD_DD27
- GPIO129_GPIO
- GPIO129_LCD_DD28
- GPIO129_MMC1_DAT5
- GPIO12_2_GPIO
- GPIO12_2_LCD_LDD_6
- GPIO12_2_MLCD_DD_6
- GPIO12_2_MMC3_CMD
- GPIO12_32KHz
- GPIO12_48_MHz
- GPIO12_A780_FLIP_LID
- GPIO12_AC97_SDATA_IN_3
- GPIO12_BSSP1_CLK
- GPIO12_CHOUT_1
- GPIO12_CIF_DD_7
- GPIO12_DFI_D3
- GPIO12_E680_LOCK_SWITCH
- GPIO12_EXT_SYNC1
- GPIO12_EXT_SYNC_1
- GPIO12_GPIO
- GPIO12_HPJACK_INSERT
- GPIO12_HX4700_ASIC3_IRQ
- GPIO12_KP_DKIN_0
- GPIO12_KP_MKIN6
- GPIO12_KP_MKIN_6
- GPIO12_KP_MKOUT_6
- GPIO12_MMC1_DAT1
- GPIO12_MMC2_DAT3
- GPIO12_PWM1_OUT
- GPIO12_PWM3_OUT
- GPIO12_SSP2_SCLK
- GPIO12_VPAC270_CF_RDY
- GPIO13
- GPIO130_CAM_RESET
- GPIO130_GPIO
- GPIO130_LCD_DD29
- GPIO130_MMC1_DAT4
- GPIO131_GPIO
- GPIO131_MMC1_DAT3
- GPIO132_GPIO
- GPIO132_MMC1_DAT2
- GPIO133_GPIO
- GPIO133_MMC1_DAT1
- GPIO134_GPIO
- GPIO134_MMC1_DAT0
- GPIO135_GPIO
- GPIO135_LCD_DD30
- GPIO136_GPIO
- GPIO136_MMC1_CMD
- GPIO137_GPIO
- GPIO137_LCD_DD31
- GPIO138_GPIO
- GPIO138_LCD_DD32
- GPIO139_GPIO
- GPIO139_MMC1_CLK
- GPIO13_2_GPIO
- GPIO13_2_LCD_LDD_7
- GPIO13_2_MLCD_DD_7
- GPIO13_BSSP1_FRM
- GPIO13_CHOUT0
- GPIO13_CLK_EXT
- GPIO13_COLIBRI_PXA300_SD_DETECT
- GPIO13_DFI_D2
- GPIO13_GPIO
- GPIO13_HX4700_W3220_IRQ
- GPIO13_KP_DKIN_1
- GPIO13_KP_KDIN_7
- GPIO13_KP_MKIN_7
- GPIO13_KP_MKOUT6
- GPIO13_KP_MKOUT_4
- GPIO13_KP_MKOUT_6
- GPIO13_KP_MKOUT_7
- GPIO13_MAGICIAN_CPLD_IRQ
- GPIO13_MBGNT
- GPIO13_MMC1_DAT0
- GPIO13_MMC2_CLK
- GPIO13_MMC_CD
- GPIO13_PWM2_OUT
- GPIO13_SSP2_TXD
- GPIO13_nUSB_DETECT
- GPIO14
- GPIO140_GPIO
- GPIO140_LCD_DD34
- GPIO140_MMC1_CD
- GPIO141_GPIO
- GPIO141_LCD_DD35
- GPIO141_MMC1_WP
- GPIO142_GPIO
- GPIO143_GPIO
- GPIO143_ND_nCS0
- GPIO144_GPIO
- GPIO144_ND_nCS1
- GPIO145_GPIO
- GPIO145_SMC_nCS0
- GPIO146_GPIO
- GPIO146_SMC_nCS1
- GPIO147_GPIO
- GPIO147_ND_nWE
- GPIO148_GPIO
- GPIO148_ND_nRE
- GPIO149_GPIO
- GPIO149_ND_CLE
- GPIO14_2_GPIO
- GPIO14_2_LCD_FCLK
- GPIO14_2_MLCD_FCLK
- GPIO14_BSSP1_RXD
- GPIO14_BT_nACTIVITY
- GPIO14_CHOUT1
- GPIO14_CLK26MOUT
- GPIO14_DFI_D1
- GPIO14_GPIO
- GPIO14_HX4700_nWLAN_IRQ
- GPIO14_HZ_CLK
- GPIO14_KP_DKIN_2
- GPIO14_KP_MKIN7
- GPIO14_KP_MKIN_7
- GPIO14_KP_MKOUT_5
- GPIO14_LCD_VSYNC
- GPIO14_MAGICIAN_TSC2046_CS
- GPIO14_MBREQ
- GPIO14_MMC1_CMD
- GPIO14_MMC2_CMD
- GPIO14_ONE_WIRE
- GPIO14_PWM3_OUT
- GPIO14_SSP2_SFRM
- GPIO14_UCLK
- GPIO14_ZIPITZ2_WIFI_POWER
- GPIO15
- GPIO150_GPIO
- GPIO150_ND_ALE
- GPIO151_GPIO
- GPIO151_MMC3_CLK
- GPIO151_SMC_SCLK
- GPIO152_GPIO
- GPIO152_SMC_BE0
- GPIO153_GPIO
- GPIO153_SMC_BE1
- GPIO154_GPIO
- GPIO154_SMC_IRQ
- GPIO155_GPIO
- GPIO155_SM_ADVMUX
- GPIO156_GPIO
- GPIO157_GPIO
- GPIO158_GPIO
- GPIO159_GPIO
- GPIO15_2_GPIO
- GPIO15_2_LCD_LCLK
- GPIO15_2_MLCD_LCLK
- GPIO15_A1200_FLIP_LID
- GPIO15_A910_FLIP_LID
- GPIO15_BSSP1_TXD
- GPIO15_DFI_D0
- GPIO15_E6_LOCK_SWITCH
- GPIO15_GPIO
- GPIO15_KP_DKIN_3
- GPIO15_KP_MKOUT7
- GPIO15_KP_MKOUT_7
- GPIO15_LCD_CS_N
- GPIO15_MMC1_CLK
- GPIO15_MMC1_CMD
- GPIO15_SDIO_INSERT
- GPIO15_SSP1_SCLK
- GPIO15_UART2_CTS
- GPIO15_UART2_RTS
- GPIO15_USB_P2_7
- GPIO15_VPAC270_LED_ORANGE
- GPIO15_nCS_1
- GPIO15_nPCE_1
- GPIO16
- GPIO160_GPIO
- GPIO160_ND_RDY1
- GPIO161_DFI_D12
- GPIO161_GPIO
- GPIO162_DFI_D11
- GPIO162_GPIO
- GPIO162_MMC3_DAT6
- GPIO163_DFI_D10
- GPIO163_GPIO
- GPIO163_MMC3_DAT4
- GPIO164_DFI_D9
- GPIO164_GPIO
- GPIO164_MMC3_DAT2
- GPIO165_DFI_D3
- GPIO165_GPIO
- GPIO165_MMC3_DAT7
- GPIO166_DFI_D2
- GPIO166_GPIO
- GPIO166_MMC3_DAT5
- GPIO167_DFI_D1
- GPIO167_GPIO
- GPIO167_MMC3_DAT3
- GPIO168_DFI_D0
- GPIO168_GPIO
- GPIO168_MMC3_DAT1
- GPIO16_2_GPIO
- GPIO16_2_LCD_PCLK
- GPIO16_2_MLCD_PCLK
- GPIO16_CIR_OUT
- GPIO16_FFUART_TXD
- GPIO16_GPIO
- GPIO16_KP_DKIN0
- GPIO16_KP_DKIN_6
- GPIO16_KP_MKIN_5
- GPIO16_ND_nCS0
- GPIO16_PWM0_OUT
- GPIO16_SMC_nCS0
- GPIO16_SMC_nCS1
- GPIO16_SSP1_FRM
- GPIO16_UART2_CTS
- GPIO16_UART2_RTS
- GPIO16_USB_HUB_RESET
- GPIO16_USB_P2_7
- GPIO16_VPAC270_CF_RESET
- GPIO16_uSIM_UVS_0
- GPIO17
- GPIO17_2_GPIO
- GPIO17_2_LCD_BIAS
- GPIO17_2_MLCD_BIAS
- GPIO17_AC97_SDATA_IN_2
- GPIO17_CIF_DD_6
- GPIO17_EXT_SYNC_MVT_0
- GPIO17_GPIO
- GPIO17_KP_DKIN1
- GPIO17_KP_MKIN_6
- GPIO17_LCD_FCLK_RD
- GPIO17_MLCD_FCLK
- GPIO17_ND_nWE
- GPIO17_PWM0_OUT
- GPIO17_PWM1_OUT
- GPIO17_SSP2_FRM
- GPIO17_VPAC270_CF_CD
- GPIO18
- GPIO18_AC97_SDATA_IN_3
- GPIO18_EXT_SYNC_MVT_1
- GPIO18_GPIO
- GPIO18_HX4700_RDY
- GPIO18_KP_DKIN2
- GPIO18_LCD_LCLK_A0
- GPIO18_MAGICIAN_UNKNOWN
- GPIO18_MLCD_LCLK
- GPIO18_MMC1_DAT0
- GPIO18_POWEROFF
- GPIO18_PWM1_OUT
- GPIO18_RDY
- GPIO18_SMC_nCS0
- GPIO18_SMC_nCS1
- GPIO18_SSP1_RXD
- GPIO18_SSP1_TXD
- GPIO18_UART2_RXD
- GPIO18_UART2_TXD
- GPIO18_nBVD1
- GPIO18_nSTSCHG
- GPIO18_nSTSCHG_MD
- GPIO19
- GPIO19_CF_nCE1
- GPIO19_DREQ_1
- GPIO19_FFUART_RXD
- GPIO19_GEN1_CAM_RST
- GPIO19_GPIO
- GPIO19_KP_DKIN3
- GPIO19_KP_MKOUT_4
- GPIO19_LCD_CS
- GPIO19_LCD_PCLK_WR
- GPIO19_MLCD_PCLK
- GPIO19_MMC1_DAT1
- GPIO19_OST_CHOUT_MVT_0
- GPIO19_PWM2_OUT
- GPIO19_SMC_nCS0
- GPIO19_SSP2_RXD
- GPIO19_SSP2_SCLK
- GPIO19_SSP2_TXD
- GPIO19_UART2_RXD
- GPIO19_UART2_TXD
- GPIO19_WLAN_STRAP
- GPIO19_ZIPITZ2_LCD_RESET
- GPIO19_nURST
- GPIO1IRQ
- GPIO1O_UART3_CTS
- GPIO1P0CTLI
- GPIO1P0CTLO
- GPIO1_2_GPIO
- GPIO1_2_KP_DKIN_1
- GPIO1_2_MMC4_CMD
- GPIO1_2_USBH_PWR
- GPIO1_CLK_ENB
- GPIO1_DATA
- GPIO1_DATA0
- GPIO1_DATA1
- GPIO1_DFI_D14
- GPIO1_DIR_INPUT
- GPIO1_GPIO
- GPIO1_INTERRUPT
- GPIO1_INTERRUPT_ENABLE
- GPIO1_KP_MKOUT_0
- GPIO1_MD
- GPIO1_MD0
- GPIO1_MD1
- GPIO1_OUTPUT_ENABLE
- GPIO1_RESET
- GPIO1_RST
- GPIO1_VPAC270_USER_BTN
- GPIO1_ZIPITZ2_POWER_BUTTON
- GPIO1_nCS2
- GPIO2
- GPIO20
- GPIO20_CF_nCE2
- GPIO20_DREQ_0
- GPIO20_GPIO
- GPIO20_KP_DKIN4
- GPIO20_KP_MKOUT_5
- GPIO20_LCD_BIAS
- GPIO20_MBREQ
- GPIO20_MLCD_BIAS
- GPIO20_MMC1_DAT2
- GPIO20_NAND_RB
- GPIO20_OST_CHOUT_MVT_1
- GPIO20_OW_DQ_IN
- GPIO20_PWM0
- GPIO20_PWM3_OUT
- GPIO20_RTC_MVT
- GPIO20_SMC_nCS1
- GPIO20_SSP1_RXD
- GPIO20_SSP1_SYSCLK
- GPIO20_SSP1_TXD
- GPIO20_nSDCS_2
- GPIO21
- GPIO21_AC97_SDATA_IN_2
- GPIO21_DVAL_0
- GPIO21_GPIO
- GPIO21_I2C_SCL
- GPIO21_KP_DKIN5
- GPIO21_LCD_CS
- GPIO21_MBGNT
- GPIO21_MMC1_DAT3
- GPIO21_ND_ALE
- GPIO21_PWM2
- GPIO21_SSP1_BITCLK
- GPIO21_nSDCS_3
- GPIO22
- GPIO22_AC97_SDATA_IN_3
- GPIO22_ETHIRQ
- GPIO22_GPIO
- GPIO22_HX4700_LCD_RL
- GPIO22_I2C_SDA
- GPIO22_KP_DKIN6
- GPIO22_KP_MKOUT_7
- GPIO22_LCD_CS2
- GPIO22_LCD_VSYNC
- GPIO22_MAGICIAN_VIBRA_EN
- GPIO22_MMC1_CLK
- GPIO22_ND_CLE
- GPIO22_PWM3
- GPIO22_SSP1_SYNC
- GPIO22_SSP2_EXTCLK
- GPIO22_SSP2_SCLK
- GPIO22_SSP2_SCLKEN
- GPIO22_SSP2_SYSCLK
- GPIO22_USB_ENABLE
- GPIO23
- GPIO23_AC97_nACRESET
- GPIO23_CF_nALE
- GPIO23_CIF_MCLK
- GPIO23_GPIO
- GPIO23_GPS_UNKNOWN1
- GPIO23_KP_DKIN7
- GPIO23_LCD_DD0
- GPIO23_MLCD_DD0
- GPIO23_MMC1_CMD
- GPIO23_SMC_nLUA
- GPIO23_SSP1_DATA_OUT
- GPIO23_SSP1_SCLK
- GPIO23_SSP1_SCLK_IN
- GPIO23_SSP2_SCLK
- GPIO23_SSP2_SCLKEN
- GPIO24
- GPIO24_AC97_SYSCLK
- GPIO24_CIF_FV
- GPIO24_GPIO
- GPIO24_GSM_MOD_RESET_CMD
- GPIO24_I2S_SYSCLK
- GPIO24_LCD_DD1
- GPIO24_MLCD_DD1
- GPIO24_MMC1_CMD
- GPIO24_MMC2_DAT0
- GPIO24_ND_nRE
- GPIO24_SSP1_SDATA_IN
- GPIO24_SSP1_SFRM
- GPIO24_SSP2_RXD
- GPIO24_SSP2_TXD
- GPIO24_UTM_RXVALID
- GPIO24_ZIPITZ2_WIFI_CS
- GPIO25
- GPIO25_AC97_SDATA_IN_0
- GPIO25_CF_nRESET
- GPIO25_CIF_LV
- GPIO25_GPIO
- GPIO25_GSM_MOD_ON_STATE
- GPIO25_I2S_BITCLK
- GPIO25_LCD_DD2
- GPIO25_MLCD_DD2
- GPIO25_MMC2_DAT1
- GPIO25_SMC_nLLA
- GPIO25_SSP1_TXD
- GPIO25_SSP2_SCLK
- GPIO25_UTM_RXACTIVE
- GPIO26
- GPIO26_AC97_SDATA_IN_1
- GPIO26_CIF_PCLK
- GPIO26_FFUART_CTS
- GPIO26_GPIO
- GPIO26_GPS_ON
- GPIO26_I2S_SYNC
- GPIO26_LCD_DD3
- GPIO26_MAGICIAN_GSM_POWER
- GPIO26_MLCD_DD3
- GPIO26_MMC2_DAT2
- GPIO26_ND_RnB1
- GPIO26_PRDY_nBSY
- GPIO26_PRDY_nBSY_MD
- GPIO26_SSP1_RXD
- GPIO26_SSP2_FRM
- GPIO26_U2D_RXERROR
- GPIO27
- GPIO27_AC97_SDATA_OUT
- GPIO27_CIF_DD_0
- GPIO27_DIR_OUTPUT
- GPIO27_FFUART_RTS
- GPIO27_GPIO
- GPIO27_GPS_RESET
- GPIO27_HX4700_CODEC_ON
- GPIO27_I2S_DATA_OUT
- GPIO27_LCD_DD4
- GPIO27_MAGICIAN_USBC_PUEN
- GPIO27_MLCD_DD4
- GPIO27_MMC2_DAT3
- GPIO27_ND_RnB2
- GPIO27_PRDY_nBSY
- GPIO27_PRDY_nBSY_MD
- GPIO27_PWM3_AF2
- GPIO27_SMC_IRQ
- GPIO27_SSP1_EXTCLK
- GPIO27_SSP1_SCLKEN
- GPIO27_SSP1_SYSCLK
- GPIO27_SSP2_EXTCLK
- GPIO27_SSP2_RXD
- GPIO27_SSP2_TXD
- GPIO27_U2D_OPMODE_0
- GPIO28
- GPIO28_AC97_BITCLK
- GPIO28_AC97_SYNC
- GPIO28_ASSP_BITCLK_IN
- GPIO28_ASSP_BITCLK_OUT
- GPIO28_CF_RDY
- GPIO28_COLIBRI_PXA320_SD_DETECT
- GPIO28_GEN2_CAM_RST
- GPIO28_GPIO
- GPIO28_I2S_BITCLK_IN
- GPIO28_I2S_BITCLK_OUT
- GPIO28_I2S_SDATA_IN
- GPIO28_LCD_DD5
- GPIO28_MLCD_DD5
- GPIO28_MMC2_CLK
- GPIO28_MMC2_CMD
- GPIO28_SMC_RDY
- GPIO28_SSP1_SFRM
- GPIO28_SSP2_RXD
- GPIO28_SSP2_TXD
- GPIO28_U2D_OPMODE_1
- GPIO29
- GPIO29_AC97_BITCLK
- GPIO29_AC97_SDATA_IN_0
- GPIO29_ASSP_RXD
- GPIO29_CF_STSCH
- GPIO29_DIR_OUTPUT
- GPIO29_GPIO
- GPIO29_I2S_SDATA_IN
- GPIO29_LCD_DD6
- GPIO29_MLCD_DD6
- GPIO29_MMC1_DAT0
- GPIO29_MMC2_CLK
- GPIO29_MMC2_CMD
- GPIO29_SMC_SCLK
- GPIO29_SSP1_SCLK
- GPIO29_SSP2_EXTCLK
- GPIO29_SSP2_RXD
- GPIO29_SSP2_SCLK
- GPIO29_U2D_TXVALID
- GPIO29_UART1_RXD
- GPIO2_2_GPIO
- GPIO2_2_KP_DKIN_0
- GPIO2_2_KP_DKIN_6
- GPIO2_2_KP_MKIN_6
- GPIO2_2_MMC4_CLK
- GPIO2_2_USBH_PEN
- GPIO2_CLK13MOUTDMD
- GPIO2_CLK_ENB
- GPIO2_DATA
- GPIO2_DFI_D13
- GPIO2_DIR_INPUT
- GPIO2_GPIO
- GPIO2_INTERRUPT
- GPIO2_INTERRUPT_ENABLE
- GPIO2_KP_MKIN_1
- GPIO2_OUTPUT_ENABLE
- GPIO2_OUT_EN_REG
- GPIO2_RDY
- GPIO2_RESET
- GPIO2_nCS3
- GPIO3
- GPIO30
- GPIO30_AC97_SDATA_OUT
- GPIO30_ASSP_TXD
- GPIO30_CF_nREG
- GPIO30_DFI_ADDR0
- GPIO30_GPIO
- GPIO30_I2S_SDATA_OUT
- GPIO30_ICP_RXD
- GPIO30_LCD_DD7
- GPIO30_MAGICIAN_BQ24022_nCHARGE_EN
- GPIO30_MLCD_DD7
- GPIO30_MMC1_CLK
- GPIO30_MMC2_CLK
- GPIO30_MMC2_DAT0
- GPIO30_UART1_RXD
- GPIO30_UART1_TXD
- GPIO30_UART3_RXD
- GPIO30_UART3_TXD
- GPIO30_ULPI_DATA_OUT_0
- GPIO30_USB_P2_2
- GPIO30_USB_P3_2
- GPIO30_USB_ULPI_D1
- GPIO30_UTM_PHYDATA_0
- GPIO31
- GPIO31_AC97_SYNC
- GPIO31_ASSP_SFRM_IN
- GPIO31_ASSP_SFRM_OUT
- GPIO31_CF_nIOIS16
- GPIO31_CIR_OUT
- GPIO31_DFI_ADDR1
- GPIO31_DIR_OUTPUT
- GPIO31_GPIO
- GPIO31_I2S_SYNC
- GPIO31_ICP_TXD
- GPIO31_LCD_DD8
- GPIO31_MLCD_DD8
- GPIO31_MMC1_CMD
- GPIO31_MMC2_CMD
- GPIO31_MMC2_DAT1
- GPIO31_UART1_CTS
- GPIO31_UART1_RXD
- GPIO31_UART1_TXD
- GPIO31_UART3_RXD
- GPIO31_UART3_TXD
- GPIO31_ULPI_DATA_OUT_1
- GPIO31_USB_P2_6
- GPIO31_USB_P3_6
- GPIO31_USB_ULPI_D0
- GPIO31_UTM_PHYDATA_1
- GPIO32
- GPIO32_AC97_SDATA_IN_1
- GPIO32_AC97_SDATA_IN_2
- GPIO32_CF_nCD1
- GPIO32_DFI_ADDR2
- GPIO32_GPIO
- GPIO32_HX4700_RS232_ON
- GPIO32_I2C_SCL
- GPIO32_I2S_SYSCLK
- GPIO32_LCD_DD9
- GPIO32_MLCD_DD9
- GPIO32_MMC2_CLK
- GPIO32_MMC2_DAT2
- GPIO32_MMC_CLK
- GPIO32_MSSCLK
- GPIO32_PWM0
- GPIO32_UART1_CTS
- GPIO32_UART1_RTS
- GPIO32_UART3_TXD
- GPIO32_ULPI_DATA_OUT_2
- GPIO32_USB_P2_4
- GPIO32_USB_VP
- GPIO32_UTM_PHYDATA_2
- GPIO33
- GPIO33_AC97_SDATA_IN_3
- GPIO33_CF_nCD2
- GPIO33_DFI_ADDR3
- GPIO33_DVAL_1
- GPIO33_FFUART_DSR
- GPIO33_FFUART_RXD
- GPIO33_GPIO
- GPIO33_I2C_SDA
- GPIO33_LCD_DD10
- GPIO33_MBGNT
- GPIO33_MLCD_DD10
- GPIO33_MMC2_DAT0
- GPIO33_MMC2_DAT3
- GPIO33_SSP1_SCLK
- GPIO33_SSP2_SCLK
- GPIO33_SSPA2_CLK
- GPIO33_UART1_DCD
- GPIO33_ULPI_DATA_OUT_3
- GPIO33_ULPI_OTG_INTR
- GPIO33_USB_ULPI_D2
- GPIO33_UTM_PHYDATA_3
- GPIO33_nCS_5
- GPIO34
- GPIO34_AC97_SYSCLK
- GPIO34_FFUART_RXD
- GPIO34_GPIO
- GPIO34_KP_MKIN_3
- GPIO34_LCD_DD11
- GPIO34_MLCD_DD11
- GPIO34_MMC2_DAT1
- GPIO34_MMC_CS0
- GPIO34_SMC_nCS1
- GPIO34_SSP1_FRM
- GPIO34_SSP2_FRM
- GPIO34_SSP3_SCLK
- GPIO34_SSPA2_FRM
- GPIO34_UART1_DSR
- GPIO34_UART1_DTR
- GPIO34_ULPI_DATA_OUT_4
- GPIO34_USB_P2_2
- GPIO34_USB_P2_5
- GPIO34_USB_ULPI_D3
- GPIO34_USB_VM
- GPIO34_UTM_PHYDATA_4
- GPIO34_UTM_RXVALID
- GPIO35
- GPIO35_AC97_SDATA_IN_0
- GPIO35_FFUART_CTS
- GPIO35_GPIO
- GPIO35_KP_MKIN_5
- GPIO35_KP_MKOUT_6
- GPIO35_LCD_DD12
- GPIO35_MLCD_DD12
- GPIO35_MMC2_DAT2
- GPIO35_SMC_BE1
- GPIO35_SSP1_RXD
- GPIO35_SSP1_TXD
- GPIO35_SSP2_RXD
- GPIO35_SSP2_SCLK
- GPIO35_SSP2_TXD
- GPIO35_SSP3_SFRM
- GPIO35_SSP3_TXD
- GPIO35_SSPA2_TXD
- GPIO35_UART1_RI
- GPIO35_ULPI_DATA_OUT_5
- GPIO35_USB_P2_1
- GPIO35_USB_P2_3
- GPIO35_USB_ULPI_D4
- GPIO35_UTM_PHYDATA_5
- GPIO35_UTM_RXACTIVE
- GPIO35_VPAC270_PCMCIA_RDY
- GPIO36
- GPIO36_AC97_SDATA_IN_1
- GPIO36_FFUART_DCD
- GPIO36_GPIO
- GPIO36_KP_MKIN_7
- GPIO36_KP_MKOUT_5
- GPIO36_LCD_DD13
- GPIO36_MLCD_DD13
- GPIO36_MMC2_DAT3
- GPIO36_SMC_BE2
- GPIO36_SSP1_RXD
- GPIO36_SSP1_TXD
- GPIO36_SSP2_SCLK
- GPIO36_SSP2_SFRM
- GPIO36_SSP2_TXD
- GPIO36_SSPA2_RXD
- GPIO36_U2D_RXERROR
- GPIO36_UART1_DSR
- GPIO36_UART1_DTR
- GPIO36_ULPI_DATA_OUT_6
- GPIO36_USB_P2_1
- GPIO36_USB_P2_4
- GPIO36_USB_ULPI_D5
- GPIO36_UTM_PHYDATA_6
- GPIO36_VPAC270_IDE_IRQ
- GPIO36_ZIPITZ2_WIFI_IRQ
- GPIO36_nCD
- GPIO36_nCD_MD
- GPIO37
- GPIO37_AC97_SDATA_OUT
- GPIO37_FFUART_DSR
- GPIO37_FFUART_TXD
- GPIO37_GPIO
- GPIO37_KP_MKIN_3
- GPIO37_LCD_DD14
- GPIO37_MAGICIAN_KEY_HANGUP
- GPIO37_MLCD_DD14
- GPIO37_MMC1_DAT7
- GPIO37_MMC2_DAT3
- GPIO37_SSP2_RXD
- GPIO37_SSP2_SFRM
- GPIO37_SSP2_TXD
- GPIO37_U2D_OPMODE0
- GPIO37_UART1_CTS
- GPIO37_UART1_RTS
- GPIO37_ULPI_DATA_OUT_7
- GPIO37_USB_P2_8
- GPIO37_USB_ULPI_DIR
- GPIO37_UTM_PHYDATA_7
- GPIO37_WLAN_RST
- GPIO37_ZIPITZ2_HEADSET_DETECT
- GPIO38
- GPIO38_AC97_SYNC
- GPIO38_CLK26MOUT
- GPIO38_FFUART_RI
- GPIO38_GPIO
- GPIO38_KP_MKIN_4
- GPIO38_KP_MKOUT_5
- GPIO38_LCD_DD15
- GPIO38_MAGICIAN_KEY_CONTACTS
- GPIO38_MLCD_DD15
- GPIO38_MMC1_DAT6
- GPIO38_MMC2_DAT2
- GPIO38_PWM1_OUT
- GPIO38_SD_PWEN
- GPIO38_SSP2_RXD
- GPIO38_SSP2_TXD
- GPIO38_SSP3_TXD
- GPIO38_U2D_OPMODE1
- GPIO38_ULPI_CLK
- GPIO38_USB_P2_3
- GPIO38_USB_ULPI_CLK
- GPIO38_UTM_CLK
- GPIO39
- GPIO39_AC97_BITCLK
- GPIO39_CI2C_SCL
- GPIO39_CI_DD_0
- GPIO39_CLK13MOUTDMD
- GPIO39_FFUART_TXD
- GPIO39_GPIO
- GPIO39_KP_MKIN_4
- GPIO39_LCD_DD16
- GPIO39_MMC2_DAT1
- GPIO39_MMC_CS1
- GPIO39_SSP2_EXTCLK
- GPIO39_SSP3_SFRM
- GPIO39_U2D_TXVALID
- GPIO39_USB_P2_6
- GPIO39_USB_ULPI_STP
- GPIO39_USB_VPO
- GPIO39_UTM_PHYDATA_0
- GPIO3_2_GPIO
- GPIO3_2_KP_DKIN_1
- GPIO3_2_KP_DKIN_7
- GPIO3_2_KP_MKIN_7
- GPIO3_2_USBH_PWR
- GPIO3_ALT1
- GPIO3_CFG_MASK
- GPIO3_CFG_SHIFT
- GPIO3_CLK26MOUTDMD
- GPIO3_DATA
- GPIO3_DEB_MASK
- GPIO3_DEB_SHIFT
- GPIO3_DFI_D12
- GPIO3_DIR_INPUT
- GPIO3_GPIO
- GPIO3_INTERRUPT
- GPIO3_INTERRUPT_ENABLE
- GPIO3_INTMD
- GPIO3_KP_DKIN_6
- GPIO3_KP_MKOUT_1
- GPIO3_LED_SELECT
- GPIO3_MD
- GPIO3_MMC1_DAT0
- GPIO3_MSK
- GPIO3_OD
- GPIO3_ODEN_MASK
- GPIO3_ODEN_SHIFT
- GPIO3_OUTPUT_ENABLE
- GPIO3_PDEN_MASK
- GPIO3_PDEN_SHIFT
- GPIO3_PIN5_IN_SEL
- GPIO3_PIN_IN_SEL
- GPIO3_PIN_IN_SHIFT
- GPIO3_PIN_TO_BIT
- GPIO3_PUDEN
- GPIO3_PUDSEL
- GPIO3_SEL_MASK
- GPIO3_SEL_SHIFT
- GPIO3_SET_MASK
- GPIO3_SET_SHIFT
- GPIO3_SLEEP_MASK
- GPIO3_SLEEP_SHIFT
- GPIO3_STS_MASK
- GPIO3_STS_SHIFT
- GPIO3_nCS2
- GPIO3_uIO_IN
- GPIO4
- GPIO40
- GPIO40_AC97_nACRESET
- GPIO40_CI2C_SDA
- GPIO40_CI_DD_1
- GPIO40_CLK26MOUTDMD
- GPIO40_FFUART_DTR
- GPIO40_GPIO
- GPIO40_KP_MKOUT_6
- GPIO40_LCD_DD17
- GPIO40_MAGICIAN_GSM_OUT2
- GPIO40_MMC1_DAT1
- GPIO40_MMC2_DAT0
- GPIO40_SSP2_RXD
- GPIO40_SSP2_SYSCLK
- GPIO40_SSP3_SCLK
- GPIO40_USB_P2_5
- GPIO40_USB_ULPI_NXT
- GPIO40_UTM_PHYDATA_1
- GPIO41
- GPIO41_CI_DD_2
- GPIO41_ETHIRQ
- GPIO41_FFUART_RTS
- GPIO41_FFUART_RXD
- GPIO41_GPIO
- GPIO41_KP_DKIN_0
- GPIO41_KP_DKIN_4
- GPIO41_KP_MKOUT_7
- GPIO41_LCD_CS2
- GPIO41_MMC1_DAT0
- GPIO41_MMC2_CMD
- GPIO41_PWM0
- GPIO41_SSP3_RXD
- GPIO41_U2D_PHYDATA_0
- GPIO41_UART1_RXD
- GPIO41_UART1_TXD
- GPIO41_USB_P2_7
- GPIO41_USB_ULPI_D6
- GPIO41_UTM_PHYDATA_2
- GPIO41_VPAC270_UDC_DETECT
- GPIO42
- GPIO42_BTUART_RXD
- GPIO42_CIF_MCLK
- GPIO42_CI_DD_3
- GPIO42_FICP_RXD
- GPIO42_GPIO
- GPIO42_HWUART_RXD
- GPIO42_KP_DKIN_1
- GPIO42_KP_DKIN_5
- GPIO42_LCD_VSYNC2
- GPIO42_MMC2_CLK
- GPIO42_PWM1
- GPIO42_U2D_PHYDATA_1
- GPIO42_UART1_RXD
- GPIO42_UART1_TXD
- GPIO42_USB_ULPI_D7
- GPIO42_UTM_PHYDATA_3
- GPIO43
- GPIO43_BSSP4_CLK
- GPIO43_BTUART_TXD
- GPIO43_BTUART_TXD_LPM_LOW
- GPIO43_CIF_FV
- GPIO43_CI_DD_4
- GPIO43_FICP_TXD
- GPIO43_GPIO
- GPIO43_HWUART_TXD
- GPIO43_KP_DKIN_2
- GPIO43_MMC1_CLK
- GPIO43_PWM3
- GPIO43_TWSI2_SCL
- GPIO43_U2D_PHYDATA_2
- GPIO43_UART1_CTS
- GPIO43_UART1_RTS
- GPIO43_UART3_RTS
- GPIO43_UTM_PHYDATA_4
- GPIO44
- GPIO44_BSSP4_FRM
- GPIO44_BTUART_CTS
- GPIO44_CIF_LV
- GPIO44_CI_DD_5
- GPIO44_GPIO
- GPIO44_HWUART_CTS
- GPIO44_KP_DKIN_3
- GPIO44_LCD_DD7
- GPIO44_MLCD_DD7
- GPIO44_TWSI2_SDA
- GPIO44_U2D_PHYDATA_3
- GPIO44_UART1_DCD
- GPIO44_UART3_CTS
- GPIO44_UTM_PHYDATA_5
- GPIO45
- GPIO45_AC97_SYSCLK
- GPIO45_BSSP4_TXD
- GPIO45_BTUART_RTS
- GPIO45_BTUART_RTS_LPM_LOW
- GPIO45_CIF_PCLK
- GPIO45_CI_DD_6
- GPIO45_GPIO
- GPIO45_HWUART_RTS
- GPIO45_SSP3_SYSCLK
- GPIO45_U2D_PHYDATA_4
- GPIO45_UART1_DSR
- GPIO45_UART1_DTR
- GPIO45_UART1_RXD
- GPIO45_UART3_RXD
- GPIO45_UTM_PHYDATA_6
- GPIO46
- GPIO46_BSSP4_RXD
- GPIO46_CIR_OUT
- GPIO46_CI_DD_7
- GPIO46_FICP_RXD
- GPIO46_GPIO
- GPIO46_INDEX
- GPIO46_MMC1_WP
- GPIO46_PWM2_OUT
- GPIO46_STUART_RXD
- GPIO46_U2D_PHYDATA_5
- GPIO46_UART1_RI
- GPIO46_UART1_TXD
- GPIO46_UART3_TXD
- GPIO46_UTM_PHYDATA_7
- GPIO47
- GPIO47_CIF_DD_0
- GPIO47_CI_DD_8
- GPIO47_FICP_TXD
- GPIO47_GPIO
- GPIO47_GSSP2_CLK
- GPIO47_INDEX
- GPIO47_PWM3_OUT
- GPIO47_STUART_TXD
- GPIO47_U2D_PHYDATA_6
- GPIO47_UART1_DSR
- GPIO47_UART1_DSR_N
- GPIO47_UART1_DTR
- GPIO47_UART2_RXD
- GPIO47_USB_P2_4
- GPIO47_UTM_RXACTIVE
- GPIO48
- GPIO48_BB_OB_DAT_1
- GPIO48_CIF_DD_5
- GPIO48_CI_DD_9
- GPIO48_GPIO
- GPIO48_GSSP2_FRM
- GPIO48_HWUART_TXD
- GPIO48_MAGICIAN_UNKNOWN
- GPIO48_MMC1_DAT4
- GPIO48_U2D_PHYDATA_7
- GPIO48_UART1_CTS
- GPIO48_UART1_DTR_N
- GPIO48_UART1_RTS
- GPIO48_UART2_TXD
- GPIO48_USB_P2_7
- GPIO48_USB_P2_8
- GPIO48_UTM_RXVALID
- GPIO48_nPOE
- GPIO49
- GPIO49_48M_CLK
- GPIO49_CI_DD_0
- GPIO49_CI_MCLK
- GPIO49_GPIO
- GPIO49_GSSP2_RXD
- GPIO49_HWUART_RXD
- GPIO49_MMC1_CMD
- GPIO49_U2D_PHYDATA_0
- GPIO49_UART1_RI
- GPIO49_UART2_CTS
- GPIO49_USB_P2_2
- GPIO49_USB_P2_7
- GPIO49_UTM_RXACTIVE
- GPIO49_nPWE
- GPIO4_2_GPIO
- GPIO4_2_KP_DKIN_1
- GPIO4_2_KP_DKIN_7
- GPIO4_2_KP_MKOUT_5
- GPIO4_5
- GPIO4_CFG_MASK
- GPIO4_CFG_SHIFT
- GPIO4_DEB_MASK
- GPIO4_DEB_SHIFT
- GPIO4_DFI_D11
- GPIO4_GPIO
- GPIO4_INT
- GPIO4_KP_DKIN_4
- GPIO4_KP_DKIN_7
- GPIO4_KP_MKIN_2
- GPIO4_MMC1_DAT1
- GPIO4_ODEN_MASK
- GPIO4_ODEN_SHIFT
- GPIO4_PDEN_MASK
- GPIO4_PDEN_SHIFT
- GPIO4_SEL_MASK
- GPIO4_SEL_SHIFT
- GPIO4_SET_MASK
- GPIO4_SET_SHIFT
- GPIO4_SLEEP_MASK
- GPIO4_SLEEP_SHIFT
- GPIO4_STS_MASK
- GPIO4_STS_SHIFT
- GPIO4_nBVD1
- GPIO4_nCS3
- GPIO4_nSTSCHG
- GPIO4_nSTSCHG_MD
- GPIO4_uSIM_CARD_STATE
- GPIO5
- GPIO50
- GPIO50_BB_OB_DAT_2
- GPIO50_CIF_DD_3
- GPIO50_CI_DD_1
- GPIO50_CI_PCLK
- GPIO50_CLK13MOUTDMD
- GPIO50_GPIO
- GPIO50_GSSP2_TXD
- GPIO50_HWUART_CTS
- GPIO50_SSP2_SCLK
- GPIO50_U2D_PHYDATA_1
- GPIO50_U2D_RXERROR
- GPIO50_UART1_DCD
- GPIO50_UART2_RTS
- GPIO50_USB_P2_7
- GPIO50_nCAM_EN
- GPIO50_nPIOR
- GPIO51
- GPIO51_BB_OB_DAT_3
- GPIO51_BSSP4_CLK
- GPIO51_CI2C_SCL
- GPIO51_CIF_DD_2
- GPIO51_CI_DD_2
- GPIO51_CI_HSYNC
- GPIO51_GPIO
- GPIO51_HWUART_RTS
- GPIO51_IRDA_SHDN
- GPIO51_MMC1_DAT3
- GPIO51_PWM2_OUT
- GPIO51_U2D_OPMODE_0
- GPIO51_U2D_PHYDATA_2
- GPIO51_UART1_CTS
- GPIO51_UART3_RXD
- GPIO51_USB_P2_5
- GPIO51_nPIOW
- GPIO52
- GPIO52_BB_OB_CLK
- GPIO52_BSSP4_FRM
- GPIO52_CI2C_SDA
- GPIO52_CIF_DD_4
- GPIO52_CI_DD_3
- GPIO52_CI_VSYNC
- GPIO52_GPIO
- GPIO52_HX4700_CPU_nBATT_FAULT
- GPIO52_MMC1_DAT2
- GPIO52_SSP3_SCLK
- GPIO52_U2D_OPMODE_1
- GPIO52_U2D_PHYDATA_3
- GPIO52_U2D_TXVALID
- GPIO52_UART1_RTS
- GPIO52_UART3_TXD
- GPIO52_USB_P2_1
- GPIO52_VPAC270_SD_READONLY
- GPIO52_nPCE_1
- GPIO53
- GPIO53_BB_OB_STB
- GPIO53_BSSP4_TXD
- GPIO53_CI2C_SCL
- GPIO53_CIF_MCLK
- GPIO53_CI_DD_4
- GPIO53_FFUART_RXD
- GPIO53_GPIO
- GPIO53_KP_MKOUT_6
- GPIO53_MMC1_CD
- GPIO53_MMC_CLK
- GPIO53_SSP1_SYSCLK
- GPIO53_U2D_PHYDATA_4
- GPIO53_UART1_RXD
- GPIO53_UART1_TXD
- GPIO53_UART3_CTS
- GPIO53_USB_P2_3
- GPIO53_UTM_TXREADY
- GPIO53_VPAC270_SD_DETECT_N
- GPIO53_nPCE_2
- GPIO54
- GPIO54_BB_OB_WAIT
- GPIO54_BSSP4_RXD
- GPIO54_CI2C_SDA
- GPIO54_CIF_PCLK
- GPIO54_CI_DD_5
- GPIO54_GPIO
- GPIO54_INCOME_LED_A
- GPIO54_LCD_LDD_0
- GPIO54_MLCD_LDD_0
- GPIO54_MMC1_DAT5
- GPIO54_MMC_CLK
- GPIO54_U2D_PHYDATA_5
- GPIO54_UART1_RXD
- GPIO54_UART1_TXD
- GPIO54_UART3_RTS
- GPIO54_USB_P2_6
- GPIO54_nPCE_2
- GPIO54_nPSKTSEL
- GPIO55
- GPIO55_BB_IB_DAT_1
- GPIO55_CIF_DD_1
- GPIO55_CI_DD_6
- GPIO55_GPIO
- GPIO55_INCOME_LED_B
- GPIO55_LCD_LDD_1
- GPIO55_MLCD_LDD_1
- GPIO55_MMC1_CMD
- GPIO55_U2D_PHYDATA_6
- GPIO55_nPREG
- GPIO56
- GPIO56_BB_IB_DAT_2
- GPIO56_CI_DD_7
- GPIO56_GPIO
- GPIO56_LCD_FCLK_RD
- GPIO56_LCD_LDD_2
- GPIO56_MAGICIAN_UNKNOWN
- GPIO56_MLCD_LDD_2
- GPIO56_MMC1_CLK
- GPIO56_MT9M111_nOE
- GPIO56_NAND_RB
- GPIO56_U2D_PHYDATA_7
- GPIO56_USB_P3_4
- GPIO56_USB_VMO
- GPIO56_nPWAIT
- GPIO57
- GPIO57_BB_IB_DAT_3
- GPIO57_CI_DD_8
- GPIO57_GPIO
- GPIO57_LCD_LCLK_A0
- GPIO57_LCD_LDD_3
- GPIO57_MAGICIAN_CAM_RESET
- GPIO57_MLCD_LDD_3
- GPIO57_MMC1_DAT0
- GPIO57_SSP1_TXD
- GPIO57_USB_nOE
- GPIO57_nIOIS16
- GPIO58
- GPIO58_CI_DD_9
- GPIO58_GPIO
- GPIO58_HX4700_TSC2046_nPENIRQ
- GPIO58_LCD_LDD_0
- GPIO58_LCD_LDD_4
- GPIO58_LCD_PCLK_WR
- GPIO58_MLCD_LDD_4
- GPIO58_MMC1_DAT1
- GPIO58_UTM_RXVALID
- GPIO59
- GPIO59_CCIC_IN7
- GPIO59_CI_MCLK
- GPIO59_GPIO
- GPIO59_HX4700_LCD_PC1
- GPIO59_LCD_DENA_BIAS
- GPIO59_LCD_LDD_1
- GPIO59_LCD_LDD_5
- GPIO59_MLCD_LDD_5
- GPIO59_MMC1_DAT2
- GPIO59_UTM_RXACTIVE
- GPIO5_2_GPIO
- GPIO5_2_KP_DKIN_0
- GPIO5_2_KP_MKOUT_6
- GPIO5_2_KP_MKOUT_7
- GPIO5_DFI_D10
- GPIO5_GPIO
- GPIO5_KP_DKIN_5
- GPIO5_KP_MKIN_0
- GPIO5_KP_MKOUT_2
- GPIO5_MMC1_DAT0
- GPIO5_MMC1_DAT2
- GPIO5_MMC2_DAT0
- GPIO5_NPIOR
- GPIO5_uSIM_uCLK
- GPIO6
- GPIO60
- GPIO60_CCIC_IN6
- GPIO60_CI_PCLK
- GPIO60_GPIO
- GPIO60_HX4700_CF_RNB
- GPIO60_LCD_DD0
- GPIO60_LCD_LDD_2
- GPIO60_LCD_LDD_6
- GPIO60_MLCD_LDD_6
- GPIO60_MMC1_DAT3
- GPIO60_U2D_RXERROR
- GPIO61
- GPIO61_CCIC_IN5
- GPIO61_CI_HSYNC
- GPIO61_GPIO
- GPIO61_HX4700_W3220_nRESET
- GPIO61_LCD_DD1
- GPIO61_LCD_LDD_3
- GPIO61_LCD_LDD_7
- GPIO61_MLCD_LDD_7
- GPIO61_U2D_OPMODE0
- GPIO62
- GPIO62_CCIC_IN4
- GPIO62_CI_VSYNC
- GPIO62_GPIO
- GPIO62_HX4700_LCD_nRESET
- GPIO62_LCD_CS_N
- GPIO62_LCD_DD2
- GPIO62_LCD_LDD_4
- GPIO62_LCD_LDD_8
- GPIO62_MLCD_LDD_8
- GPIO62_U2D_OPMODE1
- GPIO63
- GPIO63_CCIC_IN3
- GPIO63_CI2C_SCL
- GPIO63_CI_DD_9
- GPIO63_GPIO
- GPIO63_HX4700_CPU_SS_nRESET
- GPIO63_LCD_CS_N
- GPIO63_LCD_DD3
- GPIO63_LCD_LDD_5
- GPIO63_LCD_LDD_8
- GPIO63_LCD_LDD_9
- GPIO63_LCD_VSYNC
- GPIO63_MLCD_DD_8
- GPIO63_MLCD_LDD_9
- GPIO63_UART1_TXD
- GPIO63_USB_P2_8
- GPIO64
- GPIO64_CCIC_IN2
- GPIO64_CI2C_SDA
- GPIO64_CI_DD_8
- GPIO64_GPIO
- GPIO64_LCD_DD4
- GPIO64_LCD_LDD_10
- GPIO64_LCD_LDD_6
- GPIO64_LCD_LDD_9
- GPIO64_LCD_VSYNC
- GPIO64_MLCD_DD_9
- GPIO64_MLCD_LDD_10
- GPIO64_SSP2_SCLK
- GPIO64_U2D_XCVR_SEL
- GPIO64_UART1_RXD
- GPIO64_USB_P2_7
- GPIO65
- GPIO65_CCIC_IN1
- GPIO65_CI_DD_7
- GPIO65_GPIO
- GPIO65_HX4700_TSC2046_PEN_PU
- GPIO65_LCD_DD5
- GPIO65_LCD_LDD_10
- GPIO65_LCD_LDD_11
- GPIO65_LCD_LDD_7
- GPIO65_MLCD_DD_10
- GPIO65_MLCD_LDD_11
- GPIO65_SSP2_FRM
- GPIO65_U2D_TERM_SEL
- GPIO65_U2D_XCVR_SEL
- GPIO65_UART1_DSR
- GPIO65_USB_P2_6
- GPIO66
- GPIO66_CCIC_IN0
- GPIO66_CI_DD_6
- GPIO66_GPIO
- GPIO66_HX4700_ASIC3_nSDIO_IRQ
- GPIO66_LCD_DD6
- GPIO66_LCD_LDD_11
- GPIO66_LCD_LDD_12
- GPIO66_LCD_LDD_8
- GPIO66_MBREQ
- GPIO66_MLCD_DD_11
- GPIO66_MLCD_LDD_12
- GPIO66_SSP2_RXD
- GPIO66_SSP2_TXD
- GPIO66_U2D_SUSPEND
- GPIO66_U2D_TERM_SEL
- GPIO66_UART1_DTR
- GPIO66_USG_P2_5
- GPIO67
- GPIO67_CAM_HSYNC
- GPIO67_CCIC_IN7
- GPIO67_CI_DD_5
- GPIO67_GPIO
- GPIO67_HX4700_EUART_PS
- GPIO67_LCD_DD7
- GPIO67_LCD_LDD_12
- GPIO67_LCD_LDD_13
- GPIO67_LCD_LDD_9
- GPIO67_MLCD_DD_12
- GPIO67_MLCD_LDD_13
- GPIO67_MMC_CS0
- GPIO67_SSP2_RXD
- GPIO67_SSP2_TXD
- GPIO67_U2D_SUSPEND
- GPIO67_UART1_RI
- GPIO67_USB_P2_4
- GPIO67_UTM_LINESTATE_0
- GPIO68
- GPIO68_CAM_VSYNC
- GPIO68_CCIC_IN6
- GPIO68_CI_DD_4
- GPIO68_GPIO
- GPIO68_LCD_DD8
- GPIO68_LCD_LDD_10
- GPIO68_LCD_LDD_13
- GPIO68_LCD_LDD_14
- GPIO68_MLCD_DD_13
- GPIO68_MLCD_LDD_14
- GPIO68_MMC_CS1
- GPIO68_SSP3_SCLK
- GPIO68_UART1_DCD
- GPIO68_USB_P2_3
- GPIO68_UTM_LINESTATE_0
- GPIO68_UTM_LINESTATE_1
- GPIO69
- GPIO69_CAM_MCLK
- GPIO69_CCIC_IN5
- GPIO69_CI_DD_3
- GPIO69_GPIO
- GPIO69_GSSP2_CLK
- GPIO69_LCD_DD9
- GPIO69_LCD_LDD_11
- GPIO69_LCD_LDD_14
- GPIO69_LCD_LDD_15
- GPIO69_MLCD_DD_14
- GPIO69_MLCD_LDD_15
- GPIO69_MMC_CLK
- GPIO69_SSP3_FRM
- GPIO69_SSP3_SCLK
- GPIO69_U2D_TXVALID
- GPIO69_UART1_CTS
- GPIO69_USB_P2_2
- GPIO69_UTM_LINESTATE_1
- GPIO6C6_SEL_WRITE_ENABLE
- GPIO6_2_GPIO
- GPIO6_2_KP_MKOUT_7
- GPIO6_2_LCD_LDD_0
- GPIO6_2_MLCD_DD_0
- GPIO6_DFI_D9
- GPIO6_GPIO
- GPIO6_KP_DKIN_6
- GPIO6_KP_MKIN_1
- GPIO6_KP_MKIN_3
- GPIO6_MMC1_DAT1
- GPIO6_MMC1_DAT3
- GPIO6_MMC2_DAT1
- GPIO6_MMC_CLK
- GPIO6_NPIOW
- GPIO6_uSIM_uRST
- GPIO7
- GPIO70
- GPIO70_CAM_PCLK
- GPIO70_CCIC_IN4
- GPIO70_CI_DD_2
- GPIO70_GPIO
- GPIO70_GSSP2_FRM
- GPIO70_HX4700_LCD_SLIN1
- GPIO70_KP_MKIN_6
- GPIO70_LCD_DD10
- GPIO70_LCD_LDD_12
- GPIO70_LCD_LDD_15
- GPIO70_LCD_LDD_16
- GPIO70_MLCD_DD_15
- GPIO70_RTCCLK
- GPIO70_SSP3_FRM
- GPIO70_SSP3_RXD
- GPIO70_SSP3_TXD
- GPIO70_U2D_TXVALID
- GPIO70_UART1_RTS
- GPIO70_USB_P2_1
- GPIO71
- GPIO71_3_6MHz
- GPIO71_CCIC_IN3
- GPIO71_CI_DD_1
- GPIO71_EXT_MATCH_MVT
- GPIO71_GPIO
- GPIO71_GSSP2_RXD
- GPIO71_HX4700_ASIC3_nRESET
- GPIO71_KP_MKIN_7
- GPIO71_LCD_DD11
- GPIO71_LCD_LDD_13
- GPIO71_LCD_LDD_16
- GPIO71_LCD_LDD_17
- GPIO71_MLCD_DD_16
- GPIO71_SSP3_RXD
- GPIO71_SSP3_TXD
- GPIO71_TWSI3_SCL
- GPIO72
- GPIO72_32kHz
- GPIO72_CCIC_IN2
- GPIO72_CI_DD_0
- GPIO72_GPIO
- GPIO72_GSSP2_TXD
- GPIO72_HX4700_BQ24022_nCHARGE_EN
- GPIO72_LCD_DD12
- GPIO72_LCD_FCLK
- GPIO72_LCD_LDD_14
- GPIO72_LCD_LDD_17
- GPIO72_MLCD_DD_17
- GPIO72_MLCD_FCLK
- GPIO72_SSP3_RXD
- GPIO72_SSP3_TXD
- GPIO72_TWSI3_SDA
- GPIO73
- GPIO73_CCIC_IN1
- GPIO73_CI2C_SCL
- GPIO73_CI_HSYNC
- GPIO73_GPIO
- GPIO73_HX4700_LCD_UD_1
- GPIO73_LCD_CS_N
- GPIO73_LCD_DD13
- GPIO73_LCD_LCLK
- GPIO73_LCD_LDD_15
- GPIO73_MBGNT
- GPIO73_MLCD_CS
- GPIO73_MLCD_LCLK
- GPIO73_UTM_TXREADY
- GPIO74
- GPIO74_CCIC_IN0
- GPIO74_CI2C_SDA
- GPIO74_CI_VSYNC
- GPIO74_GPIO
- GPIO74_LCD_DD14
- GPIO74_LCD_FCLK
- GPIO74_LCD_PCLK
- GPIO74_LCD_VSYNC
- GPIO74_MLCD_PCLK
- GPIO74_MLCD_VSYNC
- GPIO74_PWM4_OUT
- GPIO74_U2D_RESET
- GPIO75
- GPIO75_CAM_HSYNC
- GPIO75_CI_MCLK
- GPIO75_GPIO
- GPIO75_HX4700_EARPHONE_nDET
- GPIO75_LCD_BIAS
- GPIO75_LCD_DD15
- GPIO75_LCD_LCLK
- GPIO75_MAGICIAN_SAMSUNG_POWER
- GPIO75_MLCD_BIAS
- GPIO75_MMC2_DAT0
- GPIO75_PWM3_OUT
- GPIO75_UART1_RXD
- GPIO75_UART3_RTS
- GPIO75_USB_P3_1
- GPIO76
- GPIO76_CAM_VSYNC
- GPIO76_CI_PCLK
- GPIO76_GPIO
- GPIO76_HX4700_USBC_PUEN
- GPIO76_LCD_DD16
- GPIO76_LCD_PCLK
- GPIO76_LCD_VSYNC
- GPIO76_MMC2_DAT1
- GPIO76_PWM2_OUT
- GPIO76_U2D_RESET
- GPIO76_UART1_RXD
- GPIO76_UART1_TXD
- GPIO76_UART3_CTS
- GPIO76_USB_P3_2
- GPIO77
- GPIO77_BT_UNKNOWN1
- GPIO77_CAM_MCLK
- GPIO77_CI2C_SCL
- GPIO77_CIR_OUT
- GPIO77_GPIO
- GPIO77_LCD_BIAS
- GPIO77_LCD_DD17
- GPIO77_LCD_DENA
- GPIO77_MMC2_DAT0
- GPIO77_MMC2_DAT2
- GPIO77_PWM1_OUT
- GPIO77_UART1_CTS
- GPIO77_UART1_RXD
- GPIO77_UART1_TXD
- GPIO77_UART3_TXD
- GPIO77_USB_P3_1
- GPIO77_USB_P3_3
- GPIO78
- GPIO78_CAM_PCLK
- GPIO78_CI2C_SDA
- GPIO78_GPIO
- GPIO78_KP_MKOUT_7
- GPIO78_LCD_DD0
- GPIO78_LCD_DD18
- GPIO78_MMC2_DAT1
- GPIO78_MMC2_DAT3
- GPIO78_SDIO_RO
- GPIO78_UART1_DCD
- GPIO78_UART1_RXD
- GPIO78_UART1_TXD
- GPIO78_UART3_RXD
- GPIO78_USB_P3_2
- GPIO78_USB_P3_4
- GPIO78_nCS_2
- GPIO78_nPCE_2
- GPIO79
- GPIO79_BSSP3_CLK
- GPIO79_GPIO
- GPIO79_GSSP1_CLK
- GPIO79_LCD_DD1
- GPIO79_LCD_DD19
- GPIO79_MMC2_CLK
- GPIO79_MMC2_DAT2
- GPIO79_PSKTSEL
- GPIO79_PWM2_OUT
- GPIO79_UART1_CTS
- GPIO79_UART1_DSR
- GPIO79_UART1_RTS
- GPIO79_USB_P3_3
- GPIO79_USB_P3_5
- GPIO79_nCS_3
- GPIO7_2_GPIO
- GPIO7_2_LCD_LDD_1
- GPIO7_2_MLCD_DD_1
- GPIO7_2_MMC3_DAT0
- GPIO7_48MHz
- GPIO7_CLK_BYPASS_XSC
- GPIO7_DFI_D8
- GPIO7_GPIO
- GPIO7_KP_DKIN_7
- GPIO7_KP_MKOUT_3
- GPIO7_KP_MKOUT_5
- GPIO7_MMC1_CLK
- GPIO7_MMC1_DAT2
- GPIO7_MMC2_DAT2
- GPIO7_NPIOS16
- GPIO7_UART3_RXD
- GPIO7_UART3_TXD
- GPIO8
- GPIO80
- GPIO80_BSSP3_FRM
- GPIO80_DREQ_1
- GPIO80_GPIO
- GPIO80_GSSP1_FRM
- GPIO80_LCD_DD2
- GPIO80_LCD_DD20
- GPIO80_MAYBE_CHARGE_VDROP
- GPIO80_MBREQ
- GPIO80_MMC2_CMD
- GPIO80_MMC2_DAT3
- GPIO80_PWM3_OUT
- GPIO80_UART1_DCD
- GPIO80_UART1_RI
- GPIO80_USB_P3_4
- GPIO80_USB_P3_6
- GPIO80_nCS_4
- GPIO81
- GPIO81_BB_OB_DAT_0
- GPIO81_BSSP3_TXD
- GPIO81_CIF_DD_0
- GPIO81_GPIO
- GPIO81_GSSP1_TXD
- GPIO81_HX4700_CPU_GP_nRESET
- GPIO81_LCD_DD21
- GPIO81_LCD_DD3
- GPIO81_LCD_FCLK
- GPIO81_MMC2_CLK
- GPIO81_SSP2_CLK_IN
- GPIO81_SSP2_CLK_OUT
- GPIO81_SSP3_TXD
- GPIO81_UART1_DSR
- GPIO81_UART1_DTR
- GPIO81_USB_P3_5
- GPIO81_VPAC270_BKL_ON
- GPIO82
- GPIO82_BB_IB_DAT_0
- GPIO82_BSSP3_RXD
- GPIO82_CIF_DD_5
- GPIO82_FFUART_DTR
- GPIO82_GPIO
- GPIO82_GSSP1_RXD
- GPIO82_HX4700_EUART_RESET
- GPIO82_LCD_A0
- GPIO82_LCD_DD22
- GPIO82_LCD_DD4
- GPIO82_LCD_LCLK
- GPIO82_LED_nVibra
- GPIO82_MMC2_CMD
- GPIO82_MMC_IRQ
- GPIO82_PWM4_OUT
- GPIO82_SSP2_FRM_IN
- GPIO82_SSP2_FRM_OUT
- GPIO82_SSP3_RXD
- GPIO82_UART1_CTS
- GPIO82_UART1_RI
- GPIO82_UART1_RTS
- GPIO82_USB_P3_6
- GPIO83
- GPIO83_BAC97_SYSCLK
- GPIO83_BB_IB_CLK
- GPIO83_BSSP3_SYSCLK
- GPIO83_BT_ON
- GPIO83_CIF_DD_4
- GPIO83_FFUART_RTS
- GPIO83_FFUART_TXD
- GPIO83_GPIO
- GPIO83_GSSP1_SYSCLK
- GPIO83_HX4700_WLAN_nRESET
- GPIO83_KP_DKIN_0
- GPIO83_KP_DKIN_2
- GPIO83_KP_MKOUT_0
- GPIO83_LCD_DD23
- GPIO83_LCD_DD5
- GPIO83_LCD_PCLK
- GPIO83_LCD_WR
- GPIO83_MAGICIAN_nIR_EN
- GPIO83_MMC_IRQ
- GPIO83_PWM3_OUT
- GPIO83_SSP1_SCLK
- GPIO83_SSP2_RXD
- GPIO83_SSP2_TXD
- GPIO83_SSP3_SFRM
- GPIO83_U2D_TXVALID
- GPIO83_UART1_DSR
- GPIO83_UART1_DTR
- GPIO83_VPAC270_NL_ON
- GPIO83_ZIPITZ2_LED_CHARGING
- GPIO84
- GPIO84_BAC97_SDATA_IN0
- GPIO84_BB_IB_STB
- GPIO84_BSSP2_SDATA_IN
- GPIO84_CIF_FV
- GPIO84_GPIO
- GPIO84_GSSP2_RXD
- GPIO84_HX4700_LCD_SQN
- GPIO84_KP_DKIN_1
- GPIO84_KP_MKOUT_1
- GPIO84_LCD_CS
- GPIO84_LCD_DD6
- GPIO84_LCD_DENA
- GPIO84_PWM1_OUT
- GPIO84_PWM2_OUT
- GPIO84_SSP1_SFRM
- GPIO84_SSP2_RXD
- GPIO84_SSP2_TXD
- GPIO84_SSP3_SCLK
- GPIO84_UART1_CTS
- GPIO84_UART1_RTS
- GPIO84_VPAC270_PCMCIA_CD
- GPIO85
- GPIO85_BAC97_BITCLK
- GPIO85_BB_IB_WAIT
- GPIO85_BSSP2_BITCLK
- GPIO85_CIF_LV
- GPIO85_DREQ_2
- GPIO85_FFUART_RXD
- GPIO85_GPIO
- GPIO85_GSSP2_CLK
- GPIO85_HX4700_nPCE1
- GPIO85_KP_DKIN_0
- GPIO85_KP_DKIN_2
- GPIO85_KP_MKOUT_0
- GPIO85_KP_MKOUT_2
- GPIO85_LCD_DD0
- GPIO85_LCD_DD7
- GPIO85_LCD_VSYNC
- GPIO85_MMC_WP
- GPIO85_PWM1_OUT
- GPIO85_SSP1_RXD
- GPIO85_SSP1_SCLK
- GPIO85_SSP1_TXD
- GPIO85_U2D_TXVALID
- GPIO85_UTM_RXVALID
- GPIO85_ZIPITZ2_LED_CHARGED
- GPIO85_nPCE_1
- GPIO86
- GPIO86_BAC97_nRESET
- GPIO86_BSSP2_SDATA_IN
- GPIO86_BSSP2_SYSCLK
- GPIO86_BT_MAYBE_nRESET
- GPIO86_GPIO
- GPIO86_GSSP2_RXD
- GPIO86_GSSP2_SYSCLK
- GPIO86_KP_DKIN_1
- GPIO86_KP_DKIN_3
- GPIO86_KP_MKOUT_1
- GPIO86_KP_MKOUT_3
- GPIO86_LCD_DD1
- GPIO86_LCD_DD8
- GPIO86_LCD_LDD_16
- GPIO86_MAGICIAN_GSM_RESET
- GPIO86_PWM1_OUT
- GPIO86_PWM2_OUT
- GPIO86_SSP1_FRM
- GPIO86_SSP1_RXD
- GPIO86_SSP1_TXD
- GPIO86_SSP2_RXD
- GPIO86_TX_CLK
- GPIO86_USB_P3_5
- GPIO86_UTM_RXACTIVE
- GPIO86_nPCE_1
- GPIO86_nSDCS2
- GPIO87
- GPIO87_BAC97_SYNC
- GPIO87_BSSP2_SYNC
- GPIO87_GPIO
- GPIO87_GSSP2_FRM
- GPIO87_KP_DKIN_2
- GPIO87_KP_MKOUT_2
- GPIO87_LCD_DD2
- GPIO87_LCD_DD9
- GPIO87_LCD_LDD_17
- GPIO87_LCD_POWER
- GPIO87_MAGICIAN_GSM_SELECT
- GPIO87_SSP1_EXTCLK
- GPIO87_SSP1_RXD
- GPIO87_SSP1_TXD
- GPIO87_SSP2_SFRM
- GPIO87_SSP2_TXD
- GPIO87_TX_EN
- GPIO87_U2D_RXERROR
- GPIO87_USB_P3_1
- GPIO87_UTM_RXVALID
- GPIO87_nPCE_2
- GPIO87_nSDCS3
- GPIO88
- GPIO88_BAC97_SDATA_OUT
- GPIO88_BSSP2_DATA_OUT
- GPIO88_GPIO
- GPIO88_GSM_nMOD_ON_CMD
- GPIO88_GSSP2_TXD
- GPIO88_HX4700_TSC2046_CS
- GPIO88_KP_DKIN_3
- GPIO88_KP_MKOUT_3
- GPIO88_LCD_DD10
- GPIO88_LCD_DD3
- GPIO88_RDnWR
- GPIO88_SSP1_RXD
- GPIO88_SSP1_SYSCLK
- GPIO88_SSP1_TXD
- GPIO88_SSP2_RXD
- GPIO88_SSP2_SFRM
- GPIO88_TX_DQ3
- GPIO88_U2D_OPMODE0
- GPIO88_UART2_TXD
- GPIO88_USBH1_PWR
- GPIO88_UTM_RXACTIVE
- GPIO88_ZIPITZ2_LCD_CS
- GPIO89_AC97_SYSCLK
- GPIO89_AC97_nRESET
- GPIO89_CI2C_SCL
- GPIO89_FFUART_RI
- GPIO89_GPIO
- GPIO89_KP_DKIN_3
- GPIO89_LCD_DD11
- GPIO89_LCD_DD4
- GPIO89_SSP1_EXTCLK
- GPIO89_SSP2_TXD
- GPIO89_SSP3_RXD
- GPIO89_SSP3_SCLK
- GPIO89_TX_DQ2
- GPIO89_U2D_RXERROR
- GPIO89_UART2_RXD
- GPIO89_UART3_CTS
- GPIO89_UART3_RTS
- GPIO89_USBH1_PEN
- GPIO8_2_GPIO
- GPIO8_2_LCD_LDD_2
- GPIO8_2_MLCD_DD_2
- GPIO8_2_MMC3_DAT1
- GPIO8_CIR_OUT
- GPIO8_DFI_D7
- GPIO8_GPIO
- GPIO8_KP_DKIN_4
- GPIO8_KP_MKIN_4
- GPIO8_MMC1_CMD
- GPIO8_MMC1_DAT3
- GPIO8_MMC2_DAT3
- GPIO8_MMC_CS0
- GPIO8_NPWAIT
- GPIO8_RESET
- GPIO8_RESET_MD
- GPIO8_UART3_RXD
- GPIO8_UART3_TXD
- GPIO9
- GPIO90_CI2C_SDA
- GPIO90_CIF_DD_4
- GPIO90_GPIO
- GPIO90_GSM_nMOD_OFF_CMD
- GPIO90_KP_MKIN_5
- GPIO90_LCD_DD12
- GPIO90_LCD_DD5
- GPIO90_MAGICIAN_KEY_CALENDAR
- GPIO90_SSP1_SYSCLK
- GPIO90_SSP3_FRM
- GPIO90_TX_DQ1
- GPIO90_U2D_OPMODE_0
- GPIO90_UART3_CTS
- GPIO90_UART3_RTS
- GPIO90_USB_P3_5
- GPIO90_UTM_LINESTATE_0
- GPIO90_nURST
- GPIO91_CIF_DD_5
- GPIO91_GPIO
- GPIO91_HX4700_FLASH_VPEN
- GPIO91_KP_MKIN_6
- GPIO91_LCD_DD13
- GPIO91_LCD_DD6
- GPIO91_MAGICIAN_KEY_CAMERA
- GPIO91_SDIO_EN
- GPIO91_SSP3_RXD
- GPIO91_SSP3_SCLK
- GPIO91_SSP3_TXD
- GPIO91_TX_DQ0
- GPIO91_UART2_RXD
- GPIO91_UART3_CTS
- GPIO91_UART3_RTS
- GPIO91_UART3_RXD
- GPIO91_UART3_TXD
- GPIO91_UCLK
- GPIO91_USB_P3_1
- GPIO91_UTM_LINESTATE_1
- GPIO92_CLK26MOUT
- GPIO92_GPIO
- GPIO92_HX4700_HP_DRIVER
- GPIO92_LCD_DD14
- GPIO92_LCD_DD7
- GPIO92_MII_CRS
- GPIO92_MMC_DAT_0
- GPIO92_MSBS
- GPIO92_SSP3_FRM
- GPIO92_SSP3_RXD
- GPIO92_SSP3_TXD
- GPIO92_UART2_TXD
- GPIO92_UART3_CTS
- GPIO92_UART3_RTS
- GPIO92_UART3_RXD
- GPIO92_UART3_TXD
- GPIO92_UTM_LINESTATE_0
- GPIO93_AC97_SDATA_OUT
- GPIO93_CAM_RESET
- GPIO93_CIF_DD_6
- GPIO93_CLK13MOUTDMD
- GPIO93_GPIO
- GPIO93_GSSP1_CLK
- GPIO93_HX4700_EUART_INT
- GPIO93_KEY_VOLUME_UP
- GPIO93_KP_DKIN_0
- GPIO93_LCD_DD15
- GPIO93_LCD_DD8
- GPIO93_MAGICIAN_KEY_UP
- GPIO93_MII_COL
- GPIO93_SSP3_RXD
- GPIO93_SSP3_TXD
- GPIO93_SSP4_SCLK
- GPIO93_U2D_RESET
- GPIO93_UART2_CTS
- GPIO93_UART3_RXD
- GPIO93_UART3_TXD
- GPIO93_UTM_LINESTATE_1
- GPIO94_AC97_SYNC
- GPIO94_CIF_DD_5
- GPIO94_CLK26MOUTDMD
- GPIO94_GPIO
- GPIO94_GSSP1_FRM
- GPIO94_HX4700_KEY_MAIL
- GPIO94_KEY_VOLUME_DOWN
- GPIO94_KP_DKIN_1
- GPIO94_LCD_DD16
- GPIO94_LCD_DD9
- GPIO94_MAGICIAN_KEY_DOWN
- GPIO94_RX_CLK
- GPIO94_SPI_DCLK
- GPIO94_SSP3_RXD
- GPIO94_SSP3_TXD
- GPIO94_SSP4_FRM
- GPIO94_SSP4_RXD
- GPIO94_U2D_XCVR_SEL
- GPIO94_UART2_RTS
- GPIO94_UART3_RXD
- GPIO94_UART3_TXD
- GPIO95_AC97_nRESET
- GPIO95_AC97_nRESET_GPIO_HIGH
- GPIO95_CI2C_SCL
- GPIO95_CIF_DD_4
- GPIO95_GPIO
- GPIO95_GSSP1_TXD
- GPIO95_HX4700_BATT_OFF
- GPIO95_KP_DKIN_2
- GPIO95_KP_MKIN_6
- GPIO95_LCD_DD10
- GPIO95_LCD_DD17
- GPIO95_MAGICIAN_KEY_LEFT
- GPIO95_MMC_WP
- GPIO95_OW_DQ_IN
- GPIO95_RTC_CS
- GPIO95_RX_ER
- GPIO95_SPI_CS0
- GPIO95_SSP4_RXD
- GPIO95_SSP4_SCLK
- GPIO95_SSP4_TXD
- GPIO95_TOUCHPAD_INT
- GPIO95_U2D_RESET
- GPIO95_U2D_TERM_SEL
- GPIO96_AC_DETECT
- GPIO96_CI2C_SDA
- GPIO96_DVAL_1
- GPIO96_FFUART_RXD
- GPIO96_GPIO
- GPIO96_GSSP1_RXD
- GPIO96_HX4700_BQ24022_ISET2
- GPIO96_KP_DKIN_3
- GPIO96_KP_MKOUT_6
- GPIO96_LCD_DD11
- GPIO96_LCD_DD18
- GPIO96_MAGICIAN_KEY_RIGHT
- GPIO96_MBREQ
- GPIO96_PWM3_OUT
- GPIO96_RTC_WR
- GPIO96_RX_DQ3
- GPIO96_SPI_DIN
- GPIO96_SSP4_FRM
- GPIO96_SSP4_RXD
- GPIO96_SSP4_TXD
- GPIO96_U2D_SUSPEND
- GPIO96_U2D_XCVR_SEL
- GPIO96_ZIPITZ2_SD_DETECT
- GPIO97_BSSP1_CLK
- GPIO97_CI2C_SCL
- GPIO97_DREQ_1
- GPIO97_GPIO
- GPIO97_HX4700_nBL_DETECT
- GPIO97_KP_DKIN_4
- GPIO97_KP_MKIN_3
- GPIO97_LCD_DD12
- GPIO97_LCD_DD19
- GPIO97_LED_nBlue
- GPIO97_MAGICIAN_KEY_ENTER
- GPIO97_MBGNT
- GPIO97_PWM2_OUT
- GPIO97_RTC_RD
- GPIO97_RX_DQ2
- GPIO97_SPI_DOUT
- GPIO97_SSP4_RXD
- GPIO97_SSP4_TXD
- GPIO97_TWSI6_SCL
- GPIO97_U2D_TERM_SEL
- GPIO97_UART1_RXD
- GPIO97_UART1_TXD
- GPIO97_USB_P2_2
- GPIO97_USB_P2_6
- GPIO98_AC97_SYSCLK
- GPIO98_BSSP1_FRM
- GPIO98_CI2C_SDA
- GPIO98_CIF_DD_0
- GPIO98_FFUART_RTS
- GPIO98_GPIO
- GPIO98_KP_DKIN_5
- GPIO98_KP_MKIN_4
- GPIO98_LCD_DD13
- GPIO98_LCD_DD20
- GPIO98_LCD_RST
- GPIO98_LED_nOrange
- GPIO98_MAGICIAN_KEY_RECORD
- GPIO98_PWM1_OUT
- GPIO98_RTC_IO
- GPIO98_RX_DQ1
- GPIO98_SSP4_RXD
- GPIO98_SSP4_TXD
- GPIO98_TWSI6_SDA
- GPIO98_U2D_RESET
- GPIO98_U2D_SUSPEND
- GPIO98_UART1_RXD
- GPIO98_UART1_TXD
- GPIO98_USB_P2_2
- GPIO98_USB_P2_6
- GPIO98_ZIPITZ2_LID_BUTTON
- GPIO99_AC97_SDATA_IN_1
- GPIO99_FFUART_TXD
- GPIO99_GPIO
- GPIO99_HX4700_KEY_CONTACTS
- GPIO99_KP_DKIN_6
- GPIO99_KP_MKIN_5
- GPIO99_LCD_DD21
- GPIO99_MAGICIAN_HEADPHONE_IN
- GPIO99_RX_DQ0
- GPIO99_TWSI5_SCL
- GPIO99_U2D_XCVR_SEL
- GPIO99_UART1_CTS
- GPIO99_UART1_RTS
- GPIO99_UART1_RXD
- GPIO99_UART1_TXD
- GPIO99_USB_P2_1
- GPIO99_USB_P2_2
- GPIO99_USB_P2_5
- GPIO99_USB_P2_6
- GPIO9_2_GPIO
- GPIO9_2_LCD_LDD_3
- GPIO9_2_MLCD_DD_3
- GPIO9_2_MMC3_DAT2
- GPIO9_CHARGE_EN
- GPIO9_CHOUT_0
- GPIO9_DFI_D6
- GPIO9_FFUART_CTS
- GPIO9_GPIO
- GPIO9_HZ_CLK
- GPIO9_KP_DKIN_5
- GPIO9_KP_MKIN_6
- GPIO9_KP_MKOUT_4
- GPIO9_MAGICIAN_UNKNOWN
- GPIO9_MMC1_CMD
- GPIO9_MMC2_DAT0
- GPIO9_MMC_CS1
- GPIO9_SCIO
- GPIO9_UART3_RXD
- GPIO9_USB_RCV
- GPIO9_USB_VBUS_EN
- GPIOA
- GPIOAO_0
- GPIOAO_1
- GPIOAO_10
- GPIOAO_11
- GPIOAO_12
- GPIOAO_13
- GPIOAO_2
- GPIOAO_3
- GPIOAO_4
- GPIOAO_5
- GPIOAO_6
- GPIOAO_7
- GPIOAO_8
- GPIOAO_9
- GPIOA_0
- GPIOA_1
- GPIOA_10
- GPIOA_11
- GPIOA_12
- GPIOA_13
- GPIOA_14
- GPIOA_15
- GPIOA_16
- GPIOA_17
- GPIOA_18
- GPIOA_19
- GPIOA_2
- GPIOA_20
- GPIOA_3
- GPIOA_4
- GPIOA_5
- GPIOA_6
- GPIOA_7
- GPIOA_8
- GPIOA_9
- GPIOA_CK
- GPIOA_R
- GPIOB
- GPIOBASE
- GPIOBASE_ICH0
- GPIOBASE_ICH6
- GPIOB_CK
- GPIOB_R
- GPIOC
- GPIOC0_LED_RED
- GPIOC10_CF_nPWE
- GPIOC11_PSKTSEL
- GPIOC12_nPREG
- GPIOC13_nPWAIT
- GPIOC14_nPIOIS16
- GPIOC15_nPIOR
- GPIOC1_LED_GREEN
- GPIOC2_LED_BLUE
- GPIOC3_nSD_CS
- GPIOC4_CF_nCD
- GPIOC5_nCIOW
- GPIOC6_nCIOR
- GPIOC7_nPCE1
- GPIOC8_nPCE2
- GPIOC9_nPOE
- GPIOCFG
- GPIOCGF
- GPIOCLK_0
- GPIOCLK_1
- GPIOCLK_2
- GPIOCLK_3
- GPIOCNFGR
- GPIOCON_OFF
- GPIOCSR
- GPIOCSR_DIR0
- GPIOCSR_DIR1
- GPIOCSR_DIR2
- GPIOCSR_DIR3
- GPIOCSR_DIR4
- GPIOCSR_DIR5
- GPIOCSR_DIR6
- GPIOCSR_DIR7
- GPIOCSR_VAL0
- GPIOCSR_VAL1
- GPIOCSR_VAL2
- GPIOCSR_VAL3
- GPIOCSR_VAL4
- GPIOCSR_VAL5
- GPIOCSR_VAL6
- GPIOCSR_VAL7
- GPIOCTL
- GPIOCTRL_ICH0
- GPIOCTRL_ICH6
- GPIOC_0
- GPIOC_1
- GPIOC_2
- GPIOC_3
- GPIOC_4
- GPIOC_5
- GPIOC_6
- GPIOC_7
- GPIOC_BASE
- GPIOC_CK
- GPIOC_R
- GPIOCtrl
- GPIOD
- GPIOD0_CPU_SS_INT
- GPIOD10_nSDIO_IRQ
- GPIOD11_nCIOIS16
- GPIOD12_nCWAIT
- GPIOD13_CF_RNB
- GPIOD14_nUSBC_DETECT
- GPIOD15_nPIOW
- GPIOD1_nKEY_CALENDAR
- GPIOD2_BLUETOOTH_WAKEUP
- GPIOD3_nKEY_HOME
- GPIOD4_CF_nCD
- GPIOD5_nPIO
- GPIOD6_nKEY_RECORD
- GPIOD7_nSDIO_DETECT
- GPIOD8_COM_DCD
- GPIOD9_nAC_IN
- GPIODATAIR
- GPIODATAOR
- GPIODAT_OFF
- GPIODIR
- GPIODSP0
- GPIODSP1
- GPIODSP2
- GPIODSP3
- GPIODV_0
- GPIODV_1
- GPIODV_10
- GPIODV_11
- GPIODV_12
- GPIODV_13
- GPIODV_14
- GPIODV_15
- GPIODV_16
- GPIODV_17
- GPIODV_18
- GPIODV_19
- GPIODV_2
- GPIODV_20
- GPIODV_21
- GPIODV_22
- GPIODV_23
- GPIODV_24
- GPIODV_25
- GPIODV_26
- GPIODV_27
- GPIODV_28
- GPIODV_29
- GPIODV_3
- GPIODV_4
- GPIODV_5
- GPIODV_6
- GPIODV_7
- GPIODV_8
- GPIODV_9
- GPIOD_ASIS
- GPIOD_BASE
- GPIOD_CK
- GPIOD_FLAGS_BIT_DIR_OUT
- GPIOD_FLAGS_BIT_DIR_SET
- GPIOD_FLAGS_BIT_DIR_VAL
- GPIOD_FLAGS_BIT_NONEXCLUSIVE
- GPIOD_FLAGS_BIT_OPEN_DRAIN
- GPIOD_IN
- GPIOD_OUT_HIGH
- GPIOD_OUT_HIGH_OPEN_DRAIN
- GPIOD_OUT_LOW
- GPIOD_OUT_LOW_OPEN_DRAIN
- GPIOD_R
- GPIOE
- GPIOEND
- GPIOEVENT_EVENT_FALLING_EDGE
- GPIOEVENT_EVENT_RISING_EDGE
- GPIOEVENT_REQUEST_BOTH_EDGES
- GPIOEVENT_REQUEST_FALLING_EDGE
- GPIOEVENT_REQUEST_RISING_EDGE
- GPIOEVENT_REQUEST_VALID_FLAGS
- GPIOE_0
- GPIOE_1
- GPIOE_2
- GPIOE_CK
- GPIOE_R
- GPIOF
- GPIOFUNC
- GPIOF_ACTIVE_LOW
- GPIOF_CK
- GPIOF_DIR_IN
- GPIOF_DIR_OUT
- GPIOF_EXPORT
- GPIOF_EXPORT_CHANGEABLE
- GPIOF_EXPORT_DIR_CHANGEABLE
- GPIOF_EXPORT_DIR_FIXED
- GPIOF_IN
- GPIOF_INIT_HIGH
- GPIOF_INIT_LOW
- GPIOF_OPEN_DRAIN
- GPIOF_OPEN_SOURCE
- GPIOF_OUT_INIT_HIGH
- GPIOF_OUT_INIT_LOW
- GPIOF_R
- GPIOG
- GPIOG_CK
- GPIOG_R
- GPIOH
- GPIOHANDLES_MAX
- GPIOHANDLE_GET_LINE_VALUES_IOCTL
- GPIOHANDLE_REQUEST_ACTIVE_LOW
- GPIOHANDLE_REQUEST_INPUT
- GPIOHANDLE_REQUEST_OPEN_DRAIN
- GPIOHANDLE_REQUEST_OPEN_SOURCE
- GPIOHANDLE_REQUEST_OUTPUT
- GPIOHANDLE_REQUEST_VALID_FLAGS
- GPIOHANDLE_SET_LINE_VALUES_IOCTL
- GPIOHI
- GPIOH_0
- GPIOH_1
- GPIOH_2
- GPIOH_3
- GPIOH_4
- GPIOH_5
- GPIOH_6
- GPIOH_7
- GPIOH_8
- GPIOH_9
- GPIOH_CK
- GPIOH_R
- GPIOI
- GPIOIBE
- GPIOIC
- GPIOIE
- GPIOIEV
- GPIOILEVEL
- GPIOIN
- GPIOINVR
- GPIOIS
- GPIOISTAT
- GPIOI_CK
- GPIOI_R
- GPIOJ
- GPIOJ_CK
- GPIOJ_R
- GPIOK
- GPIOK_CK
- GPIOK_R
- GPIOL
- GPIOLIB_ACPI_H
- GPIOLIB_H
- GPIOLIB_OF_H
- GPIOLINE_FLAG_ACTIVE_LOW
- GPIOLINE_FLAG_IS_OUT
- GPIOLINE_FLAG_KERNEL
- GPIOLINE_FLAG_OPEN_DRAIN
- GPIOLINE_FLAG_OPEN_SOURCE
- GPIOLO
- GPIOL_OUT_EN
- GPIOL_OUT_VAL
- GPIOM
- GPIOMIS
- GPIOMM_EXTENT
- GPIOMM_NGPIO
- GPIOMODE_DISABLED
- GPIOMODE_ENABLED
- GPIOMUX_EN
- GPION
- GPIONMIEN
- GPIOO
- GPIOODENR
- GPIOOER
- GPIOOFFSET
- GPIOOUT
- GPIOPAD_A
- GPIOPAD_A__GPIO_A_MASK
- GPIOPAD_A__GPIO_A__SHIFT
- GPIOPAD_EN
- GPIOPAD_EN__GPIO_EN_MASK
- GPIOPAD_EN__GPIO_EN__SHIFT
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK
- GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT
- GPIOPAD_INT_EN__GPIO_INT_EN_MASK
- GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT
- GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK
- GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT
- GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK
- GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT
- GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK
- GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK
- GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT
- GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK
- GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT
- GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK
- GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT
- GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK
- GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT
- GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK
- GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT
- GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK
- GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT
- GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK
- GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT
- GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK
- GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT
- GPIOPAD_MASK
- GPIOPAD_MASK__GPIO_MASK_MASK
- GPIOPAD_MASK__GPIO_MASK__SHIFT
- GPIOPAD_PD_EN__GPIO_PD_EN_MASK
- GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK
- GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT
- GPIOPAD_PU_EN__GPIO_PU_EN_MASK
- GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT
- GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK
- GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT
- GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK
- GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT
- GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK
- GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT
- GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK
- GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT
- GPIOPAD_Y
- GPIOPAD_Y__GPIO_Y_MASK
- GPIOPAD_Y__GPIO_Y__SHIFT
- GPIOPANELCTL
- GPIOPWMCTRL
- GPIOR
- GPIORIS
- GPIOR_GP1_OE
- GPIOR_GP1_OUT
- GPIOR_GP2_OE
- GPIOR_GP3_OE
- GPIOR_GP3_OUT
- GPIOR_GP4_OE
- GPIOR_GP5_OE
- GPIOR_SI2D
- GPIOR_SI2OE
- GPIOR_VOLDN
- GPIOR_VOLUP
- GPIOSEL_BT
- GPIOSEL_ENBT
- GPIOSEL_GPIO
- GPIOSEL_GPIO_MASK
- GPIOSEL_PHYDBG
- GPIOSEL_WLANDBG
- GPIOSTAT
- GPIOW_DDR
- GPIOW_DVO
- GPIOW_GPIOE
- GPIOX_0
- GPIOX_1
- GPIOX_10
- GPIOX_11
- GPIOX_12
- GPIOX_13
- GPIOX_14
- GPIOX_15
- GPIOX_16
- GPIOX_17
- GPIOX_18
- GPIOX_19
- GPIOX_2
- GPIOX_20
- GPIOX_21
- GPIOX_22
- GPIOX_3
- GPIOX_4
- GPIOX_5
- GPIOX_6
- GPIOX_7
- GPIOX_8
- GPIOX_9
- GPIOY_0
- GPIOY_1
- GPIOY_10
- GPIOY_11
- GPIOY_12
- GPIOY_13
- GPIOY_14
- GPIOY_15
- GPIOY_16
- GPIOY_2
- GPIOY_3
- GPIOY_4
- GPIOY_5
- GPIOY_6
- GPIOY_7
- GPIOY_8
- GPIOY_9
- GPIOZ
- GPIOZ_0
- GPIOZ_1
- GPIOZ_10
- GPIOZ_11
- GPIOZ_12
- GPIOZ_13
- GPIOZ_14
- GPIOZ_15
- GPIOZ_2
- GPIOZ_3
- GPIOZ_4
- GPIOZ_5
- GPIOZ_6
- GPIOZ_7
- GPIOZ_8
- GPIOZ_9
- GPIOZ_R
- GPIO_0
- GPIO_0_INT
- GPIO_0to7_CTRL
- GPIO_1
- GPIO_10
- GPIO_11
- GPIO_12
- GPIO_13
- GPIO_14
- GPIO_15
- GPIO_16to24_CTRL
- GPIO_1B
- GPIO_1Hz
- GPIO_1_INT
- GPIO_2
- GPIO_2ND_BANK
- GPIO_2_FUNC
- GPIO_2_INT
- GPIO_3
- GPIO_32_768kHz
- GPIO_32_MASK
- GPIO_36PINS
- GPIO_3B
- GPIO_3XX_INT_EN00
- GPIO_3XX_INT_EN10
- GPIO_3XX_INT_EN20
- GPIO_3XX_INT_EN30
- GPIO_3XX_INT_POL
- GPIO_3XX_INT_STAT
- GPIO_3XX_INT_TYPE
- GPIO_3_FUNC
- GPIO_3_INT
- GPIO_4
- GPIO_48PINS_EDGE_SELECT
- GPIO_4B
- GPIO_4_FUNC
- GPIO_5
- GPIO_50PINS_PULLUPDOWN
- GPIO_5V_ENABLE
- GPIO_6
- GPIO_7
- GPIO_8
- GPIO_8to15_CTRL
- GPIO_9
- GPIO_9XX_BYTESWAP
- GPIO_9XX_CTRL
- GPIO_9XX_INT_EN00
- GPIO_9XX_INT_EN10
- GPIO_9XX_INT_EN20
- GPIO_9XX_INT_EN30
- GPIO_9XX_INT_POL
- GPIO_9XX_INT_STAT
- GPIO_9XX_INT_TYPE
- GPIO_9XX_OUTPUT_EN
- GPIO_9XX_PADDRV
- GPIO_A0
- GPIO_A1
- GPIO_A2
- GPIO_A3
- GPIO_ACTIVE_HIGH
- GPIO_ACTIVE_LOW
- GPIO_ADDR_BASE
- GPIO_AF
- GPIO_AIN
- GPIO_AK5385A_CKS0
- GPIO_AK5385A_CKS1
- GPIO_AK5385A_DFS0
- GPIO_AK5385A_DFS1
- GPIO_AK5385A_MASK
- GPIO_AK5385_DFS_DOUBLE
- GPIO_AK5385_DFS_MASK
- GPIO_AK5385_DFS_NORMAL
- GPIO_AK5385_DFS_QUAD
- GPIO_ALE
- GPIO_ALL
- GPIO_ALT0
- GPIO_ALT1
- GPIO_ANAIN_MONITOR
- GPIO_ANALOG_PRESENT
- GPIO_AOUT
- GPIO_AOUT_0
- GPIO_AOUT_1
- GPIO_AOUT_ISR
- GPIO_AOUT_MASK
- GPIO_AOUT_SHIFT
- GPIO_APP_PRIORITY
- GPIO_ASSERT_INT
- GPIO_A_0
- GPIO_A_1
- GPIO_B0
- GPIO_B1
- GPIO_B2
- GPIO_B3
- GPIO_B4
- GPIO_B5
- GPIO_B6
- GPIO_B7
- GPIO_BANK
- GPIO_BANK1_MASK
- GPIO_BANK_BASE
- GPIO_BANK_OFFSET
- GPIO_BANK_SIZE
- GPIO_BANK_START
- GPIO_BANK_STRIDE
- GPIO_BAR
- GPIO_BASE
- GPIO_BASEMODE_6368_GPIO
- GPIO_BASEMODE_6368_MASK
- GPIO_BASEMODE_6368_REG
- GPIO_BASEMODE_6368_UART2
- GPIO_BASE_ADDRESS
- GPIO_BATTDEAD
- GPIO_BATTWARN
- GPIO_BIAS_CTRL
- GPIO_BIN
- GPIO_BIST_ALL_GO_STATUS_REG
- GPIO_BIST_CPU_GO_STATUS_REG
- GPIO_BIST_DEV_GO_STATUS_REG
- GPIO_BIT
- GPIO_BIT_CFG
- GPIO_BIT_CFG_FIL_CNT_SHIFT
- GPIO_BIT_CFG_FIL_MASK
- GPIO_BIT_CFG_FIL_SEL_SHIFT
- GPIO_BIT_CFG_INT_EN
- GPIO_BIT_CFG_INT_TYPE
- GPIO_BIT_CFG_PIN_SEL_MASK
- GPIO_BIT_CFG_PIN_XOR
- GPIO_BIT_CFG_TX_OD
- GPIO_BIT_CFG_TX_OE
- GPIO_BIT_EN
- GPIO_BIT_OFFSET
- GPIO_BLINK_CNT_SELECT_OFF
- GPIO_BLINK_EN
- GPIO_BLINK_EN_OFF
- GPIO_BLOCK_SHIFT
- GPIO_BOARD_START
- GPIO_BOUT
- GPIO_BOUT_0
- GPIO_BOUT_1
- GPIO_BOUT_ISR
- GPIO_BOUT_MASK
- GPIO_BOUT_SHIFT
- GPIO_BSD_EN
- GPIO_BTN_S1
- GPIO_BTRF_HWPDN_N
- GPIO_BT_CTL_HWPDN
- GPIO_BUTTON1
- GPIO_BUTTON2
- GPIO_BUTTON3
- GPIO_BUTTON4
- GPIO_BUTTON5
- GPIO_BUTTON6
- GPIO_BUTTON7
- GPIO_BUTTON8
- GPIO_BYPASS_IN
- GPIO_C0
- GPIO_C1
- GPIO_C2
- GPIO_C3
- GPIO_C4
- GPIO_C5
- GPIO_C6
- GPIO_C7
- GPIO_CARDIRQ
- GPIO_CCLK
- GPIO_CDA
- GPIO_CDB
- GPIO_CFG
- GPIO_CFG0
- GPIO_CFG0_GPIOBUF0_
- GPIO_CFG0_GPIOBUF1_
- GPIO_CFG0_GPIOBUF2_
- GPIO_CFG0_GPIOBUF3_
- GPIO_CFG0_GPIOBUF_MASK_
- GPIO_CFG0_GPIOD0_
- GPIO_CFG0_GPIOD1_
- GPIO_CFG0_GPIOD2_
- GPIO_CFG0_GPIOD3_
- GPIO_CFG0_GPIODIR0_
- GPIO_CFG0_GPIODIR1_
- GPIO_CFG0_GPIODIR2_
- GPIO_CFG0_GPIODIR3_
- GPIO_CFG0_GPIODIR_MASK_
- GPIO_CFG0_GPIOD_MASK_
- GPIO_CFG0_GPIOEN0_
- GPIO_CFG0_GPIOEN1_
- GPIO_CFG0_GPIOEN2_
- GPIO_CFG0_GPIOEN3_
- GPIO_CFG0_GPIOEN_MASK_
- GPIO_CFG0_GPIO_DATA_BIT_
- GPIO_CFG0_GPIO_DIR_BIT_
- GPIO_CFG1
- GPIO_CFG1_GPIOBUF10_
- GPIO_CFG1_GPIOBUF11_
- GPIO_CFG1_GPIOBUF4_
- GPIO_CFG1_GPIOBUF5_
- GPIO_CFG1_GPIOBUF6_
- GPIO_CFG1_GPIOBUF7_
- GPIO_CFG1_GPIOBUF8_
- GPIO_CFG1_GPIOBUF9_
- GPIO_CFG1_GPIOBUF_BIT_
- GPIO_CFG1_GPIOBUF_MASK_
- GPIO_CFG1_GPIOD10_
- GPIO_CFG1_GPIOD11_
- GPIO_CFG1_GPIOD4_
- GPIO_CFG1_GPIOD5_
- GPIO_CFG1_GPIOD6_
- GPIO_CFG1_GPIOD7_
- GPIO_CFG1_GPIOD8_
- GPIO_CFG1_GPIOD9_
- GPIO_CFG1_GPIODIR10_
- GPIO_CFG1_GPIODIR11_
- GPIO_CFG1_GPIODIR4_
- GPIO_CFG1_GPIODIR5_
- GPIO_CFG1_GPIODIR6_
- GPIO_CFG1_GPIODIR7_
- GPIO_CFG1_GPIODIR8_
- GPIO_CFG1_GPIODIR9_
- GPIO_CFG1_GPIODIR_MASK_
- GPIO_CFG1_GPIOD_MASK_
- GPIO_CFG1_GPIOEN10_
- GPIO_CFG1_GPIOEN11_
- GPIO_CFG1_GPIOEN4_
- GPIO_CFG1_GPIOEN5_
- GPIO_CFG1_GPIOEN6_
- GPIO_CFG1_GPIOEN7_
- GPIO_CFG1_GPIOEN8_
- GPIO_CFG1_GPIOEN9_
- GPIO_CFG1_GPIOEN_BIT_
- GPIO_CFG1_GPIOEN_MASK_
- GPIO_CFG1_REG
- GPIO_CFG2
- GPIO_CFG2_1588_POL_BIT_
- GPIO_CFG2_REG
- GPIO_CFG3
- GPIO_CFG3_1588_CH_SEL_BIT_
- GPIO_CFG3_1588_OE_BIT_
- GPIO_CFG3_REG
- GPIO_CFG4_REG
- GPIO_CFG_EEPR_EN_
- GPIO_CFG_GPBUF
- GPIO_CFG_GPDATA
- GPIO_CFG_GPDIR
- GPIO_CFG_GPEN
- GPIO_CFG_GPIO0_INT_POL_
- GPIO_CFG_GPIO1_INT_POL_
- GPIO_CFG_GPIO2_INT_POL_
- GPIO_CFG_GPIOBUF0_
- GPIO_CFG_GPIOBUF1_
- GPIO_CFG_GPIOBUF2_
- GPIO_CFG_GPIOD0_
- GPIO_CFG_GPIOD1_
- GPIO_CFG_GPIOD2_
- GPIO_CFG_GPIOD3_
- GPIO_CFG_GPIOD4_
- GPIO_CFG_GPIODIR0_
- GPIO_CFG_GPIODIR1_
- GPIO_CFG_GPIODIR2_
- GPIO_CFG_LED1_EN_
- GPIO_CFG_LED2_EN_
- GPIO_CFG_LED3_EN_
- GPIO_CFG_LED_1_
- GPIO_CFG_LED_2_
- GPIO_CFG_LED_3_
- GPIO_CFG_MASK
- GPIO_CFG_SHIFT
- GPIO_CF_CD
- GPIO_CF_INSERTED
- GPIO_CF_INT
- GPIO_CF_IRQ
- GPIO_CIN
- GPIO_CLAMP_MODE_DC
- GPIO_CLAMP_MODE_THERM
- GPIO_CLAMP_MODE_VRHOT
- GPIO_CLARO_DIG_COAX
- GPIO_CLARO_HP
- GPIO_CLE
- GPIO_CLK_DIV_MASK
- GPIO_CLK_ENABLE
- GPIO_CLK_ENB
- GPIO_CLOCK
- GPIO_CLOCK_DIR_IN
- GPIO_CLOCK_DIR_MASK
- GPIO_CLOCK_DIR_OUT
- GPIO_CLOCK_MASK
- GPIO_CLOCK_PULLUP_DISABLE
- GPIO_CLOCK_VAL_IN
- GPIO_CLOCK_VAL_MASK
- GPIO_CLOCK_VAL_OUT
- GPIO_CMDSRC_0
- GPIO_CMDSRC_1
- GPIO_CMDSRC_ARM
- GPIO_CMDSRC_COLDFIRE
- GPIO_CMDSRC_LPC
- GPIO_CMDSRC_RESERVED
- GPIO_CNF
- GPIO_COMMAND_ADDR
- GPIO_COMMAND_IDLE
- GPIO_COMMAND_READ
- GPIO_COMMAND_REQ1
- GPIO_COMMAND_REQ2
- GPIO_COMMAND_RESET
- GPIO_COMMAND_VIDEO
- GPIO_COMMAND_WRITE
- GPIO_CONFB
- GPIO_CONFIG_TYPE_DDC
- GPIO_CONFIG_TYPE_GENERIC_MUX
- GPIO_CONFIG_TYPE_GSL_MUX
- GPIO_CONFIG_TYPE_HPD
- GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE
- GPIO_CONFIG_TYPE_NONE
- GPIO_CONST
- GPIO_CONST_GPIOS_MASK
- GPIO_CONTROL
- GPIO_COUNT
- GPIO_CPLD_CSN
- GPIO_CPLD_RW
- GPIO_CPU_RESET_REG
- GPIO_CRT2_DDC
- GPIO_CS53x1_M_DOUBLE
- GPIO_CS53x1_M_MASK
- GPIO_CS53x1_M_QUAD
- GPIO_CS53x1_M_SINGLE
- GPIO_CTL
- GPIO_CTL_HI_REG
- GPIO_CTL_LO_REG
- GPIO_CTRL
- GPIO_CTRL_A
- GPIO_CTRL_B
- GPIO_CTRL_DIR0
- GPIO_CTRL_DIR1
- GPIO_CTRL_DIR10
- GPIO_CTRL_DIR2
- GPIO_CTRL_DIR3
- GPIO_CTRL_DIR4
- GPIO_CTRL_DIR5
- GPIO_CTRL_DIR6
- GPIO_CTRL_DIR7
- GPIO_CTRL_DIR8
- GPIO_CTRL_DIR9
- GPIO_CTRL_EPA_EN_MASK
- GPIO_CTRL_GPIO_0
- GPIO_CTRL_M
- GPIO_CTRL_SLOTSELEN
- GPIO_CTRL_SLPCTLEN
- GPIO_CTRL_VAL0
- GPIO_CTRL_VAL1
- GPIO_CTRL_VAL10
- GPIO_CTRL_VAL2
- GPIO_CTRL_VAL3
- GPIO_CTRL_VAL4
- GPIO_CTRL_VAL5
- GPIO_CTRL_VAL6
- GPIO_CTRL_VAL7
- GPIO_CTRL_VAL8
- GPIO_CTRL_VAL9
- GPIO_CTS
- GPIO_D0
- GPIO_D1_FRONT_PANEL
- GPIO_D1_INPUT_ROUTE
- GPIO_D1_JACKDTC0
- GPIO_D1_MAGIC
- GPIO_D1_OUTPUT_ENABLE
- GPIO_D2X_EXT_POWER
- GPIO_D2_ALT
- GPIO_D2_JACKDTC1
- GPIO_D2_OUTPUT_ENABLE
- GPIO_D3
- GPIO_D4_SPI_CDTO
- GPIO_D5_SPI_CCLK
- GPIO_D6_CD
- GPIO_D7_DD
- GPIO_DAT
- GPIO_DATA
- GPIO_DATA1_REG
- GPIO_DATA2_REG
- GPIO_DATA3_REG
- GPIO_DATA4_REG
- GPIO_DATA_0
- GPIO_DATA_1
- GPIO_DATA_10
- GPIO_DATA_11
- GPIO_DATA_12
- GPIO_DATA_13
- GPIO_DATA_14
- GPIO_DATA_15
- GPIO_DATA_16
- GPIO_DATA_17
- GPIO_DATA_18
- GPIO_DATA_19
- GPIO_DATA_2
- GPIO_DATA_20
- GPIO_DATA_21
- GPIO_DATA_22
- GPIO_DATA_23
- GPIO_DATA_24
- GPIO_DATA_25
- GPIO_DATA_26
- GPIO_DATA_27
- GPIO_DATA_28
- GPIO_DATA_29
- GPIO_DATA_3
- GPIO_DATA_30
- GPIO_DATA_31
- GPIO_DATA_4
- GPIO_DATA_5
- GPIO_DATA_6
- GPIO_DATA_7
- GPIO_DATA_8
- GPIO_DATA_9
- GPIO_DATA_BASE
- GPIO_DATA_CLR
- GPIO_DATA_DIRECTION
- GPIO_DATA_DIRECTION_0
- GPIO_DATA_DIRECTION_1
- GPIO_DATA_DIRECTION_10
- GPIO_DATA_DIRECTION_11
- GPIO_DATA_DIRECTION_12
- GPIO_DATA_DIRECTION_13
- GPIO_DATA_DIRECTION_14
- GPIO_DATA_DIRECTION_15
- GPIO_DATA_DIRECTION_16
- GPIO_DATA_DIRECTION_17
- GPIO_DATA_DIRECTION_18
- GPIO_DATA_DIRECTION_19
- GPIO_DATA_DIRECTION_2
- GPIO_DATA_DIRECTION_20
- GPIO_DATA_DIRECTION_21
- GPIO_DATA_DIRECTION_22
- GPIO_DATA_DIRECTION_23
- GPIO_DATA_DIRECTION_24
- GPIO_DATA_DIRECTION_25
- GPIO_DATA_DIRECTION_26
- GPIO_DATA_DIRECTION_27
- GPIO_DATA_DIRECTION_28
- GPIO_DATA_DIRECTION_29
- GPIO_DATA_DIRECTION_3
- GPIO_DATA_DIRECTION_30
- GPIO_DATA_DIRECTION_31
- GPIO_DATA_DIRECTION_4
- GPIO_DATA_DIRECTION_5
- GPIO_DATA_DIRECTION_6
- GPIO_DATA_DIRECTION_7
- GPIO_DATA_DIRECTION_8
- GPIO_DATA_DIRECTION_9
- GPIO_DATA_DIRECTION_SM750LE
- GPIO_DATA_DIRECTION_SM750LE_0
- GPIO_DATA_DIRECTION_SM750LE_1
- GPIO_DATA_DIR_IN
- GPIO_DATA_DIR_MASK
- GPIO_DATA_DIR_OUT
- GPIO_DATA_HI_REG
- GPIO_DATA_IN
- GPIO_DATA_IN_OFF
- GPIO_DATA_LO_REG
- GPIO_DATA_LO_REG_6345
- GPIO_DATA_MASK
- GPIO_DATA_OFFSET
- GPIO_DATA_OUT
- GPIO_DATA_PULLUP_DISABLE
- GPIO_DATA_SET
- GPIO_DATA_SM750LE
- GPIO_DATA_SM750LE_0
- GPIO_DATA_SM750LE_1
- GPIO_DATA_VAL_IN
- GPIO_DATA_VAL_MASK
- GPIO_DATA_VAL_OUT
- GPIO_DAT_OUT1
- GPIO_DAT_OUT2
- GPIO_DAT_OUT3
- GPIO_DAT_STAT1
- GPIO_DAT_STAT2
- GPIO_DAT_STAT3
- GPIO_DBC_CNT
- GPIO_DB_H6
- GPIO_DB_MASK
- GPIO_DCD
- GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING
- GPIO_DDC_CONFIG_TYPE_MODE_AUX
- GPIO_DDC_CONFIG_TYPE_MODE_I2C
- GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT
- GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT
- GPIO_DDC_LINE_COUNT
- GPIO_DDC_LINE_DDC1
- GPIO_DDC_LINE_DDC2
- GPIO_DDC_LINE_DDC3
- GPIO_DDC_LINE_DDC4
- GPIO_DDC_LINE_DDC5
- GPIO_DDC_LINE_DDC6
- GPIO_DDC_LINE_DDC_VGA
- GPIO_DDC_LINE_I2C_PAD
- GPIO_DDC_LINE_MAX
- GPIO_DDC_LINE_MIN
- GPIO_DDC_LINE_UNKNOWN
- GPIO_DDC_LINE_VIP_PAD
- GPIO_DDR
- GPIO_DEBOUNCE
- GPIO_DEBOUNCE_EN
- GPIO_DEBOUNCE_PRESCALE
- GPIO_DEBOUNCE_SEL1
- GPIO_DEBOUNCE_SEL2
- GPIO_DEBUG_PORT_NUM
- GPIO_DEB_MASK
- GPIO_DEB_SHIFT
- GPIO_DEFAULT_MASK
- GPIO_DELAY
- GPIO_DEV_MAX
- GPIO_DIGIN_MONITOR
- GPIO_DIGOUT_MONITOR
- GPIO_DIMM
- GPIO_DIR
- GPIO_DIR1
- GPIO_DIR2
- GPIO_DIR3
- GPIO_DIRECTION
- GPIO_DM9000
- GPIO_DOC_IRQ
- GPIO_DOC_LOCK
- GPIO_DONE
- GPIO_DR
- GPIO_DRAM1_CNTRL_REG
- GPIO_DRAM1_RATIO_REG
- GPIO_DRAM1_RESET_REG
- GPIO_DRAM1_STATUS_REG
- GPIO_DRAM2_CNTRL_REG
- GPIO_DRAM2_RATIO_REG
- GPIO_DRAM2_RESET_REG
- GPIO_DRAM2_STATUS_REG
- GPIO_DRIVE_8mA
- GPIO_DRV_PRIORITY
- GPIO_DRV_SEL10
- GPIO_DRV_STRENGTH_BITS
- GPIO_DRV_STRENGTH_BIT_MASK
- GPIO_DRV_STRENGTH_BIT_SHIFT
- GPIO_DSCLK
- GPIO_DSR
- GPIO_DS_HP_DETECT
- GPIO_DS_INPUT_ROUTE
- GPIO_DS_OUTPUT_ENABLE
- GPIO_DS_OUTPUT_FRONTLR
- GPIO_DTR
- GPIO_DVI_DDC
- GPIO_DW_APB_H
- GPIO_E2CLK
- GPIO_E740_AMP_ON
- GPIO_E740_MIC_ON
- GPIO_E740_PCMCIA_CD0
- GPIO_E740_PCMCIA_CD1
- GPIO_E740_PCMCIA_PWR0
- GPIO_E740_PCMCIA_PWR1
- GPIO_E740_PCMCIA_RDY0
- GPIO_E740_PCMCIA_RDY1
- GPIO_E740_PCMCIA_RST0
- GPIO_E740_PCMCIA_RST1
- GPIO_E740_WM9705_nAVDD2
- GPIO_E750_HP_AMP_OFF
- GPIO_E750_HP_DETECT
- GPIO_E750_PCMCIA_CD0
- GPIO_E750_PCMCIA_PWR0
- GPIO_E750_PCMCIA_RDY0
- GPIO_E750_PCMCIA_RST0
- GPIO_E750_SPK_AMP_OFF
- GPIO_E7XX_IR_OFF
- GPIO_E7XX_USB_DISC
- GPIO_E7XX_USB_PULLUP
- GPIO_E800_ANGELX_IRQ
- GPIO_E800_HP_AMP_OFF
- GPIO_E800_HP_DETECT
- GPIO_E800_PCMCIA_PWR0
- GPIO_E800_PCMCIA_PWR1
- GPIO_E800_PCMCIA_RST0
- GPIO_E800_PCMCIA_RST1
- GPIO_E800_SPK_AMP_ON
- GPIO_E800_USB_DISC
- GPIO_E800_USB_PULLUP
- GPIO_EDGE_CAUSE
- GPIO_EDGE_CAUSE_ARMADAXP_OFF
- GPIO_EDGE_CAUSE_OFF
- GPIO_EDGE_MASK
- GPIO_EDGE_MASK_ARMADAXP_OFF
- GPIO_EDGE_MASK_MV78200_OFF
- GPIO_EDGE_MASK_OFF
- GPIO_EDGE_SEL
- GPIO_EEPROM_CLK
- GPIO_EEPROM_CS
- GPIO_EEPROM_DI
- GPIO_EEPROM_DO
- GPIO_EEPROM_OE
- GPIO_EFS_HCI_SEL
- GPIO_EN
- GPIO_ENUM_UNKNOWN
- GPIO_EN_0
- GPIO_EN_1
- GPIO_ERRINTR_MASK
- GPIO_ESERIES_POWERBTN
- GPIO_ESERIES_TMIO_IRQ
- GPIO_ESERIES_TMIO_PCLR
- GPIO_ESERIES_TMIO_SUSPEND
- GPIO_ETH0_EN
- GPIO_ETH0_IRQ
- GPIO_EVENTS_ENABLE
- GPIO_EXTSRC
- GPIO_EXT_DATA
- GPIO_EXT_PORT
- GPIO_EXT_PORTA
- GPIO_EXT_PORTB
- GPIO_EXT_PORTC
- GPIO_EXT_PORTD
- GPIO_EXT_PORT_STRIDE
- GPIO_EX_GPIOE
- GPIO_FAN
- GPIO_FAN_PM
- GPIO_FE7_SEL
- GPIO_FEA_RESET
- GPIO_FEA_TU_RESET
- GPIO_FEB_RESET
- GPIO_FEB_TU_RESET
- GPIO_FEN_BT
- GPIO_FEN_GPS
- GPIO_FEN_PCI
- GPIO_FEN_USB
- GPIO_FEN_WL
- GPIO_FLTR7_AMOUNT
- GPIO_FN_A0
- GPIO_FN_A1
- GPIO_FN_A10
- GPIO_FN_A11
- GPIO_FN_A12
- GPIO_FN_A13
- GPIO_FN_A14
- GPIO_FN_A15
- GPIO_FN_A16
- GPIO_FN_A17
- GPIO_FN_A18
- GPIO_FN_A19
- GPIO_FN_A2
- GPIO_FN_A20
- GPIO_FN_A21
- GPIO_FN_A22
- GPIO_FN_A23
- GPIO_FN_A24
- GPIO_FN_A25
- GPIO_FN_A3
- GPIO_FN_A4
- GPIO_FN_A5
- GPIO_FN_A6
- GPIO_FN_A7
- GPIO_FN_A8
- GPIO_FN_A9
- GPIO_FN_ADTRG
- GPIO_FN_ADTRG0
- GPIO_FN_ADTRG1
- GPIO_FN_ADTRG_PD
- GPIO_FN_ADTRG_PE
- GPIO_FN_AFE_FS
- GPIO_FN_AFE_HC1
- GPIO_FN_AFE_RDET
- GPIO_FN_AFE_RLYCNT
- GPIO_FN_AFE_RXIN
- GPIO_FN_AFE_SCLK
- GPIO_FN_AFE_TXOUT
- GPIO_FN_AN0
- GPIO_FN_AN1
- GPIO_FN_AN2
- GPIO_FN_AN3
- GPIO_FN_APMONCTL_O
- GPIO_FN_APMPWBTOUT_O
- GPIO_FN_APMPWRBTN
- GPIO_FN_APMS3N
- GPIO_FN_APMS5N
- GPIO_FN_APMSCI_O
- GPIO_FN_APMSLPBTN
- GPIO_FN_APMVDDON
- GPIO_FN_ASEBRKAK
- GPIO_FN_ATACS0
- GPIO_FN_ATACS1
- GPIO_FN_ATADIR
- GPIO_FN_ATAG
- GPIO_FN_ATARD
- GPIO_FN_ATAWR
- GPIO_FN_AUDATA0
- GPIO_FN_AUDATA1
- GPIO_FN_AUDATA2
- GPIO_FN_AUDATA3
- GPIO_FN_AUDCK
- GPIO_FN_AUDIO_CLK
- GPIO_FN_AUDIO_CLKA_A
- GPIO_FN_AUDIO_CLKA_B
- GPIO_FN_AUDIO_CLKB_A
- GPIO_FN_AUDIO_CLKB_B
- GPIO_FN_AUDIO_CLKC
- GPIO_FN_AUDIO_CLKOUT
- GPIO_FN_AUDIO_XOUT
- GPIO_FN_AUDSYNC
- GPIO_FN_BACK
- GPIO_FN_BACK_BSREQ
- GPIO_FN_BOOTFMS
- GPIO_FN_BOOTWP
- GPIO_FN_BREQ
- GPIO_FN_BREQ_BSACK
- GPIO_FN_BS
- GPIO_FN_CAN0_RX_A
- GPIO_FN_CAN0_RX_B
- GPIO_FN_CAN0_TX_A
- GPIO_FN_CAN0_TX_B
- GPIO_FN_CAN1_RX_A
- GPIO_FN_CAN1_RX_B
- GPIO_FN_CAN1_RX_C
- GPIO_FN_CAN1_TX_A
- GPIO_FN_CAN1_TX_B
- GPIO_FN_CAN1_TX_C
- GPIO_FN_CAN_CLK_A
- GPIO_FN_CAN_CLK_B
- GPIO_FN_CAS
- GPIO_FN_CASL
- GPIO_FN_CASU
- GPIO_FN_CDE
- GPIO_FN_CE2A
- GPIO_FN_CE2B
- GPIO_FN_CKE
- GPIO_FN_CLKAUDIOAO
- GPIO_FN_CLKAUDIOBO
- GPIO_FN_CLKOUT
- GPIO_FN_CLKOUTENB
- GPIO_FN_COM1_CTS
- GPIO_FN_COM1_RTS
- GPIO_FN_COM1_RXD
- GPIO_FN_COM1_TXD
- GPIO_FN_COM2_CTS
- GPIO_FN_COM2_DCD
- GPIO_FN_COM2_DSR
- GPIO_FN_COM2_DTR
- GPIO_FN_COM2_RI
- GPIO_FN_COM2_RTS
- GPIO_FN_COM2_RXD
- GPIO_FN_COM2_TXD
- GPIO_FN_CRX0
- GPIO_FN_CRX0_CRX1
- GPIO_FN_CRX0_CRX1_CRX2
- GPIO_FN_CRX0_CRX1_CRX2_PJ20
- GPIO_FN_CRX0_CRX1_PJ22
- GPIO_FN_CRX1
- GPIO_FN_CRX1_PJ22
- GPIO_FN_CRX2
- GPIO_FN_CRX2_PJ20
- GPIO_FN_CS0
- GPIO_FN_CS1
- GPIO_FN_CS1_A26
- GPIO_FN_CS2
- GPIO_FN_CS3
- GPIO_FN_CS4
- GPIO_FN_CS5
- GPIO_FN_CS5A_CE2A
- GPIO_FN_CS5B_CE1A
- GPIO_FN_CS5CE1A
- GPIO_FN_CS5_CE1A
- GPIO_FN_CS6
- GPIO_FN_CS6A_CE2B
- GPIO_FN_CS6B_CE1B
- GPIO_FN_CS6CE1B
- GPIO_FN_CS6_CE1B
- GPIO_FN_CS7
- GPIO_FN_CTS0_A
- GPIO_FN_CTS0_B
- GPIO_FN_CTS0_C
- GPIO_FN_CTS1
- GPIO_FN_CTS1_A
- GPIO_FN_CTS1_B
- GPIO_FN_CTS1_C
- GPIO_FN_CTS1_E
- GPIO_FN_CTS2
- GPIO_FN_CTS3
- GPIO_FN_CTS4
- GPIO_FN_CTS5
- GPIO_FN_CTS7
- GPIO_FN_CTX0
- GPIO_FN_CTX0_CTX1
- GPIO_FN_CTX0_CTX1_CTX2
- GPIO_FN_CTX0_CTX1_CTX2_PJ21
- GPIO_FN_CTX0_CTX1_PJ23
- GPIO_FN_CTX1
- GPIO_FN_CTX1_PJ23
- GPIO_FN_CTX2
- GPIO_FN_CTX2_PJ21
- GPIO_FN_D0
- GPIO_FN_D1
- GPIO_FN_D10
- GPIO_FN_D11
- GPIO_FN_D12
- GPIO_FN_D13
- GPIO_FN_D14
- GPIO_FN_D15
- GPIO_FN_D16
- GPIO_FN_D17
- GPIO_FN_D18
- GPIO_FN_D19
- GPIO_FN_D2
- GPIO_FN_D20
- GPIO_FN_D21
- GPIO_FN_D22
- GPIO_FN_D23
- GPIO_FN_D24
- GPIO_FN_D25
- GPIO_FN_D26
- GPIO_FN_D27
- GPIO_FN_D28
- GPIO_FN_D29
- GPIO_FN_D3
- GPIO_FN_D30
- GPIO_FN_D31
- GPIO_FN_D32_AD0_DR0
- GPIO_FN_D33_AD1_DR1
- GPIO_FN_D34_AD2_DR2
- GPIO_FN_D35_AD3_DR3
- GPIO_FN_D36_AD4_DR4
- GPIO_FN_D37_AD5_DR5
- GPIO_FN_D38_AD6_DG0
- GPIO_FN_D39_AD7_DG1
- GPIO_FN_D4
- GPIO_FN_D40_AD8_DG2
- GPIO_FN_D41_AD9_DG3
- GPIO_FN_D42_AD10_DG4
- GPIO_FN_D43_AD11_DG5
- GPIO_FN_D44_AD12_DB0
- GPIO_FN_D45_AD13_DB1
- GPIO_FN_D46_AD14_DB2
- GPIO_FN_D47_AD15_DB3
- GPIO_FN_D48_AD16_DB4
- GPIO_FN_D49_AD17_DB5
- GPIO_FN_D5
- GPIO_FN_D50_AD18
- GPIO_FN_D51_AD19
- GPIO_FN_D52_AD20
- GPIO_FN_D53_AD21
- GPIO_FN_D54_AD22
- GPIO_FN_D55_AD23
- GPIO_FN_D56_AD24
- GPIO_FN_D57_AD25
- GPIO_FN_D58_AD26
- GPIO_FN_D59_AD27
- GPIO_FN_D6
- GPIO_FN_D60_AD28
- GPIO_FN_D61_AD29
- GPIO_FN_D62_AD30
- GPIO_FN_D63_AD31
- GPIO_FN_D7
- GPIO_FN_D8
- GPIO_FN_D9
- GPIO_FN_DA0
- GPIO_FN_DA1
- GPIO_FN_DACK
- GPIO_FN_DACK0
- GPIO_FN_DACK0_PD
- GPIO_FN_DACK0_PE
- GPIO_FN_DACK1
- GPIO_FN_DACK1_PD
- GPIO_FN_DACK1_PE
- GPIO_FN_DACK2
- GPIO_FN_DACK3
- GPIO_FN_DB0
- GPIO_FN_DB1
- GPIO_FN_DB2
- GPIO_FN_DB3
- GPIO_FN_DB4
- GPIO_FN_DB5
- GPIO_FN_DCLKIN
- GPIO_FN_DCLKOUT
- GPIO_FN_DDC0
- GPIO_FN_DDC1
- GPIO_FN_DDC2
- GPIO_FN_DDC3
- GPIO_FN_DEVSEL_DCLKOUT
- GPIO_FN_DG0
- GPIO_FN_DG1
- GPIO_FN_DG2
- GPIO_FN_DG3
- GPIO_FN_DG4
- GPIO_FN_DG5
- GPIO_FN_DIRECTION
- GPIO_FN_DISP
- GPIO_FN_DMAC_DACK0
- GPIO_FN_DMAC_DACK1
- GPIO_FN_DMAC_DREQ0
- GPIO_FN_DMAC_DREQ1
- GPIO_FN_DR0
- GPIO_FN_DR1
- GPIO_FN_DR2
- GPIO_FN_DR3
- GPIO_FN_DR4
- GPIO_FN_DR5
- GPIO_FN_DRACK0
- GPIO_FN_DRAK0
- GPIO_FN_DRAK0_PK1
- GPIO_FN_DRAK0_PK3
- GPIO_FN_DRAK1
- GPIO_FN_DRAK1_PK0
- GPIO_FN_DRAK1_PK2
- GPIO_FN_DRAK2
- GPIO_FN_DRAK3
- GPIO_FN_DREQ0
- GPIO_FN_DREQ0_PD
- GPIO_FN_DREQ0_PE
- GPIO_FN_DREQ1
- GPIO_FN_DREQ1_PD
- GPIO_FN_DREQ1_PE
- GPIO_FN_DREQ2
- GPIO_FN_DREQ3
- GPIO_FN_DU0_CDE
- GPIO_FN_DU0_DB0
- GPIO_FN_DU0_DB1
- GPIO_FN_DU0_DB2
- GPIO_FN_DU0_DB3
- GPIO_FN_DU0_DB4
- GPIO_FN_DU0_DB5
- GPIO_FN_DU0_DB6
- GPIO_FN_DU0_DB7
- GPIO_FN_DU0_DG0
- GPIO_FN_DU0_DG1
- GPIO_FN_DU0_DG2
- GPIO_FN_DU0_DG3
- GPIO_FN_DU0_DG4
- GPIO_FN_DU0_DG5
- GPIO_FN_DU0_DG6
- GPIO_FN_DU0_DG7
- GPIO_FN_DU0_DISP
- GPIO_FN_DU0_DOTCLKIN
- GPIO_FN_DU0_DOTCLKOUT
- GPIO_FN_DU0_DR0
- GPIO_FN_DU0_DR1
- GPIO_FN_DU0_DR2
- GPIO_FN_DU0_DR3
- GPIO_FN_DU0_DR4
- GPIO_FN_DU0_DR5
- GPIO_FN_DU0_DR6
- GPIO_FN_DU0_DR7
- GPIO_FN_DU0_EXHSYNC_DU0_HSYNC
- GPIO_FN_DU0_EXODDF_DU0_ODDF
- GPIO_FN_DU0_EXVSYNC_DU0_VSYNC
- GPIO_FN_DV_CLK
- GPIO_FN_DV_CLKI
- GPIO_FN_DV_D0
- GPIO_FN_DV_D1
- GPIO_FN_DV_D10
- GPIO_FN_DV_D11
- GPIO_FN_DV_D12
- GPIO_FN_DV_D13
- GPIO_FN_DV_D14
- GPIO_FN_DV_D15
- GPIO_FN_DV_D2
- GPIO_FN_DV_D3
- GPIO_FN_DV_D4
- GPIO_FN_DV_D5
- GPIO_FN_DV_D6
- GPIO_FN_DV_D7
- GPIO_FN_DV_D8
- GPIO_FN_DV_D9
- GPIO_FN_DV_DATA0
- GPIO_FN_DV_DATA1
- GPIO_FN_DV_DATA10
- GPIO_FN_DV_DATA11
- GPIO_FN_DV_DATA12
- GPIO_FN_DV_DATA13
- GPIO_FN_DV_DATA14
- GPIO_FN_DV_DATA15
- GPIO_FN_DV_DATA16
- GPIO_FN_DV_DATA17
- GPIO_FN_DV_DATA18
- GPIO_FN_DV_DATA19
- GPIO_FN_DV_DATA2
- GPIO_FN_DV_DATA20
- GPIO_FN_DV_DATA21
- GPIO_FN_DV_DATA22
- GPIO_FN_DV_DATA23
- GPIO_FN_DV_DATA3
- GPIO_FN_DV_DATA4
- GPIO_FN_DV_DATA5
- GPIO_FN_DV_DATA6
- GPIO_FN_DV_DATA7
- GPIO_FN_DV_DATA8
- GPIO_FN_DV_DATA9
- GPIO_FN_DV_HSYNC
- GPIO_FN_DV_VSYNC
- GPIO_FN_ET0_COL
- GPIO_FN_ET0_CRS
- GPIO_FN_ET0_ERXD0
- GPIO_FN_ET0_ERXD1
- GPIO_FN_ET0_ERXD2_A
- GPIO_FN_ET0_ERXD2_B
- GPIO_FN_ET0_ERXD3_A
- GPIO_FN_ET0_ERXD3_B
- GPIO_FN_ET0_ERXD4
- GPIO_FN_ET0_ERXD5
- GPIO_FN_ET0_ERXD6
- GPIO_FN_ET0_ERXD7
- GPIO_FN_ET0_ETXD0
- GPIO_FN_ET0_ETXD1_A
- GPIO_FN_ET0_ETXD1_B
- GPIO_FN_ET0_ETXD2_A
- GPIO_FN_ET0_ETXD2_B
- GPIO_FN_ET0_ETXD3_A
- GPIO_FN_ET0_ETXD3_B
- GPIO_FN_ET0_ETXD4
- GPIO_FN_ET0_ETXD5_A
- GPIO_FN_ET0_ETXD5_B
- GPIO_FN_ET0_ETXD6_A
- GPIO_FN_ET0_ETXD6_B
- GPIO_FN_ET0_ETXD7
- GPIO_FN_ET0_GTX_CLK_A
- GPIO_FN_ET0_GTX_CLK_B
- GPIO_FN_ET0_LINK_A
- GPIO_FN_ET0_LINK_B
- GPIO_FN_ET0_LINK_C
- GPIO_FN_ET0_MAGIC_A
- GPIO_FN_ET0_MAGIC_B
- GPIO_FN_ET0_MAGIC_C
- GPIO_FN_ET0_MDC
- GPIO_FN_ET0_MDIO
- GPIO_FN_ET0_MDIO_A
- GPIO_FN_ET0_MDIO_B
- GPIO_FN_ET0_PHY_INT_A
- GPIO_FN_ET0_PHY_INT_B
- GPIO_FN_ET0_PHY_INT_C
- GPIO_FN_ET0_RX_CLK_A
- GPIO_FN_ET0_RX_CLK_B
- GPIO_FN_ET0_RX_DV
- GPIO_FN_ET0_RX_ER
- GPIO_FN_ET0_TX_CLK_A
- GPIO_FN_ET0_TX_CLK_B
- GPIO_FN_ET0_TX_EN
- GPIO_FN_ET0_TX_ER
- GPIO_FN_ET1_MDC
- GPIO_FN_ET1_MDIO
- GPIO_FN_ETH_COL
- GPIO_FN_ETH_CRS
- GPIO_FN_ETH_LINK
- GPIO_FN_ETH_MAGIC
- GPIO_FN_ETH_MDC
- GPIO_FN_ETH_MDIO
- GPIO_FN_ETH_RXD0
- GPIO_FN_ETH_RXD1
- GPIO_FN_ETH_RXD2
- GPIO_FN_ETH_RXD3
- GPIO_FN_ETH_RX_CLK
- GPIO_FN_ETH_RX_DV
- GPIO_FN_ETH_RX_ER
- GPIO_FN_ETH_TXD0
- GPIO_FN_ETH_TXD1
- GPIO_FN_ETH_TXD2
- GPIO_FN_ETH_TXD3
- GPIO_FN_ETH_TX_CLK
- GPIO_FN_ETH_TX_EN
- GPIO_FN_ETH_TX_ER
- GPIO_FN_EVENT0
- GPIO_FN_EVENT1
- GPIO_FN_EVENT2
- GPIO_FN_EVENT3
- GPIO_FN_EVENT4
- GPIO_FN_EVENT5
- GPIO_FN_EVENT6
- GPIO_FN_EVENT7
- GPIO_FN_EXBUF_ENB
- GPIO_FN_EX_CS0
- GPIO_FN_EX_CS1
- GPIO_FN_EX_CS2
- GPIO_FN_EX_CS3
- GPIO_FN_EX_CS4
- GPIO_FN_EX_CS5
- GPIO_FN_EX_WAIT0
- GPIO_FN_EX_WAIT1
- GPIO_FN_EX_WAIT2
- GPIO_FN_FALE
- GPIO_FN_FALE_A
- GPIO_FN_FALE_B
- GPIO_FN_FCDE
- GPIO_FN_FCE
- GPIO_FN_FCE_A
- GPIO_FN_FCE_B
- GPIO_FN_FCLE
- GPIO_FN_FCLE_A
- GPIO_FN_FCLE_B
- GPIO_FN_FD0
- GPIO_FN_FD0_A
- GPIO_FN_FD0_B
- GPIO_FN_FD1
- GPIO_FN_FD1_A
- GPIO_FN_FD1_B
- GPIO_FN_FD2
- GPIO_FN_FD2_A
- GPIO_FN_FD2_B
- GPIO_FN_FD3
- GPIO_FN_FD3_A
- GPIO_FN_FD3_B
- GPIO_FN_FD4
- GPIO_FN_FD4_A
- GPIO_FN_FD4_B
- GPIO_FN_FD5
- GPIO_FN_FD5_A
- GPIO_FN_FD5_B
- GPIO_FN_FD6
- GPIO_FN_FD6_A
- GPIO_FN_FD6_B
- GPIO_FN_FD7
- GPIO_FN_FD7_A
- GPIO_FN_FD7_B
- GPIO_FN_FMS0
- GPIO_FN_FOE
- GPIO_FN_FRAME
- GPIO_FN_FRB
- GPIO_FN_FRB_A
- GPIO_FN_FRB_B
- GPIO_FN_FRE
- GPIO_FN_FRE_A
- GPIO_FN_FRE_B
- GPIO_FN_FSC
- GPIO_FN_FSE
- GPIO_FN_FSE_A
- GPIO_FN_FSE_B
- GPIO_FN_FSIIABCK
- GPIO_FN_FSIIALRCK
- GPIO_FN_FSIIASD
- GPIO_FN_FSIIBBCK
- GPIO_FN_FSIIBLRCK
- GPIO_FN_FSIIBSD
- GPIO_FN_FSIMCKA
- GPIO_FN_FSIMCKB
- GPIO_FN_FSIOABCK
- GPIO_FN_FSIOALRCK
- GPIO_FN_FSIOASD
- GPIO_FN_FSIOBBCK
- GPIO_FN_FSIOBLRCK
- GPIO_FN_FSIOBSD
- GPIO_FN_FSTATUS
- GPIO_FN_FWE
- GPIO_FN_FWE_A
- GPIO_FN_FWE_B
- GPIO_FN_GNT0_GNTIN
- GPIO_FN_GNT1
- GPIO_FN_GNT2
- GPIO_FN_GNT3
- GPIO_FN_HAC0_BITCLK
- GPIO_FN_HAC0_SDIN
- GPIO_FN_HAC0_SDOUT
- GPIO_FN_HAC0_SYNC
- GPIO_FN_HAC1_BITCLK
- GPIO_FN_HAC1_SDIN
- GPIO_FN_HAC1_SDOUT
- GPIO_FN_HAC1_SYNC
- GPIO_FN_HAC_RES
- GPIO_FN_HCTS0_A
- GPIO_FN_HCTS0_B
- GPIO_FN_HCTS0_C
- GPIO_FN_HCTS0_D
- GPIO_FN_HIFCS
- GPIO_FN_HIFD00
- GPIO_FN_HIFD01
- GPIO_FN_HIFD02
- GPIO_FN_HIFD03
- GPIO_FN_HIFD04
- GPIO_FN_HIFD05
- GPIO_FN_HIFD06
- GPIO_FN_HIFD07
- GPIO_FN_HIFD08
- GPIO_FN_HIFD09
- GPIO_FN_HIFD10
- GPIO_FN_HIFD11
- GPIO_FN_HIFD12
- GPIO_FN_HIFD13
- GPIO_FN_HIFD14
- GPIO_FN_HIFD15
- GPIO_FN_HIFDREQ
- GPIO_FN_HIFEBL_A
- GPIO_FN_HIFEBL_B
- GPIO_FN_HIFINT
- GPIO_FN_HIFRD
- GPIO_FN_HIFRDY
- GPIO_FN_HIFRS
- GPIO_FN_HIFWR
- GPIO_FN_HPD48
- GPIO_FN_HPD49
- GPIO_FN_HPD50
- GPIO_FN_HPD51
- GPIO_FN_HPD52
- GPIO_FN_HPD53
- GPIO_FN_HPD54
- GPIO_FN_HPD55
- GPIO_FN_HPD56
- GPIO_FN_HPD57
- GPIO_FN_HPD58
- GPIO_FN_HPD59
- GPIO_FN_HPD60
- GPIO_FN_HPD61
- GPIO_FN_HPD62
- GPIO_FN_HPD63
- GPIO_FN_HPDQM4
- GPIO_FN_HPDQM5
- GPIO_FN_HPDQM6
- GPIO_FN_HPDQM7
- GPIO_FN_HRTS0_A
- GPIO_FN_HRTS0_B
- GPIO_FN_HRTS0_C
- GPIO_FN_HRTS0_D
- GPIO_FN_HRX0_A
- GPIO_FN_HRX0_B
- GPIO_FN_HRX0_C
- GPIO_FN_HRX0_D
- GPIO_FN_HSCK0_A
- GPIO_FN_HSCK0_B
- GPIO_FN_HSCK0_C
- GPIO_FN_HSCK0_D
- GPIO_FN_HSPI_CLK
- GPIO_FN_HSPI_CLK0_C
- GPIO_FN_HSPI_CLK_A
- GPIO_FN_HSPI_CLK_B
- GPIO_FN_HSPI_CS
- GPIO_FN_HSPI_CS0_C
- GPIO_FN_HSPI_CS_A
- GPIO_FN_HSPI_CS_B
- GPIO_FN_HSPI_RX
- GPIO_FN_HSPI_RX0_C
- GPIO_FN_HSPI_RX_A
- GPIO_FN_HSPI_RX_B
- GPIO_FN_HSPI_TX
- GPIO_FN_HSPI_TX0_C
- GPIO_FN_HSPI_TX_A
- GPIO_FN_HSPI_TX_B
- GPIO_FN_HSYNC
- GPIO_FN_HTX0_A
- GPIO_FN_HTX0_B
- GPIO_FN_HTX0_C
- GPIO_FN_HTX0_D
- GPIO_FN_ICIORD
- GPIO_FN_ICIOWRAH
- GPIO_FN_IDEA0
- GPIO_FN_IDEA1
- GPIO_FN_IDEA2
- GPIO_FN_IDECS0
- GPIO_FN_IDECS1
- GPIO_FN_IDED0
- GPIO_FN_IDED1
- GPIO_FN_IDED10
- GPIO_FN_IDED11
- GPIO_FN_IDED12
- GPIO_FN_IDED13
- GPIO_FN_IDED14
- GPIO_FN_IDED15
- GPIO_FN_IDED2
- GPIO_FN_IDED3
- GPIO_FN_IDED4
- GPIO_FN_IDED5
- GPIO_FN_IDED6
- GPIO_FN_IDED7
- GPIO_FN_IDED8
- GPIO_FN_IDED9
- GPIO_FN_IDEINT
- GPIO_FN_IDEIORD
- GPIO_FN_IDEIORDY
- GPIO_FN_IDEIOWR
- GPIO_FN_IDERST
- GPIO_FN_IECLK_A
- GPIO_FN_IECLK_B
- GPIO_FN_IERX_A
- GPIO_FN_IERX_B
- GPIO_FN_IETX_A
- GPIO_FN_IETX_B
- GPIO_FN_IIC_SCL
- GPIO_FN_IIC_SDA
- GPIO_FN_INTA
- GPIO_FN_INTB
- GPIO_FN_INTC
- GPIO_FN_INTC_IRQ0
- GPIO_FN_INTC_IRQ1
- GPIO_FN_INTC_IRQ2
- GPIO_FN_INTC_IRQ3
- GPIO_FN_INTC_IRQ4
- GPIO_FN_INTC_IRQ5
- GPIO_FN_INTC_IRQ6
- GPIO_FN_INTC_IRQ7
- GPIO_FN_INTD
- GPIO_FN_IODACK
- GPIO_FN_IODREQ
- GPIO_FN_IOIS16
- GPIO_FN_IRDA_IN
- GPIO_FN_IRDA_OUT
- GPIO_FN_IRDY_HSYNC
- GPIO_FN_IRL0
- GPIO_FN_IRL1
- GPIO_FN_IRL2
- GPIO_FN_IRL3
- GPIO_FN_IRL4
- GPIO_FN_IRL5
- GPIO_FN_IRL6
- GPIO_FN_IRL7
- GPIO_FN_IRQ0
- GPIO_FN_IRQ0_A
- GPIO_FN_IRQ0_B
- GPIO_FN_IRQ0_IRL0
- GPIO_FN_IRQ0_PB
- GPIO_FN_IRQ0_PC
- GPIO_FN_IRQ0_PD
- GPIO_FN_IRQ0_PE
- GPIO_FN_IRQ0_PG
- GPIO_FN_IRQ0_PJ
- GPIO_FN_IRQ1
- GPIO_FN_IRQ10
- GPIO_FN_IRQ11
- GPIO_FN_IRQ12
- GPIO_FN_IRQ13
- GPIO_FN_IRQ14
- GPIO_FN_IRQ15
- GPIO_FN_IRQ1_A
- GPIO_FN_IRQ1_B
- GPIO_FN_IRQ1_IRL1
- GPIO_FN_IRQ1_PB
- GPIO_FN_IRQ1_PC
- GPIO_FN_IRQ1_PD
- GPIO_FN_IRQ1_PE
- GPIO_FN_IRQ1_PG
- GPIO_FN_IRQ1_PJ
- GPIO_FN_IRQ2
- GPIO_FN_IRQ2_A
- GPIO_FN_IRQ2_B
- GPIO_FN_IRQ2_IRL2
- GPIO_FN_IRQ2_PB
- GPIO_FN_IRQ2_PD
- GPIO_FN_IRQ2_PE
- GPIO_FN_IRQ2_PG
- GPIO_FN_IRQ2_PJ
- GPIO_FN_IRQ3
- GPIO_FN_IRQ3_A
- GPIO_FN_IRQ3_B
- GPIO_FN_IRQ3_IRL3
- GPIO_FN_IRQ3_PB
- GPIO_FN_IRQ3_PD
- GPIO_FN_IRQ3_PE
- GPIO_FN_IRQ3_PG
- GPIO_FN_IRQ3_PJ
- GPIO_FN_IRQ4
- GPIO_FN_IRQ4_PB
- GPIO_FN_IRQ4_PC
- GPIO_FN_IRQ4_PD
- GPIO_FN_IRQ4_PE
- GPIO_FN_IRQ4_PF
- GPIO_FN_IRQ4_PG
- GPIO_FN_IRQ5
- GPIO_FN_IRQ5_PB
- GPIO_FN_IRQ5_PC
- GPIO_FN_IRQ5_PD
- GPIO_FN_IRQ5_PE
- GPIO_FN_IRQ5_PF
- GPIO_FN_IRQ5_PG
- GPIO_FN_IRQ6
- GPIO_FN_IRQ6_PB
- GPIO_FN_IRQ6_PC
- GPIO_FN_IRQ6_PD
- GPIO_FN_IRQ6_PE
- GPIO_FN_IRQ6_PF
- GPIO_FN_IRQ6_PG
- GPIO_FN_IRQ7
- GPIO_FN_IRQ7_PB
- GPIO_FN_IRQ7_PC
- GPIO_FN_IRQ7_PD
- GPIO_FN_IRQ7_PE
- GPIO_FN_IRQ7_PF
- GPIO_FN_IRQ7_PG
- GPIO_FN_IRQ8
- GPIO_FN_IRQ9
- GPIO_FN_IRQOUT
- GPIO_FN_IRQOUT_REFOUT
- GPIO_FN_JMCTCK
- GPIO_FN_JMCTDI
- GPIO_FN_JMCTDO
- GPIO_FN_JMCTMS
- GPIO_FN_JMCTRST
- GPIO_FN_KEYIN0
- GPIO_FN_KEYIN1
- GPIO_FN_KEYIN2
- GPIO_FN_KEYIN3
- GPIO_FN_KEYIN4
- GPIO_FN_KEYOUT0
- GPIO_FN_KEYOUT1
- GPIO_FN_KEYOUT2
- GPIO_FN_KEYOUT3
- GPIO_FN_KEYOUT4_IN6
- GPIO_FN_KEYOUT5_IN5
- GPIO_FN_LAD0
- GPIO_FN_LAD1
- GPIO_FN_LAD2
- GPIO_FN_LAD3
- GPIO_FN_LCDCS
- GPIO_FN_LCDCS2
- GPIO_FN_LCDD0
- GPIO_FN_LCDD1
- GPIO_FN_LCDD10
- GPIO_FN_LCDD11
- GPIO_FN_LCDD12
- GPIO_FN_LCDD13
- GPIO_FN_LCDD14
- GPIO_FN_LCDD15
- GPIO_FN_LCDD16
- GPIO_FN_LCDD17
- GPIO_FN_LCDD18
- GPIO_FN_LCDD19
- GPIO_FN_LCDD2
- GPIO_FN_LCDD20
- GPIO_FN_LCDD21
- GPIO_FN_LCDD22
- GPIO_FN_LCDD23
- GPIO_FN_LCDD3
- GPIO_FN_LCDD4
- GPIO_FN_LCDD5
- GPIO_FN_LCDD6
- GPIO_FN_LCDD7
- GPIO_FN_LCDD8
- GPIO_FN_LCDD9
- GPIO_FN_LCDDCK
- GPIO_FN_LCDDISP
- GPIO_FN_LCDDON
- GPIO_FN_LCDDON2
- GPIO_FN_LCDHSYN
- GPIO_FN_LCDLCLK
- GPIO_FN_LCDLCLK_PTR
- GPIO_FN_LCDLCLK_PTW
- GPIO_FN_LCDRD
- GPIO_FN_LCDRS
- GPIO_FN_LCDVCPWC
- GPIO_FN_LCDVCPWC2
- GPIO_FN_LCDVEPWC
- GPIO_FN_LCDVEPWC2
- GPIO_FN_LCDVSYN
- GPIO_FN_LCDVSYN2
- GPIO_FN_LCDWR
- GPIO_FN_LCD_CL1
- GPIO_FN_LCD_CL1_A
- GPIO_FN_LCD_CL1_B
- GPIO_FN_LCD_CL2
- GPIO_FN_LCD_CL2_A
- GPIO_FN_LCD_CL2_B
- GPIO_FN_LCD_CLK
- GPIO_FN_LCD_CLK_A
- GPIO_FN_LCD_CLK_B
- GPIO_FN_LCD_DATA0
- GPIO_FN_LCD_DATA0_A
- GPIO_FN_LCD_DATA0_B
- GPIO_FN_LCD_DATA0_PG0
- GPIO_FN_LCD_DATA0_PJ0
- GPIO_FN_LCD_DATA1
- GPIO_FN_LCD_DATA10
- GPIO_FN_LCD_DATA10_A
- GPIO_FN_LCD_DATA10_B
- GPIO_FN_LCD_DATA10_PG10
- GPIO_FN_LCD_DATA10_PJ10
- GPIO_FN_LCD_DATA11
- GPIO_FN_LCD_DATA11_A
- GPIO_FN_LCD_DATA11_B
- GPIO_FN_LCD_DATA11_PG11
- GPIO_FN_LCD_DATA11_PJ11
- GPIO_FN_LCD_DATA12
- GPIO_FN_LCD_DATA12_A
- GPIO_FN_LCD_DATA12_B
- GPIO_FN_LCD_DATA12_PG12
- GPIO_FN_LCD_DATA12_PJ12
- GPIO_FN_LCD_DATA13
- GPIO_FN_LCD_DATA13_A
- GPIO_FN_LCD_DATA13_B
- GPIO_FN_LCD_DATA13_PG13
- GPIO_FN_LCD_DATA13_PJ13
- GPIO_FN_LCD_DATA14
- GPIO_FN_LCD_DATA14_A
- GPIO_FN_LCD_DATA14_B
- GPIO_FN_LCD_DATA14_PG14
- GPIO_FN_LCD_DATA14_PJ14
- GPIO_FN_LCD_DATA15
- GPIO_FN_LCD_DATA15_A
- GPIO_FN_LCD_DATA15_B
- GPIO_FN_LCD_DATA15_PG15
- GPIO_FN_LCD_DATA15_PJ15
- GPIO_FN_LCD_DATA16_PG16
- GPIO_FN_LCD_DATA16_PJ16
- GPIO_FN_LCD_DATA17_PG17
- GPIO_FN_LCD_DATA17_PJ17
- GPIO_FN_LCD_DATA18_PG18
- GPIO_FN_LCD_DATA18_PJ18
- GPIO_FN_LCD_DATA19_PG19
- GPIO_FN_LCD_DATA19_PJ19
- GPIO_FN_LCD_DATA1_A
- GPIO_FN_LCD_DATA1_B
- GPIO_FN_LCD_DATA1_PG1
- GPIO_FN_LCD_DATA1_PJ1
- GPIO_FN_LCD_DATA2
- GPIO_FN_LCD_DATA20_PG20
- GPIO_FN_LCD_DATA20_PJ20
- GPIO_FN_LCD_DATA21_PG21
- GPIO_FN_LCD_DATA21_PJ21
- GPIO_FN_LCD_DATA22_PG22
- GPIO_FN_LCD_DATA22_PJ22
- GPIO_FN_LCD_DATA23_PG23
- GPIO_FN_LCD_DATA23_PJ23
- GPIO_FN_LCD_DATA2_A
- GPIO_FN_LCD_DATA2_B
- GPIO_FN_LCD_DATA2_PG2
- GPIO_FN_LCD_DATA2_PJ2
- GPIO_FN_LCD_DATA3
- GPIO_FN_LCD_DATA3_A
- GPIO_FN_LCD_DATA3_B
- GPIO_FN_LCD_DATA3_PG3
- GPIO_FN_LCD_DATA3_PJ3
- GPIO_FN_LCD_DATA4
- GPIO_FN_LCD_DATA4_A
- GPIO_FN_LCD_DATA4_B
- GPIO_FN_LCD_DATA4_PG4
- GPIO_FN_LCD_DATA4_PJ4
- GPIO_FN_LCD_DATA5
- GPIO_FN_LCD_DATA5_A
- GPIO_FN_LCD_DATA5_B
- GPIO_FN_LCD_DATA5_PG5
- GPIO_FN_LCD_DATA5_PJ5
- GPIO_FN_LCD_DATA6
- GPIO_FN_LCD_DATA6_A
- GPIO_FN_LCD_DATA6_B
- GPIO_FN_LCD_DATA6_PG6
- GPIO_FN_LCD_DATA6_PJ6
- GPIO_FN_LCD_DATA7
- GPIO_FN_LCD_DATA7_A
- GPIO_FN_LCD_DATA7_B
- GPIO_FN_LCD_DATA7_PG7
- GPIO_FN_LCD_DATA7_PJ7
- GPIO_FN_LCD_DATA8
- GPIO_FN_LCD_DATA8_A
- GPIO_FN_LCD_DATA8_B
- GPIO_FN_LCD_DATA8_PG8
- GPIO_FN_LCD_DATA8_PJ8
- GPIO_FN_LCD_DATA9
- GPIO_FN_LCD_DATA9_A
- GPIO_FN_LCD_DATA9_B
- GPIO_FN_LCD_DATA9_PG9
- GPIO_FN_LCD_DATA9_PJ9
- GPIO_FN_LCD_DE
- GPIO_FN_LCD_DON
- GPIO_FN_LCD_DON_A
- GPIO_FN_LCD_DON_B
- GPIO_FN_LCD_EXTCLK
- GPIO_FN_LCD_FLM
- GPIO_FN_LCD_FLM_A
- GPIO_FN_LCD_FLM_B
- GPIO_FN_LCD_HSYNC
- GPIO_FN_LCD_M_DISP
- GPIO_FN_LCD_M_DISP_A
- GPIO_FN_LCD_M_DISP_B
- GPIO_FN_LCD_VCPWC
- GPIO_FN_LCD_VCPWC_A
- GPIO_FN_LCD_VCPWC_B
- GPIO_FN_LCD_VEPWC
- GPIO_FN_LCD_VEPWC_A
- GPIO_FN_LCD_VEPWC_B
- GPIO_FN_LCD_VSYNC
- GPIO_FN_LCLK
- GPIO_FN_LDRQ
- GPIO_FN_LFRAME
- GPIO_FN_LGPIO0
- GPIO_FN_LGPIO1
- GPIO_FN_LGPIO2
- GPIO_FN_LGPIO3
- GPIO_FN_LGPIO4
- GPIO_FN_LGPIO5
- GPIO_FN_LGPIO6
- GPIO_FN_LGPIO7
- GPIO_FN_LNKSTA
- GPIO_FN_LOCK_ODDF
- GPIO_FN_LPCPD
- GPIO_FN_LRESET
- GPIO_FN_MDC
- GPIO_FN_MDIO
- GPIO_FN_MISO0_PB20
- GPIO_FN_MISO0_PF12
- GPIO_FN_MISO0_PJ19
- GPIO_FN_MISO1
- GPIO_FN_MISO1_PG19
- GPIO_FN_MLB_CLK
- GPIO_FN_MLB_DAT
- GPIO_FN_MLB_SIG
- GPIO_FN_MMCCLK
- GPIO_FN_MMCCMD
- GPIO_FN_MMCDAT
- GPIO_FN_MMCDAT0
- GPIO_FN_MMCDAT1
- GPIO_FN_MMCDAT2
- GPIO_FN_MMCDAT3
- GPIO_FN_MMCDAT4
- GPIO_FN_MMCDAT5
- GPIO_FN_MMCDAT6
- GPIO_FN_MMCDAT7
- GPIO_FN_MMC_CLK
- GPIO_FN_MMC_CLK_A
- GPIO_FN_MMC_CMD
- GPIO_FN_MMC_CMD_A
- GPIO_FN_MMC_D0
- GPIO_FN_MMC_D0_A
- GPIO_FN_MMC_D1
- GPIO_FN_MMC_D1_A
- GPIO_FN_MMC_D2
- GPIO_FN_MMC_D2_A
- GPIO_FN_MMC_D3
- GPIO_FN_MMC_D3_A
- GPIO_FN_MMC_D4
- GPIO_FN_MMC_D4_A
- GPIO_FN_MMC_D5
- GPIO_FN_MMC_D5_A
- GPIO_FN_MMC_D6
- GPIO_FN_MMC_D6_A
- GPIO_FN_MMC_D7
- GPIO_FN_MMC_D7_A
- GPIO_FN_MMC_DAT
- GPIO_FN_MMC_ODMOD
- GPIO_FN_MMC_VDDON
- GPIO_FN_MOSI0
- GPIO_FN_MOSI0_PB19
- GPIO_FN_MOSI0_PJ18
- GPIO_FN_MOSI1
- GPIO_FN_MRES
- GPIO_FN_MRESETOUT
- GPIO_FN_MSIOF0_MCK
- GPIO_FN_MSIOF0_PTF_MCK
- GPIO_FN_MSIOF0_PTF_RSCK
- GPIO_FN_MSIOF0_PTF_RSYNC
- GPIO_FN_MSIOF0_PTF_RXD
- GPIO_FN_MSIOF0_PTF_SS1
- GPIO_FN_MSIOF0_PTF_SS2
- GPIO_FN_MSIOF0_PTF_TSCK
- GPIO_FN_MSIOF0_PTF_TSYNC
- GPIO_FN_MSIOF0_PTF_TXD
- GPIO_FN_MSIOF0_PTT_RSCK
- GPIO_FN_MSIOF0_PTT_RSYNC
- GPIO_FN_MSIOF0_PTT_RXD
- GPIO_FN_MSIOF0_PTT_SS1
- GPIO_FN_MSIOF0_PTT_SS2
- GPIO_FN_MSIOF0_PTT_TSCK
- GPIO_FN_MSIOF0_PTT_TSYNC
- GPIO_FN_MSIOF0_PTT_TXD
- GPIO_FN_MSIOF0_PTX_MCK
- GPIO_FN_MSIOF0_RSCK
- GPIO_FN_MSIOF0_RSYNC
- GPIO_FN_MSIOF0_RXD
- GPIO_FN_MSIOF0_SS1
- GPIO_FN_MSIOF0_SS2
- GPIO_FN_MSIOF0_TSCK
- GPIO_FN_MSIOF0_TSYNC
- GPIO_FN_MSIOF0_TXD
- GPIO_FN_MSIOF1_MCK
- GPIO_FN_MSIOF1_RSCK
- GPIO_FN_MSIOF1_RSYNC
- GPIO_FN_MSIOF1_RXD
- GPIO_FN_MSIOF1_SS1
- GPIO_FN_MSIOF1_SS2
- GPIO_FN_MSIOF1_TSCK
- GPIO_FN_MSIOF1_TSYNC
- GPIO_FN_MSIOF1_TXD
- GPIO_FN_NAF0
- GPIO_FN_NAF1
- GPIO_FN_NAF2
- GPIO_FN_NAF3
- GPIO_FN_NAF4
- GPIO_FN_NAF5
- GPIO_FN_NAF6
- GPIO_FN_NAF7
- GPIO_FN_ODDF
- GPIO_FN_ON_ALE
- GPIO_FN_ON_CLE
- GPIO_FN_ON_DQ0
- GPIO_FN_ON_DQ1
- GPIO_FN_ON_DQ2
- GPIO_FN_ON_DQ3
- GPIO_FN_ON_DQ4
- GPIO_FN_ON_DQ5
- GPIO_FN_ON_DQ6
- GPIO_FN_ON_DQ7
- GPIO_FN_ON_NCE0
- GPIO_FN_ON_NRE
- GPIO_FN_ON_NWE
- GPIO_FN_ON_NWP
- GPIO_FN_ON_R_B0
- GPIO_FN_PCC_BVD1
- GPIO_FN_PCC_BVD2
- GPIO_FN_PCC_CD1
- GPIO_FN_PCC_CD2
- GPIO_FN_PCC_DRV
- GPIO_FN_PCC_RDY
- GPIO_FN_PCC_REG
- GPIO_FN_PCC_RESET
- GPIO_FN_PCC_VS1
- GPIO_FN_PCC_VS2
- GPIO_FN_PCIFRAME_VSYNC
- GPIO_FN_PDSTATUS
- GPIO_FN_PENC0
- GPIO_FN_PENC1
- GPIO_FN_PERR
- GPIO_FN_PINT0_PB
- GPIO_FN_PINT0_PD
- GPIO_FN_PINT0_PG
- GPIO_FN_PINT0_PH
- GPIO_FN_PINT0_PJ
- GPIO_FN_PINT1_PB
- GPIO_FN_PINT1_PD
- GPIO_FN_PINT1_PG
- GPIO_FN_PINT1_PH
- GPIO_FN_PINT1_PJ
- GPIO_FN_PINT2_PB
- GPIO_FN_PINT2_PD
- GPIO_FN_PINT2_PG
- GPIO_FN_PINT2_PH
- GPIO_FN_PINT2_PJ
- GPIO_FN_PINT3_PB
- GPIO_FN_PINT3_PD
- GPIO_FN_PINT3_PG
- GPIO_FN_PINT3_PH
- GPIO_FN_PINT3_PJ
- GPIO_FN_PINT4_PB
- GPIO_FN_PINT4_PD
- GPIO_FN_PINT4_PG
- GPIO_FN_PINT4_PH
- GPIO_FN_PINT4_PJ
- GPIO_FN_PINT5_PB
- GPIO_FN_PINT5_PD
- GPIO_FN_PINT5_PG
- GPIO_FN_PINT5_PH
- GPIO_FN_PINT5_PJ
- GPIO_FN_PINT6_PB
- GPIO_FN_PINT6_PD
- GPIO_FN_PINT6_PG
- GPIO_FN_PINT6_PH
- GPIO_FN_PINT6_PJ
- GPIO_FN_PINT7_PB
- GPIO_FN_PINT7_PD
- GPIO_FN_PINT7_PG
- GPIO_FN_PINT7_PH
- GPIO_FN_PINT7_PJ
- GPIO_FN_PRESETOUT
- GPIO_FN_PWMU0
- GPIO_FN_PWMU1
- GPIO_FN_PWMU2
- GPIO_FN_PWMU3
- GPIO_FN_PWMU4
- GPIO_FN_PWMU5
- GPIO_FN_PWMX0
- GPIO_FN_PWMX1
- GPIO_FN_PWMX2
- GPIO_FN_PWMX3
- GPIO_FN_PWMX4
- GPIO_FN_PWMX5
- GPIO_FN_PWMX6
- GPIO_FN_PWMX7
- GPIO_FN_QIO2_A
- GPIO_FN_QIO2_B
- GPIO_FN_QIO3_A
- GPIO_FN_QIO3_B
- GPIO_FN_QMI_QIO1_A
- GPIO_FN_QMI_QIO1_B
- GPIO_FN_QMO_QIO0_A
- GPIO_FN_QMO_QIO0_B
- GPIO_FN_QSPCLK_A
- GPIO_FN_QSPCLK_B
- GPIO_FN_QSSL_A
- GPIO_FN_QSSL_B
- GPIO_FN_RAC_CTS
- GPIO_FN_RAC_DCD
- GPIO_FN_RAC_DSR
- GPIO_FN_RAC_DTR
- GPIO_FN_RAC_RI
- GPIO_FN_RAC_RTS
- GPIO_FN_RAC_RXD
- GPIO_FN_RAC_TXD
- GPIO_FN_RAS
- GPIO_FN_RASL
- GPIO_FN_RASU
- GPIO_FN_RD
- GPIO_FN_RDWR
- GPIO_FN_RDY
- GPIO_FN_RD_WR
- GPIO_FN_REF125CK
- GPIO_FN_REF50CK
- GPIO_FN_REFOUT
- GPIO_FN_REQ0_REQOUT
- GPIO_FN_REQ1
- GPIO_FN_REQ2
- GPIO_FN_REQ3
- GPIO_FN_RMII0_CRS_DV
- GPIO_FN_RMII0_CRS_DV_A
- GPIO_FN_RMII0_CRS_DV_B
- GPIO_FN_RMII0_MDC_A
- GPIO_FN_RMII0_MDC_B
- GPIO_FN_RMII0_MDIO_A
- GPIO_FN_RMII0_MDIO_B
- GPIO_FN_RMII0_REFCLK
- GPIO_FN_RMII0_RXD0
- GPIO_FN_RMII0_RXD0_A
- GPIO_FN_RMII0_RXD0_B
- GPIO_FN_RMII0_RXD1
- GPIO_FN_RMII0_RXD1_A
- GPIO_FN_RMII0_RXD1_B
- GPIO_FN_RMII0_RX_ER
- GPIO_FN_RMII0_RX_ER_A
- GPIO_FN_RMII0_RX_ER_B
- GPIO_FN_RMII0_TXD0
- GPIO_FN_RMII0_TXD0_A
- GPIO_FN_RMII0_TXD0_B
- GPIO_FN_RMII0_TXD1
- GPIO_FN_RMII0_TXD1_A
- GPIO_FN_RMII0_TXD1_B
- GPIO_FN_RMII0_TXD_EN_A
- GPIO_FN_RMII0_TXD_EN_B
- GPIO_FN_RMII0_TXEN
- GPIO_FN_RMII1_CRS_DV
- GPIO_FN_RMII1_REFCLK
- GPIO_FN_RMII1_RXD0
- GPIO_FN_RMII1_RXD1
- GPIO_FN_RMII1_RX_ER
- GPIO_FN_RMII1_TXD0
- GPIO_FN_RMII1_TXD1
- GPIO_FN_RMII1_TXEN
- GPIO_FN_RMII_CRS_DV
- GPIO_FN_RMII_REF_CLK
- GPIO_FN_RMII_RXD0
- GPIO_FN_RMII_RXD1
- GPIO_FN_RMII_RX_ER
- GPIO_FN_RMII_TXD0
- GPIO_FN_RMII_TXD1
- GPIO_FN_RMII_TX_EN
- GPIO_FN_RSPCK0
- GPIO_FN_RSPCK0_PB17
- GPIO_FN_RSPCK0_PJ16
- GPIO_FN_RSPCK1
- GPIO_FN_RSPI_MISO_A
- GPIO_FN_RSPI_MOSI_A
- GPIO_FN_RSPI_RSPCK_A
- GPIO_FN_RSPI_SSL_A
- GPIO_FN_RTS0_A
- GPIO_FN_RTS0_B
- GPIO_FN_RTS0_C
- GPIO_FN_RTS1
- GPIO_FN_RTS1_A
- GPIO_FN_RTS1_B
- GPIO_FN_RTS1_C
- GPIO_FN_RTS1_E
- GPIO_FN_RTS2
- GPIO_FN_RTS3
- GPIO_FN_RTS4
- GPIO_FN_RTS5
- GPIO_FN_RTS7
- GPIO_FN_RX0_A
- GPIO_FN_RX0_B
- GPIO_FN_RX1_A
- GPIO_FN_RX1_B
- GPIO_FN_RX1_C
- GPIO_FN_RX1_D
- GPIO_FN_RX1_E
- GPIO_FN_RX2_A
- GPIO_FN_RX2_B
- GPIO_FN_RX2_C
- GPIO_FN_RX2_D
- GPIO_FN_RX3_A
- GPIO_FN_RX3_B
- GPIO_FN_RX3_C
- GPIO_FN_RX3_D
- GPIO_FN_RX3_E
- GPIO_FN_RX4_A
- GPIO_FN_RX4_B
- GPIO_FN_RX4_C
- GPIO_FN_RX4_D
- GPIO_FN_RX5_A
- GPIO_FN_RX5_B
- GPIO_FN_RX5_C
- GPIO_FN_RX5_D
- GPIO_FN_RXD0
- GPIO_FN_RXD1
- GPIO_FN_RXD2
- GPIO_FN_RXD3
- GPIO_FN_RXD4
- GPIO_FN_RXD5
- GPIO_FN_RXD6
- GPIO_FN_RXD7
- GPIO_FN_R_SPI_MISO
- GPIO_FN_R_SPI_MOSI
- GPIO_FN_R_SPI_RSPCK
- GPIO_FN_R_SPI_SSL0
- GPIO_FN_R_SPI_SSL1
- GPIO_FN_SCIF0_CTS
- GPIO_FN_SCIF0_PTT_RXD
- GPIO_FN_SCIF0_PTT_SCK
- GPIO_FN_SCIF0_PTT_TXD
- GPIO_FN_SCIF0_PTU_RXD
- GPIO_FN_SCIF0_PTU_SCK
- GPIO_FN_SCIF0_PTU_TXD
- GPIO_FN_SCIF0_RTS
- GPIO_FN_SCIF0_RXD
- GPIO_FN_SCIF0_SCK
- GPIO_FN_SCIF0_TXD
- GPIO_FN_SCIF1_CTS
- GPIO_FN_SCIF1_PTS_RXD
- GPIO_FN_SCIF1_PTS_SCK
- GPIO_FN_SCIF1_PTS_TXD
- GPIO_FN_SCIF1_PTV_RXD
- GPIO_FN_SCIF1_PTV_SCK
- GPIO_FN_SCIF1_PTV_TXD
- GPIO_FN_SCIF1_RTS
- GPIO_FN_SCIF1_RXD
- GPIO_FN_SCIF1_SCK
- GPIO_FN_SCIF1_TXD
- GPIO_FN_SCIF2_CTS
- GPIO_FN_SCIF2_L_RXD
- GPIO_FN_SCIF2_L_SCK
- GPIO_FN_SCIF2_L_TXD
- GPIO_FN_SCIF2_PTT_RXD
- GPIO_FN_SCIF2_PTT_SCK
- GPIO_FN_SCIF2_PTT_TXD
- GPIO_FN_SCIF2_PTU_RXD
- GPIO_FN_SCIF2_PTU_SCK
- GPIO_FN_SCIF2_PTU_TXD
- GPIO_FN_SCIF2_RTS
- GPIO_FN_SCIF2_RXD
- GPIO_FN_SCIF2_SCK
- GPIO_FN_SCIF2_TXD
- GPIO_FN_SCIF2_V_RXD
- GPIO_FN_SCIF2_V_SCK
- GPIO_FN_SCIF2_V_TXD
- GPIO_FN_SCIF3_I_CTS
- GPIO_FN_SCIF3_I_RTS
- GPIO_FN_SCIF3_I_RXD
- GPIO_FN_SCIF3_I_SCK
- GPIO_FN_SCIF3_I_TXD
- GPIO_FN_SCIF3_PTS_CTS
- GPIO_FN_SCIF3_PTS_RTS
- GPIO_FN_SCIF3_PTS_RXD
- GPIO_FN_SCIF3_PTS_SCK
- GPIO_FN_SCIF3_PTS_TXD
- GPIO_FN_SCIF3_PTV_CTS
- GPIO_FN_SCIF3_PTV_RTS
- GPIO_FN_SCIF3_PTV_RXD
- GPIO_FN_SCIF3_PTV_SCK
- GPIO_FN_SCIF3_PTV_TXD
- GPIO_FN_SCIF3_RXD
- GPIO_FN_SCIF3_SCK
- GPIO_FN_SCIF3_TXD
- GPIO_FN_SCIF3_V_CTS
- GPIO_FN_SCIF3_V_RTS
- GPIO_FN_SCIF3_V_RXD
- GPIO_FN_SCIF3_V_SCK
- GPIO_FN_SCIF3_V_TXD
- GPIO_FN_SCIF4_PTE_RXD
- GPIO_FN_SCIF4_PTE_SCK
- GPIO_FN_SCIF4_PTE_TXD
- GPIO_FN_SCIF4_PTN_RXD
- GPIO_FN_SCIF4_PTN_SCK
- GPIO_FN_SCIF4_PTN_TXD
- GPIO_FN_SCIF4_RXD
- GPIO_FN_SCIF4_SCK
- GPIO_FN_SCIF4_TXD
- GPIO_FN_SCIF5_PTE_RXD
- GPIO_FN_SCIF5_PTE_SCK
- GPIO_FN_SCIF5_PTE_TXD
- GPIO_FN_SCIF5_PTN_RXD
- GPIO_FN_SCIF5_PTN_SCK
- GPIO_FN_SCIF5_PTN_TXD
- GPIO_FN_SCIF5_RXD
- GPIO_FN_SCIF5_SCK
- GPIO_FN_SCIF5_TXD
- GPIO_FN_SCIF_CLK_A
- GPIO_FN_SCIF_CLK_B
- GPIO_FN_SCIF_CLK_C
- GPIO_FN_SCK0
- GPIO_FN_SCK0_A
- GPIO_FN_SCK0_B
- GPIO_FN_SCK1
- GPIO_FN_SCK1_A
- GPIO_FN_SCK1_B
- GPIO_FN_SCK1_C
- GPIO_FN_SCK1_D
- GPIO_FN_SCK1_E
- GPIO_FN_SCK2
- GPIO_FN_SCK2_A
- GPIO_FN_SCK2_B
- GPIO_FN_SCK2_C
- GPIO_FN_SCK3
- GPIO_FN_SCK4
- GPIO_FN_SCK5
- GPIO_FN_SCK6
- GPIO_FN_SCK7
- GPIO_FN_SCL0
- GPIO_FN_SCL1
- GPIO_FN_SCL2
- GPIO_FN_SCL3
- GPIO_FN_SCL4
- GPIO_FN_SCL5
- GPIO_FN_SCL6
- GPIO_FN_SCL7
- GPIO_FN_SCL8
- GPIO_FN_SCL9
- GPIO_FN_SCS0_PD
- GPIO_FN_SCS0_PF
- GPIO_FN_SCS1_PD
- GPIO_FN_SCS1_PF
- GPIO_FN_SD0_CD_A
- GPIO_FN_SD0_CLK_A
- GPIO_FN_SD0_CMD_A
- GPIO_FN_SD0_DAT0_A
- GPIO_FN_SD0_DAT1_A
- GPIO_FN_SD0_DAT2_A
- GPIO_FN_SD0_DAT3_A
- GPIO_FN_SD0_WP_A
- GPIO_FN_SD1_CD_A
- GPIO_FN_SD1_CLK_A
- GPIO_FN_SD1_CMD_A
- GPIO_FN_SD1_DAT0_A
- GPIO_FN_SD1_DAT1_A
- GPIO_FN_SD1_DAT2_A
- GPIO_FN_SD1_DAT3_A
- GPIO_FN_SD1_WP_A
- GPIO_FN_SD2_CD_A
- GPIO_FN_SD2_CLK_A
- GPIO_FN_SD2_CMD_A
- GPIO_FN_SD2_DAT0_A
- GPIO_FN_SD2_DAT1_A
- GPIO_FN_SD2_DAT2_A
- GPIO_FN_SD2_DAT3_A
- GPIO_FN_SD2_WP_A
- GPIO_FN_SDA0
- GPIO_FN_SDA1
- GPIO_FN_SDA2
- GPIO_FN_SDA3
- GPIO_FN_SDA4
- GPIO_FN_SDA5
- GPIO_FN_SDA6
- GPIO_FN_SDA7
- GPIO_FN_SDA8
- GPIO_FN_SDA9
- GPIO_FN_SDHI0CD
- GPIO_FN_SDHI0CD_PTD
- GPIO_FN_SDHI0CD_PTS
- GPIO_FN_SDHI0CLK
- GPIO_FN_SDHI0CLK_PTD
- GPIO_FN_SDHI0CLK_PTS
- GPIO_FN_SDHI0CMD
- GPIO_FN_SDHI0CMD_PTD
- GPIO_FN_SDHI0CMD_PTS
- GPIO_FN_SDHI0D0
- GPIO_FN_SDHI0D0_PTD
- GPIO_FN_SDHI0D0_PTS
- GPIO_FN_SDHI0D1
- GPIO_FN_SDHI0D1_PTD
- GPIO_FN_SDHI0D1_PTS
- GPIO_FN_SDHI0D2
- GPIO_FN_SDHI0D2_PTD
- GPIO_FN_SDHI0D2_PTS
- GPIO_FN_SDHI0D3
- GPIO_FN_SDHI0D3_PTD
- GPIO_FN_SDHI0D3_PTS
- GPIO_FN_SDHI0WP
- GPIO_FN_SDHI0WP_PTD
- GPIO_FN_SDHI0WP_PTS
- GPIO_FN_SDHI1CD
- GPIO_FN_SDHI1CLK
- GPIO_FN_SDHI1CMD
- GPIO_FN_SDHI1D0
- GPIO_FN_SDHI1D1
- GPIO_FN_SDHI1D2
- GPIO_FN_SDHI1D3
- GPIO_FN_SDHI1WP
- GPIO_FN_SDHICD
- GPIO_FN_SDHICLK
- GPIO_FN_SDHICMD
- GPIO_FN_SDHID0
- GPIO_FN_SDHID1
- GPIO_FN_SDHID2
- GPIO_FN_SDHID3
- GPIO_FN_SDHIWP
- GPIO_FN_SDIF0CD
- GPIO_FN_SDIF0CLK
- GPIO_FN_SDIF0CMD
- GPIO_FN_SDIF0D0
- GPIO_FN_SDIF0D1
- GPIO_FN_SDIF0D2
- GPIO_FN_SDIF0D3
- GPIO_FN_SDIF0WP
- GPIO_FN_SDIF1CD
- GPIO_FN_SDIF1CLK
- GPIO_FN_SDIF1CMD
- GPIO_FN_SDIF1D0
- GPIO_FN_SDIF1D1
- GPIO_FN_SDIF1D2
- GPIO_FN_SDIF1D3
- GPIO_FN_SDIF1WP
- GPIO_FN_SDSELF
- GPIO_FN_SD_CD
- GPIO_FN_SD_CLK
- GPIO_FN_SD_CMD
- GPIO_FN_SD_D0
- GPIO_FN_SD_D1
- GPIO_FN_SD_D2
- GPIO_FN_SD_D3
- GPIO_FN_SD_WP
- GPIO_FN_SERIRQ
- GPIO_FN_SERR
- GPIO_FN_SGPIO0_CLK
- GPIO_FN_SGPIO0_DI
- GPIO_FN_SGPIO0_DO
- GPIO_FN_SGPIO0_LOAD
- GPIO_FN_SGPIO1_CLK
- GPIO_FN_SGPIO1_DI
- GPIO_FN_SGPIO1_DO
- GPIO_FN_SGPIO1_LOAD
- GPIO_FN_SGPIO2_CLK
- GPIO_FN_SGPIO2_DI
- GPIO_FN_SGPIO2_DO
- GPIO_FN_SGPIO2_LOAD
- GPIO_FN_SIM_CLK
- GPIO_FN_SIM_D
- GPIO_FN_SIM_RST
- GPIO_FN_SIOD
- GPIO_FN_SIOF0_MCK
- GPIO_FN_SIOF0_MCLK
- GPIO_FN_SIOF0_RXD
- GPIO_FN_SIOF0_SCK
- GPIO_FN_SIOF0_SS1
- GPIO_FN_SIOF0_SS2
- GPIO_FN_SIOF0_SYNC
- GPIO_FN_SIOF0_TXD
- GPIO_FN_SIOF1_MCK
- GPIO_FN_SIOF1_MCLK
- GPIO_FN_SIOF1_RXD
- GPIO_FN_SIOF1_SCK
- GPIO_FN_SIOF1_SS1
- GPIO_FN_SIOF1_SS2
- GPIO_FN_SIOF1_SYNC
- GPIO_FN_SIOF1_TXD
- GPIO_FN_SIOFRXD
- GPIO_FN_SIOFSCK
- GPIO_FN_SIOFSYNC
- GPIO_FN_SIOFTXD
- GPIO_FN_SIOF_MCLK_PJ
- GPIO_FN_SIOF_RXD
- GPIO_FN_SIOF_RXD_PJ
- GPIO_FN_SIOF_SCK_PJ
- GPIO_FN_SIOF_SCK_PK
- GPIO_FN_SIOF_SYNC_PJ
- GPIO_FN_SIOF_TXD_PJ
- GPIO_FN_SIOF_TXD_PK
- GPIO_FN_SIOMCK
- GPIO_FN_SIORXD
- GPIO_FN_SIOSCK
- GPIO_FN_SIOSTRB0
- GPIO_FN_SIOSTRB1
- GPIO_FN_SIOTXD
- GPIO_FN_SIUAFCK
- GPIO_FN_SIUAIBT
- GPIO_FN_SIUAILR
- GPIO_FN_SIUAISLD
- GPIO_FN_SIUAISPD
- GPIO_FN_SIUAMCK
- GPIO_FN_SIUAOBT
- GPIO_FN_SIUAOLR
- GPIO_FN_SIUAOSLD
- GPIO_FN_SIUAOSPD
- GPIO_FN_SIUBFCK
- GPIO_FN_SIUBIBT
- GPIO_FN_SIUBILR
- GPIO_FN_SIUBISLD
- GPIO_FN_SIUBMCK
- GPIO_FN_SIUBOBT
- GPIO_FN_SIUBOLR
- GPIO_FN_SIUBOSLD
- GPIO_FN_SIUFCKA
- GPIO_FN_SIUFCKB
- GPIO_FN_SIUMCKA
- GPIO_FN_SIUMCKB
- GPIO_FN_SP0_MISO
- GPIO_FN_SP0_MOSI
- GPIO_FN_SP0_SCK
- GPIO_FN_SP0_SCK_FB
- GPIO_FN_SP0_SS0
- GPIO_FN_SP0_SS1
- GPIO_FN_SP0_SS2
- GPIO_FN_SP0_SS3
- GPIO_FN_SP1_MISO
- GPIO_FN_SP1_MOSI
- GPIO_FN_SP1_SCK
- GPIO_FN_SP1_SCK_FB
- GPIO_FN_SP1_SS0
- GPIO_FN_SP1_SS1
- GPIO_FN_SPDIF_IN
- GPIO_FN_SPDIF_OUT
- GPIO_FN_SSCK0_PD
- GPIO_FN_SSCK0_PF
- GPIO_FN_SSCK1_PD
- GPIO_FN_SSCK1_PF
- GPIO_FN_SSI0_CLK
- GPIO_FN_SSI0_PD
- GPIO_FN_SSI0_PF
- GPIO_FN_SSI0_SCK
- GPIO_FN_SSI0_SDATA
- GPIO_FN_SSI0_WS
- GPIO_FN_SSI1_CLK
- GPIO_FN_SSI1_PD
- GPIO_FN_SSI1_PF
- GPIO_FN_SSI1_SCK
- GPIO_FN_SSI1_SDATA
- GPIO_FN_SSI1_WS
- GPIO_FN_SSI2_SCK
- GPIO_FN_SSI2_SDATA
- GPIO_FN_SSI2_WS
- GPIO_FN_SSI3_SCK
- GPIO_FN_SSI3_SDATA
- GPIO_FN_SSI3_WS
- GPIO_FN_SSIDATA0
- GPIO_FN_SSIDATA1
- GPIO_FN_SSIDATA2
- GPIO_FN_SSIDATA3
- GPIO_FN_SSIRXD0
- GPIO_FN_SSISCK0
- GPIO_FN_SSISCK1
- GPIO_FN_SSISCK2
- GPIO_FN_SSISCK3
- GPIO_FN_SSITXD0
- GPIO_FN_SSIWS0
- GPIO_FN_SSIWS1
- GPIO_FN_SSIWS2
- GPIO_FN_SSIWS3
- GPIO_FN_SSI_SCK0_A
- GPIO_FN_SSI_SCK0_B
- GPIO_FN_SSI_SCK1_A
- GPIO_FN_SSI_SCK1_B
- GPIO_FN_SSI_SCK23
- GPIO_FN_SSI_SDATA0_A
- GPIO_FN_SSI_SDATA0_B
- GPIO_FN_SSI_SDATA1_A
- GPIO_FN_SSI_SDATA1_B
- GPIO_FN_SSI_SDATA2
- GPIO_FN_SSI_SDATA3
- GPIO_FN_SSI_WS0_A
- GPIO_FN_SSI_WS0_B
- GPIO_FN_SSI_WS1_A
- GPIO_FN_SSI_WS1_B
- GPIO_FN_SSI_WS23
- GPIO_FN_SSL00
- GPIO_FN_SSL00_PB18
- GPIO_FN_SSL00_PJ17
- GPIO_FN_SSL10
- GPIO_FN_SSO0_PD
- GPIO_FN_SSO0_PF
- GPIO_FN_SSO1_PD
- GPIO_FN_SSO1_PF
- GPIO_FN_ST0_CLKIN
- GPIO_FN_ST0_D0
- GPIO_FN_ST0_D1
- GPIO_FN_ST0_D2
- GPIO_FN_ST0_D3
- GPIO_FN_ST0_D4
- GPIO_FN_ST0_D5
- GPIO_FN_ST0_D6
- GPIO_FN_ST0_D7
- GPIO_FN_ST0_PWM
- GPIO_FN_ST0_REQ
- GPIO_FN_ST0_SYC
- GPIO_FN_ST0_VCO_CLKIN
- GPIO_FN_ST0_VLD
- GPIO_FN_ST1_CLKIN
- GPIO_FN_ST1_D0
- GPIO_FN_ST1_D1
- GPIO_FN_ST1_D2
- GPIO_FN_ST1_D3
- GPIO_FN_ST1_D4
- GPIO_FN_ST1_D5
- GPIO_FN_ST1_D6
- GPIO_FN_ST1_D7
- GPIO_FN_ST1_PWM
- GPIO_FN_ST1_REQ
- GPIO_FN_ST1_SYC
- GPIO_FN_ST1_VCO_CLKIN
- GPIO_FN_ST1_VLD
- GPIO_FN_STATUS0
- GPIO_FN_STATUS1
- GPIO_FN_STATUS2
- GPIO_FN_STOP_CDE
- GPIO_FN_ST_CLKOUT
- GPIO_FN_SUB_CLKIN
- GPIO_FN_TCK
- GPIO_FN_TCLK
- GPIO_FN_TCLK0
- GPIO_FN_TCLK1_A
- GPIO_FN_TCLK1_B
- GPIO_FN_TCLKA
- GPIO_FN_TCLKA_A
- GPIO_FN_TCLKA_C
- GPIO_FN_TCLKA_PD
- GPIO_FN_TCLKA_PF
- GPIO_FN_TCLKB
- GPIO_FN_TCLKB_A
- GPIO_FN_TCLKB_C
- GPIO_FN_TCLKB_PD
- GPIO_FN_TCLKB_PF
- GPIO_FN_TCLKC
- GPIO_FN_TCLKC_A
- GPIO_FN_TCLKC_C
- GPIO_FN_TCLKC_PD
- GPIO_FN_TCLKC_PF
- GPIO_FN_TCLKD
- GPIO_FN_TCLKD_A
- GPIO_FN_TCLKD_C
- GPIO_FN_TCLKD_PD
- GPIO_FN_TCLKD_PF
- GPIO_FN_TDI
- GPIO_FN_TDO
- GPIO_FN_TEND0
- GPIO_FN_TEND0_PD
- GPIO_FN_TEND0_PE
- GPIO_FN_TEND1
- GPIO_FN_TEND1_PD
- GPIO_FN_TEND1_PE
- GPIO_FN_TIOC0A
- GPIO_FN_TIOC0A_A
- GPIO_FN_TIOC0A_C
- GPIO_FN_TIOC0B
- GPIO_FN_TIOC0B_A
- GPIO_FN_TIOC0B_C
- GPIO_FN_TIOC0C
- GPIO_FN_TIOC0C_A
- GPIO_FN_TIOC0C_C
- GPIO_FN_TIOC0D
- GPIO_FN_TIOC0D_A
- GPIO_FN_TIOC0D_C
- GPIO_FN_TIOC1A
- GPIO_FN_TIOC1A_A
- GPIO_FN_TIOC1A_B
- GPIO_FN_TIOC1A_C
- GPIO_FN_TIOC1B
- GPIO_FN_TIOC1B_A
- GPIO_FN_TIOC1B_B
- GPIO_FN_TIOC1B_C
- GPIO_FN_TIOC2A
- GPIO_FN_TIOC2A_A
- GPIO_FN_TIOC2A_B
- GPIO_FN_TIOC2A_C
- GPIO_FN_TIOC2B
- GPIO_FN_TIOC2B_A
- GPIO_FN_TIOC2B_B
- GPIO_FN_TIOC2B_C
- GPIO_FN_TIOC3A
- GPIO_FN_TIOC3A_A
- GPIO_FN_TIOC3A_C
- GPIO_FN_TIOC3B
- GPIO_FN_TIOC3B_A
- GPIO_FN_TIOC3B_C
- GPIO_FN_TIOC3C
- GPIO_FN_TIOC3C_A
- GPIO_FN_TIOC3C_C
- GPIO_FN_TIOC3D
- GPIO_FN_TIOC3D_A
- GPIO_FN_TIOC3D_C
- GPIO_FN_TIOC4A
- GPIO_FN_TIOC4A_A
- GPIO_FN_TIOC4A_C
- GPIO_FN_TIOC4B
- GPIO_FN_TIOC4B_A
- GPIO_FN_TIOC4B_C
- GPIO_FN_TIOC4C
- GPIO_FN_TIOC4C_A
- GPIO_FN_TIOC4C_C
- GPIO_FN_TIOC4D
- GPIO_FN_TIOC4D_A
- GPIO_FN_TIOC4D_C
- GPIO_FN_TMS
- GPIO_FN_TPUTI2
- GPIO_FN_TPUTI3
- GPIO_FN_TPUTO
- GPIO_FN_TPUTO0
- GPIO_FN_TPUTO1
- GPIO_FN_TPUTO2
- GPIO_FN_TPUTO3
- GPIO_FN_TPU_TI2A
- GPIO_FN_TPU_TI2B
- GPIO_FN_TPU_TI3A
- GPIO_FN_TPU_TI3B
- GPIO_FN_TPU_TO0
- GPIO_FN_TPU_TO1
- GPIO_FN_TPU_TO2
- GPIO_FN_TPU_TO3
- GPIO_FN_TRDY_DISPL
- GPIO_FN_TRST
- GPIO_FN_TS0_SCK
- GPIO_FN_TS0_SDAT
- GPIO_FN_TS0_SDEN
- GPIO_FN_TS0_SPSYNC
- GPIO_FN_TSIF_TS0_SCK
- GPIO_FN_TSIF_TS0_SDAT
- GPIO_FN_TSIF_TS0_SDEN
- GPIO_FN_TSIF_TS0_SPSYNC
- GPIO_FN_TS_SCK
- GPIO_FN_TS_SDAT
- GPIO_FN_TS_SDEN
- GPIO_FN_TS_SPSYNC
- GPIO_FN_TX0_A
- GPIO_FN_TX0_B
- GPIO_FN_TX1_A
- GPIO_FN_TX1_B
- GPIO_FN_TX1_C
- GPIO_FN_TX1_D
- GPIO_FN_TX1_E
- GPIO_FN_TX2_A
- GPIO_FN_TX2_B
- GPIO_FN_TX2_C
- GPIO_FN_TX2_D
- GPIO_FN_TX3_A
- GPIO_FN_TX3_B
- GPIO_FN_TX3_C
- GPIO_FN_TX3_D
- GPIO_FN_TX3_E
- GPIO_FN_TX4_A
- GPIO_FN_TX4_B
- GPIO_FN_TX4_C
- GPIO_FN_TX4_D
- GPIO_FN_TX5_A
- GPIO_FN_TX5_B
- GPIO_FN_TX5_C
- GPIO_FN_TX5_D
- GPIO_FN_TXD0
- GPIO_FN_TXD1
- GPIO_FN_TXD2
- GPIO_FN_TXD3
- GPIO_FN_TXD4
- GPIO_FN_TXD5
- GPIO_FN_TXD6
- GPIO_FN_TXD7
- GPIO_FN_UBCTRG
- GPIO_FN_USB1D_DMNS
- GPIO_FN_USB1D_DPLS
- GPIO_FN_USB1D_RCV
- GPIO_FN_USB1D_SPEED
- GPIO_FN_USB1D_SUSPEND
- GPIO_FN_USB1D_TXDPLS
- GPIO_FN_USB1D_TXENL
- GPIO_FN_USB1D_TXSE0
- GPIO_FN_USB1_PWR_EN_USBF_UPLUP
- GPIO_FN_USB2_PWR_EN
- GPIO_FN_USB_OVC0
- GPIO_FN_USB_OVC1
- GPIO_FN_USB_PENC0
- GPIO_FN_USB_PENC1
- GPIO_FN_VBIOS_CLK
- GPIO_FN_VBIOS_CS
- GPIO_FN_VBIOS_DI
- GPIO_FN_VBIOS_DO
- GPIO_FN_VBUS_EN
- GPIO_FN_VBUS_OC
- GPIO_FN_VI0_CLK
- GPIO_FN_VI0_CLKENB
- GPIO_FN_VI0_DATA0_VI0_B0
- GPIO_FN_VI0_DATA1_VI0_B1
- GPIO_FN_VI0_DATA2_VI0_B2
- GPIO_FN_VI0_DATA3_VI0_B3
- GPIO_FN_VI0_DATA4_VI0_B4
- GPIO_FN_VI0_DATA5_VI0_B5
- GPIO_FN_VI0_DATA6_VI0_G0
- GPIO_FN_VI0_DATA7_VI0_G1
- GPIO_FN_VI0_FIELD
- GPIO_FN_VI0_G2
- GPIO_FN_VI0_G3
- GPIO_FN_VI0_G4
- GPIO_FN_VI0_G5
- GPIO_FN_VI0_HSYNC
- GPIO_FN_VI0_R0
- GPIO_FN_VI0_R1
- GPIO_FN_VI0_R2
- GPIO_FN_VI0_R3
- GPIO_FN_VI0_R4
- GPIO_FN_VI0_R5
- GPIO_FN_VI0_VSYNC
- GPIO_FN_VI1_0_A
- GPIO_FN_VI1_0_B
- GPIO_FN_VI1_1_A
- GPIO_FN_VI1_1_B
- GPIO_FN_VI1_2_A
- GPIO_FN_VI1_2_B
- GPIO_FN_VI1_3_A
- GPIO_FN_VI1_3_B
- GPIO_FN_VI1_4_A
- GPIO_FN_VI1_4_B
- GPIO_FN_VI1_5_A
- GPIO_FN_VI1_5_B
- GPIO_FN_VI1_6_A
- GPIO_FN_VI1_6_B
- GPIO_FN_VI1_7_A
- GPIO_FN_VI1_7_B
- GPIO_FN_VI1_CLK_A
- GPIO_FN_VI1_CLK_B
- GPIO_FN_VIO0_CLK
- GPIO_FN_VIO0_D0
- GPIO_FN_VIO0_D1
- GPIO_FN_VIO0_D10
- GPIO_FN_VIO0_D11
- GPIO_FN_VIO0_D12
- GPIO_FN_VIO0_D13
- GPIO_FN_VIO0_D14
- GPIO_FN_VIO0_D15
- GPIO_FN_VIO0_D2
- GPIO_FN_VIO0_D3
- GPIO_FN_VIO0_D4
- GPIO_FN_VIO0_D5
- GPIO_FN_VIO0_D6
- GPIO_FN_VIO0_D7
- GPIO_FN_VIO0_D8
- GPIO_FN_VIO0_D9
- GPIO_FN_VIO0_FLD
- GPIO_FN_VIO0_HD
- GPIO_FN_VIO0_VD
- GPIO_FN_VIO1_CLK
- GPIO_FN_VIO1_D0
- GPIO_FN_VIO1_D1
- GPIO_FN_VIO1_D2
- GPIO_FN_VIO1_D3
- GPIO_FN_VIO1_D4
- GPIO_FN_VIO1_D5
- GPIO_FN_VIO1_D6
- GPIO_FN_VIO1_D7
- GPIO_FN_VIO1_FLD
- GPIO_FN_VIO1_HD
- GPIO_FN_VIO1_VD
- GPIO_FN_VIO_CKO
- GPIO_FN_VIO_CLK
- GPIO_FN_VIO_CLK1
- GPIO_FN_VIO_CLK2
- GPIO_FN_VIO_D0
- GPIO_FN_VIO_D1
- GPIO_FN_VIO_D10
- GPIO_FN_VIO_D11
- GPIO_FN_VIO_D12
- GPIO_FN_VIO_D13
- GPIO_FN_VIO_D14
- GPIO_FN_VIO_D15
- GPIO_FN_VIO_D2
- GPIO_FN_VIO_D3
- GPIO_FN_VIO_D4
- GPIO_FN_VIO_D5
- GPIO_FN_VIO_D6
- GPIO_FN_VIO_D7
- GPIO_FN_VIO_D8
- GPIO_FN_VIO_D9
- GPIO_FN_VIO_FLD
- GPIO_FN_VIO_HD
- GPIO_FN_VIO_HD1
- GPIO_FN_VIO_HD2
- GPIO_FN_VIO_STEM
- GPIO_FN_VIO_STEX
- GPIO_FN_VIO_VD
- GPIO_FN_VIO_VD1
- GPIO_FN_VIO_VD2
- GPIO_FN_VSYNC
- GPIO_FN_WAIT
- GPIO_FN_WDTOVF
- GPIO_FN_WE0
- GPIO_FN_WE0DQML
- GPIO_FN_WE0_DQMLL
- GPIO_FN_WE1
- GPIO_FN_WE1DQMUWE
- GPIO_FN_WE1_DQMLU_WE
- GPIO_FN_WE2
- GPIO_FN_WE2ICIORDDQMUL
- GPIO_FN_WE2_DQMUL_ICIORD
- GPIO_FN_WE2_ICIORD
- GPIO_FN_WE3
- GPIO_FN_WE3ICIOWRAHDQMUU
- GPIO_FN_WE3_DQMUU_AH_ICIO_WR
- GPIO_FN_WE3_ICIOWR
- GPIO_FN_WE4_CBE0
- GPIO_FN_WE5_CBE1
- GPIO_FN_WE6_CBE2
- GPIO_FN_WE7_CBE3
- GPIO_FN_WP
- GPIO_FPGA_CCLK
- GPIO_FPGA_DIN
- GPIO_FPGA_DONE
- GPIO_FPGA_DOUT
- GPIO_FPGA_INIT
- GPIO_FPGA_PGM
- GPIO_FREQ_32KHZ
- GPIO_FREQ_44KHZ
- GPIO_FREQ_48KHZ
- GPIO_FREQ_MASK
- GPIO_FUSE_BANK_REG
- GPIO_GDIR
- GPIO_GEDR
- GPIO_GENERIC_A
- GPIO_GENERIC_B
- GPIO_GENERIC_C
- GPIO_GENERIC_COUNT
- GPIO_GENERIC_D
- GPIO_GENERIC_E
- GPIO_GENERIC_F
- GPIO_GENERIC_G
- GPIO_GENERIC_MAX
- GPIO_GENERIC_MIN
- GPIO_GENERIC_UNKNOWN
- GPIO_GET_CHIPINFO_IOCTL
- GPIO_GET_LINEEVENT_IOCTL
- GPIO_GET_LINEHANDLE_IOCTL
- GPIO_GET_LINEINFO_IOCTL
- GPIO_GFER
- GPIO_GPCR
- GPIO_GPCTR0_DBR_MASK
- GPIO_GPCTR0_DBR_SHIFT
- GPIO_GPCTR0_DB_ENABLE_MASK
- GPIO_GPCTR0_IOTR_CMD_0UTPUT
- GPIO_GPCTR0_IOTR_CMD_INPUT
- GPIO_GPCTR0_IOTR_MASK
- GPIO_GPCTR0_ITR_CMD_BOTH_EDGE
- GPIO_GPCTR0_ITR_CMD_FALLING_EDGE
- GPIO_GPCTR0_ITR_CMD_RISING_EDGE
- GPIO_GPCTR0_ITR_MASK
- GPIO_GPCTR0_ITR_SHIFT
- GPIO_GPDR
- GPIO_GPIO
- GPIO_GPIO0
- GPIO_GPIO1
- GPIO_GPIO10
- GPIO_GPIO11
- GPIO_GPIO12
- GPIO_GPIO13
- GPIO_GPIO14
- GPIO_GPIO15
- GPIO_GPIO16
- GPIO_GPIO17
- GPIO_GPIO18
- GPIO_GPIO19
- GPIO_GPIO2
- GPIO_GPIO20
- GPIO_GPIO21
- GPIO_GPIO22
- GPIO_GPIO23
- GPIO_GPIO24
- GPIO_GPIO25
- GPIO_GPIO26
- GPIO_GPIO27
- GPIO_GPIO3
- GPIO_GPIO4
- GPIO_GPIO5
- GPIO_GPIO6
- GPIO_GPIO7
- GPIO_GPIO8
- GPIO_GPIO9
- GPIO_GPIO_0_0UTPUT_CTL_OFFSET
- GPIO_GPIO_PAD_0
- GPIO_GPIO_PAD_1
- GPIO_GPIO_PAD_10
- GPIO_GPIO_PAD_11
- GPIO_GPIO_PAD_12
- GPIO_GPIO_PAD_13
- GPIO_GPIO_PAD_14
- GPIO_GPIO_PAD_15
- GPIO_GPIO_PAD_16
- GPIO_GPIO_PAD_17
- GPIO_GPIO_PAD_18
- GPIO_GPIO_PAD_19
- GPIO_GPIO_PAD_2
- GPIO_GPIO_PAD_20
- GPIO_GPIO_PAD_21
- GPIO_GPIO_PAD_22
- GPIO_GPIO_PAD_23
- GPIO_GPIO_PAD_24
- GPIO_GPIO_PAD_25
- GPIO_GPIO_PAD_26
- GPIO_GPIO_PAD_27
- GPIO_GPIO_PAD_28
- GPIO_GPIO_PAD_29
- GPIO_GPIO_PAD_3
- GPIO_GPIO_PAD_30
- GPIO_GPIO_PAD_4
- GPIO_GPIO_PAD_5
- GPIO_GPIO_PAD_6
- GPIO_GPIO_PAD_7
- GPIO_GPIO_PAD_8
- GPIO_GPIO_PAD_9
- GPIO_GPIO_PAD_COUNT
- GPIO_GPIO_PAD_MAX
- GPIO_GPIO_PAD_MIN
- GPIO_GPIO_PAD_UNKNOWN
- GPIO_GPIR
- GPIO_GPLR
- GPIO_GPPWR_OFFSET
- GPIO_GPSR
- GPIO_GPS_CTL_HWPDN
- GPIO_GP_0_0
- GPIO_GP_0_1
- GPIO_GP_0_10
- GPIO_GP_0_11
- GPIO_GP_0_12
- GPIO_GP_0_13
- GPIO_GP_0_14
- GPIO_GP_0_15
- GPIO_GP_0_16
- GPIO_GP_0_17
- GPIO_GP_0_18
- GPIO_GP_0_19
- GPIO_GP_0_2
- GPIO_GP_0_20
- GPIO_GP_0_21
- GPIO_GP_0_22
- GPIO_GP_0_23
- GPIO_GP_0_24
- GPIO_GP_0_25
- GPIO_GP_0_26
- GPIO_GP_0_27
- GPIO_GP_0_28
- GPIO_GP_0_29
- GPIO_GP_0_3
- GPIO_GP_0_30
- GPIO_GP_0_31
- GPIO_GP_0_4
- GPIO_GP_0_5
- GPIO_GP_0_6
- GPIO_GP_0_7
- GPIO_GP_0_8
- GPIO_GP_0_9
- GPIO_GP_1_0
- GPIO_GP_1_1
- GPIO_GP_1_10
- GPIO_GP_1_11
- GPIO_GP_1_12
- GPIO_GP_1_13
- GPIO_GP_1_14
- GPIO_GP_1_15
- GPIO_GP_1_16
- GPIO_GP_1_17
- GPIO_GP_1_18
- GPIO_GP_1_19
- GPIO_GP_1_2
- GPIO_GP_1_20
- GPIO_GP_1_21
- GPIO_GP_1_22
- GPIO_GP_1_23
- GPIO_GP_1_24
- GPIO_GP_1_25
- GPIO_GP_1_26
- GPIO_GP_1_27
- GPIO_GP_1_28
- GPIO_GP_1_29
- GPIO_GP_1_3
- GPIO_GP_1_30
- GPIO_GP_1_31
- GPIO_GP_1_4
- GPIO_GP_1_5
- GPIO_GP_1_6
- GPIO_GP_1_7
- GPIO_GP_1_8
- GPIO_GP_1_9
- GPIO_GP_2_0
- GPIO_GP_2_1
- GPIO_GP_2_10
- GPIO_GP_2_11
- GPIO_GP_2_12
- GPIO_GP_2_13
- GPIO_GP_2_14
- GPIO_GP_2_15
- GPIO_GP_2_16
- GPIO_GP_2_17
- GPIO_GP_2_18
- GPIO_GP_2_19
- GPIO_GP_2_2
- GPIO_GP_2_20
- GPIO_GP_2_21
- GPIO_GP_2_22
- GPIO_GP_2_23
- GPIO_GP_2_24
- GPIO_GP_2_25
- GPIO_GP_2_26
- GPIO_GP_2_27
- GPIO_GP_2_28
- GPIO_GP_2_29
- GPIO_GP_2_3
- GPIO_GP_2_30
- GPIO_GP_2_31
- GPIO_GP_2_4
- GPIO_GP_2_5
- GPIO_GP_2_6
- GPIO_GP_2_7
- GPIO_GP_2_8
- GPIO_GP_2_9
- GPIO_GP_3_0
- GPIO_GP_3_1
- GPIO_GP_3_10
- GPIO_GP_3_11
- GPIO_GP_3_12
- GPIO_GP_3_13
- GPIO_GP_3_14
- GPIO_GP_3_15
- GPIO_GP_3_16
- GPIO_GP_3_17
- GPIO_GP_3_18
- GPIO_GP_3_19
- GPIO_GP_3_2
- GPIO_GP_3_20
- GPIO_GP_3_21
- GPIO_GP_3_22
- GPIO_GP_3_23
- GPIO_GP_3_24
- GPIO_GP_3_25
- GPIO_GP_3_26
- GPIO_GP_3_27
- GPIO_GP_3_28
- GPIO_GP_3_29
- GPIO_GP_3_3
- GPIO_GP_3_30
- GPIO_GP_3_31
- GPIO_GP_3_4
- GPIO_GP_3_5
- GPIO_GP_3_6
- GPIO_GP_3_7
- GPIO_GP_3_8
- GPIO_GP_3_9
- GPIO_GP_4_0
- GPIO_GP_4_1
- GPIO_GP_4_10
- GPIO_GP_4_11
- GPIO_GP_4_12
- GPIO_GP_4_13
- GPIO_GP_4_14
- GPIO_GP_4_15
- GPIO_GP_4_16
- GPIO_GP_4_17
- GPIO_GP_4_18
- GPIO_GP_4_19
- GPIO_GP_4_2
- GPIO_GP_4_20
- GPIO_GP_4_21
- GPIO_GP_4_22
- GPIO_GP_4_23
- GPIO_GP_4_24
- GPIO_GP_4_25
- GPIO_GP_4_26
- GPIO_GP_4_27
- GPIO_GP_4_28
- GPIO_GP_4_29
- GPIO_GP_4_3
- GPIO_GP_4_30
- GPIO_GP_4_31
- GPIO_GP_4_4
- GPIO_GP_4_5
- GPIO_GP_4_6
- GPIO_GP_4_7
- GPIO_GP_4_8
- GPIO_GP_4_9
- GPIO_GP_5_0
- GPIO_GP_5_1
- GPIO_GP_5_10
- GPIO_GP_5_11
- GPIO_GP_5_2
- GPIO_GP_5_3
- GPIO_GP_5_4
- GPIO_GP_5_5
- GPIO_GP_5_6
- GPIO_GP_5_7
- GPIO_GP_5_8
- GPIO_GP_5_9
- GPIO_GREEN_LED
- GPIO_GRER
- GPIO_GROUP
- GPIO_GROUP_NUM
- GPIO_GSL_COUNT
- GPIO_GSL_GENLOCK_CLOCK
- GPIO_GSL_GENLOCK_VSYNC
- GPIO_GSL_MAX
- GPIO_GSL_MIN
- GPIO_GSL_MUX_CONFIG_TYPE_DISABLE
- GPIO_GSL_MUX_CONFIG_TYPE_FLIP_SYNC
- GPIO_GSL_MUX_CONFIG_TYPE_TIMING_SYNC
- GPIO_GSL_SWAPLOCK_A
- GPIO_GSL_SWAPLOCK_B
- GPIO_GSL_UNKNOWN
- GPIO_GUMSTIX_BTRESET
- GPIO_GUMSTIX_BTRESET_MD
- GPIO_GUMSTIX_ETH0
- GPIO_GUMSTIX_ETH0_MD
- GPIO_GUMSTIX_ETH0_RST
- GPIO_GUMSTIX_ETH0_RST_MD
- GPIO_GUMSTIX_ETH1
- GPIO_GUMSTIX_ETH1_MD
- GPIO_GUMSTIX_ETH1_RST
- GPIO_GUMSTIX_ETH1_RST_MD
- GPIO_GUMSTIX_USB_GPIOn
- GPIO_GUMSTIX_USB_GPIOn_MD
- GPIO_GUMSTIX_USB_GPIOx
- GPIO_GUMSTIX_USB_GPIOx_CON_MD
- GPIO_GUMSTIX_USB_GPIOx_DIS_MD
- GPIO_HAS_INTERRUPT_EDGE_SELECT
- GPIO_HAS_OUTPUT_ENABLE
- GPIO_HAS_PULLUPDOWN_IO
- GPIO_HCI_SEL
- GPIO_HDAV_MAGIC
- GPIO_HDAV_OUTPUT_ENABLE
- GPIO_HEARTBEAT_LED
- GPIO_HI
- GPIO_HIGH
- GPIO_HI_INT_MSK
- GPIO_HI_INT_MSTAT
- GPIO_HI_INT_STAT
- GPIO_HI_ISM_POL
- GPIO_HI_ISM_SNS
- GPIO_HI_OE
- GPIO_HI_PRIORITY
- GPIO_HOG
- GPIO_HOLDB
- GPIO_HPD_1
- GPIO_HPD_2
- GPIO_HPD_3
- GPIO_HPD_4
- GPIO_HPD_5
- GPIO_HPD_6
- GPIO_HPD_COUNT
- GPIO_HPD_MAX
- GPIO_HPD_MIN
- GPIO_HPD_UNKNOWN
- GPIO_HP_DETECT
- GPIO_HP_JACK
- GPIO_HP_REAR
- GPIO_HSS0_CTS_N
- GPIO_HSS0_DCD_N
- GPIO_HSS0_RTS_N
- GPIO_HSS1_CTS_N
- GPIO_HSS1_DCD_N
- GPIO_HSS1_RTS_N
- GPIO_HV_STATUS
- GPIO_IBE
- GPIO_ICR
- GPIO_ICR1
- GPIO_ICR2
- GPIO_ID_COUNT
- GPIO_ID_DDC_CLOCK
- GPIO_ID_DDC_DATA
- GPIO_ID_GENERIC
- GPIO_ID_GPIO_PAD
- GPIO_ID_GSL
- GPIO_ID_HPD
- GPIO_ID_MAX
- GPIO_ID_MIN
- GPIO_ID_SYNC
- GPIO_ID_UNKNOWN
- GPIO_ID_VIP_PAD
- GPIO_IER
- GPIO_IMR
- GPIO_IN
- GPIO_INPUT
- GPIO_INPUT_AUX1
- GPIO_INPUT_ENABLE
- GPIO_INPUT_EVENT_COUNT
- GPIO_INPUT_FILTER
- GPIO_INPUT_INVERSION_REG
- GPIO_INPUT_INVERT
- GPIO_INPUT_OK
- GPIO_INPUT_POLARITY
- GPIO_INPUT_ROUTE
- GPIO_INT
- GPIO_INTCTRL
- GPIO_INTEN
- GPIO_INTERNAL_CLOCK
- GPIO_INTERRUPT
- GPIO_INTERRUPT_EDGE
- GPIO_INTERRUPT_EDGE_DUAL
- GPIO_INTERRUPT_EDGE_SINGLE
- GPIO_INTERRUPT_EN
- GPIO_INTERRUPT_ENABLE
- GPIO_INTERRUPT_SETUP
- GPIO_INTERRUPT_SETUP_ACTIVE_25
- GPIO_INTERRUPT_SETUP_ACTIVE_26
- GPIO_INTERRUPT_SETUP_ACTIVE_27
- GPIO_INTERRUPT_SETUP_ACTIVE_28
- GPIO_INTERRUPT_SETUP_ACTIVE_29
- GPIO_INTERRUPT_SETUP_ACTIVE_30
- GPIO_INTERRUPT_SETUP_ACTIVE_31
- GPIO_INTERRUPT_SETUP_ENABLE_25
- GPIO_INTERRUPT_SETUP_ENABLE_26
- GPIO_INTERRUPT_SETUP_ENABLE_27
- GPIO_INTERRUPT_SETUP_ENABLE_28
- GPIO_INTERRUPT_SETUP_ENABLE_29
- GPIO_INTERRUPT_SETUP_ENABLE_30
- GPIO_INTERRUPT_SETUP_ENABLE_31
- GPIO_INTERRUPT_SETUP_TRIGGER_25
- GPIO_INTERRUPT_SETUP_TRIGGER_26
- GPIO_INTERRUPT_SETUP_TRIGGER_27
- GPIO_INTERRUPT_SETUP_TRIGGER_28
- GPIO_INTERRUPT_SETUP_TRIGGER_29
- GPIO_INTERRUPT_SETUP_TRIGGER_30
- GPIO_INTERRUPT_SETUP_TRIGGER_31
- GPIO_INTERRUPT_STATUS
- GPIO_INTERRUPT_STATUS_25
- GPIO_INTERRUPT_STATUS_26
- GPIO_INTERRUPT_STATUS_27
- GPIO_INTERRUPT_STATUS_28
- GPIO_INTERRUPT_STATUS_29
- GPIO_INTERRUPT_STATUS_30
- GPIO_INTERRUPT_STATUS_31
- GPIO_INTERRUPT_TYPE
- GPIO_INTERRUPT_TYPE_EDGE
- GPIO_INTERRUPT_TYPE_LEVEL
- GPIO_INTMASK
- GPIO_INTMASK_V2
- GPIO_INTM_EDGE_TRIG_IRQ
- GPIO_INTR
- GPIO_INTR_ENA_W1C
- GPIO_INTR_ENA_W1S
- GPIO_INTR_INTR
- GPIO_INTR_INTR_W1S
- GPIO_INTR_OFFSET
- GPIO_INTSTATUS
- GPIO_INTSTATUS_V2
- GPIO_INTTYPE_LEVEL
- GPIO_INTTYPE_LEVEL_V2
- GPIO_INT_BOTH_EDGE
- GPIO_INT_BOTH_EDGES
- GPIO_INT_CLR
- GPIO_INT_CONNECTED_MASK
- GPIO_INT_EDGE_BOTH
- GPIO_INT_EDGE_FALLING
- GPIO_INT_EDGE_RISING
- GPIO_INT_EN
- GPIO_INT_EN00
- GPIO_INT_EN1
- GPIO_INT_EN10
- GPIO_INT_EN2
- GPIO_INT_EN20
- GPIO_INT_EN3
- GPIO_INT_EN30
- GPIO_INT_ENB
- GPIO_INT_EN_REG
- GPIO_INT_FALL_EDGE
- GPIO_INT_HIGH_LEV
- GPIO_INT_LEVEL
- GPIO_INT_LEVEL_H
- GPIO_INT_LEVEL_HIGH
- GPIO_INT_LEVEL_L
- GPIO_INT_LEVEL_LOW
- GPIO_INT_LEV_MASK
- GPIO_INT_LOW_LEV
- GPIO_INT_LVL
- GPIO_INT_LVL1
- GPIO_INT_LVL2
- GPIO_INT_LVL3
- GPIO_INT_LVL_EDGE_BOTH
- GPIO_INT_LVL_EDGE_FALLING
- GPIO_INT_LVL_EDGE_RISING
- GPIO_INT_LVL_LEVEL_HIGH
- GPIO_INT_LVL_LEVEL_LOW
- GPIO_INT_LVL_MASK
- GPIO_INT_MASK
- GPIO_INT_MASK_LINK_DOWN
- GPIO_INT_MASK_LINK_UP
- GPIO_INT_MSKCLR
- GPIO_INT_MSK_REG
- GPIO_INT_NONE
- GPIO_INT_POL
- GPIO_INT_POLARITY
- GPIO_INT_POLARITY_ACTIVE_HIGH
- GPIO_INT_POLARITY_ACTIVE_LOW
- GPIO_INT_POLARITY_V2
- GPIO_INT_POL_MASK
- GPIO_INT_RAWSTATUS
- GPIO_INT_REG_DP_ERR_INT
- GPIO_INT_REG_LINK_DOWN
- GPIO_INT_REG_LINK_UP
- GPIO_INT_RISE_EDGE
- GPIO_INT_SRC_CFG
- GPIO_INT_STA
- GPIO_INT_STAT
- GPIO_INT_STAT1
- GPIO_INT_STAT2
- GPIO_INT_STAT3
- GPIO_INT_STATUS
- GPIO_INT_STAT_MASKED
- GPIO_INT_STAT_RAW
- GPIO_INT_STS_REG
- GPIO_INT_TYPE
- GPIO_IN_8811A
- GPIO_IN_CTRL_BASE
- GPIO_IN_POL
- GPIO_IN_POL_OFF
- GPIO_IN_REG
- GPIO_IN_SE
- GPIO_IN_STATE_MASK
- GPIO_IN_STATUS
- GPIO_IOCLK
- GPIO_IOLOAD
- GPIO_IO_CONF
- GPIO_IO_CONF_OFF
- GPIO_IO_DATA_RD_REG
- GPIO_IO_DATA_WR_REG
- GPIO_IO_DIR_REG
- GPIO_IO_SEL
- GPIO_IO_SEL_2_GPIO09_INPUT
- GPIO_IO_SEL_2_GPIO09_IRQ
- GPIO_IO_SEL_8811A
- GPIO_IO_SIZE
- GPIO_IO_SIZE_CENTERTON
- GPIO_IRQ
- GPIO_IRQ0_MASK
- GPIO_IRQ1_MASK
- GPIO_IRQF_TRIGGER_BOTH
- GPIO_IRQF_TRIGGER_FALLING
- GPIO_IRQF_TRIGGER_RISING
- GPIO_IRQ_CLUSTER
- GPIO_IRQ_ENABLE
- GPIO_IRQ_ETHA
- GPIO_IRQ_ETHB
- GPIO_IRQ_MPCI
- GPIO_IRQ_NEC
- GPIO_IRQ_QUARK_X1000
- GPIO_IRQ_STATUS
- GPIO_IRQ_TYPE0
- GPIO_IRQ_TYPE1
- GPIO_IRQ_TYPE2
- GPIO_IR_DEVICE_NAME
- GPIO_ISM
- GPIO_ISR
- GPIO_LCDPWR
- GPIO_LCD_BASE
- GPIO_LCD_CS
- GPIO_LCD_DIN
- GPIO_LCD_DOUT
- GPIO_LCD_RESET
- GPIO_LCD_SCL
- GPIO_LDD
- GPIO_LDD10
- GPIO_LDD11
- GPIO_LDD12
- GPIO_LDD13
- GPIO_LDD14
- GPIO_LDD15
- GPIO_LDD8
- GPIO_LDD9
- GPIO_LED
- GPIO_LED_0_SHIFT
- GPIO_LED_1_SHIFT
- GPIO_LED_ALL_OFF
- GPIO_LED_BITMAP
- GPIO_LED_BLINK
- GPIO_LED_GREEN_OFF_AMBER_OFF
- GPIO_LED_GREEN_OFF_AMBER_ON
- GPIO_LED_GREEN_ON_AMBER_OFF
- GPIO_LED_GREEN_ON_AMBER_ON
- GPIO_LED_MASK
- GPIO_LED_NO_BLINK_HIGH
- GPIO_LED_NO_BLINK_LOW
- GPIO_LED_OUTPUT_CODE_HARD_RESET
- GPIO_LED_OUTPUT_CODE_MAIN
- GPIO_LED_OUTPUT_CODE_RESET
- GPIO_LED_OUTPUT_CODE_SOFT_RESET
- GPIO_LED_RED_ON_OTHER_OFF
- GPIO_LED_RGA_ON
- GPIO_LEVEL_MASK
- GPIO_LEVEL_MASK_ARMADAXP_OFF
- GPIO_LEVEL_MASK_MV78200_OFF
- GPIO_LEVEL_MASK_OFF
- GPIO_LINEIN_DET_INDEX
- GPIO_LINEOUT_DET_INDEX
- GPIO_LINEOUT_MUTE_INDEX
- GPIO_LINE_OPEN_DRAIN
- GPIO_LINE_OPEN_SOURCE
- GPIO_LLI_BIT
- GPIO_LO
- GPIO_LOCK_ENABLE
- GPIO_LOOKUP
- GPIO_LOOKUP_FLAGS_DEFAULT
- GPIO_LOOKUP_IDX
- GPIO_LOS
- GPIO_LOW
- GPIO_LO_INT_MSK
- GPIO_LO_INT_MSTAT
- GPIO_LO_INT_STAT
- GPIO_LO_ISM_POL
- GPIO_LO_ISM_SNS
- GPIO_LO_OE
- GPIO_LS_SYNC
- GPIO_LVL
- GPIO_M
- GPIO_MAGIC
- GPIO_MAPPED_IRQ_BASE
- GPIO_MAPPED_IRQ_GROUP
- GPIO_MAP_W
- GPIO_MAP_X
- GPIO_MAP_Y
- GPIO_MAP_Z
- GPIO_MASK
- GPIO_MASK2
- GPIO_MASK_0
- GPIO_MASK_1
- GPIO_MAX
- GPIO_MAX_BANK_NUM
- GPIO_MBGNT
- GPIO_MBREQ
- GPIO_MC9S08DZ60_GPS_ENABLE
- GPIO_MC9S08DZ60_HDD_ENABLE
- GPIO_MC9S08DZ60_LCD_ENABLE
- GPIO_MC9S08DZ60_SPEAKER_ENABLE
- GPIO_MC9S08DZ60_WIFI_ENABLE
- GPIO_MCP_CLK
- GPIO_MCR
- GPIO_MERIDIAN_DIG_BOARD
- GPIO_MERIDIAN_DIG_EXT
- GPIO_MERIDIAN_DIG_MASK
- GPIO_MIC_RELAY
- GPIO_MIN
- GPIO_MMC_DET
- GPIO_MOCKUP_DIR_IN
- GPIO_MOCKUP_DIR_OUT
- GPIO_MOCKUP_MAX_GC
- GPIO_MOCKUP_MAX_PROP
- GPIO_MOCKUP_MAX_RANGES
- GPIO_MOCKUP_NAME
- GPIO_MOD
- GPIO_MODDEF0
- GPIO_MODE_6348_G0_DIAG
- GPIO_MODE_6348_G0_EXT_MII
- GPIO_MODE_6348_G1_DIAG
- GPIO_MODE_6348_G1_EXT_EPHY
- GPIO_MODE_6348_G1_MII_PCCARD
- GPIO_MODE_6348_G1_MII_SNOOP
- GPIO_MODE_6348_G1_SPI_MASTER
- GPIO_MODE_6348_G1_SPI_UART
- GPIO_MODE_6348_G1_UTOPIA
- GPIO_MODE_6348_G2_DIAG
- GPIO_MODE_6348_G2_PCI
- GPIO_MODE_6348_G3_DIAG
- GPIO_MODE_6348_G3_EXT_MII
- GPIO_MODE_6348_G3_UTOPIA
- GPIO_MODE_6348_G4_DIAG
- GPIO_MODE_6348_G4_EXT_EPHY
- GPIO_MODE_6348_G4_LEGACY_LED
- GPIO_MODE_6348_G4_MII_SNOOP
- GPIO_MODE_6348_G4_UTOPIA
- GPIO_MODE_6358_EXTRACS
- GPIO_MODE_6358_EXTRA_SPI_SS
- GPIO_MODE_6358_SERIAL_LED
- GPIO_MODE_6358_UART1
- GPIO_MODE_6358_UTOPIA
- GPIO_MODE_6368_ANALOG_AFE_0
- GPIO_MODE_6368_ANALOG_AFE_1
- GPIO_MODE_6368_EBI_CS2
- GPIO_MODE_6368_EBI_CS3
- GPIO_MODE_6368_EPHY0_LED
- GPIO_MODE_6368_EPHY1_LED
- GPIO_MODE_6368_EPHY2_LED
- GPIO_MODE_6368_EPHY3_LED
- GPIO_MODE_6368_INET_LED
- GPIO_MODE_6368_NTR_PULSE
- GPIO_MODE_6368_PCI_GNT0
- GPIO_MODE_6368_PCI_GNT1
- GPIO_MODE_6368_PCI_INTB
- GPIO_MODE_6368_PCI_REQ0
- GPIO_MODE_6368_PCI_REQ1
- GPIO_MODE_6368_PCMCIA_CD1
- GPIO_MODE_6368_PCMCIA_CD2
- GPIO_MODE_6368_PCMCIA_VS1
- GPIO_MODE_6368_PCMCIA_VS2
- GPIO_MODE_6368_ROBOSW_LED0
- GPIO_MODE_6368_ROBOSW_LED1
- GPIO_MODE_6368_ROBOSW_LED_CLK
- GPIO_MODE_6368_ROBOSW_LED_DAT
- GPIO_MODE_6368_SERIAL_LED_CLK
- GPIO_MODE_6368_SERIAL_LED_DATA
- GPIO_MODE_6368_SPI_SSN2
- GPIO_MODE_6368_SPI_SSN3
- GPIO_MODE_6368_SPI_SSN4
- GPIO_MODE_6368_SPI_SSN5
- GPIO_MODE_6368_SYS_IRQ
- GPIO_MODE_6368_USBD_LED
- GPIO_MODE_BITS
- GPIO_MODE_FAST_OUTPUT
- GPIO_MODE_HARDWARE
- GPIO_MODE_INPUT
- GPIO_MODE_INTERRUPT
- GPIO_MODE_OUTPUT
- GPIO_MODE_PREFIX
- GPIO_MODE_REG
- GPIO_MODE_UNKNOWN
- GPIO_MOD_8811A
- GPIO_MOD_CTRL_BIT
- GPIO_MONID
- GPIO_MONTEREY_RESET
- GPIO_MSK
- GPIO_MSK_CNF
- GPIO_MSK_DBC_EN
- GPIO_MSK_INT_ENB
- GPIO_MSK_INT_LVL
- GPIO_MSK_INT_STA
- GPIO_MSK_OE
- GPIO_MSK_OUT
- GPIO_MULTI_1X
- GPIO_MULTI_2X
- GPIO_MULTI_4X
- GPIO_MULTI_HALF
- GPIO_MULTI_MASK
- GPIO_MUST_BE_0
- GPIO_MUTE_ALL
- GPIO_MUTE_CONTROL
- GPIO_MUTE_SUR
- GPIO_MUX
- GPIO_MUX_0
- GPIO_MUX_1
- GPIO_MUX_10
- GPIO_MUX_11
- GPIO_MUX_12
- GPIO_MUX_13
- GPIO_MUX_14
- GPIO_MUX_15
- GPIO_MUX_16
- GPIO_MUX_17
- GPIO_MUX_18
- GPIO_MUX_19
- GPIO_MUX_2
- GPIO_MUX_20
- GPIO_MUX_21
- GPIO_MUX_22
- GPIO_MUX_23
- GPIO_MUX_24
- GPIO_MUX_25
- GPIO_MUX_26
- GPIO_MUX_27
- GPIO_MUX_28
- GPIO_MUX_29
- GPIO_MUX_3
- GPIO_MUX_30
- GPIO_MUX_31
- GPIO_MUX_4
- GPIO_MUX_5
- GPIO_MUX_6
- GPIO_MUX_7
- GPIO_MUX_8
- GPIO_MUX_9
- GPIO_NAND_ALE
- GPIO_NAND_CLE
- GPIO_NAND_CS
- GPIO_NAND_RB
- GPIO_NEGATIVE_EDGE_EN
- GPIO_NEGATIVE_EDGE_STS
- GPIO_NONMASKABLE_INT
- GPIO_NR_CENTRO_BT_EN
- GPIO_NR_CENTRO_KEYB_BL
- GPIO_NR_CENTRO_SD_POWER
- GPIO_NR_CENTRO_VIBRATE_EN
- GPIO_NR_PALMLD_BL_POWER
- GPIO_NR_PALMLD_BORDER_SELECT
- GPIO_NR_PALMLD_BORDER_SWITCH
- GPIO_NR_PALMLD_BT_POWER
- GPIO_NR_PALMLD_BT_RESET
- GPIO_NR_PALMLD_EARPHONE_DETECT
- GPIO_NR_PALMLD_GPIO_RESET
- GPIO_NR_PALMLD_HOTSYNC_BUTTON_N
- GPIO_NR_PALMLD_IDE_PWEN
- GPIO_NR_PALMLD_IDE_RESET
- GPIO_NR_PALMLD_IR_DISABLE
- GPIO_NR_PALMLD_LCD_POWER
- GPIO_NR_PALMLD_LED_AMBER
- GPIO_NR_PALMLD_LED_GREEN
- GPIO_NR_PALMLD_LOCK_SWITCH
- GPIO_NR_PALMLD_PCMCIA_POWER
- GPIO_NR_PALMLD_PCMCIA_READY
- GPIO_NR_PALMLD_PCMCIA_RESET
- GPIO_NR_PALMLD_POWER_DETECT
- GPIO_NR_PALMLD_POWER_SWITCH
- GPIO_NR_PALMLD_SD_DETECT_N
- GPIO_NR_PALMLD_SD_POWER
- GPIO_NR_PALMLD_SD_READONLY
- GPIO_NR_PALMLD_USB_DETECT_N
- GPIO_NR_PALMLD_USB_INT
- GPIO_NR_PALMLD_USB_POWER
- GPIO_NR_PALMLD_USB_READY
- GPIO_NR_PALMLD_USB_RESET
- GPIO_NR_PALMLD_WM9712_IRQ
- GPIO_NR_PALMT5_BL_POWER
- GPIO_NR_PALMT5_BT_POWER
- GPIO_NR_PALMT5_BT_RESET
- GPIO_NR_PALMT5_EARPHONE_DETECT
- GPIO_NR_PALMT5_GPIO_RESET
- GPIO_NR_PALMT5_HOTSYNC_BUTTON_N
- GPIO_NR_PALMT5_IR_DISABLE
- GPIO_NR_PALMT5_LCD_POWER
- GPIO_NR_PALMT5_POWER_DETECT
- GPIO_NR_PALMT5_SD_DETECT_N
- GPIO_NR_PALMT5_SD_POWER
- GPIO_NR_PALMT5_SD_READONLY
- GPIO_NR_PALMT5_USB_DETECT_N
- GPIO_NR_PALMT5_USB_PULLUP
- GPIO_NR_PALMT5_WM9712_IRQ
- GPIO_NR_PALMTC_BL_POWER
- GPIO_NR_PALMTC_CRADLE_DETECT
- GPIO_NR_PALMTC_EARPHONE_DETECT
- GPIO_NR_PALMTC_HEADPHONE_DETECT
- GPIO_NR_PALMTC_HOTSYNC_BUTTON
- GPIO_NR_PALMTC_IR_DISABLE
- GPIO_NR_PALMTC_LCD_BLANK
- GPIO_NR_PALMTC_LCD_POWER
- GPIO_NR_PALMTC_LED_POWER
- GPIO_NR_PALMTC_PCMCIA_POWER1
- GPIO_NR_PALMTC_PCMCIA_POWER2
- GPIO_NR_PALMTC_PCMCIA_POWER3
- GPIO_NR_PALMTC_PCMCIA_PWRREADY
- GPIO_NR_PALMTC_PCMCIA_READY
- GPIO_NR_PALMTC_PCMCIA_RESET
- GPIO_NR_PALMTC_POWER_DETECT
- GPIO_NR_PALMTC_RS232_POWER
- GPIO_NR_PALMTC_SD_DETECT_N
- GPIO_NR_PALMTC_SD_POWER
- GPIO_NR_PALMTC_SD_READONLY
- GPIO_NR_PALMTC_SPEAKER_ENABLE
- GPIO_NR_PALMTC_USB_DETECT_N
- GPIO_NR_PALMTC_USB_POWER
- GPIO_NR_PALMTC_VIBRA_POWER
- GPIO_NR_PALMTE2_BL_POWER
- GPIO_NR_PALMTE2_EARPHONE_DETECT
- GPIO_NR_PALMTE2_HOTSYNC_BUTTON_N
- GPIO_NR_PALMTE2_IR_DISABLE
- GPIO_NR_PALMTE2_KEY_CALENDAR
- GPIO_NR_PALMTE2_KEY_CENTER
- GPIO_NR_PALMTE2_KEY_CONTACTS
- GPIO_NR_PALMTE2_KEY_DOWN
- GPIO_NR_PALMTE2_KEY_LEFT
- GPIO_NR_PALMTE2_KEY_NOTES
- GPIO_NR_PALMTE2_KEY_RIGHT
- GPIO_NR_PALMTE2_KEY_TASKS
- GPIO_NR_PALMTE2_KEY_UP
- GPIO_NR_PALMTE2_LCD_POWER
- GPIO_NR_PALMTE2_POWER_DETECT
- GPIO_NR_PALMTE2_SD_DETECT_N
- GPIO_NR_PALMTE2_SD_POWER
- GPIO_NR_PALMTE2_SD_READONLY
- GPIO_NR_PALMTE2_USB_DETECT_N
- GPIO_NR_PALMTE2_USB_PULLUP
- GPIO_NR_PALMTX_BL_POWER
- GPIO_NR_PALMTX_BORDER_SELECT
- GPIO_NR_PALMTX_BORDER_SWITCH
- GPIO_NR_PALMTX_BT_POWER
- GPIO_NR_PALMTX_BT_RESET
- GPIO_NR_PALMTX_EARPHONE_DETECT
- GPIO_NR_PALMTX_GPIO_RESET
- GPIO_NR_PALMTX_HOTSYNC_BUTTON_N
- GPIO_NR_PALMTX_IR_DISABLE
- GPIO_NR_PALMTX_LCD_POWER
- GPIO_NR_PALMTX_NAND_BUFFER_DIR
- GPIO_NR_PALMTX_PCMCIA_POWER1
- GPIO_NR_PALMTX_PCMCIA_POWER2
- GPIO_NR_PALMTX_PCMCIA_READY
- GPIO_NR_PALMTX_PCMCIA_RESET
- GPIO_NR_PALMTX_POWER_DETECT
- GPIO_NR_PALMTX_SD_DETECT_N
- GPIO_NR_PALMTX_SD_POWER
- GPIO_NR_PALMTX_SD_READONLY
- GPIO_NR_PALMTX_USB_DETECT_N
- GPIO_NR_PALMTX_USB_PULLUP
- GPIO_NR_PALMTX_WM9712_IRQ
- GPIO_NR_PALMZ72_BL_POWER
- GPIO_NR_PALMZ72_BT_POWER
- GPIO_NR_PALMZ72_BT_RESET
- GPIO_NR_PALMZ72_CAM_POWER
- GPIO_NR_PALMZ72_CAM_PWDN
- GPIO_NR_PALMZ72_CAM_RESET
- GPIO_NR_PALMZ72_GPIO_RESET
- GPIO_NR_PALMZ72_IR_DISABLE
- GPIO_NR_PALMZ72_LCD_POWER
- GPIO_NR_PALMZ72_LED_GREEN
- GPIO_NR_PALMZ72_POWER_DETECT
- GPIO_NR_PALMZ72_SD_DETECT_N
- GPIO_NR_PALMZ72_SD_POWER_N
- GPIO_NR_PALMZ72_SD_RO
- GPIO_NR_PALMZ72_USB_DETECT_N
- GPIO_NR_PALMZ72_USB_PULLUP
- GPIO_NR_PALMZ72_WM9712_IRQ
- GPIO_NR_PINS
- GPIO_NR_TREO680_BT_EN
- GPIO_NR_TREO680_KEYB_BL
- GPIO_NR_TREO680_LCD_EN
- GPIO_NR_TREO680_LCD_EN_N
- GPIO_NR_TREO680_LCD_POWER
- GPIO_NR_TREO680_SD_POWER
- GPIO_NR_TREO680_SD_READONLY
- GPIO_NR_TREO680_VIBRATE_EN
- GPIO_NR_TREO_AMP_EN
- GPIO_NR_TREO_BL_POWER
- GPIO_NR_TREO_EP_DETECT_N
- GPIO_NR_TREO_GREEN_LED
- GPIO_NR_TREO_GSM_HOST_WAKE
- GPIO_NR_TREO_GSM_POWER
- GPIO_NR_TREO_GSM_RESET
- GPIO_NR_TREO_GSM_TRIGGER
- GPIO_NR_TREO_GSM_WAKE
- GPIO_NR_TREO_IR_EN
- GPIO_NR_TREO_IR_TXD
- GPIO_NR_TREO_LCD_POWER
- GPIO_NR_TREO_POWER_DETECT
- GPIO_NR_TREO_RED_LED
- GPIO_NR_TREO_SD_DETECT_N
- GPIO_NR_TREO_USB_DETECT
- GPIO_NR_TREO_USB_PULLUP
- GPIO_NUM
- GPIO_NUM_PER_GROUP
- GPIO_OCR_MASK
- GPIO_OCR_SHIFT
- GPIO_OD
- GPIO_OD33_CTRL8
- GPIO_ODR
- GPIO_OD_REG
- GPIO_OE
- GPIO_OFFSET
- GPIO_ONTIME_SHIFT
- GPIO_OPEN_DRAIN
- GPIO_OPEN_SOURCE
- GPIO_OUT
- GPIO_OUTEN
- GPIO_OUTPUT
- GPIO_OUTPUT_AUX1
- GPIO_OUTPUT_AUX2
- GPIO_OUTPUT_EN
- GPIO_OUTPUT_ENABLE
- GPIO_OUTPUT_INVERT
- GPIO_OUTPUT_OK
- GPIO_OUTPUT_OPEN_DRAIN
- GPIO_OUTPUT_VAL
- GPIO_OUT_8811A
- GPIO_OUT_CLEAR
- GPIO_OUT_CTRL_BASE
- GPIO_OUT_OFF
- GPIO_OUT_REG
- GPIO_OUT_SET
- GPIO_OUT_STATUS
- GPIO_OVRUN_BIT
- GPIO_PA0
- GPIO_PA1
- GPIO_PA2
- GPIO_PA3
- GPIO_PA4
- GPIO_PA5
- GPIO_PA6
- GPIO_PA7
- GPIO_PADDRV
- GPIO_PAD_HCI_SEL
- GPIO_PB0
- GPIO_PB1
- GPIO_PB10
- GPIO_PB11
- GPIO_PB12
- GPIO_PB13
- GPIO_PB14
- GPIO_PB15
- GPIO_PB16
- GPIO_PB17
- GPIO_PB18
- GPIO_PB19
- GPIO_PB2
- GPIO_PB20
- GPIO_PB21
- GPIO_PB22
- GPIO_PB3
- GPIO_PB4
- GPIO_PB5
- GPIO_PB6
- GPIO_PB7
- GPIO_PB8
- GPIO_PB9
- GPIO_PC0
- GPIO_PC1
- GPIO_PC10
- GPIO_PC11
- GPIO_PC12
- GPIO_PC13
- GPIO_PC14
- GPIO_PC2
- GPIO_PC3
- GPIO_PC4
- GPIO_PC5
- GPIO_PC6
- GPIO_PC7
- GPIO_PC8
- GPIO_PC9
- GPIO_PCD
- GPIO_PCI
- GPIO_PCI_SUSEN
- GPIO_PCMCIA_RESET
- GPIO_PCMCIA_S0_CD_VALID
- GPIO_PCMCIA_S0_RDYINT
- GPIO_PCMCIA_S1_CD_VALID
- GPIO_PCMCIA_S1_RDYINT
- GPIO_PCMCIA_SKTSEL
- GPIO_PCOR
- GPIO_PC_CD0
- GPIO_PC_CD1
- GPIO_PC_READY0
- GPIO_PC_READY1
- GPIO_PC_RESET0
- GPIO_PC_RESET1
- GPIO_PD0
- GPIO_PD1
- GPIO_PD10
- GPIO_PD11
- GPIO_PD12
- GPIO_PD13
- GPIO_PD14
- GPIO_PD15
- GPIO_PD2
- GPIO_PD3
- GPIO_PD4
- GPIO_PD5
- GPIO_PD6
- GPIO_PD7
- GPIO_PD8
- GPIO_PD9
- GPIO_PDDR
- GPIO_PDIR
- GPIO_PDN_BT_N
- GPIO_PDN_GPS_N
- GPIO_PDOR
- GPIO_PE0
- GPIO_PE1
- GPIO_PE10
- GPIO_PE11
- GPIO_PE12
- GPIO_PE13
- GPIO_PE14
- GPIO_PE15
- GPIO_PE2
- GPIO_PE3
- GPIO_PE4
- GPIO_PE5
- GPIO_PE6
- GPIO_PE7
- GPIO_PE8
- GPIO_PE9
- GPIO_PECR
- GPIO_PERSISTENT
- GPIO_PER_BANK
- GPIO_PER_REG
- GPIO_PF
- GPIO_PF0
- GPIO_PF1
- GPIO_PF10
- GPIO_PF11
- GPIO_PF12
- GPIO_PF13
- GPIO_PF14
- GPIO_PF15
- GPIO_PF16
- GPIO_PF17
- GPIO_PF18
- GPIO_PF19
- GPIO_PF2
- GPIO_PF20
- GPIO_PF21
- GPIO_PF22
- GPIO_PF23
- GPIO_PF24
- GPIO_PF25
- GPIO_PF26
- GPIO_PF27
- GPIO_PF28
- GPIO_PF29
- GPIO_PF3
- GPIO_PF30
- GPIO_PF4
- GPIO_PF5
- GPIO_PF6
- GPIO_PF7
- GPIO_PF8
- GPIO_PF9
- GPIO_PG0
- GPIO_PG1
- GPIO_PG10
- GPIO_PG11
- GPIO_PG12
- GPIO_PG13
- GPIO_PG14
- GPIO_PG15
- GPIO_PG16
- GPIO_PG17
- GPIO_PG18
- GPIO_PG19
- GPIO_PG2
- GPIO_PG20
- GPIO_PG21
- GPIO_PG22
- GPIO_PG23
- GPIO_PG24
- GPIO_PG25
- GPIO_PG26
- GPIO_PG27
- GPIO_PG3
- GPIO_PG4
- GPIO_PG5
- GPIO_PG6
- GPIO_PG7
- GPIO_PG8
- GPIO_PG9
- GPIO_PH0
- GPIO_PH1
- GPIO_PH2
- GPIO_PH3
- GPIO_PH4
- GPIO_PH5
- GPIO_PH6
- GPIO_PH7
- GPIO_PHANTOM_OFF
- GPIO_PHCR
- GPIO_PHY_INTERRUPT
- GPIO_PIC
- GPIO_PIN
- GPIO_PIN0_CONFIG_LSB
- GPIO_PIN0_CONFIG_MASK
- GPIO_PIN0_OFFSET
- GPIO_PIN0_PAD_PULL_LSB
- GPIO_PIN0_PAD_PULL_MASK
- GPIO_PIN10_ADDRESS
- GPIO_PIN10_OFFSET
- GPIO_PIN11_ADDRESS
- GPIO_PIN11_OFFSET
- GPIO_PIN12_ADDRESS
- GPIO_PIN12_OFFSET
- GPIO_PIN13_ADDRESS
- GPIO_PIN13_OFFSET
- GPIO_PIN1_CONFIG_MASK
- GPIO_PIN1_OFFSET
- GPIO_PIN9_ADDRESS
- GPIO_PINGROUP
- GPIO_PINMUX_OTHR_6328_USB_DEV
- GPIO_PINMUX_OTHR_6328_USB_HOST
- GPIO_PINMUX_OTHR_6328_USB_MASK
- GPIO_PINMUX_OTHR_6328_USB_SHIFT
- GPIO_PINMUX_OTHR_REG
- GPIO_PINRANGE
- GPIO_PIN_ACTIVE_HIGH
- GPIO_PIN_ADD_DDC
- GPIO_PIN_ADD_DDC_I2C
- GPIO_PIN_ADD_I2C
- GPIO_PIN_ASCB
- GPIO_PIN_BT_RST
- GPIO_PIN_CONFIG
- GPIO_PIN_CONTROL_PARAMETERS
- GPIO_PIN_CTL0
- GPIO_PIN_CTL1
- GPIO_PIN_CTL2
- GPIO_PIN_CTL3
- GPIO_PIN_DECL
- GPIO_PIN_DVI_LVDS
- GPIO_PIN_INIC_RST
- GPIO_PIN_MASK
- GPIO_PIN_OF_IRQ
- GPIO_PIN_OUTPUT_STATE_ACTIVE_HIGH
- GPIO_PIN_OUTPUT_STATE_ACTIVE_LOW
- GPIO_PIN_OUTPUT_STATE_DEFAULT
- GPIO_PIN_OUTPUT_STATE_MASK
- GPIO_PIN_OUTPUT_STATE_SHIFT
- GPIO_PIN_READ
- GPIO_PIN_STATE_ACTIVE_HIGH
- GPIO_PIN_STATE_ACTIVE_LOW
- GPIO_PIN_TYPE_HW_CONTROL
- GPIO_PIN_TYPE_INPUT
- GPIO_PIN_TYPE_OUTPUT
- GPIO_PIN_WRITE
- GPIO_PJ0
- GPIO_PJ1
- GPIO_PJ10
- GPIO_PJ11
- GPIO_PJ12
- GPIO_PJ13
- GPIO_PJ14
- GPIO_PJ15
- GPIO_PJ16
- GPIO_PJ17
- GPIO_PJ18
- GPIO_PJ19
- GPIO_PJ2
- GPIO_PJ20
- GPIO_PJ21
- GPIO_PJ22
- GPIO_PJ23
- GPIO_PJ24
- GPIO_PJ25
- GPIO_PJ26
- GPIO_PJ27
- GPIO_PJ28
- GPIO_PJ29
- GPIO_PJ3
- GPIO_PJ30
- GPIO_PJ31
- GPIO_PJ4
- GPIO_PJ5
- GPIO_PJ6
- GPIO_PJ7
- GPIO_PJ8
- GPIO_PJ9
- GPIO_PK0
- GPIO_PK1
- GPIO_PK10
- GPIO_PK11
- GPIO_PK2
- GPIO_PK3
- GPIO_PK4
- GPIO_PK5
- GPIO_PK6
- GPIO_PK7
- GPIO_PK8
- GPIO_PK9
- GPIO_PKG_SEL_HCI
- GPIO_PL0
- GPIO_PL1
- GPIO_PL2
- GPIO_PL3
- GPIO_PL4
- GPIO_PL5
- GPIO_PL6
- GPIO_PL7
- GPIO_PLR
- GPIO_PM0
- GPIO_PM1
- GPIO_PME_STATUS
- GPIO_PMIC_INT
- GPIO_PMSELR
- GPIO_PN0
- GPIO_PN1
- GPIO_PN2
- GPIO_PN3
- GPIO_PN4
- GPIO_PN5
- GPIO_PN6
- GPIO_PN7
- GPIO_PORT
- GPIO_PORTA
- GPIO_PORTA_DEBOUNCE
- GPIO_PORTA_EOI
- GPIO_PORTA_EOI_V2
- GPIO_PORTB
- GPIO_PORTC
- GPIO_PORTD
- GPIO_PORTE
- GPIO_PORTF
- GPIO_PORTS_EOI
- GPIO_PORT_CTL
- GPIO_PORT_MASK
- GPIO_PORT_SHIFT
- GPIO_POSITIVE_EDGE_EN
- GPIO_POSITIVE_EDGE_STS
- GPIO_POWER
- GPIO_POWER_BUTTON
- GPIO_PP0
- GPIO_PP1
- GPIO_PP2
- GPIO_PP3
- GPIO_PP4
- GPIO_PP5
- GPIO_PPHY_SUSB
- GPIO_PQ0
- GPIO_PQ1
- GPIO_PQ2
- GPIO_PQ3
- GPIO_PQ4
- GPIO_PR0
- GPIO_PR1
- GPIO_PR2
- GPIO_PR3
- GPIO_PRDY
- GPIO_PSOR
- GPIO_PSR
- GPIO_PT
- GPIO_PTA0
- GPIO_PTA1
- GPIO_PTA2
- GPIO_PTA3
- GPIO_PTA4
- GPIO_PTA5
- GPIO_PTA6
- GPIO_PTA7
- GPIO_PTB0
- GPIO_PTB1
- GPIO_PTB2
- GPIO_PTB3
- GPIO_PTB4
- GPIO_PTB5
- GPIO_PTB6
- GPIO_PTB7
- GPIO_PTC0
- GPIO_PTC1
- GPIO_PTC2
- GPIO_PTC3
- GPIO_PTC4
- GPIO_PTC5
- GPIO_PTC6
- GPIO_PTC7
- GPIO_PTD0
- GPIO_PTD1
- GPIO_PTD2
- GPIO_PTD3
- GPIO_PTD4
- GPIO_PTD5
- GPIO_PTD6
- GPIO_PTD7
- GPIO_PTE0
- GPIO_PTE1
- GPIO_PTE2
- GPIO_PTE3
- GPIO_PTE4
- GPIO_PTE5
- GPIO_PTE6
- GPIO_PTE7
- GPIO_PTF0
- GPIO_PTF1
- GPIO_PTF2
- GPIO_PTF3
- GPIO_PTF4
- GPIO_PTF5
- GPIO_PTF6
- GPIO_PTF7
- GPIO_PTG0
- GPIO_PTG1
- GPIO_PTG2
- GPIO_PTG3
- GPIO_PTG4
- GPIO_PTG5
- GPIO_PTG6
- GPIO_PTG7
- GPIO_PTH0
- GPIO_PTH1
- GPIO_PTH2
- GPIO_PTH3
- GPIO_PTH4
- GPIO_PTH5
- GPIO_PTH6
- GPIO_PTH7
- GPIO_PTI0
- GPIO_PTI1
- GPIO_PTI2
- GPIO_PTI3
- GPIO_PTI4
- GPIO_PTI5
- GPIO_PTI6
- GPIO_PTI7
- GPIO_PTJ0
- GPIO_PTJ1
- GPIO_PTJ2
- GPIO_PTJ3
- GPIO_PTJ4
- GPIO_PTJ5
- GPIO_PTJ6
- GPIO_PTJ7
- GPIO_PTK0
- GPIO_PTK1
- GPIO_PTK2
- GPIO_PTK3
- GPIO_PTK4
- GPIO_PTK5
- GPIO_PTK6
- GPIO_PTK7
- GPIO_PTL0
- GPIO_PTL1
- GPIO_PTL2
- GPIO_PTL3
- GPIO_PTL4
- GPIO_PTL5
- GPIO_PTL6
- GPIO_PTL7
- GPIO_PTM0
- GPIO_PTM1
- GPIO_PTM2
- GPIO_PTM3
- GPIO_PTM4
- GPIO_PTM5
- GPIO_PTM6
- GPIO_PTM7
- GPIO_PTN0
- GPIO_PTN1
- GPIO_PTN2
- GPIO_PTN3
- GPIO_PTN4
- GPIO_PTN5
- GPIO_PTN6
- GPIO_PTN7
- GPIO_PTO0
- GPIO_PTO1
- GPIO_PTO2
- GPIO_PTO3
- GPIO_PTO4
- GPIO_PTO5
- GPIO_PTO6
- GPIO_PTO7
- GPIO_PTOR
- GPIO_PTP0
- GPIO_PTP1
- GPIO_PTP2
- GPIO_PTP3
- GPIO_PTP4
- GPIO_PTP5
- GPIO_PTP6
- GPIO_PTP7
- GPIO_PTQ0
- GPIO_PTQ1
- GPIO_PTQ2
- GPIO_PTQ3
- GPIO_PTQ4
- GPIO_PTQ5
- GPIO_PTQ6
- GPIO_PTQ7
- GPIO_PTR
- GPIO_PTR0
- GPIO_PTR1
- GPIO_PTR2
- GPIO_PTR3
- GPIO_PTR4
- GPIO_PTR5
- GPIO_PTR6
- GPIO_PTR7
- GPIO_PTS0
- GPIO_PTS1
- GPIO_PTS2
- GPIO_PTS3
- GPIO_PTS4
- GPIO_PTS5
- GPIO_PTS6
- GPIO_PTS7
- GPIO_PTT0
- GPIO_PTT1
- GPIO_PTT2
- GPIO_PTT3
- GPIO_PTT4
- GPIO_PTT5
- GPIO_PTT6
- GPIO_PTT7
- GPIO_PTU0
- GPIO_PTU1
- GPIO_PTU2
- GPIO_PTU3
- GPIO_PTU4
- GPIO_PTU5
- GPIO_PTU6
- GPIO_PTU7
- GPIO_PTV0
- GPIO_PTV1
- GPIO_PTV2
- GPIO_PTV3
- GPIO_PTV4
- GPIO_PTV5
- GPIO_PTV6
- GPIO_PTV7
- GPIO_PTW0
- GPIO_PTW1
- GPIO_PTW2
- GPIO_PTW3
- GPIO_PTW4
- GPIO_PTW5
- GPIO_PTW6
- GPIO_PTW7
- GPIO_PTX0
- GPIO_PTX1
- GPIO_PTX2
- GPIO_PTX3
- GPIO_PTX4
- GPIO_PTX5
- GPIO_PTX6
- GPIO_PTX7
- GPIO_PTY0
- GPIO_PTY1
- GPIO_PTY2
- GPIO_PTY3
- GPIO_PTY4
- GPIO_PTY5
- GPIO_PTY6
- GPIO_PTY7
- GPIO_PTZ0
- GPIO_PTZ1
- GPIO_PTZ2
- GPIO_PTZ3
- GPIO_PTZ4
- GPIO_PTZ5
- GPIO_PTZ6
- GPIO_PTZ7
- GPIO_PUDEN
- GPIO_PUDSEL
- GPIO_PUEN
- GPIO_PUEN_MASK
- GPIO_PUEN_SHIFT
- GPIO_PULL1
- GPIO_PULL2
- GPIO_PULL3
- GPIO_PULLDN
- GPIO_PULLUP
- GPIO_PULL_DOWN
- GPIO_PULL_EN
- GPIO_PULL_TYPE
- GPIO_PULL_UP
- GPIO_PUSH_PULL
- GPIO_PWDN
- GPIO_PWD_STATUS
- GPIO_PWRON_RESET_CFG_REG
- GPIO_QUADUART_INT
- GPIO_QUEUE_STARTED
- GPIO_QUIRK_DATA_RO_BUG
- GPIO_RATE_16000
- GPIO_RATE_176400
- GPIO_RATE_192000
- GPIO_RATE_22050
- GPIO_RATE_24000
- GPIO_RATE_32000
- GPIO_RATE_44100
- GPIO_RATE_48000
- GPIO_RATE_64000
- GPIO_RATE_88200
- GPIO_RATE_96000
- GPIO_RATE_MASK
- GPIO_RATE_SELECT
- GPIO_RCLK
- GPIO_RDY
- GPIO_READ_BACK
- GPIO_RED_LED
- GPIO_REG
- GPIO_REGEVT
- GPIO_REGEVT_INTMSK
- GPIO_REGEVT_INTPOL
- GPIO_REGISTER
- GPIO_REGS_SIZE
- GPIO_REG_ADDR
- GPIO_REG_CTRL
- GPIO_REG_DATA
- GPIO_REG_DCLR
- GPIO_REG_DSET
- GPIO_REG_EDGE
- GPIO_REG_FEDGE
- GPIO_REG_H
- GPIO_REG_HLVL
- GPIO_REG_IO
- GPIO_REG_IO_CLEAR
- GPIO_REG_IO_SET
- GPIO_REG_IO_TOGGLE
- GPIO_REG_LLVL
- GPIO_REG_OFFSET
- GPIO_REG_OFFSET_V2
- GPIO_REG_POL
- GPIO_REG_REDGE
- GPIO_REG_SHIFT
- GPIO_REG_STAT
- GPIO_RESET
- GPIO_RESULT_ALREADY_OPENED
- GPIO_RESULT_DEVICE_BUSY
- GPIO_RESULT_INVALID_DATA
- GPIO_RESULT_NON_SPECIFIC_ERROR
- GPIO_RESULT_NULL_HANDLE
- GPIO_RESULT_OK
- GPIO_RESULT_OPEN_FAILED
- GPIO_RFA_CTL
- GPIO_RFB_CTL
- GPIO_RF_RL_ID
- GPIO_RI
- GPIO_RNG_REG
- GPIO_RST
- GPIO_RTC_BOUNCE_ENABLE
- GPIO_RTC_BOUNCE_PRE_SCALE
- GPIO_RTC_DATA_CLEAR
- GPIO_RTC_DATA_SET
- GPIO_RTC_DATE_R
- GPIO_RTC_DATE_W
- GPIO_RTC_DAY_R
- GPIO_RTC_DAY_W
- GPIO_RTC_DELAY_TIME
- GPIO_RTC_HOURS_R
- GPIO_RTC_HOURS_W
- GPIO_RTC_INT_BOTH
- GPIO_RTC_INT_CLEAR
- GPIO_RTC_INT_ENABLE
- GPIO_RTC_INT_MASK
- GPIO_RTC_INT_MASKED_STATE
- GPIO_RTC_INT_RAW_STATE
- GPIO_RTC_INT_RISE_NEG
- GPIO_RTC_INT_TRIGGER
- GPIO_RTC_MINUTES_R
- GPIO_RTC_MINUTES_W
- GPIO_RTC_MONTH_R
- GPIO_RTC_MONTH_W
- GPIO_RTC_PIN_PULL_ENABLE
- GPIO_RTC_PIN_PULL_TYPE
- GPIO_RTC_PROTECT_R
- GPIO_RTC_PROTECT_W
- GPIO_RTC_RESERVED
- GPIO_RTC_SECONDS_R
- GPIO_RTC_SECONDS_W
- GPIO_RTC_YEAR_R
- GPIO_RTC_YEAR_W
- GPIO_RTS
- GPIO_RXMCLK_SEL
- GPIO_RXUVL_BIT
- GPIO_RX_DAT
- GPIO_SAMSUNG_S3C24XX_H
- GPIO_SAMSUNG_S3C64XX_H
- GPIO_SCL
- GPIO_SCR
- GPIO_SDA
- GPIO_SDLC_AAF
- GPIO_SDLC_SCLK
- GPIO_SEL
- GPIO_SET_DEBOUNCE1
- GPIO_SET_DEBOUNCE2
- GPIO_SET_DR_OFFSET
- GPIO_SET_MASK
- GPIO_SET_SHIFT
- GPIO_SIGNAL_SOURCE_DACA_HSYNC
- GPIO_SIGNAL_SOURCE_DACA_STEREO_SYNC
- GPIO_SIGNAL_SOURCE_DACA_VSYNC
- GPIO_SIGNAL_SOURCE_DACB_HSYNC
- GPIO_SIGNAL_SOURCE_DACB_STEREO_SYNC
- GPIO_SIGNAL_SOURCE_DACB_VSYNC
- GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC
- GPIO_SIGNAL_SOURCE_UNKNOWN
- GPIO_SINGLE_ENDED
- GPIO_SLEEP_MASK
- GPIO_SLEEP_SHIFT
- GPIO_SLIM_FIRMWARE_CLK
- GPIO_SLIM_FIRMWARE_DATA
- GPIO_SLIM_HDMI_DISABLE
- GPIO_SLIM_OUTPUT_ENABLE
- GPIO_SMART_CARD
- GPIO_SPDIF_IN_INV
- GPIO_SPEED
- GPIO_SPI
- GPIO_SPI_ALL
- GPIO_SPI_CSN0
- GPIO_SPI_CSN1
- GPIO_SSP_CLK
- GPIO_SSP_RXD
- GPIO_SSP_SCLK
- GPIO_SSP_SFRM
- GPIO_SSP_TXD
- GPIO_STATUS
- GPIO_STEREO_SOURCE_D1
- GPIO_STEREO_SOURCE_D2
- GPIO_STEREO_SOURCE_D3
- GPIO_STEREO_SOURCE_D4
- GPIO_STEREO_SOURCE_D5
- GPIO_STEREO_SOURCE_D6
- GPIO_STEREO_SOURCE_UNKNOWN
- GPIO_STR
- GPIO_STRAPBUS_REG
- GPIO_STS_MASK
- GPIO_STS_SHIFT
- GPIO_ST_HP
- GPIO_ST_HP_REAR
- GPIO_ST_MAGIC
- GPIO_ST_OUTPUT_ENABLE
- GPIO_SUPPORTED_BIT
- GPIO_SWITCH
- GPIO_SWITCH_0
- GPIO_SWITCH_1
- GPIO_SWITCH_2
- GPIO_SWITCH_3
- GPIO_SWITCH_4
- GPIO_SWITCH_5
- GPIO_SWITCH_6
- GPIO_SWITCH_7
- GPIO_SWPORTA_DDR
- GPIO_SWPORTA_DR
- GPIO_SWPORTB_DDR
- GPIO_SWPORTB_DR
- GPIO_SWPORTC_DDR
- GPIO_SWPORTC_DR
- GPIO_SWPORTD_DDR
- GPIO_SWPORTD_DR
- GPIO_SWPORT_DDR
- GPIO_SWPORT_DDR_STRIDE
- GPIO_SWPORT_DR
- GPIO_SWPORT_DR_STRIDE
- GPIO_SWRESET_REG
- GPIO_SYNC_COUNT
- GPIO_SYNC_HSYNC_A
- GPIO_SYNC_HSYNC_B
- GPIO_SYNC_MAX
- GPIO_SYNC_MIN
- GPIO_SYNC_UNKNOWN
- GPIO_SYNC_VSYNC_A
- GPIO_SYNC_VSYNC_B
- GPIO_SYSCON_FEAT_DIR
- GPIO_SYSCON_FEAT_IN
- GPIO_SYSCON_FEAT_OUT
- GPIO_SYS_BUSY_LED
- GPIO_TABLE_SIZE
- GPIO_TEST_N
- GPIO_TIC_ACK
- GPIO_TOGGLE_THRESHOLD
- GPIO_TO_BANK
- GPIO_TO_DBCNT_REG
- GPIO_TO_HWIRQ
- GPIO_TO_PIN
- GPIO_TRANSITORY
- GPIO_TREQA
- GPIO_TREQB
- GPIO_TUNER
- GPIO_TX_CLR
- GPIO_TX_COMPLETION
- GPIO_TX_DISABLE
- GPIO_TX_FAULT
- GPIO_TX_FRAGMENT
- GPIO_TX_FUNCTION
- GPIO_TX_SET
- GPIO_UART0_DCD
- GPIO_UART1_CTS
- GPIO_UART1_DCD
- GPIO_UART1_DSR
- GPIO_UART1_DTR
- GPIO_UART1_RTS
- GPIO_UART3_CTS
- GPIO_UART3_DCD
- GPIO_UART3_DSR
- GPIO_UART3_DTR
- GPIO_UART3_RTS
- GPIO_UART_RXD
- GPIO_UART_SCLK1
- GPIO_UART_SCLK3
- GPIO_UART_TXD
- GPIO_UCB1300_IRQ
- GPIO_UCB1400
- GPIO_ULPI_PHY_RST
- GPIO_UPHY_SUSB
- GPIO_USBOE
- GPIO_USBRN
- GPIO_USBRP
- GPIO_USBTN
- GPIO_USBTP
- GPIO_USB_4PIN_ULPI_2430C
- GPIO_USB_SUSEN
- GPIO_USE_SAMPLE_DLY_MASK
- GPIO_USE_SEL
- GPIO_USE_SEL2
- GPIO_VAL_DIR
- GPIO_VAL_VALUE
- GPIO_VARIANT_VULCAN
- GPIO_VBUS
- GPIO_VGA_DDC
- GPIO_VIP_PAD_COUNT
- GPIO_VIP_PAD_DVALID
- GPIO_VIP_PAD_MAX
- GPIO_VIP_PAD_MIN
- GPIO_VIP_PAD_PSYNC
- GPIO_VIP_PAD_SCL
- GPIO_VIP_PAD_SDA
- GPIO_VIP_PAD_UNKNOWN
- GPIO_VIP_PAD_VHAD
- GPIO_VIP_PAD_VID
- GPIO_VIP_PAD_VIPCLK
- GPIO_VIP_PAD_VPCLK0
- GPIO_VIP_PAD_VPHCTL
- GPIO_VIRT_BASE
- GPIO_VSH
- GPIO_VSL
- GPIO_WAKE
- GPIO_WAKE_GPIOPOL0_
- GPIO_WAKE_GPIOPOL10_
- GPIO_WAKE_GPIOPOL11_
- GPIO_WAKE_GPIOPOL1_
- GPIO_WAKE_GPIOPOL2_
- GPIO_WAKE_GPIOPOL3_
- GPIO_WAKE_GPIOPOL4_
- GPIO_WAKE_GPIOPOL5_
- GPIO_WAKE_GPIOPOL6_
- GPIO_WAKE_GPIOPOL7_
- GPIO_WAKE_GPIOPOL8_
- GPIO_WAKE_GPIOPOL9_
- GPIO_WAKE_GPIOPOL_MASK_
- GPIO_WAKE_GPIOWK0_
- GPIO_WAKE_GPIOWK10_
- GPIO_WAKE_GPIOWK11_
- GPIO_WAKE_GPIOWK1_
- GPIO_WAKE_GPIOWK2_
- GPIO_WAKE_GPIOWK3_
- GPIO_WAKE_GPIOWK4_
- GPIO_WAKE_GPIOWK5_
- GPIO_WAKE_GPIOWK6_
- GPIO_WAKE_GPIOWK7_
- GPIO_WAKE_GPIOWK8_
- GPIO_WAKE_GPIOWK9_
- GPIO_WAKE_GPIOWK_MASK_
- GPIO_WAKE_PHY_LINKUP_EN
- GPIO_WAKE_POL
- GPIO_WAKE_POL_SHIFT
- GPIO_WAKE_WK
- GPIO_WDTIMER
- GPIO_WD_ENAB
- GPIO_WD_FAST
- GPIO_WD_RST0
- GPIO_WD_RST1
- GPIO_WD_RST2
- GPIO_WD_TRIG
- GPIO_WLRF_HWPDN_N
- GPIO_WPB
- GPIO_WPX
- GPIO_XENSE_OUTPUT_ENABLE
- GPIO_XENSE_SPEAKERS
- GPIO_Y_0
- GPIO_Y_1
- GPIO_bit
- GPIO_nVBUS_DRV
- GPIOxx_LCD_16BPP
- GPIOxx_LCD_DSTN_16BPP
- GPIOxx_LCD_TFT_16BPP
- GPIP
- GPIROUTNMI
- GPIR_WORD
- GPIT1R0
- GPIT1R1
- GPIWP_BIT
- GPI_BAT_DET
- GPI_BTN_TOUCH
- GPI_DOCKING_STATUS
- GPI_EM1
- GPI_EM2
- GPI_EM3
- GPI_EXT_POWER
- GPI_HEADPHONE_SENSE
- GPI_IEN
- GPI_IIS_CLK
- GPI_IIS_DATA
- GPI_IIS_LRCLK
- GPI_INT
- GPI_INV
- GPI_LCD_CASE_OFF
- GPI_LINEOUT_SENSE
- GPI_LOGIC
- GPI_LOGIC1
- GPI_LOGIC2
- GPI_NMI_ENA_GPP_D_0
- GPI_NMI_STS_GPP_D_0
- GPI_OTP_INT
- GPI_PCI_INTA
- GPI_PCI_INTB
- GPI_PCI_INTC
- GPI_PCI_INTD
- GPI_PIN_BASE
- GPI_PIN_COL0
- GPI_PIN_COL1
- GPI_PIN_COL2
- GPI_PIN_COL3
- GPI_PIN_COL4
- GPI_PIN_COL5
- GPI_PIN_COL6
- GPI_PIN_COL7
- GPI_PIN_COL8
- GPI_PIN_COL9
- GPI_PIN_COL_BASE
- GPI_PIN_COL_END
- GPI_PIN_END
- GPI_PIN_ROW0
- GPI_PIN_ROW1
- GPI_PIN_ROW2
- GPI_PIN_ROW3
- GPI_PIN_ROW4
- GPI_PIN_ROW5
- GPI_PIN_ROW6
- GPI_PIN_ROW7
- GPI_PIN_ROW_BASE
- GPI_PIN_ROW_END
- GPI_REG
- GPI_SD_CD
- GPI_SD_WP
- GPI_SOFF_REQ
- GPI_VOL_DOWN
- GPI_VOL_UP
- GPLAST
- GPLEN0
- GPLEV0
- GPLL0
- GPLL0_EARLY
- GPLL0_MAIN
- GPLL0_OUT_EVEN
- GPLL0_OUT_MAIN
- GPLL0_OUT_MSSCC
- GPLL0_OUT_ODD
- GPLL0_OUT_TEST
- GPLL0_VOTE
- GPLL1
- GPLL1_EARLY
- GPLL1_OUT_EVEN
- GPLL1_OUT_MAIN
- GPLL1_OUT_ODD
- GPLL1_OUT_TEST
- GPLL1_VOTE
- GPLL2
- GPLL2_EARLY
- GPLL2_MAIN
- GPLL2_OUT_EVEN
- GPLL2_OUT_MAIN
- GPLL2_OUT_ODD
- GPLL2_OUT_TEST
- GPLL2_VOTE
- GPLL3
- GPLL3_EARLY
- GPLL3_OUT_EVEN
- GPLL3_OUT_MAIN
- GPLL3_OUT_ODD
- GPLL3_OUT_TEST
- GPLL3_VOTE
- GPLL4
- GPLL4_EARLY
- GPLL4_MAIN
- GPLL4_OUT_EVEN
- GPLL4_OUT_MAIN
- GPLL4_OUT_ODD
- GPLL4_OUT_TEST
- GPLL4_VOTE
- GPLL6
- GPLL6_MAIN
- GPLL6_OUT_EVEN
- GPLL6_OUT_MAIN
- GPLL6_OUT_ODD
- GPLL6_OUT_TEST
- GPLL7
- GPLL9
- GPLLENABLE
- GPLL_CON0
- GPLL_LOCK
- GPLR
- GPLR_OFFSET
- GPLUT
- GPLUT_LUTADR
- GPLUT_LUTDATA
- GPL_DMER_MASK_DISA
- GPL_ONLY
- GPM
- GPMC_BCH_NUM_REMAINDER
- GPMC_BCH_SIZE
- GPMC_BURST_16
- GPMC_BURST_4
- GPMC_BURST_8
- GPMC_CD_CLK
- GPMC_CD_FCLK
- GPMC_CHUNK_SHIFT
- GPMC_CONFIG
- GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX
- GPMC_CONFIG1_CLKACTIVATIONTIME
- GPMC_CONFIG1_CLKACTIVATIONTIME_MAX
- GPMC_CONFIG1_DEVICESIZE
- GPMC_CONFIG1_DEVICESIZE_16
- GPMC_CONFIG1_DEVICESIZE_MAX
- GPMC_CONFIG1_DEVICETYPE
- GPMC_CONFIG1_DEVICETYPE_NOR
- GPMC_CONFIG1_FCLK_DIV
- GPMC_CONFIG1_FCLK_DIV2
- GPMC_CONFIG1_FCLK_DIV3
- GPMC_CONFIG1_FCLK_DIV4
- GPMC_CONFIG1_MUXTYPE
- GPMC_CONFIG1_PAGE_LEN
- GPMC_CONFIG1_READMULTIPLE_SUPP
- GPMC_CONFIG1_READTYPE_ASYNC
- GPMC_CONFIG1_READTYPE_SYNC
- GPMC_CONFIG1_TIME_PARA_GRAN
- GPMC_CONFIG1_WAITMONITORINGTIME_MAX
- GPMC_CONFIG1_WAIT_MON_TIME
- GPMC_CONFIG1_WAIT_PIN_SEL
- GPMC_CONFIG1_WAIT_READ_MON
- GPMC_CONFIG1_WAIT_WRITE_MON
- GPMC_CONFIG1_WRAPBURST_SUPP
- GPMC_CONFIG1_WRITEMULTIPLE_SUPP
- GPMC_CONFIG1_WRITETYPE_ASYNC
- GPMC_CONFIG1_WRITETYPE_SYNC
- GPMC_CONFIG2_CSEXTRADELAY
- GPMC_CONFIG3_ADVEXTRADELAY
- GPMC_CONFIG4_OEEXTRADELAY
- GPMC_CONFIG4_WEEXTRADELAY
- GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN
- GPMC_CONFIG6_CYCLE2CYCLESAMECSEN
- GPMC_CONFIG7_BASEADDRESS_MASK
- GPMC_CONFIG7_CSVALID
- GPMC_CONFIG7_CSVALID_MASK
- GPMC_CONFIG7_MASK
- GPMC_CONFIG7_MASKADDRESS_MASK
- GPMC_CONFIG7_MASKADDRESS_OFFSET
- GPMC_CONFIG_DEV_SIZE
- GPMC_CONFIG_DEV_TYPE
- GPMC_CONFIG_LIMITEDADDRESS
- GPMC_CONFIG_RDY_BSY
- GPMC_CONFIG_WP
- GPMC_CONFIG_WRITEPROTECT
- GPMC_CS0_OFFSET
- GPMC_CS_CONFIG1
- GPMC_CS_CONFIG2
- GPMC_CS_CONFIG3
- GPMC_CS_CONFIG4
- GPMC_CS_CONFIG5
- GPMC_CS_CONFIG6
- GPMC_CS_CONFIG7
- GPMC_CS_NAND_ADDRESS
- GPMC_CS_NAND_COMMAND
- GPMC_CS_NAND_DATA
- GPMC_CS_NUM
- GPMC_CS_RESERVED
- GPMC_CS_SIZE
- GPMC_DEVICETYPE_NAND
- GPMC_DEVICETYPE_NOR
- GPMC_DEVWIDTH_16BIT
- GPMC_DEVWIDTH_8BIT
- GPMC_ECC1_RESULT
- GPMC_ECC_BCH_RESULT_0
- GPMC_ECC_BCH_RESULT_1
- GPMC_ECC_BCH_RESULT_2
- GPMC_ECC_BCH_RESULT_3
- GPMC_ECC_BCH_RESULT_4
- GPMC_ECC_BCH_RESULT_5
- GPMC_ECC_BCH_RESULT_6
- GPMC_ECC_CONFIG
- GPMC_ECC_CONTROL
- GPMC_ECC_CTRL_ECCCLEAR
- GPMC_ECC_CTRL_ECCDISABLE
- GPMC_ECC_CTRL_ECCREG1
- GPMC_ECC_CTRL_ECCREG2
- GPMC_ECC_CTRL_ECCREG3
- GPMC_ECC_CTRL_ECCREG4
- GPMC_ECC_CTRL_ECCREG5
- GPMC_ECC_CTRL_ECCREG6
- GPMC_ECC_CTRL_ECCREG7
- GPMC_ECC_CTRL_ECCREG8
- GPMC_ECC_CTRL_ECCREG9
- GPMC_ECC_READ
- GPMC_ECC_READSYN
- GPMC_ECC_SIZE_CONFIG
- GPMC_ECC_WRITE
- GPMC_ERR_ADDRESS
- GPMC_ERR_TYPE
- GPMC_GET_RAW
- GPMC_GET_RAW_BOOL
- GPMC_GET_RAW_MAX
- GPMC_GET_RAW_SHIFT_MAX
- GPMC_GET_TICKS
- GPMC_GET_TICKS_CD
- GPMC_GET_TICKS_CD_MAX
- GPMC_HAS_MUX_AAD
- GPMC_HAS_WR_ACCESS
- GPMC_HAS_WR_DATA_MUX_BUS
- GPMC_IRQENABLE
- GPMC_IRQSTATUS
- GPMC_IRQ_COUNT_EVENT
- GPMC_IRQ_FIFOEVENTENABLE
- GPMC_MEM_END
- GPMC_MEM_START
- GPMC_MUX_AAD
- GPMC_MUX_AD
- GPMC_NR_NAND_IRQS
- GPMC_NR_WAITPINS
- GPMC_PREFETCH_CONFIG1
- GPMC_PREFETCH_CONFIG2
- GPMC_PREFETCH_CONTROL
- GPMC_PREFETCH_STATUS
- GPMC_PRINT_CONFIG
- GPMC_REVISION
- GPMC_REVISION_MAJOR
- GPMC_REVISION_MINOR
- GPMC_SECTION_SHIFT
- GPMC_SET_ONE
- GPMC_SET_ONE_CD_MAX
- GPMC_STATUS
- GPMC_STATUS_EMPTYWRITEBUFFERSTATUS
- GPMC_SYSCONFIG
- GPMC_SYSSTATUS
- GPMC_TIMEOUT_CONTROL
- GPMI
- GPMISC1_GPADC_EN
- GPMI_ALE
- GPMI_CE0N
- GPMI_CE1N
- GPMI_CE2N
- GPMI_CE3N
- GPMI_CLE
- GPMI_CLK_MAX
- GPMI_D00
- GPMI_D01
- GPMI_D02
- GPMI_D03
- GPMI_D04
- GPMI_D05
- GPMI_D06
- GPMI_D07
- GPMI_D08
- GPMI_D09
- GPMI_D10
- GPMI_D11
- GPMI_D12
- GPMI_D13
- GPMI_D14
- GPMI_D15
- GPMI_IS_MX23
- GPMI_IS_MX28
- GPMI_IS_MX6
- GPMI_IS_MX6Q
- GPMI_IS_MX6SX
- GPMI_IS_MX7D
- GPMI_IS_MXS
- GPMI_MAX_TRANSFERS
- GPMI_NAND_BCH_INTERRUPT_RES_NAME
- GPMI_NAND_BCH_REGS_ADDR_RES_NAME
- GPMI_NAND_GPMI_REGS_ADDR_RES_NAME
- GPMI_RDN
- GPMI_RDY0
- GPMI_RDY1
- GPMI_RDY2
- GPMI_RDY3
- GPMI_RESETN
- GPMI_WPN
- GPMI_WRN
- GPMODE_ALL_PAGES
- GPMODE_AUDIO_CTL_PAGE
- GPMODE_CAPABILITIES_PAGE
- GPMODE_CDROM_PAGE
- GPMODE_FAULT_FAIL_PAGE
- GPMODE_POWER_PAGE
- GPMODE_R_W_ERROR_PAGE
- GPMODE_TO_PROTECT_PAGE
- GPMODE_VENDOR_PAGE
- GPMODE_WCACHING_PAGE
- GPMODE_WRITE_PARMS_PAGE
- GPMQBusy
- GPMQFull
- GPMQOver
- GPMUXCTL
- GPNUM
- GPN_FT_CMD
- GPN_FT_REQ_SIZE
- GPN_ID_CMD
- GPN_ID_REQ_SIZE
- GPN_ID_RSP_SIZE
- GPN_ID_SNS_CMD_SIZE
- GPN_ID_SNS_DATA_SIZE
- GPN_ID_SNS_SCMD_LEN
- GPO
- GPO0_MARK
- GPO1_MARK
- GPO2_MARK
- GPO3_MARK
- GPO3_PIN_IN_SEL
- GPO3_PIN_TO_BIT
- GPO4_MARK
- GPO5_MARK
- GPO6_MARK
- GPO7_MARK
- GPOCTLR_GPOG
- GPOENCTLR_GPOEN
- GPOER
- GPOR3_ADRS
- GPOR_TOPCAT_RESET
- GPOR_WORD
- GPOS
- GPOUTR
- GPO_BLINK
- GPO_BT_EN
- GPO_CAM_PWR_EN
- GPO_CPU_HEALTH
- GPO_EXT_AMP_ALLEGRO
- GPO_EXT_AMP_M3
- GPO_EXT_AMP_SHUTDOWN
- GPO_FAN_ON
- GPO_HDD_LED
- GPO_LAN_SEL
- GPO_LCD_EN
- GPO_LCD_VCC_EN
- GPO_LED_CLK
- GPO_LED_DATA
- GPO_M3_EXT_AMP_SHUTDN
- GPO_PRIMARY_AC97
- GPO_REG
- GPO_SECONDARY_AC97
- GPO_SET_V1
- GPO_SET_V2
- GPO_SOFT_OFF
- GPO_SPKR
- GPO_VGA_EN
- GPO_WIFI_EN
- GPPC
- GPPC_OFFSET
- GPPR_PHY_RESET_PIN
- GPPR_UARTA_MODESEL_PIN
- GPPR_UARTB_MODESEL_PIN
- GPPUD
- GPPUDCLK0
- GPP_CTL
- GPP_CTRL
- GPR
- GPR1
- GPR2
- GPR3
- GPREG0_DEFAULT
- GPREG0_DISSH
- GPREG0_DISSH_ALL
- GPREG0_DISSH_DW0
- GPREG0_DISSH_DW1
- GPREG0_DISSH_DW2
- GPREG0_DISSH_DW3
- GPREG0_DISSH_DW4
- GPREG0_DISSH_DW5
- GPREG0_DISSH_DW6
- GPREG0_DISSH_DW7
- GPREG0_LNKINTPOLL
- GPREG0_PCCNOMUTCLR
- GPREG0_PCCTMR
- GPREG0_PCCTMR_16ns
- GPREG0_PCCTMR_1ms
- GPREG0_PCCTMR_1us
- GPREG0_PCCTMR_256ns
- GPREG0_PCIRLMT
- GPREG0_PCIRLMT_4
- GPREG0_PCIRLMT_5
- GPREG0_PCIRLMT_6
- GPREG0_PCIRLMT_8
- GPREG0_PHYADDR
- GPREG0_PHYADDR_1
- GPREG1_DEFAULT
- GPREG1_HALFMODEPATCH
- GPREG1_INTDLYEN_1U
- GPREG1_INTDLYEN_2U
- GPREG1_INTDLYEN_3U
- GPREG1_INTDLYEN_4U
- GPREG1_INTDLYEN_5U
- GPREG1_INTDLYEN_6U
- GPREG1_INTDLYEN_7U
- GPREG1_INTDLYUNIT_16NS
- GPREG1_INTDLYUNIT_16US
- GPREG1_INTDLYUNIT_1US
- GPREG1_INTDLYUNIT_256NS
- GPREG1_INTRDELAYENABLE
- GPREG1_INTRDELAYUNIT
- GPREG1_PCREQN
- GPREG1_RSSPATCH
- GPREG1_RXCLKOFF
- GPREN0
- GPRS_DEFAULT_MTU
- GPRS_PDP_MTU
- GPR_1
- GPR_2
- GPR_3
- GPR_4
- GPR_ACCU
- GPR_C0
- GPR_C0EN
- GPR_C1
- GPR_C1EN
- GPR_COND
- GPR_DBAC
- GPR_DWARFNUM_NAME
- GPR_IRQ
- GPR_MASK
- GPR_NOISE0
- GPR_NOISE1
- GPR_OFFSET_NAME
- GPR_SAVE
- GPR_SHIFT
- GPR_SIZE
- GPR_WRITE_PRIORITY
- GPS
- GPSCLK_A_MARK
- GPSCLK_B_MARK
- GPSCLK_C_MARK
- GPSCS
- GPSC_CMD
- GPSC_REQ_SIZE
- GPSC_RSP_SIZE
- GPSET0
- GPSIN_A_MARK
- GPSIN_B_MARK
- GPSIN_C_MARK
- GPSR
- GPSR0_0
- GPSR0_1
- GPSR0_10
- GPSR0_11
- GPSR0_12
- GPSR0_13
- GPSR0_14
- GPSR0_15
- GPSR0_16
- GPSR0_17
- GPSR0_18
- GPSR0_19
- GPSR0_2
- GPSR0_20
- GPSR0_21
- GPSR0_3
- GPSR0_4
- GPSR0_5
- GPSR0_6
- GPSR0_7
- GPSR0_8
- GPSR0_9
- GPSR1_0
- GPSR1_1
- GPSR1_10
- GPSR1_11
- GPSR1_12
- GPSR1_13
- GPSR1_14
- GPSR1_15
- GPSR1_16
- GPSR1_17
- GPSR1_18
- GPSR1_19
- GPSR1_2
- GPSR1_20
- GPSR1_21
- GPSR1_22
- GPSR1_23
- GPSR1_24
- GPSR1_25
- GPSR1_26
- GPSR1_27
- GPSR1_28
- GPSR1_29
- GPSR1_3
- GPSR1_30
- GPSR1_31
- GPSR1_4
- GPSR1_5
- GPSR1_6
- GPSR1_7
- GPSR1_8
- GPSR1_9
- GPSR2_0
- GPSR2_1
- GPSR2_10
- GPSR2_11
- GPSR2_12
- GPSR2_13
- GPSR2_14
- GPSR2_15
- GPSR2_16
- GPSR2_17
- GPSR2_18
- GPSR2_19
- GPSR2_2
- GPSR2_20
- GPSR2_21
- GPSR2_22
- GPSR2_23
- GPSR2_24
- GPSR2_25
- GPSR2_26
- GPSR2_27
- GPSR2_28
- GPSR2_29
- GPSR2_3
- GPSR2_30
- GPSR2_31
- GPSR2_4
- GPSR2_5
- GPSR2_6
- GPSR2_7
- GPSR2_8
- GPSR2_9
- GPSR3_0
- GPSR3_1
- GPSR3_10
- GPSR3_11
- GPSR3_12
- GPSR3_13
- GPSR3_14
- GPSR3_15
- GPSR3_16
- GPSR3_2
- GPSR3_3
- GPSR3_4
- GPSR3_5
- GPSR3_6
- GPSR3_7
- GPSR3_8
- GPSR3_9
- GPSR4_0
- GPSR4_1
- GPSR4_10
- GPSR4_11
- GPSR4_12
- GPSR4_13
- GPSR4_14
- GPSR4_15
- GPSR4_16
- GPSR4_17
- GPSR4_18
- GPSR4_19
- GPSR4_2
- GPSR4_20
- GPSR4_21
- GPSR4_22
- GPSR4_23
- GPSR4_24
- GPSR4_25
- GPSR4_26
- GPSR4_27
- GPSR4_28
- GPSR4_29
- GPSR4_3
- GPSR4_30
- GPSR4_31
- GPSR4_4
- GPSR4_5
- GPSR4_6
- GPSR4_7
- GPSR4_8
- GPSR4_9
- GPSR5_0
- GPSR5_1
- GPSR5_10
- GPSR5_11
- GPSR5_12
- GPSR5_13
- GPSR5_14
- GPSR5_15
- GPSR5_16
- GPSR5_17
- GPSR5_18
- GPSR5_19
- GPSR5_2
- GPSR5_20
- GPSR5_21
- GPSR5_22
- GPSR5_23
- GPSR5_24
- GPSR5_25
- GPSR5_3
- GPSR5_4
- GPSR5_5
- GPSR5_6
- GPSR5_7
- GPSR5_8
- GPSR5_9
- GPSR6_0
- GPSR6_1
- GPSR6_10
- GPSR6_11
- GPSR6_12
- GPSR6_13
- GPSR6_14
- GPSR6_15
- GPSR6_16
- GPSR6_17
- GPSR6_18
- GPSR6_19
- GPSR6_2
- GPSR6_20
- GPSR6_21
- GPSR6_22
- GPSR6_23
- GPSR6_24
- GPSR6_25
- GPSR6_26
- GPSR6_27
- GPSR6_28
- GPSR6_29
- GPSR6_3
- GPSR6_30
- GPSR6_31
- GPSR6_4
- GPSR6_5
- GPSR6_6
- GPSR6_7
- GPSR6_8
- GPSR6_9
- GPSR7_0
- GPSR7_1
- GPSR7_2
- GPSR7_3
- GPSRCS
- GPSR_OFFSET
- GPSTATE_SHIFT
- GPSTATE_TIMER_INTERVAL
- GPSTR
- GPS_CLK_B_MARK
- GPS_CLK_C_MARK
- GPS_CLK_D_MARK
- GPS_CLK_MARK
- GPS_CONTROL_REG_BASE
- GPS_CTL_HWPDN
- GPS_FUNC_EN
- GPS_HWPDN_EN
- GPS_HWPDN_SL
- GPS_IN_BUFSIZ
- GPS_MAG_B_MARK
- GPS_MAG_C_MARK
- GPS_MAG_D_MARK
- GPS_MAG_MARK
- GPS_OUT_BUFSIZ
- GPS_SIGN_B_MARK
- GPS_SIGN_C_MARK
- GPS_SIGN_D_MARK
- GPS_SIGN_MARK
- GPS_STUB_TEST
- GPS_TIMESTAMP
- GPT0_CLK_SHIFT
- GPT0_TMR0_CPT_MASK
- GPT0_TMR1_CLK_MASK
- GPT1_CLK_ENB
- GPT1_CLK_SHIFT
- GPT2_CLK_ENB
- GPT2_CLK_SHIFT
- GPT3_CLK_ENB
- GPT3_CLK_SHIFT
- GPT6_CON_MT65xx
- GPTC
- GPTE_COHERENT
- GPTE_DECODE
- GPTE_ENCODE
- GPTE_VALID
- GPTIMER_BASE
- GPTIMER_CONFIG_IRQNT
- GPTIMER_CONFIG_ISSEP
- GPTIMER_CONFIG_NTIMERS
- GPTIMER_REGS
- GPTIMER_REGS_SIZE
- GPTU_BASE
- GPTU_CLC
- GPTU_CNT
- GPTU_CON
- GPTU_ID
- GPTU_IRCR
- GPTU_IRNCR
- GPTU_IRNEN
- GPTU_MAGIC
- GPTU_RLD
- GPTU_RUN
- GPTU_SHIFT
- GPT_CFG
- GPT_CFG_GPT_LOAD_
- GPT_CFG_TIMER_EN_
- GPT_CLK_DIV1
- GPT_CLK_DIV2
- GPT_CLK_MASK
- GPT_CLK_REG
- GPT_CLK_SRC
- GPT_CLK_SRC_RTC32K
- GPT_CLK_SRC_SYS13M
- GPT_CMP_REG
- GPT_CNT
- GPT_CNT_GPT_CNT_
- GPT_CNT_REG
- GPT_CON
- GPT_CTRL_CLEAR
- GPT_CTRL_DISABLE
- GPT_CTRL_ENABLE
- GPT_CTRL_OP
- GPT_CTRL_OP_FREERUN
- GPT_CTRL_OP_ONESHOT
- GPT_CTRL_OP_REPEAT
- GPT_CTRL_REG
- GPT_ENABLE
- GPT_HEADER_REVISION_V1
- GPT_HEADER_SIGNATURE
- GPT_HZ
- GPT_IRQ_ACK
- GPT_IRQ_ACK_REG
- GPT_IRQ_ENABLE
- GPT_IRQ_EN_REG
- GPT_MASK
- GPT_MBR_HYBRID
- GPT_MBR_PROTECTIVE
- GPT_MSCALE_MASK
- GPT_NSCALE_MASK
- GPT_NSCALE_SHIFT
- GPT_PRIMARY_PARTITION_TABLE_LBA
- GPT_TYPE_IMX1
- GPT_TYPE_IMX21
- GPT_TYPE_IMX31
- GPT_TYPE_IMX6DL
- GPT_VAL
- GPTimer
- GPU
- GPUCC_CXO_CLK
- GPUCC_GPU_CC_CX_BCR
- GPUCC_GPU_CC_GMU_BCR
- GPUCC_GPU_CC_XO_BCR
- GPUCORE_1619
- GPUMMU_PAGE_SIZE
- GPUMMU_VA_RANGE
- GPUMMU_VA_START
- GPUPLL0
- GPUPLL0_OUT_EVEN
- GPU_ACLK
- GPU_AHB_CLK
- GPU_ALIGN_UP
- GPU_AON_BCR
- GPU_AON_ISENSE_CLK
- GPU_AS_PRESENT
- GPU_BCR
- GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK
- GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT
- GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK
- GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT
- GPU_BIST_CONTROL__RESERVED_MASK
- GPU_BIST_CONTROL__RESERVED__SHIFT
- GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK
- GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT
- GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK
- GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT
- GPU_CAC_AVRG_CNTL
- GPU_CC_CXO_CLK
- GPU_CC_CX_GMU_CLK
- GPU_CC_GMU_CLK_SRC
- GPU_CC_PLL1
- GPU_CMD
- GPU_CMD_BUF_SIZE
- GPU_CMD_CLEAN_CACHES
- GPU_CMD_CLEAN_INV_CACHES
- GPU_CMD_PERFCNT_CLEAR
- GPU_CMD_PERFCNT_SAMPLE
- GPU_CMD_SOFT_RESET
- GPU_COHERENCY_FEATURES
- GPU_CONFIGREG_CACHE
- GPU_CONFIGREG_DIDT_IND
- GPU_CONFIGREG_GC_CAC_IND
- GPU_CONFIGREG_MAX
- GPU_CONFIGREG_MMR
- GPU_CONFIGREG_SMC_IND
- GPU_CORE_FEATURES
- GPU_COUNTER_CLK
- GPU_CX_BCR
- GPU_CX_GDSC
- GPU_DIE_TEMPERATURE_THROTTLING_BIT
- GPU_DIE_TEMPERATURE_THROTTLING_MASK
- GPU_DRIVER_INFO_VERSION
- GPU_ENUM_ID1
- GPU_FAULT_ADDRESS_HI
- GPU_FAULT_ADDRESS_LO
- GPU_FAULT_STATUS
- GPU_FB_START
- GPU_GARLIC_FLUSH_DONE_IND__CP0_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP0__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP1_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP1__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP2_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP2__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP3_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP3__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP4_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP4__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP5_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP5__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP6_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP6__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP7_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP7__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP8_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP8__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__CP9_MASK
- GPU_GARLIC_FLUSH_DONE_IND__CP9__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__SDMA0_MASK
- GPU_GARLIC_FLUSH_DONE_IND__SDMA0__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__SDMA1_MASK
- GPU_GARLIC_FLUSH_DONE_IND__SDMA1__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__SDMA2_MASK
- GPU_GARLIC_FLUSH_DONE_IND__SDMA2__SHIFT
- GPU_GARLIC_FLUSH_DONE_IND__SDMA3_MASK
- GPU_GARLIC_FLUSH_DONE_IND__SDMA3__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP0_MASK
- GPU_GARLIC_FLUSH_DONE__CP0__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP1_MASK
- GPU_GARLIC_FLUSH_DONE__CP1__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP2_MASK
- GPU_GARLIC_FLUSH_DONE__CP2__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP3_MASK
- GPU_GARLIC_FLUSH_DONE__CP3__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP4_MASK
- GPU_GARLIC_FLUSH_DONE__CP4__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP5_MASK
- GPU_GARLIC_FLUSH_DONE__CP5__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP6_MASK
- GPU_GARLIC_FLUSH_DONE__CP6__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP7_MASK
- GPU_GARLIC_FLUSH_DONE__CP7__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP8_MASK
- GPU_GARLIC_FLUSH_DONE__CP8__SHIFT
- GPU_GARLIC_FLUSH_DONE__CP9_MASK
- GPU_GARLIC_FLUSH_DONE__CP9__SHIFT
- GPU_GARLIC_FLUSH_DONE__SDMA0_MASK
- GPU_GARLIC_FLUSH_DONE__SDMA0__SHIFT
- GPU_GARLIC_FLUSH_DONE__SDMA1_MASK
- GPU_GARLIC_FLUSH_DONE__SDMA1__SHIFT
- GPU_GARLIC_FLUSH_DONE__SDMA2_MASK
- GPU_GARLIC_FLUSH_DONE__SDMA2__SHIFT
- GPU_GARLIC_FLUSH_DONE__SDMA3_MASK
- GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP0_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP0__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP1_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP1__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP2_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP2__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP3_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP3__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP4_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP4__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP5_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP5__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP6_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP6__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP7_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP7__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP8_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP8__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__CP9_MASK
- GPU_GARLIC_FLUSH_REQ_IND__CP9__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__SDMA0_MASK
- GPU_GARLIC_FLUSH_REQ_IND__SDMA0__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__SDMA1_MASK
- GPU_GARLIC_FLUSH_REQ_IND__SDMA1__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__SDMA2_MASK
- GPU_GARLIC_FLUSH_REQ_IND__SDMA2__SHIFT
- GPU_GARLIC_FLUSH_REQ_IND__SDMA3_MASK
- GPU_GARLIC_FLUSH_REQ_IND__SDMA3__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP0_MASK
- GPU_GARLIC_FLUSH_REQ__CP0__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP1_MASK
- GPU_GARLIC_FLUSH_REQ__CP1__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP2_MASK
- GPU_GARLIC_FLUSH_REQ__CP2__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP3_MASK
- GPU_GARLIC_FLUSH_REQ__CP3__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP4_MASK
- GPU_GARLIC_FLUSH_REQ__CP4__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP5_MASK
- GPU_GARLIC_FLUSH_REQ__CP5__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP6_MASK
- GPU_GARLIC_FLUSH_REQ__CP6__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP7_MASK
- GPU_GARLIC_FLUSH_REQ__CP7__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP8_MASK
- GPU_GARLIC_FLUSH_REQ__CP8__SHIFT
- GPU_GARLIC_FLUSH_REQ__CP9_MASK
- GPU_GARLIC_FLUSH_REQ__CP9__SHIFT
- GPU_GARLIC_FLUSH_REQ__SDMA0_MASK
- GPU_GARLIC_FLUSH_REQ__SDMA0__SHIFT
- GPU_GARLIC_FLUSH_REQ__SDMA1_MASK
- GPU_GARLIC_FLUSH_REQ__SDMA1__SHIFT
- GPU_GARLIC_FLUSH_REQ__SDMA2_MASK
- GPU_GARLIC_FLUSH_REQ__SDMA2__SHIFT
- GPU_GARLIC_FLUSH_REQ__SDMA3_MASK
- GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT
- GPU_GDSC
- GPU_GX_BCR
- GPU_GX_GDSC
- GPU_GX_GFX3D_CLK
- GPU_GX_RBBMTIMER_CLK
- GPU_HDP_FLUSH_DONE
- GPU_HDP_FLUSH_DONE_IND__CP0_MASK
- GPU_HDP_FLUSH_DONE_IND__CP0__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP1_MASK
- GPU_HDP_FLUSH_DONE_IND__CP1__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP2_MASK
- GPU_HDP_FLUSH_DONE_IND__CP2__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP3_MASK
- GPU_HDP_FLUSH_DONE_IND__CP3__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP4_MASK
- GPU_HDP_FLUSH_DONE_IND__CP4__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP5_MASK
- GPU_HDP_FLUSH_DONE_IND__CP5__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP6_MASK
- GPU_HDP_FLUSH_DONE_IND__CP6__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP7_MASK
- GPU_HDP_FLUSH_DONE_IND__CP7__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP8_MASK
- GPU_HDP_FLUSH_DONE_IND__CP8__SHIFT
- GPU_HDP_FLUSH_DONE_IND__CP9_MASK
- GPU_HDP_FLUSH_DONE_IND__CP9__SHIFT
- GPU_HDP_FLUSH_DONE_IND__SDMA0_MASK
- GPU_HDP_FLUSH_DONE_IND__SDMA0__SHIFT
- GPU_HDP_FLUSH_DONE_IND__SDMA1_MASK
- GPU_HDP_FLUSH_DONE_IND__SDMA1__SHIFT
- GPU_HDP_FLUSH_DONE__CP0_MASK
- GPU_HDP_FLUSH_DONE__CP0__MASK
- GPU_HDP_FLUSH_DONE__CP0__SHIFT
- GPU_HDP_FLUSH_DONE__CP1_MASK
- GPU_HDP_FLUSH_DONE__CP1__MASK
- GPU_HDP_FLUSH_DONE__CP1__SHIFT
- GPU_HDP_FLUSH_DONE__CP2_MASK
- GPU_HDP_FLUSH_DONE__CP2__MASK
- GPU_HDP_FLUSH_DONE__CP2__SHIFT
- GPU_HDP_FLUSH_DONE__CP3_MASK
- GPU_HDP_FLUSH_DONE__CP3__MASK
- GPU_HDP_FLUSH_DONE__CP3__SHIFT
- GPU_HDP_FLUSH_DONE__CP4_MASK
- GPU_HDP_FLUSH_DONE__CP4__MASK
- GPU_HDP_FLUSH_DONE__CP4__SHIFT
- GPU_HDP_FLUSH_DONE__CP5_MASK
- GPU_HDP_FLUSH_DONE__CP5__MASK
- GPU_HDP_FLUSH_DONE__CP5__SHIFT
- GPU_HDP_FLUSH_DONE__CP6_MASK
- GPU_HDP_FLUSH_DONE__CP6__MASK
- GPU_HDP_FLUSH_DONE__CP6__SHIFT
- GPU_HDP_FLUSH_DONE__CP7_MASK
- GPU_HDP_FLUSH_DONE__CP7__MASK
- GPU_HDP_FLUSH_DONE__CP7__SHIFT
- GPU_HDP_FLUSH_DONE__CP8_MASK
- GPU_HDP_FLUSH_DONE__CP8__MASK
- GPU_HDP_FLUSH_DONE__CP8__SHIFT
- GPU_HDP_FLUSH_DONE__CP9_MASK
- GPU_HDP_FLUSH_DONE__CP9__MASK
- GPU_HDP_FLUSH_DONE__CP9__SHIFT
- GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK
- GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK
- GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK
- GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK
- GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK
- GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK
- GPU_HDP_FLUSH_DONE__SDMA0_MASK
- GPU_HDP_FLUSH_DONE__SDMA0__MASK
- GPU_HDP_FLUSH_DONE__SDMA0__SHIFT
- GPU_HDP_FLUSH_DONE__SDMA1_MASK
- GPU_HDP_FLUSH_DONE__SDMA1__MASK
- GPU_HDP_FLUSH_DONE__SDMA1__SHIFT
- GPU_HDP_FLUSH_REQ
- GPU_HDP_FLUSH_REQ_IND__CP0_MASK
- GPU_HDP_FLUSH_REQ_IND__CP0__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP1_MASK
- GPU_HDP_FLUSH_REQ_IND__CP1__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP2_MASK
- GPU_HDP_FLUSH_REQ_IND__CP2__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP3_MASK
- GPU_HDP_FLUSH_REQ_IND__CP3__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP4_MASK
- GPU_HDP_FLUSH_REQ_IND__CP4__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP5_MASK
- GPU_HDP_FLUSH_REQ_IND__CP5__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP6_MASK
- GPU_HDP_FLUSH_REQ_IND__CP6__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP7_MASK
- GPU_HDP_FLUSH_REQ_IND__CP7__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP8_MASK
- GPU_HDP_FLUSH_REQ_IND__CP8__SHIFT
- GPU_HDP_FLUSH_REQ_IND__CP9_MASK
- GPU_HDP_FLUSH_REQ_IND__CP9__SHIFT
- GPU_HDP_FLUSH_REQ_IND__SDMA0_MASK
- GPU_HDP_FLUSH_REQ_IND__SDMA0__SHIFT
- GPU_HDP_FLUSH_REQ_IND__SDMA1_MASK
- GPU_HDP_FLUSH_REQ_IND__SDMA1__SHIFT
- GPU_HDP_FLUSH_REQ__CP0_MASK
- GPU_HDP_FLUSH_REQ__CP0__MASK
- GPU_HDP_FLUSH_REQ__CP0__SHIFT
- GPU_HDP_FLUSH_REQ__CP1_MASK
- GPU_HDP_FLUSH_REQ__CP1__MASK
- GPU_HDP_FLUSH_REQ__CP1__SHIFT
- GPU_HDP_FLUSH_REQ__CP2_MASK
- GPU_HDP_FLUSH_REQ__CP2__MASK
- GPU_HDP_FLUSH_REQ__CP2__SHIFT
- GPU_HDP_FLUSH_REQ__CP3_MASK
- GPU_HDP_FLUSH_REQ__CP3__MASK
- GPU_HDP_FLUSH_REQ__CP3__SHIFT
- GPU_HDP_FLUSH_REQ__CP4_MASK
- GPU_HDP_FLUSH_REQ__CP4__MASK
- GPU_HDP_FLUSH_REQ__CP4__SHIFT
- GPU_HDP_FLUSH_REQ__CP5_MASK
- GPU_HDP_FLUSH_REQ__CP5__MASK
- GPU_HDP_FLUSH_REQ__CP5__SHIFT
- GPU_HDP_FLUSH_REQ__CP6_MASK
- GPU_HDP_FLUSH_REQ__CP6__MASK
- GPU_HDP_FLUSH_REQ__CP6__SHIFT
- GPU_HDP_FLUSH_REQ__CP7_MASK
- GPU_HDP_FLUSH_REQ__CP7__MASK
- GPU_HDP_FLUSH_REQ__CP7__SHIFT
- GPU_HDP_FLUSH_REQ__CP8_MASK
- GPU_HDP_FLUSH_REQ__CP8__MASK
- GPU_HDP_FLUSH_REQ__CP8__SHIFT
- GPU_HDP_FLUSH_REQ__CP9_MASK
- GPU_HDP_FLUSH_REQ__CP9__MASK
- GPU_HDP_FLUSH_REQ__CP9__SHIFT
- GPU_HDP_FLUSH_REQ__SDMA0_MASK
- GPU_HDP_FLUSH_REQ__SDMA0__MASK
- GPU_HDP_FLUSH_REQ__SDMA0__SHIFT
- GPU_HDP_FLUSH_REQ__SDMA1_MASK
- GPU_HDP_FLUSH_REQ__SDMA1__MASK
- GPU_HDP_FLUSH_REQ__SDMA1__SHIFT
- GPU_ID
- GPU_INTR_STATUS_FLIP_0
- GPU_INTR_STATUS_FLIP_1
- GPU_INTR_STATUS_QUEUE_0
- GPU_INTR_STATUS_QUEUE_1
- GPU_INTR_STATUS_VSYNC_0
- GPU_INTR_STATUS_VSYNC_1
- GPU_INT_CLEAR
- GPU_INT_MASK
- GPU_INT_RAWSTAT
- GPU_INT_STAT
- GPU_IOIF
- GPU_IRQ_CLEAN_CACHES_COMPLETED
- GPU_IRQ_FAULT
- GPU_IRQ_MASK_ALL
- GPU_IRQ_MASK_ERROR
- GPU_IRQ_MULTIPLE_FAULT
- GPU_IRQ_PERFCNT_SAMPLE_COMPLETED
- GPU_IRQ_POWER_CHANGED
- GPU_IRQ_POWER_CHANGED_ALL
- GPU_IRQ_RESET_COMPLETED
- GPU_ISENSE_BCR
- GPU_JM_CONFIG
- GPU_JS_FEATURES
- GPU_JS_PRESENT
- GPU_K
- GPU_L2_FEATURES
- GPU_L2_MMU_CONFIG
- GPU_L2_PRESENT_HI
- GPU_L2_PRESENT_LO
- GPU_LATEST_FLUSH_ID
- GPU_MAX_LINE_LENGTH
- GPU_MEM_FEATURES
- GPU_MEM_START
- GPU_MMU_FEATURES
- GPU_MODEL
- GPU_PAS_ID
- GPU_PERFCNT_BASE_HI
- GPU_PERFCNT_BASE_LO
- GPU_PERFCNT_CFG
- GPU_PERFCNT_CFG_AS
- GPU_PERFCNT_CFG_MODE
- GPU_PERFCNT_CFG_MODE_MANUAL
- GPU_PERFCNT_CFG_MODE_OFF
- GPU_PERFCNT_CFG_MODE_TILE
- GPU_PERFCNT_CFG_SETSEL
- GPU_PLL
- GPU_POWER__DGPU_POWER_MASK
- GPU_POWER__DGPU_POWER__SHIFT
- GPU_POWER__IGPU_POWER_MASK
- GPU_POWER__IGPU_POWER__SHIFT
- GPU_PP0_REF
- GPU_PP1_REF
- GPU_PRFCNT_JM_EN
- GPU_PRFCNT_MMU_L2_EN
- GPU_PRFCNT_SHADER_EN
- GPU_PRFCNT_TILER_EN
- GPU_PROCESS_CORNERS
- GPU_R
- GPU_REF
- GPU_REV
- GPU_REV_EXT
- GPU_RG_CNTRL
- GPU_SHADER_CONFIG
- GPU_SHADER_PRESENT_HI
- GPU_SHADER_PRESENT_LO
- GPU_STACK_PRESENT_HI
- GPU_STACK_PRESENT_LO
- GPU_STATUS
- GPU_STATUS_PRFCNT_ACTIVE
- GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK
- GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT
- GPU_TDP_LIMIT__Reserved_MASK
- GPU_TDP_LIMIT__Reserved__SHIFT
- GPU_TEXTURE_FEATURES
- GPU_THREAD_FEATURES
- GPU_THREAD_MAX_BARRIER_SIZE
- GPU_THREAD_MAX_THREADS
- GPU_THREAD_MAX_WORKGROUP_SIZE
- GPU_THREAD_TLS_ALLOC
- GPU_TILER_CONFIG
- GPU_TILER_FEATURES
- GPU_TILER_PRESENT_HI
- GPU_TILER_PRESENT_LO
- GPU_VPU_PDN_REQ
- GPU_VPU_PUP_REQ
- GPVNDCTL
- GPWRDN
- GPWRDN_ADP_INT
- GPWRDN_BSESSVLD
- GPWRDN_CONNECT_DET
- GPWRDN_CONNECT_DET_MSK
- GPWRDN_DISCONN_DET
- GPWRDN_DISCONN_DET_MSK
- GPWRDN_DIS_VBUS
- GPWRDN_IDSTS
- GPWRDN_LINESTATE_MASK
- GPWRDN_LINESTATE_SHIFT
- GPWRDN_LNSTSCHG
- GPWRDN_LNSTSCHG_MSK
- GPWRDN_MULT_VAL_ID_BC_MASK
- GPWRDN_MULT_VAL_ID_BC_SHIFT
- GPWRDN_PMUACTV
- GPWRDN_PMUINTSEL
- GPWRDN_PWRDNCLMP
- GPWRDN_PWRDNRSTN
- GPWRDN_PWRDNSWTCH
- GPWRDN_RESTORE
- GPWRDN_RST_DET
- GPWRDN_RST_DET_MSK
- GPWRDN_SRP_DET
- GPWRDN_SRP_DET_MSK
- GPWRDN_STS_CHGINT
- GPWRDN_STS_CHGINT_MSK
- GPY_MMD_MASK
- GPY_MMD_SHIFT
- GPY_REG_MASK
- GP_ALL
- GP_ASSIGN_LAST
- GP_BASE_OFFSET
- GP_BLT_MODE
- GP_BLT_STATUS
- GP_BLT_STATUS_BLT_BUSY
- GP_BLT_STATUS_BLT_PENDING
- GP_BLT_STATUS_CE
- GP_BLT_STATUS_PB
- GP_CH3_HSRC
- GP_CH3_MODE_STR
- GP_CH3_OFFSET
- GP_CH3_WIDHI
- GP_CHIP_ID
- GP_CLIENTSEL
- GP_CMD_BOT
- GP_CMD_READ
- GP_CMD_TOP
- GP_CMD_WRITE
- GP_COUNT_CONTROL_INC
- GP_COUNT_CONTROL_NONE
- GP_COUNT_CONTROL_RESERVED
- GP_COUNT_CONTROL_RESET
- GP_DEVICE
- GP_DIR_0
- GP_DIR_1
- GP_DIR_2
- GP_DIR_3
- GP_DIR_4
- GP_DIR_5
- GP_DIR_6
- GP_DIR_7
- GP_DIR_8
- GP_DIR_9
- GP_DRIVE0
- GP_DST_OFFSET
- GP_ENTER
- GP_EXIT
- GP_GPIO_PUP_PDN_CNTRL_REG0
- GP_HST_SRC
- GP_IDLE
- GP_INDT
- GP_INOUTSEL
- GP_INPUT
- GP_INT
- GP_INT_AK
- GP_INT_CNTRL
- GP_INT_EN
- GP_IO
- GP_IO_0
- GP_IO_1
- GP_IO_2
- GP_IO_3
- GP_IO_4
- GP_IO_5
- GP_IO_6
- GP_IO_7
- GP_IO_8
- GP_IO_9
- GP_IO_SEL
- GP_IO_SEL2
- GP_IRQ0
- GP_IRQ2
- GP_IRQ5
- GP_LUT_DATA
- GP_LUT_INDEX
- GP_LVL
- GP_LVL2
- GP_OUTPUT0
- GP_OUTPUT1
- GP_OUTPUT2
- GP_OUTPUT3
- GP_PARTIITON_MAP_TYPE_1
- GP_PARTITION_MAP_TYPE_2
- GP_PARTITION_MAP_TYPE_UNDEF
- GP_PASSED
- GP_PAT_COLOR_0
- GP_PAT_COLOR_1
- GP_PAT_COLOR_2
- GP_PAT_COLOR_3
- GP_PAT_COLOR_4
- GP_PAT_COLOR_5
- GP_PAT_DATA_0
- GP_PAT_DATA_1
- GP_RASTER_MODE
- GP_REG
- GP_REGS_SIZE
- GP_REG_BYTES
- GP_REG_COUNT
- GP_REPLAY
- GP_RWBAR
- GP_RWREG1
- GP_RWREG1_ULPI_REFCLK_DISABLE
- GP_SRC_COLOR_BG
- GP_SRC_COLOR_FG
- GP_SRC_OFFSET
- GP_STATUS_100M
- GP_STATUS_10G_CX4
- GP_STATUS_10G_HIG
- GP_STATUS_10G_KR
- GP_STATUS_10G_KX4
- GP_STATUS_10G_SFI
- GP_STATUS_10G_XFI
- GP_STATUS_10M
- GP_STATUS_1G
- GP_STATUS_1G_KX
- GP_STATUS_20G_DXGXS
- GP_STATUS_20G_KR2
- GP_STATUS_2_5G
- GP_STATUS_5G
- GP_STATUS_6G
- GP_STATUS_PAUSE_RSOLUTION_RXSIDE
- GP_STATUS_PAUSE_RSOLUTION_TXSIDE
- GP_STATUS_SPEED_MASK
- GP_STRIDE
- GP_VECTOR
- GP_VECTOR_MODE
- GP_WID_HEIGHT
- GQR_LD_SCALE_MASK
- GQR_LD_SCALE_SHIFT
- GQR_LD_TYPE_MASK
- GQR_LD_TYPE_SHIFT
- GQR_QUANTIZE_FLOAT
- GQR_QUANTIZE_S16
- GQR_QUANTIZE_S8
- GQR_QUANTIZE_U16
- GQR_QUANTIZE_U8
- GQR_ST_SCALE_MASK
- GQR_ST_SCALE_SHIFT
- GQR_ST_TYPE_MASK
- GQR_ST_TYPE_SHIFT
- GQSPI_BAUD_DIV_MAX
- GQSPI_BAUD_DIV_SHIFT
- GQSPI_CFG_BAUD_RATE_DIV_MASK
- GQSPI_CFG_BAUD_RATE_DIV_SHIFT
- GQSPI_CFG_CLK_PHA_MASK
- GQSPI_CFG_CLK_POL_MASK
- GQSPI_CFG_ENDIAN_MASK
- GQSPI_CFG_EN_POLL_TO_MASK
- GQSPI_CFG_GEN_FIFO_START_MODE_MASK
- GQSPI_CFG_MODE_EN_DMA_MASK
- GQSPI_CFG_MODE_EN_MASK
- GQSPI_CFG_START_GEN_FIFO_MASK
- GQSPI_CFG_WP_HOLD_MASK
- GQSPI_CONFIG_OFST
- GQSPI_DEFAULT_NUM_CS
- GQSPI_DMA_UNALIGN
- GQSPI_EN_MASK
- GQSPI_EN_OFST
- GQSPI_FIFO_CTRL_OFST
- GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK
- GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK
- GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK
- GQSPI_GENFIFO_BUS_BOTH
- GQSPI_GENFIFO_BUS_LOWER
- GQSPI_GENFIFO_BUS_MASK
- GQSPI_GENFIFO_BUS_UPPER
- GQSPI_GENFIFO_CS_HOLD
- GQSPI_GENFIFO_CS_LOWER
- GQSPI_GENFIFO_CS_SETUP
- GQSPI_GENFIFO_CS_UPPER
- GQSPI_GENFIFO_DATA_XFER
- GQSPI_GENFIFO_EXP
- GQSPI_GENFIFO_EXP_START
- GQSPI_GENFIFO_IMM_DATA_MASK
- GQSPI_GENFIFO_MODE_DUALSPI
- GQSPI_GENFIFO_MODE_MASK
- GQSPI_GENFIFO_MODE_QUADSPI
- GQSPI_GENFIFO_MODE_SPI
- GQSPI_GENFIFO_POLL
- GQSPI_GENFIFO_RX
- GQSPI_GENFIFO_STRIPE
- GQSPI_GENFIFO_TX
- GQSPI_GEN_FIFO_OFST
- GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL
- GQSPI_GF_THRESHOLD_OFST
- GQSPI_IDR_ALL_MASK
- GQSPI_IDR_OFST
- GQSPI_IER_GENFIFOEMPTY_MASK
- GQSPI_IER_OFST
- GQSPI_IER_POLL_TIME_EXPIRE_MASK
- GQSPI_IER_RXEMPTY_MASK
- GQSPI_IER_RXNEMPTY_MASK
- GQSPI_IER_TXEMPTY_MASK
- GQSPI_IER_TXNOT_FULL_MASK
- GQSPI_IMASK_OFST
- GQSPI_IRQ_MASK
- GQSPI_ISR_GENFIFOEMPTY_MASK
- GQSPI_ISR_GENFIFOFULL_MASK
- GQSPI_ISR_GENFIFONOT_FULL_MASK
- GQSPI_ISR_IDR_MASK
- GQSPI_ISR_OFST
- GQSPI_ISR_POLL_TIME_EXPIRE_MASK
- GQSPI_ISR_RXEMPTY_MASK
- GQSPI_ISR_RXFULL_MASK
- GQSPI_ISR_RXNEMPTY_MASK
- GQSPI_ISR_TXEMPTY_MASK
- GQSPI_ISR_TXFULL_MASK
- GQSPI_ISR_TXNOT_FULL_MASK
- GQSPI_ISR_WR_TO_CLR_MASK
- GQSPI_LPBK_DLY_ADJ_OFST
- GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
- GQSPI_MODE_DMA
- GQSPI_MODE_IO
- GQSPI_QSPIDMA_DST_ADDR_MSB_OFST
- GQSPI_QSPIDMA_DST_ADDR_OFST
- GQSPI_QSPIDMA_DST_CTRL_OFST
- GQSPI_QSPIDMA_DST_CTRL_RESET_VAL
- GQSPI_QSPIDMA_DST_INTR_ALL_MASK
- GQSPI_QSPIDMA_DST_I_DIS_OFST
- GQSPI_QSPIDMA_DST_I_EN_DONE_MASK
- GQSPI_QSPIDMA_DST_I_EN_OFST
- GQSPI_QSPIDMA_DST_I_MASK_OFST
- GQSPI_QSPIDMA_DST_I_STS_DONE_MASK
- GQSPI_QSPIDMA_DST_I_STS_OFST
- GQSPI_QSPIDMA_DST_SIZE_OFST
- GQSPI_QSPIDMA_DST_STS_OFST
- GQSPI_QSPIDMA_DST_STS_WTC
- GQSPI_RXD_OFST
- GQSPI_RX_FIFO_FILL
- GQSPI_RX_FIFO_THRESHOLD
- GQSPI_RX_THRESHOLD_OFST
- GQSPI_SELECT_FLASH_BUS_BOTH
- GQSPI_SELECT_FLASH_BUS_LOWER
- GQSPI_SELECT_FLASH_BUS_UPPER
- GQSPI_SELECT_FLASH_CS_BOTH
- GQSPI_SELECT_FLASH_CS_LOWER
- GQSPI_SELECT_FLASH_CS_UPPER
- GQSPI_SELECT_MODE_DUALSPI
- GQSPI_SELECT_MODE_QUADSPI
- GQSPI_SELECT_MODE_SPI
- GQSPI_SEL_MASK
- GQSPI_SEL_OFST
- GQSPI_TXD_DEPTH
- GQSPI_TXD_OFST
- GQSPI_TX_FIFO_FILL
- GQSPI_TX_FIFO_THRESHOLD_RESET_VAL
- GQSPI_TX_THRESHOLD_OFST
- GQ_CHIP_ID
- GR00
- GR01
- GR02
- GR03
- GR04
- GR05
- GR06
- GR07
- GR08
- GR10
- GR11
- GR18_A0000_FLUSH_EN
- GR18_DRIVER_SWITCH_EN
- GR18_HK_APM_CHANGE
- GR18_HK_DISP_SWITCH
- GR18_HK_LFP_STRETCH
- GR18_HK_MULTIPLE
- GR18_HK_NONE
- GR18_HK_PFIT
- GR18_HK_POPUP_DISABLED
- GR18_HK_POPUP_ENABLED
- GR18_HK_TOGGLE_DISP
- GR18_HOTKEY_MASK
- GR18_SMM_EN
- GR18_USER_INT_EN
- GR20
- GR21
- GR22
- GR2D_DSTA_BASE_ADDR
- GR2D_DSTA_BASE_ADDR_SB
- GR2D_DSTB_BASE_ADDR
- GR2D_DSTB_BASE_ADDR_SB
- GR2D_DSTC_BASE_ADDR
- GR2D_NUM_REGS
- GR2D_PAT_BASE_ADDR
- GR2D_SRCA_BASE_ADDR
- GR2D_SRCB_BASE_ADDR
- GR2D_SRC_BASE_ADDR_SB
- GR2D_UA_BASE_ADDR
- GR2D_UA_BASE_ADDR_SB
- GR2D_VA_BASE_ADDR
- GR2D_VA_BASE_ADDR_SB
- GR3D_DW_MEMORY_OUTPUT_ADDRESS
- GR3D_GLOBAL_SAMP01SURFADDR
- GR3D_GLOBAL_SAMP23SURFADDR
- GR3D_GLOBAL_SPILLSURFADDR
- GR3D_GLOBAL_SURFADDR
- GR3D_GLOBAL_SURFOVERADDR
- GR3D_IDX_ATTRIBUTE
- GR3D_IDX_INDEX_BASE
- GR3D_NUM_REGS
- GR3D_QR_CTAG_ADDR
- GR3D_QR_CZ_ADDR
- GR3D_QR_ZTAG_ADDR
- GR3D_TEX_TEX_ADDR
- GRA00__GRPH_SET_RESET0_MASK
- GRA00__GRPH_SET_RESET0__SHIFT
- GRA00__GRPH_SET_RESET1_MASK
- GRA00__GRPH_SET_RESET1__SHIFT
- GRA00__GRPH_SET_RESET2_MASK
- GRA00__GRPH_SET_RESET2__SHIFT
- GRA00__GRPH_SET_RESET3_MASK
- GRA00__GRPH_SET_RESET3__SHIFT
- GRA01__GRPH_SET_RESET_ENA0_MASK
- GRA01__GRPH_SET_RESET_ENA0__SHIFT
- GRA01__GRPH_SET_RESET_ENA1_MASK
- GRA01__GRPH_SET_RESET_ENA1__SHIFT
- GRA01__GRPH_SET_RESET_ENA2_MASK
- GRA01__GRPH_SET_RESET_ENA2__SHIFT
- GRA01__GRPH_SET_RESET_ENA3_MASK
- GRA01__GRPH_SET_RESET_ENA3__SHIFT
- GRA02__GRPH_CCOMP_MASK
- GRA02__GRPH_CCOMP__SHIFT
- GRA03__GRPH_FN_SEL_MASK
- GRA03__GRPH_FN_SEL__SHIFT
- GRA03__GRPH_ROTATE_MASK
- GRA03__GRPH_ROTATE__SHIFT
- GRA04__GRPH_RMAP_MASK
- GRA04__GRPH_RMAP__SHIFT
- GRA05__CGA_ODDEVEN_MASK
- GRA05__CGA_ODDEVEN__SHIFT
- GRA05__GRPH_OES_MASK
- GRA05__GRPH_OES__SHIFT
- GRA05__GRPH_PACK_MASK
- GRA05__GRPH_PACK__SHIFT
- GRA05__GRPH_READ1_MASK
- GRA05__GRPH_READ1__SHIFT
- GRA05__GRPH_WRITE_MODE_MASK
- GRA05__GRPH_WRITE_MODE__SHIFT
- GRA06
- GRA06__GRPH_ADRSEL_MASK
- GRA06__GRPH_ADRSEL__SHIFT
- GRA06__GRPH_GRAPHICS_MASK
- GRA06__GRPH_GRAPHICS__SHIFT
- GRA06__GRPH_ODDEVEN_MASK
- GRA06__GRPH_ODDEVEN__SHIFT
- GRA07__GRPH_XCARE0_MASK
- GRA07__GRPH_XCARE0__SHIFT
- GRA07__GRPH_XCARE1_MASK
- GRA07__GRPH_XCARE1__SHIFT
- GRA07__GRPH_XCARE2_MASK
- GRA07__GRPH_XCARE2__SHIFT
- GRA07__GRPH_XCARE3_MASK
- GRA07__GRPH_XCARE3__SHIFT
- GRA08__GRPH_BMSK_MASK
- GRA08__GRPH_BMSK__SHIFT
- GRABSTATE
- GRAB_ACTIVE
- GRAB_BITS
- GRAB_DONE
- GRAB_IDLE
- GRACEFUL_RESET_BIT1
- GRACEFUL_STOP_ACKNOWLEDGE_RX
- GRACE_START_ENV_PREFIX
- GRACKLE_CFA
- GRACKLE_DOZE
- GRACKLE_NAP
- GRACKLE_PICR1_LOOPSNOOP
- GRACKLE_PICR1_STG
- GRACKLE_PM
- GRACKLE_SLEEP
- GRADIENT_FILL
- GRAF_MAP
- GRAM_ADDR_HORIZ_SET
- GRAM_ADDR_VERT_SET
- GRAM_READ_WRITE
- GRANTS_PER_INDIRECT_FRAME
- GRANTS_PER_PSEG
- GRANT_INVALID_REF
- GRANT_TABLE_PHYSADDR
- GRANULEROUNDDOWN
- GRANULEROUNDUP
- GRAPHICS
- GRAPHICS_CSC_ADJUST_TYPE_BYPASS
- GRAPHICS_CSC_ADJUST_TYPE_HW
- GRAPHICS_CSC_ADJUST_TYPE_SW
- GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS
- GRAPHICS_GAMUT_ADJUST_TYPE_HW
- GRAPHICS_GAMUT_ADJUST_TYPE_SW
- GRAPHICS_MODE
- GRAPHICS_OBJECT_CAP_I2C
- GRAPHICS_OBJECT_CAP_TABLE_ID
- GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID
- GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID
- GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID
- GRAPHIC_FIFO
- GRAPHIC_FIFO_MASK
- GRAPHIRE
- GRAPHIRE_BT
- GRAPH_ADDR
- GRAPH_FILTER_FUNCTION
- GRAPH_FILTER_NOTRACE
- GRAPH_INSN_OFFSET
- GRAPH_MAX_FUNC_TEST
- GRAPH_OBJECT_ENUM_ID1
- GRAPH_OBJECT_ENUM_ID2
- GRAPH_OBJECT_ENUM_ID3
- GRAPH_OBJECT_ENUM_ID4
- GRAPH_OBJECT_ENUM_ID5
- GRAPH_OBJECT_ENUM_ID6
- GRAPH_OBJECT_ENUM_ID7
- GRAPH_OBJECT_TYPE_CONNECTOR
- GRAPH_OBJECT_TYPE_DISPLAY_PATH
- GRAPH_OBJECT_TYPE_ENCODER
- GRAPH_OBJECT_TYPE_GENERIC
- GRAPH_OBJECT_TYPE_GPU
- GRAPH_OBJECT_TYPE_NONE
- GRAPH_OBJECT_TYPE_ROUTER
- GRAPH_TRACER_FLAGS
- GRAS_RASPERF_16X16_TILES
- GRAS_RASPERF_4X4_TILES
- GRAS_RASPERF_8X8_TILES
- GRAS_RASPERF_STALL_CYCLES_BY_RB
- GRAS_RASPERF_STALL_CYCLES_BY_VSC
- GRAS_RASPERF_STARVE_CYCLES_BY_TSE
- GRAS_RASPERF_WORKING_CYCLES
- GRAS_TSEPERF_CLIPPED_PRIM
- GRAS_TSEPERF_FACENESS_CULLED_PRIM
- GRAS_TSEPERF_INPUT_NULL_PRIM
- GRAS_TSEPERF_INPUT_PRIM
- GRAS_TSEPERF_NEW_PRIM
- GRAS_TSEPERF_OUTPUT_NULL_PRIM
- GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM
- GRAS_TSEPERF_PC_STARVE
- GRAS_TSEPERF_POST_CLIP_PRIM
- GRAS_TSEPERF_PRE_CLIP_PRIM
- GRAS_TSEPERF_TRIVAL_REJ_PRIM
- GRAS_TSEPERF_WORKING_CYCLES
- GRAS_TSEPERF_ZERO_AREA_PRIM
- GRAS_TSEPERF_ZERO_PIXEL_PRIM
- GRAS_TSERASPERF_STALL
- GRAVEYARD_BUFS
- GRAVEYARD_BUFSZ
- GRA_D
- GRA_FF_ALLEMPTY
- GRA_FF_ALLEMPTY_MASK
- GRA_FF_UNDERFLOW
- GRA_FF_UNDERFLOW_ENA
- GRA_FF_UNDERFLOW_ENA_MASK
- GRA_FF_UNDERFLOW_MASK
- GRA_FRAME_CNT_ISR
- GRA_FRAME_CNT_ISR_MASK
- GRA_FRAME_CNT_MASK
- GRA_FRAME_IRQ
- GRA_FRAME_IRQ0
- GRA_FRAME_IRQ0_ENA
- GRA_FRAME_IRQ0_ENA_MASK
- GRA_FRAME_IRQ0_LEVEL
- GRA_FRAME_IRQ0_LEVEL_MASK
- GRA_FRAME_IRQ0_MASK
- GRA_FRAME_IRQ1
- GRA_FRAME_IRQ1_ENA
- GRA_FRAME_IRQ1_ENA_MASK
- GRA_FRAME_IRQ1_LEVEL
- GRA_FRAME_IRQ1_LEVEL_MASK
- GRA_FRAME_IRQ1_MASK
- GRA_FRAME_IRQ_ENA
- GRA_I
- GRA_MASK
- GRAin
- GRAout
- GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK
- GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT
- GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK
- GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT
- GRBM_CAM_DATA__CAM_ADDR_MASK
- GRBM_CAM_DATA__CAM_ADDR__SHIFT
- GRBM_CAM_DATA__CAM_REMAPADDR_MASK
- GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT
- GRBM_CAM_INDEX__CAM_INDEX_MASK
- GRBM_CAM_INDEX__CAM_INDEX__SHIFT
- GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK
- GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT
- GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK
- GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK
- GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT
- GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK
- GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT
- GRBM_CHIP_REVISION__CHIP_REVISION_MASK
- GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT
- GRBM_CNTL
- GRBM_CNTL__READ_TIMEOUT_MASK
- GRBM_CNTL__READ_TIMEOUT__SHIFT
- GRBM_CNTL__REPORT_LAST_RDERR_MASK
- GRBM_CNTL__REPORT_LAST_RDERR__SHIFT
- GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK
- GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT
- GRBM_DEBUG_DATA__DATA_MASK
- GRBM_DEBUG_DATA__DATA__SHIFT
- GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT
- GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT
- GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK
- GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT
- GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT
- GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT
- GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK
- GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT
- GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK
- GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT
- GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK
- GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT
- GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK
- GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT
- GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK
- GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT
- GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK
- GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT
- GRBM_DEBUG__IGNORE_FAO_MASK
- GRBM_DEBUG__IGNORE_FAO__SHIFT
- GRBM_DEBUG__IGNORE_RDY_MASK
- GRBM_DEBUG__IGNORE_RDY__SHIFT
- GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK
- GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT
- GRBM_DSM_BYPASS__BYPASS_BITS_MASK
- GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT
- GRBM_DSM_BYPASS__BYPASS_EN_MASK
- GRBM_DSM_BYPASS__BYPASS_EN__SHIFT
- GRBM_EE_BUSY
- GRBM_FENCE_RANGE0__END_MASK
- GRBM_FENCE_RANGE0__END__SHIFT
- GRBM_FENCE_RANGE0__START_MASK
- GRBM_FENCE_RANGE0__START__SHIFT
- GRBM_FENCE_RANGE1__END_MASK
- GRBM_FENCE_RANGE1__END__SHIFT
- GRBM_FENCE_RANGE1__START_MASK
- GRBM_FENCE_RANGE1__START__SHIFT
- GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK
- GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT
- GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK
- GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT
- GRBM_GFX_CNTL_SR_DATA__MEID_MASK
- GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT
- GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK
- GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT
- GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK
- GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT
- GRBM_GFX_CNTL_SR_DATA__VMID_MASK
- GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT
- GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK
- GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT
- GRBM_GFX_CNTL__MEID_MASK
- GRBM_GFX_CNTL__MEID__SHIFT
- GRBM_GFX_CNTL__PIPEID_MASK
- GRBM_GFX_CNTL__PIPEID__SHIFT
- GRBM_GFX_CNTL__QUEUEID_MASK
- GRBM_GFX_CNTL__QUEUEID__SHIFT
- GRBM_GFX_CNTL__VMID_MASK
- GRBM_GFX_CNTL__VMID__SHIFT
- GRBM_GFX_INDEX
- GRBM_GFX_INDEX_ACP
- GRBM_GFX_INDEX_BIF
- GRBM_GFX_INDEX_BITS
- GRBM_GFX_INDEX_ISP
- GRBM_GFX_INDEX_SAMMSP
- GRBM_GFX_INDEX_SAMSCP
- GRBM_GFX_INDEX_SDMA0
- GRBM_GFX_INDEX_SDMA1
- GRBM_GFX_INDEX_SDMA2
- GRBM_GFX_INDEX_SDMA3
- GRBM_GFX_INDEX_SMU
- GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK
- GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK
- GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK
- GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK
- GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT
- GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK
- GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT
- GRBM_GFX_INDEX_TST
- GRBM_GFX_INDEX_UVD
- GRBM_GFX_INDEX_VCE0
- GRBM_GFX_INDEX_VCE1
- GRBM_GFX_INDEX_VP8
- GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX__INSTANCE_INDEX_MASK
- GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT
- GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX__SA_INDEX_MASK
- GRBM_GFX_INDEX__SA_INDEX__SHIFT
- GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX__SE_INDEX_MASK
- GRBM_GFX_INDEX__SE_INDEX__SHIFT
- GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK
- GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT
- GRBM_GFX_INDEX__SH_INDEX_MASK
- GRBM_GFX_INDEX__SH_INDEX__SHIFT
- GRBM_GFX_INDEX__VCE_ALL_PIPE
- GRBM_GFX_INDEX__VCE_INSTANCE_MASK
- GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT
- GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK
- GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT
- GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK
- GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT
- GRBM_HYP_CAM_DATA__CAM_ADDR_MASK
- GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT
- GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK
- GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT
- GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK
- GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT
- GRBM_IH_CREDIT__CREDIT_VALUE_MASK
- GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT
- GRBM_IH_CREDIT__IH_CLIENT_ID_MASK
- GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT
- GRBM_INT_CNTL
- GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK
- GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT
- GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK
- GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT
- GRBM_IOV_ERROR__IOV_ADDR_MASK
- GRBM_IOV_ERROR__IOV_ADDR__SHIFT
- GRBM_IOV_ERROR__IOV_ERROR_MASK
- GRBM_IOV_ERROR__IOV_ERROR__SHIFT
- GRBM_IOV_ERROR__IOV_OP_MASK
- GRBM_IOV_ERROR__IOV_OP__SHIFT
- GRBM_IOV_ERROR__IOV_VFID_MASK
- GRBM_IOV_ERROR__IOV_VFID__SHIFT
- GRBM_IOV_ERROR__IOV_VF_MASK
- GRBM_IOV_ERROR__IOV_VF__SHIFT
- GRBM_IOV_READ_ERROR__IOV_ADDR_MASK
- GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT
- GRBM_IOV_READ_ERROR__IOV_ERROR_MASK
- GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT
- GRBM_IOV_READ_ERROR__IOV_OP_MASK
- GRBM_IOV_READ_ERROR__IOV_OP__SHIFT
- GRBM_IOV_READ_ERROR__IOV_VFID_MASK
- GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT
- GRBM_IOV_READ_ERROR__IOV_VF_MASK
- GRBM_IOV_READ_ERROR__IOV_VF__SHIFT
- GRBM_NOWHERE__DATA_MASK
- GRBM_NOWHERE__DATA__SHIFT
- GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK
- GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_PERF_SEL
- GRBM_PERF_SEL_BCI_BUSY
- GRBM_PERF_SEL_CB_BUSY
- GRBM_PERF_SEL_CB_CLEAN
- GRBM_PERF_SEL_CH_BUSY
- GRBM_PERF_SEL_COUNT
- GRBM_PERF_SEL_CPAXI_BUSY
- GRBM_PERF_SEL_CPC_BUSY
- GRBM_PERF_SEL_CPF_BUSY
- GRBM_PERF_SEL_CPG_BUSY
- GRBM_PERF_SEL_CP_BUSY
- GRBM_PERF_SEL_CP_COHER_BUSY
- GRBM_PERF_SEL_CP_DMA_BUSY
- GRBM_PERF_SEL_DB_BUSY
- GRBM_PERF_SEL_DB_CLEAN
- GRBM_PERF_SEL_EA_BUSY
- GRBM_PERF_SEL_GDS_BUSY
- GRBM_PERF_SEL_GE_BUSY
- GRBM_PERF_SEL_GE_NO_DMA_BUSY
- GRBM_PERF_SEL_GL1CC_BUSY
- GRBM_PERF_SEL_GL2CC_BUSY
- GRBM_PERF_SEL_GUI_ACTIVE
- GRBM_PERF_SEL_GUS_BUSY
- GRBM_PERF_SEL_IA_BUSY
- GRBM_PERF_SEL_IA_NO_DMA_BUSY
- GRBM_PERF_SEL_PA_BUSY
- GRBM_PERF_SEL_PH_BUSY
- GRBM_PERF_SEL_PMM_BUSY
- GRBM_PERF_SEL_RESERVED_0
- GRBM_PERF_SEL_RESERVED_1
- GRBM_PERF_SEL_RESERVED_2
- GRBM_PERF_SEL_RESERVED_3
- GRBM_PERF_SEL_RESERVED_4
- GRBM_PERF_SEL_RESERVED_5
- GRBM_PERF_SEL_RESERVED_6
- GRBM_PERF_SEL_RESERVED_7
- GRBM_PERF_SEL_RESERVED_8
- GRBM_PERF_SEL_RESERVED_9
- GRBM_PERF_SEL_RLC_BUSY
- GRBM_PERF_SEL_RMI_BUSY
- GRBM_PERF_SEL_SC_BUSY
- GRBM_PERF_SEL_SDMA_BUSY
- GRBM_PERF_SEL_SPI_BUSY
- GRBM_PERF_SEL_SX_BUSY
- GRBM_PERF_SEL_TA_BUSY
- GRBM_PERF_SEL_TCP_BUSY
- GRBM_PERF_SEL_TC_BUSY
- GRBM_PERF_SEL_USER_DEFINED
- GRBM_PERF_SEL_UTCL1_BUSY
- GRBM_PERF_SEL_UTCL2_BUSY
- GRBM_PERF_SEL_VGT_BUSY
- GRBM_PERF_SEL_WD_BUSY
- GRBM_PERF_SEL_WD_NO_DMA_BUSY
- GRBM_PM_CNTL__PM_READY_MASK
- GRBM_PM_CNTL__PM_READY__SHIFT
- GRBM_PM_CNTL__PM_START_MASK
- GRBM_PM_CNTL__PM_START__SHIFT
- GRBM_PWR_CNTL
- GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK
- GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT
- GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK
- GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT
- GRBM_PWR_CNTL__ALL_REQ_EN_MASK
- GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT
- GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK
- GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT
- GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK
- GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT
- GRBM_PWR_CNTL__GFX_REQ_EN_MASK
- GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT
- GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK
- GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT
- GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK
- GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT
- GRBM_PWR_CNTL__REQ_TYPE_MASK
- GRBM_PWR_CNTL__REQ_TYPE__SHIFT
- GRBM_PWR_CNTL__RSP_TYPE_MASK
- GRBM_PWR_CNTL__RSP_TYPE__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT
- GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK
- GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT
- GRBM_READ_ERROR__READ_ADDRESS_MASK
- GRBM_READ_ERROR__READ_ADDRESS__SHIFT
- GRBM_READ_ERROR__READ_ERROR_MASK
- GRBM_READ_ERROR__READ_ERROR__SHIFT
- GRBM_READ_ERROR__READ_MEID_MASK
- GRBM_READ_ERROR__READ_MEID__SHIFT
- GRBM_READ_ERROR__READ_PIPEID_MASK
- GRBM_READ_ERROR__READ_PIPEID__SHIFT
- GRBM_READ_TIMEOUT
- GRBM_REG_SGIT
- GRBM_REG_SGIT_MASK
- GRBM_RQ_PENDING
- GRBM_RSMU_CFG__APERTURE_ID_MASK
- GRBM_RSMU_CFG__APERTURE_ID__SHIFT
- GRBM_RSMU_CFG__DEBUG_MASK_MASK
- GRBM_RSMU_CFG__DEBUG_MASK__SHIFT
- GRBM_RSMU_CFG__POSTED_WR_MASK
- GRBM_RSMU_CFG__POSTED_WR__SHIFT
- GRBM_RSMU_CFG__QOS_MASK
- GRBM_RSMU_CFG__QOS__SHIFT
- GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK
- GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT
- GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK
- GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK
- GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT
- GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT
- GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK
- GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT
- GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK
- GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT
- GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK
- GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT
- GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK
- GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT
- GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK
- GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT
- GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK
- GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT
- GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK
- GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT
- GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK
- GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT
- GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK
- GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT
- GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK
- GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT
- GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK
- GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT
- GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK
- GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE0_PERF_SEL
- GRBM_SE0_PERF_SEL_BCI_BUSY
- GRBM_SE0_PERF_SEL_CB_BUSY
- GRBM_SE0_PERF_SEL_CB_CLEAN
- GRBM_SE0_PERF_SEL_COUNT
- GRBM_SE0_PERF_SEL_DB_BUSY
- GRBM_SE0_PERF_SEL_DB_CLEAN
- GRBM_SE0_PERF_SEL_GL1CC_BUSY
- GRBM_SE0_PERF_SEL_PA_BUSY
- GRBM_SE0_PERF_SEL_RESERVED_0
- GRBM_SE0_PERF_SEL_RESERVED_1
- GRBM_SE0_PERF_SEL_RESERVED_2
- GRBM_SE0_PERF_SEL_RMI_BUSY
- GRBM_SE0_PERF_SEL_SC_BUSY
- GRBM_SE0_PERF_SEL_SPI_BUSY
- GRBM_SE0_PERF_SEL_SX_BUSY
- GRBM_SE0_PERF_SEL_TA_BUSY
- GRBM_SE0_PERF_SEL_TCP_BUSY
- GRBM_SE0_PERF_SEL_USER_DEFINED
- GRBM_SE0_PERF_SEL_UTCL1_BUSY
- GRBM_SE0_PERF_SEL_VGT_BUSY
- GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK
- GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT
- GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK
- GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE1_PERF_SEL
- GRBM_SE1_PERF_SEL_BCI_BUSY
- GRBM_SE1_PERF_SEL_CB_BUSY
- GRBM_SE1_PERF_SEL_CB_CLEAN
- GRBM_SE1_PERF_SEL_COUNT
- GRBM_SE1_PERF_SEL_DB_BUSY
- GRBM_SE1_PERF_SEL_DB_CLEAN
- GRBM_SE1_PERF_SEL_GL1CC_BUSY
- GRBM_SE1_PERF_SEL_PA_BUSY
- GRBM_SE1_PERF_SEL_RESERVED_0
- GRBM_SE1_PERF_SEL_RESERVED_1
- GRBM_SE1_PERF_SEL_RESERVED_2
- GRBM_SE1_PERF_SEL_RMI_BUSY
- GRBM_SE1_PERF_SEL_SC_BUSY
- GRBM_SE1_PERF_SEL_SPI_BUSY
- GRBM_SE1_PERF_SEL_SX_BUSY
- GRBM_SE1_PERF_SEL_TA_BUSY
- GRBM_SE1_PERF_SEL_TCP_BUSY
- GRBM_SE1_PERF_SEL_USER_DEFINED
- GRBM_SE1_PERF_SEL_UTCL1_BUSY
- GRBM_SE1_PERF_SEL_VGT_BUSY
- GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK
- GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT
- GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK
- GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE2_PERF_SEL
- GRBM_SE2_PERF_SEL_BCI_BUSY
- GRBM_SE2_PERF_SEL_CB_BUSY
- GRBM_SE2_PERF_SEL_CB_CLEAN
- GRBM_SE2_PERF_SEL_COUNT
- GRBM_SE2_PERF_SEL_DB_BUSY
- GRBM_SE2_PERF_SEL_DB_CLEAN
- GRBM_SE2_PERF_SEL_GL1CC_BUSY
- GRBM_SE2_PERF_SEL_PA_BUSY
- GRBM_SE2_PERF_SEL_RESERVED_0
- GRBM_SE2_PERF_SEL_RESERVED_1
- GRBM_SE2_PERF_SEL_RESERVED_2
- GRBM_SE2_PERF_SEL_RMI_BUSY
- GRBM_SE2_PERF_SEL_SC_BUSY
- GRBM_SE2_PERF_SEL_SPI_BUSY
- GRBM_SE2_PERF_SEL_SX_BUSY
- GRBM_SE2_PERF_SEL_TA_BUSY
- GRBM_SE2_PERF_SEL_TCP_BUSY
- GRBM_SE2_PERF_SEL_USER_DEFINED
- GRBM_SE2_PERF_SEL_UTCL1_BUSY
- GRBM_SE2_PERF_SEL_VGT_BUSY
- GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK
- GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT
- GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK
- GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK
- GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT
- GRBM_SE3_PERF_SEL
- GRBM_SE3_PERF_SEL_BCI_BUSY
- GRBM_SE3_PERF_SEL_CB_BUSY
- GRBM_SE3_PERF_SEL_CB_CLEAN
- GRBM_SE3_PERF_SEL_COUNT
- GRBM_SE3_PERF_SEL_DB_BUSY
- GRBM_SE3_PERF_SEL_DB_CLEAN
- GRBM_SE3_PERF_SEL_GL1CC_BUSY
- GRBM_SE3_PERF_SEL_PA_BUSY
- GRBM_SE3_PERF_SEL_RESERVED_0
- GRBM_SE3_PERF_SEL_RESERVED_1
- GRBM_SE3_PERF_SEL_RESERVED_2
- GRBM_SE3_PERF_SEL_RMI_BUSY
- GRBM_SE3_PERF_SEL_SC_BUSY
- GRBM_SE3_PERF_SEL_SPI_BUSY
- GRBM_SE3_PERF_SEL_SX_BUSY
- GRBM_SE3_PERF_SEL_TA_BUSY
- GRBM_SE3_PERF_SEL_TCP_BUSY
- GRBM_SE3_PERF_SEL_USER_DEFINED
- GRBM_SE3_PERF_SEL_UTCL1_BUSY
- GRBM_SE3_PERF_SEL_VGT_BUSY
- GRBM_SKEW_CNTL__SKEW_COUNT_MASK
- GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT
- GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK
- GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT
- GRBM_SOFT_RESET
- GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_CP_MASK
- GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_EA_MASK
- GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK
- GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK
- GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK
- GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT
- GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
- GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT
- GRBM_STATUS
- GRBM_STATUS2
- GRBM_STATUS2__CPAXI_BUSY_MASK
- GRBM_STATUS2__CPAXI_BUSY__SHIFT
- GRBM_STATUS2__CPC_BUSY_MASK
- GRBM_STATUS2__CPC_BUSY__SHIFT
- GRBM_STATUS2__CPF_BUSY_MASK
- GRBM_STATUS2__CPF_BUSY__SHIFT
- GRBM_STATUS2__CPF_RQ_PENDING_MASK
- GRBM_STATUS2__CPF_RQ_PENDING__SHIFT
- GRBM_STATUS2__CPG_BUSY_MASK
- GRBM_STATUS2__CPG_BUSY__SHIFT
- GRBM_STATUS2__EA_BUSY_MASK
- GRBM_STATUS2__EA_BUSY__SHIFT
- GRBM_STATUS2__EA_LINK_BUSY_MASK
- GRBM_STATUS2__EA_LINK_BUSY__SHIFT
- GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK
- GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK
- GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT
- GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK
- GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK
- GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK
- GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK
- GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK
- GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK
- GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK
- GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK
- GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT
- GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK
- GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT
- GRBM_STATUS2__RLC_BUSY_MASK
- GRBM_STATUS2__RLC_BUSY__SHIFT
- GRBM_STATUS2__RLC_RQ_PENDING_MASK
- GRBM_STATUS2__RLC_RQ_PENDING__SHIFT
- GRBM_STATUS2__RMI_BUSY_MASK
- GRBM_STATUS2__RMI_BUSY__SHIFT
- GRBM_STATUS2__SDMA0_RQ_PENDING_MASK
- GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT
- GRBM_STATUS2__SDMA1_RQ_PENDING_MASK
- GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT
- GRBM_STATUS2__SDMA_BUSY_MASK
- GRBM_STATUS2__SDMA_BUSY__SHIFT
- GRBM_STATUS2__TCC_CC_RESIDENT_MASK
- GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT
- GRBM_STATUS2__TCP_BUSY_MASK
- GRBM_STATUS2__TCP_BUSY__SHIFT
- GRBM_STATUS2__TC_BUSY_MASK
- GRBM_STATUS2__TC_BUSY__SHIFT
- GRBM_STATUS2__UTCL2_BUSY_MASK
- GRBM_STATUS2__UTCL2_BUSY__SHIFT
- GRBM_STATUS2__UTCL2_RQ_PENDING_MASK
- GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT
- GRBM_STATUS3__CH_BUSY_MASK
- GRBM_STATUS3__CH_BUSY__SHIFT
- GRBM_STATUS3__GL1CC_BUSY_MASK
- GRBM_STATUS3__GL1CC_BUSY__SHIFT
- GRBM_STATUS3__GL2CC_BUSY_MASK
- GRBM_STATUS3__GL2CC_BUSY__SHIFT
- GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK
- GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT
- GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK
- GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT
- GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK
- GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT
- GRBM_STATUS3__GUS_BUSY_MASK
- GRBM_STATUS3__GUS_BUSY__SHIFT
- GRBM_STATUS3__GUS_LINK_BUSY_MASK
- GRBM_STATUS3__GUS_LINK_BUSY__SHIFT
- GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK
- GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT
- GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK
- GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT
- GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK
- GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT
- GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK
- GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT
- GRBM_STATUS3__PH_BUSY_MASK
- GRBM_STATUS3__PH_BUSY__SHIFT
- GRBM_STATUS3__PMM_BUSY_MASK
- GRBM_STATUS3__PMM_BUSY__SHIFT
- GRBM_STATUS3__UTCL1_BUSY_MASK
- GRBM_STATUS3__UTCL1_BUSY__SHIFT
- GRBM_STATUS_SE0
- GRBM_STATUS_SE0__BCI_BUSY_MASK
- GRBM_STATUS_SE0__BCI_BUSY__SHIFT
- GRBM_STATUS_SE0__CB_BUSY_MASK
- GRBM_STATUS_SE0__CB_BUSY__SHIFT
- GRBM_STATUS_SE0__CB_CLEAN_MASK
- GRBM_STATUS_SE0__CB_CLEAN__SHIFT
- GRBM_STATUS_SE0__DB_BUSY_MASK
- GRBM_STATUS_SE0__DB_BUSY__SHIFT
- GRBM_STATUS_SE0__DB_CLEAN_MASK
- GRBM_STATUS_SE0__DB_CLEAN__SHIFT
- GRBM_STATUS_SE0__GL1CC_BUSY_MASK
- GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT
- GRBM_STATUS_SE0__PA_BUSY_MASK
- GRBM_STATUS_SE0__PA_BUSY__SHIFT
- GRBM_STATUS_SE0__RMI_BUSY_MASK
- GRBM_STATUS_SE0__RMI_BUSY__SHIFT
- GRBM_STATUS_SE0__SC_BUSY_MASK
- GRBM_STATUS_SE0__SC_BUSY__SHIFT
- GRBM_STATUS_SE0__SPI_BUSY_MASK
- GRBM_STATUS_SE0__SPI_BUSY__SHIFT
- GRBM_STATUS_SE0__SX_BUSY_MASK
- GRBM_STATUS_SE0__SX_BUSY__SHIFT
- GRBM_STATUS_SE0__TA_BUSY_MASK
- GRBM_STATUS_SE0__TA_BUSY__SHIFT
- GRBM_STATUS_SE0__TCP_BUSY_MASK
- GRBM_STATUS_SE0__TCP_BUSY__SHIFT
- GRBM_STATUS_SE0__UTCL1_BUSY_MASK
- GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT
- GRBM_STATUS_SE0__VGT_BUSY_MASK
- GRBM_STATUS_SE0__VGT_BUSY__SHIFT
- GRBM_STATUS_SE1
- GRBM_STATUS_SE1__BCI_BUSY_MASK
- GRBM_STATUS_SE1__BCI_BUSY__SHIFT
- GRBM_STATUS_SE1__CB_BUSY_MASK
- GRBM_STATUS_SE1__CB_BUSY__SHIFT
- GRBM_STATUS_SE1__CB_CLEAN_MASK
- GRBM_STATUS_SE1__CB_CLEAN__SHIFT
- GRBM_STATUS_SE1__DB_BUSY_MASK
- GRBM_STATUS_SE1__DB_BUSY__SHIFT
- GRBM_STATUS_SE1__DB_CLEAN_MASK
- GRBM_STATUS_SE1__DB_CLEAN__SHIFT
- GRBM_STATUS_SE1__GL1CC_BUSY_MASK
- GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT
- GRBM_STATUS_SE1__PA_BUSY_MASK
- GRBM_STATUS_SE1__PA_BUSY__SHIFT
- GRBM_STATUS_SE1__RMI_BUSY_MASK
- GRBM_STATUS_SE1__RMI_BUSY__SHIFT
- GRBM_STATUS_SE1__SC_BUSY_MASK
- GRBM_STATUS_SE1__SC_BUSY__SHIFT
- GRBM_STATUS_SE1__SPI_BUSY_MASK
- GRBM_STATUS_SE1__SPI_BUSY__SHIFT
- GRBM_STATUS_SE1__SX_BUSY_MASK
- GRBM_STATUS_SE1__SX_BUSY__SHIFT
- GRBM_STATUS_SE1__TA_BUSY_MASK
- GRBM_STATUS_SE1__TA_BUSY__SHIFT
- GRBM_STATUS_SE1__TCP_BUSY_MASK
- GRBM_STATUS_SE1__TCP_BUSY__SHIFT
- GRBM_STATUS_SE1__UTCL1_BUSY_MASK
- GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT
- GRBM_STATUS_SE1__VGT_BUSY_MASK
- GRBM_STATUS_SE1__VGT_BUSY__SHIFT
- GRBM_STATUS_SE2
- GRBM_STATUS_SE2__BCI_BUSY_MASK
- GRBM_STATUS_SE2__BCI_BUSY__SHIFT
- GRBM_STATUS_SE2__CB_BUSY_MASK
- GRBM_STATUS_SE2__CB_BUSY__SHIFT
- GRBM_STATUS_SE2__CB_CLEAN_MASK
- GRBM_STATUS_SE2__CB_CLEAN__SHIFT
- GRBM_STATUS_SE2__DB_BUSY_MASK
- GRBM_STATUS_SE2__DB_BUSY__SHIFT
- GRBM_STATUS_SE2__DB_CLEAN_MASK
- GRBM_STATUS_SE2__DB_CLEAN__SHIFT
- GRBM_STATUS_SE2__GL1CC_BUSY_MASK
- GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT
- GRBM_STATUS_SE2__PA_BUSY_MASK
- GRBM_STATUS_SE2__PA_BUSY__SHIFT
- GRBM_STATUS_SE2__RMI_BUSY_MASK
- GRBM_STATUS_SE2__RMI_BUSY__SHIFT
- GRBM_STATUS_SE2__SC_BUSY_MASK
- GRBM_STATUS_SE2__SC_BUSY__SHIFT
- GRBM_STATUS_SE2__SPI_BUSY_MASK
- GRBM_STATUS_SE2__SPI_BUSY__SHIFT
- GRBM_STATUS_SE2__SX_BUSY_MASK
- GRBM_STATUS_SE2__SX_BUSY__SHIFT
- GRBM_STATUS_SE2__TA_BUSY_MASK
- GRBM_STATUS_SE2__TA_BUSY__SHIFT
- GRBM_STATUS_SE2__TCP_BUSY_MASK
- GRBM_STATUS_SE2__TCP_BUSY__SHIFT
- GRBM_STATUS_SE2__UTCL1_BUSY_MASK
- GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT
- GRBM_STATUS_SE2__VGT_BUSY_MASK
- GRBM_STATUS_SE2__VGT_BUSY__SHIFT
- GRBM_STATUS_SE3
- GRBM_STATUS_SE3__BCI_BUSY_MASK
- GRBM_STATUS_SE3__BCI_BUSY__SHIFT
- GRBM_STATUS_SE3__CB_BUSY_MASK
- GRBM_STATUS_SE3__CB_BUSY__SHIFT
- GRBM_STATUS_SE3__CB_CLEAN_MASK
- GRBM_STATUS_SE3__CB_CLEAN__SHIFT
- GRBM_STATUS_SE3__DB_BUSY_MASK
- GRBM_STATUS_SE3__DB_BUSY__SHIFT
- GRBM_STATUS_SE3__DB_CLEAN_MASK
- GRBM_STATUS_SE3__DB_CLEAN__SHIFT
- GRBM_STATUS_SE3__GL1CC_BUSY_MASK
- GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT
- GRBM_STATUS_SE3__PA_BUSY_MASK
- GRBM_STATUS_SE3__PA_BUSY__SHIFT
- GRBM_STATUS_SE3__RMI_BUSY_MASK
- GRBM_STATUS_SE3__RMI_BUSY__SHIFT
- GRBM_STATUS_SE3__SC_BUSY_MASK
- GRBM_STATUS_SE3__SC_BUSY__SHIFT
- GRBM_STATUS_SE3__SPI_BUSY_MASK
- GRBM_STATUS_SE3__SPI_BUSY__SHIFT
- GRBM_STATUS_SE3__SX_BUSY_MASK
- GRBM_STATUS_SE3__SX_BUSY__SHIFT
- GRBM_STATUS_SE3__TA_BUSY_MASK
- GRBM_STATUS_SE3__TA_BUSY__SHIFT
- GRBM_STATUS_SE3__TCP_BUSY_MASK
- GRBM_STATUS_SE3__TCP_BUSY__SHIFT
- GRBM_STATUS_SE3__UTCL1_BUSY_MASK
- GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT
- GRBM_STATUS_SE3__VGT_BUSY_MASK
- GRBM_STATUS_SE3__VGT_BUSY__SHIFT
- GRBM_STATUS__BCI_BUSY_MASK
- GRBM_STATUS__BCI_BUSY__SHIFT
- GRBM_STATUS__CB_BUSY_MASK
- GRBM_STATUS__CB_BUSY__SHIFT
- GRBM_STATUS__CB_CLEAN_MASK
- GRBM_STATUS__CB_CLEAN__SHIFT
- GRBM_STATUS__CP_BUSY_MASK
- GRBM_STATUS__CP_BUSY__SHIFT
- GRBM_STATUS__CP_COHERENCY_BUSY_MASK
- GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT
- GRBM_STATUS__DB_BUSY_MASK
- GRBM_STATUS__DB_BUSY__SHIFT
- GRBM_STATUS__DB_CLEAN_MASK
- GRBM_STATUS__DB_CLEAN__SHIFT
- GRBM_STATUS__GDS_BUSY_MASK
- GRBM_STATUS__GDS_BUSY__SHIFT
- GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK
- GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT
- GRBM_STATUS__GE_BUSY_MASK
- GRBM_STATUS__GE_BUSY_NO_DMA_MASK
- GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT
- GRBM_STATUS__GE_BUSY__SHIFT
- GRBM_STATUS__GUI_ACTIVE_MASK
- GRBM_STATUS__GUI_ACTIVE__SHIFT
- GRBM_STATUS__IA_BUSY_MASK
- GRBM_STATUS__IA_BUSY_NO_DMA_MASK
- GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT
- GRBM_STATUS__IA_BUSY__SHIFT
- GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK
- GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT
- GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK
- GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT
- GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK
- GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT
- GRBM_STATUS__PA_BUSY_MASK
- GRBM_STATUS__PA_BUSY__SHIFT
- GRBM_STATUS__RSMU_RQ_PENDING_MASK
- GRBM_STATUS__RSMU_RQ_PENDING__SHIFT
- GRBM_STATUS__SC_BUSY_MASK
- GRBM_STATUS__SC_BUSY__SHIFT
- GRBM_STATUS__SPI_BUSY_MASK
- GRBM_STATUS__SPI_BUSY__SHIFT
- GRBM_STATUS__SRBM_RQ_PENDING_MASK
- GRBM_STATUS__SRBM_RQ_PENDING__SHIFT
- GRBM_STATUS__SX_BUSY_MASK
- GRBM_STATUS__SX_BUSY__SHIFT
- GRBM_STATUS__TA_BUSY_MASK
- GRBM_STATUS__TA_BUSY__SHIFT
- GRBM_STATUS__VGT_BUSY_MASK
- GRBM_STATUS__VGT_BUSY__SHIFT
- GRBM_STATUS__WD_BUSY_MASK
- GRBM_STATUS__WD_BUSY_NO_DMA_MASK
- GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT
- GRBM_STATUS__WD_BUSY__SHIFT
- GRBM_TRAP_ADDR_MSK__DATA_MASK
- GRBM_TRAP_ADDR_MSK__DATA__SHIFT
- GRBM_TRAP_ADDR__DATA_MASK
- GRBM_TRAP_ADDR__DATA__SHIFT
- GRBM_TRAP_OP__RW_MASK
- GRBM_TRAP_OP__RW__SHIFT
- GRBM_TRAP_WD_MSK__DATA_MASK
- GRBM_TRAP_WD_MSK__DATA__SHIFT
- GRBM_TRAP_WD__DATA_MASK
- GRBM_TRAP_WD__DATA__SHIFT
- GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK
- GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT
- GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK
- GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT
- GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK
- GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT
- GRBM_WRITE_ERROR__WRITE_ERROR_MASK
- GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT
- GRBM_WRITE_ERROR__WRITE_MEID_MASK
- GRBM_WRITE_ERROR__WRITE_MEID__SHIFT
- GRBM_WRITE_ERROR__WRITE_PIPEID_MASK
- GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT
- GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK
- GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT
- GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK
- GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT
- GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK
- GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT
- GRBM_WRITE_ERROR__WRITE_SSRCID_MASK
- GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT
- GRBM_WRITE_ERROR__WRITE_VFID_MASK
- GRBM_WRITE_ERROR__WRITE_VFID__SHIFT
- GRBM_WRITE_ERROR__WRITE_VF_MASK
- GRBM_WRITE_ERROR__WRITE_VF__SHIFT
- GRBM_WRITE_ERROR__WRITE_VMID_MASK
- GRBM_WRITE_ERROR__WRITE_VMID__SHIFT
- GRCAN_BUFFER_ALIGNMENT
- GRCAN_CONFIG_ATTR
- GRCAN_CONF_ABORT
- GRCAN_CONF_BPR
- GRCAN_CONF_BPR_BIT
- GRCAN_CONF_ENABLE0
- GRCAN_CONF_ENABLE1
- GRCAN_CONF_OPERATION
- GRCAN_CONF_PS1
- GRCAN_CONF_PS1_BIT
- GRCAN_CONF_PS1_MAX
- GRCAN_CONF_PS1_MIN
- GRCAN_CONF_PS2
- GRCAN_CONF_PS2_BIT
- GRCAN_CONF_PS2_MAX
- GRCAN_CONF_PS2_MIN
- GRCAN_CONF_RSJ
- GRCAN_CONF_RSJ_BIT
- GRCAN_CONF_RSJ_MAX
- GRCAN_CONF_RSJ_MIN
- GRCAN_CONF_SAM
- GRCAN_CONF_SCALER
- GRCAN_CONF_SCALER_BIT
- GRCAN_CONF_SCALER_INC
- GRCAN_CONF_SCALER_MAX
- GRCAN_CONF_SCALER_MIN
- GRCAN_CONF_SELECT
- GRCAN_CONF_SILENT
- GRCAN_CONF_TIMING
- GRCAN_CTRL_ENABLE
- GRCAN_CTRL_RESET
- GRCAN_DEFAULT_BUFFER_SIZE
- GRCAN_DEFAULT_DEVICE_CONFIG
- GRCAN_EFF_FRAME_MAX_BITS
- GRCAN_INVALID_BUFFER_SIZE
- GRCAN_IRQIX_IRQ
- GRCAN_IRQIX_RXSYNC
- GRCAN_IRQIX_TXSYNC
- GRCAN_IRQ_ALL
- GRCAN_IRQ_DEFAULT
- GRCAN_IRQ_ERRCTR_RELATED
- GRCAN_IRQ_ERRORS
- GRCAN_IRQ_NONE
- GRCAN_IRQ_OFF
- GRCAN_IRQ_OR
- GRCAN_IRQ_PASS
- GRCAN_IRQ_RX
- GRCAN_IRQ_RXAHBERR
- GRCAN_IRQ_RXERRCTR
- GRCAN_IRQ_RXFULL
- GRCAN_IRQ_RXIRQ
- GRCAN_IRQ_RXMISS
- GRCAN_IRQ_RXSYNC
- GRCAN_IRQ_TX
- GRCAN_IRQ_TXAHBERR
- GRCAN_IRQ_TXEMPTY
- GRCAN_IRQ_TXERRCTR
- GRCAN_IRQ_TXIRQ
- GRCAN_IRQ_TXLOSS
- GRCAN_IRQ_TXSYNC
- GRCAN_MODULE_PARAM
- GRCAN_MSG_AHBERR
- GRCAN_MSG_BID
- GRCAN_MSG_BID_BIT
- GRCAN_MSG_DATA_SHIFT
- GRCAN_MSG_DATA_SLOT_INDEX
- GRCAN_MSG_DLC
- GRCAN_MSG_DLC_BIT
- GRCAN_MSG_EID
- GRCAN_MSG_EID_BIT
- GRCAN_MSG_IDE
- GRCAN_MSG_IDE_BIT
- GRCAN_MSG_OFF
- GRCAN_MSG_OR
- GRCAN_MSG_PASS
- GRCAN_MSG_RTR
- GRCAN_MSG_RTR_BIT
- GRCAN_MSG_RXERRC
- GRCAN_MSG_RXERRC_BIT
- GRCAN_MSG_SIZE
- GRCAN_MSG_TXERRC
- GRCAN_MSG_TXERRC_BIT
- GRCAN_NAPI_WEIGHT
- GRCAN_NOT_BOOL
- GRCAN_RESERVE_SIZE
- GRCAN_RXCTRL_ENABLE
- GRCAN_RXCTRL_ONGOING
- GRCAN_SHORTWAIT_USECS
- GRCAN_STAT_ACTIVE
- GRCAN_STAT_AHBERR
- GRCAN_STAT_ERRCNT_PASSIVE_LIMIT
- GRCAN_STAT_ERRCNT_WARNING_LIMIT
- GRCAN_STAT_ERRCTR_RELATED
- GRCAN_STAT_OFF
- GRCAN_STAT_OR
- GRCAN_STAT_PASS
- GRCAN_STAT_RXERRCNT
- GRCAN_STAT_RXERRCNT_BIT
- GRCAN_STAT_TXERRCNT
- GRCAN_STAT_TXERRCNT_BIT
- GRCAN_TXBUG_SAFE_GRLIB_VERSION
- GRCAN_TXCTRL_ENABLE
- GRCAN_TXCTRL_ONGOING
- GRCAN_TXCTRL_SINGLE
- GRCAN_VALID_TR_SIZE_MASK
- GRCBASE_AVS_WRAP
- GRCBASE_BAR0_MAP
- GRCBASE_BMB
- GRCBASE_BMBN
- GRCBASE_BRB
- GRCBASE_BRB1
- GRCBASE_BTB
- GRCBASE_CAU
- GRCBASE_CCFC
- GRCBASE_CCM
- GRCBASE_CDU
- GRCBASE_CFC
- GRCBASE_CNIG
- GRCBASE_CPMU
- GRCBASE_CSDM
- GRCBASE_CSEM
- GRCBASE_DBG
- GRCBASE_DBU
- GRCBASE_DMAE
- GRCBASE_DORQ
- GRCBASE_DQ
- GRCBASE_EMAC0
- GRCBASE_EMAC1
- GRCBASE_GRC
- GRCBASE_HC
- GRCBASE_IGU
- GRCBASE_IPC
- GRCBASE_LED
- GRCBASE_MCM
- GRCBASE_MCP
- GRCBASE_MCP2
- GRCBASE_MISC
- GRCBASE_MISCS
- GRCBASE_MISC_AEU
- GRCBASE_MS
- GRCBASE_MSDM
- GRCBASE_MSEM
- GRCBASE_MSTAT0
- GRCBASE_MSTAT1
- GRCBASE_MULD
- GRCBASE_NCSI
- GRCBASE_NIG
- GRCBASE_NWM
- GRCBASE_NWS
- GRCBASE_OPTE
- GRCBASE_PBF
- GRCBASE_PBF_PB1
- GRCBASE_PBF_PB2
- GRCBASE_PCICONFIG
- GRCBASE_PCIE
- GRCBASE_PCIREG
- GRCBASE_PCM
- GRCBASE_PGLCS
- GRCBASE_PGLUE_B
- GRCBASE_PHY_PCIE
- GRCBASE_PRM
- GRCBASE_PRS
- GRCBASE_PSDM
- GRCBASE_PSEM
- GRCBASE_PSWHST
- GRCBASE_PSWHST2
- GRCBASE_PSWRD
- GRCBASE_PSWRD2
- GRCBASE_PSWRQ
- GRCBASE_PSWRQ2
- GRCBASE_PSWWR
- GRCBASE_PSWWR2
- GRCBASE_PTLD
- GRCBASE_PTU
- GRCBASE_PXP
- GRCBASE_PXP2
- GRCBASE_PXPCS
- GRCBASE_PXPREQBUS
- GRCBASE_QM
- GRCBASE_RDIF
- GRCBASE_RGFS
- GRCBASE_RGSRC
- GRCBASE_RPB
- GRCBASE_RSS
- GRCBASE_SRC
- GRCBASE_SRCH
- GRCBASE_TCFC
- GRCBASE_TCM
- GRCBASE_TDIF
- GRCBASE_TGFS
- GRCBASE_TGSRC
- GRCBASE_TIMERS
- GRCBASE_TM
- GRCBASE_TMLD
- GRCBASE_TSDM
- GRCBASE_TSEM
- GRCBASE_UCM
- GRCBASE_UMAC
- GRCBASE_UMAC0
- GRCBASE_UMAC1
- GRCBASE_UPB
- GRCBASE_USDM
- GRCBASE_USEM
- GRCBASE_WOL
- GRCBASE_XCM
- GRCBASE_XMAC
- GRCBASE_XMAC0
- GRCBASE_XMAC1
- GRCBASE_XPB
- GRCBASE_XSDM
- GRCBASE_XSEM
- GRCBASE_XYLD
- GRCBASE_YCM
- GRCBASE_YPLD
- GRCBASE_YSDM
- GRCBASE_YSEM
- GRCBASE_YULD
- GRCMBOX_BASE
- GRCMBOX_GENERAL_0
- GRCMBOX_GENERAL_1
- GRCMBOX_GENERAL_2
- GRCMBOX_GENERAL_3
- GRCMBOX_GENERAL_4
- GRCMBOX_GENERAL_5
- GRCMBOX_GENERAL_6
- GRCMBOX_GENERAL_7
- GRCMBOX_HIGH_PRIO_EV_MASK
- GRCMBOX_HIGH_PRIO_EV_VECTOR
- GRCMBOX_INTERRUPT_0
- GRCMBOX_INTERRUPT_1
- GRCMBOX_INTERRUPT_2
- GRCMBOX_INTERRUPT_3
- GRCMBOX_LOW_PRIO_EV_MASK
- GRCMBOX_LOW_PRIO_EV_VEC
- GRCMBOX_RCVJUMBO_PROD_IDX
- GRCMBOX_RCVMINI_PROD_IDX
- GRCMBOX_RCVRET_CON_IDX_0
- GRCMBOX_RCVRET_CON_IDX_1
- GRCMBOX_RCVRET_CON_IDX_10
- GRCMBOX_RCVRET_CON_IDX_11
- GRCMBOX_RCVRET_CON_IDX_12
- GRCMBOX_RCVRET_CON_IDX_13
- GRCMBOX_RCVRET_CON_IDX_14
- GRCMBOX_RCVRET_CON_IDX_15
- GRCMBOX_RCVRET_CON_IDX_2
- GRCMBOX_RCVRET_CON_IDX_3
- GRCMBOX_RCVRET_CON_IDX_4
- GRCMBOX_RCVRET_CON_IDX_5
- GRCMBOX_RCVRET_CON_IDX_6
- GRCMBOX_RCVRET_CON_IDX_7
- GRCMBOX_RCVRET_CON_IDX_8
- GRCMBOX_RCVRET_CON_IDX_9
- GRCMBOX_RCVSTD_PROD_IDX
- GRCMBOX_RELOAD_STAT
- GRCMBOX_SNDHOST_PROD_IDX_0
- GRCMBOX_SNDHOST_PROD_IDX_1
- GRCMBOX_SNDHOST_PROD_IDX_10
- GRCMBOX_SNDHOST_PROD_IDX_11
- GRCMBOX_SNDHOST_PROD_IDX_12
- GRCMBOX_SNDHOST_PROD_IDX_13
- GRCMBOX_SNDHOST_PROD_IDX_14
- GRCMBOX_SNDHOST_PROD_IDX_15
- GRCMBOX_SNDHOST_PROD_IDX_2
- GRCMBOX_SNDHOST_PROD_IDX_3
- GRCMBOX_SNDHOST_PROD_IDX_4
- GRCMBOX_SNDHOST_PROD_IDX_5
- GRCMBOX_SNDHOST_PROD_IDX_6
- GRCMBOX_SNDHOST_PROD_IDX_7
- GRCMBOX_SNDHOST_PROD_IDX_8
- GRCMBOX_SNDHOST_PROD_IDX_9
- GRCMBOX_SNDNIC_PROD_IDX_0
- GRCMBOX_SNDNIC_PROD_IDX_1
- GRCMBOX_SNDNIC_PROD_IDX_10
- GRCMBOX_SNDNIC_PROD_IDX_11
- GRCMBOX_SNDNIC_PROD_IDX_12
- GRCMBOX_SNDNIC_PROD_IDX_13
- GRCMBOX_SNDNIC_PROD_IDX_14
- GRCMBOX_SNDNIC_PROD_IDX_15
- GRCMBOX_SNDNIC_PROD_IDX_2
- GRCMBOX_SNDNIC_PROD_IDX_3
- GRCMBOX_SNDNIC_PROD_IDX_4
- GRCMBOX_SNDNIC_PROD_IDX_5
- GRCMBOX_SNDNIC_PROD_IDX_6
- GRCMBOX_SNDNIC_PROD_IDX_7
- GRCMBOX_SNDNIC_PROD_IDX_8
- GRCMBOX_SNDNIC_PROD_IDX_9
- GRCYGAIN
- GRC_ADDR_BITS
- GRC_BAR2_CONFIG
- GRC_CACHE_MISSES
- GRC_CODE_FAST_MASK
- GRC_CODE_FAST_SHIFT
- GRC_CODE_MASK
- GRC_CODE_NOM_MASK
- GRC_CODE_SHIFT
- GRC_CODE_SLOW_MASK
- GRC_CODE_SLOW_SHIFT
- GRC_CONFIG_2_SIZE_REG
- GRC_CONFIG_3_SIZE_REG
- GRC_CONFIG_REG_PF_INIT_VF
- GRC_CONFIG_REG_VF_MSIX_CONTROL
- GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK
- GRC_DIS
- GRC_DONE
- GRC_DUMP
- GRC_EEPROM_ADDR
- GRC_EEPROM_CTRL
- GRC_EEPROM_DATA
- GRC_FASTBOOT_PC
- GRC_LCLCTRL_AUTO_SEEPROM
- GRC_LCLCTRL_BANK_SELECT
- GRC_LCLCTRL_CLEARINT
- GRC_LCLCTRL_EXTMEM_ENABLE
- GRC_LCLCTRL_GPIO_INPUT0
- GRC_LCLCTRL_GPIO_INPUT1
- GRC_LCLCTRL_GPIO_INPUT2
- GRC_LCLCTRL_GPIO_INPUT3
- GRC_LCLCTRL_GPIO_OE0
- GRC_LCLCTRL_GPIO_OE1
- GRC_LCLCTRL_GPIO_OE2
- GRC_LCLCTRL_GPIO_OE3
- GRC_LCLCTRL_GPIO_OUTPUT0
- GRC_LCLCTRL_GPIO_OUTPUT1
- GRC_LCLCTRL_GPIO_OUTPUT2
- GRC_LCLCTRL_GPIO_OUTPUT3
- GRC_LCLCTRL_GPIO_UART_SEL
- GRC_LCLCTRL_INT_ACTIVE
- GRC_LCLCTRL_INT_ON_ATTN
- GRC_LCLCTRL_MEMSZ_16M
- GRC_LCLCTRL_MEMSZ_1M
- GRC_LCLCTRL_MEMSZ_256K
- GRC_LCLCTRL_MEMSZ_2M
- GRC_LCLCTRL_MEMSZ_4M
- GRC_LCLCTRL_MEMSZ_512K
- GRC_LCLCTRL_MEMSZ_8M
- GRC_LCLCTRL_MEMSZ_MASK
- GRC_LCLCTRL_SETINT
- GRC_LCLCTRL_SSRAM_TYPE
- GRC_LCLCTRL_USE_EXT_SIG_DETECT
- GRC_LCLCTRL_USE_SIG_DETECT
- GRC_LOCAL_CTRL
- GRC_MAX_NR
- GRC_MDI_CTRL
- GRC_MEM_POWER_UP
- GRC_MISC_CFG
- GRC_MISC_CFG_BOARD_ID_5700
- GRC_MISC_CFG_BOARD_ID_5701
- GRC_MISC_CFG_BOARD_ID_5702FE
- GRC_MISC_CFG_BOARD_ID_5703
- GRC_MISC_CFG_BOARD_ID_5703S
- GRC_MISC_CFG_BOARD_ID_5704
- GRC_MISC_CFG_BOARD_ID_5704CIOBE
- GRC_MISC_CFG_BOARD_ID_5704_A2
- GRC_MISC_CFG_BOARD_ID_5788
- GRC_MISC_CFG_BOARD_ID_5788M
- GRC_MISC_CFG_BOARD_ID_AC91002A1
- GRC_MISC_CFG_BOARD_ID_MASK
- GRC_MISC_CFG_CORECLK_RESET
- GRC_MISC_CFG_EPHY_IDDQ
- GRC_MISC_CFG_KEEP_GPHY_POWER
- GRC_MISC_CFG_PRESCALAR_MASK
- GRC_MISC_CFG_PRESCALAR_SHIFT
- GRC_MODE
- GRC_MODE_4X_NIC_SEND_RINGS
- GRC_MODE_ALLOW_BAD_FRMS
- GRC_MODE_B2HRX_ENABLE
- GRC_MODE_BSWAP_DATA
- GRC_MODE_BSWAP_NONFRM_DATA
- GRC_MODE_BYTE_SWAP_B2HRX_DATA
- GRC_MODE_FORCE_PCI32BIT
- GRC_MODE_HOST_SENDBDS
- GRC_MODE_HOST_STACKUP
- GRC_MODE_HTX2B_ENABLE
- GRC_MODE_INCL_CRC
- GRC_MODE_IRQ_ON_DMA_ATTN
- GRC_MODE_IRQ_ON_FLOW_ATTN
- GRC_MODE_IRQ_ON_MAC_ATTN
- GRC_MODE_IRQ_ON_RX_CPU_ATTN
- GRC_MODE_IRQ_ON_TX_CPU_ATTN
- GRC_MODE_MCAST_FRM_ENABLE
- GRC_MODE_NOFRM_CRACKING
- GRC_MODE_NOIRQ_ON_RCV
- GRC_MODE_NOIRQ_ON_SENDS
- GRC_MODE_NO_RX_PHDR_CSUM
- GRC_MODE_NO_TX_PHDR_CSUM
- GRC_MODE_NVRAM_WR_ENABLE
- GRC_MODE_PCIE_DL_SEL
- GRC_MODE_PCIE_HI_1K_EN
- GRC_MODE_PCIE_PL_SEL
- GRC_MODE_PCIE_PORT_MASK
- GRC_MODE_PCIE_TL_SEL
- GRC_MODE_SPLITHDR
- GRC_MODE_TIME_SYNC_ENABLE
- GRC_MODE_UPD_ON_COAL
- GRC_MODE_WORD_SWAP_B2HRX_DATA
- GRC_MODE_WSWAP_DATA
- GRC_MODE_WSWAP_NONFRM_DATA
- GRC_RDY_OVRD
- GRC_REG_DBG_DWORD_ENABLE
- GRC_REG_DBG_FORCE_FRAME
- GRC_REG_DBG_FORCE_VALID
- GRC_REG_DBG_SELECT
- GRC_REG_DBG_SHIFT
- GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW
- GRC_REG_PROTECTION_OVERRIDE_WINDOW
- GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0
- GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1
- GRC_REG_TIMEOUT_ATTN_ACCESS_VALID
- GRC_REG_TIMEOUT_EN
- GRC_REG_TRACE_FIFO
- GRC_REG_TRACE_FIFO_VALID_DATA
- GRC_REMOTE_RX_CPU_ATTN
- GRC_REMOTE_TX_CPU_ATTN
- GRC_RX_CPU_DRIVER_EVENT
- GRC_RX_CPU_EVENT
- GRC_RX_CPU_SEM
- GRC_RX_TIMER_REF
- GRC_SEEPROM_DELAY
- GRC_STALLED_CYCLES_BE
- GRC_STALLED_CYCLES_FE
- GRC_TIMER
- GRC_TX_CPU_EVENT
- GRC_TX_CPU_SEM
- GRC_TX_TIMER_REF
- GRC_VCPU_EXT_CTRL
- GRC_VCPU_EXT_CTRL_DISABLE_WOL
- GRC_VCPU_EXT_CTRL_HALT_CPU
- GRDOM_FULL
- GRDOM_MASK
- GRDOM_MEDIA
- GRDOM_RENDER
- GRDOM_RESET_ENABLE
- GRDOM_RESET_STATUS
- GRD_CHK_ERR
- GRE6_FEATURES
- GREATER_1G
- GRED_DEF_PRIO
- GRED_RIO_MODE
- GRED_VQ_MASK
- GRED_VQ_RED_FLAGS
- GRED_WRED_MODE
- GREEN
- GREEN_ETHERNET
- GREEN_ETH_EN
- GREEN_LED
- GREEN_LED_2
- GREEN_LED_OE
- GREEN_LED_OFF
- GREEN_LED_ON
- GREEN_PC_ENA
- GREEN_SHIFT
- GREEN_START
- GREEN_STAT_RAM
- GREEN_X_INC
- GREEN_X_INC__ALIAS__
- GREEN_Y_INC
- GREFCLK
- GREFCLK_REFCLKPER_MASK
- GREFCLK_REFCLKPER_SHIFT
- GREFCLK_REF_CLK_MODE
- GREFCLK_SOF_CNT_WKUP_ALERT_MASK
- GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT
- GREG_BIFCFG
- GREG_BIFCFG_B64DIS
- GREG_BIFCFG_M66EN
- GREG_BIFCFG_SLOWCLK
- GREG_BIFDIAG
- GREG_BIFDIAG_BIFSM
- GREG_BIFDIAG_BURSTSM
- GREG_CFG
- GREG_CFG_64BIT
- GREG_CFG_BURST16
- GREG_CFG_BURST32
- GREG_CFG_BURST64
- GREG_CFG_BURSTMSK
- GREG_CFG_ENBUG2FIX
- GREG_CFG_IBURST
- GREG_CFG_PARITY
- GREG_CFG_RESV
- GREG_CFG_RONPAULBIT
- GREG_CFG_RXDMALIM
- GREG_CFG_TXDMALIM
- GREG_IACK
- GREG_IMASK
- GREG_IMASK_ACNTEXP
- GREG_IMASK_CCNTEXP
- GREG_IMASK_CVCNTEXP
- GREG_IMASK_DTIMEXP
- GREG_IMASK_ECNTEXP
- GREG_IMASK_EOPERR
- GREG_IMASK_FCNTEXP
- GREG_IMASK_GOTFRAME
- GREG_IMASK_HOSTTOTX
- GREG_IMASK_LCCNTEXP
- GREG_IMASK_LCNTEXP
- GREG_IMASK_MAXPKTERR
- GREG_IMASK_MIFIRQ
- GREG_IMASK_NCNTEXP
- GREG_IMASK_NORXD
- GREG_IMASK_RCNTEXP
- GREG_IMASK_RFIFOVF
- GREG_IMASK_RXERR
- GREG_IMASK_RXLATERR
- GREG_IMASK_RXPERR
- GREG_IMASK_RXTERR
- GREG_IMASK_RXTOHOST
- GREG_IMASK_SENTFRAME
- GREG_IMASK_SLVERR
- GREG_IMASK_SLVPERR
- GREG_IMASK_STSTERR
- GREG_IMASK_TFIFO_UND
- GREG_IMASK_TXALL
- GREG_IMASK_TXEACK
- GREG_IMASK_TXLERR
- GREG_IMASK_TXPERR
- GREG_IMASK_TXTERR
- GREG_PCIEMASK
- GREG_PCIESTAT
- GREG_PCIESTAT_BADACK
- GREG_PCIESTAT_DTRTO
- GREG_PCIESTAT_OTHER
- GREG_REG_SIZE
- GREG_RESET_ALL
- GREG_RESET_ERX
- GREG_RESET_ETX
- GREG_SEBSTATE
- GREG_SEBSTATE_ARB
- GREG_SEBSTATE_RXWON
- GREG_STAT
- GREG_STAT2
- GREG_STAT_ABNORMAL
- GREG_STAT_ACNTEXP
- GREG_STAT_CCNTEXP
- GREG_STAT_CVCNTEXP
- GREG_STAT_DTIMEXP
- GREG_STAT_ECNTEXP
- GREG_STAT_EOPERR
- GREG_STAT_ERRORS
- GREG_STAT_FCNTEXP
- GREG_STAT_GOTFRAME
- GREG_STAT_HOSTTOTX
- GREG_STAT_LCCNTEXP
- GREG_STAT_LCNTEXP
- GREG_STAT_MAC
- GREG_STAT_MAXPKTERR
- GREG_STAT_MIF
- GREG_STAT_MIFIRQ
- GREG_STAT_NAPI
- GREG_STAT_NCNTEXP
- GREG_STAT_NORXD
- GREG_STAT_PCIERR
- GREG_STAT_PCS
- GREG_STAT_RCNTEXP
- GREG_STAT_RFIFOVF
- GREG_STAT_RXDONE
- GREG_STAT_RXERR
- GREG_STAT_RXLATERR
- GREG_STAT_RXMAC
- GREG_STAT_RXNOBUF
- GREG_STAT_RXPERR
- GREG_STAT_RXTAGERR
- GREG_STAT_RXTERR
- GREG_STAT_RXTOHOST
- GREG_STAT_SENTFRAME
- GREG_STAT_SLVERR
- GREG_STAT_SLVPERR
- GREG_STAT_STSTERR
- GREG_STAT_TFIFO_UND
- GREG_STAT_TXALL
- GREG_STAT_TXDONE
- GREG_STAT_TXEACK
- GREG_STAT_TXINTME
- GREG_STAT_TXLERR
- GREG_STAT_TXMAC
- GREG_STAT_TXNR
- GREG_STAT_TXNR_SHIFT
- GREG_STAT_TXPERR
- GREG_STAT_TXTERR
- GREG_SWRESET
- GREG_SWRST
- GREG_SWRST_CACHESIZE
- GREG_SWRST_CACHE_SHIFT
- GREG_SWRST_RSTOUT
- GREG_SWRST_RXRST
- GREG_SWRST_TXRST
- GREPROTO_CISCO
- GREPROTO_MAX
- GREPROTO_PPTP
- GRER
- GRER_OFFSET
- GRETH_BD_EN
- GRETH_BD_IE
- GRETH_BD_LEN
- GRETH_BD_WR
- GRETH_CTRL_DISDUPLEX
- GRETH_CTRL_FD
- GRETH_CTRL_GB
- GRETH_CTRL_MCEN
- GRETH_CTRL_PR
- GRETH_CTRL_PSTATIEN
- GRETH_CTRL_SP
- GRETH_DEF_MSG_ENABLE
- GRETH_H
- GRETH_INT_RE
- GRETH_INT_RX
- GRETH_INT_TE
- GRETH_INT_TX
- GRETH_MII_BUSY
- GRETH_MII_NVALID
- GRETH_REGANDIN
- GRETH_REGLOAD
- GRETH_REGORIN
- GRETH_REGSAVE
- GRETH_RESET
- GRETH_RXBD_ERR_AE
- GRETH_RXBD_ERR_CRC
- GRETH_RXBD_ERR_FT
- GRETH_RXBD_ERR_LE
- GRETH_RXBD_ERR_OE
- GRETH_RXBD_IP
- GRETH_RXBD_IP_CSERR
- GRETH_RXBD_IP_FRAG
- GRETH_RXBD_MCAST
- GRETH_RXBD_NUM
- GRETH_RXBD_NUM_MASK
- GRETH_RXBD_STATUS
- GRETH_RXBD_TCP
- GRETH_RXBD_TCP_CSERR
- GRETH_RXBD_UDP
- GRETH_RXBD_UDP_CSERR
- GRETH_RXEN
- GRETH_RXI
- GRETH_RX_BUF_PAGE_NUM
- GRETH_RX_BUF_PPGAE
- GRETH_RX_BUF_SIZE
- GRETH_STATUS_PHYSTAT
- GRETH_TXBD_CSALL
- GRETH_TXBD_ERR_AL
- GRETH_TXBD_ERR_LC
- GRETH_TXBD_ERR_UE
- GRETH_TXBD_IPCS
- GRETH_TXBD_MORE
- GRETH_TXBD_NUM
- GRETH_TXBD_NUM_MASK
- GRETH_TXBD_STATUS
- GRETH_TXBD_TCPCS
- GRETH_TXBD_UDPCS
- GRETH_TXEN
- GRETH_TXI
- GRETH_TX_BUF_PAGE_NUM
- GRETH_TX_BUF_PPGAE
- GRETH_TX_BUF_SIZE
- GREYBUS_CLASS_AUDIO
- GREYBUS_CLASS_BOOTROM
- GREYBUS_CLASS_BRIDGED_PHY
- GREYBUS_CLASS_CAMERA
- GREYBUS_CLASS_CONTROL
- GREYBUS_CLASS_DISPLAY
- GREYBUS_CLASS_FW_MANAGEMENT
- GREYBUS_CLASS_HID
- GREYBUS_CLASS_LIGHTS
- GREYBUS_CLASS_LOG
- GREYBUS_CLASS_LOOPBACK
- GREYBUS_CLASS_POWER_SUPPLY
- GREYBUS_CLASS_RAW
- GREYBUS_CLASS_SENSOR
- GREYBUS_CLASS_VENDOR
- GREYBUS_CLASS_VIBRATOR
- GREYBUS_DEVICE
- GREYBUS_DEVICE_CLASS
- GREYBUS_ID_MATCH_CLASS
- GREYBUS_ID_MATCH_DEVICE
- GREYBUS_ID_MATCH_PRODUCT
- GREYBUS_ID_MATCH_VENDOR
- GREYBUS_INTERFACE_FEATURE_TIMESYNC
- GREYBUS_PROTOCOL_AUDIO_DATA
- GREYBUS_PROTOCOL_AUDIO_MGMT
- GREYBUS_PROTOCOL_AUTHENTICATION
- GREYBUS_PROTOCOL_BOOTROM
- GREYBUS_PROTOCOL_CAMERA_DATA
- GREYBUS_PROTOCOL_CAMERA_MGMT
- GREYBUS_PROTOCOL_CONTROL
- GREYBUS_PROTOCOL_DISPLAY
- GREYBUS_PROTOCOL_FW_DOWNLOAD
- GREYBUS_PROTOCOL_FW_MANAGEMENT
- GREYBUS_PROTOCOL_GPIO
- GREYBUS_PROTOCOL_HID
- GREYBUS_PROTOCOL_I2C
- GREYBUS_PROTOCOL_LIGHTS
- GREYBUS_PROTOCOL_LOG
- GREYBUS_PROTOCOL_LOOPBACK
- GREYBUS_PROTOCOL_POWER_SUPPLY
- GREYBUS_PROTOCOL_PWM
- GREYBUS_PROTOCOL_RAW
- GREYBUS_PROTOCOL_SDIO
- GREYBUS_PROTOCOL_SENSOR
- GREYBUS_PROTOCOL_SPI
- GREYBUS_PROTOCOL_SVC
- GREYBUS_PROTOCOL_UART
- GREYBUS_PROTOCOL_USB
- GREYBUS_PROTOCOL_VENDOR
- GREYBUS_PROTOCOL_VIBRATOR
- GREYBUS_TYPE_BUNDLE
- GREYBUS_TYPE_CPORT
- GREYBUS_TYPE_INTERFACE
- GREYBUS_TYPE_INVALID
- GREYBUS_TYPE_STRING
- GREYBUS_VERSION_MAJOR
- GREYBUS_VERSION_MINOR
- GRE_ACK
- GRE_CSUM
- GRE_CT_MAX
- GRE_CT_REPLIED
- GRE_CT_UNREPLIED
- GRE_FEATURES
- GRE_FLAGS
- GRE_HEADER_SECTION
- GRE_IP_PROTO_MAX
- GRE_IRB
- GRE_IS_ACK
- GRE_IS_CSUM
- GRE_IS_KEY
- GRE_IS_REC
- GRE_IS_ROUTING
- GRE_IS_SEQ
- GRE_IS_STRICT
- GRE_KEY
- GRE_MODE_CHECKSUM
- GRE_MODE_KEY
- GRE_MODE_RESERVED
- GRE_MODE_SEQUENCE
- GRE_PPTP_KEY_MASK
- GRE_PROTO_PPP
- GRE_REC
- GRE_ROUTING
- GRE_SEQ
- GRE_STRICT
- GRE_VERSION
- GRE_VERSION_0
- GRE_VERSION_1
- GRF5101_ANTENNA
- GRFBOBCAT
- GRFCATSEYE
- GRFDAVINCI
- GRFFIREEYE
- GRFGATOR
- GRFHYPERION
- GRFRBOX
- GRF_ACODEC_SEL
- GRF_BIT
- GRF_CLR_BIT
- GRF_CON_TSADC_CH_INV
- GRF_EDP_PHY_SIDDQ_HIWORD_MASK
- GRF_EDP_PHY_SIDDQ_OFF
- GRF_EDP_PHY_SIDDQ_ON
- GRF_EDP_REF_CLK_SEL_INTER
- GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
- GRF_EMMCPHY_CON0
- GRF_EMMCPHY_CON1
- GRF_EMMCPHY_CON2
- GRF_EMMCPHY_CON3
- GRF_EMMCPHY_CON4
- GRF_EMMCPHY_CON5
- GRF_EMMCPHY_CON6
- GRF_EMMCPHY_STATUS
- GRF_SARADC_TESTBIT
- GRF_SARADC_TESTBIT_ON
- GRF_SIDDQ
- GRF_SOC_CON0
- GRF_SOC_CON12
- GRF_SOC_CON26
- GRF_SOC_CON9
- GRF_TSADC_TESTBIT_H
- GRF_TSADC_TESTBIT_H_ON
- GRF_TSADC_TESTBIT_L
- GRF_TSADC_VCM_EN_H
- GRF_TSADC_VCM_EN_L
- GRF_UOC0_CON0
- GRF_UOC1_CON0
- GRF_UOC2_CON0
- GRGPIO_BYPASS
- GRGPIO_DATA
- GRGPIO_DIR
- GRGPIO_IEDGE
- GRGPIO_IMAP_BASE
- GRGPIO_IMASK
- GRGPIO_IPOL
- GRGPIO_MAX_NGPIO
- GRGPIO_OUTPUT
- GRHL_CMD
- GRIP_INIT_DELAY
- GRIP_LENGTH_GPP
- GRIP_LENGTH_XT
- GRIP_MAX_BITS_XT
- GRIP_MAX_CHUNKS_XT
- GRIP_MAX_PORTS
- GRIP_MODE_BD
- GRIP_MODE_C64
- GRIP_MODE_DC
- GRIP_MODE_GP
- GRIP_MODE_GPP
- GRIP_MODE_NONE
- GRIP_MODE_RESET
- GRIP_MODE_XT
- GRIP_STROBE_GPP
- GRIP_STROBE_XT
- GRLIB_VERSION_MASK
- GRL_ABIST_CTRL0
- GRL_ABIST_CTRL1
- GRL_ACP_ISRC_CTRL
- GRL_AOUT_CFG
- GRL_AUDIO_CFG
- GRL_CFG0
- GRL_CFG1
- GRL_CFG2
- GRL_CFG3
- GRL_CFG4
- GRL_CFG5
- GRL_CH_SW0
- GRL_CH_SW1
- GRL_CH_SW2
- GRL_CH_SWAP
- GRL_CTRL
- GRL_CTS_CTRL
- GRL_DIVN
- GRL_I2S_C_STA0
- GRL_I2S_C_STA1
- GRL_I2S_C_STA2
- GRL_I2S_C_STA3
- GRL_I2S_C_STA4
- GRL_I2S_UV
- GRL_IFM_PORT
- GRL_INFOFRM_LNG
- GRL_INFOFRM_TYPE
- GRL_INFOFRM_VER
- GRL_INT
- GRL_INT_MASK
- GRL_L_STATUS_0
- GRL_L_STATUS_1
- GRL_L_STATUS_10
- GRL_L_STATUS_11
- GRL_L_STATUS_12
- GRL_L_STATUS_13
- GRL_L_STATUS_14
- GRL_L_STATUS_15
- GRL_L_STATUS_16
- GRL_L_STATUS_17
- GRL_L_STATUS_18
- GRL_L_STATUS_19
- GRL_L_STATUS_2
- GRL_L_STATUS_20
- GRL_L_STATUS_21
- GRL_L_STATUS_22
- GRL_L_STATUS_23
- GRL_L_STATUS_3
- GRL_L_STATUS_4
- GRL_L_STATUS_5
- GRL_L_STATUS_6
- GRL_L_STATUS_7
- GRL_L_STATUS_8
- GRL_L_STATUS_9
- GRL_MIX_CTRL
- GRL_NCTS
- GRL_R_STATUS_0
- GRL_R_STATUS_1
- GRL_R_STATUS_10
- GRL_R_STATUS_11
- GRL_R_STATUS_12
- GRL_R_STATUS_13
- GRL_R_STATUS_14
- GRL_R_STATUS_15
- GRL_R_STATUS_16
- GRL_R_STATUS_17
- GRL_R_STATUS_18
- GRL_R_STATUS_19
- GRL_R_STATUS_2
- GRL_R_STATUS_20
- GRL_R_STATUS_21
- GRL_R_STATUS_22
- GRL_R_STATUS_23
- GRL_R_STATUS_3
- GRL_R_STATUS_4
- GRL_R_STATUS_5
- GRL_R_STATUS_6
- GRL_R_STATUS_7
- GRL_R_STATUS_8
- GRL_R_STATUS_9
- GRL_SHIFT_L1
- GRL_SHIFT_R2
- GRL_STATUS
- GRMMASK_GMA_MASK
- GRND_NONBLOCK
- GRND_RANDOM
- GROFFSET
- GROSS_ERR_INT
- GROUP
- GROUP0_IRQ_BASE
- GROUP0_NR_IRQS
- GROUP1_IRQ_BASE
- GROUP1_NR_IRQS
- GROUP2_IRQ_BASE
- GROUP3_IRQ_BASE
- GROUP4_IRQ_BASE
- GROUPED_PARAMETER_HOLD
- GROUPS_L2_COHERENT
- GROUP_0
- GROUP_1
- GROUP_1_FIFO
- GROUP_1_FIRST_CLEAR
- GROUP_1_FLAGS
- GROUP_1_SECOND_CLEAR
- GROUP_2
- GROUP_2G
- GROUP_2_FIFO
- GROUP_2_FIRST_CLEAR
- GROUP_2_FLAGS
- GROUP_2_SECOND_CLEAR
- GROUP_3
- GROUP_5G
- GROUP_A
- GROUP_ADDR
- GROUP_ADDRESS
- GROUP_ADDR_BIT
- GROUP_B
- GROUP_DECL
- GROUP_DIRECTION
- GROUP_FILTER_SIZE
- GROUP_H
- GROUP_H_SIZE
- GROUP_IDX
- GROUP_ID_IS_SU_MIMO
- GROUP_KEY
- GROUP_MASK
- GROUP_NAME_MAX
- GROUP_ORDINALS
- GROUP_PROTOCOL
- GROUP_QUOTA_SYSTEM_INODE
- GROUP_SECINFO
- GROUP_SHIFT
- GROUP_SIZE
- GROUP_STATUS
- GROUP_SYM
- GROUP_TABLE_COUNT
- GROUP_TEI
- GROUP_USAGE
- GROUP_WCID
- GRO_CONSUMED
- GRO_DROP
- GRO_HASH_BUCKETS
- GRO_HELD
- GRO_MAX_HEAD
- GRO_MERGED
- GRO_MERGED_FREE
- GRO_NORMAL
- GRO_RECURSION_LIMIT
- GRP
- GRPBASEA
- GRPBASEA_ADDR
- GRPBASEB
- GRPBASEB_ADDR
- GRPBASEC
- GRPBASEC_ADDR
- GRPBASED
- GRPBASED_ADDR
- GRPBASE_GBA_MASK
- GRPBASE_V
- GRPCI1_DEBUG_CFGACCESS
- GRPCI2_DEBUG_CFGACCESS
- GRPH2_BUFFER_CNTL
- GRPH8_DATA__GRPH_DATA_MASK
- GRPH8_DATA__GRPH_DATA__SHIFT
- GRPH8_IDX__GRPH_IDX_MASK
- GRPH8_IDX__GRPH_IDX__SHIFT
- GRPH_ALPHA_CROSSBAR
- GRPH_ALPHA_SEL_A
- GRPH_ALPHA_SEL_B
- GRPH_ALPHA_SEL_G
- GRPH_ALPHA_SEL_R
- GRPH_ARRAY_1D_TILED_THIN1
- GRPH_ARRAY_2D_TILED_THIN1
- GRPH_ARRAY_LINEAR_ALIGNED
- GRPH_ARRAY_LINEAR_GENERAL
- GRPH_ARRAY_MODE
- GRPH_BANK_HEIGHT
- GRPH_BANK_WIDTH
- GRPH_BLUE_CROSSBAR
- GRPH_BLUE_SEL_A
- GRPH_BLUE_SEL_B
- GRPH_BLUE_SEL_G
- GRPH_BLUE_SEL_R
- GRPH_BUFFER_CNTL
- GRPH_COLOR_MATRIX_HW_DEFAULT
- GRPH_COLOR_MATRIX_SW
- GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK
- GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT
- GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK
- GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT
- GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK
- GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT
- GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
- GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
- GRPH_CONTROL__GRPH_ARRAY_MODE_MASK
- GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
- GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK
- GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT
- GRPH_CONTROL__GRPH_BANK_WIDTH_MASK
- GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT
- GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
- GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
- GRPH_CONTROL__GRPH_DEPTH_MASK
- GRPH_CONTROL__GRPH_DEPTH__SHIFT
- GRPH_CONTROL__GRPH_FORMAT_MASK
- GRPH_CONTROL__GRPH_FORMAT__SHIFT
- GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK
- GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT
- GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK
- GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT
- GRPH_CONTROL__GRPH_NUM_BANKS_MASK
- GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
- GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK
- GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
- GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
- GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
- GRPH_CONTROL__GRPH_TILE_SPLIT_MASK
- GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT
- GRPH_CONTROL__GRPH_Z_MASK
- GRPH_CONTROL__GRPH_Z__SHIFT
- GRPH_DEPTH
- GRPH_DEPTH_16BPP
- GRPH_DEPTH_32BPP
- GRPH_DEPTH_8BPP
- GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
- GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
- GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
- GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
- GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
- GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
- GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
- GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
- GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
- GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
- GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
- GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
- GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
- GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
- GRPH_ENABLE__GRPH_ENABLE_MASK
- GRPH_ENABLE__GRPH_ENABLE__SHIFT
- GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL_MASK
- GRPH_ENABLE__GRPH_KEYER_ALPHA_SEL__SHIFT
- GRPH_ENDIAN_8IN16
- GRPH_ENDIAN_8IN32
- GRPH_ENDIAN_8IN64
- GRPH_ENDIAN_NONE
- GRPH_ENDIAN_SWAP
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN_MASK
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_IMMEDIATE_EN__SHIFT
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
- GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
- GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN_MASK
- GRPH_FLIP_CONTROL__GRPH_XDMA_SUPER_AA_EN__SHIFT
- GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
- GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
- GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
- GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
- GRPH_FORMAT
- GRPH_FORMAT_32BPP_DIG
- GRPH_FORMAT_8B_ARGB2101010
- GRPH_FORMAT_8B_BGRA1010102
- GRPH_FORMAT_AI88
- GRPH_FORMAT_ARGB1555
- GRPH_FORMAT_ARGB2101010
- GRPH_FORMAT_ARGB4444
- GRPH_FORMAT_ARGB565
- GRPH_FORMAT_ARGB8888
- GRPH_FORMAT_BGR101111
- GRPH_FORMAT_BGRA1010102
- GRPH_FORMAT_BGRA5551
- GRPH_FORMAT_INDEXED
- GRPH_FORMAT_MONO16
- GRPH_FORMAT_RGB111110
- GRPH_GREEN_CROSSBAR
- GRPH_GREEN_SEL_A
- GRPH_GREEN_SEL_B
- GRPH_GREEN_SEL_G
- GRPH_GREEN_SEL_R
- GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
- GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
- GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
- GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
- GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
- GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
- GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
- GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
- GRPH_INT_CONTROL
- GRPH_INT_STATUS
- GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK
- GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT
- GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK
- GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT
- GRPH_MACRO_TILE_ASPECT
- GRPH_NUM_BANKS
- GRPH_PFLIP_INT_CLEAR
- GRPH_PFLIP_INT_MASK
- GRPH_PFLIP_INT_OCCURRED
- GRPH_PFLIP_INT_TYPE
- GRPH_PIPE_CONFIG
- GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT_MASK
- GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT__SHIFT
- GRPH_PITCH__GRPH_PITCH_MASK
- GRPH_PITCH__GRPH_PITCH__SHIFT
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK
- GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT
- GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK
- GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT
- GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
- GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT
- GRPH_RED_CROSSBAR
- GRPH_RED_SEL_A
- GRPH_RED_SEL_B
- GRPH_RED_SEL_G
- GRPH_RED_SEL_R
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK
- GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT
- GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK
- GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT
- GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
- GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT
- GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
- GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
- GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
- GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
- GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
- GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK
- GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT
- GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK
- GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN_MASK
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EN__SHIFT
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_MASK
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED__SHIFT
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT_MASK
- GRPH_SURFACE_COUNTER_CONTROL__GRPH_SURFACE_COUNTER_EVENT_SELECT__SHIFT
- GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX_MASK
- GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MAX__SHIFT
- GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN_MASK
- GRPH_SURFACE_COUNTER_OUTPUT__GRPH_SURFACE_COUNTER_MIN__SHIFT
- GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK
- GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT
- GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK
- GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT
- GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK
- GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT
- GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
- GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
- GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
- GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
- GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
- GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
- GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
- GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
- GRPH_TILE_SPLIT
- GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
- GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
- GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
- GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
- GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
- GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
- GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
- GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
- GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
- GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
- GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
- GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
- GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
- GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
- GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK
- GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT
- GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
- GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT
- GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT
- GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK
- GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT
- GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK
- GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT
- GRPH_X_END__GRPH_X_END_MASK
- GRPH_X_END__GRPH_X_END__SHIFT
- GRPH_X_START__GRPH_X_START_MASK
- GRPH_X_START__GRPH_X_START__SHIFT
- GRPH_Y_END__GRPH_Y_END_MASK
- GRPH_Y_END__GRPH_Y_END__SHIFT
- GRPH_Y_START__GRPH_Y_START_MASK
- GRPH_Y_START__GRPH_Y_START__SHIFT
- GRPL_CMD
- GRPMASKA
- GRPMASKA_ADDR
- GRPMASKB
- GRPMASKB_ADDR
- GRPMASKC
- GRPMASKC_ADDR
- GRPMASKD
- GRPMASKD_ADDR
- GRPQUOTA
- GRP_10_MAP
- GRP_32_MAP
- GRP_54_MAP
- GRP_76_MAP
- GRP_ACK_MSG
- GRP_ADV_MSG
- GRP_CFG_REG
- GRP_EMPRESS
- GRP_G
- GRP_ID_CSIS
- GRP_ID_FIMC
- GRP_ID_FIMC_IS
- GRP_ID_FIMC_IS_SENSOR
- GRP_ID_FLITE
- GRP_ID_SENSOR
- GRP_ID_WRITEBACK
- GRP_INT_STAT
- GRP_JOIN_MSG
- GRP_LEAVE_MSG
- GRP_MUX
- GRP_RECLAIM_MSG
- GRP_REMIT_MSG
- GRR_GSR
- GRR_QMU
- GRST
- GRST1
- GRSTCTL
- GRSTCTL_AHBIDLE
- GRSTCTL_CSFTRST
- GRSTCTL_DMAREQ
- GRSTCTL_FRMCNTRRST
- GRSTCTL_HSFTRST
- GRSTCTL_IN_TKNQ_FLSH
- GRSTCTL_RXFFLSH
- GRSTCTL_TXFFLSH
- GRSTCTL_TXFNUM
- GRSTCTL_TXFNUM_LIMIT
- GRSTCTL_TXFNUM_MASK
- GRSTCTL_TXFNUM_SHIFT
- GRTS_DEFAULT_PRESSURE_MIN
- GRTS_MAX_POS_MASK
- GRUASID
- GRUBASE
- GRUMAXINVAL
- GRUREGION
- GRUSBHC_HCIVERSION
- GRU_ASSIGN_DELAY
- GRU_BASENAME
- GRU_CACHE_CNFG
- GRU_CACHE_LINE_BYTES
- GRU_CBE_BASE
- GRU_CBR_AU
- GRU_CBR_AU_SIZE
- GRU_CB_BASE
- GRU_CB_COUNT_TO_AU
- GRU_CB_EXOPC_MASK
- GRU_CB_EXOPC_SHFT
- GRU_CB_IAA0_MASK
- GRU_CB_IAA0_SHFT
- GRU_CB_IAA1_MASK
- GRU_CB_IAA1_SHFT
- GRU_CB_ICMD_MASK
- GRU_CB_ICMD_SHFT
- GRU_CB_IMA_MASK
- GRU_CB_IMA_SHFT
- GRU_CB_LIMIT
- GRU_CB_OPC_MASK
- GRU_CB_OPC_SHFT
- GRU_CB_XTYPE_MASK
- GRU_CB_XTYPE_SHFT
- GRU_CCH_BASE
- GRU_CHIPLETS_PER_BLADE
- GRU_CHIPLETS_PER_HUB
- GRU_CREATE_CONTEXT
- GRU_DINDEX
- GRU_DRIVER_ID_STR
- GRU_DRIVER_VERSION_STR
- GRU_DSR_AU
- GRU_DSR_AU_BYTES
- GRU_DSR_AU_CL
- GRU_DSR_CL
- GRU_DS_BASE
- GRU_DS_BYTES_TO_AU
- GRU_DS_LIMIT
- GRU_DUMP_CHIPLET_STATE
- GRU_DUMP_MAGIC
- GRU_EXC_STR_SIZE
- GRU_FULLNAME
- GRU_GET_CONFIG_INFO
- GRU_GET_GSEG_STATISTICS
- GRU_GSEG0_BASE
- GRU_GSEG_PAGESIZE
- GRU_GSEG_STRIDE
- GRU_HANDLE_BYTES
- GRU_HANDLE_STRIDE
- GRU_HUBS_PER_BLADE
- GRU_IDEF2_MASK
- GRU_IDEF2_SHFT
- GRU_INT_CLEAR
- GRU_INT_EDGE
- GRU_INT_HILO
- GRU_INT_MASK
- GRU_INT_REQ
- GRU_INT_REQ_BITS
- GRU_IOCTL_NUM
- GRU_ISTATUS_MASK
- GRU_ISTATUS_SHFT
- GRU_KTEST
- GRU_LED
- GRU_MAX_BLADES
- GRU_MAX_GRUS
- GRU_MAX_OPEN_CONTEXTS
- GRU_MCS_BASE
- GRU_NUM_CB
- GRU_NUM_CBE
- GRU_NUM_CCH
- GRU_NUM_DSR_BYTES
- GRU_NUM_KERNEL_CBR
- GRU_NUM_KERNEL_DSR_BYTES
- GRU_NUM_KERNEL_DSR_CL
- GRU_NUM_TFH
- GRU_NUM_TFM
- GRU_NUM_TGH
- GRU_NUM_USER_CBR
- GRU_NUM_USER_DSR_BYTES
- GRU_OPERATION_TIMEOUT
- GRU_OPT_MISS_DEFAULT
- GRU_OPT_MISS_FMM_INTR
- GRU_OPT_MISS_FMM_POLL
- GRU_OPT_MISS_MASK
- GRU_OPT_MISS_USER_POLL
- GRU_PADDR_SHIFT
- GRU_PAGESIZE
- GRU_RESET
- GRU_SCR
- GRU_SET_CONTEXT_OPTION
- GRU_SIZE
- GRU_SIZEAVAIL
- GRU_STEAL_DELAY
- GRU_TFH_BASE
- GRU_TFM_BASE
- GRU_TGH_BASE
- GRU_USER_CALL_OS
- GRU_USER_FLUSH_TLB
- GRU_USER_GET_EXCEPTION_DETAIL
- GRU_USER_UNLOAD_CONTEXT
- GRX
- GRXFSIZ
- GRXFSIZ_DEPTH_MASK
- GRXFSIZ_DEPTH_SHIFT
- GRXSTSP
- GRXSTSR
- GRXSTS_BYTECNT_MASK
- GRXSTS_BYTECNT_SHIFT
- GRXSTS_DPID_MASK
- GRXSTS_DPID_SHIFT
- GRXSTS_EPNUM_MASK
- GRXSTS_EPNUM_SHIFT
- GRXSTS_FN_MASK
- GRXSTS_FN_SHIFT
- GRXSTS_HCHNUM_MASK
- GRXSTS_HCHNUM_SHIFT
- GRXSTS_PKTSTS_DATATOGGLEERR
- GRXSTS_PKTSTS_GLOBALOUTNAK
- GRXSTS_PKTSTS_HCHHALTED
- GRXSTS_PKTSTS_HCHIN
- GRXSTS_PKTSTS_HCHIN_XFER_COMP
- GRXSTS_PKTSTS_MASK
- GRXSTS_PKTSTS_OUTDONE
- GRXSTS_PKTSTS_OUTRX
- GRXSTS_PKTSTS_SETUPDONE
- GRXSTS_PKTSTS_SETUPRX
- GRXSTS_PKTSTS_SHIFT
- GRXTHRCFG
- GR_BUFFER_SIZE
- GR_CHIP_ID
- GR_CONTROL_DH
- GR_CONTROL_EP
- GR_CONTROL_FI
- GR_CONTROL_RW
- GR_CONTROL_SI
- GR_CONTROL_SP
- GR_CONTROL_SU
- GR_CONTROL_TM
- GR_CONTROL_TS_MASK
- GR_CONTROL_TS_POS
- GR_CONTROL_UA_MASK
- GR_CONTROL_UA_POS
- GR_CONTROL_UI
- GR_CONTROL_VI
- GR_DATA
- GR_DESC_DMAADDR_MASK
- GR_DESC_IN_CTRL_EN
- GR_DESC_IN_CTRL_IE
- GR_DESC_IN_CTRL_LEN_MASK
- GR_DESC_IN_CTRL_ML
- GR_DESC_IN_CTRL_MO
- GR_DESC_IN_CTRL_NX
- GR_DESC_IN_CTRL_PI
- GR_DESC_OUT_CTRL_EN
- GR_DESC_OUT_CTRL_IE
- GR_DESC_OUT_CTRL_LEN_MASK
- GR_DESC_OUT_CTRL_NX
- GR_DESC_OUT_CTRL_SE
- GR_DMACTRL_AD
- GR_DMACTRL_AE
- GR_DMACTRL_AI
- GR_DMACTRL_DA
- GR_DMACTRL_IE
- GR_EP0_DISCONNECT
- GR_EP0_IDATA
- GR_EP0_ISTATUS
- GR_EP0_ODATA
- GR_EP0_OSTATUS
- GR_EP0_SETUP
- GR_EP0_STALL
- GR_EP0_SUSPEND
- GR_EPCTRL_BUFSZ_MASK
- GR_EPCTRL_BUFSZ_POS
- GR_EPCTRL_BUFSZ_SCALER
- GR_EPCTRL_CB
- GR_EPCTRL_CS
- GR_EPCTRL_ED
- GR_EPCTRL_EH
- GR_EPCTRL_EV
- GR_EPCTRL_MAXPL_MASK
- GR_EPCTRL_MAXPL_POS
- GR_EPCTRL_NT_MASK
- GR_EPCTRL_NT_POS
- GR_EPCTRL_PI
- GR_EPCTRL_TT_MASK
- GR_EPCTRL_TT_POS
- GR_EPSTAT_B0
- GR_EPSTAT_B0CNT_MASK
- GR_EPSTAT_B0CNT_POS
- GR_EPSTAT_B1
- GR_EPSTAT_B1CNT_MASK
- GR_EPSTAT_B1CNT_POS
- GR_EPSTAT_BS
- GR_EPSTAT_PR
- GR_EPSTAT_PT
- GR_INDEX
- GR_IN_SW
- GR_MAXEP
- GR_MODE_MASK
- GR_OFFS
- GR_SNAP_I7
- GR_SNAP_O7
- GR_SNAP_PAD1
- GR_SNAP_RPC
- GR_SNAP_THREAD
- GR_SNAP_TNPC
- GR_SNAP_TPC
- GR_SNAP_TSTATE
- GR_SPEED
- GR_SPEED_STR
- GR_STATUS_AF_MASK
- GR_STATUS_AF_POS
- GR_STATUS_DM
- GR_STATUS_FN_MASK
- GR_STATUS_FN_POS
- GR_STATUS_NEPI_MASK
- GR_STATUS_NEPI_POS
- GR_STATUS_NEPO_MASK
- GR_STATUS_NEPO_POS
- GR_STATUS_SP
- GR_STATUS_SU
- GR_STATUS_UR
- GR_STATUS_VB
- GS
- GSADR
- GSADR_SRCSTRIDE
- GSADR_XSTART
- GSADR_YSTART
- GSBI10_H_CLK
- GSBI10_QUP_CLK
- GSBI10_QUP_SRC
- GSBI10_RESET
- GSBI10_SIM_CLK
- GSBI10_UART_CLK
- GSBI10_UART_SRC
- GSBI11_H_CLK
- GSBI11_QUP_CLK
- GSBI11_QUP_SRC
- GSBI11_RESET
- GSBI11_SIM_CLK
- GSBI11_UART_CLK
- GSBI11_UART_SRC
- GSBI12_H_CLK
- GSBI12_QUP_CLK
- GSBI12_QUP_SRC
- GSBI12_RESET
- GSBI12_SIM_CLK
- GSBI12_UART_CLK
- GSBI12_UART_SRC
- GSBI1_H_CLK
- GSBI1_QUP_CLK
- GSBI1_QUP_SRC
- GSBI1_RESET
- GSBI1_SIM_CLK
- GSBI1_UART_CLK
- GSBI1_UART_SRC
- GSBI2_H_CLK
- GSBI2_QUP_CLK
- GSBI2_QUP_SRC
- GSBI2_RESET
- GSBI2_SIM_CLK
- GSBI2_UART_CLK
- GSBI2_UART_SRC
- GSBI3_H_CLK
- GSBI3_QUP_CLK
- GSBI3_QUP_SRC
- GSBI3_RESET
- GSBI3_SIM_CLK
- GSBI3_UART_CLK
- GSBI3_UART_SRC
- GSBI4_H_CLK
- GSBI4_QUP_CLK
- GSBI4_QUP_SRC
- GSBI4_RESET
- GSBI4_SIM_CLK
- GSBI4_UART_CLK
- GSBI4_UART_SRC
- GSBI5_H_CLK
- GSBI5_QUP_CLK
- GSBI5_QUP_SRC
- GSBI5_RESET
- GSBI5_SIM_CLK
- GSBI5_UART_CLK
- GSBI5_UART_SRC
- GSBI6_H_CLK
- GSBI6_QUP_CLK
- GSBI6_QUP_SRC
- GSBI6_RESET
- GSBI6_SIM_CLK
- GSBI6_UART_CLK
- GSBI6_UART_SRC
- GSBI7_H_CLK
- GSBI7_QUP_CLK
- GSBI7_QUP_SRC
- GSBI7_RESET
- GSBI7_SIM_CLK
- GSBI7_UART_CLK
- GSBI7_UART_SRC
- GSBI8_H_CLK
- GSBI8_QUP_CLK
- GSBI8_QUP_SRC
- GSBI8_RESET
- GSBI8_SIM_CLK
- GSBI8_UART_CLK
- GSBI8_UART_SRC
- GSBI9_H_CLK
- GSBI9_QUP_CLK
- GSBI9_QUP_SRC
- GSBI9_RESET
- GSBI9_SIM_CLK
- GSBI9_UART_CLK
- GSBI9_UART_SRC
- GSBI_COMMON_SIM_SRC
- GSBI_CRCI_QUP
- GSBI_CRCI_UART
- GSBI_CTRL_REG
- GSBI_PROTOCOL_SHIFT
- GSBI_PROT_I2C
- GSBI_PROT_I2C_UART
- GSBI_PROT_I2C_UIM
- GSBI_PROT_IDLE
- GSBI_PROT_SPI
- GSBI_PROT_UART_W_FC
- GSBI_PROT_UIM
- GSCADR
- GSCADR_BLEND_CUR
- GSCADR_BLEND_GFX
- GSCADR_BLEND_GLOB
- GSCADR_BLEND_INV
- GSCADR_BLEND_M
- GSCADR_BLEND_NONE
- GSCADR_BLEND_PIX
- GSCADR_BLEND_POS
- GSCADR_BLEND_VID
- GSCADR_COLKEYSRC
- GSCADR_COLKEY_EN
- GSCADR_GBASE_ADR
- GSCADR_STR_EN
- GSCAN_BATCH_NO_THR_SET
- GSCAN_RETRY_THRESHOLD
- GSCEXTINT
- GSCL_CLK_CSIS0
- GSCL_CLK_CSIS1
- GSCL_CLK_FIMC_LITE_A
- GSCL_CLK_FIMC_LITE_B
- GSCL_CLK_FIMC_LITE_D
- GSCL_CLK_GSCL0
- GSCL_CLK_GSCL1
- GSCL_CLK_MSCL0
- GSCL_CLK_MSCL1
- GSCL_CLK_PIXEL_GSCL0
- GSCL_CLK_PIXEL_GSCL1
- GSCL_CLK_SMMU3_GSCL0
- GSCL_CLK_SMMU3_GSCL1
- GSCL_CLK_SMMU3_LITE_A
- GSCL_CLK_SMMU3_LITE_B
- GSCL_CLK_SMMU3_LITE_D
- GSCL_CLK_SMMU3_MSCL0
- GSCL_CLK_SMMU3_MSCL1
- GSCL_DOUT_ACLK_CSIS_200
- GSCL_DOUT_PCLK_M2M_100
- GSCL_MOUT_ACLK_CSIS
- GSCL_MOUT_ACLK_GSCL_333_USER
- GSCL_MOUT_ACLK_GSCL_FIMC_USER
- GSCL_MOUT_ACLK_M2M_400_USER
- GSCL_NR_CLK
- GSCL_SCLK_CSIS0_WRAP
- GSCL_SCLK_CSIS1_WRAP
- GSCR
- GSCTRL
- GSCTRL_GAMMA_EN
- GSCTRL_GPIXFMT
- GSCTRL_GPIXFMT_ARGB1555
- GSCTRL_GPIXFMT_ARGB4444
- GSCTRL_GPIXFMT_ARGB8888
- GSCTRL_GPIXFMT_INDEXED
- GSCTRL_GPIXFMT_RGB565
- GSCTRL_GPIXFMT_RGB888
- GSCTRL_GSHEIGHT
- GSCTRL_GSWIDTH
- GSCTRL_LUT_EN
- GSC_AUTOSUSPEND_DELAY
- GSC_BASE
- GSC_BLK_DISP1WB_DEST
- GSC_BLK_GSCL_WB_IN_SRC_SEL
- GSC_BLK_PXLASYNC_LO_MASK_WB
- GSC_BLK_SW_RESET_WB_DEST
- GSC_BUF_START
- GSC_BUF_STOP
- GSC_BUSCON
- GSC_BUSCON_ARCACHE
- GSC_BUSCON_AWCACHE
- GSC_BUSCON_INT_AXI_RESPONSE
- GSC_BUSCON_INT_DATA_TRANS
- GSC_BUSCON_INT_TIME_MASK
- GSC_CAMERA
- GSC_CBCR
- GSC_CLK_GATE_MODE_INIT_CNT
- GSC_CLK_GATE_MODE_SNOOP_CNT
- GSC_CLK_INIT_COUNT
- GSC_CLK_SNOOP_COUNT
- GSC_COEF_ATTR
- GSC_COEF_DEPTH
- GSC_COEF_H_8T
- GSC_COEF_PHASE
- GSC_COEF_RATIO
- GSC_COEF_V_4T
- GSC_CONTROL
- GSC_CORE_H_
- GSC_CRCB
- GSC_CROPPED_HEIGHT
- GSC_CROPPED_HEIGHT_MASK
- GSC_CROPPED_SIZE
- GSC_CROPPED_WIDTH
- GSC_CROPPED_WIDTH_MASK
- GSC_CROP_MAX
- GSC_CROP_MIN
- GSC_CTRL_CLKDIR
- GSC_CTRL_DATDIR
- GSC_CTRL_DIAG
- GSC_CTRL_ENBL
- GSC_CTRL_LPBXR
- GSC_CTX_ABORT
- GSC_CTX_M2M
- GSC_CTX_STOP_REQ
- GSC_DINO_OFFSET
- GSC_DMA
- GSC_DSTIMG_HEIGHT
- GSC_DSTIMG_HEIGHT_MASK
- GSC_DSTIMG_OFFSET
- GSC_DSTIMG_OFFSET_X
- GSC_DSTIMG_OFFSET_X_MASK
- GSC_DSTIMG_OFFSET_Y
- GSC_DSTIMG_OFFSET_Y_MASK
- GSC_DSTIMG_SIZE
- GSC_DSTIMG_WIDTH
- GSC_DSTIMG_WIDTH_MASK
- GSC_DST_FMT
- GSC_EIM_WIDTH
- GSC_ENABLE
- GSC_ENABLE_CLK_GATE_MODE_FREE
- GSC_ENABLE_CLK_GATE_MODE_MASK
- GSC_ENABLE_IN_PP_UPDATE
- GSC_ENABLE_IPC_MODE
- GSC_ENABLE_IPC_MODE_MASK
- GSC_ENABLE_NORM_MODE
- GSC_ENABLE_ON
- GSC_ENABLE_ON_CLEAR_MASK
- GSC_ENABLE_ON_CLEAR_ONESHOT
- GSC_ENABLE_OP_STATUS
- GSC_ENABLE_PP_UPDATE_FIRE_MODE
- GSC_ENABLE_PP_UPDATE_MODE_MASK
- GSC_ENABLE_PP_UPDATE_TIME_CURR
- GSC_ENABLE_PP_UPDATE_TIME_EOPAS
- GSC_ENABLE_PP_UPDATE_TIME_MASK
- GSC_ENABLE_QOS_ENABLE
- GSC_ENABLE_SFR_UPDATE
- GSC_FIMD
- GSC_HCOEF
- GSC_ID
- GSC_ID_KEYBOARD
- GSC_ID_MOUSE
- GSC_IN_BASE_ADDR_CB
- GSC_IN_BASE_ADDR_CB_CUR
- GSC_IN_BASE_ADDR_CB_MASK
- GSC_IN_BASE_ADDR_CR
- GSC_IN_BASE_ADDR_CR_CUR
- GSC_IN_BASE_ADDR_CR_MASK
- GSC_IN_BASE_ADDR_MASK
- GSC_IN_BASE_ADDR_PINGPONG
- GSC_IN_BASE_ADDR_Y
- GSC_IN_BASE_ADDR_Y_CUR
- GSC_IN_BASE_ADDR_Y_MASK
- GSC_IN_CHROMA_ORDER_CBCR
- GSC_IN_CHROMA_ORDER_CRCB
- GSC_IN_CHROMA_ORDER_MASK
- GSC_IN_CHROM_STRIDE
- GSC_IN_CHROM_STRIDE_MASK
- GSC_IN_CHROM_STRIDE_SEL_MASK
- GSC_IN_CHROM_STRIDE_SEPAR
- GSC_IN_CHROM_STRIDE_VALUE
- GSC_IN_CON
- GSC_IN_CURR_ADDR_INDEX
- GSC_IN_CURR_GET_INDEX
- GSC_IN_FORMAT_MASK
- GSC_IN_LOCAL_CAM0
- GSC_IN_LOCAL_CAM1
- GSC_IN_LOCAL_CAM3
- GSC_IN_LOCAL_FIMD_WB
- GSC_IN_LOCAL_SEL_MASK
- GSC_IN_PATH_LOCAL
- GSC_IN_PATH_MASK
- GSC_IN_PATH_MEMORY
- GSC_IN_RB_SWAP
- GSC_IN_RB_SWAP_MASK
- GSC_IN_RGB565
- GSC_IN_RGB_HD_NARROW
- GSC_IN_RGB_HD_WIDE
- GSC_IN_RGB_SD_NARROW
- GSC_IN_RGB_SD_WIDE
- GSC_IN_RGB_TYPE_MASK
- GSC_IN_ROT_180
- GSC_IN_ROT_270
- GSC_IN_ROT_90
- GSC_IN_ROT_90_XFLIP
- GSC_IN_ROT_90_YFLIP
- GSC_IN_ROT_MASK
- GSC_IN_ROT_XFLIP
- GSC_IN_ROT_YFLIP
- GSC_IN_TILE_C_16x16
- GSC_IN_TILE_C_16x8
- GSC_IN_TILE_MODE
- GSC_IN_TILE_TYPE_MASK
- GSC_IN_XRGB8888
- GSC_IN_YUV420_2P
- GSC_IN_YUV420_3P
- GSC_IN_YUV422_1P
- GSC_IN_YUV422_1P_OEDER_LSB_C
- GSC_IN_YUV422_1P_ORDER_LSB_Y
- GSC_IN_YUV422_1P_ORDER_MASK
- GSC_IN_YUV422_2P
- GSC_IN_YUV422_3P
- GSC_IRQ
- GSC_IRQ_BASE
- GSC_IRQ_DONE
- GSC_IRQ_ENABLE
- GSC_IRQ_FRMDONE_MASK
- GSC_IRQ_MAX
- GSC_IRQ_OR_MASK
- GSC_IRQ_OVERRUN
- GSC_IRQ_STATUS_FRM_DONE_IRQ
- GSC_IRQ_STATUS_OR_FRM_DONE
- GSC_IRQ_STATUS_OR_IRQ
- GSC_LSB_C
- GSC_LSB_Y
- GSC_M2M_BUF_NUM
- GSC_MAIN_H_RATIO
- GSC_MAIN_H_RATIO_MASK
- GSC_MAIN_H_RATIO_VALUE
- GSC_MAIN_V_RATIO
- GSC_MAIN_V_RATIO_MASK
- GSC_MAIN_V_RATIO_VALUE
- GSC_MAX_CLOCKS
- GSC_MAX_CTRL_NUM
- GSC_MAX_DEVS
- GSC_MAX_DST
- GSC_MAX_SRC
- GSC_MIXER
- GSC_MODULE_NAME
- GSC_OUT_BASE_ADDR_CB
- GSC_OUT_BASE_ADDR_CB_MASK
- GSC_OUT_BASE_ADDR_CR
- GSC_OUT_BASE_ADDR_CR_MASK
- GSC_OUT_BASE_ADDR_MASK
- GSC_OUT_BASE_ADDR_PINGPONG
- GSC_OUT_BASE_ADDR_Y
- GSC_OUT_BASE_ADDR_Y_MASK
- GSC_OUT_CHROMA_ORDER_CBCR
- GSC_OUT_CHROMA_ORDER_CRCB
- GSC_OUT_CHROMA_ORDER_MASK
- GSC_OUT_CHROM_STRIDE
- GSC_OUT_CHROM_STRIDE_MASK
- GSC_OUT_CHROM_STRIDE_SEL_MASK
- GSC_OUT_CHROM_STRIDE_SEPAR
- GSC_OUT_CHROM_STRIDE_VALUE
- GSC_OUT_CON
- GSC_OUT_CURR_ADDR_INDEX
- GSC_OUT_CURR_GET_INDEX
- GSC_OUT_FORMAT_MASK
- GSC_OUT_GLOBAL_ALPHA
- GSC_OUT_GLOBAL_ALPHA_MASK
- GSC_OUT_PATH_LOCAL
- GSC_OUT_PATH_MASK
- GSC_OUT_PATH_MEMORY
- GSC_OUT_RB_SWAP
- GSC_OUT_RB_SWAP_MASK
- GSC_OUT_RGB565
- GSC_OUT_RGB_HD_NARROW
- GSC_OUT_RGB_HD_WIDE
- GSC_OUT_RGB_SD_NARROW
- GSC_OUT_RGB_SD_WIDE
- GSC_OUT_RGB_TYPE_MASK
- GSC_OUT_TILE_C_16x16
- GSC_OUT_TILE_C_16x8
- GSC_OUT_TILE_MODE
- GSC_OUT_TILE_TYPE_MASK
- GSC_OUT_XRGB8888
- GSC_OUT_YUV420_2P
- GSC_OUT_YUV420_3P
- GSC_OUT_YUV422_1P
- GSC_OUT_YUV422_1P_OEDER_LSB_C
- GSC_OUT_YUV422_1P_ORDER_LSB_Y
- GSC_OUT_YUV422_1P_ORDER_MASK
- GSC_OUT_YUV422_2P
- GSC_OUT_YUV422_3P
- GSC_OUT_YUV444
- GSC_PARAMS
- GSC_PRESC_H_RATIO
- GSC_PRESC_H_RATIO_MASK
- GSC_PRESC_SHFACTOR
- GSC_PRESC_SHFACTOR_MASK
- GSC_PRESC_V_RATIO
- GSC_PRESC_V_RATIO_MASK
- GSC_PRE_SCALE_RATIO
- GSC_RCVDATA
- GSC_REG_SZ
- GSC_RESET
- GSC_RESET_TIMEOUT
- GSC_RGB
- GSC_SCALED_HEIGHT
- GSC_SCALED_HEIGHT_MASK
- GSC_SCALED_SIZE
- GSC_SCALED_WIDTH
- GSC_SCALED_WIDTH_MASK
- GSC_SCALE_MAX
- GSC_SCALE_MIN
- GSC_SCSI_ZALON_OFFSET
- GSC_SC_ALIGN_2
- GSC_SC_ALIGN_4
- GSC_SC_DOWN_RATIO_2_8
- GSC_SC_DOWN_RATIO_3_8
- GSC_SC_DOWN_RATIO_4_8
- GSC_SC_DOWN_RATIO_5_8
- GSC_SC_DOWN_RATIO_6_8
- GSC_SC_DOWN_RATIO_7_8
- GSC_SC_UP_MAX_RATIO
- GSC_SHUTDOWN_TIMEOUT
- GSC_SRCIMG_HEIGHT
- GSC_SRCIMG_HEIGHT_MASK
- GSC_SRCIMG_OFFSET
- GSC_SRCIMG_OFFSET_X
- GSC_SRCIMG_OFFSET_X_MASK
- GSC_SRCIMG_OFFSET_Y
- GSC_SRCIMG_OFFSET_Y_MASK
- GSC_SRCIMG_SIZE
- GSC_SRCIMG_WIDTH
- GSC_SRCIMG_WIDTH_MASK
- GSC_SRC_FMT
- GSC_STATUS
- GSC_STAT_CLKSHD
- GSC_STAT_CMPINTR
- GSC_STAT_DATSHD
- GSC_STAT_PERR
- GSC_STAT_RBNE
- GSC_STAT_TBNE
- GSC_STAT_TERR
- GSC_SW_RESET
- GSC_SW_RESET_SRESET
- GSC_VCOEF
- GSC_VPOSITION
- GSC_VPOS_F
- GSC_WIDTH_ITU_709
- GSC_WRITEBACK
- GSC_XMTDATA
- GSC_YUV420
- GSC_YUV422
- GSC_YUV444
- GSE
- GSEGPOFF
- GSEG_BASE
- GSEG_START
- GSIM_UCLK_GPIO_79
- GSIM_UDET_GPIO_82
- GSIM_UIO_GPIO_80
- GSIM_nURST_GPIO_81
- GSIR
- GSI_GET_HWRPB
- GSI_IEEE_FP_CONTROL
- GSI_IEEE_STATE_AT_SIGNAL
- GSI_PROC_TYPE
- GSI_QKEY
- GSI_UACPROC
- GSI_VENDOR_OPENCLOSE
- GSKT_CONTROL__GSKT_SpareRegs_MASK
- GSKT_CONTROL__GSKT_SpareRegs__SHIFT
- GSKT_CONTROL__GSKT_TxFifoBypass_MASK
- GSKT_CONTROL__GSKT_TxFifoBypass__SHIFT
- GSKT_CONTROL__GSKT_TxFifoDelay2_MASK
- GSKT_CONTROL__GSKT_TxFifoDelay2__SHIFT
- GSKT_CONTROL__GSKT_TxFifoDelay_MASK
- GSKT_CONTROL__GSKT_TxFifoDelay__SHIFT
- GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK
- GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT
- GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK
- GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT
- GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK
- GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT
- GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK
- GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT
- GSM0_SOF
- GSM1_ESCAPE
- GSM1_ESCAPE_BITS
- GSM1_SOF
- GSMIOC_DISABLE_NET
- GSMIOC_ENABLE_NET
- GSMIOC_GETCONF
- GSMIOC_GETFIRST
- GSMIOC_SETCONF
- GSMI_BUFFER_TOO_SMALL
- GSMI_BUF_ALIGN
- GSMI_BUF_SIZE
- GSMI_CALLBACK
- GSMI_CMD_CLEAR_CONFIG
- GSMI_CMD_CLEAR_EVENT_LOG
- GSMI_CMD_GET_NEXT_VAR
- GSMI_CMD_GET_NVRAM_VAR
- GSMI_CMD_HANDSHAKE_TYPE
- GSMI_CMD_LOG_S0IX_RESUME
- GSMI_CMD_LOG_S0IX_SUSPEND
- GSMI_CMD_SET_EVENT_LOG
- GSMI_CMD_SET_NVRAM_VAR
- GSMI_DEFAULT_SPINCOUNT
- GSMI_DEVICE_ERROR
- GSMI_GUID_SIZE
- GSMI_HANDSHAKE_CF
- GSMI_HANDSHAKE_NONE
- GSMI_HANDSHAKE_SPIN
- GSMI_INVALID_PARAMETER
- GSMI_LOG_ENTRY_TYPE_KERNEL
- GSMI_LOG_FULL
- GSMI_NOT_FOUND
- GSMI_NOT_READY
- GSMI_SHUTDOWN_CLEAN
- GSMI_SHUTDOWN_DIE
- GSMI_SHUTDOWN_MBE
- GSMI_SHUTDOWN_MCE
- GSMI_SHUTDOWN_NMIWDT
- GSMI_SHUTDOWN_OOPS
- GSMI_SHUTDOWN_PANIC
- GSMI_SHUTDOWN_SOFTWDT
- GSMI_SHUTDOWN_TRIPLE
- GSMI_SUCCESS
- GSMI_UNSUPPORTED
- GSMI_UNSUPPORTED2
- GSMI_VAR_NOT_FOUND
- GSM_ADDRESS
- GSM_ADDR_BASE
- GSM_BASE
- GSM_CONFIG_RESET
- GSM_CONFIG_RESET_VALUE
- GSM_CONTROL
- GSM_DATA
- GSM_FCS
- GSM_LEN
- GSM_LEN0
- GSM_LEN1
- GSM_NET_TX_TIMEOUT
- GSM_OVERRUN
- GSM_READ_ADDR_PARITY_CHECK
- GSM_READ_ADDR_PARITY_INDIC
- GSM_SEARCH
- GSM_SM_BASE
- GSM_SSOF
- GSM_START
- GSM_WRITE_ADDR_PARITY_CHECK
- GSM_WRITE_ADDR_PARITY_INDIC
- GSM_WRITE_DATA_PARITY_CHECK
- GSM_WRITE_DATA_PARITY_INDIC
- GSNPSID
- GSNPSID_ID_MASK
- GSO_BIT
- GSO_BY_FRAGS
- GSO_ENABLED
- GSO_ERROR
- GSO_MAX_SEGS
- GSO_MAX_SIZE
- GSPCAV2_H
- GSPCA_MAX_FRAMES
- GSPCA_MEMORY_NO
- GSPCA_MEMORY_READ
- GSPCA_VERSION
- GSPDA_VENDOR_ID
- GSPDA_XPLORE_M68_ID
- GSP_INITIAL_OFFSET
- GSP_LEN
- GSR
- GSR_ACOFFD
- GSR_BIT1SLT12
- GSR_BIT2SLT12
- GSR_BIT3SLT12
- GSR_CDONE
- GSR_GSCI
- GSR_MCINT
- GSR_MIINT
- GSR_MOINT
- GSR_PCR
- GSR_PIINT
- GSR_POINT
- GSR_PRIRES
- GSR_RDCS
- GSR_SCR
- GSR_SDONE
- GSR_SECRES
- GSSD_MIN_TIMEOUT
- GSSPROXY_PROGRAM
- GSSPROXY_SOCK_PATHNAME
- GSSPROXY_VERS_1
- GSSX_ACCEPT_SEC_CONTEXT
- GSSX_ACQUIRE_CRED
- GSSX_ARG_accept_sec_context_sz
- GSSX_ARG_acquire_cred_sz
- GSSX_ARG_export_cred_sz
- GSSX_ARG_get_call_context_sz
- GSSX_ARG_get_mic_sz
- GSSX_ARG_import_and_canon_name_sz
- GSSX_ARG_import_cred_sz
- GSSX_ARG_indicate_mechs_sz
- GSSX_ARG_init_sec_context_sz
- GSSX_ARG_release_handle_sz
- GSSX_ARG_store_cred_sz
- GSSX_ARG_unwrap_sz
- GSSX_ARG_verify_sz
- GSSX_ARG_wrap_size_limit_sz
- GSSX_ARG_wrap_sz
- GSSX_C_ACCEPT
- GSSX_C_BOTH
- GSSX_C_INITIATE
- GSSX_EXPORT_CRED
- GSSX_GET_CALL_CONTEXT
- GSSX_GET_MIC
- GSSX_IMPORT_AND_CANON_NAME
- GSSX_IMPORT_CRED
- GSSX_INDICATE_MECHS
- GSSX_INIT_SEC_CONTEXT
- GSSX_KMEMBUF
- GSSX_MAX_OUT_HANDLE
- GSSX_MAX_SRC_PRINC
- GSSX_NULL
- GSSX_RELEASE_HANDLE
- GSSX_RES_accept_sec_context_sz
- GSSX_RES_acquire_cred_sz
- GSSX_RES_export_cred_sz
- GSSX_RES_get_call_context_sz
- GSSX_RES_get_mic_sz
- GSSX_RES_import_and_canon_name_sz
- GSSX_RES_import_cred_sz
- GSSX_RES_indicate_mechs_sz
- GSSX_RES_init_sec_context_sz
- GSSX_RES_release_handle_sz
- GSSX_RES_store_cred_sz
- GSSX_RES_unwrap_sz
- GSSX_RES_verify_sz
- GSSX_RES_wrap_size_limit_sz
- GSSX_RES_wrap_sz
- GSSX_STORE_CRED
- GSSX_UNWRAP
- GSSX_VERIFY
- GSSX_WRAP
- GSSX_WRAP_SIZE_LIMIT
- GSSX_default_ctx_sz
- GSSX_default_in_call_ctx_sz
- GSSX_default_in_cb_sz
- GSSX_default_in_cred_sz
- GSSX_default_in_ctx_hndl_sz
- GSSX_default_in_token_sz
- GSSX_default_status_sz
- GSSX_max_creds_sz
- GSSX_max_oid_sz
- GSSX_max_output_handle_sz
- GSSX_max_output_token_sz
- GSSX_max_princ_sz
- GSS_CALLING_ERROR
- GSS_CALLING_ERROR_FIELD
- GSS_CRED_SLACK
- GSS_C_ACCEPT
- GSS_C_ANON_FLAG
- GSS_C_BOTH
- GSS_C_CALLING_ERROR_MASK
- GSS_C_CALLING_ERROR_OFFSET
- GSS_C_CONF_FLAG
- GSS_C_DELEG_FLAG
- GSS_C_GSS_CODE
- GSS_C_INDEFINITE
- GSS_C_INITIATE
- GSS_C_INTEG_FLAG
- GSS_C_MECH_CODE
- GSS_C_MUTUAL_FLAG
- GSS_C_NO_BUFFER
- GSS_C_NO_CONTEXT
- GSS_C_PROT_READY_FLAG
- GSS_C_QOP_DEFAULT
- GSS_C_REPLAY_FLAG
- GSS_C_ROUTINE_ERROR_MASK
- GSS_C_ROUTINE_ERROR_OFFSET
- GSS_C_SEQUENCE_FLAG
- GSS_C_SUPPLEMENTARY_MASK
- GSS_C_SUPPLEMENTARY_OFFSET
- GSS_C_TRANS_FLAG
- GSS_ERROR
- GSS_KEY_EXPIRE_TIMEO
- GSS_KRB5_K5CLENGTH
- GSS_KRB5_MAX_BLOCKSIZE
- GSS_KRB5_MAX_CKSUM_LEN
- GSS_KRB5_MAX_KEYLEN
- GSS_KRB5_MAX_SLACK_NEEDED
- GSS_KRB5_TOK_HDR_LEN
- GSS_OID_MAX_LEN
- GSS_RESET
- GSS_RETRY_EXPIRED
- GSS_ROUTINE_ERROR
- GSS_ROUTINE_ERROR_FIELD
- GSS_SEQ_WIN
- GSS_SLP_RESET
- GSS_SUPPLEMENTARY_INFO
- GSS_SUPPLEMENTARY_INFO_FIELD
- GSS_S_BAD_BINDINGS
- GSS_S_BAD_MECH
- GSS_S_BAD_NAME
- GSS_S_BAD_NAMETYPE
- GSS_S_BAD_QOP
- GSS_S_BAD_SIG
- GSS_S_BAD_STATUS
- GSS_S_CALL_BAD_STRUCTURE
- GSS_S_CALL_INACCESSIBLE_READ
- GSS_S_CALL_INACCESSIBLE_WRITE
- GSS_S_COMPLETE
- GSS_S_CONTEXT_EXPIRED
- GSS_S_CONTINUE_NEEDED
- GSS_S_CREDENTIALS_EXPIRED
- GSS_S_CRED_UNAVAIL
- GSS_S_DEFECTIVE_CREDENTIAL
- GSS_S_DEFECTIVE_TOKEN
- GSS_S_DUPLICATE_ELEMENT
- GSS_S_DUPLICATE_TOKEN
- GSS_S_FAILURE
- GSS_S_GAP_TOKEN
- GSS_S_NAME_NOT_MN
- GSS_S_NO_CONTEXT
- GSS_S_NO_CRED
- GSS_S_OLD_TOKEN
- GSS_S_UNAUTHORIZED
- GSS_S_UNAVAILABLE
- GSS_S_UNSEQ_TOKEN
- GSS_VERF_SLACK
- GSTA_GPIO_PER_BLOCK
- GSTA_NR_BLOCKS
- GSTA_NR_GPIO
- GSTHREADID_SIZE
- GSTS
- GST_GPIO_INPUT_VAL
- GST_GSTLEN_MPIS_OFFSET
- GST_IOPTCNT_OFFSET
- GST_IQ_FREEZE_STATE0_OFFSET
- GST_IQ_FREEZE_STATE1_OFFSET
- GST_LEN
- GST_MPI_STATE_ERROR
- GST_MPI_STATE_INIT
- GST_MPI_STATE_MASK
- GST_MPI_STATE_TERMINATION
- GST_MPI_STATE_UNINIT
- GST_MSGUTCNT_OFFSET
- GST_PHYSTATE0_OFFSET
- GST_PHYSTATE1_OFFSET
- GST_PHYSTATE2_OFFSET
- GST_PHYSTATE3_OFFSET
- GST_PHYSTATE4_OFFSET
- GST_PHYSTATE5_OFFSET
- GST_PHYSTATE6_OFFSET
- GST_PHYSTATE7_OFFSET
- GST_PHYSTATE_OFFSET
- GST_RERRINFO_OFFSET
- GST_RERRINFO_OFFSET0
- GST_RERRINFO_OFFSET1
- GST_RERRINFO_OFFSET2
- GST_RERRINFO_OFFSET3
- GST_RERRINFO_OFFSET4
- GST_RERRINFO_OFFSET5
- GST_RERRINFO_OFFSET6
- GST_RERRINFO_OFFSET7
- GSUSB_ENDPOINT_IN
- GSUSB_ENDPOINT_OUT
- GSWIP_BM_CTRL_RMON_RAM1_RES
- GSWIP_BM_CTRL_RMON_RAM2_RES
- GSWIP_BM_PCFG_CNTEN
- GSWIP_BM_PCFG_IGCNT
- GSWIP_BM_PCFGp
- GSWIP_BM_QUEUE_GCTRL
- GSWIP_BM_QUEUE_GCTRL_GL_MOD
- GSWIP_BM_RAM_ADDR
- GSWIP_BM_RAM_CTRL
- GSWIP_BM_RAM_CTRL_ADDR_MASK
- GSWIP_BM_RAM_CTRL_BAS
- GSWIP_BM_RAM_CTRL_OPMOD
- GSWIP_BM_RAM_VAL
- GSWIP_BM_RMON_CTRLp
- GSWIP_FDMA_PCTRL_EN
- GSWIP_FDMA_PCTRL_STEN
- GSWIP_FDMA_PCTRL_VLANMOD_BOTH
- GSWIP_FDMA_PCTRL_VLANMOD_DIS
- GSWIP_FDMA_PCTRL_VLANMOD_ID
- GSWIP_FDMA_PCTRL_VLANMOD_MASK
- GSWIP_FDMA_PCTRL_VLANMOD_PRIO
- GSWIP_FDMA_PCTRL_VLANMOD_SHIFT
- GSWIP_FDMA_PCTRLp
- GSWIP_MAC_CTRL_2_MLEN
- GSWIP_MAC_CTRL_2p
- GSWIP_MAC_FLEN
- GSWIP_MDIO_CTRL
- GSWIP_MDIO_CTRL_BUSY
- GSWIP_MDIO_CTRL_PHYAD_MASK
- GSWIP_MDIO_CTRL_PHYAD_SHIFT
- GSWIP_MDIO_CTRL_RD
- GSWIP_MDIO_CTRL_REGAD_MASK
- GSWIP_MDIO_CTRL_WR
- GSWIP_MDIO_GLOB
- GSWIP_MDIO_GLOB_ENABLE
- GSWIP_MDIO_MDC_CFG0
- GSWIP_MDIO_MDC_CFG1
- GSWIP_MDIO_PHY_ADDR_MASK
- GSWIP_MDIO_PHY_FCONRX_AUTO
- GSWIP_MDIO_PHY_FCONRX_DIS
- GSWIP_MDIO_PHY_FCONRX_EN
- GSWIP_MDIO_PHY_FCONRX_MASK
- GSWIP_MDIO_PHY_FCONTX_AUTO
- GSWIP_MDIO_PHY_FCONTX_DIS
- GSWIP_MDIO_PHY_FCONTX_EN
- GSWIP_MDIO_PHY_FCONTX_MASK
- GSWIP_MDIO_PHY_FDUP_AUTO
- GSWIP_MDIO_PHY_FDUP_DIS
- GSWIP_MDIO_PHY_FDUP_EN
- GSWIP_MDIO_PHY_FDUP_MASK
- GSWIP_MDIO_PHY_LINK_AUTO
- GSWIP_MDIO_PHY_LINK_DOWN
- GSWIP_MDIO_PHY_LINK_MASK
- GSWIP_MDIO_PHY_LINK_UP
- GSWIP_MDIO_PHY_MASK
- GSWIP_MDIO_PHY_SPEED_AUTO
- GSWIP_MDIO_PHY_SPEED_G1
- GSWIP_MDIO_PHY_SPEED_M10
- GSWIP_MDIO_PHY_SPEED_M100
- GSWIP_MDIO_PHY_SPEED_MASK
- GSWIP_MDIO_PHYp
- GSWIP_MDIO_READ
- GSWIP_MDIO_WRITE
- GSWIP_MII_CFG0
- GSWIP_MII_CFG1
- GSWIP_MII_CFG5
- GSWIP_MII_CFG_EN
- GSWIP_MII_CFG_LDCLKDIS
- GSWIP_MII_CFG_MODE_MASK
- GSWIP_MII_CFG_MODE_MIIM
- GSWIP_MII_CFG_MODE_MIIP
- GSWIP_MII_CFG_MODE_RGMII
- GSWIP_MII_CFG_MODE_RMIIM
- GSWIP_MII_CFG_MODE_RMIIP
- GSWIP_MII_CFG_RATE_AUTO
- GSWIP_MII_CFG_RATE_M125
- GSWIP_MII_CFG_RATE_M25
- GSWIP_MII_CFG_RATE_M2P5
- GSWIP_MII_CFG_RATE_M50
- GSWIP_MII_CFG_RATE_MASK
- GSWIP_MII_PCDU0
- GSWIP_MII_PCDU1
- GSWIP_MII_PCDU5
- GSWIP_MII_PCDU_RXDLY_MASK
- GSWIP_MII_PCDU_TXDLY_MASK
- GSWIP_PCE_DEFPVID
- GSWIP_PCE_GCTRL_0
- GSWIP_PCE_GCTRL_0_MC_VALID
- GSWIP_PCE_GCTRL_0_MTFL
- GSWIP_PCE_GCTRL_0_VLAN
- GSWIP_PCE_GCTRL_1
- GSWIP_PCE_GCTRL_1_MAC_GLOCK
- GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD
- GSWIP_PCE_PCTRL_0_INGRESS
- GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING
- GSWIP_PCE_PCTRL_0_PSTATE_LEARNING
- GSWIP_PCE_PCTRL_0_PSTATE_LISTEN
- GSWIP_PCE_PCTRL_0_PSTATE_MASK
- GSWIP_PCE_PCTRL_0_PSTATE_RX
- GSWIP_PCE_PCTRL_0_PSTATE_TX
- GSWIP_PCE_PCTRL_0_TVM
- GSWIP_PCE_PCTRL_0_VREP
- GSWIP_PCE_PCTRL_0p
- GSWIP_PCE_PMAP1
- GSWIP_PCE_PMAP2
- GSWIP_PCE_PMAP3
- GSWIP_PCE_TBL_ADDR
- GSWIP_PCE_TBL_CTRL
- GSWIP_PCE_TBL_CTRL_ADDR_MASK
- GSWIP_PCE_TBL_CTRL_BAS
- GSWIP_PCE_TBL_CTRL_GMAP_MASK
- GSWIP_PCE_TBL_CTRL_KEYFORM
- GSWIP_PCE_TBL_CTRL_OPMOD_ADRD
- GSWIP_PCE_TBL_CTRL_OPMOD_ADWR
- GSWIP_PCE_TBL_CTRL_OPMOD_KSRD
- GSWIP_PCE_TBL_CTRL_OPMOD_KSWR
- GSWIP_PCE_TBL_CTRL_OPMOD_MASK
- GSWIP_PCE_TBL_CTRL_TYPE
- GSWIP_PCE_TBL_CTRL_VLD
- GSWIP_PCE_TBL_KEY
- GSWIP_PCE_TBL_MASK
- GSWIP_PCE_TBL_VAL
- GSWIP_PCE_VCTRL
- GSWIP_PCE_VCTRL_UVR
- GSWIP_PCE_VCTRL_VEMR
- GSWIP_PCE_VCTRL_VID0
- GSWIP_PCE_VCTRL_VIMR
- GSWIP_PCE_VCTRL_VSR
- GSWIP_RX_HEADER_LEN
- GSWIP_RX_SPPID_MASK
- GSWIP_RX_SPPID_SHIFT
- GSWIP_SDMA_PCTRL_EN
- GSWIP_SDMA_PCTRL_FCEN
- GSWIP_SDMA_PCTRL_PAUFWD
- GSWIP_SDMA_PCTRLp
- GSWIP_SWRES
- GSWIP_SWRES_R0
- GSWIP_SWRES_R1
- GSWIP_TABLE_ACTIVE_VLAN
- GSWIP_TABLE_MAC_BRIDGE
- GSWIP_TABLE_MAC_BRIDGE_STATIC
- GSWIP_TABLE_VLAN_MAPPING
- GSWIP_TX_CLASS_EN
- GSWIP_TX_CLASS_MASK
- GSWIP_TX_CLASS_SHIFT
- GSWIP_TX_CRCGEN_DIS
- GSWIP_TX_DPID_APP1
- GSWIP_TX_DPID_APP2
- GSWIP_TX_DPID_APP3
- GSWIP_TX_DPID_APP4
- GSWIP_TX_DPID_APP5
- GSWIP_TX_DPID_CPU
- GSWIP_TX_DPID_ELAN
- GSWIP_TX_DPID_EN
- GSWIP_TX_DPID_EWAN
- GSWIP_TX_DPID_SHIFT
- GSWIP_TX_HEADER_LEN
- GSWIP_TX_LRN_DIS
- GSWIP_TX_PORT_MAP_EN
- GSWIP_TX_PORT_MAP_MASK
- GSWIP_TX_PORT_MAP_SEL
- GSWIP_TX_PORT_MAP_SHIFT
- GSWIP_TX_SLPID_APP1
- GSWIP_TX_SLPID_APP2
- GSWIP_TX_SLPID_APP3
- GSWIP_TX_SLPID_APP4
- GSWIP_TX_SLPID_APP5
- GSWIP_TX_SLPID_CPU
- GSWIP_TX_SLPID_SHIFT
- GSWIP_VERSION
- GSWIP_VERSION_2_0
- GSWIP_VERSION_2_1
- GSWIP_VERSION_2_2
- GSWIP_VERSION_2_2_ETC
- GSWIP_VERSION_MOD_MASK
- GSWIP_VERSION_MOD_SHIFT
- GSWIP_VERSION_REV_MASK
- GSWIP_VERSION_REV_SHIFT
- GSW_VSA_SIG
- GSYNC
- GS_ABRT_STS
- GS_AUTH_STATUS_BAD
- GS_AUTH_STATUS_GOOD
- GS_AUTH_STATUS_MASK
- GS_AUTH_STATUS_SHIFT
- GS_AUTO
- GS_BASE
- GS_BOOTROM_JUMP_PASSED
- GS_BOOTROM_MASK
- GS_BOOTROM_RSA_FAILED
- GS_BOOTROM_SHIFT
- GS_BROADCAST
- GS_CAN_FEATURE_HW_TIMESTAMP
- GS_CAN_FEATURE_IDENTIFY
- GS_CAN_FEATURE_LISTEN_ONLY
- GS_CAN_FEATURE_LOOP_BACK
- GS_CAN_FEATURE_ONE_SHOT
- GS_CAN_FEATURE_TRIPLE_SAMPLE
- GS_CAN_FLAG_OVERFLOW
- GS_CAN_IDENTIFY_OFF
- GS_CAN_IDENTIFY_ON
- GS_CAN_MODE_LISTEN_ONLY
- GS_CAN_MODE_LOOP_BACK
- GS_CAN_MODE_NORMAL
- GS_CAN_MODE_ONE_SHOT
- GS_CAN_MODE_RESET
- GS_CAN_MODE_START
- GS_CAN_MODE_TRIPLE_SAMPLE
- GS_CAN_STATE_BUS_OFF
- GS_CAN_STATE_ERROR_ACTIVE
- GS_CAN_STATE_ERROR_PASSIVE
- GS_CAN_STATE_ERROR_WARNING
- GS_CAN_STATE_SLEEPING
- GS_CAN_STATE_STOPPED
- GS_CDC_OBEX_PRODUCT_ID
- GS_CDC_PRODUCT_ID
- GS_CHIP_ID
- GS_CLEAR_BC_CB
- GS_CLEAR_STS
- GS_CLOSE_TIMEOUT
- GS_COL_STS
- GS_CONSOLE_BUF_SIZE
- GS_CUT_1024
- GS_CUT_128
- GS_CUT_256
- GS_CUT_512
- GS_DISABLE
- GS_ENABLE
- GS_FC_GFN_CMD
- GS_FC_GMAL_CMD
- GS_FC_PING_CMD
- GS_FC_TRACE_CMD
- GS_FLUSH_CTL
- GS_GA_NXT
- GS_GID_FT
- GS_GID_PN
- GS_GNN_ID
- GS_GPN_ID
- GS_GSPN_ID
- GS_HCYC_STS
- GS_HEIGHT_MAX
- GS_HEIGHT_MIN
- GS_HST_STS
- GS_INVOCATION_COUNT
- GS_INVOCATION_COUNT_UDW
- GS_LONG_NAME
- GS_MAX_INTF
- GS_MAX_RX_URBS
- GS_MAX_TX_URBS
- GS_MIA_CORE_STATE
- GS_MIA_HALT_REQUESTED
- GS_MIA_IN_RESET
- GS_MIA_ISR_ENTRY
- GS_MIA_MASK
- GS_MIA_SHIFT
- GS_NOTIFY_INTERVAL_MS
- GS_NOTIFY_MAXPACKET
- GS_OFF
- GS_PIXELCLOCK_MAX
- GS_PIXELCLOCK_MIN
- GS_PRERR_STS
- GS_PRIMITIVES_COUNT
- GS_PRIMITIVES_COUNT_UDW
- GS_PRIO
- GS_PRODUCT_ID
- GS_RCS_ID
- GS_RESET_SHIFT
- GS_RFF_ID
- GS_RFT_ID
- GS_RNN_ID
- GS_RPN_ID
- GS_RPT_ID
- GS_RSNN_NN
- GS_RSPN_ID
- GS_SCENARIO_A
- GS_SCENARIO_B
- GS_SCENARIO_C
- GS_SCENARIO_G
- GS_SET_BC_CB
- GS_SMB_STS
- GS_STAGE_OFF
- GS_STAGE_ON
- GS_STRINGS_R
- GS_STRINGS_RW
- GS_STRINGS_W
- GS_TO_REG
- GS_TO_STS
- GS_UKERNEL_DPC_ERROR
- GS_UKERNEL_EXCEPTION
- GS_UKERNEL_LAPIC_DONE
- GS_UKERNEL_MASK
- GS_UKERNEL_READY
- GS_UKERNEL_SHIFT
- GS_UNIT_CLOCK_GATE_DISABLE
- GS_USB_BREQ_BERR
- GS_USB_BREQ_BITTIMING
- GS_USB_BREQ_BT_CONST
- GS_USB_BREQ_DEVICE_CONFIG
- GS_USB_BREQ_HOST_FORMAT
- GS_USB_BREQ_IDENTIFY
- GS_USB_BREQ_MODE
- GS_USB_BREQ_TIMESTAMP
- GS_VENDOR_ID
- GS_VERSION_NAME
- GS_VERSION_NUM
- GS_VERSION_STR
- GS_WIDTH_MAX
- GS_WIDTH_MIN
- GT200_DISP
- GT200_DISP_BASE_CHANNEL_DMA
- GT200_DISP_CORE_CHANNEL_DMA
- GT200_DISP_OVERLAY_CHANNEL_DMA
- GT200_TESLA
- GT206_DISP
- GT206_DISP_CORE_CHANNEL_DMA
- GT212_DMA
- GT212_MSPDEC
- GT212_MSPPP
- GT212_MSVLD
- GT214_COMPUTE
- GT214_DISP
- GT214_DISP_BASE_CHANNEL_DMA
- GT214_DISP_CORE_CHANNEL_DMA
- GT214_DISP_CURSOR
- GT214_DISP_OVERLAY
- GT214_DISP_OVERLAY_CHANNEL_DMA
- GT214_TESLA
- GT21A_TESLA
- GT30TS00_DEVID
- GT30TS00_DEVID_MASK
- GT34TS02_DEVID
- GT34TS02_DEVID_MASK
- GT64120_BASE
- GT641XX_BASE_CLOCK
- GT641XX_CASCADE_IRQ
- GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ
- GT641XX_CPU_INT0_IRQ
- GT641XX_CPU_INT1_IRQ
- GT641XX_CPU_INT2_IRQ
- GT641XX_CPU_INT3_IRQ
- GT641XX_CPU_INT4_IRQ
- GT641XX_DMA0_IRQ
- GT641XX_DMA1_IRQ
- GT641XX_DMA2_IRQ
- GT641XX_DMA3_IRQ
- GT641XX_DMA_OUT_OF_RANGE_IRQ
- GT641XX_IRQ_BASE
- GT641XX_IRQ_TO_BIT
- GT641XX_MEMORY_ERROR_IRQ
- GT641XX_MEMORY_OUT_OF_RANGE_IRQ
- GT641XX_PCI_0_ADDRESS_ERROR_IRQ
- GT641XX_PCI_0_MASTER_ABORT_IRQ
- GT641XX_PCI_0_MASTER_READ_ERROR_IRQ
- GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ
- GT641XX_PCI_0_RETRY_TIMEOUT_IRQ
- GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ
- GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ
- GT641XX_PCI_0_TARGET_ABORT_IRQ
- GT641XX_PCI_INT0_IRQ
- GT641XX_PCI_INT1_IRQ
- GT641XX_PCI_INT2_IRQ
- GT641XX_PCI_INT3_IRQ
- GT641XX_TIMER0_IRQ
- GT641XX_TIMER1_IRQ
- GT641XX_TIMER2_IRQ
- GT641XX_TIMER3_IRQ
- GT683R_BUFFER_SIZE
- GT683R_LED_AUDIO
- GT683R_LED_BACK
- GT683R_LED_BREATHING
- GT683R_LED_COUNT
- GT683R_LED_FRONT
- GT683R_LED_NORMAL
- GT683R_LED_OFF
- GT683R_LED_SIDE
- GTA02_CHARGER_CONFIGURE_TIMEOUT
- GTA02_FLASH_BASE
- GTA02_FLASH_SIZE
- GTA02_GPIO_AMP_SHUT
- GTA02_GPIO_AUX_KEY
- GTA02_GPIO_AUX_LED
- GTA02_GPIO_HOLD_KEY
- GTA02_GPIO_HP_IN
- GTA02_GPIO_USB_PULLUP
- GTA02_IRQ_PCF50633
- GTCCR_TOG
- GTCFR_RST
- GTCFR_STP
- GTCO_VERSION
- GTC_3D_RESET_DELAY
- GTDRIVER_IPC
- GTEQT
- GTFIFOCTL
- GTFIFODBG
- GTF_CELL_GRAN
- GTF_C_PRIME
- GTF_D_C
- GTF_D_C_PRIME
- GTF_D_J
- GTF_D_K
- GTF_D_M
- GTF_D_M_PRIME
- GTF_MARGIN_PERCENTAGE
- GTF_MIN_VSYNC_BP
- GTF_MIN_V_PORCH
- GTF_M_PRIME
- GTF_PXL_CLK_GRAN
- GTF_SUPPORT
- GTF_S_C
- GTF_S_C_PRIME
- GTF_S_J
- GTF_S_K
- GTF_S_M
- GTF_S_M_PRIME
- GTF_V_FP
- GTF_accept_transfer
- GTF_invalid
- GTF_permit_access
- GTF_reading
- GTF_readonly
- GTF_sub_page
- GTF_transfer_committed
- GTF_transfer_completed
- GTF_transitive
- GTF_type_mask
- GTF_writing
- GTGREF0_REF
- GTH_CTP
- GTH_LPP
- GTH_MSU
- GTH_NONE
- GTH_PLE_WAITLOOP_DEPTH
- GTH_PTI
- GTI
- GTIER
- GTIIR
- GTIMEOUT
- GTIMR
- GTISR
- GTI_BIT
- GTI_TIV
- GTI_TIV_MAX
- GTI_TIV_MIN
- GTKEXT_PG
- GTK_REKEY_FAILURE
- GTK_SET_BSS_KEY_TAG
- GTMDR_FRR
- GTMDR_ICLK_ICAS
- GTMDR_ICLK_ICLK
- GTMDR_ICLK_MASK
- GTMDR_ICLK_SLGO
- GTMDR_ORI
- GTMDR_SPS
- GTM_buffer
- GTO0
- GTO1
- GTO2
- GTO_TIMEOUT
- GTO_TIMEOUT_CLR
- GTO_TIMEOUT_EN
- GTP0_PORT
- GTP1U_PORT
- GTP1_F_EXTHDR
- GTP1_F_MASK
- GTP1_F_NPDU
- GTP1_F_SEQ
- GTPA_FLOW
- GTPA_I_TEI
- GTPA_LINK
- GTPA_MAX
- GTPA_MS_ADDRESS
- GTPA_NET_NS_FD
- GTPA_O_TEI
- GTPA_PAD
- GTPA_PEER_ADDRESS
- GTPA_SGSN_ADDRESS
- GTPA_TID
- GTPA_UNSPEC
- GTPA_VERSION
- GTP_CMD_DELPDP
- GTP_CMD_GETPDP
- GTP_CMD_MAX
- GTP_CMD_NEWPDP
- GTP_ROLE_GGSN
- GTP_ROLE_SGSN
- GTP_TPDU
- GTP_V0
- GTP_V1
- GTR
- GTRP_F
- GTRP_S
- GTRP_V
- GTS
- GTSCC_CDMAS_DMA_DIR_SHIFT
- GTSCC_TSCCD_MASK
- GTSCC_TSCCD_SHIFT
- GTSCC_TSCCI_MASK
- GTSENDV4
- GTSENDV6
- GTT
- GTTCPHO_MAX
- GTTCPHO_SHIFT
- GTT_64K_PTE_STRIDE
- GTT_BAR0_MAP_REG_IGU_CMD
- GTT_BAR0_MAP_REG_MSDM_RAM
- GTT_BAR0_MAP_REG_MSDM_RAM_1024
- GTT_BAR0_MAP_REG_PSDM_RAM
- GTT_BAR0_MAP_REG_TSDM_RAM
- GTT_BAR0_MAP_REG_USDM_RAM
- GTT_BAR0_MAP_REG_USDM_RAM_1024
- GTT_BAR0_MAP_REG_USDM_RAM_2048
- GTT_BAR0_MAP_REG_XSDM_RAM
- GTT_BAR0_MAP_REG_YSDM_RAM
- GTT_BUFFER
- GTT_BYTE_SIZE_BITS
- GTT_CACHE_EN_ALL
- GTT_DWORD_SIZE
- GTT_DWORD_SIZE_BITS
- GTT_ENTRY_NUM_IN_ONE_PAGE
- GTT_FAULT
- GTT_HAW
- GTT_PAGE_SIZE
- GTT_SIZE
- GTT_SPTE_FLAG_64K_SPLITED
- GTT_SPTE_FLAG_MASK
- GTT_TYPE_GGTT_PTE
- GTT_TYPE_INVALID
- GTT_TYPE_MAX
- GTT_TYPE_PPGTT_ENTRY
- GTT_TYPE_PPGTT_PDE_ENTRY
- GTT_TYPE_PPGTT_PDE_PT
- GTT_TYPE_PPGTT_PDP_ENTRY
- GTT_TYPE_PPGTT_PDP_PT
- GTT_TYPE_PPGTT_PML4_ENTRY
- GTT_TYPE_PPGTT_PML4_PT
- GTT_TYPE_PPGTT_PTE_1G_ENTRY
- GTT_TYPE_PPGTT_PTE_2M_ENTRY
- GTT_TYPE_PPGTT_PTE_4K_ENTRY
- GTT_TYPE_PPGTT_PTE_64K_ENTRY
- GTT_TYPE_PPGTT_PTE_ENTRY
- GTT_TYPE_PPGTT_PTE_PT
- GTT_TYPE_PPGTT_ROOT_ENTRY
- GTT_TYPE_PPGTT_ROOT_L3_ENTRY
- GTT_TYPE_PPGTT_ROOT_L4_ENTRY
- GTT_TYPE_TABLE_ENTRY
- GTWX5715_BUTTON_GPIO
- GTWX5715_KSSPI_CLOCK
- GTWX5715_KSSPI_RXD
- GTWX5715_KSSPI_SELECT
- GTWX5715_KSSPI_TXD
- GTWX5715_LED1_GPIO
- GTWX5715_LED2_GPIO
- GTWX5715_LED3_GPIO
- GTWX5715_LED4_GPIO
- GTWX5715_LED9_GPIO
- GTXTHRCFG
- GT_ACLK_USB3OTG
- GT_ADERR_OFS
- GT_AUTO_INC
- GT_BLT_CS_ERROR_INTERRUPT
- GT_BLT_FLUSHDW_NOTIFY_INTERRUPT
- GT_BLT_USER_INTERRUPT
- GT_BOOTHD_OFS
- GT_BOOTLD_OFS
- GT_BSD_CS_ERROR_INTERRUPT
- GT_BSD_USER_INTERRUPT
- GT_CFGADDR_BUSNUM_MSK
- GT_CFGADDR_BUSNUM_SHF
- GT_CFGADDR_CFGEN_BIT
- GT_CFGADDR_CFGEN_MSK
- GT_CFGADDR_CFGEN_SHF
- GT_CFGADDR_DEVNUM_MSK
- GT_CFGADDR_DEVNUM_SHF
- GT_CFGADDR_FUNCNUM_MSK
- GT_CFGADDR_FUNCNUM_SHF
- GT_CFGADDR_REGNUM_MSK
- GT_CFGADDR_REGNUM_SHF
- GT_CHIP_ID
- GT_CLK_USB3OTG_REF
- GT_COMP0
- GT_COMP1
- GT_CONTEXT_SWITCH_INTERRUPT
- GT_CONTROL
- GT_CONTROL_AUTO_INC
- GT_CONTROL_COMP_ENABLE
- GT_CONTROL_IRQ_ENABLE
- GT_CONTROL_TIMER_ENABLE
- GT_COUNTER0
- GT_COUNTER1
- GT_CPUERR_ADDRHI_OFS
- GT_CPUERR_ADDRLO_OFS
- GT_CPUERR_DATAHI_OFS
- GT_CPUERR_DATALO_OFS
- GT_CPUERR_PARITY_OFS
- GT_CPU_ENDIAN_BIT
- GT_CPU_ENDIAN_MSK
- GT_CPU_ENDIAN_SHF
- GT_CPU_INTSEL_OFS
- GT_CPU_OFS
- GT_CPU_WR_BIT
- GT_CPU_WR_DDDD
- GT_CPU_WR_DXDXDXDX
- GT_CPU_WR_MSK
- GT_CPU_WR_SHF
- GT_CS0HD_OFS
- GT_CS0LD_OFS
- GT_CS1HD_OFS
- GT_CS1LD_OFS
- GT_CS20HD_OFS
- GT_CS20LD_OFS
- GT_CS20R_OFS
- GT_CS2HD_OFS
- GT_CS2LD_OFS
- GT_CS3BOOTHD_OFS
- GT_CS3BOOTLD_OFS
- GT_CS3BOOTR_OFS
- GT_CS3HD_OFS
- GT_CS3LD_OFS
- GT_DEF_BASE
- GT_DEF_PCI0_IO_BASE
- GT_DEF_PCI0_IO_SIZE
- GT_DEF_PCI0_MEM0_BASE
- GT_DEF_PCI0_MEM0_SIZE
- GT_DEV_B0_OFS
- GT_DEV_B1_OFS
- GT_DEV_B2_OFS
- GT_DEV_B3_OFS
- GT_DEV_BOOT_OFS
- GT_DIR
- GT_DMA0_CNT_OFS
- GT_DMA0_CTRL_OFS
- GT_DMA0_CUR_OFS
- GT_DMA0_DA_OFS
- GT_DMA0_NEXT_OFS
- GT_DMA0_SA_OFS
- GT_DMA1_CNT_OFS
- GT_DMA1_CTRL_OFS
- GT_DMA1_CUR_OFS
- GT_DMA1_DA_OFS
- GT_DMA1_NEXT_OFS
- GT_DMA1_SA_OFS
- GT_DMA2_CNT_OFS
- GT_DMA2_CTRL_OFS
- GT_DMA2_CUR_OFS
- GT_DMA2_DA_OFS
- GT_DMA2_NEXT_OFS
- GT_DMA2_SA_OFS
- GT_DMA3_CNT_OFS
- GT_DMA3_CTRL_OFS
- GT_DMA3_CUR_OFS
- GT_DMA3_DA_OFS
- GT_DMA3_NEXT_OFS
- GT_DMA3_SA_OFS
- GT_DMA_ARB_OFS
- GT_DOORBELL_ENABLE
- GT_ECC_CALC
- GT_ECC_ERRADDR
- GT_ECC_ERRDATAHI
- GT_ECC_ERRDATALO
- GT_ECC_MEM
- GT_FIFO_BLOBDROPERR
- GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL
- GT_FIFO_CTL_RC6_POLICY_STALL
- GT_FIFO_DROPERR
- GT_FIFO_FREE_ENTRIES_CHV
- GT_FIFO_FREE_ENTRIES_MASK
- GT_FIFO_IARDERR
- GT_FIFO_IAWRERR
- GT_FIFO_NUM_RESERVED_ENTRIES
- GT_FIFO_OVFERR
- GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
- GT_FIFO_SBDROPERR
- GT_FIFO_SB_READ_ABORTERR
- GT_FIFO_TIMEOUT_MS
- GT_FREQUENCY_MULTIPLIER
- GT_HINTRCAUSE_OFS
- GT_HINTRMASK_OFS
- GT_INTERVAL_FROM_US
- GT_INTRCAUSE_MASABORT0_BIT
- GT_INTRCAUSE_MASABORT0_MSK
- GT_INTRCAUSE_MASABORT0_SHF
- GT_INTRCAUSE_OFS
- GT_INTRCAUSE_TARABORT0_BIT
- GT_INTRCAUSE_TARABORT0_MSK
- GT_INTRCAUSE_TARABORT0_SHF
- GT_INTRMASK_OFS
- GT_INTR_RETRYCTR0_BIT
- GT_INTR_RETRYCTR0_MSK
- GT_INTR_RETRYCTR0_SHF
- GT_INTR_T0EXP_BIT
- GT_INTR_T0EXP_MSK
- GT_INTR_T0EXP_SHF
- GT_INT_STATUS
- GT_INT_STATUS_EVENT_FLAG
- GT_ISA_IO_BASE
- GT_ISD_OFS
- GT_LATTIM_MIN
- GT_MANID
- GT_MANID2
- GT_MAX_BANKSIZE
- GT_MULTI_OFS
- GT_NOA_ENABLE
- GT_PARITY_ERROR
- GT_PCI0IOHD_OFS
- GT_PCI0IOLD_OFS
- GT_PCI0IOREMAP_OFS
- GT_PCI0M0HD_OFS
- GT_PCI0M0LD_OFS
- GT_PCI0M0REMAP_OFS
- GT_PCI0M1HD_OFS
- GT_PCI0M1LD_OFS
- GT_PCI0M1REMAP_OFS
- GT_PCI0SYNC_OFS
- GT_PCI0_BARE_CS20DIS_BIT
- GT_PCI0_BARE_CS20DIS_MSK
- GT_PCI0_BARE_CS20DIS_SHF
- GT_PCI0_BARE_CS3BOOTDIS_BIT
- GT_PCI0_BARE_CS3BOOTDIS_MSK
- GT_PCI0_BARE_CS3BOOTDIS_SHF
- GT_PCI0_BARE_INTIODIS_BIT
- GT_PCI0_BARE_INTIODIS_MSK
- GT_PCI0_BARE_INTIODIS_SHF
- GT_PCI0_BARE_INTMEMDIS_BIT
- GT_PCI0_BARE_INTMEMDIS_MSK
- GT_PCI0_BARE_INTMEMDIS_SHF
- GT_PCI0_BARE_OFS
- GT_PCI0_BARE_SCS10DIS_BIT
- GT_PCI0_BARE_SCS10DIS_MSK
- GT_PCI0_BARE_SCS10DIS_SHF
- GT_PCI0_BARE_SCS32DIS_BIT
- GT_PCI0_BARE_SCS32DIS_MSK
- GT_PCI0_BARE_SCS32DIS_SHF
- GT_PCI0_BARE_SWSCS10DIS_BIT
- GT_PCI0_BARE_SWSCS10DIS_MSK
- GT_PCI0_BARE_SWSCS10DIS_SHF
- GT_PCI0_BARE_SWSCS32DIS_BIT
- GT_PCI0_BARE_SWSCS32DIS_MSK
- GT_PCI0_BARE_SWSCS32DIS_SHF
- GT_PCI0_BARE_SWSCS3BOOTDIS_BIT
- GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
- GT_PCI0_BARE_SWSCS3BOOTDIS_SHF
- GT_PCI0_BS_CS20_OFS
- GT_PCI0_BS_CS3BT_OFS
- GT_PCI0_BS_SCS10_OFS
- GT_PCI0_BS_SCS32_OFS
- GT_PCI0_CFGADDR_BUSNUM_MSK
- GT_PCI0_CFGADDR_BUSNUM_SHF
- GT_PCI0_CFGADDR_CONFIGEN_BIT
- GT_PCI0_CFGADDR_CONFIGEN_MSK
- GT_PCI0_CFGADDR_CONFIGEN_SHF
- GT_PCI0_CFGADDR_DEVNUM_MSK
- GT_PCI0_CFGADDR_DEVNUM_SHF
- GT_PCI0_CFGADDR_FUNCTNUM_MSK
- GT_PCI0_CFGADDR_FUNCTNUM_SHF
- GT_PCI0_CFGADDR_OFS
- GT_PCI0_CFGADDR_REGNUM_MSK
- GT_PCI0_CFGADDR_REGNUM_SHF
- GT_PCI0_CFGDATA_OFS
- GT_PCI0_CMD_MBYTESWAP_BIT
- GT_PCI0_CMD_MBYTESWAP_MSK
- GT_PCI0_CMD_MBYTESWAP_SHF
- GT_PCI0_CMD_MWORDSWAP_BIT
- GT_PCI0_CMD_MWORDSWAP_MSK
- GT_PCI0_CMD_MWORDSWAP_SHF
- GT_PCI0_CMD_OFS
- GT_PCI0_CMD_SBYTESWAP_BIT
- GT_PCI0_CMD_SBYTESWAP_MSK
- GT_PCI0_CMD_SBYTESWAP_SHF
- GT_PCI0_CMD_SWORDSWAP_BIT
- GT_PCI0_CMD_SWORDSWAP_MSK
- GT_PCI0_CMD_SWORDSWAP_SHF
- GT_PCI0_CS20_BAR_OFS
- GT_PCI0_CS3BT_BAR_OFS
- GT_PCI0_HICMASK_OFS
- GT_PCI0_IACK_OFS
- GT_PCI0_ICMASK_OFS
- GT_PCI0_INTSEL_OFS
- GT_PCI0_PREFMBR_OFS
- GT_PCI0_SCS10_BAR_OFS
- GT_PCI0_SCS32_BAR_OFS
- GT_PCI0_SCS3BT_BAR_OFS
- GT_PCI0_SERR0MASK_OFS
- GT_PCI0_SSCS10_BAR_OFS
- GT_PCI0_SSCS32_BAR_OFS
- GT_PCI0_TOR_OFS
- GT_PCI1IOHD_OFS
- GT_PCI1IOLD_OFS
- GT_PCI1IOREMAP_OFS
- GT_PCI1M0HD_OFS
- GT_PCI1M0LD_OFS
- GT_PCI1M0REMAP_OFS
- GT_PCI1M1HD_OFS
- GT_PCI1M1LD_OFS
- GT_PCI1M1REMAP_OFS
- GT_PCI1SYNC_OFS
- GT_PCI1_BARE_OFS
- GT_PCI1_BS_CS20_OFS
- GT_PCI1_BS_CS3BT_OFS
- GT_PCI1_BS_SCS10_OFS
- GT_PCI1_BS_SCS32_OFS
- GT_PCI1_CFGADDR_OFS
- GT_PCI1_CFGDATA_OFS
- GT_PCI1_CMD_OFS
- GT_PCI1_CS20_BAR_OFS
- GT_PCI1_CS3BT_BAR_OFS
- GT_PCI1_IACK_OFS
- GT_PCI1_PREFMBR_OFS
- GT_PCI1_SCS10_BAR_OFS
- GT_PCI1_SCS32_BAR_OFS
- GT_PCI1_SCS3BT_BAR_OFS
- GT_PCI1_SERR1MASK_OFS
- GT_PCI1_SSCS10_BAR_OFS
- GT_PCI1_SSCS32_BAR_OFS
- GT_PCI1_TOR_OFS
- GT_PCI_DCRM_SHF
- GT_PCI_HD_MSK
- GT_PCI_HD_SHF
- GT_PCI_IO_BASE
- GT_PCI_IO_SIZE
- GT_PCI_LD_MSK
- GT_PCI_LD_SHF
- GT_PCI_MEM_BASE
- GT_PCI_MEM_SIZE
- GT_PCI_REMAP_MSK
- GT_PCI_REMAP_SHF
- GT_PIPE
- GT_PM_INTERVAL_TO_US
- GT_READ
- GT_RENDER_CS_MASTER_ERROR_INTERRUPT
- GT_RENDER_DEBUG_INTERRUPT
- GT_RENDER_L3_PARITY_ERROR_INTERRUPT
- GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1
- GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
- GT_RENDER_SYNC_STATUS_INTERRUPT
- GT_RENDER_USER_INTERRUPT
- GT_SCS0HD_OFS
- GT_SCS0LD_OFS
- GT_SCS10AR_OFS
- GT_SCS10HD_OFS
- GT_SCS10LD_OFS
- GT_SCS1HD_OFS
- GT_SCS1LD_OFS
- GT_SCS2HD_OFS
- GT_SCS2LD_OFS
- GT_SCS32AR_OFS
- GT_SCS32HD_OFS
- GT_SCS32LD_OFS
- GT_SCS3HD_OFS
- GT_SCS3LD_OFS
- GT_SDRAM_ADDRDECODE_ADDR_0
- GT_SDRAM_ADDRDECODE_ADDR_1
- GT_SDRAM_ADDRDECODE_ADDR_2
- GT_SDRAM_ADDRDECODE_ADDR_3
- GT_SDRAM_ADDRDECODE_ADDR_4
- GT_SDRAM_ADDRDECODE_ADDR_5
- GT_SDRAM_ADDRDECODE_ADDR_6
- GT_SDRAM_ADDRDECODE_ADDR_7
- GT_SDRAM_ADDRDECODE_ADDR_MSK
- GT_SDRAM_ADDRDECODE_ADDR_SHF
- GT_SDRAM_ADDRDECODE_OFS
- GT_SDRAM_B0_64BITINT_2
- GT_SDRAM_B0_64BITINT_4
- GT_SDRAM_B0_64BITINT_BIT
- GT_SDRAM_B0_64BITINT_MSK
- GT_SDRAM_B0_64BITINT_SHF
- GT_SDRAM_B0_B0COMPAB_BIT
- GT_SDRAM_B0_B0COMPAB_MSK
- GT_SDRAM_B0_B0COMPAB_SHF
- GT_SDRAM_B0_BLEN_4
- GT_SDRAM_B0_BLEN_8
- GT_SDRAM_B0_BLEN_BIT
- GT_SDRAM_B0_BLEN_MSK
- GT_SDRAM_B0_BLEN_SHF
- GT_SDRAM_B0_BLODD_BIT
- GT_SDRAM_B0_BLODD_MSK
- GT_SDRAM_B0_BLODD_SHF
- GT_SDRAM_B0_BW_32
- GT_SDRAM_B0_BW_64
- GT_SDRAM_B0_BW_BIT
- GT_SDRAM_B0_BW_MSK
- GT_SDRAM_B0_BW_SHF
- GT_SDRAM_B0_BYPASS_BIT
- GT_SDRAM_B0_BYPASS_MSK
- GT_SDRAM_B0_BYPASS_SHF
- GT_SDRAM_B0_CASLAT_2
- GT_SDRAM_B0_CASLAT_3
- GT_SDRAM_B0_CASLAT_MSK
- GT_SDRAM_B0_CASLAT_SHF
- GT_SDRAM_B0_EXTPAR_BIT
- GT_SDRAM_B0_EXTPAR_MSK
- GT_SDRAM_B0_EXTPAR_SHF
- GT_SDRAM_B0_FTDIS_BIT
- GT_SDRAM_B0_FTDIS_MSK
- GT_SDRAM_B0_FTDIS_SHF
- GT_SDRAM_B0_OFS
- GT_SDRAM_B0_PAR_BIT
- GT_SDRAM_B0_PAR_MSK
- GT_SDRAM_B0_PAR_SHF
- GT_SDRAM_B0_SIZE_16M
- GT_SDRAM_B0_SIZE_64M
- GT_SDRAM_B0_SIZE_BIT
- GT_SDRAM_B0_SIZE_MSK
- GT_SDRAM_B0_SIZE_SHF
- GT_SDRAM_B0_SRAS2SCAS_2
- GT_SDRAM_B0_SRAS2SCAS_3
- GT_SDRAM_B0_SRAS2SCAS_BIT
- GT_SDRAM_B0_SRAS2SCAS_MSK
- GT_SDRAM_B0_SRAS2SCAS_SHF
- GT_SDRAM_B0_SRASPRCHG_2
- GT_SDRAM_B0_SRASPRCHG_3
- GT_SDRAM_B0_SRASPRCHG_BIT
- GT_SDRAM_B0_SRASPRCHG_MSK
- GT_SDRAM_B0_SRASPRCHG_SHF
- GT_SDRAM_B1_OFS
- GT_SDRAM_B2_OFS
- GT_SDRAM_B3_OFS
- GT_SDRAM_BM_OFS
- GT_SDRAM_BM_ORDER_BIT
- GT_SDRAM_BM_ORDER_LIN
- GT_SDRAM_BM_ORDER_MSK
- GT_SDRAM_BM_ORDER_SHF
- GT_SDRAM_BM_ORDER_SUB
- GT_SDRAM_BM_RSVD_ALL1
- GT_SDRAM_CFG_DUPBA_BIT
- GT_SDRAM_CFG_DUPBA_MSK
- GT_SDRAM_CFG_DUPBA_SHF
- GT_SDRAM_CFG_DUPCNTL_BIT
- GT_SDRAM_CFG_DUPCNTL_MSK
- GT_SDRAM_CFG_DUPCNTL_SHF
- GT_SDRAM_CFG_DUPEOT0_BIT
- GT_SDRAM_CFG_DUPEOT0_MSK
- GT_SDRAM_CFG_DUPEOT0_SHF
- GT_SDRAM_CFG_DUPEOT1_BIT
- GT_SDRAM_CFG_DUPEOT1_MSK
- GT_SDRAM_CFG_DUPEOT1_SHF
- GT_SDRAM_CFG_NINTERLEAVE_BIT
- GT_SDRAM_CFG_NINTERLEAVE_MSK
- GT_SDRAM_CFG_NINTERLEAVE_SHF
- GT_SDRAM_CFG_NONSTAGREF_BIT
- GT_SDRAM_CFG_NONSTAGREF_MSK
- GT_SDRAM_CFG_NONSTAGREF_SHF
- GT_SDRAM_CFG_OFS
- GT_SDRAM_CFG_REFINT_MSK
- GT_SDRAM_CFG_REFINT_SHF
- GT_SDRAM_CFG_RMW_BIT
- GT_SDRAM_CFG_RMW_MSK
- GT_SDRAM_CFG_RMW_SHF
- GT_SDRAM_OPMODE_OFS
- GT_SDRAM_OPMODE_OP_CBR
- GT_SDRAM_OPMODE_OP_MODE
- GT_SDRAM_OPMODE_OP_MSK
- GT_SDRAM_OPMODE_OP_NOP
- GT_SDRAM_OPMODE_OP_NORMAL
- GT_SDRAM_OPMODE_OP_PRCHG
- GT_SDRAM_OPMODE_OP_SHF
- GT_SOCK
- GT_TC0_OFS
- GT_TC1_OFS
- GT_TC2_OFS
- GT_TC3_OFS
- GT_TC_CONTROL_ENTC0_BIT
- GT_TC_CONTROL_ENTC0_MSK
- GT_TC_CONTROL_ENTC0_SHF
- GT_TC_CONTROL_OFS
- GT_TC_CONTROL_SELTC0_BIT
- GT_TC_CONTROL_SELTC0_MSK
- GT_TC_CONTROL_SELTC0_SHF
- GT_WRITE
- GUARANTEED_PERF
- GUARD_BAND
- GUARD_BYTE
- GUARD_ERR
- GUARD_HOLE_BASE_ADDR
- GUARD_HOLE_END_ADDR
- GUARD_HOLE_PGD_ENTRY
- GUARD_HOLE_SIZE
- GUARD_INTERVAL_19_128
- GUARD_INTERVAL_19_256
- GUARD_INTERVAL_1_128
- GUARD_INTERVAL_1_16
- GUARD_INTERVAL_1_32
- GUARD_INTERVAL_1_4
- GUARD_INTERVAL_1_8
- GUARD_INTERVAL_AUTO
- GUARD_INTERVAL_PN420
- GUARD_INTERVAL_PN595
- GUARD_INTERVAL_PN945
- GUARD_INT_1_16
- GUARD_INT_1_32
- GUARD_INT_1_4
- GUARD_INT_1_8
- GUARD_UNKNOWN
- GUC_ADS_ADDR_MASK
- GUC_ADS_ADDR_SHIFT
- GUC_ARAT_C6DIS
- GUC_BCS_RCS_IER
- GUC_BLITTER_ENGINE
- GUC_CLIENT_PRIORITY_HIGH
- GUC_CLIENT_PRIORITY_KMD_HIGH
- GUC_CLIENT_PRIORITY_KMD_NORMAL
- GUC_CLIENT_PRIORITY_NORMAL
- GUC_CLIENT_PRIORITY_NUM
- GUC_CRASH_DUMP_LOG_BUFFER
- GUC_CTL_ADS
- GUC_CTL_BASE_ADDR_SHIFT
- GUC_CTL_CTXINFO
- GUC_CTL_CTXNUM_IN16_SHIFT
- GUC_CTL_DEBUG
- GUC_CTL_DISABLE_SCHEDULER
- GUC_CTL_FEATURE
- GUC_CTL_LOG_PARAMS
- GUC_CTL_MAX_DWORDS
- GUC_CTL_WA
- GUC_CT_MSG_ACTION_MASK
- GUC_CT_MSG_ACTION_SHIFT
- GUC_CT_MSG_IS_RESPONSE
- GUC_CT_MSG_LEN_MASK
- GUC_CT_MSG_LEN_SHIFT
- GUC_CT_MSG_SEND_STATUS
- GUC_CT_MSG_WRITE_FENCE_TO_DESC
- GUC_CT_MSG_WRITE_STATUS_TO_BUFF
- GUC_CT_POOL_SIZE
- GUC_DB_SIZE
- GUC_DISABLE_SRAM_INIT_TO_ZEROES
- GUC_DOORBELL_DISABLED
- GUC_DOORBELL_ENABLED
- GUC_DOORBELL_INVALID
- GUC_DPC_LOG_BUFFER
- GUC_ELC_CTXID_OFFSET
- GUC_ELC_ENGINE_OFFSET
- GUC_ENABLE_MIA_CACHING
- GUC_ENABLE_MIA_CLOCK_GATING
- GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA
- GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA
- GUC_ENABLE_READ_CACHE_LOGIC
- GUC_FORCEWAKE_MEDIA
- GUC_FORCEWAKE_RENDER
- GUC_FW_BLOB
- GUC_GEN10_MSGCH_ENABLE
- GUC_GEN10_SHIM_WC_ENABLE
- GUC_GGTT_TOP
- GUC_INTR_DISPLAY_EVENT
- GUC_INTR_DMA_DONE
- GUC_INTR_DOORBELL_RANG
- GUC_INTR_EXEC_ERROR
- GUC_INTR_FATAL_ERROR
- GUC_INTR_GUC2HOST
- GUC_INTR_IOMMU2GUC
- GUC_INTR_NOTIF_ERROR
- GUC_INTR_SEM_SIG
- GUC_INTR_SW_INT_0
- GUC_INTR_SW_INT_1
- GUC_INTR_SW_INT_2
- GUC_INTR_SW_INT_3
- GUC_INTR_SW_INT_4
- GUC_INTR_SW_INT_5
- GUC_INTR_SW_INT_6
- GUC_INVALID_STAGE_ID
- GUC_ISR_LOG_BUFFER
- GUC_LOG_ALLOC_IN_MEGABYTE
- GUC_LOG_BUF_ADDR_SHIFT
- GUC_LOG_CONTROL_DEFAULT_LOGGING
- GUC_LOG_CONTROL_LOGGING_ENABLED
- GUC_LOG_CONTROL_VERBOSITY_MASK
- GUC_LOG_CONTROL_VERBOSITY_SHIFT
- GUC_LOG_CRASH_MASK
- GUC_LOG_CRASH_SHIFT
- GUC_LOG_DESTINATION_MASK
- GUC_LOG_DISABLED
- GUC_LOG_DPC_MASK
- GUC_LOG_DPC_SHIFT
- GUC_LOG_ISR_MASK
- GUC_LOG_ISR_SHIFT
- GUC_LOG_LEVEL_DISABLED
- GUC_LOG_LEVEL_IS_ENABLED
- GUC_LOG_LEVEL_IS_VERBOSE
- GUC_LOG_LEVEL_MAX
- GUC_LOG_LEVEL_NON_VERBOSE
- GUC_LOG_LEVEL_TO_VERBOSITY
- GUC_LOG_NOTIFY_ON_HALF_FULL
- GUC_LOG_VALID
- GUC_LOG_VERBOSITY_HIGH
- GUC_LOG_VERBOSITY_LOW
- GUC_LOG_VERBOSITY_MASK
- GUC_LOG_VERBOSITY_MAX
- GUC_LOG_VERBOSITY_MED
- GUC_LOG_VERBOSITY_MIN
- GUC_LOG_VERBOSITY_SHIFT
- GUC_LOG_VERBOSITY_ULTRA
- GUC_MAX_ENGINES_NUM
- GUC_MAX_ENGINE_CLASSES
- GUC_MAX_IDLE_COUNT
- GUC_MAX_INSTANCES_PER_CLASS
- GUC_MAX_LOG_BUFFER
- GUC_MAX_MMIO_MSG_LEN
- GUC_MAX_STAGE_DESCRIPTORS
- GUC_NUM_DOORBELLS
- GUC_PM_P24C_IER
- GUC_POWER_D0
- GUC_POWER_D1
- GUC_POWER_D2
- GUC_POWER_D3
- GUC_POWER_UNSPECIFIED
- GUC_PREEMPT_BREADCRUMB_BYTES
- GUC_PREEMPT_BREADCRUMB_DWORDS
- GUC_PREEMPT_FINISHED
- GUC_PREEMPT_INPROGRESS
- GUC_PREEMPT_NONE
- GUC_PROFILE_ENABLED
- GUC_REGSET_MASKED
- GUC_REGSET_MAX_REGISTERS
- GUC_RENDER_ENGINE
- GUC_S3_SAVE_SPACE_PAGES
- GUC_SEND_INTERRUPT
- GUC_SEND_TRIGGER
- GUC_SHIM_CONTROL
- GUC_STAGE_DESC_ATTR_ACTIVE
- GUC_STAGE_DESC_ATTR_KERNEL
- GUC_STAGE_DESC_ATTR_PCH
- GUC_STAGE_DESC_ATTR_PENDING_DB
- GUC_STAGE_DESC_ATTR_PREEMPT
- GUC_STAGE_DESC_ATTR_RESET
- GUC_STAGE_DESC_ATTR_TERMINATED
- GUC_STAGE_DESC_ATTR_WQLOCKED
- GUC_STATUS
- GUC_VCS2_VCS1_IER
- GUC_VERBOSITY_TO_LOG_LEVEL
- GUC_VIDEOENHANCE_ENGINE
- GUC_VIDEO_ENGINE
- GUC_VIDEO_ENGINE2
- GUC_WD_VECS_IER
- GUC_WOPCM_OFFSET_ALIGNMENT
- GUC_WOPCM_OFFSET_MASK
- GUC_WOPCM_OFFSET_SHIFT
- GUC_WOPCM_OFFSET_VALID
- GUC_WOPCM_RESERVED
- GUC_WOPCM_SIZE
- GUC_WOPCM_SIZE_LOCKED
- GUC_WOPCM_SIZE_MASK
- GUC_WOPCM_SIZE_SHIFT
- GUC_WOPCM_STACK_RESERVED
- GUC_WQ_SIZE
- GUESTMSG_FLAG_COOKIE
- GUEST_ACTIVITY_ACTIVE
- GUEST_ACTIVITY_HLT
- GUEST_ACTIVITY_SHUTDOWN
- GUEST_ACTIVITY_STATE
- GUEST_ACTIVITY_WAIT_SIPI
- GUEST_ASSERT
- GUEST_BNDCFGS
- GUEST_BNDCFGS_HIGH
- GUEST_CODE_CONTAINER
- GUEST_CODE_PARTITION
- GUEST_CR0
- GUEST_CR3
- GUEST_CR4
- GUEST_CS_AR_BYTES
- GUEST_CS_BASE
- GUEST_CS_LIMIT
- GUEST_CS_SELECTOR
- GUEST_DONE
- GUEST_DOORBELL_EXCEPTION
- GUEST_DR7
- GUEST_DS_AR_BYTES
- GUEST_DS_BASE
- GUEST_DS_LIMIT
- GUEST_DS_SELECTOR
- GUEST_ES_AR_BYTES
- GUEST_ES_BASE
- GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
- GUEST_FS_AR_BYTES
- GUEST_FS_BASE
- GUEST_FS_LIMIT
- GUEST_FS_SELECTOR
- GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
- GUEST_GS_AR_BYTES
- GUEST_GS_BASE
- GUEST_GS_LIMIT
- GUEST_GS_SELECTOR
- GUEST_HEAP_OFFSET
- GUEST_HEAP_SIZE
- GUEST_HEAP_USABLE_SIZE
- GUEST_IA32_DEBUGCTL
- GUEST_IA32_DEBUGCTL_HIGH
- GUEST_IA32_EFER
- GUEST_IA32_EFER_HIGH
- GUEST_IA32_PAT
- GUEST_IA32_PAT_HIGH
- GUEST_IA32_PERF_GLOBAL_CTRL
- GUEST_IA32_PERF_GLOBAL_CTRL_HIGH
- GUEST_IA32_RTIT_CTL
- GUEST_IA32_RTIT_CTL_HIGH
- GUEST_IDTR_BASE
- GUEST_IDTR_LIMIT
- GUEST_INTERRUPTIBILITY_INFO
- GUEST_INTR_STATE_MOV_SS
- GUEST_INTR_STATE_NMI
- GUEST_INTR_STATE_SMI
- GUEST_INTR_STATE_STI
- GUEST_INTR_STATUS
- GUEST_LDTR_AR_BYTES
- GUEST_LDTR_BASE
- GUEST_LDTR_LIMIT
- GUEST_LDTR_SELECTOR
- GUEST_LINEAR_ADDRESS
- GUEST_LOGIN
- GUEST_MAPPINGS_TRIES
- GUEST_PDPTR0
- GUEST_PDPTR0_HIGH
- GUEST_PDPTR1
- GUEST_PDPTR1_HIGH
- GUEST_PDPTR2
- GUEST_PDPTR2_HIGH
- GUEST_PDPTR3
- GUEST_PDPTR3_HIGH
- GUEST_PENDING_DBG_EXCEPTIONS
- GUEST_PHYSICAL_ADDRESS
- GUEST_PHYSICAL_ADDRESS_HIGH
- GUEST_PML_INDEX
- GUEST_PREFIX_SHIFT
- GUEST_RFLAGS
- GUEST_RIP
- GUEST_RSP
- GUEST_SERIALIZATION_CONTAINER
- GUEST_SERIALIZATION_PARTITION
- GUEST_SS_AR_BYTES
- GUEST_SS_BASE
- GUEST_SS_LIMIT
- GUEST_SS_SELECTOR
- GUEST_SYNC
- GUEST_SYSENTER_CS
- GUEST_SYSENTER_EIP
- GUEST_SYSENTER_ESP
- GUEST_TEST_MEM
- GUEST_TR_AR_BYTES
- GUEST_TR_BASE
- GUEST_TR_LIMIT
- GUEST_TR_SELECTOR
- GUE_FLAGS_ALL
- GUE_FLAG_PRIV
- GUE_LEN_PRIV
- GUE_PFLAGS_ALL
- GUE_PFLAG_REMCSUM
- GUE_PLEN_REMCSUM
- GUID
- GUIDINFO_REC_FIELD
- GUID_H
- GUID_HFI_INDEX_SHIFT
- GUID_INIT
- GUID_L
- GUID_LEN
- GUID_REC_SIZE
- GUID_STATE_NEED_PORT_INIT
- GUID_TBL_BLK_NUM_ENTRIES
- GUID_TBL_BLK_SIZE
- GUID_TBL_ENTRY_SIZE
- GUILLEMOT_MAX_LENGTH
- GUILLEMOT_MAX_START
- GUILLEMOT_MAX_STROBE
- GUI_ACTIVE
- GUI_CMDFIFO_DATA
- GUI_CMDFIFO_DEBUG
- GUI_CNTL
- GUI_DEBUG0
- GUI_DEBUG1
- GUI_ENGINE_ENABLE
- GUI_IDLE_INT_ENABLE
- GUI_MODE
- GUI_PROBE
- GUI_RESERVE
- GUI_SCRATCH_REG0
- GUI_SCRATCH_REG1
- GUI_SCRATCH_REG2
- GUI_SCRATCH_REG3
- GUI_SCRATCH_REG4
- GUI_SCRATCH_REG5
- GUI_STAT
- GUI_TIMEOUT
- GUI_TIMEOUT0
- GUI_TIMEOUT1
- GUI_TRAJ_CNTL
- GUMSTIX_ETH0_IRQ
- GUMSTIX_ETH1_IRQ
- GUMSTIX_GPIO_nSD_DETECT
- GUMSTIX_GPIO_nSD_WP
- GUMSTIX_IRQ_GPIO_nSD_DETECT
- GUMSTIX_S0_PRDY_nBSY_IRQ
- GUMSTIX_S0_nCD_IRQ
- GUMSTIX_S0_nSTSCHG_IRQ
- GUMSTIX_S1_PRDY_nBSY_IRQ
- GUMSTIX_S1_nCD_IRQ
- GUMSTIX_S1_nSTSCHG_IRQ
- GUMSTIX_USB_INTR_IRQ
- GUNS
- GUNZE_MAX_LENGTH
- GUNZIP_BUF
- GUNZIP_OUTLEN
- GUNZIP_PHYS
- GUP_BENCHMARK
- GUP_FAST_BENCHMARK
- GUP_LONGTERM_BENCHMARK
- GUSBCFG
- GUSBCFG_DDRSEL
- GUSBCFG_FORCEDEVMODE
- GUSBCFG_FORCEHOSTMODE
- GUSBCFG_FSINTF
- GUSBCFG_HNPCAP
- GUSBCFG_ICTRAFFICPULLREMOVE
- GUSBCFG_ICUSBCAP
- GUSBCFG_INDICATORCOMPLEMENT
- GUSBCFG_INDICATORPASSTHROUGH
- GUSBCFG_OTG_UTMI_FS_SEL
- GUSBCFG_PHYIF16
- GUSBCFG_PHYIF8
- GUSBCFG_PHYSEL
- GUSBCFG_PHY_LP_CLK_SEL
- GUSBCFG_SRPCAP
- GUSBCFG_TERMSELDLPULSE
- GUSBCFG_TOUTCAL
- GUSBCFG_TOUTCAL_LIMIT
- GUSBCFG_TOUTCAL_MASK
- GUSBCFG_TOUTCAL_SHIFT
- GUSBCFG_TXENDDELAY
- GUSBCFG_ULPI_AUTO_RES
- GUSBCFG_ULPI_CLK_SUSP_M
- GUSBCFG_ULPI_EXT_VBUS_DRV
- GUSBCFG_ULPI_FS_LS
- GUSBCFG_ULPI_INT_PROT_DIS
- GUSBCFG_ULPI_INT_VBUS_IND
- GUSBCFG_ULPI_UTMI_SEL
- GUSBCFG_USBTRDTIM_MASK
- GUSBCFG_USBTRDTIM_SHIFT
- GUSP
- GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
- GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
- GUS_CGTT_CLK_CTRL__ON_DELAY_MASK
- GUS_CGTT_CLK_CTRL__ON_DELAY__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM_MASK
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK
- GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM_MASK
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK
- GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT
- GUS_CGTT_CLK_CTRL__SPARE0_MASK
- GUS_CGTT_CLK_CTRL__SPARE0__SHIFT
- GUS_CGTT_CLK_CTRL__SPARE1_MASK
- GUS_CGTT_CLK_CTRL__SPARE1__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT
- GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK
- GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK
- GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT
- GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK
- GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT
- GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK
- GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK
- GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT
- GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK
- GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK
- GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK
- GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK
- GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK
- GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT
- GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK
- GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT
- GUS_ERR_STATUS__BUSY_ON_ERROR_MASK
- GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT
- GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK
- GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT
- GUS_ERR_STATUS__FUE_FLAG_MASK
- GUS_ERR_STATUS__FUE_FLAG__SHIFT
- GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK
- GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT
- GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK
- GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT
- GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK
- GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT
- GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK
- GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT
- GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK
- GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT
- GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK
- GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT
- GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK
- GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT
- GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK
- GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT
- GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK
- GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK
- GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK
- GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK
- GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK
- GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK
- GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK
- GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK
- GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT
- GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK
- GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK
- GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK
- GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK
- GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK
- GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK
- GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK
- GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK
- GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT
- GUS_L1_CH0_CMD_IN__COUNT_MASK
- GUS_L1_CH0_CMD_IN__COUNT__SHIFT
- GUS_L1_CH0_CMD_OUT__COUNT_MASK
- GUS_L1_CH0_CMD_OUT__COUNT__SHIFT
- GUS_L1_CH0_DATA_IN__COUNT_MASK
- GUS_L1_CH0_DATA_IN__COUNT__SHIFT
- GUS_L1_CH0_DATA_OUT__COUNT_MASK
- GUS_L1_CH0_DATA_OUT__COUNT__SHIFT
- GUS_L1_CH1_CMD_IN__COUNT_MASK
- GUS_L1_CH1_CMD_IN__COUNT__SHIFT
- GUS_L1_CH1_CMD_OUT__COUNT_MASK
- GUS_L1_CH1_CMD_OUT__COUNT__SHIFT
- GUS_L1_CH1_DATA_IN__COUNT_MASK
- GUS_L1_CH1_DATA_IN__COUNT__SHIFT
- GUS_L1_CH1_DATA_OUT__COUNT_MASK
- GUS_L1_CH1_DATA_OUT__COUNT__SHIFT
- GUS_L1_SA0_CMD_IN__COUNT_MASK
- GUS_L1_SA0_CMD_IN__COUNT__SHIFT
- GUS_L1_SA0_CMD_OUT__COUNT_MASK
- GUS_L1_SA0_CMD_OUT__COUNT__SHIFT
- GUS_L1_SA0_DATA_IN__COUNT_MASK
- GUS_L1_SA0_DATA_IN__COUNT__SHIFT
- GUS_L1_SA0_DATA_OUT__COUNT_MASK
- GUS_L1_SA0_DATA_OUT__COUNT__SHIFT
- GUS_L1_SA0_DATA_U_IN__COUNT_MASK
- GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT
- GUS_L1_SA0_DATA_U_OUT__COUNT_MASK
- GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT
- GUS_L1_SA1_CMD_IN__COUNT_MASK
- GUS_L1_SA1_CMD_IN__COUNT__SHIFT
- GUS_L1_SA1_CMD_OUT__COUNT_MASK
- GUS_L1_SA1_CMD_OUT__COUNT__SHIFT
- GUS_L1_SA1_DATA_IN__COUNT_MASK
- GUS_L1_SA1_DATA_IN__COUNT__SHIFT
- GUS_L1_SA1_DATA_OUT__COUNT_MASK
- GUS_L1_SA1_DATA_OUT__COUNT__SHIFT
- GUS_L1_SA1_DATA_U_IN__COUNT_MASK
- GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT
- GUS_L1_SA1_DATA_U_OUT__COUNT_MASK
- GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT
- GUS_L1_SA2_CMD_IN__COUNT_MASK
- GUS_L1_SA2_CMD_IN__COUNT__SHIFT
- GUS_L1_SA2_CMD_OUT__COUNT_MASK
- GUS_L1_SA2_CMD_OUT__COUNT__SHIFT
- GUS_L1_SA2_DATA_IN__COUNT_MASK
- GUS_L1_SA2_DATA_IN__COUNT__SHIFT
- GUS_L1_SA2_DATA_OUT__COUNT_MASK
- GUS_L1_SA2_DATA_OUT__COUNT__SHIFT
- GUS_L1_SA2_DATA_U_IN__COUNT_MASK
- GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT
- GUS_L1_SA2_DATA_U_OUT__COUNT_MASK
- GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT
- GUS_L1_SA3_CMD_IN__COUNT_MASK
- GUS_L1_SA3_CMD_IN__COUNT__SHIFT
- GUS_L1_SA3_CMD_OUT__COUNT_MASK
- GUS_L1_SA3_CMD_OUT__COUNT__SHIFT
- GUS_L1_SA3_DATA_IN__COUNT_MASK
- GUS_L1_SA3_DATA_IN__COUNT__SHIFT
- GUS_L1_SA3_DATA_OUT__COUNT_MASK
- GUS_L1_SA3_DATA_OUT__COUNT__SHIFT
- GUS_L1_SA3_DATA_U_IN__COUNT_MASK
- GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT
- GUS_L1_SA3_DATA_U_OUT__COUNT_MASK
- GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK
- GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT
- GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK
- GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT
- GUS_MISC2__CH_L1_PERF_MASK_MASK
- GUS_MISC2__CH_L1_PERF_MASK__SHIFT
- GUS_MISC2__CH_L1_RO_MASK_MASK
- GUS_MISC2__CH_L1_RO_MASK__SHIFT
- GUS_MISC2__FGCLKEN_HIGH_MASK
- GUS_MISC2__FGCLKEN_HIGH__SHIFT
- GUS_MISC2__FP_ATOMICS_ENABLE_MASK
- GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT
- GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK
- GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT
- GUS_MISC2__L1_RET_CLKEN_MASK
- GUS_MISC2__L1_RET_CLKEN__SHIFT
- GUS_MISC2__SA0_L1_PERF_MASK_MASK
- GUS_MISC2__SA0_L1_PERF_MASK__SHIFT
- GUS_MISC2__SA0_L1_RO_MASK_MASK
- GUS_MISC2__SA0_L1_RO_MASK__SHIFT
- GUS_MISC2__SA1_L1_PERF_MASK_MASK
- GUS_MISC2__SA1_L1_PERF_MASK__SHIFT
- GUS_MISC2__SA1_L1_RO_MASK_MASK
- GUS_MISC2__SA1_L1_RO_MASK__SHIFT
- GUS_MISC2__SA2_L1_PERF_MASK_MASK
- GUS_MISC2__SA2_L1_PERF_MASK__SHIFT
- GUS_MISC2__SA2_L1_RO_MASK_MASK
- GUS_MISC2__SA2_L1_RO_MASK__SHIFT
- GUS_MISC2__SA3_L1_PERF_MASK_MASK
- GUS_MISC2__SA3_L1_PERF_MASK__SHIFT
- GUS_MISC2__SA3_L1_RO_MASK_MASK
- GUS_MISC2__SA3_L1_RO_MASK__SHIFT
- GUS_MISC__EARLY_SDP_ORIGDATA_MASK
- GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT
- GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK
- GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT
- GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK
- GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT
- GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK
- GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT
- GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK
- GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT
- GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK
- GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT
- GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK
- GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT
- GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK
- GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT
- GUS_MISC__SEND0_IOWR_ONLY_MASK
- GUS_MISC__SEND0_IOWR_ONLY__SHIFT
- GUS_NUMVOICES
- GUS_PATCH
- GUS_PERFCOUNTER0_CFG__CLEAR_MASK
- GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT
- GUS_PERFCOUNTER0_CFG__ENABLE_MASK
- GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT
- GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK
- GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK
- GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- GUS_PERFCOUNTER1_CFG__CLEAR_MASK
- GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT
- GUS_PERFCOUNTER1_CFG__ENABLE_MASK
- GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT
- GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK
- GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK
- GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK
- GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT
- GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- GUS_PERFCOUNTER_HI__COUNTER_HI_MASK
- GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- GUS_PERFCOUNTER_LO__COUNTER_LO_MASK
- GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- GUS_RAMPMODE
- GUS_RAMPOFF
- GUS_RAMPON
- GUS_RAMPRANGE
- GUS_RAMPRATE
- GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK
- GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT
- GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK
- GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT
- GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK
- GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT
- GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK
- GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT
- GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK
- GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT
- GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK
- GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT
- GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK
- GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT
- GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK
- GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT
- GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK
- GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT
- GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK
- GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT
- GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK
- GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT
- GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK
- GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT
- GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK
- GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT
- GUS_SDP_CREDITS__TAG_LIMIT_MASK
- GUS_SDP_CREDITS__TAG_LIMIT__SHIFT
- GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK
- GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT
- GUS_SDP_ENABLE__ENABLE_MASK
- GUS_SDP_ENABLE__ENABLE__SHIFT
- GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK
- GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT
- GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK
- GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT
- GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK
- GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT
- GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK
- GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT
- GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK
- GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT
- GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK
- GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK
- GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT
- GUS_SDP_TAG_RESERVE0__VC0_MASK
- GUS_SDP_TAG_RESERVE0__VC0__SHIFT
- GUS_SDP_TAG_RESERVE0__VC1_MASK
- GUS_SDP_TAG_RESERVE0__VC1__SHIFT
- GUS_SDP_TAG_RESERVE0__VC2_MASK
- GUS_SDP_TAG_RESERVE0__VC2__SHIFT
- GUS_SDP_TAG_RESERVE0__VC3_MASK
- GUS_SDP_TAG_RESERVE0__VC3__SHIFT
- GUS_SDP_TAG_RESERVE1__VC4_MASK
- GUS_SDP_TAG_RESERVE1__VC4__SHIFT
- GUS_SDP_TAG_RESERVE1__VC5_MASK
- GUS_SDP_TAG_RESERVE1__VC5__SHIFT
- GUS_SDP_TAG_RESERVE1__VC6_MASK
- GUS_SDP_TAG_RESERVE1__VC6__SHIFT
- GUS_SDP_TAG_RESERVE1__VC7_MASK
- GUS_SDP_TAG_RESERVE1__VC7__SHIFT
- GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK
- GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK
- GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK
- GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK
- GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK
- GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK
- GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT
- GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK
- GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK
- GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT
- GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK
- GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK
- GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK
- GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK
- GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK
- GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK
- GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK
- GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT
- GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK
- GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK
- GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT
- GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK
- GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT
- GUS_VOICEBALA
- GUS_VOICEFADE
- GUS_VOICEFREQ
- GUS_VOICEMODE
- GUS_VOICEOFF
- GUS_VOICEON
- GUS_VOICESAMPLE
- GUS_VOICEVOL
- GUS_VOICEVOL2
- GUS_VOICE_POS
- GUS_VOLUME_SCALE
- GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK
- GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT
- GU_CHIP_ID
- GV100
- GV100_DISP
- GV100_DISP_CORE_CHANNEL_DMA
- GV100_DISP_CURSOR
- GV100_DISP_WINDOW_CHANNEL_DMA
- GV100_DISP_WINDOW_IMM_CHANNEL_DMA
- GVBB
- GVBB_I2C
- GVE_ADMINQ_COMMAND_ERROR_ABORTED
- GVE_ADMINQ_COMMAND_ERROR_ALREADY_EXISTS
- GVE_ADMINQ_COMMAND_ERROR_CANCELLED
- GVE_ADMINQ_COMMAND_ERROR_DATALOSS
- GVE_ADMINQ_COMMAND_ERROR_DEADLINE_EXCEEDED
- GVE_ADMINQ_COMMAND_ERROR_FAILED_PRECONDITION
- GVE_ADMINQ_COMMAND_ERROR_INTERNAL_ERROR
- GVE_ADMINQ_COMMAND_ERROR_INVALID_ARGUMENT
- GVE_ADMINQ_COMMAND_ERROR_NOT_FOUND
- GVE_ADMINQ_COMMAND_ERROR_OUT_OF_RANGE
- GVE_ADMINQ_COMMAND_ERROR_PERMISSION_DENIED
- GVE_ADMINQ_COMMAND_ERROR_RESOURCE_EXHAUSTED
- GVE_ADMINQ_COMMAND_ERROR_UNAUTHENTICATED
- GVE_ADMINQ_COMMAND_ERROR_UNAVAILABLE
- GVE_ADMINQ_COMMAND_ERROR_UNIMPLEMENTED
- GVE_ADMINQ_COMMAND_ERROR_UNKNOWN_ERROR
- GVE_ADMINQ_COMMAND_PASSED
- GVE_ADMINQ_COMMAND_UNSET
- GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES
- GVE_ADMINQ_CREATE_RX_QUEUE
- GVE_ADMINQ_CREATE_TX_QUEUE
- GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES
- GVE_ADMINQ_DESCRIBE_DEVICE
- GVE_ADMINQ_DESTROY_RX_QUEUE
- GVE_ADMINQ_DESTROY_TX_QUEUE
- GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION
- GVE_ADMINQ_REGISTER_PAGE_LIST
- GVE_ADMINQ_SET_DRIVER_PARAMETER
- GVE_ADMINQ_SLEEP_LEN
- GVE_ADMINQ_UNREGISTER_PAGE_LIST
- GVE_DEFAULT_RX_COPYBREAK
- GVE_DEVICE_STATUS_LINK_STATUS_MASK
- GVE_DEVICE_STATUS_RESET_MASK
- GVE_DOORBELL_BAR
- GVE_IRQ_ACK
- GVE_IRQ_EVENT
- GVE_IRQ_MASK
- GVE_MAIN_STATS_LEN
- GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK
- GVE_MAX_ADMINQ_RELEASE_CHECK
- GVE_MIN_MSIX
- GVE_NTFY_BLK_BASE_MSIX_IDX
- GVE_PRIV_FLAGS_ADMIN_QUEUE_OK
- GVE_PRIV_FLAGS_DEVICE_RESOURCES_OK
- GVE_PRIV_FLAGS_DEVICE_RINGS_OK
- GVE_PRIV_FLAGS_DO_RESET
- GVE_PRIV_FLAGS_NAPI_ENABLED
- GVE_PRIV_FLAGS_PROBE_IN_PROGRESS
- GVE_PRIV_FLAGS_RESET_IN_PROGRESS
- GVE_REGISTER_BAR
- GVE_RXFLG
- GVE_RXF_ERR
- GVE_RXF_FRAG
- GVE_RXF_IPV4
- GVE_RXF_IPV6
- GVE_RXF_TCP
- GVE_RXF_UDP
- GVE_RX_PAD
- GVE_SEQNO
- GVE_SET_PARAM_MTU
- GVE_TXD_SEG
- GVE_TXD_STD
- GVE_TXD_TSO
- GVE_TXF_L4CSUM
- GVE_TXF_TSTAMP
- GVE_TXSF_IPV6
- GVE_TX_MAX_IOVEC
- GVE_TX_START_THRESH
- GVE_VERSION
- GVE_VERSION_PREFIX
- GVP11_DMAC_BUSY
- GVP11_DMAC_DIR_WRITE
- GVP11_DMAC_INT_ENABLE
- GVP11_DMAC_INT_PENDING
- GVP11_XFER_MASK
- GVP_14MHZ
- GVP_24BITDMA
- GVP_25BITDMA
- GVP_ACCEL
- GVP_IO
- GVP_NOBANK
- GVP_PRODMASK
- GVP_SCSI
- GVP_SCSICLKMASK
- GVP_flags
- GVRF
- GVRP_ATTR_INVALID
- GVRP_ATTR_MAX
- GVRP_ATTR_VID
- GVT_AUX_I2C_MOT
- GVT_AUX_I2C_READ
- GVT_AUX_I2C_REPLY_ACK
- GVT_AUX_I2C_STATUS
- GVT_AUX_I2C_WRITE
- GVT_AUX_NATIVE_READ
- GVT_AUX_NATIVE_WRITE
- GVT_CMD_HASH_BITS
- GVT_CMD_STR_LEN
- GVT_CRT
- GVT_DEFAULT_TIME_SLICE
- GVT_DP_A
- GVT_DP_B
- GVT_DP_C
- GVT_DP_D
- GVT_EDID_1024_768
- GVT_EDID_1920_1200
- GVT_EDID_NUM
- GVT_FAILSAFE_GUEST_ERR
- GVT_FAILSAFE_INSUFFICIENT_RESOURCE
- GVT_FAILSAFE_UNSUPPORTED_GUEST
- GVT_FB_EVENT
- GVT_FIRMWARE_PATH
- GVT_GEN8_MMIO_RESET_OFFSET
- GVT_HDMI_B
- GVT_HDMI_C
- GVT_HDMI_D
- GVT_MAX_VGPU
- GVT_OPREGION_FUNC
- GVT_OPREGION_SUBFUNC
- GVT_PORT_MAX
- GVT_RING_CTX_NR_PDPS
- GVT_SCHED_VGPU_PRI_TIME
- GVT_TEMP_STR_LEN
- GVT_TS_BALANCE_PERIOD_MS
- GVT_TS_BALANCE_STAGE_NUM
- GV_CHIP_ID
- GWMR
- GWSR
- GWUNIT_CLKGATE_DIS
- GW_CHIP_ID
- GX00_XMISCCTRL_MFC_DIS
- GX00_XMISCCTRL_MFC_MAFC
- GX00_XMISCCTRL_MFC_MASK
- GX00_XMISCCTRL_MFC_PANELLINK
- GX6605S_CONFIG_EN
- GX6605S_CONFIG_IRQ_EN
- GX6605S_CONTRL_RST
- GX6605S_CONTRL_START
- GX6605S_STATUS_CLR
- GXBB_AO_GATE
- GXBB_WDT_CTRL_CLKDIV_EN
- GXBB_WDT_CTRL_CLK_EN
- GXBB_WDT_CTRL_DIV_MASK
- GXBB_WDT_CTRL_EE_RESET
- GXBB_WDT_CTRL_EN
- GXBB_WDT_CTRL_REG
- GXBB_WDT_RSET_REG
- GXBB_WDT_TCNT_CNT_SHIFT
- GXBB_WDT_TCNT_REG
- GXBB_WDT_TCNT_SETUP_MASK
- GXT4000P
- GXT4500P
- GXT6000P
- GXT6500P
- GXTALOUT_SELECT_DIV4
- GXTALOUT_SELECT_NO_GATING
- GX_CHIP_ID
- GX_INTC_NEN31_00
- GX_INTC_NEN63_32
- GX_INTC_NMASK31_00
- GX_INTC_NMASK63_32
- GX_INTC_PEN31_00
- GX_INTC_PEN63_32
- GX_INTC_SOURCE
- GX_PCI_ID
- GYRO_3D_CHANNEL_MAX
- GZERO_BULK_BUFLEN
- GZERO_ISOC_INTERVAL
- GZERO_ISOC_MAXPACKET
- GZERO_QLEN
- GZERO_SS_BULK_QLEN
- GZERO_SS_ISO_QLEN
- GZIP_FORMAT
- GZIP_HEAD_FCOMMENT_BIT
- GZIP_HEAD_FEXTRA_BIT
- GZIP_HEAD_FEXTRA_SHIFT
- GZIP_HEAD_FEXTRA_XLEN
- GZIP_HEAD_FHCRC_BIT
- GZIP_HEAD_FHCRC_SIZE
- GZIP_HEAD_FLG_SHIFT
- GZIP_HEAD_FNAME_BIT
- GZIP_IOBUF_SIZE
- GZ_CHIP_ID
- G_000000_MC_IDLE
- G_000001_MC_FB_START
- G_000001_MC_FB_TOP
- G_000002_MC_AGP_START
- G_000002_MC_AGP_TOP
- G_000003_AGP_BASE_ADDR
- G_000004_AGP_BASE_ADDR_2
- G_000004_MC_FB_START
- G_000004_MC_FB_TOP
- G_000005_MC_AGP_START
- G_000005_MC_AGP_TOP
- G_000006_AGP_BASE_ADDR
- G_000007_AGP_BASE_ADDR_2
- G_000009_ENABLE_PAGE_TABLES
- G_00000D_CP_MAX_DYN_STOP_LAT
- G_00000D_E2_MAX_DYN_STOP_LAT
- G_00000D_FORCE_CP
- G_00000D_FORCE_DISP
- G_00000D_FORCE_DISP1
- G_00000D_FORCE_DISP2
- G_00000D_FORCE_E2
- G_00000D_FORCE_HDP
- G_00000D_FORCE_IDCT
- G_00000D_FORCE_OV0
- G_00000D_FORCE_PB
- G_00000D_FORCE_PX
- G_00000D_FORCE_RB
- G_00000D_FORCE_RE
- G_00000D_FORCE_SE
- G_00000D_FORCE_SR
- G_00000D_FORCE_SU
- G_00000D_FORCE_SUBPIC
- G_00000D_FORCE_TAM
- G_00000D_FORCE_TDM
- G_00000D_FORCE_TOP
- G_00000D_FORCE_TV_SCLK
- G_00000D_FORCE_TX
- G_00000D_FORCE_US
- G_00000D_FORCE_VAP
- G_00000D_FORCE_VIP
- G_00000D_HDP_MAX_DYN_STOP_LAT
- G_00000D_IDCT_MAX_DYN_STOP_LAT
- G_00000D_PB_MAX_DYN_STOP_LAT
- G_00000D_RB_MAX_DYN_STOP_LAT
- G_00000D_RE_MAX_DYN_STOP_LAT
- G_00000D_SCLK_SRC_SEL
- G_00000D_SE_MAX_DYN_STOP_LAT
- G_00000D_TAM_MAX_DYN_STOP_LAT
- G_00000D_TCLK_SRC_SEL
- G_00000D_TDM_MAX_DYN_STOP_LAT
- G_00000D_TV_MAX_DYN_STOP_LAT
- G_00000D_VIP_MAX_DYN_STOP_LAT
- G_00000F_CP_CLOCK_STATUS
- G_00000F_CP_FORCEON
- G_00000F_CP_LOWER_POWER_IDLE
- G_00000F_CP_LOWER_POWER_IGNORE
- G_00000F_CP_MAX_DYN_STOP_LAT
- G_00000F_CP_NORMAL_POWER_BUSY
- G_00000F_CP_NORMAL_POWER_IGNORE
- G_00000F_CP_PROG_DELAY_VALUE
- G_00000F_CP_PROG_SHUTOFF
- G_00000F_SPARE
- G_000011_E2_CLOCK_STATUS
- G_000011_E2_FORCEON
- G_000011_E2_LOWER_POWER_IDLE
- G_000011_E2_LOWER_POWER_IGNORE
- G_000011_E2_MAX_DYN_STOP_LAT
- G_000011_E2_NORMAL_POWER_BUSY
- G_000011_E2_NORMAL_POWER_IGNORE
- G_000011_E2_PROG_DELAY_VALUE
- G_000011_E2_PROG_SHUTOFF
- G_000011_SPARE
- G_000012_K8_ADDR_EXT
- G_000013_IDCT_CLOCK_STATUS
- G_000013_IDCT_FORCEON
- G_000013_IDCT_LOWER_POWER_IDLE
- G_000013_IDCT_LOWER_POWER_IGNORE
- G_000013_IDCT_MAX_DYN_STOP_LAT
- G_000013_IDCT_NORMAL_POWER_BUSY
- G_000013_IDCT_NORMAL_POWER_IGNORE
- G_000013_IDCT_PROG_DELAY_VALUE
- G_000013_IDCT_PROG_SHUTOFF
- G_000013_SPARE
- G_000030_BIOS_DIS_ROM
- G_000030_BIOS_ROM_WRT_EN
- G_000030_BM_DAC_CRIPPLE
- G_000030_BUS_AGP_AD_STEPPING_EN
- G_000030_BUS_DBL_RESYNC
- G_000030_BUS_FLUSH_BUF
- G_000030_BUS_MASTER_DIS
- G_000030_BUS_MSTR_DISCONNECT_EN
- G_000030_BUS_MSTR_RD_LINE
- G_000030_BUS_MSTR_RD_MULT
- G_000030_BUS_MSTR_RESET
- G_000030_BUS_MSTR_WS
- G_000030_BUS_NON_PM4_READ_COMBINE_EN
- G_000030_BUS_PARKING_DIS
- G_000030_BUS_PCI_READ_RETRY_EN
- G_000030_BUS_PCI_WRT_RETRY_EN
- G_000030_BUS_PM4_READ_COMBINE_EN
- G_000030_BUS_RDY_READ_DLY
- G_000030_BUS_RD_DISCARD_EN
- G_000030_BUS_READ_BURST
- G_000030_BUS_RETRY_WS
- G_000030_BUS_SGL_READ_DISABLE
- G_000030_BUS_STOP_REQ_DIS
- G_000030_BUS_SUSPEND
- G_000030_BUS_WRT_COMBINE_EN
- G_000030_BUS_XFERD_DISCARD_EN
- G_000030_ENFRCWRDY
- G_000030_LAT_16X
- G_000030_SERR_EN
- G_000040_CRTC2_VBLANK
- G_000040_CRTC2_VLINE
- G_000040_CRTC2_VSYNC
- G_000040_CRTC_VBLANK
- G_000040_CRTC_VLINE
- G_000040_CRTC_VSYNC
- G_000040_DMA_VIPH0_INT_EN
- G_000040_DMA_VIPH1_INT_EN
- G_000040_DMA_VIPH2_INT_EN
- G_000040_DMA_VIPH3_INT_EN
- G_000040_DVI_I2C_INT
- G_000040_FP2_DETECT
- G_000040_FP_DETECT
- G_000040_GEYSERVILLE
- G_000040_GUIDMA
- G_000040_GUI_IDLE
- G_000040_GUI_IDLE_MASK
- G_000040_HDCP_AUTHORIZED_INT
- G_000040_I2C_INT_EN
- G_000040_SCRATCH_INT_MASK
- G_000040_SNAPSHOT
- G_000040_SNAPSHOT2
- G_000040_SW_INT_EN
- G_000040_VIDDMA
- G_000040_VIPH_INT_EN
- G_000040_VSYNC_DIFF_OVER_LIMIT
- G_000044_ATI_OVERDRIVE_INT_STAT
- G_000044_CAP0_INT_ACTIVE
- G_000044_CB_CONTEXT_SWITCH_STAT
- G_000044_CRTC2_VBLANK_STAT
- G_000044_CRTC2_VBLANK_STAT_AK
- G_000044_CRTC2_VLINE_STAT
- G_000044_CRTC2_VLINE_STAT_AK
- G_000044_CRTC2_VSYNC_STAT
- G_000044_CRTC2_VSYNC_STAT_AK
- G_000044_CRTC_VBLANK_STAT
- G_000044_CRTC_VBLANK_STAT_AK
- G_000044_CRTC_VLINE_STAT
- G_000044_CRTC_VLINE_STAT_AK
- G_000044_CRTC_VSYNC_STAT
- G_000044_CRTC_VSYNC_STAT_AK
- G_000044_DISPLAY_INT_STAT
- G_000044_DMA_VIPH0_INT
- G_000044_DMA_VIPH0_INT_AK
- G_000044_DMA_VIPH1_INT
- G_000044_DMA_VIPH1_INT_AK
- G_000044_DMA_VIPH2_INT
- G_000044_DMA_VIPH2_INT_AK
- G_000044_DMA_VIPH3_INT
- G_000044_DMA_VIPH3_INT_AK
- G_000044_DVI_I2C_INT_AK
- G_000044_DVI_I2C_INT_STAT
- G_000044_FP2_DETECT_STAT
- G_000044_FP2_DETECT_STAT_AK
- G_000044_FP_DETECT_STAT
- G_000044_FP_DETECT_STAT_AK
- G_000044_GEYSERVILLE_STAT
- G_000044_GEYSERVILLE_STAT_AK
- G_000044_GUIDMA_AK
- G_000044_GUIDMA_STAT
- G_000044_GUI_IDLE_STAT
- G_000044_GUI_IDLE_STAT_AK
- G_000044_HDCP_AUTHORIZED_INT_AK
- G_000044_HDCP_AUTHORIZED_INT_STAT
- G_000044_I2C_INT
- G_000044_I2C_INT_AK
- G_000044_IDCT_INT_STAT
- G_000044_MC_PROBE_FAULT_STAT
- G_000044_MC_PROTECTION_FAULT_STAT
- G_000044_RBBM_READ_INT_STAT
- G_000044_SCRATCH_INT_STAT
- G_000044_SNAPSHOT2_STAT
- G_000044_SNAPSHOT2_STAT_AK
- G_000044_SNAPSHOT_STAT
- G_000044_SNAPSHOT_STAT_AK
- G_000044_SW_INT
- G_000044_SW_INT_AK
- G_000044_SW_INT_SET
- G_000044_VGA_INT_STAT
- G_000044_VIDDMA_AK
- G_000044_VIDDMA_STAT
- G_000044_VIPH_INT
- G_000044_VSYNC_DIFF_OVER_LIMIT_STAT
- G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK
- G_00004C_BUS_MASTER_DIS
- G_00004C_BUS_MSI_REARM
- G_000050_CRTC_CUR_EN
- G_000050_CRTC_CUR_MODE
- G_000050_CRTC_C_SYNC_EN
- G_000050_CRTC_DBL_SCAN_EN
- G_000050_CRTC_DISP_REQ_EN_B
- G_000050_CRTC_EN
- G_000050_CRTC_EXT_DISP_EN
- G_000050_CRTC_ICON_EN
- G_000050_CRTC_INTERLACE_EN
- G_000050_CRTC_PIX_WIDTH
- G_000050_CRTC_VSTAT_MODE
- G_000054_CRTC_DISPLAY_DIS
- G_000054_CRTC_HSYNC_DIS
- G_000054_CRTC_HSYNC_TRISTATE
- G_000054_CRTC_SYNC_TRISTATE
- G_000054_CRTC_VGA_XOVERSCAN
- G_000054_CRTC_VSYNC_DIS
- G_000054_CRTC_VSYNC_TRISTATE
- G_000054_CRT_ON
- G_000054_VCRTC_IDX_MASTER
- G_000054_VGA_128KAP_PAGING
- G_000054_VGA_ATI_LINEAR
- G_000054_VGA_BLINK_RATE
- G_000054_VGA_CUR_B_TEST
- G_000054_VGA_MEM_PS_EN
- G_000054_VGA_PACK_DIS
- G_000054_VGA_TEXT_132
- G_000054_VGA_XCRT_CNT_EN
- G_00005F_K8_ADDR_EXT
- G_000070_MC_IND_ADDR
- G_000070_MC_IND_AIC_RBS
- G_000070_MC_IND_CITF_ARB0
- G_000070_MC_IND_CITF_ARB1
- G_000070_MC_IND_RD_INV
- G_000070_MC_IND_SEQ_RBS_0
- G_000070_MC_IND_SEQ_RBS_1
- G_000070_MC_IND_SEQ_RBS_2
- G_000070_MC_IND_SEQ_RBS_3
- G_000070_MC_IND_WR_EN
- G_000074_MC_IND_DATA
- G_000078_MC_IND_ADDR
- G_000078_MC_IND_WR_EN
- G_00007C_MC_DATA
- G_000090_MCA_ARB_IDLE
- G_000090_MCA_IDLE
- G_000090_MCA_INIT_EXECUTED
- G_000090_MCA_SEQ_IDLE
- G_000090_MC_ARBITER_IDLE
- G_000090_MC_SELECT_PM
- G_000090_MC_SEQUENCER_IDLE
- G_000090_MC_SYSTEM_IDLE
- G_000090_RESERVED12
- G_000090_RESERVED20
- G_000090_RESERVED4
- G_000090_RESERVED8
- G_0000F0_SOFT_RESET_AIC
- G_0000F0_SOFT_RESET_CG
- G_0000F0_SOFT_RESET_CP
- G_0000F0_SOFT_RESET_DISP
- G_0000F0_SOFT_RESET_E2
- G_0000F0_SOFT_RESET_GA
- G_0000F0_SOFT_RESET_HDP
- G_0000F0_SOFT_RESET_HI
- G_0000F0_SOFT_RESET_IDCT
- G_0000F0_SOFT_RESET_MC
- G_0000F0_SOFT_RESET_PP
- G_0000F0_SOFT_RESET_RB
- G_0000F0_SOFT_RESET_RE
- G_0000F0_SOFT_RESET_SE
- G_0000F0_SOFT_RESET_VAP
- G_0000F0_SOFT_RESET_VIP
- G_0000F8_CONFIG_MEMSIZE
- G_000100_EFFECTIVE_L2_CACHE_SIZE
- G_000100_EFFECTIVE_L2_QUEUE_SIZE
- G_000100_ENABLE_PT
- G_000100_INVALIDATE_ALL_L1_TLBS
- G_000100_INVALIDATE_L2_CACHE
- G_000100_MC_FB_START
- G_000100_MC_FB_TOP
- G_000102_ENABLE_PAGE_TABLE
- G_000102_PAGE_TABLE_DEPTH
- G_000104_MC_CPR_INIT_LAT
- G_000104_MC_DISP0R_INIT_LAT
- G_000104_MC_DISP1R_INIT_LAT
- G_000104_MC_E2R_INIT_LAT
- G_000104_MC_FIXED_INIT_LAT
- G_000104_MC_GLOBW_INIT_LAT
- G_000104_MC_VF_INIT_LAT
- G_000104_SAME_PAGE_PRIO
- G_000134_HDP_FB_START
- G_000148_MC_FB_START
- G_000148_MC_FB_TOP
- G_00014C_MC_AGP_START
- G_00014C_MC_AGP_TOP
- G_00015C_AGP_BASE_ADDR_2
- G_00015C_MC_FB_START
- G_00015C_MC_FB_TOP
- G_00016C_EFFECTIVE_L1_CACHE_SIZE
- G_00016C_EFFECTIVE_L1_QUEUE_SIZE
- G_00016C_ENABLE_FRAGMENT_PROCESSING
- G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE
- G_00016C_INVALIDATE_L1_TLB
- G_00016C_SYSTEM_ACCESS_MODE_MASK
- G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS
- G_00016C_TRANSLATION_MODE_OVERRIDE
- G_000170_AGP_BASE_ADDR
- G_0001F8_MC_IND_ADDR
- G_0001F8_MC_IND_WR_EN
- G_0001FC_MC_IND_DATA
- G_00023C_DISPLAY_BASE_ADDR
- G_000260_CUR_LOCK
- G_000260_CUR_OFFSET
- G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL
- G_000300_VGA_BLINK_MODE
- G_000300_VGA_BLINK_RATE
- G_000300_VGA_CURSOR_BLINK_INVERT
- G_000300_VGA_EXTD_ADDR_COUNT_ENABLE
- G_000300_VGA_LOCK_8DOT
- G_000300_VGA_VSTATUS_CNTL
- G_000310_VGA_MEMORY_BASE_ADDRESS
- G_000328_VGA_MEM_PAGE_SELECT_EN
- G_000328_VGA_RBBM_LOCK_DISABLE
- G_000328_VGA_SOFT_RESET
- G_000328_VGA_TEST_RESET_CONTROL
- G_000330_D1VGA_MODE_ENABLE
- G_000330_D1VGA_OVERSCAN_COLOR_EN
- G_000330_D1VGA_OVERSCAN_TIMING_SELECT
- G_000330_D1VGA_ROTATE
- G_000330_D1VGA_SYNC_POLARITY_SELECT
- G_000330_D1VGA_TIMING_SELECT
- G_000338_D2VGA_MODE_ENABLE
- G_000338_D2VGA_OVERSCAN_COLOR_EN
- G_000338_D2VGA_OVERSCAN_TIMING_SELECT
- G_000338_D2VGA_ROTATE
- G_000338_D2VGA_SYNC_POLARITY_SELECT
- G_000338_D2VGA_TIMING_SELECT
- G_00033C_CRTC2_DISPLAY_BASE_ADDR
- G_000360_CUR2_LOCK
- G_000360_CUR2_OFFSET
- G_0003C2_GENMO_MONO_ADDRESS_B
- G_0003C2_ODD_EVEN_MD_PGSEL
- G_0003C2_VGA_CKSEL
- G_0003C2_VGA_HSYNC_POL
- G_0003C2_VGA_RAM_EN
- G_0003C2_VGA_VSYNC_POL
- G_0003F8_CRT2_ON
- G_0003F8_CRTC2_CUR_EN
- G_0003F8_CRTC2_CUR_MODE
- G_0003F8_CRTC2_C_SYNC_EN
- G_0003F8_CRTC2_DBL_SCAN_EN
- G_0003F8_CRTC2_DISPLAY_DIS
- G_0003F8_CRTC2_DISP_REQ_EN_B
- G_0003F8_CRTC2_EN
- G_0003F8_CRTC2_HSYNC_DIS
- G_0003F8_CRTC2_HSYNC_TRISTATE
- G_0003F8_CRTC2_ICON_EN
- G_0003F8_CRTC2_INTERLACE_EN
- G_0003F8_CRTC2_PIX_WIDTH
- G_0003F8_CRTC2_SYNC_TRISTATE
- G_0003F8_CRTC2_VSYNC_DIS
- G_0003F8_CRTC2_VSYNC_TRISTATE
- G_000420_OV0_ADAPTIVE_DEINT
- G_000420_OV0_BANDWIDTH
- G_000420_OV0_BURST_PER_PLANE
- G_000420_OV0_CRTC_SEL
- G_000420_OV0_DOUBLE_BUFFER_REGS
- G_000420_OV0_GAMMA_SEL
- G_000420_OV0_HORZ_PICK_NEAREST
- G_000420_OV0_INT_EMU
- G_000420_OV0_LIN_TRANS_BYPASS
- G_000420_OV0_NO_READ_BEHIND_SCAN
- G_000420_OV0_OVERLAY_EN
- G_000420_OV0_SIGNED_UV
- G_000420_OV0_SOFT_RESET
- G_000420_OV0_SURFACE_FORMAT
- G_000420_OV0_VERT_PICK_NEAREST
- G_00070C_RB_RPTR_ADDR
- G_00070C_RB_RPTR_SWAP
- G_000740_CSQ_CNT_INDIRECT
- G_000740_CSQ_CNT_PRIMARY
- G_000740_CSQ_MODE
- G_000770_SCRATCH_SWAP
- G_000770_SCRATCH_UMSK
- G_000774_SCRATCH_ADDR
- G_0007C0_CMDSTRM_BUSY
- G_0007C0_CP_BUSY
- G_0007C0_CSF_INDIRECT2_BUSY
- G_0007C0_CSF_INDIRECT_BUSY
- G_0007C0_CSF_PRIMARY_BUSY
- G_0007C0_CSI_BUSY
- G_0007C0_CSQ_INDIRECT2_BUSY
- G_0007C0_CSQ_INDIRECT_BUSY
- G_0007C0_CSQ_PRIMARY_BUSY
- G_0007C0_GUIDMA_BUSY
- G_0007C0_MRU_BUSY
- G_0007C0_MWU_BUSY
- G_0007C0_RCIU_BUSY
- G_0007C0_RSIU_BUSY
- G_0007C0_VIDDMA_BUSY
- G_000E40_CBA2D_BUSY
- G_000E40_CFRQ_IN_RTBUF
- G_000E40_CFRQ_ON_RBB
- G_000E40_CF_PIPE_BUSY
- G_000E40_CMDFIFO_AVAIL
- G_000E40_CPRQ_IN_RTBUF
- G_000E40_CPRQ_ON_RBB
- G_000E40_CP_CMDSTRM_BUSY
- G_000E40_E2_BUSY
- G_000E40_ENG_EV_BUSY
- G_000E40_GA_BUSY
- G_000E40_GUI_ACTIVE
- G_000E40_HIRQ_IN_RTBUF
- G_000E40_HIRQ_ON_RBB
- G_000E40_PB_BUSY
- G_000E40_RB2D_BUSY
- G_000E40_RB3D_BUSY
- G_000E40_RBBM_HIBUSY
- G_000E40_RE_BUSY
- G_000E40_SE_BUSY
- G_000E40_SKID_CFBUSY
- G_000E40_TAM_BUSY
- G_000E40_TDM_BUSY
- G_000E40_TIM_BUSY
- G_000E40_VAP_BUSY
- G_000E40_VAP_VF_BUSY
- G_000E50_BIF_BUSY
- G_000E50_GRBM_RQ_PENDING
- G_000E50_HI_RQ_PENDING
- G_000E50_IH_BUSY
- G_000E50_IO_EXTERN_SIGNAL
- G_000E50_MCB_BUSY
- G_000E50_MCDW_BUSY
- G_000E50_MCDX_BUSY
- G_000E50_MCDY_BUSY
- G_000E50_MCDZ_BUSY
- G_000E50_RCU_RQ_PENDING
- G_000E50_RLC_BUSY
- G_000E50_RLC_RQ_PENDING
- G_000E50_SEM_BUSY
- G_000E50_VMC_BUSY
- G_006080_D1CRTC_CURRENT_MASTER_EN_STATE
- G_006080_D1CRTC_DISABLE_POINT_CNTL
- G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE
- G_006080_D1CRTC_MASTER_EN
- G_006080_D1CRTC_SYNC_RESET_SEL
- G_0060A4_D1CRTC_FRAME_COUNT
- G_0060E8_D1CRTC_UPDATE_LOCK
- G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS
- G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS
- G_006520_DC_LB_DISP1_END_ADR
- G_006520_DC_LB_MEMORY_SPLIT
- G_006520_DC_LB_MEMORY_SPLIT_MODE
- G_006534_D1MODE_VBLANK_ACK
- G_006534_D1MODE_VBLANK_INTERRUPT
- G_006534_D1MODE_VBLANK_OCCURRED
- G_006534_D1MODE_VBLANK_STAT
- G_006540_D1MODE_VBLANK_CP_SEL
- G_006540_D1MODE_VBLANK_INT_MASK
- G_006540_D1MODE_VLINE_INT_MASK
- G_006540_D2MODE_VBLANK_CP_SEL
- G_006540_D2MODE_VBLANK_INT_MASK
- G_006540_D2MODE_VLINE_INT_MASK
- G_006548_D1MODE_PRIORITY_A_ALWAYS_ON
- G_006548_D1MODE_PRIORITY_A_FORCE_MASK
- G_006548_D1MODE_PRIORITY_A_OFF
- G_006548_D1MODE_PRIORITY_MARK_A
- G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON
- G_00654C_D1MODE_PRIORITY_B_FORCE_MASK
- G_00654C_D1MODE_PRIORITY_B_OFF
- G_00654C_D1MODE_PRIORITY_MARK_B
- G_006880_D2CRTC_CURRENT_MASTER_EN_STATE
- G_006880_D2CRTC_DISABLE_POINT_CNTL
- G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE
- G_006880_D2CRTC_MASTER_EN
- G_006880_D2CRTC_SYNC_RESET_SEL
- G_0068A4_D2CRTC_FRAME_COUNT
- G_0068E8_D2CRTC_UPDATE_LOCK
- G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS
- G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS
- G_006D34_D2MODE_VBLANK_ACK
- G_006D34_D2MODE_VBLANK_INTERRUPT
- G_006D34_D2MODE_VBLANK_OCCURRED
- G_006D34_D2MODE_VBLANK_STAT
- G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON
- G_006D48_D2MODE_PRIORITY_A_FORCE_MASK
- G_006D48_D2MODE_PRIORITY_A_OFF
- G_006D48_D2MODE_PRIORITY_MARK_A
- G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON
- G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK
- G_006D4C_D2MODE_PRIORITY_B_OFF
- G_006D4C_D2MODE_PRIORITY_MARK_B
- G_006D58_LB_D1_MAX_REQ_OUTSTANDING
- G_006D58_LB_D2_MAX_REQ_OUTSTANDING
- G_007404_HDMI0_AZ_FORMAT_WTRIG
- G_007404_HDMI0_AZ_FORMAT_WTRIG_INT
- G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK
- G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK
- G_007828_DACA_AUTODETECT_CHECK_MASK
- G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER
- G_007828_DACA_AUTODETECT_MODE
- G_007838_DACA_AUTODETECT_INT_ENABLE
- G_007A28_DACB_AUTODETECT_CHECK_MASK
- G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER
- G_007A28_DACB_AUTODETECT_MODE
- G_007A38_DACB_AUTODETECT_INT_ENABLE
- G_007D00_DC_HOT_PLUG_DETECT1_EN
- G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
- G_007D04_DC_HOT_PLUG_DETECT1_SENSE
- G_007D08_DC_HOT_PLUG_DETECT1_INT_EN
- G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY
- G_007D10_DC_HOT_PLUG_DETECT2_EN
- G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
- G_007D14_DC_HOT_PLUG_DETECT2_SENSE
- G_007D18_DC_HOT_PLUG_DETECT2_INT_EN
- G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY
- G_007EDC_DACA_AUTODETECT_INTERRUPT
- G_007EDC_DACB_AUTODETECT_INTERRUPT
- G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT
- G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT
- G_007EDC_LB_D1_VBLANK_INTERRUPT
- G_007EDC_LB_D2_VBLANK_INTERRUPT
- G_008010_CB03_BUSY
- G_008010_CB03_CLEAN
- G_008010_CF_RQ_PENDING
- G_008010_CMDFIFO_AVAIL
- G_008010_CP_BUSY
- G_008010_CP_COHERENCY_BUSY
- G_008010_CP_RQ_PENDING
- G_008010_CR_BUSY
- G_008010_DB03_BUSY
- G_008010_DB03_CLEAN
- G_008010_GRBM_EE_BUSY
- G_008010_GUI_ACTIVE
- G_008010_PA_BUSY
- G_008010_PF_RQ_PENDING
- G_008010_SC_BUSY
- G_008010_SH_BUSY
- G_008010_SMX_BUSY
- G_008010_SPI03_BUSY
- G_008010_SX_BUSY
- G_008010_TA03_BUSY
- G_008010_TA_BUSY
- G_008010_TC_BUSY
- G_008010_VC_BUSY
- G_008010_VGT_BUSY
- G_008010_VGT_BUSY_NO_DMA
- G_008014_CB0_BUSY
- G_008014_CB1_BUSY
- G_008014_CB2_BUSY
- G_008014_CB3_BUSY
- G_008014_CR_CLEAN
- G_008014_DB0_BUSY
- G_008014_DB1_BUSY
- G_008014_DB2_BUSY
- G_008014_DB3_BUSY
- G_008014_SMX_CLEAN
- G_008014_SPI0_BUSY
- G_008014_SPI1_BUSY
- G_008014_SPI2_BUSY
- G_008014_SPI3_BUSY
- G_008014_TA0_BUSY
- G_008014_TA1_BUSY
- G_008014_TA2_BUSY
- G_008014_TA3_BUSY
- G_008C44_MEM_SIZE
- G_008C4C_MEM_SIZE
- G_008C54_MEM_SIZE
- G_008C5C_MEM_SIZE
- G_008C64_MEM_SIZE
- G_008C6C_MEM_SIZE
- G_008C74_MEM_SIZE
- G_008C7C_MEM_SIZE
- G_028000_PITCH_TILE_MAX
- G_028000_SLICE_TILE_MAX
- G_028004_SLICE_MAX
- G_028004_SLICE_START
- G_028008_SLICE_MAX
- G_028008_SLICE_START
- G_028010_ARRAY_MODE
- G_028010_FORMAT
- G_028010_READ_SIZE
- G_028010_TILE_COMPACT
- G_028010_TILE_SURFACE_ENABLE
- G_028010_ZRANGE_PRECISION
- G_028040_ARRAY_MODE
- G_028040_BANK_HEIGHT
- G_028040_BANK_WIDTH
- G_028040_FORMAT
- G_028040_MACRO_TILE_ASPECT
- G_028040_NUM_BANKS
- G_028040_READ_SIZE
- G_028040_TILE_SPLIT
- G_028040_TILE_SURFACE_ENABLE
- G_028040_ZRANGE_PRECISION
- G_028044_FORMAT
- G_028044_TILE_SPLIT
- G_028058_HEIGHT_TILE_MAX
- G_028058_PITCH_TILE_MAX
- G_02805C_SLICE_TILE_MAX
- G_028060_PITCH_TILE_MAX
- G_028060_SLICE_TILE_MAX
- G_028080_SLICE_MAX
- G_028080_SLICE_START
- G_0280A0_ARRAY_MODE
- G_0280A0_BLEND_BYPASS
- G_0280A0_BLEND_CLAMP
- G_0280A0_BLEND_FLOAT32
- G_0280A0_CLEAR_COLOR
- G_0280A0_COMP_SWAP
- G_0280A0_ENDIAN
- G_0280A0_FORMAT
- G_0280A0_NUMBER_TYPE
- G_0280A0_READ_SIZE
- G_0280A0_ROUND_MODE
- G_0280A0_SIMPLE_FLOAT
- G_0280A0_SOURCE_FORMAT
- G_0280A0_TILE_COMPACT
- G_0280A0_TILE_MODE
- G_0280C0_BASE_256B
- G_0280E0_BASE_256B
- G_028100_CMASK_BLOCK_MAX
- G_028100_FMASK_TILE_MAX
- G_028238_TARGET0_ENABLE
- G_028238_TARGET1_ENABLE
- G_028238_TARGET2_ENABLE
- G_028238_TARGET3_ENABLE
- G_028238_TARGET4_ENABLE
- G_028238_TARGET5_ENABLE
- G_028238_TARGET6_ENABLE
- G_028238_TARGET7_ENABLE
- G_02823C_OUTPUT0_ENABLE
- G_02823C_OUTPUT1_ENABLE
- G_02823C_OUTPUT2_ENABLE
- G_02823C_OUTPUT3_ENABLE
- G_02823C_OUTPUT4_ENABLE
- G_02823C_OUTPUT5_ENABLE
- G_02823C_OUTPUT6_ENABLE
- G_02823C_OUTPUT7_ENABLE
- G_028800_BACKFACE_ENABLE
- G_028800_STENCILFAIL
- G_028800_STENCILFAIL_BF
- G_028800_STENCILFUNC
- G_028800_STENCILFUNC_BF
- G_028800_STENCILZFAIL
- G_028800_STENCILZFAIL_BF
- G_028800_STENCILZPASS
- G_028800_STENCILZPASS_BF
- G_028800_STENCIL_ENABLE
- G_028800_ZFUNC
- G_028800_Z_ENABLE
- G_028800_Z_WRITE_ENABLE
- G_028808_SPECIAL_OP
- G_0288A8_ITEMSIZE
- G_0288AC_ITEMSIZE
- G_0288B0_ITEMSIZE
- G_0288B4_ITEMSIZE
- G_0288B8_ITEMSIZE
- G_0288BC_ITEMSIZE
- G_0288C0_ITEMSIZE
- G_0288C4_ITEMSIZE
- G_0288C8_ITEMSIZE
- G_028AB0_STREAMOUT
- G_028ABC_HTILE_HEIGHT
- G_028ABC_HTILE_WIDTH
- G_028ABC_LINEAR
- G_028B20_BUFFER_0_EN
- G_028B20_BUFFER_1_EN
- G_028B20_BUFFER_2_EN
- G_028B20_BUFFER_3_EN
- G_028B20_SIZE
- G_028C04_AA_MASK_CENTROID_DTMN
- G_028C04_MAX_SAMPLE_DIST
- G_028C04_MSAA_NUM_SAMPLES
- G_028C6C_SLICE_MAX
- G_028C6C_SLICE_START
- G_028C70_ARRAY_MODE
- G_028C70_BLEND_BYPASS
- G_028C70_BLEND_CLAMP
- G_028C70_COMPRESSION
- G_028C70_COMP_SWAP
- G_028C70_ENDIAN
- G_028C70_FAST_CLEAR
- G_028C70_FORMAT
- G_028C70_NUMBER_TYPE
- G_028C70_RAT
- G_028C70_RESOURCE_TYPE
- G_028C70_ROUND_MODE
- G_028C70_SIMPLE_FLOAT
- G_028C70_SOURCE_FORMAT
- G_028C70_TILE_COMPACT
- G_028C74_BANK_HEIGHT
- G_028C74_BANK_WIDTH
- G_028C74_MACRO_TILE_ASPECT
- G_028C74_NON_DISP_TILING_ORDER
- G_028C74_NUM_BANKS
- G_028C74_TILE_SPLIT
- G_028D24_HTILE_HEIGHT
- G_028D24_HTILE_WIDTH
- G_028D24_LINEAR
- G_030000_DIM
- G_030000_NON_DISP_TILING_ORDER
- G_030000_PITCH
- G_030000_TEX_WIDTH
- G_030004_ARRAY_MODE
- G_030004_TEX_DEPTH
- G_030004_TEX_HEIGHT
- G_030008_BASE_ADDRESS
- G_03000C_MIP_ADDRESS
- G_030010_BASE_LEVEL
- G_030010_DST_SEL_W
- G_030010_DST_SEL_X
- G_030010_DST_SEL_Y
- G_030010_DST_SEL_Z
- G_030010_ENDIAN_SWAP
- G_030010_FORCE_DEGAMMA
- G_030010_FORMAT_COMP_W
- G_030010_FORMAT_COMP_X
- G_030010_FORMAT_COMP_Y
- G_030010_FORMAT_COMP_Z
- G_030010_NUM_FORMAT_ALL
- G_030010_SRF_MODE_ALL
- G_030014_BASE_ARRAY
- G_030014_LAST_ARRAY
- G_030014_LAST_LEVEL
- G_030018_INTERLACED
- G_030018_MAX_ANISO
- G_030018_PERF_MODULATION
- G_030018_TILE_SPLIT
- G_03001C_BANK_HEIGHT
- G_03001C_BANK_WIDTH
- G_03001C_DATA_FORMAT
- G_03001C_MACRO_TILE_ASPECT
- G_03001C_NUM_BANKS
- G_03001C_TYPE
- G_038000_DIM
- G_038000_PITCH
- G_038000_TEX_WIDTH
- G_038000_TILE_MODE
- G_038000_TILE_TYPE
- G_038004_DATA_FORMAT
- G_038004_TEX_DEPTH
- G_038004_TEX_HEIGHT
- G_038010_BASE_LEVEL
- G_038010_DST_SEL_W
- G_038010_DST_SEL_X
- G_038010_DST_SEL_Y
- G_038010_DST_SEL_Z
- G_038010_ENDIAN_SWAP
- G_038010_FORCE_DEGAMMA
- G_038010_FORMAT_COMP_W
- G_038010_FORMAT_COMP_X
- G_038010_FORMAT_COMP_Y
- G_038010_FORMAT_COMP_Z
- G_038010_NUM_FORMAT_ALL
- G_038010_REQUEST_SIZE
- G_038010_SRF_MODE_ALL
- G_038014_BASE_ARRAY
- G_038014_LAST_ARRAY
- G_038014_LAST_LEVEL
- G_2MSL
- G_5TUPLE_LOOKUP
- G_ACSR_SPEED
- G_ACTIVE_TO_PRECHARGE_DELAY
- G_ADC12
- G_ADFSDM
- G_ALL_CHANS
- G_ALMOSTEMPTY
- G_ALMOSTFULL
- G_AOPEN_IFF_VLAN
- G_AOPEN_MAC_MATCH
- G_AOPEN_PKT_TYPE
- G_AOPEN_VLAN_PRI
- G_ATRAP_CFG_AGENTID
- G_ATRAP_CFG_CATTR
- G_ATRAP_CFG_CNT
- G_BAD_DIRECTION
- G_BAD_HOSTNAME
- G_BAD_MSG_CTX
- G_BAD_SERVICE_NAME
- G_BAD_STRING_UID
- G_BAD_TOK_HEADER
- G_BAD_USAGE
- G_BCM1480_ATRAP_CFG_AGENTID
- G_BCM1480_ATRAP_CFG_CATTR
- G_BCM1480_ATRAP_CFG_CNT
- G_BCM1480_INT_HT_INTDEST
- G_BCM1480_INT_HT_INTMSG
- G_BCM1480_INT_HT_VECTOR
- G_BCM1480_L2C_DATA_ECC
- G_BCM1480_L2C_MGMT_ECC_DIAG
- G_BCM1480_L2C_MGMT_INDEX
- G_BCM1480_L2C_MGMT_WAY
- G_BCM1480_L2C_MISC0_CACHE_DISABLE
- G_BCM1480_L2C_MISC0_CACHE_QUAD
- G_BCM1480_L2C_MISC0_WAY_ENABLE
- G_BCM1480_L2C_MISC0_WAY_LOCAL
- G_BCM1480_L2C_MISC0_WAY_REMOTE
- G_BCM1480_L2C_MISC1_WAY_AGENT_0
- G_BCM1480_L2C_MISC1_WAY_AGENT_1
- G_BCM1480_L2C_MISC1_WAY_AGENT_2
- G_BCM1480_L2C_MISC1_WAY_AGENT_3
- G_BCM1480_L2C_MISC1_WAY_AGENT_4
- G_BCM1480_L2C_MISC2_WAY_AGENT_8
- G_BCM1480_L2C_MISC2_WAY_AGENT_9
- G_BCM1480_L2C_MISC2_WAY_AGENT_A
- G_BCM1480_L2C_TAG_ECC
- G_BCM1480_L2C_TAG_INDEX
- G_BCM1480_L2C_TAG_TAG
- G_BCM1480_L2C_TAG_WAY
- G_BCM1480_MC_ADDR_COARSE_ADJ
- G_BCM1480_MC_ADDR_FINE_ADJ
- G_BCM1480_MC_ADDR_FREQ_RANGE
- G_BCM1480_MC_BLK_CLR_MARK
- G_BCM1480_MC_BLK_SET_MARK
- G_BCM1480_MC_CHANNEL_SELECT
- G_BCM1480_MC_CLK_RATIO
- G_BCM1480_MC_COL00
- G_BCM1480_MC_COL01
- G_BCM1480_MC_COL02
- G_BCM1480_MC_COL03
- G_BCM1480_MC_COL04
- G_BCM1480_MC_COL05
- G_BCM1480_MC_COL06
- G_BCM1480_MC_COL07
- G_BCM1480_MC_COL08
- G_BCM1480_MC_COL09
- G_BCM1480_MC_COL11
- G_BCM1480_MC_COL12
- G_BCM1480_MC_COL13
- G_BCM1480_MC_COL14
- G_BCM1480_MC_COMMAND
- G_BCM1480_MC_CS
- G_BCM1480_MC_CS01_BANK0
- G_BCM1480_MC_CS01_BANK1
- G_BCM1480_MC_CS01_BANK2
- G_BCM1480_MC_CS0_END
- G_BCM1480_MC_CS0_START
- G_BCM1480_MC_CS1_END
- G_BCM1480_MC_CS1_START
- G_BCM1480_MC_CS23_BANK0
- G_BCM1480_MC_CS23_BANK1
- G_BCM1480_MC_CS23_BANK2
- G_BCM1480_MC_CS2_END
- G_BCM1480_MC_CS2_START
- G_BCM1480_MC_CS3_END
- G_BCM1480_MC_CS3_START
- G_BCM1480_MC_CS_MODE
- G_BCM1480_MC_DLL_BGCTRL
- G_BCM1480_MC_DLL_DEFAULT
- G_BCM1480_MC_DLL_FREQ_RANGE
- G_BCM1480_MC_DLL_PDSEL
- G_BCM1480_MC_DLL_REGCTRL
- G_BCM1480_MC_DLL_STEP_SIZE
- G_BCM1480_MC_DQI_COARSE_ADJ
- G_BCM1480_MC_DQI_FINE_ADJ
- G_BCM1480_MC_DQI_FREQ_RANGE
- G_BCM1480_MC_DQO_COARSE_ADJ
- G_BCM1480_MC_DQO_FINE_ADJ
- G_BCM1480_MC_DQO_FREQ_RANGE
- G_BCM1480_MC_DRAM_TYPE
- G_BCM1480_MC_ECC_CORRECT
- G_BCM1480_MC_ECC_CORR_ADDR
- G_BCM1480_MC_ECC_ERR_ADDR
- G_BCM1480_MC_EMODE
- G_BCM1480_MC_INTLV0
- G_BCM1480_MC_INTLV1
- G_BCM1480_MC_INTLV2
- G_BCM1480_MC_INTLV_MODE
- G_BCM1480_MC_MAX_AGE
- G_BCM1480_MC_MODE
- G_BCM1480_MC_PG_POLICY
- G_BCM1480_MC_PVT_BYP_C1_PULLDOWN
- G_BCM1480_MC_PVT_BYP_C1_PULLUP
- G_BCM1480_MC_PVT_BYP_C2_PULLDOWN
- G_BCM1480_MC_PVT_BYP_C2_PULLUP
- G_BCM1480_MC_REF_RATE
- G_BCM1480_MC_ROW00
- G_BCM1480_MC_ROW01
- G_BCM1480_MC_ROW02
- G_BCM1480_MC_ROW03
- G_BCM1480_MC_ROW04
- G_BCM1480_MC_ROW05
- G_BCM1480_MC_ROW06
- G_BCM1480_MC_ROW07
- G_BCM1480_MC_ROW08
- G_BCM1480_MC_ROW09
- G_BCM1480_MC_ROW10
- G_BCM1480_MC_ROW11
- G_BCM1480_MC_ROW12
- G_BCM1480_MC_ROW13
- G_BCM1480_MC_ROW14
- G_BCM1480_MC_RTT_BYP_PULLDOWN
- G_BCM1480_MC_RTT_BYP_PULLUP
- G_BCM1480_MC_SLEW
- G_BCM1480_MC_tAL
- G_BCM1480_MC_tCL
- G_BCM1480_MC_tCwD
- G_BCM1480_MC_tFAW
- G_BCM1480_MC_tFIFO
- G_BCM1480_MC_tR2W
- G_BCM1480_MC_tRAP
- G_BCM1480_MC_tRCD
- G_BCM1480_MC_tRCr
- G_BCM1480_MC_tRCw
- G_BCM1480_MC_tRFC
- G_BCM1480_MC_tRP
- G_BCM1480_MC_tRRD
- G_BCM1480_MC_tRTP
- G_BCM1480_MC_tW2R
- G_BCM1480_MC_tW2W
- G_BCM1480_MC_tWR
- G_BCM1480_SCD_TRACE_CFG_MODE
- G_BCM1480_SCD_TRSEQ_SWFUNC
- G_BCM1480_SCD_WDOG_RESET_TYPE
- G_BCM1480_SPC_CNT_COUNT
- G_BCM1480_SYS_BOOT_MODE
- G_BCM1480_SYS_CONFIG
- G_BCM1480_SYS_NODEID
- G_BCM1480_SYS_PLL_DIV
- G_BCM1480_SYS_SW_DIV
- G_BKPSRAM
- G_BSEC
- G_BUFFER_ALLOC
- G_BUNDLE_ADDR
- G_CALENDARLENGTH
- G_CALIMP
- G_CEC
- G_CF_PARITY_ERR
- G_CHAN
- G_CHANNEL_ADDR
- G_CMDMODE
- G_CMDQ0_POINTER
- G_CMDQ0_SIZE
- G_CMDQ1_POINTER
- G_CMDQ1_SIZE
- G_CMDQ_PRIORITY
- G_CMD_LEN
- G_CM_MEMMGR_BASE
- G_CM_MEMMGR_MAX_PSTRUCT
- G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE
- G_CM_MEMMGR_RX_FREE_LIST_BASE
- G_CM_MEMMGR_TX_FREE_LIST_BASE
- G_CM_TIMER_BASE
- G_CONG_CONTROL_FLAVOR
- G_CONN_POLICY
- G_CONTEXT
- G_CORRECTABLE_ERROR_COUNT
- G_CPL_OPCODE
- G_CPL_STATUS
- G_CPL_TX_TNL_LSO_ETHHDRLEN
- G_CPU_IDX
- G_CPU_INDEX
- G_CQE_GENBIT
- G_CQE_OOO
- G_CQE_OPCODE
- G_CQE_QPID
- G_CQE_STATUS
- G_CQE_SWCQE
- G_CQE_TYPE
- G_CQ_BASE_HI
- G_CQ_CREDIT
- G_CQ_CREDITS
- G_CQ_CREDIT_THRES
- G_CQ_INDEX
- G_CQ_RSPQ
- G_CQ_SIZE
- G_CRC1
- G_CRC2
- G_CRC_DEF_CRC_INIT
- G_CRC_DEF_CRC_POLY
- G_CRYP1
- G_CRYP2
- G_CSPI_TRAIN_ALPHA
- G_CSPI_TRAIN_DATA_MAXT
- G_CTCP_DEF_CRC_TXOR
- G_CTCP_DEF_CRC_WIDTH
- G_CTCP_DEF_TCPCS_INIT
- G_CUT_VERSION
- G_DAC12
- G_DACK_BYTE_THRESHOLD
- G_DACK_MSS_SELECTOR
- G_DATA
- G_DATA_PATTERN
- G_DAY
- G_DBGI_RSP_ERR_REASON
- G_DCMI
- G_DDP_OFFSET
- G_DDP_STATUS
- G_DDP_ULP_MODE
- G_DDP_VALID
- G_DDRPERFM
- G_DEFAULT_PEER_MSS
- G_DELAYED_ACK_TIME
- G_DELAYED_ACK_TIMER_RESOLUTION
- G_DELAY_PS
- G_DEN
- G_DENSITY
- G_DFSDM
- G_DIP2_ERR_CNT
- G_DIP2_PARITY_ERR_THRES
- G_DIP4ERRORCNT
- G_DIP4ERRORCNTSHADOW
- G_DIP4_THRES
- G_DIV_ID
- G_DIV_ID_MASK
- G_DMA1
- G_DMA2
- G_DMAMUX
- G_DMA_ASICXFR_SIZE
- G_DMA_DESC_TYPE
- G_DMA_DSCRA_A_SIZE
- G_DMA_DSCRA_DSCR_CNT
- G_DMA_DSCRA_OFFSET
- G_DMA_DSCRA_STATUS
- G_DMA_DSCRB_A_SIZE
- G_DMA_DSCRB_B_SIZE
- G_DMA_DSCRB_OPTIONS
- G_DMA_DSCRB_PKT_SIZE
- G_DMA_DSCRB_PKT_SIZE_MSB
- G_DMA_DSCRB_STATUS
- G_DMA_EOP_COUNT_RX
- G_DMA_ETHRX_PKTTYPE
- G_DMA_ETHRX_RXCH
- G_DMA_HDR_SIZE
- G_DMA_HIGH_WATERMARK
- G_DMA_INT_PKTCNT
- G_DMA_INT_TIMEOUT
- G_DMA_LOW_WATERMARK
- G_DMA_OODLOST_RX
- G_DMA_RINGSZ
- G_DM_CUR_DSCR_DSCR_COUNT
- G_DM_DSCRA_DIR_DEST
- G_DM_DSCRA_DIR_SRC
- G_DM_DSCRB_SRC_LENGTH
- G_DM_DSCR_BASE_PRIORITY
- G_DM_DSCR_BASE_RINGSZ
- G_DM_PARTIAL_CRC_PARTIAL
- G_DM_PARTIAL_TCPCS_PARTIAL
- G_DOWNSHIFT_CNT
- G_DROP_TICKS_CNT
- G_DSI
- G_DUART_INT_TIME
- G_DUART_ISR_RX_A
- G_DUART_SIG_FULL
- G_DUP_THRESH
- G_ECN
- G_EC_BASE_HI
- G_EC_BASE_LO
- G_EC_CREDITS
- G_EC_INDEX
- G_EC_RESPQ
- G_EC_SIZE
- G_EC_TYPE
- G_EC_UP_TOKEN
- G_ELEMENT0
- G_ELEMENT1
- G_ELEMENT2
- G_ELEMENT3
- G_ETHCK
- G_ETHMAC
- G_ETHRX
- G_ETHSTP
- G_ETHTX
- G_FAST_FINWAIT2_TIME
- G_FDCAN
- G_FINWAIT2_TIME
- G_FL0_POINTER
- G_FL0_SIZE
- G_FL1_POINTER
- G_FL1_SIZE
- G_FLIT_CNT
- G_FLPARITYERROR
- G_FL_BASE_HI
- G_FL_CONG_THRES
- G_FL_ENTRY_SIZE_HI
- G_FL_ENTRY_SIZE_LO
- G_FL_INDEX_HI
- G_FL_INDEX_LO
- G_FL_SIZE
- G_FL_THRESHOLD
- G_FMC
- G_FR_PAGE_COUNT
- G_FR_PAGE_SIZE
- G_FR_PERMS
- G_FR_TYPE
- G_FW_RIWR_FLAGS
- G_FW_RIWR_OP
- G_FW_VERSION_MAJOR
- G_FW_VERSION_MICRO
- G_FW_VERSION_MINOR
- G_FW_VERSION_TYPE
- G_GENERIC_TIMER_RESOLUTION
- G_GLOBAL_TIMER_SEPARATOR
- G_GPIOA
- G_GPIOB
- G_GPIOC
- G_GPIOD
- G_GPIOE
- G_GPIOF
- G_GPIOG
- G_GPIOH
- G_GPIOI
- G_GPIOJ
- G_GPIOK
- G_GPIOZ
- G_GPIO_INTR_ATYPE0
- G_GPIO_INTR_ATYPE10
- G_GPIO_INTR_ATYPE12
- G_GPIO_INTR_ATYPE14
- G_GPIO_INTR_ATYPE2
- G_GPIO_INTR_ATYPE4
- G_GPIO_INTR_ATYPE6
- G_GPIO_INTR_ATYPE8
- G_GPIO_INTR_ATYPEX
- G_GPIO_INTR_TYPE0
- G_GPIO_INTR_TYPE10
- G_GPIO_INTR_TYPE12
- G_GPIO_INTR_TYPE14
- G_GPIO_INTR_TYPE2
- G_GPIO_INTR_TYPE4
- G_GPIO_INTR_TYPE6
- G_GPIO_INTR_TYPE8
- G_GPIO_INTR_TYPEX
- G_GPU
- G_HASH1
- G_HASH2
- G_HASHTYPE
- G_HDP
- G_HKDNORMOFF
- G_HKDUTLBOFF
- G_HKDXUTLBOFF
- G_HPZ0
- G_HSEM
- G_I2C1
- G_I2C2
- G_I2C3
- G_I2C4
- G_I2C5
- G_I2C6
- G_IBQDBGADDR
- G_IBQDBGQID
- G_IDINDEX
- G_INITIAL_SLOW_START_THRESHOLD
- G_INITIAL_SRTT
- G_INIT_CONG_WIN
- G_INTERFACE
- G_INTERRUPT_TIMER_COUNT
- G_INT_DISABLE
- G_INT_LDT_INTDEST
- G_INT_LDT_INTMSG
- G_INT_LDT_VECTOR
- G_IO_ALE_TO_CS
- G_IO_ALE_TO_WRITE
- G_IO_ALE_WIDTH
- G_IO_BURST_WIDTH
- G_IO_CS_TO_OE
- G_IO_CS_WIDTH
- G_IO_DRV_A
- G_IO_DRV_B
- G_IO_DRV_C
- G_IO_DRV_D
- G_IO_DRV_E
- G_IO_DRV_F
- G_IO_DRV_G
- G_IO_DRV_H
- G_IO_DRV_J
- G_IO_DRV_K
- G_IO_DRV_L
- G_IO_DRV_M
- G_IO_DRV_N
- G_IO_DRV_P
- G_IO_DRV_Q
- G_IO_DRV_R
- G_IO_IDLE_CYCLE
- G_IO_MULT_SIZE
- G_IO_OE_TO_CS
- G_IO_RDY_SMPLE
- G_IO_SLEW0
- G_IO_SLEW1
- G_IO_SLEW2
- G_IO_SLEW3
- G_IO_START_ADDR
- G_IO_TIMEOUT
- G_IO_WIDTH_SEL
- G_IO_WRITE_WIDTH
- G_IPCC
- G_IP_TTL
- G_ISCSI_PDU_LEN
- G_ITPARITYERROR
- G_IWDG1
- G_IWDG2
- G_KEEPALIVE_MAX
- G_KEEP_ALIVE_IDLE_TIME
- G_KEEP_ALIVE_INTERVAL_TIME
- G_L2C_MGMT_ECC_DIAG
- G_L2C_MGMT_INDEX
- G_L2C_MGMT_QUADRANT
- G_L2C_MGMT_TAG
- G_L2C_MGMT_WAY
- G_L2C_MISC_NO_WAY
- G_L2C_TAG_ECC
- G_L2C_TAG_INDEX
- G_L2C_TAG_TAG
- G_L2C_TAG_WAY
- G_L2T_IDX
- G_L2T_IDX16
- G_L2T_R_IFF
- G_L2T_R_PRIO
- G_L2T_R_VLAN
- G_L2T_STATUS
- G_L2T_W_IDX
- G_L2T_W_IFF
- G_L2T_W_PRIO
- G_L2T_W_VLAN
- G_L3_VALUE
- G_LAST
- G_LDT_ADDSTATUS_TGTDONE
- G_LDT_CLASSREV_CLASS
- G_LDT_CLASSREV_REV
- G_LDT_CMD_CAPTYPE
- G_LDT_DEVHDR_BIST
- G_LDT_DEVHDR_CLINESZ
- G_LDT_DEVHDR_HDRTYPE
- G_LDT_DEVHDR_LATTMR
- G_LDT_DEVICEID_DEVICEID
- G_LDT_DEVICEID_VENDOR
- G_LDT_LINKCTRL_CRCERR
- G_LDT_LINKCTRL_MAXIN
- G_LDT_LINKCTRL_MAXOUT
- G_LDT_LINKCTRL_WIDTHIN
- G_LDT_LINKCTRL_WIDTHOUT
- G_LDT_LINKFREQ_FREQ
- G_LDT_SRICMD_RXMARGIN
- G_LDT_SRICMD_TXINITIALOFFSET
- G_LDT_SRICTRL_BUFRELSPACE
- G_LDT_SRICTRL_NEEDNPREQ
- G_LDT_SRICTRL_NEEDPREQ
- G_LDT_SRICTRL_NEEDRESP
- G_LDT_SRICTRL_WANTNPREQ
- G_LDT_SRICTRL_WANTPREQ
- G_LDT_SRICTRL_WANTRESP
- G_LDT_STATUS_DEVSELTIMING
- G_LDT_TXBUFCNT_NPCMD
- G_LDT_TXBUFCNT_NPDATA
- G_LDT_TXBUFCNT_PCMD
- G_LDT_TXBUFCNT_PDATA
- G_LDT_TXBUFCNT_RCMD
- G_LDT_TXBUFCNT_RDATA
- G_LEARN_RESPONSE_LATENCY
- G_LOCAL_IP_RAM_ADDR
- G_LPTIM1
- G_LPTIM2
- G_LPTIM3
- G_LPTIM4
- G_LPTIM5
- G_LSO_ETH_TYPE
- G_LSO_IPHDR_WORDS
- G_LSO_MSS
- G_LSO_TCPHDR_WORDS
- G_LTDC
- G_MAC_BACKOFF_SEL
- G_MAC_BYPASS_CFG
- G_MAC_BYPASS_IFG
- G_MAC_COUNTER_ADDR
- G_MAC_ENC_FC_THRSH
- G_MAC_FC_CMD
- G_MAC_IFG_RX
- G_MAC_IFG_THRSH
- G_MAC_IFG_TX
- G_MAC_IFS1
- G_MAC_IFS2
- G_MAC_IPHDR_OFFSET
- G_MAC_LFSR_SEED
- G_MAC_MATCH
- G_MAC_MAX_FRAMESZ
- G_MAC_MIN_FRAMESZ
- G_MAC_PRE_LEN
- G_MAC_RX_CH_MSN_SEL
- G_MAC_RX_CH_SEL
- G_MAC_RX_CRC_OFFSET
- G_MAC_RX_EOP_COUNTER
- G_MAC_RX_PKT_OFFSET
- G_MAC_RX_PL_THRSH
- G_MAC_RX_RDPTR
- G_MAC_RX_RD_THRSH
- G_MAC_RX_RL_THRSH
- G_MAC_RX_WRPTR
- G_MAC_SLOT_SIZE
- G_MAC_SPEED
- G_MAC_SPEED_SEL
- G_MAC_TXD_WEIGHT0
- G_MAC_TXD_WEIGHT1
- G_MAC_TX_CRC_OFFSET
- G_MAC_TX_EOP_COUNTER
- G_MAC_TX_PKT_OFFSET
- G_MAC_TX_RDPTR
- G_MAC_TX_RD_THRSH
- G_MAC_TX_RL_THRSH
- G_MAC_TX_WRPTR
- G_MAC_TX_WR_THRSH
- G_MAC_VLAN_TAG
- G_MAGICOFF
- G_MASK
- G_MASTEROFF
- G_MASTER_DLL_TAP_COUNT
- G_MASTER_DLL_TAP_COUNT_OFFSET
- G_MAX
- G_MAXBURST1
- G_MAXBURST2
- G_MAXTRAINALPHA
- G_MAXTRAINDATA
- G_MAX_REORDER_FRAGMENTS
- G_MAX_RETRANS
- G_MAX_RX_SIZE
- G_MC3_BANK_CYCLE
- G_MC3_CE_ADDR
- G_MC3_EXTENDED_MODE
- G_MC3_MODE
- G_MC3_PARITY_ERR
- G_MC3_UE_ADDR
- G_MC3_WIDTH
- G_MC4A_WIDTH
- G_MC4_BACK_DOOR_ADDR
- G_MC4_BANK_CYCLE
- G_MC4_CE_ADDR
- G_MC4_EXTENDED_MODE
- G_MC4_MODE
- G_MC4_UE_ADDR
- G_MC_ADDR_DRIVE
- G_MC_ADDR_SKEW
- G_MC_AGE_LIMIT
- G_MC_BANK0_MAP
- G_MC_BANK1_MAP
- G_MC_BANK2_MAP
- G_MC_BANK3_MAP
- G_MC_CHANNEL_SEL
- G_MC_CLK_RATIO
- G_MC_CLOCK_DRIVE
- G_MC_COMMAND
- G_MC_CS0_END
- G_MC_CS0_PAGE
- G_MC_CS0_START
- G_MC_CS1_END
- G_MC_CS1_PAGE
- G_MC_CS1_START
- G_MC_CS2_END
- G_MC_CS2_PAGE
- G_MC_CS2_START
- G_MC_CS3_END
- G_MC_CS3_PAGE
- G_MC_CS3_START
- G_MC_CS_MODE
- G_MC_DATA_DRIVE
- G_MC_DLL_DEFAULT
- G_MC_DQI_SKEW
- G_MC_DQO_SKEW
- G_MC_DRAM_TYPE
- G_MC_EMODE
- G_MC_MODE
- G_MC_QUEUE_SIZE
- G_MC_REF_RATE
- G_MC_WR_LIMIT
- G_MC_tCrD
- G_MC_tCwCr
- G_MC_tCwD
- G_MC_tFIFO
- G_MC_tRCD
- G_MC_tRCr
- G_MC_tRCw
- G_MC_tRFC
- G_MC_tRP
- G_MC_tRRD
- G_MDIO
- G_MDMA
- G_MI0_CLK_CNT
- G_MI0_CLK_DIV
- G_MI0_PHY_ADDR
- G_MI0_PHY_REG_ADDR
- G_MI1_CLK_DIV
- G_MI1_DATA
- G_MI1_OP
- G_MI1_PHY_ADDR
- G_MI1_REG_ADDR
- G_MI1_SOF
- G_MODE_MAX_RIX
- G_MODULATION_TIMER_SEPARATOR
- G_MODULE_ADDR
- G_MONITORED_PORT_NUM
- G_MONTH
- G_MSS_IDX
- G_NOUSER
- G_NO_HOSTNAME
- G_NUMFSTTRNSEQ
- G_NUMFSTTRNSEQRX
- G_NUM_LIP
- G_NUM_PKTS_DROPPED
- G_OPCODE
- G_OUT_OF_SYNC_COUNT
- G_PACING_FLAVOR
- G_PACKET3_SET_APPEND_CNT_SRC_SELECT
- G_PARLAT
- G_PARTIDOFF
- G_PASS_OPEN_TID
- G_PASS_OPEN_TOS
- G_PCIXINITPAT
- G_PCI_MODE_CLK
- G_PCI_MODE_PCIX_INITPAT
- G_PCLKRANGE
- G_PCMCIA_MODE
- G_PE
- G_PERSIST_TIMER_MAX
- G_PERSIST_TIMER_MIN
- G_PFnLKPIDX
- G_PFnMSKSIZE
- G_PKT_TYPE
- G_PMBCTRL
- G_PM_PAR_ERR
- G_PRECHARGE_CYCLE
- G_PROMOPOFF
- G_PSCR_MDI_XOVER_MODE
- G_PSSR_CABLE_LEN
- G_PSSR_SPEED
- G_QNUM
- G_QSPI
- G_RCV_BUFSIZ
- G_READ_DATA
- G_READ_TO_WRITE_DELAY
- G_RECEIVE_BUFFER_SIZE
- G_REFLECT
- G_REFRESH_CYCLE
- G_REFRESH_DIVISOR
- G_REGISTER_OFFSET
- G_REQMODE_CLEAR_FEAT
- G_REQMODE_GET_CONF
- G_REQMODE_GET_DESC
- G_REQMODE_GET_INTF
- G_REQMODE_GET_STATUS
- G_REQMODE_SET_CONF
- G_REQMODE_SET_FEAT
- G_REQMODE_SET_INTF
- G_RESPQ_CREDIT
- G_RESPQ_SIZE
- G_RETRANSMISSION_MAX
- G_RETRANSMIT_TIMER_MAX
- G_RETRANSMIT_TIMER_MIN
- G_RF_PARITY_ERR
- G_RNG1
- G_RNG2
- G_ROUTE_TABLE_INDEX
- G_RQ_MSI_VEC
- G_RSPD_INR_VEC
- G_RSPD_LEN
- G_RSPD_TXQ0_CR
- G_RSPD_TXQ1_CR
- G_RSPD_TXQ2_CR
- G_RSPQ
- G_RSS_MASK_LEN
- G_RSTMAX
- G_RTCAPB
- G_RTE_REQ_LUT_BASE
- G_RTE_REQ_LUT_IX
- G_RTE_WRITE_REQ_LUT_BASE
- G_RTE_WRITE_REQ_LUT_IX
- G_RTR_TYPE
- G_RTTVAR_INIT
- G_RXFIFOOVERFLOW
- G_RXFIFOPARITYERROR
- G_RXFIFOPAUSEHWM
- G_RXFIFOPAUSELWM
- G_RXMAXFRAMERSIZE
- G_RXMAXPKTSIZE
- G_RXPORT0DROPCNT
- G_RXPORT1DROPCNT
- G_RXPORT2DROPCNT
- G_RXPORT3DROPCNT
- G_RX_COALESCE
- G_RX_COALESCE_SIZE
- G_RX_CREDITS
- G_RX_DACK_MODE
- G_RX_NPORTS
- G_RX_PKT_OFFSET
- G_SACK
- G_SACK_ALGORITHM
- G_SAI1
- G_SAI2
- G_SAI3
- G_SAI4
- G_SCD_BERR_DCODE
- G_SCD_BERR_RID
- G_SCD_BERR_TID
- G_SCD_L2ECC_BAD_D
- G_SCD_L2ECC_BAD_T
- G_SCD_L2ECC_CORR_D
- G_SCD_L2ECC_CORR_T
- G_SCD_MEM_BUSERR
- G_SCD_MEM_ECC_BAD
- G_SCD_MEM_ECC_CORR
- G_SCD_TIMER_CNT
- G_SCD_TIMER_INIT
- G_SCD_TRACE_CFG_CUR_ADDR
- G_SCD_TREVT_ADDR_MATCH
- G_SCD_TREVT_COUNT
- G_SCD_TREVT_DATAID
- G_SCD_TREVT_REQID
- G_SCD_TREVT_RESPID
- G_SCD_TRSEQ_EVENT1
- G_SCD_TRSEQ_EVENT2
- G_SCD_TRSEQ_EVENT3
- G_SCD_TRSEQ_EVENT4
- G_SCD_TRSEQ_FUNCTION
- G_SCD_WDOG_RESET_TYPE
- G_SCHTOKEN0
- G_SCHTOKEN1
- G_SCHTOKEN2
- G_SCHTOKEN3
- G_SDMMC1
- G_SDMMC2
- G_SDMMC3
- G_SEARCH_RESPONSE_LATENCY
- G_SIZE
- G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT
- G_SLAVE_DELAY_LINE_TAP_COUNT
- G_SLAVE_DLL_DELTA
- G_SLEEPING
- G_SMB_ADDR
- G_SMB_AFMT
- G_SMB_DATA_IN
- G_SMB_DFMT
- G_SMB_REF
- G_SMB_SCL_IN
- G_SMB_TT
- G_SPC_CFG_SRC0
- G_SPC_CFG_SRC1
- G_SPC_CFG_SRC2
- G_SPC_CFG_SRC3
- G_SPC_CFG_SRC4
- G_SPC_CFG_SRC5
- G_SPC_CFG_SRC6
- G_SPC_CFG_SRC7
- G_SPDIF
- G_SPEEDO_BIT_MINUS1
- G_SPEEDO_BIT_MINUS1_R
- G_SPEEDO_BIT_MINUS2
- G_SPEEDO_BIT_MINUS2_R
- G_SPI1
- G_SPI2
- G_SPI3
- G_SPI4
- G_SPI4_COMMAND
- G_SPI5
- G_SPI6
- G_SRCHLAT
- G_SRC_MAC_SEL
- G_SRTT_GAIN
- G_ST
- G_START_OF_ROUTING_TABLE
- G_START_OF_SERVER_INDEX
- G_STGEN
- G_STGENRO
- G_SUPPORTED_RATES
- G_SYN_COOKIE_PARAMETER
- G_SYN_ISSUE_MODE
- G_SYN_MAX
- G_SYSCFG
- G_SYS_BIN
- G_SYS_BOOT_MODE
- G_SYS_CLKCOUNT
- G_SYS_CONFIG
- G_SYS_L2C_SIZE
- G_SYS_NUM_CPUS
- G_SYS_PART
- G_SYS_PLL_DIV
- G_SYS_REVISION
- G_SYS_SOC_TYPE
- G_SYS_WAFERID1_200
- G_SYS_WAFERID2_200
- G_SYS_WAFERID_300
- G_SYS_WID
- G_SYS_XPOS
- G_SYS_YPOS
- G_TABLELATENCYDELTA
- G_TABLEOFF
- G_TCAM_PART_CNT
- G_TCAM_PART_SIZE
- G_TCAM_PART_TYPE
- G_TCAM_SERVER_REGION_USAGE
- G_TCPOPT_MSS
- G_TCPOPT_SACK
- G_TCPOPT_SND_WSCALE
- G_TCPOPT_TSTAMP
- G_TCPOPT_WSCALE_OK
- G_TERM_TID
- G_TID
- G_TIM1
- G_TIM12
- G_TIM13
- G_TIM14
- G_TIM15
- G_TIM16
- G_TIM17
- G_TIM2
- G_TIM3
- G_TIM4
- G_TIM5
- G_TIM6
- G_TIM7
- G_TIM8
- G_TIMESTAMP
- G_TMPARTSIZE
- G_TMPSENS
- G_TMTYPE
- G_TOK_TRUNC
- G_TOS
- G_TPIPAR
- G_TPI_ADDRESS
- G_TPT_PAGE_SIZE
- G_TPT_PBL_ADDR
- G_TPT_PBL_SIZE
- G_TPT_PDID
- G_TPT_PERM
- G_TPT_PSTAG
- G_TPT_QPID
- G_TPT_STAG_KEY
- G_TPT_STAG_TYPE
- G_TP_ACCESS_LATENCY
- G_TP_PC_REV
- G_TP_VERSION_MAJOR
- G_TP_VERSION_MICRO
- G_TP_VERSION_MINOR
- G_TRANSACTION_TIMER
- G_TXDROPCNTCH0RCVD
- G_TXFIFOPARITYERROR
- G_TXF_READ_THRESHOLD
- G_TXF_WRITE_THRESHOLD
- G_TXIPG
- G_TXPKT_INTF
- G_TXPKT_OPCODE
- G_TXPKT_VLAN
- G_TXPORT0DROPCNT
- G_TXPORT1DROPCNT
- G_TXPORT2DROPCNT
- G_TXPORT3DROPCNT
- G_TXSPI4SOPCNT
- G_TX_ACK_PAGES
- G_TX_CPU_IDX
- G_TX_MSS
- G_TX_NPORTS
- G_TX_PORT
- G_TX_QOS
- G_TX_SNDBUF
- G_TX_ULP_MODE
- G_TX_ULP_SUBMODE
- G_TYPECFG_TYPE0
- G_TYPECFG_TYPE1
- G_TYPECFG_TYPE2
- G_TYPECFG_TYPE3
- G_TZC1
- G_TZC2
- G_TZPC
- G_UART4
- G_UART5
- G_UART7
- G_UART8
- G_ULP_MODE
- G_UNCORRECTABLE_ERROR_COUNT
- G_UNKNOWN_QOP
- G_USART1
- G_USART2
- G_USART3
- G_USART6
- G_USBH
- G_USBO
- G_USBPHY
- G_VALIDATE_FAILED
- G_VAR_GAIN
- G_VAR_MULT
- G_VDSOFF
- G_VERSIONOFF
- G_VLAN_PRI
- G_VPD_ADDR
- G_VREF
- G_WIDTH
- G_WINDOWPROBE_MAX
- G_WINDOW_SCALE
- G_WND_SCALE
- G_WRITE_BURST_SIZE
- G_WRITE_DATA
- G_WRITE_RECOVERY_DELAY
- G_WRITE_TO_READ_DELAY
- G_WRONG_MECH
- G_WRONG_SIZE
- G_WRONG_TOKID
- G_WR_BCNTLFLT
- G_WR_LEN
- G_WR_OP
- G_WR_SGE_CREDITS
- G_WR_SGLSFLT
- G_WR_TID
- G__SQ_CONSTANT_TYPE
- G__SQ_VTX_CONSTANT_TYPE
- Gamma0
- Gamma1
- GatekeeperConfirm
- GatekeeperRequest
- GbVdroopTable_t
- Gbbase_Colkey
- Gbbase_Glalpha
- Gbps_to_icc
- GcCacWeight_Data
- Gc_Cac_Weight_Data
- Gdrctrl_Colkeym
- GenCtrl
- GenIO4
- GenIO8
- Generic
- Generic800
- Generic802
- GetAMsdu
- GetAckpolicy
- GetAcl
- GetAddr1Ptr
- GetAddr2Ptr
- GetAddr3Ptr
- GetAddr4Ptr
- GetAid
- GetAttributes
- GetBF
- GetBusInfo
- GetByte
- GetDeltaSwingTable_8723B
- GetEEPROMSize8723B
- GetEngineCapabilities
- GetEngineCompletePtr
- GetEngineControl
- GetFrDs
- GetFractionValueFromString
- GetFragNum
- GetFrameSubType
- GetFrameType
- GetHalDefVar
- GetHalDefVar8723B
- GetHalDefVar8723BSDIO
- GetHalODMVar
- GetHalfNmodeSupportByAPs819xUsb
- GetHexValueFromString
- GetHubDescriptor
- GetHubStatus
- GetHwReg
- GetHwReg8723B
- GetHwReg8723BS
- GetIndexIntoMasterCmdTable
- GetIndexIntoMasterDataTable
- GetIndexIntoMasterTable
- GetInterruptDefStatus
- GetIoUnitPage2
- GetIocFacts
- GetLCDPtrIndex
- GetLCDPtrIndexBIOS
- GetLCDStructPtr661
- GetLCDStructPtr661_2
- GetLCDromptr
- GetLanConfigPages
- GetLineFromBuffer
- GetLineNumber
- GetMData
- GetMFrag
- GetMac
- GetNmodeSupportBySecCfg8192
- GetOEMLCDPtr
- GetOEMTVPtr
- GetOEMTVPtr661
- GetOEMTVPtr661_2_GEN
- GetOEMTVPtr661_2_NEW
- GetOEMTVPtr661_2_OLD
- GetOrder
- GetOrderBit
- GetPhyRxPktCounts
- GetPortErrorCount
- GetPortFacts
- GetPortStatus
- GetPriority
- GetPrivacy
- GetPwrMgt
- GetRAMDACromptr
- GetReal
- GetReg
- GetRetry
- GetScaledFraction
- GetSequence
- GetSignalStrength
- GetTTState
- GetTVPtrIndex
- GetTVromptr
- GetTid
- GetToDs
- GetTs
- GetTupleCache
- GetU1ByteIntegerFromStringInDecimal
- GetWord
- GfxclkSrc_e
- Gi_SRC
- GlobalReset
- GotHeader
- GotName
- GotSymlink
- Gpio0
- Gpio1
- GpioIntPolarity_e
- Gplut_Lutadr
- Gplut_Lutdata
- GraphEngReg
- GraphicsDPMTuning_VEGAM
- GraphicsDRAMx16
- GreaterThan
- Greaterthan
- Greaterthanbit
- Group
- GroupDual
- GroupInterleave
- GroupMask
- Gsadr_Srcstride
- Gsadr_Xstart
- Gsadr_Ystart
- Gscadr_Gbase_Adr
- Gsctrl_Height
- Gsctrl_Width
- Gsmartmini
[..]